ARM: dts: imx50: imx50-esdhc use imx53-esdhc

According to the reference manuals, both imx50/imx53 SOC seem to share
the same eSDHC controller, especially the section on "Multi-block Read"
mentioned in commit 361b8482026c ("mmc: sdhci-esdhc-imx: fix multiblock
reads on i.MX53") is identical for both SOC.
Hence, let imx50 use imx53-esdhc.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index ceae909e2201f729e8ed64a2f9baaa3103d3d968..2a98afcd8a4e302834596ab40655646c097b3ccc 100644 (file)
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -109,7 +109,7 @@
                                ranges;
 
                                esdhc1: esdhc@50004000 {
-                                       compatible = "fsl,imx50-esdhc";
+                                       compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
                                        reg = <0x50004000 0x4000>;
                                        interrupts = <1>;
                                        clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
@@ -121,7 +121,7 @@
                                };
 
                                esdhc2: esdhc@50008000 {
-                                       compatible = "fsl,imx50-esdhc";
+                                       compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
                                        reg = <0x50008000 0x4000>;
                                        interrupts = <2>;
                                        clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
@@ -170,7 +170,7 @@
                                };
 
                                esdhc3: esdhc@50020000 {
-                                       compatible = "fsl,imx50-esdhc";
+                                       compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
                                        reg = <0x50020000 0x4000>;
                                        interrupts = <3>;
                                        clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
@@ -182,7 +182,7 @@
                                };
 
                                esdhc4: esdhc@50024000 {
-                                       compatible = "fsl,imx50-esdhc";
+                                       compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
                                        reg = <0x50024000 0x4000>;
                                        interrupts = <4>;
                                        clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,