From: Fabio Estevam Date: Tue, 19 Aug 2014 18:21:12 +0000 (-0300) Subject: ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=0783a56087e9ecfae2f01f9662ff52081c5b5e25;p=openwrt%2Fstaging%2Fblogic.git ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index ba3af22c1266..11908e8bf9ab 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -376,6 +376,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) /* Audio-related clocks configuration */ clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); + /* set PLL5 video as lcdif pix parent clock */ + clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL], + clks[IMX6SL_CLK_PLL5_VIDEO_DIV]); + + clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], + clks[IMX6SL_CLK_PLL2_PFD2]); + /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); }