From: Mika Kahola <mika.kahola@intel.com>
Date: Fri, 12 Jun 2015 07:11:32 +0000 (+0300)
Subject: drm/i915: Limit CHV max cdclk
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=0904deaf4e6bc1d854ed48255bdb170c7906c8fb;p=openwrt%2Fstaging%2Fblogic.git

drm/i915: Limit CHV max cdclk

Limit CHV maximum cdclk to 320MHz.

v2: Rebase to the latest
v3: Clean up of if-else tree

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a806f1598a46..3f4891782cf6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5271,6 +5271,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
 			dev_priv->max_cdclk_freq = 540000;
 		else
 			dev_priv->max_cdclk_freq = 675000;
+	} else if (IS_CHERRYVIEW(dev)) {
+		dev_priv->max_cdclk_freq = 320000;
 	} else if (IS_VALLEYVIEW(dev)) {
 		dev_priv->max_cdclk_freq = 400000;
 	} else {