From: Birger Koblitz Date: Wed, 19 Jan 2022 17:14:02 +0000 (+0100) Subject: realtek: Add RTL931X sub-target X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=0b8dfe085180b58b81d2657c76b080168e3bc8df;p=openwrt%2Fstaging%2Flinusw.git realtek: Add RTL931X sub-target We add the RTL931X sub-target with kernel configuration for a dual core MIPS InterAptive CPU. Signed-off-by: Sebastian Gottschall Signed-off-by: Birger Koblitz --- diff --git a/target/linux/realtek/Makefile b/target/linux/realtek/Makefile index 26b7d0afaa..704242a000 100644 --- a/target/linux/realtek/Makefile +++ b/target/linux/realtek/Makefile @@ -7,7 +7,7 @@ BOARD:=realtek BOARDNAME:=Realtek MIPS DEVICE_TYPE:=basic FEATURES:=ramdisk squashfs -SUBTARGETS:=rtl838x rtl839x rtl930x +SUBTARGETS:=rtl838x rtl839x rtl930x rtl931x KERNEL_PATCHVER:=5.10 diff --git a/target/linux/realtek/dts-5.10/rtl931x.dtsi b/target/linux/realtek/dts-5.10/rtl931x.dtsi new file mode 100644 index 0000000000..8dd4cfdc92 --- /dev/null +++ b/target/linux/realtek/dts-5.10/rtl931x.dtsi @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "realtek,rtl838x-soc"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + frequency = <1000000000>; + + cpu@0 { + compatible = "mti,interaptive"; + reg = <0>; + }; + + cpu@1 { + compatible = "mti,interaptive"; + reg = <1>; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,38400"; + }; + + lx_clk: lx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + cpuclock: cpuclock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + + /* FIXME: there should be way to detect this */ + clock-frequency = <1000000000>; + }; + + cpuintc: cpuintc { + compatible = "mti,cpu-interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + gic: interrupt-controller@1ddc0000 { + compatible = "mti,gic"; + reg = <0x1ddc0000 0x20000>; + + interrupt-controller; + #interrupt-cells = <3>; + + /* + * Declare the interrupt-parent even though the mti,gic + * binding doesn't require it, such that the kernel can + * figure out that cpu_intc is the root interrupt + * controller & should be probed first. + */ + interrupt-parent = <&cpuintc>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&cpuclock>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000000 0x10000>; + + spi0: spi@1200 { + status = "okay"; + + compatible = "realtek,rtl8380-spi"; + reg = <0x1200 0x100>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + watchdog0: watchdog@3260 { + compatible = "realtek,rtl9310-wdt"; + reg = <0x3260 0xc>; + + realtek,reset-mode = "soc"; + + clocks = <&lx_clk>; + timeout-sec = <30>; + + interrupt-parent = <&gic>; + interrupt-names = "phase1", "phase2"; + interrupts = , ; + }; + + gpio0: gpio-controller@3300 { + compatible = "realtek,rtl9310-gpio", "realtek,otto-gpio"; + reg = <0x3300 0x1c>; + + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + uart0: uart@2000 { + compatible = "ns16550a"; + reg = <0x2000 0x100>; + + clock-frequency = <200000000>; + + interrupt-parent = <&gic>; + #interrupt-cells = <3>; + interrupts = ; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + }; + + uart1: uart@2100 { + compatible = "ns16550a"; + reg = <0x2100 0x100>; + + clock-frequency = <200000000>; + + interrupt-parent = <&gic>; + #interrupt-cells = <3>; + interrupts = ; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + + status = "disabled"; + }; + }; + + + ethernet0: ethernet@1b00a300 { + status = "okay"; + compatible = "realtek,rtl838x-eth"; + reg = <0x1b00a300 0x100>; + interrupt-parent = <&gic>; + #interrupt-cells = <3>; + interrupts = ; + phy-mode = "internal"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + switch0: switch@1b000000 { + compatible = "realtek,rtl83xx-switch"; + status = "okay"; + + interrupt-parent = <&gic>; + #interrupt-cells = <3>; + interrupts = ; + }; +}; diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c index 0a1972aaf6..21f00096e5 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c @@ -45,6 +45,7 @@ #define RTL838X_STAT_PRVTE_DROP_COUNTERS (0x6A00) #define RTL839X_STAT_PRVTE_DROP_COUNTERS (0x3E00) #define RTL930X_STAT_PRVTE_DROP_COUNTERS (0xB5B8) +#define RTL931X_STAT_PRVTE_DROP_COUNTERS (0xd800) int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port); void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); @@ -106,6 +107,25 @@ const char *rtl930x_drop_cntr[] = { "STACK_NONUC_BLOCKING_PMSK", "STACK_PORT_NOT_FOUND", "ACL_LOOPBACK_DROP", "IP6_ROUTING_EXT_HEADER" }; +const char *rtl931x_drop_cntr[] = { + "ALE_RX_GOOD_PKTS", "RX_MAX_FRAME_SIZE", "MAC_RX_DROP", "OPENFLOW_IP_MPLS_TTL", "OPENFLOW_TBL_MISS", + "IGR_BW", "SPECIAL_CONGEST", "EGR_QUEUE", "RESERVED", "EGR_LINK_STATUS", "STACK_UCAST_NONUCAST_TTL", // 10 + "STACK_NONUC_BLOCKING_PMSK", "L2_CRC", "SRC_PORT_FILTER", "PARSER_PACKET_TOO_LONG", "PARSER_MALFORM_PACKET", + "MPLS_OVER_2_LBL", "EACL_METER", "IACL_METER", "PROTO_STORM", "INVALID_CAPWAP_HEADER", // 20 + "MAC_IP_SUBNET_BASED_VLAN", "OAM_PARSER", "UC_MC_RPF", "IP_MAC_BINDING_MATCH_MISMATCH", "SA_BLOCK", + "TUNNEL_IP_ADDRESS_CHECK", "EACL_DROP", "IACL_DROP", "ATTACK_PREVENT", "SYSTEM_PORT_LIMIT_LEARN", // 30, + "OAMPDU", "CCM_RX", "CFM_UNKNOWN_TYPE", "LBM_LBR_LTM_LTR", "Y_1731", "VLAN_LIMIT_LEARN", + "VLAN_ACCEPT_FRAME_TYPE", "CFI_1", "STATIC_DYNAMIC_PORT_MOVING", "PORT_MOVE_FORBID", // 40 + "L3_CRC", "BPDU_PTP_LLDP_EAPOL_RMA", "MSTP_SRC_DROP_DISABLED_BLOCKING", "INVALID_SA", "NEW_SA", + "VLAN_IGR_FILTER", "IGR_VLAN_CONVERT", "GRATUITOUS_ARP", "MSTP_SRC_DROP", "L2_HASH_FULL", // 50 + "MPLS_UNKNOWN_LBL", "L3_IPUC_NON_IP", "TTL", "MTU", "ICMP_REDIRECT", "STORM_CONTROL", "L3_DIP_DMAC_MISMATCH", + "IP4_IP_OPTION", "IP6_HBH_EXT_HEADER", "IP4_IP6_HEADER_ERROR", // 60 + "ROUTING_IP_ADDR_CHECK", "ROUTING_EXCEPTION", "DA_BLOCK", "OAM_MUX", "PORT_ISOLATION", "VLAN_EGR_FILTER", + "MIRROR_ISOLATE", "MSTP_DESTINATION_DROP", "L2_MC_BRIDGE", "IP_UC_MC_ROUTING_LOOK_UP_MISS", // 70 + "L2_UC", "L2_MC", "IP4_MC", "IP6_MC", "L3_UC_MC_ROUTE", "UNKNOWN_L2_UC_FLPM", "BC_FLPM", + "VLAN_PRO_UNKNOWN_L2_MC_FLPM", "VLAN_PRO_UNKNOWN_IP4_MC_FLPM", "VLAN_PROFILE_UNKNOWN_IP6_MC_FLPM" // 80, +}; + static ssize_t rtl838x_common_read(char __user *buffer, size_t count, loff_t *ppos, unsigned int value) { @@ -217,6 +237,11 @@ static ssize_t drop_counter_read(struct file *filp, char __user *buffer, size_t offset = RTL930X_STAT_PRVTE_DROP_COUNTERS; num = 85; break; + case RTL9310_FAMILY_ID: + d = rtl931x_drop_cntr; + offset = RTL931X_STAT_PRVTE_DROP_COUNTERS; + num = 81; + break; } buf = kmalloc(30 * num, GFP_KERNEL); diff --git a/target/linux/realtek/image/rtl931x.mk b/target/linux/realtek/image/rtl931x.mk new file mode 100644 index 0000000000..a4e40e534e --- /dev/null +++ b/target/linux/realtek/image/rtl931x.mk @@ -0,0 +1 @@ +# SPDX-License-Identifier: GPL-2.0-only diff --git a/target/linux/realtek/patches-5.10/312-rt9313-support.patch b/target/linux/realtek/patches-5.10/312-rt9313-support.patch new file mode 100644 index 0000000000..37a61106d2 --- /dev/null +++ b/target/linux/realtek/patches-5.10/312-rt9313-support.patch @@ -0,0 +1,74 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -307,14 +307,24 @@ endif + + KBUILD_AFLAGS += $(cflags-y) + KBUILD_CFLAGS += $(cflags-y) ++ifdef CONFIG_931X ++KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y) ++bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y) \ ++ VMLINUX_ENTRY_ADDRESS=$(entry-y) \ ++ PLATFORM="$(platform-y)" \ ++ ITS_INPUTS="$(its-y)" ++else + KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y) -DLINKER_LOAD_ADDRESS=$(load-ld) +-KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0) +- + bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y) \ + LINKER_LOAD_ADDRESS=$(load-ld) \ + VMLINUX_ENTRY_ADDRESS=$(entry-y) \ + PLATFORM="$(platform-y)" \ + ITS_INPUTS="$(its-y)" ++endif ++KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0) ++ ++ ++ + ifdef CONFIG_32BIT + bootvars-y += ADDR_BITS=32 + endif +--- a/arch/mips/kernel/head.S ++++ b/arch/mips/kernel/head.S +@@ -60,12 +60,14 @@ + .endm + + #ifndef CONFIG_NO_EXCEPT_FILL ++#ifndef CONFIG_RTL931X + /* + * Reserved space for exception handlers. + * Necessary for machines which link their kernels at KSEG0. + */ + .fill 0x400 + #endif ++#endif + + EXPORT(_stext) + +@@ -79,11 +81,13 @@ FEXPORT(__kernel_entry) + j kernel_entry + #endif /* CONFIG_BOOT_RAW */ + ++#ifndef CONFIG_RTL931X + #ifdef CONFIG_IMAGE_CMDLINE_HACK + .ascii "CMDLINE:" + EXPORT(__image_cmdline) + .fill 0x400 + #endif /* CONFIG_IMAGE_CMDLINE_HACK */ ++#endif + + __REF + +--- a/arch/mips/kernel/vmlinux.lds.S ++++ b/arch/mips/kernel/vmlinux.lds.S +@@ -55,7 +55,11 @@ SECTIONS + /* . = 0xa800000000300000; */ + . = 0xffffffff80300000; + #endif ++#ifdef CONFIG_RTL931X ++ . = 0x80220000; ++#else + . = LINKER_LOAD_ADDRESS; ++#endif + /* read-only */ + _text = .; /* Text and read-only data */ + .text : { diff --git a/target/linux/realtek/rtl931x/config-5.10 b/target/linux/realtek/rtl931x/config-5.10 new file mode 100644 index 0000000000..ac60938ddc --- /dev/null +++ b/target/linux/realtek/rtl931x/config-5.10 @@ -0,0 +1,223 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_CEVT_R4K=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_BOSTON=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_DIEI=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_MIPS_MT=y +CONFIG_MIPS_MT_FPAFF=y +CONFIG_MIPS_MT_SMP=y +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_NR_CPU_NR_MAP=4 +CONFIG_HIGHMEM=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CSRC_R4K=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_FIXED_PHY=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_REALTEK_OTTO=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_RTL8231=y +CONFIG_GRO_CELLS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_HWMON=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_RTL9300=y +CONFIG_I2C_RTL9300=y +CONFIG_I2C_SMBUS=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_JFFS2_ZLIB=y +CONFIG_LEDS_GPIO=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LIBFDT=y +CONFIG_LLD_VERSION=0 +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_I2C=y +CONFIG_MDIO_SMBUS=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_CBPF_JIT=y +CONFIG_MIPS_CLOCK_VSYSCALL=y +# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CMDLINE_FROM_DTB=y +# CONFIG_MIPS_ELF_APPENDED_DTB is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_LD_CAN_LINK_VDSO=y +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MIPS_SPRAM=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_BRNIMAGE_FW=y +CONFIG_MTD_SPLIT_EVA_FW=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_TPLINK_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_RTL83XX=y +CONFIG_NET_DSA_TAG_RTL83XX=y +CONFIG_NET_DSA_TAG_TRAILER=y +CONFIG_NET_RTL838X=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NVMEM=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_RATIONAL=y +# CONFIG_REALTEK_PHY is not set +CONFIG_REALTEK_SOC_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RTL838X=y +# CONFIG_RTL9300_TIMER is not set +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_LM75=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SFP=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SRCU=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TINY_SRCU=y +# CONFIG_USE_GENERIC_EARLY_PRINTK_8250 is not set +CONFIG_USE_OF=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_FORCE_MAX_ZONEORDER=13 +# CONFIG_MIPS_VPE_LOADER is not set +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_SPI_RTL838X=y +CONFIG_MIPS_MT_SMP=y +CONFIG_MIPS_CPC=y +CONFIG_MIPS_CPS=y +CONFIG_MIPS_PM=y +# CONFIG_MIPS_CMP is not set +CONFIG_MIPS_CPS_CPUIDLE=y +# CONFIG_MIPS_CPS_NS16550_BOOL is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_RTL83XX=y +# CONFIG_RTL838X is not set +# CONFIG_RTL839X is not set +CONFIG_RTL930X=y +CONFIG_RTL931X=y +CONFIG_REALTEK_OTTO_WDT=y diff --git a/target/linux/realtek/rtl931x/target.mk b/target/linux/realtek/rtl931x/target.mk new file mode 100644 index 0000000000..39892e5484 --- /dev/null +++ b/target/linux/realtek/rtl931x/target.mk @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only +ARCH:=mips +SUBTARGET:=rtl931x +CPU_TYPE:=24kc +BOARD:=realtek +BOARDNAME:=Realtek MIPS RTL931X + +KERNEL_PATCHVER:=5.10 + +define Target/Description + Build firmware images for Realtek RTL931x based boards. +endef