From: David Brownell Date: Sat, 21 Jul 2007 18:43:35 +0000 (-0700) Subject: USB: more pxa2xx_udc dead code removal X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=1060bce7b74c8914999a067803ec659949ff682e;p=openwrt%2Fstaging%2Fblogic.git USB: more pxa2xx_udc dead code removal Remove some more dead code from the pxa2xx_udc driver: support for a no-longer-undocumented hardware "test mode". Newer chips made this the default, evidently as the best workaround for deep silicon bugs. The interest was that this seemed to be the only way to kick in the (documented!) double buffering capability. Signed-off-by: David Brownell Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa2xx_udc.c index 63b9521c1322..72b4ebbf132d 100644 --- a/drivers/usb/gadget/pxa2xx_udc.c +++ b/drivers/usb/gadget/pxa2xx_udc.c @@ -93,8 +93,6 @@ static const char driver_name [] = "pxa2xx_udc"; static const char ep0name [] = "ep0"; -// #define DISABLE_TEST_MODE - #ifdef CONFIG_ARCH_IXP4XX /* cpu-specific register addresses are compiled in to this code */ @@ -113,17 +111,6 @@ static const char ep0name [] = "ep0"; #define SIZE_STR "" #endif -#ifdef DISABLE_TEST_MODE -/* (mode == 0) == no undocumented chip tweaks - * (mode & 1) == double buffer bulk IN - * (mode & 2) == double buffer bulk OUT - * ... so mode = 3 (or 7, 15, etc) does it for both - */ -static ushort fifo_mode = 0; -module_param(fifo_mode, ushort, 0); -MODULE_PARM_DESC (fifo_mode, "pxa2xx udc fifo mode"); -#endif - /* --------------------------------------------------------------------------- * endpoint related parts of the api to the usb controller hardware, * used by gadget driver; and the inner talker-to-hardware core. @@ -1252,23 +1239,6 @@ static void udc_enable (struct pxa2xx_udc *dev) UDC_RES2 = 0x00; } -#ifdef DISABLE_TEST_MODE - /* "test mode" seems to have become the default in later chip - * revs, preventing double buffering (and invalidating docs). - * this EXPERIMENT enables it for bulk endpoints by tweaking - * undefined/reserved register bits (that other drivers clear). - * Belcarra code comments noted this usage. - */ - if (fifo_mode & 1) { /* IN endpoints */ - UDC_RES1 |= USIR0_IR1|USIR0_IR6; - UDC_RES2 |= USIR1_IR11; - } - if (fifo_mode & 2) { /* OUT endpoints */ - UDC_RES1 |= USIR0_IR2|USIR0_IR7; - UDC_RES2 |= USIR1_IR12; - } -#endif - /* enable suspend/resume and reset irqs */ udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);