From: Madhav Chauhan Date: Tue, 10 Jul 2018 09:40:05 +0000 (+0530) Subject: drm/i915/icl: Define T_INIT_MASTER registers X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=146cdf3fad9c4b4653a4dfc6c79619c62ab27c15;p=openwrt%2Fstaging%2Fblogic.git drm/i915/icl: Define T_INIT_MASTER registers This patch defines DSI_T_INIT_MASTER register for DSI ports 0/1 which will be used in dphy programming. Signed-off-by: Madhav Chauhan Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/1531215614-6828-5-git-send-email-madhav.chauhan@intel.com --- diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 09bc8e730ee1..c80e56959e21 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10231,6 +10231,12 @@ enum skl_power_gate { #define PREPARE_COUNT_SHIFT 0 #define PREPARE_COUNT_MASK (0x3f << 0) +#define _ICL_DSI_T_INIT_MASTER_0 0x6b088 +#define _ICL_DSI_T_INIT_MASTER_1 0x6b888 +#define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \ + _ICL_DSI_T_INIT_MASTER_0,\ + _ICL_DSI_T_INIT_MASTER_1) + /* bits 31:0 */ #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)