From: Yangbo Lu Date: Fri, 22 Sep 2017 07:57:12 +0000 (+0800) Subject: layerscape: drop linux 4.4 support X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=19951bbf57da87093f7bde25bad41571fbdaf4d9;p=openwrt%2Fstaging%2Fwigyori.git layerscape: drop linux 4.4 support This patch is to drop linux 4.4 for layerscape. Signed-off-by: Yangbo Lu --- diff --git a/target/linux/layerscape/armv8_32b/config-default b/target/linux/layerscape/armv8_32b/config-default deleted file mode 100644 index 7aa0dd5c53..0000000000 --- a/target/linux/layerscape/armv8_32b/config-default +++ /dev/null @@ -1,152 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_ARCH_AXXIA is not set -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_MULTI_CPU_AUTO is not set -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_MXC=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_REQUIRE_GPIOLIB=y -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARM=y -# CONFIG_ARM_CPU_SUSPEND is not set -CONFIG_ARM_ERRATA_754322=y -CONFIG_ARM_ERRATA_764369=y -CONFIG_ARM_ERRATA_775420=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_LPAE=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_PMU=y -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -CONFIG_ARM_VIRT_EXT=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_CACHE_L2X0=y -CONFIG_CLKSRC_IMX_GPT=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_PABRT_V7=y -# CONFIG_CPU_THERMAL is not set -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_DEBUG_IMX_UART_PORT=1 -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -# CONFIG_DEBUG_UART_8250 is not set -# CONFIG_DEBUG_USER is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -CONFIG_EXTCON=y -CONFIG_FEC=y -# CONFIG_FSL_QMAN_FQ_LOOKUP is not set -# CONFIG_FTRACE_SYSCALLS is not set -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GPIO_MXC=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IMX_SRC=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SMP=y -CONFIG_HZ_FIXED=0 -# CONFIG_IMX_WEIM is not set -CONFIG_MICREL_PHY=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGHT_HAVE_PCI=y -# CONFIG_MMC_SDHCI_ESDHC_IMX is not set -# CONFIG_MMC_MXC is not set -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MULTI_IRQ_HANDLER=y -CONFIG_NEON=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_OLD_SIGACTION=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PAGE_OFFSET=0x80000000 -# CONFIG_PATA_IMX is not set -CONFIG_PERF_EVENTS=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PL310_ERRATA_588369=y -CONFIG_PL310_ERRATA_727915=y -# CONFIG_PL310_ERRATA_753970 is not set -CONFIG_PL310_ERRATA_769419=y -CONFIG_PM_OPP=y -CONFIG_PPS=y -# CONFIG_PROBE_EVENTS is not set -CONFIG_PTP_1588_CLOCK=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_IMXDI is not set -# CONFIG_RTC_DRV_MXC is not set -# CONFIG_SERIAL_IMX is not set -CONFIG_SMP_ON_UP=y -CONFIG_SOC_BUS=y -# CONFIG_SOC_IMX50 is not set -# CONFIG_SOC_IMX51 is not set -# CONFIG_SOC_IMX53 is not set -# CONFIG_SOC_IMX6Q is not set -# CONFIG_SOC_IMX6SL is not set -# CONFIG_SOC_IMX6SX is not set -# CONFIG_SOC_IMX6UL is not set -# CONFIG_SOC_IMX7D is not set -# CONFIG_SOC_LS1021A is not set -# CONFIG_SOC_VF610 is not set -# CONFIG_SPI_IMX is not set -CONFIG_SRAM=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -# CONFIG_THUMB2_KERNEL is not set -CONFIG_TRACING_EVENTS_GPIO=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -# CONFIG_USB_IMX21_HCD is not set -CONFIG_USE_OF=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/layerscape/armv8_64b/config-default b/target/linux/layerscape/armv8_64b/config-default deleted file mode 100644 index 960b0770e4..0000000000 --- a/target/linux/layerscape/armv8_64b/config-default +++ /dev/null @@ -1,183 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ACPI=y -CONFIG_ACPI_CCA_REQUIRED=y -# CONFIG_ACPI_CONTAINER is not set -# CONFIG_ACPI_CUSTOM_DSDT is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_DEBUGGER is not set -# CONFIG_ACPI_DOCK is not set -# CONFIG_ACPI_EC_DEBUGFS is not set -CONFIG_ACPI_FAN=y -CONFIG_ACPI_GENERIC_GSI=y -# CONFIG_ACPI_PCI_SLOT is not set -CONFIG_ACPI_PROCESSOR=y -CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y -CONFIG_ACPI_THERMAL=y -# CONFIG_ARCH_BCM_IPROC is not set -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -# CONFIG_ARCH_EXYNOS7 is not set -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -# CONFIG_ARCH_SEATTLE is not set -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -# CONFIG_ARCH_SPRD is not set -# CONFIG_ARCH_STRATIX10 is not set -# CONFIG_ARCH_THUNDER is not set -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_FRAME_POINTERS=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -# CONFIG_ARCH_XGENE is not set -# CONFIG_ARCH_ZYNQMP is not set -CONFIG_ARM64=y -# CONFIG_ARM64_16K_PAGES is not set -CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_64K_PAGES is not set -# CONFIG_ARM64_CRYPTO is not set -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_845719=y -CONFIG_ARM64_HW_AFDBM=y -# CONFIG_ARM64_LSE_ATOMICS is not set -CONFIG_ARM64_PAN=y -# CONFIG_ARM64_PTDUMP is not set -# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARM64_VA_BITS_48 is not set -# CONFIG_ARMV8_DEPRECATED is not set -CONFIG_ARM_AMBA=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -# CONFIG_ARM_PL172_MPMC is not set -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_SP805_WATCHDOG is not set -CONFIG_ATOMIC64_SELFTEST=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLOCK_COMPAT=y -CONFIG_BOUNCE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_BUILD_BIN2C=y -# CONFIG_CAVIUM_ERRATUM_22375 is not set -# CONFIG_CAVIUM_ERRATUM_23154 is not set -CONFIG_CLKSRC_ACPI=y -CONFIG_CLK_SP810=y -CONFIG_CLK_VEXPRESS_OSC=y -CONFIG_CMDLINE="console=ttyAMA0" -CONFIG_COMMON_CLK_VERSATILE=y -CONFIG_COMMON_CLK_XGENE=y -CONFIG_COMPAT=y -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_COMPAT_NETLINK_MESSAGES=y -CONFIG_COMPAT_OLD_SIGACTION=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CUSE=y -CONFIG_DEBUG_INFO=y -CONFIG_DEFAULT_IOSCHED="noop" -CONFIG_DEFAULT_NOOP=y -CONFIG_DMI=y -CONFIG_DMIID=y -# CONFIG_DMI_SYSFS is not set -CONFIG_EFI=y -# CONFIG_EFIVAR_FS is not set -CONFIG_EFI_ARMSTUB=y -CONFIG_EFI_ESRT=y -CONFIG_EFI_PARAMS_FROM_FDT=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_STUB=y -# CONFIG_EFI_VARS is not set -CONFIG_FSL_MC_BUS=y -CONFIG_FSL_QMAN_FQ_LOOKUP=y -CONFIG_FS_MBCACHE=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_ACPI=y -# CONFIG_GPIO_AMDPT is not set -# CONFIG_GPIO_XGENE is not set -CONFIG_GRACE_PERIOD=y -CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y -CONFIG_HAVE_ARCH_KASAN=y -CONFIG_HAVE_CMPXCHG_DOUBLE=y -CONFIG_HAVE_CMPXCHG_LOCAL=y -CONFIG_HAVE_DEBUG_BUGVERBOSE=y -CONFIG_HAVE_MEMORY_PRESENT=y -CONFIG_HAVE_PATA_PLATFORM=y -# CONFIG_HPET is not set -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_VIRTIO=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_RARP is not set -CONFIG_JBD2=y -# CONFIG_LIQUIDIO is not set -CONFIG_LOCKD=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_MFD_CORE=y -CONFIG_MFD_VEXPRESS_SYSREG=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NFS_FS=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NO_HZ=y -CONFIG_PCI_BUS_ADDR_T_64BIT=y -# CONFIG_PCI_HISI is not set -CONFIG_PCI_LABEL=y -# CONFIG_PHY_XGENE is not set -# CONFIG_PMIC_OPREGION is not set -CONFIG_PNP=y -CONFIG_PNPACPI=y -CONFIG_PNP_DEBUG_MESSAGES=y -CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_PROFILING=y -# CONFIG_POWER_RESET_VEXPRESS is not set -CONFIG_ROOT_NFS=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_PROC_FS is not set -CONFIG_SERIAL_8250_PNP=y -# CONFIG_SERIAL_AMBA_PL010 is not set -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SMC91X=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SUNRPC=y -# CONFIG_SWAP is not set -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSVIPC_COMPAT=y -# CONFIG_THUNDER_NIC_BGX is not set -# CONFIG_THUNDER_NIC_PF is not set -# CONFIG_THUNDER_NIC_VF is not set -CONFIG_UCS2_STRING=y -CONFIG_VEXPRESS_CONFIG=y -CONFIG_VEXPRESS_SYSCFG=y -CONFIG_VFAT_FS=y -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_VIRTIO=y -CONFIG_VIRTIO_BLK=y -# CONFIG_VIRTIO_CONSOLE is not set -CONFIG_VIRTIO_MMIO=y -# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set -CONFIG_VIRTIO_NET=y diff --git a/target/linux/layerscape/config-4.4 b/target/linux/layerscape/config-4.4 deleted file mode 100644 index 6894af0df5..0000000000 --- a/target/linux/layerscape/config-4.4 +++ /dev/null @@ -1,310 +0,0 @@ -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_ARCH_LAYERSCAPE=y -CONFIG_ARCH_PHYS_ADDR_T_64BIT=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -# CONFIG_CAVIUM_ERRATUM_27456 is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLKSRC_OF=y -CONFIG_CLKSRC_PROBE=y -CONFIG_CLK_QORIQ=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DTC=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EXT4_FS=y -CONFIG_FAT_FS=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FMAN_ARM=y -# CONFIG_FMAN_MIB_CNT_OVF_IRQ_EN is not set -# CONFIG_FMAN_P1023 is not set -# CONFIG_FMAN_P3040_P4080_P5020 is not set -# CONFIG_FMAN_PFC is not set -# CONFIG_FMAN_V3H is not set -# CONFIG_FMAN_V3L is not set -CONFIG_FRAME_POINTER=y -CONFIG_FSL_BMAN=y -CONFIG_FSL_BMAN_CONFIG=y -CONFIG_FSL_BMAN_DEBUGFS=y -# CONFIG_FSL_BMAN_TEST is not set -CONFIG_FSL_DPA=y -# CONFIG_FSL_DPAA_1588 is not set -CONFIG_FSL_DPAA_ADVANCED_DRIVERS=y -# CONFIG_FSL_DPAA_CEETM is not set -CONFIG_FSL_DPAA_CS_THRESHOLD_10G=0x10000000 -CONFIG_FSL_DPAA_CS_THRESHOLD_1G=0x06000000 -# CONFIG_FSL_DPAA_DBG_LOOP is not set -# CONFIG_FSL_DPAA_ETH_DEBUG is not set -CONFIG_FSL_DPAA_ETH_DEBUGFS=y -CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT=128 -CONFIG_FSL_DPAA_ETH_REFILL_THRESHOLD=80 -CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE=y -CONFIG_FSL_DPAA_GENERIC_DRIVER=y -# CONFIG_FSL_DPAA_HOOKS is not set -CONFIG_FSL_DPAA_INGRESS_CS_THRESHOLD=0x10000000 -# CONFIG_FSL_DPAA_MACSEC is not set -CONFIG_FSL_DPAA_OFFLINE_PORTS=y -# CONFIG_FSL_DPAA_TS is not set -CONFIG_FSL_DPA_CAN_WAIT=y -CONFIG_FSL_DPA_CAN_WAIT_SYNC=y -# CONFIG_FSL_DPA_CHECKING is not set -CONFIG_FSL_DPA_PIRQ_FAST=y -CONFIG_FSL_DPA_PIRQ_SLOW=y -CONFIG_FSL_DPA_PORTAL_SHARE=y -CONFIG_FSL_FM_MAX_FRAME_SIZE=1522 -CONFIG_FSL_FM_RX_EXTRA_HEADROOM=64 -CONFIG_FSL_IFC=y -CONFIG_FSL_QMAN=y -CONFIG_FSL_QMAN_CI_SCHED_CFG_BMAN_W=2 -CONFIG_FSL_QMAN_CI_SCHED_CFG_RW_W=2 -CONFIG_FSL_QMAN_CI_SCHED_CFG_SRCCIV=4 -CONFIG_FSL_QMAN_CI_SCHED_CFG_SRQ_W=3 -CONFIG_FSL_QMAN_CONFIG=y -CONFIG_FSL_QMAN_DEBUGFS=y -CONFIG_FSL_QMAN_FQD_SZ=10 -CONFIG_FSL_QMAN_INIT_TIMEOUT=10 -CONFIG_FSL_QMAN_PFDR_SZ=13 -CONFIG_FSL_QMAN_PIRQ_DQRR_ITHRESH=12 -CONFIG_FSL_QMAN_PIRQ_IPERIOD=100 -CONFIG_FSL_QMAN_PIRQ_MR_ITHRESH=4 -CONFIG_FSL_QMAN_POLL_LIMIT=32 -# CONFIG_FSL_QMAN_TEST is not set -CONFIG_FSL_SDK_DPAA_ETH=y -CONFIG_FSL_SDK_FMAN=y -# CONFIG_FSL_SDK_FMAN_TEST is not set -CONFIG_FSL_USDPAA=y -CONFIG_FSL_XGMAC_MDIO=y -# CONFIG_FTL is not set -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -# CONFIG_GIANFAR is not set -CONFIG_GPIOLIB=y -CONFIG_GPIO_DEVRES=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_MPC8XXX=y -CONFIG_GPIO_SYSFS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_FSL_QBMAN=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_BPF_JIT=y -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_ATTRS=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_GENERIC_RCU_GUP=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_RCU_TABLE_FREE=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_UID16=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -# CONFIG_HUGETLBFS is not set -CONFIG_I2C=y -# CONFIG_ACPI_I2C_OPREGION is not set -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_IMX=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -# CONFIG_IMX2_WDT is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IOMMU_HELPER=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LS_SCFG_MSI=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BOARDINFO=y -CONFIG_MEMORY=y -CONFIG_MFD_SYSCON=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=8 -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -# CONFIG_MMC_SDHCI_PCI is not set -# CONFIG_MMC_TIFM_SD is not set -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_BE_BYTE_SWAP=y -# CONFIG_MTD_CFI_GEOMETRY is not set -# CONFIG_MTD_CFI_NOSWAP is not set -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_FSL_IFC=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NO_BOOTMEM=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_MDIO=y -CONFIG_OF_MTD=y -CONFIG_OF_NET=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEBUG is not set -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_LAYERSCAPE=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_LAYERSCAPE=y -# CONFIG_POWER_RESET_XGENE is not set -CONFIG_POWER_SUPPLY=y -CONFIG_QMAN_CEETM_UPDATE_PERIOD=1000 -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -# CONFIG_SCHED_INFO is not set -CONFIG_SCSI=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SMP=y -CONFIG_SPARSE_IRQ=y -CONFIG_SQUASHFS=y -# CONFIG_SQUASHFS_FILE_CACHE is not set -CONFIG_SQUASHFS_FILE_DIRECT=y -# CONFIG_SQUASHFS_DECOMP_SINGLE is not set -# CONFIG_SQUASHFS_DECOMP_MULTI is not set -CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y -# CONFIG_SQUASHFS_XATTR is not set -# CONFIG_SQUASHFS_ZLIB is not set -# CONFIG_SQUASHFS_LZ4 is not set -# CONFIG_SQUASHFS_LZO is not set -CONFIG_SQUASHFS_XZ=y -# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -CONFIG_SRCU=y -CONFIG_SWIOTLB=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TREE_RCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USB=y -CONFIG_VITESSE_PHY=y -CONFIG_XPS=y -CONFIG_ZLIB_INFLATE=y -CONFIG_MTD_SPI_NOR=y -CONFIG_SPI_FSL_QUADSPI=y -CONFIG_FSL_MC_BUS=y -CONFIG_FSL_MC_RESTOOL=y -CONFIG_FSL_MC_DPIO=y -# CONFIG_FSL_QBMAN_DEBUG is not set -CONFIG_FSL_DPAA2=y -CONFIG_FSL_DPAA2_ETH=y -# CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE is not set -CONFIG_FSL_DPAA2_MAC=y -# CONFIG_FSL_DPAA2_MAC_NETDEVS is not set -CONFIG_FSL_DPAA2_EVB=y -CONFIG_FSL_DPAA2_ETHSW=y diff --git a/target/linux/layerscape/patches-4.4/0051-PCI-designware-Ensure-ATU-is-enabled-before-IO-conf-.patch b/target/linux/layerscape/patches-4.4/0051-PCI-designware-Ensure-ATU-is-enabled-before-IO-conf-.patch deleted file mode 100644 index c670dac4a5..0000000000 --- a/target/linux/layerscape/patches-4.4/0051-PCI-designware-Ensure-ATU-is-enabled-before-IO-conf-.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 7f434723cdb6823443330cd4847d5c3b8dd30bd7 Mon Sep 17 00:00:00 2001 -From: Stanimir Varbanov -Date: Fri, 18 Dec 2015 14:38:55 +0200 -Subject: [PATCH 51/70] PCI: designware: Ensure ATU is enabled before IO/conf - space accesses - -Read back the ATU CR2 register to ensure ATU programming is effective -before any subsequent I/O or config space accesses. - -Without this, PCI device enumeration is unreliable. - -[bhelgaas: changelog, comment] -Signed-off-by: Stanimir Varbanov -Signed-off-by: Bjorn Helgaas -Acked-by: Pratyush Anand ---- - drivers/pci/host/pcie-designware.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/pci/host/pcie-designware.c -+++ b/drivers/pci/host/pcie-designware.c -@@ -154,6 +154,8 @@ static int dw_pcie_wr_own_conf(struct pc - static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, - int type, u64 cpu_addr, u64 pci_addr, u32 size) - { -+ u32 val; -+ - dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index, - PCIE_ATU_VIEWPORT); - dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE); -@@ -164,6 +166,12 @@ static void dw_pcie_prog_outbound_atu(st - dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET); - dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1); - dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); -+ -+ /* -+ * Make sure ATU enable takes effect before any subsequent config -+ * and I/O accesses. -+ */ -+ dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val); - } - - static struct irq_chip dw_msi_irq_chip = { diff --git a/target/linux/layerscape/patches-4.4/0052-PCI-designware-Simplify-control-flow.patch b/target/linux/layerscape/patches-4.4/0052-PCI-designware-Simplify-control-flow.patch deleted file mode 100644 index 1eef2b61f3..0000000000 --- a/target/linux/layerscape/patches-4.4/0052-PCI-designware-Simplify-control-flow.patch +++ /dev/null @@ -1,121 +0,0 @@ -From 610b32220391c9d271290bdf8f2b8fe1cf8da9a0 Mon Sep 17 00:00:00 2001 -From: Bjorn Helgaas -Date: Tue, 5 Jan 2016 15:48:11 -0600 -Subject: [PATCH 52/70] PCI: designware: Simplify control flow - -Return values immediately when possible to simplify the control flow. - -No functional change intended. Folded in unused variable removal as -pointed out by Fabio Estevam , Arnd Bergmann -, and Thierry Reding . - -Signed-off-by: Bjorn Helgaas -Acked-by: Pratyush Anand ---- - drivers/pci/host/pcie-designware.c | 54 ++++++++++++------------------------ - 1 file changed, 18 insertions(+), 36 deletions(-) - ---- a/drivers/pci/host/pcie-designware.c -+++ b/drivers/pci/host/pcie-designware.c -@@ -128,27 +128,19 @@ static inline void dw_pcie_writel_rc(str - static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, - u32 *val) - { -- int ret; -- - if (pp->ops->rd_own_conf) -- ret = pp->ops->rd_own_conf(pp, where, size, val); -- else -- ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val); -+ return pp->ops->rd_own_conf(pp, where, size, val); - -- return ret; -+ return dw_pcie_cfg_read(pp->dbi_base + where, size, val); - } - - static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, - u32 val) - { -- int ret; -- - if (pp->ops->wr_own_conf) -- ret = pp->ops->wr_own_conf(pp, where, size, val); -- else -- ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val); -+ return pp->ops->wr_own_conf(pp, where, size, val); - -- return ret; -+ return dw_pcie_cfg_write(pp->dbi_base + where, size, val); - } - - static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, -@@ -392,8 +384,8 @@ int dw_pcie_link_up(struct pcie_port *pp - { - if (pp->ops->link_up) - return pp->ops->link_up(pp); -- else -- return 0; -+ -+ return 0; - } - - static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, -@@ -666,46 +658,36 @@ static int dw_pcie_rd_conf(struct pci_bu - int size, u32 *val) - { - struct pcie_port *pp = bus->sysdata; -- int ret; - - if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - -- if (bus->number != pp->root_bus_nr) -- if (pp->ops->rd_other_conf) -- ret = pp->ops->rd_other_conf(pp, bus, devfn, -- where, size, val); -- else -- ret = dw_pcie_rd_other_conf(pp, bus, devfn, -- where, size, val); -- else -- ret = dw_pcie_rd_own_conf(pp, where, size, val); -+ if (bus->number == pp->root_bus_nr) -+ return dw_pcie_rd_own_conf(pp, where, size, val); - -- return ret; -+ if (pp->ops->rd_other_conf) -+ return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val); -+ -+ return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val); - } - - static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 val) - { - struct pcie_port *pp = bus->sysdata; -- int ret; - - if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) - return PCIBIOS_DEVICE_NOT_FOUND; - -- if (bus->number != pp->root_bus_nr) -- if (pp->ops->wr_other_conf) -- ret = pp->ops->wr_other_conf(pp, bus, devfn, -- where, size, val); -- else -- ret = dw_pcie_wr_other_conf(pp, bus, devfn, -- where, size, val); -- else -- ret = dw_pcie_wr_own_conf(pp, where, size, val); -+ if (bus->number == pp->root_bus_nr) -+ return dw_pcie_wr_own_conf(pp, where, size, val); - -- return ret; -+ if (pp->ops->wr_other_conf) -+ return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val); -+ -+ return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); - } - - static struct pci_ops dw_pcie_ops = { diff --git a/target/linux/layerscape/patches-4.4/0053-PCI-designware-Make-config-accessor-override-checkin.patch b/target/linux/layerscape/patches-4.4/0053-PCI-designware-Make-config-accessor-override-checkin.patch deleted file mode 100644 index 299e87ebe8..0000000000 --- a/target/linux/layerscape/patches-4.4/0053-PCI-designware-Make-config-accessor-override-checkin.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 6882f9eef932e6f5cc3c57115e3d7d4b5bc19662 Mon Sep 17 00:00:00 2001 -From: Bjorn Helgaas -Date: Tue, 5 Jan 2016 15:56:30 -0600 -Subject: [PATCH 53/70] PCI: designware: Make config accessor override - checking symmetric - -Drivers based on the DesignWare core can override the config read accessors -by supplying rd_own_conf() and rd_other_conf() function pointers. -dw_pcie_rd_conf() calls dw_pcie_rd_own_conf() (for accesses to the root -bus) or dw_pcie_rd_other_conf(): - - dw_pcie_rd_conf - dw_pcie_rd_own_conf # if on root bus - dw_pcie_rd_other_conf # if not on root bus - -Previously we checked for rd_other_conf() directly in dw_pcie_rd_conf(), -but we checked for rd_own_conf() in dw_pcie_rd_own_conf(). - -Check for rd_other_conf() in dw_pcie_rd_other_conf() to make this symmetric -with the rd_own_conf() checking, and similarly for the write path. - -No functional change intended. - -Signed-off-by: Bjorn Helgaas -Acked-by: Pratyush Anand ---- - drivers/pci/host/pcie-designware.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - ---- a/drivers/pci/host/pcie-designware.c -+++ b/drivers/pci/host/pcie-designware.c -@@ -571,6 +571,9 @@ static int dw_pcie_rd_other_conf(struct - u64 cpu_addr; - void __iomem *va_cfg_base; - -+ if (pp->ops->rd_other_conf) -+ return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val); -+ - busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | - PCIE_ATU_FUNC(PCI_FUNC(devfn)); - -@@ -605,6 +608,9 @@ static int dw_pcie_wr_other_conf(struct - u64 cpu_addr; - void __iomem *va_cfg_base; - -+ if (pp->ops->wr_other_conf) -+ return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val); -+ - busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | - PCIE_ATU_FUNC(PCI_FUNC(devfn)); - -@@ -667,9 +673,6 @@ static int dw_pcie_rd_conf(struct pci_bu - if (bus->number == pp->root_bus_nr) - return dw_pcie_rd_own_conf(pp, where, size, val); - -- if (pp->ops->rd_other_conf) -- return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val); -- - return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val); - } - -@@ -684,9 +687,6 @@ static int dw_pcie_wr_conf(struct pci_bu - if (bus->number == pp->root_bus_nr) - return dw_pcie_wr_own_conf(pp, where, size, val); - -- if (pp->ops->wr_other_conf) -- return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val); -- - return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); - } - diff --git a/target/linux/layerscape/patches-4.4/0054-PCI-designware-Explain-why-we-don-t-program-ATU-for-.patch b/target/linux/layerscape/patches-4.4/0054-PCI-designware-Explain-why-we-don-t-program-ATU-for-.patch deleted file mode 100644 index f48150dab2..0000000000 --- a/target/linux/layerscape/patches-4.4/0054-PCI-designware-Explain-why-we-don-t-program-ATU-for-.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 481b1bc4ce0d58107887558342e50d6323a9601d Mon Sep 17 00:00:00 2001 -From: Jisheng Zhang -Date: Thu, 7 Jan 2016 14:12:38 +0800 -Subject: [PATCH 54/70] PCI: designware: Explain why we don't program ATU for - some platforms - -Some platforms don't support ATU, e.g., pci-keystone.c. These platforms -use their own address translation component rather than ATU, and they -provide the rd_other_conf and wr_other_conf methods to program the -translation component and perform the access. - -Add a comment to explain why we don't program the ATU for these platforms. - -[bhelgaas: changelog] -Signed-off-by: Jisheng Zhang -Signed-off-by: Bjorn Helgaas ---- - drivers/pci/host/pcie-designware.c | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/pci/host/pcie-designware.c -+++ b/drivers/pci/host/pcie-designware.c -@@ -517,6 +517,11 @@ int dw_pcie_host_init(struct pcie_port * - if (pp->ops->host_init) - pp->ops->host_init(pp); - -+ /* -+ * If the platform provides ->rd_other_conf, it means the platform -+ * uses its own address translation component rather than ATU, so -+ * we should not program the ATU here. -+ */ - if (!pp->ops->rd_other_conf) - dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, - PCIE_ATU_TYPE_MEM, pp->mem_base, diff --git a/target/linux/layerscape/patches-4.4/0055-PCI-designware-Remove-PCI_PROBE_ONLY-handling.patch b/target/linux/layerscape/patches-4.4/0055-PCI-designware-Remove-PCI_PROBE_ONLY-handling.patch deleted file mode 100644 index 13639ebebb..0000000000 --- a/target/linux/layerscape/patches-4.4/0055-PCI-designware-Remove-PCI_PROBE_ONLY-handling.patch +++ /dev/null @@ -1,41 +0,0 @@ -From ee2a430c1691d0bac3098e8db3c29d8f023b04c2 Mon Sep 17 00:00:00 2001 -From: Lorenzo Pieralisi -Date: Fri, 29 Jan 2016 11:29:32 +0000 -Subject: [PATCH 55/70] PCI: designware: Remove PCI_PROBE_ONLY handling - -The PCIe designware host driver is not used in system configurations -requiring the PCI_PROBE_ONLY flag to be set to prevent resources -assignment, therefore the driver code handling the flag can be removed -from the kernel. - -Signed-off-by: Lorenzo Pieralisi -Signed-off-by: Bjorn Helgaas -Acked-by: Pratyush Anand -Acked-by: Jingoo Han Jingoo Han -Cc: Arnd Bergmann -Cc: Gabriele Paoloni -Cc: Zhou Wang ---- - drivers/pci/host/pcie-designware.c | 10 ++++------ - 1 file changed, 4 insertions(+), 6 deletions(-) - ---- a/drivers/pci/host/pcie-designware.c -+++ b/drivers/pci/host/pcie-designware.c -@@ -556,13 +556,11 @@ int dw_pcie_host_init(struct pcie_port * - pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); - #endif - -- if (!pci_has_flag(PCI_PROBE_ONLY)) { -- pci_bus_size_bridges(bus); -- pci_bus_assign_resources(bus); -+ pci_bus_size_bridges(bus); -+ pci_bus_assign_resources(bus); - -- list_for_each_entry(child, &bus->children, node) -- pcie_bus_configure_settings(child); -- } -+ list_for_each_entry(child, &bus->children, node) -+ pcie_bus_configure_settings(child); - - pci_bus_add_devices(bus); - return 0; diff --git a/target/linux/layerscape/patches-4.4/0056-PCI-designware-Add-generic-dw_pcie_wait_for_link.patch b/target/linux/layerscape/patches-4.4/0056-PCI-designware-Add-generic-dw_pcie_wait_for_link.patch deleted file mode 100644 index b13aba33df..0000000000 --- a/target/linux/layerscape/patches-4.4/0056-PCI-designware-Add-generic-dw_pcie_wait_for_link.patch +++ /dev/null @@ -1,249 +0,0 @@ -From f0c3f31a8bd81b8e7354a187c49200f3ce52740d Mon Sep 17 00:00:00 2001 -From: Joao Pinto -Date: Thu, 10 Mar 2016 14:44:35 -0600 -Subject: [PATCH 56/70] PCI: designware: Add generic dw_pcie_wait_for_link() - -commit 886bc5ceb5cc3ad4b219502d72b277e3c3255a32 upstream -[context adjustment] -[remove drivers/pci/host/pcie-qcom.c related changes] - -Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and -spear13xx) had similar loops waiting for the link to come up. - -Add a generic dw_pcie_wait_for_link() for use by all these drivers so the -waiting is done consistently, e.g., always using usleep_range() rather than -mdelay() and using similar timeouts and retry counts. - -Note that this changes the Keystone link training/wait for link strategy, -so we initiate link training, then wait longer for the link to come up -before re-initiating link training. - -[bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c] -Signed-off-by: Joao Pinto -Signed-off-by: Bjorn Helgaas -Acked-by: Pratyush Anand -Integrated-by: Jiang Yutang ---- - drivers/pci/host/pci-dra7xx.c | 11 +---------- - drivers/pci/host/pci-exynos.c | 13 +++---------- - drivers/pci/host/pci-imx6.c | 13 ++++--------- - drivers/pci/host/pci-keystone.c | 10 ++++------ - drivers/pci/host/pcie-designware.c | 19 +++++++++++++++++++ - drivers/pci/host/pcie-designware.h | 6 ++++++ - drivers/pci/host/pcie-spear13xx.c | 14 +------------- - 7 files changed, 38 insertions(+), 48 deletions(-) - ---- a/drivers/pci/host/pci-dra7xx.c -+++ b/drivers/pci/host/pci-dra7xx.c -@@ -10,7 +10,6 @@ - * published by the Free Software Foundation. - */ - --#include - #include - #include - #include -@@ -108,7 +107,6 @@ static int dra7xx_pcie_establish_link(st - { - struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp); - u32 reg; -- unsigned int retries; - - if (dw_pcie_link_up(pp)) { - dev_err(pp->dev, "link is already up\n"); -@@ -119,14 +117,7 @@ static int dra7xx_pcie_establish_link(st - reg |= LTSSM_EN; - dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); - -- for (retries = 0; retries < 1000; retries++) { -- if (dw_pcie_link_up(pp)) -- return 0; -- usleep_range(10, 20); -- } -- -- dev_err(pp->dev, "link is not up\n"); -- return -EINVAL; -+ return dw_pcie_wait_for_link(pp); - } - - static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp) ---- a/drivers/pci/host/pci-exynos.c -+++ b/drivers/pci/host/pci-exynos.c -@@ -318,7 +318,6 @@ static int exynos_pcie_establish_link(st - { - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); - u32 val; -- unsigned int retries; - - if (dw_pcie_link_up(pp)) { - dev_err(pp->dev, "Link already up\n"); -@@ -357,13 +356,8 @@ static int exynos_pcie_establish_link(st - PCIE_APP_LTSSM_ENABLE); - - /* check if the link is up or not */ -- for (retries = 0; retries < 10; retries++) { -- if (dw_pcie_link_up(pp)) { -- dev_info(pp->dev, "Link up\n"); -- return 0; -- } -- mdelay(100); -- } -+ if (!dw_pcie_wait_for_link(pp)) -+ return 0; - - while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) { - val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED); -@@ -372,8 +366,7 @@ static int exynos_pcie_establish_link(st - /* power off phy */ - exynos_pcie_power_off_phy(pp); - -- dev_err(pp->dev, "PCIe Link Fail\n"); -- return -EINVAL; -+ return -ETIMEDOUT; - } - - static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp) ---- a/drivers/pci/host/pci-imx6.c -+++ b/drivers/pci/host/pci-imx6.c -@@ -330,19 +330,14 @@ static void imx6_pcie_init_phy(struct pc - - static int imx6_pcie_wait_for_link(struct pcie_port *pp) - { -- unsigned int retries; -+ /* check if the link is up or not */ -+ if (!dw_pcie_wait_for_link(pp)) -+ return 0; - -- for (retries = 0; retries < 200; retries++) { -- if (dw_pcie_link_up(pp)) -- return 0; -- usleep_range(100, 1000); -- } -- -- dev_err(pp->dev, "phy link never came up\n"); - dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", - readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), - readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); -- return -EINVAL; -+ return -ETIMEDOUT; - } - - static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp) ---- a/drivers/pci/host/pci-keystone.c -+++ b/drivers/pci/host/pci-keystone.c -@@ -97,17 +97,15 @@ static int ks_pcie_establish_link(struct - return 0; - } - -- ks_dw_pcie_initiate_link_train(ks_pcie); - /* check if the link is up or not */ -- for (retries = 0; retries < 200; retries++) { -- if (dw_pcie_link_up(pp)) -- return 0; -- usleep_range(100, 1000); -+ for (retries = 0; retries < 5; retries++) { - ks_dw_pcie_initiate_link_train(ks_pcie); -+ if (!dw_pcie_wait_for_link(pp)) -+ return 0; - } - - dev_err(pp->dev, "phy link never came up\n"); -- return -EINVAL; -+ return -ETIMEDOUT; - } - - static void ks_pcie_msi_irq_handler(struct irq_desc *desc) ---- a/drivers/pci/host/pcie-designware.c -+++ b/drivers/pci/host/pcie-designware.c -@@ -22,6 +22,7 @@ - #include - #include - #include -+#include - - #include "pcie-designware.h" - -@@ -380,6 +381,24 @@ static struct msi_controller dw_pcie_msi - .teardown_irq = dw_msi_teardown_irq, - }; - -+int dw_pcie_wait_for_link(struct pcie_port *pp) -+{ -+ int retries; -+ -+ /* check if the link is up or not */ -+ for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { -+ if (dw_pcie_link_up(pp)) { -+ dev_info(pp->dev, "link up\n"); -+ return 0; -+ } -+ usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); -+ } -+ -+ dev_err(pp->dev, "phy link never came up\n"); -+ -+ return -ETIMEDOUT; -+} -+ - int dw_pcie_link_up(struct pcie_port *pp) - { - if (pp->ops->link_up) ---- a/drivers/pci/host/pcie-designware.h -+++ b/drivers/pci/host/pcie-designware.h -@@ -22,6 +22,11 @@ - #define MAX_MSI_IRQS 32 - #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) - -+/* Parameters for the waiting for link up routine */ -+#define LINK_WAIT_MAX_RETRIES 10 -+#define LINK_WAIT_USLEEP_MIN 90000 -+#define LINK_WAIT_USLEEP_MAX 100000 -+ - struct pcie_port { - struct device *dev; - u8 root_bus_nr; -@@ -76,6 +81,7 @@ int dw_pcie_cfg_read(void __iomem *addr, - int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val); - irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); - void dw_pcie_msi_init(struct pcie_port *pp); -+int dw_pcie_wait_for_link(struct pcie_port *pp); - int dw_pcie_link_up(struct pcie_port *pp); - void dw_pcie_setup_rc(struct pcie_port *pp); - int dw_pcie_host_init(struct pcie_port *pp); ---- a/drivers/pci/host/pcie-spear13xx.c -+++ b/drivers/pci/host/pcie-spear13xx.c -@@ -13,7 +13,6 @@ - */ - - #include --#include - #include - #include - #include -@@ -149,7 +148,6 @@ static int spear13xx_pcie_establish_link - struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp); - struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; - u32 exp_cap_off = EXP_CAP_ID_OFFSET; -- unsigned int retries; - - if (dw_pcie_link_up(pp)) { - dev_err(pp->dev, "link already up\n"); -@@ -200,17 +198,7 @@ static int spear13xx_pcie_establish_link - | ((u32)1 << REG_TRANSLATION_ENABLE), - &app_reg->app_ctrl_0); - -- /* check if the link is up or not */ -- for (retries = 0; retries < 10; retries++) { -- if (dw_pcie_link_up(pp)) { -- dev_info(pp->dev, "link up\n"); -- return 0; -- } -- mdelay(100); -- } -- -- dev_err(pp->dev, "link Fail\n"); -- return -EINVAL; -+ return dw_pcie_wait_for_link(pp); - } - - static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg) diff --git a/target/linux/layerscape/patches-4.4/0057-PCI-designware-Add-default-link-up-check-if-sub-driv.patch b/target/linux/layerscape/patches-4.4/0057-PCI-designware-Add-default-link-up-check-if-sub-driv.patch deleted file mode 100644 index 7114fbb3af..0000000000 --- a/target/linux/layerscape/patches-4.4/0057-PCI-designware-Add-default-link-up-check-if-sub-driv.patch +++ /dev/null @@ -1,46 +0,0 @@ -From a0a4f406c7e90b2be66e88ea8b21699940c0823f Mon Sep 17 00:00:00 2001 -From: Joao Pinto -Date: Thu, 10 Mar 2016 14:44:44 -0600 -Subject: [PATCH 57/70] PCI: designware: Add default link up check if - sub-driver doesn't override - -Add a default DesignWare "link_up" test for use when a sub-driver doesn't -supply its own pcie_host_ops.link_up() method. - -[bhelgaas: changelog, split into its own patch] -Signed-off-by: Joao Pinto -Signed-off-by: Bjorn Helgaas -Acked-by: Pratyush Anand ---- - drivers/pci/host/pcie-designware.c | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/drivers/pci/host/pcie-designware.c -+++ b/drivers/pci/host/pcie-designware.c -@@ -70,6 +70,11 @@ - #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) - #define PCIE_ATU_UPPER_TARGET 0x91C - -+/* PCIe Port Logic registers */ -+#define PLR_OFFSET 0x700 -+#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c) -+#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010 -+ - static struct pci_ops dw_pcie_ops; - - int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) -@@ -401,10 +406,13 @@ int dw_pcie_wait_for_link(struct pcie_po - - int dw_pcie_link_up(struct pcie_port *pp) - { -+ u32 val; -+ - if (pp->ops->link_up) - return pp->ops->link_up(pp); - -- return 0; -+ val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); -+ return val & PCIE_PHY_DEBUG_R1_LINK_UP; - } - - static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, diff --git a/target/linux/layerscape/patches-4.4/0058-PCI-designware-Move-Root-Complex-setup-code-to-dw_pc.patch b/target/linux/layerscape/patches-4.4/0058-PCI-designware-Move-Root-Complex-setup-code-to-dw_pc.patch deleted file mode 100644 index 5826eb03b5..0000000000 --- a/target/linux/layerscape/patches-4.4/0058-PCI-designware-Move-Root-Complex-setup-code-to-dw_pc.patch +++ /dev/null @@ -1,109 +0,0 @@ -From 892a427f8a2b25b561298941cf1fc0373a98b269 Mon Sep 17 00:00:00 2001 -From: Jisheng Zhang -Date: Wed, 16 Mar 2016 19:40:33 +0800 -Subject: [PATCH 58/70] PCI: designware: Move Root Complex setup code to - dw_pcie_setup_rc() - -dw_pcie_host_init() looks up host bridge resources, ioremaps them, creates -IRQ domains, and enumerates devices below the bridge. dw_pcie_setup_rc() -programs the Root Complex registers. The Root Complex may lose power -during suspend-to-RAM, and when we resume, we want to redo the latter but -not the former. - -Move some Root Complex programming from dw_pcie_host_init() to -dw_pcie_setup_rc() where it belongs. DesignWare-based drivers can call -dw_pcie_setup_rc() in their resume paths. - -[Niklas Cassel : This change moves outbound ATU -programming, which uses pp->mem_base, to dw_pcie_setup_rc(). Apply the -dra7xx pp->mem_base update before calling dw_pcie_setup_rc().] - -[bhelgaas: changelog, fold in dra7xx fix from Niklas] -Signed-off-by: Jisheng Zhang -Signed-off-by: Bjorn Helgaas -Acked-by: Pratyush Anand ---- - drivers/pci/host/pci-dra7xx.c | 4 ++-- - drivers/pci/host/pcie-designware.c | 39 ++++++++++++++++++------------------ - 2 files changed, 21 insertions(+), 22 deletions(-) - ---- a/drivers/pci/host/pci-dra7xx.c -+++ b/drivers/pci/host/pci-dra7xx.c -@@ -142,13 +142,13 @@ static void dra7xx_pcie_enable_interrupt - - static void dra7xx_pcie_host_init(struct pcie_port *pp) - { -- dw_pcie_setup_rc(pp); -- - pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR; - pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR; - pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR; - pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR; - -+ dw_pcie_setup_rc(pp); -+ - dra7xx_pcie_establish_link(pp); - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); ---- a/drivers/pci/host/pcie-designware.c -+++ b/drivers/pci/host/pcie-designware.c -@@ -434,7 +434,6 @@ int dw_pcie_host_init(struct pcie_port * - struct platform_device *pdev = to_platform_device(pp->dev); - struct pci_bus *bus, *child; - struct resource *cfg_res; -- u32 val; - int i, ret; - LIST_HEAD(res); - struct resource_entry *win; -@@ -544,25 +543,6 @@ int dw_pcie_host_init(struct pcie_port * - if (pp->ops->host_init) - pp->ops->host_init(pp); - -- /* -- * If the platform provides ->rd_other_conf, it means the platform -- * uses its own address translation component rather than ATU, so -- * we should not program the ATU here. -- */ -- if (!pp->ops->rd_other_conf) -- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, -- PCIE_ATU_TYPE_MEM, pp->mem_base, -- pp->mem_bus_addr, pp->mem_size); -- -- dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); -- -- /* program correct class for RC */ -- dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); -- -- dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); -- val |= PORT_LOGIC_SPEED_CHANGE; -- dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); -- - pp->root_bus_nr = pp->busn->start; - if (IS_ENABLED(CONFIG_PCI_MSI)) { - bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr, -@@ -800,6 +780,25 @@ void dw_pcie_setup_rc(struct pcie_port * - val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - dw_pcie_writel_rc(pp, val, PCI_COMMAND); -+ -+ /* -+ * If the platform provides ->rd_other_conf, it means the platform -+ * uses its own address translation component rather than ATU, so -+ * we should not program the ATU here. -+ */ -+ if (!pp->ops->rd_other_conf) -+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, -+ PCIE_ATU_TYPE_MEM, pp->mem_base, -+ pp->mem_bus_addr, pp->mem_size); -+ -+ dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); -+ -+ /* program correct class for RC */ -+ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); -+ -+ dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); -+ val |= PORT_LOGIC_SPEED_CHANGE; -+ dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); - } - - MODULE_AUTHOR("Jingoo Han "); diff --git a/target/linux/layerscape/patches-4.4/0059-PCI-designware-Remove-incorrect-RC-memory-base-limit.patch b/target/linux/layerscape/patches-4.4/0059-PCI-designware-Remove-incorrect-RC-memory-base-limit.patch deleted file mode 100644 index 5eb0bb1a6f..0000000000 --- a/target/linux/layerscape/patches-4.4/0059-PCI-designware-Remove-incorrect-RC-memory-base-limit.patch +++ /dev/null @@ -1,45 +0,0 @@ -From ae717a9744a3e18f2ed0a6aa44e279c89ad5052c Mon Sep 17 00:00:00 2001 -From: Gabriele Paoloni -Date: Sat, 16 Apr 2016 12:03:39 +0100 -Subject: [PATCH 59/70] PCI: designware: Remove incorrect RC memory base/limit - configuration - -Currently dw_pcie_setup_rc() configures memory base and memory limit in the -type1 configuration header for the root complex. In doing so it uses the -CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr). -This is wrong and it is useless since the configuration is overwritten -later on when pci_bus_assign_resources() is called. - -Remove this configuration from dw_pcie_setup_rc(). - -Signed-off-by: Gabriele Paoloni -Signed-off-by: Bjorn Helgaas -Acked-by: Pratyush Anand ---- - drivers/pci/host/pcie-designware.c | 8 -------- - 1 file changed, 8 deletions(-) - ---- a/drivers/pci/host/pcie-designware.c -+++ b/drivers/pci/host/pcie-designware.c -@@ -708,8 +708,6 @@ static struct pci_ops dw_pcie_ops = { - void dw_pcie_setup_rc(struct pcie_port *pp) - { - u32 val; -- u32 membase; -- u32 memlimit; - - /* set the number of lanes */ - dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); -@@ -768,12 +766,6 @@ void dw_pcie_setup_rc(struct pcie_port * - val |= 0x00010100; - dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); - -- /* setup memory base, memory limit */ -- membase = ((u32)pp->mem_base & 0xfff00000) >> 16; -- memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000; -- val = memlimit | membase; -- dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); -- - /* setup command register */ - dw_pcie_readl_rc(pp, PCI_COMMAND, &val); - val &= 0xffff0000; diff --git a/target/linux/layerscape/patches-4.4/0140-config-add-freescale-config-for-amr64.patch b/target/linux/layerscape/patches-4.4/0140-config-add-freescale-config-for-amr64.patch deleted file mode 100644 index 74ff44bdab..0000000000 --- a/target/linux/layerscape/patches-4.4/0140-config-add-freescale-config-for-amr64.patch +++ /dev/null @@ -1,148 +0,0 @@ -From 880b7aa2e2c62e54245fb77d92db502175232d86 Mon Sep 17 00:00:00 2001 -From: Zhao Qiang -Date: Wed, 12 Oct 2016 11:01:17 +0800 -Subject: [PATCH 140/141] config: add freescale config for amr64 - -Signed-off-by: Zhao Qiang ---- - arch/arm64/configs/freescale.config | 134 +++++++++++++++++++++++++++++++++++ - 1 file changed, 134 insertions(+) - create mode 100644 arch/arm64/configs/freescale.config - ---- /dev/null -+++ b/arch/arm64/configs/freescale.config -@@ -0,0 +1,134 @@ -+# general options -+CONFIG_LOCALVERSION_AUTO=y -+CONFIG_SLAB=y -+CONFIG_MODULE_FORCE_LOAD=y -+CONFIG_MODVERSIONS=y -+CONFIG_ARM64_VA_BITS_48=y -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_SIZE=262144 -+CONFIG_PRINTK_TIME=y -+CONFIG_PID_IN_CONTEXTIDR=y -+CONFIG_IPV6=y -+# iommu -+CONFIG_IOMMU_SUPPORT=y -+CONFIG_ARM_SMMU=y -+# dpaa2 -+CONFIG_STAGING=y -+CONFIG_FSL_MC_BUS=y -+CONFIG_FSL_MC_RESTOOL=y -+CONFIG_FSL_MC_DPIO=y -+CONFIG_FSL_DPAA2=y -+CONFIG_NET_NS=y -+CONFIG_FSL_DPAA2_DCE=y -+CONFIG_FSL_DCE_FLOW_LIMIT=65536 -+CONFIG_FSL_DCE_API_TIME_TRIAL=m -+CONFIG_LS_SOC_DRIVERS=y -+# mdio -+CONFIG_FSL_XGMAC_MDIO=y -+CONFIG_MDIO_BUS_MUX_MMIOREG=y -+# phy -+CONFIG_AQUANTIA_PHY=y -+CONFIG_VITESSE_PHY=y -+CONFIG_REALTEK_PHY=y -+CONFIG_FIXED_PHY=y -+# reset support -+CONFIG_POWER_RESET_LAYERSCAPE=y -+# pci -+CONFIG_PCI_LAYERSCAPE=y -+CONFIG_PCI_HOST_GENERIC=y -+CONFIG_E1000=y -+CONFIG_E1000E=y -+# clock driver -+CONFIG_CLK_QORIQ=y -+# usb -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_DWC3=y -+CONFIG_DMADEVICES=y -+# ahci/sata -+CONFIG_AHCI_QORIQ=y -+# esdhc -+CONFIG_MMC_SDHCI_OF_ESDHC=y -+# virtualization -+CONFIG_VHOST_NET=y -+CONFIG_KVM_ARM_MAX_VCPUS=8 -+# I2C -+CONFIG_I2C=y -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_MUX=y -+CONFIG_I2C_MUX_PCA954x=y -+CONFIG_I2C_IMX=y -+# hardware monitor -+CONFIG_SENSORS_LM90=y -+CONFIG_SENSORS_INA2XX=y -+# DPAA 1 -+CONFIG_HAS_FSL_QBMAN=y -+CONFIG_CRYPTO_DEV_FSL_CAAM=y -+# network -+CONFIG_BRIDGE=m -+CONFIG_MACVLAN=y -+CONFIG_FSL_SDK_FMAN=y -+CONFIG_FMAN_ARM=y -+CONFIG_FSL_SDK_DPAA_ETH=y -+CONFIG_INET_ESP=y -+CONFIG_XFRM_USER=y -+CONFIG_NET_KEY=y -+# vfio -+CONFIG_VFIO=y -+CONFIG_VFIO_PCI=y -+CONFIG_VFIO_FSL_MC=y -+# CPU Frequency scaling -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_GOV_COMMON=y -+CONFIG_CPU_FREQ_STAT=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+CONFIG_QORIQ_CPUFREQ=y -+#ifc -+CONFIG_MTD_OF_PARTS=y -+CONFIG_MTD_GEN_PROBE=y -+CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_BLOCK=y -+CONFIG_MTD_CFI=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_CFI_STAA=y -+CONFIG_MTD_PHYSMAP_OF=y -+CONFIG_MTD_NAND=y -+CONFIG_MTD_NAND_FSL_IFC=y -+#spi -+CONFIG_SPI_FSL_DSPI=y -+CONFIG_MTD_SPI_NOR=y -+CONFIG_MTD_DATAFLASH=y -+CONFIG_MTD_M25P80=y -+CONFIG_MTD_SST25L=y -+#RTC -+CONFIG_RTC_DRV_DS3232=y -+#CryptoAPI -+CONFIG_CRYPTO_SHA256=y -+CONFIG_CRYPTO_SHA512=y -+# ls1046a -+CONFIG_MTD_CFI_BE_BYTE_SWAP=y -+CONFIG_SPI_FSL_QUADSPI=y -+CONFIG_RTC_DRV_PCF2127=y -+CONFIG_WATCHDOG=y -+CONFIG_IMX2_WDT=y -+CONFIG_HWMON=y -+CONFIG_SENSORS_LM90=y -+CONFIG_SENSORS_INA2XX=y -+CONFIG_EEPROM_AT24=y -+# lpuart -+CONFIG_SERIAL_FSL_LPUART=y -+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -+# ftm -+CONFIG_FTM_ALARM=y -+# qDMA -+CONFIG_FSL_QDMA=y -+CONFIG_DMATEST=y -+#NVMe -+CONFIG_BLK_DEV_NVME=y diff --git a/target/linux/layerscape/patches-4.4/0238-arm64-disable-CONFIG_EEPROM_AT24-for-freescale.confi.patch b/target/linux/layerscape/patches-4.4/0238-arm64-disable-CONFIG_EEPROM_AT24-for-freescale.confi.patch deleted file mode 100644 index a16524a671..0000000000 --- a/target/linux/layerscape/patches-4.4/0238-arm64-disable-CONFIG_EEPROM_AT24-for-freescale.confi.patch +++ /dev/null @@ -1,24 +0,0 @@ -From fbc31a61b7bcfbc9ae1a8acda547de891f4b8ee4 Mon Sep 17 00:00:00 2001 -From: Yangbo Lu -Date: Mon, 31 Oct 2016 17:50:03 +0800 -Subject: [PATCH 238/238] arm64: disable CONFIG_EEPROM_AT24 for - freescale.config - -Disable CONFIG_EEPROM_AT24 in freescale.config. Otherwise, i2cdump -for EEPROM will get resource busy issue. - -Signed-off-by: Yangbo Lu ---- - arch/arm64/configs/freescale.config | 1 - - 1 file changed, 1 deletion(-) - ---- a/arch/arm64/configs/freescale.config -+++ b/arch/arm64/configs/freescale.config -@@ -121,7 +121,6 @@ CONFIG_IMX2_WDT=y - CONFIG_HWMON=y - CONFIG_SENSORS_LM90=y - CONFIG_SENSORS_INA2XX=y --CONFIG_EEPROM_AT24=y - # lpuart - CONFIG_SERIAL_FSL_LPUART=y - CONFIG_SERIAL_FSL_LPUART_CONSOLE=y diff --git a/target/linux/layerscape/patches-4.4/0239-ARM-dts-ls1021a-add-PCIe-dts-node.patch b/target/linux/layerscape/patches-4.4/0239-ARM-dts-ls1021a-add-PCIe-dts-node.patch deleted file mode 100644 index 1e47060a0a..0000000000 --- a/target/linux/layerscape/patches-4.4/0239-ARM-dts-ls1021a-add-PCIe-dts-node.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 1f58043afef0dca3d12dc23ac3a35d7074412939 Mon Sep 17 00:00:00 2001 -From: Minghuan Lian -Date: Tue, 2 Feb 2016 16:30:07 +0800 -Subject: [PATCH 01/13] ARM: dts: ls1021a: add PCIe dts node - -Cherry-pick upstream patch. - -LS1021a contains two PCIe controllers. The patch adds their node to -dts file. - -Signed-off-by: Minghuan Lian -Signed-off-by: Yangbo Lu ---- - arch/arm/boot/dts/ls1021a.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 44 insertions(+) - ---- a/arch/arm/boot/dts/ls1021a.dtsi -+++ b/arch/arm/boot/dts/ls1021a.dtsi -@@ -539,5 +539,49 @@ - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - }; -+ -+ pcie@3400000 { -+ compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ -+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = ; /* controller interrupt */ -+ fsl,pcie-scfg = <&scfg 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ pcie@3500000 { -+ compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ -+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = ; -+ fsl,pcie-scfg = <&scfg 1>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; -+ }; - }; - }; diff --git a/target/linux/layerscape/patches-4.4/0240-ARM-dts-ls1021a-add-SCFG-MSI-dts-node.patch b/target/linux/layerscape/patches-4.4/0240-ARM-dts-ls1021a-add-SCFG-MSI-dts-node.patch deleted file mode 100644 index ca2663b86c..0000000000 --- a/target/linux/layerscape/patches-4.4/0240-ARM-dts-ls1021a-add-SCFG-MSI-dts-node.patch +++ /dev/null @@ -1,56 +0,0 @@ -From b57dcab78fdc76a6c56c2df71518fb022429e244 Mon Sep 17 00:00:00 2001 -From: Minghuan Lian -Date: Wed, 6 Apr 2016 19:02:07 +0800 -Subject: [PATCH 02/13] ARM: dts: ls1021a: add SCFG MSI dts node - -Cherry-pick upstream patch. - -Add SCFG MSI dts node and add msi-parent property to PCIe dts node -that points to the corresponding MSI node. - -Signed-off-by: Minghuan Lian -Tested-by: Alexander Stein -Signed-off-by: Yangbo Lu ---- - arch/arm/boot/dts/ls1021a.dtsi | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/arch/arm/boot/dts/ls1021a.dtsi -+++ b/arch/arm/boot/dts/ls1021a.dtsi -@@ -119,6 +119,20 @@ - - }; - -+ msi1: msi-controller@1570e00 { -+ compatible = "fsl,1s1021a-msi"; -+ reg = <0x0 0x1570e00 0x0 0x8>; -+ msi-controller; -+ interrupts = ; -+ }; -+ -+ msi2: msi-controller@1570e08 { -+ compatible = "fsl,1s1021a-msi"; -+ reg = <0x0 0x1570e08 0x0 0x8>; -+ msi-controller; -+ interrupts = ; -+ }; -+ - ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x1530000 0x0 0x10000>; -@@ -554,6 +568,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&msi1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, -@@ -576,6 +591,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&msi2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, diff --git a/target/linux/layerscape/patches-4.4/0241-dt-bindings-Add-bindings-for-Layerscape-SCFG-MSI.patch b/target/linux/layerscape/patches-4.4/0241-dt-bindings-Add-bindings-for-Layerscape-SCFG-MSI.patch deleted file mode 100644 index 463df7db1a..0000000000 --- a/target/linux/layerscape/patches-4.4/0241-dt-bindings-Add-bindings-for-Layerscape-SCFG-MSI.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 066320dd0643e66bc5afe0d0984e77b2e938a6f4 Mon Sep 17 00:00:00 2001 -From: Minghuan Lian -Date: Wed, 23 Mar 2016 19:08:19 +0800 -Subject: [PATCH 03/13] dt/bindings: Add bindings for Layerscape SCFG MSI - -Cherry-pick upstream patch. - -Some Layerscape SoCs use a simple MSI controller implementation. -It contains only two SCFG register to trigger and describe a -group 32 MSI interrupts. The patch adds bindings to describe -the controller. - -Signed-off-by: Minghuan Lian -Acked-by: Rob Herring -Signed-off-by: Yangbo Lu ---- - .../interrupt-controller/fsl,ls-scfg-msi.txt | 30 ++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt -@@ -0,0 +1,30 @@ -+* Freescale Layerscape SCFG PCIe MSI controller -+ -+Required properties: -+ -+- compatible: should be "fsl,-msi" to identify -+ Layerscape PCIe MSI controller block such as: -+ "fsl,1s1021a-msi" -+ "fsl,1s1043a-msi" -+- msi-controller: indicates that this is a PCIe MSI controller node -+- reg: physical base address of the controller and length of memory mapped. -+- interrupts: an interrupt to the parent interrupt controller. -+ -+Optional properties: -+- interrupt-parent: the phandle to the parent interrupt controller. -+ -+This interrupt controller hardware is a second level interrupt controller that -+is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based -+platforms. If interrupt-parent is not provided, the default parent interrupt -+controller will be used. -+Each PCIe node needs to have property msi-parent that points to -+MSI controller node -+ -+Examples: -+ -+ msi1: msi-controller@1571000 { -+ compatible = "fsl,1s1043a-msi"; -+ reg = <0x0 0x1571000 0x0 0x8>, -+ msi-controller; -+ interrupts = <0 116 0x4>; -+ }; diff --git a/target/linux/layerscape/patches-4.4/1074-mtd-nand-spi-nor-assign-MTD-of_node.patch b/target/linux/layerscape/patches-4.4/1074-mtd-nand-spi-nor-assign-MTD-of_node.patch deleted file mode 100644 index 358b51245f..0000000000 --- a/target/linux/layerscape/patches-4.4/1074-mtd-nand-spi-nor-assign-MTD-of_node.patch +++ /dev/null @@ -1,31 +0,0 @@ -From f560fdb9d71aaf3adc54341a1650577c78495df9 Mon Sep 17 00:00:00 2001 -From: Brian Norris -Date: Fri, 30 Oct 2015 20:33:22 -0700 -Subject: [PATCH 074/113] mtd: {nand,spi-nor}: assign MTD of_node - -We should pass along our flash DT node to the MTD layer, so it can set -up ofpart for us. - -cherry-pick{ -remove the code: -drivers/mtd/nand/nand_base.c | 3 + -commit:3e63b26bdd4069c3df2cd7ce7217a21d06801b41 -} - -Signed-off-by: Brian Norris -Reviewed-by: Boris Brezillon -Signed-off-by: Yuan Yao ---- - drivers/mtd/spi-nor/spi-nor.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -1228,6 +1228,7 @@ int spi_nor_scan(struct spi_nor *nor, co - mtd->flags |= MTD_NO_ERASE; - - mtd->dev.parent = dev; -+ mtd_set_of_node(mtd, np); - nor->page_size = info->page_size; - mtd->writebufsize = nor->page_size; - diff --git a/target/linux/layerscape/patches-4.4/1075-mtd-spi-nor-convert-to-spi_nor_-get-set-_flash_node.patch b/target/linux/layerscape/patches-4.4/1075-mtd-spi-nor-convert-to-spi_nor_-get-set-_flash_node.patch deleted file mode 100644 index bbe29b612a..0000000000 --- a/target/linux/layerscape/patches-4.4/1075-mtd-spi-nor-convert-to-spi_nor_-get-set-_flash_node.patch +++ /dev/null @@ -1,80 +0,0 @@ -From f906ec330da9aa83de5382653436be36273c63d3 Mon Sep 17 00:00:00 2001 -From: Brian Norris -Date: Fri, 30 Oct 2015 20:33:24 -0700 -Subject: [PATCH 075/113] mtd: spi-nor: convert to spi_nor_{get, - set}_flash_node() - -Used semantic patch with 'make coccicheck MODE=patch COCCI=script.cocci': - ----8<---- -virtual patch - -@@ -struct spi_nor b; -struct spi_nor *c; -expression d; -@@ -( --(b).flash_node = (d) -+spi_nor_set_flash_node(&b, d) -| --(c)->flash_node = (d) -+spi_nor_set_flash_node(c, d) -) ----8<---- - -And a manual conversion for the one use of spi_nor_get_flash_node(). - -Signed-off-by: Brian Norris -Reviewed-by: Boris Brezillon ---- - drivers/mtd/devices/m25p80.c | 2 +- - drivers/mtd/spi-nor/fsl-quadspi.c | 2 +- - drivers/mtd/spi-nor/nxp-spifi.c | 2 +- - drivers/mtd/spi-nor/spi-nor.c | 2 +- - 4 files changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -221,7 +221,7 @@ static int m25p_probe(struct spi_device - nor->read_reg = m25p80_read_reg; - - nor->dev = &spi->dev; -- nor->flash_node = spi->dev.of_node; -+ spi_nor_set_flash_node(nor, spi->dev.of_node); - nor->priv = flash; - - spi_set_drvdata(spi, flash); ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -1013,7 +1013,7 @@ static int fsl_qspi_probe(struct platfor - mtd = &nor->mtd; - - nor->dev = dev; -- nor->flash_node = np; -+ spi_nor_set_flash_node(nor, np); - nor->priv = q; - - /* fill the hooks */ ---- a/drivers/mtd/spi-nor/nxp-spifi.c -+++ b/drivers/mtd/spi-nor/nxp-spifi.c -@@ -330,7 +330,7 @@ static int nxp_spifi_setup_flash(struct - writel(ctrl, spifi->io_base + SPIFI_CTRL); - - spifi->nor.dev = spifi->dev; -- spifi->nor.flash_node = np; -+ spi_nor_set_flash_node(&spifi->nor, np); - spifi->nor.priv = spifi; - spifi->nor.read = nxp_spifi_read; - spifi->nor.write = nxp_spifi_write; ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -1120,7 +1120,7 @@ int spi_nor_scan(struct spi_nor *nor, co - const struct flash_info *info = NULL; - struct device *dev = nor->dev; - struct mtd_info *mtd = &nor->mtd; -- struct device_node *np = nor->flash_node; -+ struct device_node *np = spi_nor_get_flash_node(nor); - int ret; - int i; - diff --git a/target/linux/layerscape/patches-4.4/1076-mtd-spi-nor-drop-unnecessary-partition-parser-data.patch b/target/linux/layerscape/patches-4.4/1076-mtd-spi-nor-drop-unnecessary-partition-parser-data.patch deleted file mode 100644 index 0960f53318..0000000000 --- a/target/linux/layerscape/patches-4.4/1076-mtd-spi-nor-drop-unnecessary-partition-parser-data.patch +++ /dev/null @@ -1,83 +0,0 @@ -From e36da6d0a0841ea3a75d5189057bd020d737e71a Mon Sep 17 00:00:00 2001 -From: Brian Norris -Date: Fri, 30 Oct 2015 20:33:26 -0700 -Subject: [PATCH 076/113] mtd: spi-nor: drop unnecessary partition parser data - -Now that the SPI-NOR/MTD framework pass the 'flash_node' through to the -partition parsing code, we don't have to do it ourselves. - -Also convert to mtd_device_register(), since we don't need the 2nd and -3rd parameters anymore. - -Signed-off-by: Brian Norris -Reviewed-by: Boris Brezillon ---- - drivers/mtd/devices/m25p80.c | 8 ++------ - drivers/mtd/spi-nor/fsl-quadspi.c | 4 +--- - drivers/mtd/spi-nor/nxp-spifi.c | 4 +--- - 3 files changed, 4 insertions(+), 12 deletions(-) - ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -197,7 +197,6 @@ static int m25p80_erase(struct spi_nor * - */ - static int m25p_probe(struct spi_device *spi) - { -- struct mtd_part_parser_data ppdata; - struct flash_platform_data *data; - struct m25p *flash; - struct spi_nor *nor; -@@ -249,11 +248,8 @@ static int m25p_probe(struct spi_device - if (ret) - return ret; - -- ppdata.of_node = spi->dev.of_node; -- -- return mtd_device_parse_register(&nor->mtd, NULL, &ppdata, -- data ? data->parts : NULL, -- data ? data->nr_parts : 0); -+ return mtd_device_register(&nor->mtd, data ? data->parts : NULL, -+ data ? data->nr_parts : 0); - } - - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -927,7 +927,6 @@ static void fsl_qspi_unprep(struct spi_n - static int fsl_qspi_probe(struct platform_device *pdev) - { - struct device_node *np = pdev->dev.of_node; -- struct mtd_part_parser_data ppdata; - struct device *dev = &pdev->dev; - struct fsl_qspi *q; - struct resource *res; -@@ -1038,8 +1037,7 @@ static int fsl_qspi_probe(struct platfor - if (ret) - goto mutex_failed; - -- ppdata.of_node = np; -- ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0); -+ ret = mtd_device_register(mtd, NULL, 0); - if (ret) - goto mutex_failed; - ---- a/drivers/mtd/spi-nor/nxp-spifi.c -+++ b/drivers/mtd/spi-nor/nxp-spifi.c -@@ -271,7 +271,6 @@ static void nxp_spifi_dummy_id_read(stru - static int nxp_spifi_setup_flash(struct nxp_spifi *spifi, - struct device_node *np) - { -- struct mtd_part_parser_data ppdata; - enum read_mode flash_read; - u32 ctrl, property; - u16 mode = 0; -@@ -361,8 +360,7 @@ static int nxp_spifi_setup_flash(struct - return ret; - } - -- ppdata.of_node = np; -- ret = mtd_device_parse_register(&spifi->nor.mtd, NULL, &ppdata, NULL, 0); -+ ret = mtd_device_register(&spifi->nor.mtd, NULL, 0); - if (ret) { - dev_err(spifi->dev, "mtd device parse failed\n"); - return ret; diff --git a/target/linux/layerscape/patches-4.4/1077-mtd-add-get-set-of_node-flash_node-helpers.patch b/target/linux/layerscape/patches-4.4/1077-mtd-add-get-set-of_node-flash_node-helpers.patch deleted file mode 100644 index eeba1e90db..0000000000 --- a/target/linux/layerscape/patches-4.4/1077-mtd-add-get-set-of_node-flash_node-helpers.patch +++ /dev/null @@ -1,62 +0,0 @@ -From a2f87e7df641b482e217f5b0efbaf41f6b8a0cf6 Mon Sep 17 00:00:00 2001 -From: Brian Norris -Date: Fri, 30 Oct 2015 20:33:20 -0700 -Subject: [PATCH 077/113] mtd: add get/set of_node/flash_node helpers - -We are going to begin using the mtd->dev.of_node field for MTD device -nodes, so let's add helpers for it. Also, we'll be making some -conversions on spi_nor (and nand_chip eventually) too, so get that ready -with their own helpers. - -commit:28b8b26b308e656edfa9467867d5f79212da2ec3 -delete the include/linux/mtd/nand.h -just upgrade the code about spi. - -Signed-off-by: Brian Norris -Reviewed-by: Boris Brezillon -Signed-off-by: Yuan Yao ---- - include/linux/mtd/mtd.h | 11 +++++++++++ - include/linux/mtd/spi-nor.h | 11 +++++++++++ - 2 files changed, 22 insertions(+) - ---- a/include/linux/mtd/mtd.h -+++ b/include/linux/mtd/mtd.h -@@ -258,6 +258,17 @@ struct mtd_info { - int usecount; - }; - -+static inline void mtd_set_of_node(struct mtd_info *mtd, -+ struct device_node *np) -+{ -+ mtd->dev.of_node = np; -+} -+ -+static inline struct device_node *mtd_get_of_node(struct mtd_info *mtd) -+{ -+ return mtd->dev.of_node; -+} -+ - int mtd_erase(struct mtd_info *mtd, struct erase_info *instr); - int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, - void **virt, resource_size_t *phys); ---- a/include/linux/mtd/spi-nor.h -+++ b/include/linux/mtd/spi-nor.h -@@ -184,6 +184,17 @@ struct spi_nor { - void *priv; - }; - -+static inline void spi_nor_set_flash_node(struct spi_nor *nor, -+ struct device_node *np) -+{ -+ nor->flash_node = np; -+} -+ -+static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor) -+{ -+ return nor->flash_node; -+} -+ - /** - * spi_nor_scan() - scan the SPI NOR - * @nor: the spi_nor structure diff --git a/target/linux/layerscape/patches-4.4/1078-mtd-spi-nor-drop-flash_node-field.patch b/target/linux/layerscape/patches-4.4/1078-mtd-spi-nor-drop-flash_node-field.patch deleted file mode 100644 index dc551dfabb..0000000000 --- a/target/linux/layerscape/patches-4.4/1078-mtd-spi-nor-drop-flash_node-field.patch +++ /dev/null @@ -1,57 +0,0 @@ -From df36b4601bc9f84684249a26eb39b818d6785fb8 Mon Sep 17 00:00:00 2001 -From: Brian Norris -Date: Fri, 30 Oct 2015 20:33:27 -0700 -Subject: [PATCH 078/113] mtd: spi-nor: drop flash_node field - -We can just alias to the MTD of_node. - -Signed-off-by: Brian Norris -Reviewed-by: Boris Brezillon ---- - drivers/mtd/spi-nor/spi-nor.c | 1 - - include/linux/mtd/spi-nor.h | 6 ++---- - 2 files changed, 2 insertions(+), 5 deletions(-) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -1228,7 +1228,6 @@ int spi_nor_scan(struct spi_nor *nor, co - mtd->flags |= MTD_NO_ERASE; - - mtd->dev.parent = dev; -- mtd_set_of_node(mtd, np); - nor->page_size = info->page_size; - mtd->writebufsize = nor->page_size; - ---- a/include/linux/mtd/spi-nor.h -+++ b/include/linux/mtd/spi-nor.h -@@ -123,7 +123,6 @@ enum spi_nor_option_flags { - * @mtd: point to a mtd_info structure - * @lock: the lock for the read/write/erase/lock/unlock operations - * @dev: point to a spi device, or a spi nor controller device. -- * @flash_node: point to a device node describing this flash instance. - * @page_size: the page size of the SPI NOR - * @addr_width: number of address bytes - * @erase_opcode: the opcode for erasing a sector -@@ -154,7 +153,6 @@ struct spi_nor { - struct mtd_info mtd; - struct mutex lock; - struct device *dev; -- struct device_node *flash_node; - u32 page_size; - u8 addr_width; - u8 erase_opcode; -@@ -187,12 +185,12 @@ struct spi_nor { - static inline void spi_nor_set_flash_node(struct spi_nor *nor, - struct device_node *np) - { -- nor->flash_node = np; -+ mtd_set_of_node(&nor->mtd, np); - } - - static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor) - { -- return nor->flash_node; -+ return mtd_get_of_node(&nor->mtd); - } - - /** diff --git a/target/linux/layerscape/patches-4.4/1079-mtd-spi-nor-remove-unnecessary-leading-space-from-db.patch b/target/linux/layerscape/patches-4.4/1079-mtd-spi-nor-remove-unnecessary-leading-space-from-db.patch deleted file mode 100644 index 13b30cf7e3..0000000000 --- a/target/linux/layerscape/patches-4.4/1079-mtd-spi-nor-remove-unnecessary-leading-space-from-db.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 3ea419cf269832f5743d9b5ad75ece5178b02b09 Mon Sep 17 00:00:00 2001 -From: Brian Norris -Date: Fri, 30 Oct 2015 12:56:22 -0700 -Subject: [PATCH 079/113] mtd: spi-nor: remove unnecessary leading space from - dbg print - -As Cyrille noted [1], this line is wrong. - -[1] http://lists.infradead.org/pipermail/linux-mtd/2015-September/061725.html - -Signed-off-by: Brian Norris -Cc: Cyrille Pitchen ---- - drivers/mtd/spi-nor/spi-nor.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -862,7 +862,7 @@ static const struct flash_info *spi_nor_ - - tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); - if (tmp < 0) { -- dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp); -+ dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); - return ERR_PTR(tmp); - } - diff --git a/target/linux/layerscape/patches-4.4/1080-mtd-fsl-quadspi-possible-NULL-dereference.patch b/target/linux/layerscape/patches-4.4/1080-mtd-fsl-quadspi-possible-NULL-dereference.patch deleted file mode 100644 index 76898ab58d..0000000000 --- a/target/linux/layerscape/patches-4.4/1080-mtd-fsl-quadspi-possible-NULL-dereference.patch +++ /dev/null @@ -1,50 +0,0 @@ -From bd02decd1ad7cc883ce388e769a34a3c402b90c4 Mon Sep 17 00:00:00 2001 -From: Brian Norris -Date: Mon, 16 Nov 2015 10:45:30 -0800 -Subject: [PATCH 080/113] mtd: fsl-quadspi: possible NULL dereference - -It is theoretically possible to probe this driver without a matching -device tree, so let's guard against this. - -Also, use the of_device_get_match_data() helper to make this a bit -simpler. - -Coverity complained about this one. - -Signed-off-by: Brian Norris -Acked-by: Han xu ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -269,7 +269,7 @@ struct fsl_qspi { - struct clk *clk, *clk_en; - struct device *dev; - struct completion c; -- struct fsl_qspi_devtype_data *devtype_data; -+ const struct fsl_qspi_devtype_data *devtype_data; - u32 nor_size; - u32 nor_num; - u32 clk_rate; -@@ -933,8 +933,6 @@ static int fsl_qspi_probe(struct platfor - struct spi_nor *nor; - struct mtd_info *mtd; - int ret, i = 0; -- const struct of_device_id *of_id = -- of_match_device(fsl_qspi_dt_ids, &pdev->dev); - - q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL); - if (!q) -@@ -945,7 +943,9 @@ static int fsl_qspi_probe(struct platfor - return -ENODEV; - - q->dev = dev; -- q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data; -+ q->devtype_data = of_device_get_match_data(dev); -+ if (!q->devtype_data) -+ return -ENODEV; - platform_set_drvdata(pdev, q); - - /* find the resources */ diff --git a/target/linux/layerscape/patches-4.4/1081-mtd-spi-nor-provide-default-erase_sector-implementat.patch b/target/linux/layerscape/patches-4.4/1081-mtd-spi-nor-provide-default-erase_sector-implementat.patch deleted file mode 100644 index e966cafce6..0000000000 --- a/target/linux/layerscape/patches-4.4/1081-mtd-spi-nor-provide-default-erase_sector-implementat.patch +++ /dev/null @@ -1,105 +0,0 @@ -From 56bd0e13d8bc3b4486251b10ac9d2ba7434c21ee Mon Sep 17 00:00:00 2001 -From: Brian Norris -Date: Tue, 10 Nov 2015 12:15:27 -0800 -Subject: [PATCH 081/113] mtd: spi-nor: provide default erase_sector - implementation - -Some spi-nor drivers perform sector erase by duplicating their -write_reg() command. Let's not require that the driver fill this out, -and provide a default instead. - -Tested on m25p80.c and Medatek's MT8173 SPI NOR flash driver. - -Signed-off-by: Brian Norris ---- - drivers/mtd/spi-nor/spi-nor.c | 37 +++++++++++++++++++++++++++++++++---- - include/linux/mtd/spi-nor.h | 3 ++- - 2 files changed, 35 insertions(+), 5 deletions(-) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -38,6 +38,7 @@ - #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) - - #define SPI_NOR_MAX_ID_LEN 6 -+#define SPI_NOR_MAX_ADDR_WIDTH 4 - - struct flash_info { - char *name; -@@ -314,6 +315,29 @@ static void spi_nor_unlock_and_unprep(st - } - - /* -+ * Initiate the erasure of a single sector -+ */ -+static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) -+{ -+ u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; -+ int i; -+ -+ if (nor->erase) -+ return nor->erase(nor, addr); -+ -+ /* -+ * Default implementation, if driver doesn't have a specialized HW -+ * control -+ */ -+ for (i = nor->addr_width - 1; i >= 0; i--) { -+ buf[i] = addr & 0xff; -+ addr >>= 8; -+ } -+ -+ return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); -+} -+ -+/* - * Erase an address range on the nor chip. The address range may extend - * one or more erase sectors. Return an error is there is a problem erasing. - */ -@@ -372,10 +396,9 @@ static int spi_nor_erase(struct mtd_info - while (len) { - write_enable(nor); - -- if (nor->erase(nor, addr)) { -- ret = -EIO; -+ ret = spi_nor_erase_sector(nor, addr); -+ if (ret) - goto erase_err; -- } - - addr += mtd->erasesize; - len -= mtd->erasesize; -@@ -1107,7 +1130,7 @@ static int set_quad_mode(struct spi_nor - static int spi_nor_check(struct spi_nor *nor) - { - if (!nor->dev || !nor->read || !nor->write || -- !nor->read_reg || !nor->write_reg || !nor->erase) { -+ !nor->read_reg || !nor->write_reg) { - pr_err("spi-nor: please fill all the necessary fields!\n"); - return -EINVAL; - } -@@ -1310,6 +1333,12 @@ int spi_nor_scan(struct spi_nor *nor, co - nor->addr_width = 3; - } - -+ if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { -+ dev_err(dev, "address width is too large: %u\n", -+ nor->addr_width); -+ return -EINVAL; -+ } -+ - nor->read_dummy = spi_nor_read_dummy_cycles(nor); - - dev_info(dev, "%s (%lld Kbytes)\n", info->name, ---- a/include/linux/mtd/spi-nor.h -+++ b/include/linux/mtd/spi-nor.h -@@ -142,7 +142,8 @@ enum spi_nor_option_flags { - * @read: [DRIVER-SPECIFIC] read data from the SPI NOR - * @write: [DRIVER-SPECIFIC] write data to the SPI NOR - * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR -- * at the offset @offs -+ * at the offset @offs; if not provided by the driver, -+ * spi-nor will send the erase opcode via write_reg() - * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR - * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR - * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is diff --git a/target/linux/layerscape/patches-4.4/1083-mtd-spi-nor-Fix-error-message-with-unrecognized-JEDE.patch b/target/linux/layerscape/patches-4.4/1083-mtd-spi-nor-Fix-error-message-with-unrecognized-JEDE.patch deleted file mode 100644 index 6ebbdb417d..0000000000 --- a/target/linux/layerscape/patches-4.4/1083-mtd-spi-nor-Fix-error-message-with-unrecognized-JEDE.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 30e609daed95664824e95344e85c7eaedd1bfcf3 Mon Sep 17 00:00:00 2001 -From: Ricardo Ribalda -Date: Mon, 30 Nov 2015 20:41:17 +0100 -Subject: [PATCH 083/113] mtd: spi-nor: Fix error message with unrecognized - JEDEC - -The error message was: - -m25p80 spi32766.0: unrecognized JEDEC id bytes: 00, 0, 0 - -The new error message: - -m25p80 spi32766.0: unrecognized JEDEC id bytes: 00, 00, 00 - -Signed-off-by: Ricardo Ribalda Delgado -Signed-off-by: Brian Norris ---- - drivers/mtd/spi-nor/spi-nor.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -896,7 +896,7 @@ static const struct flash_info *spi_nor_ - return &spi_nor_ids[tmp]; - } - } -- dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n", -+ dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", - id[0], id[1], id[2]); - return ERR_PTR(-ENODEV); - } diff --git a/target/linux/layerscape/patches-4.4/1084-mtd-spi-nor-fix-error-handling-in-spi_nor_erase.patch b/target/linux/layerscape/patches-4.4/1084-mtd-spi-nor-fix-error-handling-in-spi_nor_erase.patch deleted file mode 100644 index 53501315e9..0000000000 --- a/target/linux/layerscape/patches-4.4/1084-mtd-spi-nor-fix-error-handling-in-spi_nor_erase.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 9e473594776da97245049019f1d1e9608ff1214a Mon Sep 17 00:00:00 2001 -From: Heiner Kallweit -Date: Tue, 17 Nov 2015 20:18:54 +0100 -Subject: [PATCH 084/113] mtd: spi-nor: fix error handling in spi_nor_erase - -The documenting comment of mtd_erase in mtdcore.c states: -Device drivers are supposed to call instr->callback() whenever -the operation completes, even if it completes with a failure. - -Currently the callback isn't called in case of failure. Fix this. - -Signed-off-by: Heiner Kallweit -Signed-off-by: Brian Norris ---- - drivers/mtd/spi-nor/spi-nor.c | 8 ++------ - 1 file changed, 2 insertions(+), 6 deletions(-) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -411,17 +411,13 @@ static int spi_nor_erase(struct mtd_info - - write_disable(nor); - -+erase_err: - spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); - -- instr->state = MTD_ERASE_DONE; -+ instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE; - mtd_erase_callback(instr); - - return ret; -- --erase_err: -- spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); -- instr->state = MTD_ERASE_FAILED; -- return ret; - } - - static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, diff --git a/target/linux/layerscape/patches-4.4/1085-mtd-spi-nor-Check-the-return-value-from-read_sr.patch b/target/linux/layerscape/patches-4.4/1085-mtd-spi-nor-Check-the-return-value-from-read_sr.patch deleted file mode 100644 index cca7ac1797..0000000000 --- a/target/linux/layerscape/patches-4.4/1085-mtd-spi-nor-Check-the-return-value-from-read_sr.patch +++ /dev/null @@ -1,58 +0,0 @@ -From d05c68e35f42a46b352d2a4bdaef9954c946e20a Mon Sep 17 00:00:00 2001 -From: Fabio Estevam -Date: Fri, 20 Nov 2015 16:26:11 -0200 -Subject: [PATCH 085/113] mtd: spi-nor: Check the return value from read_sr() - -[context adjustment] - -We should better check the return value from read_sr() and -propagate it in the case of error. - -Signed-off-by: Fabio Estevam -Signed-off-by: Brian Norris -Integrated-by: Jiang Yutang ---- - drivers/mtd/spi-nor/spi-nor.c | 10 ++++++++-- - 1 file changed, 8 insertions(+), 2 deletions(-) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -479,11 +479,13 @@ static int stm_is_locked_sr(struct spi_n - static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) - { - struct mtd_info *mtd = &nor->mtd; -- u8 status_old, status_new; -+ int status_old, status_new; - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; - u8 shift = ffs(mask) - 1, pow, val; - - status_old = read_sr(nor); -+ if (status_old < 0) -+ return status_old; - - /* SPI NOR always locks to the end */ - if (ofs + len != mtd->size) { -@@ -529,11 +531,13 @@ static int stm_lock(struct spi_nor *nor, - static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) - { - struct mtd_info *mtd = &nor->mtd; -- uint8_t status_old, status_new; -+ int status_old, status_new; - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; - u8 shift = ffs(mask) - 1, pow, val; - - status_old = read_sr(nor); -+ if (status_old < 0) -+ return status_old; - - /* Cannot unlock; would unlock larger region than requested */ - if (stm_is_locked_sr(nor, ofs - mtd->erasesize, mtd->erasesize, -@@ -1038,6 +1042,8 @@ static int macronix_quad_enable(struct s - int ret, val; - - val = read_sr(nor); -+ if (val < 0) -+ return val; - write_enable(nor); - - write_sr(nor, val | SR_QUAD_EN_MX); diff --git a/target/linux/layerscape/patches-4.4/1086-mtd-spi-nor-wait-until-lock-unlock-operations-are-re.patch b/target/linux/layerscape/patches-4.4/1086-mtd-spi-nor-wait-until-lock-unlock-operations-are-re.patch deleted file mode 100644 index 47f2c8326b..0000000000 --- a/target/linux/layerscape/patches-4.4/1086-mtd-spi-nor-wait-until-lock-unlock-operations-are-re.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 3a06c61b48fbc23046928275e37a693e1055ae74 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ezequiel=20Garc=C3=ADa?= -Date: Mon, 28 Dec 2015 17:54:51 -0300 -Subject: [PATCH 086/113] mtd: spi-nor: wait until lock/unlock operations are - ready - -On Micron and Numonyx devices, the status register write command -(WRSR), raises a work-in-progress bit (WIP) on the status register. -The datasheets for these devices specify that while the status -register write is in progress, the status register WIP bit can still -be read to check the end of the operation. - -This commit adds a wait_till_ready call on lock/unlock operations, -which is required for Micron and Numonyx but should be harmless for -others. This is needed to prevent applications from issuing erase or -program operations before the unlock operation is completed. - -Reported-by: Stas Sergeev -Signed-off-by: Ezequiel Garcia -Signed-off-by: Brian Norris ---- - drivers/mtd/spi-nor/spi-nor.c | 12 ++++++++++-- - 1 file changed, 10 insertions(+), 2 deletions(-) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -482,6 +482,7 @@ static int stm_lock(struct spi_nor *nor, - int status_old, status_new; - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; - u8 shift = ffs(mask) - 1, pow, val; -+ int ret; - - status_old = read_sr(nor); - if (status_old < 0) -@@ -520,7 +521,10 @@ static int stm_lock(struct spi_nor *nor, - return -EINVAL; - - write_enable(nor); -- return write_sr(nor, status_new); -+ ret = write_sr(nor, status_new); -+ if (ret) -+ return ret; -+ return spi_nor_wait_till_ready(nor); - } - - /* -@@ -534,6 +538,7 @@ static int stm_unlock(struct spi_nor *no - int status_old, status_new; - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; - u8 shift = ffs(mask) - 1, pow, val; -+ int ret; - - status_old = read_sr(nor); - if (status_old < 0) -@@ -570,7 +575,10 @@ static int stm_unlock(struct spi_nor *no - return -EINVAL; - - write_enable(nor); -- return write_sr(nor, status_new); -+ ret = write_sr(nor, status_new); -+ if (ret) -+ return ret; -+ return spi_nor_wait_till_ready(nor); - } - - /* diff --git a/target/linux/layerscape/patches-4.4/1087-mtd-spi-nor-fsl-quadspi-add-big-endian-support.patch b/target/linux/layerscape/patches-4.4/1087-mtd-spi-nor-fsl-quadspi-add-big-endian-support.patch deleted file mode 100644 index 9ceddd6cca..0000000000 --- a/target/linux/layerscape/patches-4.4/1087-mtd-spi-nor-fsl-quadspi-add-big-endian-support.patch +++ /dev/null @@ -1,400 +0,0 @@ -From c58b398221d88ac0db29c3bb7522a4f48dfa102c Mon Sep 17 00:00:00 2001 -From: Yuan Yao -Date: Tue, 17 Nov 2015 16:13:47 +0800 -Subject: [PATCH 087/113] mtd: spi-nor: fsl-quadspi: add big-endian support - -Add R/W functions for big- or little-endian registers: -The qSPI controller's endian is independent of the CPU core's endian. -So far, the qSPI have two versions for big-endian and little-endian. - -Signed-off-by: Yuan Yao -Acked-by: Han xu ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 157 +++++++++++++++++++++++-------------- - 1 file changed, 97 insertions(+), 60 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -275,6 +275,7 @@ struct fsl_qspi { - u32 clk_rate; - unsigned int chip_base_addr; /* We may support two chips. */ - bool has_second_chip; -+ bool big_endian; - struct mutex lock; - struct pm_qos_request pm_qos_req; - }; -@@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode - } - - /* -+ * R/W functions for big- or little-endian registers: -+ * The qSPI controller's endian is independent of the CPU core's endian. -+ * So far, although the CPU core is little-endian but the qSPI have two -+ * versions for big-endian and little-endian. -+ */ -+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr) -+{ -+ if (q->big_endian) -+ iowrite32be(val, addr); -+ else -+ iowrite32(val, addr); -+} -+ -+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) -+{ -+ if (q->big_endian) -+ return ioread32be(addr); -+ else -+ return ioread32(addr); -+} -+ -+/* - * An IC bug makes us to re-arrange the 32-bit data. - * The following chips, such as IMX6SLX, have fixed this bug. - */ -@@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(s - - static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q) - { -- writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); -- writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); -+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); -+ qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); - } - - static inline void fsl_qspi_lock_lut(struct fsl_qspi *q) - { -- writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); -- writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); -+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); -+ qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); - } - - static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id) -@@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler( - u32 reg; - - /* clear interrupt */ -- reg = readl(q->iobase + QUADSPI_FR); -- writel(reg, q->iobase + QUADSPI_FR); -+ reg = qspi_readl(q, q->iobase + QUADSPI_FR); -+ qspi_writel(q, reg, q->iobase + QUADSPI_FR); - - if (reg & QUADSPI_FR_TFF_MASK) - complete(&q->c); -@@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl - - /* Clear all the LUT table */ - for (i = 0; i < QUADSPI_LUT_NUM; i++) -- writel(0, base + QUADSPI_LUT_BASE + i * 4); -+ qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4); - - /* Quad Read */ - lut_base = SEQID_QUAD_READ * 4; -@@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl - dummy = 8; - } - -- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), -+ qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); -- writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo), -+ qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo), - base + QUADSPI_LUT(lut_base + 1)); - - /* Write enable */ - lut_base = SEQID_WREN * 4; -- writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base)); -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN), -+ base + QUADSPI_LUT(lut_base)); - - /* Page Program */ - lut_base = SEQID_PP * 4; -@@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl - addrlen = ADDR32BIT; - } - -- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), -+ qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); -- writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1)); -+ qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0), -+ base + QUADSPI_LUT(lut_base + 1)); - - /* Read Status */ - lut_base = SEQID_RDSR * 4; -- writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1), -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) | -+ LUT1(FSL_READ, PAD1, 0x1), - base + QUADSPI_LUT(lut_base)); - - /* Erase a sector */ -@@ -400,40 +426,46 @@ static void fsl_qspi_init_lut(struct fsl - cmd = q->nor[0].erase_opcode; - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT; - -- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), -+ qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); - - /* Erase the whole chip */ - lut_base = SEQID_CHIP_ERASE * 4; -- writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE), -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE), - base + QUADSPI_LUT(lut_base)); - - /* READ ID */ - lut_base = SEQID_RDID * 4; -- writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(FSL_READ, PAD1, 0x8), -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) | -+ LUT1(FSL_READ, PAD1, 0x8), - base + QUADSPI_LUT(lut_base)); - - /* Write Register */ - lut_base = SEQID_WRSR * 4; -- writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(FSL_WRITE, PAD1, 0x2), -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) | -+ LUT1(FSL_WRITE, PAD1, 0x2), - base + QUADSPI_LUT(lut_base)); - - /* Read Configuration Register */ - lut_base = SEQID_RDCR * 4; -- writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(FSL_READ, PAD1, 0x1), -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) | -+ LUT1(FSL_READ, PAD1, 0x1), - base + QUADSPI_LUT(lut_base)); - - /* Write disable */ - lut_base = SEQID_WRDI * 4; -- writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base)); -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI), -+ base + QUADSPI_LUT(lut_base)); - - /* Enter 4 Byte Mode (Micron) */ - lut_base = SEQID_EN4B * 4; -- writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base)); -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B), -+ base + QUADSPI_LUT(lut_base)); - - /* Enter 4 Byte Mode (Spansion) */ - lut_base = SEQID_BRWR * 4; -- writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base)); -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR), -+ base + QUADSPI_LUT(lut_base)); - - fsl_qspi_lock_lut(q); - } -@@ -488,15 +520,16 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c - q->chip_base_addr, addr, len, cmd); - - /* save the reg */ -- reg = readl(base + QUADSPI_MCR); -+ reg = qspi_readl(q, base + QUADSPI_MCR); - -- writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR); -- writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS, -+ qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr, -+ base + QUADSPI_SFAR); -+ qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS, - base + QUADSPI_RBCT); -- writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR); -+ qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR); - - do { -- reg2 = readl(base + QUADSPI_SR); -+ reg2 = qspi_readl(q, base + QUADSPI_SR); - if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) { - udelay(1); - dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2); -@@ -507,21 +540,22 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c - - /* trigger the LUT now */ - seqid = fsl_qspi_get_seqid(q, cmd); -- writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR); -+ qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, -+ base + QUADSPI_IPCR); - - /* Wait for the interrupt. */ - if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) { - dev_err(q->dev, - "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n", -- cmd, addr, readl(base + QUADSPI_FR), -- readl(base + QUADSPI_SR)); -+ cmd, addr, qspi_readl(q, base + QUADSPI_FR), -+ qspi_readl(q, base + QUADSPI_SR)); - err = -ETIMEDOUT; - } else { - err = 0; - } - - /* restore the MCR */ -- writel(reg, base + QUADSPI_MCR); -+ qspi_writel(q, reg, base + QUADSPI_MCR); - - return err; - } -@@ -533,7 +567,7 @@ static void fsl_qspi_read_data(struct fs - int i = 0; - - while (len > 0) { -- tmp = readl(q->iobase + QUADSPI_RBDR + i * 4); -+ tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4); - tmp = fsl_qspi_endian_xchg(q, tmp); - dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n", - q->chip_base_addr, tmp); -@@ -561,9 +595,9 @@ static inline void fsl_qspi_invalid(stru - { - u32 reg; - -- reg = readl(q->iobase + QUADSPI_MCR); -+ reg = qspi_readl(q, q->iobase + QUADSPI_MCR); - reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK; -- writel(reg, q->iobase + QUADSPI_MCR); -+ qspi_writel(q, reg, q->iobase + QUADSPI_MCR); - - /* - * The minimum delay : 1 AHB + 2 SFCK clocks. -@@ -572,7 +606,7 @@ static inline void fsl_qspi_invalid(stru - udelay(1); - - reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK); -- writel(reg, q->iobase + QUADSPI_MCR); -+ qspi_writel(q, reg, q->iobase + QUADSPI_MCR); - } - - static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor, -@@ -586,20 +620,20 @@ static int fsl_qspi_nor_write(struct fsl - q->chip_base_addr, to, count); - - /* clear the TX FIFO. */ -- tmp = readl(q->iobase + QUADSPI_MCR); -- writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR); -+ tmp = qspi_readl(q, q->iobase + QUADSPI_MCR); -+ qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR); - - /* fill the TX data to the FIFO */ - for (j = 0, i = ((count + 3) / 4); j < i; j++) { - tmp = fsl_qspi_endian_xchg(q, *txbuf); -- writel(tmp, q->iobase + QUADSPI_TBDR); -+ qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR); - txbuf++; - } - - /* fill the TXFIFO upto 16 bytes for i.MX7d */ - if (needs_fill_txfifo(q)) - for (; i < 4; i++) -- writel(tmp, q->iobase + QUADSPI_TBDR); -+ qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR); - - /* Trigger it */ - ret = fsl_qspi_runcmd(q, opcode, to, count); -@@ -615,10 +649,10 @@ static void fsl_qspi_set_map_addr(struct - int nor_size = q->nor_size; - void __iomem *base = q->iobase; - -- writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD); -- writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD); -- writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD); -- writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD); -+ qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD); -+ qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD); -+ qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD); -+ qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD); - } - - /* -@@ -640,24 +674,26 @@ static void fsl_qspi_init_abh_read(struc - int seqid; - - /* AHB configuration for access buffer 0/1/2 .*/ -- writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR); -- writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR); -- writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR); -+ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR); -+ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR); -+ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR); - /* - * Set ADATSZ with the maximum AHB buffer size to improve the - * read performance. - */ -- writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8) -- << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR); -+ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | -+ ((q->devtype_data->ahb_buf_size / 8) -+ << QUADSPI_BUF3CR_ADATSZ_SHIFT), -+ base + QUADSPI_BUF3CR); - - /* We only use the buffer3 */ -- writel(0, base + QUADSPI_BUF0IND); -- writel(0, base + QUADSPI_BUF1IND); -- writel(0, base + QUADSPI_BUF2IND); -+ qspi_writel(q, 0, base + QUADSPI_BUF0IND); -+ qspi_writel(q, 0, base + QUADSPI_BUF1IND); -+ qspi_writel(q, 0, base + QUADSPI_BUF2IND); - - /* Set the default lut sequence for AHB Read. */ - seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode); -- writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT, -+ qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT, - q->iobase + QUADSPI_BFGENCR); - } - -@@ -713,7 +749,7 @@ static int fsl_qspi_nor_setup(struct fsl - return ret; - - /* Reset the module */ -- writel(QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK, -+ qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK, - base + QUADSPI_MCR); - udelay(1); - -@@ -721,24 +757,24 @@ static int fsl_qspi_nor_setup(struct fsl - fsl_qspi_init_lut(q); - - /* Disable the module */ -- writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK, -+ qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK, - base + QUADSPI_MCR); - -- reg = readl(base + QUADSPI_SMPR); -- writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK -+ reg = qspi_readl(q, base + QUADSPI_SMPR); -+ qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK - | QUADSPI_SMPR_FSPHS_MASK - | QUADSPI_SMPR_HSENA_MASK - | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR); - - /* Enable the module */ -- writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK, -+ qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK, - base + QUADSPI_MCR); - - /* clear all interrupt status */ -- writel(0xffffffff, q->iobase + QUADSPI_FR); -+ qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR); - - /* enable the interrupt */ -- writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER); -+ qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER); - - return 0; - } -@@ -954,6 +990,7 @@ static int fsl_qspi_probe(struct platfor - if (IS_ERR(q->iobase)) - return PTR_ERR(q->iobase); - -+ q->big_endian = of_property_read_bool(np, "big-endian"); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "QuadSPI-memory"); - if (!devm_request_mem_region(dev, res->start, resource_size(res), -@@ -1101,8 +1138,8 @@ static int fsl_qspi_remove(struct platfo - } - - /* disable the hardware */ -- writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); -- writel(0x0, q->iobase + QUADSPI_RSER); -+ qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); -+ qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER); - - mutex_destroy(&q->lock); - diff --git a/target/linux/layerscape/patches-4.4/1088-mtd-spi-nor-fsl-quadspi-add-support-for-ls1021a.patch b/target/linux/layerscape/patches-4.4/1088-mtd-spi-nor-fsl-quadspi-add-support-for-ls1021a.patch deleted file mode 100644 index a5782ffc1a..0000000000 --- a/target/linux/layerscape/patches-4.4/1088-mtd-spi-nor-fsl-quadspi-add-support-for-ls1021a.patch +++ /dev/null @@ -1,63 +0,0 @@ -From da44c1517526822e73642fc71b034de8fc7d2b43 Mon Sep 17 00:00:00 2001 -From: Yuan Yao -Date: Tue, 17 Nov 2015 16:44:45 +0800 -Subject: [PATCH 088/113] mtd: spi-nor: fsl-quadspi: add support for ls1021a - -[context adjustment] - -LS1021a also support Freescale Quad SPI controller. -Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI -selectable for LS1021A SOC hardwares. - -Signed-off-by: Yuan Yao -Acked-by: Han xu -Integrated-by: Jiang Yutang ---- - drivers/mtd/spi-nor/Kconfig | 2 +- - drivers/mtd/spi-nor/fsl-quadspi.c | 10 ++++++++++ - 2 files changed, 11 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/spi-nor/Kconfig -+++ b/drivers/mtd/spi-nor/Kconfig -@@ -23,7 +23,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS - - config SPI_FSL_QUADSPI - tristate "Freescale Quad SPI controller" -- depends on ARCH_MXC || COMPILE_TEST -+ depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST - depends on HAS_IOMEM - help - This enables support for the Quad SPI controller in master mode. ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -213,6 +213,7 @@ enum fsl_qspi_devtype { - FSL_QUADSPI_IMX6SX, - FSL_QUADSPI_IMX7D, - FSL_QUADSPI_IMX6UL, -+ FSL_QUADSPI_LS1021A, - }; - - struct fsl_qspi_devtype_data { -@@ -258,6 +259,14 @@ static struct fsl_qspi_devtype_data imx6 - | QUADSPI_QUIRK_4X_INT_CLK, - }; - -+static struct fsl_qspi_devtype_data ls1021a_data = { -+ .devtype = FSL_QUADSPI_LS1021A, -+ .rxfifo = 128, -+ .txfifo = 64, -+ .ahb_buf_size = 1024, -+ .driver_data = 0, -+}; -+ - #define FSL_QSPI_MAX_CHIP 4 - struct fsl_qspi { - struct spi_nor nor[FSL_QSPI_MAX_CHIP]; -@@ -812,6 +821,7 @@ static const struct of_device_id fsl_qsp - { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, }, - { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, }, - { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, }, -+ { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids); diff --git a/target/linux/layerscape/patches-4.4/1089-mtd-spi-nor-fsl-quadspi-add-support-for-layerscape.patch b/target/linux/layerscape/patches-4.4/1089-mtd-spi-nor-fsl-quadspi-add-support-for-layerscape.patch deleted file mode 100644 index bd959df11d..0000000000 --- a/target/linux/layerscape/patches-4.4/1089-mtd-spi-nor-fsl-quadspi-add-support-for-layerscape.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 9c6153130081ef2c109e2a243a598f2bc0dc6413 Mon Sep 17 00:00:00 2001 -From: Yuan Yao -Date: Tue, 17 Nov 2015 17:06:47 +0800 -Subject: [PATCH 089/113] mtd: spi-nor: fsl-quadspi: add support for - layerscape - -[context adjustment] - -LS1043a and LS2080A in the Layerscape family also support Freescale Quad -SPI, make Quad SPI selectable for these hardwares. - -Signed-off-by: Yuan Yao -Integrated-by: Jiang Yutang ---- - drivers/mtd/spi-nor/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mtd/spi-nor/Kconfig -+++ b/drivers/mtd/spi-nor/Kconfig -@@ -23,7 +23,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS - - config SPI_FSL_QUADSPI - tristate "Freescale Quad SPI controller" -- depends on ARCH_MXC || SOC_LS1021A || COMPILE_TEST -+ depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST - depends on HAS_IOMEM - help - This enables support for the Quad SPI controller in master mode. diff --git a/target/linux/layerscape/patches-4.4/1090-mtd-spi-nor-Add-SPI-NOR-layer-PM-support.patch b/target/linux/layerscape/patches-4.4/1090-mtd-spi-nor-Add-SPI-NOR-layer-PM-support.patch deleted file mode 100644 index de3d2d5456..0000000000 --- a/target/linux/layerscape/patches-4.4/1090-mtd-spi-nor-Add-SPI-NOR-layer-PM-support.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 2c5a3db21926e9ebfd7a32e3c36a3256ed84903c Mon Sep 17 00:00:00 2001 -From: Hou Zhiqiang -Date: Thu, 19 Nov 2015 20:25:24 +0800 -Subject: [PATCH 090/113] mtd: spi-nor: Add SPI NOR layer PM support - -[context adjustment] - -Add the Power Management API in SPI NOR framework. -The Power Management system will turn off power supply to SPI flash -when system suspending, and then the SPI flash will be in the reset -state after system resuming. As a result, the status&configurations -of SPI flash driver will mismatch with its current hardware state. -So reinitialize SPI flash to make sure it is resumed to the correct -state. -And the SPI NOR layer just do common configuration depending on the -records in structure spi_nor. - -Signed-off-by: Hou Zhiqiang -Integrated-by: Jiang Yutang ---- - drivers/mtd/spi-nor/spi-nor.c | 74 ++++++++++++++++++++++++++++++++++------- - include/linux/mtd/spi-nor.h | 9 +++++ - 2 files changed, 71 insertions(+), 12 deletions(-) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -1148,6 +1148,26 @@ static int spi_nor_check(struct spi_nor - return 0; - } - -+/* -+ * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up -+ * with the software protection bits set -+ */ -+static int spi_nor_unprotect_on_powerup(struct spi_nor *nor) -+{ -+ const struct flash_info *info = NULL; -+ int ret = 0; -+ -+ info = spi_nor_read_id(nor); -+ if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || -+ JEDEC_MFR(info) == SNOR_MFR_INTEL || -+ JEDEC_MFR(info) == SNOR_MFR_SST) { -+ write_enable(nor); -+ ret = write_sr(nor, 0); -+ } -+ -+ return ret; -+} -+ - int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) - { - const struct flash_info *info = NULL; -@@ -1195,19 +1215,9 @@ int spi_nor_scan(struct spi_nor *nor, co - - mutex_init(&nor->lock); - -- /* -- * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up -- * with the software protection bits set -- */ -- -- if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || -- JEDEC_MFR(info) == SNOR_MFR_INTEL || -- JEDEC_MFR(info) == SNOR_MFR_MACRONIX || -- JEDEC_MFR(info) == SNOR_MFR_SST || -- info->flags & SPI_NOR_HAS_LOCK) { -- write_enable(nor); -- write_sr(nor, 0); -- } -+ ret = spi_nor_unprotect_on_powerup(nor); -+ if (ret) -+ return ret; - - if (!mtd->name) - mtd->name = dev_name(dev); -@@ -1374,6 +1384,45 @@ int spi_nor_scan(struct spi_nor *nor, co - } - EXPORT_SYMBOL_GPL(spi_nor_scan); - -+static int spi_nor_hw_reinit(struct spi_nor *nor) -+{ -+ const struct flash_info *info = NULL; -+ struct device *dev = nor->dev; -+ int ret; -+ -+ info = spi_nor_read_id(nor); -+ -+ ret = spi_nor_unprotect_on_powerup(nor); -+ if (ret) -+ return ret; -+ -+ if (nor->flash_read == SPI_NOR_QUAD) { -+ ret = set_quad_mode(nor, info); -+ if (ret) { -+ dev_err(dev, "quad mode not supported\n"); -+ return ret; -+ } -+ } -+ -+ if (nor->addr_width == 4 && -+ JEDEC_MFR(info) != SNOR_MFR_SPANSION) -+ set_4byte(nor, info, 1); -+ -+ return 0; -+} -+ -+int spi_nor_suspend(struct spi_nor *nor) -+{ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(spi_nor_suspend); -+ -+int spi_nor_resume(struct spi_nor *nor) -+{ -+ return spi_nor_hw_reinit(nor); -+} -+EXPORT_SYMBOL_GPL(spi_nor_resume); -+ - static const struct flash_info *spi_nor_match_id(const char *name) - { - const struct flash_info *id = spi_nor_ids; ---- a/include/linux/mtd/spi-nor.h -+++ b/include/linux/mtd/spi-nor.h -@@ -210,4 +210,13 @@ static inline struct device_node *spi_no - */ - int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode); - -+/** -+ * spi_nor_suspend/resume() - the SPI NOR layer PM API -+ * @nor: the spi_nor structure -+ * -+ * Return: 0 for success, others for failure. -+ */ -+int spi_nor_suspend(struct spi_nor *nor); -+int spi_nor_resume(struct spi_nor *nor); -+ - #endif diff --git a/target/linux/layerscape/patches-4.4/1091-mtd-spi-nor-change-return-value-of-read-write.patch b/target/linux/layerscape/patches-4.4/1091-mtd-spi-nor-change-return-value-of-read-write.patch deleted file mode 100644 index faa806e701..0000000000 --- a/target/linux/layerscape/patches-4.4/1091-mtd-spi-nor-change-return-value-of-read-write.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 0a8079b232e9188ba267e37e20f192bed6c2b29b Mon Sep 17 00:00:00 2001 -From: Michal Suchanek -Date: Wed, 2 Dec 2015 10:38:19 +0000 -Subject: [PATCH 091/113] mtd: spi-nor: change return value of read/write - -Change the return value of spi-nor device read and write methods to -allow returning amount of data transferred and errors as -read(2)/write(2) does. - -Signed-off-by: Michal Suchanek -Signed-off-by: Hou Zhiqiang ---- - drivers/mtd/devices/m25p80.c | 5 +++-- - drivers/mtd/spi-nor/fsl-quadspi.c | 5 +++-- - include/linux/mtd/spi-nor.h | 4 ++-- - 3 files changed, 8 insertions(+), 6 deletions(-) - ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -73,7 +73,7 @@ static int m25p80_write_reg(struct spi_n - return spi_write(spi, flash->command, len + 1); - } - --static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len, -+static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len, - size_t *retlen, const u_char *buf) - { - struct m25p *flash = nor->priv; -@@ -101,6 +101,7 @@ static void m25p80_write(struct spi_nor - spi_sync(spi, &m); - - *retlen += m.actual_length - cmd_sz; -+ return 0; - } - - static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor) -@@ -119,7 +120,7 @@ static inline unsigned int m25p80_rx_nbi - * Read an address range from the nor chip. The address range - * may be any size provided it is within the physical boundaries. - */ --static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len, -+static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len, - size_t *retlen, u_char *buf) - { - struct m25p *flash = nor->priv; ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -868,7 +868,7 @@ static int fsl_qspi_write_reg(struct spi - return ret; - } - --static void fsl_qspi_write(struct spi_nor *nor, loff_t to, -+static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to, - size_t len, size_t *retlen, const u_char *buf) - { - struct fsl_qspi *q = nor->priv; -@@ -878,9 +878,10 @@ static void fsl_qspi_write(struct spi_no - - /* invalid the data in the AHB buffer. */ - fsl_qspi_invalid(q); -+ return 0; - } - --static int fsl_qspi_read(struct spi_nor *nor, loff_t from, -+static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from, - size_t len, size_t *retlen, u_char *buf) - { - struct fsl_qspi *q = nor->priv; ---- a/include/linux/mtd/spi-nor.h -+++ b/include/linux/mtd/spi-nor.h -@@ -170,9 +170,9 @@ struct spi_nor { - int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); - int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); - -- int (*read)(struct spi_nor *nor, loff_t from, -+ ssize_t (*read)(struct spi_nor *nor, loff_t from, - size_t len, size_t *retlen, u_char *read_buf); -- void (*write)(struct spi_nor *nor, loff_t to, -+ ssize_t (*write)(struct spi_nor *nor, loff_t to, - size_t len, size_t *retlen, const u_char *write_buf); - int (*erase)(struct spi_nor *nor, loff_t offs); - diff --git a/target/linux/layerscape/patches-4.4/1092-mtd-fsl-quadspi-return-amount-of-data-read-written-o.patch b/target/linux/layerscape/patches-4.4/1092-mtd-fsl-quadspi-return-amount-of-data-read-written-o.patch deleted file mode 100644 index 443803693c..0000000000 --- a/target/linux/layerscape/patches-4.4/1092-mtd-fsl-quadspi-return-amount-of-data-read-written-o.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 99768b3062501b05810fb62545279da3a4371ca0 Mon Sep 17 00:00:00 2001 -From: Michal Suchanek -Date: Wed, 2 Dec 2015 10:38:19 +0000 -Subject: [PATCH 092/113] mtd: fsl-quadspi: return amount of data read/written - or error - -Return amount of data read/written or error as read(2)/write(2) does. - -Signed-off-by: Michal Suchanek -Signed-off-by: Hou Zhiqiang ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 18 +++++++++++------- - 1 file changed, 11 insertions(+), 7 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -618,7 +618,7 @@ static inline void fsl_qspi_invalid(stru - qspi_writel(q, reg, q->iobase + QUADSPI_MCR); - } - --static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor, -+static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor, - u8 opcode, unsigned int to, u32 *txbuf, - unsigned count, size_t *retlen) - { -@@ -647,8 +647,11 @@ static int fsl_qspi_nor_write(struct fsl - /* Trigger it */ - ret = fsl_qspi_runcmd(q, opcode, to, count); - -- if (ret == 0 && retlen) -- *retlen += count; -+ if (ret == 0) { -+ if (retlen) -+ *retlen += count; -+ return count; -+ } - - return ret; - } -@@ -860,6 +863,8 @@ static int fsl_qspi_write_reg(struct spi - } else if (len > 0) { - ret = fsl_qspi_nor_write(q, nor, opcode, 0, - (u32 *)buf, len, NULL); -+ if (ret > 0) -+ return 0; - } else { - dev_err(q->dev, "invalid cmd %d\n", opcode); - ret = -EINVAL; -@@ -873,12 +878,12 @@ static ssize_t fsl_qspi_write(struct spi - { - struct fsl_qspi *q = nor->priv; - -- fsl_qspi_nor_write(q, nor, nor->program_opcode, to, -+ ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to, - (u32 *)buf, len, retlen); - - /* invalid the data in the AHB buffer. */ - fsl_qspi_invalid(q); -- return 0; -+ return ret; - } - - static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from, -@@ -924,8 +929,7 @@ static ssize_t fsl_qspi_read(struct spi_ - memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs, - len); - -- *retlen += len; -- return 0; -+ return len; - } - - static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs) diff --git a/target/linux/layerscape/patches-4.4/1093-mtd-spi-nor-check-return-value-from-read-write.patch b/target/linux/layerscape/patches-4.4/1093-mtd-spi-nor-check-return-value-from-read-write.patch deleted file mode 100644 index 85a231515f..0000000000 --- a/target/linux/layerscape/patches-4.4/1093-mtd-spi-nor-check-return-value-from-read-write.patch +++ /dev/null @@ -1,127 +0,0 @@ -From 8527843351169d999995d331bbdad75560ccafb2 Mon Sep 17 00:00:00 2001 -From: Michal Suchanek -Date: Wed, 2 Dec 2015 10:38:20 +0000 -Subject: [PATCH 093/113] mtd: spi-nor: check return value from read/write - -SPI NOR hardware drivers now return useful value from their read/write -functions so check them. - -Signed-off-by: Michal Suchanek -Signed-off-by: Hou Zhiqiang ---- - drivers/mtd/spi-nor/spi-nor.c | 50 +++++++++++++++++++++++++++++------------ - 1 file changed, 36 insertions(+), 14 deletions(-) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -924,7 +924,10 @@ static int spi_nor_read(struct mtd_info - ret = nor->read(nor, from, len, retlen, buf); - - spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ); -- return ret; -+ if (ret < 0) -+ return ret; -+ -+ return 0; - } - - static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, -@@ -950,10 +953,14 @@ static int sst_write(struct mtd_info *mt - nor->program_opcode = SPINOR_OP_BP; - - /* write one byte. */ -- nor->write(nor, to, 1, retlen, buf); -+ ret = nor->write(nor, to, 1, retlen, buf); -+ if (ret < 0) -+ goto sst_write_err; -+ WARN(ret != 1, "While writing 1 byte written %i bytes\n", -+ (int)ret); - ret = spi_nor_wait_till_ready(nor); - if (ret) -- goto time_out; -+ goto sst_write_err; - } - to += actual; - -@@ -962,10 +969,14 @@ static int sst_write(struct mtd_info *mt - nor->program_opcode = SPINOR_OP_AAI_WP; - - /* write two bytes. */ -- nor->write(nor, to, 2, retlen, buf + actual); -+ ret = nor->write(nor, to, 2, retlen, buf + actual); -+ if (ret < 0) -+ goto sst_write_err; -+ WARN(ret != 2, "While writing 2 bytes written %i bytes\n", -+ (int)ret); - ret = spi_nor_wait_till_ready(nor); - if (ret) -- goto time_out; -+ goto sst_write_err; - to += 2; - nor->sst_write_second = true; - } -@@ -974,21 +985,24 @@ static int sst_write(struct mtd_info *mt - write_disable(nor); - ret = spi_nor_wait_till_ready(nor); - if (ret) -- goto time_out; -+ goto sst_write_err; - - /* Write out trailing byte if it exists. */ - if (actual != len) { - write_enable(nor); - - nor->program_opcode = SPINOR_OP_BP; -- nor->write(nor, to, 1, retlen, buf + actual); -- -+ ret = nor->write(nor, to, 1, retlen, buf + actual); -+ if (ret < 0) -+ goto sst_write_err; -+ WARN(ret != 1, "While writing 1 byte written %i bytes\n", -+ (int)ret); - ret = spi_nor_wait_till_ready(nor); - if (ret) -- goto time_out; -+ goto sst_write_err; - write_disable(nor); - } --time_out: -+sst_write_err: - spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); - return ret; - } -@@ -1017,14 +1031,18 @@ static int spi_nor_write(struct mtd_info - - /* do all the bytes fit onto one page? */ - if (page_offset + len <= nor->page_size) { -- nor->write(nor, to, len, retlen, buf); -+ ret = nor->write(nor, to, len, retlen, buf); -+ if (ret < 0) -+ goto write_err; - } else { - /* the size of data remaining on the first page */ - page_size = nor->page_size - page_offset; -- nor->write(nor, to, page_size, retlen, buf); -+ ret = nor->write(nor, to, page_size, retlen, buf); -+ if (ret < 0) -+ goto write_err; - - /* write everything in nor->page_size chunks */ -- for (i = page_size; i < len; i += page_size) { -+ for (i = ret; i < len; ) { - page_size = len - i; - if (page_size > nor->page_size) - page_size = nor->page_size; -@@ -1035,7 +1053,11 @@ static int spi_nor_write(struct mtd_info - - write_enable(nor); - -- nor->write(nor, to + i, page_size, retlen, buf + i); -+ ret = nor->write(nor, to + i, page_size, retlen, -+ buf + i); -+ if (ret < 0) -+ goto write_err; -+ i += ret; - } - } - diff --git a/target/linux/layerscape/patches-4.4/1094-mtd-spi-nor-stop-passing-around-retlen.patch b/target/linux/layerscape/patches-4.4/1094-mtd-spi-nor-stop-passing-around-retlen.patch deleted file mode 100644 index f72bc2c820..0000000000 --- a/target/linux/layerscape/patches-4.4/1094-mtd-spi-nor-stop-passing-around-retlen.patch +++ /dev/null @@ -1,215 +0,0 @@ -From a99477d72b500b48cb3614aad0ce096fe4e3f437 Mon Sep 17 00:00:00 2001 -From: Michal Suchanek -Date: Wed, 2 Dec 2015 10:38:20 +0000 -Subject: [PATCH 094/113] mtd: spi-nor: stop passing around retlen - -[context adjustment] -not apply changes of drivers/mtd/devices/m25p80.c -################# -@@ -74,7 +74,7 @@ static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) - } - - static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len, -- size_t *retlen, const u_char *buf) -+ const u_char *buf) - { - struct m25p *flash = nor->priv; - struct spi_device *spi = flash->spi; -@@ -106,7 +106,6 @@ static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len, - ret = m.actual_length - cmd_sz; - if (ret < 0) - return -EIO; -- *retlen += ret; - return ret; - } - -@@ -127,7 +126,7 @@ static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor) - * may be any size provided it is within the physical boundaries. - */ - static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len, -- size_t *retlen, u_char *buf) -+ u_char *buf) - { - struct m25p *flash = nor->priv; - struct spi_device *spi = flash->spi; -@@ -161,7 +160,6 @@ static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len, - ret = m.actual_length - m25p_cmdsz(nor) - dummy; - if (ret < 0) - return -EIO; -- *retlen += ret; - return ret; - } - -################# - -Do not pass retlen to hardware driver read/write functions. Update it in -spi-nor generic driver instead. - -Signed-off-by: Michal Suchanek -Signed-off-by: Hou Zhiqiang -Integrated-by: Jiang Yutang ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 16 ++++++---------- - drivers/mtd/spi-nor/spi-nor.c | 21 +++++++++++++-------- - include/linux/mtd/spi-nor.h | 4 ++-- - 3 files changed, 21 insertions(+), 20 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -620,7 +620,7 @@ static inline void fsl_qspi_invalid(stru - - static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor, - u8 opcode, unsigned int to, u32 *txbuf, -- unsigned count, size_t *retlen) -+ unsigned count) - { - int ret, i, j; - u32 tmp; -@@ -647,11 +647,8 @@ static ssize_t fsl_qspi_nor_write(struct - /* Trigger it */ - ret = fsl_qspi_runcmd(q, opcode, to, count); - -- if (ret == 0) { -- if (retlen) -- *retlen += count; -+ if (ret == 0) - return count; -- } - - return ret; - } -@@ -862,7 +859,7 @@ static int fsl_qspi_write_reg(struct spi - - } else if (len > 0) { - ret = fsl_qspi_nor_write(q, nor, opcode, 0, -- (u32 *)buf, len, NULL); -+ (u32 *)buf, len); - if (ret > 0) - return 0; - } else { -@@ -874,12 +871,11 @@ static int fsl_qspi_write_reg(struct spi - } - - static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to, -- size_t len, size_t *retlen, const u_char *buf) -+ size_t len, const u_char *buf) - { - struct fsl_qspi *q = nor->priv; -- - ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to, -- (u32 *)buf, len, retlen); -+ (u32 *)buf, len); - - /* invalid the data in the AHB buffer. */ - fsl_qspi_invalid(q); -@@ -887,7 +883,7 @@ static ssize_t fsl_qspi_write(struct spi - } - - static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from, -- size_t len, size_t *retlen, u_char *buf) -+ size_t len, u_char *buf) - { - struct fsl_qspi *q = nor->priv; - u8 cmd = nor->read_opcode; ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -921,12 +921,13 @@ static int spi_nor_read(struct mtd_info - if (ret) - return ret; - -- ret = nor->read(nor, from, len, retlen, buf); -+ ret = nor->read(nor, from, len, buf); - - spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ); - if (ret < 0) - return ret; - -+ *retlen += ret; - return 0; - } - -@@ -953,7 +954,7 @@ static int sst_write(struct mtd_info *mt - nor->program_opcode = SPINOR_OP_BP; - - /* write one byte. */ -- ret = nor->write(nor, to, 1, retlen, buf); -+ ret = nor->write(nor, to, 1, buf); - if (ret < 0) - goto sst_write_err; - WARN(ret != 1, "While writing 1 byte written %i bytes\n", -@@ -969,7 +970,7 @@ static int sst_write(struct mtd_info *mt - nor->program_opcode = SPINOR_OP_AAI_WP; - - /* write two bytes. */ -- ret = nor->write(nor, to, 2, retlen, buf + actual); -+ ret = nor->write(nor, to, 2, buf + actual); - if (ret < 0) - goto sst_write_err; - WARN(ret != 2, "While writing 2 bytes written %i bytes\n", -@@ -992,7 +993,7 @@ static int sst_write(struct mtd_info *mt - write_enable(nor); - - nor->program_opcode = SPINOR_OP_BP; -- ret = nor->write(nor, to, 1, retlen, buf + actual); -+ ret = nor->write(nor, to, 1, buf + actual); - if (ret < 0) - goto sst_write_err; - WARN(ret != 1, "While writing 1 byte written %i bytes\n", -@@ -1001,8 +1002,10 @@ static int sst_write(struct mtd_info *mt - if (ret) - goto sst_write_err; - write_disable(nor); -+ actual += 1; - } - sst_write_err: -+ *retlen += actual; - spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); - return ret; - } -@@ -1031,15 +1034,17 @@ static int spi_nor_write(struct mtd_info - - /* do all the bytes fit onto one page? */ - if (page_offset + len <= nor->page_size) { -- ret = nor->write(nor, to, len, retlen, buf); -+ ret = nor->write(nor, to, len, buf); - if (ret < 0) - goto write_err; -+ *retlen += ret; - } else { - /* the size of data remaining on the first page */ - page_size = nor->page_size - page_offset; -- ret = nor->write(nor, to, page_size, retlen, buf); -+ ret = nor->write(nor, to, page_size, buf); - if (ret < 0) - goto write_err; -+ *retlen += ret; - - /* write everything in nor->page_size chunks */ - for (i = ret; i < len; ) { -@@ -1053,10 +1058,10 @@ static int spi_nor_write(struct mtd_info - - write_enable(nor); - -- ret = nor->write(nor, to + i, page_size, retlen, -- buf + i); -+ ret = nor->write(nor, to + i, page_size, buf + i); - if (ret < 0) - goto write_err; -+ *retlen += ret; - i += ret; - } - } ---- a/include/linux/mtd/spi-nor.h -+++ b/include/linux/mtd/spi-nor.h -@@ -171,9 +171,9 @@ struct spi_nor { - int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); - - ssize_t (*read)(struct spi_nor *nor, loff_t from, -- size_t len, size_t *retlen, u_char *read_buf); -+ size_t len, u_char *read_buf); - ssize_t (*write)(struct spi_nor *nor, loff_t to, -- size_t len, size_t *retlen, const u_char *write_buf); -+ size_t len, const u_char *write_buf); - int (*erase)(struct spi_nor *nor, loff_t offs); - - int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); diff --git a/target/linux/layerscape/patches-4.4/1095-mtd-spi-nor-simplify-write-loop.patch b/target/linux/layerscape/patches-4.4/1095-mtd-spi-nor-simplify-write-loop.patch deleted file mode 100644 index f3179cd56e..0000000000 --- a/target/linux/layerscape/patches-4.4/1095-mtd-spi-nor-simplify-write-loop.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 93b40e12f7e580a41c4aee5597579cc539fd8544 Mon Sep 17 00:00:00 2001 -From: Michal Suchanek -Date: Wed, 2 Dec 2015 10:38:20 +0000 -Subject: [PATCH 095/113] mtd: spi-nor: simplify write loop - -The spi-nor write loop assumes that what is passed to the hardware -driver write() is what gets written. - -When write() writes less than page size at once data is dropped on the -floor. Check the amount of data writen and exit if it does not match -requested amount. - -Signed-off-by: Michal Suchanek -Signed-off-by: Hou Zhiqiang ---- - drivers/mtd/spi-nor/spi-nor.c | 58 ++++++++++++++++++----------------------- - 1 file changed, 25 insertions(+), 33 deletions(-) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -1019,8 +1019,8 @@ static int spi_nor_write(struct mtd_info - size_t *retlen, const u_char *buf) - { - struct spi_nor *nor = mtd_to_spi_nor(mtd); -- u32 page_offset, page_size, i; -- int ret; -+ size_t page_offset, page_remain, i; -+ ssize_t ret; - - dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); - -@@ -1028,45 +1028,37 @@ static int spi_nor_write(struct mtd_info - if (ret) - return ret; - -- write_enable(nor); -+ for (i = 0; i < len; ) { -+ ssize_t written; - -- page_offset = to & (nor->page_size - 1); -- -- /* do all the bytes fit onto one page? */ -- if (page_offset + len <= nor->page_size) { -- ret = nor->write(nor, to, len, buf); -- if (ret < 0) -- goto write_err; -- *retlen += ret; -- } else { -+ page_offset = to & (nor->page_size - 1); -+ WARN_ONCE(page_offset, -+ "Writing at offset %zu into a NOR page. Writing partial pages may decrease reliability and increase wear of NOR flash.", -+ page_offset); - /* the size of data remaining on the first page */ -- page_size = nor->page_size - page_offset; -- ret = nor->write(nor, to, page_size, buf); -+ page_remain = min_t(size_t, -+ nor->page_size - page_offset, len - i); -+ -+ write_enable(nor); -+ ret = nor->write(nor, to + i, page_remain, buf + i); - if (ret < 0) - goto write_err; -- *retlen += ret; -+ written = ret; - -- /* write everything in nor->page_size chunks */ -- for (i = ret; i < len; ) { -- page_size = len - i; -- if (page_size > nor->page_size) -- page_size = nor->page_size; -- -- ret = spi_nor_wait_till_ready(nor); -- if (ret) -- goto write_err; -- -- write_enable(nor); -- -- ret = nor->write(nor, to + i, page_size, buf + i); -- if (ret < 0) -- goto write_err; -- *retlen += ret; -- i += ret; -+ ret = spi_nor_wait_till_ready(nor); -+ if (ret) -+ goto write_err; -+ *retlen += written; -+ i += written; -+ if (written != page_remain) { -+ dev_err(nor->dev, -+ "While writing %zu bytes written %zd bytes\n", -+ page_remain, written); -+ ret = -EIO; -+ goto write_err; - } - } - -- ret = spi_nor_wait_till_ready(nor); - write_err: - spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); - return ret; diff --git a/target/linux/layerscape/patches-4.4/1096-mtd-spi-nor-add-read-loop.patch b/target/linux/layerscape/patches-4.4/1096-mtd-spi-nor-add-read-loop.patch deleted file mode 100644 index 59d9f3e88a..0000000000 --- a/target/linux/layerscape/patches-4.4/1096-mtd-spi-nor-add-read-loop.patch +++ /dev/null @@ -1,46 +0,0 @@ -From b5929f91416d64afacf46c649f38cc8f0eea50d2 Mon Sep 17 00:00:00 2001 -From: Michal Suchanek -Date: Wed, 2 Dec 2015 10:38:20 +0000 -Subject: [PATCH 096/113] mtd: spi-nor: add read loop - -mtdblock and ubi do not handle the situation when read returns less data -than requested. Loop in spi-nor until buffer is filled or an error is -returned. - -Signed-off-by: Michal Suchanek -Signed-off-by: Hou Zhiqiang ---- - drivers/mtd/spi-nor/spi-nor.c | 20 ++++++++++++++------ - 1 file changed, 14 insertions(+), 6 deletions(-) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -921,14 +921,22 @@ static int spi_nor_read(struct mtd_info - if (ret) - return ret; - -- ret = nor->read(nor, from, len, buf); -+ while (len) { -+ ret = nor->read(nor, from, len, buf); -+ if (ret <= 0) -+ goto read_err; - -- spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ); -- if (ret < 0) -- return ret; -+ WARN_ON(ret > len); -+ *retlen += ret; -+ buf += ret; -+ from += ret; -+ len -= ret; -+ } -+ ret = 0; - -- *retlen += ret; -- return 0; -+read_err: -+ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ); -+ return ret; - } - - static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, diff --git a/target/linux/layerscape/patches-4.4/1097-mtd-fsl-quadspi-use-the-property-fields-of-SPI-NOR.patch b/target/linux/layerscape/patches-4.4/1097-mtd-fsl-quadspi-use-the-property-fields-of-SPI-NOR.patch deleted file mode 100644 index d07264d605..0000000000 --- a/target/linux/layerscape/patches-4.4/1097-mtd-fsl-quadspi-use-the-property-fields-of-SPI-NOR.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 5c315652c1b43a6a3abe48c2842cde822ac0ff3c Mon Sep 17 00:00:00 2001 -From: Yunhui Cui -Date: Wed, 20 Jan 2016 18:40:31 +0800 -Subject: [PATCH 097/113] mtd:fsl-quadspi:use the property fields of SPI-NOR - -We can get the read/write/erase opcode from the spi nor framework -directly. This patch uses the information stored in the SPI-NOR to -remove the hardcode in the fsl_qspi_init_lut(). - -Signed-off-by: Yunhui Cui ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 40 +++++++++++-------------------------- - 1 file changed, 12 insertions(+), 28 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl - void __iomem *base = q->iobase; - int rxfifo = q->devtype_data->rxfifo; - u32 lut_base; -- u8 cmd, addrlen, dummy; - int i; - -+ struct spi_nor *nor = &q->nor[0]; -+ u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT; -+ u8 read_op = nor->read_opcode; -+ u8 read_dm = nor->read_dummy; -+ - fsl_qspi_unlock_lut(q); - - /* Clear all the LUT table */ -@@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl - /* Quad Read */ - lut_base = SEQID_QUAD_READ * 4; - -- if (q->nor_size <= SZ_16M) { -- cmd = SPINOR_OP_READ_1_1_4; -- addrlen = ADDR24BIT; -- dummy = 8; -- } else { -- /* use the 4-byte address */ -- cmd = SPINOR_OP_READ_1_1_4; -- addrlen = ADDR32BIT; -- dummy = 8; -- } -- -- qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), -+ qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); -- qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo), -+ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | -+ LUT1(FSL_READ, PAD4, rxfifo), - base + QUADSPI_LUT(lut_base + 1)); - - /* Write enable */ -@@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl - /* Page Program */ - lut_base = SEQID_PP * 4; - -- if (q->nor_size <= SZ_16M) { -- cmd = SPINOR_OP_PP; -- addrlen = ADDR24BIT; -- } else { -- /* use the 4-byte address */ -- cmd = SPINOR_OP_PP; -- addrlen = ADDR32BIT; -- } -- -- qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), -+ qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) | -+ LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); - qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0), - base + QUADSPI_LUT(lut_base + 1)); -@@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl - /* Erase a sector */ - lut_base = SEQID_SE * 4; - -- cmd = q->nor[0].erase_opcode; -- addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT; -- -- qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), -+ qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) | -+ LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); - - /* Erase the whole chip */ diff --git a/target/linux/layerscape/patches-4.4/1098-mtd-fsl-quadspi-Rename-SEQID_QUAD_READ-to-SEQID_READ.patch b/target/linux/layerscape/patches-4.4/1098-mtd-fsl-quadspi-Rename-SEQID_QUAD_READ-to-SEQID_READ.patch deleted file mode 100644 index f27ea21dd8..0000000000 --- a/target/linux/layerscape/patches-4.4/1098-mtd-fsl-quadspi-Rename-SEQID_QUAD_READ-to-SEQID_READ.patch +++ /dev/null @@ -1,46 +0,0 @@ -From c8f9be7df954fce18e96074af3f07aa5f75399e0 Mon Sep 17 00:00:00 2001 -From: Yunhui Cui -Date: Wed, 20 Jan 2016 15:52:25 +0800 -Subject: [PATCH 098/113] mtd: fsl-quadspi: Rename SEQID_QUAD_READ to - SEQID_READ - -There are some read modes for flash, such as NORMAL, FAST, -QUAD, DDR QUAD. These modes will use the identical lut table base -So rename SEQID_QUAD_READ to SEQID_READ. - -Signed-off-by: Yunhui Cui ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -193,7 +193,7 @@ - #define QUADSPI_LUT_NUM 64 - - /* SEQID -- we can have 16 seqids at most. */ --#define SEQID_QUAD_READ 0 -+#define SEQID_READ 0 - #define SEQID_WREN 1 - #define SEQID_WRDI 2 - #define SEQID_RDSR 3 -@@ -386,8 +386,8 @@ static void fsl_qspi_init_lut(struct fsl - for (i = 0; i < QUADSPI_LUT_NUM; i++) - qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4); - -- /* Quad Read */ -- lut_base = SEQID_QUAD_READ * 4; -+ /* Read */ -+ lut_base = SEQID_READ * 4; - - qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); -@@ -468,7 +468,7 @@ static int fsl_qspi_get_seqid(struct fsl - { - switch (cmd) { - case SPINOR_OP_READ_1_1_4: -- return SEQID_QUAD_READ; -+ return SEQID_READ; - case SPINOR_OP_WREN: - return SEQID_WREN; - case SPINOR_OP_WRDI: diff --git a/target/linux/layerscape/patches-4.4/1099-mtd-spi-nor-fsl-quadspi-Add-fast-read-mode-support.patch b/target/linux/layerscape/patches-4.4/1099-mtd-spi-nor-fsl-quadspi-Add-fast-read-mode-support.patch deleted file mode 100644 index ac99ba9504..0000000000 --- a/target/linux/layerscape/patches-4.4/1099-mtd-spi-nor-fsl-quadspi-Add-fast-read-mode-support.patch +++ /dev/null @@ -1,72 +0,0 @@ -From c501cdf57682265b72a8180c06e4a01dc2978375 Mon Sep 17 00:00:00 2001 -From: Yunhui Cui -Date: Mon, 1 Feb 2016 18:26:23 +0800 -Subject: [PATCH 099/113] mtd:spi-nor:fsl-quadspi:Add fast-read mode support - -The qspi driver add generic fast-read mode for different -flash venders. There are some different board flash work on -different mode, such fast-read, quad-mode. -So we have to modify the third entrace parameter of spi_nor_scan(). - -Signed-off-by: Yunhui Cui ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------ - 1 file changed, 21 insertions(+), 6 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -389,11 +389,21 @@ static void fsl_qspi_init_lut(struct fsl - /* Read */ - lut_base = SEQID_READ * 4; - -- qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), -- base + QUADSPI_LUT(lut_base)); -- qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | -- LUT1(FSL_READ, PAD4, rxfifo), -- base + QUADSPI_LUT(lut_base + 1)); -+ if (nor->flash_read == SPI_NOR_FAST) { -+ qspi_writel(q, LUT0(CMD, PAD1, read_op) | -+ LUT1(ADDR, PAD1, addrlen), -+ base + QUADSPI_LUT(lut_base)); -+ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | -+ LUT1(FSL_READ, PAD1, rxfifo), -+ base + QUADSPI_LUT(lut_base + 1)); -+ } else if (nor->flash_read == SPI_NOR_QUAD) { -+ qspi_writel(q, LUT0(CMD, PAD1, read_op) | -+ LUT1(ADDR, PAD1, addrlen), -+ base + QUADSPI_LUT(lut_base)); -+ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | -+ LUT1(FSL_READ, PAD4, rxfifo), -+ base + QUADSPI_LUT(lut_base + 1)); -+ } - - /* Write enable */ - lut_base = SEQID_WREN * 4; -@@ -468,6 +478,7 @@ static int fsl_qspi_get_seqid(struct fsl - { - switch (cmd) { - case SPINOR_OP_READ_1_1_4: -+ case SPINOR_OP_READ_FAST: - return SEQID_READ; - case SPINOR_OP_WREN: - return SEQID_WREN; -@@ -964,6 +975,7 @@ static int fsl_qspi_probe(struct platfor - struct spi_nor *nor; - struct mtd_info *mtd; - int ret, i = 0; -+ enum read_mode mode = SPI_NOR_QUAD; - - q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL); - if (!q) -@@ -1065,7 +1077,10 @@ static int fsl_qspi_probe(struct platfor - /* set the chip address for READID */ - fsl_qspi_set_base_addr(q, nor); - -- ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD); -+ ret = of_property_read_bool(np, "m25p,fast-read"); -+ mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD; -+ -+ ret = spi_nor_scan(nor, NULL, mode); - if (ret) - goto mutex_failed; - diff --git a/target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch b/target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch deleted file mode 100644 index 47fef5cd0c..0000000000 --- a/target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch +++ /dev/null @@ -1,41 +0,0 @@ -From e892dea7229d56b75c46a76b9039f9e179584a91 Mon Sep 17 00:00:00 2001 -From: Yunhui Cui -Date: Mon, 1 Feb 2016 18:48:49 +0800 -Subject: [PATCH 100/113] mtd:spi_nor: Disable Micron flash HW protection - -For Micron family ,The status register write enable/disable bit, -provides hardware data protection for the device. -When the enable/disable bit is set to 1, the status register -nonvolatile bits become read-only and the WRITE STATUS REGISTER -operation will not execute. - -Signed-off-by: Yunhui Cui ---- - drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -39,6 +39,7 @@ - - #define SPI_NOR_MAX_ID_LEN 6 - #define SPI_NOR_MAX_ADDR_WIDTH 4 -+#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f - - struct flash_info { - char *name; -@@ -1246,6 +1247,14 @@ int spi_nor_scan(struct spi_nor *nor, co - if (ret) - return ret; - -+ if (JEDEC_MFR(info) == SNOR_MFR_MICRON) { -+ ret = read_sr(nor); -+ ret &= SPI_NOR_MICRON_WRITE_ENABLE; -+ -+ write_enable(nor); -+ write_sr(nor, ret); -+ } -+ - if (!mtd->name) - mtd->name = dev_name(dev); - mtd->priv = nor; diff --git a/target/linux/layerscape/patches-4.4/1101-mtd-spi-nor-fsl-quadspi-extend-support-for-some-spec.patch b/target/linux/layerscape/patches-4.4/1101-mtd-spi-nor-fsl-quadspi-extend-support-for-some-spec.patch deleted file mode 100644 index 471ce4225f..0000000000 --- a/target/linux/layerscape/patches-4.4/1101-mtd-spi-nor-fsl-quadspi-extend-support-for-some-spec.patch +++ /dev/null @@ -1,122 +0,0 @@ -From acfc6e9b34b3b3ca0d8bbe366dd08b0fac21c740 Mon Sep 17 00:00:00 2001 -From: Yunhui Cui -Date: Tue, 2 Feb 2016 12:21:12 +0800 -Subject: [PATCH 101/113] mtd: spi-nor: fsl-quadspi: extend support for some - special requerment. - -Add extra info in LUT table to support some special requerments. -Spansion S25FS-S family flash need some special operations. - -Signed-off-by: Yunhui Cui ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 44 +++++++++++++++++++++++++++++++++++-- - include/linux/mtd/spi-nor.h | 4 ++++ - 2 files changed, 46 insertions(+), 2 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -205,6 +205,9 @@ - #define SEQID_RDCR 9 - #define SEQID_EN4B 10 - #define SEQID_BRWR 11 -+#define SEQID_RDAR 12 -+#define SEQID_WRAR 13 -+ - - #define QUADSPI_MIN_IOMAP SZ_4M - -@@ -470,6 +473,28 @@ static void fsl_qspi_init_lut(struct fsl - qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR), - base + QUADSPI_LUT(lut_base)); - -+ /* -+ * Read any device register. -+ * Used for Spansion S25FS-S family flash only. -+ */ -+ lut_base = SEQID_RDAR * 4; -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) | -+ LUT1(ADDR, PAD1, ADDR24BIT), -+ base + QUADSPI_LUT(lut_base)); -+ qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1), -+ base + QUADSPI_LUT(lut_base + 1)); -+ -+ /* -+ * Write any device register. -+ * Used for Spansion S25FS-S family flash only. -+ */ -+ lut_base = SEQID_WRAR * 4; -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) | -+ LUT1(ADDR, PAD1, ADDR24BIT), -+ base + QUADSPI_LUT(lut_base)); -+ qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1), -+ base + QUADSPI_LUT(lut_base + 1)); -+ - fsl_qspi_lock_lut(q); - } - -@@ -477,9 +502,15 @@ static void fsl_qspi_init_lut(struct fsl - static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) - { - switch (cmd) { -+ case SPINOR_OP_READ4_1_1_4: - case SPINOR_OP_READ_1_1_4: - case SPINOR_OP_READ_FAST: -+ case SPINOR_OP_READ4_FAST: - return SEQID_READ; -+ case SPINOR_OP_SPANSION_RDAR: -+ return SEQID_RDAR; -+ case SPINOR_OP_SPANSION_WRAR: -+ return SEQID_WRAR; - case SPINOR_OP_WREN: - return SEQID_WREN; - case SPINOR_OP_WRDI: -@@ -491,6 +522,7 @@ static int fsl_qspi_get_seqid(struct fsl - case SPINOR_OP_CHIP_ERASE: - return SEQID_CHIP_ERASE; - case SPINOR_OP_PP: -+ case SPINOR_OP_PP_4B: - return SEQID_PP; - case SPINOR_OP_RDID: - return SEQID_RDID; -@@ -830,8 +862,12 @@ static int fsl_qspi_read_reg(struct spi_ - { - int ret; - struct fsl_qspi *q = nor->priv; -+ u32 to = 0; -+ -+ if (opcode == SPINOR_OP_SPANSION_RDAR) -+ memcpy(&to, nor->cmd_buf, 4); - -- ret = fsl_qspi_runcmd(q, opcode, 0, len); -+ ret = fsl_qspi_runcmd(q, opcode, to, len); - if (ret) - return ret; - -@@ -843,9 +879,13 @@ static int fsl_qspi_write_reg(struct spi - { - struct fsl_qspi *q = nor->priv; - int ret; -+ u32 to = 0; -+ -+ if (opcode == SPINOR_OP_SPANSION_WRAR) -+ memcpy(&to, nor->cmd_buf, 4); - - if (!buf) { -- ret = fsl_qspi_runcmd(q, opcode, 0, 1); -+ ret = fsl_qspi_runcmd(q, opcode, to, 1); - if (ret) - return ret; - ---- a/include/linux/mtd/spi-nor.h -+++ b/include/linux/mtd/spi-nor.h -@@ -74,6 +74,10 @@ - /* Used for Spansion flashes only. */ - #define SPINOR_OP_BRWR 0x17 /* Bank register write */ - -+/* Used for Spansion S25FS-S family flash only. */ -+#define SPINOR_OP_SPANSION_RDAR 0x65 /* Read any device register */ -+#define SPINOR_OP_SPANSION_WRAR 0x71 /* Write any device register */ -+ - /* Used for Micron flashes only. */ - #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ - #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ diff --git a/target/linux/layerscape/patches-4.4/1102-mtd-spi-nor-fsl-quadspi-Support-qspi-for-ls2080a.patch b/target/linux/layerscape/patches-4.4/1102-mtd-spi-nor-fsl-quadspi-Support-qspi-for-ls2080a.patch deleted file mode 100644 index da9dd72a96..0000000000 --- a/target/linux/layerscape/patches-4.4/1102-mtd-spi-nor-fsl-quadspi-Support-qspi-for-ls2080a.patch +++ /dev/null @@ -1,83 +0,0 @@ -From d2d88e3432d68b11b0add84bd15a3aadaf44f1c1 Mon Sep 17 00:00:00 2001 -From: Yunhui Cui -Date: Mon, 28 Dec 2015 18:25:56 +0800 -Subject: [PATCH 102/113] mtd: spi-nor: fsl-quadspi:Support qspi for ls2080a - -There is a hardware feature that qspi_amba_base is added -internally by SOC design on ls2080a. So as to software, the driver -need support to the feature. - -Signed-off-by: Yunhui Cui -Signed-off-by: Yunhui Cui ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 24 ++++++++++++++++++++++-- - 1 file changed, 22 insertions(+), 2 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -41,6 +41,8 @@ - #define QUADSPI_QUIRK_TKT253890 (1 << 2) - /* Controller cannot wake up from wait mode, TKT245618 */ - #define QUADSPI_QUIRK_TKT245618 (1 << 3) -+/* QSPI_AMBA_BASE is internally added by SOC design */ -+#define QUADSPI_AMBA_BASE_INTERNAL (0x10000) - - /* The registers */ - #define QUADSPI_MCR 0x00 -@@ -217,6 +219,7 @@ enum fsl_qspi_devtype { - FSL_QUADSPI_IMX7D, - FSL_QUADSPI_IMX6UL, - FSL_QUADSPI_LS1021A, -+ FSL_QUADSPI_LS2080A, - }; - - struct fsl_qspi_devtype_data { -@@ -270,6 +273,14 @@ static struct fsl_qspi_devtype_data ls10 - .driver_data = 0, - }; - -+static struct fsl_qspi_devtype_data ls2080a_data = { -+ .devtype = FSL_QUADSPI_LS2080A, -+ .rxfifo = 128, -+ .txfifo = 64, -+ .ahb_buf_size = 1024, -+ .driver_data = QUADSPI_AMBA_BASE_INTERNAL, -+}; -+ - #define FSL_QSPI_MAX_CHIP 4 - struct fsl_qspi { - struct spi_nor nor[FSL_QSPI_MAX_CHIP]; -@@ -312,6 +323,11 @@ static inline int needs_wakeup_wait_mode - return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618; - } - -+static inline int has_added_amba_base_internal(struct fsl_qspi *q) -+{ -+ return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL; -+} -+ - /* - * R/W functions for big- or little-endian registers: - * The qSPI controller's endian is independent of the CPU core's endian. -@@ -558,8 +574,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c - /* save the reg */ - reg = qspi_readl(q, base + QUADSPI_MCR); - -- qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr, -- base + QUADSPI_SFAR); -+ if (has_added_amba_base_internal(q)) -+ qspi_writel(q, q->chip_base_addr + addr, base + QUADSPI_SFAR); -+ else -+ qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr, -+ base + QUADSPI_SFAR); - qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS, - base + QUADSPI_RBCT); - qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR); -@@ -849,6 +868,7 @@ static const struct of_device_id fsl_qsp - { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, }, - { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, }, - { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, }, -+ { .compatible = "fsl,ls2080a-qspi", .data = (void *)&ls2080a_data, }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids); diff --git a/target/linux/layerscape/patches-4.4/1103-mtd-spi-nor-Support-R-W-for-S25FS-S-family-flash.patch b/target/linux/layerscape/patches-4.4/1103-mtd-spi-nor-Support-R-W-for-S25FS-S-family-flash.patch deleted file mode 100644 index 7b954dd5c8..0000000000 --- a/target/linux/layerscape/patches-4.4/1103-mtd-spi-nor-Support-R-W-for-S25FS-S-family-flash.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 0878404f549021e7fe0a49ae0454cf53fd452add Mon Sep 17 00:00:00 2001 -From: Yunhui Cui -Date: Tue, 2 Feb 2016 12:00:27 +0800 -Subject: [PATCH 103/113] mtd: spi-nor: Support R/W for S25FS-S family flash - -With the physical sectors combination, S25FS-S family flash -requires some special operations for read/write functions. - -Signed-off-by: Yunhui Cui ---- - drivers/mtd/spi-nor/spi-nor.c | 60 +++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 60 insertions(+) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -40,6 +40,10 @@ - #define SPI_NOR_MAX_ID_LEN 6 - #define SPI_NOR_MAX_ADDR_WIDTH 4 - #define SPI_NOR_MICRON_WRITE_ENABLE 0x7f -+/* Added for S25FS-S family flash */ -+#define SPINOR_CONFIG_REG3_OFFSET 0x800004 -+#define CR3V_4KB_ERASE_UNABLE 0x8 -+#define SPINOR_S25FS_FAMILY_ID 0x81 - - struct flash_info { - char *name; -@@ -74,6 +78,8 @@ struct flash_info { - }; - - #define JEDEC_MFR(info) ((info)->id[0]) -+#define EXT_ID(info) ((info)->id[5]) -+ - - static const struct flash_info *spi_nor_match_id(const char *name); - -@@ -786,6 +792,7 @@ static const struct flash_info spi_nor_i - */ - { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)}, - { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, - { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -@@ -910,6 +917,53 @@ static const struct flash_info *spi_nor_ - return ERR_PTR(-ENODEV); - } - -+/* -+ * The S25FS-S family physical sectors may be configured as a -+ * hybrid combination of eight 4-kB parameter sectors -+ * at the top or bottom of the address space with all -+ * but one of the remaining sectors being uniform size. -+ * The Parameter Sector Erase commands (20h or 21h) must -+ * be used to erase the 4-kB parameter sectors individually. -+ * The Sector (uniform sector) Erase commands (D8h or DCh) -+ * must be used to erase any of the remaining -+ * sectors, including the portion of highest or lowest address -+ * sector that is not overlaid by the parameter sectors. -+ * The uniform sector erase command has no effect on parameter sectors. -+ */ -+static int spansion_s25fs_disable_4kb_erase(struct spi_nor *nor) -+{ -+ struct fsl_qspi *q; -+ u32 cr3v_addr = SPINOR_CONFIG_REG3_OFFSET; -+ u8 cr3v = 0x0; -+ int ret = 0x0; -+ -+ q = nor->priv; -+ -+ nor->cmd_buf[2] = cr3v_addr >> 16; -+ nor->cmd_buf[1] = cr3v_addr >> 8; -+ nor->cmd_buf[0] = cr3v_addr >> 0; -+ -+ ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1); -+ if (ret) -+ return ret; -+ if (cr3v & CR3V_4KB_ERASE_UNABLE) -+ return 0; -+ ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); -+ if (ret) -+ return ret; -+ cr3v = CR3V_4KB_ERASE_UNABLE; -+ nor->program_opcode = SPINOR_OP_SPANSION_WRAR; -+ nor->write(nor, cr3v_addr, 1, &cr3v); -+ -+ ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1); -+ if (ret) -+ return ret; -+ if (!(cr3v & CR3V_4KB_ERASE_UNABLE)) -+ return -EPERM; -+ -+ return 0; -+} -+ - static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, u_char *buf) - { -@@ -1255,6 +1309,12 @@ int spi_nor_scan(struct spi_nor *nor, co - write_sr(nor, ret); - } - -+ if (EXT_ID(info) == SPINOR_S25FS_FAMILY_ID) { -+ ret = spansion_s25fs_disable_4kb_erase(nor); -+ if (ret) -+ return ret; -+ } -+ - if (!mtd->name) - mtd->name = dev_name(dev); - mtd->priv = nor; diff --git a/target/linux/layerscape/patches-4.4/1104-mtd-fsl-quadspi-Add-quad-mode-for-flash-n25q128.patch b/target/linux/layerscape/patches-4.4/1104-mtd-fsl-quadspi-Add-quad-mode-for-flash-n25q128.patch deleted file mode 100644 index daf34e3388..0000000000 --- a/target/linux/layerscape/patches-4.4/1104-mtd-fsl-quadspi-Add-quad-mode-for-flash-n25q128.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 23cd071c47c064d56921975d196dc22177069dea Mon Sep 17 00:00:00 2001 -From: Yunhui Cui -Date: Wed, 24 Feb 2016 15:14:01 +0800 -Subject: [PATCH 104/113] mtd: fsl-quadspi: Add quad mode for flash n25q128 - -Add some lut_tables to support quad mode for flash n25q128 -on the board ls1021a-twr and solve flash Spansion and Micron -command conflict. -In switch {}, The value of command SPINOR_OP_RD_EVCR and -SPINOR_OP_SPANSION_RDAR is the same. They have to share -the same seq_id: SEQID_RDAR_OR_RD_EVCR. - -Signed-off-by: Yunhui Cui ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 47 ++++++++++++++++++++++++++++--------- - 1 file changed, 36 insertions(+), 11 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -207,9 +207,9 @@ - #define SEQID_RDCR 9 - #define SEQID_EN4B 10 - #define SEQID_BRWR 11 --#define SEQID_RDAR 12 -+#define SEQID_RDAR_OR_RD_EVCR 12 - #define SEQID_WRAR 13 -- -+#define SEQID_WD_EVCR 14 - - #define QUADSPI_MIN_IOMAP SZ_4M - -@@ -393,6 +393,7 @@ static void fsl_qspi_init_lut(struct fsl - int rxfifo = q->devtype_data->rxfifo; - u32 lut_base; - int i; -+ const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data; - - struct spi_nor *nor = &q->nor[0]; - u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT; -@@ -489,16 +490,26 @@ static void fsl_qspi_init_lut(struct fsl - qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR), - base + QUADSPI_LUT(lut_base)); - -+ - /* -- * Read any device register. -- * Used for Spansion S25FS-S family flash only. -+ * Flash Micron and Spansion command confilict -+ * use the same value 0x65. But it indicates different meaning. - */ -- lut_base = SEQID_RDAR * 4; -- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) | -- LUT1(ADDR, PAD1, ADDR24BIT), -- base + QUADSPI_LUT(lut_base)); -- qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1), -- base + QUADSPI_LUT(lut_base + 1)); -+ lut_base = SEQID_RDAR_OR_RD_EVCR * 4; -+ if (devtype_data->devtype == FSL_QUADSPI_LS2080A) { -+ /* -+ * Read any device register. -+ * Used for Spansion S25FS-S family flash only. -+ */ -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) | -+ LUT1(ADDR, PAD1, ADDR24BIT), -+ base + QUADSPI_LUT(lut_base)); -+ qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1), -+ base + QUADSPI_LUT(lut_base + 1)); -+ } else { -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR), -+ base + QUADSPI_LUT(lut_base)); -+ } - - /* - * Write any device register. -@@ -511,6 +522,11 @@ static void fsl_qspi_init_lut(struct fsl - qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1), - base + QUADSPI_LUT(lut_base + 1)); - -+ /* Write EVCR register */ -+ lut_base = SEQID_WD_EVCR * 4; -+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR), -+ base + QUADSPI_LUT(lut_base)); -+ - fsl_qspi_lock_lut(q); - } - -@@ -523,8 +539,15 @@ static int fsl_qspi_get_seqid(struct fsl - case SPINOR_OP_READ_FAST: - case SPINOR_OP_READ4_FAST: - return SEQID_READ; -+ /* -+ * Spansion & Micron use the same command value 0x65 -+ * Spansion: SPINOR_OP_SPANSION_RDAR, read any register. -+ * Micron: SPINOR_OP_RD_EVCR, -+ * read enhanced volatile configuration register. -+ * case SPINOR_OP_RD_EVCR: -+ */ - case SPINOR_OP_SPANSION_RDAR: -- return SEQID_RDAR; -+ return SEQID_RDAR_OR_RD_EVCR; - case SPINOR_OP_SPANSION_WRAR: - return SEQID_WRAR; - case SPINOR_OP_WREN: -@@ -550,6 +573,8 @@ static int fsl_qspi_get_seqid(struct fsl - return SEQID_EN4B; - case SPINOR_OP_BRWR: - return SEQID_BRWR; -+ case SPINOR_OP_WD_EVCR: -+ return SEQID_WD_EVCR; - default: - if (cmd == q->nor[0].erase_opcode) - return SEQID_SE; diff --git a/target/linux/layerscape/patches-4.4/1105-mtd-spi-nor-add-DDR-quad-read-support.patch b/target/linux/layerscape/patches-4.4/1105-mtd-spi-nor-add-DDR-quad-read-support.patch deleted file mode 100644 index df7e0d82f8..0000000000 --- a/target/linux/layerscape/patches-4.4/1105-mtd-spi-nor-add-DDR-quad-read-support.patch +++ /dev/null @@ -1,181 +0,0 @@ -From 924f021c0344554a4b61746e5c4dcfc91d618ce2 Mon Sep 17 00:00:00 2001 -From: Yunhui Cui -Date: Thu, 18 Feb 2016 16:41:53 +0800 -Subject: [PATCH 105/113] mtd: spi-nor: add DDR quad read support - -This patch adds the DDR quad read support by the following: - - [1] add SPI_NOR_DDR_QUAD read mode. - - [2] add DDR Quad read opcodes: - SPINOR_OP_READ_1_4_4_D / SPINOR_OP_READ4_1_4_4_D - - [3] add set_ddr_quad_mode() to initialize for the DDR quad read. - Currently it only works for Spansion NOR. - - [4] set dummy with 6 for Spansion family -Test this patch for Spansion s25fl128s NOR flash. - -Signed-off-by: Yunhui Cui ---- - drivers/mtd/spi-nor/spi-nor.c | 53 ++++++++++++++++++++++++++++++++++++----- - include/linux/mtd/spi-nor.h | 8 +++++-- - 2 files changed, 53 insertions(+), 8 deletions(-) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -73,7 +73,8 @@ struct flash_info { - #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */ - #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */ - #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */ --#define USE_FSR 0x80 /* use flag status register */ -+#define SPI_NOR_DDR_QUAD_READ 0x80 /* Flash supports DDR Quad Read */ -+#define USE_FSR 0x100 /* use flag status register */ - #define SPI_NOR_HAS_LOCK 0x100 /* Flash supports lock/unlock via SR */ - }; - -@@ -145,13 +146,17 @@ static int read_cr(struct spi_nor *nor) - * It can be used to support more commands with - * different dummy cycle requirements. - */ --static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor) -+static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor, -+ const struct flash_info *info) - { - switch (nor->flash_read) { - case SPI_NOR_FAST: - case SPI_NOR_DUAL: - case SPI_NOR_QUAD: - return 8; -+ case SPI_NOR_DDR_QUAD: -+ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) -+ return 6; - case SPI_NOR_NORMAL: - return 0; - } -@@ -799,7 +804,8 @@ static const struct flash_info spi_nor_i - { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, - { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, - { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, -- { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, -+ { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ -+ | SPI_NOR_DDR_QUAD_READ) }, - { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, -@@ -1195,6 +1201,23 @@ static int spansion_quad_enable(struct s - return 0; - } - -+static int set_ddr_quad_mode(struct spi_nor *nor, const struct flash_info *info) -+{ -+ int status; -+ -+ switch (JEDEC_MFR(info)) { -+ case SNOR_MFR_SPANSION: -+ status = spansion_quad_enable(nor); -+ if (status) { -+ dev_err(nor->dev, "Spansion DDR quad-read not enabled\n"); -+ return status; -+ } -+ return status; -+ default: -+ return -EINVAL; -+ } -+} -+ - static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info) - { - int status; -@@ -1385,8 +1408,15 @@ int spi_nor_scan(struct spi_nor *nor, co - if (info->flags & SPI_NOR_NO_FR) - nor->flash_read = SPI_NOR_NORMAL; - -- /* Quad/Dual-read mode takes precedence over fast/normal */ -- if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) { -+ /* DDR Quad/Quad/Dual-read mode takes precedence over fast/normal */ -+ if (mode == SPI_NOR_DDR_QUAD && info->flags & SPI_NOR_DDR_QUAD_READ) { -+ ret = set_ddr_quad_mode(nor, info); -+ if (ret) { -+ dev_err(dev, "DDR quad mode not supported\n"); -+ return ret; -+ } -+ nor->flash_read = SPI_NOR_DDR_QUAD; -+ } else if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) { - ret = set_quad_mode(nor, info); - if (ret) { - dev_err(dev, "quad mode not supported\n"); -@@ -1399,6 +1429,14 @@ int spi_nor_scan(struct spi_nor *nor, co - - /* Default commands */ - switch (nor->flash_read) { -+ case SPI_NOR_DDR_QUAD: -+ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) { /* Spansion */ -+ nor->read_opcode = SPINOR_OP_READ_1_4_4_D; -+ } else { -+ dev_err(dev, "DDR Quad Read is not supported.\n"); -+ return -EINVAL; -+ } -+ break; - case SPI_NOR_QUAD: - nor->read_opcode = SPINOR_OP_READ_1_1_4; - break; -@@ -1426,6 +1464,9 @@ int spi_nor_scan(struct spi_nor *nor, co - if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) { - /* Dedicated 4-byte command set */ - switch (nor->flash_read) { -+ case SPI_NOR_DDR_QUAD: -+ nor->read_opcode = SPINOR_OP_READ4_1_4_4_D; -+ break; - case SPI_NOR_QUAD: - nor->read_opcode = SPINOR_OP_READ4_1_1_4; - break; -@@ -1455,7 +1496,7 @@ int spi_nor_scan(struct spi_nor *nor, co - return -EINVAL; - } - -- nor->read_dummy = spi_nor_read_dummy_cycles(nor); -+ nor->read_dummy = spi_nor_read_dummy_cycles(nor, info); - - dev_info(dev, "%s (%lld Kbytes)\n", info->name, - (long long)mtd->size >> 10); ---- a/include/linux/mtd/spi-nor.h -+++ b/include/linux/mtd/spi-nor.h -@@ -30,10 +30,11 @@ - - /* - * Note on opcode nomenclature: some opcodes have a format like -- * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number -+ * SPINOR_OP_FUNCTION{4,}_x_y_z{_D}. The numbers x, y,and z stand for the number - * of I/O lines used for the opcode, address, and data (respectively). The - * FUNCTION has an optional suffix of '4', to represent an opcode which -- * requires a 4-byte (32-bit) address. -+ * requires a 4-byte (32-bit) address. The suffix of 'D' stands for the -+ * DDR mode. - */ - - /* Flash opcodes. */ -@@ -44,6 +45,7 @@ - #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ - #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */ - #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */ -+#define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */ - #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ - #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ - #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ -@@ -59,6 +61,7 @@ - #define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */ - #define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */ - #define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */ -+#define SPINOR_OP_READ4_1_4_4_D 0xee /* Read data bytes (DDR Quad SPI) */ - #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ - #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ - -@@ -107,6 +110,7 @@ enum read_mode { - SPI_NOR_FAST, - SPI_NOR_DUAL, - SPI_NOR_QUAD, -+ SPI_NOR_DDR_QUAD, - }; - - #define SPI_NOR_MAX_CMD_SIZE 8 diff --git a/target/linux/layerscape/patches-4.4/1106-mtd-fsl-quadspi-add-DDR-quad-read-for-Spansion.patch b/target/linux/layerscape/patches-4.4/1106-mtd-fsl-quadspi-add-DDR-quad-read-for-Spansion.patch deleted file mode 100644 index 3a242608ba..0000000000 --- a/target/linux/layerscape/patches-4.4/1106-mtd-fsl-quadspi-add-DDR-quad-read-for-Spansion.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 16eb35ceea5b43e6f64c1a869721ea86c0da5260 Mon Sep 17 00:00:00 2001 -From: Yunhui Cui -Date: Thu, 25 Feb 2016 10:19:15 +0800 -Subject: [PATCH 106/113] mtd: fsl-quadspi: add DDR quad read for Spansion - -Add the DDR quad read support for the fsl-quadspi driver. -And, add the Spansion s25fl128s NOR flash ddr quad mode -support. - -Signed-off-by: Yunhui Cui ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 57 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 57 insertions(+) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -296,6 +296,7 @@ struct fsl_qspi { - u32 nor_size; - u32 nor_num; - u32 clk_rate; -+ u32 ddr_smp; - unsigned int chip_base_addr; /* We may support two chips. */ - bool has_second_chip; - bool big_endian; -@@ -423,6 +424,19 @@ static void fsl_qspi_init_lut(struct fsl - qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | - LUT1(FSL_READ, PAD4, rxfifo), - base + QUADSPI_LUT(lut_base + 1)); -+ } else if (nor->flash_read == SPI_NOR_DDR_QUAD) { -+ /* read mode : 1-4-4, such as Spansion s25fl128s. */ -+ qspi_writel(q, LUT0(CMD, PAD1, read_op) -+ | LUT1(ADDR_DDR, PAD4, addrlen), -+ base + QUADSPI_LUT(lut_base)); -+ -+ qspi_writel(q, LUT0(MODE_DDR, PAD4, 0xff) -+ | LUT1(DUMMY, PAD1, read_dm), -+ base + QUADSPI_LUT(lut_base + 1)); -+ -+ qspi_writel(q, LUT0(FSL_READ_DDR, PAD4, rxfifo) -+ | LUT1(JMP_ON_CS, PAD1, 0), -+ base + QUADSPI_LUT(lut_base + 2)); - } - - /* Write enable */ -@@ -534,6 +548,8 @@ static void fsl_qspi_init_lut(struct fsl - static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) - { - switch (cmd) { -+ case SPINOR_OP_READ_1_4_4_D: -+ case SPINOR_OP_READ4_1_4_4_D: - case SPINOR_OP_READ4_1_1_4: - case SPINOR_OP_READ_1_1_4: - case SPINOR_OP_READ_FAST: -@@ -736,6 +752,32 @@ static void fsl_qspi_set_map_addr(struct - } - - /* -+ * enable controller ddr quad mode to support different -+ * vender flashes ddr quad mode. -+ */ -+static void set_ddr_quad_mode(struct fsl_qspi *q) -+{ -+ u32 reg, reg2; -+ -+ reg = qspi_readl(q, q->iobase + QUADSPI_MCR); -+ -+ /* Firstly, disable the module */ -+ qspi_writel(q, reg | QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); -+ -+ /* Set the Sampling Register for DDR */ -+ reg2 = qspi_readl(q, q->iobase + QUADSPI_SMPR); -+ reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK; -+ reg2 |= (((q->ddr_smp) << QUADSPI_SMPR_DDRSMP_SHIFT) & -+ QUADSPI_SMPR_DDRSMP_MASK); -+ qspi_writel(q, reg2, q->iobase + QUADSPI_SMPR); -+ -+ /* Enable the module again (enable the DDR too) */ -+ reg |= QUADSPI_MCR_DDR_EN_MASK; -+ qspi_writel(q, reg, q->iobase + QUADSPI_MCR); -+ -+} -+ -+/* - * There are two different ways to read out the data from the flash: - * the "IP Command Read" and the "AHB Command Read". - * -@@ -775,6 +817,11 @@ static void fsl_qspi_init_abh_read(struc - seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode); - qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT, - q->iobase + QUADSPI_BFGENCR); -+ -+ /* enable the DDR quad read */ -+ if (q->nor->flash_read == SPI_NOR_DDR_QUAD) -+ set_ddr_quad_mode(q); -+ - } - - /* This function was used to prepare and enable QSPI clock */ -@@ -1108,6 +1155,12 @@ static int fsl_qspi_probe(struct platfor - goto clk_failed; - } - -+ /* find ddrsmp value */ -+ ret = of_property_read_u32(dev->of_node, "fsl,ddr-sampling-point", -+ &q->ddr_smp); -+ if (ret) -+ q->ddr_smp = 0; -+ - /* find the irq */ - ret = platform_get_irq(pdev, 0); - if (ret < 0) { -@@ -1164,6 +1217,10 @@ static int fsl_qspi_probe(struct platfor - - ret = of_property_read_bool(np, "m25p,fast-read"); - mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD; -+ /* Can we enable the DDR Quad Read? */ -+ ret = of_property_read_bool(np, "ddr-quad-read"); -+ if (ret) -+ mode = SPI_NOR_DDR_QUAD; - - ret = spi_nor_scan(nor, NULL, mode); - if (ret) diff --git a/target/linux/layerscape/patches-4.4/1107-mtd-fsl-quadspi-disable-AHB-buffer-prefetch.patch b/target/linux/layerscape/patches-4.4/1107-mtd-fsl-quadspi-disable-AHB-buffer-prefetch.patch deleted file mode 100644 index 19dff6c92e..0000000000 --- a/target/linux/layerscape/patches-4.4/1107-mtd-fsl-quadspi-disable-AHB-buffer-prefetch.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 50aac689d5be0a086f076cd4bc8b14ee0b9ab995 Mon Sep 17 00:00:00 2001 -From: Yunhui Cui -Date: Tue, 8 Mar 2016 14:38:52 +0800 -Subject: [PATCH 107/113] mtd: fsl-quadspi: disable AHB buffer prefetch - -A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data -Affects: QuadSPI -Description: With AHB buffer prefetch enabled, the QuadSPI may return -incorrect data on the AHB -interface. The buffer pre-fetch is enabled if the fetch size as -configured either in the LUT or in -the BUFxCR register is greater than 8 bytes. -Impact: Only 64 bit read allowed. -Workaround: Keep the read data size to 64 bits (8 Bytes), which disables -the prefetch on the AHB buffer, -and prevents this issue from occurring. - -Signed-off-by: Yunhui Cui ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 29 +++++++++++++++++++++++------ - 1 file changed, 23 insertions(+), 6 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -794,19 +794,36 @@ static void fsl_qspi_init_abh_read(struc - { - void __iomem *base = q->iobase; - int seqid; -+ const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data; - - /* AHB configuration for access buffer 0/1/2 .*/ - qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR); - qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR); - qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR); -+ - /* -- * Set ADATSZ with the maximum AHB buffer size to improve the -- * read performance. -+ * Errata: A-009282: QuadSPI data prefetch may result in incorrect data -+ * Workaround: Keep the read data size to 64 bits (8 bytes). -+ * This disables the prefetch on the AHB buffer and -+ * prevents this issue from occurring. - */ -- qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | -- ((q->devtype_data->ahb_buf_size / 8) -- << QUADSPI_BUF3CR_ADATSZ_SHIFT), -- base + QUADSPI_BUF3CR); -+ if (devtype_data->devtype == FSL_QUADSPI_LS2080A || -+ devtype_data->devtype == FSL_QUADSPI_LS1021A) { -+ -+ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | -+ (1 << QUADSPI_BUF3CR_ADATSZ_SHIFT), -+ base + QUADSPI_BUF3CR); -+ -+ } else { -+ /* -+ * Set ADATSZ with the maximum AHB buffer size to improve the -+ * read performance. -+ */ -+ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | -+ ((q->devtype_data->ahb_buf_size / 8) -+ << QUADSPI_BUF3CR_ADATSZ_SHIFT), -+ base + QUADSPI_BUF3CR); -+ } - - /* We only use the buffer3 */ - qspi_writel(q, 0, base + QUADSPI_BUF0IND); diff --git a/target/linux/layerscape/patches-4.4/1108-mtd-fsl-quadspi-add-multi-flash-chip-R-W-on-ls2080a.patch b/target/linux/layerscape/patches-4.4/1108-mtd-fsl-quadspi-add-multi-flash-chip-R-W-on-ls2080a.patch deleted file mode 100644 index 4a7a5cbcdf..0000000000 --- a/target/linux/layerscape/patches-4.4/1108-mtd-fsl-quadspi-add-multi-flash-chip-R-W-on-ls2080a.patch +++ /dev/null @@ -1,42 +0,0 @@ -From d3a8ee41170ff9e5298ff354c77ff99439dfe2bf Mon Sep 17 00:00:00 2001 -From: Yunhui Cui -Date: Thu, 10 Mar 2016 11:33:40 +0800 -Subject: [PATCH 108/113] mtd: fsl-quadspi: add multi flash chip R/W on - ls2080a - -There is a hardware feature that qspi_amba_base is added -internally by SOC design on ls2080a. so memmap_phy need not -be added in driver. If memmap_phy is added, the flash A1 -addr space is [0, memmap_phy] which far more than flash size. -The AMBA memory will be divided into four parts and assign to -every chipselect. Every channel will has two valid chipselects. - -Signed-off-by: Yunhui Cui ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 14 ++++++++++---- - 1 file changed, 10 insertions(+), 4 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -744,11 +744,17 @@ static void fsl_qspi_set_map_addr(struct - { - int nor_size = q->nor_size; - void __iomem *base = q->iobase; -+ u32 mem_base; - -- qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD); -- qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD); -- qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD); -- qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD); -+ if (has_added_amba_base_internal(q)) -+ mem_base = 0x0; -+ else -+ mem_base = q->memmap_phy; -+ -+ qspi_writel(q, nor_size + mem_base, base + QUADSPI_SFA1AD); -+ qspi_writel(q, nor_size * 2 + mem_base, base + QUADSPI_SFA2AD); -+ qspi_writel(q, nor_size * 3 + mem_base, base + QUADSPI_SFB1AD); -+ qspi_writel(q, nor_size * 4 + mem_base, base + QUADSPI_SFB2AD); - } - - /* diff --git a/target/linux/layerscape/patches-4.4/1109-drivers-mtd-spi-nor-Enable-QSPI-Flash-in-Kernel.patch b/target/linux/layerscape/patches-4.4/1109-drivers-mtd-spi-nor-Enable-QSPI-Flash-in-Kernel.patch deleted file mode 100644 index 95321ebf1b..0000000000 --- a/target/linux/layerscape/patches-4.4/1109-drivers-mtd-spi-nor-Enable-QSPI-Flash-in-Kernel.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 70516f60de441829e7813c0b26567c8bda39c011 Mon Sep 17 00:00:00 2001 -From: Pratiyush Mohan Srivastava -Date: Sun, 24 Apr 2016 23:20:26 +0530 -Subject: [PATCH 109/113] drivers: mtd: spi-nor: Enable QSPI Flash in Kernel - -Enable read from QSPI flash, Write onto QSPI Flash and -erase QSPI Flash in Fast mode in Kernel. - -Signed-off-by: Pratiyush Mohan Srivastava -Signed-off-by: Prabhakar Kushwaha ---- - drivers/mtd/spi-nor/spi-nor.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -798,6 +798,7 @@ static const struct flash_info spi_nor_i - { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)}, -+ { "s25fs512s", INFO6(0x010220, 0x4d0081, 128 * 1024, 512, 0)}, - { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, - { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -@@ -964,9 +965,11 @@ static int spansion_s25fs_disable_4kb_er - ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1); - if (ret) - return ret; -+/* - if (!(cr3v & CR3V_4KB_ERASE_UNABLE)) - return -EPERM; - -+*/ - return 0; - } - diff --git a/target/linux/layerscape/patches-4.4/1110-mtd-spi-nor-fsl-quad-add-flash-S25FS-extra-support.patch b/target/linux/layerscape/patches-4.4/1110-mtd-spi-nor-fsl-quad-add-flash-S25FS-extra-support.patch deleted file mode 100644 index c018a33fb0..0000000000 --- a/target/linux/layerscape/patches-4.4/1110-mtd-spi-nor-fsl-quad-add-flash-S25FS-extra-support.patch +++ /dev/null @@ -1,157 +0,0 @@ -From 034dd6241b55ab2256eecb845e941fa9b45da38e Mon Sep 17 00:00:00 2001 -From: Yunhui Cui -Date: Thu, 28 Apr 2016 17:03:57 +0800 -Subject: [PATCH 110/113] mtd: spi-nor: fsl-quad: add flash S25FS extra - support - -[context adjustment] -not apply changes of arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts - -There are some boards have the same QSPI controller but have -different vendor flash, So, the controller can use the same -compatible and share the driver, just for a different flash to do -the appropriate adaptation. Based on this, we need add the vendor -field in spi-nor, Because we will use the field to distribute -corresponding LUT for different flash operations. - -Signed-off-by: Yunhui Cui -Signed-off-by: Pratiyush Mohan Srivastava -Signed-off-by: Prabhakar Kushwaha -Integrated-by: Jiang Yutang ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 47 ++++++++++++++++++++++++++++++------- - drivers/mtd/spi-nor/spi-nor.c | 5 ++-- - include/linux/mtd/spi-nor.h | 1 + - 3 files changed, 42 insertions(+), 11 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -213,6 +213,9 @@ - - #define QUADSPI_MIN_IOMAP SZ_4M - -+#define FLASH_VENDOR_SPANSION_FS "s25fs" -+#define SPANSION_S25FS_FAMILY (1 << 1) -+ - enum fsl_qspi_devtype { - FSL_QUADSPI_VYBRID, - FSL_QUADSPI_IMX6SX, -@@ -329,6 +332,18 @@ static inline int has_added_amba_base_in - return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL; - } - -+static u32 fsl_get_nor_vendor(struct spi_nor *nor) -+{ -+ u32 vendor_id; -+ -+ if (nor->vendor) { -+ if (memcmp(nor->vendor, FLASH_VENDOR_SPANSION_FS, -+ sizeof(FLASH_VENDOR_SPANSION_FS) - 1)) -+ vendor_id = SPANSION_S25FS_FAMILY; -+ } -+ return vendor_id; -+} -+ - /* - * R/W functions for big- or little-endian registers: - * The qSPI controller's endian is independent of the CPU core's endian. -@@ -394,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl - int rxfifo = q->devtype_data->rxfifo; - u32 lut_base; - int i; -- const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data; -+ u32 vendor; - - struct spi_nor *nor = &q->nor[0]; - u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT; - u8 read_op = nor->read_opcode; - u8 read_dm = nor->read_dummy; - -+ vendor = fsl_get_nor_vendor(nor); -+ - fsl_qspi_unlock_lut(q); - - /* Clear all the LUT table */ -@@ -418,12 +435,25 @@ static void fsl_qspi_init_lut(struct fsl - LUT1(FSL_READ, PAD1, rxfifo), - base + QUADSPI_LUT(lut_base + 1)); - } else if (nor->flash_read == SPI_NOR_QUAD) { -- qspi_writel(q, LUT0(CMD, PAD1, read_op) | -- LUT1(ADDR, PAD1, addrlen), -- base + QUADSPI_LUT(lut_base)); -- qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | -- LUT1(FSL_READ, PAD4, rxfifo), -- base + QUADSPI_LUT(lut_base + 1)); -+ if (q->nor_size == 0x4000000) { -+ read_op = 0xEC; -+ qspi_writel(q, -+ LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD4, addrlen), -+ base + QUADSPI_LUT(lut_base)); -+ qspi_writel(q, -+ LUT0(MODE, PAD4, 0xff) | LUT1(DUMMY, PAD4, read_dm), -+ base + QUADSPI_LUT(lut_base + 1)); -+ qspi_writel(q, -+ LUT0(FSL_READ, PAD4, rxfifo), -+ base + QUADSPI_LUT(lut_base + 2)); -+ } else { -+ qspi_writel(q, LUT0(CMD, PAD1, read_op) | -+ LUT1(ADDR, PAD1, addrlen), -+ base + QUADSPI_LUT(lut_base)); -+ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | -+ LUT1(FSL_READ, PAD4, rxfifo), -+ base + QUADSPI_LUT(lut_base + 1)); -+ } - } else if (nor->flash_read == SPI_NOR_DDR_QUAD) { - /* read mode : 1-4-4, such as Spansion s25fl128s. */ - qspi_writel(q, LUT0(CMD, PAD1, read_op) -@@ -510,7 +540,8 @@ static void fsl_qspi_init_lut(struct fsl - * use the same value 0x65. But it indicates different meaning. - */ - lut_base = SEQID_RDAR_OR_RD_EVCR * 4; -- if (devtype_data->devtype == FSL_QUADSPI_LS2080A) { -+ -+ if (vendor == SPANSION_S25FS_FAMILY) { - /* - * Read any device register. - * Used for Spansion S25FS-S family flash only. ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -798,7 +798,6 @@ static const struct flash_info spi_nor_i - { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)}, -- { "s25fs512s", INFO6(0x010220, 0x4d0081, 128 * 1024, 512, 0)}, - { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, - { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -@@ -965,11 +964,9 @@ static int spansion_s25fs_disable_4kb_er - ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1); - if (ret) - return ret; --/* - if (!(cr3v & CR3V_4KB_ERASE_UNABLE)) - return -EPERM; - --*/ - return 0; - } - -@@ -1343,6 +1340,8 @@ int spi_nor_scan(struct spi_nor *nor, co - - if (!mtd->name) - mtd->name = dev_name(dev); -+ if (info->name) -+ nor->vendor = info->name; - mtd->priv = nor; - mtd->type = MTD_NORFLASH; - mtd->writesize = 1; ---- a/include/linux/mtd/spi-nor.h -+++ b/include/linux/mtd/spi-nor.h -@@ -172,6 +172,7 @@ struct spi_nor { - bool sst_write_second; - u32 flags; - u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; -+ char *vendor; - - int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); - void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); diff --git a/target/linux/layerscape/patches-4.4/1111-mtd-spi-nor-disable-4kb-sector-erase-for-s25fl128.patch b/target/linux/layerscape/patches-4.4/1111-mtd-spi-nor-disable-4kb-sector-erase-for-s25fl128.patch deleted file mode 100644 index f9cdb88f13..0000000000 --- a/target/linux/layerscape/patches-4.4/1111-mtd-spi-nor-disable-4kb-sector-erase-for-s25fl128.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 30d34abc80b0a602a1327bdfbddd42d250887049 Mon Sep 17 00:00:00 2001 -From: Yutang Jiang -Date: Fri, 9 Sep 2016 22:56:12 +0800 -Subject: [PATCH 111/113] mtd: spi-nor: disable 4kb sector erase for s25fl128 - -As for s25fl128s flash, the sectors are organized either as a hybrid -combination of 4-kB and 64-kB sectors, or as uniform 256-kbyte sectors. -we should use the command 0xd8 to erase all bits, not the Parameter 4-kB -Sector Erase (P4E) command 0x20. - -Signed-off-by: Yunhui Cui -Integrated-by: Yutang Jiang ---- - drivers/mtd/spi-nor/spi-nor.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -804,7 +804,7 @@ static const struct flash_info spi_nor_i - { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, - { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, - { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, -- { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ -+ { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ - | SPI_NOR_DDR_QUAD_READ) }, - { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, diff --git a/target/linux/layerscape/patches-4.4/1112-driver-spi-fsl-quad-Hang-memcpy-Unhandled-fault-alig.patch b/target/linux/layerscape/patches-4.4/1112-driver-spi-fsl-quad-Hang-memcpy-Unhandled-fault-alig.patch deleted file mode 100644 index c6311fc4bb..0000000000 --- a/target/linux/layerscape/patches-4.4/1112-driver-spi-fsl-quad-Hang-memcpy-Unhandled-fault-alig.patch +++ /dev/null @@ -1,29 +0,0 @@ -From f1b7824a42505669476f203e126fc26dd1006af2 Mon Sep 17 00:00:00 2001 -From: Yutang Jiang -Date: Fri, 9 Sep 2016 22:57:55 +0800 -Subject: [PATCH 112/113] driver: spi: fsl-quad: Hang memcpy: Unhandled fault: - alignment fault - -vmap/iomap based on whether the buffer is in memory region or reserved region. -However, both map it as non-cacheable memory. -For armv8 specifically, non-cacheable mapping requests use a memory type -that has to be accessed aligned to the request size. memcpy() doesn't guarantee -that. memcpy_toio() can guarantee 4-bytes alignment. - -Signed-off-by: Yunhui Cui -Integrated-by: Yutang Jiang ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -1103,7 +1103,7 @@ static ssize_t fsl_qspi_read(struct spi_ - len); - - /* Read out the data directly from the AHB buffer.*/ -- memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs, -+ memcpy_toio(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs, - len); - - return len; diff --git a/target/linux/layerscape/patches-4.4/1113-mtd-spi-nor-fsl-quad-move-mtd_device_register-to-the.patch b/target/linux/layerscape/patches-4.4/1113-mtd-spi-nor-fsl-quad-move-mtd_device_register-to-the.patch deleted file mode 100644 index f54f9854e3..0000000000 --- a/target/linux/layerscape/patches-4.4/1113-mtd-spi-nor-fsl-quad-move-mtd_device_register-to-the.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 6f1195d231ab576809fe2f4cff44a6e48cff2457 Mon Sep 17 00:00:00 2001 -From: Yutang Jiang -Date: Fri, 2 Sep 2016 22:00:16 +0800 -Subject: [PATCH 113/113] mtd: spi-nor: fsl-quad: move mtd_device_register to - the last of probe - -After call mtd_device_register, the mtd devices should be workable immediately. -If before finish all of init work call the mtd_device_register, it will not -respond work request timely. - -For example, openwrt/lede have a AUTO split special flash partitions mechanism -while mtd driver register. So, before call mtd_device_register, must let all of -init work ready. - -Signed-off-by: Yutang Jiang ---- - drivers/mtd/spi-nor/fsl-quadspi.c | 14 ++++++++++---- - 1 file changed, 10 insertions(+), 4 deletions(-) - ---- a/drivers/mtd/spi-nor/fsl-quadspi.c -+++ b/drivers/mtd/spi-nor/fsl-quadspi.c -@@ -1280,10 +1280,6 @@ static int fsl_qspi_probe(struct platfor - if (ret) - goto mutex_failed; - -- ret = mtd_device_register(mtd, NULL, 0); -- if (ret) -- goto mutex_failed; -- - /* Set the correct NOR size now. */ - if (q->nor_size == 0) { - q->nor_size = mtd->size; -@@ -1313,6 +1309,16 @@ static int fsl_qspi_probe(struct platfor - goto last_init_failed; - - fsl_qspi_clk_disable_unprep(q); -+ -+ for (i = 0; i < q->nor_num; i++) { -+ /* skip the holes */ -+ if (!q->has_second_chip) -+ i *= 2; -+ -+ ret = mtd_device_register(&q->nor[i].mtd, NULL, 0); -+ if (ret) -+ goto last_init_failed; -+ } - return 0; - - last_init_failed: diff --git a/target/linux/layerscape/patches-4.4/1239-mtd-extend-physmap_of-to-let-the-device-tree-specify.patch b/target/linux/layerscape/patches-4.4/1239-mtd-extend-physmap_of-to-let-the-device-tree-specify.patch deleted file mode 100644 index 0fdbb7ea38..0000000000 --- a/target/linux/layerscape/patches-4.4/1239-mtd-extend-physmap_of-to-let-the-device-tree-specify.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 6b54054c4053215fe4add195c67daca9a466ba92 Mon Sep 17 00:00:00 2001 -From: "ying.zhang" -Date: Fri, 23 Dec 2016 22:21:22 +0800 -Subject: [PATCH] mtd: extend physmap_of to let the device tree specify the - parition probe - -This is to support custom partitioning schemes for embedded PPC. To use -define your own mtd_part_parser and then add something like: - linux,part-probe = "my_probe", "cmdlinepart"; - To the board's dts file. - -If linux,part-probe is not specified then this behaves the same as before. - -Signed-off-by: Jason Gunthorpe -Signed-off-by: David Woodhouse ---- - drivers/mtd/maps/physmap_of.c | 46 ++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 45 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/maps/physmap_of.c -+++ b/drivers/mtd/maps/physmap_of.c -@@ -112,9 +112,47 @@ static struct mtd_info *obsolete_probe(s - static const char * const part_probe_types_def[] = { - "cmdlinepart", "RedBoot", "ofpart", "ofoldpart", NULL }; - -+static const char * const *of_get_probes(struct device_node *dp) -+{ -+ const char *cp; -+ int cplen; -+ unsigned int l; -+ unsigned int count; -+ const char **res; -+ -+ cp = of_get_property(dp, "linux,part-probe", &cplen); -+ if (cp == NULL) -+ return part_probe_types_def; -+ -+ count = 0; -+ for (l = 0; l != cplen; l++) -+ if (cp[l] == 0) -+ count++; -+ -+ res = kzalloc((count + 1)*sizeof(*res), GFP_KERNEL); -+ if (!res) -+ return NULL; -+ count = 0; -+ while (cplen > 0) { -+ res[count] = cp; -+ l = strlen(cp) + 1; -+ cp += l; -+ cplen -= l; -+ count++; -+ } -+ return res; -+} -+ -+static void of_free_probes(const char * const *probes) -+{ -+ if (probes != part_probe_types_def) -+ kfree(probes); -+} -+ - static const struct of_device_id of_flash_match[]; - static int of_flash_probe(struct platform_device *dev) - { -+ const char * const *part_probe_types; - const struct of_device_id *match; - struct device_node *dp = dev->dev.of_node; - struct resource res; -@@ -273,8 +311,14 @@ static int of_flash_probe(struct platfor - goto err_out; - - ppdata.of_node = dp; -- mtd_device_parse_register(info->cmtd, part_probe_types_def, &ppdata, -+ part_probe_types = of_get_probes(dp); -+ if (!part_probe_types) { -+ err = -ENOMEM; -+ goto err_out; -+ } -+ mtd_device_parse_register(info->cmtd, part_probe_types, &ppdata, - NULL, 0); -+ of_free_probes(part_probe_types); - - kfree(mtd_list); - diff --git a/target/linux/layerscape/patches-4.4/2006-armv8-aarch32-Add-the-default-config-ls_aarch32_defc.patch b/target/linux/layerscape/patches-4.4/2006-armv8-aarch32-Add-the-default-config-ls_aarch32_defc.patch deleted file mode 100644 index 22ce5a9b96..0000000000 --- a/target/linux/layerscape/patches-4.4/2006-armv8-aarch32-Add-the-default-config-ls_aarch32_defc.patch +++ /dev/null @@ -1,209 +0,0 @@ -From 4c4e5c275a0e37570d6267802e66a350b0b93dcd Mon Sep 17 00:00:00 2001 -From: Alison Wang -Date: Tue, 17 May 2016 17:30:19 +0800 -Subject: [PATCH 06/70] armv8: aarch32: Add the default config - ls_aarch32_defconfig - -ls_aarch32_defconfig is used as the default config for running 32-bit -Linux. - -Signed-off-by: Ebony Zhu -Signed-off-by: Alison Wang ---- - arch/arm/configs/ls_aarch32_defconfig | 190 +++++++++++++++++++++++++++++++++ - 1 file changed, 190 insertions(+) - create mode 100644 arch/arm/configs/ls_aarch32_defconfig - ---- /dev/null -+++ b/arch/arm/configs/ls_aarch32_defconfig -@@ -0,0 +1,190 @@ -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_SYSVIPC=y -+CONFIG_POSIX_MQUEUE=y -+# CONFIG_CROSS_MEMORY_ATTACH is not set -+CONFIG_IRQ_DOMAIN_DEBUG=y -+CONFIG_NO_HZ_IDLE=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_LOG_BUF_SHIFT=16 -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_CC_OPTIMIZE_FOR_SIZE=y -+CONFIG_SYSCTL_SYSCALL=y -+CONFIG_KALLSYMS_ALL=y -+CONFIG_EMBEDDED=y -+# CONFIG_VM_EVENT_COUNTERS is not set -+# CONFIG_SLUB_DEBUG is not set -+CONFIG_PROFILING=y -+CONFIG_OPROFILE=y -+CONFIG_KPROBES=y -+CONFIG_JUMP_LABEL=y -+CONFIG_MODULES=y -+CONFIG_MODULE_FORCE_LOAD=y -+CONFIG_MODULE_UNLOAD=y -+# CONFIG_BLK_DEV_BSG is not set -+CONFIG_BLK_CMDLINE_PARSER=y -+CONFIG_ARCH_MXC=y -+CONFIG_ARCH_LAYERSCAPE=y -+CONFIG_ARM_LPAE=y -+# CONFIG_CACHE_L2X0 is not set -+CONFIG_PCI=y -+CONFIG_PCI_MSI=y -+CONFIG_PCI_HOST_GENERIC=y -+CONFIG_PCI_LAYERSCAPE=y -+CONFIG_SMP=y -+CONFIG_VMSPLIT_2G=y -+CONFIG_PREEMPT_VOLUNTARY=y -+CONFIG_AEABI=y -+CONFIG_HIGHMEM=y -+CONFIG_CLEANCACHE=y -+CONFIG_FRONTSWAP=y -+CONFIG_CMDLINE="console=ttyS0,115200" -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_IDLE=y -+CONFIG_VFP=y -+CONFIG_NEON=y -+CONFIG_KERNEL_MODE_NEON=y -+CONFIG_BINFMT_MISC=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_UNIX_DIAG=y -+CONFIG_XFRM_USER=y -+CONFIG_NET_KEY=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_ADVANCED_ROUTER=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_MROUTE=y -+CONFIG_INET_AH=y -+CONFIG_INET_ESP=y -+CONFIG_INET_IPCOMP=y -+CONFIG_INET_UDP_DIAG=y -+# CONFIG_IPV6 is not set -+CONFIG_NETFILTER=y -+CONFIG_CAN=y -+# CONFIG_CAN_BCM is not set -+# CONFIG_CAN_GW is not set -+CONFIG_CAN_FLEXCAN=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+# CONFIG_FW_LOADER is not set -+CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_BLOCK=y -+CONFIG_MTD_CFI=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_BE_BYTE_SWAP=y -+CONFIG_MTD_CFI_GEOMETRY=y -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_CFI_STAA=y -+CONFIG_MTD_PHYSMAP_OF=y -+CONFIG_MTD_DATAFLASH=y -+CONFIG_MTD_SST25L=y -+CONFIG_MTD_NAND=y -+CONFIG_MTD_NAND_FSL_IFC=y -+CONFIG_MTD_SPI_NOR=y -+CONFIG_SPI_FSL_QUADSPI=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_COUNT=8 -+CONFIG_BLK_DEV_RAM_SIZE=262144 -+CONFIG_NETDEVICES=y -+# CONFIG_NET_VENDOR_FREESCALE is not set -+CONFIG_E1000=y -+CONFIG_E1000E=y -+CONFIG_PHYLIB=y -+CONFIG_AT803X_PHY=y -+CONFIG_VITESSE_PHY=y -+CONFIG_BROADCOM_PHY=y -+CONFIG_REALTEK_PHY=y -+CONFIG_NATIONAL_PHY=y -+CONFIG_MICREL_PHY=y -+CONFIG_MDIO_BUS_MUX_MMIOREG=y -+CONFIG_INPUT_EVDEV=y -+# CONFIG_MOUSE_PS2_TRACKPOINT is not set -+CONFIG_SERIO_SERPORT=m -+# CONFIG_CONSOLE_TRANSLATIONS is not set -+CONFIG_SERIAL_8250=y -+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -+CONFIG_SERIAL_8250_CONSOLE=y -+CONFIG_SERIAL_8250_EXTENDED=y -+CONFIG_SERIAL_8250_SHARE_IRQ=y -+CONFIG_SERIAL_OF_PLATFORM=y -+CONFIG_SERIAL_FSL_LPUART=y -+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -+CONFIG_HW_RANDOM=y -+CONFIG_I2C=y -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_MUX=y -+CONFIG_I2C_MUX_PCA954x=y -+CONFIG_I2C_IMX=y -+CONFIG_SPI=y -+CONFIG_SPI_BITBANG=y -+CONFIG_SPI_FSL_DSPI=y -+CONFIG_PTP_1588_CLOCK=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_GPIO_MPC8XXX=y -+CONFIG_SENSORS_LTC2945=y -+CONFIG_SENSORS_LM90=y -+CONFIG_SENSORS_INA2XX=y -+CONFIG_WATCHDOG=y -+CONFIG_IMX2_WDT=y -+CONFIG_MFD_SYSCON=y -+CONFIG_FB=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_MMC=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_OF_ESDHC=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_DRV_DS3232=y -+CONFIG_DMADEVICES=y -+CONFIG_FSL_EDMA=y -+CONFIG_CLK_QORIQ=y -+# CONFIG_IOMMU_SUPPORT is not set -+CONFIG_MEMORY=y -+CONFIG_PWM=y -+CONFIG_PWM_FSL_FTM=y -+# CONFIG_RESET_CONTROLLER is not set -+CONFIG_EXT2_FS=y -+CONFIG_EXT2_FS_XATTR=y -+CONFIG_EXT3_FS=y -+CONFIG_EXT4_FS=y -+CONFIG_FANOTIFY=y -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_MSDOS_FS=y -+CONFIG_VFAT_FS=y -+CONFIG_NTFS_FS=m -+CONFIG_TMPFS=y -+CONFIG_TMPFS_POSIX_ACL=y -+CONFIG_CONFIGFS_FS=y -+CONFIG_JFFS2_FS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V4=y -+CONFIG_ROOT_NFS=y -+CONFIG_NLS_DEFAULT="cp437" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_ISO8859_2=y -+CONFIG_NLS_ISO8859_15=y -+CONFIG_NLS_UTF8=y -+CONFIG_DEBUG_FS=y -+CONFIG_DEBUG_SECTION_MISMATCH=y -+CONFIG_MAGIC_SYSRQ=y -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_FTRACE is not set -+CONFIG_PID_IN_CONTEXTIDR=y -+CONFIG_CRYPTO_LZO=y -+# CONFIG_CRYPTO_ANSI_CPRNG is not set -+# CONFIG_CRYPTO_HW is not set -+CONFIG_CRC_CCITT=m -+CONFIG_CRC_T10DIF=y -+CONFIG_CRC7=m -+CONFIG_LIBCRC32C=m diff --git a/target/linux/layerscape/patches-4.4/2027-armv8-aarch32-update-defconfig-for-LayerScape-SoC.patch b/target/linux/layerscape/patches-4.4/2027-armv8-aarch32-update-defconfig-for-LayerScape-SoC.patch deleted file mode 100644 index 97f51137b8..0000000000 --- a/target/linux/layerscape/patches-4.4/2027-armv8-aarch32-update-defconfig-for-LayerScape-SoC.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 0cc4fd2e52f23f9b35dfdac80021da97ac6c2c52 Mon Sep 17 00:00:00 2001 -From: Pan Jiafei -Date: Tue, 24 May 2016 16:15:49 +0800 -Subject: [PATCH 27/70] armv8: aarch32: update defconfig for LayerScape SoC - -Enable QBMan, FMD, DPAA ethernet, kernel bridge, ATA, -DMA_CMA, USB_STORAGE, PHY etc. - -Signed-off-by: Pan Jiafei ---- - arch/arm/configs/ls_aarch32_defconfig | 20 +++++++++++++++++++- - 1 file changed, 19 insertions(+), 1 deletion(-) - ---- a/arch/arm/configs/ls_aarch32_defconfig -+++ b/arch/arm/configs/ls_aarch32_defconfig -@@ -26,6 +26,7 @@ CONFIG_ARCH_MXC=y - CONFIG_ARCH_LAYERSCAPE=y - CONFIG_ARM_LPAE=y - # CONFIG_CACHE_L2X0 is not set -+CONFIG_HAS_FSL_QBMAN=y - CONFIG_PCI=y - CONFIG_PCI_MSI=y - CONFIG_PCI_HOST_GENERIC=y -@@ -36,6 +37,7 @@ CONFIG_PREEMPT_VOLUNTARY=y - CONFIG_AEABI=y - CONFIG_HIGHMEM=y - CONFIG_CLEANCACHE=y -+CONFIG_CMA=y - CONFIG_FRONTSWAP=y - CONFIG_CMDLINE="console=ttyS0,115200" - CONFIG_CPU_FREQ=y -@@ -62,6 +64,7 @@ CONFIG_INET_IPCOMP=y - CONFIG_INET_UDP_DIAG=y - # CONFIG_IPV6 is not set - CONFIG_NETFILTER=y -+CONFIG_BRIDGE=y - CONFIG_CAN=y - # CONFIG_CAN_BCM is not set - # CONFIG_CAN_GW is not set -@@ -69,6 +72,7 @@ CONFIG_CAN_FLEXCAN=y - CONFIG_DEVTMPFS=y - CONFIG_DEVTMPFS_MOUNT=y - # CONFIG_FW_LOADER is not set -+CONFIG_DMA_CMA=y - CONFIG_MTD=y - CONFIG_MTD_CMDLINE_PARTS=y - CONFIG_MTD_BLOCK=y -@@ -81,17 +85,26 @@ CONFIG_MTD_CFI_AMDSTD=y - CONFIG_MTD_CFI_STAA=y - CONFIG_MTD_PHYSMAP_OF=y - CONFIG_MTD_DATAFLASH=y -+CONFIG_MTD_M25P80=y - CONFIG_MTD_SST25L=y - CONFIG_MTD_NAND=y - CONFIG_MTD_NAND_FSL_IFC=y - CONFIG_MTD_SPI_NOR=y -+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y - CONFIG_SPI_FSL_QUADSPI=y -+CONFIG_BLK_DEV_SD=y -+CONFIG_ATA=y - CONFIG_BLK_DEV_LOOP=y - CONFIG_BLK_DEV_RAM=y - CONFIG_BLK_DEV_RAM_COUNT=8 - CONFIG_BLK_DEV_RAM_SIZE=262144 - CONFIG_NETDEVICES=y --# CONFIG_NET_VENDOR_FREESCALE is not set -+CONFIG_NET_VENDOR_FREESCALE is not set -+CONFIG_FSL_BMAN=y -+CONFIG_FSL_QMAN=y -+CONFIG_FSL_SDK_FMAN=y -+CONFIG_FMAN_ARM=y -+CONFIG_FSL_SDK_DPAA_ETH=y - CONFIG_E1000=y - CONFIG_E1000E=y - CONFIG_PHYLIB=y -@@ -101,6 +114,8 @@ CONFIG_BROADCOM_PHY=y - CONFIG_REALTEK_PHY=y - CONFIG_NATIONAL_PHY=y - CONFIG_MICREL_PHY=y -+CONFIG_FIXED_PHY=y -+CONFIG_FSL_XGMAC_MDIO=y - CONFIG_MDIO_BUS_MUX_MMIOREG=y - CONFIG_INPUT_EVDEV=y - # CONFIG_MOUSE_PS2_TRACKPOINT is not set -@@ -135,6 +150,8 @@ CONFIG_MFD_SYSCON=y - CONFIG_FB=y - CONFIG_USB=y - CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_STORAGE=y - CONFIG_MMC=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_PLTFM=y -@@ -143,6 +160,7 @@ CONFIG_RTC_CLASS=y - CONFIG_RTC_DRV_DS3232=y - CONFIG_DMADEVICES=y - CONFIG_FSL_EDMA=y -+CONFIG_STAGING=y - CONFIG_CLK_QORIQ=y - # CONFIG_IOMMU_SUPPORT is not set - CONFIG_MEMORY=y diff --git a/target/linux/layerscape/patches-4.4/2119-armv8-aarch32-defconfig-Enable-CAAM-support.patch b/target/linux/layerscape/patches-4.4/2119-armv8-aarch32-defconfig-Enable-CAAM-support.patch deleted file mode 100644 index 567195d1fa..0000000000 --- a/target/linux/layerscape/patches-4.4/2119-armv8-aarch32-defconfig-Enable-CAAM-support.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 035fe1e511e053c6650f37626deb5da76dcc1d92 Mon Sep 17 00:00:00 2001 -From: Ying Zhang -Date: Thu, 29 Sep 2016 11:29:48 +0800 -Subject: [PATCH 119/124] armv8: aarch32: defconfig: Enable CAAM support - -This patch is to enable the driver module for Freescale's Cryptographics -Accelerator and Assurance Module (CAAM) and related options. - -Signed-off-by: Alison Wang ---- - arch/arm/configs/ls_aarch32_defconfig | 9 +++++++-- - 1 file changed, 7 insertions(+), 2 deletions(-) - ---- a/arch/arm/configs/ls_aarch32_defconfig -+++ b/arch/arm/configs/ls_aarch32_defconfig -@@ -200,8 +200,13 @@ CONFIG_MAGIC_SYSRQ=y - # CONFIG_FTRACE is not set - CONFIG_PID_IN_CONTEXTIDR=y - CONFIG_CRYPTO_LZO=y --# CONFIG_CRYPTO_ANSI_CPRNG is not set --# CONFIG_CRYPTO_HW is not set -+CONFIG_CRYPTO_ANSI_CPRNG=y -+CONFIG_CRYPTO_DEV_FSL_CAAM=y -+CONFIG_ARM_CRYPTO=y -+CONFIG_CRYPTO_SHA1_ARM_NEON=y -+CONFIG_CRYPTO_SHA256_ARM=y -+CONFIG_CRYPTO_SHA512_ARM_NEON=y -+CONFIG_CRYPTO_AES_ARM_BS=y - CONFIG_CRC_CCITT=m - CONFIG_CRC_T10DIF=y - CONFIG_CRC7=m diff --git a/target/linux/layerscape/patches-4.4/2120-armv8-aarch32-defconfig-Enable-firmware-loading.patch b/target/linux/layerscape/patches-4.4/2120-armv8-aarch32-defconfig-Enable-firmware-loading.patch deleted file mode 100644 index 26a981c9ef..0000000000 --- a/target/linux/layerscape/patches-4.4/2120-armv8-aarch32-defconfig-Enable-firmware-loading.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 027ca2530ce94dd7d9954e57631aa34987db392e Mon Sep 17 00:00:00 2001 -From: Ying Zhang -Date: Thu, 29 Sep 2016 11:38:36 +0800 -Subject: [PATCH 120/124] armv8: aarch32: defconfig: Enable firmware loading - -As some modules require userspace firmware loading support, such as -PPFE, add this feature in the defconfig for AArch32 on ARMv8. - -Signed-off-by: Alison Wang ---- - arch/arm/configs/ls_aarch32_defconfig | 1 - - 1 file changed, 1 deletion(-) - ---- a/arch/arm/configs/ls_aarch32_defconfig -+++ b/arch/arm/configs/ls_aarch32_defconfig -@@ -71,7 +71,6 @@ CONFIG_CAN=y - CONFIG_CAN_FLEXCAN=y - CONFIG_DEVTMPFS=y - CONFIG_DEVTMPFS_MOUNT=y --# CONFIG_FW_LOADER is not set - CONFIG_DMA_CMA=y - CONFIG_MTD=y - CONFIG_MTD_CMDLINE_PARTS=y diff --git a/target/linux/layerscape/patches-4.4/2121-armv8-aarch32-defconfig-Enable-support-for-AHCI-SATA.patch b/target/linux/layerscape/patches-4.4/2121-armv8-aarch32-defconfig-Enable-support-for-AHCI-SATA.patch deleted file mode 100644 index a3a67c37bf..0000000000 --- a/target/linux/layerscape/patches-4.4/2121-armv8-aarch32-defconfig-Enable-support-for-AHCI-SATA.patch +++ /dev/null @@ -1,29 +0,0 @@ -From ff37b165bdb100450c7996c9fac0fad2e6ffe31d Mon Sep 17 00:00:00 2001 -From: Ying Zhang -Date: Thu, 29 Sep 2016 11:40:37 +0800 -Subject: [PATCH 121/124] armv8: aarch32: defconfig: Enable support for AHCI - SATA - -This patch is to enable support for the Freescale QorIQ AHCI SoC's -onboard AHCI SATA. - -Signed-off-by: Alison Wang ---- - arch/arm/configs/ls_aarch32_defconfig | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm/configs/ls_aarch32_defconfig -+++ b/arch/arm/configs/ls_aarch32_defconfig -@@ -92,7 +92,12 @@ CONFIG_MTD_SPI_NOR=y - CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y - CONFIG_SPI_FSL_QUADSPI=y - CONFIG_BLK_DEV_SD=y -+CONFIG_CHR_DEV_SG=y - CONFIG_ATA=y -+CONFIG_SATA_AHCI=y -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_QORIQ=y -+CONFIG_SATA_SIL24=y - CONFIG_BLK_DEV_LOOP=y - CONFIG_BLK_DEV_RAM=y - CONFIG_BLK_DEV_RAM_COUNT=8 diff --git a/target/linux/layerscape/patches-4.4/2122-armv8-aarch32-defconfig-Enable-USB-and-related-confi.patch b/target/linux/layerscape/patches-4.4/2122-armv8-aarch32-defconfig-Enable-USB-and-related-confi.patch deleted file mode 100644 index 83d372ba67..0000000000 --- a/target/linux/layerscape/patches-4.4/2122-armv8-aarch32-defconfig-Enable-USB-and-related-confi.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 913db32774fe5c818112232823edfda1a706552f Mon Sep 17 00:00:00 2001 -From: Ying Zhang -Date: Thu, 29 Sep 2016 11:42:40 +0800 -Subject: [PATCH 122/124] armv8: aarch32: defconfig: Enable USB and related - configuration options - -This patch is to enable USB and related configuration options for -AArch32 on ARMv8. - -Signed-off-by: Alison Wang ---- - arch/arm/configs/ls_aarch32_defconfig | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm/configs/ls_aarch32_defconfig -+++ b/arch/arm/configs/ls_aarch32_defconfig -@@ -154,8 +154,14 @@ CONFIG_MFD_SYSCON=y - CONFIG_FB=y - CONFIG_USB=y - CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_HCD_PLATFORM=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_HCD_PLATFORM=y -+CONFIG_USB_STORAGE=y - CONFIG_USB_DWC3=y - CONFIG_USB_STORAGE=y -+CONFIG_USB_ULPI=y - CONFIG_MMC=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_PLTFM=y diff --git a/target/linux/layerscape/patches-4.4/2123-armv8-aarch32-defconfig-Enable-KVM-related-configura.patch b/target/linux/layerscape/patches-4.4/2123-armv8-aarch32-defconfig-Enable-KVM-related-configura.patch deleted file mode 100644 index 4556ad9e00..0000000000 --- a/target/linux/layerscape/patches-4.4/2123-armv8-aarch32-defconfig-Enable-KVM-related-configura.patch +++ /dev/null @@ -1,59 +0,0 @@ -From dbf356cd062d6313f90323a77d4cf7c820dae40f Mon Sep 17 00:00:00 2001 -From: Ying Zhang -Date: Thu, 29 Sep 2016 13:51:32 +0800 -Subject: [PATCH 123/124] armv8: aarch32: defconfig: Enable KVM-related - configuration options - -This patch is to enable KVM-related configuration options for host and -guest. - -Signed-off-by: Alison Wang ---- - arch/arm/configs/ls_aarch32_defconfig | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm/configs/ls_aarch32_defconfig -+++ b/arch/arm/configs/ls_aarch32_defconfig -@@ -102,7 +102,11 @@ CONFIG_BLK_DEV_LOOP=y - CONFIG_BLK_DEV_RAM=y - CONFIG_BLK_DEV_RAM_COUNT=8 - CONFIG_BLK_DEV_RAM_SIZE=262144 -+CONFIG_VIRTIO_BLK=y - CONFIG_NETDEVICES=y -+CONFIG_TUN=y -+CONFIG_VIRTIO_NET=y -+CONFIG_VHOST_NET=y - CONFIG_NET_VENDOR_FREESCALE is not set - CONFIG_FSL_BMAN=y - CONFIG_FSL_QMAN=y -@@ -130,6 +134,8 @@ CONFIG_SERIAL_8250=y - CONFIG_SERIAL_8250_CONSOLE=y - CONFIG_SERIAL_8250_EXTENDED=y - CONFIG_SERIAL_8250_SHARE_IRQ=y -+CONFIG_SERIAL_AMBA_PL011=y -+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y - CONFIG_SERIAL_OF_PLATFORM=y - CONFIG_SERIAL_FSL_LPUART=y - CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -@@ -170,6 +176,7 @@ CONFIG_RTC_CLASS=y - CONFIG_RTC_DRV_DS3232=y - CONFIG_DMADEVICES=y - CONFIG_FSL_EDMA=y -+CONFIG_VIRTIO_PCI=y - CONFIG_STAGING=y - CONFIG_CLK_QORIQ=y - # CONFIG_IOMMU_SUPPORT is not set -@@ -191,6 +198,7 @@ CONFIG_VFAT_FS=y - CONFIG_NTFS_FS=m - CONFIG_TMPFS=y - CONFIG_TMPFS_POSIX_ACL=y -+CONFIG_HUGETLBFS=y - CONFIG_CONFIGFS_FS=y - CONFIG_JFFS2_FS=y - CONFIG_NFS_FS=y -@@ -221,3 +229,5 @@ CONFIG_CRC_CCITT=m - CONFIG_CRC_T10DIF=y - CONFIG_CRC7=m - CONFIG_LIBCRC32C=m -+CONFIG_VIRTUALIZATION=y -+CONFIG_KVM=y diff --git a/target/linux/layerscape/patches-4.4/2124-armv8-aarch32-defconfig-Enable-FTM-alarm-support.patch b/target/linux/layerscape/patches-4.4/2124-armv8-aarch32-defconfig-Enable-FTM-alarm-support.patch deleted file mode 100644 index ae05a88677..0000000000 --- a/target/linux/layerscape/patches-4.4/2124-armv8-aarch32-defconfig-Enable-FTM-alarm-support.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 6df7fdf7e0c76df7acc2d1a3a287bf094a94c4ff Mon Sep 17 00:00:00 2001 -From: Ying Zhang -Date: Thu, 29 Sep 2016 13:55:44 +0800 -Subject: [PATCH 124/124] armv8: aarch32: defconfig: Enable FTM alarm support - -This patch is to enable FTM alarm support. - -Signed-off-by: Alison Wang ---- - arch/arm/configs/ls_aarch32_defconfig | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm/configs/ls_aarch32_defconfig -+++ b/arch/arm/configs/ls_aarch32_defconfig -@@ -181,6 +181,8 @@ CONFIG_STAGING=y - CONFIG_CLK_QORIQ=y - # CONFIG_IOMMU_SUPPORT is not set - CONFIG_MEMORY=y -+CONFIG_LS_SOC_DRIVERS=y -+CONFIG_FTM_ALARM=y - CONFIG_PWM=y - CONFIG_PWM_FSL_FTM=y - # CONFIG_RESET_CONTROLLER is not set diff --git a/target/linux/layerscape/patches-4.4/3001-arm64-ls1043a-add-DTS-for-Freescale-LS1043A-SoC.patch b/target/linux/layerscape/patches-4.4/3001-arm64-ls1043a-add-DTS-for-Freescale-LS1043A-SoC.patch deleted file mode 100644 index 39a33282a9..0000000000 --- a/target/linux/layerscape/patches-4.4/3001-arm64-ls1043a-add-DTS-for-Freescale-LS1043A-SoC.patch +++ /dev/null @@ -1,552 +0,0 @@ -From 3ce895cbe3469bfcaa84674ec4f1b2d60e8b370b Mon Sep 17 00:00:00 2001 -From: Mingkai Hu -Date: Mon, 21 Jul 2014 14:48:42 +0800 -Subject: [PATCH 01/70] arm64/ls1043a: add DTS for Freescale LS1043A SoC - -LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks -similar to LS1021a which complies to Chassis 2.1 spec. - -Following levels of DTSI/DTS files have been created for the -LS1043A SoC family: - -- fsl-ls1043a.dtsi: - DTS-Include file for FSL LS1043A SoC. - -Signed-off-by: Li Yang -Signed-off-by: Hou Zhiqiang -Signed-off-by: Mingkai Hu -Signed-off-by: Wenbin Song -Signed-off-by: Mingkai Hu ---- - arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 525 ++++++++++++++++++++++++ - 1 file changed, 525 insertions(+) - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi - ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -@@ -0,0 +1,525 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1043A family SoC. -+ * -+ * Copyright 2014-2015, Freescale Semiconductor -+ * -+ * Mingkai Hu -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/ { -+ compatible = "fsl,ls1043a"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ /* -+ * We expect the enable-method for cpu's to be "psci", but this -+ * is dependent on the SoC FW, which will fill this in. -+ * -+ * Currently supported enable-method is psci v0.2 -+ */ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0 0x0>; -+ clocks = <&clockgen 1 0>; -+ }; -+ -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0 0x1>; -+ clocks = <&clockgen 1 0>; -+ }; -+ -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0 0x2>; -+ clocks = <&clockgen 1 0>; -+ }; -+ -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0 0x3>; -+ clocks = <&clockgen 1 0>; -+ }; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x0 0x80000000 0 0x80000000>; -+ /* DRAM space 1, size: 2GiB DRAM */ -+ }; -+ -+ sysclk: sysclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "sysclk"; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = <1 13 0x1>, /* Physical Secure PPI */ -+ <1 14 0x1>, /* Physical Non-Secure PPI */ -+ <1 11 0x1>, /* Virtual PPI */ -+ <1 10 0x1>; /* Hypervisor PPI */ -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = <0 106 0x4>, -+ <0 107 0x4>, -+ <0 95 0x4>, -+ <0 97 0x4>; -+ interrupt-affinity = <&cpu0>, -+ <&cpu1>, -+ <&cpu2>, -+ <&cpu3>; -+ }; -+ -+ gic: interrupt-controller@1400000 { -+ compatible = "arm,gic-400"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */ -+ <0x0 0x1402000 0 0x2000>, /* GICC */ -+ <0x0 0x1404000 0 0x2000>, /* GICH */ -+ <0x0 0x1406000 0 0x2000>; /* GICV */ -+ interrupts = <1 9 0xf08>; -+ }; -+ -+ soc { -+ compatible = "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ clockgen: clocking@1ee1000 { -+ compatible = "fsl,ls1043a-clockgen"; -+ reg = <0x0 0x1ee1000 0x0 0x1000>; -+ #clock-cells = <2>; -+ clocks = <&sysclk>; -+ }; -+ -+ scfg: scfg@1570000 { -+ compatible = "fsl,ls1043a-scfg", "syscon"; -+ reg = <0x0 0x1570000 0x0 0x10000>; -+ big-endian; -+ }; -+ -+ dcfg: dcfg@1ee0000 { -+ compatible = "fsl,ls1043a-dcfg", "syscon"; -+ reg = <0x0 0x1ee0000 0x0 0x10000>; -+ }; -+ -+ ifc: ifc@1530000 { -+ compatible = "fsl,ifc", "simple-bus"; -+ reg = <0x0 0x1530000 0x0 0x10000>; -+ interrupts = <0 43 0x4>; -+ }; -+ -+ esdhc: esdhc@1560000 { -+ compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; -+ reg = <0x0 0x1560000 0x0 0x10000>; -+ interrupts = <0 62 0x4>; -+ clock-frequency = <0>; -+ voltage-ranges = <1800 1800 3300 3300>; -+ sdhci,auto-cmd12; -+ big-endian; -+ bus-width = <4>; -+ }; -+ -+ dspi0: dspi@2100000 { -+ compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2100000 0x0 0x10000>; -+ interrupts = <0 64 0x4>; -+ clock-names = "dspi"; -+ clocks = <&clockgen 4 0>; -+ spi-num-chipselects = <5>; -+ big-endian; -+ status = "disabled"; -+ }; -+ -+ dspi1: dspi@2110000 { -+ compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2110000 0x0 0x10000>; -+ interrupts = <0 65 0x4>; -+ clock-names = "dspi"; -+ clocks = <&clockgen 4 0>; -+ spi-num-chipselects = <5>; -+ big-endian; -+ status = "disabled"; -+ }; -+ -+ i2c0: i2c@2180000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2180000 0x0 0x10000>; -+ interrupts = <0 56 0x4>; -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 0>; -+ dmas = <&edma0 1 39>, -+ <&edma0 1 38>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@2190000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2190000 0x0 0x10000>; -+ interrupts = <0 57 0x4>; -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 0>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@21a0000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x21a0000 0x0 0x10000>; -+ interrupts = <0 58 0x4>; -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 0>; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@21b0000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x21b0000 0x0 0x10000>; -+ interrupts = <0 59 0x4>; -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 0>; -+ status = "disabled"; -+ }; -+ -+ duart0: serial@21c0500 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x00 0x21c0500 0x0 0x100>; -+ interrupts = <0 54 0x4>; -+ clocks = <&clockgen 4 0>; -+ }; -+ -+ duart1: serial@21c0600 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x00 0x21c0600 0x0 0x100>; -+ interrupts = <0 54 0x4>; -+ clocks = <&clockgen 4 0>; -+ }; -+ -+ duart2: serial@21d0500 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21d0500 0x0 0x100>; -+ interrupts = <0 55 0x4>; -+ clocks = <&clockgen 4 0>; -+ }; -+ -+ duart3: serial@21d0600 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21d0600 0x0 0x100>; -+ interrupts = <0 55 0x4>; -+ clocks = <&clockgen 4 0>; -+ }; -+ -+ gpio1: gpio@2300000 { -+ compatible = "fsl,ls1043a-gpio"; -+ reg = <0x0 0x2300000 0x0 0x10000>; -+ interrupts = <0 66 0x4>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio2: gpio@2310000 { -+ compatible = "fsl,ls1043a-gpio"; -+ reg = <0x0 0x2310000 0x0 0x10000>; -+ interrupts = <0 67 0x4>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio3: gpio@2320000 { -+ compatible = "fsl,ls1043a-gpio"; -+ reg = <0x0 0x2320000 0x0 0x10000>; -+ interrupts = <0 68 0x4>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio4: gpio@2330000 { -+ compatible = "fsl,ls1043a-gpio"; -+ reg = <0x0 0x2330000 0x0 0x10000>; -+ interrupts = <0 134 0x4>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ lpuart0: serial@2950000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2950000 0x0 0x1000>; -+ interrupts = <0 48 0x4>; -+ clocks = <&clockgen 0 0>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart1: serial@2960000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2960000 0x0 0x1000>; -+ interrupts = <0 49 0x4>; -+ clocks = <&clockgen 4 0>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart2: serial@2970000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2970000 0x0 0x1000>; -+ interrupts = <0 50 0x4>; -+ clocks = <&clockgen 4 0>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart3: serial@2980000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2980000 0x0 0x1000>; -+ interrupts = <0 51 0x4>; -+ clocks = <&clockgen 4 0>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart4: serial@2990000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2990000 0x0 0x1000>; -+ interrupts = <0 52 0x4>; -+ clocks = <&clockgen 4 0>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart5: serial@29a0000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x29a0000 0x0 0x1000>; -+ interrupts = <0 53 0x4>; -+ clocks = <&clockgen 4 0>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ wdog0: wdog@2ad0000 { -+ compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; -+ reg = <0x0 0x2ad0000 0x0 0x10000>; -+ interrupts = <0 83 0x4>; -+ clocks = <&clockgen 4 0>; -+ clock-names = "wdog"; -+ big-endian; -+ }; -+ -+ edma0: edma@2c00000 { -+ #dma-cells = <2>; -+ compatible = "fsl,vf610-edma"; -+ reg = <0x0 0x2c00000 0x0 0x10000>, -+ <0x0 0x2c10000 0x0 0x10000>, -+ <0x0 0x2c20000 0x0 0x10000>; -+ interrupts = <0 103 0x4>, -+ <0 103 0x4>; -+ interrupt-names = "edma-tx", "edma-err"; -+ dma-channels = <32>; -+ big-endian; -+ clock-names = "dmamux0", "dmamux1"; -+ clocks = <&clockgen 4 0>, -+ <&clockgen 4 0>; -+ }; -+ -+ usb0: usb3@2f00000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x2f00000 0x0 0x10000>; -+ interrupts = <0 60 0x4>; -+ dr_mode = "host"; -+ }; -+ -+ usb1: usb3@3000000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3000000 0x0 0x10000>; -+ interrupts = <0 61 0x4>; -+ dr_mode = "host"; -+ }; -+ -+ usb2: usb3@3100000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3100000 0x0 0x10000>; -+ interrupts = <0 63 0x4>; -+ dr_mode = "host"; -+ }; -+ -+ sata: sata@3200000 { -+ compatible = "fsl,ls1043a-ahci"; -+ reg = <0x0 0x3200000 0x0 0x10000>; -+ interrupts = <0 69 0x4>; -+ clocks = <&clockgen 4 0>; -+ }; -+ -+ msi1: msi-controller1@1571000 { -+ compatible = "fsl,1s1043a-msi"; -+ reg = <0x0 0x1571000 0x0 0x4>, -+ <0x0 0x1571004 0x0 0x4>; -+ reg-names = "msiir", "msir"; -+ msi-controller; -+ interrupts = <0 116 0x4>; -+ }; -+ -+ msi2: msi-controller2@1572000 { -+ compatible = "fsl,1s1043a-msi"; -+ reg = <0x0 0x1572000 0x0 0x4>, -+ <0x0 0x1572004 0x0 0x4>; -+ reg-names = "msiir", "msir"; -+ msi-controller; -+ interrupts = <0 126 0x4>; -+ }; -+ -+ msi3: msi-controller3@1573000 { -+ compatible = "fsl,1s1043a-msi"; -+ reg = <0x0 0x1573000 0x0 0x4>, -+ <0x0 0x1573004 0x0 0x4>; -+ reg-names = "msiir", "msir"; -+ msi-controller; -+ interrupts = <0 160 0x4>; -+ }; -+ -+ pcie@3400000 { -+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ -+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 118 0x4>, /* controller interrupt */ -+ <0 117 0x4>; /* PME interrupt */ -+ interrupt-names = "intr", "pme"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&msi1>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, -+ <0000 0 0 2 &gic 0 111 0x4>, -+ <0000 0 0 3 &gic 0 112 0x4>, -+ <0000 0 0 4 &gic 0 113 0x4>; -+ }; -+ -+ pcie@3500000 { -+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ -+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 128 0x4>, -+ <0 127 0x4>; -+ interrupt-names = "intr", "pme"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ num-lanes = <2>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&msi2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, -+ <0000 0 0 2 &gic 0 121 0x4>, -+ <0000 0 0 3 &gic 0 122 0x4>, -+ <0000 0 0 4 &gic 0 123 0x4>; -+ }; -+ -+ pcie@3600000 { -+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ -+ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 162 0x4>, -+ <0 161 0x4>; -+ interrupt-names = "intr", "pme"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ num-lanes = <2>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&msi3>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, -+ <0000 0 0 2 &gic 0 155 0x4>, -+ <0000 0 0 3 &gic 0 156 0x4>, -+ <0000 0 0 4 &gic 0 157 0x4>; -+ }; -+ }; -+ -+}; diff --git a/target/linux/layerscape/patches-4.4/3002-dts-ls1043a-add-LS1043ARDB-board-support.patch b/target/linux/layerscape/patches-4.4/3002-dts-ls1043a-add-LS1043ARDB-board-support.patch deleted file mode 100644 index f36509d95c..0000000000 --- a/target/linux/layerscape/patches-4.4/3002-dts-ls1043a-add-LS1043ARDB-board-support.patch +++ /dev/null @@ -1,150 +0,0 @@ -From 57d949256241fb79b669bbca0426c2d74a3dfc6e Mon Sep 17 00:00:00 2001 -From: Shaohui Xie -Date: Fri, 8 Jul 2016 10:27:39 +0800 -Subject: [PATCH 02/70] dts/ls1043a: add LS1043ARDB board support - -commit 9a6fce16a82d3412c9350b9f08eacebaa81c0a3d -[context adjustment] - -Signed-off-by: Shaohui Xie -Signed-off-by: Mingkai Hu -Signed-off-by: Wenbin Song -Signed-off-by: Hou Zhiqiang -Signed-off-by: Mingkai Hu -Integrated-by: Zhao Qiang ---- - arch/arm64/boot/dts/freescale/Makefile | 1 + - arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 117 +++++++++++++++++++++ - 2 files changed, 118 insertions(+) - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts - ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -1,6 +1,7 @@ - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb - - always := $(dtb-y) - subdir-y := $(dts-dirs) ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts -@@ -0,0 +1,117 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1043A family SoC. -+ * -+ * Copyright 2014-2015, Freescale Semiconductor -+ * -+ * Mingkai Hu -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+#include "fsl-ls1043a.dtsi" -+ -+/ { -+ model = "LS1043A RDB Board"; -+ compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ ina220@40 { -+ compatible = "ti,ina220"; -+ reg = <0x40>; -+ shunt-resistor = <1000>; -+ }; -+ adt7461a@4c { -+ compatible = "adi,adt7461"; -+ reg = <0x4c>; -+ }; -+ eeprom@56 { -+ compatible = "at24,24c512"; -+ reg = <0x52>; -+ }; -+ eeprom@57 { -+ compatible = "at24,24c512"; -+ reg = <0x53>; -+ }; -+ rtc@68 { -+ compatible = "pericom,pt7c4338"; -+ reg = <0x68>; -+ }; -+}; -+ -+&ifc { -+ status = "okay"; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ /* NOR, NAND Flashes and FPGA on board */ -+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000 -+ 0x1 0x0 0x0 0x7e800000 0x00010000 -+ 0x2 0x0 0x0 0x7fb00000 0x00000100>; -+ -+ nor@0,0 { -+ compatible = "cfi-flash"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x0 0x0 0x8000000>; -+ bank-width = <2>; -+ device-width = <1>; -+ }; -+ -+ nand@1,0 { -+ compatible = "fsl,ifc-nand"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x1 0x0 0x10000>; -+ }; -+ -+ cpld: board-control@2,0 { -+ compatible = "fsl,ls1043ardb-cpld"; -+ reg = <0x2 0x0 0x0000100>; -+ }; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+ -+&duart1 { -+ status = "okay"; -+}; diff --git a/target/linux/layerscape/patches-4.4/3003-arm64-dts-Update-address-cells-and-reg-properties-of.patch b/target/linux/layerscape/patches-4.4/3003-arm64-dts-Update-address-cells-and-reg-properties-of.patch deleted file mode 100644 index 20cf8522a7..0000000000 --- a/target/linux/layerscape/patches-4.4/3003-arm64-dts-Update-address-cells-and-reg-properties-of.patch +++ /dev/null @@ -1,141 +0,0 @@ -From 3970a709eb4c25e298e11cfe0ea7412bb2139197 Mon Sep 17 00:00:00 2001 -From: Alison Wang -Date: Fri, 8 Jul 2016 10:50:46 +0800 -Subject: [PATCH 03/70] arm64: dts: Update address-cells and reg properties of - cpu nodes - -commit 67161e229a59faf81732892b45a9ab3bae62ea18 -[context adjustment] - -MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and -LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1, -since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update -the #address-cells and reg properties accordingly. - -Signed-off-by: Alison Wang -Integrated-by: Zhao Qiang ---- - arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 10 +++++----- - arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 18 +++++++++--------- - 2 files changed, 14 insertions(+), 14 deletions(-) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -@@ -51,7 +51,7 @@ - #size-cells = <2>; - - cpus { -- #address-cells = <2>; -+ #address-cells = <1>; - #size-cells = <0>; - - /* -@@ -63,28 +63,28 @@ - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; -- reg = <0x0 0x0>; -+ reg = <0x0>; - clocks = <&clockgen 1 0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; -- reg = <0x0 0x1>; -+ reg = <0x1>; - clocks = <&clockgen 1 0>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; -- reg = <0x0 0x2>; -+ reg = <0x2>; - clocks = <&clockgen 1 0>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; -- reg = <0x0 0x3>; -+ reg = <0x3>; - clocks = <&clockgen 1 0>; - }; - }; ---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi -@@ -51,7 +51,7 @@ - #size-cells = <2>; - - cpus { -- #address-cells = <2>; -+ #address-cells = <1>; - #size-cells = <0>; - - /* -@@ -65,56 +65,56 @@ - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; -- reg = <0x0 0x0>; -+ reg = <0x0>; - clocks = <&clockgen 1 0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; -- reg = <0x0 0x1>; -+ reg = <0x1>; - clocks = <&clockgen 1 0>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; -- reg = <0x0 0x100>; -+ reg = <0x100>; - clocks = <&clockgen 1 1>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; -- reg = <0x0 0x101>; -+ reg = <0x101>; - clocks = <&clockgen 1 1>; - }; - - cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; -- reg = <0x0 0x200>; -+ reg = <0x200>; - clocks = <&clockgen 1 2>; - }; - - cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; -- reg = <0x0 0x201>; -+ reg = <0x201>; - clocks = <&clockgen 1 2>; - }; - - cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; -- reg = <0x0 0x300>; -+ reg = <0x300>; - clocks = <&clockgen 1 3>; - }; - - cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; -- reg = <0x0 0x301>; -+ reg = <0x301>; - clocks = <&clockgen 1 3>; - }; - }; diff --git a/target/linux/layerscape/patches-4.4/3004-armv8-aarch32-Add-ITS-file-for-AArch32-Linux-on-LS10.patch b/target/linux/layerscape/patches-4.4/3004-armv8-aarch32-Add-ITS-file-for-AArch32-Linux-on-LS10.patch deleted file mode 100644 index 940d1970ae..0000000000 --- a/target/linux/layerscape/patches-4.4/3004-armv8-aarch32-Add-ITS-file-for-AArch32-Linux-on-LS10.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 503f48a0a43ddf20098b2a5ec2c3d9d91775e441 Mon Sep 17 00:00:00 2001 -From: Alison Wang -Date: Wed, 9 Dec 2015 10:53:04 +0800 -Subject: [PATCH 04/70] armv8: aarch32: Add ITS file for AArch32 Linux on - LS1043ARDB - -kernel-ls1043a-rdb-aarch32.its is added to load kernel, DTB -and root filesystrem together. - -Signed-off-by: Alison Wang ---- - kernel-ls1043a-rdb-aarch32.its | 53 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 53 insertions(+) - create mode 100644 kernel-ls1043a-rdb-aarch32.its - ---- /dev/null -+++ b/kernel-ls1043a-rdb-aarch32.its -@@ -0,0 +1,53 @@ -+/* -+ * Copyright (C) 2015, Freescale Semiconductor -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+ -+/ { -+ description = "RDB Image file for the LS1043A Linux Kernel"; -+ #address-cells = <1>; -+ -+ images { -+ kernel@1 { -+ description = "ARM32 Linux kernel"; -+ data = /incbin/("./arch/arm/boot/zImage"); -+ type = "kernel"; -+ arch = "arm"; -+ os = "linux"; -+ compression = "none"; -+ load = <0x80008000>; -+ entry = <0x80008000>; -+ }; -+ fdt@1 { -+ description = "Flattened Device Tree blob"; -+ data = /incbin/("./fsl-ls1043a-rdb.dtb"); -+ type = "flat_dt"; -+ arch = "arm"; -+ compression = "none"; -+ load = <0x90000000>; -+ }; -+ ramdisk@1 { -+ description = "LS1 Ramdisk"; -+ data = /incbin/("./fsl-image-core-ls1021atwr-wifi.rootfs.ext2.gz"); -+ type = "ramdisk"; -+ arch = "arm"; -+ os = "linux"; -+ compression = "none"; -+ }; -+ }; -+ -+ configurations { -+ default = "config@1"; -+ config@1 { -+ description = "Boot Linux kernel"; -+ kernel = "kernel@1"; -+ fdt = "fdt@1"; -+ ramdisk = "ramdisk@1"; -+ }; -+ }; -+}; diff --git a/target/linux/layerscape/patches-4.4/3005-armv8-aarch32-change-FS-file-name-in-ITS.patch b/target/linux/layerscape/patches-4.4/3005-armv8-aarch32-change-FS-file-name-in-ITS.patch deleted file mode 100644 index 2836f1ae8a..0000000000 --- a/target/linux/layerscape/patches-4.4/3005-armv8-aarch32-change-FS-file-name-in-ITS.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 8f9b9d829ea0e67760b2e67c9339f6c417084fdc Mon Sep 17 00:00:00 2001 -From: Pan Jiafei -Date: Thu, 28 Jan 2016 12:10:24 +0800 -Subject: [PATCH 05/70] armv8: aarch32: change FS file name in ITS - -Signed-off-by: Pan Jiafei ---- - kernel-ls1043a-rdb-aarch32.its | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/kernel-ls1043a-rdb-aarch32.its -+++ b/kernel-ls1043a-rdb-aarch32.its -@@ -33,7 +33,7 @@ - }; - ramdisk@1 { - description = "LS1 Ramdisk"; -- data = /incbin/("./fsl-image-core-ls1021atwr-wifi.rootfs.ext2.gz"); -+ data = /incbin/("./fsl-image-core-ls1043ardb-32b.ext2.gz"); - type = "ramdisk"; - arch = "arm"; - os = "linux"; diff --git a/target/linux/layerscape/patches-4.4/3007-armv8-aarch32-Run-32-bit-Linux-in-AArch32-execution-.patch b/target/linux/layerscape/patches-4.4/3007-armv8-aarch32-Run-32-bit-Linux-in-AArch32-execution-.patch deleted file mode 100644 index c2f5215647..0000000000 --- a/target/linux/layerscape/patches-4.4/3007-armv8-aarch32-Run-32-bit-Linux-in-AArch32-execution-.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 3a827762e11670ca815bd4ee305f5faf5f02acb9 Mon Sep 17 00:00:00 2001 -From: Alison Wang -Date: Tue, 17 May 2016 17:23:51 +0800 -Subject: [PATCH 07/70] armv8: aarch32: Run 32-bit Linux in AArch32 execution - state - -This patch adds AArch32 execution state support for LS1043A. Verified -32-bit Linux kernel can run on LS1043ARDB board. - -Signed-off-by: Ebony Zhu -Signed-off-by: Alison Wang ---- - arch/arm/mach-imx/Kconfig | 10 ++++++++++ - arch/arm/mach-imx/Makefile | 4 +++- - arch/arm/mach-imx/mach-ls1043a.c | 21 +++++++++++++++++++++ - 3 files changed, 34 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/mach-imx/mach-ls1043a.c - ---- a/arch/arm/mach-imx/Kconfig -+++ b/arch/arm/mach-imx/Kconfig -@@ -612,6 +612,16 @@ endchoice - - endif - -+config ARCH_LAYERSCAPE -+ bool "Freescale Layerscape SoC support" -+ select ARM_GIC -+ select HAVE_ARM_ARCH_TIMER -+ select PCI_LAYERSCAPE if PCI -+ select LS1_MSI if PCI_MSI -+ -+ help -+ This enables support for Freescale Layerscape SoC family. -+ - source "arch/arm/mach-imx/devices/Kconfig" - - endif ---- a/arch/arm/mach-imx/Makefile -+++ b/arch/arm/mach-imx/Makefile -@@ -75,7 +75,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop. - obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o - obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o - obj-$(CONFIG_HAVE_IMX_SRC) += src.o --ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),) -+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A)$(CONFIG_ARCH_LAYERSCAPE),) - AFLAGS_headsmp.o :=-Wa,-march=armv7-a - obj-$(CONFIG_SMP) += headsmp.o platsmp.o - obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -@@ -101,4 +101,6 @@ obj-$(CONFIG_SOC_VF610) += mach-vf610.o - - obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o - -+obj-$(CONFIG_ARCH_LAYERSCAPE) += mach-ls1043a.o -+ - obj-y += devices/ ---- /dev/null -+++ b/arch/arm/mach-imx/mach-ls1043a.c -@@ -0,0 +1,21 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+ -+#include "common.h" -+ -+static const char * const ls1043a_dt_compat[] __initconst = { -+ "fsl,ls1043a", -+ NULL, -+}; -+ -+DT_MACHINE_START(LS1043A, "Freescale LS1043A") -+ .dt_compat = ls1043a_dt_compat, -+MACHINE_END diff --git a/target/linux/layerscape/patches-4.4/3008-armv8-aarch32-Add-SMP-support-for-32-bit-Linux.patch b/target/linux/layerscape/patches-4.4/3008-armv8-aarch32-Add-SMP-support-for-32-bit-Linux.patch deleted file mode 100644 index 31f1d98aea..0000000000 --- a/target/linux/layerscape/patches-4.4/3008-armv8-aarch32-Add-SMP-support-for-32-bit-Linux.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 5d06e90bd0e3bdd104b7b25173e05617f02dc44d Mon Sep 17 00:00:00 2001 -From: Alison Wang -Date: Fri, 13 May 2016 15:09:47 +0800 -Subject: [PATCH 08/70] armv8: aarch32: Add SMP support for 32-bit Linux - -The patch adds SMP support for running 32-bit Linux kernel. Spin-table -method is used for SMP support. - -Signed-off-by: Alison Wang -Signed-off-by: Chenhui Zhao ---- - arch/arm/mach-imx/common.h | 1 + - arch/arm/mach-imx/mach-ls1043a.c | 1 + - arch/arm/mach-imx/platsmp.c | 49 ++++++++++++++++++++++++++++++++++++++ - 3 files changed, 51 insertions(+) - ---- a/arch/arm/mach-imx/common.h -+++ b/arch/arm/mach-imx/common.h -@@ -155,5 +155,6 @@ static inline void imx_init_l2cache(void - - extern struct smp_operations imx_smp_ops; - extern struct smp_operations ls1021a_smp_ops; -+extern const struct smp_operations layerscape_smp_ops; - - #endif ---- a/arch/arm/mach-imx/mach-ls1043a.c -+++ b/arch/arm/mach-imx/mach-ls1043a.c -@@ -17,5 +17,6 @@ static const char * const ls1043a_dt_com - }; - - DT_MACHINE_START(LS1043A, "Freescale LS1043A") -+ .smp = smp_ops(layerscape_smp_ops), - .dt_compat = ls1043a_dt_compat, - MACHINE_END ---- a/arch/arm/mach-imx/platsmp.c -+++ b/arch/arm/mach-imx/platsmp.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -26,6 +27,8 @@ - u32 g_diag_reg; - static void __iomem *scu_base; - -+static u64 cpu_release_addr[NR_CPUS]; -+ - static struct map_desc scu_io_desc __initdata = { - /* .virtual and .pfn are run-time assigned */ - .length = SZ_4K, -@@ -127,3 +130,49 @@ struct smp_operations ls1021a_smp_ops _ - .smp_prepare_cpus = ls1021a_smp_prepare_cpus, - .smp_boot_secondary = ls1021a_boot_secondary, - }; -+ -+static int layerscape_smp_boot_secondary(unsigned int cpu, -+ struct task_struct *idle) -+{ -+ u32 secondary_startup_phys; -+ __le32 __iomem *release_addr; -+ -+ secondary_startup_phys = virt_to_phys(secondary_startup); -+ -+ release_addr = ioremap_cache((u32)cpu_release_addr[cpu], -+ sizeof(u64)); -+ if (!release_addr) -+ return -ENOMEM; -+ -+ writel_relaxed(secondary_startup_phys, release_addr); -+ writel_relaxed(0, release_addr + 1); -+ __cpuc_flush_dcache_area((__force void *)release_addr, -+ sizeof(u64)); -+ -+ sev(); -+ -+ iounmap(release_addr); -+ -+ return 0; -+} -+ -+static void layerscape_smp_init_cpus(void) -+{ -+ struct device_node *dnt = NULL; -+ unsigned int cpu = 0; -+ -+ while ((dnt = of_find_node_by_type(dnt, "cpu"))) { -+ if (of_property_read_u64(dnt, "cpu-release-addr", -+ &cpu_release_addr[cpu])) { -+ pr_err("CPU %d: missing or invalid cpu-release-addr property\n", -+ cpu); -+ } -+ -+ cpu++; -+ } -+} -+ -+const struct smp_operations layerscape_smp_ops __initconst = { -+ .smp_init_cpus = layerscape_smp_init_cpus, -+ .smp_boot_secondary = layerscape_smp_boot_secondary, -+}; diff --git a/target/linux/layerscape/patches-4.4/3009-armv8-aarch32-Allow-RAM-to-be-mapped-for-LayerScape-.patch b/target/linux/layerscape/patches-4.4/3009-armv8-aarch32-Allow-RAM-to-be-mapped-for-LayerScape-.patch deleted file mode 100644 index 240204a16b..0000000000 --- a/target/linux/layerscape/patches-4.4/3009-armv8-aarch32-Allow-RAM-to-be-mapped-for-LayerScape-.patch +++ /dev/null @@ -1,31 +0,0 @@ -From ef25bf644b7de83849a2f804c84bb54cd2f1255f Mon Sep 17 00:00:00 2001 -From: Alison Wang -Date: Mon, 11 Apr 2016 17:25:40 +0800 -Subject: [PATCH 09/70] armv8: aarch32: Allow RAM to be mapped for LayerScape - SoC - -This patch is based on Kernel v4.1.8. As in v4.1.8, memremap() is not -introduced and the WARN() check is not relaxed to allow MT_MEMORY_RW -mappings of pfn_valid() pages, this patch is needed as a workaround for -spin-table address which locates in RAM to be mapped. - -For the latest kernel in upstream, this patch is not needed anymore. - -Signed-off-by: Alison Wang ---- - arch/arm/mm/ioremap.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm/mm/ioremap.c -+++ b/arch/arm/mm/ioremap.c -@@ -298,8 +298,10 @@ static void __iomem * __arm_ioremap_pfn_ - /* - * Don't allow RAM to be mapped - this causes problems with ARMv6+ - */ -+#ifndef CONFIG_ARCH_LAYERSCAPE - if (WARN_ON(pfn_valid(pfn))) - return NULL; -+#endif - - area = get_vm_area_caller(size, VM_IOREMAP, caller); - if (!area) diff --git a/target/linux/layerscape/patches-4.4/3010-arm-add-pgprot_cached-and-pgprot_cached_ns-support.patch b/target/linux/layerscape/patches-4.4/3010-arm-add-pgprot_cached-and-pgprot_cached_ns-support.patch deleted file mode 100644 index 43ab4d9240..0000000000 --- a/target/linux/layerscape/patches-4.4/3010-arm-add-pgprot_cached-and-pgprot_cached_ns-support.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 31a5b5189bdd33bb87f88320964a47c0da983af2 Mon Sep 17 00:00:00 2001 -From: Jianhua Xie -Date: Fri, 29 Jan 2016 16:40:46 +0800 -Subject: [PATCH 10/70] arm: add pgprot_cached and pgprot_cached_ns support - -Signed-off-by: Jianhua Xie ---- - arch/arm/include/asm/pgtable.h | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm/include/asm/pgtable.h -+++ b/arch/arm/include/asm/pgtable.h -@@ -116,6 +116,13 @@ extern pgprot_t pgprot_s2_device; - #define pgprot_noncached(prot) \ - __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED) - -+#define pgprot_cached(prot) \ -+ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED) -+ -+#define pgprot_cached_ns(prot) \ -+ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED | \ -+ L_PTE_MT_DEV_NONSHARED) -+ - #define pgprot_writecombine(prot) \ - __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE) - diff --git a/target/linux/layerscape/patches-4.4/3011-arm-add-new-non-shareable-ioremap.patch b/target/linux/layerscape/patches-4.4/3011-arm-add-new-non-shareable-ioremap.patch deleted file mode 100644 index f3ef2b3ffa..0000000000 --- a/target/linux/layerscape/patches-4.4/3011-arm-add-new-non-shareable-ioremap.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 707627a28924320a7a36bdb8b02c05651c0c384d Mon Sep 17 00:00:00 2001 -From: Pan Jiafei -Date: Fri, 8 Jul 2016 11:16:13 +0800 -Subject: [PATCH 11/70] arm: add new non-shareable ioremap - -commit 17d7448eef0fa57a0899e6a864d875e7a9082561 -[modify ioremap_cache_ns according to Linux v4.4.7] - -Signed-off-by: Pan Jiafei -Integrated-by: Zhao Qiang ---- - arch/arm/include/asm/io.h | 4 ++++ - arch/arm/include/asm/mach/map.h | 4 ++-- - arch/arm/mm/ioremap.c | 7 +++++++ - arch/arm/mm/mmu.c | 9 +++++++++ - 4 files changed, 22 insertions(+), 2 deletions(-) - ---- a/arch/arm/include/asm/io.h -+++ b/arch/arm/include/asm/io.h -@@ -129,6 +129,7 @@ static inline u32 __raw_readl(const vola - #define MT_DEVICE_NONSHARED 1 - #define MT_DEVICE_CACHED 2 - #define MT_DEVICE_WC 3 -+#define MT_MEMORY_RW_NS 4 - /* - * types 4 onwards can be found in asm/mach/map.h and are undefined - * for ioremap -@@ -399,6 +400,9 @@ void __iomem *ioremap_wc(resource_size_t - #define ioremap_wc ioremap_wc - #define ioremap_wt ioremap_wc - -+void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size); -+#define ioremap_cache_ns ioremap_cache_ns -+ - void iounmap(volatile void __iomem *iomem_cookie); - #define iounmap iounmap - ---- a/arch/arm/include/asm/mach/map.h -+++ b/arch/arm/include/asm/mach/map.h -@@ -21,9 +21,9 @@ struct map_desc { - unsigned int type; - }; - --/* types 0-3 are defined in asm/io.h */ -+/* types 0-4 are defined in asm/io.h */ - enum { -- MT_UNCACHED = 4, -+ MT_UNCACHED = 5, - MT_CACHECLEAN, - MT_MINICLEAN, - MT_LOW_VECTORS, ---- a/arch/arm/mm/ioremap.c -+++ b/arch/arm/mm/ioremap.c -@@ -394,6 +394,13 @@ void __iomem *ioremap_wc(resource_size_t - } - EXPORT_SYMBOL(ioremap_wc); - -+void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size) -+{ -+ return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RW_NS, -+ __builtin_return_address(0)); -+} -+EXPORT_SYMBOL(ioremap_cache_ns); -+ - /* - * Remap an arbitrary physical address space into the kernel virtual - * address space as memory. Needed when the kernel wants to execute ---- a/arch/arm/mm/mmu.c -+++ b/arch/arm/mm/mmu.c -@@ -313,6 +313,13 @@ static struct mem_type mem_types[] = { - .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, - .domain = DOMAIN_KERNEL, - }, -+ [MT_MEMORY_RW_NS] = { -+ .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | -+ L_PTE_XN, -+ .prot_l1 = PMD_TYPE_TABLE, -+ .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_XN, -+ .domain = DOMAIN_KERNEL, -+ }, - [MT_ROM] = { - .prot_sect = PMD_TYPE_SECT, - .domain = DOMAIN_KERNEL, -@@ -644,6 +651,7 @@ static void __init build_mem_type_table( - } - kern_pgprot |= PTE_EXT_AF; - vecs_pgprot |= PTE_EXT_AF; -+ mem_types[MT_MEMORY_RW_NS].prot_pte |= PTE_EXT_AF | cp->pte; - - /* - * Set PXN for user mappings -@@ -672,6 +680,7 @@ static void __init build_mem_type_table( - mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; - mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; - mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; -+ mem_types[MT_MEMORY_RW_NS].prot_sect |= ecc_mask | cp->pmd; - mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; - mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; - mem_types[MT_ROM].prot_sect |= cp->pmd; diff --git a/target/linux/layerscape/patches-4.4/3012-dts-ls1043a-add-fman-bman-qman-ethernet-nodes.patch b/target/linux/layerscape/patches-4.4/3012-dts-ls1043a-add-fman-bman-qman-ethernet-nodes.patch deleted file mode 100644 index cbb67c47dc..0000000000 --- a/target/linux/layerscape/patches-4.4/3012-dts-ls1043a-add-fman-bman-qman-ethernet-nodes.patch +++ /dev/null @@ -1,747 +0,0 @@ -From 10b0a19d62d932a6eb01ceb8749190aaf0ff063e Mon Sep 17 00:00:00 2001 -From: Shaohui Xie -Date: Mon, 11 Jul 2016 10:47:20 +0800 -Subject: [PATCH 12/70] dts: ls1043a: add fman/bman/qman/ethernet nodes - -commit ecb0901ba0a6558a05054d21ad9e70999a6f7ca1 -[context adjustment] - -Signed-off-by: Shaohui Xie -Signed-off-by: Zhao Qiang ---- - arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 461 ++++++++++++++++++++ - .../boot/dts/freescale/qoriq-bman1-portals.dtsi | 104 +++++ - .../boot/dts/freescale/qoriq-qman1-portals.dtsi | 136 ++++++ - 3 files changed, 701 insertions(+) - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -@@ -50,6 +50,16 @@ - #address-cells = <2>; - #size-cells = <2>; - -+ aliases { -+ ethernet0 = &fm1mac1; -+ ethernet1 = &fm1mac2; -+ ethernet2 = &fm1mac3; -+ ethernet3 = &fm1mac4; -+ ethernet4 = &fm1mac5; -+ ethernet5 = &fm1mac6; -+ ethernet6 = &fm1mac9; -+ }; -+ - cpus { - #address-cells = <1>; - #size-cells = <0>; -@@ -174,6 +184,323 @@ - bus-width = <4>; - }; - -+ qman: qman@1880000 { -+ compatible = "fsl,qman"; -+ reg = <0x00 0x1880000 0x0 0x10000>; -+ interrupts = <0 45 0x4>; -+ }; -+ -+ bman: bman@1890000 { -+ compatible = "fsl,bman"; -+ reg = <0x00 0x1890000 0x0 0x10000>; -+ interrupts = <0 45 0x4>; -+ }; -+ -+ fman0: fman@1a00000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ cell-index = <0>; -+ compatible = "fsl,fman", "simple-bus"; -+ ranges = <0x0 0x00 0x1a00000 0x100000>; -+ reg = <0x00 0x1a00000 0x0 0x100000>; -+ clock-frequency = <0>; -+ interrupts = <0 44 0x4>, -+ <0 45 0x4>; -+ -+ cc { -+ compatible = "fsl,fman-cc"; -+ }; -+ -+ muram@0 { -+ compatible = "fsl,fman-muram"; -+ reg = <0x0 0x60000>; -+ }; -+ -+ bmi@80000 { -+ compatible = "fsl,fman-bmi"; -+ reg = <0x80000 0x400>; -+ }; -+ -+ qmi@80400 { -+ compatible = "fsl,fman-qmi"; -+ reg = <0x80400 0x400>; -+ }; -+ -+ fman0_oh1: port@82000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x82000 0x1000>; -+ }; -+ -+ fman0_oh2: port@83000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x83000 0x1000>; -+ }; -+ -+ fman0_oh3: port@84000 { -+ cell-index = <2>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x84000 0x1000>; -+ }; -+ -+ fman0_oh4: port@85000 { -+ cell-index = <3>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x85000 0x1000>; -+ }; -+ -+ fman0_oh5: port@86000 { -+ cell-index = <4>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x86000 0x1000>; -+ }; -+ -+ fman0_oh6: port@87000 { -+ cell-index = <5>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x87000 0x1000>; -+ }; -+ -+ policer@c0000 { -+ compatible = "fsl,fman-policer"; -+ reg = <0xc0000 0x1000>; -+ }; -+ -+ keygen@c1000 { -+ compatible = "fsl,fman-keygen"; -+ reg = <0xc1000 0x1000>; -+ }; -+ -+ dma@c2000 { -+ compatible = "fsl,fman-dma"; -+ reg = <0xc2000 0x1000>; -+ }; -+ -+ fpm@c3000 { -+ compatible = "fsl,fman-fpm"; -+ reg = <0xc3000 0x1000>; -+ }; -+ -+ parser@c7000 { -+ compatible = "fsl,fman-parser"; -+ reg = <0xc7000 0x1000>; -+ }; -+ -+ vsps@dc000 { -+ compatible = "fsl,fman-vsps"; -+ reg = <0xdc000 0x1000>; -+ }; -+ -+ mdio0: mdio@fc000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xfc000 0x1000>; -+ }; -+ -+ xmdio0: mdio@fd000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xfd000 0x1000>; -+ }; -+ -+ fman0_rx0: port@88000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-1g-rx"; -+ reg = <0x88000 0x1000>; -+ }; -+ -+ fman0_tx0: port@a8000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-1g-tx"; -+ reg = <0xa8000 0x1000>; -+ }; -+ -+ fm1mac1: ethernet@e0000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe0000 0x1000>; -+ fsl,port-handles = <&fman0_rx0 &fman0_tx0>; -+ ptimer-handle = <&ptp_timer0>; -+ }; -+ -+ mdio@e1000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xe1000 0x1000>; -+ }; -+ -+ fman0_rx1: port@89000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-1g-rx"; -+ reg = <0x89000 0x1000>; -+ }; -+ -+ fman0_tx1: port@a9000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-1g-tx"; -+ reg = <0xa9000 0x1000>; -+ }; -+ -+ fm1mac2: ethernet@e2000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe2000 0x1000>; -+ fsl,port-handles = <&fman0_rx1 &fman0_tx1>; -+ ptimer-handle = <&ptp_timer0>; -+ }; -+ -+ mdio@e3000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xe3000 0x1000>; -+ }; -+ -+ fman0_rx2: port@8a000 { -+ cell-index = <2>; -+ compatible = "fsl,fman-port-1g-rx"; -+ reg = <0x8a000 0x1000>; -+ }; -+ -+ fman0_tx2: port@aa000 { -+ cell-index = <2>; -+ compatible = "fsl,fman-port-1g-tx"; -+ reg = <0xaa000 0x1000>; -+ }; -+ -+ fm1mac3: ethernet@e4000 { -+ cell-index = <2>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe4000 0x1000>; -+ fsl,port-handles = <&fman0_rx2 &fman0_tx2>; -+ ptimer-handle = <&ptp_timer0>; -+ }; -+ -+ mdio@e5000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xe5000 0x1000>; -+ }; -+ -+ fman0_rx3: port@8b000 { -+ cell-index = <3>; -+ compatible = "fsl,fman-port-1g-rx"; -+ reg = <0x8b000 0x1000>; -+ }; -+ -+ fman0_tx3: port@ab000 { -+ cell-index = <3>; -+ compatible = "fsl,fman-port-1g-tx"; -+ reg = <0xab000 0x1000>; -+ }; -+ -+ fm1mac4: ethernet@e6000 { -+ cell-index = <3>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe6000 0x1000>; -+ fsl,port-handles = <&fman0_rx3 &fman0_tx3>; -+ ptimer-handle = <&ptp_timer0>; -+ }; -+ -+ mdio@e7000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xe7000 0x1000>; -+ }; -+ -+ fman0_rx4: port@8c000 { -+ cell-index = <4>; -+ compatible = "fsl,fman-port-1g-rx"; -+ reg = <0x8c000 0x1000>; -+ }; -+ -+ fman0_tx4: port@ac000 { -+ cell-index = <4>; -+ compatible = "fsl,fman-port-1g-tx"; -+ reg = <0xac000 0x1000>; -+ }; -+ -+ fm1mac5: ethernet@e8000 { -+ cell-index = <4>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe8000 0x1000>; -+ fsl,port-handles = <&fman0_rx4 &fman0_tx4>; -+ ptimer-handle = <&ptp_timer0>; -+ }; -+ -+ mdio@e9000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xe9000 0x1000>; -+ }; -+ -+ fman0_rx5: port@8d000 { -+ cell-index = <5>; -+ compatible = "fsl,fman-port-1g-rx"; -+ reg = <0x8d000 0x1000>; -+ }; -+ -+ fman0_tx5: port@ad000 { -+ cell-index = <5>; -+ compatible = "fsl,fman-port-1g-tx"; -+ reg = <0xad000 0x1000>; -+ }; -+ -+ fm1mac6: ethernet@ea000 { -+ cell-index = <5>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xea000 0x1000>; -+ fsl,port-handles = <&fman0_rx5 &fman0_tx5>; -+ ptimer-handle = <&ptp_timer0>; -+ }; -+ -+ mdio@eb000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xeb000 0x1000>; -+ }; -+ -+ fman0_10g_rx0: port@90000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-10g-rx"; -+ reg = <0x90000 0x1000>; -+ }; -+ -+ fman0_10g_tx0: port@b0000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-10g-tx"; -+ reg = <0xb0000 0x1000>; -+ fsl,qman-channel-id = <0x800>; -+ }; -+ -+ fm1mac9: ethernet@f0000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xf0000 0x1000>; -+ fsl,port-handles = <&fman0_10g_rx0 &fman0_10g_tx0>; -+ }; -+ -+ mdio@f1000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xf1000 0x1000>; -+ }; -+ -+ ptp_timer0: rtc@fe000 { -+ compatible = "fsl,fman-rtc"; -+ reg = <0xfe000 0x1000>; -+ }; -+ }; -+ - dspi0: dspi@2100000 { - compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; -@@ -522,4 +849,138 @@ - }; - }; - -+ fsl,dpaa { -+ compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa"; -+ ethernet@0 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac1>; -+ }; -+ ethernet@1 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac2>; -+ }; -+ ethernet@2 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac3>; -+ }; -+ ethernet@3 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac4>; -+ }; -+ ethernet@4 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac5>; -+ }; -+ ethernet@5 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac6>; -+ }; -+ ethernet@8 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac9>; -+ }; -+ }; -+ -+ qportals: qman-portals@500000000 { -+ ranges = <0x0 0x5 0x00000000 0x8000000>; -+ }; -+ bportals: bman-portals@508000000 { -+ ranges = <0x0 0x5 0x08000000 0x8000000>; -+ }; -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ bman_fbpr: bman-fbpr { -+ size = <0 0x1000000>; -+ alignment = <0 0x1000000>; -+ }; -+ qman_fqd: qman-fqd { -+ size = <0 0x400000>; -+ alignment = <0 0x400000>; -+ }; -+ qman_pfdr: qman-pfdr { -+ size = <0 0x2000000>; -+ alignment = <0 0x2000000>; -+ }; -+ }; -+}; -+ -+&fman0 { -+ /* offline - 1 */ -+ port@82000 { -+ fsl,qman-channel-id = <0x809>; -+ }; -+ -+ /* tx - 10g - 2 */ -+ port@a8000 { -+ fsl,qman-channel-id = <0x802>; -+ }; -+ /* tx - 10g - 3 */ -+ port@a9000 { -+ fsl,qman-channel-id = <0x803>; -+ }; -+ /* tx - 1g - 2 */ -+ port@aa000 { -+ fsl,qman-channel-id = <0x804>; -+ }; -+ /* tx - 1g - 3 */ -+ port@ab000 { -+ fsl,qman-channel-id = <0x805>; -+ }; -+ /* tx - 1g - 4 */ -+ port@ac000 { -+ fsl,qman-channel-id = <0x806>; -+ }; -+ /* tx - 1g - 5 */ -+ port@ad000 { -+ fsl,qman-channel-id = <0x807>; -+ }; -+ /* tx - 10g - 0 */ -+ port@b0000 { -+ fsl,qman-channel-id = <0x800>; -+ }; -+ /* tx - 10g - 1 */ -+ port@b1000 { -+ fsl,qman-channel-id = <0x801>; -+ }; -+ /* offline - 2 */ -+ port@83000 { -+ fsl,qman-channel-id = <0x80a>; -+ }; -+ /* offline - 3 */ -+ port@84000 { -+ fsl,qman-channel-id = <0x80b>; -+ }; -+ /* offline - 4 */ -+ port@85000 { -+ fsl,qman-channel-id = <0x80c>; -+ }; -+ /* offline - 5 */ -+ port@86000 { -+ fsl,qman-channel-id = <0x80d>; -+ }; -+ /* offline - 6 */ -+ port@87000 { -+ fsl,qman-channel-id = <0x80e>; -+ }; -+}; -+ -+&bman_fbpr { -+ compatible = "fsl,bman-fbpr"; -+ alloc-ranges = <0 0 0x10000 0>; - }; -+ -+&qman_fqd { -+ compatible = "fsl,qman-fqd"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+&qman_pfdr { -+ compatible = "fsl,qman-pfdr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+/include/ "qoriq-qman1-portals.dtsi" -+/include/ "qoriq-bman1-portals.dtsi" ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi -@@ -0,0 +1,104 @@ -+/* -+ * QorIQ BMan Portal device tree stub for 10 portals -+ * -+ * Copyright 2011-2016 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+&bportals { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "simple-bus"; -+ bportal0: bman-portal@0 { -+ cell-index = <0>; -+ compatible = "fsl,bman-portal"; -+ reg = <0x0 0x4000 0x4000000 0x4000>; -+ interrupts = <0 173 0x4>; -+ }; -+ bportal1: bman-portal@10000 { -+ cell-index = <1>; -+ compatible = "fsl,bman-portal"; -+ reg = <0x10000 0x4000 0x4010000 0x4000>; -+ interrupts = <0 175 0x4>; -+ }; -+ bportal2: bman-portal@20000 { -+ cell-index = <2>; -+ compatible = "fsl,bman-portal"; -+ reg = <0x20000 0x4000 0x4020000 0x4000>; -+ interrupts = <0 177 0x4>; -+ }; -+ bportal3: bman-portal@30000 { -+ cell-index = <3>; -+ compatible = "fsl,bman-portal"; -+ reg = <0x30000 0x4000 0x4030000 0x4000>; -+ interrupts = <0 179 0x4>; -+ }; -+ bportal4: bman-portal@40000 { -+ cell-index = <4>; -+ compatible = "fsl,bman-portal"; -+ reg = <0x40000 0x4000 0x4040000 0x4000>; -+ interrupts = <0 181 0x4>; -+ }; -+ bportal5: bman-portal@50000 { -+ cell-index = <5>; -+ compatible = "fsl,bman-portal"; -+ reg = <0x50000 0x4000 0x4050000 0x4000>; -+ interrupts = <0 183 0x4>; -+ }; -+ bportal6: bman-portal@60000 { -+ cell-index = <6>; -+ compatible = "fsl,bman-portal"; -+ reg = <0x60000 0x4000 0x4060000 0x4000>; -+ interrupts = <0 185 0x4>; -+ }; -+ bportal7: bman-portal@70000 { -+ cell-index = <7>; -+ compatible = "fsl,bman-portal"; -+ reg = <0x70000 0x4000 0x4070000 0x4000>; -+ interrupts = <0 187 0x4>; -+ }; -+ bportal8: bman-portal@80000 { -+ cell-index = <8>; -+ compatible = "fsl,bman-portal"; -+ reg = <0x80000 0x4000 0x4080000 0x4000>; -+ interrupts = <0 189 0x4>; -+ }; -+/* bportal9: bman-portal@90000 { -+ cell-index = <9>; -+ compatible = "fsl,bman-portal"; -+ reg = <0x90000 0x4000 0x4090000 0x4000>; -+ interrupts = <0 191 0x4>; -+ }; */ -+ bman-bpids@0 { -+ compatible = "fsl,bpid-range"; -+ fsl,bpid-range = <32 32>; -+ }; -+ -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi -@@ -0,0 +1,136 @@ -+/* -+ * QorIQ QMan Portal device tree stub for 10 portals & 15 pool channels -+ * -+ * Copyright 2011-2016 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+&qportals { -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "simple-bus"; -+ qportal0: qman-portal@0 { -+ cell-index = <0>; -+ compatible = "fsl,qman-portal"; -+ reg = <0x0 0x4000 0x4000000 0x4000>; -+ interrupts = <0 172 0x4>; -+ fsl,qman-channel-id = <0x0>; -+ }; -+ -+ qportal1: qman-portal@10000 { -+ cell-index = <1>; -+ compatible = "fsl,qman-portal"; -+ reg = <0x10000 0x4000 0x4010000 0x4000>; -+ interrupts = <0 174 0x4>; -+ fsl,qman-channel-id = <1>; -+ }; -+ -+ qportal2: qman-portal@20000 { -+ cell-index = <2>; -+ compatible = "fsl,qman-portal"; -+ reg = <0x20000 0x4000 0x4020000 0x4000>; -+ interrupts = <0 176 0x4>; -+ fsl,qman-channel-id = <2>; -+ }; -+ -+ qportal3: qman-portal@30000 { -+ cell-index = <3>; -+ compatible = "fsl,qman-portal"; -+ reg = <0x30000 0x4000 0x4030000 0x4000>; -+ interrupts = <0 178 0x4>; -+ fsl,qman-channel-id = <3>; -+ }; -+ -+ qportal4: qman-portal@40000 { -+ cell-index = <4>; -+ compatible = "fsl,qman-portal"; -+ reg = <0x40000 0x4000 0x4040000 0x4000>; -+ interrupts = <0 180 0x4>; -+ fsl,qman-channel-id = <4>; -+ }; -+ -+ qportal5: qman-portal@50000 { -+ cell-index = <5>; -+ compatible = "fsl,qman-portal"; -+ reg = <0x50000 0x4000 0x4050000 0x4000>; -+ interrupts = <0 182 0x4>; -+ fsl,qman-channel-id = <5>; -+ }; -+ -+ qportal6: qman-portal@60000 { -+ cell-index = <6>; -+ compatible = "fsl,qman-portal"; -+ reg = <0x60000 0x4000 0x4060000 0x4000>; -+ interrupts = <0 184 0x4>; -+ fsl,qman-channel-id = <6>; -+ }; -+ -+ qportal7: qman-portal@70000 { -+ cell-index = <7>; -+ compatible = "fsl,qman-portal"; -+ reg = <0x70000 0x4000 0x4070000 0x4000>; -+ interrupts = <0 186 0x4>; -+ fsl,qman-channel-id = <7>; -+ }; -+ -+ qportal8: qman-portal@80000 { -+ cell-index = <8>; -+ compatible = "fsl,qman-portal"; -+ reg = <0x80000 0x4000 0x4080000 0x4000>; -+ interrupts = <0 188 0x4>; -+ fsl,qman-channel-id = <8>; -+ }; -+ -+/* qportal9: qman-portal@90000 { -+ cell-index = <9>; -+ compatible = "fsl,qman-portal"; -+ reg = <0x90000 0x4000 0x4090000 0x4000>; -+ interrupts = <0 190 0x4>; -+ fsl,qman-channel-id = <9>; -+ }; */ -+ -+ qman-fqids@0 { -+ compatible = "fsl,fqid-range"; -+ fsl,fqid-range = <256 256>; -+ }; -+ qman-fqids@1 { -+ compatible = "fsl,fqid-range"; -+ fsl,fqid-range = <32768 32768>; -+ }; -+ qman-pools@0 { -+ compatible = "fsl,pool-channel-range"; -+ fsl,pool-channel-range = <0x401 0xf>; -+ }; -+ qman-cgrids@0 { -+ compatible = "fsl,cgrid-range"; -+ fsl,cgrid-range = <0 256>; -+ }; -+ -+}; -\ No newline at end of file diff --git a/target/linux/layerscape/patches-4.4/3013-dts-ls1043ardb-add-mdio-phy-nodes.patch b/target/linux/layerscape/patches-4.4/3013-dts-ls1043ardb-add-mdio-phy-nodes.patch deleted file mode 100644 index 8347b4f843..0000000000 --- a/target/linux/layerscape/patches-4.4/3013-dts-ls1043ardb-add-mdio-phy-nodes.patch +++ /dev/null @@ -1,81 +0,0 @@ -From e2b301610e6201df40deb62942b18c772365eb1c Mon Sep 17 00:00:00 2001 -From: Shaohui Xie -Date: Thu, 21 Jan 2016 11:29:22 +0800 -Subject: [PATCH 13/70] dts: ls1043ardb: add mdio & phy nodes - -Signed-off-by: Shaohui Xie ---- - arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 65 +++++++++++++++++++++ - 1 file changed, 65 insertions(+) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts -@@ -115,3 +115,68 @@ - &duart1 { - status = "okay"; - }; -+ -+&fman0 { -+ ethernet@e0000 { -+ phy-handle = <&qsgmii_phy1>; -+ phy-connection-type = "qsgmii"; -+ }; -+ -+ ethernet@e2000 { -+ phy-handle = <&qsgmii_phy2>; -+ phy-connection-type = "qsgmii"; -+ }; -+ -+ ethernet@e4000 { -+ phy-handle = <&rgmii_phy1>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e6000 { -+ phy-handle = <&rgmii_phy2>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e8000 { -+ phy-handle = <&qsgmii_phy3>; -+ phy-connection-type = "qsgmii"; -+ }; -+ -+ ethernet@ea000 { -+ phy-handle = <&qsgmii_phy4>; -+ phy-connection-type = "qsgmii"; -+ }; -+ -+ ethernet@f0000 { /* 10GEC1 */ -+ phy-handle = <&aqr105_phy>; -+ phy-connection-type = "xgmii"; -+ }; -+ -+ mdio@fc000 { -+ rgmii_phy1: ethernet-phy@1 { -+ reg = <0x1>; -+ }; -+ rgmii_phy2: ethernet-phy@2 { -+ reg = <0x2>; -+ }; -+ qsgmii_phy1: ethernet-phy@3 { -+ reg = <0x4>; -+ }; -+ qsgmii_phy2: ethernet-phy@4 { -+ reg = <0x5>; -+ }; -+ qsgmii_phy3: ethernet-phy@5 { -+ reg = <0x6>; -+ }; -+ qsgmii_phy4: ethernet-phy@6 { -+ reg = <0x7>; -+ }; -+ }; -+ -+ mdio@fd000 { -+ aqr105_phy: ethernet-phy@c { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reg = <0x1>; -+ }; -+ }; -+}; diff --git a/target/linux/layerscape/patches-4.4/3022-dt-move-guts-devicetree-doc-out-of-powerpc-directory.patch b/target/linux/layerscape/patches-4.4/3022-dt-move-guts-devicetree-doc-out-of-powerpc-directory.patch deleted file mode 100644 index a3dded3736..0000000000 --- a/target/linux/layerscape/patches-4.4/3022-dt-move-guts-devicetree-doc-out-of-powerpc-directory.patch +++ /dev/null @@ -1,108 +0,0 @@ -From 0e9d79db770196e94869650d7c4d13ea23937138 Mon Sep 17 00:00:00 2001 -From: Yangbo Lu -Date: Mon, 25 Jan 2016 14:27:27 +0800 -Subject: [PATCH 22/70] dt: move guts devicetree doc out of powerpc directory - -Move guts devicetree doc to Documentation/devicetree/bindings/soc/fsl/ -since it's used by not only PowerPC but also ARM. And add a specification -for 'little-endian' property. - -Signed-off-by: Yangbo Lu ---- - .../devicetree/bindings/powerpc/fsl/guts.txt | 41 ------------------ - Documentation/devicetree/bindings/soc/fsl/guts.txt | 44 ++++++++++++++++++++ - 2 files changed, 44 insertions(+), 41 deletions(-) - delete mode 100644 Documentation/devicetree/bindings/powerpc/fsl/guts.txt - create mode 100644 Documentation/devicetree/bindings/soc/fsl/guts.txt - ---- a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt -+++ /dev/null -@@ -1,41 +0,0 @@ --* Global Utilities Block -- --The global utilities block controls power management, I/O device --enabling, power-on-reset configuration monitoring, general-purpose --I/O signal configuration, alternate function selection for multiplexed --signals, and clock control. -- --Required properties: -- -- - compatible : Should define the compatible device type for -- global-utilities. -- Possible compatibles: -- "fsl,qoriq-device-config-1.0" -- "fsl,qoriq-device-config-2.0" -- "fsl,-device-config" -- "fsl,-guts" -- - reg : Offset and length of the register set for the device. -- --Recommended properties: -- -- - fsl,has-rstcr : Indicates that the global utilities register set -- contains a functioning "reset control register" (i.e. the board -- is wired to reset upon setting the HRESET_REQ bit in this register). -- -- - fsl,liodn-bits : Indicates the number of defined bits in the LIODN -- registers, for those SOCs that have a PAMU device. -- --Examples: -- global-utilities@e0000 { /* global utilities block */ -- compatible = "fsl,mpc8548-guts"; -- reg = ; -- fsl,has-rstcr; -- }; -- -- guts: global-utilities@e0000 { -- compatible = "fsl,qoriq-device-config-1.0"; -- reg = <0xe0000 0xe00>; -- fsl,has-rstcr; -- #sleep-cells = <1>; -- fsl,liodn-bits = <12>; -- }; ---- /dev/null -+++ b/Documentation/devicetree/bindings/soc/fsl/guts.txt -@@ -0,0 +1,44 @@ -+* Global Utilities Block -+ -+The global utilities block controls power management, I/O device -+enabling, power-on-reset configuration monitoring, general-purpose -+I/O signal configuration, alternate function selection for multiplexed -+signals, and clock control. -+ -+Required properties: -+ -+ - compatible : Should define the compatible device type for -+ global-utilities. -+ Possible compatibles: -+ "fsl,qoriq-device-config-1.0" -+ "fsl,qoriq-device-config-2.0" -+ "fsl,-device-config" -+ "fsl,-guts" -+ - reg : Offset and length of the register set for the device. -+ -+Recommended properties: -+ -+ - fsl,has-rstcr : Indicates that the global utilities register set -+ contains a functioning "reset control register" (i.e. the board -+ is wired to reset upon setting the HRESET_REQ bit in this register). -+ -+ - fsl,liodn-bits : Indicates the number of defined bits in the LIODN -+ registers, for those SOCs that have a PAMU device. -+ -+ - little-endian : Indicates that the global utilities block is little -+ endian. The default is big endian. -+ -+Examples: -+ global-utilities@e0000 { /* global utilities block */ -+ compatible = "fsl,mpc8548-guts"; -+ reg = ; -+ fsl,has-rstcr; -+ }; -+ -+ guts: global-utilities@e0000 { -+ compatible = "fsl,qoriq-device-config-1.0"; -+ reg = <0xe0000 0xe00>; -+ fsl,has-rstcr; -+ #sleep-cells = <1>; -+ fsl,liodn-bits = <12>; -+ }; diff --git a/target/linux/layerscape/patches-4.4/3023-powerpc-fsl-move-mpc85xx.h-to-include-linux-fsl.patch b/target/linux/layerscape/patches-4.4/3023-powerpc-fsl-move-mpc85xx.h-to-include-linux-fsl.patch deleted file mode 100644 index 168209f2d0..0000000000 --- a/target/linux/layerscape/patches-4.4/3023-powerpc-fsl-move-mpc85xx.h-to-include-linux-fsl.patch +++ /dev/null @@ -1,283 +0,0 @@ -From 2d8816af7c19882f62c4a25edb9fcc9040312f96 Mon Sep 17 00:00:00 2001 -From: Yangbo Lu -Date: Tue, 12 Apr 2016 14:21:19 +0800 -Subject: [PATCH 23/70] powerpc/fsl: move mpc85xx.h to include/linux/fsl - -commit 2a76fbe35c14717b4f4a145e0ab83517b1f4ab4a -[context adjustment] -[doesn't apply arch/powerpc/kernel/cpu_setup_fsl_booke.S] -[doesn't apply arch/powerpc/sysdev/mpic_timer.c] - -Move mpc85xx.h to include/linux/fsl and rename it to svr.h as -a common header file. It has been used for mpc85xx and it will -be used for ARM-based SoC as well. - -Signed-off-by: Yangbo Lu -Integrated-by: Zhao Qiang ---- - arch/powerpc/include/asm/mpc85xx.h | 95 ------------------------------ - drivers/clk/clk-qoriq.c | 2 +- - drivers/i2c/busses/i2c-mpc.c | 2 +- - drivers/iommu/fsl_pamu.c | 2 +- - drivers/net/ethernet/freescale/gianfar.c | 2 +- - include/linux/fsl/svr.h | 95 ++++++++++++++++++++++++++++++ - 6 files changed, 99 insertions(+), 99 deletions(-) - delete mode 100644 arch/powerpc/include/asm/mpc85xx.h - create mode 100644 include/linux/fsl/svr.h - ---- a/arch/powerpc/include/asm/mpc85xx.h -+++ /dev/null -@@ -1,95 +0,0 @@ --/* -- * MPC85xx cpu type detection -- * -- * Copyright 2011-2012 Freescale Semiconductor, Inc. -- * -- * This is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License as published by -- * the Free Software Foundation; either version 2 of the License, or -- * (at your option) any later version. -- */ -- --#ifndef __ASM_PPC_MPC85XX_H --#define __ASM_PPC_MPC85XX_H -- --#define SVR_REV(svr) ((svr) & 0xFF) /* SOC design resision */ --#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ --#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ -- --/* Some parts define SVR[0:23] as the SOC version */ --#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC Version fields */ -- --#define SVR_8533 0x803400 --#define SVR_8535 0x803701 --#define SVR_8536 0x803700 --#define SVR_8540 0x803000 --#define SVR_8541 0x807200 --#define SVR_8543 0x803200 --#define SVR_8544 0x803401 --#define SVR_8545 0x803102 --#define SVR_8547 0x803101 --#define SVR_8548 0x803100 --#define SVR_8555 0x807100 --#define SVR_8560 0x807000 --#define SVR_8567 0x807501 --#define SVR_8568 0x807500 --#define SVR_8569 0x808000 --#define SVR_8572 0x80E000 --#define SVR_P1010 0x80F100 --#define SVR_P1011 0x80E500 --#define SVR_P1012 0x80E501 --#define SVR_P1013 0x80E700 --#define SVR_P1014 0x80F101 --#define SVR_P1017 0x80F700 --#define SVR_P1020 0x80E400 --#define SVR_P1021 0x80E401 --#define SVR_P1022 0x80E600 --#define SVR_P1023 0x80F600 --#define SVR_P1024 0x80E402 --#define SVR_P1025 0x80E403 --#define SVR_P2010 0x80E300 --#define SVR_P2020 0x80E200 --#define SVR_P2040 0x821000 --#define SVR_P2041 0x821001 --#define SVR_P3041 0x821103 --#define SVR_P4040 0x820100 --#define SVR_P4080 0x820000 --#define SVR_P5010 0x822100 --#define SVR_P5020 0x822000 --#define SVR_P5021 0X820500 --#define SVR_P5040 0x820400 --#define SVR_T4240 0x824000 --#define SVR_T4120 0x824001 --#define SVR_T4160 0x824100 --#define SVR_T4080 0x824102 --#define SVR_C291 0x850000 --#define SVR_C292 0x850020 --#define SVR_C293 0x850030 --#define SVR_B4860 0X868000 --#define SVR_G4860 0x868001 --#define SVR_G4060 0x868003 --#define SVR_B4440 0x868100 --#define SVR_G4440 0x868101 --#define SVR_B4420 0x868102 --#define SVR_B4220 0x868103 --#define SVR_T1040 0x852000 --#define SVR_T1041 0x852001 --#define SVR_T1042 0x852002 --#define SVR_T1020 0x852100 --#define SVR_T1021 0x852101 --#define SVR_T1022 0x852102 --#define SVR_T2080 0x853000 --#define SVR_T2081 0x853100 -- --#define SVR_8610 0x80A000 --#define SVR_8641 0x809000 --#define SVR_8641D 0x809001 -- --#define SVR_9130 0x860001 --#define SVR_9131 0x860000 --#define SVR_9132 0x861000 --#define SVR_9232 0x861400 -- --#define SVR_Unknown 0xFFFFFF -- --#endif ---- a/drivers/clk/clk-qoriq.c -+++ b/drivers/clk/clk-qoriq.c -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -1155,7 +1156,6 @@ bad_args: - } - - #ifdef CONFIG_PPC --#include - - static const u32 a4510_svrs[] __initconst = { - (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */ ---- a/drivers/i2c/busses/i2c-mpc.c -+++ b/drivers/i2c/busses/i2c-mpc.c -@@ -27,9 +27,9 @@ - #include - #include - #include -+#include - - #include --#include - #include - - #define DRV_NAME "mpc-i2c" ---- a/drivers/iommu/fsl_pamu.c -+++ b/drivers/iommu/fsl_pamu.c -@@ -21,10 +21,10 @@ - #include "fsl_pamu.h" - - #include -+#include - #include - #include - --#include - - /* define indexes for each operation mapping scenario */ - #define OMI_QMAN 0x00 ---- a/drivers/net/ethernet/freescale/gianfar.c -+++ b/drivers/net/ethernet/freescale/gianfar.c -@@ -86,11 +86,11 @@ - #include - #include - #include -+#include - - #include - #ifdef CONFIG_PPC - #include --#include - #endif - #include - #include ---- /dev/null -+++ b/include/linux/fsl/svr.h -@@ -0,0 +1,95 @@ -+/* -+ * MPC85xx cpu type detection -+ * -+ * Copyright 2011-2012 Freescale Semiconductor, Inc. -+ * -+ * This is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#ifndef FSL_SVR_H -+#define FSL_SVR_H -+ -+#define SVR_REV(svr) ((svr) & 0xFF) /* SOC design resision */ -+#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ -+#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ -+ -+/* Some parts define SVR[0:23] as the SOC version */ -+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC Version fields */ -+ -+#define SVR_8533 0x803400 -+#define SVR_8535 0x803701 -+#define SVR_8536 0x803700 -+#define SVR_8540 0x803000 -+#define SVR_8541 0x807200 -+#define SVR_8543 0x803200 -+#define SVR_8544 0x803401 -+#define SVR_8545 0x803102 -+#define SVR_8547 0x803101 -+#define SVR_8548 0x803100 -+#define SVR_8555 0x807100 -+#define SVR_8560 0x807000 -+#define SVR_8567 0x807501 -+#define SVR_8568 0x807500 -+#define SVR_8569 0x808000 -+#define SVR_8572 0x80E000 -+#define SVR_P1010 0x80F100 -+#define SVR_P1011 0x80E500 -+#define SVR_P1012 0x80E501 -+#define SVR_P1013 0x80E700 -+#define SVR_P1014 0x80F101 -+#define SVR_P1017 0x80F700 -+#define SVR_P1020 0x80E400 -+#define SVR_P1021 0x80E401 -+#define SVR_P1022 0x80E600 -+#define SVR_P1023 0x80F600 -+#define SVR_P1024 0x80E402 -+#define SVR_P1025 0x80E403 -+#define SVR_P2010 0x80E300 -+#define SVR_P2020 0x80E200 -+#define SVR_P2040 0x821000 -+#define SVR_P2041 0x821001 -+#define SVR_P3041 0x821103 -+#define SVR_P4040 0x820100 -+#define SVR_P4080 0x820000 -+#define SVR_P5010 0x822100 -+#define SVR_P5020 0x822000 -+#define SVR_P5021 0X820500 -+#define SVR_P5040 0x820400 -+#define SVR_T4240 0x824000 -+#define SVR_T4120 0x824001 -+#define SVR_T4160 0x824100 -+#define SVR_T4080 0x824102 -+#define SVR_C291 0x850000 -+#define SVR_C292 0x850020 -+#define SVR_C293 0x850030 -+#define SVR_B4860 0X868000 -+#define SVR_G4860 0x868001 -+#define SVR_G4060 0x868003 -+#define SVR_B4440 0x868100 -+#define SVR_G4440 0x868101 -+#define SVR_B4420 0x868102 -+#define SVR_B4220 0x868103 -+#define SVR_T1040 0x852000 -+#define SVR_T1041 0x852001 -+#define SVR_T1042 0x852002 -+#define SVR_T1020 0x852100 -+#define SVR_T1021 0x852101 -+#define SVR_T1022 0x852102 -+#define SVR_T2080 0x853000 -+#define SVR_T2081 0x853100 -+ -+#define SVR_8610 0x80A000 -+#define SVR_8641 0x809000 -+#define SVR_8641D 0x809001 -+ -+#define SVR_9130 0x860001 -+#define SVR_9131 0x860000 -+#define SVR_9132 0x861000 -+#define SVR_9232 0x861400 -+ -+#define SVR_Unknown 0xFFFFFF -+ -+#endif diff --git a/target/linux/layerscape/patches-4.4/3025-arm64-dts-align-to-the-new-clocking-model.patch b/target/linux/layerscape/patches-4.4/3025-arm64-dts-align-to-the-new-clocking-model.patch deleted file mode 100644 index 51d1b64854..0000000000 --- a/target/linux/layerscape/patches-4.4/3025-arm64-dts-align-to-the-new-clocking-model.patch +++ /dev/null @@ -1,25 +0,0 @@ -From caddf479c2deacf3d681a84db56ff164d8a5c9f7 Mon Sep 17 00:00:00 2001 -From: Madalin Bucur -Date: Wed, 23 Mar 2016 21:25:30 +0200 -Subject: [PATCH 25/70] arm64/dts: align to the new clocking model - -Signed-off-by: Madalin Bucur ---- - arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -@@ -203,9 +203,9 @@ - compatible = "fsl,fman", "simple-bus"; - ranges = <0x0 0x00 0x1a00000 0x100000>; - reg = <0x00 0x1a00000 0x0 0x100000>; -- clock-frequency = <0>; -- interrupts = <0 44 0x4>, -- <0 45 0x4>; -+ interrupts = <0 44 0x4>, <0 45 0x4>; -+ clocks = <&clockgen 3 0>; -+ clock-names = "fmanclk"; - - cc { - compatible = "fsl,fman-cc"; diff --git a/target/linux/layerscape/patches-4.4/3028-dts-ls1043-update-dts-for-ls1043.patch b/target/linux/layerscape/patches-4.4/3028-dts-ls1043-update-dts-for-ls1043.patch deleted file mode 100644 index 0517557eb8..0000000000 --- a/target/linux/layerscape/patches-4.4/3028-dts-ls1043-update-dts-for-ls1043.patch +++ /dev/null @@ -1,523 +0,0 @@ -From ad6176d72132d020317db1496be1485056ac88d7 Mon Sep 17 00:00:00 2001 -From: Liu Gang -Date: Mon, 6 Jun 2016 15:46:00 +0800 -Subject: [PATCH 28/70] dts/ls1043: update dts for ls1043 - -Signed-off-by: Zhao Qiang ---- - arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 59 +++++ - arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 264 +++++++++++++++++++- - .../boot/dts/freescale/qoriq-qman1-portals.dtsi | 10 +- - 3 files changed, 321 insertions(+), 12 deletions(-) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts -@@ -50,6 +50,10 @@ - / { - model = "LS1043A RDB Board"; - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; -+ -+ aliases { -+ crypto = &crypto; -+ }; - }; - - &i2c0 { -@@ -108,6 +112,35 @@ - }; - }; - -+&dspi0 { -+ bus-num = <0>; -+ status = "okay"; -+ -+ flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */ -+ reg = <0>; -+ spi-max-frequency = <1000000>; /* input clock */ -+ }; -+ -+ slic@2 { -+ compatible = "maxim,ds26522"; -+ reg = <2>; -+ spi-max-frequency = <2000000>; -+ fsl,spi-cs-sck-delay = <100>; -+ fsl,spi-sck-cs-delay = <50>; -+ }; -+ -+ slic@3 { -+ compatible = "maxim,ds26522"; -+ reg = <3>; -+ spi-max-frequency = <2000000>; -+ fsl,spi-cs-sck-delay = <100>; -+ fsl,spi-sck-cs-delay = <50>; -+ }; -+}; -+ - &duart0 { - status = "okay"; - }; -@@ -176,7 +209,33 @@ - mdio@fd000 { - aqr105_phy: ethernet-phy@c { - compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 132 4>; - reg = <0x1>; - }; - }; - }; -+ -+&uqe { -+ ucc_hdlc: ucc@2000 { -+ compatible = "fsl,ucc_hdlc"; -+ rx-clock-name = "clk8"; -+ tx-clock-name = "clk9"; -+ fsl,rx-sync-clock = "rsync_pin"; -+ fsl,tx-sync-clock = "tsync_pin"; -+ fsl,tx-timeslot = <0xfffffffe>; -+ fsl,rx-timeslot = <0xfffffffe>; -+ fsl,tdm-framer-type = "e1"; -+ fsl,tdm-mode = "normal"; -+ fsl,tdm-id = <0>; -+ fsl,siram-entry-id = <0>; -+ fsl,tdm-interface; -+ }; -+ -+ ucc_serial: ucc@2200 { -+ device_type = "serial"; -+ compatible = "ucc_uart"; -+ port-number = <0>; -+ rx-clock-name = "brg2"; -+ tx-clock-name = "brg2"; -+ }; -+}; ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -@@ -44,6 +44,8 @@ - * OTHER DEALINGS IN THE SOFTWARE. - */ - -+#include -+ - / { - compatible = "fsl,ls1043a"; - interrupt-parent = <&gic>; -@@ -75,6 +77,7 @@ - compatible = "arm,cortex-a53"; - reg = <0x0>; - clocks = <&clockgen 1 0>; -+ #cooling-cells = <2>; - }; - - cpu1: cpu@1 { -@@ -118,6 +121,8 @@ - <1 14 0x1>, /* Physical Non-Secure PPI */ - <1 11 0x1>, /* Virtual PPI */ - <1 10 0x1>; /* Hypervisor PPI */ -+ arm,reread-timer; -+ fsl,erratum-a008585; - }; - - pmu { -@@ -162,11 +167,64 @@ - big-endian; - }; - -+ crypto: crypto@1700000 { -+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", -+ "fsl,sec-v4.0"; -+ fsl,sec-era = <3>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x00 0x1700000 0x100000>; -+ reg = <0x00 0x1700000 0x0 0x100000>; -+ interrupts = <0 75 0x4>; -+ -+ sec_jr0: jr@10000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x10000 0x10000>; -+ interrupts = <0 71 0x4>; -+ }; -+ -+ sec_jr1: jr@20000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x20000 0x10000>; -+ interrupts = <0 72 0x4>; -+ }; -+ -+ sec_jr2: jr@30000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ interrupts = <0 73 0x4>; -+ }; -+ -+ sec_jr3: jr@40000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x40000 0x10000>; -+ interrupts = <0 74 0x4>; -+ }; -+ }; -+ - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1043a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; - }; - -+ reset: reset@1EE00B0 { -+ compatible = "fsl,ls-reset"; -+ reg = <0x0 0x1EE00B0 0x0 0x4>; -+ big-endian; -+ }; -+ -+ rcpm: rcpm@1ee2000 { -+ compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1"; -+ reg = <0x0 0x1ee2000 0x0 0x10000>; -+ }; -+ - ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x1530000 0x0 0x10000>; -@@ -501,6 +559,82 @@ - }; - }; - -+ tmu: tmu@1f00000 { -+ compatible = "fsl,qoriq-tmu", "fsl,ls1043a-tmu"; -+ reg = <0x0 0x1f00000 0x0 0x10000>; -+ interrupts = <0 33 0x4>; -+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; -+ fsl,tmu-calibration = <0x00000000 0x00000026 -+ 0x00000001 0x0000002d -+ 0x00000002 0x00000032 -+ 0x00000003 0x00000039 -+ 0x00000004 0x0000003f -+ 0x00000005 0x00000046 -+ 0x00000006 0x0000004d -+ 0x00000007 0x00000054 -+ 0x00000008 0x0000005a -+ 0x00000009 0x00000061 -+ 0x0000000a 0x0000006a -+ 0x0000000b 0x00000071 -+ -+ 0x00010000 0x00000025 -+ 0x00010001 0x0000002c -+ 0x00010002 0x00000035 -+ 0x00010003 0x0000003d -+ 0x00010004 0x00000045 -+ 0x00010005 0x0000004e -+ 0x00010006 0x00000057 -+ 0x00010007 0x00000061 -+ 0x00010008 0x0000006b -+ 0x00010009 0x00000076 -+ -+ 0x00020000 0x00000029 -+ 0x00020001 0x00000033 -+ 0x00020002 0x0000003d -+ 0x00020003 0x00000049 -+ 0x00020004 0x00000056 -+ 0x00020005 0x00000061 -+ 0x00020006 0x0000006d -+ -+ 0x00030000 0x00000021 -+ 0x00030001 0x0000002a -+ 0x00030002 0x0000003c -+ 0x00030003 0x0000004e>; -+ big-endian; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <5000>; -+ -+ thermal-sensors = <&tmu 3>; -+ -+ trips { -+ cpu_alert: cpu-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_crit: cpu-crit { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu0 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ }; -+ - dspi0: dspi@2100000 { - compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; -@@ -527,6 +661,20 @@ - status = "disabled"; - }; - -+ qspi: quadspi@1550000 { -+ compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x1550000 0x0 0x10000>, -+ <0x0 0x40000000 0x0 0x4000000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ interrupts = <0 99 0x4>; -+ clock-names = "qspi_en", "qspi"; -+ clocks = <&clockgen 4 0>, <&clockgen 4 0>; -+ big-endian; -+ status = "disabled"; -+ }; -+ - i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; -@@ -602,8 +750,8 @@ - clocks = <&clockgen 4 0>; - }; - -- gpio1: gpio@2300000 { -- compatible = "fsl,ls1043a-gpio"; -+ gpio0: gpio@2300000 { -+ compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 66 0x4>; - gpio-controller; -@@ -612,8 +760,8 @@ - #interrupt-cells = <2>; - }; - -- gpio2: gpio@2310000 { -- compatible = "fsl,ls1043a-gpio"; -+ gpio1: gpio@2310000 { -+ compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <0 67 0x4>; - gpio-controller; -@@ -622,8 +770,8 @@ - #interrupt-cells = <2>; - }; - -- gpio3: gpio@2320000 { -- compatible = "fsl,ls1043a-gpio"; -+ gpio2: gpio@2320000 { -+ compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <0 68 0x4>; - gpio-controller; -@@ -632,8 +780,8 @@ - #interrupt-cells = <2>; - }; - -- gpio4: gpio@2330000 { -- compatible = "fsl,ls1043a-gpio"; -+ gpio3: gpio@2330000 { -+ compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = <0 134 0x4>; - gpio-controller; -@@ -642,6 +790,70 @@ - #interrupt-cells = <2>; - }; - -+ uqe: uqe@2400000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ device_type = "qe"; -+ compatible = "fsl,qe", "simple-bus"; -+ ranges = <0x0 0x0 0x2400000 0x40000>; -+ reg = <0x0 0x2400000 0x0 0x480>; -+ brg-frequency = <100000000>; -+ bus-frequency = <200000000>; -+ -+ fsl,qe-num-riscs = <1>; -+ fsl,qe-num-snums = <28>; -+ -+ qeic: qeic@80 { -+ compatible = "fsl,qe-ic"; -+ reg = <0x80 0x80>; -+ #address-cells = <0>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupts = <0 77 0x04 0 77 0x04>; -+ }; -+ -+ si1: si@700 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,qe-si"; -+ reg = <0x700 0x80>; -+ }; -+ -+ siram1: siram@1000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "fsl,qe-siram"; -+ reg = <0x1000 0x800>; -+ }; -+ -+ ucc@2000 { -+ cell-index = <1>; -+ reg = <0x2000 0x200>; -+ interrupts = <32>; -+ interrupt-parent = <&qeic>; -+ }; -+ -+ ucc@2200 { -+ cell-index = <3>; -+ reg = <0x2200 0x200>; -+ interrupts = <34>; -+ interrupt-parent = <&qeic>; -+ }; -+ -+ muram@10000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "fsl,qe-muram", "fsl,cpm-muram"; -+ ranges = <0x0 0x10000 0x6000>; -+ -+ data-only@0 { -+ compatible = "fsl,qe-muram-data", -+ "fsl,cpm-muram-data"; -+ reg = <0x0 0x6000>; -+ }; -+ }; -+ }; -+ - lpuart0: serial@2950000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2950000 0x0 0x1000>; -@@ -696,6 +908,15 @@ - status = "disabled"; - }; - -+ ftm0: ftm0@29d0000 { -+ compatible = "fsl,ftm-alarm"; -+ reg = <0x0 0x29d0000 0x0 0x10000>; -+ interrupts = <0 86 0x4>; -+ big-endian; -+ rcpm-wakeup = <&rcpm 0x0 0x20000000>; -+ status = "okay"; -+ }; -+ - wdog0: wdog@2ad0000 { - compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; -@@ -726,6 +947,8 @@ - reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = <0 60 0x4>; - dr_mode = "host"; -+ configure-gfladj; -+ snps,dis_rxdet_inp3_quirk; - }; - - usb1: usb3@3000000 { -@@ -733,6 +956,8 @@ - reg = <0x0 0x3000000 0x0 0x10000>; - interrupts = <0 61 0x4>; - dr_mode = "host"; -+ configure-gfladj; -+ snps,dis_rxdet_inp3_quirk; - }; - - usb2: usb3@3100000 { -@@ -740,6 +965,8 @@ - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 63 0x4>; - dr_mode = "host"; -+ configure-gfladj; -+ snps,dis_rxdet_inp3_quirk; - }; - - sata: sata@3200000 { -@@ -749,6 +976,20 @@ - clocks = <&clockgen 4 0>; - }; - -+ qdma: qdma@8380000 { -+ compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma"; -+ reg = <0x0 0x838f000 0x0 0x11000 /* Controller regs */ -+ 0x0 0x83a0000 0x0 0x40000>; /* Block regs */ -+ interrupts = <0 152 0x4>, -+ <0 39 0x4>; -+ interrupt-names = "qdma-error", "qdma-queue"; -+ channels = <8>; -+ queues = <2>; -+ status-sizes = <64>; -+ queue-sizes = <64 64>; -+ big-endian; -+ }; -+ - msi1: msi-controller1@1571000 { - compatible = "fsl,1s1043a-msi"; - reg = <0x0 0x1571000 0x0 0x4>, -@@ -787,6 +1028,7 @@ - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -+ dma-coherent; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ -@@ -811,6 +1053,7 @@ - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -+ dma-coherent; - num-lanes = <2>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ -@@ -835,6 +1078,7 @@ - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -+ dma-coherent; - num-lanes = <2>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ -@@ -897,8 +1141,8 @@ - alignment = <0 0x1000000>; - }; - qman_fqd: qman-fqd { -- size = <0 0x400000>; -- alignment = <0 0x400000>; -+ size = <0 0x800000>; -+ alignment = <0 0x800000>; - }; - qman_pfdr: qman-pfdr { - size = <0 0x2000000>; ---- a/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi -+++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi -@@ -132,5 +132,11 @@ - compatible = "fsl,cgrid-range"; - fsl,cgrid-range = <0 256>; - }; -- --}; -\ No newline at end of file -+ qman-ceetm@0 { -+ compatible = "fsl,qman-ceetm"; -+ fsl,ceetm-lfqid-range = <0xf00000 0x1000>; -+ fsl,ceetm-sp-range = <0 12>; -+ fsl,ceetm-lni-range = <0 8>; -+ fsl,ceetm-channel-range = <0 32>; -+ }; -+}; diff --git a/target/linux/layerscape/patches-4.4/3032-arm64-Add-pdev_archdata-for-dmamask.patch b/target/linux/layerscape/patches-4.4/3032-arm64-Add-pdev_archdata-for-dmamask.patch deleted file mode 100644 index 524687254a..0000000000 --- a/target/linux/layerscape/patches-4.4/3032-arm64-Add-pdev_archdata-for-dmamask.patch +++ /dev/null @@ -1,51 +0,0 @@ -From f7e48669bb75f3b52e9f3ce1a5d885c49b7c4712 Mon Sep 17 00:00:00 2001 -From: Cristian Sovaiala -Date: Thu, 4 Jun 2015 18:27:20 +0300 -Subject: [PATCH 32/70] arm64: Add pdev_archdata for dmamask - -The dma_mask for a device structure is a pointer. This pointer -needs to be set up before the dma mask can actually be set. Most -frameworks in the kernel take care of setting this up properly but -platform devices that don't follow a regular bus structure may not -ever have this set. As a result, checks such as dma_capable will -always return false on a raw platform device and dma_set_mask will -always return -EIO. Fix this by adding a dma_mask in the -platform_device archdata and setting it to be the dma_mask. Devices -used in other frameworks can change this as needed. - -Signed-off-by: Laura Abbott ---- - arch/arm64/include/asm/device.h | 1 + - arch/arm64/kernel/setup.c | 7 +++++++ - 2 files changed, 8 insertions(+) - ---- a/arch/arm64/include/asm/device.h -+++ b/arch/arm64/include/asm/device.h -@@ -25,6 +25,7 @@ struct dev_archdata { - }; - - struct pdev_archdata { -+ u64 dma_mask; - }; - - #endif ---- a/arch/arm64/kernel/setup.c -+++ b/arch/arm64/kernel/setup.c -@@ -44,6 +44,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -381,3 +382,9 @@ static int __init topology_init(void) - return 0; - } - subsys_initcall(topology_init); -+ -+void arch_setup_pdev_archdata(struct platform_device *pdev) -+{ -+ pdev->archdata.dma_mask = DMA_BIT_MASK(32); -+ pdev->dev.dma_mask = &pdev->archdata.dma_mask; -+} diff --git a/target/linux/layerscape/patches-4.4/3033-arm64-add-ioremap-for-normal-cacheable-non-shareable.patch b/target/linux/layerscape/patches-4.4/3033-arm64-add-ioremap-for-normal-cacheable-non-shareable.patch deleted file mode 100644 index 3dd0548b8c..0000000000 --- a/target/linux/layerscape/patches-4.4/3033-arm64-add-ioremap-for-normal-cacheable-non-shareable.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 6ef5cf7b8f6b86fb3856f3449f1ad431118e5c9d Mon Sep 17 00:00:00 2001 -From: Haiying Wang -Date: Wed, 22 Apr 2015 13:07:25 -0400 -Subject: [PATCH 33/70] arm64: add ioremap for normal cacheable non-shareable - memory - -[context adjustment] - -Signed-off-by: Haiying Wang -Change-Id: Iab7413f182a64bd6ad4707dd1d6254d04f51a3b1 -Reviewed-on: http://git.am.freescale.net:8181/35486 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Roy Pledge -Reviewed-by: Stuart Yoder -Integrated-by: Jiang Yutang ---- - arch/arm64/include/asm/io.h | 2 ++ - arch/arm64/include/asm/pgtable.h | 2 ++ - 2 files changed, 4 insertions(+) - ---- a/arch/arm64/include/asm/io.h -+++ b/arch/arm64/include/asm/io.h -@@ -171,6 +171,8 @@ extern void __iomem *ioremap_cache(phys_ - #define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) - #define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC)) - #define ioremap_wt(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) -+#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), \ -+ __pgprot(PROT_NORMAL_NS)) - #define iounmap __iounmap - - /* ---- a/arch/arm64/include/asm/pgtable.h -+++ b/arch/arm64/include/asm/pgtable.h -@@ -74,6 +74,8 @@ extern void __pgd_error(const char *file - #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC)) - #define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT)) - #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL)) -+#define PROT_NORMAL_NS (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | \ -+ PTE_ATTRINDX(MT_NORMAL)) - - #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) - #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) diff --git a/target/linux/layerscape/patches-4.4/3034-arm64-add-support-to-remap-kernel-cacheable-memory-t.patch b/target/linux/layerscape/patches-4.4/3034-arm64-add-support-to-remap-kernel-cacheable-memory-t.patch deleted file mode 100644 index 33479dcf66..0000000000 --- a/target/linux/layerscape/patches-4.4/3034-arm64-add-support-to-remap-kernel-cacheable-memory-t.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 52bffb91d40a3090ecf9138fadca97f77c99afa4 Mon Sep 17 00:00:00 2001 -From: Haiying Wang -Date: Wed, 22 Apr 2015 13:09:47 -0400 -Subject: [PATCH 34/70] arm64: add support to remap kernel cacheable memory to - userspace - -Signed-off-by: Haiying Wang -Change-Id: I50ee4798a2929932fa9ff7c9cdb42cd1a215f77a -Reviewed-on: http://git.am.freescale.net:8181/35488 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Roy Pledge -Reviewed-by: Stuart Yoder ---- - arch/arm64/include/asm/pgtable.h | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/arch/arm64/include/asm/pgtable.h -+++ b/arch/arm64/include/asm/pgtable.h -@@ -389,6 +389,9 @@ static inline int has_transparent_hugepa - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) - #define pgprot_writecombine(prot) \ - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) -+#define pgprot_cached(prot) \ -+ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \ -+ PTE_PXN | PTE_UXN) - #define pgprot_device(prot) \ - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) - #define __HAVE_PHYS_MEM_ACCESS_PROT diff --git a/target/linux/layerscape/patches-4.4/3035-arm64-pgtable-add-support-to-map-cacheable-and-non-s.patch b/target/linux/layerscape/patches-4.4/3035-arm64-pgtable-add-support-to-map-cacheable-and-non-s.patch deleted file mode 100644 index 841d5efd07..0000000000 --- a/target/linux/layerscape/patches-4.4/3035-arm64-pgtable-add-support-to-map-cacheable-and-non-s.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 1d6d5b6d2363cf5a0d175f086209fb208692ec00 Mon Sep 17 00:00:00 2001 -From: Haiying Wang -Date: Sat, 8 Aug 2015 07:25:02 -0400 -Subject: [PATCH 35/70] arm64/pgtable: add support to map cacheable and non - shareable memory - -Signed-off-by: Haiying Wang ---- - arch/arm64/include/asm/pgtable.h | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/include/asm/pgtable.h -+++ b/arch/arm64/include/asm/pgtable.h -@@ -392,6 +392,8 @@ static inline int has_transparent_hugepa - #define pgprot_cached(prot) \ - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \ - PTE_PXN | PTE_UXN) -+#define pgprot_cached_ns(prot) \ -+ __pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED) - #define pgprot_device(prot) \ - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) - #define __HAVE_PHYS_MEM_ACCESS_PROT diff --git a/target/linux/layerscape/patches-4.4/3039-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch b/target/linux/layerscape/patches-4.4/3039-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch deleted file mode 100644 index 0eac882c3e..0000000000 --- a/target/linux/layerscape/patches-4.4/3039-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 03eea243622d85d59653ee076ce43ac0653dc51d Mon Sep 17 00:00:00 2001 -From: Zhao Qiang -Date: Fri, 10 Oct 2014 10:38:48 +0800 -Subject: [PATCH 39/70] arch: arm: add ARM specific fucntions required for - ehci fsl driver - -Add below functions for ARM platform which are used by ehci fsl driver: -1. spin_event_timeout function -2. set/clear bits functions - -Signed-off-by: Zhao Qiang -Signed-off-by: Rajesh Bhagat ---- - arch/arm/include/asm/delay.h | 16 ++++++++++++++++ - arch/arm/include/asm/io.h | 28 ++++++++++++++++++++++++++++ - 2 files changed, 44 insertions(+) - ---- a/arch/arm/include/asm/delay.h -+++ b/arch/arm/include/asm/delay.h -@@ -57,6 +57,22 @@ extern void __bad_udelay(void); - __const_udelay((n) * UDELAY_MULT)) : \ - __udelay(n)) - -+#define spin_event_timeout(condition, timeout, delay) \ -+({ \ -+ typeof(condition) __ret; \ -+ int i = 0; \ -+ while (!(__ret = (condition)) && (i++ < timeout)) { \ -+ if (delay) \ -+ udelay(delay); \ -+ else \ -+ cpu_relax(); \ -+ udelay(1); \ -+ } \ -+ if (!__ret) \ -+ __ret = (condition); \ -+ __ret; \ -+}) -+ - /* Loop-based definitions for assembly code. */ - extern void __loop_delay(unsigned long loops); - extern void __loop_udelay(unsigned long usecs); ---- a/arch/arm/include/asm/io.h -+++ b/arch/arm/include/asm/io.h -@@ -221,6 +221,34 @@ extern int pci_ioremap_io(unsigned int o - #endif - #endif - -+/* access ports */ -+#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr)) -+#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr)) -+ -+#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr)) -+#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr)) -+ -+#define setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr)) -+#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr)) -+ -+/* Clear and set bits in one shot. These macros can be used to clear and -+ * set multiple bits in a register using a single read-modify-write. These -+ * macros can also be used to set a multiple-bit bit pattern using a mask, -+ * by specifying the mask in the 'clear' parameter and the new bit pattern -+ * in the 'set' parameter. -+ */ -+ -+#define clrsetbits_be32(addr, clear, set) \ -+ iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr)) -+#define clrsetbits_le32(addr, clear, set) \ -+ iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr)) -+#define clrsetbits_be16(addr, clear, set) \ -+ iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr)) -+#define clrsetbits_le16(addr, clear, set) \ -+ iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr)) -+#define clrsetbits_8(addr, clear, set) \ -+ iowrite8((ioread8(addr) & ~(clear)) | (set), (addr)) -+ - /* - * IO port access primitives - * ------------------------- diff --git a/target/linux/layerscape/patches-4.4/3063-arm64-add-NO_IRQ-macro.patch b/target/linux/layerscape/patches-4.4/3063-arm64-add-NO_IRQ-macro.patch deleted file mode 100644 index 9f34fe7015..0000000000 --- a/target/linux/layerscape/patches-4.4/3063-arm64-add-NO_IRQ-macro.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 9417a4b5978a7c38ae1dee217c3b22cda8e94731 Mon Sep 17 00:00:00 2001 -From: Mingkai Hu -Date: Thu, 19 Nov 2015 15:25:37 +0800 -Subject: [PATCH 63/70] arm64: add NO_IRQ macro - -Signed-off-by: Mingkai Hu ---- - arch/arm64/include/asm/irq.h | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/include/asm/irq.h -+++ b/arch/arm64/include/asm/irq.h -@@ -3,6 +3,14 @@ - - #include - -+/* -+ * Use this value to indicate lack of interrupt -+ * capability -+ */ -+#ifndef NO_IRQ -+#define NO_IRQ ((unsigned int)(-1)) -+#endif -+ - struct pt_regs; - - extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); diff --git a/target/linux/layerscape/patches-4.4/3071-arm64-dts-add-device-tree-for-ls1012a-SoC-and-boards.patch b/target/linux/layerscape/patches-4.4/3071-arm64-dts-add-device-tree-for-ls1012a-SoC-and-boards.patch deleted file mode 100644 index 10c11eb07f..0000000000 --- a/target/linux/layerscape/patches-4.4/3071-arm64-dts-add-device-tree-for-ls1012a-SoC-and-boards.patch +++ /dev/null @@ -1,880 +0,0 @@ -From 70e0080366e76dabf90b713f57fb9fc47aa35557 Mon Sep 17 00:00:00 2001 -From: Yangbo Lu -Date: Thu, 11 Aug 2016 10:36:05 +0800 -Subject: [PATCH 071/113] arm64: dts: add device tree for ls1012a SoC and - boards -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This patch is to add device tree for ls1012a SoC and RDB/FREEDOM boards. - -Signed-off-by: Pratiyush Mohan Srivastava -Signed-off-by: Prabhakar Kushwaha -Signed-off-by: Yunhui Cui -Signed-off-by: Rajesh Bhagat -Signed-off-by: Alison Wang -Signed-off-by: Horia Geantă -Signed-off-by: Bhaskar Upadhaya -Signed-off-by: Tang Yuantian -Signed-off-by: Chenhui Zhao -Signed-off-by: Jia Hongtao -Signed-off-by: Calvin Johnson -[yangbolu: integrate] -Signed-off-by: Yangbo Lu ---- - arch/arm64/boot/dts/freescale/Makefile | 2 + - arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 186 +++++++ - arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 114 +++++ - arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 526 ++++++++++++++++++++ - 4 files changed, 828 insertions(+) - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi - ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -2,6 +2,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2 - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb - - always := $(dtb-y) - subdir-y := $(dts-dirs) ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts -@@ -0,0 +1,186 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1012A family SoC. -+ * -+ * Copyright 2016, Freescale Semiconductor Inc. -+ -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+/dts-v1/; -+ -+#include "fsl-ls1012a.dtsi" -+ -+/ { -+ model = "LS1012A FREEDOM Board"; -+ compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; -+ -+ aliases { -+ crypto = &crypto; -+ }; -+ -+ sys_mclk: clock-mclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <25000000>; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_1p8v: regulator@0 { -+ compatible = "regulator-fixed"; -+ reg = <0>; -+ regulator-name = "1P8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ }; -+ }; -+ -+ sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,widgets = -+ "Microphone", "Microphone Jack", -+ "Headphone", "Headphone Jack", -+ "Speaker", "Speaker Ext", -+ "Line", "Line In Jack"; -+ simple-audio-card,routing = -+ "MIC_IN", "Microphone Jack", -+ "Microphone Jack", "Mic Bias", -+ "LINE_IN", "Line In Jack", -+ "Headphone Jack", "HP_OUT", -+ "Speaker Ext", "LINE_OUT"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&sai2>; -+ frame-master; -+ bitclock-master; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&codec>; -+ frame-master; -+ bitclock-master; -+ system-clock-frequency = <25000000>; -+ }; -+ }; -+}; -+ -+&qspi { -+ num-cs = <2>; -+ bus-num = <0>; -+ status = "okay"; -+ fsl,ddr-sampling-point = <4>; -+ -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ m25p,fast-read; -+ reg = <0>; -+ }; -+}; -+&ftm0 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ codec: sgtl5000@a { -+ #sound-dai-cells = <0>; -+ compatible = "fsl,sgtl5000"; -+ reg = <0xa>; -+ VDDA-supply = <®_1p8v>; -+ VDDIO-supply = <®_1p8v>; -+ clocks = <&sys_mclk 1>; -+ }; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+&pfe { -+ status = "okay"; -+ ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = < 0x0 >; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ local-mac-address = [ 00 1A 2B 3C 4D 5E ]; -+ phy-mode = "sgmii"; -+ fsl,pfe-gemac-if-name = "eth0"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ fsl,pfe-gemac-mode = <0x1B00>; /* GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G */ -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ fsl,mdio-phy-mask = <0xFFFFFFF9>; -+ }; -+ }; -+ ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = < 0x1 >; /* GEM_ID */ -+ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */ -+ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ local-mac-address = [ 00 AA BB CC DD EE ]; -+ phy-mode = "sgmii"; -+ fsl,pfe-gemac-if-name = "eth1"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ fsl,pfe-gemac-mode = <0x1B00>; /* GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G */ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ fsl,mdio-phy-mask = <0xFFFFFFF9>; -+ }; -+ -+ }; -+ -+}; -+ -+ -+&esdhc0 { -+ status = "disabled"; -+}; -+ -+&esdhc1 { -+ status = "disabled"; -+}; -+ -+&sai2 { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts -@@ -0,0 +1,114 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1012A family SoC. -+ * -+ * Copyright 2016, Freescale Semiconductor Inc. -+ -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+/dts-v1/; -+ -+#include "fsl-ls1012a.dtsi" -+ -+/ { -+ model = "LS1012A RDB Board"; -+ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; -+ -+ aliases { -+ crypto = &crypto; -+ }; -+}; -+ -+&qspi { -+ num-cs = <2>; -+ bus-num = <0>; -+ status = "okay"; -+ fsl,ddr-sampling-point = <4>; -+ -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ m25p,fast-read; -+ reg = <0>; -+ }; -+}; -+&ftm0 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+&pfe { -+ status = "okay"; -+ ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = < 0x0 >; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ local-mac-address = [ 00 1A 2B 3C 4D 5E ]; -+ phy-mode = "sgmii"; -+ fsl,pfe-gemac-if-name = "eth0"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ fsl,pfe-gemac-mode = <0x1B00>; /* GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G */ -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ fsl,mdio-phy-mask = <0xFFFFFFF9>; -+ }; -+ }; -+ ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = < 0x1 >; /* GEM_ID */ -+ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */ -+ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ local-mac-address = [ 00 AA BB CC DD EE ]; -+ phy-mode = "rgmii"; -+ fsl,pfe-gemac-if-name = "eth2"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ fsl,pfe-gemac-mode = <0x1B00>; /* GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G */ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ fsl,mdio-phy-mask = <0xFFFFFFF9>; -+ }; -+ -+ }; -+ -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi -@@ -0,0 +1,526 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1043A family SoC. -+ * -+ * Copyright 2016, Freescale Semiconductor -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include -+ -+/ { -+ compatible = "fsl,ls1012a"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* -+ * We expect the enable-method for cpu's to be "psci", but this -+ * is dependent on the SoC FW, which will fill this in. -+ * -+ * Currently supported enable-method is psci v0.2 -+ */ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0>; -+ clocks = <&clockgen 1 0>; -+ #cooling-cells = <2>; -+ }; -+ -+ }; -+ -+ -+ sysclk: sysclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "sysclk"; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = <1 13 0x1>, /* Physical Secure PPI */ -+ <1 14 0x1>, /* Physical Non-Secure PPI */ -+ <1 11 0x1>, /* Virtual PPI */ -+ <1 10 0x1>; /* Hypervisor PPI */ -+ arm,reread-timer; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = <0 106 0x4>; -+ }; -+ -+ gic: interrupt-controller@1400000 { -+ compatible = "arm,gic-400"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */ -+ <0x0 0x1402000 0 0x2000>, /* GICC */ -+ <0x0 0x1404000 0 0x2000>, /* GICH */ -+ <0x0 0x1406000 0 0x2000>; /* GICV */ -+ interrupts = <1 9 0xf08>; -+ }; -+ -+ soc { -+ compatible = "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ clockgen: clocking@1ee1000 { -+ compatible = "fsl,ls1012a-clockgen"; -+ reg = <0x0 0x1ee1000 0x0 0x1000>; -+ #clock-cells = <2>; -+ clocks = <&sysclk>; -+ }; -+ -+ scfg: scfg@1570000 { -+ compatible = "fsl,ls1012a-scfg", -+ "fsl,ls1043a-scfg", -+ "syscon"; -+ reg = <0x0 0x1570000 0x0 0x10000>; -+ big-endian; -+ }; -+ -+ crypto: crypto@1700000 { -+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", -+ "fsl,sec-v4.0"; -+ fsl,sec-era = <8>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x00 0x1700000 0x100000>; -+ reg = <0x00 0x1700000 0x0 0x100000>; -+ interrupts = <0 75 0x4>; -+ -+ sec_jr0: jr@10000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x10000 0x10000>; -+ interrupts = <0 71 0x4>; -+ }; -+ -+ sec_jr1: jr@20000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x20000 0x10000>; -+ interrupts = <0 72 0x4>; -+ }; -+ -+ sec_jr2: jr@30000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x30000 0x10000>; -+ interrupts = <0 73 0x4>; -+ }; -+ -+ sec_jr3: jr@40000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x40000 0x10000>; -+ interrupts = <0 74 0x4>; -+ }; -+ }; -+ -+ -+ dcfg: dcfg@1ee0000 { -+ compatible = "fsl,ls1012a-dcfg", -+ "fsl,ls1043a-dcfg", -+ "syscon"; -+ reg = <0x0 0x1ee0000 0x0 0x10000>; -+ }; -+ -+ reset: reset@1EE00B0 { -+ compatible = "fsl,ls-reset"; -+ reg = <0x0 0x1EE00B0 0x0 0x4>; -+ big-endian; -+ }; -+ -+ rcpm: rcpm@1ee2000 { -+ compatible = "fsl,ls1012a-rcpm", -+ "fsl,ls1043a-rcpm", -+ "fsl,qoriq-rcpm-2.1"; -+ reg = <0x0 0x1ee2000 0x0 0x10000>; -+ }; -+ -+ ftm0: ftm0@29d0000 { -+ compatible = "fsl,ftm-alarm"; -+ reg = <0x0 0x29d0000 0x0 0x10000>; -+ interrupts = <0 86 0x4>; -+ big-endian; -+ rcpm-wakeup = <&rcpm 0x00020000 0x0>; -+ status = "okay"; -+ }; -+ -+ esdhc0: esdhc@1560000 { -+ compatible = "fsl,ls1012a-esdhc0", "fsl,esdhc"; -+ reg = <0x0 0x1560000 0x0 0x10000>; -+ interrupts = <0 62 0x4>; -+ clock-frequency = <0>; -+ voltage-ranges = <1800 1800 3300 3300>; -+ sdhci,auto-cmd12; -+ big-endian; -+ bus-width = <4>; -+ }; -+ -+ esdhc1: esdhc@1580000 { -+ compatible = "fsl,ls1012a-esdhc1", "fsl,esdhc"; -+ reg = <0x0 0x1580000 0x0 0x10000>; -+ interrupts = <0 65 0x4>; -+ clock-frequency = <0>; -+ voltage-ranges = <1800 1800 3300 3300>; -+ sdhci,auto-cmd12; -+ big-endian; -+ bus-width = <4>; -+ }; -+ -+ dspi0: dspi@2100000 { -+ compatible = "fsl,ls1012a-dspi", -+ "fsl,ls1043a-dspi", -+ "fsl,ls1021a-v1.0-dspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2100000 0x0 0x10000>; -+ interrupts = <0 64 0x4>; -+ clock-names = "dspi"; -+ clocks = <&clockgen 4 0>; -+ spi-num-chipselects = <5>; -+ big-endian; -+ status = "enabled"; -+ }; -+ -+ qspi: quadspi@1550000 { -+ compatible = "fsl,ls1012a-qspi", -+ "fsl,ls1043a-qspi", -+ "fsl,ls1021a-qspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x1550000 0x0 0x10000>, -+ <0x0 0x40000000 0x0 0x4000000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ interrupts = <0 99 0x4>; -+ clock-names = "qspi_en", "qspi"; -+ clocks = <&clockgen 4 0>, <&clockgen 4 0>; -+ big-endian; -+ amba-base = <0x42000000>; -+ }; -+ -+ tmu: tmu@1f00000 { -+ compatible = "fsl,qoriq-tmu", "fsl,ls1012a-tmu"; -+ reg = <0x0 0x1f00000 0x0 0x10000>; -+ interrupts = <0 33 0x4>; -+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; -+ fsl,tmu-calibration = <0x00000000 0x00000026 -+ 0x00000001 0x0000002d -+ 0x00000002 0x00000032 -+ 0x00000003 0x00000039 -+ 0x00000004 0x0000003f -+ 0x00000005 0x00000046 -+ 0x00000006 0x0000004d -+ 0x00000007 0x00000054 -+ 0x00000008 0x0000005a -+ 0x00000009 0x00000061 -+ 0x0000000a 0x0000006a -+ 0x0000000b 0x00000071 -+ -+ 0x00010000 0x00000025 -+ 0x00010001 0x0000002c -+ 0x00010002 0x00000035 -+ 0x00010003 0x0000003d -+ 0x00010004 0x00000045 -+ 0x00010005 0x0000004e -+ 0x00010006 0x00000057 -+ 0x00010007 0x00000061 -+ 0x00010008 0x0000006b -+ 0x00010009 0x00000076 -+ -+ 0x00020000 0x00000029 -+ 0x00020001 0x00000033 -+ 0x00020002 0x0000003d -+ 0x00020003 0x00000049 -+ 0x00020004 0x00000056 -+ 0x00020005 0x00000061 -+ 0x00020006 0x0000006d -+ -+ 0x00030000 0x00000021 -+ 0x00030001 0x0000002a -+ 0x00030002 0x0000003c -+ 0x00030003 0x0000004e>; -+ big-endian; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <5000>; -+ -+ thermal-sensors = <&tmu 0>; -+ -+ trips { -+ cpu_alert: cpu-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_crit: cpu-crit { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu0 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ }; -+ -+ i2c0: i2c@2180000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2180000 0x0 0x10000>; -+ interrupts = <0 56 0x4>; -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 0>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@2190000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2190000 0x0 0x10000>; -+ interrupts = <0 57 0x4>; -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 0>; -+ status = "disabled"; -+ }; -+ -+ -+ duart0: serial@21c0500 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x00 0x21c0500 0x0 0x100>; -+ interrupts = <0 54 0x4>; -+ clocks = <&clockgen 4 0>; -+ }; -+ -+ duart1: serial@21c0600 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x00 0x21c0600 0x0 0x100>; -+ interrupts = <0 54 0x4>; -+ clocks = <&clockgen 4 0>; -+ }; -+ -+ gpio0: gpio@2300000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2300000 0x0 0x10000>; -+ interrupts = <0 66 0x4>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio1: gpio@2310000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2310000 0x0 0x10000>; -+ interrupts = <0 67 0x4>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ wdog0: wdog@2ad0000 { -+ compatible = "fsl,ls1012a-wdt", -+ "fsl,ls1043a-wdt", -+ "fsl,imx21-wdt"; -+ reg = <0x0 0x2ad0000 0x0 0x10000>; -+ interrupts = <0 83 0x4>; -+ clocks = <&clockgen 4 0>; -+ clock-names = "wdog"; -+ big-endian; -+ }; -+ -+ sai1: sai@2b50000 { -+ #sound-dai-cells = <0>; -+ compatible = "fsl,vf610-sai"; -+ reg = <0x0 0x2b50000 0x0 0x10000>; -+ interrupts = <0 148 0x4>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>, -+ <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ dma-names = "tx", "rx"; -+ dmas = <&edma0 1 47>, -+ <&edma0 1 46>; -+ status = "disabled"; -+ }; -+ -+ sai2: sai@2b60000 { -+ #sound-dai-cells = <0>; -+ compatible = "fsl,vf610-sai"; -+ reg = <0x0 0x2b60000 0x0 0x10000>; -+ interrupts = <0 149 0x4>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>, -+ <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ dma-names = "tx", "rx"; -+ dmas = <&edma0 1 45>, -+ <&edma0 1 44>; -+ status = "disabled"; -+ }; -+ -+ edma0: edma@2c00000 { -+ #dma-cells = <2>; -+ compatible = "fsl,vf610-edma"; -+ reg = <0x0 0x2c00000 0x0 0x10000>, -+ <0x0 0x2c10000 0x0 0x10000>, -+ <0x0 0x2c20000 0x0 0x10000>; -+ interrupts = <0 103 0x4>, -+ <0 103 0x4>; -+ interrupt-names = "edma-tx", "edma-err"; -+ dma-channels = <32>; -+ big-endian; -+ clock-names = "dmamux0", "dmamux1"; -+ clocks = <&clockgen 4 3>, -+ <&clockgen 4 3>; -+ }; -+ -+ sata: sata@3200000 { -+ compatible = "fsl,ls1012a-ahci"; -+ reg = <0x0 0x3200000 0x0 0x10000>; -+ interrupts = <0 69 0x4>; -+ clocks = <&clockgen 4 0>; -+ }; -+ -+ msi2: msi-controller2@1572000 { -+ compatible ="fsl,1s1012a-msi", "fsl,1s1021a-msi"; -+ reg = <0x0 0x1572000 0x0 0x4>, -+ <0x0 0x1572004 0x0 0x4>; -+ reg-names = "msiir", "msir"; -+ msi-controller; -+ interrupts = <0 126 0x4>; -+ }; -+ -+ usb@8600000 { -+ compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; -+ reg = <0x0 0x8600000 0x0 0x1000>; -+ interrupts = <0 139 0x4>; -+ dr_mode = "host"; -+ phy_type = "ulpi"; -+ fsl,usb-erratum-a005697; -+ }; -+ -+ usb0: usb3@2f00000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x2f00000 0x0 0x10000>; -+ interrupts = <0 60 0x4>; -+ dr_mode = "host"; -+ configure-gfladj; -+ snps,dis_rxdet_inp3_quirk; -+ }; -+ -+ pcie@3400000 { -+ compatible = "fsl,ls1012a-pcie", -+ "fsl,ls1043a-pcie", -+ "snps,dw-pcie"; -+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ -+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 118 0x4>, /* controller interrupt */ -+ <0 117 0x4>; /* PME interrupt */ -+ interrupt-names = "intr", "pme"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&msi2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, -+ <0000 0 0 2 &gic 0 111 0x4>, -+ <0000 0 0 3 &gic 0 112 0x4>, -+ <0000 0 0 4 &gic 0 113 0x4>; -+ }; -+ }; -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ pfe_reserved: packetbuffer@83400000 { -+ reg = <0 0x83400000 0 0xc00000>; -+ }; -+ }; -+ -+ pfe: pfe@04000000 { -+ compatible = "fsl,pfe"; -+ ranges = <0x0 0x00 0x04000000 0xc00000 -+ 0x1 0x00 0x83400000 0xc00000>; -+ reg = <0x0 0x90500000 0x0 0x10000>, /* APB 64K */ -+ <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ -+ <0x0 0x83400000 0x0 0xc00000>, /* PFE DDR 12M */ -+ <0x0 0x10000000 0x0 0x2000>; /* OCRAM 8K */ -+ fsl,pfe-num-interfaces = < 0x2 >; -+ interrupts = <0 172 0x4>; -+ #interrupt-names = "hifirq"; -+ memory-region = <&pfe_reserved>; -+ fsl,pfe-scfg = <&scfg 0>; -+ }; -+ -+}; diff --git a/target/linux/layerscape/patches-4.4/3117-armv8-aarch32-Run-32-bit-Linux-for-LayerScape-SoCs.patch b/target/linux/layerscape/patches-4.4/3117-armv8-aarch32-Run-32-bit-Linux-for-LayerScape-SoCs.patch deleted file mode 100644 index 9b580b4730..0000000000 --- a/target/linux/layerscape/patches-4.4/3117-armv8-aarch32-Run-32-bit-Linux-for-LayerScape-SoCs.patch +++ /dev/null @@ -1,49 +0,0 @@ -From f6dcf8936845ea95eba432ee725cec761032fe2a Mon Sep 17 00:00:00 2001 -From: Ying Zhang -Date: Thu, 29 Sep 2016 10:12:29 +0800 -Subject: [PATCH 117/124] armv8: aarch32: Run 32-bit Linux for LayerScape SoCs - -This patch adds AArch32 execution state support for LayerScape SoCs. - -Signed-off-by: Ebony Zhu -Signed-off-by: Alison Wang ---- - arch/arm/mach-imx/Makefile | 2 ++ - arch/arm/mach-imx/mach-layerscape.c | 22 ++++++++++++++++++++++ - 2 files changed, 24 insertions(+) - create mode 100644 arch/arm/mach-imx/mach-layerscape.c - ---- a/arch/arm/mach-imx/Makefile -+++ b/arch/arm/mach-imx/Makefile -@@ -103,4 +103,6 @@ obj-$(CONFIG_SOC_LS1021A) += mach-ls1021 - - obj-$(CONFIG_ARCH_LAYERSCAPE) += mach-ls1043a.o - -+obj-$(CONFIG_ARCH_LAYERSCAPE) += mach-layerscape.o -+ - obj-y += devices/ ---- /dev/null -+++ b/arch/arm/mach-imx/mach-layerscape.c -@@ -0,0 +1,22 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+ -+#include "common.h" -+ -+static const char * const layerscape_dt_compat[] __initconst = { -+ "fsl,ls1043a", -+ "fsl,ls1012a", -+ NULL, -+}; -+ -+DT_MACHINE_START(LAYERSCAPE, "Freescale LAYERSCAPE") -+ .dt_compat = layerscape_dt_compat, -+MACHINE_END diff --git a/target/linux/layerscape/patches-4.4/3118-armv8-aarch32-Add-KVM-support-for-AArch32-on-ARMv8.patch b/target/linux/layerscape/patches-4.4/3118-armv8-aarch32-Add-KVM-support-for-AArch32-on-ARMv8.patch deleted file mode 100644 index 32ebc36b1f..0000000000 --- a/target/linux/layerscape/patches-4.4/3118-armv8-aarch32-Add-KVM-support-for-AArch32-on-ARMv8.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 44914d3b7baff0f96c3584e4d46aa992e402ef4f Mon Sep 17 00:00:00 2001 -From: Ying Zhang -Date: Thu, 29 Sep 2016 11:16:16 +0800 -Subject: [PATCH 118/124] armv8: aarch32: Add KVM support for AArch32 on ARMv8 - -This patch is to add KVM support for AArch32 execution state on ARMv8. - -Signed-off-by: Alison Wang ---- - arch/arm/include/asm/cputype.h | 2 ++ - arch/arm/kvm/guest.c | 1 + - 2 files changed, 3 insertions(+) - ---- a/arch/arm/include/asm/cputype.h -+++ b/arch/arm/include/asm/cputype.h -@@ -76,6 +76,8 @@ - #define ARM_CPU_PART_CORTEX_A15 0x4100c0f0 - #define ARM_CPU_PART_MASK 0xff00fff0 - -+#define ARM_CPU_PART_CORTEX_AARCH32_A53 0x4100d030 -+ - #define ARM_CPU_XSCALE_ARCH_MASK 0xe000 - #define ARM_CPU_XSCALE_ARCH_V1 0x2000 - #define ARM_CPU_XSCALE_ARCH_V2 0x4000 ---- a/arch/arm/kvm/guest.c -+++ b/arch/arm/kvm/guest.c -@@ -247,6 +247,7 @@ int __attribute_const__ kvm_target_cpu(v - { - switch (read_cpuid_part()) { - case ARM_CPU_PART_CORTEX_A7: -+ case ARM_CPU_PART_CORTEX_AARCH32_A53: - return KVM_ARM_TARGET_CORTEX_A7; - case ARM_CPU_PART_CORTEX_A15: - return KVM_ARM_TARGET_CORTEX_A15; diff --git a/target/linux/layerscape/patches-4.4/3131-arm64-ls1046a-add-DTS-for-Freescale-LS1046A-SoC.patch b/target/linux/layerscape/patches-4.4/3131-arm64-ls1046a-add-DTS-for-Freescale-LS1046A-SoC.patch deleted file mode 100644 index ca11f9fb8b..0000000000 --- a/target/linux/layerscape/patches-4.4/3131-arm64-ls1046a-add-DTS-for-Freescale-LS1046A-SoC.patch +++ /dev/null @@ -1,1056 +0,0 @@ -From 80ca93f1a5590529e39560099a71edb03897050e Mon Sep 17 00:00:00 2001 -From: Mingkai Hu -Date: Wed, 11 May 2016 11:29:51 +0800 -Subject: [PATCH 131/141] arm64/ls1046a: add DTS for Freescale LS1046A SoC - -LS1046a is an SoC with 4 ARMv8 A72 cores and most other IP blocks -similar to LS1043a which complies to Chassis 2.1 spec. - -Following levels of DTSI/DTS files have been created for the -LS1046A SoC family: - -- fsl-ls1046a.dtsi: - DTS-Include file for FSL LS1046A SoC. - -Signed-off-by: Gong Qianyu -Signed-off-by: Minghuan Lian -Signed-off-by: Hou Zhiqiang -Signed-off-by: Mihai Bantea -Signed-off-by: Mingkai Hu ---- - arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1029 ++++++++++++++++++++++++ - 1 file changed, 1029 insertions(+) - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi - ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi -@@ -0,0 +1,1029 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1046A family SoC. -+ * -+ * Copyright 2016, Freescale Semiconductor -+ * -+ * Mingkai Hu -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/ { -+ compatible = "fsl,ls1046a"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ ethernet0 = &fm1mac1; -+ ethernet1 = &fm1mac2; -+ ethernet2 = &fm1mac3; -+ ethernet3 = &fm1mac4; -+ ethernet4 = &fm1mac5; -+ ethernet5 = &fm1mac6; -+ ethernet6 = &fm1mac9; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x0>; -+ clocks = <&clockgen 1 0>; -+ next-level-cache = <&l2>; -+ }; -+ -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x1>; -+ clocks = <&clockgen 1 0>; -+ next-level-cache = <&l2>; -+ }; -+ -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x2>; -+ clocks = <&clockgen 1 0>; -+ next-level-cache = <&l2>; -+ }; -+ -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x3>; -+ clocks = <&clockgen 1 0>; -+ next-level-cache = <&l2>; -+ }; -+ -+ l2: l2-cache { -+ compatible = "cache"; -+ }; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x0 0x80000000 0 0x80000000>; -+ /* DRAM space 1, size: 2GiB DRAM */ -+ }; -+ -+ sysclk: sysclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "sysclk"; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = <1 13 0x1>, /* Physical Secure PPI */ -+ <1 14 0x1>, /* Physical Non-Secure PPI */ -+ <1 11 0x1>, /* Virtual PPI */ -+ <1 10 0x1>; /* Hypervisor PPI */ -+ arm,reread-timer; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = <0 106 0x4>, -+ <0 107 0x4>, -+ <0 95 0x4>, -+ <0 97 0x4>; -+ interrupt-affinity = <&cpu0>, -+ <&cpu1>, -+ <&cpu2>, -+ <&cpu3>; -+ }; -+ -+ gic: interrupt-controller@1400000 { -+ compatible = "arm,gic-400"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ reg = <0x0 0x1410000 0 0x10000>, /* GICD */ -+ <0x0 0x1420000 0 0x20000>, /* GICC */ -+ <0x0 0x1440000 0 0x20000>, /* GICH */ -+ <0x0 0x1460000 0 0x20000>; /* GICV */ -+ interrupts = <1 9 0xf08>; -+ }; -+ -+ soc { -+ compatible = "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ clockgen: clocking@1ee1000 { -+ compatible = "fsl,ls1046a-clockgen"; -+ reg = <0x0 0x1ee1000 0x0 0x1000>; -+ #clock-cells = <2>; -+ clocks = <&sysclk>; -+ }; -+ -+ scfg: scfg@1570000 { -+ compatible = "fsl,ls1046a-scfg", "syscon"; -+ reg = <0x0 0x1570000 0x0 0x10000>; -+ big-endian; -+ }; -+ -+ reset: reset@1ee00b0 { -+ compatible = "fsl,ls-reset"; -+ reg = <0x0 0x1ee00b0 0x0 0x4>; -+ big-endian; -+ }; -+ -+ rcpm: rcpm@1ee2000 { -+ compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1"; -+ reg = <0x0 0x1ee2000 0x0 0x10000>; -+ }; -+ -+ ifc: ifc@1530000 { -+ compatible = "fsl,ifc", "simple-bus"; -+ reg = <0x0 0x1530000 0x0 0x10000>; -+ interrupts = <0 43 0x4>; -+ }; -+ -+ esdhc: esdhc@1560000 { -+ compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; -+ reg = <0x0 0x1560000 0x0 0x10000>; -+ interrupts = <0 62 0x4>; -+ clock-frequency = <0>; -+ voltage-ranges = <1800 1800 3300 3300>; -+ sdhci,auto-cmd12; -+ big-endian; -+ bus-width = <4>; -+ }; -+ -+ qman: qman@1880000 { -+ compatible = "fsl,qman"; -+ reg = <0x00 0x1880000 0x0 0x10000>; -+ interrupts = <0 45 0x4>; -+ }; -+ -+ bman: bman@1890000 { -+ compatible = "fsl,bman"; -+ reg = <0x00 0x1890000 0x0 0x10000>; -+ interrupts = <0 45 0x4>; -+ }; -+ -+ fman0: fman@1a00000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ cell-index = <0>; -+ compatible = "fsl,fman", "simple-bus"; -+ ranges = <0x0 0x00 0x1a00000 0x100000>; -+ reg = <0x00 0x1a00000 0x0 0x100000>; -+ interrupts = <0 44 0x4>, <0 45 0x4>; -+ clocks = <&clockgen 3 0>; -+ clock-names = "fmanclk"; -+ -+ cc { -+ compatible = "fsl,fman-cc"; -+ }; -+ -+ muram@0 { -+ compatible = "fsl,fman-muram"; -+ reg = <0x0 0x60000>; -+ }; -+ -+ bmi@80000 { -+ compatible = "fsl,fman-bmi"; -+ reg = <0x80000 0x400>; -+ }; -+ -+ qmi@80400 { -+ compatible = "fsl,fman-qmi"; -+ reg = <0x80400 0x400>; -+ }; -+ -+ fman0_oh1: port@82000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x82000 0x1000>; -+ }; -+ -+ fman0_oh2: port@83000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x83000 0x1000>; -+ }; -+ -+ fman0_oh3: port@84000 { -+ cell-index = <2>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x84000 0x1000>; -+ }; -+ -+ fman0_oh4: port@85000 { -+ cell-index = <3>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x85000 0x1000>; -+ }; -+ -+ fman0_oh5: port@86000 { -+ cell-index = <4>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x86000 0x1000>; -+ }; -+ -+ fman0_oh6: port@87000 { -+ cell-index = <5>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x87000 0x1000>; -+ }; -+ -+ policer@c0000 { -+ compatible = "fsl,fman-policer"; -+ reg = <0xc0000 0x1000>; -+ }; -+ -+ keygen@c1000 { -+ compatible = "fsl,fman-keygen"; -+ reg = <0xc1000 0x1000>; -+ }; -+ -+ dma@c2000 { -+ compatible = "fsl,fman-dma"; -+ reg = <0xc2000 0x1000>; -+ }; -+ -+ fpm@c3000 { -+ compatible = "fsl,fman-fpm"; -+ reg = <0xc3000 0x1000>; -+ }; -+ -+ parser@c7000 { -+ compatible = "fsl,fman-parser"; -+ reg = <0xc7000 0x1000>; -+ }; -+ -+ vsps@dc000 { -+ compatible = "fsl,fman-vsps"; -+ reg = <0xdc000 0x1000>; -+ }; -+ -+ mdio0: mdio@fc000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xfc000 0x1000>; -+ }; -+ -+ xmdio0: mdio@fd000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xfd000 0x1000>; -+ }; -+ -+ fman0_rx0: port@88000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-1g-rx"; -+ reg = <0x88000 0x1000>; -+ }; -+ -+ fman0_tx0: port@a8000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-1g-tx"; -+ reg = <0xa8000 0x1000>; -+ }; -+ -+ fm1mac1: ethernet@e0000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe0000 0x1000>; -+ fsl,port-handles = <&fman0_rx0 &fman0_tx0>; -+ ptimer-handle = <&ptp_timer0>; -+ }; -+ -+ mdio@e1000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xe1000 0x1000>; -+ }; -+ -+ fman0_rx1: port@89000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-1g-rx"; -+ reg = <0x89000 0x1000>; -+ }; -+ -+ fman0_tx1: port@a9000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-1g-tx"; -+ reg = <0xa9000 0x1000>; -+ }; -+ -+ fm1mac2: ethernet@e2000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe2000 0x1000>; -+ fsl,port-handles = <&fman0_rx1 &fman0_tx1>; -+ ptimer-handle = <&ptp_timer0>; -+ }; -+ -+ mdio@e3000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xe3000 0x1000>; -+ }; -+ -+ fman0_rx2: port@8a000 { -+ cell-index = <2>; -+ compatible = "fsl,fman-port-1g-rx"; -+ reg = <0x8a000 0x1000>; -+ }; -+ -+ fman0_tx2: port@aa000 { -+ cell-index = <2>; -+ compatible = "fsl,fman-port-1g-tx"; -+ reg = <0xaa000 0x1000>; -+ }; -+ -+ fm1mac3: ethernet@e4000 { -+ cell-index = <2>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe4000 0x1000>; -+ fsl,port-handles = <&fman0_rx2 &fman0_tx2>; -+ ptimer-handle = <&ptp_timer0>; -+ }; -+ -+ mdio@e5000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xe5000 0x1000>; -+ }; -+ -+ fman0_rx3: port@8b000 { -+ cell-index = <3>; -+ compatible = "fsl,fman-port-1g-rx"; -+ reg = <0x8b000 0x1000>; -+ }; -+ -+ fman0_tx3: port@ab000 { -+ cell-index = <3>; -+ compatible = "fsl,fman-port-1g-tx"; -+ reg = <0xab000 0x1000>; -+ }; -+ -+ fm1mac4: ethernet@e6000 { -+ cell-index = <3>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe6000 0x1000>; -+ fsl,port-handles = <&fman0_rx3 &fman0_tx3>; -+ ptimer-handle = <&ptp_timer0>; -+ }; -+ -+ mdio@e7000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xe7000 0x1000>; -+ }; -+ -+ fman0_rx4: port@8c000 { -+ cell-index = <4>; -+ compatible = "fsl,fman-port-1g-rx"; -+ reg = <0x8c000 0x1000>; -+ }; -+ -+ fman0_tx4: port@ac000 { -+ cell-index = <4>; -+ compatible = "fsl,fman-port-1g-tx"; -+ reg = <0xac000 0x1000>; -+ }; -+ -+ fm1mac5: ethernet@e8000 { -+ cell-index = <4>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe8000 0x1000>; -+ fsl,port-handles = <&fman0_rx4 &fman0_tx4>; -+ ptimer-handle = <&ptp_timer0>; -+ }; -+ -+ mdio@e9000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xe9000 0x1000>; -+ }; -+ -+ fman0_rx5: port@8d000 { -+ cell-index = <5>; -+ compatible = "fsl,fman-port-1g-rx"; -+ reg = <0x8d000 0x1000>; -+ }; -+ -+ fman0_tx5: port@ad000 { -+ cell-index = <5>; -+ compatible = "fsl,fman-port-1g-tx"; -+ reg = <0xad000 0x1000>; -+ }; -+ -+ fm1mac6: ethernet@ea000 { -+ cell-index = <5>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xea000 0x1000>; -+ fsl,port-handles = <&fman0_rx5 &fman0_tx5>; -+ ptimer-handle = <&ptp_timer0>; -+ }; -+ -+ mdio@eb000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xeb000 0x1000>; -+ }; -+ -+ fman0_10g_rx0: port@90000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-10g-rx"; -+ reg = <0x90000 0x1000>; -+ }; -+ -+ fman0_10g_tx0: port@b0000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-10g-tx"; -+ reg = <0xb0000 0x1000>; -+ fsl,qman-channel-id = <0x800>; -+ }; -+ -+ fm1mac9: ethernet@f0000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xf0000 0x1000>; -+ fsl,port-handles = <&fman0_10g_rx0 &fman0_10g_tx0>; -+ }; -+ -+ mdio@f1000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xf1000 0x1000>; -+ }; -+ -+ ptp_timer0: rtc@fe000 { -+ compatible = "fsl,fman-rtc"; -+ reg = <0xfe000 0x1000>; -+ }; -+ }; -+ -+ dspi: dspi@2100000 { -+ compatible = "fsl,ls1046a-dspi", "fsl,ls1021a-v1.0-dspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2100000 0x0 0x10000>; -+ interrupts = <0 64 0x4>; -+ clock-names = "dspi"; -+ clocks = <&clockgen 4 1>; -+ spi-num-chipselects = <5>; -+ big-endian; -+ status = "disabled"; -+ }; -+ -+ qspi: quadspi@1550000 { -+ compatible = "fsl,ls1046a-qspi", "fsl,ls1021a-qspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x1550000 0x0 0x10000>, -+ <0x0 0x40000000 0x0 0x10000000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ interrupts = <0 99 0x4>; -+ clock-names = "qspi_en", "qspi"; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>; -+ big-endian; -+ fsl,qspi-has-second-chip; -+ status = "disabled"; -+ }; -+ -+ i2c0: i2c@2180000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2180000 0x0 0x10000>; -+ interrupts = <0 56 0x4>; -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 1>; -+ dmas = <&edma0 1 39>, -+ <&edma0 1 38>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@2190000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2190000 0x0 0x10000>; -+ interrupts = <0 57 0x4>; -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 1>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@21a0000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x21a0000 0x0 0x10000>; -+ interrupts = <0 58 0x4>; -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 1>; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@21b0000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x21b0000 0x0 0x10000>; -+ interrupts = <0 59 0x4>; -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 1>; -+ status = "disabled"; -+ }; -+ -+ duart0: serial@21c0500 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x00 0x21c0500 0x0 0x100>; -+ interrupts = <0 54 0x4>; -+ clocks = <&clockgen 4 1>; -+ }; -+ -+ duart1: serial@21c0600 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x00 0x21c0600 0x0 0x100>; -+ interrupts = <0 54 0x4>; -+ clocks = <&clockgen 4 1>; -+ }; -+ -+ duart2: serial@21d0500 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21d0500 0x0 0x100>; -+ interrupts = <0 55 0x4>; -+ clocks = <&clockgen 4 1>; -+ }; -+ -+ duart3: serial@21d0600 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21d0600 0x0 0x100>; -+ interrupts = <0 55 0x4>; -+ clocks = <&clockgen 4 1>; -+ }; -+ -+ gpio0: gpio@2300000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2300000 0x0 0x10000>; -+ interrupts = <0 66 0x4>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio1: gpio@2310000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2310000 0x0 0x10000>; -+ interrupts = <0 67 0x4>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio2: gpio@2320000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2320000 0x0 0x10000>; -+ interrupts = <0 68 0x4>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio3: gpio@2330000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2330000 0x0 0x10000>; -+ interrupts = <0 134 0x4>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ lpuart0: serial@2950000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2950000 0x0 0x1000>; -+ interrupts = <0 48 0x4>; -+ clocks = <&clockgen 0 0>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart1: serial@2960000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2960000 0x0 0x1000>; -+ interrupts = <0 49 0x4>; -+ clocks = <&clockgen 4 1>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart2: serial@2970000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2970000 0x0 0x1000>; -+ interrupts = <0 50 0x4>; -+ clocks = <&clockgen 4 1>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart3: serial@2980000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2980000 0x0 0x1000>; -+ interrupts = <0 51 0x4>; -+ clocks = <&clockgen 4 1>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart4: serial@2990000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2990000 0x0 0x1000>; -+ interrupts = <0 52 0x4>; -+ clocks = <&clockgen 4 1>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart5: serial@29a0000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x29a0000 0x0 0x1000>; -+ interrupts = <0 53 0x4>; -+ clocks = <&clockgen 4 1>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ ftm0: ftm0@29d0000 { -+ compatible = "fsl,ftm-alarm"; -+ reg = <0x0 0x29d0000 0x0 0x10000>; -+ interrupts = <0 86 0x4>; -+ big-endian; -+ rcpm-wakeup = <&rcpm 0x0 0x20000000>; -+ status = "okay"; -+ }; -+ -+ wdog0: wdog@2ad0000 { -+ compatible = "fsl,ls1046a-wdt", "fsl,imx21-wdt"; -+ reg = <0x0 0x2ad0000 0x0 0x10000>; -+ interrupts = <0 83 0x4>; -+ clocks = <&clockgen 4 1>; -+ clock-names = "wdog"; -+ big-endian; -+ }; -+ -+ edma0: edma@2c00000 { -+ #dma-cells = <2>; -+ compatible = "fsl,vf610-edma"; -+ reg = <0x0 0x2c00000 0x0 0x10000>, -+ <0x0 0x2c10000 0x0 0x10000>, -+ <0x0 0x2c20000 0x0 0x10000>; -+ interrupts = <0 103 0x4>, -+ <0 103 0x4>; -+ interrupt-names = "edma-tx", "edma-err"; -+ dma-channels = <32>; -+ big-endian; -+ clock-names = "dmamux0", "dmamux1"; -+ clocks = <&clockgen 4 1>, -+ <&clockgen 4 1>; -+ }; -+ -+ usb0: usb3@2f00000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x2f00000 0x0 0x10000>; -+ interrupts = <0 60 0x4>; -+ dr_mode = "host"; -+ configure-gfladj; -+ snps,dis_rxdet_inp3_quirk; -+ }; -+ -+ usb1: usb3@3000000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3000000 0x0 0x10000>; -+ interrupts = <0 61 0x4>; -+ dr_mode = "host"; -+ configure-gfladj; -+ snps,dis_rxdet_inp3_quirk; -+ }; -+ -+ usb2: usb3@3100000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3100000 0x0 0x10000>; -+ interrupts = <0 63 0x4>; -+ dr_mode = "host"; -+ configure-gfladj; -+ snps,dis_rxdet_inp3_quirk; -+ }; -+ -+ sata: sata@3200000 { -+ compatible = "fsl,ls1046a-ahci"; -+ reg = <0x0 0x3200000 0x0 0x10000>; -+ interrupts = <0 69 0x4>; -+ clocks = <&clockgen 4 1>; -+ }; -+ -+ qdma: qdma@8380000 { -+ compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; -+ reg = <0x0 0x838f000 0x0 0x11000 /* Controller regs */ -+ 0x0 0x83a0000 0x0 0x40000>; /* Block regs */ -+ interrupts = <0 152 0x4>, -+ <0 39 0x4>; -+ interrupt-names = "qdma-error", "qdma-queue"; -+ channels = <8>; -+ queues = <2>; -+ status-sizes = <64>; -+ queue-sizes = <64 64>; -+ big-endian; -+ }; -+ -+ msi1: msi-controller@1580000 { -+ compatible = "fsl,1s1046a-msi"; -+ reg = <0x0 0x1580000 0x0 0x10000>; -+ msi-controller; -+ interrupts = <0 116 0x4>, -+ <0 111 0x4>, -+ <0 112 0x4>, -+ <0 113 0x4>; -+ }; -+ -+ msi2: msi-controller@1590000 { -+ compatible = "fsl,1s1046a-msi"; -+ reg = <0x0 0x1590000 0x0 0x10000>; -+ msi-controller; -+ interrupts = <0 126 0x4>, -+ <0 121 0x4>, -+ <0 122 0x4>, -+ <0 123 0x4>; -+ }; -+ -+ msi3: msi-controller@15a0000 { -+ compatible = "fsl,1s1046a-msi"; -+ reg = <0x0 0x15a0000 0x0 0x10000>; -+ msi-controller; -+ interrupts = <0 160 0x4>, -+ <0 155 0x4>, -+ <0 156 0x4>, -+ <0 157 0x4>; -+ }; -+ -+ pcie@3400000 { -+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ -+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 118 0x4>, /* controller interrupt */ -+ <0 117 0x4>; /* PME interrupt */ -+ interrupt-names = "intr", "pme"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&msi1>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, -+ <0000 0 0 2 &gic 0 110 0x4>, -+ <0000 0 0 3 &gic 0 110 0x4>, -+ <0000 0 0 4 &gic 0 110 0x4>; -+ }; -+ -+ pcie@3500000 { -+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ -+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 128 0x4>, -+ <0 127 0x4>; -+ interrupt-names = "intr", "pme"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ num-lanes = <2>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&msi2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, -+ <0000 0 0 2 &gic 0 120 0x4>, -+ <0000 0 0 3 &gic 0 120 0x4>, -+ <0000 0 0 4 &gic 0 120 0x4>; -+ }; -+ -+ pcie@3600000 { -+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ -+ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 162 0x4>, -+ <0 161 0x4>; -+ interrupt-names = "intr", "pme"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ num-lanes = <2>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&msi3>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, -+ <0000 0 0 2 &gic 0 154 0x4>, -+ <0000 0 0 3 &gic 0 154 0x4>, -+ <0000 0 0 4 &gic 0 154 0x4>; -+ }; -+ }; -+ -+ fsl,dpaa { -+ compatible = "fsl,ls1046a-dpaa", "simple-bus", "fsl,dpaa"; -+ ethernet@0 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac1>; -+ }; -+ ethernet@1 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac2>; -+ }; -+ ethernet@2 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac3>; -+ }; -+ ethernet@3 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac4>; -+ }; -+ ethernet@4 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac5>; -+ }; -+ ethernet@5 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac6>; -+ }; -+ ethernet@8 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac9>; -+ }; -+ }; -+ -+ qportals: qman-portals@500000000 { -+ ranges = <0x0 0x5 0x00000000 0x8000000>; -+ }; -+ bportals: bman-portals@508000000 { -+ ranges = <0x0 0x5 0x08000000 0x8000000>; -+ }; -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ bman_fbpr: bman-fbpr { -+ size = <0 0x1000000>; -+ alignment = <0 0x1000000>; -+ }; -+ qman_fqd: qman-fqd { -+ size = <0 0x800000>; -+ alignment = <0 0x800000>; -+ }; -+ qman_pfdr: qman-pfdr { -+ size = <0 0x2000000>; -+ alignment = <0 0x2000000>; -+ }; -+ }; -+}; -+ -+&fman0 { -+ /* offline - 1 */ -+ port@82000 { -+ fsl,qman-channel-id = <0x809>; -+ }; -+ -+ /* tx - 10g - 2 */ -+ port@a8000 { -+ fsl,qman-channel-id = <0x802>; -+ }; -+ /* tx - 10g - 3 */ -+ port@a9000 { -+ fsl,qman-channel-id = <0x803>; -+ }; -+ /* tx - 1g - 2 */ -+ port@aa000 { -+ fsl,qman-channel-id = <0x804>; -+ }; -+ /* tx - 1g - 3 */ -+ port@ab000 { -+ fsl,qman-channel-id = <0x805>; -+ }; -+ /* tx - 1g - 4 */ -+ port@ac000 { -+ fsl,qman-channel-id = <0x806>; -+ }; -+ /* tx - 1g - 5 */ -+ port@ad000 { -+ fsl,qman-channel-id = <0x807>; -+ }; -+ /* tx - 10g - 0 */ -+ port@b0000 { -+ fsl,qman-channel-id = <0x800>; -+ }; -+ /* tx - 10g - 1 */ -+ port@b1000 { -+ fsl,qman-channel-id = <0x801>; -+ }; -+ /* offline - 2 */ -+ port@83000 { -+ fsl,qman-channel-id = <0x80a>; -+ }; -+ /* offline - 3 */ -+ port@84000 { -+ fsl,qman-channel-id = <0x80b>; -+ }; -+ /* offline - 4 */ -+ port@85000 { -+ fsl,qman-channel-id = <0x80c>; -+ }; -+ /* offline - 5 */ -+ port@86000 { -+ fsl,qman-channel-id = <0x80d>; -+ }; -+ /* offline - 6 */ -+ port@87000 { -+ fsl,qman-channel-id = <0x80e>; -+ }; -+}; -+ -+&bman_fbpr { -+ compatible = "fsl,bman-fbpr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+&qman_fqd { -+ compatible = "fsl,qman-fqd"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+&qman_pfdr { -+ compatible = "fsl,qman-pfdr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+/include/ "qoriq-qman1-portals.dtsi" -+/include/ "qoriq-bman1-portals.dtsi" diff --git a/target/linux/layerscape/patches-4.4/3132-dts-ls1046a-add-LS1046ARDB-board-support.patch b/target/linux/layerscape/patches-4.4/3132-dts-ls1046a-add-LS1046ARDB-board-support.patch deleted file mode 100644 index 77b53d76b3..0000000000 --- a/target/linux/layerscape/patches-4.4/3132-dts-ls1046a-add-LS1046ARDB-board-support.patch +++ /dev/null @@ -1,557 +0,0 @@ -From feb12cb699adbac2d4619401c7ff4fcc2fc97b6c Mon Sep 17 00:00:00 2001 -From: Mingkai Hu -Date: Mon, 26 Sep 2016 12:33:42 +0800 -Subject: [PATCH 132/141] dts/ls1046a: add LS1046ARDB board support - -commit e95a28cfd9a392fe5dc189a9ae097bbaaccd1228 -[context adjustment] - -Signed-off-by: Mingkai Hu -Integrated-by: Zhao Qiang ---- - arch/arm64/boot/dts/freescale/Makefile | 1 + - arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 198 +++++++++++++++++++++ - arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 178 +++++++++++++----- - 3 files changed, 328 insertions(+), 49 deletions(-) - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts - ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2 - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb - - always := $(dtb-y) - subdir-y := $(dts-dirs) ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts -@@ -0,0 +1,198 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1046A family SoC. -+ * -+ * Copyright 2016, Freescale Semiconductor -+ * -+ * Mingkai Hu -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+#include "fsl-ls1046a.dtsi" -+ -+/ { -+ model = "LS1046A RDB Board"; -+ compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; -+ -+ aliases { -+ ethernet0 = &fm1mac3; -+ ethernet1 = &fm1mac4; -+ ethernet2 = &fm1mac5; -+ ethernet3 = &fm1mac6; -+ ethernet4 = &fm1mac9; -+ ethernet5 = &fm1mac10; -+ }; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ ina220@40 { -+ compatible = "ti,ina220"; -+ reg = <0x40>; -+ shunt-resistor = <1000>; -+ }; -+ adt7461a@4c { -+ compatible = "adi,adt7461"; -+ reg = <0x4c>; -+ }; -+ eeprom@56 { -+ compatible = "at24,24c512"; -+ reg = <0x52>; -+ }; -+ eeprom@57 { -+ compatible = "at24,24c512"; -+ reg = <0x53>; -+ }; -+}; -+ -+&i2c3 { -+ status = "okay"; -+ rtc@51 { -+ compatible = "nxp,pcf2129"; -+ reg = <0x51>; -+ }; -+}; -+ -+&ifc { -+ status = "okay"; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ /* NAND Flashe and CPLD on board */ -+ ranges = <0x0 0x0 0x0 0x7e800000 0x00010000 -+ 0x2 0x0 0x0 0x7fb00000 0x00000100>; -+ -+ nand@0,0 { -+ compatible = "fsl,ifc-nand"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x0 0x0 0x10000>; -+ }; -+ -+ cpld: board-control@2,0 { -+ compatible = "fsl,ls1046ardb-cpld"; -+ reg = <0x2 0x0 0x0000100>; -+ }; -+}; -+ -+&qspi { -+ num-cs = <2>; -+ bus-num = <0>; -+ status = "okay"; -+ -+ qflash0: s25fs128s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+ -+ qflash1: s25fs128s@1 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <1>; -+ }; -+ -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+ -+&duart1 { -+ status = "okay"; -+}; -+ -+&fman0 { -+ ethernet@e4000 { -+ phy-handle = <&rgmii_phy1>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e6000 { -+ phy-handle = <&rgmii_phy2>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e8000 { -+ phy-handle = <&sgmii_phy1>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@ea000 { -+ phy-handle = <&sgmii_phy2>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@f0000 { /* 10GEC1 */ -+ phy-handle = <&aqr106_phy>; -+ phy-connection-type = "xgmii"; -+ }; -+ -+ ethernet@f2000 { /* 10GEC2 */ -+ fixed-link = <0 1 10000 0 0>; -+ phy-connection-type = "xgmii"; -+ }; -+ -+ mdio@fc000 { -+ rgmii_phy1: ethernet-phy@1 { -+ reg = <0x1>; -+ }; -+ rgmii_phy2: ethernet-phy@2 { -+ reg = <0x2>; -+ }; -+ sgmii_phy1: ethernet-phy@3 { -+ reg = <0x3>; -+ }; -+ sgmii_phy2: ethernet-phy@4 { -+ reg = <0x4>; -+ }; -+ }; -+ -+ mdio@fd000 { -+ aqr106_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 131 4>; -+ reg = <0x0>; -+ }; -+ }; -+}; ---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi -@@ -51,13 +51,7 @@ - #size-cells = <2>; - - aliases { -- ethernet0 = &fm1mac1; -- ethernet1 = &fm1mac2; -- ethernet2 = &fm1mac3; -- ethernet3 = &fm1mac4; -- ethernet4 = &fm1mac5; -- ethernet5 = &fm1mac6; -- ethernet6 = &fm1mac9; -+ crypto = &crypto; - }; - - cpus { -@@ -70,6 +64,7 @@ - reg = <0x0>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; -+ cpu-idle-states = <&CPU_PH20>; - }; - - cpu1: cpu@1 { -@@ -78,6 +73,7 @@ - reg = <0x1>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; -+ cpu-idle-states = <&CPU_PH20>; - }; - - cpu2: cpu@2 { -@@ -86,6 +82,7 @@ - reg = <0x2>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; -+ cpu-idle-states = <&CPU_PH20>; - }; - - cpu3: cpu@3 { -@@ -94,6 +91,7 @@ - reg = <0x3>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; -+ cpu-idle-states = <&CPU_PH20>; - }; - - l2: l2-cache { -@@ -101,6 +99,19 @@ - }; - }; - -+ idle-states { -+ entry-method = "arm,psci"; -+ -+ CPU_PH20: cpu-ph20 { -+ compatible = "arm,idle-state"; -+ idle-state-name = "PH20"; -+ arm,psci-suspend-param = <0x00010000>; -+ entry-latency-us = <1000>; -+ exit-latency-us = <1000>; -+ min-residency-us = <3000>; -+ }; -+ }; -+ - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0 0x80000000>; -@@ -193,6 +204,49 @@ - bus-width = <4>; - }; - -+ crypto: crypto@1700000 { -+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", -+ "fsl,sec-v4.0"; -+ fsl,sec-era = <8>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x00 0x1700000 0x100000>; -+ reg = <0x00 0x1700000 0x0 0x100000>; -+ interrupts = <0 75 0x4>; -+ -+ sec_jr0: jr@10000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x10000 0x10000>; -+ interrupts = <0 71 0x4>; -+ }; -+ -+ sec_jr1: jr@20000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x20000 0x10000>; -+ interrupts = <0 72 0x4>; -+ }; -+ -+ sec_jr2: jr@30000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x30000 0x10000>; -+ interrupts = <0 73 0x4>; -+ }; -+ -+ sec_jr3: jr@40000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x40000 0x10000>; -+ interrupts = <0 74 0x4>; -+ }; -+ }; -+ - qman: qman@1880000 { - compatible = "fsl,qman"; - reg = <0x00 0x1880000 0x0 0x10000>; -@@ -490,6 +544,19 @@ - fsl,qman-channel-id = <0x800>; - }; - -+ fman0_10g_rx1: port@91000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-10g-rx"; -+ reg = <0x91000 0x1000>; -+ }; -+ -+ fman0_10g_tx1: port@b1000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-10g-tx"; -+ reg = <0xb1000 0x1000>; -+ fsl,qman-channel-id = <0x801>; -+ }; -+ - fm1mac9: ethernet@f0000 { - cell-index = <0>; - compatible = "fsl,fman-memac"; -@@ -497,6 +564,13 @@ - fsl,port-handles = <&fman0_10g_rx0 &fman0_10g_tx0>; - }; - -+ fm1mac10: ethernet@f2000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xf2000 0x1000>; -+ fsl,port-handles = <&fman0_10g_rx1 &fman0_10g_tx1>; -+ }; -+ - mdio@f1000 { - #address-cells = <1>; - #size-cells = <0>; -@@ -504,6 +578,13 @@ - reg = <0xf1000 0x1000>; - }; - -+ mdio@f3000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0xf3000 0x1000>; -+ }; -+ - ptp_timer0: rtc@fe000 { - compatible = "fsl,fman-rtc"; - reg = <0xfe000 0x1000>; -@@ -657,7 +738,7 @@ - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2950000 0x0 0x1000>; - interrupts = <0 48 0x4>; -- clocks = <&clockgen 0 0>; -+ clocks = <&clockgen 4 0>; - clock-names = "ipg"; - status = "disabled"; - }; -@@ -712,7 +793,7 @@ - reg = <0x0 0x29d0000 0x0 0x10000>; - interrupts = <0 86 0x4>; - big-endian; -- rcpm-wakeup = <&rcpm 0x0 0x20000000>; -+ rcpm-wakeup = <&rcpm 0x00020000 0x0>; - status = "okay"; - }; - -@@ -789,34 +870,34 @@ - big-endian; - }; - -- msi1: msi-controller@1580000 { -- compatible = "fsl,1s1046a-msi"; -- reg = <0x0 0x1580000 0x0 0x10000>; -+ msi: msi-controller@1580000 { -+ compatible = "fsl,ls1046a-msi"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; - msi-controller; -- interrupts = <0 116 0x4>, -- <0 111 0x4>, -- <0 112 0x4>, -- <0 113 0x4>; -- }; - -- msi2: msi-controller@1590000 { -- compatible = "fsl,1s1046a-msi"; -- reg = <0x0 0x1590000 0x0 0x10000>; -- msi-controller; -- interrupts = <0 126 0x4>, -- <0 121 0x4>, -- <0 122 0x4>, -- <0 123 0x4>; -- }; -- -- msi3: msi-controller@15a0000 { -- compatible = "fsl,1s1046a-msi"; -- reg = <0x0 0x15a0000 0x0 0x10000>; -- msi-controller; -- interrupts = <0 160 0x4>, -- <0 155 0x4>, -- <0 156 0x4>, -- <0 157 0x4>; -+ msi-bank@1580000 { -+ reg = <0x0 0x1580000 0x0 0x10000>; -+ interrupts = <0 116 0x4>, -+ <0 111 0x4>, -+ <0 112 0x4>, -+ <0 113 0x4>; -+ }; -+ msi-bank@1590000 { -+ reg = <0x0 0x1590000 0x0 0x10000>; -+ interrupts = <0 126 0x4>, -+ <0 121 0x4>, -+ <0 122 0x4>, -+ <0 123 0x4>; -+ }; -+ msi-bank@15a0000 { -+ reg = <0x0 0x15a0000 0x0 0x10000>; -+ interrupts = <0 160 0x4>, -+ <0 155 0x4>, -+ <0 156 0x4>, -+ <0 157 0x4>; -+ }; - }; - - pcie@3400000 { -@@ -826,15 +907,16 @@ - reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ - <0 117 0x4>; /* PME interrupt */ -- interrupt-names = "intr", "pme"; -+ interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -+ dma-coherent; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi1>; -+ msi-parent = <&msi>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, -@@ -850,15 +932,16 @@ - reg-names = "regs", "config"; - interrupts = <0 128 0x4>, - <0 127 0x4>; -- interrupt-names = "intr", "pme"; -+ interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -+ dma-coherent; - num-lanes = <2>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi2>; -+ msi-parent = <&msi>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, -@@ -874,15 +957,16 @@ - reg-names = "regs", "config"; - interrupts = <0 162 0x4>, - <0 161 0x4>; -- interrupt-names = "intr", "pme"; -+ interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -+ dma-coherent; - num-lanes = <2>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi3>; -+ msi-parent = <&msi>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, -@@ -894,14 +978,6 @@ - - fsl,dpaa { - compatible = "fsl,ls1046a-dpaa", "simple-bus", "fsl,dpaa"; -- ethernet@0 { -- compatible = "fsl,dpa-ethernet"; -- fsl,fman-mac = <&fm1mac1>; -- }; -- ethernet@1 { -- compatible = "fsl,dpa-ethernet"; -- fsl,fman-mac = <&fm1mac2>; -- }; - ethernet@2 { - compatible = "fsl,dpa-ethernet"; - fsl,fman-mac = <&fm1mac3>; -@@ -922,6 +998,10 @@ - compatible = "fsl,dpa-ethernet"; - fsl,fman-mac = <&fm1mac9>; - }; -+ ethernet@9 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&fm1mac10>; -+ }; - }; - - qportals: qman-portals@500000000 { diff --git a/target/linux/layerscape/patches-4.4/3133-ls1046ardb-add-ITS-file.patch b/target/linux/layerscape/patches-4.4/3133-ls1046ardb-add-ITS-file.patch deleted file mode 100644 index 7461b928d5..0000000000 --- a/target/linux/layerscape/patches-4.4/3133-ls1046ardb-add-ITS-file.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 1a831d848c88f1bb9e599abc641a201be6b03ef7 Mon Sep 17 00:00:00 2001 -From: Mingkai Hu -Date: Mon, 18 Apr 2016 15:38:24 +0800 -Subject: [PATCH 133/141] ls1046ardb: add ITS file - -Signed-off-by: Mingkai Hu ---- - kernel-ls1046a-rdb.its | 55 ++++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 55 insertions(+) - create mode 100644 kernel-ls1046a-rdb.its - ---- /dev/null -+++ b/kernel-ls1046a-rdb.its -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2016, Freescale Semiconductor -+ * -+ * Mingkai Hu -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+ -+/ { -+ description = "Image file for the LS1046A Linux Kernel"; -+ #address-cells = <1>; -+ -+ images { -+ kernel@1 { -+ description = "ARM64 Linux kernel"; -+ data = /incbin/("./arch/arm64/boot/Image.gz"); -+ type = "kernel"; -+ arch = "arm64"; -+ os = "linux"; -+ compression = "gzip"; -+ load = <0x80080000>; -+ entry = <0x80080000>; -+ }; -+ fdt@1 { -+ description = "Flattened Device Tree blob"; -+ data = /incbin/("./arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb"); -+ type = "flat_dt"; -+ arch = "arm64"; -+ compression = "none"; -+ load = <0x90000000>; -+ }; -+ ramdisk@1 { -+ description = "LS1046 Ramdisk"; -+ data = /incbin/("./fsl-image-core-ls1046ardb-be.ext2.gz"); -+ type = "ramdisk"; -+ arch = "arm64"; -+ os = "linux"; -+ compression = "gzip"; -+ }; -+ }; -+ -+ configurations { -+ default = "config@1"; -+ config@1 { -+ description = "Boot Linux kernel"; -+ kernel = "kernel@1"; -+ fdt = "fdt@1"; -+ ramdisk = "ramdisk@1"; -+ }; -+ }; -+}; diff --git a/target/linux/layerscape/patches-4.4/3135-arm64-Add-DTS-support-for-FSL-s-LS1088ARDB.patch b/target/linux/layerscape/patches-4.4/3135-arm64-Add-DTS-support-for-FSL-s-LS1088ARDB.patch deleted file mode 100644 index c8aaeee2c8..0000000000 --- a/target/linux/layerscape/patches-4.4/3135-arm64-Add-DTS-support-for-FSL-s-LS1088ARDB.patch +++ /dev/null @@ -1,790 +0,0 @@ -From cbacf87fa6fb262c98033405f15697798c3a9c5d Mon Sep 17 00:00:00 2001 -From: Zhao Qiang -Date: Sun, 9 Oct 2016 14:31:50 +0800 -Subject: [PATCH 135/141] arm64: Add DTS support for FSL's LS1088ARDB - -Signed-off-by: Zhao Qiang ---- - arch/arm64/boot/dts/freescale/Makefile | 1 + - arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 203 ++++++++ - arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 557 +++++++++++++++++++++ - 3 files changed, 761 insertions(+) - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi - ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1 - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb - - always := $(dtb-y) - subdir-y := $(dts-dirs) ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts -@@ -0,0 +1,203 @@ -+/* -+ * Device Tree file for Freescale LS1088a RDB board -+ * -+ * Copyright (C) 2015, Freescale Semiconductor -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+ -+#include "fsl-ls1088a.dtsi" -+ -+/ { -+ model = "Freescale Layerscape 1088a RDB Board"; -+ compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; -+}; -+ -+&esdhc { -+ status = "okay"; -+}; -+ -+&ifc { -+ status = "disabled"; -+}; -+ -+&ftm0 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ pca9547@77 { -+ compatible = "philips,pca9547"; -+ reg = <0x77>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x2>; -+ -+ ina220@40 { -+ compatible = "ti,ina220"; -+ reg = <0x40>; -+ shunt-resistor = <1000>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ -+ rtc@51 { -+ compatible = "nxp,pcf2129"; -+ reg = <0x51>; -+ /* IRQ10_B */ -+ interrupts = <0 150 0x4>; -+ }; -+ -+ adt7461a@4c { -+ compatible = "adt7461a"; -+ reg = <0x4c>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "disabled"; -+}; -+ -+&i2c2 { -+ status = "disabled"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&dspi { -+ status = "disabled"; -+}; -+ -+&qspi { -+ status = "okay"; -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+ -+ qflash1: s25fs512s@1 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <1>; -+ }; -+}; -+ -+&sata0 { -+ status = "okay"; -+}; -+ -+&usb0 { -+ status = "okay"; -+}; -+ -+&usb1 { -+ status = "okay"; -+}; -+ -+&serial0 { -+ status = "okay"; -+}; -+ -+&serial1 { -+ status = "okay"; -+}; -+ -+&emdio1 { -+ /* Freescale F104 PHY1 */ -+ mdio1_phy1: emdio1_phy@1 { -+ reg = <0x1c>; -+ phy-connection-type = "qsgmii"; -+ }; -+ mdio1_phy2: emdio1_phy@2 { -+ reg = <0x1d>; -+ phy-connection-type = "qsgmii"; -+ }; -+ mdio1_phy3: emdio1_phy@3 { -+ reg = <0x1e>; -+ phy-connection-type = "qsgmii"; -+ }; -+ mdio1_phy4: emdio1_phy@4 { -+ reg = <0x1f>; -+ phy-connection-type = "qsgmii"; -+ }; -+ /* F104 PHY2 */ -+ mdio1_phy5: emdio1_phy@5 { -+ reg = <0x0c>; -+ phy-connection-type = "qsgmii"; -+ }; -+ mdio1_phy6: emdio1_phy@6 { -+ reg = <0x0d>; -+ phy-connection-type = "qsgmii"; -+ }; -+ mdio1_phy7: emdio1_phy@7 { -+ reg = <0x0e>; -+ phy-connection-type = "qsgmii"; -+ }; -+ mdio1_phy8: emdio1_phy@8 { -+ reg = <0x0f>; -+ phy-connection-type = "qsgmii"; -+ }; -+}; -+ -+&emdio2 { -+ /* Aquantia AQR105 10G PHY */ -+ mdio2_phy1: emdio2_phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reg = <0x0>; -+ phy-connection-type = "xfi"; -+ }; -+}; -+ -+/* DPMAC connections to external PHYs -+ * based on LS1088A RM RevC - $24.1.2 SerDes Options -+ */ -+/* DPMAC1 is 10G SFP+, fixed link */ -+&dpmac2 { -+ phy-handle = <&mdio2_phy1>; -+}; -+&dpmac3 { -+ phy-handle = <&mdio1_phy5>; -+}; -+&dpmac4 { -+ phy-handle = <&mdio1_phy6>; -+}; -+&dpmac5 { -+ phy-handle = <&mdio1_phy7>; -+}; -+&dpmac6 { -+ phy-handle = <&mdio1_phy8>; -+}; -+&dpmac7 { -+ phy-handle = <&mdio1_phy1>; -+}; -+&dpmac8 { -+ phy-handle = <&mdio1_phy2>; -+}; -+&dpmac9 { -+ phy-handle = <&mdio1_phy3>; -+}; -+&dpmac10 { -+ phy-handle = <&mdio1_phy4>; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi -@@ -0,0 +1,557 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1088A family SoC. -+ * -+ * Copyright (C) 2015, Freescale Semiconductor -+ * -+ */ -+ -+/memreserve/ 0x80000000 0x00010000; -+ -+/ { -+ compatible = "fsl,ls1088a"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ /* We have 2 clusters having 4 Cortex-A57 cores each */ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0 0x0>; -+ clocks = <&clockgen 1 0>; -+ }; -+ -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0 0x1>; -+ clocks = <&clockgen 1 0>; -+ }; -+ -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0 0x2>; -+ clocks = <&clockgen 1 0>; -+ }; -+ -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0 0x3>; -+ clocks = <&clockgen 1 0>; -+ }; -+ -+ cpu4: cpu@100 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0 0x100>; -+ clocks = <&clockgen 1 1>; -+ }; -+ -+ cpu5: cpu@101 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0 0x101>; -+ clocks = <&clockgen 1 1>; -+ }; -+ -+ cpu6: cpu@102 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0 0x102>; -+ clocks = <&clockgen 1 1>; -+ }; -+ -+ cpu7: cpu@103 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0 0x103>; -+ clocks = <&clockgen 1 1>; -+ }; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ -+ }; -+ -+ gic: interrupt-controller@6000000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ -+ <0x0 0x0c0c0000 0 0x2000>, /* GICC */ -+ <0x0 0x0c0d0000 0 0x1000>, /* GICH */ -+ <0x0 0x0c0e0000 0 0x20000>; /* GICV */ -+ #interrupt-cells = <3>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ interrupt-controller; -+ interrupts = <1 9 0x4>; -+ -+ its: gic-its@6020000 { -+ compatible = "arm,gic-v3-its"; -+ msi-controller; -+ reg = <0x0 0x6020000 0 0x20000>; -+ }; -+ }; -+ -+ sysclk: sysclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "sysclk"; -+ }; -+ -+ clockgen: clocking@1300000 { -+ compatible = "fsl,ls2080a-clockgen", "fsl,ls1088a-clockgen"; -+ reg = <0 0x1300000 0 0xa0000>; -+ #clock-cells = <2>; -+ clocks = <&sysclk>; -+ }; -+ -+ serial0: serial@21c0500 { -+ device_type = "serial"; -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21c0500 0x0 0x100>; -+ clocks = <&clockgen 4 3>; -+ interrupts = <0 32 0x4>; /* Level high type */ -+ }; -+ -+ serial1: serial@21c0600 { -+ device_type = "serial"; -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21c0600 0x0 0x100>; -+ clocks = <&clockgen 4 3>; -+ interrupts = <0 32 0x4>; /* Level high type */ -+ }; -+ -+ gpio0: gpio@2300000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2300000 0x0 0x10000>; -+ interrupts = <0 36 0x4>; /* Level high type */ -+ gpio-controller; -+ little-endian; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio1: gpio@2310000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2310000 0x0 0x10000>; -+ interrupts = <0 36 0x4>; /* Level high type */ -+ gpio-controller; -+ little-endian; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio2: gpio@2320000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2320000 0x0 0x10000>; -+ interrupts = <0 37 0x4>; /* Level high type */ -+ gpio-controller; -+ little-endian; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio3: gpio@2330000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2330000 0x0 0x10000>; -+ interrupts = <0 37 0x4>; /* Level high type */ -+ gpio-controller; -+ little-endian; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ /* TODO: WRIOP (CCSR?) */ -+ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */ -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8B96000 0x0 0x1000>; -+ device_type = "mdio"; -+ little-endian; /* force the driver in LE mode */ -+ -+ /* Not necessary on the QDS, but needed on the RDB */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */ -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8B97000 0x0 0x1000>; -+ device_type = "mdio"; -+ little-endian; /* force the driver in LE mode */ -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ ifc: ifc@2240000 { -+ compatible = "fsl,ifc", "simple-bus"; -+ reg = <0x0 0x2240000 0x0 0x20000>; -+ interrupts = <0 21 0x4>; /* Level high type */ -+ little-endian; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ -+ ranges = <0 0 0x5 0x80000000 0x08000000 -+ 2 0 0x5 0x30000000 0x00010000 -+ 3 0 0x5 0x20000000 0x00010000>; -+ }; -+ -+ esdhc: esdhc@2140000 { -+ compatible = "fsl,ls2080a-esdhc", "fsl,ls1088a-esdhc", "fsl,esdhc"; -+ reg = <0x0 0x2140000 0x0 0x10000>; -+ interrupts = <0 28 0x4>; /* Level high type */ -+ clock-frequency = <0>; -+ voltage-ranges = <1800 1800 3300 3300>; -+ sdhci,auto-cmd12; -+ little-endian; -+ bus-width = <4>; -+ }; -+ -+ ftm0: ftm0@2800000 { -+ compatible = "fsl,ftm-alarm"; -+ reg = <0x0 0x2800000 0x0 0x10000>; -+ interrupts = <0 44 4>; -+ }; -+ -+ reset: reset@1E60000 { -+ compatible = "fsl,ls-reset"; -+ reg = <0x0 0x1E60000 0x0 0x10000>; -+ }; -+ -+ dspi: dspi@2100000 { -+ compatible = "fsl,ls2085a-dspi", "fsl,ls1088a-dspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2100000 0x0 0x10000>; -+ interrupts = <0 26 0x4>; /* Level high type */ -+ clocks = <&clockgen 4 3>; -+ clock-names = "dspi"; -+ spi-num-chipselects = <5>; -+ bus-num = <0>; -+ }; -+ -+ i2c0: i2c@2000000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2000000 0x0 0x10000>; -+ interrupts = <0 34 0x4>; /* Level high type */ -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 3>; -+ }; -+ -+ i2c1: i2c@2010000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2010000 0x0 0x10000>; -+ interrupts = <0 34 0x4>; /* Level high type */ -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 3>; -+ }; -+ -+ i2c2: i2c@2020000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2020000 0x0 0x10000>; -+ interrupts = <0 35 0x4>; /* Level high type */ -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 3>; -+ }; -+ -+ i2c3: i2c@2030000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2030000 0x0 0x10000>; -+ interrupts = <0 35 0x4>; /* Level high type */ -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 3>; -+ }; -+ -+ qspi: quadspi@20c0000 { -+ compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20c0000 0x0 0x10000>, -+ <0x0 0x20000000 0x0 0x10000000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ interrupts = <0 25 0x4>; /* Level high type */ -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "qspi_en", "qspi"; -+ }; -+ -+ pcie@3400000 { -+ compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ -+ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 108 0x4>; /* aer interrupt */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, -+ <0000 0 0 2 &gic 0 0 0 110 4>, -+ <0000 0 0 3 &gic 0 0 0 111 4>, -+ <0000 0 0 4 &gic 0 0 0 112 4>; -+ }; -+ pcie@3500000 { -+ compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ -+ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 113 0x4>; /* aer interrupt */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, -+ <0000 0 0 2 &gic 0 0 0 115 4>, -+ <0000 0 0 3 &gic 0 0 0 116 4>, -+ <0000 0 0 4 &gic 0 0 0 117 4>; -+ }; -+ -+ pcie@3600000 { -+ compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ -+ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 118 0x4>; /* aer interrupt */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-lanes = <8>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, -+ <0000 0 0 2 &gic 0 0 0 120 4>, -+ <0000 0 0 3 &gic 0 0 0 121 4>, -+ <0000 0 0 4 &gic 0 0 0 122 4>; -+ }; -+ -+ sata0: sata@3200000 { -+ compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci"; -+ reg = <0x0 0x3200000 0x0 0x10000>; -+ interrupts = <0 133 0x4>; /* Level high type */ -+ clocks = <&clockgen 4 3>; -+ }; -+ -+ usb0: usb3@3100000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3100000 0x0 0x10000>; -+ interrupts = <0 80 0x4>; /* Level high type */ -+ dr_mode = "host"; -+ configure-gfladj; -+ snps,dis_rxdet_inp3_quirk; -+ }; -+ -+ usb1: usb3@3110000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3110000 0x0 0x10000>; -+ interrupts = <0 81 0x4>; /* Level high type */ -+ dr_mode = "host"; -+ configure-gfladj; -+ snps,dis_rxdet_inp3_quirk; -+ }; -+ -+ smmu: iommu@5000000 { -+ compatible = "arm,mmu-500"; -+ reg = <0 0x5000000 0 0x800000>; -+ #global-interrupts = <12>; -+ interrupts = <0 13 4>, /* global secure fault */ -+ <0 14 4>, /* combined secure interrupt */ -+ <0 15 4>, /* global non-secure fault */ -+ <0 16 4>, /* combined non-secure interrupt */ -+ /* performance counter interrupts 0-7 */ -+ <0 211 4>, -+ <0 212 4>, -+ <0 213 4>, -+ <0 214 4>, -+ <0 215 4>, -+ <0 216 4>, -+ <0 217 4>, -+ <0 218 4>, -+ /* per context interrupt, 64 interrupts */ -+ <0 146 4>, -+ <0 147 4>, -+ <0 148 4>, -+ <0 149 4>, -+ <0 150 4>, -+ <0 151 4>, -+ <0 152 4>, -+ <0 153 4>, -+ <0 154 4>, -+ <0 155 4>, -+ <0 156 4>, -+ <0 157 4>, -+ <0 158 4>, -+ <0 159 4>, -+ <0 160 4>, -+ <0 161 4>, -+ <0 162 4>, -+ <0 163 4>, -+ <0 164 4>, -+ <0 165 4>, -+ <0 166 4>, -+ <0 167 4>, -+ <0 168 4>, -+ <0 169 4>, -+ <0 170 4>, -+ <0 171 4>, -+ <0 172 4>, -+ <0 173 4>, -+ <0 174 4>, -+ <0 175 4>, -+ <0 176 4>, -+ <0 177 4>, -+ <0 178 4>, -+ <0 179 4>, -+ <0 180 4>, -+ <0 181 4>, -+ <0 182 4>, -+ <0 183 4>, -+ <0 184 4>, -+ <0 185 4>, -+ <0 186 4>, -+ <0 187 4>, -+ <0 188 4>, -+ <0 189 4>, -+ <0 190 4>, -+ <0 191 4>, -+ <0 192 4>, -+ <0 193 4>, -+ <0 194 4>, -+ <0 195 4>, -+ <0 196 4>, -+ <0 197 4>, -+ <0 198 4>, -+ <0 199 4>, -+ <0 200 4>, -+ <0 201 4>, -+ <0 202 4>, -+ <0 203 4>, -+ <0 204 4>, -+ <0 205 4>, -+ <0 206 4>, -+ <0 207 4>, -+ <0 208 4>, -+ <0 209 4>; -+ mmu-masters = <&fsl_mc 0x300 0>; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = <1 13 0x1>,/*Phy Secure PPI, edge triggered*/ -+ <1 14 0x1>, /*Phy Non-Secure PPI, edge triggered*/ -+ <1 11 0x1>, /*Virtual PPI, edge triggered */ -+ <1 10 0x1>; /*Hypervisor PPI, edge triggered */ -+ }; -+ -+ fsl_mc: fsl-mc@80c000000 { -+ compatible = "fsl,qoriq-mc"; -+ #stream-id-cells = <2>; -+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ -+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ -+ msi-parent = <&its>; -+ #address-cells = <3>; -+ #size-cells = <1>; -+ -+ /* -+ * Region type 0x0 - MC portals -+ * Region type 0x1 - QBMAN portals -+ */ -+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 -+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; -+ -+ dpmacs { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dpmac1: dpmac@1 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <1>; -+ }; -+ dpmac2: dpmac@2 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <2>; -+ }; -+ dpmac3: dpmac@3 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <3>; -+ }; -+ dpmac4: dpmac@4 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <4>; -+ }; -+ dpmac5: dpmac@5 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <5>; -+ }; -+ dpmac6: dpmac@6 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <6>; -+ }; -+ dpmac7: dpmac@7 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <7>; -+ }; -+ dpmac8: dpmac@8 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <8>; -+ }; -+ dpmac9: dpmac@9 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <9>; -+ }; -+ dpmac10: dpmac@10 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xa>; -+ }; -+ }; -+ }; -+ -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00000000 0x80000000 0 0x80000000>; -+ /* DRAM space 1 - 2 GB DRAM */ -+ }; -+}; diff --git a/target/linux/layerscape/patches-4.4/3139-ls1088ardb-add-ITS-file.patch b/target/linux/layerscape/patches-4.4/3139-ls1088ardb-add-ITS-file.patch deleted file mode 100644 index 8b66c3e57a..0000000000 --- a/target/linux/layerscape/patches-4.4/3139-ls1088ardb-add-ITS-file.patch +++ /dev/null @@ -1,69 +0,0 @@ -From caaab508dc2ba749d8394b5934353b1c47f37d75 Mon Sep 17 00:00:00 2001 -From: Zhao Qiang -Date: Sun, 9 Oct 2016 15:14:16 +0800 -Subject: [PATCH 139/141] ls1088ardb: add ITS file - -Signed-off-by: Zhao Qiang ---- - kernel-ls1088a-rdb.its | 55 ++++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 55 insertions(+) - create mode 100644 kernel-ls1088a-rdb.its - ---- /dev/null -+++ b/kernel-ls1088a-rdb.its -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2015, Freescale Semiconductor -+ * -+ * Raghav Dogra -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+ -+/ { -+ description = "Simulator Image file for the LS1088A Linux Kernel"; -+ #address-cells = <1>; -+ -+ images { -+ kernel@1 { -+ description = "ARM64 Linux kernel"; -+ data = /incbin/("./arch/arm64/boot/Image.gz"); -+ type = "kernel"; -+ arch = "arm64"; -+ os = "linux"; -+ compression = "gzip"; -+ load = <0x80080000>; -+ entry = <0x80080000>; -+ }; -+ fdt@1 { -+ description = "Flattened Device Tree blob"; -+ data = /incbin/("./arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dtb"); -+ type = "flat_dt"; -+ arch = "arm64"; -+ compression = "none"; -+ load = <0x90000000>; -+ }; -+ ramdisk@1 { -+ description = "LS2 Ramdisk"; -+ data = /incbin/("./fsl-image-core-ls1088ardb-be.ext2.gz"); -+ type = "ramdisk"; -+ arch = "arm64"; -+ os = "linux"; -+ compression = "none"; -+ }; -+ }; -+ -+ configurations { -+ default = "config@1"; -+ config@1 { -+ description = "Boot Linux kernel"; -+ kernel = "kernel@1"; -+ fdt = "fdt@1"; -+ ramdisk = "ramdisk@1"; -+ }; -+ }; -+}; diff --git a/target/linux/layerscape/patches-4.4/3141-caam-add-caam-node-for-ls1088a.patch b/target/linux/layerscape/patches-4.4/3141-caam-add-caam-node-for-ls1088a.patch deleted file mode 100644 index 386a32102a..0000000000 --- a/target/linux/layerscape/patches-4.4/3141-caam-add-caam-node-for-ls1088a.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 89b3b66aa955fed15585a4ba7120cf63f9e92aba Mon Sep 17 00:00:00 2001 -From: Zhao Qiang -Date: Thu, 13 Oct 2016 10:19:08 +0800 -Subject: [PATCH 141/141] caam: add caam node for ls1088a - -Signed-off-by: Zhao Qiang ---- - arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 43 ++++++++++++++++++++++++ - 1 file changed, 43 insertions(+) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi -@@ -485,6 +485,49 @@ - <1 10 0x1>; /*Hypervisor PPI, edge triggered */ - }; - -+ crypto: crypto@8000000 { -+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", -+ "fsl,sec-v4.0"; -+ fsl,sec-era = <8>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x00 0x8000000 0x100000>; -+ reg = <0x00 0x8000000 0x0 0x100000>; -+ interrupts = <0 139 0x4>; -+ -+ sec_jr0: jr@10000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x10000 0x10000>; -+ interrupts = <0 140 0x4>; -+ }; -+ -+ sec_jr1: jr@20000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x20000 0x10000>; -+ interrupts = <0 141 0x4>; -+ }; -+ -+ sec_jr2: jr@30000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x30000 0x10000>; -+ interrupts = <0 142 0x4>; -+ }; -+ -+ sec_jr3: jr@40000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x40000 0x10000>; -+ interrupts = <0 143 0x4>; -+ }; -+ }; -+ - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - #stream-id-cells = <2>; diff --git a/target/linux/layerscape/patches-4.4/3143-armv8-aarch32-Execute-32-bit-Linux-for-ls1046a.patch b/target/linux/layerscape/patches-4.4/3143-armv8-aarch32-Execute-32-bit-Linux-for-ls1046a.patch deleted file mode 100644 index 8754ea4fdb..0000000000 --- a/target/linux/layerscape/patches-4.4/3143-armv8-aarch32-Execute-32-bit-Linux-for-ls1046a.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 887fd872791ce6e60045f4c6a97926365c6c817c Mon Sep 17 00:00:00 2001 -From: Yutang Jiang -Date: Wed, 7 Dec 2016 00:47:35 +0800 -Subject: [PATCH] armv8: aarch32: Execute 32-bit Linux for ls1046a - -Signed-off-by: Yutang Jiang ---- - arch/arm/mach-imx/mach-layerscape.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/arch/arm/mach-imx/mach-layerscape.c -+++ b/arch/arm/mach-imx/mach-layerscape.c -@@ -12,11 +12,13 @@ - #include "common.h" - - static const char * const layerscape_dt_compat[] __initconst = { -- "fsl,ls1043a", - "fsl,ls1012a", -+ "fsl,ls1043a", -+ "fsl,ls1046a", - NULL, - }; - - DT_MACHINE_START(LAYERSCAPE, "Freescale LAYERSCAPE") -+ .smp = smp_ops(layerscape_smp_ops), - .dt_compat = layerscape_dt_compat, - MACHINE_END diff --git a/target/linux/layerscape/patches-4.4/3226-mtd-spi-nor-fsl-quadspi-Enable-fast-read-for-LS1088A.patch b/target/linux/layerscape/patches-4.4/3226-mtd-spi-nor-fsl-quadspi-Enable-fast-read-for-LS1088A.patch deleted file mode 100644 index fa2a1d3089..0000000000 --- a/target/linux/layerscape/patches-4.4/3226-mtd-spi-nor-fsl-quadspi-Enable-fast-read-for-LS1088A.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 72b250c04f543d4eeda06b32e699444b15cac5cc Mon Sep 17 00:00:00 2001 -From: "ying.zhang" -Date: Sat, 17 Dec 2016 00:39:28 +0800 -Subject: [PATCH 226/226] mtd:spi-nor:fsl-quadspi:Enable fast-read for - LS1088ARDB - -Add fast-read mode for LS1088ARDB board. - -Signed-off-by: Yuan Yao -Integrated-by: Jiang Yutang ---- - arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 2 ++ - arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 1 + - 2 files changed, 3 insertions(+) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts -@@ -91,6 +91,7 @@ - compatible = "spansion,m25p80"; - #address-cells = <1>; - #size-cells = <1>; -+ m25p,fast-read; - spi-max-frequency = <20000000>; - reg = <0>; - }; -@@ -99,6 +100,7 @@ - compatible = "spansion,m25p80"; - #address-cells = <1>; - #size-cells = <1>; -+ m25p,fast-read; - spi-max-frequency = <20000000>; - reg = <1>; - }; ---- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi -@@ -294,6 +294,7 @@ - interrupts = <0 25 0x4>; /* Level high type */ - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "qspi_en", "qspi"; -+ fsl,qspi-has-second-chip; - }; - - pcie@3400000 { diff --git a/target/linux/layerscape/patches-4.4/3227-ls2088a-dts-add-ls2088a-dts.patch b/target/linux/layerscape/patches-4.4/3227-ls2088a-dts-add-ls2088a-dts.patch deleted file mode 100644 index b3b6991dd7..0000000000 --- a/target/linux/layerscape/patches-4.4/3227-ls2088a-dts-add-ls2088a-dts.patch +++ /dev/null @@ -1,1338 +0,0 @@ -From 45ba5bb2bdc9462fe5998aeb75e2c7e33b56c9fb Mon Sep 17 00:00:00 2001 -From: Zhao Qiang -Date: Mon, 7 Nov 2016 10:23:52 +0800 -Subject: [PATCH 227/238] ls2088a/dts: add ls2088a dts - -Signed-off-by: Zhao Qiang ---- - arch/arm64/boot/dts/freescale/Makefile | 2 + - arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 241 ++++++ - arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 207 +++++ - arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 854 +++++++++++++++++++++ - 4 files changed, 1304 insertions(+) - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi - ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -6,6 +6,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1 - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb - - always := $(dtb-y) - subdir-y := $(dts-dirs) ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts -@@ -0,0 +1,241 @@ -+/* -+ * Device Tree file for Freescale LS2080a QDS Board -+ * -+ * Copyright (C) 2016, Freescale Semiconductor -+ * -+ * Abhimanyu Saini -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+ -+#include "fsl-ls2088a.dtsi" -+ -+/ { -+ model = "Freescale Layerscape 2088a QDS Board"; -+ compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; -+}; -+ -+&esdhc { -+ status = "okay"; -+}; -+ -+&ifc { -+ status = "okay"; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x5 0x80000000 0x08000000 -+ 0x2 0x0 0x5 0x30000000 0x00010000 -+ 0x3 0x0 0x5 0x20000000 0x00010000>; -+ -+ nor@0,0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "cfi-flash"; -+ reg = <0x0 0x0 0x8000000>; -+ bank-width = <2>; -+ device-width = <1>; -+ }; -+ -+ nand@2,0 { -+ compatible = "fsl,ifc-nand"; -+ reg = <0x2 0x0 0x10000>; -+ }; -+ -+ cpld@3,0 { -+ reg = <0x3 0x0 0x10000>; -+ compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis", -+ "fsl,fpga-qixis"; -+ }; -+}; -+ -+&ftm0 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ pca9547@77 { -+ compatible = "nxp,pca9547"; -+ reg = <0x77>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x00>; -+ rtc@68 { -+ compatible = "dallas,ds3232"; -+ reg = <0x68>; -+ }; -+ }; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x02>; -+ -+ ina220@40 { -+ compatible = "ti,ina220"; -+ reg = <0x40>; -+ shunt-resistor = <500>; -+ }; -+ ina220@41 { -+ compatible = "ti,ina220"; -+ reg = <0x41>; -+ shunt-resistor = <1000>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ -+ adt7481@4c { -+ compatible = "adi,adt7461"; -+ reg = <0x4c>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "disabled"; -+}; -+ -+&i2c2 { -+ status = "disabled"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&dspi { -+ status = "okay"; -+ dflash0: n25q128a { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <3000000>; -+ reg = <0>; -+ }; -+ dflash1: sst25wf040b { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <3000000>; -+ reg = <1>; -+ }; -+ dflash2: en25s64 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <3000000>; -+ reg = <2>; -+ }; -+}; -+ -+&qspi { -+ status = "okay"; -+ qflash0: s25fs256s1@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <20000000>; -+ m25p,fast-read; -+ reg = <0>; -+ }; -+ -+ qflash2: s25fs256s1@2 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <20000000>; -+ m25p,fast-read; -+ reg = <2>; -+ }; -+}; -+ -+&sata0 { -+ status = "okay"; -+}; -+ -+&sata1 { -+ status = "okay"; -+}; -+ -+&usb0 { -+ status = "okay"; -+}; -+ -+&usb1 { -+ status = "okay"; -+}; -+ -+&ifc { -+ boardctrl: board-control@3,0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus"; -+ reg = <3 0 0x300>; /* TODO check address */ -+ ranges = <0 3 0 0x300>; -+ -+ mdio_mux_emi1 { -+ compatible = "mdio-mux-mmioreg", "mdio-mux"; -+ mdio-parent-bus = <&emdio1>; -+ reg = <0x54 1>; /* BRDCFG4 */ -+ mux-mask = <0xe0>; /* EMI1_MDIO */ -+ -+ #address-cells=<1>; -+ #size-cells = <0>; -+ -+ /* Child MDIO buses, one for each riser card: -+ reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. -+ -+ VSC8234 PHYs on the riser cards. -+ */ -+ -+ mdio_mux3: mdio@60 { -+ reg = <0x60>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mdio0_phy12: mdio_phy0@1c { -+ reg = <0x1c>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy13: mdio_phy1@1d { -+ reg = <0x1d>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy14: mdio_phy2@1e { -+ reg = <0x1e>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy15: mdio_phy3@1f { -+ reg = <0x1f>; -+ phy-connection-type = "sgmii"; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ -+&dpmac9 { -+ phy-handle = <&mdio0_phy12>; -+}; -+&dpmac10 { -+ phy-handle = <&mdio0_phy13>; -+}; -+&dpmac11 { -+ phy-handle = <&mdio0_phy14>; -+}; -+&dpmac12 { -+ phy-handle = <&mdio0_phy15>; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts -@@ -0,0 +1,207 @@ -+/* -+ * Device Tree file for Freescale LS2080a RDB board -+ * -+ * Copyright (C) 2015, Freescale Semiconductor -+ * -+ * Abhimanyu Saini -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+ -+#include "fsl-ls2088a.dtsi" -+ -+/ { -+ model = "Freescale Layerscape 2088a RDB Board"; -+ compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; -+}; -+ -+&esdhc { -+ status = "okay"; -+}; -+ -+&ifc { -+ status = "okay"; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x5 0x80000000 0x08000000 -+ 0x2 0x0 0x5 0x30000000 0x00010000 -+ 0x3 0x0 0x5 0x20000000 0x00010000>; -+ -+ nor@0,0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "cfi-flash"; -+ reg = <0x0 0x0 0x8000000>; -+ bank-width = <2>; -+ device-width = <1>; -+ }; -+ -+ nand@2,0 { -+ compatible = "fsl,ifc-nand"; -+ reg = <0x2 0x0 0x10000>; -+ }; -+ -+ cpld@3,0 { -+ reg = <0x3 0x0 0x10000>; -+ compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis", -+ "fsl,fpga-qixis"; -+ }; -+}; -+ -+&ftm0 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ pca9547@75 { -+ compatible = "nxp,pca9547"; -+ reg = <0x75>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ i2c-mux-never-disable; -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x01>; -+ rtc@68 { -+ compatible = "dallas,ds3232"; -+ reg = <0x68>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ -+ adt7481@4c { -+ compatible = "adi,adt7461"; -+ reg = <0x4c>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "disabled"; -+}; -+ -+&i2c2 { -+ status = "disabled"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&dspi { -+ status = "okay"; -+ dflash0: n25q512a { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <3000000>; -+ reg = <0>; -+ }; -+}; -+ -+&qspi { -+ status = "disabled"; -+}; -+ -+&sata0 { -+ status = "okay"; -+}; -+ -+&sata1 { -+ status = "okay"; -+}; -+ -+&usb0 { -+ status = "okay"; -+}; -+ -+&usb1 { -+ status = "okay"; -+}; -+ -+&emdio1 { -+ /* CS4340 PHYs */ -+ mdio1_phy1: emdio1_phy@1 { -+ reg = <0x10>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio1_phy2: emdio1_phy@2 { -+ reg = <0x11>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio1_phy3: emdio1_phy@3 { -+ reg = <0x12>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio1_phy4: emdio1_phy@4 { -+ reg = <0x13>; -+ phy-connection-type = "xfi"; -+ }; -+}; -+ -+&emdio2 { -+ /* AQR405 PHYs */ -+ mdio2_phy1: emdio2_phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 1 0x4>; /* Level high type */ -+ reg = <0x0>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio2_phy2: emdio2_phy@2 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 2 0x4>; /* Level high type */ -+ reg = <0x1>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio2_phy3: emdio2_phy@3 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 4 0x4>; /* Level high type */ -+ reg = <0x2>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio2_phy4: emdio2_phy@4 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 5 0x4>; /* Level high type */ -+ reg = <0x3>; -+ phy-connection-type = "xfi"; -+ }; -+}; -+ -+/* Update DPMAC connections to external PHYs, under the assumption of -+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board. -+ */ -+&dpmac1 { -+ phy-handle = <&mdio1_phy1>; -+}; -+&dpmac2 { -+ phy-handle = <&mdio1_phy2>; -+}; -+&dpmac3 { -+ phy-handle = <&mdio1_phy3>; -+}; -+&dpmac4 { -+ phy-handle = <&mdio1_phy4>; -+}; -+&dpmac5 { -+ phy-handle = <&mdio2_phy1>; -+}; -+&dpmac6 { -+ phy-handle = <&mdio2_phy2>; -+}; -+&dpmac7 { -+ phy-handle = <&mdio2_phy3>; -+}; -+&dpmac8 { -+ phy-handle = <&mdio2_phy4>; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi -@@ -0,0 +1,854 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-2088A family SoC. -+ * -+ * Copyright (C) 2016, Freescale Semiconductor -+ * -+ * Abhimanyu Saini -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include -+ -+/memreserve/ 0x80000000 0x00010000; -+ -+/ { -+ compatible = "fsl,ls2088a"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x0 0x0>; -+ clocks = <&clockgen 1 0>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_PW20>; -+ }; -+ -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x0 0x1>; -+ clocks = <&clockgen 1 0>; -+ cpu-idle-states = <&CPU_PW20>; -+ }; -+ -+ cpu2: cpu@100 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x0 0x100>; -+ clocks = <&clockgen 1 1>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_PW20>; -+ }; -+ -+ cpu3: cpu@101 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x0 0x101>; -+ clocks = <&clockgen 1 1>; -+ cpu-idle-states = <&CPU_PW20>; -+ }; -+ -+ cpu4: cpu@200 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x0 0x200>; -+ clocks = <&clockgen 1 2>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_PW20>; -+ }; -+ -+ cpu5: cpu@201 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x0 0x201>; -+ clocks = <&clockgen 1 2>; -+ cpu-idle-states = <&CPU_PW20>; -+ }; -+ -+ cpu6: cpu@300 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x0 0x300>; -+ clocks = <&clockgen 1 3>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_PW20>; -+ }; -+ -+ cpu7: cpu@301 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x0 0x301>; -+ clocks = <&clockgen 1 3>; -+ cpu-idle-states = <&CPU_PW20>; -+ }; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ -+ }; -+ -+ idle-states { -+ entry-method = "arm,psci"; -+ -+ CPU_PW20: cpu-pw20 { -+ compatible = "arm,idle-state"; -+ idle-state-name = "PW20"; -+ arm,psci-suspend-param = <0x00010000>; -+ entry-latency-us = <2000>; -+ exit-latency-us = <2000>; -+ min-residency-us = <6000>; -+ }; -+ }; -+ -+ gic: interrupt-controller@6000000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ -+ <0x0 0x0c0c0000 0 0x2000>, /* GICC */ -+ <0x0 0x0c0d0000 0 0x1000>, /* GICH */ -+ <0x0 0x0c0e0000 0 0x20000>; /* GICV */ -+ #interrupt-cells = <3>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ interrupt-controller; -+ interrupts = <1 9 0x4>; -+ -+ its: gic-its@6020000 { -+ compatible = "arm,gic-v3-its"; -+ msi-controller; -+ reg = <0x0 0x6020000 0 0x20000>; -+ }; -+ }; -+ -+ sysclk: sysclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "sysclk"; -+ }; -+ -+ clockgen: clocking@1300000 { -+ compatible = "fsl,ls2088a-clockgen"; -+ reg = <0 0x1300000 0 0xa0000>; -+ #clock-cells = <2>; -+ clocks = <&sysclk>; -+ }; -+ -+ tmu: tmu@1f80000 { -+ compatible = "fsl,qoriq-tmu", "fsl,ls2080a-tmu", "fsl,ls2088a-tmu"; -+ reg = <0x0 0x1f80000 0x0 0x10000>; -+ interrupts = <0 23 0x4>; -+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; -+ fsl,tmu-calibration = <0x00000000 0x00000026 -+ 0x00000001 0x0000002d -+ 0x00000002 0x00000032 -+ 0x00000003 0x00000039 -+ 0x00000004 0x0000003f -+ 0x00000005 0x00000046 -+ 0x00000006 0x0000004d -+ 0x00000007 0x00000054 -+ 0x00000008 0x0000005a -+ 0x00000009 0x00000061 -+ 0x0000000a 0x0000006a -+ 0x0000000b 0x00000071 -+ -+ 0x00010000 0x00000025 -+ 0x00010001 0x0000002c -+ 0x00010002 0x00000035 -+ 0x00010003 0x0000003d -+ 0x00010004 0x00000045 -+ 0x00010005 0x0000004e -+ 0x00010006 0x00000057 -+ 0x00010007 0x00000061 -+ 0x00010008 0x0000006b -+ 0x00010009 0x00000076 -+ -+ 0x00020000 0x00000029 -+ 0x00020001 0x00000033 -+ 0x00020002 0x0000003d -+ 0x00020003 0x00000049 -+ 0x00020004 0x00000056 -+ 0x00020005 0x00000061 -+ 0x00020006 0x0000006d -+ -+ 0x00030000 0x00000021 -+ 0x00030001 0x0000002a -+ 0x00030002 0x0000003c -+ 0x00030003 0x0000004e>; -+ little-endian; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <5000>; -+ -+ thermal-sensors = <&tmu 4>; -+ -+ trips { -+ cpu_alert: cpu-alert { -+ temperature = <75000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_crit: cpu-crit { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu0 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ map1 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu2 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ map2 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu4 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ map3 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu6 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ }; -+ -+ serial0: serial@21c0500 { -+ device_type = "serial"; -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21c0500 0x0 0x100>; -+ clocks = <&clockgen 4 3>; -+ interrupts = <0 32 0x4>; /* Level high type */ -+ }; -+ -+ serial1: serial@21c0600 { -+ device_type = "serial"; -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21c0600 0x0 0x100>; -+ clocks = <&clockgen 4 3>; -+ interrupts = <0 32 0x4>; /* Level high type */ -+ }; -+ cluster1_core0_watchdog: wdt@c000000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc000000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster1_core1_watchdog: wdt@c010000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc010000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster2_core0_watchdog: wdt@c100000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc100000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster2_core1_watchdog: wdt@c110000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc110000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster3_core0_watchdog: wdt@c200000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc200000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster3_core1_watchdog: wdt@c210000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc210000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster4_core0_watchdog: wdt@c300000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc300000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster4_core1_watchdog: wdt@c310000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc310000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ gpio0: gpio@2300000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2300000 0x0 0x10000>; -+ interrupts = <0 36 0x4>; /* Level high type */ -+ gpio-controller; -+ little-endian; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio1: gpio@2310000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2310000 0x0 0x10000>; -+ interrupts = <0 36 0x4>; /* Level high type */ -+ gpio-controller; -+ little-endian; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio2: gpio@2320000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2320000 0x0 0x10000>; -+ interrupts = <0 37 0x4>; /* Level high type */ -+ gpio-controller; -+ little-endian; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio3: gpio@2330000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2330000 0x0 0x10000>; -+ interrupts = <0 37 0x4>; /* Level high type */ -+ gpio-controller; -+ little-endian; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ /* TODO: WRIOP (CCSR?) */ -+ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */ -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8B96000 0x0 0x1000>; -+ device_type = "mdio"; /* TODO: is this necessary? */ -+ little-endian; /* force the driver in LE mode */ -+ -+ /* Not necessary on the QDS, but needed on the RDB */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */ -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8B97000 0x0 0x1000>; -+ device_type = "mdio"; /* TODO: is this necessary? */ -+ little-endian; /* force the driver in LE mode */ -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ ifc: ifc@2240000 { -+ compatible = "fsl,ifc", "simple-bus"; -+ reg = <0x0 0x2240000 0x0 0x20000>; -+ interrupts = <0 21 0x4>; /* Level high type */ -+ little-endian; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ -+ ranges = <0 0 0x5 0x80000000 0x08000000 -+ 2 0 0x5 0x30000000 0x00010000 -+ 3 0 0x5 0x20000000 0x00010000>; -+ }; -+ -+ esdhc: esdhc@2140000 { -+ compatible = "fsl,ls2088a-esdhc", "fsl,ls2080a-esdhc", -+ "fsl,esdhc"; -+ reg = <0x0 0x2140000 0x0 0x10000>; -+ interrupts = <0 28 0x4>; /* Level high type */ -+ clock-frequency = <0>; -+ voltage-ranges = <1800 1800 3300 3300>; -+ sdhci,auto-cmd12; -+ little-endian; -+ bus-width = <4>; -+ }; -+ -+ ftm0: ftm0@2800000 { -+ compatible = "fsl,ftm-alarm"; -+ reg = <0x0 0x2800000 0x0 0x10000>; -+ interrupts = <0 44 4>; -+ }; -+ -+ reset: reset@1E60000 { -+ compatible = "fsl,ls-reset"; -+ reg = <0x0 0x1E60000 0x0 0x10000>; -+ }; -+ -+ dspi: dspi@2100000 { -+ compatible = "fsl,ls2088a-dspi", "fsl,ls2085a-dspi", -+ "fsl,ls2080a-dspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2100000 0x0 0x10000>; -+ interrupts = <0 26 0x4>; /* Level high type */ -+ clocks = <&clockgen 4 3>; -+ clock-names = "dspi"; -+ spi-num-chipselects = <5>; -+ bus-num = <0>; -+ }; -+ -+ i2c0: i2c@2000000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2000000 0x0 0x10000>; -+ interrupts = <0 34 0x4>; /* Level high type */ -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 3>; -+ }; -+ -+ i2c1: i2c@2010000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2010000 0x0 0x10000>; -+ interrupts = <0 34 0x4>; /* Level high type */ -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 3>; -+ }; -+ -+ i2c2: i2c@2020000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2020000 0x0 0x10000>; -+ interrupts = <0 35 0x4>; /* Level high type */ -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 3>; -+ }; -+ -+ i2c3: i2c@2030000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2030000 0x0 0x10000>; -+ interrupts = <0 35 0x4>; /* Level high type */ -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 3>; -+ }; -+ -+ qspi: quadspi@20c0000 { -+ compatible = "fsl,ls2088a-qspi", "fsl,ls2080a-qspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20c0000 0x0 0x10000>, -+ <0x0 0x20000000 0x0 0x10000000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ interrupts = <0 25 0x4>; /* Level high type */ -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "qspi_en", "qspi"; -+ }; -+ -+ pcie1: pcie@3400000 { -+ compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie", -+ "fsl,ls2085a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ -+ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 108 0x4>; /* Level high type */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ fsl,lut_diff; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, -+ <0000 0 0 2 &gic 0 0 0 110 4>, -+ <0000 0 0 3 &gic 0 0 0 111 4>, -+ <0000 0 0 4 &gic 0 0 0 112 4>; -+ }; -+ -+ pcie2: pcie@3500000 { -+ compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie", -+ "fsl,ls2085a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ -+ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 113 0x4>; /* Level high type */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ fsl,lut_diff; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, -+ <0000 0 0 2 &gic 0 0 0 115 4>, -+ <0000 0 0 3 &gic 0 0 0 116 4>, -+ <0000 0 0 4 &gic 0 0 0 117 4>; -+ }; -+ -+ pcie3: pcie@3600000 { -+ compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie", -+ "fsl,ls2085a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ -+ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 118 0x4>; /* Level high type */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ fsl,lut_diff; -+ num-lanes = <8>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, -+ <0000 0 0 2 &gic 0 0 0 120 4>, -+ <0000 0 0 3 &gic 0 0 0 121 4>, -+ <0000 0 0 4 &gic 0 0 0 122 4>; -+ }; -+ -+ pcie4: pcie@3700000 { -+ compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie", -+ "fsl,ls2085a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ -+ 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 123 0x4>; /* Level high type */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ fsl,lut_diff; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, -+ <0000 0 0 2 &gic 0 0 0 125 4>, -+ <0000 0 0 3 &gic 0 0 0 126 4>, -+ <0000 0 0 4 &gic 0 0 0 127 4>; -+ }; -+ -+ sata0: sata@3200000 { -+ status = "disabled"; -+ compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci"; -+ reg = <0x0 0x3200000 0x0 0x10000>; -+ interrupts = <0 133 0x4>; /* Level high type */ -+ clocks = <&clockgen 4 3>; -+ }; -+ -+ sata1: sata@3210000 { -+ status = "disabled"; -+ compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci"; -+ reg = <0x0 0x3210000 0x0 0x10000>; -+ interrupts = <0 136 0x4>; /* Level high type */ -+ clocks = <&clockgen 4 3>; -+ }; -+ -+ usb0: usb3@3100000 { -+ status = "disabled"; -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3100000 0x0 0x10000>; -+ interrupts = <0 80 0x4>; /* Level high type */ -+ dr_mode = "host"; -+ configure-gfladj; -+ snps,dis_rxdet_inp3_quirk; -+ }; -+ -+ usb1: usb3@3110000 { -+ status = "disabled"; -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3110000 0x0 0x10000>; -+ interrupts = <0 81 0x4>; /* Level high type */ -+ dr_mode = "host"; -+ configure-gfladj; -+ snps,dis_rxdet_inp3_quirk; -+ }; -+ -+ smmu: iommu@5000000 { -+ compatible = "arm,mmu-500"; -+ reg = <0 0x5000000 0 0x800000>; -+ #global-interrupts = <12>; -+ interrupts = <0 13 4>, /* global secure fault */ -+ <0 14 4>, /* combined secure interrupt */ -+ <0 15 4>, /* global non-secure fault */ -+ <0 16 4>, /* combined non-secure interrupt */ -+ /* performance counter interrupts 0-7 */ -+ <0 211 4>, -+ <0 212 4>, -+ <0 213 4>, -+ <0 214 4>, -+ <0 215 4>, -+ <0 216 4>, -+ <0 217 4>, -+ <0 218 4>, -+ /* per context interrupt, 64 interrupts */ -+ <0 146 4>, -+ <0 147 4>, -+ <0 148 4>, -+ <0 149 4>, -+ <0 150 4>, -+ <0 151 4>, -+ <0 152 4>, -+ <0 153 4>, -+ <0 154 4>, -+ <0 155 4>, -+ <0 156 4>, -+ <0 157 4>, -+ <0 158 4>, -+ <0 159 4>, -+ <0 160 4>, -+ <0 161 4>, -+ <0 162 4>, -+ <0 163 4>, -+ <0 164 4>, -+ <0 165 4>, -+ <0 166 4>, -+ <0 167 4>, -+ <0 168 4>, -+ <0 169 4>, -+ <0 170 4>, -+ <0 171 4>, -+ <0 172 4>, -+ <0 173 4>, -+ <0 174 4>, -+ <0 175 4>, -+ <0 176 4>, -+ <0 177 4>, -+ <0 178 4>, -+ <0 179 4>, -+ <0 180 4>, -+ <0 181 4>, -+ <0 182 4>, -+ <0 183 4>, -+ <0 184 4>, -+ <0 185 4>, -+ <0 186 4>, -+ <0 187 4>, -+ <0 188 4>, -+ <0 189 4>, -+ <0 190 4>, -+ <0 191 4>, -+ <0 192 4>, -+ <0 193 4>, -+ <0 194 4>, -+ <0 195 4>, -+ <0 196 4>, -+ <0 197 4>, -+ <0 198 4>, -+ <0 199 4>, -+ <0 200 4>, -+ <0 201 4>, -+ <0 202 4>, -+ <0 203 4>, -+ <0 204 4>, -+ <0 205 4>, -+ <0 206 4>, -+ <0 207 4>, -+ <0 208 4>, -+ <0 209 4>; -+ mmu-masters = <&fsl_mc 0x300 0>; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = <1 13 0x1>, /* Physical Secure PPI, edge triggered */ -+ <1 14 0x1>, /* Physical Non-Secure PPI, edge triggered */ -+ <1 11 0x1>, /* Virtual PPI, edge triggered */ -+ <1 10 0x1>; /* Hypervisor PPI, edge triggered */ -+ arm,reread-timer; -+ fsl,erratum-a008585; -+ }; -+ -+ fsl_mc: fsl-mc@80c000000 { -+ compatible = "fsl,qoriq-mc"; -+ #stream-id-cells = <2>; -+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ -+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ -+ msi-parent = <&its>; -+ #address-cells = <3>; -+ #size-cells = <1>; -+ -+ /* -+ * Region type 0x0 - MC portals -+ * Region type 0x1 - QBMAN portals -+ */ -+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 -+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; -+ -+ /* -+ * Define the maximum number of MACs present on the SoC. -+ * They won't necessarily be all probed, since the -+ * Data Path Layout file and the MC firmware can put fewer -+ * actual DPMAC objects on the MC bus. -+ */ -+ dpmacs { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dpmac1: dpmac@1 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <1>; -+ }; -+ dpmac2: dpmac@2 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <2>; -+ }; -+ dpmac3: dpmac@3 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <3>; -+ }; -+ dpmac4: dpmac@4 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <4>; -+ }; -+ dpmac5: dpmac@5 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <5>; -+ }; -+ dpmac6: dpmac@6 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <6>; -+ }; -+ dpmac7: dpmac@7 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <7>; -+ }; -+ dpmac8: dpmac@8 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <8>; -+ }; -+ dpmac9: dpmac@9 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <9>; -+ }; -+ dpmac10: dpmac@10 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xa>; -+ }; -+ dpmac11: dpmac@11 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xb>; -+ }; -+ dpmac12: dpmac@12 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xc>; -+ }; -+ dpmac13: dpmac@13 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xd>; -+ }; -+ dpmac14: dpmac@14 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xe>; -+ }; -+ dpmac15: dpmac@15 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xf>; -+ }; -+ dpmac16: dpmac@16 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0x10>; -+ }; -+ }; -+ }; -+ -+ ccn@4000000 { -+ compatible = "arm,ccn-504"; -+ reg = <0x0 0x04000000 0x0 0x01000000>; -+ interrupts = <0 12 4>; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00000000 0x80000000 0 0x80000000>; -+ /* DRAM space 1 - 2 GB DRAM */ -+ }; -+}; diff --git a/target/linux/layerscape/patches-4.4/3228-ls2088a-add-ls2088a-its.patch b/target/linux/layerscape/patches-4.4/3228-ls2088a-add-ls2088a-its.patch deleted file mode 100644 index 7aa6382575..0000000000 --- a/target/linux/layerscape/patches-4.4/3228-ls2088a-add-ls2088a-its.patch +++ /dev/null @@ -1,129 +0,0 @@ -From e0f9ccd657893d1a10dfbae291900b3045c471fc Mon Sep 17 00:00:00 2001 -From: Zhao Qiang -Date: Mon, 7 Nov 2016 10:38:51 +0800 -Subject: [PATCH 228/238] ls2088a: add ls2088a its - -Signed-off-by: Zhao Qiang ---- - kernel2088a-qds.its | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++ - kernel2088a-rdb.its | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 110 insertions(+) - create mode 100644 kernel2088a-qds.its - create mode 100644 kernel2088a-rdb.its - ---- /dev/null -+++ b/kernel2088a-qds.its -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2016, Freescale Semiconductor -+ * -+ * Abhimanyu Saini -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+ -+/ { -+ description = "QDS Image file for the LS2080A Linux Kernel"; -+ #address-cells = <1>; -+ -+ images { -+ kernel@1 { -+ description = "ARM64 Linux kernel"; -+ data = /incbin/("./arch/arm64/boot/Image.gz"); -+ type = "kernel"; -+ arch = "arm64"; -+ os = "linux"; -+ compression = "gzip"; -+ load = <0x80080000>; -+ entry = <0x80080000>; -+ }; -+ fdt@1 { -+ description = "Flattened Device Tree blob"; -+ data = /incbin/("./arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dtb"); -+ type = "flat_dt"; -+ arch = "arm64"; -+ compression = "none"; -+ load = <0x90000000>; -+ }; -+ ramdisk@1 { -+ description = "LS2 Ramdisk"; -+ data = /incbin/("./fsl-image-core-ls2088aqds.ext2.gz"); -+ type = "ramdisk"; -+ arch = "arm64"; -+ os = "linux"; -+ compression = "none"; -+ }; -+ }; -+ -+ configurations { -+ default = "config@1"; -+ config@1 { -+ description = "Boot Linux kernel"; -+ kernel = "kernel@1"; -+ fdt = "fdt@1"; -+ ramdisk = "ramdisk@1"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/kernel2088a-rdb.its -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2016, Freescale Semiconductor -+ * -+ * Abhimanyu Saini -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+/dts-v1/; -+ -+/ { -+ description = "RDB Image file for the LS2080A Linux Kernel"; -+ #address-cells = <1>; -+ -+ images { -+ kernel@1 { -+ description = "ARM64 Linux kernel"; -+ data = /incbin/("./arch/arm64/boot/Image.gz"); -+ type = "kernel"; -+ arch = "arm64"; -+ os = "linux"; -+ compression = "gzip"; -+ load = <0x80080000>; -+ entry = <0x80080000>; -+ }; -+ fdt@1 { -+ description = "Flattened Device Tree blob"; -+ data = /incbin/("./arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dtb"); -+ type = "flat_dt"; -+ arch = "arm64"; -+ compression = "none"; -+ load = <0x90000000>; -+ }; -+ ramdisk@1 { -+ description = "LS2 Ramdisk"; -+ data = /incbin/("./fsl-image-core-ls2088ardb.ext2.gz"); -+ type = "ramdisk"; -+ arch = "arm64"; -+ os = "linux"; -+ compression = "none"; -+ }; -+ }; -+ -+ configurations { -+ default = "config@1"; -+ config@1 { -+ description = "Boot Linux kernel"; -+ kernel = "kernel@1"; -+ fdt = "fdt@1"; -+ ramdisk = "ramdisk@1"; -+ }; -+ }; -+}; diff --git a/target/linux/layerscape/patches-4.4/3229-arm-dts-ls1021a-fix-typo-of-MSI-compatible-string.patch b/target/linux/layerscape/patches-4.4/3229-arm-dts-ls1021a-fix-typo-of-MSI-compatible-string.patch deleted file mode 100644 index 926efff7ad..0000000000 --- a/target/linux/layerscape/patches-4.4/3229-arm-dts-ls1021a-fix-typo-of-MSI-compatible-string.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 2c39dc6c100854ed9d617bab9a25557adb6f531a Mon Sep 17 00:00:00 2001 -From: Minghuan Lian -Date: Tue, 17 Jan 2017 17:32:36 +0800 -Subject: [PATCH 05/13] arm: dts: ls1021a: fix typo of MSI compatible string - -Cherry-pick patchwork patch. - -"1" should be replaced by "l". This is a typo. -The patch is to fix it. - -Signed-off-by: Minghuan Lian -Signed-off-by: Yangbo Lu ---- - arch/arm/boot/dts/ls1021a.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/ls1021a.dtsi -+++ b/arch/arm/boot/dts/ls1021a.dtsi -@@ -120,14 +120,14 @@ - }; - - msi1: msi-controller@1570e00 { -- compatible = "fsl,1s1021a-msi"; -+ compatible = "fsl,ls1021a-msi"; - reg = <0x0 0x1570e00 0x0 0x8>; - msi-controller; - interrupts = ; - }; - - msi2: msi-controller@1570e08 { -- compatible = "fsl,1s1021a-msi"; -+ compatible = "fsl,ls1021a-msi"; - reg = <0x0 0x1570e08 0x0 0x8>; - msi-controller; - interrupts = ; diff --git a/target/linux/layerscape/patches-4.4/3230-arm64-dts-ls1043a-fix-typo-of-MSI-compatible-string.patch b/target/linux/layerscape/patches-4.4/3230-arm64-dts-ls1043a-fix-typo-of-MSI-compatible-string.patch deleted file mode 100644 index 4fcd40db72..0000000000 --- a/target/linux/layerscape/patches-4.4/3230-arm64-dts-ls1043a-fix-typo-of-MSI-compatible-string.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 56ff33e848d1a9b77f81e0d3b5ee0b79edcd4938 Mon Sep 17 00:00:00 2001 -From: Minghuan Lian -Date: Thu, 16 Feb 2017 17:52:08 +0800 -Subject: [PATCH 06/13] arm64: dts: ls1043a: fix typo of MSI compatible string - -Cherry-pick patchwork patch with context adjustment. - -"1" should be replaced by "l". This is a typo. -The patch is to fix it. - -Signed-off-by: Minghuan Lian -Signed-off-by: Yangbo Lu ---- - arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -@@ -991,7 +991,7 @@ - }; - - msi1: msi-controller1@1571000 { -- compatible = "fsl,1s1043a-msi"; -+ compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1571000 0x0 0x4>, - <0x0 0x1571004 0x0 0x4>; - reg-names = "msiir", "msir"; -@@ -1000,7 +1000,7 @@ - }; - - msi2: msi-controller2@1572000 { -- compatible = "fsl,1s1043a-msi"; -+ compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1572000 0x0 0x4>, - <0x0 0x1572004 0x0 0x4>; - reg-names = "msiir", "msir"; -@@ -1009,7 +1009,7 @@ - }; - - msi3: msi-controller3@1573000 { -- compatible = "fsl,1s1043a-msi"; -+ compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1573000 0x0 0x4>, - <0x0 0x1573004 0x0 0x4>; - reg-names = "msiir", "msir"; diff --git a/target/linux/layerscape/patches-4.4/3231-arm-dts-ls1021a-share-all-MSIs.patch b/target/linux/layerscape/patches-4.4/3231-arm-dts-ls1021a-share-all-MSIs.patch deleted file mode 100644 index 09a61dd058..0000000000 --- a/target/linux/layerscape/patches-4.4/3231-arm-dts-ls1021a-share-all-MSIs.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 190ae222ef6ded27021620afdc3f5a36861d3625 Mon Sep 17 00:00:00 2001 -From: Minghuan Lian -Date: Tue, 17 Jan 2017 17:32:38 +0800 -Subject: [PATCH 07/13] arm: dts: ls1021a: share all MSIs - -Cherry-pick patchwork patch. - -In order to maximize the use of MSI, a PCIe controller will share -all MSI controllers. The patch changes msi-parent to refer to all -MSI controller dts nodes. - -Signed-off-by: Minghuan Lian -Signed-off-by: Yangbo Lu ---- - arch/arm/boot/dts/ls1021a.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/ls1021a.dtsi -+++ b/arch/arm/boot/dts/ls1021a.dtsi -@@ -568,7 +568,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi1>; -+ msi-parent = <&msi1>, <&msi2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, -@@ -591,7 +591,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi2>; -+ msi-parent = <&msi1>, <&msi2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, diff --git a/target/linux/layerscape/patches-4.4/3232-arm64-dts-ls1043a-share-all-MSIs.patch b/target/linux/layerscape/patches-4.4/3232-arm64-dts-ls1043a-share-all-MSIs.patch deleted file mode 100644 index 4380b5a21d..0000000000 --- a/target/linux/layerscape/patches-4.4/3232-arm64-dts-ls1043a-share-all-MSIs.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 60eedf7a9512683e2a8a998863cc5942e9dbdae5 Mon Sep 17 00:00:00 2001 -From: Minghuan Lian -Date: Tue, 17 Jan 2017 17:32:39 +0800 -Subject: [PATCH 08/13] arm64: dts: ls1043a: share all MSIs - -Cherry-pick patchwork patch. - -In order to maximize the use of MSI, a PCIe controller will share -all MSI controllers. The patch changes "msi-parent" to refer to all -MSI controller dts nodes. - -Signed-off-by: Minghuan Lian -Signed-off-by: Yangbo Lu ---- - arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -@@ -1033,7 +1033,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi1>; -+ msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, -@@ -1058,7 +1058,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi2>; -+ msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, -@@ -1083,7 +1083,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi3>; -+ msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, diff --git a/target/linux/layerscape/patches-4.4/3233-arm64-dts-ls1046a-update-MSI-dts-node.patch b/target/linux/layerscape/patches-4.4/3233-arm64-dts-ls1046a-update-MSI-dts-node.patch deleted file mode 100644 index 02f2e724e5..0000000000 --- a/target/linux/layerscape/patches-4.4/3233-arm64-dts-ls1046a-update-MSI-dts-node.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 1569c166572f9576c6726472b5a726a1a56900bd Mon Sep 17 00:00:00 2001 -From: Yangbo Lu -Date: Thu, 16 Feb 2017 18:00:14 +0800 -Subject: [PATCH] arm64: dts: ls1046a: update MSI dts node - -Update MSI dts node according to below patchwork patch. - -arm64: dts: ls1046a: add MSI dts node -https://patchwork.kernel.org/patch/9520299 - -Signed-off-by: Yangbo Lu ---- - arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 58 +++++++++++++------------- - 1 file changed, 30 insertions(+), 28 deletions(-) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi -@@ -44,6 +44,8 @@ - * OTHER DEALINGS IN THE SOFTWARE. - */ - -+#include -+ - / { - compatible = "fsl,ls1046a"; - interrupt-parent = <&gic>; -@@ -870,34 +872,34 @@ - big-endian; - }; - -- msi: msi-controller@1580000 { -+ msi1: msi-controller@1580000 { - compatible = "fsl,ls1046a-msi"; -- #address-cells = <2>; -- #size-cells = <2>; -- ranges; - msi-controller; -+ reg = <0x0 0x1580000 0x0 0x10000>; -+ interrupts = , -+ , -+ , -+ ; -+ }; - -- msi-bank@1580000 { -- reg = <0x0 0x1580000 0x0 0x10000>; -- interrupts = <0 116 0x4>, -- <0 111 0x4>, -- <0 112 0x4>, -- <0 113 0x4>; -- }; -- msi-bank@1590000 { -- reg = <0x0 0x1590000 0x0 0x10000>; -- interrupts = <0 126 0x4>, -- <0 121 0x4>, -- <0 122 0x4>, -- <0 123 0x4>; -- }; -- msi-bank@15a0000 { -- reg = <0x0 0x15a0000 0x0 0x10000>; -- interrupts = <0 160 0x4>, -- <0 155 0x4>, -- <0 156 0x4>, -- <0 157 0x4>; -- }; -+ msi2: msi-controller@1590000 { -+ compatible = "fsl,ls1046a-msi"; -+ msi-controller; -+ reg = <0x0 0x1590000 0x0 0x10000>; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+ -+ msi3: msi-controller@15a0000 { -+ compatible = "fsl,ls1046a-msi"; -+ msi-controller; -+ reg = <0x0 0x15a0000 0x0 0x10000>; -+ interrupts = , -+ , -+ , -+ ; - }; - - pcie@3400000 { -@@ -916,7 +918,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi>; -+ msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, -@@ -941,7 +943,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi>; -+ msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, -@@ -966,7 +968,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi>; -+ msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, diff --git a/target/linux/layerscape/patches-4.4/3234-dts-ls1043a-change-GIC-register-for-rev1.1.patch b/target/linux/layerscape/patches-4.4/3234-dts-ls1043a-change-GIC-register-for-rev1.1.patch deleted file mode 100644 index c693b28a7c..0000000000 --- a/target/linux/layerscape/patches-4.4/3234-dts-ls1043a-change-GIC-register-for-rev1.1.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 118d9d4b959d30a582d4bd26d1a1918a43ea0ddf Mon Sep 17 00:00:00 2001 -From: Gong Qianyu -Date: Wed, 7 Sep 2016 18:33:09 +0800 -Subject: [PATCH 13/13] dts: ls1043a: change GIC register for rev1.1 - -Cherry-pick sdk patch. - -Signed-off-by: Gong Qianyu -Signed-off-by: Minghuan Lian -Signed-off-by: Mingkai Hu -Signed-off-by: Yangbo Lu ---- - arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -@@ -141,10 +141,10 @@ - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; -- reg = <0x0 0x1401000 0 0x1000>, /* GICD */ -- <0x0 0x1402000 0 0x2000>, /* GICC */ -- <0x0 0x1404000 0 0x2000>, /* GICH */ -- <0x0 0x1406000 0 0x2000>; /* GICV */ -+ reg = <0x0 0x1410000 0 0x10000>, /* GICD */ -+ <0x0 0x1420000 0 0x20000>, /* GICC */ -+ <0x0 0x1440000 0 0x20000>, /* GICH */ -+ <0x0 0x1460000 0 0x20000>; /* GICV */ - interrupts = <1 9 0xf08>; - }; - diff --git a/target/linux/layerscape/patches-4.4/4043-driver-memory-Removal-of-deprecated-NO_IRQ.patch b/target/linux/layerscape/patches-4.4/4043-driver-memory-Removal-of-deprecated-NO_IRQ.patch deleted file mode 100644 index a2ff5ab19d..0000000000 --- a/target/linux/layerscape/patches-4.4/4043-driver-memory-Removal-of-deprecated-NO_IRQ.patch +++ /dev/null @@ -1,24 +0,0 @@ -From ae1f7ae8bbacbdbf9df3977449f97d1432ff1957 Mon Sep 17 00:00:00 2001 -From: Raghav Dogra -Date: Wed, 16 Dec 2015 16:11:31 +0530 -Subject: [PATCH 43/70] driver/memory: Removal of deprecated NO_IRQ - -Replacing the NO_IRQ macro with 0. If there is no interrupt, -returned value will be 0 regardless of what NO_IRQ is defined. - -Signed-off-by: Raghav Dogra ---- - drivers/memory/fsl_ifc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/memory/fsl_ifc.c -+++ b/drivers/memory/fsl_ifc.c -@@ -260,7 +260,7 @@ static int fsl_ifc_ctrl_probe(struct pla - - /* get the Controller level irq */ - fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0); -- if (fsl_ifc_ctrl_dev->irq == NO_IRQ) { -+ if (fsl_ifc_ctrl_dev->irq == 0) { - dev_err(&dev->dev, "failed to get irq resource " - "for IFC\n"); - ret = -ENODEV; diff --git a/target/linux/layerscape/patches-4.4/4044-drivers-memory-Add-deep-sleep-support-for-IFC.patch b/target/linux/layerscape/patches-4.4/4044-drivers-memory-Add-deep-sleep-support-for-IFC.patch deleted file mode 100644 index dc6508f1ec..0000000000 --- a/target/linux/layerscape/patches-4.4/4044-drivers-memory-Add-deep-sleep-support-for-IFC.patch +++ /dev/null @@ -1,233 +0,0 @@ -From bb35d670afd2f3501de36c158e9842817ce013b8 Mon Sep 17 00:00:00 2001 -From: Raghav Dogra -Date: Fri, 15 Jan 2016 17:10:09 +0530 -Subject: [PATCH 44/70] drivers/memory: Add deep sleep support for IFC - -Add support of suspend, resume function to support deep sleep. -Also make sure of SRAM initialization during resume. - -Signed-off-by: Raghav Dogra ---- - drivers/memory/fsl_ifc.c | 163 ++++++++++++++++++++++++++++++++++++++++++++++ - include/linux/fsl_ifc.h | 6 ++ - 2 files changed, 169 insertions(+) - ---- a/drivers/memory/fsl_ifc.c -+++ b/drivers/memory/fsl_ifc.c -@@ -24,6 +24,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -35,6 +36,8 @@ - - struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev; - EXPORT_SYMBOL(fsl_ifc_ctrl_dev); -+#define FSL_IFC_V1_3_0 0x01030000 -+#define IFC_TIMEOUT_MSECS 100000 /* 100ms */ - - /* - * convert_ifc_address - convert the base address -@@ -309,6 +312,161 @@ err: - return ret; - } - -+#ifdef CONFIG_PM_SLEEP -+/* save ifc registers */ -+static int fsl_ifc_suspend(struct device *dev) -+{ -+ struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev); -+ struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -+ __be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en, -+ gpcm_evter_intr_en; -+ -+ ctrl->saved_regs = kzalloc(sizeof(struct fsl_ifc_regs), GFP_KERNEL); -+ if (!ctrl->saved_regs) -+ return -ENOMEM; -+ -+ cm_evter_intr_en = ifc_in32(&ifc->cm_evter_intr_en); -+ nand_evter_intr_en = ifc_in32(&ifc->ifc_nand.nand_evter_intr_en); -+ nor_evter_intr_en = ifc_in32(&ifc->ifc_nor.nor_evter_intr_en); -+ gpcm_evter_intr_en = ifc_in32(&ifc->ifc_gpcm.gpcm_evter_intr_en); -+ -+/* IFC interrupts disabled */ -+ -+ ifc_out32(0x0, &ifc->cm_evter_intr_en); -+ ifc_out32(0x0, &ifc->ifc_nand.nand_evter_intr_en); -+ ifc_out32(0x0, &ifc->ifc_nor.nor_evter_intr_en); -+ ifc_out32(0x0, &ifc->ifc_gpcm.gpcm_evter_intr_en); -+ -+ memcpy_fromio(ctrl->saved_regs, ifc, sizeof(struct fsl_ifc_regs)); -+ -+/* save the interrupt values */ -+ ctrl->saved_regs->cm_evter_intr_en = cm_evter_intr_en; -+ ctrl->saved_regs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en; -+ ctrl->saved_regs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en; -+ ctrl->saved_regs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en; -+ -+ return 0; -+} -+ -+/* restore ifc registers */ -+static int fsl_ifc_resume(struct device *dev) -+{ -+ struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev); -+ struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -+ struct fsl_ifc_regs *savd_regs = ctrl->saved_regs; -+ uint32_t ver = 0, ncfgr, status, ifc_bank, i; -+ -+/* -+ * IFC interrupts disabled -+ */ -+ ifc_out32(0x0, &ifc->cm_evter_intr_en); -+ ifc_out32(0x0, &ifc->ifc_nand.nand_evter_intr_en); -+ ifc_out32(0x0, &ifc->ifc_nor.nor_evter_intr_en); -+ ifc_out32(0x0, &ifc->ifc_gpcm.gpcm_evter_intr_en); -+ -+ -+ if (ctrl->saved_regs) { -+ for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) { -+ ifc_out32(savd_regs->cspr_cs[ifc_bank].cspr_ext, -+ &ifc->cspr_cs[ifc_bank].cspr_ext); -+ ifc_out32(savd_regs->cspr_cs[ifc_bank].cspr, -+ &ifc->cspr_cs[ifc_bank].cspr); -+ ifc_out32(savd_regs->amask_cs[ifc_bank].amask, -+ &ifc->amask_cs[ifc_bank].amask); -+ ifc_out32(savd_regs->csor_cs[ifc_bank].csor_ext, -+ &ifc->csor_cs[ifc_bank].csor_ext); -+ ifc_out32(savd_regs->csor_cs[ifc_bank].csor, -+ &ifc->csor_cs[ifc_bank].csor); -+ for (i = 0; i < 4; i++) { -+ ifc_out32(savd_regs->ftim_cs[ifc_bank].ftim[i], -+ &ifc->ftim_cs[ifc_bank].ftim[i]); -+ } -+ } -+ ifc_out32(savd_regs->ifc_gcr, &ifc->ifc_gcr); -+ ifc_out32(savd_regs->cm_evter_en, &ifc->cm_evter_en); -+ -+/* -+* IFC controller NAND machine registers -+*/ -+ ifc_out32(savd_regs->ifc_nand.ncfgr, &ifc->ifc_nand.ncfgr); -+ ifc_out32(savd_regs->ifc_nand.nand_fcr0, -+ &ifc->ifc_nand.nand_fcr0); -+ ifc_out32(savd_regs->ifc_nand.nand_fcr1, -+ &ifc->ifc_nand.nand_fcr1); -+ ifc_out32(savd_regs->ifc_nand.row0, &ifc->ifc_nand.row0); -+ ifc_out32(savd_regs->ifc_nand.row1, &ifc->ifc_nand.row1); -+ ifc_out32(savd_regs->ifc_nand.col0, &ifc->ifc_nand.col0); -+ ifc_out32(savd_regs->ifc_nand.col1, &ifc->ifc_nand.col1); -+ ifc_out32(savd_regs->ifc_nand.row2, &ifc->ifc_nand.row2); -+ ifc_out32(savd_regs->ifc_nand.col2, &ifc->ifc_nand.col2); -+ ifc_out32(savd_regs->ifc_nand.row3, &ifc->ifc_nand.row3); -+ ifc_out32(savd_regs->ifc_nand.col3, &ifc->ifc_nand.col3); -+ ifc_out32(savd_regs->ifc_nand.nand_fbcr, -+ &ifc->ifc_nand.nand_fbcr); -+ ifc_out32(savd_regs->ifc_nand.nand_fir0, -+ &ifc->ifc_nand.nand_fir0); -+ ifc_out32(savd_regs->ifc_nand.nand_fir1, -+ &ifc->ifc_nand.nand_fir1); -+ ifc_out32(savd_regs->ifc_nand.nand_fir2, -+ &ifc->ifc_nand.nand_fir2); -+ ifc_out32(savd_regs->ifc_nand.nand_csel, -+ &ifc->ifc_nand.nand_csel); -+ ifc_out32(savd_regs->ifc_nand.nandseq_strt, -+ &ifc->ifc_nand.nandseq_strt); -+ ifc_out32(savd_regs->ifc_nand.nand_evter_en, -+ &ifc->ifc_nand.nand_evter_en); -+ ifc_out32(savd_regs->ifc_nand.nanndcr, &ifc->ifc_nand.nanndcr); -+ -+/* -+* IFC controller NOR machine registers -+*/ -+ ifc_out32(savd_regs->ifc_nor.nor_evter_en, -+ &ifc->ifc_nor.nor_evter_en); -+ ifc_out32(savd_regs->ifc_nor.norcr, &ifc->ifc_nor.norcr); -+ -+/* -+ * IFC controller GPCM Machine registers -+ */ -+ ifc_out32(savd_regs->ifc_gpcm.gpcm_evter_en, -+ &ifc->ifc_gpcm.gpcm_evter_en); -+ -+ -+ -+/* -+ * IFC interrupts enabled -+ */ -+ ifc_out32(ctrl->saved_regs->cm_evter_intr_en, &ifc->cm_evter_intr_en); -+ ifc_out32(ctrl->saved_regs->ifc_nand.nand_evter_intr_en, -+ &ifc->ifc_nand.nand_evter_intr_en); -+ ifc_out32(ctrl->saved_regs->ifc_nor.nor_evter_intr_en, -+ &ifc->ifc_nor.nor_evter_intr_en); -+ ifc_out32(ctrl->saved_regs->ifc_gpcm.gpcm_evter_intr_en, -+ &ifc->ifc_gpcm.gpcm_evter_intr_en); -+ -+ kfree(ctrl->saved_regs); -+ ctrl->saved_regs = NULL; -+ } -+ -+ ver = ifc_in32(&ctrl->regs->ifc_rev); -+ ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr); -+ if (ver >= FSL_IFC_V1_3_0) { -+ -+ ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN, -+ &ifc->ifc_nand.ncfgr); -+ /* wait for SRAM_INIT bit to be clear or timeout */ -+ status = spin_event_timeout( -+ !(ifc_in32(&ifc->ifc_nand.ncfgr) -+ & IFC_NAND_SRAM_INIT_EN), -+ IFC_TIMEOUT_MSECS, 0); -+ -+ if (!status) -+ dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT"); -+ } -+ -+ return 0; -+} -+#endif /* CONFIG_PM_SLEEP */ -+ - static const struct of_device_id fsl_ifc_match[] = { - { - .compatible = "fsl,ifc", -@@ -316,10 +474,15 @@ static const struct of_device_id fsl_ifc - {}, - }; - -+static const struct dev_pm_ops ifc_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(fsl_ifc_suspend, fsl_ifc_resume) -+}; -+ - static struct platform_driver fsl_ifc_ctrl_driver = { - .driver = { - .name = "fsl-ifc", - .of_match_table = fsl_ifc_match, -+ .pm = &ifc_pm_ops, - }, - .probe = fsl_ifc_ctrl_probe, - .remove = fsl_ifc_ctrl_remove, ---- a/include/linux/fsl_ifc.h -+++ b/include/linux/fsl_ifc.h -@@ -270,6 +270,8 @@ - */ - /* Auto Boot Mode */ - #define IFC_NAND_NCFGR_BOOT 0x80000000 -+/* SRAM INIT EN */ -+#define IFC_NAND_SRAM_INIT_EN 0x20000000 - /* Addressing Mode-ROW0+n/COL0 */ - #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 - /* Addressing Mode-ROW0+n/COL0+n */ -@@ -842,6 +844,10 @@ struct fsl_ifc_ctrl { - u32 nand_stat; - wait_queue_head_t nand_wait; - bool little_endian; -+#ifdef CONFIG_PM_SLEEP -+ /*save regs when system goes to deep sleep*/ -+ struct fsl_ifc_regs *saved_regs; -+#endif - }; - - extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev; diff --git a/target/linux/layerscape/patches-4.4/4045-driver-memory-Update-dependency-of-IFC-for-Layerscap.patch b/target/linux/layerscape/patches-4.4/4045-driver-memory-Update-dependency-of-IFC-for-Layerscap.patch deleted file mode 100644 index a40eef1c20..0000000000 --- a/target/linux/layerscape/patches-4.4/4045-driver-memory-Update-dependency-of-IFC-for-Layerscap.patch +++ /dev/null @@ -1,51 +0,0 @@ -From bf489e54ef3de7de2d9caf896141fd08490a89c9 Mon Sep 17 00:00:00 2001 -From: Raghav Dogra -Date: Wed, 16 Dec 2015 16:11:50 +0530 -Subject: [PATCH 45/70] driver/memory: Update dependency of IFC for Layerscape - -IFC NAND is not working on ARM layescape platform due to -undefined macro FSL_SOC. -This patch fixes the dependency to enable NAND. - -Signed-off-by: Raghav Dogra ---- - drivers/memory/Kconfig | 2 +- - drivers/memory/fsl_ifc.c | 4 +++- - drivers/mtd/nand/Kconfig | 2 +- - 3 files changed, 5 insertions(+), 3 deletions(-) - ---- a/drivers/memory/Kconfig -+++ b/drivers/memory/Kconfig -@@ -103,7 +103,7 @@ config FSL_CORENET_CF - - config FSL_IFC - bool -- depends on FSL_SOC -+ depends on FSL_SOC || ARCH_LAYERSCAPE - - config JZ4780_NEMC - bool "Ingenic JZ4780 SoC NEMC driver" ---- a/drivers/memory/fsl_ifc.c -+++ b/drivers/memory/fsl_ifc.c -@@ -32,7 +32,9 @@ - #include - #include - #include --#include -+#include -+#include -+#include - - struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev; - EXPORT_SYMBOL(fsl_ifc_ctrl_dev); ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -436,7 +436,7 @@ config MTD_NAND_FSL_ELBC - - config MTD_NAND_FSL_IFC - tristate "NAND support for Freescale IFC controller" -- depends on MTD_NAND && FSL_SOC -+ depends on MTD_NAND && (FSL_SOC || ARCH_LAYERSCAPE) - select FSL_IFC - select MEMORY - help diff --git a/target/linux/layerscape/patches-4.4/4046-mtd-ifc-Segregate-IFC-fcm-and-runtime-registers.patch b/target/linux/layerscape/patches-4.4/4046-mtd-ifc-Segregate-IFC-fcm-and-runtime-registers.patch deleted file mode 100644 index d64e002983..0000000000 --- a/target/linux/layerscape/patches-4.4/4046-mtd-ifc-Segregate-IFC-fcm-and-runtime-registers.patch +++ /dev/null @@ -1,705 +0,0 @@ -From 1c62b9982b7f6cb560d1237d2658945c070c91d4 Mon Sep 17 00:00:00 2001 -From: Raghav Dogra -Date: Wed, 20 Jan 2016 13:06:32 +0530 -Subject: [PATCH 46/70] mtd/ifc: Segregate IFC fcm and runtime registers - -IFC has two set of registers viz FCM (Flash control machine) -aka global and run time registers. These set are defined in two -memory map PAGES. Upto IFC 1.4 PAGE size is 4 KB and from IFC2.0 -PAGE size is 64KB - -Signed-off-by: Jaiprakash Singh -Signed-off-by: Raghav Dogra ---- - drivers/memory/fsl_ifc.c | 251 ++++++++++++++++++++------------------- - drivers/mtd/nand/fsl_ifc_nand.c | 72 ++++++----- - include/linux/fsl_ifc.h | 48 +++++--- - 3 files changed, 203 insertions(+), 168 deletions(-) - ---- a/drivers/memory/fsl_ifc.c -+++ b/drivers/memory/fsl_ifc.c -@@ -64,11 +64,11 @@ int fsl_ifc_find(phys_addr_t addr_base) - { - int i = 0; - -- if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs) -+ if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs) - return -ENODEV; - - for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) { -- u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr); -+ u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr); - if (cspr & CSPR_V && (cspr & CSPR_BA) == - convert_ifc_address(addr_base)) - return i; -@@ -80,7 +80,7 @@ EXPORT_SYMBOL(fsl_ifc_find); - - static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl) - { -- struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -+ struct fsl_ifc_fcm __iomem *ifc = ctrl->gregs; - - /* - * Clear all the common status and event registers -@@ -109,7 +109,7 @@ static int fsl_ifc_ctrl_remove(struct pl - irq_dispose_mapping(ctrl->nand_irq); - irq_dispose_mapping(ctrl->irq); - -- iounmap(ctrl->regs); -+ iounmap(ctrl->gregs); - - dev_set_drvdata(&dev->dev, NULL); - kfree(ctrl); -@@ -127,7 +127,7 @@ static DEFINE_SPINLOCK(nand_irq_lock); - - static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl) - { -- struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -+ struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; - unsigned long flags; - u32 stat; - -@@ -162,7 +162,7 @@ static irqreturn_t fsl_ifc_nand_irq(int - static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data) - { - struct fsl_ifc_ctrl *ctrl = data; -- struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -+ struct fsl_ifc_fcm __iomem *ifc = ctrl->gregs; - u32 err_axiid, err_srcid, status, cs_err, err_addr; - irqreturn_t ret = IRQ_NONE; - -@@ -220,6 +220,7 @@ static int fsl_ifc_ctrl_probe(struct pla - { - int ret = 0; - int version, banks; -+ void __iomem *addr; - - dev_info(&dev->dev, "Freescale Integrated Flash Controller\n"); - -@@ -230,22 +231,13 @@ static int fsl_ifc_ctrl_probe(struct pla - dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev); - - /* IOMAP the entire IFC region */ -- fsl_ifc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0); -- if (!fsl_ifc_ctrl_dev->regs) { -+ fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0); -+ if (!fsl_ifc_ctrl_dev->gregs) { - dev_err(&dev->dev, "failed to get memory region\n"); - ret = -ENODEV; - goto err; - } - -- version = ifc_in32(&fsl_ifc_ctrl_dev->regs->ifc_rev) & -- FSL_IFC_VERSION_MASK; -- banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8; -- dev_info(&dev->dev, "IFC version %d.%d, %d banks\n", -- version >> 24, (version >> 16) & 0xf, banks); -- -- fsl_ifc_ctrl_dev->version = version; -- fsl_ifc_ctrl_dev->banks = banks; -- - if (of_property_read_bool(dev->dev.of_node, "little-endian")) { - fsl_ifc_ctrl_dev->little_endian = true; - dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n"); -@@ -254,8 +246,9 @@ static int fsl_ifc_ctrl_probe(struct pla - dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n"); - } - -- version = ioread32be(&fsl_ifc_ctrl_dev->regs->ifc_rev) & -+ version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) & - FSL_IFC_VERSION_MASK; -+ - banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8; - dev_info(&dev->dev, "IFC version %d.%d, %d banks\n", - version >> 24, (version >> 16) & 0xf, banks); -@@ -263,6 +256,14 @@ static int fsl_ifc_ctrl_probe(struct pla - fsl_ifc_ctrl_dev->version = version; - fsl_ifc_ctrl_dev->banks = banks; - -+ addr = fsl_ifc_ctrl_dev->gregs; -+ if (version >= FSL_IFC_VERSION_2_0_0) -+ fsl_ifc_ctrl_dev->rregs = -+ (struct fsl_ifc_runtime *)(addr + PGOFFSET_64K); -+ else -+ fsl_ifc_ctrl_dev->rregs = -+ (struct fsl_ifc_runtime *)(addr + PGOFFSET_4K); -+ - /* get the Controller level irq */ - fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0); - if (fsl_ifc_ctrl_dev->irq == 0) { -@@ -319,33 +320,39 @@ err: - static int fsl_ifc_suspend(struct device *dev) - { - struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev); -- struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -+ struct fsl_ifc_fcm __iomem *fcm = ctrl->gregs; -+ struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs; - __be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en, - gpcm_evter_intr_en; - -- ctrl->saved_regs = kzalloc(sizeof(struct fsl_ifc_regs), GFP_KERNEL); -- if (!ctrl->saved_regs) -+ ctrl->saved_gregs = kzalloc(sizeof(struct fsl_ifc_fcm), GFP_KERNEL); -+ if (!ctrl->saved_gregs) -+ return -ENOMEM; -+ ctrl->saved_rregs = kzalloc(sizeof(struct fsl_ifc_runtime), GFP_KERNEL); -+ if (!ctrl->saved_rregs) - return -ENOMEM; - -- cm_evter_intr_en = ifc_in32(&ifc->cm_evter_intr_en); -- nand_evter_intr_en = ifc_in32(&ifc->ifc_nand.nand_evter_intr_en); -- nor_evter_intr_en = ifc_in32(&ifc->ifc_nor.nor_evter_intr_en); -- gpcm_evter_intr_en = ifc_in32(&ifc->ifc_gpcm.gpcm_evter_intr_en); -+ cm_evter_intr_en = ifc_in32(&fcm->cm_evter_intr_en); -+ nand_evter_intr_en = ifc_in32(&runtime->ifc_nand.nand_evter_intr_en); -+ nor_evter_intr_en = ifc_in32(&runtime->ifc_nor.nor_evter_intr_en); -+ gpcm_evter_intr_en = ifc_in32(&runtime->ifc_gpcm.gpcm_evter_intr_en); - - /* IFC interrupts disabled */ - -- ifc_out32(0x0, &ifc->cm_evter_intr_en); -- ifc_out32(0x0, &ifc->ifc_nand.nand_evter_intr_en); -- ifc_out32(0x0, &ifc->ifc_nor.nor_evter_intr_en); -- ifc_out32(0x0, &ifc->ifc_gpcm.gpcm_evter_intr_en); -- -- memcpy_fromio(ctrl->saved_regs, ifc, sizeof(struct fsl_ifc_regs)); -+ ifc_out32(0x0, &fcm->cm_evter_intr_en); -+ ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en); -+ ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en); -+ ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en); -+ -+ memcpy_fromio(ctrl->saved_gregs, fcm, sizeof(struct fsl_ifc_fcm)); -+ memcpy_fromio(ctrl->saved_rregs, runtime, -+ sizeof(struct fsl_ifc_runtime)); - - /* save the interrupt values */ -- ctrl->saved_regs->cm_evter_intr_en = cm_evter_intr_en; -- ctrl->saved_regs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en; -- ctrl->saved_regs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en; -- ctrl->saved_regs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en; -+ ctrl->saved_gregs->cm_evter_intr_en = cm_evter_intr_en; -+ ctrl->saved_rregs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en; -+ ctrl->saved_rregs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en; -+ ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en; - - return 0; - } -@@ -354,110 +361,116 @@ static int fsl_ifc_suspend(struct device - static int fsl_ifc_resume(struct device *dev) - { - struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev); -- struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -- struct fsl_ifc_regs *savd_regs = ctrl->saved_regs; -+ struct fsl_ifc_fcm __iomem *fcm = ctrl->gregs; -+ struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs; -+ struct fsl_ifc_fcm *savd_gregs = ctrl->saved_gregs; -+ struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs; - uint32_t ver = 0, ncfgr, status, ifc_bank, i; - - /* - * IFC interrupts disabled - */ -- ifc_out32(0x0, &ifc->cm_evter_intr_en); -- ifc_out32(0x0, &ifc->ifc_nand.nand_evter_intr_en); -- ifc_out32(0x0, &ifc->ifc_nor.nor_evter_intr_en); -- ifc_out32(0x0, &ifc->ifc_gpcm.gpcm_evter_intr_en); -+ ifc_out32(0x0, &fcm->cm_evter_intr_en); -+ ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en); -+ ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en); -+ ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en); - - -- if (ctrl->saved_regs) { -+ if (ctrl->saved_gregs) { - for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) { -- ifc_out32(savd_regs->cspr_cs[ifc_bank].cspr_ext, -- &ifc->cspr_cs[ifc_bank].cspr_ext); -- ifc_out32(savd_regs->cspr_cs[ifc_bank].cspr, -- &ifc->cspr_cs[ifc_bank].cspr); -- ifc_out32(savd_regs->amask_cs[ifc_bank].amask, -- &ifc->amask_cs[ifc_bank].amask); -- ifc_out32(savd_regs->csor_cs[ifc_bank].csor_ext, -- &ifc->csor_cs[ifc_bank].csor_ext); -- ifc_out32(savd_regs->csor_cs[ifc_bank].csor, -- &ifc->csor_cs[ifc_bank].csor); -+ ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr_ext, -+ &fcm->cspr_cs[ifc_bank].cspr_ext); -+ ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr, -+ &fcm->cspr_cs[ifc_bank].cspr); -+ ifc_out32(savd_gregs->amask_cs[ifc_bank].amask, -+ &fcm->amask_cs[ifc_bank].amask); -+ ifc_out32(savd_gregs->csor_cs[ifc_bank].csor_ext, -+ &fcm->csor_cs[ifc_bank].csor_ext); -+ ifc_out32(savd_gregs->csor_cs[ifc_bank].csor, -+ &fcm->csor_cs[ifc_bank].csor); - for (i = 0; i < 4; i++) { -- ifc_out32(savd_regs->ftim_cs[ifc_bank].ftim[i], -- &ifc->ftim_cs[ifc_bank].ftim[i]); -+ ifc_out32(savd_gregs->ftim_cs[ifc_bank].ftim[i], -+ &fcm->ftim_cs[ifc_bank].ftim[i]); - } - } -- ifc_out32(savd_regs->ifc_gcr, &ifc->ifc_gcr); -- ifc_out32(savd_regs->cm_evter_en, &ifc->cm_evter_en); -- --/* --* IFC controller NAND machine registers --*/ -- ifc_out32(savd_regs->ifc_nand.ncfgr, &ifc->ifc_nand.ncfgr); -- ifc_out32(savd_regs->ifc_nand.nand_fcr0, -- &ifc->ifc_nand.nand_fcr0); -- ifc_out32(savd_regs->ifc_nand.nand_fcr1, -- &ifc->ifc_nand.nand_fcr1); -- ifc_out32(savd_regs->ifc_nand.row0, &ifc->ifc_nand.row0); -- ifc_out32(savd_regs->ifc_nand.row1, &ifc->ifc_nand.row1); -- ifc_out32(savd_regs->ifc_nand.col0, &ifc->ifc_nand.col0); -- ifc_out32(savd_regs->ifc_nand.col1, &ifc->ifc_nand.col1); -- ifc_out32(savd_regs->ifc_nand.row2, &ifc->ifc_nand.row2); -- ifc_out32(savd_regs->ifc_nand.col2, &ifc->ifc_nand.col2); -- ifc_out32(savd_regs->ifc_nand.row3, &ifc->ifc_nand.row3); -- ifc_out32(savd_regs->ifc_nand.col3, &ifc->ifc_nand.col3); -- ifc_out32(savd_regs->ifc_nand.nand_fbcr, -- &ifc->ifc_nand.nand_fbcr); -- ifc_out32(savd_regs->ifc_nand.nand_fir0, -- &ifc->ifc_nand.nand_fir0); -- ifc_out32(savd_regs->ifc_nand.nand_fir1, -- &ifc->ifc_nand.nand_fir1); -- ifc_out32(savd_regs->ifc_nand.nand_fir2, -- &ifc->ifc_nand.nand_fir2); -- ifc_out32(savd_regs->ifc_nand.nand_csel, -- &ifc->ifc_nand.nand_csel); -- ifc_out32(savd_regs->ifc_nand.nandseq_strt, -- &ifc->ifc_nand.nandseq_strt); -- ifc_out32(savd_regs->ifc_nand.nand_evter_en, -- &ifc->ifc_nand.nand_evter_en); -- ifc_out32(savd_regs->ifc_nand.nanndcr, &ifc->ifc_nand.nanndcr); -- --/* --* IFC controller NOR machine registers --*/ -- ifc_out32(savd_regs->ifc_nor.nor_evter_en, -- &ifc->ifc_nor.nor_evter_en); -- ifc_out32(savd_regs->ifc_nor.norcr, &ifc->ifc_nor.norcr); -- --/* -- * IFC controller GPCM Machine registers -- */ -- ifc_out32(savd_regs->ifc_gpcm.gpcm_evter_en, -- &ifc->ifc_gpcm.gpcm_evter_en); -- -- -- --/* -- * IFC interrupts enabled -- */ -- ifc_out32(ctrl->saved_regs->cm_evter_intr_en, &ifc->cm_evter_intr_en); -- ifc_out32(ctrl->saved_regs->ifc_nand.nand_evter_intr_en, -- &ifc->ifc_nand.nand_evter_intr_en); -- ifc_out32(ctrl->saved_regs->ifc_nor.nor_evter_intr_en, -- &ifc->ifc_nor.nor_evter_intr_en); -- ifc_out32(ctrl->saved_regs->ifc_gpcm.gpcm_evter_intr_en, -- &ifc->ifc_gpcm.gpcm_evter_intr_en); -+ ifc_out32(savd_gregs->rb_map, &fcm->rb_map); -+ ifc_out32(savd_gregs->wb_map, &fcm->wb_map); -+ ifc_out32(savd_gregs->ifc_gcr, &fcm->ifc_gcr); -+ ifc_out32(savd_gregs->ddr_ccr_low, &fcm->ddr_ccr_low); -+ ifc_out32(savd_gregs->cm_evter_en, &fcm->cm_evter_en); -+ } - -- kfree(ctrl->saved_regs); -- ctrl->saved_regs = NULL; -+ if (ctrl->saved_rregs) { -+ /* IFC controller NAND machine registers */ -+ ifc_out32(savd_rregs->ifc_nand.ncfgr, -+ &runtime->ifc_nand.ncfgr); -+ ifc_out32(savd_rregs->ifc_nand.nand_fcr0, -+ &runtime->ifc_nand.nand_fcr0); -+ ifc_out32(savd_rregs->ifc_nand.nand_fcr1, -+ &runtime->ifc_nand.nand_fcr1); -+ ifc_out32(savd_rregs->ifc_nand.row0, &runtime->ifc_nand.row0); -+ ifc_out32(savd_rregs->ifc_nand.row1, &runtime->ifc_nand.row1); -+ ifc_out32(savd_rregs->ifc_nand.col0, &runtime->ifc_nand.col0); -+ ifc_out32(savd_rregs->ifc_nand.col1, &runtime->ifc_nand.col1); -+ ifc_out32(savd_rregs->ifc_nand.row2, &runtime->ifc_nand.row2); -+ ifc_out32(savd_rregs->ifc_nand.col2, &runtime->ifc_nand.col2); -+ ifc_out32(savd_rregs->ifc_nand.row3, &runtime->ifc_nand.row3); -+ ifc_out32(savd_rregs->ifc_nand.col3, &runtime->ifc_nand.col3); -+ ifc_out32(savd_rregs->ifc_nand.nand_fbcr, -+ &runtime->ifc_nand.nand_fbcr); -+ ifc_out32(savd_rregs->ifc_nand.nand_fir0, -+ &runtime->ifc_nand.nand_fir0); -+ ifc_out32(savd_rregs->ifc_nand.nand_fir1, -+ &runtime->ifc_nand.nand_fir1); -+ ifc_out32(savd_rregs->ifc_nand.nand_fir2, -+ &runtime->ifc_nand.nand_fir2); -+ ifc_out32(savd_rregs->ifc_nand.nand_csel, -+ &runtime->ifc_nand.nand_csel); -+ ifc_out32(savd_rregs->ifc_nand.nandseq_strt, -+ &runtime->ifc_nand.nandseq_strt); -+ ifc_out32(savd_rregs->ifc_nand.nand_evter_en, -+ &runtime->ifc_nand.nand_evter_en); -+ ifc_out32(savd_rregs->ifc_nand.nanndcr, -+ &runtime->ifc_nand.nanndcr); -+ ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg0, -+ &runtime->ifc_nand.nand_dll_lowcfg0); -+ ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg1, -+ &runtime->ifc_nand.nand_dll_lowcfg1); -+ -+ /* IFC controller NOR machine registers */ -+ ifc_out32(savd_rregs->ifc_nor.nor_evter_en, -+ &runtime->ifc_nor.nor_evter_en); -+ ifc_out32(savd_rregs->ifc_nor.norcr, &runtime->ifc_nor.norcr); -+ -+ /* IFC controller GPCM Machine registers */ -+ ifc_out32(savd_rregs->ifc_gpcm.gpcm_evter_en, -+ &runtime->ifc_gpcm.gpcm_evter_en); -+ -+ /* IFC interrupts enabled */ -+ ifc_out32(ctrl->saved_gregs->cm_evter_intr_en, -+ &fcm->cm_evter_intr_en); -+ ifc_out32(ctrl->saved_rregs->ifc_nand.nand_evter_intr_en, -+ &runtime->ifc_nand.nand_evter_intr_en); -+ ifc_out32(ctrl->saved_rregs->ifc_nor.nor_evter_intr_en, -+ &runtime->ifc_nor.nor_evter_intr_en); -+ ifc_out32(ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en, -+ &runtime->ifc_gpcm.gpcm_evter_intr_en); -+ -+ kfree(ctrl->saved_gregs); -+ kfree(ctrl->saved_rregs); -+ ctrl->saved_gregs = NULL; -+ ctrl->saved_rregs = NULL; - } - -- ver = ifc_in32(&ctrl->regs->ifc_rev); -- ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr); -+ ver = ifc_in32(&fcm->ifc_rev); -+ ncfgr = ifc_in32(&runtime->ifc_nand.ncfgr); - if (ver >= FSL_IFC_V1_3_0) { - - ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN, -- &ifc->ifc_nand.ncfgr); -+ &runtime->ifc_nand.ncfgr); - /* wait for SRAM_INIT bit to be clear or timeout */ - status = spin_event_timeout( -- !(ifc_in32(&ifc->ifc_nand.ncfgr) -+ !(ifc_in32(&runtime->ifc_nand.ncfgr) - & IFC_NAND_SRAM_INIT_EN), - IFC_TIMEOUT_MSECS, 0); - ---- a/drivers/mtd/nand/fsl_ifc_nand.c -+++ b/drivers/mtd/nand/fsl_ifc_nand.c -@@ -233,7 +233,7 @@ static void set_addr(struct mtd_info *mt - struct nand_chip *chip = mtd->priv; - struct fsl_ifc_mtd *priv = chip->priv; - struct fsl_ifc_ctrl *ctrl = priv->ctrl; -- struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -+ struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; - int buf_num; - - ifc_nand_ctrl->page = page_addr; -@@ -296,7 +296,7 @@ static void fsl_ifc_run_command(struct m - struct fsl_ifc_mtd *priv = chip->priv; - struct fsl_ifc_ctrl *ctrl = priv->ctrl; - struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl; -- struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -+ struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; - u32 eccstat[4]; - int i; - -@@ -372,7 +372,7 @@ static void fsl_ifc_do_read(struct nand_ - { - struct fsl_ifc_mtd *priv = chip->priv; - struct fsl_ifc_ctrl *ctrl = priv->ctrl; -- struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -+ struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; - - /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ - if (mtd->writesize > 512) { -@@ -412,7 +412,7 @@ static void fsl_ifc_cmdfunc(struct mtd_i - struct nand_chip *chip = mtd->priv; - struct fsl_ifc_mtd *priv = chip->priv; - struct fsl_ifc_ctrl *ctrl = priv->ctrl; -- struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -+ struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; - - /* clear the read buffer */ - ifc_nand_ctrl->read_bytes = 0; -@@ -724,7 +724,7 @@ static int fsl_ifc_wait(struct mtd_info - { - struct fsl_ifc_mtd *priv = chip->priv; - struct fsl_ifc_ctrl *ctrl = priv->ctrl; -- struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -+ struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; - u32 nand_fsr; - - /* Use READ_STATUS command, but wait for the device to be ready */ -@@ -826,39 +826,42 @@ static int fsl_ifc_chip_init_tail(struct - static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv) - { - struct fsl_ifc_ctrl *ctrl = priv->ctrl; -- struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -+ struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs; -+ struct fsl_ifc_fcm __iomem *ifc_global = ctrl->gregs; - uint32_t csor = 0, csor_8k = 0, csor_ext = 0; - uint32_t cs = priv->bank; - - /* Save CSOR and CSOR_ext */ -- csor = ifc_in32(&ifc->csor_cs[cs].csor); -- csor_ext = ifc_in32(&ifc->csor_cs[cs].csor_ext); -+ csor = ifc_in32(&ifc_global->csor_cs[cs].csor); -+ csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext); - - /* chage PageSize 8K and SpareSize 1K*/ - csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; -- ifc_out32(csor_8k, &ifc->csor_cs[cs].csor); -- ifc_out32(0x0000400, &ifc->csor_cs[cs].csor_ext); -+ ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor); -+ ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext); - - /* READID */ - ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | -- (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | -- (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT), -- &ifc->ifc_nand.nand_fir0); -+ (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | -+ (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT), -+ &ifc_runtime->ifc_nand.nand_fir0); - ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT, -- &ifc->ifc_nand.nand_fcr0); -- ifc_out32(0x0, &ifc->ifc_nand.row3); -+ &ifc_runtime->ifc_nand.nand_fcr0); -+ ifc_out32(0x0, &ifc_runtime->ifc_nand.row3); - -- ifc_out32(0x0, &ifc->ifc_nand.nand_fbcr); -+ ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr); - - /* Program ROW0/COL0 */ -- ifc_out32(0x0, &ifc->ifc_nand.row0); -- ifc_out32(0x0, &ifc->ifc_nand.col0); -+ ifc_out32(0x0, &ifc_runtime->ifc_nand.row0); -+ ifc_out32(0x0, &ifc_runtime->ifc_nand.col0); - - /* set the chip select for NAND Transaction */ -- ifc_out32(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel); -+ ifc_out32(cs << IFC_NAND_CSEL_SHIFT, -+ &ifc_runtime->ifc_nand.nand_csel); - - /* start read seq */ -- ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt); -+ ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, -+ &ifc_runtime->ifc_nand.nandseq_strt); - - /* wait for command complete flag or timeout */ - wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, -@@ -868,14 +871,15 @@ static void fsl_ifc_sram_init(struct fsl - printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n"); - - /* Restore CSOR and CSOR_ext */ -- ifc_out32(csor, &ifc->csor_cs[cs].csor); -- ifc_out32(csor_ext, &ifc->csor_cs[cs].csor_ext); -+ ifc_out32(csor, &ifc_global->csor_cs[cs].csor); -+ ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext); - } - - static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) - { - struct fsl_ifc_ctrl *ctrl = priv->ctrl; -- struct fsl_ifc_regs __iomem *ifc = ctrl->regs; -+ struct fsl_ifc_fcm __iomem *ifc_global = ctrl->gregs; -+ struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs; - struct nand_chip *chip = &priv->chip; - struct nand_ecclayout *layout; - u32 csor; -@@ -886,7 +890,8 @@ static int fsl_ifc_chip_init(struct fsl_ - - /* fill in nand_chip structure */ - /* set up function call table */ -- if ((ifc_in32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16) -+ if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)) -+ & CSPR_PORT_SIZE_16) - chip->read_byte = fsl_ifc_read_byte16; - else - chip->read_byte = fsl_ifc_read_byte; -@@ -900,13 +905,14 @@ static int fsl_ifc_chip_init(struct fsl_ - chip->bbt_td = &bbt_main_descr; - chip->bbt_md = &bbt_mirror_descr; - -- ifc_out32(0x0, &ifc->ifc_nand.ncfgr); -+ ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr); - - /* set up nand options */ - chip->bbt_options = NAND_BBT_USE_FLASH; - chip->options = NAND_NO_SUBPAGE_WRITE; - -- if (ifc_in32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) { -+ if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr) -+ & CSPR_PORT_SIZE_16) { - chip->read_byte = fsl_ifc_read_byte16; - chip->options |= NAND_BUSWIDTH_16; - } else { -@@ -919,7 +925,7 @@ static int fsl_ifc_chip_init(struct fsl_ - chip->ecc.read_page = fsl_ifc_read_page; - chip->ecc.write_page = fsl_ifc_write_page; - -- csor = ifc_in32(&ifc->csor_cs[priv->bank].csor); -+ csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor); - - /* Hardware generates ECC per 512 Bytes */ - chip->ecc.size = 512; -@@ -1005,10 +1011,10 @@ static int fsl_ifc_chip_remove(struct fs - return 0; - } - --static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank, -+static int match_bank(struct fsl_ifc_fcm __iomem *ifc_global, int bank, - phys_addr_t addr) - { -- u32 cspr = ifc_in32(&ifc->cspr_cs[bank].cspr); -+ u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr); - - if (!(cspr & CSPR_V)) - return 0; -@@ -1022,7 +1028,7 @@ static DEFINE_MUTEX(fsl_ifc_nand_mutex); - - static int fsl_ifc_nand_probe(struct platform_device *dev) - { -- struct fsl_ifc_regs __iomem *ifc; -+ struct fsl_ifc_runtime __iomem *ifc; - struct fsl_ifc_mtd *priv; - struct resource res; - static const char *part_probe_types[] -@@ -1033,9 +1039,9 @@ static int fsl_ifc_nand_probe(struct pla - struct mtd_part_parser_data ppdata; - - ppdata.of_node = dev->dev.of_node; -- if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs) -+ if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs) - return -ENODEV; -- ifc = fsl_ifc_ctrl_dev->regs; -+ ifc = fsl_ifc_ctrl_dev->rregs; - - /* get, allocate and map the memory resource */ - ret = of_address_to_resource(node, 0, &res); -@@ -1046,7 +1052,7 @@ static int fsl_ifc_nand_probe(struct pla - - /* find which chip select it is connected to */ - for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) { -- if (match_bank(ifc, bank, res.start)) -+ if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start)) - break; - } - ---- a/include/linux/fsl_ifc.h -+++ b/include/linux/fsl_ifc.h -@@ -39,6 +39,10 @@ - #define FSL_IFC_VERSION_MASK 0x0F0F0000 - #define FSL_IFC_VERSION_1_0_0 0x01000000 - #define FSL_IFC_VERSION_1_1_0 0x01010000 -+#define FSL_IFC_VERSION_2_0_0 0x02000000 -+ -+#define PGOFFSET_64K (64*1024) -+#define PGOFFSET_4K (4*1024) - - /* - * CSPR - Chip Select Property Register -@@ -725,20 +729,26 @@ struct fsl_ifc_nand { - __be32 nand_evter_en; - u32 res17[0x2]; - __be32 nand_evter_intr_en; -- u32 res18[0x2]; -+ __be32 nand_vol_addr_stat; -+ u32 res18; - __be32 nand_erattr0; - __be32 nand_erattr1; - u32 res19[0x10]; - __be32 nand_fsr; -- u32 res20; -- __be32 nand_eccstat[4]; -- u32 res21[0x20]; -+ u32 res20[0x3]; -+ __be32 nand_eccstat[6]; -+ u32 res21[0x1c]; - __be32 nanndcr; - u32 res22[0x2]; - __be32 nand_autoboot_trgr; - u32 res23; - __be32 nand_mdr; -- u32 res24[0x5C]; -+ u32 res24[0x1C]; -+ __be32 nand_dll_lowcfg0; -+ __be32 nand_dll_lowcfg1; -+ u32 res25; -+ __be32 nand_dll_lowstat; -+ u32 res26[0x3c]; - }; - - /* -@@ -773,13 +783,12 @@ struct fsl_ifc_gpcm { - __be32 gpcm_erattr1; - __be32 gpcm_erattr2; - __be32 gpcm_stat; -- u32 res4[0x1F3]; - }; - - /* - * IFC Controller Registers - */ --struct fsl_ifc_regs { -+struct fsl_ifc_fcm { - __be32 ifc_rev; - u32 res1[0x2]; - struct { -@@ -805,21 +814,26 @@ struct fsl_ifc_regs { - } ftim_cs[FSL_IFC_BANK_COUNT]; - u32 res9[0x30]; - __be32 rb_stat; -- u32 res10[0x2]; -+ __be32 rb_map; -+ __be32 wb_map; - __be32 ifc_gcr; -- u32 res11[0x2]; -+ u32 res10[0x2]; - __be32 cm_evter_stat; -- u32 res12[0x2]; -+ u32 res11[0x2]; - __be32 cm_evter_en; -- u32 res13[0x2]; -+ u32 res12[0x2]; - __be32 cm_evter_intr_en; -- u32 res14[0x2]; -+ u32 res13[0x2]; - __be32 cm_erattr0; - __be32 cm_erattr1; -- u32 res15[0x2]; -+ u32 res14[0x2]; - __be32 ifc_ccr; - __be32 ifc_csr; -- u32 res16[0x2EB]; -+ __be32 ddr_ccr_low; -+}; -+ -+ -+struct fsl_ifc_runtime { - struct fsl_ifc_nand ifc_nand; - struct fsl_ifc_nor ifc_nor; - struct fsl_ifc_gpcm ifc_gpcm; -@@ -833,7 +847,8 @@ extern int fsl_ifc_find(phys_addr_t addr - struct fsl_ifc_ctrl { - /* device info */ - struct device *dev; -- struct fsl_ifc_regs __iomem *regs; -+ struct fsl_ifc_fcm __iomem *gregs; -+ struct fsl_ifc_runtime __iomem *rregs; - int irq; - int nand_irq; - spinlock_t lock; -@@ -846,7 +861,8 @@ struct fsl_ifc_ctrl { - bool little_endian; - #ifdef CONFIG_PM_SLEEP - /*save regs when system goes to deep sleep*/ -- struct fsl_ifc_regs *saved_regs; -+ struct fsl_ifc_fcm *saved_gregs; -+ struct fsl_ifc_runtime *saved_rregs; - #endif - }; - diff --git a/target/linux/layerscape/patches-4.4/4047-drivers-memory-Fix-build-error-for-arm64.patch b/target/linux/layerscape/patches-4.4/4047-drivers-memory-Fix-build-error-for-arm64.patch deleted file mode 100644 index da7f18f1f9..0000000000 --- a/target/linux/layerscape/patches-4.4/4047-drivers-memory-Fix-build-error-for-arm64.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 0ce5d6bd62a9f1dbaa2d39c3535a8bdb31cf7951 Mon Sep 17 00:00:00 2001 -From: Raghav Dogra -Date: Wed, 24 Feb 2016 23:12:58 +0530 -Subject: [PATCH 47/70] drivers/memory: Fix build error for arm64 - -Replace spin_event_timeout() with arch independent macro - -Signed-off-by: Raghav Dogra -Signed-off-by: Prabhakar Kushwaha ---- - drivers/memory/fsl_ifc.c | 16 +++++++++------- - 1 file changed, 9 insertions(+), 7 deletions(-) - ---- a/drivers/memory/fsl_ifc.c -+++ b/drivers/memory/fsl_ifc.c -@@ -39,7 +39,7 @@ - struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev; - EXPORT_SYMBOL(fsl_ifc_ctrl_dev); - #define FSL_IFC_V1_3_0 0x01030000 --#define IFC_TIMEOUT_MSECS 100000 /* 100ms */ -+#define IFC_TIMEOUT_MSECS 1000 /* 1000ms */ - - /* - * convert_ifc_address - convert the base address -@@ -365,7 +365,7 @@ static int fsl_ifc_resume(struct device - struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs; - struct fsl_ifc_fcm *savd_gregs = ctrl->saved_gregs; - struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs; -- uint32_t ver = 0, ncfgr, status, ifc_bank, i; -+ uint32_t ver = 0, ncfgr, timeout, ifc_bank, i; - - /* - * IFC interrupts disabled -@@ -469,12 +469,14 @@ static int fsl_ifc_resume(struct device - ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN, - &runtime->ifc_nand.ncfgr); - /* wait for SRAM_INIT bit to be clear or timeout */ -- status = spin_event_timeout( -- !(ifc_in32(&runtime->ifc_nand.ncfgr) -- & IFC_NAND_SRAM_INIT_EN), -- IFC_TIMEOUT_MSECS, 0); -+ timeout = 10; -+ while ((ifc_in32(&runtime->ifc_nand.ncfgr) & -+ IFC_NAND_SRAM_INIT_EN) && timeout) { -+ mdelay(IFC_TIMEOUT_MSECS); -+ timeout--; -+ } - -- if (!status) -+ if (!timeout) - dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT"); - } - diff --git a/target/linux/layerscape/patches-4.4/4234-fsl-ifc-fix-compilation-error-when-COMPAT-not-enable.patch b/target/linux/layerscape/patches-4.4/4234-fsl-ifc-fix-compilation-error-when-COMPAT-not-enable.patch deleted file mode 100644 index 2097be0c7f..0000000000 --- a/target/linux/layerscape/patches-4.4/4234-fsl-ifc-fix-compilation-error-when-COMPAT-not-enable.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 6183d512e7539033ccfd177d5f5819302d1fda99 Mon Sep 17 00:00:00 2001 -From: Lijun Pan -Date: Wed, 23 Sep 2015 17:06:01 -0500 -Subject: [PATCH 234/238] fsl-ifc: fix compilation error when COMPAT not - enabled - -When CONFIG_COMPAT is not enabled for cases when 64K pages -are enabled, there are a series of include dependencies that -result in some definitions in sched.h that get missed (e.g. - TASK_NORMAL). Explictly include sched.h to resolve this. -(This seems to be what other drivers do as well) - -Signed-off-by: Lijun Pan -[Stuart: updated subject and commit message] -Signed-off-by: Stuart Yoder ---- - drivers/memory/fsl_ifc.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/memory/fsl_ifc.c -+++ b/drivers/memory/fsl_ifc.c -@@ -35,6 +35,7 @@ - #include - #include - #include -+#include - - struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev; - EXPORT_SYMBOL(fsl_ifc_ctrl_dev); diff --git a/target/linux/layerscape/patches-4.4/7014-temp-QE-headers-are-needed-by-FMD.patch b/target/linux/layerscape/patches-4.4/7014-temp-QE-headers-are-needed-by-FMD.patch deleted file mode 100644 index e6962c2665..0000000000 --- a/target/linux/layerscape/patches-4.4/7014-temp-QE-headers-are-needed-by-FMD.patch +++ /dev/null @@ -1,1317 +0,0 @@ -From 03c463111e16f9bae8a659408e5f02333af13239 Mon Sep 17 00:00:00 2001 -From: Madalin Bucur -Date: Tue, 5 Jan 2016 15:41:28 +0200 -Subject: [PATCH 14/70] temp: QE headers are needed by FMD - -Signed-off-by: Madalin Bucur ---- - include/linux/fsl/immap_qe.h | 488 +++++++++++++++++++++++++ - include/linux/fsl/qe.h | 810 ++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 1298 insertions(+) - create mode 100644 include/linux/fsl/immap_qe.h - create mode 100644 include/linux/fsl/qe.h - ---- /dev/null -+++ b/include/linux/fsl/immap_qe.h -@@ -0,0 +1,488 @@ -+/* -+ * QUICC Engine (QE) Internal Memory Map. -+ * The Internal Memory Map for devices with QE on them. This -+ * is the superset of all QE devices (8360, etc.). -+ * Copyright (C) 2006. Freescale Semiconductor, Inc. All rights reserved. -+ * -+ * Authors: -+ * Shlomi Gridish -+ * Li Yang -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+#ifndef _ASM_POWERPC_IMMAP_QE_H -+#define _ASM_POWERPC_IMMAP_QE_H -+#ifdef __KERNEL__ -+ -+#include -+#include -+ -+#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */ -+ -+/* QE I-RAM */ -+struct qe_iram { -+ __be32 iadd; /* I-RAM Address Register */ -+ __be32 idata; /* I-RAM Data Register */ -+ u8 res0[0x04]; -+ __be32 iready; /* I-RAM Ready Register */ -+ u8 res1[0x70]; -+} __packed; -+ -+/* QE Interrupt Controller */ -+struct qe_ic_regs { -+ __be32 qicr; -+ __be32 qivec; -+ __be32 qripnr; -+ __be32 qipnr; -+ __be32 qipxcc; -+ __be32 qipycc; -+ __be32 qipwcc; -+ __be32 qipzcc; -+ __be32 qimr; -+ __be32 qrimr; -+ __be32 qicnr; -+ u8 res0[0x4]; -+ __be32 qiprta; -+ __be32 qiprtb; -+ u8 res1[0x4]; -+ __be32 qricr; -+ u8 res2[0x20]; -+ __be32 qhivec; -+ u8 res3[0x1C]; -+} __packed; -+ -+/* Communications Processor */ -+struct cp_qe { -+ __be32 cecr; /* QE command register */ -+ __be32 ceccr; /* QE controller configuration register */ -+ __be32 cecdr; /* QE command data register */ -+ u8 res0[0xA]; -+ __be16 ceter; /* QE timer event register */ -+ u8 res1[0x2]; -+ __be16 cetmr; /* QE timers mask register */ -+ __be32 cetscr; /* QE time-stamp timer control register */ -+ __be32 cetsr1; /* QE time-stamp register 1 */ -+ __be32 cetsr2; /* QE time-stamp register 2 */ -+ u8 res2[0x8]; -+ __be32 cevter; /* QE virtual tasks event register */ -+ __be32 cevtmr; /* QE virtual tasks mask register */ -+ __be16 cercr; /* QE RAM control register */ -+ u8 res3[0x2]; -+ u8 res4[0x24]; -+ __be16 ceexe1; /* QE external request 1 event register */ -+ u8 res5[0x2]; -+ __be16 ceexm1; /* QE external request 1 mask register */ -+ u8 res6[0x2]; -+ __be16 ceexe2; /* QE external request 2 event register */ -+ u8 res7[0x2]; -+ __be16 ceexm2; /* QE external request 2 mask register */ -+ u8 res8[0x2]; -+ __be16 ceexe3; /* QE external request 3 event register */ -+ u8 res9[0x2]; -+ __be16 ceexm3; /* QE external request 3 mask register */ -+ u8 res10[0x2]; -+ __be16 ceexe4; /* QE external request 4 event register */ -+ u8 res11[0x2]; -+ __be16 ceexm4; /* QE external request 4 mask register */ -+ u8 res12[0x3A]; -+ __be32 ceurnr; /* QE microcode revision number register */ -+ u8 res13[0x244]; -+} __packed; -+ -+/* QE Multiplexer */ -+struct qe_mux { -+ __be32 cmxgcr; /* CMX general clock route register */ -+ __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */ -+ __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */ -+ __be32 cmxsi1syr; /* CMX SI1 SYNC route register */ -+ __be32 cmxucr[4]; /* CMX UCCx clock route registers */ -+ __be32 cmxupcr; /* CMX UPC clock route register */ -+ u8 res0[0x1C]; -+} __packed; -+ -+/* QE Timers */ -+struct qe_timers { -+ u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/ -+ u8 res0[0x3]; -+ u8 gtcfr2; /* Timer 3 and timer 4 global config register*/ -+ u8 res1[0xB]; -+ __be16 gtmdr1; /* Timer 1 mode register */ -+ __be16 gtmdr2; /* Timer 2 mode register */ -+ __be16 gtrfr1; /* Timer 1 reference register */ -+ __be16 gtrfr2; /* Timer 2 reference register */ -+ __be16 gtcpr1; /* Timer 1 capture register */ -+ __be16 gtcpr2; /* Timer 2 capture register */ -+ __be16 gtcnr1; /* Timer 1 counter */ -+ __be16 gtcnr2; /* Timer 2 counter */ -+ __be16 gtmdr3; /* Timer 3 mode register */ -+ __be16 gtmdr4; /* Timer 4 mode register */ -+ __be16 gtrfr3; /* Timer 3 reference register */ -+ __be16 gtrfr4; /* Timer 4 reference register */ -+ __be16 gtcpr3; /* Timer 3 capture register */ -+ __be16 gtcpr4; /* Timer 4 capture register */ -+ __be16 gtcnr3; /* Timer 3 counter */ -+ __be16 gtcnr4; /* Timer 4 counter */ -+ __be16 gtevr1; /* Timer 1 event register */ -+ __be16 gtevr2; /* Timer 2 event register */ -+ __be16 gtevr3; /* Timer 3 event register */ -+ __be16 gtevr4; /* Timer 4 event register */ -+ __be16 gtps; /* Timer 1 prescale register */ -+ u8 res2[0x46]; -+} __packed; -+ -+/* BRG */ -+struct qe_brg { -+ __be32 brgc[16]; /* BRG configuration registers */ -+ u8 res0[0x40]; -+} __packed; -+ -+/* SPI */ -+struct spi { -+ u8 res0[0x20]; -+ __be32 spmode; /* SPI mode register */ -+ u8 res1[0x2]; -+ u8 spie; /* SPI event register */ -+ u8 res2[0x1]; -+ u8 res3[0x2]; -+ u8 spim; /* SPI mask register */ -+ u8 res4[0x1]; -+ u8 res5[0x1]; -+ u8 spcom; /* SPI command register */ -+ u8 res6[0x2]; -+ __be32 spitd; /* SPI transmit data register (cpu mode) */ -+ __be32 spird; /* SPI receive data register (cpu mode) */ -+ u8 res7[0x8]; -+} __packed; -+ -+/* SI */ -+struct si1 { -+ __be16 sixmr1[4]; /* SI1 TDMx (x = A B C D) mode register */ -+ u8 siglmr1_h; /* SI1 global mode register high */ -+ u8 res0[0x1]; -+ u8 sicmdr1_h; /* SI1 command register high */ -+ u8 res2[0x1]; -+ u8 sistr1_h; /* SI1 status register high */ -+ u8 res3[0x1]; -+ __be16 sirsr1_h; /* SI1 RAM shadow address register high */ -+ u8 sitarc1; /* SI1 RAM counter Tx TDMA */ -+ u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ -+ u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ -+ u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ -+ u8 sirarc1; /* SI1 RAM counter Rx TDMA */ -+ u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ -+ u8 sircrc1; /* SI1 RAM counter Rx TDMC */ -+ u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ -+ u8 res4[0x8]; -+ __be16 siemr1; /* SI1 TDME mode register 16 bits */ -+ __be16 sifmr1; /* SI1 TDMF mode register 16 bits */ -+ __be16 sigmr1; /* SI1 TDMG mode register 16 bits */ -+ __be16 sihmr1; /* SI1 TDMH mode register 16 bits */ -+ u8 siglmg1_l; /* SI1 global mode register low 8 bits */ -+ u8 res5[0x1]; -+ u8 sicmdr1_l; /* SI1 command register low 8 bits */ -+ u8 res6[0x1]; -+ u8 sistr1_l; /* SI1 status register low 8 bits */ -+ u8 res7[0x1]; -+ __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/ -+ u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ -+ u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ -+ u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ -+ u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ -+ u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ -+ u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ -+ u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ -+ u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ -+ u8 res8[0x8]; -+ __be32 siml1; /* SI1 multiframe limit register */ -+ u8 siedm1; /* SI1 extended diagnostic mode register */ -+ u8 res9[0xBB]; -+} __packed; -+ -+/* SI Routing Tables */ -+struct sir { -+ u8 tx[0x400]; -+ u8 rx[0x400]; -+ u8 res0[0x800]; -+} __packed; -+ -+/* USB Controller */ -+struct qe_usb_ctlr { -+ u8 usb_usmod; -+ u8 usb_usadr; -+ u8 usb_uscom; -+ u8 res1[1]; -+ __be16 usb_usep[4]; -+ u8 res2[4]; -+ __be16 usb_usber; -+ u8 res3[2]; -+ __be16 usb_usbmr; -+ u8 res4[1]; -+ u8 usb_usbs; -+ __be16 usb_ussft; -+ u8 res5[2]; -+ __be16 usb_usfrn; -+ u8 res6[0x22]; -+} __packed; -+ -+/* MCC */ -+struct qe_mcc { -+ __be32 mcce; /* MCC event register */ -+ __be32 mccm; /* MCC mask register */ -+ __be32 mccf; /* MCC configuration register */ -+ __be32 merl; /* MCC emergency request level register */ -+ u8 res0[0xF0]; -+} __packed; -+ -+/* QE UCC Slow */ -+struct ucc_slow { -+ __be32 gumr_l; /* UCCx general mode register (low) */ -+ __be32 gumr_h; /* UCCx general mode register (high) */ -+ __be16 upsmr; /* UCCx protocol-specific mode register */ -+ u8 res0[0x2]; -+ __be16 utodr; /* UCCx transmit on demand register */ -+ __be16 udsr; /* UCCx data synchronization register */ -+ __be16 ucce; /* UCCx event register */ -+ u8 res1[0x2]; -+ __be16 uccm; /* UCCx mask register */ -+ u8 res2[0x1]; -+ u8 uccs; /* UCCx status register */ -+ u8 res3[0x24]; -+ __be16 utpt; -+ u8 res4[0x52]; -+ u8 guemr; /* UCC general extended mode register */ -+} __packed; -+ -+/* QE UCC Fast */ -+struct ucc_fast { -+ __be32 gumr; /* UCCx general mode register */ -+ __be32 upsmr; /* UCCx protocol-specific mode register */ -+ __be16 utodr; /* UCCx transmit on demand register */ -+ u8 res0[0x2]; -+ __be16 udsr; /* UCCx data synchronization register */ -+ u8 res1[0x2]; -+ __be32 ucce; /* UCCx event register */ -+ __be32 uccm; /* UCCx mask register */ -+ u8 uccs; /* UCCx status register */ -+ u8 res2[0x7]; -+ __be32 urfb; /* UCC receive FIFO base */ -+ __be16 urfs; /* UCC receive FIFO size */ -+ u8 res3[0x2]; -+ __be16 urfet; /* UCC receive FIFO emergency threshold */ -+ __be16 urfset; /* UCC receive FIFO special emergency -+ threshold */ -+ __be32 utfb; /* UCC transmit FIFO base */ -+ __be16 utfs; /* UCC transmit FIFO size */ -+ u8 res4[0x2]; -+ __be16 utfet; /* UCC transmit FIFO emergency threshold */ -+ u8 res5[0x2]; -+ __be16 utftt; /* UCC transmit FIFO transmit threshold */ -+ u8 res6[0x2]; -+ __be16 utpt; /* UCC transmit polling timer */ -+ u8 res7[0x2]; -+ __be32 urtry; /* UCC retry counter register */ -+ u8 res8[0x4C]; -+ u8 guemr; /* UCC general extended mode register */ -+} __packed; -+ -+struct ucc { -+ union { -+ struct ucc_slow slow; -+ struct ucc_fast fast; -+ u8 res[0x200]; /* UCC blocks are 512 bytes each */ -+ }; -+} __packed; -+ -+/* MultiPHY UTOPIA POS Controllers (UPC) */ -+struct upc { -+ __be32 upgcr; /* UTOPIA/POS general configuration register */ -+ __be32 uplpa; /* UTOPIA/POS last PHY address */ -+ __be32 uphec; /* ATM HEC register */ -+ __be32 upuc; /* UTOPIA/POS UCC configuration */ -+ __be32 updc1; /* UTOPIA/POS device 1 configuration */ -+ __be32 updc2; /* UTOPIA/POS device 2 configuration */ -+ __be32 updc3; /* UTOPIA/POS device 3 configuration */ -+ __be32 updc4; /* UTOPIA/POS device 4 configuration */ -+ __be32 upstpa; /* UTOPIA/POS STPA threshold */ -+ u8 res0[0xC]; -+ __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */ -+ __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */ -+ __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */ -+ __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */ -+ __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */ -+ __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */ -+ __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */ -+ __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */ -+ __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */ -+ __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */ -+ __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */ -+ __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */ -+ __be32 upde1; /* UTOPIA/POS device 1 event */ -+ __be32 upde2; /* UTOPIA/POS device 2 event */ -+ __be32 upde3; /* UTOPIA/POS device 3 event */ -+ __be32 upde4; /* UTOPIA/POS device 4 event */ -+ __be16 uprp1; -+ __be16 uprp2; -+ __be16 uprp3; -+ __be16 uprp4; -+ u8 res1[0x8]; -+ __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */ -+ __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */ -+ __be16 uptirr1_2; /* Device 1 transmit internal rate 2 */ -+ __be16 uptirr1_3; /* Device 1 transmit internal rate 3 */ -+ __be16 uptirr2_0; /* Device 2 transmit internal rate 0 */ -+ __be16 uptirr2_1; /* Device 2 transmit internal rate 1 */ -+ __be16 uptirr2_2; /* Device 2 transmit internal rate 2 */ -+ __be16 uptirr2_3; /* Device 2 transmit internal rate 3 */ -+ __be16 uptirr3_0; /* Device 3 transmit internal rate 0 */ -+ __be16 uptirr3_1; /* Device 3 transmit internal rate 1 */ -+ __be16 uptirr3_2; /* Device 3 transmit internal rate 2 */ -+ __be16 uptirr3_3; /* Device 3 transmit internal rate 3 */ -+ __be16 uptirr4_0; /* Device 4 transmit internal rate 0 */ -+ __be16 uptirr4_1; /* Device 4 transmit internal rate 1 */ -+ __be16 uptirr4_2; /* Device 4 transmit internal rate 2 */ -+ __be16 uptirr4_3; /* Device 4 transmit internal rate 3 */ -+ __be32 uper1; /* Device 1 port enable register */ -+ __be32 uper2; /* Device 2 port enable register */ -+ __be32 uper3; /* Device 3 port enable register */ -+ __be32 uper4; /* Device 4 port enable register */ -+ u8 res2[0x150]; -+} __packed; -+ -+/* SDMA */ -+struct sdma { -+ __be32 sdsr; /* Serial DMA status register */ -+ __be32 sdmr; /* Serial DMA mode register */ -+ __be32 sdtr1; /* SDMA system bus threshold register */ -+ __be32 sdtr2; /* SDMA secondary bus threshold register */ -+ __be32 sdhy1; /* SDMA system bus hysteresis register */ -+ __be32 sdhy2; /* SDMA secondary bus hysteresis register */ -+ __be32 sdta1; /* SDMA system bus address register */ -+ __be32 sdta2; /* SDMA secondary bus address register */ -+ __be32 sdtm1; /* SDMA system bus MSNUM register */ -+ __be32 sdtm2; /* SDMA secondary bus MSNUM register */ -+ u8 res0[0x10]; -+ __be32 sdaqr; /* SDMA address bus qualify register */ -+ __be32 sdaqmr; /* SDMA address bus qualify mask register */ -+ u8 res1[0x4]; -+ __be32 sdebcr; /* SDMA CAM entries base register */ -+ u8 res2[0x38]; -+} __packed; -+ -+/* Debug Space */ -+struct dbg { -+ __be32 bpdcr; /* Breakpoint debug command register */ -+ __be32 bpdsr; /* Breakpoint debug status register */ -+ __be32 bpdmr; /* Breakpoint debug mask register */ -+ __be32 bprmrr0; /* Breakpoint request mode risc register 0 */ -+ __be32 bprmrr1; /* Breakpoint request mode risc register 1 */ -+ u8 res0[0x8]; -+ __be32 bprmtr0; /* Breakpoint request mode trb register 0 */ -+ __be32 bprmtr1; /* Breakpoint request mode trb register 1 */ -+ u8 res1[0x8]; -+ __be32 bprmir; /* Breakpoint request mode immediate register */ -+ __be32 bprmsr; /* Breakpoint request mode serial register */ -+ __be32 bpemr; /* Breakpoint exit mode register */ -+ u8 res2[0x48]; -+} __packed; -+ -+/* -+ * RISC Special Registers (Trap and Breakpoint). These are described in -+ * the QE Developer's Handbook. -+ */ -+struct rsp { -+ __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */ -+ u8 res0[64]; -+ __be32 ibcr0; -+ __be32 ibs0; -+ __be32 ibcnr0; -+ u8 res1[4]; -+ __be32 ibcr1; -+ __be32 ibs1; -+ __be32 ibcnr1; -+ __be32 npcr; -+ __be32 dbcr; -+ __be32 dbar; -+ __be32 dbamr; -+ __be32 dbsr; -+ __be32 dbcnr; -+ u8 res2[12]; -+ __be32 dbdr_h; -+ __be32 dbdr_l; -+ __be32 dbdmr_h; -+ __be32 dbdmr_l; -+ __be32 bsr; -+ __be32 bor; -+ __be32 bior; -+ u8 res3[4]; -+ __be32 iatr[4]; -+ __be32 eccr; /* Exception control configuration register */ -+ __be32 eicr; -+ u8 res4[0x100-0xf8]; -+} __packed; -+ -+struct qe_immap { -+ struct qe_iram iram; /* I-RAM */ -+ struct qe_ic_regs ic; /* Interrupt Controller */ -+ struct cp_qe cp; /* Communications Processor */ -+ struct qe_mux qmx; /* QE Multiplexer */ -+ struct qe_timers qet; /* QE Timers */ -+ struct spi spi[0x2]; /* spi */ -+ struct qe_mcc mcc; /* mcc */ -+ struct qe_brg brg; /* brg */ -+ struct qe_usb_ctlr usb; /* USB */ -+ struct si1 si1; /* SI */ -+ u8 res11[0x800]; -+ struct sir sir; /* SI Routing Tables */ -+ struct ucc ucc1; /* ucc1 */ -+ struct ucc ucc3; /* ucc3 */ -+ struct ucc ucc5; /* ucc5 */ -+ struct ucc ucc7; /* ucc7 */ -+ u8 res12[0x600]; -+ struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/ -+ struct ucc ucc2; /* ucc2 */ -+ struct ucc ucc4; /* ucc4 */ -+ struct ucc ucc6; /* ucc6 */ -+ struct ucc ucc8; /* ucc8 */ -+ u8 res13[0x600]; -+ struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/ -+ struct sdma sdma; /* SDMA */ -+ struct dbg dbg; /* 0x104080 - 0x1040FF -+ Debug Space */ -+ struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF -+ RISC Special Registers -+ (Trap and Breakpoint) */ -+ u8 res14[0x300]; /* 0x104300 - 0x1045FF */ -+ u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */ -+ u8 res16[0x8000]; /* 0x108000 - 0x110000 */ -+ u8 muram[0xC000]; /* 0x110000 - 0x11C000 -+ Multi-user RAM */ -+ u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ -+ u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ -+} __packed; -+ -+extern struct qe_immap __iomem *qe_immr; -+extern phys_addr_t get_qe_base(void); -+ -+/* -+ * Returns the offset within the QE address space of the given pointer. -+ * -+ * Note that the QE does not support 36-bit physical addresses, so if -+ * get_qe_base() returns a number above 4GB, the caller will probably fail. -+ */ -+static inline phys_addr_t immrbar_virt_to_phys(void *address) -+{ -+ void *q = (void *)qe_immr; -+ -+ /* Is it a MURAM address? */ -+ if ((address >= q) && (address < (q + QE_IMMAP_SIZE))) -+ return get_qe_base() + (address - q); -+ -+ /* It's an address returned by kmalloc */ -+ return virt_to_phys(address); -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* _ASM_POWERPC_IMMAP_QE_H */ ---- /dev/null -+++ b/include/linux/fsl/qe.h -@@ -0,0 +1,810 @@ -+/* -+ * Copyright (C) 2006, 2012 Freescale Semiconductor, Inc. All rights reserved. -+ * -+ * Authors: Shlomi Gridish -+ * Li Yang -+ * -+ * Description: -+ * QUICC Engine (QE) external definitions and structure. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+#ifndef _ASM_POWERPC_QE_H -+#define _ASM_POWERPC_QE_H -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */ -+#define QE_NUM_OF_BRGS 16 -+#define QE_NUM_OF_PORTS 1024 -+ -+/* Memory partitions -+*/ -+#define MEM_PART_SYSTEM 0 -+#define MEM_PART_SECONDARY 1 -+#define MEM_PART_MURAM 2 -+ -+extern int siram_init_flag; -+ -+/* Clocks and BRGs */ -+enum qe_clock { -+ QE_CLK_NONE = 0, -+ QE_BRG1, /* Baud Rate Generator 1 */ -+ QE_BRG2, /* Baud Rate Generator 2 */ -+ QE_BRG3, /* Baud Rate Generator 3 */ -+ QE_BRG4, /* Baud Rate Generator 4 */ -+ QE_BRG5, /* Baud Rate Generator 5 */ -+ QE_BRG6, /* Baud Rate Generator 6 */ -+ QE_BRG7, /* Baud Rate Generator 7 */ -+ QE_BRG8, /* Baud Rate Generator 8 */ -+ QE_BRG9, /* Baud Rate Generator 9 */ -+ QE_BRG10, /* Baud Rate Generator 10 */ -+ QE_BRG11, /* Baud Rate Generator 11 */ -+ QE_BRG12, /* Baud Rate Generator 12 */ -+ QE_BRG13, /* Baud Rate Generator 13 */ -+ QE_BRG14, /* Baud Rate Generator 14 */ -+ QE_BRG15, /* Baud Rate Generator 15 */ -+ QE_BRG16, /* Baud Rate Generator 16 */ -+ QE_CLK1, /* Clock 1 */ -+ QE_CLK2, /* Clock 2 */ -+ QE_CLK3, /* Clock 3 */ -+ QE_CLK4, /* Clock 4 */ -+ QE_CLK5, /* Clock 5 */ -+ QE_CLK6, /* Clock 6 */ -+ QE_CLK7, /* Clock 7 */ -+ QE_CLK8, /* Clock 8 */ -+ QE_CLK9, /* Clock 9 */ -+ QE_CLK10, /* Clock 10 */ -+ QE_CLK11, /* Clock 11 */ -+ QE_CLK12, /* Clock 12 */ -+ QE_CLK13, /* Clock 13 */ -+ QE_CLK14, /* Clock 14 */ -+ QE_CLK15, /* Clock 15 */ -+ QE_CLK16, /* Clock 16 */ -+ QE_CLK17, /* Clock 17 */ -+ QE_CLK18, /* Clock 18 */ -+ QE_CLK19, /* Clock 19 */ -+ QE_CLK20, /* Clock 20 */ -+ QE_CLK21, /* Clock 21 */ -+ QE_CLK22, /* Clock 22 */ -+ QE_CLK23, /* Clock 23 */ -+ QE_CLK24, /* Clock 24 */ -+ QE_RSYNC_PIN, /* RSYNC from pin */ -+ QE_TSYNC_PIN, /* TSYNC from pin */ -+ QE_CLK_DUMMY -+}; -+ -+static inline bool qe_clock_is_brg(enum qe_clock clk) -+{ -+ return clk >= QE_BRG1 && clk <= QE_BRG16; -+} -+ -+extern spinlock_t cmxgcr_lock; -+ -+/* Export QE common operations */ -+#ifdef CONFIG_QUICC_ENGINE -+extern void qe_reset(void); -+#else -+static inline void qe_reset(void) {} -+#endif -+ -+/* QE PIO */ -+#define QE_PIO_PINS 32 -+ -+struct qe_pio_regs { -+ __be32 cpodr; /* Open drain register */ -+ __be32 cpdata; /* Data register */ -+ __be32 cpdir1; /* Direction register */ -+ __be32 cpdir2; /* Direction register */ -+ __be32 cppar1; /* Pin assignment register */ -+ __be32 cppar2; /* Pin assignment register */ -+#ifdef CONFIG_PPC_85xx -+ u8 pad[8]; -+#endif -+}; -+ -+#define QE_PIO_DIR_IN 2 -+#define QE_PIO_DIR_OUT 1 -+extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, -+ int dir, int open_drain, int assignment, -+ int has_irq); -+#ifdef CONFIG_QUICC_ENGINE -+extern int par_io_init(struct device_node *np); -+extern int par_io_of_config(struct device_node *np); -+extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, -+ int assignment, int has_irq); -+extern int par_io_data_set(u8 port, u8 pin, u8 val); -+#else -+static inline int par_io_init(struct device_node *np) { return -ENOSYS; } -+static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; } -+static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, -+ int assignment, int has_irq) { return -ENOSYS; } -+static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } -+#endif /* CONFIG_QUICC_ENGINE */ -+ -+/* -+ * Pin multiplexing functions. -+ */ -+struct qe_pin; -+#ifdef CONFIG_QE_GPIO -+extern struct qe_pin *qe_pin_request(struct device_node *np, int index); -+extern void qe_pin_free(struct qe_pin *qe_pin); -+extern void qe_pin_set_gpio(struct qe_pin *qe_pin); -+extern void qe_pin_set_dedicated(struct qe_pin *pin); -+#else -+static inline struct qe_pin *qe_pin_request(struct device_node *np, int index) -+{ -+ return ERR_PTR(-ENOSYS); -+} -+static inline void qe_pin_free(struct qe_pin *qe_pin) {} -+static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {} -+static inline void qe_pin_set_dedicated(struct qe_pin *pin) {} -+#endif /* CONFIG_QE_GPIO */ -+ -+#ifdef CONFIG_QUICC_ENGINE -+int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); -+#else -+static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, -+ u32 cmd_input) -+{ -+ return -ENOSYS; -+} -+#endif /* CONFIG_QUICC_ENGINE */ -+ -+/* QE internal API */ -+enum qe_clock qe_clock_source(const char *source); -+unsigned int qe_get_brg_clk(void); -+int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); -+int qe_get_snum(void); -+void qe_put_snum(u8 snum); -+unsigned int qe_get_num_of_risc(void); -+unsigned int qe_get_num_of_snums(void); -+ -+static inline int qe_alive_during_sleep(void) -+{ -+ /* -+ * MPC8568E reference manual says: -+ * -+ * "...power down sequence waits for all I/O interfaces to become idle. -+ * In some applications this may happen eventually without actively -+ * shutting down interfaces, but most likely, software will have to -+ * take steps to shut down the eTSEC, QUICC Engine Block, and PCI -+ * interfaces before issuing the command (either the write to the core -+ * MSR[WE] as described above or writing to POWMGTCSR) to put the -+ * device into sleep state." -+ * -+ * MPC8569E reference manual has a similar paragraph. -+ */ -+#ifdef CONFIG_PPC_85xx -+ return 0; -+#else -+ return 1; -+#endif -+} -+ -+int qe_muram_init(void); -+ -+#if defined(CONFIG_QUICC_ENGINE) -+unsigned long qe_muram_alloc(unsigned long size, unsigned long align); -+int qe_muram_free(unsigned long offset); -+unsigned long qe_muram_alloc_fixed(unsigned long offset, unsigned long size); -+void __iomem *qe_muram_addr(unsigned long offset); -+unsigned long qe_muram_offset(void __iomem *addr); -+dma_addr_t qe_muram_dma(void __iomem *addr); -+#else -+static inline unsigned long qe_muram_alloc(unsigned long size, -+ unsigned long align) -+{ -+ return -ENOSYS; -+} -+ -+static inline int qe_muram_free(unsigned long offset) -+{ -+ return -ENOSYS; -+} -+ -+static inline unsigned long qe_muram_alloc_fixed(unsigned long offset, -+ unsigned long size) -+{ -+ return -ENOSYS; -+} -+ -+static inline void __iomem *qe_muram_addr(unsigned long offset) -+{ -+ return NULL; -+} -+ -+static inline unsigned long qe_muram_offset(void __iomem *addr) -+{ -+ return -ENOSYS; -+} -+ -+static inline dma_addr_t qe_muram_dma(void __iomem *addr) -+{ -+ return 0; -+} -+#endif /* defined(CONFIG_QUICC_ENGINE) */ -+ -+/* Structure that defines QE firmware binary files. -+ * -+ * See Documentation/powerpc/qe_firmware.txt for a description of these -+ * fields. -+ */ -+struct qe_firmware { -+ struct qe_header { -+ __be32 length; /* Length of the entire structure, in bytes */ -+ u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ -+ u8 version; /* Version of this layout. First ver is '1' */ -+ } header; -+ u8 id[62]; /* Null-terminated identifier string */ -+ u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ -+ u8 count; /* Number of microcode[] structures */ -+ struct { -+ __be16 model; /* The SOC model */ -+ u8 major; /* The SOC revision major */ -+ u8 minor; /* The SOC revision minor */ -+ } __packed soc; -+ u8 padding[4]; /* Reserved, for alignment */ -+ __be64 extended_modes; /* Extended modes */ -+ __be32 vtraps[8]; /* Virtual trap addresses */ -+ u8 reserved[4]; /* Reserved, for future expansion */ -+ struct qe_microcode { -+ u8 id[32]; /* Null-terminated identifier */ -+ __be32 traps[16]; /* Trap addresses, 0 == ignore */ -+ __be32 eccr; /* The value for the ECCR register */ -+ __be32 iram_offset; /* Offset into I-RAM for the code */ -+ __be32 count; /* Number of 32-bit words of the code */ -+ __be32 code_offset; /* Offset of the actual microcode */ -+ u8 major; /* The microcode version major */ -+ u8 minor; /* The microcode version minor */ -+ u8 revision; /* The microcode version revision */ -+ u8 padding; /* Reserved, for alignment */ -+ u8 reserved[4]; /* Reserved, for future expansion */ -+ } __packed microcode[1]; -+ /* All microcode binaries should be located here */ -+ /* CRC32 should be located here, after the microcode binaries */ -+} __packed; -+ -+struct qe_firmware_info { -+ char id[64]; /* Firmware name */ -+ u32 vtraps[8]; /* Virtual trap addresses */ -+ u64 extended_modes; /* Extended modes */ -+}; -+ -+#ifdef CONFIG_QUICC_ENGINE -+/* Upload a firmware to the QE */ -+int qe_upload_firmware(const struct qe_firmware *firmware); -+#else -+static inline int qe_upload_firmware(const struct qe_firmware *firmware) -+{ -+ return -ENOSYS; -+} -+#endif /* CONFIG_QUICC_ENGINE */ -+ -+/* Obtain information on the uploaded firmware */ -+struct qe_firmware_info *qe_get_firmware_info(void); -+ -+/* QE USB */ -+int qe_usb_clock_set(enum qe_clock clk, int rate); -+ -+/* Buffer descriptors */ -+struct qe_bd { -+ __be16 status; -+ __be16 length; -+ __be32 buf; -+} __packed; -+ -+#define BD_STATUS_MASK 0xffff0000 -+#define BD_LENGTH_MASK 0x0000ffff -+ -+/* Buffer descriptor control/status used by serial -+ */ -+ -+#define BD_SC_EMPTY (0x8000) /* Receive is empty */ -+#define BD_SC_READY (0x8000) /* Transmit is ready */ -+#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */ -+#define BD_SC_INTRPT (0x1000) /* Interrupt on change */ -+#define BD_SC_LAST (0x0800) /* Last buffer in frame */ -+#define BD_SC_TC (0x0400) /* Transmit CRC */ -+#define BD_SC_CM (0x0200) /* Continuous mode */ -+#define BD_SC_ID (0x0100) /* Rec'd too many idles */ -+#define BD_SC_P (0x0100) /* xmt preamble */ -+#define BD_SC_BR (0x0020) /* Break received */ -+#define BD_SC_FR (0x0010) /* Framing error */ -+#define BD_SC_PR (0x0008) /* Parity error */ -+#define BD_SC_NAK (0x0004) /* NAK - did not respond */ -+#define BD_SC_OV (0x0002) /* Overrun */ -+#define BD_SC_UN (0x0002) /* Underrun */ -+#define BD_SC_CD (0x0001) /* */ -+#define BD_SC_CL (0x0001) /* Collision */ -+ -+/* Alignment */ -+#define QE_INTR_TABLE_ALIGN 16 /* ??? */ -+#define QE_ALIGNMENT_OF_BD 8 -+#define QE_ALIGNMENT_OF_PRAM 64 -+ -+/* RISC allocation */ -+#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ -+#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ -+#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ -+#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ -+#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ -+ QE_RISC_ALLOCATION_RISC2) -+#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ -+ QE_RISC_ALLOCATION_RISC2 | \ -+ QE_RISC_ALLOCATION_RISC3 | \ -+ QE_RISC_ALLOCATION_RISC4) -+ -+/* QE extended filtering Table Lookup Key Size */ -+enum qe_fltr_tbl_lookup_key_size { -+ QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES -+ = 0x3f, /* LookupKey parsed by the Generate LookupKey -+ CMD is truncated to 8 bytes */ -+ QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES -+ = 0x5f, /* LookupKey parsed by the Generate LookupKey -+ CMD is truncated to 16 bytes */ -+}; -+ -+/* QE FLTR extended filtering Largest External Table Lookup Key Size */ -+enum qe_fltr_largest_external_tbl_lookup_key_size { -+ QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE -+ = 0x0,/* not used */ -+ QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES -+ = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */ -+ QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES -+ = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */ -+}; -+ -+/* structure representing QE parameter RAM */ -+struct qe_timer_tables { -+ u16 tm_base; /* QE timer table base adr */ -+ u16 tm_ptr; /* QE timer table pointer */ -+ u16 r_tmr; /* QE timer mode register */ -+ u16 r_tmv; /* QE timer valid register */ -+ u32 tm_cmd; /* QE timer cmd register */ -+ u32 tm_cnt; /* QE timer internal cnt */ -+} __packed; -+ -+#define QE_FLTR_TAD_SIZE 8 -+ -+/* QE extended filtering Termination Action Descriptor (TAD) */ -+struct qe_fltr_tad { -+ u8 serialized[QE_FLTR_TAD_SIZE]; -+} __packed; -+ -+/* Communication Direction */ -+enum comm_dir { -+ COMM_DIR_NONE = 0, -+ COMM_DIR_RX = 1, -+ COMM_DIR_TX = 2, -+ COMM_DIR_RX_AND_TX = 3 -+}; -+ -+/* QE CMXUCR Registers. -+ * There are two UCCs represented in each of the four CMXUCR registers. -+ * These values are for the UCC in the LSBs -+ */ -+#define QE_CMXUCR_MII_ENET_MNG 0x00007000 -+#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12 -+#define QE_CMXUCR_GRANT 0x00008000 -+#define QE_CMXUCR_TSA 0x00004000 -+#define QE_CMXUCR_BKPT 0x00000100 -+#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F -+ -+/* QE CMXGCR Registers. -+*/ -+#define QE_CMXGCR_MII_ENET_MNG 0x00007000 -+#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 -+#define QE_CMXGCR_USBCS 0x0000000f -+#define QE_CMXGCR_USBCS_CLK3 0x1 -+#define QE_CMXGCR_USBCS_CLK5 0x2 -+#define QE_CMXGCR_USBCS_CLK7 0x3 -+#define QE_CMXGCR_USBCS_CLK9 0x4 -+#define QE_CMXGCR_USBCS_CLK13 0x5 -+#define QE_CMXGCR_USBCS_CLK17 0x6 -+#define QE_CMXGCR_USBCS_CLK19 0x7 -+#define QE_CMXGCR_USBCS_CLK21 0x8 -+#define QE_CMXGCR_USBCS_BRG9 0x9 -+#define QE_CMXGCR_USBCS_BRG10 0xa -+ -+/* QE CECR Commands. -+*/ -+#define QE_CR_FLG 0x00010000 -+#define QE_RESET 0x80000000 -+#define QE_INIT_TX_RX 0x00000000 -+#define QE_INIT_RX 0x00000001 -+#define QE_INIT_TX 0x00000002 -+#define QE_ENTER_HUNT_MODE 0x00000003 -+#define QE_STOP_TX 0x00000004 -+#define QE_GRACEFUL_STOP_TX 0x00000005 -+#define QE_RESTART_TX 0x00000006 -+#define QE_CLOSE_RX_BD 0x00000007 -+#define QE_SWITCH_COMMAND 0x00000007 -+#define QE_SET_GROUP_ADDRESS 0x00000008 -+#define QE_START_IDMA 0x00000009 -+#define QE_MCC_STOP_RX 0x00000009 -+#define QE_ATM_TRANSMIT 0x0000000a -+#define QE_HPAC_CLEAR_ALL 0x0000000b -+#define QE_GRACEFUL_STOP_RX 0x0000001a -+#define QE_RESTART_RX 0x0000001b -+#define QE_HPAC_SET_PRIORITY 0x0000010b -+#define QE_HPAC_STOP_TX 0x0000020b -+#define QE_HPAC_STOP_RX 0x0000030b -+#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b -+#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b -+#define QE_HPAC_START_TX 0x0000060b -+#define QE_HPAC_START_RX 0x0000070b -+#define QE_USB_STOP_TX 0x0000000a -+#define QE_USB_RESTART_TX 0x0000000c -+#define QE_QMC_STOP_TX 0x0000000c -+#define QE_QMC_STOP_RX 0x0000000d -+#define QE_SS7_SU_FIL_RESET 0x0000000e -+/* jonathbr added from here down for 83xx */ -+#define QE_RESET_BCS 0x0000000a -+#define QE_MCC_INIT_TX_RX_16 0x00000003 -+#define QE_MCC_STOP_TX 0x00000004 -+#define QE_MCC_INIT_TX_1 0x00000005 -+#define QE_MCC_INIT_RX_1 0x00000006 -+#define QE_MCC_RESET 0x00000007 -+#define QE_SET_TIMER 0x00000008 -+#define QE_RANDOM_NUMBER 0x0000000c -+#define QE_ATM_MULTI_THREAD_INIT 0x00000011 -+#define QE_ASSIGN_PAGE 0x00000012 -+#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013 -+#define QE_START_FLOW_CONTROL 0x00000014 -+#define QE_STOP_FLOW_CONTROL 0x00000015 -+#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 -+ -+#define QE_ASSIGN_RISC 0x00000010 -+#define QE_CR_MCN_NORMAL_SHIFT 6 -+#define QE_CR_MCN_USB_SHIFT 4 -+#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8 -+#define QE_CR_SNUM_SHIFT 17 -+ -+/* QE CECR Sub Block - sub block of QE command. -+*/ -+#define QE_CR_SUBBLOCK_INVALID 0x00000000 -+#define QE_CR_SUBBLOCK_USB 0x03200000 -+#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 -+#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 -+#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 -+#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 -+#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 -+#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 -+#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 -+#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 -+#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 -+#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 -+#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 -+#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 -+#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 -+#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 -+#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 -+#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 -+#define QE_CR_SUBBLOCK_MCC1 0x03800000 -+#define QE_CR_SUBBLOCK_MCC2 0x03a00000 -+#define QE_CR_SUBBLOCK_MCC3 0x03000000 -+#define QE_CR_SUBBLOCK_IDMA1 0x02800000 -+#define QE_CR_SUBBLOCK_IDMA2 0x02a00000 -+#define QE_CR_SUBBLOCK_IDMA3 0x02c00000 -+#define QE_CR_SUBBLOCK_IDMA4 0x02e00000 -+#define QE_CR_SUBBLOCK_HPAC 0x01e00000 -+#define QE_CR_SUBBLOCK_SPI1 0x01400000 -+#define QE_CR_SUBBLOCK_SPI2 0x01600000 -+#define QE_CR_SUBBLOCK_RAND 0x01c00000 -+#define QE_CR_SUBBLOCK_TIMER 0x01e00000 -+#define QE_CR_SUBBLOCK_GENERAL 0x03c00000 -+ -+/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */ -+#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ -+#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 -+#define QE_CR_PROTOCOL_QMC 0x02 -+#define QE_CR_PROTOCOL_UART 0x04 -+#define QE_CR_PROTOCOL_ATM_POS 0x0A -+#define QE_CR_PROTOCOL_ETHERNET 0x0C -+#define QE_CR_PROTOCOL_L2_SWITCH 0x0D -+ -+/* BRG configuration register */ -+#define QE_BRGC_ENABLE 0x00010000 -+#define QE_BRGC_DIVISOR_SHIFT 1 -+#define QE_BRGC_DIVISOR_MAX 0xFFF -+#define QE_BRGC_DIV16 1 -+ -+/* QE Timers registers */ -+#define QE_GTCFR1_PCAS 0x80 -+#define QE_GTCFR1_STP2 0x20 -+#define QE_GTCFR1_RST2 0x10 -+#define QE_GTCFR1_GM2 0x08 -+#define QE_GTCFR1_GM1 0x04 -+#define QE_GTCFR1_STP1 0x02 -+#define QE_GTCFR1_RST1 0x01 -+ -+/* SDMA registers */ -+#define QE_SDSR_BER1 0x02000000 -+#define QE_SDSR_BER2 0x01000000 -+ -+#define QE_SDMR_GLB_1_MSK 0x80000000 -+#define QE_SDMR_ADR_SEL 0x20000000 -+#define QE_SDMR_BER1_MSK 0x02000000 -+#define QE_SDMR_BER2_MSK 0x01000000 -+#define QE_SDMR_EB1_MSK 0x00800000 -+#define QE_SDMR_ER1_MSK 0x00080000 -+#define QE_SDMR_ER2_MSK 0x00040000 -+#define QE_SDMR_CEN_MASK 0x0000E000 -+#define QE_SDMR_SBER_1 0x00000200 -+#define QE_SDMR_SBER_2 0x00000200 -+#define QE_SDMR_EB1_PR_MASK 0x000000C0 -+#define QE_SDMR_ER1_PR 0x00000008 -+ -+#define QE_SDMR_CEN_SHIFT 13 -+#define QE_SDMR_EB1_PR_SHIFT 6 -+ -+#define QE_SDTM_MSNUM_SHIFT 24 -+ -+#define QE_SDEBCR_BA_MASK 0x01FFFFFF -+ -+/* Communication Processor */ -+#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ -+#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ -+#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ -+ -+/* I-RAM */ -+#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ -+#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ -+#define QE_IRAM_READY 0x80000000 /* Ready */ -+ -+/* UPC */ -+#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ -+#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ -+#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ -+#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */ -+#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ -+ -+/* UCC GUEMR register */ -+#define UCC_GUEMR_MODE_MASK_RX 0x02 -+#define UCC_GUEMR_MODE_FAST_RX 0x02 -+#define UCC_GUEMR_MODE_SLOW_RX 0x00 -+#define UCC_GUEMR_MODE_MASK_TX 0x01 -+#define UCC_GUEMR_MODE_FAST_TX 0x01 -+#define UCC_GUEMR_MODE_SLOW_TX 0x00 -+#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX) -+#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but -+ must be set 1 */ -+ -+/* structure representing UCC SLOW parameter RAM */ -+struct ucc_slow_pram { -+ __be16 rbase; /* RX BD base address */ -+ __be16 tbase; /* TX BD base address */ -+ u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */ -+ u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */ -+ __be16 mrblr; /* Rx buffer length */ -+ __be32 rstate; /* Rx internal state */ -+ __be32 rptr; /* Rx internal data pointer */ -+ __be16 rbptr; /* rb BD Pointer */ -+ __be16 rcount; /* Rx internal byte count */ -+ __be32 rtemp; /* Rx temp */ -+ __be32 tstate; /* Tx internal state */ -+ __be32 tptr; /* Tx internal data pointer */ -+ __be16 tbptr; /* Tx BD pointer */ -+ __be16 tcount; /* Tx byte count */ -+ __be32 ttemp; /* Tx temp */ -+ __be32 rcrc; /* temp receive CRC */ -+ __be32 tcrc; /* temp transmit CRC */ -+} __packed; -+ -+/* General UCC SLOW Mode Register (GUMRH & GUMRL) */ -+#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000 -+#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000 -+#define UCC_SLOW_GUMR_H_REVD 0x00002000 -+#define UCC_SLOW_GUMR_H_TRX 0x00001000 -+#define UCC_SLOW_GUMR_H_TTX 0x00000800 -+#define UCC_SLOW_GUMR_H_CDP 0x00000400 -+#define UCC_SLOW_GUMR_H_CTSP 0x00000200 -+#define UCC_SLOW_GUMR_H_CDS 0x00000100 -+#define UCC_SLOW_GUMR_H_CTSS 0x00000080 -+#define UCC_SLOW_GUMR_H_TFL 0x00000040 -+#define UCC_SLOW_GUMR_H_RFW 0x00000020 -+#define UCC_SLOW_GUMR_H_TXSY 0x00000010 -+#define UCC_SLOW_GUMR_H_4SYNC 0x00000004 -+#define UCC_SLOW_GUMR_H_8SYNC 0x00000008 -+#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c -+#define UCC_SLOW_GUMR_H_RTSM 0x00000002 -+#define UCC_SLOW_GUMR_H_RSYN 0x00000001 -+ -+#define UCC_SLOW_GUMR_L_TCI 0x10000000 -+#define UCC_SLOW_GUMR_L_RINV 0x02000000 -+#define UCC_SLOW_GUMR_L_TINV 0x01000000 -+#define UCC_SLOW_GUMR_L_TEND 0x00040000 -+#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000 -+#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000 -+#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000 -+#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000 -+#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000 -+#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000 -+#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000 -+#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000 -+#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000 -+#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000 -+#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800 -+#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000 -+#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100 -+#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000 -+#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0 -+#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0 -+#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080 -+#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040 -+#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000 -+#define UCC_SLOW_GUMR_L_ENR 0x00000020 -+#define UCC_SLOW_GUMR_L_ENT 0x00000010 -+#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F -+#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008 -+#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006 -+#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004 -+#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002 -+ -+/* General UCC FAST Mode Register */ -+#define UCC_FAST_GUMR_TCI 0x20000000 -+#define UCC_FAST_GUMR_TRX 0x10000000 -+#define UCC_FAST_GUMR_TTX 0x08000000 -+#define UCC_FAST_GUMR_CDP 0x04000000 -+#define UCC_FAST_GUMR_CTSP 0x02000000 -+#define UCC_FAST_GUMR_CDS 0x01000000 -+#define UCC_FAST_GUMR_CTSS 0x00800000 -+#define UCC_FAST_GUMR_TXSY 0x00020000 -+#define UCC_FAST_GUMR_RSYN 0x00010000 -+#define UCC_FAST_GUMR_RTSM 0x00002000 -+#define UCC_FAST_GUMR_REVD 0x00000400 -+#define UCC_FAST_GUMR_ENR 0x00000020 -+#define UCC_FAST_GUMR_ENT 0x00000010 -+ -+/* UART Slow UCC Event Register (UCCE) */ -+#define UCC_UART_UCCE_AB 0x0200 -+#define UCC_UART_UCCE_IDLE 0x0100 -+#define UCC_UART_UCCE_GRA 0x0080 -+#define UCC_UART_UCCE_BRKE 0x0040 -+#define UCC_UART_UCCE_BRKS 0x0020 -+#define UCC_UART_UCCE_CCR 0x0008 -+#define UCC_UART_UCCE_BSY 0x0004 -+#define UCC_UART_UCCE_TX 0x0002 -+#define UCC_UART_UCCE_RX 0x0001 -+ -+/* HDLC Slow UCC Event Register (UCCE) */ -+#define UCC_HDLC_UCCE_GLR 0x1000 -+#define UCC_HDLC_UCCE_GLT 0x0800 -+#define UCC_HDLC_UCCE_IDLE 0x0100 -+#define UCC_HDLC_UCCE_BRKE 0x0040 -+#define UCC_HDLC_UCCE_BRKS 0x0020 -+#define UCC_HDLC_UCCE_TXE 0x0010 -+#define UCC_HDLC_UCCE_RXF 0x0008 -+#define UCC_HDLC_UCCE_BSY 0x0004 -+#define UCC_HDLC_UCCE_TXB 0x0002 -+#define UCC_HDLC_UCCE_RXB 0x0001 -+ -+/* BISYNC Slow UCC Event Register (UCCE) */ -+#define UCC_BISYNC_UCCE_GRA 0x0080 -+#define UCC_BISYNC_UCCE_TXE 0x0010 -+#define UCC_BISYNC_UCCE_RCH 0x0008 -+#define UCC_BISYNC_UCCE_BSY 0x0004 -+#define UCC_BISYNC_UCCE_TXB 0x0002 -+#define UCC_BISYNC_UCCE_RXB 0x0001 -+ -+/* Transparent UCC Event Register (UCCE) */ -+#define UCC_TRANS_UCCE_GRA 0x0080 -+#define UCC_TRANS_UCCE_TXE 0x0010 -+#define UCC_TRANS_UCCE_RXF 0x0008 -+#define UCC_TRANS_UCCE_BSY 0x0004 -+#define UCC_TRANS_UCCE_TXB 0x0002 -+#define UCC_TRANS_UCCE_RXB 0x0001 -+ -+ -+/* Gigabit Ethernet Fast UCC Event Register (UCCE) */ -+#define UCC_GETH_UCCE_MPD 0x80000000 -+#define UCC_GETH_UCCE_SCAR 0x40000000 -+#define UCC_GETH_UCCE_GRA 0x20000000 -+#define UCC_GETH_UCCE_CBPR 0x10000000 -+#define UCC_GETH_UCCE_BSY 0x08000000 -+#define UCC_GETH_UCCE_RXC 0x04000000 -+#define UCC_GETH_UCCE_TXC 0x02000000 -+#define UCC_GETH_UCCE_TXE 0x01000000 -+#define UCC_GETH_UCCE_TXB7 0x00800000 -+#define UCC_GETH_UCCE_TXB6 0x00400000 -+#define UCC_GETH_UCCE_TXB5 0x00200000 -+#define UCC_GETH_UCCE_TXB4 0x00100000 -+#define UCC_GETH_UCCE_TXB3 0x00080000 -+#define UCC_GETH_UCCE_TXB2 0x00040000 -+#define UCC_GETH_UCCE_TXB1 0x00020000 -+#define UCC_GETH_UCCE_TXB0 0x00010000 -+#define UCC_GETH_UCCE_RXB7 0x00008000 -+#define UCC_GETH_UCCE_RXB6 0x00004000 -+#define UCC_GETH_UCCE_RXB5 0x00002000 -+#define UCC_GETH_UCCE_RXB4 0x00001000 -+#define UCC_GETH_UCCE_RXB3 0x00000800 -+#define UCC_GETH_UCCE_RXB2 0x00000400 -+#define UCC_GETH_UCCE_RXB1 0x00000200 -+#define UCC_GETH_UCCE_RXB0 0x00000100 -+#define UCC_GETH_UCCE_RXF7 0x00000080 -+#define UCC_GETH_UCCE_RXF6 0x00000040 -+#define UCC_GETH_UCCE_RXF5 0x00000020 -+#define UCC_GETH_UCCE_RXF4 0x00000010 -+#define UCC_GETH_UCCE_RXF3 0x00000008 -+#define UCC_GETH_UCCE_RXF2 0x00000004 -+#define UCC_GETH_UCCE_RXF1 0x00000002 -+#define UCC_GETH_UCCE_RXF0 0x00000001 -+ -+/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */ -+#define UCC_UART_UPSMR_FLC 0x8000 -+#define UCC_UART_UPSMR_SL 0x4000 -+#define UCC_UART_UPSMR_CL_MASK 0x3000 -+#define UCC_UART_UPSMR_CL_8 0x3000 -+#define UCC_UART_UPSMR_CL_7 0x2000 -+#define UCC_UART_UPSMR_CL_6 0x1000 -+#define UCC_UART_UPSMR_CL_5 0x0000 -+#define UCC_UART_UPSMR_UM_MASK 0x0c00 -+#define UCC_UART_UPSMR_UM_NORMAL 0x0000 -+#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400 -+#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00 -+#define UCC_UART_UPSMR_FRZ 0x0200 -+#define UCC_UART_UPSMR_RZS 0x0100 -+#define UCC_UART_UPSMR_SYN 0x0080 -+#define UCC_UART_UPSMR_DRT 0x0040 -+#define UCC_UART_UPSMR_PEN 0x0010 -+#define UCC_UART_UPSMR_RPM_MASK 0x000c -+#define UCC_UART_UPSMR_RPM_ODD 0x0000 -+#define UCC_UART_UPSMR_RPM_LOW 0x0004 -+#define UCC_UART_UPSMR_RPM_EVEN 0x0008 -+#define UCC_UART_UPSMR_RPM_HIGH 0x000C -+#define UCC_UART_UPSMR_TPM_MASK 0x0003 -+#define UCC_UART_UPSMR_TPM_ODD 0x0000 -+#define UCC_UART_UPSMR_TPM_LOW 0x0001 -+#define UCC_UART_UPSMR_TPM_EVEN 0x0002 -+#define UCC_UART_UPSMR_TPM_HIGH 0x0003 -+ -+/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */ -+#define UCC_GETH_UPSMR_FTFE 0x80000000 -+#define UCC_GETH_UPSMR_PTPE 0x40000000 -+#define UCC_GETH_UPSMR_ECM 0x04000000 -+#define UCC_GETH_UPSMR_HSE 0x02000000 -+#define UCC_GETH_UPSMR_PRO 0x00400000 -+#define UCC_GETH_UPSMR_CAP 0x00200000 -+#define UCC_GETH_UPSMR_RSH 0x00100000 -+#define UCC_GETH_UPSMR_RPM 0x00080000 -+#define UCC_GETH_UPSMR_R10M 0x00040000 -+#define UCC_GETH_UPSMR_RLPB 0x00020000 -+#define UCC_GETH_UPSMR_TBIM 0x00010000 -+#define UCC_GETH_UPSMR_RES1 0x00002000 -+#define UCC_GETH_UPSMR_RMM 0x00001000 -+#define UCC_GETH_UPSMR_CAM 0x00000400 -+#define UCC_GETH_UPSMR_BRO 0x00000200 -+#define UCC_GETH_UPSMR_SMM 0x00000080 -+#define UCC_GETH_UPSMR_SGMM 0x00000020 -+ -+/* UCC Transmit On Demand Register (UTODR) */ -+#define UCC_SLOW_TOD 0x8000 -+#define UCC_FAST_TOD 0x8000 -+ -+/* UCC Bus Mode Register masks */ -+/* Not to be confused with the Bundle Mode Register */ -+#define UCC_BMR_GBL 0x20 -+#define UCC_BMR_BO_BE 0x10 -+#define UCC_BMR_CETM 0x04 -+#define UCC_BMR_DTB 0x02 -+#define UCC_BMR_BDB 0x01 -+ -+/* Function code masks */ -+#define FC_GBL 0x20 -+#define FC_DTB_LCL 0x02 -+#define UCC_FAST_FUNCTION_CODE_GBL 0x20 -+#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02 -+#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01 -+ -+#endif /* __KERNEL__ */ -+#endif /* _ASM_POWERPC_QE_H */ diff --git a/target/linux/layerscape/patches-4.4/7015-fmd-add-fman-driver.patch b/target/linux/layerscape/patches-4.4/7015-fmd-add-fman-driver.patch deleted file mode 100644 index 2d89ff9999..0000000000 --- a/target/linux/layerscape/patches-4.4/7015-fmd-add-fman-driver.patch +++ /dev/null @@ -1,116265 +0,0 @@ -From 9a69168a7ab58035571d9d19d531a40aa7f909dd Mon Sep 17 00:00:00 2001 -From: Zhao Qiang -Date: Wed, 16 Dec 2015 21:46:52 +0200 -Subject: [PATCH 15/70] fmd: add fman driver - -Add fman driver code of dpaa, put it to drivers/net/ethernet/freescale/sdk_fman. -fman is frame manager, combining ethernet MACs with packet parsing and -classification logic, providing intelligent distribution and queuing -decisions for incomming traffic. - -Signed-off-by: Mandy Lavi -Signed-off-by: Madalin Bucur -Signed-off-by: Zhao Qiang ---- - drivers/net/ethernet/freescale/Kconfig | 1 + - drivers/net/ethernet/freescale/Makefile | 1 + - drivers/net/ethernet/freescale/sdk_fman/Kconfig | 151 + - drivers/net/ethernet/freescale/sdk_fman/Makefile | 11 + - .../freescale/sdk_fman/Peripherals/FM/HC/Makefile | 15 + - .../freescale/sdk_fman/Peripherals/FM/HC/hc.c | 1232 ++++ - .../freescale/sdk_fman/Peripherals/FM/MAC/Makefile | 28 + - .../freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c | 1463 ++++ - .../freescale/sdk_fman/Peripherals/FM/MAC/dtsec.h | 228 + - .../sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.c | 97 + - .../sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.h | 42 + - .../freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c | 646 ++ - .../freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h | 224 + - .../sdk_fman/Peripherals/FM/MAC/fman_crc32.c | 119 + - .../sdk_fman/Peripherals/FM/MAC/fman_crc32.h | 43 + - .../sdk_fman/Peripherals/FM/MAC/fman_dtsec.c | 845 +++ - .../Peripherals/FM/MAC/fman_dtsec_mii_acc.c | 163 + - .../sdk_fman/Peripherals/FM/MAC/fman_memac.c | 511 ++ - .../Peripherals/FM/MAC/fman_memac_mii_acc.c | 213 + - .../sdk_fman/Peripherals/FM/MAC/fman_tgec.c | 367 + - .../freescale/sdk_fman/Peripherals/FM/MAC/memac.c | 1088 +++ - .../freescale/sdk_fman/Peripherals/FM/MAC/memac.h | 110 + - .../sdk_fman/Peripherals/FM/MAC/memac_mii_acc.c | 78 + - .../sdk_fman/Peripherals/FM/MAC/memac_mii_acc.h | 73 + - .../freescale/sdk_fman/Peripherals/FM/MAC/tgec.c | 974 +++ - .../freescale/sdk_fman/Peripherals/FM/MAC/tgec.h | 151 + - .../sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.c | 139 + - .../sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.h | 80 + - .../sdk_fman/Peripherals/FM/MACSEC/Makefile | 15 + - .../sdk_fman/Peripherals/FM/MACSEC/fm_macsec.c | 237 + - .../sdk_fman/Peripherals/FM/MACSEC/fm_macsec.h | 203 + - .../Peripherals/FM/MACSEC/fm_macsec_guest.c | 59 + - .../Peripherals/FM/MACSEC/fm_macsec_master.c | 1031 +++ - .../Peripherals/FM/MACSEC/fm_macsec_master.h | 479 ++ - .../Peripherals/FM/MACSEC/fm_macsec_secy.c | 883 +++ - .../Peripherals/FM/MACSEC/fm_macsec_secy.h | 144 + - .../freescale/sdk_fman/Peripherals/FM/Makefile | 23 + - .../freescale/sdk_fman/Peripherals/FM/Pcd/Makefile | 26 + - .../freescale/sdk_fman/Peripherals/FM/Pcd/crc64.h | 360 + - .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c | 7538 ++++++++++++++++++++ - .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.h | 399 ++ - .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_kg.c | 3242 +++++++++ - .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_kg.h | 206 + - .../sdk_fman/Peripherals/FM/Pcd/fm_manip.c | 5571 +++++++++++++++ - .../sdk_fman/Peripherals/FM/Pcd/fm_manip.h | 555 ++ - .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd.c | 2094 ++++++ - .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd.h | 543 ++ - .../sdk_fman/Peripherals/FM/Pcd/fm_pcd_ipc.h | 280 + - .../sdk_fman/Peripherals/FM/Pcd/fm_plcr.c | 1846 +++++ - .../sdk_fman/Peripherals/FM/Pcd/fm_plcr.h | 165 + - .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.c | 422 ++ - .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.h | 316 + - .../sdk_fman/Peripherals/FM/Pcd/fm_replic.c | 984 +++ - .../sdk_fman/Peripherals/FM/Pcd/fm_replic.h | 101 + - .../sdk_fman/Peripherals/FM/Pcd/fman_kg.c | 888 +++ - .../sdk_fman/Peripherals/FM/Pcd/fman_prs.c | 129 + - .../sdk_fman/Peripherals/FM/Port/Makefile | 15 + - .../sdk_fman/Peripherals/FM/Port/fm_port.c | 6436 +++++++++++++++++ - .../sdk_fman/Peripherals/FM/Port/fm_port.h | 999 +++ - .../sdk_fman/Peripherals/FM/Port/fm_port_dsar.h | 494 ++ - .../sdk_fman/Peripherals/FM/Port/fm_port_im.c | 753 ++ - .../sdk_fman/Peripherals/FM/Port/fman_port.c | 1568 ++++ - .../freescale/sdk_fman/Peripherals/FM/Rtc/Makefile | 15 + - .../freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.c | 692 ++ - .../freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.h | 96 + - .../sdk_fman/Peripherals/FM/Rtc/fman_rtc.c | 334 + - .../freescale/sdk_fman/Peripherals/FM/SP/Makefile | 15 + - .../freescale/sdk_fman/Peripherals/FM/SP/fm_sp.c | 757 ++ - .../freescale/sdk_fman/Peripherals/FM/SP/fm_sp.h | 85 + - .../freescale/sdk_fman/Peripherals/FM/SP/fman_sp.c | 197 + - .../freescale/sdk_fman/Peripherals/FM/fm.c | 5195 ++++++++++++++ - .../freescale/sdk_fman/Peripherals/FM/fm.h | 646 ++ - .../freescale/sdk_fman/Peripherals/FM/fm_ipc.h | 465 ++ - .../freescale/sdk_fman/Peripherals/FM/fm_muram.c | 174 + - .../freescale/sdk_fman/Peripherals/FM/fman.c | 1399 ++++ - .../sdk_fman/Peripherals/FM/inc/fm_common.h | 1203 ++++ - .../freescale/sdk_fman/Peripherals/FM/inc/fm_hc.h | 93 + - .../sdk_fman/Peripherals/FM/inc/fm_sp_common.h | 117 + - .../net/ethernet/freescale/sdk_fman/etc/Makefile | 12 + - .../net/ethernet/freescale/sdk_fman/etc/error.c | 95 + - drivers/net/ethernet/freescale/sdk_fman/etc/list.c | 71 + - .../net/ethernet/freescale/sdk_fman/etc/memcpy.c | 620 ++ - drivers/net/ethernet/freescale/sdk_fman/etc/mm.c | 1155 +++ - drivers/net/ethernet/freescale/sdk_fman/etc/mm.h | 105 + - .../net/ethernet/freescale/sdk_fman/etc/sprint.c | 81 + - .../ethernet/freescale/sdk_fman/fmanv3h_dflags.h | 57 + - .../ethernet/freescale/sdk_fman/fmanv3l_dflags.h | 56 + - .../sdk_fman/inc/Peripherals/crc_mac_addr_ext.h | 364 + - .../freescale/sdk_fman/inc/Peripherals/dpaa_ext.h | 207 + - .../freescale/sdk_fman/inc/Peripherals/fm_ext.h | 1705 +++++ - .../sdk_fman/inc/Peripherals/fm_mac_ext.h | 846 +++ - .../sdk_fman/inc/Peripherals/fm_macsec_ext.h | 1271 ++++ - .../sdk_fman/inc/Peripherals/fm_muram_ext.h | 170 + - .../sdk_fman/inc/Peripherals/fm_pcd_ext.h | 3974 +++++++++++ - .../sdk_fman/inc/Peripherals/fm_port_ext.h | 2608 +++++++ - .../sdk_fman/inc/Peripherals/fm_rtc_ext.h | 619 ++ - .../sdk_fman/inc/Peripherals/fm_vsp_ext.h | 411 ++ - .../sdk_fman/inc/Peripherals/mii_acc_ext.h | 76 + - .../net/ethernet/freescale/sdk_fman/inc/core_ext.h | 90 + - .../freescale/sdk_fman/inc/cores/arm_ext.h | 55 + - .../freescale/sdk_fman/inc/cores/e500v2_ext.h | 476 ++ - .../freescale/sdk_fman/inc/cores/ppc_ext.h | 141 + - .../ethernet/freescale/sdk_fman/inc/ddr_std_ext.h | 77 + - .../ethernet/freescale/sdk_fman/inc/debug_ext.h | 233 + - .../ethernet/freescale/sdk_fman/inc/endian_ext.h | 447 ++ - .../net/ethernet/freescale/sdk_fman/inc/enet_ext.h | 205 + - .../ethernet/freescale/sdk_fman/inc/error_ext.h | 529 ++ - .../ethernet/freescale/sdk_fman/inc/etc/list_ext.h | 358 + - .../ethernet/freescale/sdk_fman/inc/etc/mem_ext.h | 318 + - .../freescale/sdk_fman/inc/etc/memcpy_ext.h | 208 + - .../ethernet/freescale/sdk_fman/inc/etc/mm_ext.h | 310 + - .../freescale/sdk_fman/inc/etc/sprint_ext.h | 118 + - .../sdk_fman/inc/flib/common/arch/ppc_access.h | 37 + - .../freescale/sdk_fman/inc/flib/common/general.h | 52 + - .../freescale/sdk_fman/inc/flib/fman_common.h | 78 + - .../freescale/sdk_fman/inc/flib/fsl_enet.h | 273 + - .../freescale/sdk_fman/inc/flib/fsl_fman.h | 825 +++ - .../freescale/sdk_fman/inc/flib/fsl_fman_dtsec.h | 1096 +++ - .../sdk_fman/inc/flib/fsl_fman_dtsec_mii_acc.h | 107 + - .../freescale/sdk_fman/inc/flib/fsl_fman_kg.h | 514 ++ - .../freescale/sdk_fman/inc/flib/fsl_fman_memac.h | 427 ++ - .../sdk_fman/inc/flib/fsl_fman_memac_mii_acc.h | 78 + - .../freescale/sdk_fman/inc/flib/fsl_fman_port.h | 593 ++ - .../freescale/sdk_fman/inc/flib/fsl_fman_prs.h | 102 + - .../freescale/sdk_fman/inc/flib/fsl_fman_rtc.h | 449 ++ - .../freescale/sdk_fman/inc/flib/fsl_fman_sp.h | 138 + - .../freescale/sdk_fman/inc/flib/fsl_fman_tgec.h | 479 ++ - .../integrations/FMANV3H/dpaa_integration_ext.h | 290 + - .../sdk_fman/inc/integrations/FMANV3H/part_ext.h | 71 + - .../integrations/FMANV3H/part_integration_ext.h | 304 + - .../integrations/FMANV3L/dpaa_integration_ext.h | 292 + - .../sdk_fman/inc/integrations/FMANV3L/part_ext.h | 59 + - .../integrations/FMANV3L/part_integration_ext.h | 304 + - .../inc/integrations/LS1043/dpaa_integration_ext.h | 291 + - .../sdk_fman/inc/integrations/LS1043/part_ext.h | 64 + - .../inc/integrations/LS1043/part_integration_ext.h | 185 + - .../inc/integrations/P1023/dpaa_integration_ext.h | 213 + - .../sdk_fman/inc/integrations/P1023/part_ext.h | 82 + - .../inc/integrations/P1023/part_integration_ext.h | 635 ++ - .../P3040_P4080_P5020/dpaa_integration_ext.h | 276 + - .../inc/integrations/P3040_P4080_P5020/part_ext.h | 83 + - .../P3040_P4080_P5020/part_integration_ext.h | 336 + - .../net/ethernet/freescale/sdk_fman/inc/math_ext.h | 99 + - .../net/ethernet/freescale/sdk_fman/inc/ncsw_ext.h | 435 ++ - .../net/ethernet/freescale/sdk_fman/inc/net_ext.h | 430 ++ - .../net/ethernet/freescale/sdk_fman/inc/std_ext.h | 48 + - .../ethernet/freescale/sdk_fman/inc/stdarg_ext.h | 49 + - .../ethernet/freescale/sdk_fman/inc/stdlib_ext.h | 162 + - .../ethernet/freescale/sdk_fman/inc/string_ext.h | 56 + - .../ethernet/freescale/sdk_fman/inc/types_ext.h | 62 + - .../ethernet/freescale/sdk_fman/inc/xx_common.h | 56 + - .../net/ethernet/freescale/sdk_fman/inc/xx_ext.h | 791 ++ - .../ethernet/freescale/sdk_fman/ls1043_dflags.h | 56 + - .../net/ethernet/freescale/sdk_fman/ncsw_config.mk | 53 + - .../net/ethernet/freescale/sdk_fman/p1023_dflags.h | 65 + - .../freescale/sdk_fman/p3040_4080_5020_dflags.h | 62 + - .../net/ethernet/freescale/sdk_fman/src/Makefile | 11 + - .../freescale/sdk_fman/src/inc/system/sys_ext.h | 118 + - .../freescale/sdk_fman/src/inc/system/sys_io_ext.h | 46 + - .../freescale/sdk_fman/src/inc/types_linux.h | 208 + - .../sdk_fman/src/inc/wrapper/fsl_fman_test.h | 84 + - .../sdk_fman/src/inc/wrapper/lnxwrp_exp_sym.h | 127 + - .../sdk_fman/src/inc/wrapper/lnxwrp_fm_ext.h | 163 + - .../sdk_fman/src/inc/wrapper/lnxwrp_fsl_fman.h | 919 +++ - .../ethernet/freescale/sdk_fman/src/inc/xx/xx.h | 50 + - .../freescale/sdk_fman/src/system/Makefile | 10 + - .../freescale/sdk_fman/src/system/sys_io.c | 171 + - .../freescale/sdk_fman/src/wrapper/Makefile | 19 + - .../freescale/sdk_fman/src/wrapper/fman_test.c | 1665 +++++ - .../freescale/sdk_fman/src/wrapper/lnxwrp_fm.c | 2795 ++++++++ - .../freescale/sdk_fman/src/wrapper/lnxwrp_fm.h | 294 + - .../sdk_fman/src/wrapper/lnxwrp_fm_port.c | 1507 ++++ - .../sdk_fman/src/wrapper/lnxwrp_ioctls_fm.c | 4813 +++++++++++++ - .../sdk_fman/src/wrapper/lnxwrp_ioctls_fm_compat.c | 1300 ++++ - .../sdk_fman/src/wrapper/lnxwrp_ioctls_fm_compat.h | 755 ++ - .../sdk_fman/src/wrapper/lnxwrp_resources.h | 121 + - .../sdk_fman/src/wrapper/lnxwrp_resources_ut.c | 191 + - .../sdk_fman/src/wrapper/lnxwrp_resources_ut.h | 144 + - .../sdk_fman/src/wrapper/lnxwrp_resources_ut.make | 28 + - .../freescale/sdk_fman/src/wrapper/lnxwrp_sysfs.c | 60 + - .../freescale/sdk_fman/src/wrapper/lnxwrp_sysfs.h | 60 + - .../sdk_fman/src/wrapper/lnxwrp_sysfs_fm.c | 1855 +++++ - .../sdk_fman/src/wrapper/lnxwrp_sysfs_fm.h | 136 + - .../sdk_fman/src/wrapper/lnxwrp_sysfs_fm_port.c | 1255 ++++ - .../sdk_fman/src/wrapper/lnxwrp_sysfs_fm_port.h | 56 + - .../ethernet/freescale/sdk_fman/src/xx/Makefile | 18 + - .../freescale/sdk_fman/src/xx/module_strings.c | 45 + - .../ethernet/freescale/sdk_fman/src/xx/udivdi3.c | 132 + - .../freescale/sdk_fman/src/xx/xx_arm_linux.c | 905 +++ - .../ethernet/freescale/sdk_fman/src/xx/xx_linux.c | 918 +++ - include/uapi/linux/fmd/Kbuild | 5 + - include/uapi/linux/fmd/Peripherals/Kbuild | 4 + - include/uapi/linux/fmd/Peripherals/fm_ioctls.h | 628 ++ - include/uapi/linux/fmd/Peripherals/fm_pcd_ioctls.h | 3084 ++++++++ - .../uapi/linux/fmd/Peripherals/fm_port_ioctls.h | 948 +++ - .../uapi/linux/fmd/Peripherals/fm_test_ioctls.h | 208 + - include/uapi/linux/fmd/integrations/Kbuild | 1 + - .../linux/fmd/integrations/integration_ioctls.h | 56 + - include/uapi/linux/fmd/ioctls.h | 96 + - include/uapi/linux/fmd/net_ioctls.h | 430 ++ - 200 files changed, 115244 insertions(+) - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Kconfig - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/hc.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec_mii_acc.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac.c - create mode 100755 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac_mii_acc.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_tgec.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac_mii_acc.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac_mii_acc.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_guest.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_master.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_master.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/crc64.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_kg.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_kg.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_manip.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_manip.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd_ipc.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_plcr.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_plcr.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_replic.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_replic.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fman_kg.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fman_prs.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port.h - create mode 100755 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port_dsar.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port_im.c - create mode 100755 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fman_port.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.h - create mode 100755 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fman_rtc.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/fm_sp.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/fm_sp.h - create mode 100755 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/fman_sp.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm_ipc.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm_muram.c - create mode 100755 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fman.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc/fm_common.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc/fm_hc.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc/fm_sp_common.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/error.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/list.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/memcpy.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/mm.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/mm.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/etc/sprint.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/fmanv3h_dflags.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/fmanv3l_dflags.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/crc_mac_addr_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/dpaa_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_mac_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_macsec_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_muram_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_pcd_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_port_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_rtc_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_vsp_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/mii_acc_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/core_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/cores/arm_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/cores/e500v2_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/cores/ppc_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/ddr_std_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/debug_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/endian_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/enet_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/error_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/etc/list_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/etc/mem_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/etc/memcpy_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/etc/mm_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/etc/sprint_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/common/arch/ppc_access.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/common/general.h - create mode 100755 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fman_common.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_enet.h - create mode 100755 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_dtsec.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_dtsec_mii_acc.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_kg.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_memac.h - create mode 100755 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_memac_mii_acc.h - create mode 100755 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_port.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_prs.h - create mode 100755 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_rtc.h - create mode 100755 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_sp.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_tgec.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3H/dpaa_integration_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3H/part_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3H/part_integration_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3L/dpaa_integration_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3L/part_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3L/part_integration_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/LS1043/dpaa_integration_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/LS1043/part_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/LS1043/part_integration_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P1023/dpaa_integration_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P1023/part_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P1023/part_integration_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P3040_P4080_P5020/dpaa_integration_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P3040_P4080_P5020/part_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P3040_P4080_P5020/part_integration_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/math_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/ncsw_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/net_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/std_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/stdarg_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/stdlib_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/string_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/types_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/xx_common.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/inc/xx_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/ls1043_dflags.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/p1023_dflags.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/p3040_4080_5020_dflags.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/system/sys_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/system/sys_io_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/types_linux.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/fsl_fman_test.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/lnxwrp_exp_sym.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/lnxwrp_fm_ext.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/lnxwrp_fsl_fman.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/inc/xx/xx.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/system/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/system/sys_io.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/fman_test.c - create mode 100755 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_fm.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_fm.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_fm_port.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_ioctls_fm.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_ioctls_fm_compat.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_ioctls_fm_compat.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_resources.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_resources_ut.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_resources_ut.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_resources_ut.make - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs_fm.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs_fm.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs_fm_port.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs_fm_port.h - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/xx/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/xx/module_strings.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/xx/udivdi3.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/xx/xx_arm_linux.c - create mode 100644 drivers/net/ethernet/freescale/sdk_fman/src/xx/xx_linux.c - create mode 100644 include/uapi/linux/fmd/Kbuild - create mode 100644 include/uapi/linux/fmd/Peripherals/Kbuild - create mode 100644 include/uapi/linux/fmd/Peripherals/fm_ioctls.h - create mode 100644 include/uapi/linux/fmd/Peripherals/fm_pcd_ioctls.h - create mode 100644 include/uapi/linux/fmd/Peripherals/fm_port_ioctls.h - create mode 100644 include/uapi/linux/fmd/Peripherals/fm_test_ioctls.h - create mode 100644 include/uapi/linux/fmd/integrations/Kbuild - create mode 100644 include/uapi/linux/fmd/integrations/integration_ioctls.h - create mode 100644 include/uapi/linux/fmd/ioctls.h - create mode 100644 include/uapi/linux/fmd/net_ioctls.h - ---- a/drivers/net/ethernet/freescale/Kconfig -+++ b/drivers/net/ethernet/freescale/Kconfig -@@ -92,4 +92,5 @@ config GIANFAR - and MPC86xx family of chips, the eTSEC on LS1021A and the FEC - on the 8540. - -+source "drivers/net/ethernet/freescale/sdk_fman/Kconfig" - endif # NET_VENDOR_FREESCALE ---- a/drivers/net/ethernet/freescale/Makefile -+++ b/drivers/net/ethernet/freescale/Makefile -@@ -17,3 +17,4 @@ gianfar_driver-objs := gianfar.o \ - gianfar_ethtool.o - obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o - ucc_geth_driver-objs := ucc_geth.o ucc_geth_ethtool.o -+obj-$(if $(CONFIG_FSL_SDK_FMAN),y) += sdk_fman/ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Kconfig -@@ -0,0 +1,151 @@ -+menu "Frame Manager support" -+ -+menuconfig FSL_SDK_FMAN -+ bool "Freescale Frame Manager (datapath) support - SDK driver" -+ depends on (FSL_SOC || ARM64 || ARM) && FSL_BMAN && FSL_QMAN -+ default y -+ ---help--- -+ If unsure, say Y. -+ -+if FSL_SDK_FMAN -+ -+config FSL_SDK_FMAN_TEST -+ bool "FMan test module" -+ default n -+ select FSL_DPAA_HOOKS -+ ---help--- -+ This option compiles test code for FMan. -+ -+menu "FMAN Processor support" -+choice -+ depends on FSL_SDK_FMAN -+ prompt "Processor Type" -+ -+config FMAN_ARM -+ bool "LS1043" -+ depends on ARM64 || ARM -+ ---help--- -+ Choose "LS1043" for the ARM platforms: -+ LS1043 -+ -+config FMAN_P3040_P4080_P5020 -+ bool "P3040 P4080 5020" -+ -+config FMAN_P1023 -+ bool "P1023" -+ -+config FMAN_V3H -+ bool "FmanV3H" -+ ---help--- -+ Choose "FmanV3H" for Fman rev3H: -+ B4860, T4240, T4160, etc -+ -+config FMAN_V3L -+ bool "FmanV3L" -+ ---help--- -+ Choose "FmanV3L" for Fman rev3L: -+ T1040, T1042, T1020, T1022, T1023, T1024, etc -+ -+endchoice -+endmenu -+ -+config FMAN_MIB_CNT_OVF_IRQ_EN -+ bool "Enable the dTSEC MIB counters overflow interrupt" -+ default n -+ ---help--- -+ Enable the dTSEC MIB counters overflow interrupt to get -+ accurate MIB counters values. Enabled it compensates -+ for the counters overflow but reduces performance and -+ triggers error messages in HV setups. -+ -+config FSL_FM_MAX_FRAME_SIZE -+ int "Maximum L2 frame size" -+ depends on FSL_SDK_FMAN -+ range 64 9600 -+ default "1522" -+ help -+ Configure this in relation to the maximum possible MTU of your -+ network configuration. In particular, one would need to -+ increase this value in order to use jumbo frames. -+ FSL_FM_MAX_FRAME_SIZE must accommodate the Ethernet FCS (4 bytes) -+ and one ETH+VLAN header (18 bytes), to a total of 22 bytes in -+ excess of the desired L3 MTU. -+ -+ Note that having too large a FSL_FM_MAX_FRAME_SIZE (much larger -+ than the actual MTU) may lead to buffer exhaustion, especially -+ in the case of badly fragmented datagrams on the Rx path. -+ Conversely, having a FSL_FM_MAX_FRAME_SIZE smaller than the actual -+ MTU will lead to frames being dropped. -+ -+ This can be overridden by specifying "fsl_fm_max_frm" in -+ the kernel bootargs: -+ * in Hypervisor-based scenarios, by adding a "chosen" node -+ with the "bootargs" property specifying -+ "fsl_fm_max_frm="; -+ * in non-Hypervisor-based scenarios, via u-boot's env, by -+ modifying the "bootargs" env variable. -+ -+config FSL_FM_RX_EXTRA_HEADROOM -+ int "Add extra headroom at beginning of data buffers" -+ depends on FSL_SDK_FMAN -+ range 16 384 -+ default "64" -+ help -+ Configure this to tell the Frame Manager to reserve some extra -+ space at the beginning of a data buffer on the receive path, -+ before Internal Context fields are copied. This is in addition -+ to the private data area already reserved for driver internal -+ use. The provided value must be a multiple of 16. -+ -+ This setting can be overridden by specifying -+ "fsl_fm_rx_extra_headroom" in the kernel bootargs: -+ * in Hypervisor-based scenarios, by adding a "chosen" node -+ with the "bootargs" property specifying -+ "fsl_fm_rx_extra_headroom="; -+ * in non-Hypervisor-based scenarios, via u-boot's env, by -+ modifying the "bootargs" env variable. -+ -+config FMAN_PFC -+ bool "FMan PFC support (EXPERIMENTAL)" -+ depends on ( FMAN_V3H || FMAN_V3L || FMAN_ARM) && FSL_SDK_FMAN -+ default n -+ ---help--- -+ This option enables PFC support on FMan v3 ports. -+ Data Center Bridging defines Classes of Service that are -+ flow-controlled using PFC pause frames. -+ -+if FMAN_PFC -+config FMAN_PFC_COS_COUNT -+ int "Number of PFC Classes of Service" -+ depends on FMAN_PFC && FSL_SDK_FMAN -+ range 1 4 -+ default "3" -+ -+config FMAN_PFC_QUANTA_0 -+ int "The pause quanta for PFC CoS 0" -+ depends on FMAN_PFC && FSL_SDK_FMAN -+ range 0 65535 -+ default "65535" -+ -+config FMAN_PFC_QUANTA_1 -+ int "The pause quanta for PFC CoS 1" -+ depends on FMAN_PFC && FSL_SDK_FMAN -+ range 0 65535 -+ default "65535" -+ -+config FMAN_PFC_QUANTA_2 -+ int "The pause quanta for PFC CoS 2" -+ depends on FMAN_PFC && FSL_SDK_FMAN -+ range 0 65535 -+ default "65535" -+ -+config FMAN_PFC_QUANTA_3 -+ int "The pause quanta for PFC CoS 3" -+ depends on FMAN_PFC && FSL_SDK_FMAN -+ range 0 65535 -+ default "65535" -+endif -+ -+endif # FSL_SDK_FMAN -+ -+endmenu ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Makefile -@@ -0,0 +1,11 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+# -+obj-y += etc/ -+obj-y += Peripherals/FM/ -+obj-y += src/ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/Makefile -@@ -0,0 +1,15 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+ -+NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc -+ -+ccflags-y += -I$(NCSW_FM_INC) -+ -+obj-y += fsl-ncsw-Hc.o -+ -+fsl-ncsw-Hc-objs := hc.o ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/hc.c -@@ -0,0 +1,1232 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "sprint_ext.h" -+#include "string_ext.h" -+ -+#include "fm_common.h" -+#include "fm_hc.h" -+ -+ -+/**************************************************************************//** -+ @Description defaults -+*//***************************************************************************/ -+#define DEFAULT_dataMemId 0 -+ -+#define HC_HCOR_OPCODE_PLCR_PRFL 0x0 -+#define HC_HCOR_OPCODE_KG_SCM 0x1 -+#define HC_HCOR_OPCODE_SYNC 0x2 -+#define HC_HCOR_OPCODE_CC 0x3 -+#define HC_HCOR_OPCODE_CC_AGE_MASK 0x4 -+#define HC_HCOR_OPCODE_CC_CAPWAP_REASSM_TIMEOUT 0x5 -+#define HC_HCOR_OPCODE_CC_REASSM_TIMEOUT 0x10 -+#define HC_HCOR_OPCODE_CC_IP_FRAG_INITIALIZATION 0x11 -+#define HC_HCOR_OPCODE_CC_UPDATE_WITH_AGING 0x13 -+#define HC_HCOR_ACTION_REG_REASSM_TIMEOUT_ACTIVE_SHIFT 24 -+#define HC_HCOR_EXTRA_REG_REASSM_TIMEOUT_TSBS_SHIFT 24 -+#define HC_HCOR_EXTRA_REG_CC_AGING_ADD 0x80000000 -+#define HC_HCOR_EXTRA_REG_CC_AGING_REMOVE 0x40000000 -+#define HC_HCOR_EXTRA_REG_CC_AGING_CHANGE_MASK 0xC0000000 -+#define HC_HCOR_EXTRA_REG_CC_REMOVE_INDX_SHIFT 24 -+#define HC_HCOR_EXTRA_REG_CC_REMOVE_INDX_MASK 0x1F000000 -+#define HC_HCOR_ACTION_REG_REASSM_TIMEOUT_RES_SHIFT 16 -+#define HC_HCOR_ACTION_REG_REASSM_TIMEOUT_RES_MASK 0xF -+#define HC_HCOR_ACTION_REG_IP_FRAG_SCRATCH_POOL_CMD_SHIFT 24 -+#define HC_HCOR_ACTION_REG_IP_FRAG_SCRATCH_POOL_BPID 16 -+ -+#define HC_HCOR_GBL 0x20000000 -+ -+#define HC_HCOR_KG_SCHEME_COUNTER 0x00000400 -+ -+#if (DPAA_VERSION == 10) -+#define HC_HCOR_KG_SCHEME_REGS_MASK 0xFFFFF800 -+#else -+#define HC_HCOR_KG_SCHEME_REGS_MASK 0xFFFFFE00 -+#endif /* (DPAA_VERSION == 10) */ -+ -+#define SIZE_OF_HC_FRAME_PORT_REGS (sizeof(t_HcFrame)-sizeof(struct fman_kg_scheme_regs)+sizeof(t_FmPcdKgPortRegs)) -+#define SIZE_OF_HC_FRAME_SCHEME_REGS sizeof(t_HcFrame) -+#define SIZE_OF_HC_FRAME_PROFILES_REGS (sizeof(t_HcFrame)-sizeof(struct fman_kg_scheme_regs)+sizeof(t_FmPcdPlcrProfileRegs)) -+#define SIZE_OF_HC_FRAME_PROFILE_CNT (sizeof(t_HcFrame)-sizeof(t_FmPcdPlcrProfileRegs)+sizeof(uint32_t)) -+#define SIZE_OF_HC_FRAME_READ_OR_CC_DYNAMIC 16 -+ -+#define HC_CMD_POOL_SIZE (INTG_MAX_NUM_OF_CORES) -+ -+#define BUILD_FD(len) \ -+do { \ -+ memset(&fmFd, 0, sizeof(t_DpaaFD)); \ -+ DPAA_FD_SET_ADDR(&fmFd, p_HcFrame); \ -+ DPAA_FD_SET_OFFSET(&fmFd, 0); \ -+ DPAA_FD_SET_LENGTH(&fmFd, len); \ -+} while (0) -+ -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+typedef struct t_FmPcdKgPortRegs { -+ volatile uint32_t spReg; -+ volatile uint32_t cppReg; -+} t_FmPcdKgPortRegs; -+ -+typedef struct t_HcFrame { -+ volatile uint32_t opcode; -+ volatile uint32_t actionReg; -+ volatile uint32_t extraReg; -+ volatile uint32_t commandSequence; -+ union { -+ struct fman_kg_scheme_regs schemeRegs; -+ struct fman_kg_scheme_regs schemeRegsWithoutCounter; -+ t_FmPcdPlcrProfileRegs profileRegs; -+ volatile uint32_t singleRegForWrite; /* for writing SP, CPP, profile counter */ -+ t_FmPcdKgPortRegs portRegsForRead; -+ volatile uint32_t clsPlanEntries[CLS_PLAN_NUM_PER_GRP]; -+ t_FmPcdCcCapwapReassmTimeoutParams ccCapwapReassmTimeout; -+ t_FmPcdCcReassmTimeoutParams ccReassmTimeout; -+ } hcSpecificData; -+} t_HcFrame; -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+ -+typedef struct t_FmHc { -+ t_Handle h_FmPcd; -+ t_Handle h_HcPortDev; -+ t_FmPcdQmEnqueueCallback *f_QmEnqueue; /**< A callback for enqueuing frames to the QM */ -+ t_Handle h_QmArg; /**< A handle to the QM module */ -+ uint8_t dataMemId; /**< Memory partition ID for data buffers */ -+ -+ uint32_t seqNum[HC_CMD_POOL_SIZE]; /* FIFO of seqNum to use when -+ taking buffer */ -+ uint32_t nextSeqNumLocation; /* seqNum location in seqNum[] for next buffer */ -+ volatile bool enqueued[HC_CMD_POOL_SIZE]; /* HC is active - frame is enqueued -+ and not confirmed yet */ -+ t_HcFrame *p_Frm[HC_CMD_POOL_SIZE]; -+} t_FmHc; -+ -+ -+static t_Error FillBufPool(t_FmHc *p_FmHc) -+{ -+ uint32_t i; -+ -+ ASSERT_COND(p_FmHc); -+ -+ for (i = 0; i < HC_CMD_POOL_SIZE; i++) -+ { -+#ifdef FM_LOCKUP_ALIGNMENT_ERRATA_FMAN_SW004 -+ p_FmHc->p_Frm[i] = (t_HcFrame *)XX_MallocSmart((sizeof(t_HcFrame) + (16 - (sizeof(t_FmHc) % 16))), -+ p_FmHc->dataMemId, -+ 16); -+#else -+ p_FmHc->p_Frm[i] = (t_HcFrame *)XX_MallocSmart(sizeof(t_HcFrame), -+ p_FmHc->dataMemId, -+ 16); -+#endif /* FM_LOCKUP_ALIGNMENT_ERRATA_FMAN_SW004 */ -+ if (!p_FmHc->p_Frm[i]) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FM HC frames!")); -+ } -+ -+ /* Initialize FIFO of seqNum to use during GetBuf */ -+ for (i = 0; i < HC_CMD_POOL_SIZE; i++) -+ { -+ p_FmHc->seqNum[i] = i; -+ } -+ p_FmHc->nextSeqNumLocation = 0; -+ -+ return E_OK; -+} -+ -+static __inline__ t_HcFrame * GetBuf(t_FmHc *p_FmHc, uint32_t *p_SeqNum) -+{ -+ uint32_t intFlags; -+ -+ ASSERT_COND(p_FmHc); -+ -+ intFlags = FmPcdLock(p_FmHc->h_FmPcd); -+ -+ if (p_FmHc->nextSeqNumLocation == HC_CMD_POOL_SIZE) -+ { -+ /* No more buffers */ -+ FmPcdUnlock(p_FmHc->h_FmPcd, intFlags); -+ return NULL; -+ } -+ -+ *p_SeqNum = p_FmHc->seqNum[p_FmHc->nextSeqNumLocation]; -+ p_FmHc->nextSeqNumLocation++; -+ -+ FmPcdUnlock(p_FmHc->h_FmPcd, intFlags); -+ return p_FmHc->p_Frm[*p_SeqNum]; -+} -+ -+static __inline__ void PutBuf(t_FmHc *p_FmHc, t_HcFrame *p_Buf, uint32_t seqNum) -+{ -+ uint32_t intFlags; -+ -+ UNUSED(p_Buf); -+ -+ intFlags = FmPcdLock(p_FmHc->h_FmPcd); -+ ASSERT_COND(p_FmHc->nextSeqNumLocation); -+ p_FmHc->nextSeqNumLocation--; -+ p_FmHc->seqNum[p_FmHc->nextSeqNumLocation] = seqNum; -+ FmPcdUnlock(p_FmHc->h_FmPcd, intFlags); -+} -+ -+static __inline__ t_Error EnQFrm(t_FmHc *p_FmHc, t_DpaaFD *p_FmFd, uint32_t seqNum) -+{ -+ t_Error err = E_OK; -+ uint32_t intFlags; -+ uint32_t timeout=100; -+ -+ intFlags = FmPcdLock(p_FmHc->h_FmPcd); -+ ASSERT_COND(!p_FmHc->enqueued[seqNum]); -+ p_FmHc->enqueued[seqNum] = TRUE; -+ FmPcdUnlock(p_FmHc->h_FmPcd, intFlags); -+ DBG(TRACE, ("Send Hc, SeqNum %d, buff@0x%x, fd offset 0x%x", -+ seqNum, -+ DPAA_FD_GET_ADDR(p_FmFd), -+ DPAA_FD_GET_OFFSET(p_FmFd))); -+ err = p_FmHc->f_QmEnqueue(p_FmHc->h_QmArg, (void *)p_FmFd); -+ if (err) -+ RETURN_ERROR(MINOR, err, ("HC enqueue failed")); -+ -+ while (p_FmHc->enqueued[seqNum] && --timeout) -+ XX_UDelay(100); -+ -+ if (!timeout) -+ RETURN_ERROR(MINOR, E_TIMEOUT, ("HC Callback, timeout exceeded")); -+ -+ return err; -+} -+ -+ -+t_Handle FmHcConfigAndInit(t_FmHcParams *p_FmHcParams) -+{ -+ t_FmHc *p_FmHc; -+ t_FmPortParams fmPortParam; -+ t_Error err; -+ -+ p_FmHc = (t_FmHc *)XX_Malloc(sizeof(t_FmHc)); -+ if (!p_FmHc) -+ { -+ REPORT_ERROR(MINOR, E_NO_MEMORY, ("HC obj")); -+ return NULL; -+ } -+ memset(p_FmHc,0,sizeof(t_FmHc)); -+ -+ p_FmHc->h_FmPcd = p_FmHcParams->h_FmPcd; -+ p_FmHc->f_QmEnqueue = p_FmHcParams->params.f_QmEnqueue; -+ p_FmHc->h_QmArg = p_FmHcParams->params.h_QmArg; -+ p_FmHc->dataMemId = DEFAULT_dataMemId; -+ -+ err = FillBufPool(p_FmHc); -+ if (err != E_OK) -+ { -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ FmHcFree(p_FmHc); -+ return NULL; -+ } -+ -+ if (!FmIsMaster(p_FmHcParams->h_Fm)) -+ return (t_Handle)p_FmHc; -+ -+ memset(&fmPortParam, 0, sizeof(fmPortParam)); -+ fmPortParam.baseAddr = p_FmHcParams->params.portBaseAddr; -+ fmPortParam.portType = e_FM_PORT_TYPE_OH_HOST_COMMAND; -+ fmPortParam.portId = p_FmHcParams->params.portId; -+ fmPortParam.liodnBase = p_FmHcParams->params.liodnBase; -+ fmPortParam.h_Fm = p_FmHcParams->h_Fm; -+ -+ fmPortParam.specificParams.nonRxParams.errFqid = p_FmHcParams->params.errFqid; -+ fmPortParam.specificParams.nonRxParams.dfltFqid = p_FmHcParams->params.confFqid; -+ fmPortParam.specificParams.nonRxParams.qmChannel = p_FmHcParams->params.qmChannel; -+ -+ p_FmHc->h_HcPortDev = FM_PORT_Config(&fmPortParam); -+ if (!p_FmHc->h_HcPortDev) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_HANDLE, ("FM HC port!")); -+ XX_Free(p_FmHc); -+ return NULL; -+ } -+ -+ err = FM_PORT_ConfigMaxFrameLength(p_FmHc->h_HcPortDev, -+ (uint16_t)sizeof(t_HcFrame)); -+ -+ if (err != E_OK) -+ { -+ REPORT_ERROR(MAJOR, err, ("FM HC port init!")); -+ FmHcFree(p_FmHc); -+ return NULL; -+ } -+ -+ /* final init */ -+ err = FM_PORT_Init(p_FmHc->h_HcPortDev); -+ if (err != E_OK) -+ { -+ REPORT_ERROR(MAJOR, err, ("FM HC port init!")); -+ FmHcFree(p_FmHc); -+ return NULL; -+ } -+ -+ err = FM_PORT_Enable(p_FmHc->h_HcPortDev); -+ if (err != E_OK) -+ { -+ REPORT_ERROR(MAJOR, err, ("FM HC port enable!")); -+ FmHcFree(p_FmHc); -+ return NULL; -+ } -+ -+ return (t_Handle)p_FmHc; -+} -+ -+void FmHcFree(t_Handle h_FmHc) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ int i; -+ -+ if (!p_FmHc) -+ return; -+ -+ for (i=0; ip_Frm[i]) -+ XX_FreeSmart(p_FmHc->p_Frm[i]); -+ else -+ break; -+ -+ if (p_FmHc->h_HcPortDev) -+ FM_PORT_Free(p_FmHc->h_HcPortDev); -+ -+ XX_Free(p_FmHc); -+} -+ -+/*****************************************************************************/ -+t_Error FmHcSetFramesDataMemory(t_Handle h_FmHc, -+ uint8_t memId) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ int i; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmHc, E_INVALID_HANDLE); -+ -+ p_FmHc->dataMemId = memId; -+ -+ for (i=0; ip_Frm[i]) -+ XX_FreeSmart(p_FmHc->p_Frm[i]); -+ -+ return FillBufPool(p_FmHc); -+} -+ -+void FmHcTxConf(t_Handle h_FmHc, t_DpaaFD *p_Fd) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_HcFrame *p_HcFrame; -+ uint32_t intFlags; -+ -+ ASSERT_COND(p_FmHc); -+ -+ intFlags = FmPcdLock(p_FmHc->h_FmPcd); -+ p_HcFrame = (t_HcFrame *)PTR_MOVE(DPAA_FD_GET_ADDR(p_Fd), DPAA_FD_GET_OFFSET(p_Fd)); -+ -+ DBG(TRACE, ("Hc Conf, SeqNum %d, FD@0x%x, fd offset 0x%x", -+ p_HcFrame->commandSequence, DPAA_FD_GET_ADDR(p_Fd), DPAA_FD_GET_OFFSET(p_Fd))); -+ -+ if (!(p_FmHc->enqueued[p_HcFrame->commandSequence])) -+ REPORT_ERROR(MINOR, E_INVALID_FRAME, ("Not an Host-Command frame received!")); -+ else -+ p_FmHc->enqueued[p_HcFrame->commandSequence] = FALSE; -+ FmPcdUnlock(p_FmHc->h_FmPcd, intFlags); -+} -+ -+t_Error FmHcPcdKgSetScheme(t_Handle h_FmHc, -+ t_Handle h_Scheme, -+ struct fman_kg_scheme_regs *p_SchemeRegs, -+ bool updateCounter) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_Error err = E_OK; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ uint8_t physicalSchemeId; -+ uint32_t seqNum; -+ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ -+ physicalSchemeId = FmPcdKgGetSchemeId(h_Scheme); -+ -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM); -+ p_HcFrame->actionReg = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, updateCounter); -+ p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK; -+ memcpy(&p_HcFrame->hcSpecificData.schemeRegs, p_SchemeRegs, sizeof(struct fman_kg_scheme_regs)); -+ if (!updateCounter) -+ { -+ p_HcFrame->hcSpecificData.schemeRegs.kgse_dv0 = p_SchemeRegs->kgse_dv0; -+ p_HcFrame->hcSpecificData.schemeRegs.kgse_dv1 = p_SchemeRegs->kgse_dv1; -+ p_HcFrame->hcSpecificData.schemeRegs.kgse_ccbs = p_SchemeRegs->kgse_ccbs; -+ p_HcFrame->hcSpecificData.schemeRegs.kgse_mv = p_SchemeRegs->kgse_mv; -+ } -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(sizeof(t_HcFrame)); -+ -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Error FmHcPcdKgDeleteScheme(t_Handle h_FmHc, t_Handle h_Scheme) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_Error err = E_OK; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ uint8_t physicalSchemeId = FmPcdKgGetSchemeId(h_Scheme); -+ uint32_t seqNum; -+ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM); -+ p_HcFrame->actionReg = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, TRUE); -+ p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK; -+ memset(&p_HcFrame->hcSpecificData.schemeRegs, 0, sizeof(struct fman_kg_scheme_regs)); -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(sizeof(t_HcFrame)); -+ -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Error FmHcPcdKgCcGetSetParams(t_Handle h_FmHc, t_Handle h_Scheme, uint32_t requiredAction, uint32_t value) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_Error err = E_OK; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ uint8_t relativeSchemeId; -+ uint8_t physicalSchemeId = FmPcdKgGetSchemeId(h_Scheme); -+ uint32_t tmpReg32 = 0; -+ uint32_t seqNum; -+ -+ /* Scheme is locked by calling routine */ -+ /* WARNING - this lock will not be efficient if other HC routine will attempt to change -+ * "kgse_mode" or "kgse_om" without locking scheme ! -+ */ -+ -+ relativeSchemeId = FmPcdKgGetRelativeSchemeId(p_FmHc->h_FmPcd, physicalSchemeId); -+ if ( relativeSchemeId == FM_PCD_KG_NUM_OF_SCHEMES) -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG); -+ -+ if (!FmPcdKgGetRequiredActionFlag(p_FmHc->h_FmPcd, relativeSchemeId) || -+ !(FmPcdKgGetRequiredAction(p_FmHc->h_FmPcd, relativeSchemeId) & requiredAction)) -+ { -+ if ((requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA) && -+ (FmPcdKgGetNextEngine(p_FmHc->h_FmPcd, relativeSchemeId) == e_FM_PCD_PLCR)) -+ { -+ if ((FmPcdKgIsDirectPlcr(p_FmHc->h_FmPcd, relativeSchemeId) == FALSE) || -+ (FmPcdKgIsDistrOnPlcrProfile(p_FmHc->h_FmPcd, relativeSchemeId) == TRUE)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("In this situation PP can not be with distribution and has to be shared")); -+ err = FmPcdPlcrCcGetSetParams(p_FmHc->h_FmPcd, FmPcdKgGetRelativeProfileId(p_FmHc->h_FmPcd, relativeSchemeId), requiredAction); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ else /* From here we deal with KG-Schemes only */ -+ { -+ /* Pre change general code */ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM); -+ p_HcFrame->actionReg = FmPcdKgBuildReadSchemeActionReg(physicalSchemeId); -+ p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK; -+ p_HcFrame->commandSequence = seqNum; -+ BUILD_FD(SIZE_OF_HC_FRAME_READ_OR_CC_DYNAMIC); -+ if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ /* specific change */ -+ if ((requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA) && -+ ((FmPcdKgGetNextEngine(p_FmHc->h_FmPcd, relativeSchemeId) == e_FM_PCD_DONE) && -+ (FmPcdKgGetDoneAction(p_FmHc->h_FmPcd, relativeSchemeId) == e_FM_PCD_ENQ_FRAME))) -+ { -+ tmpReg32 = p_HcFrame->hcSpecificData.schemeRegs.kgse_mode; -+ ASSERT_COND(tmpReg32 & (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME)); -+ p_HcFrame->hcSpecificData.schemeRegs.kgse_mode = tmpReg32 | NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA; -+ } -+ -+ if ((requiredAction & UPDATE_KG_NIA_CC_WA) && -+ (FmPcdKgGetNextEngine(p_FmHc->h_FmPcd, relativeSchemeId) == e_FM_PCD_CC)) -+ { -+ tmpReg32 = p_HcFrame->hcSpecificData.schemeRegs.kgse_mode; -+ ASSERT_COND(tmpReg32 & (NIA_ENG_FM_CTL | NIA_FM_CTL_AC_CC)); -+ tmpReg32 &= ~NIA_FM_CTL_AC_CC; -+ p_HcFrame->hcSpecificData.schemeRegs.kgse_mode = tmpReg32 | NIA_FM_CTL_AC_PRE_CC; -+ } -+ -+ if (requiredAction & UPDATE_KG_OPT_MODE) -+ p_HcFrame->hcSpecificData.schemeRegs.kgse_om = value; -+ -+ if (requiredAction & UPDATE_KG_NIA) -+ { -+ tmpReg32 = p_HcFrame->hcSpecificData.schemeRegs.kgse_mode; -+ tmpReg32 &= ~(NIA_ENG_MASK | NIA_AC_MASK); -+ tmpReg32 |= value; -+ p_HcFrame->hcSpecificData.schemeRegs.kgse_mode = tmpReg32; -+ } -+ -+ /* Post change general code */ -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM); -+ p_HcFrame->actionReg = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, FALSE); -+ p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK; -+ -+ BUILD_FD(sizeof(t_HcFrame)); -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ } -+ -+ return E_OK; -+} -+ -+uint32_t FmHcPcdKgGetSchemeCounter(t_Handle h_FmHc, t_Handle h_Scheme) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_Error err; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ uint32_t retVal; -+ uint8_t relativeSchemeId; -+ uint8_t physicalSchemeId = FmPcdKgGetSchemeId(h_Scheme); -+ uint32_t seqNum; -+ -+ relativeSchemeId = FmPcdKgGetRelativeSchemeId(p_FmHc->h_FmPcd, physicalSchemeId); -+ if ( relativeSchemeId == FM_PCD_KG_NUM_OF_SCHEMES) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG); -+ return 0; -+ } -+ -+ /* first read scheme and check that it is valid */ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ { -+ REPORT_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ return 0; -+ } -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM); -+ p_HcFrame->actionReg = FmPcdKgBuildReadSchemeActionReg(physicalSchemeId); -+ p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK; -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(SIZE_OF_HC_FRAME_READ_OR_CC_DYNAMIC); -+ -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ if (err != E_OK) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ return 0; -+ } -+ -+ if (!FmPcdKgHwSchemeIsValid(p_HcFrame->hcSpecificData.schemeRegs.kgse_mode)) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ REPORT_ERROR(MAJOR, E_ALREADY_EXISTS, ("Scheme is invalid")); -+ return 0; -+ } -+ -+ retVal = p_HcFrame->hcSpecificData.schemeRegs.kgse_spc; -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ -+ return retVal; -+} -+ -+t_Error FmHcPcdKgSetSchemeCounter(t_Handle h_FmHc, t_Handle h_Scheme, uint32_t value) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_Error err = E_OK; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ uint8_t relativeSchemeId, physicalSchemeId; -+ uint32_t seqNum; -+ -+ physicalSchemeId = FmPcdKgGetSchemeId(h_Scheme); -+ relativeSchemeId = FmPcdKgGetRelativeSchemeId(p_FmHc->h_FmPcd, physicalSchemeId); -+ if ( relativeSchemeId == FM_PCD_KG_NUM_OF_SCHEMES) -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG); -+ -+ /* first read scheme and check that it is valid */ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM); -+ p_HcFrame->actionReg = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, TRUE); -+ p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_COUNTER; -+ /* write counter */ -+ p_HcFrame->hcSpecificData.singleRegForWrite = value; -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(sizeof(t_HcFrame)); -+ -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ return err; -+} -+ -+t_Error FmHcPcdKgSetClsPlan(t_Handle h_FmHc, t_FmPcdKgInterModuleClsPlanSet *p_Set) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ uint8_t i, idx; -+ uint32_t seqNum; -+ t_Error err = E_OK; -+ -+ ASSERT_COND(p_FmHc); -+ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ -+ for (i = p_Set->baseEntry; i < (p_Set->baseEntry+p_Set->numOfClsPlanEntries); i+=8) -+ { -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM); -+ p_HcFrame->actionReg = FmPcdKgBuildWriteClsPlanBlockActionReg((uint8_t)(i / CLS_PLAN_NUM_PER_GRP)); -+ p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK; -+ -+ idx = (uint8_t)(i - p_Set->baseEntry); -+ ASSERT_COND(idx < FM_PCD_MAX_NUM_OF_CLS_PLANS); -+ memcpy(&p_HcFrame->hcSpecificData.clsPlanEntries, &p_Set->vectors[idx], CLS_PLAN_NUM_PER_GRP*sizeof(uint32_t)); -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(sizeof(t_HcFrame)); -+ -+ if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ } -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ return err; -+} -+ -+t_Error FmHcPcdKgDeleteClsPlan(t_Handle h_FmHc, uint8_t grpId) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_FmPcdKgInterModuleClsPlanSet *p_ClsPlanSet; -+ -+ p_ClsPlanSet = (t_FmPcdKgInterModuleClsPlanSet *)XX_Malloc(sizeof(t_FmPcdKgInterModuleClsPlanSet)); -+ if (!p_ClsPlanSet) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Classification plan set")); -+ -+ memset(p_ClsPlanSet, 0, sizeof(t_FmPcdKgInterModuleClsPlanSet)); -+ -+ p_ClsPlanSet->baseEntry = FmPcdKgGetClsPlanGrpBase(p_FmHc->h_FmPcd, grpId); -+ p_ClsPlanSet->numOfClsPlanEntries = FmPcdKgGetClsPlanGrpSize(p_FmHc->h_FmPcd, grpId); -+ ASSERT_COND(p_ClsPlanSet->numOfClsPlanEntries <= FM_PCD_MAX_NUM_OF_CLS_PLANS); -+ -+ if (FmHcPcdKgSetClsPlan(p_FmHc, p_ClsPlanSet) != E_OK) -+ { -+ XX_Free(p_ClsPlanSet); -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ } -+ -+ XX_Free(p_ClsPlanSet); -+ FmPcdKgDestroyClsPlanGrp(p_FmHc->h_FmPcd, grpId); -+ -+ return E_OK; -+} -+ -+t_Error FmHcPcdCcCapwapTimeoutReassm(t_Handle h_FmHc, t_FmPcdCcCapwapReassmTimeoutParams *p_CcCapwapReassmTimeoutParams ) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ t_Error err; -+ uint32_t seqNum; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmHc, E_INVALID_HANDLE,0); -+ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_CC_CAPWAP_REASSM_TIMEOUT); -+ memcpy(&p_HcFrame->hcSpecificData.ccCapwapReassmTimeout, p_CcCapwapReassmTimeoutParams, sizeof(t_FmPcdCcCapwapReassmTimeoutParams)); -+ p_HcFrame->commandSequence = seqNum; -+ BUILD_FD(sizeof(t_HcFrame)); -+ -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ return err; -+} -+ -+t_Error FmHcPcdCcIpFragScratchPollCmd(t_Handle h_FmHc, bool fill, t_FmPcdCcFragScratchPoolCmdParams *p_FmPcdCcFragScratchPoolCmdParams) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ t_Error err; -+ uint32_t seqNum; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmHc, E_INVALID_HANDLE,0); -+ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_CC_IP_FRAG_INITIALIZATION); -+ p_HcFrame->actionReg = (uint32_t)(((fill == TRUE) ? 0 : 1) << HC_HCOR_ACTION_REG_IP_FRAG_SCRATCH_POOL_CMD_SHIFT); -+ p_HcFrame->actionReg |= p_FmPcdCcFragScratchPoolCmdParams->bufferPoolId << HC_HCOR_ACTION_REG_IP_FRAG_SCRATCH_POOL_BPID; -+ if (fill == TRUE) -+ { -+ p_HcFrame->extraReg = p_FmPcdCcFragScratchPoolCmdParams->numOfBuffers; -+ } -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(sizeof(t_HcFrame)); -+ if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ p_FmPcdCcFragScratchPoolCmdParams->numOfBuffers = p_HcFrame->extraReg; -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ return E_OK; -+} -+ -+t_Error FmHcPcdCcTimeoutReassm(t_Handle h_FmHc, t_FmPcdCcReassmTimeoutParams *p_CcReassmTimeoutParams, uint8_t *p_Result) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ t_Error err; -+ uint32_t seqNum; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmHc, E_INVALID_HANDLE,0); -+ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_CC_REASSM_TIMEOUT); -+ p_HcFrame->actionReg = (uint32_t)((p_CcReassmTimeoutParams->activate ? 0 : 1) << HC_HCOR_ACTION_REG_REASSM_TIMEOUT_ACTIVE_SHIFT); -+ p_HcFrame->extraReg = (p_CcReassmTimeoutParams->tsbs << HC_HCOR_EXTRA_REG_REASSM_TIMEOUT_TSBS_SHIFT) | p_CcReassmTimeoutParams->iprcpt; -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(sizeof(t_HcFrame)); -+ if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ *p_Result = (uint8_t) -+ ((p_HcFrame->actionReg >> HC_HCOR_ACTION_REG_REASSM_TIMEOUT_RES_SHIFT) & HC_HCOR_ACTION_REG_REASSM_TIMEOUT_RES_MASK); -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ return E_OK; -+} -+ -+t_Error FmHcPcdPlcrCcGetSetParams(t_Handle h_FmHc,uint16_t absoluteProfileId, uint32_t requiredAction) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ t_Error err; -+ uint32_t tmpReg32 = 0; -+ uint32_t requiredActionTmp, requiredActionFlag; -+ uint32_t seqNum; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmHc, E_INVALID_HANDLE,0); -+ -+ /* Profile is locked by calling routine */ -+ /* WARNING - this lock will not be efficient if other HC routine will attempt to change -+ * "fmpl_pegnia" "fmpl_peynia" or "fmpl_pernia" without locking Profile ! -+ */ -+ -+ requiredActionTmp = FmPcdPlcrGetRequiredAction(p_FmHc->h_FmPcd, absoluteProfileId); -+ requiredActionFlag = FmPcdPlcrGetRequiredActionFlag(p_FmHc->h_FmPcd, absoluteProfileId); -+ -+ if (!requiredActionFlag || !(requiredActionTmp & requiredAction)) -+ { -+ if (requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA) -+ { -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ /* first read scheme and check that it is valid */ -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL); -+ p_HcFrame->actionReg = FmPcdPlcrBuildReadPlcrActionReg(absoluteProfileId); -+ p_HcFrame->extraReg = 0x00008000; -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(SIZE_OF_HC_FRAME_READ_OR_CC_DYNAMIC); -+ -+ if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ tmpReg32 = p_HcFrame->hcSpecificData.profileRegs.fmpl_pegnia; -+ if (!(tmpReg32 & (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME))) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("Next engine of this policer profile has to be assigned to FM_PCD_DONE")); -+ } -+ -+ tmpReg32 |= NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA; -+ -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL); -+ p_HcFrame->actionReg = FmPcdPlcrBuildWritePlcrActionReg(absoluteProfileId); -+ p_HcFrame->actionReg |= FmPcdPlcrBuildNiaProfileReg(TRUE, FALSE, FALSE); -+ p_HcFrame->extraReg = 0x00008000; -+ p_HcFrame->hcSpecificData.singleRegForWrite = tmpReg32; -+ -+ BUILD_FD(SIZE_OF_HC_FRAME_PROFILE_CNT); -+ -+ if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ tmpReg32 = p_HcFrame->hcSpecificData.profileRegs.fmpl_peynia; -+ if (!(tmpReg32 & (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME))) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Next engine of this policer profile has to be assigned to FM_PCD_DONE")); -+ } -+ -+ tmpReg32 |= NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA; -+ -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL); -+ p_HcFrame->actionReg = FmPcdPlcrBuildWritePlcrActionReg(absoluteProfileId); -+ p_HcFrame->actionReg |= FmPcdPlcrBuildNiaProfileReg(FALSE, TRUE, FALSE); -+ p_HcFrame->extraReg = 0x00008000; -+ p_HcFrame->hcSpecificData.singleRegForWrite = tmpReg32; -+ -+ BUILD_FD(SIZE_OF_HC_FRAME_PROFILE_CNT); -+ -+ if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ tmpReg32 = p_HcFrame->hcSpecificData.profileRegs.fmpl_pernia; -+ if (!(tmpReg32 & (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME))) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Next engine of this policer profile has to be assigned to FM_PCD_DONE")); -+ } -+ -+ tmpReg32 |= NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA; -+ -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL); -+ p_HcFrame->actionReg = FmPcdPlcrBuildWritePlcrActionReg(absoluteProfileId); -+ p_HcFrame->actionReg |= FmPcdPlcrBuildNiaProfileReg(FALSE, FALSE, TRUE); -+ p_HcFrame->extraReg = 0x00008000; -+ p_HcFrame->hcSpecificData.singleRegForWrite = tmpReg32; -+ -+ BUILD_FD(SIZE_OF_HC_FRAME_PROFILE_CNT); -+ -+ if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ } -+ } -+ -+ return E_OK; -+} -+ -+t_Error FmHcPcdPlcrSetProfile(t_Handle h_FmHc, t_Handle h_Profile, t_FmPcdPlcrProfileRegs *p_PlcrRegs) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_Error err = E_OK; -+ uint16_t profileIndx; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ uint32_t seqNum; -+ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ -+ profileIndx = FmPcdPlcrProfileGetAbsoluteId(h_Profile); -+ -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL); -+ p_HcFrame->actionReg = FmPcdPlcrBuildWritePlcrActionRegs(profileIndx); -+ p_HcFrame->extraReg = 0x00008000; -+ memcpy(&p_HcFrame->hcSpecificData.profileRegs, p_PlcrRegs, sizeof(t_FmPcdPlcrProfileRegs)); -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(sizeof(t_HcFrame)); -+ -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Error FmHcPcdPlcrDeleteProfile(t_Handle h_FmHc, t_Handle h_Profile) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ uint16_t absoluteProfileId = FmPcdPlcrProfileGetAbsoluteId(h_Profile); -+ t_Error err = E_OK; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ uint32_t seqNum; -+ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL); -+ p_HcFrame->actionReg = FmPcdPlcrBuildWritePlcrActionReg(absoluteProfileId); -+ p_HcFrame->actionReg |= 0x00008000; -+ p_HcFrame->extraReg = 0x00008000; -+ memset(&p_HcFrame->hcSpecificData.profileRegs, 0, sizeof(t_FmPcdPlcrProfileRegs)); -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(sizeof(t_HcFrame)); -+ -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Error FmHcPcdPlcrSetProfileCounter(t_Handle h_FmHc, t_Handle h_Profile, e_FmPcdPlcrProfileCounters counter, uint32_t value) -+{ -+ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ uint16_t absoluteProfileId = FmPcdPlcrProfileGetAbsoluteId(h_Profile); -+ t_Error err = E_OK; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ uint32_t seqNum; -+ -+ /* first read scheme and check that it is valid */ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL); -+ p_HcFrame->actionReg = FmPcdPlcrBuildWritePlcrActionReg(absoluteProfileId); -+ p_HcFrame->actionReg |= FmPcdPlcrBuildCounterProfileReg(counter); -+ p_HcFrame->extraReg = 0x00008000; -+ p_HcFrame->hcSpecificData.singleRegForWrite = value; -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(SIZE_OF_HC_FRAME_PROFILE_CNT); -+ -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+uint32_t FmHcPcdPlcrGetProfileCounter(t_Handle h_FmHc, t_Handle h_Profile, e_FmPcdPlcrProfileCounters counter) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ uint16_t absoluteProfileId = FmPcdPlcrProfileGetAbsoluteId(h_Profile); -+ t_Error err; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ uint32_t retVal = 0; -+ uint32_t seqNum; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmHc, E_INVALID_HANDLE,0); -+ -+ /* first read scheme and check that it is valid */ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ { -+ REPORT_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ return 0; -+ } -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_PLCR_PRFL); -+ p_HcFrame->actionReg = FmPcdPlcrBuildReadPlcrActionReg(absoluteProfileId); -+ p_HcFrame->extraReg = 0x00008000; -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(SIZE_OF_HC_FRAME_READ_OR_CC_DYNAMIC); -+ -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ if (err != E_OK) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ return 0; -+ } -+ -+ switch (counter) -+ { -+ case e_FM_PCD_PLCR_PROFILE_GREEN_PACKET_TOTAL_COUNTER: -+ retVal = p_HcFrame->hcSpecificData.profileRegs.fmpl_pegpc; -+ break; -+ case e_FM_PCD_PLCR_PROFILE_YELLOW_PACKET_TOTAL_COUNTER: -+ retVal = p_HcFrame->hcSpecificData.profileRegs.fmpl_peypc; -+ break; -+ case e_FM_PCD_PLCR_PROFILE_RED_PACKET_TOTAL_COUNTER: -+ retVal = p_HcFrame->hcSpecificData.profileRegs.fmpl_perpc; -+ break; -+ case e_FM_PCD_PLCR_PROFILE_RECOLOURED_YELLOW_PACKET_TOTAL_COUNTER: -+ retVal = p_HcFrame->hcSpecificData.profileRegs.fmpl_perypc; -+ break; -+ case e_FM_PCD_PLCR_PROFILE_RECOLOURED_RED_PACKET_TOTAL_COUNTER: -+ retVal = p_HcFrame->hcSpecificData.profileRegs.fmpl_perrpc; -+ break; -+ default: -+ REPORT_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ return retVal; -+} -+ -+t_Error FmHcKgWriteSp(t_Handle h_FmHc, uint8_t hardwarePortId, uint32_t spReg, bool add) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ t_Error err = E_OK; -+ uint32_t seqNum; -+ -+ ASSERT_COND(p_FmHc); -+ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ /* first read SP register */ -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM); -+ p_HcFrame->actionReg = FmPcdKgBuildReadPortSchemeBindActionReg(hardwarePortId); -+ p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK; -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(SIZE_OF_HC_FRAME_PORT_REGS); -+ -+ if ((err = EnQFrm(p_FmHc, &fmFd, seqNum)) != E_OK) -+ { -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ /* spReg is the first reg, so we can use it both for read and for write */ -+ if (add) -+ p_HcFrame->hcSpecificData.portRegsForRead.spReg |= spReg; -+ else -+ p_HcFrame->hcSpecificData.portRegsForRead.spReg &= ~spReg; -+ -+ p_HcFrame->actionReg = FmPcdKgBuildWritePortSchemeBindActionReg(hardwarePortId); -+ -+ BUILD_FD(sizeof(t_HcFrame)); -+ -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Error FmHcKgWriteCpp(t_Handle h_FmHc, uint8_t hardwarePortId, uint32_t cppReg) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ t_Error err = E_OK; -+ uint32_t seqNum; -+ -+ ASSERT_COND(p_FmHc); -+ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ /* first read SP register */ -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_KG_SCM); -+ p_HcFrame->actionReg = FmPcdKgBuildWritePortClsPlanBindActionReg(hardwarePortId); -+ p_HcFrame->extraReg = HC_HCOR_KG_SCHEME_REGS_MASK; -+ p_HcFrame->hcSpecificData.singleRegForWrite = cppReg; -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(sizeof(t_HcFrame)); -+ -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Error FmHcPcdCcDoDynamicChange(t_Handle h_FmHc, uint32_t oldAdAddrOffset, uint32_t newAdAddrOffset) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ t_Error err = E_OK; -+ uint32_t seqNum; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmHc, E_INVALID_HANDLE); -+ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_CC); -+ p_HcFrame->actionReg = newAdAddrOffset; -+ p_HcFrame->actionReg |= 0xc0000000; -+ p_HcFrame->extraReg = oldAdAddrOffset; -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(SIZE_OF_HC_FRAME_READ_OR_CC_DYNAMIC); -+ -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Error FmHcPcdSync(t_Handle h_FmHc) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ t_HcFrame *p_HcFrame; -+ t_DpaaFD fmFd; -+ t_Error err = E_OK; -+ uint32_t seqNum; -+ -+ ASSERT_COND(p_FmHc); -+ -+ p_HcFrame = GetBuf(p_FmHc, &seqNum); -+ if (!p_HcFrame) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("HC Frame object")); -+ memset(p_HcFrame, 0, sizeof(t_HcFrame)); -+ /* first read SP register */ -+ p_HcFrame->opcode = (uint32_t)(HC_HCOR_GBL | HC_HCOR_OPCODE_SYNC); -+ p_HcFrame->actionReg = 0; -+ p_HcFrame->extraReg = 0; -+ p_HcFrame->commandSequence = seqNum; -+ -+ BUILD_FD(sizeof(t_HcFrame)); -+ -+ err = EnQFrm(p_FmHc, &fmFd, seqNum); -+ -+ PutBuf(p_FmHc, p_HcFrame, seqNum); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Handle FmHcGetPort(t_Handle h_FmHc) -+{ -+ t_FmHc *p_FmHc = (t_FmHc*)h_FmHc; -+ return p_FmHc->h_HcPortDev; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/Makefile -@@ -0,0 +1,28 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+ -+NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc -+ -+ccflags-y += -I$(NCSW_FM_INC) -+ -+obj-y += fsl-ncsw-MAC.o -+ -+fsl-ncsw-MAC-objs := dtsec.o dtsec_mii_acc.o fm_mac.o tgec.o tgec_mii_acc.o \ -+ fman_dtsec.o fman_dtsec_mii_acc.o fman_memac.o \ -+ fman_tgec.o fman_crc32.o -+ -+ifeq ($(CONFIG_FMAN_V3H),y) -+fsl-ncsw-MAC-objs += memac.o memac_mii_acc.o fman_memac_mii_acc.o -+endif -+ifeq ($(CONFIG_FMAN_V3L),y) -+fsl-ncsw-MAC-objs += memac.o memac_mii_acc.o fman_memac_mii_acc.o -+endif -+ifeq ($(CONFIG_FMAN_ARM),y) -+fsl-ncsw-MAC-objs += memac.o memac_mii_acc.o fman_memac_mii_acc.o -+endif -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c -@@ -0,0 +1,1463 @@ -+/* -+ * Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/****************************************************************************** -+ @File dtsec.c -+ -+ @Description FMan dTSEC driver -+*//***************************************************************************/ -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "string_ext.h" -+#include "xx_ext.h" -+#include "endian_ext.h" -+#include "debug_ext.h" -+#include "crc_mac_addr_ext.h" -+ -+#include "fm_common.h" -+#include "dtsec.h" -+#include "fsl_fman_dtsec.h" -+#include "fsl_fman_dtsec_mii_acc.h" -+ -+/*****************************************************************************/ -+/* Internal routines */ -+/*****************************************************************************/ -+ -+static t_Error CheckInitParameters(t_Dtsec *p_Dtsec) -+{ -+ if (ENET_SPEED_FROM_MODE(p_Dtsec->enetMode) >= e_ENET_SPEED_10000) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet 1G MAC driver only supports 1G or lower speeds")); -+ if (p_Dtsec->macId >= FM_MAX_NUM_OF_1G_MACS) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("macId can not be greater than the number of 1G MACs")); -+ if (p_Dtsec->addr == 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet MAC Must have a valid MAC Address")); -+ if ((ENET_SPEED_FROM_MODE(p_Dtsec->enetMode) >= e_ENET_SPEED_1000) && -+ p_Dtsec->p_DtsecDriverParam->halfdup_on) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet MAC 1G can't work in half duplex")); -+ if (p_Dtsec->p_DtsecDriverParam->halfdup_on && (p_Dtsec->p_DtsecDriverParam)->loopback) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("LoopBack is not supported in halfDuplex mode")); -+#ifdef FM_RX_PREAM_4_ERRATA_DTSEC_A001 -+ if (p_Dtsec->fmMacControllerDriver.fmRevInfo.majorRev <= 6) /* fixed for rev3 */ -+ if (p_Dtsec->p_DtsecDriverParam->rx_preamble) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("preambleRxEn")); -+#endif /* FM_RX_PREAM_4_ERRATA_DTSEC_A001 */ -+ if (((p_Dtsec->p_DtsecDriverParam)->tx_preamble || (p_Dtsec->p_DtsecDriverParam)->rx_preamble) &&( (p_Dtsec->p_DtsecDriverParam)->preamble_len != 0x7)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Preamble length should be 0x7 bytes")); -+ if ((p_Dtsec->p_DtsecDriverParam)->halfdup_on && -+ (p_Dtsec->p_DtsecDriverParam->tx_time_stamp_en || p_Dtsec->p_DtsecDriverParam->rx_time_stamp_en)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dTSEC in half duplex mode has to be with 1588 timeStamping diable")); -+ if ((p_Dtsec->p_DtsecDriverParam)->rx_flow && (p_Dtsec->p_DtsecDriverParam)->rx_ctrl_acc ) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Receive control frame are not passed to the system memory so it can not be accept ")); -+ if ((p_Dtsec->p_DtsecDriverParam)->rx_prepend > MAX_PACKET_ALIGNMENT) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("packetAlignmentPadding can't be greater than %d ",MAX_PACKET_ALIGNMENT )); -+ if (((p_Dtsec->p_DtsecDriverParam)->non_back_to_back_ipg1 > MAX_INTER_PACKET_GAP) || -+ ((p_Dtsec->p_DtsecDriverParam)->non_back_to_back_ipg2 > MAX_INTER_PACKET_GAP) || -+ ((p_Dtsec->p_DtsecDriverParam)->back_to_back_ipg > MAX_INTER_PACKET_GAP)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Inter packet gap can't be greater than %d ",MAX_INTER_PACKET_GAP )); -+ if ((p_Dtsec->p_DtsecDriverParam)->halfdup_alt_backoff_val > MAX_INTER_PALTERNATE_BEB) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("alternateBackoffVal can't be greater than %d ",MAX_INTER_PALTERNATE_BEB )); -+ if ((p_Dtsec->p_DtsecDriverParam)->halfdup_retransmit > MAX_RETRANSMISSION) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("maxRetransmission can't be greater than %d ",MAX_RETRANSMISSION )); -+ if ((p_Dtsec->p_DtsecDriverParam)->halfdup_coll_window > MAX_COLLISION_WINDOW) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("collisionWindow can't be greater than %d ",MAX_COLLISION_WINDOW )); -+ -+ /* If Auto negotiation process is disabled, need to */ -+ /* Set up the PHY using the MII Management Interface */ -+ if (p_Dtsec->p_DtsecDriverParam->tbipa > MAX_PHYS) -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, ("PHY address (should be 0-%d)", MAX_PHYS)); -+ if (!p_Dtsec->f_Exception) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("uninitialized f_Exception")); -+ if (!p_Dtsec->f_Event) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("uninitialized f_Event")); -+ -+#ifdef FM_LEN_CHECK_ERRATA_FMAN_SW002 -+ if (p_Dtsec->p_DtsecDriverParam->rx_len_check) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("LengthCheck!")); -+#endif /* FM_LEN_CHECK_ERRATA_FMAN_SW002 */ -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static uint32_t GetMacAddrHashCode(uint64_t ethAddr) -+{ -+ uint32_t crc; -+ -+ /* CRC calculation */ -+ GET_MAC_ADDR_CRC(ethAddr, crc); -+ -+ crc = GetMirror32(crc); -+ -+ return crc; -+} -+ -+/* ......................................................................... */ -+ -+static void UpdateStatistics(t_Dtsec *p_Dtsec) -+{ -+ uint32_t car1, car2; -+ -+ fman_dtsec_get_clear_carry_regs(p_Dtsec->p_MemMap, &car1, &car2); -+ -+ if (car1) -+ { -+ if (car1 & CAR1_TR64) -+ p_Dtsec->internalStatistics.tr64 += VAL22BIT; -+ if (car1 & CAR1_TR127) -+ p_Dtsec->internalStatistics.tr127 += VAL22BIT; -+ if (car1 & CAR1_TR255) -+ p_Dtsec->internalStatistics.tr255 += VAL22BIT; -+ if (car1 & CAR1_TR511) -+ p_Dtsec->internalStatistics.tr511 += VAL22BIT; -+ if (car1 & CAR1_TRK1) -+ p_Dtsec->internalStatistics.tr1k += VAL22BIT; -+ if (car1 & CAR1_TRMAX) -+ p_Dtsec->internalStatistics.trmax += VAL22BIT; -+ if (car1 & CAR1_TRMGV) -+ p_Dtsec->internalStatistics.trmgv += VAL22BIT; -+ if (car1 & CAR1_RBYT) -+ p_Dtsec->internalStatistics.rbyt += (uint64_t)VAL32BIT; -+ if (car1 & CAR1_RPKT) -+ p_Dtsec->internalStatistics.rpkt += VAL22BIT; -+ if (car1 & CAR1_RMCA) -+ p_Dtsec->internalStatistics.rmca += VAL22BIT; -+ if (car1 & CAR1_RBCA) -+ p_Dtsec->internalStatistics.rbca += VAL22BIT; -+ if (car1 & CAR1_RXPF) -+ p_Dtsec->internalStatistics.rxpf += VAL16BIT; -+ if (car1 & CAR1_RALN) -+ p_Dtsec->internalStatistics.raln += VAL16BIT; -+ if (car1 & CAR1_RFLR) -+ p_Dtsec->internalStatistics.rflr += VAL16BIT; -+ if (car1 & CAR1_RCDE) -+ p_Dtsec->internalStatistics.rcde += VAL16BIT; -+ if (car1 & CAR1_RCSE) -+ p_Dtsec->internalStatistics.rcse += VAL16BIT; -+ if (car1 & CAR1_RUND) -+ p_Dtsec->internalStatistics.rund += VAL16BIT; -+ if (car1 & CAR1_ROVR) -+ p_Dtsec->internalStatistics.rovr += VAL16BIT; -+ if (car1 & CAR1_RFRG) -+ p_Dtsec->internalStatistics.rfrg += VAL16BIT; -+ if (car1 & CAR1_RJBR) -+ p_Dtsec->internalStatistics.rjbr += VAL16BIT; -+ if (car1 & CAR1_RDRP) -+ p_Dtsec->internalStatistics.rdrp += VAL16BIT; -+ } -+ if (car2) -+ { -+ if (car2 & CAR2_TFCS) -+ p_Dtsec->internalStatistics.tfcs += VAL12BIT; -+ if (car2 & CAR2_TBYT) -+ p_Dtsec->internalStatistics.tbyt += (uint64_t)VAL32BIT; -+ if (car2 & CAR2_TPKT) -+ p_Dtsec->internalStatistics.tpkt += VAL22BIT; -+ if (car2 & CAR2_TMCA) -+ p_Dtsec->internalStatistics.tmca += VAL22BIT; -+ if (car2 & CAR2_TBCA) -+ p_Dtsec->internalStatistics.tbca += VAL22BIT; -+ if (car2 & CAR2_TXPF) -+ p_Dtsec->internalStatistics.txpf += VAL16BIT; -+ if (car2 & CAR2_TDRP) -+ p_Dtsec->internalStatistics.tdrp += VAL16BIT; -+ } -+} -+ -+/* .............................................................................. */ -+ -+static uint16_t DtsecGetMaxFrameLength(t_Handle h_Dtsec) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_VALUE(p_Dtsec, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_VALUE(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE, 0); -+ -+ return fman_dtsec_get_max_frame_len(p_Dtsec->p_MemMap); -+} -+ -+/* .............................................................................. */ -+ -+static void DtsecIsr(t_Handle h_Dtsec) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ uint32_t event; -+ struct dtsec_regs *p_DtsecMemMap = p_Dtsec->p_MemMap; -+ -+ /* do not handle MDIO events */ -+ event = fman_dtsec_get_event(p_DtsecMemMap, (uint32_t)(~(DTSEC_IMASK_MMRDEN | DTSEC_IMASK_MMWREN))); -+ -+ event &= fman_dtsec_get_interrupt_mask(p_DtsecMemMap); -+ -+ fman_dtsec_ack_event(p_DtsecMemMap, event); -+ -+ if (event & DTSEC_IMASK_BREN) -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_BAB_RX); -+ if (event & DTSEC_IMASK_RXCEN) -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_RX_CTL); -+ if (event & DTSEC_IMASK_MSROEN) -+ UpdateStatistics(p_Dtsec); -+ if (event & DTSEC_IMASK_GTSCEN) -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET); -+ if (event & DTSEC_IMASK_BTEN) -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_BAB_TX); -+ if (event & DTSEC_IMASK_TXCEN) -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_TX_CTL); -+ if (event & DTSEC_IMASK_TXEEN) -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_TX_ERR); -+ if (event & DTSEC_IMASK_LCEN) -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_LATE_COL); -+ if (event & DTSEC_IMASK_CRLEN) -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_COL_RET_LMT); -+ if (event & DTSEC_IMASK_XFUNEN) -+ { -+#ifdef FM_TX_LOCKUP_ERRATA_DTSEC6 -+ if (p_Dtsec->fmMacControllerDriver.fmRevInfo.majorRev == 2) -+ { -+ uint32_t tpkt1, tmpReg1, tpkt2, tmpReg2, i; -+ /* a. Write 0x00E0_0C00 to DTSEC_ID */ -+ /* This is a read only regidter */ -+ -+ /* b. Read and save the value of TPKT */ -+ tpkt1 = GET_UINT32(p_DtsecMemMap->tpkt); -+ -+ /* c. Read the register at dTSEC address offset 0x32C */ -+ tmpReg1 = GET_UINT32(*(uint32_t*)((uint8_t*)p_DtsecMemMap + 0x32c)); -+ -+ /* d. Compare bits [9:15] to bits [25:31] of the register at address offset 0x32C. */ -+ if ((tmpReg1 & 0x007F0000) != (tmpReg1 & 0x0000007F)) -+ { -+ /* If they are not equal, save the value of this register and wait for at least -+ * MAXFRM*16 ns */ -+ XX_UDelay((uint32_t)(MIN(DtsecGetMaxFrameLength(p_Dtsec)*16/1000, 1))); -+ } -+ -+ /* e. Read and save TPKT again and read the register at dTSEC address offset -+ 0x32C again*/ -+ tpkt2 = GET_UINT32(p_DtsecMemMap->tpkt); -+ tmpReg2 = GET_UINT32(*(uint32_t*)((uint8_t*)p_DtsecMemMap + 0x32c)); -+ -+ /* f. Compare the value of TPKT saved in step b to value read in step e. Also -+ compare bits [9:15] of the register at offset 0x32C saved in step d to the value -+ of bits [9:15] saved in step e. If the two registers values are unchanged, then -+ the transmit portion of the dTSEC controller is locked up and the user should -+ proceed to the recover sequence. */ -+ if ((tpkt1 == tpkt2) && ((tmpReg1 & 0x007F0000) == (tmpReg2 & 0x007F0000))) -+ { -+ /* recover sequence */ -+ -+ /* a.Write a 1 to RCTRL[GRS]*/ -+ -+ WRITE_UINT32(p_DtsecMemMap->rctrl, GET_UINT32(p_DtsecMemMap->rctrl) | RCTRL_GRS); -+ -+ /* b.Wait until IEVENT[GRSC]=1, or at least 100 us has elapsed. */ -+ for (i = 0 ; i < 100 ; i++ ) -+ { -+ if (GET_UINT32(p_DtsecMemMap->ievent) & DTSEC_IMASK_GRSCEN) -+ break; -+ XX_UDelay(1); -+ } -+ if (GET_UINT32(p_DtsecMemMap->ievent) & DTSEC_IMASK_GRSCEN) -+ WRITE_UINT32(p_DtsecMemMap->ievent, DTSEC_IMASK_GRSCEN); -+ else -+ DBG(INFO,("Rx lockup due to dTSEC Tx lockup")); -+ -+ /* c.Write a 1 to bit n of FM_RSTC (offset 0x0CC of FPM)*/ -+ FmResetMac(p_Dtsec->fmMacControllerDriver.h_Fm, e_FM_MAC_1G, p_Dtsec->fmMacControllerDriver.macId); -+ -+ /* d.Wait 4 Tx clocks (32 ns) */ -+ XX_UDelay(1); -+ -+ /* e.Write a 0 to bit n of FM_RSTC. */ -+ /* cleared by FMAN */ -+ } -+ } -+#endif /* FM_TX_LOCKUP_ERRATA_DTSEC6 */ -+ -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_TX_FIFO_UNDRN); -+ } -+ if (event & DTSEC_IMASK_MAGEN) -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_MAG_PCKT); -+ if (event & DTSEC_IMASK_GRSCEN) -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET); -+ if (event & DTSEC_IMASK_TDPEEN) -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_TX_DATA_ERR); -+ if (event & DTSEC_IMASK_RDPEEN) -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_RX_DATA_ERR); -+ -+ /* - masked interrupts */ -+ ASSERT_COND(!(event & DTSEC_IMASK_ABRTEN)); -+ ASSERT_COND(!(event & DTSEC_IMASK_IFERREN)); -+} -+ -+static void DtsecMdioIsr(t_Handle h_Dtsec) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ uint32_t event; -+ struct dtsec_regs *p_DtsecMemMap = p_Dtsec->p_MemMap; -+ -+ event = GET_UINT32(p_DtsecMemMap->ievent); -+ /* handle only MDIO events */ -+ event &= (DTSEC_IMASK_MMRDEN | DTSEC_IMASK_MMWREN); -+ if (event) -+ { -+ event &= GET_UINT32(p_DtsecMemMap->imask); -+ -+ WRITE_UINT32(p_DtsecMemMap->ievent, event); -+ -+ if (event & DTSEC_IMASK_MMRDEN) -+ p_Dtsec->f_Event(p_Dtsec->h_App, e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET); -+ if (event & DTSEC_IMASK_MMWREN) -+ p_Dtsec->f_Event(p_Dtsec->h_App, e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET); -+ } -+} -+ -+static void Dtsec1588Isr(t_Handle h_Dtsec) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ uint32_t event; -+ struct dtsec_regs *p_DtsecMemMap = p_Dtsec->p_MemMap; -+ -+ if (p_Dtsec->ptpTsuEnabled) -+ { -+ event = fman_dtsec_check_and_clear_tmr_event(p_DtsecMemMap); -+ -+ if (event) -+ { -+ ASSERT_COND(event & TMR_PEVENT_TSRE); -+ p_Dtsec->f_Exception(p_Dtsec->h_App, e_FM_MAC_EX_1G_1588_TS_RX_ERR); -+ } -+ } -+} -+ -+/* ........................................................................... */ -+ -+static void FreeInitResources(t_Dtsec *p_Dtsec) -+{ -+ if (p_Dtsec->mdioIrq != NO_IRQ) -+ { -+ XX_DisableIntr(p_Dtsec->mdioIrq); -+ XX_FreeIntr(p_Dtsec->mdioIrq); -+ } -+ FmUnregisterIntr(p_Dtsec->fmMacControllerDriver.h_Fm, e_FM_MOD_1G_MAC, p_Dtsec->macId, e_FM_INTR_TYPE_ERR); -+ FmUnregisterIntr(p_Dtsec->fmMacControllerDriver.h_Fm, e_FM_MOD_1G_MAC, p_Dtsec->macId, e_FM_INTR_TYPE_NORMAL); -+ -+ /* release the driver's group hash table */ -+ FreeHashTable(p_Dtsec->p_MulticastAddrHash); -+ p_Dtsec->p_MulticastAddrHash = NULL; -+ -+ /* release the driver's individual hash table */ -+ FreeHashTable(p_Dtsec->p_UnicastAddrHash); -+ p_Dtsec->p_UnicastAddrHash = NULL; -+} -+ -+/* ........................................................................... */ -+ -+static t_Error GracefulStop(t_Dtsec *p_Dtsec, e_CommMode mode) -+{ -+ struct dtsec_regs *p_MemMap; -+ -+ ASSERT_COND(p_Dtsec); -+ -+ p_MemMap = p_Dtsec->p_MemMap; -+ ASSERT_COND(p_MemMap); -+ -+ /* Assert the graceful transmit stop bit */ -+ if (mode & e_COMM_MODE_RX) -+ { -+ fman_dtsec_stop_rx(p_MemMap); -+ -+#ifdef FM_GRS_ERRATA_DTSEC_A002 -+ if (p_Dtsec->fmMacControllerDriver.fmRevInfo.majorRev == 2) -+ XX_UDelay(100); -+#else /* FM_GRS_ERRATA_DTSEC_A002 */ -+#ifdef FM_GTS_AFTER_DROPPED_FRAME_ERRATA_DTSEC_A004839 -+ XX_UDelay(10); -+#endif /* FM_GTS_AFTER_DROPPED_FRAME_ERRATA_DTSEC_A004839 */ -+#endif /* FM_GRS_ERRATA_DTSEC_A002 */ -+ } -+ -+ if (mode & e_COMM_MODE_TX) -+#if defined(FM_GTS_ERRATA_DTSEC_A004) || defined(FM_GTS_AFTER_MAC_ABORTED_FRAME_ERRATA_DTSEC_A0012) -+ if (p_Dtsec->fmMacControllerDriver.fmRevInfo.majorRev == 2) -+ DBG(INFO, ("GTS not supported due to DTSEC_A004 errata.")); -+#else /* not defined(FM_GTS_ERRATA_DTSEC_A004) ||... */ -+#ifdef FM_GTS_UNDERRUN_ERRATA_DTSEC_A0014 -+ DBG(INFO, ("GTS not supported due to DTSEC_A0014 errata.")); -+#else /* FM_GTS_UNDERRUN_ERRATA_DTSEC_A0014 */ -+ fman_dtsec_stop_tx(p_MemMap); -+#endif /* FM_GTS_UNDERRUN_ERRATA_DTSEC_A0014 */ -+#endif /* defined(FM_GTS_ERRATA_DTSEC_A004) ||... */ -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error GracefulRestart(t_Dtsec *p_Dtsec, e_CommMode mode) -+{ -+ struct dtsec_regs *p_MemMap; -+ -+ ASSERT_COND(p_Dtsec); -+ p_MemMap = p_Dtsec->p_MemMap; -+ ASSERT_COND(p_MemMap); -+ -+ /* clear the graceful receive stop bit */ -+ if (mode & e_COMM_MODE_TX) -+ fman_dtsec_start_tx(p_MemMap); -+ -+ if (mode & e_COMM_MODE_RX) -+ fman_dtsec_start_rx(p_MemMap); -+ -+ return E_OK; -+} -+ -+ -+/*****************************************************************************/ -+/* dTSEC Configs modification functions */ -+/*****************************************************************************/ -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecConfigLoopback(t_Handle h_Dtsec, bool newVal) -+{ -+ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ p_Dtsec->p_DtsecDriverParam->loopback = newVal; -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecConfigMaxFrameLength(t_Handle h_Dtsec, uint16_t newVal) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ p_Dtsec->p_DtsecDriverParam->maximum_frame = newVal; -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecConfigPadAndCrc(t_Handle h_Dtsec, bool newVal) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ p_Dtsec->p_DtsecDriverParam->tx_pad_crc = newVal; -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecConfigHalfDuplex(t_Handle h_Dtsec, bool newVal) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ p_Dtsec->p_DtsecDriverParam->halfdup_on = newVal; -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecConfigTbiPhyAddr(t_Handle h_Dtsec, uint8_t newVal) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ p_Dtsec->p_DtsecDriverParam->tbi_phy_addr = newVal; -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecConfigLengthCheck(t_Handle h_Dtsec, bool newVal) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ p_Dtsec->p_DtsecDriverParam->rx_len_check = newVal; -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecConfigException(t_Handle h_Dtsec, e_FmMacExceptions exception, bool enable) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ uint32_t bitMask = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ if (exception != e_FM_MAC_EX_1G_1588_TS_RX_ERR) -+ { -+ GET_EXCEPTION_FLAG(bitMask, exception); -+ if (bitMask) -+ { -+ if (enable) -+ p_Dtsec->exceptions |= bitMask; -+ else -+ p_Dtsec->exceptions &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); -+ } -+ else -+ { -+ if (!p_Dtsec->ptpTsuEnabled) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exception valid for 1588 only")); -+ -+ if (enable) -+ p_Dtsec->enTsuErrExeption = TRUE; -+ else -+ p_Dtsec->enTsuErrExeption = FALSE; -+ } -+ -+ return E_OK; -+} -+ -+ -+/*****************************************************************************/ -+/* dTSEC Run Time API functions */ -+/*****************************************************************************/ -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecEnable(t_Handle h_Dtsec, e_CommMode mode) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ fman_dtsec_enable(p_Dtsec->p_MemMap, -+ (bool)!!(mode & e_COMM_MODE_RX), -+ (bool)!!(mode & e_COMM_MODE_TX)); -+ -+ GracefulRestart(p_Dtsec, mode); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecDisable (t_Handle h_Dtsec, e_CommMode mode) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ GracefulStop(p_Dtsec, mode); -+ -+ fman_dtsec_disable(p_Dtsec->p_MemMap, -+ (bool)!!(mode & e_COMM_MODE_RX), -+ (bool)!!(mode & e_COMM_MODE_TX)); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecSetTxPauseFrames(t_Handle h_Dtsec, -+ uint8_t priority, -+ uint16_t pauseTime, -+ uint16_t threshTime) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ UNUSED(priority);UNUSED(threshTime); -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+#ifdef FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 -+ if (p_Dtsec->fmMacControllerDriver.fmRevInfo.majorRev == 2) -+ if (0 < pauseTime && pauseTime <= 320) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, -+ ("This pause-time value of %d is illegal due to errata dTSEC-A003!" -+ " value should be greater than 320.")); -+#endif /* FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 */ -+ -+ fman_dtsec_set_tx_pause_frames(p_Dtsec->p_MemMap, pauseTime); -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+/* backward compatibility. will be removed in the future. */ -+static t_Error DtsecTxMacPause(t_Handle h_Dtsec, uint16_t pauseTime) -+{ -+ return DtsecSetTxPauseFrames(h_Dtsec, 0, pauseTime, 0); -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecRxIgnoreMacPause(t_Handle h_Dtsec, bool en) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ bool accept_pause = !en; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ fman_dtsec_handle_rx_pause(p_Dtsec->p_MemMap, accept_pause); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecEnable1588TimeStamp(t_Handle h_Dtsec) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ p_Dtsec->ptpTsuEnabled = TRUE; -+ fman_dtsec_set_ts(p_Dtsec->p_MemMap, TRUE); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecDisable1588TimeStamp(t_Handle h_Dtsec) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ p_Dtsec->ptpTsuEnabled = FALSE; -+ fman_dtsec_set_ts(p_Dtsec->p_MemMap, FALSE); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecGetStatistics(t_Handle h_Dtsec, t_FmMacStatistics *p_Statistics) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ struct dtsec_regs *p_DtsecMemMap; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_Statistics, E_NULL_POINTER); -+ -+ p_DtsecMemMap = p_Dtsec->p_MemMap; -+ -+ if (p_Dtsec->statisticsLevel == e_FM_MAC_NONE_STATISTICS) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Statistics disabled")); -+ -+ memset(p_Statistics, 0xff, sizeof(t_FmMacStatistics)); -+ -+ if (p_Dtsec->statisticsLevel == e_FM_MAC_FULL_STATISTICS) -+ { -+ p_Statistics->eStatPkts64 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TR64) -+ + p_Dtsec->internalStatistics.tr64; -+ p_Statistics->eStatPkts65to127 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TR127) -+ + p_Dtsec->internalStatistics.tr127; -+ p_Statistics->eStatPkts128to255 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TR255) -+ + p_Dtsec->internalStatistics.tr255; -+ p_Statistics->eStatPkts256to511 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TR511) -+ + p_Dtsec->internalStatistics.tr511; -+ p_Statistics->eStatPkts512to1023 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TR1K) -+ + p_Dtsec->internalStatistics.tr1k; -+ p_Statistics->eStatPkts1024to1518 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TRMAX) -+ + p_Dtsec->internalStatistics.trmax; -+ p_Statistics->eStatPkts1519to1522 = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TRMGV) -+ + p_Dtsec->internalStatistics.trmgv; -+ -+ /* MIB II */ -+ p_Statistics->ifInOctets = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RBYT) -+ + p_Dtsec->internalStatistics.rbyt; -+ p_Statistics->ifInPkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RPKT) -+ + p_Dtsec->internalStatistics.rpkt; -+ p_Statistics->ifInUcastPkts = 0; -+ p_Statistics->ifInMcastPkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RMCA) -+ + p_Dtsec->internalStatistics.rmca; -+ p_Statistics->ifInBcastPkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RBCA) -+ + p_Dtsec->internalStatistics.rbca; -+ p_Statistics->ifOutOctets = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TBYT) -+ + p_Dtsec->internalStatistics.tbyt; -+ p_Statistics->ifOutPkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TPKT) -+ + p_Dtsec->internalStatistics.tpkt; -+ p_Statistics->ifOutUcastPkts = 0; -+ p_Statistics->ifOutMcastPkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TMCA) -+ + p_Dtsec->internalStatistics.tmca; -+ p_Statistics->ifOutBcastPkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TBCA) -+ + p_Dtsec->internalStatistics.tbca; -+ } -+ -+ p_Statistics->eStatFragments = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RFRG) -+ + p_Dtsec->internalStatistics.rfrg; -+ p_Statistics->eStatJabbers = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RJBR) -+ + p_Dtsec->internalStatistics.rjbr; -+ p_Statistics->eStatsDropEvents = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RDRP) -+ + p_Dtsec->internalStatistics.rdrp; -+ p_Statistics->eStatCRCAlignErrors = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RALN) -+ + p_Dtsec->internalStatistics.raln; -+ p_Statistics->eStatUndersizePkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RUND) -+ + p_Dtsec->internalStatistics.rund; -+ p_Statistics->eStatOversizePkts = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_ROVR) -+ + p_Dtsec->internalStatistics.rovr; -+ p_Statistics->reStatPause = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_RXPF) -+ + p_Dtsec->internalStatistics.rxpf; -+ p_Statistics->teStatPause = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TXPF) -+ + p_Dtsec->internalStatistics.txpf; -+ p_Statistics->ifInDiscards = p_Statistics->eStatsDropEvents; -+ p_Statistics->ifInErrors = p_Statistics->eStatsDropEvents + p_Statistics->eStatCRCAlignErrors -+ + fman_dtsec_get_stat_counter(p_DtsecMemMap,E_DTSEC_STAT_RFLR) + p_Dtsec->internalStatistics.rflr -+ + fman_dtsec_get_stat_counter(p_DtsecMemMap,E_DTSEC_STAT_RCDE) + p_Dtsec->internalStatistics.rcde -+ + fman_dtsec_get_stat_counter(p_DtsecMemMap,E_DTSEC_STAT_RCSE) + p_Dtsec->internalStatistics.rcse; -+ -+ p_Statistics->ifOutDiscards = fman_dtsec_get_stat_counter(p_DtsecMemMap, E_DTSEC_STAT_TDRP) -+ + p_Dtsec->internalStatistics.tdrp; -+ p_Statistics->ifOutErrors = p_Statistics->ifOutDiscards /**< Number of frames transmitted with error: */ -+ + fman_dtsec_get_stat_counter(p_DtsecMemMap,E_DTSEC_STAT_TFCS) -+ + p_Dtsec->internalStatistics.tfcs; -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecModifyMacAddress (t_Handle h_Dtsec, t_EnetAddr *p_EnetAddr) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ /* Initialize MAC Station Address registers (1 & 2) */ -+ /* Station address have to be swapped (big endian to little endian */ -+ p_Dtsec->addr = ENET_ADDR_TO_UINT64(*p_EnetAddr); -+ fman_dtsec_set_mac_address(p_Dtsec->p_MemMap, (uint8_t *)(*p_EnetAddr)); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecResetCounters (t_Handle h_Dtsec) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ /* clear HW counters */ -+ fman_dtsec_reset_stat(p_Dtsec->p_MemMap); -+ -+ /* clear SW counters holding carries */ -+ memset(&p_Dtsec->internalStatistics, 0, sizeof(t_InternalStatistics)); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecAddExactMatchMacAddress(t_Handle h_Dtsec, t_EnetAddr *p_EthAddr) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *) h_Dtsec; -+ uint64_t ethAddr; -+ uint8_t paddrNum; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr); -+ -+ if (ethAddr & GROUP_ADDRESS) -+ /* Multicast address has no effect in PADDR */ -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Multicast address")); -+ -+ /* Make sure no PADDR contains this address */ -+ for (paddrNum = 0; paddrNum < DTSEC_NUM_OF_PADDRS; paddrNum++) -+ if (p_Dtsec->indAddrRegUsed[paddrNum]) -+ if (p_Dtsec->paddr[paddrNum] == ethAddr) -+ RETURN_ERROR(MAJOR, E_ALREADY_EXISTS, NO_MSG); -+ -+ /* Find first unused PADDR */ -+ for (paddrNum = 0; paddrNum < DTSEC_NUM_OF_PADDRS; paddrNum++) -+ if (!(p_Dtsec->indAddrRegUsed[paddrNum])) -+ { -+ /* mark this PADDR as used */ -+ p_Dtsec->indAddrRegUsed[paddrNum] = TRUE; -+ /* store address */ -+ p_Dtsec->paddr[paddrNum] = ethAddr; -+ -+ /* put in hardware */ -+ fman_dtsec_add_addr_in_paddr(p_Dtsec->p_MemMap, (uint64_t)PTR_TO_UINT(ðAddr), paddrNum); -+ p_Dtsec->numOfIndAddrInRegs++; -+ -+ return E_OK; -+ } -+ -+ /* No free PADDR */ -+ RETURN_ERROR(MAJOR, E_FULL, NO_MSG); -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecDelExactMatchMacAddress(t_Handle h_Dtsec, t_EnetAddr *p_EthAddr) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *) h_Dtsec; -+ uint64_t ethAddr; -+ uint8_t paddrNum; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr); -+ -+ /* Find used PADDR containing this address */ -+ for (paddrNum = 0; paddrNum < DTSEC_NUM_OF_PADDRS; paddrNum++) -+ { -+ if ((p_Dtsec->indAddrRegUsed[paddrNum]) && -+ (p_Dtsec->paddr[paddrNum] == ethAddr)) -+ { -+ /* mark this PADDR as not used */ -+ p_Dtsec->indAddrRegUsed[paddrNum] = FALSE; -+ /* clear in hardware */ -+ fman_dtsec_clear_addr_in_paddr(p_Dtsec->p_MemMap, paddrNum); -+ p_Dtsec->numOfIndAddrInRegs--; -+ -+ return E_OK; -+ } -+ } -+ -+ RETURN_ERROR(MAJOR, E_NOT_FOUND, NO_MSG); -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecAddHashMacAddress(t_Handle h_Dtsec, t_EnetAddr *p_EthAddr) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ t_EthHashEntry *p_HashEntry; -+ uint64_t ethAddr; -+ int32_t bucket; -+ uint32_t crc; -+ bool mcast, ghtx; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr); -+ -+ ghtx = (bool)((fman_dtsec_get_rctrl(p_Dtsec->p_MemMap) & RCTRL_GHTX) ? TRUE : FALSE); -+ mcast = (bool)((ethAddr & MAC_GROUP_ADDRESS) ? TRUE : FALSE); -+ -+ if (ghtx && !mcast) /* Cannot handle unicast mac addr when GHTX is on */ -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Could not compute hash bucket")); -+ -+ crc = GetMacAddrHashCode(ethAddr); -+ -+ /* considering the 9 highest order bits in crc H[8:0]: -+ * if ghtx = 0 H[8:6] (highest order 3 bits) identify the hash register -+ * and H[5:1] (next 5 bits) identify the hash bit -+ * if ghts = 1 H[8:5] (highest order 4 bits) identify the hash register -+ * and H[4:0] (next 5 bits) identify the hash bit. -+ * -+ * In bucket index output the low 5 bits identify the hash register bit, -+ * while the higher 4 bits identify the hash register -+ */ -+ -+ if (ghtx) -+ bucket = (int32_t)((crc >> 23) & 0x1ff); -+ else { -+ bucket = (int32_t)((crc >> 24) & 0xff); -+ /* if !ghtx and mcast the bit must be set in gaddr instead of igaddr. */ -+ if (mcast) -+ bucket += 0x100; -+ } -+ -+ fman_dtsec_set_bucket(p_Dtsec->p_MemMap, bucket, TRUE); -+ -+ /* Create element to be added to the driver hash table */ -+ p_HashEntry = (t_EthHashEntry *)XX_Malloc(sizeof(t_EthHashEntry)); -+ p_HashEntry->addr = ethAddr; -+ INIT_LIST(&p_HashEntry->node); -+ -+ if (ethAddr & MAC_GROUP_ADDRESS) -+ /* Group Address */ -+ LIST_AddToTail(&(p_HashEntry->node), &(p_Dtsec->p_MulticastAddrHash->p_Lsts[bucket])); -+ else -+ LIST_AddToTail(&(p_HashEntry->node), &(p_Dtsec->p_UnicastAddrHash->p_Lsts[bucket])); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecDelHashMacAddress(t_Handle h_Dtsec, t_EnetAddr *p_EthAddr) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ t_List *p_Pos; -+ t_EthHashEntry *p_HashEntry = NULL; -+ uint64_t ethAddr; -+ int32_t bucket; -+ uint32_t crc; -+ bool mcast, ghtx; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr); -+ -+ ghtx = (bool)((fman_dtsec_get_rctrl(p_Dtsec->p_MemMap) & RCTRL_GHTX) ? TRUE : FALSE); -+ mcast = (bool)((ethAddr & MAC_GROUP_ADDRESS) ? TRUE : FALSE); -+ -+ if (ghtx && !mcast) /* Cannot handle unicast mac addr when GHTX is on */ -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Could not compute hash bucket")); -+ -+ crc = GetMacAddrHashCode(ethAddr); -+ -+ if (ghtx) -+ bucket = (int32_t)((crc >> 23) & 0x1ff); -+ else { -+ bucket = (int32_t)((crc >> 24) & 0xff); -+ /* if !ghtx and mcast the bit must be set in gaddr instead of igaddr. */ -+ if (mcast) -+ bucket += 0x100; -+ } -+ -+ if (ethAddr & MAC_GROUP_ADDRESS) -+ { -+ /* Group Address */ -+ LIST_FOR_EACH(p_Pos, &(p_Dtsec->p_MulticastAddrHash->p_Lsts[bucket])) -+ { -+ p_HashEntry = ETH_HASH_ENTRY_OBJ(p_Pos); -+ if (p_HashEntry->addr == ethAddr) -+ { -+ LIST_DelAndInit(&p_HashEntry->node); -+ XX_Free(p_HashEntry); -+ break; -+ } -+ } -+ if (LIST_IsEmpty(&p_Dtsec->p_MulticastAddrHash->p_Lsts[bucket])) -+ fman_dtsec_set_bucket(p_Dtsec->p_MemMap, bucket, FALSE); -+ } -+ else -+ { -+ /* Individual Address */ -+ LIST_FOR_EACH(p_Pos, &(p_Dtsec->p_UnicastAddrHash->p_Lsts[bucket])) -+ { -+ p_HashEntry = ETH_HASH_ENTRY_OBJ(p_Pos); -+ if (p_HashEntry->addr == ethAddr) -+ { -+ LIST_DelAndInit(&p_HashEntry->node); -+ XX_Free(p_HashEntry); -+ break; -+ } -+ } -+ if (LIST_IsEmpty(&p_Dtsec->p_UnicastAddrHash->p_Lsts[bucket])) -+ fman_dtsec_set_bucket(p_Dtsec->p_MemMap, bucket, FALSE); -+ } -+ -+ /* address does not exist */ -+ ASSERT_COND(p_HashEntry != NULL); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecSetPromiscuous(t_Handle h_Dtsec, bool newVal) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ fman_dtsec_set_uc_promisc(p_Dtsec->p_MemMap, newVal); -+ fman_dtsec_set_mc_promisc(p_Dtsec->p_MemMap, newVal); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecSetStatistics(t_Handle h_Dtsec, e_FmMacStatisticsLevel statisticsLevel) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ p_Dtsec->statisticsLevel = statisticsLevel; -+ -+ err = (t_Error)fman_dtsec_set_stat_level(p_Dtsec->p_MemMap, -+ (enum dtsec_stat_level)statisticsLevel); -+ if (err != E_OK) -+ return err; -+ -+ switch (statisticsLevel) -+ { -+ case (e_FM_MAC_NONE_STATISTICS): -+ p_Dtsec->exceptions &= ~DTSEC_IMASK_MSROEN; -+ break; -+ case (e_FM_MAC_PARTIAL_STATISTICS): -+ p_Dtsec->exceptions |= DTSEC_IMASK_MSROEN; -+ break; -+ case (e_FM_MAC_FULL_STATISTICS): -+ p_Dtsec->exceptions |= DTSEC_IMASK_MSROEN; -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecSetWakeOnLan(t_Handle h_Dtsec, bool en) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ fman_dtsec_set_wol(p_Dtsec->p_MemMap, en); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecAdjustLink(t_Handle h_Dtsec, e_EnetSpeed speed, bool fullDuplex) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ int err; -+ enum enet_interface enet_interface; -+ enum enet_speed enet_speed; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ p_Dtsec->enetMode = MAKE_ENET_MODE(ENET_INTERFACE_FROM_MODE(p_Dtsec->enetMode), speed); -+ enet_interface = (enum enet_interface) ENET_INTERFACE_FROM_MODE(p_Dtsec->enetMode); -+ enet_speed = (enum enet_speed) ENET_SPEED_FROM_MODE(p_Dtsec->enetMode); -+ p_Dtsec->halfDuplex = !fullDuplex; -+ -+ err = fman_dtsec_adjust_link(p_Dtsec->p_MemMap, enet_interface, enet_speed, fullDuplex); -+ -+ if (err == -EINVAL) -+ RETURN_ERROR(MAJOR, E_CONFLICT, ("Ethernet interface does not support Half Duplex mode")); -+ -+ return (t_Error)err; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecRestartAutoneg(t_Handle h_Dtsec) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ uint16_t tmpReg16; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ DTSEC_MII_ReadPhyReg(p_Dtsec, p_Dtsec->tbi_phy_addr, 0, &tmpReg16); -+ -+ tmpReg16 &= ~( PHY_CR_SPEED0 | PHY_CR_SPEED1 ); -+ tmpReg16 |= (PHY_CR_ANE | PHY_CR_RESET_AN | PHY_CR_FULLDUPLEX | PHY_CR_SPEED1); -+ -+ DTSEC_MII_WritePhyReg(p_Dtsec, p_Dtsec->tbi_phy_addr, 0, tmpReg16); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecGetId(t_Handle h_Dtsec, uint32_t *macId) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ *macId = p_Dtsec->macId; -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecGetVersion(t_Handle h_Dtsec, uint32_t *macVersion) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ *macVersion = fman_dtsec_get_revision(p_Dtsec->p_MemMap); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecSetException(t_Handle h_Dtsec, e_FmMacExceptions exception, bool enable) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ uint32_t bitMask = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ -+ if (exception != e_FM_MAC_EX_1G_1588_TS_RX_ERR) -+ { -+ GET_EXCEPTION_FLAG(bitMask, exception); -+ if (bitMask) -+ { -+ if (enable) -+ p_Dtsec->exceptions |= bitMask; -+ else -+ p_Dtsec->exceptions &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); -+ -+ if (enable) -+ fman_dtsec_enable_interrupt(p_Dtsec->p_MemMap, bitMask); -+ else -+ fman_dtsec_disable_interrupt(p_Dtsec->p_MemMap, bitMask); -+ } -+ else -+ { -+ if (!p_Dtsec->ptpTsuEnabled) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exception valid for 1588 only")); -+ -+ if (enable) -+ { -+ p_Dtsec->enTsuErrExeption = TRUE; -+ fman_dtsec_enable_tmr_interrupt(p_Dtsec->p_MemMap); -+ } -+ else -+ { -+ p_Dtsec->enTsuErrExeption = FALSE; -+ fman_dtsec_disable_tmr_interrupt(p_Dtsec->p_MemMap); -+ } -+ } -+ -+ return E_OK; -+} -+ -+ -+/*****************************************************************************/ -+/* dTSEC Init & Free API */ -+/*****************************************************************************/ -+ -+/* .............................................................................. */ -+ -+static t_Error DtsecInit(t_Handle h_Dtsec) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ struct dtsec_cfg *p_DtsecDriverParam; -+ t_Error err; -+ uint16_t maxFrmLn; -+ enum enet_interface enet_interface; -+ enum enet_speed enet_speed; -+ t_EnetAddr ethAddr; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_DtsecDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec->fmMacControllerDriver.h_Fm, E_INVALID_HANDLE); -+ -+ FM_GetRevision(p_Dtsec->fmMacControllerDriver.h_Fm, &p_Dtsec->fmMacControllerDriver.fmRevInfo); -+ CHECK_INIT_PARAMETERS(p_Dtsec, CheckInitParameters); -+ -+ p_DtsecDriverParam = p_Dtsec->p_DtsecDriverParam; -+ p_Dtsec->halfDuplex = p_DtsecDriverParam->halfdup_on; -+ -+ enet_interface = (enum enet_interface)ENET_INTERFACE_FROM_MODE(p_Dtsec->enetMode); -+ enet_speed = (enum enet_speed)ENET_SPEED_FROM_MODE(p_Dtsec->enetMode); -+ MAKE_ENET_ADDR_FROM_UINT64(p_Dtsec->addr, ethAddr); -+ -+ err = (t_Error)fman_dtsec_init(p_Dtsec->p_MemMap, -+ p_DtsecDriverParam, -+ enet_interface, -+ enet_speed, -+ (uint8_t*)ethAddr, -+ p_Dtsec->fmMacControllerDriver.fmRevInfo.majorRev, -+ p_Dtsec->fmMacControllerDriver.fmRevInfo.minorRev, -+ p_Dtsec->exceptions); -+ if (err) -+ { -+ FreeInitResources(p_Dtsec); -+ RETURN_ERROR(MAJOR, err, ("This DTSEC version does not support the required i/f mode")); -+ } -+ -+ if (ENET_INTERFACE_FROM_MODE(p_Dtsec->enetMode) == e_ENET_IF_SGMII) -+ { -+ uint16_t tmpReg16; -+ -+ /* Configure the TBI PHY Control Register */ -+ tmpReg16 = PHY_TBICON_CLK_SEL | PHY_TBICON_SRESET; -+ DTSEC_MII_WritePhyReg(p_Dtsec, (uint8_t)p_DtsecDriverParam->tbipa, 17, tmpReg16); -+ -+ tmpReg16 = PHY_TBICON_CLK_SEL; -+ DTSEC_MII_WritePhyReg(p_Dtsec, (uint8_t)p_DtsecDriverParam->tbipa, 17, tmpReg16); -+ -+ tmpReg16 = (PHY_CR_PHY_RESET | PHY_CR_ANE | PHY_CR_FULLDUPLEX | PHY_CR_SPEED1); -+ DTSEC_MII_WritePhyReg(p_Dtsec, (uint8_t)p_DtsecDriverParam->tbipa, 0, tmpReg16); -+ -+ if (p_Dtsec->enetMode & ENET_IF_SGMII_BASEX) -+ tmpReg16 = PHY_TBIANA_1000X; -+ else -+ tmpReg16 = PHY_TBIANA_SGMII; -+ DTSEC_MII_WritePhyReg(p_Dtsec, (uint8_t)p_DtsecDriverParam->tbipa, 4, tmpReg16); -+ -+ tmpReg16 = (PHY_CR_ANE | PHY_CR_RESET_AN | PHY_CR_FULLDUPLEX | PHY_CR_SPEED1); -+ -+ DTSEC_MII_WritePhyReg(p_Dtsec, (uint8_t)p_DtsecDriverParam->tbipa, 0, tmpReg16); -+ } -+ -+ /* Max Frame Length */ -+ maxFrmLn = fman_dtsec_get_max_frame_len(p_Dtsec->p_MemMap); -+ err = FmSetMacMaxFrame(p_Dtsec->fmMacControllerDriver.h_Fm, e_FM_MAC_1G, -+ p_Dtsec->fmMacControllerDriver.macId, maxFrmLn); -+ if (err) -+ RETURN_ERROR(MINOR,err, NO_MSG); -+ -+ p_Dtsec->p_MulticastAddrHash = AllocHashTable(EXTENDED_HASH_TABLE_SIZE); -+ if (!p_Dtsec->p_MulticastAddrHash) { -+ FreeInitResources(p_Dtsec); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MC hash table is FAILED")); -+ } -+ -+ p_Dtsec->p_UnicastAddrHash = AllocHashTable(HASH_TABLE_SIZE); -+ if (!p_Dtsec->p_UnicastAddrHash) -+ { -+ FreeInitResources(p_Dtsec); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("UC hash table is FAILED")); -+ } -+ -+ /* register err intr handler for dtsec to FPM (err)*/ -+ FmRegisterIntr(p_Dtsec->fmMacControllerDriver.h_Fm, -+ e_FM_MOD_1G_MAC, -+ p_Dtsec->macId, -+ e_FM_INTR_TYPE_ERR, -+ DtsecIsr, -+ p_Dtsec); -+ /* register 1588 intr handler for TMR to FPM (normal)*/ -+ FmRegisterIntr(p_Dtsec->fmMacControllerDriver.h_Fm, -+ e_FM_MOD_1G_MAC, -+ p_Dtsec->macId, -+ e_FM_INTR_TYPE_NORMAL, -+ Dtsec1588Isr, -+ p_Dtsec); -+ /* register normal intr handler for dtsec to main interrupt controller. */ -+ if (p_Dtsec->mdioIrq != NO_IRQ) -+ { -+ XX_SetIntr(p_Dtsec->mdioIrq, DtsecMdioIsr, p_Dtsec); -+ XX_EnableIntr(p_Dtsec->mdioIrq); -+ } -+ -+ XX_Free(p_DtsecDriverParam); -+ p_Dtsec->p_DtsecDriverParam = NULL; -+ -+ err = DtsecSetStatistics(h_Dtsec, e_FM_MAC_FULL_STATISTICS); -+ if (err) -+ { -+ FreeInitResources(p_Dtsec); -+ RETURN_ERROR(MAJOR, err, ("Undefined statistics level")); -+ } -+ -+ return E_OK; -+} -+ -+/* ........................................................................... */ -+ -+static t_Error DtsecFree(t_Handle h_Dtsec) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ -+ if (p_Dtsec->p_DtsecDriverParam) -+ { -+ /* Called after config */ -+ XX_Free(p_Dtsec->p_DtsecDriverParam); -+ p_Dtsec->p_DtsecDriverParam = NULL; -+ } -+ else -+ /* Called after init */ -+ FreeInitResources(p_Dtsec); -+ -+ XX_Free(p_Dtsec); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static void InitFmMacControllerDriver(t_FmMacControllerDriver *p_FmMacControllerDriver) -+{ -+ p_FmMacControllerDriver->f_FM_MAC_Init = DtsecInit; -+ p_FmMacControllerDriver->f_FM_MAC_Free = DtsecFree; -+ -+ p_FmMacControllerDriver->f_FM_MAC_SetStatistics = DtsecSetStatistics; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback = DtsecConfigLoopback; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength = DtsecConfigMaxFrameLength; -+ -+ p_FmMacControllerDriver->f_FM_MAC_ConfigWan = NULL; /* Not supported on dTSEC */ -+ -+ p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc = DtsecConfigPadAndCrc; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex = DtsecConfigHalfDuplex; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck = DtsecConfigLengthCheck; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigTbiPhyAddr = DtsecConfigTbiPhyAddr; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigException = DtsecConfigException; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit = NULL; -+ -+ p_FmMacControllerDriver->f_FM_MAC_Enable = DtsecEnable; -+ p_FmMacControllerDriver->f_FM_MAC_Disable = DtsecDisable; -+ -+ p_FmMacControllerDriver->f_FM_MAC_SetException = DtsecSetException; -+ -+ p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous = DtsecSetPromiscuous; -+ p_FmMacControllerDriver->f_FM_MAC_AdjustLink = DtsecAdjustLink; -+ p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan = DtsecSetWakeOnLan; -+ p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg = DtsecRestartAutoneg; -+ -+ p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp = DtsecEnable1588TimeStamp; -+ p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp = DtsecDisable1588TimeStamp; -+ -+ p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames = DtsecTxMacPause; -+ p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames = DtsecSetTxPauseFrames; -+ p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames = DtsecRxIgnoreMacPause; -+ -+ p_FmMacControllerDriver->f_FM_MAC_ResetCounters = DtsecResetCounters; -+ p_FmMacControllerDriver->f_FM_MAC_GetStatistics = DtsecGetStatistics; -+ -+ p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr = DtsecModifyMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr = DtsecAddHashMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr = DtsecDelHashMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr = DtsecAddExactMatchMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr = DtsecDelExactMatchMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_GetId = DtsecGetId; -+ p_FmMacControllerDriver->f_FM_MAC_GetVersion = DtsecGetVersion; -+ p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength = DtsecGetMaxFrameLength; -+ -+ p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg = DTSEC_MII_WritePhyReg; -+ p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg = DTSEC_MII_ReadPhyReg; -+ -+} -+ -+ -+/*****************************************************************************/ -+/* dTSEC Config Main Entry */ -+/*****************************************************************************/ -+ -+/* .............................................................................. */ -+ -+t_Handle DTSEC_Config(t_FmMacParams *p_FmMacParam) -+{ -+ t_Dtsec *p_Dtsec; -+ struct dtsec_cfg *p_DtsecDriverParam; -+ uintptr_t baseAddr; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmMacParam, E_NULL_POINTER, NULL); -+ -+ baseAddr = p_FmMacParam->baseAddr; -+ -+ /* allocate memory for the UCC GETH data structure. */ -+ p_Dtsec = (t_Dtsec *)XX_Malloc(sizeof(t_Dtsec)); -+ if (!p_Dtsec) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("dTSEC driver structure")); -+ return NULL; -+ } -+ memset(p_Dtsec, 0, sizeof(t_Dtsec)); -+ InitFmMacControllerDriver(&p_Dtsec->fmMacControllerDriver); -+ -+ /* allocate memory for the dTSEC driver parameters data structure. */ -+ p_DtsecDriverParam = (struct dtsec_cfg *) XX_Malloc(sizeof(struct dtsec_cfg)); -+ if (!p_DtsecDriverParam) -+ { -+ XX_Free(p_Dtsec); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("dTSEC driver parameters")); -+ return NULL; -+ } -+ memset(p_DtsecDriverParam, 0, sizeof(struct dtsec_cfg)); -+ -+ /* Plant parameter structure pointer */ -+ p_Dtsec->p_DtsecDriverParam = p_DtsecDriverParam; -+ -+ fman_dtsec_defconfig(p_DtsecDriverParam); -+ -+ p_Dtsec->p_MemMap = (struct dtsec_regs *)UINT_TO_PTR(baseAddr); -+ p_Dtsec->p_MiiMemMap = (struct dtsec_mii_reg *)UINT_TO_PTR(baseAddr + DTSEC_TO_MII_OFFSET); -+ p_Dtsec->addr = ENET_ADDR_TO_UINT64(p_FmMacParam->addr); -+ p_Dtsec->enetMode = p_FmMacParam->enetMode; -+ p_Dtsec->macId = p_FmMacParam->macId; -+ p_Dtsec->exceptions = DEFAULT_exceptions; -+ p_Dtsec->mdioIrq = p_FmMacParam->mdioIrq; -+ p_Dtsec->f_Exception = p_FmMacParam->f_Exception; -+ p_Dtsec->f_Event = p_FmMacParam->f_Event; -+ p_Dtsec->h_App = p_FmMacParam->h_App; -+ p_Dtsec->ptpTsuEnabled = p_Dtsec->p_DtsecDriverParam->ptp_tsu_en; -+ p_Dtsec->enTsuErrExeption = p_Dtsec->p_DtsecDriverParam->ptp_exception_en; -+ p_Dtsec->tbi_phy_addr = p_Dtsec->p_DtsecDriverParam->tbi_phy_addr; -+ -+ return p_Dtsec; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.h -@@ -0,0 +1,228 @@ -+/* -+ * Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/****************************************************************************** -+ @File dtsec.h -+ -+ @Description FM dTSEC ... -+*//***************************************************************************/ -+#ifndef __DTSEC_H -+#define __DTSEC_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "list_ext.h" -+#include "enet_ext.h" -+ -+#include "dtsec_mii_acc.h" -+#include "fm_mac.h" -+ -+ -+#define DEFAULT_exceptions \ -+ ((uint32_t)(DTSEC_IMASK_BREN | \ -+ DTSEC_IMASK_RXCEN | \ -+ DTSEC_IMASK_BTEN | \ -+ DTSEC_IMASK_TXCEN | \ -+ DTSEC_IMASK_TXEEN | \ -+ DTSEC_IMASK_ABRTEN | \ -+ DTSEC_IMASK_LCEN | \ -+ DTSEC_IMASK_CRLEN | \ -+ DTSEC_IMASK_XFUNEN | \ -+ DTSEC_IMASK_IFERREN | \ -+ DTSEC_IMASK_MAGEN | \ -+ DTSEC_IMASK_TDPEEN | \ -+ DTSEC_IMASK_RDPEEN)) -+ -+#define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \ -+ case e_FM_MAC_EX_1G_BAB_RX: \ -+ bitMask = DTSEC_IMASK_BREN; break; \ -+ case e_FM_MAC_EX_1G_RX_CTL: \ -+ bitMask = DTSEC_IMASK_RXCEN; break; \ -+ case e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET: \ -+ bitMask = DTSEC_IMASK_GTSCEN ; break; \ -+ case e_FM_MAC_EX_1G_BAB_TX: \ -+ bitMask = DTSEC_IMASK_BTEN ; break; \ -+ case e_FM_MAC_EX_1G_TX_CTL: \ -+ bitMask = DTSEC_IMASK_TXCEN ; break; \ -+ case e_FM_MAC_EX_1G_TX_ERR: \ -+ bitMask = DTSEC_IMASK_TXEEN ; break; \ -+ case e_FM_MAC_EX_1G_LATE_COL: \ -+ bitMask = DTSEC_IMASK_LCEN ; break; \ -+ case e_FM_MAC_EX_1G_COL_RET_LMT: \ -+ bitMask = DTSEC_IMASK_CRLEN ; break; \ -+ case e_FM_MAC_EX_1G_TX_FIFO_UNDRN: \ -+ bitMask = DTSEC_IMASK_XFUNEN ; break; \ -+ case e_FM_MAC_EX_1G_MAG_PCKT: \ -+ bitMask = DTSEC_IMASK_MAGEN ; break; \ -+ case e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET: \ -+ bitMask = DTSEC_IMASK_MMRDEN; break; \ -+ case e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET: \ -+ bitMask = DTSEC_IMASK_MMWREN ; break; \ -+ case e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET: \ -+ bitMask = DTSEC_IMASK_GRSCEN; break; \ -+ case e_FM_MAC_EX_1G_TX_DATA_ERR: \ -+ bitMask = DTSEC_IMASK_TDPEEN; break; \ -+ case e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL: \ -+ bitMask = DTSEC_IMASK_MSROEN ; break; \ -+ default: bitMask = 0;break;} -+ -+ -+#define MAX_PACKET_ALIGNMENT 31 -+#define MAX_INTER_PACKET_GAP 0x7f -+#define MAX_INTER_PALTERNATE_BEB 0x0f -+#define MAX_RETRANSMISSION 0x0f -+#define MAX_COLLISION_WINDOW 0x03ff -+ -+ -+/********************* From mac ext ******************************************/ -+typedef uint32_t t_ErrorDisable; -+ -+#define ERROR_DISABLE_TRANSMIT 0x00400000 -+#define ERROR_DISABLE_LATE_COLLISION 0x00040000 -+#define ERROR_DISABLE_COLLISION_RETRY_LIMIT 0x00020000 -+#define ERROR_DISABLE_TxFIFO_UNDERRUN 0x00010000 -+#define ERROR_DISABLE_TxABORT 0x00008000 -+#define ERROR_DISABLE_INTERFACE 0x00004000 -+#define ERROR_DISABLE_TxDATA_PARITY 0x00000002 -+#define ERROR_DISABLE_RxDATA_PARITY 0x00000001 -+ -+/*****************************************************************************/ -+#define DTSEC_NUM_OF_PADDRS 15 /* number of pattern match registers (entries) */ -+ -+#define GROUP_ADDRESS 0x0000010000000000LL /* Group address bit indication */ -+ -+#define HASH_TABLE_SIZE 256 /* Hash table size (= 32 bits * 8 regs) */ -+ -+#define HASH_TABLE_SIZE 256 /* Hash table size (32 bits * 8 regs) */ -+#define EXTENDED_HASH_TABLE_SIZE 512 /* Extended Hash table size (32 bits * 16 regs) */ -+ -+#define DTSEC_TO_MII_OFFSET 0x1000 /* number of pattern match registers (entries) */ -+ -+#define MAX_PHYS 32 /* maximum number of phys */ -+ -+#define VAL32BIT 0x100000000LL -+#define VAL22BIT 0x00400000 -+#define VAL16BIT 0x00010000 -+#define VAL12BIT 0x00001000 -+ -+/* CAR1/2 bits */ -+#define CAR1_TR64 0x80000000 -+#define CAR1_TR127 0x40000000 -+#define CAR1_TR255 0x20000000 -+#define CAR1_TR511 0x10000000 -+#define CAR1_TRK1 0x08000000 -+#define CAR1_TRMAX 0x04000000 -+#define CAR1_TRMGV 0x02000000 -+ -+#define CAR1_RBYT 0x00010000 -+#define CAR1_RPKT 0x00008000 -+#define CAR1_RMCA 0x00002000 -+#define CAR1_RBCA 0x00001000 -+#define CAR1_RXPF 0x00000400 -+#define CAR1_RALN 0x00000100 -+#define CAR1_RFLR 0x00000080 -+#define CAR1_RCDE 0x00000040 -+#define CAR1_RCSE 0x00000020 -+#define CAR1_RUND 0x00000010 -+#define CAR1_ROVR 0x00000008 -+#define CAR1_RFRG 0x00000004 -+#define CAR1_RJBR 0x00000002 -+#define CAR1_RDRP 0x00000001 -+ -+#define CAR2_TFCS 0x00040000 -+#define CAR2_TBYT 0x00002000 -+#define CAR2_TPKT 0x00001000 -+#define CAR2_TMCA 0x00000800 -+#define CAR2_TBCA 0x00000400 -+#define CAR2_TXPF 0x00000200 -+#define CAR2_TDRP 0x00000001 -+ -+typedef struct t_InternalStatistics -+{ -+ uint64_t tr64; -+ uint64_t tr127; -+ uint64_t tr255; -+ uint64_t tr511; -+ uint64_t tr1k; -+ uint64_t trmax; -+ uint64_t trmgv; -+ uint64_t rfrg; -+ uint64_t rjbr; -+ uint64_t rdrp; -+ uint64_t raln; -+ uint64_t rund; -+ uint64_t rovr; -+ uint64_t rxpf; -+ uint64_t txpf; -+ uint64_t rbyt; -+ uint64_t rpkt; -+ uint64_t rmca; -+ uint64_t rbca; -+ uint64_t rflr; -+ uint64_t rcde; -+ uint64_t rcse; -+ uint64_t tbyt; -+ uint64_t tpkt; -+ uint64_t tmca; -+ uint64_t tbca; -+ uint64_t tdrp; -+ uint64_t tfcs; -+} t_InternalStatistics; -+ -+typedef struct { -+ t_FmMacControllerDriver fmMacControllerDriver; -+ t_Handle h_App; /**< Handle to the upper layer application */ -+ struct dtsec_regs *p_MemMap; /**< pointer to dTSEC memory mapped registers. */ -+ struct dtsec_mii_reg *p_MiiMemMap; /**< pointer to dTSEC MII memory mapped registers. */ -+ uint64_t addr; /**< MAC address of device; */ -+ e_EnetMode enetMode; /**< Ethernet physical interface */ -+ t_FmMacExceptionCallback *f_Exception; -+ int mdioIrq; -+ t_FmMacExceptionCallback *f_Event; -+ bool indAddrRegUsed[DTSEC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */ -+ uint64_t paddr[DTSEC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */ -+ uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */ -+ bool halfDuplex; -+ t_InternalStatistics internalStatistics; -+ t_EthHash *p_MulticastAddrHash; /* pointer to driver's global address hash table */ -+ t_EthHash *p_UnicastAddrHash; /* pointer to driver's individual address hash table */ -+ uint8_t macId; -+ uint8_t tbi_phy_addr; -+ uint32_t exceptions; -+ bool ptpTsuEnabled; -+ bool enTsuErrExeption; -+ e_FmMacStatisticsLevel statisticsLevel; -+ struct dtsec_cfg *p_DtsecDriverParam; -+} t_Dtsec; -+ -+ -+#endif /* __DTSEC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.c -@@ -0,0 +1,97 @@ -+/* -+ * Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File dtsec_mii_acc.c -+ -+ @Description FM dtsec MII register access MAC ... -+*//***************************************************************************/ -+ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "fm_mac.h" -+#include "dtsec.h" -+#include "fsl_fman_dtsec_mii_acc.h" -+ -+ -+/*****************************************************************************/ -+t_Error DTSEC_MII_WritePhyReg(t_Handle h_Dtsec, -+ uint8_t phyAddr, -+ uint8_t reg, -+ uint16_t data) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ struct dtsec_mii_reg *miiregs; -+ uint16_t dtsec_freq; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE); -+ -+ dtsec_freq = (uint16_t)(p_Dtsec->fmMacControllerDriver.clkFreq >> 1); -+ miiregs = p_Dtsec->p_MiiMemMap; -+ -+ err = (t_Error)fman_dtsec_mii_write_reg(miiregs, phyAddr, reg, data, dtsec_freq); -+ -+ return err; -+} -+ -+/*****************************************************************************/ -+t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec, -+ uint8_t phyAddr, -+ uint8_t reg, -+ uint16_t *p_Data) -+{ -+ t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec; -+ struct dtsec_mii_reg *miiregs; -+ uint16_t dtsec_freq; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE); -+ -+ dtsec_freq = (uint16_t)(p_Dtsec->fmMacControllerDriver.clkFreq >> 1); -+ miiregs = p_Dtsec->p_MiiMemMap; -+ -+ err = fman_dtsec_mii_read_reg(miiregs, phyAddr, reg, p_Data, dtsec_freq); -+ -+ if (*p_Data == 0xffff) -+ RETURN_ERROR(MINOR, E_NO_DEVICE, -+ ("Read wrong data (0xffff): phyAddr 0x%x, reg 0x%x", -+ phyAddr, reg)); -+ if (err) -+ RETURN_ERROR(MINOR, (t_Error)err, NO_MSG); -+ -+ return E_OK; -+} -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.h -@@ -0,0 +1,42 @@ -+/* -+ * Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __DTSEC_MII_ACC_H -+#define __DTSEC_MII_ACC_H -+ -+#include "std_ext.h" -+ -+ -+t_Error DTSEC_MII_WritePhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t data); -+t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data); -+ -+#endif /* __DTSEC_MII_ACC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c -@@ -0,0 +1,646 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_mac.c -+ -+ @Description FM MAC ... -+*//***************************************************************************/ -+#include "std_ext.h" -+#include "string_ext.h" -+#include "sprint_ext.h" -+#include "error_ext.h" -+#include "fm_ext.h" -+ -+#include "fm_common.h" -+#include "fm_mac.h" -+ -+ -+/* ......................................................................... */ -+ -+t_Handle FM_MAC_Config (t_FmMacParams *p_FmMacParam) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver; -+ uint16_t fmClkFreq; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmMacParam, E_INVALID_HANDLE, NULL); -+ -+ fmClkFreq = FmGetClockFreq(p_FmMacParam->h_Fm); -+ if (fmClkFreq == 0) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Can't get clock for MAC!")); -+ return NULL; -+ } -+ -+#if (DPAA_VERSION == 10) -+ if (ENET_SPEED_FROM_MODE(p_FmMacParam->enetMode) < e_ENET_SPEED_10000) -+ p_FmMacControllerDriver = (t_FmMacControllerDriver *)DTSEC_Config(p_FmMacParam); -+ else -+#if FM_MAX_NUM_OF_10G_MACS > 0 -+ p_FmMacControllerDriver = (t_FmMacControllerDriver *)TGEC_Config(p_FmMacParam); -+#else -+ p_FmMacControllerDriver = NULL; -+#endif /* FM_MAX_NUM_OF_10G_MACS > 0 */ -+#else -+ p_FmMacControllerDriver = (t_FmMacControllerDriver *)MEMAC_Config(p_FmMacParam); -+#endif /* (DPAA_VERSION == 10) */ -+ -+ if (!p_FmMacControllerDriver) -+ return NULL; -+ -+ p_FmMacControllerDriver->h_Fm = p_FmMacParam->h_Fm; -+ p_FmMacControllerDriver->enetMode = p_FmMacParam->enetMode; -+ p_FmMacControllerDriver->macId = p_FmMacParam->macId; -+ p_FmMacControllerDriver->resetOnInit = DEFAULT_resetOnInit; -+ -+ p_FmMacControllerDriver->clkFreq = fmClkFreq; -+ -+ return (t_Handle)p_FmMacControllerDriver; -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_Init (t_Handle h_FmMac) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->resetOnInit && -+ !p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit && -+ (FmResetMac(p_FmMacControllerDriver->h_Fm, -+ ((ENET_INTERFACE_FROM_MODE(p_FmMacControllerDriver->enetMode) == e_ENET_IF_XGMII) ? -+ e_FM_MAC_10G : e_FM_MAC_1G), -+ p_FmMacControllerDriver->macId) != E_OK)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Can't reset MAC!")); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_Init) -+ return p_FmMacControllerDriver->f_FM_MAC_Init(h_FmMac); -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_Free (t_Handle h_FmMac) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_Free) -+ return p_FmMacControllerDriver->f_FM_MAC_Free(h_FmMac); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_ConfigResetOnInit (t_Handle h_FmMac, bool enable) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit) -+ return p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit(h_FmMac, enable); -+ -+ p_FmMacControllerDriver->resetOnInit = enable; -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_ConfigLoopback (t_Handle h_FmMac, bool newVal) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback) -+ return p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback(h_FmMac, newVal); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_ConfigMaxFrameLength (t_Handle h_FmMac, uint16_t newVal) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength) -+ return p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength(h_FmMac, newVal); -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_ConfigWan (t_Handle h_FmMac, bool flag) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_ConfigWan) -+ return p_FmMacControllerDriver->f_FM_MAC_ConfigWan(h_FmMac, flag); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_ConfigPadAndCrc (t_Handle h_FmMac, bool newVal) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc) -+ return p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc(h_FmMac, newVal); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_ConfigHalfDuplex (t_Handle h_FmMac, bool newVal) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex) -+ return p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex(h_FmMac,newVal); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_ConfigTbiPhyAddr (t_Handle h_FmMac, uint8_t newVal) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_ConfigTbiPhyAddr) -+ return p_FmMacControllerDriver->f_FM_MAC_ConfigTbiPhyAddr(h_FmMac,newVal); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_ConfigLengthCheck (t_Handle h_FmMac, bool newVal) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck) -+ return p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck(h_FmMac,newVal); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_ConfigException (t_Handle h_FmMac, e_FmMacExceptions ex, bool enable) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_ConfigException) -+ return p_FmMacControllerDriver->f_FM_MAC_ConfigException(h_FmMac, ex, enable); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -+/* ......................................................................... */ -+ -+t_Error FM_MAC_ConfigSkipFman11Workaround (t_Handle h_FmMac) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_ConfigSkipFman11Workaround) -+ return p_FmMacControllerDriver->f_FM_MAC_ConfigSkipFman11Workaround(h_FmMac); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ -+ -+ -+/*****************************************************************************/ -+/* Run Time Control */ -+/*****************************************************************************/ -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_Enable (t_Handle h_FmMac, e_CommMode mode) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_Enable) -+ return p_FmMacControllerDriver->f_FM_MAC_Enable(h_FmMac, mode); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_Disable (t_Handle h_FmMac, e_CommMode mode) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_Disable) -+ return p_FmMacControllerDriver->f_FM_MAC_Disable(h_FmMac, mode); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_Enable1588TimeStamp (t_Handle h_FmMac) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp) -+ return p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp(h_FmMac); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_Disable1588TimeStamp (t_Handle h_FmMac) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp) -+ return p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp(h_FmMac); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_SetTxAutoPauseFrames(t_Handle h_FmMac, -+ uint16_t pauseTime) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames) -+ return p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames(h_FmMac, -+ pauseTime); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_SetTxPauseFrames(t_Handle h_FmMac, -+ uint8_t priority, -+ uint16_t pauseTime, -+ uint16_t threshTime) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames) -+ return p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames(h_FmMac, -+ priority, -+ pauseTime, -+ threshTime); -+ -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_SetRxIgnorePauseFrames (t_Handle h_FmMac, bool en) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames) -+ return p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames(h_FmMac, en); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_SetWakeOnLan (t_Handle h_FmMac, bool en) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan) -+ return p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan(h_FmMac, en); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_ResetCounters (t_Handle h_FmMac) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_ResetCounters) -+ return p_FmMacControllerDriver->f_FM_MAC_ResetCounters(h_FmMac); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_SetException(t_Handle h_FmMac, e_FmMacExceptions ex, bool enable) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_SetException) -+ return p_FmMacControllerDriver->f_FM_MAC_SetException(h_FmMac, ex, enable); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_SetStatistics (t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_SetStatistics) -+ return p_FmMacControllerDriver->f_FM_MAC_SetStatistics(h_FmMac, statisticsLevel); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_GetStatistics (t_Handle h_FmMac, t_FmMacStatistics *p_Statistics) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_GetStatistics) -+ return p_FmMacControllerDriver->f_FM_MAC_GetStatistics(h_FmMac, p_Statistics); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_ModifyMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr) -+ return p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr(h_FmMac, p_EnetAddr); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_AddHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr) -+ return p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr(h_FmMac, p_EnetAddr); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_RemoveHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr) -+ return p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr(h_FmMac, p_EnetAddr); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_AddExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr) -+ return p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr(h_FmMac, p_EnetAddr); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_RemovelExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr) -+ return p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr(h_FmMac, p_EnetAddr); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_GetVesrion (t_Handle h_FmMac, uint32_t *macVresion) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_GetVersion) -+ return p_FmMacControllerDriver->f_FM_MAC_GetVersion(h_FmMac, macVresion); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+ -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_GetId (t_Handle h_FmMac, uint32_t *macId) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_GetId) -+ return p_FmMacControllerDriver->f_FM_MAC_GetId(h_FmMac, macId); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_SetPromiscuous (t_Handle h_FmMac, bool newVal) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous) -+ return p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous(h_FmMac, newVal); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_AdjustLink(t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_AdjustLink) -+ return p_FmMacControllerDriver->f_FM_MAC_AdjustLink(h_FmMac, speed, fullDuplex); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_RestartAutoneg(t_Handle h_FmMac) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg) -+ return p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg(h_FmMac); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_MII_WritePhyReg (t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg) -+ return p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg(h_FmMac, phyAddr, reg, data); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+t_Error FM_MAC_MII_ReadPhyReg(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg) -+ return p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg(h_FmMac, phyAddr, reg, p_Data); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+uint16_t FM_MAC_GetMaxFrameLength(t_Handle h_FmMac) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmMacControllerDriver, E_INVALID_HANDLE, 0); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength) -+ return p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength(h_FmMac); -+ -+ REPORT_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+ return 0; -+} -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+/*****************************************************************************/ -+t_Error FM_MAC_DumpRegs(t_Handle h_FmMac) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_DumpRegs) -+ return p_FmMacControllerDriver->f_FM_MAC_DumpRegs(h_FmMac); -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+#endif /* (defined(DEBUG_ERRORS) && ... */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h -@@ -0,0 +1,224 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_mac.h -+ -+ @Description FM MAC ... -+*//***************************************************************************/ -+#ifndef __FM_MAC_H -+#define __FM_MAC_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "list_ext.h" -+#include "fm_mac_ext.h" -+#include "fm_common.h" -+ -+ -+#define __ERR_MODULE__ MODULE_FM_MAC -+ -+/**************************************************************************//** -+ @Description defaults -+*//***************************************************************************/ -+ -+ -+#define DEFAULT_halfDuplex FALSE -+#define DEFAULT_padAndCrcEnable TRUE -+#define DEFAULT_resetOnInit FALSE -+ -+ -+typedef struct { -+ uint64_t addr; /* Ethernet Address */ -+ t_List node; -+} t_EthHashEntry; -+#define ETH_HASH_ENTRY_OBJ(ptr) LIST_OBJECT(ptr, t_EthHashEntry, node) -+ -+typedef struct { -+ uint16_t size; -+ t_List *p_Lsts; -+} t_EthHash; -+ -+typedef struct { -+ t_Error (*f_FM_MAC_Init) (t_Handle h_FmMac); -+ t_Error (*f_FM_MAC_Free) (t_Handle h_FmMac); -+ -+ t_Error (*f_FM_MAC_SetStatistics) (t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel); -+ t_Error (*f_FM_MAC_ConfigLoopback) (t_Handle h_FmMac, bool newVal); -+ t_Error (*f_FM_MAC_ConfigMaxFrameLength) (t_Handle h_FmMac, uint16_t newVal); -+ t_Error (*f_FM_MAC_ConfigWan) (t_Handle h_FmMac, bool flag); -+ t_Error (*f_FM_MAC_ConfigPadAndCrc) (t_Handle h_FmMac, bool newVal); -+ t_Error (*f_FM_MAC_ConfigHalfDuplex) (t_Handle h_FmMac, bool newVal); -+ t_Error (*f_FM_MAC_ConfigLengthCheck) (t_Handle h_FmMac, bool newVal); -+ t_Error (*f_FM_MAC_ConfigTbiPhyAddr) (t_Handle h_FmMac, uint8_t newVal); -+ t_Error (*f_FM_MAC_ConfigException) (t_Handle h_FmMac, e_FmMacExceptions, bool enable); -+ t_Error (*f_FM_MAC_ConfigResetOnInit) (t_Handle h_FmMac, bool enable); -+#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -+ t_Error (*f_FM_MAC_ConfigSkipFman11Workaround) (t_Handle h_FmMac); -+#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ -+ -+ t_Error (*f_FM_MAC_SetException) (t_Handle h_FmMac, e_FmMacExceptions ex, bool enable); -+ -+ t_Error (*f_FM_MAC_Enable) (t_Handle h_FmMac, e_CommMode mode); -+ t_Error (*f_FM_MAC_Disable) (t_Handle h_FmMac, e_CommMode mode); -+ t_Error (*f_FM_MAC_Enable1588TimeStamp) (t_Handle h_FmMac); -+ t_Error (*f_FM_MAC_Disable1588TimeStamp) (t_Handle h_FmMac); -+ t_Error (*f_FM_MAC_Reset) (t_Handle h_FmMac, bool wait); -+ -+ t_Error (*f_FM_MAC_SetTxAutoPauseFrames) (t_Handle h_FmMac, -+ uint16_t pauseTime); -+ t_Error (*f_FM_MAC_SetTxPauseFrames) (t_Handle h_FmMac, -+ uint8_t priority, -+ uint16_t pauseTime, -+ uint16_t threshTime); -+ t_Error (*f_FM_MAC_SetRxIgnorePauseFrames) (t_Handle h_FmMac, bool en); -+ -+ t_Error (*f_FM_MAC_ResetCounters) (t_Handle h_FmMac); -+ t_Error (*f_FM_MAC_GetStatistics) (t_Handle h_FmMac, t_FmMacStatistics *p_Statistics); -+ -+ t_Error (*f_FM_MAC_ModifyMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr); -+ t_Error (*f_FM_MAC_AddHashMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr); -+ t_Error (*f_FM_MAC_RemoveHashMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr); -+ t_Error (*f_FM_MAC_AddExactMatchMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr); -+ t_Error (*f_FM_MAC_RemovelExactMatchMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr); -+ -+ t_Error (*f_FM_MAC_SetPromiscuous) (t_Handle h_FmMac, bool newVal); -+ t_Error (*f_FM_MAC_AdjustLink) (t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex); -+ t_Error (*f_FM_MAC_RestartAutoneg) (t_Handle h_FmMac); -+ -+ t_Error (*f_FM_MAC_SetWakeOnLan) (t_Handle h_FmMac, bool en); -+ -+ t_Error (*f_FM_MAC_GetId) (t_Handle h_FmMac, uint32_t *macId); -+ -+ t_Error (*f_FM_MAC_GetVersion) (t_Handle h_FmMac, uint32_t *macVersion); -+ -+ uint16_t (*f_FM_MAC_GetMaxFrameLength) (t_Handle h_FmMac); -+ -+ t_Error (*f_FM_MAC_MII_WritePhyReg)(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data); -+ t_Error (*f_FM_MAC_MII_ReadPhyReg)(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data); -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_Error (*f_FM_MAC_DumpRegs) (t_Handle h_FmMac); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+ t_Handle h_Fm; -+ t_FmRevisionInfo fmRevInfo; -+ e_EnetMode enetMode; -+ uint8_t macId; -+ bool resetOnInit; -+ uint16_t clkFreq; -+} t_FmMacControllerDriver; -+ -+ -+#if (DPAA_VERSION == 10) -+t_Handle DTSEC_Config(t_FmMacParams *p_FmMacParam); -+t_Handle TGEC_Config(t_FmMacParams *p_FmMacParams); -+#else -+t_Handle MEMAC_Config(t_FmMacParams *p_FmMacParam); -+#endif /* (DPAA_VERSION == 10) */ -+uint16_t FM_MAC_GetMaxFrameLength(t_Handle FmMac); -+ -+ -+/* ........................................................................... */ -+ -+static __inline__ t_EthHashEntry *DequeueAddrFromHashEntry(t_List *p_AddrLst) -+{ -+ t_EthHashEntry *p_HashEntry = NULL; -+ if (!LIST_IsEmpty(p_AddrLst)) -+ { -+ p_HashEntry = ETH_HASH_ENTRY_OBJ(p_AddrLst->p_Next); -+ LIST_DelAndInit(&p_HashEntry->node); -+ } -+ return p_HashEntry; -+} -+ -+/* ........................................................................... */ -+ -+static __inline__ void FreeHashTable(t_EthHash *p_Hash) -+{ -+ t_EthHashEntry *p_HashEntry; -+ int i = 0; -+ -+ if (p_Hash) -+ { -+ if (p_Hash->p_Lsts) -+ { -+ for (i=0; isize; i++) -+ { -+ p_HashEntry = DequeueAddrFromHashEntry(&p_Hash->p_Lsts[i]); -+ while (p_HashEntry) -+ { -+ XX_Free(p_HashEntry); -+ p_HashEntry = DequeueAddrFromHashEntry(&p_Hash->p_Lsts[i]); -+ } -+ } -+ -+ XX_Free(p_Hash->p_Lsts); -+ } -+ -+ XX_Free(p_Hash); -+ } -+} -+ -+/* ........................................................................... */ -+ -+static __inline__ t_EthHash * AllocHashTable(uint16_t size) -+{ -+ uint32_t i; -+ t_EthHash *p_Hash; -+ -+ /* Allocate address hash table */ -+ p_Hash = (t_EthHash *)XX_Malloc(sizeof(t_EthHash)); -+ if (!p_Hash) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Address hash table")); -+ return NULL; -+ } -+ p_Hash->size = size; -+ -+ p_Hash->p_Lsts = (t_List *)XX_Malloc(p_Hash->size*sizeof(t_List)); -+ if (!p_Hash->p_Lsts) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Address hash table")); -+ XX_Free(p_Hash); -+ return NULL; -+ } -+ -+ for (i=0 ; isize; i++) -+ INIT_LIST(&p_Hash->p_Lsts[i]); -+ -+ return p_Hash; -+} -+ -+ -+#endif /* __FM_MAC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.c -@@ -0,0 +1,119 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include "fman_crc32.h" -+#include "common/general.h" -+ -+ -+/* precomputed CRC values for address hashing */ -+static const uint32_t crc_tbl[256] = { -+ 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, -+ 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, -+ 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, -+ 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, -+ 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, -+ 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, -+ 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, -+ 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, -+ 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, -+ 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, -+ 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, -+ 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, -+ 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, -+ 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, -+ 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, -+ 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, -+ 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, -+ 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, -+ 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, -+ 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, -+ 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, -+ 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, -+ 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, -+ 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, -+ 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, -+ 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, -+ 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, -+ 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, -+ 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, -+ 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, -+ 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, -+ 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, -+ 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, -+ 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, -+ 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, -+ 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, -+ 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, -+ 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, -+ 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, -+ 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, -+ 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, -+ 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, -+ 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d -+}; -+ -+/* Get the mirrored value of a byte size number. (0x11010011 --> 0x11001011) */ -+static inline uint8_t get_mirror8(uint8_t n) -+{ -+ uint8_t mirror[16] = { -+ 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, -+ 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f -+ }; -+ return (uint8_t)(((mirror[n & 0x0f] << 4) | (mirror[n >> 4]))); -+} -+ -+static inline uint32_t get_mirror32(uint32_t n) -+{ -+ return ((uint32_t)get_mirror8((uint8_t)(n))<<24) | -+ ((uint32_t)get_mirror8((uint8_t)(n>>8))<<16) | -+ ((uint32_t)get_mirror8((uint8_t)(n>>16))<<8) | -+ ((uint32_t)get_mirror8((uint8_t)(n>>24))); -+} -+ -+uint32_t get_mac_addr_crc(uint64_t _addr) -+{ -+ uint32_t i; -+ uint8_t data; -+ uint32_t crc; -+ -+ /* CRC calculation */ -+ crc = 0xffffffff; -+ for (i = 0; i < 6; i++) { -+ data = (uint8_t)(_addr >> ((5-i)*8)); -+ crc = crc ^ data; -+ crc = crc_tbl[crc&0xff] ^ (crc>>8); -+ } -+ -+ crc = get_mirror32(crc); -+ return crc; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.h -@@ -0,0 +1,43 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#ifndef __FMAN_CRC32_H -+#define __FMAN_CRC32_H -+ -+#include "common/general.h" -+ -+ -+uint32_t get_mac_addr_crc(uint64_t _addr); -+ -+ -+#endif /* __FMAN_CRC32_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec.c -@@ -0,0 +1,845 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include "fsl_fman_dtsec.h" -+ -+ -+void fman_dtsec_stop_rx(struct dtsec_regs *regs) -+{ -+ /* Assert the graceful stop bit */ -+ iowrite32be(ioread32be(®s->rctrl) | RCTRL_GRS, ®s->rctrl); -+} -+ -+void fman_dtsec_stop_tx(struct dtsec_regs *regs) -+{ -+ /* Assert the graceful stop bit */ -+ iowrite32be(ioread32be(®s->tctrl) | DTSEC_TCTRL_GTS, ®s->tctrl); -+} -+ -+void fman_dtsec_start_tx(struct dtsec_regs *regs) -+{ -+ /* clear the graceful stop bit */ -+ iowrite32be(ioread32be(®s->tctrl) & ~DTSEC_TCTRL_GTS, ®s->tctrl); -+} -+ -+void fman_dtsec_start_rx(struct dtsec_regs *regs) -+{ -+ /* clear the graceful stop bit */ -+ iowrite32be(ioread32be(®s->rctrl) & ~RCTRL_GRS, ®s->rctrl); -+} -+ -+void fman_dtsec_defconfig(struct dtsec_cfg *cfg) -+{ -+ cfg->halfdup_on = DEFAULT_HALFDUP_ON; -+ cfg->halfdup_retransmit = DEFAULT_HALFDUP_RETRANSMIT; -+ cfg->halfdup_coll_window = DEFAULT_HALFDUP_COLL_WINDOW; -+ cfg->halfdup_excess_defer = DEFAULT_HALFDUP_EXCESS_DEFER; -+ cfg->halfdup_no_backoff = DEFAULT_HALFDUP_NO_BACKOFF; -+ cfg->halfdup_bp_no_backoff = DEFAULT_HALFDUP_BP_NO_BACKOFF; -+ cfg->halfdup_alt_backoff_val = DEFAULT_HALFDUP_ALT_BACKOFF_VAL; -+ cfg->halfdup_alt_backoff_en = DEFAULT_HALFDUP_ALT_BACKOFF_EN; -+ cfg->rx_drop_bcast = DEFAULT_RX_DROP_BCAST; -+ cfg->rx_short_frm = DEFAULT_RX_SHORT_FRM; -+ cfg->rx_len_check = DEFAULT_RX_LEN_CHECK; -+ cfg->tx_pad_crc = DEFAULT_TX_PAD_CRC; -+ cfg->tx_crc = DEFAULT_TX_CRC; -+ cfg->rx_ctrl_acc = DEFAULT_RX_CTRL_ACC; -+ cfg->tx_pause_time = DEFAULT_TX_PAUSE_TIME; -+ cfg->tbipa = DEFAULT_TBIPA; /* PHY address 0 is reserved (DPAA RM)*/ -+ cfg->rx_prepend = DEFAULT_RX_PREPEND; -+ cfg->ptp_tsu_en = DEFAULT_PTP_TSU_EN; -+ cfg->ptp_exception_en = DEFAULT_PTP_EXCEPTION_EN; -+ cfg->preamble_len = DEFAULT_PREAMBLE_LEN; -+ cfg->rx_preamble = DEFAULT_RX_PREAMBLE; -+ cfg->tx_preamble = DEFAULT_TX_PREAMBLE; -+ cfg->loopback = DEFAULT_LOOPBACK; -+ cfg->rx_time_stamp_en = DEFAULT_RX_TIME_STAMP_EN; -+ cfg->tx_time_stamp_en = DEFAULT_TX_TIME_STAMP_EN; -+ cfg->rx_flow = DEFAULT_RX_FLOW; -+ cfg->tx_flow = DEFAULT_TX_FLOW; -+ cfg->rx_group_hash_exd = DEFAULT_RX_GROUP_HASH_EXD; -+ cfg->tx_pause_time_extd = DEFAULT_TX_PAUSE_TIME_EXTD; -+ cfg->rx_promisc = DEFAULT_RX_PROMISC; -+ cfg->non_back_to_back_ipg1 = DEFAULT_NON_BACK_TO_BACK_IPG1; -+ cfg->non_back_to_back_ipg2 = DEFAULT_NON_BACK_TO_BACK_IPG2; -+ cfg->min_ifg_enforcement = DEFAULT_MIN_IFG_ENFORCEMENT; -+ cfg->back_to_back_ipg = DEFAULT_BACK_TO_BACK_IPG; -+ cfg->maximum_frame = DEFAULT_MAXIMUM_FRAME; -+ cfg->tbi_phy_addr = DEFAULT_TBI_PHY_ADDR; -+ cfg->wake_on_lan = DEFAULT_WAKE_ON_LAN; -+} -+ -+int fman_dtsec_init(struct dtsec_regs *regs, struct dtsec_cfg *cfg, -+ enum enet_interface iface_mode, -+ enum enet_speed iface_speed, -+ uint8_t *macaddr, -+ uint8_t fm_rev_maj, -+ uint8_t fm_rev_min, -+ uint32_t exception_mask) -+{ -+ bool is_rgmii = FALSE; -+ bool is_sgmii = FALSE; -+ bool is_qsgmii = FALSE; -+ int i; -+ uint32_t tmp; -+ -+UNUSED(fm_rev_maj);UNUSED(fm_rev_min); -+ -+ /* let's start with a soft reset */ -+ iowrite32be(MACCFG1_SOFT_RESET, ®s->maccfg1); -+ iowrite32be(0, ®s->maccfg1); -+ -+ /*************dtsec_id2******************/ -+ tmp = ioread32be(®s->tsec_id2); -+ -+ /* check RGMII support */ -+ if (iface_mode == E_ENET_IF_RGMII || -+ iface_mode == E_ENET_IF_RMII) -+ if (tmp & DTSEC_ID2_INT_REDUCED_OFF) -+ return -EINVAL; -+ -+ if (iface_mode == E_ENET_IF_SGMII || -+ iface_mode == E_ENET_IF_MII) -+ if (tmp & DTSEC_ID2_INT_REDUCED_OFF) -+ return -EINVAL; -+ -+ /***************ECNTRL************************/ -+ -+ is_rgmii = (bool)((iface_mode == E_ENET_IF_RGMII) ? TRUE : FALSE); -+ is_sgmii = (bool)((iface_mode == E_ENET_IF_SGMII) ? TRUE : FALSE); -+ is_qsgmii = (bool)((iface_mode == E_ENET_IF_QSGMII) ? TRUE : FALSE); -+ -+ tmp = 0; -+ if (is_rgmii || iface_mode == E_ENET_IF_GMII) -+ tmp |= DTSEC_ECNTRL_GMIIM; -+ if (is_sgmii) -+ tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM); -+ if (is_qsgmii) -+ tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM | -+ DTSEC_ECNTRL_QSGMIIM); -+ if (is_rgmii) -+ tmp |= DTSEC_ECNTRL_RPM; -+ if (iface_speed == E_ENET_SPEED_100) -+ tmp |= DTSEC_ECNTRL_R100M; -+ -+ iowrite32be(tmp, ®s->ecntrl); -+ /***************ECNTRL************************/ -+ -+ /***************TCTRL************************/ -+ tmp = 0; -+ if (cfg->halfdup_on) -+ tmp |= DTSEC_TCTRL_THDF; -+ if (cfg->tx_time_stamp_en) -+ tmp |= DTSEC_TCTRL_TTSE; -+ -+ iowrite32be(tmp, ®s->tctrl); -+ -+ /***************TCTRL************************/ -+ -+ /***************PTV************************/ -+ tmp = 0; -+ -+#ifdef FM_SHORT_PAUSE_TIME_ERRATA_DTSEC1 -+ if ((fm_rev_maj == 1) && (fm_rev_min == 0)) -+ cfg->tx_pause_time += 2; -+#endif /* FM_SHORT_PAUSE_TIME_ERRATA_DTSEC1 */ -+ -+ if (cfg->tx_pause_time) -+ tmp |= cfg->tx_pause_time; -+ if (cfg->tx_pause_time_extd) -+ tmp |= cfg->tx_pause_time_extd << PTV_PTE_OFST; -+ iowrite32be(tmp, ®s->ptv); -+ -+ /***************RCTRL************************/ -+ tmp = 0; -+ tmp |= ((uint32_t)(cfg->rx_prepend & 0x0000001f)) << 16; -+ if (cfg->rx_ctrl_acc) -+ tmp |= RCTRL_CFA; -+ if (cfg->rx_group_hash_exd) -+ tmp |= RCTRL_GHTX; -+ if (cfg->rx_time_stamp_en) -+ tmp |= RCTRL_RTSE; -+ if (cfg->rx_drop_bcast) -+ tmp |= RCTRL_BC_REJ; -+ if (cfg->rx_short_frm) -+ tmp |= RCTRL_RSF; -+ if (cfg->rx_promisc) -+ tmp |= RCTRL_PROM; -+ -+ iowrite32be(tmp, ®s->rctrl); -+ /***************RCTRL************************/ -+ -+ /* -+ * Assign a Phy Address to the TBI (TBIPA). -+ * Done also in cases where TBI is not selected to avoid conflict with -+ * the external PHY's Physical address -+ */ -+ iowrite32be(cfg->tbipa, ®s->tbipa); -+ -+ /***************TMR_CTL************************/ -+ iowrite32be(0, ®s->tmr_ctrl); -+ -+ if (cfg->ptp_tsu_en) { -+ tmp = 0; -+ tmp |= TMR_PEVENT_TSRE; -+ iowrite32be(tmp, ®s->tmr_pevent); -+ -+ if (cfg->ptp_exception_en) { -+ tmp = 0; -+ tmp |= TMR_PEMASK_TSREEN; -+ iowrite32be(tmp, ®s->tmr_pemask); -+ } -+ } -+ -+ /***************MACCFG1***********************/ -+ tmp = 0; -+ if (cfg->loopback) -+ tmp |= MACCFG1_LOOPBACK; -+ if (cfg->rx_flow) -+ tmp |= MACCFG1_RX_FLOW; -+ if (cfg->tx_flow) -+ tmp |= MACCFG1_TX_FLOW; -+ iowrite32be(tmp, ®s->maccfg1); -+ -+ /***************MACCFG1***********************/ -+ -+ /***************MACCFG2***********************/ -+ tmp = 0; -+ -+ if (iface_speed < E_ENET_SPEED_1000) -+ tmp |= MACCFG2_NIBBLE_MODE; -+ else if (iface_speed == E_ENET_SPEED_1000) -+ tmp |= MACCFG2_BYTE_MODE; -+ -+ tmp |= ((uint32_t) cfg->preamble_len & 0x0000000f) -+ << PREAMBLE_LENGTH_SHIFT; -+ -+ if (cfg->rx_preamble) -+ tmp |= MACCFG2_PRE_AM_Rx_EN; -+ if (cfg->tx_preamble) -+ tmp |= MACCFG2_PRE_AM_Tx_EN; -+ if (cfg->rx_len_check) -+ tmp |= MACCFG2_LENGTH_CHECK; -+ if (cfg->tx_pad_crc) -+ tmp |= MACCFG2_PAD_CRC_EN; -+ if (cfg->tx_crc) -+ tmp |= MACCFG2_CRC_EN; -+ if (!cfg->halfdup_on) -+ tmp |= MACCFG2_FULL_DUPLEX; -+ iowrite32be(tmp, ®s->maccfg2); -+ -+ /***************MACCFG2***********************/ -+ -+ /***************IPGIFG************************/ -+ tmp = (((cfg->non_back_to_back_ipg1 << -+ IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT) -+ & IPGIFG_NON_BACK_TO_BACK_IPG_1) -+ | ((cfg->non_back_to_back_ipg2 << -+ IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT) -+ & IPGIFG_NON_BACK_TO_BACK_IPG_2) -+ | ((cfg->min_ifg_enforcement << -+ IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT) -+ & IPGIFG_MIN_IFG_ENFORCEMENT) -+ | (cfg->back_to_back_ipg & IPGIFG_BACK_TO_BACK_IPG)); -+ iowrite32be(tmp, ®s->ipgifg); -+ -+ /***************IPGIFG************************/ -+ -+ /***************HAFDUP************************/ -+ tmp = 0; -+ -+ if (cfg->halfdup_alt_backoff_en) -+ tmp = (uint32_t)(HAFDUP_ALT_BEB | -+ ((cfg->halfdup_alt_backoff_val & 0x0000000f) -+ << HAFDUP_ALTERNATE_BEB_TRUNCATION_SHIFT)); -+ if (cfg->halfdup_bp_no_backoff) -+ tmp |= HAFDUP_BP_NO_BACKOFF; -+ if (cfg->halfdup_no_backoff) -+ tmp |= HAFDUP_NO_BACKOFF; -+ if (cfg->halfdup_excess_defer) -+ tmp |= HAFDUP_EXCESS_DEFER; -+ tmp |= ((cfg->halfdup_retransmit << HAFDUP_RETRANSMISSION_MAX_SHIFT) -+ & HAFDUP_RETRANSMISSION_MAX); -+ tmp |= (cfg->halfdup_coll_window & HAFDUP_COLLISION_WINDOW); -+ -+ iowrite32be(tmp, ®s->hafdup); -+ /***************HAFDUP************************/ -+ -+ /***************MAXFRM************************/ -+ /* Initialize MAXFRM */ -+ iowrite32be(cfg->maximum_frame, ®s->maxfrm); -+ -+ /***************MAXFRM************************/ -+ -+ /***************CAM1************************/ -+ iowrite32be(0xffffffff, ®s->cam1); -+ iowrite32be(0xffffffff, ®s->cam2); -+ -+ /***************IMASK************************/ -+ iowrite32be(exception_mask, ®s->imask); -+ /***************IMASK************************/ -+ -+ /***************IEVENT************************/ -+ iowrite32be(0xffffffff, ®s->ievent); -+ -+ /***************MACSTNADDR1/2*****************/ -+ -+ tmp = (uint32_t)((macaddr[5] << 24) | -+ (macaddr[4] << 16) | -+ (macaddr[3] << 8) | -+ macaddr[2]); -+ iowrite32be(tmp, ®s->macstnaddr1); -+ -+ tmp = (uint32_t)((macaddr[1] << 24) | -+ (macaddr[0] << 16)); -+ iowrite32be(tmp, ®s->macstnaddr2); -+ -+ /***************MACSTNADDR1/2*****************/ -+ -+ /*****************HASH************************/ -+ for (i = 0; i < NUM_OF_HASH_REGS ; i++) { -+ /* Initialize IADDRx */ -+ iowrite32be(0, ®s->igaddr[i]); -+ /* Initialize GADDRx */ -+ iowrite32be(0, ®s->gaddr[i]); -+ } -+ -+ fman_dtsec_reset_stat(regs); -+ -+ return 0; -+} -+ -+uint16_t fman_dtsec_get_max_frame_len(struct dtsec_regs *regs) -+{ -+ return (uint16_t)ioread32be(®s->maxfrm); -+} -+ -+void fman_dtsec_set_max_frame_len(struct dtsec_regs *regs, uint16_t length) -+{ -+ iowrite32be(length, ®s->maxfrm); -+} -+ -+void fman_dtsec_set_mac_address(struct dtsec_regs *regs, uint8_t *adr) -+{ -+ uint32_t tmp; -+ -+ tmp = (uint32_t)((adr[5] << 24) | -+ (adr[4] << 16) | -+ (adr[3] << 8) | -+ adr[2]); -+ iowrite32be(tmp, ®s->macstnaddr1); -+ -+ tmp = (uint32_t)((adr[1] << 24) | -+ (adr[0] << 16)); -+ iowrite32be(tmp, ®s->macstnaddr2); -+} -+ -+void fman_dtsec_get_mac_address(struct dtsec_regs *regs, uint8_t *macaddr) -+{ -+ uint32_t tmp1, tmp2; -+ -+ tmp1 = ioread32be(®s->macstnaddr1); -+ tmp2 = ioread32be(®s->macstnaddr2); -+ -+ macaddr[0] = (uint8_t)((tmp2 & 0x00ff0000) >> 16); -+ macaddr[1] = (uint8_t)((tmp2 & 0xff000000) >> 24); -+ macaddr[2] = (uint8_t)(tmp1 & 0x000000ff); -+ macaddr[3] = (uint8_t)((tmp1 & 0x0000ff00) >> 8); -+ macaddr[4] = (uint8_t)((tmp1 & 0x00ff0000) >> 16); -+ macaddr[5] = (uint8_t)((tmp1 & 0xff000000) >> 24); -+} -+ -+void fman_dtsec_set_hash_table(struct dtsec_regs *regs, uint32_t crc, bool mcast, bool ghtx) -+{ -+ int32_t bucket; -+ if (ghtx) -+ bucket = (int32_t)((crc >> 23) & 0x1ff); -+ else { -+ bucket = (int32_t)((crc >> 24) & 0xff); -+ /* if !ghtx and mcast the bit must be set in gaddr instead of igaddr. */ -+ if (mcast) -+ bucket += 0x100; -+ } -+ fman_dtsec_set_bucket(regs, bucket, TRUE); -+} -+ -+void fman_dtsec_set_bucket(struct dtsec_regs *regs, int bucket, bool enable) -+{ -+ int reg_idx = (bucket >> 5) & 0xf; -+ int bit_idx = bucket & 0x1f; -+ uint32_t bit_mask = 0x80000000 >> bit_idx; -+ uint32_t *reg; -+ -+ if (reg_idx > 7) -+ reg = ®s->gaddr[reg_idx-8]; -+ else -+ reg = ®s->igaddr[reg_idx]; -+ -+ if (enable) -+ iowrite32be(ioread32be(reg) | bit_mask, reg); -+ else -+ iowrite32be(ioread32be(reg) & (~bit_mask), reg); -+} -+ -+void fman_dtsec_reset_filter_table(struct dtsec_regs *regs, bool mcast, bool ucast) -+{ -+ int i; -+ bool ghtx; -+ -+ ghtx = (bool)((ioread32be(®s->rctrl) & RCTRL_GHTX) ? TRUE : FALSE); -+ -+ if (ucast || (ghtx && mcast)) { -+ for (i = 0; i < NUM_OF_HASH_REGS; i++) -+ iowrite32be(0, ®s->igaddr[i]); -+ } -+ if (mcast) { -+ for (i = 0; i < NUM_OF_HASH_REGS; i++) -+ iowrite32be(0, ®s->gaddr[i]); -+ } -+} -+ -+int fman_dtsec_set_tbi_phy_addr(struct dtsec_regs *regs, -+ uint8_t addr) -+{ -+ if (addr > 0 && addr < 32) -+ iowrite32be(addr, ®s->tbipa); -+ else -+ return -EINVAL; -+ -+ return 0; -+} -+ -+void fman_dtsec_set_wol(struct dtsec_regs *regs, bool en) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->maccfg2); -+ if (en) -+ tmp |= MACCFG2_MAGIC_PACKET_EN; -+ else -+ tmp &= ~MACCFG2_MAGIC_PACKET_EN; -+ iowrite32be(tmp, ®s->maccfg2); -+} -+ -+int fman_dtsec_adjust_link(struct dtsec_regs *regs, -+ enum enet_interface iface_mode, -+ enum enet_speed speed, bool full_dx) -+{ -+ uint32_t tmp; -+ -+ UNUSED(iface_mode); -+ -+ if ((speed == E_ENET_SPEED_1000) && !full_dx) -+ return -EINVAL; -+ -+ tmp = ioread32be(®s->maccfg2); -+ if (!full_dx) -+ tmp &= ~MACCFG2_FULL_DUPLEX; -+ else -+ tmp |= MACCFG2_FULL_DUPLEX; -+ -+ tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE); -+ if (speed < E_ENET_SPEED_1000) -+ tmp |= MACCFG2_NIBBLE_MODE; -+ else if (speed == E_ENET_SPEED_1000) -+ tmp |= MACCFG2_BYTE_MODE; -+ iowrite32be(tmp, ®s->maccfg2); -+ -+ tmp = ioread32be(®s->ecntrl); -+ if (speed == E_ENET_SPEED_100) -+ tmp |= DTSEC_ECNTRL_R100M; -+ else -+ tmp &= ~DTSEC_ECNTRL_R100M; -+ iowrite32be(tmp, ®s->ecntrl); -+ -+ return 0; -+} -+ -+void fman_dtsec_set_uc_promisc(struct dtsec_regs *regs, bool enable) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->rctrl); -+ -+ if (enable) -+ tmp |= RCTRL_UPROM; -+ else -+ tmp &= ~RCTRL_UPROM; -+ -+ iowrite32be(tmp, ®s->rctrl); -+} -+ -+void fman_dtsec_set_mc_promisc(struct dtsec_regs *regs, bool enable) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->rctrl); -+ -+ if (enable) -+ tmp |= RCTRL_MPROM; -+ else -+ tmp &= ~RCTRL_MPROM; -+ -+ iowrite32be(tmp, ®s->rctrl); -+} -+ -+bool fman_dtsec_get_clear_carry_regs(struct dtsec_regs *regs, -+ uint32_t *car1, uint32_t *car2) -+{ -+ /* read carry registers */ -+ *car1 = ioread32be(®s->car1); -+ *car2 = ioread32be(®s->car2); -+ /* clear carry registers */ -+ if (*car1) -+ iowrite32be(*car1, ®s->car1); -+ if (*car2) -+ iowrite32be(*car2, ®s->car2); -+ -+ return (bool)((*car1 | *car2) ? TRUE : FALSE); -+} -+ -+void fman_dtsec_reset_stat(struct dtsec_regs *regs) -+{ -+ /* clear HW counters */ -+ iowrite32be(ioread32be(®s->ecntrl) | -+ DTSEC_ECNTRL_CLRCNT, ®s->ecntrl); -+} -+ -+int fman_dtsec_set_stat_level(struct dtsec_regs *regs, enum dtsec_stat_level level) -+{ -+ switch (level) { -+ case E_MAC_STAT_NONE: -+ iowrite32be(0xffffffff, ®s->cam1); -+ iowrite32be(0xffffffff, ®s->cam2); -+ iowrite32be(ioread32be(®s->ecntrl) & ~DTSEC_ECNTRL_STEN, -+ ®s->ecntrl); -+ iowrite32be(ioread32be(®s->imask) & ~DTSEC_IMASK_MSROEN, -+ ®s->imask); -+ break; -+ case E_MAC_STAT_PARTIAL: -+ iowrite32be(CAM1_ERRORS_ONLY, ®s->cam1); -+ iowrite32be(CAM2_ERRORS_ONLY, ®s->cam2); -+ iowrite32be(ioread32be(®s->ecntrl) | DTSEC_ECNTRL_STEN, -+ ®s->ecntrl); -+ iowrite32be(ioread32be(®s->imask) | DTSEC_IMASK_MSROEN, -+ ®s->imask); -+ break; -+ case E_MAC_STAT_MIB_GRP1: -+ iowrite32be((uint32_t)~CAM1_MIB_GRP_1, ®s->cam1); -+ iowrite32be((uint32_t)~CAM2_MIB_GRP_1, ®s->cam2); -+ iowrite32be(ioread32be(®s->ecntrl) | DTSEC_ECNTRL_STEN, -+ ®s->ecntrl); -+ iowrite32be(ioread32be(®s->imask) | DTSEC_IMASK_MSROEN, -+ ®s->imask); -+ break; -+ case E_MAC_STAT_FULL: -+ iowrite32be(0, ®s->cam1); -+ iowrite32be(0, ®s->cam2); -+ iowrite32be(ioread32be(®s->ecntrl) | DTSEC_ECNTRL_STEN, -+ ®s->ecntrl); -+ iowrite32be(ioread32be(®s->imask) | DTSEC_IMASK_MSROEN, -+ ®s->imask); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+void fman_dtsec_set_ts(struct dtsec_regs *regs, bool en) -+{ -+ if (en) { -+ iowrite32be(ioread32be(®s->rctrl) | RCTRL_RTSE, -+ ®s->rctrl); -+ iowrite32be(ioread32be(®s->tctrl) | DTSEC_TCTRL_TTSE, -+ ®s->tctrl); -+ } else { -+ iowrite32be(ioread32be(®s->rctrl) & ~RCTRL_RTSE, -+ ®s->rctrl); -+ iowrite32be(ioread32be(®s->tctrl) & ~DTSEC_TCTRL_TTSE, -+ ®s->tctrl); -+ } -+} -+ -+void fman_dtsec_enable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->maccfg1); -+ -+ if (apply_rx) -+ tmp |= MACCFG1_RX_EN ; -+ -+ if (apply_tx) -+ tmp |= MACCFG1_TX_EN ; -+ -+ iowrite32be(tmp, ®s->maccfg1); -+} -+ -+void fman_dtsec_clear_addr_in_paddr(struct dtsec_regs *regs, uint8_t paddr_num) -+{ -+ iowrite32be(0, ®s->macaddr[paddr_num].exact_match1); -+ iowrite32be(0, ®s->macaddr[paddr_num].exact_match2); -+} -+ -+void fman_dtsec_add_addr_in_paddr(struct dtsec_regs *regs, -+ uint64_t addr, -+ uint8_t paddr_num) -+{ -+ uint32_t tmp; -+ -+ tmp = (uint32_t)(addr); -+ /* swap */ -+ tmp = (((tmp & 0x000000FF) << 24) | -+ ((tmp & 0x0000FF00) << 8) | -+ ((tmp & 0x00FF0000) >> 8) | -+ ((tmp & 0xFF000000) >> 24)); -+ iowrite32be(tmp, ®s->macaddr[paddr_num].exact_match1); -+ -+ tmp = (uint32_t)(addr>>32); -+ /* swap */ -+ tmp = (((tmp & 0x000000FF) << 24) | -+ ((tmp & 0x0000FF00) << 8) | -+ ((tmp & 0x00FF0000) >> 8) | -+ ((tmp & 0xFF000000) >> 24)); -+ iowrite32be(tmp, ®s->macaddr[paddr_num].exact_match2); -+} -+ -+void fman_dtsec_disable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->maccfg1); -+ -+ if (apply_rx) -+ tmp &= ~MACCFG1_RX_EN; -+ -+ if (apply_tx) -+ tmp &= ~MACCFG1_TX_EN; -+ -+ iowrite32be(tmp, ®s->maccfg1); -+} -+ -+void fman_dtsec_set_tx_pause_frames(struct dtsec_regs *regs, uint16_t time) -+{ -+ uint32_t ptv = 0; -+ -+ /* fixme: don't enable tx pause for half-duplex */ -+ -+ if (time) { -+ ptv = ioread32be(®s->ptv); -+ ptv &= 0xffff0000; -+ ptv |= time & 0x0000ffff; -+ iowrite32be(ptv, ®s->ptv); -+ -+ /* trigger the transmission of a flow-control pause frame */ -+ iowrite32be(ioread32be(®s->maccfg1) | MACCFG1_TX_FLOW, -+ ®s->maccfg1); -+ } else -+ iowrite32be(ioread32be(®s->maccfg1) & ~MACCFG1_TX_FLOW, -+ ®s->maccfg1); -+} -+ -+void fman_dtsec_handle_rx_pause(struct dtsec_regs *regs, bool en) -+{ -+ uint32_t tmp; -+ -+ /* todo: check if mac is set to full-duplex */ -+ -+ tmp = ioread32be(®s->maccfg1); -+ if (en) -+ tmp |= MACCFG1_RX_FLOW; -+ else -+ tmp &= ~MACCFG1_RX_FLOW; -+ iowrite32be(tmp, ®s->maccfg1); -+} -+ -+uint32_t fman_dtsec_get_rctrl(struct dtsec_regs *regs) -+{ -+ return ioread32be(®s->rctrl); -+} -+ -+uint32_t fman_dtsec_get_revision(struct dtsec_regs *regs) -+{ -+ return ioread32be(®s->tsec_id); -+} -+ -+uint32_t fman_dtsec_get_event(struct dtsec_regs *regs, uint32_t ev_mask) -+{ -+ return ioread32be(®s->ievent) & ev_mask; -+} -+ -+void fman_dtsec_ack_event(struct dtsec_regs *regs, uint32_t ev_mask) -+{ -+ iowrite32be(ev_mask, ®s->ievent); -+} -+ -+uint32_t fman_dtsec_get_interrupt_mask(struct dtsec_regs *regs) -+{ -+ return ioread32be(®s->imask); -+} -+ -+uint32_t fman_dtsec_check_and_clear_tmr_event(struct dtsec_regs *regs) -+{ -+ uint32_t event; -+ -+ event = ioread32be(®s->tmr_pevent); -+ event &= ioread32be(®s->tmr_pemask); -+ -+ if (event) -+ iowrite32be(event, ®s->tmr_pevent); -+ return event; -+} -+ -+void fman_dtsec_enable_tmr_interrupt(struct dtsec_regs *regs) -+{ -+ iowrite32be(ioread32be(®s->tmr_pemask) | TMR_PEMASK_TSREEN, -+ ®s->tmr_pemask); -+} -+ -+void fman_dtsec_disable_tmr_interrupt(struct dtsec_regs *regs) -+{ -+ iowrite32be(ioread32be(®s->tmr_pemask) & ~TMR_PEMASK_TSREEN, -+ ®s->tmr_pemask); -+} -+ -+void fman_dtsec_enable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask) -+{ -+ iowrite32be(ioread32be(®s->imask) | ev_mask, ®s->imask); -+} -+ -+void fman_dtsec_disable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask) -+{ -+ iowrite32be(ioread32be(®s->imask) & ~ev_mask, ®s->imask); -+} -+ -+uint32_t fman_dtsec_get_stat_counter(struct dtsec_regs *regs, -+ enum dtsec_stat_counters reg_name) -+{ -+ uint32_t ret_val; -+ -+ switch (reg_name) { -+ case E_DTSEC_STAT_TR64: -+ ret_val = ioread32be(®s->tr64); -+ break; -+ case E_DTSEC_STAT_TR127: -+ ret_val = ioread32be(®s->tr127); -+ break; -+ case E_DTSEC_STAT_TR255: -+ ret_val = ioread32be(®s->tr255); -+ break; -+ case E_DTSEC_STAT_TR511: -+ ret_val = ioread32be(®s->tr511); -+ break; -+ case E_DTSEC_STAT_TR1K: -+ ret_val = ioread32be(®s->tr1k); -+ break; -+ case E_DTSEC_STAT_TRMAX: -+ ret_val = ioread32be(®s->trmax); -+ break; -+ case E_DTSEC_STAT_TRMGV: -+ ret_val = ioread32be(®s->trmgv); -+ break; -+ case E_DTSEC_STAT_RBYT: -+ ret_val = ioread32be(®s->rbyt); -+ break; -+ case E_DTSEC_STAT_RPKT: -+ ret_val = ioread32be(®s->rpkt); -+ break; -+ case E_DTSEC_STAT_RMCA: -+ ret_val = ioread32be(®s->rmca); -+ break; -+ case E_DTSEC_STAT_RBCA: -+ ret_val = ioread32be(®s->rbca); -+ break; -+ case E_DTSEC_STAT_RXPF: -+ ret_val = ioread32be(®s->rxpf); -+ break; -+ case E_DTSEC_STAT_RALN: -+ ret_val = ioread32be(®s->raln); -+ break; -+ case E_DTSEC_STAT_RFLR: -+ ret_val = ioread32be(®s->rflr); -+ break; -+ case E_DTSEC_STAT_RCDE: -+ ret_val = ioread32be(®s->rcde); -+ break; -+ case E_DTSEC_STAT_RCSE: -+ ret_val = ioread32be(®s->rcse); -+ break; -+ case E_DTSEC_STAT_RUND: -+ ret_val = ioread32be(®s->rund); -+ break; -+ case E_DTSEC_STAT_ROVR: -+ ret_val = ioread32be(®s->rovr); -+ break; -+ case E_DTSEC_STAT_RFRG: -+ ret_val = ioread32be(®s->rfrg); -+ break; -+ case E_DTSEC_STAT_RJBR: -+ ret_val = ioread32be(®s->rjbr); -+ break; -+ case E_DTSEC_STAT_RDRP: -+ ret_val = ioread32be(®s->rdrp); -+ break; -+ case E_DTSEC_STAT_TFCS: -+ ret_val = ioread32be(®s->tfcs); -+ break; -+ case E_DTSEC_STAT_TBYT: -+ ret_val = ioread32be(®s->tbyt); -+ break; -+ case E_DTSEC_STAT_TPKT: -+ ret_val = ioread32be(®s->tpkt); -+ break; -+ case E_DTSEC_STAT_TMCA: -+ ret_val = ioread32be(®s->tmca); -+ break; -+ case E_DTSEC_STAT_TBCA: -+ ret_val = ioread32be(®s->tbca); -+ break; -+ case E_DTSEC_STAT_TXPF: -+ ret_val = ioread32be(®s->txpf); -+ break; -+ case E_DTSEC_STAT_TNCL: -+ ret_val = ioread32be(®s->tncl); -+ break; -+ case E_DTSEC_STAT_TDRP: -+ ret_val = ioread32be(®s->tdrp); -+ break; -+ default: -+ ret_val = 0; -+ } -+ -+ return ret_val; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec_mii_acc.c -@@ -0,0 +1,163 @@ -+/* -+ * Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include "common/general.h" -+#include "fsl_fman_dtsec_mii_acc.h" -+ -+ -+/** -+ * dtsec_mii_get_div() - calculates the value of the dtsec mii divider -+ * @dtsec_freq: dtsec clock frequency (in Mhz) -+ * -+ * This function calculates the dtsec mii clock divider that determines -+ * the MII MDC clock. MII MDC clock will be set to work in the range -+ * of 1.5 to 2.5Mhz -+ * The output of this function is the value of MIIMCFG[MgmtClk] which -+ * implicitly determines the divider value. -+ * Note: the dTSEC system clock is equal to 1/2 of the FMan clock. -+ * -+ * The table below which reflects dtsec_mii_get_div() functionality -+ * shows the relations among dtsec_freq, MgmtClk, actual divider -+ * and the MII frequency: -+ * -+ * dtsec freq MgmtClk div MII freq Mhz -+ * [0.....80] 1 (1/4)(1/8) [0 to 2.5] -+ * [81...120] 2 (1/6)(1/8) [1.6 to 2.5] -+ * [121..160] 3 (1/8)(1/8) [1.8 to 2.5] -+ * [161..200] 4 (1/10)(1/8) [2.0 to 2.5] -+ * [201..280] 5 (1/14)(1/8) [1.8 to 2.5] -+ * [281..400] 6 (1/20)(1/8) [1.1 to 2.5] -+ * [401..560] 7 (1/28)(1/8) [1.8 to 2.5] -+ * [560..frq] 7 (1/28)(1/8) [frq/224] -+ * -+ * Returns: the MIIMCFG[MgmtClk] appropriate value -+ */ -+ -+static uint8_t dtsec_mii_get_div(uint16_t dtsec_freq) -+{ -+ uint16_t mgmt_clk; -+ -+ if (dtsec_freq < 80) mgmt_clk = 1; -+ else if (dtsec_freq < 120) mgmt_clk = 2; -+ else if (dtsec_freq < 160) mgmt_clk = 3; -+ else if (dtsec_freq < 200) mgmt_clk = 4; -+ else if (dtsec_freq < 280) mgmt_clk = 5; -+ else if (dtsec_freq < 400) mgmt_clk = 6; -+ else mgmt_clk = 7; -+ -+ return (uint8_t)mgmt_clk; -+} -+ -+void fman_dtsec_mii_reset(struct dtsec_mii_reg *regs) -+{ -+ /* Reset the management interface */ -+ iowrite32be(ioread32be(®s->miimcfg) | MIIMCFG_RESET_MGMT, -+ ®s->miimcfg); -+ iowrite32be(ioread32be(®s->miimcfg) & ~MIIMCFG_RESET_MGMT, -+ ®s->miimcfg); -+} -+ -+ -+int fman_dtsec_mii_write_reg(struct dtsec_mii_reg *regs, uint8_t addr, -+ uint8_t reg, uint16_t data, uint16_t dtsec_freq) -+{ -+ uint32_t tmp; -+ -+ /* Setup the MII Mgmt clock speed */ -+ iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), ®s->miimcfg); -+ wmb(); -+ -+ /* Stop the MII management read cycle */ -+ iowrite32be(0, ®s->miimcom); -+ /* Dummy read to make sure MIIMCOM is written */ -+ tmp = ioread32be(®s->miimcom); -+ wmb(); -+ -+ /* Setting up MII Management Address Register */ -+ tmp = (uint32_t)((addr << MIIMADD_PHY_ADDR_SHIFT) | reg); -+ iowrite32be(tmp, ®s->miimadd); -+ wmb(); -+ -+ /* Setting up MII Management Control Register with data */ -+ iowrite32be((uint32_t)data, ®s->miimcon); -+ /* Dummy read to make sure MIIMCON is written */ -+ tmp = ioread32be(®s->miimcon); -+ wmb(); -+ -+ /* Wait until MII management write is complete */ -+ /* todo: a timeout could be useful here */ -+ while ((ioread32be(®s->miimind)) & MIIMIND_BUSY) -+ /* busy wait */; -+ -+ return 0; -+} -+ -+int fman_dtsec_mii_read_reg(struct dtsec_mii_reg *regs, uint8_t addr, -+ uint8_t reg, uint16_t *data, uint16_t dtsec_freq) -+{ -+ uint32_t tmp; -+ -+ /* Setup the MII Mgmt clock speed */ -+ iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), ®s->miimcfg); -+ wmb(); -+ -+ /* Setting up the MII Management Address Register */ -+ tmp = (uint32_t)((addr << MIIMADD_PHY_ADDR_SHIFT) | reg); -+ iowrite32be(tmp, ®s->miimadd); -+ wmb(); -+ -+ /* Perform an MII management read cycle */ -+ iowrite32be(MIIMCOM_READ_CYCLE, ®s->miimcom); -+ /* Dummy read to make sure MIIMCOM is written */ -+ tmp = ioread32be(®s->miimcom); -+ wmb(); -+ -+ /* Wait until MII management read is complete */ -+ /* todo: a timeout could be useful here */ -+ while ((ioread32be(®s->miimind)) & MIIMIND_BUSY) -+ /* busy wait */; -+ -+ /* Read MII management status */ -+ *data = (uint16_t)ioread32be(®s->miimstat); -+ wmb(); -+ -+ iowrite32be(0, ®s->miimcom); -+ /* Dummy read to make sure MIIMCOM is written */ -+ tmp = ioread32be(®s->miimcom); -+ -+ if (*data == 0xffff) -+ return -ENXIO; -+ -+ return 0; -+} -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac.c -@@ -0,0 +1,511 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include "fsl_fman_memac.h" -+ -+ -+uint32_t fman_memac_get_event(struct memac_regs *regs, uint32_t ev_mask) -+{ -+ return ioread32be(®s->ievent) & ev_mask; -+} -+ -+uint32_t fman_memac_get_interrupt_mask(struct memac_regs *regs) -+{ -+ return ioread32be(®s->imask); -+} -+ -+void fman_memac_ack_event(struct memac_regs *regs, uint32_t ev_mask) -+{ -+ iowrite32be(ev_mask, ®s->ievent); -+} -+ -+void fman_memac_set_promiscuous(struct memac_regs *regs, bool val) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->command_config); -+ -+ if (val) -+ tmp |= CMD_CFG_PROMIS_EN; -+ else -+ tmp &= ~CMD_CFG_PROMIS_EN; -+ -+ iowrite32be(tmp, ®s->command_config); -+} -+ -+void fman_memac_clear_addr_in_paddr(struct memac_regs *regs, -+ uint8_t paddr_num) -+{ -+ if (paddr_num == 0) { -+ iowrite32be(0, ®s->mac_addr0.mac_addr_l); -+ iowrite32be(0, ®s->mac_addr0.mac_addr_u); -+ } else { -+ iowrite32be(0x0, ®s->mac_addr[paddr_num - 1].mac_addr_l); -+ iowrite32be(0x0, ®s->mac_addr[paddr_num - 1].mac_addr_u); -+ } -+} -+ -+void fman_memac_add_addr_in_paddr(struct memac_regs *regs, -+ uint8_t *adr, -+ uint8_t paddr_num) -+{ -+ uint32_t tmp0, tmp1; -+ -+ tmp0 = (uint32_t)(adr[0] | -+ adr[1] << 8 | -+ adr[2] << 16 | -+ adr[3] << 24); -+ tmp1 = (uint32_t)(adr[4] | adr[5] << 8); -+ -+ if (paddr_num == 0) { -+ iowrite32be(tmp0, ®s->mac_addr0.mac_addr_l); -+ iowrite32be(tmp1, ®s->mac_addr0.mac_addr_u); -+ } else { -+ iowrite32be(tmp0, ®s->mac_addr[paddr_num-1].mac_addr_l); -+ iowrite32be(tmp1, ®s->mac_addr[paddr_num-1].mac_addr_u); -+ } -+} -+ -+void fman_memac_enable(struct memac_regs *regs, bool apply_rx, bool apply_tx) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->command_config); -+ -+ if (apply_rx) -+ tmp |= CMD_CFG_RX_EN; -+ -+ if (apply_tx) -+ tmp |= CMD_CFG_TX_EN; -+ -+ iowrite32be(tmp, ®s->command_config); -+} -+ -+void fman_memac_disable(struct memac_regs *regs, bool apply_rx, bool apply_tx) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->command_config); -+ -+ if (apply_rx) -+ tmp &= ~CMD_CFG_RX_EN; -+ -+ if (apply_tx) -+ tmp &= ~CMD_CFG_TX_EN; -+ -+ iowrite32be(tmp, ®s->command_config); -+} -+ -+void fman_memac_reset_stat(struct memac_regs *regs) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->statn_config); -+ -+ tmp |= STATS_CFG_CLR; -+ -+ iowrite32be(tmp, ®s->statn_config); -+ -+ while (ioread32be(®s->statn_config) & STATS_CFG_CLR); -+} -+ -+void fman_memac_reset(struct memac_regs *regs) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->command_config); -+ -+ tmp |= CMD_CFG_SW_RESET; -+ -+ iowrite32be(tmp, ®s->command_config); -+ -+ while (ioread32be(®s->command_config) & CMD_CFG_SW_RESET); -+} -+ -+int fman_memac_init(struct memac_regs *regs, -+ struct memac_cfg *cfg, -+ enum enet_interface enet_interface, -+ enum enet_speed enet_speed, -+ bool slow_10g_if, -+ uint32_t exceptions) -+{ -+ uint32_t tmp; -+ -+ /* Config */ -+ tmp = 0; -+ if (cfg->wan_mode_enable) -+ tmp |= CMD_CFG_WAN_MODE; -+ if (cfg->promiscuous_mode_enable) -+ tmp |= CMD_CFG_PROMIS_EN; -+ if (cfg->pause_forward_enable) -+ tmp |= CMD_CFG_PAUSE_FWD; -+ if (cfg->pause_ignore) -+ tmp |= CMD_CFG_PAUSE_IGNORE; -+ if (cfg->tx_addr_ins_enable) -+ tmp |= CMD_CFG_TX_ADDR_INS; -+ if (cfg->loopback_enable) -+ tmp |= CMD_CFG_LOOPBACK_EN; -+ if (cfg->cmd_frame_enable) -+ tmp |= CMD_CFG_CNT_FRM_EN; -+ if (cfg->send_idle_enable) -+ tmp |= CMD_CFG_SEND_IDLE; -+ if (cfg->no_length_check_enable) -+ tmp |= CMD_CFG_NO_LEN_CHK; -+ if (cfg->rx_sfd_any) -+ tmp |= CMD_CFG_SFD_ANY; -+ if (cfg->pad_enable) -+ tmp |= CMD_CFG_TX_PAD_EN; -+ if (cfg->wake_on_lan) -+ tmp |= CMD_CFG_MG; -+ -+ tmp |= CMD_CFG_CRC_FWD; -+ -+ iowrite32be(tmp, ®s->command_config); -+ -+ /* Max Frame Length */ -+ iowrite32be((uint32_t)cfg->max_frame_length, ®s->maxfrm); -+ -+ /* Pause Time */ -+ iowrite32be((uint32_t)cfg->pause_quanta, ®s->pause_quanta[0]); -+ iowrite32be((uint32_t)0, ®s->pause_thresh[0]); -+ -+ /* IF_MODE */ -+ tmp = 0; -+ switch (enet_interface) { -+ case E_ENET_IF_XGMII: -+ case E_ENET_IF_XFI: -+ tmp |= IF_MODE_XGMII; -+ break; -+ default: -+ tmp |= IF_MODE_GMII; -+ if (enet_interface == E_ENET_IF_RGMII && !cfg->loopback_enable) -+ tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO; -+ } -+ iowrite32be(tmp, ®s->if_mode); -+ -+ /* TX_FIFO_SECTIONS */ -+ tmp = 0; -+ if (enet_interface == E_ENET_IF_XGMII || -+ enet_interface == E_ENET_IF_XFI) { -+ if(slow_10g_if) { -+ tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G | -+ TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G); -+ } else { -+ tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G | -+ TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G); -+ } -+ } else { -+ tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G | -+ TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G); -+ } -+ iowrite32be(tmp, ®s->tx_fifo_sections); -+ -+ /* clear all pending events and set-up interrupts */ -+ fman_memac_ack_event(regs, 0xffffffff); -+ fman_memac_set_exception(regs, exceptions, TRUE); -+ -+ return 0; -+} -+ -+void fman_memac_set_exception(struct memac_regs *regs, uint32_t val, bool enable) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->imask); -+ if (enable) -+ tmp |= val; -+ else -+ tmp &= ~val; -+ -+ iowrite32be(tmp, ®s->imask); -+} -+ -+void fman_memac_reset_filter_table(struct memac_regs *regs) -+{ -+ uint32_t i; -+ for (i = 0; i < 64; i++) -+ iowrite32be(i & ~HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl); -+} -+ -+void fman_memac_set_hash_table_entry(struct memac_regs *regs, uint32_t crc) -+{ -+ iowrite32be(crc | HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl); -+} -+ -+void fman_memac_set_hash_table(struct memac_regs *regs, uint32_t val) -+{ -+ iowrite32be(val, ®s->hashtable_ctrl); -+} -+ -+uint16_t fman_memac_get_max_frame_len(struct memac_regs *regs) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->maxfrm); -+ -+ return(uint16_t)tmp; -+} -+ -+ -+void fman_memac_set_tx_pause_frames(struct memac_regs *regs, -+ uint8_t priority, -+ uint16_t pause_time, -+ uint16_t thresh_time) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->tx_fifo_sections); -+ -+ if (priority == 0xff) { -+ GET_TX_EMPTY_DEFAULT_VALUE(tmp); -+ iowrite32be(tmp, ®s->tx_fifo_sections); -+ -+ tmp = ioread32be(®s->command_config); -+ tmp &= ~CMD_CFG_PFC_MODE; -+ priority = 0; -+ } else { -+ GET_TX_EMPTY_PFC_VALUE(tmp); -+ iowrite32be(tmp, ®s->tx_fifo_sections); -+ -+ tmp = ioread32be(®s->command_config); -+ tmp |= CMD_CFG_PFC_MODE; -+ } -+ -+ iowrite32be(tmp, ®s->command_config); -+ -+ tmp = ioread32be(®s->pause_quanta[priority / 2]); -+ if (priority % 2) -+ tmp &= 0x0000FFFF; -+ else -+ tmp &= 0xFFFF0000; -+ tmp |= ((uint32_t)pause_time << (16 * (priority % 2))); -+ iowrite32be(tmp, ®s->pause_quanta[priority / 2]); -+ -+ tmp = ioread32be(®s->pause_thresh[priority / 2]); -+ if (priority % 2) -+ tmp &= 0x0000FFFF; -+ else -+ tmp &= 0xFFFF0000; -+ tmp |= ((uint32_t)thresh_time<<(16 * (priority % 2))); -+ iowrite32be(tmp, ®s->pause_thresh[priority / 2]); -+} -+ -+void fman_memac_set_rx_ignore_pause_frames(struct memac_regs *regs,bool enable) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->command_config); -+ if (enable) -+ tmp |= CMD_CFG_PAUSE_IGNORE; -+ else -+ tmp &= ~CMD_CFG_PAUSE_IGNORE; -+ -+ iowrite32be(tmp, ®s->command_config); -+} -+ -+void fman_memac_set_wol(struct memac_regs *regs, bool enable) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->command_config); -+ -+ if (enable) -+ tmp |= CMD_CFG_MG; -+ else -+ tmp &= ~CMD_CFG_MG; -+ -+ iowrite32be(tmp, ®s->command_config); -+} -+ -+#define GET_MEMAC_CNTR_64(bn) \ -+ (ioread32be(®s->bn ## _l) | \ -+ ((uint64_t)ioread32be(®s->bn ## _u) << 32)) -+ -+uint64_t fman_memac_get_counter(struct memac_regs *regs, -+ enum memac_counters reg_name) -+{ -+ uint64_t ret_val; -+ -+ switch (reg_name) { -+ case E_MEMAC_COUNTER_R64: -+ ret_val = GET_MEMAC_CNTR_64(r64); -+ break; -+ case E_MEMAC_COUNTER_R127: -+ ret_val = GET_MEMAC_CNTR_64(r127); -+ break; -+ case E_MEMAC_COUNTER_R255: -+ ret_val = GET_MEMAC_CNTR_64(r255); -+ break; -+ case E_MEMAC_COUNTER_R511: -+ ret_val = GET_MEMAC_CNTR_64(r511); -+ break; -+ case E_MEMAC_COUNTER_R1023: -+ ret_val = GET_MEMAC_CNTR_64(r1023); -+ break; -+ case E_MEMAC_COUNTER_R1518: -+ ret_val = GET_MEMAC_CNTR_64(r1518); -+ break; -+ case E_MEMAC_COUNTER_R1519X: -+ ret_val = GET_MEMAC_CNTR_64(r1519x); -+ break; -+ case E_MEMAC_COUNTER_RFRG: -+ ret_val = GET_MEMAC_CNTR_64(rfrg); -+ break; -+ case E_MEMAC_COUNTER_RJBR: -+ ret_val = GET_MEMAC_CNTR_64(rjbr); -+ break; -+ case E_MEMAC_COUNTER_RDRP: -+ ret_val = GET_MEMAC_CNTR_64(rdrp); -+ break; -+ case E_MEMAC_COUNTER_RALN: -+ ret_val = GET_MEMAC_CNTR_64(raln); -+ break; -+ case E_MEMAC_COUNTER_TUND: -+ ret_val = GET_MEMAC_CNTR_64(tund); -+ break; -+ case E_MEMAC_COUNTER_ROVR: -+ ret_val = GET_MEMAC_CNTR_64(rovr); -+ break; -+ case E_MEMAC_COUNTER_RXPF: -+ ret_val = GET_MEMAC_CNTR_64(rxpf); -+ break; -+ case E_MEMAC_COUNTER_TXPF: -+ ret_val = GET_MEMAC_CNTR_64(txpf); -+ break; -+ case E_MEMAC_COUNTER_ROCT: -+ ret_val = GET_MEMAC_CNTR_64(roct); -+ break; -+ case E_MEMAC_COUNTER_RMCA: -+ ret_val = GET_MEMAC_CNTR_64(rmca); -+ break; -+ case E_MEMAC_COUNTER_RBCA: -+ ret_val = GET_MEMAC_CNTR_64(rbca); -+ break; -+ case E_MEMAC_COUNTER_RPKT: -+ ret_val = GET_MEMAC_CNTR_64(rpkt); -+ break; -+ case E_MEMAC_COUNTER_RUCA: -+ ret_val = GET_MEMAC_CNTR_64(ruca); -+ break; -+ case E_MEMAC_COUNTER_RERR: -+ ret_val = GET_MEMAC_CNTR_64(rerr); -+ break; -+ case E_MEMAC_COUNTER_TOCT: -+ ret_val = GET_MEMAC_CNTR_64(toct); -+ break; -+ case E_MEMAC_COUNTER_TMCA: -+ ret_val = GET_MEMAC_CNTR_64(tmca); -+ break; -+ case E_MEMAC_COUNTER_TBCA: -+ ret_val = GET_MEMAC_CNTR_64(tbca); -+ break; -+ case E_MEMAC_COUNTER_TUCA: -+ ret_val = GET_MEMAC_CNTR_64(tuca); -+ break; -+ case E_MEMAC_COUNTER_TERR: -+ ret_val = GET_MEMAC_CNTR_64(terr); -+ break; -+ default: -+ ret_val = 0; -+ } -+ -+ return ret_val; -+} -+ -+void fman_memac_adjust_link(struct memac_regs *regs, -+ enum enet_interface iface_mode, -+ enum enet_speed speed, bool full_dx) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->if_mode); -+ -+ if (full_dx) -+ tmp &= ~IF_MODE_HD; -+ else -+ tmp |= IF_MODE_HD; -+ -+ if (iface_mode == E_ENET_IF_RGMII) { -+ /* Configure RGMII in manual mode */ -+ tmp &= ~IF_MODE_RGMII_AUTO; -+ tmp &= ~IF_MODE_RGMII_SP_MASK; -+ -+ if (full_dx) -+ tmp |= IF_MODE_RGMII_FD; -+ else -+ tmp &= ~IF_MODE_RGMII_FD; -+ -+ switch (speed) { -+ case E_ENET_SPEED_1000: -+ tmp |= IF_MODE_RGMII_1000; -+ break; -+ case E_ENET_SPEED_100: -+ tmp |= IF_MODE_RGMII_100; -+ break; -+ case E_ENET_SPEED_10: -+ tmp |= IF_MODE_RGMII_10; -+ break; -+ default: -+ break; -+ } -+ } -+ -+ iowrite32be(tmp, ®s->if_mode); -+} -+ -+void fman_memac_defconfig(struct memac_cfg *cfg) -+{ -+ cfg->reset_on_init = FALSE; -+ cfg->wan_mode_enable = FALSE; -+ cfg->promiscuous_mode_enable = FALSE; -+ cfg->pause_forward_enable = FALSE; -+ cfg->pause_ignore = FALSE; -+ cfg->tx_addr_ins_enable = FALSE; -+ cfg->loopback_enable = FALSE; -+ cfg->cmd_frame_enable = FALSE; -+ cfg->rx_error_discard = FALSE; -+ cfg->send_idle_enable = FALSE; -+ cfg->no_length_check_enable = TRUE; -+ cfg->lgth_check_nostdr = FALSE; -+ cfg->time_stamp_enable = FALSE; -+ cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH; -+ cfg->max_frame_length = DEFAULT_FRAME_LENGTH; -+ cfg->pause_quanta = DEFAULT_PAUSE_QUANTA; -+ cfg->pad_enable = TRUE; -+ cfg->phy_tx_ena_on = FALSE; -+ cfg->rx_sfd_any = FALSE; -+ cfg->rx_pbl_fwd = FALSE; -+ cfg->tx_pbl_fwd = FALSE; -+ cfg->debug_mode = FALSE; -+ cfg->wake_on_lan = FALSE; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac_mii_acc.c -@@ -0,0 +1,213 @@ -+/* -+ * Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include "fsl_fman_memac_mii_acc.h" -+ -+static void write_phy_reg_10g(struct memac_mii_access_mem_map *mii_regs, -+ uint8_t phy_addr, uint8_t reg, uint16_t data) -+{ -+ uint32_t tmp_reg; -+ -+ tmp_reg = ioread32be(&mii_regs->mdio_cfg); -+ /* Leave only MDIO_CLK_DIV bits set on */ -+ tmp_reg &= MDIO_CFG_CLK_DIV_MASK; -+ /* Set maximum MDIO_HOLD value to allow phy to see -+ change of data signal */ -+ tmp_reg |= MDIO_CFG_HOLD_MASK; -+ /* Add 10G interface mode */ -+ tmp_reg |= MDIO_CFG_ENC45; -+ iowrite32be(tmp_reg, &mii_regs->mdio_cfg); -+ -+ /* Wait for command completion */ -+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY) -+ udelay(1); -+ -+ /* Specify phy and register to be accessed */ -+ iowrite32be(phy_addr, &mii_regs->mdio_ctrl); -+ iowrite32be(reg, &mii_regs->mdio_addr); -+ wmb(); -+ -+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY) -+ udelay(1); -+ -+ /* Write data */ -+ iowrite32be(data, &mii_regs->mdio_data); -+ wmb(); -+ -+ /* Wait for write transaction end */ -+ while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY) -+ udelay(1); -+} -+ -+static uint32_t read_phy_reg_10g(struct memac_mii_access_mem_map *mii_regs, -+ uint8_t phy_addr, uint8_t reg, uint16_t *data) -+{ -+ uint32_t tmp_reg; -+ -+ tmp_reg = ioread32be(&mii_regs->mdio_cfg); -+ /* Leave only MDIO_CLK_DIV bits set on */ -+ tmp_reg &= MDIO_CFG_CLK_DIV_MASK; -+ /* Set maximum MDIO_HOLD value to allow phy to see -+ change of data signal */ -+ tmp_reg |= MDIO_CFG_HOLD_MASK; -+ /* Add 10G interface mode */ -+ tmp_reg |= MDIO_CFG_ENC45; -+ iowrite32be(tmp_reg, &mii_regs->mdio_cfg); -+ -+ /* Wait for command completion */ -+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY) -+ udelay(1); -+ -+ /* Specify phy and register to be accessed */ -+ iowrite32be(phy_addr, &mii_regs->mdio_ctrl); -+ iowrite32be(reg, &mii_regs->mdio_addr); -+ wmb(); -+ -+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY) -+ udelay(1); -+ -+ /* Read cycle */ -+ tmp_reg = phy_addr; -+ tmp_reg |= MDIO_CTL_READ; -+ iowrite32be(tmp_reg, &mii_regs->mdio_ctrl); -+ wmb(); -+ -+ /* Wait for data to be available */ -+ while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY) -+ udelay(1); -+ -+ *data = (uint16_t)ioread32be(&mii_regs->mdio_data); -+ -+ /* Check if there was an error */ -+ return ioread32be(&mii_regs->mdio_cfg); -+} -+ -+static void write_phy_reg_1g(struct memac_mii_access_mem_map *mii_regs, -+ uint8_t phy_addr, uint8_t reg, uint16_t data) -+{ -+ uint32_t tmp_reg; -+ -+ /* Leave only MDIO_CLK_DIV and MDIO_HOLD bits set on */ -+ tmp_reg = ioread32be(&mii_regs->mdio_cfg); -+ tmp_reg &= (MDIO_CFG_CLK_DIV_MASK | MDIO_CFG_HOLD_MASK); -+ iowrite32be(tmp_reg, &mii_regs->mdio_cfg); -+ -+ /* Wait for command completion */ -+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY) -+ udelay(1); -+ -+ /* Write transaction */ -+ tmp_reg = (phy_addr << MDIO_CTL_PHY_ADDR_SHIFT); -+ tmp_reg |= reg; -+ iowrite32be(tmp_reg, &mii_regs->mdio_ctrl); -+ -+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY) -+ udelay(1); -+ -+ iowrite32be(data, &mii_regs->mdio_data); -+ -+ wmb(); -+ -+ /* Wait for write transaction to end */ -+ while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY) -+ udelay(1); -+} -+ -+static uint32_t read_phy_reg_1g(struct memac_mii_access_mem_map *mii_regs, -+ uint8_t phy_addr, uint8_t reg, uint16_t *data) -+{ -+ uint32_t tmp_reg; -+ -+ /* Leave only MDIO_CLK_DIV and MDIO_HOLD bits set on */ -+ tmp_reg = ioread32be(&mii_regs->mdio_cfg); -+ tmp_reg &= (MDIO_CFG_CLK_DIV_MASK | MDIO_CFG_HOLD_MASK); -+ iowrite32be(tmp_reg, &mii_regs->mdio_cfg); -+ -+ /* Wait for command completion */ -+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY) -+ udelay(1); -+ -+ /* Read transaction */ -+ tmp_reg = (phy_addr << MDIO_CTL_PHY_ADDR_SHIFT); -+ tmp_reg |= reg; -+ tmp_reg |= MDIO_CTL_READ; -+ iowrite32be(tmp_reg, &mii_regs->mdio_ctrl); -+ -+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY) -+ udelay(1); -+ -+ /* Wait for data to be available */ -+ while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY) -+ udelay(1); -+ -+ *data = (uint16_t)ioread32be(&mii_regs->mdio_data); -+ -+ /* Check error */ -+ return ioread32be(&mii_regs->mdio_cfg); -+} -+ -+/*****************************************************************************/ -+int fman_memac_mii_write_phy_reg(struct memac_mii_access_mem_map *mii_regs, -+ uint8_t phy_addr, uint8_t reg, uint16_t data, -+ enum enet_speed enet_speed) -+{ -+ /* Figure out interface type - 10G vs 1G. -+ In 10G interface both phy_addr and devAddr present. */ -+ if (enet_speed == E_ENET_SPEED_10000) -+ write_phy_reg_10g(mii_regs, phy_addr, reg, data); -+ else -+ write_phy_reg_1g(mii_regs, phy_addr, reg, data); -+ -+ return 0; -+} -+ -+/*****************************************************************************/ -+int fman_memac_mii_read_phy_reg(struct memac_mii_access_mem_map *mii_regs, -+ uint8_t phy_addr, uint8_t reg, uint16_t *data, -+ enum enet_speed enet_speed) -+{ -+ uint32_t ans; -+ /* Figure out interface type - 10G vs 1G. -+ In 10G interface both phy_addr and devAddr present. */ -+ if (enet_speed == E_ENET_SPEED_10000) -+ ans = read_phy_reg_10g(mii_regs, phy_addr, reg, data); -+ else -+ ans = read_phy_reg_1g(mii_regs, phy_addr, reg, data); -+ -+ if (ans & MDIO_CFG_READ_ERR) -+ return -EINVAL; -+ return 0; -+} -+ -+/* ......................................................................... */ -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_tgec.c -@@ -0,0 +1,367 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include "fsl_fman_tgec.h" -+ -+ -+void fman_tgec_set_mac_address(struct tgec_regs *regs, uint8_t *adr) -+{ -+ uint32_t tmp0, tmp1; -+ -+ tmp0 = (uint32_t)(adr[0] | -+ adr[1] << 8 | -+ adr[2] << 16 | -+ adr[3] << 24); -+ tmp1 = (uint32_t)(adr[4] | adr[5] << 8); -+ iowrite32be(tmp0, ®s->mac_addr_0); -+ iowrite32be(tmp1, ®s->mac_addr_1); -+} -+ -+void fman_tgec_reset_stat(struct tgec_regs *regs) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->command_config); -+ -+ tmp |= CMD_CFG_STAT_CLR; -+ -+ iowrite32be(tmp, ®s->command_config); -+ -+ while (ioread32be(®s->command_config) & CMD_CFG_STAT_CLR) ; -+} -+ -+#define GET_TGEC_CNTR_64(bn) \ -+ (((uint64_t)ioread32be(®s->bn ## _u) << 32) | \ -+ ioread32be(®s->bn ## _l)) -+ -+uint64_t fman_tgec_get_counter(struct tgec_regs *regs, enum tgec_counters reg_name) -+{ -+ uint64_t ret_val; -+ -+ switch (reg_name) { -+ case E_TGEC_COUNTER_R64: -+ ret_val = GET_TGEC_CNTR_64(r64); -+ break; -+ case E_TGEC_COUNTER_R127: -+ ret_val = GET_TGEC_CNTR_64(r127); -+ break; -+ case E_TGEC_COUNTER_R255: -+ ret_val = GET_TGEC_CNTR_64(r255); -+ break; -+ case E_TGEC_COUNTER_R511: -+ ret_val = GET_TGEC_CNTR_64(r511); -+ break; -+ case E_TGEC_COUNTER_R1023: -+ ret_val = GET_TGEC_CNTR_64(r1023); -+ break; -+ case E_TGEC_COUNTER_R1518: -+ ret_val = GET_TGEC_CNTR_64(r1518); -+ break; -+ case E_TGEC_COUNTER_R1519X: -+ ret_val = GET_TGEC_CNTR_64(r1519x); -+ break; -+ case E_TGEC_COUNTER_TRFRG: -+ ret_val = GET_TGEC_CNTR_64(trfrg); -+ break; -+ case E_TGEC_COUNTER_TRJBR: -+ ret_val = GET_TGEC_CNTR_64(trjbr); -+ break; -+ case E_TGEC_COUNTER_RDRP: -+ ret_val = GET_TGEC_CNTR_64(rdrp); -+ break; -+ case E_TGEC_COUNTER_RALN: -+ ret_val = GET_TGEC_CNTR_64(raln); -+ break; -+ case E_TGEC_COUNTER_TRUND: -+ ret_val = GET_TGEC_CNTR_64(trund); -+ break; -+ case E_TGEC_COUNTER_TROVR: -+ ret_val = GET_TGEC_CNTR_64(trovr); -+ break; -+ case E_TGEC_COUNTER_RXPF: -+ ret_val = GET_TGEC_CNTR_64(rxpf); -+ break; -+ case E_TGEC_COUNTER_TXPF: -+ ret_val = GET_TGEC_CNTR_64(txpf); -+ break; -+ case E_TGEC_COUNTER_ROCT: -+ ret_val = GET_TGEC_CNTR_64(roct); -+ break; -+ case E_TGEC_COUNTER_RMCA: -+ ret_val = GET_TGEC_CNTR_64(rmca); -+ break; -+ case E_TGEC_COUNTER_RBCA: -+ ret_val = GET_TGEC_CNTR_64(rbca); -+ break; -+ case E_TGEC_COUNTER_RPKT: -+ ret_val = GET_TGEC_CNTR_64(rpkt); -+ break; -+ case E_TGEC_COUNTER_RUCA: -+ ret_val = GET_TGEC_CNTR_64(ruca); -+ break; -+ case E_TGEC_COUNTER_RERR: -+ ret_val = GET_TGEC_CNTR_64(rerr); -+ break; -+ case E_TGEC_COUNTER_TOCT: -+ ret_val = GET_TGEC_CNTR_64(toct); -+ break; -+ case E_TGEC_COUNTER_TMCA: -+ ret_val = GET_TGEC_CNTR_64(tmca); -+ break; -+ case E_TGEC_COUNTER_TBCA: -+ ret_val = GET_TGEC_CNTR_64(tbca); -+ break; -+ case E_TGEC_COUNTER_TUCA: -+ ret_val = GET_TGEC_CNTR_64(tuca); -+ break; -+ case E_TGEC_COUNTER_TERR: -+ ret_val = GET_TGEC_CNTR_64(terr); -+ break; -+ default: -+ ret_val = 0; -+ } -+ -+ return ret_val; -+} -+ -+void fman_tgec_enable(struct tgec_regs *regs, bool apply_rx, bool apply_tx) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->command_config); -+ if (apply_rx) -+ tmp |= CMD_CFG_RX_EN; -+ if (apply_tx) -+ tmp |= CMD_CFG_TX_EN; -+ iowrite32be(tmp, ®s->command_config); -+} -+ -+void fman_tgec_disable(struct tgec_regs *regs, bool apply_rx, bool apply_tx) -+{ -+ uint32_t tmp_reg_32; -+ -+ tmp_reg_32 = ioread32be(®s->command_config); -+ if (apply_rx) -+ tmp_reg_32 &= ~CMD_CFG_RX_EN; -+ if (apply_tx) -+ tmp_reg_32 &= ~CMD_CFG_TX_EN; -+ iowrite32be(tmp_reg_32, ®s->command_config); -+} -+ -+void fman_tgec_set_promiscuous(struct tgec_regs *regs, bool val) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->command_config); -+ if (val) -+ tmp |= CMD_CFG_PROMIS_EN; -+ else -+ tmp &= ~CMD_CFG_PROMIS_EN; -+ iowrite32be(tmp, ®s->command_config); -+} -+ -+void fman_tgec_reset_filter_table(struct tgec_regs *regs) -+{ -+ uint32_t i; -+ for (i = 0; i < 512; i++) -+ iowrite32be(i & ~TGEC_HASH_MCAST_EN, ®s->hashtable_ctrl); -+} -+ -+void fman_tgec_set_hash_table_entry(struct tgec_regs *regs, uint32_t crc) -+{ -+ uint32_t hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK; /* Take 9 MSB bits */ -+ iowrite32be(hash | TGEC_HASH_MCAST_EN, ®s->hashtable_ctrl); -+} -+ -+void fman_tgec_set_hash_table(struct tgec_regs *regs, uint32_t value) -+{ -+ iowrite32be(value, ®s->hashtable_ctrl); -+} -+ -+void fman_tgec_set_tx_pause_frames(struct tgec_regs *regs, uint16_t pause_time) -+{ -+ iowrite32be((uint32_t)pause_time, ®s->pause_quant); -+} -+ -+void fman_tgec_set_rx_ignore_pause_frames(struct tgec_regs *regs, bool en) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->command_config); -+ if (en) -+ tmp |= CMD_CFG_PAUSE_IGNORE; -+ else -+ tmp &= ~CMD_CFG_PAUSE_IGNORE; -+ iowrite32be(tmp, ®s->command_config); -+} -+ -+void fman_tgec_enable_1588_time_stamp(struct tgec_regs *regs, bool en) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->command_config); -+ if (en) -+ tmp |= CMD_CFG_EN_TIMESTAMP; -+ else -+ tmp &= ~CMD_CFG_EN_TIMESTAMP; -+ iowrite32be(tmp, ®s->command_config); -+} -+ -+uint32_t fman_tgec_get_event(struct tgec_regs *regs, uint32_t ev_mask) -+{ -+ return ioread32be(®s->ievent) & ev_mask; -+} -+ -+void fman_tgec_ack_event(struct tgec_regs *regs, uint32_t ev_mask) -+{ -+ iowrite32be(ev_mask, ®s->ievent); -+} -+ -+uint32_t fman_tgec_get_interrupt_mask(struct tgec_regs *regs) -+{ -+ return ioread32be(®s->imask); -+} -+ -+void fman_tgec_add_addr_in_paddr(struct tgec_regs *regs, uint8_t *adr) -+{ -+ uint32_t tmp0, tmp1; -+ -+ tmp0 = (uint32_t)(adr[0] | -+ adr[1] << 8 | -+ adr[2] << 16 | -+ adr[3] << 24); -+ tmp1 = (uint32_t)(adr[4] | adr[5] << 8); -+ iowrite32be(tmp0, ®s->mac_addr_2); -+ iowrite32be(tmp1, ®s->mac_addr_3); -+} -+ -+void fman_tgec_clear_addr_in_paddr(struct tgec_regs *regs) -+{ -+ iowrite32be(0, ®s->mac_addr_2); -+ iowrite32be(0, ®s->mac_addr_3); -+} -+ -+uint32_t fman_tgec_get_revision(struct tgec_regs *regs) -+{ -+ return ioread32be(®s->tgec_id); -+} -+ -+void fman_tgec_enable_interrupt(struct tgec_regs *regs, uint32_t ev_mask) -+{ -+ iowrite32be(ioread32be(®s->imask) | ev_mask, ®s->imask); -+} -+ -+void fman_tgec_disable_interrupt(struct tgec_regs *regs, uint32_t ev_mask) -+{ -+ iowrite32be(ioread32be(®s->imask) & ~ev_mask, ®s->imask); -+} -+ -+uint16_t fman_tgec_get_max_frame_len(struct tgec_regs *regs) -+{ -+ return (uint16_t) ioread32be(®s->maxfrm); -+} -+ -+void fman_tgec_defconfig(struct tgec_cfg *cfg) -+{ -+ cfg->wan_mode_enable = DEFAULT_WAN_MODE_ENABLE; -+ cfg->promiscuous_mode_enable = DEFAULT_PROMISCUOUS_MODE_ENABLE; -+ cfg->pause_forward_enable = DEFAULT_PAUSE_FORWARD_ENABLE; -+ cfg->pause_ignore = DEFAULT_PAUSE_IGNORE; -+ cfg->tx_addr_ins_enable = DEFAULT_TX_ADDR_INS_ENABLE; -+ cfg->loopback_enable = DEFAULT_LOOPBACK_ENABLE; -+ cfg->cmd_frame_enable = DEFAULT_CMD_FRAME_ENABLE; -+ cfg->rx_error_discard = DEFAULT_RX_ERROR_DISCARD; -+ cfg->send_idle_enable = DEFAULT_SEND_IDLE_ENABLE; -+ cfg->no_length_check_enable = DEFAULT_NO_LENGTH_CHECK_ENABLE; -+ cfg->lgth_check_nostdr = DEFAULT_LGTH_CHECK_NOSTDR; -+ cfg->time_stamp_enable = DEFAULT_TIME_STAMP_ENABLE; -+ cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH; -+ cfg->max_frame_length = DEFAULT_MAX_FRAME_LENGTH; -+ cfg->pause_quant = DEFAULT_PAUSE_QUANT; -+#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -+ cfg->skip_fman11_workaround = FALSE; -+#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ -+} -+ -+int fman_tgec_init(struct tgec_regs *regs, struct tgec_cfg *cfg, -+ uint32_t exception_mask) -+{ -+ uint32_t tmp; -+ -+ /* Config */ -+ tmp = 0x40; /* CRC forward */ -+ if (cfg->wan_mode_enable) -+ tmp |= CMD_CFG_WAN_MODE; -+ if (cfg->promiscuous_mode_enable) -+ tmp |= CMD_CFG_PROMIS_EN; -+ if (cfg->pause_forward_enable) -+ tmp |= CMD_CFG_PAUSE_FWD; -+ if (cfg->pause_ignore) -+ tmp |= CMD_CFG_PAUSE_IGNORE; -+ if (cfg->tx_addr_ins_enable) -+ tmp |= CMD_CFG_TX_ADDR_INS; -+ if (cfg->loopback_enable) -+ tmp |= CMD_CFG_LOOPBACK_EN; -+ if (cfg->cmd_frame_enable) -+ tmp |= CMD_CFG_CMD_FRM_EN; -+ if (cfg->rx_error_discard) -+ tmp |= CMD_CFG_RX_ER_DISC; -+ if (cfg->send_idle_enable) -+ tmp |= CMD_CFG_SEND_IDLE; -+ if (cfg->no_length_check_enable) -+ tmp |= CMD_CFG_NO_LEN_CHK; -+ if (cfg->time_stamp_enable) -+ tmp |= CMD_CFG_EN_TIMESTAMP; -+ iowrite32be(tmp, ®s->command_config); -+ -+ /* Max Frame Length */ -+ iowrite32be((uint32_t)cfg->max_frame_length, ®s->maxfrm); -+ /* Pause Time */ -+ iowrite32be(cfg->pause_quant, ®s->pause_quant); -+ -+ /* clear all pending events and set-up interrupts */ -+ fman_tgec_ack_event(regs, 0xffffffff); -+ fman_tgec_enable_interrupt(regs, exception_mask); -+ -+ return 0; -+} -+ -+void fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(struct tgec_regs *regs) -+{ -+ uint32_t tmp; -+ -+ /* restore the default tx ipg Length */ -+ tmp = (ioread32be(®s->tx_ipg_len) & ~TGEC_TX_IPG_LENGTH_MASK) | 12; -+ -+ iowrite32be(tmp, ®s->tx_ipg_len); -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c -@@ -0,0 +1,1088 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File memac.c -+ -+ @Description FM mEMAC driver -+*//***************************************************************************/ -+ -+#include "std_ext.h" -+#include "string_ext.h" -+#include "error_ext.h" -+#include "xx_ext.h" -+#include "endian_ext.h" -+#include "debug_ext.h" -+ -+#include "fm_common.h" -+#include "memac.h" -+ -+ -+/*****************************************************************************/ -+/* Internal routines */ -+/*****************************************************************************/ -+ -+/* ......................................................................... */ -+ -+static uint32_t GetMacAddrHashCode(uint64_t ethAddr) -+{ -+ uint64_t mask1, mask2; -+ uint32_t xorVal = 0; -+ uint8_t i, j; -+ -+ for (i=0; i<6; i++) -+ { -+ mask1 = ethAddr & (uint64_t)0x01; -+ ethAddr >>= 1; -+ -+ for (j=0; j<7; j++) -+ { -+ mask2 = ethAddr & (uint64_t)0x01; -+ mask1 ^= mask2; -+ ethAddr >>= 1; -+ } -+ -+ xorVal |= (mask1 << (5-i)); -+ } -+ -+ return xorVal; -+} -+ -+/* ......................................................................... */ -+ -+static void SetupSgmiiInternalPhy(t_Memac *p_Memac, uint8_t phyAddr) -+{ -+ uint16_t tmpReg16; -+ e_EnetMode enetMode; -+ -+ /* In case the higher MACs are used (i.e. the MACs that should support 10G), -+ speed=10000 is provided for SGMII ports. Temporary modify enet mode -+ to 1G one, so MII functions can work correctly. */ -+ enetMode = p_Memac->enetMode; -+ -+ /* SGMII mode + AN enable */ -+ tmpReg16 = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII; -+ if ((p_Memac->enetMode) == e_ENET_MODE_SGMII_2500) -+ tmpReg16 = PHY_SGMII_CR_PHY_RESET | PHY_SGMII_IF_SPEED_GIGABIT | PHY_SGMII_IF_MODE_SGMII; -+ -+ p_Memac->enetMode = MAKE_ENET_MODE(ENET_INTERFACE_FROM_MODE(p_Memac->enetMode), e_ENET_SPEED_1000); -+ MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x14, tmpReg16); -+ -+ /* Device ability according to SGMII specification */ -+ tmpReg16 = PHY_SGMII_DEV_ABILITY_SGMII; -+ MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x4, tmpReg16); -+ -+ /* Adjust link timer for SGMII - -+ According to Cisco SGMII specification the timer should be 1.6 ms. -+ The link_timer register is configured in units of the clock. -+ - When running as 1G SGMII, Serdes clock is 125 MHz, so -+ unit = 1 / (125*10^6 Hz) = 8 ns. -+ 1.6 ms in units of 8 ns = 1.6ms / 8ns = 2 * 10^5 = 0x30d40 -+ - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so -+ unit = 1 / (312.5*10^6 Hz) = 3.2 ns. -+ 1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120. -+ Since link_timer value of 1G SGMII will be too short for 2.5 SGMII, -+ we always set up here a value of 2.5 SGMII. */ -+ MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x13, 0x0007); -+ MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x12, 0xa120); -+ -+ /* Restart AN */ -+ tmpReg16 = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN; -+ MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x0, tmpReg16); -+ -+ /* Restore original enet mode */ -+ p_Memac->enetMode = enetMode; -+} -+ -+/* ......................................................................... */ -+ -+static void SetupSgmiiInternalPhyBaseX(t_Memac *p_Memac, uint8_t phyAddr) -+{ -+ uint16_t tmpReg16; -+ e_EnetMode enetMode; -+ -+ /* In case the higher MACs are used (i.e. the MACs that should support 10G), -+ speed=10000 is provided for SGMII ports. Temporary modify enet mode -+ to 1G one, so MII functions can work correctly. */ -+ enetMode = p_Memac->enetMode; -+ p_Memac->enetMode = MAKE_ENET_MODE(ENET_INTERFACE_FROM_MODE(p_Memac->enetMode), e_ENET_SPEED_1000); -+ -+ /* 1000BaseX mode */ -+ tmpReg16 = PHY_SGMII_IF_MODE_1000X; -+ MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x14, tmpReg16); -+ -+ /* AN Device capability */ -+ tmpReg16 = PHY_SGMII_DEV_ABILITY_1000X; -+ MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x4, tmpReg16); -+ -+ /* Adjust link timer for SGMII - -+ For Serdes 1000BaseX auto-negotiation the timer should be 10 ms. -+ The link_timer register is configured in units of the clock. -+ - When running as 1G SGMII, Serdes clock is 125 MHz, so -+ unit = 1 / (125*10^6 Hz) = 8 ns. -+ 10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0 -+ - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so -+ unit = 1 / (312.5*10^6 Hz) = 3.2 ns. -+ 10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08. -+ Since link_timer value of 1G SGMII will be too short for 2.5 SGMII, -+ we always set up here a value of 2.5 SGMII. */ -+ MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x13, 0x002f); -+ MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x12, 0xaf08); -+ -+ /* Restart AN */ -+ tmpReg16 = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN; -+ MEMAC_MII_WritePhyReg(p_Memac, phyAddr, 0x0, tmpReg16); -+ -+ /* Restore original enet mode */ -+ p_Memac->enetMode = enetMode; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error CheckInitParameters(t_Memac *p_Memac) -+{ -+ e_FmMacType portType; -+ -+ portType = ((ENET_SPEED_FROM_MODE(p_Memac->enetMode) < e_ENET_SPEED_10000) ? e_FM_MAC_1G : e_FM_MAC_10G); -+ -+#if (FM_MAX_NUM_OF_10G_MACS > 0) -+ if ((portType == e_FM_MAC_10G) && (p_Memac->macId >= FM_MAX_NUM_OF_10G_MACS)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("10G MAC ID must be less than %d", FM_MAX_NUM_OF_10G_MACS)); -+#endif /* (FM_MAX_NUM_OF_10G_MACS > 0) */ -+ -+ if ((portType == e_FM_MAC_1G) && (p_Memac->macId >= FM_MAX_NUM_OF_1G_MACS)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("1G MAC ID must be less than %d", FM_MAX_NUM_OF_1G_MACS)); -+ if (p_Memac->addr == 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet MAC must have a valid MAC address")); -+ if (!p_Memac->f_Exception) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Uninitialized f_Exception")); -+ if (!p_Memac->f_Event) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Uninitialized f_Event")); -+#ifdef FM_LEN_CHECK_ERRATA_FMAN_SW002 -+ if (!p_Memac->p_MemacDriverParam->no_length_check_enable) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("LengthCheck!")); -+#endif /* FM_LEN_CHECK_ERRATA_FMAN_SW002 */ -+ -+ return E_OK; -+} -+ -+/* ........................................................................... */ -+ -+static void MemacErrException(t_Handle h_Memac) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ uint32_t event, imask; -+ -+ event = fman_memac_get_event(p_Memac->p_MemMap, 0xffffffff); -+ imask = fman_memac_get_interrupt_mask(p_Memac->p_MemMap); -+ -+ /* Imask include both error and notification/event bits. -+ Leaving only error bits enabled by imask. -+ The imask error bits are shifted by 16 bits offset from -+ their corresponding location in the ievent - hence the >> 16 */ -+ event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16); -+ -+ fman_memac_ack_event(p_Memac->p_MemMap, event); -+ -+ if (event & MEMAC_IEVNT_TS_ECC_ER) -+ p_Memac->f_Exception(p_Memac->h_App, e_FM_MAC_EX_TS_FIFO_ECC_ERR); -+ if (event & MEMAC_IEVNT_TX_ECC_ER) -+ p_Memac->f_Exception(p_Memac->h_App, e_FM_MAC_EX_10G_1TX_ECC_ER); -+ if (event & MEMAC_IEVNT_RX_ECC_ER) -+ p_Memac->f_Exception(p_Memac->h_App, e_FM_MAC_EX_10G_RX_ECC_ER); -+} -+ -+static void MemacException(t_Handle h_Memac) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ uint32_t event, imask; -+ -+ event = fman_memac_get_event(p_Memac->p_MemMap, 0xffffffff); -+ imask = fman_memac_get_interrupt_mask(p_Memac->p_MemMap); -+ -+ /* Imask include both error and notification/event bits. -+ Leaving only error bits enabled by imask. -+ The imask error bits are shifted by 16 bits offset from -+ their corresponding location in the ievent - hence the >> 16 */ -+ event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16); -+ -+ fman_memac_ack_event(p_Memac->p_MemMap, event); -+ -+ if (event & MEMAC_IEVNT_MGI) -+ p_Memac->f_Exception(p_Memac->h_App, e_FM_MAC_EX_MAGIC_PACKET_INDICATION); -+} -+ -+/* ......................................................................... */ -+ -+static void FreeInitResources(t_Memac *p_Memac) -+{ -+ e_FmMacType portType; -+ -+ portType = -+ ((ENET_SPEED_FROM_MODE(p_Memac->enetMode) < e_ENET_SPEED_10000) ? e_FM_MAC_1G : e_FM_MAC_10G); -+ -+ if (portType == e_FM_MAC_10G) -+ FmUnregisterIntr(p_Memac->fmMacControllerDriver.h_Fm, e_FM_MOD_10G_MAC, p_Memac->macId, e_FM_INTR_TYPE_ERR); -+ else -+ FmUnregisterIntr(p_Memac->fmMacControllerDriver.h_Fm, e_FM_MOD_1G_MAC, p_Memac->macId, e_FM_INTR_TYPE_ERR); -+ -+ /* release the driver's group hash table */ -+ FreeHashTable(p_Memac->p_MulticastAddrHash); -+ p_Memac->p_MulticastAddrHash = NULL; -+ -+ /* release the driver's individual hash table */ -+ FreeHashTable(p_Memac->p_UnicastAddrHash); -+ p_Memac->p_UnicastAddrHash = NULL; -+} -+ -+ -+/*****************************************************************************/ -+/* mEMAC API routines */ -+/*****************************************************************************/ -+ -+/* ......................................................................... */ -+ -+static t_Error MemacEnable(t_Handle h_Memac, e_CommMode mode) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ fman_memac_enable(p_Memac->p_MemMap, (mode & e_COMM_MODE_RX), (mode & e_COMM_MODE_TX)); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacDisable (t_Handle h_Memac, e_CommMode mode) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ fman_memac_disable(p_Memac->p_MemMap, (mode & e_COMM_MODE_RX), (mode & e_COMM_MODE_TX)); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacSetPromiscuous(t_Handle h_Memac, bool newVal) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ fman_memac_set_promiscuous(p_Memac->p_MemMap, newVal); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error MemacAdjustLink(t_Handle h_Memac, e_EnetSpeed speed, bool fullDuplex) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ if ((speed >= e_ENET_SPEED_1000) && (!fullDuplex)) -+ RETURN_ERROR(MAJOR, E_CONFLICT, -+ ("Ethernet MAC 1G or 10G does not support half-duplex")); -+ -+ fman_memac_adjust_link(p_Memac->p_MemMap, -+ (enum enet_interface)ENET_INTERFACE_FROM_MODE(p_Memac->enetMode), -+ (enum enet_speed)speed, -+ fullDuplex); -+ return E_OK; -+} -+ -+ -+/*****************************************************************************/ -+/* Memac Configs modification functions */ -+/*****************************************************************************/ -+ -+/* ......................................................................... */ -+ -+static t_Error MemacConfigLoopback(t_Handle h_Memac, bool newVal) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ p_Memac->p_MemacDriverParam->loopback_enable = newVal; -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacConfigWan(t_Handle h_Memac, bool newVal) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ p_Memac->p_MemacDriverParam->wan_mode_enable = newVal; -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacConfigMaxFrameLength(t_Handle h_Memac, uint16_t newVal) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ p_Memac->p_MemacDriverParam->max_frame_length = newVal; -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacConfigPad(t_Handle h_Memac, bool newVal) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ p_Memac->p_MemacDriverParam->pad_enable = newVal; -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacConfigLengthCheck(t_Handle h_Memac, bool newVal) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ p_Memac->p_MemacDriverParam->no_length_check_enable = !newVal; -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacConfigException(t_Handle h_Memac, e_FmMacExceptions exception, bool enable) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ uint32_t bitMask = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ GET_EXCEPTION_FLAG(bitMask, exception); -+ if (bitMask) -+ { -+ if (enable) -+ p_Memac->exceptions |= bitMask; -+ else -+ p_Memac->exceptions &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacConfigResetOnInit(t_Handle h_Memac, bool enable) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ p_Memac->p_MemacDriverParam->reset_on_init = enable; -+ -+ return E_OK; -+} -+ -+ -+/*****************************************************************************/ -+/* Memac Run Time API functions */ -+/*****************************************************************************/ -+ -+/* ......................................................................... */ -+ -+static t_Error MemacSetTxPauseFrames(t_Handle h_Memac, -+ uint8_t priority, -+ uint16_t pauseTime, -+ uint16_t threshTime) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ if (priority != 0xFF) -+ { -+ bool PortConfigured, PreFetchEnabled; -+ -+ if (FmGetTnumAgingPeriod(p_Memac->fmMacControllerDriver.h_Fm) == 0) -+ RETURN_ERROR(MAJOR, E_CONFLICT, ("For PFC operation, TNUM aging must be enabled")); -+ -+ FmGetPortPreFetchConfiguration(p_Memac->fmMacControllerDriver.h_Fm, -+ p_Memac->fmMacControllerDriver.macId, -+ &PortConfigured, -+ &PreFetchEnabled); -+ -+ if ((ENET_SPEED_FROM_MODE(p_Memac->fmMacControllerDriver.enetMode) == e_ENET_SPEED_1000) && !PortConfigured) -+ DBG(INFO, ("For PFC correct operation, prefetch must be configured on the FM Tx PORT")); -+ -+ if ((ENET_SPEED_FROM_MODE(p_Memac->fmMacControllerDriver.enetMode) == e_ENET_SPEED_1000) && PortConfigured && !PreFetchEnabled) -+ DBG(WARNING, ("For PFC correct operation, prefetch must be configured on the FM Tx PORT")); -+ } -+ -+ fman_memac_set_tx_pause_frames(p_Memac->p_MemMap, priority, pauseTime, threshTime); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacSetTxAutoPauseFrames(t_Handle h_Memac, -+ uint16_t pauseTime) -+{ -+ return MemacSetTxPauseFrames(h_Memac, FM_MAC_NO_PFC, pauseTime, 0); -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacSetRxIgnorePauseFrames(t_Handle h_Memac, bool en) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ fman_memac_set_rx_ignore_pause_frames(p_Memac->p_MemMap, en); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacSetWakeOnLan(t_Handle h_Memac, bool en) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ fman_memac_set_wol(p_Memac->p_MemMap, en); -+ -+ return E_OK; -+} -+ -+/* .............................................................................. */ -+ -+static t_Error MemacEnable1588TimeStamp(t_Handle h_Memac) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+UNUSED(p_Memac); -+DBG(WARNING, ("mEMAC has 1588 always enabled!")); -+ -+ return E_OK; -+} -+ -+/* Counters handling */ -+/* ......................................................................... */ -+ -+static t_Error MemacGetStatistics(t_Handle h_Memac, t_FmMacStatistics *p_Statistics) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_Statistics, E_NULL_POINTER); -+ -+ p_Statistics->eStatPkts64 = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R64); -+ p_Statistics->eStatPkts65to127 = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R127); -+ p_Statistics->eStatPkts128to255 = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R255); -+ p_Statistics->eStatPkts256to511 = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R511); -+ p_Statistics->eStatPkts512to1023 = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R1023); -+ p_Statistics->eStatPkts1024to1518 = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R1518); -+ p_Statistics->eStatPkts1519to1522 = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_R1519X); -+/* */ -+ p_Statistics->eStatFragments = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RFRG); -+ p_Statistics->eStatJabbers = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RJBR); -+ -+ p_Statistics->eStatsDropEvents = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RDRP); -+ p_Statistics->eStatCRCAlignErrors = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RALN); -+ -+ p_Statistics->eStatUndersizePkts = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_TUND); -+ p_Statistics->eStatOversizePkts = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_ROVR); -+/* Pause */ -+ p_Statistics->reStatPause = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RXPF); -+ p_Statistics->teStatPause = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_TXPF); -+ -+/* MIB II */ -+ p_Statistics->ifInOctets = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_ROCT); -+ p_Statistics->ifInUcastPkts = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RUCA); -+ p_Statistics->ifInMcastPkts = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RMCA); -+ p_Statistics->ifInBcastPkts = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RBCA); -+ p_Statistics->ifInPkts = p_Statistics->ifInUcastPkts -+ + p_Statistics->ifInMcastPkts -+ + p_Statistics->ifInBcastPkts; -+ p_Statistics->ifInDiscards = 0; -+ p_Statistics->ifInErrors = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_RERR); -+ -+ p_Statistics->ifOutOctets = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_TOCT); -+ p_Statistics->ifOutUcastPkts = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_TUCA); -+ p_Statistics->ifOutMcastPkts = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_TMCA); -+ p_Statistics->ifOutBcastPkts = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_TBCA); -+ p_Statistics->ifOutPkts = p_Statistics->ifOutUcastPkts -+ + p_Statistics->ifOutMcastPkts -+ + p_Statistics->ifOutBcastPkts; -+ p_Statistics->ifOutDiscards = 0; -+ p_Statistics->ifOutErrors = fman_memac_get_counter(p_Memac->p_MemMap, E_MEMAC_COUNTER_TERR); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacModifyMacAddress (t_Handle h_Memac, t_EnetAddr *p_EnetAddr) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ fman_memac_add_addr_in_paddr(p_Memac->p_MemMap, (uint8_t *)(*p_EnetAddr), 0); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacResetCounters (t_Handle h_Memac) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ fman_memac_reset_stat(p_Memac->p_MemMap); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacAddExactMatchMacAddress(t_Handle h_Memac, t_EnetAddr *p_EthAddr) -+{ -+ t_Memac *p_Memac = (t_Memac *) h_Memac; -+ uint64_t ethAddr; -+ uint8_t paddrNum; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr); -+ -+ if (ethAddr & GROUP_ADDRESS) -+ /* Multicast address has no effect in PADDR */ -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Multicast address")); -+ -+ /* Make sure no PADDR contains this address */ -+ for (paddrNum = 0; paddrNum < MEMAC_NUM_OF_PADDRS; paddrNum++) -+ if (p_Memac->indAddrRegUsed[paddrNum]) -+ if (p_Memac->paddr[paddrNum] == ethAddr) -+ RETURN_ERROR(MAJOR, E_ALREADY_EXISTS, NO_MSG); -+ -+ /* Find first unused PADDR */ -+ for (paddrNum = 0; paddrNum < MEMAC_NUM_OF_PADDRS; paddrNum++) -+ if (!(p_Memac->indAddrRegUsed[paddrNum])) -+ { -+ /* mark this PADDR as used */ -+ p_Memac->indAddrRegUsed[paddrNum] = TRUE; -+ /* store address */ -+ p_Memac->paddr[paddrNum] = ethAddr; -+ -+ /* put in hardware */ -+ fman_memac_add_addr_in_paddr(p_Memac->p_MemMap, (uint8_t*)(*p_EthAddr), paddrNum); -+ p_Memac->numOfIndAddrInRegs++; -+ -+ return E_OK; -+ } -+ -+ /* No free PADDR */ -+ RETURN_ERROR(MAJOR, E_FULL, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacDelExactMatchMacAddress(t_Handle h_Memac, t_EnetAddr *p_EthAddr) -+{ -+ t_Memac *p_Memac = (t_Memac *) h_Memac; -+ uint64_t ethAddr; -+ uint8_t paddrNum; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr); -+ -+ /* Find used PADDR containing this address */ -+ for (paddrNum = 0; paddrNum < MEMAC_NUM_OF_PADDRS; paddrNum++) -+ { -+ if ((p_Memac->indAddrRegUsed[paddrNum]) && -+ (p_Memac->paddr[paddrNum] == ethAddr)) -+ { -+ /* mark this PADDR as not used */ -+ p_Memac->indAddrRegUsed[paddrNum] = FALSE; -+ /* clear in hardware */ -+ fman_memac_clear_addr_in_paddr(p_Memac->p_MemMap, paddrNum); -+ p_Memac->numOfIndAddrInRegs--; -+ -+ return E_OK; -+ } -+ } -+ -+ RETURN_ERROR(MAJOR, E_NOT_FOUND, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacGetId(t_Handle h_Memac, uint32_t *macId) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ *macId = p_Memac->macId; -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+ -+static t_Error MemacAddHashMacAddress(t_Handle h_Memac, t_EnetAddr *p_EthAddr) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ t_EthHashEntry *p_HashEntry; -+ uint32_t hash; -+ uint64_t ethAddr; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr); -+ -+ if (!(ethAddr & GROUP_ADDRESS)) -+ /* Unicast addresses not supported in hash */ -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Unicast Address")); -+ -+ hash = GetMacAddrHashCode(ethAddr) & HASH_CTRL_ADDR_MASK; -+ -+ /* Create element to be added to the driver hash table */ -+ p_HashEntry = (t_EthHashEntry *)XX_Malloc(sizeof(t_EthHashEntry)); -+ p_HashEntry->addr = ethAddr; -+ INIT_LIST(&p_HashEntry->node); -+ -+ LIST_AddToTail(&(p_HashEntry->node), &(p_Memac->p_MulticastAddrHash->p_Lsts[hash])); -+ fman_memac_set_hash_table(p_Memac->p_MemMap, (hash | HASH_CTRL_MCAST_EN)); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacDelHashMacAddress(t_Handle h_Memac, t_EnetAddr *p_EthAddr) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ t_EthHashEntry *p_HashEntry = NULL; -+ t_List *p_Pos; -+ uint32_t hash; -+ uint64_t ethAddr; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr); -+ -+ hash = GetMacAddrHashCode(ethAddr) & HASH_CTRL_ADDR_MASK; -+ -+ LIST_FOR_EACH(p_Pos, &(p_Memac->p_MulticastAddrHash->p_Lsts[hash])) -+ { -+ p_HashEntry = ETH_HASH_ENTRY_OBJ(p_Pos); -+ if (p_HashEntry->addr == ethAddr) -+ { -+ LIST_DelAndInit(&p_HashEntry->node); -+ XX_Free(p_HashEntry); -+ break; -+ } -+ } -+ if (LIST_IsEmpty(&p_Memac->p_MulticastAddrHash->p_Lsts[hash])) -+ fman_memac_set_hash_table(p_Memac->p_MemMap, (hash & ~HASH_CTRL_MCAST_EN)); -+ -+ return E_OK; -+} -+ -+ -+/* ......................................................................... */ -+ -+static t_Error MemacSetException(t_Handle h_Memac, e_FmMacExceptions exception, bool enable) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ uint32_t bitMask = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ -+ GET_EXCEPTION_FLAG(bitMask, exception); -+ if (bitMask) -+ { -+ if (enable) -+ p_Memac->exceptions |= bitMask; -+ else -+ p_Memac->exceptions &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); -+ -+ fman_memac_set_exception(p_Memac->p_MemMap, bitMask, enable); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static uint16_t MemacGetMaxFrameLength(t_Handle h_Memac) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_VALUE(p_Memac, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_VALUE(!p_Memac->p_MemacDriverParam, E_INVALID_STATE, 0); -+ -+ return fman_memac_get_max_frame_len(p_Memac->p_MemMap); -+} -+ -+ -+/*****************************************************************************/ -+/* mEMAC Init & Free API */ -+/*****************************************************************************/ -+ -+/* ......................................................................... */ -+void *g_MemacRegs; -+static t_Error MemacInit(t_Handle h_Memac) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ struct memac_cfg *p_MemacDriverParam; -+ enum enet_interface enet_interface; -+ enum enet_speed enet_speed; -+ uint8_t i, phyAddr; -+ t_EnetAddr ethAddr; -+ e_FmMacType portType; -+ t_Error err; -+ bool slow_10g_if = FALSE; -+ if (p_Memac->macId == 3) /* This is a quick WA */ -+ g_MemacRegs = p_Memac->p_MemMap; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Memac->p_MemacDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_Memac->fmMacControllerDriver.h_Fm, E_INVALID_HANDLE); -+ -+ FM_GetRevision(p_Memac->fmMacControllerDriver.h_Fm, &p_Memac->fmMacControllerDriver.fmRevInfo); -+ if (p_Memac->fmMacControllerDriver.fmRevInfo.majorRev == 6 && -+ p_Memac->fmMacControllerDriver.fmRevInfo.minorRev == 4) -+ slow_10g_if = TRUE; -+ -+ CHECK_INIT_PARAMETERS(p_Memac, CheckInitParameters); -+ -+ p_MemacDriverParam = p_Memac->p_MemacDriverParam; -+ -+ portType = -+ ((ENET_SPEED_FROM_MODE(p_Memac->enetMode) < e_ENET_SPEED_10000) ? e_FM_MAC_1G : e_FM_MAC_10G); -+ -+ /* First, reset the MAC if desired. */ -+ if (p_MemacDriverParam->reset_on_init) -+ fman_memac_reset(p_Memac->p_MemMap); -+ -+ /* MAC Address */ -+ MAKE_ENET_ADDR_FROM_UINT64(p_Memac->addr, ethAddr); -+ fman_memac_add_addr_in_paddr(p_Memac->p_MemMap, (uint8_t*)ethAddr, 0); -+ -+ enet_interface = (enum enet_interface) ENET_INTERFACE_FROM_MODE(p_Memac->enetMode); -+ enet_speed = (enum enet_speed) ENET_SPEED_FROM_MODE(p_Memac->enetMode); -+ -+ fman_memac_init(p_Memac->p_MemMap, -+ p_Memac->p_MemacDriverParam, -+ enet_interface, -+ enet_speed, -+ slow_10g_if, -+ p_Memac->exceptions); -+ -+#ifdef FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 -+ { -+ uint32_t tmpReg = 0; -+ -+ FM_GetRevision(p_Memac->fmMacControllerDriver.h_Fm, &p_Memac->fmMacControllerDriver.fmRevInfo); -+ /* check the FMAN version - the bug exists only in rev1 */ -+ if ((p_Memac->fmMacControllerDriver.fmRevInfo.majorRev == 6) && -+ (p_Memac->fmMacControllerDriver.fmRevInfo.minorRev == 0)) -+ { -+ /* MAC strips CRC from received frames - this workaround should -+ decrease the likelihood of bug appearance -+ */ -+ tmpReg = GET_UINT32(p_Memac->p_MemMap->command_config); -+ tmpReg &= ~CMD_CFG_CRC_FWD; -+ WRITE_UINT32(p_Memac->p_MemMap->command_config, tmpReg); -+ /* DBG(WARNING, ("mEMAC strips CRC from received frames as part of A006320 errata workaround"));*/ -+ } -+ } -+#endif /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 */ -+ -+ if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_SGMII) -+ { -+ /* Configure internal SGMII PHY */ -+ if (p_Memac->enetMode & ENET_IF_SGMII_BASEX) -+ SetupSgmiiInternalPhyBaseX(p_Memac, PHY_MDIO_ADDR); -+ else -+ SetupSgmiiInternalPhy(p_Memac, PHY_MDIO_ADDR); -+ } -+ else if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_QSGMII) -+ { -+ /* Configure 4 internal SGMII PHYs */ -+ for (i = 0; i < 4; i++) -+ { -+ /* QSGMII PHY address occupies 3 upper bits of 5-bit -+ phyAddress; the lower 2 bits are used to extend -+ register address space and access each one of 4 -+ ports inside QSGMII. */ -+ phyAddr = (uint8_t)((PHY_MDIO_ADDR << 2) | i); -+ if (p_Memac->enetMode & ENET_IF_SGMII_BASEX) -+ SetupSgmiiInternalPhyBaseX(p_Memac, phyAddr); -+ else -+ SetupSgmiiInternalPhy(p_Memac, phyAddr); -+ } -+ } -+ -+ /* Max Frame Length */ -+ err = FmSetMacMaxFrame(p_Memac->fmMacControllerDriver.h_Fm, -+ portType, -+ p_Memac->fmMacControllerDriver.macId, -+ p_MemacDriverParam->max_frame_length); -+ if (err) -+ RETURN_ERROR(MAJOR, err, ("settings Mac max frame length is FAILED")); -+ -+ p_Memac->p_MulticastAddrHash = AllocHashTable(HASH_TABLE_SIZE); -+ if (!p_Memac->p_MulticastAddrHash) -+ { -+ FreeInitResources(p_Memac); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("allocation hash table is FAILED")); -+ } -+ -+ p_Memac->p_UnicastAddrHash = AllocHashTable(HASH_TABLE_SIZE); -+ if (!p_Memac->p_UnicastAddrHash) -+ { -+ FreeInitResources(p_Memac); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("allocation hash table is FAILED")); -+ } -+ -+ FmRegisterIntr(p_Memac->fmMacControllerDriver.h_Fm, -+ (portType == e_FM_MAC_10G) ? e_FM_MOD_10G_MAC : e_FM_MOD_1G_MAC, -+ p_Memac->macId, -+ e_FM_INTR_TYPE_ERR, -+ MemacErrException, -+ p_Memac); -+ -+ FmRegisterIntr(p_Memac->fmMacControllerDriver.h_Fm, -+ (portType == e_FM_MAC_10G) ? e_FM_MOD_10G_MAC : e_FM_MOD_1G_MAC, -+ p_Memac->macId, -+ e_FM_INTR_TYPE_NORMAL, -+ MemacException, -+ p_Memac); -+ -+ XX_Free(p_MemacDriverParam); -+ p_Memac->p_MemacDriverParam = NULL; -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error MemacFree(t_Handle h_Memac) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ -+ if (p_Memac->p_MemacDriverParam) -+ { -+ /* Called after config */ -+ XX_Free(p_Memac->p_MemacDriverParam); -+ p_Memac->p_MemacDriverParam = NULL; -+ } -+ else -+ /* Called after init */ -+ FreeInitResources(p_Memac); -+ -+ XX_Free(p_Memac); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static void InitFmMacControllerDriver(t_FmMacControllerDriver *p_FmMacControllerDriver) -+{ -+ p_FmMacControllerDriver->f_FM_MAC_Init = MemacInit; -+ p_FmMacControllerDriver->f_FM_MAC_Free = MemacFree; -+ -+ p_FmMacControllerDriver->f_FM_MAC_SetStatistics = NULL; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback = MemacConfigLoopback; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength = MemacConfigMaxFrameLength; -+ -+ p_FmMacControllerDriver->f_FM_MAC_ConfigWan = MemacConfigWan; -+ -+ p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc = MemacConfigPad; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex = NULL; /* half-duplex is detected automatically */ -+ p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck = MemacConfigLengthCheck; -+ -+ p_FmMacControllerDriver->f_FM_MAC_ConfigException = MemacConfigException; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit = MemacConfigResetOnInit; -+ -+ p_FmMacControllerDriver->f_FM_MAC_SetException = MemacSetException; -+ -+ p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp = MemacEnable1588TimeStamp; /* always enabled */ -+ p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp = NULL; -+ -+ p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous = MemacSetPromiscuous; -+ p_FmMacControllerDriver->f_FM_MAC_AdjustLink = MemacAdjustLink; -+ p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg = NULL; -+ -+ p_FmMacControllerDriver->f_FM_MAC_Enable = MemacEnable; -+ p_FmMacControllerDriver->f_FM_MAC_Disable = MemacDisable; -+ -+ p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames = MemacSetTxAutoPauseFrames; -+ p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames = MemacSetTxPauseFrames; -+ p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames = MemacSetRxIgnorePauseFrames; -+ -+ p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan = MemacSetWakeOnLan; -+ -+ p_FmMacControllerDriver->f_FM_MAC_ResetCounters = MemacResetCounters; -+ p_FmMacControllerDriver->f_FM_MAC_GetStatistics = MemacGetStatistics; -+ -+ p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr = MemacModifyMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr = MemacAddHashMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr = MemacDelHashMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr = MemacAddExactMatchMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr = MemacDelExactMatchMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_GetId = MemacGetId; -+ p_FmMacControllerDriver->f_FM_MAC_GetVersion = NULL; -+ p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength = MemacGetMaxFrameLength; -+ -+ p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg = MEMAC_MII_WritePhyReg; -+ p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg = MEMAC_MII_ReadPhyReg; -+} -+ -+ -+/*****************************************************************************/ -+/* mEMAC Config Main Entry */ -+/*****************************************************************************/ -+ -+/* ......................................................................... */ -+ -+t_Handle MEMAC_Config(t_FmMacParams *p_FmMacParam) -+{ -+ t_Memac *p_Memac; -+ struct memac_cfg *p_MemacDriverParam; -+ uintptr_t baseAddr; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmMacParam, E_NULL_POINTER, NULL); -+ -+ baseAddr = p_FmMacParam->baseAddr; -+ /* Allocate memory for the mEMAC data structure */ -+ p_Memac = (t_Memac *)XX_Malloc(sizeof(t_Memac)); -+ if (!p_Memac) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("mEMAC driver structure")); -+ return NULL; -+ } -+ memset(p_Memac, 0, sizeof(t_Memac)); -+ InitFmMacControllerDriver(&p_Memac->fmMacControllerDriver); -+ -+ /* Allocate memory for the mEMAC driver parameters data structure */ -+ p_MemacDriverParam = (struct memac_cfg *)XX_Malloc(sizeof(struct memac_cfg)); -+ if (!p_MemacDriverParam) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("mEMAC driver parameters")); -+ XX_Free(p_Memac); -+ return NULL; -+ } -+ memset(p_MemacDriverParam, 0, sizeof(struct memac_cfg)); -+ -+ /* Plant parameter structure pointer */ -+ p_Memac->p_MemacDriverParam = p_MemacDriverParam; -+ -+ fman_memac_defconfig(p_MemacDriverParam); -+ -+ p_Memac->addr = ENET_ADDR_TO_UINT64(p_FmMacParam->addr); -+ -+ p_Memac->p_MemMap = (struct memac_regs *)UINT_TO_PTR(baseAddr); -+ p_Memac->p_MiiMemMap = (struct memac_mii_access_mem_map*)UINT_TO_PTR(baseAddr + MEMAC_TO_MII_OFFSET); -+ -+ p_Memac->enetMode = p_FmMacParam->enetMode; -+ p_Memac->macId = p_FmMacParam->macId; -+ p_Memac->exceptions = MEMAC_default_exceptions; -+ p_Memac->f_Exception = p_FmMacParam->f_Exception; -+ p_Memac->f_Event = p_FmMacParam->f_Event; -+ p_Memac->h_App = p_FmMacParam->h_App; -+ -+ return p_Memac; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.h -@@ -0,0 +1,110 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File memac.h -+ -+ @Description FM Multirate Ethernet MAC (mEMAC) -+*//***************************************************************************/ -+#ifndef __MEMAC_H -+#define __MEMAC_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "list_ext.h" -+ -+#include "fsl_fman_memac_mii_acc.h" -+#include "fm_mac.h" -+#include "fsl_fman_memac.h" -+ -+ -+#define MEMAC_default_exceptions \ -+ ((uint32_t)(MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER | MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI)) -+ -+#define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \ -+ case e_FM_MAC_EX_10G_1TX_ECC_ER: \ -+ bitMask = MEMAC_IMASK_TECC_ER; break; \ -+ case e_FM_MAC_EX_10G_RX_ECC_ER: \ -+ bitMask = MEMAC_IMASK_RECC_ER; break; \ -+ case e_FM_MAC_EX_TS_FIFO_ECC_ERR: \ -+ bitMask = MEMAC_IMASK_TSECC_ER; break; \ -+ case e_FM_MAC_EX_MAGIC_PACKET_INDICATION: \ -+ bitMask = MEMAC_IMASK_MGI; break; \ -+ default: bitMask = 0;break;} -+ -+ -+typedef struct -+{ -+ t_FmMacControllerDriver fmMacControllerDriver; /**< Upper Mac control block */ -+ t_Handle h_App; /**< Handle to the upper layer application */ -+ struct memac_regs *p_MemMap; /**< Pointer to MAC memory mapped registers */ -+ struct memac_mii_access_mem_map *p_MiiMemMap; /**< Pointer to MII memory mapped registers */ -+ uint64_t addr; /**< MAC address of device */ -+ e_EnetMode enetMode; /**< Ethernet physical interface */ -+ t_FmMacExceptionCallback *f_Exception; -+ int mdioIrq; -+ t_FmMacExceptionCallback *f_Event; -+ bool indAddrRegUsed[MEMAC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */ -+ uint64_t paddr[MEMAC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */ -+ uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */ -+ t_EthHash *p_MulticastAddrHash; /**< Pointer to driver's global address hash table */ -+ t_EthHash *p_UnicastAddrHash; /**< Pointer to driver's individual address hash table */ -+ bool debugMode; -+ uint8_t macId; -+ uint32_t exceptions; -+ struct memac_cfg *p_MemacDriverParam; -+} t_Memac; -+ -+ -+/* Internal PHY access */ -+#define PHY_MDIO_ADDR 0 -+ -+/* Internal PHY Registers - SGMII */ -+#define PHY_SGMII_CR_PHY_RESET 0x8000 -+#define PHY_SGMII_CR_RESET_AN 0x0200 -+#define PHY_SGMII_CR_DEF_VAL 0x1140 -+#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001 -+#define PHY_SGMII_DEV_ABILITY_1000X 0x01A0 -+#define PHY_SGMII_IF_SPEED_GIGABIT 0x0008 -+#define PHY_SGMII_IF_MODE_AN 0x0002 -+#define PHY_SGMII_IF_MODE_SGMII 0x0001 -+#define PHY_SGMII_IF_MODE_1000X 0x0000 -+ -+ -+#define MEMAC_TO_MII_OFFSET 0x030 /* Offset from the MEM map to the MDIO mem map */ -+ -+t_Error MEMAC_MII_WritePhyReg(t_Handle h_Memac, uint8_t phyAddr, uint8_t reg, uint16_t data); -+t_Error MEMAC_MII_ReadPhyReg(t_Handle h_Memac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data); -+ -+ -+#endif /* __MEMAC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac_mii_acc.c -@@ -0,0 +1,78 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "fm_mac.h" -+#include "memac.h" -+#include "xx_ext.h" -+ -+#include "fm_common.h" -+#include "memac_mii_acc.h" -+ -+ -+/*****************************************************************************/ -+t_Error MEMAC_MII_WritePhyReg(t_Handle h_Memac, -+ uint8_t phyAddr, -+ uint8_t reg, -+ uint16_t data) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Memac->p_MiiMemMap, E_INVALID_HANDLE); -+ -+ return (t_Error)fman_memac_mii_write_phy_reg(p_Memac->p_MiiMemMap, -+ phyAddr, -+ reg, -+ data, -+ (enum enet_speed)ENET_SPEED_FROM_MODE(p_Memac->enetMode)); -+} -+ -+/*****************************************************************************/ -+t_Error MEMAC_MII_ReadPhyReg(t_Handle h_Memac, -+ uint8_t phyAddr, -+ uint8_t reg, -+ uint16_t *p_Data) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Memac->p_MiiMemMap, E_INVALID_HANDLE); -+ -+ return fman_memac_mii_read_phy_reg(p_Memac->p_MiiMemMap, -+ phyAddr, -+ reg, -+ p_Data, -+ (enum enet_speed)ENET_SPEED_FROM_MODE(p_Memac->enetMode)); -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac_mii_acc.h -@@ -0,0 +1,73 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#ifndef __MEMAC_MII_ACC_H -+#define __MEMAC_MII_ACC_H -+ -+#include "std_ext.h" -+ -+ -+/* MII Management Registers */ -+#define MDIO_CFG_CLK_DIV_MASK 0x0080ff80 -+#define MDIO_CFG_CLK_DIV_SHIFT 7 -+#define MDIO_CFG_HOLD_MASK 0x0000001c -+#define MDIO_CFG_ENC45 0x00000040 -+#define MDIO_CFG_READ_ERR 0x00000002 -+#define MDIO_CFG_BSY 0x00000001 -+ -+#define MDIO_CTL_PHY_ADDR_SHIFT 5 -+#define MDIO_CTL_READ 0x00008000 -+ -+#define MDIO_DATA_BSY 0x80000000 -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+/*----------------------------------------------------*/ -+/* MII Configuration Control Memory Map Registers */ -+/*----------------------------------------------------*/ -+typedef struct t_MemacMiiAccessMemMap -+{ -+ volatile uint32_t mdio_cfg; /* 0x030 */ -+ volatile uint32_t mdio_ctrl; /* 0x034 */ -+ volatile uint32_t mdio_data; /* 0x038 */ -+ volatile uint32_t mdio_addr; /* 0x03c */ -+} t_MemacMiiAccessMemMap ; -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+ -+#endif /* __MEMAC_MII_ACC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.c -@@ -0,0 +1,974 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File tgec.c -+ -+ @Description FM 10G MAC ... -+*//***************************************************************************/ -+ -+#include "std_ext.h" -+#include "string_ext.h" -+#include "error_ext.h" -+#include "xx_ext.h" -+#include "endian_ext.h" -+#include "debug_ext.h" -+#include "crc_mac_addr_ext.h" -+ -+#include "fm_common.h" -+#include "fsl_fman_tgec.h" -+#include "tgec.h" -+ -+ -+/*****************************************************************************/ -+/* Internal routines */ -+/*****************************************************************************/ -+ -+static t_Error CheckInitParameters(t_Tgec *p_Tgec) -+{ -+ if (ENET_SPEED_FROM_MODE(p_Tgec->enetMode) < e_ENET_SPEED_10000) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet 10G MAC driver only support 10G speed")); -+#if (FM_MAX_NUM_OF_10G_MACS > 0) -+ if (p_Tgec->macId >= FM_MAX_NUM_OF_10G_MACS) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("macId of 10G can not be greater than 0")); -+#endif /* (FM_MAX_NUM_OF_10G_MACS > 0) */ -+ -+ if (p_Tgec->addr == 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet 10G MAC Must have a valid MAC Address")); -+ if (!p_Tgec->f_Exception) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("uninitialized f_Exception")); -+ if (!p_Tgec->f_Event) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("uninitialized f_Event")); -+#ifdef FM_LEN_CHECK_ERRATA_FMAN_SW002 -+ if (!p_Tgec->p_TgecDriverParam->no_length_check_enable) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("LengthCheck!")); -+#endif /* FM_LEN_CHECK_ERRATA_FMAN_SW002 */ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static uint32_t GetMacAddrHashCode(uint64_t ethAddr) -+{ -+ uint32_t crc; -+ -+ /* CRC calculation */ -+ GET_MAC_ADDR_CRC(ethAddr, crc); -+ -+ crc = GetMirror32(crc); -+ -+ return crc; -+} -+ -+/* ......................................................................... */ -+ -+static void TgecErrException(t_Handle h_Tgec) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ uint32_t event; -+ struct tgec_regs *p_TgecMemMap = p_Tgec->p_MemMap; -+ -+ /* do not handle MDIO events */ -+ event = fman_tgec_get_event(p_TgecMemMap, ~(TGEC_IMASK_MDIO_SCAN_EVENT | TGEC_IMASK_MDIO_CMD_CMPL)); -+ event &= fman_tgec_get_interrupt_mask(p_TgecMemMap); -+ -+ fman_tgec_ack_event(p_TgecMemMap, event); -+ -+ if (event & TGEC_IMASK_REM_FAULT) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_REM_FAULT); -+ if (event & TGEC_IMASK_LOC_FAULT) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_LOC_FAULT); -+ if (event & TGEC_IMASK_TX_ECC_ER) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_1TX_ECC_ER); -+ if (event & TGEC_IMASK_TX_FIFO_UNFL) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_TX_FIFO_UNFL); -+ if (event & TGEC_IMASK_TX_FIFO_OVFL) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_TX_FIFO_OVFL); -+ if (event & TGEC_IMASK_TX_ER) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_TX_ER); -+ if (event & TGEC_IMASK_RX_FIFO_OVFL) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_FIFO_OVFL); -+ if (event & TGEC_IMASK_RX_ECC_ER) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_ECC_ER); -+ if (event & TGEC_IMASK_RX_JAB_FRM) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_JAB_FRM); -+ if (event & TGEC_IMASK_RX_OVRSZ_FRM) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_OVRSZ_FRM); -+ if (event & TGEC_IMASK_RX_RUNT_FRM) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_RUNT_FRM); -+ if (event & TGEC_IMASK_RX_FRAG_FRM) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_FRAG_FRM); -+ if (event & TGEC_IMASK_RX_LEN_ER) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_LEN_ER); -+ if (event & TGEC_IMASK_RX_CRC_ER) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_CRC_ER); -+ if (event & TGEC_IMASK_RX_ALIGN_ER) -+ p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_ALIGN_ER); -+} -+ -+/* ......................................................................... */ -+ -+static void TgecException(t_Handle h_Tgec) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ uint32_t event; -+ struct tgec_regs *p_TgecMemMap = p_Tgec->p_MemMap; -+ -+ /* handle only MDIO events */ -+ event = fman_tgec_get_event(p_TgecMemMap, (TGEC_IMASK_MDIO_SCAN_EVENT | TGEC_IMASK_MDIO_CMD_CMPL)); -+ event &= fman_tgec_get_interrupt_mask(p_TgecMemMap); -+ -+ fman_tgec_ack_event(p_TgecMemMap, event); -+ -+ if (event & TGEC_IMASK_MDIO_SCAN_EVENT) -+ p_Tgec->f_Event(p_Tgec->h_App, e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO); -+ if (event & TGEC_IMASK_MDIO_CMD_CMPL) -+ p_Tgec->f_Event(p_Tgec->h_App, e_FM_MAC_EX_10G_MDIO_CMD_CMPL); -+} -+ -+/* ......................................................................... */ -+ -+static void FreeInitResources(t_Tgec *p_Tgec) -+{ -+ if (p_Tgec->mdioIrq != NO_IRQ) -+ { -+ XX_DisableIntr(p_Tgec->mdioIrq); -+ XX_FreeIntr(p_Tgec->mdioIrq); -+ } -+ -+ FmUnregisterIntr(p_Tgec->fmMacControllerDriver.h_Fm, e_FM_MOD_10G_MAC, p_Tgec->macId, e_FM_INTR_TYPE_ERR); -+ -+ /* release the driver's group hash table */ -+ FreeHashTable(p_Tgec->p_MulticastAddrHash); -+ p_Tgec->p_MulticastAddrHash = NULL; -+ -+ /* release the driver's individual hash table */ -+ FreeHashTable(p_Tgec->p_UnicastAddrHash); -+ p_Tgec->p_UnicastAddrHash = NULL; -+} -+ -+ -+/*****************************************************************************/ -+/* 10G MAC API routines */ -+/*****************************************************************************/ -+ -+/* ......................................................................... */ -+ -+static t_Error TgecEnable(t_Handle h_Tgec, e_CommMode mode) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ fman_tgec_enable(p_Tgec->p_MemMap, (mode & e_COMM_MODE_RX), (mode & e_COMM_MODE_TX)); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecDisable (t_Handle h_Tgec, e_CommMode mode) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ fman_tgec_disable(p_Tgec->p_MemMap, (mode & e_COMM_MODE_RX), (mode & e_COMM_MODE_TX)); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecSetPromiscuous(t_Handle h_Tgec, bool newVal) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ fman_tgec_set_promiscuous(p_Tgec->p_MemMap, newVal); -+ -+ return E_OK; -+} -+ -+ -+/*****************************************************************************/ -+/* Tgec Configs modification functions */ -+/*****************************************************************************/ -+ -+/* ......................................................................... */ -+ -+static t_Error TgecConfigLoopback(t_Handle h_Tgec, bool newVal) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ p_Tgec->p_TgecDriverParam->loopback_enable = newVal; -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecConfigWan(t_Handle h_Tgec, bool newVal) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ p_Tgec->p_TgecDriverParam->wan_mode_enable = newVal; -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecConfigMaxFrameLength(t_Handle h_Tgec, uint16_t newVal) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ p_Tgec->p_TgecDriverParam->max_frame_length = newVal; -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecConfigLengthCheck(t_Handle h_Tgec, bool newVal) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ UNUSED(newVal); -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ p_Tgec->p_TgecDriverParam->no_length_check_enable = !newVal; -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecConfigException(t_Handle h_Tgec, e_FmMacExceptions exception, bool enable) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ uint32_t bitMask = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ GET_EXCEPTION_FLAG(bitMask, exception); -+ if (bitMask) -+ { -+ if (enable) -+ p_Tgec->exceptions |= bitMask; -+ else -+ p_Tgec->exceptions &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); -+ -+ return E_OK; -+} -+ -+#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -+/* ......................................................................... */ -+ -+static t_Error TgecConfigSkipFman11Workaround(t_Handle h_Tgec) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ p_Tgec->p_TgecDriverParam->skip_fman11_workaround = TRUE; -+ -+ return E_OK; -+} -+#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ -+ -+ -+/*****************************************************************************/ -+/* Tgec Run Time API functions */ -+/*****************************************************************************/ -+ -+/* ......................................................................... */ -+/* backward compatibility. will be removed in the future. */ -+static t_Error TgecTxMacPause(t_Handle h_Tgec, uint16_t pauseTime) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ fman_tgec_set_tx_pause_frames(p_Tgec->p_MemMap, pauseTime); -+ -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecSetTxPauseFrames(t_Handle h_Tgec, -+ uint8_t priority, -+ uint16_t pauseTime, -+ uint16_t threshTime) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ UNUSED(priority); UNUSED(threshTime); -+ -+ fman_tgec_set_tx_pause_frames(p_Tgec->p_MemMap, pauseTime); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecRxIgnoreMacPause(t_Handle h_Tgec, bool en) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ fman_tgec_set_rx_ignore_pause_frames(p_Tgec->p_MemMap, en); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecGetStatistics(t_Handle h_Tgec, t_FmMacStatistics *p_Statistics) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ struct tgec_regs *p_TgecMemMap; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_Statistics, E_NULL_POINTER); -+ -+ p_TgecMemMap = p_Tgec->p_MemMap; -+ -+ p_Statistics->eStatPkts64 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R64); -+ p_Statistics->eStatPkts65to127 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R127); -+ p_Statistics->eStatPkts128to255 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R255); -+ p_Statistics->eStatPkts256to511 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R511); -+ p_Statistics->eStatPkts512to1023 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R1023); -+ p_Statistics->eStatPkts1024to1518 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R1518); -+ p_Statistics->eStatPkts1519to1522 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R1519X); -+/* */ -+ p_Statistics->eStatFragments = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TRFRG); -+ p_Statistics->eStatJabbers = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TRJBR); -+ -+ p_Statistics->eStatsDropEvents = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RDRP); -+ p_Statistics->eStatCRCAlignErrors = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RALN); -+ -+ p_Statistics->eStatUndersizePkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TRUND); -+ p_Statistics->eStatOversizePkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TROVR); -+/* Pause */ -+ p_Statistics->reStatPause = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RXPF); -+ p_Statistics->teStatPause = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TXPF); -+ -+/* MIB II */ -+ p_Statistics->ifInOctets = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_ROCT); -+ p_Statistics->ifInUcastPkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RUCA); -+ p_Statistics->ifInMcastPkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RMCA); -+ p_Statistics->ifInBcastPkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RBCA); -+ p_Statistics->ifInPkts = p_Statistics->ifInUcastPkts -+ + p_Statistics->ifInMcastPkts -+ + p_Statistics->ifInBcastPkts; -+ p_Statistics->ifInDiscards = 0; -+ p_Statistics->ifInErrors = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RERR); -+ -+ p_Statistics->ifOutOctets = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TOCT); -+ p_Statistics->ifOutUcastPkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TUCA); -+ p_Statistics->ifOutMcastPkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TMCA); -+ p_Statistics->ifOutBcastPkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TBCA); -+ p_Statistics->ifOutPkts = p_Statistics->ifOutUcastPkts -+ + p_Statistics->ifOutMcastPkts -+ + p_Statistics->ifOutBcastPkts; -+ p_Statistics->ifOutDiscards = 0; -+ p_Statistics->ifOutErrors = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TERR); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecEnable1588TimeStamp(t_Handle h_Tgec) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ fman_tgec_enable_1588_time_stamp(p_Tgec->p_MemMap, 1); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecDisable1588TimeStamp(t_Handle h_Tgec) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ fman_tgec_enable_1588_time_stamp(p_Tgec->p_MemMap, 0); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecModifyMacAddress (t_Handle h_Tgec, t_EnetAddr *p_EnetAddr) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ p_Tgec->addr = ENET_ADDR_TO_UINT64(*p_EnetAddr); -+ fman_tgec_set_mac_address(p_Tgec->p_MemMap, (uint8_t *)(*p_EnetAddr)); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecResetCounters (t_Handle h_Tgec) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ fman_tgec_reset_stat(p_Tgec->p_MemMap); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecAddExactMatchMacAddress(t_Handle h_Tgec, t_EnetAddr *p_EthAddr) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *) h_Tgec; -+ uint64_t ethAddr; -+ uint8_t paddrNum; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr); -+ -+ if (ethAddr & GROUP_ADDRESS) -+ /* Multicast address has no effect in PADDR */ -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Multicast address")); -+ -+ /* Make sure no PADDR contains this address */ -+ for (paddrNum = 0; paddrNum < TGEC_NUM_OF_PADDRS; paddrNum++) -+ if (p_Tgec->indAddrRegUsed[paddrNum]) -+ if (p_Tgec->paddr[paddrNum] == ethAddr) -+ RETURN_ERROR(MAJOR, E_ALREADY_EXISTS, NO_MSG); -+ -+ /* Find first unused PADDR */ -+ for (paddrNum = 0; paddrNum < TGEC_NUM_OF_PADDRS; paddrNum++) -+ { -+ if (!(p_Tgec->indAddrRegUsed[paddrNum])) -+ { -+ /* mark this PADDR as used */ -+ p_Tgec->indAddrRegUsed[paddrNum] = TRUE; -+ /* store address */ -+ p_Tgec->paddr[paddrNum] = ethAddr; -+ -+ /* put in hardware */ -+ fman_tgec_add_addr_in_paddr(p_Tgec->p_MemMap, (uint8_t*)(*p_EthAddr)/* , paddrNum */); -+ p_Tgec->numOfIndAddrInRegs++; -+ -+ return E_OK; -+ } -+ } -+ -+ /* No free PADDR */ -+ RETURN_ERROR(MAJOR, E_FULL, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecDelExactMatchMacAddress(t_Handle h_Tgec, t_EnetAddr *p_EthAddr) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *) h_Tgec; -+ uint64_t ethAddr; -+ uint8_t paddrNum; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr); -+ -+ /* Find used PADDR containing this address */ -+ for (paddrNum = 0; paddrNum < TGEC_NUM_OF_PADDRS; paddrNum++) -+ { -+ if ((p_Tgec->indAddrRegUsed[paddrNum]) && -+ (p_Tgec->paddr[paddrNum] == ethAddr)) -+ { -+ /* mark this PADDR as not used */ -+ p_Tgec->indAddrRegUsed[paddrNum] = FALSE; -+ /* clear in hardware */ -+ fman_tgec_clear_addr_in_paddr(p_Tgec->p_MemMap /*, paddrNum */); -+ p_Tgec->numOfIndAddrInRegs--; -+ -+ return E_OK; -+ } -+ } -+ -+ RETURN_ERROR(MAJOR, E_NOT_FOUND, NO_MSG); -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecAddHashMacAddress(t_Handle h_Tgec, t_EnetAddr *p_EthAddr) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ t_EthHashEntry *p_HashEntry; -+ uint32_t crc; -+ uint32_t hash; -+ uint64_t ethAddr; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr); -+ -+ if (!(ethAddr & GROUP_ADDRESS)) -+ /* Unicast addresses not supported in hash */ -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Unicast Address")); -+ -+ /* CRC calculation */ -+ crc = GetMacAddrHashCode(ethAddr); -+ -+ hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK; /* Take 9 MSB bits */ -+ -+ /* Create element to be added to the driver hash table */ -+ p_HashEntry = (t_EthHashEntry *)XX_Malloc(sizeof(t_EthHashEntry)); -+ p_HashEntry->addr = ethAddr; -+ INIT_LIST(&p_HashEntry->node); -+ -+ LIST_AddToTail(&(p_HashEntry->node), &(p_Tgec->p_MulticastAddrHash->p_Lsts[hash])); -+ fman_tgec_set_hash_table(p_Tgec->p_MemMap, (hash | TGEC_HASH_MCAST_EN)); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecDelHashMacAddress(t_Handle h_Tgec, t_EnetAddr *p_EthAddr) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ t_EthHashEntry *p_HashEntry = NULL; -+ t_List *p_Pos; -+ uint32_t crc; -+ uint32_t hash; -+ uint64_t ethAddr; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ ethAddr = ((*(uint64_t *)p_EthAddr) >> 16); -+ -+ /* CRC calculation */ -+ crc = GetMacAddrHashCode(ethAddr); -+ -+ hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK; /* Take 9 MSB bits */ -+ -+ LIST_FOR_EACH(p_Pos, &(p_Tgec->p_MulticastAddrHash->p_Lsts[hash])) -+ { -+ p_HashEntry = ETH_HASH_ENTRY_OBJ(p_Pos); -+ if (p_HashEntry->addr == ethAddr) -+ { -+ LIST_DelAndInit(&p_HashEntry->node); -+ XX_Free(p_HashEntry); -+ break; -+ } -+ } -+ if (LIST_IsEmpty(&p_Tgec->p_MulticastAddrHash->p_Lsts[hash])) -+ fman_tgec_set_hash_table(p_Tgec->p_MemMap, (hash & ~TGEC_HASH_MCAST_EN)); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecGetId(t_Handle h_Tgec, uint32_t *macId) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ UNUSED(p_Tgec); -+ UNUSED(macId); -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("TgecGetId Not Supported")); -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecGetVersion(t_Handle h_Tgec, uint32_t *macVersion) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ *macVersion = fman_tgec_get_revision(p_Tgec->p_MemMap); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecSetExcpetion(t_Handle h_Tgec, e_FmMacExceptions exception, bool enable) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ uint32_t bitMask = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ -+ GET_EXCEPTION_FLAG(bitMask, exception); -+ if (bitMask) -+ { -+ if (enable) -+ p_Tgec->exceptions |= bitMask; -+ else -+ p_Tgec->exceptions &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); -+ -+ if (enable) -+ fman_tgec_enable_interrupt(p_Tgec->p_MemMap, bitMask); -+ else -+ fman_tgec_disable_interrupt(p_Tgec->p_MemMap, bitMask); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static uint16_t TgecGetMaxFrameLength(t_Handle h_Tgec) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_VALUE(p_Tgec, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_VALUE(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE, 0); -+ -+ return fman_tgec_get_max_frame_len(p_Tgec->p_MemMap); -+} -+ -+/* ......................................................................... */ -+ -+#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -+static t_Error TgecTxEccWorkaround(t_Tgec *p_Tgec) -+{ -+ t_Error err; -+ -+#if defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0) -+ XX_Print("Applying 10G TX ECC workaround (10GMAC-A004) ... "); -+#endif /* (DEBUG_ERRORS > 0) */ -+ /* enable and set promiscuous */ -+ fman_tgec_enable(p_Tgec->p_MemMap, TRUE, TRUE); -+ fman_tgec_set_promiscuous(p_Tgec->p_MemMap, TRUE); -+ err = Fm10GTxEccWorkaround(p_Tgec->fmMacControllerDriver.h_Fm, p_Tgec->macId); -+ /* disable */ -+ fman_tgec_set_promiscuous(p_Tgec->p_MemMap, FALSE); -+ fman_tgec_enable(p_Tgec->p_MemMap, FALSE, FALSE); -+ fman_tgec_reset_stat(p_Tgec->p_MemMap); -+ fman_tgec_ack_event(p_Tgec->p_MemMap, 0xffffffff); -+#if defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0) -+ if (err) -+ XX_Print("FAILED!\n"); -+ else -+ XX_Print("done.\n"); -+#endif /* (DEBUG_ERRORS > 0) */ -+ -+ return err; -+} -+#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ -+ -+/*****************************************************************************/ -+/* FM Init & Free API */ -+/*****************************************************************************/ -+ -+/* ......................................................................... */ -+ -+static t_Error TgecInit(t_Handle h_Tgec) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ struct tgec_cfg *p_TgecDriverParam; -+ t_EnetAddr ethAddr; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_Tgec->fmMacControllerDriver.h_Fm, E_INVALID_HANDLE); -+ -+ FM_GetRevision(p_Tgec->fmMacControllerDriver.h_Fm, &p_Tgec->fmMacControllerDriver.fmRevInfo); -+ CHECK_INIT_PARAMETERS(p_Tgec, CheckInitParameters); -+ -+ p_TgecDriverParam = p_Tgec->p_TgecDriverParam; -+ -+ MAKE_ENET_ADDR_FROM_UINT64(p_Tgec->addr, ethAddr); -+ fman_tgec_set_mac_address(p_Tgec->p_MemMap, (uint8_t *)ethAddr); -+ -+ /* interrupts */ -+#ifdef FM_10G_REM_N_LCL_FLT_EX_10GMAC_ERRATA_SW005 -+ { -+ if (p_Tgec->fmMacControllerDriver.fmRevInfo.majorRev <=2) -+ p_Tgec->exceptions &= ~(TGEC_IMASK_REM_FAULT | TGEC_IMASK_LOC_FAULT); -+ } -+#endif /* FM_10G_REM_N_LCL_FLT_EX_10GMAC_ERRATA_SW005 */ -+ -+#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -+ if (!p_Tgec->p_TgecDriverParam->skip_fman11_workaround && -+ ((err = TgecTxEccWorkaround(p_Tgec)) != E_OK)) -+ { -+ FreeInitResources(p_Tgec); -+ REPORT_ERROR(MINOR, err, ("TgecTxEccWorkaround FAILED")); -+ } -+#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ -+ -+ err = fman_tgec_init(p_Tgec->p_MemMap, p_TgecDriverParam, p_Tgec->exceptions); -+ if (err) -+ { -+ FreeInitResources(p_Tgec); -+ RETURN_ERROR(MAJOR, err, ("This TGEC version does not support the required i/f mode")); -+ } -+ -+ /* Max Frame Length */ -+ err = FmSetMacMaxFrame(p_Tgec->fmMacControllerDriver.h_Fm, -+ e_FM_MAC_10G, -+ p_Tgec->fmMacControllerDriver.macId, -+ p_TgecDriverParam->max_frame_length); -+ if (err != E_OK) -+ { -+ FreeInitResources(p_Tgec); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+/* we consider having no IPC a non crasher... */ -+ -+#ifdef FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007 -+ if (p_Tgec->fmMacControllerDriver.fmRevInfo.majorRev == 2) -+ fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(p_Tgec->p_MemMap); -+#endif /* FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007 */ -+ -+ p_Tgec->p_MulticastAddrHash = AllocHashTable(HASH_TABLE_SIZE); -+ if (!p_Tgec->p_MulticastAddrHash) -+ { -+ FreeInitResources(p_Tgec); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("allocation hash table is FAILED")); -+ } -+ -+ p_Tgec->p_UnicastAddrHash = AllocHashTable(HASH_TABLE_SIZE); -+ if (!p_Tgec->p_UnicastAddrHash) -+ { -+ FreeInitResources(p_Tgec); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("allocation hash table is FAILED")); -+ } -+ -+ FmRegisterIntr(p_Tgec->fmMacControllerDriver.h_Fm, -+ e_FM_MOD_10G_MAC, -+ p_Tgec->macId, -+ e_FM_INTR_TYPE_ERR, -+ TgecErrException, -+ p_Tgec); -+ if (p_Tgec->mdioIrq != NO_IRQ) -+ { -+ XX_SetIntr(p_Tgec->mdioIrq, TgecException, p_Tgec); -+ XX_EnableIntr(p_Tgec->mdioIrq); -+ } -+ -+ XX_Free(p_TgecDriverParam); -+ p_Tgec->p_TgecDriverParam = NULL; -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static t_Error TgecFree(t_Handle h_Tgec) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ -+ if (p_Tgec->p_TgecDriverParam) -+ { -+ /* Called after config */ -+ XX_Free(p_Tgec->p_TgecDriverParam); -+ p_Tgec->p_TgecDriverParam = NULL; -+ } -+ else -+ /* Called after init */ -+ FreeInitResources(p_Tgec); -+ -+ XX_Free(p_Tgec); -+ -+ return E_OK; -+} -+ -+/* ......................................................................... */ -+ -+static void InitFmMacControllerDriver(t_FmMacControllerDriver *p_FmMacControllerDriver) -+{ -+ p_FmMacControllerDriver->f_FM_MAC_Init = TgecInit; -+ p_FmMacControllerDriver->f_FM_MAC_Free = TgecFree; -+ -+ p_FmMacControllerDriver->f_FM_MAC_SetStatistics = NULL; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback = TgecConfigLoopback; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength = TgecConfigMaxFrameLength; -+ -+ p_FmMacControllerDriver->f_FM_MAC_ConfigWan = TgecConfigWan; -+ -+ p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc = NULL; /* TGEC always works with pad+crc */ -+ p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex = NULL; /* half-duplex is not supported in xgec */ -+ p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck = TgecConfigLengthCheck; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigException = TgecConfigException; -+ p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit = NULL; -+ -+#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -+ p_FmMacControllerDriver->f_FM_MAC_ConfigSkipFman11Workaround= TgecConfigSkipFman11Workaround; -+#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ -+ -+ p_FmMacControllerDriver->f_FM_MAC_SetException = TgecSetExcpetion; -+ -+ p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp = TgecEnable1588TimeStamp; -+ p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp = TgecDisable1588TimeStamp; -+ -+ p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous = TgecSetPromiscuous; -+ p_FmMacControllerDriver->f_FM_MAC_AdjustLink = NULL; -+ p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan = NULL; -+ p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg = NULL; -+ -+ p_FmMacControllerDriver->f_FM_MAC_Enable = TgecEnable; -+ p_FmMacControllerDriver->f_FM_MAC_Disable = TgecDisable; -+ -+ p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames = TgecTxMacPause; -+ p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames = TgecSetTxPauseFrames; -+ p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames = TgecRxIgnoreMacPause; -+ -+ p_FmMacControllerDriver->f_FM_MAC_ResetCounters = TgecResetCounters; -+ p_FmMacControllerDriver->f_FM_MAC_GetStatistics = TgecGetStatistics; -+ -+ p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr = TgecModifyMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr = TgecAddHashMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr = TgecDelHashMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr = TgecAddExactMatchMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr = TgecDelExactMatchMacAddress; -+ p_FmMacControllerDriver->f_FM_MAC_GetId = TgecGetId; -+ p_FmMacControllerDriver->f_FM_MAC_GetVersion = TgecGetVersion; -+ p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength = TgecGetMaxFrameLength; -+ -+ p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg = TGEC_MII_WritePhyReg; -+ p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg = TGEC_MII_ReadPhyReg; -+} -+ -+ -+/*****************************************************************************/ -+/* Tgec Config Main Entry */ -+/*****************************************************************************/ -+ -+/* ......................................................................... */ -+ -+t_Handle TGEC_Config(t_FmMacParams *p_FmMacParam) -+{ -+ t_Tgec *p_Tgec; -+ struct tgec_cfg *p_TgecDriverParam; -+ uintptr_t baseAddr; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmMacParam, E_NULL_POINTER, NULL); -+ -+ baseAddr = p_FmMacParam->baseAddr; -+ /* allocate memory for the UCC GETH data structure. */ -+ p_Tgec = (t_Tgec *)XX_Malloc(sizeof(t_Tgec)); -+ if (!p_Tgec) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("10G MAC driver structure")); -+ return NULL; -+ } -+ memset(p_Tgec, 0, sizeof(t_Tgec)); -+ InitFmMacControllerDriver(&p_Tgec->fmMacControllerDriver); -+ -+ /* allocate memory for the 10G MAC driver parameters data structure. */ -+ p_TgecDriverParam = (struct tgec_cfg *) XX_Malloc(sizeof(struct tgec_cfg)); -+ if (!p_TgecDriverParam) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("10G MAC driver parameters")); -+ XX_Free(p_Tgec); -+ return NULL; -+ } -+ memset(p_TgecDriverParam, 0, sizeof(struct tgec_cfg)); -+ -+ /* Plant parameter structure pointer */ -+ p_Tgec->p_TgecDriverParam = p_TgecDriverParam; -+ -+ fman_tgec_defconfig(p_TgecDriverParam); -+ -+ p_Tgec->p_MemMap = (struct tgec_regs *)UINT_TO_PTR(baseAddr); -+ p_Tgec->p_MiiMemMap = (t_TgecMiiAccessMemMap *)UINT_TO_PTR(baseAddr + TGEC_TO_MII_OFFSET); -+ p_Tgec->addr = ENET_ADDR_TO_UINT64(p_FmMacParam->addr); -+ p_Tgec->enetMode = p_FmMacParam->enetMode; -+ p_Tgec->macId = p_FmMacParam->macId; -+ p_Tgec->exceptions = DEFAULT_exceptions; -+ p_Tgec->mdioIrq = p_FmMacParam->mdioIrq; -+ p_Tgec->f_Exception = p_FmMacParam->f_Exception; -+ p_Tgec->f_Event = p_FmMacParam->f_Event; -+ p_Tgec->h_App = p_FmMacParam->h_App; -+ -+ return p_Tgec; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.h -@@ -0,0 +1,151 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File tgec.h -+ -+ @Description FM 10G MAC ... -+*//***************************************************************************/ -+#ifndef __TGEC_H -+#define __TGEC_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "list_ext.h" -+#include "enet_ext.h" -+ -+#include "tgec_mii_acc.h" -+#include "fm_mac.h" -+ -+ -+#define DEFAULT_exceptions \ -+ ((uint32_t)(TGEC_IMASK_MDIO_SCAN_EVENT | \ -+ TGEC_IMASK_REM_FAULT | \ -+ TGEC_IMASK_LOC_FAULT | \ -+ TGEC_IMASK_TX_ECC_ER | \ -+ TGEC_IMASK_TX_FIFO_UNFL | \ -+ TGEC_IMASK_TX_FIFO_OVFL | \ -+ TGEC_IMASK_TX_ER | \ -+ TGEC_IMASK_RX_FIFO_OVFL | \ -+ TGEC_IMASK_RX_ECC_ER | \ -+ TGEC_IMASK_RX_JAB_FRM | \ -+ TGEC_IMASK_RX_OVRSZ_FRM | \ -+ TGEC_IMASK_RX_RUNT_FRM | \ -+ TGEC_IMASK_RX_FRAG_FRM | \ -+ TGEC_IMASK_RX_CRC_ER | \ -+ TGEC_IMASK_RX_ALIGN_ER)) -+ -+#define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \ -+ case e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO: \ -+ bitMask = TGEC_IMASK_MDIO_SCAN_EVENT ; break; \ -+ case e_FM_MAC_EX_10G_MDIO_CMD_CMPL: \ -+ bitMask = TGEC_IMASK_MDIO_CMD_CMPL ; break; \ -+ case e_FM_MAC_EX_10G_REM_FAULT: \ -+ bitMask = TGEC_IMASK_REM_FAULT ; break; \ -+ case e_FM_MAC_EX_10G_LOC_FAULT: \ -+ bitMask = TGEC_IMASK_LOC_FAULT ; break; \ -+ case e_FM_MAC_EX_10G_1TX_ECC_ER: \ -+ bitMask = TGEC_IMASK_TX_ECC_ER ; break; \ -+ case e_FM_MAC_EX_10G_TX_FIFO_UNFL: \ -+ bitMask = TGEC_IMASK_TX_FIFO_UNFL ; break; \ -+ case e_FM_MAC_EX_10G_TX_FIFO_OVFL: \ -+ bitMask = TGEC_IMASK_TX_FIFO_OVFL ; break; \ -+ case e_FM_MAC_EX_10G_TX_ER: \ -+ bitMask = TGEC_IMASK_TX_ER ; break; \ -+ case e_FM_MAC_EX_10G_RX_FIFO_OVFL: \ -+ bitMask = TGEC_IMASK_RX_FIFO_OVFL ; break; \ -+ case e_FM_MAC_EX_10G_RX_ECC_ER: \ -+ bitMask = TGEC_IMASK_RX_ECC_ER ; break; \ -+ case e_FM_MAC_EX_10G_RX_JAB_FRM: \ -+ bitMask = TGEC_IMASK_RX_JAB_FRM ; break; \ -+ case e_FM_MAC_EX_10G_RX_OVRSZ_FRM: \ -+ bitMask = TGEC_IMASK_RX_OVRSZ_FRM ; break; \ -+ case e_FM_MAC_EX_10G_RX_RUNT_FRM: \ -+ bitMask = TGEC_IMASK_RX_RUNT_FRM ; break; \ -+ case e_FM_MAC_EX_10G_RX_FRAG_FRM: \ -+ bitMask = TGEC_IMASK_RX_FRAG_FRM ; break; \ -+ case e_FM_MAC_EX_10G_RX_LEN_ER: \ -+ bitMask = TGEC_IMASK_RX_LEN_ER ; break; \ -+ case e_FM_MAC_EX_10G_RX_CRC_ER: \ -+ bitMask = TGEC_IMASK_RX_CRC_ER ; break; \ -+ case e_FM_MAC_EX_10G_RX_ALIGN_ER: \ -+ bitMask = TGEC_IMASK_RX_ALIGN_ER ; break; \ -+ default: bitMask = 0;break;} -+ -+#define MAX_PACKET_ALIGNMENT 31 -+#define MAX_INTER_PACKET_GAP 0x7f -+#define MAX_INTER_PALTERNATE_BEB 0x0f -+#define MAX_RETRANSMISSION 0x0f -+#define MAX_COLLISION_WINDOW 0x03ff -+ -+#define TGEC_NUM_OF_PADDRS 1 /* number of pattern match registers (entries) */ -+ -+#define GROUP_ADDRESS 0x0000010000000000LL /* Group address bit indication */ -+ -+#define HASH_TABLE_SIZE 512 /* Hash table size (= 32 bits * 8 regs) */ -+ -+#define TGEC_TO_MII_OFFSET 0x1030 /* Offset from the MEM map to the MDIO mem map */ -+ -+/* 10-gigabit Ethernet MAC Controller ID (10GEC_ID) */ -+#define TGEC_ID_ID 0xffff0000 -+#define TGEC_ID_MAC_VERSION 0x0000FF00 -+#define TGEC_ID_MAC_REV 0x000000ff -+ -+ -+typedef struct { -+ t_FmMacControllerDriver fmMacControllerDriver; /**< Upper Mac control block */ -+ t_Handle h_App; /**< Handle to the upper layer application */ -+ struct tgec_regs *p_MemMap; /**< pointer to 10G memory mapped registers. */ -+ t_TgecMiiAccessMemMap *p_MiiMemMap; /**< pointer to MII memory mapped registers. */ -+ uint64_t addr; /**< MAC address of device; */ -+ e_EnetMode enetMode; /**< Ethernet physical interface */ -+ t_FmMacExceptionCallback *f_Exception; -+ int mdioIrq; -+ t_FmMacExceptionCallback *f_Event; -+ bool indAddrRegUsed[TGEC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */ -+ uint64_t paddr[TGEC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */ -+ uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */ -+ t_EthHash *p_MulticastAddrHash; /**< pointer to driver's global address hash table */ -+ t_EthHash *p_UnicastAddrHash; /**< pointer to driver's individual address hash table */ -+ bool debugMode; -+ uint8_t macId; -+ uint32_t exceptions; -+ struct tgec_cfg *p_TgecDriverParam; -+} t_Tgec; -+ -+ -+t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec, uint8_t phyAddr, uint8_t reg, uint16_t data); -+t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data); -+ -+ -+#endif /* __TGEC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.c -@@ -0,0 +1,139 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "fm_mac.h" -+#include "tgec.h" -+#include "xx_ext.h" -+ -+#include "fm_common.h" -+ -+ -+/*****************************************************************************/ -+t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec, -+ uint8_t phyAddr, -+ uint8_t reg, -+ uint16_t data) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ t_TgecMiiAccessMemMap *p_MiiAccess; -+ uint32_t cfgStatusReg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE); -+ -+ p_MiiAccess = p_Tgec->p_MiiMemMap; -+ -+ /* Configure MII */ -+ cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status); -+ cfgStatusReg &= ~MIIMCOM_DIV_MASK; -+ /* (one half of fm clock => 2.5Mhz) */ -+ cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT); -+ WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg); -+ -+ while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY) -+ XX_UDelay (1); -+ -+ WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr); -+ -+ WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg); -+ -+ CORE_MemoryBarrier(); -+ -+ while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY) -+ XX_UDelay (1); -+ -+ WRITE_UINT32(p_MiiAccess->mdio_data, data); -+ -+ CORE_MemoryBarrier(); -+ -+ while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY) -+ XX_UDelay (1); -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec, -+ uint8_t phyAddr, -+ uint8_t reg, -+ uint16_t *p_Data) -+{ -+ t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; -+ t_TgecMiiAccessMemMap *p_MiiAccess; -+ uint32_t cfgStatusReg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE); -+ -+ p_MiiAccess = p_Tgec->p_MiiMemMap; -+ -+ /* Configure MII */ -+ cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status); -+ cfgStatusReg &= ~MIIMCOM_DIV_MASK; -+ /* (one half of fm clock => 2.5Mhz) */ -+ cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT); -+ WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg); -+ -+ while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY) -+ XX_UDelay (1); -+ -+ WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr); -+ -+ WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg); -+ -+ CORE_MemoryBarrier(); -+ -+ while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY) -+ XX_UDelay (1); -+ -+ WRITE_UINT32(p_MiiAccess->mdio_command, (uint32_t)(phyAddr | MIIMCOM_READ_CYCLE)); -+ -+ CORE_MemoryBarrier(); -+ -+ while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY) -+ XX_UDelay (1); -+ -+ *p_Data = (uint16_t)GET_UINT32(p_MiiAccess->mdio_data); -+ -+ cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status); -+ -+ if (cfgStatusReg & MIIMIND_READ_ERROR) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, -+ ("Read Error: phyAddr 0x%x, dev 0x%x, reg 0x%x, cfgStatusReg 0x%x", -+ ((phyAddr & 0xe0)>>5), (phyAddr & 0x1f), reg, cfgStatusReg)); -+ -+ return E_OK; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.h -@@ -0,0 +1,80 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#ifndef __TGEC_MII_ACC_H -+#define __TGEC_MII_ACC_H -+ -+#include "std_ext.h" -+ -+ -+/* MII Management Command Register */ -+#define MIIMCOM_READ_POST_INCREMENT 0x00004000 -+#define MIIMCOM_READ_CYCLE 0x00008000 -+#define MIIMCOM_SCAN_CYCLE 0x00000800 -+#define MIIMCOM_PREAMBLE_DISABLE 0x00000400 -+ -+#define MIIMCOM_MDIO_HOLD_1_REG_CLK 0 -+#define MIIMCOM_MDIO_HOLD_2_REG_CLK 1 -+#define MIIMCOM_MDIO_HOLD_3_REG_CLK 2 -+#define MIIMCOM_MDIO_HOLD_4_REG_CLK 3 -+ -+#define MIIMCOM_DIV_MASK 0x0000ff00 -+#define MIIMCOM_DIV_SHIFT 8 -+ -+/* MII Management Indicator Register */ -+#define MIIMIND_BUSY 0x00000001 -+#define MIIMIND_READ_ERROR 0x00000002 -+ -+#define MIIDATA_BUSY 0x80000000 -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+/*----------------------------------------------------*/ -+/* MII Configuration Control Memory Map Registers */ -+/*----------------------------------------------------*/ -+typedef _Packed struct t_TgecMiiAccessMemMap -+{ -+ volatile uint32_t mdio_cfg_status; /* 0x030 */ -+ volatile uint32_t mdio_command; /* 0x034 */ -+ volatile uint32_t mdio_data; /* 0x038 */ -+ volatile uint32_t mdio_regaddr; /* 0x03c */ -+} _PackedType t_TgecMiiAccessMemMap ; -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+ -+#endif /* __TGEC_MII_ACC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/Makefile -@@ -0,0 +1,15 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+ -+NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc -+ -+ccflags-y += -I$(NCSW_FM_INC) -+ -+obj-y += fsl-ncsw-macsec.o -+ -+fsl-ncsw-macsec-objs := fm_macsec.o fm_macsec_guest.o fm_macsec_master.o fm_macsec_secy.o ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec.c -@@ -0,0 +1,237 @@ -+/* -+ * Copyright 2008-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+/****************************************************************************** -+ -+ @File fm_macsec.c -+ -+ @Description FM MACSEC driver routines implementation. -+*//***************************************************************************/ -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "xx_ext.h" -+#include "string_ext.h" -+#include "sprint_ext.h" -+#include "debug_ext.h" -+ -+#include "fm_macsec.h" -+ -+ -+/****************************************/ -+/* API Init unit functions */ -+/****************************************/ -+t_Handle FM_MACSEC_Config(t_FmMacsecParams *p_FmMacsecParam) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmMacsecParam, E_INVALID_HANDLE, NULL); -+ -+ if (p_FmMacsecParam->guestMode) -+ p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)FM_MACSEC_GUEST_Config(p_FmMacsecParam); -+ else -+ p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)FM_MACSEC_MASTER_Config(p_FmMacsecParam); -+ -+ if (!p_FmMacsecControllerDriver) -+ return NULL; -+ -+ return (t_Handle)p_FmMacsecControllerDriver; -+} -+ -+t_Error FM_MACSEC_Init(t_Handle h_FmMacsec) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_Init) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_Init(h_FmMacsec); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_Free(t_Handle h_FmMacsec) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_Free) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_Free(h_FmMacsec); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_ConfigUnknownSciFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUnknownSciFrameTreatment treatMode) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUnknownSciFrameTreatment) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUnknownSciFrameTreatment(h_FmMacsec, treatMode); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_ConfigInvalidTagsFrameTreatment(t_Handle h_FmMacsec, bool deliverUncontrolled) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigInvalidTagsFrameTreatment) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigInvalidTagsFrameTreatment(h_FmMacsec, deliverUncontrolled); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment(t_Handle h_FmMacsec, bool discardUncontrolled) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment(h_FmMacsec, discardUncontrolled); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_ConfigUntagFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUntagFrameTreatment treatMode) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUntagFrameTreatment) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUntagFrameTreatment(h_FmMacsec, treatMode); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_ConfigPnExhaustionThreshold(t_Handle h_FmMacsec, uint32_t pnExhThr) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigPnExhaustionThreshold) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigPnExhaustionThreshold(h_FmMacsec, pnExhThr); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_ConfigKeysUnreadable(t_Handle h_FmMacsec) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigKeysUnreadable) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigKeysUnreadable(h_FmMacsec); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_ConfigSectagWithoutSCI(t_Handle h_FmMacsec) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigSectagWithoutSCI) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigSectagWithoutSCI(h_FmMacsec); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_ConfigException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigException) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigException(h_FmMacsec, exception, enable); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_GetRevision(t_Handle h_FmMacsec, uint32_t *p_MacsecRevision) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_GetRevision) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_GetRevision(h_FmMacsec, p_MacsecRevision); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+ -+t_Error FM_MACSEC_Enable(t_Handle h_FmMacsec) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_Enable) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_Enable(h_FmMacsec); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_Disable(t_Handle h_FmMacsec) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_Disable) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_Disable(h_FmMacsec); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_SetException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable) -+{ -+ t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecControllerDriver->f_FM_MACSEC_SetException) -+ return p_FmMacsecControllerDriver->f_FM_MACSEC_SetException(h_FmMacsec, exception, enable); -+ -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec.h -@@ -0,0 +1,203 @@ -+/* -+ * Copyright 2008-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/****************************************************************************** -+ @File fm_macsec.h -+ -+ @Description FM MACSEC internal structures and definitions. -+*//***************************************************************************/ -+#ifndef __FM_MACSEC_H -+#define __FM_MACSEC_H -+ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "fm_macsec_ext.h" -+ -+#include "fm_common.h" -+ -+ -+#define __ERR_MODULE__ MODULE_FM_MACSEC -+ -+ -+typedef struct -+{ -+ t_Error (*f_FM_MACSEC_Init) (t_Handle h_FmMacsec); -+ t_Error (*f_FM_MACSEC_Free) (t_Handle h_FmMacsec); -+ -+ t_Error (*f_FM_MACSEC_ConfigUnknownSciFrameTreatment) (t_Handle h_FmMacsec, e_FmMacsecUnknownSciFrameTreatment treatMode); -+ t_Error (*f_FM_MACSEC_ConfigInvalidTagsFrameTreatment) (t_Handle h_FmMacsec, bool deliverUncontrolled); -+ t_Error (*f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment) (t_Handle h_FmMacsec, bool discardUncontrolled); -+ t_Error (*f_FM_MACSEC_ConfigChangedTextWithNoEncryptFrameTreatment) (t_Handle h_FmMacsec, bool deliverUncontrolled); -+ t_Error (*f_FM_MACSEC_ConfigUntagFrameTreatment) (t_Handle h_FmMacsec, e_FmMacsecUntagFrameTreatment treatMode); -+ t_Error (*f_FM_MACSEC_ConfigOnlyScbIsSetFrameTreatment) (t_Handle h_FmMacsec, bool deliverUncontrolled); -+ t_Error (*f_FM_MACSEC_ConfigPnExhaustionThreshold) (t_Handle h_FmMacsec, uint32_t pnExhThr); -+ t_Error (*f_FM_MACSEC_ConfigKeysUnreadable) (t_Handle h_FmMacsec); -+ t_Error (*f_FM_MACSEC_ConfigSectagWithoutSCI) (t_Handle h_FmMacsec); -+ t_Error (*f_FM_MACSEC_ConfigException) (t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable); -+ -+ t_Error (*f_FM_MACSEC_GetRevision) (t_Handle h_FmMacsec, uint32_t *p_MacsecRevision); -+ t_Error (*f_FM_MACSEC_Enable) (t_Handle h_FmMacsec); -+ t_Error (*f_FM_MACSEC_Disable) (t_Handle h_FmMacsec); -+ t_Error (*f_FM_MACSEC_SetException) (t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable); -+ -+} t_FmMacsecControllerDriver; -+ -+t_Handle FM_MACSEC_GUEST_Config(t_FmMacsecParams *p_FmMacsecParam); -+t_Handle FM_MACSEC_MASTER_Config(t_FmMacsecParams *p_FmMacsecParams); -+ -+/***********************************************************************/ -+/* MACSEC internal routines */ -+/***********************************************************************/ -+ -+/**************************************************************************//** -+ -+ @Group FM_MACSEC_InterModule_grp FM MACSEC Inter-Module Unit -+ -+ @Description FM MACSEC Inter Module functions - -+ These are not User API routines but routines that may be called -+ from other modules. This will be the case in a single core environment, -+ where instead of using the XX messaging mechanism, the routines may be -+ called from other modules. In a multicore environment, the other modules may -+ be run by other cores and therefore these routines may not be called directly. -+ -+ @{ -+*//***************************************************************************/ -+ -+#define MAX_NUM_OF_SA_PER_SC 4 -+ -+typedef enum -+{ -+ e_SC_RX = 0, -+ e_SC_TX -+} e_ScType; -+ -+typedef enum -+{ -+ e_SC_SA_A = 0, -+ e_SC_SA_B , -+ e_SC_SA_C , -+ e_SC_SA_D -+} e_ScSaId; -+ -+typedef struct -+{ -+ uint32_t scId; -+ macsecSCI_t sci; -+ bool replayProtect; -+ uint32_t replayWindow; -+ e_FmMacsecValidFrameBehavior validateFrames; -+ uint16_t confidentialityOffset; -+ e_FmMacsecSecYCipherSuite cipherSuite; -+} t_RxScParams; -+ -+typedef struct -+{ -+ uint32_t scId; -+ macsecSCI_t sci; -+ bool protectFrames; -+ e_FmMacsecSciInsertionMode sciInsertionMode; -+ bool confidentialityEnable; -+ uint16_t confidentialityOffset; -+ e_FmMacsecSecYCipherSuite cipherSuite; -+} t_TxScParams; -+ -+typedef enum e_FmMacsecGlobalExceptions { -+ e_FM_MACSEC_EX_TX_SC, /**< Tx Sc 0 frame discarded error. */ -+ e_FM_MACSEC_EX_ECC /**< MACSEC memory ECC multiple-bit error. */ -+} e_FmMacsecGlobalExceptions; -+ -+typedef enum e_FmMacsecGlobalEvents { -+ e_FM_MACSEC_EV_TX_SC_NEXT_PN /**< Tx Sc 0 Next Pn exhaustion threshold reached. */ -+} e_FmMacsecGlobalEvents; -+ -+/**************************************************************************//** -+ @Description Enum for inter-module interrupts registration -+*//***************************************************************************/ -+typedef enum e_FmMacsecEventModules{ -+ e_FM_MACSEC_MOD_SC_TX, -+ e_FM_MACSEC_MOD_DUMMY_LAST -+} e_FmMacsecEventModules; -+ -+typedef enum e_FmMacsecInterModuleEvent { -+ e_FM_MACSEC_EV_SC_TX, -+ e_FM_MACSEC_EV_ERR_SC_TX, -+ e_FM_MACSEC_EV_DUMMY_LAST -+} e_FmMacsecInterModuleEvent; -+ -+#define NUM_OF_INTER_MODULE_EVENTS (NUM_OF_TX_SC * 2) -+ -+#define GET_MACSEC_MODULE_EVENT(mod, id, intrType, event) \ -+ switch(mod){ \ -+ case e_FM_MACSEC_MOD_SC_TX: \ -+ event = (intrType == e_FM_INTR_TYPE_ERR) ? \ -+ e_FM_MACSEC_EV_ERR_SC_TX: \ -+ e_FM_MACSEC_EV_SC_TX; \ -+ event += (uint8_t)(2 * id);break; \ -+ break; \ -+ default:event = e_FM_MACSEC_EV_DUMMY_LAST; \ -+ break;} -+ -+void FmMacsecRegisterIntr(t_Handle h_FmMacsec, -+ e_FmMacsecEventModules module, -+ uint8_t modId, -+ e_FmIntrType intrType, -+ void (*f_Isr) (t_Handle h_Arg, uint32_t id), -+ t_Handle h_Arg); -+ -+void FmMacsecUnregisterIntr(t_Handle h_FmMacsec, -+ e_FmMacsecEventModules module, -+ uint8_t modId, -+ e_FmIntrType intrType); -+ -+t_Error FmMacsecAllocScs(t_Handle h_FmMacsec, e_ScType type, bool isPtp, uint32_t numOfScs, uint32_t *p_ScIds); -+t_Error FmMacsecFreeScs(t_Handle h_FmMacsec, e_ScType type, uint32_t numOfScs, uint32_t *p_ScIds); -+t_Error FmMacsecCreateRxSc(t_Handle h_FmMacsec, t_RxScParams *p_RxScParams); -+t_Error FmMacsecDeleteRxSc(t_Handle h_FmMacsec, uint32_t scId); -+t_Error FmMacsecCreateTxSc(t_Handle h_FmMacsec, t_TxScParams *p_RxScParams); -+t_Error FmMacsecDeleteTxSc(t_Handle h_FmMacsec, uint32_t scId); -+t_Error FmMacsecCreateRxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecAN_t an, uint32_t lowestPn, macsecSAKey_t key); -+t_Error FmMacsecCreateTxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecSAKey_t key); -+t_Error FmMacsecDeleteRxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId); -+t_Error FmMacsecDeleteTxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId); -+t_Error FmMacsecRxSaSetReceive(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, bool enableReceive); -+t_Error FmMacsecRxSaUpdateNextPn(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, uint32_t updtNextPN); -+t_Error FmMacsecRxSaUpdateLowestPn(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, uint32_t updtLowestPN); -+t_Error FmMacsecTxSaSetActive(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecAN_t an); -+t_Error FmMacsecTxSaGetActive(t_Handle h_FmMacsec, uint32_t scId, macsecAN_t *p_An); -+t_Error FmMacsecSetPTP(t_Handle h_FmMacsec, bool enable); -+ -+t_Error FmMacsecSetException(t_Handle h_FmMacsec, e_FmMacsecGlobalExceptions exception, uint32_t scId, bool enable); -+t_Error FmMacsecSetEvent(t_Handle h_FmMacsec, e_FmMacsecGlobalEvents event, uint32_t scId, bool enable); -+ -+ -+ -+#endif /* __FM_MACSEC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_guest.c -@@ -0,0 +1,59 @@ -+/* -+ * Copyright 2008-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/****************************************************************************** -+ @File fm_macsec.c -+ -+ @Description FM MACSEC driver routines implementation. -+*//***************************************************************************/ -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "xx_ext.h" -+#include "string_ext.h" -+#include "sprint_ext.h" -+#include "debug_ext.h" -+#include "fm_macsec.h" -+ -+ -+/****************************************/ -+/* static functions */ -+/****************************************/ -+ -+/****************************************/ -+/* API Init unit functions */ -+/****************************************/ -+t_Handle FM_MACSEC_GUEST_Config(t_FmMacsecParams *p_FmMacsecParam) -+{ -+ UNUSED(p_FmMacsecParam); -+ return NULL; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_master.c -@@ -0,0 +1,1031 @@ -+/* -+ * Copyright 2008-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/****************************************************************************** -+ @File fm_macsec.c -+ -+ @Description FM MACSEC driver routines implementation. -+*//***************************************************************************/ -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "xx_ext.h" -+#include "string_ext.h" -+#include "sprint_ext.h" -+#include "fm_mac_ext.h" -+ -+#include "fm_macsec_master.h" -+ -+ -+extern uint16_t FM_MAC_GetMaxFrameLength(t_Handle FmMac); -+ -+ -+/****************************************/ -+/* static functions */ -+/****************************************/ -+static t_Error CheckFmMacsecParameters(t_FmMacsec *p_FmMacsec) -+{ -+ if (!p_FmMacsec->f_Exception) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceptions callback not provided")); -+ -+ return E_OK; -+} -+ -+static void UnimplementedIsr(t_Handle h_Arg, uint32_t id) -+{ -+ UNUSED(h_Arg); UNUSED(id); -+ -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Unimplemented Isr!")); -+} -+ -+static void MacsecEventIsr(t_Handle h_FmMacsec) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ uint32_t events,event,i; -+ -+ SANITY_CHECK_RETURN(p_FmMacsec, E_INVALID_HANDLE); -+ -+ events = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->evr); -+ events |= GET_UINT32(p_FmMacsec->p_FmMacsecRegs->ever); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->evr,events); -+ -+ for (i=0; iintrMng[event].f_Isr(p_FmMacsec->intrMng[event].h_SrcHandle, i); -+ } -+} -+ -+static void MacsecErrorIsr(t_Handle h_FmMacsec) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ uint32_t errors,error,i; -+ -+ SANITY_CHECK_RETURN(p_FmMacsec, E_INVALID_HANDLE); -+ -+ errors = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->err); -+ errors |= GET_UINT32(p_FmMacsec->p_FmMacsecRegs->erer); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->err,errors); -+ -+ for (i=0; iintrMng[error].f_Isr(p_FmMacsec->intrMng[error].h_SrcHandle, i); -+ } -+ -+ if (errors & FM_MACSEC_EX_ECC) -+ { -+ uint8_t eccType; -+ uint32_t tmpReg; -+ -+ tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->meec); -+ ASSERT_COND(tmpReg & MECC_CAP); -+ eccType = (uint8_t)((tmpReg & MECC_CET) >> MECC_CET_SHIFT); -+ -+ if (!eccType && (p_FmMacsec->userExceptions & FM_MACSEC_USER_EX_SINGLE_BIT_ECC)) -+ p_FmMacsec->f_Exception(p_FmMacsec->h_App,e_FM_MACSEC_EX_SINGLE_BIT_ECC); -+ else if (eccType && (p_FmMacsec->userExceptions & FM_MACSEC_USER_EX_MULTI_BIT_ECC)) -+ p_FmMacsec->f_Exception(p_FmMacsec->h_App,e_FM_MACSEC_EX_MULTI_BIT_ECC); -+ else -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->meec,tmpReg); -+ } -+} -+ -+static t_Error MacsecInit(t_Handle h_FmMacsec) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_FmMacsecDriverParam *p_FmMacsecDriverParam = NULL; -+ uint32_t tmpReg,i,macId; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ CHECK_INIT_PARAMETERS(p_FmMacsec, CheckFmMacsecParameters); -+ -+ p_FmMacsecDriverParam = p_FmMacsec->p_FmMacsecDriverParam; -+ -+ for (i=0;iintrMng[i].f_Isr = UnimplementedIsr; -+ -+ tmpReg = 0; -+ tmpReg |= (p_FmMacsecDriverParam->changedTextWithNoEncryptDeliverUncontrolled << CFG_UECT_SHIFT)| -+ (p_FmMacsecDriverParam->onlyScbIsSetDeliverUncontrolled << CFG_ESCBT_SHIFT) | -+ (p_FmMacsecDriverParam->unknownSciTreatMode << CFG_USFT_SHIFT) | -+ (p_FmMacsecDriverParam->invalidTagsDeliverUncontrolled << CFG_ITT_SHIFT) | -+ (p_FmMacsecDriverParam->encryptWithNoChangedTextDiscardUncontrolled << CFG_KFT_SHIFT) | -+ (p_FmMacsecDriverParam->untagTreatMode << CFG_UFT_SHIFT) | -+ (p_FmMacsecDriverParam->keysUnreadable << CFG_KSS_SHIFT) | -+ (p_FmMacsecDriverParam->reservedSc0 << CFG_S0I_SHIFT) | -+ (p_FmMacsecDriverParam->byPassMode << CFG_BYPN_SHIFT); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->cfg, tmpReg); -+ -+ tmpReg = FM_MAC_GetMaxFrameLength(p_FmMacsec->h_FmMac); -+ /* At least Ethernet FCS (4 bytes) overhead must be subtracted from MFL. -+ * In addition, the SCI (8 bytes) overhead might be subtracted as well. */ -+ tmpReg -= p_FmMacsecDriverParam->mflSubtract; -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->mfl, tmpReg); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->tpnet, p_FmMacsecDriverParam->pnExhThr); -+ -+ if (!p_FmMacsec->userExceptions) -+ p_FmMacsec->exceptions &= ~FM_MACSEC_EX_ECC; -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->erer, p_FmMacsec->exceptions); -+ -+ p_FmMacsec->numRxScAvailable = NUM_OF_RX_SC; -+ if (p_FmMacsecDriverParam->reservedSc0) -+ p_FmMacsec->numRxScAvailable --; -+ p_FmMacsec->numTxScAvailable = NUM_OF_TX_SC; -+ -+ XX_Free(p_FmMacsecDriverParam); -+ p_FmMacsec->p_FmMacsecDriverParam = NULL; -+ -+ FM_MAC_GetId(p_FmMacsec->h_FmMac, &macId); -+ FmRegisterIntr(p_FmMacsec->h_Fm, -+ e_FM_MOD_MACSEC, -+ (uint8_t)macId, -+ e_FM_INTR_TYPE_NORMAL, -+ MacsecEventIsr, -+ p_FmMacsec); -+ -+ FmRegisterIntr(p_FmMacsec->h_Fm, -+ e_FM_MOD_MACSEC, -+ 0, -+ e_FM_INTR_TYPE_ERR, -+ MacsecErrorIsr, -+ p_FmMacsec); -+ -+ return E_OK; -+} -+ -+static t_Error MacsecFree(t_Handle h_FmMacsec) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ uint32_t macId; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ FM_MAC_GetId(p_FmMacsec->h_FmMac, &macId); -+ FmUnregisterIntr(p_FmMacsec->h_Fm, -+ e_FM_MOD_MACSEC, -+ (uint8_t)macId, -+ e_FM_INTR_TYPE_NORMAL); -+ -+ FmUnregisterIntr(p_FmMacsec->h_Fm, -+ e_FM_MOD_MACSEC, -+ 0, -+ e_FM_INTR_TYPE_ERR); -+ -+ if (p_FmMacsec->rxScSpinLock) -+ XX_FreeSpinlock(p_FmMacsec->rxScSpinLock); -+ if (p_FmMacsec->txScSpinLock) -+ XX_FreeSpinlock(p_FmMacsec->txScSpinLock); -+ -+ XX_Free(p_FmMacsec); -+ -+ return E_OK; -+} -+ -+static t_Error MacsecConfigUnknownSciFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUnknownSciFrameTreatment treatMode) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ p_FmMacsec->p_FmMacsecDriverParam->unknownSciTreatMode = treatMode; -+ -+ return E_OK; -+} -+ -+static t_Error MacsecConfigInvalidTagsFrameTreatment(t_Handle h_FmMacsec, bool deliverUncontrolled) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ p_FmMacsec->p_FmMacsecDriverParam->invalidTagsDeliverUncontrolled = deliverUncontrolled; -+ -+ return E_OK; -+} -+ -+static t_Error MacsecConfigChangedTextWithNoEncryptFrameTreatment(t_Handle h_FmMacsec, bool deliverUncontrolled) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ p_FmMacsec->p_FmMacsecDriverParam->changedTextWithNoEncryptDeliverUncontrolled = deliverUncontrolled; -+ -+ return E_OK; -+} -+ -+static t_Error MacsecConfigOnlyScbIsSetFrameTreatment(t_Handle h_FmMacsec, bool deliverUncontrolled) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ p_FmMacsec->p_FmMacsecDriverParam->onlyScbIsSetDeliverUncontrolled = deliverUncontrolled; -+ -+ return E_OK; -+} -+ -+static t_Error MacsecConfigEncryptWithNoChangedTextFrameTreatment(t_Handle h_FmMacsec, bool discardUncontrolled) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ p_FmMacsec->p_FmMacsecDriverParam->encryptWithNoChangedTextDiscardUncontrolled = discardUncontrolled; -+ -+ return E_OK; -+} -+ -+static t_Error MacsecConfigUntagFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUntagFrameTreatment treatMode) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ p_FmMacsec->p_FmMacsecDriverParam->untagTreatMode = treatMode; -+ -+ return E_OK; -+} -+ -+static t_Error MacsecConfigPnExhaustionThreshold(t_Handle h_FmMacsec, uint32_t pnExhThr) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ p_FmMacsec->p_FmMacsecDriverParam->pnExhThr = pnExhThr; -+ -+ return E_OK; -+} -+ -+static t_Error MacsecConfigKeysUnreadable(t_Handle h_FmMacsec) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ p_FmMacsec->p_FmMacsecDriverParam->keysUnreadable = TRUE; -+ -+ return E_OK; -+} -+ -+static t_Error MacsecConfigSectagWithoutSCI(t_Handle h_FmMacsec) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ p_FmMacsec->p_FmMacsecDriverParam->sectagOverhead -= MACSEC_SCI_SIZE; -+ p_FmMacsec->p_FmMacsecDriverParam->mflSubtract += MACSEC_SCI_SIZE; -+ -+ return E_OK; -+} -+ -+static t_Error MacsecConfigException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ uint32_t bitMask = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ GET_USER_EXCEPTION_FLAG(bitMask, exception); -+ if (bitMask) -+ { -+ if (enable) -+ p_FmMacsec->userExceptions |= bitMask; -+ else -+ p_FmMacsec->userExceptions &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); -+ -+ return E_OK; -+} -+ -+static t_Error MacsecGetRevision(t_Handle h_FmMacsec, uint32_t *p_MacsecRevision) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ *p_MacsecRevision = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->ip_rev1); -+ -+ return E_OK; -+} -+ -+static t_Error MacsecEnable(t_Handle h_FmMacsec) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ uint32_t tmpReg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->cfg); -+ tmpReg |= CFG_BYPN; -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->cfg,tmpReg); -+ -+ return E_OK; -+} -+ -+static t_Error MacsecDisable(t_Handle h_FmMacsec) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ uint32_t tmpReg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->cfg); -+ tmpReg &= ~CFG_BYPN; -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->cfg,tmpReg); -+ -+ return E_OK; -+} -+ -+static t_Error MacsecSetException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ uint32_t bitMask; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ GET_USER_EXCEPTION_FLAG(bitMask, exception); -+ if (bitMask) -+ { -+ if (enable) -+ p_FmMacsec->userExceptions |= bitMask; -+ else -+ p_FmMacsec->userExceptions &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); -+ -+ if (!p_FmMacsec->userExceptions) -+ p_FmMacsec->exceptions &= ~FM_MACSEC_EX_ECC; -+ else -+ p_FmMacsec->exceptions |= FM_MACSEC_EX_ECC; -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->erer, p_FmMacsec->exceptions); -+ -+ return E_OK; -+} -+ -+static void InitFmMacsecControllerDriver(t_FmMacsecControllerDriver *p_FmMacsecControllerDriver) -+{ -+ p_FmMacsecControllerDriver->f_FM_MACSEC_Init = MacsecInit; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_Free = MacsecFree; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUnknownSciFrameTreatment = MacsecConfigUnknownSciFrameTreatment; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigInvalidTagsFrameTreatment = MacsecConfigInvalidTagsFrameTreatment; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment = MacsecConfigEncryptWithNoChangedTextFrameTreatment; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUntagFrameTreatment = MacsecConfigUntagFrameTreatment; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigChangedTextWithNoEncryptFrameTreatment = MacsecConfigChangedTextWithNoEncryptFrameTreatment; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigOnlyScbIsSetFrameTreatment = MacsecConfigOnlyScbIsSetFrameTreatment; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigPnExhaustionThreshold = MacsecConfigPnExhaustionThreshold; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigKeysUnreadable = MacsecConfigKeysUnreadable; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigSectagWithoutSCI = MacsecConfigSectagWithoutSCI; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigException = MacsecConfigException; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_GetRevision = MacsecGetRevision; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_Enable = MacsecEnable; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_Disable = MacsecDisable; -+ p_FmMacsecControllerDriver->f_FM_MACSEC_SetException = MacsecSetException; -+} -+ -+/****************************************/ -+/* Inter-Module functions */ -+/****************************************/ -+ -+void FmMacsecRegisterIntr(t_Handle h_FmMacsec, -+ e_FmMacsecEventModules module, -+ uint8_t modId, -+ e_FmIntrType intrType, -+ void (*f_Isr) (t_Handle h_Arg, uint32_t id), -+ t_Handle h_Arg) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ uint8_t event= 0; -+ -+ SANITY_CHECK_RETURN(p_FmMacsec, E_INVALID_HANDLE); -+ -+ GET_MACSEC_MODULE_EVENT(module, modId, intrType, event); -+ -+ ASSERT_COND(event != e_FM_MACSEC_EV_DUMMY_LAST); -+ p_FmMacsec->intrMng[event].f_Isr = f_Isr; -+ p_FmMacsec->intrMng[event].h_SrcHandle = h_Arg; -+} -+ -+void FmMacsecUnregisterIntr(t_Handle h_FmMacsec, -+ e_FmMacsecEventModules module, -+ uint8_t modId, -+ e_FmIntrType intrType) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ uint8_t event= 0; -+ -+ SANITY_CHECK_RETURN(p_FmMacsec, E_INVALID_HANDLE); -+ -+ GET_MACSEC_MODULE_EVENT(module, modId,intrType, event); -+ -+ ASSERT_COND(event != e_FM_MACSEC_EV_DUMMY_LAST); -+ p_FmMacsec->intrMng[event].f_Isr = NULL; -+ p_FmMacsec->intrMng[event].h_SrcHandle = NULL; -+} -+ -+t_Error FmMacsecAllocScs(t_Handle h_FmMacsec, e_ScType type, bool isPtp, uint32_t numOfScs, uint32_t *p_ScIds) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ bool *p_ScTable; -+ uint32_t *p_ScAvailable,i; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_ScIds, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(numOfScs, E_INVALID_HANDLE); -+ -+ if (type == e_SC_RX) -+ { -+ p_ScTable = (bool *)p_FmMacsec->rxScTable; -+ p_ScAvailable = &p_FmMacsec->numRxScAvailable; -+ i = (NUM_OF_RX_SC - 1); -+ } -+ else -+ { -+ p_ScTable = (bool *)p_FmMacsec->txScTable; -+ p_ScAvailable = &p_FmMacsec->numTxScAvailable; -+ i = (NUM_OF_TX_SC - 1); -+ -+ } -+ if (*p_ScAvailable < numOfScs) -+ RETURN_ERROR(MINOR, E_NOT_AVAILABLE, ("Not enough SCs available")); -+ -+ if (isPtp) -+ { -+ i = 0; -+ if (p_ScTable[i]) -+ RETURN_ERROR(MINOR, E_NOT_AVAILABLE, ("Sc 0 Not available")); -+ } -+ -+ for (;numOfScs;i--) -+ { -+ if (p_ScTable[i]) -+ continue; -+ numOfScs --; -+ (*p_ScAvailable)--; -+ p_ScIds[numOfScs] = i; -+ p_ScTable[i] = TRUE; -+ } -+ -+ return err; -+} -+ -+t_Error FmMacsecFreeScs(t_Handle h_FmMacsec, e_ScType type, uint32_t numOfScs, uint32_t *p_ScIds) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ bool *p_ScTable; -+ uint32_t *p_ScAvailable,maxNumOfSc,i; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_ScIds, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(numOfScs, E_INVALID_HANDLE); -+ -+ if (type == e_SC_RX) -+ { -+ p_ScTable = (bool *)p_FmMacsec->rxScTable; -+ p_ScAvailable = &p_FmMacsec->numRxScAvailable; -+ maxNumOfSc = NUM_OF_RX_SC; -+ } -+ else -+ { -+ p_ScTable = (bool *)p_FmMacsec->txScTable; -+ p_ScAvailable = &p_FmMacsec->numTxScAvailable; -+ maxNumOfSc = NUM_OF_TX_SC; -+ } -+ -+ if ((*p_ScAvailable + numOfScs) > maxNumOfSc) -+ RETURN_ERROR(MINOR, E_FULL, ("Too much SCs")); -+ -+ for (i=0;ip_FmMacsecRegs->cfg); -+ if (enable && (tmpReg & CFG_S0I)) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("MACSEC already in point-to-point mode")); -+ -+ if (enable) -+ tmpReg |= CFG_S0I; -+ else -+ tmpReg &= ~CFG_S0I; -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->cfg, tmpReg); -+ -+ return E_OK; -+} -+ -+t_Error FmMacsecCreateRxSc(t_Handle h_FmMacsec, t_RxScParams *p_RxScParams) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ uint32_t tmpReg = 0, intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_RxScParams, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_RxScParams->scId < NUM_OF_RX_SC, E_INVALID_HANDLE); -+ -+ intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, p_RxScParams->scId); -+ tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsccfg); -+ if (tmpReg & RX_SCCFG_SCI_EN_MASK) -+ { -+ XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags); -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Rx Sc %d must be disable",p_RxScParams->scId)); -+ } -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsci1h, GET_SCI_FIRST_HALF(p_RxScParams->sci)); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsci2h, GET_SCI_SECOND_HALF(p_RxScParams->sci)); -+ tmpReg |= ((p_RxScParams->replayProtect << RX_SCCFG_RP_SHIFT) & RX_SCCFG_RP_MASK); -+ tmpReg |= ((p_RxScParams->validateFrames << RX_SCCFG_VF_SHIFT) & RX_SCCFG_VF_MASK); -+ tmpReg |= ((p_RxScParams->confidentialityOffset << RX_SCCFG_CO_SHIFT) & RX_SCCFG_CO_MASK); -+ tmpReg |= RX_SCCFG_SCI_EN_MASK; -+ tmpReg |= (p_RxScParams->cipherSuite << RX_SCCFG_CS_SHIFT); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsccfg, tmpReg); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rpw, p_RxScParams->replayWindow); -+ -+ XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags); -+ -+ return err; -+} -+ -+t_Error FmMacsecDeleteRxSc(t_Handle h_FmMacsec, uint32_t scId) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ uint32_t tmpReg = 0, intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE); -+ -+ intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock); -+ -+ tmpReg &= ~RX_SCCFG_SCI_EN_MASK; -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, scId); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsccfg, tmpReg); -+ -+ XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags); -+ -+ return err; -+} -+ -+t_Error FmMacsecCreateTxSc(t_Handle h_FmMacsec, t_TxScParams *p_TxScParams) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ uint32_t tmpReg = 0, intFlags; -+ bool alwaysIncludeSCI = FALSE, useES = FALSE, useSCB = FALSE; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_TxScParams, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_TxScParams->scId < NUM_OF_TX_SC, E_INVALID_HANDLE); -+ -+ intFlags = XX_LockIntrSpinlock(p_FmMacsec->txScSpinLock); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsca, p_TxScParams->scId); -+ -+ tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->txsccfg); -+ if (tmpReg & TX_SCCFG_SCE_MASK) -+ { -+ XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags); -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Tx Sc %d must be disable",p_TxScParams->scId)); -+ } -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsci1h, GET_SCI_FIRST_HALF(p_TxScParams->sci)); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsci2h, GET_SCI_SECOND_HALF(p_TxScParams->sci)); -+ alwaysIncludeSCI = (p_TxScParams->sciInsertionMode == e_FM_MACSEC_SCI_INSERTION_MODE_EXPLICIT_SECTAG); -+ useES = (p_TxScParams->sciInsertionMode == e_FM_MACSEC_SCI_INSERTION_MODE_EXPLICIT_MAC_SA); -+ -+ tmpReg |= ((p_TxScParams->protectFrames << TX_SCCFG_PF_SHIFT) & TX_SCCFG_PF_MASK); -+ tmpReg |= ((alwaysIncludeSCI << TX_SCCFG_AIS_SHIFT) & TX_SCCFG_AIS_MASK); -+ tmpReg |= ((useES << TX_SCCFG_UES_SHIFT) & TX_SCCFG_UES_MASK); -+ tmpReg |= ((useSCB << TX_SCCFG_USCB_SHIFT) & TX_SCCFG_USCB_MASK); -+ tmpReg |= ((p_TxScParams->confidentialityEnable << TX_SCCFG_CE_SHIFT) & TX_SCCFG_CE_MASK); -+ tmpReg |= ((p_TxScParams->confidentialityOffset << TX_SCCFG_CO_SHIFT) & TX_SCCFG_CO_MASK); -+ tmpReg |= TX_SCCFG_SCE_MASK; -+ tmpReg |= (p_TxScParams->cipherSuite << TX_SCCFG_CS_SHIFT); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsccfg, tmpReg); -+ -+ XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags); -+ -+ return err; -+} -+ -+t_Error FmMacsecDeleteTxSc(t_Handle h_FmMacsec, uint32_t scId) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ uint32_t tmpReg = 0, intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_TX_SC, E_INVALID_HANDLE); -+ -+ intFlags = XX_LockIntrSpinlock(p_FmMacsec->txScSpinLock); -+ -+ tmpReg &= ~TX_SCCFG_SCE_MASK; -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsca, scId); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsccfg, tmpReg); -+ -+ XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags); -+ -+ return err; -+} -+ -+t_Error FmMacsecCreateRxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecAN_t an, uint32_t lowestPn, macsecSAKey_t key) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ uint32_t tmpReg = 0, intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_RX_SC, E_INVALID_HANDLE); -+ -+ intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, scId); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsanpn, DEFAULT_initNextPn); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsalpn, lowestPn); -+ MemCpy8((void*)p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsak, key, sizeof(macsecSAKey_t)); -+ -+ tmpReg |= RX_SACFG_ACTIVE; -+ tmpReg |= ((an << RX_SACFG_AN_SHIFT) & RX_SACFG_AN_MASK); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsacs, tmpReg); -+ -+ XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags); -+ -+ return err; -+} -+ -+t_Error FmMacsecCreateTxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecSAKey_t key) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ uint32_t tmpReg = 0, intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_TX_SC, E_INVALID_HANDLE); -+ -+ intFlags = XX_LockIntrSpinlock(p_FmMacsec->txScSpinLock); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsca, scId); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecTxScSa[saId].txsanpn, DEFAULT_initNextPn); -+ MemCpy8((void*)p_FmMacsec->p_FmMacsecRegs->fmMacsecTxScSa[saId].txsak, key, sizeof(macsecSAKey_t)); -+ -+ tmpReg |= TX_SACFG_ACTIVE; -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecTxScSa[saId].txsacs, tmpReg); -+ -+ XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags); -+ -+ return err; -+} -+ -+t_Error FmMacsecDeleteRxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ uint32_t tmpReg = 0, i, intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_RX_SC, E_INVALID_HANDLE); -+ -+ intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, scId); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsanpn, 0x0); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsalpn, 0x0); -+ for (i=0; i<4; i++) -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsak[i], 0x0); -+ -+ tmpReg |= RX_SACFG_ACTIVE; -+ tmpReg &= ~RX_SACFG_EN_MASK; -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsacs, tmpReg); -+ -+ XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags); -+ -+ return err; -+} -+ -+t_Error FmMacsecDeleteTxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ uint32_t tmpReg = 0, i, intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_TX_SC, E_INVALID_HANDLE); -+ -+ intFlags = XX_LockIntrSpinlock(p_FmMacsec->txScSpinLock); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsca, scId); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecTxScSa[saId].txsanpn, 0x0); -+ for (i=0; i<4; i++) -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecTxScSa[saId].txsak[i], 0x0); -+ -+ tmpReg |= TX_SACFG_ACTIVE; -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecTxScSa[saId].txsacs, tmpReg); -+ -+ XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags); -+ -+ return err; -+} -+ -+t_Error FmMacsecRxSaSetReceive(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, bool enableReceive) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ uint32_t tmpReg = 0, intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_RX_SC, E_INVALID_HANDLE); -+ -+ intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, scId); -+ tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsacs); -+ if (enableReceive) -+ tmpReg |= RX_SACFG_EN_MASK; -+ else -+ tmpReg &= ~RX_SACFG_EN_MASK; -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsacs, tmpReg); -+ -+ XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags); -+ -+ return err; -+} -+ -+t_Error FmMacsecRxSaUpdateNextPn(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, uint32_t updtNextPN) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ uint32_t intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_RX_SC, E_INVALID_HANDLE); -+ -+ intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, scId); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsanpn, updtNextPN); -+ -+ XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags); -+ -+ return err; -+} -+ -+t_Error FmMacsecRxSaUpdateLowestPn(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, uint32_t updtLowestPN) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ uint32_t intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_RX_SC, E_INVALID_HANDLE); -+ -+ intFlags = XX_LockIntrSpinlock(p_FmMacsec->rxScSpinLock); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->rxsca, scId); -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->fmMacsecRxScSa[saId].rxsalpn, updtLowestPN); -+ -+ XX_UnlockIntrSpinlock(p_FmMacsec->rxScSpinLock, intFlags); -+ -+ return err; -+} -+ -+t_Error FmMacsecTxSaSetActive(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecAN_t an) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ uint32_t tmpReg = 0, intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(saId < NUM_OF_SA_PER_TX_SC, E_INVALID_HANDLE); -+ -+ intFlags = XX_LockIntrSpinlock(p_FmMacsec->txScSpinLock); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsca, scId); -+ -+ tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->txsccfg); -+ -+ tmpReg |= ((an << TX_SCCFG_AN_SHIFT) & TX_SCCFG_AN_MASK); -+ tmpReg |= ((saId << TX_SCCFG_ASA_SHIFT) & TX_SCCFG_ASA_MASK); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsccfg, tmpReg); -+ -+ XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags); -+ -+ return err; -+} -+ -+t_Error FmMacsecTxSaGetActive(t_Handle h_FmMacsec, uint32_t scId, macsecAN_t *p_An) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ t_Error err = E_OK; -+ uint32_t tmpReg = 0, intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(scId < NUM_OF_RX_SC, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_An, E_INVALID_HANDLE); -+ -+ intFlags = XX_LockIntrSpinlock(p_FmMacsec->txScSpinLock); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->txsca, scId); -+ -+ tmpReg = GET_UINT32(p_FmMacsec->p_FmMacsecRegs->txsccfg); -+ -+ XX_UnlockIntrSpinlock(p_FmMacsec->txScSpinLock, intFlags); -+ -+ *p_An = (macsecAN_t)((tmpReg & TX_SCCFG_AN_MASK) >> TX_SCCFG_AN_SHIFT); -+ -+ return err; -+} -+ -+t_Error FmMacsecSetException(t_Handle h_FmMacsec, e_FmMacsecGlobalExceptions exception, uint32_t scId, bool enable) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ uint32_t bitMask; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ GET_EXCEPTION_FLAG(bitMask, exception, scId); -+ if (bitMask) -+ { -+ if (enable) -+ p_FmMacsec->exceptions |= bitMask; -+ else -+ p_FmMacsec->exceptions &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->erer, p_FmMacsec->exceptions); -+ -+ return E_OK; -+} -+ -+t_Error FmMacsecSetEvent(t_Handle h_FmMacsec, e_FmMacsecGlobalEvents event, uint32_t scId, bool enable) -+{ -+ t_FmMacsec *p_FmMacsec = (t_FmMacsec*)h_FmMacsec; -+ uint32_t bitMask; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsec->p_FmMacsecDriverParam, E_INVALID_HANDLE); -+ -+ GET_EVENT_FLAG(bitMask, event, scId); -+ if (bitMask) -+ { -+ if (enable) -+ p_FmMacsec->events |= bitMask; -+ else -+ p_FmMacsec->events &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined event")); -+ -+ WRITE_UINT32(p_FmMacsec->p_FmMacsecRegs->ever, p_FmMacsec->events); -+ -+ return E_OK; -+} -+ -+/****************************************/ -+/* API Init unit functions */ -+/****************************************/ -+t_Handle FM_MACSEC_MASTER_Config(t_FmMacsecParams *p_FmMacsecParam) -+{ -+ t_FmMacsec *p_FmMacsec; -+ uint32_t macId; -+ -+ /* Allocate FM MACSEC structure */ -+ p_FmMacsec = (t_FmMacsec *) XX_Malloc(sizeof(t_FmMacsec)); -+ if (!p_FmMacsec) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC driver structure")); -+ return NULL; -+ } -+ memset(p_FmMacsec, 0, sizeof(t_FmMacsec)); -+ InitFmMacsecControllerDriver(&p_FmMacsec->fmMacsecControllerDriver); -+ -+ /* Allocate the FM MACSEC driver's parameters structure */ -+ p_FmMacsec->p_FmMacsecDriverParam = (t_FmMacsecDriverParam *)XX_Malloc(sizeof(t_FmMacsecDriverParam)); -+ if (!p_FmMacsec->p_FmMacsecDriverParam) -+ { -+ XX_Free(p_FmMacsec); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC driver parameters")); -+ return NULL; -+ } -+ memset(p_FmMacsec->p_FmMacsecDriverParam, 0, sizeof(t_FmMacsecDriverParam)); -+ -+ /* Initialize FM MACSEC parameters which will be kept by the driver */ -+ p_FmMacsec->h_Fm = p_FmMacsecParam->h_Fm; -+ p_FmMacsec->h_FmMac = p_FmMacsecParam->nonGuestParams.h_FmMac; -+ p_FmMacsec->p_FmMacsecRegs = (t_FmMacsecRegs *)UINT_TO_PTR(p_FmMacsecParam->nonGuestParams.baseAddr); -+ p_FmMacsec->f_Exception = p_FmMacsecParam->nonGuestParams.f_Exception; -+ p_FmMacsec->h_App = p_FmMacsecParam->nonGuestParams.h_App; -+ p_FmMacsec->userExceptions = DEFAULT_userExceptions; -+ p_FmMacsec->exceptions = DEFAULT_exceptions; -+ p_FmMacsec->events = DEFAULT_events; -+ p_FmMacsec->rxScSpinLock = XX_InitSpinlock(); -+ p_FmMacsec->txScSpinLock = XX_InitSpinlock(); -+ -+ /* Initialize FM MACSEC driver parameters parameters (for initialization phase only) */ -+ p_FmMacsec->p_FmMacsecDriverParam->unknownSciTreatMode = DEFAULT_unknownSciFrameTreatment; -+ p_FmMacsec->p_FmMacsecDriverParam->invalidTagsDeliverUncontrolled = DEFAULT_invalidTagsFrameTreatment; -+ p_FmMacsec->p_FmMacsecDriverParam->encryptWithNoChangedTextDiscardUncontrolled = DEFAULT_encryptWithNoChangedTextFrameTreatment; -+ p_FmMacsec->p_FmMacsecDriverParam->untagTreatMode = DEFAULT_untagFrameTreatment; -+ p_FmMacsec->p_FmMacsecDriverParam->keysUnreadable = DEFAULT_keysUnreadable; -+ p_FmMacsec->p_FmMacsecDriverParam->reservedSc0 = DEFAULT_sc0ReservedForPTP; -+ p_FmMacsec->p_FmMacsecDriverParam->byPassMode = !DEFAULT_normalMode; -+ p_FmMacsec->p_FmMacsecDriverParam->pnExhThr = DEFAULT_pnExhThr; -+ p_FmMacsec->p_FmMacsecDriverParam->sectagOverhead = DEFAULT_sectagOverhead; -+ p_FmMacsec->p_FmMacsecDriverParam->mflSubtract = DEFAULT_mflSubtract; -+ /* build the FM MACSEC master IPC address */ -+ memset(p_FmMacsec->fmMacsecModuleName, 0, (sizeof(char))*MODULE_NAME_SIZE); -+ FM_MAC_GetId(p_FmMacsec->h_FmMac,&macId); -+ if (Sprint (p_FmMacsec->fmMacsecModuleName, "FM-%d-MAC-%d-MACSEC-Master", -+ FmGetId(p_FmMacsec->h_Fm),macId) != 24) -+ { -+ XX_Free(p_FmMacsec->p_FmMacsecDriverParam); -+ XX_Free(p_FmMacsec); -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Sprint failed")); -+ return NULL; -+ } -+ return p_FmMacsec; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_master.h -@@ -0,0 +1,479 @@ -+/* -+ * Copyright 2008-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/****************************************************************************** -+ @File fm_macsec_master.h -+ -+ @Description FM MACSEC internal structures and definitions. -+*//***************************************************************************/ -+#ifndef __FM_MACSEC_MASTER_H -+#define __FM_MACSEC_MASTER_H -+ -+#include "error_ext.h" -+#include "std_ext.h" -+ -+#include "fm_macsec.h" -+ -+ -+#define MACSEC_ICV_SIZE 16 -+#define MACSEC_SECTAG_SIZE 16 -+#define MACSEC_SCI_SIZE 8 -+#define MACSEC_FCS_SIZE 4 -+ -+/**************************************************************************//** -+ @Description Exceptions -+*//***************************************************************************/ -+ -+#define FM_MACSEC_EX_TX_SC_0 0x80000000 -+#define FM_MACSEC_EX_TX_SC(sc) (FM_MACSEC_EX_TX_SC_0 >> (sc)) -+#define FM_MACSEC_EX_ECC 0x00000001 -+ -+#define GET_EXCEPTION_FLAG(bitMask, exception, id) switch (exception){ \ -+ case e_FM_MACSEC_EX_TX_SC: \ -+ bitMask = FM_MACSEC_EX_TX_SC(id); break; \ -+ case e_FM_MACSEC_EX_ECC: \ -+ bitMask = FM_MACSEC_EX_ECC; break; \ -+ default: bitMask = 0;break;} -+ -+#define FM_MACSEC_USER_EX_SINGLE_BIT_ECC 0x80000000 -+#define FM_MACSEC_USER_EX_MULTI_BIT_ECC 0x40000000 -+ -+#define GET_USER_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \ -+ case e_FM_MACSEC_EX_SINGLE_BIT_ECC: \ -+ bitMask = FM_MACSEC_USER_EX_SINGLE_BIT_ECC; break; \ -+ case e_FM_MACSEC_EX_MULTI_BIT_ECC: \ -+ bitMask = FM_MACSEC_USER_EX_MULTI_BIT_ECC; break; \ -+ default: bitMask = 0;break;} -+ -+/**************************************************************************//** -+ @Description Events -+*//***************************************************************************/ -+ -+#define FM_MACSEC_EV_TX_SC_0_NEXT_PN 0x80000000 -+#define FM_MACSEC_EV_TX_SC_NEXT_PN(sc) (FM_MACSEC_EV_TX_SC_0_NEXT_PN >> (sc)) -+ -+#define GET_EVENT_FLAG(bitMask, event, id) switch (event){ \ -+ case e_FM_MACSEC_EV_TX_SC_NEXT_PN: \ -+ bitMask = FM_MACSEC_EV_TX_SC_NEXT_PN(id); break; \ -+ default: bitMask = 0;break;} -+ -+/**************************************************************************//** -+ @Description Defaults -+*//***************************************************************************/ -+#define DEFAULT_userExceptions (FM_MACSEC_USER_EX_SINGLE_BIT_ECC |\ -+ FM_MACSEC_USER_EX_MULTI_BIT_ECC) -+ -+#define DEFAULT_exceptions (FM_MACSEC_EX_TX_SC(0) |\ -+ FM_MACSEC_EX_TX_SC(1) |\ -+ FM_MACSEC_EX_TX_SC(2) |\ -+ FM_MACSEC_EX_TX_SC(3) |\ -+ FM_MACSEC_EX_TX_SC(4) |\ -+ FM_MACSEC_EX_TX_SC(5) |\ -+ FM_MACSEC_EX_TX_SC(6) |\ -+ FM_MACSEC_EX_TX_SC(7) |\ -+ FM_MACSEC_EX_TX_SC(8) |\ -+ FM_MACSEC_EX_TX_SC(9) |\ -+ FM_MACSEC_EX_TX_SC(10) |\ -+ FM_MACSEC_EX_TX_SC(11) |\ -+ FM_MACSEC_EX_TX_SC(12) |\ -+ FM_MACSEC_EX_TX_SC(13) |\ -+ FM_MACSEC_EX_TX_SC(14) |\ -+ FM_MACSEC_EX_TX_SC(15) |\ -+ FM_MACSEC_EX_ECC ) -+ -+#define DEFAULT_events (FM_MACSEC_EV_TX_SC_NEXT_PN(0) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(1) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(2) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(3) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(4) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(5) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(6) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(7) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(8) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(9) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(10) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(11) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(12) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(13) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(14) |\ -+ FM_MACSEC_EV_TX_SC_NEXT_PN(15) ) -+ -+#define DEFAULT_unknownSciFrameTreatment e_FM_MACSEC_UNKNOWN_SCI_FRAME_TREATMENT_DISCARD_BOTH -+#define DEFAULT_invalidTagsFrameTreatment FALSE -+#define DEFAULT_encryptWithNoChangedTextFrameTreatment FALSE -+#define DEFAULT_untagFrameTreatment e_FM_MACSEC_UNTAG_FRAME_TREATMENT_DELIVER_UNCONTROLLED_DISCARD_CONTROLLED -+#define DEFAULT_changedTextWithNoEncryptFrameTreatment FALSE -+#define DEFAULT_onlyScbIsSetFrameTreatment FALSE -+#define DEFAULT_keysUnreadable FALSE -+#define DEFAULT_normalMode TRUE -+#define DEFAULT_sc0ReservedForPTP FALSE -+#define DEFAULT_initNextPn 1 -+#define DEFAULT_pnExhThr 0xffffffff -+#define DEFAULT_sectagOverhead (MACSEC_ICV_SIZE + MACSEC_SECTAG_SIZE) -+#define DEFAULT_mflSubtract MACSEC_FCS_SIZE -+ -+ -+/**************************************************************************//** -+ @Description Memory Mapped Registers -+*//***************************************************************************/ -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+typedef _Packed struct -+{ -+ /* MACsec configuration */ -+ volatile uint32_t cfg; /**< MACsec configuration */ -+ volatile uint32_t et; /**< MACsec EtherType */ -+ volatile uint8_t res1[56]; /**< reserved */ -+ volatile uint32_t mfl; /**< Maximum Frame Length */ -+ volatile uint32_t tpnet; /**< TX Packet Number exhaustion threshold */ -+ volatile uint8_t res2[56]; /**< reserved */ -+ volatile uint32_t rxsca; /**< RX SC access select */ -+ volatile uint8_t res3[60]; /**< reserved */ -+ volatile uint32_t txsca; /**< TX SC access select */ -+ volatile uint8_t res4[60]; /**< reserved */ -+ -+ /* RX configuration, status and statistic */ -+ volatile uint32_t rxsci1h; /**< RX Secure Channel Identifier first half */ -+ volatile uint32_t rxsci2h; /**< RX Secure Channel Identifier second half */ -+ volatile uint8_t res5[8]; /**< reserved */ -+ volatile uint32_t ifio1hs; /**< ifInOctets first half Statistic */ -+ volatile uint32_t ifio2hs; /**< ifInOctets second half Statistic */ -+ volatile uint32_t ifiups; /**< ifInUcastPkts Statistic */ -+ volatile uint8_t res6[4]; /**< reserved */ -+ volatile uint32_t ifimps; /**< ifInMulticastPkts Statistic */ -+ volatile uint32_t ifibps; /**< ifInBroadcastPkts Statistic */ -+ volatile uint32_t rxsccfg; /**< RX Secure Channel configuration */ -+ volatile uint32_t rpw; /**< replayWindow */ -+ volatile uint8_t res7[16]; /**< reserved */ -+ volatile uint32_t inov1hs; /**< InOctetsValidated first half Statistic */ -+ volatile uint32_t inov2hs; /**< InOctetsValidated second half Statistic */ -+ volatile uint32_t inod1hs; /**< InOctetsDecrypted first half Statistic */ -+ volatile uint32_t inod2hs; /**< InOctetsDecrypted second half Statistic */ -+ volatile uint32_t rxscipus; /**< RX Secure Channel InPktsUnchecked Statistic */ -+ volatile uint32_t rxscipds; /**< RX Secure Channel InPktsDelayed Statistic */ -+ volatile uint32_t rxscipls; /**< RX Secure Channel InPktsLate Statistic */ -+ volatile uint8_t res8[4]; /**< reserved */ -+ volatile uint32_t rxaninuss[MAX_NUM_OF_SA_PER_SC]; /**< RX AN 0-3 InNotUsingSA Statistic */ -+ volatile uint32_t rxanipuss[MAX_NUM_OF_SA_PER_SC]; /**< RX AN 0-3 InPktsUnusedSA Statistic */ -+ _Packed struct -+ { -+ volatile uint32_t rxsacs; /**< RX Security Association configuration and status */ -+ volatile uint32_t rxsanpn; /**< RX Security Association nextPN */ -+ volatile uint32_t rxsalpn; /**< RX Security Association lowestPN */ -+ volatile uint32_t rxsaipos; /**< RX Security Association InPktsOK Statistic */ -+ volatile uint32_t rxsak[4]; /**< RX Security Association key (128 bit) */ -+ volatile uint32_t rxsah[4]; /**< RX Security Association hash (128 bit) */ -+ volatile uint32_t rxsaipis; /**< RX Security Association InPktsInvalid Statistic */ -+ volatile uint32_t rxsaipnvs; /**< RX Security Association InPktsNotValid Statistic */ -+ volatile uint8_t res9[8]; /**< reserved */ -+ } _PackedType fmMacsecRxScSa[NUM_OF_SA_PER_RX_SC]; -+ -+ /* TX configuration, status and statistic */ -+ volatile uint32_t txsci1h; /**< TX Secure Channel Identifier first half */ -+ volatile uint32_t txsci2h; /**< TX Secure Channel Identifier second half */ -+ volatile uint8_t res10[8]; /**< reserved */ -+ volatile uint32_t ifoo1hs; /**< ifOutOctets first half Statistic */ -+ volatile uint32_t ifoo2hs; /**< ifOutOctets second half Statistic */ -+ volatile uint32_t ifoups; /**< ifOutUcastPkts Statistic */ -+ volatile uint32_t opus; /**< OutPktsUntagged Statistic */ -+ volatile uint32_t ifomps; /**< ifOutMulticastPkts Statistic */ -+ volatile uint32_t ifobps; /**< ifOutBroadcastPkts Statistic */ -+ volatile uint32_t txsccfg; /**< TX Secure Channel configuration */ -+ volatile uint32_t optls; /**< OutPktsTooLong Statistic */ -+ volatile uint8_t res11[16]; /**< reserved */ -+ volatile uint32_t oop1hs; /**< OutOctetsProtected first half Statistic */ -+ volatile uint32_t oop2hs; /**< OutOctetsProtected second half Statistic */ -+ volatile uint32_t ooe1hs; /**< OutOctetsEncrypted first half Statistic */ -+ volatile uint32_t ooe2hs; /**< OutOctetsEncrypted second half Statistic */ -+ volatile uint8_t res12[48]; /**< reserved */ -+ _Packed struct -+ { -+ volatile uint32_t txsacs; /**< TX Security Association configuration and status */ -+ volatile uint32_t txsanpn; /**< TX Security Association nextPN */ -+ volatile uint32_t txsaopps; /**< TX Security Association OutPktsProtected Statistic */ -+ volatile uint32_t txsaopes; /**< TX Security Association OutPktsEncrypted Statistic */ -+ volatile uint32_t txsak[4]; /**< TX Security Association key (128 bit) */ -+ volatile uint32_t txsah[4]; /**< TX Security Association hash (128 bit) */ -+ volatile uint8_t res13[16]; /**< reserved */ -+ } _PackedType fmMacsecTxScSa[NUM_OF_SA_PER_TX_SC]; -+ volatile uint8_t res14[248]; /**< reserved */ -+ -+ /* Global configuration and status */ -+ volatile uint32_t ip_rev1; /**< MACsec IP Block Revision 1 register */ -+ volatile uint32_t ip_rev2; /**< MACsec IP Block Revision 2 register */ -+ volatile uint32_t evr; /**< MACsec Event Register */ -+ volatile uint32_t ever; /**< MACsec Event Enable Register */ -+ volatile uint32_t evfr; /**< MACsec Event Force Register */ -+ volatile uint32_t err; /**< MACsec Error Register */ -+ volatile uint32_t erer; /**< MACsec Error Enable Register */ -+ volatile uint32_t erfr; /**< MACsec Error Force Register */ -+ volatile uint8_t res15[40]; /**< reserved */ -+ volatile uint32_t meec; /**< MACsec Memory ECC Error Capture Register */ -+ volatile uint32_t idle; /**< MACsec Idle status Register */ -+ volatile uint8_t res16[184]; /**< reserved */ -+ /* DEBUG */ -+ volatile uint32_t rxec; /**< MACsec RX error capture Register */ -+ volatile uint8_t res17[28]; /**< reserved */ -+ volatile uint32_t txec; /**< MACsec TX error capture Register */ -+ volatile uint8_t res18[220]; /**< reserved */ -+ -+ /* Macsec Rx global statistic */ -+ volatile uint32_t ifiocp1hs; /**< ifInOctetsCp first half Statistic */ -+ volatile uint32_t ifiocp2hs; /**< ifInOctetsCp second half Statistic */ -+ volatile uint32_t ifiupcps; /**< ifInUcastPktsCp Statistic */ -+ volatile uint8_t res19[4]; /**< reserved */ -+ volatile uint32_t ifioup1hs; /**< ifInOctetsUp first half Statistic */ -+ volatile uint32_t ifioup2hs; /**< ifInOctetsUp second half Statistic */ -+ volatile uint32_t ifiupups; /**< ifInUcastPktsUp Statistic */ -+ volatile uint8_t res20[4]; /**< reserved */ -+ volatile uint32_t ifimpcps; /**< ifInMulticastPktsCp Statistic */ -+ volatile uint32_t ifibpcps; /**< ifInBroadcastPktsCp Statistic */ -+ volatile uint32_t ifimpups; /**< ifInMulticastPktsUp Statistic */ -+ volatile uint32_t ifibpups; /**< ifInBroadcastPktsUp Statistic */ -+ volatile uint32_t ipwts; /**< InPktsWithoutTag Statistic */ -+ volatile uint32_t ipkays; /**< InPktsKaY Statistic */ -+ volatile uint32_t ipbts; /**< InPktsBadTag Statistic */ -+ volatile uint32_t ipsnfs; /**< InPktsSCINotFound Statistic */ -+ volatile uint32_t ipuecs; /**< InPktsUnsupportedEC Statistic */ -+ volatile uint32_t ipescbs; /**< InPktsEponSingleCopyBroadcast Statistic */ -+ volatile uint32_t iptls; /**< InPktsTooLong Statistic */ -+ volatile uint8_t res21[52]; /**< reserved */ -+ -+ /* Macsec Tx global statistic */ -+ volatile uint32_t opds; /**< OutPktsDiscarded Statistic */ -+#if (DPAA_VERSION >= 11) -+ volatile uint8_t res22[124]; /**< reserved */ -+ _Packed struct -+ { -+ volatile uint32_t rxsak[8]; /**< RX Security Association key (128/256 bit) */ -+ volatile uint8_t res23[32]; /**< reserved */ -+ } _PackedType rxScSaKey[NUM_OF_SA_PER_RX_SC]; -+ _Packed struct -+ { -+ volatile uint32_t txsak[8]; /**< TX Security Association key (128/256 bit) */ -+ volatile uint8_t res24[32]; /**< reserved */ -+ } _PackedType txScSaKey[NUM_OF_SA_PER_TX_SC]; -+#endif /* (DPAA_VERSION >= 11) */ -+} _PackedType t_FmMacsecRegs; -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+ -+/**************************************************************************//** -+ @Description General defines -+*//***************************************************************************/ -+ -+#define SCI_HIGH_MASK 0xffffffff00000000LL -+#define SCI_LOW_MASK 0x00000000ffffffffLL -+ -+#define LONG_SHIFT 32 -+ -+#define GET_SCI_FIRST_HALF(sci) (uint32_t)((macsecSCI_t)((macsecSCI_t)(sci) & SCI_HIGH_MASK) >> LONG_SHIFT) -+#define GET_SCI_SECOND_HALF(sci) (uint32_t)((macsecSCI_t)(sci) & SCI_LOW_MASK) -+ -+/**************************************************************************//** -+ @Description Configuration defines -+*//***************************************************************************/ -+ -+/* masks */ -+#define CFG_UECT 0x00000800 -+#define CFG_ESCBT 0x00000400 -+#define CFG_USFT 0x00000300 -+#define CFG_ITT 0x00000080 -+#define CFG_KFT 0x00000040 -+#define CFG_UFT 0x00000030 -+#define CFG_KSS 0x00000004 -+#define CFG_BYPN 0x00000002 -+#define CFG_S0I 0x00000001 -+ -+#define ET_TYPE 0x0000ffff -+ -+#define MFL_MAX_LEN 0x0000ffff -+ -+#define RXSCA_SC_SEL 0x0000000f -+ -+#define TXSCA_SC_SEL 0x0000000f -+ -+#define IP_REV_1_IP_ID 0xffff0000 -+#define IP_REV_1_IP_MJ 0x0000ff00 -+#define IP_REV_1_IP_MM 0x000000ff -+ -+#define IP_REV_2_IP_INT 0x00ff0000 -+#define IP_REV_2_IP_ERR 0x0000ff00 -+#define IP_REV_2_IP_CFG 0x000000ff -+ -+#define MECC_CAP 0x80000000 -+#define MECC_CET 0x40000000 -+#define MECC_SERCNT 0x00ff0000 -+#define MECC_MEMADDR 0x000001ff -+ -+/* shifts */ -+#define CFG_UECT_SHIFT (31-20) -+#define CFG_ESCBT_SHIFT (31-21) -+#define CFG_USFT_SHIFT (31-23) -+#define CFG_ITT_SHIFT (31-24) -+#define CFG_KFT_SHIFT (31-25) -+#define CFG_UFT_SHIFT (31-27) -+#define CFG_KSS_SHIFT (31-29) -+#define CFG_BYPN_SHIFT (31-30) -+#define CFG_S0I_SHIFT (31-31) -+ -+#define IP_REV_1_IP_ID_SHIFT (31-15) -+#define IP_REV_1_IP_MJ_SHIFT (31-23) -+#define IP_REV_1_IP_MM_SHIFT (31-31) -+ -+#define IP_REV_2_IP_INT_SHIFT (31-15) -+#define IP_REV_2_IP_ERR_SHIFT (31-23) -+#define IP_REV_2_IP_CFG_SHIFT (31-31) -+ -+#define MECC_CAP_SHIFT (31-0) -+#define MECC_CET_SHIFT (31-1) -+#define MECC_SERCNT_SHIFT (31-15) -+#define MECC_MEMADDR_SHIFT (31-31) -+ -+/**************************************************************************//** -+ @Description RX SC defines -+*//***************************************************************************/ -+ -+/* masks */ -+#define RX_SCCFG_SCI_EN_MASK 0x00000800 -+#define RX_SCCFG_RP_MASK 0x00000400 -+#define RX_SCCFG_VF_MASK 0x00000300 -+#define RX_SCCFG_CO_MASK 0x0000003f -+ -+/* shifts */ -+#define RX_SCCFG_SCI_EN_SHIFT (31-20) -+#define RX_SCCFG_RP_SHIFT (31-21) -+#define RX_SCCFG_VF_SHIFT (31-23) -+#define RX_SCCFG_CO_SHIFT (31-31) -+#define RX_SCCFG_CS_SHIFT (31-7) -+ -+/**************************************************************************//** -+ @Description RX SA defines -+*//***************************************************************************/ -+ -+/* masks */ -+#define RX_SACFG_ACTIVE 0x80000000 -+#define RX_SACFG_AN_MASK 0x00000006 -+#define RX_SACFG_EN_MASK 0x00000001 -+ -+/* shifts */ -+#define RX_SACFG_AN_SHIFT (31-30) -+#define RX_SACFG_EN_SHIFT (31-31) -+ -+/**************************************************************************//** -+ @Description TX SC defines -+*//***************************************************************************/ -+ -+/* masks */ -+#define TX_SCCFG_AN_MASK 0x000c0000 -+#define TX_SCCFG_ASA_MASK 0x00020000 -+#define TX_SCCFG_SCE_MASK 0x00010000 -+#define TX_SCCFG_CO_MASK 0x00003f00 -+#define TX_SCCFG_CE_MASK 0x00000010 -+#define TX_SCCFG_PF_MASK 0x00000008 -+#define TX_SCCFG_AIS_MASK 0x00000004 -+#define TX_SCCFG_UES_MASK 0x00000002 -+#define TX_SCCFG_USCB_MASK 0x00000001 -+ -+/* shifts */ -+#define TX_SCCFG_AN_SHIFT (31-13) -+#define TX_SCCFG_ASA_SHIFT (31-14) -+#define TX_SCCFG_SCE_SHIFT (31-15) -+#define TX_SCCFG_CO_SHIFT (31-23) -+#define TX_SCCFG_CE_SHIFT (31-27) -+#define TX_SCCFG_PF_SHIFT (31-28) -+#define TX_SCCFG_AIS_SHIFT (31-29) -+#define TX_SCCFG_UES_SHIFT (31-30) -+#define TX_SCCFG_USCB_SHIFT (31-31) -+#define TX_SCCFG_CS_SHIFT (31-7) -+ -+/**************************************************************************//** -+ @Description TX SA defines -+*//***************************************************************************/ -+ -+/* masks */ -+#define TX_SACFG_ACTIVE 0x80000000 -+ -+ -+typedef struct -+{ -+ void (*f_Isr) (t_Handle h_Arg, uint32_t id); -+ t_Handle h_SrcHandle; -+} t_FmMacsecIntrSrc; -+ -+typedef struct -+{ -+ e_FmMacsecUnknownSciFrameTreatment unknownSciTreatMode; -+ bool invalidTagsDeliverUncontrolled; -+ bool changedTextWithNoEncryptDeliverUncontrolled; -+ bool onlyScbIsSetDeliverUncontrolled; -+ bool encryptWithNoChangedTextDiscardUncontrolled; -+ e_FmMacsecUntagFrameTreatment untagTreatMode; -+ uint32_t pnExhThr; -+ bool keysUnreadable; -+ bool byPassMode; -+ bool reservedSc0; -+ uint32_t sectagOverhead; -+ uint32_t mflSubtract; -+} t_FmMacsecDriverParam; -+ -+typedef struct -+{ -+ t_FmMacsecControllerDriver fmMacsecControllerDriver; -+ t_Handle h_Fm; -+ t_FmMacsecRegs *p_FmMacsecRegs; -+ t_Handle h_FmMac; /**< A handle to the FM MAC object related to */ -+ char fmMacsecModuleName[MODULE_NAME_SIZE]; -+ t_FmMacsecIntrSrc intrMng[NUM_OF_INTER_MODULE_EVENTS]; -+ uint32_t events; -+ uint32_t exceptions; -+ uint32_t userExceptions; -+ t_FmMacsecExceptionsCallback *f_Exception; /**< Exception Callback Routine */ -+ t_Handle h_App; /**< A handle to an application layer object; This handle will -+ be passed by the driver upon calling the above callbacks */ -+ bool rxScTable[NUM_OF_RX_SC]; -+ uint32_t numRxScAvailable; -+ bool txScTable[NUM_OF_TX_SC]; -+ uint32_t numTxScAvailable; -+ t_Handle rxScSpinLock; -+ t_Handle txScSpinLock; -+ t_FmMacsecDriverParam *p_FmMacsecDriverParam; -+} t_FmMacsec; -+ -+ -+#endif /* __FM_MACSEC_MASTER_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.c -@@ -0,0 +1,883 @@ -+/* -+ * Copyright 2008-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/****************************************************************************** -+ @File fm_macsec_secy.c -+ -+ @Description FM MACSEC SECY driver routines implementation. -+*//***************************************************************************/ -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "xx_ext.h" -+#include "string_ext.h" -+#include "sprint_ext.h" -+ -+#include "fm_macsec_secy.h" -+ -+ -+/****************************************/ -+/* static functions */ -+/****************************************/ -+static void FmMacsecSecYExceptionsIsr(t_Handle h_FmMacsecSecY, uint32_t id) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ -+ UNUSED(id); -+ SANITY_CHECK_RETURN(p_FmMacsecSecY, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecSecY->exceptions & FM_MACSEC_SECY_EX_FRAME_DISCARDED) -+ p_FmMacsecSecY->f_Exception(p_FmMacsecSecY->h_App, e_FM_MACSEC_SECY_EX_FRAME_DISCARDED); -+} -+ -+static void FmMacsecSecYEventsIsr(t_Handle h_FmMacsecSecY, uint32_t id) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ -+ UNUSED(id); -+ SANITY_CHECK_RETURN(p_FmMacsecSecY, E_INVALID_HANDLE); -+ -+ if (p_FmMacsecSecY->events & FM_MACSEC_SECY_EV_NEXT_PN) -+ p_FmMacsecSecY->f_Event(p_FmMacsecSecY->h_App, e_FM_MACSEC_SECY_EV_NEXT_PN); -+} -+ -+static t_Error CheckFmMacsecSecYParameters(t_FmMacsecSecY *p_FmMacsecSecY) -+{ -+ if (!p_FmMacsecSecY->f_Exception) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceptions callback not provided")); -+ -+ if (!p_FmMacsecSecY->f_Event) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Events callback not provided")); -+ -+ if (!p_FmMacsecSecY->numOfRxSc) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Num of Rx Scs must be greater than '0'")); -+ -+ -+ return E_OK; -+} -+ -+static t_Handle FmMacsecSecYCreateSc(t_FmMacsecSecY *p_FmMacsecSecY, -+ macsecSCI_t sci, -+ e_FmMacsecSecYCipherSuite cipherSuite, -+ e_ScType type) -+{ -+ t_SecYSc *p_ScTable; -+ void *p_Params; -+ uint32_t numOfSc,i; -+ t_Error err = E_OK; -+ t_RxScParams rxScParams; -+ t_TxScParams txScParams; -+ -+ ASSERT_COND(p_FmMacsecSecY); -+ ASSERT_COND(p_FmMacsecSecY->h_FmMacsec); -+ -+ if (type == e_SC_RX) -+ { -+ memset(&rxScParams, 0, sizeof(rxScParams)); -+ i = (NUM_OF_RX_SC - 1); -+ p_ScTable = p_FmMacsecSecY->p_RxSc; -+ numOfSc = p_FmMacsecSecY->numOfRxSc; -+ rxScParams.confidentialityOffset = p_FmMacsecSecY->confidentialityOffset; -+ rxScParams.replayProtect = p_FmMacsecSecY->replayProtect; -+ rxScParams.replayWindow = p_FmMacsecSecY->replayWindow; -+ rxScParams.validateFrames = p_FmMacsecSecY->validateFrames; -+ rxScParams.cipherSuite = cipherSuite; -+ p_Params = &rxScParams; -+ } -+ else -+ { -+ memset(&txScParams, 0, sizeof(txScParams)); -+ i = (NUM_OF_TX_SC - 1); -+ p_ScTable = p_FmMacsecSecY->p_TxSc; -+ numOfSc = p_FmMacsecSecY->numOfTxSc; -+ txScParams.sciInsertionMode = p_FmMacsecSecY->sciInsertionMode; -+ txScParams.protectFrames = p_FmMacsecSecY->protectFrames; -+ txScParams.confidentialityEnable = p_FmMacsecSecY->confidentialityEnable; -+ txScParams.confidentialityOffset = p_FmMacsecSecY->confidentialityOffset; -+ txScParams.cipherSuite = cipherSuite; -+ p_Params = &txScParams; -+ } -+ -+ for (i=0;iscId = p_ScTable[i].scId; -+ ((t_RxScParams *)p_Params)->sci = sci; -+ if ((err = FmMacsecCreateRxSc(p_FmMacsecSecY->h_FmMacsec, (t_RxScParams *)p_Params)) != E_OK) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY RX SC")); -+ return NULL; -+ } -+ } -+ else -+ { -+ ((t_TxScParams *)p_Params)->scId = p_ScTable[i].scId; -+ ((t_TxScParams *)p_Params)->sci = sci; -+ if ((err = FmMacsecCreateTxSc(p_FmMacsecSecY->h_FmMacsec, (t_TxScParams *)p_Params)) != E_OK) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY TX SC")); -+ return NULL; -+ } -+ } -+ -+ p_ScTable[i].inUse = TRUE; -+ return &p_ScTable[i]; -+} -+ -+static t_Error FmMacsecSecYDeleteSc(t_FmMacsecSecY *p_FmMacsecSecY, t_SecYSc *p_FmSecYSc, e_ScType type) -+{ -+ t_Error err = E_OK; -+ -+ ASSERT_COND(p_FmMacsecSecY); -+ ASSERT_COND(p_FmMacsecSecY->h_FmMacsec); -+ ASSERT_COND(p_FmSecYSc); -+ -+ if (type == e_SC_RX) -+ { -+ if ((err = FmMacsecDeleteRxSc(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ else -+ if ((err = FmMacsecDeleteTxSc(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ p_FmSecYSc->inUse = FALSE; -+ -+ return err; -+} -+ -+/****************************************/ -+/* API Init unit functions */ -+/****************************************/ -+t_Handle FM_MACSEC_SECY_Config(t_FmMacsecSecYParams *p_FmMacsecSecYParam) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY; -+ -+ /* Allocate FM MACSEC structure */ -+ p_FmMacsecSecY = (t_FmMacsecSecY *) XX_Malloc(sizeof(t_FmMacsecSecY)); -+ if (!p_FmMacsecSecY) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY driver structure")); -+ return NULL; -+ } -+ memset(p_FmMacsecSecY, 0, sizeof(t_FmMacsecSecY)); -+ -+ /* Allocate the FM MACSEC driver's parameters structure */ -+ p_FmMacsecSecY->p_FmMacsecSecYDriverParam = (t_FmMacsecSecYDriverParam *)XX_Malloc(sizeof(t_FmMacsecSecYDriverParam)); -+ if (!p_FmMacsecSecY->p_FmMacsecSecYDriverParam) -+ { -+ XX_Free(p_FmMacsecSecY); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY driver parameters")); -+ return NULL; -+ } -+ memset(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, 0, sizeof(t_FmMacsecSecYDriverParam)); -+ -+ /* Initialize FM MACSEC SECY parameters which will be kept by the driver */ -+ p_FmMacsecSecY->h_FmMacsec = p_FmMacsecSecYParam->h_FmMacsec; -+ p_FmMacsecSecY->f_Event = p_FmMacsecSecYParam->f_Event; -+ p_FmMacsecSecY->f_Exception = p_FmMacsecSecYParam->f_Exception; -+ p_FmMacsecSecY->h_App = p_FmMacsecSecYParam->h_App; -+ p_FmMacsecSecY->confidentialityEnable = DEFAULT_confidentialityEnable; -+ p_FmMacsecSecY->confidentialityOffset = DEFAULT_confidentialityOffset; -+ p_FmMacsecSecY->validateFrames = DEFAULT_validateFrames; -+ p_FmMacsecSecY->replayProtect = DEFAULT_replayEnable; -+ p_FmMacsecSecY->replayWindow = DEFAULT_replayWindow; -+ p_FmMacsecSecY->protectFrames = DEFAULT_protectFrames; -+ p_FmMacsecSecY->sciInsertionMode = DEFAULT_sciInsertionMode; -+ p_FmMacsecSecY->isPointToPoint = DEFAULT_ptp; -+ p_FmMacsecSecY->numOfRxSc = p_FmMacsecSecYParam->numReceiveChannels; -+ p_FmMacsecSecY->numOfTxSc = DEFAULT_numOfTxSc; -+ p_FmMacsecSecY->exceptions = DEFAULT_exceptions; -+ p_FmMacsecSecY->events = DEFAULT_events; -+ -+ memcpy(&p_FmMacsecSecY->p_FmMacsecSecYDriverParam->txScParams, -+ &p_FmMacsecSecYParam->txScParams, -+ sizeof(t_FmMacsecSecYSCParams)); -+ return p_FmMacsecSecY; -+} -+ -+t_Error FM_MACSEC_SECY_Init(t_Handle h_FmMacsecSecY) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_FmMacsecSecYDriverParam *p_FmMacsecSecYDriverParam = NULL; -+ uint32_t rxScIds[NUM_OF_RX_SC], txScIds[NUM_OF_TX_SC], i, j; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_HANDLE); -+ -+ CHECK_INIT_PARAMETERS(p_FmMacsecSecY, CheckFmMacsecSecYParameters); -+ -+ p_FmMacsecSecYDriverParam = p_FmMacsecSecY->p_FmMacsecSecYDriverParam; -+ -+ if ((p_FmMacsecSecY->isPointToPoint) && -+ ((err = FmMacsecSetPTP(p_FmMacsecSecY->h_FmMacsec, TRUE)) != E_OK)) -+ RETURN_ERROR(MAJOR, err, ("Can't set Poin-to-Point")); -+ -+ /* Rx Sc Allocation */ -+ p_FmMacsecSecY->p_RxSc = (t_SecYSc *)XX_Malloc(sizeof(t_SecYSc) * p_FmMacsecSecY->numOfRxSc); -+ if (!p_FmMacsecSecY->p_RxSc) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY RX SC")); -+ memset(p_FmMacsecSecY->p_RxSc, 0, sizeof(t_SecYSc) * p_FmMacsecSecY->numOfRxSc); -+ if ((err = FmMacsecAllocScs(p_FmMacsecSecY->h_FmMacsec, e_SC_RX, p_FmMacsecSecY->isPointToPoint, p_FmMacsecSecY->numOfRxSc, rxScIds)) != E_OK) -+ { -+ if (p_FmMacsecSecY->p_TxSc) -+ XX_Free(p_FmMacsecSecY->p_TxSc); -+ if (p_FmMacsecSecY->p_RxSc) -+ XX_Free(p_FmMacsecSecY->p_RxSc); -+ return ERROR_CODE(err); -+ } -+ for (i=0; inumOfRxSc; i++) -+ { -+ p_FmMacsecSecY->p_RxSc[i].scId = rxScIds[i]; -+ p_FmMacsecSecY->p_RxSc[i].type = e_SC_RX; -+ for (j=0; jp_RxSc[i].sa[j].saId = (e_ScSaId)SECY_AN_FREE_VALUE; -+ } -+ -+ /* Tx Sc Allocation */ -+ p_FmMacsecSecY->p_TxSc = (t_SecYSc *)XX_Malloc(sizeof(t_SecYSc) * p_FmMacsecSecY->numOfTxSc); -+ if (!p_FmMacsecSecY->p_TxSc) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY TX SC")); -+ memset(p_FmMacsecSecY->p_TxSc, 0, sizeof(t_SecYSc) * p_FmMacsecSecY->numOfTxSc); -+ -+ if ((err = FmMacsecAllocScs(p_FmMacsecSecY->h_FmMacsec, e_SC_TX, p_FmMacsecSecY->isPointToPoint, p_FmMacsecSecY->numOfTxSc, txScIds)) != E_OK) -+ { -+ if (p_FmMacsecSecY->p_TxSc) -+ XX_Free(p_FmMacsecSecY->p_TxSc); -+ if (p_FmMacsecSecY->p_RxSc) -+ XX_Free(p_FmMacsecSecY->p_RxSc); -+ return ERROR_CODE(err); -+ } -+ for (i=0; inumOfTxSc; i++) -+ { -+ p_FmMacsecSecY->p_TxSc[i].scId = txScIds[i]; -+ p_FmMacsecSecY->p_TxSc[i].type = e_SC_TX; -+ for (j=0; jp_TxSc[i].sa[j].saId = (e_ScSaId)SECY_AN_FREE_VALUE; -+ FmMacsecRegisterIntr(p_FmMacsecSecY->h_FmMacsec, -+ e_FM_MACSEC_MOD_SC_TX, -+ (uint8_t)txScIds[i], -+ e_FM_INTR_TYPE_ERR, -+ FmMacsecSecYExceptionsIsr, -+ p_FmMacsecSecY); -+ FmMacsecRegisterIntr(p_FmMacsecSecY->h_FmMacsec, -+ e_FM_MACSEC_MOD_SC_TX, -+ (uint8_t)txScIds[i], -+ e_FM_INTR_TYPE_NORMAL, -+ FmMacsecSecYEventsIsr, -+ p_FmMacsecSecY); -+ -+ if (p_FmMacsecSecY->exceptions & FM_MACSEC_SECY_EX_FRAME_DISCARDED) -+ FmMacsecSetException(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EX_TX_SC, txScIds[i], TRUE); -+ if (p_FmMacsecSecY->events & FM_MACSEC_SECY_EV_NEXT_PN) -+ FmMacsecSetEvent(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EV_TX_SC_NEXT_PN, txScIds[i], TRUE); -+ } -+ -+ FmMacsecSecYCreateSc(p_FmMacsecSecY, -+ p_FmMacsecSecYDriverParam->txScParams.sci, -+ p_FmMacsecSecYDriverParam->txScParams.cipherSuite, -+ e_SC_TX); -+ XX_Free(p_FmMacsecSecYDriverParam); -+ p_FmMacsecSecY->p_FmMacsecSecYDriverParam = NULL; -+ -+ return E_OK; -+} -+ -+t_Error FM_MACSEC_SECY_Free(t_Handle h_FmMacsecSecY) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_Error err = E_OK; -+ uint32_t rxScIds[NUM_OF_RX_SC], txScIds[NUM_OF_TX_SC], i; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ -+ if (p_FmMacsecSecY->isPointToPoint) -+ FmMacsecSetPTP(p_FmMacsecSecY->h_FmMacsec, FALSE); -+ if (p_FmMacsecSecY->p_RxSc) -+ { -+ for (i=0; inumOfRxSc; i++) -+ rxScIds[i] = p_FmMacsecSecY->p_RxSc[i].scId; -+ if ((err = FmMacsecFreeScs(p_FmMacsecSecY->h_FmMacsec, e_SC_RX, p_FmMacsecSecY->numOfRxSc, rxScIds)) != E_OK) -+ return ERROR_CODE(err); -+ XX_Free(p_FmMacsecSecY->p_RxSc); -+ } -+ if (p_FmMacsecSecY->p_TxSc) -+ { -+ FmMacsecSecYDeleteSc(p_FmMacsecSecY, &p_FmMacsecSecY->p_TxSc[0], e_SC_TX); -+ -+ for (i=0; inumOfTxSc; i++) { -+ txScIds[i] = p_FmMacsecSecY->p_TxSc[i].scId; -+ FmMacsecUnregisterIntr(p_FmMacsecSecY->h_FmMacsec, -+ e_FM_MACSEC_MOD_SC_TX, -+ (uint8_t)txScIds[i], -+ e_FM_INTR_TYPE_ERR); -+ FmMacsecUnregisterIntr(p_FmMacsecSecY->h_FmMacsec, -+ e_FM_MACSEC_MOD_SC_TX, -+ (uint8_t)txScIds[i], -+ e_FM_INTR_TYPE_NORMAL); -+ -+ if (p_FmMacsecSecY->exceptions & FM_MACSEC_SECY_EX_FRAME_DISCARDED) -+ FmMacsecSetException(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EX_TX_SC, txScIds[i], FALSE); -+ if (p_FmMacsecSecY->events & FM_MACSEC_SECY_EV_NEXT_PN) -+ FmMacsecSetEvent(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EV_TX_SC_NEXT_PN, txScIds[i], FALSE); -+ } -+ -+ if ((err = FmMacsecFreeScs(p_FmMacsecSecY->h_FmMacsec, e_SC_TX, p_FmMacsecSecY->numOfTxSc, txScIds)) != E_OK) -+ return ERROR_CODE(err); -+ XX_Free(p_FmMacsecSecY->p_TxSc); -+ } -+ -+ XX_Free(p_FmMacsecSecY); -+ -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_ConfigSciInsertionMode(t_Handle h_FmMacsecSecY, e_FmMacsecSciInsertionMode sciInsertionMode) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ -+ p_FmMacsecSecY->sciInsertionMode = sciInsertionMode; -+ -+ return E_OK; -+} -+ -+t_Error FM_MACSEC_SECY_ConfigProtectFrames(t_Handle h_FmMacsecSecY, bool protectFrames) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ -+ p_FmMacsecSecY->protectFrames = protectFrames; -+ -+ return E_OK; -+} -+ -+t_Error FM_MACSEC_SECY_ConfigReplayWindow(t_Handle h_FmMacsecSecY, bool replayProtect, uint32_t replayWindow) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ -+ p_FmMacsecSecY->replayProtect = replayProtect; -+ p_FmMacsecSecY->replayWindow = replayWindow; -+ -+ return E_OK; -+} -+ -+t_Error FM_MACSEC_SECY_ConfigValidationMode(t_Handle h_FmMacsecSecY, e_FmMacsecValidFrameBehavior validateFrames) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ -+ p_FmMacsecSecY->validateFrames = validateFrames; -+ -+ return E_OK; -+} -+ -+t_Error FM_MACSEC_SECY_ConfigConfidentiality(t_Handle h_FmMacsecSecY, bool confidentialityEnable, uint16_t confidentialityOffset) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ -+ p_FmMacsecSecY->confidentialityEnable = confidentialityEnable; -+ p_FmMacsecSecY->confidentialityOffset = confidentialityOffset; -+ -+ return E_OK; -+} -+ -+t_Error FM_MACSEC_SECY_ConfigPointToPoint(t_Handle h_FmMacsecSecY) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ -+ p_FmMacsecSecY->numOfRxSc = 1; -+ p_FmMacsecSecY->isPointToPoint = TRUE; -+ p_FmMacsecSecY->sciInsertionMode = e_FM_MACSEC_SCI_INSERTION_MODE_IMPLICT_PTP; -+ -+ return E_OK; -+} -+ -+t_Error FM_MACSEC_SECY_ConfigException(t_Handle h_FmMacsecSecY, e_FmMacsecSecYExceptions exception, bool enable) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ uint32_t bitMask = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ -+ GET_EXCEPTION_FLAG(bitMask, exception); -+ if (bitMask) -+ { -+ if (enable) -+ p_FmMacsecSecY->exceptions |= bitMask; -+ else -+ p_FmMacsecSecY->exceptions &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); -+ -+ return E_OK; -+} -+ -+t_Error FM_MACSEC_SECY_ConfigEvent(t_Handle h_FmMacsecSecY, e_FmMacsecSecYEvents event, bool enable) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ uint32_t bitMask = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ -+ GET_EVENT_FLAG(bitMask, event); -+ if (bitMask) -+ { -+ if (enable) -+ p_FmMacsecSecY->events |= bitMask; -+ else -+ p_FmMacsecSecY->events &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined event")); -+ -+ return E_OK; -+} -+ -+t_Handle FM_MACSEC_SECY_CreateRxSc(t_Handle h_FmMacsecSecY, t_FmMacsecSecYSCParams *p_ScParams) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmMacsecSecY, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(p_ScParams, E_NULL_POINTER, NULL); -+ SANITY_CHECK_RETURN_VALUE(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE, NULL); -+ -+ return FmMacsecSecYCreateSc(p_FmMacsecSecY, p_ScParams->sci, p_ScParams->cipherSuite, e_SC_RX); -+} -+ -+t_Error FM_MACSEC_SECY_DeleteRxSc(t_Handle h_FmMacsecSecY, t_Handle h_Sc) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ -+ return FmMacsecSecYDeleteSc(p_FmMacsecSecY, p_FmSecYSc, e_SC_RX); -+} -+ -+t_Error FM_MACSEC_SECY_CreateRxSa(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t lowestPn, macsecSAKey_t key) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE); -+ -+ if (p_FmSecYSc->sa[an].saId != SECY_AN_FREE_VALUE) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is already assigned",an)); -+ -+ if ((err = FmMacsecCreateRxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, (e_ScSaId)p_FmSecYSc->numOfSa, an, lowestPn, key)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ p_FmSecYSc->sa[an].saId = (e_ScSaId)p_FmSecYSc->numOfSa++; -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_DeleteRxSa(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE); -+ -+ if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is already deleted",an)); -+ -+ if ((err = FmMacsecDeleteRxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ p_FmSecYSc->numOfSa--; -+ p_FmSecYSc->sa[an].saId = (e_ScSaId)SECY_AN_FREE_VALUE; -+ /* TODO - check if statistics need to be read*/ -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_RxSaEnableReceive(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE); -+ -+ if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an)); -+ -+ if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, TRUE)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ p_FmSecYSc->sa[an].active = TRUE; -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_RxSaDisableReceive(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE); -+ -+ if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an)); -+ -+ if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, FALSE)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ p_FmSecYSc->sa[an].active = FALSE; -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_RxSaUpdateNextPn(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t updtNextPN) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE); -+ -+ if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an)); -+ -+ if ((err = FmMacsecRxSaUpdateNextPn(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, updtNextPN)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_RxSaUpdateLowestPn(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t updtLowestPN) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE); -+ -+ if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an)); -+ -+ if ((err = FmMacsecRxSaUpdateLowestPn(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, updtLowestPN)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_RxSaModifyKey(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, macsecSAKey_t key) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE); -+ -+ if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an)); -+ -+ if (p_FmSecYSc->sa[an].active) -+ if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, FALSE)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ /* TODO - statistics should be read */ -+ -+ if ((err = FmMacsecCreateRxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, an, 1, key)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ if (p_FmSecYSc->sa[an].active) -+ if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, TRUE)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ return err; -+} -+ -+ -+t_Error FM_MACSEC_SECY_CreateTxSa(t_Handle h_FmMacsecSecY, macsecAN_t an, macsecSAKey_t key) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0]; -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE); -+ -+ if (p_FmSecYSc->sa[an].saId != SECY_AN_FREE_VALUE) -+ RETURN_ERROR(MINOR, err, ("An %d is already assigned",an)); -+ -+ if ((err = FmMacsecCreateTxSa(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, (e_ScSaId)p_FmSecYSc->numOfSa, key)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ p_FmSecYSc->sa[an].saId = (e_ScSaId)p_FmSecYSc->numOfSa++; -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_DeleteTxSa(t_Handle h_FmMacsecSecY, macsecAN_t an) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0]; -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE); -+ -+ if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is already deleted",an)); -+ -+ if ((err = FmMacsecDeleteTxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ p_FmSecYSc->numOfSa--; -+ p_FmSecYSc->sa[an].saId = (e_ScSaId)SECY_AN_FREE_VALUE; -+ /* TODO - check if statistics need to be read*/ -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_TxSaModifyKey(t_Handle h_FmMacsecSecY, macsecAN_t nextActiveAn, macsecSAKey_t key) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc; -+ macsecAN_t currentAn; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0]; -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(nextActiveAn < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE); -+ -+ if ((err = FmMacsecTxSaGetActive(p_FmMacsecSecY->h_FmMacsec, -+ p_FmSecYSc->scId, -+ ¤tAn)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ if ((err = FmMacsecTxSaSetActive(p_FmMacsecSecY->h_FmMacsec, -+ p_FmSecYSc->scId, -+ p_FmSecYSc->sa[nextActiveAn].saId, -+ nextActiveAn)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ /* TODO - statistics should be read */ -+ -+ if ((err = FmMacsecCreateTxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[currentAn].saId, key)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_TxSaSetActive(t_Handle h_FmMacsecSecY, macsecAN_t an) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0]; -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE); -+ -+ if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an)); -+ -+ if ((err = FmMacsecTxSaSetActive(p_FmMacsecSecY->h_FmMacsec, -+ p_FmSecYSc->scId, -+ p_FmSecYSc->sa[an].saId, -+ an)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_TxSaGetActive(t_Handle h_FmMacsecSecY, macsecAN_t *p_An) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0]; -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_An, E_INVALID_HANDLE); -+ -+ if ((err = FmMacsecTxSaGetActive(p_FmMacsecSecY->h_FmMacsec, -+ p_FmSecYSc->scId, -+ p_An)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_GetRxScPhysId(t_Handle h_FmMacsecSecY, t_Handle h_Sc, uint32_t *p_ScPhysId) -+{ -+ t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(((t_FmMacsecSecY *)h_FmMacsecSecY)->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!((t_FmMacsecSecY *)h_FmMacsecSecY)->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+#ifdef DISABLE_SANITY_CHECKS -+ UNUSED(h_FmMacsecSecY); -+#endif /* DISABLE_SANITY_CHECKS */ -+ -+ *p_ScPhysId = p_FmSecYSc->scId; -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_GetTxScPhysId(t_Handle h_FmMacsecSecY, uint32_t *p_ScPhysId) -+{ -+ t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY; -+ t_SecYSc *p_FmSecYSc; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE); -+ p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0]; -+ SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE); -+ -+ *p_ScPhysId = p_FmSecYSc->scId; -+ return err; -+} -+ -+t_Error FM_MACSEC_SECY_SetException(t_Handle h_FmMacsecSecY, e_FmMacsecExceptions exception, bool enable) -+{ -+ UNUSED(h_FmMacsecSecY);UNUSED(exception);UNUSED(enable); -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_SECY_SetEvent(t_Handle h_FmMacsecSecY, e_FmMacsecSecYEvents event, bool enable) -+{ -+ UNUSED(h_FmMacsecSecY);UNUSED(event);UNUSED(enable); -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_SECY_GetStatistics(t_Handle h_FmMacsecSecY, t_FmMacsecSecYStatistics *p_Statistics) -+{ -+ UNUSED(h_FmMacsecSecY);UNUSED(p_Statistics); -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_SECY_RxScGetStatistics(t_Handle h_FmMacsecSecY, t_Handle h_Sc, t_FmMacsecSecYRxScStatistics *p_Statistics) -+{ -+ UNUSED(h_FmMacsecSecY);UNUSED(h_Sc);UNUSED(p_Statistics); -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_SECY_RxSaGetStatistics(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, t_FmMacsecSecYRxSaStatistics *p_Statistics) -+{ -+ UNUSED(h_FmMacsecSecY);UNUSED(h_Sc);UNUSED(an);UNUSED(p_Statistics); -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_SECY_TxScGetStatistics(t_Handle h_FmMacsecSecY, t_FmMacsecSecYTxScStatistics *p_Statistics) -+{ -+ UNUSED(h_FmMacsecSecY);UNUSED(p_Statistics); -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ -+t_Error FM_MACSEC_SECY_TxSaGetStatistics(t_Handle h_FmMacsecSecY, macsecAN_t an, t_FmMacsecSecYTxSaStatistics *p_Statistics) -+{ -+ UNUSED(h_FmMacsecSecY);UNUSED(an);UNUSED(p_Statistics); -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+} -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.h -@@ -0,0 +1,144 @@ -+/* -+ * Copyright 2008-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/****************************************************************************** -+ @File fm_macsec_secy.h -+ -+ @Description FM MACSEC SecY internal structures and definitions. -+*//***************************************************************************/ -+#ifndef __FM_MACSEC_SECY_H -+#define __FM_MACSEC_SECY_H -+ -+#include "error_ext.h" -+#include "std_ext.h" -+ -+#include "fm_macsec.h" -+ -+ -+/**************************************************************************//** -+ @Description Exceptions -+*//***************************************************************************/ -+ -+#define FM_MACSEC_SECY_EX_FRAME_DISCARDED 0x80000000 -+ -+#define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \ -+ case e_FM_MACSEC_SECY_EX_FRAME_DISCARDED: \ -+ bitMask = FM_MACSEC_SECY_EX_FRAME_DISCARDED; break; \ -+ default: bitMask = 0;break;} -+ -+/**************************************************************************//** -+ @Description Events -+*//***************************************************************************/ -+ -+#define FM_MACSEC_SECY_EV_NEXT_PN 0x80000000 -+ -+#define GET_EVENT_FLAG(bitMask, event) switch (event){ \ -+ case e_FM_MACSEC_SECY_EV_NEXT_PN: \ -+ bitMask = FM_MACSEC_SECY_EV_NEXT_PN; break; \ -+ default: bitMask = 0;break;} -+ -+/**************************************************************************//** -+ @Description Defaults -+*//***************************************************************************/ -+ -+#define DEFAULT_exceptions (FM_MACSEC_SECY_EX_FRAME_DISCARDED) -+#define DEFAULT_events (FM_MACSEC_SECY_EV_NEXT_PN) -+#define DEFAULT_numOfTxSc 1 -+#define DEFAULT_confidentialityEnable FALSE -+#define DEFAULT_confidentialityOffset 0 -+#define DEFAULT_sciInsertionMode e_FM_MACSEC_SCI_INSERTION_MODE_EXPLICIT_SECTAG -+#define DEFAULT_validateFrames e_FM_MACSEC_VALID_FRAME_BEHAVIOR_STRICT -+#define DEFAULT_replayEnable FALSE -+#define DEFAULT_replayWindow 0 -+#define DEFAULT_protectFrames TRUE -+#define DEFAULT_ptp FALSE -+ -+/**************************************************************************//** -+ @Description General defines -+*//***************************************************************************/ -+ -+#define SECY_AN_FREE_VALUE MAX_NUM_OF_SA_PER_SC -+ -+ -+typedef struct { -+ e_ScSaId saId; -+ bool active; -+ union { -+ t_FmMacsecSecYRxSaStatistics rxSaStatistics; -+ t_FmMacsecSecYTxSaStatistics txSaStatistics; -+ }; -+} t_SecYSa; -+ -+typedef struct { -+ bool inUse; -+ uint32_t scId; -+ e_ScType type; -+ uint8_t numOfSa; -+ t_SecYSa sa[MAX_NUM_OF_SA_PER_SC]; -+ union { -+ t_FmMacsecSecYRxScStatistics rxScStatistics; -+ t_FmMacsecSecYTxScStatistics txScStatistics; -+ }; -+} t_SecYSc; -+ -+typedef struct { -+ t_FmMacsecSecYSCParams txScParams; /**< Tx SC Params */ -+} t_FmMacsecSecYDriverParam; -+ -+typedef struct { -+ t_Handle h_FmMacsec; -+ bool confidentialityEnable; /**< TRUE - confidentiality protection and integrity protection -+ FALSE - no confidentiality protection, only integrity protection*/ -+ uint16_t confidentialityOffset; /**< The number of initial octets of each MSDU without confidentiality protection -+ common values are 0, 30, and 50 */ -+ bool replayProtect; /**< replay protection function mode */ -+ uint32_t replayWindow; /**< the size of the replay window */ -+ e_FmMacsecValidFrameBehavior validateFrames; /**< validation function mode */ -+ e_FmMacsecSciInsertionMode sciInsertionMode; -+ bool protectFrames; -+ bool isPointToPoint; -+ e_FmMacsecSecYCipherSuite cipherSuite; /**< Cipher suite to be used for this SecY */ -+ uint32_t numOfRxSc; /**< Number of receive channels */ -+ uint32_t numOfTxSc; /**< Number of transmit channels */ -+ t_SecYSc *p_RxSc; -+ t_SecYSc *p_TxSc; -+ uint32_t events; -+ uint32_t exceptions; -+ t_FmMacsecSecYExceptionsCallback *f_Exception; /**< TODO */ -+ t_FmMacsecSecYEventsCallback *f_Event; /**< TODO */ -+ t_Handle h_App; -+ t_FmMacsecSecYStatistics statistics; -+ t_FmMacsecSecYDriverParam *p_FmMacsecSecYDriverParam; -+} t_FmMacsecSecY; -+ -+ -+#endif /* __FM_MACSEC_SECY_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Makefile -@@ -0,0 +1,23 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc -+ -+ccflags-y += -I$(NCSW_FM_INC) -+ -+ -+obj-y += fsl-ncsw-PFM1.o -+ -+fsl-ncsw-PFM1-objs := fm.o fm_muram.o fman.o -+ -+obj-y += MAC/ -+obj-y += Pcd/ -+obj-y += SP/ -+obj-y += Port/ -+obj-y += HC/ -+obj-y += Rtc/ -+obj-y += MACSEC/ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/Makefile -@@ -0,0 +1,26 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+ -+NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc -+ -+ccflags-y += -I$(NCSW_FM_INC) -+ -+obj-y += fsl-ncsw-Pcd.o -+ -+fsl-ncsw-Pcd-objs := fman_kg.o fman_prs.o fm_cc.o fm_kg.o fm_pcd.o fm_plcr.o fm_prs.o fm_manip.o -+ -+ifeq ($(CONFIG_FMAN_V3H),y) -+fsl-ncsw-Pcd-objs += fm_replic.o -+endif -+ifeq ($(CONFIG_FMAN_V3L),y) -+fsl-ncsw-Pcd-objs += fm_replic.o -+endif -+ifeq ($(CONFIG_FMAN_ARM),y) -+fsl-ncsw-Pcd-objs += fm_replic.o -+endif -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/crc64.h -@@ -0,0 +1,360 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+ /**************************************************************************//** -+ @File crc64.h -+ -+ @Description brief This file contains the CRC64 Table, and __inline__ -+ functions used for calculating crc. -+*//***************************************************************************/ -+#ifndef __CRC64_H -+#define __CRC64_H -+ -+#include "std_ext.h" -+ -+ -+#define BITS_PER_BYTE 8 -+ -+#define CRC64_EXPON_ECMA_182 0xC96C5795D7870F42ULL -+#define CRC64_DEFAULT_INITVAL 0xFFFFFFFFFFFFFFFFULL -+ -+#define CRC64_BYTE_MASK 0xFF -+#define CRC64_TABLE_ENTRIES ( 1 << BITS_PER_BYTE ) -+#define CRC64_ODD_MASK 1 -+ -+ -+/** -+ \brief '64 bit crc' Table -+ */ -+struct crc64_t { -+ uint64_t initial; /**< Initial seed */ -+ uint64_t table[CRC64_TABLE_ENTRIES]; /**< CRC table entries */ -+}; -+ -+ -+static struct crc64_t CRC64_ECMA_182 = { -+ CRC64_DEFAULT_INITVAL, -+ { -+ 0x0000000000000000ULL, -+ 0xb32e4cbe03a75f6fULL, -+ 0xf4843657a840a05bULL, -+ 0x47aa7ae9abe7ff34ULL, -+ 0x7bd0c384ff8f5e33ULL, -+ 0xc8fe8f3afc28015cULL, -+ 0x8f54f5d357cffe68ULL, -+ 0x3c7ab96d5468a107ULL, -+ 0xf7a18709ff1ebc66ULL, -+ 0x448fcbb7fcb9e309ULL, -+ 0x0325b15e575e1c3dULL, -+ 0xb00bfde054f94352ULL, -+ 0x8c71448d0091e255ULL, -+ 0x3f5f08330336bd3aULL, -+ 0x78f572daa8d1420eULL, -+ 0xcbdb3e64ab761d61ULL, -+ 0x7d9ba13851336649ULL, -+ 0xceb5ed8652943926ULL, -+ 0x891f976ff973c612ULL, -+ 0x3a31dbd1fad4997dULL, -+ 0x064b62bcaebc387aULL, -+ 0xb5652e02ad1b6715ULL, -+ 0xf2cf54eb06fc9821ULL, -+ 0x41e11855055bc74eULL, -+ 0x8a3a2631ae2dda2fULL, -+ 0x39146a8fad8a8540ULL, -+ 0x7ebe1066066d7a74ULL, -+ 0xcd905cd805ca251bULL, -+ 0xf1eae5b551a2841cULL, -+ 0x42c4a90b5205db73ULL, -+ 0x056ed3e2f9e22447ULL, -+ 0xb6409f5cfa457b28ULL, -+ 0xfb374270a266cc92ULL, -+ 0x48190ecea1c193fdULL, -+ 0x0fb374270a266cc9ULL, -+ 0xbc9d3899098133a6ULL, -+ 0x80e781f45de992a1ULL, -+ 0x33c9cd4a5e4ecdceULL, -+ 0x7463b7a3f5a932faULL, -+ 0xc74dfb1df60e6d95ULL, -+ 0x0c96c5795d7870f4ULL, -+ 0xbfb889c75edf2f9bULL, -+ 0xf812f32ef538d0afULL, -+ 0x4b3cbf90f69f8fc0ULL, -+ 0x774606fda2f72ec7ULL, -+ 0xc4684a43a15071a8ULL, -+ 0x83c230aa0ab78e9cULL, -+ 0x30ec7c140910d1f3ULL, -+ 0x86ace348f355aadbULL, -+ 0x3582aff6f0f2f5b4ULL, -+ 0x7228d51f5b150a80ULL, -+ 0xc10699a158b255efULL, -+ 0xfd7c20cc0cdaf4e8ULL, -+ 0x4e526c720f7dab87ULL, -+ 0x09f8169ba49a54b3ULL, -+ 0xbad65a25a73d0bdcULL, -+ 0x710d64410c4b16bdULL, -+ 0xc22328ff0fec49d2ULL, -+ 0x85895216a40bb6e6ULL, -+ 0x36a71ea8a7ace989ULL, -+ 0x0adda7c5f3c4488eULL, -+ 0xb9f3eb7bf06317e1ULL, -+ 0xfe5991925b84e8d5ULL, -+ 0x4d77dd2c5823b7baULL, -+ 0x64b62bcaebc387a1ULL, -+ 0xd7986774e864d8ceULL, -+ 0x90321d9d438327faULL, -+ 0x231c512340247895ULL, -+ 0x1f66e84e144cd992ULL, -+ 0xac48a4f017eb86fdULL, -+ 0xebe2de19bc0c79c9ULL, -+ 0x58cc92a7bfab26a6ULL, -+ 0x9317acc314dd3bc7ULL, -+ 0x2039e07d177a64a8ULL, -+ 0x67939a94bc9d9b9cULL, -+ 0xd4bdd62abf3ac4f3ULL, -+ 0xe8c76f47eb5265f4ULL, -+ 0x5be923f9e8f53a9bULL, -+ 0x1c4359104312c5afULL, -+ 0xaf6d15ae40b59ac0ULL, -+ 0x192d8af2baf0e1e8ULL, -+ 0xaa03c64cb957be87ULL, -+ 0xeda9bca512b041b3ULL, -+ 0x5e87f01b11171edcULL, -+ 0x62fd4976457fbfdbULL, -+ 0xd1d305c846d8e0b4ULL, -+ 0x96797f21ed3f1f80ULL, -+ 0x2557339fee9840efULL, -+ 0xee8c0dfb45ee5d8eULL, -+ 0x5da24145464902e1ULL, -+ 0x1a083bacedaefdd5ULL, -+ 0xa9267712ee09a2baULL, -+ 0x955cce7fba6103bdULL, -+ 0x267282c1b9c65cd2ULL, -+ 0x61d8f8281221a3e6ULL, -+ 0xd2f6b4961186fc89ULL, -+ 0x9f8169ba49a54b33ULL, -+ 0x2caf25044a02145cULL, -+ 0x6b055fede1e5eb68ULL, -+ 0xd82b1353e242b407ULL, -+ 0xe451aa3eb62a1500ULL, -+ 0x577fe680b58d4a6fULL, -+ 0x10d59c691e6ab55bULL, -+ 0xa3fbd0d71dcdea34ULL, -+ 0x6820eeb3b6bbf755ULL, -+ 0xdb0ea20db51ca83aULL, -+ 0x9ca4d8e41efb570eULL, -+ 0x2f8a945a1d5c0861ULL, -+ 0x13f02d374934a966ULL, -+ 0xa0de61894a93f609ULL, -+ 0xe7741b60e174093dULL, -+ 0x545a57dee2d35652ULL, -+ 0xe21ac88218962d7aULL, -+ 0x5134843c1b317215ULL, -+ 0x169efed5b0d68d21ULL, -+ 0xa5b0b26bb371d24eULL, -+ 0x99ca0b06e7197349ULL, -+ 0x2ae447b8e4be2c26ULL, -+ 0x6d4e3d514f59d312ULL, -+ 0xde6071ef4cfe8c7dULL, -+ 0x15bb4f8be788911cULL, -+ 0xa6950335e42fce73ULL, -+ 0xe13f79dc4fc83147ULL, -+ 0x521135624c6f6e28ULL, -+ 0x6e6b8c0f1807cf2fULL, -+ 0xdd45c0b11ba09040ULL, -+ 0x9aefba58b0476f74ULL, -+ 0x29c1f6e6b3e0301bULL, -+ 0xc96c5795d7870f42ULL, -+ 0x7a421b2bd420502dULL, -+ 0x3de861c27fc7af19ULL, -+ 0x8ec62d7c7c60f076ULL, -+ 0xb2bc941128085171ULL, -+ 0x0192d8af2baf0e1eULL, -+ 0x4638a2468048f12aULL, -+ 0xf516eef883efae45ULL, -+ 0x3ecdd09c2899b324ULL, -+ 0x8de39c222b3eec4bULL, -+ 0xca49e6cb80d9137fULL, -+ 0x7967aa75837e4c10ULL, -+ 0x451d1318d716ed17ULL, -+ 0xf6335fa6d4b1b278ULL, -+ 0xb199254f7f564d4cULL, -+ 0x02b769f17cf11223ULL, -+ 0xb4f7f6ad86b4690bULL, -+ 0x07d9ba1385133664ULL, -+ 0x4073c0fa2ef4c950ULL, -+ 0xf35d8c442d53963fULL, -+ 0xcf273529793b3738ULL, -+ 0x7c0979977a9c6857ULL, -+ 0x3ba3037ed17b9763ULL, -+ 0x888d4fc0d2dcc80cULL, -+ 0x435671a479aad56dULL, -+ 0xf0783d1a7a0d8a02ULL, -+ 0xb7d247f3d1ea7536ULL, -+ 0x04fc0b4dd24d2a59ULL, -+ 0x3886b22086258b5eULL, -+ 0x8ba8fe9e8582d431ULL, -+ 0xcc0284772e652b05ULL, -+ 0x7f2cc8c92dc2746aULL, -+ 0x325b15e575e1c3d0ULL, -+ 0x8175595b76469cbfULL, -+ 0xc6df23b2dda1638bULL, -+ 0x75f16f0cde063ce4ULL, -+ 0x498bd6618a6e9de3ULL, -+ 0xfaa59adf89c9c28cULL, -+ 0xbd0fe036222e3db8ULL, -+ 0x0e21ac88218962d7ULL, -+ 0xc5fa92ec8aff7fb6ULL, -+ 0x76d4de52895820d9ULL, -+ 0x317ea4bb22bfdfedULL, -+ 0x8250e80521188082ULL, -+ 0xbe2a516875702185ULL, -+ 0x0d041dd676d77eeaULL, -+ 0x4aae673fdd3081deULL, -+ 0xf9802b81de97deb1ULL, -+ 0x4fc0b4dd24d2a599ULL, -+ 0xfceef8632775faf6ULL, -+ 0xbb44828a8c9205c2ULL, -+ 0x086ace348f355aadULL, -+ 0x34107759db5dfbaaULL, -+ 0x873e3be7d8faa4c5ULL, -+ 0xc094410e731d5bf1ULL, -+ 0x73ba0db070ba049eULL, -+ 0xb86133d4dbcc19ffULL, -+ 0x0b4f7f6ad86b4690ULL, -+ 0x4ce50583738cb9a4ULL, -+ 0xffcb493d702be6cbULL, -+ 0xc3b1f050244347ccULL, -+ 0x709fbcee27e418a3ULL, -+ 0x3735c6078c03e797ULL, -+ 0x841b8ab98fa4b8f8ULL, -+ 0xadda7c5f3c4488e3ULL, -+ 0x1ef430e13fe3d78cULL, -+ 0x595e4a08940428b8ULL, -+ 0xea7006b697a377d7ULL, -+ 0xd60abfdbc3cbd6d0ULL, -+ 0x6524f365c06c89bfULL, -+ 0x228e898c6b8b768bULL, -+ 0x91a0c532682c29e4ULL, -+ 0x5a7bfb56c35a3485ULL, -+ 0xe955b7e8c0fd6beaULL, -+ 0xaeffcd016b1a94deULL, -+ 0x1dd181bf68bdcbb1ULL, -+ 0x21ab38d23cd56ab6ULL, -+ 0x9285746c3f7235d9ULL, -+ 0xd52f0e859495caedULL, -+ 0x6601423b97329582ULL, -+ 0xd041dd676d77eeaaULL, -+ 0x636f91d96ed0b1c5ULL, -+ 0x24c5eb30c5374ef1ULL, -+ 0x97eba78ec690119eULL, -+ 0xab911ee392f8b099ULL, -+ 0x18bf525d915feff6ULL, -+ 0x5f1528b43ab810c2ULL, -+ 0xec3b640a391f4fadULL, -+ 0x27e05a6e926952ccULL, -+ 0x94ce16d091ce0da3ULL, -+ 0xd3646c393a29f297ULL, -+ 0x604a2087398eadf8ULL, -+ 0x5c3099ea6de60cffULL, -+ 0xef1ed5546e415390ULL, -+ 0xa8b4afbdc5a6aca4ULL, -+ 0x1b9ae303c601f3cbULL, -+ 0x56ed3e2f9e224471ULL, -+ 0xe5c372919d851b1eULL, -+ 0xa26908783662e42aULL, -+ 0x114744c635c5bb45ULL, -+ 0x2d3dfdab61ad1a42ULL, -+ 0x9e13b115620a452dULL, -+ 0xd9b9cbfcc9edba19ULL, -+ 0x6a978742ca4ae576ULL, -+ 0xa14cb926613cf817ULL, -+ 0x1262f598629ba778ULL, -+ 0x55c88f71c97c584cULL, -+ 0xe6e6c3cfcadb0723ULL, -+ 0xda9c7aa29eb3a624ULL, -+ 0x69b2361c9d14f94bULL, -+ 0x2e184cf536f3067fULL, -+ 0x9d36004b35545910ULL, -+ 0x2b769f17cf112238ULL, -+ 0x9858d3a9ccb67d57ULL, -+ 0xdff2a94067518263ULL, -+ 0x6cdce5fe64f6dd0cULL, -+ 0x50a65c93309e7c0bULL, -+ 0xe388102d33392364ULL, -+ 0xa4226ac498dedc50ULL, -+ 0x170c267a9b79833fULL, -+ 0xdcd7181e300f9e5eULL, -+ 0x6ff954a033a8c131ULL, -+ 0x28532e49984f3e05ULL, -+ 0x9b7d62f79be8616aULL, -+ 0xa707db9acf80c06dULL, -+ 0x14299724cc279f02ULL, -+ 0x5383edcd67c06036ULL, -+ 0xe0ada17364673f59ULL -+ } -+}; -+ -+ -+/** -+ \brief Initializes the crc seed -+ */ -+static __inline__ uint64_t crc64_init(void) -+{ -+ return CRC64_ECMA_182.initial; -+} -+ -+/** -+ \brief Computes 64 bit the crc -+ \param[in] data Pointer to the Data in the frame -+ \param[in] len Length of the Data -+ \param[in] crc seed -+ \return calculated crc -+ */ -+static __inline__ uint64_t crc64_compute(void const *data, -+ uint32_t len, -+ uint64_t seed) -+{ -+ uint32_t i; -+ uint64_t crc = seed; -+ uint8_t *bdata = (uint8_t *) data; -+ -+ for (i = 0; i < len; i++) -+ crc = -+ CRC64_ECMA_182. -+ table[(crc ^ *bdata++) & CRC64_BYTE_MASK] ^ (crc >> 8); -+ -+ return crc; -+} -+ -+ -+#endif /* __CRC64_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c -@@ -0,0 +1,7538 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_cc.c -+ -+ @Description FM Coarse Classifier implementation -+ *//***************************************************************************/ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "string_ext.h" -+#include "debug_ext.h" -+#include "fm_pcd_ext.h" -+#include "fm_muram_ext.h" -+ -+#include "fm_common.h" -+#include "fm_pcd.h" -+#include "fm_hc.h" -+#include "fm_cc.h" -+#include "crc64.h" -+ -+/****************************************/ -+/* static functions */ -+/****************************************/ -+ -+ -+static t_Error CcRootTryLock(t_Handle h_FmPcdCcTree) -+{ -+ t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcTree; -+ -+ ASSERT_COND(h_FmPcdCcTree); -+ -+ if (FmPcdLockTryLock(p_FmPcdCcTree->p_Lock)) -+ return E_OK; -+ -+ return ERROR_CODE(E_BUSY); -+} -+ -+static void CcRootReleaseLock(t_Handle h_FmPcdCcTree) -+{ -+ t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcTree; -+ -+ ASSERT_COND(h_FmPcdCcTree); -+ -+ FmPcdLockUnlock(p_FmPcdCcTree->p_Lock); -+} -+ -+static void UpdateNodeOwner(t_FmPcdCcNode *p_CcNode, bool add) -+{ -+ uint32_t intFlags; -+ -+ ASSERT_COND(p_CcNode); -+ -+ intFlags = XX_LockIntrSpinlock(p_CcNode->h_Spinlock); -+ -+ if (add) -+ p_CcNode->owners++; -+ else -+ { -+ ASSERT_COND(p_CcNode->owners); -+ p_CcNode->owners--; -+ } -+ -+ XX_UnlockIntrSpinlock(p_CcNode->h_Spinlock, intFlags); -+} -+ -+static __inline__ t_FmPcdStatsObj* DequeueStatsObj(t_List *p_List) -+{ -+ t_FmPcdStatsObj *p_StatsObj = NULL; -+ t_List *p_Next; -+ -+ if (!LIST_IsEmpty(p_List)) -+ { -+ p_Next = LIST_FIRST(p_List); -+ p_StatsObj = LIST_OBJECT(p_Next, t_FmPcdStatsObj, node); -+ ASSERT_COND(p_StatsObj); -+ LIST_DelAndInit(p_Next); -+ } -+ -+ return p_StatsObj; -+} -+ -+static __inline__ void EnqueueStatsObj(t_List *p_List, -+ t_FmPcdStatsObj *p_StatsObj) -+{ -+ LIST_AddToTail(&p_StatsObj->node, p_List); -+} -+ -+static void FreeStatObjects(t_List *p_List, t_Handle h_FmMuram) -+{ -+ t_FmPcdStatsObj *p_StatsObj; -+ -+ while (!LIST_IsEmpty(p_List)) -+ { -+ p_StatsObj = DequeueStatsObj(p_List); -+ ASSERT_COND(p_StatsObj); -+ -+ FM_MURAM_FreeMem(h_FmMuram, p_StatsObj->h_StatsAd); -+ FM_MURAM_FreeMem(h_FmMuram, p_StatsObj->h_StatsCounters); -+ -+ XX_Free(p_StatsObj); -+ } -+} -+ -+static t_FmPcdStatsObj* GetStatsObj(t_FmPcdCcNode *p_CcNode) -+{ -+ t_FmPcdStatsObj* p_StatsObj; -+ t_Handle h_FmMuram; -+ -+ ASSERT_COND(p_CcNode); -+ -+ /* If 'maxNumOfKeys' was passed, all statistics object were preallocated -+ upon node initialization */ -+ if (p_CcNode->maxNumOfKeys) -+ { -+ p_StatsObj = DequeueStatsObj(&p_CcNode->availableStatsLst); -+ } -+ else -+ { -+ h_FmMuram = ((t_FmPcd *)(p_CcNode->h_FmPcd))->h_FmMuram; -+ ASSERT_COND(h_FmMuram); -+ -+ p_StatsObj = XX_Malloc(sizeof(t_FmPcdStatsObj)); -+ if (!p_StatsObj) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("statistics object")); -+ return NULL; -+ } -+ -+ p_StatsObj->h_StatsAd = (t_Handle)FM_MURAM_AllocMem( -+ h_FmMuram, FM_PCD_CC_AD_ENTRY_SIZE, FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_StatsObj->h_StatsAd) -+ { -+ XX_Free(p_StatsObj); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("MURAM allocation for statistics ADs")); -+ return NULL; -+ } -+ MemSet8(p_StatsObj->h_StatsAd, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ p_StatsObj->h_StatsCounters = (t_Handle)FM_MURAM_AllocMem( -+ h_FmMuram, p_CcNode->countersArraySize, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_StatsObj->h_StatsCounters) -+ { -+ FM_MURAM_FreeMem(h_FmMuram, p_StatsObj->h_StatsAd); -+ XX_Free(p_StatsObj); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("MURAM allocation for statistics counters")); -+ return NULL; -+ } -+ MemSet8(p_StatsObj->h_StatsCounters, 0, p_CcNode->countersArraySize); -+ } -+ -+ return p_StatsObj; -+} -+ -+static void PutStatsObj(t_FmPcdCcNode *p_CcNode, t_FmPcdStatsObj *p_StatsObj) -+{ -+ t_Handle h_FmMuram; -+ -+ ASSERT_COND(p_CcNode); -+ ASSERT_COND(p_StatsObj); -+ -+ /* If 'maxNumOfKeys' was passed, all statistics object were preallocated -+ upon node initialization and now will be enqueued back to the list */ -+ if (p_CcNode->maxNumOfKeys) -+ { -+ /* Nullify counters */ -+ MemSet8(p_StatsObj->h_StatsCounters, 0, p_CcNode->countersArraySize); -+ -+ EnqueueStatsObj(&p_CcNode->availableStatsLst, p_StatsObj); -+ } -+ else -+ { -+ h_FmMuram = ((t_FmPcd *)(p_CcNode->h_FmPcd))->h_FmMuram; -+ ASSERT_COND(h_FmMuram); -+ -+ FM_MURAM_FreeMem(h_FmMuram, p_StatsObj->h_StatsAd); -+ FM_MURAM_FreeMem(h_FmMuram, p_StatsObj->h_StatsCounters); -+ -+ XX_Free(p_StatsObj); -+ } -+} -+ -+static void SetStatsCounters(t_AdOfTypeStats *p_StatsAd, -+ uint32_t statsCountersAddr) -+{ -+ uint32_t tmp = (statsCountersAddr & FM_PCD_AD_STATS_COUNTERS_ADDR_MASK); -+ -+ WRITE_UINT32(p_StatsAd->statsTableAddr, tmp); -+} -+ -+ -+static void UpdateStatsAd(t_FmPcdCcStatsParams *p_FmPcdCcStatsParams, -+ t_Handle h_Ad, uint64_t physicalMuramBase) -+{ -+ t_AdOfTypeStats *p_StatsAd; -+ uint32_t statsCountersAddr, nextActionAddr, tmp; -+#if (DPAA_VERSION >= 11) -+ uint32_t frameLengthRangesAddr; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ p_StatsAd = (t_AdOfTypeStats *)p_FmPcdCcStatsParams->h_StatsAd; -+ -+ tmp = FM_PCD_AD_STATS_TYPE; -+ -+#if (DPAA_VERSION >= 11) -+ if (p_FmPcdCcStatsParams->h_StatsFLRs) -+ { -+ frameLengthRangesAddr = (uint32_t)((XX_VirtToPhys( -+ p_FmPcdCcStatsParams->h_StatsFLRs) - physicalMuramBase)); -+ tmp |= (frameLengthRangesAddr & FM_PCD_AD_STATS_FLR_ADDR_MASK); -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ WRITE_UINT32(p_StatsAd->profileTableAddr, tmp); -+ -+ nextActionAddr = (uint32_t)((XX_VirtToPhys(h_Ad) - physicalMuramBase)); -+ tmp = 0; -+ tmp |= (uint32_t)((nextActionAddr << FM_PCD_AD_STATS_NEXT_ACTION_SHIFT) -+ & FM_PCD_AD_STATS_NEXT_ACTION_MASK); -+ tmp |= (FM_PCD_AD_STATS_NAD_EN | FM_PCD_AD_STATS_OP_CODE); -+ -+#if (DPAA_VERSION >= 11) -+ if (p_FmPcdCcStatsParams->h_StatsFLRs) -+ tmp |= FM_PCD_AD_STATS_FLR_EN; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ WRITE_UINT32(p_StatsAd->nextActionIndx, tmp); -+ -+ statsCountersAddr = (uint32_t)((XX_VirtToPhys( -+ p_FmPcdCcStatsParams->h_StatsCounters) - physicalMuramBase)); -+ SetStatsCounters(p_StatsAd, statsCountersAddr); -+} -+ -+static void FillAdOfTypeContLookup(t_Handle h_Ad, -+ t_FmPcdCcStatsParams *p_FmPcdCcStatsParams, -+ t_Handle h_FmPcd, t_Handle p_CcNode, -+ t_Handle h_Manip, t_Handle h_FrmReplic) -+{ -+ t_FmPcdCcNode *p_Node = (t_FmPcdCcNode *)p_CcNode; -+ t_AdOfTypeContLookup *p_AdContLookup = (t_AdOfTypeContLookup *)h_Ad; -+ t_Handle h_TmpAd; -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint32_t tmpReg32; -+ t_Handle p_AdNewPtr = NULL; -+ -+ UNUSED(h_Manip); -+ UNUSED(h_FrmReplic); -+ -+ /* there are 3 cases handled in this routine of building a "Continue lookup" type AD. -+ * Case 1: No Manip. The action descriptor is built within the match table. -+ * p_AdResult = p_AdNewPtr; -+ * Case 2: Manip exists. A new AD is created - p_AdNewPtr. It is initialized -+ * either in the FmPcdManipUpdateAdResultForCc routine or it was already -+ * initialized and returned here. -+ * p_AdResult (within the match table) will be initialized after -+ * this routine returns and point to the existing AD. -+ * Case 3: Manip exists. The action descriptor is built within the match table. -+ * FmPcdManipUpdateAdContLookupForCc returns a NULL p_AdNewPtr. -+ */ -+ -+ /* As default, the "new" ptr is the current one. i.e. the content of the result -+ * AD will be written into the match table itself (case (1))*/ -+ p_AdNewPtr = p_AdContLookup; -+ -+ /* Initialize an action descriptor, if current statistics mode requires an Ad */ -+ if (p_FmPcdCcStatsParams) -+ { -+ ASSERT_COND(p_FmPcdCcStatsParams->h_StatsAd); -+ ASSERT_COND(p_FmPcdCcStatsParams->h_StatsCounters); -+ -+ /* Swapping addresses between statistics Ad and the current lookup AD */ -+ h_TmpAd = p_FmPcdCcStatsParams->h_StatsAd; -+ p_FmPcdCcStatsParams->h_StatsAd = h_Ad; -+ h_Ad = h_TmpAd; -+ -+ p_AdNewPtr = h_Ad; -+ p_AdContLookup = h_Ad; -+ -+ /* Init statistics Ad and connect current lookup AD as 'next action' from statistics Ad */ -+ UpdateStatsAd(p_FmPcdCcStatsParams, h_Ad, p_FmPcd->physicalMuramBase); -+ } -+ -+#if DPAA_VERSION >= 11 -+ if (h_Manip && h_FrmReplic) -+ FmPcdManipUpdateAdContLookupForCc( -+ h_Manip, -+ h_Ad, -+ &p_AdNewPtr, -+ (uint32_t)((XX_VirtToPhys( -+ FrmReplicGroupGetSourceTableDescriptor(h_FrmReplic)) -+ - p_FmPcd->physicalMuramBase))); -+ else -+ if (h_FrmReplic) -+ FrmReplicGroupUpdateAd(h_FrmReplic, h_Ad, &p_AdNewPtr); -+ else -+#endif /* (DPAA_VERSION >= 11) */ -+ if (h_Manip) -+ FmPcdManipUpdateAdContLookupForCc( -+ h_Manip, -+ h_Ad, -+ &p_AdNewPtr, -+ -+#ifdef FM_CAPWAP_SUPPORT -+ /*no check for opcode of manip - this step can be reached only with capwap_applic_specific*/ -+ (uint32_t)((XX_VirtToPhys(p_Node->h_AdTable) - p_FmPcd->physicalMuramBase)) -+#else /* not FM_CAPWAP_SUPPORT */ -+ (uint32_t)((XX_VirtToPhys(p_Node->h_Ad) -+ - p_FmPcd->physicalMuramBase)) -+#endif /* not FM_CAPWAP_SUPPORT */ -+ ); -+ -+ /* if (p_AdNewPtr = NULL) --> Done. (case (3)) */ -+ if (p_AdNewPtr) -+ { -+ /* cases (1) & (2) */ -+ tmpReg32 = 0; -+ tmpReg32 |= FM_PCD_AD_CONT_LOOKUP_TYPE; -+ tmpReg32 |= -+ p_Node->sizeOfExtraction ? ((p_Node->sizeOfExtraction - 1) << 24) : -+ 0; -+ tmpReg32 |= (uint32_t)(XX_VirtToPhys(p_Node->h_AdTable) -+ - p_FmPcd->physicalMuramBase); -+ WRITE_UINT32(p_AdContLookup->ccAdBase, tmpReg32); -+ -+ tmpReg32 = 0; -+ tmpReg32 |= p_Node->numOfKeys << 24; -+ tmpReg32 |= (p_Node->lclMask ? FM_PCD_AD_CONT_LOOKUP_LCL_MASK : 0); -+ tmpReg32 |= -+ p_Node->h_KeysMatchTable ? (uint32_t)(XX_VirtToPhys( -+ p_Node->h_KeysMatchTable) - p_FmPcd->physicalMuramBase) : -+ 0; -+ WRITE_UINT32(p_AdContLookup->matchTblPtr, tmpReg32); -+ -+ tmpReg32 = 0; -+ tmpReg32 |= p_Node->prsArrayOffset << 24; -+ tmpReg32 |= p_Node->offset << 16; -+ tmpReg32 |= p_Node->parseCode; -+ WRITE_UINT32(p_AdContLookup->pcAndOffsets, tmpReg32); -+ -+ MemCpy8((void*)&p_AdContLookup->gmask, p_Node->p_GlblMask, -+ CC_GLBL_MASK_SIZE); -+ } -+} -+ -+static t_Error AllocAndFillAdForContLookupManip(t_Handle h_CcNode) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ uint32_t intFlags; -+ -+ ASSERT_COND(p_CcNode); -+ -+ intFlags = XX_LockIntrSpinlock(p_CcNode->h_Spinlock); -+ -+ if (!p_CcNode->h_Ad) -+ { -+ if (p_CcNode->maxNumOfKeys) -+ p_CcNode->h_Ad = p_CcNode->h_TmpAd; -+ else -+ p_CcNode->h_Ad = (t_Handle)FM_MURAM_AllocMem( -+ ((t_FmPcd *)(p_CcNode->h_FmPcd))->h_FmMuram, -+ FM_PCD_CC_AD_ENTRY_SIZE, FM_PCD_CC_AD_TABLE_ALIGN); -+ -+ XX_UnlockIntrSpinlock(p_CcNode->h_Spinlock, intFlags); -+ -+ if (!p_CcNode->h_Ad) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM allocation for CC action descriptor")); -+ -+ MemSet8(p_CcNode->h_Ad, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ FillAdOfTypeContLookup(p_CcNode->h_Ad, NULL, p_CcNode->h_FmPcd, -+ p_CcNode, NULL, NULL); -+ } -+ else -+ XX_UnlockIntrSpinlock(p_CcNode->h_Spinlock, intFlags); -+ -+ return E_OK; -+} -+ -+static t_Error SetRequiredAction1( -+ t_Handle h_FmPcd, uint32_t requiredAction, -+ t_FmPcdCcKeyAndNextEngineParams *p_CcKeyAndNextEngineParamsTmp, -+ t_Handle h_AdTmp, uint16_t numOfEntries, t_Handle h_Tree) -+{ -+ t_AdOfTypeResult *p_AdTmp = (t_AdOfTypeResult *)h_AdTmp; -+ uint32_t tmpReg32; -+ t_Error err; -+ t_FmPcdCcNode *p_CcNode; -+ int i = 0; -+ uint16_t tmp = 0; -+ uint16_t profileId; -+ uint8_t relativeSchemeId, physicalSchemeId; -+ t_CcNodeInformation ccNodeInfo; -+ -+ for (i = 0; i < numOfEntries; i++) -+ { -+ if (i == 0) -+ h_AdTmp = PTR_MOVE(h_AdTmp, i*FM_PCD_CC_AD_ENTRY_SIZE); -+ else -+ h_AdTmp = PTR_MOVE(h_AdTmp, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ switch (p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.nextEngine) -+ { -+ case (e_FM_PCD_CC): -+ if (requiredAction) -+ { -+ p_CcNode = -+ p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.ccParams.h_CcNode; -+ ASSERT_COND(p_CcNode); -+ if (p_CcNode->shadowAction == requiredAction) -+ break; -+ if ((requiredAction & UPDATE_CC_WITH_TREE) -+ && !(p_CcNode->shadowAction & UPDATE_CC_WITH_TREE)) -+ { -+ -+ memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation)); -+ ccNodeInfo.h_CcNode = h_Tree; -+ EnqueueNodeInfoToRelevantLst(&p_CcNode->ccTreesLst, -+ &ccNodeInfo, NULL); -+ p_CcKeyAndNextEngineParamsTmp[i].shadowAction |= -+ UPDATE_CC_WITH_TREE; -+ } -+ if ((requiredAction & UPDATE_CC_SHADOW_CLEAR) -+ && !(p_CcNode->shadowAction & UPDATE_CC_SHADOW_CLEAR)) -+ { -+ -+ p_CcNode->shadowAction = 0; -+ } -+ -+ if ((requiredAction & UPDATE_CC_WITH_DELETE_TREE) -+ && !(p_CcNode->shadowAction -+ & UPDATE_CC_WITH_DELETE_TREE)) -+ { -+ DequeueNodeInfoFromRelevantLst(&p_CcNode->ccTreesLst, -+ h_Tree, NULL); -+ p_CcKeyAndNextEngineParamsTmp[i].shadowAction |= -+ UPDATE_CC_WITH_DELETE_TREE; -+ } -+ if (p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.nextEngine -+ != e_FM_PCD_INVALID) -+ tmp = (uint8_t)(p_CcNode->numOfKeys + 1); -+ else -+ tmp = p_CcNode->numOfKeys; -+ err = SetRequiredAction1(h_FmPcd, requiredAction, -+ p_CcNode->keyAndNextEngineParams, -+ p_CcNode->h_AdTable, tmp, h_Tree); -+ if (err != E_OK) -+ return err; -+ if (requiredAction != UPDATE_CC_SHADOW_CLEAR) -+ p_CcNode->shadowAction |= requiredAction; -+ } -+ break; -+ -+ case (e_FM_PCD_KG): -+ if ((requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA) -+ && !(p_CcKeyAndNextEngineParamsTmp[i].shadowAction -+ & UPDATE_NIA_ENQ_WITHOUT_DMA)) -+ { -+ physicalSchemeId = -+ FmPcdKgGetSchemeId( -+ p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.kgParams.h_DirectScheme); -+ relativeSchemeId = FmPcdKgGetRelativeSchemeId( -+ h_FmPcd, physicalSchemeId); -+ if (relativeSchemeId == FM_PCD_KG_NUM_OF_SCHEMES) -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG); -+ if (!FmPcdKgIsSchemeValidSw( -+ p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.kgParams.h_DirectScheme)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("Invalid direct scheme.")); -+ if (!KgIsSchemeAlwaysDirect(h_FmPcd, relativeSchemeId)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_STATE, -+ ("For this action scheme has to be direct.")); -+ err = -+ FmPcdKgCcGetSetParams( -+ h_FmPcd, -+ p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.kgParams.h_DirectScheme, -+ requiredAction, 0); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ p_CcKeyAndNextEngineParamsTmp[i].shadowAction |= -+ requiredAction; -+ } -+ break; -+ -+ case (e_FM_PCD_PLCR): -+ if ((requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA) -+ && !(p_CcKeyAndNextEngineParamsTmp[i].shadowAction -+ & UPDATE_NIA_ENQ_WITHOUT_DMA)) -+ { -+ if (!p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.plcrParams.overrideParams) -+ RETURN_ERROR( -+ MAJOR, -+ E_NOT_SUPPORTED, -+ ("In this initialization only overrideFqid can be initialized")); -+ if (!p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.plcrParams.sharedProfile) -+ RETURN_ERROR( -+ MAJOR, -+ E_NOT_SUPPORTED, -+ ("In this initialization only overrideFqid can be initialized")); -+ err = -+ FmPcdPlcrGetAbsoluteIdByProfileParams( -+ h_FmPcd, -+ e_FM_PCD_PLCR_SHARED, -+ NULL, -+ p_CcKeyAndNextEngineParamsTmp[i].nextEngineParams.params.plcrParams.newRelativeProfileId, -+ &profileId); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ err = FmPcdPlcrCcGetSetParams(h_FmPcd, profileId, -+ requiredAction); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ p_CcKeyAndNextEngineParamsTmp[i].shadowAction |= -+ requiredAction; -+ } -+ break; -+ -+ case (e_FM_PCD_DONE): -+ if ((requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA) -+ && !(p_CcKeyAndNextEngineParamsTmp[i].shadowAction -+ & UPDATE_NIA_ENQ_WITHOUT_DMA)) -+ { -+ tmpReg32 = GET_UINT32(p_AdTmp->nia); -+ if ((tmpReg32 & GET_NIA_BMI_AC_ENQ_FRAME(h_FmPcd)) -+ != GET_NIA_BMI_AC_ENQ_FRAME(h_FmPcd)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("Next engine was previously assigned not as PCD_DONE")); -+ tmpReg32 |= NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA; -+ WRITE_UINT32(p_AdTmp->nia, tmpReg32); -+ p_CcKeyAndNextEngineParamsTmp[i].shadowAction |= -+ requiredAction; -+ } -+ break; -+ -+ default: -+ break; -+ } -+ } -+ -+ return E_OK; -+} -+ -+static t_Error SetRequiredAction( -+ t_Handle h_FmPcd, uint32_t requiredAction, -+ t_FmPcdCcKeyAndNextEngineParams *p_CcKeyAndNextEngineParamsTmp, -+ t_Handle h_AdTmp, uint16_t numOfEntries, t_Handle h_Tree) -+{ -+ t_Error err = SetRequiredAction1(h_FmPcd, requiredAction, -+ p_CcKeyAndNextEngineParamsTmp, h_AdTmp, -+ numOfEntries, h_Tree); -+ if (err != E_OK) -+ return err; -+ return SetRequiredAction1(h_FmPcd, UPDATE_CC_SHADOW_CLEAR, -+ p_CcKeyAndNextEngineParamsTmp, h_AdTmp, -+ numOfEntries, h_Tree); -+} -+ -+static t_Error ReleaseModifiedDataStructure( -+ t_Handle h_FmPcd, t_List *h_FmPcdOldPointersLst, -+ t_List *h_FmPcdNewPointersLst, -+ t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalParams, -+ bool useShadowStructs) -+{ -+ t_List *p_Pos; -+ t_Error err = E_OK; -+ t_CcNodeInformation ccNodeInfo, *p_CcNodeInformation; -+ t_Handle h_Muram; -+ t_FmPcdCcNode *p_FmPcdCcNextNode, *p_FmPcdCcWorkingOnNode; -+ t_List *p_UpdateLst; -+ uint32_t intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_AdditionalParams->h_CurrentNode, -+ E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(h_FmPcdOldPointersLst, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(h_FmPcdNewPointersLst, E_INVALID_HANDLE); -+ -+ /* We don't update subtree of the new node with new tree because it was done in the previous stage */ -+ if (p_AdditionalParams->h_NodeForAdd) -+ { -+ p_FmPcdCcNextNode = (t_FmPcdCcNode*)p_AdditionalParams->h_NodeForAdd; -+ -+ if (!p_AdditionalParams->tree) -+ p_UpdateLst = &p_FmPcdCcNextNode->ccPrevNodesLst; -+ else -+ p_UpdateLst = &p_FmPcdCcNextNode->ccTreeIdLst; -+ -+ p_CcNodeInformation = FindNodeInfoInReleventLst( -+ p_UpdateLst, p_AdditionalParams->h_CurrentNode, -+ p_FmPcdCcNextNode->h_Spinlock); -+ -+ if (p_CcNodeInformation) -+ p_CcNodeInformation->index++; -+ else -+ { -+ memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation)); -+ ccNodeInfo.h_CcNode = (t_Handle)p_AdditionalParams->h_CurrentNode; -+ ccNodeInfo.index = 1; -+ EnqueueNodeInfoToRelevantLst(p_UpdateLst, &ccNodeInfo, -+ p_FmPcdCcNextNode->h_Spinlock); -+ } -+ if (p_AdditionalParams->h_ManipForAdd) -+ { -+ p_CcNodeInformation = FindNodeInfoInReleventLst( -+ FmPcdManipGetNodeLstPointedOnThisManip( -+ p_AdditionalParams->h_ManipForAdd), -+ p_AdditionalParams->h_CurrentNode, -+ FmPcdManipGetSpinlock(p_AdditionalParams->h_ManipForAdd)); -+ -+ if (p_CcNodeInformation) -+ p_CcNodeInformation->index++; -+ else -+ { -+ memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation)); -+ ccNodeInfo.h_CcNode = -+ (t_Handle)p_AdditionalParams->h_CurrentNode; -+ ccNodeInfo.index = 1; -+ EnqueueNodeInfoToRelevantLst( -+ FmPcdManipGetNodeLstPointedOnThisManip( -+ p_AdditionalParams->h_ManipForAdd), -+ &ccNodeInfo, -+ FmPcdManipGetSpinlock( -+ p_AdditionalParams->h_ManipForAdd)); -+ } -+ } -+ } -+ -+ if (p_AdditionalParams->h_NodeForRmv) -+ { -+ p_FmPcdCcNextNode = (t_FmPcdCcNode*)p_AdditionalParams->h_NodeForRmv; -+ -+ if (!p_AdditionalParams->tree) -+ { -+ p_UpdateLst = &p_FmPcdCcNextNode->ccPrevNodesLst; -+ p_FmPcdCcWorkingOnNode = -+ (t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode); -+ -+ for (p_Pos = LIST_FIRST(&p_FmPcdCcWorkingOnNode->ccTreesLst); -+ p_Pos != (&p_FmPcdCcWorkingOnNode->ccTreesLst); p_Pos = -+ LIST_NEXT(p_Pos)) -+ { -+ p_CcNodeInformation = CC_NODE_F_OBJECT(p_Pos); -+ -+ ASSERT_COND(p_CcNodeInformation->h_CcNode); -+ -+ err = -+ SetRequiredAction( -+ h_FmPcd, -+ UPDATE_CC_WITH_DELETE_TREE, -+ &((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->keyAndNextEngineParams[p_AdditionalParams->savedKeyIndex], -+ PTR_MOVE(((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->h_AdTable, p_AdditionalParams->savedKeyIndex*FM_PCD_CC_AD_ENTRY_SIZE), -+ 1, p_CcNodeInformation->h_CcNode); -+ } -+ } -+ else -+ { -+ p_UpdateLst = &p_FmPcdCcNextNode->ccTreeIdLst; -+ -+ err = -+ SetRequiredAction( -+ h_FmPcd, -+ UPDATE_CC_WITH_DELETE_TREE, -+ &((t_FmPcdCcTree *)(p_AdditionalParams->h_CurrentNode))->keyAndNextEngineParams[p_AdditionalParams->savedKeyIndex], -+ UINT_TO_PTR(((t_FmPcdCcTree *)(p_AdditionalParams->h_CurrentNode))->ccTreeBaseAddr + p_AdditionalParams->savedKeyIndex*FM_PCD_CC_AD_ENTRY_SIZE), -+ 1, p_AdditionalParams->h_CurrentNode); -+ } -+ if (err) -+ return err; -+ -+ /* We remove from the subtree of the removed node tree because it wasn't done in the previous stage -+ Update ccPrevNodesLst or ccTreeIdLst of the removed node -+ Update of the node owner */ -+ p_CcNodeInformation = FindNodeInfoInReleventLst( -+ p_UpdateLst, p_AdditionalParams->h_CurrentNode, -+ p_FmPcdCcNextNode->h_Spinlock); -+ -+ ASSERT_COND(p_CcNodeInformation); -+ ASSERT_COND(p_CcNodeInformation->index); -+ -+ p_CcNodeInformation->index--; -+ -+ if (p_CcNodeInformation->index == 0) -+ DequeueNodeInfoFromRelevantLst(p_UpdateLst, -+ p_AdditionalParams->h_CurrentNode, -+ p_FmPcdCcNextNode->h_Spinlock); -+ -+ UpdateNodeOwner(p_FmPcdCcNextNode, FALSE); -+ -+ if (p_AdditionalParams->h_ManipForRmv) -+ { -+ p_CcNodeInformation = FindNodeInfoInReleventLst( -+ FmPcdManipGetNodeLstPointedOnThisManip( -+ p_AdditionalParams->h_ManipForRmv), -+ p_AdditionalParams->h_CurrentNode, -+ FmPcdManipGetSpinlock(p_AdditionalParams->h_ManipForRmv)); -+ -+ ASSERT_COND(p_CcNodeInformation); -+ ASSERT_COND(p_CcNodeInformation->index); -+ -+ p_CcNodeInformation->index--; -+ -+ if (p_CcNodeInformation->index == 0) -+ DequeueNodeInfoFromRelevantLst( -+ FmPcdManipGetNodeLstPointedOnThisManip( -+ p_AdditionalParams->h_ManipForRmv), -+ p_AdditionalParams->h_CurrentNode, -+ FmPcdManipGetSpinlock( -+ p_AdditionalParams->h_ManipForRmv)); -+ } -+ } -+ -+ if (p_AdditionalParams->h_ManipForRmv) -+ FmPcdManipUpdateOwner(p_AdditionalParams->h_ManipForRmv, FALSE); -+ -+ if (p_AdditionalParams->p_StatsObjForRmv) -+ PutStatsObj((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode), -+ p_AdditionalParams->p_StatsObjForRmv); -+ -+#if (DPAA_VERSION >= 11) -+ if (p_AdditionalParams->h_FrmReplicForRmv) -+ FrmReplicGroupUpdateOwner(p_AdditionalParams->h_FrmReplicForRmv, -+ FALSE/* remove */); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ if (!useShadowStructs) -+ { -+ h_Muram = FmPcdGetMuramHandle(h_FmPcd); -+ ASSERT_COND(h_Muram); -+ -+ if ((p_AdditionalParams->tree && !((t_FmPcd *)h_FmPcd)->p_CcShadow) -+ || (!p_AdditionalParams->tree -+ && !((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->maxNumOfKeys)) -+ { -+ /* We release new AD which was allocated and updated for copy from to actual AD */ -+ for (p_Pos = LIST_FIRST(h_FmPcdNewPointersLst); -+ p_Pos != (h_FmPcdNewPointersLst); p_Pos = LIST_NEXT(p_Pos)) -+ { -+ -+ p_CcNodeInformation = CC_NODE_F_OBJECT(p_Pos); -+ ASSERT_COND(p_CcNodeInformation->h_CcNode); -+ FM_MURAM_FreeMem(h_Muram, p_CcNodeInformation->h_CcNode); -+ } -+ } -+ -+ /* Free Old data structure if it has to be freed - new data structure was allocated*/ -+ if (p_AdditionalParams->p_AdTableOld) -+ FM_MURAM_FreeMem(h_Muram, p_AdditionalParams->p_AdTableOld); -+ -+ if (p_AdditionalParams->p_KeysMatchTableOld) -+ FM_MURAM_FreeMem(h_Muram, p_AdditionalParams->p_KeysMatchTableOld); -+ } -+ -+ /* Update current modified node with changed fields if it's required*/ -+ if (!p_AdditionalParams->tree) -+ { -+ if (p_AdditionalParams->p_AdTableNew) -+ ((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->h_AdTable = -+ p_AdditionalParams->p_AdTableNew; -+ -+ if (p_AdditionalParams->p_KeysMatchTableNew) -+ ((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->h_KeysMatchTable = -+ p_AdditionalParams->p_KeysMatchTableNew; -+ -+ /* Locking node's spinlock before updating 'keys and next engine' structure, -+ as it maybe used to retrieve keys statistics */ -+ intFlags = -+ XX_LockIntrSpinlock( -+ ((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->h_Spinlock); -+ -+ ((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->numOfKeys = -+ p_AdditionalParams->numOfKeys; -+ -+ memcpy(((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->keyAndNextEngineParams, -+ &p_AdditionalParams->keyAndNextEngineParams, -+ sizeof(t_FmPcdCcKeyAndNextEngineParams) * (CC_MAX_NUM_OF_KEYS)); -+ -+ XX_UnlockIntrSpinlock( -+ ((t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode))->h_Spinlock, -+ intFlags); -+ } -+ else -+ { -+ uint8_t numEntries = -+ ((t_FmPcdCcTree *)(p_AdditionalParams->h_CurrentNode))->numOfEntries; -+ ASSERT_COND(numEntries < FM_PCD_MAX_NUM_OF_CC_GROUPS); -+ memcpy(&((t_FmPcdCcTree *)(p_AdditionalParams->h_CurrentNode))->keyAndNextEngineParams, -+ &p_AdditionalParams->keyAndNextEngineParams, -+ sizeof(t_FmPcdCcKeyAndNextEngineParams) * numEntries); -+ } -+ -+ ReleaseLst(h_FmPcdOldPointersLst); -+ ReleaseLst(h_FmPcdNewPointersLst); -+ -+ XX_Free(p_AdditionalParams); -+ -+ return E_OK; -+} -+ -+static t_Handle BuildNewAd( -+ t_Handle h_Ad, -+ t_FmPcdModifyCcKeyAdditionalParams *p_FmPcdModifyCcKeyAdditionalParams, -+ t_FmPcdCcNode *p_CcNode, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams) -+{ -+ t_FmPcdCcNode *p_FmPcdCcNodeTmp; -+ t_Handle h_OrigAd = NULL; -+ -+ p_FmPcdCcNodeTmp = (t_FmPcdCcNode*)XX_Malloc(sizeof(t_FmPcdCcNode)); -+ if (!p_FmPcdCcNodeTmp) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("p_FmPcdCcNodeTmp")); -+ return NULL; -+ } -+ memset(p_FmPcdCcNodeTmp, 0, sizeof(t_FmPcdCcNode)); -+ -+ p_FmPcdCcNodeTmp->numOfKeys = p_FmPcdModifyCcKeyAdditionalParams->numOfKeys; -+ p_FmPcdCcNodeTmp->h_KeysMatchTable = -+ p_FmPcdModifyCcKeyAdditionalParams->p_KeysMatchTableNew; -+ p_FmPcdCcNodeTmp->h_AdTable = -+ p_FmPcdModifyCcKeyAdditionalParams->p_AdTableNew; -+ -+ p_FmPcdCcNodeTmp->lclMask = p_CcNode->lclMask; -+ p_FmPcdCcNodeTmp->parseCode = p_CcNode->parseCode; -+ p_FmPcdCcNodeTmp->offset = p_CcNode->offset; -+ p_FmPcdCcNodeTmp->prsArrayOffset = p_CcNode->prsArrayOffset; -+ p_FmPcdCcNodeTmp->ctrlFlow = p_CcNode->ctrlFlow; -+ p_FmPcdCcNodeTmp->ccKeySizeAccExtraction = p_CcNode->ccKeySizeAccExtraction; -+ p_FmPcdCcNodeTmp->sizeOfExtraction = p_CcNode->sizeOfExtraction; -+ p_FmPcdCcNodeTmp->glblMaskSize = p_CcNode->glblMaskSize; -+ p_FmPcdCcNodeTmp->p_GlblMask = p_CcNode->p_GlblMask; -+ -+ if (p_FmPcdCcNextEngineParams->nextEngine == e_FM_PCD_CC) -+ { -+ if (p_FmPcdCcNextEngineParams->h_Manip) -+ { -+ h_OrigAd = p_CcNode->h_Ad; -+ if (AllocAndFillAdForContLookupManip( -+ p_FmPcdCcNextEngineParams->params.ccParams.h_CcNode) -+ != E_OK) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ XX_Free(p_FmPcdCcNodeTmp); -+ return NULL; -+ } -+ } -+ FillAdOfTypeContLookup(h_Ad, NULL, p_CcNode->h_FmPcd, p_FmPcdCcNodeTmp, -+ h_OrigAd ? NULL : p_FmPcdCcNextEngineParams->h_Manip, NULL); -+ } -+ -+#if (DPAA_VERSION >= 11) -+ if ((p_FmPcdCcNextEngineParams->nextEngine == e_FM_PCD_FR) -+ && (p_FmPcdCcNextEngineParams->params.frParams.h_FrmReplic)) -+ { -+ FillAdOfTypeContLookup( -+ h_Ad, NULL, p_CcNode->h_FmPcd, p_FmPcdCcNodeTmp, -+ p_FmPcdCcNextEngineParams->h_Manip, -+ p_FmPcdCcNextEngineParams->params.frParams.h_FrmReplic); -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ XX_Free(p_FmPcdCcNodeTmp); -+ -+ return E_OK; -+} -+ -+static t_Error DynamicChangeHc( -+ t_Handle h_FmPcd, t_List *h_OldPointersLst, t_List *h_NewPointersLst, -+ t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalParams, -+ bool useShadowStructs) -+{ -+ t_List *p_PosOld, *p_PosNew; -+ uint32_t oldAdAddrOffset, newAdAddrOffset; -+ uint16_t i = 0; -+ t_Error err = E_OK; -+ uint8_t numOfModifiedPtr; -+ -+ ASSERT_COND(h_FmPcd); -+ ASSERT_COND(h_OldPointersLst); -+ ASSERT_COND(h_NewPointersLst); -+ -+ numOfModifiedPtr = (uint8_t)LIST_NumOfObjs(h_OldPointersLst); -+ -+ if (numOfModifiedPtr) -+ { -+ p_PosNew = LIST_FIRST(h_NewPointersLst); -+ p_PosOld = LIST_FIRST(h_OldPointersLst); -+ -+ /* Retrieve address of new AD */ -+ newAdAddrOffset = FmPcdCcGetNodeAddrOffsetFromNodeInfo(h_FmPcd, -+ p_PosNew); -+ if (newAdAddrOffset == (uint32_t)ILLEGAL_BASE) -+ { -+ ReleaseModifiedDataStructure(h_FmPcd, h_OldPointersLst, -+ h_NewPointersLst, -+ p_AdditionalParams, useShadowStructs); -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("New AD address")); -+ } -+ -+ for (i = 0; i < numOfModifiedPtr; i++) -+ { -+ /* Retrieve address of current AD */ -+ oldAdAddrOffset = FmPcdCcGetNodeAddrOffsetFromNodeInfo(h_FmPcd, -+ p_PosOld); -+ if (oldAdAddrOffset == (uint32_t)ILLEGAL_BASE) -+ { -+ ReleaseModifiedDataStructure(h_FmPcd, h_OldPointersLst, -+ h_NewPointersLst, -+ p_AdditionalParams, -+ useShadowStructs); -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Old AD address")); -+ } -+ -+ /* Invoke host command to copy from new AD to old AD */ -+ err = FmHcPcdCcDoDynamicChange(((t_FmPcd *)h_FmPcd)->h_Hc, -+ oldAdAddrOffset, newAdAddrOffset); -+ if (err) -+ { -+ ReleaseModifiedDataStructure(h_FmPcd, h_OldPointersLst, -+ h_NewPointersLst, -+ p_AdditionalParams, -+ useShadowStructs); -+ RETURN_ERROR( -+ MAJOR, -+ err, -+ ("For part of nodes changes are done - situation is danger")); -+ } -+ -+ p_PosOld = LIST_NEXT(p_PosOld); -+ } -+ } -+ return E_OK; -+} -+ -+static t_Error DoDynamicChange( -+ t_Handle h_FmPcd, t_List *h_OldPointersLst, t_List *h_NewPointersLst, -+ t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalParams, -+ bool useShadowStructs) -+{ -+ t_FmPcdCcNode *p_CcNode = -+ (t_FmPcdCcNode *)(p_AdditionalParams->h_CurrentNode); -+ t_List *p_PosNew; -+ t_CcNodeInformation *p_CcNodeInfo; -+ t_FmPcdCcNextEngineParams nextEngineParams; -+ t_Handle h_Ad; -+ uint32_t keySize; -+ t_Error err = E_OK; -+ uint8_t numOfModifiedPtr; -+ -+ ASSERT_COND(h_FmPcd); -+ -+ memset(&nextEngineParams, 0, sizeof(t_FmPcdCcNextEngineParams)); -+ -+ numOfModifiedPtr = (uint8_t)LIST_NumOfObjs(h_OldPointersLst); -+ -+ if (numOfModifiedPtr) -+ { -+ -+ p_PosNew = LIST_FIRST(h_NewPointersLst); -+ -+ /* Invoke host-command to copy from the new Ad to existing Ads */ -+ err = DynamicChangeHc(h_FmPcd, h_OldPointersLst, h_NewPointersLst, -+ p_AdditionalParams, useShadowStructs); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (useShadowStructs) -+ { -+ /* When the host-command above has ended, the old structures are 'free'and we can update -+ them by copying from the new shadow structures. */ -+ if (p_CcNode->lclMask) -+ keySize = (uint32_t)(2 * p_CcNode->ccKeySizeAccExtraction); -+ else -+ keySize = p_CcNode->ccKeySizeAccExtraction; -+ -+ MemCpy8(p_AdditionalParams->p_KeysMatchTableOld, -+ p_AdditionalParams->p_KeysMatchTableNew, -+ p_CcNode->maxNumOfKeys * keySize * sizeof(uint8_t)); -+ -+ MemCpy8( -+ p_AdditionalParams->p_AdTableOld, -+ p_AdditionalParams->p_AdTableNew, -+ (uint32_t)((p_CcNode->maxNumOfKeys + 1) -+ * FM_PCD_CC_AD_ENTRY_SIZE)); -+ -+ /* Retrieve the address of the allocated Ad */ -+ p_CcNodeInfo = CC_NODE_F_OBJECT(p_PosNew); -+ h_Ad = p_CcNodeInfo->h_CcNode; -+ -+ /* Build a new Ad that holds the old (now updated) structures */ -+ p_AdditionalParams->p_KeysMatchTableNew = -+ p_AdditionalParams->p_KeysMatchTableOld; -+ p_AdditionalParams->p_AdTableNew = p_AdditionalParams->p_AdTableOld; -+ -+ nextEngineParams.nextEngine = e_FM_PCD_CC; -+ nextEngineParams.params.ccParams.h_CcNode = (t_Handle)p_CcNode; -+ -+ BuildNewAd(h_Ad, p_AdditionalParams, p_CcNode, &nextEngineParams); -+ -+ /* HC to copy from the new Ad (old updated structures) to current Ad (uses shadow structures) */ -+ err = DynamicChangeHc(h_FmPcd, h_OldPointersLst, h_NewPointersLst, -+ p_AdditionalParams, useShadowStructs); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ } -+ -+ err = ReleaseModifiedDataStructure(h_FmPcd, h_OldPointersLst, -+ h_NewPointersLst, -+ p_AdditionalParams, useShadowStructs); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+#ifdef FM_CAPWAP_SUPPORT -+static bool IsCapwapApplSpecific(t_Handle h_Node) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_Node; -+ bool isManipForCapwapApplSpecificBuild = FALSE; -+ int i = 0; -+ -+ ASSERT_COND(h_Node); -+ /* assumption that this function called only for INDEXED_FLOW_ID - so no miss*/ -+ for (i = 0; i < p_CcNode->numOfKeys; i++) -+ { -+ if ( p_CcNode->keyAndNextEngineParams[i].nextEngineParams.h_Manip && -+ FmPcdManipIsCapwapApplSpecific(p_CcNode->keyAndNextEngineParams[i].nextEngineParams.h_Manip)) -+ { -+ isManipForCapwapApplSpecificBuild = TRUE; -+ break; -+ } -+ } -+ return isManipForCapwapApplSpecificBuild; -+ -+} -+#endif /* FM_CAPWAP_SUPPORT */ -+ -+static t_Error CcUpdateParam( -+ t_Handle h_FmPcd, t_Handle h_PcdParams, t_Handle h_FmPort, -+ t_FmPcdCcKeyAndNextEngineParams *p_CcKeyAndNextEngineParams, -+ uint16_t numOfEntries, t_Handle h_Ad, bool validate, uint16_t level, -+ t_Handle h_FmTree, bool modify) -+{ -+ t_FmPcdCcNode *p_CcNode; -+ t_Error err; -+ uint16_t tmp = 0; -+ int i = 0; -+ t_FmPcdCcTree *p_CcTree = (t_FmPcdCcTree *)h_FmTree; -+ -+ level++; -+ -+ if (p_CcTree->h_IpReassemblyManip) -+ { -+ err = FmPcdManipUpdate(h_FmPcd, h_PcdParams, h_FmPort, -+ p_CcTree->h_IpReassemblyManip, NULL, validate, -+ level, h_FmTree, modify); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ if (p_CcTree->h_CapwapReassemblyManip) -+ { -+ err = FmPcdManipUpdate(h_FmPcd, h_PcdParams, h_FmPort, -+ p_CcTree->h_CapwapReassemblyManip, NULL, validate, -+ level, h_FmTree, modify); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ if (numOfEntries) -+ { -+ for (i = 0; i < numOfEntries; i++) -+ { -+ if (i == 0) -+ h_Ad = PTR_MOVE(h_Ad, i*FM_PCD_CC_AD_ENTRY_SIZE); -+ else -+ h_Ad = PTR_MOVE(h_Ad, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ if (p_CcKeyAndNextEngineParams[i].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ { -+ p_CcNode = -+ p_CcKeyAndNextEngineParams[i].nextEngineParams.params.ccParams.h_CcNode; -+ ASSERT_COND(p_CcNode); -+ -+ if (p_CcKeyAndNextEngineParams[i].nextEngineParams.h_Manip) -+ { -+ err = -+ FmPcdManipUpdate( -+ h_FmPcd, -+ NULL, -+ h_FmPort, -+ p_CcKeyAndNextEngineParams[i].nextEngineParams.h_Manip, -+ h_Ad, validate, level, h_FmTree, modify); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ if (p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.nextEngine -+ != e_FM_PCD_INVALID) -+ tmp = (uint8_t)(p_CcNode->numOfKeys + 1); -+ else -+ tmp = p_CcNode->numOfKeys; -+ -+ err = CcUpdateParam(h_FmPcd, h_PcdParams, h_FmPort, -+ p_CcNode->keyAndNextEngineParams, tmp, -+ p_CcNode->h_AdTable, validate, level, -+ h_FmTree, modify); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ else -+ { -+ if (p_CcKeyAndNextEngineParams[i].nextEngineParams.h_Manip) -+ { -+ err = -+ FmPcdManipUpdate( -+ h_FmPcd, -+ NULL, -+ h_FmPort, -+ p_CcKeyAndNextEngineParams[i].nextEngineParams.h_Manip, -+ h_Ad, validate, level, h_FmTree, modify); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ } -+ } -+ } -+ -+ return E_OK; -+} -+ -+static ccPrivateInfo_t IcDefineCode(t_FmPcdCcNodeParams *p_CcNodeParam) -+{ -+ switch (p_CcNodeParam->extractCcParams.extractNonHdr.action) -+ { -+ case (e_FM_PCD_ACTION_EXACT_MATCH): -+ switch (p_CcNodeParam->extractCcParams.extractNonHdr.src) -+ { -+ case (e_FM_PCD_EXTRACT_FROM_KEY): -+ return CC_PRIVATE_INFO_IC_KEY_EXACT_MATCH; -+ case (e_FM_PCD_EXTRACT_FROM_HASH): -+ return CC_PRIVATE_INFO_IC_HASH_EXACT_MATCH; -+ default: -+ return CC_PRIVATE_INFO_NONE; -+ } -+ -+ case (e_FM_PCD_ACTION_INDEXED_LOOKUP): -+ switch (p_CcNodeParam->extractCcParams.extractNonHdr.src) -+ { -+ case (e_FM_PCD_EXTRACT_FROM_HASH): -+ return CC_PRIVATE_INFO_IC_HASH_INDEX_LOOKUP; -+ case (e_FM_PCD_EXTRACT_FROM_FLOW_ID): -+ return CC_PRIVATE_INFO_IC_DEQ_FQID_INDEX_LOOKUP; -+ default: -+ return CC_PRIVATE_INFO_NONE; -+ } -+ -+ default: -+ break; -+ } -+ -+ return CC_PRIVATE_INFO_NONE; -+} -+ -+static t_CcNodeInformation * DequeueAdditionalInfoFromRelevantLst( -+ t_List *p_List) -+{ -+ t_CcNodeInformation *p_CcNodeInfo = NULL; -+ -+ if (!LIST_IsEmpty(p_List)) -+ { -+ p_CcNodeInfo = CC_NODE_F_OBJECT(p_List->p_Next); -+ LIST_DelAndInit(&p_CcNodeInfo->node); -+ } -+ -+ return p_CcNodeInfo; -+} -+ -+void ReleaseLst(t_List *p_List) -+{ -+ t_CcNodeInformation *p_CcNodeInfo = NULL; -+ -+ if (!LIST_IsEmpty(p_List)) -+ { -+ p_CcNodeInfo = DequeueAdditionalInfoFromRelevantLst(p_List); -+ while (p_CcNodeInfo) -+ { -+ XX_Free(p_CcNodeInfo); -+ p_CcNodeInfo = DequeueAdditionalInfoFromRelevantLst(p_List); -+ } -+ } -+ -+ LIST_Del(p_List); -+} -+ -+static void DeleteNode(t_FmPcdCcNode *p_CcNode) -+{ -+ uint32_t i; -+ -+ if (!p_CcNode) -+ return; -+ -+ if (p_CcNode->p_GlblMask) -+ { -+ XX_Free(p_CcNode->p_GlblMask); -+ p_CcNode->p_GlblMask = NULL; -+ } -+ -+ if (p_CcNode->h_KeysMatchTable) -+ { -+ FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_CcNode->h_FmPcd), -+ p_CcNode->h_KeysMatchTable); -+ p_CcNode->h_KeysMatchTable = NULL; -+ } -+ -+ if (p_CcNode->h_AdTable) -+ { -+ FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_CcNode->h_FmPcd), -+ p_CcNode->h_AdTable); -+ p_CcNode->h_AdTable = NULL; -+ } -+ -+ if (p_CcNode->h_Ad) -+ { -+ FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_CcNode->h_FmPcd), -+ p_CcNode->h_Ad); -+ p_CcNode->h_Ad = NULL; -+ p_CcNode->h_TmpAd = NULL; -+ } -+ -+ if (p_CcNode->h_StatsFLRs) -+ { -+ FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_CcNode->h_FmPcd), -+ p_CcNode->h_StatsFLRs); -+ p_CcNode->h_StatsFLRs = NULL; -+ } -+ -+ if (p_CcNode->h_Spinlock) -+ { -+ XX_FreeSpinlock(p_CcNode->h_Spinlock); -+ p_CcNode->h_Spinlock = NULL; -+ } -+ -+ /* Restore the original counters pointer instead of the mutual pointer (mutual to all hash buckets) */ -+ if (p_CcNode->isHashBucket -+ && (p_CcNode->statisticsMode != e_FM_PCD_CC_STATS_MODE_NONE)) -+ p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].p_StatsObj->h_StatsCounters = -+ p_CcNode->h_PrivMissStatsCounters; -+ -+ /* Releasing all currently used statistics objects, including 'miss' entry */ -+ for (i = 0; i < p_CcNode->numOfKeys + 1; i++) -+ if (p_CcNode->keyAndNextEngineParams[i].p_StatsObj) -+ PutStatsObj(p_CcNode, -+ p_CcNode->keyAndNextEngineParams[i].p_StatsObj); -+ -+ if (!LIST_IsEmpty(&p_CcNode->availableStatsLst)) -+ { -+ t_Handle h_FmMuram = FmPcdGetMuramHandle(p_CcNode->h_FmPcd); -+ ASSERT_COND(h_FmMuram); -+ -+ FreeStatObjects(&p_CcNode->availableStatsLst, h_FmMuram); -+ } -+ -+ LIST_Del(&p_CcNode->availableStatsLst); -+ -+ ReleaseLst(&p_CcNode->ccPrevNodesLst); -+ ReleaseLst(&p_CcNode->ccTreeIdLst); -+ ReleaseLst(&p_CcNode->ccTreesLst); -+ -+ XX_Free(p_CcNode); -+} -+ -+static void DeleteTree(t_FmPcdCcTree *p_FmPcdTree, t_FmPcd *p_FmPcd) -+{ -+ if (p_FmPcdTree) -+ { -+ if (p_FmPcdTree->ccTreeBaseAddr) -+ { -+ FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_FmPcd), -+ UINT_TO_PTR(p_FmPcdTree->ccTreeBaseAddr)); -+ p_FmPcdTree->ccTreeBaseAddr = 0; -+ } -+ -+ ReleaseLst(&p_FmPcdTree->fmPortsLst); -+ -+ XX_Free(p_FmPcdTree); -+ } -+} -+ -+static void GetCcExtractKeySize(uint8_t parseCodeRealSize, -+ uint8_t *parseCodeCcSize) -+{ -+ if ((parseCodeRealSize > 0) && (parseCodeRealSize < 2)) -+ *parseCodeCcSize = 1; -+ else -+ if (parseCodeRealSize == 2) -+ *parseCodeCcSize = 2; -+ else -+ if ((parseCodeRealSize > 2) && (parseCodeRealSize <= 4)) -+ *parseCodeCcSize = 4; -+ else -+ if ((parseCodeRealSize > 4) && (parseCodeRealSize <= 8)) -+ *parseCodeCcSize = 8; -+ else -+ if ((parseCodeRealSize > 8) && (parseCodeRealSize <= 16)) -+ *parseCodeCcSize = 16; -+ else -+ if ((parseCodeRealSize > 16) -+ && (parseCodeRealSize <= 24)) -+ *parseCodeCcSize = 24; -+ else -+ if ((parseCodeRealSize > 24) -+ && (parseCodeRealSize <= 32)) -+ *parseCodeCcSize = 32; -+ else -+ if ((parseCodeRealSize > 32) -+ && (parseCodeRealSize <= 40)) -+ *parseCodeCcSize = 40; -+ else -+ if ((parseCodeRealSize > 40) -+ && (parseCodeRealSize <= 48)) -+ *parseCodeCcSize = 48; -+ else -+ if ((parseCodeRealSize > 48) -+ && (parseCodeRealSize <= 56)) -+ *parseCodeCcSize = 56; -+ else -+ *parseCodeCcSize = 0; -+} -+ -+static void GetSizeHeaderField(e_NetHeaderType hdr, t_FmPcdFields field, -+ uint8_t *parseCodeRealSize) -+{ -+ switch (hdr) -+ { -+ case (HEADER_TYPE_ETH): -+ switch (field.eth) -+ { -+ case (NET_HEADER_FIELD_ETH_DA): -+ *parseCodeRealSize = 6; -+ break; -+ -+ case (NET_HEADER_FIELD_ETH_SA): -+ *parseCodeRealSize = 6; -+ break; -+ -+ case (NET_HEADER_FIELD_ETH_TYPE): -+ *parseCodeRealSize = 2; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported1")); -+ *parseCodeRealSize = CC_SIZE_ILLEGAL; -+ break; -+ } -+ break; -+ -+ case (HEADER_TYPE_PPPoE): -+ switch (field.pppoe) -+ { -+ case (NET_HEADER_FIELD_PPPoE_PID): -+ *parseCodeRealSize = 2; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported1")); -+ *parseCodeRealSize = CC_SIZE_ILLEGAL; -+ break; -+ } -+ break; -+ -+ case (HEADER_TYPE_VLAN): -+ switch (field.vlan) -+ { -+ case (NET_HEADER_FIELD_VLAN_TCI): -+ *parseCodeRealSize = 2; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported2")); -+ *parseCodeRealSize = CC_SIZE_ILLEGAL; -+ break; -+ } -+ break; -+ -+ case (HEADER_TYPE_MPLS): -+ switch (field.mpls) -+ { -+ case (NET_HEADER_FIELD_MPLS_LABEL_STACK): -+ *parseCodeRealSize = 4; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported3")); -+ *parseCodeRealSize = CC_SIZE_ILLEGAL; -+ break; -+ } -+ break; -+ -+ case (HEADER_TYPE_IPv4): -+ switch (field.ipv4) -+ { -+ case (NET_HEADER_FIELD_IPv4_DST_IP): -+ case (NET_HEADER_FIELD_IPv4_SRC_IP): -+ *parseCodeRealSize = 4; -+ break; -+ -+ case (NET_HEADER_FIELD_IPv4_TOS): -+ case (NET_HEADER_FIELD_IPv4_PROTO): -+ *parseCodeRealSize = 1; -+ break; -+ -+ case (NET_HEADER_FIELD_IPv4_DST_IP -+ | NET_HEADER_FIELD_IPv4_SRC_IP): -+ *parseCodeRealSize = 8; -+ break; -+ -+ case (NET_HEADER_FIELD_IPv4_TTL): -+ *parseCodeRealSize = 1; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported4")); -+ *parseCodeRealSize = CC_SIZE_ILLEGAL; -+ break; -+ } -+ break; -+ -+ case (HEADER_TYPE_IPv6): -+ switch (field.ipv6) -+ { -+ case (NET_HEADER_FIELD_IPv6_VER | NET_HEADER_FIELD_IPv6_FL -+ | NET_HEADER_FIELD_IPv6_TC): -+ *parseCodeRealSize = 4; -+ break; -+ -+ case (NET_HEADER_FIELD_IPv6_NEXT_HDR): -+ case (NET_HEADER_FIELD_IPv6_HOP_LIMIT): -+ *parseCodeRealSize = 1; -+ break; -+ -+ case (NET_HEADER_FIELD_IPv6_DST_IP): -+ case (NET_HEADER_FIELD_IPv6_SRC_IP): -+ *parseCodeRealSize = 16; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported5")); -+ *parseCodeRealSize = CC_SIZE_ILLEGAL; -+ break; -+ } -+ break; -+ -+ case (HEADER_TYPE_IP): -+ switch (field.ip) -+ { -+ case (NET_HEADER_FIELD_IP_DSCP): -+ case (NET_HEADER_FIELD_IP_PROTO): -+ *parseCodeRealSize = 1; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported5")); -+ *parseCodeRealSize = CC_SIZE_ILLEGAL; -+ break; -+ } -+ break; -+ -+ case (HEADER_TYPE_GRE): -+ switch (field.gre) -+ { -+ case (NET_HEADER_FIELD_GRE_TYPE): -+ *parseCodeRealSize = 2; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported6")); -+ *parseCodeRealSize = CC_SIZE_ILLEGAL; -+ break; -+ } -+ break; -+ -+ case (HEADER_TYPE_MINENCAP): -+ switch (field.minencap) -+ { -+ case (NET_HEADER_FIELD_MINENCAP_TYPE): -+ *parseCodeRealSize = 1; -+ break; -+ -+ case (NET_HEADER_FIELD_MINENCAP_DST_IP): -+ case (NET_HEADER_FIELD_MINENCAP_SRC_IP): -+ *parseCodeRealSize = 4; -+ break; -+ -+ case (NET_HEADER_FIELD_MINENCAP_SRC_IP -+ | NET_HEADER_FIELD_MINENCAP_DST_IP): -+ *parseCodeRealSize = 8; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported7")); -+ *parseCodeRealSize = CC_SIZE_ILLEGAL; -+ break; -+ } -+ break; -+ -+ case (HEADER_TYPE_TCP): -+ switch (field.tcp) -+ { -+ case (NET_HEADER_FIELD_TCP_PORT_SRC): -+ case (NET_HEADER_FIELD_TCP_PORT_DST): -+ *parseCodeRealSize = 2; -+ break; -+ -+ case (NET_HEADER_FIELD_TCP_PORT_SRC -+ | NET_HEADER_FIELD_TCP_PORT_DST): -+ *parseCodeRealSize = 4; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported8")); -+ *parseCodeRealSize = CC_SIZE_ILLEGAL; -+ break; -+ } -+ break; -+ -+ case (HEADER_TYPE_UDP): -+ switch (field.udp) -+ { -+ case (NET_HEADER_FIELD_UDP_PORT_SRC): -+ case (NET_HEADER_FIELD_UDP_PORT_DST): -+ *parseCodeRealSize = 2; -+ break; -+ -+ case (NET_HEADER_FIELD_UDP_PORT_SRC -+ | NET_HEADER_FIELD_UDP_PORT_DST): -+ *parseCodeRealSize = 4; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported9")); -+ *parseCodeRealSize = CC_SIZE_ILLEGAL; -+ break; -+ } -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported10")); -+ *parseCodeRealSize = CC_SIZE_ILLEGAL; -+ break; -+ } -+} -+ -+t_Error ValidateNextEngineParams( -+ t_Handle h_FmPcd, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams, -+ e_FmPcdCcStatsMode statsMode) -+{ -+ uint16_t absoluteProfileId; -+ t_Error err = E_OK; -+ uint8_t relativeSchemeId; -+ -+ if ((statsMode == e_FM_PCD_CC_STATS_MODE_NONE) -+ && (p_FmPcdCcNextEngineParams->statisticsEn)) -+ RETURN_ERROR( -+ MAJOR, -+ E_CONFLICT, -+ ("Statistics are requested for a key, but statistics mode was set" -+ "to 'NONE' upon initialization")); -+ -+ switch (p_FmPcdCcNextEngineParams->nextEngine) -+ { -+ case (e_FM_PCD_INVALID): -+ err = E_NOT_SUPPORTED; -+ break; -+ -+ case (e_FM_PCD_DONE): -+ if ((p_FmPcdCcNextEngineParams->params.enqueueParams.action -+ == e_FM_PCD_ENQ_FRAME) -+ && p_FmPcdCcNextEngineParams->params.enqueueParams.overrideFqid) -+ { -+ if (!p_FmPcdCcNextEngineParams->params.enqueueParams.newFqid) -+ RETURN_ERROR( -+ MAJOR, -+ E_CONFLICT, -+ ("When overrideFqid is set, newFqid must not be zero")); -+ if (p_FmPcdCcNextEngineParams->params.enqueueParams.newFqid -+ & ~0x00FFFFFF) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("fqidForCtrlFlow must be between 1 and 2^24-1")); -+ } -+ break; -+ -+ case (e_FM_PCD_KG): -+ relativeSchemeId = -+ FmPcdKgGetRelativeSchemeId( -+ h_FmPcd, -+ FmPcdKgGetSchemeId( -+ p_FmPcdCcNextEngineParams->params.kgParams.h_DirectScheme)); -+ if (relativeSchemeId == FM_PCD_KG_NUM_OF_SCHEMES) -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG); -+ if (!FmPcdKgIsSchemeValidSw( -+ p_FmPcdCcNextEngineParams->params.kgParams.h_DirectScheme)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("not valid schemeIndex in KG next engine param")); -+ if (!KgIsSchemeAlwaysDirect(h_FmPcd, relativeSchemeId)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("CC Node may point only to a scheme that is always direct.")); -+ break; -+ -+ case (e_FM_PCD_PLCR): -+ if (p_FmPcdCcNextEngineParams->params.plcrParams.overrideParams) -+ { -+ /* if private policer profile, it may be uninitialized yet, therefore no checks are done at this stage */ -+ if (p_FmPcdCcNextEngineParams->params.plcrParams.sharedProfile) -+ { -+ err = -+ FmPcdPlcrGetAbsoluteIdByProfileParams( -+ h_FmPcd, -+ e_FM_PCD_PLCR_SHARED, -+ NULL, -+ p_FmPcdCcNextEngineParams->params.plcrParams.newRelativeProfileId, -+ &absoluteProfileId); -+ if (err) -+ RETURN_ERROR(MAJOR, err, -+ ("Shared profile offset is out of range")); -+ if (!FmPcdPlcrIsProfileValid(h_FmPcd, absoluteProfileId)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("Invalid profile")); -+ } -+ } -+ break; -+ -+ case (e_FM_PCD_HASH): -+ p_FmPcdCcNextEngineParams->nextEngine = e_FM_PCD_CC; -+ case (e_FM_PCD_CC): -+ if (!p_FmPcdCcNextEngineParams->params.ccParams.h_CcNode) -+ RETURN_ERROR(MAJOR, E_NULL_POINTER, -+ ("handler to next Node is NULL")); -+ break; -+ -+#if (DPAA_VERSION >= 11) -+ case (e_FM_PCD_FR): -+ if (!p_FmPcdCcNextEngineParams->params.frParams.h_FrmReplic) -+ err = E_NOT_SUPPORTED; -+ break; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("Next engine is not correct")); -+ } -+ -+ -+ return err; -+} -+ -+static uint8_t GetGenParseCode(e_FmPcdExtractFrom src, -+ uint32_t offset, bool glblMask, -+ uint8_t *parseArrayOffset, bool fromIc, -+ ccPrivateInfo_t icCode) -+{ -+ if (!fromIc) -+ { -+ switch (src) -+ { -+ case (e_FM_PCD_EXTRACT_FROM_FRAME_START): -+ if (glblMask) -+ return CC_PC_GENERIC_WITH_MASK; -+ else -+ return CC_PC_GENERIC_WITHOUT_MASK; -+ -+ case (e_FM_PCD_EXTRACT_FROM_CURR_END_OF_PARSE): -+ *parseArrayOffset = CC_PC_PR_NEXT_HEADER_OFFSET; -+ if (offset) -+ return CC_PR_OFFSET; -+ else -+ return CC_PR_WITHOUT_OFFSET; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 'extract from' src")); -+ return CC_PC_ILLEGAL; -+ } -+ } -+ else -+ { -+ switch (icCode) -+ { -+ case (CC_PRIVATE_INFO_IC_KEY_EXACT_MATCH): -+ *parseArrayOffset = 0x50; -+ return CC_PC_GENERIC_IC_GMASK; -+ -+ case (CC_PRIVATE_INFO_IC_HASH_EXACT_MATCH): -+ *parseArrayOffset = 0x48; -+ return CC_PC_GENERIC_IC_GMASK; -+ -+ case (CC_PRIVATE_INFO_IC_HASH_INDEX_LOOKUP): -+ *parseArrayOffset = 0x48; -+ return CC_PC_GENERIC_IC_HASH_INDEXED; -+ -+ case (CC_PRIVATE_INFO_IC_DEQ_FQID_INDEX_LOOKUP): -+ *parseArrayOffset = 0x16; -+ return CC_PC_GENERIC_IC_HASH_INDEXED; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 'extract from' src")); -+ break; -+ } -+ } -+ -+ return CC_PC_ILLEGAL; -+} -+ -+static uint8_t GetFullFieldParseCode(e_NetHeaderType hdr, e_FmPcdHdrIndex index, -+ t_FmPcdFields field) -+{ -+ switch (hdr) -+ { -+ case (HEADER_TYPE_NONE): -+ ASSERT_COND(FALSE); -+ return CC_PC_ILLEGAL; -+ -+ case (HEADER_TYPE_ETH): -+ switch (field.eth) -+ { -+ case (NET_HEADER_FIELD_ETH_DA): -+ return CC_PC_FF_MACDST; -+ case (NET_HEADER_FIELD_ETH_SA): -+ return CC_PC_FF_MACSRC; -+ case (NET_HEADER_FIELD_ETH_TYPE): -+ return CC_PC_FF_ETYPE; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+ -+ case (HEADER_TYPE_VLAN): -+ switch (field.vlan) -+ { -+ case (NET_HEADER_FIELD_VLAN_TCI): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) -+ || (index == e_FM_PCD_HDR_INDEX_1)) -+ return CC_PC_FF_TCI1; -+ if (index == e_FM_PCD_HDR_INDEX_LAST) -+ return CC_PC_FF_TCI2; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+ -+ case (HEADER_TYPE_MPLS): -+ switch (field.mpls) -+ { -+ case (NET_HEADER_FIELD_MPLS_LABEL_STACK): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) -+ || (index == e_FM_PCD_HDR_INDEX_1)) -+ return CC_PC_FF_MPLS1; -+ if (index == e_FM_PCD_HDR_INDEX_LAST) -+ return CC_PC_FF_MPLS_LAST; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal MPLS index")); -+ return CC_PC_ILLEGAL; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+ -+ case (HEADER_TYPE_IPv4): -+ switch (field.ipv4) -+ { -+ case (NET_HEADER_FIELD_IPv4_DST_IP): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) -+ || (index == e_FM_PCD_HDR_INDEX_1)) -+ return CC_PC_FF_IPV4DST1; -+ if (index == e_FM_PCD_HDR_INDEX_2) -+ return CC_PC_FF_IPV4DST2; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv4 index")); -+ return CC_PC_ILLEGAL; -+ case (NET_HEADER_FIELD_IPv4_TOS): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) -+ || (index == e_FM_PCD_HDR_INDEX_1)) -+ return CC_PC_FF_IPV4IPTOS_TC1; -+ if (index == e_FM_PCD_HDR_INDEX_2) -+ return CC_PC_FF_IPV4IPTOS_TC2; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv4 index")); -+ return CC_PC_ILLEGAL; -+ case (NET_HEADER_FIELD_IPv4_PROTO): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) -+ || (index == e_FM_PCD_HDR_INDEX_1)) -+ return CC_PC_FF_IPV4PTYPE1; -+ if (index == e_FM_PCD_HDR_INDEX_2) -+ return CC_PC_FF_IPV4PTYPE2; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv4 index")); -+ return CC_PC_ILLEGAL; -+ case (NET_HEADER_FIELD_IPv4_SRC_IP): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) -+ || (index == e_FM_PCD_HDR_INDEX_1)) -+ return CC_PC_FF_IPV4SRC1; -+ if (index == e_FM_PCD_HDR_INDEX_2) -+ return CC_PC_FF_IPV4SRC2; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv4 index")); -+ return CC_PC_ILLEGAL; -+ case (NET_HEADER_FIELD_IPv4_SRC_IP -+ | NET_HEADER_FIELD_IPv4_DST_IP): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) -+ || (index == e_FM_PCD_HDR_INDEX_1)) -+ return CC_PC_FF_IPV4SRC1_IPV4DST1; -+ if (index == e_FM_PCD_HDR_INDEX_2) -+ return CC_PC_FF_IPV4SRC2_IPV4DST2; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv4 index")); -+ return CC_PC_ILLEGAL; -+ case (NET_HEADER_FIELD_IPv4_TTL): -+ return CC_PC_FF_IPV4TTL; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+ -+ case (HEADER_TYPE_IPv6): -+ switch (field.ipv6) -+ { -+ case (NET_HEADER_FIELD_IPv6_VER | NET_HEADER_FIELD_IPv6_FL -+ | NET_HEADER_FIELD_IPv6_TC): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) -+ || (index == e_FM_PCD_HDR_INDEX_1)) -+ return CC_PC_FF_IPTOS_IPV6TC1_IPV6FLOW1; -+ if (index == e_FM_PCD_HDR_INDEX_2) -+ return CC_PC_FF_IPTOS_IPV6TC2_IPV6FLOW2; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv6 index")); -+ return CC_PC_ILLEGAL; -+ -+ case (NET_HEADER_FIELD_IPv6_NEXT_HDR): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) -+ || (index == e_FM_PCD_HDR_INDEX_1)) -+ return CC_PC_FF_IPV6PTYPE1; -+ if (index == e_FM_PCD_HDR_INDEX_2) -+ return CC_PC_FF_IPV6PTYPE2; -+ if (index == e_FM_PCD_HDR_INDEX_LAST) -+ return CC_PC_FF_IPPID; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv6 index")); -+ return CC_PC_ILLEGAL; -+ -+ case (NET_HEADER_FIELD_IPv6_DST_IP): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) -+ || (index == e_FM_PCD_HDR_INDEX_1)) -+ return CC_PC_FF_IPV6DST1; -+ if (index == e_FM_PCD_HDR_INDEX_2) -+ return CC_PC_FF_IPV6DST2; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv6 index")); -+ return CC_PC_ILLEGAL; -+ -+ case (NET_HEADER_FIELD_IPv6_SRC_IP): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) -+ || (index == e_FM_PCD_HDR_INDEX_1)) -+ return CC_PC_FF_IPV6SRC1; -+ if (index == e_FM_PCD_HDR_INDEX_2) -+ return CC_PC_FF_IPV6SRC2; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv6 index")); -+ return CC_PC_ILLEGAL; -+ -+ case (NET_HEADER_FIELD_IPv6_HOP_LIMIT): -+ return CC_PC_FF_IPV6HOP_LIMIT; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+ -+ case (HEADER_TYPE_IP): -+ switch (field.ip) -+ { -+ case (NET_HEADER_FIELD_IP_DSCP): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) -+ || (index == e_FM_PCD_HDR_INDEX_1)) -+ return CC_PC_FF_IPDSCP; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IP index")); -+ return CC_PC_ILLEGAL; -+ -+ case (NET_HEADER_FIELD_IP_PROTO): -+ if (index == e_FM_PCD_HDR_INDEX_LAST) -+ return CC_PC_FF_IPPID; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IP index")); -+ return CC_PC_ILLEGAL; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+ -+ case (HEADER_TYPE_GRE): -+ switch (field.gre) -+ { -+ case (NET_HEADER_FIELD_GRE_TYPE): -+ return CC_PC_FF_GREPTYPE; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+ -+ case (HEADER_TYPE_MINENCAP): -+ switch (field.minencap) -+ { -+ case (NET_HEADER_FIELD_MINENCAP_TYPE): -+ return CC_PC_FF_MINENCAP_PTYPE; -+ -+ case (NET_HEADER_FIELD_MINENCAP_DST_IP): -+ return CC_PC_FF_MINENCAP_IPDST; -+ -+ case (NET_HEADER_FIELD_MINENCAP_SRC_IP): -+ return CC_PC_FF_MINENCAP_IPSRC; -+ -+ case (NET_HEADER_FIELD_MINENCAP_SRC_IP -+ | NET_HEADER_FIELD_MINENCAP_DST_IP): -+ return CC_PC_FF_MINENCAP_IPSRC_IPDST; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+ -+ case (HEADER_TYPE_TCP): -+ switch (field.tcp) -+ { -+ case (NET_HEADER_FIELD_TCP_PORT_SRC): -+ return CC_PC_FF_L4PSRC; -+ -+ case (NET_HEADER_FIELD_TCP_PORT_DST): -+ return CC_PC_FF_L4PDST; -+ -+ case (NET_HEADER_FIELD_TCP_PORT_DST -+ | NET_HEADER_FIELD_TCP_PORT_SRC): -+ return CC_PC_FF_L4PSRC_L4PDST; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+ -+ case (HEADER_TYPE_PPPoE): -+ switch (field.pppoe) -+ { -+ case (NET_HEADER_FIELD_PPPoE_PID): -+ return CC_PC_FF_PPPPID; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+ -+ case (HEADER_TYPE_UDP): -+ switch (field.udp) -+ { -+ case (NET_HEADER_FIELD_UDP_PORT_SRC): -+ return CC_PC_FF_L4PSRC; -+ -+ case (NET_HEADER_FIELD_UDP_PORT_DST): -+ return CC_PC_FF_L4PDST; -+ -+ case (NET_HEADER_FIELD_UDP_PORT_DST -+ | NET_HEADER_FIELD_UDP_PORT_SRC): -+ return CC_PC_FF_L4PSRC_L4PDST; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+} -+ -+static uint8_t GetPrParseCode(e_NetHeaderType hdr, e_FmPcdHdrIndex hdrIndex, -+ uint32_t offset, bool glblMask, -+ uint8_t *parseArrayOffset) -+{ -+ bool offsetRelevant = FALSE; -+ -+ if (offset) -+ offsetRelevant = TRUE; -+ -+ switch (hdr) -+ { -+ case (HEADER_TYPE_NONE): -+ ASSERT_COND(FALSE); -+ return CC_PC_ILLEGAL; -+ -+ case (HEADER_TYPE_ETH): -+ *parseArrayOffset = (uint8_t)CC_PC_PR_ETH_OFFSET; -+ break; -+ -+ case (HEADER_TYPE_USER_DEFINED_SHIM1): -+ if (offset || glblMask) -+ *parseArrayOffset = (uint8_t)CC_PC_PR_USER_DEFINED_SHIM1_OFFSET; -+ else -+ return CC_PC_PR_SHIM1; -+ break; -+ -+ case (HEADER_TYPE_USER_DEFINED_SHIM2): -+ if (offset || glblMask) -+ *parseArrayOffset = (uint8_t)CC_PC_PR_USER_DEFINED_SHIM2_OFFSET; -+ else -+ return CC_PC_PR_SHIM2; -+ break; -+ -+ case (HEADER_TYPE_LLC_SNAP): -+ *parseArrayOffset = CC_PC_PR_USER_LLC_SNAP_OFFSET; -+ break; -+ -+ case (HEADER_TYPE_PPPoE): -+ *parseArrayOffset = CC_PC_PR_PPPOE_OFFSET; -+ break; -+ -+ case (HEADER_TYPE_MPLS): -+ if ((hdrIndex == e_FM_PCD_HDR_INDEX_NONE) -+ || (hdrIndex == e_FM_PCD_HDR_INDEX_1)) -+ *parseArrayOffset = CC_PC_PR_MPLS1_OFFSET; -+ else -+ if (hdrIndex == e_FM_PCD_HDR_INDEX_LAST) -+ *parseArrayOffset = CC_PC_PR_MPLS_LAST_OFFSET; -+ else -+ { -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal MPLS header index")); -+ return CC_PC_ILLEGAL; -+ } -+ break; -+ -+ case (HEADER_TYPE_IPv4): -+ case (HEADER_TYPE_IPv6): -+ if ((hdrIndex == e_FM_PCD_HDR_INDEX_NONE) -+ || (hdrIndex == e_FM_PCD_HDR_INDEX_1)) -+ *parseArrayOffset = CC_PC_PR_IP1_OFFSET; -+ else -+ if (hdrIndex == e_FM_PCD_HDR_INDEX_2) -+ *parseArrayOffset = CC_PC_PR_IP_LAST_OFFSET; -+ else -+ { -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IP header index")); -+ return CC_PC_ILLEGAL; -+ } -+ break; -+ -+ case (HEADER_TYPE_MINENCAP): -+ *parseArrayOffset = CC_PC_PR_MINENC_OFFSET; -+ break; -+ -+ case (HEADER_TYPE_GRE): -+ *parseArrayOffset = CC_PC_PR_GRE_OFFSET; -+ break; -+ -+ case (HEADER_TYPE_TCP): -+ case (HEADER_TYPE_UDP): -+ case (HEADER_TYPE_IPSEC_AH): -+ case (HEADER_TYPE_IPSEC_ESP): -+ case (HEADER_TYPE_DCCP): -+ case (HEADER_TYPE_SCTP): -+ *parseArrayOffset = CC_PC_PR_L4_OFFSET; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IP header for this type of operation")); -+ return CC_PC_ILLEGAL; -+ } -+ -+ if (offsetRelevant) -+ return CC_PR_OFFSET; -+ else -+ return CC_PR_WITHOUT_OFFSET; -+} -+ -+static uint8_t GetFieldParseCode(e_NetHeaderType hdr, t_FmPcdFields field, -+ uint32_t offset, uint8_t *parseArrayOffset, -+ e_FmPcdHdrIndex hdrIndex) -+{ -+ bool offsetRelevant = FALSE; -+ -+ if (offset) -+ offsetRelevant = TRUE; -+ -+ switch (hdr) -+ { -+ case (HEADER_TYPE_NONE): -+ ASSERT_COND(FALSE); -+ break; -+ case (HEADER_TYPE_ETH): -+ switch (field.eth) -+ { -+ case (NET_HEADER_FIELD_ETH_TYPE): -+ *parseArrayOffset = CC_PC_PR_ETYPE_LAST_OFFSET; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+ break; -+ -+ case (HEADER_TYPE_VLAN): -+ switch (field.vlan) -+ { -+ case (NET_HEADER_FIELD_VLAN_TCI): -+ if ((hdrIndex == e_FM_PCD_HDR_INDEX_NONE) -+ || (hdrIndex == e_FM_PCD_HDR_INDEX_1)) -+ *parseArrayOffset = CC_PC_PR_VLAN1_OFFSET; -+ else -+ if (hdrIndex == e_FM_PCD_HDR_INDEX_LAST) -+ *parseArrayOffset = CC_PC_PR_VLAN2_OFFSET; -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return CC_PC_ILLEGAL; -+ } -+ break; -+ -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal header ")); -+ return CC_PC_ILLEGAL; -+ } -+ -+ if (offsetRelevant) -+ return CC_PR_OFFSET; -+ else -+ return CC_PR_WITHOUT_OFFSET; -+} -+ -+static void FillAdOfTypeResult(t_Handle h_Ad, -+ t_FmPcdCcStatsParams *p_FmPcdCcStatsParams, -+ t_FmPcd *p_FmPcd, -+ t_FmPcdCcNextEngineParams *p_CcNextEngineParams) -+{ -+ t_AdOfTypeResult *p_AdResult = (t_AdOfTypeResult *)h_Ad; -+ t_Handle h_TmpAd; -+ uint32_t tmp = 0, tmpNia = 0; -+ uint16_t profileId; -+ t_Handle p_AdNewPtr = NULL; -+ -+ /* There are 3 cases handled in this routine of building a "result" type AD. -+ * Case 1: No Manip. The action descriptor is built within the match table. -+ * Case 2: Manip exists. A new AD is created - p_AdNewPtr. It is initialized -+ * either in the FmPcdManipUpdateAdResultForCc routine or it was already -+ * initialized and returned here. -+ * p_AdResult (within the match table) will be initialized after -+ * this routine returns and point to the existing AD. -+ * Case 3: Manip exists. The action descriptor is built within the match table. -+ * FmPcdManipUpdateAdResultForCc returns a NULL p_AdNewPtr. -+ * -+ * If statistics were enabled and the statistics mode of this node requires -+ * a statistics Ad, it will be placed after the result Ad and before the -+ * manip Ad, if manip Ad exists here. -+ */ -+ -+ /* As default, the "new" ptr is the current one. i.e. the content of the result -+ * AD will be written into the match table itself (case (1))*/ -+ p_AdNewPtr = p_AdResult; -+ -+ /* Initialize an action descriptor, if current statistics mode requires an Ad */ -+ if (p_FmPcdCcStatsParams) -+ { -+ ASSERT_COND(p_FmPcdCcStatsParams->h_StatsAd); -+ ASSERT_COND(p_FmPcdCcStatsParams->h_StatsCounters); -+ -+ /* Swapping addresses between statistics Ad and the current lookup AD addresses */ -+ h_TmpAd = p_FmPcdCcStatsParams->h_StatsAd; -+ p_FmPcdCcStatsParams->h_StatsAd = h_Ad; -+ h_Ad = h_TmpAd; -+ -+ p_AdNewPtr = h_Ad; -+ p_AdResult = h_Ad; -+ -+ /* Init statistics Ad and connect current lookup AD as 'next action' from statistics Ad */ -+ UpdateStatsAd(p_FmPcdCcStatsParams, h_Ad, p_FmPcd->physicalMuramBase); -+ } -+ -+ /* Create manip and return p_AdNewPtr to either a new descriptor or NULL */ -+ if (p_CcNextEngineParams->h_Manip) -+ FmPcdManipUpdateAdResultForCc(p_CcNextEngineParams->h_Manip, -+ p_CcNextEngineParams, h_Ad, &p_AdNewPtr); -+ -+ /* if (p_AdNewPtr = NULL) --> Done. (case (3)) */ -+ if (p_AdNewPtr) -+ { -+ /* case (1) and (2) */ -+ switch (p_CcNextEngineParams->nextEngine) -+ { -+ case (e_FM_PCD_DONE): -+ if (p_CcNextEngineParams->params.enqueueParams.action -+ == e_FM_PCD_ENQ_FRAME) -+ { -+ if (p_CcNextEngineParams->params.enqueueParams.overrideFqid) -+ { -+ tmp = FM_PCD_AD_RESULT_CONTRL_FLOW_TYPE; -+ tmp |= -+ p_CcNextEngineParams->params.enqueueParams.newFqid; -+#if (DPAA_VERSION >= 11) -+ tmp |= -+ (p_CcNextEngineParams->params.enqueueParams.newRelativeStorageProfileId -+ & FM_PCD_AD_RESULT_VSP_MASK) -+ << FM_PCD_AD_RESULT_VSP_SHIFT; -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ else -+ { -+ tmp = FM_PCD_AD_RESULT_DATA_FLOW_TYPE; -+ tmp |= FM_PCD_AD_RESULT_PLCR_DIS; -+ } -+ } -+ -+ if (p_CcNextEngineParams->params.enqueueParams.action -+ == e_FM_PCD_DROP_FRAME) -+ tmpNia |= GET_NIA_BMI_AC_DISCARD_FRAME(p_FmPcd); -+ else -+ tmpNia |= GET_NIA_BMI_AC_ENQ_FRAME(p_FmPcd); -+ break; -+ -+ case (e_FM_PCD_KG): -+ if (p_CcNextEngineParams->params.kgParams.overrideFqid) -+ { -+ tmp = FM_PCD_AD_RESULT_CONTRL_FLOW_TYPE; -+ tmp |= p_CcNextEngineParams->params.kgParams.newFqid; -+#if (DPAA_VERSION >= 11) -+ tmp |= -+ (p_CcNextEngineParams->params.kgParams.newRelativeStorageProfileId -+ & FM_PCD_AD_RESULT_VSP_MASK) -+ << FM_PCD_AD_RESULT_VSP_SHIFT; -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ else -+ { -+ tmp = FM_PCD_AD_RESULT_DATA_FLOW_TYPE; -+ tmp |= FM_PCD_AD_RESULT_PLCR_DIS; -+ } -+ tmpNia = NIA_KG_DIRECT; -+ tmpNia |= NIA_ENG_KG; -+ tmpNia |= NIA_KG_CC_EN; -+ tmpNia |= FmPcdKgGetSchemeId( -+ p_CcNextEngineParams->params.kgParams.h_DirectScheme); -+ break; -+ -+ case (e_FM_PCD_PLCR): -+ if (p_CcNextEngineParams->params.plcrParams.overrideParams) -+ { -+ tmp = FM_PCD_AD_RESULT_CONTRL_FLOW_TYPE; -+ -+ /* if private policer profile, it may be uninitialized yet, therefore no checks are done at this stage */ -+ if (p_CcNextEngineParams->params.plcrParams.sharedProfile) -+ { -+ tmpNia |= NIA_PLCR_ABSOLUTE; -+ FmPcdPlcrGetAbsoluteIdByProfileParams( -+ (t_Handle)p_FmPcd, -+ e_FM_PCD_PLCR_SHARED, -+ NULL, -+ p_CcNextEngineParams->params.plcrParams.newRelativeProfileId, -+ &profileId); -+ } -+ else -+ profileId = -+ p_CcNextEngineParams->params.plcrParams.newRelativeProfileId; -+ -+ tmp |= p_CcNextEngineParams->params.plcrParams.newFqid; -+#if (DPAA_VERSION >= 11) -+ tmp |= -+ (p_CcNextEngineParams->params.plcrParams.newRelativeStorageProfileId -+ & FM_PCD_AD_RESULT_VSP_MASK) -+ << FM_PCD_AD_RESULT_VSP_SHIFT; -+#endif /* (DPAA_VERSION >= 11) */ -+ WRITE_UINT32( -+ p_AdResult->plcrProfile, -+ (uint32_t)((uint32_t)profileId << FM_PCD_AD_PROFILEID_FOR_CNTRL_SHIFT)); -+ } -+ else -+ tmp = FM_PCD_AD_RESULT_DATA_FLOW_TYPE; -+ -+ tmpNia |= -+ NIA_ENG_PLCR -+ | p_CcNextEngineParams->params.plcrParams.newRelativeProfileId; -+ break; -+ -+ default: -+ return; -+ }WRITE_UINT32(p_AdResult->fqid, tmp); -+ -+ if (p_CcNextEngineParams->h_Manip) -+ { -+ tmp = GET_UINT32(p_AdResult->plcrProfile); -+ tmp |= (uint32_t)(XX_VirtToPhys(p_AdNewPtr) -+ - (p_FmPcd->physicalMuramBase)) >> 4; -+ WRITE_UINT32(p_AdResult->plcrProfile, tmp); -+ -+ tmpNia |= FM_PCD_AD_RESULT_EXTENDED_MODE; -+ tmpNia |= FM_PCD_AD_RESULT_NADEN; -+ } -+ -+#if (DPAA_VERSION >= 11) -+ tmpNia |= FM_PCD_AD_RESULT_NO_OM_VSPE; -+#endif /* (DPAA_VERSION >= 11) */ -+ WRITE_UINT32(p_AdResult->nia, tmpNia); -+ } -+} -+ -+static t_Error CcUpdateParams(t_Handle h_FmPcd, t_Handle h_PcdParams, -+ t_Handle h_FmPort, t_Handle h_FmTree, -+ bool validate) -+{ -+ t_FmPcdCcTree *p_CcTree = (t_FmPcdCcTree *)h_FmTree; -+ -+ return CcUpdateParam(h_FmPcd, h_PcdParams, h_FmPort, -+ p_CcTree->keyAndNextEngineParams, -+ p_CcTree->numOfEntries, -+ UINT_TO_PTR(p_CcTree->ccTreeBaseAddr), validate, 0, -+ h_FmTree, FALSE); -+} -+ -+ -+static void ReleaseNewNodeCommonPart( -+ t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalInfo) -+{ -+ if (p_AdditionalInfo->p_AdTableNew) -+ FM_MURAM_FreeMem( -+ FmPcdGetMuramHandle( -+ ((t_FmPcdCcNode *)(p_AdditionalInfo->h_CurrentNode))->h_FmPcd), -+ p_AdditionalInfo->p_AdTableNew); -+ -+ if (p_AdditionalInfo->p_KeysMatchTableNew) -+ FM_MURAM_FreeMem( -+ FmPcdGetMuramHandle( -+ ((t_FmPcdCcNode *)(p_AdditionalInfo->h_CurrentNode))->h_FmPcd), -+ p_AdditionalInfo->p_KeysMatchTableNew); -+} -+ -+static t_Error UpdateGblMask(t_FmPcdCcNode *p_CcNode, uint8_t keySize, -+ uint8_t *p_Mask) -+{ -+ uint8_t prvGlblMaskSize = p_CcNode->glblMaskSize; -+ -+ if (p_Mask && !p_CcNode->glblMaskUpdated && (keySize <= 4) -+ && !p_CcNode->lclMask) -+ { -+ if (p_CcNode->parseCode && (p_CcNode->parseCode != CC_PC_FF_TCI1) -+ && (p_CcNode->parseCode != CC_PC_FF_TCI2) -+ && (p_CcNode->parseCode != CC_PC_FF_MPLS1) -+ && (p_CcNode->parseCode != CC_PC_FF_MPLS_LAST) -+ && (p_CcNode->parseCode != CC_PC_FF_IPV4IPTOS_TC1) -+ && (p_CcNode->parseCode != CC_PC_FF_IPV4IPTOS_TC2) -+ && (p_CcNode->parseCode != CC_PC_FF_IPTOS_IPV6TC1_IPV6FLOW1) -+ && (p_CcNode->parseCode != CC_PC_FF_IPDSCP) -+ && (p_CcNode->parseCode != CC_PC_FF_IPTOS_IPV6TC2_IPV6FLOW2)) -+ { -+ p_CcNode->glblMaskSize = 0; -+ p_CcNode->lclMask = TRUE; -+ } -+ else -+ { -+ memcpy(p_CcNode->p_GlblMask, p_Mask, (sizeof(uint8_t)) * keySize); -+ p_CcNode->glblMaskUpdated = TRUE; -+ p_CcNode->glblMaskSize = 4; -+ } -+ } -+ else -+ if (p_Mask && (keySize <= 4) && !p_CcNode->lclMask) -+ { -+ if (memcmp(p_CcNode->p_GlblMask, p_Mask, keySize) != 0) -+ { -+ p_CcNode->lclMask = TRUE; -+ p_CcNode->glblMaskSize = 0; -+ } -+ } -+ else -+ if (!p_Mask && p_CcNode->glblMaskUpdated && (keySize <= 4)) -+ { -+ uint32_t tmpMask = 0xffffffff; -+ if (memcmp(p_CcNode->p_GlblMask, &tmpMask, 4) != 0) -+ { -+ p_CcNode->lclMask = TRUE; -+ p_CcNode->glblMaskSize = 0; -+ } -+ } -+ else -+ if (p_Mask) -+ { -+ p_CcNode->lclMask = TRUE; -+ p_CcNode->glblMaskSize = 0; -+ } -+ -+ /* In static mode (maxNumOfKeys > 0), local mask is supported -+ only is mask support was enabled at initialization */ -+ if (p_CcNode->maxNumOfKeys && (!p_CcNode->maskSupport) && p_CcNode->lclMask) -+ { -+ p_CcNode->lclMask = FALSE; -+ p_CcNode->glblMaskSize = prvGlblMaskSize; -+ return ERROR_CODE(E_NOT_SUPPORTED); -+ } -+ -+ return E_OK; -+} -+ -+static __inline__ t_Handle GetNewAd(t_Handle h_FmPcdCcNodeOrTree, bool isTree) -+{ -+ t_FmPcd *p_FmPcd; -+ t_Handle h_Ad; -+ -+ if (isTree) -+ p_FmPcd = (t_FmPcd *)(((t_FmPcdCcTree *)h_FmPcdCcNodeOrTree)->h_FmPcd); -+ else -+ p_FmPcd = (t_FmPcd *)(((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->h_FmPcd); -+ -+ if ((isTree && p_FmPcd->p_CcShadow) -+ || (!isTree && ((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->maxNumOfKeys)) -+ { -+ /* The allocated shadow is divided as follows: -+ 0 . . . 16 . . . -+ --------------------------------------------------- -+ | Shadow | Shadow Keys | Shadow Next | -+ | Ad | Match Table | Engine Table | -+ | (16 bytes) | (maximal size) | (maximal size) | -+ --------------------------------------------------- -+ */ -+ if (!p_FmPcd->p_CcShadow) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("CC Shadow not allocated")); -+ return NULL; -+ } -+ -+ h_Ad = p_FmPcd->p_CcShadow; -+ } -+ else -+ { -+ h_Ad = (t_Handle)FM_MURAM_AllocMem(FmPcdGetMuramHandle(p_FmPcd), -+ FM_PCD_CC_AD_ENTRY_SIZE, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!h_Ad) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("MURAM allocation for CC node action descriptor")); -+ return NULL; -+ } -+ } -+ -+ return h_Ad; -+} -+ -+static t_Error BuildNewNodeCommonPart( -+ t_FmPcdCcNode *p_CcNode, int *size, -+ t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalInfo) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ -+ if (p_CcNode->lclMask) -+ *size = 2 * p_CcNode->ccKeySizeAccExtraction; -+ else -+ *size = p_CcNode->ccKeySizeAccExtraction; -+ -+ if (p_CcNode->maxNumOfKeys == 0) -+ { -+ p_AdditionalInfo->p_AdTableNew = (t_Handle)FM_MURAM_AllocMem( -+ FmPcdGetMuramHandle(p_FmPcd), -+ (uint32_t)((p_AdditionalInfo->numOfKeys + 1) -+ * FM_PCD_CC_AD_ENTRY_SIZE), -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_AdditionalInfo->p_AdTableNew) -+ RETURN_ERROR( -+ MAJOR, E_NO_MEMORY, -+ ("MURAM allocation for CC node action descriptors table")); -+ -+ p_AdditionalInfo->p_KeysMatchTableNew = (t_Handle)FM_MURAM_AllocMem( -+ FmPcdGetMuramHandle(p_FmPcd), -+ (uint32_t)(*size * sizeof(uint8_t) -+ * (p_AdditionalInfo->numOfKeys + 1)), -+ FM_PCD_CC_KEYS_MATCH_TABLE_ALIGN); -+ if (!p_AdditionalInfo->p_KeysMatchTableNew) -+ { -+ FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_CcNode->h_FmPcd), -+ p_AdditionalInfo->p_AdTableNew); -+ p_AdditionalInfo->p_AdTableNew = NULL; -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM allocation for CC node key match table")); -+ } -+ -+ MemSet8( -+ (uint8_t*)p_AdditionalInfo->p_AdTableNew, -+ 0, -+ (uint32_t)((p_AdditionalInfo->numOfKeys + 1) -+ * FM_PCD_CC_AD_ENTRY_SIZE)); -+ MemSet8((uint8_t*)p_AdditionalInfo->p_KeysMatchTableNew, 0, -+ *size * sizeof(uint8_t) * (p_AdditionalInfo->numOfKeys + 1)); -+ } -+ else -+ { -+ /* The allocated shadow is divided as follows: -+ 0 . . . 16 . . . -+ --------------------------------------------------- -+ | Shadow | Shadow Keys | Shadow Next | -+ | Ad | Match Table | Engine Table | -+ | (16 bytes) | (maximal size) | (maximal size) | -+ --------------------------------------------------- -+ */ -+ -+ if (!p_FmPcd->p_CcShadow) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("CC Shadow not allocated")); -+ -+ p_AdditionalInfo->p_KeysMatchTableNew = -+ PTR_MOVE(p_FmPcd->p_CcShadow, FM_PCD_CC_AD_ENTRY_SIZE); -+ p_AdditionalInfo->p_AdTableNew = -+ PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableNew, p_CcNode->keysMatchTableMaxSize); -+ -+ MemSet8( -+ (uint8_t*)p_AdditionalInfo->p_AdTableNew, -+ 0, -+ (uint32_t)((p_CcNode->maxNumOfKeys + 1) -+ * FM_PCD_CC_AD_ENTRY_SIZE)); -+ MemSet8((uint8_t*)p_AdditionalInfo->p_KeysMatchTableNew, 0, -+ (*size) * sizeof(uint8_t) * (p_CcNode->maxNumOfKeys)); -+ } -+ -+ p_AdditionalInfo->p_AdTableOld = p_CcNode->h_AdTable; -+ p_AdditionalInfo->p_KeysMatchTableOld = p_CcNode->h_KeysMatchTable; -+ -+ return E_OK; -+} -+ -+static t_Error BuildNewNodeAddOrMdfyKeyAndNextEngine( -+ t_Handle h_FmPcd, t_FmPcdCcNode *p_CcNode, uint16_t keyIndex, -+ t_FmPcdCcKeyParams *p_KeyParams, -+ t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalInfo, bool add) -+{ -+ t_Error err = E_OK; -+ t_Handle p_AdTableNewTmp, p_KeysMatchTableNewTmp; -+ t_Handle p_KeysMatchTableOldTmp, p_AdTableOldTmp; -+ int size; -+ int i = 0, j = 0; -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint32_t requiredAction = 0; -+ bool prvLclMask; -+ t_CcNodeInformation *p_CcNodeInformation; -+ t_FmPcdCcStatsParams statsParams = { 0 }; -+ t_List *p_Pos; -+ t_FmPcdStatsObj *p_StatsObj; -+ -+ /* Check that new NIA is legal */ -+ err = ValidateNextEngineParams(h_FmPcd, &p_KeyParams->ccNextEngineParams, -+ p_CcNode->statisticsMode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ prvLclMask = p_CcNode->lclMask; -+ -+ /* Check that new key is not require update of localMask */ -+ err = UpdateGblMask(p_CcNode, p_CcNode->ccKeySizeAccExtraction, -+ p_KeyParams->p_Mask); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ -+ /* Update internal data structure with new next engine for the given index */ -+ memcpy(&p_AdditionalInfo->keyAndNextEngineParams[keyIndex].nextEngineParams, -+ &p_KeyParams->ccNextEngineParams, sizeof(t_FmPcdCcNextEngineParams)); -+ -+ memcpy(p_AdditionalInfo->keyAndNextEngineParams[keyIndex].key, -+ p_KeyParams->p_Key, p_CcNode->userSizeOfExtraction); -+ -+ if ((p_AdditionalInfo->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ && p_AdditionalInfo->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip) -+ { -+ err = -+ AllocAndFillAdForContLookupManip( -+ p_AdditionalInfo->keyAndNextEngineParams[keyIndex].nextEngineParams.params.ccParams.h_CcNode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ -+ if (p_KeyParams->p_Mask) -+ memcpy(p_AdditionalInfo->keyAndNextEngineParams[keyIndex].mask, -+ p_KeyParams->p_Mask, p_CcNode->userSizeOfExtraction); -+ else -+ memset(p_AdditionalInfo->keyAndNextEngineParams[keyIndex].mask, 0xFF, -+ p_CcNode->userSizeOfExtraction); -+ -+ /* Update numOfKeys */ -+ if (add) -+ p_AdditionalInfo->numOfKeys = (uint8_t)(p_CcNode->numOfKeys + 1); -+ else -+ p_AdditionalInfo->numOfKeys = (uint8_t)p_CcNode->numOfKeys; -+ -+ /* Allocate new tables in MURAM: keys match table and action descriptors table */ -+ err = BuildNewNodeCommonPart(p_CcNode, &size, p_AdditionalInfo); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ /* Check that manip is legal and what requiredAction is necessary for this manip */ -+ if (p_KeyParams->ccNextEngineParams.h_Manip) -+ { -+ err = FmPcdManipCheckParamsForCcNextEngine( -+ &p_KeyParams->ccNextEngineParams, &requiredAction); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ -+ p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction = -+ requiredAction; -+ p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction |= -+ UPDATE_CC_WITH_TREE; -+ -+ /* Update new Ad and new Key Table according to new requirement */ -+ i = 0; -+ for (j = 0; j < p_AdditionalInfo->numOfKeys; j++) -+ { -+ p_AdTableNewTmp = -+ PTR_MOVE(p_AdditionalInfo->p_AdTableNew, j*FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ if (j == keyIndex) -+ { -+ if (p_KeyParams->ccNextEngineParams.statisticsEn) -+ { -+ /* Allocate a statistics object that holds statistics AD and counters. -+ - For added key - New statistics AD and counters pointer need to be allocated -+ new statistics object. If statistics were enabled, we need to replace the -+ existing descriptor with a new descriptor with nullified counters. -+ */ -+ p_StatsObj = GetStatsObj(p_CcNode); -+ ASSERT_COND(p_StatsObj); -+ -+ /* Store allocated statistics object */ -+ ASSERT_COND(keyIndex < CC_MAX_NUM_OF_KEYS); -+ p_AdditionalInfo->keyAndNextEngineParams[keyIndex].p_StatsObj = -+ p_StatsObj; -+ -+ statsParams.h_StatsAd = p_StatsObj->h_StatsAd; -+ statsParams.h_StatsCounters = p_StatsObj->h_StatsCounters; -+#if (DPAA_VERSION >= 11) -+ statsParams.h_StatsFLRs = p_CcNode->h_StatsFLRs; -+ -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ /* Building action descriptor for the received new key */ -+ NextStepAd(p_AdTableNewTmp, &statsParams, -+ &p_KeyParams->ccNextEngineParams, p_FmPcd); -+ } -+ else -+ { -+ /* Building action descriptor for the received new key */ -+ NextStepAd(p_AdTableNewTmp, NULL, -+ &p_KeyParams->ccNextEngineParams, p_FmPcd); -+ } -+ -+ /* Copy the received new key into keys match table */ -+ p_KeysMatchTableNewTmp = -+ PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableNew, j*size*sizeof(uint8_t)); -+ -+ MemCpy8((void*)p_KeysMatchTableNewTmp, p_KeyParams->p_Key, -+ p_CcNode->userSizeOfExtraction); -+ -+ /* Update mask for the received new key */ -+ if (p_CcNode->lclMask) -+ { -+ if (p_KeyParams->p_Mask) -+ { -+ MemCpy8(PTR_MOVE(p_KeysMatchTableNewTmp, -+ p_CcNode->ccKeySizeAccExtraction), -+ p_KeyParams->p_Mask, -+ p_CcNode->userSizeOfExtraction); -+ } -+ else -+ if (p_CcNode->ccKeySizeAccExtraction > 4) -+ { -+ MemSet8(PTR_MOVE(p_KeysMatchTableNewTmp, -+ p_CcNode->ccKeySizeAccExtraction), -+ 0xff, p_CcNode->userSizeOfExtraction); -+ } -+ else -+ { -+ MemCpy8(PTR_MOVE(p_KeysMatchTableNewTmp, -+ p_CcNode->ccKeySizeAccExtraction), -+ p_CcNode->p_GlblMask, -+ p_CcNode->userSizeOfExtraction); -+ } -+ } -+ -+ /* If key modification requested, the old entry is omitted and replaced by the new parameters */ -+ if (!add) -+ i++; -+ } -+ else -+ { -+ /* Copy existing action descriptors to the newly allocated Ad table */ -+ p_AdTableOldTmp = -+ PTR_MOVE(p_AdditionalInfo->p_AdTableOld, i*FM_PCD_CC_AD_ENTRY_SIZE); -+ MemCpy8(p_AdTableNewTmp, p_AdTableOldTmp, -+ FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ /* Copy existing keys and their masks to the newly allocated keys match table */ -+ p_KeysMatchTableNewTmp = -+ PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableNew, j * size * sizeof(uint8_t)); -+ p_KeysMatchTableOldTmp = -+ PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableOld, i * size * sizeof(uint8_t)); -+ -+ if (p_CcNode->lclMask) -+ { -+ if (prvLclMask) -+ { -+ MemCpy8( -+ PTR_MOVE(p_KeysMatchTableNewTmp, p_CcNode->ccKeySizeAccExtraction), -+ PTR_MOVE(p_KeysMatchTableOldTmp, p_CcNode->ccKeySizeAccExtraction), -+ p_CcNode->ccKeySizeAccExtraction); -+ } -+ else -+ { -+ p_KeysMatchTableOldTmp = -+ PTR_MOVE(p_CcNode->h_KeysMatchTable, -+ i * (int)p_CcNode->ccKeySizeAccExtraction * sizeof(uint8_t)); -+ -+ if (p_CcNode->ccKeySizeAccExtraction > 4) -+ { -+ MemSet8(PTR_MOVE(p_KeysMatchTableNewTmp, -+ p_CcNode->ccKeySizeAccExtraction), -+ 0xff, p_CcNode->userSizeOfExtraction); -+ } -+ else -+ { -+ MemCpy8(PTR_MOVE(p_KeysMatchTableNewTmp, -+ p_CcNode->ccKeySizeAccExtraction), -+ p_CcNode->p_GlblMask, -+ p_CcNode->userSizeOfExtraction); -+ } -+ } -+ } -+ -+ MemCpy8(p_KeysMatchTableNewTmp, p_KeysMatchTableOldTmp, -+ p_CcNode->ccKeySizeAccExtraction); -+ -+ i++; -+ } -+ } -+ -+ /* Miss action descriptor */ -+ p_AdTableNewTmp = -+ PTR_MOVE(p_AdditionalInfo->p_AdTableNew, j * FM_PCD_CC_AD_ENTRY_SIZE); -+ p_AdTableOldTmp = -+ PTR_MOVE(p_AdditionalInfo->p_AdTableOld, i * FM_PCD_CC_AD_ENTRY_SIZE); -+ MemCpy8(p_AdTableNewTmp, p_AdTableOldTmp, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ if (!LIST_IsEmpty(&p_CcNode->ccTreesLst)) -+ { -+ LIST_FOR_EACH(p_Pos, &p_CcNode->ccTreesLst) -+ { -+ p_CcNodeInformation = CC_NODE_F_OBJECT(p_Pos); -+ ASSERT_COND(p_CcNodeInformation->h_CcNode); -+ /* Update the manipulation which has to be updated from parameters of the port */ -+ /* It's has to be updated with restrictions defined in the function */ -+ err = -+ SetRequiredAction( -+ p_CcNode->h_FmPcd, -+ p_CcNode->shadowAction -+ | p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction, -+ &p_AdditionalInfo->keyAndNextEngineParams[keyIndex], -+ PTR_MOVE(p_AdditionalInfo->p_AdTableNew, keyIndex*FM_PCD_CC_AD_ENTRY_SIZE), -+ 1, p_CcNodeInformation->h_CcNode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ -+ err = -+ CcUpdateParam( -+ p_CcNode->h_FmPcd, -+ NULL, -+ NULL, -+ &p_AdditionalInfo->keyAndNextEngineParams[keyIndex], -+ 1, -+ PTR_MOVE(p_AdditionalInfo->p_AdTableNew, keyIndex*FM_PCD_CC_AD_ENTRY_SIZE), -+ TRUE, p_CcNodeInformation->index, -+ p_CcNodeInformation->h_CcNode, TRUE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ } -+ -+ if (p_CcNode->lclMask) -+ memset(p_CcNode->p_GlblMask, 0xff, CC_GLBL_MASK_SIZE * sizeof(uint8_t)); -+ -+ if (p_KeyParams->ccNextEngineParams.nextEngine == e_FM_PCD_CC) -+ p_AdditionalInfo->h_NodeForAdd = -+ p_KeyParams->ccNextEngineParams.params.ccParams.h_CcNode; -+ if (p_KeyParams->ccNextEngineParams.h_Manip) -+ p_AdditionalInfo->h_ManipForAdd = -+ p_KeyParams->ccNextEngineParams.h_Manip; -+ -+#if (DPAA_VERSION >= 11) -+ if ((p_KeyParams->ccNextEngineParams.nextEngine == e_FM_PCD_FR) -+ && (p_KeyParams->ccNextEngineParams.params.frParams.h_FrmReplic)) -+ p_AdditionalInfo->h_FrmReplicForAdd = -+ p_KeyParams->ccNextEngineParams.params.frParams.h_FrmReplic; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ if (!add) -+ { -+ if (p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ p_AdditionalInfo->h_NodeForRmv = -+ p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.params.ccParams.h_CcNode; -+ -+ if (p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip) -+ p_AdditionalInfo->h_ManipForRmv = -+ p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip; -+ -+ /* If statistics were previously enabled, store the old statistics object to be released */ -+ if (p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj) -+ { -+ p_AdditionalInfo->p_StatsObjForRmv = -+ p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj; -+ } -+ -+#if (DPAA_VERSION >= 11) -+ if ((p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine -+ == e_FM_PCD_FR) -+ && (p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic)) -+ p_AdditionalInfo->h_FrmReplicForRmv = -+ p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic; -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ -+ return E_OK; -+} -+ -+static t_Error BuildNewNodeRemoveKey( -+ t_FmPcdCcNode *p_CcNode, uint16_t keyIndex, -+ t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalInfo) -+{ -+ int i = 0, j = 0; -+ t_Handle p_AdTableNewTmp, p_KeysMatchTableNewTmp; -+ t_Handle p_KeysMatchTableOldTmp, p_AdTableOldTmp; -+ int size; -+ t_Error err = E_OK; -+ -+ /*save new numOfKeys*/ -+ p_AdditionalInfo->numOfKeys = (uint16_t)(p_CcNode->numOfKeys - 1); -+ -+ /*function which allocates in the memory new KeyTbl, AdTbl*/ -+ err = BuildNewNodeCommonPart(p_CcNode, &size, p_AdditionalInfo); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ /*update new Ad and new Key Table according to new requirement*/ -+ for (i = 0, j = 0; j < p_CcNode->numOfKeys; i++, j++) -+ { -+ if (j == keyIndex) -+ j++; -+ -+ if (j == p_CcNode->numOfKeys) -+ break; -+ p_AdTableNewTmp = -+ PTR_MOVE(p_AdditionalInfo->p_AdTableNew, i * FM_PCD_CC_AD_ENTRY_SIZE); -+ p_AdTableOldTmp = -+ PTR_MOVE(p_AdditionalInfo->p_AdTableOld, j * FM_PCD_CC_AD_ENTRY_SIZE); -+ MemCpy8(p_AdTableNewTmp, p_AdTableOldTmp, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ p_KeysMatchTableOldTmp = -+ PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableOld, j * size * sizeof(uint8_t)); -+ p_KeysMatchTableNewTmp = -+ PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableNew, i * size * sizeof(uint8_t)); -+ MemCpy8(p_KeysMatchTableNewTmp, p_KeysMatchTableOldTmp, -+ size * sizeof(uint8_t)); -+ } -+ -+ p_AdTableNewTmp = -+ PTR_MOVE(p_AdditionalInfo->p_AdTableNew, i * FM_PCD_CC_AD_ENTRY_SIZE); -+ p_AdTableOldTmp = -+ PTR_MOVE(p_AdditionalInfo->p_AdTableOld, j * FM_PCD_CC_AD_ENTRY_SIZE); -+ MemCpy8(p_AdTableNewTmp, p_AdTableOldTmp, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ if (p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ p_AdditionalInfo->h_NodeForRmv = -+ p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.params.ccParams.h_CcNode; -+ -+ if (p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip) -+ p_AdditionalInfo->h_ManipForRmv = -+ p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip; -+ -+ /* If statistics were previously enabled, store the old statistics object to be released */ -+ if (p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj) -+ { -+ p_AdditionalInfo->p_StatsObjForRmv = -+ p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj; -+ } -+ -+#if (DPAA_VERSION >= 11) -+ if ((p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine -+ == e_FM_PCD_FR) -+ && (p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic)) -+ p_AdditionalInfo->h_FrmReplicForRmv = -+ p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ return E_OK; -+} -+ -+static t_Error BuildNewNodeModifyKey( -+ t_FmPcdCcNode *p_CcNode, uint16_t keyIndex, uint8_t *p_Key, -+ uint8_t *p_Mask, t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalInfo) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ t_Error err = E_OK; -+ t_Handle p_AdTableNewTmp, p_KeysMatchTableNewTmp; -+ t_Handle p_KeysMatchTableOldTmp, p_AdTableOldTmp; -+ int size; -+ int i = 0, j = 0; -+ bool prvLclMask; -+ t_FmPcdStatsObj *p_StatsObj, tmpStatsObj; -+ p_AdditionalInfo->numOfKeys = p_CcNode->numOfKeys; -+ -+ prvLclMask = p_CcNode->lclMask; -+ -+ /* Check that new key is not require update of localMask */ -+ err = UpdateGblMask(p_CcNode, p_CcNode->ccKeySizeAccExtraction, p_Mask); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ -+ /* Update internal data structure with new next engine for the given index */ -+ memcpy(p_AdditionalInfo->keyAndNextEngineParams[keyIndex].key, p_Key, -+ p_CcNode->userSizeOfExtraction); -+ -+ if (p_Mask) -+ memcpy(p_AdditionalInfo->keyAndNextEngineParams[keyIndex].mask, p_Mask, -+ p_CcNode->userSizeOfExtraction); -+ else -+ memset(p_AdditionalInfo->keyAndNextEngineParams[keyIndex].mask, 0xFF, -+ p_CcNode->userSizeOfExtraction); -+ -+ /*function which build in the memory new KeyTbl, AdTbl*/ -+ err = BuildNewNodeCommonPart(p_CcNode, &size, p_AdditionalInfo); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ /*fill the New AdTable and New KeyTable*/ -+ for (j = 0, i = 0; j < p_AdditionalInfo->numOfKeys; j++, i++) -+ { -+ p_AdTableNewTmp = -+ PTR_MOVE(p_AdditionalInfo->p_AdTableNew, j*FM_PCD_CC_AD_ENTRY_SIZE); -+ p_AdTableOldTmp = -+ PTR_MOVE(p_AdditionalInfo->p_AdTableOld, i*FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ MemCpy8(p_AdTableNewTmp, p_AdTableOldTmp, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ if (j == keyIndex) -+ { -+ ASSERT_COND(keyIndex < CC_MAX_NUM_OF_KEYS); -+ if (p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj) -+ { -+ /* As statistics were enabled, we need to update the existing -+ statistics descriptor with a new nullified counters. */ -+ p_StatsObj = GetStatsObj(p_CcNode); -+ ASSERT_COND(p_StatsObj); -+ -+ SetStatsCounters( -+ p_AdTableNewTmp, -+ (uint32_t)((XX_VirtToPhys(p_StatsObj->h_StatsCounters) -+ - p_FmPcd->physicalMuramBase))); -+ -+ tmpStatsObj.h_StatsAd = p_StatsObj->h_StatsAd; -+ tmpStatsObj.h_StatsCounters = p_StatsObj->h_StatsCounters; -+ -+ /* As we need to replace only the counters, we build a new statistics -+ object that holds the old AD and the new counters - this will be the -+ currently used statistics object. -+ The newly allocated AD is not required and may be released back to -+ the available objects with the previous counters pointer. */ -+ p_StatsObj->h_StatsAd = -+ p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj->h_StatsAd; -+ -+ p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj->h_StatsAd = -+ tmpStatsObj.h_StatsAd; -+ -+ /* Store allocated statistics object */ -+ p_AdditionalInfo->keyAndNextEngineParams[keyIndex].p_StatsObj = -+ p_StatsObj; -+ -+ /* As statistics were previously enabled, store the old statistics object to be released */ -+ p_AdditionalInfo->p_StatsObjForRmv = -+ p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj; -+ } -+ -+ p_KeysMatchTableNewTmp = -+ PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableNew, j * size * sizeof(uint8_t)); -+ -+ MemCpy8(p_KeysMatchTableNewTmp, p_Key, -+ p_CcNode->userSizeOfExtraction); -+ -+ if (p_CcNode->lclMask) -+ { -+ if (p_Mask) -+ MemCpy8(PTR_MOVE(p_KeysMatchTableNewTmp, -+ p_CcNode->ccKeySizeAccExtraction), -+ p_Mask, p_CcNode->userSizeOfExtraction); -+ else -+ if (p_CcNode->ccKeySizeAccExtraction > 4) -+ MemSet8(PTR_MOVE(p_KeysMatchTableNewTmp, -+ p_CcNode->ccKeySizeAccExtraction), -+ 0xff, p_CcNode->userSizeOfExtraction); -+ else -+ MemCpy8(PTR_MOVE(p_KeysMatchTableNewTmp, -+ p_CcNode->ccKeySizeAccExtraction), -+ p_CcNode->p_GlblMask, -+ p_CcNode->userSizeOfExtraction); -+ } -+ } -+ else -+ { -+ p_KeysMatchTableNewTmp = -+ PTR_MOVE(p_AdditionalInfo->p_KeysMatchTableNew, j * size * sizeof(uint8_t)); -+ p_KeysMatchTableOldTmp = -+ PTR_MOVE(p_CcNode->h_KeysMatchTable, i * size * sizeof(uint8_t)); -+ -+ if (p_CcNode->lclMask) -+ { -+ if (prvLclMask) -+ MemCpy8( -+ PTR_MOVE(p_KeysMatchTableNewTmp, p_CcNode->ccKeySizeAccExtraction), -+ PTR_MOVE(p_KeysMatchTableOldTmp, p_CcNode->ccKeySizeAccExtraction), -+ p_CcNode->userSizeOfExtraction); -+ else -+ { -+ p_KeysMatchTableOldTmp = -+ PTR_MOVE(p_CcNode->h_KeysMatchTable, -+ i * (int)p_CcNode->ccKeySizeAccExtraction * sizeof(uint8_t)); -+ -+ if (p_CcNode->ccKeySizeAccExtraction > 4) -+ MemSet8(PTR_MOVE(p_KeysMatchTableNewTmp, -+ p_CcNode->ccKeySizeAccExtraction), -+ 0xff, p_CcNode->userSizeOfExtraction); -+ else -+ MemCpy8( -+ PTR_MOVE(p_KeysMatchTableNewTmp, p_CcNode->ccKeySizeAccExtraction), -+ p_CcNode->p_GlblMask, -+ p_CcNode->userSizeOfExtraction); -+ } -+ } -+ MemCpy8((void*)p_KeysMatchTableNewTmp, p_KeysMatchTableOldTmp, -+ p_CcNode->ccKeySizeAccExtraction); -+ } -+ } -+ -+ p_AdTableNewTmp = -+ PTR_MOVE(p_AdditionalInfo->p_AdTableNew, j * FM_PCD_CC_AD_ENTRY_SIZE); -+ p_AdTableOldTmp = PTR_MOVE(p_CcNode->h_AdTable, i * FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ MemCpy8(p_AdTableNewTmp, p_AdTableOldTmp, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ return E_OK; -+} -+ -+static t_Error BuildNewNodeModifyNextEngine( -+ t_Handle h_FmPcd, t_Handle h_FmPcdCcNodeOrTree, uint16_t keyIndex, -+ t_FmPcdCcNextEngineParams *p_CcNextEngineParams, t_List *h_OldLst, -+ t_List *h_NewLst, t_FmPcdModifyCcKeyAdditionalParams *p_AdditionalInfo) -+{ -+ t_Error err = E_OK; -+ uint32_t requiredAction = 0; -+ t_List *p_Pos; -+ t_CcNodeInformation *p_CcNodeInformation, ccNodeInfo; -+ t_Handle p_Ad; -+ t_FmPcdCcNode *p_FmPcdCcNode1 = NULL; -+ t_FmPcdCcTree *p_FmPcdCcTree = NULL; -+ t_FmPcdStatsObj *p_StatsObj; -+ t_FmPcdCcStatsParams statsParams = { 0 }; -+ -+ ASSERT_COND(p_CcNextEngineParams); -+ -+ /* check that new NIA is legal */ -+ if (!p_AdditionalInfo->tree) -+ err = ValidateNextEngineParams( -+ h_FmPcd, p_CcNextEngineParams, -+ ((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->statisticsMode); -+ else -+ /* Statistics are not supported for CC root */ -+ err = ValidateNextEngineParams(h_FmPcd, p_CcNextEngineParams, -+ e_FM_PCD_CC_STATS_MODE_NONE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ /* Update internal data structure for next engine per index (index - key) */ -+ memcpy(&p_AdditionalInfo->keyAndNextEngineParams[keyIndex].nextEngineParams, -+ p_CcNextEngineParams, sizeof(t_FmPcdCcNextEngineParams)); -+ -+ /* Check that manip is legal and what requiredAction is necessary for this manip */ -+ if (p_CcNextEngineParams->h_Manip) -+ { -+ err = FmPcdManipCheckParamsForCcNextEngine(p_CcNextEngineParams, -+ &requiredAction); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ -+ if (!p_AdditionalInfo->tree) -+ { -+ p_FmPcdCcNode1 = (t_FmPcdCcNode *)h_FmPcdCcNodeOrTree; -+ p_AdditionalInfo->numOfKeys = p_FmPcdCcNode1->numOfKeys; -+ p_Ad = p_FmPcdCcNode1->h_AdTable; -+ -+ if (p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ p_AdditionalInfo->h_NodeForRmv = -+ p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.params.ccParams.h_CcNode; -+ -+ if (p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip) -+ p_AdditionalInfo->h_ManipForRmv = -+ p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip; -+ -+#if (DPAA_VERSION >= 11) -+ if ((p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine -+ == e_FM_PCD_FR) -+ && (p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic)) -+ p_AdditionalInfo->h_FrmReplicForRmv = -+ p_FmPcdCcNode1->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic; -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ else -+ { -+ p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcNodeOrTree; -+ p_Ad = UINT_TO_PTR(p_FmPcdCcTree->ccTreeBaseAddr); -+ -+ if (p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ p_AdditionalInfo->h_NodeForRmv = -+ p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.params.ccParams.h_CcNode; -+ -+ if (p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip) -+ p_AdditionalInfo->h_ManipForRmv = -+ p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.h_Manip; -+ -+#if (DPAA_VERSION >= 11) -+ if ((p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.nextEngine -+ == e_FM_PCD_FR) -+ && (p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic)) -+ p_AdditionalInfo->h_FrmReplicForRmv = -+ p_FmPcdCcTree->keyAndNextEngineParams[keyIndex].nextEngineParams.params.frParams.h_FrmReplic; -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ -+ if ((p_CcNextEngineParams->nextEngine == e_FM_PCD_CC) -+ && p_CcNextEngineParams->h_Manip) -+ { -+ err = AllocAndFillAdForContLookupManip( -+ p_CcNextEngineParams->params.ccParams.h_CcNode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ -+ ASSERT_COND(p_Ad); -+ -+ memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation)); -+ ccNodeInfo.h_CcNode = PTR_MOVE(p_Ad, keyIndex * FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ /* If statistics were enabled, this Ad is the statistics Ad. Need to follow its -+ nextAction to retrieve the actual Nia-Ad. If statistics should remain enabled, -+ only the actual Nia-Ad should be modified. */ -+ if ((!p_AdditionalInfo->tree) -+ && (((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->keyAndNextEngineParams[keyIndex].p_StatsObj) -+ && (p_CcNextEngineParams->statisticsEn)) -+ ccNodeInfo.h_CcNode = -+ ((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->keyAndNextEngineParams[keyIndex].p_StatsObj->h_StatsAd; -+ -+ EnqueueNodeInfoToRelevantLst(h_OldLst, &ccNodeInfo, NULL); -+ -+ memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation)); -+ p_Ad = GetNewAd(h_FmPcdCcNodeOrTree, p_AdditionalInfo->tree); -+ if (!p_Ad) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM allocation for CC node action descriptor")); -+ MemSet8((uint8_t *)p_Ad, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ /* If statistics were not enabled before, but requested now - Allocate a statistics -+ object that holds statistics AD and counters. */ -+ if ((!p_AdditionalInfo->tree) -+ && (!((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->keyAndNextEngineParams[keyIndex].p_StatsObj) -+ && (p_CcNextEngineParams->statisticsEn)) -+ { -+ p_StatsObj = GetStatsObj((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree); -+ ASSERT_COND(p_StatsObj); -+ -+ /* Store allocated statistics object */ -+ p_AdditionalInfo->keyAndNextEngineParams[keyIndex].p_StatsObj = -+ p_StatsObj; -+ -+ statsParams.h_StatsAd = p_StatsObj->h_StatsAd; -+ statsParams.h_StatsCounters = p_StatsObj->h_StatsCounters; -+ -+#if (DPAA_VERSION >= 11) -+ statsParams.h_StatsFLRs = -+ ((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->h_StatsFLRs; -+ -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ NextStepAd(p_Ad, &statsParams, p_CcNextEngineParams, h_FmPcd); -+ } -+ else -+ NextStepAd(p_Ad, NULL, p_CcNextEngineParams, h_FmPcd); -+ -+ ccNodeInfo.h_CcNode = p_Ad; -+ EnqueueNodeInfoToRelevantLst(h_NewLst, &ccNodeInfo, NULL); -+ -+ p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction = -+ requiredAction; -+ p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction |= -+ UPDATE_CC_WITH_TREE; -+ -+ if (!p_AdditionalInfo->tree) -+ { -+ ASSERT_COND(p_FmPcdCcNode1); -+ if (!LIST_IsEmpty(&p_FmPcdCcNode1->ccTreesLst)) -+ { -+ LIST_FOR_EACH(p_Pos, &p_FmPcdCcNode1->ccTreesLst) -+ { -+ p_CcNodeInformation = CC_NODE_F_OBJECT(p_Pos); -+ -+ ASSERT_COND(p_CcNodeInformation->h_CcNode); -+ /* Update the manipulation which has to be updated from parameters of the port -+ it's has to be updated with restrictions defined in the function */ -+ -+ err = -+ SetRequiredAction( -+ p_FmPcdCcNode1->h_FmPcd, -+ p_FmPcdCcNode1->shadowAction -+ | p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction, -+ &p_AdditionalInfo->keyAndNextEngineParams[keyIndex], -+ p_Ad, 1, p_CcNodeInformation->h_CcNode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ -+ err = CcUpdateParam( -+ p_FmPcdCcNode1->h_FmPcd, NULL, NULL, -+ &p_AdditionalInfo->keyAndNextEngineParams[keyIndex], 1, -+ p_Ad, TRUE, p_CcNodeInformation->index, -+ p_CcNodeInformation->h_CcNode, TRUE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ } -+ } -+ else -+ { -+ ASSERT_COND(p_FmPcdCcTree); -+ -+ err = -+ SetRequiredAction( -+ h_FmPcd, -+ p_FmPcdCcTree->requiredAction -+ | p_AdditionalInfo->keyAndNextEngineParams[keyIndex].requiredAction, -+ &p_AdditionalInfo->keyAndNextEngineParams[keyIndex], -+ p_Ad, 1, (t_Handle)p_FmPcdCcTree); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ -+ err = CcUpdateParam(h_FmPcd, NULL, NULL, -+ &p_AdditionalInfo->keyAndNextEngineParams[keyIndex], -+ 1, p_Ad, TRUE, 0, (t_Handle)p_FmPcdCcTree, TRUE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ -+ if (p_CcNextEngineParams->nextEngine == e_FM_PCD_CC) -+ p_AdditionalInfo->h_NodeForAdd = -+ p_CcNextEngineParams->params.ccParams.h_CcNode; -+ if (p_CcNextEngineParams->h_Manip) -+ p_AdditionalInfo->h_ManipForAdd = p_CcNextEngineParams->h_Manip; -+ -+ /* If statistics were previously enabled, but now are disabled, -+ store the old statistics object to be released */ -+ if ((!p_AdditionalInfo->tree) -+ && (((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->keyAndNextEngineParams[keyIndex].p_StatsObj) -+ && (!p_CcNextEngineParams->statisticsEn)) -+ { -+ p_AdditionalInfo->p_StatsObjForRmv = -+ ((t_FmPcdCcNode *)h_FmPcdCcNodeOrTree)->keyAndNextEngineParams[keyIndex].p_StatsObj; -+ -+ -+ p_AdditionalInfo->keyAndNextEngineParams[keyIndex].p_StatsObj = NULL; -+ } -+#if (DPAA_VERSION >= 11) -+ if ((p_CcNextEngineParams->nextEngine == e_FM_PCD_FR) -+ && (p_CcNextEngineParams->params.frParams.h_FrmReplic)) -+ p_AdditionalInfo->h_FrmReplicForAdd = -+ p_CcNextEngineParams->params.frParams.h_FrmReplic; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ return E_OK; -+} -+ -+static void UpdateAdPtrOfNodesWhichPointsOnCrntMdfNode( -+ t_FmPcdCcNode *p_CrntMdfNode, t_List *h_OldLst, -+ t_FmPcdCcNextEngineParams **p_NextEngineParams) -+{ -+ t_CcNodeInformation *p_CcNodeInformation; -+ t_FmPcdCcNode *p_NodePtrOnCurrentMdfNode = NULL; -+ t_List *p_Pos; -+ int i = 0; -+ t_Handle p_AdTablePtOnCrntCurrentMdfNode/*, p_AdTableNewModified*/; -+ t_CcNodeInformation ccNodeInfo; -+ -+ LIST_FOR_EACH(p_Pos, &p_CrntMdfNode->ccPrevNodesLst) -+ { -+ p_CcNodeInformation = CC_NODE_F_OBJECT(p_Pos); -+ p_NodePtrOnCurrentMdfNode = -+ (t_FmPcdCcNode *)p_CcNodeInformation->h_CcNode; -+ -+ ASSERT_COND(p_NodePtrOnCurrentMdfNode); -+ -+ /* Search in the previous node which exact index points on this current modified node for getting AD */ -+ for (i = 0; i < p_NodePtrOnCurrentMdfNode->numOfKeys + 1; i++) -+ { -+ if (p_NodePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ { -+ if (p_NodePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams.params.ccParams.h_CcNode -+ == (t_Handle)p_CrntMdfNode) -+ { -+ if (p_NodePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams.h_Manip) -+ p_AdTablePtOnCrntCurrentMdfNode = p_CrntMdfNode->h_Ad; -+ else -+ if (p_NodePtrOnCurrentMdfNode->keyAndNextEngineParams[i].p_StatsObj) -+ p_AdTablePtOnCrntCurrentMdfNode = -+ p_NodePtrOnCurrentMdfNode->keyAndNextEngineParams[i].p_StatsObj->h_StatsAd; -+ else -+ p_AdTablePtOnCrntCurrentMdfNode = -+ PTR_MOVE(p_NodePtrOnCurrentMdfNode->h_AdTable, i*FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation)); -+ ccNodeInfo.h_CcNode = p_AdTablePtOnCrntCurrentMdfNode; -+ EnqueueNodeInfoToRelevantLst(h_OldLst, &ccNodeInfo, NULL); -+ -+ if (!(*p_NextEngineParams)) -+ *p_NextEngineParams = -+ &p_NodePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams; -+ } -+ } -+ } -+ -+ ASSERT_COND(i != p_NodePtrOnCurrentMdfNode->numOfKeys); -+ } -+} -+ -+static void UpdateAdPtrOfTreesWhichPointsOnCrntMdfNode( -+ t_FmPcdCcNode *p_CrntMdfNode, t_List *h_OldLst, -+ t_FmPcdCcNextEngineParams **p_NextEngineParams) -+{ -+ t_CcNodeInformation *p_CcNodeInformation; -+ t_FmPcdCcTree *p_TreePtrOnCurrentMdfNode = NULL; -+ t_List *p_Pos; -+ int i = 0; -+ t_Handle p_AdTableTmp; -+ t_CcNodeInformation ccNodeInfo; -+ -+ LIST_FOR_EACH(p_Pos, &p_CrntMdfNode->ccTreeIdLst) -+ { -+ p_CcNodeInformation = CC_NODE_F_OBJECT(p_Pos); -+ p_TreePtrOnCurrentMdfNode = -+ (t_FmPcdCcTree *)p_CcNodeInformation->h_CcNode; -+ -+ ASSERT_COND(p_TreePtrOnCurrentMdfNode); -+ -+ /*search in the trees which exact index points on this current modified node for getting AD */ -+ for (i = 0; i < p_TreePtrOnCurrentMdfNode->numOfEntries; i++) -+ { -+ if (p_TreePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ { -+ if (p_TreePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams.params.ccParams.h_CcNode -+ == (t_Handle)p_CrntMdfNode) -+ { -+ p_AdTableTmp = -+ UINT_TO_PTR(p_TreePtrOnCurrentMdfNode->ccTreeBaseAddr + i*FM_PCD_CC_AD_ENTRY_SIZE); -+ memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation)); -+ ccNodeInfo.h_CcNode = p_AdTableTmp; -+ EnqueueNodeInfoToRelevantLst(h_OldLst, &ccNodeInfo, NULL); -+ -+ if (!(*p_NextEngineParams)) -+ *p_NextEngineParams = -+ &p_TreePtrOnCurrentMdfNode->keyAndNextEngineParams[i].nextEngineParams; -+ } -+ } -+ } -+ -+ ASSERT_COND(i == p_TreePtrOnCurrentMdfNode->numOfEntries); -+ } -+} -+ -+static t_FmPcdModifyCcKeyAdditionalParams * ModifyNodeCommonPart( -+ t_Handle h_FmPcdCcNodeOrTree, uint16_t keyIndex, -+ e_ModifyState modifyState, bool ttlCheck, bool hashCheck, bool tree) -+{ -+ t_FmPcdModifyCcKeyAdditionalParams *p_FmPcdModifyCcKeyAdditionalParams; -+ int i = 0, j = 0; -+ bool wasUpdate = FALSE; -+ t_FmPcdCcNode *p_CcNode = NULL; -+ t_FmPcdCcTree *p_FmPcdCcTree; -+ uint16_t numOfKeys; -+ t_FmPcdCcKeyAndNextEngineParams *p_KeyAndNextEngineParams; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmPcdCcNodeOrTree, E_INVALID_HANDLE, NULL); -+ -+ if (!tree) -+ { -+ p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNodeOrTree; -+ numOfKeys = p_CcNode->numOfKeys; -+ -+ /* node has to be pointed by another node or tree */ -+ -+ p_KeyAndNextEngineParams = (t_FmPcdCcKeyAndNextEngineParams *)XX_Malloc( -+ sizeof(t_FmPcdCcKeyAndNextEngineParams) * (numOfKeys + 1)); -+ if (!p_KeyAndNextEngineParams) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Next engine and required action structure")); -+ return NULL; -+ } -+ memcpy(p_KeyAndNextEngineParams, p_CcNode->keyAndNextEngineParams, -+ (numOfKeys + 1) * sizeof(t_FmPcdCcKeyAndNextEngineParams)); -+ -+ if (ttlCheck) -+ { -+ if ((p_CcNode->parseCode == CC_PC_FF_IPV4TTL) -+ || (p_CcNode->parseCode == CC_PC_FF_IPV6HOP_LIMIT)) -+ { -+ XX_Free(p_KeyAndNextEngineParams); -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("nodeId of CC_PC_FF_IPV4TTL or CC_PC_FF_IPV6HOP_LIMIT can not be used for this operation")); -+ return NULL; -+ } -+ } -+ -+ if (hashCheck) -+ { -+ if (p_CcNode->parseCode == CC_PC_GENERIC_IC_HASH_INDEXED) -+ { -+ XX_Free(p_KeyAndNextEngineParams); -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("nodeId of CC_PC_GENERIC_IC_HASH_INDEXED can not be used for this operation")); -+ return NULL; -+ } -+ } -+ } -+ else -+ { -+ p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcNodeOrTree; -+ numOfKeys = p_FmPcdCcTree->numOfEntries; -+ -+ p_KeyAndNextEngineParams = (t_FmPcdCcKeyAndNextEngineParams *)XX_Malloc( -+ sizeof(t_FmPcdCcKeyAndNextEngineParams) -+ * FM_PCD_MAX_NUM_OF_CC_GROUPS); -+ if (!p_KeyAndNextEngineParams) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Next engine and required action structure")); -+ return NULL; -+ } -+ memcpy(p_KeyAndNextEngineParams, -+ p_FmPcdCcTree->keyAndNextEngineParams, -+ FM_PCD_MAX_NUM_OF_CC_GROUPS -+ * sizeof(t_FmPcdCcKeyAndNextEngineParams)); -+ } -+ -+ p_FmPcdModifyCcKeyAdditionalParams = -+ (t_FmPcdModifyCcKeyAdditionalParams *)XX_Malloc( -+ sizeof(t_FmPcdModifyCcKeyAdditionalParams)); -+ if (!p_FmPcdModifyCcKeyAdditionalParams) -+ { -+ XX_Free(p_KeyAndNextEngineParams); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Allocation of internal data structure FAILED")); -+ return NULL; -+ } -+ memset(p_FmPcdModifyCcKeyAdditionalParams, 0, -+ sizeof(t_FmPcdModifyCcKeyAdditionalParams)); -+ -+ p_FmPcdModifyCcKeyAdditionalParams->h_CurrentNode = h_FmPcdCcNodeOrTree; -+ p_FmPcdModifyCcKeyAdditionalParams->savedKeyIndex = keyIndex; -+ -+ while (i < numOfKeys) -+ { -+ if ((j == keyIndex) && !wasUpdate) -+ { -+ if (modifyState == e_MODIFY_STATE_ADD) -+ j++; -+ else -+ if (modifyState == e_MODIFY_STATE_REMOVE) -+ i++; -+ wasUpdate = TRUE; -+ } -+ else -+ { -+ memcpy(&p_FmPcdModifyCcKeyAdditionalParams->keyAndNextEngineParams[j], -+ p_KeyAndNextEngineParams + i, -+ sizeof(t_FmPcdCcKeyAndNextEngineParams)); -+ i++; -+ j++; -+ } -+ } -+ -+ if (keyIndex == numOfKeys) -+ { -+ if (modifyState == e_MODIFY_STATE_ADD) -+ j++; -+ } -+ -+ memcpy(&p_FmPcdModifyCcKeyAdditionalParams->keyAndNextEngineParams[j], -+ p_KeyAndNextEngineParams + numOfKeys, -+ sizeof(t_FmPcdCcKeyAndNextEngineParams)); -+ -+ XX_Free(p_KeyAndNextEngineParams); -+ -+ return p_FmPcdModifyCcKeyAdditionalParams; -+} -+ -+static t_Error UpdatePtrWhichPointOnCrntMdfNode( -+ t_FmPcdCcNode *p_CcNode, -+ t_FmPcdModifyCcKeyAdditionalParams *p_FmPcdModifyCcKeyAdditionalParams, -+ t_List *h_OldLst, t_List *h_NewLst) -+{ -+ t_FmPcdCcNextEngineParams *p_NextEngineParams = NULL; -+ t_CcNodeInformation ccNodeInfo = { 0 }; -+ t_Handle h_NewAd; -+ t_Handle h_OrigAd = NULL; -+ -+ /* Building a list of all action descriptors that point to the previous node */ -+ if (!LIST_IsEmpty(&p_CcNode->ccPrevNodesLst)) -+ UpdateAdPtrOfNodesWhichPointsOnCrntMdfNode(p_CcNode, h_OldLst, -+ &p_NextEngineParams); -+ -+ if (!LIST_IsEmpty(&p_CcNode->ccTreeIdLst)) -+ UpdateAdPtrOfTreesWhichPointsOnCrntMdfNode(p_CcNode, h_OldLst, -+ &p_NextEngineParams); -+ -+ /* This node must be found as next engine of one of its previous nodes or trees*/ -+ if (p_NextEngineParams) -+ { -+ /* Building a new action descriptor that points to the modified node */ -+ h_NewAd = GetNewAd(p_CcNode, FALSE); -+ if (!h_NewAd) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ MemSet8(h_NewAd, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ h_OrigAd = p_CcNode->h_Ad; -+ BuildNewAd(h_NewAd, p_FmPcdModifyCcKeyAdditionalParams, p_CcNode, -+ p_NextEngineParams); -+ -+ ccNodeInfo.h_CcNode = h_NewAd; -+ EnqueueNodeInfoToRelevantLst(h_NewLst, &ccNodeInfo, NULL); -+ -+ if (p_NextEngineParams->h_Manip && !h_OrigAd) -+ FmPcdManipUpdateOwner(p_NextEngineParams->h_Manip, FALSE); -+ } -+ return E_OK; -+} -+ -+static void UpdateCcRootOwner(t_FmPcdCcTree *p_FmPcdCcTree, bool add) -+{ -+ ASSERT_COND(p_FmPcdCcTree); -+ -+ /* this routine must be protected by the calling routine! */ -+ -+ if (add) -+ p_FmPcdCcTree->owners++; -+ else -+ { -+ ASSERT_COND(p_FmPcdCcTree->owners); -+ p_FmPcdCcTree->owners--; -+ } -+} -+ -+static t_Error CheckAndSetManipParamsWithCcNodeParams(t_FmPcdCcNode *p_CcNode) -+{ -+ t_Error err = E_OK; -+ int i = 0; -+ -+ for (i = 0; i < p_CcNode->numOfKeys; i++) -+ { -+ if (p_CcNode->keyAndNextEngineParams[i].nextEngineParams.h_Manip) -+ { -+ err = -+ FmPcdManipCheckParamsWithCcNodeParams( -+ p_CcNode->keyAndNextEngineParams[i].nextEngineParams.h_Manip, -+ (t_Handle)p_CcNode); -+ if (err) -+ return err; -+ } -+ } -+ -+ return err; -+} -+static t_Error ValidateAndCalcStatsParams(t_FmPcdCcNode *p_CcNode, -+ t_FmPcdCcNodeParams *p_CcNodeParam, -+ uint32_t *p_NumOfRanges, -+ uint32_t *p_CountersArraySize) -+{ -+ e_FmPcdCcStatsMode statisticsMode = p_CcNode->statisticsMode; -+ uint32_t i; -+ -+ UNUSED(p_CcNodeParam); -+ -+ switch (statisticsMode) -+ { -+ case e_FM_PCD_CC_STATS_MODE_NONE: -+ for (i = 0; i < p_CcNode->numOfKeys; i++) -+ if (p_CcNodeParam->keysParams.keyParams[i].ccNextEngineParams.statisticsEn) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("Statistics cannot be enabled for key %d when statistics mode was set to 'NONE'", i)); -+ return E_OK; -+ -+ case e_FM_PCD_CC_STATS_MODE_FRAME: -+ case e_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME: -+ *p_NumOfRanges = 1; -+ *p_CountersArraySize = 2 * FM_PCD_CC_STATS_COUNTER_SIZE; -+ return E_OK; -+ -+#if (DPAA_VERSION >= 11) -+ case e_FM_PCD_CC_STATS_MODE_RMON: -+ { -+ uint16_t *p_FrameLengthRanges = -+ p_CcNodeParam->keysParams.frameLengthRanges; -+ uint32_t i; -+ -+ if (p_FrameLengthRanges[0] <= 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Statistics mode")); -+ -+ if (p_FrameLengthRanges[0] == 0xFFFF) -+ { -+ *p_NumOfRanges = 1; -+ *p_CountersArraySize = 2 * FM_PCD_CC_STATS_COUNTER_SIZE; -+ return E_OK; -+ } -+ -+ for (i = 1; i < FM_PCD_CC_STATS_MAX_NUM_OF_FLR; i++) -+ { -+ if (p_FrameLengthRanges[i - 1] >= p_FrameLengthRanges[i]) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("Frame length range must be larger at least by 1 from preceding range")); -+ -+ /* Stop when last range is reached */ -+ if (p_FrameLengthRanges[i] == 0xFFFF) -+ break; -+ } -+ -+ if ((i >= FM_PCD_CC_STATS_MAX_NUM_OF_FLR) -+ || (p_FrameLengthRanges[i] != 0xFFFF)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("Last Frame length range must be 0xFFFF")); -+ -+ *p_NumOfRanges = i + 1; -+ -+ /* Allocate an extra counter for byte count, as counters -+ array always begins with byte count */ -+ *p_CountersArraySize = (*p_NumOfRanges + 1) -+ * FM_PCD_CC_STATS_COUNTER_SIZE; -+ -+ } -+ return E_OK; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Statistics mode")); -+ } -+} -+ -+static t_Error CheckParams(t_Handle h_FmPcd, t_FmPcdCcNodeParams *p_CcNodeParam, -+ t_FmPcdCcNode *p_CcNode, bool *isKeyTblAlloc) -+{ -+ int tmp = 0; -+ t_FmPcdCcKeyParams *p_KeyParams; -+ t_Error err; -+ uint32_t requiredAction = 0; -+ -+ /* Validate statistics parameters */ -+ err = ValidateAndCalcStatsParams(p_CcNode, p_CcNodeParam, -+ &(p_CcNode->numOfStatsFLRs), -+ &(p_CcNode->countersArraySize)); -+ if (err) -+ RETURN_ERROR(MAJOR, err, ("Invalid statistics parameters")); -+ -+ /* Validate next engine parameters on Miss */ -+ err = ValidateNextEngineParams( -+ h_FmPcd, &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss, -+ p_CcNode->statisticsMode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, -+ ("For this node MissNextEngineParams are not valid")); -+ -+ if (p_CcNodeParam->keysParams.ccNextEngineParamsForMiss.h_Manip) -+ { -+ err = FmPcdManipCheckParamsForCcNextEngine( -+ &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss, -+ &requiredAction); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ -+ memcpy(&p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams, -+ &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss, -+ sizeof(t_FmPcdCcNextEngineParams)); -+ -+ p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].requiredAction = -+ requiredAction; -+ -+ if ((p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ && p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.h_Manip) -+ { -+ err = -+ AllocAndFillAdForContLookupManip( -+ p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.params.ccParams.h_CcNode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ -+ for (tmp = 0; tmp < p_CcNode->numOfKeys; tmp++) -+ { -+ p_KeyParams = &p_CcNodeParam->keysParams.keyParams[tmp]; -+ -+ if (!p_KeyParams->p_Key) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("p_Key is not initialized")); -+ -+ err = ValidateNextEngineParams(h_FmPcd, -+ &p_KeyParams->ccNextEngineParams, -+ p_CcNode->statisticsMode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ -+ err = UpdateGblMask(p_CcNode, p_CcNodeParam->keysParams.keySize, -+ p_KeyParams->p_Mask); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ -+ if (p_KeyParams->ccNextEngineParams.h_Manip) -+ { -+ err = FmPcdManipCheckParamsForCcNextEngine( -+ &p_KeyParams->ccNextEngineParams, &requiredAction); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ -+ /* Store 'key' parameters - key, mask (if passed by the user) */ -+ memcpy(p_CcNode->keyAndNextEngineParams[tmp].key, p_KeyParams->p_Key, -+ p_CcNodeParam->keysParams.keySize); -+ -+ if (p_KeyParams->p_Mask) -+ memcpy(p_CcNode->keyAndNextEngineParams[tmp].mask, -+ p_KeyParams->p_Mask, p_CcNodeParam->keysParams.keySize); -+ else -+ memset((void *)(p_CcNode->keyAndNextEngineParams[tmp].mask), 0xFF, -+ p_CcNodeParam->keysParams.keySize); -+ -+ /* Store next engine parameters */ -+ memcpy(&p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams, -+ &p_KeyParams->ccNextEngineParams, -+ sizeof(t_FmPcdCcNextEngineParams)); -+ -+ p_CcNode->keyAndNextEngineParams[tmp].requiredAction = requiredAction; -+ -+ if ((p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ && p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.h_Manip) -+ { -+ err = -+ AllocAndFillAdForContLookupManip( -+ p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.params.ccParams.h_CcNode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ } -+ -+ if (p_CcNode->maxNumOfKeys) -+ { -+ if (p_CcNode->maxNumOfKeys < p_CcNode->numOfKeys) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("Number of keys exceed the provided maximal number of keys")); -+ } -+ -+ *isKeyTblAlloc = TRUE; -+ -+ return E_OK; -+} -+ -+static t_Error Ipv4TtlOrIpv6HopLimitCheckParams( -+ t_Handle h_FmPcd, t_FmPcdCcNodeParams *p_CcNodeParam, -+ t_FmPcdCcNode *p_CcNode, bool *isKeyTblAlloc) -+{ -+ int tmp = 0; -+ t_FmPcdCcKeyParams *p_KeyParams; -+ t_Error err; -+ uint8_t key = 0x01; -+ uint32_t requiredAction = 0; -+ -+ if (p_CcNode->numOfKeys != 1) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("For node of the type IPV4_TTL or IPV6_HOP_LIMIT the maximal supported 'numOfKeys' is 1")); -+ -+ if ((p_CcNodeParam->keysParams.maxNumOfKeys) -+ && (p_CcNodeParam->keysParams.maxNumOfKeys != 1)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("For node of the type IPV4_TTL or IPV6_HOP_LIMIT the maximal supported 'maxNumOfKeys' is 1")); -+ -+ /* Validate statistics parameters */ -+ err = ValidateAndCalcStatsParams(p_CcNode, p_CcNodeParam, -+ &(p_CcNode->numOfStatsFLRs), -+ &(p_CcNode->countersArraySize)); -+ if (err) -+ RETURN_ERROR(MAJOR, err, ("Invalid statistics parameters")); -+ -+ err = ValidateNextEngineParams( -+ h_FmPcd, &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss, -+ p_CcNodeParam->keysParams.statisticsMode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, -+ ("For this node MissNextEngineParams are not valid")); -+ -+ if (p_CcNodeParam->keysParams.ccNextEngineParamsForMiss.h_Manip) -+ { -+ err = FmPcdManipCheckParamsForCcNextEngine( -+ &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss, -+ &requiredAction); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ -+ memcpy(&p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams, -+ &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss, -+ sizeof(t_FmPcdCcNextEngineParams)); -+ -+ p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].requiredAction = -+ requiredAction; -+ -+ if ((p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ && p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.h_Manip) -+ { -+ err = -+ AllocAndFillAdForContLookupManip( -+ p_CcNode->keyAndNextEngineParams[p_CcNode->numOfKeys].nextEngineParams.params.ccParams.h_CcNode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ -+ for (tmp = 0; tmp < p_CcNode->numOfKeys; tmp++) -+ { -+ p_KeyParams = &p_CcNodeParam->keysParams.keyParams[tmp]; -+ -+ if (p_KeyParams->p_Mask) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("For node of the type IPV4_TTL or IPV6_HOP_LIMIT p_Mask can not be initialized")); -+ -+ if (memcmp(p_KeyParams->p_Key, &key, 1) != 0) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("For node of the type IPV4_TTL or IPV6_HOP_LIMIT p_Key has to be 1")); -+ -+ err = ValidateNextEngineParams(h_FmPcd, -+ &p_KeyParams->ccNextEngineParams, -+ p_CcNode->statisticsMode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ -+ if (p_KeyParams->ccNextEngineParams.h_Manip) -+ { -+ err = FmPcdManipCheckParamsForCcNextEngine( -+ &p_KeyParams->ccNextEngineParams, &requiredAction); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ -+ /* Store 'key' parameters - key (fixed to 0x01), key size of 1 byte and full mask */ -+ p_CcNode->keyAndNextEngineParams[tmp].key[0] = key; -+ p_CcNode->keyAndNextEngineParams[tmp].mask[0] = 0xFF; -+ -+ /* Store NextEngine parameters */ -+ memcpy(&p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams, -+ &p_KeyParams->ccNextEngineParams, -+ sizeof(t_FmPcdCcNextEngineParams)); -+ -+ if ((p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ && p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.h_Manip) -+ { -+ err = -+ AllocAndFillAdForContLookupManip( -+ p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.params.ccParams.h_CcNode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ p_CcNode->keyAndNextEngineParams[tmp].requiredAction = requiredAction; -+ } -+ -+ *isKeyTblAlloc = FALSE; -+ -+ return E_OK; -+} -+ -+static t_Error IcHashIndexedCheckParams(t_Handle h_FmPcd, -+ t_FmPcdCcNodeParams *p_CcNodeParam, -+ t_FmPcdCcNode *p_CcNode, -+ bool *isKeyTblAlloc) -+{ -+ int tmp = 0, countOnes = 0; -+ t_FmPcdCcKeyParams *p_KeyParams; -+ t_Error err; -+ uint16_t glblMask = p_CcNodeParam->extractCcParams.extractNonHdr.icIndxMask; -+ uint16_t countMask = (uint16_t)(glblMask >> 4); -+ uint32_t requiredAction = 0; -+ -+ if (glblMask & 0x000f) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("icIndxMask has to be with last nibble 0")); -+ -+ while (countMask) -+ { -+ countOnes++; -+ countMask = (uint16_t)(countMask >> 1); -+ } -+ -+ if (!POWER_OF_2(p_CcNode->numOfKeys)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("For Node of the type INDEXED numOfKeys has to be powerOfTwo")); -+ -+ if (p_CcNode->numOfKeys != ((uint32_t)1 << countOnes)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("For Node of the type IC_HASH_INDEXED numOfKeys has to be powerOfTwo")); -+ -+ if (p_CcNodeParam->keysParams.maxNumOfKeys -+ && (p_CcNodeParam->keysParams.maxNumOfKeys != p_CcNode->numOfKeys)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("For Node of the type INDEXED 'maxNumOfKeys' should be 0 or equal 'numOfKeys'")); -+ -+ /* Validate statistics parameters */ -+ err = ValidateAndCalcStatsParams(p_CcNode, p_CcNodeParam, -+ &(p_CcNode->numOfStatsFLRs), -+ &(p_CcNode->countersArraySize)); -+ if (err) -+ RETURN_ERROR(MAJOR, err, ("Invalid statistics parameters")); -+ -+ err = ValidateNextEngineParams( -+ h_FmPcd, &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss, -+ p_CcNode->statisticsMode); -+ if (GET_ERROR_TYPE(err) != E_NOT_SUPPORTED) -+ RETURN_ERROR( -+ MAJOR, -+ err, -+ ("MissNextEngineParams for the node of the type IC_INDEX_HASH has to be UnInitialized")); -+ -+ for (tmp = 0; tmp < p_CcNode->numOfKeys; tmp++) -+ { -+ p_KeyParams = &p_CcNodeParam->keysParams.keyParams[tmp]; -+ -+ if (p_KeyParams->p_Mask || p_KeyParams->p_Key) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("For Node of the type IC_HASH_INDEXED p_Key or p_Mask has to be NULL")); -+ -+ if ((glblMask & (tmp * 16)) == (tmp * 16)) -+ { -+ err = ValidateNextEngineParams(h_FmPcd, -+ &p_KeyParams->ccNextEngineParams, -+ p_CcNode->statisticsMode); -+ if (err) -+ RETURN_ERROR( -+ MAJOR, -+ err, -+ ("This index has to be initialized for the node of the type IC_INDEX_HASH according to settings of GlobalMask ")); -+ -+ if (p_KeyParams->ccNextEngineParams.h_Manip) -+ { -+ err = FmPcdManipCheckParamsForCcNextEngine( -+ &p_KeyParams->ccNextEngineParams, &requiredAction); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ p_CcNode->keyAndNextEngineParams[tmp].requiredAction = -+ requiredAction; -+ } -+ -+ memcpy(&p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams, -+ &p_KeyParams->ccNextEngineParams, -+ sizeof(t_FmPcdCcNextEngineParams)); -+ -+ if ((p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ && p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.h_Manip) -+ { -+ err = -+ AllocAndFillAdForContLookupManip( -+ p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.params.ccParams.h_CcNode); -+ if (err) -+ RETURN_ERROR(MAJOR, err, (NO_MSG)); -+ } -+ } -+ else -+ { -+ err = ValidateNextEngineParams(h_FmPcd, -+ &p_KeyParams->ccNextEngineParams, -+ p_CcNode->statisticsMode); -+ if (GET_ERROR_TYPE(err) != E_NOT_SUPPORTED) -+ RETURN_ERROR( -+ MAJOR, -+ err, -+ ("This index has to be UnInitialized for the node of the type IC_INDEX_HASH according to settings of GlobalMask")); -+ } -+ } -+ -+ *isKeyTblAlloc = FALSE; -+ cpu_to_be16s(&glblMask); -+ memcpy(PTR_MOVE(p_CcNode->p_GlblMask, 2), &glblMask, 2); -+ -+ return E_OK; -+} -+ -+static t_Error ModifyNextEngineParamNode( -+ t_Handle h_FmPcd, t_Handle h_FmPcdCcNode, uint16_t keyIndex, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode; -+ t_FmPcd *p_FmPcd; -+ t_List h_OldPointersLst, h_NewPointersLst; -+ t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_VALUE); -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE); -+ -+ if (keyIndex >= p_CcNode->numOfKeys) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("keyIndex > previously cleared last index + 1")); -+ -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ -+ INIT_LIST(&h_OldPointersLst); -+ INIT_LIST(&h_NewPointersLst); -+ -+ p_ModifyKeyParams = ModifyNodeCommonPart(p_CcNode, keyIndex, -+ e_MODIFY_STATE_CHANGE, FALSE, -+ FALSE, FALSE); -+ if (!p_ModifyKeyParams) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ -+ if (p_CcNode->maxNumOfKeys -+ && !TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock)) -+ { -+ XX_Free(p_ModifyKeyParams); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = BuildNewNodeModifyNextEngine(h_FmPcd, p_CcNode, keyIndex, -+ p_FmPcdCcNextEngineParams, -+ &h_OldPointersLst, &h_NewPointersLst, -+ p_ModifyKeyParams); -+ if (err) -+ { -+ XX_Free(p_ModifyKeyParams); -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst, -+ p_ModifyKeyParams, FALSE); -+ -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ -+ return err; -+} -+ -+static t_Error FindKeyIndex(t_Handle h_CcNode, uint8_t keySize, uint8_t *p_Key, -+ uint8_t *p_Mask, uint16_t *p_KeyIndex) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ uint8_t tmpMask[FM_PCD_MAX_SIZE_OF_KEY]; -+ uint16_t i; -+ -+ ASSERT_COND(p_Key); -+ ASSERT_COND(p_KeyIndex); -+ ASSERT_COND(keySize < FM_PCD_MAX_SIZE_OF_KEY); -+ -+ if (keySize != p_CcNode->userSizeOfExtraction) -+ RETURN_ERROR( -+ MINOR, E_INVALID_VALUE, -+ ("Key size doesn't match the extraction size of the node")); -+ -+ /* If user didn't pass a mask for this key, we'll look for full extraction mask */ -+ if (!p_Mask) -+ memset(tmpMask, 0xFF, keySize); -+ -+ for (i = 0; i < p_CcNode->numOfKeys; i++) -+ { -+ /* Comparing received key */ -+ if (memcmp(p_Key, p_CcNode->keyAndNextEngineParams[i].key, keySize) -+ == 0) -+ { -+ if (p_Mask) -+ { -+ /* If a user passed a mask for this key, it must match to the existing key's mask for a correct match */ -+ if (memcmp(p_Mask, p_CcNode->keyAndNextEngineParams[i].mask, -+ keySize) == 0) -+ { -+ *p_KeyIndex = i; -+ return E_OK; -+ } -+ } -+ else -+ { -+ /* If user didn't pass a mask for this key, check if the existing key mask is full extraction */ -+ if (memcmp(tmpMask, p_CcNode->keyAndNextEngineParams[i].mask, -+ keySize) == 0) -+ { -+ *p_KeyIndex = i; -+ return E_OK; -+ } -+ } -+ } -+ } -+ -+ return ERROR_CODE(E_NOT_FOUND); -+} -+ -+static t_Error CalcAndUpdateCcShadow(t_FmPcdCcNode *p_CcNode, -+ bool isKeyTblAlloc, -+ uint32_t *p_MatchTableSize, -+ uint32_t *p_AdTableSize) -+{ -+ uint32_t shadowSize; -+ t_Error err; -+ -+ /* Calculate keys table maximal size - each entry consists of a key and a mask, -+ (if local mask support is requested) */ -+ *p_MatchTableSize = p_CcNode->ccKeySizeAccExtraction * sizeof(uint8_t) -+ * p_CcNode->maxNumOfKeys; -+ -+ if (p_CcNode->maskSupport) -+ *p_MatchTableSize *= 2; -+ -+ /* Calculate next action descriptors table, including one more entry for miss */ -+ *p_AdTableSize = (uint32_t)((p_CcNode->maxNumOfKeys + 1) -+ * FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ /* Calculate maximal shadow size of this node. -+ All shadow structures will be used for runtime modifications host command. If -+ keys table was allocated for this node, the keys table and next engines table may -+ be modified in run time (entries added or removed), so shadow tables are requires. -+ Otherwise, the only supported runtime modification is a specific next engine update -+ and this requires shadow memory of a single AD */ -+ -+ /* Shadow size should be enough to hold the following 3 structures: -+ * 1 - an action descriptor */ -+ shadowSize = FM_PCD_CC_AD_ENTRY_SIZE; -+ -+ /* 2 - keys match table, if was allocated for the current node */ -+ if (isKeyTblAlloc) -+ shadowSize += *p_MatchTableSize; -+ -+ /* 3 - next action descriptors table */ -+ shadowSize += *p_AdTableSize; -+ -+ /* Update shadow to the calculated size */ -+ err = FmPcdUpdateCcShadow(p_CcNode->h_FmPcd, (uint32_t)shadowSize, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (err != E_OK) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM allocation for CC node shadow")); -+ } -+ -+ return E_OK; -+} -+ -+static t_Error AllocStatsObjs(t_FmPcdCcNode *p_CcNode) -+{ -+ t_FmPcdStatsObj *p_StatsObj; -+ t_Handle h_FmMuram, h_StatsAd, h_StatsCounters; -+ uint32_t i; -+ -+ h_FmMuram = FmPcdGetMuramHandle(p_CcNode->h_FmPcd); -+ if (!h_FmMuram) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("FM MURAM")); -+ -+ /* Allocate statistics ADs and statistics counter. An extra pair (AD + counters) -+ will be allocated to support runtime modifications */ -+ for (i = 0; i < p_CcNode->maxNumOfKeys + 2; i++) -+ { -+ /* Allocate list object structure */ -+ p_StatsObj = XX_Malloc(sizeof(t_FmPcdStatsObj)); -+ if (!p_StatsObj) -+ { -+ FreeStatObjects(&p_CcNode->availableStatsLst, h_FmMuram); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Statistics object")); -+ } -+ memset(p_StatsObj, 0, sizeof(t_FmPcdStatsObj)); -+ -+ /* Allocate statistics AD from MURAM */ -+ h_StatsAd = (t_Handle)FM_MURAM_AllocMem(h_FmMuram, -+ FM_PCD_CC_AD_ENTRY_SIZE, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!h_StatsAd) -+ { -+ FreeStatObjects(&p_CcNode->availableStatsLst, h_FmMuram); -+ XX_Free(p_StatsObj); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM allocation for statistics ADs")); -+ } -+ MemSet8(h_StatsAd, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ /* Allocate statistics counters from MURAM */ -+ h_StatsCounters = (t_Handle)FM_MURAM_AllocMem( -+ h_FmMuram, p_CcNode->countersArraySize, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!h_StatsCounters) -+ { -+ FreeStatObjects(&p_CcNode->availableStatsLst, h_FmMuram); -+ FM_MURAM_FreeMem(h_FmMuram, h_StatsAd); -+ XX_Free(p_StatsObj); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM allocation for statistics counters")); -+ } -+ MemSet8(h_StatsCounters, 0, p_CcNode->countersArraySize); -+ -+ p_StatsObj->h_StatsAd = h_StatsAd; -+ p_StatsObj->h_StatsCounters = h_StatsCounters; -+ -+ EnqueueStatsObj(&p_CcNode->availableStatsLst, p_StatsObj); -+ } -+ -+ return E_OK; -+} -+ -+static t_Error MatchTableGetKeyStatistics( -+ t_FmPcdCcNode *p_CcNode, uint16_t keyIndex, -+ t_FmPcdCcKeyStatistics *p_KeyStatistics) -+{ -+ uint32_t *p_StatsCounters, i; -+ -+ if (p_CcNode->statisticsMode == e_FM_PCD_CC_STATS_MODE_NONE) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("Statistics were not enabled for this match table")); -+ -+ if (!p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("Statistics were not enabled for this key")); -+ -+ memset(p_KeyStatistics, 0, sizeof(t_FmPcdCcKeyStatistics)); -+ -+ p_StatsCounters = -+ p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj->h_StatsCounters; -+ ASSERT_COND(p_StatsCounters); -+ -+ p_KeyStatistics->byteCount = GET_UINT32(*p_StatsCounters); -+ -+ for (i = 1; i <= p_CcNode->numOfStatsFLRs; i++) -+ { -+ p_StatsCounters = -+ PTR_MOVE(p_StatsCounters, FM_PCD_CC_STATS_COUNTER_SIZE); -+ -+ p_KeyStatistics->frameCount += GET_UINT32(*p_StatsCounters); -+ -+#if (DPAA_VERSION >= 11) -+ p_KeyStatistics->frameLengthRangeCount[i - 1] = -+ GET_UINT32(*p_StatsCounters); -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ -+ return E_OK; -+} -+ -+static t_Error MatchTableSet(t_Handle h_FmPcd, t_FmPcdCcNode *p_CcNode, -+ t_FmPcdCcNodeParams *p_CcNodeParam) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ t_FmPcdCcNode *p_FmPcdCcNextNode; -+ t_Error err = E_OK; -+ uint32_t tmp, keySize; -+ bool glblMask = FALSE; -+ t_FmPcdCcKeyParams *p_KeyParams; -+ t_Handle h_FmMuram, p_KeysMatchTblTmp, p_AdTableTmp; -+#if (DPAA_VERSION >= 11) -+ t_Handle h_StatsFLRs; -+#endif /* (DPAA_VERSION >= 11) */ -+ bool fullField = FALSE; -+ ccPrivateInfo_t icCode = CC_PRIVATE_INFO_NONE; -+ bool isKeyTblAlloc, fromIc = FALSE; -+ uint32_t matchTableSize, adTableSize; -+ t_CcNodeInformation ccNodeInfo, *p_CcInformation; -+ t_FmPcdStatsObj *p_StatsObj; -+ t_FmPcdCcStatsParams statsParams = { 0 }; -+ t_Handle h_Manip; -+ -+ ASSERT_COND(h_FmPcd); -+ ASSERT_COND(p_CcNode); -+ ASSERT_COND(p_CcNodeParam); -+ -+ p_CcNode->p_GlblMask = (t_Handle)XX_Malloc( -+ CC_GLBL_MASK_SIZE * sizeof(uint8_t)); -+ memset(p_CcNode->p_GlblMask, 0, CC_GLBL_MASK_SIZE * sizeof(uint8_t)); -+ -+ p_CcNode->h_FmPcd = h_FmPcd; -+ p_CcNode->numOfKeys = p_CcNodeParam->keysParams.numOfKeys; -+ p_CcNode->maxNumOfKeys = p_CcNodeParam->keysParams.maxNumOfKeys; -+ p_CcNode->maskSupport = p_CcNodeParam->keysParams.maskSupport; -+ p_CcNode->statisticsMode = p_CcNodeParam->keysParams.statisticsMode; -+ -+ /* For backward compatibility - even if statistics mode is nullified, -+ we'll fix it to frame mode so we can support per-key request for -+ statistics using 'statisticsEn' in next engine parameters */ -+ if (!p_CcNode->maxNumOfKeys -+ && (p_CcNode->statisticsMode == e_FM_PCD_CC_STATS_MODE_NONE)) -+ p_CcNode->statisticsMode = e_FM_PCD_CC_STATS_MODE_FRAME; -+ -+ h_FmMuram = FmPcdGetMuramHandle(h_FmPcd); -+ if (!h_FmMuram) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("FM MURAM")); -+ -+ INIT_LIST(&p_CcNode->ccPrevNodesLst); -+ INIT_LIST(&p_CcNode->ccTreeIdLst); -+ INIT_LIST(&p_CcNode->ccTreesLst); -+ INIT_LIST(&p_CcNode->availableStatsLst); -+ -+ p_CcNode->h_Spinlock = XX_InitSpinlock(); -+ if (!p_CcNode->h_Spinlock) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("CC node spinlock")); -+ } -+ -+ if ((p_CcNodeParam->extractCcParams.type == e_FM_PCD_EXTRACT_BY_HDR) -+ && ((p_CcNodeParam->extractCcParams.extractByHdr.hdr -+ == HEADER_TYPE_IPv4) -+ || (p_CcNodeParam->extractCcParams.extractByHdr.hdr -+ == HEADER_TYPE_IPv6)) -+ && (p_CcNodeParam->extractCcParams.extractByHdr.type -+ == e_FM_PCD_EXTRACT_FULL_FIELD) -+ && ((p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fullField.ipv6 -+ == NET_HEADER_FIELD_IPv6_HOP_LIMIT) -+ || (p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fullField.ipv4 -+ == NET_HEADER_FIELD_IPv4_TTL))) -+ { -+ err = Ipv4TtlOrIpv6HopLimitCheckParams(h_FmPcd, p_CcNodeParam, p_CcNode, -+ &isKeyTblAlloc); -+ glblMask = FALSE; -+ } -+ else -+ if ((p_CcNodeParam->extractCcParams.type == e_FM_PCD_EXTRACT_NON_HDR) -+ && ((p_CcNodeParam->extractCcParams.extractNonHdr.src -+ == e_FM_PCD_EXTRACT_FROM_KEY) -+ || (p_CcNodeParam->extractCcParams.extractNonHdr.src -+ == e_FM_PCD_EXTRACT_FROM_HASH) -+ || (p_CcNodeParam->extractCcParams.extractNonHdr.src -+ == e_FM_PCD_EXTRACT_FROM_FLOW_ID))) -+ { -+ if ((p_CcNodeParam->extractCcParams.extractNonHdr.src -+ == e_FM_PCD_EXTRACT_FROM_FLOW_ID) -+ && (p_CcNodeParam->extractCcParams.extractNonHdr.offset != 0)) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("In the case of the extraction from e_FM_PCD_EXTRACT_FROM_FLOW_ID offset has to be 0")); -+ } -+ -+ icCode = IcDefineCode(p_CcNodeParam); -+ fromIc = TRUE; -+ if (icCode == CC_PRIVATE_INFO_NONE) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("user asked extraction from IC and field in internal context or action wasn't initialized in the right way")); -+ } -+ -+ if ((icCode == CC_PRIVATE_INFO_IC_DEQ_FQID_INDEX_LOOKUP) -+ || (icCode == CC_PRIVATE_INFO_IC_HASH_INDEX_LOOKUP)) -+ { -+ err = IcHashIndexedCheckParams(h_FmPcd, p_CcNodeParam, p_CcNode, -+ &isKeyTblAlloc); -+ glblMask = TRUE; -+ } -+ else -+ { -+ err = CheckParams(h_FmPcd, p_CcNodeParam, p_CcNode, -+ &isKeyTblAlloc); -+ if (p_CcNode->glblMaskSize) -+ glblMask = TRUE; -+ } -+ } -+ else -+ { -+ err = CheckParams(h_FmPcd, p_CcNodeParam, p_CcNode, &isKeyTblAlloc); -+ if (p_CcNode->glblMaskSize) -+ glblMask = TRUE; -+ } -+ -+ if (err) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ switch (p_CcNodeParam->extractCcParams.type) -+ { -+ case (e_FM_PCD_EXTRACT_BY_HDR): -+ switch (p_CcNodeParam->extractCcParams.extractByHdr.type) -+ { -+ case (e_FM_PCD_EXTRACT_FULL_FIELD): -+ p_CcNode->parseCode = -+ GetFullFieldParseCode( -+ p_CcNodeParam->extractCcParams.extractByHdr.hdr, -+ p_CcNodeParam->extractCcParams.extractByHdr.hdrIndex, -+ p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fullField); -+ GetSizeHeaderField( -+ p_CcNodeParam->extractCcParams.extractByHdr.hdr, -+ p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fullField, -+ &p_CcNode->sizeOfExtraction); -+ fullField = TRUE; -+ if ((p_CcNode->parseCode != CC_PC_FF_TCI1) -+ && (p_CcNode->parseCode != CC_PC_FF_TCI2) -+ && (p_CcNode->parseCode != CC_PC_FF_MPLS1) -+ && (p_CcNode->parseCode != CC_PC_FF_MPLS_LAST) -+ && (p_CcNode->parseCode != CC_PC_FF_IPV4IPTOS_TC1) -+ && (p_CcNode->parseCode != CC_PC_FF_IPV4IPTOS_TC2) -+ && (p_CcNode->parseCode -+ != CC_PC_FF_IPTOS_IPV6TC1_IPV6FLOW1) -+ && (p_CcNode->parseCode != CC_PC_FF_IPDSCP) -+ && (p_CcNode->parseCode -+ != CC_PC_FF_IPTOS_IPV6TC2_IPV6FLOW2) -+ && glblMask) -+ { -+ glblMask = FALSE; -+ p_CcNode->glblMaskSize = 4; -+ p_CcNode->lclMask = TRUE; -+ } -+ break; -+ -+ case (e_FM_PCD_EXTRACT_FROM_HDR): -+ p_CcNode->sizeOfExtraction = -+ p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromHdr.size; -+ p_CcNode->offset = -+ p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromHdr.offset; -+ p_CcNode->userOffset = -+ p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromHdr.offset; -+ p_CcNode->parseCode = -+ GetPrParseCode( -+ p_CcNodeParam->extractCcParams.extractByHdr.hdr, -+ p_CcNodeParam->extractCcParams.extractByHdr.hdrIndex, -+ p_CcNode->offset, glblMask, -+ &p_CcNode->prsArrayOffset); -+ break; -+ -+ case (e_FM_PCD_EXTRACT_FROM_FIELD): -+ p_CcNode->offset = -+ p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromField.offset; -+ p_CcNode->userOffset = -+ p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromField.offset; -+ p_CcNode->sizeOfExtraction = -+ p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromField.size; -+ p_CcNode->parseCode = -+ GetFieldParseCode( -+ p_CcNodeParam->extractCcParams.extractByHdr.hdr, -+ p_CcNodeParam->extractCcParams.extractByHdr.extractByHdrType.fromField.field, -+ p_CcNode->offset, -+ &p_CcNode->prsArrayOffset, -+ p_CcNodeParam->extractCcParams.extractByHdr.hdrIndex); -+ break; -+ -+ default: -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ break; -+ -+ case (e_FM_PCD_EXTRACT_NON_HDR): -+ /* get the field code for the generic extract */ -+ p_CcNode->sizeOfExtraction = -+ p_CcNodeParam->extractCcParams.extractNonHdr.size; -+ p_CcNode->offset = -+ p_CcNodeParam->extractCcParams.extractNonHdr.offset; -+ p_CcNode->userOffset = -+ p_CcNodeParam->extractCcParams.extractNonHdr.offset; -+ p_CcNode->parseCode = GetGenParseCode( -+ p_CcNodeParam->extractCcParams.extractNonHdr.src, -+ p_CcNode->offset, glblMask, &p_CcNode->prsArrayOffset, -+ fromIc, icCode); -+ -+ if (p_CcNode->parseCode == CC_PC_GENERIC_IC_HASH_INDEXED) -+ { -+ if ((p_CcNode->offset + p_CcNode->sizeOfExtraction) > 8) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_SELECTION, -+ ("when node of the type CC_PC_GENERIC_IC_HASH_INDEXED offset + size can not be bigger then size of HASH 64 bits (8 bytes)")); -+ } -+ } -+ if ((p_CcNode->parseCode == CC_PC_GENERIC_IC_GMASK) -+ || (p_CcNode->parseCode == CC_PC_GENERIC_IC_HASH_INDEXED)) -+ { -+ p_CcNode->offset += p_CcNode->prsArrayOffset; -+ p_CcNode->prsArrayOffset = 0; -+ } -+ break; -+ -+ default: -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ -+ if (p_CcNode->parseCode == CC_PC_ILLEGAL) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("illegal extraction type")); -+ } -+ -+ if ((p_CcNode->sizeOfExtraction > FM_PCD_MAX_SIZE_OF_KEY) -+ || !p_CcNode->sizeOfExtraction) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("sizeOfExatrction can not be greater than 56 and not 0")); -+ } -+ -+ if (p_CcNodeParam->keysParams.keySize != p_CcNode->sizeOfExtraction) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("keySize has to be equal to sizeOfExtraction")); -+ } -+ -+ p_CcNode->userSizeOfExtraction = p_CcNode->sizeOfExtraction; -+ -+ if (!glblMask) -+ memset(p_CcNode->p_GlblMask, 0xff, CC_GLBL_MASK_SIZE * sizeof(uint8_t)); -+ -+ err = CheckAndSetManipParamsWithCcNodeParams(p_CcNode); -+ if (err != E_OK) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("keySize has to be equal to sizeOfExtraction")); -+ } -+ -+ /* Calculating matching table entry size by rounding up the user-defined size of extraction to valid entry size */ -+ GetCcExtractKeySize(p_CcNode->sizeOfExtraction, -+ &p_CcNode->ccKeySizeAccExtraction); -+ -+ /* If local mask is used, it is stored next to each key in the keys match table */ -+ if (p_CcNode->lclMask) -+ keySize = (uint32_t)(2 * p_CcNode->ccKeySizeAccExtraction); -+ else -+ keySize = p_CcNode->ccKeySizeAccExtraction; -+ -+ /* Update CC shadow with maximal size required by this node */ -+ if (p_CcNode->maxNumOfKeys) -+ { -+ err = CalcAndUpdateCcShadow(p_CcNode, isKeyTblAlloc, &matchTableSize, -+ &adTableSize); -+ if (err != E_OK) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ p_CcNode->keysMatchTableMaxSize = matchTableSize; -+ -+ if (p_CcNode->statisticsMode != e_FM_PCD_CC_STATS_MODE_NONE) -+ { -+ err = AllocStatsObjs(p_CcNode); -+ if (err != E_OK) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ } -+ -+ /* If manipulation will be initialized before this node, it will use the table -+ descriptor in the AD table of previous node and this node will need an extra -+ AD as his table descriptor. */ -+ p_CcNode->h_TmpAd = (t_Handle)FM_MURAM_AllocMem( -+ h_FmMuram, FM_PCD_CC_AD_ENTRY_SIZE, FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_CcNode->h_TmpAd) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM allocation for CC action descriptor")); -+ } -+ } -+ else -+ { -+ matchTableSize = (uint32_t)(keySize * sizeof(uint8_t) -+ * (p_CcNode->numOfKeys + 1)); -+ adTableSize = (uint32_t)(FM_PCD_CC_AD_ENTRY_SIZE -+ * (p_CcNode->numOfKeys + 1)); -+ } -+ -+#if (DPAA_VERSION >= 11) -+ switch (p_CcNode->statisticsMode) -+ { -+ -+ case e_FM_PCD_CC_STATS_MODE_RMON: -+ /* If RMON statistics or RMON conditional statistics modes are requested, -+ allocate frame length ranges array */ -+ p_CcNode->h_StatsFLRs = FM_MURAM_AllocMem( -+ h_FmMuram, -+ (uint32_t)(p_CcNode->numOfStatsFLRs) -+ * FM_PCD_CC_STATS_FLR_SIZE, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ -+ if (!p_CcNode->h_StatsFLRs) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR( -+ MAJOR, E_NO_MEMORY, -+ ("MURAM allocation for CC frame length ranges array")); -+ } -+ -+ /* Initialize using value received from the user */ -+ for (tmp = 0; tmp < p_CcNode->numOfStatsFLRs; tmp++) -+ { -+ uint16_t flr = -+ cpu_to_be16(p_CcNodeParam->keysParams.frameLengthRanges[tmp]); -+ -+ h_StatsFLRs = -+ PTR_MOVE(p_CcNode->h_StatsFLRs, tmp * FM_PCD_CC_STATS_FLR_SIZE); -+ -+ MemCpy8(h_StatsFLRs, -+ &flr, -+ FM_PCD_CC_STATS_FLR_SIZE); -+ } -+ break; -+ -+ default: -+ break; -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ /* Allocate keys match table. Not required for some CC nodes, for example for IPv4 TTL -+ identification, IPv6 hop count identification, etc. */ -+ if (isKeyTblAlloc) -+ { -+ p_CcNode->h_KeysMatchTable = (t_Handle)FM_MURAM_AllocMem( -+ h_FmMuram, matchTableSize, FM_PCD_CC_KEYS_MATCH_TABLE_ALIGN); -+ if (!p_CcNode->h_KeysMatchTable) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM allocation for CC node key match table")); -+ } -+ MemSet8((uint8_t *)p_CcNode->h_KeysMatchTable, 0, matchTableSize); -+ } -+ -+ /* Allocate action descriptors table */ -+ p_CcNode->h_AdTable = (t_Handle)FM_MURAM_AllocMem(h_FmMuram, adTableSize, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_CcNode->h_AdTable) -+ { -+ DeleteNode(p_CcNode); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM allocation for CC node action descriptors table")); -+ } -+ MemSet8((uint8_t *)p_CcNode->h_AdTable, 0, adTableSize); -+ -+ p_KeysMatchTblTmp = p_CcNode->h_KeysMatchTable; -+ p_AdTableTmp = p_CcNode->h_AdTable; -+ -+ /* For each key, create the key and the next step AD */ -+ for (tmp = 0; tmp < p_CcNode->numOfKeys; tmp++) -+ { -+ p_KeyParams = &p_CcNodeParam->keysParams.keyParams[tmp]; -+ -+ if (p_KeysMatchTblTmp) -+ { -+ /* Copy the key */ -+ MemCpy8((void*)p_KeysMatchTblTmp, p_KeyParams->p_Key, -+ p_CcNode->sizeOfExtraction); -+ -+ /* Copy the key mask or initialize it to 0xFF..F */ -+ if (p_CcNode->lclMask && p_KeyParams->p_Mask) -+ { -+ MemCpy8(PTR_MOVE(p_KeysMatchTblTmp, -+ p_CcNode->ccKeySizeAccExtraction), /* User's size of extraction rounded up to a valid matching table entry size */ -+ p_KeyParams->p_Mask, p_CcNode->sizeOfExtraction); /* Exact size of extraction as received from the user */ -+ } -+ else -+ if (p_CcNode->lclMask) -+ { -+ MemSet8(PTR_MOVE(p_KeysMatchTblTmp, -+ p_CcNode->ccKeySizeAccExtraction), /* User's size of extraction rounded up to a valid matching table entry size */ -+ 0xff, p_CcNode->sizeOfExtraction); /* Exact size of extraction as received from the user */ -+ } -+ -+ p_KeysMatchTblTmp = -+ PTR_MOVE(p_KeysMatchTblTmp, keySize * sizeof(uint8_t)); -+ } -+ -+ /* Create the next action descriptor in the match table */ -+ if (p_KeyParams->ccNextEngineParams.statisticsEn) -+ { -+ p_StatsObj = GetStatsObj(p_CcNode); -+ ASSERT_COND(p_StatsObj); -+ -+ statsParams.h_StatsAd = p_StatsObj->h_StatsAd; -+ statsParams.h_StatsCounters = p_StatsObj->h_StatsCounters; -+#if (DPAA_VERSION >= 11) -+ statsParams.h_StatsFLRs = p_CcNode->h_StatsFLRs; -+ -+#endif /* (DPAA_VERSION >= 11) */ -+ NextStepAd(p_AdTableTmp, &statsParams, -+ &p_KeyParams->ccNextEngineParams, p_FmPcd); -+ -+ p_CcNode->keyAndNextEngineParams[tmp].p_StatsObj = p_StatsObj; -+ } -+ else -+ { -+ NextStepAd(p_AdTableTmp, NULL, &p_KeyParams->ccNextEngineParams, -+ p_FmPcd); -+ -+ p_CcNode->keyAndNextEngineParams[tmp].p_StatsObj = NULL; -+ } -+ -+ p_AdTableTmp = PTR_MOVE(p_AdTableTmp, FM_PCD_CC_AD_ENTRY_SIZE); -+ } -+ -+ /* Update next engine for the 'miss' entry */ -+ if (p_CcNodeParam->keysParams.ccNextEngineParamsForMiss.statisticsEn) -+ { -+ p_StatsObj = GetStatsObj(p_CcNode); -+ ASSERT_COND(p_StatsObj); -+ -+ /* All 'bucket' nodes of a hash table should share the same statistics counters, -+ allocated by the hash table. So, if this node is a bucket of a hash table, -+ we'll replace the locally allocated counters with the shared counters. */ -+ if (p_CcNode->isHashBucket) -+ { -+ ASSERT_COND(p_CcNode->h_MissStatsCounters); -+ -+ /* Store original counters pointer and replace it with mutual preallocated pointer */ -+ p_CcNode->h_PrivMissStatsCounters = p_StatsObj->h_StatsCounters; -+ p_StatsObj->h_StatsCounters = p_CcNode->h_MissStatsCounters; -+ } -+ -+ statsParams.h_StatsAd = p_StatsObj->h_StatsAd; -+ statsParams.h_StatsCounters = p_StatsObj->h_StatsCounters; -+#if (DPAA_VERSION >= 11) -+ statsParams.h_StatsFLRs = p_CcNode->h_StatsFLRs; -+ -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ NextStepAd(p_AdTableTmp, &statsParams, -+ &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss, -+ p_FmPcd); -+ -+ p_CcNode->keyAndNextEngineParams[tmp].p_StatsObj = p_StatsObj; -+ } -+ else -+ { -+ NextStepAd(p_AdTableTmp, NULL, -+ &p_CcNodeParam->keysParams.ccNextEngineParamsForMiss, -+ p_FmPcd); -+ -+ p_CcNode->keyAndNextEngineParams[tmp].p_StatsObj = NULL; -+ } -+ -+ /* This parameter will be used to initialize the "key length" field in the action descriptor -+ that points to this node and it should be 0 for full field extraction */ -+ if (fullField == TRUE) -+ p_CcNode->sizeOfExtraction = 0; -+ -+ for (tmp = 0; tmp < MIN(p_CcNode->numOfKeys + 1, CC_MAX_NUM_OF_KEYS); tmp++) -+ { -+ if (p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ { -+ p_FmPcdCcNextNode = -+ (t_FmPcdCcNode*)p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.params.ccParams.h_CcNode; -+ p_CcInformation = FindNodeInfoInReleventLst( -+ &p_FmPcdCcNextNode->ccPrevNodesLst, (t_Handle)p_CcNode, -+ p_FmPcdCcNextNode->h_Spinlock); -+ if (!p_CcInformation) -+ { -+ memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation)); -+ ccNodeInfo.h_CcNode = (t_Handle)p_CcNode; -+ ccNodeInfo.index = 1; -+ EnqueueNodeInfoToRelevantLst(&p_FmPcdCcNextNode->ccPrevNodesLst, -+ &ccNodeInfo, -+ p_FmPcdCcNextNode->h_Spinlock); -+ } -+ else -+ p_CcInformation->index++; -+ -+ if (p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.h_Manip) -+ { -+ h_Manip = -+ p_CcNode->keyAndNextEngineParams[tmp].nextEngineParams.h_Manip; -+ p_CcInformation = FindNodeInfoInReleventLst( -+ FmPcdManipGetNodeLstPointedOnThisManip(h_Manip), -+ (t_Handle)p_CcNode, FmPcdManipGetSpinlock(h_Manip)); -+ if (!p_CcInformation) -+ { -+ memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation)); -+ ccNodeInfo.h_CcNode = (t_Handle)p_CcNode; -+ ccNodeInfo.index = 1; -+ EnqueueNodeInfoToRelevantLst( -+ FmPcdManipGetNodeLstPointedOnThisManip(h_Manip), -+ &ccNodeInfo, FmPcdManipGetSpinlock(h_Manip)); -+ } -+ else -+ p_CcInformation->index++; -+ } -+ } -+ } -+ -+ p_AdTableTmp = p_CcNode->h_AdTable; -+ -+ if (!FmPcdLockTryLockAll(h_FmPcd)) -+ { -+ FM_PCD_MatchTableDelete((t_Handle)p_CcNode); -+ DBG(TRACE, ("FmPcdLockTryLockAll failed")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ /* Required action for each next engine */ -+ for (tmp = 0; tmp < MIN(p_CcNode->numOfKeys + 1, CC_MAX_NUM_OF_KEYS); tmp++) -+ { -+ if (p_CcNode->keyAndNextEngineParams[tmp].requiredAction) -+ { -+ err = SetRequiredAction( -+ h_FmPcd, -+ p_CcNode->keyAndNextEngineParams[tmp].requiredAction, -+ &p_CcNode->keyAndNextEngineParams[tmp], p_AdTableTmp, 1, -+ NULL); -+ if (err) -+ { -+ FmPcdLockUnlockAll(h_FmPcd); -+ FM_PCD_MatchTableDelete((t_Handle)p_CcNode); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ p_AdTableTmp = PTR_MOVE(p_AdTableTmp, FM_PCD_CC_AD_ENTRY_SIZE); -+ } -+ } -+ -+ FmPcdLockUnlockAll(h_FmPcd); -+ -+ return E_OK; -+} -+/************************** End of static functions **************************/ -+ -+/*****************************************************************************/ -+/* Inter-module API routines */ -+/*****************************************************************************/ -+ -+t_CcNodeInformation* FindNodeInfoInReleventLst(t_List *p_List, t_Handle h_Info, -+ t_Handle h_Spinlock) -+{ -+ t_CcNodeInformation *p_CcInformation; -+ t_List *p_Pos; -+ uint32_t intFlags; -+ -+ intFlags = XX_LockIntrSpinlock(h_Spinlock); -+ -+ for (p_Pos = LIST_FIRST(p_List); p_Pos != (p_List); -+ p_Pos = LIST_NEXT(p_Pos)) -+ { -+ p_CcInformation = CC_NODE_F_OBJECT(p_Pos); -+ -+ ASSERT_COND(p_CcInformation->h_CcNode); -+ -+ if (p_CcInformation->h_CcNode == h_Info) -+ { -+ XX_UnlockIntrSpinlock(h_Spinlock, intFlags); -+ return p_CcInformation; -+ } -+ } -+ -+ XX_UnlockIntrSpinlock(h_Spinlock, intFlags); -+ -+ return NULL; -+} -+ -+void EnqueueNodeInfoToRelevantLst(t_List *p_List, t_CcNodeInformation *p_CcInfo, -+ t_Handle h_Spinlock) -+{ -+ t_CcNodeInformation *p_CcInformation; -+ uint32_t intFlags = 0; -+ -+ p_CcInformation = (t_CcNodeInformation *)XX_Malloc( -+ sizeof(t_CcNodeInformation)); -+ -+ if (p_CcInformation) -+ { -+ memset(p_CcInformation, 0, sizeof(t_CcNodeInformation)); -+ memcpy(p_CcInformation, p_CcInfo, sizeof(t_CcNodeInformation)); -+ INIT_LIST(&p_CcInformation->node); -+ -+ if (h_Spinlock) -+ intFlags = XX_LockIntrSpinlock(h_Spinlock); -+ -+ LIST_AddToTail(&p_CcInformation->node, p_List); -+ -+ if (h_Spinlock) -+ XX_UnlockIntrSpinlock(h_Spinlock, intFlags); -+ } -+ else -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("CC Node Information")); -+} -+ -+void DequeueNodeInfoFromRelevantLst(t_List *p_List, t_Handle h_Info, -+ t_Handle h_Spinlock) -+{ -+ t_CcNodeInformation *p_CcInformation = NULL; -+ uint32_t intFlags = 0; -+ t_List *p_Pos; -+ -+ if (h_Spinlock) -+ intFlags = XX_LockIntrSpinlock(h_Spinlock); -+ -+ if (LIST_IsEmpty(p_List)) -+ { -+ XX_RestoreAllIntr(intFlags); -+ return; -+ } -+ -+ for (p_Pos = LIST_FIRST(p_List); p_Pos != (p_List); -+ p_Pos = LIST_NEXT(p_Pos)) -+ { -+ p_CcInformation = CC_NODE_F_OBJECT(p_Pos); -+ ASSERT_COND(p_CcInformation); -+ ASSERT_COND(p_CcInformation->h_CcNode); -+ if (p_CcInformation->h_CcNode == h_Info) -+ break; -+ } -+ -+ if (p_CcInformation) -+ { -+ LIST_DelAndInit(&p_CcInformation->node); -+ XX_Free(p_CcInformation); -+ } -+ -+ if (h_Spinlock) -+ XX_UnlockIntrSpinlock(h_Spinlock, intFlags); -+} -+ -+void NextStepAd(t_Handle h_Ad, t_FmPcdCcStatsParams *p_FmPcdCcStatsParams, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams, -+ t_FmPcd *p_FmPcd) -+{ -+ switch (p_FmPcdCcNextEngineParams->nextEngine) -+ { -+ case (e_FM_PCD_KG): -+ case (e_FM_PCD_PLCR): -+ case (e_FM_PCD_DONE): -+ /* if NIA is not CC, create a "result" type AD */ -+ FillAdOfTypeResult(h_Ad, p_FmPcdCcStatsParams, p_FmPcd, -+ p_FmPcdCcNextEngineParams); -+ break; -+#if (DPAA_VERSION >= 11) -+ case (e_FM_PCD_FR): -+ if (p_FmPcdCcNextEngineParams->params.frParams.h_FrmReplic) -+ { -+ FillAdOfTypeContLookup( -+ h_Ad, p_FmPcdCcStatsParams, p_FmPcd, -+ p_FmPcdCcNextEngineParams->params.ccParams.h_CcNode, -+ p_FmPcdCcNextEngineParams->h_Manip, -+ p_FmPcdCcNextEngineParams->params.frParams.h_FrmReplic); -+ FrmReplicGroupUpdateOwner( -+ p_FmPcdCcNextEngineParams->params.frParams.h_FrmReplic, -+ TRUE/* add */); -+ } -+ break; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ case (e_FM_PCD_CC): -+ /* if NIA is not CC, create a TD to continue the CC lookup */ -+ FillAdOfTypeContLookup( -+ h_Ad, p_FmPcdCcStatsParams, p_FmPcd, -+ p_FmPcdCcNextEngineParams->params.ccParams.h_CcNode, -+ p_FmPcdCcNextEngineParams->h_Manip, NULL); -+ -+ UpdateNodeOwner(p_FmPcdCcNextEngineParams->params.ccParams.h_CcNode, -+ TRUE); -+ break; -+ -+ default: -+ return; -+ } -+} -+ -+t_Error FmPcdCcTreeAddIPR(t_Handle h_FmPcd, t_Handle h_FmTree, -+ t_Handle h_NetEnv, t_Handle h_IpReassemblyManip, -+ bool createSchemes) -+{ -+ t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmTree; -+ t_FmPcdCcNextEngineParams nextEngineParams; -+ t_NetEnvParams netEnvParams; -+ t_Handle h_Ad; -+ bool isIpv6Present; -+ uint8_t ipv4GroupId, ipv6GroupId; -+ t_Error err; -+ -+ ASSERT_COND(p_FmPcdCcTree); -+ -+ /* this routine must be protected by the calling routine! */ -+ -+ memset(&nextEngineParams, 0, sizeof(t_FmPcdCcNextEngineParams)); -+ memset(&netEnvParams, 0, sizeof(t_NetEnvParams)); -+ -+ h_Ad = UINT_TO_PTR(p_FmPcdCcTree->ccTreeBaseAddr); -+ -+ isIpv6Present = FmPcdManipIpReassmIsIpv6Hdr(h_IpReassemblyManip); -+ -+ if (isIpv6Present -+ && (p_FmPcdCcTree->numOfEntries > (FM_PCD_MAX_NUM_OF_CC_GROUPS - 2))) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("need two free entries for IPR")); -+ -+ if (p_FmPcdCcTree->numOfEntries > (FM_PCD_MAX_NUM_OF_CC_GROUPS - 1)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("need two free entries for IPR")); -+ -+ nextEngineParams.nextEngine = e_FM_PCD_DONE; -+ nextEngineParams.h_Manip = h_IpReassemblyManip; -+ -+ /* Lock tree */ -+ err = CcRootTryLock(p_FmPcdCcTree); -+ if (err) -+ return ERROR_CODE(E_BUSY); -+ -+ if (p_FmPcdCcTree->h_IpReassemblyManip == h_IpReassemblyManip) -+ { -+ CcRootReleaseLock(p_FmPcdCcTree); -+ return E_OK; -+ } -+ -+ if ((p_FmPcdCcTree->h_IpReassemblyManip) -+ && (p_FmPcdCcTree->h_IpReassemblyManip != h_IpReassemblyManip)) -+ { -+ CcRootReleaseLock(p_FmPcdCcTree); -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("This tree was previously updated with different IPR")); -+ } -+ -+ /* Initialize IPR for the first time for this tree */ -+ if (isIpv6Present) -+ { -+ ipv6GroupId = p_FmPcdCcTree->numOfGrps++; -+ p_FmPcdCcTree->fmPcdGroupParam[ipv6GroupId].baseGroupEntry = -+ (FM_PCD_MAX_NUM_OF_CC_GROUPS - 2); -+ -+ if (createSchemes) -+ { -+ err = FmPcdManipBuildIpReassmScheme(h_FmPcd, h_NetEnv, -+ p_FmPcdCcTree, -+ h_IpReassemblyManip, FALSE, -+ ipv6GroupId); -+ if (err) -+ { -+ p_FmPcdCcTree->numOfGrps--; -+ CcRootReleaseLock(p_FmPcdCcTree); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ } -+ -+ NextStepAd( -+ PTR_MOVE(h_Ad, (FM_PCD_MAX_NUM_OF_CC_GROUPS-2) * FM_PCD_CC_AD_ENTRY_SIZE), -+ NULL, &nextEngineParams, h_FmPcd); -+ } -+ -+ ipv4GroupId = p_FmPcdCcTree->numOfGrps++; -+ p_FmPcdCcTree->fmPcdGroupParam[ipv4GroupId].totalBitsMask = 0; -+ p_FmPcdCcTree->fmPcdGroupParam[ipv4GroupId].baseGroupEntry = -+ (FM_PCD_MAX_NUM_OF_CC_GROUPS - 1); -+ -+ if (createSchemes) -+ { -+ err = FmPcdManipBuildIpReassmScheme(h_FmPcd, h_NetEnv, p_FmPcdCcTree, -+ h_IpReassemblyManip, TRUE, -+ ipv4GroupId); -+ if (err) -+ { -+ p_FmPcdCcTree->numOfGrps--; -+ if (isIpv6Present) -+ { -+ p_FmPcdCcTree->numOfGrps--; -+ FmPcdManipDeleteIpReassmSchemes(h_IpReassemblyManip); -+ } -+ CcRootReleaseLock(p_FmPcdCcTree); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ } -+ -+ NextStepAd( -+ PTR_MOVE(h_Ad, (FM_PCD_MAX_NUM_OF_CC_GROUPS-1) * FM_PCD_CC_AD_ENTRY_SIZE), -+ NULL, &nextEngineParams, h_FmPcd); -+ -+ p_FmPcdCcTree->h_IpReassemblyManip = h_IpReassemblyManip; -+ -+ CcRootReleaseLock(p_FmPcdCcTree); -+ -+ return E_OK; -+} -+ -+t_Error FmPcdCcTreeAddCPR(t_Handle h_FmPcd, t_Handle h_FmTree, -+ t_Handle h_NetEnv, t_Handle h_ReassemblyManip, -+ bool createSchemes) -+{ -+ t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmTree; -+ t_FmPcdCcNextEngineParams nextEngineParams; -+ t_NetEnvParams netEnvParams; -+ t_Handle h_Ad; -+ uint8_t groupId; -+ t_Error err; -+ -+ ASSERT_COND(p_FmPcdCcTree); -+ -+ /* this routine must be protected by the calling routine! */ -+ memset(&nextEngineParams, 0, sizeof(t_FmPcdCcNextEngineParams)); -+ memset(&netEnvParams, 0, sizeof(t_NetEnvParams)); -+ -+ h_Ad = UINT_TO_PTR(p_FmPcdCcTree->ccTreeBaseAddr); -+ -+ if (p_FmPcdCcTree->numOfEntries > (FM_PCD_MAX_NUM_OF_CC_GROUPS - 1)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("need one free entries for CPR")); -+ -+ nextEngineParams.nextEngine = e_FM_PCD_DONE; -+ nextEngineParams.h_Manip = h_ReassemblyManip; -+ -+ /* Lock tree */ -+ err = CcRootTryLock(p_FmPcdCcTree); -+ if (err) -+ return ERROR_CODE(E_BUSY); -+ -+ if (p_FmPcdCcTree->h_CapwapReassemblyManip == h_ReassemblyManip) -+ { -+ CcRootReleaseLock(p_FmPcdCcTree); -+ return E_OK; -+ } -+ -+ if ((p_FmPcdCcTree->h_CapwapReassemblyManip) -+ && (p_FmPcdCcTree->h_CapwapReassemblyManip != h_ReassemblyManip)) -+ { -+ CcRootReleaseLock(p_FmPcdCcTree); -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("This tree was previously updated with different CPR")); -+ } -+ -+ groupId = p_FmPcdCcTree->numOfGrps++; -+ p_FmPcdCcTree->fmPcdGroupParam[groupId].baseGroupEntry = -+ (FM_PCD_MAX_NUM_OF_CC_GROUPS - 1); -+ -+ if (createSchemes) -+ { -+ err = FmPcdManipBuildCapwapReassmScheme(h_FmPcd, h_NetEnv, -+ p_FmPcdCcTree, -+ h_ReassemblyManip, groupId); -+ if (err) -+ { -+ p_FmPcdCcTree->numOfGrps--; -+ CcRootReleaseLock(p_FmPcdCcTree); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ } -+ -+ NextStepAd( -+ PTR_MOVE(h_Ad, (FM_PCD_MAX_NUM_OF_CC_GROUPS-1) * FM_PCD_CC_AD_ENTRY_SIZE), -+ NULL, &nextEngineParams, h_FmPcd); -+ -+ p_FmPcdCcTree->h_CapwapReassemblyManip = h_ReassemblyManip; -+ -+ CcRootReleaseLock(p_FmPcdCcTree); -+ -+ return E_OK; -+} -+ -+t_Handle FmPcdCcTreeGetSavedManipParams(t_Handle h_FmTree) -+{ -+ t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmTree; -+ -+ ASSERT_COND(p_FmPcdCcTree); -+ -+ return p_FmPcdCcTree->h_FmPcdCcSavedManipParams; -+} -+ -+void FmPcdCcTreeSetSavedManipParams(t_Handle h_FmTree, -+ t_Handle h_SavedManipParams) -+{ -+ t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmTree; -+ -+ ASSERT_COND(p_FmPcdCcTree); -+ -+ p_FmPcdCcTree->h_FmPcdCcSavedManipParams = h_SavedManipParams; -+} -+ -+uint8_t FmPcdCcGetParseCode(t_Handle h_CcNode) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ -+ ASSERT_COND(p_CcNode); -+ -+ return p_CcNode->parseCode; -+} -+ -+uint8_t FmPcdCcGetOffset(t_Handle h_CcNode) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ -+ ASSERT_COND(p_CcNode); -+ -+ return p_CcNode->offset; -+} -+ -+uint16_t FmPcdCcGetNumOfKeys(t_Handle h_CcNode) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ -+ ASSERT_COND(p_CcNode); -+ -+ return p_CcNode->numOfKeys; -+} -+ -+t_Error FmPcdCcModifyNextEngineParamTree( -+ t_Handle h_FmPcd, t_Handle h_FmPcdCcTree, uint8_t grpId, uint8_t index, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams) -+{ -+ t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcTree; -+ t_FmPcd *p_FmPcd; -+ t_List h_OldPointersLst, h_NewPointersLst; -+ uint16_t keyIndex; -+ t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(h_FmPcdCcTree, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((grpId <= 7), E_INVALID_VALUE); -+ -+ if (grpId >= p_FmPcdCcTree->numOfGrps) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, -+ ("grpId you asked > numOfGroup of relevant tree")); -+ -+ if (index >= p_FmPcdCcTree->fmPcdGroupParam[grpId].numOfEntriesInGroup) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("index > numOfEntriesInGroup")); -+ -+ p_FmPcd = (t_FmPcd *)h_FmPcd; -+ -+ INIT_LIST(&h_OldPointersLst); -+ INIT_LIST(&h_NewPointersLst); -+ -+ keyIndex = (uint16_t)(p_FmPcdCcTree->fmPcdGroupParam[grpId].baseGroupEntry -+ + index); -+ -+ p_ModifyKeyParams = ModifyNodeCommonPart(p_FmPcdCcTree, keyIndex, -+ e_MODIFY_STATE_CHANGE, FALSE, -+ FALSE, TRUE); -+ if (!p_ModifyKeyParams) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ -+ p_ModifyKeyParams->tree = TRUE; -+ -+ if (p_FmPcd->p_CcShadow -+ && !TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock)) -+ { -+ XX_Free(p_ModifyKeyParams); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = BuildNewNodeModifyNextEngine(p_FmPcd, p_FmPcdCcTree, keyIndex, -+ p_FmPcdCcNextEngineParams, -+ &h_OldPointersLst, &h_NewPointersLst, -+ p_ModifyKeyParams); -+ if (err) -+ { -+ XX_Free(p_ModifyKeyParams); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst, -+ p_ModifyKeyParams, FALSE); -+ -+ if (p_FmPcd->p_CcShadow) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ -+ return err; -+ -+} -+ -+t_Error FmPcdCcRemoveKey(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode, -+ uint16_t keyIndex) -+{ -+ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode; -+ t_FmPcd *p_FmPcd; -+ t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams; -+ t_List h_OldPointersLst, h_NewPointersLst; -+ bool useShadowStructs = FALSE; -+ t_Error err = E_OK; -+ -+ if (keyIndex >= p_CcNode->numOfKeys) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("impossible to remove key when numOfKeys <= keyIndex")); -+ -+ if (p_CcNode->h_FmPcd != h_FmPcd) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("handler to FmPcd is different from the handle provided at node initialization time")); -+ -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ -+ INIT_LIST(&h_OldPointersLst); -+ INIT_LIST(&h_NewPointersLst); -+ -+ p_ModifyKeyParams = ModifyNodeCommonPart(p_CcNode, keyIndex, -+ e_MODIFY_STATE_REMOVE, TRUE, TRUE, -+ FALSE); -+ if (!p_ModifyKeyParams) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ -+ if (p_CcNode->maxNumOfKeys) -+ { -+ if (!TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock)) -+ { -+ XX_Free(p_ModifyKeyParams); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ useShadowStructs = TRUE; -+ } -+ -+ err = BuildNewNodeRemoveKey(p_CcNode, keyIndex, p_ModifyKeyParams); -+ if (err) -+ { -+ XX_Free(p_ModifyKeyParams); -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ err = UpdatePtrWhichPointOnCrntMdfNode(p_CcNode, p_ModifyKeyParams, -+ &h_OldPointersLst, -+ &h_NewPointersLst); -+ if (err) -+ { -+ ReleaseNewNodeCommonPart(p_ModifyKeyParams); -+ XX_Free(p_ModifyKeyParams); -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst, -+ p_ModifyKeyParams, useShadowStructs); -+ -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ -+ return err; -+} -+ -+t_Error FmPcdCcModifyKey(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode, -+ uint16_t keyIndex, uint8_t keySize, uint8_t *p_Key, -+ uint8_t *p_Mask) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode; -+ t_FmPcd *p_FmPcd; -+ t_List h_OldPointersLst, h_NewPointersLst; -+ t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams; -+ uint16_t tmpKeyIndex; -+ bool useShadowStructs = FALSE; -+ t_Error err = E_OK; -+ -+ if (keyIndex >= p_CcNode->numOfKeys) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("keyIndex > previously cleared last index + 1")); -+ -+ if (keySize != p_CcNode->userSizeOfExtraction) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("size for ModifyKey has to be the same as defined in SetNode")); -+ -+ if (p_CcNode->h_FmPcd != h_FmPcd) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("handler to FmPcd is different from the handle provided at node initialization time")); -+ -+ err = FindKeyIndex(h_FmPcdCcNode, keySize, p_Key, p_Mask, &tmpKeyIndex); -+ if (GET_ERROR_TYPE(err) != E_NOT_FOUND) -+ RETURN_ERROR( -+ MINOR, -+ E_ALREADY_EXISTS, -+ ("The received key and mask pair was already found in the match table of the provided node")); -+ -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ -+ INIT_LIST(&h_OldPointersLst); -+ INIT_LIST(&h_NewPointersLst); -+ -+ p_ModifyKeyParams = ModifyNodeCommonPart(p_CcNode, keyIndex, -+ e_MODIFY_STATE_CHANGE, TRUE, TRUE, -+ FALSE); -+ if (!p_ModifyKeyParams) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ -+ if (p_CcNode->maxNumOfKeys) -+ { -+ if (!TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock)) -+ { -+ XX_Free(p_ModifyKeyParams); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ useShadowStructs = TRUE; -+ } -+ -+ err = BuildNewNodeModifyKey(p_CcNode, keyIndex, p_Key, p_Mask, -+ p_ModifyKeyParams); -+ if (err) -+ { -+ XX_Free(p_ModifyKeyParams); -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ err = UpdatePtrWhichPointOnCrntMdfNode(p_CcNode, p_ModifyKeyParams, -+ &h_OldPointersLst, -+ &h_NewPointersLst); -+ if (err) -+ { -+ ReleaseNewNodeCommonPart(p_ModifyKeyParams); -+ XX_Free(p_ModifyKeyParams); -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst, -+ p_ModifyKeyParams, useShadowStructs); -+ -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ -+ return err; -+} -+ -+t_Error FmPcdCcModifyMissNextEngineParamNode( -+ t_Handle h_FmPcd, t_Handle h_FmPcdCcNode, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode; -+ t_FmPcd *p_FmPcd; -+ t_List h_OldPointersLst, h_NewPointersLst; -+ uint16_t keyIndex; -+ t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_VALUE); -+ -+ keyIndex = p_CcNode->numOfKeys; -+ -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ -+ INIT_LIST(&h_OldPointersLst); -+ INIT_LIST(&h_NewPointersLst); -+ -+ p_ModifyKeyParams = ModifyNodeCommonPart(p_CcNode, keyIndex, -+ e_MODIFY_STATE_CHANGE, FALSE, TRUE, -+ FALSE); -+ if (!p_ModifyKeyParams) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ -+ if (p_CcNode->maxNumOfKeys -+ && !TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock)) -+ { -+ XX_Free(p_ModifyKeyParams); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = BuildNewNodeModifyNextEngine(h_FmPcd, p_CcNode, keyIndex, -+ p_FmPcdCcNextEngineParams, -+ &h_OldPointersLst, &h_NewPointersLst, -+ p_ModifyKeyParams); -+ if (err) -+ { -+ XX_Free(p_ModifyKeyParams); -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst, -+ p_ModifyKeyParams, FALSE); -+ -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ -+ return err; -+} -+ -+t_Error FmPcdCcAddKey(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode, -+ uint16_t keyIndex, uint8_t keySize, -+ t_FmPcdCcKeyParams *p_FmPcdCcKeyParams) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode; -+ t_FmPcd *p_FmPcd; -+ t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams; -+ t_List h_OldPointersLst, h_NewPointersLst; -+ bool useShadowStructs = FALSE; -+ uint16_t tmpKeyIndex; -+ t_Error err = E_OK; -+ -+ if (keyIndex > p_CcNode->numOfKeys) -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, -+ ("keyIndex > previously cleared last index + 1")); -+ -+ if (keySize != p_CcNode->userSizeOfExtraction) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("keySize has to be defined as it was defined in initialization step")); -+ -+ if (p_CcNode->h_FmPcd != h_FmPcd) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("handler to FmPcd is different from the handle provided at node initialization time")); -+ -+ if (p_CcNode->maxNumOfKeys) -+ { -+ if (p_CcNode->numOfKeys == p_CcNode->maxNumOfKeys) -+ RETURN_ERROR( -+ MAJOR, -+ E_FULL, -+ ("number of keys exceeds the maximal number of keys provided at node initialization time")); -+ } -+ else -+ if (p_CcNode->numOfKeys == FM_PCD_MAX_NUM_OF_KEYS) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("number of keys can not be larger than %d", FM_PCD_MAX_NUM_OF_KEYS)); -+ -+ err = FindKeyIndex(h_FmPcdCcNode, keySize, p_FmPcdCcKeyParams->p_Key, -+ p_FmPcdCcKeyParams->p_Mask, &tmpKeyIndex); -+ if (GET_ERROR_TYPE(err) != E_NOT_FOUND) -+ RETURN_ERROR( -+ MAJOR, -+ E_ALREADY_EXISTS, -+ ("The received key and mask pair was already found in the match table of the provided node")); -+ -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ -+ INIT_LIST(&h_OldPointersLst); -+ INIT_LIST(&h_NewPointersLst); -+ -+ p_ModifyKeyParams = ModifyNodeCommonPart(p_CcNode, keyIndex, -+ e_MODIFY_STATE_ADD, TRUE, TRUE, -+ FALSE); -+ if (!p_ModifyKeyParams) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ -+ if (p_CcNode->maxNumOfKeys) -+ { -+ if (!TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock)) -+ { -+ XX_Free(p_ModifyKeyParams); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ useShadowStructs = TRUE; -+ } -+ -+ err = BuildNewNodeAddOrMdfyKeyAndNextEngine(h_FmPcd, p_CcNode, keyIndex, -+ p_FmPcdCcKeyParams, -+ p_ModifyKeyParams, TRUE); -+ if (err) -+ { -+ ReleaseNewNodeCommonPart(p_ModifyKeyParams); -+ XX_Free(p_ModifyKeyParams); -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ err = UpdatePtrWhichPointOnCrntMdfNode(p_CcNode, p_ModifyKeyParams, -+ &h_OldPointersLst, -+ &h_NewPointersLst); -+ if (err) -+ { -+ ReleaseNewNodeCommonPart(p_ModifyKeyParams); -+ XX_Free(p_ModifyKeyParams); -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst, -+ p_ModifyKeyParams, useShadowStructs); -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ -+ return err; -+} -+ -+t_Error FmPcdCcModifyKeyAndNextEngine(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode, -+ uint16_t keyIndex, uint8_t keySize, -+ t_FmPcdCcKeyParams *p_FmPcdCcKeyParams) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode; -+ t_FmPcd *p_FmPcd; -+ t_List h_OldPointersLst, h_NewPointersLst; -+ t_FmPcdModifyCcKeyAdditionalParams *p_ModifyKeyParams; -+ uint16_t tmpKeyIndex; -+ bool useShadowStructs = FALSE; -+ t_Error err = E_OK; -+ -+ if (keyIndex > p_CcNode->numOfKeys) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("keyIndex > previously cleared last index + 1")); -+ -+ if (keySize != p_CcNode->userSizeOfExtraction) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("keySize has to be defined as it was defined in initialization step")); -+ -+ if (p_CcNode->h_FmPcd != h_FmPcd) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("handler to FmPcd is different from the handle provided at node initialization time")); -+ -+ err = FindKeyIndex(h_FmPcdCcNode, keySize, p_FmPcdCcKeyParams->p_Key, -+ p_FmPcdCcKeyParams->p_Mask, &tmpKeyIndex); -+ if (GET_ERROR_TYPE(err) != E_NOT_FOUND) -+ RETURN_ERROR( -+ MINOR, -+ E_ALREADY_EXISTS, -+ ("The received key and mask pair was already found in the match table of the provided node")); -+ -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ -+ INIT_LIST(&h_OldPointersLst); -+ INIT_LIST(&h_NewPointersLst); -+ -+ p_ModifyKeyParams = ModifyNodeCommonPart(p_CcNode, keyIndex, -+ e_MODIFY_STATE_CHANGE, TRUE, TRUE, -+ FALSE); -+ if (!p_ModifyKeyParams) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ -+ if (p_CcNode->maxNumOfKeys) -+ { -+ if (!TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock)) -+ { -+ XX_Free(p_ModifyKeyParams); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ useShadowStructs = TRUE; -+ } -+ -+ err = BuildNewNodeAddOrMdfyKeyAndNextEngine(h_FmPcd, p_CcNode, keyIndex, -+ p_FmPcdCcKeyParams, -+ p_ModifyKeyParams, FALSE); -+ if (err) -+ { -+ ReleaseNewNodeCommonPart(p_ModifyKeyParams); -+ XX_Free(p_ModifyKeyParams); -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ err = UpdatePtrWhichPointOnCrntMdfNode(p_CcNode, p_ModifyKeyParams, -+ &h_OldPointersLst, -+ &h_NewPointersLst); -+ if (err) -+ { -+ ReleaseNewNodeCommonPart(p_ModifyKeyParams); -+ XX_Free(p_ModifyKeyParams); -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ err = DoDynamicChange(p_FmPcd, &h_OldPointersLst, &h_NewPointersLst, -+ p_ModifyKeyParams, useShadowStructs); -+ -+ if (p_CcNode->maxNumOfKeys) -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ -+ return err; -+} -+ -+uint32_t FmPcdCcGetNodeAddrOffsetFromNodeInfo(t_Handle h_FmPcd, -+ t_Handle h_Pointer) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ t_CcNodeInformation *p_CcNodeInfo; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_HANDLE, -+ (uint32_t)ILLEGAL_BASE); -+ -+ p_CcNodeInfo = CC_NODE_F_OBJECT(h_Pointer); -+ -+ return (uint32_t)(XX_VirtToPhys(p_CcNodeInfo->h_CcNode) -+ - p_FmPcd->physicalMuramBase); -+} -+ -+t_Error FmPcdCcGetGrpParams(t_Handle h_FmPcdCcTree, uint8_t grpId, -+ uint32_t *p_GrpBits, uint8_t *p_GrpBase) -+{ -+ t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcTree; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPcdCcTree, E_INVALID_HANDLE); -+ -+ if (grpId >= p_FmPcdCcTree->numOfGrps) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, -+ ("grpId you asked > numOfGroup of relevant tree")); -+ -+ *p_GrpBits = p_FmPcdCcTree->fmPcdGroupParam[grpId].totalBitsMask; -+ *p_GrpBase = p_FmPcdCcTree->fmPcdGroupParam[grpId].baseGroupEntry; -+ -+ return E_OK; -+} -+ -+t_Error FmPcdCcBindTree(t_Handle h_FmPcd, t_Handle h_PcdParams, -+ t_Handle h_FmPcdCcTree, uint32_t *p_Offset, -+ t_Handle h_FmPort) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcTree; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(h_FmPcdCcTree, E_INVALID_HANDLE); -+ -+ /* this routine must be protected by the calling routine by locking all PCD modules! */ -+ -+ err = CcUpdateParams(h_FmPcd, h_PcdParams, h_FmPort, h_FmPcdCcTree, TRUE); -+ -+ if (err == E_OK) -+ UpdateCcRootOwner(p_FmPcdCcTree, TRUE); -+ -+ *p_Offset = (uint32_t)(XX_VirtToPhys( -+ UINT_TO_PTR(p_FmPcdCcTree->ccTreeBaseAddr)) -+ - p_FmPcd->physicalMuramBase); -+ -+ return err; -+} -+ -+t_Error FmPcdCcUnbindTree(t_Handle h_FmPcd, t_Handle h_FmPcdCcTree) -+{ -+ t_FmPcdCcTree *p_FmPcdCcTree = (t_FmPcdCcTree *)h_FmPcdCcTree; -+ -+ /* this routine must be protected by the calling routine by locking all PCD modules! */ -+ -+ UNUSED(h_FmPcd); -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPcdCcTree, E_INVALID_HANDLE); -+ -+ UpdateCcRootOwner(p_FmPcdCcTree, FALSE); -+ -+ return E_OK; -+} -+ -+t_Error FmPcdCcNodeTreeTryLock(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode, -+ t_List *p_List) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_FmPcdCcNode; -+ t_List *p_Pos, *p_Tmp; -+ t_CcNodeInformation *p_CcNodeInfo, nodeInfo; -+ uint32_t intFlags; -+ t_Error err = E_OK; -+ -+ intFlags = FmPcdLock(h_FmPcd); -+ -+ LIST_FOR_EACH(p_Pos, &p_CcNode->ccTreesLst) -+ { -+ p_CcNodeInfo = CC_NODE_F_OBJECT(p_Pos); -+ ASSERT_COND(p_CcNodeInfo->h_CcNode); -+ -+ err = CcRootTryLock(p_CcNodeInfo->h_CcNode); -+ -+ if (err) -+ { -+ LIST_FOR_EACH(p_Tmp, &p_CcNode->ccTreesLst) -+ { -+ if (p_Tmp == p_Pos) -+ break; -+ -+ CcRootReleaseLock(p_CcNodeInfo->h_CcNode); -+ } -+ break; -+ } -+ -+ memset(&nodeInfo, 0, sizeof(t_CcNodeInformation)); -+ nodeInfo.h_CcNode = p_CcNodeInfo->h_CcNode; -+ EnqueueNodeInfoToRelevantLst(p_List, &nodeInfo, NULL); -+ } -+ -+ FmPcdUnlock(h_FmPcd, intFlags); -+ CORE_MemoryBarrier(); -+ -+ return err; -+} -+ -+void FmPcdCcNodeTreeReleaseLock(t_Handle h_FmPcd, t_List *p_List) -+{ -+ t_List *p_Pos; -+ t_CcNodeInformation *p_CcNodeInfo; -+ t_Handle h_FmPcdCcTree; -+ uint32_t intFlags; -+ -+ intFlags = FmPcdLock(h_FmPcd); -+ -+ LIST_FOR_EACH(p_Pos, p_List) -+ { -+ p_CcNodeInfo = CC_NODE_F_OBJECT(p_Pos); -+ h_FmPcdCcTree = p_CcNodeInfo->h_CcNode; -+ CcRootReleaseLock(h_FmPcdCcTree); -+ } -+ -+ ReleaseLst(p_List); -+ -+ FmPcdUnlock(h_FmPcd, intFlags); -+ CORE_MemoryBarrier(); -+} -+ -+t_Error FmPcdUpdateCcShadow(t_FmPcd *p_FmPcd, uint32_t size, uint32_t align) -+{ -+ uint32_t intFlags; -+ uint32_t newSize = 0, newAlign = 0; -+ bool allocFail = FALSE; -+ -+ ASSERT_COND(p_FmPcd); -+ -+ if (!size) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("size must be larger then 0")); -+ -+ if (!POWER_OF_2(align)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("alignment must be power of 2")); -+ -+ newSize = p_FmPcd->ccShadowSize; -+ newAlign = p_FmPcd->ccShadowAlign; -+ -+ /* Check if current shadow is large enough to hold the requested size */ -+ if (size > p_FmPcd->ccShadowSize) -+ newSize = size; -+ -+ /* Check if current shadow matches the requested alignment */ -+ if (align > p_FmPcd->ccShadowAlign) -+ newAlign = align; -+ -+ /* If a bigger shadow size or bigger shadow alignment are required, -+ a new shadow will be allocated */ -+ if ((newSize != p_FmPcd->ccShadowSize) -+ || (newAlign != p_FmPcd->ccShadowAlign)) -+ { -+ intFlags = FmPcdLock(p_FmPcd); -+ -+ if (p_FmPcd->p_CcShadow) -+ { -+ FM_MURAM_FreeMem(FmPcdGetMuramHandle(p_FmPcd), p_FmPcd->p_CcShadow); -+ p_FmPcd->ccShadowSize = 0; -+ p_FmPcd->ccShadowAlign = 0; -+ } -+ -+ p_FmPcd->p_CcShadow = FM_MURAM_AllocMem(FmPcdGetMuramHandle(p_FmPcd), -+ newSize, newAlign); -+ if (!p_FmPcd->p_CcShadow) -+ { -+ allocFail = TRUE; -+ -+ /* If new shadow size allocation failed, -+ re-allocate with previous parameters */ -+ p_FmPcd->p_CcShadow = FM_MURAM_AllocMem( -+ FmPcdGetMuramHandle(p_FmPcd), p_FmPcd->ccShadowSize, -+ p_FmPcd->ccShadowAlign); -+ } -+ -+ FmPcdUnlock(p_FmPcd, intFlags); -+ -+ if (allocFail) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM allocation for CC Shadow memory")); -+ -+ p_FmPcd->ccShadowSize = newSize; -+ p_FmPcd->ccShadowAlign = newAlign; -+ } -+ -+ return E_OK; -+} -+ -+#if (DPAA_VERSION >= 11) -+void FmPcdCcGetAdTablesThatPointOnReplicGroup(t_Handle h_Node, -+ t_Handle h_ReplicGroup, -+ t_List *p_AdTables, -+ uint32_t *p_NumOfAdTables) -+{ -+ t_FmPcdCcNode *p_CurrentNode = (t_FmPcdCcNode *)h_Node; -+ int i = 0; -+ void * p_AdTable; -+ t_CcNodeInformation ccNodeInfo; -+ -+ ASSERT_COND(h_Node); -+ *p_NumOfAdTables = 0; -+ -+ /* search in the current node which exact index points on this current replicator group for getting AD */ -+ for (i = 0; i < p_CurrentNode->numOfKeys + 1; i++) -+ { -+ if ((p_CurrentNode->keyAndNextEngineParams[i].nextEngineParams.nextEngine -+ == e_FM_PCD_FR) -+ && ((p_CurrentNode->keyAndNextEngineParams[i].nextEngineParams.params.frParams.h_FrmReplic -+ == (t_Handle)h_ReplicGroup))) -+ { -+ /* save the current ad table in the list */ -+ /* this entry uses the input replicator group */ -+ p_AdTable = -+ PTR_MOVE(p_CurrentNode->h_AdTable, i*FM_PCD_CC_AD_ENTRY_SIZE); -+ memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation)); -+ ccNodeInfo.h_CcNode = p_AdTable; -+ EnqueueNodeInfoToRelevantLst(p_AdTables, &ccNodeInfo, NULL); -+ (*p_NumOfAdTables)++; -+ } -+ } -+ -+ ASSERT_COND(i != p_CurrentNode->numOfKeys); -+} -+#endif /* (DPAA_VERSION >= 11) */ -+/*********************** End of inter-module routines ************************/ -+ -+/****************************************/ -+/* API Init unit functions */ -+/****************************************/ -+ -+t_Handle FM_PCD_CcRootBuild(t_Handle h_FmPcd, -+ t_FmPcdCcTreeParams *p_PcdGroupsParam) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ t_Error err = E_OK; -+ int i = 0, j = 0, k = 0; -+ t_FmPcdCcTree *p_FmPcdCcTree; -+ uint8_t numOfEntries; -+ t_Handle p_CcTreeTmp; -+ t_FmPcdCcGrpParams *p_FmPcdCcGroupParams; -+ t_FmPcdCcKeyAndNextEngineParams *p_Params, *p_KeyAndNextEngineParams; -+ t_NetEnvParams netEnvParams; -+ uint8_t lastOne = 0; -+ uint32_t requiredAction = 0; -+ t_FmPcdCcNode *p_FmPcdCcNextNode; -+ t_CcNodeInformation ccNodeInfo, *p_CcInformation; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(p_PcdGroupsParam, E_INVALID_HANDLE, NULL); -+ -+ if (p_PcdGroupsParam->numOfGrps > FM_PCD_MAX_NUM_OF_CC_GROUPS) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("numOfGrps should not exceed %d", FM_PCD_MAX_NUM_OF_CC_GROUPS)); -+ return NULL; -+ } -+ -+ p_FmPcdCcTree = (t_FmPcdCcTree*)XX_Malloc(sizeof(t_FmPcdCcTree)); -+ if (!p_FmPcdCcTree) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("PCD tree structure")); -+ return NULL; -+ } -+ memset(p_FmPcdCcTree, 0, sizeof(t_FmPcdCcTree)); -+ p_FmPcdCcTree->h_FmPcd = h_FmPcd; -+ -+ p_Params = (t_FmPcdCcKeyAndNextEngineParams*)XX_Malloc( -+ FM_PCD_MAX_NUM_OF_CC_GROUPS -+ * sizeof(t_FmPcdCcKeyAndNextEngineParams)); -+ memset(p_Params, -+ 0, -+ FM_PCD_MAX_NUM_OF_CC_GROUPS -+ * sizeof(t_FmPcdCcKeyAndNextEngineParams)); -+ -+ INIT_LIST(&p_FmPcdCcTree->fmPortsLst); -+ -+#ifdef FM_CAPWAP_SUPPORT -+ if ((p_PcdGroupsParam->numOfGrps == 1) && -+ (p_PcdGroupsParam->ccGrpParams[0].numOfDistinctionUnits == 0) && -+ (p_PcdGroupsParam->ccGrpParams[0].nextEnginePerEntriesInGrp[0].nextEngine == e_FM_PCD_CC) && -+ p_PcdGroupsParam->ccGrpParams[0].nextEnginePerEntriesInGrp[0].params.ccParams.h_CcNode && -+ IsCapwapApplSpecific(p_PcdGroupsParam->ccGrpParams[0].nextEnginePerEntriesInGrp[0].params.ccParams.h_CcNode)) -+ { -+ p_PcdGroupsParam->ccGrpParams[0].nextEnginePerEntriesInGrp[0].h_Manip = FmPcdManipApplSpecificBuild(); -+ if (!p_PcdGroupsParam->ccGrpParams[0].nextEnginePerEntriesInGrp[0].h_Manip) -+ { -+ DeleteTree(p_FmPcdCcTree,p_FmPcd); -+ XX_Free(p_Params); -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ return NULL; -+ } -+ } -+#endif /* FM_CAPWAP_SUPPORT */ -+ -+ numOfEntries = 0; -+ p_FmPcdCcTree->netEnvId = FmPcdGetNetEnvId(p_PcdGroupsParam->h_NetEnv); -+ -+ for (i = 0; i < p_PcdGroupsParam->numOfGrps; i++) -+ { -+ p_FmPcdCcGroupParams = &p_PcdGroupsParam->ccGrpParams[i]; -+ -+ if (p_FmPcdCcGroupParams->numOfDistinctionUnits -+ > FM_PCD_MAX_NUM_OF_CC_UNITS) -+ { -+ DeleteTree(p_FmPcdCcTree, p_FmPcd); -+ XX_Free(p_Params); -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("numOfDistinctionUnits (group %d) should not exceed %d", i, FM_PCD_MAX_NUM_OF_CC_UNITS)); -+ return NULL; -+ } -+ -+ p_FmPcdCcTree->fmPcdGroupParam[i].baseGroupEntry = numOfEntries; -+ p_FmPcdCcTree->fmPcdGroupParam[i].numOfEntriesInGroup = (uint8_t)(0x01 -+ << p_FmPcdCcGroupParams->numOfDistinctionUnits); -+ numOfEntries += p_FmPcdCcTree->fmPcdGroupParam[i].numOfEntriesInGroup; -+ if (numOfEntries > FM_PCD_MAX_NUM_OF_CC_GROUPS) -+ { -+ DeleteTree(p_FmPcdCcTree, p_FmPcd); -+ XX_Free(p_Params); -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("numOfEntries can not be larger than %d", FM_PCD_MAX_NUM_OF_CC_GROUPS)); -+ return NULL; -+ } -+ -+ if (lastOne) -+ { -+ if (p_FmPcdCcTree->fmPcdGroupParam[i].numOfEntriesInGroup > lastOne) -+ { -+ DeleteTree(p_FmPcdCcTree, p_FmPcd); -+ XX_Free(p_Params); -+ REPORT_ERROR(MAJOR, E_CONFLICT, ("numOfEntries per group must be set in descending order")); -+ return NULL; -+ } -+ } -+ -+ lastOne = p_FmPcdCcTree->fmPcdGroupParam[i].numOfEntriesInGroup; -+ -+ netEnvParams.netEnvId = p_FmPcdCcTree->netEnvId; -+ netEnvParams.numOfDistinctionUnits = -+ p_FmPcdCcGroupParams->numOfDistinctionUnits; -+ -+ memcpy(netEnvParams.unitIds, &p_FmPcdCcGroupParams->unitIds, -+ (sizeof(uint8_t)) * p_FmPcdCcGroupParams->numOfDistinctionUnits); -+ -+ err = PcdGetUnitsVector(p_FmPcd, &netEnvParams); -+ if (err) -+ { -+ DeleteTree(p_FmPcdCcTree, p_FmPcd); -+ XX_Free(p_Params); -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ return NULL; -+ } -+ -+ p_FmPcdCcTree->fmPcdGroupParam[i].totalBitsMask = netEnvParams.vector; -+ for (j = 0; j < p_FmPcdCcTree->fmPcdGroupParam[i].numOfEntriesInGroup; -+ j++) -+ { -+ err = ValidateNextEngineParams( -+ h_FmPcd, -+ &p_FmPcdCcGroupParams->nextEnginePerEntriesInGrp[j], -+ e_FM_PCD_CC_STATS_MODE_NONE); -+ if (err) -+ { -+ DeleteTree(p_FmPcdCcTree, p_FmPcd); -+ XX_Free(p_Params); -+ REPORT_ERROR(MAJOR, err, (NO_MSG)); -+ return NULL; -+ } -+ -+ if (p_FmPcdCcGroupParams->nextEnginePerEntriesInGrp[j].h_Manip) -+ { -+ err = FmPcdManipCheckParamsForCcNextEngine( -+ &p_FmPcdCcGroupParams->nextEnginePerEntriesInGrp[j], -+ &requiredAction); -+ if (err) -+ { -+ DeleteTree(p_FmPcdCcTree, p_FmPcd); -+ XX_Free(p_Params); -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ return NULL; -+ } -+ } -+ p_KeyAndNextEngineParams = p_Params + k; -+ -+ memcpy(&p_KeyAndNextEngineParams->nextEngineParams, -+ &p_FmPcdCcGroupParams->nextEnginePerEntriesInGrp[j], -+ sizeof(t_FmPcdCcNextEngineParams)); -+ -+ if ((p_KeyAndNextEngineParams->nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ && p_KeyAndNextEngineParams->nextEngineParams.h_Manip) -+ { -+ err = -+ AllocAndFillAdForContLookupManip( -+ p_KeyAndNextEngineParams->nextEngineParams.params.ccParams.h_CcNode); -+ if (err) -+ { -+ DeleteTree(p_FmPcdCcTree, p_FmPcd); -+ XX_Free(p_Params); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("MURAM allocation for CC Tree")); -+ return NULL; -+ } -+ } -+ -+ requiredAction |= UPDATE_CC_WITH_TREE; -+ p_KeyAndNextEngineParams->requiredAction = requiredAction; -+ -+ k++; -+ } -+ } -+ -+ p_FmPcdCcTree->numOfEntries = (uint8_t)k; -+ p_FmPcdCcTree->numOfGrps = p_PcdGroupsParam->numOfGrps; -+ -+ p_FmPcdCcTree->ccTreeBaseAddr = -+ PTR_TO_UINT(FM_MURAM_AllocMem(FmPcdGetMuramHandle(h_FmPcd), -+ (uint32_t)( FM_PCD_MAX_NUM_OF_CC_GROUPS * FM_PCD_CC_AD_ENTRY_SIZE), -+ FM_PCD_CC_TREE_ADDR_ALIGN)); -+ if (!p_FmPcdCcTree->ccTreeBaseAddr) -+ { -+ DeleteTree(p_FmPcdCcTree, p_FmPcd); -+ XX_Free(p_Params); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("MURAM allocation for CC Tree")); -+ return NULL; -+ } -+ MemSet8( -+ UINT_TO_PTR(p_FmPcdCcTree->ccTreeBaseAddr), 0, -+ (uint32_t)(FM_PCD_MAX_NUM_OF_CC_GROUPS * FM_PCD_CC_AD_ENTRY_SIZE)); -+ -+ p_CcTreeTmp = UINT_TO_PTR(p_FmPcdCcTree->ccTreeBaseAddr); -+ -+ for (i = 0; i < numOfEntries; i++) -+ { -+ p_KeyAndNextEngineParams = p_Params + i; -+ -+ NextStepAd(p_CcTreeTmp, NULL, -+ &p_KeyAndNextEngineParams->nextEngineParams, p_FmPcd); -+ -+ p_CcTreeTmp = PTR_MOVE(p_CcTreeTmp, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ memcpy(&p_FmPcdCcTree->keyAndNextEngineParams[i], -+ p_KeyAndNextEngineParams, -+ sizeof(t_FmPcdCcKeyAndNextEngineParams)); -+ -+ if (p_FmPcdCcTree->keyAndNextEngineParams[i].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ { -+ p_FmPcdCcNextNode = -+ (t_FmPcdCcNode*)p_FmPcdCcTree->keyAndNextEngineParams[i].nextEngineParams.params.ccParams.h_CcNode; -+ p_CcInformation = FindNodeInfoInReleventLst( -+ &p_FmPcdCcNextNode->ccTreeIdLst, (t_Handle)p_FmPcdCcTree, -+ p_FmPcdCcNextNode->h_Spinlock); -+ -+ if (!p_CcInformation) -+ { -+ memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation)); -+ ccNodeInfo.h_CcNode = (t_Handle)p_FmPcdCcTree; -+ ccNodeInfo.index = 1; -+ EnqueueNodeInfoToRelevantLst(&p_FmPcdCcNextNode->ccTreeIdLst, -+ &ccNodeInfo, -+ p_FmPcdCcNextNode->h_Spinlock); -+ } -+ else -+ p_CcInformation->index++; -+ } -+ } -+ -+ FmPcdIncNetEnvOwners(h_FmPcd, p_FmPcdCcTree->netEnvId); -+ p_CcTreeTmp = UINT_TO_PTR(p_FmPcdCcTree->ccTreeBaseAddr); -+ -+ if (!FmPcdLockTryLockAll(p_FmPcd)) -+ { -+ FM_PCD_CcRootDelete(p_FmPcdCcTree); -+ XX_Free(p_Params); -+ DBG(TRACE, ("FmPcdLockTryLockAll failed")); -+ return NULL; -+ } -+ -+ for (i = 0; i < numOfEntries; i++) -+ { -+ if (p_FmPcdCcTree->keyAndNextEngineParams[i].requiredAction) -+ { -+ err = SetRequiredAction( -+ h_FmPcd, -+ p_FmPcdCcTree->keyAndNextEngineParams[i].requiredAction, -+ &p_FmPcdCcTree->keyAndNextEngineParams[i], p_CcTreeTmp, 1, -+ p_FmPcdCcTree); -+ if (err) -+ { -+ FmPcdLockUnlockAll(p_FmPcd); -+ FM_PCD_CcRootDelete(p_FmPcdCcTree); -+ XX_Free(p_Params); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("No memory")); -+ return NULL; -+ } -+ p_CcTreeTmp = PTR_MOVE(p_CcTreeTmp, FM_PCD_CC_AD_ENTRY_SIZE); -+ } -+ } -+ -+ FmPcdLockUnlockAll(p_FmPcd); -+ p_FmPcdCcTree->p_Lock = FmPcdAcquireLock(p_FmPcd); -+ if (!p_FmPcdCcTree->p_Lock) -+ { -+ FM_PCD_CcRootDelete(p_FmPcdCcTree); -+ XX_Free(p_Params); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM CC lock")); -+ return NULL; -+ } -+ -+ XX_Free(p_Params); -+ -+ return p_FmPcdCcTree; -+} -+ -+t_Error FM_PCD_CcRootDelete(t_Handle h_CcTree) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdCcTree *p_CcTree = (t_FmPcdCcTree *)h_CcTree; -+ int i = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_CcTree, E_INVALID_STATE); -+ p_FmPcd = (t_FmPcd *)p_CcTree->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ -+ FmPcdDecNetEnvOwners(p_FmPcd, p_CcTree->netEnvId); -+ -+ if (p_CcTree->owners) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_SELECTION, -+ ("the tree with this ID can not be removed because this tree is occupied, first - unbind this tree")); -+ -+ /* Delete ip-reassembly schemes if exist */ -+ if (p_CcTree->h_IpReassemblyManip) -+ { -+ FmPcdManipDeleteIpReassmSchemes(p_CcTree->h_IpReassemblyManip); -+ FmPcdManipUpdateOwner(p_CcTree->h_IpReassemblyManip, FALSE); -+ } -+ -+ /* Delete capwap-reassembly schemes if exist */ -+ if (p_CcTree->h_CapwapReassemblyManip) -+ { -+ FmPcdManipDeleteCapwapReassmSchemes(p_CcTree->h_CapwapReassemblyManip); -+ FmPcdManipUpdateOwner(p_CcTree->h_CapwapReassemblyManip, FALSE); -+ } -+ -+ for (i = 0; i < p_CcTree->numOfEntries; i++) -+ { -+ if (p_CcTree->keyAndNextEngineParams[i].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ UpdateNodeOwner( -+ p_CcTree->keyAndNextEngineParams[i].nextEngineParams.params.ccParams.h_CcNode, -+ FALSE); -+ -+ if (p_CcTree->keyAndNextEngineParams[i].nextEngineParams.h_Manip) -+ FmPcdManipUpdateOwner( -+ p_CcTree->keyAndNextEngineParams[i].nextEngineParams.h_Manip, -+ FALSE); -+ -+#ifdef FM_CAPWAP_SUPPORT -+ if ((p_CcTree->numOfGrps == 1) && -+ (p_CcTree->fmPcdGroupParam[0].numOfEntriesInGroup == 1) && -+ (p_CcTree->keyAndNextEngineParams[0].nextEngineParams.nextEngine == e_FM_PCD_CC) && -+ p_CcTree->keyAndNextEngineParams[0].nextEngineParams.params.ccParams.h_CcNode && -+ IsCapwapApplSpecific(p_CcTree->keyAndNextEngineParams[0].nextEngineParams.params.ccParams.h_CcNode)) -+ { -+ if (FM_PCD_ManipNodeDelete(p_CcTree->keyAndNextEngineParams[0].nextEngineParams.h_Manip) != E_OK) -+ return E_INVALID_STATE; -+ } -+#endif /* FM_CAPWAP_SUPPORT */ -+ -+#if (DPAA_VERSION >= 11) -+ if ((p_CcTree->keyAndNextEngineParams[i].nextEngineParams.nextEngine -+ == e_FM_PCD_FR) -+ && (p_CcTree->keyAndNextEngineParams[i].nextEngineParams.params.frParams.h_FrmReplic)) -+ FrmReplicGroupUpdateOwner( -+ p_CcTree->keyAndNextEngineParams[i].nextEngineParams.params.frParams.h_FrmReplic, -+ FALSE); -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ -+ if (p_CcTree->p_Lock) -+ FmPcdReleaseLock(p_CcTree->h_FmPcd, p_CcTree->p_Lock); -+ -+ DeleteTree(p_CcTree, p_FmPcd); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_CcRootModifyNextEngine( -+ t_Handle h_CcTree, uint8_t grpId, uint8_t index, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdCcTree *p_CcTree = (t_FmPcdCcTree *)h_CcTree; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcdCcNextEngineParams, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_CcTree, E_INVALID_STATE); -+ p_FmPcd = (t_FmPcd *)p_CcTree->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ -+ if (!FmPcdLockTryLockAll(p_FmPcd)) -+ { -+ DBG(TRACE, ("FmPcdLockTryLockAll failed")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = FmPcdCcModifyNextEngineParamTree(p_FmPcd, p_CcTree, grpId, index, -+ p_FmPcdCcNextEngineParams); -+ FmPcdLockUnlockAll(p_FmPcd); -+ -+ if (err) -+ { -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ return E_OK; -+} -+ -+t_Handle FM_PCD_MatchTableSet(t_Handle h_FmPcd, -+ t_FmPcdCcNodeParams *p_CcNodeParam) -+{ -+ t_FmPcdCcNode *p_CcNode; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(p_CcNodeParam, E_NULL_POINTER, NULL); -+ -+ p_CcNode = (t_FmPcdCcNode*)XX_Malloc(sizeof(t_FmPcdCcNode)); -+ if (!p_CcNode) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("No memory")); -+ return NULL; -+ } -+ memset(p_CcNode, 0, sizeof(t_FmPcdCcNode)); -+ -+ err = MatchTableSet(h_FmPcd, p_CcNode, p_CcNodeParam); -+ -+ switch(GET_ERROR_TYPE(err) -+) { -+ case E_OK: -+ break; -+ -+ case E_BUSY: -+ DBG(TRACE, ("E_BUSY error")); -+ return NULL; -+ -+ default: -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ return NULL; -+ } -+ -+ return p_CcNode; -+} -+ -+t_Error FM_PCD_MatchTableDelete(t_Handle h_CcNode) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ int i = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_CcNode->h_FmPcd, E_INVALID_HANDLE); -+ -+ if (p_CcNode->owners) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("This node cannot be removed because it is occupied; first unbind this node")); -+ -+ for (i = 0; i < p_CcNode->numOfKeys; i++) -+ if (p_CcNode->keyAndNextEngineParams[i].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ UpdateNodeOwner( -+ p_CcNode->keyAndNextEngineParams[i].nextEngineParams.params.ccParams.h_CcNode, -+ FALSE); -+ -+ if (p_CcNode->keyAndNextEngineParams[i].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ UpdateNodeOwner( -+ p_CcNode->keyAndNextEngineParams[i].nextEngineParams.params.ccParams.h_CcNode, -+ FALSE); -+ -+ /* Handle also Miss entry */ -+ for (i = 0; i < p_CcNode->numOfKeys + 1; i++) -+ { -+ if (p_CcNode->keyAndNextEngineParams[i].nextEngineParams.h_Manip) -+ FmPcdManipUpdateOwner( -+ p_CcNode->keyAndNextEngineParams[i].nextEngineParams.h_Manip, -+ FALSE); -+ -+#if (DPAA_VERSION >= 11) -+ if ((p_CcNode->keyAndNextEngineParams[i].nextEngineParams.nextEngine -+ == e_FM_PCD_FR) -+ && (p_CcNode->keyAndNextEngineParams[i].nextEngineParams.params.frParams.h_FrmReplic)) -+ { -+ FrmReplicGroupUpdateOwner( -+ p_CcNode->keyAndNextEngineParams[i].nextEngineParams.params.frParams.h_FrmReplic, -+ FALSE); -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ -+ DeleteNode(p_CcNode); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_MatchTableAddKey(t_Handle h_CcNode, uint16_t keyIndex, -+ uint8_t keySize, -+ t_FmPcdCcKeyParams *p_KeyParams) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_KeyParams, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE); -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->h_Hc, E_INVALID_HANDLE); -+ -+ if (keyIndex == FM_PCD_LAST_KEY_INDEX) -+ keyIndex = p_CcNode->numOfKeys; -+ -+ if (!FmPcdLockTryLockAll(p_FmPcd)) -+ { -+ DBG(TRACE, ("FmPcdLockTryLockAll failed")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = FmPcdCcAddKey(p_FmPcd, p_CcNode, keyIndex, keySize, p_KeyParams); -+ -+ FmPcdLockUnlockAll(p_FmPcd); -+ -+ switch(GET_ERROR_TYPE(err) -+) { -+ case E_OK: -+ return E_OK; -+ -+ case E_BUSY: -+ DBG(TRACE, ("E_BUSY error")); -+ return ERROR_CODE(E_BUSY); -+ -+ default: -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+} -+ -+t_Error FM_PCD_MatchTableRemoveKey(t_Handle h_CcNode, uint16_t keyIndex) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE); -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->h_Hc, E_INVALID_HANDLE); -+ -+ if (!FmPcdLockTryLockAll(p_FmPcd)) -+ { -+ DBG(TRACE, ("FmPcdLockTryLockAll failed")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = FmPcdCcRemoveKey(p_FmPcd, p_CcNode, keyIndex); -+ -+ FmPcdLockUnlockAll(p_FmPcd); -+ -+ switch(GET_ERROR_TYPE(err) -+) { -+ case E_OK: -+ return E_OK; -+ -+ case E_BUSY: -+ DBG(TRACE, ("E_BUSY error")); -+ return ERROR_CODE(E_BUSY); -+ -+ default: -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_MatchTableModifyKey(t_Handle h_CcNode, uint16_t keyIndex, -+ uint8_t keySize, uint8_t *p_Key, -+ uint8_t *p_Mask) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Key, E_NULL_POINTER); -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->h_Hc, E_INVALID_HANDLE); -+ -+ -+ if (!FmPcdLockTryLockAll(p_FmPcd)) -+ { -+ DBG(TRACE, ("FmPcdLockTryLockAll failed")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = FmPcdCcModifyKey(p_FmPcd, p_CcNode, keyIndex, keySize, p_Key, p_Mask); -+ -+ FmPcdLockUnlockAll(p_FmPcd); -+ -+ switch(GET_ERROR_TYPE(err) -+) { -+ case E_OK: -+ return E_OK; -+ -+ case E_BUSY: -+ DBG(TRACE, ("E_BUSY error")); -+ return ERROR_CODE(E_BUSY); -+ -+ default: -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+} -+ -+t_Error FM_PCD_MatchTableModifyNextEngine( -+ t_Handle h_CcNode, uint16_t keyIndex, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcdCcNextEngineParams, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE); -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->h_Hc, E_INVALID_HANDLE); -+ -+ if (!FmPcdLockTryLockAll(p_FmPcd)) -+ { -+ DBG(TRACE, ("FmPcdLockTryLockAll failed")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = ModifyNextEngineParamNode(p_FmPcd, p_CcNode, keyIndex, -+ p_FmPcdCcNextEngineParams); -+ -+ FmPcdLockUnlockAll(p_FmPcd); -+ -+ switch(GET_ERROR_TYPE(err) -+) { -+ case E_OK: -+ return E_OK; -+ -+ case E_BUSY: -+ DBG(TRACE, ("E_BUSY error")); -+ return ERROR_CODE(E_BUSY); -+ -+ default: -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+} -+ -+t_Error FM_PCD_MatchTableModifyMissNextEngine( -+ t_Handle h_CcNode, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcdCcNextEngineParams, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE); -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->h_Hc, E_INVALID_HANDLE); -+ -+ if (!FmPcdLockTryLockAll(p_FmPcd)) -+ { -+ DBG(TRACE, ("FmPcdLockTryLockAll failed")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = FmPcdCcModifyMissNextEngineParamNode(p_FmPcd, p_CcNode, -+ p_FmPcdCcNextEngineParams); -+ -+ FmPcdLockUnlockAll(p_FmPcd); -+ -+ switch(GET_ERROR_TYPE(err) -+) { -+ case E_OK: -+ return E_OK; -+ -+ case E_BUSY: -+ DBG(TRACE, ("E_BUSY error")); -+ return ERROR_CODE(E_BUSY); -+ -+ default: -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+} -+ -+t_Error FM_PCD_MatchTableModifyKeyAndNextEngine(t_Handle h_CcNode, -+ uint16_t keyIndex, -+ uint8_t keySize, -+ t_FmPcdCcKeyParams *p_KeyParams) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_KeyParams, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE); -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->h_Hc, E_INVALID_HANDLE); -+ -+ if (!FmPcdLockTryLockAll(p_FmPcd)) -+ { -+ DBG(TRACE, ("FmPcdLockTryLockAll failed")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = FmPcdCcModifyKeyAndNextEngine(p_FmPcd, p_CcNode, keyIndex, keySize, -+ p_KeyParams); -+ -+ FmPcdLockUnlockAll(p_FmPcd); -+ -+ switch(GET_ERROR_TYPE(err) -+) { -+ case E_OK: -+ return E_OK; -+ -+ case E_BUSY: -+ DBG(TRACE, ("E_BUSY error")); -+ return ERROR_CODE(E_BUSY); -+ -+ default: -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+} -+ -+t_Error FM_PCD_MatchTableFindNRemoveKey(t_Handle h_CcNode, uint8_t keySize, -+ uint8_t *p_Key, uint8_t *p_Mask) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ uint16_t keyIndex; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Key, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE); -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->h_Hc, E_INVALID_HANDLE); -+ -+ if (!FmPcdLockTryLockAll(p_FmPcd)) -+ { -+ DBG(TRACE, ("FmPcdLockTryLockAll failed")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = FindKeyIndex(p_CcNode, keySize, p_Key, p_Mask, &keyIndex); -+ if (GET_ERROR_TYPE(err) != E_OK) -+ { -+ FmPcdLockUnlockAll(p_FmPcd); -+ RETURN_ERROR( -+ MAJOR, -+ err, -+ ("The received key and mask pair was not found in the match table of the provided node")); -+ } -+ -+ err = FmPcdCcRemoveKey(p_FmPcd, p_CcNode, keyIndex); -+ -+ FmPcdLockUnlockAll(p_FmPcd); -+ -+ switch(GET_ERROR_TYPE(err) -+) { -+ case E_OK: -+ return E_OK; -+ -+ case E_BUSY: -+ DBG(TRACE, ("E_BUSY error")); -+ return ERROR_CODE(E_BUSY); -+ -+ default: -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+} -+ -+t_Error FM_PCD_MatchTableFindNModifyNextEngine( -+ t_Handle h_CcNode, uint8_t keySize, uint8_t *p_Key, uint8_t *p_Mask, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ uint16_t keyIndex; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Key, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcdCcNextEngineParams, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE); -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->h_Hc, E_INVALID_HANDLE); -+ -+ if (!FmPcdLockTryLockAll(p_FmPcd)) -+ { -+ DBG(TRACE, ("FmPcdLockTryLockAll failed")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = FindKeyIndex(p_CcNode, keySize, p_Key, p_Mask, &keyIndex); -+ if (GET_ERROR_TYPE(err) != E_OK) -+ { -+ FmPcdLockUnlockAll(p_FmPcd); -+ RETURN_ERROR( -+ MAJOR, -+ err, -+ ("The received key and mask pair was not found in the match table of the provided node")); -+ } -+ -+ err = ModifyNextEngineParamNode(p_FmPcd, p_CcNode, keyIndex, -+ p_FmPcdCcNextEngineParams); -+ -+ FmPcdLockUnlockAll(p_FmPcd); -+ -+ switch(GET_ERROR_TYPE(err) -+) { -+ case E_OK: -+ return E_OK; -+ -+ case E_BUSY: -+ DBG(TRACE, ("E_BUSY error")); -+ return ERROR_CODE(E_BUSY); -+ -+ default: -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+} -+ -+t_Error FM_PCD_MatchTableFindNModifyKeyAndNextEngine( -+ t_Handle h_CcNode, uint8_t keySize, uint8_t *p_Key, uint8_t *p_Mask, -+ t_FmPcdCcKeyParams *p_KeyParams) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ uint16_t keyIndex; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Key, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_KeyParams, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE); -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->h_Hc, E_INVALID_HANDLE); -+ -+ if (!FmPcdLockTryLockAll(p_FmPcd)) -+ { -+ DBG(TRACE, ("FmPcdLockTryLockAll failed")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = FindKeyIndex(p_CcNode, keySize, p_Key, p_Mask, &keyIndex); -+ if (GET_ERROR_TYPE(err) != E_OK) -+ { -+ FmPcdLockUnlockAll(p_FmPcd); -+ RETURN_ERROR( -+ MAJOR, -+ err, -+ ("The received key and mask pair was not found in the match table of the provided node")); -+ } -+ -+ err = FmPcdCcModifyKeyAndNextEngine(p_FmPcd, h_CcNode, keyIndex, keySize, -+ p_KeyParams); -+ -+ FmPcdLockUnlockAll(p_FmPcd); -+ -+ switch(GET_ERROR_TYPE(err) -+) { -+ case E_OK: -+ return E_OK; -+ -+ case E_BUSY: -+ DBG(TRACE, ("E_BUSY error")); -+ return ERROR_CODE(E_BUSY); -+ -+ default: -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+} -+ -+t_Error FM_PCD_MatchTableFindNModifyKey(t_Handle h_CcNode, uint8_t keySize, -+ uint8_t *p_Key, uint8_t *p_Mask, -+ uint8_t *p_NewKey, uint8_t *p_NewMask) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ t_List h_List; -+ uint16_t keyIndex; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Key, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_NewKey, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE); -+ p_FmPcd = (t_FmPcd *)p_CcNode->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->h_Hc, E_INVALID_HANDLE); -+ -+ INIT_LIST(&h_List); -+ -+ err = FmPcdCcNodeTreeTryLock(p_FmPcd, p_CcNode, &h_List); -+ if (err) -+ { -+ DBG(TRACE, ("Node's trees lock failed")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = FindKeyIndex(p_CcNode, keySize, p_Key, p_Mask, &keyIndex); -+ if (GET_ERROR_TYPE(err) != E_OK) -+ { -+ FmPcdCcNodeTreeReleaseLock(p_FmPcd, &h_List); -+ RETURN_ERROR(MAJOR, err, -+ ("The received key and mask pair was not found in the " -+ "match table of the provided node")); -+ } -+ -+ err = FmPcdCcModifyKey(p_FmPcd, p_CcNode, keyIndex, keySize, p_NewKey, -+ p_NewMask); -+ -+ FmPcdCcNodeTreeReleaseLock(p_FmPcd, &h_List); -+ -+ switch(GET_ERROR_TYPE(err) -+) { -+ case E_OK: -+ return E_OK; -+ -+ case E_BUSY: -+ DBG(TRACE, ("E_BUSY error")); -+ return ERROR_CODE(E_BUSY); -+ -+ default: -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+} -+ -+t_Error FM_PCD_MatchTableGetNextEngine( -+ t_Handle h_CcNode, uint16_t keyIndex, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ -+ SANITY_CHECK_RETURN_ERROR(p_CcNode, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcdCcNextEngineParams, E_NULL_POINTER); -+ -+ if (keyIndex >= p_CcNode->numOfKeys) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("keyIndex exceeds current number of keys")); -+ -+ if (keyIndex > (FM_PCD_MAX_NUM_OF_KEYS - 1)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("keyIndex can not be larger than %d", (FM_PCD_MAX_NUM_OF_KEYS - 1))); -+ -+ memcpy(p_FmPcdCcNextEngineParams, -+ &p_CcNode->keyAndNextEngineParams[keyIndex].nextEngineParams, -+ sizeof(t_FmPcdCcNextEngineParams)); -+ -+ return E_OK; -+} -+ -+ -+uint32_t FM_PCD_MatchTableGetKeyCounter(t_Handle h_CcNode, uint16_t keyIndex) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ uint32_t *p_StatsCounters, frameCount; -+ uint32_t intFlags; -+ -+ SANITY_CHECK_RETURN_VALUE(p_CcNode, E_INVALID_HANDLE, 0); -+ -+ if (p_CcNode->statisticsMode == e_FM_PCD_CC_STATS_MODE_NONE) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Statistics were not enabled for this match table")); -+ return 0; -+ } -+ -+ if ((p_CcNode->statisticsMode != e_FM_PCD_CC_STATS_MODE_FRAME) -+ && (p_CcNode->statisticsMode -+ != e_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME)) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Frame count is not supported in the statistics mode of this match table")); -+ return 0; -+ } -+ -+ intFlags = XX_LockIntrSpinlock(p_CcNode->h_Spinlock); -+ -+ if (keyIndex >= p_CcNode->numOfKeys) -+ { -+ XX_UnlockIntrSpinlock(p_CcNode->h_Spinlock, intFlags); -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("The provided keyIndex exceeds the number of keys in this match table")); -+ return 0; -+ } -+ -+ if (!p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj) -+ { -+ XX_UnlockIntrSpinlock(p_CcNode->h_Spinlock, intFlags); -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Statistics were not enabled for this key")); -+ return 0; -+ } -+ -+ p_StatsCounters = -+ p_CcNode->keyAndNextEngineParams[keyIndex].p_StatsObj->h_StatsCounters; -+ ASSERT_COND(p_StatsCounters); -+ -+ /* The first counter is byte counter, so we need to advance to the next counter */ -+ frameCount = GET_UINT32(*(uint32_t *)(PTR_MOVE(p_StatsCounters, -+ FM_PCD_CC_STATS_COUNTER_SIZE))); -+ -+ XX_UnlockIntrSpinlock(p_CcNode->h_Spinlock, intFlags); -+ -+ return frameCount; -+} -+ -+t_Error FM_PCD_MatchTableGetKeyStatistics( -+ t_Handle h_CcNode, uint16_t keyIndex, -+ t_FmPcdCcKeyStatistics *p_KeyStatistics) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ uint32_t intFlags; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(h_CcNode, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_KeyStatistics, E_NULL_POINTER); -+ -+ intFlags = XX_LockIntrSpinlock(p_CcNode->h_Spinlock); -+ -+ if (keyIndex >= p_CcNode->numOfKeys) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("The provided keyIndex exceeds the number of keys in this match table")); -+ -+ err = MatchTableGetKeyStatistics(p_CcNode, keyIndex, p_KeyStatistics); -+ -+ XX_UnlockIntrSpinlock(p_CcNode->h_Spinlock, intFlags); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_MatchTableGetMissStatistics( -+ t_Handle h_CcNode, t_FmPcdCcKeyStatistics *p_MissStatistics) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ uint32_t intFlags; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(h_CcNode, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_MissStatistics, E_NULL_POINTER); -+ -+ intFlags = XX_LockIntrSpinlock(p_CcNode->h_Spinlock); -+ -+ err = MatchTableGetKeyStatistics(p_CcNode, p_CcNode->numOfKeys, -+ p_MissStatistics); -+ -+ XX_UnlockIntrSpinlock(p_CcNode->h_Spinlock, intFlags); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_MatchTableFindNGetKeyStatistics( -+ t_Handle h_CcNode, uint8_t keySize, uint8_t *p_Key, uint8_t *p_Mask, -+ t_FmPcdCcKeyStatistics *p_KeyStatistics) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ uint16_t keyIndex; -+ uint32_t intFlags; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Key, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_KeyStatistics, E_NULL_POINTER); -+ -+ intFlags = XX_LockIntrSpinlock(p_CcNode->h_Spinlock); -+ -+ err = FindKeyIndex(p_CcNode, keySize, p_Key, p_Mask, &keyIndex); -+ if (GET_ERROR_TYPE(err) != E_OK) -+ { -+ XX_UnlockIntrSpinlock(p_CcNode->h_Spinlock, intFlags); -+ RETURN_ERROR(MAJOR, err, -+ ("The received key and mask pair was not found in the " -+ "match table of the provided node")); -+ } -+ -+ ASSERT_COND(keyIndex < p_CcNode->numOfKeys); -+ -+ err = MatchTableGetKeyStatistics(p_CcNode, keyIndex, p_KeyStatistics); -+ -+ XX_UnlockIntrSpinlock(p_CcNode->h_Spinlock, intFlags); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_MatchTableGetIndexedHashBucket(t_Handle h_CcNode, -+ uint8_t keySize, uint8_t *p_Key, -+ uint8_t hashShift, -+ t_Handle *p_CcNodeBucketHandle, -+ uint8_t *p_BucketIndex, -+ uint16_t *p_LastIndex) -+{ -+ t_FmPcdCcNode *p_CcNode = (t_FmPcdCcNode *)h_CcNode; -+ uint16_t glblMask; -+ uint64_t crc64 = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(h_CcNode, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR( -+ p_CcNode->parseCode == CC_PC_GENERIC_IC_HASH_INDEXED, -+ E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_Key, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_CcNodeBucketHandle, E_NULL_POINTER); -+ -+ memcpy(&glblMask, PTR_MOVE(p_CcNode->p_GlblMask, 2), 2); -+ be16_to_cpus(&glblMask); -+ -+ crc64 = crc64_init(); -+ crc64 = crc64_compute(p_Key, keySize, crc64); -+ crc64 >>= hashShift; -+ -+ *p_BucketIndex = (uint8_t)(((crc64 >> (8 * (6 - p_CcNode->userOffset))) -+ & glblMask) >> 4); -+ if (*p_BucketIndex >= p_CcNode->numOfKeys) -+ RETURN_ERROR(MINOR, E_NOT_IN_RANGE, ("bucket index!")); -+ -+ *p_CcNodeBucketHandle = -+ p_CcNode->keyAndNextEngineParams[*p_BucketIndex].nextEngineParams.params.ccParams.h_CcNode; -+ if (!*p_CcNodeBucketHandle) -+ RETURN_ERROR(MINOR, E_NOT_FOUND, ("bucket!")); -+ -+ *p_LastIndex = ((t_FmPcdCcNode *)*p_CcNodeBucketHandle)->numOfKeys; -+ -+ return E_OK; -+} -+ -+t_Handle FM_PCD_HashTableSet(t_Handle h_FmPcd, t_FmPcdHashTableParams *p_Param) -+{ -+ t_FmPcdCcNode *p_CcNodeHashTbl; -+ t_FmPcdCcNodeParams *p_IndxHashCcNodeParam, *p_ExactMatchCcNodeParam; -+ t_FmPcdCcNode *p_CcNode; -+ t_Handle h_MissStatsCounters = NULL; -+ t_FmPcdCcKeyParams *p_HashKeyParams; -+ int i; -+ uint16_t numOfSets, numOfWays, countMask, onesCount = 0; -+ bool statsEnForMiss = FALSE; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(p_Param, E_NULL_POINTER, NULL); -+ -+ if (p_Param->maxNumOfKeys == 0) -+ { -+ REPORT_ERROR(MINOR, E_INVALID_VALUE, ("Max number of keys must be higher then 0")); -+ return NULL; -+ } -+ -+ if (p_Param->hashResMask == 0) -+ { -+ REPORT_ERROR(MINOR, E_INVALID_VALUE, ("Hash result mask must differ from 0")); -+ return NULL; -+ } -+ -+#if (DPAA_VERSION >= 11) -+ if (p_Param->statisticsMode == e_FM_PCD_CC_STATS_MODE_RMON) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("RMON statistics mode is not supported for hash table")); -+ return NULL; -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ p_ExactMatchCcNodeParam = (t_FmPcdCcNodeParams*)XX_Malloc( -+ sizeof(t_FmPcdCcNodeParams)); -+ if (!p_ExactMatchCcNodeParam) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("p_ExactMatchCcNodeParam")); -+ return NULL; -+ } -+ memset(p_ExactMatchCcNodeParam, 0, sizeof(t_FmPcdCcNodeParams)); -+ -+ p_IndxHashCcNodeParam = (t_FmPcdCcNodeParams*)XX_Malloc( -+ sizeof(t_FmPcdCcNodeParams)); -+ if (!p_IndxHashCcNodeParam) -+ { -+ XX_Free(p_ExactMatchCcNodeParam); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("p_IndxHashCcNodeParam")); -+ return NULL; -+ } -+ memset(p_IndxHashCcNodeParam, 0, sizeof(t_FmPcdCcNodeParams)); -+ -+ /* Calculate number of sets and number of ways of the hash table */ -+ countMask = (uint16_t)(p_Param->hashResMask >> 4); -+ while (countMask) -+ { -+ onesCount++; -+ countMask = (uint16_t)(countMask >> 1); -+ } -+ -+ numOfSets = (uint16_t)(1 << onesCount); -+ numOfWays = (uint16_t)DIV_CEIL(p_Param->maxNumOfKeys, numOfSets); -+ -+ if (p_Param->maxNumOfKeys % numOfSets) -+ DBG(INFO, ("'maxNumOfKeys' is not a multiple of hash number of ways, so number of ways will be rounded up")); -+ -+ if ((p_Param->statisticsMode == e_FM_PCD_CC_STATS_MODE_FRAME) -+ || (p_Param->statisticsMode == e_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME)) -+ { -+ /* Allocating a statistics counters table that will be used by all -+ 'miss' entries of the hash table */ -+ h_MissStatsCounters = (t_Handle)FM_MURAM_AllocMem( -+ FmPcdGetMuramHandle(h_FmPcd), 2 * FM_PCD_CC_STATS_COUNTER_SIZE, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!h_MissStatsCounters) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("MURAM allocation for statistics table for hash miss")); -+ XX_Free(p_IndxHashCcNodeParam); -+ XX_Free(p_ExactMatchCcNodeParam); -+ return NULL; -+ } -+ memset(h_MissStatsCounters, 0, (2 * FM_PCD_CC_STATS_COUNTER_SIZE)); -+ -+ /* Always enable statistics for 'miss', so that a statistics AD will be -+ initialized from the start. We'll store the requested 'statistics enable' -+ value and it will be used when statistics are read by the user. */ -+ statsEnForMiss = p_Param->ccNextEngineParamsForMiss.statisticsEn; -+ p_Param->ccNextEngineParamsForMiss.statisticsEn = TRUE; -+ } -+ -+ /* Building exact-match node params, will be used to create the hash buckets */ -+ p_ExactMatchCcNodeParam->extractCcParams.type = e_FM_PCD_EXTRACT_NON_HDR; -+ -+ p_ExactMatchCcNodeParam->extractCcParams.extractNonHdr.src = -+ e_FM_PCD_EXTRACT_FROM_KEY; -+ p_ExactMatchCcNodeParam->extractCcParams.extractNonHdr.action = -+ e_FM_PCD_ACTION_EXACT_MATCH; -+ p_ExactMatchCcNodeParam->extractCcParams.extractNonHdr.offset = 0; -+ p_ExactMatchCcNodeParam->extractCcParams.extractNonHdr.size = -+ p_Param->matchKeySize; -+ -+ p_ExactMatchCcNodeParam->keysParams.maxNumOfKeys = numOfWays; -+ p_ExactMatchCcNodeParam->keysParams.maskSupport = FALSE; -+ p_ExactMatchCcNodeParam->keysParams.statisticsMode = -+ p_Param->statisticsMode; -+ p_ExactMatchCcNodeParam->keysParams.numOfKeys = 0; -+ p_ExactMatchCcNodeParam->keysParams.keySize = p_Param->matchKeySize; -+ p_ExactMatchCcNodeParam->keysParams.ccNextEngineParamsForMiss = -+ p_Param->ccNextEngineParamsForMiss; -+ -+ p_HashKeyParams = p_IndxHashCcNodeParam->keysParams.keyParams; -+ -+ for (i = 0; i < numOfSets; i++) -+ { -+ /* Each exact-match node will be marked as a 'bucket' and provided with -+ a pointer to statistics counters, to be used for 'miss' entry -+ statistics */ -+ p_CcNode = (t_FmPcdCcNode *)XX_Malloc(sizeof(t_FmPcdCcNode)); -+ if (!p_CcNode) -+ break; -+ memset(p_CcNode, 0, sizeof(t_FmPcdCcNode)); -+ -+ p_CcNode->isHashBucket = TRUE; -+ p_CcNode->h_MissStatsCounters = h_MissStatsCounters; -+ -+ err = MatchTableSet(h_FmPcd, p_CcNode, p_ExactMatchCcNodeParam); -+ if (err) -+ break; -+ -+ p_HashKeyParams[i].ccNextEngineParams.nextEngine = e_FM_PCD_CC; -+ p_HashKeyParams[i].ccNextEngineParams.statisticsEn = FALSE; -+ p_HashKeyParams[i].ccNextEngineParams.params.ccParams.h_CcNode = -+ p_CcNode; -+ } -+ -+ if (i < numOfSets) -+ { -+ for (i = i - 1; i >= 0; i--) -+ FM_PCD_MatchTableDelete( -+ p_HashKeyParams[i].ccNextEngineParams.params.ccParams.h_CcNode); -+ -+ FM_MURAM_FreeMem(FmPcdGetMuramHandle(h_FmPcd), h_MissStatsCounters); -+ -+ REPORT_ERROR(MAJOR, E_NULL_POINTER, NO_MSG); -+ XX_Free(p_IndxHashCcNodeParam); -+ XX_Free(p_ExactMatchCcNodeParam); -+ return NULL; -+ } -+ -+ /* Creating indexed-hash CC node */ -+ p_IndxHashCcNodeParam->extractCcParams.type = e_FM_PCD_EXTRACT_NON_HDR; -+ p_IndxHashCcNodeParam->extractCcParams.extractNonHdr.src = -+ e_FM_PCD_EXTRACT_FROM_HASH; -+ p_IndxHashCcNodeParam->extractCcParams.extractNonHdr.action = -+ e_FM_PCD_ACTION_INDEXED_LOOKUP; -+ p_IndxHashCcNodeParam->extractCcParams.extractNonHdr.icIndxMask = -+ p_Param->hashResMask; -+ p_IndxHashCcNodeParam->extractCcParams.extractNonHdr.offset = -+ p_Param->hashShift; -+ p_IndxHashCcNodeParam->extractCcParams.extractNonHdr.size = 2; -+ -+ p_IndxHashCcNodeParam->keysParams.maxNumOfKeys = numOfSets; -+ p_IndxHashCcNodeParam->keysParams.maskSupport = FALSE; -+ p_IndxHashCcNodeParam->keysParams.statisticsMode = -+ e_FM_PCD_CC_STATS_MODE_NONE; -+ /* Number of keys of this node is number of sets of the hash */ -+ p_IndxHashCcNodeParam->keysParams.numOfKeys = numOfSets; -+ p_IndxHashCcNodeParam->keysParams.keySize = 2; -+ -+ p_CcNodeHashTbl = FM_PCD_MatchTableSet(h_FmPcd, p_IndxHashCcNodeParam); -+ -+ if (p_CcNodeHashTbl) -+ { -+ p_CcNodeHashTbl->kgHashShift = p_Param->kgHashShift; -+ -+ /* Storing the allocated counters for buckets 'miss' in the hash table -+ and if statistics for miss were enabled. */ -+ p_CcNodeHashTbl->h_MissStatsCounters = h_MissStatsCounters; -+ p_CcNodeHashTbl->statsEnForMiss = statsEnForMiss; -+ } -+ -+ XX_Free(p_IndxHashCcNodeParam); -+ XX_Free(p_ExactMatchCcNodeParam); -+ -+ return p_CcNodeHashTbl; -+} -+ -+t_Error FM_PCD_HashTableDelete(t_Handle h_HashTbl) -+{ -+ t_FmPcdCcNode *p_HashTbl = (t_FmPcdCcNode *)h_HashTbl; -+ t_Handle h_FmPcd; -+ t_Handle *p_HashBuckets, h_MissStatsCounters; -+ uint16_t i, numOfBuckets; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_HashTbl, E_INVALID_HANDLE); -+ -+ /* Store all hash buckets before the hash is freed */ -+ numOfBuckets = p_HashTbl->numOfKeys; -+ -+ p_HashBuckets = (t_Handle *)XX_Malloc(numOfBuckets * sizeof(t_Handle)); -+ if (!p_HashBuckets) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ -+ for (i = 0; i < numOfBuckets; i++) -+ p_HashBuckets[i] = -+ p_HashTbl->keyAndNextEngineParams[i].nextEngineParams.params.ccParams.h_CcNode; -+ -+ h_FmPcd = p_HashTbl->h_FmPcd; -+ h_MissStatsCounters = p_HashTbl->h_MissStatsCounters; -+ -+ /* Free the hash */ -+ err = FM_PCD_MatchTableDelete(p_HashTbl); -+ -+ /* Free each hash bucket */ -+ for (i = 0; i < numOfBuckets; i++) -+ err |= FM_PCD_MatchTableDelete(p_HashBuckets[i]); -+ -+ XX_Free(p_HashBuckets); -+ -+ /* Free statistics counters for 'miss', if these were allocated */ -+ if (h_MissStatsCounters) -+ FM_MURAM_FreeMem(FmPcdGetMuramHandle(h_FmPcd), h_MissStatsCounters); -+ -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_HashTableAddKey(t_Handle h_HashTbl, uint8_t keySize, -+ t_FmPcdCcKeyParams *p_KeyParams) -+{ -+ t_FmPcdCcNode *p_HashTbl = (t_FmPcdCcNode *)h_HashTbl; -+ t_Handle h_HashBucket; -+ uint8_t bucketIndex; -+ uint16_t lastIndex; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_HashTbl, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_KeyParams, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_KeyParams->p_Key, E_NULL_POINTER); -+ -+ if (p_KeyParams->p_Mask) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("Keys masks not supported for hash table")); -+ -+ err = FM_PCD_MatchTableGetIndexedHashBucket(p_HashTbl, keySize, -+ p_KeyParams->p_Key, -+ p_HashTbl->kgHashShift, -+ &h_HashBucket, &bucketIndex, -+ &lastIndex); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ return FM_PCD_MatchTableAddKey(h_HashBucket, FM_PCD_LAST_KEY_INDEX, keySize, -+ p_KeyParams); -+} -+ -+t_Error FM_PCD_HashTableRemoveKey(t_Handle h_HashTbl, uint8_t keySize, -+ uint8_t *p_Key) -+{ -+ t_FmPcdCcNode *p_HashTbl = (t_FmPcdCcNode *)h_HashTbl; -+ t_Handle h_HashBucket; -+ uint8_t bucketIndex; -+ uint16_t lastIndex; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_HashTbl, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Key, E_NULL_POINTER); -+ -+ err = FM_PCD_MatchTableGetIndexedHashBucket(p_HashTbl, keySize, p_Key, -+ p_HashTbl->kgHashShift, -+ &h_HashBucket, &bucketIndex, -+ &lastIndex); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ return FM_PCD_MatchTableFindNRemoveKey(h_HashBucket, keySize, p_Key, NULL); -+} -+ -+t_Error FM_PCD_HashTableModifyNextEngine( -+ t_Handle h_HashTbl, uint8_t keySize, uint8_t *p_Key, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams) -+{ -+ t_FmPcdCcNode *p_HashTbl = (t_FmPcdCcNode *)h_HashTbl; -+ t_Handle h_HashBucket; -+ uint8_t bucketIndex; -+ uint16_t lastIndex; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_HashTbl, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Key, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcdCcNextEngineParams, E_NULL_POINTER); -+ -+ err = FM_PCD_MatchTableGetIndexedHashBucket(p_HashTbl, keySize, p_Key, -+ p_HashTbl->kgHashShift, -+ &h_HashBucket, &bucketIndex, -+ &lastIndex); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ return FM_PCD_MatchTableFindNModifyNextEngine(h_HashBucket, keySize, p_Key, -+ NULL, -+ p_FmPcdCcNextEngineParams); -+} -+ -+t_Error FM_PCD_HashTableModifyMissNextEngine( -+ t_Handle h_HashTbl, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams) -+{ -+ t_FmPcdCcNode *p_HashTbl = (t_FmPcdCcNode *)h_HashTbl; -+ t_Handle h_HashBucket; -+ uint8_t i; -+ bool nullifyMissStats = FALSE; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(h_HashTbl, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcdCcNextEngineParams, E_NULL_POINTER); -+ -+ if ((!p_HashTbl->h_MissStatsCounters) -+ && (p_FmPcdCcNextEngineParams->statisticsEn)) -+ RETURN_ERROR( -+ MAJOR, -+ E_CONFLICT, -+ ("Statistics are requested for a key, but statistics mode was set" -+ "to 'NONE' upon initialization")); -+ -+ if (p_HashTbl->h_MissStatsCounters) -+ { -+ if ((!p_HashTbl->statsEnForMiss) -+ && (p_FmPcdCcNextEngineParams->statisticsEn)) -+ nullifyMissStats = TRUE; -+ -+ if ((p_HashTbl->statsEnForMiss) -+ && (!p_FmPcdCcNextEngineParams->statisticsEn)) -+ { -+ p_HashTbl->statsEnForMiss = FALSE; -+ p_FmPcdCcNextEngineParams->statisticsEn = TRUE; -+ } -+ } -+ -+ for (i = 0; i < p_HashTbl->numOfKeys; i++) -+ { -+ h_HashBucket = -+ p_HashTbl->keyAndNextEngineParams[i].nextEngineParams.params.ccParams.h_CcNode; -+ -+ err = FM_PCD_MatchTableModifyMissNextEngine(h_HashBucket, -+ p_FmPcdCcNextEngineParams); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ if (nullifyMissStats) -+ { -+ memset(p_HashTbl->h_MissStatsCounters, 0, -+ (2 * FM_PCD_CC_STATS_COUNTER_SIZE)); -+ memset(p_HashTbl->h_MissStatsCounters, 0, -+ (2 * FM_PCD_CC_STATS_COUNTER_SIZE)); -+ p_HashTbl->statsEnForMiss = TRUE; -+ } -+ -+ return E_OK; -+} -+ -+ -+t_Error FM_PCD_HashTableGetMissNextEngine( -+ t_Handle h_HashTbl, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams) -+{ -+ t_FmPcdCcNode *p_HashTbl = (t_FmPcdCcNode *)h_HashTbl; -+ t_FmPcdCcNode *p_HashBucket; -+ -+ SANITY_CHECK_RETURN_ERROR(p_HashTbl, E_INVALID_HANDLE); -+ -+ /* Miss next engine of each bucket was initialized with the next engine of the hash table */ -+ p_HashBucket = -+ p_HashTbl->keyAndNextEngineParams[0].nextEngineParams.params.ccParams.h_CcNode; -+ -+ memcpy(p_FmPcdCcNextEngineParams, -+ &p_HashBucket->keyAndNextEngineParams[p_HashBucket->numOfKeys].nextEngineParams, -+ sizeof(t_FmPcdCcNextEngineParams)); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_HashTableFindNGetKeyStatistics( -+ t_Handle h_HashTbl, uint8_t keySize, uint8_t *p_Key, -+ t_FmPcdCcKeyStatistics *p_KeyStatistics) -+{ -+ t_FmPcdCcNode *p_HashTbl = (t_FmPcdCcNode *)h_HashTbl; -+ t_Handle h_HashBucket; -+ uint8_t bucketIndex; -+ uint16_t lastIndex; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_HashTbl, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Key, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_KeyStatistics, E_NULL_POINTER); -+ -+ err = FM_PCD_MatchTableGetIndexedHashBucket(p_HashTbl, keySize, p_Key, -+ p_HashTbl->kgHashShift, -+ &h_HashBucket, &bucketIndex, -+ &lastIndex); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ return FM_PCD_MatchTableFindNGetKeyStatistics(h_HashBucket, keySize, p_Key, -+ NULL, p_KeyStatistics); -+} -+ -+t_Error FM_PCD_HashTableGetMissStatistics( -+ t_Handle h_HashTbl, t_FmPcdCcKeyStatistics *p_MissStatistics) -+{ -+ t_FmPcdCcNode *p_HashTbl = (t_FmPcdCcNode *)h_HashTbl; -+ t_Handle h_HashBucket; -+ -+ SANITY_CHECK_RETURN_ERROR(p_HashTbl, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_MissStatistics, E_NULL_POINTER); -+ -+ if (!p_HashTbl->statsEnForMiss) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("Statistics were not enabled for miss")); -+ -+ h_HashBucket = -+ p_HashTbl->keyAndNextEngineParams[0].nextEngineParams.params.ccParams.h_CcNode; -+ -+ return FM_PCD_MatchTableGetMissStatistics(h_HashBucket, p_MissStatistics); -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.h -@@ -0,0 +1,399 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_cc.h -+ -+ @Description FM PCD CC ... -+*//***************************************************************************/ -+#ifndef __FM_CC_H -+#define __FM_CC_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "list_ext.h" -+ -+#include "fm_pcd.h" -+ -+ -+/***********************************************************************/ -+/* Coarse classification defines */ -+/***********************************************************************/ -+ -+#define CC_MAX_NUM_OF_KEYS (FM_PCD_MAX_NUM_OF_KEYS + 1) -+ -+#define CC_PC_FF_MACDST 0x00 -+#define CC_PC_FF_MACSRC 0x01 -+#define CC_PC_FF_ETYPE 0x02 -+ -+#define CC_PC_FF_TCI1 0x03 -+#define CC_PC_FF_TCI2 0x04 -+ -+#define CC_PC_FF_MPLS1 0x06 -+#define CC_PC_FF_MPLS_LAST 0x07 -+ -+#define CC_PC_FF_IPV4DST1 0x08 -+#define CC_PC_FF_IPV4DST2 0x16 -+#define CC_PC_FF_IPV4IPTOS_TC1 0x09 -+#define CC_PC_FF_IPV4IPTOS_TC2 0x17 -+#define CC_PC_FF_IPV4PTYPE1 0x0A -+#define CC_PC_FF_IPV4PTYPE2 0x18 -+#define CC_PC_FF_IPV4SRC1 0x0b -+#define CC_PC_FF_IPV4SRC2 0x19 -+#define CC_PC_FF_IPV4SRC1_IPV4DST1 0x0c -+#define CC_PC_FF_IPV4SRC2_IPV4DST2 0x1a -+#define CC_PC_FF_IPV4TTL 0x29 -+ -+ -+#define CC_PC_FF_IPTOS_IPV6TC1_IPV6FLOW1 0x0d /*TODO - CLASS - what is it? TOS*/ -+#define CC_PC_FF_IPTOS_IPV6TC2_IPV6FLOW2 0x1b -+#define CC_PC_FF_IPV6PTYPE1 0x0e -+#define CC_PC_FF_IPV6PTYPE2 0x1c -+#define CC_PC_FF_IPV6DST1 0x0f -+#define CC_PC_FF_IPV6DST2 0x1d -+#define CC_PC_FF_IPV6SRC1 0x10 -+#define CC_PC_FF_IPV6SRC2 0x1e -+#define CC_PC_FF_IPV6HOP_LIMIT 0x2a -+#define CC_PC_FF_IPPID 0x24 -+#define CC_PC_FF_IPDSCP 0x76 -+ -+#define CC_PC_FF_GREPTYPE 0x11 -+ -+#define CC_PC_FF_MINENCAP_PTYPE 0x12 -+#define CC_PC_FF_MINENCAP_IPDST 0x13 -+#define CC_PC_FF_MINENCAP_IPSRC 0x14 -+#define CC_PC_FF_MINENCAP_IPSRC_IPDST 0x15 -+ -+#define CC_PC_FF_L4PSRC 0x1f -+#define CC_PC_FF_L4PDST 0x20 -+#define CC_PC_FF_L4PSRC_L4PDST 0x21 -+ -+#define CC_PC_FF_PPPPID 0x05 -+ -+#define CC_PC_PR_SHIM1 0x22 -+#define CC_PC_PR_SHIM2 0x23 -+ -+#define CC_PC_GENERIC_WITHOUT_MASK 0x27 -+#define CC_PC_GENERIC_WITH_MASK 0x28 -+#define CC_PC_GENERIC_IC_GMASK 0x2B -+#define CC_PC_GENERIC_IC_HASH_INDEXED 0x2C -+#define CC_PC_GENERIC_IC_AGING_MASK 0x2D -+ -+#define CC_PR_OFFSET 0x25 -+#define CC_PR_WITHOUT_OFFSET 0x26 -+ -+#define CC_PC_PR_ETH_OFFSET 19 -+#define CC_PC_PR_USER_DEFINED_SHIM1_OFFSET 16 -+#define CC_PC_PR_USER_DEFINED_SHIM2_OFFSET 17 -+#define CC_PC_PR_USER_LLC_SNAP_OFFSET 20 -+#define CC_PC_PR_VLAN1_OFFSET 21 -+#define CC_PC_PR_VLAN2_OFFSET 22 -+#define CC_PC_PR_PPPOE_OFFSET 24 -+#define CC_PC_PR_MPLS1_OFFSET 25 -+#define CC_PC_PR_MPLS_LAST_OFFSET 26 -+#define CC_PC_PR_IP1_OFFSET 27 -+#define CC_PC_PR_IP_LAST_OFFSET 28 -+#define CC_PC_PR_MINENC_OFFSET 28 -+#define CC_PC_PR_L4_OFFSET 30 -+#define CC_PC_PR_GRE_OFFSET 29 -+#define CC_PC_PR_ETYPE_LAST_OFFSET 23 -+#define CC_PC_PR_NEXT_HEADER_OFFSET 31 -+ -+#define CC_PC_ILLEGAL 0xff -+#define CC_SIZE_ILLEGAL 0 -+ -+#define FM_PCD_CC_KEYS_MATCH_TABLE_ALIGN 16 -+#define FM_PCD_CC_AD_TABLE_ALIGN 16 -+#define FM_PCD_CC_AD_ENTRY_SIZE 16 -+#define FM_PCD_CC_NUM_OF_KEYS 255 -+#define FM_PCD_CC_TREE_ADDR_ALIGN 256 -+ -+#define FM_PCD_AD_RESULT_CONTRL_FLOW_TYPE 0x00000000 -+#define FM_PCD_AD_RESULT_DATA_FLOW_TYPE 0x80000000 -+#define FM_PCD_AD_RESULT_PLCR_DIS 0x20000000 -+#define FM_PCD_AD_RESULT_EXTENDED_MODE 0x80000000 -+#define FM_PCD_AD_RESULT_NADEN 0x20000000 -+#define FM_PCD_AD_RESULT_STATISTICS_EN 0x40000000 -+ -+#define FM_PCD_AD_CONT_LOOKUP_TYPE 0x40000000 -+#define FM_PCD_AD_CONT_LOOKUP_LCL_MASK 0x00800000 -+ -+#define FM_PCD_AD_STATS_TYPE 0x40000000 -+#define FM_PCD_AD_STATS_FLR_ADDR_MASK 0x00FFFFFF -+#define FM_PCD_AD_STATS_COUNTERS_ADDR_MASK 0x00FFFFFF -+#define FM_PCD_AD_STATS_NEXT_ACTION_MASK 0xFFFF0000 -+#define FM_PCD_AD_STATS_NEXT_ACTION_SHIFT 12 -+#define FM_PCD_AD_STATS_NAD_EN 0x00008000 -+#define FM_PCD_AD_STATS_OP_CODE 0x00000036 -+#define FM_PCD_AD_STATS_FLR_EN 0x00004000 -+#define FM_PCD_AD_STATS_COND_EN 0x00002000 -+ -+ -+ -+#define FM_PCD_AD_BYPASS_TYPE 0xc0000000 -+ -+#define FM_PCD_AD_TYPE_MASK 0xc0000000 -+#define FM_PCD_AD_OPCODE_MASK 0x0000000f -+ -+#define FM_PCD_AD_PROFILEID_FOR_CNTRL_SHIFT 16 -+#if (DPAA_VERSION >= 11) -+#define FM_PCD_AD_RESULT_VSP_SHIFT 24 -+#define FM_PCD_AD_RESULT_NO_OM_VSPE 0x02000000 -+#define FM_PCD_AD_RESULT_VSP_MASK 0x3f -+#define FM_PCD_AD_NCSPFQIDM_MASK 0x80000000 -+#endif /* (DPAA_VERSION >= 11) */ -+ -+#define GLBL_MASK_FOR_HASH_INDEXED 0xfff00000 -+#define CC_GLBL_MASK_SIZE 4 -+#define CC_AGING_MASK_SIZE 4 -+ -+typedef uint32_t ccPrivateInfo_t; /**< private info of CC: */ -+ -+#define CC_PRIVATE_INFO_NONE 0 -+#define CC_PRIVATE_INFO_IC_HASH_INDEX_LOOKUP 0x80000000 -+#define CC_PRIVATE_INFO_IC_HASH_EXACT_MATCH 0x40000000 -+#define CC_PRIVATE_INFO_IC_KEY_EXACT_MATCH 0x20000000 -+#define CC_PRIVATE_INFO_IC_DEQ_FQID_INDEX_LOOKUP 0x10000000 -+ -+#define CC_BUILD_AGING_MASK(numOfKeys) ((((1LL << ((numOfKeys) + 1)) - 1)) << (31 - (numOfKeys))) -+/***********************************************************************/ -+/* Memory map */ -+/***********************************************************************/ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+typedef struct -+{ -+ volatile uint32_t fqid; -+ volatile uint32_t plcrProfile; -+ volatile uint32_t nia; -+ volatile uint32_t res; -+} t_AdOfTypeResult; -+ -+typedef struct -+{ -+ volatile uint32_t ccAdBase; -+ volatile uint32_t matchTblPtr; -+ volatile uint32_t pcAndOffsets; -+ volatile uint32_t gmask; -+} t_AdOfTypeContLookup; -+ -+typedef struct -+{ -+ volatile uint32_t profileTableAddr; -+ volatile uint32_t reserved; -+ volatile uint32_t nextActionIndx; -+ volatile uint32_t statsTableAddr; -+} t_AdOfTypeStats; -+ -+typedef union -+{ -+ volatile t_AdOfTypeResult adResult; -+ volatile t_AdOfTypeContLookup adContLookup; -+} t_Ad; -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+ -+/***********************************************************************/ -+/* Driver's internal structures */ -+/***********************************************************************/ -+ -+typedef struct t_FmPcdStatsObj -+{ -+ t_Handle h_StatsAd; -+ t_Handle h_StatsCounters; -+ t_List node; -+} t_FmPcdStatsObj; -+ -+typedef struct -+{ -+ uint8_t key[FM_PCD_MAX_SIZE_OF_KEY]; -+ uint8_t mask[FM_PCD_MAX_SIZE_OF_KEY]; -+ -+ t_FmPcdCcNextEngineParams nextEngineParams; -+ uint32_t requiredAction; -+ uint32_t shadowAction; -+ -+ t_FmPcdStatsObj *p_StatsObj; -+ -+} t_FmPcdCcKeyAndNextEngineParams; -+ -+typedef struct -+{ -+ t_Handle p_Ad; -+ e_FmPcdEngine fmPcdEngine; -+ bool adAllocated; -+ bool isTree; -+ -+ uint32_t myInfo; -+ t_List *h_CcNextNodesLst; -+ t_Handle h_AdditionalInfo; -+ t_Handle h_Node; -+} t_FmPcdModifyCcAdditionalParams; -+ -+typedef struct -+{ -+ t_Handle p_AdTableNew; -+ t_Handle p_KeysMatchTableNew; -+ t_Handle p_AdTableOld; -+ t_Handle p_KeysMatchTableOld; -+ uint16_t numOfKeys; -+ t_Handle h_CurrentNode; -+ uint16_t savedKeyIndex; -+ t_Handle h_NodeForAdd; -+ t_Handle h_NodeForRmv; -+ t_Handle h_ManipForRmv; -+ t_Handle h_ManipForAdd; -+ t_FmPcdStatsObj *p_StatsObjForRmv; -+#if (DPAA_VERSION >= 11) -+ t_Handle h_FrmReplicForAdd; -+ t_Handle h_FrmReplicForRmv; -+#endif /* (DPAA_VERSION >= 11) */ -+ bool tree; -+ -+ t_FmPcdCcKeyAndNextEngineParams keyAndNextEngineParams[CC_MAX_NUM_OF_KEYS]; -+} t_FmPcdModifyCcKeyAdditionalParams; -+ -+typedef struct -+{ -+ t_Handle h_Manip; -+ t_Handle h_CcNode; -+} t_CcNextEngineInfo; -+ -+typedef struct -+{ -+ uint16_t numOfKeys; -+ uint16_t maxNumOfKeys; -+ -+ bool maskSupport; -+ uint32_t keysMatchTableMaxSize; -+ -+ e_FmPcdCcStatsMode statisticsMode; -+ uint32_t numOfStatsFLRs; -+ uint32_t countersArraySize; -+ -+ bool isHashBucket; /**< Valid for match table node that is a bucket of a hash table only */ -+ t_Handle h_MissStatsCounters; /**< Valid for hash table node and match table that is a bucket; -+ Holds the statistics counters allocated by the hash table and -+ are shared by all hash table buckets; */ -+ t_Handle h_PrivMissStatsCounters; /**< Valid for match table node that is a bucket of a hash table only; -+ Holds the statistics counters that were allocated for this node -+ and replaced by the shared counters (allocated by the hash table); */ -+ bool statsEnForMiss; /**< Valid for hash table node only; TRUE is statistics are currently -+ enabled for hash 'miss', FALSE otherwise; This parameter effects the -+ returned statistics count to user, statistics AD always present for 'miss' -+ for all hash buckets; */ -+ bool glblMaskUpdated; -+ t_Handle p_GlblMask; -+ bool lclMask; -+ uint8_t parseCode; -+ uint8_t offset; -+ uint8_t prsArrayOffset; -+ bool ctrlFlow; -+ uint16_t owners; -+ -+ uint8_t ccKeySizeAccExtraction; -+ uint8_t sizeOfExtraction; -+ uint8_t glblMaskSize; -+ -+ t_Handle h_KeysMatchTable; -+ t_Handle h_AdTable; -+ t_Handle h_StatsAds; -+ t_Handle h_TmpAd; -+ t_Handle h_Ad; -+ t_Handle h_StatsFLRs; -+ -+ t_List availableStatsLst; -+ -+ t_List ccPrevNodesLst; -+ -+ t_List ccTreeIdLst; -+ t_List ccTreesLst; -+ -+ t_Handle h_FmPcd; -+ uint32_t shadowAction; -+ uint8_t userSizeOfExtraction; -+ uint8_t userOffset; -+ uint8_t kgHashShift; /* used in hash-table */ -+ -+ t_Handle h_Spinlock; -+ -+ t_FmPcdCcKeyAndNextEngineParams keyAndNextEngineParams[CC_MAX_NUM_OF_KEYS]; -+} t_FmPcdCcNode; -+ -+typedef struct -+{ -+ t_FmPcdCcNode *p_FmPcdCcNode; -+ bool occupied; -+ uint16_t owners; -+ volatile bool lock; -+} t_FmPcdCcNodeArray; -+ -+typedef struct -+{ -+ uint8_t numOfEntriesInGroup; -+ uint32_t totalBitsMask; -+ uint8_t baseGroupEntry; -+} t_FmPcdCcGroupParam; -+ -+typedef struct -+{ -+ t_Handle h_FmPcd; -+ uint8_t netEnvId; -+ uintptr_t ccTreeBaseAddr; -+ uint8_t numOfGrps; -+ t_FmPcdCcGroupParam fmPcdGroupParam[FM_PCD_MAX_NUM_OF_CC_GROUPS]; -+ t_List fmPortsLst; -+ t_FmPcdLock *p_Lock; -+ uint8_t numOfEntries; -+ uint16_t owners; -+ t_Handle h_FmPcdCcSavedManipParams; -+ bool modifiedState; -+ uint32_t requiredAction; -+ t_Handle h_IpReassemblyManip; -+ t_Handle h_CapwapReassemblyManip; -+ -+ t_FmPcdCcKeyAndNextEngineParams keyAndNextEngineParams[FM_PCD_MAX_NUM_OF_CC_GROUPS]; -+} t_FmPcdCcTree; -+ -+ -+t_Error FmPcdCcNodeTreeTryLock(t_Handle h_FmPcd,t_Handle h_FmPcdCcNode, t_List *p_List); -+void FmPcdCcNodeTreeReleaseLock(t_Handle h_FmPcd, t_List *p_List); -+t_Error FmPcdUpdateCcShadow (t_FmPcd *p_FmPcd, uint32_t size, uint32_t align); -+ -+ -+#endif /* __FM_CC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_kg.c -@@ -0,0 +1,3242 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_kg.c -+ -+ @Description FM PCD ... -+*//***************************************************************************/ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "string_ext.h" -+#include "debug_ext.h" -+#include "net_ext.h" -+#include "fm_port_ext.h" -+ -+#include "fm_common.h" -+#include "fm_pcd.h" -+#include "fm_hc.h" -+#include "fm_pcd_ipc.h" -+#include "fm_kg.h" -+#include "fsl_fman_kg.h" -+ -+ -+/****************************************/ -+/* static functions */ -+/****************************************/ -+ -+static uint32_t KgHwLock(t_Handle h_FmPcdKg) -+{ -+ ASSERT_COND(h_FmPcdKg); -+ return XX_LockIntrSpinlock(((t_FmPcdKg *)h_FmPcdKg)->h_HwSpinlock); -+} -+ -+static void KgHwUnlock(t_Handle h_FmPcdKg, uint32_t intFlags) -+{ -+ ASSERT_COND(h_FmPcdKg); -+ XX_UnlockIntrSpinlock(((t_FmPcdKg *)h_FmPcdKg)->h_HwSpinlock, intFlags); -+} -+ -+static uint32_t KgSchemeLock(t_Handle h_Scheme) -+{ -+ ASSERT_COND(h_Scheme); -+ return FmPcdLockSpinlock(((t_FmPcdKgScheme *)h_Scheme)->p_Lock); -+} -+ -+static void KgSchemeUnlock(t_Handle h_Scheme, uint32_t intFlags) -+{ -+ ASSERT_COND(h_Scheme); -+ FmPcdUnlockSpinlock(((t_FmPcdKgScheme *)h_Scheme)->p_Lock, intFlags); -+} -+ -+static bool KgSchemeFlagTryLock(t_Handle h_Scheme) -+{ -+ ASSERT_COND(h_Scheme); -+ return FmPcdLockTryLock(((t_FmPcdKgScheme *)h_Scheme)->p_Lock); -+} -+ -+static void KgSchemeFlagUnlock(t_Handle h_Scheme) -+{ -+ ASSERT_COND(h_Scheme); -+ FmPcdLockUnlock(((t_FmPcdKgScheme *)h_Scheme)->p_Lock); -+} -+ -+static t_Error WriteKgarWait(t_FmPcd *p_FmPcd, uint32_t fmkg_ar) -+{ -+ -+ struct fman_kg_regs *regs = p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs; -+ -+ if (fman_kg_write_ar_wait(regs, fmkg_ar)) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Keygen scheme access violation")); -+ -+ return E_OK; -+} -+ -+static e_FmPcdKgExtractDfltSelect GetGenericSwDefault(t_FmPcdKgExtractDflt swDefaults[], uint8_t numOfSwDefaults, uint8_t code) -+{ -+ int i; -+ -+ switch (code) -+ { -+ case (KG_SCH_GEN_PARSE_RESULT_N_FQID): -+ case (KG_SCH_GEN_DEFAULT): -+ case (KG_SCH_GEN_NEXTHDR): -+ for (i=0 ; ifmRevInfo.majorRev < 6) -+ return KG_SCH_KN_PTYPE2; -+#endif /* FM_KG_NO_IPPID_SUPPORT */ -+ return KG_SCH_KN_IPPID; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv6 index")); -+ return 0; -+ case (NET_HEADER_FIELD_IPv6_VER | NET_HEADER_FIELD_IPv6_FL | NET_HEADER_FIELD_IPv6_TC): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) || (index == e_FM_PCD_HDR_INDEX_1)) -+ return (KG_SCH_KN_IPV6FL1 | KG_SCH_KN_IPTOS_TC1); -+ if ((index == e_FM_PCD_HDR_INDEX_2) || (index == e_FM_PCD_HDR_INDEX_LAST)) -+ return (KG_SCH_KN_IPV6FL2 | KG_SCH_KN_IPTOS_TC2); -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv6 index")); -+ return 0; -+ case (NET_HEADER_FIELD_IPv6_VER | NET_HEADER_FIELD_IPv6_TC): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) || (index == e_FM_PCD_HDR_INDEX_1)) -+ return KG_SCH_KN_IPTOS_TC1; -+ if ((index == e_FM_PCD_HDR_INDEX_2) || (index == e_FM_PCD_HDR_INDEX_LAST)) -+ return KG_SCH_KN_IPTOS_TC2; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv6 index")); -+ return 0; -+ case (NET_HEADER_FIELD_IPv6_FL): -+ if ((index == e_FM_PCD_HDR_INDEX_NONE) || (index == e_FM_PCD_HDR_INDEX_1)) -+ return KG_SCH_KN_IPV6FL1; -+ if ((index == e_FM_PCD_HDR_INDEX_2) || (index == e_FM_PCD_HDR_INDEX_LAST)) -+ return KG_SCH_KN_IPV6FL2; -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal IPv6 index")); -+ return 0; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return 0; -+ } -+ case (HEADER_TYPE_GRE): -+ switch (field.gre) -+ { -+ case (NET_HEADER_FIELD_GRE_TYPE): -+ return KG_SCH_KN_GREPTYPE; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return 0; -+ } -+ case (HEADER_TYPE_MINENCAP): -+ switch (field.minencap) -+ { -+ case (NET_HEADER_FIELD_MINENCAP_SRC_IP): -+ return KG_SCH_KN_IPSRC2; -+ case (NET_HEADER_FIELD_MINENCAP_DST_IP): -+ return KG_SCH_KN_IPDST2; -+ case (NET_HEADER_FIELD_MINENCAP_TYPE): -+ return KG_SCH_KN_PTYPE2; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return 0; -+ } -+ case (HEADER_TYPE_TCP): -+ switch (field.tcp) -+ { -+ case (NET_HEADER_FIELD_TCP_PORT_SRC): -+ return KG_SCH_KN_L4PSRC; -+ case (NET_HEADER_FIELD_TCP_PORT_DST): -+ return KG_SCH_KN_L4PDST; -+ case (NET_HEADER_FIELD_TCP_FLAGS): -+ return KG_SCH_KN_TFLG; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return 0; -+ } -+ case (HEADER_TYPE_UDP): -+ switch (field.udp) -+ { -+ case (NET_HEADER_FIELD_UDP_PORT_SRC): -+ return KG_SCH_KN_L4PSRC; -+ case (NET_HEADER_FIELD_UDP_PORT_DST): -+ return KG_SCH_KN_L4PDST; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return 0; -+ } -+ case (HEADER_TYPE_IPSEC_AH): -+ switch (field.ipsecAh) -+ { -+ case (NET_HEADER_FIELD_IPSEC_AH_SPI): -+ return KG_SCH_KN_IPSEC_SPI; -+ case (NET_HEADER_FIELD_IPSEC_AH_NH): -+ return KG_SCH_KN_IPSEC_NH; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return 0; -+ } -+ case (HEADER_TYPE_IPSEC_ESP): -+ switch (field.ipsecEsp) -+ { -+ case (NET_HEADER_FIELD_IPSEC_ESP_SPI): -+ return KG_SCH_KN_IPSEC_SPI; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return 0; -+ } -+ case (HEADER_TYPE_SCTP): -+ switch (field.sctp) -+ { -+ case (NET_HEADER_FIELD_SCTP_PORT_SRC): -+ return KG_SCH_KN_L4PSRC; -+ case (NET_HEADER_FIELD_SCTP_PORT_DST): -+ return KG_SCH_KN_L4PDST; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return 0; -+ } -+ case (HEADER_TYPE_DCCP): -+ switch (field.dccp) -+ { -+ case (NET_HEADER_FIELD_DCCP_PORT_SRC): -+ return KG_SCH_KN_L4PSRC; -+ case (NET_HEADER_FIELD_DCCP_PORT_DST): -+ return KG_SCH_KN_L4PDST; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return 0; -+ } -+ case (HEADER_TYPE_PPPoE): -+ switch (field.pppoe) -+ { -+ case (NET_HEADER_FIELD_PPPoE_PID): -+ return KG_SCH_KN_PPPID; -+ case (NET_HEADER_FIELD_PPPoE_SID): -+ return KG_SCH_KN_PPPSID; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return 0; -+ } -+ default: -+ break; -+ -+ } -+ -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Extraction not supported")); -+ return 0; -+} -+ -+ -+static uint8_t GetKnownFieldId(uint32_t bitMask) -+{ -+ uint8_t cnt = 0; -+ -+ while (bitMask) -+ if (bitMask & 0x80000000) -+ break; -+ else -+ { -+ cnt++; -+ bitMask <<= 1; -+ } -+ return cnt; -+ -+} -+ -+static uint8_t GetExtractedOrMask(uint8_t bitOffset, bool fqid) -+{ -+ uint8_t i, mask, numOfOnesToClear, walking1Mask = 1; -+ -+ /* bitOffset 1-7 --> mask 0x1-0x7F */ -+ if (bitOffset<8) -+ { -+ mask = 0; -+ for (i = 0 ; i < bitOffset ; i++, walking1Mask <<= 1) -+ mask |= walking1Mask; -+ } -+ else -+ { -+ mask = 0xFF; -+ numOfOnesToClear = 0; -+ if (fqid && bitOffset>24) -+ /* bitOffset 25-31 --> mask 0xFE-0x80 */ -+ numOfOnesToClear = (uint8_t)(bitOffset-24); -+ else -+ /* bitOffset 9-15 --> mask 0xFE-0x80 */ -+ if (!fqid && bitOffset>8) -+ numOfOnesToClear = (uint8_t)(bitOffset-8); -+ for (i = 0 ; i < numOfOnesToClear ; i++, walking1Mask <<= 1) -+ mask &= ~walking1Mask; -+ /* bitOffset 8-24 for FQID, 8 for PP --> no mask (0xFF)*/ -+ } -+ return mask; -+} -+ -+static void IncSchemeOwners(t_FmPcd *p_FmPcd, t_FmPcdKgInterModuleBindPortToSchemes *p_BindPort) -+{ -+ t_FmPcdKg *p_FmPcdKg; -+ t_FmPcdKgScheme *p_Scheme; -+ uint32_t intFlags; -+ uint8_t relativeSchemeId; -+ int i; -+ -+ p_FmPcdKg = p_FmPcd->p_FmPcdKg; -+ -+ /* for each scheme - update owners counters */ -+ for (i = 0; i < p_BindPort->numOfSchemes; i++) -+ { -+ relativeSchemeId = FmPcdKgGetRelativeSchemeId(p_FmPcd, p_BindPort->schemesIds[i]); -+ ASSERT_COND(relativeSchemeId < FM_PCD_KG_NUM_OF_SCHEMES); -+ -+ p_Scheme = &p_FmPcdKg->schemes[relativeSchemeId]; -+ -+ /* increment owners number */ -+ intFlags = KgSchemeLock(p_Scheme); -+ p_Scheme->owners++; -+ KgSchemeUnlock(p_Scheme, intFlags); -+ } -+} -+ -+static void DecSchemeOwners(t_FmPcd *p_FmPcd, t_FmPcdKgInterModuleBindPortToSchemes *p_BindPort) -+{ -+ t_FmPcdKg *p_FmPcdKg; -+ t_FmPcdKgScheme *p_Scheme; -+ uint32_t intFlags; -+ uint8_t relativeSchemeId; -+ int i; -+ -+ p_FmPcdKg = p_FmPcd->p_FmPcdKg; -+ -+ /* for each scheme - update owners counters */ -+ for (i = 0; i < p_BindPort->numOfSchemes; i++) -+ { -+ relativeSchemeId = FmPcdKgGetRelativeSchemeId(p_FmPcd, p_BindPort->schemesIds[i]); -+ ASSERT_COND(relativeSchemeId < FM_PCD_KG_NUM_OF_SCHEMES); -+ -+ p_Scheme = &p_FmPcdKg->schemes[relativeSchemeId]; -+ -+ /* increment owners number */ -+ ASSERT_COND(p_Scheme->owners); -+ intFlags = KgSchemeLock(p_Scheme); -+ p_Scheme->owners--; -+ KgSchemeUnlock(p_Scheme, intFlags); -+ } -+} -+ -+static void UpdateRequiredActionFlag(t_FmPcdKgScheme *p_Scheme, bool set) -+{ -+ /* this routine is locked by the calling routine */ -+ ASSERT_COND(p_Scheme); -+ ASSERT_COND(p_Scheme->valid); -+ -+ if (set) -+ p_Scheme->requiredActionFlag = TRUE; -+ else -+ { -+ p_Scheme->requiredAction = 0; -+ p_Scheme->requiredActionFlag = FALSE; -+ } -+} -+ -+static t_Error KgWriteSp(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, uint32_t spReg, bool add) -+{ -+ struct fman_kg_regs *p_KgRegs; -+ -+ uint32_t tmpKgarReg = 0, intFlags; -+ t_Error err = E_OK; -+ -+ /* The calling routine had locked the port, so for each port only one core can access -+ * (so we don't need a lock here) */ -+ -+ if (p_FmPcd->h_Hc) -+ return FmHcKgWriteSp(p_FmPcd->h_Hc, hardwarePortId, spReg, add); -+ -+ p_KgRegs = p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs; -+ -+ tmpKgarReg = FmPcdKgBuildReadPortSchemeBindActionReg(hardwarePortId); -+ /* lock a common KG reg */ -+ intFlags = KgHwLock(p_FmPcd->p_FmPcdKg); -+ err = WriteKgarWait(p_FmPcd, tmpKgarReg); -+ if (err) -+ { -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ fman_kg_write_sp(p_KgRegs, spReg, add); -+ -+ tmpKgarReg = FmPcdKgBuildWritePortSchemeBindActionReg(hardwarePortId); -+ -+ err = WriteKgarWait(p_FmPcd, tmpKgarReg); -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+ return err; -+} -+ -+static t_Error KgWriteCpp(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, uint32_t cppReg) -+{ -+ struct fman_kg_regs *p_KgRegs; -+ uint32_t tmpKgarReg, intFlags; -+ t_Error err; -+ -+ p_KgRegs = p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs; -+ -+ if (p_FmPcd->h_Hc) -+ { -+ err = FmHcKgWriteCpp(p_FmPcd->h_Hc, hardwarePortId, cppReg); -+ return err; -+ } -+ -+ intFlags = KgHwLock(p_FmPcd->p_FmPcdKg); -+ fman_kg_write_cpp(p_KgRegs, cppReg); -+ tmpKgarReg = FmPcdKgBuildWritePortClsPlanBindActionReg(hardwarePortId); -+ err = WriteKgarWait(p_FmPcd, tmpKgarReg); -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+ -+ return err; -+} -+ -+static uint32_t BuildCppReg(t_FmPcd *p_FmPcd, uint8_t clsPlanGrpId) -+{ -+ uint32_t tmpKgpeCpp; -+ -+ tmpKgpeCpp = (uint32_t)(p_FmPcd->p_FmPcdKg->clsPlanGrps[clsPlanGrpId].baseEntry / 8); -+ tmpKgpeCpp |= (uint32_t)(((p_FmPcd->p_FmPcdKg->clsPlanGrps[clsPlanGrpId].sizeOfGrp / 8) - 1) << FM_KG_PE_CPP_MASK_SHIFT); -+ -+ return tmpKgpeCpp; -+} -+ -+static t_Error BindPortToClsPlanGrp(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, uint8_t clsPlanGrpId) -+{ -+ uint32_t tmpKgpeCpp = 0; -+ -+ tmpKgpeCpp = BuildCppReg(p_FmPcd, clsPlanGrpId); -+ return KgWriteCpp(p_FmPcd, hardwarePortId, tmpKgpeCpp); -+} -+ -+static void UnbindPortToClsPlanGrp(t_FmPcd *p_FmPcd, uint8_t hardwarePortId) -+{ -+ KgWriteCpp(p_FmPcd, hardwarePortId, 0); -+} -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+static uint32_t ReadClsPlanBlockActionReg(uint8_t grpId) -+{ -+ return (uint32_t)(FM_KG_KGAR_GO | -+ FM_KG_KGAR_READ | -+ FM_PCD_KG_KGAR_SEL_CLS_PLAN_ENTRY | -+ DUMMY_PORT_ID | -+ ((uint32_t)grpId << FM_PCD_KG_KGAR_NUM_SHIFT) | -+ FM_PCD_KG_KGAR_WSEL_MASK); -+ -+ /* if we ever want to write 1 by 1, use: -+ sel = (uint8_t)(0x01 << (7- (entryId % CLS_PLAN_NUM_PER_GRP))); -+ */ -+} -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+static void PcdKgErrorException(t_Handle h_FmPcd) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ uint32_t event,schemeIndexes = 0, index = 0; -+ struct fman_kg_regs *p_KgRegs; -+ -+ ASSERT_COND(FmIsMaster(p_FmPcd->h_Fm)); -+ p_KgRegs = p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs; -+ fman_kg_get_event(p_KgRegs, &event, &schemeIndexes); -+ -+ if (event & FM_EX_KG_DOUBLE_ECC) -+ p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC); -+ if (event & FM_EX_KG_KEYSIZE_OVERFLOW) -+ { -+ if (schemeIndexes) -+ { -+ while (schemeIndexes) -+ { -+ if (schemeIndexes & 0x1) -+ p_FmPcd->f_FmPcdIndexedException(p_FmPcd->h_App,e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW, (uint16_t)(31 - index)); -+ schemeIndexes >>= 1; -+ index+=1; -+ } -+ } -+ else /* this should happen only when interrupt is forced. */ -+ p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW); -+ } -+} -+ -+static t_Error KgInitGuest(t_FmPcd *p_FmPcd) -+{ -+ t_Error err = E_OK; -+ t_FmPcdIpcKgSchemesParams kgAlloc; -+ uint32_t replyLength; -+ t_FmPcdIpcReply reply; -+ t_FmPcdIpcMsg msg; -+ -+ ASSERT_COND(p_FmPcd->guestId != NCSW_MASTER_ID); -+ -+ /* in GUEST_PARTITION, we use the IPC */ -+ memset(&reply, 0, sizeof(reply)); -+ memset(&msg, 0, sizeof(msg)); -+ memset(&kgAlloc, 0, sizeof(t_FmPcdIpcKgSchemesParams)); -+ kgAlloc.numOfSchemes = p_FmPcd->p_FmPcdKg->numOfSchemes; -+ kgAlloc.guestId = p_FmPcd->guestId; -+ msg.msgId = FM_PCD_ALLOC_KG_SCHEMES; -+ memcpy(msg.msgBody, &kgAlloc, sizeof(kgAlloc)); -+ replyLength = sizeof(uint32_t) + p_FmPcd->p_FmPcdKg->numOfSchemes*sizeof(uint8_t); -+ if ((err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(kgAlloc), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ if (replyLength != (sizeof(uint32_t) + p_FmPcd->p_FmPcdKg->numOfSchemes*sizeof(uint8_t))) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ memcpy(p_FmPcd->p_FmPcdKg->schemesIds, (uint8_t*)(reply.replyBody),p_FmPcd->p_FmPcdKg->numOfSchemes*sizeof(uint8_t)); -+ -+ return (t_Error)reply.error; -+} -+ -+static t_Error KgInitMaster(t_FmPcd *p_FmPcd) -+{ -+ t_Error err = E_OK; -+ struct fman_kg_regs *p_Regs = p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs; -+ -+ ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID); -+ -+ if (p_FmPcd->exceptions & FM_EX_KG_DOUBLE_ECC) -+ FmEnableRamsEcc(p_FmPcd->h_Fm); -+ -+ fman_kg_init(p_Regs, p_FmPcd->exceptions, GET_NIA_BMI_AC_ENQ_FRAME(p_FmPcd)); -+ -+ /* register even if no interrupts enabled, to allow future enablement */ -+ FmRegisterIntr(p_FmPcd->h_Fm, -+ e_FM_MOD_KG, -+ 0, -+ e_FM_INTR_TYPE_ERR, -+ PcdKgErrorException, -+ p_FmPcd); -+ -+ fman_kg_enable_scheme_interrupts(p_Regs); -+ -+ if (p_FmPcd->p_FmPcdKg->numOfSchemes) -+ { -+ err = FmPcdKgAllocSchemes(p_FmPcd, -+ p_FmPcd->p_FmPcdKg->numOfSchemes, -+ p_FmPcd->guestId, -+ p_FmPcd->p_FmPcdKg->schemesIds); -+ if (err) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ return E_OK; -+} -+ -+static void ValidateSchemeSw(t_FmPcdKgScheme *p_Scheme) -+{ -+ ASSERT_COND(!p_Scheme->valid); -+ if (p_Scheme->netEnvId != ILLEGAL_NETENV) -+ FmPcdIncNetEnvOwners(p_Scheme->h_FmPcd, p_Scheme->netEnvId); -+ p_Scheme->valid = TRUE; -+} -+ -+static t_Error InvalidateSchemeSw(t_FmPcdKgScheme *p_Scheme) -+{ -+ if (p_Scheme->owners) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Trying to delete a scheme that has ports bound to")); -+ -+ if (p_Scheme->netEnvId != ILLEGAL_NETENV) -+ FmPcdDecNetEnvOwners(p_Scheme->h_FmPcd, p_Scheme->netEnvId); -+ p_Scheme->valid = FALSE; -+ -+ return E_OK; -+} -+ -+static t_Error BuildSchemeRegs(t_FmPcdKgScheme *p_Scheme, -+ t_FmPcdKgSchemeParams *p_SchemeParams, -+ struct fman_kg_scheme_regs *p_SchemeRegs) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)(p_Scheme->h_FmPcd); -+ uint32_t grpBits = 0; -+ uint8_t grpBase; -+ bool direct=TRUE, absolute=FALSE; -+ uint16_t profileId=0, numOfProfiles=0, relativeProfileId; -+ t_Error err = E_OK; -+ int i = 0; -+ t_NetEnvParams netEnvParams; -+ uint32_t tmpReg, fqbTmp = 0, ppcTmp = 0, selectTmp, maskTmp, knownTmp, genTmp; -+ t_FmPcdKgKeyExtractAndHashParams *p_KeyAndHash = NULL; -+ uint8_t j, curr, idx; -+ uint8_t id, shift=0, code=0, offset=0, size=0; -+ t_FmPcdExtractEntry *p_Extract = NULL; -+ t_FmPcdKgExtractedOrParams *p_ExtractOr; -+ bool generic = FALSE; -+ t_KnownFieldsMasks bitMask; -+ e_FmPcdKgExtractDfltSelect swDefault = (e_FmPcdKgExtractDfltSelect)0; -+ t_FmPcdKgSchemesExtracts *p_LocalExtractsArray; -+ uint8_t numOfSwDefaults = 0; -+ t_FmPcdKgExtractDflt swDefaults[NUM_OF_SW_DEFAULTS]; -+ uint8_t currGenId = 0; -+ -+ memset(swDefaults, 0, NUM_OF_SW_DEFAULTS*sizeof(t_FmPcdKgExtractDflt)); -+ memset(p_SchemeRegs, 0, sizeof(struct fman_kg_scheme_regs)); -+ -+ if (p_SchemeParams->netEnvParams.numOfDistinctionUnits > FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("numOfDistinctionUnits should not exceed %d", FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS)); -+ -+ /* by netEnv parameters, get match vector */ -+ if (!p_SchemeParams->alwaysDirect) -+ { -+ p_Scheme->netEnvId = FmPcdGetNetEnvId(p_SchemeParams->netEnvParams.h_NetEnv); -+ netEnvParams.netEnvId = p_Scheme->netEnvId; -+ netEnvParams.numOfDistinctionUnits = p_SchemeParams->netEnvParams.numOfDistinctionUnits; -+ memcpy(netEnvParams.unitIds, p_SchemeParams->netEnvParams.unitIds, (sizeof(uint8_t))*p_SchemeParams->netEnvParams.numOfDistinctionUnits); -+ err = PcdGetUnitsVector(p_FmPcd, &netEnvParams); -+ if (err) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ p_Scheme->matchVector = netEnvParams.vector; -+ } -+ else -+ { -+ p_Scheme->matchVector = SCHEME_ALWAYS_DIRECT; -+ p_Scheme->netEnvId = ILLEGAL_NETENV; -+ } -+ -+ if (p_SchemeParams->nextEngine == e_FM_PCD_INVALID) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Next Engine of the scheme is not Valid")); -+ -+ if (p_SchemeParams->bypassFqidGeneration) -+ { -+#ifdef FM_KG_NO_BYPASS_FQID_GEN -+ if ((p_FmPcd->fmRevInfo.majorRev != 4) && (p_FmPcd->fmRevInfo.majorRev < 6)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("bypassFqidGeneration.")); -+#endif /* FM_KG_NO_BYPASS_FQID_GEN */ -+ if (p_SchemeParams->baseFqid) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("baseFqid set for a scheme that does not generate an FQID")); -+ } -+ else -+ if (!p_SchemeParams->baseFqid) -+ DBG(WARNING, ("baseFqid is 0.")); -+ -+ if (p_SchemeParams->nextEngine == e_FM_PCD_PLCR) -+ { -+ direct = p_SchemeParams->kgNextEngineParams.plcrProfile.direct; -+ p_Scheme->directPlcr = direct; -+ absolute = (bool)(p_SchemeParams->kgNextEngineParams.plcrProfile.sharedProfile ? TRUE : FALSE); -+ if (!direct && absolute) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Indirect policing is not available when profile is shared.")); -+ -+ if (direct) -+ { -+ profileId = p_SchemeParams->kgNextEngineParams.plcrProfile.profileSelect.directRelativeProfileId; -+ numOfProfiles = 1; -+ } -+ else -+ { -+ profileId = p_SchemeParams->kgNextEngineParams.plcrProfile.profileSelect.indirectProfile.fqidOffsetRelativeProfileIdBase; -+ shift = p_SchemeParams->kgNextEngineParams.plcrProfile.profileSelect.indirectProfile.fqidOffsetShift; -+ numOfProfiles = p_SchemeParams->kgNextEngineParams.plcrProfile.profileSelect.indirectProfile.numOfProfiles; -+ } -+ } -+ -+ if (p_SchemeParams->nextEngine == e_FM_PCD_CC) -+ { -+#ifdef FM_KG_NO_BYPASS_PLCR_PROFILE_GEN -+ if ((p_SchemeParams->kgNextEngineParams.cc.plcrNext) && (p_SchemeParams->kgNextEngineParams.cc.bypassPlcrProfileGeneration)) -+ { -+ if ((p_FmPcd->fmRevInfo.majorRev != 4) && (p_FmPcd->fmRevInfo.majorRev < 6)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("bypassPlcrProfileGeneration.")); -+ } -+#endif /* FM_KG_NO_BYPASS_PLCR_PROFILE_GEN */ -+ -+ err = FmPcdCcGetGrpParams(p_SchemeParams->kgNextEngineParams.cc.h_CcTree, -+ p_SchemeParams->kgNextEngineParams.cc.grpId, -+ &grpBits, -+ &grpBase); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ p_Scheme->ccUnits = grpBits; -+ -+ if ((p_SchemeParams->kgNextEngineParams.cc.plcrNext) && -+ (!p_SchemeParams->kgNextEngineParams.cc.bypassPlcrProfileGeneration)) -+ { -+ if (p_SchemeParams->kgNextEngineParams.cc.plcrProfile.sharedProfile) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Shared profile may not be used after Coarse classification.")); -+ absolute = FALSE; -+ direct = p_SchemeParams->kgNextEngineParams.cc.plcrProfile.direct; -+ if (direct) -+ { -+ profileId = p_SchemeParams->kgNextEngineParams.cc.plcrProfile.profileSelect.directRelativeProfileId; -+ numOfProfiles = 1; -+ } -+ else -+ { -+ profileId = p_SchemeParams->kgNextEngineParams.cc.plcrProfile.profileSelect.indirectProfile.fqidOffsetRelativeProfileIdBase; -+ shift = p_SchemeParams->kgNextEngineParams.cc.plcrProfile.profileSelect.indirectProfile.fqidOffsetShift; -+ numOfProfiles = p_SchemeParams->kgNextEngineParams.cc.plcrProfile.profileSelect.indirectProfile.numOfProfiles; -+ } -+ } -+ } -+ -+ /* if policer is used directly after KG, or after CC */ -+ if ((p_SchemeParams->nextEngine == e_FM_PCD_PLCR) || -+ ((p_SchemeParams->nextEngine == e_FM_PCD_CC) && -+ (p_SchemeParams->kgNextEngineParams.cc.plcrNext) && -+ (!p_SchemeParams->kgNextEngineParams.cc.bypassPlcrProfileGeneration))) -+ { -+ /* if private policer profile, it may be uninitialized yet, therefore no checks are done at this stage */ -+ if (absolute) -+ { -+ /* for absolute direct policy only, */ -+ relativeProfileId = profileId; -+ err = FmPcdPlcrGetAbsoluteIdByProfileParams((t_Handle)p_FmPcd,e_FM_PCD_PLCR_SHARED,NULL, relativeProfileId, &profileId); -+ if (err) -+ RETURN_ERROR(MAJOR, err, ("Shared profile not valid offset")); -+ if (!FmPcdPlcrIsProfileValid(p_FmPcd, profileId)) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Shared profile not valid.")); -+ p_Scheme->relativeProfileId = profileId; -+ } -+ else -+ { -+ /* save relative profile id's for later check */ -+ p_Scheme->nextRelativePlcrProfile = TRUE; -+ p_Scheme->relativeProfileId = profileId; -+ p_Scheme->numOfProfiles = numOfProfiles; -+ } -+ } -+ else -+ { -+ /* if policer is NOT going to be used after KG at all than if bypassFqidGeneration -+ is set, we do not need numOfUsedExtractedOrs and hashDistributionNumOfFqids */ -+ if (p_SchemeParams->bypassFqidGeneration && p_SchemeParams->numOfUsedExtractedOrs) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("numOfUsedExtractedOrs is set in a scheme that does not generate FQID or policer profile ID")); -+ if (p_SchemeParams->bypassFqidGeneration && -+ p_SchemeParams->useHash && -+ p_SchemeParams->keyExtractAndHashParams.hashDistributionNumOfFqids) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("hashDistributionNumOfFqids is set in a scheme that does not generate FQID or policer profile ID")); -+ } -+ -+ /* configure all 21 scheme registers */ -+ tmpReg = KG_SCH_MODE_EN; -+ switch (p_SchemeParams->nextEngine) -+ { -+ case (e_FM_PCD_PLCR): -+ /* add to mode register - NIA */ -+ tmpReg |= KG_SCH_MODE_NIA_PLCR; -+ tmpReg |= NIA_ENG_PLCR; -+ tmpReg |= (uint32_t)(p_SchemeParams->kgNextEngineParams.plcrProfile.sharedProfile ? NIA_PLCR_ABSOLUTE:0); -+ /* initialize policer profile command - */ -+ /* configure kgse_ppc */ -+ if (direct) -+ /* use profileId as base, other fields are 0 */ -+ p_SchemeRegs->kgse_ppc = (uint32_t)profileId; -+ else -+ { -+ if (shift > MAX_PP_SHIFT) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fqidOffsetShift may not be larger than %d", MAX_PP_SHIFT)); -+ -+ if (!numOfProfiles || !POWER_OF_2(numOfProfiles)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numOfProfiles must not be 0 and must be a power of 2")); -+ -+ ppcTmp = ((uint32_t)shift << KG_SCH_PP_SHIFT_HIGH_SHIFT) & KG_SCH_PP_SHIFT_HIGH; -+ ppcTmp |= ((uint32_t)shift << KG_SCH_PP_SHIFT_LOW_SHIFT) & KG_SCH_PP_SHIFT_LOW; -+ ppcTmp |= ((uint32_t)(numOfProfiles-1) << KG_SCH_PP_MASK_SHIFT); -+ ppcTmp |= (uint32_t)profileId; -+ -+ p_SchemeRegs->kgse_ppc = ppcTmp; -+ } -+ break; -+ case (e_FM_PCD_CC): -+ /* mode reg - define NIA */ -+ tmpReg |= (NIA_ENG_FM_CTL | NIA_FM_CTL_AC_CC); -+ -+ p_SchemeRegs->kgse_ccbs = grpBits; -+ tmpReg |= (uint32_t)(grpBase << KG_SCH_MODE_CCOBASE_SHIFT); -+ -+ if (p_SchemeParams->kgNextEngineParams.cc.plcrNext) -+ { -+ if (!p_SchemeParams->kgNextEngineParams.cc.bypassPlcrProfileGeneration) -+ { -+ /* find out if absolute or relative */ -+ if (absolute) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("It is illegal to request a shared profile in a scheme that is in a KG->CC->PLCR flow")); -+ if (direct) -+ { -+ /* mask = 0, base = directProfileId */ -+ p_SchemeRegs->kgse_ppc = (uint32_t)profileId; -+ } -+ else -+ { -+ if (shift > MAX_PP_SHIFT) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fqidOffsetShift may not be larger than %d", MAX_PP_SHIFT)); -+ if (!numOfProfiles || !POWER_OF_2(numOfProfiles)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numOfProfiles must not be 0 and must be a power of 2")); -+ -+ ppcTmp = ((uint32_t)shift << KG_SCH_PP_SHIFT_HIGH_SHIFT) & KG_SCH_PP_SHIFT_HIGH; -+ ppcTmp |= ((uint32_t)shift << KG_SCH_PP_SHIFT_LOW_SHIFT) & KG_SCH_PP_SHIFT_LOW; -+ ppcTmp |= ((uint32_t)(numOfProfiles-1) << KG_SCH_PP_MASK_SHIFT); -+ ppcTmp |= (uint32_t)profileId; -+ -+ p_SchemeRegs->kgse_ppc = ppcTmp; -+ } -+ } -+ } -+ break; -+ case (e_FM_PCD_DONE): -+ if (p_SchemeParams->kgNextEngineParams.doneAction == e_FM_PCD_DROP_FRAME) -+ tmpReg |= GET_NIA_BMI_AC_DISCARD_FRAME(p_FmPcd); -+ else -+ tmpReg |= GET_NIA_BMI_AC_ENQ_FRAME(p_FmPcd); -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Next engine not supported")); -+ } -+ p_SchemeRegs->kgse_mode = tmpReg; -+ -+ p_SchemeRegs->kgse_mv = p_Scheme->matchVector; -+ -+#if (DPAA_VERSION >= 11) -+ if (p_SchemeParams->overrideStorageProfile) -+ { -+ p_SchemeRegs->kgse_om |= KG_SCH_OM_VSPE; -+ -+ if (p_SchemeParams->storageProfile.direct) -+ { -+ profileId = p_SchemeParams->storageProfile.profileSelect.directRelativeProfileId; -+ shift = 0; -+ numOfProfiles = 1; -+ } -+ else -+ { -+ profileId = p_SchemeParams->storageProfile.profileSelect.indirectProfile.fqidOffsetRelativeProfileIdBase; -+ shift = p_SchemeParams->storageProfile.profileSelect.indirectProfile.fqidOffsetShift; -+ numOfProfiles = p_SchemeParams->storageProfile.profileSelect.indirectProfile.numOfProfiles; -+ } -+ if (shift > MAX_SP_SHIFT) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fqidOffsetShift may not be larger than %d", MAX_SP_SHIFT)); -+ -+ if (!numOfProfiles || !POWER_OF_2(numOfProfiles)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numOfProfiles must not be 0 and must be a power of 2")); -+ -+ tmpReg = (uint32_t)shift << KG_SCH_VSP_SHIFT; -+ tmpReg |= ((uint32_t)(numOfProfiles-1) << KG_SCH_VSP_MASK_SHIFT); -+ tmpReg |= (uint32_t)profileId; -+ -+ -+ p_SchemeRegs->kgse_vsp = tmpReg; -+ -+ p_Scheme->vspe = TRUE; -+ -+ } -+ else -+ p_SchemeRegs->kgse_vsp = KG_SCH_VSP_NO_KSP_EN; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ if (p_SchemeParams->useHash) -+ { -+ p_KeyAndHash = &p_SchemeParams->keyExtractAndHashParams; -+ -+ if (p_KeyAndHash->numOfUsedExtracts >= FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numOfUsedExtracts out of range")); -+ -+ /* configure kgse_dv0 */ -+ p_SchemeRegs->kgse_dv0 = p_KeyAndHash->privateDflt0; -+ -+ /* configure kgse_dv1 */ -+ p_SchemeRegs->kgse_dv1 = p_KeyAndHash->privateDflt1; -+ -+ if (!p_SchemeParams->bypassFqidGeneration) -+ { -+ if (!p_KeyAndHash->hashDistributionNumOfFqids || !POWER_OF_2(p_KeyAndHash->hashDistributionNumOfFqids)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("hashDistributionNumOfFqids must not be 0 and must be a power of 2")); -+ if ((p_KeyAndHash->hashDistributionNumOfFqids-1) & p_SchemeParams->baseFqid) -+ DBG(WARNING, ("baseFqid unaligned. Distribution may result in less than hashDistributionNumOfFqids queues.")); -+ } -+ -+ /* configure kgse_ekdv */ -+ tmpReg = 0; -+ for ( i=0 ;inumOfUsedDflts ; i++) -+ { -+ switch (p_KeyAndHash->dflts[i].type) -+ { -+ case (e_FM_PCD_KG_MAC_ADDR): -+ tmpReg |= (p_KeyAndHash->dflts[i].dfltSelect << KG_SCH_DEF_MAC_ADDR_SHIFT); -+ break; -+ case (e_FM_PCD_KG_TCI): -+ tmpReg |= (p_KeyAndHash->dflts[i].dfltSelect << KG_SCH_DEF_TCI_SHIFT); -+ break; -+ case (e_FM_PCD_KG_ENET_TYPE): -+ tmpReg |= (p_KeyAndHash->dflts[i].dfltSelect << KG_SCH_DEF_ENET_TYPE_SHIFT); -+ break; -+ case (e_FM_PCD_KG_PPP_SESSION_ID): -+ tmpReg |= (p_KeyAndHash->dflts[i].dfltSelect << KG_SCH_DEF_PPP_SESSION_ID_SHIFT); -+ break; -+ case (e_FM_PCD_KG_PPP_PROTOCOL_ID): -+ tmpReg |= (p_KeyAndHash->dflts[i].dfltSelect << KG_SCH_DEF_PPP_PROTOCOL_ID_SHIFT); -+ break; -+ case (e_FM_PCD_KG_MPLS_LABEL): -+ tmpReg |= (p_KeyAndHash->dflts[i].dfltSelect << KG_SCH_DEF_MPLS_LABEL_SHIFT); -+ break; -+ case (e_FM_PCD_KG_IP_ADDR): -+ tmpReg |= (p_KeyAndHash->dflts[i].dfltSelect << KG_SCH_DEF_IP_ADDR_SHIFT); -+ break; -+ case (e_FM_PCD_KG_PROTOCOL_TYPE): -+ tmpReg |= (p_KeyAndHash->dflts[i].dfltSelect << KG_SCH_DEF_PROTOCOL_TYPE_SHIFT); -+ break; -+ case (e_FM_PCD_KG_IP_TOS_TC): -+ tmpReg |= (p_KeyAndHash->dflts[i].dfltSelect << KG_SCH_DEF_IP_TOS_TC_SHIFT); -+ break; -+ case (e_FM_PCD_KG_IPV6_FLOW_LABEL): -+ tmpReg |= (p_KeyAndHash->dflts[i].dfltSelect << KG_SCH_DEF_L4_PORT_SHIFT); -+ break; -+ case (e_FM_PCD_KG_IPSEC_SPI): -+ tmpReg |= (p_KeyAndHash->dflts[i].dfltSelect << KG_SCH_DEF_IPSEC_SPI_SHIFT); -+ break; -+ case (e_FM_PCD_KG_L4_PORT): -+ tmpReg |= (p_KeyAndHash->dflts[i].dfltSelect << KG_SCH_DEF_L4_PORT_SHIFT); -+ break; -+ case (e_FM_PCD_KG_TCP_FLAG): -+ tmpReg |= (p_KeyAndHash->dflts[i].dfltSelect << KG_SCH_DEF_TCP_FLAG_SHIFT); -+ break; -+ case (e_FM_PCD_KG_GENERIC_FROM_DATA): -+ swDefaults[numOfSwDefaults].type = e_FM_PCD_KG_GENERIC_FROM_DATA; -+ swDefaults[numOfSwDefaults].dfltSelect = p_KeyAndHash->dflts[i].dfltSelect; -+ numOfSwDefaults ++; -+ break; -+ case (e_FM_PCD_KG_GENERIC_FROM_DATA_NO_V): -+ swDefaults[numOfSwDefaults].type = e_FM_PCD_KG_GENERIC_FROM_DATA_NO_V; -+ swDefaults[numOfSwDefaults].dfltSelect = p_KeyAndHash->dflts[i].dfltSelect; -+ numOfSwDefaults ++; -+ break; -+ case (e_FM_PCD_KG_GENERIC_NOT_FROM_DATA): -+ swDefaults[numOfSwDefaults].type = e_FM_PCD_KG_GENERIC_NOT_FROM_DATA; -+ swDefaults[numOfSwDefaults].dfltSelect = p_KeyAndHash->dflts[i].dfltSelect; -+ numOfSwDefaults ++; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ } -+ p_SchemeRegs->kgse_ekdv = tmpReg; -+ -+ p_LocalExtractsArray = (t_FmPcdKgSchemesExtracts *)XX_Malloc(sizeof(t_FmPcdKgSchemesExtracts)); -+ if (!p_LocalExtractsArray) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("No memory")); -+ -+ /* configure kgse_ekfc and kgse_gec */ -+ knownTmp = 0; -+ for ( i=0 ;inumOfUsedExtracts ; i++) -+ { -+ p_Extract = &p_KeyAndHash->extractArray[i]; -+ switch (p_Extract->type) -+ { -+ case (e_FM_PCD_KG_EXTRACT_PORT_PRIVATE_INFO): -+ knownTmp |= KG_SCH_KN_PORT_ID; -+ /* save in driver structure */ -+ p_LocalExtractsArray->extractsArray[i].id = GetKnownFieldId(KG_SCH_KN_PORT_ID); -+ p_LocalExtractsArray->extractsArray[i].known = TRUE; -+ break; -+ case (e_FM_PCD_EXTRACT_BY_HDR): -+ switch (p_Extract->extractByHdr.hdr) -+ { -+#if (DPAA_VERSION >= 11) || ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+ case (HEADER_TYPE_UDP_LITE): -+ p_Extract->extractByHdr.hdr = HEADER_TYPE_UDP; -+ break; -+#endif /* (DPAA_VERSION >= 11) || ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+ case (HEADER_TYPE_UDP_ENCAP_ESP): -+ switch (p_Extract->extractByHdr.type) -+ { -+ case (e_FM_PCD_EXTRACT_FROM_HDR): -+ /* case where extraction from ESP only */ -+ if (p_Extract->extractByHdr.extractByHdrType.fromHdr.offset >= UDP_HEADER_SIZE) -+ { -+ p_Extract->extractByHdr.hdr = FmPcdGetAliasHdr(p_FmPcd, p_Scheme->netEnvId, HEADER_TYPE_UDP_ENCAP_ESP); -+ p_Extract->extractByHdr.extractByHdrType.fromHdr.offset -= UDP_HEADER_SIZE; -+ p_Extract->extractByHdr.ignoreProtocolValidation = TRUE; -+ } -+ else -+ { -+ p_Extract->extractByHdr.hdr = HEADER_TYPE_UDP; -+ p_Extract->extractByHdr.ignoreProtocolValidation = FALSE; -+ } -+ break; -+ case (e_FM_PCD_EXTRACT_FROM_FIELD): -+ switch (p_Extract->extractByHdr.extractByHdrType.fromField.field.udpEncapEsp) -+ { -+ case (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC): -+ case (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_DST): -+ case (NET_HEADER_FIELD_UDP_ENCAP_ESP_LEN): -+ case (NET_HEADER_FIELD_UDP_ENCAP_ESP_CKSUM): -+ p_Extract->extractByHdr.hdr = HEADER_TYPE_UDP; -+ break; -+ case (NET_HEADER_FIELD_UDP_ENCAP_ESP_SPI): -+ p_Extract->extractByHdr.type = e_FM_PCD_EXTRACT_FROM_HDR; -+ p_Extract->extractByHdr.hdr = FmPcdGetAliasHdr(p_FmPcd, p_Scheme->netEnvId, HEADER_TYPE_UDP_ENCAP_ESP); -+ /*p_Extract->extractByHdr.extractByHdrType.fromField.offset += ESP_SPI_OFFSET;*/ -+ p_Extract->extractByHdr.ignoreProtocolValidation = TRUE; -+ break; -+ case (NET_HEADER_FIELD_UDP_ENCAP_ESP_SEQUENCE_NUM): -+ p_Extract->extractByHdr.type = e_FM_PCD_EXTRACT_FROM_HDR; -+ p_Extract->extractByHdr.hdr = FmPcdGetAliasHdr(p_FmPcd, p_Scheme->netEnvId, HEADER_TYPE_UDP_ENCAP_ESP); -+ p_Extract->extractByHdr.extractByHdrType.fromField.offset += ESP_SEQ_NUM_OFFSET; -+ p_Extract->extractByHdr.ignoreProtocolValidation = TRUE; -+ break; -+ } -+ break; -+ case (e_FM_PCD_EXTRACT_FULL_FIELD): -+ switch (p_Extract->extractByHdr.extractByHdrType.fullField.udpEncapEsp) -+ { -+ case (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC): -+ case (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_DST): -+ case (NET_HEADER_FIELD_UDP_ENCAP_ESP_LEN): -+ case (NET_HEADER_FIELD_UDP_ENCAP_ESP_CKSUM): -+ p_Extract->extractByHdr.hdr = HEADER_TYPE_UDP; -+ break; -+ case (NET_HEADER_FIELD_UDP_ENCAP_ESP_SPI): -+ p_Extract->extractByHdr.type = e_FM_PCD_EXTRACT_FROM_HDR; -+ p_Extract->extractByHdr.hdr = FmPcdGetAliasHdr(p_FmPcd, p_Scheme->netEnvId, HEADER_TYPE_UDP_ENCAP_ESP); -+ p_Extract->extractByHdr.extractByHdrType.fromHdr.size = ESP_SPI_SIZE; -+ p_Extract->extractByHdr.extractByHdrType.fromHdr.offset = ESP_SPI_OFFSET; -+ p_Extract->extractByHdr.ignoreProtocolValidation = TRUE; -+ break; -+ case (NET_HEADER_FIELD_UDP_ENCAP_ESP_SEQUENCE_NUM): -+ p_Extract->extractByHdr.type = e_FM_PCD_EXTRACT_FROM_HDR; -+ p_Extract->extractByHdr.hdr = FmPcdGetAliasHdr(p_FmPcd, p_Scheme->netEnvId, HEADER_TYPE_UDP_ENCAP_ESP); -+ p_Extract->extractByHdr.extractByHdrType.fromHdr.size = ESP_SEQ_NUM_SIZE; -+ p_Extract->extractByHdr.extractByHdrType.fromHdr.offset = ESP_SEQ_NUM_OFFSET; -+ p_Extract->extractByHdr.ignoreProtocolValidation = TRUE; -+ break; -+ } -+ break; -+ } -+ break; -+ default: -+ break; -+ } -+ switch (p_Extract->extractByHdr.type) -+ { -+ case (e_FM_PCD_EXTRACT_FROM_HDR): -+ generic = TRUE; -+ /* get the header code for the generic extract */ -+ code = GetGenHdrCode(p_Extract->extractByHdr.hdr, p_Extract->extractByHdr.hdrIndex, p_Extract->extractByHdr.ignoreProtocolValidation); -+ /* set generic register fields */ -+ offset = p_Extract->extractByHdr.extractByHdrType.fromHdr.offset; -+ size = p_Extract->extractByHdr.extractByHdrType.fromHdr.size; -+ break; -+ case (e_FM_PCD_EXTRACT_FROM_FIELD): -+ generic = TRUE; -+ /* get the field code for the generic extract */ -+ code = GetGenFieldCode(p_Extract->extractByHdr.hdr, -+ p_Extract->extractByHdr.extractByHdrType.fromField.field, p_Extract->extractByHdr.ignoreProtocolValidation,p_Extract->extractByHdr.hdrIndex); -+ offset = p_Extract->extractByHdr.extractByHdrType.fromField.offset; -+ size = p_Extract->extractByHdr.extractByHdrType.fromField.size; -+ break; -+ case (e_FM_PCD_EXTRACT_FULL_FIELD): -+ if (!p_Extract->extractByHdr.ignoreProtocolValidation) -+ { -+ /* if we have a known field for it - use it, otherwise use generic */ -+ bitMask = GetKnownProtMask(p_FmPcd, p_Extract->extractByHdr.hdr, p_Extract->extractByHdr.hdrIndex, -+ p_Extract->extractByHdr.extractByHdrType.fullField); -+ if (bitMask) -+ { -+ knownTmp |= bitMask; -+ /* save in driver structure */ -+ p_LocalExtractsArray->extractsArray[i].id = GetKnownFieldId(bitMask); -+ p_LocalExtractsArray->extractsArray[i].known = TRUE; -+ } -+ else -+ generic = TRUE; -+ } -+ else -+ generic = TRUE; -+ if (generic) -+ { -+ /* tmp - till we cover more headers under generic */ -+ XX_Free(p_LocalExtractsArray); -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Full header selection not supported")); -+ } -+ break; -+ default: -+ XX_Free(p_LocalExtractsArray); -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ break; -+ case (e_FM_PCD_EXTRACT_NON_HDR): -+ /* use generic */ -+ generic = TRUE; -+ offset = 0; -+ /* get the field code for the generic extract */ -+ code = GetGenCode(p_Extract->extractNonHdr.src, &offset); -+ offset += p_Extract->extractNonHdr.offset; -+ size = p_Extract->extractNonHdr.size; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ -+ if (generic) -+ { -+ /* set generic register fields */ -+ if (currGenId >= FM_KG_NUM_OF_GENERIC_REGS) -+ { -+ XX_Free(p_LocalExtractsArray); -+ RETURN_ERROR(MAJOR, E_FULL, ("Generic registers are fully used")); -+ } -+ if (!code) -+ { -+ XX_Free(p_LocalExtractsArray); -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, NO_MSG); -+ } -+ -+ genTmp = KG_SCH_GEN_VALID; -+ genTmp |= (uint32_t)(code << KG_SCH_GEN_HT_SHIFT); -+ genTmp |= offset; -+ if ((size > MAX_KG_SCH_SIZE) || (size < 1)) -+ { -+ XX_Free(p_LocalExtractsArray); -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Illegal extraction (size out of range)")); -+ } -+ genTmp |= (uint32_t)((size - 1) << KG_SCH_GEN_SIZE_SHIFT); -+ swDefault = GetGenericSwDefault(swDefaults, numOfSwDefaults, code); -+ if (swDefault == e_FM_PCD_KG_DFLT_ILLEGAL) -+ DBG(WARNING, ("No sw default configured")); -+ else -+ genTmp |= swDefault << KG_SCH_GEN_DEF_SHIFT; -+ -+ genTmp |= KG_SCH_GEN_MASK; -+ p_SchemeRegs->kgse_gec[currGenId] = genTmp; -+ /* save in driver structure */ -+ p_LocalExtractsArray->extractsArray[i].id = currGenId++; -+ p_LocalExtractsArray->extractsArray[i].known = FALSE; -+ generic = FALSE; -+ } -+ } -+ p_SchemeRegs->kgse_ekfc = knownTmp; -+ -+ selectTmp = 0; -+ maskTmp = 0xFFFFFFFF; -+ /* configure kgse_bmch, kgse_bmcl and kgse_fqb */ -+ -+ if (p_KeyAndHash->numOfUsedMasks > FM_PCD_KG_NUM_OF_EXTRACT_MASKS) -+ { -+ XX_Free(p_LocalExtractsArray); -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Only %d masks supported", FM_PCD_KG_NUM_OF_EXTRACT_MASKS)); -+ } -+ for ( i=0 ;inumOfUsedMasks ; i++) -+ { -+ /* Get the relative id of the extract (for known 0-0x1f, for generic 0-7) */ -+ id = p_LocalExtractsArray->extractsArray[p_KeyAndHash->masks[i].extractArrayIndex].id; -+ /* Get the shift of the select field (depending on i) */ -+ GET_MASK_SEL_SHIFT(shift,i); -+ if (p_LocalExtractsArray->extractsArray[p_KeyAndHash->masks[i].extractArrayIndex].known) -+ selectTmp |= id << shift; -+ else -+ selectTmp |= (id + MASK_FOR_GENERIC_BASE_ID) << shift; -+ -+ /* Get the shift of the offset field (depending on i) - may -+ be in kgse_bmch or in kgse_fqb (depending on i) */ -+ GET_MASK_OFFSET_SHIFT(shift,i); -+ if (i<=1) -+ selectTmp |= p_KeyAndHash->masks[i].offset << shift; -+ else -+ fqbTmp |= p_KeyAndHash->masks[i].offset << shift; -+ -+ /* Get the shift of the mask field (depending on i) */ -+ GET_MASK_SHIFT(shift,i); -+ /* pass all bits */ -+ maskTmp |= KG_SCH_BITMASK_MASK << shift; -+ /* clear bits that need masking */ -+ maskTmp &= ~(0xFF << shift) ; -+ /* set mask bits */ -+ maskTmp |= (p_KeyAndHash->masks[i].mask << shift) ; -+ } -+ p_SchemeRegs->kgse_bmch = selectTmp; -+ p_SchemeRegs->kgse_bmcl = maskTmp; -+ /* kgse_fqb will be written t the end of the routine */ -+ -+ /* configure kgse_hc */ -+ if (p_KeyAndHash->hashShift > MAX_HASH_SHIFT) -+ { -+ XX_Free(p_LocalExtractsArray); -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("hashShift must not be larger than %d", MAX_HASH_SHIFT)); -+ } -+ if (p_KeyAndHash->hashDistributionFqidsShift > MAX_DIST_FQID_SHIFT) -+ { -+ XX_Free(p_LocalExtractsArray); -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("hashDistributionFqidsShift must not be larger than %d", MAX_DIST_FQID_SHIFT)); -+ } -+ -+ tmpReg = 0; -+ -+ tmpReg |= ((p_KeyAndHash->hashDistributionNumOfFqids - 1) << p_KeyAndHash->hashDistributionFqidsShift); -+ tmpReg |= p_KeyAndHash->hashShift << KG_SCH_HASH_CONFIG_SHIFT_SHIFT; -+ -+ if (p_KeyAndHash->symmetricHash) -+ { -+ if ((!!(p_SchemeRegs->kgse_ekfc & KG_SCH_KN_MACSRC) != !!(p_SchemeRegs->kgse_ekfc & KG_SCH_KN_MACDST)) || -+ (!!(p_SchemeRegs->kgse_ekfc & KG_SCH_KN_IPSRC1) != !!(p_SchemeRegs->kgse_ekfc & KG_SCH_KN_IPDST1)) || -+ (!!(p_SchemeRegs->kgse_ekfc & KG_SCH_KN_IPSRC2) != !!(p_SchemeRegs->kgse_ekfc & KG_SCH_KN_IPDST2)) || -+ (!!(p_SchemeRegs->kgse_ekfc & KG_SCH_KN_L4PSRC) != !!(p_SchemeRegs->kgse_ekfc & KG_SCH_KN_L4PDST))) -+ { -+ XX_Free(p_LocalExtractsArray); -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("symmetricHash set but src/dest extractions missing")); -+ } -+ tmpReg |= KG_SCH_HASH_CONFIG_SYM; -+ } -+ p_SchemeRegs->kgse_hc = tmpReg; -+ -+ /* build the return array describing the order of the extractions */ -+ -+ /* the last currGenId places of the array -+ are for generic extracts that are always last. -+ We now sort for the calculation of the order of the known -+ extractions we sort the known extracts between orderedArray[0] and -+ orderedArray[p_KeyAndHash->numOfUsedExtracts - currGenId - 1]. -+ for the calculation of the order of the generic extractions we use: -+ num_of_generic - currGenId -+ num_of_known - p_KeyAndHash->numOfUsedExtracts - currGenId -+ first_generic_index = num_of_known */ -+ curr = 0; -+ for (i=0;inumOfUsedExtracts ; i++) -+ { -+ if (p_LocalExtractsArray->extractsArray[i].known) -+ { -+ ASSERT_COND(curr<(p_KeyAndHash->numOfUsedExtracts - currGenId)); -+ j = curr; -+ /* id is the extract id (port id = 0, mac src = 1 etc.). the value in the array is the original -+ index in the user's extractions array */ -+ /* we compare the id of the current extract with the id of the extract in the orderedArray[j-1] -+ location */ -+ while ((j > 0) && (p_LocalExtractsArray->extractsArray[i].id < -+ p_LocalExtractsArray->extractsArray[p_Scheme->orderedArray[j-1]].id)) -+ { -+ p_Scheme->orderedArray[j] = -+ p_Scheme->orderedArray[j-1]; -+ j--; -+ } -+ p_Scheme->orderedArray[j] = (uint8_t)i; -+ curr++; -+ } -+ else -+ { -+ /* index is first_generic_index + generic index (id) */ -+ idx = (uint8_t)(p_KeyAndHash->numOfUsedExtracts - currGenId + p_LocalExtractsArray->extractsArray[i].id); -+ ASSERT_COND(idx < FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY); -+ p_Scheme->orderedArray[idx]= (uint8_t)i; -+ } -+ } -+ XX_Free(p_LocalExtractsArray); -+ } -+ else -+ { -+ /* clear all unused registers: */ -+ p_SchemeRegs->kgse_ekfc = 0; -+ p_SchemeRegs->kgse_ekdv = 0; -+ p_SchemeRegs->kgse_bmch = 0; -+ p_SchemeRegs->kgse_bmcl = 0; -+ p_SchemeRegs->kgse_hc = 0; -+ p_SchemeRegs->kgse_dv0 = 0; -+ p_SchemeRegs->kgse_dv1 = 0; -+ } -+ -+ if (p_SchemeParams->bypassFqidGeneration) -+ p_SchemeRegs->kgse_hc |= KG_SCH_HASH_CONFIG_NO_FQID; -+ -+ /* configure kgse_spc */ -+ if ( p_SchemeParams->schemeCounter.update) -+ p_SchemeRegs->kgse_spc = p_SchemeParams->schemeCounter.value; -+ -+ -+ /* check that are enough generic registers */ -+ if (p_SchemeParams->numOfUsedExtractedOrs + currGenId > FM_KG_NUM_OF_GENERIC_REGS) -+ RETURN_ERROR(MAJOR, E_FULL, ("Generic registers are fully used")); -+ -+ /* extracted OR mask on Qid */ -+ for ( i=0 ;inumOfUsedExtractedOrs ; i++) -+ { -+ -+ p_Scheme->extractedOrs = TRUE; -+ /* configure kgse_gec[i] */ -+ p_ExtractOr = &p_SchemeParams->extractedOrs[i]; -+ switch (p_ExtractOr->type) -+ { -+ case (e_FM_PCD_KG_EXTRACT_PORT_PRIVATE_INFO): -+ code = KG_SCH_GEN_PARSE_RESULT_N_FQID; -+ offset = 0; -+ break; -+ case (e_FM_PCD_EXTRACT_BY_HDR): -+ /* get the header code for the generic extract */ -+ code = GetGenHdrCode(p_ExtractOr->extractByHdr.hdr, p_ExtractOr->extractByHdr.hdrIndex, p_ExtractOr->extractByHdr.ignoreProtocolValidation); -+ /* set generic register fields */ -+ offset = p_ExtractOr->extractionOffset; -+ break; -+ case (e_FM_PCD_EXTRACT_NON_HDR): -+ /* get the field code for the generic extract */ -+ offset = 0; -+ code = GetGenCode(p_ExtractOr->src, &offset); -+ offset += p_ExtractOr->extractionOffset; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ -+ /* set generic register fields */ -+ if (!code) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, NO_MSG); -+ genTmp = KG_SCH_GEN_EXTRACT_TYPE | KG_SCH_GEN_VALID; -+ genTmp |= (uint32_t)(code << KG_SCH_GEN_HT_SHIFT); -+ genTmp |= offset; -+ if (!!p_ExtractOr->bitOffsetInFqid == !!p_ExtractOr->bitOffsetInPlcrProfile) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, (" extracted byte must effect either FQID or Policer profile")); -+ -+ /************************************************************************************ -+ bitOffsetInFqid and bitOffsetInPolicerProfile are translated to rotate parameter -+ in the following way: -+ -+ Driver API and implementation: -+ ============================== -+ FQID: extracted OR byte may be shifted right 1-31 bits to effect parts of the FQID. -+ if shifted less than 8 bits, or more than 24 bits a mask is set on the bits that -+ are not overlapping FQID. -+ ------------------------ -+ | FQID (24) | -+ ------------------------ -+ -------- -+ | | extracted OR byte -+ -------- -+ -+ Policer Profile: extracted OR byte may be shifted right 1-15 bits to effect parts of the -+ PP id. Unless shifted exactly 8 bits to overlap the PP id, a mask is set on the bits that -+ are not overlapping PP id. -+ -+ -------- -+ | PP (8) | -+ -------- -+ -------- -+ | | extracted OR byte -+ -------- -+ -+ HW implementation -+ ================= -+ FQID and PP construct a 32 bit word in the way describe below. Extracted byte is located -+ as the highest byte of that word and may be rotated to effect any part os the FQID or -+ the PP. -+ ------------------------ -------- -+ | FQID (24) || PP (8) | -+ ------------------------ -------- -+ -------- -+ | | extracted OR byte -+ -------- -+ -+ ************************************************************************************/ -+ -+ if (p_ExtractOr->bitOffsetInFqid) -+ { -+ if (p_ExtractOr->bitOffsetInFqid > MAX_KG_SCH_FQID_BIT_OFFSET ) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal extraction (bitOffsetInFqid out of range)")); -+ if (p_ExtractOr->bitOffsetInFqid<8) -+ genTmp |= (uint32_t)((p_ExtractOr->bitOffsetInFqid+24) << KG_SCH_GEN_SIZE_SHIFT); -+ else -+ genTmp |= (uint32_t)((p_ExtractOr->bitOffsetInFqid-8) << KG_SCH_GEN_SIZE_SHIFT); -+ p_ExtractOr->mask &= GetExtractedOrMask(p_ExtractOr->bitOffsetInFqid, TRUE); -+ } -+ else /* effect policer profile */ -+ { -+ if (p_ExtractOr->bitOffsetInPlcrProfile > MAX_KG_SCH_PP_BIT_OFFSET ) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal extraction (bitOffsetInPlcrProfile out of range)")); -+ p_Scheme->bitOffsetInPlcrProfile = p_ExtractOr->bitOffsetInPlcrProfile; -+ genTmp |= (uint32_t)((p_ExtractOr->bitOffsetInPlcrProfile+16) << KG_SCH_GEN_SIZE_SHIFT); -+ p_ExtractOr->mask &= GetExtractedOrMask(p_ExtractOr->bitOffsetInPlcrProfile, FALSE); -+ } -+ -+ genTmp |= (uint32_t)(p_ExtractOr->extractionOffset << KG_SCH_GEN_DEF_SHIFT); -+ /* clear bits that need masking */ -+ genTmp &= ~KG_SCH_GEN_MASK ; -+ /* set mask bits */ -+ genTmp |= (uint32_t)(p_ExtractOr->mask << KG_SCH_GEN_MASK_SHIFT); -+ p_SchemeRegs->kgse_gec[currGenId++] = genTmp; -+ -+ } -+ /* clear all unused GEC registers */ -+ for ( i=currGenId ;ikgse_gec[i] = 0; -+ -+ /* add base Qid for this scheme */ -+ /* add configuration for kgse_fqb */ -+ if (p_SchemeParams->baseFqid & ~0x00FFFFFF) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("baseFqid must be between 1 and 2^24-1")); -+ -+ fqbTmp |= p_SchemeParams->baseFqid; -+ p_SchemeRegs->kgse_fqb = fqbTmp; -+ -+ p_Scheme->nextEngine = p_SchemeParams->nextEngine; -+ p_Scheme->doneAction = p_SchemeParams->kgNextEngineParams.doneAction; -+ -+ return E_OK; -+} -+ -+ -+/*****************************************************************************/ -+/* Inter-module API routines */ -+/*****************************************************************************/ -+ -+t_Error FmPcdKgBuildClsPlanGrp(t_Handle h_FmPcd, t_FmPcdKgInterModuleClsPlanGrpParams *p_Grp, t_FmPcdKgInterModuleClsPlanSet *p_ClsPlanSet) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_FmPcdKgClsPlanGrp *p_ClsPlanGrp; -+ t_FmPcdIpcKgClsPlanParams kgAlloc; -+ t_Error err = E_OK; -+ uint32_t oredVectors = 0; -+ int i, j; -+ -+ /* this routine is protected by the calling routine ! */ -+ if (p_Grp->numOfOptions >= FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE,("Too many classification plan basic options selected.")); -+ -+ /* find a new clsPlan group */ -+ for (i = 0; i < FM_MAX_NUM_OF_PORTS; i++) -+ if (!p_FmPcd->p_FmPcdKg->clsPlanGrps[i].used) -+ break; -+ if (i == FM_MAX_NUM_OF_PORTS) -+ RETURN_ERROR(MAJOR, E_FULL,("No classification plan groups available.")); -+ -+ p_FmPcd->p_FmPcdKg->clsPlanGrps[i].used = TRUE; -+ -+ p_Grp->clsPlanGrpId = (uint8_t)i; -+ -+ if (p_Grp->numOfOptions == 0) -+ p_FmPcd->p_FmPcdKg->emptyClsPlanGrpId = (uint8_t)i; -+ -+ p_ClsPlanGrp = &p_FmPcd->p_FmPcdKg->clsPlanGrps[i]; -+ p_ClsPlanGrp->netEnvId = p_Grp->netEnvId; -+ p_ClsPlanGrp->owners = 0; -+ FmPcdSetClsPlanGrpId(p_FmPcd, p_Grp->netEnvId, p_Grp->clsPlanGrpId); -+ if (p_Grp->numOfOptions != 0) -+ FmPcdIncNetEnvOwners(p_FmPcd, p_Grp->netEnvId); -+ -+ p_ClsPlanGrp->sizeOfGrp = (uint16_t)(1 << p_Grp->numOfOptions); -+ /* a minimal group of 8 is required */ -+ if (p_ClsPlanGrp->sizeOfGrp < CLS_PLAN_NUM_PER_GRP) -+ p_ClsPlanGrp->sizeOfGrp = CLS_PLAN_NUM_PER_GRP; -+ if (p_FmPcd->guestId == NCSW_MASTER_ID) -+ { -+ err = KgAllocClsPlanEntries(h_FmPcd, p_ClsPlanGrp->sizeOfGrp, p_FmPcd->guestId, &p_ClsPlanGrp->baseEntry); -+ -+ if (err) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, NO_MSG); -+ } -+ else -+ { -+ t_FmPcdIpcMsg msg; -+ uint32_t replyLength; -+ t_FmPcdIpcReply reply; -+ -+ /* in GUEST_PARTITION, we use the IPC, to also set a private driver group if required */ -+ memset(&reply, 0, sizeof(reply)); -+ memset(&msg, 0, sizeof(msg)); -+ memset(&kgAlloc, 0, sizeof(kgAlloc)); -+ kgAlloc.guestId = p_FmPcd->guestId; -+ kgAlloc.numOfClsPlanEntries = p_ClsPlanGrp->sizeOfGrp; -+ msg.msgId = FM_PCD_ALLOC_KG_CLSPLAN; -+ memcpy(msg.msgBody, &kgAlloc, sizeof(kgAlloc)); -+ replyLength = (sizeof(uint32_t) + sizeof(p_ClsPlanGrp->baseEntry)); -+ if ((err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(kgAlloc), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (replyLength != (sizeof(uint32_t) + sizeof(p_ClsPlanGrp->baseEntry))) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ if ((t_Error)reply.error != E_OK) -+ RETURN_ERROR(MINOR, (t_Error)reply.error, NO_MSG); -+ -+ p_ClsPlanGrp->baseEntry = *(uint8_t*)(reply.replyBody); -+ } -+ -+ /* build classification plan entries parameters */ -+ p_ClsPlanSet->baseEntry = p_ClsPlanGrp->baseEntry; -+ p_ClsPlanSet->numOfClsPlanEntries = p_ClsPlanGrp->sizeOfGrp; -+ -+ oredVectors = 0; -+ for (i = 0; inumOfOptions; i++) -+ { -+ oredVectors |= p_Grp->optVectors[i]; -+ /* save an array of used options - the indexes represent the power of 2 index */ -+ p_ClsPlanGrp->optArray[i] = p_Grp->options[i]; -+ } -+ /* set the classification plan relevant entries so that all bits -+ * relevant to the list of options is cleared -+ */ -+ for (j = 0; jsizeOfGrp; j++) -+ p_ClsPlanSet->vectors[j] = ~oredVectors; -+ -+ for (i = 0; inumOfOptions; i++) -+ { -+ /* option i got the place 2^i in the clsPlan array. all entries that -+ * have bit i set, should have the vector bit cleared. So each option -+ * has one location that it is exclusive (1,2,4,8...) and represent the -+ * presence of that option only, and other locations that represent a -+ * combination of options. -+ * e.g: -+ * If ethernet-BC is option 1 it gets entry 2 in the table. Entry 2 -+ * now represents a frame with ethernet-BC header - so the bit -+ * representing ethernet-BC should be set and all other option bits -+ * should be cleared. -+ * Entries 2,3,6,7,10... also have ethernet-BC and therefore have bit -+ * vector[1] set, but they also have other bits set: -+ * 3=1+2, options 0 and 1 -+ * 6=2+4, options 1 and 2 -+ * 7=1+2+4, options 0,1,and 2 -+ * 10=2+8, options 1 and 3 -+ * etc. -+ * */ -+ -+ /* now for each option (i), we set their bits in all entries (j) -+ * that contain bit 2^i. -+ */ -+ for (j = 0; jsizeOfGrp; j++) -+ { -+ if (j & (1<vectors[j] |= p_Grp->optVectors[i]; -+ } -+ } -+ -+ return E_OK; -+} -+ -+void FmPcdKgDestroyClsPlanGrp(t_Handle h_FmPcd, uint8_t grpId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_FmPcdIpcKgClsPlanParams kgAlloc; -+ t_Error err; -+ t_FmPcdIpcMsg msg; -+ uint32_t replyLength; -+ t_FmPcdIpcReply reply; -+ -+ /* check that no port is bound to this clsPlan */ -+ if (p_FmPcd->p_FmPcdKg->clsPlanGrps[grpId].owners) -+ { -+ REPORT_ERROR(MINOR, E_INVALID_STATE, ("Trying to delete a clsPlan grp that has ports bound to")); -+ return; -+ } -+ -+ FmPcdSetClsPlanGrpId(p_FmPcd, p_FmPcd->p_FmPcdKg->clsPlanGrps[grpId].netEnvId, ILLEGAL_CLS_PLAN); -+ -+ if (grpId == p_FmPcd->p_FmPcdKg->emptyClsPlanGrpId) -+ p_FmPcd->p_FmPcdKg->emptyClsPlanGrpId = ILLEGAL_CLS_PLAN; -+ else -+ FmPcdDecNetEnvOwners(p_FmPcd, p_FmPcd->p_FmPcdKg->clsPlanGrps[grpId].netEnvId); -+ -+ /* free blocks */ -+ if (p_FmPcd->guestId == NCSW_MASTER_ID) -+ KgFreeClsPlanEntries(h_FmPcd, -+ p_FmPcd->p_FmPcdKg->clsPlanGrps[grpId].sizeOfGrp, -+ p_FmPcd->guestId, -+ p_FmPcd->p_FmPcdKg->clsPlanGrps[grpId].baseEntry); -+ else /* in GUEST_PARTITION, we use the IPC, to also set a private driver group if required */ -+ { -+ memset(&reply, 0, sizeof(reply)); -+ memset(&msg, 0, sizeof(msg)); -+ kgAlloc.guestId = p_FmPcd->guestId; -+ kgAlloc.numOfClsPlanEntries = p_FmPcd->p_FmPcdKg->clsPlanGrps[grpId].sizeOfGrp; -+ kgAlloc.clsPlanBase = p_FmPcd->p_FmPcdKg->clsPlanGrps[grpId].baseEntry; -+ msg.msgId = FM_PCD_FREE_KG_CLSPLAN; -+ memcpy(msg.msgBody, &kgAlloc, sizeof(kgAlloc)); -+ replyLength = sizeof(uint32_t); -+ err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(kgAlloc), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ { -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ return; -+ } -+ if (replyLength != sizeof(uint32_t)) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ return; -+ } -+ if ((t_Error)reply.error != E_OK) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Free KG clsPlan failed")); -+ return; -+ } -+ } -+ -+ /* clear clsPlan driver structure */ -+ memset(&p_FmPcd->p_FmPcdKg->clsPlanGrps[grpId], 0, sizeof(t_FmPcdKgClsPlanGrp)); -+} -+ -+t_Error FmPcdKgBuildBindPortToSchemes(t_Handle h_FmPcd, t_FmPcdKgInterModuleBindPortToSchemes *p_BindPort, uint32_t *p_SpReg, bool add) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint32_t j, schemesPerPortVector = 0; -+ t_FmPcdKgScheme *p_Scheme; -+ uint8_t i, relativeSchemeId; -+ uint32_t tmp, walking1Mask; -+ uint8_t swPortIndex = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdKg, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE); -+ -+ /* for each scheme */ -+ for (i = 0; inumOfSchemes; i++) -+ { -+ relativeSchemeId = FmPcdKgGetRelativeSchemeId(p_FmPcd, p_BindPort->schemesIds[i]); -+ if (relativeSchemeId >= FM_PCD_KG_NUM_OF_SCHEMES) -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG); -+ -+ if (add) -+ { -+ p_Scheme = &p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId]; -+ if (!FmPcdKgIsSchemeValidSw(p_Scheme)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Requested scheme is invalid.")); -+ /* check netEnvId of the port against the scheme netEnvId */ -+ if ((p_Scheme->netEnvId != p_BindPort->netEnvId) && (p_Scheme->netEnvId != ILLEGAL_NETENV)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Port may not be bound to requested scheme - differ in netEnvId")); -+ -+ /* if next engine is private port policer profile, we need to check that it is valid */ -+ HW_PORT_ID_TO_SW_PORT_INDX(swPortIndex, p_BindPort->hardwarePortId); -+ if (p_Scheme->nextRelativePlcrProfile) -+ { -+ for (j = 0;jnumOfProfiles;j++) -+ { -+ ASSERT_COND(p_FmPcd->p_FmPcdPlcr->portsMapping[swPortIndex].h_FmPort); -+ if (p_Scheme->relativeProfileId+j >= p_FmPcd->p_FmPcdPlcr->portsMapping[swPortIndex].numOfProfiles) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Relative profile not in range")); -+ if (!FmPcdPlcrIsProfileValid(p_FmPcd, (uint16_t)(p_FmPcd->p_FmPcdPlcr->portsMapping[swPortIndex].profilesBase + p_Scheme->relativeProfileId + j))) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Relative profile not valid.")); -+ } -+ } -+ if (!p_BindPort->useClsPlan) -+ { -+ /* This check may be redundant as port is a assigned to the whole NetEnv */ -+ -+ /* if this port does not use clsPlan, it may not be bound to schemes with units that contain -+ cls plan options. Schemes that are used only directly, should not be checked. -+ it also may not be bound to schemes that go to CC with units that are options - so we OR -+ the match vector and the grpBits (= ccUnits) */ -+ if ((p_Scheme->matchVector != SCHEME_ALWAYS_DIRECT) || p_Scheme->ccUnits) -+ { -+ uint8_t netEnvId; -+ walking1Mask = 0x80000000; -+ netEnvId = (p_Scheme->netEnvId == ILLEGAL_NETENV)? p_BindPort->netEnvId:p_Scheme->netEnvId; -+ tmp = (p_Scheme->matchVector == SCHEME_ALWAYS_DIRECT)? 0:p_Scheme->matchVector; -+ tmp |= p_Scheme->ccUnits; -+ while (tmp) -+ { -+ if (tmp & walking1Mask) -+ { -+ tmp &= ~walking1Mask; -+ if (!PcdNetEnvIsUnitWithoutOpts(p_FmPcd, netEnvId, walking1Mask)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Port (without clsPlan) may not be bound to requested scheme - uses clsPlan options")); -+ } -+ walking1Mask >>= 1; -+ } -+ } -+ } -+ } -+ /* build vector */ -+ schemesPerPortVector |= 1 << (31 - p_BindPort->schemesIds[i]); -+ } -+ -+ *p_SpReg = schemesPerPortVector; -+ -+ return E_OK; -+} -+ -+t_Error FmPcdKgBindPortToSchemes(t_Handle h_FmPcd , t_FmPcdKgInterModuleBindPortToSchemes *p_SchemeBind) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint32_t spReg; -+ t_Error err = E_OK; -+ -+ err = FmPcdKgBuildBindPortToSchemes(h_FmPcd, p_SchemeBind, &spReg, TRUE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ err = KgWriteSp(p_FmPcd, p_SchemeBind->hardwarePortId, spReg, TRUE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ IncSchemeOwners(p_FmPcd, p_SchemeBind); -+ -+ return E_OK; -+} -+ -+t_Error FmPcdKgUnbindPortToSchemes(t_Handle h_FmPcd, t_FmPcdKgInterModuleBindPortToSchemes *p_SchemeBind) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint32_t spReg; -+ t_Error err = E_OK; -+ -+ err = FmPcdKgBuildBindPortToSchemes(p_FmPcd, p_SchemeBind, &spReg, FALSE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ err = KgWriteSp(p_FmPcd, p_SchemeBind->hardwarePortId, spReg, FALSE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ DecSchemeOwners(p_FmPcd, p_SchemeBind); -+ -+ return E_OK; -+} -+ -+bool FmPcdKgIsSchemeValidSw(t_Handle h_Scheme) -+{ -+ t_FmPcdKgScheme *p_Scheme = (t_FmPcdKgScheme*)h_Scheme; -+ -+ return p_Scheme->valid; -+} -+ -+bool KgIsSchemeAlwaysDirect(t_Handle h_FmPcd, uint8_t schemeId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ if (p_FmPcd->p_FmPcdKg->schemes[schemeId].matchVector == SCHEME_ALWAYS_DIRECT) -+ return TRUE; -+ else -+ return FALSE; -+} -+ -+t_Error FmPcdKgAllocSchemes(t_Handle h_FmPcd, uint8_t numOfSchemes, uint8_t guestId, uint8_t *p_SchemesIds) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ uint8_t i, j; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdKg, E_INVALID_HANDLE); -+ -+ /* This routine is issued only on master core of master partition - -+ either directly or through IPC, so no need for lock */ -+ -+ for (j = 0, i = 0; i < FM_PCD_KG_NUM_OF_SCHEMES && j < numOfSchemes; i++) -+ { -+ if (!p_FmPcd->p_FmPcdKg->schemesMng[i].allocated) -+ { -+ p_FmPcd->p_FmPcdKg->schemesMng[i].allocated = TRUE; -+ p_FmPcd->p_FmPcdKg->schemesMng[i].ownerId = guestId; -+ p_SchemesIds[j] = i; -+ j++; -+ } -+ } -+ -+ if (j != numOfSchemes) -+ { -+ /* roll back */ -+ for (j--; j; j--) -+ { -+ p_FmPcd->p_FmPcdKg->schemesMng[p_SchemesIds[j]].allocated = FALSE; -+ p_FmPcd->p_FmPcdKg->schemesMng[p_SchemesIds[j]].ownerId = 0; -+ p_SchemesIds[j] = 0; -+ } -+ -+ RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, ("No schemes found")); -+ } -+ -+ return E_OK; -+} -+ -+t_Error FmPcdKgFreeSchemes(t_Handle h_FmPcd, uint8_t numOfSchemes, uint8_t guestId, uint8_t *p_SchemesIds) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ uint8_t i; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdKg, E_INVALID_HANDLE); -+ -+ /* This routine is issued only on master core of master partition - -+ either directly or through IPC */ -+ -+ for (i = 0; i < numOfSchemes; i++) -+ { -+ if (!p_FmPcd->p_FmPcdKg->schemesMng[p_SchemesIds[i]].allocated) -+ { -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Scheme was not previously allocated")); -+ } -+ if (p_FmPcd->p_FmPcdKg->schemesMng[p_SchemesIds[i]].ownerId != guestId) -+ { -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Scheme is not owned by caller. ")); -+ } -+ p_FmPcd->p_FmPcdKg->schemesMng[p_SchemesIds[i]].allocated = FALSE; -+ p_FmPcd->p_FmPcdKg->schemesMng[p_SchemesIds[i]].ownerId = 0; -+ } -+ -+ return E_OK; -+} -+ -+t_Error KgAllocClsPlanEntries(t_Handle h_FmPcd, uint16_t numOfClsPlanEntries, uint8_t guestId, uint8_t *p_First) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ uint8_t numOfBlocks, blocksFound=0, first=0; -+ uint8_t i, j; -+ -+ /* This routine is issued only on master core of master partition - -+ either directly or through IPC, so no need for lock */ -+ -+ if (!numOfClsPlanEntries) -+ return E_OK; -+ -+ if ((numOfClsPlanEntries % CLS_PLAN_NUM_PER_GRP) || (!POWER_OF_2(numOfClsPlanEntries))) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numOfClsPlanEntries must be a power of 2 and divisible by 8")); -+ -+ numOfBlocks = (uint8_t)(numOfClsPlanEntries/CLS_PLAN_NUM_PER_GRP); -+ -+ /* try to find consequent blocks */ -+ first = 0; -+ for (i = 0; i < FM_PCD_MAX_NUM_OF_CLS_PLANS/CLS_PLAN_NUM_PER_GRP;) -+ { -+ if (!p_FmPcd->p_FmPcdKg->clsPlanBlocksMng[i].allocated) -+ { -+ blocksFound++; -+ i++; -+ if (blocksFound == numOfBlocks) -+ break; -+ } -+ else -+ { -+ blocksFound = 0; -+ /* advance i to the next aligned address */ -+ first = i = (uint8_t)(first + numOfBlocks); -+ } -+ } -+ -+ if (blocksFound == numOfBlocks) -+ { -+ *p_First = (uint8_t)(first * CLS_PLAN_NUM_PER_GRP); -+ for (j = first; j < (first + numOfBlocks); j++) -+ { -+ p_FmPcd->p_FmPcdKg->clsPlanBlocksMng[j].allocated = TRUE; -+ p_FmPcd->p_FmPcdKg->clsPlanBlocksMng[j].ownerId = guestId; -+ } -+ return E_OK; -+ } -+ else -+ RETURN_ERROR(MINOR, E_FULL, ("No resources for clsPlan")); -+} -+ -+void KgFreeClsPlanEntries(t_Handle h_FmPcd, uint16_t numOfClsPlanEntries, uint8_t guestId, uint8_t base) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint8_t numOfBlocks; -+ uint8_t i, baseBlock; -+ -+#ifdef DISABLE_ASSERTIONS -+UNUSED(guestId); -+#endif /* DISABLE_ASSERTIONS */ -+ -+ /* This routine is issued only on master core of master partition - -+ either directly or through IPC, so no need for lock */ -+ -+ numOfBlocks = (uint8_t)(numOfClsPlanEntries/CLS_PLAN_NUM_PER_GRP); -+ ASSERT_COND(!(base%CLS_PLAN_NUM_PER_GRP)); -+ -+ baseBlock = (uint8_t)(base/CLS_PLAN_NUM_PER_GRP); -+ for (i=baseBlock;ip_FmPcdKg->clsPlanBlocksMng[i].allocated); -+ ASSERT_COND(guestId == p_FmPcd->p_FmPcdKg->clsPlanBlocksMng[i].ownerId); -+ p_FmPcd->p_FmPcdKg->clsPlanBlocksMng[i].allocated = FALSE; -+ p_FmPcd->p_FmPcdKg->clsPlanBlocksMng[i].ownerId = 0; -+ } -+} -+ -+void KgEnable(t_FmPcd *p_FmPcd) -+{ -+ struct fman_kg_regs *p_Regs = p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs; -+ -+ ASSERT_COND(FmIsMaster(p_FmPcd->h_Fm)); -+ fman_kg_enable(p_Regs); -+} -+ -+void KgDisable(t_FmPcd *p_FmPcd) -+{ -+ struct fman_kg_regs *p_Regs = p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs; -+ -+ ASSERT_COND(FmIsMaster(p_FmPcd->h_Fm)); -+ fman_kg_disable(p_Regs); -+} -+ -+void KgSetClsPlan(t_Handle h_FmPcd, t_FmPcdKgInterModuleClsPlanSet *p_Set) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ struct fman_kg_cp_regs *p_FmPcdKgPortRegs; -+ uint32_t tmpKgarReg = 0, intFlags; -+ uint16_t i, j; -+ -+ /* This routine is protected by the calling routine ! */ -+ ASSERT_COND(FmIsMaster(p_FmPcd->h_Fm)); -+ p_FmPcdKgPortRegs = &p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->clsPlanRegs; -+ -+ intFlags = KgHwLock(p_FmPcd->p_FmPcdKg); -+ for (i=p_Set->baseEntry;ibaseEntry+p_Set->numOfClsPlanEntries;i+=8) -+ { -+ tmpKgarReg = FmPcdKgBuildWriteClsPlanBlockActionReg((uint8_t)(i / CLS_PLAN_NUM_PER_GRP)); -+ -+ for (j = i; j < i+8; j++) -+ { -+ ASSERT_COND(IN_RANGE(0, (j - p_Set->baseEntry), FM_PCD_MAX_NUM_OF_CLS_PLANS-1)); -+ WRITE_UINT32(p_FmPcdKgPortRegs->kgcpe[j % CLS_PLAN_NUM_PER_GRP],p_Set->vectors[j - p_Set->baseEntry]); -+ } -+ -+ if (WriteKgarWait(p_FmPcd, tmpKgarReg) != E_OK) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("WriteKgarWait FAILED")); -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+ return; -+ } -+ } -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+} -+ -+t_Handle KgConfig( t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams) -+{ -+ t_FmPcdKg *p_FmPcdKg; -+ -+ UNUSED(p_FmPcd); -+ -+ if (p_FmPcdParams->numOfSchemes > FM_PCD_KG_NUM_OF_SCHEMES) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("numOfSchemes should not exceed %d", FM_PCD_KG_NUM_OF_SCHEMES)); -+ return NULL; -+ } -+ -+ p_FmPcdKg = (t_FmPcdKg *)XX_Malloc(sizeof(t_FmPcdKg)); -+ if (!p_FmPcdKg) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM Keygen allocation FAILED")); -+ return NULL; -+ } -+ memset(p_FmPcdKg, 0, sizeof(t_FmPcdKg)); -+ -+ -+ if (FmIsMaster(p_FmPcd->h_Fm)) -+ { -+ p_FmPcdKg->p_FmPcdKgRegs = (struct fman_kg_regs *)UINT_TO_PTR(FmGetPcdKgBaseAddr(p_FmPcdParams->h_Fm)); -+ p_FmPcd->exceptions |= DEFAULT_fmPcdKgErrorExceptions; -+ p_FmPcdKg->p_IndirectAccessRegs = (u_FmPcdKgIndirectAccessRegs *)&p_FmPcdKg->p_FmPcdKgRegs->fmkg_indirect[0]; -+ } -+ -+ p_FmPcdKg->numOfSchemes = p_FmPcdParams->numOfSchemes; -+ if ((p_FmPcd->guestId == NCSW_MASTER_ID) && !p_FmPcdKg->numOfSchemes) -+ { -+ p_FmPcdKg->numOfSchemes = FM_PCD_KG_NUM_OF_SCHEMES; -+ DBG(WARNING, ("numOfSchemes was defined 0 by user, re-defined by driver to FM_PCD_KG_NUM_OF_SCHEMES")); -+ } -+ -+ p_FmPcdKg->emptyClsPlanGrpId = ILLEGAL_CLS_PLAN; -+ -+ return p_FmPcdKg; -+} -+ -+t_Error KgInit(t_FmPcd *p_FmPcd) -+{ -+ t_Error err = E_OK; -+ -+ p_FmPcd->p_FmPcdKg->h_HwSpinlock = XX_InitSpinlock(); -+ if (!p_FmPcd->p_FmPcdKg->h_HwSpinlock) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FM KG HW spinlock")); -+ -+ if (p_FmPcd->guestId == NCSW_MASTER_ID) -+ err = KgInitMaster(p_FmPcd); -+ else -+ err = KgInitGuest(p_FmPcd); -+ -+ if (err != E_OK) -+ { -+ if (p_FmPcd->p_FmPcdKg->h_HwSpinlock) -+ XX_FreeSpinlock(p_FmPcd->p_FmPcdKg->h_HwSpinlock); -+ } -+ -+ return err; -+} -+ -+t_Error KgFree(t_FmPcd *p_FmPcd) -+{ -+ t_FmPcdIpcKgSchemesParams kgAlloc; -+ t_Error err = E_OK; -+ t_FmPcdIpcMsg msg; -+ uint32_t replyLength; -+ t_FmPcdIpcReply reply; -+ -+ FmUnregisterIntr(p_FmPcd->h_Fm, e_FM_MOD_KG, 0, e_FM_INTR_TYPE_ERR); -+ -+ if (p_FmPcd->guestId == NCSW_MASTER_ID) -+ { -+ err = FmPcdKgFreeSchemes(p_FmPcd, -+ p_FmPcd->p_FmPcdKg->numOfSchemes, -+ p_FmPcd->guestId, -+ p_FmPcd->p_FmPcdKg->schemesIds); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (p_FmPcd->p_FmPcdKg->h_HwSpinlock) -+ XX_FreeSpinlock(p_FmPcd->p_FmPcdKg->h_HwSpinlock); -+ -+ return E_OK; -+ } -+ -+ /* guest */ -+ memset(&reply, 0, sizeof(reply)); -+ memset(&msg, 0, sizeof(msg)); -+ kgAlloc.numOfSchemes = p_FmPcd->p_FmPcdKg->numOfSchemes; -+ kgAlloc.guestId = p_FmPcd->guestId; -+ ASSERT_COND(kgAlloc.numOfSchemes < FM_PCD_KG_NUM_OF_SCHEMES); -+ memcpy(kgAlloc.schemesIds, p_FmPcd->p_FmPcdKg->schemesIds, (sizeof(uint8_t))*kgAlloc.numOfSchemes); -+ msg.msgId = FM_PCD_FREE_KG_SCHEMES; -+ memcpy(msg.msgBody, &kgAlloc, sizeof(kgAlloc)); -+ replyLength = sizeof(uint32_t); -+ if ((err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(kgAlloc), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ if (replyLength != sizeof(uint32_t)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ -+ if (p_FmPcd->p_FmPcdKg->h_HwSpinlock) -+ XX_FreeSpinlock(p_FmPcd->p_FmPcdKg->h_HwSpinlock); -+ -+ return (t_Error)reply.error; -+} -+ -+t_Error FmPcdKgSetOrBindToClsPlanGrp(t_Handle h_FmPcd, uint8_t hardwarePortId, uint8_t netEnvId, protocolOpt_t *p_OptArray, uint8_t *p_ClsPlanGrpId, bool *p_IsEmptyClsPlanGrp) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ t_FmPcdKgInterModuleClsPlanGrpParams grpParams, *p_GrpParams; -+ t_FmPcdKgClsPlanGrp *p_ClsPlanGrp; -+ t_FmPcdKgInterModuleClsPlanSet *p_ClsPlanSet; -+ t_Error err; -+ -+ /* This function is issued only from FM_PORT_SetPcd which locked all PCD modules, -+ so no need for lock here */ -+ -+ memset(&grpParams, 0, sizeof(grpParams)); -+ grpParams.clsPlanGrpId = ILLEGAL_CLS_PLAN; -+ p_GrpParams = &grpParams; -+ -+ p_GrpParams->netEnvId = netEnvId; -+ -+ /* Get from the NetEnv the information of the clsPlan (can be already created, -+ * or needs to build) */ -+ err = PcdGetClsPlanGrpParams(h_FmPcd, p_GrpParams); -+ if (err) -+ RETURN_ERROR(MINOR,err,NO_MSG); -+ -+ if (p_GrpParams->grpExists) -+ { -+ /* this group was already updated (at least) in SW */ -+ *p_ClsPlanGrpId = p_GrpParams->clsPlanGrpId; -+ } -+ else -+ { -+ p_ClsPlanSet = (t_FmPcdKgInterModuleClsPlanSet *)XX_Malloc(sizeof(t_FmPcdKgInterModuleClsPlanSet)); -+ if (!p_ClsPlanSet) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Classification plan set")); -+ memset(p_ClsPlanSet, 0, sizeof(t_FmPcdKgInterModuleClsPlanSet)); -+ /* Build (in SW) the clsPlan parameters, including the vectors to be written to HW */ -+ err = FmPcdKgBuildClsPlanGrp(h_FmPcd, p_GrpParams, p_ClsPlanSet); -+ if (err) -+ { -+ XX_Free(p_ClsPlanSet); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ *p_ClsPlanGrpId = p_GrpParams->clsPlanGrpId; -+ -+ if (p_FmPcd->h_Hc) -+ { -+ /* write clsPlan entries to memory */ -+ err = FmHcPcdKgSetClsPlan(p_FmPcd->h_Hc, p_ClsPlanSet); -+ if (err) -+ { -+ XX_Free(p_ClsPlanSet); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ } -+ else -+ /* write clsPlan entries to memory */ -+ KgSetClsPlan(p_FmPcd, p_ClsPlanSet); -+ -+ XX_Free(p_ClsPlanSet); -+ } -+ -+ /* Set caller parameters */ -+ -+ /* mark if this is an empty classification group */ -+ if (*p_ClsPlanGrpId == p_FmPcd->p_FmPcdKg->emptyClsPlanGrpId) -+ *p_IsEmptyClsPlanGrp = TRUE; -+ else -+ *p_IsEmptyClsPlanGrp = FALSE; -+ -+ p_ClsPlanGrp = &p_FmPcd->p_FmPcdKg->clsPlanGrps[*p_ClsPlanGrpId]; -+ -+ /* increment owners number */ -+ p_ClsPlanGrp->owners++; -+ -+ /* copy options array for port */ -+ memcpy(p_OptArray, &p_FmPcd->p_FmPcdKg->clsPlanGrps[*p_ClsPlanGrpId].optArray, FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)*sizeof(protocolOpt_t)); -+ -+ /* bind port to the new or existing group */ -+ err = BindPortToClsPlanGrp(p_FmPcd, hardwarePortId, p_GrpParams->clsPlanGrpId); -+ if (err) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Error FmPcdKgDeleteOrUnbindPortToClsPlanGrp(t_Handle h_FmPcd, uint8_t hardwarePortId, uint8_t clsPlanGrpId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ t_FmPcdKgClsPlanGrp *p_ClsPlanGrp = &p_FmPcd->p_FmPcdKg->clsPlanGrps[clsPlanGrpId]; -+ t_FmPcdKgInterModuleClsPlanSet *p_ClsPlanSet; -+ t_Error err; -+ -+ /* This function is issued only from FM_PORT_DeletePcd which locked all PCD modules, -+ so no need for lock here */ -+ -+ UnbindPortToClsPlanGrp(p_FmPcd, hardwarePortId); -+ -+ /* decrement owners number */ -+ ASSERT_COND(p_ClsPlanGrp->owners); -+ p_ClsPlanGrp->owners--; -+ -+ if (!p_ClsPlanGrp->owners) -+ { -+ if (p_FmPcd->h_Hc) -+ { -+ err = FmHcPcdKgDeleteClsPlan(p_FmPcd->h_Hc, clsPlanGrpId); -+ return err; -+ } -+ else -+ { -+ /* clear clsPlan entries in memory */ -+ p_ClsPlanSet = (t_FmPcdKgInterModuleClsPlanSet *)XX_Malloc(sizeof(t_FmPcdKgInterModuleClsPlanSet)); -+ if (!p_ClsPlanSet) -+ { -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Classification plan set")); -+ } -+ memset(p_ClsPlanSet, 0, sizeof(t_FmPcdKgInterModuleClsPlanSet)); -+ -+ p_ClsPlanSet->baseEntry = p_FmPcd->p_FmPcdKg->clsPlanGrps[clsPlanGrpId].baseEntry; -+ p_ClsPlanSet->numOfClsPlanEntries = p_FmPcd->p_FmPcdKg->clsPlanGrps[clsPlanGrpId].sizeOfGrp; -+ KgSetClsPlan(p_FmPcd, p_ClsPlanSet); -+ XX_Free(p_ClsPlanSet); -+ -+ FmPcdKgDestroyClsPlanGrp(h_FmPcd, clsPlanGrpId); -+ } -+ } -+ return E_OK; -+} -+ -+uint32_t FmPcdKgGetRequiredAction(t_Handle h_FmPcd, uint8_t schemeId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ ASSERT_COND(p_FmPcd->p_FmPcdKg->schemes[schemeId].valid); -+ -+ return p_FmPcd->p_FmPcdKg->schemes[schemeId].requiredAction; -+} -+ -+uint32_t FmPcdKgGetRequiredActionFlag(t_Handle h_FmPcd, uint8_t schemeId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ ASSERT_COND(p_FmPcd->p_FmPcdKg->schemes[schemeId].valid); -+ -+ return p_FmPcd->p_FmPcdKg->schemes[schemeId].requiredActionFlag; -+} -+ -+bool FmPcdKgIsDirectPlcr(t_Handle h_FmPcd, uint8_t schemeId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ ASSERT_COND(p_FmPcd->p_FmPcdKg->schemes[schemeId].valid); -+ -+ return p_FmPcd->p_FmPcdKg->schemes[schemeId].directPlcr; -+} -+ -+ -+uint16_t FmPcdKgGetRelativeProfileId(t_Handle h_FmPcd, uint8_t schemeId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ ASSERT_COND(p_FmPcd->p_FmPcdKg->schemes[schemeId].valid); -+ -+ return p_FmPcd->p_FmPcdKg->schemes[schemeId].relativeProfileId; -+} -+ -+bool FmPcdKgIsDistrOnPlcrProfile(t_Handle h_FmPcd, uint8_t schemeId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ ASSERT_COND(p_FmPcd->p_FmPcdKg->schemes[schemeId].valid); -+ -+ if ((p_FmPcd->p_FmPcdKg->schemes[schemeId].extractedOrs && -+ p_FmPcd->p_FmPcdKg->schemes[schemeId].bitOffsetInPlcrProfile) || -+ p_FmPcd->p_FmPcdKg->schemes[schemeId].nextRelativePlcrProfile) -+ return TRUE; -+ else -+ return FALSE; -+ -+} -+ -+e_FmPcdEngine FmPcdKgGetNextEngine(t_Handle h_FmPcd, uint8_t relativeSchemeId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ ASSERT_COND(p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId].valid); -+ -+ return p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId].nextEngine; -+} -+ -+e_FmPcdDoneAction FmPcdKgGetDoneAction(t_Handle h_FmPcd, uint8_t schemeId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ ASSERT_COND(p_FmPcd->p_FmPcdKg->schemes[schemeId].valid); -+ -+ return p_FmPcd->p_FmPcdKg->schemes[schemeId].doneAction; -+} -+ -+void FmPcdKgUpdateRequiredAction(t_Handle h_Scheme, uint32_t requiredAction) -+{ -+ t_FmPcdKgScheme *p_Scheme = (t_FmPcdKgScheme *)h_Scheme; -+ -+ /* this routine is protected by calling routine */ -+ -+ ASSERT_COND(p_Scheme->valid); -+ -+ p_Scheme->requiredAction |= requiredAction; -+} -+ -+bool FmPcdKgHwSchemeIsValid(uint32_t schemeModeReg) -+{ -+ return (bool)!!(schemeModeReg & KG_SCH_MODE_EN); -+} -+ -+uint32_t FmPcdKgBuildWriteSchemeActionReg(uint8_t schemeId, bool updateCounter) -+{ -+ return (uint32_t)(((uint32_t)schemeId << FM_PCD_KG_KGAR_NUM_SHIFT) | -+ FM_KG_KGAR_GO | -+ FM_KG_KGAR_WRITE | -+ FM_KG_KGAR_SEL_SCHEME_ENTRY | -+ DUMMY_PORT_ID | -+ (updateCounter ? FM_KG_KGAR_SCM_WSEL_UPDATE_CNT:0)); -+} -+ -+uint32_t FmPcdKgBuildReadSchemeActionReg(uint8_t schemeId) -+{ -+ return (uint32_t)(((uint32_t)schemeId << FM_PCD_KG_KGAR_NUM_SHIFT) | -+ FM_KG_KGAR_GO | -+ FM_KG_KGAR_READ | -+ FM_KG_KGAR_SEL_SCHEME_ENTRY | -+ DUMMY_PORT_ID | -+ FM_KG_KGAR_SCM_WSEL_UPDATE_CNT); -+ -+} -+ -+uint32_t FmPcdKgBuildWriteClsPlanBlockActionReg(uint8_t grpId) -+{ -+ return (uint32_t)(FM_KG_KGAR_GO | -+ FM_KG_KGAR_WRITE | -+ FM_PCD_KG_KGAR_SEL_CLS_PLAN_ENTRY | -+ DUMMY_PORT_ID | -+ ((uint32_t)grpId << FM_PCD_KG_KGAR_NUM_SHIFT) | -+ FM_PCD_KG_KGAR_WSEL_MASK); -+ -+ /* if we ever want to write 1 by 1, use: -+ sel = (uint8_t)(0x01 << (7- (entryId % CLS_PLAN_NUM_PER_GRP))); -+ */ -+} -+ -+uint32_t FmPcdKgBuildWritePortSchemeBindActionReg(uint8_t hardwarePortId) -+{ -+ -+ return (uint32_t)(FM_KG_KGAR_GO | -+ FM_KG_KGAR_WRITE | -+ FM_PCD_KG_KGAR_SEL_PORT_ENTRY | -+ hardwarePortId | -+ FM_PCD_KG_KGAR_SEL_PORT_WSEL_SP); -+} -+ -+uint32_t FmPcdKgBuildReadPortSchemeBindActionReg(uint8_t hardwarePortId) -+{ -+ -+ return (uint32_t)(FM_KG_KGAR_GO | -+ FM_KG_KGAR_READ | -+ FM_PCD_KG_KGAR_SEL_PORT_ENTRY | -+ hardwarePortId | -+ FM_PCD_KG_KGAR_SEL_PORT_WSEL_SP); -+} -+ -+uint32_t FmPcdKgBuildWritePortClsPlanBindActionReg(uint8_t hardwarePortId) -+{ -+ -+ return (uint32_t)(FM_KG_KGAR_GO | -+ FM_KG_KGAR_WRITE | -+ FM_PCD_KG_KGAR_SEL_PORT_ENTRY | -+ hardwarePortId | -+ FM_PCD_KG_KGAR_SEL_PORT_WSEL_CPP); -+} -+ -+uint8_t FmPcdKgGetClsPlanGrpBase(t_Handle h_FmPcd, uint8_t clsPlanGrp) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ return p_FmPcd->p_FmPcdKg->clsPlanGrps[clsPlanGrp].baseEntry; -+} -+ -+uint16_t FmPcdKgGetClsPlanGrpSize(t_Handle h_FmPcd, uint8_t clsPlanGrp) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ return p_FmPcd->p_FmPcdKg->clsPlanGrps[clsPlanGrp].sizeOfGrp; -+} -+ -+ -+uint8_t FmPcdKgGetSchemeId(t_Handle h_Scheme) -+{ -+ return ((t_FmPcdKgScheme*)h_Scheme)->schemeId; -+ -+} -+ -+#if (DPAA_VERSION >= 11) -+bool FmPcdKgGetVspe(t_Handle h_Scheme) -+{ -+ return ((t_FmPcdKgScheme*)h_Scheme)->vspe; -+ -+} -+#endif /* (DPAA_VERSION >= 11) */ -+ -+uint8_t FmPcdKgGetRelativeSchemeId(t_Handle h_FmPcd, uint8_t schemeId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint8_t i; -+ -+ for (i = 0;ip_FmPcdKg->numOfSchemes;i++) -+ if (p_FmPcd->p_FmPcdKg->schemesIds[i] == schemeId) -+ return i; -+ -+ if (i == p_FmPcd->p_FmPcdKg->numOfSchemes) -+ REPORT_ERROR(MAJOR, E_NOT_IN_RANGE, ("Scheme is out of partition range")); -+ -+ return FM_PCD_KG_NUM_OF_SCHEMES; -+} -+ -+t_Handle FmPcdKgGetSchemeHandle(t_Handle h_FmPcd, uint8_t relativeSchemeId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ ASSERT_COND(p_FmPcd); -+ -+ /* check that schemeId is in range */ -+ if (relativeSchemeId >= p_FmPcd->p_FmPcdKg->numOfSchemes) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_IN_RANGE, ("relative-scheme-id %d!", relativeSchemeId)); -+ return NULL; -+ } -+ -+ if (!FmPcdKgIsSchemeValidSw(&p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId])) -+ return NULL; -+ -+ return &p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId]; -+} -+ -+bool FmPcdKgIsSchemeHasOwners(t_Handle h_Scheme) -+{ -+ return (((t_FmPcdKgScheme*)h_Scheme)->owners == 0)?FALSE:TRUE; -+} -+ -+t_Error FmPcdKgCcGetSetParams(t_Handle h_FmPcd, t_Handle h_Scheme, uint32_t requiredAction, uint32_t value) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint8_t relativeSchemeId, physicalSchemeId; -+ uint32_t tmpKgarReg, tmpReg32 = 0, intFlags; -+ t_Error err; -+ t_FmPcdKgScheme *p_Scheme = (t_FmPcdKgScheme*)h_Scheme; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_VALUE(p_FmPcd->p_FmPcdKg, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_VALUE(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE, 0); -+ -+ /* Calling function locked all PCD modules, so no need to lock here */ -+ -+ if (!FmPcdKgIsSchemeValidSw(h_Scheme)) -+ RETURN_ERROR(MAJOR, E_ALREADY_EXISTS, ("Scheme is Invalid")); -+ -+ if (p_FmPcd->h_Hc) -+ { -+ err = FmHcPcdKgCcGetSetParams(p_FmPcd->h_Hc, h_Scheme, requiredAction, value); -+ -+ UpdateRequiredActionFlag(h_Scheme,TRUE); -+ FmPcdKgUpdateRequiredAction(h_Scheme,requiredAction); -+ return err; -+ } -+ -+ physicalSchemeId = p_Scheme->schemeId; -+ -+ relativeSchemeId = FmPcdKgGetRelativeSchemeId(p_FmPcd, physicalSchemeId); -+ if (relativeSchemeId >= FM_PCD_KG_NUM_OF_SCHEMES) -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG); -+ -+ if (!p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId].requiredActionFlag || -+ !(p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId].requiredAction & requiredAction)) -+ { -+ if (requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA) -+ { -+ switch (p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId].nextEngine) -+ { -+ case (e_FM_PCD_DONE): -+ if (p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId].doneAction == e_FM_PCD_ENQ_FRAME) -+ { -+ tmpKgarReg = FmPcdKgBuildReadSchemeActionReg(physicalSchemeId); -+ intFlags = KgHwLock(p_FmPcd->p_FmPcdKg); -+ WriteKgarWait(p_FmPcd, tmpKgarReg); -+ tmpReg32 = GET_UINT32(p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->schemeRegs.kgse_mode); -+ ASSERT_COND(tmpReg32 & (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME)); -+ WRITE_UINT32(p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->schemeRegs.kgse_mode, tmpReg32 | NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA); -+ /* call indirect command for scheme write */ -+ tmpKgarReg = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, FALSE); -+ WriteKgarWait(p_FmPcd, tmpKgarReg); -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+ } -+ break; -+ case (e_FM_PCD_PLCR): -+ if (!p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId].directPlcr || -+ (p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId].extractedOrs && -+ p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId].bitOffsetInPlcrProfile) || -+ p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId].nextRelativePlcrProfile) -+ { -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("In this situation PP can not be with distribution and has to be shared")); -+ } -+ err = FmPcdPlcrCcGetSetParams(h_FmPcd, p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId].relativeProfileId, requiredAction); -+ if (err) -+ { -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE,("in this situation the next engine after scheme can be or PLCR or ENQ_FRAME")); -+ } -+ } -+ if (requiredAction & UPDATE_KG_NIA_CC_WA) -+ { -+ if (p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId].nextEngine == e_FM_PCD_CC) -+ { -+ tmpKgarReg = FmPcdKgBuildReadSchemeActionReg(physicalSchemeId); -+ intFlags = KgHwLock(p_FmPcd->p_FmPcdKg); -+ WriteKgarWait(p_FmPcd, tmpKgarReg); -+ tmpReg32 = GET_UINT32(p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->schemeRegs.kgse_mode); -+ ASSERT_COND(tmpReg32 & (NIA_ENG_FM_CTL | NIA_FM_CTL_AC_CC)); -+ tmpReg32 &= ~NIA_FM_CTL_AC_CC; -+ WRITE_UINT32(p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->schemeRegs.kgse_mode, tmpReg32 | NIA_FM_CTL_AC_PRE_CC); -+ /* call indirect command for scheme write */ -+ tmpKgarReg = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, FALSE); -+ WriteKgarWait(p_FmPcd, tmpKgarReg); -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+ } -+ } -+ if (requiredAction & UPDATE_KG_OPT_MODE) -+ { -+ tmpKgarReg = FmPcdKgBuildReadSchemeActionReg(physicalSchemeId); -+ intFlags = KgHwLock(p_FmPcd->p_FmPcdKg); -+ WriteKgarWait(p_FmPcd, tmpKgarReg); -+ WRITE_UINT32(p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->schemeRegs.kgse_om, value); -+ /* call indirect command for scheme write */ -+ tmpKgarReg = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, FALSE); -+ WriteKgarWait(p_FmPcd, tmpKgarReg); -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+ } -+ if (requiredAction & UPDATE_KG_NIA) -+ { -+ tmpKgarReg = FmPcdKgBuildReadSchemeActionReg(physicalSchemeId); -+ intFlags = KgHwLock(p_FmPcd->p_FmPcdKg); -+ WriteKgarWait(p_FmPcd, tmpKgarReg); -+ tmpReg32 = GET_UINT32(p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->schemeRegs.kgse_mode); -+ tmpReg32 &= ~(NIA_ENG_MASK | NIA_AC_MASK); -+ tmpReg32 |= value; -+ WRITE_UINT32(p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->schemeRegs.kgse_mode, tmpReg32); -+ /* call indirect command for scheme write */ -+ tmpKgarReg = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, FALSE); -+ WriteKgarWait(p_FmPcd, tmpKgarReg); -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+ } -+ } -+ -+ UpdateRequiredActionFlag(h_Scheme, TRUE); -+ FmPcdKgUpdateRequiredAction(h_Scheme, requiredAction); -+ -+ return E_OK; -+} -+/*********************** End of inter-module routines ************************/ -+ -+ -+/****************************************/ -+/* API routines */ -+/****************************************/ -+ -+t_Handle FM_PCD_KgSchemeSet(t_Handle h_FmPcd, t_FmPcdKgSchemeParams *p_SchemeParams) -+{ -+ t_FmPcd *p_FmPcd; -+ struct fman_kg_scheme_regs schemeRegs; -+ struct fman_kg_scheme_regs *p_MemRegs; -+ uint8_t i; -+ t_Error err = E_OK; -+ uint32_t tmpKgarReg; -+ uint32_t intFlags; -+ uint8_t physicalSchemeId, relativeSchemeId = 0; -+ t_FmPcdKgScheme *p_Scheme; -+ -+ if (p_SchemeParams->modify) -+ { -+ p_Scheme = (t_FmPcdKgScheme *)p_SchemeParams->id.h_Scheme; -+ p_FmPcd = p_Scheme->h_FmPcd; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPcd, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(p_FmPcd->p_FmPcdKg, E_INVALID_HANDLE, NULL); -+ -+ if (!FmPcdKgIsSchemeValidSw(p_Scheme)) -+ { -+ REPORT_ERROR(MAJOR, E_ALREADY_EXISTS, -+ ("Scheme is invalid")); -+ return NULL; -+ } -+ -+ if (!KgSchemeFlagTryLock(p_Scheme)) -+ { -+ DBG(TRACE, ("Scheme Try Lock - BUSY")); -+ /* Signal to caller BUSY condition */ -+ p_SchemeParams->id.h_Scheme = NULL; -+ return NULL; -+ } -+ } -+ else -+ { -+ p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPcd, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(p_FmPcd->p_FmPcdKg, E_INVALID_HANDLE, NULL); -+ -+ relativeSchemeId = p_SchemeParams->id.relativeSchemeId; -+ /* check that schemeId is in range */ -+ if (relativeSchemeId >= p_FmPcd->p_FmPcdKg->numOfSchemes) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_IN_RANGE, ("relative-scheme-id %d!", relativeSchemeId)); -+ return NULL; -+ } -+ -+ p_Scheme = &p_FmPcd->p_FmPcdKg->schemes[relativeSchemeId]; -+ if (FmPcdKgIsSchemeValidSw(p_Scheme)) -+ { -+ REPORT_ERROR(MAJOR, E_ALREADY_EXISTS, -+ ("Scheme id (%d)!", relativeSchemeId)); -+ return NULL; -+ } -+ /* Clear all fields, scheme may have beed previously used */ -+ memset(p_Scheme, 0, sizeof(t_FmPcdKgScheme)); -+ -+ p_Scheme->schemeId = p_FmPcd->p_FmPcdKg->schemesIds[relativeSchemeId]; -+ p_Scheme->h_FmPcd = p_FmPcd; -+ -+ p_Scheme->p_Lock = FmPcdAcquireLock(p_FmPcd); -+ if (!p_Scheme->p_Lock) -+ REPORT_ERROR(MAJOR, E_NOT_AVAILABLE, ("FM KG Scheme lock obj!")); -+ } -+ -+ err = BuildSchemeRegs((t_Handle)p_Scheme, p_SchemeParams, &schemeRegs); -+ if (err) -+ { -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ if (p_SchemeParams->modify) -+ KgSchemeFlagUnlock(p_Scheme); -+ if (!p_SchemeParams->modify && -+ p_Scheme->p_Lock) -+ FmPcdReleaseLock(p_FmPcd, p_Scheme->p_Lock); -+ return NULL; -+ } -+ -+ if (p_FmPcd->h_Hc) -+ { -+ err = FmHcPcdKgSetScheme(p_FmPcd->h_Hc, -+ (t_Handle)p_Scheme, -+ &schemeRegs, -+ p_SchemeParams->schemeCounter.update); -+ if (p_SchemeParams->modify) -+ KgSchemeFlagUnlock(p_Scheme); -+ if (err) -+ { -+ if (!p_SchemeParams->modify && -+ p_Scheme->p_Lock) -+ FmPcdReleaseLock(p_FmPcd, p_Scheme->p_Lock); -+ return NULL; -+ } -+ if (!p_SchemeParams->modify) -+ ValidateSchemeSw(p_Scheme); -+ return (t_Handle)p_Scheme; -+ } -+ -+ physicalSchemeId = p_Scheme->schemeId; -+ -+ /* configure all 21 scheme registers */ -+ p_MemRegs = &p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->schemeRegs; -+ intFlags = KgHwLock(p_FmPcd->p_FmPcdKg); -+ WRITE_UINT32(p_MemRegs->kgse_ppc, schemeRegs.kgse_ppc); -+ WRITE_UINT32(p_MemRegs->kgse_ccbs, schemeRegs.kgse_ccbs); -+ WRITE_UINT32(p_MemRegs->kgse_mode, schemeRegs.kgse_mode); -+ WRITE_UINT32(p_MemRegs->kgse_mv, schemeRegs.kgse_mv); -+ WRITE_UINT32(p_MemRegs->kgse_dv0, schemeRegs.kgse_dv0); -+ WRITE_UINT32(p_MemRegs->kgse_dv1, schemeRegs.kgse_dv1); -+ WRITE_UINT32(p_MemRegs->kgse_ekdv, schemeRegs.kgse_ekdv); -+ WRITE_UINT32(p_MemRegs->kgse_ekfc, schemeRegs.kgse_ekfc); -+ WRITE_UINT32(p_MemRegs->kgse_bmch, schemeRegs.kgse_bmch); -+ WRITE_UINT32(p_MemRegs->kgse_bmcl, schemeRegs.kgse_bmcl); -+ WRITE_UINT32(p_MemRegs->kgse_hc, schemeRegs.kgse_hc); -+ WRITE_UINT32(p_MemRegs->kgse_spc, schemeRegs.kgse_spc); -+ WRITE_UINT32(p_MemRegs->kgse_fqb, schemeRegs.kgse_fqb); -+ WRITE_UINT32(p_MemRegs->kgse_om, schemeRegs.kgse_om); -+ WRITE_UINT32(p_MemRegs->kgse_vsp, schemeRegs.kgse_vsp); -+ for (i=0 ; ikgse_gec[i], schemeRegs.kgse_gec[i]); -+ -+ /* call indirect command for scheme write */ -+ tmpKgarReg = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, p_SchemeParams->schemeCounter.update); -+ -+ WriteKgarWait(p_FmPcd, tmpKgarReg); -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+ -+ if (!p_SchemeParams->modify) -+ ValidateSchemeSw(p_Scheme); -+ else -+ KgSchemeFlagUnlock(p_Scheme); -+ -+ return (t_Handle)p_Scheme; -+} -+ -+t_Error FM_PCD_KgSchemeDelete(t_Handle h_Scheme) -+{ -+ t_FmPcd *p_FmPcd; -+ uint8_t physicalSchemeId; -+ uint32_t tmpKgarReg, intFlags; -+ t_Error err = E_OK; -+ t_FmPcdKgScheme *p_Scheme = (t_FmPcdKgScheme *)h_Scheme; -+ -+ SANITY_CHECK_RETURN_ERROR(h_Scheme, E_INVALID_HANDLE); -+ -+ p_FmPcd = (t_FmPcd*)(p_Scheme->h_FmPcd); -+ -+ UpdateRequiredActionFlag(h_Scheme, FALSE); -+ -+ /* check that no port is bound to this scheme */ -+ err = InvalidateSchemeSw(h_Scheme); -+ if (err) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ if (p_FmPcd->h_Hc) -+ { -+ err = FmHcPcdKgDeleteScheme(p_FmPcd->h_Hc, h_Scheme); -+ if (p_Scheme->p_Lock) -+ FmPcdReleaseLock(p_FmPcd, p_Scheme->p_Lock); -+ return err; -+ } -+ -+ physicalSchemeId = ((t_FmPcdKgScheme *)h_Scheme)->schemeId; -+ -+ intFlags = KgHwLock(p_FmPcd->p_FmPcdKg); -+ /* clear mode register, including enable bit */ -+ WRITE_UINT32(p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->schemeRegs.kgse_mode, 0); -+ -+ /* call indirect command for scheme write */ -+ tmpKgarReg = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, FALSE); -+ -+ WriteKgarWait(p_FmPcd, tmpKgarReg); -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+ -+ if (p_Scheme->p_Lock) -+ FmPcdReleaseLock(p_FmPcd, p_Scheme->p_Lock); -+ -+ return E_OK; -+} -+ -+uint32_t FM_PCD_KgSchemeGetCounter(t_Handle h_Scheme) -+{ -+ t_FmPcd *p_FmPcd; -+ uint32_t tmpKgarReg, spc, intFlags; -+ uint8_t physicalSchemeId; -+ -+ SANITY_CHECK_RETURN_VALUE(h_Scheme, E_INVALID_HANDLE, 0); -+ -+ p_FmPcd = (t_FmPcd*)(((t_FmPcdKgScheme *)h_Scheme)->h_FmPcd); -+ if (p_FmPcd->h_Hc) -+ return FmHcPcdKgGetSchemeCounter(p_FmPcd->h_Hc, h_Scheme); -+ -+ physicalSchemeId = ((t_FmPcdKgScheme *)h_Scheme)->schemeId; -+ -+ if (FmPcdKgGetRelativeSchemeId(p_FmPcd, physicalSchemeId) == FM_PCD_KG_NUM_OF_SCHEMES) -+ REPORT_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG); -+ -+ tmpKgarReg = FmPcdKgBuildReadSchemeActionReg(physicalSchemeId); -+ intFlags = KgHwLock(p_FmPcd->p_FmPcdKg); -+ WriteKgarWait(p_FmPcd, tmpKgarReg); -+ if (!(GET_UINT32(p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->schemeRegs.kgse_mode) & KG_SCH_MODE_EN)) -+ REPORT_ERROR(MAJOR, E_ALREADY_EXISTS, ("Scheme is Invalid")); -+ spc = GET_UINT32(p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->schemeRegs.kgse_spc); -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+ -+ return spc; -+} -+ -+t_Error FM_PCD_KgSchemeSetCounter(t_Handle h_Scheme, uint32_t value) -+{ -+ t_FmPcd *p_FmPcd; -+ uint32_t tmpKgarReg, intFlags; -+ uint8_t physicalSchemeId; -+ -+ SANITY_CHECK_RETURN_VALUE(h_Scheme, E_INVALID_HANDLE, 0); -+ -+ p_FmPcd = (t_FmPcd*)(((t_FmPcdKgScheme *)h_Scheme)->h_FmPcd); -+ -+ if (!FmPcdKgIsSchemeValidSw(h_Scheme)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Requested scheme is invalid.")); -+ -+ if (p_FmPcd->h_Hc) -+ return FmHcPcdKgSetSchemeCounter(p_FmPcd->h_Hc, h_Scheme, value); -+ -+ physicalSchemeId = ((t_FmPcdKgScheme *)h_Scheme)->schemeId; -+ /* check that schemeId is in range */ -+ if (FmPcdKgGetRelativeSchemeId(p_FmPcd, physicalSchemeId) == FM_PCD_KG_NUM_OF_SCHEMES) -+ REPORT_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG); -+ -+ /* read specified scheme into scheme registers */ -+ tmpKgarReg = FmPcdKgBuildReadSchemeActionReg(physicalSchemeId); -+ intFlags = KgHwLock(p_FmPcd->p_FmPcdKg); -+ WriteKgarWait(p_FmPcd, tmpKgarReg); -+ if (!(GET_UINT32(p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->schemeRegs.kgse_mode) & KG_SCH_MODE_EN)) -+ { -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+ RETURN_ERROR(MAJOR, E_ALREADY_EXISTS, ("Scheme is Invalid")); -+ } -+ -+ /* change counter value */ -+ WRITE_UINT32(p_FmPcd->p_FmPcdKg->p_IndirectAccessRegs->schemeRegs.kgse_spc, value); -+ -+ /* call indirect command for scheme write */ -+ tmpKgarReg = FmPcdKgBuildWriteSchemeActionReg(physicalSchemeId, TRUE); -+ -+ WriteKgarWait(p_FmPcd, tmpKgarReg); -+ KgHwUnlock(p_FmPcd->p_FmPcdKg, intFlags); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_KgSetAdditionalDataAfterParsing(t_Handle h_FmPcd, uint8_t payloadOffset) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ struct fman_kg_regs *p_Regs; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdKg, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs, E_NULL_POINTER); -+ -+ p_Regs = p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs; -+ if (!FmIsMaster(p_FmPcd->h_Fm)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_KgSetAdditionalDataAfterParsing - guest mode!")); -+ -+ WRITE_UINT32(p_Regs->fmkg_fdor,payloadOffset); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_KgSetDfltValue(t_Handle h_FmPcd, uint8_t valueId, uint32_t value) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ struct fman_kg_regs *p_Regs; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(((valueId == 0) || (valueId == 1)), E_INVALID_VALUE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdKg, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs, E_NULL_POINTER); -+ -+ p_Regs = p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs; -+ -+ if (!FmIsMaster(p_FmPcd->h_Fm)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_KgSetDfltValue - guest mode!")); -+ -+ if (valueId == 0) -+ WRITE_UINT32(p_Regs->fmkg_gdv0r,value); -+ else -+ WRITE_UINT32(p_Regs->fmkg_gdv1r,value); -+ return E_OK; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_kg.h -@@ -0,0 +1,206 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_kg.h -+ -+ @Description FM KG private header -+*//***************************************************************************/ -+#ifndef __FM_KG_H -+#define __FM_KG_H -+ -+#include "std_ext.h" -+ -+/***********************************************************************/ -+/* Keygen defines */ -+/***********************************************************************/ -+/* maskes */ -+#if (DPAA_VERSION >= 11) -+#define KG_SCH_VSP_SHIFT_MASK 0x0003f000 -+#define KG_SCH_OM_VSPE 0x00000001 -+#define KG_SCH_VSP_NO_KSP_EN 0x80000000 -+ -+#define MAX_SP_SHIFT 23 -+#define KG_SCH_VSP_MASK_SHIFT 12 -+#define KG_SCH_VSP_SHIFT 24 -+#endif /* (DPAA_VERSION >= 11) */ -+ -+typedef uint32_t t_KnownFieldsMasks; -+#define KG_SCH_KN_PORT_ID 0x80000000 -+#define KG_SCH_KN_MACDST 0x40000000 -+#define KG_SCH_KN_MACSRC 0x20000000 -+#define KG_SCH_KN_TCI1 0x10000000 -+#define KG_SCH_KN_TCI2 0x08000000 -+#define KG_SCH_KN_ETYPE 0x04000000 -+#define KG_SCH_KN_PPPSID 0x02000000 -+#define KG_SCH_KN_PPPID 0x01000000 -+#define KG_SCH_KN_MPLS1 0x00800000 -+#define KG_SCH_KN_MPLS2 0x00400000 -+#define KG_SCH_KN_MPLS_LAST 0x00200000 -+#define KG_SCH_KN_IPSRC1 0x00100000 -+#define KG_SCH_KN_IPDST1 0x00080000 -+#define KG_SCH_KN_PTYPE1 0x00040000 -+#define KG_SCH_KN_IPTOS_TC1 0x00020000 -+#define KG_SCH_KN_IPV6FL1 0x00010000 -+#define KG_SCH_KN_IPSRC2 0x00008000 -+#define KG_SCH_KN_IPDST2 0x00004000 -+#define KG_SCH_KN_PTYPE2 0x00002000 -+#define KG_SCH_KN_IPTOS_TC2 0x00001000 -+#define KG_SCH_KN_IPV6FL2 0x00000800 -+#define KG_SCH_KN_GREPTYPE 0x00000400 -+#define KG_SCH_KN_IPSEC_SPI 0x00000200 -+#define KG_SCH_KN_IPSEC_NH 0x00000100 -+#define KG_SCH_KN_IPPID 0x00000080 -+#define KG_SCH_KN_L4PSRC 0x00000004 -+#define KG_SCH_KN_L4PDST 0x00000002 -+#define KG_SCH_KN_TFLG 0x00000001 -+ -+typedef uint8_t t_GenericCodes; -+#define KG_SCH_GEN_SHIM1 0x70 -+#define KG_SCH_GEN_DEFAULT 0x10 -+#define KG_SCH_GEN_PARSE_RESULT_N_FQID 0x20 -+#define KG_SCH_GEN_START_OF_FRM 0x40 -+#define KG_SCH_GEN_SHIM2 0x71 -+#define KG_SCH_GEN_IP_PID_NO_V 0x72 -+#define KG_SCH_GEN_ETH 0x03 -+#define KG_SCH_GEN_ETH_NO_V 0x73 -+#define KG_SCH_GEN_SNAP 0x04 -+#define KG_SCH_GEN_SNAP_NO_V 0x74 -+#define KG_SCH_GEN_VLAN1 0x05 -+#define KG_SCH_GEN_VLAN1_NO_V 0x75 -+#define KG_SCH_GEN_VLAN2 0x06 -+#define KG_SCH_GEN_VLAN2_NO_V 0x76 -+#define KG_SCH_GEN_ETH_TYPE 0x07 -+#define KG_SCH_GEN_ETH_TYPE_NO_V 0x77 -+#define KG_SCH_GEN_PPP 0x08 -+#define KG_SCH_GEN_PPP_NO_V 0x78 -+#define KG_SCH_GEN_MPLS1 0x09 -+#define KG_SCH_GEN_MPLS2 0x19 -+#define KG_SCH_GEN_MPLS3 0x29 -+#define KG_SCH_GEN_MPLS1_NO_V 0x79 -+#define KG_SCH_GEN_MPLS_LAST 0x0a -+#define KG_SCH_GEN_MPLS_LAST_NO_V 0x7a -+#define KG_SCH_GEN_IPV4 0x0b -+#define KG_SCH_GEN_IPV6 0x1b -+#define KG_SCH_GEN_L3_NO_V 0x7b -+#define KG_SCH_GEN_IPV4_TUNNELED 0x0c -+#define KG_SCH_GEN_IPV6_TUNNELED 0x1c -+#define KG_SCH_GEN_MIN_ENCAP 0x2c -+#define KG_SCH_GEN_IP2_NO_V 0x7c -+#define KG_SCH_GEN_GRE 0x0d -+#define KG_SCH_GEN_GRE_NO_V 0x7d -+#define KG_SCH_GEN_TCP 0x0e -+#define KG_SCH_GEN_UDP 0x1e -+#define KG_SCH_GEN_IPSEC_AH 0x2e -+#define KG_SCH_GEN_SCTP 0x3e -+#define KG_SCH_GEN_DCCP 0x4e -+#define KG_SCH_GEN_IPSEC_ESP 0x6e -+#define KG_SCH_GEN_L4_NO_V 0x7e -+#define KG_SCH_GEN_NEXTHDR 0x7f -+/* shifts */ -+#define KG_SCH_PP_SHIFT_HIGH_SHIFT 27 -+#define KG_SCH_PP_SHIFT_LOW_SHIFT 12 -+#define KG_SCH_PP_MASK_SHIFT 16 -+#define KG_SCH_MODE_CCOBASE_SHIFT 24 -+#define KG_SCH_DEF_MAC_ADDR_SHIFT 30 -+#define KG_SCH_DEF_TCI_SHIFT 28 -+#define KG_SCH_DEF_ENET_TYPE_SHIFT 26 -+#define KG_SCH_DEF_PPP_SESSION_ID_SHIFT 24 -+#define KG_SCH_DEF_PPP_PROTOCOL_ID_SHIFT 22 -+#define KG_SCH_DEF_MPLS_LABEL_SHIFT 20 -+#define KG_SCH_DEF_IP_ADDR_SHIFT 18 -+#define KG_SCH_DEF_PROTOCOL_TYPE_SHIFT 16 -+#define KG_SCH_DEF_IP_TOS_TC_SHIFT 14 -+#define KG_SCH_DEF_IPV6_FLOW_LABEL_SHIFT 12 -+#define KG_SCH_DEF_IPSEC_SPI_SHIFT 10 -+#define KG_SCH_DEF_L4_PORT_SHIFT 8 -+#define KG_SCH_DEF_TCP_FLAG_SHIFT 6 -+#define KG_SCH_HASH_CONFIG_SHIFT_SHIFT 24 -+#define KG_SCH_GEN_MASK_SHIFT 16 -+#define KG_SCH_GEN_HT_SHIFT 8 -+#define KG_SCH_GEN_SIZE_SHIFT 24 -+#define KG_SCH_GEN_DEF_SHIFT 29 -+#define FM_PCD_KG_KGAR_NUM_SHIFT 16 -+ -+/* others */ -+#define NUM_OF_SW_DEFAULTS 3 -+#define MAX_PP_SHIFT 23 -+#define MAX_KG_SCH_SIZE 16 -+#define MASK_FOR_GENERIC_BASE_ID 0x20 -+#define MAX_HASH_SHIFT 40 -+#define MAX_KG_SCH_FQID_BIT_OFFSET 31 -+#define MAX_KG_SCH_PP_BIT_OFFSET 15 -+#define MAX_DIST_FQID_SHIFT 23 -+ -+#define GET_MASK_SEL_SHIFT(shift,i) \ -+switch (i) { \ -+ case (0):shift = 26;break; \ -+ case (1):shift = 20;break; \ -+ case (2):shift = 10;break; \ -+ case (3):shift = 4;break; \ -+ default: \ -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); \ -+} -+ -+#define GET_MASK_OFFSET_SHIFT(shift,i) \ -+switch (i) { \ -+ case (0):shift = 16;break; \ -+ case (1):shift = 0;break; \ -+ case (2):shift = 28;break; \ -+ case (3):shift = 24;break; \ -+ default: \ -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); \ -+} -+ -+#define GET_MASK_SHIFT(shift,i) \ -+switch (i) { \ -+ case (0):shift = 24;break; \ -+ case (1):shift = 16;break; \ -+ case (2):shift = 8;break; \ -+ case (3):shift = 0;break; \ -+ default: \ -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); \ -+} -+ -+/***********************************************************************/ -+/* Keygen defines */ -+/***********************************************************************/ -+ -+#define KG_DOUBLE_MEANING_REGS_OFFSET 0x100 -+#define NO_VALIDATION 0x70 -+#define KG_ACTION_REG_TO 1024 -+#define KG_MAX_PROFILE 255 -+#define SCHEME_ALWAYS_DIRECT 0xFFFFFFFF -+ -+ -+#endif /* __FM_KG_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_manip.c -@@ -0,0 +1,5571 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_manip.c -+ -+ @Description FM PCD manip ... -+ *//***************************************************************************/ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "string_ext.h" -+#include "debug_ext.h" -+#include "fm_pcd_ext.h" -+#include "fm_port_ext.h" -+#include "fm_muram_ext.h" -+#include "memcpy_ext.h" -+ -+#include "fm_common.h" -+#include "fm_hc.h" -+#include "fm_manip.h" -+ -+/****************************************/ -+/* static functions */ -+/****************************************/ -+static t_Handle GetManipInfo(t_FmPcdManip *p_Manip, e_ManipInfo manipInfo) -+{ -+ t_FmPcdManip *p_CurManip = p_Manip; -+ -+ if (!MANIP_IS_UNIFIED(p_Manip)) -+ p_CurManip = p_Manip; -+ else -+ { -+ /* go to first unified */ -+ while (MANIP_IS_UNIFIED_NON_FIRST(p_CurManip)) -+ p_CurManip = p_CurManip->h_PrevManip; -+ } -+ -+ switch (manipInfo) -+ { -+ case (e_MANIP_HMCT): -+ return p_CurManip->p_Hmct; -+ case (e_MANIP_HMTD): -+ return p_CurManip->h_Ad; -+ case (e_MANIP_HANDLER_TABLE_OWNER): -+ return (t_Handle)p_CurManip; -+ default: -+ return NULL; -+ } -+} -+ -+static uint16_t GetHmctSize(t_FmPcdManip *p_Manip) -+{ -+ uint16_t size = 0; -+ t_FmPcdManip *p_CurManip = p_Manip; -+ -+ if (!MANIP_IS_UNIFIED(p_Manip)) -+ return p_Manip->tableSize; -+ -+ /* accumulate sizes, starting with the first node */ -+ while (MANIP_IS_UNIFIED_NON_FIRST(p_CurManip)) -+ p_CurManip = p_CurManip->h_PrevManip; -+ -+ while (MANIP_IS_UNIFIED_NON_LAST(p_CurManip)) -+ { -+ size += p_CurManip->tableSize; -+ p_CurManip = (t_FmPcdManip *)p_CurManip->h_NextManip; -+ } -+ size += p_CurManip->tableSize; /* add last size */ -+ -+ return (size); -+} -+ -+static uint16_t GetDataSize(t_FmPcdManip *p_Manip) -+{ -+ uint16_t size = 0; -+ t_FmPcdManip *p_CurManip = p_Manip; -+ -+ if (!MANIP_IS_UNIFIED(p_Manip)) -+ return p_Manip->dataSize; -+ -+ /* accumulate sizes, starting with the first node */ -+ while (MANIP_IS_UNIFIED_NON_FIRST(p_CurManip)) -+ p_CurManip = p_CurManip->h_PrevManip; -+ -+ while (MANIP_IS_UNIFIED_NON_LAST(p_CurManip)) -+ { -+ size += p_CurManip->dataSize; -+ p_CurManip = (t_FmPcdManip *)p_CurManip->h_NextManip; -+ } -+ size += p_CurManip->dataSize; /* add last size */ -+ -+ return (size); -+} -+ -+static t_Error CalculateTableSize(t_FmPcdManipParams *p_FmPcdManipParams, -+ uint16_t *p_TableSize, uint8_t *p_DataSize) -+{ -+ uint8_t localDataSize, remain, tableSize = 0, dataSize = 0; -+ -+ if (p_FmPcdManipParams->u.hdr.rmv) -+ { -+ switch (p_FmPcdManipParams->u.hdr.rmvParams.type) -+ { -+ case (e_FM_PCD_MANIP_RMV_GENERIC): -+ tableSize += HMCD_BASIC_SIZE; -+ break; -+ case (e_FM_PCD_MANIP_RMV_BY_HDR): -+ switch (p_FmPcdManipParams->u.hdr.rmvParams.u.byHdr.type) -+ { -+ case (e_FM_PCD_MANIP_RMV_BY_HDR_SPECIFIC_L2): -+#if (DPAA_VERSION >= 11) -+ case (e_FM_PCD_MANIP_RMV_BY_HDR_CAPWAP): -+ case (e_FM_PCD_MANIP_RMV_BY_HDR_FROM_START): -+#endif /* (DPAA_VERSION >= 11) */ -+ tableSize += HMCD_BASIC_SIZE; -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, -+ ("Unknown byHdr.type")); -+ } -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, -+ ("Unknown rmvParams.type")); -+ } -+ } -+ -+ if (p_FmPcdManipParams->u.hdr.insrt) -+ { -+ switch (p_FmPcdManipParams->u.hdr.insrtParams.type) -+ { -+ case (e_FM_PCD_MANIP_INSRT_GENERIC): -+ remain = -+ (uint8_t)(p_FmPcdManipParams->u.hdr.insrtParams.u.generic.size -+ % 4); -+ if (remain) -+ localDataSize = -+ (uint8_t)(p_FmPcdManipParams->u.hdr.insrtParams.u.generic.size -+ + 4 - remain); -+ else -+ localDataSize = -+ p_FmPcdManipParams->u.hdr.insrtParams.u.generic.size; -+ tableSize += (uint8_t)(HMCD_BASIC_SIZE + localDataSize); -+ break; -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR): -+ { -+ switch (p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.type) -+ { -+ -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_SPECIFIC_L2): -+ tableSize += HMCD_BASIC_SIZE + HMCD_PTR_SIZE; -+ switch (p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.specificL2Params.specificL2) -+ { -+ case (e_FM_PCD_MANIP_HDR_INSRT_MPLS): -+ case (e_FM_PCD_MANIP_HDR_INSRT_PPPOE): -+ dataSize += -+ p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.specificL2Params.size; -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+ } -+ break; -+#if (DPAA_VERSION >= 11) -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_IP): -+ tableSize += -+ (HMCD_BASIC_SIZE + HMCD_PTR_SIZE -+ + HMCD_PARAM_SIZE -+ + p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.ipParams.insrt.size); -+ dataSize += 2; -+ break; -+ -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_UDP): -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_UDP_LITE): -+ tableSize += (HMCD_BASIC_SIZE + HMCD_L4_HDR_SIZE); -+ -+ break; -+ -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_CAPWAP): -+ tableSize += -+ (HMCD_BASIC_SIZE -+ + p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.insrt.size); -+ break; -+#endif /* (DPAA_VERSION >= 11) */ -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, -+ ("Unknown byHdr.type")); -+ } -+ } -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, -+ ("Unknown insrtParams.type")); -+ } -+ } -+ -+ if (p_FmPcdManipParams->u.hdr.fieldUpdate) -+ { -+ switch (p_FmPcdManipParams->u.hdr.fieldUpdateParams.type) -+ { -+ case (e_FM_PCD_MANIP_HDR_FIELD_UPDATE_VLAN): -+ tableSize += HMCD_BASIC_SIZE; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.vlan.updateType -+ == e_FM_PCD_MANIP_HDR_FIELD_UPDATE_DSCP_TO_VLAN) -+ { -+ tableSize += HMCD_PTR_SIZE; -+ dataSize += DSCP_TO_VLAN_TABLE_SIZE; -+ } -+ break; -+ case (e_FM_PCD_MANIP_HDR_FIELD_UPDATE_IPV4): -+ tableSize += HMCD_BASIC_SIZE; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.validUpdates -+ & HDR_MANIP_IPV4_ID) -+ { -+ tableSize += HMCD_PARAM_SIZE; -+ dataSize += 2; -+ } -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.validUpdates -+ & HDR_MANIP_IPV4_SRC) -+ tableSize += HMCD_IPV4_ADDR_SIZE; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.validUpdates -+ & HDR_MANIP_IPV4_DST) -+ tableSize += HMCD_IPV4_ADDR_SIZE; -+ break; -+ case (e_FM_PCD_MANIP_HDR_FIELD_UPDATE_IPV6): -+ tableSize += HMCD_BASIC_SIZE; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.validUpdates -+ & HDR_MANIP_IPV6_SRC) -+ tableSize += HMCD_IPV6_ADDR_SIZE; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.validUpdates -+ & HDR_MANIP_IPV6_DST) -+ tableSize += HMCD_IPV6_ADDR_SIZE; -+ break; -+ case (e_FM_PCD_MANIP_HDR_FIELD_UPDATE_TCP_UDP): -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.tcpUdp.validUpdates -+ == HDR_MANIP_TCP_UDP_CHECKSUM) -+ /* we implement this case with the update-checksum descriptor */ -+ tableSize += HMCD_BASIC_SIZE; -+ else -+ /* we implement this case with the TCP/UDP-update descriptor */ -+ tableSize += HMCD_BASIC_SIZE + HMCD_PARAM_SIZE; -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, -+ ("Unknown fieldUpdateParams.type")); -+ } -+ } -+ -+ if (p_FmPcdManipParams->u.hdr.custom) -+ { -+ switch (p_FmPcdManipParams->u.hdr.customParams.type) -+ { -+ case (e_FM_PCD_MANIP_HDR_CUSTOM_IP_REPLACE): -+ { -+ tableSize += HMCD_BASIC_SIZE + HMCD_PARAM_SIZE + HMCD_PARAM_SIZE; -+ dataSize += -+ p_FmPcdManipParams->u.hdr.customParams.u.ipHdrReplace.hdrSize; -+ if ((p_FmPcdManipParams->u.hdr.customParams.u.ipHdrReplace.replaceType -+ == e_FM_PCD_MANIP_HDR_CUSTOM_REPLACE_IPV6_BY_IPV4) -+ && (p_FmPcdManipParams->u.hdr.customParams.u.ipHdrReplace.updateIpv4Id)) -+ dataSize += 2; -+ } -+ break; -+ case (e_FM_PCD_MANIP_HDR_CUSTOM_GEN_FIELD_REPLACE): -+ tableSize += HMCD_BASIC_SIZE + HMCD_PARAM_SIZE; -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, -+ ("Unknown customParams.type")); -+ } -+ } -+ -+ *p_TableSize = tableSize; -+ *p_DataSize = dataSize; -+ -+ return E_OK; -+} -+ -+static t_Error GetPrOffsetByHeaderOrField(t_FmManipHdrInfo *p_HdrInfo, -+ uint8_t *parseArrayOffset) -+{ -+ e_NetHeaderType hdr = p_HdrInfo->hdr; -+ e_FmPcdHdrIndex hdrIndex = p_HdrInfo->hdrIndex; -+ bool byField = p_HdrInfo->byField; -+ t_FmPcdFields field; -+ -+ if (byField) -+ field = p_HdrInfo->fullField; -+ -+ if (byField) -+ { -+ switch (hdr) -+ { -+ case (HEADER_TYPE_ETH): -+ switch (field.eth) -+ { -+ case (NET_HEADER_FIELD_ETH_TYPE): -+ *parseArrayOffset = CC_PC_PR_ETYPE_LAST_OFFSET; -+ break; -+ default: -+ RETURN_ERROR( -+ MAJOR, -+ E_NOT_SUPPORTED, -+ ("Header manipulation of the type Ethernet with this field not supported")); -+ } -+ break; -+ case (HEADER_TYPE_VLAN): -+ switch (field.vlan) -+ { -+ case (NET_HEADER_FIELD_VLAN_TCI): -+ if ((hdrIndex == e_FM_PCD_HDR_INDEX_NONE) -+ || (hdrIndex == e_FM_PCD_HDR_INDEX_1)) -+ *parseArrayOffset = CC_PC_PR_VLAN1_OFFSET; -+ else -+ if (hdrIndex == e_FM_PCD_HDR_INDEX_LAST) -+ *parseArrayOffset = CC_PC_PR_VLAN2_OFFSET; -+ break; -+ default: -+ RETURN_ERROR( -+ MAJOR, -+ E_NOT_SUPPORTED, -+ ("Header manipulation of the type VLAN with this field not supported")); -+ } -+ break; -+ default: -+ RETURN_ERROR( -+ MAJOR, -+ E_NOT_SUPPORTED, -+ ("Header manipulation of this header by field not supported")); -+ } -+ } -+ else -+ { -+ switch (hdr) -+ { -+ case (HEADER_TYPE_ETH): -+ *parseArrayOffset = (uint8_t)CC_PC_PR_ETH_OFFSET; -+ break; -+ case (HEADER_TYPE_USER_DEFINED_SHIM1): -+ *parseArrayOffset = (uint8_t)CC_PC_PR_USER_DEFINED_SHIM1_OFFSET; -+ break; -+ case (HEADER_TYPE_USER_DEFINED_SHIM2): -+ *parseArrayOffset = (uint8_t)CC_PC_PR_USER_DEFINED_SHIM2_OFFSET; -+ break; -+ case (HEADER_TYPE_LLC_SNAP): -+ *parseArrayOffset = CC_PC_PR_USER_LLC_SNAP_OFFSET; -+ break; -+ case (HEADER_TYPE_PPPoE): -+ *parseArrayOffset = CC_PC_PR_PPPOE_OFFSET; -+ break; -+ case (HEADER_TYPE_MPLS): -+ if ((hdrIndex == e_FM_PCD_HDR_INDEX_NONE) -+ || (hdrIndex == e_FM_PCD_HDR_INDEX_1)) -+ *parseArrayOffset = CC_PC_PR_MPLS1_OFFSET; -+ else -+ if (hdrIndex == e_FM_PCD_HDR_INDEX_LAST) -+ *parseArrayOffset = CC_PC_PR_MPLS_LAST_OFFSET; -+ break; -+ case (HEADER_TYPE_IPv4): -+ case (HEADER_TYPE_IPv6): -+ if ((hdrIndex == e_FM_PCD_HDR_INDEX_NONE) -+ || (hdrIndex == e_FM_PCD_HDR_INDEX_1)) -+ *parseArrayOffset = CC_PC_PR_IP1_OFFSET; -+ else -+ if (hdrIndex == e_FM_PCD_HDR_INDEX_2) -+ *parseArrayOffset = CC_PC_PR_IP_LAST_OFFSET; -+ break; -+ case (HEADER_TYPE_MINENCAP): -+ *parseArrayOffset = CC_PC_PR_MINENC_OFFSET; -+ break; -+ case (HEADER_TYPE_GRE): -+ *parseArrayOffset = CC_PC_PR_GRE_OFFSET; -+ break; -+ case (HEADER_TYPE_TCP): -+ case (HEADER_TYPE_UDP): -+ case (HEADER_TYPE_IPSEC_AH): -+ case (HEADER_TYPE_IPSEC_ESP): -+ case (HEADER_TYPE_DCCP): -+ case (HEADER_TYPE_SCTP): -+ *parseArrayOffset = CC_PC_PR_L4_OFFSET; -+ break; -+ case (HEADER_TYPE_CAPWAP): -+ case (HEADER_TYPE_CAPWAP_DTLS): -+ *parseArrayOffset = CC_PC_PR_NEXT_HEADER_OFFSET; -+ break; -+ default: -+ RETURN_ERROR( -+ MAJOR, -+ E_NOT_SUPPORTED, -+ ("Header manipulation of this header is not supported")); -+ } -+ } -+ return E_OK; -+} -+ -+static t_Error BuildHmct(t_FmPcdManip *p_Manip, -+ t_FmPcdManipParams *p_FmPcdManipParams, -+ uint8_t *p_DestHmct, uint8_t *p_DestData, bool new) -+{ -+ uint32_t *p_TmpHmct = (uint32_t*)p_DestHmct, *p_LocalData; -+ uint32_t tmpReg = 0, *p_Last = NULL, tmp_ipv6_addr; -+ uint8_t remain, i, size = 0, origSize, *p_UsrData = NULL, *p_TmpData = -+ p_DestData; -+ t_Handle h_FmPcd = p_Manip->h_FmPcd; -+ uint8_t j = 0; -+ -+ if (p_FmPcdManipParams->u.hdr.rmv) -+ { -+ if (p_FmPcdManipParams->u.hdr.rmvParams.type -+ == e_FM_PCD_MANIP_RMV_GENERIC) -+ { -+ /* initialize HMCD */ -+ tmpReg = (uint32_t)(HMCD_OPCODE_GENERIC_RMV) << HMCD_OC_SHIFT; -+ /* tmp, should be conditional */ -+ tmpReg |= p_FmPcdManipParams->u.hdr.rmvParams.u.generic.offset -+ << HMCD_RMV_OFFSET_SHIFT; -+ tmpReg |= p_FmPcdManipParams->u.hdr.rmvParams.u.generic.size -+ << HMCD_RMV_SIZE_SHIFT; -+ } -+ else -+ if (p_FmPcdManipParams->u.hdr.rmvParams.type -+ == e_FM_PCD_MANIP_RMV_BY_HDR) -+ { -+ switch (p_FmPcdManipParams->u.hdr.rmvParams.u.byHdr.type) -+ { -+ case (e_FM_PCD_MANIP_RMV_BY_HDR_SPECIFIC_L2): -+ { -+ uint8_t hmcdOpt; -+ -+ /* initialize HMCD */ -+ tmpReg = (uint32_t)(HMCD_OPCODE_L2_RMV) << HMCD_OC_SHIFT; -+ -+ switch (p_FmPcdManipParams->u.hdr.rmvParams.u.byHdr.u.specificL2) -+ { -+ case (e_FM_PCD_MANIP_HDR_RMV_ETHERNET): -+ hmcdOpt = HMCD_RMV_L2_ETHERNET; -+ break; -+ case (e_FM_PCD_MANIP_HDR_RMV_STACKED_QTAGS): -+ hmcdOpt = HMCD_RMV_L2_STACKED_QTAGS; -+ break; -+ case (e_FM_PCD_MANIP_HDR_RMV_ETHERNET_AND_MPLS): -+ hmcdOpt = HMCD_RMV_L2_ETHERNET_AND_MPLS; -+ break; -+ case (e_FM_PCD_MANIP_HDR_RMV_MPLS): -+ hmcdOpt = HMCD_RMV_L2_MPLS; -+ break; -+ case (e_FM_PCD_MANIP_HDR_RMV_PPPOE): -+ hmcdOpt = HMCD_RMV_L2_PPPOE; -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+ } -+ tmpReg |= hmcdOpt << HMCD_L2_MODE_SHIFT; -+ break; -+ } -+#if (DPAA_VERSION >= 11) -+ case (e_FM_PCD_MANIP_RMV_BY_HDR_CAPWAP): -+ tmpReg = (uint32_t)(HMCD_OPCODE_CAPWAP_RMV) -+ << HMCD_OC_SHIFT; -+ break; -+ case (e_FM_PCD_MANIP_RMV_BY_HDR_FROM_START): -+ { -+ uint8_t prsArrayOffset; -+ t_Error err = E_OK; -+ -+ tmpReg = (uint32_t)(HMCD_OPCODE_RMV_TILL) -+ << HMCD_OC_SHIFT; -+ -+ err = -+ GetPrOffsetByHeaderOrField( -+ &p_FmPcdManipParams->u.hdr.rmvParams.u.byHdr.u.hdrInfo, -+ &prsArrayOffset); -+ ASSERT_COND(!err); -+ /* was previously checked */ -+ -+ tmpReg |= ((uint32_t)prsArrayOffset << 16); -+ } -+ break; -+#endif /* (DPAA_VERSION >= 11) */ -+ default: -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("manip header remove by hdr type!")); -+ } -+ } -+ -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ /* advance to next command */ -+ p_TmpHmct += HMCD_BASIC_SIZE / 4; -+ } -+ -+ if (p_FmPcdManipParams->u.hdr.insrt) -+ { -+ if (p_FmPcdManipParams->u.hdr.insrtParams.type -+ == e_FM_PCD_MANIP_INSRT_GENERIC) -+ { -+ /* initialize HMCD */ -+ if (p_FmPcdManipParams->u.hdr.insrtParams.u.generic.replace) -+ tmpReg = (uint32_t)(HMCD_OPCODE_GENERIC_REPLACE) -+ << HMCD_OC_SHIFT; -+ else -+ tmpReg = (uint32_t)(HMCD_OPCODE_GENERIC_INSRT) << HMCD_OC_SHIFT; -+ -+ tmpReg |= p_FmPcdManipParams->u.hdr.insrtParams.u.generic.offset -+ << HMCD_INSRT_OFFSET_SHIFT; -+ tmpReg |= p_FmPcdManipParams->u.hdr.insrtParams.u.generic.size -+ << HMCD_INSRT_SIZE_SHIFT; -+ -+ size = p_FmPcdManipParams->u.hdr.insrtParams.u.generic.size; -+ p_UsrData = p_FmPcdManipParams->u.hdr.insrtParams.u.generic.p_Data; -+ -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ -+ p_TmpHmct += HMCD_BASIC_SIZE / 4; -+ -+ /* initialize data to be inserted */ -+ /* if size is not a multiple of 4, padd with 0's */ -+ origSize = size; -+ remain = (uint8_t)(size % 4); -+ if (remain) -+ { -+ size += (uint8_t)(4 - remain); -+ p_LocalData = (uint32_t *)XX_Malloc(size); -+ memset((uint8_t *)p_LocalData, 0, size); -+ memcpy((uint8_t *)p_LocalData, p_UsrData, origSize); -+ } -+ else -+ p_LocalData = (uint32_t*)p_UsrData; -+ -+ /* initialize data and advance pointer to next command */ -+ MemCpy8(p_TmpHmct, p_LocalData, size); -+ p_TmpHmct += size / sizeof(uint32_t); -+ -+ if (remain) -+ XX_Free(p_LocalData); -+ } -+ -+ else -+ if (p_FmPcdManipParams->u.hdr.insrtParams.type -+ == e_FM_PCD_MANIP_INSRT_BY_HDR) -+ { -+ switch (p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.type) -+ { -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_SPECIFIC_L2): -+ { -+ uint8_t hmcdOpt; -+ -+ /* initialize HMCD */ -+ tmpReg = (uint32_t)(HMCD_OPCODE_L2_INSRT) -+ << HMCD_OC_SHIFT; -+ -+ switch (p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.specificL2Params.specificL2) -+ { -+ case (e_FM_PCD_MANIP_HDR_INSRT_MPLS): -+ if (p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.specificL2Params.update) -+ hmcdOpt = HMCD_INSRT_N_UPDATE_L2_MPLS; -+ else -+ hmcdOpt = HMCD_INSRT_L2_MPLS; -+ break; -+ case (e_FM_PCD_MANIP_HDR_INSRT_PPPOE): -+ hmcdOpt = HMCD_INSRT_L2_PPPOE; -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); -+ } -+ tmpReg |= hmcdOpt << HMCD_L2_MODE_SHIFT; -+ -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ -+ p_TmpHmct += HMCD_BASIC_SIZE / 4; -+ -+ /* set size and pointer of user's data */ -+ size = -+ (uint8_t)p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.specificL2Params.size; -+ -+ ASSERT_COND(p_TmpData); -+ MemCpy8( -+ p_TmpData, -+ p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.specificL2Params.p_Data, -+ size); -+ tmpReg = -+ (size << HMCD_INSRT_L2_SIZE_SHIFT) -+ | (uint32_t)(XX_VirtToPhys(p_TmpData) -+ - (((t_FmPcd*)h_FmPcd)->physicalMuramBase)); -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ p_TmpHmct += HMCD_PTR_SIZE / 4; -+ p_TmpData += size; -+ } -+ break; -+#if (DPAA_VERSION >= 11) -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_IP): -+ tmpReg = (uint32_t)(HMCD_OPCODE_IP_INSRT) -+ << HMCD_OC_SHIFT; -+ if (p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.ipParams.calcL4Checksum) -+ tmpReg |= HMCD_IP_L4_CS_CALC; -+ if (p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.ipParams.mappingMode -+ == e_FM_PCD_MANIP_HDR_QOS_MAPPING_AS_IS) -+ tmpReg |= HMCD_IP_OR_QOS; -+ tmpReg |= -+ p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.ipParams.lastPidOffset -+ & HMCD_IP_LAST_PID_MASK; -+ tmpReg |= -+ ((p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.ipParams.insrt.size -+ << HMCD_IP_SIZE_SHIFT) -+ & HMCD_IP_SIZE_MASK); -+ if (p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.ipParams.dontFragOverwrite) -+ tmpReg |= HMCD_IP_DF_MODE; -+ -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ -+ p_TmpHmct += HMCD_BASIC_SIZE / 4; -+ -+ /* set IP id */ -+ ASSERT_COND(p_TmpData); -+ WRITE_UINT16( -+ *(uint16_t*)p_TmpData, -+ p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.ipParams.id); -+ WRITE_UINT32( -+ *p_TmpHmct, -+ (uint32_t)(XX_VirtToPhys(p_TmpData) - (((t_FmPcd*)p_Manip->h_FmPcd)->physicalMuramBase))); -+ p_TmpData += 2; -+ p_TmpHmct += HMCD_PTR_SIZE / 4; -+ -+ WRITE_UINT8(*p_TmpHmct, p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.ipParams.lastDstOffset); -+ p_TmpHmct += HMCD_PARAM_SIZE / 4; -+ -+ MemCpy8( -+ p_TmpHmct, -+ p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.ipParams.insrt.p_Data, -+ p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.ipParams.insrt.size); -+ p_TmpHmct += -+ p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.ipParams.insrt.size -+ / 4; -+ break; -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_UDP_LITE): -+ tmpReg = HMCD_INSRT_UDP_LITE; -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_UDP): -+ tmpReg |= (uint32_t)(HMCD_OPCODE_UDP_INSRT) -+ << HMCD_OC_SHIFT; -+ -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ -+ p_TmpHmct += HMCD_BASIC_SIZE / 4; -+ -+ MemCpy8( -+ p_TmpHmct, -+ p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.insrt.p_Data, -+ p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.insrt.size); -+ p_TmpHmct += -+ p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.insrt.size -+ / 4; -+ break; -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_CAPWAP): -+ tmpReg = (uint32_t)(HMCD_OPCODE_CAPWAP_INSRT) -+ << HMCD_OC_SHIFT; -+ tmpReg |= HMCD_CAPWAP_INSRT; -+ -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ -+ p_TmpHmct += HMCD_BASIC_SIZE / 4; -+ -+ MemCpy8( -+ p_TmpHmct, -+ p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.insrt.p_Data, -+ p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.insrt.size); -+ p_TmpHmct += -+ p_FmPcdManipParams->u.hdr.insrtParams.u.byHdr.u.insrt.size -+ / 4; -+ break; -+#endif /* (DPAA_VERSION >= 11) */ -+ default: -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("manip header insert by header type!")); -+ -+ } -+ } -+ } -+ -+ if (p_FmPcdManipParams->u.hdr.fieldUpdate) -+ { -+ switch (p_FmPcdManipParams->u.hdr.fieldUpdateParams.type) -+ { -+ case (e_FM_PCD_MANIP_HDR_FIELD_UPDATE_VLAN): -+ /* set opcode */ -+ tmpReg = (uint32_t)(HMCD_OPCODE_VLAN_PRI_UPDATE) -+ << HMCD_OC_SHIFT; -+ -+ /* set mode & table pointer */ -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.vlan.updateType -+ == e_FM_PCD_MANIP_HDR_FIELD_UPDATE_DSCP_TO_VLAN) -+ { -+ /* set Mode */ -+ tmpReg |= (uint32_t)(HMCD_VLAN_PRI_UPDATE_DSCP_TO_VPRI) -+ << HMCD_VLAN_PRI_REP_MODE_SHIFT; -+ /* set VPRI default */ -+ tmpReg |= -+ p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.vlan.u.dscpToVpri.vpriDefVal; -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ /* write the table pointer into the Manip descriptor */ -+ p_TmpHmct += HMCD_BASIC_SIZE / 4; -+ -+ tmpReg = 0; -+ ASSERT_COND(p_TmpData); -+ for (i = 0; i < HMCD_DSCP_VALUES; i++) -+ { -+ /* first we build from each 8 values a 32bit register */ -+ tmpReg |= -+ (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.vlan.u.dscpToVpri.dscpToVpriTable[i]) -+ << (32 - 4 * (j + 1)); -+ j++; -+ /* Than we write this register to the next table word -+ * (i=7-->word 0, i=15-->word 1,... i=63-->word 7) */ -+ if ((i % 8) == 7) -+ { -+ WRITE_UINT32(*((uint32_t*)p_TmpData + (i+1)/8-1), -+ tmpReg); -+ tmpReg = 0; -+ j = 0; -+ } -+ } -+ -+ WRITE_UINT32( -+ *p_TmpHmct, -+ (uint32_t)(XX_VirtToPhys(p_TmpData) - (((t_FmPcd*)h_FmPcd)->physicalMuramBase))); -+ p_TmpHmct += HMCD_PTR_SIZE / 4; -+ -+ p_TmpData += DSCP_TO_VLAN_TABLE_SIZE; -+ } -+ else -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.vlan.updateType -+ == e_FM_PCD_MANIP_HDR_FIELD_UPDATE_VLAN_VPRI) -+ { -+ /* set Mode */ -+ /* line commented out as it has no-side-effect ('0' value). */ -+ /*tmpReg |= HMCD_VLAN_PRI_UPDATE << HMCD_VLAN_PRI_REP_MODE_SHIFT*/; -+ /* set VPRI parameter */ -+ tmpReg |= -+ p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.vlan.u.vpri; -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ p_TmpHmct += HMCD_BASIC_SIZE / 4; -+ } -+ break; -+ -+ case (e_FM_PCD_MANIP_HDR_FIELD_UPDATE_IPV4): -+ /* set opcode */ -+ tmpReg = (uint32_t)(HMCD_OPCODE_IPV4_UPDATE) << HMCD_OC_SHIFT; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.validUpdates -+ & HDR_MANIP_IPV4_TTL) -+ tmpReg |= HMCD_IPV4_UPDATE_TTL; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.validUpdates -+ & HDR_MANIP_IPV4_TOS) -+ { -+ tmpReg |= HMCD_IPV4_UPDATE_TOS; -+ tmpReg |= -+ p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.tos -+ << HMCD_IPV4_UPDATE_TOS_SHIFT; -+ } -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.validUpdates -+ & HDR_MANIP_IPV4_ID) -+ tmpReg |= HMCD_IPV4_UPDATE_ID; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.validUpdates -+ & HDR_MANIP_IPV4_SRC) -+ tmpReg |= HMCD_IPV4_UPDATE_SRC; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.validUpdates -+ & HDR_MANIP_IPV4_DST) -+ tmpReg |= HMCD_IPV4_UPDATE_DST; -+ /* write the first 4 bytes of the descriptor */ -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ -+ p_TmpHmct += HMCD_BASIC_SIZE / 4; -+ -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.validUpdates -+ & HDR_MANIP_IPV4_ID) -+ { -+ ASSERT_COND(p_TmpData); -+ WRITE_UINT16( -+ *(uint16_t*)p_TmpData, -+ p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.id); -+ WRITE_UINT32( -+ *p_TmpHmct, -+ (uint32_t)(XX_VirtToPhys(p_TmpData) - (((t_FmPcd*)p_Manip->h_FmPcd)->physicalMuramBase))); -+ p_TmpData += 2; -+ p_TmpHmct += HMCD_PTR_SIZE / 4; -+ } -+ -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.validUpdates -+ & HDR_MANIP_IPV4_SRC) -+ { -+ WRITE_UINT32( -+ *p_TmpHmct, -+ p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.src); -+ p_TmpHmct += HMCD_IPV4_ADDR_SIZE / 4; -+ } -+ -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.validUpdates -+ & HDR_MANIP_IPV4_DST) -+ { -+ WRITE_UINT32( -+ *p_TmpHmct, -+ p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv4.dst); -+ p_TmpHmct += HMCD_IPV4_ADDR_SIZE / 4; -+ } -+ break; -+ -+ case (e_FM_PCD_MANIP_HDR_FIELD_UPDATE_IPV6): -+ /* set opcode */ -+ tmpReg = (uint32_t)(HMCD_OPCODE_IPV6_UPDATE) << HMCD_OC_SHIFT; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv6.validUpdates -+ & HDR_MANIP_IPV6_HL) -+ tmpReg |= HMCD_IPV6_UPDATE_HL; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv6.validUpdates -+ & HDR_MANIP_IPV6_TC) -+ { -+ tmpReg |= HMCD_IPV6_UPDATE_TC; -+ tmpReg |= -+ p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv6.trafficClass -+ << HMCD_IPV6_UPDATE_TC_SHIFT; -+ } -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv6.validUpdates -+ & HDR_MANIP_IPV6_SRC) -+ tmpReg |= HMCD_IPV6_UPDATE_SRC; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv6.validUpdates -+ & HDR_MANIP_IPV6_DST) -+ tmpReg |= HMCD_IPV6_UPDATE_DST; -+ /* write the first 4 bytes of the descriptor */ -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ -+ p_TmpHmct += HMCD_BASIC_SIZE / 4; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv6.validUpdates -+ & HDR_MANIP_IPV6_SRC) -+ { -+ for (i = 0; i < NET_HEADER_FIELD_IPv6_ADDR_SIZE; i += 4) -+ { -+ memcpy(&tmp_ipv6_addr, -+ &p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv6.src[i], -+ sizeof(uint32_t)); -+ WRITE_UINT32(*p_TmpHmct, tmp_ipv6_addr); -+ p_TmpHmct += HMCD_PTR_SIZE / 4; -+ } -+ } -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv6.validUpdates -+ & HDR_MANIP_IPV6_DST) -+ { -+ for (i = 0; i < NET_HEADER_FIELD_IPv6_ADDR_SIZE; i += 4) -+ { -+ memcpy(&tmp_ipv6_addr, -+ &p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.ipv6.dst[i], -+ sizeof(uint32_t)); -+ WRITE_UINT32(*p_TmpHmct, tmp_ipv6_addr); -+ p_TmpHmct += HMCD_PTR_SIZE / 4; -+ } -+ } -+ break; -+ -+ case (e_FM_PCD_MANIP_HDR_FIELD_UPDATE_TCP_UDP): -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.tcpUdp.validUpdates -+ == HDR_MANIP_TCP_UDP_CHECKSUM) -+ { -+ /* we implement this case with the update-checksum descriptor */ -+ /* set opcode */ -+ tmpReg = (uint32_t)(HMCD_OPCODE_TCP_UDP_CHECKSUM) -+ << HMCD_OC_SHIFT; -+ /* write the first 4 bytes of the descriptor */ -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ -+ p_TmpHmct += HMCD_BASIC_SIZE / 4; -+ } -+ else -+ { -+ /* we implement this case with the TCP/UDP update descriptor */ -+ /* set opcode */ -+ tmpReg = (uint32_t)(HMCD_OPCODE_TCP_UDP_UPDATE) -+ << HMCD_OC_SHIFT; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.tcpUdp.validUpdates -+ & HDR_MANIP_TCP_UDP_DST) -+ tmpReg |= HMCD_TCP_UDP_UPDATE_DST; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.tcpUdp.validUpdates -+ & HDR_MANIP_TCP_UDP_SRC) -+ tmpReg |= HMCD_TCP_UDP_UPDATE_SRC; -+ /* write the first 4 bytes of the descriptor */ -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ -+ p_TmpHmct += HMCD_BASIC_SIZE / 4; -+ -+ tmpReg = 0; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.tcpUdp.validUpdates -+ & HDR_MANIP_TCP_UDP_SRC) -+ tmpReg |= -+ ((uint32_t)p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.tcpUdp.src) -+ << HMCD_TCP_UDP_UPDATE_SRC_SHIFT; -+ if (p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.tcpUdp.validUpdates -+ & HDR_MANIP_TCP_UDP_DST) -+ tmpReg |= -+ ((uint32_t)p_FmPcdManipParams->u.hdr.fieldUpdateParams.u.tcpUdp.dst); -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ p_TmpHmct += HMCD_PTR_SIZE / 4; -+ } -+ break; -+ -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, -+ ("Unknown fieldUpdateParams.type")); -+ } -+ } -+ -+ if (p_FmPcdManipParams->u.hdr.custom) -+ { -+ switch (p_FmPcdManipParams->u.hdr.customParams.type) -+ { -+ case (e_FM_PCD_MANIP_HDR_CUSTOM_IP_REPLACE): -+ /* set opcode */ -+ tmpReg = (uint32_t)(HMCD_OPCODE_REPLACE_IP) << HMCD_OC_SHIFT; -+ -+ if (p_FmPcdManipParams->u.hdr.customParams.u.ipHdrReplace.decTtlHl) -+ tmpReg |= HMCD_IP_REPLACE_TTL_HL; -+ if (p_FmPcdManipParams->u.hdr.customParams.u.ipHdrReplace.replaceType -+ == e_FM_PCD_MANIP_HDR_CUSTOM_REPLACE_IPV4_BY_IPV6) -+ /* line commented out as it has no-side-effect ('0' value). */ -+ /*tmpReg |= HMCD_IP_REPLACE_REPLACE_IPV4*/; -+ else -+ if (p_FmPcdManipParams->u.hdr.customParams.u.ipHdrReplace.replaceType -+ == e_FM_PCD_MANIP_HDR_CUSTOM_REPLACE_IPV6_BY_IPV4) -+ { -+ tmpReg |= HMCD_IP_REPLACE_REPLACE_IPV6; -+ if (p_FmPcdManipParams->u.hdr.customParams.u.ipHdrReplace.updateIpv4Id) -+ tmpReg |= HMCD_IP_REPLACE_ID; -+ } -+ else -+ RETURN_ERROR( -+ MINOR, -+ E_NOT_SUPPORTED, -+ ("One flag out of HDR_MANIP_IP_REPLACE_IPV4, HDR_MANIP_IP_REPLACE_IPV6 - must be set.")); -+ -+ /* write the first 4 bytes of the descriptor */ -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ -+ p_TmpHmct += HMCD_BASIC_SIZE / 4; -+ -+ size = -+ p_FmPcdManipParams->u.hdr.customParams.u.ipHdrReplace.hdrSize; -+ ASSERT_COND(p_TmpData); -+ MemCpy8( -+ p_TmpData, -+ p_FmPcdManipParams->u.hdr.customParams.u.ipHdrReplace.hdr, -+ size); -+ tmpReg = (uint32_t)(size << HMCD_IP_REPLACE_L3HDRSIZE_SHIFT); -+ tmpReg |= (uint32_t)(XX_VirtToPhys(p_TmpData) -+ - (((t_FmPcd*)h_FmPcd)->physicalMuramBase)); -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ p_TmpHmct += HMCD_PTR_SIZE / 4; -+ p_TmpData += size; -+ -+ if ((p_FmPcdManipParams->u.hdr.customParams.u.ipHdrReplace.replaceType -+ == e_FM_PCD_MANIP_HDR_CUSTOM_REPLACE_IPV6_BY_IPV4) -+ && (p_FmPcdManipParams->u.hdr.customParams.u.ipHdrReplace.updateIpv4Id)) -+ { -+ WRITE_UINT16( -+ *(uint16_t*)p_TmpData, -+ p_FmPcdManipParams->u.hdr.customParams.u.ipHdrReplace.id); -+ WRITE_UINT32( -+ *p_TmpHmct, -+ (uint32_t)(XX_VirtToPhys(p_TmpData) - (((t_FmPcd*)h_FmPcd)->physicalMuramBase))); -+ p_TmpData += 2; -+ } -+ p_TmpHmct += HMCD_PTR_SIZE / 4; -+ break; -+ case (e_FM_PCD_MANIP_HDR_CUSTOM_GEN_FIELD_REPLACE): -+ /* set opcode */ -+ tmpReg = (uint32_t)(HMCD_OPCODE_GEN_FIELD_REPLACE) << HMCD_OC_SHIFT; -+ tmpReg |= p_FmPcdManipParams->u.hdr.customParams.u.genFieldReplace.size << HMCD_GEN_FIELD_SIZE_SHIFT; -+ tmpReg |= p_FmPcdManipParams->u.hdr.customParams.u.genFieldReplace.srcOffset << HMCD_GEN_FIELD_SRC_OFF_SHIFT; -+ tmpReg |= p_FmPcdManipParams->u.hdr.customParams.u.genFieldReplace.dstOffset << HMCD_GEN_FIELD_DST_OFF_SHIFT; -+ if (p_FmPcdManipParams->u.hdr.customParams.u.genFieldReplace.mask) -+ tmpReg |= HMCD_GEN_FIELD_MASK_EN; -+ -+ /* write the first 4 bytes of the descriptor */ -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ /* save a pointer to the "last" indication word */ -+ p_Last = p_TmpHmct; -+ -+ p_TmpHmct += HMCD_BASIC_SIZE/4; -+ -+ if (p_FmPcdManipParams->u.hdr.customParams.u.genFieldReplace.mask) -+ { -+ tmpReg = p_FmPcdManipParams->u.hdr.customParams.u.genFieldReplace.mask << HMCD_GEN_FIELD_MASK_SHIFT; -+ tmpReg |= p_FmPcdManipParams->u.hdr.customParams.u.genFieldReplace.maskOffset << HMCD_GEN_FIELD_MASK_OFF_SHIFT; -+ /* write the next 4 bytes of the descriptor */ -+ WRITE_UINT32(*p_TmpHmct, tmpReg); -+ } -+ p_TmpHmct += HMCD_PARAM_SIZE/4; -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, -+ ("Unknown customParams.type")); -+ } -+ } -+ -+ /* If this node has a nextManip, and no parsing is required, the old table must be copied to the new table -+ the old table and should be freed */ -+ if (p_FmPcdManipParams->h_NextManip -+ && (p_Manip->nextManipType == e_FM_PCD_MANIP_HDR) -+ && (MANIP_DONT_REPARSE(p_Manip))) -+ { -+ if (new) -+ { -+ /* If this is the first time this manip is created we need to free unused memory. If it -+ * is a dynamic changes case, the memory used is either the CC shadow or the existing -+ * table - no allocation, no free */ -+ MANIP_UPDATE_UNIFIED_POSITION(p_FmPcdManipParams->h_NextManip); -+ -+ p_Manip->unifiedPosition = e_MANIP_UNIFIED_FIRST; -+ } -+ } -+ else -+ { -+ ASSERT_COND(p_Last); -+ /* set the "last" indication on the last command of the current table */ -+ WRITE_UINT32(*p_Last, GET_UINT32(*p_Last) | HMCD_LAST); -+ } -+ -+ return E_OK; -+} -+ -+static t_Error CreateManipActionNew(t_FmPcdManip *p_Manip, -+ t_FmPcdManipParams *p_FmPcdManipParams) -+{ -+ t_FmPcdManip *p_CurManip; -+ t_Error err; -+ uint32_t nextSize = 0, totalSize; -+ uint16_t tmpReg; -+ uint8_t *p_OldHmct, *p_TmpHmctPtr, *p_TmpDataPtr; -+ -+ /* set Manip structure */ -+ -+ p_Manip->dontParseAfterManip = -+ p_FmPcdManipParams->u.hdr.dontParseAfterManip; -+ -+ if (p_FmPcdManipParams->h_NextManip) -+ { /* Next Header manipulation exists */ -+ p_Manip->nextManipType = MANIP_GET_TYPE(p_FmPcdManipParams->h_NextManip); -+ -+ if ((p_Manip->nextManipType == e_FM_PCD_MANIP_HDR) && p_Manip->dontParseAfterManip) -+ nextSize = (uint32_t)(GetHmctSize(p_FmPcdManipParams->h_NextManip) -+ + GetDataSize(p_FmPcdManipParams->h_NextManip)); -+ else /* either parsing is required or next manip is Frag; no table merging. */ -+ p_Manip->cascaded = TRUE; -+ /* pass up the "cascaded" attribute. The whole chain is cascaded -+ * if something is cascaded along the way. */ -+ if (MANIP_IS_CASCADED(p_FmPcdManipParams->h_NextManip)) -+ p_Manip->cascaded = TRUE; -+ } -+ -+ /* Allocate new table */ -+ /* calculate table size according to manip parameters */ -+ err = CalculateTableSize(p_FmPcdManipParams, &p_Manip->tableSize, -+ &p_Manip->dataSize); -+ if (err) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ totalSize = (uint16_t)(p_Manip->tableSize + p_Manip->dataSize + nextSize); -+ -+ p_Manip->p_Hmct = (uint8_t*)FM_MURAM_AllocMem( -+ ((t_FmPcd *)p_Manip->h_FmPcd)->h_FmMuram, totalSize, 4); -+ if (!p_Manip->p_Hmct) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM alloc failed")); -+ -+ if (p_Manip->dataSize) -+ p_Manip->p_Data = -+ (uint8_t*)PTR_MOVE(p_Manip->p_Hmct, (p_Manip->tableSize + nextSize)); -+ -+ /* update shadow size to allow runtime replacement of Header manipulation */ -+ /* The allocated shadow is divided as follows: -+ 0 . . . 16 . . . -+ -------------------------------- -+ | Shadow | Shadow HMTD | -+ | HMTD | Match Table | -+ | (16 bytes) | (maximal size) | -+ -------------------------------- -+ */ -+ -+ err = FmPcdUpdateCcShadow(p_Manip->h_FmPcd, (uint32_t)(totalSize + 16), -+ (uint16_t)FM_PCD_CC_AD_TABLE_ALIGN); -+ if (err != E_OK) -+ { -+ FM_MURAM_FreeMem(p_Manip->h_FmPcd, p_Manip->p_Hmct); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM allocation for HdrManip node shadow")); -+ } -+ -+ if (p_FmPcdManipParams->h_NextManip -+ && (p_Manip->nextManipType == e_FM_PCD_MANIP_HDR) -+ && (MANIP_DONT_REPARSE(p_Manip))) -+ { -+ p_OldHmct = (uint8_t *)GetManipInfo(p_FmPcdManipParams->h_NextManip, -+ e_MANIP_HMCT); -+ p_CurManip = p_FmPcdManipParams->h_NextManip; -+ /* Run till the last Manip (which is the first to configure) */ -+ while (MANIP_IS_UNIFIED_NON_LAST(p_CurManip)) -+ p_CurManip = p_CurManip->h_NextManip; -+ -+ while (p_CurManip) -+ { -+ /* If this is a unified table, point to the part of the table -+ * which is the relative offset in HMCT. -+ */ -+ p_TmpHmctPtr = (uint8_t*)PTR_MOVE(p_Manip->p_Hmct, -+ (p_Manip->tableSize + -+ (PTR_TO_UINT(p_CurManip->p_Hmct) - -+ PTR_TO_UINT(p_OldHmct)))); -+ if (p_CurManip->p_Data) -+ p_TmpDataPtr = (uint8_t*)PTR_MOVE(p_Manip->p_Hmct, -+ (p_Manip->tableSize + -+ (PTR_TO_UINT(p_CurManip->p_Data) - -+ PTR_TO_UINT(p_OldHmct)))); -+ else -+ p_TmpDataPtr = NULL; -+ -+ BuildHmct(p_CurManip, &p_CurManip->manipParams, p_TmpHmctPtr, -+ p_TmpDataPtr, FALSE); -+ /* update old manip table pointer */ -+ MANIP_SET_HMCT_PTR(p_CurManip, p_TmpHmctPtr); -+ MANIP_SET_DATA_PTR(p_CurManip, p_TmpDataPtr); -+ -+ p_CurManip = p_CurManip->h_PrevManip; -+ } -+ /* We copied the HMCT to create a new large HMCT so we can free the old one */ -+ FM_MURAM_FreeMem(MANIP_GET_MURAM(p_FmPcdManipParams->h_NextManip), -+ p_OldHmct); -+ } -+ -+ /* Fill table */ -+ err = BuildHmct(p_Manip, p_FmPcdManipParams, p_Manip->p_Hmct, -+ p_Manip->p_Data, TRUE); -+ if (err) -+ { -+ FM_MURAM_FreeMem(p_Manip->h_FmPcd, p_Manip->p_Hmct); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ /* Build HMTD (table descriptor) */ -+ tmpReg = HMTD_CFG_TYPE; /* NADEN = 0 */ -+ -+ /* add parseAfterManip */ -+ if (!p_Manip->dontParseAfterManip) -+ tmpReg |= HMTD_CFG_PRS_AFTER_HM; -+ -+ /* create cascade */ -+ /*if (p_FmPcdManipParams->h_NextManip -+ && (!MANIP_DONT_REPARSE(p_Manip) || (p_Manip->nextManipType != e_FM_PCD_MANIP_HDR)))*/ -+ if (p_Manip->cascaded) -+ { -+ uint16_t nextAd; -+ /* indicate that there's another HM table descriptor */ -+ tmpReg |= HMTD_CFG_NEXT_AD_EN; -+ /* get address of next HMTD (table descriptor; h_Ad). -+ * If the next HMTD was removed due to table unifing, get the address -+ * of the "next next" as written in the h_Ad of the next h_Manip node. -+ */ -+ if (p_Manip->unifiedPosition != e_MANIP_UNIFIED_FIRST) -+ nextAd = (uint16_t)((uint32_t)(XX_VirtToPhys(MANIP_GET_HMTD_PTR(p_FmPcdManipParams->h_NextManip)) - (((t_FmPcd*)p_Manip->h_FmPcd)->physicalMuramBase)) >> 4); -+ else -+ nextAd = ((t_Hmtd *)((t_FmPcdManip *)p_FmPcdManipParams->h_NextManip)->h_Ad)->nextAdIdx; -+ -+ WRITE_UINT16(((t_Hmtd *)p_Manip->h_Ad)->nextAdIdx, nextAd); -+ } -+ -+ WRITE_UINT16(((t_Hmtd *)p_Manip->h_Ad)->cfg, tmpReg); -+ WRITE_UINT32( -+ ((t_Hmtd *)p_Manip->h_Ad)->hmcdBasePtr, -+ (uint32_t)(XX_VirtToPhys(p_Manip->p_Hmct) - (((t_FmPcd*)p_Manip->h_FmPcd)->physicalMuramBase))); -+ -+ WRITE_UINT8(((t_Hmtd *)p_Manip->h_Ad)->opCode, HMAN_OC); -+ -+ if (p_Manip->unifiedPosition == e_MANIP_UNIFIED_FIRST) -+ { -+ /* The HMTD of the next Manip is never going to be used */ -+ if (((t_FmPcdManip *)p_FmPcdManipParams->h_NextManip)->muramAllocate) -+ FM_MURAM_FreeMem( -+ ((t_FmPcd *)((t_FmPcdManip *)p_FmPcdManipParams->h_NextManip)->h_FmPcd)->h_FmMuram, -+ ((t_FmPcdManip *)p_FmPcdManipParams->h_NextManip)->h_Ad); -+ else -+ XX_Free(((t_FmPcdManip *)p_FmPcdManipParams->h_NextManip)->h_Ad); -+ ((t_FmPcdManip *)p_FmPcdManipParams->h_NextManip)->h_Ad = NULL; -+ } -+ -+ return E_OK; -+} -+ -+static t_Error CreateManipActionShadow(t_FmPcdManip *p_Manip, -+ t_FmPcdManipParams *p_FmPcdManipParams) -+{ -+ uint8_t *p_WholeHmct, *p_TmpHmctPtr, newDataSize, *p_TmpDataPtr = NULL; -+ uint16_t newSize; -+ t_FmPcd *p_FmPcd = (t_FmPcd *)p_Manip->h_FmPcd; -+ t_Error err; -+ t_FmPcdManip *p_CurManip = p_Manip; -+ -+ err = CalculateTableSize(p_FmPcdManipParams, &newSize, &newDataSize); -+ if (err) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ /* check coherency of new table parameters */ -+ if (newSize > p_Manip->tableSize) -+ RETURN_ERROR( -+ MINOR, -+ E_INVALID_VALUE, -+ ("New Hdr Manip configuration requires larger size than current one (command table).")); -+ if (newDataSize > p_Manip->dataSize) -+ RETURN_ERROR( -+ MINOR, -+ E_INVALID_VALUE, -+ ("New Hdr Manip configuration requires larger size than current one (data).")); -+ if (p_FmPcdManipParams->h_NextManip) -+ RETURN_ERROR( -+ MINOR, E_INVALID_VALUE, -+ ("New Hdr Manip configuration can not contain h_NextManip.")); -+ if (MANIP_IS_UNIFIED(p_Manip) && (newSize != p_Manip->tableSize)) -+ RETURN_ERROR( -+ MINOR, -+ E_INVALID_VALUE, -+ ("New Hdr Manip configuration in a chained manipulation requires different size than current one.")); -+ if (p_Manip->dontParseAfterManip -+ != p_FmPcdManipParams->u.hdr.dontParseAfterManip) -+ RETURN_ERROR( -+ MINOR, -+ E_INVALID_VALUE, -+ ("New Hdr Manip configuration differs in dontParseAfterManip value.")); -+ -+ p_Manip->tableSize = newSize; -+ p_Manip->dataSize = newDataSize; -+ -+ /* Build the new table in the shadow */ -+ if (!MANIP_IS_UNIFIED(p_Manip)) -+ { -+ p_TmpHmctPtr = (uint8_t*)PTR_MOVE(p_FmPcd->p_CcShadow, 16); -+ if (p_Manip->p_Data) -+ p_TmpDataPtr = -+ (uint8_t*)PTR_MOVE(p_TmpHmctPtr, -+ (PTR_TO_UINT(p_Manip->p_Data) - PTR_TO_UINT(p_Manip->p_Hmct))); -+ -+ BuildHmct(p_Manip, p_FmPcdManipParams, p_TmpHmctPtr, p_Manip->p_Data, -+ FALSE); -+ } -+ else -+ { -+ p_WholeHmct = (uint8_t *)GetManipInfo(p_Manip, e_MANIP_HMCT); -+ ASSERT_COND(p_WholeHmct); -+ -+ /* Run till the last Manip (which is the first to configure) */ -+ while (MANIP_IS_UNIFIED_NON_LAST(p_CurManip)) -+ p_CurManip = p_CurManip->h_NextManip; -+ -+ while (p_CurManip) -+ { -+ /* If this is a non-head node in a unified table, point to the part of the shadow -+ * which is the relative offset in HMCT. -+ * else, point to the beginning of the -+ * shadow table (we save 16 for the HMTD. -+ */ -+ p_TmpHmctPtr = -+ (uint8_t*)PTR_MOVE(p_FmPcd->p_CcShadow, -+ (16 + PTR_TO_UINT(p_CurManip->p_Hmct) - PTR_TO_UINT(p_WholeHmct))); -+ if (p_CurManip->p_Data) -+ p_TmpDataPtr = -+ (uint8_t*)PTR_MOVE(p_FmPcd->p_CcShadow, -+ (16 + PTR_TO_UINT(p_CurManip->p_Data) - PTR_TO_UINT(p_WholeHmct))); -+ -+ BuildHmct(p_CurManip, &p_CurManip->manipParams, p_TmpHmctPtr, -+ p_TmpDataPtr, FALSE); -+ p_CurManip = p_CurManip->h_PrevManip; -+ } -+ } -+ -+ return E_OK; -+} -+ -+static t_Error CreateManipActionBackToOrig( -+ t_FmPcdManip *p_Manip, t_FmPcdManipParams *p_FmPcdManipParams) -+{ -+ uint8_t *p_WholeHmct = NULL, *p_TmpHmctPtr, *p_TmpDataPtr; -+ t_FmPcdManip *p_CurManip = p_Manip; -+ -+ /* Build the new table in the shadow */ -+ if (!MANIP_IS_UNIFIED(p_Manip)) -+ BuildHmct(p_Manip, p_FmPcdManipParams, p_Manip->p_Hmct, p_Manip->p_Data, -+ FALSE); -+ else -+ { -+ p_WholeHmct = (uint8_t *)GetManipInfo(p_Manip, e_MANIP_HMCT); -+ ASSERT_COND(p_WholeHmct); -+ -+ /* Run till the last Manip (which is the first to configure) */ -+ while (MANIP_IS_UNIFIED_NON_LAST(p_CurManip)) -+ p_CurManip = p_CurManip->h_NextManip; -+ -+ while (p_CurManip) -+ { -+ /* If this is a unified table, point to the part of the table -+ * which is the relative offset in HMCT. -+ */ -+ p_TmpHmctPtr = p_CurManip->p_Hmct; /*- (uint32_t)p_WholeHmct*/ -+ p_TmpDataPtr = p_CurManip->p_Data; /*- (uint32_t)p_WholeHmct*/ -+ -+ BuildHmct(p_CurManip, &p_CurManip->manipParams, p_TmpHmctPtr, -+ p_TmpDataPtr, FALSE); -+ -+ p_CurManip = p_CurManip->h_PrevManip; -+ } -+ } -+ -+ return E_OK; -+} -+ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+static t_Error UpdateManipIc(t_Handle h_Manip, uint8_t icOffset) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_Manip; -+ t_Handle p_Ad; -+ uint32_t tmpReg32 = 0; -+ SANITY_CHECK_RETURN_ERROR(h_Manip, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_Ad, E_INVALID_HANDLE); -+ -+ switch (p_Manip->opcode) -+ { -+ case (HMAN_OC_MV_INT_FRAME_HDR_FROM_FRM_TO_BUFFER_PREFFIX): -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ if (p_Manip->updateParams & INTERNAL_CONTEXT_OFFSET) -+ { -+ tmpReg32 = -+ *(uint32_t *)&((t_AdOfTypeContLookup *)p_Ad)->pcAndOffsets; -+ tmpReg32 |= (uint32_t)((uint32_t)icOffset << 16); -+ *(uint32_t *)&((t_AdOfTypeContLookup *)p_Ad)->pcAndOffsets = -+ tmpReg32; -+ p_Manip->updateParams &= ~INTERNAL_CONTEXT_OFFSET; -+ p_Manip->icOffset = icOffset; -+ } -+ else -+ { -+ if (p_Manip->icOffset != icOffset) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("this manipulation was updated previously by different value");); -+ } -+ break; -+ case (HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST): -+ if (p_Manip->h_Frag) -+ { -+ if (p_Manip->updateParams & INTERNAL_CONTEXT_OFFSET) -+ { -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ tmpReg32 |= GET_UINT32(((t_AdOfTypeContLookup *)p_Ad)->pcAndOffsets); -+ tmpReg32 |= (uint32_t)((uint32_t)icOffset << 16); -+ WRITE_UINT32(((t_AdOfTypeContLookup *)p_Ad)->pcAndOffsets, tmpReg32); -+ p_Manip->updateParams &= ~INTERNAL_CONTEXT_OFFSET; -+ p_Manip->icOffset = icOffset; -+ } -+ else -+ { -+ if (p_Manip->icOffset != icOffset) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("this manipulation was updated previousely by different value");); -+ } -+ } -+ break; -+ } -+ -+ return E_OK; -+} -+ -+static t_Error UpdateInitMvIntFrameHeaderFromFrameToBufferPrefix( -+ t_Handle h_FmPort, t_FmPcdManip *p_Manip, t_Handle h_Ad, bool validate) -+{ -+ -+ t_AdOfTypeContLookup *p_Ad = (t_AdOfTypeContLookup *)h_Ad; -+ t_FmPortGetSetCcParams fmPortGetSetCcParams; -+ t_Error err; -+ uint32_t tmpReg32; -+ -+ memset(&fmPortGetSetCcParams, 0, sizeof(t_FmPortGetSetCcParams)); -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR( -+ (p_Manip->opcode & HMAN_OC_MV_INT_FRAME_HDR_FROM_FRM_TO_BUFFER_PREFFIX), -+ E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_Manip->muramAllocate, E_INVALID_STATE); -+ -+ if (p_Manip->updateParams) -+ { -+ if ((!(p_Manip->updateParams & OFFSET_OF_PR)) -+ || (p_Manip->shadowUpdateParams & OFFSET_OF_PR)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_STATE, -+ ("in this stage parameters from Port has not be updated")); -+ -+ fmPortGetSetCcParams.getCcParams.type = p_Manip->updateParams; -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_PSO; -+ fmPortGetSetCcParams.setCcParams.psoSize = 16; -+ -+ err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ if (fmPortGetSetCcParams.getCcParams.type & OFFSET_OF_PR) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_STATE, -+ ("Parser result offset wasn't configured previousely")); -+#ifdef FM_LOCKUP_ALIGNMENT_ERRATA_FMAN_SW004 -+ ASSERT_COND(!(fmPortGetSetCcParams.getCcParams.prOffset % 16)); -+#endif -+ } -+ else -+ if (validate) -+ { -+ if ((!(p_Manip->shadowUpdateParams & OFFSET_OF_PR)) -+ || (p_Manip->updateParams & OFFSET_OF_PR)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_STATE, -+ ("in this stage parameters from Port has be updated")); -+ fmPortGetSetCcParams.getCcParams.type = p_Manip->shadowUpdateParams; -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_PSO; -+ fmPortGetSetCcParams.setCcParams.psoSize = 16; -+ -+ err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ if (fmPortGetSetCcParams.getCcParams.type & OFFSET_OF_PR) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_STATE, -+ ("Parser result offset wasn't configured previousely")); -+ -+ } -+ -+ ASSERT_COND(p_Ad); -+ -+ if (p_Manip->updateParams & OFFSET_OF_PR) -+ { -+ tmpReg32 = 0; -+ tmpReg32 |= fmPortGetSetCcParams.getCcParams.prOffset; -+ WRITE_UINT32(p_Ad->matchTblPtr, -+ (GET_UINT32(p_Ad->matchTblPtr) | tmpReg32)); -+ p_Manip->updateParams &= ~OFFSET_OF_PR; -+ p_Manip->shadowUpdateParams |= OFFSET_OF_PR; -+ } -+ else -+ if (validate) -+ { -+ tmpReg32 = GET_UINT32(p_Ad->matchTblPtr); -+ if ((uint8_t)tmpReg32 != fmPortGetSetCcParams.getCcParams.prOffset) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("this manipulation was updated previousely by different value");); -+ } -+ -+ return E_OK; -+} -+ -+static t_Error UpdateModifyCapwapFragmenation(t_FmPcdManip *p_Manip, t_Handle h_Ad, bool validate,t_Handle h_FmTree) -+{ -+ t_AdOfTypeContLookup *p_Ad = (t_AdOfTypeContLookup *)h_Ad; -+ t_FmPcdCcSavedManipParams *p_SavedManipParams = NULL; -+ uint32_t tmpReg32 = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip,E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_Frag,E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Manip->frag,E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(((p_Manip->opcode == HMAN_OC_CAPWAP_FRAGMENTATION) || (p_Manip->opcode == HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER)), E_INVALID_STATE); -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Frag; -+ -+ if (p_Manip->updateParams) -+ { -+ -+ if ((!(p_Manip->updateParams & OFFSET_OF_DATA)) || -+ ((p_Manip->shadowUpdateParams & OFFSET_OF_DATA))) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("in this stage parameters from Port has not be updated")); -+ p_SavedManipParams = FmPcdCcTreeGetSavedManipParams(h_FmTree); -+ if (!p_SavedManipParams) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("for this manipulation tree has to be configured previosely with this type")); -+ p_Manip->capwapFragParams.dataOffset = p_SavedManipParams->capwapParams.dataOffset; -+ -+ tmpReg32 = GET_UINT32(p_Ad->pcAndOffsets); -+ tmpReg32 |= ((uint32_t)p_Manip->capwapFragParams.dataOffset<< 16); -+ WRITE_UINT32(p_Ad->pcAndOffsets,tmpReg32); -+ -+ p_Manip->updateParams &= ~OFFSET_OF_DATA; -+ p_Manip->shadowUpdateParams |= OFFSET_OF_DATA; -+ } -+ else if (validate) -+ { -+ -+ p_SavedManipParams = FmPcdCcTreeGetSavedManipParams(h_FmTree); -+ if (!p_SavedManipParams) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("for this manipulation tree has to be configured previosely with this type")); -+ if (p_Manip->capwapFragParams.dataOffset != p_SavedManipParams->capwapParams.dataOffset) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("this manipulation was updated previousely by different value")); -+ } -+ -+ return E_OK; -+} -+ -+static t_Error UpdateInitCapwapFragmentation(t_Handle h_FmPort, -+ t_FmPcdManip *p_Manip, -+ t_Handle h_Ad, -+ bool validate, -+ t_Handle h_FmTree) -+{ -+ t_AdOfTypeContLookup *p_Ad; -+ t_FmPortGetSetCcParams fmPortGetSetCcParams; -+ t_Error err; -+ uint32_t tmpReg32 = 0; -+ t_FmPcdCcSavedManipParams *p_SavedManipParams; -+ -+ UNUSED(h_Ad); -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip,E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_Frag,E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Manip->frag,E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(((p_Manip->opcode == HMAN_OC_CAPWAP_FRAGMENTATION) || -+ (p_Manip->opcode == HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER)), E_INVALID_STATE); -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Frag; -+ -+ if (p_Manip->updateParams) -+ { -+ if ((!(p_Manip->updateParams & OFFSET_OF_DATA)) || -+ ((p_Manip->shadowUpdateParams & OFFSET_OF_DATA))) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("in this stage parameters from Port has not be updated")); -+ fmPortGetSetCcParams.getCcParams.type = p_Manip->updateParams; -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_NIA_PNEN | UPDATE_FMFP_PRC_WITH_ONE_RISC_ONLY; -+ fmPortGetSetCcParams.setCcParams.nia = NIA_FM_CTL_AC_POP_TO_N_STEP | NIA_ENG_FM_CTL; -+ /* For CAPWAP Rassembly used FMAN_CTRL2 hardcoded - so for fragmentation its better to use FMAN_CTRL1 */ -+ fmPortGetSetCcParams.setCcParams.orFmanCtrl = FPM_PORT_FM_CTL1; -+ -+ err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (fmPortGetSetCcParams.getCcParams.type & OFFSET_OF_DATA) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Data offset wasn't configured previousely")); -+ -+ p_SavedManipParams = (t_FmPcdCcSavedManipParams *)XX_Malloc(sizeof(t_FmPcdCcSavedManipParams)); -+ p_SavedManipParams->capwapParams.dataOffset = fmPortGetSetCcParams.getCcParams.dataOffset; -+ -+#ifdef FM_LOCKUP_ALIGNMENT_ERRATA_FMAN_SW004 -+ ASSERT_COND(!(p_SavedManipParams->capwapParams.dataOffset % 16)); -+#endif /* FM_LOCKUP_ALIGNMENT_ERRATA_FMAN_SW004 */ -+ -+ FmPcdCcTreeSetSavedManipParams(h_FmTree, (t_Handle)p_SavedManipParams); -+ } -+ else if (validate) -+ { -+ if ((!(p_Manip->shadowUpdateParams & OFFSET_OF_DATA)) || -+ ((p_Manip->updateParams & OFFSET_OF_DATA))) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("in this stage parameters from Port has be updated")); -+ fmPortGetSetCcParams.getCcParams.type = p_Manip->shadowUpdateParams; -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_NIA_PNEN | UPDATE_FMFP_PRC_WITH_ONE_RISC_ONLY; -+ fmPortGetSetCcParams.setCcParams.nia = NIA_FM_CTL_AC_POP_TO_N_STEP | NIA_ENG_FM_CTL; -+ err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (fmPortGetSetCcParams.getCcParams.type & OFFSET_OF_DATA) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Data offset wasn't configured previousely")); -+ } -+ -+ if (p_Manip->updateParams) -+ { -+ tmpReg32 = GET_UINT32(p_Ad->pcAndOffsets); -+ tmpReg32 |= ((uint32_t)fmPortGetSetCcParams.getCcParams.dataOffset<< 16); -+ WRITE_UINT32(p_Ad->pcAndOffsets,tmpReg32); -+ -+ p_Manip->updateParams &= ~OFFSET_OF_DATA; -+ p_Manip->shadowUpdateParams |= OFFSET_OF_DATA; -+ p_Manip->capwapFragParams.dataOffset = fmPortGetSetCcParams.getCcParams.dataOffset; -+ } -+ else if (validate) -+ { -+ if (p_Manip->capwapFragParams.dataOffset != fmPortGetSetCcParams.getCcParams.dataOffset) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("this manipulation was updated previousely by different value")); -+ } -+ -+ return E_OK; -+} -+ -+static t_Error UpdateInitCapwapReasm(t_Handle h_FmPcd, -+ t_Handle h_FmPort, -+ t_FmPcdManip *p_Manip, -+ t_Handle h_Ad, -+ bool validate) -+{ -+ t_CapwapReasmPram *p_ReassmTbl; -+ t_Error err; -+ t_FmPortGetSetCcParams fmPortGetSetCcParams; -+ uint8_t i = 0; -+ uint16_t size; -+ uint32_t tmpReg32; -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ t_FmPcdCcCapwapReassmTimeoutParams ccCapwapReassmTimeoutParams; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip,E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_Frag,E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Manip->frag,E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Manip->opcode == HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST), E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(h_FmPcd,E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->h_Hc,E_INVALID_HANDLE); -+ -+ if (p_Manip->h_FmPcd != h_FmPcd) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("handler of PCD previously was initiated by different value")); -+ -+ UNUSED(h_Ad); -+ -+ memset(&fmPortGetSetCcParams, 0, sizeof(t_FmPortGetSetCcParams)); -+ p_ReassmTbl = (t_CapwapReasmPram *)p_Manip->h_Frag; -+ -+ if (p_Manip->updateParams) -+ { -+ if ((!(p_Manip->updateParams & NUM_OF_TASKS) && -+ !(p_Manip->updateParams & OFFSET_OF_DATA) && -+ !(p_Manip->updateParams & OFFSET_OF_PR) && -+ !(p_Manip->updateParams & HW_PORT_ID)) || -+ ((p_Manip->shadowUpdateParams & NUM_OF_TASKS) || -+ (p_Manip->shadowUpdateParams & OFFSET_OF_DATA) || (p_Manip->shadowUpdateParams & OFFSET_OF_PR) || -+ (p_Manip->shadowUpdateParams & HW_PORT_ID))) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("in this stage parameters from Port has not be updated")); -+ -+ fmPortGetSetCcParams.getCcParams.type = p_Manip->updateParams; -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_NIA_PNEN; -+ fmPortGetSetCcParams.setCcParams.nia = NIA_FM_CTL_AC_POP_TO_N_STEP | NIA_ENG_FM_CTL; -+ -+ err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (fmPortGetSetCcParams.getCcParams.type & NUM_OF_TASKS) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Num of tasks wasn't configured previousely")); -+ if (fmPortGetSetCcParams.getCcParams.type & OFFSET_OF_DATA) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("offset of the data wasn't configured previousely")); -+ if (fmPortGetSetCcParams.getCcParams.type & HW_PORT_ID) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("hwPortId wasn't updated")); -+#ifdef FM_LOCKUP_ALIGNMENT_ERRATA_FMAN_SW004 -+ ASSERT_COND((fmPortGetSetCcParams.getCcParams.dataOffset % 16) == 0); -+#endif /* FM_LOCKUP_ALIGNMENT_ERRATA_FMAN_SW004 */ -+ } -+ else if (validate) -+ { -+ if ((!(p_Manip->shadowUpdateParams & NUM_OF_TASKS) && -+ !(p_Manip->shadowUpdateParams & OFFSET_OF_DATA) && -+ !(p_Manip->shadowUpdateParams & OFFSET_OF_PR) && -+ !(p_Manip->shadowUpdateParams & HW_PORT_ID)) && -+ ((p_Manip->updateParams & NUM_OF_TASKS) || -+ (p_Manip->updateParams & OFFSET_OF_DATA) || (p_Manip->updateParams & OFFSET_OF_PR) || -+ (p_Manip->updateParams & HW_PORT_ID))) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("in this stage parameters from Port has be updated")); -+ -+ fmPortGetSetCcParams.getCcParams.type = p_Manip->shadowUpdateParams; -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_NIA_PNEN; -+ fmPortGetSetCcParams.setCcParams.nia = NIA_FM_CTL_AC_POP_TO_N_STEP | NIA_ENG_FM_CTL; -+ -+ err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (fmPortGetSetCcParams.getCcParams.type & NUM_OF_TASKS) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("NumOfTasks wasn't configured previously")); -+ if (fmPortGetSetCcParams.getCcParams.type & OFFSET_OF_DATA) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("offset of the data wasn't configured previously")); -+ if (fmPortGetSetCcParams.getCcParams.type & HW_PORT_ID) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("hwPortId wasn't updated")); -+ } -+ -+ if (p_Manip->updateParams) -+ { -+ if (p_Manip->updateParams & NUM_OF_TASKS) -+ { -+ /*recommendation of Microcode team - (maxNumFramesInProcess * 2) */ -+ size = (uint16_t)(p_Manip->capwapFragParams.maxNumFramesInProcess*2 + fmPortGetSetCcParams.getCcParams.numOfTasks); -+ if (size > 255) -+ RETURN_ERROR(MAJOR,E_INVALID_VALUE, ("numOfOpenReassmEntries + numOfTasks per port can not be greater than 256")); -+ -+ p_Manip->capwapFragParams.numOfTasks = fmPortGetSetCcParams.getCcParams.numOfTasks; -+ -+ /*p_ReassmFrmDescrIndxPoolTbl*/ -+ p_Manip->capwapFragParams.p_ReassmFrmDescrIndxPoolTbl = -+ (t_Handle)FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, -+ (uint32_t)(size + 1), -+ 4); -+ if (!p_Manip->capwapFragParams.p_ReassmFrmDescrIndxPoolTbl) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM alloc for CAPWAP Reassembly frame buffer index pool table")); -+ -+ MemSet8(p_Manip->capwapFragParams.p_ReassmFrmDescrIndxPoolTbl, 0, (uint32_t)(size + 1)); -+ -+ for ( i = 0; i < size; i++) -+ WRITE_UINT8(*(uint8_t *)PTR_MOVE(p_Manip->capwapFragParams.p_ReassmFrmDescrIndxPoolTbl, i), (uint8_t)(i+1)); -+ -+ tmpReg32 = (uint32_t)(XX_VirtToPhys(p_Manip->capwapFragParams.p_ReassmFrmDescrIndxPoolTbl) - p_FmPcd->physicalMuramBase); -+ -+ WRITE_UINT32(p_ReassmTbl->reasmFrmDescIndexPoolTblPtr, tmpReg32); -+ -+ /*p_ReassmFrmDescrPoolTbl*/ -+ p_Manip->capwapFragParams.p_ReassmFrmDescrPoolTbl = -+ (t_Handle)FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, -+ (uint32_t)((size + 1) * FM_PCD_MANIP_CAPWAP_REASM_RFD_SIZE), -+ 4); -+ -+ if (!p_Manip->capwapFragParams.p_ReassmFrmDescrPoolTbl) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM alloc for CAPWAP Reassembly frame buffer pool table")); -+ -+ MemSet8(p_Manip->capwapFragParams.p_ReassmFrmDescrPoolTbl, 0, (uint32_t)((size +1)* FM_PCD_MANIP_CAPWAP_REASM_RFD_SIZE)); -+ -+ tmpReg32 = (uint32_t)(XX_VirtToPhys(p_Manip->capwapFragParams.p_ReassmFrmDescrPoolTbl) - p_FmPcd->physicalMuramBase); -+ -+ WRITE_UINT32(p_ReassmTbl->reasmFrmDescPoolTblPtr, tmpReg32); -+ -+ /*p_TimeOutTbl*/ -+ -+ p_Manip->capwapFragParams.p_TimeOutTbl = -+ (t_Handle)FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, -+ (uint32_t)((size + 1)* FM_PCD_MANIP_CAPWAP_REASM_TIME_OUT_ENTRY_SIZE), -+ 4); -+ -+ if (!p_Manip->capwapFragParams.p_TimeOutTbl) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM alloc for CAPWAP Reassembly timeout table")); -+ -+ MemSet8(p_Manip->capwapFragParams.p_TimeOutTbl, 0, (uint16_t)((size + 1)*FM_PCD_MANIP_CAPWAP_REASM_TIME_OUT_ENTRY_SIZE)); -+ -+ tmpReg32 = (uint32_t)(XX_VirtToPhys(p_Manip->capwapFragParams.p_TimeOutTbl) - p_FmPcd->physicalMuramBase); -+ WRITE_UINT32(p_ReassmTbl->timeOutTblPtr, tmpReg32); -+ -+ p_Manip->updateParams &= ~NUM_OF_TASKS; -+ p_Manip->shadowUpdateParams |= NUM_OF_TASKS; -+ } -+ -+ if (p_Manip->updateParams & OFFSET_OF_DATA) -+ { -+ p_Manip->capwapFragParams.dataOffset = fmPortGetSetCcParams.getCcParams.dataOffset; -+ tmpReg32 = GET_UINT32(p_ReassmTbl->mode); -+ tmpReg32|= p_Manip->capwapFragParams.dataOffset; -+ WRITE_UINT32(p_ReassmTbl->mode, tmpReg32); -+ p_Manip->updateParams &= ~OFFSET_OF_DATA; -+ p_Manip->shadowUpdateParams |= OFFSET_OF_DATA; -+ } -+ -+ if (!(fmPortGetSetCcParams.getCcParams.type & OFFSET_OF_PR)) -+ { -+ p_Manip->capwapFragParams.prOffset = fmPortGetSetCcParams.getCcParams.prOffset; -+ -+ tmpReg32 = GET_UINT32(p_ReassmTbl->mode); -+ tmpReg32|= FM_PCD_MANIP_CAPWAP_REASM_PR_COPY; -+ WRITE_UINT32(p_ReassmTbl->mode, tmpReg32); -+ -+ tmpReg32 = GET_UINT32(p_ReassmTbl->intStatsTblPtr); -+ tmpReg32 |= (uint32_t)p_Manip->capwapFragParams.prOffset << 24; -+ WRITE_UINT32(p_ReassmTbl->intStatsTblPtr, tmpReg32); -+ p_Manip->updateParams &= ~OFFSET_OF_PR; -+ p_Manip->shadowUpdateParams |= OFFSET_OF_PR; -+ } -+ else -+ { -+ p_Manip->capwapFragParams.prOffset = 0xff; -+ p_Manip->updateParams &= ~OFFSET_OF_PR; -+ p_Manip->shadowUpdateParams |= OFFSET_OF_PR; -+ } -+ -+ p_Manip->capwapFragParams.hwPortId = fmPortGetSetCcParams.getCcParams.hardwarePortId; -+ p_Manip->updateParams &= ~HW_PORT_ID; -+ p_Manip->shadowUpdateParams |= HW_PORT_ID; -+ -+ /*timeout hc */ -+ ccCapwapReassmTimeoutParams.fqidForTimeOutFrames = p_Manip->capwapFragParams.fqidForTimeOutFrames; -+ ccCapwapReassmTimeoutParams.portIdAndCapwapReassmTbl = (uint32_t)p_Manip->capwapFragParams.hwPortId << 24; -+ ccCapwapReassmTimeoutParams.portIdAndCapwapReassmTbl |= (uint32_t)((XX_VirtToPhys(p_ReassmTbl) - p_FmPcd->physicalMuramBase)); -+ ccCapwapReassmTimeoutParams.timeoutRequestTime = (((uint32_t)1<capwapFragParams.bitFor1Micro) * p_Manip->capwapFragParams.timeoutRoutineRequestTime)/2; -+ return FmHcPcdCcCapwapTimeoutReassm(p_FmPcd->h_Hc,&ccCapwapReassmTimeoutParams); -+ } -+ -+ else if (validate) -+ { -+ if (fmPortGetSetCcParams.getCcParams.hardwarePortId != p_Manip->capwapFragParams.hwPortId) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Reassembly manipulation previously was assigned to another port")); -+ if (fmPortGetSetCcParams.getCcParams.numOfTasks != p_Manip->capwapFragParams.numOfTasks) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numOfTasks for this manipulation previously was defined by another value ")); -+ -+ if (!(fmPortGetSetCcParams.getCcParams.type & OFFSET_OF_PR)) -+ { -+ if (p_Manip->capwapFragParams.prOffset != fmPortGetSetCcParams.getCcParams.prOffset) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Parse result offset previously was defined by another value ")); -+ } -+ else -+ { -+ if (p_Manip->capwapFragParams.prOffset != 0xff) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Parse result offset previously was defined by another value ")); -+ } -+ if (fmPortGetSetCcParams.getCcParams.dataOffset != p_Manip->capwapFragParams.dataOffset) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Data offset previously was defined by another value ")); -+ } -+ -+ return E_OK; -+} -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ -+t_Error FmPcdRegisterReassmPort(t_Handle h_FmPcd, t_Handle h_ReasmCommonPramTbl) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_FmPcdCcReassmTimeoutParams ccReassmTimeoutParams = { 0 }; -+ t_Error err = E_OK; -+ uint8_t result; -+ uint32_t bitFor1Micro, tsbs, log2num; -+ -+ ASSERT_COND(p_FmPcd); -+ ASSERT_COND(h_ReasmCommonPramTbl); -+ -+ bitFor1Micro = FmGetTimeStampScale(p_FmPcd->h_Fm); -+ if (bitFor1Micro == 0) -+ RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, ("Timestamp scale")); -+ -+ bitFor1Micro = 32 - bitFor1Micro; -+ LOG2(FM_PCD_MANIP_REASM_TIMEOUT_THREAD_THRESH, log2num); -+ tsbs = bitFor1Micro - log2num; -+ -+ ccReassmTimeoutParams.iprcpt = (uint32_t)(XX_VirtToPhys( -+ h_ReasmCommonPramTbl) - p_FmPcd->physicalMuramBase); -+ ccReassmTimeoutParams.tsbs = (uint8_t)tsbs; -+ ccReassmTimeoutParams.activate = TRUE; -+ if ((err = FmHcPcdCcTimeoutReassm(p_FmPcd->h_Hc, &ccReassmTimeoutParams, -+ &result)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ switch (result) -+ { -+ case (0): -+ return E_OK; -+ case (1): -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("failed to allocate TNUM")); -+ case (2): -+ RETURN_ERROR( -+ MAJOR, E_NO_MEMORY, -+ ("failed to allocate internal buffer from the HC-Port")); -+ case (3): -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("'Disable Timeout Task' with invalid IPRCPT")); -+ case (4): -+ RETURN_ERROR(MAJOR, E_FULL, ("too many timeout tasks")); -+ case (5): -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("invalid sub command")); -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); -+ } -+ return E_OK; -+} -+ -+static t_Error CreateReassCommonTable(t_FmPcdManip *p_Manip) -+{ -+ uint32_t tmpReg32 = 0, i, bitFor1Micro; -+ uint64_t tmpReg64, size; -+ t_FmPcd *p_FmPcd = (t_FmPcd *)p_Manip->h_FmPcd; -+ t_Error err = E_OK; -+ -+ bitFor1Micro = FmGetTimeStampScale(p_FmPcd->h_Fm); -+ if (bitFor1Micro == 0) -+ RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, ("Timestamp scale")); -+ -+ /* Allocation of the Reassembly Common Parameters table. This table is located in the -+ MURAM. Its size is 64 bytes and its base address should be 8-byte aligned. */ -+ p_Manip->reassmParams.p_ReassCommonTbl = -+ (t_ReassCommonTbl *)FM_MURAM_AllocMem( -+ p_FmPcd->h_FmMuram, -+ FM_PCD_MANIP_REASM_COMMON_PARAM_TABLE_SIZE, -+ FM_PCD_MANIP_REASM_COMMON_PARAM_TABLE_ALIGN); -+ -+ if (!p_Manip->reassmParams.p_ReassCommonTbl) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM alloc for Reassembly common parameters table")); -+ -+ MemSet8(p_Manip->reassmParams.p_ReassCommonTbl, 0, -+ FM_PCD_MANIP_REASM_COMMON_PARAM_TABLE_SIZE); -+ -+ /* Setting the TimeOut Mode.*/ -+ tmpReg32 = 0; -+ if (p_Manip->reassmParams.timeOutMode -+ == e_FM_PCD_MANIP_TIME_OUT_BETWEEN_FRAMES) -+ tmpReg32 |= FM_PCD_MANIP_REASM_TIME_OUT_BETWEEN_FRAMES; -+ -+ /* Setting TimeOut FQID - Frames that time out are enqueued to this FQID. -+ In order to cause TimeOut frames to be discarded, this queue should be configured accordingly*/ -+ tmpReg32 |= p_Manip->reassmParams.fqidForTimeOutFrames; -+ WRITE_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->timeoutModeAndFqid, -+ tmpReg32); -+ -+ /* Calculation the size of IP Reassembly Frame Descriptor - number of frames that are allowed to be reassembled simultaneously + 129.*/ -+ size = p_Manip->reassmParams.maxNumFramesInProcess + 129; -+ -+ /*Allocation of IP Reassembly Frame Descriptor Indexes Pool - This pool resides in the MURAM */ -+ p_Manip->reassmParams.reassFrmDescrIndxPoolTblAddr = -+ PTR_TO_UINT(FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, -+ (uint32_t)(size * 2), -+ 256)); -+ if (!p_Manip->reassmParams.reassFrmDescrIndxPoolTblAddr) -+ RETURN_ERROR( -+ MAJOR, E_NO_MEMORY, -+ ("MURAM alloc for Reassembly frame descriptor indexes pool")); -+ -+ MemSet8(UINT_TO_PTR(p_Manip->reassmParams.reassFrmDescrIndxPoolTblAddr), -+ 0, (uint32_t)(size * 2)); -+ -+ /* The entries in IP Reassembly Frame Descriptor Indexes Pool contains indexes starting with 1 up to -+ the maximum number of frames that are allowed to be reassembled simultaneously + 128. -+ The last entry in this pool must contain the index zero*/ -+ for (i = 0; i < (size - 1); i++) -+ WRITE_UINT16( -+ *(uint16_t *)PTR_MOVE(UINT_TO_PTR(p_Manip->reassmParams.reassFrmDescrIndxPoolTblAddr), (i<<1)), -+ (uint16_t)(i+1)); -+ -+ /* Sets the IP Reassembly Frame Descriptor Indexes Pool offset from MURAM */ -+ tmpReg32 = (uint32_t)(XX_VirtToPhys( -+ UINT_TO_PTR(p_Manip->reassmParams.reassFrmDescrIndxPoolTblAddr)) -+ - p_FmPcd->physicalMuramBase); -+ WRITE_UINT32( -+ p_Manip->reassmParams.p_ReassCommonTbl->reassFrmDescIndexPoolTblPtr, -+ tmpReg32); -+ -+ /* Allocation of the Reassembly Frame Descriptors Pool - This pool resides in external memory. -+ The number of entries in this pool should be equal to the number of entries in IP Reassembly Frame Descriptor Indexes Pool.*/ -+ p_Manip->reassmParams.reassFrmDescrPoolTblAddr = -+ PTR_TO_UINT(XX_MallocSmart((uint32_t)(size * 64), p_Manip->reassmParams.dataMemId, 64)); -+ -+ if (!p_Manip->reassmParams.reassFrmDescrPoolTblAddr) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory allocation FAILED")); -+ -+ MemSet8(UINT_TO_PTR(p_Manip->reassmParams.reassFrmDescrPoolTblAddr), 0, -+ (uint32_t)(size * 64)); -+ -+ /* Sets the Reassembly Frame Descriptors Pool and liodn offset*/ -+ tmpReg64 = (uint64_t)(XX_VirtToPhys( -+ UINT_TO_PTR(p_Manip->reassmParams.reassFrmDescrPoolTblAddr))); -+ tmpReg64 |= ((uint64_t)(p_Manip->reassmParams.dataLiodnOffset -+ & FM_PCD_MANIP_REASM_LIODN_MASK) -+ << (uint64_t)FM_PCD_MANIP_REASM_LIODN_SHIFT); -+ tmpReg64 |= ((uint64_t)(p_Manip->reassmParams.dataLiodnOffset -+ & FM_PCD_MANIP_REASM_ELIODN_MASK) -+ << (uint64_t)FM_PCD_MANIP_REASM_ELIODN_SHIFT); -+ WRITE_UINT32( -+ p_Manip->reassmParams.p_ReassCommonTbl->liodnAndReassFrmDescPoolPtrHi, -+ (uint32_t)(tmpReg64 >> 32)); -+ WRITE_UINT32( -+ p_Manip->reassmParams.p_ReassCommonTbl->reassFrmDescPoolPtrLow, -+ (uint32_t)tmpReg64); -+ -+ /*Allocation of the TimeOut table - This table resides in the MURAM. -+ The number of entries in this table is identical to the number of entries in the Reassembly Frame Descriptors Pool*/ -+ p_Manip->reassmParams.timeOutTblAddr = -+ PTR_TO_UINT(FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, (uint32_t)(size * 8),8)); -+ -+ if (!p_Manip->reassmParams.timeOutTblAddr) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM alloc for Reassembly timeout table")); -+ -+ MemSet8(UINT_TO_PTR(p_Manip->reassmParams.timeOutTblAddr), 0, -+ (uint16_t)(size * 8)); -+ -+ /* Sets the TimeOut table offset from MURAM */ -+ tmpReg32 = (uint32_t)(XX_VirtToPhys( -+ UINT_TO_PTR(p_Manip->reassmParams.timeOutTblAddr)) -+ - p_FmPcd->physicalMuramBase); -+ WRITE_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->timeOutTblPtr, -+ tmpReg32); -+ -+ /* Sets the Expiration Delay */ -+ tmpReg32 = 0; -+ tmpReg32 |= (((uint32_t)(1 << bitFor1Micro)) -+ * p_Manip->reassmParams.timeoutThresholdForReassmProcess); -+ WRITE_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->expirationDelay, -+ tmpReg32); -+ -+ err = FmPcdRegisterReassmPort(p_FmPcd, -+ p_Manip->reassmParams.p_ReassCommonTbl); -+ if (err != E_OK) -+ { -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, -+ p_Manip->reassmParams.p_ReassCommonTbl); -+ RETURN_ERROR(MAJOR, err, ("port registration")); -+ } -+ -+ return err; -+} -+ -+static t_Error CreateReassTable(t_FmPcdManip *p_Manip, e_NetHeaderType hdr) -+{ -+ t_FmPcd *p_FmPcd = p_Manip->h_FmPcd; -+ uint32_t tmpReg32, autoLearnHashTblSize; -+ uint32_t numOfWays, setSize, setSizeCode, keySize; -+ uint32_t waySize, numOfSets, numOfEntries; -+ uint64_t tmpReg64; -+ uint16_t minFragSize; -+ uint16_t maxReassemSize; -+ uintptr_t *p_AutoLearnHashTblAddr, *p_AutoLearnSetLockTblAddr; -+ t_ReassTbl **p_ReassTbl; -+ -+ switch (hdr) -+ { -+ case HEADER_TYPE_IPv4: -+ p_ReassTbl = &p_Manip->reassmParams.ip.p_Ipv4ReassTbl; -+ p_AutoLearnHashTblAddr = -+ &p_Manip->reassmParams.ip.ipv4AutoLearnHashTblAddr; -+ p_AutoLearnSetLockTblAddr = -+ &p_Manip->reassmParams.ip.ipv4AutoLearnSetLockTblAddr; -+ minFragSize = p_Manip->reassmParams.ip.minFragSize[0]; -+ maxReassemSize = 0; -+ numOfWays = p_Manip->reassmParams.ip.numOfFramesPerHashEntry[0]; -+ keySize = 4 + 4 + 1 + 2; /* 3-tuple + IP-Id */ -+ break; -+ case HEADER_TYPE_IPv6: -+ p_ReassTbl = &p_Manip->reassmParams.ip.p_Ipv6ReassTbl; -+ p_AutoLearnHashTblAddr = -+ &p_Manip->reassmParams.ip.ipv6AutoLearnHashTblAddr; -+ p_AutoLearnSetLockTblAddr = -+ &p_Manip->reassmParams.ip.ipv6AutoLearnSetLockTblAddr; -+ minFragSize = p_Manip->reassmParams.ip.minFragSize[1]; -+ maxReassemSize = 0; -+ numOfWays = p_Manip->reassmParams.ip.numOfFramesPerHashEntry[1]; -+ keySize = 16 + 16 + 4; /* 2-tuple + IP-Id */ -+ if (numOfWays > e_FM_PCD_MANIP_SIX_WAYS_HASH) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("num of ways")); -+ break; -+ case HEADER_TYPE_CAPWAP: -+ p_ReassTbl = &p_Manip->reassmParams.capwap.p_ReassTbl; -+ p_AutoLearnHashTblAddr = -+ &p_Manip->reassmParams.capwap.autoLearnHashTblAddr; -+ p_AutoLearnSetLockTblAddr = -+ &p_Manip->reassmParams.capwap.autoLearnSetLockTblAddr; -+ minFragSize = 0; -+ maxReassemSize = p_Manip->reassmParams.capwap.maxRessembledsSize; -+ numOfWays = p_Manip->reassmParams.capwap.numOfFramesPerHashEntry; -+ keySize = 4; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("header type")); -+ } -+ keySize += 2; /* 2 bytes reserved for RFDIndex */ -+#if (DPAA_VERSION >= 11) -+ keySize += 2; /* 2 bytes reserved */ -+#endif /* (DPAA_VERSION >= 11) */ -+ waySize = ROUND_UP(keySize, 8); -+ -+ /* Allocates the Reassembly Parameters Table - This table is located in the MURAM.*/ -+ *p_ReassTbl = (t_ReassTbl *)FM_MURAM_AllocMem( -+ p_FmPcd->h_FmMuram, FM_PCD_MANIP_REASM_TABLE_SIZE, -+ FM_PCD_MANIP_REASM_TABLE_ALIGN); -+ if (!*p_ReassTbl) -+ RETURN_ERROR( MAJOR, E_NO_MEMORY, -+ ("MURAM alloc for Reassembly specific parameters table")); -+ memset(*p_ReassTbl, 0, sizeof(t_ReassTbl)); -+ -+ /* Sets the Reassembly common Parameters table offset from MURAM in the Reassembly Table descriptor*/ -+ tmpReg32 = (uint32_t)(XX_VirtToPhys(p_Manip->reassmParams.p_ReassCommonTbl) -+ - p_FmPcd->physicalMuramBase); -+ WRITE_UINT32((*p_ReassTbl)->reassCommonPrmTblPtr, tmpReg32); -+ -+ /* Calculate set size (set size is rounded-up to next power of 2) */ -+ NEXT_POWER_OF_2(numOfWays * waySize, setSize); -+ -+ /* Get set size code */ -+ LOG2(setSize, setSizeCode); -+ -+ /* Sets ways number and set size code */ -+ WRITE_UINT16((*p_ReassTbl)->waysNumAndSetSize, -+ (uint16_t)((numOfWays << 8) | setSizeCode)); -+ -+ /* It is recommended that the total number of entries in this table -+ (number of sets * number of ways) will be twice the number of frames that -+ are expected to be reassembled simultaneously.*/ -+ numOfEntries = (uint32_t)(p_Manip->reassmParams.maxNumFramesInProcess * 2); -+ -+ /* sets number calculation - number of entries = number of sets * number of ways */ -+ numOfSets = numOfEntries / numOfWays; -+ -+ /* Sets AutoLearnHashKeyMask*/ -+ NEXT_POWER_OF_2(numOfSets, numOfSets); -+ -+ WRITE_UINT16((*p_ReassTbl)->autoLearnHashKeyMask, -+ (uint16_t)(numOfSets - 1)); -+ -+ /* Allocation of Reassembly Automatic Learning Hash Table - This table resides in external memory. -+ The size of this table is determined by the number of sets and the set size. -+ Table size = set size * number of sets -+ This table base address should be aligned to SetSize.*/ -+ autoLearnHashTblSize = numOfSets * setSize; -+ -+ *p_AutoLearnHashTblAddr = -+ PTR_TO_UINT(XX_MallocSmart(autoLearnHashTblSize, p_Manip->reassmParams.dataMemId, setSize)); -+ if (!*p_AutoLearnHashTblAddr) -+ { -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, *p_ReassTbl); -+ *p_ReassTbl = NULL; -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory allocation FAILED")); -+ } -+ MemSet8(UINT_TO_PTR(*p_AutoLearnHashTblAddr), 0, autoLearnHashTblSize); -+ -+ /* Sets the Reassembly Automatic Learning Hash Table and liodn offset */ -+ tmpReg64 = ((uint64_t)(p_Manip->reassmParams.dataLiodnOffset -+ & FM_PCD_MANIP_REASM_LIODN_MASK) -+ << (uint64_t)FM_PCD_MANIP_REASM_LIODN_SHIFT); -+ tmpReg64 |= ((uint64_t)(p_Manip->reassmParams.dataLiodnOffset -+ & FM_PCD_MANIP_REASM_ELIODN_MASK) -+ << (uint64_t)FM_PCD_MANIP_REASM_ELIODN_SHIFT); -+ tmpReg64 |= XX_VirtToPhys(UINT_TO_PTR(*p_AutoLearnHashTblAddr)); -+ WRITE_UINT32( (*p_ReassTbl)->liodnAlAndAutoLearnHashTblPtrHi, -+ (uint32_t)(tmpReg64 >> 32)); -+ WRITE_UINT32((*p_ReassTbl)->autoLearnHashTblPtrLow, (uint32_t)tmpReg64); -+ -+ /* Allocation of the Set Lock table - This table resides in external memory -+ The size of this table is (number of sets in the Reassembly Automatic Learning Hash table)*4 bytes. -+ This table resides in external memory and its base address should be 4-byte aligned */ -+ *p_AutoLearnSetLockTblAddr = -+ PTR_TO_UINT(XX_MallocSmart((uint32_t)(numOfSets * 4), p_Manip->reassmParams.dataMemId, 4)); -+ if (!*p_AutoLearnSetLockTblAddr) -+ { -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, *p_ReassTbl); -+ *p_ReassTbl = NULL; -+ XX_FreeSmart(UINT_TO_PTR(*p_AutoLearnHashTblAddr)); -+ *p_AutoLearnHashTblAddr = 0; -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory allocation FAILED")); -+ } -+ MemSet8(UINT_TO_PTR(*p_AutoLearnSetLockTblAddr), 0, (numOfSets * 4)); -+ -+ /* sets Set Lock table pointer and liodn offset*/ -+ tmpReg64 = ((uint64_t)(p_Manip->reassmParams.dataLiodnOffset -+ & FM_PCD_MANIP_REASM_LIODN_MASK) -+ << (uint64_t)FM_PCD_MANIP_REASM_LIODN_SHIFT); -+ tmpReg64 |= ((uint64_t)(p_Manip->reassmParams.dataLiodnOffset -+ & FM_PCD_MANIP_REASM_ELIODN_MASK) -+ << (uint64_t)FM_PCD_MANIP_REASM_ELIODN_SHIFT); -+ tmpReg64 |= XX_VirtToPhys(UINT_TO_PTR(*p_AutoLearnSetLockTblAddr)); -+ WRITE_UINT32( (*p_ReassTbl)->liodnSlAndAutoLearnSetLockTblPtrHi, -+ (uint32_t)(tmpReg64 >> 32)); -+ WRITE_UINT32((*p_ReassTbl)->autoLearnSetLockTblPtrLow, (uint32_t)tmpReg64); -+ -+ /* Sets user's requested minimum fragment size (in Bytes) for First/Middle fragment */ -+ WRITE_UINT16((*p_ReassTbl)->minFragSize, minFragSize); -+ -+ WRITE_UINT16((*p_ReassTbl)->maxReassemblySize, maxReassemSize); -+ -+ return E_OK; -+} -+ -+static t_Error UpdateInitReasm(t_Handle h_FmPcd, t_Handle h_PcdParams, -+ t_Handle h_FmPort, t_FmPcdManip *p_Manip, -+ t_Handle h_Ad, bool validate) -+{ -+ t_FmPortGetSetCcParams fmPortGetSetCcParams; -+ uint32_t tmpReg32; -+ t_Error err; -+ t_FmPortPcdParams *p_PcdParams = (t_FmPortPcdParams *)h_PcdParams; -+#if (DPAA_VERSION >= 11) -+ t_FmPcdCtrlParamsPage *p_ParamsPage; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Manip->frag, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR( -+ (p_Manip->opcode == HMAN_OC_IP_REASSEMBLY) || (p_Manip->opcode == HMAN_OC_CAPWAP_REASSEMBLY), -+ E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Manip->updateParams || h_PcdParams, -+ E_INVALID_HANDLE); -+ -+ UNUSED(h_Ad); -+ -+ if (!p_Manip->updateParams) -+ return E_OK; -+ -+ if (p_Manip->h_FmPcd != h_FmPcd) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_STATE, -+ ("handler of PCD previously was initiated by different value")); -+ -+ if (p_Manip->updateParams) -+ { -+ if ((!(p_Manip->updateParams -+ & (NUM_OF_TASKS | NUM_OF_EXTRA_TASKS | DISCARD_MASK))) -+ || ((p_Manip->shadowUpdateParams -+ & (NUM_OF_TASKS | NUM_OF_EXTRA_TASKS | DISCARD_MASK)))) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_STATE, -+ ("in this stage parameters from Port has not be updated")); -+ -+ fmPortGetSetCcParams.setCcParams.type = 0; -+ if (p_Manip->opcode == HMAN_OC_CAPWAP_REASSEMBLY) -+ { -+ fmPortGetSetCcParams.setCcParams.type |= UPDATE_OFP_DPTE; -+ fmPortGetSetCcParams.setCcParams.ofpDpde = 0xF; -+ } -+ fmPortGetSetCcParams.getCcParams.type = p_Manip->updateParams | FM_REV; -+ if ((err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams)) -+ != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ if (fmPortGetSetCcParams.getCcParams.type -+ & (NUM_OF_TASKS | NUM_OF_EXTRA_TASKS | DISCARD_MASK | FM_REV)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("offset of the data wasn't configured previously")); -+ if (p_Manip->updateParams -+ & (NUM_OF_TASKS | NUM_OF_EXTRA_TASKS | DISCARD_MASK)) -+ { -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ uint8_t *p_Ptr, i, totalNumOfTnums; -+ -+ totalNumOfTnums = -+ (uint8_t)(fmPortGetSetCcParams.getCcParams.numOfTasks -+ + fmPortGetSetCcParams.getCcParams.numOfExtraTasks); -+ -+ p_Manip->reassmParams.internalBufferPoolAddr = -+ PTR_TO_UINT(FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, -+ (uint32_t)(totalNumOfTnums * BMI_FIFO_UNITS), -+ BMI_FIFO_UNITS)); -+ if (!p_Manip->reassmParams.internalBufferPoolAddr) -+ RETURN_ERROR( -+ MAJOR, E_NO_MEMORY, -+ ("MURAM alloc for Reassembly internal buffers pool")); -+ MemSet8( -+ UINT_TO_PTR(p_Manip->reassmParams.internalBufferPoolAddr), -+ 0, (uint32_t)(totalNumOfTnums * BMI_FIFO_UNITS)); -+ -+ p_Manip->reassmParams.internalBufferPoolManagementIndexAddr = -+ PTR_TO_UINT(FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, -+ (uint32_t)(5 + totalNumOfTnums), -+ 4)); -+ if (!p_Manip->reassmParams.internalBufferPoolManagementIndexAddr) -+ RETURN_ERROR( -+ MAJOR, -+ E_NO_MEMORY, -+ ("MURAM alloc for Reassembly internal buffers management")); -+ -+ p_Ptr = -+ (uint8_t*)UINT_TO_PTR(p_Manip->reassmParams.internalBufferPoolManagementIndexAddr); -+ WRITE_UINT32( -+ *(uint32_t*)p_Ptr, -+ (uint32_t)(XX_VirtToPhys(UINT_TO_PTR(p_Manip->reassmParams.internalBufferPoolAddr)) - p_FmPcd->physicalMuramBase)); -+ for (i = 0, p_Ptr += 4; i < totalNumOfTnums; i++, p_Ptr++) -+ WRITE_UINT8(*p_Ptr, i); -+ WRITE_UINT8(*p_Ptr, 0xFF); -+ -+ tmpReg32 = -+ (4 << FM_PCD_MANIP_REASM_COMMON_INT_BUFFER_IDX_SHIFT) -+ | ((uint32_t)(XX_VirtToPhys( -+ UINT_TO_PTR(p_Manip->reassmParams.internalBufferPoolManagementIndexAddr)) -+ - p_FmPcd->physicalMuramBase)); -+ WRITE_UINT32( -+ p_Manip->reassmParams.p_ReassCommonTbl->internalBufferManagement, -+ tmpReg32); -+ -+ p_Manip->updateParams &= ~(NUM_OF_TASKS | NUM_OF_EXTRA_TASKS -+ | DISCARD_MASK); -+ p_Manip->shadowUpdateParams |= (NUM_OF_TASKS | NUM_OF_EXTRA_TASKS -+ | DISCARD_MASK); -+ } -+ } -+ -+ if (p_Manip->opcode == HMAN_OC_CAPWAP_REASSEMBLY) -+ { -+ if (p_Manip->reassmParams.capwap.h_Scheme) -+ { -+ p_PcdParams->p_KgParams->h_Schemes[p_PcdParams->p_KgParams->numOfSchemes] = -+ p_Manip->reassmParams.capwap.h_Scheme; -+ p_PcdParams->p_KgParams->numOfSchemes++; -+ } -+ -+ } -+ else -+ { -+ if (p_Manip->reassmParams.ip.h_Ipv4Scheme) -+ { -+ p_PcdParams->p_KgParams->h_Schemes[p_PcdParams->p_KgParams->numOfSchemes] = -+ p_Manip->reassmParams.ip.h_Ipv4Scheme; -+ p_PcdParams->p_KgParams->numOfSchemes++; -+ } -+ if (p_Manip->reassmParams.ip.h_Ipv6Scheme) -+ { -+ p_PcdParams->p_KgParams->h_Schemes[p_PcdParams->p_KgParams->numOfSchemes] = -+ p_Manip->reassmParams.ip.h_Ipv6Scheme; -+ p_PcdParams->p_KgParams->numOfSchemes++; -+ } -+#if (DPAA_VERSION >= 11) -+ if (fmPortGetSetCcParams.getCcParams.revInfo.majorRev >= 6) -+ { -+ if ((err = FmPortSetGprFunc(h_FmPort, e_FM_PORT_GPR_MURAM_PAGE, -+ (void**)&p_ParamsPage)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ tmpReg32 = NIA_ENG_KG; -+ if (p_Manip->reassmParams.ip.h_Ipv4Scheme) -+ { -+ tmpReg32 |= NIA_KG_DIRECT; -+ tmpReg32 |= NIA_KG_CC_EN; -+ tmpReg32 |= FmPcdKgGetSchemeId( -+ p_Manip->reassmParams.ip.h_Ipv4Scheme); -+ WRITE_UINT32(p_ParamsPage->iprIpv4Nia, tmpReg32); -+ } -+ if (p_Manip->reassmParams.ip.h_Ipv6Scheme) -+ { -+ tmpReg32 &= ~NIA_AC_MASK; -+ tmpReg32 |= NIA_KG_DIRECT; -+ tmpReg32 |= NIA_KG_CC_EN; -+ tmpReg32 |= FmPcdKgGetSchemeId( -+ p_Manip->reassmParams.ip.h_Ipv6Scheme); -+ WRITE_UINT32(p_ParamsPage->iprIpv6Nia, tmpReg32); -+ } -+ } -+#else -+ if (fmPortGetSetCcParams.getCcParams.revInfo.majorRev < 6) -+ { -+ WRITE_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->discardMask, -+ fmPortGetSetCcParams.getCcParams.discardMask); -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ return E_OK; -+} -+ -+#if (DPAA_VERSION == 10) -+static t_Error FmPcdFragHcScratchPoolFill(t_Handle h_FmPcd, uint8_t scratchBpid) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_FmPcdCcFragScratchPoolCmdParams fmPcdCcFragScratchPoolCmdParams; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ -+ memset(&fmPcdCcFragScratchPoolCmdParams, 0, sizeof(t_FmPcdCcFragScratchPoolCmdParams)); -+ -+ fmPcdCcFragScratchPoolCmdParams.numOfBuffers = NUM_OF_SCRATCH_POOL_BUFFERS; -+ fmPcdCcFragScratchPoolCmdParams.bufferPoolId = scratchBpid; -+ if ((err = FmHcPcdCcIpFragScratchPollCmd(p_FmPcd->h_Hc, TRUE, &fmPcdCcFragScratchPoolCmdParams)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (fmPcdCcFragScratchPoolCmdParams.numOfBuffers != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Fill scratch pool failed," -+ "Failed to release %d buffers to the BM (missing FBPRs)", -+ fmPcdCcFragScratchPoolCmdParams.numOfBuffers)); -+ -+ return E_OK; -+} -+ -+static t_Error FmPcdFragHcScratchPoolEmpty(t_Handle h_FmPcd, uint8_t scratchBpid) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_FmPcdCcFragScratchPoolCmdParams fmPcdCcFragScratchPoolCmdParams; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ -+ memset(&fmPcdCcFragScratchPoolCmdParams, 0, sizeof(t_FmPcdCcFragScratchPoolCmdParams)); -+ -+ fmPcdCcFragScratchPoolCmdParams.bufferPoolId = scratchBpid; -+ if ((err = FmHcPcdCcIpFragScratchPollCmd(p_FmPcd->h_Hc, FALSE, &fmPcdCcFragScratchPoolCmdParams)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ return E_OK; -+} -+#endif /* (DPAA_VERSION == 10) */ -+ -+static void ReleaseManipHandler(t_FmPcdManip *p_Manip, t_FmPcd *p_FmPcd) -+{ -+ if (p_Manip->h_Ad) -+ { -+ if (p_Manip->muramAllocate) -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, p_Manip->h_Ad); -+ else -+ XX_Free(p_Manip->h_Ad); -+ p_Manip->h_Ad = NULL; -+ } -+ if (p_Manip->p_Template) -+ { -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, p_Manip->p_Template); -+ p_Manip->p_Template = NULL; -+ } -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ if (p_Manip->h_Frag) -+ { -+ if (p_Manip->capwapFragParams.p_AutoLearnHashTbl) -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, -+ p_Manip->capwapFragParams.p_AutoLearnHashTbl); -+ if (p_Manip->capwapFragParams.p_ReassmFrmDescrPoolTbl) -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, -+ p_Manip->capwapFragParams.p_ReassmFrmDescrPoolTbl); -+ if (p_Manip->capwapFragParams.p_ReassmFrmDescrIndxPoolTbl) -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, -+ p_Manip->capwapFragParams.p_ReassmFrmDescrIndxPoolTbl); -+ if (p_Manip->capwapFragParams.p_TimeOutTbl) -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, -+ p_Manip->capwapFragParams.p_TimeOutTbl); -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, p_Manip->h_Frag); -+ -+ } -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ if (p_Manip->frag) -+ { -+ if (p_Manip->fragParams.p_Frag) -+ { -+#if (DPAA_VERSION == 10) -+ FmPcdFragHcScratchPoolEmpty((t_Handle)p_FmPcd, p_Manip->fragParams.scratchBpid); -+#endif /* (DPAA_VERSION == 10) */ -+ -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, p_Manip->fragParams.p_Frag); -+ } -+ } -+ else -+ if (p_Manip->reassm) -+ { -+ FmPcdUnregisterReassmPort(p_FmPcd, -+ p_Manip->reassmParams.p_ReassCommonTbl); -+ -+ if (p_Manip->reassmParams.timeOutTblAddr) -+ FM_MURAM_FreeMem( -+ p_FmPcd->h_FmMuram, -+ UINT_TO_PTR(p_Manip->reassmParams.timeOutTblAddr)); -+ if (p_Manip->reassmParams.reassFrmDescrPoolTblAddr) -+ XX_FreeSmart( -+ UINT_TO_PTR(p_Manip->reassmParams.reassFrmDescrPoolTblAddr)); -+ if (p_Manip->reassmParams.p_ReassCommonTbl) -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, -+ p_Manip->reassmParams.p_ReassCommonTbl); -+ if (p_Manip->reassmParams.reassFrmDescrIndxPoolTblAddr) -+ FM_MURAM_FreeMem( -+ p_FmPcd->h_FmMuram, -+ UINT_TO_PTR(p_Manip->reassmParams.reassFrmDescrIndxPoolTblAddr)); -+ if (p_Manip->reassmParams.internalBufferPoolManagementIndexAddr) -+ FM_MURAM_FreeMem( -+ p_FmPcd->h_FmMuram, -+ UINT_TO_PTR(p_Manip->reassmParams.internalBufferPoolManagementIndexAddr)); -+ if (p_Manip->reassmParams.internalBufferPoolAddr) -+ FM_MURAM_FreeMem( -+ p_FmPcd->h_FmMuram, -+ UINT_TO_PTR(p_Manip->reassmParams.internalBufferPoolAddr)); -+ if (p_Manip->reassmParams.hdr == HEADER_TYPE_CAPWAP) -+ { -+ -+ } -+ else -+ { -+ if (p_Manip->reassmParams.ip.ipv4AutoLearnHashTblAddr) -+ XX_FreeSmart( -+ UINT_TO_PTR(p_Manip->reassmParams.ip.ipv4AutoLearnHashTblAddr)); -+ if (p_Manip->reassmParams.ip.ipv6AutoLearnHashTblAddr) -+ XX_FreeSmart( -+ UINT_TO_PTR(p_Manip->reassmParams.ip.ipv6AutoLearnHashTblAddr)); -+ if (p_Manip->reassmParams.ip.ipv4AutoLearnSetLockTblAddr) -+ XX_FreeSmart( -+ UINT_TO_PTR(p_Manip->reassmParams.ip.ipv4AutoLearnSetLockTblAddr)); -+ if (p_Manip->reassmParams.ip.ipv6AutoLearnSetLockTblAddr) -+ XX_FreeSmart( -+ UINT_TO_PTR(p_Manip->reassmParams.ip.ipv6AutoLearnSetLockTblAddr)); -+ if (p_Manip->reassmParams.ip.p_Ipv4ReassTbl) -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, -+ p_Manip->reassmParams.ip.p_Ipv4ReassTbl); -+ if (p_Manip->reassmParams.ip.p_Ipv6ReassTbl) -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, -+ p_Manip->reassmParams.ip.p_Ipv6ReassTbl); -+ if (p_Manip->reassmParams.ip.h_Ipv6Ad) -+ XX_FreeSmart(p_Manip->reassmParams.ip.h_Ipv6Ad); -+ if (p_Manip->reassmParams.ip.h_Ipv4Ad) -+ XX_FreeSmart(p_Manip->reassmParams.ip.h_Ipv4Ad); -+ } -+ } -+ -+ if (p_Manip->p_StatsTbl) -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, p_Manip->p_StatsTbl); -+} -+ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+static t_Error CheckManipParamsAndSetType(t_FmPcdManip *p_Manip, t_FmPcdManipParams *p_ManipParams) -+{ -+ if (p_ManipParams->u.hdr.rmv) -+ { -+ switch (p_ManipParams->u.hdr.rmvParams.type) -+ { -+ case (e_FM_PCD_MANIP_RMV_BY_HDR): -+ switch (p_ManipParams->u.hdr.rmvParams.u.byHdr.type) -+ { -+ case (e_FM_PCD_MANIP_RMV_BY_HDR_FROM_START) : -+ if (p_ManipParams->u.hdr.rmvParams.u.byHdr.u.fromStartByHdr.include) -+ { -+ switch (p_ManipParams->u.hdr.rmvParams.u.byHdr.u.fromStartByHdr.hdrInfo.hdr) -+ { -+ case (HEADER_TYPE_CAPWAP_DTLS) : -+ p_Manip->opcode = HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST; -+ p_Manip->muramAllocate = TRUE; -+ if (p_ManipParams->u.hdr.insrt) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("for CAPWAP_DTLS_HDR remove can not be insrt manipualtion after")); -+ if (p_ManipParams->fragOrReasm) -+ { -+ if (!p_ManipParams->fragOrReasmParams.frag) -+ { -+ switch (p_ManipParams->fragOrReasmParams.hdr) -+ { -+ case (HEADER_TYPE_CAPWAP): -+ p_Manip->opcode = HMAN_OC_CAPWAP_REASSEMBLY; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("unsupported header for Reassembly")); -+ } -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("for this type of manipulation frag can not be TRUE")); -+ } -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("non valid net header of remove location")); -+ } -+ } -+ else -+ { -+ switch (p_ManipParams->u.hdr.rmvParams.u.byHdr.u.fromStartByHdr.hdrInfo.hdr) -+ { -+ case (HEADER_TYPE_CAPWAP_DTLS) : -+ case (HEADER_TYPE_CAPWAP) : -+ if (p_ManipParams->fragOrReasm || p_ManipParams->u.hdr.insrt) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("for the type of remove e_FM_PCD_MANIP_RMV_FROM_START_OF_FRAME_TILL_CAPWAP can not be insert or fragOrReasm TRUE")); -+ p_Manip->opcode = HMAN_OC_RMV_N_OR_INSRT_INT_FRM_HDR; -+ p_Manip->muramAllocate = TRUE; -+ p_ManipParams->u.hdr.insrt = TRUE; //internal frame header -+ break; -+ default : -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("invalid type of remove manipulation")); -+ } -+ } -+ break; -+ default : -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("invalid type of remove manipulation")); -+ } -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("invalid type of remove manipulation")); -+ } -+ } -+ else if (p_ManipParams->u.hdr.insrt) -+ { -+ switch (p_ManipParams->u.hdr.insrtParams.type) -+ { -+ case (e_FM_PCD_MANIP_INSRT_BY_TEMPLATE) : -+ -+ p_Manip->opcode = HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER; -+ p_Manip->muramAllocate = FALSE; -+ if (p_ManipParams->fragOrReasm) -+ { -+ if (p_ManipParams->fragOrReasmParams.frag) -+ { -+ switch (p_ManipParams->fragOrReasmParams.hdr) -+ { -+ case (HEADER_TYPE_CAPWAP): -+ p_Manip->opcode = HMAN_OC_CAPWAP_FRAGMENTATION; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Invalid header for fragmentation")); -+ } -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_STATE,("can not reach this point")); -+ } -+ break; -+ -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("for only isert manipulation unsupported type")); -+ } -+ } -+ else if (p_ManipParams->fragOrReasm) -+ { -+ if (p_ManipParams->fragOrReasmParams.frag) -+ { -+ switch (p_ManipParams->fragOrReasmParams.hdr) -+ { -+ case (HEADER_TYPE_CAPWAP): -+ p_Manip->opcode = HMAN_OC_CAPWAP_FRAGMENTATION; -+ p_Manip->muramAllocate = FALSE; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Unsupported header for fragmentation")); -+ } -+ } -+ else -+ { -+ switch (p_ManipParams->fragOrReasmParams.hdr) -+ { -+ case (HEADER_TYPE_CAPWAP): -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Reassembly has to be with additional operation - rmv = TRUE, type of remove - e_FM_PCD_MANIP_RMV_FROM_START_OF_FRAME_INCLUDE_SPECIFIC_LOCATION,type = e_FM_PCD_MANIP_LOC_BY_HDR, hdr = HEADER_TYPE_CAPWAP_DTLS")); -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Unsupported header for reassembly")); -+ } -+ } -+ -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("User didn't ask for any manipulation")); -+ -+ p_Manip->insrt = p_ManipParams->u.hdr.insrt; -+ p_Manip->rmv = p_ManipParams->u.hdr.rmv; -+ -+ return E_OK; -+} -+ -+#else /* not (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+static t_Error CheckManipParamsAndSetType(t_FmPcdManip *p_Manip, -+ t_FmPcdManipParams *p_ManipParams) -+{ -+ switch (p_ManipParams->type) -+ { -+ case e_FM_PCD_MANIP_HDR: -+ /* Check that next-manip is not already used */ -+ if (p_ManipParams->h_NextManip) -+ { -+ if (!MANIP_IS_FIRST(p_ManipParams->h_NextManip)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_STATE, -+ ("h_NextManip is already a part of another chain")); -+ if ((MANIP_GET_TYPE(p_ManipParams->h_NextManip) -+ != e_FM_PCD_MANIP_HDR) && -+ (MANIP_GET_TYPE(p_ManipParams->h_NextManip) -+ != e_FM_PCD_MANIP_FRAG)) -+ RETURN_ERROR( -+ MAJOR, -+ E_NOT_SUPPORTED, -+ ("For a Header Manipulation node - no support of h_NextManip of type other than Header Manipulation or Fragmentation.")); -+ } -+ -+ if (p_ManipParams->u.hdr.rmv) -+ { -+ switch (p_ManipParams->u.hdr.rmvParams.type) -+ { -+ case (e_FM_PCD_MANIP_RMV_BY_HDR): -+ switch (p_ManipParams->u.hdr.rmvParams.u.byHdr.type) -+ { -+ case (e_FM_PCD_MANIP_RMV_BY_HDR_SPECIFIC_L2): -+ break; -+#if (DPAA_VERSION >= 11) -+ case (e_FM_PCD_MANIP_RMV_BY_HDR_CAPWAP): -+ break; -+ case (e_FM_PCD_MANIP_RMV_BY_HDR_FROM_START): -+ { -+ t_Error err; -+ uint8_t prsArrayOffset; -+ -+ err = -+ GetPrOffsetByHeaderOrField( -+ &p_ManipParams->u.hdr.rmvParams.u.byHdr.u.hdrInfo, -+ &prsArrayOffset); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ break; -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ default: -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("invalid type of remove manipulation")); -+ } -+ break; -+ case (e_FM_PCD_MANIP_RMV_GENERIC): -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("invalid type of remove manipulation")); -+ } -+ p_Manip->opcode = HMAN_OC; -+ p_Manip->muramAllocate = TRUE; -+ p_Manip->rmv = TRUE; -+ } -+ else -+ if (p_ManipParams->u.hdr.insrt) -+ { -+ switch (p_ManipParams->u.hdr.insrtParams.type) -+ { -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR): -+ { -+ switch (p_ManipParams->u.hdr.insrtParams.u.byHdr.type) -+ { -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_SPECIFIC_L2): -+ /* nothing to check */ -+ break; -+#if (DPAA_VERSION >= 11) -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_IP): -+ if (p_ManipParams->u.hdr.insrtParams.u.byHdr.u.ipParams.insrt.size -+ % 4) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("IP inserted header must be of size which is a multiple of four bytes")); -+ break; -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_CAPWAP): -+ if (p_ManipParams->u.hdr.insrtParams.u.byHdr.u.insrt.size -+ % 4) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("CAPWAP inserted header must be of size which is a multiple of four bytes")); -+ break; -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_UDP): -+ case (e_FM_PCD_MANIP_INSRT_BY_HDR_UDP_LITE): -+ if (p_ManipParams->u.hdr.insrtParams.u.byHdr.u.insrt.size -+ != 8) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("Inserted header must be of size 8")); -+ break; -+#endif /* (DPAA_VERSION >= 11) */ -+ default: -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("unsupported insert by header type")); -+ } -+ } -+ case (e_FM_PCD_MANIP_INSRT_GENERIC): -+ break; -+ default: -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("for only insert manipulation unsupported type")); -+ } -+ p_Manip->opcode = HMAN_OC; -+ p_Manip->muramAllocate = TRUE; -+ p_Manip->insrt = TRUE; -+ } -+ else -+ if (p_ManipParams->u.hdr.fieldUpdate) -+ { -+ /* Check parameters */ -+ if (p_ManipParams->u.hdr.fieldUpdateParams.type -+ == e_FM_PCD_MANIP_HDR_FIELD_UPDATE_VLAN) -+ { -+ if ((p_ManipParams->u.hdr.fieldUpdateParams.u.vlan.updateType -+ == e_FM_PCD_MANIP_HDR_FIELD_UPDATE_VLAN_VPRI) -+ && (p_ManipParams->u.hdr.fieldUpdateParams.u.vlan.u.vpri -+ > 7)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("vpri should get values of 0-7 ")); -+ if (p_ManipParams->u.hdr.fieldUpdateParams.u.vlan.updateType -+ == e_FM_PCD_MANIP_HDR_FIELD_UPDATE_DSCP_TO_VLAN) -+ { -+ int i; -+ -+ if (p_ManipParams->u.hdr.fieldUpdateParams.u.vlan.u.dscpToVpri.vpriDefVal -+ > 7) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("vpriDefVal should get values of 0-7 ")); -+ for (i = 0; i < FM_PCD_MANIP_DSCP_TO_VLAN_TRANS; -+ i++) -+ if (p_ManipParams->u.hdr.fieldUpdateParams.u.vlan.u.dscpToVpri.dscpToVpriTable[i] -+ & 0xf0) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("dscpToVpriTabl value out of range (0-15)")); -+ } -+ -+ } -+ -+ p_Manip->opcode = HMAN_OC; -+ p_Manip->muramAllocate = TRUE; -+ p_Manip->fieldUpdate = TRUE; -+ } -+ else -+ if (p_ManipParams->u.hdr.custom) -+ { -+ if (p_ManipParams->u.hdr.customParams.type == e_FM_PCD_MANIP_HDR_CUSTOM_GEN_FIELD_REPLACE) -+ { -+ -+ if ((p_ManipParams->u.hdr.customParams.u.genFieldReplace.size == 0) || -+ (p_ManipParams->u.hdr.customParams.u.genFieldReplace.size > 8)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("size should get values of 1-8 ")); -+ -+ if (p_ManipParams->u.hdr.customParams.u.genFieldReplace.srcOffset > 7) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("srcOffset should be <= 7")); -+ -+ if ((p_ManipParams->u.hdr.customParams.u.genFieldReplace.srcOffset + -+ p_ManipParams->u.hdr.customParams.u.genFieldReplace.size) > 8) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("(srcOffset + size) should be <= 8")); -+ -+ if ((p_ManipParams->u.hdr.customParams.u.genFieldReplace.dstOffset + -+ p_ManipParams->u.hdr.customParams.u.genFieldReplace.size) > 256) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("(dstOffset + size) should be <= 256")); -+ -+ } -+ -+ p_Manip->opcode = HMAN_OC; -+ p_Manip->muramAllocate = TRUE; -+ p_Manip->custom = TRUE; -+ } -+ break; -+ case e_FM_PCD_MANIP_REASSEM: -+ if (p_ManipParams->h_NextManip) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, -+ ("next manip with reassembly")); -+ switch (p_ManipParams->u.reassem.hdr) -+ { -+ case (HEADER_TYPE_IPv4): -+ p_Manip->reassmParams.hdr = HEADER_TYPE_IPv4; -+ p_Manip->opcode = HMAN_OC_IP_REASSEMBLY; -+ break; -+ case (HEADER_TYPE_IPv6): -+ p_Manip->reassmParams.hdr = HEADER_TYPE_IPv6; -+ p_Manip->opcode = HMAN_OC_IP_REASSEMBLY; -+ break; -+#if (DPAA_VERSION >= 11) -+ case (HEADER_TYPE_CAPWAP): -+ p_Manip->reassmParams.hdr = HEADER_TYPE_CAPWAP; -+ p_Manip->opcode = HMAN_OC_CAPWAP_REASSEMBLY; -+ break; -+#endif /* (DPAA_VERSION >= 11) */ -+ default: -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, -+ ("header for reassembly")); -+ } -+ break; -+ case e_FM_PCD_MANIP_FRAG: -+ if (p_ManipParams->h_NextManip) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, -+ ("next manip with fragmentation")); -+ switch (p_ManipParams->u.frag.hdr) -+ { -+ case (HEADER_TYPE_IPv4): -+ case (HEADER_TYPE_IPv6): -+ p_Manip->opcode = HMAN_OC_IP_FRAGMENTATION; -+ break; -+#if (DPAA_VERSION >= 11) -+ case (HEADER_TYPE_CAPWAP): -+ p_Manip->opcode = HMAN_OC_CAPWAP_FRAGMENTATION; -+ break; -+#endif /* (DPAA_VERSION >= 11) */ -+ default: -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, -+ ("header for fragmentation")); -+ } -+ p_Manip->muramAllocate = TRUE; -+ break; -+ case e_FM_PCD_MANIP_SPECIAL_OFFLOAD: -+ switch (p_ManipParams->u.specialOffload.type) -+ { -+ case (e_FM_PCD_MANIP_SPECIAL_OFFLOAD_IPSEC): -+ p_Manip->opcode = HMAN_OC_IPSEC_MANIP; -+ p_Manip->muramAllocate = TRUE; -+ break; -+#if (DPAA_VERSION >= 11) -+ case (e_FM_PCD_MANIP_SPECIAL_OFFLOAD_CAPWAP): -+ p_Manip->opcode = HMAN_OC_CAPWAP_MANIP; -+ p_Manip->muramAllocate = TRUE; -+ break; -+#endif /* (DPAA_VERSION >= 11) */ -+ default: -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, -+ ("special offload type")); -+ } -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("manip type")); -+ } -+ -+ return E_OK; -+} -+#endif /* not (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ -+static t_Error UpdateIndxStats(t_Handle h_FmPcd, -+ t_Handle h_FmPort, -+ t_FmPcdManip *p_Manip) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ uint32_t tmpReg32 = 0; -+ t_AdOfTypeContLookup *p_Ad; -+ t_FmPortGetSetCcParams fmPortGetSetCcParams; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip,E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_Ad,E_INVALID_HANDLE); -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ if (p_Manip->h_FmPcd != h_FmPcd) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("handler of PCD previously was initiated by different value")); -+ -+ memset(&fmPortGetSetCcParams, 0, sizeof(t_FmPortGetSetCcParams)); -+ -+ if (!p_Manip->p_StatsTbl) -+ { -+ -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_NIA_PNDN; -+ fmPortGetSetCcParams.setCcParams.nia = NIA_FM_CTL_AC_CC; -+ err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ tmpReg32 = GET_UINT32(p_Ad->ccAdBase); -+ -+ p_Manip->p_StatsTbl = -+ (t_Handle)FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, -+ (uint32_t)p_Manip->owner * FM_PCD_MANIP_INDEXED_STATS_ENTRY_SIZE, -+ 4); -+ if (!p_Manip->p_StatsTbl) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM alloc for Manipulation indexed statistics table")); -+ -+ MemSet8(p_Manip->p_StatsTbl, 0, (uint32_t)(p_Manip->owner * 4)); -+ -+ tmpReg32 |= (uint32_t)(XX_VirtToPhys(p_Manip->p_StatsTbl) - p_FmPcd->physicalMuramBase); -+ -+ if (p_Manip->cnia) -+ tmpReg32 |= FM_PCD_MANIP_INDEXED_STATS_CNIA; -+ -+ tmpReg32 |= FM_PCD_MANIP_INDEXED_STATS_DPD; -+ WRITE_UINT32(p_Ad->ccAdBase, tmpReg32); -+ } -+ else -+ { -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_NIA_PNDN; -+ fmPortGetSetCcParams.setCcParams.nia = NIA_FM_CTL_AC_CC; -+ err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ return E_OK; -+} -+ -+static t_Error RmvHdrTillSpecLocNOrInsrtIntFrmHdr(t_FmPcdManipHdrRmvParams *p_ManipParams, t_FmPcdManip *p_Manip) -+{ -+ t_AdOfTypeContLookup *p_Ad; -+ uint32_t tmpReg32 = 0; -+ uint8_t prsArrayOffset = 0; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip,E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_ManipParams,E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_Ad,E_INVALID_HANDLE); -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ if (p_Manip->rmv) -+ { -+ err = GetPrOffsetByHeaderOrField(&p_ManipParams->u.byHdr.u.fromStartByHdr.hdrInfo, &prsArrayOffset); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ tmpReg32 |= (uint32_t)prsArrayOffset << 24; -+ tmpReg32 |= HMAN_RMV_HDR; -+ } -+ -+ if (p_Manip->insrt) -+ tmpReg32 |= HMAN_INSRT_INT_FRM_HDR; -+ -+ tmpReg32 |= (uint32_t)HMAN_OC_RMV_N_OR_INSRT_INT_FRM_HDR; -+ -+ WRITE_UINT32(p_Ad->pcAndOffsets, tmpReg32); -+ -+ tmpReg32 = 0; -+ tmpReg32 |= FM_PCD_AD_CONT_LOOKUP_TYPE; -+ WRITE_UINT32(p_Ad->ccAdBase, tmpReg32); -+ -+ return E_OK; -+} -+ -+static t_Error MvIntFrameHeaderFromFrameToBufferPrefix(t_FmPcdManip *p_Manip, -+ bool caamUsed) -+{ -+ t_AdOfTypeContLookup *p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ uint32_t tmpReg32 = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Ad, E_INVALID_HANDLE); -+ -+ p_Manip->updateParams |= OFFSET_OF_PR | INTERNAL_CONTEXT_OFFSET; -+ -+ tmpReg32 = 0; -+ tmpReg32 |= FM_PCD_AD_CONT_LOOKUP_TYPE; -+ *(uint32_t *)&p_Ad->ccAdBase = tmpReg32; -+ -+ tmpReg32 = 0; -+ tmpReg32 |= HMAN_OC_MV_INT_FRAME_HDR_FROM_FRM_TO_BUFFER_PREFFIX; -+ tmpReg32 |= (uint32_t)0x16 << 16; -+ *(uint32_t *)&p_Ad->pcAndOffsets = tmpReg32; -+ -+ if (caamUsed) -+ *(uint32_t *)&p_Ad->gmask = 0xf0000000; -+ -+ return E_OK; -+} -+ -+static t_Error CapwapRmvDtlsHdr(t_FmPcd *p_FmPcd, t_FmPcdManip *p_Manip) -+{ -+ t_AdOfTypeContLookup *p_Ad; -+ uint32_t tmpReg32 = 0; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_Ad,E_INVALID_HANDLE); -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ -+ tmpReg32 = 0; -+ tmpReg32 |= (uint32_t)HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST; -+ WRITE_UINT32(p_Ad->pcAndOffsets, tmpReg32); -+ -+ tmpReg32 = 0; -+ tmpReg32 |= FM_PCD_AD_CONT_LOOKUP_TYPE; -+ -+ -+ if (p_Manip->h_Frag) -+ { -+ p_Manip->updateParams |= INTERNAL_CONTEXT_OFFSET; -+ tmpReg32 |= (uint32_t)(XX_VirtToPhys(p_Manip->h_Frag) - (p_FmPcd->physicalMuramBase)); -+ } -+ -+ WRITE_UINT32(p_Ad->ccAdBase, tmpReg32); -+ -+ return err; -+} -+ -+static t_Error CapwapReassembly(t_CapwapReassemblyParams *p_ManipParams, -+ t_FmPcdManip *p_Manip, -+ t_FmPcd *p_FmPcd, -+ uint8_t poolId) -+{ -+ t_Handle p_Table; -+ uint32_t tmpReg32 = 0; -+ int i = 0; -+ uint8_t log2Num; -+ uint8_t numOfSets; -+ uint32_t j = 0; -+ uint32_t bitFor1Micro; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_Ad, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->h_Hc, E_INVALID_HANDLE); -+ -+ if (!p_FmPcd->h_Hc) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE,("hc port has to be initialized in this mode")); -+ if (!POWER_OF_2(p_ManipParams->timeoutRoutineRequestTime)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("timeoutRoutineRequestTime has to be power of 2")); -+ if (!POWER_OF_2(p_ManipParams->maxNumFramesInProcess)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE,("maxNumFramesInProcess has to be power of 2")); -+ if (!p_ManipParams->timeoutRoutineRequestTime && p_ManipParams->timeoutThresholdForReassmProcess) -+ DBG(WARNING, ("if timeoutRoutineRequestTime 0, timeoutThresholdForReassmProcess is uselessly")); -+ if (p_ManipParams->numOfFramesPerHashEntry == e_FM_PCD_MANIP_FOUR_WAYS_HASH) -+ { -+ if ((p_ManipParams->maxNumFramesInProcess < 4) || -+ (p_ManipParams->maxNumFramesInProcess > 512)) -+ RETURN_ERROR(MAJOR,E_INVALID_VALUE, ("In the case of numOfFramesPerHashEntry = e_FM_PCD_MANIP_EIGHT_WAYS_HASH maxNumFramesInProcess has to be in the range 4-512")); -+ } -+ else -+ { -+ if ((p_ManipParams->maxNumFramesInProcess < 8) || -+ (p_ManipParams->maxNumFramesInProcess > 2048)) -+ RETURN_ERROR(MAJOR,E_INVALID_VALUE, ("In the case of numOfFramesPerHashEntry = e_FM_PCD_MANIP_FOUR_WAYS_HASH maxNumFramesInProcess has to be in the range 8-2048")); -+ } -+ -+ bitFor1Micro = FmGetTimeStampScale(p_FmPcd->h_Fm); -+ if (bitFor1Micro == 0) -+ RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, ("Timestamp scale")); -+ -+ p_Manip->updateParams |= (NUM_OF_TASKS | OFFSET_OF_PR | OFFSET_OF_DATA | HW_PORT_ID); -+ -+ p_Manip->h_Frag = (t_Handle)FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, -+ FM_PCD_MANIP_CAPWAP_REASM_TABLE_SIZE, -+ FM_PCD_MANIP_CAPWAP_REASM_TABLE_ALIGN); -+ if (!p_Manip->h_Frag) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM alloc CAPWAP reassembly parameters table")); -+ -+ MemSet8(p_Manip->h_Frag, 0, FM_PCD_MANIP_CAPWAP_REASM_TABLE_SIZE); -+ -+ p_Table = (t_CapwapReasmPram *)p_Manip->h_Frag; -+ -+ p_Manip->capwapFragParams.p_AutoLearnHashTbl = -+ (t_Handle)FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, -+ (uint32_t)(p_ManipParams->maxNumFramesInProcess * 2 * FM_PCD_MANIP_CAPWAP_REASM_AUTO_LEARNING_HASH_ENTRY_SIZE), -+ FM_PCD_MANIP_CAPWAP_REASM_TABLE_ALIGN); -+ -+ if (!p_Manip->capwapFragParams.p_AutoLearnHashTbl) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY,("MURAM alloc for CAPWAP automatic learning hash table")); -+ -+ MemSet8(p_Manip->capwapFragParams.p_AutoLearnHashTbl, 0, (uint32_t)(p_ManipParams->maxNumFramesInProcess * 2 * FM_PCD_MANIP_CAPWAP_REASM_AUTO_LEARNING_HASH_ENTRY_SIZE)); -+ -+ tmpReg32 = (uint32_t)(XX_VirtToPhys(p_Manip->capwapFragParams.p_AutoLearnHashTbl) - p_FmPcd->physicalMuramBase); -+ -+ WRITE_UINT32(((t_CapwapReasmPram *)p_Table)->autoLearnHashTblPtr, tmpReg32); -+ -+ tmpReg32 = 0; -+ if (p_ManipParams->timeOutMode == e_FM_PCD_MANIP_TIME_OUT_BETWEEN_FRAMES) -+ tmpReg32 |= FM_PCD_MANIP_CAPWAP_REASM_TIME_OUT_BETWEEN_FRAMES; -+ if (p_ManipParams->haltOnDuplicationFrag) -+ tmpReg32 |= FM_PCD_MANIP_CAPWAP_REASM_HALT_ON_DUPLICATE_FRAG; -+ if (p_ManipParams->numOfFramesPerHashEntry == e_FM_PCD_MANIP_EIGHT_WAYS_HASH) -+ { -+ i = 8; -+ tmpReg32 |= FM_PCD_MANIP_CAPWAP_REASM_AUTOMATIC_LEARNIN_HASH_8_WAYS; -+ } -+ else -+ i = 4; -+ -+ numOfSets = (uint8_t)((p_ManipParams->maxNumFramesInProcess * 2) / i); -+ LOG2(numOfSets, log2Num); -+ tmpReg32 |= (uint32_t)(log2Num - 1) << 24; -+ -+ WRITE_UINT32(((t_CapwapReasmPram *)p_Table)->mode, tmpReg32); -+ -+ for (j=0; jmaxNumFramesInProcess*2; j++) -+ if (((j / i) % 2)== 0) -+ WRITE_UINT32(*(uint32_t *)PTR_MOVE(p_Manip->capwapFragParams.p_AutoLearnHashTbl, j * FM_PCD_MANIP_CAPWAP_REASM_AUTO_LEARNING_HASH_ENTRY_SIZE), 0x80000000); -+ -+ tmpReg32 = 0x00008000; -+ tmpReg32 |= (uint32_t)poolId << 16; -+ WRITE_UINT32(((t_CapwapReasmPram *)p_Table)->bufferPoolIdAndRisc1SetIndexes, tmpReg32); -+ WRITE_UINT32(((t_CapwapReasmPram *)p_Table)->risc23SetIndexes, 0x80008000); -+ WRITE_UINT32(((t_CapwapReasmPram *)p_Table)->risc4SetIndexesAndExtendedStatsTblPtr, 0x80000000); -+ -+ p_Manip->capwapFragParams.maxNumFramesInProcess = p_ManipParams->maxNumFramesInProcess; -+ -+ p_Manip->capwapFragParams.sgBpid = poolId; -+ -+ p_Manip->capwapFragParams.fqidForTimeOutFrames = p_ManipParams->fqidForTimeOutFrames; -+ p_Manip->capwapFragParams.timeoutRoutineRequestTime = p_ManipParams->timeoutRoutineRequestTime; -+ p_Manip->capwapFragParams.bitFor1Micro = bitFor1Micro; -+ -+ tmpReg32 = 0; -+ tmpReg32 |= (((uint32_t)1<capwapFragParams.bitFor1Micro) * p_ManipParams->timeoutThresholdForReassmProcess); -+ WRITE_UINT32(((t_CapwapReasmPram *)p_Table)->expirationDelay, tmpReg32); -+ -+ return E_OK; -+} -+ -+static t_Error CapwapFragmentation(t_CapwapFragmentationParams *p_ManipParams, -+ t_FmPcdManip *p_Manip, -+ t_FmPcd *p_FmPcd, -+ uint8_t poolId) -+{ -+ t_AdOfTypeContLookup *p_Ad; -+ uint32_t tmpReg32 = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_Ad,E_INVALID_HANDLE); -+ -+ p_Manip->updateParams |= OFFSET_OF_DATA; -+ -+ p_Manip->frag = TRUE; -+ -+ p_Manip->h_Frag = (t_Handle)FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, -+ FM_PCD_CC_AD_ENTRY_SIZE, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_Manip->h_Frag) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM alloc for CAPWAP fragmentation table descriptor")); -+ -+ MemSet8(p_Manip->h_Frag, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Frag; -+ -+ tmpReg32 = 0; -+ tmpReg32 |= (uint32_t)HMAN_OC_CAPWAP_FRAGMENTATION; -+ -+ if (p_ManipParams->headerOptionsCompr) -+ tmpReg32 |= FM_PCD_MANIP_CAPWAP_FRAG_COMPR_OPTION_FIELD_EN; -+ tmpReg32 |= ((uint32_t)poolId << 8); -+ WRITE_UINT32(p_Ad->pcAndOffsets, tmpReg32); -+ -+ tmpReg32 = 0; -+ tmpReg32 |= FM_PCD_AD_CONT_LOOKUP_TYPE; -+ WRITE_UINT32(p_Ad->ccAdBase, tmpReg32); -+ -+ p_Manip->sizeForFragmentation = p_ManipParams->sizeForFragmentation; -+ p_Manip->capwapFragParams.sgBpid = poolId; -+ -+ return E_OK; -+} -+ -+static t_Error IndxStats(t_FmPcdStatsParams *p_StatsParams,t_FmPcdManip *p_Manip,t_FmPcd *p_FmPcd) -+{ -+ t_AdOfTypeContLookup *p_Ad; -+ uint32_t tmpReg32 = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_Ad,E_INVALID_HANDLE); -+ -+ UNUSED(p_FmPcd); -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ -+ tmpReg32 = 0; -+ tmpReg32 |= (uint32_t)HMAN_OC_CAPWAP_INDEXED_STATS; -+ if (p_StatsParams->type == e_FM_PCD_STATS_PER_FLOWID) -+ tmpReg32 |= (uint32_t)0x16 << 16; -+ WRITE_UINT32(p_Ad->pcAndOffsets, tmpReg32); -+ -+ tmpReg32 = 0; -+ tmpReg32 |= FM_PCD_AD_CONT_LOOKUP_TYPE; -+ WRITE_UINT32(p_Ad->ccAdBase, tmpReg32); -+ -+ return E_OK; -+} -+ -+static t_Error InsrtHdrByTempl(t_FmPcdManipHdrInsrtParams *p_ManipParams, t_FmPcdManip *p_Manip, t_FmPcd *p_FmPcd) -+{ -+ t_FmPcdManipHdrInsrtByTemplateParams *p_InsrtByTemplate = &p_ManipParams->u.byTemplate; -+ uint8_t tmpReg8 = 0xff; -+ t_AdOfTypeContLookup *p_Ad; -+ bool ipModify = FALSE; -+ uint32_t tmpReg32 = 0, tmpRegNia = 0; -+ uint16_t tmpReg16 = 0; -+ t_Error err = E_OK; -+ uint8_t extraAddedBytes = 0, blockSize = 0, extraAddedBytesAlignedToBlockSize = 0, log2Num = 0; -+ uint8_t *p_Template = NULL; -+ -+ SANITY_CHECK_RETURN_ERROR(p_ManipParams,E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_Manip,E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_Ad,E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd,E_NULL_POINTER); -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ if (p_Manip->insrt) -+ { -+ if ((!p_InsrtByTemplate->size && p_InsrtByTemplate->modifyOuterIp) || -+ (!p_InsrtByTemplate->size && p_InsrtByTemplate->modifyOuterVlan)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Inconsistent parameters : asking for header template modifications with no template for insertion (template size)")); -+ -+ if (p_InsrtByTemplate->size && p_InsrtByTemplate->modifyOuterIp && (p_InsrtByTemplate->size <= p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Inconsistent parameters : size of template < ipOuterOffset")); -+ -+ if (p_InsrtByTemplate->size > 128) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Size of header template for insertion can not be more than 128")); -+ -+ if (p_InsrtByTemplate->size) -+ { -+ p_Manip->p_Template = (uint8_t *)FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, -+ p_InsrtByTemplate->size, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if(!p_Manip->p_Template) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory allocation in MURAM FAILED")); -+ -+ tmpReg32 = (uint32_t)(XX_VirtToPhys(p_Manip->p_Template) - (p_FmPcd->physicalMuramBase)); -+ tmpReg32 |= (uint32_t)p_InsrtByTemplate->size << 24; -+ *(uint32_t *)&p_Ad->matchTblPtr = tmpReg32; -+ } -+ -+ tmpReg32 = 0; -+ -+ p_Template = (uint8_t *)XX_Malloc(p_InsrtByTemplate->size * sizeof(uint8_t)); -+ -+ if (!p_Template) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("XX_Malloc allocation FAILED")); -+ -+ memcpy(p_Template, p_InsrtByTemplate->hdrTemplate, p_InsrtByTemplate->size * sizeof(uint8_t)); -+ -+ if (p_InsrtByTemplate->modifyOuterIp) -+ { -+ ipModify = TRUE; -+ -+ tmpReg8 = (uint8_t)p_Template[p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset]; -+ -+ if((tmpReg8 & 0xf0) == 0x40) -+ tmpReg8 = 4; -+ else if((tmpReg8 & 0xf0) == 0x60) -+ tmpReg8 = 6; -+ else -+ tmpReg8 = 0xff; -+ -+ if (tmpReg8 != 0xff) -+ { -+ if(p_InsrtByTemplate->modifyOuterIpParams.dscpEcn & 0xff00) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Inconsistent parameters : IPV4 present in header template, dscpEcn has to be only 1 byte")); -+ if(p_InsrtByTemplate->modifyOuterIpParams.recalculateLength) -+ { -+ -+ if((p_InsrtByTemplate->modifyOuterIpParams.recalculateLengthParams.extraBytesAddedAlignedToBlockSize + p_InsrtByTemplate->modifyOuterIpParams.recalculateLengthParams.extraBytesAddedNotAlignedToBlockSize) > 255) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("extra Byte added can not be more than 256 bytes")); -+ extraAddedBytes = (uint8_t) (p_InsrtByTemplate->modifyOuterIpParams.recalculateLengthParams.extraBytesAddedAlignedToBlockSize + p_InsrtByTemplate->modifyOuterIpParams.recalculateLengthParams.extraBytesAddedNotAlignedToBlockSize); -+ blockSize = p_InsrtByTemplate->modifyOuterIpParams.recalculateLengthParams.blockSize; -+ extraAddedBytesAlignedToBlockSize = p_InsrtByTemplate->modifyOuterIpParams.recalculateLengthParams.extraBytesAddedAlignedToBlockSize; -+ /*IP header template - IP totalLength - -+ (1 byte) extraByteForIp = headerTemplateSize - ipOffset + insertedBytesAfterThisStage , -+ in the case of SEC insertedBytesAfterThisStage - SEC trailer (21/31) + header(13) -+ second byte - extraByteForIp = headerTemplate - ipOffset + insertedBytesAfterThisStage*/ -+ } -+ if (blockSize) -+ { -+ if (!POWER_OF_2(blockSize)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("inputFrmPaddingUpToBlockSize has to be power of 2")); -+ } -+ -+ } -+ if (tmpReg8 == 4) -+ { -+ if ((IPv4_HDRCHECKSUM_FIELD_OFFSET_FROM_IP + p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset) > p_InsrtByTemplate->size) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Inconsistent parameters : IP present in header template, user asked for IP modifications but ipOffset + ipTotalLengthFieldOffset in header template bigger than template size")); -+ -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + IPv4_DSCECN_FIELD_OFFSET_FROM_IP] = (uint8_t)p_InsrtByTemplate->modifyOuterIpParams.dscpEcn; -+ -+ if (blockSize) -+ blockSize -= 1; -+ -+ if ((p_InsrtByTemplate->size - p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + extraAddedBytes) > 255) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("p_InsrtByTemplate->size - p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + extraAddedBytes has to be less than 255")); -+ -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + IPv4_TOTALLENGTH_FIELD_OFFSET_FROM_IP + 1] = blockSize; // IPV6 - in AD instead of SEQ IND -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + IPv4_TOTALLENGTH_FIELD_OFFSET_FROM_IP] = (uint8_t)(p_InsrtByTemplate->size - p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + extraAddedBytes);// for IPV6 decrement additional 40 bytes of IPV6 heade size -+ -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + IPv4_ID_FIELD_OFFSET_FROM_IP] = 0x00; -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + IPv4_ID_FIELD_OFFSET_FROM_IP + 1] = extraAddedBytesAlignedToBlockSize; -+ -+ /*IP header template - relevant only for ipv4 CheckSum = 0*/ -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + IPv4_HDRCHECKSUM_FIELD_OFFSET_FROM_IP] = 0x00; -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + IPv4_HDRCHECKSUM_FIELD_OFFSET_FROM_IP + 1] = 0x00; -+ -+ /*UDP checksum has to be 0*/ -+ if (p_InsrtByTemplate->modifyOuterIpParams.udpPresent) -+ { -+ if ((p_InsrtByTemplate->modifyOuterIpParams.udpOffset + UDP_CHECKSUM_FIELD_OFFSET_FROM_UDP + UDP_CHECKSUM_FIELD_SIZE) > p_InsrtByTemplate->size) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Inconsistent parameters : UDP present according to user but (UDP offset + UDP header size) < size of header template")); -+ -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.udpOffset + UDP_CHECKSUM_FIELD_OFFSET_FROM_UDP ] = 0x00; -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.udpOffset + UDP_CHECKSUM_FIELD_OFFSET_FROM_UDP + 1] = 0x00; -+ -+ } -+ -+ if (p_InsrtByTemplate->modifyOuterIpParams.ipIdentGenId > 7) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("ipIdentGenId has to be one out of 8 sequence number generators (0 - 7) for IP identification field")); -+ -+ tmpRegNia |= (uint32_t)p_InsrtByTemplate->modifyOuterIpParams.ipIdentGenId<<24; -+ } -+ else if (tmpReg8 == 6) -+ { -+ /*TODO - add check for maximum value of blockSize;*/ -+ if (blockSize) -+ LOG2(blockSize, log2Num); -+ tmpRegNia |= (uint32_t)log2Num << 24; -+ -+ // for IPV6 decrement additional 40 bytes of IPV6 heade size - because IPV6 header size is not included in payloadLength -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + IPv6_PAYLOAD_LENGTH_OFFSET_FROM_IP] = (uint8_t)(p_InsrtByTemplate->size - p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + extraAddedBytes - 40); -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + IPv6_PAYLOAD_LENGTH_OFFSET_FROM_IP + 1] = extraAddedBytesAlignedToBlockSize; -+ if (p_InsrtByTemplate->modifyOuterIpParams.udpPresent) -+ { -+ if ((p_InsrtByTemplate->modifyOuterIpParams.udpOffset + UDP_CHECKSUM_FIELD_OFFSET_FROM_UDP + UDP_CHECKSUM_FIELD_SIZE) > p_InsrtByTemplate->size) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Inconsistent parameters : UDP present according to user but (UDP offset + UDP header size) < size of header template")); -+ if (p_Template[p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset + IPv6_NEXT_HEADER_OFFSET_FROM_IP] != 0x88) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("OUr suppport is only IPv6/UDPLite")); -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.udpOffset + UDP_LENGTH_FIELD_OFFSET_FROM_UDP] = 0x00; -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.udpOffset + UDP_LENGTH_FIELD_OFFSET_FROM_UDP + 1] = 0x08; -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.udpOffset + UDP_CHECKSUM_FIELD_OFFSET_FROM_UDP] = 0x00; -+ p_Template[p_InsrtByTemplate->modifyOuterIpParams.udpOffset + UDP_CHECKSUM_FIELD_OFFSET_FROM_UDP + 1] = 0x00; -+ } -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("IP version supported only IPV4")); -+ } -+ -+ tmpReg32 = tmpReg16 = tmpReg8 = 0; -+ /*TODO - check it*/ -+ if (p_InsrtByTemplate->modifyOuterVlan) -+ { -+ if (p_InsrtByTemplate->modifyOuterVlanParams.vpri & ~0x07) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE,("Inconsistent parameters : user asked for VLAN modifications but VPRI more than 3 bits")); -+ -+ memcpy(&tmpReg16, &p_Template[VLAN_TAG_FIELD_OFFSET_FROM_ETH], 2*(sizeof(uint8_t))); -+ if ((tmpReg16 != 0x9100) && (tmpReg16!= 0x9200) && (tmpReg16 != 0x8100)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE,("Inconsistent parameters : user asked for VLAN modifications but Tag Protocol identifier is not VLAN ")); -+ -+ memcpy(&tmpReg8, &p_Template[14],1*(sizeof(uint8_t))); -+ tmpReg8 &= 0x1f; -+ tmpReg8 |= (uint8_t)(p_InsrtByTemplate->modifyOuterVlanParams.vpri << 5); -+ -+ p_Template[14] = tmpReg8; -+ } -+ -+ MemCpy8(p_Manip->p_Template, p_Template, p_InsrtByTemplate->size); -+ -+ XX_Free(p_Template); -+ } -+ -+ tmpReg32 = 0; -+ if (p_Manip->h_Frag) -+ { -+ tmpRegNia |= (uint32_t)(XX_VirtToPhys(p_Manip->h_Frag) - (p_FmPcd->physicalMuramBase)); -+ tmpReg32 |= (uint32_t)p_Manip->sizeForFragmentation << 16; -+ } -+ else -+ tmpReg32 = 0xffff0000; -+ -+ if (ipModify) -+ tmpReg32 |= (uint32_t)p_InsrtByTemplate->modifyOuterIpParams.ipOuterOffset << 8; -+ else -+ tmpReg32 |= (uint32_t)0x0000ff00; -+ -+ tmpReg32 |= (uint32_t)HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER; -+ *(uint32_t *)&p_Ad->pcAndOffsets = tmpReg32; -+ -+ tmpRegNia |= FM_PCD_AD_CONT_LOOKUP_TYPE; -+ *(uint32_t *)&p_Ad->ccAdBase = tmpRegNia; -+ -+ return err; -+} -+ -+static t_Error CheckStatsParamsAndSetType(t_FmPcdManip *p_Manip, t_FmPcdStatsParams *p_StatsParams) -+{ -+ -+ switch (p_StatsParams->type) -+ { -+ case (e_FM_PCD_STATS_PER_FLOWID): -+ p_Manip->opcode = HMAN_OC_CAPWAP_INDEXED_STATS; -+ p_Manip->muramAllocate = TRUE; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Unsupported statistics type")); -+ } -+ -+ return E_OK; -+} -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ -+static t_Error FillReassmManipParams(t_FmPcdManip *p_Manip, e_NetHeaderType hdr) -+{ -+ t_AdOfTypeContLookup *p_Ad; -+ t_FmPcd *p_FmPcd = (t_FmPcd *)p_Manip->h_FmPcd; -+ uint32_t tmpReg32; -+ t_Error err = E_OK; -+ -+ /* Creates the Reassembly Parameters table. It contains parameters that are specific to either the IPv4 reassembly -+ function or to the IPv6 reassembly function. If both IPv4 reassembly and IPv6 reassembly are required, then -+ two separate IP Reassembly Parameter tables are required.*/ -+ if ((err = CreateReassTable(p_Manip, hdr)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ /* Sets the first Ad register (ccAdBase) - Action Descriptor Type and Pointer to the Reassembly Parameters Table offset from MURAM*/ -+ tmpReg32 = 0; -+ tmpReg32 |= FM_PCD_AD_CONT_LOOKUP_TYPE; -+ -+ /* Gets the required Action descriptor table pointer */ -+ switch (hdr) -+ { -+ case HEADER_TYPE_IPv4: -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->reassmParams.ip.h_Ipv4Ad; -+ tmpReg32 |= (uint32_t)(XX_VirtToPhys( -+ p_Manip->reassmParams.ip.p_Ipv4ReassTbl) -+ - (p_FmPcd->physicalMuramBase)); -+ break; -+ case HEADER_TYPE_IPv6: -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->reassmParams.ip.h_Ipv6Ad; -+ tmpReg32 |= (uint32_t)(XX_VirtToPhys( -+ p_Manip->reassmParams.ip.p_Ipv6ReassTbl) -+ - (p_FmPcd->physicalMuramBase)); -+ break; -+ case HEADER_TYPE_CAPWAP: -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->reassmParams.capwap.h_Ad; -+ tmpReg32 |= (uint32_t)(XX_VirtToPhys( -+ p_Manip->reassmParams.capwap.p_ReassTbl) -+ - (p_FmPcd->physicalMuramBase)); -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("header type")); -+ } -+ -+ WRITE_UINT32(p_Ad->ccAdBase, tmpReg32); -+ -+ /* Sets the second Ad register (matchTblPtr) - Buffer pool ID (BPID for V2) and Scatter/Gather table offset*/ -+ /* mark the Scatter/Gather table offset to be set later on when the port will be known */ -+ p_Manip->updateParams = (NUM_OF_TASKS | NUM_OF_EXTRA_TASKS | DISCARD_MASK); -+ -+ if ((hdr == HEADER_TYPE_IPv6) || (hdr == HEADER_TYPE_IPv4)) -+ { -+#if (DPAA_VERSION == 10) -+ tmpReg32 = (uint32_t)(p_Manip->reassmParams.sgBpid << 8); -+ WRITE_UINT32(p_Ad->matchTblPtr, tmpReg32); -+#endif /* (DPAA_VERSION == 10) */ -+#if (DPAA_VERSION >= 11) -+ if (p_Manip->reassmParams.ip.nonConsistentSpFqid != 0) -+ { -+ tmpReg32 = FM_PCD_AD_NCSPFQIDM_MASK -+ | (uint32_t)(p_Manip->reassmParams.ip.nonConsistentSpFqid); -+ WRITE_UINT32(p_Ad->gmask, tmpReg32); -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ /* Sets the third Ad register (pcAndOffsets)- IP Reassemble Operation Code*/ -+ tmpReg32 = 0; -+ tmpReg32 |= (uint32_t)HMAN_OC_IP_REASSEMBLY; -+ } -+#if (DPAA_VERSION >= 11) -+ else -+ if (hdr == HEADER_TYPE_CAPWAP) -+ { -+ tmpReg32 = 0; -+ tmpReg32 |= (uint32_t)HMAN_OC_CAPWAP_REASSEMBLY; -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ WRITE_UINT32(p_Ad->pcAndOffsets, tmpReg32); -+ -+ p_Manip->reassm = TRUE; -+ -+ return E_OK; -+} -+ -+static t_Error SetIpv4ReassmManip(t_FmPcdManip *p_Manip) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)p_Manip->h_FmPcd; -+ -+ /* Allocation if IPv4 Action descriptor */ -+ p_Manip->reassmParams.ip.h_Ipv4Ad = (t_Handle)XX_MallocSmart( -+ FM_PCD_CC_AD_ENTRY_SIZE, p_Manip->reassmParams.dataMemId, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_Manip->reassmParams.ip.h_Ipv4Ad) -+ { -+ ReleaseManipHandler(p_Manip, p_FmPcd); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("Allocation of IPv4 table descriptor")); -+ } -+ -+ memset(p_Manip->reassmParams.ip.h_Ipv4Ad, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ /* Fill reassembly manipulation parameter in the IP Reassembly Action Descriptor */ -+ return FillReassmManipParams(p_Manip, HEADER_TYPE_IPv4); -+} -+ -+static t_Error SetIpv6ReassmManip(t_FmPcdManip *p_Manip) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)p_Manip->h_FmPcd; -+ -+ /* Allocation if IPv6 Action descriptor */ -+ p_Manip->reassmParams.ip.h_Ipv6Ad = (t_Handle)XX_MallocSmart( -+ FM_PCD_CC_AD_ENTRY_SIZE, p_Manip->reassmParams.dataMemId, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_Manip->reassmParams.ip.h_Ipv6Ad) -+ { -+ ReleaseManipHandler(p_Manip, p_FmPcd); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("Allocation of IPv6 table descriptor")); -+ } -+ -+ memset(p_Manip->reassmParams.ip.h_Ipv6Ad, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ /* Fill reassembly manipulation parameter in the IP Reassembly Action Descriptor */ -+ return FillReassmManipParams(p_Manip, HEADER_TYPE_IPv6); -+} -+ -+static t_Error IpReassembly(t_FmPcdManipReassemParams *p_ManipReassmParams, -+ t_FmPcdManip *p_Manip) -+{ -+ uint32_t maxSetNumber = 10000; -+ t_FmPcdManipReassemIpParams reassmManipParams = -+ p_ManipReassmParams->u.ipReassem; -+ t_Error res; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(((t_FmPcd *)p_Manip->h_FmPcd)->h_Hc, -+ E_INVALID_HANDLE); -+ -+ /* Check validation of user's parameter.*/ -+ if ((reassmManipParams.timeoutThresholdForReassmProcess < 1000) -+ || (reassmManipParams.timeoutThresholdForReassmProcess > 8000000)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("timeoutThresholdForReassmProcess should be 1msec - 8sec")); -+ /* It is recommended that the total number of entries in this table (number of sets * number of ways) -+ will be twice the number of frames that are expected to be reassembled simultaneously.*/ -+ if (reassmManipParams.maxNumFramesInProcess -+ > (reassmManipParams.maxNumFramesInProcess * maxSetNumber / 2)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("maxNumFramesInProcess has to be less than (maximun set number * number of ways / 2)")); -+ -+ if ((p_ManipReassmParams->hdr == HEADER_TYPE_IPv6) -+ && (reassmManipParams.minFragSize[1] < 256)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("minFragSize[1] must be >= 256")); -+ -+ /* Saves user's reassembly manipulation parameters */ -+ p_Manip->reassmParams.ip.relativeSchemeId[0] = -+ reassmManipParams.relativeSchemeId[0]; -+ p_Manip->reassmParams.ip.relativeSchemeId[1] = -+ reassmManipParams.relativeSchemeId[1]; -+ p_Manip->reassmParams.ip.numOfFramesPerHashEntry[0] = -+ reassmManipParams.numOfFramesPerHashEntry[0]; -+ p_Manip->reassmParams.ip.numOfFramesPerHashEntry[1] = -+ reassmManipParams.numOfFramesPerHashEntry[1]; -+ p_Manip->reassmParams.ip.minFragSize[0] = reassmManipParams.minFragSize[0]; -+ p_Manip->reassmParams.ip.minFragSize[1] = reassmManipParams.minFragSize[1]; -+ p_Manip->reassmParams.maxNumFramesInProcess = -+ reassmManipParams.maxNumFramesInProcess; -+ p_Manip->reassmParams.timeOutMode = reassmManipParams.timeOutMode; -+ p_Manip->reassmParams.fqidForTimeOutFrames = -+ reassmManipParams.fqidForTimeOutFrames; -+ p_Manip->reassmParams.timeoutThresholdForReassmProcess = -+ reassmManipParams.timeoutThresholdForReassmProcess; -+ p_Manip->reassmParams.dataMemId = reassmManipParams.dataMemId; -+ p_Manip->reassmParams.dataLiodnOffset = reassmManipParams.dataLiodnOffset; -+#if (DPAA_VERSION == 10) -+ p_Manip->reassmParams.sgBpid = reassmManipParams.sgBpid; -+#endif /* (DPAA_VERSION == 10) */ -+#if (DPAA_VERSION >= 11) -+ if (reassmManipParams.nonConsistentSpFqid != 0) -+ { -+ p_Manip->reassmParams.ip.nonConsistentSpFqid = -+ reassmManipParams.nonConsistentSpFqid; -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ /* Creates and initializes the IP Reassembly common parameter table */ -+ CreateReassCommonTable(p_Manip); -+ -+ /* Creation of IPv4 reassembly manipulation */ -+ if ((p_Manip->reassmParams.hdr == HEADER_TYPE_IPv6) -+ || (p_Manip->reassmParams.hdr == HEADER_TYPE_IPv4)) -+ { -+ res = SetIpv4ReassmManip(p_Manip); -+ if (res != E_OK) -+ return res; -+ } -+ -+ /* Creation of IPv6 reassembly manipulation */ -+ if (p_Manip->reassmParams.hdr == HEADER_TYPE_IPv6) -+ { -+ res = SetIpv6ReassmManip(p_Manip); -+ if (res != E_OK) -+ return res; -+ } -+ -+ return E_OK; -+} -+ -+static void setIpReassmSchemeParams(t_FmPcd* p_FmPcd, -+ t_FmPcdKgSchemeParams *p_Scheme, -+ t_Handle h_CcTree, bool ipv4, -+ uint8_t groupId) -+{ -+ uint32_t j; -+ uint8_t res; -+ -+ /* Configures scheme's network environment parameters */ -+ p_Scheme->netEnvParams.numOfDistinctionUnits = 2; -+ if (ipv4) -+ res = FmPcdNetEnvGetUnitId( -+ p_FmPcd, FmPcdGetNetEnvId(p_Scheme->netEnvParams.h_NetEnv), -+ HEADER_TYPE_IPv4, FALSE, 0); -+ else -+ res = FmPcdNetEnvGetUnitId( -+ p_FmPcd, FmPcdGetNetEnvId(p_Scheme->netEnvParams.h_NetEnv), -+ HEADER_TYPE_IPv6, FALSE, 0); -+ ASSERT_COND(res != FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS); -+ p_Scheme->netEnvParams.unitIds[0] = res; -+ -+ res = FmPcdNetEnvGetUnitId( -+ p_FmPcd, FmPcdGetNetEnvId(p_Scheme->netEnvParams.h_NetEnv), -+ HEADER_TYPE_USER_DEFINED_SHIM2, FALSE, 0); -+ ASSERT_COND(res != FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS); -+ p_Scheme->netEnvParams.unitIds[1] = res; -+ -+ /* Configures scheme's next engine parameters*/ -+ p_Scheme->nextEngine = e_FM_PCD_CC; -+ p_Scheme->kgNextEngineParams.cc.h_CcTree = h_CcTree; -+ p_Scheme->kgNextEngineParams.cc.grpId = groupId; -+ p_Scheme->useHash = TRUE; -+ -+ /* Configures scheme's key*/ -+ if (ipv4 == TRUE) -+ { -+ p_Scheme->keyExtractAndHashParams.numOfUsedExtracts = 4; -+ p_Scheme->keyExtractAndHashParams.extractArray[0].type = -+ e_FM_PCD_EXTRACT_BY_HDR; -+ p_Scheme->keyExtractAndHashParams.extractArray[0].extractByHdr.type = -+ e_FM_PCD_EXTRACT_FULL_FIELD; -+ p_Scheme->keyExtractAndHashParams.extractArray[0].extractByHdr.hdr = -+ HEADER_TYPE_IPv4; -+ p_Scheme->keyExtractAndHashParams.extractArray[0].extractByHdr.extractByHdrType.fullField.ipv4 = -+ NET_HEADER_FIELD_IPv4_DST_IP; -+ p_Scheme->keyExtractAndHashParams.extractArray[1].type = -+ e_FM_PCD_EXTRACT_BY_HDR; -+ p_Scheme->keyExtractAndHashParams.extractArray[1].extractByHdr.type = -+ e_FM_PCD_EXTRACT_FULL_FIELD; -+ p_Scheme->keyExtractAndHashParams.extractArray[1].extractByHdr.hdr = -+ HEADER_TYPE_IPv4; -+ p_Scheme->keyExtractAndHashParams.extractArray[1].extractByHdr.extractByHdrType.fullField.ipv4 = -+ NET_HEADER_FIELD_IPv4_SRC_IP; -+ p_Scheme->keyExtractAndHashParams.extractArray[2].type = -+ e_FM_PCD_EXTRACT_BY_HDR; -+ p_Scheme->keyExtractAndHashParams.extractArray[2].extractByHdr.type = -+ e_FM_PCD_EXTRACT_FULL_FIELD; -+ p_Scheme->keyExtractAndHashParams.extractArray[2].extractByHdr.hdr = -+ HEADER_TYPE_IPv4; -+ p_Scheme->keyExtractAndHashParams.extractArray[2].extractByHdr.extractByHdrType.fullField.ipv4 = -+ NET_HEADER_FIELD_IPv4_PROTO; -+ p_Scheme->keyExtractAndHashParams.extractArray[3].type = -+ e_FM_PCD_EXTRACT_BY_HDR; -+ p_Scheme->keyExtractAndHashParams.extractArray[3].extractByHdr.hdr = -+ HEADER_TYPE_IPv4; -+ p_Scheme->keyExtractAndHashParams.extractArray[3].extractByHdr.type = -+ e_FM_PCD_EXTRACT_FROM_HDR; -+ p_Scheme->keyExtractAndHashParams.extractArray[3].extractByHdr.ignoreProtocolValidation = -+ FALSE; -+ p_Scheme->keyExtractAndHashParams.extractArray[3].extractByHdr.extractByHdrType.fromHdr.size = -+ 2; -+ p_Scheme->keyExtractAndHashParams.extractArray[3].extractByHdr.extractByHdrType.fromHdr.offset = -+ 4; -+ } -+ else /* IPv6 */ -+ { -+ p_Scheme->keyExtractAndHashParams.numOfUsedExtracts = 3; -+ p_Scheme->keyExtractAndHashParams.extractArray[0].type = -+ e_FM_PCD_EXTRACT_BY_HDR; -+ p_Scheme->keyExtractAndHashParams.extractArray[0].extractByHdr.type = -+ e_FM_PCD_EXTRACT_FULL_FIELD; -+ p_Scheme->keyExtractAndHashParams.extractArray[0].extractByHdr.hdr = -+ HEADER_TYPE_IPv6; -+ p_Scheme->keyExtractAndHashParams.extractArray[0].extractByHdr.extractByHdrType.fullField.ipv6 = -+ NET_HEADER_FIELD_IPv6_DST_IP; -+ p_Scheme->keyExtractAndHashParams.extractArray[1].type = -+ e_FM_PCD_EXTRACT_BY_HDR; -+ p_Scheme->keyExtractAndHashParams.extractArray[1].extractByHdr.type = -+ e_FM_PCD_EXTRACT_FULL_FIELD; -+ p_Scheme->keyExtractAndHashParams.extractArray[1].extractByHdr.hdr = -+ HEADER_TYPE_IPv6; -+ p_Scheme->keyExtractAndHashParams.extractArray[1].extractByHdr.extractByHdrType.fullField.ipv6 = -+ NET_HEADER_FIELD_IPv6_SRC_IP; -+ p_Scheme->keyExtractAndHashParams.extractArray[2].type = -+ e_FM_PCD_EXTRACT_BY_HDR; -+ p_Scheme->keyExtractAndHashParams.extractArray[2].extractByHdr.hdr = -+ HEADER_TYPE_USER_DEFINED_SHIM2; -+ p_Scheme->keyExtractAndHashParams.extractArray[2].extractByHdr.type = -+ e_FM_PCD_EXTRACT_FROM_HDR; -+ p_Scheme->keyExtractAndHashParams.extractArray[2].extractByHdr.extractByHdrType.fromHdr.size = -+ 4; -+ p_Scheme->keyExtractAndHashParams.extractArray[2].extractByHdr.extractByHdrType.fromHdr.offset = -+ 4; -+ p_Scheme->keyExtractAndHashParams.extractArray[2].extractByHdr.ignoreProtocolValidation = -+ TRUE; -+ } -+ -+ p_Scheme->keyExtractAndHashParams.privateDflt0 = 0x01020304; -+ p_Scheme->keyExtractAndHashParams.privateDflt1 = 0x11121314; -+ p_Scheme->keyExtractAndHashParams.numOfUsedDflts = -+ FM_PCD_KG_NUM_OF_DEFAULT_GROUPS; -+ for (j = 0; j < FM_PCD_KG_NUM_OF_DEFAULT_GROUPS; j++) -+ { -+ p_Scheme->keyExtractAndHashParams.dflts[j].type = -+ (e_FmPcdKgKnownFieldsDfltTypes)j; /* all types */ -+ p_Scheme->keyExtractAndHashParams.dflts[j].dfltSelect = -+ e_FM_PCD_KG_DFLT_GBL_0; -+ } -+} -+ -+static t_Error IpReassemblyStats(t_FmPcdManip *p_Manip, -+ t_FmPcdManipReassemIpStats *p_Stats) -+{ -+ ASSERT_COND(p_Manip); -+ ASSERT_COND(p_Stats); -+ ASSERT_COND(p_Manip->reassmParams.p_ReassCommonTbl); -+ -+ p_Stats->timeout = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalTimeOutCounter); -+ p_Stats->rfdPoolBusy = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalRfdPoolBusyCounter); -+ p_Stats->internalBufferBusy = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalInternalBufferBusy); -+ p_Stats->externalBufferBusy = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalExternalBufferBusy); -+ p_Stats->sgFragments = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalSgFragmentCounter); -+ p_Stats->dmaSemaphoreDepletion = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalDmaSemaphoreDepletionCounter); -+#if (DPAA_VERSION >= 11) -+ p_Stats->nonConsistentSp = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalNCSPCounter); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ if (p_Manip->reassmParams.ip.p_Ipv4ReassTbl) -+ { -+ p_Stats->specificHdrStatistics[0].successfullyReassembled = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv4ReassTbl->totalSuccessfullyReasmFramesCounter); -+ p_Stats->specificHdrStatistics[0].validFragments = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv4ReassTbl->totalValidFragmentCounter); -+ p_Stats->specificHdrStatistics[0].processedFragments = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv4ReassTbl->totalProcessedFragCounter); -+ p_Stats->specificHdrStatistics[0].malformedFragments = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv4ReassTbl->totalMalformdFragCounter); -+ p_Stats->specificHdrStatistics[0].autoLearnBusy = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv4ReassTbl->totalSetBusyCounter); -+ p_Stats->specificHdrStatistics[0].discardedFragments = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv4ReassTbl->totalDiscardedFragsCounter); -+ p_Stats->specificHdrStatistics[0].moreThan16Fragments = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv4ReassTbl->totalMoreThan16FramesCounter); -+ } -+ if (p_Manip->reassmParams.ip.p_Ipv6ReassTbl) -+ { -+ p_Stats->specificHdrStatistics[1].successfullyReassembled = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv6ReassTbl->totalSuccessfullyReasmFramesCounter); -+ p_Stats->specificHdrStatistics[1].validFragments = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv6ReassTbl->totalValidFragmentCounter); -+ p_Stats->specificHdrStatistics[1].processedFragments = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv6ReassTbl->totalProcessedFragCounter); -+ p_Stats->specificHdrStatistics[1].malformedFragments = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv6ReassTbl->totalMalformdFragCounter); -+ p_Stats->specificHdrStatistics[1].autoLearnBusy = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv6ReassTbl->totalSetBusyCounter); -+ p_Stats->specificHdrStatistics[1].discardedFragments = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv6ReassTbl->totalDiscardedFragsCounter); -+ p_Stats->specificHdrStatistics[1].moreThan16Fragments = -+ GET_UINT32(p_Manip->reassmParams.ip.p_Ipv6ReassTbl->totalMoreThan16FramesCounter); -+ } -+ return E_OK; -+} -+ -+static t_Error IpFragmentationStats(t_FmPcdManip *p_Manip, -+ t_FmPcdManipFragIpStats *p_Stats) -+{ -+ t_AdOfTypeContLookup *p_Ad; -+ -+ ASSERT_COND(p_Manip); -+ ASSERT_COND(p_Stats); -+ ASSERT_COND(p_Manip->h_Ad); -+ ASSERT_COND(p_Manip->fragParams.p_Frag); -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ -+ p_Stats->totalFrames = GET_UINT32(p_Ad->gmask); -+ p_Stats->fragmentedFrames = GET_UINT32(p_Manip->fragParams.p_Frag->ccAdBase) -+ & 0x00ffffff; -+ p_Stats->generatedFragments = -+ GET_UINT32(p_Manip->fragParams.p_Frag->matchTblPtr); -+ -+ return E_OK; -+} -+ -+static t_Error IpFragmentation(t_FmPcdManipFragIpParams *p_ManipParams, -+ t_FmPcdManip *p_Manip) -+{ -+ uint32_t pcAndOffsetsReg = 0, ccAdBaseReg = 0, gmaskReg = 0; -+ t_FmPcd *p_FmPcd; -+#if (DPAA_VERSION == 10) -+ t_Error err = E_OK; -+#endif /* (DPAA_VERSION == 10) */ -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_Ad, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_ManipParams->sizeForFragmentation != 0xFFFF, -+ E_INVALID_VALUE); -+ -+ p_FmPcd = p_Manip->h_FmPcd; -+ /* Allocation of fragmentation Action Descriptor */ -+ p_Manip->fragParams.p_Frag = (t_AdOfTypeContLookup *)FM_MURAM_AllocMem( -+ p_FmPcd->h_FmMuram, FM_PCD_CC_AD_ENTRY_SIZE, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_Manip->fragParams.p_Frag) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM alloc for Fragmentation table descriptor")); -+ MemSet8(p_Manip->fragParams.p_Frag, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ /* Prepare the third Ad register (pcAndOffsets)- OperationCode */ -+ pcAndOffsetsReg = (uint32_t)HMAN_OC_IP_FRAGMENTATION; -+ -+ /* Prepare the first Ad register (ccAdBase) - Don't frag action and Action descriptor type*/ -+ ccAdBaseReg = FM_PCD_AD_CONT_LOOKUP_TYPE; -+ ccAdBaseReg |= (p_ManipParams->dontFragAction -+ << FM_PCD_MANIP_IP_FRAG_DF_SHIFT); -+ -+ -+ /* Set Scatter/Gather BPid */ -+ if (p_ManipParams->sgBpidEn) -+ { -+ ccAdBaseReg |= FM_PCD_MANIP_IP_FRAG_SG_BDID_EN; -+ pcAndOffsetsReg |= ((p_ManipParams->sgBpid -+ << FM_PCD_MANIP_IP_FRAG_SG_BDID_SHIFT) -+ & FM_PCD_MANIP_IP_FRAG_SG_BDID_MASK); -+ } -+ -+ /* Prepare the first Ad register (gmask) - scratch buffer pool id and Pointer to fragment ID */ -+ gmaskReg = (uint32_t)(XX_VirtToPhys(UINT_TO_PTR(p_FmPcd->ipv6FrameIdAddr)) -+ - p_FmPcd->physicalMuramBase); -+#if (DPAA_VERSION == 10) -+ gmaskReg |= p_ManipParams->scratchBpid << FM_PCD_MANIP_IP_FRAG_SCRATCH_BPID; -+#else -+ gmaskReg |= (0xFF) << FM_PCD_MANIP_IP_FRAG_SCRATCH_BPID; -+#endif /* (DPAA_VERSION == 10) */ -+ -+ /* Set all Ad registers */ -+ WRITE_UINT32(p_Manip->fragParams.p_Frag->pcAndOffsets, pcAndOffsetsReg); -+ WRITE_UINT32(p_Manip->fragParams.p_Frag->ccAdBase, ccAdBaseReg); -+ WRITE_UINT32(p_Manip->fragParams.p_Frag->gmask, gmaskReg); -+ -+ /* Saves user's fragmentation manipulation parameters */ -+ p_Manip->frag = TRUE; -+ p_Manip->sizeForFragmentation = p_ManipParams->sizeForFragmentation; -+ -+#if (DPAA_VERSION == 10) -+ p_Manip->fragParams.scratchBpid = p_ManipParams->scratchBpid; -+ -+ /* scratch buffer pool initialization */ -+ if ((err = FmPcdFragHcScratchPoolFill((t_Handle)p_FmPcd, p_ManipParams->scratchBpid)) != E_OK) -+ { -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, p_Manip->fragParams.p_Frag); -+ p_Manip->fragParams.p_Frag = NULL; -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+#endif /* (DPAA_VERSION == 10) */ -+ -+ return E_OK; -+} -+ -+static t_Error IPManip(t_FmPcdManip *p_Manip) -+{ -+ t_Error err = E_OK; -+ t_FmPcd *p_FmPcd; -+ t_AdOfTypeContLookup *p_Ad; -+ uint32_t tmpReg32 = 0, tmpRegNia = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip, E_INVALID_HANDLE); -+ p_FmPcd = p_Manip->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ -+ tmpReg32 = FM_PCD_MANIP_IP_NO_FRAGMENTATION; -+ if (p_Manip->frag == TRUE) -+ { -+ tmpRegNia = (uint32_t)(XX_VirtToPhys(p_Manip->fragParams.p_Frag) -+ - (p_FmPcd->physicalMuramBase)); -+ tmpReg32 = (uint32_t)p_Manip->sizeForFragmentation -+ << FM_PCD_MANIP_IP_MTU_SHIFT; -+ } -+ -+ tmpRegNia |= FM_PCD_AD_CONT_LOOKUP_TYPE; -+ tmpReg32 |= HMAN_OC_IP_MANIP; -+ -+#if (DPAA_VERSION >= 11) -+ tmpRegNia |= FM_PCD_MANIP_IP_CNIA; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ WRITE_UINT32(p_Ad->pcAndOffsets, tmpReg32); -+ WRITE_UINT32(p_Ad->ccAdBase, tmpRegNia); -+ WRITE_UINT32(p_Ad->gmask, 0); -+ /* Total frame counter - MUST be initialized to zero.*/ -+ -+ return err; -+} -+ -+static t_Error UpdateInitIpFrag(t_Handle h_FmPcd, t_Handle h_PcdParams, -+ t_Handle h_FmPort, t_FmPcdManip *p_Manip, -+ t_Handle h_Ad, bool validate) -+{ -+ t_FmPortGetSetCcParams fmPortGetSetCcParams; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Manip->opcode == HMAN_OC_IP_FRAGMENTATION), -+ E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(h_FmPort, E_INVALID_HANDLE); -+ -+ UNUSED(h_FmPcd); -+ UNUSED(h_Ad); -+ UNUSED(h_PcdParams); -+ UNUSED(validate); -+ UNUSED(p_Manip); -+ -+ fmPortGetSetCcParams.setCcParams.type = 0; -+ fmPortGetSetCcParams.getCcParams.type = MANIP_EXTRA_SPACE; -+ if ((err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (!fmPortGetSetCcParams.getCcParams.internalBufferOffset) -+ DBG(WARNING, ("manipExtraSpace must be larger than '0'")); -+ -+ return E_OK; -+} -+ -+static t_Error IPSecManip(t_FmPcdManipParams *p_ManipParams, -+ t_FmPcdManip *p_Manip) -+{ -+ t_AdOfTypeContLookup *p_Ad; -+ t_FmPcdManipSpecialOffloadIPSecParams *p_IPSecParams; -+ t_Error err = E_OK; -+ uint32_t tmpReg32 = 0; -+ uint32_t power; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_ManipParams, E_INVALID_HANDLE); -+ -+ p_IPSecParams = &p_ManipParams->u.specialOffload.u.ipsec; -+ -+ SANITY_CHECK_RETURN_ERROR( -+ !p_IPSecParams->variableIpHdrLen || p_IPSecParams->decryption, -+ E_INVALID_VALUE); -+ SANITY_CHECK_RETURN_ERROR( -+ !p_IPSecParams->variableIpVersion || !p_IPSecParams->decryption, -+ E_INVALID_VALUE); -+ SANITY_CHECK_RETURN_ERROR( -+ !p_IPSecParams->variableIpVersion || p_IPSecParams->outerIPHdrLen, -+ E_INVALID_VALUE); -+ SANITY_CHECK_RETURN_ERROR( -+ !p_IPSecParams->arwSize || p_IPSecParams->arwAddr, -+ E_INVALID_VALUE); -+ SANITY_CHECK_RETURN_ERROR( -+ !p_IPSecParams->arwSize || p_IPSecParams->decryption, -+ E_INVALID_VALUE); -+ SANITY_CHECK_RETURN_ERROR((p_IPSecParams->arwSize % 16) == 0, E_INVALID_VALUE); -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ -+ tmpReg32 |= FM_PCD_AD_CONT_LOOKUP_TYPE; -+ tmpReg32 |= (p_IPSecParams->decryption) ? FM_PCD_MANIP_IPSEC_DEC : 0; -+ tmpReg32 |= (p_IPSecParams->ecnCopy) ? FM_PCD_MANIP_IPSEC_ECN_EN : 0; -+ tmpReg32 |= (p_IPSecParams->dscpCopy) ? FM_PCD_MANIP_IPSEC_DSCP_EN : 0; -+ tmpReg32 |= -+ (p_IPSecParams->variableIpHdrLen) ? FM_PCD_MANIP_IPSEC_VIPL_EN : 0; -+ tmpReg32 |= -+ (p_IPSecParams->variableIpVersion) ? FM_PCD_MANIP_IPSEC_VIPV_EN : 0; -+ if (p_IPSecParams->arwSize) -+ tmpReg32 |= (uint32_t)((XX_VirtToPhys(UINT_TO_PTR(p_IPSecParams->arwAddr))-FM_MM_MURAM) -+ & (FM_MURAM_SIZE-1)); -+ WRITE_UINT32(p_Ad->ccAdBase, tmpReg32); -+ -+ tmpReg32 = 0; -+ if (p_IPSecParams->arwSize) { -+ NEXT_POWER_OF_2((p_IPSecParams->arwSize + 32), power); -+ LOG2(power, power); -+ tmpReg32 = (p_IPSecParams->arwSize | (power - 5)) << FM_PCD_MANIP_IPSEC_ARW_SIZE_SHIFT; -+ } -+ -+ if (p_ManipParams->h_NextManip) -+ tmpReg32 |= -+ (uint32_t)(XX_VirtToPhys(((t_FmPcdManip *)p_ManipParams->h_NextManip)->h_Ad)- -+ (((t_FmPcd *)p_Manip->h_FmPcd)->physicalMuramBase)) >> 4; -+ WRITE_UINT32(p_Ad->matchTblPtr, tmpReg32); -+ -+ tmpReg32 = HMAN_OC_IPSEC_MANIP; -+ tmpReg32 |= p_IPSecParams->outerIPHdrLen -+ << FM_PCD_MANIP_IPSEC_IP_HDR_LEN_SHIFT; -+ if (p_ManipParams->h_NextManip) -+ tmpReg32 |= FM_PCD_MANIP_IPSEC_NADEN; -+ WRITE_UINT32(p_Ad->pcAndOffsets, tmpReg32); -+ -+ return err; -+} -+ -+static t_Error SetCapwapReassmManip(t_FmPcdManip *p_Manip) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)p_Manip->h_FmPcd; -+ -+ /* Allocation if CAPWAP Action descriptor */ -+ p_Manip->reassmParams.capwap.h_Ad = (t_Handle)XX_MallocSmart( -+ FM_PCD_CC_AD_ENTRY_SIZE, p_Manip->reassmParams.dataMemId, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_Manip->reassmParams.capwap.h_Ad) -+ { -+ ReleaseManipHandler(p_Manip, p_FmPcd); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("Allocation of CAPWAP table descriptor")); -+ } -+ -+ memset(p_Manip->reassmParams.capwap.h_Ad, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ /* Fill reassembly manipulation parameter in the Reassembly Action Descriptor */ -+ return FillReassmManipParams(p_Manip, HEADER_TYPE_CAPWAP); -+} -+ -+static void setCapwapReassmSchemeParams(t_FmPcd* p_FmPcd, -+ t_FmPcdKgSchemeParams *p_Scheme, -+ t_Handle h_CcTree, uint8_t groupId) -+{ -+ uint8_t res; -+ -+ /* Configures scheme's network environment parameters */ -+ p_Scheme->netEnvParams.numOfDistinctionUnits = 1; -+ res = FmPcdNetEnvGetUnitId( -+ p_FmPcd, FmPcdGetNetEnvId(p_Scheme->netEnvParams.h_NetEnv), -+ HEADER_TYPE_USER_DEFINED_SHIM2, FALSE, 0); -+ ASSERT_COND(res != FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS); -+ p_Scheme->netEnvParams.unitIds[0] = res; -+ -+ /* Configures scheme's next engine parameters*/ -+ p_Scheme->nextEngine = e_FM_PCD_CC; -+ p_Scheme->kgNextEngineParams.cc.h_CcTree = h_CcTree; -+ p_Scheme->kgNextEngineParams.cc.grpId = groupId; -+ p_Scheme->useHash = TRUE; -+ -+ /* Configures scheme's key*/ -+ p_Scheme->keyExtractAndHashParams.numOfUsedExtracts = 2; -+ p_Scheme->keyExtractAndHashParams.extractArray[0].type = -+ e_FM_PCD_EXTRACT_NON_HDR; -+ p_Scheme->keyExtractAndHashParams.extractArray[0].extractNonHdr.src = -+ e_FM_PCD_EXTRACT_FROM_PARSE_RESULT; -+ p_Scheme->keyExtractAndHashParams.extractArray[0].extractNonHdr.action = -+ e_FM_PCD_ACTION_NONE; -+ p_Scheme->keyExtractAndHashParams.extractArray[0].extractNonHdr.offset = 20; -+ p_Scheme->keyExtractAndHashParams.extractArray[0].extractNonHdr.size = 4; -+ p_Scheme->keyExtractAndHashParams.extractArray[1].type = -+ e_FM_PCD_EXTRACT_NON_HDR; -+ p_Scheme->keyExtractAndHashParams.extractArray[1].extractNonHdr.src = -+ e_FM_PCD_EXTRACT_FROM_DFLT_VALUE; -+ p_Scheme->keyExtractAndHashParams.extractArray[1].extractNonHdr.action = -+ e_FM_PCD_ACTION_NONE; -+ p_Scheme->keyExtractAndHashParams.extractArray[1].extractNonHdr.offset = 0; -+ p_Scheme->keyExtractAndHashParams.extractArray[1].extractNonHdr.size = 1; -+ -+ p_Scheme->keyExtractAndHashParams.privateDflt0 = 0x0; -+ p_Scheme->keyExtractAndHashParams.privateDflt1 = 0x0; -+ p_Scheme->keyExtractAndHashParams.numOfUsedDflts = 1; -+ p_Scheme->keyExtractAndHashParams.dflts[0].type = e_FM_PCD_KG_GENERIC_NOT_FROM_DATA; -+ p_Scheme->keyExtractAndHashParams.dflts[0].dfltSelect = e_FM_PCD_KG_DFLT_PRIVATE_0; -+} -+ -+#if (DPAA_VERSION >= 11) -+static t_Error CapwapReassemblyStats(t_FmPcdManip *p_Manip, -+ t_FmPcdManipReassemCapwapStats *p_Stats) -+{ -+ ASSERT_COND(p_Manip); -+ ASSERT_COND(p_Stats); -+ ASSERT_COND(p_Manip->reassmParams.p_ReassCommonTbl); -+ -+ p_Stats->timeout = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalTimeOutCounter); -+ p_Stats->rfdPoolBusy = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalRfdPoolBusyCounter); -+ p_Stats->internalBufferBusy = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalInternalBufferBusy); -+ p_Stats->externalBufferBusy = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalExternalBufferBusy); -+ p_Stats->sgFragments = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalSgFragmentCounter); -+ p_Stats->dmaSemaphoreDepletion = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalDmaSemaphoreDepletionCounter); -+ p_Stats->exceedMaxReassemblyFrameLen = -+ GET_UINT32(p_Manip->reassmParams.p_ReassCommonTbl->totalNCSPCounter); -+ -+ p_Stats->successfullyReassembled = -+ GET_UINT32(p_Manip->reassmParams.capwap.p_ReassTbl->totalSuccessfullyReasmFramesCounter); -+ p_Stats->validFragments = -+ GET_UINT32(p_Manip->reassmParams.capwap.p_ReassTbl->totalValidFragmentCounter); -+ p_Stats->processedFragments = -+ GET_UINT32(p_Manip->reassmParams.capwap.p_ReassTbl->totalProcessedFragCounter); -+ p_Stats->malformedFragments = -+ GET_UINT32(p_Manip->reassmParams.capwap.p_ReassTbl->totalMalformdFragCounter); -+ p_Stats->autoLearnBusy = -+ GET_UINT32(p_Manip->reassmParams.capwap.p_ReassTbl->totalSetBusyCounter); -+ p_Stats->discardedFragments = -+ GET_UINT32(p_Manip->reassmParams.capwap.p_ReassTbl->totalDiscardedFragsCounter); -+ p_Stats->moreThan16Fragments = -+ GET_UINT32(p_Manip->reassmParams.capwap.p_ReassTbl->totalMoreThan16FramesCounter); -+ -+ return E_OK; -+} -+ -+static t_Error CapwapFragmentationStats(t_FmPcdManip *p_Manip, -+ t_FmPcdManipFragCapwapStats *p_Stats) -+{ -+ t_AdOfTypeContLookup *p_Ad; -+ -+ ASSERT_COND(p_Manip); -+ ASSERT_COND(p_Stats); -+ ASSERT_COND(p_Manip->h_Ad); -+ ASSERT_COND(p_Manip->fragParams.p_Frag); -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ -+ p_Stats->totalFrames = GET_UINT32(p_Ad->gmask); -+ -+ return E_OK; -+} -+ -+static t_Error CapwapReassembly(t_FmPcdManipReassemParams *p_ManipReassmParams, -+ t_FmPcdManip *p_Manip) -+{ -+ uint32_t maxSetNumber = 10000; -+ t_FmPcdManipReassemCapwapParams reassmManipParams = -+ p_ManipReassmParams->u.capwapReassem; -+ t_Error res; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(((t_FmPcd *)p_Manip->h_FmPcd)->h_Hc, -+ E_INVALID_HANDLE); -+ -+ /* Check validation of user's parameter.*/ -+ if ((reassmManipParams.timeoutThresholdForReassmProcess < 1000) -+ || (reassmManipParams.timeoutThresholdForReassmProcess > 8000000)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("timeoutThresholdForReassmProcess should be 1msec - 8sec")); -+ /* It is recommended that the total number of entries in this table (number of sets * number of ways) -+ will be twice the number of frames that are expected to be reassembled simultaneously.*/ -+ if (reassmManipParams.maxNumFramesInProcess -+ > (reassmManipParams.maxNumFramesInProcess * maxSetNumber / 2)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("maxNumFramesInProcess has to be less than (maximun set number * number of ways / 2)")); -+ -+ /* Saves user's reassembly manipulation parameters */ -+ p_Manip->reassmParams.capwap.relativeSchemeId = -+ reassmManipParams.relativeSchemeId; -+ p_Manip->reassmParams.capwap.numOfFramesPerHashEntry = -+ reassmManipParams.numOfFramesPerHashEntry; -+ p_Manip->reassmParams.capwap.maxRessembledsSize = -+ reassmManipParams.maxReassembledFrameLength; -+ p_Manip->reassmParams.maxNumFramesInProcess = -+ reassmManipParams.maxNumFramesInProcess; -+ p_Manip->reassmParams.timeOutMode = reassmManipParams.timeOutMode; -+ p_Manip->reassmParams.fqidForTimeOutFrames = -+ reassmManipParams.fqidForTimeOutFrames; -+ p_Manip->reassmParams.timeoutThresholdForReassmProcess = -+ reassmManipParams.timeoutThresholdForReassmProcess; -+ p_Manip->reassmParams.dataMemId = reassmManipParams.dataMemId; -+ p_Manip->reassmParams.dataLiodnOffset = reassmManipParams.dataLiodnOffset; -+ -+ /* Creates and initializes the Reassembly common parameter table */ -+ CreateReassCommonTable(p_Manip); -+ -+ res = SetCapwapReassmManip(p_Manip); -+ if (res != E_OK) -+ return res; -+ -+ return E_OK; -+} -+ -+static t_Error CapwapFragmentation(t_FmPcdManipFragCapwapParams *p_ManipParams, -+ t_FmPcdManip *p_Manip) -+{ -+ t_FmPcd *p_FmPcd; -+ t_AdOfTypeContLookup *p_Ad; -+ uint32_t pcAndOffsetsReg = 0, ccAdBaseReg = 0, gmaskReg = 0; -+ uint32_t tmpReg32 = 0, tmpRegNia = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip->h_Ad, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_ManipParams->sizeForFragmentation != 0xFFFF, -+ E_INVALID_VALUE); -+ p_FmPcd = p_Manip->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ -+ /* Allocation of fragmentation Action Descriptor */ -+ p_Manip->fragParams.p_Frag = (t_AdOfTypeContLookup *)FM_MURAM_AllocMem( -+ p_FmPcd->h_FmMuram, FM_PCD_CC_AD_ENTRY_SIZE, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_Manip->fragParams.p_Frag) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("MURAM alloc for Fragmentation table descriptor")); -+ MemSet8(p_Manip->fragParams.p_Frag, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ /* Prepare the third Ad register (pcAndOffsets)- OperationCode */ -+ pcAndOffsetsReg = (uint32_t)HMAN_OC_CAPWAP_FRAGMENTATION; -+ -+ /* Prepare the first Ad register (ccAdBase) - Don't frag action and Action descriptor type*/ -+ ccAdBaseReg = FM_PCD_AD_CONT_LOOKUP_TYPE; -+ ccAdBaseReg |= -+ (p_ManipParams->compressModeEn) ? FM_PCD_MANIP_CAPWAP_FRAG_COMPRESS_EN : -+ 0; -+ -+ /* Set Scatter/Gather BPid */ -+ if (p_ManipParams->sgBpidEn) -+ { -+ ccAdBaseReg |= FM_PCD_MANIP_CAPWAP_FRAG_SG_BDID_EN; -+ pcAndOffsetsReg |= ((p_ManipParams->sgBpid -+ << FM_PCD_MANIP_CAPWAP_FRAG_SG_BDID_SHIFT) -+ & FM_PCD_MANIP_CAPWAP_FRAG_SG_BDID_MASK); -+ } -+ -+ /* Prepare the first Ad register (gmask) - scratch buffer pool id and Pointer to fragment ID */ -+ gmaskReg = (uint32_t)(XX_VirtToPhys(UINT_TO_PTR(p_FmPcd->capwapFrameIdAddr)) -+ - p_FmPcd->physicalMuramBase); -+ gmaskReg |= (0xFF) << FM_PCD_MANIP_IP_FRAG_SCRATCH_BPID; -+ -+ /* Set all Ad registers */ -+ WRITE_UINT32(p_Manip->fragParams.p_Frag->pcAndOffsets, pcAndOffsetsReg); -+ WRITE_UINT32(p_Manip->fragParams.p_Frag->ccAdBase, ccAdBaseReg); -+ WRITE_UINT32(p_Manip->fragParams.p_Frag->gmask, gmaskReg); -+ -+ /* Saves user's fragmentation manipulation parameters */ -+ p_Manip->frag = TRUE; -+ p_Manip->sizeForFragmentation = p_ManipParams->sizeForFragmentation; -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ -+ tmpRegNia = (uint32_t)(XX_VirtToPhys(p_Manip->fragParams.p_Frag) -+ - (p_FmPcd->physicalMuramBase)); -+ tmpReg32 = (uint32_t)p_Manip->sizeForFragmentation -+ << FM_PCD_MANIP_CAPWAP_FRAG_CHECK_MTU_SHIFT; -+ -+ tmpRegNia |= FM_PCD_AD_CONT_LOOKUP_TYPE; -+ tmpReg32 |= HMAN_OC_CAPWAP_FRAG_CHECK; -+ -+ tmpRegNia |= FM_PCD_MANIP_CAPWAP_FRAG_CHECK_CNIA; -+ -+ WRITE_UINT32(p_Ad->pcAndOffsets, tmpReg32); -+ WRITE_UINT32(p_Ad->ccAdBase, tmpRegNia); -+ WRITE_UINT32(p_Ad->gmask, 0); -+ /* Total frame counter - MUST be initialized to zero.*/ -+ -+ return E_OK; -+} -+ -+static t_Error UpdateInitCapwapFrag(t_Handle h_FmPcd, t_Handle h_PcdParams, -+ t_Handle h_FmPort, t_FmPcdManip *p_Manip, -+ t_Handle h_Ad, bool validate) -+{ -+ t_FmPortGetSetCcParams fmPortGetSetCcParams; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Manip->opcode == HMAN_OC_CAPWAP_FRAGMENTATION), -+ E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(h_FmPort, E_INVALID_HANDLE); -+ -+ UNUSED(h_FmPcd); -+ UNUSED(h_Ad); -+ UNUSED(h_PcdParams); -+ UNUSED(validate); -+ UNUSED(p_Manip); -+ -+ fmPortGetSetCcParams.setCcParams.type = 0; -+ fmPortGetSetCcParams.getCcParams.type = MANIP_EXTRA_SPACE; -+ if ((err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (!fmPortGetSetCcParams.getCcParams.internalBufferOffset) -+ DBG(WARNING, ("manipExtraSpace must be larger than '0'")); -+ -+ return E_OK; -+} -+ -+static t_Error CapwapManip(t_FmPcdManipParams *p_ManipParams, -+ t_FmPcdManip *p_Manip) -+{ -+ t_AdOfTypeContLookup *p_Ad; -+ t_FmPcdManipSpecialOffloadCapwapParams *p_Params; -+ t_Error err = E_OK; -+ uint32_t tmpReg32 = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_ManipParams, E_INVALID_HANDLE); -+ -+ p_Params = &p_ManipParams->u.specialOffload.u.capwap; -+ -+ p_Ad = (t_AdOfTypeContLookup *)p_Manip->h_Ad; -+ tmpReg32 |= FM_PCD_AD_CONT_LOOKUP_TYPE; -+ tmpReg32 |= (p_Params->dtls) ? FM_PCD_MANIP_CAPWAP_DTLS : 0; -+ /* TODO - add 'qosSrc' */ -+ WRITE_UINT32(p_Ad->ccAdBase, tmpReg32); -+ -+ tmpReg32 = HMAN_OC_CAPWAP_MANIP; -+ if (p_ManipParams->h_NextManip) -+ { -+ WRITE_UINT32( -+ p_Ad->matchTblPtr, -+ (uint32_t)(XX_VirtToPhys(((t_FmPcdManip *)p_ManipParams->h_NextManip)->h_Ad)- (((t_FmPcd *)p_Manip->h_FmPcd)->physicalMuramBase)) >> 4); -+ -+ tmpReg32 |= FM_PCD_MANIP_CAPWAP_NADEN; -+ } -+ -+ WRITE_UINT32(p_Ad->pcAndOffsets, tmpReg32); -+ -+ return err; -+} -+#endif /* (DPAA_VERSION >= 11) */ -+ -+static t_Handle ManipOrStatsSetNode(t_Handle h_FmPcd, t_Handle *p_Params, -+ bool stats) -+{ -+ t_FmPcdManip *p_Manip; -+ t_Error err; -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ -+ p_Manip = (t_FmPcdManip*)XX_Malloc(sizeof(t_FmPcdManip)); -+ if (!p_Manip) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("No memory")); -+ return NULL; -+ } -+ memset(p_Manip, 0, sizeof(t_FmPcdManip)); -+ -+ p_Manip->type = ((t_FmPcdManipParams *)p_Params)->type; -+ memcpy((uint8_t*)&p_Manip->manipParams, p_Params, -+ sizeof(p_Manip->manipParams)); -+ -+ if (!stats) -+ err = CheckManipParamsAndSetType(p_Manip, -+ (t_FmPcdManipParams *)p_Params); -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ else -+ err = CheckStatsParamsAndSetType(p_Manip, (t_FmPcdStatsParams *)p_Params); -+#else /* not (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ else -+ { -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Statistics node!")); -+ XX_Free(p_Manip); -+ return NULL; -+ } -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ if (err) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Invalid header manipulation type")); -+ XX_Free(p_Manip); -+ return NULL; -+ } -+ -+ if ((p_Manip->opcode != HMAN_OC_IP_REASSEMBLY) && (p_Manip->opcode != HMAN_OC_CAPWAP_REASSEMBLY)) -+ { -+ /* In Case of reassembly manipulation the reassembly action descriptor will -+ be defines later on */ -+ if (p_Manip->muramAllocate) -+ { -+ p_Manip->h_Ad = (t_Handle)FM_MURAM_AllocMem( -+ p_FmPcd->h_FmMuram, FM_PCD_CC_AD_ENTRY_SIZE, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_Manip->h_Ad) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("MURAM alloc for Manipulation action descriptor")); -+ ReleaseManipHandler(p_Manip, p_FmPcd); -+ XX_Free(p_Manip); -+ return NULL; -+ } -+ -+ MemSet8(p_Manip->h_Ad, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ } -+ else -+ { -+ p_Manip->h_Ad = (t_Handle)XX_Malloc( -+ FM_PCD_CC_AD_ENTRY_SIZE * sizeof(uint8_t)); -+ if (!p_Manip->h_Ad) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Allocation of Manipulation action descriptor")); -+ ReleaseManipHandler(p_Manip, p_FmPcd); -+ XX_Free(p_Manip); -+ return NULL; -+ } -+ -+ memset(p_Manip->h_Ad, 0, FM_PCD_CC_AD_ENTRY_SIZE * sizeof(uint8_t)); -+ } -+ } -+ -+ p_Manip->h_FmPcd = h_FmPcd; -+ -+ return p_Manip; -+} -+ -+static void UpdateAdPtrOfNodesWhichPointsOnCrntMdfManip( -+ t_FmPcdManip *p_CrntMdfManip, t_List *h_NodesLst) -+{ -+ t_CcNodeInformation *p_CcNodeInformation; -+ t_FmPcdCcNode *p_NodePtrOnCurrentMdfManip = NULL; -+ t_List *p_Pos; -+ int i = 0; -+ t_Handle p_AdTablePtOnCrntCurrentMdfNode/*, p_AdTableNewModified*/; -+ t_CcNodeInformation ccNodeInfo; -+ -+ LIST_FOR_EACH(p_Pos, &p_CrntMdfManip->nodesLst) -+ { -+ p_CcNodeInformation = CC_NODE_F_OBJECT(p_Pos); -+ p_NodePtrOnCurrentMdfManip = -+ (t_FmPcdCcNode *)p_CcNodeInformation->h_CcNode; -+ -+ ASSERT_COND(p_NodePtrOnCurrentMdfManip); -+ -+ /* Search in the previous node which exact index points on this current modified node for getting AD */ -+ for (i = 0; i < p_NodePtrOnCurrentMdfManip->numOfKeys + 1; i++) -+ { -+ if (p_NodePtrOnCurrentMdfManip->keyAndNextEngineParams[i].nextEngineParams.nextEngine -+ == e_FM_PCD_CC) -+ { -+ if (p_NodePtrOnCurrentMdfManip->keyAndNextEngineParams[i].nextEngineParams.h_Manip -+ == (t_Handle)p_CrntMdfManip) -+ { -+ if (p_NodePtrOnCurrentMdfManip->keyAndNextEngineParams[i].p_StatsObj) -+ p_AdTablePtOnCrntCurrentMdfNode = -+ p_NodePtrOnCurrentMdfManip->keyAndNextEngineParams[i].p_StatsObj->h_StatsAd; -+ else -+ p_AdTablePtOnCrntCurrentMdfNode = -+ PTR_MOVE(p_NodePtrOnCurrentMdfManip->h_AdTable, i*FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ memset(&ccNodeInfo, 0, sizeof(t_CcNodeInformation)); -+ ccNodeInfo.h_CcNode = p_AdTablePtOnCrntCurrentMdfNode; -+ EnqueueNodeInfoToRelevantLst(h_NodesLst, &ccNodeInfo, NULL); -+ } -+ } -+ } -+ -+ ASSERT_COND(i != p_NodePtrOnCurrentMdfManip->numOfKeys); -+ } -+} -+ -+static void BuildHmtd(uint8_t *p_Dest, uint8_t *p_Src, uint8_t *p_Hmcd, -+ t_FmPcd *p_FmPcd) -+{ -+ t_Error err; -+ -+ /* Copy the HMTD */ -+ MemCpy8(p_Dest, (uint8_t*)p_Src, 16); -+ /* Replace the HMCT table pointer */ -+ WRITE_UINT32( -+ ((t_Hmtd *)p_Dest)->hmcdBasePtr, -+ (uint32_t)(XX_VirtToPhys(p_Hmcd) - ((t_FmPcd*)p_FmPcd)->physicalMuramBase)); -+ /* Call Host Command to replace HMTD by a new HMTD */ -+ err = FmHcPcdCcDoDynamicChange( -+ p_FmPcd->h_Hc, -+ (uint32_t)(XX_VirtToPhys(p_Src) - p_FmPcd->physicalMuramBase), -+ (uint32_t)(XX_VirtToPhys(p_Dest) - p_FmPcd->physicalMuramBase)); -+ if (err) -+ REPORT_ERROR(MINOR, err, ("Failed in dynamic manip change, continued to the rest of the owners.")); -+} -+ -+static t_Error FmPcdManipInitUpdate(t_Handle h_FmPcd, t_Handle h_PcdParams, -+ t_Handle h_FmPort, t_Handle h_Manip, -+ t_Handle h_Ad, bool validate, int level, -+ t_Handle h_FmTree) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_Manip; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(h_Manip, E_INVALID_HANDLE); -+ -+ UNUSED(level); -+ UNUSED(h_FmTree); -+ -+ switch (p_Manip->opcode) -+ { -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ case (HMAN_OC_MV_INT_FRAME_HDR_FROM_FRM_TO_BUFFER_PREFFIX): -+ err = UpdateInitMvIntFrameHeaderFromFrameToBufferPrefix(h_FmPort, -+ p_Manip, -+ h_Ad, -+ validate); -+ break; -+ case (HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER): -+ if (!p_Manip->h_Frag) -+ break; -+ case (HMAN_OC_CAPWAP_FRAGMENTATION): -+ err = UpdateInitCapwapFragmentation(h_FmPort, p_Manip, h_Ad, validate, h_FmTree); -+ break; -+ case (HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST): -+ if (p_Manip->h_Frag) -+ err = UpdateInitCapwapReasm(h_FmPcd, h_FmPort, p_Manip, h_Ad, validate); -+ break; -+ case (HMAN_OC_CAPWAP_INDEXED_STATS): -+ err = UpdateIndxStats(h_FmPcd, h_FmPort, p_Manip); -+ break; -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ case (HMAN_OC_IP_REASSEMBLY): -+ err = UpdateInitReasm(h_FmPcd, h_PcdParams, h_FmPort, p_Manip, h_Ad, -+ validate); -+ break; -+ case (HMAN_OC_IP_FRAGMENTATION): -+ err = UpdateInitIpFrag(h_FmPcd, h_PcdParams, h_FmPort, p_Manip, -+ h_Ad, validate); -+ break; -+#if (DPAA_VERSION >= 11) -+ case (HMAN_OC_CAPWAP_FRAGMENTATION): -+ err = UpdateInitCapwapFrag(h_FmPcd, h_PcdParams, h_FmPort, p_Manip, -+ h_Ad, validate); -+ break; -+ case (HMAN_OC_CAPWAP_REASSEMBLY): -+ err = UpdateInitReasm(h_FmPcd, h_PcdParams, h_FmPort, p_Manip, h_Ad, -+ validate); -+ break; -+#endif /* (DPAA_VERSION >= 11) */ -+ default: -+ return E_OK; -+ } -+ -+ return err; -+} -+ -+static t_Error FmPcdManipModifyUpdate(t_Handle h_Manip, t_Handle h_Ad, -+ bool validate, int level, -+ t_Handle h_FmTree) -+{ -+ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_Manip; -+ t_Error err = E_OK; -+ -+ UNUSED(level); -+ -+ switch (p_Manip->opcode) -+ { -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ case (HMAN_OC_MV_INT_FRAME_HDR_FROM_FRM_TO_BUFFER_PREFFIX): -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("modify node with this type of manipulation is not suppported")); -+ case (HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST): -+ -+ if (p_Manip->h_Frag) -+ { -+ if (!(p_Manip->shadowUpdateParams & NUM_OF_TASKS) -+ && !(p_Manip->shadowUpdateParams & OFFSET_OF_DATA) -+ && !(p_Manip->shadowUpdateParams & OFFSET_OF_PR)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("modify node with this type of manipulation requires manipulation be updated previously in SetPcd function")); -+ } -+ break; -+ case (HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER): -+ if (p_Manip->h_Frag) -+ err = UpdateModifyCapwapFragmenation(p_Manip, h_Ad, validate, h_FmTree); -+ break; -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ default: -+ return E_OK; -+ } -+ -+ return err; -+} -+ -+/*****************************************************************************/ -+/* Inter-module API routines */ -+/*****************************************************************************/ -+ -+t_Error FmPcdManipUpdate(t_Handle h_FmPcd, t_Handle h_PcdParams, -+ t_Handle h_FmPort, t_Handle h_Manip, t_Handle h_Ad, -+ bool validate, int level, t_Handle h_FmTree, -+ bool modify) -+{ -+ t_Error err; -+ -+ if (!modify) -+ err = FmPcdManipInitUpdate(h_FmPcd, h_PcdParams, h_FmPort, h_Manip, -+ h_Ad, validate, level, h_FmTree); -+ else -+ err = FmPcdManipModifyUpdate(h_Manip, h_Ad, validate, level, h_FmTree); -+ -+ return err; -+} -+ -+void FmPcdManipUpdateOwner(t_Handle h_Manip, bool add) -+{ -+ -+ uint32_t intFlags; -+ -+ intFlags = XX_LockIntrSpinlock(((t_FmPcdManip *)h_Manip)->h_Spinlock); -+ if (add) -+ ((t_FmPcdManip *)h_Manip)->owner++; -+ else -+ { -+ ASSERT_COND(((t_FmPcdManip *)h_Manip)->owner); -+ ((t_FmPcdManip *)h_Manip)->owner--; -+ } -+ XX_UnlockIntrSpinlock(((t_FmPcdManip *)h_Manip)->h_Spinlock, intFlags); -+} -+ -+t_List *FmPcdManipGetNodeLstPointedOnThisManip(t_Handle h_Manip) -+{ -+ ASSERT_COND(h_Manip); -+ return &((t_FmPcdManip *)h_Manip)->nodesLst; -+} -+ -+t_List *FmPcdManipGetSpinlock(t_Handle h_Manip) -+{ -+ ASSERT_COND(h_Manip); -+ return ((t_FmPcdManip *)h_Manip)->h_Spinlock; -+} -+ -+t_Error FmPcdManipCheckParamsForCcNextEngine( -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams, -+ uint32_t *requiredAction) -+{ -+ t_FmPcdManip *p_Manip; -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ t_Error err = E_OK; -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10))*/ -+ bool pointFromCc = TRUE; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcdCcNextEngineParams, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcdCcNextEngineParams->h_Manip, -+ E_NULL_POINTER); -+ -+ p_Manip = (t_FmPcdManip *)(p_FmPcdCcNextEngineParams->h_Manip); -+ *requiredAction = 0; -+ -+ while (p_Manip) -+ { -+ switch (p_Manip->opcode) -+ { -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ case (HMAN_OC_CAPWAP_INDEXED_STATS): -+ if (p_FmPcdCcNextEngineParams->nextEngine != e_FM_PCD_DONE) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("For this type of header manipulation has to be nextEngine e_FM_PCD_DONE")); -+ if (p_FmPcdCcNextEngineParams->params.enqueueParams.overrideFqid) -+ p_Manip->cnia = TRUE; -+ case (HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST): -+ *requiredAction = UPDATE_NIA_ENQ_WITHOUT_DMA; -+ case (HMAN_OC_RMV_N_OR_INSRT_INT_FRM_HDR): -+ p_Manip->ownerTmp++; -+ break; -+ case (HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER): -+ if ((p_FmPcdCcNextEngineParams->nextEngine != e_FM_PCD_DONE) -+ && !p_FmPcdCcNextEngineParams->params.enqueueParams.overrideFqid) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("For this type of header manipulation has to be nextEngine e_FM_PCD_DONE with fqidForCtrlFlow FALSE")); -+ p_Manip->ownerTmp++; -+ break; -+ case (HMAN_OC_MV_INT_FRAME_HDR_FROM_FRM_TO_BUFFER_PREFFIX): -+ if ((p_FmPcdCcNextEngineParams->nextEngine != e_FM_PCD_CC) -+ && (FmPcdCcGetParseCode(p_FmPcdCcNextEngineParams->params.ccParams.h_CcNode) -+ != CC_PC_GENERIC_IC_HASH_INDEXED)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("For this type of header manipulation next engine has to be CC and action = e_FM_PCD_ACTION_INDEXED_LOOKUP")); -+ err = UpdateManipIc(p_FmPcdCcNextEngineParams->h_Manip, -+ FmPcdCcGetOffset(p_FmPcdCcNextEngineParams->params.ccParams.h_CcNode)); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ *requiredAction = UPDATE_NIA_ENQ_WITHOUT_DMA; -+ break; -+ #endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ case (HMAN_OC_IP_FRAGMENTATION): -+ case (HMAN_OC_IP_REASSEMBLY): -+#if (DPAA_VERSION >= 11) -+ case (HMAN_OC_CAPWAP_REASSEMBLY): -+ case (HMAN_OC_CAPWAP_FRAGMENTATION): -+#endif /* (DPAA_VERSION >= 11) */ -+ if (p_FmPcdCcNextEngineParams->nextEngine != e_FM_PCD_DONE) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("For this type of header manipulation has to be nextEngine e_FM_PCD_DONE")); -+ p_Manip->ownerTmp++; -+ break; -+ case (HMAN_OC_IPSEC_MANIP): -+#if (DPAA_VERSION >= 11) -+ case (HMAN_OC_CAPWAP_MANIP): -+#endif /* (DPAA_VERSION >= 11) */ -+ p_Manip->ownerTmp++; -+ break; -+ case (HMAN_OC): -+ if ((p_FmPcdCcNextEngineParams->nextEngine == e_FM_PCD_CC) -+ && MANIP_IS_CASCADED(p_Manip)) -+ RETURN_ERROR( -+ MINOR, -+ E_INVALID_STATE, -+ ("Can't have a cascaded manipulation when and Next Engine is CC")); -+ if (!MANIP_IS_FIRST(p_Manip) && pointFromCc) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("h_Manip is already used and may not be shared (no sharing of non-head manip nodes)")); -+ break; -+ default: -+ RETURN_ERROR( -+ MAJOR, E_INVALID_STATE, -+ ("invalid type of header manipulation for this state")); -+ } -+ p_Manip = p_Manip->h_NextManip; -+ pointFromCc = FALSE; -+ } -+ return E_OK; -+} -+ -+ -+t_Error FmPcdManipCheckParamsWithCcNodeParams(t_Handle h_Manip, -+ t_Handle h_FmPcdCcNode) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_Manip; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(h_Manip, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(h_FmPcdCcNode, E_INVALID_HANDLE); -+ -+ switch (p_Manip->opcode) -+ { -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ case (HMAN_OC_CAPWAP_INDEXED_STATS): -+ if (p_Manip->ownerTmp != FmPcdCcGetNumOfKeys(h_FmPcdCcNode)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("The manipulation of the type statistics flowId if exist has to be pointed by all numOfKeys")); -+ break; -+ case (HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST): -+ if (p_Manip->h_Frag) -+ { -+ if (p_Manip->ownerTmp != FmPcdCcGetNumOfKeys(h_FmPcdCcNode)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("The manipulation of the type remove DTLS if exist has to be pointed by all numOfKeys")); -+ err = UpdateManipIc(h_Manip, FmPcdCcGetOffset(h_FmPcdCcNode)); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ break; -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ default: -+ break; -+ } -+ -+ return err; -+} -+ -+void FmPcdManipUpdateAdResultForCc( -+ t_Handle h_Manip, t_FmPcdCcNextEngineParams *p_CcNextEngineParams, -+ t_Handle p_Ad, t_Handle *p_AdNewPtr) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_Manip; -+ -+ /* This routine creates a Manip AD and can return in "p_AdNewPtr" -+ * either the new descriptor or NULL if it writes the Manip AD into p_AD (into the match table) */ -+ -+ ASSERT_COND(p_Manip); -+ ASSERT_COND(p_CcNextEngineParams); -+ ASSERT_COND(p_Ad); -+ ASSERT_COND(p_AdNewPtr); -+ -+ FmPcdManipUpdateOwner(h_Manip, TRUE); -+ -+ /* According to "type", either build & initialize a new AD (p_AdNew) or initialize -+ * p_Ad ( the AD in the match table) and set p_AdNew = NULL. */ -+ switch (p_Manip->opcode) -+ { -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ case (HMAN_OC_RMV_N_OR_INSRT_INT_FRM_HDR): -+ case (HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST): -+ case (HMAN_OC_CAPWAP_INDEXED_STATS): -+ *p_AdNewPtr = p_Manip->h_Ad; -+ break; -+ case (HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER): -+ case (HMAN_OC_CAPWAP_FRAGMENTATION): -+ WRITE_UINT32(((t_AdOfTypeResult *)p_Ad)->fqid, -+ ((t_AdOfTypeResult *)(p_Manip->h_Ad))->fqid); -+ WRITE_UINT32(((t_AdOfTypeResult *)p_Ad)->plcrProfile, -+ ((t_AdOfTypeResult *)(p_Manip->h_Ad))->plcrProfile); -+ WRITE_UINT32(((t_AdOfTypeResult *)p_Ad)->nia, -+ ((t_AdOfTypeResult *)(p_Manip->h_Ad))->nia); -+ *p_AdNewPtr = NULL; -+ break; -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ case (HMAN_OC_IPSEC_MANIP): -+#if (DPAA_VERSION >= 11) -+ case (HMAN_OC_CAPWAP_MANIP): -+#endif /* (DPAA_VERSION >= 11) */ -+ *p_AdNewPtr = p_Manip->h_Ad; -+ break; -+ case (HMAN_OC_IP_FRAGMENTATION): -+#if (DPAA_VERSION >= 11) -+ case (HMAN_OC_CAPWAP_FRAGMENTATION): -+#endif /* (DPAA_VERSION >= 11) */ -+ if ((p_CcNextEngineParams->nextEngine == e_FM_PCD_DONE) -+ && (!p_CcNextEngineParams->params.enqueueParams.overrideFqid)) -+ { -+ memcpy((uint8_t *)p_Ad, (uint8_t *)p_Manip->h_Ad, -+ sizeof(t_AdOfTypeContLookup)); -+#if (DPAA_VERSION >= 11) -+ WRITE_UINT32( -+ ((t_AdOfTypeContLookup *)p_Ad)->ccAdBase, -+ GET_UINT32(((t_AdOfTypeContLookup *)p_Ad)->ccAdBase) & ~FM_PCD_MANIP_IP_CNIA); -+#endif /* (DPAA_VERSION >= 11) */ -+ *p_AdNewPtr = NULL; -+ } -+ else -+ *p_AdNewPtr = p_Manip->h_Ad; -+ break; -+ case (HMAN_OC_IP_REASSEMBLY): -+ if (FmPcdManipIpReassmIsIpv6Hdr(p_Manip)) -+ { -+ if (!p_Manip->reassmParams.ip.ipv6Assigned) -+ { -+ *p_AdNewPtr = p_Manip->reassmParams.ip.h_Ipv6Ad; -+ p_Manip->reassmParams.ip.ipv6Assigned = TRUE; -+ FmPcdManipUpdateOwner(h_Manip, FALSE); -+ } -+ else -+ { -+ *p_AdNewPtr = p_Manip->reassmParams.ip.h_Ipv4Ad; -+ p_Manip->reassmParams.ip.ipv6Assigned = FALSE; -+ } -+ } -+ else -+ *p_AdNewPtr = p_Manip->reassmParams.ip.h_Ipv4Ad; -+ memcpy((uint8_t *)p_Ad, (uint8_t *)*p_AdNewPtr, -+ sizeof(t_AdOfTypeContLookup)); -+ *p_AdNewPtr = NULL; -+ break; -+#if (DPAA_VERSION >= 11) -+ case (HMAN_OC_CAPWAP_REASSEMBLY): -+ *p_AdNewPtr = p_Manip->reassmParams.capwap.h_Ad; -+ memcpy((uint8_t *)p_Ad, (uint8_t *)*p_AdNewPtr, -+ sizeof(t_AdOfTypeContLookup)); -+ *p_AdNewPtr = NULL; -+ break; -+#endif /* (DPAA_VERSION >= 11) */ -+ case (HMAN_OC): -+ /* Allocate and initialize HMTD */ -+ *p_AdNewPtr = p_Manip->h_Ad; -+ break; -+ default: -+ break; -+ } -+} -+ -+void FmPcdManipUpdateAdContLookupForCc(t_Handle h_Manip, t_Handle p_Ad, -+ t_Handle *p_AdNewPtr, -+ uint32_t adTableOffset) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_Manip; -+ -+ /* This routine creates a Manip AD and can return in "p_AdNewPtr" -+ * either the new descriptor or NULL if it writes the Manip AD into p_AD (into the match table) */ -+ ASSERT_COND(p_Manip); -+ -+ FmPcdManipUpdateOwner(h_Manip, TRUE); -+ -+ switch (p_Manip->opcode) -+ { -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ case (HMAN_OC_MV_INT_FRAME_HDR_FROM_FRM_TO_BUFFER_PREFFIX): -+ WRITE_UINT32(((t_AdOfTypeContLookup *)p_Ad)->ccAdBase, -+ ((t_AdOfTypeContLookup *)(p_Manip->h_Ad))->ccAdBase); -+ WRITE_UINT32( -+ ((t_AdOfTypeContLookup *)p_Ad)->matchTblPtr, -+ ((t_AdOfTypeContLookup *)(p_Manip->h_Ad))->matchTblPtr); -+ WRITE_UINT32( -+ ((t_AdOfTypeContLookup *)p_Ad)->pcAndOffsets, -+ ((t_AdOfTypeContLookup *)(p_Manip->h_Ad))->pcAndOffsets); -+ WRITE_UINT32(((t_AdOfTypeContLookup *)p_Ad)->gmask, -+ ((t_AdOfTypeContLookup *)(p_Manip->h_Ad))->gmask); -+ WRITE_UINT32( -+ ((t_AdOfTypeContLookup *)p_Ad)->ccAdBase, -+ (GET_UINT32(((t_AdOfTypeContLookup *)p_Ad)->ccAdBase) | adTableOffset)); -+ *p_AdNewPtr = NULL; -+ break; -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ case (HMAN_OC): -+ /* Initialize HMTD within the match table*/ -+ MemSet8(p_Ad, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ /* copy the existing HMTD *//* ask Alla - memcpy??? */ -+ memcpy((uint8_t*)p_Ad, p_Manip->h_Ad, sizeof(t_Hmtd)); -+ /* update NADEN to be "1"*/ -+ WRITE_UINT16( -+ ((t_Hmtd *)p_Ad)->cfg, -+ (uint16_t)(GET_UINT16(((t_Hmtd *)p_Ad)->cfg) | HMTD_CFG_NEXT_AD_EN)); -+ /* update next action descriptor */ -+ WRITE_UINT16(((t_Hmtd *)p_Ad)->nextAdIdx, -+ (uint16_t)(adTableOffset >> 4)); -+ /* mark that Manip's HMTD is not used */ -+ *p_AdNewPtr = NULL; -+ break; -+ -+ default: -+ break; -+ } -+} -+ -+t_Error FmPcdManipBuildIpReassmScheme(t_FmPcd *p_FmPcd, t_Handle h_NetEnv, -+ t_Handle h_CcTree, t_Handle h_Manip, -+ bool isIpv4, uint8_t groupId) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_Manip; -+ t_FmPcdKgSchemeParams *p_SchemeParams = NULL; -+ t_Handle h_Scheme; -+ -+ ASSERT_COND(p_FmPcd); -+ ASSERT_COND(h_NetEnv); -+ ASSERT_COND(p_Manip); -+ -+ /* scheme was already build, no need to check for IPv6 */ -+ if (p_Manip->reassmParams.ip.h_Ipv4Scheme) -+ return E_OK; -+ -+ if (isIpv4) { -+ h_Scheme = FmPcdKgGetSchemeHandle(p_FmPcd, p_Manip->reassmParams.ip.relativeSchemeId[0]); -+ if (h_Scheme) { -+ /* scheme was found */ -+ p_Manip->reassmParams.ip.h_Ipv4Scheme = h_Scheme; -+ return E_OK; -+ } -+ } else { -+ h_Scheme = FmPcdKgGetSchemeHandle(p_FmPcd, p_Manip->reassmParams.ip.relativeSchemeId[1]); -+ if (h_Scheme) { -+ /* scheme was found */ -+ p_Manip->reassmParams.ip.h_Ipv6Scheme = h_Scheme; -+ return E_OK; -+ } -+ } -+ -+ p_SchemeParams = XX_Malloc(sizeof(t_FmPcdKgSchemeParams)); -+ if (!p_SchemeParams) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("Memory allocation failed for scheme")); -+ -+ /* Configures the IPv4 or IPv6 scheme*/ -+ memset(p_SchemeParams, 0, sizeof(t_FmPcdKgSchemeParams)); -+ p_SchemeParams->netEnvParams.h_NetEnv = h_NetEnv; -+ p_SchemeParams->id.relativeSchemeId = (uint8_t)( -+ (isIpv4 == TRUE) ? p_Manip->reassmParams.ip.relativeSchemeId[0] : -+ p_Manip->reassmParams.ip.relativeSchemeId[1]); -+ p_SchemeParams->schemeCounter.update = TRUE; -+#if (DPAA_VERSION >= 11) -+ p_SchemeParams->alwaysDirect = TRUE; -+ p_SchemeParams->bypassFqidGeneration = TRUE; -+#else -+ p_SchemeParams->keyExtractAndHashParams.hashDistributionNumOfFqids = 1; -+ p_SchemeParams->baseFqid = 0xFFFFFF; /*TODO- baseFqid*/ -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ setIpReassmSchemeParams(p_FmPcd, p_SchemeParams, h_CcTree, isIpv4, groupId); -+ -+ /* Sets the new scheme */ -+ if (isIpv4) -+ p_Manip->reassmParams.ip.h_Ipv4Scheme = FM_PCD_KgSchemeSet( -+ p_FmPcd, p_SchemeParams); -+ else -+ p_Manip->reassmParams.ip.h_Ipv6Scheme = FM_PCD_KgSchemeSet( -+ p_FmPcd, p_SchemeParams); -+ -+ XX_Free(p_SchemeParams); -+ -+ return E_OK; -+} -+ -+t_Error FmPcdManipDeleteIpReassmSchemes(t_Handle h_Manip) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_Manip; -+ -+ ASSERT_COND(p_Manip); -+ -+ if ((p_Manip->reassmParams.ip.h_Ipv4Scheme) && -+ !FmPcdKgIsSchemeHasOwners(p_Manip->reassmParams.ip.h_Ipv4Scheme)) -+ FM_PCD_KgSchemeDelete(p_Manip->reassmParams.ip.h_Ipv4Scheme); -+ -+ if ((p_Manip->reassmParams.ip.h_Ipv6Scheme) && -+ !FmPcdKgIsSchemeHasOwners(p_Manip->reassmParams.ip.h_Ipv6Scheme)) -+ FM_PCD_KgSchemeDelete(p_Manip->reassmParams.ip.h_Ipv6Scheme); -+ -+ return E_OK; -+} -+ -+bool FmPcdManipIpReassmIsIpv6Hdr(t_Handle h_Manip) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_Manip; -+ -+ ASSERT_COND(p_Manip); -+ -+ return (p_Manip->reassmParams.hdr == HEADER_TYPE_IPv6); -+} -+ -+t_Error FmPcdManipBuildCapwapReassmScheme(t_FmPcd *p_FmPcd, t_Handle h_NetEnv, -+ t_Handle h_CcTree, t_Handle h_Manip, -+ uint8_t groupId) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_Manip; -+ t_FmPcdKgSchemeParams *p_SchemeParams = NULL; -+ -+ ASSERT_COND(p_FmPcd); -+ ASSERT_COND(h_NetEnv); -+ ASSERT_COND(p_Manip); -+ -+ /* scheme was already build, no need to check for IPv6 */ -+ if (p_Manip->reassmParams.capwap.h_Scheme) -+ return E_OK; -+ -+ p_SchemeParams = XX_Malloc(sizeof(t_FmPcdKgSchemeParams)); -+ if (!p_SchemeParams) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, -+ ("Memory allocation failed for scheme")); -+ -+ memset(p_SchemeParams, 0, sizeof(t_FmPcdKgSchemeParams)); -+ p_SchemeParams->netEnvParams.h_NetEnv = h_NetEnv; -+ p_SchemeParams->id.relativeSchemeId = -+ (uint8_t)p_Manip->reassmParams.capwap.relativeSchemeId; -+ p_SchemeParams->schemeCounter.update = TRUE; -+ p_SchemeParams->bypassFqidGeneration = TRUE; -+ -+ setCapwapReassmSchemeParams(p_FmPcd, p_SchemeParams, h_CcTree, groupId); -+ -+ p_Manip->reassmParams.capwap.h_Scheme = FM_PCD_KgSchemeSet(p_FmPcd, -+ p_SchemeParams); -+ -+ XX_Free(p_SchemeParams); -+ -+ return E_OK; -+} -+ -+t_Error FmPcdManipDeleteCapwapReassmSchemes(t_Handle h_Manip) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_Manip; -+ -+ ASSERT_COND(p_Manip); -+ -+ if (p_Manip->reassmParams.capwap.h_Scheme) -+ FM_PCD_KgSchemeDelete(p_Manip->reassmParams.capwap.h_Scheme); -+ -+ return E_OK; -+} -+ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+t_Handle FmPcdManipApplSpecificBuild(void) -+{ -+ t_FmPcdManip *p_Manip; -+ -+ p_Manip = (t_FmPcdManip*)XX_Malloc(sizeof(t_FmPcdManip)); -+ if (!p_Manip) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("No memory")); -+ return NULL; -+ } -+ memset(p_Manip, 0, sizeof(t_FmPcdManip)); -+ -+ p_Manip->opcode = HMAN_OC_MV_INT_FRAME_HDR_FROM_FRM_TO_BUFFER_PREFFIX; -+ p_Manip->muramAllocate = FALSE; -+ -+ p_Manip->h_Ad = (t_Handle)XX_Malloc(FM_PCD_CC_AD_ENTRY_SIZE * sizeof(uint8_t)); -+ if (!p_Manip->h_Ad) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Allocation of Manipulation action descriptor")); -+ XX_Free(p_Manip); -+ return NULL; -+ } -+ -+ memset(p_Manip->h_Ad, 0, FM_PCD_CC_AD_ENTRY_SIZE * sizeof(uint8_t)); -+ -+ /*treatFdStatusFieldsAsErrors = TRUE hardcoded - assumption its always come after CAAM*/ -+ /*Application specific = type of flowId index, move internal frame header from data to IC, -+ SEC errors check*/ -+ if (MvIntFrameHeaderFromFrameToBufferPrefix(p_Manip, TRUE)!= E_OK) -+ { -+ XX_Free(p_Manip->h_Ad); -+ XX_Free(p_Manip); -+ return NULL; -+ } -+ return p_Manip; -+} -+ -+bool FmPcdManipIsCapwapApplSpecific(t_Handle h_Manip) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_Manip; -+ ASSERT_COND(h_Manip); -+ -+ return (bool)((p_Manip->opcode == HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST) ? TRUE : FALSE); -+} -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+/*********************** End of inter-module routines ************************/ -+ -+/****************************************/ -+/* API Init unit functions */ -+/****************************************/ -+ -+t_Handle FM_PCD_ManipNodeSet(t_Handle h_FmPcd, -+ t_FmPcdManipParams *p_ManipParams) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ t_FmPcdManip *p_Manip; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(p_ManipParams, E_INVALID_HANDLE, NULL); -+ -+ p_Manip = ManipOrStatsSetNode(h_FmPcd, (t_Handle)p_ManipParams, FALSE); -+ if (!p_Manip) -+ return NULL; -+ -+ if (((p_Manip->opcode == HMAN_OC_IP_REASSEMBLY) -+ || (p_Manip->opcode == HMAN_OC_IP_FRAGMENTATION) -+ || (p_Manip->opcode == HMAN_OC) -+ || (p_Manip->opcode == HMAN_OC_IPSEC_MANIP) -+#if (DPAA_VERSION >= 11) -+ || (p_Manip->opcode == HMAN_OC_CAPWAP_MANIP) -+ || (p_Manip->opcode == HMAN_OC_CAPWAP_FRAGMENTATION) -+ || (p_Manip->opcode == HMAN_OC_CAPWAP_REASSEMBLY) -+#endif /* (DPAA_VERSION >= 11) */ -+ ) && (!FmPcdIsAdvancedOffloadSupported(p_FmPcd))) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Advanced-offload must be enabled")); -+ XX_Free(p_Manip); -+ return NULL; -+ } -+ p_Manip->h_Spinlock = XX_InitSpinlock(); -+ if (!p_Manip->h_Spinlock) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("UNSUPPORTED HEADER MANIPULATION TYPE")); -+ ReleaseManipHandler(p_Manip, p_FmPcd); -+ XX_Free(p_Manip); -+ return NULL; -+ }INIT_LIST(&p_Manip->nodesLst); -+ -+ switch (p_Manip->opcode) -+ { -+ case (HMAN_OC_IP_REASSEMBLY): -+ /* IpReassembly */ -+ err = IpReassembly(&p_ManipParams->u.reassem, p_Manip); -+ break; -+ case (HMAN_OC_IP_FRAGMENTATION): -+ /* IpFragmentation */ -+ err = IpFragmentation(&p_ManipParams->u.frag.u.ipFrag, p_Manip); -+ if (err) -+ break; -+ err = IPManip(p_Manip); -+ break; -+ case (HMAN_OC_IPSEC_MANIP): -+ err = IPSecManip(p_ManipParams, p_Manip); -+ break; -+#if (DPAA_VERSION >= 11) -+ case (HMAN_OC_CAPWAP_REASSEMBLY): -+ /* CapwapReassembly */ -+ err = CapwapReassembly(&p_ManipParams->u.reassem, p_Manip); -+ break; -+ case (HMAN_OC_CAPWAP_FRAGMENTATION): -+ /* CapwapFragmentation */ -+ err = CapwapFragmentation(&p_ManipParams->u.frag.u.capwapFrag, -+ p_Manip); -+ break; -+ case (HMAN_OC_CAPWAP_MANIP): -+ err = CapwapManip(p_ManipParams, p_Manip); -+ break; -+#endif /* (DPAA_VERSION >= 11) */ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ case (HMAN_OC_RMV_N_OR_INSRT_INT_FRM_HDR): -+ /* HmanType1 */ -+ err = RmvHdrTillSpecLocNOrInsrtIntFrmHdr(&p_ManipParams->u.hdr.rmvParams, p_Manip); -+ break; -+ case (HMAN_OC_CAPWAP_FRAGMENTATION): -+ err = CapwapFragmentation(&p_ManipParams->fragOrReasmParams.u.capwapFragParams, -+ p_Manip, -+ p_FmPcd, -+ p_ManipParams->fragOrReasmParams.sgBpid); -+ if (err) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("UNSUPPORTED HEADER MANIPULATION TYPE")); -+ ReleaseManipHandler(p_Manip, p_FmPcd); -+ XX_Free(p_Manip); -+ return NULL; -+ } -+ if (p_Manip->insrt) -+ p_Manip->opcode = HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER; -+ case (HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER): -+ /* HmanType2 + if user asked only for fragmentation still need to allocate HmanType2 */ -+ err = InsrtHdrByTempl(&p_ManipParams->u.hdr.insrtParams, p_Manip, p_FmPcd); -+ break; -+ case (HMAN_OC_CAPWAP_REASSEMBLY): -+ err = CapwapReassembly(&p_ManipParams->fragOrReasmParams.u.capwapReasmParams, -+ p_Manip, -+ p_FmPcd, -+ p_ManipParams->fragOrReasmParams.sgBpid); -+ if (err) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("UNSUPPORTED HEADER MANIPULATION TYPE")); -+ ReleaseManipHandler(p_Manip, p_FmPcd); -+ XX_Free(p_Manip); -+ return NULL; -+ } -+ if (p_Manip->rmv) -+ p_Manip->opcode = HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST; -+ case (HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST): -+ /*CAPWAP decapsulation + if user asked only for reassembly still need to allocate CAPWAP decapsulation*/ -+ err = CapwapRmvDtlsHdr(p_FmPcd, p_Manip); -+ break; -+ case (HMAN_OC_MV_INT_FRAME_HDR_FROM_FRM_TO_BUFFER_PREFFIX): -+ /*Application Specific type 1*/ -+ err = MvIntFrameHeaderFromFrameToBufferPrefix(p_Manip, TRUE); -+ break; -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ case (HMAN_OC): -+ /* New Manip */ -+ err = CreateManipActionNew(p_Manip, p_ManipParams); -+ break; -+ default: -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("UNSUPPORTED HEADER MANIPULATION TYPE")); -+ ReleaseManipHandler(p_Manip, p_FmPcd); -+ XX_Free(p_Manip); -+ return NULL; -+ } -+ -+ if (err) -+ { -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ ReleaseManipHandler(p_Manip, p_FmPcd); -+ XX_Free(p_Manip); -+ return NULL; -+ } -+ -+ if (p_ManipParams->h_NextManip) -+ { -+ /* in the check routine we've verified that h_NextManip has no owners -+ * and that only supported types are allowed. */ -+ p_Manip->h_NextManip = p_ManipParams->h_NextManip; -+ /* save a "prev" pointer in h_NextManip */ -+ MANIP_SET_PREV(p_Manip->h_NextManip, p_Manip); -+ FmPcdManipUpdateOwner(p_Manip->h_NextManip, TRUE); -+ } -+ -+ return p_Manip; -+} -+ -+t_Error FM_PCD_ManipNodeReplace(t_Handle h_Manip, -+ t_FmPcdManipParams *p_ManipParams) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_Manip, *p_FirstManip; -+ t_FmPcd *p_FmPcd = (t_FmPcd *)(p_Manip->h_FmPcd); -+ t_Error err; -+ uint8_t *p_WholeHmct = NULL, *p_ShadowHmct = NULL, *p_Hmtd = NULL; -+ t_List lstOfNodeshichPointsOnCrntMdfManip, *p_Pos; -+ t_CcNodeInformation *p_CcNodeInfo; -+ SANITY_CHECK_RETURN_ERROR(h_Manip, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_ManipParams, E_INVALID_HANDLE); -+ -+ INIT_LIST(&lstOfNodeshichPointsOnCrntMdfManip); -+ -+ if ((p_ManipParams->type != e_FM_PCD_MANIP_HDR) -+ || (p_Manip->type != e_FM_PCD_MANIP_HDR)) -+ RETURN_ERROR( -+ MINOR, -+ E_NOT_SUPPORTED, -+ ("FM_PCD_ManipNodeReplace Functionality supported only for Header Manipulation.")); -+ -+ ASSERT_COND(p_Manip->opcode == HMAN_OC); -+ ASSERT_COND(p_Manip->manipParams.h_NextManip == p_Manip->h_NextManip); -+ memcpy((uint8_t*)&p_Manip->manipParams, p_ManipParams, -+ sizeof(p_Manip->manipParams)); -+ p_Manip->manipParams.h_NextManip = p_Manip->h_NextManip; -+ -+ /* The replacement of the HdrManip depends on the node type.*/ -+ /* -+ * (1) If this is an independent node, all its owners should be updated. -+ * -+ * (2) If it is the head of a cascaded chain (it does not have a "prev" but -+ * it has a "next" and it has a "cascaded" indication), the next -+ * node remains unchanged, and the behavior is as in (1). -+ * -+ * (3) If it is not the head, but a part of a cascaded chain, in can be -+ * also replaced as a regular node with just one owner. -+ * -+ * (4) If it is a part of a chain implemented as a unified table, the -+ * whole table is replaced and the owners of the head node must be updated. -+ * -+ */ -+ /* lock shadow */ -+ if (!p_FmPcd->p_CcShadow) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("CC Shadow not allocated")); -+ -+ if (!TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock)) -+ return ERROR_CODE(E_BUSY); -+ -+ /* this routine creates a new manip action in the CC Shadow. */ -+ err = CreateManipActionShadow(p_Manip, p_ManipParams); -+ if (err) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ /* If the owners list is empty (these are NOT the "owners" counter, but pointers from CC) -+ * replace only HMTD and no lcok is required. Otherwise -+ * lock the whole PCD -+ * In case 4 MANIP_IS_UNIFIED_NON_FIRST(p_Manip) - Use the head node instead. */ -+ if (!FmPcdLockTryLockAll(p_FmPcd)) -+ { -+ DBG(TRACE, ("FmPcdLockTryLockAll failed")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ p_ShadowHmct = (uint8_t*)PTR_MOVE(p_FmPcd->p_CcShadow, 16); -+ -+ p_FirstManip = (t_FmPcdManip*)GetManipInfo(p_Manip, -+ e_MANIP_HANDLER_TABLE_OWNER); -+ ASSERT_COND(p_FirstManip); -+ -+ if (!LIST_IsEmpty(&p_FirstManip->nodesLst)) -+ UpdateAdPtrOfNodesWhichPointsOnCrntMdfManip( -+ p_FirstManip, &lstOfNodeshichPointsOnCrntMdfManip); -+ -+ p_Hmtd = (uint8_t *)GetManipInfo(p_Manip, e_MANIP_HMTD); -+ ASSERT_COND(p_Hmtd); -+ BuildHmtd(p_FmPcd->p_CcShadow, (uint8_t *)p_Hmtd, p_ShadowHmct, -+ ((t_FmPcd*)(p_Manip->h_FmPcd))); -+ -+ LIST_FOR_EACH(p_Pos, &lstOfNodeshichPointsOnCrntMdfManip) -+ { -+ p_CcNodeInfo = CC_NODE_F_OBJECT(p_Pos); -+ BuildHmtd(p_FmPcd->p_CcShadow, (uint8_t *)p_CcNodeInfo->h_CcNode, -+ p_ShadowHmct, ((t_FmPcd*)(p_Manip->h_FmPcd))); -+ } -+ -+ p_WholeHmct = (uint8_t *)GetManipInfo(p_Manip, e_MANIP_HMCT); -+ ASSERT_COND(p_WholeHmct); -+ -+ /* re-build the HMCT n the original location */ -+ err = CreateManipActionBackToOrig(p_Manip, p_ManipParams); -+ if (err) -+ { -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ p_Hmtd = (uint8_t *)GetManipInfo(p_Manip, e_MANIP_HMTD); -+ ASSERT_COND(p_Hmtd); -+ BuildHmtd(p_FmPcd->p_CcShadow, (uint8_t *)p_Hmtd, p_WholeHmct, -+ ((t_FmPcd*)p_Manip->h_FmPcd)); -+ -+ /* If LIST > 0, create a list of p_Ad's that point to the HMCT. Join also t_HMTD to this list. -+ * For each p_Hmct (from list+fixed): -+ * call Host Command to replace HMTD by a new one */LIST_FOR_EACH(p_Pos, &lstOfNodeshichPointsOnCrntMdfManip) -+ { -+ p_CcNodeInfo = CC_NODE_F_OBJECT(p_Pos); -+ BuildHmtd(p_FmPcd->p_CcShadow, (uint8_t *)p_CcNodeInfo->h_CcNode, -+ p_WholeHmct, ((t_FmPcd*)(p_Manip->h_FmPcd))); -+ } -+ -+ -+ ReleaseLst(&lstOfNodeshichPointsOnCrntMdfManip); -+ -+ FmPcdLockUnlockAll(p_FmPcd); -+ -+ /* unlock shadow */ -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_ManipNodeDelete(t_Handle h_ManipNode) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_ManipNode; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip, E_INVALID_HANDLE); -+ -+ if (p_Manip->owner) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("This manipulation node not be removed because this node is occupied, first - unbind this node ")); -+ -+ if (p_Manip->h_NextManip) -+ { -+ MANIP_SET_PREV(p_Manip->h_NextManip, NULL); -+ FmPcdManipUpdateOwner(p_Manip->h_NextManip, FALSE); -+ } -+ -+ if (p_Manip->p_Hmct -+ && (MANIP_IS_UNIFIED_FIRST(p_Manip) || !MANIP_IS_UNIFIED(p_Manip))) -+ FM_MURAM_FreeMem(((t_FmPcd *)p_Manip->h_FmPcd)->h_FmMuram, -+ p_Manip->p_Hmct); -+ -+ if (p_Manip->h_Spinlock) -+ { -+ XX_FreeSpinlock(p_Manip->h_Spinlock); -+ p_Manip->h_Spinlock = NULL; -+ } -+ -+ ReleaseManipHandler(p_Manip, p_Manip->h_FmPcd); -+ -+ XX_Free(h_ManipNode); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_ManipGetStatistics(t_Handle h_ManipNode, -+ t_FmPcdManipStats *p_FmPcdManipStats) -+{ -+ t_FmPcdManip *p_Manip = (t_FmPcdManip *)h_ManipNode; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Manip, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcdManipStats, E_NULL_POINTER); -+ -+ switch (p_Manip->opcode) -+ { -+ case (HMAN_OC_IP_REASSEMBLY): -+ return IpReassemblyStats(p_Manip, -+ &p_FmPcdManipStats->u.reassem.u.ipReassem); -+ case (HMAN_OC_IP_FRAGMENTATION): -+ return IpFragmentationStats(p_Manip, -+ &p_FmPcdManipStats->u.frag.u.ipFrag); -+#if (DPAA_VERSION >= 11) -+ case (HMAN_OC_CAPWAP_REASSEMBLY): -+ return CapwapReassemblyStats( -+ p_Manip, &p_FmPcdManipStats->u.reassem.u.capwapReassem); -+ case (HMAN_OC_CAPWAP_FRAGMENTATION): -+ return CapwapFragmentationStats( -+ p_Manip, &p_FmPcdManipStats->u.frag.u.capwapFrag); -+#endif /* (DPAA_VERSION >= 11) */ -+ default: -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, -+ ("no statistics to this type of manip")); -+ } -+ -+ return E_OK; -+} -+ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+t_Handle FM_PCD_StatisticsSetNode(t_Handle h_FmPcd, t_FmPcdStatsParams *p_StatsParams) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ t_FmPcdManip *p_Manip; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmPcd,E_INVALID_HANDLE,NULL); -+ SANITY_CHECK_RETURN_VALUE(p_StatsParams,E_INVALID_HANDLE,NULL); -+ -+ p_Manip = ManipOrStatsSetNode(h_FmPcd, (t_Handle)p_StatsParams, TRUE); -+ if (!p_Manip) -+ return NULL; -+ -+ switch (p_Manip->opcode) -+ { -+ case (HMAN_OC_CAPWAP_INDEXED_STATS): -+ /* Indexed statistics */ -+ err = IndxStats(p_StatsParams, p_Manip, p_FmPcd); -+ break; -+ default: -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("UNSUPPORTED Statistics type")); -+ ReleaseManipHandler(p_Manip, p_FmPcd); -+ XX_Free(p_Manip); -+ return NULL; -+ } -+ -+ if (err) -+ { -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ ReleaseManipHandler(p_Manip, p_FmPcd); -+ XX_Free(p_Manip); -+ return NULL; -+ } -+ -+ return p_Manip; -+} -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_manip.h -@@ -0,0 +1,555 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_manip.h -+ -+ @Description FM PCD manip... -+*//***************************************************************************/ -+#ifndef __FM_MANIP_H -+#define __FM_MANIP_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "list_ext.h" -+ -+#include "fm_cc.h" -+ -+ -+/***********************************************************************/ -+/* Header manipulations defines */ -+/***********************************************************************/ -+ -+#define NUM_OF_SCRATCH_POOL_BUFFERS 1000 /*TODO - Change it!!*/ -+ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+#define HMAN_OC_RMV_N_OR_INSRT_INT_FRM_HDR 0x2e -+#define HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER 0x31 -+#define HMAN_OC_MV_INT_FRAME_HDR_FROM_FRM_TO_BUFFER_PREFFIX 0x2f -+#define HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST 0x30 -+#define HMAN_OC_CAPWAP_REASSEMBLY 0x11 /* dummy */ -+#define HMAN_OC_CAPWAP_INDEXED_STATS 0x32 /* dummy */ -+#define HMAN_OC_CAPWAP_FRAGMENTATION 0x33 -+#else -+#define HMAN_OC_CAPWAP_MANIP 0x2F -+#define HMAN_OC_CAPWAP_FRAG_CHECK 0x2E -+#define HMAN_OC_CAPWAP_FRAGMENTATION 0x33 -+#define HMAN_OC_CAPWAP_REASSEMBLY 0x30 -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+#define HMAN_OC_IP_MANIP 0x34 -+#define HMAN_OC_IP_FRAGMENTATION 0x74 -+#define HMAN_OC_IP_REASSEMBLY 0xB4 -+#define HMAN_OC_IPSEC_MANIP 0xF4 -+#define HMAN_OC 0x35 -+ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+#define HMAN_RMV_HDR 0x80000000 -+#define HMAN_INSRT_INT_FRM_HDR 0x40000000 -+ -+#define UDP_CHECKSUM_FIELD_OFFSET_FROM_UDP 6 -+#define UDP_CHECKSUM_FIELD_SIZE 2 -+#define UDP_LENGTH_FIELD_OFFSET_FROM_UDP 4 -+ -+#define IPv4_DSCECN_FIELD_OFFSET_FROM_IP 1 -+#define IPv4_TOTALLENGTH_FIELD_OFFSET_FROM_IP 2 -+#define IPv4_HDRCHECKSUM_FIELD_OFFSET_FROM_IP 10 -+#define VLAN_TAG_FIELD_OFFSET_FROM_ETH 12 -+#define IPv4_ID_FIELD_OFFSET_FROM_IP 4 -+ -+#define IPv6_PAYLOAD_LENGTH_OFFSET_FROM_IP 4 -+#define IPv6_NEXT_HEADER_OFFSET_FROM_IP 6 -+ -+#define FM_PCD_MANIP_CAPWAP_REASM_TABLE_SIZE 0x80 -+#define FM_PCD_MANIP_CAPWAP_REASM_TABLE_ALIGN 8 -+#define FM_PCD_MANIP_CAPWAP_REASM_RFD_SIZE 32 -+#define FM_PCD_MANIP_CAPWAP_REASM_AUTO_LEARNING_HASH_ENTRY_SIZE 4 -+#define FM_PCD_MANIP_CAPWAP_REASM_TIME_OUT_ENTRY_SIZE 8 -+ -+ -+#define FM_PCD_MANIP_CAPWAP_REASM_TIME_OUT_BETWEEN_FRAMES 0x40000000 -+#define FM_PCD_MANIP_CAPWAP_REASM_HALT_ON_DUPLICATE_FRAG 0x10000000 -+#define FM_PCD_MANIP_CAPWAP_REASM_AUTOMATIC_LEARNIN_HASH_8_WAYS 0x08000000 -+#define FM_PCD_MANIP_CAPWAP_REASM_PR_COPY 0x00800000 -+ -+#define FM_PCD_MANIP_CAPWAP_FRAG_COMPR_OPTION_FIELD_EN 0x80000000 -+ -+#define FM_PCD_MANIP_INDEXED_STATS_ENTRY_SIZE 4 -+#define FM_PCD_MANIP_INDEXED_STATS_CNIA 0x20000000 -+#define FM_PCD_MANIP_INDEXED_STATS_DPD 0x10000000 -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ -+#if (DPAA_VERSION >= 11) -+#define FM_PCD_MANIP_CAPWAP_DTLS 0x00040000 -+#define FM_PCD_MANIP_CAPWAP_NADEN 0x20000000 -+ -+#define FM_PCD_MANIP_CAPWAP_FRAG_CHECK_MTU_SHIFT 16 -+#define FM_PCD_MANIP_CAPWAP_FRAG_CHECK_NO_FRAGMENTATION 0xFFFF0000 -+#define FM_PCD_MANIP_CAPWAP_FRAG_CHECK_CNIA 0x20000000 -+ -+#define FM_PCD_MANIP_CAPWAP_FRAG_COMPRESS_EN 0x04000000 -+#define FM_PCD_MANIP_CAPWAP_FRAG_SCRATCH_BPID 24 -+#define FM_PCD_MANIP_CAPWAP_FRAG_SG_BDID_EN 0x08000000 -+#define FM_PCD_MANIP_CAPWAP_FRAG_SG_BDID_MASK 0xFF000000 -+#define FM_PCD_MANIP_CAPWAP_FRAG_SG_BDID_SHIFT 24 -+#endif /* (DPAA_VERSION >= 11) */ -+ -+#define FM_PCD_MANIP_REASM_TABLE_SIZE 0x40 -+#define FM_PCD_MANIP_REASM_TABLE_ALIGN 8 -+ -+#define FM_PCD_MANIP_REASM_COMMON_PARAM_TABLE_SIZE 64 -+#define FM_PCD_MANIP_REASM_COMMON_PARAM_TABLE_ALIGN 8 -+#define FM_PCD_MANIP_REASM_TIME_OUT_BETWEEN_FRAMES 0x80000000 -+#define FM_PCD_MANIP_REASM_COUPLING_ENABLE 0x40000000 -+#define FM_PCD_MANIP_REASM_COUPLING_MASK 0xFF000000 -+#define FM_PCD_MANIP_REASM_COUPLING_SHIFT 24 -+#define FM_PCD_MANIP_REASM_LIODN_MASK 0x0000003F -+#define FM_PCD_MANIP_REASM_LIODN_SHIFT 56 -+#define FM_PCD_MANIP_REASM_ELIODN_MASK 0x000003c0 -+#define FM_PCD_MANIP_REASM_ELIODN_SHIFT 38 -+#define FM_PCD_MANIP_REASM_COMMON_INT_BUFFER_IDX_MASK 0x000000FF -+#define FM_PCD_MANIP_REASM_COMMON_INT_BUFFER_IDX_SHIFT 24 -+#define FM_PCD_MANIP_REASM_TIMEOUT_THREAD_THRESH 1024 -+ -+#define FM_PCD_MANIP_IP_MTU_SHIFT 16 -+#define FM_PCD_MANIP_IP_NO_FRAGMENTATION 0xFFFF0000 -+#define FM_PCD_MANIP_IP_CNIA 0x20000000 -+ -+#define FM_PCD_MANIP_IP_FRAG_DF_SHIFT 28 -+#define FM_PCD_MANIP_IP_FRAG_SCRATCH_BPID 24 -+#define FM_PCD_MANIP_IP_FRAG_SG_BDID_EN 0x08000000 -+#define FM_PCD_MANIP_IP_FRAG_SG_BDID_MASK 0xFF000000 -+#define FM_PCD_MANIP_IP_FRAG_SG_BDID_SHIFT 24 -+ -+#define FM_PCD_MANIP_IPSEC_DEC 0x10000000 -+#define FM_PCD_MANIP_IPSEC_VIPV_EN 0x08000000 -+#define FM_PCD_MANIP_IPSEC_ECN_EN 0x04000000 -+#define FM_PCD_MANIP_IPSEC_DSCP_EN 0x02000000 -+#define FM_PCD_MANIP_IPSEC_VIPL_EN 0x01000000 -+#define FM_PCD_MANIP_IPSEC_NADEN 0x20000000 -+ -+#define FM_PCD_MANIP_IPSEC_IP_HDR_LEN_MASK 0x00FF0000 -+#define FM_PCD_MANIP_IPSEC_IP_HDR_LEN_SHIFT 16 -+ -+#define FM_PCD_MANIP_IPSEC_ARW_SIZE_MASK 0xFFFF0000 -+#define FM_PCD_MANIP_IPSEC_ARW_SIZE_SHIFT 16 -+ -+#define e_FM_MANIP_IP_INDX 1 -+ -+#define HMCD_OPCODE_GENERIC_RMV 0x01 -+#define HMCD_OPCODE_GENERIC_INSRT 0x02 -+#define HMCD_OPCODE_GENERIC_REPLACE 0x05 -+#define HMCD_OPCODE_L2_RMV 0x08 -+#define HMCD_OPCODE_L2_INSRT 0x09 -+#define HMCD_OPCODE_VLAN_PRI_UPDATE 0x0B -+#define HMCD_OPCODE_IPV4_UPDATE 0x0C -+#define HMCD_OPCODE_IPV6_UPDATE 0x10 -+#define HMCD_OPCODE_TCP_UDP_UPDATE 0x0E -+#define HMCD_OPCODE_TCP_UDP_CHECKSUM 0x14 -+#define HMCD_OPCODE_REPLACE_IP 0x12 -+#define HMCD_OPCODE_RMV_TILL 0x15 -+#define HMCD_OPCODE_UDP_INSRT 0x16 -+#define HMCD_OPCODE_IP_INSRT 0x17 -+#define HMCD_OPCODE_CAPWAP_RMV 0x18 -+#define HMCD_OPCODE_CAPWAP_INSRT 0x18 -+#define HMCD_OPCODE_GEN_FIELD_REPLACE 0x19 -+ -+#define HMCD_LAST 0x00800000 -+ -+#define HMCD_DSCP_VALUES 64 -+ -+#define HMCD_BASIC_SIZE 4 -+#define HMCD_PTR_SIZE 4 -+#define HMCD_PARAM_SIZE 4 -+#define HMCD_IPV4_ADDR_SIZE 4 -+#define HMCD_IPV6_ADDR_SIZE 0x10 -+#define HMCD_L4_HDR_SIZE 8 -+ -+#define HMCD_CAPWAP_INSRT 0x00010000 -+#define HMCD_INSRT_UDP_LITE 0x00010000 -+#define HMCD_IP_ID_MASK 0x0000FFFF -+#define HMCD_IP_SIZE_MASK 0x0000FF00 -+#define HMCD_IP_SIZE_SHIFT 8 -+#define HMCD_IP_LAST_PID_MASK 0x000000FF -+#define HMCD_IP_OR_QOS 0x00010000 -+#define HMCD_IP_L4_CS_CALC 0x00040000 -+#define HMCD_IP_DF_MODE 0x00400000 -+ -+ -+#define HMCD_OC_SHIFT 24 -+ -+#define HMCD_RMV_OFFSET_SHIFT 0 -+#define HMCD_RMV_SIZE_SHIFT 8 -+ -+#define HMCD_INSRT_OFFSET_SHIFT 0 -+#define HMCD_INSRT_SIZE_SHIFT 8 -+ -+#define HMTD_CFG_TYPE 0x4000 -+#define HMTD_CFG_EXT_HMCT 0x0080 -+#define HMTD_CFG_PRS_AFTER_HM 0x0040 -+#define HMTD_CFG_NEXT_AD_EN 0x0020 -+ -+#define HMCD_RMV_L2_ETHERNET 0 -+#define HMCD_RMV_L2_STACKED_QTAGS 1 -+#define HMCD_RMV_L2_ETHERNET_AND_MPLS 2 -+#define HMCD_RMV_L2_MPLS 3 -+#define HMCD_RMV_L2_PPPOE 4 -+ -+#define HMCD_INSRT_L2_MPLS 0 -+#define HMCD_INSRT_N_UPDATE_L2_MPLS 1 -+#define HMCD_INSRT_L2_PPPOE 2 -+#define HMCD_INSRT_L2_SIZE_SHIFT 24 -+ -+#define HMCD_L2_MODE_SHIFT 16 -+ -+#define HMCD_VLAN_PRI_REP_MODE_SHIFT 16 -+#define HMCD_VLAN_PRI_UPDATE 0 -+#define HMCD_VLAN_PRI_UPDATE_DSCP_TO_VPRI 1 -+ -+#define HMCD_IPV4_UPDATE_TTL 0x00000001 -+#define HMCD_IPV4_UPDATE_TOS 0x00000002 -+#define HMCD_IPV4_UPDATE_DST 0x00000020 -+#define HMCD_IPV4_UPDATE_SRC 0x00000040 -+#define HMCD_IPV4_UPDATE_ID 0x00000080 -+#define HMCD_IPV4_UPDATE_TOS_SHIFT 8 -+ -+#define HMCD_IPV6_UPDATE_HL 0x00000001 -+#define HMCD_IPV6_UPDATE_TC 0x00000002 -+#define HMCD_IPV6_UPDATE_DST 0x00000040 -+#define HMCD_IPV6_UPDATE_SRC 0x00000080 -+#define HMCD_IPV6_UPDATE_TC_SHIFT 8 -+ -+#define HMCD_TCP_UDP_UPDATE_DST 0x00004000 -+#define HMCD_TCP_UDP_UPDATE_SRC 0x00008000 -+#define HMCD_TCP_UDP_UPDATE_SRC_SHIFT 16 -+ -+#define HMCD_IP_REPLACE_REPLACE_IPV4 0x00000000 -+#define HMCD_IP_REPLACE_REPLACE_IPV6 0x00010000 -+#define HMCD_IP_REPLACE_TTL_HL 0x00200000 -+#define HMCD_IP_REPLACE_ID 0x00400000 -+ -+#define HMCD_IP_REPLACE_L3HDRSIZE_SHIFT 24 -+ -+#define HMCD_GEN_FIELD_SIZE_SHIFT 16 -+#define HMCD_GEN_FIELD_SRC_OFF_SHIFT 8 -+#define HMCD_GEN_FIELD_DST_OFF_SHIFT 0 -+#define HMCD_GEN_FIELD_MASK_EN 0x00400000 -+ -+#define HMCD_GEN_FIELD_MASK_OFF_SHIFT 16 -+#define HMCD_GEN_FIELD_MASK_SHIFT 24 -+ -+#define DSCP_TO_VLAN_TABLE_SIZE 32 -+ -+#define MANIP_GET_HMCT_SIZE(h_Manip) (((t_FmPcdManip *)h_Manip)->tableSize) -+#define MANIP_GET_DATA_SIZE(h_Manip) (((t_FmPcdManip *)h_Manip)->dataSize) -+ -+#define MANIP_GET_HMCT_PTR(h_Manip) (((t_FmPcdManip *)h_Manip)->p_Hmct) -+#define MANIP_GET_DATA_PTR(h_Manip) (((t_FmPcdManip *)h_Manip)->p_Data) -+ -+#define MANIP_SET_HMCT_PTR(h_Manip, h_NewPtr) (((t_FmPcdManip *)h_Manip)->p_Hmct = h_NewPtr) -+#define MANIP_SET_DATA_PTR(h_Manip, h_NewPtr) (((t_FmPcdManip *)h_Manip)->p_Data = h_NewPtr) -+ -+#define MANIP_GET_HMTD_PTR(h_Manip) (((t_FmPcdManip *)h_Manip)->h_Ad) -+#define MANIP_DONT_REPARSE(h_Manip) (((t_FmPcdManip *)h_Manip)->dontParseAfterManip) -+#define MANIP_SET_PREV(h_Manip, h_Prev) (((t_FmPcdManip *)h_Manip)->h_PrevManip = h_Prev) -+#define MANIP_GET_OWNERS(h_Manip) (((t_FmPcdManip *)h_Manip)->owner) -+#define MANIP_GET_TYPE(h_Manip) (((t_FmPcdManip *)h_Manip)->type) -+#define MANIP_SET_UNIFIED_TBL_PTR_INDICATION(h_Manip) (((t_FmPcdManip *)h_Manip)->unifiedTablePtr = TRUE) -+#define MANIP_GET_MURAM(h_Manip) (((t_FmPcd *)((t_FmPcdManip *)h_Manip)->h_FmPcd)->h_FmMuram) -+#define MANIP_FREE_HMTD(h_Manip) \ -+ {if (((t_FmPcdManip *)h_Manip)->muramAllocate) \ -+ FM_MURAM_FreeMem(((t_FmPcd *)((t_FmPcdManip *)h_Manip)->h_FmPcd)->h_FmMuram, ((t_FmPcdManip *)h_Manip)->h_Ad);\ -+ else \ -+ XX_Free(((t_FmPcdManip *)h_Manip)->h_Ad); \ -+ ((t_FmPcdManip *)h_Manip)->h_Ad = NULL; \ -+ } -+/* position regarding Manip SW structure */ -+#define MANIP_IS_FIRST(h_Manip) (!(((t_FmPcdManip *)h_Manip)->h_PrevManip)) -+#define MANIP_IS_CASCADED(h_Manip) (((t_FmPcdManip *)h_Manip)->cascaded) -+#define MANIP_IS_UNIFIED(h_Manip) (!(((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_NONE)) -+#define MANIP_IS_UNIFIED_NON_FIRST(h_Manip) ((((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_MID) || \ -+ (((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_LAST)) -+#define MANIP_IS_UNIFIED_NON_LAST(h_Manip) ((((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_FIRST) ||\ -+ (((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_MID)) -+#define MANIP_IS_UNIFIED_FIRST(h_Manip) (((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_FIRST) -+#define MANIP_IS_UNIFIED_LAST(h_Manip) (((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_LAST) -+ -+#define MANIP_UPDATE_UNIFIED_POSITION(h_Manip) (((t_FmPcdManip *)h_Manip)->unifiedPosition = \ -+ (((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_NONE)? \ -+ e_MANIP_UNIFIED_LAST : e_MANIP_UNIFIED_MID) -+ -+typedef enum e_ManipUnifiedPosition { -+ e_MANIP_UNIFIED_NONE = 0, -+ e_MANIP_UNIFIED_FIRST, -+ e_MANIP_UNIFIED_MID, -+ e_MANIP_UNIFIED_LAST -+} e_ManipUnifiedPosition; -+ -+typedef enum e_ManipInfo { -+ e_MANIP_HMTD, -+ e_MANIP_HMCT, -+ e_MANIP_HANDLER_TABLE_OWNER -+}e_ManipInfo; -+/***********************************************************************/ -+/* Memory map */ -+/***********************************************************************/ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+typedef struct t_CapwapReasmPram { -+ volatile uint32_t mode; -+ volatile uint32_t autoLearnHashTblPtr; -+ volatile uint32_t intStatsTblPtr; -+ volatile uint32_t reasmFrmDescPoolTblPtr; -+ volatile uint32_t reasmFrmDescIndexPoolTblPtr; -+ volatile uint32_t timeOutTblPtr; -+ volatile uint32_t bufferPoolIdAndRisc1SetIndexes; -+ volatile uint32_t risc23SetIndexes; -+ volatile uint32_t risc4SetIndexesAndExtendedStatsTblPtr; -+ volatile uint32_t extendedStatsTblPtr; -+ volatile uint32_t expirationDelay; -+ volatile uint32_t totalProcessedFragCounter; -+ volatile uint32_t totalUnsuccessfulReasmFramesCounter; -+ volatile uint32_t totalDuplicatedFragCounter; -+ volatile uint32_t totalMalformdFragCounter; -+ volatile uint32_t totalTimeOutCounter; -+ volatile uint32_t totalSetBusyCounter; -+ volatile uint32_t totalRfdPoolBusyCounter; -+ volatile uint32_t totalDiscardedFragsCounter; -+ volatile uint32_t totalMoreThan16FramesCounter; -+ volatile uint32_t internalBufferBusy; -+ volatile uint32_t externalBufferBusy; -+ volatile uint32_t reserved1[4]; -+} t_CapwapReasmPram; -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ -+typedef _Packed struct t_ReassTbl { -+ volatile uint16_t waysNumAndSetSize; -+ volatile uint16_t autoLearnHashKeyMask; -+ volatile uint32_t reassCommonPrmTblPtr; -+ volatile uint32_t liodnAlAndAutoLearnHashTblPtrHi; -+ volatile uint32_t autoLearnHashTblPtrLow; -+ volatile uint32_t liodnSlAndAutoLearnSetLockTblPtrHi; -+ volatile uint32_t autoLearnSetLockTblPtrLow; -+ volatile uint16_t minFragSize; /* Not relevant for CAPWAP*/ -+ volatile uint16_t maxReassemblySize; /* Only relevant for CAPWAP*/ -+ volatile uint32_t totalSuccessfullyReasmFramesCounter; -+ volatile uint32_t totalValidFragmentCounter; -+ volatile uint32_t totalProcessedFragCounter; -+ volatile uint32_t totalMalformdFragCounter; -+ volatile uint32_t totalSetBusyCounter; -+ volatile uint32_t totalDiscardedFragsCounter; -+ volatile uint32_t totalMoreThan16FramesCounter; -+ volatile uint32_t reserved2[2]; -+} _PackedType t_ReassTbl; -+ -+typedef struct t_ReassCommonTbl { -+ volatile uint32_t timeoutModeAndFqid; -+ volatile uint32_t reassFrmDescIndexPoolTblPtr; -+ volatile uint32_t liodnAndReassFrmDescPoolPtrHi; -+ volatile uint32_t reassFrmDescPoolPtrLow; -+ volatile uint32_t timeOutTblPtr; -+ volatile uint32_t expirationDelay; -+ volatile uint32_t internalBufferManagement; -+ volatile uint32_t reserved2; -+ volatile uint32_t totalTimeOutCounter; -+ volatile uint32_t totalRfdPoolBusyCounter; -+ volatile uint32_t totalInternalBufferBusy; -+ volatile uint32_t totalExternalBufferBusy; -+ volatile uint32_t totalSgFragmentCounter; -+ volatile uint32_t totalDmaSemaphoreDepletionCounter; -+ volatile uint32_t totalNCSPCounter; -+ volatile uint32_t discardMask; -+} t_ReassCommonTbl; -+ -+typedef _Packed struct t_Hmtd { -+ volatile uint16_t cfg; -+ volatile uint8_t eliodnOffset; -+ volatile uint8_t extHmcdBasePtrHi; -+ volatile uint32_t hmcdBasePtr; -+ volatile uint16_t nextAdIdx; -+ volatile uint8_t res1; -+ volatile uint8_t opCode; -+ volatile uint32_t res2; -+} _PackedType t_Hmtd; -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+ -+/***********************************************************************/ -+/* Driver's internal structures */ -+/***********************************************************************/ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+typedef struct -+{ -+ t_Handle p_AutoLearnHashTbl; -+ t_Handle p_ReassmFrmDescrPoolTbl; -+ t_Handle p_ReassmFrmDescrIndxPoolTbl; -+ t_Handle p_TimeOutTbl; -+ uint16_t maxNumFramesInProcess; -+ uint8_t numOfTasks; -+ //uint8_t poolId; -+ uint8_t prOffset; -+ uint16_t dataOffset; -+ uint8_t sgBpid; -+ uint8_t hwPortId; -+ uint32_t fqidForTimeOutFrames; -+ uint32_t timeoutRoutineRequestTime; -+ uint32_t bitFor1Micro; -+} t_CapwapFragParams; -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ -+typedef struct -+{ -+ t_AdOfTypeContLookup *p_Frag; -+#if (DPAA_VERSION == 10) -+ uint8_t scratchBpid; -+#endif /* (DPAA_VERSION == 10) */ -+} t_FragParams; -+ -+typedef struct t_ReassmParams -+{ -+ e_NetHeaderType hdr; /* Header selection */ -+ t_ReassCommonTbl *p_ReassCommonTbl; -+ uintptr_t reassFrmDescrIndxPoolTblAddr; -+ uintptr_t reassFrmDescrPoolTblAddr; -+ uintptr_t timeOutTblAddr; -+ uintptr_t internalBufferPoolManagementIndexAddr; -+ uintptr_t internalBufferPoolAddr; -+ uint32_t maxNumFramesInProcess; -+ uint8_t sgBpid; -+ uint8_t dataMemId; -+ uint16_t dataLiodnOffset; -+ uint32_t fqidForTimeOutFrames; -+ e_FmPcdManipReassemTimeOutMode timeOutMode; -+ uint32_t timeoutThresholdForReassmProcess; -+ union { -+ struct { -+ t_Handle h_Ipv4Ad; -+ t_Handle h_Ipv6Ad; -+ bool ipv6Assigned; -+ t_ReassTbl *p_Ipv4ReassTbl; -+ t_ReassTbl *p_Ipv6ReassTbl; -+ uintptr_t ipv4AutoLearnHashTblAddr; -+ uintptr_t ipv6AutoLearnHashTblAddr; -+ uintptr_t ipv4AutoLearnSetLockTblAddr; -+ uintptr_t ipv6AutoLearnSetLockTblAddr; -+ uint16_t minFragSize[2]; -+ e_FmPcdManipReassemWaysNumber numOfFramesPerHashEntry[2]; -+ uint8_t relativeSchemeId[2]; -+ t_Handle h_Ipv4Scheme; -+ t_Handle h_Ipv6Scheme; -+ uint32_t nonConsistentSpFqid; -+ } ip; -+ struct { -+ t_Handle h_Ad; -+ t_ReassTbl *p_ReassTbl; -+ uintptr_t autoLearnHashTblAddr; -+ uintptr_t autoLearnSetLockTblAddr; -+ uint16_t maxRessembledsSize; -+ e_FmPcdManipReassemWaysNumber numOfFramesPerHashEntry; -+ uint8_t relativeSchemeId; -+ t_Handle h_Scheme; -+ } capwap; -+ }; -+} t_ReassmParams; -+ -+typedef struct{ -+ e_FmPcdManipType type; -+ t_FmPcdManipParams manipParams; -+ bool muramAllocate; -+ t_Handle h_Ad; -+ uint32_t opcode; -+ bool rmv; -+ bool insrt; -+ t_Handle h_NextManip; -+ t_Handle h_PrevManip; -+ e_FmPcdManipType nextManipType; -+ /* HdrManip parameters*/ -+ uint8_t *p_Hmct; -+ uint8_t *p_Data; -+ bool dontParseAfterManip; -+ bool fieldUpdate; -+ bool custom; -+ uint16_t tableSize; -+ uint8_t dataSize; -+ bool cascaded; -+ e_ManipUnifiedPosition unifiedPosition; -+ /* end HdrManip */ -+ uint8_t *p_Template; -+ uint16_t owner; -+ uint32_t updateParams; -+ uint32_t shadowUpdateParams; -+ bool frag; -+ bool reassm; -+ uint16_t sizeForFragmentation; -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ t_Handle h_Frag; -+ t_CapwapFragParams capwapFragParams; -+#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */ -+ union { -+ t_ReassmParams reassmParams; -+ t_FragParams fragParams; -+ }; -+ uint8_t icOffset; -+ uint16_t ownerTmp; -+ bool cnia; -+ t_Handle p_StatsTbl; -+ t_Handle h_FmPcd; -+ t_List nodesLst; -+ t_Handle h_Spinlock; -+} t_FmPcdManip; -+ -+typedef struct t_FmPcdCcSavedManipParams -+{ -+ union -+ { -+ struct -+ { -+ uint16_t dataOffset; -+ //uint8_t poolId; -+ }capwapParams; -+ struct -+ { -+ uint16_t dataOffset; -+ uint8_t poolId; -+ }ipParams; -+ }; -+ -+} t_FmPcdCcSavedManipParams; -+ -+ -+#endif /* __FM_MANIP_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd.c -@@ -0,0 +1,2094 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_pcd.c -+ -+ @Description FM PCD ... -+*//***************************************************************************/ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "string_ext.h" -+#include "xx_ext.h" -+#include "sprint_ext.h" -+#include "debug_ext.h" -+#include "net_ext.h" -+#include "fm_ext.h" -+#include "fm_pcd_ext.h" -+ -+#include "fm_common.h" -+#include "fm_pcd.h" -+#include "fm_pcd_ipc.h" -+#include "fm_hc.h" -+#include "fm_muram_ext.h" -+ -+ -+/****************************************/ -+/* static functions */ -+/****************************************/ -+ -+static t_Error CheckFmPcdParameters(t_FmPcd *p_FmPcd) -+{ -+ if (!p_FmPcd->h_Fm) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("h_Fm has to be initialized")); -+ -+ if (p_FmPcd->guestId == NCSW_MASTER_ID) -+ { -+ if (p_FmPcd->p_FmPcdKg && !p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Something WRONG")); -+ -+ if (p_FmPcd->p_FmPcdPlcr && !p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Something WRONG")); -+ -+ if (!p_FmPcd->f_Exception) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("f_FmPcdExceptions has to be initialized")); -+ -+ if ((!p_FmPcd->f_FmPcdIndexedException) && (p_FmPcd->p_FmPcdPlcr || p_FmPcd->p_FmPcdKg)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("f_FmPcdIndexedException has to be initialized")); -+ -+ if (p_FmPcd->p_FmPcdDriverParam->prsMaxParseCycleLimit > PRS_MAX_CYCLE_LIMIT) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("prsMaxParseCycleLimit has to be less than 8191")); -+ } -+ -+ return E_OK; -+} -+ -+static volatile bool blockingFlag = FALSE; -+static void IpcMsgCompletionCB(t_Handle h_FmPcd, -+ uint8_t *p_Msg, -+ uint8_t *p_Reply, -+ uint32_t replyLength, -+ t_Error status) -+{ -+ UNUSED(h_FmPcd);UNUSED(p_Msg);UNUSED(p_Reply);UNUSED(replyLength);UNUSED(status); -+ blockingFlag = FALSE; -+} -+ -+static t_Error IpcMsgHandlerCB(t_Handle h_FmPcd, -+ uint8_t *p_Msg, -+ uint32_t msgLength, -+ uint8_t *p_Reply, -+ uint32_t *p_ReplyLength) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_Error err = E_OK; -+ t_FmPcdIpcMsg *p_IpcMsg = (t_FmPcdIpcMsg*)p_Msg; -+ t_FmPcdIpcReply *p_IpcReply = (t_FmPcdIpcReply*)p_Reply; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((msgLength >= sizeof(uint32_t)), E_INVALID_VALUE); -+ -+#ifdef DISABLE_SANITY_CHECKS -+ UNUSED(msgLength); -+#endif /* DISABLE_SANITY_CHECKS */ -+ -+ ASSERT_COND(p_Msg); -+ -+ memset(p_IpcReply, 0, (sizeof(uint8_t) * FM_PCD_MAX_REPLY_SIZE)); -+ *p_ReplyLength = 0; -+ -+ switch (p_IpcMsg->msgId) -+ { -+ case (FM_PCD_MASTER_IS_ALIVE): -+ *(uint8_t*)(p_IpcReply->replyBody) = 1; -+ p_IpcReply->error = E_OK; -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(uint8_t); -+ break; -+ case (FM_PCD_MASTER_IS_ENABLED): -+ /* count partitions registrations */ -+ if (p_FmPcd->enabled) -+ p_FmPcd->numOfEnabledGuestPartitionsPcds++; -+ *(uint8_t*)(p_IpcReply->replyBody) = (uint8_t)p_FmPcd->enabled; -+ p_IpcReply->error = E_OK; -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(uint8_t); -+ break; -+ case (FM_PCD_GUEST_DISABLE): -+ if (p_FmPcd->numOfEnabledGuestPartitionsPcds) -+ { -+ p_FmPcd->numOfEnabledGuestPartitionsPcds--; -+ p_IpcReply->error = E_OK; -+ } -+ else -+ { -+ REPORT_ERROR(MINOR, E_INVALID_STATE,("Trying to disable an unregistered partition")); -+ p_IpcReply->error = E_INVALID_STATE; -+ } -+ *p_ReplyLength = sizeof(uint32_t); -+ break; -+ case (FM_PCD_GET_COUNTER): -+ { -+ e_FmPcdCounters inCounter; -+ uint32_t outCounter; -+ -+ memcpy((uint8_t*)&inCounter, p_IpcMsg->msgBody, sizeof(uint32_t)); -+ outCounter = FM_PCD_GetCounter(h_FmPcd, inCounter); -+ memcpy(p_IpcReply->replyBody, (uint8_t*)&outCounter, sizeof(uint32_t)); -+ p_IpcReply->error = E_OK; -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(uint32_t); -+ break; -+ } -+ case (FM_PCD_ALLOC_KG_SCHEMES): -+ { -+ t_FmPcdIpcKgSchemesParams ipcSchemesParams; -+ -+ memcpy((uint8_t*)&ipcSchemesParams, p_IpcMsg->msgBody, sizeof(t_FmPcdIpcKgSchemesParams)); -+ err = FmPcdKgAllocSchemes(h_FmPcd, -+ ipcSchemesParams.numOfSchemes, -+ ipcSchemesParams.guestId, -+ p_IpcReply->replyBody); -+ p_IpcReply->error = err; -+ *p_ReplyLength = sizeof(uint32_t) + ipcSchemesParams.numOfSchemes*sizeof(uint8_t); -+ break; -+ } -+ case (FM_PCD_FREE_KG_SCHEMES): -+ { -+ t_FmPcdIpcKgSchemesParams ipcSchemesParams; -+ -+ memcpy((uint8_t*)&ipcSchemesParams, p_IpcMsg->msgBody, sizeof(t_FmPcdIpcKgSchemesParams)); -+ err = FmPcdKgFreeSchemes(h_FmPcd, -+ ipcSchemesParams.numOfSchemes, -+ ipcSchemesParams.guestId, -+ ipcSchemesParams.schemesIds); -+ p_IpcReply->error = err; -+ *p_ReplyLength = sizeof(uint32_t); -+ break; -+ } -+ case (FM_PCD_ALLOC_KG_CLSPLAN): -+ { -+ t_FmPcdIpcKgClsPlanParams ipcKgClsPlanParams; -+ -+ memcpy((uint8_t*)&ipcKgClsPlanParams, p_IpcMsg->msgBody, sizeof(t_FmPcdIpcKgClsPlanParams)); -+ err = KgAllocClsPlanEntries(h_FmPcd, -+ ipcKgClsPlanParams.numOfClsPlanEntries, -+ ipcKgClsPlanParams.guestId, -+ p_IpcReply->replyBody); -+ p_IpcReply->error = err; -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(uint8_t); -+ break; -+ } -+ case (FM_PCD_FREE_KG_CLSPLAN): -+ { -+ t_FmPcdIpcKgClsPlanParams ipcKgClsPlanParams; -+ -+ memcpy((uint8_t*)&ipcKgClsPlanParams, p_IpcMsg->msgBody, sizeof(t_FmPcdIpcKgClsPlanParams)); -+ KgFreeClsPlanEntries(h_FmPcd, -+ ipcKgClsPlanParams.numOfClsPlanEntries, -+ ipcKgClsPlanParams.guestId, -+ ipcKgClsPlanParams.clsPlanBase); -+ *p_ReplyLength = sizeof(uint32_t); -+ break; -+ } -+ case (FM_PCD_ALLOC_PROFILES): -+ { -+ t_FmIpcResourceAllocParams ipcAllocParams; -+ uint16_t base; -+ memcpy(&ipcAllocParams, p_IpcMsg->msgBody, sizeof(t_FmIpcResourceAllocParams)); -+ base = PlcrAllocProfilesForPartition(h_FmPcd, -+ ipcAllocParams.base, -+ ipcAllocParams.num, -+ ipcAllocParams.guestId); -+ memcpy(p_IpcReply->replyBody, (uint16_t*)&base, sizeof(uint16_t)); -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(uint16_t); -+ break; -+ } -+ case (FM_PCD_FREE_PROFILES): -+ { -+ t_FmIpcResourceAllocParams ipcAllocParams; -+ memcpy(&ipcAllocParams, p_IpcMsg->msgBody, sizeof(t_FmIpcResourceAllocParams)); -+ PlcrFreeProfilesForPartition(h_FmPcd, -+ ipcAllocParams.base, -+ ipcAllocParams.num, -+ ipcAllocParams.guestId); -+ break; -+ } -+ case (FM_PCD_SET_PORT_PROFILES): -+ { -+ t_FmIpcResourceAllocParams ipcAllocParams; -+ memcpy(&ipcAllocParams, p_IpcMsg->msgBody, sizeof(t_FmIpcResourceAllocParams)); -+ PlcrSetPortProfiles(h_FmPcd, -+ ipcAllocParams.guestId, -+ ipcAllocParams.num, -+ ipcAllocParams.base); -+ break; -+ } -+ case (FM_PCD_CLEAR_PORT_PROFILES): -+ { -+ t_FmIpcResourceAllocParams ipcAllocParams; -+ memcpy(&ipcAllocParams, p_IpcMsg->msgBody, sizeof(t_FmIpcResourceAllocParams)); -+ PlcrClearPortProfiles(h_FmPcd, -+ ipcAllocParams.guestId); -+ break; -+ } -+ case (FM_PCD_GET_SW_PRS_OFFSET): -+ { -+ t_FmPcdIpcSwPrsLable ipcSwPrsLable; -+ uint32_t swPrsOffset; -+ -+ memcpy((uint8_t*)&ipcSwPrsLable, p_IpcMsg->msgBody, sizeof(t_FmPcdIpcSwPrsLable)); -+ swPrsOffset = -+ FmPcdGetSwPrsOffset(h_FmPcd, -+ (e_NetHeaderType)ipcSwPrsLable.enumHdr, -+ ipcSwPrsLable.indexPerHdr); -+ memcpy(p_IpcReply->replyBody, (uint8_t*)&swPrsOffset, sizeof(uint32_t)); -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(uint32_t); -+ break; -+ } -+ case (FM_PCD_PRS_INC_PORT_STATS): -+ { -+ t_FmPcdIpcPrsIncludePort ipcPrsIncludePort; -+ -+ memcpy((uint8_t*)&ipcPrsIncludePort, p_IpcMsg->msgBody, sizeof(t_FmPcdIpcPrsIncludePort)); -+ PrsIncludePortInStatistics(h_FmPcd, -+ ipcPrsIncludePort.hardwarePortId, -+ ipcPrsIncludePort.include); -+ break; -+ } -+ default: -+ *p_ReplyLength = 0; -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, ("command not found!!!")); -+ } -+ return E_OK; -+} -+ -+static uint32_t NetEnvLock(t_Handle h_NetEnv) -+{ -+ ASSERT_COND(h_NetEnv); -+ return XX_LockIntrSpinlock(((t_FmPcdNetEnv*)h_NetEnv)->h_Spinlock); -+} -+ -+static void NetEnvUnlock(t_Handle h_NetEnv, uint32_t intFlags) -+{ -+ ASSERT_COND(h_NetEnv); -+ XX_UnlockIntrSpinlock(((t_FmPcdNetEnv*)h_NetEnv)->h_Spinlock, intFlags); -+} -+ -+static void EnqueueLockToFreeLst(t_FmPcd *p_FmPcd, t_FmPcdLock *p_Lock) -+{ -+ uint32_t intFlags; -+ -+ intFlags = XX_LockIntrSpinlock(p_FmPcd->h_Spinlock); -+ LIST_AddToTail(&p_Lock->node, &p_FmPcd->freeLocksLst); -+ XX_UnlockIntrSpinlock(p_FmPcd->h_Spinlock, intFlags); -+} -+ -+static t_FmPcdLock * DequeueLockFromFreeLst(t_FmPcd *p_FmPcd) -+{ -+ t_FmPcdLock *p_Lock = NULL; -+ uint32_t intFlags; -+ -+ intFlags = XX_LockIntrSpinlock(p_FmPcd->h_Spinlock); -+ if (!LIST_IsEmpty(&p_FmPcd->freeLocksLst)) -+ { -+ p_Lock = FM_PCD_LOCK_OBJ(p_FmPcd->freeLocksLst.p_Next); -+ LIST_DelAndInit(&p_Lock->node); -+ } -+ XX_UnlockIntrSpinlock(p_FmPcd->h_Spinlock, intFlags); -+ -+ return p_Lock; -+} -+ -+static void EnqueueLockToAcquiredLst(t_FmPcd *p_FmPcd, t_FmPcdLock *p_Lock) -+{ -+ uint32_t intFlags; -+ -+ intFlags = XX_LockIntrSpinlock(p_FmPcd->h_Spinlock); -+ LIST_AddToTail(&p_Lock->node, &p_FmPcd->acquiredLocksLst); -+ XX_UnlockIntrSpinlock(p_FmPcd->h_Spinlock, intFlags); -+} -+ -+static t_Error FillFreeLocksLst(t_FmPcd *p_FmPcd) -+{ -+ t_FmPcdLock *p_Lock; -+ int i; -+ -+ for (i=0; i<10; i++) -+ { -+ p_Lock = (t_FmPcdLock *)XX_Malloc(sizeof(t_FmPcdLock)); -+ if (!p_Lock) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("FM-PCD lock obj!")); -+ memset(p_Lock, 0, sizeof(t_FmPcdLock)); -+ INIT_LIST(&p_Lock->node); -+ p_Lock->h_Spinlock = XX_InitSpinlock(); -+ if (!p_Lock->h_Spinlock) -+ { -+ XX_Free(p_Lock); -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("FM-PCD spinlock obj!")); -+ } -+ EnqueueLockToFreeLst(p_FmPcd, p_Lock); -+ } -+ -+ return E_OK; -+} -+ -+static void ReleaseFreeLocksLst(t_FmPcd *p_FmPcd) -+{ -+ t_FmPcdLock *p_Lock; -+ -+ p_Lock = DequeueLockFromFreeLst(p_FmPcd); -+ while (p_Lock) -+ { -+ XX_FreeSpinlock(p_Lock->h_Spinlock); -+ XX_Free(p_Lock); -+ p_Lock = DequeueLockFromFreeLst(p_FmPcd); -+ } -+} -+ -+ -+ -+/*****************************************************************************/ -+/* Inter-module API routines */ -+/*****************************************************************************/ -+ -+void FmPcdSetClsPlanGrpId(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint8_t clsPlanGrpId) -+{ -+ ASSERT_COND(p_FmPcd); -+ p_FmPcd->netEnvs[netEnvId].clsPlanGrpId = clsPlanGrpId; -+} -+ -+t_Error PcdGetClsPlanGrpParams(t_FmPcd *p_FmPcd, t_FmPcdKgInterModuleClsPlanGrpParams *p_GrpParams) -+{ -+ uint8_t netEnvId = p_GrpParams->netEnvId; -+ int i, k, j; -+ -+ ASSERT_COND(p_FmPcd); -+ if (p_FmPcd->netEnvs[netEnvId].clsPlanGrpId != ILLEGAL_CLS_PLAN) -+ { -+ p_GrpParams->grpExists = TRUE; -+ p_GrpParams->clsPlanGrpId = p_FmPcd->netEnvs[netEnvId].clsPlanGrpId; -+ return E_OK; -+ } -+ -+ for (i=0; ((i < FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS) && -+ (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[0].hdr != HEADER_TYPE_NONE)); i++) -+ { -+ for (k=0; ((k < FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS) && -+ (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[k].hdr != HEADER_TYPE_NONE)); k++) -+ { -+ /* if an option exists, add it to the opts list */ -+ if (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[k].opt) -+ { -+ /* check if this option already exists, add if it doesn't */ -+ for (j = 0;jnumOfOptions;j++) -+ { -+ if (p_GrpParams->options[j] == p_FmPcd->netEnvs[netEnvId].units[i].hdrs[k].opt) -+ break; -+ } -+ p_GrpParams->optVectors[j] |= p_FmPcd->netEnvs[netEnvId].unitsVectors[i]; -+ if (j == p_GrpParams->numOfOptions) -+ { -+ p_GrpParams->options[p_GrpParams->numOfOptions] = p_FmPcd->netEnvs[netEnvId].units[i].hdrs[k].opt; -+ p_GrpParams->numOfOptions++; -+ } -+ } -+ } -+ } -+ -+ if (p_GrpParams->numOfOptions == 0) -+ { -+ if (p_FmPcd->p_FmPcdKg->emptyClsPlanGrpId != ILLEGAL_CLS_PLAN) -+ { -+ p_GrpParams->grpExists = TRUE; -+ p_GrpParams->clsPlanGrpId = p_FmPcd->p_FmPcdKg->emptyClsPlanGrpId; -+ } -+ } -+ -+ return E_OK; -+ -+} -+ -+t_Error PcdGetVectorForOpt(t_FmPcd *p_FmPcd, uint8_t netEnvId, protocolOpt_t opt, uint32_t *p_Vector) -+{ -+ uint8_t j,k; -+ -+ *p_Vector = 0; -+ -+ ASSERT_COND(p_FmPcd); -+ for (j=0; ((j < FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS) && -+ (p_FmPcd->netEnvs[netEnvId].units[j].hdrs[0].hdr != HEADER_TYPE_NONE)); j++) -+ { -+ for (k=0; ((k < FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS) && -+ (p_FmPcd->netEnvs[netEnvId].units[j].hdrs[k].hdr != HEADER_TYPE_NONE)); k++) -+ { -+ if (p_FmPcd->netEnvs[netEnvId].units[j].hdrs[k].opt == opt) -+ *p_Vector |= p_FmPcd->netEnvs[netEnvId].unitsVectors[j]; -+ } -+ } -+ -+ if (!*p_Vector) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Requested option was not defined for this Network Environment Characteristics module")); -+ else -+ return E_OK; -+} -+ -+t_Error PcdGetUnitsVector(t_FmPcd *p_FmPcd, t_NetEnvParams *p_Params) -+{ -+ int i; -+ -+ ASSERT_COND(p_FmPcd); -+ ASSERT_COND(p_Params->netEnvId < FM_MAX_NUM_OF_PORTS); -+ -+ p_Params->vector = 0; -+ for (i=0; inumOfDistinctionUnits ;i++) -+ { -+ if (p_FmPcd->netEnvs[p_Params->netEnvId].units[p_Params->unitIds[i]].hdrs[0].hdr == HEADER_TYPE_NONE) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Requested unit was not defined for this Network Environment Characteristics module")); -+ ASSERT_COND(p_FmPcd->netEnvs[p_Params->netEnvId].unitsVectors[p_Params->unitIds[i]]); -+ p_Params->vector |= p_FmPcd->netEnvs[p_Params->netEnvId].unitsVectors[p_Params->unitIds[i]]; -+ } -+ -+ return E_OK; -+} -+ -+bool PcdNetEnvIsUnitWithoutOpts(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint32_t unitVector) -+{ -+ int i=0, k; -+ -+ ASSERT_COND(p_FmPcd); -+ /* check whether a given unit may be used by non-clsPlan users. */ -+ /* first, recognize the unit by its vector */ -+ while (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[0].hdr != HEADER_TYPE_NONE) -+ { -+ if (p_FmPcd->netEnvs[netEnvId].unitsVectors[i] == unitVector) -+ { -+ for (k=0; -+ ((k < FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS) && -+ (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[k].hdr != HEADER_TYPE_NONE)); -+ k++) -+ /* check that no option exists */ -+ if ((protocolOpt_t)p_FmPcd->netEnvs[netEnvId].units[i].hdrs[k].opt) -+ return FALSE; -+ break; -+ } -+ i++; -+ } -+ /* assert that a unit was found to mach the vector */ -+ ASSERT_COND(p_FmPcd->netEnvs[netEnvId].units[i].hdrs[0].hdr != HEADER_TYPE_NONE); -+ -+ return TRUE; -+} -+bool FmPcdNetEnvIsHdrExist(t_Handle h_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ int i, k; -+ -+ ASSERT_COND(p_FmPcd); -+ -+ for (i=0; ((i < FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS) && -+ (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[0].hdr != HEADER_TYPE_NONE)); i++) -+ { -+ for (k=0; ((k < FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS) && -+ (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[k].hdr != HEADER_TYPE_NONE)); k++) -+ if (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[k].hdr == hdr) -+ return TRUE; -+ } -+ for (i=0; ((i < FM_PCD_MAX_NUM_OF_ALIAS_HDRS) && -+ (p_FmPcd->netEnvs[netEnvId].aliasHdrs[i].hdr != HEADER_TYPE_NONE)); i++) -+ { -+ if (p_FmPcd->netEnvs[netEnvId].aliasHdrs[i].hdr == hdr) -+ return TRUE; -+ } -+ -+ return FALSE; -+} -+ -+uint8_t FmPcdNetEnvGetUnitId(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr, bool interchangeable, protocolOpt_t opt) -+{ -+ uint8_t i, k; -+ -+ ASSERT_COND(p_FmPcd); -+ -+ if (interchangeable) -+ { -+ for (i=0; (i < FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS) && -+ (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[0].hdr != HEADER_TYPE_NONE); i++) -+ { -+ for (k=0; (k < FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS) && -+ (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[k].hdr != HEADER_TYPE_NONE); k++) -+ { -+ if ((p_FmPcd->netEnvs[netEnvId].units[i].hdrs[k].hdr == hdr) && -+ (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[k].opt == opt)) -+ -+ return i; -+ } -+ } -+ } -+ else -+ { -+ for (i=0; (i < FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS) && -+ (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[0].hdr != HEADER_TYPE_NONE); i++) -+ if ((p_FmPcd->netEnvs[netEnvId].units[i].hdrs[0].hdr == hdr) && -+ (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[0].opt == opt) && -+ (p_FmPcd->netEnvs[netEnvId].units[i].hdrs[1].hdr == HEADER_TYPE_NONE)) -+ return i; -+ -+ for (i=0; (i < FM_PCD_MAX_NUM_OF_ALIAS_HDRS) && -+ (p_FmPcd->netEnvs[netEnvId].aliasHdrs[i].hdr != HEADER_TYPE_NONE); i++) -+ if ((p_FmPcd->netEnvs[netEnvId].aliasHdrs[i].hdr == hdr) && -+ (p_FmPcd->netEnvs[netEnvId].aliasHdrs[i].opt == opt)) -+ return p_FmPcd->netEnvs[netEnvId].aliasHdrs[i].aliasHdr; -+ } -+ -+ return FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS; -+} -+ -+t_Error FmPcdUnregisterReassmPort(t_Handle h_FmPcd, t_Handle h_ReasmCommonPramTbl) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_FmPcdCcReassmTimeoutParams ccReassmTimeoutParams = {0}; -+ uint8_t result; -+ t_Error err = E_OK; -+ -+ ASSERT_COND(p_FmPcd); -+ ASSERT_COND(h_ReasmCommonPramTbl); -+ -+ ccReassmTimeoutParams.iprcpt = (uint32_t)(XX_VirtToPhys(h_ReasmCommonPramTbl) - p_FmPcd->physicalMuramBase); -+ ccReassmTimeoutParams.activate = FALSE; /*Disable Timeout Task*/ -+ -+ if ((err = FmHcPcdCcTimeoutReassm(p_FmPcd->h_Hc, &ccReassmTimeoutParams, &result)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ switch (result) -+ { -+ case (0): -+ return E_OK; -+ case (1): -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("")); -+ case (2): -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("")); -+ case (3): -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("Disable Timeout Task with invalid IPRCPT")); -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); -+ } -+ -+ return E_OK; -+} -+ -+e_NetHeaderType FmPcdGetAliasHdr(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr) -+{ -+ int i; -+ -+ ASSERT_COND(p_FmPcd); -+ ASSERT_COND(netEnvId < FM_MAX_NUM_OF_PORTS); -+ -+ for (i=0; (i < FM_PCD_MAX_NUM_OF_ALIAS_HDRS) -+ && (p_FmPcd->netEnvs[netEnvId].aliasHdrs[i].hdr != HEADER_TYPE_NONE); i++) -+ { -+ if (p_FmPcd->netEnvs[netEnvId].aliasHdrs[i].hdr == hdr) -+ return p_FmPcd->netEnvs[netEnvId].aliasHdrs[i].aliasHdr; -+ } -+ -+ return HEADER_TYPE_NONE; -+} -+ -+void FmPcdPortRegister(t_Handle h_FmPcd, t_Handle h_FmPort, uint8_t hardwarePortId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint16_t swPortIndex = 0; -+ -+ ASSERT_COND(h_FmPcd); -+ HW_PORT_ID_TO_SW_PORT_INDX(swPortIndex, hardwarePortId); -+ p_FmPcd->p_FmPcdPlcr->portsMapping[swPortIndex].h_FmPort = h_FmPort; -+} -+ -+uint32_t FmPcdGetLcv(t_Handle h_FmPcd, uint32_t netEnvId, uint8_t hdrNum) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ ASSERT_COND(h_FmPcd); -+ return p_FmPcd->netEnvs[netEnvId].lcvs[hdrNum]; -+} -+ -+uint32_t FmPcdGetMacsecLcv(t_Handle h_FmPcd, uint32_t netEnvId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ ASSERT_COND(h_FmPcd); -+ return p_FmPcd->netEnvs[netEnvId].macsecVector; -+} -+ -+uint8_t FmPcdGetNetEnvId(t_Handle h_NetEnv) -+{ -+ return ((t_FmPcdNetEnv*)h_NetEnv)->netEnvId; -+} -+ -+void FmPcdIncNetEnvOwners(t_Handle h_FmPcd, uint8_t netEnvId) -+{ -+ uint32_t intFlags; -+ -+ ASSERT_COND(h_FmPcd); -+ -+ intFlags = NetEnvLock(&((t_FmPcd*)h_FmPcd)->netEnvs[netEnvId]); -+ ((t_FmPcd*)h_FmPcd)->netEnvs[netEnvId].owners++; -+ NetEnvUnlock(&((t_FmPcd*)h_FmPcd)->netEnvs[netEnvId], intFlags); -+} -+ -+void FmPcdDecNetEnvOwners(t_Handle h_FmPcd, uint8_t netEnvId) -+{ -+ uint32_t intFlags; -+ -+ ASSERT_COND(h_FmPcd); -+ ASSERT_COND(((t_FmPcd*)h_FmPcd)->netEnvs[netEnvId].owners); -+ -+ intFlags = NetEnvLock(&((t_FmPcd*)h_FmPcd)->netEnvs[netEnvId]); -+ ((t_FmPcd*)h_FmPcd)->netEnvs[netEnvId].owners--; -+ NetEnvUnlock(&((t_FmPcd*)h_FmPcd)->netEnvs[netEnvId], intFlags); -+} -+ -+uint32_t FmPcdLock(t_Handle h_FmPcd) -+{ -+ ASSERT_COND(h_FmPcd); -+ return XX_LockIntrSpinlock(((t_FmPcd*)h_FmPcd)->h_Spinlock); -+} -+ -+void FmPcdUnlock(t_Handle h_FmPcd, uint32_t intFlags) -+{ -+ ASSERT_COND(h_FmPcd); -+ XX_UnlockIntrSpinlock(((t_FmPcd*)h_FmPcd)->h_Spinlock, intFlags); -+} -+ -+t_FmPcdLock * FmPcdAcquireLock(t_Handle h_FmPcd) -+{ -+ t_FmPcdLock *p_Lock; -+ ASSERT_COND(h_FmPcd); -+ p_Lock = DequeueLockFromFreeLst((t_FmPcd*)h_FmPcd); -+ if (!p_Lock) -+ { -+ FillFreeLocksLst(h_FmPcd); -+ p_Lock = DequeueLockFromFreeLst((t_FmPcd*)h_FmPcd); -+ } -+ -+ if (p_Lock) -+ EnqueueLockToAcquiredLst((t_FmPcd*)h_FmPcd, p_Lock); -+ return p_Lock; -+} -+ -+void FmPcdReleaseLock(t_Handle h_FmPcd, t_FmPcdLock *p_Lock) -+{ -+ uint32_t intFlags; -+ ASSERT_COND(h_FmPcd); -+ intFlags = FmPcdLock(h_FmPcd); -+ LIST_DelAndInit(&p_Lock->node); -+ FmPcdUnlock(h_FmPcd, intFlags); -+ EnqueueLockToFreeLst((t_FmPcd*)h_FmPcd, p_Lock); -+} -+ -+bool FmPcdLockTryLockAll(t_Handle h_FmPcd) -+{ -+ uint32_t intFlags; -+ t_List *p_Pos, *p_SavedPos=NULL; -+ -+ ASSERT_COND(h_FmPcd); -+ intFlags = FmPcdLock(h_FmPcd); -+ LIST_FOR_EACH(p_Pos, &((t_FmPcd*)h_FmPcd)->acquiredLocksLst) -+ { -+ t_FmPcdLock *p_Lock = FM_PCD_LOCK_OBJ(p_Pos); -+ if (!FmPcdLockTryLock(p_Lock)) -+ { -+ p_SavedPos = p_Pos; -+ break; -+ } -+ } -+ if (p_SavedPos) -+ { -+ LIST_FOR_EACH(p_Pos, &((t_FmPcd*)h_FmPcd)->acquiredLocksLst) -+ { -+ t_FmPcdLock *p_Lock = FM_PCD_LOCK_OBJ(p_Pos); -+ if (p_Pos == p_SavedPos) -+ break; -+ FmPcdLockUnlock(p_Lock); -+ } -+ } -+ FmPcdUnlock(h_FmPcd, intFlags); -+ -+ CORE_MemoryBarrier(); -+ -+ if (p_SavedPos) -+ return FALSE; -+ -+ return TRUE; -+} -+ -+void FmPcdLockUnlockAll(t_Handle h_FmPcd) -+{ -+ uint32_t intFlags; -+ t_List *p_Pos; -+ -+ ASSERT_COND(h_FmPcd); -+ intFlags = FmPcdLock(h_FmPcd); -+ LIST_FOR_EACH(p_Pos, &((t_FmPcd*)h_FmPcd)->acquiredLocksLst) -+ { -+ t_FmPcdLock *p_Lock = FM_PCD_LOCK_OBJ(p_Pos); -+ p_Lock->flag = FALSE; -+ } -+ FmPcdUnlock(h_FmPcd, intFlags); -+ -+ CORE_MemoryBarrier(); -+} -+ -+t_Error FmPcdHcSync(t_Handle h_FmPcd) -+{ -+ ASSERT_COND(h_FmPcd); -+ ASSERT_COND(((t_FmPcd*)h_FmPcd)->h_Hc); -+ -+ return FmHcPcdSync(((t_FmPcd*)h_FmPcd)->h_Hc); -+} -+ -+t_Handle FmPcdGetHcHandle(t_Handle h_FmPcd) -+{ -+ ASSERT_COND(h_FmPcd); -+ return ((t_FmPcd*)h_FmPcd)->h_Hc; -+} -+ -+bool FmPcdIsAdvancedOffloadSupported(t_Handle h_FmPcd) -+{ -+ ASSERT_COND(h_FmPcd); -+ return ((t_FmPcd*)h_FmPcd)->advancedOffloadSupport; -+} -+/*********************** End of inter-module routines ************************/ -+ -+ -+/****************************************/ -+/* API Init unit functions */ -+/****************************************/ -+ -+t_Handle FM_PCD_Config(t_FmPcdParams *p_FmPcdParams) -+{ -+ t_FmPcd *p_FmPcd = NULL; -+ t_FmPhysAddr physicalMuramBase; -+ uint8_t i; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPcdParams, E_INVALID_HANDLE,NULL); -+ -+ p_FmPcd = (t_FmPcd *) XX_Malloc(sizeof(t_FmPcd)); -+ if (!p_FmPcd) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM PCD")); -+ return NULL; -+ } -+ memset(p_FmPcd, 0, sizeof(t_FmPcd)); -+ -+ p_FmPcd->p_FmPcdDriverParam = (t_FmPcdDriverParam *) XX_Malloc(sizeof(t_FmPcdDriverParam)); -+ if (!p_FmPcd->p_FmPcdDriverParam) -+ { -+ XX_Free(p_FmPcd); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM PCD Driver Param")); -+ return NULL; -+ } -+ memset(p_FmPcd->p_FmPcdDriverParam, 0, sizeof(t_FmPcdDriverParam)); -+ -+ p_FmPcd->h_Fm = p_FmPcdParams->h_Fm; -+ p_FmPcd->guestId = FmGetGuestId(p_FmPcd->h_Fm); -+ p_FmPcd->h_FmMuram = FmGetMuramHandle(p_FmPcd->h_Fm); -+ if (p_FmPcd->h_FmMuram) -+ { -+ FmGetPhysicalMuramBase(p_FmPcdParams->h_Fm, &physicalMuramBase); -+ p_FmPcd->physicalMuramBase = (uint64_t)((uint64_t)(&physicalMuramBase)->low | ((uint64_t)(&physicalMuramBase)->high << 32)); -+ } -+ -+ for (i = 0; inetEnvs[i].clsPlanGrpId = ILLEGAL_CLS_PLAN; -+ -+ if (p_FmPcdParams->useHostCommand) -+ { -+ t_FmHcParams hcParams; -+ -+ memset(&hcParams, 0, sizeof(hcParams)); -+ hcParams.h_Fm = p_FmPcd->h_Fm; -+ hcParams.h_FmPcd = (t_Handle)p_FmPcd; -+ memcpy((uint8_t*)&hcParams.params, (uint8_t*)&p_FmPcdParams->hc, sizeof(t_FmPcdHcParams)); -+ p_FmPcd->h_Hc = FmHcConfigAndInit(&hcParams); -+ if (!p_FmPcd->h_Hc) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM PCD HC")); -+ FM_PCD_Free(p_FmPcd); -+ return NULL; -+ } -+ } -+ else if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("No Host Command defined for a guest partition.")); -+ -+ if (p_FmPcdParams->kgSupport) -+ { -+ p_FmPcd->p_FmPcdKg = (t_FmPcdKg *)KgConfig(p_FmPcd, p_FmPcdParams); -+ if (!p_FmPcd->p_FmPcdKg) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM PCD Keygen")); -+ FM_PCD_Free(p_FmPcd); -+ return NULL; -+ } -+ } -+ -+ if (p_FmPcdParams->plcrSupport) -+ { -+ p_FmPcd->p_FmPcdPlcr = (t_FmPcdPlcr *)PlcrConfig(p_FmPcd, p_FmPcdParams); -+ if (!p_FmPcd->p_FmPcdPlcr) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM PCD Policer")); -+ FM_PCD_Free(p_FmPcd); -+ return NULL; -+ } -+ } -+ -+ if (p_FmPcdParams->prsSupport) -+ { -+ p_FmPcd->p_FmPcdPrs = (t_FmPcdPrs *)PrsConfig(p_FmPcd, p_FmPcdParams); -+ if (!p_FmPcd->p_FmPcdPrs) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM PCD Parser")); -+ FM_PCD_Free(p_FmPcd); -+ return NULL; -+ } -+ } -+ -+ p_FmPcd->h_Spinlock = XX_InitSpinlock(); -+ if (!p_FmPcd->h_Spinlock) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM PCD spinlock")); -+ FM_PCD_Free(p_FmPcd); -+ return NULL; -+ } -+ INIT_LIST(&p_FmPcd->freeLocksLst); -+ INIT_LIST(&p_FmPcd->acquiredLocksLst); -+ -+ p_FmPcd->numOfEnabledGuestPartitionsPcds = 0; -+ -+ p_FmPcd->f_Exception = p_FmPcdParams->f_Exception; -+ p_FmPcd->f_FmPcdIndexedException = p_FmPcdParams->f_ExceptionId; -+ p_FmPcd->h_App = p_FmPcdParams->h_App; -+ -+ p_FmPcd->p_CcShadow = NULL; -+ p_FmPcd->ccShadowSize = 0; -+ p_FmPcd->ccShadowAlign = 0; -+ -+ p_FmPcd->h_ShadowSpinlock = XX_InitSpinlock(); -+ if (!p_FmPcd->h_ShadowSpinlock) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM PCD shadow spinlock")); -+ FM_PCD_Free(p_FmPcd); -+ return NULL; -+ } -+ -+ return p_FmPcd; -+} -+ -+t_Error FM_PCD_Init(t_Handle h_FmPcd) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_Error err = E_OK; -+ t_FmPcdIpcMsg msg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdDriverParam, E_INVALID_HANDLE); -+ -+ FM_GetRevision(p_FmPcd->h_Fm, &p_FmPcd->fmRevInfo); -+ -+ if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ { -+ memset(p_FmPcd->fmPcdIpcHandlerModuleName, 0, (sizeof(char)) * MODULE_NAME_SIZE); -+ if (Sprint (p_FmPcd->fmPcdIpcHandlerModuleName, "FM_PCD_%d_%d", FmGetId(p_FmPcd->h_Fm), NCSW_MASTER_ID) != 10) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Sprint failed")); -+ memset(p_FmPcd->fmPcdModuleName, 0, (sizeof(char)) * MODULE_NAME_SIZE); -+ if (Sprint (p_FmPcd->fmPcdModuleName, "FM_PCD_%d_%d",FmGetId(p_FmPcd->h_Fm), p_FmPcd->guestId) != (p_FmPcd->guestId<10 ? 10:11)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Sprint failed")); -+ -+ p_FmPcd->h_IpcSession = XX_IpcInitSession(p_FmPcd->fmPcdIpcHandlerModuleName, p_FmPcd->fmPcdModuleName); -+ if (p_FmPcd->h_IpcSession) -+ { -+ t_FmPcdIpcReply reply; -+ uint32_t replyLength; -+ uint8_t isMasterAlive = 0; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_PCD_MASTER_IS_ALIVE; -+ msg.msgBody[0] = p_FmPcd->guestId; -+ blockingFlag = TRUE; -+ -+ do -+ { -+ replyLength = sizeof(uint32_t) + sizeof(isMasterAlive); -+ if ((err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId)+sizeof(p_FmPcd->guestId), -+ (uint8_t*)&reply, -+ &replyLength, -+ IpcMsgCompletionCB, -+ h_FmPcd)) != E_OK) -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ while (blockingFlag) ; -+ if (replyLength != (sizeof(uint32_t) + sizeof(isMasterAlive))) -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ isMasterAlive = *(uint8_t*)(reply.replyBody); -+ } while (!isMasterAlive); -+ } -+ } -+ -+ CHECK_INIT_PARAMETERS(p_FmPcd, CheckFmPcdParameters); -+ -+ if (p_FmPcd->p_FmPcdKg) -+ { -+ err = KgInit(p_FmPcd); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ if (p_FmPcd->p_FmPcdPlcr) -+ { -+ err = PlcrInit(p_FmPcd); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ if (p_FmPcd->p_FmPcdPrs) -+ { -+ err = PrsInit(p_FmPcd); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ if (p_FmPcd->guestId == NCSW_MASTER_ID) -+ { -+ /* register to inter-core messaging mechanism */ -+ memset(p_FmPcd->fmPcdModuleName, 0, (sizeof(char)) * MODULE_NAME_SIZE); -+ if (Sprint (p_FmPcd->fmPcdModuleName, "FM_PCD_%d_%d",FmGetId(p_FmPcd->h_Fm),NCSW_MASTER_ID) != 10) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Sprint failed")); -+ err = XX_IpcRegisterMsgHandler(p_FmPcd->fmPcdModuleName, IpcMsgHandlerCB, p_FmPcd, FM_PCD_MAX_REPLY_SIZE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ /* IPv6 Frame-Id used for fragmentation */ -+ p_FmPcd->ipv6FrameIdAddr = PTR_TO_UINT(FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, 4, 4)); -+ if (!p_FmPcd->ipv6FrameIdAddr) -+ { -+ FM_PCD_Free(p_FmPcd); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM allocation for IPv6 Frame-Id")); -+ } -+ IOMemSet32(UINT_TO_PTR(p_FmPcd->ipv6FrameIdAddr), 0, 4); -+ -+ /* CAPWAP Frame-Id used for fragmentation */ -+ p_FmPcd->capwapFrameIdAddr = PTR_TO_UINT(FM_MURAM_AllocMem(p_FmPcd->h_FmMuram, 2, 4)); -+ if (!p_FmPcd->capwapFrameIdAddr) -+ { -+ FM_PCD_Free(p_FmPcd); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM allocation for CAPWAP Frame-Id")); -+ } -+ IOMemSet32(UINT_TO_PTR(p_FmPcd->capwapFrameIdAddr), 0, 2); -+ -+ XX_Free(p_FmPcd->p_FmPcdDriverParam); -+ p_FmPcd->p_FmPcdDriverParam = NULL; -+ -+ FmRegisterPcd(p_FmPcd->h_Fm, p_FmPcd); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_Free(t_Handle h_FmPcd) -+{ -+ t_FmPcd *p_FmPcd =(t_FmPcd *)h_FmPcd; -+ t_Error err = E_OK; -+ -+ if (p_FmPcd->ipv6FrameIdAddr) -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, UINT_TO_PTR(p_FmPcd->ipv6FrameIdAddr)); -+ -+ if (p_FmPcd->capwapFrameIdAddr) -+ FM_MURAM_FreeMem(p_FmPcd->h_FmMuram, UINT_TO_PTR(p_FmPcd->capwapFrameIdAddr)); -+ -+ if (p_FmPcd->enabled) -+ FM_PCD_Disable(p_FmPcd); -+ -+ if (p_FmPcd->p_FmPcdDriverParam) -+ { -+ XX_Free(p_FmPcd->p_FmPcdDriverParam); -+ p_FmPcd->p_FmPcdDriverParam = NULL; -+ } -+ -+ if (p_FmPcd->p_FmPcdKg) -+ { -+ if ((err = KgFree(p_FmPcd)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ XX_Free(p_FmPcd->p_FmPcdKg); -+ p_FmPcd->p_FmPcdKg = NULL; -+ } -+ -+ if (p_FmPcd->p_FmPcdPlcr) -+ { -+ PlcrFree(p_FmPcd); -+ XX_Free(p_FmPcd->p_FmPcdPlcr); -+ p_FmPcd->p_FmPcdPlcr = NULL; -+ } -+ -+ if (p_FmPcd->p_FmPcdPrs) -+ { -+ if (p_FmPcd->guestId == NCSW_MASTER_ID) -+ PrsFree(p_FmPcd); -+ XX_Free(p_FmPcd->p_FmPcdPrs); -+ p_FmPcd->p_FmPcdPrs = NULL; -+ } -+ -+ if (p_FmPcd->h_Hc) -+ { -+ FmHcFree(p_FmPcd->h_Hc); -+ p_FmPcd->h_Hc = NULL; -+ } -+ -+ XX_IpcUnregisterMsgHandler(p_FmPcd->fmPcdModuleName); -+ -+ FmUnregisterPcd(p_FmPcd->h_Fm); -+ -+ ReleaseFreeLocksLst(p_FmPcd); -+ -+ if (p_FmPcd->h_Spinlock) -+ XX_FreeSpinlock(p_FmPcd->h_Spinlock); -+ -+ if (p_FmPcd->h_ShadowSpinlock) -+ XX_FreeSpinlock(p_FmPcd->h_ShadowSpinlock); -+ -+ XX_Free(p_FmPcd); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_ConfigException(t_Handle h_FmPcd, e_FmPcdExceptions exception, bool enable) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint32_t bitMask = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ -+ if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_ConfigException - guest mode!")); -+ -+ GET_FM_PCD_EXCEPTION_FLAG(bitMask, exception); -+ if (bitMask) -+ { -+ if (enable) -+ p_FmPcd->exceptions |= bitMask; -+ else -+ p_FmPcd->exceptions &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_ConfigHcFramesDataMemory(t_Handle h_FmPcd, uint8_t memId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->h_Hc, E_INVALID_HANDLE); -+ -+ return FmHcSetFramesDataMemory(p_FmPcd->h_Hc, memId); -+} -+ -+t_Error FM_PCD_Enable(t_Handle h_FmPcd) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_HANDLE); -+ -+ if (p_FmPcd->enabled) -+ return E_OK; -+ -+ if ((p_FmPcd->guestId != NCSW_MASTER_ID) && -+ p_FmPcd->h_IpcSession) -+ { -+ uint8_t enabled; -+ t_FmPcdIpcMsg msg; -+ t_FmPcdIpcReply reply; -+ uint32_t replyLength; -+ -+ memset(&reply, 0, sizeof(reply)); -+ memset(&msg, 0, sizeof(msg)); -+ msg.msgId = FM_PCD_MASTER_IS_ENABLED; -+ replyLength = sizeof(uint32_t) + sizeof(enabled); -+ if ((err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ if (replyLength != sizeof(uint32_t) + sizeof(enabled)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ p_FmPcd->enabled = (bool)!!(*(uint8_t*)(reply.replyBody)); -+ if (!p_FmPcd->enabled) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("FM-PCD master should be enabled first!")); -+ -+ return E_OK; -+ } -+ else if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without IPC!")); -+ -+ if (p_FmPcd->p_FmPcdKg) -+ KgEnable(p_FmPcd); -+ -+ if (p_FmPcd->p_FmPcdPlcr) -+ PlcrEnable(p_FmPcd); -+ -+ if (p_FmPcd->p_FmPcdPrs) -+ PrsEnable(p_FmPcd); -+ -+ p_FmPcd->enabled = TRUE; -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_Disable(t_Handle h_FmPcd) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_HANDLE); -+ -+ if (!p_FmPcd->enabled) -+ return E_OK; -+ -+ if ((p_FmPcd->guestId != NCSW_MASTER_ID) && -+ p_FmPcd->h_IpcSession) -+ { -+ t_FmPcdIpcMsg msg; -+ t_FmPcdIpcReply reply; -+ uint32_t replyLength; -+ -+ memset(&reply, 0, sizeof(reply)); -+ memset(&msg, 0, sizeof(msg)); -+ msg.msgId = FM_PCD_GUEST_DISABLE; -+ replyLength = sizeof(uint32_t); -+ if ((err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ if (replyLength != sizeof(uint32_t)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ if (reply.error == E_OK) -+ p_FmPcd->enabled = FALSE; -+ -+ return (t_Error)(reply.error); -+ } -+ else if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without IPC!")); -+ -+ if (p_FmPcd->numOfEnabledGuestPartitionsPcds != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("Trying to disable a master partition PCD while" -+ "guest partitions are still enabled!")); -+ -+ if (p_FmPcd->p_FmPcdKg) -+ KgDisable(p_FmPcd); -+ -+ if (p_FmPcd->p_FmPcdPlcr) -+ PlcrDisable(p_FmPcd); -+ -+ if (p_FmPcd->p_FmPcdPrs) -+ PrsDisable(p_FmPcd); -+ -+ p_FmPcd->enabled = FALSE; -+ -+ return E_OK; -+} -+ -+t_Handle FM_PCD_NetEnvCharacteristicsSet(t_Handle h_FmPcd, t_FmPcdNetEnvParams *p_NetEnvParams) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint32_t intFlags, specialUnits = 0; -+ uint8_t bitId = 0; -+ uint8_t i, j, k; -+ uint8_t netEnvCurrId; -+ uint8_t ipsecAhUnit = 0,ipsecEspUnit = 0; -+ bool ipsecAhExists = FALSE, ipsecEspExists = FALSE, shim1Selected = FALSE; -+ uint8_t hdrNum; -+ t_FmPcdNetEnvParams *p_ModifiedNetEnvParams; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_STATE, NULL); -+ SANITY_CHECK_RETURN_VALUE(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE, NULL); -+ SANITY_CHECK_RETURN_VALUE(p_NetEnvParams, E_NULL_POINTER, NULL); -+ -+ intFlags = FmPcdLock(p_FmPcd); -+ -+ /* find a new netEnv */ -+ for (i = 0; i < FM_MAX_NUM_OF_PORTS; i++) -+ if (!p_FmPcd->netEnvs[i].used) -+ break; -+ -+ if (i== FM_MAX_NUM_OF_PORTS) -+ { -+ REPORT_ERROR(MAJOR, E_FULL,("No more than %d netEnv's allowed.", FM_MAX_NUM_OF_PORTS)); -+ FmPcdUnlock(p_FmPcd, intFlags); -+ return NULL; -+ } -+ -+ p_FmPcd->netEnvs[i].used = TRUE; -+ FmPcdUnlock(p_FmPcd, intFlags); -+ -+ /* As anyone doesn't have handle of this netEnv yet, no need -+ to protect it with spinlocks */ -+ -+ p_ModifiedNetEnvParams = (t_FmPcdNetEnvParams *)XX_Malloc(sizeof(t_FmPcdNetEnvParams)); -+ if (!p_ModifiedNetEnvParams) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FmPcdNetEnvParams")); -+ return NULL; -+ } -+ -+ memcpy(p_ModifiedNetEnvParams, p_NetEnvParams, sizeof(t_FmPcdNetEnvParams)); -+ p_NetEnvParams = p_ModifiedNetEnvParams; -+ -+ netEnvCurrId = (uint8_t)i; -+ -+ /* clear from previous use */ -+ memset(&p_FmPcd->netEnvs[netEnvCurrId].units, 0, FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS * sizeof(t_FmPcdIntDistinctionUnit)); -+ memset(&p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs, 0, FM_PCD_MAX_NUM_OF_ALIAS_HDRS * sizeof(t_FmPcdNetEnvAliases)); -+ memcpy(&p_FmPcd->netEnvs[netEnvCurrId].units, p_NetEnvParams->units, p_NetEnvParams->numOfDistinctionUnits*sizeof(t_FmPcdIntDistinctionUnit)); -+ -+ p_FmPcd->netEnvs[netEnvCurrId].netEnvId = netEnvCurrId; -+ p_FmPcd->netEnvs[netEnvCurrId].h_FmPcd = p_FmPcd; -+ -+ p_FmPcd->netEnvs[netEnvCurrId].clsPlanGrpId = ILLEGAL_CLS_PLAN; -+ -+ /* check that header with opt is not interchanged with the same header */ -+ for (i = 0; (i < FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS) -+ && (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[0].hdr != HEADER_TYPE_NONE); i++) -+ { -+ for (k = 0; (k < FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS) -+ && (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr != HEADER_TYPE_NONE); k++) -+ { -+ /* if an option exists, check that other headers are not the same header -+ without option */ -+ if (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].opt) -+ { -+ for (j = 0; (j < FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS) -+ && (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[j].hdr != HEADER_TYPE_NONE); j++) -+ { -+ if ((p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[j].hdr == p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr) && -+ !p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[j].opt) -+ { -+ REPORT_ERROR(MINOR, E_FULL, -+ ("Illegal unit - header with opt may not be interchangeable with the same header without opt")); -+ XX_Free(p_ModifiedNetEnvParams); -+ return NULL; -+ } -+ } -+ } -+ } -+ } -+ -+ /* Specific headers checking */ -+ for (i = 0; (i < FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS) -+ && (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[0].hdr != HEADER_TYPE_NONE); i++) -+ { -+ for (k = 0; (k < FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS) -+ && (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr != HEADER_TYPE_NONE); k++) -+ { -+ /* Some headers pairs may not be defined on different units as the parser -+ doesn't distinguish */ -+ /* IPSEC_AH and IPSEC_SPI can't be 2 units, */ -+ /* check that header with opt is not interchanged with the same header */ -+ if (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr == HEADER_TYPE_IPSEC_AH) -+ { -+ if (ipsecEspExists && (ipsecEspUnit != i)) -+ { -+ REPORT_ERROR(MINOR, E_INVALID_STATE, ("HEADER_TYPE_IPSEC_AH and HEADER_TYPE_IPSEC_ESP may not be defined in separate units")); -+ XX_Free(p_ModifiedNetEnvParams); -+ return NULL; -+ } -+ else -+ { -+ ipsecAhUnit = i; -+ ipsecAhExists = TRUE; -+ } -+ } -+ if (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr == HEADER_TYPE_IPSEC_ESP) -+ { -+ if (ipsecAhExists && (ipsecAhUnit != i)) -+ { -+ REPORT_ERROR(MINOR, E_INVALID_STATE, ("HEADER_TYPE_IPSEC_AH and HEADER_TYPE_IPSEC_ESP may not be defined in separate units")); -+ XX_Free(p_ModifiedNetEnvParams); -+ return NULL; -+ } -+ else -+ { -+ ipsecEspUnit = i; -+ ipsecEspExists = TRUE; -+ } -+ } -+ /* ENCAP_ESP */ -+ if (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr == HEADER_TYPE_UDP_ENCAP_ESP) -+ { -+ /* IPSec UDP encapsulation is currently set to use SHIM1 */ -+ p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs[specialUnits].hdr = HEADER_TYPE_UDP_ENCAP_ESP; -+ p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs[specialUnits++].aliasHdr = HEADER_TYPE_USER_DEFINED_SHIM1; -+ p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr = HEADER_TYPE_USER_DEFINED_SHIM1; -+ p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].opt = 0; -+ } -+#if (DPAA_VERSION >= 11) || ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+ /* UDP_LITE */ -+ if (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr == HEADER_TYPE_UDP_LITE) -+ { -+ p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs[specialUnits].hdr = HEADER_TYPE_UDP_LITE; -+ p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs[specialUnits++].aliasHdr = HEADER_TYPE_UDP; -+ p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr = HEADER_TYPE_UDP; -+ p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].opt = 0; -+ } -+#endif /* (DPAA_VERSION >= 11) || ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+ -+ /* IP FRAG */ -+ if ((p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr == HEADER_TYPE_IPv4) && -+ (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].opt == IPV4_FRAG_1)) -+ { -+ /* If IPv4+Frag, we need to set 2 units - SHIM 2 and IPv4. We first set SHIM2, and than check if -+ * IPv4 exists. If so we don't need to set an extra unit -+ * We consider as "having IPv4" any IPv4 without interchangable headers -+ * but including any options. */ -+ p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs[specialUnits].hdr = HEADER_TYPE_IPv4; -+ p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs[specialUnits].opt = IPV4_FRAG_1; -+ p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs[specialUnits++].aliasHdr = HEADER_TYPE_USER_DEFINED_SHIM2; -+ p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr = HEADER_TYPE_USER_DEFINED_SHIM2; -+ p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].opt = 0; -+ -+ /* check if IPv4 header exists by itself */ -+ if (FmPcdNetEnvGetUnitId(p_FmPcd, netEnvCurrId, HEADER_TYPE_IPv4, FALSE, 0) == FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS) -+ { -+ p_FmPcd->netEnvs[netEnvCurrId].units[p_NetEnvParams->numOfDistinctionUnits].hdrs[0].hdr = HEADER_TYPE_IPv4; -+ p_FmPcd->netEnvs[netEnvCurrId].units[p_NetEnvParams->numOfDistinctionUnits++].hdrs[0].opt = 0; -+ } -+ } -+ if ((p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr == HEADER_TYPE_IPv6) && -+ (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].opt == IPV6_FRAG_1)) -+ { -+ /* If IPv6+Frag, we need to set 2 units - SHIM 2 and IPv6. We first set SHIM2, and than check if -+ * IPv4 exists. If so we don't need to set an extra unit -+ * We consider as "having IPv6" any IPv6 without interchangable headers -+ * but including any options. */ -+ p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs[specialUnits].hdr = HEADER_TYPE_IPv6; -+ p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs[specialUnits].opt = IPV6_FRAG_1; -+ p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs[specialUnits++].aliasHdr = HEADER_TYPE_USER_DEFINED_SHIM2; -+ p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr = HEADER_TYPE_USER_DEFINED_SHIM2; -+ p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].opt = 0; -+ -+ /* check if IPv6 header exists by itself */ -+ if (FmPcdNetEnvGetUnitId(p_FmPcd, netEnvCurrId, HEADER_TYPE_IPv6, FALSE, 0) == FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS) -+ { -+ p_FmPcd->netEnvs[netEnvCurrId].units[p_NetEnvParams->numOfDistinctionUnits].hdrs[0].hdr = HEADER_TYPE_IPv6; -+ p_FmPcd->netEnvs[netEnvCurrId].units[p_NetEnvParams->numOfDistinctionUnits++].hdrs[0].opt = 0; -+ } -+ } -+#if (DPAA_VERSION >= 11) -+ /* CAPWAP FRAG */ -+ if ((p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr == HEADER_TYPE_CAPWAP) && -+ (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].opt == CAPWAP_FRAG_1)) -+ { -+ p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs[specialUnits].hdr = HEADER_TYPE_CAPWAP; -+ p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs[specialUnits].opt = CAPWAP_FRAG_1; -+ p_FmPcd->netEnvs[netEnvCurrId].aliasHdrs[specialUnits++].aliasHdr = HEADER_TYPE_USER_DEFINED_SHIM2; -+ p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr = HEADER_TYPE_USER_DEFINED_SHIM2; -+ p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].opt = 0; -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ } -+ -+ /* if private header (shim), check that no other headers specified */ -+ for (i = 0; (i < FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS) -+ && (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[0].hdr != HEADER_TYPE_NONE); i++) -+ { -+ if (IS_PRIVATE_HEADER(p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[0].hdr)) -+ if (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[1].hdr != HEADER_TYPE_NONE) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("SHIM header may not be interchanged with other headers")); -+ XX_Free(p_ModifiedNetEnvParams); -+ return NULL; -+ } -+ } -+ -+ for (i = 0; i < p_NetEnvParams->numOfDistinctionUnits; i++) -+ { -+ if (IS_PRIVATE_HEADER(p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[0].hdr)) -+ switch (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[0].hdr) -+ { -+ case (HEADER_TYPE_USER_DEFINED_SHIM1): -+ if (shim1Selected) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("SHIM header cannot be selected with UDP_IPSEC_ESP")); -+ XX_Free(p_ModifiedNetEnvParams); -+ return NULL; -+ } -+ shim1Selected = TRUE; -+ p_FmPcd->netEnvs[netEnvCurrId].unitsVectors[i] = 0x00000001; -+ break; -+ case (HEADER_TYPE_USER_DEFINED_SHIM2): -+ p_FmPcd->netEnvs[netEnvCurrId].unitsVectors[i] = 0x00000002; -+ break; -+ default: -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Requested SHIM not supported")); -+ } -+ else -+ { -+ p_FmPcd->netEnvs[netEnvCurrId].unitsVectors[i] = (uint32_t)(0x80000000 >> bitId++); -+ -+ if (IS_SPECIAL_HEADER(p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[0].hdr)) -+ p_FmPcd->netEnvs[netEnvCurrId].macsecVector = p_FmPcd->netEnvs[netEnvCurrId].unitsVectors[i]; -+ } -+ } -+ -+ /* define a set of hardware parser LCV's according to the defined netenv */ -+ -+ /* set an array of LCV's for each header in the netEnv */ -+ for (i = 0; (i < FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS) -+ && (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[0].hdr != HEADER_TYPE_NONE); i++) -+ { -+ /* private headers have no LCV in the hard parser */ -+ if (!IS_PRIVATE_HEADER(p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[0].hdr)) -+ { -+ for (k = 0; (k < FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS) -+ && (p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr != HEADER_TYPE_NONE); k++) -+ { -+ hdrNum = GetPrsHdrNum(p_FmPcd->netEnvs[netEnvCurrId].units[i].hdrs[k].hdr); -+ if ((hdrNum == ILLEGAL_HDR_NUM) || (hdrNum == NO_HDR_NUM)) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, NO_MSG); -+ XX_Free(p_ModifiedNetEnvParams); -+ return NULL; -+ } -+ p_FmPcd->netEnvs[netEnvCurrId].lcvs[hdrNum] |= p_FmPcd->netEnvs[netEnvCurrId].unitsVectors[i]; -+ } -+ } -+ } -+ XX_Free(p_ModifiedNetEnvParams); -+ -+ p_FmPcd->netEnvs[netEnvCurrId].h_Spinlock = XX_InitSpinlock(); -+ if (!p_FmPcd->netEnvs[netEnvCurrId].h_Spinlock) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM Pcd NetEnv spinlock")); -+ return NULL; -+ } -+ return &p_FmPcd->netEnvs[netEnvCurrId]; -+} -+ -+t_Error FM_PCD_NetEnvCharacteristicsDelete(t_Handle h_NetEnv) -+{ -+ t_FmPcdNetEnv *p_NetEnv = (t_FmPcdNetEnv*)h_NetEnv; -+ t_FmPcd *p_FmPcd = p_NetEnv->h_FmPcd; -+ uint32_t intFlags; -+ uint8_t netEnvId = p_NetEnv->netEnvId; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE); -+ -+ /* check that no port is bound to this netEnv */ -+ if (p_FmPcd->netEnvs[netEnvId].owners) -+ { -+ RETURN_ERROR(MINOR, E_INVALID_STATE, -+ ("Trying to delete a netEnv that has ports/schemes/trees/clsPlanGrps bound to")); -+ } -+ -+ intFlags = FmPcdLock(p_FmPcd); -+ -+ p_FmPcd->netEnvs[netEnvId].used = FALSE; -+ p_FmPcd->netEnvs[netEnvId].clsPlanGrpId = ILLEGAL_CLS_PLAN; -+ -+ memset(p_FmPcd->netEnvs[netEnvId].units, 0, sizeof(t_FmPcdIntDistinctionUnit)*FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS); -+ memset(p_FmPcd->netEnvs[netEnvId].unitsVectors, 0, sizeof(uint32_t)*FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS); -+ memset(p_FmPcd->netEnvs[netEnvId].lcvs, 0, sizeof(uint32_t)*FM_PCD_PRS_NUM_OF_HDRS); -+ -+ if (p_FmPcd->netEnvs[netEnvId].h_Spinlock) -+ XX_FreeSpinlock(p_FmPcd->netEnvs[netEnvId].h_Spinlock); -+ -+ FmPcdUnlock(p_FmPcd, intFlags); -+ return E_OK; -+} -+ -+void FM_PCD_HcTxConf(t_Handle h_FmPcd, t_DpaaFD *p_Fd) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ SANITY_CHECK_RETURN(h_FmPcd, E_INVALID_STATE); -+ -+ FmHcTxConf(p_FmPcd->h_Hc, p_Fd); -+} -+ -+t_Error FM_PCD_SetAdvancedOffloadSupport(t_Handle h_FmPcd) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_FmCtrlCodeRevisionInfo revInfo; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPcd->enabled, E_INVALID_STATE); -+ -+ if ((err = FM_GetFmanCtrlCodeRevision(p_FmPcd->h_Fm, &revInfo)) != E_OK) -+ { -+ DBG(WARNING, ("FM in guest-mode without IPC, can't validate firmware revision.")); -+ revInfo.packageRev = IP_OFFLOAD_PACKAGE_NUMBER; -+ } -+ if (!IS_OFFLOAD_PACKAGE(revInfo.packageRev)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Fman ctrl code package")); -+ -+ if (!p_FmPcd->h_Hc) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("HC must be initialized in this mode")); -+ -+ p_FmPcd->advancedOffloadSupport = TRUE; -+ -+ return E_OK; -+} -+ -+uint32_t FM_PCD_GetCounter(t_Handle h_FmPcd, e_FmPcdCounters counter) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint32_t outCounter = 0; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_VALUE(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE, 0); -+ -+ switch (counter) -+ { -+ case (e_FM_PCD_KG_COUNTERS_TOTAL): -+ if (!p_FmPcd->p_FmPcdKg) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("KeyGen is not activated")); -+ return 0; -+ } -+ if ((p_FmPcd->guestId != NCSW_MASTER_ID) && -+ !p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs && -+ !p_FmPcd->h_IpcSession) -+ { -+ REPORT_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without neither IPC nor mapped register!")); -+ return 0; -+ } -+ break; -+ -+ case (e_FM_PCD_PLCR_COUNTERS_YELLOW): -+ case (e_FM_PCD_PLCR_COUNTERS_RED): -+ case (e_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_RED): -+ case (e_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_YELLOW): -+ case (e_FM_PCD_PLCR_COUNTERS_TOTAL): -+ case (e_FM_PCD_PLCR_COUNTERS_LENGTH_MISMATCH): -+ if (!p_FmPcd->p_FmPcdPlcr) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Policer is not activated")); -+ return 0; -+ } -+ if ((p_FmPcd->guestId != NCSW_MASTER_ID) && -+ !p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs && -+ !p_FmPcd->h_IpcSession) -+ { -+ REPORT_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("running in \"guest-mode\" without neither IPC nor mapped register!")); -+ return 0; -+ } -+ -+ /* check that counters are enabled */ -+ if (p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs && -+ !(GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_gcr) & FM_PCD_PLCR_GCR_STEN)) -+ { -+ REPORT_ERROR(MINOR, E_INVALID_STATE, ("Requested counter was not enabled")); -+ return 0; -+ } -+ ASSERT_COND(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs || -+ ((p_FmPcd->guestId != NCSW_MASTER_ID) && p_FmPcd->h_IpcSession)); -+ break; -+ -+ case (e_FM_PCD_PRS_COUNTERS_PARSE_DISPATCH): -+ case (e_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED): -+ case (e_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED): -+ case (e_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED): -+ case (e_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED): -+ case (e_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED_WITH_ERR): -+ case (e_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED_WITH_ERR): -+ case (e_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED_WITH_ERR): -+ case (e_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED_WITH_ERR): -+ case (e_FM_PCD_PRS_COUNTERS_SOFT_PRS_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_SOFT_PRS_STALL_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_HARD_PRS_CYCLE_INCL_STALL_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_READ_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_READ_STALL_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_WRITE_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_WRITE_STALL_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_FPM_COMMAND_STALL_CYCLES): -+ if (!p_FmPcd->p_FmPcdPrs) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Parser is not activated")); -+ return 0; -+ } -+ if ((p_FmPcd->guestId != NCSW_MASTER_ID) && -+ !p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs && -+ !p_FmPcd->h_IpcSession) -+ { -+ REPORT_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without neither IPC nor mapped register!")); -+ return 0; -+ } -+ break; -+ default: -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Unsupported type of counter")); -+ return 0; -+ } -+ -+ if ((p_FmPcd->guestId != NCSW_MASTER_ID) && -+ p_FmPcd->h_IpcSession) -+ { -+ t_FmPcdIpcMsg msg; -+ t_FmPcdIpcReply reply; -+ uint32_t replyLength; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_PCD_GET_COUNTER; -+ memcpy(msg.msgBody, (uint8_t *)&counter, sizeof(uint32_t)); -+ replyLength = sizeof(uint32_t) + sizeof(uint32_t); -+ if ((err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) +sizeof(uint32_t), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ if (replyLength != sizeof(uint32_t) + sizeof(uint32_t)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ -+ memcpy((uint8_t*)&outCounter, reply.replyBody, sizeof(uint32_t)); -+ return outCounter; -+ } -+ -+ switch (counter) -+ { -+ /* Parser statistics */ -+ case (e_FM_PCD_PRS_COUNTERS_PARSE_DISPATCH): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_pds); -+ case (e_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_l2rrs); -+ case (e_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_l3rrs); -+ case (e_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_l4rrs); -+ case (e_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_srrs); -+ case (e_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED_WITH_ERR): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_l2rres); -+ case (e_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED_WITH_ERR): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_l3rres); -+ case (e_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED_WITH_ERR): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_l4rres); -+ case (e_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED_WITH_ERR): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_srres); -+ case (e_FM_PCD_PRS_COUNTERS_SOFT_PRS_CYCLES): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_spcs); -+ case (e_FM_PCD_PRS_COUNTERS_SOFT_PRS_STALL_CYCLES): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_spscs); -+ case (e_FM_PCD_PRS_COUNTERS_HARD_PRS_CYCLE_INCL_STALL_CYCLES): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_hxscs); -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_READ_CYCLES): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_mrcs); -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_READ_STALL_CYCLES): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_mrscs); -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_WRITE_CYCLES): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_mwcs); -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_WRITE_STALL_CYCLES): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_mwscs); -+ case (e_FM_PCD_PRS_COUNTERS_FPM_COMMAND_STALL_CYCLES): -+ return GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_fcscs); -+ case (e_FM_PCD_KG_COUNTERS_TOTAL): -+ return GET_UINT32(p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs->fmkg_tpc); -+ -+ /* Policer statistics */ -+ case (e_FM_PCD_PLCR_COUNTERS_YELLOW): -+ return GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_ypcnt); -+ case (e_FM_PCD_PLCR_COUNTERS_RED): -+ return GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_rpcnt); -+ case (e_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_RED): -+ return GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_rrpcnt); -+ case (e_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_YELLOW): -+ return GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_rypcnt); -+ case (e_FM_PCD_PLCR_COUNTERS_TOTAL): -+ return GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_tpcnt); -+ case (e_FM_PCD_PLCR_COUNTERS_LENGTH_MISMATCH): -+ return GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_flmcnt); -+ } -+ return 0; -+} -+ -+t_Error FM_PCD_SetException(t_Handle h_FmPcd, e_FmPcdExceptions exception, bool enable) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint32_t bitMask = 0, tmpReg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE); -+ -+ if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_SetException - guest mode!")); -+ -+ GET_FM_PCD_EXCEPTION_FLAG(bitMask, exception); -+ -+ if (bitMask) -+ { -+ if (enable) -+ p_FmPcd->exceptions |= bitMask; -+ else -+ p_FmPcd->exceptions &= ~bitMask; -+ -+ switch (exception) -+ { -+ case (e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC): -+ case (e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW): -+ if (!p_FmPcd->p_FmPcdKg) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Can't ask for this interrupt - keygen is not working")); -+ break; -+ case (e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC): -+ case (e_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR): -+ case (e_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE): -+ case (e_FM_PCD_PLCR_EXCEPTION_ATOMIC_ACTION_COMPLETE): -+ if (!p_FmPcd->p_FmPcdPlcr) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Can't ask for this interrupt - policer is not working")); -+ break; -+ case (e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC): -+ case (e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC): -+ if (!p_FmPcd->p_FmPcdPrs) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Can't ask for this interrupt - parser is not working")); -+ break; -+ } -+ -+ switch (exception) -+ { -+ case (e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC): -+ tmpReg = GET_UINT32(p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs->fmkg_eeer); -+ if (enable) -+ tmpReg |= FM_EX_KG_DOUBLE_ECC; -+ else -+ tmpReg &= ~FM_EX_KG_DOUBLE_ECC; -+ WRITE_UINT32(p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs->fmkg_eeer, tmpReg); -+ break; -+ case (e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW): -+ tmpReg = GET_UINT32(p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs->fmkg_eeer); -+ if (enable) -+ tmpReg |= FM_EX_KG_KEYSIZE_OVERFLOW; -+ else -+ tmpReg &= ~FM_EX_KG_KEYSIZE_OVERFLOW; -+ WRITE_UINT32(p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs->fmkg_eeer, tmpReg); -+ break; -+ case (e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC): -+ tmpReg = GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_perer); -+ if (enable) -+ tmpReg |= FM_PCD_PRS_DOUBLE_ECC; -+ else -+ tmpReg &= ~FM_PCD_PRS_DOUBLE_ECC; -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_perer, tmpReg); -+ break; -+ case (e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC): -+ tmpReg = GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_pever); -+ if (enable) -+ tmpReg |= FM_PCD_PRS_SINGLE_ECC; -+ else -+ tmpReg &= ~FM_PCD_PRS_SINGLE_ECC; -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_pever, tmpReg); -+ break; -+ case (e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC): -+ tmpReg = GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_eier); -+ if (enable) -+ tmpReg |= FM_PCD_PLCR_DOUBLE_ECC; -+ else -+ tmpReg &= ~FM_PCD_PLCR_DOUBLE_ECC; -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_eier, tmpReg); -+ break; -+ case (e_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR): -+ tmpReg = GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_eier); -+ if (enable) -+ tmpReg |= FM_PCD_PLCR_INIT_ENTRY_ERROR; -+ else -+ tmpReg &= ~FM_PCD_PLCR_INIT_ENTRY_ERROR; -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_eier, tmpReg); -+ break; -+ case (e_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE): -+ tmpReg = GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_ier); -+ if (enable) -+ tmpReg |= FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE; -+ else -+ tmpReg &= ~FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE; -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_ier, tmpReg); -+ break; -+ case (e_FM_PCD_PLCR_EXCEPTION_ATOMIC_ACTION_COMPLETE): -+ tmpReg = GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_ier); -+ if (enable) -+ tmpReg |= FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE; -+ else -+ tmpReg &= ~FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE; -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_ier, tmpReg); -+ break; -+ } -+ /* for ECC exceptions driver automatically enables ECC mechanism, if disabled. -+ Driver may disable them automatically, depending on driver's status */ -+ if (enable && ((exception == e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC) | -+ (exception == e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC) | -+ (exception == e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC) | -+ (exception == e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC))) -+ FmEnableRamsEcc(p_FmPcd->h_Fm); -+ if (!enable && ((exception == e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC) | -+ (exception == e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC) | -+ (exception == e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC) | -+ (exception == e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC))) -+ FmDisableRamsEcc(p_FmPcd->h_Fm); -+ } -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_ForceIntr (t_Handle h_FmPcd, e_FmPcdExceptions exception) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE); -+ -+ if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_ForceIntr - guest mode!")); -+ -+ switch (exception) -+ { -+ case (e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC): -+ case (e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW): -+ if (!p_FmPcd->p_FmPcdKg) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Can't ask for this interrupt - keygen is not working")); -+ break; -+ case (e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC): -+ case (e_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR): -+ case (e_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE): -+ case (e_FM_PCD_PLCR_EXCEPTION_ATOMIC_ACTION_COMPLETE): -+ if (!p_FmPcd->p_FmPcdPlcr) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Can't ask for this interrupt - policer is not working")); -+ break; -+ case (e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC): -+ case (e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC): -+ if (!p_FmPcd->p_FmPcdPrs) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Can't ask for this interrupt -parsrer is not working")); -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Invalid interrupt requested")); -+ } -+ switch (exception) -+ { -+ case e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC: -+ if (!(p_FmPcd->exceptions & FM_PCD_EX_PRS_DOUBLE_ECC)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ break; -+ case e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC: -+ if (!(p_FmPcd->exceptions & FM_PCD_EX_PRS_SINGLE_ECC)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ break; -+ case e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC: -+ if (!(p_FmPcd->exceptions & FM_EX_KG_DOUBLE_ECC)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ WRITE_UINT32(p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs->fmkg_feer, FM_EX_KG_DOUBLE_ECC); -+ break; -+ case e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW: -+ if (!(p_FmPcd->exceptions & FM_EX_KG_KEYSIZE_OVERFLOW)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ WRITE_UINT32(p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs->fmkg_feer, FM_EX_KG_KEYSIZE_OVERFLOW); -+ break; -+ case e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC: -+ if (!(p_FmPcd->exceptions & FM_PCD_EX_PLCR_DOUBLE_ECC)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_eifr, FM_PCD_PLCR_DOUBLE_ECC); -+ break; -+ case e_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR: -+ if (!(p_FmPcd->exceptions & FM_PCD_EX_PLCR_INIT_ENTRY_ERROR)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_eifr, FM_PCD_PLCR_INIT_ENTRY_ERROR); -+ break; -+ case e_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE: -+ if (!(p_FmPcd->exceptions & FM_PCD_EX_PLCR_PRAM_SELF_INIT_COMPLETE)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_ifr, FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE); -+ break; -+ case e_FM_PCD_PLCR_EXCEPTION_ATOMIC_ACTION_COMPLETE: -+ if (!(p_FmPcd->exceptions & FM_PCD_EX_PLCR_ATOMIC_ACTION_COMPLETE)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_ifr, FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE); -+ break; -+ } -+ -+ return E_OK; -+} -+ -+ -+t_Error FM_PCD_ModifyCounter(t_Handle h_FmPcd, e_FmPcdCounters counter, uint32_t value) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE); -+ -+ if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_ModifyCounter - guest mode!")); -+ -+ switch (counter) -+ { -+ case (e_FM_PCD_KG_COUNTERS_TOTAL): -+ if (!p_FmPcd->p_FmPcdKg) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Invalid counters - KeyGen is not working")); -+ break; -+ case (e_FM_PCD_PLCR_COUNTERS_YELLOW): -+ case (e_FM_PCD_PLCR_COUNTERS_RED): -+ case (e_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_RED): -+ case (e_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_YELLOW): -+ case (e_FM_PCD_PLCR_COUNTERS_TOTAL): -+ case (e_FM_PCD_PLCR_COUNTERS_LENGTH_MISMATCH): -+ if (!p_FmPcd->p_FmPcdPlcr) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Invalid counters - Policer is not working")); -+ if (!(GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_gcr) & FM_PCD_PLCR_GCR_STEN)) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Requested counter was not enabled")); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_PARSE_DISPATCH): -+ case (e_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED): -+ case (e_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED): -+ case (e_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED): -+ case (e_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED): -+ case (e_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED_WITH_ERR): -+ case (e_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED_WITH_ERR): -+ case (e_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED_WITH_ERR): -+ case (e_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED_WITH_ERR): -+ case (e_FM_PCD_PRS_COUNTERS_SOFT_PRS_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_SOFT_PRS_STALL_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_HARD_PRS_CYCLE_INCL_STALL_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_READ_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_READ_STALL_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_WRITE_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_WRITE_STALL_CYCLES): -+ case (e_FM_PCD_PRS_COUNTERS_FPM_COMMAND_STALL_CYCLES): -+ if (!p_FmPcd->p_FmPcdPrs) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Unsupported type of counter")); -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Unsupported type of counter")); -+ } -+ switch (counter) -+ { -+ case (e_FM_PCD_PRS_COUNTERS_PARSE_DISPATCH): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_pds, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_l2rrs, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_l3rrs, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_l4rrs, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_srrs, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED_WITH_ERR): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_l2rres, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED_WITH_ERR): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_l3rres, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED_WITH_ERR): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_l4rres, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED_WITH_ERR): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_srres, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_SOFT_PRS_CYCLES): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_spcs, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_SOFT_PRS_STALL_CYCLES): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_spscs, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_HARD_PRS_CYCLE_INCL_STALL_CYCLES): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_hxscs, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_READ_CYCLES): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_mrcs, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_READ_STALL_CYCLES): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_mrscs, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_WRITE_CYCLES): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_mwcs, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_MURAM_WRITE_STALL_CYCLES): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_mwscs, value); -+ break; -+ case (e_FM_PCD_PRS_COUNTERS_FPM_COMMAND_STALL_CYCLES): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->fmpr_fcscs, value); -+ break; -+ case (e_FM_PCD_KG_COUNTERS_TOTAL): -+ WRITE_UINT32(p_FmPcd->p_FmPcdKg->p_FmPcdKgRegs->fmkg_tpc,value); -+ break; -+ -+ /*Policer counters*/ -+ case (e_FM_PCD_PLCR_COUNTERS_YELLOW): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_ypcnt, value); -+ break; -+ case (e_FM_PCD_PLCR_COUNTERS_RED): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_rpcnt, value); -+ break; -+ case (e_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_RED): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_rrpcnt, value); -+ break; -+ case (e_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_YELLOW): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_rypcnt, value); -+ break; -+ case (e_FM_PCD_PLCR_COUNTERS_TOTAL): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_tpcnt, value); -+ break; -+ case (e_FM_PCD_PLCR_COUNTERS_LENGTH_MISMATCH): -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_flmcnt, value); -+ break; -+ } -+ -+ return E_OK; -+} -+ -+t_Handle FM_PCD_GetHcPort(t_Handle h_FmPcd) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ return FmHcGetPort(p_FmPcd->h_Hc); -+} -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd.h -@@ -0,0 +1,543 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_pcd.h -+ -+ @Description FM PCD ... -+*//***************************************************************************/ -+#ifndef __FM_PCD_H -+#define __FM_PCD_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "list_ext.h" -+#include "fm_pcd_ext.h" -+#include "fm_common.h" -+#include "fsl_fman_prs.h" -+#include "fsl_fman_kg.h" -+ -+#define __ERR_MODULE__ MODULE_FM_PCD -+ -+ -+/****************************/ -+/* Defaults */ -+/****************************/ -+#define DEFAULT_plcrAutoRefresh FALSE -+#define DEFAULT_fmPcdKgErrorExceptions (FM_EX_KG_DOUBLE_ECC | FM_EX_KG_KEYSIZE_OVERFLOW) -+#define DEFAULT_fmPcdPlcrErrorExceptions (FM_PCD_EX_PLCR_DOUBLE_ECC | FM_PCD_EX_PLCR_INIT_ENTRY_ERROR) -+#define DEFAULT_fmPcdPlcrExceptions 0 -+#define DEFAULT_fmPcdPrsErrorExceptions (FM_PCD_EX_PRS_DOUBLE_ECC) -+ -+#define DEFAULT_fmPcdPrsExceptions FM_PCD_EX_PRS_SINGLE_ECC -+#define DEFAULT_numOfUsedProfilesPerWindow 16 -+#define DEFAULT_numOfSharedPlcrProfiles 4 -+ -+/****************************/ -+/* Network defines */ -+/****************************/ -+#define UDP_HEADER_SIZE 8 -+ -+#define ESP_SPI_OFFSET 0 -+#define ESP_SPI_SIZE 4 -+#define ESP_SEQ_NUM_OFFSET ESP_SPI_SIZE -+#define ESP_SEQ_NUM_SIZE 4 -+ -+/****************************/ -+/* General defines */ -+/****************************/ -+#define ILLEGAL_CLS_PLAN 0xff -+#define ILLEGAL_NETENV 0xff -+ -+#define FM_PCD_MAX_NUM_OF_ALIAS_HDRS 3 -+ -+/****************************/ -+/* Error defines */ -+/****************************/ -+ -+#define FM_PCD_EX_PLCR_DOUBLE_ECC 0x20000000 -+#define FM_PCD_EX_PLCR_INIT_ENTRY_ERROR 0x10000000 -+#define FM_PCD_EX_PLCR_PRAM_SELF_INIT_COMPLETE 0x08000000 -+#define FM_PCD_EX_PLCR_ATOMIC_ACTION_COMPLETE 0x04000000 -+ -+#define GET_FM_PCD_EXCEPTION_FLAG(bitMask, exception) \ -+switch (exception){ \ -+ case e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC: \ -+ bitMask = FM_EX_KG_DOUBLE_ECC; break; \ -+ case e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC: \ -+ bitMask = FM_PCD_EX_PLCR_DOUBLE_ECC; break; \ -+ case e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW: \ -+ bitMask = FM_EX_KG_KEYSIZE_OVERFLOW; break; \ -+ case e_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR: \ -+ bitMask = FM_PCD_EX_PLCR_INIT_ENTRY_ERROR; break; \ -+ case e_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE: \ -+ bitMask = FM_PCD_EX_PLCR_PRAM_SELF_INIT_COMPLETE; break; \ -+ case e_FM_PCD_PLCR_EXCEPTION_ATOMIC_ACTION_COMPLETE: \ -+ bitMask = FM_PCD_EX_PLCR_ATOMIC_ACTION_COMPLETE; break; \ -+ case e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC: \ -+ bitMask = FM_PCD_EX_PRS_DOUBLE_ECC; break; \ -+ case e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC: \ -+ bitMask = FM_PCD_EX_PRS_SINGLE_ECC; break; \ -+ default: bitMask = 0;break;} -+ -+/***********************************************************************/ -+/* Policer defines */ -+/***********************************************************************/ -+#define FM_PCD_PLCR_GCR_STEN 0x40000000 -+#define FM_PCD_PLCR_DOUBLE_ECC 0x80000000 -+#define FM_PCD_PLCR_INIT_ENTRY_ERROR 0x40000000 -+#define FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE 0x80000000 -+#define FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE 0x40000000 -+ -+/***********************************************************************/ -+/* Memory map */ -+/***********************************************************************/ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+ -+typedef struct { -+/* General Configuration and Status Registers */ -+ volatile uint32_t fmpl_gcr; /* 0x000 FMPL_GCR - FM Policer General Configuration */ -+ volatile uint32_t fmpl_gsr; /* 0x004 FMPL_GSR - FM Policer Global Status Register */ -+ volatile uint32_t fmpl_evr; /* 0x008 FMPL_EVR - FM Policer Event Register */ -+ volatile uint32_t fmpl_ier; /* 0x00C FMPL_IER - FM Policer Interrupt Enable Register */ -+ volatile uint32_t fmpl_ifr; /* 0x010 FMPL_IFR - FM Policer Interrupt Force Register */ -+ volatile uint32_t fmpl_eevr; /* 0x014 FMPL_EEVR - FM Policer Error Event Register */ -+ volatile uint32_t fmpl_eier; /* 0x018 FMPL_EIER - FM Policer Error Interrupt Enable Register */ -+ volatile uint32_t fmpl_eifr; /* 0x01C FMPL_EIFR - FM Policer Error Interrupt Force Register */ -+/* Global Statistic Counters */ -+ volatile uint32_t fmpl_rpcnt; /* 0x020 FMPL_RPC - FM Policer RED Packets Counter */ -+ volatile uint32_t fmpl_ypcnt; /* 0x024 FMPL_YPC - FM Policer YELLOW Packets Counter */ -+ volatile uint32_t fmpl_rrpcnt; /* 0x028 FMPL_RRPC - FM Policer Recolored RED Packet Counter */ -+ volatile uint32_t fmpl_rypcnt; /* 0x02C FMPL_RYPC - FM Policer Recolored YELLOW Packet Counter */ -+ volatile uint32_t fmpl_tpcnt; /* 0x030 FMPL_TPC - FM Policer Total Packet Counter */ -+ volatile uint32_t fmpl_flmcnt; /* 0x034 FMPL_FLMC - FM Policer Frame Length Mismatch Counter */ -+ volatile uint32_t fmpl_res0[21]; /* 0x038 - 0x08B Reserved */ -+/* Profile RAM Access Registers */ -+ volatile uint32_t fmpl_par; /* 0x08C FMPL_PAR - FM Policer Profile Action Register*/ -+ t_FmPcdPlcrProfileRegs profileRegs; -+/* Error Capture Registers */ -+ volatile uint32_t fmpl_serc; /* 0x100 FMPL_SERC - FM Policer Soft Error Capture */ -+ volatile uint32_t fmpl_upcr; /* 0x104 FMPL_UPCR - FM Policer Uninitialized Profile Capture Register */ -+ volatile uint32_t fmpl_res2; /* 0x108 Reserved */ -+/* Debug Registers */ -+ volatile uint32_t fmpl_res3[61]; /* 0x10C-0x200 Reserved Debug*/ -+/* Profile Selection Mapping Registers Per Port-ID (n=1-11, 16) */ -+ volatile uint32_t fmpl_dpmr; /* 0x200 FMPL_DPMR - FM Policer Default Mapping Register */ -+ volatile uint32_t fmpl_pmr[63]; /*+default 0x204-0x2FF FMPL_PMR1 - FMPL_PMR63, - FM Policer Profile Mapping Registers. -+ (for port-ID 1-11, only for supported Port-ID registers) */ -+} t_FmPcdPlcrRegs; -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+ -+/***********************************************************************/ -+/* Driver's internal structures */ -+/***********************************************************************/ -+ -+typedef struct { -+ bool known; -+ uint8_t id; -+} t_FmPcdKgSchemesExtractsEntry; -+ -+typedef struct { -+ t_FmPcdKgSchemesExtractsEntry extractsArray[FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY]; -+} t_FmPcdKgSchemesExtracts; -+ -+typedef struct { -+ t_Handle h_Manip; -+ bool keepRes; -+ e_FmPcdEngine nextEngine; -+ uint8_t parseCode; -+} t_FmPcdInfoForManip; -+ -+/**************************************************************************//** -+ @Description A structure of parameters to communicate -+ between the port and PCD regarding the KG scheme. -+*//***************************************************************************/ -+typedef struct { -+ uint8_t netEnvId; /* in */ -+ uint8_t numOfDistinctionUnits; /* in */ -+ uint8_t unitIds[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; /* in */ -+ uint32_t vector; /* out */ -+} t_NetEnvParams; -+ -+typedef struct { -+ bool allocated; -+ uint8_t ownerId; /* guestId for KG in multi-partition only. -+ portId for PLCR in any environment */ -+} t_FmPcdAllocMng; -+ -+typedef struct { -+ volatile bool lock; -+ bool used; -+ uint8_t owners; -+ uint8_t netEnvId; -+ uint8_t guestId; -+ uint8_t baseEntry; -+ uint16_t sizeOfGrp; -+ protocolOpt_t optArray[FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)]; -+} t_FmPcdKgClsPlanGrp; -+ -+typedef struct { -+ t_Handle h_FmPcd; -+ uint8_t schemeId; -+ t_FmPcdLock *p_Lock; -+ bool valid; -+ uint8_t netEnvId; -+ uint8_t owners; -+ uint32_t matchVector; -+ uint32_t ccUnits; -+ bool nextRelativePlcrProfile; -+ uint16_t relativeProfileId; -+ uint16_t numOfProfiles; -+ t_FmPcdKgKeyOrder orderedArray; -+ e_FmPcdEngine nextEngine; -+ e_FmPcdDoneAction doneAction; -+ bool requiredActionFlag; -+ uint32_t requiredAction; -+ bool extractedOrs; -+ uint8_t bitOffsetInPlcrProfile; -+ bool directPlcr; -+#if (DPAA_VERSION >= 11) -+ bool vspe; -+#endif -+} t_FmPcdKgScheme; -+ -+typedef union { -+ struct fman_kg_scheme_regs schemeRegs; -+ struct fman_kg_pe_regs portRegs; -+ struct fman_kg_cp_regs clsPlanRegs; -+} u_FmPcdKgIndirectAccessRegs; -+ -+typedef struct { -+ struct fman_kg_regs *p_FmPcdKgRegs; -+ uint32_t schemeExceptionsBitMask; -+ uint8_t numOfSchemes; -+ t_Handle h_HwSpinlock; -+ uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES]; -+ t_FmPcdKgScheme schemes[FM_PCD_KG_NUM_OF_SCHEMES]; -+ t_FmPcdKgClsPlanGrp clsPlanGrps[FM_MAX_NUM_OF_PORTS]; -+ uint8_t emptyClsPlanGrpId; -+ t_FmPcdAllocMng schemesMng[FM_PCD_KG_NUM_OF_SCHEMES]; /* only for MASTER ! */ -+ t_FmPcdAllocMng clsPlanBlocksMng[FM_PCD_MAX_NUM_OF_CLS_PLANS/CLS_PLAN_NUM_PER_GRP]; -+ u_FmPcdKgIndirectAccessRegs *p_IndirectAccessRegs; -+} t_FmPcdKg; -+ -+typedef struct { -+ uint16_t profilesBase; -+ uint16_t numOfProfiles; -+ t_Handle h_FmPort; -+} t_FmPcdPlcrMapParam; -+ -+typedef struct { -+ uint16_t absoluteProfileId; -+ t_Handle h_FmPcd; -+ bool valid; -+ t_FmPcdLock *p_Lock; -+ t_FmPcdAllocMng profilesMng; -+ bool requiredActionFlag; -+ uint32_t requiredAction; -+ e_FmPcdEngine nextEngineOnGreen; /**< Green next engine type */ -+ u_FmPcdPlcrNextEngineParams paramsOnGreen; /**< Green next engine params */ -+ -+ e_FmPcdEngine nextEngineOnYellow; /**< Yellow next engine type */ -+ u_FmPcdPlcrNextEngineParams paramsOnYellow; /**< Yellow next engine params */ -+ -+ e_FmPcdEngine nextEngineOnRed; /**< Red next engine type */ -+ u_FmPcdPlcrNextEngineParams paramsOnRed; /**< Red next engine params */ -+} t_FmPcdPlcrProfile; -+ -+typedef struct { -+ t_FmPcdPlcrRegs *p_FmPcdPlcrRegs; -+ uint16_t partPlcrProfilesBase; -+ uint16_t partNumOfPlcrProfiles; -+ t_FmPcdPlcrProfile profiles[FM_PCD_PLCR_NUM_ENTRIES]; -+ uint16_t numOfSharedProfiles; -+ uint16_t sharedProfilesIds[FM_PCD_PLCR_NUM_ENTRIES]; -+ t_FmPcdPlcrMapParam portsMapping[FM_MAX_NUM_OF_PORTS]; -+ t_Handle h_HwSpinlock; -+ t_Handle h_SwSpinlock; -+} t_FmPcdPlcr; -+ -+typedef struct { -+ uint32_t *p_SwPrsCode; -+ uint32_t *p_CurrSwPrs; -+ uint8_t currLabel; -+ struct fman_prs_regs *p_FmPcdPrsRegs; -+ t_FmPcdPrsLabelParams labelsTable[FM_PCD_PRS_NUM_OF_LABELS]; -+ uint32_t fmPcdPrsPortIdStatistics; -+} t_FmPcdPrs; -+ -+typedef struct { -+ struct { -+ e_NetHeaderType hdr; -+ protocolOpt_t opt; /* only one option !! */ -+ } hdrs[FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS]; -+} t_FmPcdIntDistinctionUnit; -+ -+typedef struct { -+ e_NetHeaderType hdr; -+ protocolOpt_t opt; /* only one option !! */ -+ e_NetHeaderType aliasHdr; -+} t_FmPcdNetEnvAliases; -+ -+typedef struct { -+ uint8_t netEnvId; -+ t_Handle h_FmPcd; -+ t_Handle h_Spinlock; -+ bool used; -+ uint8_t owners; -+ uint8_t clsPlanGrpId; -+ t_FmPcdIntDistinctionUnit units[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; -+ uint32_t unitsVectors[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; -+ uint32_t lcvs[FM_PCD_PRS_NUM_OF_HDRS]; -+ uint32_t macsecVector; -+ t_FmPcdNetEnvAliases aliasHdrs[FM_PCD_MAX_NUM_OF_ALIAS_HDRS]; -+} t_FmPcdNetEnv; -+ -+typedef struct { -+ struct fman_prs_cfg dfltCfg; -+ bool plcrAutoRefresh; -+ uint16_t prsMaxParseCycleLimit; -+} t_FmPcdDriverParam; -+ -+typedef struct { -+ t_Handle h_Fm; -+ t_Handle h_FmMuram; -+ t_FmRevisionInfo fmRevInfo; -+ -+ uint64_t physicalMuramBase; -+ -+ t_Handle h_Spinlock; -+ t_List freeLocksLst; -+ t_List acquiredLocksLst; -+ -+ t_Handle h_IpcSession; /* relevant for guest only */ -+ bool enabled; -+ uint8_t guestId; /**< Guest Partition Id */ -+ uint8_t numOfEnabledGuestPartitionsPcds; -+ char fmPcdModuleName[MODULE_NAME_SIZE]; -+ char fmPcdIpcHandlerModuleName[MODULE_NAME_SIZE]; /* relevant for guest only - this is the master's name */ -+ t_FmPcdNetEnv netEnvs[FM_MAX_NUM_OF_PORTS]; -+ t_FmPcdKg *p_FmPcdKg; -+ t_FmPcdPlcr *p_FmPcdPlcr; -+ t_FmPcdPrs *p_FmPcdPrs; -+ -+ void *p_CcShadow; /**< CC MURAM shadow */ -+ uint32_t ccShadowSize; -+ uint32_t ccShadowAlign; -+ volatile bool shadowLock; -+ t_Handle h_ShadowSpinlock; -+ -+ t_Handle h_Hc; -+ -+ uint32_t exceptions; -+ t_FmPcdExceptionCallback *f_Exception; -+ t_FmPcdIdExceptionCallback *f_FmPcdIndexedException; -+ t_Handle h_App; -+ uintptr_t ipv6FrameIdAddr; -+ uintptr_t capwapFrameIdAddr; -+ bool advancedOffloadSupport; -+ -+ t_FmPcdDriverParam *p_FmPcdDriverParam; -+} t_FmPcd; -+ -+#if (DPAA_VERSION >= 11) -+typedef uint8_t t_FmPcdFrmReplicUpdateType; -+#define FRM_REPLIC_UPDATE_COUNTER 0x01 -+#define FRM_REPLIC_UPDATE_INFO 0x02 -+#endif /* (DPAA_VERSION >= 11) */ -+/***********************************************************************/ -+/* PCD internal routines */ -+/***********************************************************************/ -+ -+t_Error PcdGetVectorForOpt(t_FmPcd *p_FmPcd, uint8_t netEnvId, protocolOpt_t opt, uint32_t *p_Vector); -+t_Error PcdGetUnitsVector(t_FmPcd *p_FmPcd, t_NetEnvParams *p_Params); -+bool PcdNetEnvIsUnitWithoutOpts(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint32_t unitVector); -+t_Error PcdGetClsPlanGrpParams(t_FmPcd *p_FmPcd, t_FmPcdKgInterModuleClsPlanGrpParams *p_GrpParams); -+void FmPcdSetClsPlanGrpId(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint8_t clsPlanGrpId); -+e_NetHeaderType FmPcdGetAliasHdr(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr); -+uint8_t FmPcdNetEnvGetUnitIdForSingleHdr(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr); -+uint8_t FmPcdNetEnvGetUnitId(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr, bool interchangeable, protocolOpt_t opt); -+ -+t_Error FmPcdManipBuildIpReassmScheme(t_FmPcd *p_FmPcd, t_Handle h_NetEnv, t_Handle h_CcTree, t_Handle h_Manip, bool isIpv4, uint8_t groupId); -+t_Error FmPcdManipDeleteIpReassmSchemes(t_Handle h_Manip); -+t_Error FmPcdManipBuildCapwapReassmScheme(t_FmPcd *p_FmPcd, t_Handle h_NetEnv, t_Handle h_CcTree, t_Handle h_Manip, uint8_t groupId); -+t_Error FmPcdManipDeleteCapwapReassmSchemes(t_Handle h_Manip); -+bool FmPcdManipIpReassmIsIpv6Hdr(t_Handle h_Manip); -+ -+t_Handle KgConfig( t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams); -+t_Error KgInit(t_FmPcd *p_FmPcd); -+t_Error KgFree(t_FmPcd *p_FmPcd); -+void KgSetClsPlan(t_Handle h_FmPcd, t_FmPcdKgInterModuleClsPlanSet *p_Set); -+bool KgIsSchemeAlwaysDirect(t_Handle h_FmPcd, uint8_t schemeId); -+void KgEnable(t_FmPcd *p_FmPcd); -+void KgDisable(t_FmPcd *p_FmPcd); -+t_Error KgAllocClsPlanEntries(t_Handle h_FmPcd, uint16_t numOfClsPlanEntries, uint8_t guestId, uint8_t *p_First); -+void KgFreeClsPlanEntries(t_Handle h_FmPcd, uint16_t numOfClsPlanEntries, uint8_t guestId, uint8_t base); -+ -+/* only for MULTI partittion */ -+t_Error FmPcdKgAllocSchemes(t_Handle h_FmPcd, uint8_t numOfSchemes, uint8_t guestId, uint8_t *p_SchemesIds); -+t_Error FmPcdKgFreeSchemes(t_Handle h_FmPcd, uint8_t numOfSchemes, uint8_t guestId, uint8_t *p_SchemesIds); -+/* only for SINGLE partittion */ -+t_Error KgBindPortToSchemes(t_Handle h_FmPcd , uint8_t hardwarePortId, uint32_t spReg); -+ -+t_FmPcdLock *FmPcdAcquireLock(t_Handle h_FmPcd); -+void FmPcdReleaseLock(t_Handle h_FmPcd, t_FmPcdLock *p_Lock); -+ -+t_Handle PlcrConfig(t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams); -+t_Error PlcrInit(t_FmPcd *p_FmPcd); -+t_Error PlcrFree(t_FmPcd *p_FmPcd); -+void PlcrEnable(t_FmPcd *p_FmPcd); -+void PlcrDisable(t_FmPcd *p_FmPcd); -+uint16_t PlcrAllocProfilesForPartition(t_FmPcd *p_FmPcd, uint16_t base, uint16_t numOfProfiles, uint8_t guestId); -+void PlcrFreeProfilesForPartition(t_FmPcd *p_FmPcd, uint16_t base, uint16_t numOfProfiles, uint8_t guestId); -+t_Error PlcrSetPortProfiles(t_FmPcd *p_FmPcd, -+ uint8_t hardwarePortId, -+ uint16_t numOfProfiles, -+ uint16_t base); -+t_Error PlcrClearPortProfiles(t_FmPcd *p_FmPcd, uint8_t hardwarePortId); -+ -+t_Handle PrsConfig(t_FmPcd *p_FmPcd,t_FmPcdParams *p_FmPcdParams); -+t_Error PrsInit(t_FmPcd *p_FmPcd); -+void PrsEnable(t_FmPcd *p_FmPcd); -+void PrsDisable(t_FmPcd *p_FmPcd); -+void PrsFree(t_FmPcd *p_FmPcd ); -+t_Error PrsIncludePortInStatistics(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, bool include); -+ -+t_Error FmPcdCcGetGrpParams(t_Handle treeId, uint8_t grpId, uint32_t *p_GrpBits, uint8_t *p_GrpBase); -+uint8_t FmPcdCcGetOffset(t_Handle h_CcNode); -+uint8_t FmPcdCcGetParseCode(t_Handle h_CcNode); -+uint16_t FmPcdCcGetNumOfKeys(t_Handle h_CcNode); -+t_Error ValidateNextEngineParams(t_Handle h_FmPcd, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams, e_FmPcdCcStatsMode supportedStatsMode); -+ -+void FmPcdManipUpdateOwner(t_Handle h_Manip, bool add); -+t_Error FmPcdManipCheckParamsForCcNextEngine(t_FmPcdCcNextEngineParams *p_InfoForManip, uint32_t *requiredAction); -+void FmPcdManipUpdateAdResultForCc(t_Handle h_Manip, -+ t_FmPcdCcNextEngineParams *p_CcNextEngineParams, -+ t_Handle p_Ad, -+ t_Handle *p_AdNewPtr); -+void FmPcdManipUpdateAdContLookupForCc(t_Handle h_Manip, t_Handle p_Ad, t_Handle *p_AdNew, uint32_t adTableOffset); -+void FmPcdManipUpdateOwner(t_Handle h_Manip, bool add); -+t_Error FmPcdManipCheckParamsWithCcNodeParams(t_Handle h_Manip, t_Handle h_FmPcdCcNode); -+#ifdef FM_CAPWAP_SUPPORT -+t_Handle FmPcdManipApplSpecificBuild(void); -+bool FmPcdManipIsCapwapApplSpecific(t_Handle h_Manip); -+#endif /* FM_CAPWAP_SUPPORT */ -+#if (DPAA_VERSION >= 11) -+void * FrmReplicGroupGetSourceTableDescriptor(t_Handle h_ReplicGroup); -+void FrmReplicGroupUpdateOwner(t_Handle h_ReplicGroup, bool add); -+void FrmReplicGroupUpdateAd(t_Handle h_ReplicGroup, void *p_Ad, t_Handle *h_AdNew); -+ -+void FmPcdCcGetAdTablesThatPointOnReplicGroup(t_Handle h_Node, -+ t_Handle h_ReplicGroup, -+ t_List *p_AdTables, -+ uint32_t *p_NumOfAdTables); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+void EnqueueNodeInfoToRelevantLst(t_List *p_List, t_CcNodeInformation *p_CcInfo, t_Handle h_Spinlock); -+void DequeueNodeInfoFromRelevantLst(t_List *p_List, t_Handle h_Info, t_Handle h_Spinlock); -+t_CcNodeInformation* FindNodeInfoInReleventLst(t_List *p_List, t_Handle h_Info, t_Handle h_Spinlock); -+t_List *FmPcdManipGetSpinlock(t_Handle h_Manip); -+t_List *FmPcdManipGetNodeLstPointedOnThisManip(t_Handle h_Manip); -+ -+typedef struct -+{ -+ t_Handle h_StatsAd; -+ t_Handle h_StatsCounters; -+#if (DPAA_VERSION >= 11) -+ t_Handle h_StatsFLRs; -+#endif /* (DPAA_VERSION >= 11) */ -+} t_FmPcdCcStatsParams; -+ -+void NextStepAd(t_Handle h_Ad, -+ t_FmPcdCcStatsParams *p_FmPcdCcStatsParams, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams, -+ t_FmPcd *p_FmPcd); -+void ReleaseLst(t_List *p_List); -+ -+static __inline__ t_Handle FmPcdGetMuramHandle(t_Handle h_FmPcd) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ ASSERT_COND(p_FmPcd); -+ return p_FmPcd->h_FmMuram; -+} -+ -+static __inline__ uint64_t FmPcdGetMuramPhysBase(t_Handle h_FmPcd) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ ASSERT_COND(p_FmPcd); -+ return p_FmPcd->physicalMuramBase; -+} -+ -+static __inline__ uint32_t FmPcdLockSpinlock(t_FmPcdLock *p_Lock) -+{ -+ ASSERT_COND(p_Lock); -+ return XX_LockIntrSpinlock(p_Lock->h_Spinlock); -+} -+ -+static __inline__ void FmPcdUnlockSpinlock(t_FmPcdLock *p_Lock, uint32_t flags) -+{ -+ ASSERT_COND(p_Lock); -+ XX_UnlockIntrSpinlock(p_Lock->h_Spinlock, flags); -+} -+ -+static __inline__ bool FmPcdLockTryLock(t_FmPcdLock *p_Lock) -+{ -+ uint32_t intFlags; -+ -+ ASSERT_COND(p_Lock); -+ intFlags = XX_LockIntrSpinlock(p_Lock->h_Spinlock); -+ if (p_Lock->flag) -+ { -+ XX_UnlockIntrSpinlock(p_Lock->h_Spinlock, intFlags); -+ return FALSE; -+ } -+ p_Lock->flag = TRUE; -+ XX_UnlockIntrSpinlock(p_Lock->h_Spinlock, intFlags); -+ return TRUE; -+} -+ -+static __inline__ void FmPcdLockUnlock(t_FmPcdLock *p_Lock) -+{ -+ ASSERT_COND(p_Lock); -+ p_Lock->flag = FALSE; -+} -+ -+ -+#endif /* __FM_PCD_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd_ipc.h -@@ -0,0 +1,280 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File fm_pcd_ipc.h -+ -+ @Description FM PCD Inter-Partition prototypes, structures and definitions. -+*//***************************************************************************/ -+#ifndef __FM_PCD_IPC_H -+#define __FM_PCD_IPC_H -+ -+#include "std_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group FM_grp Frame Manager API -+ -+ @Description FM API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+/**************************************************************************//** -+ @Description Structure for getting a sw parser address according to a label -+ Fields commented 'IN' are passed by the port module to be used -+ by the FM module. -+ Fields commented 'OUT' will be filled by FM before returning to port. -+*//***************************************************************************/ -+typedef _Packed struct t_FmPcdIpcSwPrsLable -+{ -+ uint32_t enumHdr; /**< IN. The existence of this header will invoke -+ the sw parser code. */ -+ uint8_t indexPerHdr; /**< IN. Normally 0, if more than one sw parser -+ attachments for the same header, use this -+ -+ index to distinguish between them. */ -+} _PackedType t_FmPcdIpcSwPrsLable; -+ -+/**************************************************************************//** -+ @Description Structure for port-PCD communication. -+ Fields commented 'IN' are passed by the port module to be used -+ by the FM module. -+ Fields commented 'OUT' will be filled by FM before returning to port. -+ Some fields are optional (depending on configuration) and -+ will be analized by the port and FM modules accordingly. -+*//***************************************************************************/ -+ -+typedef struct t_FmPcdIpcKgSchemesParams -+{ -+ uint8_t guestId; -+ uint8_t numOfSchemes; -+ uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES]; -+} _PackedType t_FmPcdIpcKgSchemesParams; -+ -+typedef struct t_FmPcdIpcKgClsPlanParams -+{ -+ uint8_t guestId; -+ uint16_t numOfClsPlanEntries; -+ uint8_t clsPlanBase; -+} _PackedType t_FmPcdIpcKgClsPlanParams; -+ -+typedef _Packed struct t_FmPcdIpcPrsIncludePort -+{ -+ uint8_t hardwarePortId; -+ bool include; -+} _PackedType t_FmPcdIpcPrsIncludePort; -+ -+ -+#define FM_PCD_MAX_REPLY_SIZE 16 -+#define FM_PCD_MAX_MSG_SIZE 36 -+#define FM_PCD_MAX_REPLY_BODY_SIZE 36 -+ -+typedef _Packed struct { -+ uint32_t msgId; -+ uint8_t msgBody[FM_PCD_MAX_MSG_SIZE]; -+} _PackedType t_FmPcdIpcMsg; -+ -+typedef _Packed struct t_FmPcdIpcReply { -+ uint32_t error; -+ uint8_t replyBody[FM_PCD_MAX_REPLY_BODY_SIZE]; -+} _PackedType t_FmPcdIpcReply; -+ -+typedef _Packed struct t_FmIpcResourceAllocParams { -+ uint8_t guestId; -+ uint16_t base; -+ uint16_t num; -+}_PackedType t_FmIpcResourceAllocParams; -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+ -+ -+/**************************************************************************//** -+ @Function FM_PCD_ALLOC_KG_SCHEMES -+ -+ @Description Used by FM PCD front-end in order to allocate KG resources -+ -+ @Param[in/out] t_FmPcdIpcKgAllocParams Pointer -+*//***************************************************************************/ -+#define FM_PCD_ALLOC_KG_SCHEMES 3 -+ -+/**************************************************************************//** -+ @Function FM_PCD_FREE_KG_SCHEMES -+ -+ @Description Used by FM PCD front-end in order to Free KG resources -+ -+ @Param[in/out] t_FmPcdIpcKgSchemesParams Pointer -+*//***************************************************************************/ -+#define FM_PCD_FREE_KG_SCHEMES 4 -+ -+/**************************************************************************//** -+ @Function FM_PCD_ALLOC_PROFILES -+ -+ @Description Used by FM PCD front-end in order to allocate Policer profiles -+ -+ @Param[in/out] t_FmIpcResourceAllocParams Pointer -+*//***************************************************************************/ -+#define FM_PCD_ALLOC_PROFILES 5 -+ -+/**************************************************************************//** -+ @Function FM_PCD_FREE_PROFILES -+ -+ @Description Used by FM PCD front-end in order to Free Policer profiles -+ -+ @Param[in/out] t_FmIpcResourceAllocParams Pointer -+*//***************************************************************************/ -+#define FM_PCD_FREE_PROFILES 6 -+ -+/**************************************************************************//** -+ @Function FM_PCD_SET_PORT_PROFILES -+ -+ @Description Used by FM PCD front-end in order to allocate Policer profiles -+ for specific port -+ -+ @Param[in/out] t_FmIpcResourceAllocParams Pointer -+*//***************************************************************************/ -+#define FM_PCD_SET_PORT_PROFILES 7 -+ -+/**************************************************************************//** -+ @Function FM_PCD_CLEAR_PORT_PROFILES -+ -+ @Description Used by FM PCD front-end in order to allocate Policer profiles -+ for specific port -+ -+ @Param[in/out] t_FmIpcResourceAllocParams Pointer -+*//***************************************************************************/ -+#define FM_PCD_CLEAR_PORT_PROFILES 8 -+ -+/**************************************************************************//** -+ @Function FM_PCD_GET_PHYS_MURAM_BASE -+ -+ @Description Used by FM PCD front-end in order to get MURAM base address -+ -+ @Param[in/out] t_FmPcdIcPhysAddr Pointer -+*//***************************************************************************/ -+#define FM_PCD_GET_PHYS_MURAM_BASE 9 -+ -+/**************************************************************************//** -+ @Function FM_PCD_GET_SW_PRS_OFFSET -+ -+ @Description Used by FM front-end to get the SW parser offset of the start of -+ code relevant to a given label. -+ -+ @Param[in/out] t_FmPcdIpcSwPrsLable Pointer -+*//***************************************************************************/ -+#define FM_PCD_GET_SW_PRS_OFFSET 10 -+ -+/**************************************************************************//** -+ @Function FM_PCD_MASTER_IS_ENABLED -+ -+ @Description Used by FM front-end in order to verify -+ PCD enablement. -+ -+ @Param[in] bool Pointer -+*//***************************************************************************/ -+#define FM_PCD_MASTER_IS_ENABLED 15 -+ -+/**************************************************************************//** -+ @Function FM_PCD_GUEST_DISABLE -+ -+ @Description Used by FM front-end to inform back-end when -+ front-end PCD is disabled -+ -+ @Param[in] None -+*//***************************************************************************/ -+#define FM_PCD_GUEST_DISABLE 16 -+ -+/**************************************************************************//** -+ @Function FM_PCD_FREE_KG_CLSPLAN -+ -+ @Description Used by FM PCD front-end in order to Free KG classification plan entries -+ -+ @Param[in/out] t_FmPcdIpcKgClsPlanParams Pointer -+*//***************************************************************************/ -+#define FM_PCD_FREE_KG_CLSPLAN 22 -+ -+/**************************************************************************//** -+ @Function FM_PCD_ALLOC_KG_CLSPLAN -+ -+ @Description Used by FM PCD front-end in order to allocate KG classification plan entries -+ -+ @Param[in/out] t_FmPcdIpcKgClsPlanParams Pointer -+*//***************************************************************************/ -+#define FM_PCD_ALLOC_KG_CLSPLAN 23 -+ -+/**************************************************************************//** -+ @Function FM_PCD_MASTER_IS_ALIVE -+ -+ @Description Used by FM front-end to check that back-end exists -+ -+ @Param[in] None -+*//***************************************************************************/ -+#define FM_PCD_MASTER_IS_ALIVE 24 -+ -+/**************************************************************************//** -+ @Function FM_PCD_GET_COUNTER -+ -+ @Description Used by FM front-end to read PCD counters -+ -+ @Param[in/out] t_FmPcdIpcGetCounter Pointer -+*//***************************************************************************/ -+#define FM_PCD_GET_COUNTER 25 -+ -+/**************************************************************************//** -+ @Function FM_PCD_PRS_INC_PORT_STATS -+ -+ @Description Used by FM front-end to set/clear statistics for port -+ -+ @Param[in/out] t_FmPcdIpcPrsIncludePort Pointer -+*//***************************************************************************/ -+#define FM_PCD_PRS_INC_PORT_STATS 26 -+ -+#if (DPAA_VERSION >= 11) -+/* TODO - doc */ -+#define FM_PCD_ALLOC_SP 27 -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ -+/** @} */ /* end of FM_PCD_IPC_grp group */ -+/** @} */ /* end of FM_grp group */ -+ -+ -+#endif /* __FM_PCD_IPC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_plcr.c -@@ -0,0 +1,1846 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_plcr.c -+ -+ @Description FM PCD POLICER... -+*//***************************************************************************/ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "string_ext.h" -+#include "debug_ext.h" -+#include "net_ext.h" -+#include "fm_ext.h" -+ -+#include "fm_common.h" -+#include "fm_pcd.h" -+#include "fm_hc.h" -+#include "fm_pcd_ipc.h" -+#include "fm_plcr.h" -+ -+ -+/****************************************/ -+/* static functions */ -+/****************************************/ -+ -+static uint32_t PlcrProfileLock(t_Handle h_Profile) -+{ -+ ASSERT_COND(h_Profile); -+ return FmPcdLockSpinlock(((t_FmPcdPlcrProfile *)h_Profile)->p_Lock); -+} -+ -+static void PlcrProfileUnlock(t_Handle h_Profile, uint32_t intFlags) -+{ -+ ASSERT_COND(h_Profile); -+ FmPcdUnlockSpinlock(((t_FmPcdPlcrProfile *)h_Profile)->p_Lock, intFlags); -+} -+ -+static bool PlcrProfileFlagTryLock(t_Handle h_Profile) -+{ -+ ASSERT_COND(h_Profile); -+ return FmPcdLockTryLock(((t_FmPcdPlcrProfile *)h_Profile)->p_Lock); -+} -+ -+static void PlcrProfileFlagUnlock(t_Handle h_Profile) -+{ -+ ASSERT_COND(h_Profile); -+ FmPcdLockUnlock(((t_FmPcdPlcrProfile *)h_Profile)->p_Lock); -+} -+ -+static uint32_t PlcrHwLock(t_Handle h_FmPcdPlcr) -+{ -+ ASSERT_COND(h_FmPcdPlcr); -+ return XX_LockIntrSpinlock(((t_FmPcdPlcr*)h_FmPcdPlcr)->h_HwSpinlock); -+} -+ -+static void PlcrHwUnlock(t_Handle h_FmPcdPlcr, uint32_t intFlags) -+{ -+ ASSERT_COND(h_FmPcdPlcr); -+ XX_UnlockIntrSpinlock(((t_FmPcdPlcr*)h_FmPcdPlcr)->h_HwSpinlock, intFlags); -+} -+ -+static uint32_t PlcrSwLock(t_Handle h_FmPcdPlcr) -+{ -+ ASSERT_COND(h_FmPcdPlcr); -+ return XX_LockIntrSpinlock(((t_FmPcdPlcr*)h_FmPcdPlcr)->h_SwSpinlock); -+} -+ -+static void PlcrSwUnlock(t_Handle h_FmPcdPlcr, uint32_t intFlags) -+{ -+ ASSERT_COND(h_FmPcdPlcr); -+ XX_UnlockIntrSpinlock(((t_FmPcdPlcr*)h_FmPcdPlcr)->h_SwSpinlock, intFlags); -+} -+ -+static bool IsProfileShared(t_Handle h_FmPcd, uint16_t absoluteProfileId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint16_t i; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPcd, E_INVALID_HANDLE, FALSE); -+ -+ for (i=0;ip_FmPcdPlcr->numOfSharedProfiles;i++) -+ if (p_FmPcd->p_FmPcdPlcr->sharedProfilesIds[i] == absoluteProfileId) -+ return TRUE; -+ return FALSE; -+} -+ -+static t_Error SetProfileNia(t_FmPcd *p_FmPcd, e_FmPcdEngine nextEngine, u_FmPcdPlcrNextEngineParams *p_NextEngineParams, uint32_t *nextAction) -+{ -+ uint32_t nia; -+ uint16_t absoluteProfileId; -+ uint8_t relativeSchemeId, physicalSchemeId; -+ -+ nia = FM_PCD_PLCR_NIA_VALID; -+ -+ switch (nextEngine) -+ { -+ case e_FM_PCD_DONE : -+ switch (p_NextEngineParams->action) -+ { -+ case e_FM_PCD_DROP_FRAME : -+ nia |= GET_NIA_BMI_AC_DISCARD_FRAME(p_FmPcd); -+ break; -+ case e_FM_PCD_ENQ_FRAME: -+ nia |= GET_NIA_BMI_AC_ENQ_FRAME(p_FmPcd); -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ break; -+ case e_FM_PCD_KG: -+ physicalSchemeId = FmPcdKgGetSchemeId(p_NextEngineParams->h_DirectScheme); -+ relativeSchemeId = FmPcdKgGetRelativeSchemeId(p_FmPcd, physicalSchemeId); -+ if (relativeSchemeId >= FM_PCD_KG_NUM_OF_SCHEMES) -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, NO_MSG); -+ if (!FmPcdKgIsSchemeValidSw(p_NextEngineParams->h_DirectScheme)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Invalid direct scheme.")); -+ if (!KgIsSchemeAlwaysDirect(p_FmPcd, relativeSchemeId)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Policer Profile may point only to a scheme that is always direct.")); -+ nia |= NIA_ENG_KG | NIA_KG_DIRECT | physicalSchemeId; -+ break; -+ case e_FM_PCD_PLCR: -+ absoluteProfileId = ((t_FmPcdPlcrProfile *)p_NextEngineParams->h_Profile)->absoluteProfileId; -+ if (!IsProfileShared(p_FmPcd, absoluteProfileId)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Next profile must be a shared profile")); -+ if (!FmPcdPlcrIsProfileValid(p_FmPcd, absoluteProfileId)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Invalid profile ")); -+ nia |= NIA_ENG_PLCR | NIA_PLCR_ABSOLUTE | absoluteProfileId; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ -+ *nextAction = nia; -+ -+ return E_OK; -+} -+ -+static uint32_t CalcFPP(uint32_t fpp) -+{ -+ if (fpp > 15) -+ return 15 - (0x1f - fpp); -+ else -+ return 16 + fpp; -+} -+ -+static void GetInfoRateReg(e_FmPcdPlcrRateMode rateMode, -+ uint32_t rate, -+ uint64_t tsuInTenthNano, -+ uint32_t fppShift, -+ uint64_t *p_Integer, -+ uint64_t *p_Fraction) -+{ -+ uint64_t tmp, div; -+ -+ if (rateMode == e_FM_PCD_PLCR_BYTE_MODE) -+ { -+ /* now we calculate the initial integer for the bigger rate */ -+ /* from Kbps to Bytes/TSU */ -+ tmp = (uint64_t)rate; -+ tmp *= 1000; /* kb --> b */ -+ tmp *= tsuInTenthNano; /* bps --> bpTsu(in 10nano) */ -+ -+ div = 1000000000; /* nano */ -+ div *= 10; /* 10 nano */ -+ div *= 8; /* bit to byte */ -+ } -+ else -+ { -+ /* now we calculate the initial integer for the bigger rate */ -+ /* from Kbps to Bytes/TSU */ -+ tmp = (uint64_t)rate; -+ tmp *= tsuInTenthNano; /* bps --> bpTsu(in 10nano) */ -+ -+ div = 1000000000; /* nano */ -+ div *= 10; /* 10 nano */ -+ } -+ *p_Integer = (tmp<committedInfoRate > p_NonPassthroughAlgParam->peakOrExcessInfoRate) -+ GetInfoRateReg(p_NonPassthroughAlgParam->rateMode, p_NonPassthroughAlgParam->committedInfoRate, tsuInTenthNanos, 0, &integer, &fraction); -+ else -+ GetInfoRateReg(p_NonPassthroughAlgParam->rateMode, p_NonPassthroughAlgParam->peakOrExcessInfoRate, tsuInTenthNanos, 0, &integer, &fraction); -+ -+ /* we shift integer, as in cir/pir it is represented by the MSB 16 bits, and -+ * the LSB bits are for the fraction */ -+ temp = (uint32_t)((integer<<16) & 0x00000000FFFFFFFF); -+ /* temp is effected by the rate. For low rates it may be as low as 0, and then we'll -+ * take max FP = 31. -+ * For high rates it will never exceed the 32 bit reg (after the 16 shift), as it is -+ * limited by the 10G physical port. -+ */ -+ if (temp != 0) -+ { -+ /* In this case, the largest rate integer is non 0, if it does not occupy all (high) 16 -+ * bits of the PIR_EIR we can use this fact and enlarge it to occupy all 16 bits. -+ * The logic is to have as many bits for integer in the higher rates, but if we have "0"s -+ * in the integer part of the cir/pir register, than these bits are wasted. So we want -+ * to use these bits for the fraction. in this way we will have for fraction - the number -+ * of "0" bits and the rest - for integer. -+ * In other words: For each bit we shift it in PIR_EIR, we move the FP in the TS -+ * one bit to the left - preserving the relationship and achieving more bits -+ * for integer in the TS. -+ */ -+ -+ /* count zeroes left of the higher used bit (in order to shift the value such that -+ * unused bits may be used for fraction). -+ */ -+ while ((temp & 0x80000000) == 0) -+ { -+ temp = temp << 1; -+ fppShift++; -+ } -+ if (fppShift > 15) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_SELECTION, ("timeStampPeriod to Information rate ratio is too small")); -+ return; -+ } -+ } -+ else -+ { -+ temp = (uint32_t)fraction; /* fraction will alyas be smaller than 2^16 */ -+ if (!temp) -+ /* integer and fraction are 0, we set FP to its max val */ -+ fppShift = 31; -+ else -+ { -+ /* integer was 0 but fraction is not. FP is 16 for the fraction, -+ * + all left zeroes of the fraction. */ -+ fppShift=16; -+ /* count zeroes left of the higher used bit (in order to shift the value such that -+ * unused bits may be used for fraction). -+ */ -+ while ((temp & 0x8000) == 0) -+ { -+ temp = temp << 1; -+ fppShift++; -+ } -+ } -+ } -+ -+ /* -+ * This means that the FM TS register will now be used so that 'fppShift' bits are for -+ * fraction and the rest for integer */ -+ /* now we re-calculate cir and pir_eir with the calculated FP */ -+ GetInfoRateReg(p_NonPassthroughAlgParam->rateMode, p_NonPassthroughAlgParam->committedInfoRate, tsuInTenthNanos, fppShift, &integer, &fraction); -+ *cir = (uint32_t)(integer << 16 | (fraction & 0xFFFF)); -+ GetInfoRateReg(p_NonPassthroughAlgParam->rateMode, p_NonPassthroughAlgParam->peakOrExcessInfoRate, tsuInTenthNanos, fppShift, &integer, &fraction); -+ *pir_eir = (uint32_t)(integer << 16 | (fraction & 0xFFFF)); -+ -+ *cbs = p_NonPassthroughAlgParam->committedBurstSize; -+ *pbs_ebs = p_NonPassthroughAlgParam->peakOrExcessBurstSize; -+ -+ /* convert FP as it should be written to reg. -+ * 0-15 --> 16-31 -+ * 16-31 --> 0-15 -+ */ -+ *fpp = CalcFPP(fppShift); -+} -+ -+static void WritePar(t_FmPcd *p_FmPcd, uint32_t par) -+{ -+ t_FmPcdPlcrRegs *p_FmPcdPlcrRegs = p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs; -+ -+ ASSERT_COND(FmIsMaster(p_FmPcd->h_Fm)); -+ WRITE_UINT32(p_FmPcdPlcrRegs->fmpl_par, par); -+ -+ while (GET_UINT32(p_FmPcdPlcrRegs->fmpl_par) & FM_PCD_PLCR_PAR_GO) ; -+} -+ -+static t_Error BuildProfileRegs(t_FmPcd *p_FmPcd, -+ t_FmPcdPlcrProfileParams *p_ProfileParams, -+ t_FmPcdPlcrProfileRegs *p_PlcrRegs) -+{ -+ t_Error err = E_OK; -+ uint32_t pemode, gnia, ynia, rnia, bitFor1Micro; -+ -+ ASSERT_COND(p_FmPcd); -+ -+ bitFor1Micro = FmGetTimeStampScale(p_FmPcd->h_Fm); -+ if (bitFor1Micro == 0) -+ RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, ("Timestamp scale")); -+ -+/* Set G, Y, R Nia */ -+ err = SetProfileNia(p_FmPcd, p_ProfileParams->nextEngineOnGreen, &(p_ProfileParams->paramsOnGreen), &gnia); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ err = SetProfileNia(p_FmPcd, p_ProfileParams->nextEngineOnYellow, &(p_ProfileParams->paramsOnYellow), &ynia); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ err = SetProfileNia(p_FmPcd, p_ProfileParams->nextEngineOnRed, &(p_ProfileParams->paramsOnRed), &rnia); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+/* Mode fmpl_pemode */ -+ pemode = FM_PCD_PLCR_PEMODE_PI; -+ -+ switch (p_ProfileParams->algSelection) -+ { -+ case e_FM_PCD_PLCR_PASS_THROUGH: -+ p_PlcrRegs->fmpl_pecir = 0; -+ p_PlcrRegs->fmpl_pecbs = 0; -+ p_PlcrRegs->fmpl_pepepir_eir = 0; -+ p_PlcrRegs->fmpl_pepbs_ebs = 0; -+ p_PlcrRegs->fmpl_pelts = 0; -+ p_PlcrRegs->fmpl_pects = 0; -+ p_PlcrRegs->fmpl_pepts_ets = 0; -+ pemode &= ~FM_PCD_PLCR_PEMODE_ALG_MASK; -+ switch (p_ProfileParams->colorMode) -+ { -+ case e_FM_PCD_PLCR_COLOR_BLIND: -+ pemode |= FM_PCD_PLCR_PEMODE_CBLND; -+ switch (p_ProfileParams->color.dfltColor) -+ { -+ case e_FM_PCD_PLCR_GREEN: -+ pemode &= ~FM_PCD_PLCR_PEMODE_DEFC_MASK; -+ break; -+ case e_FM_PCD_PLCR_YELLOW: -+ pemode |= FM_PCD_PLCR_PEMODE_DEFC_Y; -+ break; -+ case e_FM_PCD_PLCR_RED: -+ pemode |= FM_PCD_PLCR_PEMODE_DEFC_R; -+ break; -+ case e_FM_PCD_PLCR_OVERRIDE: -+ pemode |= FM_PCD_PLCR_PEMODE_DEFC_OVERRIDE; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ -+ break; -+ case e_FM_PCD_PLCR_COLOR_AWARE: -+ pemode &= ~FM_PCD_PLCR_PEMODE_CBLND; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ break; -+ -+ case e_FM_PCD_PLCR_RFC_2698: -+ /* Select algorithm MODE[ALG] = "01" */ -+ pemode |= FM_PCD_PLCR_PEMODE_ALG_RFC2698; -+ if (p_ProfileParams->nonPassthroughAlgParams.committedInfoRate > p_ProfileParams->nonPassthroughAlgParams.peakOrExcessInfoRate) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("in RFC2698 Peak rate must be equal or larger than committedInfoRate.")); -+ goto cont_rfc; -+ case e_FM_PCD_PLCR_RFC_4115: -+ /* Select algorithm MODE[ALG] = "10" */ -+ pemode |= FM_PCD_PLCR_PEMODE_ALG_RFC4115; -+cont_rfc: -+ /* Select Color-Blind / Color-Aware operation (MODE[CBLND]) */ -+ switch (p_ProfileParams->colorMode) -+ { -+ case e_FM_PCD_PLCR_COLOR_BLIND: -+ pemode |= FM_PCD_PLCR_PEMODE_CBLND; -+ break; -+ case e_FM_PCD_PLCR_COLOR_AWARE: -+ pemode &= ~FM_PCD_PLCR_PEMODE_CBLND; -+ /*In color aware more select override color interpretation (MODE[OVCLR]) */ -+ switch (p_ProfileParams->color.override) -+ { -+ case e_FM_PCD_PLCR_GREEN: -+ pemode &= ~FM_PCD_PLCR_PEMODE_OVCLR_MASK; -+ break; -+ case e_FM_PCD_PLCR_YELLOW: -+ pemode |= FM_PCD_PLCR_PEMODE_OVCLR_Y; -+ break; -+ case e_FM_PCD_PLCR_RED: -+ pemode |= FM_PCD_PLCR_PEMODE_OVCLR_R; -+ break; -+ case e_FM_PCD_PLCR_OVERRIDE: -+ pemode |= FM_PCD_PLCR_PEMODE_OVCLR_G_NC; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ /* Select Measurement Unit Mode to BYTE or PACKET (MODE[PKT]) */ -+ switch (p_ProfileParams->nonPassthroughAlgParams.rateMode) -+ { -+ case e_FM_PCD_PLCR_BYTE_MODE : -+ pemode &= ~FM_PCD_PLCR_PEMODE_PKT; -+ switch (p_ProfileParams->nonPassthroughAlgParams.byteModeParams.frameLengthSelection) -+ { -+ case e_FM_PCD_PLCR_L2_FRM_LEN: -+ pemode |= FM_PCD_PLCR_PEMODE_FLS_L2; -+ break; -+ case e_FM_PCD_PLCR_L3_FRM_LEN: -+ pemode |= FM_PCD_PLCR_PEMODE_FLS_L3; -+ break; -+ case e_FM_PCD_PLCR_L4_FRM_LEN: -+ pemode |= FM_PCD_PLCR_PEMODE_FLS_L4; -+ break; -+ case e_FM_PCD_PLCR_FULL_FRM_LEN: -+ pemode |= FM_PCD_PLCR_PEMODE_FLS_FULL; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ switch (p_ProfileParams->nonPassthroughAlgParams.byteModeParams.rollBackFrameSelection) -+ { -+ case e_FM_PCD_PLCR_ROLLBACK_L2_FRM_LEN: -+ pemode &= ~FM_PCD_PLCR_PEMODE_RBFLS; -+ break; -+ case e_FM_PCD_PLCR_ROLLBACK_FULL_FRM_LEN: -+ pemode |= FM_PCD_PLCR_PEMODE_RBFLS; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ break; -+ case e_FM_PCD_PLCR_PACKET_MODE : -+ pemode |= FM_PCD_PLCR_PEMODE_PKT; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ /* Select timeStamp floating point position (MODE[FPP]) to fit the actual traffic rates. For PACKET -+ mode with low traffic rates move the fixed point to the left to increase fraction accuracy. For BYTE -+ mode with high traffic rates move the fixed point to the right to increase integer accuracy. */ -+ -+ /* Configure Traffic Parameters*/ -+ { -+ uint32_t cir=0, cbs=0, pir_eir=0, pbs_ebs=0, fpp=0; -+ -+ CalcRates(bitFor1Micro, &p_ProfileParams->nonPassthroughAlgParams, &cir, &cbs, &pir_eir, &pbs_ebs, &fpp); -+ -+ /* Set Committed Information Rate (CIR) */ -+ p_PlcrRegs->fmpl_pecir = cir; -+ /* Set Committed Burst Size (CBS). */ -+ p_PlcrRegs->fmpl_pecbs = cbs; -+ /* Set Peak Information Rate (PIR_EIR used as PIR) */ -+ p_PlcrRegs->fmpl_pepepir_eir = pir_eir; -+ /* Set Peak Burst Size (PBS_EBS used as PBS) */ -+ p_PlcrRegs->fmpl_pepbs_ebs = pbs_ebs; -+ -+ /* Initialize the Metering Buckets to be full (write them with 0xFFFFFFFF. */ -+ /* Peak Rate Token Bucket Size (PTS_ETS used as PTS) */ -+ p_PlcrRegs->fmpl_pepts_ets = 0xFFFFFFFF; -+ /* Committed Rate Token Bucket Size (CTS) */ -+ p_PlcrRegs->fmpl_pects = 0xFFFFFFFF; -+ -+ /* Set the FPP based on calculation */ -+ pemode |= (fpp << FM_PCD_PLCR_PEMODE_FPP_SHIFT); -+ } -+ break; /* FM_PCD_PLCR_PEMODE_ALG_RFC2698 , FM_PCD_PLCR_PEMODE_ALG_RFC4115 */ -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ -+ p_PlcrRegs->fmpl_pemode = pemode; -+ -+ p_PlcrRegs->fmpl_pegnia = gnia; -+ p_PlcrRegs->fmpl_peynia = ynia; -+ p_PlcrRegs->fmpl_pernia = rnia; -+ -+ /* Zero Counters */ -+ p_PlcrRegs->fmpl_pegpc = 0; -+ p_PlcrRegs->fmpl_peypc = 0; -+ p_PlcrRegs->fmpl_perpc = 0; -+ p_PlcrRegs->fmpl_perypc = 0; -+ p_PlcrRegs->fmpl_perrpc = 0; -+ -+ return E_OK; -+} -+ -+static t_Error AllocSharedProfiles(t_FmPcd *p_FmPcd, uint16_t numOfProfiles, uint16_t *profilesIds) -+{ -+ uint32_t profilesFound; -+ uint16_t i, k=0; -+ uint32_t intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ -+ if (!numOfProfiles) -+ return E_OK; -+ -+ if (numOfProfiles>FM_PCD_PLCR_NUM_ENTRIES) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, ("numProfiles is too big.")); -+ -+ intFlags = PlcrSwLock(p_FmPcd->p_FmPcdPlcr); -+ /* Find numOfProfiles free profiles (may be spread) */ -+ profilesFound = 0; -+ for (i=0;ip_FmPcdPlcr->profiles[i].profilesMng.allocated) -+ { -+ profilesFound++; -+ profilesIds[k] = i; -+ k++; -+ if (profilesFound == numOfProfiles) -+ break; -+ } -+ -+ if (profilesFound != numOfProfiles) -+ { -+ PlcrSwUnlock(p_FmPcd->p_FmPcdPlcr, intFlags); -+ RETURN_ERROR(MAJOR, E_INVALID_STATE,NO_MSG); -+ } -+ -+ for (i = 0;ip_FmPcdPlcr->profiles[profilesIds[i]].profilesMng.allocated = TRUE; -+ p_FmPcd->p_FmPcdPlcr->profiles[profilesIds[i]].profilesMng.ownerId = 0; -+ } -+ PlcrSwUnlock(p_FmPcd->p_FmPcdPlcr, intFlags); -+ -+ return E_OK; -+} -+ -+static void FreeSharedProfiles(t_FmPcd *p_FmPcd, uint16_t numOfProfiles, uint16_t *profilesIds) -+{ -+ uint16_t i; -+ -+ SANITY_CHECK_RETURN(p_FmPcd, E_INVALID_HANDLE); -+ -+ ASSERT_COND(numOfProfiles); -+ -+ for (i=0; i < numOfProfiles; i++) -+ { -+ ASSERT_COND(p_FmPcd->p_FmPcdPlcr->profiles[profilesIds[i]].profilesMng.allocated); -+ p_FmPcd->p_FmPcdPlcr->profiles[profilesIds[i]].profilesMng.allocated = FALSE; -+ p_FmPcd->p_FmPcdPlcr->profiles[profilesIds[i]].profilesMng.ownerId = p_FmPcd->guestId; -+ } -+} -+ -+static void UpdateRequiredActionFlag(t_Handle h_FmPcd, uint16_t absoluteProfileId, bool set) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ /* this routine is protected by calling routine */ -+ -+ ASSERT_COND(p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].valid); -+ -+ if (set) -+ p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].requiredActionFlag = TRUE; -+ else -+ { -+ p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].requiredAction = 0; -+ p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].requiredActionFlag = FALSE; -+ } -+} -+ -+/*********************************************/ -+/*............Policer Exception..............*/ -+/*********************************************/ -+static void EventsCB(t_Handle h_FmPcd) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ uint32_t event, mask, force; -+ -+ ASSERT_COND(FmIsMaster(p_FmPcd->h_Fm)); -+ event = GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_evr); -+ mask = GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_ier); -+ -+ event &= mask; -+ -+ /* clear the forced events */ -+ force = GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_ifr); -+ if (force & event) -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_ifr, force & ~event); -+ -+ -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_evr, event); -+ -+ if (event & FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE) -+ p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE); -+ if (event & FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE) -+ p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_PLCR_EXCEPTION_ATOMIC_ACTION_COMPLETE); -+} -+ -+/* ..... */ -+ -+static void ErrorExceptionsCB(t_Handle h_FmPcd) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ uint32_t event, force, captureReg, mask; -+ -+ ASSERT_COND(FmIsMaster(p_FmPcd->h_Fm)); -+ event = GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_eevr); -+ mask = GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_eier); -+ -+ event &= mask; -+ -+ /* clear the forced events */ -+ force = GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_eifr); -+ if (force & event) -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_eifr, force & ~event); -+ -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_eevr, event); -+ -+ if (event & FM_PCD_PLCR_DOUBLE_ECC) -+ p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC); -+ if (event & FM_PCD_PLCR_INIT_ENTRY_ERROR) -+ { -+ captureReg = GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_upcr); -+ /*ASSERT_COND(captureReg & PLCR_ERR_UNINIT_CAP); -+ p_UnInitCapt->profileNum = (uint8_t)(captureReg & PLCR_ERR_UNINIT_NUM_MASK); -+ p_UnInitCapt->portId = (uint8_t)((captureReg & PLCR_ERR_UNINIT_PID_MASK) >>PLCR_ERR_UNINIT_PID_SHIFT) ; -+ p_UnInitCapt->absolute = (bool)(captureReg & PLCR_ERR_UNINIT_ABSOLUTE_MASK);*/ -+ p_FmPcd->f_FmPcdIndexedException(p_FmPcd->h_App,e_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR,(uint16_t)(captureReg & PLCR_ERR_UNINIT_NUM_MASK)); -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_upcr, PLCR_ERR_UNINIT_CAP); -+ } -+} -+ -+ -+/*****************************************************************************/ -+/* Inter-module API routines */ -+/*****************************************************************************/ -+ -+t_Handle PlcrConfig(t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams) -+{ -+ t_FmPcdPlcr *p_FmPcdPlcr; -+ uint16_t i=0; -+ -+ UNUSED(p_FmPcd); -+ UNUSED(p_FmPcdParams); -+ -+ p_FmPcdPlcr = (t_FmPcdPlcr *) XX_Malloc(sizeof(t_FmPcdPlcr)); -+ if (!p_FmPcdPlcr) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM Policer structure allocation FAILED")); -+ return NULL; -+ } -+ memset(p_FmPcdPlcr, 0, sizeof(t_FmPcdPlcr)); -+ if (p_FmPcd->guestId == NCSW_MASTER_ID) -+ { -+ p_FmPcdPlcr->p_FmPcdPlcrRegs = (t_FmPcdPlcrRegs *)UINT_TO_PTR(FmGetPcdPlcrBaseAddr(p_FmPcdParams->h_Fm)); -+ p_FmPcd->p_FmPcdDriverParam->plcrAutoRefresh = DEFAULT_plcrAutoRefresh; -+ p_FmPcd->exceptions |= (DEFAULT_fmPcdPlcrExceptions | DEFAULT_fmPcdPlcrErrorExceptions); -+ } -+ -+ p_FmPcdPlcr->numOfSharedProfiles = DEFAULT_numOfSharedPlcrProfiles; -+ -+ p_FmPcdPlcr->partPlcrProfilesBase = p_FmPcdParams->partPlcrProfilesBase; -+ p_FmPcdPlcr->partNumOfPlcrProfiles = p_FmPcdParams->partNumOfPlcrProfiles; -+ /* for backward compatabilty. if no policer profile, will set automatically to the max */ -+ if ((p_FmPcd->guestId == NCSW_MASTER_ID) && -+ (p_FmPcdPlcr->partNumOfPlcrProfiles == 0)) -+ p_FmPcdPlcr->partNumOfPlcrProfiles = FM_PCD_PLCR_NUM_ENTRIES; -+ -+ for (i=0; iprofiles[i].profilesMng.ownerId = (uint8_t)ILLEGAL_BASE; -+ -+ return p_FmPcdPlcr; -+} -+ -+t_Error PlcrInit(t_FmPcd *p_FmPcd) -+{ -+ t_FmPcdDriverParam *p_Param = p_FmPcd->p_FmPcdDriverParam; -+ t_FmPcdPlcr *p_FmPcdPlcr = p_FmPcd->p_FmPcdPlcr; -+ t_FmPcdPlcrRegs *p_Regs = p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs; -+ t_Error err = E_OK; -+ uint32_t tmpReg32 = 0; -+ uint16_t base; -+ -+ if ((p_FmPcdPlcr->partPlcrProfilesBase + p_FmPcdPlcr->partNumOfPlcrProfiles) > FM_PCD_PLCR_NUM_ENTRIES) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("partPlcrProfilesBase+partNumOfPlcrProfiles out of range!!!")); -+ -+ p_FmPcdPlcr->h_HwSpinlock = XX_InitSpinlock(); -+ if (!p_FmPcdPlcr->h_HwSpinlock) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FM Policer HW spinlock")); -+ -+ p_FmPcdPlcr->h_SwSpinlock = XX_InitSpinlock(); -+ if (!p_FmPcdPlcr->h_SwSpinlock) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FM Policer SW spinlock")); -+ -+ base = PlcrAllocProfilesForPartition(p_FmPcd, -+ p_FmPcdPlcr->partPlcrProfilesBase, -+ p_FmPcdPlcr->partNumOfPlcrProfiles, -+ p_FmPcd->guestId); -+ if (base == (uint16_t)ILLEGAL_BASE) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); -+ -+ if (p_FmPcdPlcr->numOfSharedProfiles) -+ { -+ err = AllocSharedProfiles(p_FmPcd, -+ p_FmPcdPlcr->numOfSharedProfiles, -+ p_FmPcdPlcr->sharedProfilesIds); -+ if (err) -+ RETURN_ERROR(MAJOR, err,NO_MSG); -+ } -+ -+ if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ return E_OK; -+ -+ /**********************FMPL_GCR******************/ -+ tmpReg32 = 0; -+ tmpReg32 |= FM_PCD_PLCR_GCR_STEN; -+ if (p_Param->plcrAutoRefresh) -+ tmpReg32 |= FM_PCD_PLCR_GCR_DAR; -+ tmpReg32 |= GET_NIA_BMI_AC_ENQ_FRAME(p_FmPcd); -+ -+ WRITE_UINT32(p_Regs->fmpl_gcr, tmpReg32); -+ /**********************FMPL_GCR******************/ -+ -+ /**********************FMPL_EEVR******************/ -+ WRITE_UINT32(p_Regs->fmpl_eevr, (FM_PCD_PLCR_DOUBLE_ECC | FM_PCD_PLCR_INIT_ENTRY_ERROR)); -+ /**********************FMPL_EEVR******************/ -+ /**********************FMPL_EIER******************/ -+ tmpReg32 = 0; -+ if (p_FmPcd->exceptions & FM_PCD_EX_PLCR_DOUBLE_ECC) -+ { -+ FmEnableRamsEcc(p_FmPcd->h_Fm); -+ tmpReg32 |= FM_PCD_PLCR_DOUBLE_ECC; -+ } -+ if (p_FmPcd->exceptions & FM_PCD_EX_PLCR_INIT_ENTRY_ERROR) -+ tmpReg32 |= FM_PCD_PLCR_INIT_ENTRY_ERROR; -+ WRITE_UINT32(p_Regs->fmpl_eier, tmpReg32); -+ /**********************FMPL_EIER******************/ -+ -+ /**********************FMPL_EVR******************/ -+ WRITE_UINT32(p_Regs->fmpl_evr, (FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE | FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE)); -+ /**********************FMPL_EVR******************/ -+ /**********************FMPL_IER******************/ -+ tmpReg32 = 0; -+ if (p_FmPcd->exceptions & FM_PCD_EX_PLCR_PRAM_SELF_INIT_COMPLETE) -+ tmpReg32 |= FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE; -+ if (p_FmPcd->exceptions & FM_PCD_EX_PLCR_ATOMIC_ACTION_COMPLETE) -+ tmpReg32 |= FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE; -+ WRITE_UINT32(p_Regs->fmpl_ier, tmpReg32); -+ /**********************FMPL_IER******************/ -+ -+ /* register even if no interrupts enabled, to allow future enablement */ -+ FmRegisterIntr(p_FmPcd->h_Fm, -+ e_FM_MOD_PLCR, -+ 0, -+ e_FM_INTR_TYPE_ERR, -+ ErrorExceptionsCB, -+ p_FmPcd); -+ FmRegisterIntr(p_FmPcd->h_Fm, -+ e_FM_MOD_PLCR, -+ 0, -+ e_FM_INTR_TYPE_NORMAL, -+ EventsCB, -+ p_FmPcd); -+ -+ /* driver initializes one DFLT profile at the last entry*/ -+ /**********************FMPL_DPMR******************/ -+ tmpReg32 = 0; -+ WRITE_UINT32(p_Regs->fmpl_dpmr, tmpReg32); -+ p_FmPcd->p_FmPcdPlcr->profiles[0].profilesMng.allocated = TRUE; -+ -+ return E_OK; -+} -+ -+t_Error PlcrFree(t_FmPcd *p_FmPcd) -+{ -+ FmUnregisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PLCR, 0, e_FM_INTR_TYPE_ERR); -+ FmUnregisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PLCR, 0, e_FM_INTR_TYPE_NORMAL); -+ -+ if (p_FmPcd->p_FmPcdPlcr->numOfSharedProfiles) -+ FreeSharedProfiles(p_FmPcd, -+ p_FmPcd->p_FmPcdPlcr->numOfSharedProfiles, -+ p_FmPcd->p_FmPcdPlcr->sharedProfilesIds); -+ -+ if (p_FmPcd->p_FmPcdPlcr->partNumOfPlcrProfiles) -+ PlcrFreeProfilesForPartition(p_FmPcd, -+ p_FmPcd->p_FmPcdPlcr->partPlcrProfilesBase, -+ p_FmPcd->p_FmPcdPlcr->partNumOfPlcrProfiles, -+ p_FmPcd->guestId); -+ -+ if (p_FmPcd->p_FmPcdPlcr->h_SwSpinlock) -+ XX_FreeSpinlock(p_FmPcd->p_FmPcdPlcr->h_SwSpinlock); -+ -+ if (p_FmPcd->p_FmPcdPlcr->h_HwSpinlock) -+ XX_FreeSpinlock(p_FmPcd->p_FmPcdPlcr->h_HwSpinlock); -+ -+ return E_OK; -+} -+ -+void PlcrEnable(t_FmPcd *p_FmPcd) -+{ -+ t_FmPcdPlcrRegs *p_Regs = p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs; -+ -+ WRITE_UINT32(p_Regs->fmpl_gcr, GET_UINT32(p_Regs->fmpl_gcr) | FM_PCD_PLCR_GCR_EN); -+} -+ -+void PlcrDisable(t_FmPcd *p_FmPcd) -+{ -+ t_FmPcdPlcrRegs *p_Regs = p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs; -+ -+ WRITE_UINT32(p_Regs->fmpl_gcr, GET_UINT32(p_Regs->fmpl_gcr) & ~FM_PCD_PLCR_GCR_EN); -+} -+ -+uint16_t PlcrAllocProfilesForPartition(t_FmPcd *p_FmPcd, uint16_t base, uint16_t numOfProfiles, uint8_t guestId) -+{ -+ uint32_t intFlags; -+ uint16_t profilesFound = 0; -+ int i = 0; -+ -+ ASSERT_COND(p_FmPcd); -+ ASSERT_COND(p_FmPcd->p_FmPcdPlcr); -+ -+ if (!numOfProfiles) -+ return 0; -+ -+ if ((numOfProfiles > FM_PCD_PLCR_NUM_ENTRIES) || -+ (base + numOfProfiles > FM_PCD_PLCR_NUM_ENTRIES)) -+ return (uint16_t)ILLEGAL_BASE; -+ -+ if (p_FmPcd->h_IpcSession) -+ { -+ t_FmIpcResourceAllocParams ipcAllocParams; -+ t_FmPcdIpcMsg msg; -+ t_FmPcdIpcReply reply; -+ t_Error err; -+ uint32_t replyLength; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ memset(&ipcAllocParams, 0, sizeof(t_FmIpcResourceAllocParams)); -+ ipcAllocParams.guestId = p_FmPcd->guestId; -+ ipcAllocParams.num = p_FmPcd->p_FmPcdPlcr->partNumOfPlcrProfiles; -+ ipcAllocParams.base = p_FmPcd->p_FmPcdPlcr->partPlcrProfilesBase; -+ msg.msgId = FM_PCD_ALLOC_PROFILES; -+ memcpy(msg.msgBody, &ipcAllocParams, sizeof(t_FmIpcResourceAllocParams)); -+ replyLength = sizeof(uint32_t) + sizeof(uint16_t); -+ err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(t_FmIpcResourceAllocParams), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL); -+ if ((err != E_OK) || -+ (replyLength != (sizeof(uint32_t) + sizeof(uint16_t)))) -+ { -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ return (uint16_t)ILLEGAL_BASE; -+ } -+ else -+ memcpy((uint8_t*)&p_FmPcd->p_FmPcdPlcr->partPlcrProfilesBase, reply.replyBody, sizeof(uint16_t)); -+ if (p_FmPcd->p_FmPcdPlcr->partPlcrProfilesBase == (uint16_t)ILLEGAL_BASE) -+ { -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ return (uint16_t)ILLEGAL_BASE; -+ } -+ } -+ else if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ { -+ DBG(WARNING, ("FM Guest mode, without IPC - can't validate Policer-profiles range!")); -+ return (uint16_t)ILLEGAL_BASE; -+ } -+ -+ intFlags = XX_LockIntrSpinlock(p_FmPcd->h_Spinlock); -+ for (i=base; i<(base+numOfProfiles); i++) -+ if (p_FmPcd->p_FmPcdPlcr->profiles[i].profilesMng.ownerId == (uint8_t)ILLEGAL_BASE) -+ profilesFound++; -+ else -+ break; -+ -+ if (profilesFound == numOfProfiles) -+ for (i=base; i<(base+numOfProfiles); i++) -+ p_FmPcd->p_FmPcdPlcr->profiles[i].profilesMng.ownerId = guestId; -+ else -+ { -+ XX_UnlockIntrSpinlock(p_FmPcd->h_Spinlock, intFlags); -+ return (uint16_t)ILLEGAL_BASE; -+ } -+ XX_UnlockIntrSpinlock(p_FmPcd->h_Spinlock, intFlags); -+ -+ return base; -+} -+ -+void PlcrFreeProfilesForPartition(t_FmPcd *p_FmPcd, uint16_t base, uint16_t numOfProfiles, uint8_t guestId) -+{ -+ int i = 0; -+ -+ ASSERT_COND(p_FmPcd); -+ ASSERT_COND(p_FmPcd->p_FmPcdPlcr); -+ -+ if (p_FmPcd->h_IpcSession) -+ { -+ t_FmIpcResourceAllocParams ipcAllocParams; -+ t_FmPcdIpcMsg msg; -+ t_Error err; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&ipcAllocParams, 0, sizeof(t_FmIpcResourceAllocParams)); -+ ipcAllocParams.guestId = p_FmPcd->guestId; -+ ipcAllocParams.num = p_FmPcd->p_FmPcdPlcr->partNumOfPlcrProfiles; -+ ipcAllocParams.base = p_FmPcd->p_FmPcdPlcr->partPlcrProfilesBase; -+ msg.msgId = FM_PCD_FREE_PROFILES; -+ memcpy(msg.msgBody, &ipcAllocParams, sizeof(t_FmIpcResourceAllocParams)); -+ err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(t_FmIpcResourceAllocParams), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ return; -+ } -+ else if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ { -+ DBG(WARNING, ("FM Guest mode, without IPC - can't validate Policer-profiles range!")); -+ return; -+ } -+ -+ for (i=base; i<(base+numOfProfiles); i++) -+ { -+ if (p_FmPcd->p_FmPcdPlcr->profiles[i].profilesMng.ownerId == guestId) -+ p_FmPcd->p_FmPcdPlcr->profiles[i].profilesMng.ownerId = (uint8_t)ILLEGAL_BASE; -+ else -+ DBG(WARNING, ("Request for freeing storage profile window which wasn't allocated to this partition")); -+ } -+} -+ -+t_Error PlcrSetPortProfiles(t_FmPcd *p_FmPcd, -+ uint8_t hardwarePortId, -+ uint16_t numOfProfiles, -+ uint16_t base) -+{ -+ t_FmPcdPlcrRegs *p_Regs = p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs; -+ uint32_t log2Num, tmpReg32; -+ -+ if ((p_FmPcd->guestId != NCSW_MASTER_ID) && -+ !p_Regs && -+ p_FmPcd->h_IpcSession) -+ { -+ t_FmIpcResourceAllocParams ipcAllocParams; -+ t_FmPcdIpcMsg msg; -+ t_Error err; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&ipcAllocParams, 0, sizeof(t_FmIpcResourceAllocParams)); -+ ipcAllocParams.guestId = hardwarePortId; -+ ipcAllocParams.num = numOfProfiles; -+ ipcAllocParams.base = base; -+ msg.msgId = FM_PCD_SET_PORT_PROFILES; -+ memcpy(msg.msgBody, &ipcAllocParams, sizeof(t_FmIpcResourceAllocParams)); -+ err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(t_FmIpcResourceAllocParams), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ return E_OK; -+ } -+ else if (!p_Regs) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("Either IPC or 'baseAddress' is required!")); -+ -+ ASSERT_COND(IN_RANGE(1, hardwarePortId, 63)); -+ -+ if (GET_UINT32(p_Regs->fmpl_pmr[hardwarePortId-1]) & FM_PCD_PLCR_PMR_V) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("The requesting port has already an allocated profiles window.")); -+ -+ /**********************FMPL_PMRx******************/ -+ LOG2((uint64_t)numOfProfiles, log2Num); -+ tmpReg32 = base; -+ tmpReg32 |= log2Num << 16; -+ tmpReg32 |= FM_PCD_PLCR_PMR_V; -+ WRITE_UINT32(p_Regs->fmpl_pmr[hardwarePortId-1], tmpReg32); -+ -+ return E_OK; -+} -+ -+t_Error PlcrClearPortProfiles(t_FmPcd *p_FmPcd, uint8_t hardwarePortId) -+{ -+ t_FmPcdPlcrRegs *p_Regs = p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs; -+ -+ if ((p_FmPcd->guestId != NCSW_MASTER_ID) && -+ !p_Regs && -+ p_FmPcd->h_IpcSession) -+ { -+ t_FmIpcResourceAllocParams ipcAllocParams; -+ t_FmPcdIpcMsg msg; -+ t_Error err; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&ipcAllocParams, 0, sizeof(t_FmIpcResourceAllocParams)); -+ ipcAllocParams.guestId = hardwarePortId; -+ msg.msgId = FM_PCD_CLEAR_PORT_PROFILES; -+ memcpy(msg.msgBody, &ipcAllocParams, sizeof(t_FmIpcResourceAllocParams)); -+ err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(t_FmIpcResourceAllocParams), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ return E_OK; -+ } -+ else if (!p_Regs) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("Either IPC or 'baseAddress' is required!")); -+ -+ ASSERT_COND(IN_RANGE(1, hardwarePortId, 63)); -+ WRITE_UINT32(p_Regs->fmpl_pmr[hardwarePortId-1], 0); -+ -+ return E_OK; -+} -+ -+t_Error FmPcdPlcrAllocProfiles(t_Handle h_FmPcd, uint8_t hardwarePortId, uint16_t numOfProfiles) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_Error err = E_OK; -+ uint32_t profilesFound; -+ uint32_t intFlags; -+ uint16_t i, first, swPortIndex = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ -+ if (!numOfProfiles) -+ return E_OK; -+ -+ ASSERT_COND(hardwarePortId); -+ -+ if (numOfProfiles>FM_PCD_PLCR_NUM_ENTRIES) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, ("numProfiles is too big.")); -+ -+ if (!POWER_OF_2(numOfProfiles)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numProfiles must be a power of 2.")); -+ -+ first = 0; -+ profilesFound = 0; -+ intFlags = PlcrSwLock(p_FmPcd->p_FmPcdPlcr); -+ -+ for (i=0; ip_FmPcdPlcr->profiles[i].profilesMng.allocated) -+ { -+ profilesFound++; -+ i++; -+ if (profilesFound == numOfProfiles) -+ break; -+ } -+ else -+ { -+ profilesFound = 0; -+ /* advance i to the next aligned address */ -+ i = first = (uint16_t)(first + numOfProfiles); -+ } -+ } -+ -+ if (profilesFound == numOfProfiles) -+ { -+ for (i=first; ip_FmPcdPlcr->profiles[i].profilesMng.allocated = TRUE; -+ p_FmPcd->p_FmPcdPlcr->profiles[i].profilesMng.ownerId = hardwarePortId; -+ } -+ } -+ else -+ { -+ PlcrSwUnlock(p_FmPcd->p_FmPcdPlcr, intFlags); -+ RETURN_ERROR(MINOR, E_FULL, ("No profiles.")); -+ } -+ PlcrSwUnlock(p_FmPcd->p_FmPcdPlcr, intFlags); -+ -+ err = PlcrSetPortProfiles(p_FmPcd, hardwarePortId, numOfProfiles, first); -+ if (err) -+ { -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ HW_PORT_ID_TO_SW_PORT_INDX(swPortIndex, hardwarePortId); -+ -+ p_FmPcd->p_FmPcdPlcr->portsMapping[swPortIndex].numOfProfiles = numOfProfiles; -+ p_FmPcd->p_FmPcdPlcr->portsMapping[swPortIndex].profilesBase = first; -+ -+ return E_OK; -+} -+ -+t_Error FmPcdPlcrFreeProfiles(t_Handle h_FmPcd, uint8_t hardwarePortId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_Error err = E_OK; -+ uint32_t intFlags; -+ uint16_t i, swPortIndex = 0; -+ -+ ASSERT_COND(IN_RANGE(1, hardwarePortId, 63)); -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_HANDLE); -+ -+ HW_PORT_ID_TO_SW_PORT_INDX(swPortIndex, hardwarePortId); -+ -+ err = PlcrClearPortProfiles(p_FmPcd, hardwarePortId); -+ if (err) -+ RETURN_ERROR(MAJOR, err,NO_MSG); -+ -+ intFlags = PlcrSwLock(p_FmPcd->p_FmPcdPlcr); -+ for (i=p_FmPcd->p_FmPcdPlcr->portsMapping[swPortIndex].profilesBase; -+ i<(p_FmPcd->p_FmPcdPlcr->portsMapping[swPortIndex].profilesBase + -+ p_FmPcd->p_FmPcdPlcr->portsMapping[swPortIndex].numOfProfiles); -+ i++) -+ { -+ ASSERT_COND(p_FmPcd->p_FmPcdPlcr->profiles[i].profilesMng.ownerId == hardwarePortId); -+ ASSERT_COND(p_FmPcd->p_FmPcdPlcr->profiles[i].profilesMng.allocated); -+ -+ p_FmPcd->p_FmPcdPlcr->profiles[i].profilesMng.allocated = FALSE; -+ p_FmPcd->p_FmPcdPlcr->profiles[i].profilesMng.ownerId = p_FmPcd->guestId; -+ } -+ PlcrSwUnlock(p_FmPcd->p_FmPcdPlcr, intFlags); -+ -+ p_FmPcd->p_FmPcdPlcr->portsMapping[swPortIndex].numOfProfiles = 0; -+ p_FmPcd->p_FmPcdPlcr->portsMapping[swPortIndex].profilesBase = 0; -+ -+ return E_OK; -+} -+ -+t_Error FmPcdPlcrCcGetSetParams(t_Handle h_FmPcd, uint16_t profileIndx ,uint32_t requiredAction) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ t_FmPcdPlcr *p_FmPcdPlcr = p_FmPcd->p_FmPcdPlcr; -+ t_FmPcdPlcrRegs *p_FmPcdPlcrRegs = p_FmPcdPlcr->p_FmPcdPlcrRegs; -+ uint32_t tmpReg32, intFlags; -+ t_Error err; -+ -+ /* Calling function locked all PCD modules, so no need to lock here */ -+ -+ if (profileIndx >= FM_PCD_PLCR_NUM_ENTRIES) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE,("Policer profile out of range")); -+ -+ if (!FmPcdPlcrIsProfileValid(p_FmPcd, profileIndx)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE,("Policer profile is not valid")); -+ -+ /*intFlags = PlcrProfileLock(&p_FmPcd->p_FmPcdPlcr->profiles[profileIndx]);*/ -+ -+ if (p_FmPcd->h_Hc) -+ { -+ err = FmHcPcdPlcrCcGetSetParams(p_FmPcd->h_Hc, profileIndx, requiredAction); -+ -+ UpdateRequiredActionFlag(p_FmPcd, profileIndx, TRUE); -+ FmPcdPlcrUpdateRequiredAction(p_FmPcd, profileIndx, requiredAction); -+ -+ /*PlcrProfileUnlock(&p_FmPcd->p_FmPcdPlcr->profiles[profileIndx], intFlags);*/ -+ return err; -+ } -+ -+ /* lock the HW because once we read the registers we don't want them to be changed -+ * by another access. (We can copy to a tmp location and release the lock!) */ -+ -+ intFlags = PlcrHwLock(p_FmPcdPlcr); -+ WritePar(p_FmPcd, FmPcdPlcrBuildReadPlcrActionReg(profileIndx)); -+ -+ if (!p_FmPcd->p_FmPcdPlcr->profiles[profileIndx].requiredActionFlag || -+ !(p_FmPcd->p_FmPcdPlcr->profiles[profileIndx].requiredAction & requiredAction)) -+ { -+ if (requiredAction & UPDATE_NIA_ENQ_WITHOUT_DMA) -+ { -+ if ((p_FmPcd->p_FmPcdPlcr->profiles[profileIndx].nextEngineOnGreen!= e_FM_PCD_DONE) || -+ (p_FmPcd->p_FmPcdPlcr->profiles[profileIndx].nextEngineOnYellow!= e_FM_PCD_DONE) || -+ (p_FmPcd->p_FmPcdPlcr->profiles[profileIndx].nextEngineOnRed!= e_FM_PCD_DONE)) -+ { -+ PlcrHwUnlock(p_FmPcdPlcr, intFlags); -+ /*PlcrProfileUnlock(&p_FmPcd->p_FmPcdPlcr->profiles[profileIndx], intFlags);*/ -+ RETURN_ERROR (MAJOR, E_OK, ("In this case the next engine can be e_FM_PCD_DONE")); -+ } -+ -+ if (p_FmPcd->p_FmPcdPlcr->profiles[profileIndx].paramsOnGreen.action == e_FM_PCD_ENQ_FRAME) -+ { -+ tmpReg32 = GET_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pegnia); -+ if (!(tmpReg32 & (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME))) -+ { -+ PlcrHwUnlock(p_FmPcdPlcr, intFlags); -+ /*PlcrProfileUnlock(&p_FmPcd->p_FmPcdPlcr->profiles[profileIndx], intFlags);*/ -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Next engine of this policer profile has to be assigned to FM_PCD_DONE")); -+ } -+ tmpReg32 |= NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA; -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pegnia, tmpReg32); -+ tmpReg32 = FmPcdPlcrBuildWritePlcrActionReg(profileIndx); -+ tmpReg32 |= FM_PCD_PLCR_PAR_PWSEL_PEGNIA; -+ WritePar(p_FmPcd, tmpReg32); -+ } -+ -+ if (p_FmPcd->p_FmPcdPlcr->profiles[profileIndx].paramsOnYellow.action == e_FM_PCD_ENQ_FRAME) -+ { -+ tmpReg32 = GET_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_peynia); -+ if (!(tmpReg32 & (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME))) -+ { -+ PlcrHwUnlock(p_FmPcdPlcr, intFlags); -+ /*PlcrProfileUnlock(&p_FmPcd->p_FmPcdPlcr->profiles[profileIndx], intFlags);*/ -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Next engine of this policer profile has to be assigned to FM_PCD_DONE")); -+ } -+ tmpReg32 |= NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA; -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_peynia, tmpReg32); -+ tmpReg32 = FmPcdPlcrBuildWritePlcrActionReg(profileIndx); -+ tmpReg32 |= FM_PCD_PLCR_PAR_PWSEL_PEYNIA; -+ WritePar(p_FmPcd, tmpReg32); -+ PlcrHwUnlock(p_FmPcdPlcr, intFlags); -+ } -+ -+ if (p_FmPcd->p_FmPcdPlcr->profiles[profileIndx].paramsOnRed.action == e_FM_PCD_ENQ_FRAME) -+ { -+ tmpReg32 = GET_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pernia); -+ if (!(tmpReg32 & (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME))) -+ { -+ PlcrHwUnlock(p_FmPcdPlcr, intFlags); -+ /*PlcrProfileUnlock(&p_FmPcd->p_FmPcdPlcr->profiles[profileIndx], intFlags);*/ -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Next engine of this policer profile has to be assigned to FM_PCD_DONE")); -+ } -+ tmpReg32 |= NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA; -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pernia, tmpReg32); -+ tmpReg32 = FmPcdPlcrBuildWritePlcrActionReg(profileIndx); -+ tmpReg32 |= FM_PCD_PLCR_PAR_PWSEL_PERNIA; -+ WritePar(p_FmPcd, tmpReg32); -+ -+ } -+ } -+ } -+ PlcrHwUnlock(p_FmPcdPlcr, intFlags); -+ -+ UpdateRequiredActionFlag(p_FmPcd, profileIndx, TRUE); -+ FmPcdPlcrUpdateRequiredAction(p_FmPcd, profileIndx, requiredAction); -+ -+ /*PlcrProfileUnlock(&p_FmPcd->p_FmPcdPlcr->profiles[profileIndx], intFlags);*/ -+ -+ return E_OK; -+} -+ -+uint32_t FmPcdPlcrGetRequiredActionFlag(t_Handle h_FmPcd, uint16_t absoluteProfileId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ ASSERT_COND(p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].valid); -+ -+ return p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].requiredActionFlag; -+} -+ -+uint32_t FmPcdPlcrGetRequiredAction(t_Handle h_FmPcd, uint16_t absoluteProfileId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ ASSERT_COND(p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].valid); -+ -+ return p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].requiredAction; -+} -+ -+bool FmPcdPlcrIsProfileValid(t_Handle h_FmPcd, uint16_t absoluteProfileId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_FmPcdPlcr *p_FmPcdPlcr = p_FmPcd->p_FmPcdPlcr; -+ -+ ASSERT_COND(absoluteProfileId < FM_PCD_PLCR_NUM_ENTRIES); -+ -+ return p_FmPcdPlcr->profiles[absoluteProfileId].valid; -+} -+ -+void FmPcdPlcrValidateProfileSw(t_Handle h_FmPcd, uint16_t absoluteProfileId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint32_t intFlags; -+ -+ ASSERT_COND(!p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].valid); -+ -+ intFlags = PlcrProfileLock(&p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId]); -+ p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].valid = TRUE; -+ PlcrProfileUnlock(&p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId], intFlags); -+} -+ -+void FmPcdPlcrInvalidateProfileSw(t_Handle h_FmPcd, uint16_t absoluteProfileId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint32_t intFlags; -+ -+ ASSERT_COND(p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].valid); -+ -+ intFlags = PlcrProfileLock(&p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId]); -+ p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].valid = FALSE; -+ PlcrProfileUnlock(&p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId], intFlags); -+} -+ -+uint16_t FmPcdPlcrProfileGetAbsoluteId(t_Handle h_Profile) -+{ -+ return ((t_FmPcdPlcrProfile*)h_Profile)->absoluteProfileId; -+} -+ -+t_Error FmPcdPlcrGetAbsoluteIdByProfileParams(t_Handle h_FmPcd, -+ e_FmPcdProfileTypeSelection profileType, -+ t_Handle h_FmPort, -+ uint16_t relativeProfile, -+ uint16_t *p_AbsoluteId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ t_FmPcdPlcr *p_FmPcdPlcr = p_FmPcd->p_FmPcdPlcr; -+ uint8_t i; -+ -+ switch (profileType) -+ { -+ case e_FM_PCD_PLCR_PORT_PRIVATE: -+ /* get port PCD id from port handle */ -+ for (i=0;ip_FmPcdPlcr->portsMapping[i].h_FmPort == h_FmPort) -+ break; -+ if (i == FM_MAX_NUM_OF_PORTS) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE , ("Invalid port handle.")); -+ -+ if (!p_FmPcd->p_FmPcdPlcr->portsMapping[i].numOfProfiles) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION , ("Port has no allocated profiles")); -+ if (relativeProfile >= p_FmPcd->p_FmPcdPlcr->portsMapping[i].numOfProfiles) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION , ("Profile id is out of range")); -+ *p_AbsoluteId = (uint16_t)(p_FmPcd->p_FmPcdPlcr->portsMapping[i].profilesBase + relativeProfile); -+ break; -+ case e_FM_PCD_PLCR_SHARED: -+ if (relativeProfile >= p_FmPcdPlcr->numOfSharedProfiles) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION , ("Profile id is out of range")); -+ *p_AbsoluteId = (uint16_t)(p_FmPcdPlcr->sharedProfilesIds[relativeProfile]); -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Invalid policer profile type")); -+ } -+ -+ return E_OK; -+} -+ -+uint16_t FmPcdPlcrGetPortProfilesBase(t_Handle h_FmPcd, uint8_t hardwarePortId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ uint16_t swPortIndex = 0; -+ -+ HW_PORT_ID_TO_SW_PORT_INDX(swPortIndex, hardwarePortId); -+ -+ return p_FmPcd->p_FmPcdPlcr->portsMapping[swPortIndex].profilesBase; -+} -+ -+uint16_t FmPcdPlcrGetPortNumOfProfiles(t_Handle h_FmPcd, uint8_t hardwarePortId) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ uint16_t swPortIndex = 0; -+ -+ HW_PORT_ID_TO_SW_PORT_INDX(swPortIndex, hardwarePortId); -+ -+ return p_FmPcd->p_FmPcdPlcr->portsMapping[swPortIndex].numOfProfiles; -+ -+} -+uint32_t FmPcdPlcrBuildWritePlcrActionReg(uint16_t absoluteProfileId) -+{ -+ return (uint32_t)(FM_PCD_PLCR_PAR_GO | -+ ((uint32_t)absoluteProfileId << FM_PCD_PLCR_PAR_PNUM_SHIFT)); -+} -+ -+uint32_t FmPcdPlcrBuildWritePlcrActionRegs(uint16_t absoluteProfileId) -+{ -+ return (uint32_t)(FM_PCD_PLCR_PAR_GO | -+ ((uint32_t)absoluteProfileId << FM_PCD_PLCR_PAR_PNUM_SHIFT) | -+ FM_PCD_PLCR_PAR_PWSEL_MASK); -+} -+ -+bool FmPcdPlcrHwProfileIsValid(uint32_t profileModeReg) -+{ -+ -+ if (profileModeReg & FM_PCD_PLCR_PEMODE_PI) -+ return TRUE; -+ else -+ return FALSE; -+} -+ -+uint32_t FmPcdPlcrBuildReadPlcrActionReg(uint16_t absoluteProfileId) -+{ -+ return (uint32_t)(FM_PCD_PLCR_PAR_GO | -+ FM_PCD_PLCR_PAR_R | -+ ((uint32_t)absoluteProfileId << FM_PCD_PLCR_PAR_PNUM_SHIFT) | -+ FM_PCD_PLCR_PAR_PWSEL_MASK); -+} -+ -+uint32_t FmPcdPlcrBuildCounterProfileReg(e_FmPcdPlcrProfileCounters counter) -+{ -+ switch (counter) -+ { -+ case (e_FM_PCD_PLCR_PROFILE_GREEN_PACKET_TOTAL_COUNTER): -+ return FM_PCD_PLCR_PAR_PWSEL_PEGPC; -+ case (e_FM_PCD_PLCR_PROFILE_YELLOW_PACKET_TOTAL_COUNTER): -+ return FM_PCD_PLCR_PAR_PWSEL_PEYPC; -+ case (e_FM_PCD_PLCR_PROFILE_RED_PACKET_TOTAL_COUNTER) : -+ return FM_PCD_PLCR_PAR_PWSEL_PERPC; -+ case (e_FM_PCD_PLCR_PROFILE_RECOLOURED_YELLOW_PACKET_TOTAL_COUNTER) : -+ return FM_PCD_PLCR_PAR_PWSEL_PERYPC; -+ case (e_FM_PCD_PLCR_PROFILE_RECOLOURED_RED_PACKET_TOTAL_COUNTER) : -+ return FM_PCD_PLCR_PAR_PWSEL_PERRPC; -+ default: -+ REPORT_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ return 0; -+ } -+} -+ -+uint32_t FmPcdPlcrBuildNiaProfileReg(bool green, bool yellow, bool red) -+{ -+ -+ uint32_t tmpReg32 = 0; -+ -+ if (green) -+ tmpReg32 |= FM_PCD_PLCR_PAR_PWSEL_PEGNIA; -+ if (yellow) -+ tmpReg32 |= FM_PCD_PLCR_PAR_PWSEL_PEYNIA; -+ if (red) -+ tmpReg32 |= FM_PCD_PLCR_PAR_PWSEL_PERNIA; -+ -+ return tmpReg32; -+} -+ -+void FmPcdPlcrUpdateRequiredAction(t_Handle h_FmPcd, uint16_t absoluteProfileId, uint32_t requiredAction) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ /* this routine is protected by calling routine */ -+ -+ ASSERT_COND(p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].valid); -+ -+ p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId].requiredAction |= requiredAction; -+} -+ -+/*********************** End of inter-module routines ************************/ -+ -+ -+/**************************************************/ -+/*............Policer API.........................*/ -+/**************************************************/ -+ -+t_Error FM_PCD_ConfigPlcrAutoRefreshMode(t_Handle h_FmPcd, bool enable) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPlcr, E_INVALID_HANDLE); -+ -+ if (!FmIsMaster(p_FmPcd->h_Fm)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_ConfigPlcrAutoRefreshMode - guest mode!")); -+ -+ p_FmPcd->p_FmPcdDriverParam->plcrAutoRefresh = enable; -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_ConfigPlcrNumOfSharedProfiles(t_Handle h_FmPcd, uint16_t numOfSharedPlcrProfiles) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPlcr, E_INVALID_HANDLE); -+ -+ p_FmPcd->p_FmPcdPlcr->numOfSharedProfiles = numOfSharedPlcrProfiles; -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_SetPlcrStatistics(t_Handle h_FmPcd, bool enable) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint32_t tmpReg32; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPlcr, E_INVALID_HANDLE); -+ -+ if (!FmIsMaster(p_FmPcd->h_Fm)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_SetPlcrStatistics - guest mode!")); -+ -+ tmpReg32 = GET_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_gcr); -+ if (enable) -+ tmpReg32 |= FM_PCD_PLCR_GCR_STEN; -+ else -+ tmpReg32 &= ~FM_PCD_PLCR_GCR_STEN; -+ -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_gcr, tmpReg32); -+ return E_OK; -+} -+ -+t_Handle FM_PCD_PlcrProfileSet(t_Handle h_FmPcd, -+ t_FmPcdPlcrProfileParams *p_ProfileParams) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdPlcrRegs *p_FmPcdPlcrRegs; -+ t_FmPcdPlcrProfileRegs plcrProfileReg; -+ uint32_t intFlags; -+ uint16_t absoluteProfileId; -+ t_Error err = E_OK; -+ uint32_t tmpReg32; -+ t_FmPcdPlcrProfile *p_Profile; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_HANDLE, NULL); -+ -+ if (p_ProfileParams->modify) -+ { -+ p_Profile = (t_FmPcdPlcrProfile *)p_ProfileParams->id.h_Profile; -+ p_FmPcd = p_Profile->h_FmPcd; -+ absoluteProfileId = p_Profile->absoluteProfileId; -+ if (absoluteProfileId >= FM_PCD_PLCR_NUM_ENTRIES) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("profileId too Big ")); -+ return NULL; -+ } -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPcd->p_FmPcdPlcr, E_INVALID_HANDLE, NULL); -+ -+ /* Try lock profile using flag */ -+ if (!PlcrProfileFlagTryLock(p_Profile)) -+ { -+ DBG(TRACE, ("Profile Try Lock - BUSY")); -+ /* Signal to caller BUSY condition */ -+ p_ProfileParams->id.h_Profile = NULL; -+ return NULL; -+ } -+ } -+ else -+ { -+ p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPcd->p_FmPcdPlcr, E_INVALID_HANDLE, NULL); -+ -+ /* SMP: needs to be protected only if another core now changes the windows */ -+ err = FmPcdPlcrGetAbsoluteIdByProfileParams(h_FmPcd, -+ p_ProfileParams->id.newParams.profileType, -+ p_ProfileParams->id.newParams.h_FmPort, -+ p_ProfileParams->id.newParams.relativeProfileId, -+ &absoluteProfileId); -+ if (err) -+ { -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ return NULL; -+ } -+ -+ if (absoluteProfileId >= FM_PCD_PLCR_NUM_ENTRIES) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("profileId too Big ")); -+ return NULL; -+ } -+ -+ if (FmPcdPlcrIsProfileValid(p_FmPcd, absoluteProfileId)) -+ { -+ REPORT_ERROR(MAJOR, E_ALREADY_EXISTS, ("Policer Profile is already used")); -+ return NULL; -+ } -+ -+ /* initialize profile struct */ -+ p_Profile = &p_FmPcd->p_FmPcdPlcr->profiles[absoluteProfileId]; -+ -+ p_Profile->h_FmPcd = p_FmPcd; -+ p_Profile->absoluteProfileId = absoluteProfileId; -+ -+ p_Profile->p_Lock = FmPcdAcquireLock(p_FmPcd); -+ if (!p_Profile->p_Lock) -+ REPORT_ERROR(MAJOR, E_NOT_AVAILABLE, ("FM Policer Profile lock obj!")); -+ } -+ -+ SANITY_CHECK_RETURN_VALUE(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE, NULL); -+ -+ p_Profile->nextEngineOnGreen = p_ProfileParams->nextEngineOnGreen; -+ memcpy(&p_Profile->paramsOnGreen, &(p_ProfileParams->paramsOnGreen), sizeof(u_FmPcdPlcrNextEngineParams)); -+ -+ p_Profile->nextEngineOnYellow = p_ProfileParams->nextEngineOnYellow; -+ memcpy(&p_Profile->paramsOnYellow, &(p_ProfileParams->paramsOnYellow), sizeof(u_FmPcdPlcrNextEngineParams)); -+ -+ p_Profile->nextEngineOnRed = p_ProfileParams->nextEngineOnRed; -+ memcpy(&p_Profile->paramsOnRed, &(p_ProfileParams->paramsOnRed), sizeof(u_FmPcdPlcrNextEngineParams)); -+ -+ memset(&plcrProfileReg, 0, sizeof(t_FmPcdPlcrProfileRegs)); -+ -+ /* build the policer profile registers */ -+ err = BuildProfileRegs(h_FmPcd, p_ProfileParams, &plcrProfileReg); -+ if (err) -+ { -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ if (p_ProfileParams->modify) -+ /* unlock */ -+ PlcrProfileFlagUnlock(p_Profile); -+ if (!p_ProfileParams->modify && -+ p_Profile->p_Lock) -+ /* release allocated Profile lock */ -+ FmPcdReleaseLock(p_FmPcd, p_Profile->p_Lock); -+ return NULL; -+ } -+ -+ if (p_FmPcd->h_Hc) -+ { -+ err = FmHcPcdPlcrSetProfile(p_FmPcd->h_Hc, (t_Handle)p_Profile, &plcrProfileReg); -+ if (p_ProfileParams->modify) -+ PlcrProfileFlagUnlock(p_Profile); -+ if (err) -+ { -+ /* release the allocated scheme lock */ -+ if (!p_ProfileParams->modify && -+ p_Profile->p_Lock) -+ FmPcdReleaseLock(p_FmPcd, p_Profile->p_Lock); -+ -+ return NULL; -+ } -+ if (!p_ProfileParams->modify) -+ FmPcdPlcrValidateProfileSw(p_FmPcd,absoluteProfileId); -+ return (t_Handle)p_Profile; -+ } -+ -+ p_FmPcdPlcrRegs = p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs; -+ SANITY_CHECK_RETURN_VALUE(p_FmPcdPlcrRegs, E_INVALID_HANDLE, NULL); -+ -+ intFlags = PlcrHwLock(p_FmPcd->p_FmPcdPlcr); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pemode , plcrProfileReg.fmpl_pemode); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pegnia , plcrProfileReg.fmpl_pegnia); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_peynia , plcrProfileReg.fmpl_peynia); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pernia , plcrProfileReg.fmpl_pernia); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pecir , plcrProfileReg.fmpl_pecir); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pecbs , plcrProfileReg.fmpl_pecbs); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pepepir_eir,plcrProfileReg.fmpl_pepepir_eir); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pepbs_ebs,plcrProfileReg.fmpl_pepbs_ebs); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pelts , plcrProfileReg.fmpl_pelts); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pects , plcrProfileReg.fmpl_pects); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pepts_ets,plcrProfileReg.fmpl_pepts_ets); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pegpc , plcrProfileReg.fmpl_pegpc); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_peypc , plcrProfileReg.fmpl_peypc); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_perpc , plcrProfileReg.fmpl_perpc); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_perypc , plcrProfileReg.fmpl_perypc); -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_perrpc , plcrProfileReg.fmpl_perrpc); -+ -+ tmpReg32 = FmPcdPlcrBuildWritePlcrActionRegs(absoluteProfileId); -+ WritePar(p_FmPcd, tmpReg32); -+ -+ PlcrHwUnlock(p_FmPcd->p_FmPcdPlcr, intFlags); -+ -+ if (!p_ProfileParams->modify) -+ FmPcdPlcrValidateProfileSw(p_FmPcd,absoluteProfileId); -+ else -+ PlcrProfileFlagUnlock(p_Profile); -+ -+ return (t_Handle)p_Profile; -+} -+ -+t_Error FM_PCD_PlcrProfileDelete(t_Handle h_Profile) -+{ -+ t_FmPcdPlcrProfile *p_Profile = (t_FmPcdPlcrProfile*)h_Profile; -+ t_FmPcd *p_FmPcd; -+ uint16_t profileIndx; -+ uint32_t tmpReg32, intFlags; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Profile, E_INVALID_HANDLE); -+ p_FmPcd = p_Profile->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ -+ profileIndx = p_Profile->absoluteProfileId; -+ -+ UpdateRequiredActionFlag(p_FmPcd, profileIndx, FALSE); -+ -+ FmPcdPlcrInvalidateProfileSw(p_FmPcd,profileIndx); -+ -+ if (p_FmPcd->h_Hc) -+ { -+ err = FmHcPcdPlcrDeleteProfile(p_FmPcd->h_Hc, h_Profile); -+ if (p_Profile->p_Lock) -+ /* release allocated Profile lock */ -+ FmPcdReleaseLock(p_FmPcd, p_Profile->p_Lock); -+ -+ return err; -+ } -+ -+ intFlags = PlcrHwLock(p_FmPcd->p_FmPcdPlcr); -+ WRITE_UINT32(p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->profileRegs.fmpl_pemode, ~FM_PCD_PLCR_PEMODE_PI); -+ -+ tmpReg32 = FmPcdPlcrBuildWritePlcrActionRegs(profileIndx); -+ WritePar(p_FmPcd, tmpReg32); -+ PlcrHwUnlock(p_FmPcd->p_FmPcdPlcr, intFlags); -+ -+ -+ if (p_Profile->p_Lock) -+ /* release allocated Profile lock */ -+ FmPcdReleaseLock(p_FmPcd, p_Profile->p_Lock); -+ -+ /* we do not memset profile as all its fields are being re-initialized at "set", -+ * plus its allocation information is still valid. */ -+ return E_OK; -+} -+ -+/***************************************************/ -+/*............Policer Profile Counter..............*/ -+/***************************************************/ -+uint32_t FM_PCD_PlcrProfileGetCounter(t_Handle h_Profile, e_FmPcdPlcrProfileCounters counter) -+{ -+ t_FmPcdPlcrProfile *p_Profile = (t_FmPcdPlcrProfile*)h_Profile; -+ t_FmPcd *p_FmPcd; -+ uint16_t profileIndx; -+ uint32_t intFlags, counterVal = 0; -+ t_FmPcdPlcrRegs *p_FmPcdPlcrRegs; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Profile, E_INVALID_HANDLE); -+ p_FmPcd = p_Profile->h_FmPcd; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ -+ if (p_FmPcd->h_Hc) -+ return FmHcPcdPlcrGetProfileCounter(p_FmPcd->h_Hc, h_Profile, counter); -+ -+ p_FmPcdPlcrRegs = p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs; -+ SANITY_CHECK_RETURN_VALUE(p_FmPcdPlcrRegs, E_INVALID_HANDLE, 0); -+ -+ profileIndx = p_Profile->absoluteProfileId; -+ -+ if (profileIndx >= FM_PCD_PLCR_NUM_ENTRIES) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("profileId too Big ")); -+ return 0; -+ } -+ intFlags = PlcrHwLock(p_FmPcd->p_FmPcdPlcr); -+ WritePar(p_FmPcd, FmPcdPlcrBuildReadPlcrActionReg(profileIndx)); -+ -+ switch (counter) -+ { -+ case e_FM_PCD_PLCR_PROFILE_GREEN_PACKET_TOTAL_COUNTER: -+ counterVal = (GET_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pegpc)); -+ break; -+ case e_FM_PCD_PLCR_PROFILE_YELLOW_PACKET_TOTAL_COUNTER: -+ counterVal = GET_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_peypc); -+ break; -+ case e_FM_PCD_PLCR_PROFILE_RED_PACKET_TOTAL_COUNTER: -+ counterVal = GET_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_perpc); -+ break; -+ case e_FM_PCD_PLCR_PROFILE_RECOLOURED_YELLOW_PACKET_TOTAL_COUNTER: -+ counterVal = GET_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_perypc); -+ break; -+ case e_FM_PCD_PLCR_PROFILE_RECOLOURED_RED_PACKET_TOTAL_COUNTER: -+ counterVal = GET_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_perrpc); -+ break; -+ default: -+ REPORT_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ break; -+ } -+ PlcrHwUnlock(p_FmPcd->p_FmPcdPlcr, intFlags); -+ -+ return counterVal; -+} -+ -+t_Error FM_PCD_PlcrProfileSetCounter(t_Handle h_Profile, e_FmPcdPlcrProfileCounters counter, uint32_t value) -+{ -+ t_FmPcdPlcrProfile *p_Profile = (t_FmPcdPlcrProfile*)h_Profile; -+ t_FmPcd *p_FmPcd; -+ uint16_t profileIndx; -+ uint32_t tmpReg32, intFlags; -+ t_FmPcdPlcrRegs *p_FmPcdPlcrRegs; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Profile, E_INVALID_HANDLE); -+ -+ p_FmPcd = p_Profile->h_FmPcd; -+ profileIndx = p_Profile->absoluteProfileId; -+ -+ if (p_FmPcd->h_Hc) -+ return FmHcPcdPlcrSetProfileCounter(p_FmPcd->h_Hc, h_Profile, counter, value); -+ -+ p_FmPcdPlcrRegs = p_FmPcd->p_FmPcdPlcr->p_FmPcdPlcrRegs; -+ SANITY_CHECK_RETURN_ERROR(p_FmPcdPlcrRegs, E_INVALID_HANDLE); -+ -+ intFlags = PlcrHwLock(p_FmPcd->p_FmPcdPlcr); -+ switch (counter) -+ { -+ case e_FM_PCD_PLCR_PROFILE_GREEN_PACKET_TOTAL_COUNTER: -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_pegpc, value); -+ break; -+ case e_FM_PCD_PLCR_PROFILE_YELLOW_PACKET_TOTAL_COUNTER: -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_peypc, value); -+ break; -+ case e_FM_PCD_PLCR_PROFILE_RED_PACKET_TOTAL_COUNTER: -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_perpc, value); -+ break; -+ case e_FM_PCD_PLCR_PROFILE_RECOLOURED_YELLOW_PACKET_TOTAL_COUNTER: -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_perypc ,value); -+ break; -+ case e_FM_PCD_PLCR_PROFILE_RECOLOURED_RED_PACKET_TOTAL_COUNTER: -+ WRITE_UINT32(p_FmPcdPlcrRegs->profileRegs.fmpl_perrpc ,value); -+ break; -+ default: -+ PlcrHwUnlock(p_FmPcd->p_FmPcdPlcr, intFlags); -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ -+ /* Activate the atomic write action by writing FMPL_PAR with: GO=1, RW=1, PSI=0, PNUM = -+ * Profile Number, PWSEL=0xFFFF (select all words). -+ */ -+ tmpReg32 = FmPcdPlcrBuildWritePlcrActionReg(profileIndx); -+ tmpReg32 |= FmPcdPlcrBuildCounterProfileReg(counter); -+ WritePar(p_FmPcd, tmpReg32); -+ PlcrHwUnlock(p_FmPcd->p_FmPcdPlcr, intFlags); -+ -+ return E_OK; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_plcr.h -@@ -0,0 +1,165 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_plcr.h -+ -+ @Description FM Policer private header -+*//***************************************************************************/ -+#ifndef __FM_PLCR_H -+#define __FM_PLCR_H -+ -+#include "std_ext.h" -+ -+ -+/***********************************************************************/ -+/* Policer defines */ -+/***********************************************************************/ -+ -+#define FM_PCD_PLCR_PAR_GO 0x80000000 -+#define FM_PCD_PLCR_PAR_PWSEL_MASK 0x0000FFFF -+#define FM_PCD_PLCR_PAR_R 0x40000000 -+ -+/* shifts */ -+#define FM_PCD_PLCR_PAR_PNUM_SHIFT 16 -+ -+/* masks */ -+#define FM_PCD_PLCR_PEMODE_PI 0x80000000 -+#define FM_PCD_PLCR_PEMODE_CBLND 0x40000000 -+#define FM_PCD_PLCR_PEMODE_ALG_MASK 0x30000000 -+#define FM_PCD_PLCR_PEMODE_ALG_RFC2698 0x10000000 -+#define FM_PCD_PLCR_PEMODE_ALG_RFC4115 0x20000000 -+#define FM_PCD_PLCR_PEMODE_DEFC_MASK 0x0C000000 -+#define FM_PCD_PLCR_PEMODE_DEFC_Y 0x04000000 -+#define FM_PCD_PLCR_PEMODE_DEFC_R 0x08000000 -+#define FM_PCD_PLCR_PEMODE_DEFC_OVERRIDE 0x0C000000 -+#define FM_PCD_PLCR_PEMODE_OVCLR_MASK 0x03000000 -+#define FM_PCD_PLCR_PEMODE_OVCLR_Y 0x01000000 -+#define FM_PCD_PLCR_PEMODE_OVCLR_R 0x02000000 -+#define FM_PCD_PLCR_PEMODE_OVCLR_G_NC 0x03000000 -+#define FM_PCD_PLCR_PEMODE_PKT 0x00800000 -+#define FM_PCD_PLCR_PEMODE_FPP_MASK 0x001F0000 -+#define FM_PCD_PLCR_PEMODE_FPP_SHIFT 16 -+#define FM_PCD_PLCR_PEMODE_FLS_MASK 0x0000F000 -+#define FM_PCD_PLCR_PEMODE_FLS_L2 0x00003000 -+#define FM_PCD_PLCR_PEMODE_FLS_L3 0x0000B000 -+#define FM_PCD_PLCR_PEMODE_FLS_L4 0x0000E000 -+#define FM_PCD_PLCR_PEMODE_FLS_FULL 0x0000F000 -+#define FM_PCD_PLCR_PEMODE_RBFLS 0x00000800 -+#define FM_PCD_PLCR_PEMODE_TRA 0x00000004 -+#define FM_PCD_PLCR_PEMODE_TRB 0x00000002 -+#define FM_PCD_PLCR_PEMODE_TRC 0x00000001 -+#define FM_PCD_PLCR_DOUBLE_ECC 0x80000000 -+#define FM_PCD_PLCR_INIT_ENTRY_ERROR 0x40000000 -+#define FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE 0x80000000 -+#define FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE 0x40000000 -+ -+#define FM_PCD_PLCR_NIA_VALID 0x80000000 -+ -+#define FM_PCD_PLCR_GCR_EN 0x80000000 -+#define FM_PCD_PLCR_GCR_STEN 0x40000000 -+#define FM_PCD_PLCR_GCR_DAR 0x20000000 -+#define FM_PCD_PLCR_GCR_DEFNIA 0x00FFFFFF -+#define FM_PCD_PLCR_NIA_ABS 0x00000100 -+ -+#define FM_PCD_PLCR_GSR_BSY 0x80000000 -+#define FM_PCD_PLCR_GSR_DQS 0x60000000 -+#define FM_PCD_PLCR_GSR_RPB 0x20000000 -+#define FM_PCD_PLCR_GSR_FQS 0x0C000000 -+#define FM_PCD_PLCR_GSR_LPALG 0x0000C000 -+#define FM_PCD_PLCR_GSR_LPCA 0x00003000 -+#define FM_PCD_PLCR_GSR_LPNUM 0x000000FF -+ -+#define FM_PCD_PLCR_EVR_PSIC 0x80000000 -+#define FM_PCD_PLCR_EVR_AAC 0x40000000 -+ -+#define FM_PCD_PLCR_PAR_PSI 0x20000000 -+#define FM_PCD_PLCR_PAR_PNUM 0x00FF0000 -+/* PWSEL Selctive select options */ -+#define FM_PCD_PLCR_PAR_PWSEL_PEMODE 0x00008000 /* 0 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PEGNIA 0x00004000 /* 1 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PEYNIA 0x00002000 /* 2 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PERNIA 0x00001000 /* 3 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PECIR 0x00000800 /* 4 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PECBS 0x00000400 /* 5 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PEPIR_EIR 0x00000200 /* 6 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PEPBS_EBS 0x00000100 /* 7 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PELTS 0x00000080 /* 8 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PECTS 0x00000040 /* 9 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PEPTS_ETS 0x00000020 /* 10 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PEGPC 0x00000010 /* 11 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PEYPC 0x00000008 /* 12 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PERPC 0x00000004 /* 13 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PERYPC 0x00000002 /* 14 */ -+#define FM_PCD_PLCR_PAR_PWSEL_PERRPC 0x00000001 /* 15 */ -+ -+#define FM_PCD_PLCR_PAR_PMR_BRN_1TO1 0x0000 /* - Full bit replacement. {PBNUM[0:N-1] -+ 1-> 2^N specific locations. */ -+#define FM_PCD_PLCR_PAR_PMR_BRN_2TO2 0x1 /* - {PBNUM[0:N-2],PNUM[N-1]}. -+ 2-> 2^(N-1) base locations. */ -+#define FM_PCD_PLCR_PAR_PMR_BRN_4TO4 0x2 /* - {PBNUM[0:N-3],PNUM[N-2:N-1]}. -+ 4-> 2^(N-2) base locations. */ -+#define FM_PCD_PLCR_PAR_PMR_BRN_8TO8 0x3 /* - {PBNUM[0:N-4],PNUM[N-3:N-1]}. -+ 8->2^(N-3) base locations. */ -+#define FM_PCD_PLCR_PAR_PMR_BRN_16TO16 0x4 /* - {PBNUM[0:N-5],PNUM[N-4:N-1]}. -+ 16-> 2^(N-4) base locations. */ -+#define FM_PCD_PLCR_PAR_PMR_BRN_32TO32 0x5 /* {PBNUM[0:N-6],PNUM[N-5:N-1]}. -+ 32-> 2^(N-5) base locations. */ -+#define FM_PCD_PLCR_PAR_PMR_BRN_64TO64 0x6 /* {PBNUM[0:N-7],PNUM[N-6:N-1]}. -+ 64-> 2^(N-6) base locations. */ -+#define FM_PCD_PLCR_PAR_PMR_BRN_128TO128 0x7 /* {PBNUM[0:N-8],PNUM[N-7:N-1]}. -+ 128-> 2^(N-7) base locations. */ -+#define FM_PCD_PLCR_PAR_PMR_BRN_256TO256 0x8 /* - No bit replacement for N=8. {PNUM[N-8:N-1]}. -+ When N=8 this option maps all 256 profiles by the DISPATCH bus into one group. */ -+ -+#define FM_PCD_PLCR_PMR_V 0x80000000 -+#define PLCR_ERR_ECC_CAP 0x80000000 -+#define PLCR_ERR_ECC_TYPE_DOUBLE 0x40000000 -+#define PLCR_ERR_ECC_PNUM_MASK 0x00000FF0 -+#define PLCR_ERR_ECC_OFFSET_MASK 0x0000000F -+ -+#define PLCR_ERR_UNINIT_CAP 0x80000000 -+#define PLCR_ERR_UNINIT_NUM_MASK 0x000000FF -+#define PLCR_ERR_UNINIT_PID_MASK 0x003f0000 -+#define PLCR_ERR_UNINIT_ABSOLUTE_MASK 0x00008000 -+ -+/* shifts */ -+#define PLCR_ERR_ECC_PNUM_SHIFT 4 -+#define PLCR_ERR_UNINIT_PID_SHIFT 16 -+ -+#define FM_PCD_PLCR_PMR_BRN_SHIFT 16 -+ -+#define PLCR_PORT_WINDOW_SIZE(hardwarePortId) -+ -+ -+#endif /* __FM_PLCR_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.c -@@ -0,0 +1,422 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_pcd.c -+ -+ @Description FM PCD ... -+*//***************************************************************************/ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "string_ext.h" -+#include "debug_ext.h" -+#include "net_ext.h" -+ -+#include "fm_common.h" -+#include "fm_pcd.h" -+#include "fm_pcd_ipc.h" -+#include "fm_prs.h" -+#include "fsl_fman_prs.h" -+ -+ -+static void PcdPrsErrorException(t_Handle h_FmPcd) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ uint32_t event, ev_mask; -+ struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs; -+ -+ ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID); -+ ev_mask = fman_prs_get_err_ev_mask(PrsRegs); -+ -+ event = fman_prs_get_err_event(PrsRegs, ev_mask); -+ -+ fman_prs_ack_err_event(PrsRegs, event); -+ -+ DBG(TRACE, ("parser error - 0x%08x\n",event)); -+ -+ if(event & FM_PCD_PRS_DOUBLE_ECC) -+ p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC); -+} -+ -+static void PcdPrsException(t_Handle h_FmPcd) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ uint32_t event, ev_mask; -+ struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs; -+ -+ ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID); -+ ev_mask = fman_prs_get_expt_ev_mask(PrsRegs); -+ event = fman_prs_get_expt_event(PrsRegs, ev_mask); -+ -+ ASSERT_COND(event & FM_PCD_PRS_SINGLE_ECC); -+ -+ DBG(TRACE, ("parser event - 0x%08x\n",event)); -+ -+ fman_prs_ack_expt_event(PrsRegs, event); -+ -+ p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC); -+} -+ -+t_Handle PrsConfig(t_FmPcd *p_FmPcd,t_FmPcdParams *p_FmPcdParams) -+{ -+ t_FmPcdPrs *p_FmPcdPrs; -+ uintptr_t baseAddr; -+ -+ UNUSED(p_FmPcd); -+ UNUSED(p_FmPcdParams); -+ -+ p_FmPcdPrs = (t_FmPcdPrs *) XX_Malloc(sizeof(t_FmPcdPrs)); -+ if (!p_FmPcdPrs) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM Parser structure allocation FAILED")); -+ return NULL; -+ } -+ memset(p_FmPcdPrs, 0, sizeof(t_FmPcdPrs)); -+ fman_prs_defconfig(&p_FmPcd->p_FmPcdDriverParam->dfltCfg); -+ -+ if (p_FmPcd->guestId == NCSW_MASTER_ID) -+ { -+ baseAddr = FmGetPcdPrsBaseAddr(p_FmPcdParams->h_Fm); -+ p_FmPcdPrs->p_SwPrsCode = (uint32_t *)UINT_TO_PTR(baseAddr); -+ p_FmPcdPrs->p_FmPcdPrsRegs = (struct fman_prs_regs *)UINT_TO_PTR(baseAddr + PRS_REGS_OFFSET); -+ } -+ -+ p_FmPcdPrs->fmPcdPrsPortIdStatistics = p_FmPcd->p_FmPcdDriverParam->dfltCfg.port_id_stat; -+ p_FmPcd->p_FmPcdDriverParam->prsMaxParseCycleLimit = p_FmPcd->p_FmPcdDriverParam->dfltCfg.max_prs_cyc_lim; -+ p_FmPcd->exceptions |= p_FmPcd->p_FmPcdDriverParam->dfltCfg.prs_exceptions; -+ -+ return p_FmPcdPrs; -+} -+ -+#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+ static uint8_t swPrsPatch[] = SW_PRS_UDP_LITE_PATCH; -+#else -+ static uint8_t swPrsPatch[] = SW_PRS_OFFLOAD_PATCH; -+#endif /* FM_CAPWAP_SUPPORT */ -+ -+t_Error PrsInit(t_FmPcd *p_FmPcd) -+{ -+ t_FmPcdDriverParam *p_Param = p_FmPcd->p_FmPcdDriverParam; -+ uint32_t *p_TmpCode; -+ uint32_t *p_LoadTarget = (uint32_t *)PTR_MOVE(p_FmPcd->p_FmPcdPrs->p_SwPrsCode, -+ FM_PCD_SW_PRS_SIZE-FM_PCD_PRS_SW_PATCHES_SIZE); -+ struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs; -+ uint32_t i; -+ -+ ASSERT_COND(sizeof(swPrsPatch) <= (FM_PCD_PRS_SW_PATCHES_SIZE-FM_PCD_PRS_SW_TAIL_SIZE)); -+ -+ /* nothing to do in guest-partition */ -+ if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ return E_OK; -+ -+ p_TmpCode = (uint32_t *)XX_MallocSmart(ROUND_UP(sizeof(swPrsPatch),4), 0, sizeof(uint32_t)); -+ if (!p_TmpCode) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Tmp Sw-Parser code allocation FAILED")); -+ memset((uint8_t *)p_TmpCode, 0, ROUND_UP(sizeof(swPrsPatch),4)); -+ memcpy((uint8_t *)p_TmpCode, (uint8_t *)swPrsPatch, sizeof(swPrsPatch)); -+ -+ fman_prs_init(PrsRegs, &p_Param->dfltCfg); -+ -+ /* register even if no interrupts enabled, to allow future enablement */ -+ FmRegisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_ERR, PcdPrsErrorException, p_FmPcd); -+ -+ /* register even if no interrupts enabled, to allow future enablement */ -+ FmRegisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_NORMAL, PcdPrsException, p_FmPcd); -+ -+ if(p_FmPcd->exceptions & FM_PCD_EX_PRS_SINGLE_ECC) -+ FmEnableRamsEcc(p_FmPcd->h_Fm); -+ -+ if(p_FmPcd->exceptions & FM_PCD_EX_PRS_DOUBLE_ECC) -+ FmEnableRamsEcc(p_FmPcd->h_Fm); -+ -+ /* load sw parser Ip-Frag patch */ -+ for (i=0; iguestId == NCSW_MASTER_ID); -+ FmUnregisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_ERR); -+ /* register even if no interrupts enabled, to allow future enablement */ -+ FmUnregisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_NORMAL); -+} -+ -+void PrsEnable(t_FmPcd *p_FmPcd) -+{ -+ struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs; -+ -+ ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID); -+ fman_prs_enable(PrsRegs); -+} -+ -+void PrsDisable(t_FmPcd *p_FmPcd) -+{ -+ struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs; -+ -+ ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID); -+ fman_prs_disable(PrsRegs); -+} -+ -+int PrsIsEnabled(t_FmPcd *p_FmPcd) -+{ -+ struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs; -+ -+ ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID); -+ return fman_prs_is_enabled(PrsRegs); -+} -+ -+t_Error PrsIncludePortInStatistics(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, bool include) -+{ -+ struct fman_prs_regs *PrsRegs; -+ uint32_t bitMask = 0; -+ uint8_t prsPortId; -+ -+ SANITY_CHECK_RETURN_ERROR((hardwarePortId >=1 && hardwarePortId <= 16), E_INVALID_VALUE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE); -+ -+ PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs; -+ -+ GET_FM_PCD_PRS_PORT_ID(prsPortId, hardwarePortId); -+ GET_FM_PCD_INDEX_FLAG(bitMask, prsPortId); -+ -+ if (include) -+ p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics |= bitMask; -+ else -+ p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics &= ~bitMask; -+ -+ fman_prs_set_stst_port_msk(PrsRegs, -+ p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics); -+ -+ return E_OK; -+} -+ -+t_Error FmPcdPrsIncludePortInStatistics(t_Handle h_FmPcd, uint8_t hardwarePortId, bool include) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR((hardwarePortId >=1 && hardwarePortId <= 16), E_INVALID_VALUE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE); -+ -+ if ((p_FmPcd->guestId != NCSW_MASTER_ID) && -+ p_FmPcd->h_IpcSession) -+ { -+ t_FmPcdIpcPrsIncludePort prsIncludePortParams; -+ t_FmPcdIpcMsg msg; -+ -+ prsIncludePortParams.hardwarePortId = hardwarePortId; -+ prsIncludePortParams.include = include; -+ memset(&msg, 0, sizeof(msg)); -+ msg.msgId = FM_PCD_PRS_INC_PORT_STATS; -+ memcpy(msg.msgBody, &prsIncludePortParams, sizeof(prsIncludePortParams)); -+ err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) +sizeof(prsIncludePortParams), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ return E_OK; -+ } -+ else if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without IPC!")); -+ -+ return PrsIncludePortInStatistics(p_FmPcd, hardwarePortId, include); -+} -+ -+uint32_t FmPcdGetSwPrsOffset(t_Handle h_FmPcd, e_NetHeaderType hdr, uint8_t indexPerHdr) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd; -+ t_FmPcdPrsLabelParams *p_Label; -+ int i; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPcd, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_VALUE(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_HANDLE, 0); -+ -+ if ((p_FmPcd->guestId != NCSW_MASTER_ID) && -+ p_FmPcd->h_IpcSession) -+ { -+ t_Error err = E_OK; -+ t_FmPcdIpcSwPrsLable labelParams; -+ t_FmPcdIpcMsg msg; -+ uint32_t prsOffset = 0; -+ t_FmPcdIpcReply reply; -+ uint32_t replyLength; -+ -+ memset(&reply, 0, sizeof(reply)); -+ memset(&msg, 0, sizeof(msg)); -+ labelParams.enumHdr = (uint32_t)hdr; -+ labelParams.indexPerHdr = indexPerHdr; -+ msg.msgId = FM_PCD_GET_SW_PRS_OFFSET; -+ memcpy(msg.msgBody, &labelParams, sizeof(labelParams)); -+ replyLength = sizeof(uint32_t) + sizeof(uint32_t); -+ err = XX_IpcSendMessage(p_FmPcd->h_IpcSession, -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) +sizeof(labelParams), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ if (replyLength != sizeof(uint32_t) + sizeof(uint32_t)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ -+ memcpy((uint8_t*)&prsOffset, reply.replyBody, sizeof(uint32_t)); -+ return prsOffset; -+ } -+ else if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without IPC!")); -+ -+ ASSERT_COND(p_FmPcd->p_FmPcdPrs->currLabel < FM_PCD_PRS_NUM_OF_LABELS); -+ -+ for (i=0; ip_FmPcdPrs->currLabel; i++) -+ { -+ p_Label = &p_FmPcd->p_FmPcdPrs->labelsTable[i]; -+ -+ if ((hdr == p_Label->hdr) && (indexPerHdr == p_Label->indexPerHdr)) -+ return p_Label->instructionOffset; -+ } -+ -+ REPORT_ERROR(MAJOR, E_NOT_FOUND, ("Sw Parser attachment Not found")); -+ return (uint32_t)ILLEGAL_BASE; -+} -+ -+void FM_PCD_SetPrsStatistics(t_Handle h_FmPcd, bool enable) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ struct fman_prs_regs *PrsRegs; -+ -+ SANITY_CHECK_RETURN(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE); -+ -+ PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs; -+ -+ -+ if(p_FmPcd->guestId != NCSW_MASTER_ID) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_SetPrsStatistics - guest mode!")); -+ return; -+ } -+ -+ fman_prs_set_stst(PrsRegs, enable); -+} -+ -+t_Error FM_PCD_PrsLoadSw(t_Handle h_FmPcd, t_FmPcdPrsSwParams *p_SwPrs) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ uint32_t *p_LoadTarget; -+ uint32_t *p_TmpCode; -+ int i; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_SwPrs, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPcd->enabled, E_INVALID_HANDLE); -+ -+ if (p_FmPcd->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM in guest-mode!")); -+ -+ if (!p_SwPrs->override) -+ { -+ if(p_FmPcd->p_FmPcdPrs->p_CurrSwPrs > p_FmPcd->p_FmPcdPrs->p_SwPrsCode + p_SwPrs->base*2/4) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("SW parser base must be larger than current loaded code")); -+ } -+ else -+ p_FmPcd->p_FmPcdPrs->currLabel = 0; -+ -+ if (p_SwPrs->size > FM_PCD_SW_PRS_SIZE - FM_PCD_PRS_SW_TAIL_SIZE - p_SwPrs->base*2) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("p_SwPrs->size may not be larger than MAX_SW_PRS_CODE_SIZE")); -+ -+ if (p_FmPcd->p_FmPcdPrs->currLabel + p_SwPrs->numOfLabels > FM_PCD_PRS_NUM_OF_LABELS) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceeded number of labels allowed ")); -+ -+ p_TmpCode = (uint32_t *)XX_MallocSmart(ROUND_UP(p_SwPrs->size,4), 0, sizeof(uint32_t)); -+ if (!p_TmpCode) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Tmp Sw-Parser code allocation FAILED")); -+ memset((uint8_t *)p_TmpCode, 0, ROUND_UP(p_SwPrs->size,4)); -+ memcpy((uint8_t *)p_TmpCode, p_SwPrs->p_Code, p_SwPrs->size); -+ -+ /* save sw parser labels */ -+ memcpy(&p_FmPcd->p_FmPcdPrs->labelsTable[p_FmPcd->p_FmPcdPrs->currLabel], -+ p_SwPrs->labelsTable, -+ p_SwPrs->numOfLabels*sizeof(t_FmPcdPrsLabelParams)); -+ p_FmPcd->p_FmPcdPrs->currLabel += p_SwPrs->numOfLabels; -+ -+ /* load sw parser code */ -+ p_LoadTarget = p_FmPcd->p_FmPcdPrs->p_SwPrsCode + p_SwPrs->base*2/4; -+ -+ for(i=0; isize, 4); i++) -+ WRITE_UINT32(p_LoadTarget[i], GET_UINT32(p_TmpCode[i])); -+ -+ p_FmPcd->p_FmPcdPrs->p_CurrSwPrs = -+ p_FmPcd->p_FmPcdPrs->p_SwPrsCode + p_SwPrs->base*2/4 + ROUND_UP(p_SwPrs->size,4); -+ -+ /* copy data parameters */ -+ for (i=0;ip_FmPcdPrs->p_SwPrsCode+PRS_SW_DATA/4+i), p_SwPrs->swPrsDataParams[i]); -+ -+ /* Clear last 4 bytes */ -+ WRITE_UINT32(*(p_FmPcd->p_FmPcdPrs->p_SwPrsCode+(PRS_SW_DATA-FM_PCD_PRS_SW_TAIL_SIZE)/4), 0); -+ -+ XX_FreeSmart(p_TmpCode); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_ConfigPrsMaxCycleLimit(t_Handle h_FmPcd,uint16_t value) -+{ -+ t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdDriverParam, E_INVALID_HANDLE); -+ -+ if(p_FmPcd->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_ConfigPrsMaxCycleLimit - guest mode!")); -+ -+ p_FmPcd->p_FmPcdDriverParam->prsMaxParseCycleLimit = value; -+ -+ return E_OK; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.h -@@ -0,0 +1,316 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_prs.h -+ -+ @Description FM Parser private header -+ *//***************************************************************************/ -+#ifndef __FM_PRS_H -+#define __FM_PRS_H -+ -+#include "std_ext.h" -+ -+/***********************************************************************/ -+/* SW parser IP_FRAG patch */ -+/***********************************************************************/ -+ -+#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+#define SW_PRS_UDP_LITE_PATCH \ -+{\ -+ 0x31,0x52,0x00,0xDA,0xFC,0x00,0x00,0x00,0x00,0x00, \ -+ 0x00,0x00,0x50,0x2C,0x40,0x00,0x31,0x92,0x50,0x2C, \ -+ 0x00,0x88,0x18,0x2F,0x00,0x01,0x1B,0xFE,0x18,0x71, \ -+ 0x02,0x1F,0x00,0x08,0x00,0x83,0x02,0x1F,0x00,0x20, \ -+ 0x28,0x1B,0x00,0x05,0x29,0x1F,0x30,0xD0,0x60,0x4F, \ -+ 0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F,0x00,0x52, \ -+ 0x00,0x01,0x07,0x01,0x60,0x3B,0x00,0x00,0x30,0xD0, \ -+ 0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00, \ -+ 0x40,0x4C,0x00,0x00,0x02,0x8F,0x00,0x00,0x30,0xF2, \ -+ 0x00,0x06,0x18,0x5D,0x00,0x00,0x9F,0xFF,0x30,0xF2, \ -+ 0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0,0x00,0x52, \ -+ 0x00,0x08,0x28,0x1A,0x60,0x37,0x00,0x00,0x30,0xF2, \ -+ 0x18,0x5D,0x06,0x00,0x29,0x1E,0x30,0xF2,0x2F,0x0E, \ -+ 0x30,0x72,0x00,0x00,0x9B,0x8F,0x00,0x06,0x2F,0x0E, \ -+ 0x32,0xF1,0x32,0xB0,0x00,0x4F,0x00,0x57,0x00,0x28, \ -+ 0x00,0x00,0x97,0x9E,0x00,0x4E,0x30,0x72,0x00,0x06, \ -+ 0x2F,0x0E,0x32,0xC1,0x32,0xF0,0x00,0x4A,0x00,0x80, \ -+ 0x00,0x02,0x00,0x00,0x97,0x9E,0x40,0x7E,0x00,0x08, \ -+ 0x08,0x16,0x00,0x54,0x00,0x01,0x1B,0xFE,0x00,0x00, \ -+ 0x9F,0x9E,0x40,0xB3,0x00,0x00,0x02,0x1F,0x00,0x08, \ -+ 0x28,0x1B,0x30,0x73,0x29,0x1F,0x30,0xD0,0x60,0x9F, \ -+ 0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F,0x00,0x52, \ -+ 0x00,0x01,0x07,0x01,0x60,0x8B,0x00,0x00,0x30,0xD0, \ -+ 0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00, \ -+ 0x40,0x9C,0x00,0x00,0x02,0x8F,0x00,0x00,0x30,0xF2, \ -+ 0x00,0x06,0x18,0xAD,0x00,0x00,0x9F,0xFF,0x30,0xF2, \ -+ 0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0,0x00,0x52, \ -+ 0x00,0x08,0x28,0x1A,0x60,0x87,0x00,0x00,0x30,0xF2, \ -+ 0x18,0xAD,0x06,0x00,0x29,0x1E,0x30,0xF2,0x50,0xB3, \ -+ 0xFF,0xFF,0x18,0xB8,0x08,0x16,0x00,0x54,0x00,0x01, \ -+ 0x1B,0xFE,0x18,0xC5,0x32,0xF1,0x28,0x5D,0x32,0xF1, \ -+ 0x00,0x55,0x00,0x08,0x28,0x5F,0x00,0x00,0x8F,0x9F, \ -+ 0x29,0x33,0x08,0x16,0x00,0x49,0x00,0x01,0x1B,0xFF, \ -+ 0x00,0x01,0x1B,0xFF \ -+} -+#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+ -+#if (DPAA_VERSION == 10) -+/* Version: 106.1.9 */ -+#define SW_PRS_OFFLOAD_PATCH \ -+{ \ -+ 0x31,0x52,0x00,0xDA,0x0A,0x00,0x00,0x00,0x00,0x00, \ -+ 0x00,0x00,0x43,0x0A,0x00,0x00,0x00,0x01,0x1B,0xFE, \ -+ 0x00,0x00,0x99,0x00,0x53,0x13,0x00,0x00,0x00,0x00, \ -+ 0x9F,0x98,0x53,0x13,0x00,0x00,0x1B,0x23,0x33,0xF1, \ -+ 0x00,0xF9,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00, \ -+ 0x28,0x7F,0x00,0x03,0x00,0x02,0x00,0x00,0x00,0x01, \ -+ 0x32,0xC1,0x32,0xF0,0x00,0x4A,0x00,0x80,0x1F,0xFF, \ -+ 0x00,0x01,0x1B,0xFE,0x31,0x52,0x00,0xDA,0x06,0x00, \ -+ 0x00,0x00,0x00,0x00,0x00,0x00,0x43,0x2F,0x00,0x00, \ -+ 0x00,0x01,0x1B,0xFE,0x31,0x52,0x00,0xDA,0x00,0x40, \ -+ 0x00,0x00,0x00,0x00,0x00,0x00,0x53,0x95,0x00,0x00, \ -+ 0x00,0x00,0x9B,0x8F,0x2F,0x0F,0x32,0xC1,0x00,0x55, \ -+ 0x00,0x28,0x28,0x43,0x30,0x7E,0x43,0x45,0x00,0x00, \ -+ 0x30,0x7E,0x43,0x45,0x00,0x3C,0x1B,0x5D,0x32,0x11, \ -+ 0x32,0xC0,0x00,0x4F,0x00,0x81,0x00,0x00,0x83,0x8F, \ -+ 0x2F,0x0F,0x06,0x00,0x32,0x11,0x32,0xC0,0x00,0x4F, \ -+ 0x00,0x55,0x00,0x01,0x00,0x81,0x32,0x11,0x00,0x00, \ -+ 0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04,0x00,0x4D, \ -+ 0x28,0x43,0x06,0x00,0x1B,0x3E,0x30,0x7E,0x53,0x79, \ -+ 0x00,0x2B,0x32,0x11,0x32,0xC0,0x00,0x4F,0x00,0x81, \ -+ 0x00,0x00,0x87,0x8F,0x28,0x23,0x06,0x00,0x32,0x11, \ -+ 0x32,0xC0,0x00,0x4F,0x00,0x55,0x00,0x01,0x00,0x81, \ -+ 0x32,0x11,0x00,0x00,0x83,0x8E,0x00,0x50,0x00,0x01, \ -+ 0x01,0x04,0x00,0x4D,0x28,0x43,0x06,0x00,0x00,0x01, \ -+ 0x1B,0xFE,0x00,0x00,0x9B,0x8E,0x53,0x90,0x00,0x00, \ -+ 0x06,0x29,0x00,0x00,0x83,0x8F,0x28,0x23,0x06,0x00, \ -+ 0x06,0x29,0x32,0xC1,0x00,0x55,0x00,0x28,0x00,0x00, \ -+ 0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04,0x00,0x4D, \ -+ 0x28,0x43,0x06,0x00,0x00,0x01,0x1B,0xFE,0x32,0xC1, \ -+ 0x00,0x55,0x00,0x28,0x28,0x43,0x1B,0xCF,0x00,0x00, \ -+ 0x9B,0x8F,0x2F,0x0F,0x32,0xC1,0x00,0x55,0x00,0x28, \ -+ 0x28,0x43,0x30,0x7E,0x43,0xBF,0x00,0x2C,0x32,0x11, \ -+ 0x32,0xC0,0x00,0x4F,0x00,0x81,0x00,0x00,0x87,0x8F, \ -+ 0x28,0x23,0x06,0x00,0x32,0x11,0x32,0xC0,0x00,0x4F, \ -+ 0x00,0x81,0x00,0x00,0x83,0x8F,0x2F,0x0F,0x06,0x00, \ -+ 0x32,0x11,0x32,0xC0,0x00,0x4F,0x00,0x55,0x00,0x01, \ -+ 0x00,0x81,0x32,0x11,0x00,0x00,0x83,0x8E,0x00,0x50, \ -+ 0x00,0x01,0x01,0x04,0x00,0x4D,0x28,0x43,0x06,0x00, \ -+ 0x1B,0x9C,0x33,0xF1,0x00,0xF9,0x00,0x01,0x00,0x00, \ -+ 0x00,0x00,0x00,0x00,0x28,0x7F,0x00,0x03,0x00,0x02, \ -+ 0x00,0x00,0x00,0x01,0x32,0xC1,0x32,0xF0,0x00,0x4A, \ -+ 0x00,0x80,0x1F,0xFF,0x00,0x01,0x1B,0xFE, \ -+} -+ -+#else -+#define SW_PRS_OFFLOAD_PATCH \ -+{ \ -+ 0x31,0x52,0x00,0xDA,0x0E,0x4F,0x00,0x00,0x00,0x00, \ -+ 0x00,0x00,0x51,0x16,0x08,0x4B,0x31,0x53,0x00,0xFB, \ -+ 0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x29,0x2B, \ -+ 0x33,0xF1,0x00,0xFB,0x00,0xDF,0x00,0x00,0x00,0x00, \ -+ 0x00,0x00,0x28,0x7F,0x31,0x52,0x00,0xDA,0x0A,0x00, \ -+ 0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x20,0x00,0x00, \ -+ 0x00,0x01,0x1B,0xFE,0x00,0x00,0x99,0x00,0x51,0x29, \ -+ 0x00,0x00,0x00,0x00,0x9F,0x98,0x51,0x29,0x00,0x00, \ -+ 0x19,0x44,0x09,0x5F,0x00,0x20,0x00,0x00,0x09,0x4F, \ -+ 0x00,0x20,0x00,0x00,0x34,0xB7,0x00,0xF9,0x00,0x00, \ -+ 0x01,0x00,0x00,0x00,0x00,0x00,0x2B,0x97,0x31,0xB3, \ -+ 0x29,0x8F,0x33,0xF1,0x00,0xF9,0x00,0x01,0x00,0x00, \ -+ 0x00,0x00,0x00,0x00,0x28,0x7F,0x00,0x03,0x00,0x02, \ -+ 0x00,0x00,0x00,0x01,0x1B,0xFE,0x00,0x01,0x1B,0xFE, \ -+ 0x31,0x52,0x00,0xDA,0xFC,0x00,0x00,0x00,0x00,0x00, \ -+ 0x00,0x00,0x51,0x52,0x40,0x00,0x31,0x92,0x51,0x52, \ -+ 0x00,0x88,0x19,0x55,0x08,0x05,0x00,0x00,0x19,0x99, \ -+ 0x02,0x1F,0x00,0x08,0x00,0x83,0x02,0x1F,0x00,0x20, \ -+ 0x28,0x1B,0x00,0x05,0x29,0x1F,0x30,0xD0,0x61,0x75, \ -+ 0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F,0x00,0x52, \ -+ 0x00,0x01,0x07,0x01,0x61,0x61,0x00,0x00,0x30,0xD0, \ -+ 0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00, \ -+ 0x41,0x72,0x00,0x00,0x02,0x8F,0x00,0x00,0x30,0xF2, \ -+ 0x00,0x06,0x19,0x83,0x00,0x00,0x9F,0xFF,0x30,0xF2, \ -+ 0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0,0x00,0x52, \ -+ 0x00,0x08,0x28,0x1A,0x61,0x5D,0x00,0x00,0x30,0xF2, \ -+ 0x19,0x83,0x06,0x00,0x29,0x1E,0x30,0xF2,0x29,0x0E, \ -+ 0x30,0x72,0x00,0x00,0x9B,0x8F,0x00,0x06,0x29,0x0E, \ -+ 0x32,0xF1,0x32,0xB0,0x00,0x4F,0x00,0x57,0x00,0x28, \ -+ 0x00,0x00,0x97,0x9E,0x00,0x4E,0x30,0x72,0x00,0x06, \ -+ 0x29,0x0E,0x08,0x05,0x00,0x01,0x31,0x52,0x00,0xDA, \ -+ 0x0E,0x4F,0x00,0x00,0x00,0x00,0x00,0x00,0x51,0xAF, \ -+ 0x04,0x4B,0x31,0x53,0x00,0xFB,0xFF,0xF0,0x00,0x00, \ -+ 0x00,0x00,0x00,0x00,0x29,0x2B,0x33,0xF1,0x00,0xFB, \ -+ 0x00,0xDF,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x7F, \ -+ 0x31,0x52,0x00,0xDA,0x06,0x00,0x00,0x00,0x00,0x00, \ -+ 0x00,0x00,0x41,0xB9,0x00,0x00,0x00,0x01,0x1B,0xFE, \ -+ 0x31,0x52,0x00,0xDA,0x00,0x40,0x00,0x00,0x00,0x00, \ -+ 0x00,0x00,0x42,0x06,0x00,0x00,0x00,0x00,0x9B,0x8F, \ -+ 0x28,0x01,0x32,0xC1,0x00,0x55,0x00,0x28,0x28,0x43, \ -+ 0x30,0x00,0x41,0xEB,0x00,0x2C,0x32,0x11,0x32,0xC0, \ -+ 0x00,0x4F,0x00,0x81,0x00,0x00,0x87,0x8F,0x28,0x23, \ -+ 0x06,0x00,0x32,0x11,0x32,0xC0,0x00,0x4F,0x00,0x81, \ -+ 0x00,0x00,0x83,0x8F,0x28,0x01,0x06,0x00,0x32,0x11, \ -+ 0x32,0xC0,0x00,0x4F,0x00,0x55,0x00,0x01,0x00,0x81, \ -+ 0x32,0x11,0x00,0x00,0x83,0x8E,0x00,0x50,0x00,0x01, \ -+ 0x01,0x04,0x00,0x4D,0x28,0x43,0x06,0x00,0x19,0xC8, \ -+ 0x09,0x5F,0x00,0x20,0x00,0x00,0x09,0x4F,0x00,0x20, \ -+ 0x00,0x00,0x34,0xB7,0x00,0xF9,0x00,0x00,0x01,0x00, \ -+ 0x00,0x00,0x00,0x00,0x2B,0x97,0x31,0xB3,0x29,0x8F, \ -+ 0x33,0xF1,0x00,0xF9,0x00,0x01,0x00,0x00,0x00,0x00, \ -+ 0x00,0x00,0x28,0x7F,0x00,0x03,0x00,0x02,0x00,0x00, \ -+ 0x00,0x01,0x1B,0xFE,0x30,0x50,0x52,0x0B,0x00,0x00, \ -+ 0x00,0x01,0x1B,0xFE,0x32,0xF1,0x32,0xC0,0x00,0x4F, \ -+ 0x00,0x81,0x00,0x02,0x00,0x00,0x97,0x9E,0x42,0x18, \ -+ 0x00,0x08,0x08,0x16,0x00,0x54,0x00,0x01,0x1B,0xFE, \ -+ 0x00,0x00,0x9F,0x9E,0x42,0x4D,0x00,0x00,0x02,0x1F, \ -+ 0x00,0x08,0x28,0x1B,0x30,0x73,0x29,0x1F,0x30,0xD0, \ -+ 0x62,0x39,0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F, \ -+ 0x00,0x52,0x00,0x01,0x07,0x01,0x62,0x25,0x00,0x00, \ -+ 0x30,0xD0,0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00, \ -+ 0x00,0x00,0x42,0x36,0x00,0x00,0x02,0x8F,0x00,0x00, \ -+ 0x30,0xF2,0x00,0x06,0x1A,0x47,0x00,0x00,0x9F,0xFF, \ -+ 0x30,0xF2,0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0, \ -+ 0x00,0x52,0x00,0x08,0x28,0x1A,0x62,0x21,0x00,0x00, \ -+ 0x30,0xF2,0x1A,0x47,0x06,0x00,0x29,0x1E,0x30,0xF2, \ -+ 0x52,0x4D,0xFF,0xFF,0x1A,0x52,0x08,0x16,0x00,0x54, \ -+ 0x00,0x01,0x1B,0xFE,0x1A,0x5F,0x32,0xF1,0x28,0x5D, \ -+ 0x32,0xF1,0x00,0x55,0x00,0x08,0x28,0x5F,0x00,0x00, \ -+ 0x8F,0x9F,0x29,0x33,0x08,0x16,0x00,0x49,0x00,0x01, \ -+ 0x1B,0xFF,0x00,0x01,0x1B,0xFF,0x31,0x52,0x00,0xDA, \ -+ 0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x52,0x6D, \ -+ 0x40,0x00,0x31,0x92,0x52,0x6D,0x00,0x88,0x1A,0x70, \ -+ 0x08,0x05,0x00,0x00,0x1A,0xB4,0x02,0x1F,0x00,0x08, \ -+ 0x00,0x83,0x02,0x1F,0x00,0x20,0x28,0x1B,0x00,0x05, \ -+ 0x29,0x1F,0x30,0xD0,0x62,0x90,0x00,0x07,0x00,0x05, \ -+ 0x00,0x00,0xC3,0x8F,0x00,0x52,0x00,0x01,0x07,0x01, \ -+ 0x62,0x7C,0x00,0x00,0x30,0xD0,0x00,0xDA,0x00,0x01, \ -+ 0x00,0x00,0x00,0x00,0x00,0x00,0x42,0x8D,0x00,0x00, \ -+ 0x02,0x8F,0x00,0x00,0x30,0xF2,0x00,0x06,0x1A,0x9E, \ -+ 0x00,0x00,0x9F,0xFF,0x30,0xF2,0x00,0x06,0x29,0x1E, \ -+ 0x07,0x08,0x30,0xD0,0x00,0x52,0x00,0x08,0x28,0x1A, \ -+ 0x62,0x78,0x00,0x00,0x30,0xF2,0x1A,0x9E,0x06,0x00, \ -+ 0x29,0x1E,0x30,0xF2,0x29,0x0E,0x30,0x72,0x00,0x00, \ -+ 0x9B,0x8F,0x00,0x06,0x29,0x0E,0x32,0xF1,0x32,0xB0, \ -+ 0x00,0x4F,0x00,0x57,0x00,0x28,0x00,0x00,0x97,0x9E, \ -+ 0x00,0x4E,0x30,0x72,0x00,0x06,0x29,0x0E,0x08,0x05, \ -+ 0x00,0x01,0x31,0x52,0x00,0xDA,0x0E,0x4F,0x00,0x00, \ -+ 0x00,0x00,0x00,0x00,0x52,0xCA,0x04,0x4B,0x31,0x53, \ -+ 0x00,0xFB,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, \ -+ 0x29,0x2B,0x33,0xF1,0x00,0xFB,0x00,0xDF,0x00,0x00, \ -+ 0x00,0x00,0x00,0x00,0x28,0x7F,0x31,0x52,0x00,0xDA, \ -+ 0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x42,0xD4, \ -+ 0x00,0x00,0x00,0x01,0x1B,0xFE,0x31,0x52,0x00,0xDA, \ -+ 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x53,0x37, \ -+ 0x00,0x00,0x00,0x00,0x9B,0x8F,0x28,0x01,0x32,0xC1, \ -+ 0x00,0x55,0x00,0x28,0x28,0x43,0x30,0x00,0x42,0xEA, \ -+ 0x00,0x00,0x30,0x00,0x42,0xEA,0x00,0x3C,0x1B,0x02, \ -+ 0x32,0x11,0x32,0xC0,0x00,0x4F,0x00,0x81,0x00,0x00, \ -+ 0x83,0x8F,0x28,0x01,0x06,0x00,0x32,0x11,0x32,0xC0, \ -+ 0x00,0x4F,0x00,0x55,0x00,0x01,0x00,0x81,0x32,0x11, \ -+ 0x00,0x00,0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04, \ -+ 0x00,0x4D,0x28,0x43,0x06,0x00,0x1A,0xE3,0x30,0x00, \ -+ 0x43,0x20,0x00,0x2B,0x00,0x00,0x9B,0x8E,0x43,0x0E, \ -+ 0x00,0x00,0x32,0xC1,0x00,0x55,0x00,0x28,0x28,0x43, \ -+ 0x1B,0x1F,0x06,0x29,0x00,0x00,0x83,0x8F,0x28,0x23, \ -+ 0x06,0x00,0x06,0x29,0x32,0xC1,0x00,0x55,0x00,0x28, \ -+ 0x00,0x00,0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04, \ -+ 0x00,0x4D,0x28,0x43,0x06,0x00,0x1B,0x37,0x32,0x11, \ -+ 0x32,0xC0,0x00,0x4F,0x00,0x81,0x00,0x00,0x87,0x8F, \ -+ 0x28,0x23,0x06,0x00,0x32,0x11,0x32,0xC0,0x00,0x4F, \ -+ 0x00,0x55,0x00,0x01,0x00,0x81,0x32,0x11,0x00,0x00, \ -+ 0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04,0x00,0x4D, \ -+ 0x28,0x43,0x06,0x00,0x30,0x50,0x53,0x3C,0x00,0x00, \ -+ 0x00,0x01,0x1B,0xFE,0x32,0xF1,0x32,0xC0,0x00,0x4F, \ -+ 0x00,0x81,0x00,0x02,0x00,0x00,0x97,0x9E,0x43,0x49, \ -+ 0x00,0x08,0x08,0x16,0x00,0x54,0x00,0x01,0x1B,0xFE, \ -+ 0x00,0x00,0x9F,0x9E,0x43,0x7E,0x00,0x00,0x02,0x1F, \ -+ 0x00,0x08,0x28,0x1B,0x30,0x73,0x29,0x1F,0x30,0xD0, \ -+ 0x63,0x6A,0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F, \ -+ 0x00,0x52,0x00,0x01,0x07,0x01,0x63,0x56,0x00,0x00, \ -+ 0x30,0xD0,0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00, \ -+ 0x00,0x00,0x43,0x67,0x00,0x00,0x02,0x8F,0x00,0x00, \ -+ 0x30,0xF2,0x00,0x06,0x1B,0x78,0x00,0x00,0x9F,0xFF, \ -+ 0x30,0xF2,0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0, \ -+ 0x00,0x52,0x00,0x08,0x28,0x1A,0x63,0x52,0x00,0x00, \ -+ 0x30,0xF2,0x1B,0x78,0x06,0x00,0x29,0x1E,0x30,0xF2, \ -+ 0x53,0x7E,0xFF,0xFF,0x1B,0x83,0x08,0x16,0x00,0x54, \ -+ 0x00,0x01,0x1B,0xFE,0x1B,0x90,0x32,0xF1,0x28,0x5D, \ -+ 0x32,0xF1,0x00,0x55,0x00,0x08,0x28,0x5F,0x00,0x00, \ -+ 0x8F,0x9F,0x29,0x33,0x08,0x16,0x00,0x49,0x00,0x01, \ -+ 0x1B,0xFF,0x00,0x01,0x1B,0xFF,0x08,0x07,0x00,0x02, \ -+ 0x00,0x00,0x8D,0x80,0x53,0x9C,0x00,0x01,0x30,0x71, \ -+ 0x00,0x55,0x00,0x01,0x28,0x0F,0x00,0x00,0x8D,0x00, \ -+ 0x53,0xA4,0x00,0x01,0x30,0x71,0x00,0x55,0x00,0x01, \ -+ 0x28,0x0F,0x00,0x00,0x83,0x8E,0x53,0xB9,0x00,0x00, \ -+ 0x00,0x00,0x86,0x08,0x30,0x71,0x00,0x7B,0x03,0xB9, \ -+ 0x33,0xB4,0x00,0xDA,0xFF,0xFF,0x00,0x0F,0x00,0x00, \ -+ 0x00,0x00,0x00,0x00,0x86,0x09,0x01,0x03,0x00,0x7D, \ -+ 0x03,0xB9,0x1B,0xC8,0x33,0xD1,0x00,0xF9,0x00,0x10, \ -+ 0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x7B,0x09,0x5F, \ -+ 0x00,0x1A,0x00,0x00,0x09,0x4F,0x00,0x1A,0x00,0x00, \ -+ 0x00,0x01,0x1B,0xFF,0x00,0x00,0x8C,0x00,0x53,0xF0, \ -+ 0x00,0x01,0x34,0xF5,0x00,0xFB,0xFF,0xFF,0x00,0x7F, \ -+ 0x00,0x00,0x00,0x00,0x2A,0x9F,0x00,0x00,0x93,0x8F, \ -+ 0x28,0x49,0x00,0x00,0x97,0x8F,0x28,0x4B,0x34,0x61, \ -+ 0x28,0x4D,0x34,0x71,0x28,0x4F,0x34,0xB7,0x00,0xF9, \ -+ 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x2B,0x97, \ -+ 0x33,0xF1,0x00,0xF9,0x00,0x01,0x00,0x00,0x00,0x00, \ -+ 0x00,0x00,0x28,0x7F,0x00,0x03,0x00,0x02,0x00,0x00, \ -+ 0x00,0x01,0x1B,0xFF,0x00,0x01,0x1B,0xFF, \ -+} -+#endif /* (DPAA_VERSION == 10) */ -+ -+/****************************/ -+/* Parser defines */ -+/****************************/ -+#define FM_PCD_PRS_SW_TAIL_SIZE 4 /**< Number of bytes that must be cleared at -+ the end of the SW parser area */ -+ -+/* masks */ -+#define PRS_ERR_CAP 0x80000000 -+#define PRS_ERR_TYPE_DOUBLE 0x40000000 -+#define PRS_ERR_SINGLE_ECC_CNT_MASK 0x00FF0000 -+#define PRS_ERR_ADDR_MASK 0x000001FF -+ -+/* others */ -+#define PRS_MAX_CYCLE_LIMIT 8191 -+#define PRS_SW_DATA 0x00000800 -+#define PRS_REGS_OFFSET 0x00000840 -+ -+#define GET_FM_PCD_PRS_PORT_ID(prsPortId,hardwarePortId) \ -+ prsPortId = (uint8_t)(hardwarePortId & 0x0f) -+ -+#define GET_FM_PCD_INDEX_FLAG(bitMask, prsPortId) \ -+ bitMask = 0x80000000>>prsPortId -+ -+#endif /* __FM_PRS_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_replic.c -@@ -0,0 +1,984 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_replic.c -+ -+ @Description FM frame replicator -+*//***************************************************************************/ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "string_ext.h" -+#include "debug_ext.h" -+#include "fm_pcd_ext.h" -+#include "fm_muram_ext.h" -+#include "fm_common.h" -+#include "fm_hc.h" -+#include "fm_replic.h" -+#include "fm_cc.h" -+#include "list_ext.h" -+ -+ -+/****************************************/ -+/* static functions */ -+/****************************************/ -+static uint8_t GetMemberPosition(t_FmPcdFrmReplicGroup *p_ReplicGroup, -+ uint32_t memberIndex, -+ bool isAddOperation) -+{ -+ uint8_t memberPosition; -+ uint32_t lastMemberIndex; -+ -+ ASSERT_COND(p_ReplicGroup); -+ -+ /* the last member index is different between add and remove operation - -+ in case of remove - this is exactly the last member index -+ in case of add - this is the last member index + 1 - e.g. -+ if we have 4 members, the index of the actual last member is 3(because the -+ index starts from 0) therefore in order to add a new member as the last -+ member we shall use memberIndex = 4 and not 3 -+ */ -+ if (isAddOperation) -+ lastMemberIndex = p_ReplicGroup->numOfEntries; -+ else -+ lastMemberIndex = p_ReplicGroup->numOfEntries-1; -+ -+ /* last */ -+ if (memberIndex == lastMemberIndex) -+ memberPosition = FRM_REPLIC_LAST_MEMBER_INDEX; -+ else -+ { -+ /* first */ -+ if (memberIndex == 0) -+ memberPosition = FRM_REPLIC_FIRST_MEMBER_INDEX; -+ else -+ { -+ /* middle */ -+ ASSERT_COND(memberIndex < lastMemberIndex); -+ memberPosition = FRM_REPLIC_MIDDLE_MEMBER_INDEX; -+ } -+ } -+ return memberPosition; -+} -+ -+static t_Error MemberCheckParams(t_Handle h_FmPcd, -+ t_FmPcdCcNextEngineParams *p_MemberParams) -+{ -+ t_Error err; -+ -+ -+ if ((p_MemberParams->nextEngine != e_FM_PCD_DONE) && -+ (p_MemberParams->nextEngine != e_FM_PCD_KG) && -+ (p_MemberParams->nextEngine != e_FM_PCD_PLCR)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Next engine of a member should be MatchTable(cc) or Done or Policer")); -+ -+ /* check the regular parameters of the next engine */ -+ err = ValidateNextEngineParams(h_FmPcd, p_MemberParams, e_FM_PCD_CC_STATS_MODE_NONE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, ("member next engine parameters")); -+ -+ return E_OK; -+} -+ -+static t_Error CheckParams(t_Handle h_FmPcd, -+ t_FmPcdFrmReplicGroupParams *p_ReplicGroupParam) -+{ -+ int i; -+ t_Error err; -+ -+ /* check that max num of entries is at least 2 */ -+ if (!IN_RANGE(2, p_ReplicGroupParam->maxNumOfEntries, FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES)) -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, ("maxNumOfEntries in the frame replicator parameters should be 2-%d",FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES)); -+ -+ /* check that number of entries is greater than zero */ -+ if (!p_ReplicGroupParam->numOfEntries) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numOFEntries in the frame replicator group should be greater than zero")); -+ -+ /* check that max num of entries is equal or greater than number of entries */ -+ if (p_ReplicGroupParam->maxNumOfEntries < p_ReplicGroupParam->numOfEntries) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("maxNumOfEntries should be equal or greater than numOfEntries")); -+ -+ for (i=0; inumOfEntries; i++) -+ { -+ err = MemberCheckParams(h_FmPcd, &p_ReplicGroupParam->nextEngineParams[i]); -+ if (err) -+ RETURN_ERROR(MAJOR, err, ("member check parameters")); -+ } -+ return E_OK; -+} -+ -+static t_FmPcdFrmReplicMember *GetAvailableMember(t_FmPcdFrmReplicGroup *p_ReplicGroup) -+{ -+ t_FmPcdFrmReplicMember *p_ReplicMember = NULL; -+ t_List *p_Next; -+ -+ if (!LIST_IsEmpty(&p_ReplicGroup->availableMembersList)) -+ { -+ p_Next = LIST_FIRST(&p_ReplicGroup->availableMembersList); -+ p_ReplicMember = LIST_OBJECT(p_Next, t_FmPcdFrmReplicMember, node); -+ ASSERT_COND(p_ReplicMember); -+ LIST_DelAndInit(p_Next); -+ } -+ return p_ReplicMember; -+} -+ -+static void PutAvailableMember(t_FmPcdFrmReplicGroup *p_ReplicGroup, -+ t_FmPcdFrmReplicMember *p_ReplicMember) -+{ -+ LIST_AddToTail(&p_ReplicMember->node, &p_ReplicGroup->availableMembersList); -+} -+ -+static void AddMemberToList(t_FmPcdFrmReplicGroup *p_ReplicGroup, -+ t_FmPcdFrmReplicMember *p_CurrentMember, -+ t_List *p_ListHead) -+{ -+ LIST_Add(&p_CurrentMember->node, p_ListHead); -+ -+ p_ReplicGroup->numOfEntries++; -+} -+ -+static void RemoveMemberFromList(t_FmPcdFrmReplicGroup *p_ReplicGroup, -+ t_FmPcdFrmReplicMember *p_CurrentMember) -+{ -+ ASSERT_COND(p_ReplicGroup->numOfEntries); -+ LIST_DelAndInit(&p_CurrentMember->node); -+ p_ReplicGroup->numOfEntries--; -+} -+ -+static void LinkSourceToMember(t_FmPcdFrmReplicGroup *p_ReplicGroup, -+ t_AdOfTypeContLookup *p_SourceTd, -+ t_FmPcdFrmReplicMember *p_ReplicMember) -+{ -+ t_FmPcd *p_FmPcd; -+ -+ ASSERT_COND(p_SourceTd); -+ ASSERT_COND(p_ReplicMember); -+ ASSERT_COND(p_ReplicGroup); -+ ASSERT_COND(p_ReplicGroup->h_FmPcd); -+ -+ /* Link the first member in the group to the source TD */ -+ p_FmPcd = p_ReplicGroup->h_FmPcd; -+ -+ WRITE_UINT32(p_SourceTd->matchTblPtr, -+ (uint32_t)(XX_VirtToPhys(p_ReplicMember->p_MemberAd) - -+ p_FmPcd->physicalMuramBase)); -+} -+ -+static void LinkMemberToMember(t_FmPcdFrmReplicGroup *p_ReplicGroup, -+ t_FmPcdFrmReplicMember *p_CurrentMember, -+ t_FmPcdFrmReplicMember *p_NextMember) -+{ -+ t_AdOfTypeResult *p_CurrReplicAd = (t_AdOfTypeResult*)p_CurrentMember->p_MemberAd; -+ t_AdOfTypeResult *p_NextReplicAd = NULL; -+ t_FmPcd *p_FmPcd; -+ uint32_t offset = 0; -+ -+ /* Check if the next member exists or it's NULL (- means that this is the last member) */ -+ if (p_NextMember) -+ { -+ p_NextReplicAd = (t_AdOfTypeResult*)p_NextMember->p_MemberAd; -+ p_FmPcd = p_ReplicGroup->h_FmPcd; -+ offset = (XX_VirtToPhys(p_NextReplicAd) - (p_FmPcd->physicalMuramBase)); -+ offset = ((offset>>NEXT_FRM_REPLIC_ADDR_SHIFT)<< NEXT_FRM_REPLIC_MEMBER_INDEX_SHIFT); -+ } -+ -+ /* link the current AD to point to the AD of the next member */ -+ WRITE_UINT32(p_CurrReplicAd->res, offset); -+} -+ -+static t_Error ModifyDescriptor(t_FmPcdFrmReplicGroup *p_ReplicGroup, -+ void *p_OldDescriptor, -+ void *p_NewDescriptor) -+{ -+ t_Handle h_Hc; -+ t_Error err; -+ t_FmPcd *p_FmPcd; -+ -+ ASSERT_COND(p_ReplicGroup); -+ ASSERT_COND(p_ReplicGroup->h_FmPcd); -+ ASSERT_COND(p_OldDescriptor); -+ ASSERT_COND(p_NewDescriptor); -+ -+ p_FmPcd = p_ReplicGroup->h_FmPcd; -+ h_Hc = FmPcdGetHcHandle(p_FmPcd); -+ if (!h_Hc) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("Host command")); -+ -+ err = FmHcPcdCcDoDynamicChange(h_Hc, -+ (uint32_t)(XX_VirtToPhys(p_OldDescriptor) - p_FmPcd->physicalMuramBase), -+ (uint32_t)(XX_VirtToPhys(p_NewDescriptor) - p_FmPcd->physicalMuramBase)); -+ if (err) -+ RETURN_ERROR(MAJOR, err, ("Dynamic change host command")); -+ -+ return E_OK; -+} -+ -+static void FillReplicAdOfTypeResult(void *p_ReplicAd, bool last) -+{ -+ t_AdOfTypeResult *p_CurrReplicAd = (t_AdOfTypeResult*)p_ReplicAd; -+ uint32_t tmp; -+ -+ tmp = GET_UINT32(p_CurrReplicAd->plcrProfile); -+ if (last) -+ /* clear the NL bit in case it's the last member in the group*/ -+ WRITE_UINT32(p_CurrReplicAd->plcrProfile,(tmp & ~FRM_REPLIC_NL_BIT)); -+ else -+ /* set the NL bit in case it's not the last member in the group */ -+ WRITE_UINT32(p_CurrReplicAd->plcrProfile, (tmp |FRM_REPLIC_NL_BIT)); -+ -+ /* set FR bit in the action descriptor */ -+ tmp = GET_UINT32(p_CurrReplicAd->nia); -+ WRITE_UINT32(p_CurrReplicAd->nia, -+ (tmp | FRM_REPLIC_FR_BIT | FM_PCD_AD_RESULT_EXTENDED_MODE )); -+} -+ -+static void BuildSourceTd(void *p_Ad) -+{ -+ t_AdOfTypeContLookup *p_SourceTd; -+ -+ ASSERT_COND(p_Ad); -+ -+ p_SourceTd = (t_AdOfTypeContLookup *)p_Ad; -+ -+ IOMemSet32((uint8_t*)p_SourceTd, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ /* initialize the source table descriptor */ -+ WRITE_UINT32(p_SourceTd->ccAdBase, FM_PCD_AD_CONT_LOOKUP_TYPE); -+ WRITE_UINT32(p_SourceTd->pcAndOffsets, FRM_REPLIC_SOURCE_TD_OPCODE); -+} -+ -+static t_Error BuildShadowAndModifyDescriptor(t_FmPcdFrmReplicGroup *p_ReplicGroup, -+ t_FmPcdFrmReplicMember *p_NextMember, -+ t_FmPcdFrmReplicMember *p_CurrentMember, -+ bool sourceDescriptor, -+ bool last) -+{ -+ t_FmPcd *p_FmPcd; -+ t_FmPcdFrmReplicMember shadowMember; -+ t_Error err; -+ -+ ASSERT_COND(p_ReplicGroup); -+ ASSERT_COND(p_ReplicGroup->h_FmPcd); -+ -+ p_FmPcd = p_ReplicGroup->h_FmPcd; -+ ASSERT_COND(p_FmPcd->p_CcShadow); -+ -+ if (!TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock)) -+ return ERROR_CODE(E_BUSY); -+ -+ if (sourceDescriptor) -+ { -+ BuildSourceTd(p_FmPcd->p_CcShadow); -+ LinkSourceToMember(p_ReplicGroup, p_FmPcd->p_CcShadow, p_NextMember); -+ -+ /* Modify the source table descriptor according to the prepared shadow descriptor */ -+ err = ModifyDescriptor(p_ReplicGroup, -+ p_ReplicGroup->p_SourceTd, -+ p_FmPcd->p_CcShadow/* new prepared source td */); -+ -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ if (err) -+ RETURN_ERROR(MAJOR, err, ("Modify source Descriptor in BuildShadowAndModifyDescriptor")); -+ -+ } -+ else -+ { -+ IO2IOCpy32(p_FmPcd->p_CcShadow, -+ p_CurrentMember->p_MemberAd, -+ FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ /* update the last bit in the shadow ad */ -+ FillReplicAdOfTypeResult(p_FmPcd->p_CcShadow, last); -+ -+ shadowMember.p_MemberAd = p_FmPcd->p_CcShadow; -+ -+ /* update the next FR member index */ -+ LinkMemberToMember(p_ReplicGroup, &shadowMember, p_NextMember); -+ -+ /* Modify the next member according to the prepared shadow descriptor */ -+ err = ModifyDescriptor(p_ReplicGroup, -+ p_CurrentMember->p_MemberAd, -+ p_FmPcd->p_CcShadow); -+ -+ RELEASE_LOCK(p_FmPcd->shadowLock); -+ if (err) -+ RETURN_ERROR(MAJOR, err, ("Modify Descriptor in BuildShadowAndModifyDescriptor")); -+ } -+ -+ -+ return E_OK; -+} -+ -+static t_FmPcdFrmReplicMember* GetMemberByIndex(t_FmPcdFrmReplicGroup *p_ReplicGroup, -+ uint16_t memberIndex) -+{ -+ int i=0; -+ t_List *p_Pos; -+ t_FmPcdFrmReplicMember *p_Member = NULL; -+ -+ LIST_FOR_EACH(p_Pos, &p_ReplicGroup->membersList) -+ { -+ if (i == memberIndex) -+ { -+ p_Member = LIST_OBJECT(p_Pos, t_FmPcdFrmReplicMember, node); -+ return p_Member; -+ } -+ i++; -+ } -+ return p_Member; -+} -+ -+static t_Error AllocMember(t_FmPcdFrmReplicGroup *p_ReplicGroup) -+{ -+ t_FmPcdFrmReplicMember *p_CurrentMember; -+ t_Handle h_Muram; -+ -+ ASSERT_COND(p_ReplicGroup); -+ -+ h_Muram = FmPcdGetMuramHandle(p_ReplicGroup->h_FmPcd); -+ ASSERT_COND(h_Muram); -+ -+ /* Initialize an internal structure of a member to add to the available members list */ -+ p_CurrentMember = (t_FmPcdFrmReplicMember *)XX_Malloc(sizeof(t_FmPcdFrmReplicMember)); -+ if (!p_CurrentMember) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Frame replicator member")); -+ -+ memset(p_CurrentMember, 0 ,sizeof(t_FmPcdFrmReplicMember)); -+ -+ /* Allocate the member AD */ -+ p_CurrentMember->p_MemberAd = -+ (t_AdOfTypeResult*)FM_MURAM_AllocMem(h_Muram, -+ FM_PCD_CC_AD_ENTRY_SIZE, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_CurrentMember->p_MemberAd) -+ { -+ XX_Free(p_CurrentMember); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("member AD table")); -+ } -+ IOMemSet32((uint8_t*)p_CurrentMember->p_MemberAd, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ /* Add the new member to the available members list */ -+ LIST_AddToTail(&p_CurrentMember->node, &(p_ReplicGroup->availableMembersList)); -+ -+ return E_OK; -+} -+ -+static t_FmPcdFrmReplicMember* InitMember(t_FmPcdFrmReplicGroup *p_ReplicGroup, -+ t_FmPcdCcNextEngineParams *p_MemberParams, -+ bool last) -+{ -+ t_FmPcdFrmReplicMember *p_CurrentMember = NULL; -+ -+ ASSERT_COND(p_ReplicGroup); -+ -+ /* Get an available member from the internal members list */ -+ p_CurrentMember = GetAvailableMember(p_ReplicGroup); -+ if (!p_CurrentMember) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_FOUND, ("Available member")); -+ return NULL; -+ } -+ p_CurrentMember->h_Manip = NULL; -+ -+ /* clear the Ad of the new member */ -+ IOMemSet32((uint8_t*)p_CurrentMember->p_MemberAd, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ INIT_LIST(&p_CurrentMember->node); -+ -+ /* Initialize the Ad of the member */ -+ NextStepAd(p_CurrentMember->p_MemberAd, -+ NULL, -+ p_MemberParams, -+ p_ReplicGroup->h_FmPcd); -+ -+ /* save Manip handle (for free needs) */ -+ if (p_MemberParams->h_Manip) -+ p_CurrentMember->h_Manip = p_MemberParams->h_Manip; -+ -+ /* Initialize the relevant frame replicator fields in the AD */ -+ FillReplicAdOfTypeResult(p_CurrentMember->p_MemberAd, last); -+ -+ return p_CurrentMember; -+} -+ -+static void FreeMember(t_FmPcdFrmReplicGroup *p_ReplicGroup, -+ t_FmPcdFrmReplicMember *p_Member) -+{ -+ /* Note: Can't free the member AD just returns the member to the available -+ member list - therefore only memset the AD */ -+ -+ /* zero the AD */ -+ IOMemSet32(p_Member->p_MemberAd, 0, FM_PCD_CC_AD_ENTRY_SIZE); -+ -+ -+ /* return the member to the available members list */ -+ PutAvailableMember(p_ReplicGroup, p_Member); -+} -+ -+static t_Error RemoveMember(t_FmPcdFrmReplicGroup *p_ReplicGroup, -+ uint16_t memberIndex) -+{ -+ t_FmPcd *p_FmPcd = NULL; -+ t_FmPcdFrmReplicMember *p_CurrentMember = NULL, *p_PreviousMember = NULL, *p_NextMember = NULL; -+ t_Error err; -+ uint8_t memberPosition; -+ -+ p_FmPcd = p_ReplicGroup->h_FmPcd; -+ ASSERT_COND(p_FmPcd); -+ UNUSED(p_FmPcd); -+ -+ p_CurrentMember = GetMemberByIndex(p_ReplicGroup, memberIndex); -+ ASSERT_COND(p_CurrentMember); -+ -+ /* determine the member position in the group */ -+ memberPosition = GetMemberPosition(p_ReplicGroup, -+ memberIndex, -+ FALSE/*remove operation*/); -+ -+ switch (memberPosition) -+ { -+ case FRM_REPLIC_FIRST_MEMBER_INDEX: -+ p_NextMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex+1)); -+ ASSERT_COND(p_NextMember); -+ -+ /* update the source td itself by using a host command */ -+ err = BuildShadowAndModifyDescriptor(p_ReplicGroup, -+ p_NextMember, -+ NULL, -+ TRUE/*sourceDescriptor*/, -+ FALSE/*last*/); -+ break; -+ -+ case FRM_REPLIC_MIDDLE_MEMBER_INDEX: -+ p_PreviousMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex-1)); -+ ASSERT_COND(p_PreviousMember); -+ -+ p_NextMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex+1)); -+ ASSERT_COND(p_NextMember); -+ -+ err = BuildShadowAndModifyDescriptor(p_ReplicGroup, -+ p_NextMember, -+ p_PreviousMember, -+ FALSE/*sourceDescriptor*/, -+ FALSE/*last*/); -+ -+ break; -+ -+ case FRM_REPLIC_LAST_MEMBER_INDEX: -+ p_PreviousMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex-1)); -+ ASSERT_COND(p_PreviousMember); -+ -+ err = BuildShadowAndModifyDescriptor(p_ReplicGroup, -+ NULL, -+ p_PreviousMember, -+ FALSE/*sourceDescriptor*/, -+ TRUE/*last*/); -+ break; -+ -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("member position in remove member")); -+ } -+ -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (p_CurrentMember->h_Manip) -+ { -+ FmPcdManipUpdateOwner(p_CurrentMember->h_Manip, FALSE); -+ p_CurrentMember->h_Manip = NULL; -+ } -+ -+ /* remove the member from the driver internal members list */ -+ RemoveMemberFromList(p_ReplicGroup, p_CurrentMember); -+ -+ /* return the member to the available members list */ -+ FreeMember(p_ReplicGroup, p_CurrentMember); -+ -+ return E_OK; -+} -+ -+static void DeleteGroup(t_FmPcdFrmReplicGroup *p_ReplicGroup) -+{ -+ int i, j; -+ t_Handle h_Muram; -+ t_FmPcdFrmReplicMember *p_Member, *p_CurrentMember; -+ -+ if (p_ReplicGroup) -+ { -+ ASSERT_COND(p_ReplicGroup->h_FmPcd); -+ h_Muram = FmPcdGetMuramHandle(p_ReplicGroup->h_FmPcd); -+ ASSERT_COND(h_Muram); -+ -+ /* free the source table descriptor */ -+ if (p_ReplicGroup->p_SourceTd) -+ { -+ FM_MURAM_FreeMem(h_Muram, p_ReplicGroup->p_SourceTd); -+ p_ReplicGroup->p_SourceTd = NULL; -+ } -+ -+ /* Remove all members from the members linked list (hw and sw) and -+ return the members to the available members list */ -+ if (p_ReplicGroup->numOfEntries) -+ { -+ j = p_ReplicGroup->numOfEntries-1; -+ -+ /* manually removal of the member because there are no owners of -+ this group */ -+ for (i=j; i>=0; i--) -+ { -+ p_CurrentMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)i/*memberIndex*/); -+ ASSERT_COND(p_CurrentMember); -+ -+ if (p_CurrentMember->h_Manip) -+ { -+ FmPcdManipUpdateOwner(p_CurrentMember->h_Manip, FALSE); -+ p_CurrentMember->h_Manip = NULL; -+ } -+ -+ /* remove the member from the internal driver members list */ -+ RemoveMemberFromList(p_ReplicGroup, p_CurrentMember); -+ -+ /* return the member to the available members list */ -+ FreeMember(p_ReplicGroup, p_CurrentMember); -+ } -+ } -+ -+ /* Free members AD */ -+ for (i=0; imaxNumOfEntries; i++) -+ { -+ p_Member = GetAvailableMember(p_ReplicGroup); -+ ASSERT_COND(p_Member); -+ if (p_Member->p_MemberAd) -+ { -+ FM_MURAM_FreeMem(h_Muram, p_Member->p_MemberAd); -+ p_Member->p_MemberAd = NULL; -+ } -+ XX_Free(p_Member); -+ } -+ -+ /* release the group lock */ -+ if (p_ReplicGroup->p_Lock) -+ FmPcdReleaseLock(p_ReplicGroup->h_FmPcd, p_ReplicGroup->p_Lock); -+ -+ /* free the replicator group */ -+ XX_Free(p_ReplicGroup); -+ } -+} -+ -+ -+/*****************************************************************************/ -+/* Inter-module API routines */ -+/*****************************************************************************/ -+ -+/* NOTE: the inter-module routines are locked by cc in case of using them */ -+void * FrmReplicGroupGetSourceTableDescriptor(t_Handle h_ReplicGroup) -+{ -+ t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup; -+ ASSERT_COND(p_ReplicGroup); -+ -+ return (p_ReplicGroup->p_SourceTd); -+} -+ -+void FrmReplicGroupUpdateAd(t_Handle h_ReplicGroup, -+ void *p_Ad, -+ t_Handle *h_AdNew) -+{ -+ t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup; -+ t_AdOfTypeResult *p_AdResult = (t_AdOfTypeResult*)p_Ad; -+ t_FmPcd *p_FmPcd; -+ -+ ASSERT_COND(p_ReplicGroup); -+ p_FmPcd = p_ReplicGroup->h_FmPcd; -+ -+ /* build a bypass ad */ -+ WRITE_UINT32(p_AdResult->fqid, FM_PCD_AD_BYPASS_TYPE | -+ (uint32_t)((XX_VirtToPhys(p_ReplicGroup->p_SourceTd)) - p_FmPcd->physicalMuramBase)); -+ -+ *h_AdNew = NULL; -+} -+ -+void FrmReplicGroupUpdateOwner(t_Handle h_ReplicGroup, -+ bool add) -+{ -+ t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup; -+ ASSERT_COND(p_ReplicGroup); -+ -+ /* update the group owner counter */ -+ if (add) -+ p_ReplicGroup->owners++; -+ else -+ { -+ ASSERT_COND(p_ReplicGroup->owners); -+ p_ReplicGroup->owners--; -+ } -+} -+ -+t_Error FrmReplicGroupTryLock(t_Handle h_ReplicGroup) -+{ -+ t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup; -+ -+ ASSERT_COND(h_ReplicGroup); -+ -+ if (FmPcdLockTryLock(p_ReplicGroup->p_Lock)) -+ return E_OK; -+ -+ return ERROR_CODE(E_BUSY); -+} -+ -+void FrmReplicGroupUnlock(t_Handle h_ReplicGroup) -+{ -+ t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup; -+ -+ ASSERT_COND(h_ReplicGroup); -+ -+ FmPcdLockUnlock(p_ReplicGroup->p_Lock); -+} -+/*********************** End of inter-module routines ************************/ -+ -+ -+/****************************************/ -+/* API Init unit functions */ -+/****************************************/ -+t_Handle FM_PCD_FrmReplicSetGroup(t_Handle h_FmPcd, -+ t_FmPcdFrmReplicGroupParams *p_ReplicGroupParam) -+{ -+ t_FmPcdFrmReplicGroup *p_ReplicGroup; -+ t_FmPcdFrmReplicMember *p_CurrentMember, *p_NextMember = NULL; -+ int i; -+ t_Error err; -+ bool last = FALSE; -+ t_Handle h_Muram; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(p_ReplicGroupParam, E_INVALID_HANDLE, NULL); -+ -+ if (!FmPcdIsAdvancedOffloadSupported(h_FmPcd)) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Advanced-offload must be enabled")); -+ return NULL; -+ } -+ -+ err = CheckParams(h_FmPcd, p_ReplicGroupParam); -+ if (err) -+ { -+ REPORT_ERROR(MAJOR, err, (NO_MSG)); -+ return NULL; -+ } -+ -+ p_ReplicGroup = (t_FmPcdFrmReplicGroup*)XX_Malloc(sizeof(t_FmPcdFrmReplicGroup)); -+ if (!p_ReplicGroup) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("No memory")); -+ return NULL; -+ } -+ memset(p_ReplicGroup, 0, sizeof(t_FmPcdFrmReplicGroup)); -+ -+ /* initialize lists for internal driver use */ -+ INIT_LIST(&p_ReplicGroup->availableMembersList); -+ INIT_LIST(&p_ReplicGroup->membersList); -+ -+ p_ReplicGroup->h_FmPcd = h_FmPcd; -+ -+ h_Muram = FmPcdGetMuramHandle(p_ReplicGroup->h_FmPcd); -+ ASSERT_COND(h_Muram); -+ -+ /* initialize the group lock */ -+ p_ReplicGroup->p_Lock = FmPcdAcquireLock(p_ReplicGroup->h_FmPcd); -+ if (!p_ReplicGroup->p_Lock) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Replic group lock")); -+ DeleteGroup(p_ReplicGroup); -+ return NULL; -+ } -+ -+ /* Allocate the frame replicator source table descriptor */ -+ p_ReplicGroup->p_SourceTd = -+ (t_Handle)FM_MURAM_AllocMem(h_Muram, -+ FM_PCD_CC_AD_ENTRY_SIZE, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (!p_ReplicGroup->p_SourceTd) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("frame replicator source table descriptor")); -+ DeleteGroup(p_ReplicGroup); -+ return NULL; -+ } -+ -+ /* update the shadow size - required for the host commands */ -+ err = FmPcdUpdateCcShadow(p_ReplicGroup->h_FmPcd, -+ FM_PCD_CC_AD_ENTRY_SIZE, -+ FM_PCD_CC_AD_TABLE_ALIGN); -+ if (err) -+ { -+ REPORT_ERROR(MAJOR, err, ("Update CC shadow")); -+ DeleteGroup(p_ReplicGroup); -+ return NULL; -+ } -+ -+ p_ReplicGroup->maxNumOfEntries = p_ReplicGroupParam->maxNumOfEntries; -+ -+ /* Allocate the maximal number of members ADs and Statistics AD for the group -+ It prevents allocation of Muram in run-time */ -+ for (i=0; imaxNumOfEntries; i++) -+ { -+ err = AllocMember(p_ReplicGroup); -+ if (err) -+ { -+ REPORT_ERROR(MAJOR, err, ("allocate a new member")); -+ DeleteGroup(p_ReplicGroup); -+ return NULL; -+ } -+ } -+ -+ /* Initialize the members linked lists: -+ (hw - the one that is used by the FMan controller and -+ sw - the one that is managed by the driver internally) */ -+ for (i=(p_ReplicGroupParam->numOfEntries-1); i>=0; i--) -+ { -+ /* check if this is the last member in the group */ -+ if (i == (p_ReplicGroupParam->numOfEntries-1)) -+ last = TRUE; -+ else -+ last = FALSE; -+ -+ /* Initialize a new member */ -+ p_CurrentMember = InitMember(p_ReplicGroup, -+ &(p_ReplicGroupParam->nextEngineParams[i]), -+ last); -+ if (!p_CurrentMember) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_HANDLE, ("No available member")); -+ DeleteGroup(p_ReplicGroup); -+ return NULL; -+ } -+ -+ /* Build the members group - link two consecutive members in the hw linked list */ -+ LinkMemberToMember(p_ReplicGroup, p_CurrentMember, p_NextMember); -+ -+ /* update the driver internal members list to be compatible to the hw members linked list */ -+ AddMemberToList(p_ReplicGroup, p_CurrentMember, &p_ReplicGroup->membersList); -+ -+ p_NextMember = p_CurrentMember; -+ } -+ -+ /* initialize the source table descriptor */ -+ BuildSourceTd(p_ReplicGroup->p_SourceTd); -+ -+ /* link the source table descriptor to point to the first member in the group */ -+ LinkSourceToMember(p_ReplicGroup, p_ReplicGroup->p_SourceTd, p_NextMember); -+ -+ return p_ReplicGroup; -+} -+ -+t_Error FM_PCD_FrmReplicDeleteGroup(t_Handle h_ReplicGroup) -+{ -+ t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup; -+ -+ SANITY_CHECK_RETURN_ERROR(p_ReplicGroup, E_INVALID_HANDLE); -+ -+ if (p_ReplicGroup->owners) -+ RETURN_ERROR(MAJOR, -+ E_INVALID_STATE, -+ ("the group has owners and can't be deleted")); -+ -+ DeleteGroup(p_ReplicGroup); -+ -+ return E_OK; -+} -+ -+ -+/*****************************************************************************/ -+/* API Run-time Frame replicator Control unit functions */ -+/*****************************************************************************/ -+t_Error FM_PCD_FrmReplicAddMember(t_Handle h_ReplicGroup, -+ uint16_t memberIndex, -+ t_FmPcdCcNextEngineParams *p_MemberParams) -+{ -+ t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup*) h_ReplicGroup; -+ t_FmPcdFrmReplicMember *p_NewMember, *p_CurrentMember = NULL, *p_PreviousMember = NULL; -+ t_Error err; -+ uint8_t memberPosition; -+ -+ SANITY_CHECK_RETURN_ERROR(p_ReplicGroup, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_MemberParams, E_INVALID_HANDLE); -+ -+ /* group lock */ -+ err = FrmReplicGroupTryLock(p_ReplicGroup); -+ if (GET_ERROR_TYPE(err) == E_BUSY) -+ return ERROR_CODE(E_BUSY); -+ -+ if (memberIndex > p_ReplicGroup->numOfEntries) -+ { -+ /* unlock */ -+ FrmReplicGroupUnlock(p_ReplicGroup); -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, -+ ("memberIndex is greater than the members in the list")); -+ } -+ -+ if (memberIndex >= p_ReplicGroup->maxNumOfEntries) -+ { -+ /* unlock */ -+ FrmReplicGroupUnlock(p_ReplicGroup); -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("memberIndex is greater than the allowed number of members in the group")); -+ } -+ -+ if ((p_ReplicGroup->numOfEntries + 1) > FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES) -+ { -+ /* unlock */ -+ FrmReplicGroupUnlock(p_ReplicGroup); -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("numOfEntries with new entry can not be larger than %d\n", -+ FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES)); -+ } -+ -+ err = MemberCheckParams(p_ReplicGroup->h_FmPcd, p_MemberParams); -+ if (err) -+ { -+ /* unlock */ -+ FrmReplicGroupUnlock(p_ReplicGroup); -+ RETURN_ERROR(MAJOR, err, ("member check parameters in add operation")); -+ } -+ /* determine the member position in the group */ -+ memberPosition = GetMemberPosition(p_ReplicGroup, -+ memberIndex, -+ TRUE/* add operation */); -+ -+ /* Initialize a new member */ -+ p_NewMember = InitMember(p_ReplicGroup, -+ p_MemberParams, -+ (memberPosition == FRM_REPLIC_LAST_MEMBER_INDEX ? TRUE : FALSE)); -+ if (!p_NewMember) -+ { -+ /* unlock */ -+ FrmReplicGroupUnlock(p_ReplicGroup); -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("No available member")); -+ } -+ -+ switch (memberPosition) -+ { -+ case FRM_REPLIC_FIRST_MEMBER_INDEX: -+ p_CurrentMember = GetMemberByIndex(p_ReplicGroup, memberIndex); -+ ASSERT_COND(p_CurrentMember); -+ -+ LinkMemberToMember(p_ReplicGroup, p_NewMember, p_CurrentMember); -+ -+ /* update the internal group source TD */ -+ LinkSourceToMember(p_ReplicGroup, -+ p_ReplicGroup->p_SourceTd, -+ p_NewMember); -+ -+ /* add member to the internal sw member list */ -+ AddMemberToList(p_ReplicGroup, -+ p_NewMember, -+ &p_ReplicGroup->membersList); -+ break; -+ -+ case FRM_REPLIC_MIDDLE_MEMBER_INDEX: -+ p_CurrentMember = GetMemberByIndex(p_ReplicGroup, memberIndex); -+ ASSERT_COND(p_CurrentMember); -+ -+ p_PreviousMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex-1)); -+ ASSERT_COND(p_PreviousMember); -+ -+ LinkMemberToMember(p_ReplicGroup, p_NewMember, p_CurrentMember); -+ LinkMemberToMember(p_ReplicGroup, p_PreviousMember, p_NewMember); -+ -+ AddMemberToList(p_ReplicGroup, p_NewMember, &p_PreviousMember->node); -+ break; -+ -+ case FRM_REPLIC_LAST_MEMBER_INDEX: -+ p_PreviousMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex-1)); -+ ASSERT_COND(p_PreviousMember); -+ -+ LinkMemberToMember(p_ReplicGroup, p_PreviousMember, p_NewMember); -+ FillReplicAdOfTypeResult(p_PreviousMember->p_MemberAd, FALSE/*last*/); -+ -+ /* add the new member to the internal sw member list */ -+ AddMemberToList(p_ReplicGroup, p_NewMember, &p_PreviousMember->node); -+ break; -+ -+ default: -+ /* unlock */ -+ FrmReplicGroupUnlock(p_ReplicGroup); -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("member position in add member")); -+ -+ } -+ -+ /* unlock */ -+ FrmReplicGroupUnlock(p_ReplicGroup); -+ -+ return E_OK; -+} -+ -+t_Error FM_PCD_FrmReplicRemoveMember(t_Handle h_ReplicGroup, -+ uint16_t memberIndex) -+{ -+ t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup*) h_ReplicGroup; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_ReplicGroup, E_INVALID_HANDLE); -+ -+ /* lock */ -+ err = FrmReplicGroupTryLock(p_ReplicGroup); -+ if (GET_ERROR_TYPE(err) == E_BUSY) -+ return ERROR_CODE(E_BUSY); -+ -+ if (memberIndex >= p_ReplicGroup->numOfEntries) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("member index to remove")); -+ -+ /* Design decision: group must contain at least one member -+ No possibility to remove the last member from the group */ -+ if (p_ReplicGroup->numOfEntries == 1) -+ RETURN_ERROR(MAJOR, E_CONFLICT, ("Can't remove the last member. At least one member should be related to a group.")); -+ -+ err = RemoveMember(p_ReplicGroup, memberIndex); -+ -+ /* unlock */ -+ FrmReplicGroupUnlock(p_ReplicGroup); -+ -+ switch (GET_ERROR_TYPE(err)) -+ { -+ case E_OK: -+ return E_OK; -+ -+ case E_BUSY: -+ DBG(TRACE, ("E_BUSY error")); -+ return ERROR_CODE(E_BUSY); -+ -+ default: -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+} -+ -+/*********************** End of API routines ************************/ -+ -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_replic.h -@@ -0,0 +1,101 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_replic.h -+ -+ @Description FM frame replicator -+*//***************************************************************************/ -+#ifndef __FM_REPLIC_H -+#define __FM_REPLIC_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+ -+ -+#define FRM_REPLIC_SOURCE_TD_OPCODE 0x75 -+#define NEXT_FRM_REPLIC_ADDR_SHIFT 4 -+#define NEXT_FRM_REPLIC_MEMBER_INDEX_SHIFT 16 -+#define FRM_REPLIC_FR_BIT 0x08000000 -+#define FRM_REPLIC_NL_BIT 0x10000000 -+#define FRM_REPLIC_INVALID_MEMBER_INDEX 0xffff -+#define FRM_REPLIC_FIRST_MEMBER_INDEX 0 -+ -+#define FRM_REPLIC_MIDDLE_MEMBER_INDEX 1 -+#define FRM_REPLIC_LAST_MEMBER_INDEX 2 -+ -+#define SOURCE_TD_ITSELF_OPTION 0x01 -+#define SOURCE_TD_COPY_OPTION 0x02 -+#define SOURCE_TD_ITSELF_AND_COPY_OPTION SOURCE_TD_ITSELF_OPTION | SOURCE_TD_COPY_OPTION -+#define SOURCE_TD_NONE 0x04 -+ -+/*typedef enum e_SourceTdOption -+{ -+ e_SOURCE_TD_NONE = 0, -+ e_SOURCE_TD_ITSELF_OPTION = 1, -+ e_SOURCE_TD_COPY_OPTION = 2, -+ e_SOURCE_TD_ITSELF_AND_COPY_OPTION = e_SOURCE_TD_ITSELF_OPTION | e_SOURCE_TD_COPY_OPTION -+} e_SourceTdOption; -+*/ -+ -+typedef struct -+{ -+ volatile uint32_t type; -+ volatile uint32_t frGroupPointer; -+ volatile uint32_t operationCode; -+ volatile uint32_t reserved; -+} t_FrmReplicGroupSourceAd; -+ -+typedef struct t_FmPcdFrmReplicMember -+{ -+ void *p_MemberAd; /**< pointer to the member AD */ -+ void *p_StatisticsAd;/**< pointer to the statistics AD of the member */ -+ t_Handle h_Manip; /**< manip handle - need for free routines */ -+ t_List node; -+} t_FmPcdFrmReplicMember; -+ -+typedef struct t_FmPcdFrmReplicGroup -+{ -+ t_Handle h_FmPcd; -+ -+ uint8_t maxNumOfEntries;/**< maximal number of members in the group */ -+ uint8_t numOfEntries; /**< actual number of members in the group */ -+ uint16_t owners; /**< how many keys share this frame replicator group */ -+ void *p_SourceTd; /**< pointer to the frame replicator source table descriptor */ -+ t_List membersList; /**< the members list - should reflect the order of the members as in the hw linked list*/ -+ t_List availableMembersList;/**< list of all the available members in the group */ -+ t_FmPcdLock *p_Lock; -+} t_FmPcdFrmReplicGroup; -+ -+ -+#endif /* __FM_REPLIC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fman_kg.c -@@ -0,0 +1,888 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "fsl_fman_kg.h" -+ -+/****************************************/ -+/* static functions */ -+/****************************************/ -+ -+ -+static uint32_t build_ar_bind_scheme(uint8_t hwport_id, bool write) -+{ -+ uint32_t rw; -+ -+ rw = write ? (uint32_t)FM_KG_KGAR_WRITE : (uint32_t)FM_KG_KGAR_READ; -+ -+ return (uint32_t)(FM_KG_KGAR_GO | -+ rw | -+ FM_PCD_KG_KGAR_SEL_PORT_ENTRY | -+ hwport_id | -+ FM_PCD_KG_KGAR_SEL_PORT_WSEL_SP); -+} -+ -+static void clear_pe_all_scheme(struct fman_kg_regs *regs, uint8_t hwport_id) -+{ -+ uint32_t ar; -+ -+ fman_kg_write_sp(regs, 0xffffffff, 0); -+ -+ ar = build_ar_bind_scheme(hwport_id, TRUE); -+ fman_kg_write_ar_wait(regs, ar); -+} -+ -+static uint32_t build_ar_bind_cls_plan(uint8_t hwport_id, bool write) -+{ -+ uint32_t rw; -+ -+ rw = write ? (uint32_t)FM_KG_KGAR_WRITE : (uint32_t)FM_KG_KGAR_READ; -+ -+ return (uint32_t)(FM_KG_KGAR_GO | -+ rw | -+ FM_PCD_KG_KGAR_SEL_PORT_ENTRY | -+ hwport_id | -+ FM_PCD_KG_KGAR_SEL_PORT_WSEL_CPP); -+} -+ -+static void clear_pe_all_cls_plan(struct fman_kg_regs *regs, uint8_t hwport_id) -+{ -+ uint32_t ar; -+ -+ fman_kg_write_cpp(regs, 0); -+ -+ ar = build_ar_bind_cls_plan(hwport_id, TRUE); -+ fman_kg_write_ar_wait(regs, ar); -+} -+ -+static uint8_t get_gen_ht_code(enum fman_kg_gen_extract_src src, -+ bool no_validation, -+ uint8_t *offset) -+{ -+ int code; -+ -+ switch (src) { -+ case E_FMAN_KG_GEN_EXTRACT_ETH: -+ code = no_validation ? 0x73 : 0x3; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_ETYPE: -+ code = no_validation ? 0x77 : 0x7; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_SNAP: -+ code = no_validation ? 0x74 : 0x4; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_VLAN_TCI_1: -+ code = no_validation ? 0x75 : 0x5; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_VLAN_TCI_N: -+ code = no_validation ? 0x76 : 0x6; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_PPPoE: -+ code = no_validation ? 0x78 : 0x8; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_MPLS_1: -+ code = no_validation ? 0x79 : 0x9; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_MPLS_2: -+ code = no_validation ? FM_KG_SCH_GEN_HT_INVALID : 0x19; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_MPLS_3: -+ code = no_validation ? FM_KG_SCH_GEN_HT_INVALID : 0x29; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_MPLS_N: -+ code = no_validation ? 0x7a : 0xa; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_IPv4_1: -+ code = no_validation ? 0x7b : 0xb; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_IPv6_1: -+ code = no_validation ? 0x7b : 0x1b; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_IPv4_2: -+ code = no_validation ? 0x7c : 0xc; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_IPv6_2: -+ code = no_validation ? 0x7c : 0x1c; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_MINENCAP: -+ code = no_validation ? 0x7c : 0x2c; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_IP_PID: -+ code = no_validation ? 0x72 : 0x2; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_GRE: -+ code = no_validation ? 0x7d : 0xd; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_TCP: -+ code = no_validation ? 0x7e : 0xe; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_UDP: -+ code = no_validation ? 0x7e : 0x1e; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_SCTP: -+ code = no_validation ? 0x7e : 0x3e; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_DCCP: -+ code = no_validation ? 0x7e : 0x4e; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_IPSEC_AH: -+ code = no_validation ? 0x7e : 0x2e; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_IPSEC_ESP: -+ code = no_validation ? 0x7e : 0x6e; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_SHIM_1: -+ code = 0x70; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_SHIM_2: -+ code = 0x71; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_FROM_DFLT: -+ code = 0x10; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_FROM_FRAME_START: -+ code = 0x40; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_FROM_PARSE_RESULT: -+ code = 0x20; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_FROM_END_OF_PARSE: -+ code = 0x7f; -+ break; -+ -+ case E_FMAN_KG_GEN_EXTRACT_FROM_FQID: -+ code = 0x20; -+ *offset += 0x20; -+ break; -+ -+ default: -+ code = FM_KG_SCH_GEN_HT_INVALID; -+ } -+ -+ return (uint8_t)code; -+} -+ -+static uint32_t build_ar_scheme(uint8_t scheme, -+ uint8_t hwport_id, -+ bool update_counter, -+ bool write) -+{ -+ uint32_t rw; -+ -+ rw = (uint32_t)(write ? FM_KG_KGAR_WRITE : FM_KG_KGAR_READ); -+ -+ return (uint32_t)(FM_KG_KGAR_GO | -+ rw | -+ FM_KG_KGAR_SEL_SCHEME_ENTRY | -+ hwport_id | -+ ((uint32_t)scheme << FM_KG_KGAR_NUM_SHIFT) | -+ (update_counter ? FM_KG_KGAR_SCM_WSEL_UPDATE_CNT : 0)); -+} -+ -+static uint32_t build_ar_cls_plan(uint8_t grp, -+ uint8_t entries_mask, -+ uint8_t hwport_id, -+ bool write) -+{ -+ uint32_t rw; -+ -+ rw = (uint32_t)(write ? FM_KG_KGAR_WRITE : FM_KG_KGAR_READ); -+ -+ return (uint32_t)(FM_KG_KGAR_GO | -+ rw | -+ FM_PCD_KG_KGAR_SEL_CLS_PLAN_ENTRY | -+ hwport_id | -+ ((uint32_t)grp << FM_KG_KGAR_NUM_SHIFT) | -+ ((uint32_t)entries_mask << FM_KG_KGAR_WSEL_SHIFT)); -+} -+ -+int fman_kg_write_ar_wait(struct fman_kg_regs *regs, uint32_t fmkg_ar) -+{ -+ iowrite32be(fmkg_ar, ®s->fmkg_ar); -+ /* Wait for GO to be idle and read error */ -+ while ((fmkg_ar = ioread32be(®s->fmkg_ar)) & FM_KG_KGAR_GO) ; -+ if (fmkg_ar & FM_PCD_KG_KGAR_ERR) -+ return -EINVAL; -+ return 0; -+} -+ -+void fman_kg_write_sp(struct fman_kg_regs *regs, uint32_t sp, bool add) -+{ -+ -+ struct fman_kg_pe_regs *kgpe_regs; -+ uint32_t tmp; -+ -+ kgpe_regs = (struct fman_kg_pe_regs *)&(regs->fmkg_indirect[0]); -+ tmp = ioread32be(&kgpe_regs->fmkg_pe_sp); -+ -+ if (add) -+ tmp |= sp; -+ else /* clear */ -+ tmp &= ~sp; -+ -+ iowrite32be(tmp, &kgpe_regs->fmkg_pe_sp); -+ -+} -+ -+void fman_kg_write_cpp(struct fman_kg_regs *regs, uint32_t cpp) -+{ -+ struct fman_kg_pe_regs *kgpe_regs; -+ -+ kgpe_regs = (struct fman_kg_pe_regs *)&(regs->fmkg_indirect[0]); -+ -+ iowrite32be(cpp, &kgpe_regs->fmkg_pe_cpp); -+} -+ -+void fman_kg_get_event(struct fman_kg_regs *regs, -+ uint32_t *event, -+ uint32_t *scheme_idx) -+{ -+ uint32_t mask, force; -+ -+ *event = ioread32be(®s->fmkg_eer); -+ mask = ioread32be(®s->fmkg_eeer); -+ *scheme_idx = ioread32be(®s->fmkg_seer); -+ *scheme_idx &= ioread32be(®s->fmkg_seeer); -+ -+ *event &= mask; -+ -+ /* clear the forced events */ -+ force = ioread32be(®s->fmkg_feer); -+ if (force & *event) -+ iowrite32be(force & ~*event ,®s->fmkg_feer); -+ -+ iowrite32be(*event, ®s->fmkg_eer); -+ iowrite32be(*scheme_idx, ®s->fmkg_seer); -+} -+ -+ -+void fman_kg_init(struct fman_kg_regs *regs, -+ uint32_t exceptions, -+ uint32_t dflt_nia) -+{ -+ uint32_t tmp; -+ int i; -+ -+ iowrite32be(FM_EX_KG_DOUBLE_ECC | FM_EX_KG_KEYSIZE_OVERFLOW, -+ ®s->fmkg_eer); -+ -+ tmp = 0; -+ if (exceptions & FM_EX_KG_DOUBLE_ECC) -+ tmp |= FM_EX_KG_DOUBLE_ECC; -+ -+ if (exceptions & FM_EX_KG_KEYSIZE_OVERFLOW) -+ tmp |= FM_EX_KG_KEYSIZE_OVERFLOW; -+ -+ iowrite32be(tmp, ®s->fmkg_eeer); -+ iowrite32be(0, ®s->fmkg_fdor); -+ iowrite32be(0, ®s->fmkg_gdv0r); -+ iowrite32be(0, ®s->fmkg_gdv1r); -+ iowrite32be(dflt_nia, ®s->fmkg_gcr); -+ -+ /* Clear binding between ports to schemes and classification plans -+ * so that all ports are not bound to any scheme/classification plan */ -+ for (i = 0; i < FMAN_MAX_NUM_OF_HW_PORTS; i++) { -+ clear_pe_all_scheme(regs, (uint8_t)i); -+ clear_pe_all_cls_plan(regs, (uint8_t)i); -+ } -+} -+ -+void fman_kg_enable_scheme_interrupts(struct fman_kg_regs *regs) -+{ -+ /* enable and enable all scheme interrupts */ -+ iowrite32be(0xFFFFFFFF, ®s->fmkg_seer); -+ iowrite32be(0xFFFFFFFF, ®s->fmkg_seeer); -+} -+ -+void fman_kg_enable(struct fman_kg_regs *regs) -+{ -+ iowrite32be(ioread32be(®s->fmkg_gcr) | FM_KG_KGGCR_EN, -+ ®s->fmkg_gcr); -+} -+ -+void fman_kg_disable(struct fman_kg_regs *regs) -+{ -+ iowrite32be(ioread32be(®s->fmkg_gcr) & ~FM_KG_KGGCR_EN, -+ ®s->fmkg_gcr); -+} -+ -+void fman_kg_set_data_after_prs(struct fman_kg_regs *regs, uint8_t offset) -+{ -+ iowrite32be(offset, ®s->fmkg_fdor); -+} -+ -+void fman_kg_set_dflt_val(struct fman_kg_regs *regs, -+ uint8_t def_id, -+ uint32_t val) -+{ -+ if(def_id == 0) -+ iowrite32be(val, ®s->fmkg_gdv0r); -+ else -+ iowrite32be(val, ®s->fmkg_gdv1r); -+} -+ -+ -+void fman_kg_set_exception(struct fman_kg_regs *regs, -+ uint32_t exception, -+ bool enable) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->fmkg_eeer); -+ -+ if (enable) { -+ tmp |= exception; -+ } else { -+ tmp &= ~exception; -+ } -+ -+ iowrite32be(tmp, ®s->fmkg_eeer); -+} -+ -+void fman_kg_get_exception(struct fman_kg_regs *regs, -+ uint32_t *events, -+ uint32_t *scheme_ids, -+ bool clear) -+{ -+ uint32_t mask; -+ -+ *events = ioread32be(®s->fmkg_eer); -+ mask = ioread32be(®s->fmkg_eeer); -+ *events &= mask; -+ -+ *scheme_ids = 0; -+ -+ if (*events & FM_EX_KG_KEYSIZE_OVERFLOW) { -+ *scheme_ids = ioread32be(®s->fmkg_seer); -+ mask = ioread32be(®s->fmkg_seeer); -+ *scheme_ids &= mask; -+ } -+ -+ if (clear) { -+ iowrite32be(*scheme_ids, ®s->fmkg_seer); -+ iowrite32be(*events, ®s->fmkg_eer); -+ } -+} -+ -+void fman_kg_get_capture(struct fman_kg_regs *regs, -+ struct fman_kg_ex_ecc_attr *ecc_attr, -+ bool clear) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->fmkg_serc); -+ -+ if (tmp & KG_FMKG_SERC_CAP) { -+ /* Captured data is valid */ -+ ecc_attr->valid = TRUE; -+ ecc_attr->double_ecc = -+ (bool)((tmp & KG_FMKG_SERC_CET) ? TRUE : FALSE); -+ ecc_attr->single_ecc_count = -+ (uint8_t)((tmp & KG_FMKG_SERC_CNT_MSK) >> -+ KG_FMKG_SERC_CNT_SHIFT); -+ ecc_attr->addr = (uint16_t)(tmp & KG_FMKG_SERC_ADDR_MSK); -+ -+ if (clear) -+ iowrite32be(KG_FMKG_SERC_CAP, ®s->fmkg_serc); -+ } else { -+ /* No ECC error is captured */ -+ ecc_attr->valid = FALSE; -+ } -+} -+ -+int fman_kg_build_scheme(struct fman_kg_scheme_params *params, -+ struct fman_kg_scheme_regs *scheme_regs) -+{ -+ struct fman_kg_extract_params *extract_params; -+ struct fman_kg_gen_extract_params *gen_params; -+ uint32_t tmp_reg, i, select, mask, fqb; -+ uint8_t offset, shift, ht; -+ -+ /* Zero out all registers so no need to care about unused ones */ -+ memset(scheme_regs, 0, sizeof(struct fman_kg_scheme_regs)); -+ -+ /* Mode register */ -+ tmp_reg = fm_kg_build_nia(params->next_engine, -+ params->next_engine_action); -+ if (tmp_reg == KG_NIA_INVALID) { -+ return -EINVAL; -+ } -+ -+ if (params->next_engine == E_FMAN_PCD_PLCR) { -+ tmp_reg |= FMAN_KG_SCH_MODE_NIA_PLCR; -+ } -+ else if (params->next_engine == E_FMAN_PCD_CC) { -+ tmp_reg |= (uint32_t)params->cc_params.base_offset << -+ FMAN_KG_SCH_MODE_CCOBASE_SHIFT; -+ } -+ -+ tmp_reg |= FMAN_KG_SCH_MODE_EN; -+ scheme_regs->kgse_mode = tmp_reg; -+ -+ /* Match vector */ -+ scheme_regs->kgse_mv = params->match_vector; -+ -+ extract_params = ¶ms->extract_params; -+ -+ /* Scheme default values registers */ -+ scheme_regs->kgse_dv0 = extract_params->def_scheme_0; -+ scheme_regs->kgse_dv1 = extract_params->def_scheme_1; -+ -+ /* Extract Known Fields Command register */ -+ scheme_regs->kgse_ekfc = extract_params->known_fields; -+ -+ /* Entry Extract Known Default Value register */ -+ tmp_reg = 0; -+ tmp_reg |= extract_params->known_fields_def.mac_addr << -+ FMAN_KG_SCH_DEF_MAC_ADDR_SHIFT; -+ tmp_reg |= extract_params->known_fields_def.vlan_tci << -+ FMAN_KG_SCH_DEF_VLAN_TCI_SHIFT; -+ tmp_reg |= extract_params->known_fields_def.etype << -+ FMAN_KG_SCH_DEF_ETYPE_SHIFT; -+ tmp_reg |= extract_params->known_fields_def.ppp_sid << -+ FMAN_KG_SCH_DEF_PPP_SID_SHIFT; -+ tmp_reg |= extract_params->known_fields_def.ppp_pid << -+ FMAN_KG_SCH_DEF_PPP_PID_SHIFT; -+ tmp_reg |= extract_params->known_fields_def.mpls << -+ FMAN_KG_SCH_DEF_MPLS_SHIFT; -+ tmp_reg |= extract_params->known_fields_def.ip_addr << -+ FMAN_KG_SCH_DEF_IP_ADDR_SHIFT; -+ tmp_reg |= extract_params->known_fields_def.ptype << -+ FMAN_KG_SCH_DEF_PTYPE_SHIFT; -+ tmp_reg |= extract_params->known_fields_def.ip_tos_tc << -+ FMAN_KG_SCH_DEF_IP_TOS_TC_SHIFT; -+ tmp_reg |= extract_params->known_fields_def.ipv6_fl << -+ FMAN_KG_SCH_DEF_IPv6_FL_SHIFT; -+ tmp_reg |= extract_params->known_fields_def.ipsec_spi << -+ FMAN_KG_SCH_DEF_IPSEC_SPI_SHIFT; -+ tmp_reg |= extract_params->known_fields_def.l4_port << -+ FMAN_KG_SCH_DEF_L4_PORT_SHIFT; -+ tmp_reg |= extract_params->known_fields_def.tcp_flg << -+ FMAN_KG_SCH_DEF_TCP_FLG_SHIFT; -+ -+ scheme_regs->kgse_ekdv = tmp_reg; -+ -+ /* Generic extract registers */ -+ if (extract_params->gen_extract_num > FM_KG_NUM_OF_GENERIC_REGS) { -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < extract_params->gen_extract_num; i++) { -+ gen_params = extract_params->gen_extract + i; -+ -+ tmp_reg = FMAN_KG_SCH_GEN_VALID; -+ tmp_reg |= (uint32_t)gen_params->def_val << -+ FMAN_KG_SCH_GEN_DEF_SHIFT; -+ -+ if (gen_params->type == E_FMAN_KG_HASH_EXTRACT) { -+ if ((gen_params->extract > FMAN_KG_SCH_GEN_SIZE_MAX) || -+ (gen_params->extract == 0)) { -+ return -EINVAL; -+ } -+ } else { -+ tmp_reg |= FMAN_KG_SCH_GEN_OR; -+ } -+ -+ tmp_reg |= (uint32_t)gen_params->extract << -+ FMAN_KG_SCH_GEN_SIZE_SHIFT; -+ tmp_reg |= (uint32_t)gen_params->mask << -+ FMAN_KG_SCH_GEN_MASK_SHIFT; -+ -+ offset = gen_params->offset; -+ ht = get_gen_ht_code(gen_params->src, -+ gen_params->no_validation, -+ &offset); -+ tmp_reg |= (uint32_t)ht << FMAN_KG_SCH_GEN_HT_SHIFT; -+ tmp_reg |= offset; -+ -+ scheme_regs->kgse_gec[i] = tmp_reg; -+ } -+ -+ /* Masks registers */ -+ if (extract_params->masks_num > FM_KG_EXTRACT_MASKS_NUM) { -+ return -EINVAL; -+ } -+ -+ select = 0; -+ mask = 0; -+ fqb = 0; -+ for (i = 0; i < extract_params->masks_num; i++) { -+ /* MCSx fields */ -+ KG_GET_MASK_SEL_SHIFT(shift, i); -+ if (extract_params->masks[i].is_known) { -+ /* Mask known field */ -+ select |= extract_params->masks[i].field_or_gen_idx << -+ shift; -+ } else { -+ /* Mask generic extract */ -+ select |= (extract_params->masks[i].field_or_gen_idx + -+ FM_KG_MASK_SEL_GEN_BASE) << shift; -+ } -+ -+ /* MOx fields - spread between se_bmch and se_fqb registers */ -+ KG_GET_MASK_OFFSET_SHIFT(shift, i); -+ if (i < 2) { -+ select |= (uint32_t)extract_params->masks[i].offset << -+ shift; -+ } else { -+ fqb |= (uint32_t)extract_params->masks[i].offset << -+ shift; -+ } -+ -+ /* BMx fields */ -+ KG_GET_MASK_SHIFT(shift, i); -+ mask |= (uint32_t)extract_params->masks[i].mask << shift; -+ } -+ -+ /* Finish with rest of BMx fileds - -+ * don't mask bits for unused masks by setting -+ * corresponding BMx field = 0xFF */ -+ for (i = extract_params->masks_num; i < FM_KG_EXTRACT_MASKS_NUM; i++) { -+ KG_GET_MASK_SHIFT(shift, i); -+ mask |= 0xFF << shift; -+ } -+ -+ scheme_regs->kgse_bmch = select; -+ scheme_regs->kgse_bmcl = mask; -+ -+ /* Finish with FQB register initialization. -+ * Check fqid is 24-bit value. */ -+ if (params->base_fqid & ~0x00FFFFFF) { -+ return -EINVAL; -+ } -+ -+ fqb |= params->base_fqid; -+ scheme_regs->kgse_fqb = fqb; -+ -+ /* Hash Configuration register */ -+ tmp_reg = 0; -+ if (params->hash_params.use_hash) { -+ /* Check hash mask is 24-bit value */ -+ if (params->hash_params.mask & ~0x00FFFFFF) { -+ return -EINVAL; -+ } -+ -+ /* Hash function produces 64-bit value, 24 bits of that -+ * are used to generate fq_id and policer profile. -+ * Thus, maximal shift is 40 bits to allow 24 bits out of 64. -+ */ -+ if (params->hash_params.shift_r > FMAN_KG_SCH_HASH_HSHIFT_MAX) { -+ return -EINVAL; -+ } -+ -+ tmp_reg |= params->hash_params.mask; -+ tmp_reg |= (uint32_t)params->hash_params.shift_r << -+ FMAN_KG_SCH_HASH_HSHIFT_SHIFT; -+ -+ if (params->hash_params.sym) { -+ tmp_reg |= FMAN_KG_SCH_HASH_SYM; -+ } -+ -+ } -+ -+ if (params->bypass_fqid_gen) { -+ tmp_reg |= FMAN_KG_SCH_HASH_NO_FQID_GEN; -+ } -+ -+ scheme_regs->kgse_hc = tmp_reg; -+ -+ /* Policer Profile register */ -+ if (params->policer_params.bypass_pp_gen) { -+ tmp_reg = 0; -+ } else { -+ /* Lower 8 bits of 24-bits extracted from hash result -+ * are used for policer profile generation. -+ * That leaves maximum shift value = 23. */ -+ if (params->policer_params.shift > FMAN_KG_SCH_PP_SHIFT_MAX) { -+ return -EINVAL; -+ } -+ -+ tmp_reg = params->policer_params.base; -+ tmp_reg |= ((uint32_t)params->policer_params.shift << -+ FMAN_KG_SCH_PP_SH_SHIFT) & -+ FMAN_KG_SCH_PP_SH_MASK; -+ tmp_reg |= ((uint32_t)params->policer_params.shift << -+ FMAN_KG_SCH_PP_SL_SHIFT) & -+ FMAN_KG_SCH_PP_SL_MASK; -+ tmp_reg |= (uint32_t)params->policer_params.mask << -+ FMAN_KG_SCH_PP_MASK_SHIFT; -+ } -+ -+ scheme_regs->kgse_ppc = tmp_reg; -+ -+ /* Coarse Classification Bit Select register */ -+ if (params->next_engine == E_FMAN_PCD_CC) { -+ scheme_regs->kgse_ccbs = params->cc_params.qlcv_bits_sel; -+ } -+ -+ /* Packets Counter register */ -+ if (params->update_counter) { -+ scheme_regs->kgse_spc = params->counter_value; -+ } -+ -+ return 0; -+} -+ -+int fman_kg_write_scheme(struct fman_kg_regs *regs, -+ uint8_t scheme_id, -+ uint8_t hwport_id, -+ struct fman_kg_scheme_regs *scheme_regs, -+ bool update_counter) -+{ -+ struct fman_kg_scheme_regs *kgse_regs; -+ uint32_t tmp_reg; -+ int err, i; -+ -+ /* Write indirect scheme registers */ -+ kgse_regs = (struct fman_kg_scheme_regs *)&(regs->fmkg_indirect[0]); -+ -+ iowrite32be(scheme_regs->kgse_mode, &kgse_regs->kgse_mode); -+ iowrite32be(scheme_regs->kgse_ekfc, &kgse_regs->kgse_ekfc); -+ iowrite32be(scheme_regs->kgse_ekdv, &kgse_regs->kgse_ekdv); -+ iowrite32be(scheme_regs->kgse_bmch, &kgse_regs->kgse_bmch); -+ iowrite32be(scheme_regs->kgse_bmcl, &kgse_regs->kgse_bmcl); -+ iowrite32be(scheme_regs->kgse_fqb, &kgse_regs->kgse_fqb); -+ iowrite32be(scheme_regs->kgse_hc, &kgse_regs->kgse_hc); -+ iowrite32be(scheme_regs->kgse_ppc, &kgse_regs->kgse_ppc); -+ iowrite32be(scheme_regs->kgse_spc, &kgse_regs->kgse_spc); -+ iowrite32be(scheme_regs->kgse_dv0, &kgse_regs->kgse_dv0); -+ iowrite32be(scheme_regs->kgse_dv1, &kgse_regs->kgse_dv1); -+ iowrite32be(scheme_regs->kgse_ccbs, &kgse_regs->kgse_ccbs); -+ iowrite32be(scheme_regs->kgse_mv, &kgse_regs->kgse_mv); -+ -+ for (i = 0 ; i < FM_KG_NUM_OF_GENERIC_REGS ; i++) -+ iowrite32be(scheme_regs->kgse_gec[i], &kgse_regs->kgse_gec[i]); -+ -+ /* Write AR (Action register) */ -+ tmp_reg = build_ar_scheme(scheme_id, hwport_id, update_counter, TRUE); -+ err = fman_kg_write_ar_wait(regs, tmp_reg); -+ return err; -+} -+ -+int fman_kg_delete_scheme(struct fman_kg_regs *regs, -+ uint8_t scheme_id, -+ uint8_t hwport_id) -+{ -+ struct fman_kg_scheme_regs *kgse_regs; -+ uint32_t tmp_reg; -+ int err, i; -+ -+ kgse_regs = (struct fman_kg_scheme_regs *)&(regs->fmkg_indirect[0]); -+ -+ /* Clear all registers including enable bit in mode register */ -+ for (i = 0; i < (sizeof(struct fman_kg_scheme_regs)) / 4; ++i) { -+ iowrite32be(0, ((uint32_t *)kgse_regs + i)); -+ } -+ -+ /* Write AR (Action register) */ -+ tmp_reg = build_ar_scheme(scheme_id, hwport_id, FALSE, TRUE); -+ err = fman_kg_write_ar_wait(regs, tmp_reg); -+ return err; -+} -+ -+int fman_kg_get_scheme_counter(struct fman_kg_regs *regs, -+ uint8_t scheme_id, -+ uint8_t hwport_id, -+ uint32_t *counter) -+{ -+ struct fman_kg_scheme_regs *kgse_regs; -+ uint32_t tmp_reg; -+ int err; -+ -+ kgse_regs = (struct fman_kg_scheme_regs *)&(regs->fmkg_indirect[0]); -+ -+ tmp_reg = build_ar_scheme(scheme_id, hwport_id, TRUE, FALSE); -+ err = fman_kg_write_ar_wait(regs, tmp_reg); -+ -+ if (err != 0) -+ return err; -+ -+ *counter = ioread32be(&kgse_regs->kgse_spc); -+ -+ return 0; -+} -+ -+int fman_kg_set_scheme_counter(struct fman_kg_regs *regs, -+ uint8_t scheme_id, -+ uint8_t hwport_id, -+ uint32_t counter) -+{ -+ struct fman_kg_scheme_regs *kgse_regs; -+ uint32_t tmp_reg; -+ int err; -+ -+ kgse_regs = (struct fman_kg_scheme_regs *)&(regs->fmkg_indirect[0]); -+ -+ tmp_reg = build_ar_scheme(scheme_id, hwport_id, TRUE, FALSE); -+ -+ err = fman_kg_write_ar_wait(regs, tmp_reg); -+ if (err != 0) -+ return err; -+ -+ /* Keygen indirect access memory contains all scheme_id registers -+ * by now. Change only counter value. */ -+ iowrite32be(counter, &kgse_regs->kgse_spc); -+ -+ /* Write back scheme registers */ -+ tmp_reg = build_ar_scheme(scheme_id, hwport_id, TRUE, TRUE); -+ err = fman_kg_write_ar_wait(regs, tmp_reg); -+ -+ return err; -+} -+ -+uint32_t fman_kg_get_schemes_total_counter(struct fman_kg_regs *regs) -+{ -+ return ioread32be(®s->fmkg_tpc); -+} -+ -+int fman_kg_build_cls_plan(struct fman_kg_cls_plan_params *params, -+ struct fman_kg_cp_regs *cls_plan_regs) -+{ -+ uint8_t entries_set, entry_bit; -+ int i; -+ -+ /* Zero out all group's register */ -+ memset(cls_plan_regs, 0, sizeof(struct fman_kg_cp_regs)); -+ -+ /* Go over all classification entries in params->entries_mask and -+ * configure the corresponding cpe register */ -+ entries_set = params->entries_mask; -+ for (i = 0; entries_set; i++) { -+ entry_bit = (uint8_t)(0x80 >> i); -+ if ((entry_bit & entries_set) == 0) -+ continue; -+ entries_set ^= entry_bit; -+ cls_plan_regs->kgcpe[i] = params->mask_vector[i]; -+ } -+ -+ return 0; -+} -+ -+int fman_kg_write_cls_plan(struct fman_kg_regs *regs, -+ uint8_t grp_id, -+ uint8_t entries_mask, -+ uint8_t hwport_id, -+ struct fman_kg_cp_regs *cls_plan_regs) -+{ -+ struct fman_kg_cp_regs *kgcpe_regs; -+ uint32_t tmp_reg; -+ int i, err; -+ -+ /* Check group index is valid and the group isn't empty */ -+ if (grp_id >= FM_KG_CLS_PLAN_GRPS_NUM) -+ return -EINVAL; -+ -+ /* Write indirect classification plan registers */ -+ kgcpe_regs = (struct fman_kg_cp_regs *)&(regs->fmkg_indirect[0]); -+ -+ for (i = 0; i < FM_KG_NUM_CLS_PLAN_ENTR; i++) { -+ iowrite32be(cls_plan_regs->kgcpe[i], &kgcpe_regs->kgcpe[i]); -+ } -+ -+ tmp_reg = build_ar_cls_plan(grp_id, entries_mask, hwport_id, TRUE); -+ err = fman_kg_write_ar_wait(regs, tmp_reg); -+ return err; -+} -+ -+int fman_kg_write_bind_schemes(struct fman_kg_regs *regs, -+ uint8_t hwport_id, -+ uint32_t schemes) -+{ -+ struct fman_kg_pe_regs *kg_pe_regs; -+ uint32_t tmp_reg; -+ int err; -+ -+ kg_pe_regs = (struct fman_kg_pe_regs *)&(regs->fmkg_indirect[0]); -+ -+ iowrite32be(schemes, &kg_pe_regs->fmkg_pe_sp); -+ -+ tmp_reg = build_ar_bind_scheme(hwport_id, TRUE); -+ err = fman_kg_write_ar_wait(regs, tmp_reg); -+ return err; -+} -+ -+int fman_kg_build_bind_cls_plans(uint8_t grp_base, -+ uint8_t grp_mask, -+ uint32_t *bind_cls_plans) -+{ -+ /* Check grp_base and grp_mask are 5-bits values */ -+ if ((grp_base & ~0x0000001F) || (grp_mask & ~0x0000001F)) -+ return -EINVAL; -+ -+ *bind_cls_plans = (uint32_t) ((grp_mask << FMAN_KG_PE_CPP_MASK_SHIFT) | grp_base); -+ return 0; -+} -+ -+ -+int fman_kg_write_bind_cls_plans(struct fman_kg_regs *regs, -+ uint8_t hwport_id, -+ uint32_t bind_cls_plans) -+{ -+ struct fman_kg_pe_regs *kg_pe_regs; -+ uint32_t tmp_reg; -+ int err; -+ -+ kg_pe_regs = (struct fman_kg_pe_regs *)&(regs->fmkg_indirect[0]); -+ -+ iowrite32be(bind_cls_plans, &kg_pe_regs->fmkg_pe_cpp); -+ -+ tmp_reg = build_ar_bind_cls_plan(hwport_id, TRUE); -+ err = fman_kg_write_ar_wait(regs, tmp_reg); -+ return err; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fman_prs.c -@@ -0,0 +1,129 @@ -+/* -+ * Copyright 2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "fsl_fman_prs.h" -+ -+uint32_t fman_prs_get_err_event(struct fman_prs_regs *regs, uint32_t ev_mask) -+{ -+ return ioread32be(®s->fmpr_perr) & ev_mask; -+} -+ -+uint32_t fman_prs_get_err_ev_mask(struct fman_prs_regs *regs) -+{ -+ return ioread32be(®s->fmpr_perer); -+} -+ -+void fman_prs_ack_err_event(struct fman_prs_regs *regs, uint32_t event) -+{ -+ iowrite32be(event, ®s->fmpr_perr); -+} -+ -+uint32_t fman_prs_get_expt_event(struct fman_prs_regs *regs, uint32_t ev_mask) -+{ -+ return ioread32be(®s->fmpr_pevr) & ev_mask; -+} -+ -+uint32_t fman_prs_get_expt_ev_mask(struct fman_prs_regs *regs) -+{ -+ return ioread32be(®s->fmpr_pever); -+} -+ -+void fman_prs_ack_expt_event(struct fman_prs_regs *regs, uint32_t event) -+{ -+ iowrite32be(event, ®s->fmpr_pevr); -+} -+ -+void fman_prs_defconfig(struct fman_prs_cfg *cfg) -+{ -+ cfg->port_id_stat = 0; -+ cfg->max_prs_cyc_lim = DEFAULT_MAX_PRS_CYC_LIM; -+ cfg->prs_exceptions = 0x03000000; -+} -+ -+int fman_prs_init(struct fman_prs_regs *regs, struct fman_prs_cfg *cfg) -+{ -+ uint32_t tmp; -+ -+ iowrite32be(cfg->max_prs_cyc_lim, ®s->fmpr_rpclim); -+ iowrite32be((FM_PCD_PRS_SINGLE_ECC | FM_PCD_PRS_PORT_IDLE_STS), -+ ®s->fmpr_pevr); -+ -+ if (cfg->prs_exceptions & FM_PCD_EX_PRS_SINGLE_ECC) -+ iowrite32be(FM_PCD_PRS_SINGLE_ECC, ®s->fmpr_pever); -+ else -+ iowrite32be(0, ®s->fmpr_pever); -+ -+ iowrite32be(FM_PCD_PRS_DOUBLE_ECC, ®s->fmpr_perr); -+ -+ tmp = 0; -+ if (cfg->prs_exceptions & FM_PCD_EX_PRS_DOUBLE_ECC) -+ tmp |= FM_PCD_PRS_DOUBLE_ECC; -+ iowrite32be(tmp, ®s->fmpr_perer); -+ -+ iowrite32be(cfg->port_id_stat, ®s->fmpr_ppsc); -+ -+ return 0; -+} -+ -+void fman_prs_enable(struct fman_prs_regs *regs) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->fmpr_rpimac) | FM_PCD_PRS_RPIMAC_EN; -+ iowrite32be(tmp, ®s->fmpr_rpimac); -+} -+ -+void fman_prs_disable(struct fman_prs_regs *regs) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(®s->fmpr_rpimac) & ~FM_PCD_PRS_RPIMAC_EN; -+ iowrite32be(tmp, ®s->fmpr_rpimac); -+} -+ -+int fman_prs_is_enabled(struct fman_prs_regs *regs) -+{ -+ return ioread32be(®s->fmpr_rpimac) & FM_PCD_PRS_RPIMAC_EN; -+} -+ -+void fman_prs_set_stst_port_msk(struct fman_prs_regs *regs, uint32_t pid_msk) -+{ -+ iowrite32be(pid_msk, ®s->fmpr_ppsc); -+} -+ -+void fman_prs_set_stst(struct fman_prs_regs *regs, bool enable) -+{ -+ if (enable) -+ iowrite32be(FM_PCD_PRS_PPSC_ALL_PORTS, ®s->fmpr_ppsc); -+ else -+ iowrite32be(0, ®s->fmpr_ppsc); -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/Makefile -@@ -0,0 +1,15 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+ -+NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc -+ -+ccflags-y += -I$(NCSW_FM_INC) -+ -+obj-y += fsl-ncsw-Pcd.o -+ -+fsl-ncsw-Pcd-objs := fm_port.o fm_port_im.o fman_port.o ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port.c -@@ -0,0 +1,6436 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_port.c -+ -+ @Description FM driver routines implementation. -+ *//***************************************************************************/ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "string_ext.h" -+#include "sprint_ext.h" -+#include "debug_ext.h" -+#include "fm_muram_ext.h" -+ -+#include "fman_common.h" -+#include "fm_port.h" -+#include "fm_port_dsar.h" -+#include "common/general.h" -+ -+/****************************************/ -+/* static functions */ -+/****************************************/ -+static t_Error FmPortConfigAutoResForDeepSleepSupport1(t_FmPort *p_FmPort); -+ -+static t_Error CheckInitParameters(t_FmPort *p_FmPort) -+{ -+ t_FmPortDriverParam *p_Params = p_FmPort->p_FmPortDriverParam; -+ struct fman_port_cfg *p_DfltConfig = &p_Params->dfltCfg; -+ t_Error ans = E_OK; -+ uint32_t unusedMask; -+ -+ if (p_FmPort->imEn) -+ { -+ if (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G) -+ if (p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth -+ > 2) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("fifoDeqPipelineDepth for IM 10G can't be larger than 2")); -+ -+ if ((ans = FmPortImCheckInitParameters(p_FmPort)) != E_OK) -+ return ERROR_CODE(ans); -+ } -+ else -+ { -+ /****************************************/ -+ /* Rx only */ -+ /****************************************/ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)) -+ { -+ /* external buffer pools */ -+ if (!p_Params->extBufPools.numOfPoolsUsed) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("extBufPools.numOfPoolsUsed=0. At least one buffer pool must be defined")); -+ -+ if (FmSpCheckBufPoolsParams(&p_Params->extBufPools, -+ p_Params->p_BackupBmPools, -+ &p_Params->bufPoolDepletion) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); -+ -+ /* Check that part of IC that needs copying is small enough to enter start margin */ -+ if (p_Params->intContext.size -+ && (p_Params->intContext.size -+ + p_Params->intContext.extBufOffset -+ > p_Params->bufMargins.startMargins)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("intContext.size is larger than start margins")); -+ -+ if ((p_Params->liodnOffset != (uint16_t)DPAA_LIODN_DONT_OVERRIDE) -+ && (p_Params->liodnOffset & ~FM_LIODN_OFFSET_MASK)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("liodnOffset is larger than %d", FM_LIODN_OFFSET_MASK+1)); -+ -+#ifdef FM_NO_BACKUP_POOLS -+ if ((p_FmPort->fmRevInfo.majorRev != 4) && (p_FmPort->fmRevInfo.majorRev < 6)) -+ if (p_FmPort->p_FmPortDriverParam->p_BackupBmPools) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("BackupBmPools")); -+#endif /* FM_NO_BACKUP_POOLS */ -+ } -+ -+ /****************************************/ -+ /* Non Rx ports */ -+ /****************************************/ -+ else -+ { -+ if (p_Params->deqSubPortal >= FM_MAX_NUM_OF_SUB_PORTALS) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ (" deqSubPortal has to be in the range of 0 - %d", FM_MAX_NUM_OF_SUB_PORTALS)); -+ -+ /* to protect HW internal-context from overwrite */ -+ if ((p_Params->intContext.size) -+ && (p_Params->intContext.intContextOffset -+ < MIN_TX_INT_OFFSET)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("non-Rx intContext.intContextOffset can't be smaller than %d", MIN_TX_INT_OFFSET)); -+ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_TX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_TX_10G) -+ /* in O/H DEFAULT_notSupported indicates that it is not supported and should not be checked */ -+ || (p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth -+ != DEFAULT_notSupported)) -+ { -+ /* Check that not larger than 8 */ -+ if ((!p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth) -+ || (p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth -+ > MAX_FIFO_PIPELINE_DEPTH)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("fifoDeqPipelineDepth can't be larger than %d", MAX_FIFO_PIPELINE_DEPTH)); -+ } -+ } -+ -+ /****************************************/ -+ /* Rx Or Offline Parsing */ -+ /****************************************/ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ { -+ if (!p_Params->dfltFqid) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("dfltFqid must be between 1 and 2^24-1")); -+#if defined(FM_CAPWAP_SUPPORT) && defined(FM_LOCKUP_ALIGNMENT_ERRATA_FMAN_SW004) -+ if (p_FmPort->p_FmPortDriverParam->bufferPrefixContent.manipExtraSpace % 16) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufferPrefixContent.manipExtraSpace has to be devidable by 16")); -+#endif /* defined(FM_CAPWAP_SUPPORT) && ... */ -+ } -+ -+ /****************************************/ -+ /* All ports */ -+ /****************************************/ -+ /* common BMI registers values */ -+ /* Check that Queue Id is not larger than 2^24, and is not 0 */ -+ if ((p_Params->errFqid & ~0x00FFFFFF) || !p_Params->errFqid) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("errFqid must be between 1 and 2^24-1")); -+ if (p_Params->dfltFqid & ~0x00FFFFFF) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("dfltFqid must be between 1 and 2^24-1")); -+ } -+ -+ /****************************************/ -+ /* Rx only */ -+ /****************************************/ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)) -+ { -+ if (p_DfltConfig->rx_pri_elevation % BMI_FIFO_UNITS) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("rxFifoPriElevationLevel has to be divisible by %d", BMI_FIFO_UNITS)); -+ if ((p_DfltConfig->rx_pri_elevation < BMI_FIFO_UNITS) -+ || (p_DfltConfig->rx_pri_elevation > MAX_PORT_FIFO_SIZE)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("rxFifoPriElevationLevel has to be in the range of 256 - %d", MAX_PORT_FIFO_SIZE)); -+ if (p_DfltConfig->rx_fifo_thr % BMI_FIFO_UNITS) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("rxFifoThreshold has to be divisible by %d", BMI_FIFO_UNITS)); -+ if ((p_DfltConfig->rx_fifo_thr < BMI_FIFO_UNITS) -+ || (p_DfltConfig->rx_fifo_thr > MAX_PORT_FIFO_SIZE)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("rxFifoThreshold has to be in the range of 256 - %d", MAX_PORT_FIFO_SIZE)); -+ -+ /* Check that not larger than 16 */ -+ if (p_DfltConfig->rx_cut_end_bytes > FRAME_END_DATA_SIZE) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("cutBytesFromEnd can't be larger than %d", FRAME_END_DATA_SIZE)); -+ -+ if (FmSpCheckBufMargins(&p_Params->bufMargins) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); -+ -+ /* extra FIFO size (allowed only to Rx ports) */ -+ if (p_Params->setSizeOfFifo -+ && (p_FmPort->fifoBufs.extra % BMI_FIFO_UNITS)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("fifoBufs.extra has to be divisible by %d", BMI_FIFO_UNITS)); -+ -+ if (p_Params->bufPoolDepletion.poolsGrpModeEnable -+ && !p_Params->bufPoolDepletion.numOfPools) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("bufPoolDepletion.numOfPools can not be 0 when poolsGrpModeEnable=TRUE")); -+#ifdef FM_CSI_CFED_LIMIT -+ if (p_FmPort->fmRevInfo.majorRev == 4) -+ { -+ /* Check that not larger than 16 */ -+ if (p_DfltConfig->rx_cut_end_bytes + p_DfltConfig->checksum_bytes_ignore > FRAME_END_DATA_SIZE) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("cheksumLastBytesIgnore + cutBytesFromEnd can't be larger than %d", FRAME_END_DATA_SIZE)); -+ } -+#endif /* FM_CSI_CFED_LIMIT */ -+ } -+ -+ /****************************************/ -+ /* Non Rx ports */ -+ /****************************************/ -+ /* extra FIFO size (allowed only to Rx ports) */ -+ else -+ if (p_FmPort->fifoBufs.extra) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ (" No fifoBufs.extra for non Rx ports")); -+ -+ /****************************************/ -+ /* Tx only */ -+ /****************************************/ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_TX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_TX_10G)) -+ { -+ if (p_DfltConfig->tx_fifo_min_level % BMI_FIFO_UNITS) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("txFifoMinFillLevel has to be divisible by %d", BMI_FIFO_UNITS)); -+ if (p_DfltConfig->tx_fifo_min_level > (MAX_PORT_FIFO_SIZE - 256)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("txFifoMinFillLevel has to be in the range of 0 - %d", (MAX_PORT_FIFO_SIZE - 256))); -+ if (p_DfltConfig->tx_fifo_low_comf_level % BMI_FIFO_UNITS) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("txFifoLowComfLevel has to be divisible by %d", BMI_FIFO_UNITS)); -+ if ((p_DfltConfig->tx_fifo_low_comf_level < BMI_FIFO_UNITS) -+ || (p_DfltConfig->tx_fifo_low_comf_level > MAX_PORT_FIFO_SIZE)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("txFifoLowComfLevel has to be in the range of 256 - %d", MAX_PORT_FIFO_SIZE)); -+ -+ if (p_FmPort->portType == e_FM_PORT_TYPE_TX) -+ if (p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth -+ > 2) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("fifoDeqPipelineDepth for 1G can't be larger than 2")); -+ } -+ -+ /****************************************/ -+ /* Non Tx Ports */ -+ /****************************************/ -+ /* If discard override was selected , no frames may be discarded. */ -+ else -+ if (p_DfltConfig->discard_override && p_Params->errorsToDiscard) -+ RETURN_ERROR( -+ MAJOR, -+ E_CONFLICT, -+ ("errorsToDiscard is not empty, but frmDiscardOverride selected (all discarded frames to be enqueued to error queue).")); -+ -+ /****************************************/ -+ /* Rx and Offline parsing */ -+ /****************************************/ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ { -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ unusedMask = BMI_STATUS_OP_MASK_UNUSED; -+ else -+ unusedMask = BMI_STATUS_RX_MASK_UNUSED; -+ -+ /* Check that no common bits with BMI_STATUS_MASK_UNUSED */ -+ if (p_Params->errorsToDiscard & unusedMask) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, -+ ("errorsToDiscard contains undefined bits")); -+ } -+ -+ /****************************************/ -+ /* Offline Ports */ -+ /****************************************/ -+#ifdef FM_OP_OPEN_DMA_MIN_LIMIT -+ if ((p_FmPort->fmRevInfo.majorRev >= 6) -+ && (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ && p_Params->setNumOfOpenDmas -+ && (p_FmPort->openDmas.num < MIN_NUM_OF_OP_DMAS)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("For Offline port, openDmas.num can't be smaller than %d", MIN_NUM_OF_OP_DMAS)); -+#endif /* FM_OP_OPEN_DMA_MIN_LIMIT */ -+ -+ /****************************************/ -+ /* Offline & HC Ports */ -+ /****************************************/ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_OH_HOST_COMMAND)) -+ { -+#ifndef FM_FRAME_END_PARAMS_FOR_OP -+ if ((p_FmPort->fmRevInfo.majorRev < 6) && -+ (p_FmPort->p_FmPortDriverParam->cheksumLastBytesIgnore != DEFAULT_notSupported)) -+ /* this is an indication that user called config for this mode which is not supported in this integration */ -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("cheksumLastBytesIgnore is available for Rx & Tx ports only")); -+#endif /* !FM_FRAME_END_PARAMS_FOR_OP */ -+ -+#ifndef FM_DEQ_PIPELINE_PARAMS_FOR_OP -+ if ((!((p_FmPort->fmRevInfo.majorRev == 4) || -+ (p_FmPort->fmRevInfo.majorRev >= 6))) && -+ (p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth != DEFAULT_notSupported)) -+ /* this is an indication that user called config for this mode which is not supported in this integration */ -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, ("fifoDeqPipelineDepth is available for Tx ports only")); -+#endif /* !FM_DEQ_PIPELINE_PARAMS_FOR_OP */ -+ } -+ -+ /****************************************/ -+ /* All ports */ -+ /****************************************/ -+ /* Check that not larger than 16 */ -+ if ((p_Params->cheksumLastBytesIgnore > FRAME_END_DATA_SIZE) -+ && ((p_Params->cheksumLastBytesIgnore != DEFAULT_notSupported))) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("cheksumLastBytesIgnore can't be larger than %d", FRAME_END_DATA_SIZE)); -+ -+ if (FmSpCheckIntContextParams(&p_Params->intContext) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); -+ -+ /* common BMI registers values */ -+ if (p_Params->setNumOfTasks -+ && ((!p_FmPort->tasks.num) -+ || (p_FmPort->tasks.num > MAX_NUM_OF_TASKS))) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("tasks.num can't be larger than %d", MAX_NUM_OF_TASKS)); -+ if (p_Params->setNumOfTasks -+ && (p_FmPort->tasks.extra > MAX_NUM_OF_EXTRA_TASKS)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("tasks.extra can't be larger than %d", MAX_NUM_OF_EXTRA_TASKS)); -+ if (p_Params->setNumOfOpenDmas -+ && ((!p_FmPort->openDmas.num) -+ || (p_FmPort->openDmas.num > MAX_NUM_OF_DMAS))) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("openDmas.num can't be larger than %d", MAX_NUM_OF_DMAS)); -+ if (p_Params->setNumOfOpenDmas -+ && (p_FmPort->openDmas.extra > MAX_NUM_OF_EXTRA_DMAS)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("openDmas.extra can't be larger than %d", MAX_NUM_OF_EXTRA_DMAS)); -+ if (p_Params->setSizeOfFifo -+ && (!p_FmPort->fifoBufs.num -+ || (p_FmPort->fifoBufs.num > MAX_PORT_FIFO_SIZE))) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("fifoBufs.num has to be in the range of 256 - %d", MAX_PORT_FIFO_SIZE)); -+ if (p_Params->setSizeOfFifo && (p_FmPort->fifoBufs.num % BMI_FIFO_UNITS)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("fifoBufs.num has to be divisible by %d", BMI_FIFO_UNITS)); -+ -+#ifdef FM_QMI_NO_DEQ_OPTIONS_SUPPORT -+ if (p_FmPort->fmRevInfo.majorRev == 4) -+ if (p_FmPort->p_FmPortDriverParam->deqPrefetchOption != DEFAULT_notSupported) -+ /* this is an indication that user called config for this mode which is not supported in this integration */ -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, ("deqPrefetchOption")); -+#endif /* FM_QMI_NO_DEQ_OPTIONS_SUPPORT */ -+ -+ return E_OK; -+} -+ -+static t_Error VerifySizeOfFifo(t_FmPort *p_FmPort) -+{ -+ uint32_t minFifoSizeRequired = 0, optFifoSizeForB2B = 0; -+ -+ /*************************/ -+ /* TX PORTS */ -+ /*************************/ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_TX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_TX_10G)) -+ { -+ minFifoSizeRequired = -+ (uint32_t)(ROUND_UP(p_FmPort->maxFrameLength, BMI_FIFO_UNITS) -+ + (3 * BMI_FIFO_UNITS)); -+ if (!p_FmPort->imEn) -+ minFifoSizeRequired += -+ p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth -+ * BMI_FIFO_UNITS; -+ -+ optFifoSizeForB2B = minFifoSizeRequired; -+ -+ /* Add some margin for back-to-back capability to improve performance, -+ allows the hardware to pipeline new frame dma while the previous -+ frame not yet transmitted. */ -+ if (p_FmPort->portType == e_FM_PORT_TYPE_TX_10G) -+ optFifoSizeForB2B += 3 * BMI_FIFO_UNITS; -+ else -+ optFifoSizeForB2B += 2 * BMI_FIFO_UNITS; -+ } -+ -+ /*************************/ -+ /* RX IM PORTS */ -+ /*************************/ -+ else -+ if (((p_FmPort->portType == e_FM_PORT_TYPE_RX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)) -+ && p_FmPort->imEn) -+ { -+ optFifoSizeForB2B = -+ minFifoSizeRequired = -+ (uint32_t)(ROUND_UP(p_FmPort->maxFrameLength, BMI_FIFO_UNITS) -+ + (4 * BMI_FIFO_UNITS)); -+ } -+ -+ /*************************/ -+ /* RX non-IM PORTS */ -+ /*************************/ -+ else -+ if (((p_FmPort->portType == e_FM_PORT_TYPE_RX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)) -+ && !p_FmPort->imEn) -+ { -+ if (p_FmPort->fmRevInfo.majorRev == 4) -+ { -+ if (p_FmPort->rxPoolsParams.numOfPools == 1) -+ minFifoSizeRequired = 8 * BMI_FIFO_UNITS; -+ else -+ minFifoSizeRequired = -+ (uint32_t)(ROUND_UP(p_FmPort->rxPoolsParams.secondLargestBufSize, BMI_FIFO_UNITS) -+ + (7 * BMI_FIFO_UNITS)); -+ } -+ else -+ { -+#if (DPAA_VERSION >= 11) -+ minFifoSizeRequired = -+ (uint32_t)(ROUND_UP(p_FmPort->maxFrameLength, BMI_FIFO_UNITS) -+ + (5 * BMI_FIFO_UNITS)); -+ /* 4 according to spec + 1 for FOF>0 */ -+#else -+ minFifoSizeRequired = (uint32_t) -+ (ROUND_UP(MIN(p_FmPort->maxFrameLength, p_FmPort->rxPoolsParams.largestBufSize), BMI_FIFO_UNITS) -+ + (7*BMI_FIFO_UNITS)); -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ -+ optFifoSizeForB2B = minFifoSizeRequired; -+ -+ /* Add some margin for back-to-back capability to improve performance, -+ allows the hardware to pipeline new frame dma while the previous -+ frame not yet transmitted. */ -+ if (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G) -+ optFifoSizeForB2B += 8 * BMI_FIFO_UNITS; -+ else -+ optFifoSizeForB2B += 3 * BMI_FIFO_UNITS; -+ } -+ -+ /* For O/H ports, check fifo size and update if necessary */ -+ else -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_OH_HOST_COMMAND)) -+ { -+#if (DPAA_VERSION >= 11) -+ optFifoSizeForB2B = -+ minFifoSizeRequired = -+ (uint32_t)(ROUND_UP(p_FmPort->maxFrameLength, BMI_FIFO_UNITS) -+ + ((p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth -+ + 5) * BMI_FIFO_UNITS)); -+ /* 4 according to spec + 1 for FOF>0 */ -+#else -+ optFifoSizeForB2B = minFifoSizeRequired = (uint32_t)((p_FmPort->tasks.num + 2) * BMI_FIFO_UNITS); -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ -+ ASSERT_COND(minFifoSizeRequired > 0); -+ ASSERT_COND(optFifoSizeForB2B >= minFifoSizeRequired); -+ -+ /* Verify the size */ -+ if (p_FmPort->fifoBufs.num < minFifoSizeRequired) -+ DBG(INFO, -+ ("FIFO size is %d and should be enlarged to %d bytes",p_FmPort->fifoBufs.num, minFifoSizeRequired)); -+ else if (p_FmPort->fifoBufs.num < optFifoSizeForB2B) -+ DBG(INFO, -+ ("For back-to-back frames processing, FIFO size is %d and needs to enlarge to %d bytes", p_FmPort->fifoBufs.num, optFifoSizeForB2B)); -+ -+ return E_OK; -+} -+ -+static void FmPortDriverParamFree(t_FmPort *p_FmPort) -+{ -+ if (p_FmPort->p_FmPortDriverParam) -+ { -+ XX_Free(p_FmPort->p_FmPortDriverParam); -+ p_FmPort->p_FmPortDriverParam = NULL; -+ } -+} -+ -+static t_Error SetExtBufferPools(t_FmPort *p_FmPort) -+{ -+ t_FmExtPools *p_ExtBufPools = &p_FmPort->p_FmPortDriverParam->extBufPools; -+ t_FmBufPoolDepletion *p_BufPoolDepletion = -+ &p_FmPort->p_FmPortDriverParam->bufPoolDepletion; -+ uint8_t orderedArray[FM_PORT_MAX_NUM_OF_EXT_POOLS]; -+ uint16_t sizesArray[BM_MAX_NUM_OF_POOLS]; -+ int i = 0, j = 0, err; -+ struct fman_port_bpools bpools; -+ -+ memset(&orderedArray, 0, sizeof(uint8_t) * FM_PORT_MAX_NUM_OF_EXT_POOLS); -+ memset(&sizesArray, 0, sizeof(uint16_t) * BM_MAX_NUM_OF_POOLS); -+ memcpy(&p_FmPort->extBufPools, p_ExtBufPools, sizeof(t_FmExtPools)); -+ -+ FmSpSetBufPoolsInAscOrderOfBufSizes(p_ExtBufPools, orderedArray, -+ sizesArray); -+ -+ /* Prepare flibs bpools structure */ -+ memset(&bpools, 0, sizeof(struct fman_port_bpools)); -+ bpools.count = p_ExtBufPools->numOfPoolsUsed; -+ bpools.counters_enable = TRUE; -+ for (i = 0; i < p_ExtBufPools->numOfPoolsUsed; i++) -+ { -+ bpools.bpool[i].bpid = orderedArray[i]; -+ bpools.bpool[i].size = sizesArray[orderedArray[i]]; -+ /* functionality available only for some derivatives (limited by config) */ -+ if (p_FmPort->p_FmPortDriverParam->p_BackupBmPools) -+ for (j = 0; -+ j -+ < p_FmPort->p_FmPortDriverParam->p_BackupBmPools->numOfBackupPools; -+ j++) -+ if (orderedArray[i] -+ == p_FmPort->p_FmPortDriverParam->p_BackupBmPools->poolIds[j]) -+ { -+ bpools.bpool[i].is_backup = TRUE; -+ break; -+ } -+ } -+ -+ /* save pools parameters for later use */ -+ p_FmPort->rxPoolsParams.numOfPools = p_ExtBufPools->numOfPoolsUsed; -+ p_FmPort->rxPoolsParams.largestBufSize = -+ sizesArray[orderedArray[p_ExtBufPools->numOfPoolsUsed - 1]]; -+ p_FmPort->rxPoolsParams.secondLargestBufSize = -+ sizesArray[orderedArray[p_ExtBufPools->numOfPoolsUsed - 2]]; -+ -+ /* FMBM_RMPD reg. - pool depletion */ -+ if (p_BufPoolDepletion->poolsGrpModeEnable) -+ { -+ bpools.grp_bp_depleted_num = p_BufPoolDepletion->numOfPools; -+ for (i = 0; i < BM_MAX_NUM_OF_POOLS; i++) -+ { -+ if (p_BufPoolDepletion->poolsToConsider[i]) -+ { -+ for (j = 0; j < p_ExtBufPools->numOfPoolsUsed; j++) -+ { -+ if (i == orderedArray[j]) -+ { -+ bpools.bpool[j].grp_bp_depleted = TRUE; -+ break; -+ } -+ } -+ } -+ } -+ } -+ -+ if (p_BufPoolDepletion->singlePoolModeEnable) -+ { -+ for (i = 0; i < BM_MAX_NUM_OF_POOLS; i++) -+ { -+ if (p_BufPoolDepletion->poolsToConsiderForSingleMode[i]) -+ { -+ for (j = 0; j < p_ExtBufPools->numOfPoolsUsed; j++) -+ { -+ if (i == orderedArray[j]) -+ { -+ bpools.bpool[j].single_bp_depleted = TRUE; -+ break; -+ } -+ } -+ } -+ } -+ } -+ -+#if (DPAA_VERSION >= 11) -+ /* fill QbbPEV */ -+ if (p_BufPoolDepletion->poolsGrpModeEnable -+ || p_BufPoolDepletion->singlePoolModeEnable) -+ { -+ for (i = 0; i < FM_MAX_NUM_OF_PFC_PRIORITIES; i++) -+ { -+ if (p_BufPoolDepletion->pfcPrioritiesEn[i] == TRUE) -+ { -+ bpools.bpool[i].pfc_priorities_en = TRUE; -+ } -+ } -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ /* Issue flibs function */ -+ err = fman_port_set_bpools(&p_FmPort->port, &bpools); -+ if (err != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fman_port_set_bpools")); -+ -+ if (p_FmPort->p_FmPortDriverParam->p_BackupBmPools) -+ XX_Free(p_FmPort->p_FmPortDriverParam->p_BackupBmPools); -+ -+ return E_OK; -+} -+ -+static t_Error ClearPerfCnts(t_FmPort *p_FmPort) -+{ -+ if (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ FM_PORT_ModifyCounter(p_FmPort, e_FM_PORT_COUNTERS_QUEUE_UTIL, 0); -+ FM_PORT_ModifyCounter(p_FmPort, e_FM_PORT_COUNTERS_TASK_UTIL, 0); -+ FM_PORT_ModifyCounter(p_FmPort, e_FM_PORT_COUNTERS_DMA_UTIL, 0); -+ FM_PORT_ModifyCounter(p_FmPort, e_FM_PORT_COUNTERS_FIFO_UTIL, 0); -+ return E_OK; -+} -+ -+static t_Error InitLowLevelDriver(t_FmPort *p_FmPort) -+{ -+ t_FmPortDriverParam *p_DriverParams = p_FmPort->p_FmPortDriverParam; -+ struct fman_port_params portParams; -+ uint32_t tmpVal; -+ t_Error err; -+ -+ /* Set up flibs parameters and issue init function */ -+ -+ memset(&portParams, 0, sizeof(struct fman_port_params)); -+ portParams.discard_mask = p_DriverParams->errorsToDiscard; -+ portParams.dflt_fqid = p_DriverParams->dfltFqid; -+ portParams.err_fqid = p_DriverParams->errFqid; -+ portParams.deq_sp = p_DriverParams->deqSubPortal; -+ portParams.dont_release_buf = p_DriverParams->dontReleaseBuf; -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX_10G): -+ case (e_FM_PORT_TYPE_RX): -+ portParams.err_mask = (RX_ERRS_TO_ENQ & ~portParams.discard_mask); -+ if (!p_FmPort->imEn) -+ { -+ if (p_DriverParams->forwardReuseIntContext) -+ p_DriverParams->dfltCfg.rx_fd_bits = -+ (uint8_t)(BMI_PORT_RFNE_FRWD_RPD >> 24); -+ } -+ break; -+ -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ portParams.err_mask = (OP_ERRS_TO_ENQ & ~portParams.discard_mask); -+ break; -+ break; -+ -+ default: -+ break; -+ } -+ -+ tmpVal = -+ (uint32_t)( -+ (p_FmPort->internalBufferOffset % OFFSET_UNITS) ? (p_FmPort->internalBufferOffset -+ / OFFSET_UNITS + 1) : -+ (p_FmPort->internalBufferOffset / OFFSET_UNITS)); -+ p_FmPort->internalBufferOffset = (uint8_t)(tmpVal * OFFSET_UNITS); -+ p_DriverParams->dfltCfg.int_buf_start_margin = -+ p_FmPort->internalBufferOffset; -+ -+ p_DriverParams->dfltCfg.ext_buf_start_margin = -+ p_DriverParams->bufMargins.startMargins; -+ p_DriverParams->dfltCfg.ext_buf_end_margin = -+ p_DriverParams->bufMargins.endMargins; -+ -+ p_DriverParams->dfltCfg.ic_ext_offset = -+ p_DriverParams->intContext.extBufOffset; -+ p_DriverParams->dfltCfg.ic_int_offset = -+ p_DriverParams->intContext.intContextOffset; -+ p_DriverParams->dfltCfg.ic_size = p_DriverParams->intContext.size; -+ -+ p_DriverParams->dfltCfg.stats_counters_enable = TRUE; -+ p_DriverParams->dfltCfg.perf_counters_enable = TRUE; -+ p_DriverParams->dfltCfg.queue_counters_enable = TRUE; -+ -+ p_DriverParams->dfltCfg.perf_cnt_params.task_val = -+ (uint8_t)p_FmPort->tasks.num; -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING || -+ p_FmPort->portType == e_FM_PORT_TYPE_OH_HOST_COMMAND)p_DriverParams->dfltCfg.perf_cnt_params.queue_val = 0; -+ else -+ p_DriverParams->dfltCfg.perf_cnt_params.queue_val = 1; -+ p_DriverParams->dfltCfg.perf_cnt_params.dma_val = -+ (uint8_t)p_FmPort->openDmas.num; -+ p_DriverParams->dfltCfg.perf_cnt_params.fifo_val = p_FmPort->fifoBufs.num; -+ -+ if (0 -+ != fman_port_init(&p_FmPort->port, &p_DriverParams->dfltCfg, -+ &portParams)) -+ RETURN_ERROR(MAJOR, E_NO_DEVICE, ("fman_port_init")); -+ -+ if (p_FmPort->imEn && ((err = FmPortImInit(p_FmPort)) != E_OK)) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ else -+ { -+ // from QMIInit -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX)) -+ { -+ if (p_DriverParams->deqPrefetchOption == e_FM_PORT_DEQ_NO_PREFETCH) -+ FmSetPortPreFetchConfiguration(p_FmPort->h_Fm, p_FmPort->portId, -+ FALSE); -+ else -+ FmSetPortPreFetchConfiguration(p_FmPort->h_Fm, p_FmPort->portId, -+ TRUE); -+ } -+ } -+ /* The code bellow is a trick so the FM will not release the buffer -+ to BM nor will try to enqueue the frame to QM */ -+ if (((p_FmPort->portType == e_FM_PORT_TYPE_TX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_TX)) && (!p_FmPort->imEn)) -+ { -+ if (!p_DriverParams->dfltFqid && p_DriverParams->dontReleaseBuf) -+ { -+ /* override fmbm_tcfqid 0 with a false non-0 value. This will force FM to -+ * act according to tfene. Otherwise, if fmbm_tcfqid is 0 the FM will release -+ * buffers to BM regardless of fmbm_tfene -+ */ -+ WRITE_UINT32(p_FmPort->port.bmi_regs->tx.fmbm_tcfqid, 0xFFFFFF); -+ WRITE_UINT32(p_FmPort->port.bmi_regs->tx.fmbm_tfene, -+ NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE); -+ } -+ } -+ -+ return E_OK; -+} -+ -+static bool CheckRxBmiCounter(t_FmPort *p_FmPort, e_FmPortCounters counter) -+{ -+ UNUSED(p_FmPort); -+ -+ switch (counter) -+ { -+ case (e_FM_PORT_COUNTERS_CYCLE): -+ case (e_FM_PORT_COUNTERS_TASK_UTIL): -+ case (e_FM_PORT_COUNTERS_QUEUE_UTIL): -+ case (e_FM_PORT_COUNTERS_DMA_UTIL): -+ case (e_FM_PORT_COUNTERS_FIFO_UTIL): -+ case (e_FM_PORT_COUNTERS_RX_PAUSE_ACTIVATION): -+ case (e_FM_PORT_COUNTERS_FRAME): -+ case (e_FM_PORT_COUNTERS_DISCARD_FRAME): -+ case (e_FM_PORT_COUNTERS_RX_BAD_FRAME): -+ case (e_FM_PORT_COUNTERS_RX_LARGE_FRAME): -+ case (e_FM_PORT_COUNTERS_RX_FILTER_FRAME): -+ case (e_FM_PORT_COUNTERS_RX_LIST_DMA_ERR): -+ case (e_FM_PORT_COUNTERS_RX_OUT_OF_BUFFERS_DISCARD): -+ case (e_FM_PORT_COUNTERS_DEALLOC_BUF): -+ case (e_FM_PORT_COUNTERS_PREPARE_TO_ENQUEUE_COUNTER): -+ return TRUE; -+ default: -+ return FALSE; -+ } -+} -+ -+static bool CheckTxBmiCounter(t_FmPort *p_FmPort, e_FmPortCounters counter) -+{ -+ UNUSED(p_FmPort); -+ -+ switch (counter) -+ { -+ case (e_FM_PORT_COUNTERS_CYCLE): -+ case (e_FM_PORT_COUNTERS_TASK_UTIL): -+ case (e_FM_PORT_COUNTERS_QUEUE_UTIL): -+ case (e_FM_PORT_COUNTERS_DMA_UTIL): -+ case (e_FM_PORT_COUNTERS_FIFO_UTIL): -+ case (e_FM_PORT_COUNTERS_FRAME): -+ case (e_FM_PORT_COUNTERS_DISCARD_FRAME): -+ case (e_FM_PORT_COUNTERS_LENGTH_ERR): -+ case (e_FM_PORT_COUNTERS_UNSUPPRTED_FORMAT): -+ case (e_FM_PORT_COUNTERS_DEALLOC_BUF): -+ return TRUE; -+ default: -+ return FALSE; -+ } -+} -+ -+static bool CheckOhBmiCounter(t_FmPort *p_FmPort, e_FmPortCounters counter) -+{ -+ switch (counter) -+ { -+ case (e_FM_PORT_COUNTERS_CYCLE): -+ case (e_FM_PORT_COUNTERS_TASK_UTIL): -+ case (e_FM_PORT_COUNTERS_DMA_UTIL): -+ case (e_FM_PORT_COUNTERS_FIFO_UTIL): -+ case (e_FM_PORT_COUNTERS_FRAME): -+ case (e_FM_PORT_COUNTERS_DISCARD_FRAME): -+ case (e_FM_PORT_COUNTERS_RX_LIST_DMA_ERR): -+ case (e_FM_PORT_COUNTERS_WRED_DISCARD): -+ case (e_FM_PORT_COUNTERS_LENGTH_ERR): -+ case (e_FM_PORT_COUNTERS_UNSUPPRTED_FORMAT): -+ case (e_FM_PORT_COUNTERS_DEALLOC_BUF): -+ return TRUE; -+ case (e_FM_PORT_COUNTERS_RX_FILTER_FRAME): -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_HOST_COMMAND) -+ return FALSE; -+ else -+ return TRUE; -+ default: -+ return FALSE; -+ } -+} -+ -+static t_Error BmiPortCheckAndGetCounterType( -+ t_FmPort *p_FmPort, e_FmPortCounters counter, -+ enum fman_port_stats_counters *p_StatsType, -+ enum fman_port_perf_counters *p_PerfType, bool *p_IsStats) -+{ -+ volatile uint32_t *p_Reg; -+ bool isValid; -+ -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX_10G): -+ case (e_FM_PORT_TYPE_RX): -+ p_Reg = &p_FmPort->port.bmi_regs->rx.fmbm_rstc; -+ isValid = CheckRxBmiCounter(p_FmPort, counter); -+ break; -+ case (e_FM_PORT_TYPE_TX_10G): -+ case (e_FM_PORT_TYPE_TX): -+ p_Reg = &p_FmPort->port.bmi_regs->tx.fmbm_tstc; -+ isValid = CheckTxBmiCounter(p_FmPort, counter); -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ case (e_FM_PORT_TYPE_OH_HOST_COMMAND): -+ p_Reg = &p_FmPort->port.bmi_regs->oh.fmbm_ostc; -+ isValid = CheckOhBmiCounter(p_FmPort, counter); -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Unsupported port type")); -+ } -+ -+ if (!isValid) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, -+ ("Requested counter is not available for this port type")); -+ -+ /* check that counters are enabled */ -+ switch (counter) -+ { -+ case (e_FM_PORT_COUNTERS_CYCLE): -+ case (e_FM_PORT_COUNTERS_TASK_UTIL): -+ case (e_FM_PORT_COUNTERS_QUEUE_UTIL): -+ case (e_FM_PORT_COUNTERS_DMA_UTIL): -+ case (e_FM_PORT_COUNTERS_FIFO_UTIL): -+ case (e_FM_PORT_COUNTERS_RX_PAUSE_ACTIVATION): -+ /* performance counters - may be read when disabled */ -+ *p_IsStats = FALSE; -+ break; -+ case (e_FM_PORT_COUNTERS_FRAME): -+ case (e_FM_PORT_COUNTERS_DISCARD_FRAME): -+ case (e_FM_PORT_COUNTERS_DEALLOC_BUF): -+ case (e_FM_PORT_COUNTERS_RX_BAD_FRAME): -+ case (e_FM_PORT_COUNTERS_RX_LARGE_FRAME): -+ case (e_FM_PORT_COUNTERS_RX_FILTER_FRAME): -+ case (e_FM_PORT_COUNTERS_RX_LIST_DMA_ERR): -+ case (e_FM_PORT_COUNTERS_RX_OUT_OF_BUFFERS_DISCARD): -+ case (e_FM_PORT_COUNTERS_LENGTH_ERR): -+ case (e_FM_PORT_COUNTERS_UNSUPPRTED_FORMAT): -+ case (e_FM_PORT_COUNTERS_WRED_DISCARD): -+ *p_IsStats = TRUE; -+ if (!(GET_UINT32(*p_Reg) & BMI_COUNTERS_EN)) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, -+ ("Requested counter was not enabled")); -+ break; -+ default: -+ break; -+ } -+ -+ /* Set counter */ -+ switch (counter) -+ { -+ case (e_FM_PORT_COUNTERS_CYCLE): -+ *p_PerfType = E_FMAN_PORT_PERF_CNT_CYCLE; -+ break; -+ case (e_FM_PORT_COUNTERS_TASK_UTIL): -+ *p_PerfType = E_FMAN_PORT_PERF_CNT_TASK_UTIL; -+ break; -+ case (e_FM_PORT_COUNTERS_QUEUE_UTIL): -+ *p_PerfType = E_FMAN_PORT_PERF_CNT_QUEUE_UTIL; -+ break; -+ case (e_FM_PORT_COUNTERS_DMA_UTIL): -+ *p_PerfType = E_FMAN_PORT_PERF_CNT_DMA_UTIL; -+ break; -+ case (e_FM_PORT_COUNTERS_FIFO_UTIL): -+ *p_PerfType = E_FMAN_PORT_PERF_CNT_FIFO_UTIL; -+ break; -+ case (e_FM_PORT_COUNTERS_RX_PAUSE_ACTIVATION): -+ *p_PerfType = E_FMAN_PORT_PERF_CNT_RX_PAUSE; -+ break; -+ case (e_FM_PORT_COUNTERS_FRAME): -+ *p_StatsType = E_FMAN_PORT_STATS_CNT_FRAME; -+ break; -+ case (e_FM_PORT_COUNTERS_DISCARD_FRAME): -+ *p_StatsType = E_FMAN_PORT_STATS_CNT_DISCARD; -+ break; -+ case (e_FM_PORT_COUNTERS_DEALLOC_BUF): -+ *p_StatsType = E_FMAN_PORT_STATS_CNT_DEALLOC_BUF; -+ break; -+ case (e_FM_PORT_COUNTERS_RX_BAD_FRAME): -+ *p_StatsType = E_FMAN_PORT_STATS_CNT_RX_BAD_FRAME; -+ break; -+ case (e_FM_PORT_COUNTERS_RX_LARGE_FRAME): -+ *p_StatsType = E_FMAN_PORT_STATS_CNT_RX_LARGE_FRAME; -+ break; -+ case (e_FM_PORT_COUNTERS_RX_OUT_OF_BUFFERS_DISCARD): -+ *p_StatsType = E_FMAN_PORT_STATS_CNT_RX_OUT_OF_BUF; -+ break; -+ case (e_FM_PORT_COUNTERS_RX_FILTER_FRAME): -+ *p_StatsType = E_FMAN_PORT_STATS_CNT_FILTERED_FRAME; -+ break; -+ case (e_FM_PORT_COUNTERS_RX_LIST_DMA_ERR): -+ *p_StatsType = E_FMAN_PORT_STATS_CNT_DMA_ERR; -+ break; -+ case (e_FM_PORT_COUNTERS_WRED_DISCARD): -+ *p_StatsType = E_FMAN_PORT_STATS_CNT_WRED_DISCARD; -+ break; -+ case (e_FM_PORT_COUNTERS_LENGTH_ERR): -+ *p_StatsType = E_FMAN_PORT_STATS_CNT_LEN_ERR; -+ break; -+ case (e_FM_PORT_COUNTERS_UNSUPPRTED_FORMAT): -+ *p_StatsType = E_FMAN_PORT_STATS_CNT_UNSUPPORTED_FORMAT; -+ break; -+ default: -+ break; -+ } -+ -+ return E_OK; -+} -+ -+static t_Error AdditionalPrsParams(t_FmPort *p_FmPort, -+ t_FmPcdPrsAdditionalHdrParams *p_HdrParams, -+ uint32_t *p_SoftSeqAttachReg) -+{ -+ uint8_t hdrNum, Ipv4HdrNum; -+ u_FmPcdHdrPrsOpts *p_prsOpts; -+ uint32_t tmpReg = *p_SoftSeqAttachReg, tmpPrsOffset; -+ -+ if (IS_PRIVATE_HEADER(p_HdrParams->hdr) -+ || IS_SPECIAL_HEADER(p_HdrParams->hdr)) -+ RETURN_ERROR( -+ MAJOR, E_NOT_SUPPORTED, -+ ("No additional parameters for private or special headers.")); -+ -+ if (p_HdrParams->errDisable) -+ tmpReg |= PRS_HDR_ERROR_DIS; -+ -+ /* Set parser options */ -+ if (p_HdrParams->usePrsOpts) -+ { -+ p_prsOpts = &p_HdrParams->prsOpts; -+ switch (p_HdrParams->hdr) -+ { -+ case (HEADER_TYPE_MPLS): -+ if (p_prsOpts->mplsPrsOptions.labelInterpretationEnable) -+ tmpReg |= PRS_HDR_MPLS_LBL_INTER_EN; -+ hdrNum = GetPrsHdrNum(p_prsOpts->mplsPrsOptions.nextParse); -+ if (hdrNum == ILLEGAL_HDR_NUM) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); -+ Ipv4HdrNum = GetPrsHdrNum(HEADER_TYPE_IPv4); -+ if (hdrNum < Ipv4HdrNum) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("Header must be equal or higher than IPv4")); -+ tmpReg |= ((uint32_t)hdrNum * PRS_HDR_ENTRY_SIZE) -+ << PRS_HDR_MPLS_NEXT_HDR_SHIFT; -+ break; -+ case (HEADER_TYPE_PPPoE): -+ if (p_prsOpts->pppoePrsOptions.enableMTUCheck) -+ tmpReg |= PRS_HDR_PPPOE_MTU_CHECK_EN; -+ break; -+ case (HEADER_TYPE_IPv6): -+ if (p_prsOpts->ipv6PrsOptions.routingHdrEnable) -+ tmpReg |= PRS_HDR_IPV6_ROUTE_HDR_EN; -+ break; -+ case (HEADER_TYPE_TCP): -+ if (p_prsOpts->tcpPrsOptions.padIgnoreChecksum) -+ tmpReg |= PRS_HDR_TCP_PAD_REMOVAL; -+ else -+ tmpReg &= ~PRS_HDR_TCP_PAD_REMOVAL; -+ break; -+ case (HEADER_TYPE_UDP): -+ if (p_prsOpts->udpPrsOptions.padIgnoreChecksum) -+ tmpReg |= PRS_HDR_UDP_PAD_REMOVAL; -+ else -+ tmpReg &= ~PRS_HDR_UDP_PAD_REMOVAL; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Invalid header")); -+ } -+ } -+ -+ /* set software parsing (address is divided in 2 since parser uses 2 byte access. */ -+ if (p_HdrParams->swPrsEnable) -+ { -+ tmpPrsOffset = FmPcdGetSwPrsOffset(p_FmPort->h_FmPcd, p_HdrParams->hdr, -+ p_HdrParams->indexPerHdr); -+ if (tmpPrsOffset == ILLEGAL_BASE) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); -+ tmpReg |= (PRS_HDR_SW_PRS_EN | tmpPrsOffset); -+ } -+ *p_SoftSeqAttachReg = tmpReg; -+ -+ return E_OK; -+} -+ -+static uint32_t GetPortSchemeBindParams( -+ t_Handle h_FmPort, t_FmPcdKgInterModuleBindPortToSchemes *p_SchemeBind) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ uint32_t walking1Mask = 0x80000000, tmp; -+ uint8_t idx = 0; -+ -+ p_SchemeBind->netEnvId = p_FmPort->netEnvId; -+ p_SchemeBind->hardwarePortId = p_FmPort->hardwarePortId; -+ p_SchemeBind->useClsPlan = p_FmPort->useClsPlan; -+ p_SchemeBind->numOfSchemes = 0; -+ tmp = p_FmPort->schemesPerPortVector; -+ if (tmp) -+ { -+ while (tmp) -+ { -+ if (tmp & walking1Mask) -+ { -+ p_SchemeBind->schemesIds[p_SchemeBind->numOfSchemes] = idx; -+ p_SchemeBind->numOfSchemes++; -+ tmp &= ~walking1Mask; -+ } -+ walking1Mask >>= 1; -+ idx++; -+ } -+ } -+ -+ return tmp; -+} -+ -+static void FmPortCheckNApplyMacsec(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ volatile uint32_t *p_BmiCfgReg = NULL; -+ uint32_t macsecEn = BMI_PORT_CFG_EN_MACSEC; -+ uint32_t lcv, walking1Mask = 0x80000000; -+ uint8_t cnt = 0; -+ -+ ASSERT_COND(p_FmPort); -+ ASSERT_COND(p_FmPort->h_FmPcd); -+ ASSERT_COND(!p_FmPort->p_FmPortDriverParam); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX)) -+ return; -+ -+ p_BmiCfgReg = &p_FmPort->port.bmi_regs->rx.fmbm_rcfg; -+ /* get LCV for MACSEC */ -+ if ((lcv = FmPcdGetMacsecLcv(p_FmPort->h_FmPcd, p_FmPort->netEnvId)) -+ != 0) -+ { -+ while (!(lcv & walking1Mask)) -+ { -+ cnt++; -+ walking1Mask >>= 1; -+ } -+ -+ macsecEn |= (uint32_t)cnt << BMI_PORT_CFG_MS_SEL_SHIFT; -+ WRITE_UINT32(*p_BmiCfgReg, GET_UINT32(*p_BmiCfgReg) | macsecEn); -+ } -+} -+ -+static t_Error SetPcd(t_FmPort *p_FmPort, t_FmPortPcdParams *p_PcdParams) -+{ -+ t_Error err = E_OK; -+ uint32_t tmpReg; -+ volatile uint32_t *p_BmiNia = NULL; -+ volatile uint32_t *p_BmiPrsNia = NULL; -+ volatile uint32_t *p_BmiPrsStartOffset = NULL; -+ volatile uint32_t *p_BmiInitPrsResult = NULL; -+ volatile uint32_t *p_BmiCcBase = NULL; -+ uint16_t hdrNum, L3HdrNum, greHdrNum; -+ int i; -+ bool isEmptyClsPlanGrp; -+ uint32_t tmpHxs[FM_PCD_PRS_NUM_OF_HDRS]; -+ uint16_t absoluteProfileId; -+ uint8_t physicalSchemeId; -+ uint32_t ccTreePhysOffset; -+ t_FmPcdKgInterModuleBindPortToSchemes schemeBind; -+ uint32_t initialSwPrs = 0; -+ -+ ASSERT_COND(p_FmPort); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ if (p_FmPort->imEn) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for non-independant mode ports only")); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for Rx and offline parsing ports only")); -+ -+ p_FmPort->netEnvId = FmPcdGetNetEnvId(p_PcdParams->h_NetEnv); -+ -+ p_FmPort->pcdEngines = 0; -+ -+ /* initialize p_FmPort->pcdEngines field in port's structure */ -+ switch (p_PcdParams->pcdSupport) -+ { -+ case (e_FM_PORT_PCD_SUPPORT_NONE): -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("No PCD configuration required if e_FM_PORT_PCD_SUPPORT_NONE selected")); -+ case (e_FM_PORT_PCD_SUPPORT_PRS_ONLY): -+ p_FmPort->pcdEngines |= FM_PCD_PRS; -+ break; -+ case (e_FM_PORT_PCD_SUPPORT_PLCR_ONLY): -+ p_FmPort->pcdEngines |= FM_PCD_PLCR; -+ break; -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_PLCR): -+ p_FmPort->pcdEngines |= FM_PCD_PRS; -+ p_FmPort->pcdEngines |= FM_PCD_PLCR; -+ break; -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_KG): -+ p_FmPort->pcdEngines |= FM_PCD_PRS; -+ p_FmPort->pcdEngines |= FM_PCD_KG; -+ break; -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_CC): -+ p_FmPort->pcdEngines |= FM_PCD_PRS; -+ p_FmPort->pcdEngines |= FM_PCD_CC; -+ p_FmPort->pcdEngines |= FM_PCD_KG; -+ break; -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_CC_AND_PLCR): -+ p_FmPort->pcdEngines |= FM_PCD_PRS; -+ p_FmPort->pcdEngines |= FM_PCD_KG; -+ p_FmPort->pcdEngines |= FM_PCD_CC; -+ p_FmPort->pcdEngines |= FM_PCD_PLCR; -+ break; -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_CC): -+ p_FmPort->pcdEngines |= FM_PCD_PRS; -+ p_FmPort->pcdEngines |= FM_PCD_CC; -+ break; -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_CC_AND_PLCR): -+ p_FmPort->pcdEngines |= FM_PCD_PRS; -+ p_FmPort->pcdEngines |= FM_PCD_CC; -+ p_FmPort->pcdEngines |= FM_PCD_PLCR; -+ break; -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_PLCR): -+ p_FmPort->pcdEngines |= FM_PCD_PRS; -+ p_FmPort->pcdEngines |= FM_PCD_KG; -+ p_FmPort->pcdEngines |= FM_PCD_PLCR; -+ break; -+ case (e_FM_PORT_PCD_SUPPORT_CC_ONLY): -+ p_FmPort->pcdEngines |= FM_PCD_CC; -+ break; -+#ifdef FM_CAPWAP_SUPPORT -+ case (e_FM_PORT_PCD_SUPPORT_CC_AND_KG): -+ p_FmPort->pcdEngines |= FM_PCD_CC; -+ p_FmPort->pcdEngines |= FM_PCD_KG; -+ break; -+ case (e_FM_PORT_PCD_SUPPORT_CC_AND_KG_AND_PLCR): -+ p_FmPort->pcdEngines |= FM_PCD_CC; -+ p_FmPort->pcdEngines |= FM_PCD_KG; -+ p_FmPort->pcdEngines |= FM_PCD_PLCR; -+ break; -+#endif /* FM_CAPWAP_SUPPORT */ -+ -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("invalid pcdSupport")); -+ } -+ -+ if ((p_FmPort->pcdEngines & FM_PCD_PRS) -+ && (p_PcdParams->p_PrsParams->numOfHdrsWithAdditionalParams -+ > FM_PCD_PRS_NUM_OF_HDRS)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("Port parser numOfHdrsWithAdditionalParams may not exceed %d", FM_PCD_PRS_NUM_OF_HDRS)); -+ -+ /* check that parameters exist for each and only each defined engine */ -+ if ((!!(p_FmPort->pcdEngines & FM_PCD_PRS) != !!p_PcdParams->p_PrsParams) -+ || (!!(p_FmPort->pcdEngines & FM_PCD_KG) -+ != !!p_PcdParams->p_KgParams) -+ || (!!(p_FmPort->pcdEngines & FM_PCD_CC) -+ != !!p_PcdParams->p_CcParams)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("PCD initialization structure is not consistent with pcdSupport")); -+ -+ /* get PCD registers pointers */ -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX_10G): -+ case (e_FM_PORT_TYPE_RX): -+ p_BmiNia = &p_FmPort->port.bmi_regs->rx.fmbm_rfne; -+ p_BmiPrsNia = &p_FmPort->port.bmi_regs->rx.fmbm_rfpne; -+ p_BmiPrsStartOffset = &p_FmPort->port.bmi_regs->rx.fmbm_rpso; -+ p_BmiInitPrsResult = &p_FmPort->port.bmi_regs->rx.fmbm_rprai[0]; -+ p_BmiCcBase = &p_FmPort->port.bmi_regs->rx.fmbm_rccb; -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ p_BmiNia = &p_FmPort->port.bmi_regs->oh.fmbm_ofne; -+ p_BmiPrsNia = &p_FmPort->port.bmi_regs->oh.fmbm_ofpne; -+ p_BmiPrsStartOffset = &p_FmPort->port.bmi_regs->oh.fmbm_opso; -+ p_BmiInitPrsResult = &p_FmPort->port.bmi_regs->oh.fmbm_oprai[0]; -+ p_BmiCcBase = &p_FmPort->port.bmi_regs->oh.fmbm_occb; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Invalid port type")); -+ } -+ -+ /* set PCD port parameter */ -+ if (p_FmPort->pcdEngines & FM_PCD_CC) -+ { -+ err = FmPcdCcBindTree(p_FmPort->h_FmPcd, p_PcdParams, -+ p_PcdParams->p_CcParams->h_CcTree, -+ &ccTreePhysOffset, p_FmPort); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ WRITE_UINT32(*p_BmiCcBase, ccTreePhysOffset); -+ p_FmPort->ccTreeId = p_PcdParams->p_CcParams->h_CcTree; -+ } -+ -+ if (p_FmPort->pcdEngines & FM_PCD_KG) -+ { -+ if (p_PcdParams->p_KgParams->numOfSchemes == 0) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("For ports using Keygen, at least one scheme must be bound. ")); -+ -+ err = FmPcdKgSetOrBindToClsPlanGrp(p_FmPort->h_FmPcd, -+ p_FmPort->hardwarePortId, -+ p_FmPort->netEnvId, -+ p_FmPort->optArray, -+ &p_FmPort->clsPlanGrpId, -+ &isEmptyClsPlanGrp); -+ if (err) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("FmPcdKgSetOrBindToClsPlanGrp failed. ")); -+ -+ p_FmPort->useClsPlan = !isEmptyClsPlanGrp; -+ -+ schemeBind.netEnvId = p_FmPort->netEnvId; -+ schemeBind.hardwarePortId = p_FmPort->hardwarePortId; -+ schemeBind.numOfSchemes = p_PcdParams->p_KgParams->numOfSchemes; -+ schemeBind.useClsPlan = p_FmPort->useClsPlan; -+ -+ /* for each scheme */ -+ for (i = 0; i < p_PcdParams->p_KgParams->numOfSchemes; i++) -+ { -+ ASSERT_COND(p_PcdParams->p_KgParams->h_Schemes[i]); -+ physicalSchemeId = FmPcdKgGetSchemeId( -+ p_PcdParams->p_KgParams->h_Schemes[i]); -+ schemeBind.schemesIds[i] = physicalSchemeId; -+ /* build vector */ -+ p_FmPort->schemesPerPortVector |= 1 -+ << (31 - (uint32_t)physicalSchemeId); -+#if (DPAA_VERSION >= 11) -+ /*because of the state that VSPE is defined per port - all PCD path should be according to this requirement -+ if !VSPE - in port, for relevant scheme VSPE can not be set*/ -+ if (!p_FmPort->vspe -+ && FmPcdKgGetVspe((p_PcdParams->p_KgParams->h_Schemes[i]))) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("VSPE is not at port level")); -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ -+ err = FmPcdKgBindPortToSchemes(p_FmPort->h_FmPcd, &schemeBind); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ /***************************/ -+ /* configure NIA after BMI */ -+ /***************************/ -+ /* rfne may contain FDCS bits, so first we read them. */ -+ p_FmPort->savedBmiNia = GET_UINT32(*p_BmiNia) & BMI_RFNE_FDCS_MASK; -+ -+ /* If policer is used directly after BMI or PRS */ -+ if ((p_FmPort->pcdEngines & FM_PCD_PLCR) -+ && ((p_PcdParams->pcdSupport == e_FM_PORT_PCD_SUPPORT_PLCR_ONLY) -+ || (p_PcdParams->pcdSupport -+ == e_FM_PORT_PCD_SUPPORT_PRS_AND_PLCR))) -+ { -+ if (!p_PcdParams->p_PlcrParams->h_Profile) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("Profile should be initialized")); -+ -+ absoluteProfileId = (uint16_t)FmPcdPlcrProfileGetAbsoluteId( -+ p_PcdParams->p_PlcrParams->h_Profile); -+ -+ if (!FmPcdPlcrIsProfileValid(p_FmPort->h_FmPcd, absoluteProfileId)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("Private port profile not valid.")); -+ -+ tmpReg = (uint32_t)(absoluteProfileId | NIA_PLCR_ABSOLUTE); -+ -+ if (p_FmPort->pcdEngines & FM_PCD_PRS) /* e_FM_PCD_SUPPORT_PRS_AND_PLCR */ -+ /* update BMI HPNIA */ -+ WRITE_UINT32(*p_BmiPrsNia, (uint32_t)(NIA_ENG_PLCR | tmpReg)); -+ else -+ /* e_FM_PCD_SUPPORT_PLCR_ONLY */ -+ /* update BMI NIA */ -+ p_FmPort->savedBmiNia |= (uint32_t)(NIA_ENG_PLCR); -+ } -+ -+ /* if CC is used directly after BMI */ -+ if ((p_PcdParams->pcdSupport == e_FM_PORT_PCD_SUPPORT_CC_ONLY) -+#ifdef FM_CAPWAP_SUPPORT -+ || (p_PcdParams->pcdSupport == e_FM_PORT_PCD_SUPPORT_CC_AND_KG) -+ || (p_PcdParams->pcdSupport == e_FM_PORT_PCD_SUPPORT_CC_AND_KG_AND_PLCR) -+#endif /* FM_CAPWAP_SUPPORT */ -+ ) -+ { -+ if (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_OPERATION, -+ ("e_FM_PORT_PCD_SUPPORT_CC_xx available for offline parsing ports only")); -+ p_FmPort->savedBmiNia |= (uint32_t)(NIA_ENG_FM_CTL | NIA_FM_CTL_AC_CC); -+ /* check that prs start offset == RIM[FOF] */ -+ } -+ -+ if (p_FmPort->pcdEngines & FM_PCD_PRS) -+ { -+ ASSERT_COND(p_PcdParams->p_PrsParams); -+#if (DPAA_VERSION >= 11) -+ if (p_PcdParams->p_PrsParams->firstPrsHdr == HEADER_TYPE_CAPWAP) -+ hdrNum = OFFLOAD_SW_PATCH_CAPWAP_LABEL; -+ else -+ { -+#endif /* (DPAA_VERSION >= 11) */ -+ /* if PRS is used it is always first */ -+ hdrNum = GetPrsHdrNum(p_PcdParams->p_PrsParams->firstPrsHdr); -+ if (hdrNum == ILLEGAL_HDR_NUM) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Unsupported header.")); -+#if (DPAA_VERSION >= 11) -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ p_FmPort->savedBmiNia |= (uint32_t)(NIA_ENG_PRS | (uint32_t)(hdrNum)); -+ /* set after parser NIA */ -+ tmpReg = 0; -+ switch (p_PcdParams->pcdSupport) -+ { -+ case (e_FM_PORT_PCD_SUPPORT_PRS_ONLY): -+ WRITE_UINT32(*p_BmiPrsNia, -+ GET_NIA_BMI_AC_ENQ_FRAME(p_FmPort->h_FmPcd)); -+ break; -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_CC): -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_CC_AND_PLCR): -+ tmpReg = NIA_KG_CC_EN; -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_KG): -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_PLCR): -+ if (p_PcdParams->p_KgParams->directScheme) -+ { -+ physicalSchemeId = FmPcdKgGetSchemeId( -+ p_PcdParams->p_KgParams->h_DirectScheme); -+ /* check that this scheme was bound to this port */ -+ for (i = 0; i < p_PcdParams->p_KgParams->numOfSchemes; i++) -+ if (p_PcdParams->p_KgParams->h_DirectScheme -+ == p_PcdParams->p_KgParams->h_Schemes[i]) -+ break; -+ if (i == p_PcdParams->p_KgParams->numOfSchemes) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("Direct scheme is not one of the port selected schemes.")); -+ tmpReg |= (uint32_t)(NIA_KG_DIRECT | physicalSchemeId); -+ } -+ WRITE_UINT32(*p_BmiPrsNia, NIA_ENG_KG | tmpReg); -+ break; -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_CC): -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_CC_AND_PLCR): -+ WRITE_UINT32(*p_BmiPrsNia, -+ (uint32_t)(NIA_ENG_FM_CTL | NIA_FM_CTL_AC_CC)); -+ break; -+ case (e_FM_PORT_PCD_SUPPORT_PRS_AND_PLCR): -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Invalid PCD support")); -+ } -+ -+ /* set start parsing offset */ -+ WRITE_UINT32(*p_BmiPrsStartOffset, -+ p_PcdParams->p_PrsParams->parsingOffset); -+ -+ /************************************/ -+ /* Parser port parameters */ -+ /************************************/ -+ /* stop before configuring */ -+ WRITE_UINT32(p_FmPort->p_FmPortPrsRegs->pcac, PRS_CAC_STOP); -+ /* wait for parser to be in idle state */ -+ while (GET_UINT32(p_FmPort->p_FmPortPrsRegs->pcac) & PRS_CAC_ACTIVE) -+ ; -+ -+ /* set soft seq attachment register */ -+ memset(tmpHxs, 0, FM_PCD_PRS_NUM_OF_HDRS * sizeof(uint32_t)); -+ -+ /* set protocol options */ -+ for (i = 0; p_FmPort->optArray[i]; i++) -+ switch (p_FmPort->optArray[i]) -+ { -+ case (ETH_BROADCAST): -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_ETH); -+ tmpHxs[hdrNum] |= (i + 1) << PRS_HDR_ETH_BC_SHIFT; -+ break; -+ case (ETH_MULTICAST): -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_ETH); -+ tmpHxs[hdrNum] |= (i + 1) << PRS_HDR_ETH_MC_SHIFT; -+ break; -+ case (VLAN_STACKED): -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_VLAN); -+ tmpHxs[hdrNum] |= (i + 1) << PRS_HDR_VLAN_STACKED_SHIFT; -+ break; -+ case (MPLS_STACKED): -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_MPLS); -+ tmpHxs[hdrNum] |= (i + 1) << PRS_HDR_MPLS_STACKED_SHIFT; -+ break; -+ case (IPV4_BROADCAST_1): -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_IPv4); -+ tmpHxs[hdrNum] |= (i + 1) << PRS_HDR_IPV4_1_BC_SHIFT; -+ break; -+ case (IPV4_MULTICAST_1): -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_IPv4); -+ tmpHxs[hdrNum] |= (i + 1) << PRS_HDR_IPV4_1_MC_SHIFT; -+ break; -+ case (IPV4_UNICAST_2): -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_IPv4); -+ tmpHxs[hdrNum] |= (i + 1) << PRS_HDR_IPV4_2_UC_SHIFT; -+ break; -+ case (IPV4_MULTICAST_BROADCAST_2): -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_IPv4); -+ tmpHxs[hdrNum] |= (i + 1) << PRS_HDR_IPV4_2_MC_BC_SHIFT; -+ break; -+ case (IPV6_MULTICAST_1): -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_IPv6); -+ tmpHxs[hdrNum] |= (i + 1) << PRS_HDR_IPV6_1_MC_SHIFT; -+ break; -+ case (IPV6_UNICAST_2): -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_IPv6); -+ tmpHxs[hdrNum] |= (i + 1) << PRS_HDR_IPV6_2_UC_SHIFT; -+ break; -+ case (IPV6_MULTICAST_2): -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_IPv6); -+ tmpHxs[hdrNum] |= (i + 1) << PRS_HDR_IPV6_2_MC_SHIFT; -+ break; -+ } -+ -+ if (FmPcdNetEnvIsHdrExist(p_FmPort->h_FmPcd, p_FmPort->netEnvId, -+ HEADER_TYPE_UDP_ENCAP_ESP)) -+ { -+ if (p_PcdParams->p_PrsParams->numOfHdrsWithAdditionalParams == FM_PCD_PRS_NUM_OF_HDRS) -+ RETURN_ERROR( -+ MINOR, E_INVALID_VALUE, -+ ("If HEADER_TYPE_UDP_ENCAP_ESP is used, numOfHdrsWithAdditionalParams may be up to FM_PCD_PRS_NUM_OF_HDRS - 1")); -+ -+ p_PcdParams->p_PrsParams->additionalParams[p_PcdParams->p_PrsParams->numOfHdrsWithAdditionalParams].hdr = -+ HEADER_TYPE_UDP; -+ p_PcdParams->p_PrsParams->additionalParams[p_PcdParams->p_PrsParams->numOfHdrsWithAdditionalParams].swPrsEnable = -+ TRUE; -+ p_PcdParams->p_PrsParams->numOfHdrsWithAdditionalParams++; -+ } -+ -+ /* set MPLS default next header - HW reset workaround */ -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_MPLS); -+ tmpHxs[hdrNum] |= PRS_HDR_MPLS_LBL_INTER_EN; -+ L3HdrNum = GetPrsHdrNum(HEADER_TYPE_USER_DEFINED_L3); -+ tmpHxs[hdrNum] |= (uint32_t)L3HdrNum << PRS_HDR_MPLS_NEXT_HDR_SHIFT; -+ -+ /* for GRE, disable errors */ -+ greHdrNum = GetPrsHdrNum(HEADER_TYPE_GRE); -+ tmpHxs[greHdrNum] |= PRS_HDR_ERROR_DIS; -+ -+ /* For UDP remove PAD from L4 checksum calculation */ -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_UDP); -+ tmpHxs[hdrNum] |= PRS_HDR_UDP_PAD_REMOVAL; -+ /* For TCP remove PAD from L4 checksum calculation */ -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_TCP); -+ tmpHxs[hdrNum] |= PRS_HDR_TCP_PAD_REMOVAL; -+ -+ /* config additional params for specific headers */ -+ for (i = 0; i < p_PcdParams->p_PrsParams->numOfHdrsWithAdditionalParams; -+ i++) -+ { -+ /* case for using sw parser as the initial NIA address, before -+ * HW parsing -+ */ -+ if ((p_PcdParams->p_PrsParams->additionalParams[i].hdr == HEADER_TYPE_NONE) && -+ p_PcdParams->p_PrsParams->additionalParams[i].swPrsEnable) -+ { -+ initialSwPrs = FmPcdGetSwPrsOffset(p_FmPort->h_FmPcd, HEADER_TYPE_NONE, -+ p_PcdParams->p_PrsParams->additionalParams[i].indexPerHdr); -+ if (initialSwPrs == ILLEGAL_BASE) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); -+ -+ /* clear parser first HXS */ -+ p_FmPort->savedBmiNia &= ~BMI_RFNE_HXS_MASK; /* 0x000000FF */ -+ /* rewrite with soft parser start */ -+ p_FmPort->savedBmiNia |= initialSwPrs; -+ continue; -+ } -+ -+ hdrNum = -+ GetPrsHdrNum(p_PcdParams->p_PrsParams->additionalParams[i].hdr); -+ if (hdrNum == ILLEGAL_HDR_NUM) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); -+ if (hdrNum == NO_HDR_NUM) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("Private headers may not use additional parameters")); -+ -+ err = AdditionalPrsParams( -+ p_FmPort, &p_PcdParams->p_PrsParams->additionalParams[i], -+ &tmpHxs[hdrNum]); -+ if (err) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); -+ } -+ -+ /* Check if ip-reassembly port - need to link sw-parser code */ -+ if (p_FmPort->h_IpReassemblyManip) -+ { -+ /* link to sw parser code for IP Frag - only if no other code is applied. */ -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_IPv4); -+ if (!(tmpHxs[hdrNum] & PRS_HDR_SW_PRS_EN)) -+ tmpHxs[hdrNum] |= (PRS_HDR_SW_PRS_EN | OFFLOAD_SW_PATCH_IPv4_IPR_LABEL); -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_IPv6); -+ if (!(tmpHxs[hdrNum] & PRS_HDR_SW_PRS_EN)) -+ tmpHxs[hdrNum] |= (PRS_HDR_SW_PRS_EN | OFFLOAD_SW_PATCH_IPv6_IPR_LABEL); -+ } else { -+ if (FmPcdNetEnvIsHdrExist(p_FmPort->h_FmPcd, p_FmPort->netEnvId, HEADER_TYPE_UDP_LITE)) -+ { -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_IPv6); -+ if (!(tmpHxs[hdrNum] & PRS_HDR_SW_PRS_EN)) -+ tmpHxs[hdrNum] |= (PRS_HDR_SW_PRS_EN | OFFLOAD_SW_PATCH_IPv6_IPF_LABEL); -+ } else if ((FmPcdIsAdvancedOffloadSupported(p_FmPort->h_FmPcd) -+ && (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING))) -+ { -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_IPv6); -+ if (!(tmpHxs[hdrNum] & PRS_HDR_SW_PRS_EN)) -+ tmpHxs[hdrNum] |= (PRS_HDR_SW_PRS_EN | OFFLOAD_SW_PATCH_IPv6_IPF_LABEL); -+ } -+ } -+ -+#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+ if (FmPcdNetEnvIsHdrExist(p_FmPort->h_FmPcd, p_FmPort->netEnvId, -+ HEADER_TYPE_UDP_LITE)) -+ { -+ /* link to sw parser code for udp lite - only if no other code is applied. */ -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_IPv6); -+ if (!(tmpHxs[hdrNum] & PRS_HDR_SW_PRS_EN)) -+ tmpHxs[hdrNum] |= (PRS_HDR_SW_PRS_EN | UDP_LITE_SW_PATCH_LABEL); -+ } -+#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+ for (i = 0; i < FM_PCD_PRS_NUM_OF_HDRS; i++) -+ { -+ /* For all header set LCV as taken from netEnv*/ -+ WRITE_UINT32( -+ p_FmPort->p_FmPortPrsRegs->hdrs[i].lcv, -+ FmPcdGetLcv(p_FmPort->h_FmPcd, p_FmPort->netEnvId, (uint8_t)i)); -+ /* set HXS register according to default+Additional params+protocol options */ -+ WRITE_UINT32(p_FmPort->p_FmPortPrsRegs->hdrs[i].softSeqAttach, -+ tmpHxs[i]); -+ } -+ -+ /* set tpid. */ -+ tmpReg = PRS_TPID_DFLT; -+ if (p_PcdParams->p_PrsParams->setVlanTpid1) -+ { -+ tmpReg &= PRS_TPID2_MASK; -+ tmpReg |= (uint32_t)p_PcdParams->p_PrsParams->vlanTpid1 -+ << PRS_PCTPID_SHIFT; -+ } -+ if (p_PcdParams->p_PrsParams->setVlanTpid2) -+ { -+ tmpReg &= PRS_TPID1_MASK; -+ tmpReg |= (uint32_t)p_PcdParams->p_PrsParams->vlanTpid2; -+ }WRITE_UINT32(p_FmPort->p_FmPortPrsRegs->pctpid, tmpReg); -+ -+ /* enable parser */ -+ WRITE_UINT32(p_FmPort->p_FmPortPrsRegs->pcac, 0); -+ -+ if (p_PcdParams->p_PrsParams->prsResultPrivateInfo) -+ p_FmPort->privateInfo = -+ p_PcdParams->p_PrsParams->prsResultPrivateInfo; -+ -+ } /* end parser */ -+ else { -+ if (FmPcdIsAdvancedOffloadSupported(p_FmPort->h_FmPcd) -+ && (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ { -+ hdrNum = GetPrsHdrNum(HEADER_TYPE_IPv6); -+ WRITE_UINT32(p_FmPort->p_FmPortPrsRegs->hdrs[hdrNum].softSeqAttach, -+ (PRS_HDR_SW_PRS_EN | OFFLOAD_SW_PATCH_IPv6_IPF_LABEL)); -+ } -+ -+ WRITE_UINT32(*p_BmiPrsStartOffset, 0); -+ -+ p_FmPort->privateInfo = 0; -+ } -+ -+ FmPortCheckNApplyMacsec(p_FmPort); -+ -+ WRITE_UINT32( -+ *p_BmiPrsStartOffset, -+ GET_UINT32(*p_BmiPrsStartOffset) + p_FmPort->internalBufferOffset); -+ -+ /* set initial parser result - used for all engines */ -+ for (i = 0; i < FM_PORT_PRS_RESULT_NUM_OF_WORDS; i++) -+ { -+ if (!i) -+ WRITE_UINT32( -+ *(p_BmiInitPrsResult), -+ (uint32_t)(((uint32_t)p_FmPort->privateInfo << BMI_PR_PORTID_SHIFT) | BMI_PRS_RESULT_HIGH)); -+ else -+ { -+ if (i < FM_PORT_PRS_RESULT_NUM_OF_WORDS / 2) -+ WRITE_UINT32(*(p_BmiInitPrsResult+i), BMI_PRS_RESULT_HIGH); -+ else -+ WRITE_UINT32(*(p_BmiInitPrsResult+i), BMI_PRS_RESULT_LOW); -+ } -+ } -+ -+ return E_OK; -+} -+ -+static t_Error DeletePcd(t_FmPort *p_FmPort) -+{ -+ t_Error err = E_OK; -+ volatile uint32_t *p_BmiNia = NULL; -+ volatile uint32_t *p_BmiPrsStartOffset = NULL; -+ -+ ASSERT_COND(p_FmPort); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ if (p_FmPort->imEn) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for non-independant mode ports only")); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("available for Rx and offline parsing ports only")); -+ -+ if (!p_FmPort->pcdEngines) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, ("called for non PCD port")); -+ -+ /* get PCD registers pointers */ -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX_10G): -+ case (e_FM_PORT_TYPE_RX): -+ p_BmiNia = &p_FmPort->port.bmi_regs->rx.fmbm_rfne; -+ p_BmiPrsStartOffset = &p_FmPort->port.bmi_regs->rx.fmbm_rpso; -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ p_BmiNia = &p_FmPort->port.bmi_regs->oh.fmbm_ofne; -+ p_BmiPrsStartOffset = &p_FmPort->port.bmi_regs->oh.fmbm_opso; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Invalid port type")); -+ } -+ -+ if ((GET_UINT32(*p_BmiNia) & GET_NO_PCD_NIA_BMI_AC_ENQ_FRAME()) -+ != GET_NO_PCD_NIA_BMI_AC_ENQ_FRAME()) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("port has to be detached previousely")); -+ -+ WRITE_UINT32(*p_BmiPrsStartOffset, 0); -+ -+ /* "cut" PCD out of the port's flow - go to BMI */ -+ /* WRITE_UINT32(*p_BmiNia, (p_FmPort->savedBmiNia & BMI_RFNE_FDCS_MASK) | (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME)); */ -+ -+ if (p_FmPort->pcdEngines & FM_PCD_PRS) -+ { -+ /* stop parser */ -+ WRITE_UINT32(p_FmPort->p_FmPortPrsRegs->pcac, PRS_CAC_STOP); -+ /* wait for parser to be in idle state */ -+ while (GET_UINT32(p_FmPort->p_FmPortPrsRegs->pcac) & PRS_CAC_ACTIVE) -+ ; -+ } -+ -+ if (p_FmPort->pcdEngines & FM_PCD_KG) -+ { -+ t_FmPcdKgInterModuleBindPortToSchemes schemeBind; -+ -+ /* unbind all schemes */ -+ p_FmPort->schemesPerPortVector = GetPortSchemeBindParams(p_FmPort, -+ &schemeBind); -+ -+ err = FmPcdKgUnbindPortToSchemes(p_FmPort->h_FmPcd, &schemeBind); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ err = FmPcdKgDeleteOrUnbindPortToClsPlanGrp(p_FmPort->h_FmPcd, -+ p_FmPort->hardwarePortId, -+ p_FmPort->clsPlanGrpId); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ p_FmPort->useClsPlan = FALSE; -+ } -+ -+ if (p_FmPort->pcdEngines & FM_PCD_CC) -+ { -+ /* unbind - we need to get the treeId too */ -+ err = FmPcdCcUnbindTree(p_FmPort->h_FmPcd, p_FmPort->ccTreeId); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ p_FmPort->pcdEngines = 0; -+ -+ return E_OK; -+} -+ -+static t_Error AttachPCD(t_FmPort *p_FmPort) -+{ -+ volatile uint32_t *p_BmiNia = NULL; -+ -+ ASSERT_COND(p_FmPort); -+ -+ /* get PCD registers pointers */ -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ p_BmiNia = &p_FmPort->port.bmi_regs->oh.fmbm_ofne; -+ else -+ p_BmiNia = &p_FmPort->port.bmi_regs->rx.fmbm_rfne; -+ -+ /* check that current NIA is BMI to BMI */ -+ if ((GET_UINT32(*p_BmiNia) & ~BMI_RFNE_FDCS_MASK) -+ != GET_NO_PCD_NIA_BMI_AC_ENQ_FRAME()) -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("may be called only for ports in BMI-to-BMI state.")); -+ -+ if (p_FmPort->requiredAction & UPDATE_FMFP_PRC_WITH_ONE_RISC_ONLY) -+ if (FmSetNumOfRiscsPerPort(p_FmPort->h_Fm, p_FmPort->hardwarePortId, 1, -+ p_FmPort->orFmanCtrl) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ -+ if (p_FmPort->requiredAction & UPDATE_NIA_CMNE) -+ { -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ WRITE_UINT32(p_FmPort->port.bmi_regs->oh.fmbm_ocmne, -+ p_FmPort->savedBmiCmne); -+ else -+ WRITE_UINT32(p_FmPort->port.bmi_regs->rx.fmbm_rcmne, -+ p_FmPort->savedBmiCmne); -+ } -+ -+ if (p_FmPort->requiredAction & UPDATE_NIA_PNEN) -+ WRITE_UINT32(p_FmPort->p_FmPortQmiRegs->fmqm_pnen, -+ p_FmPort->savedQmiPnen); -+ -+ if (p_FmPort->requiredAction & UPDATE_NIA_FENE) -+ { -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ WRITE_UINT32(p_FmPort->port.bmi_regs->oh.fmbm_ofene, -+ p_FmPort->savedBmiFene); -+ else -+ WRITE_UINT32(p_FmPort->port.bmi_regs->rx.fmbm_rfene, -+ p_FmPort->savedBmiFene); -+ } -+ -+ if (p_FmPort->requiredAction & UPDATE_NIA_FPNE) -+ { -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ WRITE_UINT32(p_FmPort->port.bmi_regs->oh.fmbm_ofpne, -+ p_FmPort->savedBmiFpne); -+ else -+ WRITE_UINT32(p_FmPort->port.bmi_regs->rx.fmbm_rfpne, -+ p_FmPort->savedBmiFpne); -+ } -+ -+ if (p_FmPort->requiredAction & UPDATE_OFP_DPTE) -+ { -+ ASSERT_COND(p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING); -+ -+ WRITE_UINT32(p_FmPort->port.bmi_regs->oh.fmbm_ofp, -+ p_FmPort->savedBmiOfp); -+ } -+ -+ WRITE_UINT32(*p_BmiNia, p_FmPort->savedBmiNia); -+ -+ if (p_FmPort->requiredAction & UPDATE_NIA_PNDN) -+ { -+ p_FmPort->origNonRxQmiRegsPndn = -+ GET_UINT32(p_FmPort->port.qmi_regs->fmqm_pndn); -+ WRITE_UINT32(p_FmPort->port.qmi_regs->fmqm_pndn, -+ p_FmPort->savedNonRxQmiRegsPndn); -+ } -+ -+ return E_OK; -+} -+ -+static t_Error DetachPCD(t_FmPort *p_FmPort) -+{ -+ volatile uint32_t *p_BmiNia = NULL; -+ -+ ASSERT_COND(p_FmPort); -+ -+ /* get PCD registers pointers */ -+ if (p_FmPort->requiredAction & UPDATE_NIA_PNDN) -+ WRITE_UINT32(p_FmPort->port.qmi_regs->fmqm_pndn, -+ p_FmPort->origNonRxQmiRegsPndn); -+ -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ p_BmiNia = &p_FmPort->port.bmi_regs->oh.fmbm_ofne; -+ else -+ p_BmiNia = &p_FmPort->port.bmi_regs->rx.fmbm_rfne; -+ -+ WRITE_UINT32( -+ *p_BmiNia, -+ (p_FmPort->savedBmiNia & BMI_RFNE_FDCS_MASK) | GET_NO_PCD_NIA_BMI_AC_ENQ_FRAME()); -+ -+ if (FmPcdGetHcHandle(p_FmPort->h_FmPcd)) -+ FmPcdHcSync(p_FmPort->h_FmPcd); -+ -+ if (p_FmPort->requiredAction & UPDATE_NIA_FENE) -+ { -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ WRITE_UINT32(p_FmPort->port.bmi_regs->oh.fmbm_ofene, -+ NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR); -+ else -+ WRITE_UINT32(p_FmPort->port.bmi_regs->rx.fmbm_rfene, -+ NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR); -+ } -+ -+ if (p_FmPort->requiredAction & UPDATE_NIA_PNEN) -+ WRITE_UINT32(p_FmPort->port.qmi_regs->fmqm_pnen, -+ NIA_ENG_BMI | NIA_BMI_AC_RELEASE); -+ -+ if (p_FmPort->requiredAction & UPDATE_FMFP_PRC_WITH_ONE_RISC_ONLY) -+ if (FmSetNumOfRiscsPerPort(p_FmPort->h_Fm, p_FmPort->hardwarePortId, 2, -+ p_FmPort->orFmanCtrl) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ -+ p_FmPort->requiredAction = 0; -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+/* Inter-module API routines */ -+/*****************************************************************************/ -+void FmPortSetMacsecCmd(t_Handle h_FmPort, uint8_t dfltSci) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ volatile uint32_t *p_BmiCfgReg = NULL; -+ uint32_t tmpReg; -+ -+ SANITY_CHECK_RETURN(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN(p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_TX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_TX)) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_OPERATION, ("The routine is relevant for Tx ports only")); -+ return; -+ } -+ -+ p_BmiCfgReg = &p_FmPort->port.bmi_regs->tx.fmbm_tfca; -+ tmpReg = GET_UINT32(*p_BmiCfgReg) & ~BMI_CMD_ATTR_MACCMD_MASK; -+ tmpReg |= BMI_CMD_ATTR_MACCMD_SECURED; -+ tmpReg |= (((uint32_t)dfltSci << BMI_CMD_ATTR_MACCMD_SC_SHIFT) -+ & BMI_CMD_ATTR_MACCMD_SC_MASK); -+ -+ WRITE_UINT32(*p_BmiCfgReg, tmpReg); -+} -+ -+uint8_t FmPortGetNetEnvId(t_Handle h_FmPort) -+{ -+ return ((t_FmPort*)h_FmPort)->netEnvId; -+} -+ -+uint8_t FmPortGetHardwarePortId(t_Handle h_FmPort) -+{ -+ return ((t_FmPort*)h_FmPort)->hardwarePortId; -+} -+ -+uint32_t FmPortGetPcdEngines(t_Handle h_FmPort) -+{ -+ return ((t_FmPort*)h_FmPort)->pcdEngines; -+} -+ -+#if (DPAA_VERSION >= 11) -+t_Error FmPortSetGprFunc(t_Handle h_FmPort, e_FmPortGprFuncType gprFunc, -+ void **p_Value) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ uint32_t muramPageOffset; -+ -+ ASSERT_COND(p_FmPort); -+ ASSERT_COND(p_Value); -+ -+ if (p_FmPort->gprFunc != e_FM_PORT_GPR_EMPTY) -+ { -+ if (p_FmPort->gprFunc != gprFunc) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("gpr was assigned with different func")); -+ } -+ else -+ { -+ switch (gprFunc) -+ { -+ case (e_FM_PORT_GPR_MURAM_PAGE): -+ p_FmPort->p_ParamsPage = FM_MURAM_AllocMem(p_FmPort->h_FmMuram, -+ 256, 8); -+ if (!p_FmPort->p_ParamsPage) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM alloc for page")); -+ -+ IOMemSet32(p_FmPort->p_ParamsPage, 0, 256); -+ muramPageOffset = -+ (uint32_t)(XX_VirtToPhys(p_FmPort->p_ParamsPage) -+ - p_FmPort->fmMuramPhysBaseAddr); -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX_10G): -+ case (e_FM_PORT_TYPE_RX): -+ WRITE_UINT32( -+ p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rgpr, -+ muramPageOffset); -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ WRITE_UINT32( -+ p_FmPort->p_FmPortBmiRegs->ohPortBmiRegs.fmbm_ogpr, -+ muramPageOffset); -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("Invalid port type")); -+ } -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ p_FmPort->gprFunc = gprFunc; -+ } -+ -+ switch (p_FmPort->gprFunc) -+ { -+ case (e_FM_PORT_GPR_MURAM_PAGE): -+ *p_Value = p_FmPort->p_ParamsPage; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ -+ return E_OK; -+} -+#endif /* (DPAA_VERSION >= 11) */ -+ -+t_Error FmPortGetSetCcParams(t_Handle h_FmPort, -+ t_FmPortGetSetCcParams *p_CcParams) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ int tmpInt; -+ volatile uint32_t *p_BmiPrsStartOffset = NULL; -+ -+ /* this function called from Cc for pass and receive parameters port params between CC and PORT*/ -+ -+ if ((p_CcParams->getCcParams.type & OFFSET_OF_PR) -+ && (p_FmPort->bufferOffsets.prsResultOffset != ILLEGAL_BASE)) -+ { -+ p_CcParams->getCcParams.prOffset = -+ (uint8_t)p_FmPort->bufferOffsets.prsResultOffset; -+ p_CcParams->getCcParams.type &= ~OFFSET_OF_PR; -+ } -+ if (p_CcParams->getCcParams.type & HW_PORT_ID) -+ { -+ p_CcParams->getCcParams.hardwarePortId = -+ (uint8_t)p_FmPort->hardwarePortId; -+ p_CcParams->getCcParams.type &= ~HW_PORT_ID; -+ } -+ if ((p_CcParams->getCcParams.type & OFFSET_OF_DATA) -+ && (p_FmPort->bufferOffsets.dataOffset != ILLEGAL_BASE)) -+ { -+ p_CcParams->getCcParams.dataOffset = -+ (uint16_t)p_FmPort->bufferOffsets.dataOffset; -+ p_CcParams->getCcParams.type &= ~OFFSET_OF_DATA; -+ } -+ if (p_CcParams->getCcParams.type & NUM_OF_TASKS) -+ { -+ p_CcParams->getCcParams.numOfTasks = (uint8_t)p_FmPort->tasks.num; -+ p_CcParams->getCcParams.type &= ~NUM_OF_TASKS; -+ } -+ if (p_CcParams->getCcParams.type & NUM_OF_EXTRA_TASKS) -+ { -+ p_CcParams->getCcParams.numOfExtraTasks = -+ (uint8_t)p_FmPort->tasks.extra; -+ p_CcParams->getCcParams.type &= ~NUM_OF_EXTRA_TASKS; -+ } -+ if (p_CcParams->getCcParams.type & FM_REV) -+ { -+ p_CcParams->getCcParams.revInfo.majorRev = p_FmPort->fmRevInfo.majorRev; -+ p_CcParams->getCcParams.revInfo.minorRev = p_FmPort->fmRevInfo.minorRev; -+ p_CcParams->getCcParams.type &= ~FM_REV; -+ } -+ if (p_CcParams->getCcParams.type & DISCARD_MASK) -+ { -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ p_CcParams->getCcParams.discardMask = -+ GET_UINT32(p_FmPort->p_FmPortBmiRegs->ohPortBmiRegs.fmbm_ofsdm); -+ else -+ p_CcParams->getCcParams.discardMask = -+ GET_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfsdm); -+ p_CcParams->getCcParams.type &= ~DISCARD_MASK; -+ } -+ if (p_CcParams->getCcParams.type & MANIP_EXTRA_SPACE) -+ { -+ p_CcParams->getCcParams.internalBufferOffset = -+ p_FmPort->internalBufferOffset; -+ p_CcParams->getCcParams.type &= ~MANIP_EXTRA_SPACE; -+ } -+ if (p_CcParams->getCcParams.type & GET_NIA_FPNE) -+ { -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ p_CcParams->getCcParams.nia = -+ GET_UINT32(p_FmPort->port.bmi_regs->oh.fmbm_ofpne); -+ else -+ p_CcParams->getCcParams.nia = -+ GET_UINT32(p_FmPort->port.bmi_regs->rx.fmbm_rfpne); -+ p_CcParams->getCcParams.type &= ~GET_NIA_FPNE; -+ } -+ if (p_CcParams->getCcParams.type & GET_NIA_PNDN) -+ { -+ if (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Invalid port type")); -+ p_CcParams->getCcParams.nia = -+ GET_UINT32(p_FmPort->p_FmPortQmiRegs->nonRxQmiRegs.fmqm_pndn); -+ p_CcParams->getCcParams.type &= ~GET_NIA_PNDN; -+ } -+ -+ if ((p_CcParams->setCcParams.type & UPDATE_FMFP_PRC_WITH_ONE_RISC_ONLY) -+ && !(p_FmPort->requiredAction & UPDATE_FMFP_PRC_WITH_ONE_RISC_ONLY)) -+ { -+ p_FmPort->requiredAction |= UPDATE_FMFP_PRC_WITH_ONE_RISC_ONLY; -+ p_FmPort->orFmanCtrl = p_CcParams->setCcParams.orFmanCtrl; -+ } -+ -+ if ((p_CcParams->setCcParams.type & UPDATE_NIA_PNEN) -+ && !(p_FmPort->requiredAction & UPDATE_NIA_PNEN)) -+ { -+ p_FmPort->savedQmiPnen = p_CcParams->setCcParams.nia; -+ p_FmPort->requiredAction |= UPDATE_NIA_PNEN; -+ } -+ else -+ if (p_CcParams->setCcParams.type & UPDATE_NIA_PNEN) -+ { -+ if (p_FmPort->savedQmiPnen != p_CcParams->setCcParams.nia) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("PNEN was defined previously different")); -+ } -+ -+ if ((p_CcParams->setCcParams.type & UPDATE_NIA_PNDN) -+ && !(p_FmPort->requiredAction & UPDATE_NIA_PNDN)) -+ { -+ p_FmPort->savedNonRxQmiRegsPndn = p_CcParams->setCcParams.nia; -+ p_FmPort->requiredAction |= UPDATE_NIA_PNDN; -+ } -+ else -+ if (p_CcParams->setCcParams.type & UPDATE_NIA_PNDN) -+ { -+ if (p_FmPort->savedNonRxQmiRegsPndn != p_CcParams->setCcParams.nia) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("PNDN was defined previously different")); -+ } -+ -+ if ((p_CcParams->setCcParams.type & UPDATE_NIA_FENE) -+ && (p_CcParams->setCcParams.overwrite -+ || !(p_FmPort->requiredAction & UPDATE_NIA_FENE))) -+ { -+ p_FmPort->savedBmiFene = p_CcParams->setCcParams.nia; -+ p_FmPort->requiredAction |= UPDATE_NIA_FENE; -+ } -+ else -+ if (p_CcParams->setCcParams.type & UPDATE_NIA_FENE) -+ { -+ if (p_FmPort->savedBmiFene != p_CcParams->setCcParams.nia) -+ RETURN_ERROR( MAJOR, E_INVALID_STATE, -+ ("xFENE was defined previously different")); -+ } -+ -+ if ((p_CcParams->setCcParams.type & UPDATE_NIA_FPNE) -+ && !(p_FmPort->requiredAction & UPDATE_NIA_FPNE)) -+ { -+ p_FmPort->savedBmiFpne = p_CcParams->setCcParams.nia; -+ p_FmPort->requiredAction |= UPDATE_NIA_FPNE; -+ } -+ else -+ if (p_CcParams->setCcParams.type & UPDATE_NIA_FPNE) -+ { -+ if (p_FmPort->savedBmiFpne != p_CcParams->setCcParams.nia) -+ RETURN_ERROR( MAJOR, E_INVALID_STATE, -+ ("xFPNE was defined previously different")); -+ } -+ -+ if ((p_CcParams->setCcParams.type & UPDATE_NIA_CMNE) -+ && !(p_FmPort->requiredAction & UPDATE_NIA_CMNE)) -+ { -+ p_FmPort->savedBmiCmne = p_CcParams->setCcParams.nia; -+ p_FmPort->requiredAction |= UPDATE_NIA_CMNE; -+ } -+ else -+ if (p_CcParams->setCcParams.type & UPDATE_NIA_CMNE) -+ { -+ if (p_FmPort->savedBmiCmne != p_CcParams->setCcParams.nia) -+ RETURN_ERROR( MAJOR, E_INVALID_STATE, -+ ("xCMNE was defined previously different")); -+ } -+ -+ if ((p_CcParams->setCcParams.type & UPDATE_PSO) -+ && !(p_FmPort->requiredAction & UPDATE_PSO)) -+ { -+ /* get PCD registers pointers */ -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX_10G): -+ case (e_FM_PORT_TYPE_RX): -+ p_BmiPrsStartOffset = &p_FmPort->port.bmi_regs->rx.fmbm_rpso; -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ p_BmiPrsStartOffset = &p_FmPort->port.bmi_regs->oh.fmbm_opso; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Invalid port type")); -+ } -+ -+ /* set start parsing offset */ -+ tmpInt = (int)GET_UINT32(*p_BmiPrsStartOffset) -+ + p_CcParams->setCcParams.psoSize; -+ if (tmpInt > 0) -+ WRITE_UINT32(*p_BmiPrsStartOffset, (uint32_t)tmpInt); -+ -+ p_FmPort->requiredAction |= UPDATE_PSO; -+ p_FmPort->savedPrsStartOffset = p_CcParams->setCcParams.psoSize; -+ } -+ else -+ if (p_CcParams->setCcParams.type & UPDATE_PSO) -+ { -+ if (p_FmPort->savedPrsStartOffset -+ != p_CcParams->setCcParams.psoSize) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("parser start offset was defoned previousley different")); -+ } -+ -+ if ((p_CcParams->setCcParams.type & UPDATE_OFP_DPTE) -+ && !(p_FmPort->requiredAction & UPDATE_OFP_DPTE)) -+ { -+ if (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Invalid port type")); -+ p_FmPort->savedBmiOfp = GET_UINT32(p_FmPort->port.bmi_regs->oh.fmbm_ofp); -+ p_FmPort->savedBmiOfp &= ~BMI_FIFO_PIPELINE_DEPTH_MASK; -+ p_FmPort->savedBmiOfp |= p_CcParams->setCcParams.ofpDpde -+ << BMI_FIFO_PIPELINE_DEPTH_SHIFT; -+ p_FmPort->requiredAction |= UPDATE_OFP_DPTE; -+ } -+ -+ return E_OK; -+} -+/*********************** End of inter-module routines ************************/ -+ -+/****************************************/ -+/* API Init unit functions */ -+/****************************************/ -+ -+t_Handle FM_PORT_Config(t_FmPortParams *p_FmPortParams) -+{ -+ t_FmPort *p_FmPort; -+ uintptr_t baseAddr = p_FmPortParams->baseAddr; -+ uint32_t tmpReg; -+ -+ /* Allocate FM structure */ -+ p_FmPort = (t_FmPort *)XX_Malloc(sizeof(t_FmPort)); -+ if (!p_FmPort) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM Port driver structure")); -+ return NULL; -+ } -+ memset(p_FmPort, 0, sizeof(t_FmPort)); -+ -+ /* Allocate the FM driver's parameters structure */ -+ p_FmPort->p_FmPortDriverParam = (t_FmPortDriverParam *)XX_Malloc( -+ sizeof(t_FmPortDriverParam)); -+ if (!p_FmPort->p_FmPortDriverParam) -+ { -+ XX_Free(p_FmPort); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM Port driver parameters")); -+ return NULL; -+ } -+ memset(p_FmPort->p_FmPortDriverParam, 0, sizeof(t_FmPortDriverParam)); -+ -+ /* Initialize FM port parameters which will be kept by the driver */ -+ p_FmPort->portType = p_FmPortParams->portType; -+ p_FmPort->portId = p_FmPortParams->portId; -+ p_FmPort->pcdEngines = FM_PCD_NONE; -+ p_FmPort->f_Exception = p_FmPortParams->f_Exception; -+ p_FmPort->h_App = p_FmPortParams->h_App; -+ p_FmPort->h_Fm = p_FmPortParams->h_Fm; -+ -+ /* get FM revision */ -+ FM_GetRevision(p_FmPort->h_Fm, &p_FmPort->fmRevInfo); -+ -+ /* calculate global portId number */ -+ p_FmPort->hardwarePortId = SwPortIdToHwPortId(p_FmPort->portType, -+ p_FmPortParams->portId, -+ p_FmPort->fmRevInfo.majorRev, -+ p_FmPort->fmRevInfo.minorRev); -+ -+ if (p_FmPort->fmRevInfo.majorRev >= 6) -+ { -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_OH_HOST_COMMAND) -+ && (p_FmPortParams->portId != FM_OH_PORT_ID)) -+ DBG(WARNING, -+ ("Port ID %d is recommended for HC port. Overwriting HW defaults to be suitable for HC.", -+ FM_OH_PORT_ID)); -+ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ && (p_FmPortParams->portId == FM_OH_PORT_ID)) -+ DBG(WARNING, ("Use non-zero portId for OP port due to insufficient resources on portId 0.")); -+ } -+ -+ /* Set up FM port parameters for initialization phase only */ -+ -+ /* First, fill in flibs struct */ -+ fman_port_defconfig(&p_FmPort->p_FmPortDriverParam->dfltCfg, -+ (enum fman_port_type)p_FmPort->portType); -+ /* Overwrite some integration specific parameters */ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.rx_pri_elevation = -+ DEFAULT_PORT_rxFifoPriElevationLevel; -+ p_FmPort->p_FmPortDriverParam->dfltCfg.rx_fifo_thr = -+ DEFAULT_PORT_rxFifoThreshold; -+ -+#if defined(FM_OP_NO_VSP_NO_RELEASE_ERRATA_FMAN_A006675) || defined(FM_ERROR_VSP_NO_MATCH_SW006) -+ p_FmPort->p_FmPortDriverParam->dfltCfg.errata_A006675 = TRUE; -+#else -+ p_FmPort->p_FmPortDriverParam->dfltCfg.errata_A006675 = FALSE; -+#endif -+ if ((p_FmPort->fmRevInfo.majorRev == 6) -+ && (p_FmPort->fmRevInfo.minorRev == 0)) -+ p_FmPort->p_FmPortDriverParam->dfltCfg.errata_A006320 = TRUE; -+ else -+ p_FmPort->p_FmPortDriverParam->dfltCfg.errata_A006320 = FALSE; -+ -+ /* Excessive Threshold register - exists for pre-FMv3 chips only */ -+ if (p_FmPort->fmRevInfo.majorRev < 6) -+ { -+#ifdef FM_NO_RESTRICT_ON_ACCESS_RSRC -+ p_FmPort->p_FmPortDriverParam->dfltCfg.excessive_threshold_register = -+ TRUE; -+#endif -+ p_FmPort->p_FmPortDriverParam->dfltCfg.fmbm_rebm_has_sgd = FALSE; -+ p_FmPort->p_FmPortDriverParam->dfltCfg.fmbm_tfne_has_features = FALSE; -+ } -+ else -+ { -+ p_FmPort->p_FmPortDriverParam->dfltCfg.excessive_threshold_register = -+ FALSE; -+ p_FmPort->p_FmPortDriverParam->dfltCfg.fmbm_rebm_has_sgd = TRUE; -+ p_FmPort->p_FmPortDriverParam->dfltCfg.fmbm_tfne_has_features = TRUE; -+ } -+ if (p_FmPort->fmRevInfo.majorRev == 4) -+ p_FmPort->p_FmPortDriverParam->dfltCfg.qmi_deq_options_support = FALSE; -+ else -+ p_FmPort->p_FmPortDriverParam->dfltCfg.qmi_deq_options_support = TRUE; -+ -+ /* Continue with other parameters */ -+ p_FmPort->p_FmPortDriverParam->baseAddr = baseAddr; -+ /* set memory map pointers */ -+ p_FmPort->p_FmPortQmiRegs = -+ (t_FmPortQmiRegs *)UINT_TO_PTR(baseAddr + QMI_PORT_REGS_OFFSET); -+ p_FmPort->p_FmPortBmiRegs = -+ (u_FmPortBmiRegs *)UINT_TO_PTR(baseAddr + BMI_PORT_REGS_OFFSET); -+ p_FmPort->p_FmPortPrsRegs = -+ (t_FmPortPrsRegs *)UINT_TO_PTR(baseAddr + PRS_PORT_REGS_OFFSET); -+ -+ p_FmPort->p_FmPortDriverParam->bufferPrefixContent.privDataSize = -+ DEFAULT_PORT_bufferPrefixContent_privDataSize; -+ p_FmPort->p_FmPortDriverParam->bufferPrefixContent.passPrsResult = -+ DEFAULT_PORT_bufferPrefixContent_passPrsResult; -+ p_FmPort->p_FmPortDriverParam->bufferPrefixContent.passTimeStamp = -+ DEFAULT_PORT_bufferPrefixContent_passTimeStamp; -+ p_FmPort->p_FmPortDriverParam->bufferPrefixContent.passAllOtherPCDInfo = -+ DEFAULT_PORT_bufferPrefixContent_passTimeStamp; -+ p_FmPort->p_FmPortDriverParam->bufferPrefixContent.dataAlign = -+ DEFAULT_PORT_bufferPrefixContent_dataAlign; -+ /* p_FmPort->p_FmPortDriverParam->dmaSwapData = (e_FmDmaSwapOption)DEFAULT_PORT_dmaSwapData; -+ p_FmPort->p_FmPortDriverParam->dmaIntContextCacheAttr = (e_FmDmaCacheOption)DEFAULT_PORT_dmaIntContextCacheAttr; -+ p_FmPort->p_FmPortDriverParam->dmaHeaderCacheAttr = (e_FmDmaCacheOption)DEFAULT_PORT_dmaHeaderCacheAttr; -+ p_FmPort->p_FmPortDriverParam->dmaScatterGatherCacheAttr = (e_FmDmaCacheOption)DEFAULT_PORT_dmaScatterGatherCacheAttr; -+ p_FmPort->p_FmPortDriverParam->dmaWriteOptimize = DEFAULT_PORT_dmaWriteOptimize; -+ */ -+ p_FmPort->p_FmPortDriverParam->liodnBase = p_FmPortParams->liodnBase; -+ p_FmPort->p_FmPortDriverParam->cheksumLastBytesIgnore = -+ DEFAULT_PORT_cheksumLastBytesIgnore; -+ -+ p_FmPort->maxFrameLength = DEFAULT_PORT_maxFrameLength; -+ /* resource distribution. */ -+ p_FmPort->fifoBufs.num = DEFAULT_PORT_numOfFifoBufs(p_FmPort->portType) -+ * BMI_FIFO_UNITS; -+ p_FmPort->fifoBufs.extra = DEFAULT_PORT_extraNumOfFifoBufs -+ * BMI_FIFO_UNITS; -+ p_FmPort->openDmas.num = DEFAULT_PORT_numOfOpenDmas(p_FmPort->portType); -+ p_FmPort->openDmas.extra = -+ DEFAULT_PORT_extraNumOfOpenDmas(p_FmPort->portType); -+ p_FmPort->tasks.num = DEFAULT_PORT_numOfTasks(p_FmPort->portType); -+ p_FmPort->tasks.extra = DEFAULT_PORT_extraNumOfTasks(p_FmPort->portType); -+ -+ -+#ifdef FM_HEAVY_TRAFFIC_SEQUENCER_HANG_ERRATA_FMAN_A006981 -+ if ((p_FmPort->fmRevInfo.majorRev == 6) -+ && (p_FmPort->fmRevInfo.minorRev == 0) -+ && ((p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_TX))) -+ { -+ p_FmPort->openDmas.num = 16; -+ p_FmPort->openDmas.extra = 0; -+ } -+#endif /* FM_HEAVY_TRAFFIC_SEQUENCER_HANG_ERRATA_FMAN_A006981 */ -+ -+ /* Port type specific initialization: */ -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX): -+ case (e_FM_PORT_TYPE_RX_10G): -+ /* Initialize FM port parameters for initialization phase only */ -+ p_FmPort->p_FmPortDriverParam->cutBytesFromEnd = -+ DEFAULT_PORT_cutBytesFromEnd; -+ p_FmPort->p_FmPortDriverParam->enBufPoolDepletion = FALSE; -+ p_FmPort->p_FmPortDriverParam->frmDiscardOverride = -+ DEFAULT_PORT_frmDiscardOverride; -+ -+ tmpReg = -+ GET_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfp); -+ p_FmPort->p_FmPortDriverParam->rxFifoPriElevationLevel = -+ (((tmpReg & BMI_RX_FIFO_PRI_ELEVATION_MASK) -+ >> BMI_RX_FIFO_PRI_ELEVATION_SHIFT) + 1) -+ * BMI_FIFO_UNITS; -+ p_FmPort->p_FmPortDriverParam->rxFifoThreshold = (((tmpReg -+ & BMI_RX_FIFO_THRESHOLD_MASK) -+ >> BMI_RX_FIFO_THRESHOLD_SHIFT) + 1) * BMI_FIFO_UNITS; -+ -+ p_FmPort->p_FmPortDriverParam->bufMargins.endMargins = -+ DEFAULT_PORT_BufMargins_endMargins; -+ p_FmPort->p_FmPortDriverParam->errorsToDiscard = -+ DEFAULT_PORT_errorsToDiscard; -+ p_FmPort->p_FmPortDriverParam->forwardReuseIntContext = -+ DEFAULT_PORT_forwardIntContextReuse; -+#if (DPAA_VERSION >= 11) -+ p_FmPort->p_FmPortDriverParam->noScatherGather = -+ DEFAULT_PORT_noScatherGather; -+#endif /* (DPAA_VERSION >= 11) */ -+ break; -+ -+ case (e_FM_PORT_TYPE_TX): -+ p_FmPort->p_FmPortDriverParam->dontReleaseBuf = FALSE; -+#ifdef FM_WRONG_RESET_VALUES_ERRATA_FMAN_A005127 -+ tmpReg = 0x00001013; -+ WRITE_UINT32( p_FmPort->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tfp, -+ tmpReg); -+#endif /* FM_WRONG_RESET_VALUES_ERRATA_FMAN_A005127 */ -+ case (e_FM_PORT_TYPE_TX_10G): -+ tmpReg = -+ GET_UINT32(p_FmPort->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tfp); -+ p_FmPort->p_FmPortDriverParam->txFifoMinFillLevel = ((tmpReg -+ & BMI_TX_FIFO_MIN_FILL_MASK) -+ >> BMI_TX_FIFO_MIN_FILL_SHIFT) * BMI_FIFO_UNITS; -+ p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth = -+ (uint8_t)(((tmpReg & BMI_FIFO_PIPELINE_DEPTH_MASK) -+ >> BMI_FIFO_PIPELINE_DEPTH_SHIFT) + 1); -+ p_FmPort->p_FmPortDriverParam->txFifoLowComfLevel = (((tmpReg -+ & BMI_TX_LOW_COMF_MASK) >> BMI_TX_LOW_COMF_SHIFT) + 1) -+ * BMI_FIFO_UNITS; -+ -+ p_FmPort->p_FmPortDriverParam->deqType = DEFAULT_PORT_deqType; -+ p_FmPort->p_FmPortDriverParam->deqPrefetchOption = -+ DEFAULT_PORT_deqPrefetchOption; -+ p_FmPort->p_FmPortDriverParam->deqHighPriority = -+ (bool)((p_FmPort->portType == e_FM_PORT_TYPE_TX) ? DEFAULT_PORT_deqHighPriority_1G : -+ DEFAULT_PORT_deqHighPriority_10G); -+ p_FmPort->p_FmPortDriverParam->deqByteCnt = -+ (uint16_t)( -+ (p_FmPort->portType == e_FM_PORT_TYPE_TX) ? DEFAULT_PORT_deqByteCnt_1G : -+ DEFAULT_PORT_deqByteCnt_10G); -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ p_FmPort->p_FmPortDriverParam->errorsToDiscard = -+ DEFAULT_PORT_errorsToDiscard; -+#if (DPAA_VERSION >= 11) -+ p_FmPort->p_FmPortDriverParam->noScatherGather = -+ DEFAULT_PORT_noScatherGather; -+#endif /* (DPAA_VERSION >= 11) */ -+ case (e_FM_PORT_TYPE_OH_HOST_COMMAND): -+ p_FmPort->p_FmPortDriverParam->deqPrefetchOption = -+ DEFAULT_PORT_deqPrefetchOption_HC; -+ p_FmPort->p_FmPortDriverParam->deqHighPriority = -+ DEFAULT_PORT_deqHighPriority_1G; -+ p_FmPort->p_FmPortDriverParam->deqType = DEFAULT_PORT_deqType; -+ p_FmPort->p_FmPortDriverParam->deqByteCnt = -+ DEFAULT_PORT_deqByteCnt_1G; -+ -+ tmpReg = -+ GET_UINT32(p_FmPort->p_FmPortBmiRegs->ohPortBmiRegs.fmbm_ofp); -+ p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth = -+ (uint8_t)(((tmpReg & BMI_FIFO_PIPELINE_DEPTH_MASK) -+ >> BMI_FIFO_PIPELINE_DEPTH_SHIFT) + 1); -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_OH_HOST_COMMAND) -+ && (p_FmPortParams->portId != FM_OH_PORT_ID)) -+ { -+ /* Overwrite HC defaults */ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth = -+ DEFAULT_PORT_fifoDeqPipelineDepth_OH; -+ } -+ -+#ifndef FM_FRAME_END_PARAMS_FOR_OP -+ if (p_FmPort->fmRevInfo.majorRev < 6) -+ p_FmPort->p_FmPortDriverParam->cheksumLastBytesIgnore = DEFAULT_notSupported; -+#endif /* !FM_FRAME_END_PARAMS_FOR_OP */ -+ -+#ifndef FM_DEQ_PIPELINE_PARAMS_FOR_OP -+ if (!((p_FmPort->fmRevInfo.majorRev == 4) || -+ (p_FmPort->fmRevInfo.majorRev >= 6))) -+ p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth = DEFAULT_notSupported; -+#endif /* !FM_DEQ_PIPELINE_PARAMS_FOR_OP */ -+ break; -+ -+ default: -+ XX_Free(p_FmPort->p_FmPortDriverParam); -+ XX_Free(p_FmPort); -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Invalid port type")); -+ return NULL; -+ } -+#ifdef FM_QMI_NO_DEQ_OPTIONS_SUPPORT -+ if (p_FmPort->fmRevInfo.majorRev == 4) -+ p_FmPort->p_FmPortDriverParam->deqPrefetchOption = (e_FmPortDeqPrefetchOption)DEFAULT_notSupported; -+#endif /* FM_QMI_NO_DEQ_OPTIONS_SUPPORT */ -+ -+ p_FmPort->imEn = p_FmPortParams->independentModeEnable; -+ -+ if (p_FmPort->imEn) -+ { -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_TX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_TX_10G)) -+ p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth = -+ DEFAULT_PORT_fifoDeqPipelineDepth_IM; -+ FmPortConfigIM(p_FmPort, p_FmPortParams); -+ } -+ else -+ { -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX): -+ case (e_FM_PORT_TYPE_RX_10G): -+ /* Initialize FM port parameters for initialization phase only */ -+ memcpy(&p_FmPort->p_FmPortDriverParam->extBufPools, -+ &p_FmPortParams->specificParams.rxParams.extBufPools, -+ sizeof(t_FmExtPools)); -+ p_FmPort->p_FmPortDriverParam->errFqid = -+ p_FmPortParams->specificParams.rxParams.errFqid; -+ p_FmPort->p_FmPortDriverParam->dfltFqid = -+ p_FmPortParams->specificParams.rxParams.dfltFqid; -+ p_FmPort->p_FmPortDriverParam->liodnOffset = -+ p_FmPortParams->specificParams.rxParams.liodnOffset; -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ case (e_FM_PORT_TYPE_TX): -+ case (e_FM_PORT_TYPE_TX_10G): -+ case (e_FM_PORT_TYPE_OH_HOST_COMMAND): -+ p_FmPort->p_FmPortDriverParam->errFqid = -+ p_FmPortParams->specificParams.nonRxParams.errFqid; -+ p_FmPort->p_FmPortDriverParam->deqSubPortal = -+ (uint8_t)(p_FmPortParams->specificParams.nonRxParams.qmChannel -+ & QMI_DEQ_CFG_SUBPORTAL_MASK); -+ p_FmPort->p_FmPortDriverParam->dfltFqid = -+ p_FmPortParams->specificParams.nonRxParams.dfltFqid; -+ break; -+ default: -+ XX_Free(p_FmPort->p_FmPortDriverParam); -+ XX_Free(p_FmPort); -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Invalid port type")); -+ return NULL; -+ } -+ } -+ -+ memset(p_FmPort->name, 0, (sizeof(char)) * MODULE_NAME_SIZE); -+ if (Sprint( -+ p_FmPort->name, -+ "FM-%d-port-%s-%d", -+ FmGetId(p_FmPort->h_Fm), -+ ((p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING -+ || (p_FmPort->portType == e_FM_PORT_TYPE_OH_HOST_COMMAND)) ? "OH" : -+ (p_FmPort->portType == e_FM_PORT_TYPE_RX ? "1g-RX" : -+ (p_FmPort->portType == e_FM_PORT_TYPE_TX ? "1g-TX" : -+ (p_FmPort->portType -+ == e_FM_PORT_TYPE_RX_10G ? "10g-RX" : -+ "10g-TX")))), -+ p_FmPort->portId) == 0) -+ { -+ XX_Free(p_FmPort->p_FmPortDriverParam); -+ XX_Free(p_FmPort); -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Sprint failed")); -+ return NULL; -+ } -+ -+ p_FmPort->h_Spinlock = XX_InitSpinlock(); -+ if (!p_FmPort->h_Spinlock) -+ { -+ XX_Free(p_FmPort->p_FmPortDriverParam); -+ XX_Free(p_FmPort); -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Sprint failed")); -+ return NULL; -+ } -+ -+ return p_FmPort; -+} -+ -+t_FmPort *rx_port = 0; -+t_FmPort *tx_port = 0; -+ -+/**************************************************************************//** -+ @Function FM_PORT_Init -+ -+ @Description Initializes the FM module -+ -+ @Param[in] h_FmPort - FM module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+ *//***************************************************************************/ -+t_Error FM_PORT_Init(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_FmPortDriverParam *p_DriverParams; -+ t_Error errCode; -+ t_FmInterModulePortInitParams fmParams; -+ t_FmRevisionInfo revInfo; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ errCode = FmSpBuildBufferStructure( -+ &p_FmPort->p_FmPortDriverParam->intContext, -+ &p_FmPort->p_FmPortDriverParam->bufferPrefixContent, -+ &p_FmPort->p_FmPortDriverParam->bufMargins, -+ &p_FmPort->bufferOffsets, &p_FmPort->internalBufferOffset); -+ if (errCode != E_OK) -+ RETURN_ERROR(MAJOR, errCode, NO_MSG); -+#ifdef FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 -+ if ((p_FmPort->p_FmPortDriverParam->bcbWorkaround) && -+ (p_FmPort->portType == e_FM_PORT_TYPE_RX)) -+ { -+ p_FmPort->p_FmPortDriverParam->errorsToDiscard |= FM_PORT_FRM_ERR_PHYSICAL; -+ if (!p_FmPort->fifoBufs.num) -+ p_FmPort->fifoBufs.num = DEFAULT_PORT_numOfFifoBufs(p_FmPort->portType)*BMI_FIFO_UNITS; -+ p_FmPort->fifoBufs.num += 4*KILOBYTE; -+ } -+#endif /* FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 */ -+ -+ CHECK_INIT_PARAMETERS(p_FmPort, CheckInitParameters); -+ -+ p_DriverParams = p_FmPort->p_FmPortDriverParam; -+ -+ /* Set up flibs port structure */ -+ memset(&p_FmPort->port, 0, sizeof(struct fman_port)); -+ p_FmPort->port.type = (enum fman_port_type)p_FmPort->portType; -+ FM_GetRevision(p_FmPort->h_Fm, &revInfo); -+ p_FmPort->port.fm_rev_maj = revInfo.majorRev; -+ p_FmPort->port.fm_rev_min = revInfo.minorRev; -+ p_FmPort->port.bmi_regs = -+ (union fman_port_bmi_regs *)UINT_TO_PTR(p_DriverParams->baseAddr + BMI_PORT_REGS_OFFSET); -+ p_FmPort->port.qmi_regs = -+ (struct fman_port_qmi_regs *)UINT_TO_PTR(p_DriverParams->baseAddr + QMI_PORT_REGS_OFFSET); -+ p_FmPort->port.ext_pools_num = (uint8_t)((revInfo.majorRev == 4) ? 4 : 8); -+ p_FmPort->port.im_en = p_FmPort->imEn; -+ p_FmPort->p_FmPortPrsRegs = -+ (t_FmPortPrsRegs *)UINT_TO_PTR(p_DriverParams->baseAddr + PRS_PORT_REGS_OFFSET); -+ -+ if (((p_FmPort->portType == e_FM_PORT_TYPE_RX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX)) && !p_FmPort->imEn) -+ { -+ /* Call the external Buffer routine which also checks fifo -+ size and updates it if necessary */ -+ /* define external buffer pools and pool depletion*/ -+ errCode = SetExtBufferPools(p_FmPort); -+ if (errCode) -+ RETURN_ERROR(MAJOR, errCode, NO_MSG); -+ /* check if the largest external buffer pool is large enough */ -+ if (p_DriverParams->bufMargins.startMargins + MIN_EXT_BUF_SIZE -+ + p_DriverParams->bufMargins.endMargins -+ > p_FmPort->rxPoolsParams.largestBufSize) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("bufMargins.startMargins (%d) + minimum buf size (64) + bufMargins.endMargins (%d) is larger than maximum external buffer size (%d)", p_DriverParams->bufMargins.startMargins, p_DriverParams->bufMargins.endMargins, p_FmPort->rxPoolsParams.largestBufSize)); -+ } -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ { -+ { -+#ifdef FM_NO_OP_OBSERVED_POOLS -+ t_FmRevisionInfo revInfo; -+ -+ FM_GetRevision(p_FmPort->h_Fm, &revInfo); -+ if ((revInfo.majorRev == 4) && (p_DriverParams->enBufPoolDepletion)) -+#endif /* FM_NO_OP_OBSERVED_POOLS */ -+ { -+ /* define external buffer pools */ -+ errCode = SetExtBufferPools(p_FmPort); -+ if (errCode) -+ RETURN_ERROR(MAJOR, errCode, NO_MSG); -+ } -+ } -+ } -+ -+ /************************************************************/ -+ /* Call FM module routine for communicating parameters */ -+ /************************************************************/ -+ memset(&fmParams, 0, sizeof(fmParams)); -+ fmParams.hardwarePortId = p_FmPort->hardwarePortId; -+ fmParams.portType = (e_FmPortType)p_FmPort->portType; -+ fmParams.numOfTasks = (uint8_t)p_FmPort->tasks.num; -+ fmParams.numOfExtraTasks = (uint8_t)p_FmPort->tasks.extra; -+ fmParams.numOfOpenDmas = (uint8_t)p_FmPort->openDmas.num; -+ fmParams.numOfExtraOpenDmas = (uint8_t)p_FmPort->openDmas.extra; -+ -+ if (p_FmPort->fifoBufs.num) -+ { -+ errCode = VerifySizeOfFifo(p_FmPort); -+ if (errCode != E_OK) -+ RETURN_ERROR(MAJOR, errCode, NO_MSG); -+ } -+ fmParams.sizeOfFifo = p_FmPort->fifoBufs.num; -+ fmParams.extraSizeOfFifo = p_FmPort->fifoBufs.extra; -+ fmParams.independentMode = p_FmPort->imEn; -+ fmParams.liodnOffset = p_DriverParams->liodnOffset; -+ fmParams.liodnBase = p_DriverParams->liodnBase; -+ fmParams.deqPipelineDepth = -+ p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth; -+ fmParams.maxFrameLength = p_FmPort->maxFrameLength; -+#ifndef FM_DEQ_PIPELINE_PARAMS_FOR_OP -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) || -+ (p_FmPort->portType == e_FM_PORT_TYPE_OH_HOST_COMMAND)) -+ { -+ if (!((p_FmPort->fmRevInfo.majorRev == 4) || -+ (p_FmPort->fmRevInfo.majorRev >= 6))) -+ /* HC ports do not have fifoDeqPipelineDepth, but it is needed only -+ * for deq threshold calculation. -+ */ -+ fmParams.deqPipelineDepth = 2; -+ } -+#endif /* !FM_DEQ_PIPELINE_PARAMS_FOR_OP */ -+ -+ errCode = FmGetSetPortParams(p_FmPort->h_Fm, &fmParams); -+ if (errCode) -+ RETURN_ERROR(MAJOR, errCode, NO_MSG); -+ -+ /* get params for use in init */ -+ p_FmPort->fmMuramPhysBaseAddr = -+ (uint64_t)((uint64_t)(fmParams.fmMuramPhysBaseAddr.low) -+ | ((uint64_t)(fmParams.fmMuramPhysBaseAddr.high) << 32)); -+ p_FmPort->h_FmMuram = FmGetMuramHandle(p_FmPort->h_Fm); -+ -+ errCode = InitLowLevelDriver(p_FmPort); -+ if (errCode != E_OK) -+ RETURN_ERROR(MAJOR, errCode, NO_MSG); -+ -+ FmPortDriverParamFree(p_FmPort); -+ -+#if (DPAA_VERSION >= 11) -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ { -+ t_FmPcdCtrlParamsPage *p_ParamsPage; -+ -+ FmPortSetGprFunc(p_FmPort, e_FM_PORT_GPR_MURAM_PAGE, -+ (void**)&p_ParamsPage); -+ ASSERT_COND(p_ParamsPage); -+ -+ WRITE_UINT32(p_ParamsPage->misc, FM_CTL_PARAMS_PAGE_ALWAYS_ON); -+#ifdef FM_OP_NO_VSP_NO_RELEASE_ERRATA_FMAN_A006675 -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ { -+ WRITE_UINT32( -+ p_ParamsPage->misc, -+ (GET_UINT32(p_ParamsPage->misc) | FM_CTL_PARAMS_PAGE_OP_FIX_EN)); -+ WRITE_UINT32( -+ p_ParamsPage->discardMask, -+ GET_UINT32(p_FmPort->p_FmPortBmiRegs->ohPortBmiRegs.fmbm_ofsdm)); -+ } -+#endif /* FM_OP_NO_VSP_NO_RELEASE_ERRATA_FMAN_A006675 */ -+#ifdef FM_ERROR_VSP_NO_MATCH_SW006 -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ WRITE_UINT32( -+ p_ParamsPage->errorsDiscardMask, -+ (GET_UINT32(p_FmPort->p_FmPortBmiRegs->ohPortBmiRegs.fmbm_ofsdm) | GET_UINT32(p_FmPort->p_FmPortBmiRegs->ohPortBmiRegs.fmbm_ofsem))); -+ else -+ WRITE_UINT32( -+ p_ParamsPage->errorsDiscardMask, -+ (GET_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfsdm) | GET_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfsem))); -+#endif /* FM_ERROR_VSP_NO_MATCH_SW006 */ -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ if (p_FmPort->deepSleepVars.autoResMaxSizes) -+ FmPortConfigAutoResForDeepSleepSupport1(p_FmPort); -+ return E_OK; -+} -+ -+/**************************************************************************//** -+ @Function FM_PORT_Free -+ -+ @Description Frees all resources that were assigned to FM module. -+ -+ Calling this routine invalidates the descriptor. -+ -+ @Param[in] h_FmPort - FM module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+ *//***************************************************************************/ -+t_Error FM_PORT_Free(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_FmInterModulePortFreeParams fmParams; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ -+ if (p_FmPort->pcdEngines) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("Trying to free a port with PCD. FM_PORT_DeletePCD must be called first.")); -+ -+ if (p_FmPort->enabled) -+ { -+ if (FM_PORT_Disable(p_FmPort) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("FM_PORT_Disable FAILED")); -+ } -+ -+ if (p_FmPort->imEn) -+ FmPortImFree(p_FmPort); -+ -+ FmPortDriverParamFree(p_FmPort); -+ -+ memset(&fmParams, 0, sizeof(fmParams)); -+ fmParams.hardwarePortId = p_FmPort->hardwarePortId; -+ fmParams.portType = (e_FmPortType)p_FmPort->portType; -+ fmParams.deqPipelineDepth = -+ p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth; -+ -+ FmFreePortParams(p_FmPort->h_Fm, &fmParams); -+ -+#if (DPAA_VERSION >= 11) -+ if (FmVSPFreeForPort(p_FmPort->h_Fm, p_FmPort->portType, p_FmPort->portId) -+ != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("VSP free of port FAILED")); -+ -+ if (p_FmPort->p_ParamsPage) -+ FM_MURAM_FreeMem(p_FmPort->h_FmMuram, p_FmPort->p_ParamsPage); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ if (p_FmPort->h_Spinlock) -+ XX_FreeSpinlock(p_FmPort->h_Spinlock); -+ -+ XX_Free(p_FmPort); -+ -+ return E_OK; -+} -+ -+/*************************************************/ -+/* API Advanced Init unit functions */ -+/*************************************************/ -+ -+t_Error FM_PORT_ConfigNumOfOpenDmas(t_Handle h_FmPort, t_FmPortRsrc *p_OpenDmas) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->p_FmPortDriverParam->setNumOfOpenDmas = TRUE; -+ memcpy(&p_FmPort->openDmas, p_OpenDmas, sizeof(t_FmPortRsrc)); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigNumOfTasks(t_Handle h_FmPort, t_FmPortRsrc *p_NumOfTasks) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ memcpy(&p_FmPort->tasks, p_NumOfTasks, sizeof(t_FmPortRsrc)); -+ p_FmPort->p_FmPortDriverParam->setNumOfTasks = TRUE; -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigSizeOfFifo(t_Handle h_FmPort, t_FmPortRsrc *p_SizeOfFifo) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->p_FmPortDriverParam->setSizeOfFifo = TRUE; -+ memcpy(&p_FmPort->fifoBufs, p_SizeOfFifo, sizeof(t_FmPortRsrc)); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigDeqHighPriority(t_Handle h_FmPort, bool highPri) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("not available for Rx ports")); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.deq_high_pri = highPri; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigDeqType(t_Handle h_FmPort, e_FmPortDeqType deqType) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("not available for Rx ports")); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.deq_type = -+ (enum fman_port_deq_type)deqType; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigDeqPrefetchOption( -+ t_Handle h_FmPort, e_FmPortDeqPrefetchOption deqPrefetchOption) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("not available for Rx ports")); -+ p_FmPort->p_FmPortDriverParam->dfltCfg.deq_prefetch_opt = -+ (enum fman_port_deq_prefetch)deqPrefetchOption; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigBackupPools(t_Handle h_FmPort, -+ t_FmBackupBmPools *p_BackupBmPools) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for Rx ports only")); -+ -+ p_FmPort->p_FmPortDriverParam->p_BackupBmPools = -+ (t_FmBackupBmPools *)XX_Malloc(sizeof(t_FmBackupBmPools)); -+ if (!p_FmPort->p_FmPortDriverParam->p_BackupBmPools) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("p_BackupBmPools allocation failed")); -+ memcpy(p_FmPort->p_FmPortDriverParam->p_BackupBmPools, p_BackupBmPools, -+ sizeof(t_FmBackupBmPools)); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigDeqByteCnt(t_Handle h_FmPort, uint16_t deqByteCnt) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("not available for Rx ports")); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.deq_byte_cnt = deqByteCnt; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigBufferPrefixContent( -+ t_Handle h_FmPort, t_FmBufferPrefixContent *p_FmBufferPrefixContent) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ memcpy(&p_FmPort->p_FmPortDriverParam->bufferPrefixContent, -+ p_FmBufferPrefixContent, sizeof(t_FmBufferPrefixContent)); -+ /* if dataAlign was not initialized by user, we return to driver's default */ -+ if (!p_FmPort->p_FmPortDriverParam->bufferPrefixContent.dataAlign) -+ p_FmPort->p_FmPortDriverParam->bufferPrefixContent.dataAlign = -+ DEFAULT_PORT_bufferPrefixContent_dataAlign; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigCheksumLastBytesIgnore(t_Handle h_FmPort, -+ uint8_t checksumLastBytesIgnore) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.checksum_bytes_ignore = -+ checksumLastBytesIgnore; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigCutBytesFromEnd(t_Handle h_FmPort, -+ uint8_t cutBytesFromEnd) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for Rx ports only")); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.rx_cut_end_bytes = cutBytesFromEnd; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigPoolDepletion(t_Handle h_FmPort, -+ t_FmBufPoolDepletion *p_BufPoolDepletion) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for Rx ports only")); -+ -+ p_FmPort->p_FmPortDriverParam->enBufPoolDepletion = TRUE; -+ memcpy(&p_FmPort->p_FmPortDriverParam->bufPoolDepletion, p_BufPoolDepletion, -+ sizeof(t_FmBufPoolDepletion)); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigObservedPoolDepletion( -+ t_Handle h_FmPort, -+ t_FmPortObservedBufPoolDepletion *p_FmPortObservedBufPoolDepletion) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for OP ports only")); -+ -+ p_FmPort->p_FmPortDriverParam->enBufPoolDepletion = TRUE; -+ memcpy(&p_FmPort->p_FmPortDriverParam->bufPoolDepletion, -+ &p_FmPortObservedBufPoolDepletion->poolDepletionParams, -+ sizeof(t_FmBufPoolDepletion)); -+ memcpy(&p_FmPort->p_FmPortDriverParam->extBufPools, -+ &p_FmPortObservedBufPoolDepletion->poolsParams, -+ sizeof(t_FmExtPools)); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigExtBufPools(t_Handle h_FmPort, t_FmExtPools *p_FmExtPools) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ if (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for OP ports only")); -+ -+ memcpy(&p_FmPort->p_FmPortDriverParam->extBufPools, p_FmExtPools, -+ sizeof(t_FmExtPools)); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigDontReleaseTxBufToBM(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_TX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_TX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for Tx ports only")); -+ -+ p_FmPort->p_FmPortDriverParam->dontReleaseBuf = TRUE; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigDfltColor(t_Handle h_FmPort, e_FmPortColor color) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ p_FmPort->p_FmPortDriverParam->dfltCfg.color = (enum fman_port_color)color; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigSyncReq(t_Handle h_FmPort, bool syncReq) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_TX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_TX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("Not available for Tx ports")); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.sync_req = syncReq; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigFrmDiscardOverride(t_Handle h_FmPort, bool override) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_TX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_TX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("Not available for Tx ports")); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.discard_override = override; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigErrorsToDiscard(t_Handle h_FmPort, -+ fmPortFrameErrSelect_t errs) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("available for Rx and offline parsing ports only")); -+ -+ p_FmPort->p_FmPortDriverParam->errorsToDiscard = errs; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigDmaSwapData(t_Handle h_FmPort, e_FmDmaSwapOption swapData) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.dma_swap_data = -+ (enum fman_port_dma_swap)swapData; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigDmaIcCacheAttr(t_Handle h_FmPort, -+ e_FmDmaCacheOption intContextCacheAttr) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.dma_ic_stash_on = -+ (bool)(intContextCacheAttr == e_FM_DMA_STASH); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigDmaHdrAttr(t_Handle h_FmPort, -+ e_FmDmaCacheOption headerCacheAttr) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.dma_header_stash_on = -+ (bool)(headerCacheAttr == e_FM_DMA_STASH); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigDmaScatterGatherAttr( -+ t_Handle h_FmPort, e_FmDmaCacheOption scatterGatherCacheAttr) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.dma_sg_stash_on = -+ (bool)(scatterGatherCacheAttr == e_FM_DMA_STASH); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigDmaWriteOptimize(t_Handle h_FmPort, bool optimize) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_TX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_TX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("Not available for Tx ports")); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.dma_write_optimize = optimize; -+ -+ return E_OK; -+} -+ -+#if (DPAA_VERSION >= 11) -+t_Error FM_PORT_ConfigNoScatherGather(t_Handle h_FmPort, bool noScatherGather) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ UNUSED(noScatherGather); -+ UNUSED(p_FmPort); -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->p_FmPortDriverParam->noScatherGather = noScatherGather; -+ -+ return E_OK; -+} -+#endif /* (DPAA_VERSION >= 11) */ -+ -+t_Error FM_PORT_ConfigForwardReuseIntContext(t_Handle h_FmPort, -+ bool forwardReuse) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for Rx ports only")); -+ -+ p_FmPort->p_FmPortDriverParam->forwardReuseIntContext = forwardReuse; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigMaxFrameLength(t_Handle h_FmPort, uint16_t length) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->maxFrameLength = length; -+ -+ return E_OK; -+} -+ -+#ifdef FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 -+t_Error FM_PORT_ConfigBCBWorkaround(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->p_FmPortDriverParam->bcbWorkaround = TRUE; -+ -+ return E_OK; -+} -+#endif /* FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 */ -+ -+/****************************************************/ -+/* Hidden-DEBUG Only API */ -+/****************************************************/ -+ -+t_Error FM_PORT_ConfigTxFifoMinFillLevel(t_Handle h_FmPort, -+ uint32_t minFillLevel) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_TX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_TX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for Tx ports only")); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_min_level = minFillLevel; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigFifoDeqPipelineDepth(t_Handle h_FmPort, -+ uint8_t deqPipelineDepth) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("Not available for Rx ports")); -+ -+ if (p_FmPort->imEn) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("Not available for IM ports!")); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_deq_pipeline_depth = -+ deqPipelineDepth; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigTxFifoLowComfLevel(t_Handle h_FmPort, -+ uint32_t fifoLowComfLevel) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_TX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_TX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for Tx ports only")); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.tx_fifo_low_comf_level = -+ fifoLowComfLevel; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigRxFifoThreshold(t_Handle h_FmPort, uint32_t fifoThreshold) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for Rx ports only")); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.rx_fifo_thr = fifoThreshold; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigRxFifoPriElevationLevel(t_Handle h_FmPort, -+ uint32_t priElevationLevel) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for Rx ports only")); -+ -+ p_FmPort->p_FmPortDriverParam->dfltCfg.rx_pri_elevation = priElevationLevel; -+ -+ return E_OK; -+} -+/****************************************************/ -+/* API Run-time Control unit functions */ -+/****************************************************/ -+ -+t_Error FM_PORT_SetNumOfOpenDmas(t_Handle h_FmPort, -+ t_FmPortRsrc *p_NumOfOpenDmas) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ if ((!p_NumOfOpenDmas->num) || (p_NumOfOpenDmas->num > MAX_NUM_OF_DMAS)) -+ RETURN_ERROR( MAJOR, E_INVALID_VALUE, -+ ("openDmas-num can't be larger than %d", MAX_NUM_OF_DMAS)); -+ if (p_NumOfOpenDmas->extra > MAX_NUM_OF_EXTRA_DMAS) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("openDmas-extra can't be larger than %d", MAX_NUM_OF_EXTRA_DMAS)); -+ err = FmSetNumOfOpenDmas(p_FmPort->h_Fm, p_FmPort->hardwarePortId, -+ (uint8_t*)&p_NumOfOpenDmas->num, -+ (uint8_t*)&p_NumOfOpenDmas->extra, FALSE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ memcpy(&p_FmPort->openDmas, p_NumOfOpenDmas, sizeof(t_FmPortRsrc)); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_SetNumOfTasks(t_Handle h_FmPort, t_FmPortRsrc *p_NumOfTasks) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ /* only driver uses host command port, so ASSERT rather than RETURN_ERROR */ -+ ASSERT_COND(p_FmPort->portType != e_FM_PORT_TYPE_OH_HOST_COMMAND); -+ -+ if ((!p_NumOfTasks->num) || (p_NumOfTasks->num > MAX_NUM_OF_TASKS)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("NumOfTasks-num can't be larger than %d", MAX_NUM_OF_TASKS)); -+ if (p_NumOfTasks->extra > MAX_NUM_OF_EXTRA_TASKS) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("NumOfTasks-extra can't be larger than %d", MAX_NUM_OF_EXTRA_TASKS)); -+ -+ err = FmSetNumOfTasks(p_FmPort->h_Fm, p_FmPort->hardwarePortId, -+ (uint8_t*)&p_NumOfTasks->num, -+ (uint8_t*)&p_NumOfTasks->extra, FALSE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ /* update driver's struct */ -+ memcpy(&p_FmPort->tasks, p_NumOfTasks, sizeof(t_FmPortRsrc)); -+ return E_OK; -+} -+ -+t_Error FM_PORT_SetSizeOfFifo(t_Handle h_FmPort, t_FmPortRsrc *p_SizeOfFifo) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ if (!p_SizeOfFifo->num || (p_SizeOfFifo->num > MAX_PORT_FIFO_SIZE)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("SizeOfFifo-num has to be in the range of 256 - %d", MAX_PORT_FIFO_SIZE)); -+ if (p_SizeOfFifo->num % BMI_FIFO_UNITS) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("SizeOfFifo-num has to be divisible by %d", BMI_FIFO_UNITS)); -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)) -+ { -+ /* extra FIFO size (allowed only to Rx ports) */ -+ if (p_SizeOfFifo->extra % BMI_FIFO_UNITS) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("SizeOfFifo-extra has to be divisible by %d", BMI_FIFO_UNITS)); -+ } -+ else -+ if (p_SizeOfFifo->extra) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ (" No SizeOfFifo-extra for non Rx ports")); -+ -+ memcpy(&p_FmPort->fifoBufs, p_SizeOfFifo, sizeof(t_FmPortRsrc)); -+ -+ /* we do not change user's parameter */ -+ err = VerifySizeOfFifo(p_FmPort); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ err = FmSetSizeOfFifo(p_FmPort->h_Fm, p_FmPort->hardwarePortId, -+ &p_SizeOfFifo->num, &p_SizeOfFifo->extra, FALSE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+uint32_t FM_PORT_GetBufferDataOffset(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPort, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_VALUE(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE, -+ 0); -+ -+ return p_FmPort->bufferOffsets.dataOffset; -+} -+ -+uint8_t * FM_PORT_GetBufferICInfo(t_Handle h_FmPort, char *p_Data) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPort, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE, -+ NULL); -+ -+ if (p_FmPort->bufferOffsets.pcdInfoOffset == ILLEGAL_BASE) -+ return NULL; -+ -+ return (uint8_t *)PTR_MOVE(p_Data, p_FmPort->bufferOffsets.pcdInfoOffset); -+} -+ -+t_FmPrsResult * FM_PORT_GetBufferPrsResult(t_Handle h_FmPort, char *p_Data) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPort, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE, -+ NULL); -+ -+ if (p_FmPort->bufferOffsets.prsResultOffset == ILLEGAL_BASE) -+ return NULL; -+ -+ return (t_FmPrsResult *)PTR_MOVE(p_Data, p_FmPort->bufferOffsets.prsResultOffset); -+} -+ -+uint64_t * FM_PORT_GetBufferTimeStamp(t_Handle h_FmPort, char *p_Data) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPort, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE, -+ NULL); -+ -+ if (p_FmPort->bufferOffsets.timeStampOffset == ILLEGAL_BASE) -+ return NULL; -+ -+ return (uint64_t *)PTR_MOVE(p_Data, p_FmPort->bufferOffsets.timeStampOffset); -+} -+ -+uint8_t * FM_PORT_GetBufferHashResult(t_Handle h_FmPort, char *p_Data) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPort, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE, -+ NULL); -+ -+ if (p_FmPort->bufferOffsets.hashResultOffset == ILLEGAL_BASE) -+ return NULL; -+ -+ return (uint8_t *)PTR_MOVE(p_Data, p_FmPort->bufferOffsets.hashResultOffset); -+} -+ -+t_Error FM_PORT_Disable(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ int err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ if (p_FmPort->imEn) -+ FmPortImDisable(p_FmPort); -+ -+ err = fman_port_disable(&p_FmPort->port); -+ if (err == -EBUSY) -+ { -+ DBG(WARNING, ("%s: BMI or QMI is Busy. Port forced down", -+ p_FmPort->name)); -+ } -+ else -+ if (err != 0) -+ { -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fman_port_disable")); -+ } -+ -+ p_FmPort->enabled = FALSE; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_Enable(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ int err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ /* Used by FM_PORT_Free routine as indication -+ if to disable port. Thus set it to TRUE prior -+ to enabling itself. This way if part of enable -+ process fails there will be still things -+ to disable during Free. For example, if BMI -+ enable succeeded but QMI failed, still BMI -+ needs to be disabled by Free. */ -+ p_FmPort->enabled = TRUE; -+ -+ if (p_FmPort->imEn) -+ FmPortImEnable(p_FmPort); -+ -+ err = fman_port_enable(&p_FmPort->port); -+ if (err != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fman_port_enable")); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_SetRateLimit(t_Handle h_FmPort, t_FmPortRateLimit *p_RateLimit) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ uint8_t factor, countUnitBit; -+ uint16_t baseGran; -+ struct fman_port_rate_limiter params; -+ int err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_TX_10G): -+ case (e_FM_PORT_TYPE_TX): -+ baseGran = BMI_RATE_LIMIT_GRAN_TX; -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ baseGran = BMI_RATE_LIMIT_GRAN_OP; -+ break; -+ default: -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("available for Tx and Offline parsing ports only")); -+ } -+ -+ countUnitBit = (uint8_t)FmGetTimeStampScale(p_FmPort->h_Fm); /* TimeStamp per nano seconds units */ -+ /* normally, we use 1 usec as the reference count */ -+ factor = 1; -+ /* if ratelimit is too small for a 1usec factor, multiply the factor */ -+ while (p_RateLimit->rateLimit < baseGran / factor) -+ { -+ if (countUnitBit == 31) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Rate limit is too small")); -+ -+ countUnitBit++; -+ factor <<= 1; -+ } -+ /* if ratelimit is too large for a 1usec factor, it is also larger than max rate*/ -+ if (p_RateLimit->rateLimit -+ > ((uint32_t)baseGran * (1 << 10) * (uint32_t)factor)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Rate limit is too large")); -+ -+ if (!p_RateLimit->maxBurstSize -+ || (p_RateLimit->maxBurstSize > BMI_RATE_LIMIT_MAX_BURST_SIZE)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("maxBurstSize must be between 1K and %dk", BMI_RATE_LIMIT_MAX_BURST_SIZE)); -+ -+ params.count_1micro_bit = (uint8_t)FmGetTimeStampScale(p_FmPort->h_Fm); -+ params.high_burst_size_gran = FALSE; -+ params.burst_size = p_RateLimit->maxBurstSize; -+ params.rate = p_RateLimit->rateLimit; -+ params.rate_factor = E_FMAN_PORT_RATE_DOWN_NONE; -+ -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ { -+#ifndef FM_NO_ADVANCED_RATE_LIMITER -+ -+ if ((p_FmPort->fmRevInfo.majorRev == 4) -+ || (p_FmPort->fmRevInfo.majorRev >= 6)) -+ { -+ params.high_burst_size_gran = TRUE; -+ } -+ else -+#endif /* ! FM_NO_ADVANCED_RATE_LIMITER */ -+ { -+ if (p_RateLimit->rateLimitDivider -+ != e_FM_PORT_DUAL_RATE_LIMITER_NONE) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, -+ ("FM_PORT_ConfigDualRateLimitScaleDown")); -+ -+ if (p_RateLimit->maxBurstSize % 1000) -+ { -+ p_RateLimit->maxBurstSize = -+ (uint16_t)((p_RateLimit->maxBurstSize / 1000) + 1); -+ DBG(WARNING, ("rateLimit.maxBurstSize rounded up to %d", (p_RateLimit->maxBurstSize/1000+1)*1000)); -+ } -+ else -+ p_RateLimit->maxBurstSize = (uint16_t)(p_RateLimit->maxBurstSize -+ / 1000); -+ } -+ params.rate_factor = -+ (enum fman_port_rate_limiter_scale_down)p_RateLimit->rateLimitDivider; -+ params.burst_size = p_RateLimit->maxBurstSize; -+ } -+ -+ err = fman_port_set_rate_limiter(&p_FmPort->port, ¶ms); -+ if (err != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fman_port_set_rate_limiter")); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_DeleteRateLimit(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ int err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX_10G) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_OH_HOST_COMMAND)) -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("available for Tx and Offline parsing ports only")); -+ -+ err = fman_port_delete_rate_limiter(&p_FmPort->port); -+ if (err != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fman_port_set_rate_limiter")); -+ return E_OK; -+} -+ -+t_Error FM_PORT_SetPfcPrioritiesMappingToQmanWQ(t_Handle h_FmPort, uint8_t prio, -+ uint8_t wq) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ uint32_t tmpReg; -+ uint32_t wqTmpReg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_TX) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_TX_10G)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("PFC mapping is available for Tx ports only")); -+ -+ if (prio > 7) -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, -+ ("PFC priority (%d) is out of range (0-7)", prio)); -+ if (wq > 7) -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, -+ ("WQ (%d) is out of range (0-7)", wq)); -+ -+ tmpReg = GET_UINT32(p_FmPort->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tpfcm[0]); -+ tmpReg &= ~(0xf << ((7 - prio) * 4)); -+ wqTmpReg = ((uint32_t)wq << ((7 - prio) * 4)); -+ tmpReg |= wqTmpReg; -+ -+ WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tpfcm[0], -+ tmpReg); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_SetFrameQueueCounters(t_Handle h_FmPort, bool enable) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ fman_port_set_queue_cnt_mode(&p_FmPort->port, enable); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_SetPerformanceCounters(t_Handle h_FmPort, bool enable) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ int err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ err = fman_port_set_perf_cnt_mode(&p_FmPort->port, enable); -+ if (err != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fman_port_set_perf_cnt_mode")); -+ return E_OK; -+} -+ -+t_Error FM_PORT_SetPerformanceCountersParams( -+ t_Handle h_FmPort, t_FmPortPerformanceCnt *p_FmPortPerformanceCnt) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ struct fman_port_perf_cnt_params params; -+ int err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ -+ /* check parameters */ -+ if (!p_FmPortPerformanceCnt->taskCompVal -+ || (p_FmPortPerformanceCnt->taskCompVal > p_FmPort->tasks.num)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("taskCompVal (%d) has to be in the range of 1 - %d (current value)!", p_FmPortPerformanceCnt->taskCompVal, p_FmPort->tasks.num)); -+ if (!p_FmPortPerformanceCnt->dmaCompVal -+ || (p_FmPortPerformanceCnt->dmaCompVal > p_FmPort->openDmas.num)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("dmaCompVal (%d) has to be in the range of 1 - %d (current value)!", p_FmPortPerformanceCnt->dmaCompVal, p_FmPort->openDmas.num)); -+ if (!p_FmPortPerformanceCnt->fifoCompVal -+ || (p_FmPortPerformanceCnt->fifoCompVal > p_FmPort->fifoBufs.num)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("fifoCompVal (%d) has to be in the range of 256 - %d (current value)!", p_FmPortPerformanceCnt->fifoCompVal, p_FmPort->fifoBufs.num)); -+ if (p_FmPortPerformanceCnt->fifoCompVal % BMI_FIFO_UNITS) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("fifoCompVal (%d) has to be divisible by %d", p_FmPortPerformanceCnt->fifoCompVal, BMI_FIFO_UNITS)); -+ -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX_10G): -+ case (e_FM_PORT_TYPE_RX): -+ if (!p_FmPortPerformanceCnt->queueCompVal -+ || (p_FmPortPerformanceCnt->queueCompVal -+ > MAX_PERFORMANCE_RX_QUEUE_COMP)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("performanceCnt.queueCompVal for Rx has to be in the range of 1 - %d", MAX_PERFORMANCE_RX_QUEUE_COMP)); -+ break; -+ case (e_FM_PORT_TYPE_TX_10G): -+ case (e_FM_PORT_TYPE_TX): -+ if (!p_FmPortPerformanceCnt->queueCompVal -+ || (p_FmPortPerformanceCnt->queueCompVal -+ > MAX_PERFORMANCE_TX_QUEUE_COMP)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("performanceCnt.queueCompVal for Tx has to be in the range of 1 - %d", MAX_PERFORMANCE_TX_QUEUE_COMP)); -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ case (e_FM_PORT_TYPE_OH_HOST_COMMAND): -+ if (p_FmPortPerformanceCnt->queueCompVal) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("performanceCnt.queueCompVal is not relevant for H/O ports.")); -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Invalid port type")); -+ } -+ -+ params.task_val = p_FmPortPerformanceCnt->taskCompVal; -+ params.queue_val = p_FmPortPerformanceCnt->queueCompVal; -+ params.dma_val = p_FmPortPerformanceCnt->dmaCompVal; -+ params.fifo_val = p_FmPortPerformanceCnt->fifoCompVal; -+ -+ err = fman_port_set_perf_cnt_params(&p_FmPort->port, ¶ms); -+ if (err != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fman_port_set_perf_cnt_params")); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_AnalyzePerformanceParams(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_FmPortPerformanceCnt currParams, savedParams; -+ t_Error err; -+ bool underTest, failed = FALSE; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ -+ XX_Print("Analyzing Performance parameters for port (type %d, id%d)\n", -+ p_FmPort->portType, p_FmPort->portId); -+ -+ currParams.taskCompVal = (uint8_t)p_FmPort->tasks.num; -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_OH_HOST_COMMAND)) -+ currParams.queueCompVal = 0; -+ else -+ currParams.queueCompVal = 1; -+ currParams.dmaCompVal = (uint8_t)p_FmPort->openDmas.num; -+ currParams.fifoCompVal = p_FmPort->fifoBufs.num; -+ -+ FM_PORT_SetPerformanceCounters(p_FmPort, FALSE); -+ ClearPerfCnts(p_FmPort); -+ if ((err = FM_PORT_SetPerformanceCountersParams(p_FmPort, &currParams)) -+ != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ FM_PORT_SetPerformanceCounters(p_FmPort, TRUE); -+ XX_UDelay(1000000); -+ FM_PORT_SetPerformanceCounters(p_FmPort, FALSE); -+ if (FM_PORT_GetCounter(p_FmPort, e_FM_PORT_COUNTERS_TASK_UTIL)) -+ { -+ XX_Print( -+ "Max num of defined port tasks (%d) utilized - Please enlarge\n", -+ p_FmPort->tasks.num); -+ failed = TRUE; -+ } -+ if (FM_PORT_GetCounter(p_FmPort, e_FM_PORT_COUNTERS_DMA_UTIL)) -+ { -+ XX_Print( -+ "Max num of defined port openDmas (%d) utilized - Please enlarge\n", -+ p_FmPort->openDmas.num); -+ failed = TRUE; -+ } -+ if (FM_PORT_GetCounter(p_FmPort, e_FM_PORT_COUNTERS_FIFO_UTIL)) -+ { -+ XX_Print( -+ "Max size of defined port fifo (%d) utilized - Please enlarge\n", -+ p_FmPort->fifoBufs.num); -+ failed = TRUE; -+ } -+ if (failed) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ -+ memset(&savedParams, 0, sizeof(savedParams)); -+ while (TRUE) -+ { -+ underTest = FALSE; -+ if ((currParams.taskCompVal != 1) && !savedParams.taskCompVal) -+ { -+ currParams.taskCompVal--; -+ underTest = TRUE; -+ } -+ if ((currParams.dmaCompVal != 1) && !savedParams.dmaCompVal) -+ { -+ currParams.dmaCompVal--; -+ underTest = TRUE; -+ } -+ if ((currParams.fifoCompVal != BMI_FIFO_UNITS) -+ && !savedParams.fifoCompVal) -+ { -+ currParams.fifoCompVal -= BMI_FIFO_UNITS; -+ underTest = TRUE; -+ } -+ if (!underTest) -+ break; -+ -+ ClearPerfCnts(p_FmPort); -+ if ((err = FM_PORT_SetPerformanceCountersParams(p_FmPort, &currParams)) -+ != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ FM_PORT_SetPerformanceCounters(p_FmPort, TRUE); -+ XX_UDelay(1000000); -+ FM_PORT_SetPerformanceCounters(p_FmPort, FALSE); -+ -+ if (!savedParams.taskCompVal -+ && FM_PORT_GetCounter(p_FmPort, e_FM_PORT_COUNTERS_TASK_UTIL)) -+ savedParams.taskCompVal = (uint8_t)(currParams.taskCompVal + 2); -+ if (!savedParams.dmaCompVal -+ && FM_PORT_GetCounter(p_FmPort, e_FM_PORT_COUNTERS_DMA_UTIL)) -+ savedParams.dmaCompVal = (uint8_t)(currParams.dmaCompVal + 2); -+ if (!savedParams.fifoCompVal -+ && FM_PORT_GetCounter(p_FmPort, e_FM_PORT_COUNTERS_FIFO_UTIL)) -+ savedParams.fifoCompVal = currParams.fifoCompVal -+ + (2 * BMI_FIFO_UNITS); -+ } -+ -+ XX_Print("best vals: tasks %d, dmas %d, fifos %d\n", -+ savedParams.taskCompVal, savedParams.dmaCompVal, -+ savedParams.fifoCompVal); -+ return E_OK; -+} -+ -+t_Error FM_PORT_SetStatisticsCounters(t_Handle h_FmPort, bool enable) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ int err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ err = fman_port_set_stats_cnt_mode(&p_FmPort->port, enable); -+ if (err != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fman_port_set_stats_cnt_mode")); -+ return E_OK; -+} -+ -+t_Error FM_PORT_SetErrorsRoute(t_Handle h_FmPort, fmPortFrameErrSelect_t errs) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ volatile uint32_t *p_ErrDiscard = NULL; -+ int err; -+ -+ UNUSED(p_ErrDiscard); -+ err = fman_port_set_err_mask(&p_FmPort->port, (uint32_t)errs); -+ if (err != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fman_port_set_err_mask")); -+ -+#ifdef FM_ERROR_VSP_NO_MATCH_SW006 -+ if (p_FmPort->fmRevInfo.majorRev >= 6) -+ { -+ t_FmPcdCtrlParamsPage *p_ParamsPage; -+ -+ FmPortSetGprFunc(p_FmPort, e_FM_PORT_GPR_MURAM_PAGE, -+ (void**)&p_ParamsPage); -+ ASSERT_COND(p_ParamsPage); -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX_10G): -+ case (e_FM_PORT_TYPE_RX): -+ p_ErrDiscard = -+ &p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfsdm; -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ p_ErrDiscard = -+ &p_FmPort->p_FmPortBmiRegs->ohPortBmiRegs.fmbm_ofsdm; -+ break; -+ default: -+ RETURN_ERROR( -+ MAJOR, E_INVALID_OPERATION, -+ ("available for Rx and offline parsing ports only")); -+ } -+ WRITE_UINT32(p_ParamsPage->errorsDiscardMask, -+ GET_UINT32(*p_ErrDiscard) | errs); -+ } -+#endif /* FM_ERROR_VSP_NO_MATCH_SW006 */ -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_SetAllocBufCounter(t_Handle h_FmPort, uint8_t poolId, -+ bool enable) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ int err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(poolIdp_FmPortDriverParam, E_INVALID_STATE); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for Rx ports only")); -+ -+ err = fman_port_set_bpool_cnt_mode(&p_FmPort->port, poolId, enable); -+ if (err != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fman_port_set_bpool_cnt_mode")); -+ return E_OK; -+} -+ -+t_Error FM_PORT_GetBmiCounters(t_Handle h_FmPort, t_FmPortBmiStats *p_BmiStats) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)){ -+ p_BmiStats->cntCycle = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_CYCLE); -+ /* fmbm_rccn */ -+ p_BmiStats->cntTaskUtil = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_TASK_UTIL); -+ /* fmbm_rtuc */ -+ p_BmiStats->cntQueueUtil = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_QUEUE_UTIL); -+ /* fmbm_rrquc */ -+ p_BmiStats->cntDmaUtil = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_DMA_UTIL); -+ /* fmbm_rduc */ -+ p_BmiStats->cntFifoUtil = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_FIFO_UTIL); -+ /* fmbm_rfuc */ -+ p_BmiStats->cntRxPauseActivation = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_RX_PAUSE_ACTIVATION); -+ /* fmbm_rpac */ -+ p_BmiStats->cntFrame = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_FRAME); -+ /* fmbm_rfrc */ -+ p_BmiStats->cntDiscardFrame = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_DISCARD_FRAME); -+ /* fmbm_rfdc */ -+ p_BmiStats->cntDeallocBuf = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_DEALLOC_BUF); -+ /* fmbm_rbdc */ -+ p_BmiStats->cntRxBadFrame = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_RX_BAD_FRAME); -+ /* fmbm_rfbc */ -+ p_BmiStats->cntRxLargeFrame = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_RX_LARGE_FRAME); -+ /* fmbm_rlfc */ -+ p_BmiStats->cntRxFilterFrame = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_RX_FILTER_FRAME); -+ /* fmbm_rffc */ -+ p_BmiStats->cntRxListDmaErr = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_RX_LIST_DMA_ERR); -+ /* fmbm_rfldec */ -+ p_BmiStats->cntRxOutOfBuffersDiscard = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_RX_OUT_OF_BUFFERS_DISCARD); -+ /* fmbm_rodc */ -+ p_BmiStats->cntWredDiscard = 0; -+ p_BmiStats->cntLengthErr = 0; -+ p_BmiStats->cntUnsupportedFormat = 0; -+ } -+ else if ((p_FmPort->portType == e_FM_PORT_TYPE_TX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_TX_10G)){ -+ p_BmiStats->cntCycle = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_CYCLE); -+ /* fmbm_tccn */ -+ p_BmiStats->cntTaskUtil = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_TASK_UTIL); -+ /* fmbm_ttuc */ -+ p_BmiStats->cntQueueUtil = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_QUEUE_UTIL); -+ /* fmbm_ttcquc */ -+ p_BmiStats->cntDmaUtil = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_DMA_UTIL); -+ /* fmbm_tduc */ -+ p_BmiStats->cntFifoUtil = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_FIFO_UTIL); -+ /* fmbm_tfuc */ -+ p_BmiStats->cntRxPauseActivation = 0; -+ p_BmiStats->cntFrame = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_FRAME); -+ /* fmbm_tfrc */ -+ p_BmiStats->cntDiscardFrame = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_DISCARD_FRAME); -+ /* fmbm_tfdc */ -+ p_BmiStats->cntDeallocBuf = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_DEALLOC_BUF); -+ /* fmbm_tbdc */ -+ p_BmiStats->cntRxBadFrame = 0; -+ p_BmiStats->cntRxLargeFrame = 0; -+ p_BmiStats->cntRxFilterFrame = 0; -+ p_BmiStats->cntRxListDmaErr = 0; -+ p_BmiStats->cntRxOutOfBuffersDiscard = 0; -+ p_BmiStats->cntWredDiscard = 0; -+ p_BmiStats->cntLengthErr = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_LENGTH_ERR); -+ /* fmbm_tfledc */ -+ p_BmiStats->cntUnsupportedFormat = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_UNSUPPRTED_FORMAT); -+ /* fmbm_tfufdc */ -+ } -+ else if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) { -+ p_BmiStats->cntCycle = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_CYCLE); -+ /* fmbm_occn */ -+ p_BmiStats->cntTaskUtil = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_TASK_UTIL); -+ /* fmbm_otuc */ -+ p_BmiStats->cntQueueUtil = 0; -+ p_BmiStats->cntDmaUtil = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_DMA_UTIL); -+ /* fmbm_oduc */ -+ p_BmiStats->cntFifoUtil = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_FIFO_UTIL); -+ /* fmbm_ofuc*/ -+ p_BmiStats->cntRxPauseActivation = 0; -+ p_BmiStats->cntFrame = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_FRAME); -+ /* fmbm_ofrc */ -+ p_BmiStats->cntDiscardFrame = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_DISCARD_FRAME); -+ /* fmbm_ofdc */ -+ p_BmiStats->cntDeallocBuf = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_DEALLOC_BUF); -+ /* fmbm_obdc*/ -+ p_BmiStats->cntRxBadFrame = 0; -+ p_BmiStats->cntRxLargeFrame = 0; -+ p_BmiStats->cntRxFilterFrame = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_RX_FILTER_FRAME); -+ /* fmbm_offc */ -+ p_BmiStats->cntRxListDmaErr = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_RX_LIST_DMA_ERR); -+ /* fmbm_ofldec */ -+ p_BmiStats->cntRxOutOfBuffersDiscard = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_RX_OUT_OF_BUFFERS_DISCARD); -+ /* fmbm_rodc */ -+ p_BmiStats->cntWredDiscard = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_WRED_DISCARD); -+ /* fmbm_ofwdc */ -+ p_BmiStats->cntLengthErr = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_LENGTH_ERR); -+ /* fmbm_ofledc */ -+ p_BmiStats->cntUnsupportedFormat = -+ FM_PORT_GetCounter(h_FmPort, e_FM_PORT_COUNTERS_UNSUPPRTED_FORMAT); -+ /* fmbm_ofufdc */ -+ } -+ return E_OK; -+} -+ -+uint32_t FM_PORT_GetCounter(t_Handle h_FmPort, e_FmPortCounters counter) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ bool bmiCounter = FALSE; -+ enum fman_port_stats_counters statsType; -+ enum fman_port_perf_counters perfType; -+ enum fman_port_qmi_counters queueType; -+ bool isStats; -+ t_Error errCode; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPort, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ switch (counter) -+ { -+ case (e_FM_PORT_COUNTERS_DEQ_TOTAL): -+ case (e_FM_PORT_COUNTERS_DEQ_FROM_DEFAULT): -+ case (e_FM_PORT_COUNTERS_DEQ_CONFIRM): -+ /* check that counter is available for the port type */ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)) -+ { -+ REPORT_ERROR(MINOR, E_INVALID_STATE, -+ ("Requested counter is not available for Rx ports")); -+ return 0; -+ } -+ bmiCounter = FALSE; -+ break; -+ case (e_FM_PORT_COUNTERS_ENQ_TOTAL): -+ bmiCounter = FALSE; -+ break; -+ default: /* BMI counters (or error - will be checked in BMI routine )*/ -+ bmiCounter = TRUE; -+ break; -+ } -+ -+ if (bmiCounter) -+ { -+ errCode = BmiPortCheckAndGetCounterType(p_FmPort, counter, &statsType, -+ &perfType, &isStats); -+ if (errCode != E_OK) -+ { -+ REPORT_ERROR(MINOR, errCode, NO_MSG); -+ return 0; -+ } -+ if (isStats) -+ return fman_port_get_stats_counter(&p_FmPort->port, statsType); -+ else -+ return fman_port_get_perf_counter(&p_FmPort->port, perfType); -+ } -+ else /* QMI counter */ -+ { -+ /* check that counters are enabled */ -+ if (!(GET_UINT32(p_FmPort->port.qmi_regs->fmqm_pnc) -+ & QMI_PORT_CFG_EN_COUNTERS)) -+ -+ { -+ REPORT_ERROR(MINOR, E_INVALID_STATE, ("Requested counter was not enabled")); -+ return 0; -+ } -+ -+ /* Set counter */ -+ switch (counter) -+ { -+ case (e_FM_PORT_COUNTERS_ENQ_TOTAL): -+ queueType = E_FMAN_PORT_ENQ_TOTAL; -+ break; -+ case (e_FM_PORT_COUNTERS_DEQ_TOTAL): -+ queueType = E_FMAN_PORT_DEQ_TOTAL; -+ break; -+ case (e_FM_PORT_COUNTERS_DEQ_FROM_DEFAULT): -+ queueType = E_FMAN_PORT_DEQ_FROM_DFLT; -+ break; -+ case (e_FM_PORT_COUNTERS_DEQ_CONFIRM): -+ queueType = E_FMAN_PORT_DEQ_CONFIRM; -+ break; -+ default: -+ REPORT_ERROR(MINOR, E_INVALID_STATE, ("Requested counter is not available")); -+ return 0; -+ } -+ -+ return fman_port_get_qmi_counter(&p_FmPort->port, queueType); -+ } -+ -+ return 0; -+} -+ -+t_Error FM_PORT_ModifyCounter(t_Handle h_FmPort, e_FmPortCounters counter, -+ uint32_t value) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ bool bmiCounter = FALSE; -+ enum fman_port_stats_counters statsType; -+ enum fman_port_perf_counters perfType; -+ enum fman_port_qmi_counters queueType; -+ bool isStats; -+ t_Error errCode; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ switch (counter) -+ { -+ case (e_FM_PORT_COUNTERS_DEQ_TOTAL): -+ case (e_FM_PORT_COUNTERS_DEQ_FROM_DEFAULT): -+ case (e_FM_PORT_COUNTERS_DEQ_CONFIRM): -+ /* check that counter is available for the port type */ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) -+ || (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)) -+ RETURN_ERROR( -+ MINOR, E_INVALID_STATE, -+ ("Requested counter is not available for Rx ports")); -+ case (e_FM_PORT_COUNTERS_ENQ_TOTAL): -+ bmiCounter = FALSE; -+ break; -+ default: /* BMI counters (or error - will be checked in BMI routine )*/ -+ bmiCounter = TRUE; -+ break; -+ } -+ -+ if (bmiCounter) -+ { -+ errCode = BmiPortCheckAndGetCounterType(p_FmPort, counter, &statsType, -+ &perfType, &isStats); -+ if (errCode != E_OK) -+ { -+ RETURN_ERROR(MINOR, errCode, NO_MSG); -+ } -+ if (isStats) -+ fman_port_set_stats_counter(&p_FmPort->port, statsType, value); -+ else -+ fman_port_set_perf_counter(&p_FmPort->port, perfType, value); -+ } -+ else /* QMI counter */ -+ { -+ /* check that counters are enabled */ -+ if (!(GET_UINT32(p_FmPort->port.qmi_regs->fmqm_pnc) -+ & QMI_PORT_CFG_EN_COUNTERS)) -+ { -+ RETURN_ERROR(MINOR, E_INVALID_STATE, -+ ("Requested counter was not enabled")); -+ } -+ -+ /* Set counter */ -+ switch (counter) -+ { -+ case (e_FM_PORT_COUNTERS_ENQ_TOTAL): -+ queueType = E_FMAN_PORT_ENQ_TOTAL; -+ break; -+ case (e_FM_PORT_COUNTERS_DEQ_TOTAL): -+ queueType = E_FMAN_PORT_DEQ_TOTAL; -+ break; -+ case (e_FM_PORT_COUNTERS_DEQ_FROM_DEFAULT): -+ queueType = E_FMAN_PORT_DEQ_FROM_DFLT; -+ break; -+ case (e_FM_PORT_COUNTERS_DEQ_CONFIRM): -+ queueType = E_FMAN_PORT_DEQ_CONFIRM; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("Requested counter is not available")); -+ } -+ -+ fman_port_set_qmi_counter(&p_FmPort->port, queueType, value); -+ } -+ -+ return E_OK; -+} -+ -+uint32_t FM_PORT_GetAllocBufCounter(t_Handle h_FmPort, uint8_t poolId) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPort, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX) -+ && (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)) -+ { -+ REPORT_ERROR(MINOR, E_INVALID_STATE, ("Requested counter is not available for non-Rx ports")); -+ return 0; -+ } -+ return fman_port_get_bpool_counter(&p_FmPort->port, poolId); -+} -+ -+t_Error FM_PORT_ModifyAllocBufCounter(t_Handle h_FmPort, uint8_t poolId, -+ uint32_t value) -+{ -+ t_FmPort *p_FmPort = (t_FmPort *)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX) -+ && (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)) -+ RETURN_ERROR( MINOR, E_INVALID_STATE, -+ ("Requested counter is not available for non-Rx ports")); -+ -+ fman_port_set_bpool_counter(&p_FmPort->port, poolId, value); -+ return E_OK; -+} -+bool FM_PORT_IsStalled(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_Error err; -+ bool isStalled; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmPort, E_INVALID_HANDLE, FALSE); -+ SANITY_CHECK_RETURN_VALUE(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE, -+ FALSE); -+ -+ err = FmIsPortStalled(p_FmPort->h_Fm, p_FmPort->hardwarePortId, &isStalled); -+ if (err != E_OK) -+ { -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ return TRUE; -+ } -+ return isStalled; -+} -+ -+t_Error FM_PORT_ReleaseStalled(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ return FmResumeStalledPort(p_FmPort->h_Fm, p_FmPort->hardwarePortId); -+} -+ -+t_Error FM_PORT_SetRxL4ChecksumVerify(t_Handle h_FmPort, bool l4Checksum) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ int err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for Rx ports only")); -+ -+ if (l4Checksum) -+ err = fman_port_modify_rx_fd_bits( -+ &p_FmPort->port, (uint8_t)(BMI_PORT_RFNE_FRWD_DCL4C >> 24), -+ TRUE); -+ else -+ err = fman_port_modify_rx_fd_bits( -+ &p_FmPort->port, (uint8_t)(BMI_PORT_RFNE_FRWD_DCL4C >> 24), -+ FALSE); -+ if (err != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fman_port_modify_rx_fd_bits")); -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+/* API Run-time PCD Control unit functions */ -+/*****************************************************************************/ -+ -+#if (DPAA_VERSION >= 11) -+t_Error FM_PORT_VSPAlloc(t_Handle h_FmPort, t_FmPortVSPAllocParams *p_VSPParams) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_Error err = E_OK; -+ volatile uint32_t *p_BmiStorageProfileId = NULL, *p_BmiVspe = NULL; -+ uint32_t tmpReg = 0, tmp = 0; -+ uint16_t hwStoragePrflId; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->h_Fm, E_INVALID_HANDLE); -+ /*for numOfProfiles = 0 don't call this function*/ -+ SANITY_CHECK_RETURN_ERROR(p_VSPParams->numOfProfiles, E_INVALID_VALUE); -+ /*dfltRelativeId should be in the range of numOfProfiles*/ -+ SANITY_CHECK_RETURN_ERROR( -+ p_VSPParams->dfltRelativeId < p_VSPParams->numOfProfiles, -+ E_INVALID_VALUE); -+ /*p_FmPort should be from Rx type or OP*/ -+ SANITY_CHECK_RETURN_ERROR( -+ ((p_FmPort->portType == e_FM_PORT_TYPE_RX_10G) || (p_FmPort->portType == e_FM_PORT_TYPE_RX) || (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)), -+ E_INVALID_VALUE); -+ /*port should be disabled*/ -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->enabled, E_INVALID_STATE); -+ /*if its called for Rx port relevant Tx Port should be passed (initialized) too and it should be disabled*/ -+ SANITY_CHECK_RETURN_ERROR( -+ ((p_VSPParams->h_FmTxPort && !((t_FmPort *)(p_VSPParams->h_FmTxPort))->enabled) || (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)), -+ E_INVALID_VALUE); -+ /*should be called before SetPCD - this port should be without PCD*/ -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->pcdEngines, E_INVALID_STATE); -+ -+ /*alloc window of VSPs for this port*/ -+ err = FmVSPAllocForPort(p_FmPort->h_Fm, p_FmPort->portType, -+ p_FmPort->portId, p_VSPParams->numOfProfiles); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ /*get absolute VSP ID for dfltRelative*/ -+ err = FmVSPGetAbsoluteProfileId(p_FmPort->h_Fm, p_FmPort->portType, -+ p_FmPort->portId, -+ p_VSPParams->dfltRelativeId, -+ &hwStoragePrflId); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ /*fill relevant registers for p_FmPort and relative TxPort in the case p_FmPort from Rx type*/ -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX_10G): -+ case (e_FM_PORT_TYPE_RX): -+ p_BmiStorageProfileId = -+ &(((t_FmPort *)(p_VSPParams->h_FmTxPort))->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tcfqid); -+ p_BmiVspe = -+ &(((t_FmPort *)(p_VSPParams->h_FmTxPort))->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tfne); -+ -+ tmpReg = GET_UINT32(*p_BmiStorageProfileId) & ~BMI_SP_ID_MASK; -+ tmpReg |= (uint32_t)hwStoragePrflId << BMI_SP_ID_SHIFT; -+ WRITE_UINT32(*p_BmiStorageProfileId, tmpReg); -+ -+ tmpReg = GET_UINT32(*p_BmiVspe); -+ WRITE_UINT32(*p_BmiVspe, tmpReg | BMI_SP_EN); -+ -+ p_BmiStorageProfileId = -+ &p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfqid; -+ p_BmiVspe = &p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rpp; -+ hwStoragePrflId = p_VSPParams->dfltRelativeId; -+ break; -+ -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ tmpReg = NIA_ENG_BMI | NIA_BMI_AC_FETCH_ALL_FRAME; -+ WRITE_UINT32( p_FmPort->p_FmPortQmiRegs->nonRxQmiRegs.fmqm_pndn, -+ tmpReg); -+ -+ p_BmiStorageProfileId = -+ &p_FmPort->p_FmPortBmiRegs->ohPortBmiRegs.fmbm_ofqid; -+ p_BmiVspe = &p_FmPort->p_FmPortBmiRegs->ohPortBmiRegs.fmbm_opp; -+ tmp |= BMI_EBD_EN; -+ break; -+ -+ default: -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("available for Rx and offline parsing ports only")); -+ } -+ -+ p_FmPort->vspe = TRUE; -+ p_FmPort->dfltRelativeId = p_VSPParams->dfltRelativeId; -+ -+ tmpReg = GET_UINT32(*p_BmiStorageProfileId) & ~BMI_SP_ID_MASK; -+ tmpReg |= (uint32_t)hwStoragePrflId << BMI_SP_ID_SHIFT; -+ WRITE_UINT32(*p_BmiStorageProfileId, tmpReg); -+ -+ tmpReg = GET_UINT32(*p_BmiVspe); -+ WRITE_UINT32(*p_BmiVspe, tmpReg | BMI_SP_EN | tmp); -+ return E_OK; -+} -+#endif /* (DPAA_VERSION >= 11) */ -+ -+t_Error FM_PORT_PcdPlcrAllocProfiles(t_Handle h_FmPort, uint16_t numOfProfiles) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_Error err = E_OK; -+ -+ p_FmPort->h_FmPcd = FmGetPcdHandle(p_FmPort->h_Fm); -+ ASSERT_COND(p_FmPort->h_FmPcd); -+ -+ if (!TRY_LOCK(p_FmPort->h_Spinlock, &p_FmPort->lock)) -+ { -+ DBG(TRACE, ("FM Port Try Lock - BUSY")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ if (numOfProfiles) -+ { -+ err = FmPcdPlcrAllocProfiles(p_FmPort->h_FmPcd, -+ p_FmPort->hardwarePortId, numOfProfiles); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ /* set the port handle within the PCD policer, even if no profiles defined */ -+ FmPcdPortRegister(p_FmPort->h_FmPcd, h_FmPort, p_FmPort->hardwarePortId); -+ -+ RELEASE_LOCK(p_FmPort->lock); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_PcdPlcrFreeProfiles(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_Error err = E_OK; -+ -+ if (!TRY_LOCK(p_FmPort->h_Spinlock, &p_FmPort->lock)) -+ { -+ DBG(TRACE, ("FM Port Try Lock - BUSY")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = FmPcdPlcrFreeProfiles(p_FmPort->h_FmPcd, p_FmPort->hardwarePortId); -+ -+ RELEASE_LOCK(p_FmPort->lock); -+ -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_PcdKgModifyInitialScheme(t_Handle h_FmPort, -+ t_FmPcdKgSchemeSelect *p_FmPcdKgScheme) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ volatile uint32_t *p_BmiHpnia = NULL; -+ uint32_t tmpReg; -+ uint8_t relativeSchemeId; -+ uint8_t physicalSchemeId; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->pcdEngines & FM_PCD_KG, -+ E_INVALID_STATE); -+ -+ tmpReg = (uint32_t)((p_FmPort->pcdEngines & FM_PCD_CC) ? NIA_KG_CC_EN : 0); -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX_10G): -+ case (e_FM_PORT_TYPE_RX): -+ p_BmiHpnia = &p_FmPort->port.bmi_regs->rx.fmbm_rfpne; -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ p_BmiHpnia = &p_FmPort->port.bmi_regs->oh.fmbm_ofpne; -+ break; -+ default: -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("available for Rx and offline parsing ports only")); -+ } -+ -+ if (!TRY_LOCK(p_FmPort->h_Spinlock, &p_FmPort->lock)) -+ { -+ DBG(TRACE, ("FM Port Try Lock - BUSY")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ /* if we want to change to direct scheme, we need to check that this scheme is valid */ -+ if (p_FmPcdKgScheme->direct) -+ { -+ physicalSchemeId = FmPcdKgGetSchemeId(p_FmPcdKgScheme->h_DirectScheme); -+ /* check that this scheme is bound to this port */ -+ if (!(p_FmPort->schemesPerPortVector -+ & (uint32_t)(1 << (31 - (uint32_t)physicalSchemeId)))) -+ { -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR( -+ MAJOR, E_INVALID_STATE, -+ ("called with a scheme that is not bound to this port")); -+ } -+ -+ relativeSchemeId = FmPcdKgGetRelativeSchemeId(p_FmPort->h_FmPcd, -+ physicalSchemeId); -+ if (relativeSchemeId >= FM_PCD_KG_NUM_OF_SCHEMES) -+ { -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, -+ ("called with invalid Scheme ")); -+ } -+ -+ if (!FmPcdKgIsSchemeValidSw(p_FmPcdKgScheme->h_DirectScheme)) -+ { -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("called with uninitialized Scheme ")); -+ } -+ -+ WRITE_UINT32( -+ *p_BmiHpnia, -+ NIA_ENG_KG | tmpReg | NIA_KG_DIRECT | (uint32_t)physicalSchemeId); -+ } -+ else -+ /* change to indirect scheme */ -+ WRITE_UINT32(*p_BmiHpnia, NIA_ENG_KG | tmpReg); -+ RELEASE_LOCK(p_FmPort->lock); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_PcdPlcrModifyInitialProfile(t_Handle h_FmPort, -+ t_Handle h_Profile) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ volatile uint32_t *p_BmiNia; -+ volatile uint32_t *p_BmiHpnia; -+ uint32_t tmpReg; -+ uint16_t absoluteProfileId = FmPcdPlcrProfileGetAbsoluteId(h_Profile); -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->pcdEngines & FM_PCD_PLCR, -+ E_INVALID_STATE); -+ -+ /* check relevance of this routine - only when policer is used -+ directly after BMI or Parser */ -+ if ((p_FmPort->pcdEngines & FM_PCD_KG) -+ || (p_FmPort->pcdEngines & FM_PCD_CC)) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("relevant only when PCD support mode is e_FM_PCD_SUPPORT_PLCR_ONLY or e_FM_PCD_SUPPORT_PRS_AND_PLCR")); -+ -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX_10G): -+ case (e_FM_PORT_TYPE_RX): -+ p_BmiNia = &p_FmPort->port.bmi_regs->rx.fmbm_rfne; -+ p_BmiHpnia = &p_FmPort->port.bmi_regs->rx.fmbm_rfpne; -+ tmpReg = GET_UINT32(*p_BmiNia) & BMI_RFNE_FDCS_MASK; -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ p_BmiNia = &p_FmPort->port.bmi_regs->oh.fmbm_ofne; -+ p_BmiHpnia = &p_FmPort->port.bmi_regs->oh.fmbm_ofpne; -+ tmpReg = 0; -+ break; -+ default: -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("available for Rx and offline parsing ports only")); -+ } -+ -+ if (!TRY_LOCK(p_FmPort->h_Spinlock, &p_FmPort->lock)) -+ { -+ DBG(TRACE, ("FM Port Try Lock - BUSY")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ if (!FmPcdPlcrIsProfileValid(p_FmPort->h_FmPcd, absoluteProfileId)) -+ { -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, ("Invalid profile")); -+ } -+ -+ tmpReg |= (uint32_t)(NIA_ENG_PLCR | NIA_PLCR_ABSOLUTE | absoluteProfileId); -+ -+ if (p_FmPort->pcdEngines & FM_PCD_PRS) /* e_FM_PCD_SUPPORT_PRS_AND_PLCR */ -+ { -+ /* update BMI HPNIA */ -+ WRITE_UINT32(*p_BmiHpnia, tmpReg); -+ } -+ else /* e_FM_PCD_SUPPORT_PLCR_ONLY */ -+ { -+ /* rfne may contain FDCS bits, so first we read them. */ -+ tmpReg |= (GET_UINT32(*p_BmiNia) & BMI_RFNE_FDCS_MASK); -+ /* update BMI NIA */ -+ WRITE_UINT32(*p_BmiNia, tmpReg); -+ }RELEASE_LOCK(p_FmPort->lock); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_PcdCcModifyTree(t_Handle h_FmPort, t_Handle h_CcTree) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_Error err = E_OK; -+ volatile uint32_t *p_BmiCcBase = NULL; -+ volatile uint32_t *p_BmiNia = NULL; -+ uint32_t ccTreePhysOffset; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(h_CcTree, E_INVALID_HANDLE); -+ -+ if (p_FmPort->imEn) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for non-independent mode ports only")); -+ -+ /* get PCD registers pointers */ -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX_10G): -+ case (e_FM_PORT_TYPE_RX): -+ p_BmiNia = &p_FmPort->port.bmi_regs->rx.fmbm_rfne; -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ p_BmiNia = &p_FmPort->port.bmi_regs->oh.fmbm_ofne; -+ break; -+ default: -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("available for Rx and offline parsing ports only")); -+ } -+ -+ /* check that current NIA is BMI to BMI */ -+ if ((GET_UINT32(*p_BmiNia) & ~BMI_RFNE_FDCS_MASK) -+ != GET_NIA_BMI_AC_ENQ_FRAME(p_FmPort->h_FmPcd)) -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("may be called only for ports in BMI-to-BMI state.")); -+ -+ if (p_FmPort->pcdEngines & FM_PCD_CC) -+ { -+ if (p_FmPort->h_IpReassemblyManip) -+ { -+ err = FmPcdCcTreeAddIPR(p_FmPort->h_FmPcd, h_CcTree, NULL, -+ p_FmPort->h_IpReassemblyManip, FALSE); -+ if (err != E_OK) -+ { -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ } -+ else -+ if (p_FmPort->h_CapwapReassemblyManip) -+ { -+ err = FmPcdCcTreeAddCPR(p_FmPort->h_FmPcd, h_CcTree, NULL, -+ p_FmPort->h_CapwapReassemblyManip, -+ FALSE); -+ if (err != E_OK) -+ { -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ } -+ switch (p_FmPort->portType) -+ { -+ case (e_FM_PORT_TYPE_RX_10G): -+ case (e_FM_PORT_TYPE_RX): -+ p_BmiCcBase = &p_FmPort->port.bmi_regs->rx.fmbm_rccb; -+ break; -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ p_BmiCcBase = &p_FmPort->port.bmi_regs->oh.fmbm_occb; -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Invalid port type")); -+ } -+ -+ if (!TRY_LOCK(p_FmPort->h_Spinlock, &p_FmPort->lock)) -+ { -+ DBG(TRACE, ("FM Port Try Lock - BUSY")); -+ return ERROR_CODE(E_BUSY); -+ } -+ err = FmPcdCcBindTree(p_FmPort->h_FmPcd, NULL, h_CcTree, -+ &ccTreePhysOffset, h_FmPort); -+ if (err) -+ { -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ }WRITE_UINT32(*p_BmiCcBase, ccTreePhysOffset); -+ -+ p_FmPort->ccTreeId = h_CcTree; -+ RELEASE_LOCK(p_FmPort->lock); -+ } -+ else -+ RETURN_ERROR( MAJOR, E_INVALID_STATE, -+ ("Coarse Classification not defined for this port.")); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_AttachPCD(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ if (p_FmPort->imEn) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for non-independent mode ports only")); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("available for Rx and offline parsing ports only")); -+ -+ if (!TRY_LOCK(p_FmPort->h_Spinlock, &p_FmPort->lock)) -+ { -+ DBG(TRACE, ("FM Port Try Lock - BUSY")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ if (p_FmPort->h_ReassemblyTree) -+ p_FmPort->pcdEngines |= FM_PCD_CC; -+ -+ err = AttachPCD(h_FmPort); -+ RELEASE_LOCK(p_FmPort->lock); -+ -+ return err; -+} -+ -+t_Error FM_PORT_DetachPCD(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ if (p_FmPort->imEn) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for non-independent mode ports only")); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("available for Rx and offline parsing ports only")); -+ -+ if (!TRY_LOCK(p_FmPort->h_Spinlock, &p_FmPort->lock)) -+ { -+ DBG(TRACE, ("FM Port Try Lock - BUSY")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = DetachPCD(h_FmPort); -+ if (err != E_OK) -+ { -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ if (p_FmPort->h_ReassemblyTree) -+ p_FmPort->pcdEngines &= ~FM_PCD_CC; -+ RELEASE_LOCK(p_FmPort->lock); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_SetPCD(t_Handle h_FmPort, t_FmPortPcdParams *p_PcdParam) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_Error err = E_OK; -+ t_FmPortPcdParams modifiedPcdParams, *p_PcdParams; -+ t_FmPcdCcTreeParams *p_FmPcdCcTreeParams; -+ t_FmPortPcdCcParams fmPortPcdCcParams; -+ t_FmPortGetSetCcParams fmPortGetSetCcParams; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_PcdParam, E_NULL_POINTER); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ if (p_FmPort->imEn) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for non-independent mode ports only")); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("available for Rx and offline parsing ports only")); -+ -+ if (!TRY_LOCK(p_FmPort->h_Spinlock, &p_FmPort->lock)) -+ { -+ DBG(TRACE, ("FM Port Try Lock - BUSY")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ p_FmPort->h_FmPcd = FmGetPcdHandle(p_FmPort->h_Fm); -+ ASSERT_COND(p_FmPort->h_FmPcd); -+ -+ if (p_PcdParam->p_CcParams && !p_PcdParam->p_CcParams->h_CcTree) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, -+ ("Tree handle must be given if CC is required")); -+ -+ memcpy(&modifiedPcdParams, p_PcdParam, sizeof(t_FmPortPcdParams)); -+ p_PcdParams = &modifiedPcdParams; -+ if ((p_PcdParams->h_IpReassemblyManip) -+#if (DPAA_VERSION >= 11) -+ || (p_PcdParams->h_CapwapReassemblyManip) -+#endif /* (DPAA_VERSION >= 11) */ -+ ) -+ { -+ if ((p_PcdParams->pcdSupport != e_FM_PORT_PCD_SUPPORT_PRS_AND_KG) -+ && (p_PcdParams->pcdSupport -+ != e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_CC) -+ && (p_PcdParams->pcdSupport -+ != e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_CC_AND_PLCR) -+ && (p_PcdParams->pcdSupport -+ != e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_PLCR)) -+ { -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR( MAJOR, E_INVALID_STATE, -+ ("pcdSupport must have KG for supporting Reassembly")); -+ } -+ p_FmPort->h_IpReassemblyManip = p_PcdParams->h_IpReassemblyManip; -+#if (DPAA_VERSION >= 11) -+ if ((p_PcdParams->h_IpReassemblyManip) -+ && (p_PcdParams->h_CapwapReassemblyManip)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("Either IP-R or CAPWAP-R is allowed")); -+ if ((p_PcdParams->h_CapwapReassemblyManip) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("CAPWAP-R is allowed only on offline-port")); -+ if (p_PcdParams->h_CapwapReassemblyManip) -+ p_FmPort->h_CapwapReassemblyManip = -+ p_PcdParams->h_CapwapReassemblyManip; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ if (!p_PcdParams->p_CcParams) -+ { -+ if (!((p_PcdParams->pcdSupport == e_FM_PORT_PCD_SUPPORT_PRS_AND_KG) -+ || (p_PcdParams->pcdSupport -+ == e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_PLCR))) -+ { -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_STATE, -+ ("PCD initialization structure is not consistent with pcdSupport")); -+ } -+ -+ /* No user-tree, need to build internal tree */ -+ p_FmPcdCcTreeParams = (t_FmPcdCcTreeParams*)XX_Malloc( -+ sizeof(t_FmPcdCcTreeParams)); -+ if (!p_FmPcdCcTreeParams) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("p_FmPcdCcTreeParams")); -+ memset(p_FmPcdCcTreeParams, 0, sizeof(t_FmPcdCcTreeParams)); -+ p_FmPcdCcTreeParams->h_NetEnv = p_PcdParams->h_NetEnv; -+ p_FmPort->h_ReassemblyTree = FM_PCD_CcRootBuild( -+ p_FmPort->h_FmPcd, p_FmPcdCcTreeParams); -+ -+ if (!p_FmPort->h_ReassemblyTree) -+ { -+ RELEASE_LOCK(p_FmPort->lock); -+ XX_Free(p_FmPcdCcTreeParams); -+ RETURN_ERROR( MAJOR, E_INVALID_HANDLE, -+ ("FM_PCD_CcBuildTree for Reassembly failed")); -+ } -+ if (p_PcdParams->pcdSupport == e_FM_PORT_PCD_SUPPORT_PRS_AND_KG) -+ p_PcdParams->pcdSupport = -+ e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_CC; -+ else -+ p_PcdParams->pcdSupport = -+ e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_CC_AND_PLCR; -+ -+ memset(&fmPortPcdCcParams, 0, sizeof(t_FmPortPcdCcParams)); -+ fmPortPcdCcParams.h_CcTree = p_FmPort->h_ReassemblyTree; -+ p_PcdParams->p_CcParams = &fmPortPcdCcParams; -+ XX_Free(p_FmPcdCcTreeParams); -+ } -+ -+ if (p_FmPort->h_IpReassemblyManip) -+ err = FmPcdCcTreeAddIPR(p_FmPort->h_FmPcd, -+ p_PcdParams->p_CcParams->h_CcTree, -+ p_PcdParams->h_NetEnv, -+ p_FmPort->h_IpReassemblyManip, TRUE); -+#if (DPAA_VERSION >= 11) -+ else -+ if (p_FmPort->h_CapwapReassemblyManip) -+ err = FmPcdCcTreeAddCPR(p_FmPort->h_FmPcd, -+ p_PcdParams->p_CcParams->h_CcTree, -+ p_PcdParams->h_NetEnv, -+ p_FmPort->h_CapwapReassemblyManip, -+ TRUE); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ if (err != E_OK) -+ { -+ if (p_FmPort->h_ReassemblyTree) -+ { -+ FM_PCD_CcRootDelete(p_FmPort->h_ReassemblyTree); -+ p_FmPort->h_ReassemblyTree = NULL; -+ }RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ } -+ -+ if (!FmPcdLockTryLockAll(p_FmPort->h_FmPcd)) -+ { -+ if (p_FmPort->h_ReassemblyTree) -+ { -+ FM_PCD_CcRootDelete(p_FmPort->h_ReassemblyTree); -+ p_FmPort->h_ReassemblyTree = NULL; -+ }RELEASE_LOCK(p_FmPort->lock); -+ DBG(TRACE, ("Try LockAll - BUSY")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = SetPcd(h_FmPort, p_PcdParams); -+ if (err) -+ { -+ if (p_FmPort->h_ReassemblyTree) -+ { -+ FM_PCD_CcRootDelete(p_FmPort->h_ReassemblyTree); -+ p_FmPort->h_ReassemblyTree = NULL; -+ } -+ FmPcdLockUnlockAll(p_FmPort->h_FmPcd); -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ if ((p_FmPort->pcdEngines & FM_PCD_PRS) -+ && (p_PcdParams->p_PrsParams->includeInPrsStatistics)) -+ { -+ err = FmPcdPrsIncludePortInStatistics(p_FmPort->h_FmPcd, -+ p_FmPort->hardwarePortId, TRUE); -+ if (err) -+ { -+ DeletePcd(p_FmPort); -+ if (p_FmPort->h_ReassemblyTree) -+ { -+ FM_PCD_CcRootDelete(p_FmPort->h_ReassemblyTree); -+ p_FmPort->h_ReassemblyTree = NULL; -+ } -+ FmPcdLockUnlockAll(p_FmPort->h_FmPcd); -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ p_FmPort->includeInPrsStatistics = TRUE; -+ } -+ -+ FmPcdIncNetEnvOwners(p_FmPort->h_FmPcd, p_FmPort->netEnvId); -+ -+ if (FmPcdIsAdvancedOffloadSupported(p_FmPort->h_FmPcd)) -+ { -+ memset(&fmPortGetSetCcParams, 0, sizeof(t_FmPortGetSetCcParams)); -+ -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ { -+#ifdef FM_KG_ERASE_FLOW_ID_ERRATA_FMAN_SW004 -+ if ((p_FmPort->fmRevInfo.majorRev < 6) && -+ (p_FmPort->pcdEngines & FM_PCD_KG)) -+ { -+ int i; -+ for (i = 0; ip_KgParams->numOfSchemes; i++) -+ /* The following function must be locked */ -+ FmPcdKgCcGetSetParams(p_FmPort->h_FmPcd, -+ p_PcdParams->p_KgParams->h_Schemes[i], -+ UPDATE_KG_NIA_CC_WA, -+ 0); -+ } -+#endif /* FM_KG_ERASE_FLOW_ID_ERRATA_FMAN_SW004 */ -+ -+#if (DPAA_VERSION >= 11) -+ { -+ t_FmPcdCtrlParamsPage *p_ParamsPage; -+ -+ FmPortSetGprFunc(p_FmPort, e_FM_PORT_GPR_MURAM_PAGE, -+ (void**)&p_ParamsPage); -+ ASSERT_COND(p_ParamsPage); -+ WRITE_UINT32(p_ParamsPage->postBmiFetchNia, -+ p_FmPort->savedBmiNia); -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ /* Set post-bmi-fetch nia */ -+ p_FmPort->savedBmiNia &= BMI_RFNE_FDCS_MASK; -+ p_FmPort->savedBmiNia |= (NIA_FM_CTL_AC_POST_BMI_FETCH -+ | NIA_ENG_FM_CTL); -+ -+ /* Set pre-bmi-fetch nia */ -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_NIA_PNDN; -+#if (DPAA_VERSION >= 11) -+ fmPortGetSetCcParams.setCcParams.nia = -+ (NIA_FM_CTL_AC_PRE_BMI_FETCH_FULL_FRAME | NIA_ENG_FM_CTL); -+#else -+ fmPortGetSetCcParams.setCcParams.nia = (NIA_FM_CTL_AC_PRE_BMI_FETCH_HEADER | NIA_ENG_FM_CTL); -+#endif /* (DPAA_VERSION >= 11) */ -+ if ((err = FmPortGetSetCcParams(p_FmPort, &fmPortGetSetCcParams)) -+ != E_OK) -+ { -+ DeletePcd(p_FmPort); -+ if (p_FmPort->h_ReassemblyTree) -+ { -+ FM_PCD_CcRootDelete(p_FmPort->h_ReassemblyTree); -+ p_FmPort->h_ReassemblyTree = NULL; -+ } -+ FmPcdLockUnlockAll(p_FmPort->h_FmPcd); -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ } -+ -+ FmPcdLockUnlockAll(p_FmPort->h_FmPcd); -+ -+ /* Set pop-to-next-step nia */ -+#if (DPAA_VERSION == 10) -+ if (p_FmPort->fmRevInfo.majorRev < 6) -+ { -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_NIA_PNEN; -+ fmPortGetSetCcParams.setCcParams.nia = NIA_FM_CTL_AC_POP_TO_N_STEP | NIA_ENG_FM_CTL; -+ } -+ else -+ { -+#endif /* (DPAA_VERSION == 10) */ -+ fmPortGetSetCcParams.getCcParams.type = GET_NIA_FPNE; -+#if (DPAA_VERSION == 10) -+ } -+#endif /* (DPAA_VERSION == 10) */ -+ if ((err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams)) -+ != E_OK) -+ { -+ DeletePcd(p_FmPort); -+ if (p_FmPort->h_ReassemblyTree) -+ { -+ FM_PCD_CcRootDelete(p_FmPort->h_ReassemblyTree); -+ p_FmPort->h_ReassemblyTree = NULL; -+ }RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ /* Set post-bmi-prepare-to-enq nia */ -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_NIA_FENE; -+ fmPortGetSetCcParams.setCcParams.nia = (NIA_FM_CTL_AC_POST_BMI_ENQ -+ | NIA_ENG_FM_CTL); -+ if ((err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams)) -+ != E_OK) -+ { -+ DeletePcd(p_FmPort); -+ if (p_FmPort->h_ReassemblyTree) -+ { -+ FM_PCD_CcRootDelete(p_FmPort->h_ReassemblyTree); -+ p_FmPort->h_ReassemblyTree = NULL; -+ }RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ if ((p_FmPort->h_IpReassemblyManip) -+ || (p_FmPort->h_CapwapReassemblyManip)) -+ { -+#if (DPAA_VERSION == 10) -+ if (p_FmPort->fmRevInfo.majorRev < 6) -+ { -+ /* Overwrite post-bmi-prepare-to-enq nia */ -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_NIA_FENE; -+ fmPortGetSetCcParams.setCcParams.nia = (NIA_FM_CTL_AC_POST_BMI_ENQ_ORR | NIA_ENG_FM_CTL | NIA_ORDER_RESTOR); -+ fmPortGetSetCcParams.setCcParams.overwrite = TRUE; -+ } -+ else -+ { -+#endif /* (DPAA_VERSION == 10) */ -+ /* Set the ORR bit (for order-restoration) */ -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_NIA_FPNE; -+ fmPortGetSetCcParams.setCcParams.nia = -+ fmPortGetSetCcParams.getCcParams.nia | NIA_ORDER_RESTOR; -+#if (DPAA_VERSION == 10) -+ } -+#endif /* (DPAA_VERSION == 10) */ -+ if ((err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams)) -+ != E_OK) -+ { -+ DeletePcd(p_FmPort); -+ if (p_FmPort->h_ReassemblyTree) -+ { -+ FM_PCD_CcRootDelete(p_FmPort->h_ReassemblyTree); -+ p_FmPort->h_ReassemblyTree = NULL; -+ }RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ } -+ } -+ else -+ FmPcdLockUnlockAll(p_FmPort->h_FmPcd); -+ -+#if (DPAA_VERSION >= 11) -+ { -+ t_FmPcdCtrlParamsPage *p_ParamsPage; -+ -+ memset(&fmPortGetSetCcParams, 0, sizeof(t_FmPortGetSetCcParams)); -+ -+ fmPortGetSetCcParams.setCcParams.type = UPDATE_NIA_CMNE; -+ if (FmPcdIsAdvancedOffloadSupported(p_FmPort->h_FmPcd)) -+ fmPortGetSetCcParams.setCcParams.nia = NIA_FM_CTL_AC_POP_TO_N_STEP -+ | NIA_ENG_FM_CTL; -+ else -+ fmPortGetSetCcParams.setCcParams.nia = -+ NIA_FM_CTL_AC_NO_IPACC_POP_TO_N_STEP | NIA_ENG_FM_CTL; -+ if ((err = FmPortGetSetCcParams(h_FmPort, &fmPortGetSetCcParams)) -+ != E_OK) -+ { -+ DeletePcd(p_FmPort); -+ if (p_FmPort->h_ReassemblyTree) -+ { -+ FM_PCD_CcRootDelete(p_FmPort->h_ReassemblyTree); -+ p_FmPort->h_ReassemblyTree = NULL; -+ }RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ FmPortSetGprFunc(p_FmPort, e_FM_PORT_GPR_MURAM_PAGE, -+ (void**)&p_ParamsPage); -+ ASSERT_COND(p_ParamsPage); -+ -+ if (FmPcdIsAdvancedOffloadSupported(p_FmPort->h_FmPcd)) -+ WRITE_UINT32( -+ p_ParamsPage->misc, -+ GET_UINT32(p_ParamsPage->misc) | FM_CTL_PARAMS_PAGE_OFFLOAD_SUPPORT_EN); -+ -+ if ((p_FmPort->h_IpReassemblyManip) -+ || (p_FmPort->h_CapwapReassemblyManip)) -+ { -+ if (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ WRITE_UINT32( -+ p_ParamsPage->discardMask, -+ GET_UINT32(p_FmPort->p_FmPortBmiRegs->ohPortBmiRegs.fmbm_ofsdm)); -+ else -+ WRITE_UINT32( -+ p_ParamsPage->discardMask, -+ GET_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfsdm)); -+ } -+#ifdef FM_ERROR_VSP_NO_MATCH_SW006 -+ if (p_FmPort->vspe) -+ WRITE_UINT32( -+ p_ParamsPage->misc, -+ GET_UINT32(p_ParamsPage->misc) | (p_FmPort->dfltRelativeId & FM_CTL_PARAMS_PAGE_ERROR_VSP_MASK)); -+#endif /* FM_ERROR_VSP_NO_MATCH_SW006 */ -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ err = AttachPCD(h_FmPort); -+ if (err) -+ { -+ DeletePcd(p_FmPort); -+ if (p_FmPort->h_ReassemblyTree) -+ { -+ FM_PCD_CcRootDelete(p_FmPort->h_ReassemblyTree); -+ p_FmPort->h_ReassemblyTree = NULL; -+ }RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ RELEASE_LOCK(p_FmPort->lock); -+ -+ return err; -+} -+ -+t_Error FM_PORT_DeletePCD(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ -+ if (p_FmPort->imEn) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, -+ ("available for non-independant mode ports only")); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ RETURN_ERROR( MAJOR, E_INVALID_OPERATION, -+ ("available for Rx and offline parsing ports only")); -+ -+ if (!TRY_LOCK(p_FmPort->h_Spinlock, &p_FmPort->lock)) -+ { -+ DBG(TRACE, ("FM Port Try Lock - BUSY")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = DetachPCD(h_FmPort); -+ if (err) -+ { -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ FmPcdDecNetEnvOwners(p_FmPort->h_FmPcd, p_FmPort->netEnvId); -+ -+ /* we do it anyway, instead of checking if included */ -+ if ((p_FmPort->pcdEngines & FM_PCD_PRS) && p_FmPort->includeInPrsStatistics) -+ { -+ FmPcdPrsIncludePortInStatistics(p_FmPort->h_FmPcd, -+ p_FmPort->hardwarePortId, FALSE); -+ p_FmPort->includeInPrsStatistics = FALSE; -+ } -+ -+ if (!FmPcdLockTryLockAll(p_FmPort->h_FmPcd)) -+ { -+ RELEASE_LOCK(p_FmPort->lock); -+ DBG(TRACE, ("Try LockAll - BUSY")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = DeletePcd(h_FmPort); -+ FmPcdLockUnlockAll(p_FmPort->h_FmPcd); -+ if (err) -+ { -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ if (p_FmPort->h_ReassemblyTree) -+ { -+ err = FM_PCD_CcRootDelete(p_FmPort->h_ReassemblyTree); -+ if (err) -+ { -+ RELEASE_LOCK(p_FmPort->lock); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ p_FmPort->h_ReassemblyTree = NULL; -+ }RELEASE_LOCK(p_FmPort->lock); -+ -+ return err; -+} -+ -+t_Error FM_PORT_PcdKgBindSchemes(t_Handle h_FmPort, -+ t_FmPcdPortSchemesParams *p_PortScheme) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_FmPcdKgInterModuleBindPortToSchemes schemeBind; -+ t_Error err = E_OK; -+ uint32_t tmpScmVec = 0; -+ int i; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->pcdEngines & FM_PCD_KG, -+ E_INVALID_STATE); -+ -+ schemeBind.netEnvId = p_FmPort->netEnvId; -+ schemeBind.hardwarePortId = p_FmPort->hardwarePortId; -+ schemeBind.numOfSchemes = p_PortScheme->numOfSchemes; -+ schemeBind.useClsPlan = p_FmPort->useClsPlan; -+ for (i = 0; i < schemeBind.numOfSchemes; i++) -+ { -+ schemeBind.schemesIds[i] = FmPcdKgGetSchemeId( -+ p_PortScheme->h_Schemes[i]); -+ /* build vector */ -+ tmpScmVec |= 1 << (31 - (uint32_t)schemeBind.schemesIds[i]); -+ } -+ -+ if (!TRY_LOCK(p_FmPort->h_Spinlock, &p_FmPort->lock)) -+ { -+ DBG(TRACE, ("FM Port Try Lock - BUSY")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = FmPcdKgBindPortToSchemes(p_FmPort->h_FmPcd, &schemeBind); -+ if (err == E_OK) -+ p_FmPort->schemesPerPortVector |= tmpScmVec; -+ -+#ifdef FM_KG_ERASE_FLOW_ID_ERRATA_FMAN_SW004 -+ if ((FmPcdIsAdvancedOffloadSupported(p_FmPort->h_FmPcd)) && -+ (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) && -+ (p_FmPort->fmRevInfo.majorRev < 6)) -+ { -+ for (i=0; inumOfSchemes; i++) -+ FmPcdKgCcGetSetParams(p_FmPort->h_FmPcd, p_PortScheme->h_Schemes[i], UPDATE_KG_NIA_CC_WA, 0); -+ } -+#endif /* FM_KG_ERASE_FLOW_ID_ERRATA_FMAN_SW004 */ -+ -+ RELEASE_LOCK(p_FmPort->lock); -+ -+ return err; -+} -+ -+t_Error FM_PORT_PcdKgUnbindSchemes(t_Handle h_FmPort, -+ t_FmPcdPortSchemesParams *p_PortScheme) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_FmPcdKgInterModuleBindPortToSchemes schemeBind; -+ t_Error err = E_OK; -+ uint32_t tmpScmVec = 0; -+ int i; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->pcdEngines & FM_PCD_KG, -+ E_INVALID_STATE); -+ -+ schemeBind.netEnvId = p_FmPort->netEnvId; -+ schemeBind.hardwarePortId = p_FmPort->hardwarePortId; -+ schemeBind.numOfSchemes = p_PortScheme->numOfSchemes; -+ for (i = 0; i < schemeBind.numOfSchemes; i++) -+ { -+ schemeBind.schemesIds[i] = FmPcdKgGetSchemeId( -+ p_PortScheme->h_Schemes[i]); -+ /* build vector */ -+ tmpScmVec |= 1 << (31 - (uint32_t)schemeBind.schemesIds[i]); -+ } -+ -+ if (!TRY_LOCK(p_FmPort->h_Spinlock, &p_FmPort->lock)) -+ { -+ DBG(TRACE, ("FM Port Try Lock - BUSY")); -+ return ERROR_CODE(E_BUSY); -+ } -+ -+ err = FmPcdKgUnbindPortToSchemes(p_FmPort->h_FmPcd, &schemeBind); -+ if (err == E_OK) -+ p_FmPort->schemesPerPortVector &= ~tmpScmVec; -+ RELEASE_LOCK(p_FmPort->lock); -+ -+ return err; -+} -+ -+t_Error FM_PORT_AddCongestionGrps(t_Handle h_FmPort, -+ t_FmPortCongestionGrps *p_CongestionGrps) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ uint8_t priorityTmpArray[FM_PORT_NUM_OF_CONGESTION_GRPS]; -+ uint8_t mod, index; -+ uint32_t i, grpsMap[FMAN_PORT_CG_MAP_NUM]; -+ int err; -+#if (DPAA_VERSION >= 11) -+ int j; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ -+ /* un-necessary check of the indexes; probably will be needed in the future when there -+ will be more CGs available .... -+ for (i=0; inumOfCongestionGrpsToConsider; i++) -+ if (p_CongestionGrps->congestionGrpsToConsider[i] >= FM_PORT_NUM_OF_CONGESTION_GRPS) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("CG id!")); -+ */ -+ -+#ifdef FM_NO_OP_OBSERVED_CGS -+ if ((p_FmPort->fmRevInfo.majorRev != 4) && -+ (p_FmPort->fmRevInfo.majorRev < 6)) -+ { -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) && -+ (p_FmPort->portType != e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Available for Rx ports only")); -+ } -+ else -+#endif /* FM_NO_OP_OBSERVED_CGS */ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, -+ ("Available for Rx & OP ports only")); -+ -+ /* Prepare groups map array */ -+ memset(grpsMap, 0, FMAN_PORT_CG_MAP_NUM * sizeof(uint32_t)); -+ for (i = 0; i < p_CongestionGrps->numOfCongestionGrpsToConsider; i++) -+ { -+ index = (uint8_t)(p_CongestionGrps->congestionGrpsToConsider[i] / 32); -+ mod = (uint8_t)(p_CongestionGrps->congestionGrpsToConsider[i] % 32); -+ if (p_FmPort->fmRevInfo.majorRev != 4) -+ grpsMap[7 - index] |= (uint32_t)(1 << mod); -+ else -+ grpsMap[0] |= (uint32_t)(1 << mod); -+ } -+ -+ memset(&priorityTmpArray, 0, -+ FM_PORT_NUM_OF_CONGESTION_GRPS * sizeof(uint8_t)); -+ -+ for (i = 0; i < p_CongestionGrps->numOfCongestionGrpsToConsider; i++) -+ { -+#if (DPAA_VERSION >= 11) -+ for (j = 0; j < FM_MAX_NUM_OF_PFC_PRIORITIES; j++) -+ if (p_CongestionGrps->pfcPrioritiesEn[i][j]) -+ priorityTmpArray[p_CongestionGrps->congestionGrpsToConsider[i]] |= -+ (0x01 << (FM_MAX_NUM_OF_PFC_PRIORITIES - j - 1)); -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ -+#if (DPAA_VERSION >= 11) -+ for (i = 0; i < FM_PORT_NUM_OF_CONGESTION_GRPS; i++) -+ { -+ err = FmSetCongestionGroupPFCpriority(p_FmPort->h_Fm, i, -+ priorityTmpArray[i]); -+ if (err) -+ return err; -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ err = fman_port_add_congestion_grps(&p_FmPort->port, grpsMap); -+ if (err != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fman_port_add_congestion_grps")); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_RemoveCongestionGrps(t_Handle h_FmPort, -+ t_FmPortCongestionGrps *p_CongestionGrps) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ uint8_t mod, index; -+ uint32_t i, grpsMap[FMAN_PORT_CG_MAP_NUM]; -+ int err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ -+ { -+#ifdef FM_NO_OP_OBSERVED_CGS -+ t_FmRevisionInfo revInfo; -+ -+ FM_GetRevision(p_FmPort->h_Fm, &revInfo); -+ if (revInfo.majorRev != 4) -+ { -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) && -+ (p_FmPort->portType != e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Available for Rx ports only")); -+ } -+ else -+#endif /* FM_NO_OP_OBSERVED_CGS */ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_RX) -+ && (p_FmPort->portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, -+ ("Available for Rx & OP ports only")); -+ } -+ -+ /* Prepare groups map array */ -+ memset(grpsMap, 0, FMAN_PORT_CG_MAP_NUM * sizeof(uint32_t)); -+ for (i = 0; i < p_CongestionGrps->numOfCongestionGrpsToConsider; i++) -+ { -+ index = (uint8_t)(p_CongestionGrps->congestionGrpsToConsider[i] / 32); -+ mod = (uint8_t)(p_CongestionGrps->congestionGrpsToConsider[i] % 32); -+ if (p_FmPort->fmRevInfo.majorRev != 4) -+ grpsMap[7 - index] |= (uint32_t)(1 << mod); -+ else -+ grpsMap[0] |= (uint32_t)(1 << mod); -+ } -+ -+#if (DPAA_VERSION >= 11) -+ for (i = 0; i < p_CongestionGrps->numOfCongestionGrpsToConsider; i++) -+ { -+ t_Error err = FmSetCongestionGroupPFCpriority( -+ p_FmPort->h_Fm, p_CongestionGrps->congestionGrpsToConsider[i], -+ 0); -+ if (err) -+ return err; -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ err = fman_port_remove_congestion_grps(&p_FmPort->port, grpsMap); -+ if (err != 0) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("fman_port_remove_congestion_grps")); -+ return E_OK; -+} -+ -+#if (DPAA_VERSION >= 11) -+t_Error FM_PORT_GetIPv4OptionsCount(t_Handle h_FmPort, -+ uint32_t *p_Ipv4OptionsCount) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR( -+ (p_FmPort->portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING), -+ E_INVALID_VALUE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_ParamsPage, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_Ipv4OptionsCount, E_NULL_POINTER); -+ -+ *p_Ipv4OptionsCount = GET_UINT32(p_FmPort->p_ParamsPage->ipfOptionsCounter); -+ -+ return E_OK; -+} -+#endif /* (DPAA_VERSION >= 11) */ -+ -+t_Error FM_PORT_ConfigDsarSupport(t_Handle h_FmPortRx, -+ t_FmPortDsarTablesSizes *params) -+{ -+ t_FmPort *p_FmPort = (t_FmPort *)h_FmPortRx; -+ p_FmPort->deepSleepVars.autoResMaxSizes = XX_Malloc( -+ sizeof(struct t_FmPortDsarTablesSizes)); -+ memcpy(p_FmPort->deepSleepVars.autoResMaxSizes, params, -+ sizeof(struct t_FmPortDsarTablesSizes)); -+ return E_OK; -+} -+ -+static t_Error FmPortConfigAutoResForDeepSleepSupport1(t_FmPort *p_FmPort) -+{ -+ uint32_t *param_page; -+ t_FmPortDsarTablesSizes *params = p_FmPort->deepSleepVars.autoResMaxSizes; -+ t_ArCommonDesc *ArCommonDescPtr; -+ uint32_t size = sizeof(t_ArCommonDesc); -+ // ARP -+ // should put here if (params->max_num_of_arp_entries)? -+ size = ROUND_UP(size,4); -+ size += sizeof(t_DsarArpDescriptor); -+ size += sizeof(t_DsarArpBindingEntry) * params->maxNumOfArpEntries; -+ size += sizeof(t_DsarArpStatistics); -+ //ICMPV4 -+ size = ROUND_UP(size,4); -+ size += sizeof(t_DsarIcmpV4Descriptor); -+ size += sizeof(t_DsarIcmpV4BindingEntry) * params->maxNumOfEchoIpv4Entries; -+ size += sizeof(t_DsarIcmpV4Statistics); -+ //ICMPV6 -+ size = ROUND_UP(size,4); -+ size += sizeof(t_DsarIcmpV6Descriptor); -+ size += sizeof(t_DsarIcmpV6BindingEntry) * params->maxNumOfEchoIpv6Entries; -+ size += sizeof(t_DsarIcmpV6Statistics); -+ //ND -+ size = ROUND_UP(size,4); -+ size += sizeof(t_DsarNdDescriptor); -+ size += sizeof(t_DsarIcmpV6BindingEntry) * params->maxNumOfNdpEntries; -+ size += sizeof(t_DsarIcmpV6Statistics); -+ //SNMP -+ size = ROUND_UP(size,4); -+ size += sizeof(t_DsarSnmpDescriptor); -+ size += sizeof(t_DsarSnmpIpv4AddrTblEntry) -+ * params->maxNumOfSnmpIPV4Entries; -+ size += sizeof(t_DsarSnmpIpv6AddrTblEntry) -+ * params->maxNumOfSnmpIPV6Entries; -+ size += sizeof(t_OidsTblEntry) * params->maxNumOfSnmpOidEntries; -+ size += params->maxNumOfSnmpOidChar; -+ size += sizeof(t_DsarIcmpV6Statistics); -+ //filters -+ size = ROUND_UP(size,4); -+ size += params->maxNumOfIpProtFiltering; -+ size = ROUND_UP(size,4); -+ size += params->maxNumOfUdpPortFiltering * sizeof(t_PortTblEntry); -+ size = ROUND_UP(size,4); -+ size += params->maxNumOfTcpPortFiltering * sizeof(t_PortTblEntry); -+ -+ // add here for more protocols -+ -+ // statistics -+ size = ROUND_UP(size,4); -+ size += sizeof(t_ArStatistics); -+ -+ ArCommonDescPtr = FM_MURAM_AllocMem(p_FmPort->h_FmMuram, size, 0x10); -+ -+ param_page = -+ XX_PhysToVirt( -+ p_FmPort->fmMuramPhysBaseAddr -+ + GET_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rgpr)); -+ WRITE_UINT32( -+ *param_page, -+ (uint32_t)(XX_VirtToPhys(ArCommonDescPtr) - p_FmPort->fmMuramPhysBaseAddr)); -+ return E_OK; -+} -+ -+t_FmPortDsarTablesSizes* FM_PORT_GetDsarTablesMaxSizes(t_Handle h_FmPortRx) -+{ -+ t_FmPort *p_FmPort = (t_FmPort *)h_FmPortRx; -+ return p_FmPort->deepSleepVars.autoResMaxSizes; -+} -+ -+struct arOffsets -+{ -+ uint32_t arp; -+ uint32_t nd; -+ uint32_t icmpv4; -+ uint32_t icmpv6; -+ uint32_t snmp; -+ uint32_t stats; -+ uint32_t filtIp; -+ uint32_t filtUdp; -+ uint32_t filtTcp; -+}; -+ -+static uint32_t AR_ComputeOffsets(struct arOffsets* of, -+ struct t_FmPortDsarParams *params, -+ t_FmPort *p_FmPort) -+{ -+ uint32_t size = sizeof(t_ArCommonDesc); -+ // ARP -+ if (params->p_AutoResArpInfo) -+ { -+ size = ROUND_UP(size,4); -+ of->arp = size; -+ size += sizeof(t_DsarArpDescriptor); -+ size += sizeof(t_DsarArpBindingEntry) -+ * params->p_AutoResArpInfo->tableSize; -+ size += sizeof(t_DsarArpStatistics); -+ } -+ // ICMPV4 -+ if (params->p_AutoResEchoIpv4Info) -+ { -+ size = ROUND_UP(size,4); -+ of->icmpv4 = size; -+ size += sizeof(t_DsarIcmpV4Descriptor); -+ size += sizeof(t_DsarIcmpV4BindingEntry) -+ * params->p_AutoResEchoIpv4Info->tableSize; -+ size += sizeof(t_DsarIcmpV4Statistics); -+ } -+ // ICMPV6 -+ if (params->p_AutoResEchoIpv6Info) -+ { -+ size = ROUND_UP(size,4); -+ of->icmpv6 = size; -+ size += sizeof(t_DsarIcmpV6Descriptor); -+ size += sizeof(t_DsarIcmpV6BindingEntry) -+ * params->p_AutoResEchoIpv6Info->tableSize; -+ size += sizeof(t_DsarIcmpV6Statistics); -+ } -+ // ND -+ if (params->p_AutoResNdpInfo) -+ { -+ size = ROUND_UP(size,4); -+ of->nd = size; -+ size += sizeof(t_DsarNdDescriptor); -+ size += sizeof(t_DsarIcmpV6BindingEntry) -+ * (params->p_AutoResNdpInfo->tableSizeAssigned -+ + params->p_AutoResNdpInfo->tableSizeTmp); -+ size += sizeof(t_DsarIcmpV6Statistics); -+ } -+ // SNMP -+ if (params->p_AutoResSnmpInfo) -+ { -+ size = ROUND_UP(size,4); -+ of->snmp = size; -+ size += sizeof(t_DsarSnmpDescriptor); -+ size += sizeof(t_DsarSnmpIpv4AddrTblEntry) -+ * params->p_AutoResSnmpInfo->numOfIpv4Addresses; -+ size += sizeof(t_DsarSnmpIpv6AddrTblEntry) -+ * params->p_AutoResSnmpInfo->numOfIpv6Addresses; -+ size += sizeof(t_OidsTblEntry) * params->p_AutoResSnmpInfo->oidsTblSize; -+ size += p_FmPort->deepSleepVars.autoResMaxSizes->maxNumOfSnmpOidChar; -+ size += sizeof(t_DsarIcmpV6Statistics); -+ } -+ //filters -+ size = ROUND_UP(size,4); -+ if (params->p_AutoResFilteringInfo) -+ { -+ of->filtIp = size; -+ size += params->p_AutoResFilteringInfo->ipProtTableSize; -+ size = ROUND_UP(size,4); -+ of->filtUdp = size; -+ size += params->p_AutoResFilteringInfo->udpPortsTableSize -+ * sizeof(t_PortTblEntry); -+ size = ROUND_UP(size,4); -+ of->filtTcp = size; -+ size += params->p_AutoResFilteringInfo->tcpPortsTableSize -+ * sizeof(t_PortTblEntry); -+ } -+ // add here for more protocols -+ // statistics -+ size = ROUND_UP(size,4); -+ of->stats = size; -+ size += sizeof(t_ArStatistics); -+ return size; -+} -+ -+uint32_t* ARDesc; -+void PrsEnable(t_Handle p_FmPcd); -+void PrsDisable(t_Handle p_FmPcd); -+int PrsIsEnabled(t_Handle p_FmPcd); -+t_Handle FM_PCD_GetHcPort(t_Handle h_FmPcd); -+ -+static t_Error DsarCheckParams(t_FmPortDsarParams *params, -+ t_FmPortDsarTablesSizes *sizes) -+{ -+ bool macInit = FALSE; -+ uint8_t mac[6]; -+ int i = 0; -+ -+ // check table sizes -+ if (params->p_AutoResArpInfo -+ && sizes->maxNumOfArpEntries < params->p_AutoResArpInfo->tableSize) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("DSAR: Arp table size exceeds the configured maximum size.")); -+ if (params->p_AutoResEchoIpv4Info -+ && sizes->maxNumOfEchoIpv4Entries -+ < params->p_AutoResEchoIpv4Info->tableSize) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("DSAR: EchoIpv4 table size exceeds the configured maximum size.")); -+ if (params->p_AutoResNdpInfo -+ && sizes->maxNumOfNdpEntries -+ < params->p_AutoResNdpInfo->tableSizeAssigned -+ + params->p_AutoResNdpInfo->tableSizeTmp) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("DSAR: NDP table size exceeds the configured maximum size.")); -+ if (params->p_AutoResEchoIpv6Info -+ && sizes->maxNumOfEchoIpv6Entries -+ < params->p_AutoResEchoIpv6Info->tableSize) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("DSAR: EchoIpv6 table size exceeds the configured maximum size.")); -+ if (params->p_AutoResSnmpInfo -+ && sizes->maxNumOfSnmpOidEntries -+ < params->p_AutoResSnmpInfo->oidsTblSize) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("DSAR: Snmp Oid table size exceeds the configured maximum size.")); -+ if (params->p_AutoResSnmpInfo -+ && sizes->maxNumOfSnmpIPV4Entries -+ < params->p_AutoResSnmpInfo->numOfIpv4Addresses) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("DSAR: Snmp ipv4 table size exceeds the configured maximum size.")); -+ if (params->p_AutoResSnmpInfo -+ && sizes->maxNumOfSnmpIPV6Entries -+ < params->p_AutoResSnmpInfo->numOfIpv6Addresses) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("DSAR: Snmp ipv6 table size exceeds the configured maximum size.")); -+ if (params->p_AutoResFilteringInfo) -+ { -+ if (sizes->maxNumOfIpProtFiltering -+ < params->p_AutoResFilteringInfo->ipProtTableSize) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("DSAR: ip filter table size exceeds the configured maximum size.")); -+ if (sizes->maxNumOfTcpPortFiltering -+ < params->p_AutoResFilteringInfo->udpPortsTableSize) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("DSAR: udp filter table size exceeds the configured maximum size.")); -+ if (sizes->maxNumOfUdpPortFiltering -+ < params->p_AutoResFilteringInfo->tcpPortsTableSize) -+ RETURN_ERROR( -+ MAJOR, -+ E_INVALID_VALUE, -+ ("DSAR: tcp filter table size exceeds the configured maximum size.")); -+ } -+ /* check only 1 MAC address is configured (this is what ucode currently supports) */ -+ if (params->p_AutoResArpInfo && params->p_AutoResArpInfo->tableSize) -+ { -+ memcpy(mac, params->p_AutoResArpInfo->p_AutoResTable[0].mac, 6); -+ i = 1; -+ macInit = TRUE; -+ -+ for (; i < params->p_AutoResArpInfo->tableSize; i++) -+ if (memcmp(mac, params->p_AutoResArpInfo->p_AutoResTable[i].mac, 6)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("DSAR: Only 1 mac address is currently supported.")); -+ } -+ if (params->p_AutoResEchoIpv4Info -+ && params->p_AutoResEchoIpv4Info->tableSize) -+ { -+ i = 0; -+ if (!macInit) -+ { -+ memcpy(mac, params->p_AutoResEchoIpv4Info->p_AutoResTable[0].mac, -+ 6); -+ i = 1; -+ macInit = TRUE; -+ } -+ for (; i < params->p_AutoResEchoIpv4Info->tableSize; i++) -+ if (memcmp(mac, -+ params->p_AutoResEchoIpv4Info->p_AutoResTable[i].mac, 6)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("DSAR: Only 1 mac address is currently supported.")); -+ } -+ if (params->p_AutoResEchoIpv6Info -+ && params->p_AutoResEchoIpv6Info->tableSize) -+ { -+ i = 0; -+ if (!macInit) -+ { -+ memcpy(mac, params->p_AutoResEchoIpv6Info->p_AutoResTable[0].mac, -+ 6); -+ i = 1; -+ macInit = TRUE; -+ } -+ for (; i < params->p_AutoResEchoIpv6Info->tableSize; i++) -+ if (memcmp(mac, -+ params->p_AutoResEchoIpv6Info->p_AutoResTable[i].mac, 6)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("DSAR: Only 1 mac address is currently supported.")); -+ } -+ if (params->p_AutoResNdpInfo && params->p_AutoResNdpInfo->tableSizeAssigned) -+ { -+ i = 0; -+ if (!macInit) -+ { -+ memcpy(mac, params->p_AutoResNdpInfo->p_AutoResTableAssigned[0].mac, -+ 6); -+ i = 1; -+ macInit = TRUE; -+ } -+ for (; i < params->p_AutoResNdpInfo->tableSizeAssigned; i++) -+ if (memcmp(mac, -+ params->p_AutoResNdpInfo->p_AutoResTableAssigned[i].mac, -+ 6)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("DSAR: Only 1 mac address is currently supported.")); -+ } -+ if (params->p_AutoResNdpInfo && params->p_AutoResNdpInfo->tableSizeTmp) -+ { -+ i = 0; -+ if (!macInit) -+ { -+ memcpy(mac, params->p_AutoResNdpInfo->p_AutoResTableTmp[0].mac, 6); -+ i = 1; -+ } -+ for (; i < params->p_AutoResNdpInfo->tableSizeTmp; i++) -+ if (memcmp(mac, params->p_AutoResNdpInfo->p_AutoResTableTmp[i].mac, -+ 6)) -+ RETURN_ERROR( -+ MAJOR, E_INVALID_VALUE, -+ ("DSAR: Only 1 mac address is currently supported.")); -+ } -+ return E_OK; -+} -+ -+static int GetBERLen(uint8_t* buf) -+{ -+ if (*buf & 0x80) -+ { -+ if ((*buf & 0x7F) == 1) -+ return buf[1]; -+ else -+ return *(uint16_t*)&buf[1]; // assuming max len is 2 -+ } -+ else -+ return buf[0]; -+} -+#define TOTAL_BER_LEN(len) (len < 128) ? len + 2 : len + 3 -+ -+#define SCFG_FMCLKDPSLPCR_ADDR 0xFFE0FC00C -+#define SCFG_FMCLKDPSLPCR_DS_VAL 0x08402000 -+#define SCFG_FMCLKDPSLPCR_NORMAL_VAL 0x00402000 -+static int fm_soc_suspend(void) -+{ -+ uint32_t *fmclk, tmp32; -+ fmclk = ioremap(SCFG_FMCLKDPSLPCR_ADDR, 4); -+ tmp32 = GET_UINT32(*fmclk); -+ WRITE_UINT32(*fmclk, SCFG_FMCLKDPSLPCR_DS_VAL); -+ tmp32 = GET_UINT32(*fmclk); -+ iounmap(fmclk); -+ return 0; -+} -+ -+void fm_clk_down(void) -+{ -+ uint32_t *fmclk, tmp32; -+ fmclk = ioremap(SCFG_FMCLKDPSLPCR_ADDR, 4); -+ tmp32 = GET_UINT32(*fmclk); -+ WRITE_UINT32(*fmclk, SCFG_FMCLKDPSLPCR_DS_VAL | 0x40000000); -+ tmp32 = GET_UINT32(*fmclk); -+ iounmap(fmclk); -+} -+ -+t_Error FM_PORT_EnterDsar(t_Handle h_FmPortRx, t_FmPortDsarParams *params) -+{ -+ int i, j; -+ t_Error err; -+ uint32_t nia; -+ t_FmPort *p_FmPort = (t_FmPort *)h_FmPortRx; -+ t_FmPort *p_FmPortTx = (t_FmPort *)params->h_FmPortTx; -+ t_DsarArpDescriptor *ArpDescriptor; -+ t_DsarIcmpV4Descriptor* ICMPV4Descriptor; -+ t_DsarIcmpV6Descriptor* ICMPV6Descriptor; -+ t_DsarNdDescriptor* NDDescriptor; -+ -+ uint64_t fmMuramVirtBaseAddr = (uint64_t)PTR_TO_UINT(XX_PhysToVirt(p_FmPort->fmMuramPhysBaseAddr)); -+ uint32_t *param_page = XX_PhysToVirt(p_FmPort->fmMuramPhysBaseAddr + GET_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rgpr)); -+ t_ArCommonDesc *ArCommonDescPtr = (t_ArCommonDesc*)(XX_PhysToVirt(p_FmPort->fmMuramPhysBaseAddr + GET_UINT32(*param_page))); -+ struct arOffsets* of; -+ uint8_t tmp = 0; -+ t_FmGetSetParams fmGetSetParams; -+ memset(&fmGetSetParams, 0, sizeof (t_FmGetSetParams)); -+ fmGetSetParams.setParams.type = UPDATE_FPM_BRKC_SLP; -+ fmGetSetParams.setParams.sleep = 1; -+ -+ err = DsarCheckParams(params, p_FmPort->deepSleepVars.autoResMaxSizes); -+ if (err != E_OK) -+ return err; -+ -+ p_FmPort->deepSleepVars.autoResOffsets = XX_Malloc(sizeof(struct arOffsets)); -+ of = (struct arOffsets *)p_FmPort->deepSleepVars.autoResOffsets; -+ IOMemSet32(ArCommonDescPtr, 0, AR_ComputeOffsets(of, params, p_FmPort)); -+ -+ // common -+ WRITE_UINT8(ArCommonDescPtr->arTxPort, p_FmPortTx->hardwarePortId); -+ nia = GET_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfne); // bmi nia -+ if ((nia & 0x007C0000) == 0x00440000) // bmi nia is parser -+ WRITE_UINT32(ArCommonDescPtr->activeHPNIA, GET_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfpne)); -+ else -+ WRITE_UINT32(ArCommonDescPtr->activeHPNIA, nia); -+ WRITE_UINT16(ArCommonDescPtr->snmpPort, 161); -+ -+ // ARP -+ if (params->p_AutoResArpInfo) -+ { -+ t_DsarArpBindingEntry* arp_bindings; -+ ArpDescriptor = (t_DsarArpDescriptor*)(PTR_TO_UINT(ArCommonDescPtr) + of->arp); -+ WRITE_UINT32(ArCommonDescPtr->p_ArpDescriptor, PTR_TO_UINT(ArpDescriptor) - fmMuramVirtBaseAddr); -+ arp_bindings = (t_DsarArpBindingEntry*)(PTR_TO_UINT(ArpDescriptor) + sizeof(t_DsarArpDescriptor)); -+ if (params->p_AutoResArpInfo->enableConflictDetection) -+ WRITE_UINT16(ArpDescriptor->control, 1); -+ else -+ WRITE_UINT16(ArpDescriptor->control, 0); -+ if (params->p_AutoResArpInfo->tableSize) -+ { -+ t_FmPortDsarArpEntry* arp_entry = params->p_AutoResArpInfo->p_AutoResTable; -+ WRITE_UINT16(*(uint16_t*)&ArCommonDescPtr->macStationAddr[0], *(uint16_t*)&arp_entry[0].mac[0]); -+ WRITE_UINT32(*(uint32_t*)&ArCommonDescPtr->macStationAddr[2], *(uint32_t*)&arp_entry[0].mac[2]); -+ WRITE_UINT16(ArpDescriptor->numOfBindings, params->p_AutoResArpInfo->tableSize); -+ -+ for (i = 0; i < params->p_AutoResArpInfo->tableSize; i++) -+ { -+ WRITE_UINT32(arp_bindings[i].ipv4Addr, arp_entry[i].ipAddress); -+ if (arp_entry[i].isVlan) -+ WRITE_UINT16(arp_bindings[i].vlanId, arp_entry[i].vid & 0xFFF); -+ } -+ WRITE_UINT32(ArpDescriptor->p_Bindings, PTR_TO_UINT(arp_bindings) - fmMuramVirtBaseAddr); -+ } -+ WRITE_UINT32(ArpDescriptor->p_Statistics, PTR_TO_UINT(arp_bindings) + -+ sizeof(t_DsarArpBindingEntry) * params->p_AutoResArpInfo->tableSize - fmMuramVirtBaseAddr); -+ } -+ -+ // ICMPV4 -+ if (params->p_AutoResEchoIpv4Info) -+ { -+ t_DsarIcmpV4BindingEntry* icmpv4_bindings; -+ ICMPV4Descriptor = (t_DsarIcmpV4Descriptor*)(PTR_TO_UINT(ArCommonDescPtr) + of->icmpv4); -+ WRITE_UINT32(ArCommonDescPtr->p_IcmpV4Descriptor, PTR_TO_UINT(ICMPV4Descriptor) - fmMuramVirtBaseAddr); -+ icmpv4_bindings = (t_DsarIcmpV4BindingEntry*)(PTR_TO_UINT(ICMPV4Descriptor) + sizeof(t_DsarIcmpV4Descriptor)); -+ WRITE_UINT16(ICMPV4Descriptor->control, 0); -+ if (params->p_AutoResEchoIpv4Info->tableSize) -+ { -+ t_FmPortDsarArpEntry* arp_entry = params->p_AutoResEchoIpv4Info->p_AutoResTable; -+ WRITE_UINT16(*(uint16_t*)&ArCommonDescPtr->macStationAddr[0], *(uint16_t*)&arp_entry[0].mac[0]); -+ WRITE_UINT32(*(uint32_t*)&ArCommonDescPtr->macStationAddr[2], *(uint32_t*)&arp_entry[0].mac[2]); -+ WRITE_UINT16(ICMPV4Descriptor->numOfBindings, params->p_AutoResEchoIpv4Info->tableSize); -+ -+ for (i = 0; i < params->p_AutoResEchoIpv4Info->tableSize; i++) -+ { -+ WRITE_UINT32(icmpv4_bindings[i].ipv4Addr, arp_entry[i].ipAddress); -+ if (arp_entry[i].isVlan) -+ WRITE_UINT16(icmpv4_bindings[i].vlanId, arp_entry[i].vid & 0xFFF); -+ } -+ WRITE_UINT32(ICMPV4Descriptor->p_Bindings, PTR_TO_UINT(icmpv4_bindings) - fmMuramVirtBaseAddr); -+ } -+ WRITE_UINT32(ICMPV4Descriptor->p_Statistics, PTR_TO_UINT(icmpv4_bindings) + -+ sizeof(t_DsarIcmpV4BindingEntry) * params->p_AutoResEchoIpv4Info->tableSize - fmMuramVirtBaseAddr); -+ } -+ -+ // ICMPV6 -+ if (params->p_AutoResEchoIpv6Info) -+ { -+ t_DsarIcmpV6BindingEntry* icmpv6_bindings; -+ ICMPV6Descriptor = (t_DsarIcmpV6Descriptor*)(PTR_TO_UINT(ArCommonDescPtr) + of->icmpv6); -+ WRITE_UINT32(ArCommonDescPtr->p_IcmpV6Descriptor, PTR_TO_UINT(ICMPV6Descriptor) - fmMuramVirtBaseAddr); -+ icmpv6_bindings = (t_DsarIcmpV6BindingEntry*)(PTR_TO_UINT(ICMPV6Descriptor) + sizeof(t_DsarIcmpV6Descriptor)); -+ WRITE_UINT16(ICMPV6Descriptor->control, 0); -+ if (params->p_AutoResEchoIpv6Info->tableSize) -+ { -+ t_FmPortDsarNdpEntry* ndp_entry = params->p_AutoResEchoIpv6Info->p_AutoResTable; -+ WRITE_UINT16(*(uint16_t*)&ArCommonDescPtr->macStationAddr[0], *(uint16_t*)&ndp_entry[0].mac[0]); -+ WRITE_UINT32(*(uint32_t*)&ArCommonDescPtr->macStationAddr[2], *(uint32_t*)&ndp_entry[0].mac[2]); -+ WRITE_UINT16(ICMPV6Descriptor->numOfBindings, params->p_AutoResEchoIpv6Info->tableSize); -+ -+ for (i = 0; i < params->p_AutoResEchoIpv6Info->tableSize; i++) -+ { -+ for (j = 0; j < 4; j++) -+ WRITE_UINT32(icmpv6_bindings[i].ipv6Addr[j], ndp_entry[i].ipAddress[j]); -+ if (ndp_entry[i].isVlan) -+ WRITE_UINT16(*(uint16_t*)&icmpv6_bindings[i].ipv6Addr[4], ndp_entry[i].vid & 0xFFF); // writing vlan -+ } -+ WRITE_UINT32(ICMPV6Descriptor->p_Bindings, PTR_TO_UINT(icmpv6_bindings) - fmMuramVirtBaseAddr); -+ } -+ WRITE_UINT32(ICMPV6Descriptor->p_Statistics, PTR_TO_UINT(icmpv6_bindings) + -+ sizeof(t_DsarIcmpV6BindingEntry) * params->p_AutoResEchoIpv6Info->tableSize - fmMuramVirtBaseAddr); -+ } -+ -+ // ND -+ if (params->p_AutoResNdpInfo) -+ { -+ t_DsarIcmpV6BindingEntry* icmpv6_bindings; -+ NDDescriptor = (t_DsarNdDescriptor*)(PTR_TO_UINT(ArCommonDescPtr) + of->nd); -+ WRITE_UINT32(ArCommonDescPtr->p_NdDescriptor, PTR_TO_UINT(NDDescriptor) - fmMuramVirtBaseAddr); -+ icmpv6_bindings = (t_DsarIcmpV6BindingEntry*)(PTR_TO_UINT(NDDescriptor) + sizeof(t_DsarNdDescriptor)); -+ if (params->p_AutoResNdpInfo->enableConflictDetection) -+ WRITE_UINT16(NDDescriptor->control, 1); -+ else -+ WRITE_UINT16(NDDescriptor->control, 0); -+ if (params->p_AutoResNdpInfo->tableSizeAssigned + params->p_AutoResNdpInfo->tableSizeTmp) -+ { -+ t_FmPortDsarNdpEntry* ndp_entry = params->p_AutoResNdpInfo->p_AutoResTableAssigned; -+ WRITE_UINT16(*(uint16_t*)&ArCommonDescPtr->macStationAddr[0], *(uint16_t*)&ndp_entry[0].mac[0]); -+ WRITE_UINT32(*(uint32_t*)&ArCommonDescPtr->macStationAddr[2], *(uint32_t*)&ndp_entry[0].mac[2]); -+ WRITE_UINT16(NDDescriptor->numOfBindings, params->p_AutoResNdpInfo->tableSizeAssigned -+ + params->p_AutoResNdpInfo->tableSizeTmp); -+ -+ for (i = 0; i < params->p_AutoResNdpInfo->tableSizeAssigned; i++) -+ { -+ for (j = 0; j < 4; j++) -+ WRITE_UINT32(icmpv6_bindings[i].ipv6Addr[j], ndp_entry[i].ipAddress[j]); -+ if (ndp_entry[i].isVlan) -+ WRITE_UINT16(*(uint16_t*)&icmpv6_bindings[i].ipv6Addr[4], ndp_entry[i].vid & 0xFFF); // writing vlan -+ } -+ ndp_entry = params->p_AutoResNdpInfo->p_AutoResTableTmp; -+ for (i = 0; i < params->p_AutoResNdpInfo->tableSizeTmp; i++) -+ { -+ for (j = 0; j < 4; j++) -+ WRITE_UINT32(icmpv6_bindings[i + params->p_AutoResNdpInfo->tableSizeAssigned].ipv6Addr[j], ndp_entry[i].ipAddress[j]); -+ if (ndp_entry[i].isVlan) -+ WRITE_UINT16(*(uint16_t*)&icmpv6_bindings[i + params->p_AutoResNdpInfo->tableSizeAssigned].ipv6Addr[4], ndp_entry[i].vid & 0xFFF); // writing vlan -+ } -+ WRITE_UINT32(NDDescriptor->p_Bindings, PTR_TO_UINT(icmpv6_bindings) - fmMuramVirtBaseAddr); -+ } -+ WRITE_UINT32(NDDescriptor->p_Statistics, PTR_TO_UINT(icmpv6_bindings) + sizeof(t_DsarIcmpV6BindingEntry) -+ * (params->p_AutoResNdpInfo->tableSizeAssigned + params->p_AutoResNdpInfo->tableSizeTmp) -+ - fmMuramVirtBaseAddr); -+ WRITE_UINT32(NDDescriptor->solicitedAddr, 0xFFFFFFFF); -+ } -+ -+ // SNMP -+ if (params->p_AutoResSnmpInfo) -+ { -+ t_FmPortDsarSnmpInfo *snmpSrc = params->p_AutoResSnmpInfo; -+ t_DsarSnmpIpv4AddrTblEntry* snmpIpv4Addr; -+ t_DsarSnmpIpv6AddrTblEntry* snmpIpv6Addr; -+ t_OidsTblEntry* snmpOid; -+ uint8_t *charPointer; -+ int len; -+ t_DsarSnmpDescriptor* SnmpDescriptor = (t_DsarSnmpDescriptor*)(PTR_TO_UINT(ArCommonDescPtr) + of->snmp); -+ WRITE_UINT32(ArCommonDescPtr->p_SnmpDescriptor, PTR_TO_UINT(SnmpDescriptor) - fmMuramVirtBaseAddr); -+ WRITE_UINT16(SnmpDescriptor->control, snmpSrc->control); -+ WRITE_UINT16(SnmpDescriptor->maxSnmpMsgLength, snmpSrc->maxSnmpMsgLength); -+ snmpIpv4Addr = (t_DsarSnmpIpv4AddrTblEntry*)(PTR_TO_UINT(SnmpDescriptor) + sizeof(t_DsarSnmpDescriptor)); -+ if (snmpSrc->numOfIpv4Addresses) -+ { -+ t_FmPortDsarSnmpIpv4AddrTblEntry* snmpIpv4AddrSrc = snmpSrc->p_Ipv4AddrTbl; -+ WRITE_UINT16(SnmpDescriptor->numOfIpv4Addresses, snmpSrc->numOfIpv4Addresses); -+ for (i = 0; i < snmpSrc->numOfIpv4Addresses; i++) -+ { -+ WRITE_UINT32(snmpIpv4Addr[i].ipv4Addr, snmpIpv4AddrSrc[i].ipv4Addr); -+ if (snmpIpv4AddrSrc[i].isVlan) -+ WRITE_UINT16(snmpIpv4Addr[i].vlanId, snmpIpv4AddrSrc[i].vid & 0xFFF); -+ } -+ WRITE_UINT32(SnmpDescriptor->p_Ipv4AddrTbl, PTR_TO_UINT(snmpIpv4Addr) - fmMuramVirtBaseAddr); -+ } -+ snmpIpv6Addr = (t_DsarSnmpIpv6AddrTblEntry*)(PTR_TO_UINT(snmpIpv4Addr) -+ + sizeof(t_DsarSnmpIpv4AddrTblEntry) * snmpSrc->numOfIpv4Addresses); -+ if (snmpSrc->numOfIpv6Addresses) -+ { -+ t_FmPortDsarSnmpIpv6AddrTblEntry* snmpIpv6AddrSrc = snmpSrc->p_Ipv6AddrTbl; -+ WRITE_UINT16(SnmpDescriptor->numOfIpv6Addresses, snmpSrc->numOfIpv6Addresses); -+ for (i = 0; i < snmpSrc->numOfIpv6Addresses; i++) -+ { -+ for (j = 0; j < 4; j++) -+ WRITE_UINT32(snmpIpv6Addr[i].ipv6Addr[j], snmpIpv6AddrSrc[i].ipv6Addr[j]); -+ if (snmpIpv6AddrSrc[i].isVlan) -+ WRITE_UINT16(snmpIpv6Addr[i].vlanId, snmpIpv6AddrSrc[i].vid & 0xFFF); -+ } -+ WRITE_UINT32(SnmpDescriptor->p_Ipv6AddrTbl, PTR_TO_UINT(snmpIpv6Addr) - fmMuramVirtBaseAddr); -+ } -+ snmpOid = (t_OidsTblEntry*)(PTR_TO_UINT(snmpIpv6Addr) -+ + sizeof(t_DsarSnmpIpv6AddrTblEntry) * snmpSrc->numOfIpv6Addresses); -+ charPointer = (uint8_t*)(PTR_TO_UINT(snmpOid) -+ + sizeof(t_OidsTblEntry) * snmpSrc->oidsTblSize); -+ len = TOTAL_BER_LEN(GetBERLen(&snmpSrc->p_RdOnlyCommunityStr[1])); -+ Mem2IOCpy32(charPointer, snmpSrc->p_RdOnlyCommunityStr, len); -+ WRITE_UINT32(SnmpDescriptor->p_RdOnlyCommunityStr, PTR_TO_UINT(charPointer) - fmMuramVirtBaseAddr); -+ charPointer += len; -+ len = TOTAL_BER_LEN(GetBERLen(&snmpSrc->p_RdWrCommunityStr[1])); -+ Mem2IOCpy32(charPointer, snmpSrc->p_RdWrCommunityStr, len); -+ WRITE_UINT32(SnmpDescriptor->p_RdWrCommunityStr, PTR_TO_UINT(charPointer) - fmMuramVirtBaseAddr); -+ charPointer += len; -+ WRITE_UINT32(SnmpDescriptor->oidsTblSize, snmpSrc->oidsTblSize); -+ WRITE_UINT32(SnmpDescriptor->p_OidsTbl, PTR_TO_UINT(snmpOid) - fmMuramVirtBaseAddr); -+ for (i = 0; i < snmpSrc->oidsTblSize; i++) -+ { -+ WRITE_UINT16(snmpOid->oidSize, snmpSrc->p_OidsTbl[i].oidSize); -+ WRITE_UINT16(snmpOid->resSize, snmpSrc->p_OidsTbl[i].resSize); -+ Mem2IOCpy32(charPointer, snmpSrc->p_OidsTbl[i].oidVal, snmpSrc->p_OidsTbl[i].oidSize); -+ WRITE_UINT32(snmpOid->p_Oid, PTR_TO_UINT(charPointer) - fmMuramVirtBaseAddr); -+ charPointer += snmpSrc->p_OidsTbl[i].oidSize; -+ if (snmpSrc->p_OidsTbl[i].resSize <= 4) -+ WRITE_UINT32(snmpOid->resValOrPtr, *snmpSrc->p_OidsTbl[i].resVal); -+ else -+ { -+ Mem2IOCpy32(charPointer, snmpSrc->p_OidsTbl[i].resVal, snmpSrc->p_OidsTbl[i].resSize); -+ WRITE_UINT32(snmpOid->resValOrPtr, PTR_TO_UINT(charPointer) - fmMuramVirtBaseAddr); -+ charPointer += snmpSrc->p_OidsTbl[i].resSize; -+ } -+ snmpOid++; -+ } -+ charPointer = UINT_TO_PTR(ROUND_UP(PTR_TO_UINT(charPointer),4)); -+ WRITE_UINT32(SnmpDescriptor->p_Statistics, PTR_TO_UINT(charPointer) - fmMuramVirtBaseAddr); -+ } -+ -+ // filtering -+ if (params->p_AutoResFilteringInfo) -+ { -+ if (params->p_AutoResFilteringInfo->ipProtPassOnHit) -+ tmp |= IP_PROT_TBL_PASS_MASK; -+ if (params->p_AutoResFilteringInfo->udpPortPassOnHit) -+ tmp |= UDP_PORT_TBL_PASS_MASK; -+ if (params->p_AutoResFilteringInfo->tcpPortPassOnHit) -+ tmp |= TCP_PORT_TBL_PASS_MASK; -+ WRITE_UINT8(ArCommonDescPtr->filterControl, tmp); -+ WRITE_UINT16(ArCommonDescPtr->tcpControlPass, params->p_AutoResFilteringInfo->tcpFlagsMask); -+ -+ // ip filtering -+ if (params->p_AutoResFilteringInfo->ipProtTableSize) -+ { -+ uint8_t* ip_tbl = (uint8_t*)(PTR_TO_UINT(ArCommonDescPtr) + of->filtIp); -+ WRITE_UINT8(ArCommonDescPtr->ipProtocolTblSize, params->p_AutoResFilteringInfo->ipProtTableSize); -+ for (i = 0; i < params->p_AutoResFilteringInfo->ipProtTableSize; i++) -+ WRITE_UINT8(ip_tbl[i], params->p_AutoResFilteringInfo->p_IpProtTablePtr[i]); -+ WRITE_UINT32(ArCommonDescPtr->p_IpProtocolFiltTbl, PTR_TO_UINT(ip_tbl) - fmMuramVirtBaseAddr); -+ } -+ -+ // udp filtering -+ if (params->p_AutoResFilteringInfo->udpPortsTableSize) -+ { -+ t_PortTblEntry* udp_tbl = (t_PortTblEntry*)(PTR_TO_UINT(ArCommonDescPtr) + of->filtUdp); -+ WRITE_UINT8(ArCommonDescPtr->udpPortTblSize, params->p_AutoResFilteringInfo->udpPortsTableSize); -+ for (i = 0; i < params->p_AutoResFilteringInfo->udpPortsTableSize; i++) -+ { -+ WRITE_UINT32(udp_tbl[i].Ports, -+ (params->p_AutoResFilteringInfo->p_UdpPortsTablePtr[i].srcPort << 16) + -+ params->p_AutoResFilteringInfo->p_UdpPortsTablePtr[i].dstPort); -+ WRITE_UINT32(udp_tbl[i].PortsMask, -+ (params->p_AutoResFilteringInfo->p_UdpPortsTablePtr[i].srcPortMask << 16) + -+ params->p_AutoResFilteringInfo->p_UdpPortsTablePtr[i].dstPortMask); -+ } -+ WRITE_UINT32(ArCommonDescPtr->p_UdpPortFiltTbl, PTR_TO_UINT(udp_tbl) - fmMuramVirtBaseAddr); -+ } -+ -+ // tcp filtering -+ if (params->p_AutoResFilteringInfo->tcpPortsTableSize) -+ { -+ t_PortTblEntry* tcp_tbl = (t_PortTblEntry*)(PTR_TO_UINT(ArCommonDescPtr) + of->filtTcp); -+ WRITE_UINT8(ArCommonDescPtr->tcpPortTblSize, params->p_AutoResFilteringInfo->tcpPortsTableSize); -+ for (i = 0; i < params->p_AutoResFilteringInfo->tcpPortsTableSize; i++) -+ { -+ WRITE_UINT32(tcp_tbl[i].Ports, -+ (params->p_AutoResFilteringInfo->p_TcpPortsTablePtr[i].srcPort << 16) + -+ params->p_AutoResFilteringInfo->p_TcpPortsTablePtr[i].dstPort); -+ WRITE_UINT32(tcp_tbl[i].PortsMask, -+ (params->p_AutoResFilteringInfo->p_TcpPortsTablePtr[i].srcPortMask << 16) + -+ params->p_AutoResFilteringInfo->p_TcpPortsTablePtr[i].dstPortMask); -+ } -+ WRITE_UINT32(ArCommonDescPtr->p_TcpPortFiltTbl, PTR_TO_UINT(tcp_tbl) - fmMuramVirtBaseAddr); -+ } -+ } -+ // common stats -+ WRITE_UINT32(ArCommonDescPtr->p_ArStats, PTR_TO_UINT(ArCommonDescPtr) + of->stats - fmMuramVirtBaseAddr); -+ -+ // get into Deep Sleep sequence: -+ -+ // Ensures that FMan do not enter the idle state. This is done by programing -+ // FMDPSLPCR[FM_STOP] to one. -+ fm_soc_suspend(); -+ -+ ARDesc = UINT_TO_PTR(XX_VirtToPhys(ArCommonDescPtr)); -+ return E_OK; -+ -+} -+ -+void FM_ChangeClock(t_Handle h_Fm, int hardwarePortId); -+t_Error FM_PORT_EnterDsarFinal(t_Handle h_DsarRxPort, t_Handle h_DsarTxPort) -+{ -+ t_FmGetSetParams fmGetSetParams; -+ t_FmPort *p_FmPort = (t_FmPort *)h_DsarRxPort; -+ t_FmPort *p_FmPortTx = (t_FmPort *)h_DsarTxPort; -+ t_Handle *h_FmPcd = FmGetPcd(p_FmPort->h_Fm); -+ t_FmPort *p_FmPortHc = FM_PCD_GetHcPort(h_FmPcd); -+ memset(&fmGetSetParams, 0, sizeof (t_FmGetSetParams)); -+ fmGetSetParams.setParams.type = UPDATE_FM_CLD; -+ FmGetSetParams(p_FmPort->h_Fm, &fmGetSetParams); -+ -+ /* Issue graceful stop to HC port */ -+ FM_PORT_Disable(p_FmPortHc); -+ -+ // config tx port -+ p_FmPort->deepSleepVars.fmbm_tcfg = GET_UINT32(p_FmPortTx->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tcfg); -+ WRITE_UINT32(p_FmPortTx->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tcfg, GET_UINT32(p_FmPortTx->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tcfg) | BMI_PORT_CFG_IM | BMI_PORT_CFG_EN); -+ // ???? -+ p_FmPort->deepSleepVars.fmbm_tcmne = GET_UINT32(p_FmPortTx->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tcmne); -+ WRITE_UINT32(p_FmPortTx->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tcmne, 0xE); -+ // Stage 7:echo -+ p_FmPort->deepSleepVars.fmbm_rfpne = GET_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfpne); -+ WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfpne, 0x2E); -+ if (!PrsIsEnabled(h_FmPcd)) -+ { -+ p_FmPort->deepSleepVars.dsarEnabledParser = TRUE; -+ PrsEnable(h_FmPcd); -+ } -+ else -+ p_FmPort->deepSleepVars.dsarEnabledParser = FALSE; -+ -+ p_FmPort->deepSleepVars.fmbm_rfne = GET_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfne); -+ WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfne, 0x440000); -+ -+ // save rcfg for restoring: accumulate mode is changed by ucode -+ p_FmPort->deepSleepVars.fmbm_rcfg = GET_UINT32(p_FmPort->port.bmi_regs->rx.fmbm_rcfg); -+ WRITE_UINT32(p_FmPort->port.bmi_regs->rx.fmbm_rcfg, p_FmPort->deepSleepVars.fmbm_rcfg | BMI_PORT_CFG_AM); -+ memset(&fmGetSetParams, 0, sizeof (t_FmGetSetParams)); -+ fmGetSetParams.setParams.type = UPDATE_FPM_BRKC_SLP; -+ fmGetSetParams.setParams.sleep = 1; -+ FmGetSetParams(p_FmPort->h_Fm, &fmGetSetParams); -+ -+// ***** issue external request sync command -+ memset(&fmGetSetParams, 0, sizeof (t_FmGetSetParams)); -+ fmGetSetParams.setParams.type = UPDATE_FPM_EXTC; -+ FmGetSetParams(p_FmPort->h_Fm, &fmGetSetParams); -+ // get -+ memset(&fmGetSetParams, 0, sizeof (t_FmGetSetParams)); -+ fmGetSetParams.getParams.type = GET_FMFP_EXTC; -+ FmGetSetParams(p_FmPort->h_Fm, &fmGetSetParams); -+ if (fmGetSetParams.getParams.fmfp_extc != 0) -+ { -+ // clear -+ memset(&fmGetSetParams, 0, sizeof (t_FmGetSetParams)); -+ fmGetSetParams.setParams.type = UPDATE_FPM_EXTC_CLEAR; -+ FmGetSetParams(p_FmPort->h_Fm, &fmGetSetParams); -+} -+ -+ memset(&fmGetSetParams, 0, sizeof (t_FmGetSetParams)); -+ fmGetSetParams.getParams.type = GET_FMFP_EXTC | GET_FM_NPI; -+ do -+ { -+ FmGetSetParams(p_FmPort->h_Fm, &fmGetSetParams); -+ } while (fmGetSetParams.getParams.fmfp_extc != 0 && fmGetSetParams.getParams.fm_npi == 0); -+ if (fmGetSetParams.getParams.fm_npi != 0) -+ XX_Print("FM: Sync did not finish\n"); -+ -+ // check that all stoped -+ memset(&fmGetSetParams, 0, sizeof (t_FmGetSetParams)); -+ fmGetSetParams.getParams.type = GET_FMQM_GS | GET_FM_NPI; -+ FmGetSetParams(p_FmPort->h_Fm, &fmGetSetParams); -+ while (fmGetSetParams.getParams.fmqm_gs & 0xF0000000) -+ FmGetSetParams(p_FmPort->h_Fm, &fmGetSetParams); -+ if (fmGetSetParams.getParams.fmqm_gs == 0 && fmGetSetParams.getParams.fm_npi == 0) -+ XX_Print("FM: Sleeping\n"); -+// FM_ChangeClock(p_FmPort->h_Fm, p_FmPort->hardwarePortId); -+ -+ return E_OK; -+} -+ -+EXPORT_SYMBOL(FM_PORT_EnterDsarFinal); -+ -+void FM_PORT_Dsar_DumpRegs() -+{ -+ uint32_t* hh = XX_PhysToVirt(PTR_TO_UINT(ARDesc)); -+ DUMP_MEMORY(hh, 0x220); -+} -+ -+void FM_PORT_ExitDsar(t_Handle h_FmPortRx, t_Handle h_FmPortTx) -+{ -+ t_FmPort *p_FmPort = (t_FmPort *)h_FmPortRx; -+ t_FmPort *p_FmPortTx = (t_FmPort *)h_FmPortTx; -+ t_Handle *h_FmPcd = FmGetPcd(p_FmPort->h_Fm); -+ t_FmPort *p_FmPortHc = FM_PCD_GetHcPort(h_FmPcd); -+ t_FmGetSetParams fmGetSetParams; -+ memset(&fmGetSetParams, 0, sizeof (t_FmGetSetParams)); -+ fmGetSetParams.setParams.type = UPDATE_FPM_BRKC_SLP; -+ fmGetSetParams.setParams.sleep = 0; -+ if (p_FmPort->deepSleepVars.autoResOffsets) -+ { -+ XX_Free(p_FmPort->deepSleepVars.autoResOffsets); -+ p_FmPort->deepSleepVars.autoResOffsets = 0; -+ } -+ -+ if (p_FmPort->deepSleepVars.dsarEnabledParser) -+ PrsDisable(FmGetPcd(p_FmPort->h_Fm)); -+ WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfpne, p_FmPort->deepSleepVars.fmbm_rfpne); -+ WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfne, p_FmPort->deepSleepVars.fmbm_rfne); -+ WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rcfg, p_FmPort->deepSleepVars.fmbm_rcfg); -+ FmGetSetParams(p_FmPort->h_Fm, &fmGetSetParams); -+ WRITE_UINT32(p_FmPortTx->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tcmne, p_FmPort->deepSleepVars.fmbm_tcmne); -+ WRITE_UINT32(p_FmPortTx->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tcfg, p_FmPort->deepSleepVars.fmbm_tcfg); -+ FM_PORT_Enable(p_FmPortHc); -+} -+ -+bool FM_PORT_IsInDsar(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort *)h_FmPort; -+ return PTR_TO_UINT(p_FmPort->deepSleepVars.autoResOffsets); -+} -+ -+t_Error FM_PORT_GetDsarStats(t_Handle h_FmPortRx, t_FmPortDsarStats *stats) -+{ -+ t_FmPort *p_FmPort = (t_FmPort *)h_FmPortRx; -+ struct arOffsets *of = (struct arOffsets*)p_FmPort->deepSleepVars.autoResOffsets; -+ uint8_t* fmMuramVirtBaseAddr = XX_PhysToVirt(p_FmPort->fmMuramPhysBaseAddr); -+ uint32_t *param_page = XX_PhysToVirt(p_FmPort->fmMuramPhysBaseAddr + GET_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rgpr)); -+ t_ArCommonDesc *ArCommonDescPtr = (t_ArCommonDesc*)(XX_PhysToVirt(p_FmPort->fmMuramPhysBaseAddr + GET_UINT32(*param_page))); -+ t_DsarArpDescriptor *ArpDescriptor = (t_DsarArpDescriptor*)(PTR_TO_UINT(ArCommonDescPtr) + of->arp); -+ t_DsarArpStatistics* arp_stats = (t_DsarArpStatistics*)(PTR_TO_UINT(ArpDescriptor->p_Statistics) + fmMuramVirtBaseAddr); -+ t_DsarIcmpV4Descriptor* ICMPV4Descriptor = (t_DsarIcmpV4Descriptor*)(PTR_TO_UINT(ArCommonDescPtr) + of->icmpv4); -+ t_DsarIcmpV4Statistics* icmpv4_stats = (t_DsarIcmpV4Statistics*)(PTR_TO_UINT(ICMPV4Descriptor->p_Statistics) + fmMuramVirtBaseAddr); -+ t_DsarNdDescriptor* NDDescriptor = (t_DsarNdDescriptor*)(PTR_TO_UINT(ArCommonDescPtr) + of->nd); -+ t_NdStatistics* nd_stats = (t_NdStatistics*)(PTR_TO_UINT(NDDescriptor->p_Statistics) + fmMuramVirtBaseAddr); -+ t_DsarIcmpV6Descriptor* ICMPV6Descriptor = (t_DsarIcmpV6Descriptor*)(PTR_TO_UINT(ArCommonDescPtr) + of->icmpv6); -+ t_DsarIcmpV6Statistics* icmpv6_stats = (t_DsarIcmpV6Statistics*)(PTR_TO_UINT(ICMPV6Descriptor->p_Statistics) + fmMuramVirtBaseAddr); -+ t_DsarSnmpDescriptor* SnmpDescriptor = (t_DsarSnmpDescriptor*)(PTR_TO_UINT(ArCommonDescPtr) + of->snmp); -+ t_DsarSnmpStatistics* snmp_stats = (t_DsarSnmpStatistics*)(PTR_TO_UINT(SnmpDescriptor->p_Statistics) + fmMuramVirtBaseAddr); -+ stats->arpArCnt = arp_stats->arCnt; -+ stats->echoIcmpv4ArCnt = icmpv4_stats->arCnt; -+ stats->ndpArCnt = nd_stats->arCnt; -+ stats->echoIcmpv6ArCnt = icmpv6_stats->arCnt; -+ stats->snmpGetCnt = snmp_stats->snmpGetReqCnt; -+ stats->snmpGetNextCnt = snmp_stats->snmpGetNextReqCnt; -+ return E_OK; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port.h -@@ -0,0 +1,999 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_port.h -+ -+ @Description FM Port internal structures and definitions. -+*//***************************************************************************/ -+#ifndef __FM_PORT_H -+#define __FM_PORT_H -+ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "fm_port_ext.h" -+ -+#include "fm_common.h" -+#include "fm_sp_common.h" -+#include "fsl_fman_sp.h" -+#include "fm_port_ext.h" -+#include "fsl_fman_port.h" -+ -+#define __ERR_MODULE__ MODULE_FM_PORT -+ -+ -+#define MIN_EXT_BUF_SIZE 64 -+#define DATA_ALIGNMENT 64 -+#define MAX_LIODN_OFFSET 64 -+#define MAX_PORT_FIFO_SIZE MIN(BMI_MAX_FIFO_SIZE, 1024*BMI_FIFO_UNITS) -+ -+/**************************************************************************//** -+ @Description Memory Map defines -+*//***************************************************************************/ -+#define BMI_PORT_REGS_OFFSET 0 -+#define QMI_PORT_REGS_OFFSET 0x400 -+#define PRS_PORT_REGS_OFFSET 0x800 -+ -+/**************************************************************************//** -+ @Description defaults -+*//***************************************************************************/ -+#define DEFAULT_PORT_deqHighPriority_1G FALSE -+#define DEFAULT_PORT_deqHighPriority_10G TRUE -+#define DEFAULT_PORT_deqType e_FM_PORT_DEQ_TYPE1 -+#define DEFAULT_PORT_deqPrefetchOption e_FM_PORT_DEQ_FULL_PREFETCH -+#define DEFAULT_PORT_deqPrefetchOption_HC e_FM_PORT_DEQ_NO_PREFETCH -+#define DEFAULT_PORT_deqByteCnt_10G 0x1400 -+#define DEFAULT_PORT_deqByteCnt_1G 0x400 -+#define DEFAULT_PORT_bufferPrefixContent_privDataSize DEFAULT_FM_SP_bufferPrefixContent_privDataSize -+#define DEFAULT_PORT_bufferPrefixContent_passPrsResult DEFAULT_FM_SP_bufferPrefixContent_passPrsResult -+#define DEFAULT_PORT_bufferPrefixContent_passTimeStamp DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp -+#define DEFAULT_PORT_bufferPrefixContent_allOtherPCDInfo DEFAULT_FM_SP_bufferPrefixContent_allOtherPCDInfo -+#define DEFAULT_PORT_bufferPrefixContent_dataAlign DEFAULT_FM_SP_bufferPrefixContent_dataAlign -+#define DEFAULT_PORT_cheksumLastBytesIgnore 0 -+#define DEFAULT_PORT_cutBytesFromEnd 4 -+#define DEFAULT_PORT_fifoDeqPipelineDepth_IM 2 -+ -+#define DEFAULT_PORT_frmDiscardOverride FALSE -+ -+#define DEFAULT_PORT_dmaSwapData (e_FmDmaSwapOption)DEFAULT_FMAN_SP_DMA_SWAP_DATA -+#define DEFAULT_PORT_dmaIntContextCacheAttr (e_FmDmaCacheOption)DEFAULT_FMAN_SP_DMA_INT_CONTEXT_CACHE_ATTR -+#define DEFAULT_PORT_dmaHeaderCacheAttr (e_FmDmaCacheOption)DEFAULT_FMAN_SP_DMA_HEADER_CACHE_ATTR -+#define DEFAULT_PORT_dmaScatterGatherCacheAttr (e_FmDmaCacheOption)DEFAULT_FMAN_SP_DMA_SCATTER_GATHER_CACHE_ATTR -+#define DEFAULT_PORT_dmaWriteOptimize DEFAULT_FMAN_SP_DMA_WRITE_OPTIMIZE -+ -+#define DEFAULT_PORT_noScatherGather DEFAULT_FMAN_SP_NO_SCATTER_GATHER -+#define DEFAULT_PORT_forwardIntContextReuse FALSE -+#define DEFAULT_PORT_BufMargins_startMargins 32 -+#define DEFAULT_PORT_BufMargins_endMargins 0 -+#define DEFAULT_PORT_syncReq TRUE -+#define DEFAULT_PORT_syncReqForHc FALSE -+#define DEFAULT_PORT_color e_FM_PORT_COLOR_GREEN -+#define DEFAULT_PORT_errorsToDiscard FM_PORT_FRM_ERR_CLS_DISCARD -+/* #define DEFAULT_PORT_dualRateLimitScaleDown e_FM_PORT_DUAL_RATE_LIMITER_NONE */ -+/* #define DEFAULT_PORT_rateLimitBurstSizeHighGranularity FALSE */ -+#define DEFAULT_PORT_exception IM_EV_BSY -+#define DEFAULT_PORT_maxFrameLength 9600 -+ -+#define DEFAULT_notSupported 0xff -+ -+#if (DPAA_VERSION < 11) -+#define DEFAULT_PORT_rxFifoPriElevationLevel MAX_PORT_FIFO_SIZE -+#define DEFAULT_PORT_rxFifoThreshold (MAX_PORT_FIFO_SIZE*3/4) -+ -+#define DEFAULT_PORT_txFifoMinFillLevel 0 -+#define DEFAULT_PORT_txFifoLowComfLevel (5*KILOBYTE) -+#define DEFAULT_PORT_fifoDeqPipelineDepth_1G 1 -+#define DEFAULT_PORT_fifoDeqPipelineDepth_10G 4 -+ -+#define DEFAULT_PORT_fifoDeqPipelineDepth_OH 2 -+ -+/* Host command port MUST NOT be changed to more than 1 !!! */ -+#define DEFAULT_PORT_numOfTasks(type) \ -+ (uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \ -+ ((type) == e_FM_PORT_TYPE_TX_10G)) ? 16 : \ -+ ((((type) == e_FM_PORT_TYPE_RX) || \ -+ ((type) == e_FM_PORT_TYPE_TX) || \ -+ ((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) ? 3 : 1)) -+ -+#define DEFAULT_PORT_extraNumOfTasks(type) \ -+ (uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G) ? 8 : \ -+ (((type) == e_FM_PORT_TYPE_RX) ? 2 : 0)) -+ -+#define DEFAULT_PORT_numOfOpenDmas(type) \ -+ (uint32_t)((((type) == e_FM_PORT_TYPE_TX_10G) || \ -+ ((type) == e_FM_PORT_TYPE_RX_10G)) ? 8 : 1 ) -+ -+#define DEFAULT_PORT_extraNumOfOpenDmas(type) \ -+ (uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G) ? 8 : \ -+ (((type) == e_FM_PORT_TYPE_RX) ? 1 : 0)) -+ -+#define DEFAULT_PORT_numOfFifoBufs(type) \ -+ (uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \ -+ ((type) == e_FM_PORT_TYPE_TX_10G)) ? 48 : \ -+ ((type) == e_FM_PORT_TYPE_RX) ? 45 : \ -+ ((type) == e_FM_PORT_TYPE_TX) ? 44 : 8) -+ -+#define DEFAULT_PORT_extraNumOfFifoBufs 0 -+ -+#else /* (DPAA_VERSION < 11) */ -+/* Defaults are registers' reset values */ -+#define DEFAULT_PORT_rxFifoPriElevationLevel MAX_PORT_FIFO_SIZE -+#define DEFAULT_PORT_rxFifoThreshold MAX_PORT_FIFO_SIZE -+ -+#define DEFAULT_PORT_txFifoMinFillLevel 0 -+#define DEFAULT_PORT_txFifoLowComfLevel (5 * KILOBYTE) -+#define DEFAULT_PORT_fifoDeqPipelineDepth_1G 2 -+#define DEFAULT_PORT_fifoDeqPipelineDepth_10G 4 -+ -+#define DEFAULT_PORT_fifoDeqPipelineDepth_OH 2 -+ -+#define DEFAULT_PORT_numOfTasks(type) \ -+ (uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \ -+ ((type) == e_FM_PORT_TYPE_TX_10G)) ? 14 : \ -+ (((type) == e_FM_PORT_TYPE_RX) || \ -+ ((type) == e_FM_PORT_TYPE_TX)) ? 4 : \ -+ ((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) ? 6 : 1) -+ -+#define DEFAULT_PORT_extraNumOfTasks(type) 0 -+ -+#define DEFAULT_PORT_numOfOpenDmas(type) \ -+ (uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G) ? 8 : \ -+ ((type) == e_FM_PORT_TYPE_TX_10G) ? 12 : \ -+ ((type) == e_FM_PORT_TYPE_RX) ? 2 : \ -+ ((type) == e_FM_PORT_TYPE_TX) ? 3 : \ -+ ((type) == e_FM_PORT_TYPE_OH_HOST_COMMAND) ? 2 : 4) -+ -+#define DEFAULT_PORT_extraNumOfOpenDmas(type) 0 -+ -+#define DEFAULT_PORT_numOfFifoBufs(type) \ -+ (uint32_t) (((type) == e_FM_PORT_TYPE_RX_10G) ? 96 : \ -+ ((type) == e_FM_PORT_TYPE_TX_10G) ? 64 : \ -+ ((type) == e_FM_PORT_TYPE_OH_HOST_COMMAND) ? 10 : 50) -+ -+#define DEFAULT_PORT_extraNumOfFifoBufs 0 -+ -+#endif /* (DPAA_VERSION < 11) */ -+ -+#define DEFAULT_PORT_txBdRingLength 16 -+#define DEFAULT_PORT_rxBdRingLength 128 -+#define DEFAULT_PORT_ImfwExtStructsMemId 0 -+#define DEFAULT_PORT_ImfwExtStructsMemAttr MEMORY_ATTR_CACHEABLE -+ -+#define FM_PORT_CG_REG_NUM(_cgId) (((FM_PORT_NUM_OF_CONGESTION_GRPS/32)-1)-_cgId/32) -+ -+/**************************************************************************//** -+ @Collection PCD Engines -+*//***************************************************************************/ -+typedef uint32_t fmPcdEngines_t; /**< options as defined below: */ -+ -+#define FM_PCD_NONE 0 /**< No PCD Engine indicated */ -+#define FM_PCD_PRS 0x80000000 /**< Parser indicated */ -+#define FM_PCD_KG 0x40000000 /**< Keygen indicated */ -+#define FM_PCD_CC 0x20000000 /**< Coarse classification indicated */ -+#define FM_PCD_PLCR 0x10000000 /**< Policer indicated */ -+#define FM_PCD_MANIP 0x08000000 /**< Manipulation indicated */ -+/* @} */ -+ -+#define FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS 8 -+#define FM_PORT_MAX_NUM_OF_CONGESTION_GRPS_ALL_INTEGRATIONS 256 -+#define FM_PORT_CG_REG_NUM(_cgId) (((FM_PORT_NUM_OF_CONGESTION_GRPS/32)-1)-_cgId/32) -+ -+#define FM_OH_PORT_ID 0 -+ -+/***********************************************************************/ -+/* SW parser OFFLOAD labels (offsets) */ -+/***********************************************************************/ -+#if (DPAA_VERSION == 10) -+#define OFFLOAD_SW_PATCH_IPv4_IPR_LABEL 0x300 -+#define OFFLOAD_SW_PATCH_IPv6_IPR_LABEL 0x325 -+#define OFFLOAD_SW_PATCH_IPv6_IPF_LABEL 0x325 -+#else -+#define OFFLOAD_SW_PATCH_IPv4_IPR_LABEL 0x100 -+/* Will be used for: -+ * 1. identify fragments -+ * 2. udp-lite -+ */ -+#define OFFLOAD_SW_PATCH_IPv6_IPR_LABEL 0x146 -+/* Will be used for: -+ * 1. will identify the fragmentable area -+ * 2. udp-lite -+ */ -+#define OFFLOAD_SW_PATCH_IPv6_IPF_LABEL 0x261 -+#define OFFLOAD_SW_PATCH_CAPWAP_LABEL 0x38d -+#endif /* (DPAA_VERSION == 10) */ -+ -+#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+#define UDP_LITE_SW_PATCH_LABEL 0x2E0 -+#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+ -+ -+/**************************************************************************//** -+ @Description Memory Mapped Registers -+*//***************************************************************************/ -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+typedef struct -+{ -+ volatile uint32_t fmbm_rcfg; /**< Rx Configuration */ -+ volatile uint32_t fmbm_rst; /**< Rx Status */ -+ volatile uint32_t fmbm_rda; /**< Rx DMA attributes*/ -+ volatile uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/ -+ volatile uint32_t fmbm_rfed; /**< Rx Frame End Data*/ -+ volatile uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/ -+ volatile uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/ -+ volatile uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/ -+ volatile uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/ -+ volatile uint32_t fmbm_rfca; /**< Rx Frame Command Attributes.*/ -+ volatile uint32_t fmbm_rfpne; /**< Rx Frame Parser Next Engine*/ -+ volatile uint32_t fmbm_rpso; /**< Rx Parse Start Offset*/ -+ volatile uint32_t fmbm_rpp; /**< Rx Policer Profile */ -+ volatile uint32_t fmbm_rccb; /**< Rx Coarse Classification Base */ -+ volatile uint32_t fmbm_reth; /**< Rx Excessive Threshold */ -+ volatile uint32_t reserved1[0x01];/**< (0x03C) */ -+ volatile uint32_t fmbm_rprai[FM_PORT_PRS_RESULT_NUM_OF_WORDS]; -+ /**< Rx Parse Results Array Initialization*/ -+ volatile uint32_t fmbm_rfqid; /**< Rx Frame Queue ID*/ -+ volatile uint32_t fmbm_refqid; /**< Rx Error Frame Queue ID*/ -+ volatile uint32_t fmbm_rfsdm; /**< Rx Frame Status Discard Mask*/ -+ volatile uint32_t fmbm_rfsem; /**< Rx Frame Status Error Mask*/ -+ volatile uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */ -+ volatile uint32_t reserved2[0x02];/**< (0x074-0x078) */ -+ volatile uint32_t fmbm_rcmne; /**< Rx Frame Continuous Mode Next Engine */ -+ volatile uint32_t reserved3[0x20];/**< (0x080 0x0FF) */ -+ volatile uint32_t fmbm_ebmpi[FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS]; -+ /**< Buffer Manager pool Information-*/ -+ volatile uint32_t fmbm_acnt[FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS]; -+ /**< Allocate Counter-*/ -+ volatile uint32_t reserved4[0x08]; -+ /**< 0x130/0x140 - 0x15F reserved -*/ -+ volatile uint32_t fmbm_rcgm[FM_PORT_MAX_NUM_OF_CONGESTION_GRPS_ALL_INTEGRATIONS/32]; -+ /**< Congestion Group Map*/ -+ volatile uint32_t fmbm_rmpd; /**< BM Pool Depletion */ -+ volatile uint32_t reserved5[0x1F];/**< (0x184 0x1FF) */ -+ volatile uint32_t fmbm_rstc; /**< Rx Statistics Counters*/ -+ volatile uint32_t fmbm_rfrc; /**< Rx Frame Counter*/ -+ volatile uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/ -+ volatile uint32_t fmbm_rlfc; /**< Rx Large Frames Counter*/ -+ volatile uint32_t fmbm_rffc; /**< Rx Filter Frames Counter*/ -+ volatile uint32_t fmbm_rfcd; /**< Rx Frame Discard Counter*/ -+ volatile uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/ -+ volatile uint32_t fmbm_rodc; /**< Rx Out of Buffers Discard Counter-*/ -+ volatile uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter-*/ -+ volatile uint32_t fmbm_rpec; /**< Rx RX Prepare to enqueue Counter-*/ -+ volatile uint32_t reserved6[0x16];/**< (0x228 0x27F) */ -+ volatile uint32_t fmbm_rpc; /**< Rx Performance Counters*/ -+ volatile uint32_t fmbm_rpcp; /**< Rx Performance Count Parameters*/ -+ volatile uint32_t fmbm_rccn; /**< Rx Cycle Counter*/ -+ volatile uint32_t fmbm_rtuc; /**< Rx Tasks Utilization Counter*/ -+ volatile uint32_t fmbm_rrquc; /**< Rx Receive Queue Utilization Counter*/ -+ volatile uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/ -+ volatile uint32_t fmbm_rfuc; /**< Rx FIFO Utilization Counter*/ -+ volatile uint32_t fmbm_rpac; /**< Rx Pause Activation Counter*/ -+ volatile uint32_t reserved7[0x18];/**< (0x2A0-0x2FF) */ -+ volatile uint32_t fmbm_rdcfg[0x3];/**< Rx Debug-*/ -+ volatile uint32_t fmbm_rgpr; /**< Rx General Purpose Register. */ -+ volatile uint32_t reserved8[0x3a];/**< (0x310-0x3FF) */ -+} t_FmPortRxBmiRegs; -+ -+typedef struct -+{ -+ volatile uint32_t fmbm_tcfg; /**< Tx Configuration */ -+ volatile uint32_t fmbm_tst; /**< Tx Status */ -+ volatile uint32_t fmbm_tda; /**< Tx DMA attributes */ -+ volatile uint32_t fmbm_tfp; /**< Tx FIFO Parameters */ -+ volatile uint32_t fmbm_tfed; /**< Tx Frame End Data */ -+ volatile uint32_t fmbm_ticp; /**< Tx Internal Context Parameters */ -+ volatile uint32_t fmbm_tfdne; /**< Tx Frame Dequeue Next Engine. */ -+ volatile uint32_t fmbm_tfca; /**< Tx Frame Command attribute. */ -+ volatile uint32_t fmbm_tcfqid; /**< Tx Confirmation Frame Queue ID. */ -+ volatile uint32_t fmbm_tfeqid; /**< Tx Frame Error Queue ID */ -+ volatile uint32_t fmbm_tfene; /**< Tx Frame Enqueue Next Engine */ -+ volatile uint32_t fmbm_trlmts; /**< Tx Rate Limiter Scale */ -+ volatile uint32_t fmbm_trlmt; /**< Tx Rate Limiter */ -+ volatile uint32_t fmbm_tccb; /**< Tx Coarse Classification Base */ -+ volatile uint32_t reserved0[0x0e];/**< (0x038-0x070) */ -+ volatile uint32_t fmbm_tfne; /**< Tx Frame Next Engine */ -+ volatile uint32_t fmbm_tpfcm[0x02];/**< Tx Priority based Flow Control (PFC) Mapping */ -+ volatile uint32_t fmbm_tcmne; /**< Tx Frame Continuous Mode Next Engine */ -+ volatile uint32_t reserved2[0x60];/**< (0x080-0x200) */ -+ volatile uint32_t fmbm_tstc; /**< Tx Statistics Counters */ -+ volatile uint32_t fmbm_tfrc; /**< Tx Frame Counter */ -+ volatile uint32_t fmbm_tfdc; /**< Tx Frames Discard Counter */ -+ volatile uint32_t fmbm_tfledc; /**< Tx Frame Length error discard counter */ -+ volatile uint32_t fmbm_tfufdc; /**< Tx Frame unsupported format discard Counter */ -+ volatile uint32_t fmbm_tbdc; /**< Tx Buffers Deallocate Counter */ -+ volatile uint32_t reserved3[0x1A];/**< (0x218-0x280) */ -+ volatile uint32_t fmbm_tpc; /**< Tx Performance Counters*/ -+ volatile uint32_t fmbm_tpcp; /**< Tx Performance Count Parameters*/ -+ volatile uint32_t fmbm_tccn; /**< Tx Cycle Counter*/ -+ volatile uint32_t fmbm_ttuc; /**< Tx Tasks Utilization Counter*/ -+ volatile uint32_t fmbm_ttcquc; /**< Tx Transmit Confirm Queue Utilization Counter*/ -+ volatile uint32_t fmbm_tduc; /**< Tx DMA Utilization Counter*/ -+ volatile uint32_t fmbm_tfuc; /**< Tx FIFO Utilization Counter*/ -+ volatile uint32_t reserved4[16]; /**< (0x29C-0x2FF) */ -+ volatile uint32_t fmbm_tdcfg[0x3];/**< Tx Debug-*/ -+ volatile uint32_t fmbm_tgpr; /**< O/H General Purpose Register */ -+ volatile uint32_t reserved5[0x3a];/**< (0x310-0x3FF) */ -+} t_FmPortTxBmiRegs; -+ -+typedef struct -+{ -+ volatile uint32_t fmbm_ocfg; /**< O/H Configuration */ -+ volatile uint32_t fmbm_ost; /**< O/H Status */ -+ volatile uint32_t fmbm_oda; /**< O/H DMA attributes */ -+ volatile uint32_t fmbm_oicp; /**< O/H Internal Context Parameters */ -+ volatile uint32_t fmbm_ofdne; /**< O/H Frame Dequeue Next Engine */ -+ volatile uint32_t fmbm_ofne; /**< O/H Frame Next Engine */ -+ volatile uint32_t fmbm_ofca; /**< O/H Frame Command Attributes. */ -+ volatile uint32_t fmbm_ofpne; /**< O/H Frame Parser Next Engine */ -+ volatile uint32_t fmbm_opso; /**< O/H Parse Start Offset */ -+ volatile uint32_t fmbm_opp; /**< O/H Policer Profile */ -+ volatile uint32_t fmbm_occb; /**< O/H Coarse Classification base */ -+ volatile uint32_t fmbm_oim; /**< O/H Internal margins*/ -+ volatile uint32_t fmbm_ofp; /**< O/H Fifo Parameters*/ -+ volatile uint32_t fmbm_ofed; /**< O/H Frame End Data*/ -+ volatile uint32_t reserved0[2]; /**< (0x038 - 0x03F) */ -+ volatile uint32_t fmbm_oprai[FM_PORT_PRS_RESULT_NUM_OF_WORDS]; -+ /**< O/H Parse Results Array Initialization */ -+ volatile uint32_t fmbm_ofqid; /**< O/H Frame Queue ID */ -+ volatile uint32_t fmbm_oefqid; /**< O/H Error Frame Queue ID */ -+ volatile uint32_t fmbm_ofsdm; /**< O/H Frame Status Discard Mask */ -+ volatile uint32_t fmbm_ofsem; /**< O/H Frame Status Error Mask */ -+ volatile uint32_t fmbm_ofene; /**< O/H Frame Enqueue Next Engine */ -+ volatile uint32_t fmbm_orlmts; /**< O/H Rate Limiter Scale */ -+ volatile uint32_t fmbm_orlmt; /**< O/H Rate Limiter */ -+ volatile uint32_t fmbm_ocmne; /**< O/H Continuous Mode Next Engine */ -+ volatile uint32_t reserved1[0x20];/**< (0x080 - 0x0FF) */ -+ volatile uint32_t fmbm_oebmpi[2]; /**< Buffer Manager Observed Pool Information */ -+ volatile uint32_t reserved2[0x16];/**< (0x108 - 0x15F) */ -+ volatile uint32_t fmbm_ocgm; /**< Observed Congestion Group Map */ -+ volatile uint32_t reserved3[0x7]; /**< (0x164 - 0x17F) */ -+ volatile uint32_t fmbm_ompd; /**< Observed BMan Pool Depletion */ -+ volatile uint32_t reserved4[0x1F];/**< (0x184 - 0x1FF) */ -+ volatile uint32_t fmbm_ostc; /**< O/H Statistics Counters */ -+ volatile uint32_t fmbm_ofrc; /**< O/H Frame Counter */ -+ volatile uint32_t fmbm_ofdc; /**< O/H Frames Discard Counter */ -+ volatile uint32_t fmbm_ofledc; /**< O/H Frames Length Error Discard Counter */ -+ volatile uint32_t fmbm_ofufdc; /**< O/H Frames Unsupported Format Discard Counter */ -+ volatile uint32_t fmbm_offc; /**< O/H Filter Frames Counter */ -+ volatile uint32_t fmbm_ofwdc; /**< - Rx Frames WRED Discard Counter */ -+ volatile uint32_t fmbm_ofldec; /**< O/H Frames List DMA Error Counter */ -+ volatile uint32_t fmbm_obdc; /**< O/H Buffers Deallocate Counter */ -+ volatile uint32_t fmbm_oodc; /**< O/H Out of Buffers Discard Counter */ -+ volatile uint32_t fmbm_opec; /**< O/H Prepare to enqueue Counter */ -+ volatile uint32_t reserved5[0x15];/**< ( - 0x27F) */ -+ volatile uint32_t fmbm_opc; /**< O/H Performance Counters */ -+ volatile uint32_t fmbm_opcp; /**< O/H Performance Count Parameters */ -+ volatile uint32_t fmbm_occn; /**< O/H Cycle Counter */ -+ volatile uint32_t fmbm_otuc; /**< O/H Tasks Utilization Counter */ -+ volatile uint32_t fmbm_oduc; /**< O/H DMA Utilization Counter */ -+ volatile uint32_t fmbm_ofuc; /**< O/H FIFO Utilization Counter */ -+ volatile uint32_t reserved6[26]; /**< (0x298-0x2FF) */ -+ volatile uint32_t fmbm_odcfg[0x3];/**< O/H Debug (only 1 in P1023) */ -+ volatile uint32_t fmbm_ogpr; /**< O/H General Purpose Register. */ -+ volatile uint32_t reserved7[0x3a];/**< (0x310 0x3FF) */ -+} t_FmPortOhBmiRegs; -+ -+typedef union -+{ -+ t_FmPortRxBmiRegs rxPortBmiRegs; -+ t_FmPortTxBmiRegs txPortBmiRegs; -+ t_FmPortOhBmiRegs ohPortBmiRegs; -+} u_FmPortBmiRegs; -+ -+typedef struct -+{ -+ volatile uint32_t reserved1[2]; /**< 0xn024 - 0x02B */ -+ volatile uint32_t fmqm_pndn; /**< PortID n Dequeue NIA Register */ -+ volatile uint32_t fmqm_pndc; /**< PortID n Dequeue Config Register */ -+ volatile uint32_t fmqm_pndtfc; /**< PortID n Dequeue Total Frame Counter */ -+ volatile uint32_t fmqm_pndfdc; /**< PortID n Dequeue FQID from Default Counter */ -+ volatile uint32_t fmqm_pndcc; /**< PortID n Dequeue Confirm Counter */ -+} t_FmPortNonRxQmiRegs; -+ -+typedef struct -+{ -+ volatile uint32_t fmqm_pnc; /**< PortID n Configuration Register */ -+ volatile uint32_t fmqm_pns; /**< PortID n Status Register */ -+ volatile uint32_t fmqm_pnts; /**< PortID n Task Status Register */ -+ volatile uint32_t reserved0[4]; /**< 0xn00C - 0xn01B */ -+ volatile uint32_t fmqm_pnen; /**< PortID n Enqueue NIA Register */ -+ volatile uint32_t fmqm_pnetfc; /**< PortID n Enqueue Total Frame Counter */ -+ t_FmPortNonRxQmiRegs nonRxQmiRegs; /**< Registers for Tx Hc & Op ports */ -+} t_FmPortQmiRegs; -+ -+typedef struct -+{ -+ struct -+ { -+ volatile uint32_t softSeqAttach; /**< Soft Sequence Attachment */ -+ volatile uint32_t lcv; /**< Line-up Enable Confirmation Mask */ -+ } hdrs[FM_PCD_PRS_NUM_OF_HDRS]; -+ volatile uint32_t reserved0[0xde]; -+ volatile uint32_t pcac; /**< Parse Internal Memory Configuration Access Control Register */ -+ volatile uint32_t pctpid; /**< Parse Internal Memory Configured TPID Register */ -+} t_FmPortPrsRegs; -+ -+/**************************************************************************//* -+ @Description Basic buffer descriptor (BD) structure -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ volatile uint16_t status; -+ volatile uint16_t length; -+ volatile uint8_t reserved0[0x6]; -+ volatile uint8_t reserved1[0x1]; -+ volatile t_FmPhysAddr buff; -+} _PackedType t_FmImBd; -+ -+typedef _Packed struct -+{ -+ volatile uint16_t gen; /**< tbd */ -+ volatile uint8_t reserved0[0x1]; -+ volatile t_FmPhysAddr bdRingBase; /**< tbd */ -+ volatile uint16_t bdRingSize; /**< tbd */ -+ volatile uint16_t offsetIn; /**< tbd */ -+ volatile uint16_t offsetOut; /**< tbd */ -+ volatile uint8_t reserved1[0x12]; /**< 0x0e - 0x1f */ -+} _PackedType t_FmPortImQd; -+ -+typedef _Packed struct -+{ -+ volatile uint32_t mode; /**< Mode register */ -+ volatile uint32_t rxQdPtr; /**< tbd */ -+ volatile uint32_t txQdPtr; /**< tbd */ -+ volatile uint16_t mrblr; /**< tbd */ -+ volatile uint16_t rxQdBsyCnt; /**< tbd */ -+ volatile uint8_t reserved0[0x10]; /**< 0x10 - 0x1f */ -+ t_FmPortImQd rxQd; -+ t_FmPortImQd txQd; -+ volatile uint8_t reserved1[0xa0]; /**< 0x60 - 0xff */ -+} _PackedType t_FmPortImPram; -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+ -+/**************************************************************************//** -+ @Description Registers bit fields -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description BMI defines -+*//***************************************************************************/ -+#if (DPAA_VERSION >= 11) -+#define BMI_SP_ID_MASK 0xff000000 -+#define BMI_SP_ID_SHIFT 24 -+#define BMI_SP_EN 0x01000000 -+#endif /* (DPAA_VERSION >= 11) */ -+ -+#define BMI_PORT_CFG_EN 0x80000000 -+#define BMI_PORT_CFG_EN_MACSEC 0x00800000 -+#define BMI_PORT_CFG_FDOVR 0x02000000 -+#define BMI_PORT_CFG_IM 0x01000000 -+#define BMI_PORT_CFG_AM 0x00000040 -+#define BMI_PORT_STATUS_BSY 0x80000000 -+#define BMI_COUNTERS_EN 0x80000000 -+ -+#define BMI_PORT_RFNE_FRWD_DCL4C 0x10000000 -+#define BMI_PORT_RFNE_FRWD_RPD 0x40000000 -+#define BMI_RFNE_FDCS_MASK 0xFF000000 -+#define BMI_RFNE_HXS_MASK 0x000000FF -+ -+#define BMI_CMD_MR_LEAC 0x00200000 -+#define BMI_CMD_MR_SLEAC 0x00100000 -+#define BMI_CMD_MR_MA 0x00080000 -+#define BMI_CMD_MR_DEAS 0x00040000 -+#define BMI_CMD_RX_MR_DEF (BMI_CMD_MR_LEAC | \ -+ BMI_CMD_MR_SLEAC | \ -+ BMI_CMD_MR_MA | \ -+ BMI_CMD_MR_DEAS) -+#define BMI_CMD_ATTR_ORDER 0x80000000 -+#define BMI_CMD_ATTR_SYNC 0x02000000 -+#define BMI_CMD_ATTR_MODE_MISS_ALLIGN_ADDR_EN 0x00080000 -+#define BMI_CMD_ATTR_MACCMD_MASK 0x0000ff00 -+#define BMI_CMD_ATTR_MACCMD_OVERRIDE 0x00008000 -+#define BMI_CMD_ATTR_MACCMD_SECURED 0x00001000 -+#define BMI_CMD_ATTR_MACCMD_SC_MASK 0x00000f00 -+ -+#define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000 -+#define BMI_STATUS_RX_MASK_UNUSED (uint32_t)(~(FM_PORT_FRM_ERR_DMA | \ -+ FM_PORT_FRM_ERR_PHYSICAL | \ -+ FM_PORT_FRM_ERR_SIZE | \ -+ FM_PORT_FRM_ERR_CLS_DISCARD | \ -+ FM_PORT_FRM_ERR_EXTRACTION | \ -+ FM_PORT_FRM_ERR_NO_SCHEME | \ -+ FM_PORT_FRM_ERR_COLOR_RED | \ -+ FM_PORT_FRM_ERR_COLOR_YELLOW | \ -+ FM_PORT_FRM_ERR_ILL_PLCR | \ -+ FM_PORT_FRM_ERR_PLCR_FRAME_LEN | \ -+ FM_PORT_FRM_ERR_PRS_TIMEOUT | \ -+ FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT | \ -+ FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED | \ -+ FM_PORT_FRM_ERR_PRS_HDR_ERR | \ -+ FM_PORT_FRM_ERR_IPRE | \ -+ FM_PORT_FRM_ERR_IPR_NCSP | \ -+ FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW)) -+ -+#define BMI_STATUS_OP_MASK_UNUSED (uint32_t)(BMI_STATUS_RX_MASK_UNUSED & \ -+ ~(FM_PORT_FRM_ERR_LENGTH | \ -+ FM_PORT_FRM_ERR_NON_FM | \ -+ FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT)) -+ -+#define BMI_RATE_LIMIT_EN 0x80000000 -+#define BMI_RATE_LIMIT_BURST_SIZE_GRAN 0x80000000 -+#define BMI_RATE_LIMIT_SCALE_BY_2 0x00000001 -+#define BMI_RATE_LIMIT_SCALE_BY_4 0x00000002 -+#define BMI_RATE_LIMIT_SCALE_BY_8 0x00000003 -+ -+#define BMI_RX_FIFO_THRESHOLD_BC 0x80000000 -+ -+#define BMI_PRS_RESULT_HIGH 0x00000000 -+#define BMI_PRS_RESULT_LOW 0xFFFFFFFF -+ -+ -+#define RX_ERRS_TO_ENQ (FM_PORT_FRM_ERR_DMA | \ -+ FM_PORT_FRM_ERR_PHYSICAL | \ -+ FM_PORT_FRM_ERR_SIZE | \ -+ FM_PORT_FRM_ERR_EXTRACTION | \ -+ FM_PORT_FRM_ERR_NO_SCHEME | \ -+ FM_PORT_FRM_ERR_ILL_PLCR | \ -+ FM_PORT_FRM_ERR_PLCR_FRAME_LEN | \ -+ FM_PORT_FRM_ERR_PRS_TIMEOUT | \ -+ FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT | \ -+ FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED | \ -+ FM_PORT_FRM_ERR_PRS_HDR_ERR | \ -+ FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW | \ -+ FM_PORT_FRM_ERR_IPRE) -+ -+#define OP_ERRS_TO_ENQ (RX_ERRS_TO_ENQ | \ -+ FM_PORT_FRM_ERR_LENGTH | \ -+ FM_PORT_FRM_ERR_NON_FM | \ -+ FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT) -+ -+ -+#define BMI_RX_FIFO_PRI_ELEVATION_MASK 0x03FF0000 -+#define BMI_RX_FIFO_THRESHOLD_MASK 0x000003FF -+#define BMI_TX_FIFO_MIN_FILL_MASK 0x03FF0000 -+#define BMI_FIFO_PIPELINE_DEPTH_MASK 0x0000F000 -+#define BMI_TX_LOW_COMF_MASK 0x000003FF -+ -+/* shifts */ -+#define BMI_PORT_CFG_MS_SEL_SHIFT 16 -+#define BMI_DMA_ATTR_IC_CACHE_SHIFT FMAN_SP_DMA_ATTR_IC_CACHE_SHIFT -+#define BMI_DMA_ATTR_HDR_CACHE_SHIFT FMAN_SP_DMA_ATTR_HDR_CACHE_SHIFT -+#define BMI_DMA_ATTR_SG_CACHE_SHIFT FMAN_SP_DMA_ATTR_SG_CACHE_SHIFT -+ -+#define BMI_IM_FOF_SHIFT 28 -+#define BMI_PR_PORTID_SHIFT 24 -+ -+#define BMI_RX_FIFO_PRI_ELEVATION_SHIFT 16 -+#define BMI_RX_FIFO_THRESHOLD_SHIFT 0 -+ -+#define BMI_RX_FRAME_END_CS_IGNORE_SHIFT 24 -+#define BMI_RX_FRAME_END_CUT_SHIFT 16 -+ -+#define BMI_IC_SIZE_SHIFT FMAN_SP_IC_SIZE_SHIFT -+ -+#define BMI_INT_BUF_MARG_SHIFT 28 -+ -+#define BMI_EXT_BUF_MARG_END_SHIFT FMAN_SP_EXT_BUF_MARG_END_SHIFT -+ -+#define BMI_CMD_ATTR_COLOR_SHIFT 26 -+#define BMI_CMD_ATTR_COM_MODE_SHIFT 16 -+#define BMI_CMD_ATTR_MACCMD_SHIFT 8 -+#define BMI_CMD_ATTR_MACCMD_OVERRIDE_SHIFT 15 -+#define BMI_CMD_ATTR_MACCMD_SECURED_SHIFT 12 -+#define BMI_CMD_ATTR_MACCMD_SC_SHIFT 8 -+ -+#define BMI_POOL_DEP_NUM_OF_POOLS_VECTOR_SHIFT 24 -+ -+#define BMI_TX_FIFO_MIN_FILL_SHIFT 16 -+#define BMI_TX_LOW_COMF_SHIFT 0 -+ -+#define BMI_PERFORMANCE_TASK_COMP_SHIFT 24 -+#define BMI_PERFORMANCE_PORT_COMP_SHIFT 16 -+#define BMI_PERFORMANCE_DMA_COMP_SHIFT 12 -+#define BMI_PERFORMANCE_FIFO_COMP_SHIFT 0 -+ -+#define BMI_MAX_BURST_SHIFT 16 -+#define BMI_COUNT_RATE_UNIT_SHIFT 16 -+ -+/* sizes */ -+#define FRAME_END_DATA_SIZE 16 -+#define FRAME_OFFSET_UNITS 16 -+#define MIN_TX_INT_OFFSET 16 -+#define MAX_FRAME_OFFSET 64 -+#define MAX_FIFO_PIPELINE_DEPTH 8 -+#define MAX_PERFORMANCE_TASK_COMP 64 -+#define MAX_PERFORMANCE_TX_QUEUE_COMP 8 -+#define MAX_PERFORMANCE_RX_QUEUE_COMP 64 -+#define MAX_PERFORMANCE_DMA_COMP 16 -+#define MAX_NUM_OF_TASKS 64 -+#define MAX_NUM_OF_EXTRA_TASKS 8 -+#define MAX_NUM_OF_DMAS 16 -+#define MAX_NUM_OF_EXTRA_DMAS 8 -+#define MAX_BURST_SIZE 1024 -+#define MIN_NUM_OF_OP_DMAS 2 -+ -+ -+/**************************************************************************//** -+ @Description QMI defines -+*//***************************************************************************/ -+/* masks */ -+#define QMI_PORT_CFG_EN 0x80000000 -+#define QMI_PORT_CFG_EN_COUNTERS 0x10000000 -+#define QMI_PORT_STATUS_DEQ_TNUM_BSY 0x80000000 -+#define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000 -+ -+#define QMI_DEQ_CFG_PREFETCH_NO_TNUM 0x02000000 -+#define QMI_DEQ_CFG_PREFETCH_WAITING_TNUM 0 -+#define QMI_DEQ_CFG_PREFETCH_1_FRAME 0 -+#define QMI_DEQ_CFG_PREFETCH_3_FRAMES 0x01000000 -+ -+#define QMI_DEQ_CFG_PRI 0x80000000 -+#define QMI_DEQ_CFG_TYPE1 0x10000000 -+#define QMI_DEQ_CFG_TYPE2 0x20000000 -+#define QMI_DEQ_CFG_TYPE3 0x30000000 -+ -+#define QMI_DEQ_CFG_SUBPORTAL_MASK 0x1f -+#define QMI_DEQ_CFG_SUBPORTAL_SHIFT 20 -+ -+/**************************************************************************//** -+ @Description PARSER defines -+*//***************************************************************************/ -+/* masks */ -+#define PRS_HDR_ERROR_DIS 0x00000800 -+#define PRS_HDR_SW_PRS_EN 0x00000400 -+#define PRS_CP_OFFSET_MASK 0x0000000F -+#define PRS_TPID1_MASK 0xFFFF0000 -+#define PRS_TPID2_MASK 0x0000FFFF -+#define PRS_TPID_DFLT 0x91009100 -+ -+#define PRS_HDR_MPLS_LBL_INTER_EN 0x00200000 -+#define PRS_HDR_IPV6_ROUTE_HDR_EN 0x00008000 -+#define PRS_HDR_PPPOE_MTU_CHECK_EN 0x80000000 -+#define PRS_HDR_UDP_PAD_REMOVAL 0x80000000 -+#define PRS_HDR_TCP_PAD_REMOVAL 0x80000000 -+#define PRS_CAC_STOP 0x00000001 -+#define PRS_CAC_ACTIVE 0x00000100 -+ -+/* shifts */ -+#define PRS_PCTPID_SHIFT 16 -+#define PRS_HDR_MPLS_NEXT_HDR_SHIFT 22 -+#define PRS_HDR_ETH_BC_SHIFT 28 -+#define PRS_HDR_ETH_MC_SHIFT 24 -+#define PRS_HDR_VLAN_STACKED_SHIFT 16 -+#define PRS_HDR_MPLS_STACKED_SHIFT 16 -+#define PRS_HDR_IPV4_1_BC_SHIFT 28 -+#define PRS_HDR_IPV4_1_MC_SHIFT 24 -+#define PRS_HDR_IPV4_2_UC_SHIFT 20 -+#define PRS_HDR_IPV4_2_MC_BC_SHIFT 16 -+#define PRS_HDR_IPV6_1_MC_SHIFT 24 -+#define PRS_HDR_IPV6_2_UC_SHIFT 20 -+#define PRS_HDR_IPV6_2_MC_SHIFT 16 -+ -+#define PRS_HDR_ETH_BC_MASK 0x0fffffff -+#define PRS_HDR_ETH_MC_MASK 0xf0ffffff -+#define PRS_HDR_VLAN_STACKED_MASK 0xfff0ffff -+#define PRS_HDR_MPLS_STACKED_MASK 0xfff0ffff -+#define PRS_HDR_IPV4_1_BC_MASK 0x0fffffff -+#define PRS_HDR_IPV4_1_MC_MASK 0xf0ffffff -+#define PRS_HDR_IPV4_2_UC_MASK 0xff0fffff -+#define PRS_HDR_IPV4_2_MC_BC_MASK 0xfff0ffff -+#define PRS_HDR_IPV6_1_MC_MASK 0xf0ffffff -+#define PRS_HDR_IPV6_2_UC_MASK 0xff0fffff -+#define PRS_HDR_IPV6_2_MC_MASK 0xfff0ffff -+ -+/* others */ -+#define PRS_HDR_ENTRY_SIZE 8 -+#define DEFAULT_CLS_PLAN_VECTOR 0xFFFFFFFF -+ -+#define IPSEC_SW_PATCH_START 0x20 -+#define SCTP_SW_PATCH_START 0x4D -+#define DCCP_SW_PATCH_START 0x41 -+ -+/**************************************************************************//** -+ @Description IM defines -+*//***************************************************************************/ -+#define BD_R_E 0x80000000 -+#define BD_L 0x08000000 -+ -+#define BD_RX_CRE 0x00080000 -+#define BD_RX_FTL 0x00040000 -+#define BD_RX_FTS 0x00020000 -+#define BD_RX_OV 0x00010000 -+ -+#define BD_RX_ERRORS (BD_RX_CRE | BD_RX_FTL | BD_RX_FTS | BD_RX_OV) -+ -+#define FM_IM_SIZEOF_BD sizeof(t_FmImBd) -+ -+#define BD_STATUS_MASK 0xffff0000 -+#define BD_LENGTH_MASK 0x0000ffff -+ -+#define BD_STATUS_AND_LENGTH_SET(bd, val) WRITE_UINT32(*(volatile uint32_t*)(bd), (val)) -+ -+#define BD_STATUS_AND_LENGTH(bd) GET_UINT32(*(volatile uint32_t*)(bd)) -+ -+#define BD_GET(id) &p_FmPort->im.p_BdRing[id] -+ -+#define IM_ILEGAL_BD_ID 0xffff -+ -+/* others */ -+#define IM_PRAM_ALIGN 0x100 -+ -+/* masks */ -+#define IM_MODE_GBL 0x20000000 -+#define IM_MODE_BO_MASK 0x18000000 -+#define IM_MODE_BO_SHIFT 3 -+#define IM_MODE_GRC_STP 0x00800000 -+ -+#define IM_MODE_SET_BO(val) (uint32_t)((val << (31-IM_MODE_BO_SHIFT)) & IM_MODE_BO_MASK) -+ -+#define IM_RXQD_BSYINTM 0x0008 -+#define IM_RXQD_RXFINTM 0x0010 -+#define IM_RXQD_FPMEVT_SEL_MASK 0x0003 -+ -+#define IM_EV_BSY 0x40000000 -+#define IM_EV_RX 0x80000000 -+ -+ -+/**************************************************************************//** -+ @Description Additional defines -+*//***************************************************************************/ -+ -+typedef struct { -+ t_Handle h_FmMuram; -+ t_FmPortImPram *p_FmPortImPram; -+ uint8_t fwExtStructsMemId; -+ uint32_t fwExtStructsMemAttr; -+ uint16_t bdRingSize; -+ t_FmImBd *p_BdRing; -+ t_Handle *p_BdShadow; -+ uint16_t currBdId; -+ uint16_t firstBdOfFrameId; -+ -+ /* Rx port parameters */ -+ uint8_t dataMemId; /**< Memory partition ID for data buffers */ -+ uint32_t dataMemAttributes; /**< Memory attributes for data buffers */ -+ t_BufferPoolInfo rxPool; -+ uint16_t mrblr; -+ uint16_t rxFrameAccumLength; -+ t_FmPortImRxStoreCallback *f_RxStore; -+ -+ /* Tx port parameters */ -+ uint32_t txFirstBdStatus; -+ t_FmPortImTxConfCallback *f_TxConf; -+} t_FmMacIm; -+ -+ -+typedef struct { -+ struct fman_port_cfg dfltCfg; -+ uint32_t dfltFqid; -+ uint32_t confFqid; -+ uint32_t errFqid; -+ uintptr_t baseAddr; -+ uint8_t deqSubPortal; -+ bool deqHighPriority; -+ e_FmPortDeqType deqType; -+ e_FmPortDeqPrefetchOption deqPrefetchOption; -+ uint16_t deqByteCnt; -+ uint8_t cheksumLastBytesIgnore; -+ uint8_t cutBytesFromEnd; -+ t_FmBufPoolDepletion bufPoolDepletion; -+ uint8_t pipelineDepth; -+ uint16_t fifoLowComfLevel; -+ bool frmDiscardOverride; -+ bool enRateLimit; -+ t_FmPortRateLimit rateLimit; -+ e_FmPortDualRateLimiterScaleDown rateLimitDivider; -+ bool enBufPoolDepletion; -+ uint16_t liodnOffset; -+ uint16_t liodnBase; -+ t_FmExtPools extBufPools; -+ e_FmDmaSwapOption dmaSwapData; -+ e_FmDmaCacheOption dmaIntContextCacheAttr; -+ e_FmDmaCacheOption dmaHeaderCacheAttr; -+ e_FmDmaCacheOption dmaScatterGatherCacheAttr; -+ bool dmaReadOptimize; -+ bool dmaWriteOptimize; -+ uint32_t txFifoMinFillLevel; -+ uint32_t txFifoLowComfLevel; -+ uint32_t rxFifoPriElevationLevel; -+ uint32_t rxFifoThreshold; -+ t_FmSpBufMargins bufMargins; -+ t_FmSpIntContextDataCopy intContext; -+ bool syncReq; -+ e_FmPortColor color; -+ fmPortFrameErrSelect_t errorsToDiscard; -+ fmPortFrameErrSelect_t errorsToEnq; -+ bool forwardReuseIntContext; -+ t_FmBufferPrefixContent bufferPrefixContent; -+ t_FmBackupBmPools *p_BackupBmPools; -+ bool dontReleaseBuf; -+ bool setNumOfTasks; -+ bool setNumOfOpenDmas; -+ bool setSizeOfFifo; -+#if (DPAA_VERSION >= 11) -+ bool noScatherGather; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+#ifdef FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 -+ bool bcbWorkaround; -+#endif /* FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 */ -+} t_FmPortDriverParam; -+ -+ -+typedef struct t_FmPortRxPoolsParams -+{ -+ uint8_t numOfPools; -+ uint16_t secondLargestBufSize; -+ uint16_t largestBufSize; -+} t_FmPortRxPoolsParams; -+ -+typedef struct t_FmPortDsarVars { -+ t_Handle *autoResOffsets; -+ t_FmPortDsarTablesSizes *autoResMaxSizes; -+ uint32_t fmbm_tcfg; -+ uint32_t fmbm_tcmne; -+ uint32_t fmbm_rfne; -+ uint32_t fmbm_rfpne; -+ uint32_t fmbm_rcfg; -+ bool dsarEnabledParser; -+} t_FmPortDsarVars; -+typedef struct { -+ struct fman_port port; -+ t_Handle h_Fm; -+ t_Handle h_FmPcd; -+ t_Handle h_FmMuram; -+ t_FmRevisionInfo fmRevInfo; -+ uint8_t portId; -+ e_FmPortType portType; -+ int enabled; -+ char name[MODULE_NAME_SIZE]; -+ uint8_t hardwarePortId; -+ uint16_t fmClkFreq; -+ t_FmPortQmiRegs *p_FmPortQmiRegs; -+ u_FmPortBmiRegs *p_FmPortBmiRegs; -+ t_FmPortPrsRegs *p_FmPortPrsRegs; -+ fmPcdEngines_t pcdEngines; -+ uint32_t savedBmiNia; -+ uint8_t netEnvId; -+ uint32_t optArray[FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)]; -+ uint32_t lcvs[FM_PCD_PRS_NUM_OF_HDRS]; -+ uint8_t privateInfo; -+ uint32_t schemesPerPortVector; -+ bool useClsPlan; -+ uint8_t clsPlanGrpId; -+ t_Handle ccTreeId; -+ t_Handle completeArg; -+ void (*f_Complete)(t_Handle arg); -+ t_FmSpBufferOffsets bufferOffsets; -+ /* Independent-Mode parameters support */ -+ bool imEn; -+ t_FmMacIm im; -+ volatile bool lock; -+ t_Handle h_Spinlock; -+ t_FmPortExceptionCallback *f_Exception; -+ t_Handle h_App; -+ uint8_t internalBufferOffset; -+ uint8_t fmanCtrlEventId; -+ uint32_t exceptions; -+ bool polling; -+ t_FmExtPools extBufPools; -+ uint32_t requiredAction; -+ uint32_t savedQmiPnen; -+ uint32_t savedBmiFene; -+ uint32_t savedBmiFpne; -+ uint32_t savedBmiCmne; -+ uint32_t savedBmiOfp; -+ uint32_t savedNonRxQmiRegsPndn; -+ uint32_t origNonRxQmiRegsPndn; -+ int savedPrsStartOffset; -+ bool includeInPrsStatistics; -+ uint16_t maxFrameLength; -+ t_FmFmanCtrl orFmanCtrl; -+ t_FmPortRsrc openDmas; -+ t_FmPortRsrc tasks; -+ t_FmPortRsrc fifoBufs; -+ t_FmPortRxPoolsParams rxPoolsParams; -+// bool explicitUserSizeOfFifo; -+ t_Handle h_IpReassemblyManip; -+ t_Handle h_CapwapReassemblyManip; -+ t_Handle h_ReassemblyTree; -+ uint64_t fmMuramPhysBaseAddr; -+#if (DPAA_VERSION >= 11) -+ bool vspe; -+ uint8_t dfltRelativeId; -+ e_FmPortGprFuncType gprFunc; -+ t_FmPcdCtrlParamsPage *p_ParamsPage; -+#endif /* (DPAA_VERSION >= 11) */ -+ t_FmPortDsarVars deepSleepVars; -+ t_FmPortDriverParam *p_FmPortDriverParam; -+} t_FmPort; -+ -+ -+void FmPortConfigIM (t_FmPort *p_FmPort, t_FmPortParams *p_FmPortParams); -+t_Error FmPortImCheckInitParameters(t_FmPort *p_FmPort); -+ -+t_Error FmPortImInit(t_FmPort *p_FmPort); -+void FmPortImFree(t_FmPort *p_FmPort); -+ -+t_Error FmPortImEnable (t_FmPort *p_FmPort); -+t_Error FmPortImDisable (t_FmPort *p_FmPort); -+t_Error FmPortImRx (t_FmPort *p_FmPort); -+ -+void FmPortSetMacsecLcv(t_Handle h_FmPort); -+void FmPortSetMacsecCmd(t_Handle h_FmPort, uint8_t dfltSci); -+ -+ -+t_Error FM_PORT_SetNumOfOpenDmas(t_Handle h_FmPort, t_FmPortRsrc *p_NumOfOpenDmas); -+t_Error FM_PORT_SetNumOfTasks(t_Handle h_FmPort, t_FmPortRsrc *p_NumOfTasks); -+t_Error FM_PORT_SetSizeOfFifo(t_Handle h_FmPort, t_FmPortRsrc *p_SizeOfFifo); -+ -+static __inline__ uint8_t * BdBufferGet (t_PhysToVirt *f_PhysToVirt, t_FmImBd *p_Bd) -+{ -+ uint64_t physAddr = (uint64_t)((uint64_t)GET_UINT8(p_Bd->buff.high) << 32); -+ physAddr |= GET_UINT32(p_Bd->buff.low); -+ -+ return (uint8_t *)f_PhysToVirt((physAddress_t)(physAddr)); -+} -+ -+static __inline__ void SET_ADDR(volatile t_FmPhysAddr *fmPhysAddr, uint64_t value) -+{ -+ WRITE_UINT8(fmPhysAddr->high,(uint8_t)((value & 0x000000ff00000000LL) >> 32)); -+ WRITE_UINT32(fmPhysAddr->low,(uint32_t)value); -+} -+ -+static __inline__ void BdBufferSet(t_VirtToPhys *f_VirtToPhys, t_FmImBd *p_Bd, uint8_t *p_Buffer) -+{ -+ uint64_t physAddr = (uint64_t)(f_VirtToPhys(p_Buffer)); -+ SET_ADDR(&p_Bd->buff, physAddr); -+} -+ -+static __inline__ uint16_t GetNextBdId(t_FmPort *p_FmPort, uint16_t id) -+{ -+ if (id < p_FmPort->im.bdRingSize-1) -+ return (uint16_t)(id+1); -+ else -+ return 0; -+} -+ -+void FM_PORT_Dsar_DumpRegs(void); -+ -+ -+#endif /* __FM_PORT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port_dsar.h -@@ -0,0 +1,494 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ @File fm_port_dsar.h -+ -+ @Description Deep Sleep Auto Response project - common module header file. -+ -+ Author - Eyal Harari -+ -+ @Cautions See the FMan Controller spec and design document for more information. -+*//***************************************************************************/ -+ -+#ifndef __FM_PORT_DSAR_H_ -+#define __FM_PORT_DSAR_H_ -+ -+#define DSAR_GETSER_MASK 0xFF0000FF -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response VLAN-IPv4 Binding Table (for ARP/ICMPv4) -+ Refer to the FMan Controller spec for more details. -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ uint32_t ipv4Addr; /*!< 32 bit IPv4 Address. */ -+ uint16_t vlanId; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */ -+ /*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */ -+ uint16_t reserved; -+} _PackedType t_DsarArpBindingEntry; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response Address Resolution Protocol Statistics Descriptor -+ Refer to the FMan Controller spec for more details. -+ 0x00 INVAL_CNT Invalid ARP IPv4-Ethernet counter -+ 0x04 ECHO_CNT Echo counter -+ 0x08 CD_CNT Conflict Detection counter -+ 0x0C AR_CNT Auto-Response counter -+ 0x10 RATM_CNT Replies Addressed To Me counter -+ 0x14 UKOP_CNT Unknown Operation counter -+ 0x18 NMTP_CNT Not my TPA counter -+ 0x1C NMVLAN_CNT Not My VLAN counter -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ uint32_t invalCnt; /**< Invalid ARP IPv4-Ethernet counter. */ -+ uint32_t echoCnt; /**< Echo counter. */ -+ uint32_t cdCnt; /**< Conflict Detection counter. */ -+ uint32_t arCnt; /**< Auto-Response counter. */ -+ uint32_t ratmCnt; /**< Replies Addressed To Me counter. */ -+ uint32_t ukopCnt; /**< Unknown Operation counter. */ -+ uint32_t nmtpCnt; /**< Not my TPA counter. */ -+ uint32_t nmVlanCnt; /**< Not My VLAN counter */ -+} _PackedType t_DsarArpStatistics; -+ -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response Address Resolution Protocol Descriptor -+ 0x0 0-15 Control bits [0-15]. Bit 15 = CDEN. -+ 0x2 0-15 NumOfBindings Number of entries in the binding list. -+ 0x4 0-15 BindingsPointer Bindings Pointer. This points to an IPv4-MAC Addresses Bindings list. -+ 0x6 0-15 -+ 0x8 0-15 StatisticsPointer Statistics Pointer. This field points to the ARP Descriptors statistics data structure. -+ 0xA 0-15 -+ 0xC 0-15 Reserved Reserved. Must be cleared. -+ 0xE 015 -+ -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ uint16_t control; /** Control bits [0-15]. Bit 15 = CDEN */ -+ uint16_t numOfBindings; /**< Number of VLAN-IPv4 */ -+ uint32_t p_Bindings; /**< VLAN-IPv4 Bindings table pointer. */ -+ uint32_t p_Statistics; /**< Statistics Data Structure pointer. */ -+ uint32_t reserved1; /**< Reserved. */ -+} _PackedType t_DsarArpDescriptor; -+ -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response VLAN-IPv4 Binding Table (for ARP/ICMPv4) -+ Refer to the FMan Controller spec for more details. -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ uint32_t ipv4Addr; /*!< 32 bit IPv4 Address. */ -+ uint16_t vlanId; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */ -+ /*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */ -+ uint16_t reserved; -+} _PackedType t_DsarIcmpV4BindingEntry; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response ICMPv4 Statistics Descriptor -+ Refer to the FMan Controller spec for more details. -+ 0x00 INVAL_CNT Invalid ICMPv4 header counter -+ 0x04 NMVLAN_CNT Not My VLAN counter -+ 0x08 NMIP_CNT Not My IP counter -+ 0x0C AR_CNT Auto-Response counter -+ 0x10 CSERR_CNT Checksum Error counter -+ 0x14 Reserved Reserved -+ 0x18 Reserved Reserved -+ 0x1C Reserved Reserved -+ -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ uint32_t invalCnt; /**< Invalid ICMPv4 Echo counter. */ -+ uint32_t nmVlanCnt; /**< Not My VLAN counter */ -+ uint32_t nmIpCnt; /**< Not My IP counter */ -+ uint32_t arCnt; /**< Auto-Response counter */ -+ uint32_t cserrCnt; /**< Checksum Error counter */ -+ uint32_t reserved0; /**< Reserved */ -+ uint32_t reserved1; /**< Reserved */ -+ uint32_t reserved2; /**< Reserved */ -+} _PackedType t_DsarIcmpV4Statistics; -+ -+ -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response ICMPv4 Descriptor -+ 0x0 0-15 Control bits [0-15] -+ 0x2 0-15 NumOfBindings Number of entries in the binding list. -+ 0x4 0-15 BindingsPointer Bindings Pointer. This points to an VLAN-IPv4 Addresses Bindings list. -+ 0x6 0-15 -+ 0x8 0-15 StatisticsPointer Statistics Pointer. This field points to the ICMPv4 statistics data structure. -+ 0xA 0-15 -+ 0xC 0-15 Reserved Reserved. Must be cleared. -+ 0xE 015 -+ -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ uint16_t control; /** Control bits [0-15]. */ -+ uint16_t numOfBindings; /**< Number of VLAN-IPv4 */ -+ uint32_t p_Bindings; /**< VLAN-IPv4 Bindings table pointer. */ -+ uint32_t p_Statistics; /**< Statistics Data Structure pointer. */ -+ uint32_t reserved1; /**< Reserved. */ -+} _PackedType t_DsarIcmpV4Descriptor; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response VLAN-IPv4 Binding Table (for ARP/ICMPv4) -+ The 4 left-most bits (15:12) of the VlanId parameter are control flags. -+ Flags[3:1] (VlanId[15:13]): Reserved, should be cleared. -+ Flags[0] (VlanId[12]): Temporary address. -+ ? 0 - Assigned IP address. -+ ? 1- Temporary (tentative) IP address. -+ Refer to the FMan Controller spec for more details. -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ uint32_t ipv6Addr[4]; /*!< 3 * 32 bit IPv4 Address. */ -+ uint16_t resFlags:4; /*!< reserved flags. should be cleared */ -+ uint16_t vlanId:12; /*!< 12 bits VLAN ID. */ -+ /*!< This field should be 0x000 for an entry with no VLAN tag or a null VLAN ID. */ -+ uint16_t reserved; -+} _PackedType t_DsarIcmpV6BindingEntry; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response ICMPv4 Statistics Descriptor -+ Refer to the FMan Controller spec for more details. -+ 0x00 INVAL_CNT Invalid ICMPv4 header counter -+ 0x04 NMVLAN_CNT Not My VLAN counter -+ 0x08 NMIP_CNT Not My IP counter -+ 0x0C AR_CNT Auto-Response counter -+ 0x10 CSERR_CNT Checksum Error counter -+ 0x14 MCAST_CNT Multicast counter -+ 0x18 Reserved Reserved -+ 0x1C Reserved Reserved -+ -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ uint32_t invalCnt; /**< Invalid ICMPv4 Echo counter. */ -+ uint32_t nmVlanCnt; /**< Not My VLAN counter */ -+ uint32_t nmIpCnt; /**< Not My IP counter */ -+ uint32_t arCnt; /**< Auto-Response counter */ -+ uint32_t reserved1; /**< Reserved */ -+ uint32_t reserved2; /**< Reserved */ -+ uint32_t reserved3; /**< Reserved */ -+ uint32_t reserved4; /**< Reserved */ -+} _PackedType t_DsarIcmpV6Statistics; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response Neighbor Discovery Statistics Descriptor -+ 0x00 INVAL_CNT Invalid Neighbor Discovery message counter -+ 0x04 NMVLAN_CNT Not My VLAN counter -+ 0x08 NMIP_CNT Not My IP counter -+ 0x0C AR_CNT Auto-Response counter -+ 0x10 CSERR_CNT Checksum Error counter -+ 0x14 USADVERT_CNT Unsolicited Neighbor Advertisements counter -+ 0x18 NMMCAST_CNT Not My Multicast group counter -+ 0x1C NSLLA_CNT No Source Link-Layer Address counter. Indicates that there was a match on a Target -+ Address of a packet that its source IP address is a unicast address, but the ICMPv6 -+ Source Link-layer Address option is omitted -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ uint32_t invalCnt; /**< Invalid ICMPv4 Echo counter. */ -+ uint32_t nmVlanCnt; /**< Not My VLAN counter */ -+ uint32_t nmIpCnt; /**< Not My IP counter */ -+ uint32_t arCnt; /**< Auto-Response counter */ -+ uint32_t reserved1; /**< Reserved */ -+ uint32_t usadvertCnt; /**< Unsolicited Neighbor Advertisements counter */ -+ uint32_t nmmcastCnt; /**< Not My Multicast group counter */ -+ uint32_t nsllaCnt; /**< No Source Link-Layer Address counter */ -+} _PackedType t_NdStatistics; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response ICMPv6 Descriptor -+ 0x0 0-15 Control bits [0-15] -+ 0x2 0-15 NumOfBindings Number of entries in the binding list. -+ 0x4 0-15 BindingsPointer Bindings Pointer. This points to an VLAN-IPv4 Addresses Bindings list. -+ 0x6 0-15 -+ 0x8 0-15 StatisticsPointer Statistics Pointer. This field points to the ICMPv4 statistics data structure. -+ 0xA 0-15 -+ 0xC 0-15 Reserved Reserved. Must be cleared. -+ 0xE 015 -+ -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ uint16_t control; /** Control bits [0-15]. */ -+ uint16_t numOfBindings; /**< Number of VLAN-IPv6 */ -+ uint32_t p_Bindings; /**< VLAN-IPv4 Bindings table pointer. */ -+ uint32_t p_Statistics; /**< Statistics Data Structure pointer. */ -+ uint32_t reserved1; /**< Reserved. */ -+} _PackedType t_DsarIcmpV6Descriptor; -+ -+ -+/**************************************************************************//** -+ @Description Internet Control Message Protocol (ICMPv6) Echo message header -+ The fields names are taken from RFC 4443. -+*//***************************************************************************/ -+/* 0 1 2 3 */ -+/* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 */ -+/* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -+/* | Type | Code | Checksum | */ -+/* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -+/* | Identifier | Sequence Number | */ -+/* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -+/* | Data ... */ -+/* +-+-+-+-+- */ -+typedef _Packed struct -+{ -+ uint8_t type; -+ uint8_t code; -+ uint16_t checksum; -+ uint16_t identifier; -+ uint16_t sequenceNumber; -+} _PackedType t_IcmpV6EchoHdr; -+ -+/**************************************************************************//** -+ @Description Internet Control Message Protocol (ICMPv6) -+ Neighbor Solicitation/Advertisement header -+ The fields names are taken from RFC 4861. -+ The R/S/O fields are valid for Neighbor Advertisement only -+*//***************************************************************************/ -+/* 0 1 2 3 -+ * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 -+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ -+ * | Type | Code | Checksum | -+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ -+ * |R|S|O| Reserved | -+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ -+ * | | -+ * + + -+ * | | -+ * + Target Address + -+ * | | -+ * + + -+ * | | -+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ -+ * | Options ... -+ * +-+-+-+-+-+-+-+-+-+-+-+- -+ * -+ * Options Format: -+ * 0 1 2 3 -+ * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 -+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ -+ * | Type | Length | Link-Layer Address ... | -+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ -+ * | Link-Layer Address | -+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ -+*/ -+typedef _Packed struct -+{ -+ uint8_t type; -+ uint8_t code; -+ uint16_t checksum; -+ uint32_t router:1; -+ uint32_t solicited:1; -+ uint32_t override:1; -+ uint32_t reserved:29; -+ uint32_t targetAddr[4]; -+ uint8_t optionType; -+ uint8_t optionLength; -+ uint8_t linkLayerAddr[6]; -+} _PackedType t_IcmpV6NdHdr; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response ICMPv6 Descriptor -+ 0x0 0-15 Control bits [0-15] -+ 0x2 0-15 NumOfBindings Number of entries in the binding list. -+ 0x4 0-15 BindingsPointer Bindings Pointer. This points to an VLAN-IPv4 Addresses Bindings list. -+ 0x6 0-15 -+ 0x8 0-15 StatisticsPointer Statistics Pointer. This field points to the ICMPv4 statistics data structure. -+ 0xA 0-15 -+ 0xC 0-15 Reserved Reserved. Must be cleared. -+ 0xE 015 -+ -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ uint16_t control; /** Control bits [0-15]. */ -+ uint16_t numOfBindings; /**< Number of VLAN-IPv6 */ -+ uint32_t p_Bindings; /**< VLAN-IPv4 Bindings table pointer. */ -+ uint32_t p_Statistics; /**< Statistics Data Structure pointer. */ -+ uint32_t solicitedAddr; /**< Solicited Node Multicast Group Address */ -+} _PackedType t_DsarNdDescriptor; -+ -+/**************************************************************************//** -+@Description Deep Sleep Auto Response SNMP OIDs table entry -+ -+*//***************************************************************************/ -+typedef struct { -+ uint16_t oidSize; /**< Size in octets of the OID. */ -+ uint16_t resSize; /**< Size in octets of the value that is attached to the OID. */ -+ uint32_t p_Oid; /**< Pointer to the OID. OID is encoded in BER but type and length are excluded. */ -+ uint32_t resValOrPtr; /**< Value (for up to 4 octets) or pointer to the Value. Encoded in BER. */ -+ uint32_t reserved; -+} t_OidsTblEntry; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response SNMP IPv4 Addresses Table Entry -+ Refer to the FMan Controller spec for more details. -+*//***************************************************************************/ -+typedef struct -+{ -+ uint32_t ipv4Addr; /*!< 32 bit IPv4 Address. */ -+ uint16_t vlanId; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */ -+ /*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */ -+ uint16_t reserved; -+} t_DsarSnmpIpv4AddrTblEntry; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response SNMP IPv6 Addresses Table Entry -+ Refer to the FMan Controller spec for more details. -+*//***************************************************************************/ -+#pragma pack(push,1) -+typedef struct -+{ -+ uint32_t ipv6Addr[4]; /*!< 4 * 32 bit IPv6 Address. */ -+ uint16_t vlanId; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */ -+ /*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */ -+ uint16_t reserved; -+} t_DsarSnmpIpv6AddrTblEntry; -+#pragma pack(pop) -+ -+/**************************************************************************//** -+@Description Deep Sleep Auto Response SNMP statistics table -+ -+*//***************************************************************************/ -+typedef struct { -+ uint32_t snmpErrCnt; /**< Counts SNMP errors (wrong version, BER encoding, format). */ -+ uint32_t snmpCommunityErrCnt; /**< Counts messages that were dropped due to insufficient permission. */ -+ uint32_t snmpTotalDiscardCnt; /**< Counts any message that was dropped. */ -+ uint32_t snmpGetReqCnt; /**< Counts the number of get-request messages */ -+ uint32_t snmpGetNextReqCnt; /**< Counts the number of get-next-request messages */ -+} t_DsarSnmpStatistics; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response SNMP Descriptor -+ -+*//***************************************************************************/ -+typedef struct -+{ -+ uint16_t control; /**< Control bits [0-15]. */ -+ uint16_t maxSnmpMsgLength; /**< Maximal allowed SNMP message length. */ -+ uint16_t numOfIpv4Addresses; /**< Number of entries in IPv4 addresses table. */ -+ uint16_t numOfIpv6Addresses; /**< Number of entries in IPv6 addresses table. */ -+ uint32_t p_Ipv4AddrTbl; /**< Pointer to IPv4 addresses table. */ -+ uint32_t p_Ipv6AddrTbl; /**< Pointer to IPv6 addresses table. */ -+ uint32_t p_RdOnlyCommunityStr; /**< Pointer to the Read Only Community String. */ -+ uint32_t p_RdWrCommunityStr; /**< Pointer to the Read Write Community String. */ -+ uint32_t p_OidsTbl; /**< Pointer to OIDs table. */ -+ uint32_t oidsTblSize; /**< Number of entries in OIDs table. */ -+ uint32_t p_Statistics; /**< Pointer to SNMP statistics table. */ -+} t_DsarSnmpDescriptor; -+ -+/**************************************************************************//** -+@Description Deep Sleep Auto Response (Common) Statistics -+ -+*//***************************************************************************/ -+typedef _Packed struct { -+ uint32_t dsarDiscarded; -+ uint32_t dsarErrDiscarded; -+ uint32_t dsarFragDiscarded; -+ uint32_t dsarTunnelDiscarded; -+ uint32_t dsarArpDiscarded; -+ uint32_t dsarIpDiscarded; -+ uint32_t dsarTcpDiscarded; -+ uint32_t dsarUdpDiscarded; -+ uint32_t dsarIcmpV6ChecksumErr; /* ICMPv6 Checksum Error counter */ -+ uint32_t dsarIcmpV6OtherType; /* ICMPv6 'Other' type (not Echo or Neighbor Solicitaion/Advertisement counter */ -+ uint32_t dsarIcmpV4OtherType; /* ICMPv4 'Other' type (not Echo) counter */ -+} _PackedType t_ArStatistics; -+ -+ -+/**************************************************************************//** -+@Description Deep Sleep Auto Response TCP/UDP port filter table entry -+ -+*//***************************************************************************/ -+typedef _Packed struct { -+ uint32_t Ports; -+ uint32_t PortsMask; -+} _PackedType t_PortTblEntry; -+ -+ -+ -+/**************************************************************************//** -+@Description Deep Sleep Auto Response Common Parameters Descriptor -+ -+*//***************************************************************************/ -+typedef _Packed struct { -+ uint8_t arTxPort; /* 0x00 0-7 Auto Response Transmit Port number */ -+ uint8_t controlBits; /* 0x00 8-15 Auto Response control bits */ -+ uint16_t res1; /* 0x00 16-31 Reserved */ -+ uint32_t activeHPNIA; /* 0x04 0-31 Active mode Hardware Parser NIA */ -+ uint16_t snmpPort; /* 0x08 0-15 SNMP Port. */ -+ uint8_t macStationAddr[6]; /* 0x08 16-31 and 0x0C 0-31 MAC Station Address */ -+ uint8_t res2; /* 0x10 0-7 Reserved */ -+ uint8_t filterControl; /* 0x10 8-15 Filtering Control Bits. */ -+ uint16_t tcpControlPass; /* 0x10 16-31 TCP control pass flags */ -+ uint8_t ipProtocolTblSize; /* 0x14 0-7 IP Protocol Table Size. */ -+ uint8_t udpPortTblSize; /* 0x14 8-15 UDP Port Table Size. */ -+ uint8_t tcpPortTblSize; /* 0x14 16-23 TCP Port Table Size. */ -+ uint8_t res3; /* 0x14 24-31 Reserved */ -+ uint32_t p_IpProtocolFiltTbl; /* 0x18 0-31 Pointer to IP Protocol Filter Table */ -+ uint32_t p_UdpPortFiltTbl; /* 0x1C 0-31 Pointer to UDP Port Filter Table */ -+ uint32_t p_TcpPortFiltTbl; /* 0x20 0-31 Pointer to TCP Port Filter Table */ -+ uint32_t res4; /* 0x24 Reserved */ -+ uint32_t p_ArpDescriptor; /* 0x28 0-31 ARP Descriptor Pointer. */ -+ uint32_t p_NdDescriptor; /* 0x2C 0-31 Neighbor Discovery Descriptor. */ -+ uint32_t p_IcmpV4Descriptor; /* 0x30 0-31 ICMPv4 Descriptor pointer. */ -+ uint32_t p_IcmpV6Descriptor; /* 0x34 0-31 ICMPv6 Descriptor pointer. */ -+ uint32_t p_SnmpDescriptor; /* 0x38 0-31 SNMP Descriptor pointer. */ -+ uint32_t p_ArStats; /* 0x3C 0-31 Pointer to Auto Response Statistics */ -+} _PackedType t_ArCommonDesc; -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+/* t_ArCommonDesc.filterControl bits */ -+#define IP_PROT_TBL_PASS_MASK 0x08 -+#define UDP_PORT_TBL_PASS_MASK 0x04 -+#define TCP_PORT_TBL_PASS_MASK 0x02 -+ -+/* Offset of TCF flags within TCP packet */ -+#define TCP_FLAGS_OFFSET 12 -+ -+ -+#endif /* __FM_PORT_DSAR_H_ */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port_im.c -@@ -0,0 +1,753 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_port_im.c -+ -+ @Description FM Port Independent-Mode ... -+*//***************************************************************************/ -+#include "std_ext.h" -+#include "string_ext.h" -+#include "error_ext.h" -+#include "memcpy_ext.h" -+#include "fm_muram_ext.h" -+ -+#include "fm_port.h" -+ -+ -+#define TX_CONF_STATUS_UNSENT 0x1 -+ -+ -+typedef enum e_TxConfType -+{ -+ e_TX_CONF_TYPE_CHECK = 0 /**< check if all the buffers were touched by the muxator, no confirmation callback */ -+ ,e_TX_CONF_TYPE_CALLBACK = 1 /**< confirm to user all the available sent buffers */ -+ ,e_TX_CONF_TYPE_FLUSH = 3 /**< confirm all buffers plus the unsent one with an appropriate status */ -+} e_TxConfType; -+ -+ -+static void ImException(t_Handle h_FmPort, uint32_t event) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ ASSERT_COND(((event & (IM_EV_RX | IM_EV_BSY)) && FmIsMaster(p_FmPort->h_Fm)) || -+ !FmIsMaster(p_FmPort->h_Fm)); -+ -+ if (event & IM_EV_RX) -+ FmPortImRx(p_FmPort); -+ if ((event & IM_EV_BSY) && p_FmPort->f_Exception) -+ p_FmPort->f_Exception(p_FmPort->h_App, e_FM_PORT_EXCEPTION_IM_BUSY); -+} -+ -+ -+static t_Error TxConf(t_FmPort *p_FmPort, e_TxConfType confType) -+{ -+ t_Error retVal = E_BUSY; -+ uint32_t bdStatus; -+ uint16_t savedStartBdId, confBdId; -+ -+ ASSERT_COND(p_FmPort); -+ -+ /* -+ if (confType==e_TX_CONF_TYPE_CHECK) -+ return (WfqEntryIsQueueEmpty(p_FmPort->im.h_WfqEntry) ? E_OK : E_BUSY); -+ */ -+ -+ confBdId = savedStartBdId = p_FmPort->im.currBdId; -+ bdStatus = BD_STATUS_AND_LENGTH(BD_GET(confBdId)); -+ -+ /* If R bit is set, we don't enter, or we break. -+ we run till we get to R, or complete the loop */ -+ while ((!(bdStatus & BD_R_E) || (confType == e_TX_CONF_TYPE_FLUSH)) && (retVal != E_OK)) -+ { -+ if (confType & e_TX_CONF_TYPE_CALLBACK) /* if it is confirmation with user callbacks */ -+ BD_STATUS_AND_LENGTH_SET(BD_GET(confBdId), 0); -+ -+ /* case 1: R bit is 0 and Length is set -> confirm! */ -+ if ((confType & e_TX_CONF_TYPE_CALLBACK) && (bdStatus & BD_LENGTH_MASK)) -+ { -+ if (p_FmPort->im.f_TxConf) -+ { -+ if ((confType == e_TX_CONF_TYPE_FLUSH) && (bdStatus & BD_R_E)) -+ p_FmPort->im.f_TxConf(p_FmPort->h_App, -+ BdBufferGet(XX_PhysToVirt, BD_GET(confBdId)), -+ TX_CONF_STATUS_UNSENT, -+ p_FmPort->im.p_BdShadow[confBdId]); -+ else -+ p_FmPort->im.f_TxConf(p_FmPort->h_App, -+ BdBufferGet(XX_PhysToVirt, BD_GET(confBdId)), -+ 0, -+ p_FmPort->im.p_BdShadow[confBdId]); -+ } -+ } -+ /* case 2: R bit is 0 and Length is 0 -> not used yet, nop! */ -+ -+ confBdId = GetNextBdId(p_FmPort, confBdId); -+ if (confBdId == savedStartBdId) -+ retVal = E_OK; -+ bdStatus = BD_STATUS_AND_LENGTH(BD_GET(confBdId)); -+ } -+ -+ return retVal; -+} -+ -+t_Error FmPortImEnable(t_FmPort *p_FmPort) -+{ -+ uint32_t tmpReg = GET_UINT32(p_FmPort->im.p_FmPortImPram->mode); -+ WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, (uint32_t)(tmpReg & ~IM_MODE_GRC_STP)); -+ return E_OK; -+} -+ -+t_Error FmPortImDisable(t_FmPort *p_FmPort) -+{ -+ uint32_t tmpReg = GET_UINT32(p_FmPort->im.p_FmPortImPram->mode); -+ WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, (uint32_t)(tmpReg | IM_MODE_GRC_STP)); -+ return E_OK; -+} -+ -+t_Error FmPortImRx(t_FmPort *p_FmPort) -+{ -+ t_Handle h_CurrUserPriv, h_NewUserPriv; -+ uint32_t bdStatus; -+ volatile uint8_t buffPos; -+ uint16_t length; -+ uint16_t errors; -+ uint8_t *p_CurData, *p_Data; -+ uint32_t flags; -+ -+ ASSERT_COND(p_FmPort); -+ -+ flags = XX_LockIntrSpinlock(p_FmPort->h_Spinlock); -+ if (p_FmPort->lock) -+ { -+ XX_UnlockIntrSpinlock(p_FmPort->h_Spinlock, flags); -+ return E_OK; -+ } -+ p_FmPort->lock = TRUE; -+ XX_UnlockIntrSpinlock(p_FmPort->h_Spinlock, flags); -+ -+ bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId)); -+ -+ while (!(bdStatus & BD_R_E)) /* while there is data in the Rx BD */ -+ { -+ if ((p_Data = p_FmPort->im.rxPool.f_GetBuf(p_FmPort->im.rxPool.h_BufferPool, &h_NewUserPriv)) == NULL) -+ { -+ p_FmPort->lock = FALSE; -+ RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, ("Data buffer")); -+ } -+ -+ if (p_FmPort->im.firstBdOfFrameId == IM_ILEGAL_BD_ID) -+ p_FmPort->im.firstBdOfFrameId = p_FmPort->im.currBdId; -+ -+ p_CurData = BdBufferGet(p_FmPort->im.rxPool.f_PhysToVirt, BD_GET(p_FmPort->im.currBdId)); -+ h_CurrUserPriv = p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId]; -+ length = (uint16_t)((bdStatus & BD_L) ? -+ ((bdStatus & BD_LENGTH_MASK) - p_FmPort->im.rxFrameAccumLength): -+ (bdStatus & BD_LENGTH_MASK)); -+ p_FmPort->im.rxFrameAccumLength += length; -+ -+ /* determine whether buffer is first, last, first and last (single */ -+ /* buffer frame) or middle (not first and not last) */ -+ buffPos = (uint8_t)((p_FmPort->im.currBdId == p_FmPort->im.firstBdOfFrameId) ? -+ ((bdStatus & BD_L) ? SINGLE_BUF : FIRST_BUF) : -+ ((bdStatus & BD_L) ? LAST_BUF : MIDDLE_BUF)); -+ -+ if (bdStatus & BD_L) -+ { -+ p_FmPort->im.rxFrameAccumLength = 0; -+ p_FmPort->im.firstBdOfFrameId = IM_ILEGAL_BD_ID; -+ } -+ -+ BdBufferSet(p_FmPort->im.rxPool.f_VirtToPhys, BD_GET(p_FmPort->im.currBdId), p_Data); -+ -+ BD_STATUS_AND_LENGTH_SET(BD_GET(p_FmPort->im.currBdId), BD_R_E); -+ -+ errors = (uint16_t)((bdStatus & BD_RX_ERRORS) >> 16); -+ p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId] = h_NewUserPriv; -+ -+ p_FmPort->im.currBdId = GetNextBdId(p_FmPort, p_FmPort->im.currBdId); -+ WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.offsetOut, (uint16_t)(p_FmPort->im.currBdId<<4)); -+ /* Pass the buffer if one of the conditions is true: -+ - There are no errors -+ - This is a part of a larger frame ( the application has already received some buffers ) */ -+ if ((buffPos != SINGLE_BUF) || !errors) -+ { -+ if (p_FmPort->im.f_RxStore(p_FmPort->h_App, -+ p_CurData, -+ length, -+ errors, -+ buffPos, -+ h_CurrUserPriv) == e_RX_STORE_RESPONSE_PAUSE) -+ break; -+ } -+ else if (p_FmPort->im.rxPool.f_PutBuf(p_FmPort->im.rxPool.h_BufferPool, -+ p_CurData, -+ h_CurrUserPriv)) -+ { -+ p_FmPort->lock = FALSE; -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Failed freeing data buffer")); -+ } -+ -+ bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId)); -+ } -+ p_FmPort->lock = FALSE; -+ return E_OK; -+} -+ -+void FmPortConfigIM (t_FmPort *p_FmPort, t_FmPortParams *p_FmPortParams) -+{ -+ ASSERT_COND(p_FmPort); -+ -+ SANITY_CHECK_RETURN(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->im.h_FmMuram = p_FmPortParams->specificParams.imRxTxParams.h_FmMuram; -+ p_FmPort->p_FmPortDriverParam->liodnOffset = p_FmPortParams->specificParams.imRxTxParams.liodnOffset; -+ p_FmPort->im.dataMemId = p_FmPortParams->specificParams.imRxTxParams.dataMemId; -+ p_FmPort->im.dataMemAttributes = p_FmPortParams->specificParams.imRxTxParams.dataMemAttributes; -+ -+ p_FmPort->im.fwExtStructsMemId = DEFAULT_PORT_ImfwExtStructsMemId; -+ p_FmPort->im.fwExtStructsMemAttr = DEFAULT_PORT_ImfwExtStructsMemAttr; -+ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) || -+ (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)) -+ { -+ p_FmPort->im.rxPool.h_BufferPool = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.h_BufferPool; -+ p_FmPort->im.rxPool.f_GetBuf = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.f_GetBuf; -+ p_FmPort->im.rxPool.f_PutBuf = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.f_PutBuf; -+ p_FmPort->im.rxPool.bufferSize = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.bufferSize; -+ p_FmPort->im.rxPool.f_PhysToVirt = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.f_PhysToVirt; -+ if (!p_FmPort->im.rxPool.f_PhysToVirt) -+ p_FmPort->im.rxPool.f_PhysToVirt = XX_PhysToVirt; -+ p_FmPort->im.rxPool.f_VirtToPhys = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.f_VirtToPhys; -+ if (!p_FmPort->im.rxPool.f_VirtToPhys) -+ p_FmPort->im.rxPool.f_VirtToPhys = XX_VirtToPhys; -+ p_FmPort->im.f_RxStore = p_FmPortParams->specificParams.imRxTxParams.f_RxStore; -+ -+ p_FmPort->im.mrblr = 0x8000; -+ while (p_FmPort->im.mrblr) -+ { -+ if (p_FmPort->im.rxPool.bufferSize & p_FmPort->im.mrblr) -+ break; -+ p_FmPort->im.mrblr >>= 1; -+ } -+ if (p_FmPort->im.mrblr != p_FmPort->im.rxPool.bufferSize) -+ DBG(WARNING, ("Max-Rx-Buffer-Length set to %d", p_FmPort->im.mrblr)); -+ p_FmPort->im.bdRingSize = DEFAULT_PORT_rxBdRingLength; -+ p_FmPort->exceptions = DEFAULT_PORT_exception; -+ if (FmIsMaster(p_FmPort->h_Fm)) -+ p_FmPort->polling = FALSE; -+ else -+ p_FmPort->polling = TRUE; -+ p_FmPort->fmanCtrlEventId = (uint8_t)NO_IRQ; -+ } -+ else -+ { -+ p_FmPort->im.f_TxConf = p_FmPortParams->specificParams.imRxTxParams.f_TxConf; -+ -+ p_FmPort->im.bdRingSize = DEFAULT_PORT_txBdRingLength; -+ } -+} -+ -+t_Error FmPortImCheckInitParameters(t_FmPort *p_FmPort) -+{ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX) && -+ (p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) && -+ (p_FmPort->portType != e_FM_PORT_TYPE_TX) && -+ (p_FmPort->portType != e_FM_PORT_TYPE_TX_10G)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); -+ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) || -+ (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)) -+ { -+ if (!POWER_OF_2(p_FmPort->im.mrblr)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("max Rx buffer length must be power of 2!!!")); -+ if (p_FmPort->im.mrblr < 256) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("max Rx buffer length must at least 256!!!")); -+ if (p_FmPort->p_FmPortDriverParam->liodnOffset & ~FM_LIODN_OFFSET_MASK) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("liodnOffset is larger than %d", FM_LIODN_OFFSET_MASK+1)); -+ } -+ -+ return E_OK; -+} -+ -+t_Error FmPortImInit(t_FmPort *p_FmPort) -+{ -+ t_FmImBd *p_Bd=NULL; -+ t_Handle h_BufContext; -+ uint64_t tmpPhysBase; -+ uint16_t log2Num; -+ uint8_t *p_Data/*, *p_Tmp*/; -+ int i; -+ t_Error err; -+ uint16_t tmpReg16; -+ uint32_t tmpReg32; -+ -+ ASSERT_COND(p_FmPort); -+ -+ p_FmPort->im.p_FmPortImPram = -+ (t_FmPortImPram *)FM_MURAM_AllocMem(p_FmPort->im.h_FmMuram, sizeof(t_FmPortImPram), IM_PRAM_ALIGN); -+ if (!p_FmPort->im.p_FmPortImPram) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Parameter-RAM!!!")); -+ WRITE_BLOCK(p_FmPort->im.p_FmPortImPram, 0, sizeof(t_FmPortImPram)); -+ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) || -+ (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)) -+ { -+ p_FmPort->im.p_BdRing = -+ (t_FmImBd *)XX_MallocSmart((uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize), -+ p_FmPort->im.fwExtStructsMemId, -+ 4); -+ if (!p_FmPort->im.p_BdRing) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Rx BD ring!!!")); -+ IOMemSet32(p_FmPort->im.p_BdRing, 0, (uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize)); -+ -+ p_FmPort->im.p_BdShadow = (t_Handle *)XX_Malloc((uint32_t)(sizeof(t_Handle)*p_FmPort->im.bdRingSize)); -+ if (!p_FmPort->im.p_BdShadow) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Rx BD shadow!!!")); -+ memset(p_FmPort->im.p_BdShadow, 0, (uint32_t)(sizeof(t_Handle)*p_FmPort->im.bdRingSize)); -+ -+ /* Initialize the Rx-BD ring */ -+ for (i=0; iim.bdRingSize; i++) -+ { -+ p_Bd = BD_GET(i); -+ BD_STATUS_AND_LENGTH_SET (p_Bd, BD_R_E); -+ -+ if ((p_Data = p_FmPort->im.rxPool.f_GetBuf(p_FmPort->im.rxPool.h_BufferPool, &h_BufContext)) == NULL) -+ RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, ("Data buffer")); -+ BdBufferSet(p_FmPort->im.rxPool.f_VirtToPhys, p_Bd, p_Data); -+ p_FmPort->im.p_BdShadow[i] = h_BufContext; -+ } -+ -+ if ((p_FmPort->im.dataMemAttributes & MEMORY_ATTR_CACHEABLE) || -+ (p_FmPort->im.fwExtStructsMemAttr & MEMORY_ATTR_CACHEABLE)) -+ WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, IM_MODE_GBL | IM_MODE_SET_BO(2)); -+ else -+ WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, IM_MODE_SET_BO(2)); -+ -+ WRITE_UINT32(p_FmPort->im.p_FmPortImPram->rxQdPtr, -+ (uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) - -+ p_FmPort->fmMuramPhysBaseAddr + 0x20)); -+ -+ LOG2((uint64_t)p_FmPort->im.mrblr, log2Num); -+ WRITE_UINT16(p_FmPort->im.p_FmPortImPram->mrblr, log2Num); -+ -+ /* Initialize Rx QD */ -+ tmpPhysBase = (uint64_t)(XX_VirtToPhys(p_FmPort->im.p_BdRing)); -+ SET_ADDR(&p_FmPort->im.p_FmPortImPram->rxQd.bdRingBase, tmpPhysBase); -+ WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.bdRingSize, (uint16_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize)); -+ -+ /* Update the IM PRAM address in the BMI */ -+ WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfqid, -+ (uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) - -+ p_FmPort->fmMuramPhysBaseAddr)); -+ if (!p_FmPort->polling || p_FmPort->exceptions) -+ { -+ /* Allocate, configure and register interrupts */ -+ err = FmAllocFmanCtrlEventReg(p_FmPort->h_Fm, &p_FmPort->fmanCtrlEventId); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ ASSERT_COND(!(p_FmPort->fmanCtrlEventId & ~IM_RXQD_FPMEVT_SEL_MASK)); -+ tmpReg16 = (uint16_t)(p_FmPort->fmanCtrlEventId & IM_RXQD_FPMEVT_SEL_MASK); -+ tmpReg32 = 0; -+ -+ if (p_FmPort->exceptions & IM_EV_BSY) -+ { -+ tmpReg16 |= IM_RXQD_BSYINTM; -+ tmpReg32 |= IM_EV_BSY; -+ } -+ if (!p_FmPort->polling) -+ { -+ tmpReg16 |= IM_RXQD_RXFINTM; -+ tmpReg32 |= IM_EV_RX; -+ } -+ WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, tmpReg16); -+ -+ FmRegisterFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, ImException , (t_Handle)p_FmPort); -+ -+ FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, tmpReg32); -+ } -+ else -+ p_FmPort->fmanCtrlEventId = (uint8_t)NO_IRQ; -+ } -+ else -+ { -+ p_FmPort->im.p_BdRing = (t_FmImBd *)XX_MallocSmart((uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize), p_FmPort->im.fwExtStructsMemId, 4); -+ if (!p_FmPort->im.p_BdRing) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Tx BD ring!!!")); -+ IOMemSet32(p_FmPort->im.p_BdRing, 0, (uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize)); -+ -+ p_FmPort->im.p_BdShadow = (t_Handle *)XX_Malloc((uint32_t)(sizeof(t_Handle)*p_FmPort->im.bdRingSize)); -+ if (!p_FmPort->im.p_BdShadow) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Rx BD shadow!!!")); -+ memset(p_FmPort->im.p_BdShadow, 0, (uint32_t)(sizeof(t_Handle)*p_FmPort->im.bdRingSize)); -+ p_FmPort->im.firstBdOfFrameId = IM_ILEGAL_BD_ID; -+ -+ if ((p_FmPort->im.dataMemAttributes & MEMORY_ATTR_CACHEABLE) || -+ (p_FmPort->im.fwExtStructsMemAttr & MEMORY_ATTR_CACHEABLE)) -+ WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, IM_MODE_GBL | IM_MODE_SET_BO(2)); -+ else -+ WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, IM_MODE_SET_BO(2)); -+ -+ WRITE_UINT32(p_FmPort->im.p_FmPortImPram->txQdPtr, -+ (uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) - -+ p_FmPort->fmMuramPhysBaseAddr + 0x40)); -+ -+ /* Initialize Tx QD */ -+ tmpPhysBase = (uint64_t)(XX_VirtToPhys(p_FmPort->im.p_BdRing)); -+ SET_ADDR(&p_FmPort->im.p_FmPortImPram->txQd.bdRingBase, tmpPhysBase); -+ WRITE_UINT16(p_FmPort->im.p_FmPortImPram->txQd.bdRingSize, (uint16_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize)); -+ -+ /* Update the IM PRAM address in the BMI */ -+ WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tcfqid, -+ (uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) - -+ p_FmPort->fmMuramPhysBaseAddr)); -+ } -+ -+ -+ return E_OK; -+} -+ -+void FmPortImFree(t_FmPort *p_FmPort) -+{ -+ uint32_t bdStatus; -+ uint8_t *p_CurData; -+ -+ ASSERT_COND(p_FmPort); -+ ASSERT_COND(p_FmPort->im.p_FmPortImPram); -+ -+ if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) || -+ (p_FmPort->portType == e_FM_PORT_TYPE_RX_10G)) -+ { -+ if (!p_FmPort->polling || p_FmPort->exceptions) -+ { -+ /* Deallocate and unregister interrupts */ -+ FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, 0); -+ -+ FmFreeFmanCtrlEventReg(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId); -+ -+ WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, 0); -+ -+ FmUnregisterFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId); -+ } -+ /* Try first clean what has received */ -+ FmPortImRx(p_FmPort); -+ -+ /* Now, get rid of the the empty buffer! */ -+ bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId)); -+ -+ while (bdStatus & BD_R_E) /* while there is data in the Rx BD */ -+ { -+ p_CurData = BdBufferGet(p_FmPort->im.rxPool.f_PhysToVirt, BD_GET(p_FmPort->im.currBdId)); -+ -+ BdBufferSet(p_FmPort->im.rxPool.f_VirtToPhys, BD_GET(p_FmPort->im.currBdId), NULL); -+ BD_STATUS_AND_LENGTH_SET(BD_GET(p_FmPort->im.currBdId), 0); -+ -+ p_FmPort->im.rxPool.f_PutBuf(p_FmPort->im.rxPool.h_BufferPool, -+ p_CurData, -+ p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId]); -+ -+ p_FmPort->im.currBdId = GetNextBdId(p_FmPort, p_FmPort->im.currBdId); -+ bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId)); -+ } -+ } -+ else -+ TxConf(p_FmPort, e_TX_CONF_TYPE_FLUSH); -+ -+ FM_MURAM_FreeMem(p_FmPort->im.h_FmMuram, p_FmPort->im.p_FmPortImPram); -+ -+ if (p_FmPort->im.p_BdShadow) -+ XX_Free(p_FmPort->im.p_BdShadow); -+ -+ if (p_FmPort->im.p_BdRing) -+ XX_FreeSmart(p_FmPort->im.p_BdRing); -+} -+ -+ -+t_Error FM_PORT_ConfigIMMaxRxBufLength(t_Handle h_FmPort, uint16_t newVal) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->im.mrblr = newVal; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigIMRxBdRingLength(t_Handle h_FmPort, uint16_t newVal) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->im.bdRingSize = newVal; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigIMTxBdRingLength(t_Handle h_FmPort, uint16_t newVal) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->im.bdRingSize = newVal; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigIMFmanCtrlExternalStructsMemory(t_Handle h_FmPort, -+ uint8_t memId, -+ uint32_t memAttributes) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ p_FmPort->im.fwExtStructsMemId = memId; -+ p_FmPort->im.fwExtStructsMemAttr = memAttributes; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ConfigIMPolling(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) && (p_FmPort->portType != e_FM_PORT_TYPE_RX)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, ("Available for Rx ports only")); -+ -+ if (!FmIsMaster(p_FmPort->h_Fm)) -+ RETURN_ERROR(MAJOR, E_INVALID_OPERATION, ("Available on master-partition only;" -+ "in guest-partitions, IM is always in polling!")); -+ -+ p_FmPort->polling = TRUE; -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_SetIMExceptions(t_Handle h_FmPort, e_FmPortExceptions exception, bool enable) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ t_Error err; -+ uint16_t tmpReg16; -+ uint32_t tmpReg32; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ if (exception == e_FM_PORT_EXCEPTION_IM_BUSY) -+ { -+ if (enable) -+ { -+ p_FmPort->exceptions |= IM_EV_BSY; -+ if (p_FmPort->fmanCtrlEventId == (uint8_t)NO_IRQ) -+ { -+ /* Allocate, configure and register interrupts */ -+ err = FmAllocFmanCtrlEventReg(p_FmPort->h_Fm, &p_FmPort->fmanCtrlEventId); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ ASSERT_COND(!(p_FmPort->fmanCtrlEventId & ~IM_RXQD_FPMEVT_SEL_MASK)); -+ -+ FmRegisterFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, ImException, (t_Handle)p_FmPort); -+ tmpReg16 = (uint16_t)((p_FmPort->fmanCtrlEventId & IM_RXQD_FPMEVT_SEL_MASK) | IM_RXQD_BSYINTM); -+ tmpReg32 = IM_EV_BSY; -+ } -+ else -+ { -+ tmpReg16 = (uint16_t)(GET_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen) | IM_RXQD_BSYINTM); -+ tmpReg32 = FmGetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId) | IM_EV_BSY; -+ } -+ -+ WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, tmpReg16); -+ FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, tmpReg32); -+ } -+ else -+ { -+ p_FmPort->exceptions &= ~IM_EV_BSY; -+ if (!p_FmPort->exceptions && p_FmPort->polling) -+ { -+ FmFreeFmanCtrlEventReg(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId); -+ FmUnregisterFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId); -+ FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, 0); -+ WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, 0); -+ p_FmPort->fmanCtrlEventId = (uint8_t)NO_IRQ; -+ } -+ else -+ { -+ tmpReg16 = (uint16_t)(GET_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen) & ~IM_RXQD_BSYINTM); -+ WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, tmpReg16); -+ tmpReg32 = FmGetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId) & ~IM_EV_BSY; -+ FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, tmpReg32); -+ } -+ } -+ } -+ else -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, ("Invalid exception.")); -+ -+ return E_OK; -+} -+ -+t_Error FM_PORT_ImTx( t_Handle h_FmPort, -+ uint8_t *p_Data, -+ uint16_t length, -+ bool lastBuffer, -+ t_Handle h_BufContext) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ uint16_t nextBdId; -+ uint32_t bdStatus, nextBdStatus; -+ bool firstBuffer; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId)); -+ nextBdId = GetNextBdId(p_FmPort, p_FmPort->im.currBdId); -+ nextBdStatus = BD_STATUS_AND_LENGTH(BD_GET(nextBdId)); -+ -+ if (!(bdStatus & BD_R_E) && !(nextBdStatus & BD_R_E)) -+ { -+ /* Confirm the current BD - BD is available */ -+ if ((bdStatus & BD_LENGTH_MASK) && (p_FmPort->im.f_TxConf)) -+ p_FmPort->im.f_TxConf (p_FmPort->h_App, -+ BdBufferGet(XX_PhysToVirt, BD_GET(p_FmPort->im.currBdId)), -+ 0, -+ p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId]); -+ -+ bdStatus = length; -+ -+ /* if this is the first BD of a frame */ -+ if (p_FmPort->im.firstBdOfFrameId == IM_ILEGAL_BD_ID) -+ { -+ firstBuffer = TRUE; -+ p_FmPort->im.txFirstBdStatus = (bdStatus | BD_R_E); -+ -+ if (!lastBuffer) -+ p_FmPort->im.firstBdOfFrameId = p_FmPort->im.currBdId; -+ } -+ else -+ firstBuffer = FALSE; -+ -+ BdBufferSet(XX_VirtToPhys, BD_GET(p_FmPort->im.currBdId), p_Data); -+ p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId] = h_BufContext; -+ -+ /* deal with last */ -+ if (lastBuffer) -+ { -+ /* if single buffer frame */ -+ if (firstBuffer) -+ BD_STATUS_AND_LENGTH_SET(BD_GET(p_FmPort->im.currBdId), p_FmPort->im.txFirstBdStatus | BD_L); -+ else -+ { -+ /* Set the last BD of the frame */ -+ BD_STATUS_AND_LENGTH_SET (BD_GET(p_FmPort->im.currBdId), (bdStatus | BD_R_E | BD_L)); -+ /* Set the first BD of the frame */ -+ BD_STATUS_AND_LENGTH_SET(BD_GET(p_FmPort->im.firstBdOfFrameId), p_FmPort->im.txFirstBdStatus); -+ p_FmPort->im.firstBdOfFrameId = IM_ILEGAL_BD_ID; -+ } -+ WRITE_UINT16(p_FmPort->im.p_FmPortImPram->txQd.offsetIn, (uint16_t)(GetNextBdId(p_FmPort, p_FmPort->im.currBdId)<<4)); -+ } -+ else if (!firstBuffer) /* mid frame buffer */ -+ BD_STATUS_AND_LENGTH_SET (BD_GET(p_FmPort->im.currBdId), bdStatus | BD_R_E); -+ -+ p_FmPort->im.currBdId = GetNextBdId(p_FmPort, p_FmPort->im.currBdId); -+ } -+ else -+ { -+ /* Discard current frame. Return error. */ -+ if (p_FmPort->im.firstBdOfFrameId != IM_ILEGAL_BD_ID) -+ { -+ /* Error: No free BD */ -+ /* Response: Discard current frame. Return error. */ -+ uint16_t cleanBdId = p_FmPort->im.firstBdOfFrameId; -+ -+ ASSERT_COND(p_FmPort->im.firstBdOfFrameId != p_FmPort->im.currBdId); -+ -+ /* Since firstInFrame is not NULL, one buffer at least has already been -+ inserted into the BD ring. Using do-while covers the situation of a -+ frame spanned throughout the whole Tx BD ring (p_CleanBd is incremented -+ prior to testing whether or not it's equal to TxBd). */ -+ do -+ { -+ BD_STATUS_AND_LENGTH_SET(BD_GET(cleanBdId), 0); -+ /* Advance BD pointer */ -+ cleanBdId = GetNextBdId(p_FmPort, cleanBdId); -+ } while (cleanBdId != p_FmPort->im.currBdId); -+ -+ p_FmPort->im.currBdId = cleanBdId; -+ p_FmPort->im.firstBdOfFrameId = IM_ILEGAL_BD_ID; -+ } -+ -+ return ERROR_CODE(E_FULL); -+ } -+ -+ return E_OK; -+} -+ -+void FM_PORT_ImTxConf(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN(p_FmPort->imEn, E_INVALID_STATE); -+ SANITY_CHECK_RETURN(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ TxConf(p_FmPort, e_TX_CONF_TYPE_CALLBACK); -+} -+ -+t_Error FM_PORT_ImRx(t_Handle h_FmPort) -+{ -+ t_FmPort *p_FmPort = (t_FmPort*)h_FmPort; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE); -+ -+ return FmPortImRx(p_FmPort); -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fman_port.c -@@ -0,0 +1,1568 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include "common/general.h" -+ -+#include "fman_common.h" -+#include "fsl_fman_port.h" -+ -+ -+/* problem Eyal: the following should not be here*/ -+#define NIA_FM_CTL_AC_NO_IPACC_PRE_BMI_ENQ_FRAME 0x00000028 -+ -+static uint32_t get_no_pcd_nia_bmi_ac_enc_frame(struct fman_port_cfg *cfg) -+{ -+ if (cfg->errata_A006675) -+ return NIA_ENG_FM_CTL | -+ NIA_FM_CTL_AC_NO_IPACC_PRE_BMI_ENQ_FRAME; -+ else -+ return NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME; -+} -+ -+static int init_bmi_rx(struct fman_port *port, -+ struct fman_port_cfg *cfg, -+ struct fman_port_params *params) -+{ -+ struct fman_port_rx_bmi_regs *regs = &port->bmi_regs->rx; -+ uint32_t tmp; -+ -+ /* Rx Configuration register */ -+ tmp = 0; -+ if (port->im_en) -+ tmp |= BMI_PORT_CFG_IM; -+ else if (cfg->discard_override) -+ tmp |= BMI_PORT_CFG_FDOVR; -+ iowrite32be(tmp, ®s->fmbm_rcfg); -+ -+ /* DMA attributes */ -+ tmp = (uint32_t)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT; -+ if (cfg->dma_ic_stash_on) -+ tmp |= BMI_DMA_ATTR_IC_STASH_ON; -+ if (cfg->dma_header_stash_on) -+ tmp |= BMI_DMA_ATTR_HDR_STASH_ON; -+ if (cfg->dma_sg_stash_on) -+ tmp |= BMI_DMA_ATTR_SG_STASH_ON; -+ if (cfg->dma_write_optimize) -+ tmp |= BMI_DMA_ATTR_WRITE_OPTIMIZE; -+ iowrite32be(tmp, ®s->fmbm_rda); -+ -+ /* Rx FIFO parameters */ -+ tmp = (cfg->rx_pri_elevation / FMAN_PORT_BMI_FIFO_UNITS - 1) << -+ BMI_RX_FIFO_PRI_ELEVATION_SHIFT; -+ tmp |= cfg->rx_fifo_thr / FMAN_PORT_BMI_FIFO_UNITS - 1; -+ iowrite32be(tmp, ®s->fmbm_rfp); -+ -+ if (cfg->excessive_threshold_register) -+ /* always allow access to the extra resources */ -+ iowrite32be(BMI_RX_FIFO_THRESHOLD_ETHE, ®s->fmbm_reth); -+ -+ /* Frame end data */ -+ tmp = (uint32_t)cfg->checksum_bytes_ignore << -+ BMI_RX_FRAME_END_CS_IGNORE_SHIFT; -+ tmp |= (uint32_t)cfg->rx_cut_end_bytes << -+ BMI_RX_FRAME_END_CUT_SHIFT; -+ if (cfg->errata_A006320) -+ tmp &= 0xffe0ffff; -+ iowrite32be(tmp, ®s->fmbm_rfed); -+ -+ /* Internal context parameters */ -+ tmp = ((uint32_t)cfg->ic_ext_offset / FMAN_PORT_IC_OFFSET_UNITS) << -+ BMI_IC_TO_EXT_SHIFT; -+ tmp |= ((uint32_t)cfg->ic_int_offset / FMAN_PORT_IC_OFFSET_UNITS) << -+ BMI_IC_FROM_INT_SHIFT; -+ tmp |= cfg->ic_size / FMAN_PORT_IC_OFFSET_UNITS; -+ iowrite32be(tmp, ®s->fmbm_ricp); -+ -+ /* Internal buffer offset */ -+ tmp = ((uint32_t)cfg->int_buf_start_margin / FMAN_PORT_IC_OFFSET_UNITS) -+ << BMI_INT_BUF_MARG_SHIFT; -+ iowrite32be(tmp, ®s->fmbm_rim); -+ -+ /* External buffer margins */ -+ if (!port->im_en) -+ { -+ tmp = (uint32_t)cfg->ext_buf_start_margin << -+ BMI_EXT_BUF_MARG_START_SHIFT; -+ tmp |= (uint32_t)cfg->ext_buf_end_margin; -+ if (cfg->fmbm_rebm_has_sgd && cfg->no_scatter_gather) -+ tmp |= BMI_SG_DISABLE; -+ iowrite32be(tmp, ®s->fmbm_rebm); -+ } -+ -+ /* Frame attributes */ -+ tmp = BMI_CMD_RX_MR_DEF; -+ if (!port->im_en) -+ { -+ tmp |= BMI_CMD_ATTR_ORDER; -+ tmp |= (uint32_t)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT; -+ if (cfg->sync_req) -+ tmp |= BMI_CMD_ATTR_SYNC; -+ } -+ iowrite32be(tmp, ®s->fmbm_rfca); -+ -+ /* NIA */ -+ if (port->im_en) -+ tmp = NIA_ENG_FM_CTL | NIA_FM_CTL_AC_IND_MODE_RX; -+ else -+ { -+ tmp = (uint32_t)cfg->rx_fd_bits << BMI_NEXT_ENG_FD_BITS_SHIFT; -+ tmp |= get_no_pcd_nia_bmi_ac_enc_frame(cfg); -+ } -+ iowrite32be(tmp, ®s->fmbm_rfne); -+ -+ /* Enqueue NIA */ -+ iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, ®s->fmbm_rfene); -+ -+ /* Default/error queues */ -+ if (!port->im_en) -+ { -+ iowrite32be((params->dflt_fqid & 0x00FFFFFF), ®s->fmbm_rfqid); -+ iowrite32be((params->err_fqid & 0x00FFFFFF), ®s->fmbm_refqid); -+ } -+ -+ /* Discard/error masks */ -+ iowrite32be(params->discard_mask, ®s->fmbm_rfsdm); -+ iowrite32be(params->err_mask, ®s->fmbm_rfsem); -+ -+ /* Statistics counters */ -+ tmp = 0; -+ if (cfg->stats_counters_enable) -+ tmp = BMI_COUNTERS_EN; -+ iowrite32be(tmp, ®s->fmbm_rstc); -+ -+ /* Performance counters */ -+ fman_port_set_perf_cnt_params(port, &cfg->perf_cnt_params); -+ tmp = 0; -+ if (cfg->perf_counters_enable) -+ tmp = BMI_COUNTERS_EN; -+ iowrite32be(tmp, ®s->fmbm_rpc); -+ -+ return 0; -+} -+ -+static int init_bmi_tx(struct fman_port *port, -+ struct fman_port_cfg *cfg, -+ struct fman_port_params *params) -+{ -+ struct fman_port_tx_bmi_regs *regs = &port->bmi_regs->tx; -+ uint32_t tmp; -+ -+ /* Tx Configuration register */ -+ tmp = 0; -+ if (port->im_en) -+ tmp |= BMI_PORT_CFG_IM; -+ iowrite32be(tmp, ®s->fmbm_tcfg); -+ -+ /* DMA attributes */ -+ tmp = (uint32_t)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT; -+ if (cfg->dma_ic_stash_on) -+ tmp |= BMI_DMA_ATTR_IC_STASH_ON; -+ if (cfg->dma_header_stash_on) -+ tmp |= BMI_DMA_ATTR_HDR_STASH_ON; -+ if (cfg->dma_sg_stash_on) -+ tmp |= BMI_DMA_ATTR_SG_STASH_ON; -+ iowrite32be(tmp, ®s->fmbm_tda); -+ -+ /* Tx FIFO parameters */ -+ tmp = (cfg->tx_fifo_min_level / FMAN_PORT_BMI_FIFO_UNITS) << -+ BMI_TX_FIFO_MIN_FILL_SHIFT; -+ tmp |= ((uint32_t)cfg->tx_fifo_deq_pipeline_depth - 1) << -+ BMI_FIFO_PIPELINE_DEPTH_SHIFT; -+ tmp |= (uint32_t)(cfg->tx_fifo_low_comf_level / -+ FMAN_PORT_BMI_FIFO_UNITS - 1); -+ iowrite32be(tmp, ®s->fmbm_tfp); -+ -+ /* Frame end data */ -+ tmp = (uint32_t)cfg->checksum_bytes_ignore << -+ BMI_FRAME_END_CS_IGNORE_SHIFT; -+ iowrite32be(tmp, ®s->fmbm_tfed); -+ -+ /* Internal context parameters */ -+ if (!port->im_en) -+ { -+ tmp = ((uint32_t)cfg->ic_ext_offset / FMAN_PORT_IC_OFFSET_UNITS) << -+ BMI_IC_TO_EXT_SHIFT; -+ tmp |= ((uint32_t)cfg->ic_int_offset / FMAN_PORT_IC_OFFSET_UNITS) << -+ BMI_IC_FROM_INT_SHIFT; -+ tmp |= cfg->ic_size / FMAN_PORT_IC_OFFSET_UNITS; -+ iowrite32be(tmp, ®s->fmbm_ticp); -+ } -+ /* Frame attributes */ -+ tmp = BMI_CMD_TX_MR_DEF; -+ if (port->im_en) -+ tmp |= BMI_CMD_MR_DEAS; -+ else -+ { -+ tmp |= BMI_CMD_ATTR_ORDER; -+ tmp |= (uint32_t)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT; -+ } -+ iowrite32be(tmp, ®s->fmbm_tfca); -+ -+ /* Dequeue NIA + enqueue NIA */ -+ if (port->im_en) -+ { -+ iowrite32be(NIA_ENG_FM_CTL | NIA_FM_CTL_AC_IND_MODE_TX, ®s->fmbm_tfdne); -+ iowrite32be(NIA_ENG_FM_CTL | NIA_FM_CTL_AC_IND_MODE_TX, ®s->fmbm_tfene); -+ } -+ else -+ { -+ iowrite32be(NIA_ENG_QMI_DEQ, ®s->fmbm_tfdne); -+ iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, ®s->fmbm_tfene); -+ if (cfg->fmbm_tfne_has_features) -+ iowrite32be(!params->dflt_fqid ? -+ BMI_EBD_EN | NIA_BMI_AC_FETCH_ALL_FRAME : -+ NIA_BMI_AC_FETCH_ALL_FRAME, ®s->fmbm_tfne); -+ if (!params->dflt_fqid && params->dont_release_buf) -+ { -+ iowrite32be(0x00FFFFFF, ®s->fmbm_tcfqid); -+ iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE, ®s->fmbm_tfene); -+ if (cfg->fmbm_tfne_has_features) -+ iowrite32be(ioread32be(®s->fmbm_tfne) & ~BMI_EBD_EN, ®s->fmbm_tfne); -+ } -+ } -+ -+ /* Confirmation/error queues */ -+ if (!port->im_en) -+ { -+ if (params->dflt_fqid || !params->dont_release_buf) -+ iowrite32be(params->dflt_fqid & 0x00FFFFFF, ®s->fmbm_tcfqid); -+ iowrite32be((params->err_fqid & 0x00FFFFFF), ®s->fmbm_tefqid); -+ } -+ /* Statistics counters */ -+ tmp = 0; -+ if (cfg->stats_counters_enable) -+ tmp = BMI_COUNTERS_EN; -+ iowrite32be(tmp, ®s->fmbm_tstc); -+ -+ /* Performance counters */ -+ fman_port_set_perf_cnt_params(port, &cfg->perf_cnt_params); -+ tmp = 0; -+ if (cfg->perf_counters_enable) -+ tmp = BMI_COUNTERS_EN; -+ iowrite32be(tmp, ®s->fmbm_tpc); -+ -+ return 0; -+} -+ -+static int init_bmi_oh(struct fman_port *port, -+ struct fman_port_cfg *cfg, -+ struct fman_port_params *params) -+{ -+ struct fman_port_oh_bmi_regs *regs = &port->bmi_regs->oh; -+ uint32_t tmp; -+ -+ /* OP Configuration register */ -+ tmp = 0; -+ if (cfg->discard_override) -+ tmp |= BMI_PORT_CFG_FDOVR; -+ iowrite32be(tmp, ®s->fmbm_ocfg); -+ -+ /* DMA attributes */ -+ tmp = (uint32_t)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT; -+ if (cfg->dma_ic_stash_on) -+ tmp |= BMI_DMA_ATTR_IC_STASH_ON; -+ if (cfg->dma_header_stash_on) -+ tmp |= BMI_DMA_ATTR_HDR_STASH_ON; -+ if (cfg->dma_sg_stash_on) -+ tmp |= BMI_DMA_ATTR_SG_STASH_ON; -+ if (cfg->dma_write_optimize) -+ tmp |= BMI_DMA_ATTR_WRITE_OPTIMIZE; -+ iowrite32be(tmp, ®s->fmbm_oda); -+ -+ /* Tx FIFO parameters */ -+ tmp = ((uint32_t)cfg->tx_fifo_deq_pipeline_depth - 1) << -+ BMI_FIFO_PIPELINE_DEPTH_SHIFT; -+ iowrite32be(tmp, ®s->fmbm_ofp); -+ -+ /* Internal context parameters */ -+ tmp = ((uint32_t)cfg->ic_ext_offset / FMAN_PORT_IC_OFFSET_UNITS) << -+ BMI_IC_TO_EXT_SHIFT; -+ tmp |= ((uint32_t)cfg->ic_int_offset / FMAN_PORT_IC_OFFSET_UNITS) << -+ BMI_IC_FROM_INT_SHIFT; -+ tmp |= cfg->ic_size / FMAN_PORT_IC_OFFSET_UNITS; -+ iowrite32be(tmp, ®s->fmbm_oicp); -+ -+ /* Frame attributes */ -+ tmp = BMI_CMD_OP_MR_DEF; -+ tmp |= (uint32_t)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT; -+ if (cfg->sync_req) -+ tmp |= BMI_CMD_ATTR_SYNC; -+ if (port->type == E_FMAN_PORT_TYPE_OP) -+ tmp |= BMI_CMD_ATTR_ORDER; -+ iowrite32be(tmp, ®s->fmbm_ofca); -+ -+ /* Internal buffer offset */ -+ tmp = ((uint32_t)cfg->int_buf_start_margin / FMAN_PORT_IC_OFFSET_UNITS) -+ << BMI_INT_BUF_MARG_SHIFT; -+ iowrite32be(tmp, ®s->fmbm_oim); -+ -+ /* Dequeue NIA */ -+ iowrite32be(NIA_ENG_QMI_DEQ, ®s->fmbm_ofdne); -+ -+ /* NIA and Enqueue NIA */ -+ if (port->type == E_FMAN_PORT_TYPE_HC) { -+ iowrite32be(NIA_ENG_FM_CTL | NIA_FM_CTL_AC_HC, -+ ®s->fmbm_ofne); -+ iowrite32be(NIA_ENG_QMI_ENQ, ®s->fmbm_ofene); -+ } else { -+ iowrite32be(get_no_pcd_nia_bmi_ac_enc_frame(cfg), -+ ®s->fmbm_ofne); -+ iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, -+ ®s->fmbm_ofene); -+ } -+ -+ /* Default/error queues */ -+ iowrite32be((params->dflt_fqid & 0x00FFFFFF), ®s->fmbm_ofqid); -+ iowrite32be((params->err_fqid & 0x00FFFFFF), ®s->fmbm_oefqid); -+ -+ /* Discard/error masks */ -+ if (port->type == E_FMAN_PORT_TYPE_OP) { -+ iowrite32be(params->discard_mask, ®s->fmbm_ofsdm); -+ iowrite32be(params->err_mask, ®s->fmbm_ofsem); -+ } -+ -+ /* Statistics counters */ -+ tmp = 0; -+ if (cfg->stats_counters_enable) -+ tmp = BMI_COUNTERS_EN; -+ iowrite32be(tmp, ®s->fmbm_ostc); -+ -+ /* Performance counters */ -+ fman_port_set_perf_cnt_params(port, &cfg->perf_cnt_params); -+ tmp = 0; -+ if (cfg->perf_counters_enable) -+ tmp = BMI_COUNTERS_EN; -+ iowrite32be(tmp, ®s->fmbm_opc); -+ -+ return 0; -+} -+ -+static int init_qmi(struct fman_port *port, -+ struct fman_port_cfg *cfg, -+ struct fman_port_params *params) -+{ -+ struct fman_port_qmi_regs *regs = port->qmi_regs; -+ uint32_t tmp; -+ -+ tmp = 0; -+ if (cfg->queue_counters_enable) -+ tmp |= QMI_PORT_CFG_EN_COUNTERS; -+ iowrite32be(tmp, ®s->fmqm_pnc); -+ -+ /* Rx port configuration */ -+ if ((port->type == E_FMAN_PORT_TYPE_RX) || -+ (port->type == E_FMAN_PORT_TYPE_RX_10G)) { -+ /* Enqueue NIA */ -+ iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_RELEASE, ®s->fmqm_pnen); -+ return 0; -+ } -+ -+ /* Continue with Tx and O/H port configuration */ -+ if ((port->type == E_FMAN_PORT_TYPE_TX) || -+ (port->type == E_FMAN_PORT_TYPE_TX_10G)) { -+ /* Enqueue NIA */ -+ iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE, -+ ®s->fmqm_pnen); -+ /* Dequeue NIA */ -+ iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX, ®s->fmqm_pndn); -+ } else { -+ /* Enqueue NIA */ -+ iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_RELEASE, ®s->fmqm_pnen); -+ /* Dequeue NIA */ -+ iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_FETCH, ®s->fmqm_pndn); -+ } -+ -+ /* Dequeue Configuration register */ -+ tmp = 0; -+ if (cfg->deq_high_pri) -+ tmp |= QMI_DEQ_CFG_PRI; -+ -+ switch (cfg->deq_type) { -+ case E_FMAN_PORT_DEQ_BY_PRI: -+ tmp |= QMI_DEQ_CFG_TYPE1; -+ break; -+ case E_FMAN_PORT_DEQ_ACTIVE_FQ: -+ tmp |= QMI_DEQ_CFG_TYPE2; -+ break; -+ case E_FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS: -+ tmp |= QMI_DEQ_CFG_TYPE3; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (cfg->qmi_deq_options_support) { -+ if ((port->type == E_FMAN_PORT_TYPE_HC) && -+ (cfg->deq_prefetch_opt != E_FMAN_PORT_DEQ_NO_PREFETCH)) -+ return -EINVAL; -+ -+ switch (cfg->deq_prefetch_opt) { -+ case E_FMAN_PORT_DEQ_NO_PREFETCH: -+ break; -+ case E_FMAN_PORT_DEQ_PART_PREFETCH: -+ tmp |= QMI_DEQ_CFG_PREFETCH_PARTIAL; -+ break; -+ case E_FMAN_PORT_DEQ_FULL_PREFETCH: -+ tmp |= QMI_DEQ_CFG_PREFETCH_FULL; -+ break; -+ default: -+ return -EINVAL; -+ } -+ } -+ tmp |= (uint32_t)(params->deq_sp & QMI_DEQ_CFG_SP_MASK) << -+ QMI_DEQ_CFG_SP_SHIFT; -+ tmp |= cfg->deq_byte_cnt; -+ iowrite32be(tmp, ®s->fmqm_pndc); -+ -+ return 0; -+} -+ -+static void get_rx_stats_reg(struct fman_port *port, -+ enum fman_port_stats_counters counter, -+ uint32_t **stats_reg) -+{ -+ struct fman_port_rx_bmi_regs *regs = &port->bmi_regs->rx; -+ -+ switch (counter) { -+ case E_FMAN_PORT_STATS_CNT_FRAME: -+ *stats_reg = ®s->fmbm_rfrc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_DISCARD: -+ *stats_reg = ®s->fmbm_rfdc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_DEALLOC_BUF: -+ *stats_reg = ®s->fmbm_rbdc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_RX_BAD_FRAME: -+ *stats_reg = ®s->fmbm_rfbc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_RX_LARGE_FRAME: -+ *stats_reg = ®s->fmbm_rlfc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_RX_OUT_OF_BUF: -+ *stats_reg = ®s->fmbm_rodc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_FILTERED_FRAME: -+ *stats_reg = ®s->fmbm_rffc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_DMA_ERR: -+ *stats_reg = ®s->fmbm_rfldec; -+ break; -+ default: -+ *stats_reg = NULL; -+ } -+} -+ -+static void get_tx_stats_reg(struct fman_port *port, -+ enum fman_port_stats_counters counter, -+ uint32_t **stats_reg) -+{ -+ struct fman_port_tx_bmi_regs *regs = &port->bmi_regs->tx; -+ -+ switch (counter) { -+ case E_FMAN_PORT_STATS_CNT_FRAME: -+ *stats_reg = ®s->fmbm_tfrc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_DISCARD: -+ *stats_reg = ®s->fmbm_tfdc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_DEALLOC_BUF: -+ *stats_reg = ®s->fmbm_tbdc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_LEN_ERR: -+ *stats_reg = ®s->fmbm_tfledc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_UNSUPPORTED_FORMAT: -+ *stats_reg = ®s->fmbm_tfufdc; -+ break; -+ default: -+ *stats_reg = NULL; -+ } -+} -+ -+static void get_oh_stats_reg(struct fman_port *port, -+ enum fman_port_stats_counters counter, -+ uint32_t **stats_reg) -+{ -+ struct fman_port_oh_bmi_regs *regs = &port->bmi_regs->oh; -+ -+ switch (counter) { -+ case E_FMAN_PORT_STATS_CNT_FRAME: -+ *stats_reg = ®s->fmbm_ofrc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_DISCARD: -+ *stats_reg = ®s->fmbm_ofdc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_DEALLOC_BUF: -+ *stats_reg = ®s->fmbm_obdc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_FILTERED_FRAME: -+ *stats_reg = ®s->fmbm_offc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_DMA_ERR: -+ *stats_reg = ®s->fmbm_ofldec; -+ break; -+ case E_FMAN_PORT_STATS_CNT_LEN_ERR: -+ *stats_reg = ®s->fmbm_ofledc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_UNSUPPORTED_FORMAT: -+ *stats_reg = ®s->fmbm_ofufdc; -+ break; -+ case E_FMAN_PORT_STATS_CNT_WRED_DISCARD: -+ *stats_reg = ®s->fmbm_ofwdc; -+ break; -+ default: -+ *stats_reg = NULL; -+ } -+} -+ -+static void get_rx_perf_reg(struct fman_port *port, -+ enum fman_port_perf_counters counter, -+ uint32_t **perf_reg) -+{ -+ struct fman_port_rx_bmi_regs *regs = &port->bmi_regs->rx; -+ -+ switch (counter) { -+ case E_FMAN_PORT_PERF_CNT_CYCLE: -+ *perf_reg = ®s->fmbm_rccn; -+ break; -+ case E_FMAN_PORT_PERF_CNT_TASK_UTIL: -+ *perf_reg = ®s->fmbm_rtuc; -+ break; -+ case E_FMAN_PORT_PERF_CNT_QUEUE_UTIL: -+ *perf_reg = ®s->fmbm_rrquc; -+ break; -+ case E_FMAN_PORT_PERF_CNT_DMA_UTIL: -+ *perf_reg = ®s->fmbm_rduc; -+ break; -+ case E_FMAN_PORT_PERF_CNT_FIFO_UTIL: -+ *perf_reg = ®s->fmbm_rfuc; -+ break; -+ case E_FMAN_PORT_PERF_CNT_RX_PAUSE: -+ *perf_reg = ®s->fmbm_rpac; -+ break; -+ default: -+ *perf_reg = NULL; -+ } -+} -+ -+static void get_tx_perf_reg(struct fman_port *port, -+ enum fman_port_perf_counters counter, -+ uint32_t **perf_reg) -+{ -+ struct fman_port_tx_bmi_regs *regs = &port->bmi_regs->tx; -+ -+ switch (counter) { -+ case E_FMAN_PORT_PERF_CNT_CYCLE: -+ *perf_reg = ®s->fmbm_tccn; -+ break; -+ case E_FMAN_PORT_PERF_CNT_TASK_UTIL: -+ *perf_reg = ®s->fmbm_ttuc; -+ break; -+ case E_FMAN_PORT_PERF_CNT_QUEUE_UTIL: -+ *perf_reg = ®s->fmbm_ttcquc; -+ break; -+ case E_FMAN_PORT_PERF_CNT_DMA_UTIL: -+ *perf_reg = ®s->fmbm_tduc; -+ break; -+ case E_FMAN_PORT_PERF_CNT_FIFO_UTIL: -+ *perf_reg = ®s->fmbm_tfuc; -+ break; -+ default: -+ *perf_reg = NULL; -+ } -+} -+ -+static void get_oh_perf_reg(struct fman_port *port, -+ enum fman_port_perf_counters counter, -+ uint32_t **perf_reg) -+{ -+ struct fman_port_oh_bmi_regs *regs = &port->bmi_regs->oh; -+ -+ switch (counter) { -+ case E_FMAN_PORT_PERF_CNT_CYCLE: -+ *perf_reg = ®s->fmbm_occn; -+ break; -+ case E_FMAN_PORT_PERF_CNT_TASK_UTIL: -+ *perf_reg = ®s->fmbm_otuc; -+ break; -+ case E_FMAN_PORT_PERF_CNT_DMA_UTIL: -+ *perf_reg = ®s->fmbm_oduc; -+ break; -+ case E_FMAN_PORT_PERF_CNT_FIFO_UTIL: -+ *perf_reg = ®s->fmbm_ofuc; -+ break; -+ default: -+ *perf_reg = NULL; -+ } -+} -+ -+static void get_qmi_counter_reg(struct fman_port *port, -+ enum fman_port_qmi_counters counter, -+ uint32_t **queue_reg) -+{ -+ struct fman_port_qmi_regs *regs = port->qmi_regs; -+ -+ switch (counter) { -+ case E_FMAN_PORT_ENQ_TOTAL: -+ *queue_reg = ®s->fmqm_pnetfc; -+ break; -+ case E_FMAN_PORT_DEQ_TOTAL: -+ if ((port->type == E_FMAN_PORT_TYPE_RX) || -+ (port->type == E_FMAN_PORT_TYPE_RX_10G)) -+ /* Counter not available for Rx ports */ -+ *queue_reg = NULL; -+ else -+ *queue_reg = ®s->fmqm_pndtfc; -+ break; -+ case E_FMAN_PORT_DEQ_FROM_DFLT: -+ if ((port->type == E_FMAN_PORT_TYPE_RX) || -+ (port->type == E_FMAN_PORT_TYPE_RX_10G)) -+ /* Counter not available for Rx ports */ -+ *queue_reg = NULL; -+ else -+ *queue_reg = ®s->fmqm_pndfdc; -+ break; -+ case E_FMAN_PORT_DEQ_CONFIRM: -+ if ((port->type == E_FMAN_PORT_TYPE_RX) || -+ (port->type == E_FMAN_PORT_TYPE_RX_10G)) -+ /* Counter not available for Rx ports */ -+ *queue_reg = NULL; -+ else -+ *queue_reg = ®s->fmqm_pndcc; -+ break; -+ default: -+ *queue_reg = NULL; -+ } -+} -+ -+void fman_port_defconfig(struct fman_port_cfg *cfg, enum fman_port_type type) -+{ -+ cfg->dma_swap_data = E_FMAN_PORT_DMA_NO_SWAP; -+ cfg->dma_ic_stash_on = FALSE; -+ cfg->dma_header_stash_on = FALSE; -+ cfg->dma_sg_stash_on = FALSE; -+ cfg->dma_write_optimize = TRUE; -+ cfg->color = E_FMAN_PORT_COLOR_GREEN; -+ cfg->discard_override = FALSE; -+ cfg->checksum_bytes_ignore = 0; -+ cfg->rx_cut_end_bytes = 4; -+ cfg->rx_pri_elevation = ((0x3FF + 1) * FMAN_PORT_BMI_FIFO_UNITS); -+ cfg->rx_fifo_thr = ((0x3FF + 1) * FMAN_PORT_BMI_FIFO_UNITS); -+ cfg->rx_fd_bits = 0; -+ cfg->ic_ext_offset = 0; -+ cfg->ic_int_offset = 0; -+ cfg->ic_size = 0; -+ cfg->int_buf_start_margin = 0; -+ cfg->ext_buf_start_margin = 0; -+ cfg->ext_buf_end_margin = 0; -+ cfg->tx_fifo_min_level = 0; -+ cfg->tx_fifo_low_comf_level = (5 * KILOBYTE); -+ cfg->stats_counters_enable = TRUE; -+ cfg->perf_counters_enable = TRUE; -+ cfg->deq_type = E_FMAN_PORT_DEQ_BY_PRI; -+ -+ if (type == E_FMAN_PORT_TYPE_HC) { -+ cfg->sync_req = FALSE; -+ cfg->deq_prefetch_opt = E_FMAN_PORT_DEQ_NO_PREFETCH; -+ } else { -+ cfg->sync_req = TRUE; -+ cfg->deq_prefetch_opt = E_FMAN_PORT_DEQ_FULL_PREFETCH; -+ } -+ -+ if (type == E_FMAN_PORT_TYPE_TX_10G) { -+ cfg->tx_fifo_deq_pipeline_depth = 4; -+ cfg->deq_high_pri = TRUE; -+ cfg->deq_byte_cnt = 0x1400; -+ } else { -+ if ((type == E_FMAN_PORT_TYPE_HC) || -+ (type == E_FMAN_PORT_TYPE_OP)) -+ cfg->tx_fifo_deq_pipeline_depth = 2; -+ else -+ cfg->tx_fifo_deq_pipeline_depth = 1; -+ -+ cfg->deq_high_pri = FALSE; -+ cfg->deq_byte_cnt = 0x400; -+ } -+ cfg->no_scatter_gather = DEFAULT_FMAN_SP_NO_SCATTER_GATHER; -+} -+ -+static uint8_t fman_port_find_bpool(struct fman_port *port, uint8_t bpid) -+{ -+ uint32_t *bp_reg, tmp; -+ uint8_t i, id; -+ -+ /* Find the pool */ -+ bp_reg = port->bmi_regs->rx.fmbm_ebmpi; -+ for (i = 0; -+ (i < port->ext_pools_num && (i < FMAN_PORT_MAX_EXT_POOLS_NUM)); -+ i++) { -+ tmp = ioread32be(&bp_reg[i]); -+ id = (uint8_t)((tmp & BMI_EXT_BUF_POOL_ID_MASK) >> -+ BMI_EXT_BUF_POOL_ID_SHIFT); -+ -+ if (id == bpid) -+ break; -+ } -+ -+ return i; -+} -+ -+int fman_port_init(struct fman_port *port, -+ struct fman_port_cfg *cfg, -+ struct fman_port_params *params) -+{ -+ int err; -+ -+ /* Init BMI registers */ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ err = init_bmi_rx(port, cfg, params); -+ break; -+ case E_FMAN_PORT_TYPE_TX: -+ case E_FMAN_PORT_TYPE_TX_10G: -+ err = init_bmi_tx(port, cfg, params); -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ case E_FMAN_PORT_TYPE_HC: -+ err = init_bmi_oh(port, cfg, params); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (err) -+ return err; -+ -+ /* Init QMI registers */ -+ if (!port->im_en) -+ { -+ err = init_qmi(port, cfg, params); -+ return err; -+ } -+ return 0; -+} -+ -+int fman_port_enable(struct fman_port *port) -+{ -+ uint32_t *bmi_cfg_reg, tmp; -+ bool rx_port; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg; -+ rx_port = TRUE; -+ break; -+ case E_FMAN_PORT_TYPE_TX: -+ case E_FMAN_PORT_TYPE_TX_10G: -+ bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg; -+ rx_port = FALSE; -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ case E_FMAN_PORT_TYPE_HC: -+ bmi_cfg_reg = &port->bmi_regs->oh.fmbm_ocfg; -+ rx_port = FALSE; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ /* Enable QMI */ -+ if (!rx_port) { -+ tmp = ioread32be(&port->qmi_regs->fmqm_pnc) | QMI_PORT_CFG_EN; -+ iowrite32be(tmp, &port->qmi_regs->fmqm_pnc); -+ } -+ -+ /* Enable BMI */ -+ tmp = ioread32be(bmi_cfg_reg) | BMI_PORT_CFG_EN; -+ iowrite32be(tmp, bmi_cfg_reg); -+ -+ return 0; -+} -+ -+int fman_port_disable(const struct fman_port *port) -+{ -+ uint32_t *bmi_cfg_reg, *bmi_status_reg, tmp; -+ bool rx_port, failure = FALSE; -+ int count; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg; -+ bmi_status_reg = &port->bmi_regs->rx.fmbm_rst; -+ rx_port = TRUE; -+ break; -+ case E_FMAN_PORT_TYPE_TX: -+ case E_FMAN_PORT_TYPE_TX_10G: -+ bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg; -+ bmi_status_reg = &port->bmi_regs->tx.fmbm_tst; -+ rx_port = FALSE; -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ case E_FMAN_PORT_TYPE_HC: -+ bmi_cfg_reg = &port->bmi_regs->oh.fmbm_ocfg; -+ bmi_status_reg = &port->bmi_regs->oh.fmbm_ost; -+ rx_port = FALSE; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ /* Disable QMI */ -+ if (!rx_port) { -+ tmp = ioread32be(&port->qmi_regs->fmqm_pnc) & ~QMI_PORT_CFG_EN; -+ iowrite32be(tmp, &port->qmi_regs->fmqm_pnc); -+ -+ /* Wait for QMI to finish FD handling */ -+ count = 100; -+ do { -+ udelay(10); -+ tmp = ioread32be(&port->qmi_regs->fmqm_pns); -+ } while ((tmp & QMI_PORT_STATUS_DEQ_FD_BSY) && --count); -+ -+ if (count == 0) -+ { -+ /* Timeout */ -+ failure = TRUE; -+ } -+ } -+ -+ /* Disable BMI */ -+ tmp = ioread32be(bmi_cfg_reg) & ~BMI_PORT_CFG_EN; -+ iowrite32be(tmp, bmi_cfg_reg); -+ -+ /* Wait for graceful stop end */ -+ count = 500; -+ do { -+ udelay(10); -+ tmp = ioread32be(bmi_status_reg); -+ } while ((tmp & BMI_PORT_STATUS_BSY) && --count); -+ -+ if (count == 0) -+ { -+ /* Timeout */ -+ failure = TRUE; -+ } -+ -+ if (failure) -+ return -EBUSY; -+ -+ return 0; -+} -+ -+int fman_port_set_bpools(const struct fman_port *port, -+ const struct fman_port_bpools *bp) -+{ -+ uint32_t tmp, *bp_reg, *bp_depl_reg; -+ uint8_t i, max_bp_num; -+ bool grp_depl_used = FALSE, rx_port; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ max_bp_num = port->ext_pools_num; -+ rx_port = TRUE; -+ bp_reg = port->bmi_regs->rx.fmbm_ebmpi; -+ bp_depl_reg = &port->bmi_regs->rx.fmbm_mpd; -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ if (port->fm_rev_maj != 4) -+ return -EINVAL; -+ max_bp_num = FMAN_PORT_OBS_EXT_POOLS_NUM; -+ rx_port = FALSE; -+ bp_reg = port->bmi_regs->oh.fmbm_oebmpi; -+ bp_depl_reg = &port->bmi_regs->oh.fmbm_ompd; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (rx_port) { -+ /* Check buffers are provided in ascending order */ -+ for (i = 0; -+ (i < (bp->count-1) && (i < FMAN_PORT_MAX_EXT_POOLS_NUM - 1)); -+ i++) { -+ if (bp->bpool[i].size > bp->bpool[i+1].size) -+ return -EINVAL; -+ } -+ } -+ -+ /* Set up external buffers pools */ -+ for (i = 0; i < bp->count; i++) { -+ tmp = BMI_EXT_BUF_POOL_VALID; -+ tmp |= ((uint32_t)bp->bpool[i].bpid << -+ BMI_EXT_BUF_POOL_ID_SHIFT) & BMI_EXT_BUF_POOL_ID_MASK; -+ -+ if (rx_port) { -+ if (bp->counters_enable) -+ tmp |= BMI_EXT_BUF_POOL_EN_COUNTER; -+ -+ if (bp->bpool[i].is_backup) -+ tmp |= BMI_EXT_BUF_POOL_BACKUP; -+ -+ tmp |= (uint32_t)bp->bpool[i].size; -+ } -+ -+ iowrite32be(tmp, &bp_reg[i]); -+ } -+ -+ /* Clear unused pools */ -+ for (i = bp->count; i < max_bp_num; i++) -+ iowrite32be(0, &bp_reg[i]); -+ -+ /* Pools depletion */ -+ tmp = 0; -+ for (i = 0; i < FMAN_PORT_MAX_EXT_POOLS_NUM; i++) { -+ if (bp->bpool[i].grp_bp_depleted) { -+ grp_depl_used = TRUE; -+ tmp |= 0x80000000 >> i; -+ } -+ -+ if (bp->bpool[i].single_bp_depleted) -+ tmp |= 0x80 >> i; -+ -+ if (bp->bpool[i].pfc_priorities_en) -+ tmp |= 0x0100 << i; -+ } -+ -+ if (grp_depl_used) -+ tmp |= ((uint32_t)bp->grp_bp_depleted_num - 1) << -+ BMI_POOL_DEP_NUM_OF_POOLS_SHIFT; -+ -+ iowrite32be(tmp, bp_depl_reg); -+ return 0; -+} -+ -+int fman_port_set_rate_limiter(struct fman_port *port, -+ struct fman_port_rate_limiter *rate_limiter) -+{ -+ uint32_t *rate_limit_reg, *rate_limit_scale_reg; -+ uint32_t granularity, tmp; -+ uint8_t usec_bit, factor; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_TX: -+ case E_FMAN_PORT_TYPE_TX_10G: -+ rate_limit_reg = &port->bmi_regs->tx.fmbm_trlmt; -+ rate_limit_scale_reg = &port->bmi_regs->tx.fmbm_trlmts; -+ granularity = BMI_RATE_LIMIT_GRAN_TX; -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ rate_limit_reg = &port->bmi_regs->oh.fmbm_orlmt; -+ rate_limit_scale_reg = &port->bmi_regs->oh.fmbm_orlmts; -+ granularity = BMI_RATE_LIMIT_GRAN_OP; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ /* Factor is per 1 usec count */ -+ factor = 1; -+ usec_bit = rate_limiter->count_1micro_bit; -+ -+ /* If rate limit is too small for an 1usec factor, adjust timestamp -+ * scale and multiply the factor */ -+ while (rate_limiter->rate < (granularity / factor)) { -+ if (usec_bit == 31) -+ /* Can't configure rate limiter - rate is too small */ -+ return -EINVAL; -+ -+ usec_bit++; -+ factor <<= 1; -+ } -+ -+ /* Figure out register value. The "while" above quarantees that -+ * (rate_limiter->rate * factor / granularity) >= 1 */ -+ tmp = (uint32_t)(rate_limiter->rate * factor / granularity - 1); -+ -+ /* Check rate limit isn't too large */ -+ if (tmp >= BMI_RATE_LIMIT_MAX_RATE_IN_GRAN_UNITS) -+ return -EINVAL; -+ -+ /* Check burst size is in allowed range */ -+ if ((rate_limiter->burst_size == 0) || -+ (rate_limiter->burst_size > -+ BMI_RATE_LIMIT_MAX_BURST_SIZE)) -+ return -EINVAL; -+ -+ tmp |= (uint32_t)(rate_limiter->burst_size - 1) << -+ BMI_RATE_LIMIT_MAX_BURST_SHIFT; -+ -+ if ((port->type == E_FMAN_PORT_TYPE_OP) && -+ (port->fm_rev_maj == 4)) { -+ if (rate_limiter->high_burst_size_gran) -+ tmp |= BMI_RATE_LIMIT_HIGH_BURST_SIZE_GRAN; -+ } -+ -+ iowrite32be(tmp, rate_limit_reg); -+ -+ /* Set up rate limiter scale register */ -+ tmp = BMI_RATE_LIMIT_SCALE_EN; -+ tmp |= (31 - (uint32_t)usec_bit) << BMI_RATE_LIMIT_SCALE_TSBS_SHIFT; -+ -+ if ((port->type == E_FMAN_PORT_TYPE_OP) && -+ (port->fm_rev_maj == 4)) -+ tmp |= rate_limiter->rate_factor; -+ -+ iowrite32be(tmp, rate_limit_scale_reg); -+ -+ return 0; -+} -+ -+int fman_port_delete_rate_limiter(struct fman_port *port) -+{ -+ uint32_t *rate_limit_scale_reg; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_TX: -+ case E_FMAN_PORT_TYPE_TX_10G: -+ rate_limit_scale_reg = &port->bmi_regs->tx.fmbm_trlmts; -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ rate_limit_scale_reg = &port->bmi_regs->oh.fmbm_orlmts; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ iowrite32be(0, rate_limit_scale_reg); -+ return 0; -+} -+ -+int fman_port_set_err_mask(struct fman_port *port, uint32_t err_mask) -+{ -+ uint32_t *err_mask_reg; -+ -+ /* Obtain register address */ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ err_mask_reg = &port->bmi_regs->rx.fmbm_rfsem; -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ err_mask_reg = &port->bmi_regs->oh.fmbm_ofsem; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ iowrite32be(err_mask, err_mask_reg); -+ return 0; -+} -+ -+int fman_port_set_discard_mask(struct fman_port *port, uint32_t discard_mask) -+{ -+ uint32_t *discard_mask_reg; -+ -+ /* Obtain register address */ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ discard_mask_reg = &port->bmi_regs->rx.fmbm_rfsdm; -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ discard_mask_reg = &port->bmi_regs->oh.fmbm_ofsdm; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ iowrite32be(discard_mask, discard_mask_reg); -+ return 0; -+} -+ -+int fman_port_modify_rx_fd_bits(struct fman_port *port, -+ uint8_t rx_fd_bits, -+ bool add) -+{ -+ uint32_t tmp; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ tmp = ioread32be(&port->bmi_regs->rx.fmbm_rfne); -+ -+ if (add) -+ tmp |= (uint32_t)rx_fd_bits << BMI_NEXT_ENG_FD_BITS_SHIFT; -+ else -+ tmp &= ~((uint32_t)rx_fd_bits << BMI_NEXT_ENG_FD_BITS_SHIFT); -+ -+ iowrite32be(tmp, &port->bmi_regs->rx.fmbm_rfne); -+ return 0; -+} -+ -+int fman_port_set_perf_cnt_params(struct fman_port *port, -+ struct fman_port_perf_cnt_params *params) -+{ -+ uint32_t *pcp_reg, tmp; -+ -+ /* Obtain register address and check parameters are in range */ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ pcp_reg = &port->bmi_regs->rx.fmbm_rpcp; -+ if ((params->queue_val == 0) || -+ (params->queue_val > MAX_PERFORMANCE_RX_QUEUE_COMP)) -+ return -EINVAL; -+ break; -+ case E_FMAN_PORT_TYPE_TX: -+ case E_FMAN_PORT_TYPE_TX_10G: -+ pcp_reg = &port->bmi_regs->tx.fmbm_tpcp; -+ if ((params->queue_val == 0) || -+ (params->queue_val > MAX_PERFORMANCE_TX_QUEUE_COMP)) -+ return -EINVAL; -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ case E_FMAN_PORT_TYPE_HC: -+ pcp_reg = &port->bmi_regs->oh.fmbm_opcp; -+ if (params->queue_val != 0) -+ return -EINVAL; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if ((params->task_val == 0) || -+ (params->task_val > MAX_PERFORMANCE_TASK_COMP)) -+ return -EINVAL; -+ if ((params->dma_val == 0) || -+ (params->dma_val > MAX_PERFORMANCE_DMA_COMP)) -+ return -EINVAL; -+ if ((params->fifo_val == 0) || -+ ((params->fifo_val / FMAN_PORT_BMI_FIFO_UNITS) > -+ MAX_PERFORMANCE_FIFO_COMP)) -+ return -EINVAL; -+ tmp = (uint32_t)(params->task_val - 1) << -+ BMI_PERFORMANCE_TASK_COMP_SHIFT; -+ tmp |= (uint32_t)(params->dma_val - 1) << -+ BMI_PERFORMANCE_DMA_COMP_SHIFT; -+ tmp |= (uint32_t)(params->fifo_val / FMAN_PORT_BMI_FIFO_UNITS - 1); -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ case E_FMAN_PORT_TYPE_TX: -+ case E_FMAN_PORT_TYPE_TX_10G: -+ tmp |= (uint32_t)(params->queue_val - 1) << -+ BMI_PERFORMANCE_QUEUE_COMP_SHIFT; -+ break; -+ default: -+ break; -+ } -+ -+ -+ iowrite32be(tmp, pcp_reg); -+ return 0; -+} -+ -+int fman_port_set_stats_cnt_mode(struct fman_port *port, bool enable) -+{ -+ uint32_t *stats_reg, tmp; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ stats_reg = &port->bmi_regs->rx.fmbm_rstc; -+ break; -+ case E_FMAN_PORT_TYPE_TX: -+ case E_FMAN_PORT_TYPE_TX_10G: -+ stats_reg = &port->bmi_regs->tx.fmbm_tstc; -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ case E_FMAN_PORT_TYPE_HC: -+ stats_reg = &port->bmi_regs->oh.fmbm_ostc; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ tmp = ioread32be(stats_reg); -+ -+ if (enable) -+ tmp |= BMI_COUNTERS_EN; -+ else -+ tmp &= ~BMI_COUNTERS_EN; -+ -+ iowrite32be(tmp, stats_reg); -+ return 0; -+} -+ -+int fman_port_set_perf_cnt_mode(struct fman_port *port, bool enable) -+{ -+ uint32_t *stats_reg, tmp; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ stats_reg = &port->bmi_regs->rx.fmbm_rpc; -+ break; -+ case E_FMAN_PORT_TYPE_TX: -+ case E_FMAN_PORT_TYPE_TX_10G: -+ stats_reg = &port->bmi_regs->tx.fmbm_tpc; -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ case E_FMAN_PORT_TYPE_HC: -+ stats_reg = &port->bmi_regs->oh.fmbm_opc; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ tmp = ioread32be(stats_reg); -+ -+ if (enable) -+ tmp |= BMI_COUNTERS_EN; -+ else -+ tmp &= ~BMI_COUNTERS_EN; -+ -+ iowrite32be(tmp, stats_reg); -+ return 0; -+} -+ -+int fman_port_set_queue_cnt_mode(struct fman_port *port, bool enable) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(&port->qmi_regs->fmqm_pnc); -+ -+ if (enable) -+ tmp |= QMI_PORT_CFG_EN_COUNTERS; -+ else -+ tmp &= ~QMI_PORT_CFG_EN_COUNTERS; -+ -+ iowrite32be(tmp, &port->qmi_regs->fmqm_pnc); -+ return 0; -+} -+ -+int fman_port_set_bpool_cnt_mode(struct fman_port *port, -+ uint8_t bpid, -+ bool enable) -+{ -+ uint8_t index; -+ uint32_t tmp; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ /* Find the pool */ -+ index = fman_port_find_bpool(port, bpid); -+ if (index == port->ext_pools_num || index == FMAN_PORT_MAX_EXT_POOLS_NUM) -+ /* Not found */ -+ return -EINVAL; -+ -+ tmp = ioread32be(&port->bmi_regs->rx.fmbm_ebmpi[index]); -+ -+ if (enable) -+ tmp |= BMI_EXT_BUF_POOL_EN_COUNTER; -+ else -+ tmp &= ~BMI_EXT_BUF_POOL_EN_COUNTER; -+ -+ iowrite32be(tmp, &port->bmi_regs->rx.fmbm_ebmpi[index]); -+ return 0; -+} -+ -+uint32_t fman_port_get_stats_counter(struct fman_port *port, -+ enum fman_port_stats_counters counter) -+{ -+ uint32_t *stats_reg, ret_val; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ get_rx_stats_reg(port, counter, &stats_reg); -+ break; -+ case E_FMAN_PORT_TYPE_TX: -+ case E_FMAN_PORT_TYPE_TX_10G: -+ get_tx_stats_reg(port, counter, &stats_reg); -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ case E_FMAN_PORT_TYPE_HC: -+ get_oh_stats_reg(port, counter, &stats_reg); -+ break; -+ default: -+ stats_reg = NULL; -+ } -+ -+ if (stats_reg == NULL) -+ return 0; -+ -+ ret_val = ioread32be(stats_reg); -+ return ret_val; -+} -+ -+void fman_port_set_stats_counter(struct fman_port *port, -+ enum fman_port_stats_counters counter, -+ uint32_t value) -+{ -+ uint32_t *stats_reg; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ get_rx_stats_reg(port, counter, &stats_reg); -+ break; -+ case E_FMAN_PORT_TYPE_TX: -+ case E_FMAN_PORT_TYPE_TX_10G: -+ get_tx_stats_reg(port, counter, &stats_reg); -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ case E_FMAN_PORT_TYPE_HC: -+ get_oh_stats_reg(port, counter, &stats_reg); -+ break; -+ default: -+ stats_reg = NULL; -+ } -+ -+ if (stats_reg == NULL) -+ return; -+ -+ iowrite32be(value, stats_reg); -+} -+ -+uint32_t fman_port_get_perf_counter(struct fman_port *port, -+ enum fman_port_perf_counters counter) -+{ -+ uint32_t *perf_reg, ret_val; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ get_rx_perf_reg(port, counter, &perf_reg); -+ break; -+ case E_FMAN_PORT_TYPE_TX: -+ case E_FMAN_PORT_TYPE_TX_10G: -+ get_tx_perf_reg(port, counter, &perf_reg); -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ case E_FMAN_PORT_TYPE_HC: -+ get_oh_perf_reg(port, counter, &perf_reg); -+ break; -+ default: -+ perf_reg = NULL; -+ } -+ -+ if (perf_reg == NULL) -+ return 0; -+ -+ ret_val = ioread32be(perf_reg); -+ return ret_val; -+} -+ -+void fman_port_set_perf_counter(struct fman_port *port, -+ enum fman_port_perf_counters counter, -+ uint32_t value) -+{ -+ uint32_t *perf_reg; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ get_rx_perf_reg(port, counter, &perf_reg); -+ break; -+ case E_FMAN_PORT_TYPE_TX: -+ case E_FMAN_PORT_TYPE_TX_10G: -+ get_tx_perf_reg(port, counter, &perf_reg); -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ case E_FMAN_PORT_TYPE_HC: -+ get_oh_perf_reg(port, counter, &perf_reg); -+ break; -+ default: -+ perf_reg = NULL; -+ } -+ -+ if (perf_reg == NULL) -+ return; -+ -+ iowrite32be(value, perf_reg); -+} -+ -+uint32_t fman_port_get_qmi_counter(struct fman_port *port, -+ enum fman_port_qmi_counters counter) -+{ -+ uint32_t *queue_reg, ret_val; -+ -+ get_qmi_counter_reg(port, counter, &queue_reg); -+ -+ if (queue_reg == NULL) -+ return 0; -+ -+ ret_val = ioread32be(queue_reg); -+ return ret_val; -+} -+ -+void fman_port_set_qmi_counter(struct fman_port *port, -+ enum fman_port_qmi_counters counter, -+ uint32_t value) -+{ -+ uint32_t *queue_reg; -+ -+ get_qmi_counter_reg(port, counter, &queue_reg); -+ -+ if (queue_reg == NULL) -+ return; -+ -+ iowrite32be(value, queue_reg); -+} -+ -+uint32_t fman_port_get_bpool_counter(struct fman_port *port, uint8_t bpid) -+{ -+ uint8_t index; -+ uint32_t ret_val; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ break; -+ default: -+ return 0; -+ } -+ -+ /* Find the pool */ -+ index = fman_port_find_bpool(port, bpid); -+ if (index == port->ext_pools_num || index == FMAN_PORT_MAX_EXT_POOLS_NUM) -+ /* Not found */ -+ return 0; -+ -+ ret_val = ioread32be(&port->bmi_regs->rx.fmbm_acnt[index]); -+ return ret_val; -+} -+ -+void fman_port_set_bpool_counter(struct fman_port *port, -+ uint8_t bpid, -+ uint32_t value) -+{ -+ uint8_t index; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ break; -+ default: -+ return; -+ } -+ -+ /* Find the pool */ -+ index = fman_port_find_bpool(port, bpid); -+ if (index == port->ext_pools_num || index == FMAN_PORT_MAX_EXT_POOLS_NUM) -+ /* Not found */ -+ return; -+ -+ iowrite32be(value, &port->bmi_regs->rx.fmbm_acnt[index]); -+} -+ -+int fman_port_add_congestion_grps(struct fman_port *port, -+ uint32_t grps_map[FMAN_PORT_CG_MAP_NUM]) -+{ -+ int i; -+ uint32_t tmp, *grp_map_reg; -+ uint8_t max_grp_map_num; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ if (port->fm_rev_maj == 4) -+ max_grp_map_num = 1; -+ else -+ max_grp_map_num = FMAN_PORT_CG_MAP_NUM; -+ grp_map_reg = port->bmi_regs->rx.fmbm_rcgm; -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ max_grp_map_num = 1; -+ if (port->fm_rev_maj != 4) -+ return -EINVAL; -+ grp_map_reg = port->bmi_regs->oh.fmbm_ocgm; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ for (i = (max_grp_map_num - 1); i >= 0; i--) { -+ if (grps_map[i] == 0) -+ continue; -+ tmp = ioread32be(&grp_map_reg[i]); -+ tmp |= grps_map[i]; -+ iowrite32be(tmp, &grp_map_reg[i]); -+ } -+ -+ return 0; -+} -+ -+int fman_port_remove_congestion_grps(struct fman_port *port, -+ uint32_t grps_map[FMAN_PORT_CG_MAP_NUM]) -+{ -+ int i; -+ uint32_t tmp, *grp_map_reg; -+ uint8_t max_grp_map_num; -+ -+ switch (port->type) { -+ case E_FMAN_PORT_TYPE_RX: -+ case E_FMAN_PORT_TYPE_RX_10G: -+ if (port->fm_rev_maj == 4) -+ max_grp_map_num = 1; -+ else -+ max_grp_map_num = FMAN_PORT_CG_MAP_NUM; -+ grp_map_reg = port->bmi_regs->rx.fmbm_rcgm; -+ break; -+ case E_FMAN_PORT_TYPE_OP: -+ max_grp_map_num = 1; -+ if (port->fm_rev_maj != 4) -+ return -EINVAL; -+ grp_map_reg = port->bmi_regs->oh.fmbm_ocgm; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ for (i = (max_grp_map_num - 1); i >= 0; i--) { -+ if (grps_map[i] == 0) -+ continue; -+ tmp = ioread32be(&grp_map_reg[i]); -+ tmp &= ~grps_map[i]; -+ iowrite32be(tmp, &grp_map_reg[i]); -+ } -+ return 0; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/Makefile -@@ -0,0 +1,15 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+ -+NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc -+ -+ccflags-y += -I$(NCSW_FM_INC) -+ -+obj-y += fsl-ncsw-RTC.o -+ -+fsl-ncsw-RTC-objs := fm_rtc.o fman_rtc.o ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.c -@@ -0,0 +1,692 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_rtc.c -+ -+ @Description FM RTC driver implementation. -+ -+ @Cautions None -+*//***************************************************************************/ -+ -+#include "error_ext.h" -+#include "debug_ext.h" -+#include "string_ext.h" -+#include "part_ext.h" -+#include "xx_ext.h" -+#include "ncsw_ext.h" -+ -+#include "fm_rtc.h" -+#include "fm_common.h" -+ -+ -+ -+/*****************************************************************************/ -+static t_Error CheckInitParameters(t_FmRtc *p_Rtc) -+{ -+ struct rtc_cfg *p_RtcDriverParam = p_Rtc->p_RtcDriverParam; -+ int i; -+ -+ if ((p_RtcDriverParam->src_clk != E_FMAN_RTC_SOURCE_CLOCK_EXTERNAL) && -+ (p_RtcDriverParam->src_clk != E_FMAN_RTC_SOURCE_CLOCK_SYSTEM) && -+ (p_RtcDriverParam->src_clk != E_FMAN_RTC_SOURCE_CLOCK_OSCILATOR)) -+ RETURN_ERROR(MAJOR, E_INVALID_CLOCK, ("Source clock undefined")); -+ -+ if (p_Rtc->outputClockDivisor == 0) -+ { -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("Divisor for output clock (should be positive)")); -+ } -+ -+ for (i=0; i < FM_RTC_NUM_OF_ALARMS; i++) -+ { -+ if ((p_RtcDriverParam->alarm_polarity[i] != E_FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW) && -+ (p_RtcDriverParam->alarm_polarity[i] != E_FMAN_RTC_ALARM_POLARITY_ACTIVE_HIGH)) -+ { -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm %d signal polarity", i)); -+ } -+ } -+ for (i=0; i < FM_RTC_NUM_OF_EXT_TRIGGERS; i++) -+ { -+ if ((p_RtcDriverParam->trigger_polarity[i] != E_FMAN_RTC_TRIGGER_ON_FALLING_EDGE) && -+ (p_RtcDriverParam->trigger_polarity[i] != E_FMAN_RTC_TRIGGER_ON_RISING_EDGE)) -+ { -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Trigger %d signal polarity", i)); -+ } -+ } -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+static void RtcExceptions(t_Handle h_FmRtc) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ struct rtc_regs *p_MemMap; -+ register uint32_t events; -+ -+ ASSERT_COND(p_Rtc); -+ p_MemMap = p_Rtc->p_MemMap; -+ -+ events = fman_rtc_check_and_clear_event(p_MemMap); -+ if (events & FMAN_RTC_TMR_TEVENT_ALM1) -+ { -+ if (p_Rtc->alarmParams[0].clearOnExpiration) -+ { -+ fman_rtc_set_timer_alarm_l(p_MemMap, 0, 0); -+ fman_rtc_disable_interupt(p_MemMap, FMAN_RTC_TMR_TEVENT_ALM1); -+ } -+ ASSERT_COND(p_Rtc->alarmParams[0].f_AlarmCallback); -+ p_Rtc->alarmParams[0].f_AlarmCallback(p_Rtc->h_App, 0); -+ } -+ if (events & FMAN_RTC_TMR_TEVENT_ALM2) -+ { -+ if (p_Rtc->alarmParams[1].clearOnExpiration) -+ { -+ fman_rtc_set_timer_alarm_l(p_MemMap, 1, 0); -+ fman_rtc_disable_interupt(p_MemMap, FMAN_RTC_TMR_TEVENT_ALM2); -+ } -+ ASSERT_COND(p_Rtc->alarmParams[1].f_AlarmCallback); -+ p_Rtc->alarmParams[1].f_AlarmCallback(p_Rtc->h_App, 1); -+ } -+ if (events & FMAN_RTC_TMR_TEVENT_PP1) -+ { -+ ASSERT_COND(p_Rtc->periodicPulseParams[0].f_PeriodicPulseCallback); -+ p_Rtc->periodicPulseParams[0].f_PeriodicPulseCallback(p_Rtc->h_App, 0); -+ } -+ if (events & FMAN_RTC_TMR_TEVENT_PP2) -+ { -+ ASSERT_COND(p_Rtc->periodicPulseParams[1].f_PeriodicPulseCallback); -+ p_Rtc->periodicPulseParams[1].f_PeriodicPulseCallback(p_Rtc->h_App, 1); -+ } -+ if (events & FMAN_RTC_TMR_TEVENT_ETS1) -+ { -+ ASSERT_COND(p_Rtc->externalTriggerParams[0].f_ExternalTriggerCallback); -+ p_Rtc->externalTriggerParams[0].f_ExternalTriggerCallback(p_Rtc->h_App, 0); -+ } -+ if (events & FMAN_RTC_TMR_TEVENT_ETS2) -+ { -+ ASSERT_COND(p_Rtc->externalTriggerParams[1].f_ExternalTriggerCallback); -+ p_Rtc->externalTriggerParams[1].f_ExternalTriggerCallback(p_Rtc->h_App, 1); -+ } -+} -+ -+ -+/*****************************************************************************/ -+t_Handle FM_RTC_Config(t_FmRtcParams *p_FmRtcParam) -+{ -+ t_FmRtc *p_Rtc; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmRtcParam, E_NULL_POINTER, NULL); -+ -+ /* Allocate memory for the FM RTC driver parameters */ -+ p_Rtc = (t_FmRtc *)XX_Malloc(sizeof(t_FmRtc)); -+ if (!p_Rtc) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM RTC driver structure")); -+ return NULL; -+ } -+ -+ memset(p_Rtc, 0, sizeof(t_FmRtc)); -+ -+ /* Allocate memory for the FM RTC driver parameters */ -+ p_Rtc->p_RtcDriverParam = (struct rtc_cfg *)XX_Malloc(sizeof(struct rtc_cfg)); -+ if (!p_Rtc->p_RtcDriverParam) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM RTC driver parameters")); -+ XX_Free(p_Rtc); -+ return NULL; -+ } -+ -+ memset(p_Rtc->p_RtcDriverParam, 0, sizeof(struct rtc_cfg)); -+ -+ /* Store RTC configuration parameters */ -+ p_Rtc->h_Fm = p_FmRtcParam->h_Fm; -+ -+ /* Set default RTC configuration parameters */ -+ fman_rtc_defconfig(p_Rtc->p_RtcDriverParam); -+ -+ p_Rtc->outputClockDivisor = DEFAULT_OUTPUT_CLOCK_DIVISOR; -+ p_Rtc->p_RtcDriverParam->bypass = DEFAULT_BYPASS; -+ p_Rtc->clockPeriodNanoSec = DEFAULT_CLOCK_PERIOD; /* 1 usec */ -+ -+ -+ /* Store RTC parameters in the RTC control structure */ -+ p_Rtc->p_MemMap = (struct rtc_regs *)UINT_TO_PTR(p_FmRtcParam->baseAddress); -+ p_Rtc->h_App = p_FmRtcParam->h_App; -+ -+ return p_Rtc; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_Init(t_Handle h_FmRtc) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ struct rtc_cfg *p_RtcDriverParam; -+ struct rtc_regs *p_MemMap; -+ uint32_t freqCompensation = 0; -+ uint64_t tmpDouble; -+ bool init_freq_comp = FALSE; -+ -+ p_RtcDriverParam = p_Rtc->p_RtcDriverParam; -+ p_MemMap = p_Rtc->p_MemMap; -+ -+ if (CheckInitParameters(p_Rtc)!=E_OK) -+ RETURN_ERROR(MAJOR, E_CONFLICT, -+ ("Init Parameters are not Valid")); -+ -+ /* TODO check that no timestamping MACs are working in this stage. */ -+ -+ /* find source clock frequency in Mhz */ -+ if (p_Rtc->p_RtcDriverParam->src_clk != E_FMAN_RTC_SOURCE_CLOCK_SYSTEM) -+ p_Rtc->srcClkFreqMhz = p_Rtc->p_RtcDriverParam->ext_src_clk_freq; -+ else -+ p_Rtc->srcClkFreqMhz = (uint32_t)(FmGetMacClockFreq(p_Rtc->h_Fm)); -+ -+ /* if timer in Master mode Initialize TMR_CTRL */ -+ /* We want the counter (TMR_CNT) to count in nano-seconds */ -+ if (!p_RtcDriverParam->timer_slave_mode && p_Rtc->p_RtcDriverParam->bypass) -+ p_Rtc->clockPeriodNanoSec = (1000 / p_Rtc->srcClkFreqMhz); -+ else -+ { -+ /* Initialize TMR_ADD with the initial frequency compensation value: -+ freqCompensation = (2^32 / frequency ratio) */ -+ /* frequency ratio = sorce clock/rtc clock = -+ * (p_Rtc->srcClkFreqMhz*1000000))/ 1/(p_Rtc->clockPeriodNanoSec * 1000000000) */ -+ init_freq_comp = TRUE; -+ freqCompensation = (uint32_t)DIV_CEIL(ACCUMULATOR_OVERFLOW * 1000, -+ p_Rtc->clockPeriodNanoSec * p_Rtc->srcClkFreqMhz); -+ } -+ -+ /* check the legality of the relation between source and destination clocks */ -+ /* should be larger than 1.0001 */ -+ tmpDouble = 10000 * (uint64_t)p_Rtc->clockPeriodNanoSec * (uint64_t)p_Rtc->srcClkFreqMhz; -+ if ((tmpDouble) <= 10001) -+ RETURN_ERROR(MAJOR, E_CONFLICT, -+ ("Invalid relation between source and destination clocks. Should be larger than 1.0001")); -+ -+ fman_rtc_init(p_RtcDriverParam, -+ p_MemMap, -+ FM_RTC_NUM_OF_ALARMS, -+ FM_RTC_NUM_OF_PERIODIC_PULSES, -+ FM_RTC_NUM_OF_EXT_TRIGGERS, -+ init_freq_comp, -+ freqCompensation, -+ p_Rtc->outputClockDivisor); -+ -+ /* Register the FM RTC interrupt */ -+ FmRegisterIntr(p_Rtc->h_Fm, e_FM_MOD_TMR, 0, e_FM_INTR_TYPE_NORMAL, RtcExceptions , p_Rtc); -+ -+ /* Free parameters structures */ -+ XX_Free(p_Rtc->p_RtcDriverParam); -+ p_Rtc->p_RtcDriverParam = NULL; -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_Free(t_Handle h_FmRtc) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ -+ if (p_Rtc->p_RtcDriverParam) -+ { -+ XX_Free(p_Rtc->p_RtcDriverParam); -+ } -+ else -+ { -+ FM_RTC_Disable(h_FmRtc); -+ } -+ -+ /* Unregister FM RTC interrupt */ -+ FmUnregisterIntr(p_Rtc->h_Fm, e_FM_MOD_TMR, 0, e_FM_INTR_TYPE_NORMAL); -+ XX_Free(p_Rtc); -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_ConfigSourceClock(t_Handle h_FmRtc, -+ e_FmSrcClk srcClk, -+ uint32_t freqInMhz) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ p_Rtc->p_RtcDriverParam->src_clk = (enum fman_src_clock)srcClk; -+ if (srcClk != e_FM_RTC_SOURCE_CLOCK_SYSTEM) -+ p_Rtc->p_RtcDriverParam->ext_src_clk_freq = freqInMhz; -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_ConfigPeriod(t_Handle h_FmRtc, uint32_t period) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ p_Rtc->clockPeriodNanoSec = period; -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_ConfigFrequencyBypass(t_Handle h_FmRtc, bool enabled) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ p_Rtc->p_RtcDriverParam->bypass = enabled; -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_ConfigInvertedInputClockPhase(t_Handle h_FmRtc, bool inverted) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ p_Rtc->p_RtcDriverParam->invert_input_clk_phase = inverted; -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_ConfigInvertedOutputClockPhase(t_Handle h_FmRtc, bool inverted) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ p_Rtc->p_RtcDriverParam->invert_output_clk_phase = inverted; -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_ConfigOutputClockDivisor(t_Handle h_FmRtc, uint16_t divisor) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ p_Rtc->outputClockDivisor = divisor; -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_ConfigPulseRealignment(t_Handle h_FmRtc, bool enable) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ p_Rtc->p_RtcDriverParam->pulse_realign = enable; -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_ConfigAlarmPolarity(t_Handle h_FmRtc, -+ uint8_t alarmId, -+ e_FmRtcAlarmPolarity alarmPolarity) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ if (alarmId >= FM_RTC_NUM_OF_ALARMS) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm ID")); -+ -+ p_Rtc->p_RtcDriverParam->alarm_polarity[alarmId] = -+ (enum fman_rtc_alarm_polarity)alarmPolarity; -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_ConfigExternalTriggerPolarity(t_Handle h_FmRtc, -+ uint8_t triggerId, -+ e_FmRtcTriggerPolarity triggerPolarity) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ if (triggerId >= FM_RTC_NUM_OF_EXT_TRIGGERS) -+ { -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External trigger ID")); -+ } -+ -+ p_Rtc->p_RtcDriverParam->trigger_polarity[triggerId] = -+ (enum fman_rtc_trigger_polarity)triggerPolarity; -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_Enable(t_Handle h_FmRtc, bool resetClock) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ fman_rtc_enable(p_Rtc->p_MemMap, resetClock); -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_Disable(t_Handle h_FmRtc) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ /* TODO A check must be added here, that no timestamping MAC's -+ * are working in this stage. */ -+ fman_rtc_disable(p_Rtc->p_MemMap); -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_SetClockOffset(t_Handle h_FmRtc, int64_t offset) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ fman_rtc_set_timer_offset(p_Rtc->p_MemMap, offset); -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_SetAlarm(t_Handle h_FmRtc, t_FmRtcAlarmParams *p_FmRtcAlarmParams) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ uint64_t tmpAlarm; -+ bool enable = FALSE; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ if (p_FmRtcAlarmParams->alarmId >= FM_RTC_NUM_OF_ALARMS) -+ { -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm ID")); -+ } -+ -+ if (p_FmRtcAlarmParams->alarmTime < p_Rtc->clockPeriodNanoSec) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, -+ ("Alarm time must be equal or larger than RTC period - %d nanoseconds", -+ p_Rtc->clockPeriodNanoSec)); -+ if (p_FmRtcAlarmParams->alarmTime % (uint64_t)p_Rtc->clockPeriodNanoSec) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, -+ ("Alarm time must be a multiple of RTC period - %d nanoseconds", -+ p_Rtc->clockPeriodNanoSec)); -+ tmpAlarm = p_FmRtcAlarmParams->alarmTime/(uint64_t)p_Rtc->clockPeriodNanoSec; -+ -+ if (p_FmRtcAlarmParams->f_AlarmCallback) -+ { -+ p_Rtc->alarmParams[p_FmRtcAlarmParams->alarmId].f_AlarmCallback = p_FmRtcAlarmParams->f_AlarmCallback; -+ p_Rtc->alarmParams[p_FmRtcAlarmParams->alarmId].clearOnExpiration = p_FmRtcAlarmParams->clearOnExpiration; -+ enable = TRUE; -+ } -+ -+ fman_rtc_set_alarm(p_Rtc->p_MemMap, p_FmRtcAlarmParams->alarmId, (unsigned long)tmpAlarm, enable); -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_SetPeriodicPulse(t_Handle h_FmRtc, t_FmRtcPeriodicPulseParams *p_FmRtcPeriodicPulseParams) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ bool enable = FALSE; -+ uint64_t tmpFiper; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ if (p_FmRtcPeriodicPulseParams->periodicPulseId >= FM_RTC_NUM_OF_PERIODIC_PULSES) -+ { -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Periodic pulse ID")); -+ } -+ if (fman_rtc_is_enabled(p_Rtc->p_MemMap)) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Can't set Periodic pulse when RTC is enabled.")); -+ if (p_FmRtcPeriodicPulseParams->periodicPulsePeriod < p_Rtc->clockPeriodNanoSec) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, -+ ("Periodic pulse must be equal or larger than RTC period - %d nanoseconds", -+ p_Rtc->clockPeriodNanoSec)); -+ if (p_FmRtcPeriodicPulseParams->periodicPulsePeriod % (uint64_t)p_Rtc->clockPeriodNanoSec) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, -+ ("Periodic pulse must be a multiple of RTC period - %d nanoseconds", -+ p_Rtc->clockPeriodNanoSec)); -+ tmpFiper = p_FmRtcPeriodicPulseParams->periodicPulsePeriod/(uint64_t)p_Rtc->clockPeriodNanoSec; -+ if (tmpFiper & 0xffffffff00000000LL) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, -+ ("Periodic pulse/RTC Period must be smaller than 4294967296", -+ p_Rtc->clockPeriodNanoSec)); -+ -+ if (p_FmRtcPeriodicPulseParams->f_PeriodicPulseCallback) -+ { -+ p_Rtc->periodicPulseParams[p_FmRtcPeriodicPulseParams->periodicPulseId].f_PeriodicPulseCallback = -+ p_FmRtcPeriodicPulseParams->f_PeriodicPulseCallback; -+ enable = TRUE; -+ } -+ fman_rtc_set_periodic_pulse(p_Rtc->p_MemMap, p_FmRtcPeriodicPulseParams->periodicPulseId, (uint32_t)tmpFiper, enable); -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_ClearPeriodicPulse(t_Handle h_FmRtc, uint8_t periodicPulseId) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ if (periodicPulseId >= FM_RTC_NUM_OF_PERIODIC_PULSES) -+ { -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Periodic pulse ID")); -+ } -+ -+ p_Rtc->periodicPulseParams[periodicPulseId].f_PeriodicPulseCallback = NULL; -+ fman_rtc_clear_periodic_pulse(p_Rtc->p_MemMap, periodicPulseId); -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_SetExternalTrigger(t_Handle h_FmRtc, t_FmRtcExternalTriggerParams *p_FmRtcExternalTriggerParams) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ bool enable = FALSE; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ if (p_FmRtcExternalTriggerParams->externalTriggerId >= FM_RTC_NUM_OF_EXT_TRIGGERS) -+ { -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External Trigger ID")); -+ } -+ -+ if (p_FmRtcExternalTriggerParams->f_ExternalTriggerCallback) -+ { -+ p_Rtc->externalTriggerParams[p_FmRtcExternalTriggerParams->externalTriggerId].f_ExternalTriggerCallback = p_FmRtcExternalTriggerParams->f_ExternalTriggerCallback; -+ enable = TRUE; -+ } -+ -+ fman_rtc_set_ext_trigger(p_Rtc->p_MemMap, p_FmRtcExternalTriggerParams->externalTriggerId, enable, p_FmRtcExternalTriggerParams->usePulseAsInput); -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_ClearExternalTrigger(t_Handle h_FmRtc, uint8_t externalTriggerId) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ if (externalTriggerId >= FM_RTC_NUM_OF_EXT_TRIGGERS) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External Trigger ID")); -+ -+ p_Rtc->externalTriggerParams[externalTriggerId].f_ExternalTriggerCallback = NULL; -+ -+ fman_rtc_clear_external_trigger(p_Rtc->p_MemMap, externalTriggerId); -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_GetExternalTriggerTimeStamp(t_Handle h_FmRtc, -+ uint8_t triggerId, -+ uint64_t *p_TimeStamp) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ if (triggerId >= FM_RTC_NUM_OF_EXT_TRIGGERS) -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External trigger ID")); -+ -+ *p_TimeStamp = fman_rtc_get_trigger_stamp(p_Rtc->p_MemMap, triggerId)*p_Rtc->clockPeriodNanoSec; -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_GetCurrentTime(t_Handle h_FmRtc, uint64_t *p_Ts) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ *p_Ts = fman_rtc_get_timer(p_Rtc->p_MemMap)*p_Rtc->clockPeriodNanoSec; -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_SetCurrentTime(t_Handle h_FmRtc, uint64_t ts) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ ts = ts/p_Rtc->clockPeriodNanoSec; -+ fman_rtc_set_timer(p_Rtc->p_MemMap, (int64_t)ts); -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_GetFreqCompensation(t_Handle h_FmRtc, uint32_t *p_Compensation) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ *p_Compensation = fman_rtc_get_frequency_compensation(p_Rtc->p_MemMap); -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_SetFreqCompensation(t_Handle h_FmRtc, uint32_t freqCompensation) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ /* set the new freqCompensation */ -+ fman_rtc_set_frequency_compensation(p_Rtc->p_MemMap, freqCompensation); -+ -+ return E_OK; -+} -+ -+#ifdef CONFIG_PTP_1588_CLOCK_DPAA -+/*****************************************************************************/ -+t_Error FM_RTC_EnableInterrupt(t_Handle h_FmRtc, uint32_t events) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ /* enable interrupt */ -+ fman_rtc_enable_interupt(p_Rtc->p_MemMap, events); -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+t_Error FM_RTC_DisableInterrupt(t_Handle h_FmRtc, uint32_t events) -+{ -+ t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); -+ -+ /* disable interrupt */ -+ fman_rtc_disable_interupt(p_Rtc->p_MemMap, events); -+ -+ return E_OK; -+} -+#endif ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.h -@@ -0,0 +1,96 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_rtc.h -+ -+ @Description Memory map and internal definitions for FM RTC IEEE1588 Timer driver. -+ -+ @Cautions None -+*//***************************************************************************/ -+ -+#ifndef __FM_RTC_H__ -+#define __FM_RTC_H__ -+ -+#include "std_ext.h" -+#include "fm_rtc_ext.h" -+ -+ -+#define __ERR_MODULE__ MODULE_FM_RTC -+ -+/* General definitions */ -+ -+#define ACCUMULATOR_OVERFLOW ((uint64_t)(1LL << 32)) -+#define DEFAULT_OUTPUT_CLOCK_DIVISOR 0x00000002 -+#define DEFAULT_BYPASS FALSE -+#define DEFAULT_CLOCK_PERIOD 1000 -+ -+ -+ -+typedef struct t_FmRtcAlarm -+{ -+ t_FmRtcExceptionsCallback *f_AlarmCallback; -+ bool clearOnExpiration; -+} t_FmRtcAlarm; -+ -+typedef struct t_FmRtcPeriodicPulse -+{ -+ t_FmRtcExceptionsCallback *f_PeriodicPulseCallback; -+} t_FmRtcPeriodicPulse; -+ -+typedef struct t_FmRtcExternalTrigger -+{ -+ t_FmRtcExceptionsCallback *f_ExternalTriggerCallback; -+} t_FmRtcExternalTrigger; -+ -+ -+/**************************************************************************//** -+ @Description RTC FM driver control structure. -+*//***************************************************************************/ -+typedef struct t_FmRtc -+{ -+ t_Part *p_Part; /**< Pointer to the integration device */ -+ t_Handle h_Fm; -+ t_Handle h_App; /**< Application handle */ -+ struct rtc_regs *p_MemMap; -+ uint32_t clockPeriodNanoSec; /**< RTC clock period in nano-seconds (for FS mode) */ -+ uint32_t srcClkFreqMhz; -+ uint16_t outputClockDivisor; /**< Output clock divisor (for FS mode) */ -+ t_FmRtcAlarm alarmParams[FM_RTC_NUM_OF_ALARMS]; -+ t_FmRtcPeriodicPulse periodicPulseParams[FM_RTC_NUM_OF_PERIODIC_PULSES]; -+ t_FmRtcExternalTrigger externalTriggerParams[FM_RTC_NUM_OF_EXT_TRIGGERS]; -+ struct rtc_cfg *p_RtcDriverParam; /**< RTC Driver parameters (for Init phase) */ -+} t_FmRtc; -+ -+ -+#endif /* __FM_RTC_H__ */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fman_rtc.c -@@ -0,0 +1,334 @@ -+/* -+ * Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "fsl_fman_rtc.h" -+ -+void fman_rtc_defconfig(struct rtc_cfg *cfg) -+{ -+ int i; -+ cfg->src_clk = DEFAULT_SRC_CLOCK; -+ cfg->invert_input_clk_phase = DEFAULT_INVERT_INPUT_CLK_PHASE; -+ cfg->invert_output_clk_phase = DEFAULT_INVERT_OUTPUT_CLK_PHASE; -+ cfg->pulse_realign = DEFAULT_PULSE_REALIGN; -+ for (i = 0; i < FMAN_RTC_MAX_NUM_OF_ALARMS; i++) -+ cfg->alarm_polarity[i] = DEFAULT_ALARM_POLARITY; -+ for (i = 0; i < FMAN_RTC_MAX_NUM_OF_EXT_TRIGGERS; i++) -+ cfg->trigger_polarity[i] = DEFAULT_TRIGGER_POLARITY; -+} -+ -+uint32_t fman_rtc_get_events(struct rtc_regs *regs) -+{ -+ return ioread32be(®s->tmr_tevent); -+} -+ -+uint32_t fman_rtc_get_event(struct rtc_regs *regs, uint32_t ev_mask) -+{ -+ return ioread32be(®s->tmr_tevent) & ev_mask; -+} -+ -+uint32_t fman_rtc_get_interrupt_mask(struct rtc_regs *regs) -+{ -+ return ioread32be(®s->tmr_temask); -+} -+ -+void fman_rtc_set_interrupt_mask(struct rtc_regs *regs, uint32_t mask) -+{ -+ iowrite32be(mask, ®s->tmr_temask); -+} -+ -+void fman_rtc_ack_event(struct rtc_regs *regs, uint32_t events) -+{ -+ iowrite32be(events, ®s->tmr_tevent); -+} -+ -+uint32_t fman_rtc_check_and_clear_event(struct rtc_regs *regs) -+{ -+ uint32_t event; -+ -+ event = ioread32be(®s->tmr_tevent); -+ event &= ioread32be(®s->tmr_temask); -+ -+ if (event) -+ iowrite32be(event, ®s->tmr_tevent); -+ return event; -+} -+ -+uint32_t fman_rtc_get_frequency_compensation(struct rtc_regs *regs) -+{ -+ return ioread32be(®s->tmr_add); -+} -+ -+void fman_rtc_set_frequency_compensation(struct rtc_regs *regs, uint32_t val) -+{ -+ iowrite32be(val, ®s->tmr_add); -+} -+ -+void fman_rtc_enable_interupt(struct rtc_regs *regs, uint32_t events) -+{ -+ fman_rtc_set_interrupt_mask(regs, fman_rtc_get_interrupt_mask(regs) | events); -+} -+ -+void fman_rtc_disable_interupt(struct rtc_regs *regs, uint32_t events) -+{ -+ fman_rtc_set_interrupt_mask(regs, fman_rtc_get_interrupt_mask(regs) & ~events); -+} -+ -+void fman_rtc_set_timer_alarm_l(struct rtc_regs *regs, int index, uint32_t val) -+{ -+ iowrite32be(val, ®s->tmr_alarm[index].tmr_alarm_l); -+} -+ -+void fman_rtc_set_timer_fiper(struct rtc_regs *regs, int index, uint32_t val) -+{ -+ iowrite32be(val, ®s->tmr_fiper[index]); -+} -+ -+void fman_rtc_set_timer_alarm(struct rtc_regs *regs, int index, int64_t val) -+{ -+ iowrite32be((uint32_t)val, ®s->tmr_alarm[index].tmr_alarm_l); -+ iowrite32be((uint32_t)(val >> 32), ®s->tmr_alarm[index].tmr_alarm_h); -+} -+ -+void fman_rtc_set_timer_offset(struct rtc_regs *regs, int64_t val) -+{ -+ iowrite32be((uint32_t)val, ®s->tmr_off_l); -+ iowrite32be((uint32_t)(val >> 32), ®s->tmr_off_h); -+} -+ -+uint64_t fman_rtc_get_trigger_stamp(struct rtc_regs *regs, int id) -+{ -+ uint64_t time; -+ /* TMR_CNT_L must be read first to get an accurate value */ -+ time = (uint64_t)ioread32be(®s->tmr_etts[id].tmr_etts_l); -+ time |= ((uint64_t)ioread32be(®s->tmr_etts[id].tmr_etts_h) -+ << 32); -+ -+ return time; -+} -+ -+uint32_t fman_rtc_get_timer_ctrl(struct rtc_regs *regs) -+{ -+ return ioread32be(®s->tmr_ctrl); -+} -+ -+void fman_rtc_set_timer_ctrl(struct rtc_regs *regs, uint32_t val) -+{ -+ iowrite32be(val, ®s->tmr_ctrl); -+} -+ -+void fman_rtc_timers_soft_reset(struct rtc_regs *regs) -+{ -+ fman_rtc_set_timer_ctrl(regs, FMAN_RTC_TMR_CTRL_TMSR); -+ udelay(10); -+ fman_rtc_set_timer_ctrl(regs, 0); -+} -+ -+void fman_rtc_init(struct rtc_cfg *cfg, struct rtc_regs *regs, int num_alarms, -+ int num_fipers, int num_ext_triggers, bool init_freq_comp, -+ uint32_t freq_compensation, uint32_t output_clock_divisor) -+{ -+ uint32_t tmr_ctrl; -+ int i; -+ -+ fman_rtc_timers_soft_reset(regs); -+ -+ /* Set the source clock */ -+ switch (cfg->src_clk) { -+ case E_FMAN_RTC_SOURCE_CLOCK_SYSTEM: -+ tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_MAC_CLK; -+ break; -+ case E_FMAN_RTC_SOURCE_CLOCK_OSCILATOR: -+ tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_OSC_CLK; -+ break; -+ default: -+ /* Use a clock from the External TMR reference clock.*/ -+ tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_EXT_CLK; -+ break; -+ } -+ -+ /* whatever period the user picked, the timestamp will advance in '1' -+ * every time the period passed. */ -+ tmr_ctrl |= ((1 << FMAN_RTC_TMR_CTRL_TCLK_PERIOD_SHIFT) & -+ FMAN_RTC_TMR_CTRL_TCLK_PERIOD_MASK); -+ -+ if (cfg->invert_input_clk_phase) -+ tmr_ctrl |= FMAN_RTC_TMR_CTRL_CIPH; -+ if (cfg->invert_output_clk_phase) -+ tmr_ctrl |= FMAN_RTC_TMR_CTRL_COPH; -+ -+ for (i = 0; i < num_alarms; i++) { -+ if (cfg->alarm_polarity[i] == -+ E_FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW) -+ tmr_ctrl |= (FMAN_RTC_TMR_CTRL_ALMP1 >> i); -+ } -+ -+ for (i = 0; i < num_ext_triggers; i++) -+ if (cfg->trigger_polarity[i] == -+ E_FMAN_RTC_TRIGGER_ON_FALLING_EDGE) -+ tmr_ctrl |= (FMAN_RTC_TMR_CTRL_ETEP1 << i); -+ -+ if (!cfg->timer_slave_mode && cfg->bypass) -+ tmr_ctrl |= FMAN_RTC_TMR_CTRL_BYP; -+ -+ fman_rtc_set_timer_ctrl(regs, tmr_ctrl); -+ if (init_freq_comp) -+ fman_rtc_set_frequency_compensation(regs, freq_compensation); -+ -+ /* Clear TMR_ALARM registers */ -+ for (i = 0; i < num_alarms; i++) -+ fman_rtc_set_timer_alarm(regs, i, 0xFFFFFFFFFFFFFFFFLL); -+ -+ /* Clear TMR_TEVENT */ -+ fman_rtc_ack_event(regs, FMAN_RTC_TMR_TEVENT_ALL); -+ -+ /* Initialize TMR_TEMASK */ -+ fman_rtc_set_interrupt_mask(regs, 0); -+ -+ /* Clear TMR_FIPER registers */ -+ for (i = 0; i < num_fipers; i++) -+ fman_rtc_set_timer_fiper(regs, i, 0xFFFFFFFF); -+ -+ /* Initialize TMR_PRSC */ -+ iowrite32be(output_clock_divisor, ®s->tmr_prsc); -+ -+ /* Clear TMR_OFF */ -+ fman_rtc_set_timer_offset(regs, 0); -+} -+ -+bool fman_rtc_is_enabled(struct rtc_regs *regs) -+{ -+ return (bool)(fman_rtc_get_timer_ctrl(regs) & FMAN_RTC_TMR_CTRL_TE); -+} -+ -+void fman_rtc_enable(struct rtc_regs *regs, bool reset_clock) -+{ -+ uint32_t tmr_ctrl = fman_rtc_get_timer_ctrl(regs); -+ -+ /* TODO check that no timestamping MACs are working in this stage. */ -+ if (reset_clock) { -+ fman_rtc_set_timer_ctrl(regs, (tmr_ctrl | FMAN_RTC_TMR_CTRL_TMSR)); -+ -+ udelay(10); -+ /* Clear TMR_OFF */ -+ fman_rtc_set_timer_offset(regs, 0); -+ } -+ -+ fman_rtc_set_timer_ctrl(regs, (tmr_ctrl | FMAN_RTC_TMR_CTRL_TE)); -+} -+ -+void fman_rtc_disable(struct rtc_regs *regs) -+{ -+ fman_rtc_set_timer_ctrl(regs, (fman_rtc_get_timer_ctrl(regs) -+ & ~(FMAN_RTC_TMR_CTRL_TE))); -+} -+ -+void fman_rtc_clear_periodic_pulse(struct rtc_regs *regs, int id) -+{ -+ uint32_t tmp_reg; -+ if (id == 0) -+ tmp_reg = FMAN_RTC_TMR_TEVENT_PP1; -+ else -+ tmp_reg = FMAN_RTC_TMR_TEVENT_PP2; -+ fman_rtc_disable_interupt(regs, tmp_reg); -+ -+ tmp_reg = fman_rtc_get_timer_ctrl(regs); -+ if (tmp_reg & FMAN_RTC_TMR_CTRL_FS) -+ fman_rtc_set_timer_ctrl(regs, tmp_reg & ~FMAN_RTC_TMR_CTRL_FS); -+ -+ fman_rtc_set_timer_fiper(regs, id, 0xFFFFFFFF); -+} -+ -+void fman_rtc_clear_external_trigger(struct rtc_regs *regs, int id) -+{ -+ uint32_t tmpReg, tmp_ctrl; -+ -+ if (id == 0) -+ tmpReg = FMAN_RTC_TMR_TEVENT_ETS1; -+ else -+ tmpReg = FMAN_RTC_TMR_TEVENT_ETS2; -+ fman_rtc_disable_interupt(regs, tmpReg); -+ -+ if (id == 0) -+ tmpReg = FMAN_RTC_TMR_CTRL_PP1L; -+ else -+ tmpReg = FMAN_RTC_TMR_CTRL_PP2L; -+ tmp_ctrl = fman_rtc_get_timer_ctrl(regs); -+ if (tmp_ctrl & tmpReg) -+ fman_rtc_set_timer_ctrl(regs, tmp_ctrl & ~tmpReg); -+} -+ -+void fman_rtc_set_alarm(struct rtc_regs *regs, int id, uint32_t val, bool enable) -+{ -+ uint32_t tmpReg; -+ fman_rtc_set_timer_alarm(regs, id, val); -+ if (enable) { -+ if (id == 0) -+ tmpReg = FMAN_RTC_TMR_TEVENT_ALM1; -+ else -+ tmpReg = FMAN_RTC_TMR_TEVENT_ALM2; -+ fman_rtc_enable_interupt(regs, tmpReg); -+ } -+} -+ -+void fman_rtc_set_periodic_pulse(struct rtc_regs *regs, int id, uint32_t val, -+ bool enable) -+{ -+ uint32_t tmpReg; -+ fman_rtc_set_timer_fiper(regs, id, val); -+ if (enable) { -+ if (id == 0) -+ tmpReg = FMAN_RTC_TMR_TEVENT_PP1; -+ else -+ tmpReg = FMAN_RTC_TMR_TEVENT_PP2; -+ fman_rtc_enable_interupt(regs, tmpReg); -+ } -+} -+ -+void fman_rtc_set_ext_trigger(struct rtc_regs *regs, int id, bool enable, -+ bool use_pulse_as_input) -+{ -+ uint32_t tmpReg; -+ if (enable) { -+ if (id == 0) -+ tmpReg = FMAN_RTC_TMR_TEVENT_ETS1; -+ else -+ tmpReg = FMAN_RTC_TMR_TEVENT_ETS2; -+ fman_rtc_enable_interupt(regs, tmpReg); -+ } -+ if (use_pulse_as_input) { -+ if (id == 0) -+ tmpReg = FMAN_RTC_TMR_CTRL_PP1L; -+ else -+ tmpReg = FMAN_RTC_TMR_CTRL_PP2L; -+ fman_rtc_set_timer_ctrl(regs, fman_rtc_get_timer_ctrl(regs) | tmpReg); -+ } -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/Makefile -@@ -0,0 +1,15 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+ -+NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc -+ -+ccflags-y += -I$(NCSW_FM_INC) -+ -+obj-y += fsl-ncsw-sp.o -+ -+fsl-ncsw-sp-objs := fm_sp.o fman_sp.o ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/fm_sp.c -@@ -0,0 +1,757 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_sp.c -+ -+ @Description FM PCD Storage profile ... -+*//***************************************************************************/ -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "string_ext.h" -+#include "debug_ext.h" -+#include "net_ext.h" -+ -+#include "fm_vsp_ext.h" -+#include "fm_sp.h" -+#include "fm_common.h" -+#include "fsl_fman_sp.h" -+ -+ -+#if (DPAA_VERSION >= 11) -+static t_Error CheckParamsGeneratedInternally(t_FmVspEntry *p_FmVspEntry) -+{ -+ t_Error err = E_OK; -+ -+ if ((err = FmSpCheckIntContextParams(&p_FmVspEntry->intContext))!= E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ if ((err = FmSpCheckBufMargins(&p_FmVspEntry->bufMargins)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ return err; -+ -+} -+ -+static t_Error CheckParams(t_FmVspEntry *p_FmVspEntry) -+{ -+ t_Error err = E_OK; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->h_Fm, E_INVALID_HANDLE); -+ -+ if ((err = FmSpCheckBufPoolsParams(&p_FmVspEntry->p_FmVspEntryDriverParams->extBufPools, -+ p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools, -+ p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion)) != E_OK) -+ -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (p_FmVspEntry->p_FmVspEntryDriverParams->liodnOffset & ~FM_LIODN_OFFSET_MASK) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("liodnOffset is larger than %d", FM_LIODN_OFFSET_MASK+1)); -+ -+ err = FmVSPCheckRelativeProfile(p_FmVspEntry->h_Fm, -+ p_FmVspEntry->portType, -+ p_FmVspEntry->portId, -+ p_FmVspEntry->relativeProfileId); -+ -+ return err; -+} -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ -+/*****************************************************************************/ -+/* Inter-module API routines */ -+/*****************************************************************************/ -+void FmSpSetBufPoolsInAscOrderOfBufSizes(t_FmExtPools *p_FmExtPools, -+ uint8_t *orderedArray, -+ uint16_t *sizesArray) -+{ -+ uint16_t bufSize = 0; -+ int i=0, j=0, k=0; -+ -+ /* First we copy the external buffers pools information to an ordered local array */ -+ for (i=0;inumOfPoolsUsed;i++) -+ { -+ /* get pool size */ -+ bufSize = p_FmExtPools->extBufPool[i].size; -+ -+ /* keep sizes in an array according to poolId for direct access */ -+ sizesArray[p_FmExtPools->extBufPool[i].id] = bufSize; -+ -+ /* save poolId in an ordered array according to size */ -+ for (j=0;j<=i;j++) -+ { -+ /* this is the next free place in the array */ -+ if (j==i) -+ orderedArray[i] = p_FmExtPools->extBufPool[i].id; -+ else -+ { -+ /* find the right place for this poolId */ -+ if (bufSize < sizesArray[orderedArray[j]]) -+ { -+ /* move the poolIds one place ahead to make room for this poolId */ -+ for (k=i;k>j;k--) -+ orderedArray[k] = orderedArray[k-1]; -+ -+ /* now k==j, this is the place for the new size */ -+ orderedArray[k] = p_FmExtPools->extBufPool[i].id; -+ break; -+ } -+ } -+ } -+ } -+} -+ -+t_Error FmSpCheckBufPoolsParams(t_FmExtPools *p_FmExtPools, -+ t_FmBackupBmPools *p_FmBackupBmPools, -+ t_FmBufPoolDepletion *p_FmBufPoolDepletion) -+{ -+ -+ int i = 0, j = 0; -+ bool found; -+ uint8_t count = 0; -+ -+ if (p_FmExtPools) -+ { -+ if (p_FmExtPools->numOfPoolsUsed > FM_PORT_MAX_NUM_OF_EXT_POOLS) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numOfPoolsUsed can't be larger than %d", FM_PORT_MAX_NUM_OF_EXT_POOLS)); -+ -+ for (i=0;inumOfPoolsUsed;i++) -+ { -+ if (p_FmExtPools->extBufPool[i].id >= BM_MAX_NUM_OF_POOLS) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("extBufPools.extBufPool[%d].id can't be larger than %d", i, BM_MAX_NUM_OF_POOLS)); -+ if (!p_FmExtPools->extBufPool[i].size) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("extBufPools.extBufPool[%d].size is 0", i)); -+ } -+ } -+ if (!p_FmExtPools && (p_FmBackupBmPools || p_FmBufPoolDepletion)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("backupBmPools ot bufPoolDepletion can not be defined without external pools")); -+ -+ /* backup BM pools indication is valid only for some chip derivatives -+ (limited by the config routine) */ -+ if (p_FmBackupBmPools) -+ { -+ if (p_FmBackupBmPools->numOfBackupPools >= p_FmExtPools->numOfPoolsUsed) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("p_BackupBmPools must be smaller than extBufPools.numOfPoolsUsed")); -+ found = FALSE; -+ for (i = 0;inumOfBackupPools;i++) -+ { -+ -+ for (j=0;jnumOfPoolsUsed;j++) -+ { -+ if (p_FmBackupBmPools->poolIds[i] == p_FmExtPools->extBufPool[j].id) -+ { -+ found = TRUE; -+ break; -+ } -+ } -+ if (!found) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("All p_BackupBmPools.poolIds must be included in extBufPools.extBufPool[n].id")); -+ else -+ found = FALSE; -+ } -+ } -+ -+ /* up to extBufPools.numOfPoolsUsed pools may be defined */ -+ if (p_FmBufPoolDepletion && p_FmBufPoolDepletion->poolsGrpModeEnable) -+ { -+ if ((p_FmBufPoolDepletion->numOfPools > p_FmExtPools->numOfPoolsUsed)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufPoolDepletion.numOfPools can't be larger than %d and can't be larger than numOfPoolsUsed", FM_PORT_MAX_NUM_OF_EXT_POOLS)); -+ -+ if (!p_FmBufPoolDepletion->numOfPools) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufPoolDepletion.numOfPoolsToConsider can not be 0 when poolsGrpModeEnable=TRUE")); -+ -+ found = FALSE; -+ count = 0; -+ /* for each pool that is in poolsToConsider, check if it is defined -+ in extBufPool */ -+ for (i=0;ipoolsToConsider[i]) -+ { -+ for (j=0;jnumOfPoolsUsed;j++) -+ { -+ if (i == p_FmExtPools->extBufPool[j].id) -+ { -+ found = TRUE; -+ count++; -+ break; -+ } -+ } -+ if (!found) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Pools selected for depletion are not used.")); -+ else -+ found = FALSE; -+ } -+ } -+ /* check that the number of pools that we have checked is equal to the number announced by the user */ -+ if (count != p_FmBufPoolDepletion->numOfPools) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufPoolDepletion.numOfPools is larger than the number of pools defined.")); -+ } -+ -+ if (p_FmBufPoolDepletion && p_FmBufPoolDepletion->singlePoolModeEnable) -+ { -+ /* calculate vector for number of pools depletion */ -+ found = FALSE; -+ count = 0; -+ for (i=0;ipoolsToConsiderForSingleMode[i]) -+ { -+ for (j=0;jnumOfPoolsUsed;j++) -+ { -+ if (i == p_FmExtPools->extBufPool[j].id) -+ { -+ found = TRUE; -+ count++; -+ break; -+ } -+ } -+ if (!found) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Pools selected for depletion are not used.")); -+ else -+ found = FALSE; -+ } -+ } -+ if (!count) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("No pools defined for single buffer mode pool depletion.")); -+ } -+ -+ return E_OK; -+} -+ -+t_Error FmSpCheckIntContextParams(t_FmSpIntContextDataCopy *p_FmSpIntContextDataCopy) -+{ -+ /* Check that divisible by 16 and not larger than 240 */ -+ if (p_FmSpIntContextDataCopy->intContextOffset >MAX_INT_OFFSET) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.intContextOffset can't be larger than %d", MAX_INT_OFFSET)); -+ if (p_FmSpIntContextDataCopy->intContextOffset % OFFSET_UNITS) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.intContextOffset has to be divisible by %d", OFFSET_UNITS)); -+ -+ /* check that ic size+ic internal offset, does not exceed ic block size */ -+ if (p_FmSpIntContextDataCopy->size + p_FmSpIntContextDataCopy->intContextOffset > MAX_IC_SIZE) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.size + intContext.intContextOffset has to be smaller than %d", MAX_IC_SIZE)); -+ /* Check that divisible by 16 and not larger than 256 */ -+ if (p_FmSpIntContextDataCopy->size % OFFSET_UNITS) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.size has to be divisible by %d", OFFSET_UNITS)); -+ -+ /* Check that divisible by 16 and not larger than 4K */ -+ if (p_FmSpIntContextDataCopy->extBufOffset > MAX_EXT_OFFSET) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.extBufOffset can't be larger than %d", MAX_EXT_OFFSET)); -+ if (p_FmSpIntContextDataCopy->extBufOffset % OFFSET_UNITS) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.extBufOffset has to be divisible by %d", OFFSET_UNITS)); -+ -+ return E_OK; -+} -+ -+t_Error FmSpCheckBufMargins(t_FmSpBufMargins *p_FmSpBufMargins) -+{ -+ /* Check the margin definition */ -+ if (p_FmSpBufMargins->startMargins > MAX_EXT_BUFFER_OFFSET) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufMargins.startMargins can't be larger than %d", MAX_EXT_BUFFER_OFFSET)); -+ if (p_FmSpBufMargins->endMargins > MAX_EXT_BUFFER_OFFSET) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufMargins.endMargins can't be larger than %d", MAX_EXT_BUFFER_OFFSET)); -+ -+ return E_OK; -+} -+ -+t_Error FmSpBuildBufferStructure(t_FmSpIntContextDataCopy *p_FmSpIntContextDataCopy, -+ t_FmBufferPrefixContent *p_BufferPrefixContent, -+ t_FmSpBufMargins *p_FmSpBufMargins, -+ t_FmSpBufferOffsets *p_FmSpBufferOffsets, -+ uint8_t *internalBufferOffset) -+{ -+ uint32_t tmp; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmSpIntContextDataCopy, E_INVALID_VALUE); -+ ASSERT_COND(p_FmSpIntContextDataCopy); -+ ASSERT_COND(p_BufferPrefixContent); -+ ASSERT_COND(p_FmSpBufMargins); -+ ASSERT_COND(p_FmSpBufferOffsets); -+ -+ /* Align start of internal context data to 16 byte */ -+ p_FmSpIntContextDataCopy->extBufOffset = -+ (uint16_t)((p_BufferPrefixContent->privDataSize & (OFFSET_UNITS-1)) ? -+ ((p_BufferPrefixContent->privDataSize + OFFSET_UNITS) & ~(uint16_t)(OFFSET_UNITS-1)) : -+ p_BufferPrefixContent->privDataSize); -+ -+ /* Translate margin and intContext params to FM parameters */ -+ /* Initialize with illegal value. Later we'll set legal values. */ -+ p_FmSpBufferOffsets->prsResultOffset = (uint32_t)ILLEGAL_BASE; -+ p_FmSpBufferOffsets->timeStampOffset = (uint32_t)ILLEGAL_BASE; -+ p_FmSpBufferOffsets->hashResultOffset= (uint32_t)ILLEGAL_BASE; -+ p_FmSpBufferOffsets->pcdInfoOffset = (uint32_t)ILLEGAL_BASE; -+ -+ /* Internally the driver supports 4 options -+ 1. prsResult/timestamp/hashResult selection (in fact 8 options, but for simplicity we'll -+ relate to it as 1). -+ 2. All IC context (from AD) not including debug.*/ -+ -+ /* This 'if' covers option 2. We copy from beginning of context. */ -+ if (p_BufferPrefixContent->passAllOtherPCDInfo) -+ { -+ p_FmSpIntContextDataCopy->size = 128; /* must be aligned to 16 */ -+ /* Start copying data after 16 bytes (FD) from the beginning of the internal context */ -+ p_FmSpIntContextDataCopy->intContextOffset = 16; -+ -+ if (p_BufferPrefixContent->passAllOtherPCDInfo) -+ p_FmSpBufferOffsets->pcdInfoOffset = p_FmSpIntContextDataCopy->extBufOffset; -+ if (p_BufferPrefixContent->passPrsResult) -+ p_FmSpBufferOffsets->prsResultOffset = -+ (uint32_t)(p_FmSpIntContextDataCopy->extBufOffset + 16); -+ if (p_BufferPrefixContent->passTimeStamp) -+ p_FmSpBufferOffsets->timeStampOffset = -+ (uint32_t)(p_FmSpIntContextDataCopy->extBufOffset + 48); -+ if (p_BufferPrefixContent->passHashResult) -+ p_FmSpBufferOffsets->hashResultOffset = -+ (uint32_t)(p_FmSpIntContextDataCopy->extBufOffset + 56); -+ } -+ else -+ { -+ /* This case covers the options under 1 */ -+ /* Copy size must be in 16-byte granularity. */ -+ p_FmSpIntContextDataCopy->size = -+ (uint16_t)((p_BufferPrefixContent->passPrsResult ? 32 : 0) + -+ ((p_BufferPrefixContent->passTimeStamp || -+ p_BufferPrefixContent->passHashResult) ? 16 : 0)); -+ -+ /* Align start of internal context data to 16 byte */ -+ p_FmSpIntContextDataCopy->intContextOffset = -+ (uint8_t)(p_BufferPrefixContent->passPrsResult ? 32 : -+ ((p_BufferPrefixContent->passTimeStamp || -+ p_BufferPrefixContent->passHashResult) ? 64 : 0)); -+ -+ if (p_BufferPrefixContent->passPrsResult) -+ p_FmSpBufferOffsets->prsResultOffset = p_FmSpIntContextDataCopy->extBufOffset; -+ if (p_BufferPrefixContent->passTimeStamp) -+ p_FmSpBufferOffsets->timeStampOffset = p_BufferPrefixContent->passPrsResult ? -+ (p_FmSpIntContextDataCopy->extBufOffset + sizeof(t_FmPrsResult)) : -+ p_FmSpIntContextDataCopy->extBufOffset; -+ if (p_BufferPrefixContent->passHashResult) -+ /* If PR is not requested, whether TS is requested or not, IC will be copied from TS */ -+ p_FmSpBufferOffsets->hashResultOffset = p_BufferPrefixContent->passPrsResult ? -+ (p_FmSpIntContextDataCopy->extBufOffset + sizeof(t_FmPrsResult) + 8) : -+ p_FmSpIntContextDataCopy->extBufOffset + 8; -+ } -+ -+ if (p_FmSpIntContextDataCopy->size) -+ p_FmSpBufMargins->startMargins = -+ (uint16_t)(p_FmSpIntContextDataCopy->extBufOffset + -+ p_FmSpIntContextDataCopy->size); -+ else -+ /* No Internal Context passing, STartMargin is immediately after privateInfo */ -+ p_FmSpBufMargins->startMargins = p_BufferPrefixContent->privDataSize; -+ -+ /* save extra space for manip in both external and internal buffers */ -+ if (p_BufferPrefixContent->manipExtraSpace) -+ { -+ uint8_t extraSpace; -+#ifdef FM_CAPWAP_SUPPORT -+ if ((p_BufferPrefixContent->manipExtraSpace + CAPWAP_FRAG_EXTRA_SPACE) >= 256) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("p_BufferPrefixContent->manipExtraSpace should be less than %d", -+ 256-CAPWAP_FRAG_EXTRA_SPACE)); -+ extraSpace = (uint8_t)(p_BufferPrefixContent->manipExtraSpace + CAPWAP_FRAG_EXTRA_SPACE); -+#else -+ extraSpace = p_BufferPrefixContent->manipExtraSpace; -+#endif /* FM_CAPWAP_SUPPORT */ -+ p_FmSpBufferOffsets->manipOffset = p_FmSpBufMargins->startMargins; -+ p_FmSpBufMargins->startMargins += extraSpace; -+ *internalBufferOffset = extraSpace; -+ } -+ -+ /* align data start */ -+ tmp = (uint32_t)(p_FmSpBufMargins->startMargins % p_BufferPrefixContent->dataAlign); -+ if (tmp) -+ p_FmSpBufMargins->startMargins += (p_BufferPrefixContent->dataAlign-tmp); -+ p_FmSpBufferOffsets->dataOffset = p_FmSpBufMargins->startMargins; -+ -+ return E_OK; -+} -+/*********************** End of inter-module routines ************************/ -+ -+ -+#if (DPAA_VERSION >= 11) -+/*****************************************************************************/ -+/* API routines */ -+/*****************************************************************************/ -+t_Handle FM_VSP_Config(t_FmVspParams *p_FmVspParams) -+{ -+ t_FmVspEntry *p_FmVspEntry = NULL; -+ struct fm_storage_profile_params fm_vsp_params; -+ -+ p_FmVspEntry = (t_FmVspEntry *)XX_Malloc(sizeof(t_FmVspEntry)); -+ if (!p_FmVspEntry) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("p_StorageProfile allocation failed")); -+ return NULL; -+ } -+ memset(p_FmVspEntry, 0, sizeof(t_FmVspEntry)); -+ -+ p_FmVspEntry->p_FmVspEntryDriverParams = (t_FmVspEntryDriverParams *)XX_Malloc(sizeof(t_FmVspEntryDriverParams)); -+ if (!p_FmVspEntry->p_FmVspEntryDriverParams) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("p_StorageProfile allocation failed")); -+ XX_Free(p_FmVspEntry); -+ return NULL; -+ } -+ memset(p_FmVspEntry->p_FmVspEntryDriverParams, 0, sizeof(t_FmVspEntryDriverParams)); -+ fman_vsp_defconfig(&fm_vsp_params); -+ p_FmVspEntry->p_FmVspEntryDriverParams->dmaHeaderCacheAttr = fm_vsp_params.header_cache_attr; -+ p_FmVspEntry->p_FmVspEntryDriverParams->dmaIntContextCacheAttr = fm_vsp_params.int_context_cache_attr; -+ p_FmVspEntry->p_FmVspEntryDriverParams->dmaScatterGatherCacheAttr = fm_vsp_params.scatter_gather_cache_attr; -+ p_FmVspEntry->p_FmVspEntryDriverParams->dmaSwapData = fm_vsp_params.dma_swap_data; -+ p_FmVspEntry->p_FmVspEntryDriverParams->dmaWriteOptimize = fm_vsp_params.dma_write_optimize; -+ p_FmVspEntry->p_FmVspEntryDriverParams->noScatherGather = fm_vsp_params.no_scather_gather; -+ p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.privDataSize = DEFAULT_FM_SP_bufferPrefixContent_privDataSize; -+ p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.passPrsResult= DEFAULT_FM_SP_bufferPrefixContent_passPrsResult; -+ p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.passTimeStamp= DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp; -+ p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.passAllOtherPCDInfo -+ = DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp; -+ p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.dataAlign = DEFAULT_FM_SP_bufferPrefixContent_dataAlign; -+ p_FmVspEntry->p_FmVspEntryDriverParams->liodnOffset = p_FmVspParams->liodnOffset; -+ -+ memcpy(&p_FmVspEntry->p_FmVspEntryDriverParams->extBufPools, &p_FmVspParams->extBufPools, sizeof(t_FmExtPools)); -+ p_FmVspEntry->h_Fm = p_FmVspParams->h_Fm; -+ p_FmVspEntry->portType = p_FmVspParams->portParams.portType; -+ p_FmVspEntry->portId = p_FmVspParams->portParams.portId; -+ -+ p_FmVspEntry->relativeProfileId = p_FmVspParams->relativeProfileId; -+ -+ return p_FmVspEntry; -+} -+ -+t_Error FM_VSP_Init(t_Handle h_FmVsp) -+{ -+ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry *)h_FmVsp; -+ struct fm_storage_profile_params fm_vsp_params; -+ uint8_t orderedArray[FM_PORT_MAX_NUM_OF_EXT_POOLS]; -+ uint16_t sizesArray[BM_MAX_NUM_OF_POOLS]; -+ t_Error err; -+ uint16_t absoluteProfileId = 0; -+ int i = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams,E_INVALID_HANDLE); -+ -+ CHECK_INIT_PARAMETERS(p_FmVspEntry, CheckParams); -+ -+ memset(&orderedArray, 0, sizeof(uint8_t) * FM_PORT_MAX_NUM_OF_EXT_POOLS); -+ memset(&sizesArray, 0, sizeof(uint16_t) * BM_MAX_NUM_OF_POOLS); -+ -+ err = FmSpBuildBufferStructure(&p_FmVspEntry->intContext, -+ &p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent, -+ &p_FmVspEntry->bufMargins, -+ &p_FmVspEntry->bufferOffsets, -+ &p_FmVspEntry->internalBufferOffset); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ -+ err = CheckParamsGeneratedInternally(p_FmVspEntry); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ -+ p_FmVspEntry->p_FmSpRegsBase = -+ (struct fm_pcd_storage_profile_regs *)FmGetVSPBaseAddr(p_FmVspEntry->h_Fm); -+ if (!p_FmVspEntry->p_FmSpRegsBase) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("impossible to initialize SpRegsBase")); -+ -+ /* order external buffer pools in ascending order of buffer pools sizes */ -+ FmSpSetBufPoolsInAscOrderOfBufSizes(&(p_FmVspEntry->p_FmVspEntryDriverParams)->extBufPools, -+ orderedArray, -+ sizesArray); -+ -+ p_FmVspEntry->extBufPools.numOfPoolsUsed = -+ p_FmVspEntry->p_FmVspEntryDriverParams->extBufPools.numOfPoolsUsed; -+ for (i = 0; i < p_FmVspEntry->extBufPools.numOfPoolsUsed; i++) -+ { -+ p_FmVspEntry->extBufPools.extBufPool[i].id = orderedArray[i]; -+ p_FmVspEntry->extBufPools.extBufPool[i].size = sizesArray[orderedArray[i]]; -+ } -+ -+ /* on user responsibility to fill it according requirement */ -+ memset(&fm_vsp_params, 0, sizeof(struct fm_storage_profile_params)); -+ fm_vsp_params.dma_swap_data = p_FmVspEntry->p_FmVspEntryDriverParams->dmaSwapData; -+ fm_vsp_params.int_context_cache_attr = p_FmVspEntry->p_FmVspEntryDriverParams->dmaIntContextCacheAttr; -+ fm_vsp_params.header_cache_attr = p_FmVspEntry->p_FmVspEntryDriverParams->dmaHeaderCacheAttr; -+ fm_vsp_params.scatter_gather_cache_attr = p_FmVspEntry->p_FmVspEntryDriverParams->dmaScatterGatherCacheAttr; -+ fm_vsp_params.dma_write_optimize = p_FmVspEntry->p_FmVspEntryDriverParams->dmaWriteOptimize; -+ fm_vsp_params.liodn_offset = p_FmVspEntry->p_FmVspEntryDriverParams->liodnOffset; -+ fm_vsp_params.no_scather_gather = p_FmVspEntry->p_FmVspEntryDriverParams->noScatherGather; -+ -+ if (p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion) -+ { -+ fm_vsp_params.buf_pool_depletion.buf_pool_depletion_enabled = TRUE; -+ fm_vsp_params.buf_pool_depletion.pools_grp_mode_enable = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->poolsGrpModeEnable; -+ fm_vsp_params.buf_pool_depletion.num_pools = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->numOfPools; -+ fm_vsp_params.buf_pool_depletion.pools_to_consider = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->poolsToConsider; -+ fm_vsp_params.buf_pool_depletion.single_pool_mode_enable = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->singlePoolModeEnable; -+ fm_vsp_params.buf_pool_depletion.pools_to_consider_for_single_mode = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->poolsToConsiderForSingleMode; -+ fm_vsp_params.buf_pool_depletion.has_pfc_priorities = TRUE; -+ fm_vsp_params.buf_pool_depletion.pfc_priorities_en = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->pfcPrioritiesEn; -+ } -+ else -+ fm_vsp_params.buf_pool_depletion.buf_pool_depletion_enabled = FALSE; -+ -+ if (p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools) -+ { -+ fm_vsp_params.backup_pools.num_backup_pools = p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools->numOfBackupPools; -+ fm_vsp_params.backup_pools.pool_ids = p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools->poolIds; -+ } -+ else -+ fm_vsp_params.backup_pools.num_backup_pools = 0; -+ -+ fm_vsp_params.fm_ext_pools.num_pools_used = p_FmVspEntry->extBufPools.numOfPoolsUsed; -+ fm_vsp_params.fm_ext_pools.ext_buf_pool = (struct fman_ext_pool_params*)&p_FmVspEntry->extBufPools.extBufPool; -+ fm_vsp_params.buf_margins = (struct fman_sp_buf_margins*)&p_FmVspEntry->bufMargins; -+ fm_vsp_params.int_context = (struct fman_sp_int_context_data_copy*)&p_FmVspEntry->intContext; -+ -+ /* no check on err - it was checked earlier */ -+ FmVSPGetAbsoluteProfileId(p_FmVspEntry->h_Fm, -+ p_FmVspEntry->portType, -+ p_FmVspEntry->portId, -+ p_FmVspEntry->relativeProfileId, -+ &absoluteProfileId); -+ -+ ASSERT_COND(p_FmVspEntry->p_FmSpRegsBase); -+ ASSERT_COND(fm_vsp_params.int_context); -+ ASSERT_COND(fm_vsp_params.buf_margins); -+ ASSERT_COND((absoluteProfileId <= FM_VSP_MAX_NUM_OF_ENTRIES)); -+ -+ /* Set all registers related to VSP */ -+ fman_vsp_init(p_FmVspEntry->p_FmSpRegsBase, absoluteProfileId, &fm_vsp_params,FM_PORT_MAX_NUM_OF_EXT_POOLS, BM_MAX_NUM_OF_POOLS, FM_MAX_NUM_OF_PFC_PRIORITIES); -+ -+ p_FmVspEntry->absoluteSpId = absoluteProfileId; -+ -+ if (p_FmVspEntry->p_FmVspEntryDriverParams) -+ XX_Free(p_FmVspEntry->p_FmVspEntryDriverParams); -+ p_FmVspEntry->p_FmVspEntryDriverParams = NULL; -+ -+ return E_OK; -+} -+ -+t_Error FM_VSP_Free(t_Handle h_FmVsp) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry *)h_FmVsp; -+ SANITY_CHECK_RETURN_ERROR(h_FmVsp, E_INVALID_HANDLE); -+ XX_Free(p_FmVspEntry); -+ return E_OK; -+} -+ -+t_Error FM_VSP_ConfigBufferPrefixContent(t_Handle h_FmVsp, t_FmBufferPrefixContent *p_FmBufferPrefixContent) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE); -+ -+ memcpy(&p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent, p_FmBufferPrefixContent, sizeof(t_FmBufferPrefixContent)); -+ /* if dataAlign was not initialized by user, we return to driver's default */ -+ if (!p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.dataAlign) -+ p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.dataAlign = DEFAULT_FM_SP_bufferPrefixContent_dataAlign; -+ -+ return E_OK; -+} -+ -+t_Error FM_VSP_ConfigDmaSwapData(t_Handle h_FmVsp, e_FmDmaSwapOption swapData) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE); -+ -+ p_FmVspEntry->p_FmVspEntryDriverParams->dmaSwapData = swapData; -+ -+ return E_OK; -+} -+ -+t_Error FM_VSP_ConfigDmaIcCacheAttr(t_Handle h_FmVsp, e_FmDmaCacheOption intContextCacheAttr) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE); -+ -+ p_FmVspEntry->p_FmVspEntryDriverParams->dmaIntContextCacheAttr = intContextCacheAttr; -+ -+ return E_OK; -+} -+ -+t_Error FM_VSP_ConfigDmaHdrAttr(t_Handle h_FmVsp, e_FmDmaCacheOption headerCacheAttr) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE); -+ -+ p_FmVspEntry->p_FmVspEntryDriverParams->dmaHeaderCacheAttr = headerCacheAttr; -+ -+ return E_OK; -+} -+ -+t_Error FM_VSP_ConfigDmaScatterGatherAttr(t_Handle h_FmVsp, e_FmDmaCacheOption scatterGatherCacheAttr) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE); -+ -+ p_FmVspEntry->p_FmVspEntryDriverParams->dmaScatterGatherCacheAttr = scatterGatherCacheAttr; -+ -+ return E_OK; -+} -+ -+t_Error FM_VSP_ConfigDmaWriteOptimize(t_Handle h_FmVsp, bool optimize) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE); -+ -+ -+ p_FmVspEntry->p_FmVspEntryDriverParams->dmaWriteOptimize = optimize; -+ -+ return E_OK; -+} -+ -+t_Error FM_VSP_ConfigNoScatherGather(t_Handle h_FmVsp, bool noScatherGather) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE); -+ -+ -+ p_FmVspEntry->p_FmVspEntryDriverParams->noScatherGather = noScatherGather; -+ -+ return E_OK; -+} -+ -+t_Error FM_VSP_ConfigPoolDepletion(t_Handle h_FmVsp, t_FmBufPoolDepletion *p_BufPoolDepletion) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmVsp, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_BufPoolDepletion, E_INVALID_HANDLE); -+ -+ p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion = (t_FmBufPoolDepletion *)XX_Malloc(sizeof(t_FmBufPoolDepletion)); -+ if (!p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("p_BufPoolDepletion allocation failed")); -+ memcpy(p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion, p_BufPoolDepletion, sizeof(t_FmBufPoolDepletion)); -+ -+ return E_OK; -+} -+ -+t_Error FM_VSP_ConfigBackupPools(t_Handle h_FmVsp, t_FmBackupBmPools *p_BackupBmPools) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmVsp, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_BackupBmPools, E_INVALID_HANDLE); -+ -+ p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools = (t_FmBackupBmPools *)XX_Malloc(sizeof(t_FmBackupBmPools)); -+ if (!p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("p_BackupBmPools allocation failed")); -+ memcpy(p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools, p_BackupBmPools, sizeof(t_FmBackupBmPools)); -+ -+ return E_OK; -+} -+ -+uint32_t FM_VSP_GetBufferDataOffset(t_Handle h_FmVsp) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, 0); -+ -+ return p_FmVspEntry->bufferOffsets.dataOffset; -+} -+ -+uint8_t * FM_VSP_GetBufferICInfo(t_Handle h_FmVsp, char *p_Data) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, NULL); -+ -+ if (p_FmVspEntry->bufferOffsets.pcdInfoOffset == ILLEGAL_BASE) -+ return NULL; -+ -+ return (uint8_t *)PTR_MOVE(p_Data, p_FmVspEntry->bufferOffsets.pcdInfoOffset); -+} -+ -+t_FmPrsResult * FM_VSP_GetBufferPrsResult(t_Handle h_FmVsp, char *p_Data) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, NULL); -+ -+ if (p_FmVspEntry->bufferOffsets.prsResultOffset == ILLEGAL_BASE) -+ return NULL; -+ -+ return (t_FmPrsResult *)PTR_MOVE(p_Data, p_FmVspEntry->bufferOffsets.prsResultOffset); -+} -+ -+uint64_t * FM_VSP_GetBufferTimeStamp(t_Handle h_FmVsp, char *p_Data) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, NULL); -+ -+ if (p_FmVspEntry->bufferOffsets.timeStampOffset == ILLEGAL_BASE) -+ return NULL; -+ -+ return (uint64_t *)PTR_MOVE(p_Data, p_FmVspEntry->bufferOffsets.timeStampOffset); -+} -+ -+uint8_t * FM_VSP_GetBufferHashResult(t_Handle h_FmVsp, char *p_Data) -+{ -+ t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, NULL); -+ -+ if (p_FmVspEntry->bufferOffsets.hashResultOffset == ILLEGAL_BASE) -+ return NULL; -+ -+ return (uint8_t *)PTR_MOVE(p_Data, p_FmVspEntry->bufferOffsets.hashResultOffset); -+} -+ -+#endif /* (DPAA_VERSION >= 11) */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/fm_sp.h -@@ -0,0 +1,85 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_sp.h -+ -+ @Description FM SP ... -+*//***************************************************************************/ -+#ifndef __FM_SP_H -+#define __FM_SP_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "list_ext.h" -+ -+#include "fm_sp_common.h" -+#include "fm_common.h" -+ -+ -+#define __ERR_MODULE__ MODULE_FM_SP -+ -+typedef struct { -+ t_FmBufferPrefixContent bufferPrefixContent; -+ e_FmDmaSwapOption dmaSwapData; -+ e_FmDmaCacheOption dmaIntContextCacheAttr; -+ e_FmDmaCacheOption dmaHeaderCacheAttr; -+ e_FmDmaCacheOption dmaScatterGatherCacheAttr; -+ bool dmaWriteOptimize; -+ uint16_t liodnOffset; -+ bool noScatherGather; -+ t_FmBufPoolDepletion *p_BufPoolDepletion; -+ t_FmBackupBmPools *p_BackupBmPools; -+ t_FmExtPools extBufPools; -+} t_FmVspEntryDriverParams; -+ -+typedef struct { -+ bool valid; -+ volatile bool lock; -+ uint8_t pointedOwners; -+ uint16_t absoluteSpId; -+ uint8_t internalBufferOffset; -+ t_FmSpBufMargins bufMargins; -+ t_FmSpIntContextDataCopy intContext; -+ t_FmSpBufferOffsets bufferOffsets; -+ t_Handle h_Fm; -+ e_FmPortType portType; /**< Port type */ -+ uint8_t portId; /**< Port Id - relative to type */ -+ uint8_t relativeProfileId; -+ struct fm_pcd_storage_profile_regs *p_FmSpRegsBase; -+ t_FmExtPools extBufPools; -+ t_FmVspEntryDriverParams *p_FmVspEntryDriverParams; -+} t_FmVspEntry; -+ -+ -+#endif /* __FM_SP_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/fman_sp.c -@@ -0,0 +1,197 @@ -+/* -+ * Copyright 2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "fsl_fman_sp.h" -+ -+ -+uint32_t fman_vsp_get_statistics(struct fm_pcd_storage_profile_regs *regs, -+ uint16_t index) -+{ -+ struct fm_pcd_storage_profile_regs *sp_regs; -+ sp_regs = ®s[index]; -+ return ioread32be(&sp_regs->fm_sp_acnt); -+} -+ -+void fman_vsp_set_statistics(struct fm_pcd_storage_profile_regs *regs, -+ uint16_t index, uint32_t value) -+{ -+ struct fm_pcd_storage_profile_regs *sp_regs; -+ sp_regs = ®s[index]; -+ iowrite32be(value, &sp_regs->fm_sp_acnt); -+} -+ -+void fman_vsp_defconfig(struct fm_storage_profile_params *cfg) -+{ -+ cfg->dma_swap_data = -+ DEFAULT_FMAN_SP_DMA_SWAP_DATA; -+ cfg->int_context_cache_attr = -+ DEFAULT_FMAN_SP_DMA_INT_CONTEXT_CACHE_ATTR; -+ cfg->header_cache_attr = -+ DEFAULT_FMAN_SP_DMA_HEADER_CACHE_ATTR; -+ cfg->scatter_gather_cache_attr = -+ DEFAULT_FMAN_SP_DMA_SCATTER_GATHER_CACHE_ATTR; -+ cfg->dma_write_optimize = -+ DEFAULT_FMAN_SP_DMA_WRITE_OPTIMIZE; -+ cfg->no_scather_gather = -+ DEFAULT_FMAN_SP_NO_SCATTER_GATHER; -+} -+ -+static inline uint32_t calc_vec_dep(int max_pools, bool *pools, -+ struct fman_ext_pools *ext_buf_pools, uint32_t mask) -+{ -+ int i, j; -+ uint32_t vector = 0; -+ for (i = 0; i < max_pools; i++) -+ if (pools[i]) -+ for (j = 0; j < ext_buf_pools->num_pools_used; j++) -+ if (i == ext_buf_pools->ext_buf_pool[j].id) { -+ vector |= mask >> j; -+ break; -+ } -+ return vector; -+} -+ -+void fman_vsp_init(struct fm_pcd_storage_profile_regs *regs, -+ uint16_t index, struct fm_storage_profile_params *fm_vsp_params, -+ int port_max_num_of_ext_pools, int bm_max_num_of_pools, -+ int max_num_of_pfc_priorities) -+{ -+ int i = 0, j = 0; -+ struct fm_pcd_storage_profile_regs *sp_regs; -+ uint32_t tmp_reg, vector; -+ struct fman_ext_pools *ext_buf_pools = &fm_vsp_params->fm_ext_pools; -+ struct fman_buf_pool_depletion *buf_pool_depletion = -+ &fm_vsp_params->buf_pool_depletion; -+ struct fman_backup_bm_pools *backup_pools = -+ &fm_vsp_params->backup_pools; -+ struct fman_sp_int_context_data_copy *int_context_data_copy = -+ fm_vsp_params->int_context; -+ struct fman_sp_buf_margins *external_buffer_margins = -+ fm_vsp_params->buf_margins; -+ bool no_scather_gather = fm_vsp_params->no_scather_gather; -+ uint16_t liodn_offset = fm_vsp_params->liodn_offset; -+ -+ sp_regs = ®s[index]; -+ -+ /* fill external buffers manager pool information register*/ -+ for (i = 0; i < ext_buf_pools->num_pools_used; i++) { -+ tmp_reg = FMAN_SP_EXT_BUF_POOL_VALID | -+ FMAN_SP_EXT_BUF_POOL_EN_COUNTER; -+ tmp_reg |= ((uint32_t)ext_buf_pools->ext_buf_pool[i].id << -+ FMAN_SP_EXT_BUF_POOL_ID_SHIFT); -+ tmp_reg |= ext_buf_pools->ext_buf_pool[i].size; -+ /* functionality available only for some deriviatives -+ (limited by config) */ -+ for (j = 0; j < backup_pools->num_backup_pools; j++) -+ if (ext_buf_pools->ext_buf_pool[i].id == -+ backup_pools->pool_ids[j]) { -+ tmp_reg |= FMAN_SP_EXT_BUF_POOL_BACKUP; -+ break; -+ } -+ iowrite32be(tmp_reg, &sp_regs->fm_sp_ebmpi[i]); -+ } -+ -+ /* clear unused pools */ -+ for (i = ext_buf_pools->num_pools_used; -+ i < port_max_num_of_ext_pools; i++) -+ iowrite32be(0, &sp_regs->fm_sp_ebmpi[i]); -+ -+ /* fill pool depletion register*/ -+ tmp_reg = 0; -+ if (buf_pool_depletion->buf_pool_depletion_enabled && buf_pool_depletion->pools_grp_mode_enable) { -+ /* calculate vector for number of pools depletion */ -+ vector = calc_vec_dep(bm_max_num_of_pools, buf_pool_depletion-> -+ pools_to_consider, ext_buf_pools, 0x80000000); -+ -+ /* configure num of pools and vector for number of pools mode */ -+ tmp_reg |= (((uint32_t)buf_pool_depletion->num_pools - 1) << -+ FMAN_SP_POOL_DEP_NUM_OF_POOLS_SHIFT); -+ tmp_reg |= vector; -+ } -+ -+ if (buf_pool_depletion->buf_pool_depletion_enabled && buf_pool_depletion->single_pool_mode_enable) { -+ /* calculate vector for number of pools depletion */ -+ vector = calc_vec_dep(bm_max_num_of_pools, buf_pool_depletion-> -+ pools_to_consider_for_single_mode, -+ ext_buf_pools, 0x00000080); -+ -+ /* configure num of pools and vector for number of pools mode */ -+ tmp_reg |= vector; -+ } -+ -+ /* fill QbbPEV */ -+ if (buf_pool_depletion->buf_pool_depletion_enabled) { -+ vector = 0; -+ for (i = 0; i < max_num_of_pfc_priorities; i++) -+ if (buf_pool_depletion->pfc_priorities_en[i] == TRUE) -+ vector |= 0x00000100 << i; -+ tmp_reg |= vector; -+ } -+ iowrite32be(tmp_reg, &sp_regs->fm_sp_mpd); -+ -+ /* fill dma attributes register */ -+ tmp_reg = 0; -+ tmp_reg |= (uint32_t)fm_vsp_params->dma_swap_data << -+ FMAN_SP_DMA_ATTR_SWP_SHIFT; -+ tmp_reg |= (uint32_t)fm_vsp_params->int_context_cache_attr << -+ FMAN_SP_DMA_ATTR_IC_CACHE_SHIFT; -+ tmp_reg |= (uint32_t)fm_vsp_params->header_cache_attr << -+ FMAN_SP_DMA_ATTR_HDR_CACHE_SHIFT; -+ tmp_reg |= (uint32_t)fm_vsp_params->scatter_gather_cache_attr << -+ FMAN_SP_DMA_ATTR_SG_CACHE_SHIFT; -+ if (fm_vsp_params->dma_write_optimize) -+ tmp_reg |= FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE; -+ iowrite32be(tmp_reg, &sp_regs->fm_sp_da); -+ -+ /* IC parameters - fill internal context parameters register */ -+ tmp_reg = 0; -+ tmp_reg |= (((uint32_t)int_context_data_copy->ext_buf_offset/ -+ OFFSET_UNITS) << FMAN_SP_IC_TO_EXT_SHIFT); -+ tmp_reg |= (((uint32_t)int_context_data_copy->int_context_offset/ -+ OFFSET_UNITS) << FMAN_SP_IC_FROM_INT_SHIFT); -+ tmp_reg |= (((uint32_t)int_context_data_copy->size/OFFSET_UNITS) << -+ FMAN_SP_IC_SIZE_SHIFT); -+ iowrite32be(tmp_reg, &sp_regs->fm_sp_icp); -+ -+ /* buffer margins - fill external buffer margins register */ -+ tmp_reg = 0; -+ tmp_reg |= (((uint32_t)external_buffer_margins->start_margins) << -+ FMAN_SP_EXT_BUF_MARG_START_SHIFT); -+ tmp_reg |= (((uint32_t)external_buffer_margins->end_margins) << -+ FMAN_SP_EXT_BUF_MARG_END_SHIFT); -+ if (no_scather_gather) -+ tmp_reg |= FMAN_SP_SG_DISABLE; -+ iowrite32be(tmp_reg, &sp_regs->fm_sp_ebm); -+ -+ /* buffer margins - fill spliodn register */ -+ iowrite32be(liodn_offset, &sp_regs->fm_sp_spliodn); -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm.c -@@ -0,0 +1,5195 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm.c -+ -+ @Description FM driver routines implementation. -+*//***************************************************************************/ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "xx_ext.h" -+#include "string_ext.h" -+#include "sprint_ext.h" -+#include "debug_ext.h" -+#include "fm_muram_ext.h" -+ -+#include "fm_common.h" -+#include "fm_ipc.h" -+#include "fm.h" -+#ifndef CONFIG_FMAN_ARM -+#include -+#endif -+#include "fsl_fman.h" -+ -+ -+/****************************************/ -+/* static functions */ -+/****************************************/ -+ -+static volatile bool blockingFlag = FALSE; -+static void IpcMsgCompletionCB(t_Handle h_Fm, -+ uint8_t *p_Msg, -+ uint8_t *p_Reply, -+ uint32_t replyLength, -+ t_Error status) -+{ -+ UNUSED(h_Fm);UNUSED(p_Msg);UNUSED(p_Reply);UNUSED(replyLength);UNUSED(status); -+ blockingFlag = FALSE; -+} -+ -+static void FreeInitResources(t_Fm *p_Fm) -+{ -+ if (p_Fm->camBaseAddr) -+ FM_MURAM_FreeMem(p_Fm->h_FmMuram, UINT_TO_PTR(p_Fm->camBaseAddr)); -+ if (p_Fm->fifoBaseAddr) -+ FM_MURAM_FreeMem(p_Fm->h_FmMuram, UINT_TO_PTR(p_Fm->fifoBaseAddr)); -+ if (p_Fm->resAddr) -+ FM_MURAM_FreeMem(p_Fm->h_FmMuram, UINT_TO_PTR(p_Fm->resAddr)); -+} -+ -+static bool IsFmanCtrlCodeLoaded(t_Fm *p_Fm) -+{ -+ t_FMIramRegs *p_Iram; -+ -+ ASSERT_COND(p_Fm); -+ p_Iram = (t_FMIramRegs *)UINT_TO_PTR(p_Fm->baseAddr + FM_MM_IMEM); -+ -+ return (bool)!!(GET_UINT32(p_Iram->iready) & IRAM_READY); -+} -+ -+static t_Error CheckFmParameters(t_Fm *p_Fm) -+{ -+ if (IsFmanCtrlCodeLoaded(p_Fm) && !p_Fm->resetOnInit) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Old FMan CTRL code is loaded; FM must be reset!")); -+#if (DPAA_VERSION < 11) -+ if (!p_Fm->p_FmDriverParam->dma_axi_dbg_num_of_beats || -+ (p_Fm->p_FmDriverParam->dma_axi_dbg_num_of_beats > DMA_MODE_MAX_AXI_DBG_NUM_OF_BEATS)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("axiDbgNumOfBeats has to be in the range 1 - %d", DMA_MODE_MAX_AXI_DBG_NUM_OF_BEATS)); -+#endif /* (DPAA_VERSION < 11) */ -+ if (p_Fm->p_FmDriverParam->dma_cam_num_of_entries % DMA_CAM_UNITS) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_cam_num_of_entries has to be divisble by %d", DMA_CAM_UNITS)); -+// if (!p_Fm->p_FmDriverParam->dma_cam_num_of_entries || (p_Fm->p_FmDriverParam->dma_cam_num_of_entries > DMA_MODE_MAX_CAM_NUM_OF_ENTRIES)) -+// RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_cam_num_of_entries has to be in the range 1 - %d", DMA_MODE_MAX_CAM_NUM_OF_ENTRIES)); -+ if (p_Fm->p_FmDriverParam->dma_comm_qtsh_asrt_emer > DMA_THRESH_MAX_COMMQ) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_comm_qtsh_asrt_emer can not be larger than %d", DMA_THRESH_MAX_COMMQ)); -+ if (p_Fm->p_FmDriverParam->dma_comm_qtsh_clr_emer > DMA_THRESH_MAX_COMMQ) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_comm_qtsh_clr_emer can not be larger than %d", DMA_THRESH_MAX_COMMQ)); -+ if (p_Fm->p_FmDriverParam->dma_comm_qtsh_clr_emer >= p_Fm->p_FmDriverParam->dma_comm_qtsh_asrt_emer) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_comm_qtsh_clr_emer must be smaller than dma_comm_qtsh_asrt_emer")); -+#if (DPAA_VERSION < 11) -+ if (p_Fm->p_FmDriverParam->dma_read_buf_tsh_asrt_emer > DMA_THRESH_MAX_BUF) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_read_buf_tsh_asrt_emer can not be larger than %d", DMA_THRESH_MAX_BUF)); -+ if (p_Fm->p_FmDriverParam->dma_read_buf_tsh_clr_emer > DMA_THRESH_MAX_BUF) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_read_buf_tsh_clr_emer can not be larger than %d", DMA_THRESH_MAX_BUF)); -+ if (p_Fm->p_FmDriverParam->dma_read_buf_tsh_clr_emer >= p_Fm->p_FmDriverParam->dma_read_buf_tsh_asrt_emer) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_read_buf_tsh_clr_emer must be smaller than dma_read_buf_tsh_asrt_emer")); -+ if (p_Fm->p_FmDriverParam->dma_write_buf_tsh_asrt_emer > DMA_THRESH_MAX_BUF) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_write_buf_tsh_asrt_emer can not be larger than %d", DMA_THRESH_MAX_BUF)); -+ if (p_Fm->p_FmDriverParam->dma_write_buf_tsh_clr_emer > DMA_THRESH_MAX_BUF) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_write_buf_tsh_clr_emer can not be larger than %d", DMA_THRESH_MAX_BUF)); -+ if (p_Fm->p_FmDriverParam->dma_write_buf_tsh_clr_emer >= p_Fm->p_FmDriverParam->dma_write_buf_tsh_asrt_emer) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_write_buf_tsh_clr_emer must be smaller than dma_write_buf_tsh_asrt_emer")); -+#else /* (DPAA_VERSION >= 11) */ -+ if ((p_Fm->p_FmDriverParam->dma_dbg_cnt_mode == E_FMAN_DMA_DBG_CNT_INT_READ_EM)|| -+ (p_Fm->p_FmDriverParam->dma_dbg_cnt_mode == E_FMAN_DMA_DBG_CNT_INT_WRITE_EM) || -+ (p_Fm->p_FmDriverParam->dma_dbg_cnt_mode == E_FMAN_DMA_DBG_CNT_RAW_WAR_PROT)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_dbg_cnt_mode value not supported by this integration.")); -+ if ((p_Fm->p_FmDriverParam->dma_emergency_bus_select == FM_DMA_MURAM_READ_EMERGENCY)|| -+ (p_Fm->p_FmDriverParam->dma_emergency_bus_select == FM_DMA_MURAM_WRITE_EMERGENCY)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("emergencyBusSelect value not supported by this integration.")); -+ if (p_Fm->p_FmDriverParam->dma_stop_on_bus_error) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_stop_on_bus_error not supported by this integration.")); -+#ifdef FM_AID_MODE_NO_TNUM_SW005 -+ if (p_Fm->p_FmDriverParam->dma_aid_mode != E_FMAN_DMA_AID_OUT_PORT_ID) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_aid_mode not supported by this integration.")); -+#endif /* FM_AID_MODE_NO_TNUM_SW005 */ -+ if (p_Fm->p_FmDriverParam->dma_axi_dbg_num_of_beats) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("dma_axi_dbg_num_of_beats not supported by this integration.")); -+#endif /* (DPAA_VERSION < 11) */ -+ -+ if (!p_Fm->p_FmStateStruct->fmClkFreq) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("fmClkFreq must be set.")); -+ if (USEC_TO_CLK(p_Fm->p_FmDriverParam->dma_watchdog, p_Fm->p_FmStateStruct->fmClkFreq) > DMA_MAX_WATCHDOG) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("dma_watchdog depends on FM clock. dma_watchdog(in microseconds) * clk (in Mhz), may not exceed 0x08x", DMA_MAX_WATCHDOG)); -+ -+#if (DPAA_VERSION >= 11) -+ if ((p_Fm->partVSPBase + p_Fm->partNumOfVSPs) > FM_VSP_MAX_NUM_OF_ENTRIES) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("partVSPBase+partNumOfVSPs out of range!!!")); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ if (p_Fm->p_FmStateStruct->totalFifoSize % BMI_FIFO_UNITS) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("totalFifoSize number has to be divisible by %d", BMI_FIFO_UNITS)); -+ if (!p_Fm->p_FmStateStruct->totalFifoSize || -+ (p_Fm->p_FmStateStruct->totalFifoSize > BMI_MAX_FIFO_SIZE)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("totalFifoSize (currently defined as %d) has to be in the range of 256 to %d", -+ p_Fm->p_FmStateStruct->totalFifoSize, -+ BMI_MAX_FIFO_SIZE)); -+ if (!p_Fm->p_FmStateStruct->totalNumOfTasks || -+ (p_Fm->p_FmStateStruct->totalNumOfTasks > BMI_MAX_NUM_OF_TASKS)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("totalNumOfTasks number has to be in the range 1 - %d", BMI_MAX_NUM_OF_TASKS)); -+ -+#ifdef FM_HAS_TOTAL_DMAS -+ if (!p_Fm->p_FmStateStruct->maxNumOfOpenDmas || -+ (p_Fm->p_FmStateStruct->maxNumOfOpenDmas > BMI_MAX_NUM_OF_DMAS)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("maxNumOfOpenDmas number has to be in the range 1 - %d", BMI_MAX_NUM_OF_DMAS)); -+#endif /* FM_HAS_TOTAL_DMAS */ -+ -+ if (p_Fm->p_FmDriverParam->disp_limit_tsh > FPM_MAX_DISP_LIMIT) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("disp_limit_tsh can't be greater than %d", FPM_MAX_DISP_LIMIT)); -+ -+ if (!p_Fm->f_Exception) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceptions callback not provided")); -+ if (!p_Fm->f_BusError) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceptions callback not provided")); -+ -+#ifdef FM_NO_WATCHDOG -+ if ((p_Fm->p_FmStateStruct->revInfo.majorRev == 2) && -+ (p_Fm->p_FmDriverParam->dma_watchdog)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("watchdog!")); -+#endif /* FM_NO_WATCHDOG */ -+ -+#ifdef FM_ECC_HALT_NO_SYNC_ERRATA_10GMAC_A008 -+ if ((p_Fm->p_FmStateStruct->revInfo.majorRev < 6) && -+ (p_Fm->p_FmDriverParam->halt_on_unrecov_ecc_err)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("HaltOnEccError!")); -+#endif /* FM_ECC_HALT_NO_SYNC_ERRATA_10GMAC_A008 */ -+ -+#ifdef FM_NO_TNUM_AGING -+ if ((p_Fm->p_FmStateStruct->revInfo.majorRev != 4) && -+ (p_Fm->p_FmStateStruct->revInfo.majorRev < 6)) -+ if (p_Fm->p_FmDriverParam->tnum_aging_period) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Tnum aging!")); -+#endif /* FM_NO_TNUM_AGING */ -+ -+ /* check that user did not set revision-dependent exceptions */ -+#ifdef FM_NO_DISPATCH_RAM_ECC -+ if ((p_Fm->p_FmStateStruct->revInfo.majorRev != 4) && -+ (p_Fm->p_FmStateStruct->revInfo.majorRev < 6)) -+ if (p_Fm->userSetExceptions & FM_EX_BMI_DISPATCH_RAM_ECC) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("exception e_FM_EX_BMI_DISPATCH_RAM_ECC!")); -+#endif /* FM_NO_DISPATCH_RAM_ECC */ -+ -+#ifdef FM_QMI_NO_ECC_EXCEPTIONS -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev == 4) -+ if (p_Fm->userSetExceptions & (FM_EX_QMI_SINGLE_ECC | FM_EX_QMI_DOUBLE_ECC)) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("exception e_FM_EX_QMI_SINGLE_ECC/e_FM_EX_QMI_DOUBLE_ECC!")); -+#endif /* FM_QMI_NO_ECC_EXCEPTIONS */ -+ -+#ifdef FM_QMI_NO_SINGLE_ECC_EXCEPTION -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev >= 6) -+ if (p_Fm->userSetExceptions & FM_EX_QMI_SINGLE_ECC) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("exception e_FM_EX_QMI_SINGLE_ECC!")); -+#endif /* FM_QMI_NO_SINGLE_ECC_EXCEPTION */ -+ -+ return E_OK; -+} -+ -+ -+static void SendIpcIsr(t_Fm *p_Fm, uint32_t macEvent, uint32_t pendingReg) -+{ -+ ASSERT_COND(p_Fm->guestId == NCSW_MASTER_ID); -+ -+ if (p_Fm->intrMng[macEvent].guestId == NCSW_MASTER_ID) -+ p_Fm->intrMng[macEvent].f_Isr(p_Fm->intrMng[macEvent].h_SrcHandle); -+ -+ /* If the MAC is running on guest-partition and we have IPC session with it, -+ we inform him about the event through IPC; otherwise, we ignore the event. */ -+ else if (p_Fm->h_IpcSessions[p_Fm->intrMng[macEvent].guestId]) -+ { -+ t_Error err; -+ t_FmIpcIsr fmIpcIsr; -+ t_FmIpcMsg msg; -+ -+ memset(&msg, 0, sizeof(msg)); -+ msg.msgId = FM_GUEST_ISR; -+ fmIpcIsr.pendingReg = pendingReg; -+ fmIpcIsr.boolErr = FALSE; -+ memcpy(msg.msgBody, &fmIpcIsr, sizeof(fmIpcIsr)); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[p_Fm->intrMng[macEvent].guestId], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(fmIpcIsr), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ } -+ else -+ DBG(TRACE, ("FM Guest mode, without IPC - can't call ISR!")); -+} -+ -+static void BmiErrEvent(t_Fm *p_Fm) -+{ -+ uint32_t event; -+ struct fman_bmi_regs *bmi_rg = p_Fm->p_FmBmiRegs; -+ -+ -+ event = fman_get_bmi_err_event(bmi_rg); -+ -+ if (event & BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC) -+ p_Fm->f_Exception(p_Fm->h_App,e_FM_EX_BMI_STORAGE_PROFILE_ECC); -+ if (event & BMI_ERR_INTR_EN_LIST_RAM_ECC) -+ p_Fm->f_Exception(p_Fm->h_App,e_FM_EX_BMI_LIST_RAM_ECC); -+ if (event & BMI_ERR_INTR_EN_STATISTICS_RAM_ECC) -+ p_Fm->f_Exception(p_Fm->h_App,e_FM_EX_BMI_STATISTICS_RAM_ECC); -+ if (event & BMI_ERR_INTR_EN_DISPATCH_RAM_ECC) -+ p_Fm->f_Exception(p_Fm->h_App,e_FM_EX_BMI_DISPATCH_RAM_ECC); -+} -+ -+static void QmiErrEvent(t_Fm *p_Fm) -+{ -+ uint32_t event; -+ struct fman_qmi_regs *qmi_rg = p_Fm->p_FmQmiRegs; -+ -+ event = fman_get_qmi_err_event(qmi_rg); -+ -+ if (event & QMI_ERR_INTR_EN_DOUBLE_ECC) -+ p_Fm->f_Exception(p_Fm->h_App,e_FM_EX_QMI_DOUBLE_ECC); -+ if (event & QMI_ERR_INTR_EN_DEQ_FROM_DEF) -+ p_Fm->f_Exception(p_Fm->h_App,e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID); -+} -+ -+static void DmaErrEvent(t_Fm *p_Fm) -+{ -+ uint32_t status, com_id; -+ uint8_t tnum; -+ uint8_t hardwarePortId; -+ uint8_t relativePortId; -+ uint16_t liodn; -+ struct fman_dma_regs *dma_rg = p_Fm->p_FmDmaRegs; -+ -+ status = fman_get_dma_err_event(dma_rg); -+ -+ if (status & DMA_STATUS_BUS_ERR) -+ { -+ com_id = fman_get_dma_com_id(dma_rg); -+ hardwarePortId = (uint8_t)(((com_id & DMA_TRANSFER_PORTID_MASK) >> DMA_TRANSFER_PORTID_SHIFT)); -+ ASSERT_COND(IN_RANGE(1, hardwarePortId, 63)); -+ HW_PORT_ID_TO_SW_PORT_ID(relativePortId, hardwarePortId); -+ tnum = (uint8_t)((com_id & DMA_TRANSFER_TNUM_MASK) >> DMA_TRANSFER_TNUM_SHIFT); -+ liodn = (uint16_t)(com_id & DMA_TRANSFER_LIODN_MASK); -+ ASSERT_COND(p_Fm->p_FmStateStruct->portsTypes[hardwarePortId] != e_FM_PORT_TYPE_DUMMY); -+ p_Fm->f_BusError(p_Fm->h_App, -+ p_Fm->p_FmStateStruct->portsTypes[hardwarePortId], -+ relativePortId, -+ fman_get_dma_addr(dma_rg), -+ tnum, -+ liodn); -+ } -+ if (status & DMA_STATUS_FM_SPDAT_ECC) -+ p_Fm->f_Exception(p_Fm->h_App, e_FM_EX_DMA_SINGLE_PORT_ECC); -+ if (status & DMA_STATUS_READ_ECC) -+ p_Fm->f_Exception(p_Fm->h_App, e_FM_EX_DMA_READ_ECC); -+ if (status & DMA_STATUS_SYSTEM_WRITE_ECC) -+ p_Fm->f_Exception(p_Fm->h_App, e_FM_EX_DMA_SYSTEM_WRITE_ECC); -+ if (status & DMA_STATUS_FM_WRITE_ECC) -+ p_Fm->f_Exception(p_Fm->h_App, e_FM_EX_DMA_FM_WRITE_ECC); -+ } -+ -+static void FpmErrEvent(t_Fm *p_Fm) -+{ -+ uint32_t event; -+ struct fman_fpm_regs *fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ event = fman_get_fpm_err_event(fpm_rg); -+ -+ if ((event & FPM_EV_MASK_DOUBLE_ECC) && (event & FPM_EV_MASK_DOUBLE_ECC_EN)) -+ p_Fm->f_Exception(p_Fm->h_App,e_FM_EX_FPM_DOUBLE_ECC); -+ if ((event & FPM_EV_MASK_STALL) && (event & FPM_EV_MASK_STALL_EN)) -+ p_Fm->f_Exception(p_Fm->h_App,e_FM_EX_FPM_STALL_ON_TASKS); -+ if ((event & FPM_EV_MASK_SINGLE_ECC) && (event & FPM_EV_MASK_SINGLE_ECC_EN)) -+ p_Fm->f_Exception(p_Fm->h_App,e_FM_EX_FPM_SINGLE_ECC); -+} -+ -+static void MuramErrIntr(t_Fm *p_Fm) -+{ -+ uint32_t event; -+ struct fman_fpm_regs *fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ event = fman_get_muram_err_event(fpm_rg); -+ -+ if (event & FPM_RAM_MURAM_ECC) -+ p_Fm->f_Exception(p_Fm->h_App, e_FM_EX_MURAM_ECC); -+} -+ -+static void IramErrIntr(t_Fm *p_Fm) -+{ -+ uint32_t event; -+ struct fman_fpm_regs *fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ event = fman_get_iram_err_event(fpm_rg); -+ -+ if (event & FPM_RAM_IRAM_ECC) -+ p_Fm->f_Exception(p_Fm->h_App, e_FM_EX_IRAM_ECC); -+} -+ -+static void QmiEvent(t_Fm *p_Fm) -+{ -+ uint32_t event; -+ struct fman_qmi_regs *qmi_rg = p_Fm->p_FmQmiRegs; -+ -+ event = fman_get_qmi_event(qmi_rg); -+ -+ if (event & QMI_INTR_EN_SINGLE_ECC) -+ p_Fm->f_Exception(p_Fm->h_App,e_FM_EX_QMI_SINGLE_ECC); -+} -+ -+static void UnimplementedIsr(t_Handle h_Arg) -+{ -+ UNUSED(h_Arg); -+ -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Unimplemented ISR!")); -+} -+ -+static void UnimplementedFmanCtrlIsr(t_Handle h_Arg, uint32_t event) -+{ -+ UNUSED(h_Arg); UNUSED(event); -+ -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Unimplemented FmCtl ISR!")); -+} -+ -+static void EnableTimeStamp(t_Fm *p_Fm) -+{ -+ struct fman_fpm_regs *fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ ASSERT_COND(p_Fm->p_FmStateStruct); -+ ASSERT_COND(p_Fm->p_FmStateStruct->count1MicroBit); -+ -+ fman_enable_time_stamp(fpm_rg, p_Fm->p_FmStateStruct->count1MicroBit, p_Fm->p_FmStateStruct->fmClkFreq); -+ -+ p_Fm->p_FmStateStruct->enabledTimeStamp = TRUE; -+} -+ -+static t_Error ClearIRam(t_Fm *p_Fm) -+{ -+ t_FMIramRegs *p_Iram; -+ int i; -+ int iram_size; -+ -+ ASSERT_COND(p_Fm); -+ p_Iram = (t_FMIramRegs *)UINT_TO_PTR(p_Fm->baseAddr + FM_MM_IMEM); -+ iram_size = FM_IRAM_SIZE(p_Fm->p_FmStateStruct->revInfo.majorRev,p_Fm->p_FmStateStruct->revInfo.minorRev); -+ -+ /* Enable the auto-increment */ -+ WRITE_UINT32(p_Iram->iadd, IRAM_IADD_AIE); -+ while (GET_UINT32(p_Iram->iadd) != IRAM_IADD_AIE) ; -+ -+ for (i=0; i < (iram_size/4); i++) -+ WRITE_UINT32(p_Iram->idata, 0xffffffff); -+ -+ WRITE_UINT32(p_Iram->iadd, iram_size - 4); -+ CORE_MemoryBarrier(); -+ while (GET_UINT32(p_Iram->idata) != 0xffffffff) ; -+ -+ return E_OK; -+} -+ -+static t_Error LoadFmanCtrlCode(t_Fm *p_Fm) -+{ -+ t_FMIramRegs *p_Iram; -+ int i; -+ uint32_t tmp; -+ uint8_t compTo16; -+ -+ ASSERT_COND(p_Fm); -+ p_Iram = (t_FMIramRegs *)UINT_TO_PTR(p_Fm->baseAddr + FM_MM_IMEM); -+ -+ /* Enable the auto-increment */ -+ WRITE_UINT32(p_Iram->iadd, IRAM_IADD_AIE); -+ while (GET_UINT32(p_Iram->iadd) != IRAM_IADD_AIE) ; -+ -+ for (i=0; i < (p_Fm->firmware.size / 4); i++) -+ WRITE_UINT32(p_Iram->idata, p_Fm->firmware.p_Code[i]); -+ -+ compTo16 = (uint8_t)(p_Fm->firmware.size % 16); -+ if (compTo16) -+ for (i=0; i < ((16-compTo16) / 4); i++) -+ WRITE_UINT32(p_Iram->idata, 0xffffffff); -+ -+ WRITE_UINT32(p_Iram->iadd,p_Fm->firmware.size-4); -+ while (GET_UINT32(p_Iram->iadd) != (p_Fm->firmware.size-4)) ; -+ -+ /* verify that writing has completed */ -+ while (GET_UINT32(p_Iram->idata) != p_Fm->firmware.p_Code[(p_Fm->firmware.size / 4)-1]) ; -+ -+ if (p_Fm->fwVerify) -+ { -+ WRITE_UINT32(p_Iram->iadd, IRAM_IADD_AIE); -+ while (GET_UINT32(p_Iram->iadd) != IRAM_IADD_AIE) ; -+ for (i=0; i < (p_Fm->firmware.size / 4); i++) -+ { -+ tmp = GET_UINT32(p_Iram->idata); -+ if (tmp != p_Fm->firmware.p_Code[i]) -+ RETURN_ERROR(MAJOR, E_WRITE_FAILED, -+ ("UCode write error : write 0x%x, read 0x%x", -+ p_Fm->firmware.p_Code[i],tmp)); -+ } -+ WRITE_UINT32(p_Iram->iadd, 0x0); -+ } -+ -+ /* Enable patch from IRAM */ -+ WRITE_UINT32(p_Iram->iready, IRAM_READY); -+ XX_UDelay(1000); -+ -+ DBG(INFO, ("FMan-Controller code (ver %d.%d.%d) loaded to IRAM.", -+ ((uint16_t *)p_Fm->firmware.p_Code)[2], -+ ((uint8_t *)p_Fm->firmware.p_Code)[6], -+ ((uint8_t *)p_Fm->firmware.p_Code)[7])); -+ -+ return E_OK; -+} -+ -+#ifdef FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 -+static t_Error FwNotResetErratumBugzilla6173WA(t_Fm *p_Fm) -+{ -+ t_FMIramRegs *p_Iram = (t_FMIramRegs *)UINT_TO_PTR(p_Fm->baseAddr + FM_MM_IMEM); -+ uint32_t tmpReg; -+ uint32_t savedSpliodn[63]; -+ -+ /* write to IRAM first location the debug instruction */ -+ WRITE_UINT32(p_Iram->iadd, 0); -+ while (GET_UINT32(p_Iram->iadd) != 0) ; -+ WRITE_UINT32(p_Iram->idata, FM_FW_DEBUG_INSTRUCTION); -+ -+ WRITE_UINT32(p_Iram->iadd, 0); -+ while (GET_UINT32(p_Iram->iadd) != 0) ; -+ while (GET_UINT32(p_Iram->idata) != FM_FW_DEBUG_INSTRUCTION) ; -+ -+ /* Enable patch from IRAM */ -+ WRITE_UINT32(p_Iram->iready, IRAM_READY); -+ CORE_MemoryBarrier(); -+ XX_UDelay(100); -+ IO2MemCpy32((uint8_t *)savedSpliodn, -+ (uint8_t *)p_Fm->p_FmBmiRegs->fmbm_spliodn, -+ 63*sizeof(uint32_t)); -+ -+ /* reset FMAN */ -+ WRITE_UINT32(p_Fm->p_FmFpmRegs->fm_rstc, FPM_RSTC_FM_RESET); -+ CORE_MemoryBarrier(); -+ XX_UDelay(100); -+ -+ /* verify breakpoint debug status register */ -+ tmpReg = GET_UINT32(*(uint32_t *)UINT_TO_PTR(p_Fm->baseAddr + FM_DEBUG_STATUS_REGISTER_OFFSET)); -+ if (!tmpReg) -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Invalid debug status register value is '0'")); -+ -+ /*************************************/ -+ /* Load FMan-Controller code to IRAM */ -+ /*************************************/ -+ ClearIRam(p_Fm); -+ if (p_Fm->firmware.p_Code && -+ (LoadFmanCtrlCode(p_Fm) != E_OK)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ XX_UDelay(100); -+ -+ /* reset FMAN again to start the microcode */ -+ WRITE_UINT32(p_Fm->p_FmFpmRegs->fm_rstc, FPM_RSTC_FM_RESET); -+ CORE_MemoryBarrier(); -+ XX_UDelay(100); -+ Mem2IOCpy32((uint8_t *)p_Fm->p_FmBmiRegs->fmbm_spliodn, -+ (uint8_t *)savedSpliodn, -+ 63*sizeof(uint32_t)); -+ -+ if (fman_is_qmi_halt_not_busy_state(p_Fm->p_FmQmiRegs)) -+ { -+ fman_resume(p_Fm->p_FmFpmRegs); -+ CORE_MemoryBarrier(); -+ XX_UDelay(100); -+ } -+ -+ return E_OK; -+} -+#endif /* FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 */ -+ -+static void GuestErrorIsr(t_Fm *p_Fm, uint32_t pending) -+{ -+#define FM_G_CALL_1G_MAC_ERR_ISR(_id) \ -+do { \ -+ p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_ERR_1G_MAC0+_id)].f_Isr(p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_ERR_1G_MAC0+_id)].h_SrcHandle);\ -+} while (0) -+#define FM_G_CALL_10G_MAC_ERR_ISR(_id) \ -+do { \ -+ p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_ERR_10G_MAC0+_id)].f_Isr(p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_ERR_10G_MAC0+_id)].h_SrcHandle);\ -+} while (0) -+ -+ /* error interrupts */ -+ if (pending & ERR_INTR_EN_1G_MAC0) -+ FM_G_CALL_1G_MAC_ERR_ISR(0); -+ if (pending & ERR_INTR_EN_1G_MAC1) -+ FM_G_CALL_1G_MAC_ERR_ISR(1); -+ if (pending & ERR_INTR_EN_1G_MAC2) -+ FM_G_CALL_1G_MAC_ERR_ISR(2); -+ if (pending & ERR_INTR_EN_1G_MAC3) -+ FM_G_CALL_1G_MAC_ERR_ISR(3); -+ if (pending & ERR_INTR_EN_1G_MAC4) -+ FM_G_CALL_1G_MAC_ERR_ISR(4); -+ if (pending & ERR_INTR_EN_1G_MAC5) -+ FM_G_CALL_1G_MAC_ERR_ISR(5); -+ if (pending & ERR_INTR_EN_1G_MAC6) -+ FM_G_CALL_1G_MAC_ERR_ISR(6); -+ if (pending & ERR_INTR_EN_1G_MAC7) -+ FM_G_CALL_1G_MAC_ERR_ISR(7); -+ if (pending & ERR_INTR_EN_10G_MAC0) -+ FM_G_CALL_10G_MAC_ERR_ISR(0); -+ if (pending & ERR_INTR_EN_10G_MAC1) -+ FM_G_CALL_10G_MAC_ERR_ISR(1); -+} -+ -+static void GuestEventIsr(t_Fm *p_Fm, uint32_t pending) -+{ -+#define FM_G_CALL_1G_MAC_ISR(_id) \ -+do { \ -+ p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_1G_MAC0+_id)].f_Isr(p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_1G_MAC0+_id)].h_SrcHandle);\ -+} while (0) -+#define FM_G_CALL_10G_MAC_ISR(_id) \ -+do { \ -+ p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_10G_MAC0+_id)].f_Isr(p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_10G_MAC0+_id)].h_SrcHandle);\ -+} while (0) -+ -+ if (pending & INTR_EN_1G_MAC0) -+ FM_G_CALL_1G_MAC_ISR(0); -+ if (pending & INTR_EN_1G_MAC1) -+ FM_G_CALL_1G_MAC_ISR(1); -+ if (pending & INTR_EN_1G_MAC2) -+ FM_G_CALL_1G_MAC_ISR(2); -+ if (pending & INTR_EN_1G_MAC3) -+ FM_G_CALL_1G_MAC_ISR(3); -+ if (pending & INTR_EN_1G_MAC4) -+ FM_G_CALL_1G_MAC_ISR(4); -+ if (pending & INTR_EN_1G_MAC5) -+ FM_G_CALL_1G_MAC_ISR(5); -+ if (pending & INTR_EN_1G_MAC6) -+ FM_G_CALL_1G_MAC_ISR(6); -+ if (pending & INTR_EN_1G_MAC7) -+ FM_G_CALL_1G_MAC_ISR(7); -+ if (pending & INTR_EN_10G_MAC0) -+ FM_G_CALL_10G_MAC_ISR(0); -+ if (pending & INTR_EN_10G_MAC1) -+ FM_G_CALL_10G_MAC_ISR(1); -+ if (pending & INTR_EN_TMR) -+ p_Fm->intrMng[e_FM_EV_TMR].f_Isr(p_Fm->intrMng[e_FM_EV_TMR].h_SrcHandle); -+} -+ -+#if (DPAA_VERSION >= 11) -+static t_Error SetVSPWindow(t_Handle h_Fm, -+ uint8_t hardwarePortId, -+ uint8_t baseStorageProfile, -+ uint8_t log2NumOfProfiles) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_Fm; -+ -+ ASSERT_COND(h_Fm); -+ ASSERT_COND(IN_RANGE(1, hardwarePortId, 63)); -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ !p_Fm->p_FmBmiRegs && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_FmIpcVspSetPortWindow fmIpcVspSetPortWindow; -+ t_FmIpcMsg msg; -+ t_Error err = E_OK; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&fmIpcVspSetPortWindow, 0, sizeof(t_FmIpcVspSetPortWindow)); -+ fmIpcVspSetPortWindow.hardwarePortId = hardwarePortId; -+ fmIpcVspSetPortWindow.baseStorageProfile = baseStorageProfile; -+ fmIpcVspSetPortWindow.log2NumOfProfiles = log2NumOfProfiles; -+ msg.msgId = FM_VSP_SET_PORT_WINDOW; -+ memcpy(msg.msgBody, &fmIpcVspSetPortWindow, sizeof(t_FmIpcVspSetPortWindow)); -+ -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ return E_OK; -+ } -+ else if (!p_Fm->p_FmBmiRegs) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("Either IPC or 'baseAddress' is required!")); -+ -+ fman_set_vsp_window(p_Fm->p_FmBmiRegs, -+ hardwarePortId, -+ baseStorageProfile, -+ log2NumOfProfiles); -+ -+ return E_OK; -+} -+ -+static uint8_t AllocVSPsForPartition(t_Handle h_Fm, uint8_t base, uint8_t numOfProfiles, uint8_t guestId) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_Fm; -+ uint8_t profilesFound = 0; -+ int i = 0; -+ uint32_t intFlags; -+ -+ if (!numOfProfiles) -+ return E_OK; -+ -+ if ((numOfProfiles > FM_VSP_MAX_NUM_OF_ENTRIES) || -+ (base + numOfProfiles > FM_VSP_MAX_NUM_OF_ENTRIES)) -+ return (uint8_t)ILLEGAL_BASE; -+ -+ if (p_Fm->h_IpcSessions[0]) -+ { -+ t_FmIpcResourceAllocParams ipcAllocParams; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ t_Error err; -+ uint32_t replyLength; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ memset(&ipcAllocParams, 0, sizeof(t_FmIpcResourceAllocParams)); -+ ipcAllocParams.guestId = p_Fm->guestId; -+ ipcAllocParams.num = p_Fm->partNumOfVSPs; -+ ipcAllocParams.base = p_Fm->partVSPBase; -+ msg.msgId = FM_VSP_ALLOC; -+ memcpy(msg.msgBody, &ipcAllocParams, sizeof(t_FmIpcResourceAllocParams)); -+ replyLength = sizeof(uint32_t) + sizeof(uint8_t); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(t_FmIpcResourceAllocParams), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL); -+ if ((err != E_OK) || -+ (replyLength != (sizeof(uint32_t) + sizeof(uint8_t)))) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ else -+ memcpy((uint8_t*)&p_Fm->partVSPBase, reply.replyBody, sizeof(uint8_t)); -+ if (p_Fm->partVSPBase == (uint8_t)(ILLEGAL_BASE)) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ if (p_Fm->guestId != NCSW_MASTER_ID) -+ { -+ DBG(WARNING, ("FM Guest mode, without IPC - can't validate VSP range!")); -+ return (uint8_t)ILLEGAL_BASE; -+ } -+ -+ intFlags = XX_LockIntrSpinlock(p_Fm->h_Spinlock); -+ for (i = base; i < base + numOfProfiles; i++) -+ if (p_Fm->p_FmSp->profiles[i].profilesMng.ownerId == (uint8_t)ILLEGAL_BASE) -+ profilesFound++; -+ else -+ break; -+ -+ if (profilesFound == numOfProfiles) -+ for (i = base; ip_FmSp->profiles[i].profilesMng.ownerId = guestId; -+ else -+ { -+ XX_UnlockIntrSpinlock(p_Fm->h_Spinlock, intFlags); -+ return (uint8_t)ILLEGAL_BASE; -+ } -+ XX_UnlockIntrSpinlock(p_Fm->h_Spinlock, intFlags); -+ -+ return base; -+} -+ -+static void FreeVSPsForPartition(t_Handle h_Fm, uint8_t base, uint8_t numOfProfiles, uint8_t guestId) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_Fm; -+ int i = 0; -+ -+ ASSERT_COND(p_Fm); -+ -+ if (p_Fm->h_IpcSessions[0]) -+ { -+ t_FmIpcResourceAllocParams ipcAllocParams; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength; -+ t_Error err; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ memset(&ipcAllocParams, 0, sizeof(t_FmIpcResourceAllocParams)); -+ ipcAllocParams.guestId = p_Fm->guestId; -+ ipcAllocParams.num = p_Fm->partNumOfVSPs; -+ ipcAllocParams.base = p_Fm->partVSPBase; -+ msg.msgId = FM_VSP_FREE; -+ memcpy(msg.msgBody, &ipcAllocParams, sizeof(t_FmIpcResourceAllocParams)); -+ replyLength = sizeof(uint32_t) + sizeof(uint8_t); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(t_FmIpcResourceAllocParams), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ return; -+ } -+ if (p_Fm->guestId != NCSW_MASTER_ID) -+ { -+ DBG(WARNING, ("FM Guest mode, without IPC - can't validate VSP range!")); -+ return; -+ } -+ -+ ASSERT_COND(p_Fm->p_FmSp); -+ -+ for (i=base; ip_FmSp->profiles[i].profilesMng.ownerId == guestId) -+ p_Fm->p_FmSp->profiles[i].profilesMng.ownerId = (uint8_t)ILLEGAL_BASE; -+ else -+ DBG(WARNING, ("Request for freeing storage profile window which wasn't allocated to this partition")); -+ } -+} -+#endif /* (DPAA_VERSION >= 11) */ -+ -+static t_Error FmGuestHandleIpcMsgCB(t_Handle h_Fm, -+ uint8_t *p_Msg, -+ uint32_t msgLength, -+ uint8_t *p_Reply, -+ uint32_t *p_ReplyLength) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ t_FmIpcMsg *p_IpcMsg = (t_FmIpcMsg*)p_Msg; -+ -+ UNUSED(p_Reply); -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((msgLength > sizeof(uint32_t)), E_INVALID_VALUE); -+ -+#ifdef DISABLE_SANITY_CHECKS -+ UNUSED(msgLength); -+#endif /* DISABLE_SANITY_CHECKS */ -+ -+ ASSERT_COND(p_Msg); -+ -+ *p_ReplyLength = 0; -+ -+ switch (p_IpcMsg->msgId) -+ { -+ case (FM_GUEST_ISR): -+ { -+ t_FmIpcIsr ipcIsr; -+ -+ memcpy((uint8_t*)&ipcIsr, p_IpcMsg->msgBody, sizeof(t_FmIpcIsr)); -+ if (ipcIsr.boolErr) -+ GuestErrorIsr(p_Fm, ipcIsr.pendingReg); -+ else -+ GuestEventIsr(p_Fm, ipcIsr.pendingReg); -+ break; -+ } -+ default: -+ *p_ReplyLength = 0; -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, ("command not found!!!")); -+ } -+ return E_OK; -+} -+ -+static t_Error FmHandleIpcMsgCB(t_Handle h_Fm, -+ uint8_t *p_Msg, -+ uint32_t msgLength, -+ uint8_t *p_Reply, -+ uint32_t *p_ReplyLength) -+{ -+ t_Error err; -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ t_FmIpcMsg *p_IpcMsg = (t_FmIpcMsg*)p_Msg; -+ t_FmIpcReply *p_IpcReply = (t_FmIpcReply*)p_Reply; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((msgLength >= sizeof(uint32_t)), E_INVALID_VALUE); -+ -+#ifdef DISABLE_SANITY_CHECKS -+ UNUSED(msgLength); -+#endif /* DISABLE_SANITY_CHECKS */ -+ -+ ASSERT_COND(p_IpcMsg); -+ -+ memset(p_IpcReply, 0, (sizeof(uint8_t) * FM_IPC_MAX_REPLY_SIZE)); -+ *p_ReplyLength = 0; -+ -+ switch (p_IpcMsg->msgId) -+ { -+ case (FM_GET_SET_PORT_PARAMS): -+ { -+ t_FmIpcPortInInitParams ipcInitParams; -+ t_FmInterModulePortInitParams initParams; -+ t_FmIpcPortOutInitParams ipcOutInitParams; -+ -+ memcpy((uint8_t*)&ipcInitParams, p_IpcMsg->msgBody, sizeof(t_FmIpcPortInInitParams)); -+ initParams.hardwarePortId = ipcInitParams.hardwarePortId; -+ initParams.portType = (e_FmPortType)ipcInitParams.enumPortType; -+ initParams.independentMode = (bool)(ipcInitParams.boolIndependentMode); -+ initParams.liodnOffset = ipcInitParams.liodnOffset; -+ initParams.numOfTasks = ipcInitParams.numOfTasks; -+ initParams.numOfExtraTasks = ipcInitParams.numOfExtraTasks; -+ initParams.numOfOpenDmas = ipcInitParams.numOfOpenDmas; -+ initParams.numOfExtraOpenDmas = ipcInitParams.numOfExtraOpenDmas; -+ initParams.sizeOfFifo = ipcInitParams.sizeOfFifo; -+ initParams.extraSizeOfFifo = ipcInitParams.extraSizeOfFifo; -+ initParams.deqPipelineDepth = ipcInitParams.deqPipelineDepth; -+ initParams.maxFrameLength = ipcInitParams.maxFrameLength; -+ initParams.liodnBase = ipcInitParams.liodnBase; -+ -+ p_IpcReply->error = (uint32_t)FmGetSetPortParams(h_Fm, &initParams); -+ -+ ipcOutInitParams.ipcPhysAddr.high = initParams.fmMuramPhysBaseAddr.high; -+ ipcOutInitParams.ipcPhysAddr.low = initParams.fmMuramPhysBaseAddr.low; -+ ipcOutInitParams.sizeOfFifo = initParams.sizeOfFifo; -+ ipcOutInitParams.extraSizeOfFifo = initParams.extraSizeOfFifo; -+ ipcOutInitParams.numOfTasks = initParams.numOfTasks; -+ ipcOutInitParams.numOfExtraTasks = initParams.numOfExtraTasks; -+ ipcOutInitParams.numOfOpenDmas = initParams.numOfOpenDmas; -+ ipcOutInitParams.numOfExtraOpenDmas = initParams.numOfExtraOpenDmas; -+ memcpy(p_IpcReply->replyBody, (uint8_t*)&ipcOutInitParams, sizeof(ipcOutInitParams)); -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(t_FmIpcPortOutInitParams); -+ break; -+ } -+ case (FM_SET_SIZE_OF_FIFO): -+ { -+ t_FmIpcPortRsrcParams ipcPortRsrcParams; -+ -+ memcpy((uint8_t*)&ipcPortRsrcParams, p_IpcMsg->msgBody, sizeof(t_FmIpcPortRsrcParams)); -+ p_IpcReply->error = (uint32_t)FmSetSizeOfFifo(h_Fm, -+ ipcPortRsrcParams.hardwarePortId, -+ &ipcPortRsrcParams.val, -+ &ipcPortRsrcParams.extra, -+ (bool)ipcPortRsrcParams.boolInitialConfig); -+ *p_ReplyLength = sizeof(uint32_t); -+ break; -+ } -+ case (FM_SET_NUM_OF_TASKS): -+ { -+ t_FmIpcPortRsrcParams ipcPortRsrcParams; -+ -+ memcpy((uint8_t*)&ipcPortRsrcParams, p_IpcMsg->msgBody, sizeof(t_FmIpcPortRsrcParams)); -+ p_IpcReply->error = (uint32_t)FmSetNumOfTasks(h_Fm, ipcPortRsrcParams.hardwarePortId, -+ (uint8_t*)&ipcPortRsrcParams.val, -+ (uint8_t*)&ipcPortRsrcParams.extra, -+ (bool)ipcPortRsrcParams.boolInitialConfig); -+ *p_ReplyLength = sizeof(uint32_t); -+ break; -+ } -+ case (FM_SET_NUM_OF_OPEN_DMAS): -+ { -+ t_FmIpcPortRsrcParams ipcPortRsrcParams; -+ -+ memcpy((uint8_t*)&ipcPortRsrcParams, p_IpcMsg->msgBody, sizeof(t_FmIpcPortRsrcParams)); -+ p_IpcReply->error = (uint32_t)FmSetNumOfOpenDmas(h_Fm, ipcPortRsrcParams.hardwarePortId, -+ (uint8_t*)&ipcPortRsrcParams.val, -+ (uint8_t*)&ipcPortRsrcParams.extra, -+ (bool)ipcPortRsrcParams.boolInitialConfig); -+ *p_ReplyLength = sizeof(uint32_t); -+ break; -+ } -+ case (FM_RESUME_STALLED_PORT): -+ *p_ReplyLength = sizeof(uint32_t); -+ p_IpcReply->error = (uint32_t)FmResumeStalledPort(h_Fm, p_IpcMsg->msgBody[0]); -+ break; -+ case (FM_MASTER_IS_ALIVE): -+ { -+ uint8_t guestId = p_IpcMsg->msgBody[0]; -+ /* build the FM master partition IPC address */ -+ memset(p_Fm->fmIpcHandlerModuleName[guestId], 0, (sizeof(char)) * MODULE_NAME_SIZE); -+ if (Sprint (p_Fm->fmIpcHandlerModuleName[guestId], "FM_%d_%d",p_Fm->p_FmStateStruct->fmId, guestId) != (guestId<10 ? 6:7)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Sprint failed")); -+ p_Fm->h_IpcSessions[guestId] = XX_IpcInitSession(p_Fm->fmIpcHandlerModuleName[guestId], p_Fm->fmModuleName); -+ if (p_Fm->h_IpcSessions[guestId] == NULL) -+ RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, ("FM Master IPC session for guest %d", guestId)); -+ *(uint8_t*)(p_IpcReply->replyBody) = 1; -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(uint8_t); -+ break; -+ } -+ case (FM_IS_PORT_STALLED): -+ { -+ bool tmp; -+ -+ p_IpcReply->error = (uint32_t)FmIsPortStalled(h_Fm, p_IpcMsg->msgBody[0], &tmp); -+ *(uint8_t*)(p_IpcReply->replyBody) = (uint8_t)tmp; -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(uint8_t); -+ break; -+ } -+ case (FM_RESET_MAC): -+ { -+ t_FmIpcMacParams ipcMacParams; -+ -+ memcpy((uint8_t*)&ipcMacParams, p_IpcMsg->msgBody, sizeof(t_FmIpcMacParams)); -+ p_IpcReply->error = (uint32_t)FmResetMac(p_Fm, -+ (e_FmMacType)(ipcMacParams.enumType), -+ ipcMacParams.id); -+ *p_ReplyLength = sizeof(uint32_t); -+ break; -+ } -+ case (FM_SET_MAC_MAX_FRAME): -+ { -+ t_FmIpcMacMaxFrameParams ipcMacMaxFrameParams; -+ -+ memcpy((uint8_t*)&ipcMacMaxFrameParams, p_IpcMsg->msgBody, sizeof(t_FmIpcMacMaxFrameParams)); -+ err = FmSetMacMaxFrame(p_Fm, -+ (e_FmMacType)(ipcMacMaxFrameParams.macParams.enumType), -+ ipcMacMaxFrameParams.macParams.id, -+ ipcMacMaxFrameParams.maxFrameLength); -+ if (err != E_OK) -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ break; -+ } -+#if (DPAA_VERSION >= 11) -+ case (FM_VSP_ALLOC) : -+ { -+ t_FmIpcResourceAllocParams ipcAllocParams; -+ uint8_t vspBase; -+ memcpy(&ipcAllocParams, p_IpcMsg->msgBody, sizeof(t_FmIpcResourceAllocParams)); -+ vspBase = AllocVSPsForPartition(h_Fm, (uint8_t)ipcAllocParams.base, (uint8_t)ipcAllocParams.num, ipcAllocParams.guestId); -+ memcpy(p_IpcReply->replyBody, (uint8_t*)&vspBase, sizeof(uint8_t)); -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(uint8_t); -+ break; -+ } -+ case (FM_VSP_FREE) : -+ { -+ t_FmIpcResourceAllocParams ipcAllocParams; -+ memcpy(&ipcAllocParams, p_IpcMsg->msgBody, sizeof(t_FmIpcResourceAllocParams)); -+ FreeVSPsForPartition(h_Fm, (uint8_t)ipcAllocParams.base, (uint8_t)ipcAllocParams.num, ipcAllocParams.guestId); -+ break; -+ } -+ case (FM_VSP_SET_PORT_WINDOW) : -+ { -+ t_FmIpcVspSetPortWindow ipcVspSetPortWindow; -+ memcpy(&ipcVspSetPortWindow, p_IpcMsg->msgBody, sizeof(t_FmIpcVspSetPortWindow)); -+ err = SetVSPWindow(h_Fm, -+ ipcVspSetPortWindow.hardwarePortId, -+ ipcVspSetPortWindow.baseStorageProfile, -+ ipcVspSetPortWindow.log2NumOfProfiles); -+ return err; -+ } -+ case (FM_SET_CONG_GRP_PFC_PRIO) : -+ { -+ t_FmIpcSetCongestionGroupPfcPriority fmIpcSetCongestionGroupPfcPriority; -+ memcpy(&fmIpcSetCongestionGroupPfcPriority, p_IpcMsg->msgBody, sizeof(t_FmIpcSetCongestionGroupPfcPriority)); -+ err = FmSetCongestionGroupPFCpriority(h_Fm, -+ fmIpcSetCongestionGroupPfcPriority.congestionGroupId, -+ fmIpcSetCongestionGroupPfcPriority.priorityBitMap); -+ return err; -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ case (FM_FREE_PORT): -+ { -+ t_FmInterModulePortFreeParams portParams; -+ t_FmIpcPortFreeParams ipcPortParams; -+ -+ memcpy((uint8_t*)&ipcPortParams, p_IpcMsg->msgBody, sizeof(t_FmIpcPortFreeParams)); -+ portParams.hardwarePortId = ipcPortParams.hardwarePortId; -+ portParams.portType = (e_FmPortType)(ipcPortParams.enumPortType); -+ portParams.deqPipelineDepth = ipcPortParams.deqPipelineDepth; -+ FmFreePortParams(h_Fm, &portParams); -+ break; -+ } -+ case (FM_REGISTER_INTR): -+ { -+ t_FmIpcRegisterIntr ipcRegIntr; -+ -+ memcpy((uint8_t*)&ipcRegIntr, p_IpcMsg->msgBody, sizeof(ipcRegIntr)); -+ p_Fm->intrMng[ipcRegIntr.event].guestId = ipcRegIntr.guestId; -+ break; -+ } -+ case (FM_GET_PARAMS): -+ { -+ t_FmIpcParams ipcParams; -+ -+ /* Get clock frequency */ -+ ipcParams.fmClkFreq = p_Fm->p_FmStateStruct->fmClkFreq; -+ ipcParams.fmMacClkFreq = p_Fm->p_FmStateStruct->fmMacClkFreq; -+ -+ fman_get_revision(p_Fm->p_FmFpmRegs,&ipcParams.majorRev,&ipcParams.minorRev); -+ -+ memcpy(p_IpcReply->replyBody, (uint8_t*)&ipcParams, sizeof(t_FmIpcParams)); -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(t_FmIpcParams); -+ break; -+ } -+ case (FM_GET_FMAN_CTRL_CODE_REV): -+ { -+ t_FmCtrlCodeRevisionInfo fmanCtrlRevInfo; -+ t_FmIpcFmanCtrlCodeRevisionInfo ipcRevInfo; -+ -+ p_IpcReply->error = (uint32_t)FM_GetFmanCtrlCodeRevision(h_Fm, &fmanCtrlRevInfo); -+ ipcRevInfo.packageRev = fmanCtrlRevInfo.packageRev; -+ ipcRevInfo.majorRev = fmanCtrlRevInfo.majorRev; -+ ipcRevInfo.minorRev = fmanCtrlRevInfo.minorRev; -+ memcpy(p_IpcReply->replyBody, (uint8_t*)&ipcRevInfo, sizeof(t_FmIpcFmanCtrlCodeRevisionInfo)); -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(t_FmIpcFmanCtrlCodeRevisionInfo); -+ break; -+ } -+ -+ case (FM_DMA_STAT): -+ { -+ t_FmDmaStatus dmaStatus; -+ t_FmIpcDmaStatus ipcDmaStatus; -+ -+ FM_GetDmaStatus(h_Fm, &dmaStatus); -+ ipcDmaStatus.boolCmqNotEmpty = (uint8_t)dmaStatus.cmqNotEmpty; -+ ipcDmaStatus.boolBusError = (uint8_t)dmaStatus.busError; -+ ipcDmaStatus.boolReadBufEccError = (uint8_t)dmaStatus.readBufEccError; -+ ipcDmaStatus.boolWriteBufEccSysError = (uint8_t)dmaStatus.writeBufEccSysError; -+ ipcDmaStatus.boolWriteBufEccFmError = (uint8_t)dmaStatus.writeBufEccFmError; -+ ipcDmaStatus.boolSinglePortEccError = (uint8_t)dmaStatus.singlePortEccError; -+ memcpy(p_IpcReply->replyBody, (uint8_t*)&ipcDmaStatus, sizeof(t_FmIpcDmaStatus)); -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(t_FmIpcDmaStatus); -+ break; -+ } -+ case (FM_ALLOC_FMAN_CTRL_EVENT_REG): -+ p_IpcReply->error = (uint32_t)FmAllocFmanCtrlEventReg(h_Fm, (uint8_t*)p_IpcReply->replyBody); -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(uint8_t); -+ break; -+ case (FM_FREE_FMAN_CTRL_EVENT_REG): -+ FmFreeFmanCtrlEventReg(h_Fm, p_IpcMsg->msgBody[0]); -+ break; -+ case (FM_GET_TIMESTAMP_SCALE): -+ { -+ uint32_t timeStamp = FmGetTimeStampScale(h_Fm); -+ -+ memcpy(p_IpcReply->replyBody, (uint8_t*)&timeStamp, sizeof(uint32_t)); -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(uint32_t); -+ break; -+ } -+ case (FM_GET_COUNTER): -+ { -+ e_FmCounters inCounter; -+ uint32_t outCounter; -+ -+ memcpy((uint8_t*)&inCounter, p_IpcMsg->msgBody, sizeof(uint32_t)); -+ outCounter = FM_GetCounter(h_Fm, inCounter); -+ memcpy(p_IpcReply->replyBody, (uint8_t*)&outCounter, sizeof(uint32_t)); -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(uint32_t); -+ break; -+ } -+ case (FM_SET_FMAN_CTRL_EVENTS_ENABLE): -+ { -+ t_FmIpcFmanEvents ipcFmanEvents; -+ -+ memcpy((uint8_t*)&ipcFmanEvents, p_IpcMsg->msgBody, sizeof(t_FmIpcFmanEvents)); -+ FmSetFmanCtrlIntr(h_Fm, -+ ipcFmanEvents.eventRegId, -+ ipcFmanEvents.enableEvents); -+ break; -+ } -+ case (FM_GET_FMAN_CTRL_EVENTS_ENABLE): -+ { -+ uint32_t tmp = FmGetFmanCtrlIntr(h_Fm, p_IpcMsg->msgBody[0]); -+ -+ memcpy(p_IpcReply->replyBody, (uint8_t*)&tmp, sizeof(uint32_t)); -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(uint32_t); -+ break; -+ } -+ case (FM_GET_PHYS_MURAM_BASE): -+ { -+ t_FmPhysAddr physAddr; -+ t_FmIpcPhysAddr ipcPhysAddr; -+ -+ FmGetPhysicalMuramBase(h_Fm, &physAddr); -+ ipcPhysAddr.high = physAddr.high; -+ ipcPhysAddr.low = physAddr.low; -+ memcpy(p_IpcReply->replyBody, (uint8_t*)&ipcPhysAddr, sizeof(t_FmIpcPhysAddr)); -+ *p_ReplyLength = sizeof(uint32_t) + sizeof(t_FmIpcPhysAddr); -+ break; -+ } -+ case (FM_ENABLE_RAM_ECC): -+ { -+ if (((err = FM_EnableRamsEcc(h_Fm)) != E_OK) || -+ ((err = FM_SetException(h_Fm, e_FM_EX_IRAM_ECC, TRUE)) != E_OK) || -+ ((err = FM_SetException(h_Fm, e_FM_EX_MURAM_ECC, TRUE)) != E_OK)) -+#if (!(defined(DEBUG_ERRORS)) || (DEBUG_ERRORS == 0)) -+ UNUSED(err); -+#else -+ REPORT_ERROR(MINOR, err, NO_MSG); -+#endif /* (!(defined(DEBUG_ERRORS)) || (DEBUG_ERRORS == 0)) */ -+ break; -+ } -+ case (FM_DISABLE_RAM_ECC): -+ { -+ -+ if (((err = FM_SetException(h_Fm, e_FM_EX_IRAM_ECC, FALSE)) != E_OK) || -+ ((err = FM_SetException(h_Fm, e_FM_EX_MURAM_ECC, FALSE)) != E_OK) || -+ ((err = FM_DisableRamsEcc(h_Fm)) != E_OK)) -+#if (!(defined(DEBUG_ERRORS)) || (DEBUG_ERRORS == 0)) -+ UNUSED(err); -+#else -+ REPORT_ERROR(MINOR, err, NO_MSG); -+#endif /* (!(defined(DEBUG_ERRORS)) || (DEBUG_ERRORS == 0)) */ -+ break; -+ } -+ case (FM_SET_NUM_OF_FMAN_CTRL): -+ { -+ t_FmIpcPortNumOfFmanCtrls ipcPortNumOfFmanCtrls; -+ -+ memcpy((uint8_t*)&ipcPortNumOfFmanCtrls, p_IpcMsg->msgBody, sizeof(t_FmIpcPortNumOfFmanCtrls)); -+ err = FmSetNumOfRiscsPerPort(h_Fm, -+ ipcPortNumOfFmanCtrls.hardwarePortId, -+ ipcPortNumOfFmanCtrls.numOfFmanCtrls, -+ ipcPortNumOfFmanCtrls.orFmanCtrl); -+ if (err != E_OK) -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ break; -+ } -+#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -+ case (FM_10G_TX_ECC_WA): -+ p_IpcReply->error = (uint32_t)Fm10GTxEccWorkaround(h_Fm, p_IpcMsg->msgBody[0]); -+ *p_ReplyLength = sizeof(uint32_t); -+ break; -+#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ -+ default: -+ *p_ReplyLength = 0; -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, ("command not found!!!")); -+ } -+ return E_OK; -+} -+ -+ -+/****************************************/ -+/* Inter-Module functions */ -+/****************************************/ -+#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -+t_Error Fm10GTxEccWorkaround(t_Handle h_Fm, uint8_t macId) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ t_Error err = E_OK; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength; -+ uint8_t rxHardwarePortId, txHardwarePortId; -+ struct fman_fpm_regs *fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ if (p_Fm->guestId != NCSW_MASTER_ID) -+ { -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_10G_TX_ECC_WA; -+ msg.msgBody[0] = macId; -+ replyLength = sizeof(uint32_t); -+ if ((err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId)+sizeof(macId), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ if (replyLength != sizeof(uint32_t)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ return (t_Error)(reply.error); -+ } -+ -+ SANITY_CHECK_RETURN_ERROR((macId == 0), E_NOT_SUPPORTED); -+ SANITY_CHECK_RETURN_ERROR(IsFmanCtrlCodeLoaded(p_Fm), E_INVALID_STATE); -+ -+ rxHardwarePortId = SwPortIdToHwPortId(e_FM_PORT_TYPE_RX_10G, -+ macId, -+ p_Fm->p_FmStateStruct->revInfo.majorRev, -+ p_Fm->p_FmStateStruct->revInfo.minorRev); -+ txHardwarePortId = SwPortIdToHwPortId(e_FM_PORT_TYPE_TX_10G, -+ macId, -+ p_Fm->p_FmStateStruct->revInfo.majorRev, -+ p_Fm->p_FmStateStruct->revInfo.minorRev); -+ if ((p_Fm->p_FmStateStruct->portsTypes[rxHardwarePortId] != e_FM_PORT_TYPE_DUMMY) || -+ (p_Fm->p_FmStateStruct->portsTypes[txHardwarePortId] != e_FM_PORT_TYPE_DUMMY)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("MAC should be initialized prior to Rx and Tx ports!")); -+ -+ return fman_set_erratum_10gmac_a004_wa(fpm_rg); -+} -+#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ -+ -+uint16_t FmGetTnumAgingPeriod(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_Fm; -+ -+ SANITY_CHECK_RETURN_VALUE(p_Fm, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_VALUE(!p_Fm->p_FmDriverParam, E_INVALID_STATE, 0); -+ -+ return p_Fm->tnumAgingPeriod; -+} -+ -+t_Error FmSetPortPreFetchConfiguration(t_Handle h_Fm, -+ uint8_t portNum, -+ bool preFetchConfigured) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ -+ p_Fm->portsPreFetchConfigured[portNum] = TRUE; -+ p_Fm->portsPreFetchValue[portNum] = preFetchConfigured; -+ -+ return E_OK; -+} -+ -+t_Error FmGetPortPreFetchConfiguration(t_Handle h_Fm, -+ uint8_t portNum, -+ bool *p_PortConfigured, -+ bool *p_PreFetchConfigured) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ -+ /* If the prefetch wasn't configured yet (not enable or disabled) -+ we return the value TRUE as it was already configured */ -+ if (!p_Fm->portsPreFetchConfigured[portNum]) -+ { -+ *p_PortConfigured = FALSE; -+ *p_PreFetchConfigured = FALSE; -+ } -+ else -+ { -+ *p_PortConfigured = TRUE; -+ *p_PreFetchConfigured = (p_Fm->portsPreFetchConfigured[portNum]); -+ } -+ -+ return E_OK; -+} -+ -+t_Error FmSetCongestionGroupPFCpriority(t_Handle h_Fm, -+ uint32_t congestionGroupId, -+ uint8_t priorityBitMap) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_Fm; -+ uint32_t regNum; -+ -+ ASSERT_COND(h_Fm); -+ -+ if (congestionGroupId > FM_PORT_NUM_OF_CONGESTION_GRPS) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("Congestion group ID bigger than %d", -+ FM_PORT_NUM_OF_CONGESTION_GRPS)); -+ -+ if (p_Fm->guestId == NCSW_MASTER_ID) -+ { -+ ASSERT_COND(p_Fm->baseAddr); -+ regNum = (FM_PORT_NUM_OF_CONGESTION_GRPS - 1 - congestionGroupId) / 4; -+ fman_set_congestion_group_pfc_priority((uint32_t *)((p_Fm->baseAddr+FM_MM_CGP)), -+ congestionGroupId, -+ priorityBitMap, -+ regNum); -+ } -+ else if (p_Fm->h_IpcSessions[0]) -+ { -+ t_Error err; -+ t_FmIpcMsg msg; -+ t_FmIpcSetCongestionGroupPfcPriority fmIpcSetCongestionGroupPfcPriority; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&fmIpcSetCongestionGroupPfcPriority, 0, sizeof(t_FmIpcSetCongestionGroupPfcPriority)); -+ fmIpcSetCongestionGroupPfcPriority.congestionGroupId = congestionGroupId; -+ fmIpcSetCongestionGroupPfcPriority.priorityBitMap = priorityBitMap; -+ -+ msg.msgId = FM_SET_CONG_GRP_PFC_PRIO; -+ memcpy(msg.msgBody, &fmIpcSetCongestionGroupPfcPriority, sizeof(t_FmIpcSetCongestionGroupPfcPriority)); -+ -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("guest without IPC!")); -+ -+ return E_OK; -+} -+ -+uintptr_t FmGetPcdPrsBaseAddr(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_VALUE(p_Fm, E_INVALID_HANDLE, 0); -+ -+ if (!p_Fm->baseAddr) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, -+ ("No base-addr; probably Guest with IPC!")); -+ return 0; -+ } -+ -+ return (p_Fm->baseAddr + FM_MM_PRS); -+} -+ -+uintptr_t FmGetPcdKgBaseAddr(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_VALUE(p_Fm, E_INVALID_HANDLE, 0); -+ -+ if (!p_Fm->baseAddr) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, -+ ("No base-addr; probably Guest with IPC!")); -+ return 0; -+ } -+ -+ return (p_Fm->baseAddr + FM_MM_KG); -+} -+ -+uintptr_t FmGetPcdPlcrBaseAddr(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_VALUE(p_Fm, E_INVALID_HANDLE, 0); -+ -+ if (!p_Fm->baseAddr) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, -+ ("No base-addr; probably Guest with IPC!")); -+ return 0; -+ } -+ -+ return (p_Fm->baseAddr + FM_MM_PLCR); -+} -+ -+#if (DPAA_VERSION >= 11) -+uintptr_t FmGetVSPBaseAddr(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_VALUE(p_Fm, E_INVALID_HANDLE, 0); -+ -+ return p_Fm->vspBaseAddr; -+} -+#endif /* (DPAA_VERSION >= 11) */ -+ -+t_Handle FmGetMuramHandle(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_VALUE(p_Fm, E_INVALID_HANDLE, NULL); -+ -+ return (p_Fm->h_FmMuram); -+} -+ -+void FmGetPhysicalMuramBase(t_Handle h_Fm, t_FmPhysAddr *p_FmPhysAddr) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ if (p_Fm->fmMuramPhysBaseAddr) -+ { -+ /* General FM driver initialization */ -+ p_FmPhysAddr->low = (uint32_t)p_Fm->fmMuramPhysBaseAddr; -+ p_FmPhysAddr->high = (uint8_t)((p_Fm->fmMuramPhysBaseAddr & 0x000000ff00000000LL) >> 32); -+ return; -+ } -+ -+ ASSERT_COND(p_Fm->guestId != NCSW_MASTER_ID); -+ -+ if (p_Fm->h_IpcSessions[0]) -+ { -+ t_Error err; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength; -+ t_FmIpcPhysAddr ipcPhysAddr; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_GET_PHYS_MURAM_BASE; -+ replyLength = sizeof(uint32_t) + sizeof(t_FmPhysAddr); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ { -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ return; -+ } -+ if (replyLength != (sizeof(uint32_t) + sizeof(t_FmPhysAddr))) -+ { -+ REPORT_ERROR(MINOR, E_INVALID_VALUE,("IPC reply length mismatch")); -+ return; -+ } -+ memcpy((uint8_t*)&ipcPhysAddr, reply.replyBody, sizeof(t_FmIpcPhysAddr)); -+ p_FmPhysAddr->high = ipcPhysAddr.high; -+ p_FmPhysAddr->low = ipcPhysAddr.low; -+ } -+ else -+ REPORT_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without neither IPC nor mapped register!")); -+} -+ -+#if (DPAA_VERSION >= 11) -+t_Error FmVSPAllocForPort (t_Handle h_Fm, -+ e_FmPortType portType, -+ uint8_t portId, -+ uint8_t numOfVSPs) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_Fm; -+ t_Error err = E_OK; -+ uint32_t profilesFound, intFlags; -+ uint8_t first, i; -+ uint8_t log2Num; -+ uint8_t swPortIndex=0, hardwarePortId; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ -+ if (!numOfVSPs) -+ return E_OK; -+ -+ if (numOfVSPs > FM_VSP_MAX_NUM_OF_ENTRIES) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, ("numProfiles can not be bigger than %d.",FM_VSP_MAX_NUM_OF_ENTRIES)); -+ -+ if (!POWER_OF_2(numOfVSPs)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numProfiles must be a power of 2.")); -+ -+ LOG2((uint64_t)numOfVSPs, log2Num); -+ -+ if ((log2Num == 0) || (p_Fm->partVSPBase == 0)) -+ first = 0; -+ else -+ first = 1< (p_Fm->partVSPBase + p_Fm->partNumOfVSPs)) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, ("can not allocate storage profile port window")); -+ -+ if (first < p_Fm->partVSPBase) -+ while (first < p_Fm->partVSPBase) -+ first = first + numOfVSPs; -+ -+ if ((first + numOfVSPs) > (p_Fm->partVSPBase + p_Fm->partNumOfVSPs)) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, ("can not allocate storage profile port window")); -+ -+ intFlags = XX_LockIntrSpinlock(p_Fm->h_Spinlock); -+ profilesFound = 0; -+ for (i=first; i < p_Fm->partVSPBase + p_Fm->partNumOfVSPs; ) -+ { -+ if (!p_Fm->p_FmSp->profiles[i].profilesMng.allocated) -+ { -+ profilesFound++; -+ i++; -+ if (profilesFound == numOfVSPs) -+ break; -+ } -+ else -+ { -+ profilesFound = 0; -+ /* advance i to the next aligned address */ -+ first = i = (uint8_t)(first + numOfVSPs); -+ } -+ } -+ if (profilesFound == numOfVSPs) -+ for (i = first; ip_FmSp->profiles[i].profilesMng.allocated = TRUE; -+ else -+ { -+ XX_UnlockIntrSpinlock(p_Fm->h_Spinlock, intFlags); -+ RETURN_ERROR(MINOR, E_FULL, ("No profiles.")); -+ } -+ -+ hardwarePortId = SwPortIdToHwPortId(portType, -+ portId, -+ p_Fm->p_FmStateStruct->revInfo.majorRev, -+ p_Fm->p_FmStateStruct->revInfo.minorRev); -+ HW_PORT_ID_TO_SW_PORT_INDX(swPortIndex, hardwarePortId); -+ -+ p_Fm->p_FmSp->portsMapping[swPortIndex].numOfProfiles = numOfVSPs; -+ p_Fm->p_FmSp->portsMapping[swPortIndex].profilesBase = first; -+ -+ if ((err = SetVSPWindow(h_Fm,hardwarePortId, first,log2Num)) != E_OK) -+ for (i = first; i < first + numOfVSPs; i++) -+ p_Fm->p_FmSp->profiles[i].profilesMng.allocated = FALSE; -+ -+ XX_UnlockIntrSpinlock(p_Fm->h_Spinlock, intFlags); -+ -+ return err; -+} -+ -+t_Error FmVSPFreeForPort(t_Handle h_Fm, -+ e_FmPortType portType, -+ uint8_t portId) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_Fm; -+ uint8_t swPortIndex=0, hardwarePortId, first, numOfVSPs, i; -+ uint32_t intFlags; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ -+ hardwarePortId = SwPortIdToHwPortId(portType, -+ portId, -+ p_Fm->p_FmStateStruct->revInfo.majorRev, -+ p_Fm->p_FmStateStruct->revInfo.minorRev); -+ HW_PORT_ID_TO_SW_PORT_INDX(swPortIndex, hardwarePortId); -+ -+ numOfVSPs = (uint8_t)p_Fm->p_FmSp->portsMapping[swPortIndex].numOfProfiles; -+ first = (uint8_t)p_Fm->p_FmSp->portsMapping[swPortIndex].profilesBase; -+ -+ intFlags = XX_LockIntrSpinlock(p_Fm->h_Spinlock); -+ for (i = first; i < first + numOfVSPs; i++) -+ p_Fm->p_FmSp->profiles[i].profilesMng.allocated = FALSE; -+ XX_UnlockIntrSpinlock(p_Fm->h_Spinlock, intFlags); -+ -+ p_Fm->p_FmSp->portsMapping[swPortIndex].numOfProfiles = 0; -+ p_Fm->p_FmSp->portsMapping[swPortIndex].profilesBase = 0; -+ -+ return E_OK; -+} -+#endif /* (DPAA_VERSION >= 11) */ -+ -+t_Error FmAllocFmanCtrlEventReg(t_Handle h_Fm, uint8_t *p_EventId) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ uint8_t i; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_Error err; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_ALLOC_FMAN_CTRL_EVENT_REG; -+ replyLength = sizeof(uint32_t) + sizeof(uint8_t); -+ if ((err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (replyLength != (sizeof(uint32_t) + sizeof(uint8_t))) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ -+ *p_EventId = *(uint8_t*)(reply.replyBody); -+ -+ return (t_Error)(reply.error); -+ } -+ else if (p_Fm->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without IPC!")); -+ -+ for (i=0;iusedEventRegs[i]) -+ { -+ p_Fm->usedEventRegs[i] = TRUE; -+ *p_EventId = i; -+ break; -+ } -+ -+ if (i==FM_NUM_OF_FMAN_CTRL_EVENT_REGS) -+ RETURN_ERROR(MAJOR, E_BUSY, ("No resource - FMan controller event register.")); -+ -+ return E_OK; -+} -+ -+void FmFreeFmanCtrlEventReg(t_Handle h_Fm, uint8_t eventId) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN(p_Fm, E_INVALID_HANDLE); -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_Error err; -+ t_FmIpcMsg msg; -+ -+ memset(&msg, 0, sizeof(msg)); -+ msg.msgId = FM_FREE_FMAN_CTRL_EVENT_REG; -+ msg.msgBody[0] = eventId; -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId)+sizeof(eventId), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ return; -+ } -+ else if (p_Fm->guestId != NCSW_MASTER_ID) -+ { -+ REPORT_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without IPC!")); -+ return; -+ } -+ -+ ((t_Fm*)h_Fm)->usedEventRegs[eventId] = FALSE; -+} -+ -+void FmSetFmanCtrlIntr(t_Handle h_Fm, uint8_t eventRegId, uint32_t enableEvents) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ struct fman_fpm_regs *fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ !p_Fm->p_FmFpmRegs && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_FmIpcFmanEvents fmanCtrl; -+ t_Error err; -+ t_FmIpcMsg msg; -+ -+ fmanCtrl.eventRegId = eventRegId; -+ fmanCtrl.enableEvents = enableEvents; -+ memset(&msg, 0, sizeof(msg)); -+ msg.msgId = FM_SET_FMAN_CTRL_EVENTS_ENABLE; -+ memcpy(msg.msgBody, &fmanCtrl, sizeof(fmanCtrl)); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId)+sizeof(fmanCtrl), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ return; -+ } -+ else if (!p_Fm->p_FmFpmRegs) -+ { -+ REPORT_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("Either IPC or 'baseAddress' is required!")); -+ return; -+ } -+ -+ ASSERT_COND(eventRegId < FM_NUM_OF_FMAN_CTRL_EVENT_REGS); -+ fman_set_ctrl_intr(fpm_rg, eventRegId, enableEvents); -+} -+ -+uint32_t FmGetFmanCtrlIntr(t_Handle h_Fm, uint8_t eventRegId) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ struct fman_fpm_regs *fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ !p_Fm->p_FmFpmRegs && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_Error err; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength, ctrlIntr; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_GET_FMAN_CTRL_EVENTS_ENABLE; -+ msg.msgBody[0] = eventRegId; -+ replyLength = sizeof(uint32_t) + sizeof(uint32_t); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId)+sizeof(eventRegId), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ { -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ return 0; -+ } -+ if (replyLength != (sizeof(uint32_t) + sizeof(uint32_t))) -+ { -+ REPORT_ERROR(MINOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ return 0; -+ } -+ memcpy((uint8_t*)&ctrlIntr, reply.replyBody, sizeof(uint32_t)); -+ return ctrlIntr; -+ } -+ else if (!p_Fm->p_FmFpmRegs) -+ { -+ REPORT_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("Either IPC or 'baseAddress' is required!")); -+ return 0; -+ } -+ -+ return fman_get_ctrl_intr(fpm_rg, eventRegId); -+} -+ -+void FmRegisterIntr(t_Handle h_Fm, -+ e_FmEventModules module, -+ uint8_t modId, -+ e_FmIntrType intrType, -+ void (*f_Isr) (t_Handle h_Arg), -+ t_Handle h_Arg) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ int event = 0; -+ -+ ASSERT_COND(h_Fm); -+ -+ GET_FM_MODULE_EVENT(module, modId, intrType, event); -+ ASSERT_COND(event < e_FM_EV_DUMMY_LAST); -+ -+ /* register in local FM structure */ -+ p_Fm->intrMng[event].f_Isr = f_Isr; -+ p_Fm->intrMng[event].h_SrcHandle = h_Arg; -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_FmIpcRegisterIntr fmIpcRegisterIntr; -+ t_Error err; -+ t_FmIpcMsg msg; -+ -+ /* register in Master FM structure */ -+ fmIpcRegisterIntr.event = (uint32_t)event; -+ fmIpcRegisterIntr.guestId = p_Fm->guestId; -+ memset(&msg, 0, sizeof(msg)); -+ msg.msgId = FM_REGISTER_INTR; -+ memcpy(msg.msgBody, &fmIpcRegisterIntr, sizeof(fmIpcRegisterIntr)); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(fmIpcRegisterIntr), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ } -+ else if (p_Fm->guestId != NCSW_MASTER_ID) -+ REPORT_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without IPC!")); -+} -+ -+void FmUnregisterIntr(t_Handle h_Fm, -+ e_FmEventModules module, -+ uint8_t modId, -+ e_FmIntrType intrType) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ int event = 0; -+ -+ ASSERT_COND(h_Fm); -+ -+ GET_FM_MODULE_EVENT(module, modId,intrType, event); -+ ASSERT_COND(event < e_FM_EV_DUMMY_LAST); -+ -+ p_Fm->intrMng[event].f_Isr = UnimplementedIsr; -+ p_Fm->intrMng[event].h_SrcHandle = NULL; -+} -+ -+void FmRegisterFmanCtrlIntr(t_Handle h_Fm, uint8_t eventRegId, void (*f_Isr) (t_Handle h_Arg, uint32_t event), t_Handle h_Arg) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ ASSERT_COND(eventRegIdguestId != NCSW_MASTER_ID) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM in guest-mode")); -+ return; -+ } -+ -+ p_Fm->fmanCtrlIntr[eventRegId].f_Isr = f_Isr; -+ p_Fm->fmanCtrlIntr[eventRegId].h_SrcHandle = h_Arg; -+} -+ -+void FmUnregisterFmanCtrlIntr(t_Handle h_Fm, uint8_t eventRegId) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ ASSERT_COND(eventRegIdguestId != NCSW_MASTER_ID) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM in guest-mode")); -+ return; -+ } -+ -+ p_Fm->fmanCtrlIntr[eventRegId].f_Isr = UnimplementedFmanCtrlIsr; -+ p_Fm->fmanCtrlIntr[eventRegId].h_SrcHandle = NULL; -+} -+ -+void FmRegisterPcd(t_Handle h_Fm, t_Handle h_FmPcd) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ if (p_Fm->h_Pcd) -+ REPORT_ERROR(MAJOR, E_ALREADY_EXISTS, ("PCD already set")); -+ -+ p_Fm->h_Pcd = h_FmPcd; -+} -+ -+void FmUnregisterPcd(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ if (!p_Fm->h_Pcd) -+ REPORT_ERROR(MAJOR, E_NOT_FOUND, ("PCD handle!")); -+ -+ p_Fm->h_Pcd = NULL; -+} -+ -+t_Handle FmGetPcdHandle(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ return p_Fm->h_Pcd; -+} -+ -+uint8_t FmGetId(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_VALUE(p_Fm, E_INVALID_HANDLE, 0xff); -+ -+ return p_Fm->p_FmStateStruct->fmId; -+} -+ -+t_Error FmSetNumOfRiscsPerPort(t_Handle h_Fm, -+ uint8_t hardwarePortId, -+ uint8_t numOfFmanCtrls, -+ t_FmFmanCtrl orFmanCtrl) -+{ -+ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ struct fman_fpm_regs *fpm_rg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(((numOfFmanCtrls > 0) && (numOfFmanCtrls < 3)) , E_INVALID_HANDLE); -+ -+ fpm_rg = p_Fm->p_FmFpmRegs; -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ !p_Fm->p_FmFpmRegs && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_Error err; -+ t_FmIpcPortNumOfFmanCtrls params; -+ t_FmIpcMsg msg; -+ -+ memset(&msg, 0, sizeof(msg)); -+ params.hardwarePortId = hardwarePortId; -+ params.numOfFmanCtrls = numOfFmanCtrls; -+ params.orFmanCtrl = orFmanCtrl; -+ msg.msgId = FM_SET_NUM_OF_FMAN_CTRL; -+ memcpy(msg.msgBody, ¶ms, sizeof(params)); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) +sizeof(params), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ return E_OK; -+ } -+ else if (!p_Fm->p_FmFpmRegs) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("Either IPC or 'baseAddress' is required!")); -+ -+ fman_set_num_of_riscs_per_port(fpm_rg, hardwarePortId, numOfFmanCtrls, orFmanCtrl); -+ -+ return E_OK; -+} -+ -+t_Error FmGetSetPortParams(t_Handle h_Fm, t_FmInterModulePortInitParams *p_PortParams) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ t_Error err; -+ uint32_t intFlags; -+ uint8_t hardwarePortId = p_PortParams->hardwarePortId, macId; -+ struct fman_rg fman_rg; -+ -+ fman_rg.bmi_rg = p_Fm->p_FmBmiRegs; -+ fman_rg.qmi_rg = p_Fm->p_FmQmiRegs; -+ fman_rg.fpm_rg = p_Fm->p_FmFpmRegs; -+ fman_rg.dma_rg = p_Fm->p_FmDmaRegs; -+ -+ if (p_Fm->guestId != NCSW_MASTER_ID) -+ { -+ t_FmIpcPortInInitParams portInParams; -+ t_FmIpcPortOutInitParams portOutParams; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength; -+ -+ portInParams.hardwarePortId = p_PortParams->hardwarePortId; -+ portInParams.enumPortType = (uint32_t)p_PortParams->portType; -+ portInParams.boolIndependentMode= (uint8_t)p_PortParams->independentMode; -+ portInParams.liodnOffset = p_PortParams->liodnOffset; -+ portInParams.numOfTasks = p_PortParams->numOfTasks; -+ portInParams.numOfExtraTasks = p_PortParams->numOfExtraTasks; -+ portInParams.numOfOpenDmas = p_PortParams->numOfOpenDmas; -+ portInParams.numOfExtraOpenDmas = p_PortParams->numOfExtraOpenDmas; -+ portInParams.sizeOfFifo = p_PortParams->sizeOfFifo; -+ portInParams.extraSizeOfFifo = p_PortParams->extraSizeOfFifo; -+ portInParams.deqPipelineDepth = p_PortParams->deqPipelineDepth; -+ portInParams.maxFrameLength = p_PortParams->maxFrameLength; -+ portInParams.liodnBase = p_PortParams->liodnBase; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_GET_SET_PORT_PARAMS; -+ memcpy(msg.msgBody, &portInParams, sizeof(portInParams)); -+ replyLength = (sizeof(uint32_t) + sizeof(t_FmIpcPortOutInitParams)); -+ if ((err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) +sizeof(portInParams), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ if (replyLength != (sizeof(uint32_t) + sizeof(t_FmIpcPortOutInitParams))) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ memcpy((uint8_t*)&portOutParams, reply.replyBody, sizeof(t_FmIpcPortOutInitParams)); -+ -+ p_PortParams->fmMuramPhysBaseAddr.high = portOutParams.ipcPhysAddr.high; -+ p_PortParams->fmMuramPhysBaseAddr.low = portOutParams.ipcPhysAddr.low; -+ p_PortParams->numOfTasks = portOutParams.numOfTasks; -+ p_PortParams->numOfExtraTasks = portOutParams.numOfExtraTasks; -+ p_PortParams->numOfOpenDmas = portOutParams.numOfOpenDmas; -+ p_PortParams->numOfExtraOpenDmas = portOutParams.numOfExtraOpenDmas; -+ p_PortParams->sizeOfFifo = portOutParams.sizeOfFifo; -+ p_PortParams->extraSizeOfFifo = portOutParams.extraSizeOfFifo; -+ -+ return (t_Error)(reply.error); -+ } -+ -+ ASSERT_COND(IN_RANGE(1, hardwarePortId, 63)); -+ -+ intFlags = XX_LockIntrSpinlock(p_Fm->h_Spinlock); -+ if (p_PortParams->independentMode) -+ { -+ /* set port parameters */ -+ p_Fm->independentMode = p_PortParams->independentMode; -+ /* disable dispatch limit */ -+ fman_qmi_disable_dispatch_limit(fman_rg.fpm_rg); -+ } -+ -+ if (p_PortParams->portType == e_FM_PORT_TYPE_OH_HOST_COMMAND) -+ { -+ if (p_Fm->hcPortInitialized) -+ { -+ XX_UnlockIntrSpinlock(p_Fm->h_Spinlock, intFlags); -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Only one host command port is allowed.")); -+ } -+ else -+ p_Fm->hcPortInitialized = TRUE; -+ } -+ p_Fm->p_FmStateStruct->portsTypes[hardwarePortId] = p_PortParams->portType; -+ -+ err = FmSetNumOfTasks(p_Fm, hardwarePortId, &p_PortParams->numOfTasks, &p_PortParams->numOfExtraTasks, TRUE); -+ if (err) -+ { -+ XX_UnlockIntrSpinlock(p_Fm->h_Spinlock, intFlags); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+#ifdef FM_QMI_NO_DEQ_OPTIONS_SUPPORT -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev != 4) -+#endif /* FM_QMI_NO_DEQ_OPTIONS_SUPPORT */ -+ if ((p_PortParams->portType != e_FM_PORT_TYPE_RX) && -+ (p_PortParams->portType != e_FM_PORT_TYPE_RX_10G)) -+ /* for transmit & O/H ports */ -+ { -+ uint8_t enqTh; -+ uint8_t deqTh; -+ -+ /* update qmi ENQ/DEQ threshold */ -+ p_Fm->p_FmStateStruct->accumulatedNumOfDeqTnums += p_PortParams->deqPipelineDepth; -+ enqTh = fman_get_qmi_enq_th(fman_rg.qmi_rg); -+ /* if enqTh is too big, we reduce it to the max value that is still OK */ -+ if (enqTh >= (QMI_MAX_NUM_OF_TNUMS - p_Fm->p_FmStateStruct->accumulatedNumOfDeqTnums)) -+ { -+ enqTh = (uint8_t)(QMI_MAX_NUM_OF_TNUMS - p_Fm->p_FmStateStruct->accumulatedNumOfDeqTnums - 1); -+ fman_set_qmi_enq_th(fman_rg.qmi_rg, enqTh); -+ } -+ -+ deqTh = fman_get_qmi_deq_th(fman_rg.qmi_rg); -+ /* if deqTh is too small, we enlarge it to the min value that is still OK. -+ deqTh may not be larger than 63 (QMI_MAX_NUM_OF_TNUMS-1). */ -+ if ((deqTh <= p_Fm->p_FmStateStruct->accumulatedNumOfDeqTnums) && (deqTh < QMI_MAX_NUM_OF_TNUMS-1)) -+ { -+ deqTh = (uint8_t)(p_Fm->p_FmStateStruct->accumulatedNumOfDeqTnums + 1); -+ fman_set_qmi_deq_th(fman_rg.qmi_rg, deqTh); -+ } -+ } -+ -+#ifdef FM_LOW_END_RESTRICTION -+ if ((hardwarePortId==0x1) || (hardwarePortId==0x29)) -+ { -+ if (p_Fm->p_FmStateStruct->lowEndRestriction) -+ { -+ XX_UnlockIntrSpinlock(p_Fm->h_Spinlock, intFlags); -+ RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, ("OP #0 cannot work with Tx Port #1.")); -+ } -+ else -+ p_Fm->p_FmStateStruct->lowEndRestriction = TRUE; -+ } -+#endif /* FM_LOW_END_RESTRICTION */ -+ -+ err = FmSetSizeOfFifo(p_Fm, -+ hardwarePortId, -+ &p_PortParams->sizeOfFifo, -+ &p_PortParams->extraSizeOfFifo, -+ TRUE); -+ if (err) -+ { -+ XX_UnlockIntrSpinlock(p_Fm->h_Spinlock, intFlags); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ err = FmSetNumOfOpenDmas(p_Fm, -+ hardwarePortId, -+ &p_PortParams->numOfOpenDmas, -+ &p_PortParams->numOfExtraOpenDmas, -+ TRUE); -+ if (err) -+ { -+ XX_UnlockIntrSpinlock(p_Fm->h_Spinlock, intFlags); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ fman_set_liodn_per_port(&fman_rg, -+ hardwarePortId, -+ p_PortParams->liodnBase, -+ p_PortParams->liodnOffset); -+ -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev < 6) -+ fman_set_order_restoration_per_port(fman_rg.fpm_rg, -+ hardwarePortId, -+ p_PortParams->independentMode, -+ !!((p_PortParams->portType==e_FM_PORT_TYPE_RX) || (p_PortParams->portType==e_FM_PORT_TYPE_RX_10G))); -+ -+ HW_PORT_ID_TO_SW_PORT_ID(macId, hardwarePortId); -+ -+#if defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS) -+ if ((p_PortParams->portType == e_FM_PORT_TYPE_TX_10G) || -+ (p_PortParams->portType == e_FM_PORT_TYPE_RX_10G)) -+ { -+ ASSERT_COND(macId < FM_MAX_NUM_OF_10G_MACS); -+ if (p_PortParams->maxFrameLength >= p_Fm->p_FmStateStruct->macMaxFrameLengths10G[macId]) -+ p_Fm->p_FmStateStruct->portMaxFrameLengths10G[macId] = p_PortParams->maxFrameLength; -+ else -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, ("Port maxFrameLength is smaller than MAC current MTU")); -+ } -+ else -+#endif /* defined(FM_MAX_NUM_OF_10G_MACS) && ... */ -+ if ((p_PortParams->portType == e_FM_PORT_TYPE_TX) || -+ (p_PortParams->portType == e_FM_PORT_TYPE_RX)) -+ { -+ ASSERT_COND(macId < FM_MAX_NUM_OF_1G_MACS); -+ if (p_PortParams->maxFrameLength >= p_Fm->p_FmStateStruct->macMaxFrameLengths1G[macId]) -+ p_Fm->p_FmStateStruct->portMaxFrameLengths1G[macId] = p_PortParams->maxFrameLength; -+ else -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, ("Port maxFrameLength is smaller than MAC current MTU")); -+ } -+ -+ FmGetPhysicalMuramBase(p_Fm, &p_PortParams->fmMuramPhysBaseAddr); -+ XX_UnlockIntrSpinlock(p_Fm->h_Spinlock, intFlags); -+ -+ return E_OK; -+} -+ -+void FmFreePortParams(t_Handle h_Fm,t_FmInterModulePortFreeParams *p_PortParams) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ uint32_t intFlags; -+ uint8_t hardwarePortId = p_PortParams->hardwarePortId; -+ uint8_t numOfTasks, numOfDmas, macId; -+ uint16_t sizeOfFifo; -+ t_Error err; -+ t_FmIpcPortFreeParams portParams; -+ t_FmIpcMsg msg; -+ struct fman_qmi_regs *qmi_rg = p_Fm->p_FmQmiRegs; -+ struct fman_bmi_regs *bmi_rg = p_Fm->p_FmBmiRegs; -+ -+ if (p_Fm->guestId != NCSW_MASTER_ID) -+ { -+ portParams.hardwarePortId = p_PortParams->hardwarePortId; -+ portParams.enumPortType = (uint32_t)p_PortParams->portType; -+ portParams.deqPipelineDepth = p_PortParams->deqPipelineDepth; -+ memset(&msg, 0, sizeof(msg)); -+ msg.msgId = FM_FREE_PORT; -+ memcpy(msg.msgBody, &portParams, sizeof(portParams)); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId)+sizeof(portParams), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ return; -+ } -+ -+ ASSERT_COND(IN_RANGE(1, hardwarePortId, 63)); -+ -+ intFlags = XX_LockIntrSpinlock(p_Fm->h_Spinlock); -+ -+ if (p_PortParams->portType == e_FM_PORT_TYPE_OH_HOST_COMMAND) -+ { -+ ASSERT_COND(p_Fm->hcPortInitialized); -+ p_Fm->hcPortInitialized = FALSE; -+ } -+ -+ p_Fm->p_FmStateStruct->portsTypes[hardwarePortId] = e_FM_PORT_TYPE_DUMMY; -+ -+ /* free numOfTasks */ -+ numOfTasks = fman_get_num_of_tasks(bmi_rg, hardwarePortId); -+ ASSERT_COND(p_Fm->p_FmStateStruct->accumulatedNumOfTasks >= numOfTasks); -+ p_Fm->p_FmStateStruct->accumulatedNumOfTasks -= numOfTasks; -+ -+ /* free numOfOpenDmas */ -+ numOfDmas = fman_get_num_of_dmas(bmi_rg, hardwarePortId); -+ ASSERT_COND(p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas >= numOfDmas); -+ p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas -= numOfDmas; -+ -+#ifdef FM_HAS_TOTAL_DMAS -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev < 6) -+ { -+ /* update total num of DMA's with committed number of open DMAS, and max uncommitted pool. */ -+ fman_set_num_of_open_dmas(bmi_rg, -+ hardwarePortId, -+ 1, -+ 0, -+ (uint8_t)(p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas + p_Fm->p_FmStateStruct->extraOpenDmasPoolSize)); -+ } -+#endif /* FM_HAS_TOTAL_DMAS */ -+ -+ /* free sizeOfFifo */ -+ sizeOfFifo = fman_get_size_of_fifo(bmi_rg, hardwarePortId); -+ ASSERT_COND(p_Fm->p_FmStateStruct->accumulatedFifoSize >= (sizeOfFifo * BMI_FIFO_UNITS)); -+ p_Fm->p_FmStateStruct->accumulatedFifoSize -= (sizeOfFifo * BMI_FIFO_UNITS); -+ -+#ifdef FM_QMI_NO_DEQ_OPTIONS_SUPPORT -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev != 4) -+#endif /* FM_QMI_NO_DEQ_OPTIONS_SUPPORT */ -+ if ((p_PortParams->portType != e_FM_PORT_TYPE_RX) && -+ (p_PortParams->portType != e_FM_PORT_TYPE_RX_10G)) -+ /* for transmit & O/H ports */ -+ { -+ uint8_t enqTh; -+ uint8_t deqTh; -+ -+ /* update qmi ENQ/DEQ threshold */ -+ p_Fm->p_FmStateStruct->accumulatedNumOfDeqTnums -= p_PortParams->deqPipelineDepth; -+ -+ /* p_Fm->p_FmStateStruct->accumulatedNumOfDeqTnums is now smaller, -+ so we can enlarge enqTh */ -+ enqTh = (uint8_t)(QMI_MAX_NUM_OF_TNUMS - p_Fm->p_FmStateStruct->accumulatedNumOfDeqTnums - 1); -+ -+ /* p_Fm->p_FmStateStruct->accumulatedNumOfDeqTnums is now smaller, -+ so we can reduce deqTh */ -+ deqTh = (uint8_t)(p_Fm->p_FmStateStruct->accumulatedNumOfDeqTnums + 1); -+ -+ fman_set_qmi_enq_th(qmi_rg, enqTh); -+ fman_set_qmi_deq_th(qmi_rg, deqTh); -+ } -+ -+ HW_PORT_ID_TO_SW_PORT_ID(macId, hardwarePortId); -+ -+#if defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS) -+ if ((p_PortParams->portType == e_FM_PORT_TYPE_TX_10G) || -+ (p_PortParams->portType == e_FM_PORT_TYPE_RX_10G)) -+ { -+ ASSERT_COND(macId < FM_MAX_NUM_OF_10G_MACS); -+ p_Fm->p_FmStateStruct->portMaxFrameLengths10G[macId] = 0; -+ } -+ else -+#endif /* defined(FM_MAX_NUM_OF_10G_MACS) && ... */ -+ if ((p_PortParams->portType == e_FM_PORT_TYPE_TX) || -+ (p_PortParams->portType == e_FM_PORT_TYPE_RX)) -+ { -+ ASSERT_COND(macId < FM_MAX_NUM_OF_1G_MACS); -+ p_Fm->p_FmStateStruct->portMaxFrameLengths1G[macId] = 0; -+ } -+ -+#ifdef FM_LOW_END_RESTRICTION -+ if ((hardwarePortId==0x1) || (hardwarePortId==0x29)) -+ p_Fm->p_FmStateStruct->lowEndRestriction = FALSE; -+#endif /* FM_LOW_END_RESTRICTION */ -+ XX_UnlockIntrSpinlock(p_Fm->h_Spinlock, intFlags); -+} -+ -+t_Error FmIsPortStalled(t_Handle h_Fm, uint8_t hardwarePortId, bool *p_IsStalled) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ t_Error err; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength; -+ struct fman_fpm_regs *fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ !p_Fm->baseAddr && -+ p_Fm->h_IpcSessions[0]) -+ { -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_IS_PORT_STALLED; -+ msg.msgBody[0] = hardwarePortId; -+ replyLength = sizeof(uint32_t) + sizeof(uint8_t); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId)+sizeof(hardwarePortId), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ if (replyLength != (sizeof(uint32_t) + sizeof(uint8_t))) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ -+ *p_IsStalled = (bool)!!(*(uint8_t*)(reply.replyBody)); -+ -+ return (t_Error)(reply.error); -+ } -+ else if (!p_Fm->baseAddr) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("Either IPC or 'baseAddress' is required!")); -+ -+ *p_IsStalled = fman_is_port_stalled(fpm_rg, hardwarePortId); -+ -+ return E_OK; -+} -+ -+t_Error FmResumeStalledPort(t_Handle h_Fm, uint8_t hardwarePortId) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ t_Error err; -+ bool isStalled; -+ struct fman_fpm_regs *fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ !p_Fm->baseAddr && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_RESUME_STALLED_PORT; -+ msg.msgBody[0] = hardwarePortId; -+ replyLength = sizeof(uint32_t); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(hardwarePortId), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ if (replyLength != sizeof(uint32_t)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ return (t_Error)(reply.error); -+ } -+ else if (!p_Fm->baseAddr) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("Either IPC or 'baseAddress' is required!")); -+ -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev >= 6) -+ RETURN_ERROR(MINOR, E_NOT_AVAILABLE, ("Not available for this FM revision!")); -+ -+ /* Get port status */ -+ err = FmIsPortStalled(h_Fm, hardwarePortId, &isStalled); -+ if (err) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Can't get port status")); -+ if (!isStalled) -+ return E_OK; -+ -+ fman_resume_stalled_port(fpm_rg, hardwarePortId); -+ -+ return E_OK; -+} -+ -+t_Error FmResetMac(t_Handle h_Fm, e_FmMacType type, uint8_t macId) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ t_Error err; -+ struct fman_fpm_regs *fpm_rg = p_Fm->p_FmFpmRegs; -+ -+#if (DPAA_VERSION >= 11) -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev >= 6) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("FMan MAC reset!")); -+#endif /*(DPAA_VERSION >= 11)*/ -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ !p_Fm->baseAddr && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_FmIpcMacParams macParams; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ macParams.id = macId; -+ macParams.enumType = (uint32_t)type; -+ msg.msgId = FM_RESET_MAC; -+ memcpy(msg.msgBody, &macParams, sizeof(macParams)); -+ replyLength = sizeof(uint32_t); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId)+sizeof(macParams), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ if (replyLength != sizeof(uint32_t)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ return (t_Error)(reply.error); -+ } -+ else if (!p_Fm->baseAddr) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("Either IPC or 'baseAddress' is required!")); -+ -+ err = (t_Error)fman_reset_mac(fpm_rg, macId, !!(type == e_FM_MAC_10G)); -+ -+ if (err == -EBUSY) -+ return ERROR_CODE(E_TIMEOUT); -+ else if (err) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal MAC ID")); -+ -+ return E_OK; -+} -+ -+t_Error FmSetMacMaxFrame(t_Handle h_Fm, e_FmMacType type, uint8_t macId, uint16_t mtu) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_FmIpcMacMaxFrameParams macMaxFrameLengthParams; -+ t_Error err; -+ t_FmIpcMsg msg; -+ -+ memset(&msg, 0, sizeof(msg)); -+ macMaxFrameLengthParams.macParams.id = macId; -+ macMaxFrameLengthParams.macParams.enumType = (uint32_t)type; -+ macMaxFrameLengthParams.maxFrameLength = (uint16_t)mtu; -+ msg.msgId = FM_SET_MAC_MAX_FRAME; -+ memcpy(msg.msgBody, &macMaxFrameLengthParams, sizeof(macMaxFrameLengthParams)); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId)+sizeof(macMaxFrameLengthParams), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ return E_OK; -+ } -+ else if (p_Fm->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without IPC!")); -+ -+ /* if port is already initialized, check that MaxFrameLength is smaller -+ * or equal to the port's max */ -+#if (defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS)) -+ if (type == e_FM_MAC_10G) -+ { -+ if ((!p_Fm->p_FmStateStruct->portMaxFrameLengths10G[macId]) -+ || (p_Fm->p_FmStateStruct->portMaxFrameLengths10G[macId] && -+ (mtu <= p_Fm->p_FmStateStruct->portMaxFrameLengths10G[macId]))) -+ p_Fm->p_FmStateStruct->macMaxFrameLengths10G[macId] = mtu; -+ else -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, ("MAC maxFrameLength is larger than Port maxFrameLength")); -+ -+ } -+ else -+#else -+ UNUSED(type); -+#endif /* (defined(FM_MAX_NUM_OF_10G_MACS) && ... */ -+ if ((!p_Fm->p_FmStateStruct->portMaxFrameLengths1G[macId]) -+ || (p_Fm->p_FmStateStruct->portMaxFrameLengths1G[macId] && -+ (mtu <= p_Fm->p_FmStateStruct->portMaxFrameLengths1G[macId]))) -+ p_Fm->p_FmStateStruct->macMaxFrameLengths1G[macId] = mtu; -+ else -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, ("MAC maxFrameLength is larger than Port maxFrameLength")); -+ -+ return E_OK; -+} -+ -+uint16_t FmGetClockFreq(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ /* for multicore environment: this depends on the -+ * fact that fmClkFreq was properly initialized at "init". */ -+ return p_Fm->p_FmStateStruct->fmClkFreq; -+} -+ -+uint16_t FmGetMacClockFreq(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ return p_Fm->p_FmStateStruct->fmMacClkFreq; -+} -+ -+uint32_t FmGetTimeStampScale(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ !p_Fm->baseAddr && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_Error err; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength, timeStamp; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_GET_TIMESTAMP_SCALE; -+ replyLength = sizeof(uint32_t) + sizeof(uint32_t); -+ if ((err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ { -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ return 0; -+ } -+ if (replyLength != (sizeof(uint32_t) + sizeof(uint32_t))) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ return 0; -+ } -+ -+ memcpy((uint8_t*)&timeStamp, reply.replyBody, sizeof(uint32_t)); -+ return timeStamp; -+ } -+ else if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ p_Fm->baseAddr) -+ { -+ if (!(GET_UINT32(p_Fm->p_FmFpmRegs->fmfp_tsc1) & FPM_TS_CTL_EN)) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("timestamp is not enabled!")); -+ return 0; -+ } -+ } -+ else if (p_Fm->guestId != NCSW_MASTER_ID) -+ DBG(WARNING, ("No IPC - can't validate FM if timestamp enabled.")); -+ -+ return p_Fm->p_FmStateStruct->count1MicroBit; -+} -+ -+t_Error FmEnableRamsEcc(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ -+ p_Fm->p_FmStateStruct->ramsEccOwners++; -+ p_Fm->p_FmStateStruct->internalCall = TRUE; -+ -+ return FM_EnableRamsEcc(p_Fm); -+} -+ -+t_Error FmDisableRamsEcc(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ -+ ASSERT_COND(p_Fm->p_FmStateStruct->ramsEccOwners); -+ p_Fm->p_FmStateStruct->ramsEccOwners--; -+ -+ if (p_Fm->p_FmStateStruct->ramsEccOwners==0) -+ { -+ p_Fm->p_FmStateStruct->internalCall = TRUE; -+ return FM_DisableRamsEcc(p_Fm); -+ } -+ -+ return E_OK; -+} -+ -+uint8_t FmGetGuestId(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ return p_Fm->guestId; -+} -+ -+bool FmIsMaster(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ return (p_Fm->guestId == NCSW_MASTER_ID); -+} -+ -+t_Error FmSetSizeOfFifo(t_Handle h_Fm, -+ uint8_t hardwarePortId, -+ uint32_t *p_SizeOfFifo, -+ uint32_t *p_ExtraSizeOfFifo, -+ bool initialConfig) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ t_FmIpcPortRsrcParams rsrcParams; -+ t_Error err; -+ struct fman_bmi_regs *bmi_rg = p_Fm->p_FmBmiRegs; -+ uint32_t sizeOfFifo = *p_SizeOfFifo, extraSizeOfFifo = *p_ExtraSizeOfFifo; -+ uint16_t currentVal = 0, currentExtraVal = 0; -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ !p_Fm->baseAddr && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength; -+ -+ rsrcParams.hardwarePortId = hardwarePortId; -+ rsrcParams.val = sizeOfFifo; -+ rsrcParams.extra = extraSizeOfFifo; -+ rsrcParams.boolInitialConfig = (uint8_t)initialConfig; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_SET_SIZE_OF_FIFO; -+ memcpy(msg.msgBody, &rsrcParams, sizeof(rsrcParams)); -+ replyLength = sizeof(uint32_t); -+ if ((err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(rsrcParams), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ if (replyLength != sizeof(uint32_t)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ return (t_Error)(reply.error); -+ } -+ else if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ p_Fm->baseAddr) -+ { -+ DBG(WARNING, ("No IPC - can't validate FM total-fifo size.")); -+ fman_set_size_of_fifo(bmi_rg, hardwarePortId, sizeOfFifo, extraSizeOfFifo); -+ } -+ else if (p_Fm->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without neither IPC nor mapped register!")); -+ -+ if (!initialConfig) -+ { -+ /* !initialConfig - runtime change of existing value. -+ * - read the current FIFO and extra FIFO size */ -+ currentExtraVal = fman_get_size_of_extra_fifo(bmi_rg, hardwarePortId); -+ currentVal = fman_get_size_of_fifo(bmi_rg, hardwarePortId); -+ } -+ -+ if (extraSizeOfFifo > currentExtraVal) -+ { -+ if (extraSizeOfFifo && !p_Fm->p_FmStateStruct->extraFifoPoolSize) -+ /* if this is the first time a port requires extraFifoPoolSize, the total extraFifoPoolSize -+ * must be initialized to 1 buffer per port -+ */ -+ p_Fm->p_FmStateStruct->extraFifoPoolSize = FM_MAX_NUM_OF_RX_PORTS*BMI_FIFO_UNITS; -+ -+ p_Fm->p_FmStateStruct->extraFifoPoolSize = MAX(p_Fm->p_FmStateStruct->extraFifoPoolSize, extraSizeOfFifo); -+ } -+ -+ /* check that there are enough uncommitted fifo size */ -+ if ((p_Fm->p_FmStateStruct->accumulatedFifoSize - currentVal + sizeOfFifo) > -+ (p_Fm->p_FmStateStruct->totalFifoSize - p_Fm->p_FmStateStruct->extraFifoPoolSize)){ -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("Port request fifo size + accumulated size > total FIFO size:")); -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, -+ ("port 0x%x requested %d bytes, extra size = %d, accumulated size = %d total size = %d", -+ hardwarePortId, sizeOfFifo, p_Fm->p_FmStateStruct->extraFifoPoolSize, -+ p_Fm->p_FmStateStruct->accumulatedFifoSize, -+ p_Fm->p_FmStateStruct->totalFifoSize)); -+ } -+ else -+ { -+ /* update accumulated */ -+ ASSERT_COND(p_Fm->p_FmStateStruct->accumulatedFifoSize >= currentVal); -+ p_Fm->p_FmStateStruct->accumulatedFifoSize -= currentVal; -+ p_Fm->p_FmStateStruct->accumulatedFifoSize += sizeOfFifo; -+ fman_set_size_of_fifo(bmi_rg, hardwarePortId, sizeOfFifo, extraSizeOfFifo); -+ } -+ -+ return E_OK; -+} -+ -+t_Error FmSetNumOfTasks(t_Handle h_Fm, -+ uint8_t hardwarePortId, -+ uint8_t *p_NumOfTasks, -+ uint8_t *p_NumOfExtraTasks, -+ bool initialConfig) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_Fm; -+ t_Error err; -+ struct fman_bmi_regs *bmi_rg = p_Fm->p_FmBmiRegs; -+ uint8_t currentVal = 0, currentExtraVal = 0, numOfTasks = *p_NumOfTasks, numOfExtraTasks = *p_NumOfExtraTasks; -+ -+ ASSERT_COND(IN_RANGE(1, hardwarePortId, 63)); -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ !p_Fm->baseAddr && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_FmIpcPortRsrcParams rsrcParams; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength; -+ -+ rsrcParams.hardwarePortId = hardwarePortId; -+ rsrcParams.val = numOfTasks; -+ rsrcParams.extra = numOfExtraTasks; -+ rsrcParams.boolInitialConfig = (uint8_t)initialConfig; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_SET_NUM_OF_TASKS; -+ memcpy(msg.msgBody, &rsrcParams, sizeof(rsrcParams)); -+ replyLength = sizeof(uint32_t); -+ if ((err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(rsrcParams), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ if (replyLength != sizeof(uint32_t)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ return (t_Error)(reply.error); -+ } -+ else if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ p_Fm->baseAddr) -+ { -+ DBG(WARNING, ("No IPC - can't validate FM total-num-of-tasks.")); -+ fman_set_num_of_tasks(bmi_rg, hardwarePortId, numOfTasks, numOfExtraTasks); -+ } -+ else if (p_Fm->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without neither IPC nor mapped register!")); -+ -+ if (!initialConfig) -+ { -+ /* !initialConfig - runtime change of existing value. -+ * - read the current number of tasks */ -+ currentVal = fman_get_num_of_tasks(bmi_rg, hardwarePortId); -+ currentExtraVal = fman_get_num_extra_tasks(bmi_rg, hardwarePortId); -+ } -+ -+ if (numOfExtraTasks > currentExtraVal) -+ p_Fm->p_FmStateStruct->extraTasksPoolSize = -+ (uint8_t)MAX(p_Fm->p_FmStateStruct->extraTasksPoolSize, numOfExtraTasks); -+ -+ /* check that there are enough uncommitted tasks */ -+ if ((p_Fm->p_FmStateStruct->accumulatedNumOfTasks - currentVal + numOfTasks) > -+ (p_Fm->p_FmStateStruct->totalNumOfTasks - p_Fm->p_FmStateStruct->extraTasksPoolSize)) -+ RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, -+ ("Requested numOfTasks and extra tasks pool for fm%d exceed total numOfTasks.", -+ p_Fm->p_FmStateStruct->fmId)); -+ else -+ { -+ ASSERT_COND(p_Fm->p_FmStateStruct->accumulatedNumOfTasks >= currentVal); -+ /* update accumulated */ -+ p_Fm->p_FmStateStruct->accumulatedNumOfTasks -= currentVal; -+ p_Fm->p_FmStateStruct->accumulatedNumOfTasks += numOfTasks; -+ fman_set_num_of_tasks(bmi_rg, hardwarePortId, numOfTasks, numOfExtraTasks); -+ } -+ -+ return E_OK; -+} -+ -+t_Error FmSetNumOfOpenDmas(t_Handle h_Fm, -+ uint8_t hardwarePortId, -+ uint8_t *p_NumOfOpenDmas, -+ uint8_t *p_NumOfExtraOpenDmas, -+ bool initialConfig) -+ -+{ -+ t_Fm *p_Fm = (t_Fm *)h_Fm; -+ t_Error err; -+ struct fman_bmi_regs *bmi_rg = p_Fm->p_FmBmiRegs; -+ uint8_t numOfOpenDmas = *p_NumOfOpenDmas, numOfExtraOpenDmas = *p_NumOfExtraOpenDmas; -+ uint8_t totalNumDmas = 0, currentVal = 0, currentExtraVal = 0; -+ -+ ASSERT_COND(IN_RANGE(1, hardwarePortId, 63)); -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ !p_Fm->baseAddr && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_FmIpcPortRsrcParams rsrcParams; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength; -+ -+ rsrcParams.hardwarePortId = hardwarePortId; -+ rsrcParams.val = numOfOpenDmas; -+ rsrcParams.extra = numOfExtraOpenDmas; -+ rsrcParams.boolInitialConfig = (uint8_t)initialConfig; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_SET_NUM_OF_OPEN_DMAS; -+ memcpy(msg.msgBody, &rsrcParams, sizeof(rsrcParams)); -+ replyLength = sizeof(uint32_t); -+ if ((err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) + sizeof(rsrcParams), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ if (replyLength != sizeof(uint32_t)) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ return (t_Error)(reply.error); -+ } -+#ifdef FM_HAS_TOTAL_DMAS -+ else if (p_Fm->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("running in guest-mode without IPC!")); -+#else -+ else if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ p_Fm->baseAddr && -+ (p_Fm->p_FmStateStruct->revInfo.majorRev >= 6)) -+ { -+ /*DBG(WARNING, ("No IPC - can't validate FM total-num-of-dmas."));*/ -+ -+ if (!numOfOpenDmas) -+ { -+ /* first config without explic it value: Do Nothing - reset value shouldn't be -+ changed, read register for port save */ -+ *p_NumOfOpenDmas = fman_get_num_of_dmas(bmi_rg, hardwarePortId); -+ *p_NumOfExtraOpenDmas = fman_get_num_extra_dmas(bmi_rg, hardwarePortId); -+ } -+ else -+ /* whether it is the first time with explicit value, or runtime "set" - write register */ -+ fman_set_num_of_open_dmas(bmi_rg, -+ hardwarePortId, -+ numOfOpenDmas, -+ numOfExtraOpenDmas, -+ p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas + p_Fm->p_FmStateStruct->extraOpenDmasPoolSize); -+ } -+ else if (p_Fm->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without neither IPC nor mapped register!")); -+#endif /* FM_HAS_TOTAL_DMAS */ -+ -+ if (!initialConfig) -+ { -+ /* !initialConfig - runtime change of existing value. -+ * - read the current number of open Dma's */ -+ currentExtraVal = fman_get_num_extra_dmas(bmi_rg, hardwarePortId); -+ currentVal = fman_get_num_of_dmas(bmi_rg, hardwarePortId); -+ } -+ -+#ifdef FM_NO_GUARANTEED_RESET_VALUES -+ /* it's illegal to be in a state where this is not the first set and no value is specified */ -+ ASSERT_COND(initialConfig || numOfOpenDmas); -+ if (!numOfOpenDmas) -+ { -+ /* !numOfOpenDmas - first configuration according to values in regs. -+ * - read the current number of open Dma's */ -+ currentExtraVal = fman_get_num_extra_dmas(bmi_rg, hardwarePortId); -+ currentVal = fman_get_num_of_dmas(bmi_rg, hardwarePortId); -+ /* This is the first configuration and user did not specify value (!numOfOpenDmas), -+ * reset values will be used and we just save these values for resource management */ -+ p_Fm->p_FmStateStruct->extraOpenDmasPoolSize = -+ (uint8_t)MAX(p_Fm->p_FmStateStruct->extraOpenDmasPoolSize, currentExtraVal); -+ p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas += currentVal; -+ *p_NumOfOpenDmas = currentVal; -+ *p_NumOfExtraOpenDmas = currentExtraVal; -+ return E_OK; -+ } -+#endif /* FM_NO_GUARANTEED_RESET_VALUES */ -+ -+ if (numOfExtraOpenDmas > currentExtraVal) -+ p_Fm->p_FmStateStruct->extraOpenDmasPoolSize = -+ (uint8_t)MAX(p_Fm->p_FmStateStruct->extraOpenDmasPoolSize, numOfExtraOpenDmas); -+ -+#ifdef FM_HAS_TOTAL_DMAS -+ if ((p_Fm->p_FmStateStruct->revInfo.majorRev < 6) && -+ (p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas - currentVal + numOfOpenDmas > -+ p_Fm->p_FmStateStruct->maxNumOfOpenDmas)) -+ RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, -+ ("Requested numOfOpenDmas for fm%d exceeds total numOfOpenDmas.", -+ p_Fm->p_FmStateStruct->fmId)); -+#else -+ if ((p_Fm->p_FmStateStruct->revInfo.majorRev >= 6) && -+#ifdef FM_HEAVY_TRAFFIC_SEQUENCER_HANG_ERRATA_FMAN_A006981 -+ !((p_Fm->p_FmStateStruct->revInfo.majorRev == 6) && -+ (p_Fm->p_FmStateStruct->revInfo.minorRev == 0)) && -+#endif /* FM_HEAVY_TRAFFIC_SEQUENCER_HANG_ERRATA_FMAN_A006981 */ -+ (p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas - currentVal + numOfOpenDmas > DMA_THRESH_MAX_COMMQ + 1)) -+ RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, -+ ("Requested numOfOpenDmas for fm%d exceeds DMA Command queue (%d)", -+ p_Fm->p_FmStateStruct->fmId, DMA_THRESH_MAX_COMMQ+1)); -+#endif /* FM_HAS_TOTAL_DMAS */ -+ else -+ { -+ ASSERT_COND(p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas >= currentVal); -+ /* update acummulated */ -+ p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas -= currentVal; -+ p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas += numOfOpenDmas; -+ -+#ifdef FM_HAS_TOTAL_DMAS -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev < 6) -+ totalNumDmas = (uint8_t)(p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas + p_Fm->p_FmStateStruct->extraOpenDmasPoolSize); -+#endif /* FM_HAS_TOTAL_DMAS */ -+ fman_set_num_of_open_dmas(bmi_rg, -+ hardwarePortId, -+ numOfOpenDmas, -+ numOfExtraOpenDmas, -+ totalNumDmas); -+ } -+ -+ return E_OK; -+} -+ -+#if (DPAA_VERSION >= 11) -+t_Error FmVSPCheckRelativeProfile(t_Handle h_Fm, -+ e_FmPortType portType, -+ uint8_t portId, -+ uint16_t relativeProfile) -+{ -+ t_Fm *p_Fm; -+ t_FmSp *p_FmPcdSp; -+ uint8_t swPortIndex=0, hardwarePortId; -+ -+ ASSERT_COND(h_Fm); -+ p_Fm = (t_Fm*)h_Fm; -+ -+ hardwarePortId = SwPortIdToHwPortId(portType, -+ portId, -+ p_Fm->p_FmStateStruct->revInfo.majorRev, -+ p_Fm->p_FmStateStruct->revInfo.minorRev); -+ ASSERT_COND(hardwarePortId); -+ HW_PORT_ID_TO_SW_PORT_INDX(swPortIndex, hardwarePortId); -+ -+ p_FmPcdSp = p_Fm->p_FmSp; -+ ASSERT_COND(p_FmPcdSp); -+ -+ if (!p_FmPcdSp->portsMapping[swPortIndex].numOfProfiles) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE , ("Port has no allocated profiles")); -+ if (relativeProfile >= p_FmPcdSp->portsMapping[swPortIndex].numOfProfiles) -+ RETURN_ERROR(MAJOR, E_NOT_IN_RANGE , ("Profile id is out of range")); -+ -+ return E_OK; -+} -+ -+t_Error FmVSPGetAbsoluteProfileId(t_Handle h_Fm, -+ e_FmPortType portType, -+ uint8_t portId, -+ uint16_t relativeProfile, -+ uint16_t *p_AbsoluteId) -+{ -+ t_Fm *p_Fm; -+ t_FmSp *p_FmPcdSp; -+ uint8_t swPortIndex=0, hardwarePortId; -+ t_Error err; -+ -+ ASSERT_COND(h_Fm); -+ p_Fm = (t_Fm*)h_Fm; -+ -+ err = FmVSPCheckRelativeProfile(h_Fm, portType, portId, relativeProfile); -+ if (err != E_OK) -+ return err; -+ -+ hardwarePortId = SwPortIdToHwPortId(portType, -+ portId, -+ p_Fm->p_FmStateStruct->revInfo.majorRev, -+ p_Fm->p_FmStateStruct->revInfo.minorRev); -+ ASSERT_COND(hardwarePortId); -+ HW_PORT_ID_TO_SW_PORT_INDX(swPortIndex, hardwarePortId); -+ -+ p_FmPcdSp = p_Fm->p_FmSp; -+ ASSERT_COND(p_FmPcdSp); -+ -+ *p_AbsoluteId = (uint16_t)(p_FmPcdSp->portsMapping[swPortIndex].profilesBase + relativeProfile); -+ -+ return E_OK; -+} -+#endif /* (DPAA_VERSION >= 11) */ -+ -+static t_Error InitFmDma(t_Fm *p_Fm) -+{ -+ t_Error err; -+ -+ err = (t_Error)fman_dma_init(p_Fm->p_FmDmaRegs, p_Fm->p_FmDriverParam); -+ if (err != E_OK) -+ return err; -+ -+ /* Allocate MURAM for CAM */ -+ p_Fm->camBaseAddr = PTR_TO_UINT(FM_MURAM_AllocMem(p_Fm->h_FmMuram, -+ (uint32_t)(p_Fm->p_FmDriverParam->dma_cam_num_of_entries*DMA_CAM_SIZEOF_ENTRY), -+ DMA_CAM_ALIGN)); -+ if (!p_Fm->camBaseAddr) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM alloc for DMA CAM failed")); -+ -+ WRITE_BLOCK(UINT_TO_PTR(p_Fm->camBaseAddr), -+ 0, -+ (uint32_t)(p_Fm->p_FmDriverParam->dma_cam_num_of_entries*DMA_CAM_SIZEOF_ENTRY)); -+ -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev == 2) -+ { -+ FM_MURAM_FreeMem(p_Fm->h_FmMuram, UINT_TO_PTR(p_Fm->camBaseAddr)); -+ -+ p_Fm->camBaseAddr = PTR_TO_UINT(FM_MURAM_AllocMem(p_Fm->h_FmMuram, -+ (uint32_t)(p_Fm->p_FmDriverParam->dma_cam_num_of_entries*72 + 128), -+ 64)); -+ if (!p_Fm->camBaseAddr) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM alloc for DMA CAM failed")); -+ -+ WRITE_BLOCK(UINT_TO_PTR(p_Fm->camBaseAddr), -+ 0, -+ (uint32_t)(p_Fm->p_FmDriverParam->dma_cam_num_of_entries*72 + 128)); -+ -+ switch(p_Fm->p_FmDriverParam->dma_cam_num_of_entries) -+ { -+ case (8): -+ WRITE_UINT32(*(uint32_t*)p_Fm->camBaseAddr, 0xff000000); -+ break; -+ case (16): -+ WRITE_UINT32(*(uint32_t*)p_Fm->camBaseAddr, 0xffff0000); -+ break; -+ case (24): -+ WRITE_UINT32(*(uint32_t*)p_Fm->camBaseAddr, 0xffffff00); -+ break; -+ case (32): -+ WRITE_UINT32(*(uint32_t*)p_Fm->camBaseAddr, 0xffffffff); -+ break; -+ default: -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("wrong dma_cam_num_of_entries")); -+ } -+ } -+ -+ p_Fm->p_FmDriverParam->cam_base_addr = -+ (uint32_t)(XX_VirtToPhys(UINT_TO_PTR(p_Fm->camBaseAddr)) - p_Fm->fmMuramPhysBaseAddr); -+ -+ return E_OK; -+} -+ -+static t_Error InitFmFpm(t_Fm *p_Fm) -+{ -+ return (t_Error)fman_fpm_init(p_Fm->p_FmFpmRegs, p_Fm->p_FmDriverParam); -+} -+ -+static t_Error InitFmBmi(t_Fm *p_Fm) -+{ -+ return (t_Error)fman_bmi_init(p_Fm->p_FmBmiRegs, p_Fm->p_FmDriverParam); -+} -+ -+static t_Error InitFmQmi(t_Fm *p_Fm) -+{ -+ return (t_Error)fman_qmi_init(p_Fm->p_FmQmiRegs, p_Fm->p_FmDriverParam); -+} -+ -+static t_Error InitGuestMode(t_Fm *p_Fm) -+{ -+ t_Error err = E_OK; -+ int i; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength; -+ -+ ASSERT_COND(p_Fm); -+ ASSERT_COND(p_Fm->guestId != NCSW_MASTER_ID); -+ -+ /* build the FM guest partition IPC address */ -+ if (Sprint (p_Fm->fmModuleName, "FM_%d_%d",p_Fm->p_FmStateStruct->fmId, p_Fm->guestId) != (p_Fm->guestId<10 ? 6:7)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Sprint failed")); -+ -+ /* build the FM master partition IPC address */ -+ memset(p_Fm->fmIpcHandlerModuleName, 0, (sizeof(char)) * MODULE_NAME_SIZE); -+ if (Sprint (p_Fm->fmIpcHandlerModuleName[0], "FM_%d_%d",p_Fm->p_FmStateStruct->fmId, NCSW_MASTER_ID) != 6) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Sprint failed")); -+ -+ for (i=0;iintrMng[i].f_Isr = UnimplementedIsr; -+ -+ p_Fm->h_IpcSessions[0] = XX_IpcInitSession(p_Fm->fmIpcHandlerModuleName[0], p_Fm->fmModuleName); -+ if (p_Fm->h_IpcSessions[0]) -+ { -+ uint8_t isMasterAlive; -+ t_FmIpcParams ipcParams; -+ -+ err = XX_IpcRegisterMsgHandler(p_Fm->fmModuleName, FmGuestHandleIpcMsgCB, p_Fm, FM_IPC_MAX_REPLY_SIZE); -+ if (err) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_MASTER_IS_ALIVE; -+ msg.msgBody[0] = p_Fm->guestId; -+ replyLength = sizeof(uint32_t) + sizeof(uint8_t); -+ do -+ { -+ blockingFlag = TRUE; -+ if ((err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId)+sizeof(p_Fm->guestId), -+ (uint8_t*)&reply, -+ &replyLength, -+ IpcMsgCompletionCB, -+ p_Fm)) != E_OK) -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ while (blockingFlag) ; -+ if (replyLength != (sizeof(uint32_t) + sizeof(uint8_t))) -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ isMasterAlive = *(uint8_t*)(reply.replyBody); -+ } while (!isMasterAlive); -+ -+ /* read FM parameters and save */ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_GET_PARAMS; -+ replyLength = sizeof(uint32_t) + sizeof(t_FmIpcParams); -+ if ((err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ if (replyLength != (sizeof(uint32_t) + sizeof(t_FmIpcParams))) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ memcpy((uint8_t*)&ipcParams, reply.replyBody, sizeof(t_FmIpcParams)); -+ -+ p_Fm->p_FmStateStruct->fmClkFreq = ipcParams.fmClkFreq; -+ p_Fm->p_FmStateStruct->fmMacClkFreq = ipcParams.fmMacClkFreq; -+ p_Fm->p_FmStateStruct->revInfo.majorRev = ipcParams.majorRev; -+ p_Fm->p_FmStateStruct->revInfo.minorRev = ipcParams.minorRev; -+ } -+ else -+ { -+ DBG(WARNING, ("FM Guest mode - without IPC")); -+ if (!p_Fm->p_FmStateStruct->fmClkFreq) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("No fmClkFreq configured for guest without IPC")); -+ if (p_Fm->baseAddr) -+ { -+ fman_get_revision(p_Fm->p_FmFpmRegs, -+ &p_Fm->p_FmStateStruct->revInfo.majorRev, -+ &p_Fm->p_FmStateStruct->revInfo.minorRev); -+ -+ } -+ } -+ -+#if (DPAA_VERSION >= 11) -+ p_Fm->partVSPBase = AllocVSPsForPartition(p_Fm, p_Fm->partVSPBase, p_Fm->partNumOfVSPs, p_Fm->guestId); -+ if (p_Fm->partVSPBase == (uint8_t)(ILLEGAL_BASE)) -+ DBG(WARNING, ("partition VSPs allocation is FAILED")); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ /* General FM driver initialization */ -+ if (p_Fm->baseAddr) -+ p_Fm->fmMuramPhysBaseAddr = -+ (uint64_t)(XX_VirtToPhys(UINT_TO_PTR(p_Fm->baseAddr + FM_MM_MURAM))); -+ -+ XX_Free(p_Fm->p_FmDriverParam); -+ p_Fm->p_FmDriverParam = NULL; -+ -+ if ((p_Fm->guestId == NCSW_MASTER_ID) || -+ (p_Fm->h_IpcSessions[0])) -+ { -+ FM_DisableRamsEcc(p_Fm); -+ FmMuramClear(p_Fm->h_FmMuram); -+ FM_EnableRamsEcc(p_Fm); -+ } -+ -+ return E_OK; -+} -+ -+static __inline__ enum fman_exceptions FmanExceptionTrans(e_FmExceptions exception) -+{ -+ switch (exception) { -+ case e_FM_EX_DMA_BUS_ERROR: -+ return E_FMAN_EX_DMA_BUS_ERROR; -+ case e_FM_EX_DMA_READ_ECC: -+ return E_FMAN_EX_DMA_READ_ECC; -+ case e_FM_EX_DMA_SYSTEM_WRITE_ECC: -+ return E_FMAN_EX_DMA_SYSTEM_WRITE_ECC; -+ case e_FM_EX_DMA_FM_WRITE_ECC: -+ return E_FMAN_EX_DMA_FM_WRITE_ECC; -+ case e_FM_EX_FPM_STALL_ON_TASKS: -+ return E_FMAN_EX_FPM_STALL_ON_TASKS; -+ case e_FM_EX_FPM_SINGLE_ECC: -+ return E_FMAN_EX_FPM_SINGLE_ECC; -+ case e_FM_EX_FPM_DOUBLE_ECC: -+ return E_FMAN_EX_FPM_DOUBLE_ECC; -+ case e_FM_EX_QMI_SINGLE_ECC: -+ return E_FMAN_EX_QMI_SINGLE_ECC; -+ case e_FM_EX_QMI_DOUBLE_ECC: -+ return E_FMAN_EX_QMI_DOUBLE_ECC; -+ case e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: -+ return E_FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID; -+ case e_FM_EX_BMI_LIST_RAM_ECC: -+ return E_FMAN_EX_BMI_LIST_RAM_ECC; -+ case e_FM_EX_BMI_STORAGE_PROFILE_ECC: -+ return E_FMAN_EX_BMI_STORAGE_PROFILE_ECC; -+ case e_FM_EX_BMI_STATISTICS_RAM_ECC: -+ return E_FMAN_EX_BMI_STATISTICS_RAM_ECC; -+ case e_FM_EX_BMI_DISPATCH_RAM_ECC: -+ return E_FMAN_EX_BMI_DISPATCH_RAM_ECC; -+ case e_FM_EX_IRAM_ECC: -+ return E_FMAN_EX_IRAM_ECC; -+ case e_FM_EX_MURAM_ECC: -+ return E_FMAN_EX_MURAM_ECC; -+ default: -+ return E_FMAN_EX_DMA_BUS_ERROR; -+ } -+} -+ -+uint8_t SwPortIdToHwPortId(e_FmPortType type, uint8_t relativePortId, uint8_t majorRev, uint8_t minorRev) -+{ -+ switch (type) -+ { -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ case (e_FM_PORT_TYPE_OH_HOST_COMMAND): -+ CHECK_PORT_ID_OH_PORTS(relativePortId); -+ return (uint8_t)(BASE_OH_PORTID + (relativePortId)); -+ case (e_FM_PORT_TYPE_RX): -+ CHECK_PORT_ID_1G_RX_PORTS(relativePortId); -+ return (uint8_t)(BASE_1G_RX_PORTID + (relativePortId)); -+ case (e_FM_PORT_TYPE_RX_10G): -+ /* The 10G port in T1024 (FMan Version 6.4) is the first port. -+ * This is the reason why the 1G port offset is used. -+ */ -+ if (majorRev == 6 && minorRev == 4) -+ { -+ CHECK_PORT_ID_1G_RX_PORTS(relativePortId); -+ return (uint8_t)(BASE_1G_RX_PORTID + (relativePortId)); -+ } -+ else -+ { -+ CHECK_PORT_ID_10G_RX_PORTS(relativePortId); -+ return (uint8_t)(BASE_10G_RX_PORTID + (relativePortId)); -+ } -+ case (e_FM_PORT_TYPE_TX): -+ CHECK_PORT_ID_1G_TX_PORTS(relativePortId); -+ return (uint8_t)(BASE_1G_TX_PORTID + (relativePortId)); -+ case (e_FM_PORT_TYPE_TX_10G): -+ /* The 10G port in T1024 (FMan Version 6.4) is the first port. -+ * This is the reason why the 1G port offset is used. -+ */ -+ if (majorRev == 6 && minorRev == 4) -+ { -+ CHECK_PORT_ID_1G_TX_PORTS(relativePortId); -+ return (uint8_t)(BASE_1G_TX_PORTID + (relativePortId)); -+ } -+ else -+ { -+ CHECK_PORT_ID_10G_TX_PORTS(relativePortId); -+ return (uint8_t)(BASE_10G_TX_PORTID + (relativePortId)); -+ } -+ default: -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal port type")); -+ return 0; -+ } -+} -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+t_Error FmDumpPortRegs (t_Handle h_Fm, uint8_t hardwarePortId) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_Fm; -+ -+ DECLARE_DUMP; -+ -+ ASSERT_COND(IN_RANGE(1, hardwarePortId, 63)); -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(((p_Fm->guestId == NCSW_MASTER_ID) || -+ p_Fm->baseAddr), E_INVALID_OPERATION); -+ -+ DUMP_TITLE(&p_Fm->p_FmBmiRegs->fmbm_pp[hardwarePortId-1], ("fmbm_pp for port %u", (hardwarePortId))); -+ DUMP_MEMORY(&p_Fm->p_FmBmiRegs->fmbm_pp[hardwarePortId-1], sizeof(uint32_t)); -+ -+ DUMP_TITLE(&p_Fm->p_FmBmiRegs->fmbm_pfs[hardwarePortId-1], ("fmbm_pfs for port %u", (hardwarePortId ))); -+ DUMP_MEMORY(&p_Fm->p_FmBmiRegs->fmbm_pfs[hardwarePortId-1], sizeof(uint32_t)); -+ -+ DUMP_TITLE(&p_Fm->p_FmBmiRegs->fmbm_spliodn[hardwarePortId-1], ("fmbm_spliodn for port %u", (hardwarePortId))); -+ DUMP_MEMORY(&p_Fm->p_FmBmiRegs->fmbm_spliodn[hardwarePortId-1], sizeof(uint32_t)); -+ -+ DUMP_TITLE(&p_Fm->p_FmFpmRegs->fmfp_ps[hardwarePortId], ("fmfp_ps for port %u", (hardwarePortId))); -+ DUMP_MEMORY(&p_Fm->p_FmFpmRegs->fmfp_ps[hardwarePortId], sizeof(uint32_t)); -+ -+ DUMP_TITLE(&p_Fm->p_FmDmaRegs->fmdmplr[hardwarePortId/2], ("fmdmplr for port %u", (hardwarePortId))); -+ DUMP_MEMORY(&p_Fm->p_FmDmaRegs->fmdmplr[hardwarePortId/2], sizeof(uint32_t)); -+ -+ return E_OK; -+} -+#endif /* (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) */ -+ -+ -+/*****************************************************************************/ -+/* API Init unit functions */ -+/*****************************************************************************/ -+t_Handle FM_Config(t_FmParams *p_FmParam) -+{ -+ t_Fm *p_Fm; -+ uint8_t i; -+ uintptr_t baseAddr; -+ -+ SANITY_CHECK_RETURN_VALUE(p_FmParam, E_NULL_POINTER, NULL); -+ SANITY_CHECK_RETURN_VALUE(((p_FmParam->firmware.p_Code && p_FmParam->firmware.size) || -+ (!p_FmParam->firmware.p_Code && !p_FmParam->firmware.size)), -+ E_INVALID_VALUE, NULL); -+ -+ baseAddr = p_FmParam->baseAddr; -+ -+ /* Allocate FM structure */ -+ p_Fm = (t_Fm *) XX_Malloc(sizeof(t_Fm)); -+ if (!p_Fm) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM driver structure")); -+ return NULL; -+ } -+ memset(p_Fm, 0, sizeof(t_Fm)); -+ -+ p_Fm->p_FmStateStruct = (t_FmStateStruct *) XX_Malloc(sizeof(t_FmStateStruct)); -+ if (!p_Fm->p_FmStateStruct) -+ { -+ XX_Free(p_Fm); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM Status structure")); -+ return NULL; -+ } -+ memset(p_Fm->p_FmStateStruct, 0, sizeof(t_FmStateStruct)); -+ -+ /* Initialize FM parameters which will be kept by the driver */ -+ p_Fm->p_FmStateStruct->fmId = p_FmParam->fmId; -+ p_Fm->guestId = p_FmParam->guestId; -+ -+ for (i=0; ip_FmStateStruct->portsTypes[i] = e_FM_PORT_TYPE_DUMMY; -+ -+ /* Allocate the FM driver's parameters structure */ -+ p_Fm->p_FmDriverParam = (struct fman_cfg *)XX_Malloc(sizeof(struct fman_cfg)); -+ if (!p_Fm->p_FmDriverParam) -+ { -+ XX_Free(p_Fm->p_FmStateStruct); -+ XX_Free(p_Fm); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM driver parameters")); -+ return NULL; -+ } -+ memset(p_Fm->p_FmDriverParam, 0, sizeof(struct fman_cfg)); -+ -+#if (DPAA_VERSION >= 11) -+ p_Fm->p_FmSp = (t_FmSp *)XX_Malloc(sizeof(t_FmSp)); -+ if (!p_Fm->p_FmSp) -+ { -+ XX_Free(p_Fm->p_FmDriverParam); -+ XX_Free(p_Fm->p_FmStateStruct); -+ XX_Free(p_Fm); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("allocation for internal data structure failed")); -+ return NULL; -+ } -+ memset(p_Fm->p_FmSp, 0, sizeof(t_FmSp)); -+ -+ for (i=0; ip_FmSp->profiles[i].profilesMng.ownerId = (uint8_t)ILLEGAL_BASE; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ /* Initialize FM parameters which will be kept by the driver */ -+ p_Fm->p_FmStateStruct->fmId = p_FmParam->fmId; -+ p_Fm->h_FmMuram = p_FmParam->h_FmMuram; -+ p_Fm->h_App = p_FmParam->h_App; -+ p_Fm->p_FmStateStruct->fmClkFreq = p_FmParam->fmClkFreq; -+ p_Fm->p_FmStateStruct->fmMacClkFreq = p_FmParam->fmClkFreq / ((!p_FmParam->fmMacClkRatio)? 2: p_FmParam->fmMacClkRatio); -+ p_Fm->f_Exception = p_FmParam->f_Exception; -+ p_Fm->f_BusError = p_FmParam->f_BusError; -+ p_Fm->p_FmFpmRegs = (struct fman_fpm_regs *)UINT_TO_PTR(baseAddr + FM_MM_FPM); -+ p_Fm->p_FmBmiRegs = (struct fman_bmi_regs *)UINT_TO_PTR(baseAddr + FM_MM_BMI); -+ p_Fm->p_FmQmiRegs = (struct fman_qmi_regs *)UINT_TO_PTR(baseAddr + FM_MM_QMI); -+ p_Fm->p_FmDmaRegs = (struct fman_dma_regs *)UINT_TO_PTR(baseAddr + FM_MM_DMA); -+ p_Fm->p_FmRegs = (struct fman_regs *)UINT_TO_PTR(baseAddr + FM_MM_BMI); -+ p_Fm->baseAddr = baseAddr; -+ p_Fm->p_FmStateStruct->irq = p_FmParam->irq; -+ p_Fm->p_FmStateStruct->errIrq = p_FmParam->errIrq; -+ p_Fm->hcPortInitialized = FALSE; -+ p_Fm->independentMode = FALSE; -+ -+ p_Fm->h_Spinlock = XX_InitSpinlock(); -+ if (!p_Fm->h_Spinlock) -+ { -+ XX_Free(p_Fm->p_FmDriverParam); -+ XX_Free(p_Fm->p_FmStateStruct); -+ XX_Free(p_Fm); -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("can't allocate spinlock!")); -+ return NULL; -+ } -+ -+#if (DPAA_VERSION >= 11) -+ p_Fm->partVSPBase = p_FmParam->partVSPBase; -+ p_Fm->partNumOfVSPs = p_FmParam->partNumOfVSPs; -+ p_Fm->vspBaseAddr = p_FmParam->vspBaseAddr; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ fman_defconfig(p_Fm->p_FmDriverParam, -+ !!(p_Fm->guestId == NCSW_MASTER_ID)); -+/* overide macros dependent parameters */ -+#ifdef FM_PEDANTIC_DMA -+ p_Fm->p_FmDriverParam->pedantic_dma = TRUE; -+ p_Fm->p_FmDriverParam->dma_aid_override = TRUE; -+#endif /* FM_PEDANTIC_DMA */ -+#ifndef FM_QMI_NO_DEQ_OPTIONS_SUPPORT -+ p_Fm->p_FmDriverParam->qmi_deq_option_support = TRUE; -+#endif /* !FM_QMI_NO_DEQ_OPTIONS_SUPPORT */ -+ -+ p_Fm->p_FmStateStruct->ramsEccEnable = FALSE; -+ p_Fm->p_FmStateStruct->extraFifoPoolSize = 0; -+ p_Fm->p_FmStateStruct->exceptions = DEFAULT_exceptions; -+ p_Fm->resetOnInit = DEFAULT_resetOnInit; -+ p_Fm->fwVerify = DEFAULT_VerifyUcode; -+ p_Fm->firmware.size = p_FmParam->firmware.size; -+ if (p_Fm->firmware.size) -+ { -+ p_Fm->firmware.p_Code = (uint32_t *)XX_Malloc(p_Fm->firmware.size); -+ if (!p_Fm->firmware.p_Code) -+ { -+ XX_FreeSpinlock(p_Fm->h_Spinlock); -+ XX_Free(p_Fm->p_FmStateStruct); -+ XX_Free(p_Fm->p_FmDriverParam); -+ XX_Free(p_Fm); -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM firmware code")); -+ return NULL; -+ } -+ memcpy(p_Fm->firmware.p_Code, p_FmParam->firmware.p_Code ,p_Fm->firmware.size); -+ } -+ -+ if (p_Fm->guestId != NCSW_MASTER_ID) -+ return p_Fm; -+ -+ /* read revision */ -+ /* Chip dependent, will be configured in Init */ -+ fman_get_revision(p_Fm->p_FmFpmRegs, -+ &p_Fm->p_FmStateStruct->revInfo.majorRev, -+ &p_Fm->p_FmStateStruct->revInfo.minorRev); -+ -+#ifdef FM_AID_MODE_NO_TNUM_SW005 -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev >= 6) -+ p_Fm->p_FmDriverParam->dma_aid_mode = e_FM_DMA_AID_OUT_PORT_ID; -+#endif /* FM_AID_MODE_NO_TNUM_SW005 */ -+#ifndef FM_QMI_NO_DEQ_OPTIONS_SUPPORT -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev != 4) -+ p_Fm->p_FmDriverParam->qmi_def_tnums_thresh = QMI_DEF_TNUMS_THRESH; -+#endif /* FM_QMI_NO_DEQ_OPTIONS_SUPPORT */ -+ -+ p_Fm->p_FmStateStruct->totalFifoSize = 0; -+ p_Fm->p_FmStateStruct->totalNumOfTasks = -+ DEFAULT_totalNumOfTasks(p_Fm->p_FmStateStruct->revInfo.majorRev, -+ p_Fm->p_FmStateStruct->revInfo.minorRev); -+ -+#ifdef FM_HAS_TOTAL_DMAS -+ p_Fm->p_FmStateStruct->maxNumOfOpenDmas = BMI_MAX_NUM_OF_DMAS; -+#endif /* FM_HAS_TOTAL_DMAS */ -+#if (DPAA_VERSION < 11) -+ p_Fm->p_FmDriverParam->dma_comm_qtsh_clr_emer = DEFAULT_dmaCommQLow; -+ p_Fm->p_FmDriverParam->dma_comm_qtsh_asrt_emer = DEFAULT_dmaCommQHigh; -+ p_Fm->p_FmDriverParam->dma_cam_num_of_entries = DEFAULT_dmaCamNumOfEntries; -+ p_Fm->p_FmDriverParam->dma_read_buf_tsh_clr_emer = DEFAULT_dmaReadIntBufLow; -+ p_Fm->p_FmDriverParam->dma_read_buf_tsh_asrt_emer = DEFAULT_dmaReadIntBufHigh; -+ p_Fm->p_FmDriverParam->dma_write_buf_tsh_clr_emer = DEFAULT_dmaWriteIntBufLow; -+ p_Fm->p_FmDriverParam->dma_write_buf_tsh_asrt_emer = DEFAULT_dmaWriteIntBufHigh; -+ p_Fm->p_FmDriverParam->dma_axi_dbg_num_of_beats = DEFAULT_axiDbgNumOfBeats; -+#endif /* (DPAA_VERSION < 11) */ -+#ifdef FM_NO_TNUM_AGING -+ p_Fm->p_FmDriverParam->tnum_aging_period = 0; -+#endif -+ p_Fm->tnumAgingPeriod = p_Fm->p_FmDriverParam->tnum_aging_period; -+ -+ return p_Fm; -+} -+ -+/**************************************************************************//** -+ @Function FM_Init -+ -+ @Description Initializes the FM module -+ -+ @Param[in] h_Fm - FM module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_Init(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ struct fman_cfg *p_FmDriverParam = NULL; -+ t_Error err = E_OK; -+ int i; -+ t_FmRevisionInfo revInfo; -+ struct fman_rg fman_rg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ -+ fman_rg.bmi_rg = p_Fm->p_FmBmiRegs; -+ fman_rg.qmi_rg = p_Fm->p_FmQmiRegs; -+ fman_rg.fpm_rg = p_Fm->p_FmFpmRegs; -+ fman_rg.dma_rg = p_Fm->p_FmDmaRegs; -+ -+ p_Fm->p_FmStateStruct->count1MicroBit = FM_TIMESTAMP_1_USEC_BIT; -+ p_Fm->p_FmDriverParam->num_of_fman_ctrl_evnt_regs = FM_NUM_OF_FMAN_CTRL_EVENT_REGS; -+ -+ if (p_Fm->guestId != NCSW_MASTER_ID) -+ return InitGuestMode(p_Fm); -+ -+ /* if user didn't configured totalFifoSize - (totalFifoSize=0) we configure default -+ * according to chip. otherwise, we use user's configuration. -+ */ -+ if (p_Fm->p_FmStateStruct->totalFifoSize == 0) -+ p_Fm->p_FmStateStruct->totalFifoSize = DEFAULT_totalFifoSize(p_Fm->p_FmStateStruct->revInfo.majorRev, -+ p_Fm->p_FmStateStruct->revInfo.minorRev); -+ -+ CHECK_INIT_PARAMETERS(p_Fm, CheckFmParameters); -+ -+ p_FmDriverParam = p_Fm->p_FmDriverParam; -+ -+ FM_GetRevision(p_Fm, &revInfo); -+ -+ /* clear revision-dependent non existing exception */ -+#ifdef FM_NO_DISPATCH_RAM_ECC -+ if ((revInfo.majorRev != 4) && -+ (revInfo.majorRev < 6)) -+ p_Fm->p_FmStateStruct->exceptions &= ~FM_EX_BMI_DISPATCH_RAM_ECC; -+#endif /* FM_NO_DISPATCH_RAM_ECC */ -+ -+#ifdef FM_QMI_NO_ECC_EXCEPTIONS -+ if (revInfo.majorRev == 4) -+ p_Fm->p_FmStateStruct->exceptions &= ~(FM_EX_QMI_SINGLE_ECC | FM_EX_QMI_DOUBLE_ECC); -+#endif /* FM_QMI_NO_ECC_EXCEPTIONS */ -+ -+#ifdef FM_QMI_NO_SINGLE_ECC_EXCEPTION -+ if (revInfo.majorRev >= 6) -+ p_Fm->p_FmStateStruct->exceptions &= ~FM_EX_QMI_SINGLE_ECC; -+#endif /* FM_QMI_NO_SINGLE_ECC_EXCEPTION */ -+ -+ FmMuramClear(p_Fm->h_FmMuram); -+ -+ /* clear CPG */ -+ IOMemSet32(UINT_TO_PTR(p_Fm->baseAddr + FM_MM_CGP), 0, FM_PORT_NUM_OF_CONGESTION_GRPS); -+ -+ /* add to the default exceptions the user's definitions */ -+ p_Fm->p_FmStateStruct->exceptions |= p_Fm->userSetExceptions; -+ -+ /* Reset the FM if required */ -+ if (p_Fm->resetOnInit) -+ { -+#ifdef FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 -+ if ((err = FwNotResetErratumBugzilla6173WA(p_Fm)) != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+#else /* not FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 */ -+#ifndef CONFIG_FMAN_ARM -+ { -+ u32 svr = mfspr(SPRN_SVR); -+ -+ if (((SVR_SOC_VER(svr) == SVR_T4240 && SVR_REV(svr) > 0x10)) || -+ ((SVR_SOC_VER(svr) == SVR_T4160 && SVR_REV(svr) > 0x10)) || -+ ((SVR_SOC_VER(svr) == SVR_T4080 && SVR_REV(svr) > 0x10)) || -+ (SVR_SOC_VER(svr) == SVR_T1024) || -+ (SVR_SOC_VER(svr) == SVR_T1023) || -+ (SVR_SOC_VER(svr) == SVR_T2080) || -+ (SVR_SOC_VER(svr) == SVR_T2081)) { -+ DBG(WARNING, ("Hack: No FM reset!\n")); -+ } else { -+ WRITE_UINT32(p_Fm->p_FmFpmRegs->fm_rstc, FPM_RSTC_FM_RESET); -+ CORE_MemoryBarrier(); -+ XX_UDelay(100); -+ } -+ } -+#endif -+ if (fman_is_qmi_halt_not_busy_state(p_Fm->p_FmQmiRegs)) -+ { -+ fman_resume(p_Fm->p_FmFpmRegs); -+ XX_UDelay(100); -+ } -+#endif /* not FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 */ -+ } -+ -+#ifdef FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 -+ if (!p_Fm->resetOnInit) /* Skip operations done in errata workaround */ -+ { -+#endif /* FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 */ -+ /* Load FMan-Controller code to IRAM */ -+ -+ ClearIRam(p_Fm); -+ -+ if (p_Fm->firmware.p_Code && (LoadFmanCtrlCode(p_Fm) != E_OK)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+#ifdef FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 -+ } -+#endif /* FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 */ -+ -+#ifdef FM_CAPWAP_SUPPORT -+ /* save first 256 byte in MURAM */ -+ p_Fm->resAddr = PTR_TO_UINT(FM_MURAM_AllocMem(p_Fm->h_FmMuram, 256, 0)); -+ if (!p_Fm->resAddr) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM alloc for reserved Area failed")); -+ -+ WRITE_BLOCK(UINT_TO_PTR(p_Fm->resAddr), 0, 256); -+#endif /* FM_CAPWAP_SUPPORT */ -+ -+#if (DPAA_VERSION >= 11) -+ p_Fm->partVSPBase = AllocVSPsForPartition(h_Fm, p_Fm->partVSPBase, p_Fm->partNumOfVSPs, p_Fm->guestId); -+ if (p_Fm->partVSPBase == (uint8_t)(ILLEGAL_BASE)) -+ DBG(WARNING, ("partition VSPs allocation is FAILED")); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ /* General FM driver initialization */ -+ p_Fm->fmMuramPhysBaseAddr = -+ (uint64_t)(XX_VirtToPhys(UINT_TO_PTR(p_Fm->baseAddr + FM_MM_MURAM))); -+ -+ for (i=0;iintrMng[i].f_Isr = UnimplementedIsr; -+ for (i=0;ifmanCtrlIntr[i].f_Isr = UnimplementedFmanCtrlIsr; -+ -+ p_FmDriverParam->exceptions = p_Fm->p_FmStateStruct->exceptions; -+ -+ /**********************/ -+ /* Init DMA Registers */ -+ /**********************/ -+ err = InitFmDma(p_Fm); -+ if (err != E_OK) -+ { -+ FreeInitResources(p_Fm); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ /**********************/ -+ /* Init FPM Registers */ -+ /**********************/ -+ err = InitFmFpm(p_Fm); -+ if (err != E_OK) -+ { -+ FreeInitResources(p_Fm); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ /* define common resources */ -+ /* allocate MURAM for FIFO according to total size */ -+ p_Fm->fifoBaseAddr = PTR_TO_UINT(FM_MURAM_AllocMem(p_Fm->h_FmMuram, -+ p_Fm->p_FmStateStruct->totalFifoSize, -+ BMI_FIFO_ALIGN)); -+ if (!p_Fm->fifoBaseAddr) -+ { -+ FreeInitResources(p_Fm); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MURAM alloc for BMI FIFO failed")); -+ } -+ -+ p_FmDriverParam->fifo_base_addr = (uint32_t)(XX_VirtToPhys(UINT_TO_PTR(p_Fm->fifoBaseAddr)) - p_Fm->fmMuramPhysBaseAddr); -+ p_FmDriverParam->total_fifo_size = p_Fm->p_FmStateStruct->totalFifoSize; -+ p_FmDriverParam->total_num_of_tasks = p_Fm->p_FmStateStruct->totalNumOfTasks; -+ p_FmDriverParam->clk_freq = p_Fm->p_FmStateStruct->fmClkFreq; -+ -+ /**********************/ -+ /* Init BMI Registers */ -+ /**********************/ -+ err = InitFmBmi(p_Fm); -+ if (err != E_OK) -+ { -+ FreeInitResources(p_Fm); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ /**********************/ -+ /* Init QMI Registers */ -+ /**********************/ -+ err = InitFmQmi(p_Fm); -+ if (err != E_OK) -+ { -+ FreeInitResources(p_Fm); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ /* build the FM master partition IPC address */ -+ if (Sprint (p_Fm->fmModuleName, "FM_%d_%d",p_Fm->p_FmStateStruct->fmId, NCSW_MASTER_ID) != 6) -+ { -+ FreeInitResources(p_Fm); -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Sprint failed")); -+ } -+ -+ err = XX_IpcRegisterMsgHandler(p_Fm->fmModuleName, FmHandleIpcMsgCB, p_Fm, FM_IPC_MAX_REPLY_SIZE); -+ if (err) -+ { -+ FreeInitResources(p_Fm); -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ } -+ -+ /* Register the FM interrupts handlers */ -+ if (p_Fm->p_FmStateStruct->irq != NO_IRQ) -+ { -+ XX_SetIntr(p_Fm->p_FmStateStruct->irq, FM_EventIsr, p_Fm); -+ XX_EnableIntr(p_Fm->p_FmStateStruct->irq); -+ } -+ -+ if (p_Fm->p_FmStateStruct->errIrq != NO_IRQ) -+ { -+ XX_SetIntr(p_Fm->p_FmStateStruct->errIrq, (void (*) (t_Handle))FM_ErrorIsr, p_Fm); -+ XX_EnableIntr(p_Fm->p_FmStateStruct->errIrq); -+ } -+ -+ err = (t_Error)fman_enable(&fman_rg , p_FmDriverParam); -+ if (err != E_OK) -+ return err; /* FIXME */ -+ -+ EnableTimeStamp(p_Fm); -+ -+ if (p_Fm->firmware.p_Code) -+ { -+ XX_Free(p_Fm->firmware.p_Code); -+ p_Fm->firmware.p_Code = NULL; -+ } -+ -+ XX_Free(p_Fm->p_FmDriverParam); -+ p_Fm->p_FmDriverParam = NULL; -+ -+ return E_OK; -+} -+ -+/**************************************************************************//** -+ @Function FM_Free -+ -+ @Description Frees all resources that were assigned to FM module. -+ -+ Calling this routine invalidates the descriptor. -+ -+ @Param[in] h_Fm - FM module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_Free(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ struct fman_rg fman_rg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ -+ fman_rg.bmi_rg = p_Fm->p_FmBmiRegs; -+ fman_rg.qmi_rg = p_Fm->p_FmQmiRegs; -+ fman_rg.fpm_rg = p_Fm->p_FmFpmRegs; -+ fman_rg.dma_rg = p_Fm->p_FmDmaRegs; -+ -+ if (p_Fm->guestId != NCSW_MASTER_ID) -+ { -+#if (DPAA_VERSION >= 11) -+ FreeVSPsForPartition(h_Fm, p_Fm->partVSPBase, p_Fm->partNumOfVSPs, p_Fm->guestId); -+ -+ if (p_Fm->p_FmSp) -+ { -+ XX_Free(p_Fm->p_FmSp); -+ p_Fm->p_FmSp = NULL; -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ if (p_Fm->fmModuleName[0] != 0) -+ XX_IpcUnregisterMsgHandler(p_Fm->fmModuleName); -+ -+ if (!p_Fm->recoveryMode) -+ XX_Free(p_Fm->p_FmStateStruct); -+ -+ XX_Free(p_Fm); -+ -+ return E_OK; -+ } -+ -+ fman_free_resources(&fman_rg); -+ -+ if ((p_Fm->guestId == NCSW_MASTER_ID) && (p_Fm->fmModuleName[0] != 0)) -+ XX_IpcUnregisterMsgHandler(p_Fm->fmModuleName); -+ -+ if (p_Fm->p_FmStateStruct) -+ { -+ if (p_Fm->p_FmStateStruct->irq != NO_IRQ) -+ { -+ XX_DisableIntr(p_Fm->p_FmStateStruct->irq); -+ XX_FreeIntr(p_Fm->p_FmStateStruct->irq); -+ } -+ if (p_Fm->p_FmStateStruct->errIrq != NO_IRQ) -+ { -+ XX_DisableIntr(p_Fm->p_FmStateStruct->errIrq); -+ XX_FreeIntr(p_Fm->p_FmStateStruct->errIrq); -+ } -+ } -+ -+#if (DPAA_VERSION >= 11) -+ FreeVSPsForPartition(h_Fm, p_Fm->partVSPBase, p_Fm->partNumOfVSPs, p_Fm->guestId); -+ -+ if (p_Fm->p_FmSp) -+ { -+ XX_Free(p_Fm->p_FmSp); -+ p_Fm->p_FmSp = NULL; -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ if (p_Fm->h_Spinlock) -+ XX_FreeSpinlock(p_Fm->h_Spinlock); -+ -+ if (p_Fm->p_FmDriverParam) -+ { -+ if (p_Fm->firmware.p_Code) -+ XX_Free(p_Fm->firmware.p_Code); -+ XX_Free(p_Fm->p_FmDriverParam); -+ p_Fm->p_FmDriverParam = NULL; -+ } -+ -+ FreeInitResources(p_Fm); -+ -+ if (!p_Fm->recoveryMode && p_Fm->p_FmStateStruct) -+ XX_Free(p_Fm->p_FmStateStruct); -+ -+ XX_Free(p_Fm); -+ -+ return E_OK; -+} -+ -+/*************************************************/ -+/* API Advanced Init unit functions */ -+/*************************************************/ -+ -+t_Error FM_ConfigResetOnInit(t_Handle h_Fm, bool enable) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ p_Fm->resetOnInit = enable; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigTotalFifoSize(t_Handle h_Fm, uint32_t totalFifoSize) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ p_Fm->p_FmStateStruct->totalFifoSize = totalFifoSize; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigDmaCacheOverride(t_Handle h_Fm, e_FmDmaCacheOverride cacheOverride) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ enum fman_dma_cache_override fsl_cache_override; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ FMAN_CACHE_OVERRIDE_TRANS(fsl_cache_override, cacheOverride) -+ p_Fm->p_FmDriverParam->dma_cache_override = fsl_cache_override; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigDmaAidOverride(t_Handle h_Fm, bool aidOverride) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ p_Fm->p_FmDriverParam->dma_aid_override = aidOverride; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigDmaAidMode(t_Handle h_Fm, e_FmDmaAidMode aidMode) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ enum fman_dma_aid_mode fsl_aid_mode; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ FMAN_AID_MODE_TRANS(fsl_aid_mode, aidMode); -+ p_Fm->p_FmDriverParam->dma_aid_mode = fsl_aid_mode; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigDmaAxiDbgNumOfBeats(t_Handle h_Fm, uint8_t axiDbgNumOfBeats) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+#if (DPAA_VERSION >= 11) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("Not available for this FM revision!")); -+#else -+ p_Fm->p_FmDriverParam->dma_axi_dbg_num_of_beats = axiDbgNumOfBeats; -+ -+ return E_OK; -+#endif /* (DPAA_VERSION >= 11) */ -+} -+ -+t_Error FM_ConfigDmaCamNumOfEntries(t_Handle h_Fm, uint8_t numOfEntries) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ p_Fm->p_FmDriverParam->dma_cam_num_of_entries = numOfEntries; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigDmaDbgCounter(t_Handle h_Fm, e_FmDmaDbgCntMode fmDmaDbgCntMode) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ enum fman_dma_dbg_cnt_mode fsl_dma_dbg_cnt; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ FMAN_DMA_DBG_CNT_TRANS(fsl_dma_dbg_cnt, fmDmaDbgCntMode); -+ p_Fm->p_FmDriverParam->dma_dbg_cnt_mode = fsl_dma_dbg_cnt; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigDmaStopOnBusErr(t_Handle h_Fm, bool stop) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ p_Fm->p_FmDriverParam->dma_stop_on_bus_error = stop; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigDmaEmergency(t_Handle h_Fm, t_FmDmaEmergency *p_Emergency) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ enum fman_dma_emergency_level fsl_dma_emer; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ FMAN_DMA_EMER_TRANS(fsl_dma_emer, p_Emergency->emergencyLevel); -+ p_Fm->p_FmDriverParam->dma_en_emergency = TRUE; -+ p_Fm->p_FmDriverParam->dma_emergency_bus_select = (uint32_t)p_Emergency->emergencyBusSelect; -+ p_Fm->p_FmDriverParam->dma_emergency_level = fsl_dma_emer; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigDmaEmergencySmoother(t_Handle h_Fm, uint32_t emergencyCnt) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ p_Fm->p_FmDriverParam->dma_en_emergency_smoother = TRUE; -+ p_Fm->p_FmDriverParam->dma_emergency_switch_counter = emergencyCnt; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigDmaErr(t_Handle h_Fm, e_FmDmaErr dmaErr) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ enum fman_dma_err fsl_dma_err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ FMAN_DMA_ERR_TRANS(fsl_dma_err, dmaErr); -+ p_Fm->p_FmDriverParam->dma_err = fsl_dma_err; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigCatastrophicErr(t_Handle h_Fm, e_FmCatastrophicErr catastrophicErr) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ enum fman_catastrophic_err fsl_catastrophic_err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ FMAN_CATASTROPHIC_ERR_TRANS(fsl_catastrophic_err, catastrophicErr); -+ p_Fm->p_FmDriverParam->catastrophic_err = fsl_catastrophic_err; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigEnableMuramTestMode(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev >= 6) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("Not available for this FM revision!")); -+ -+ p_Fm->p_FmDriverParam->en_muram_test_mode = TRUE; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigEnableIramTestMode(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE ); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev >= 6) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("Not available for this FM revision!")); -+ -+ p_Fm->p_FmDriverParam->en_iram_test_mode = TRUE; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigHaltOnExternalActivation(t_Handle h_Fm, bool enable) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ p_Fm->p_FmDriverParam->halt_on_external_activ = enable; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigHaltOnUnrecoverableEccError(t_Handle h_Fm, bool enable) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev >= 6) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("Not available for this FM revision!")); -+ -+ p_Fm->p_FmDriverParam->halt_on_unrecov_ecc_err = enable; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigException(t_Handle h_Fm, e_FmExceptions exception, bool enable) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ uint32_t bitMask = 0; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ GET_EXCEPTION_FLAG(bitMask, exception); -+ if (bitMask) -+ { -+ if (enable) -+ p_Fm->userSetExceptions |= bitMask; -+ else -+ p_Fm->p_FmStateStruct->exceptions &= ~bitMask; -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigExternalEccRamsEnable(t_Handle h_Fm, bool enable) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ p_Fm->p_FmDriverParam->external_ecc_rams_enable = enable; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigTnumAgingPeriod(t_Handle h_Fm, uint16_t tnumAgingPeriod) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ p_Fm->p_FmDriverParam->tnum_aging_period = tnumAgingPeriod; -+ p_Fm->tnumAgingPeriod = p_Fm->p_FmDriverParam->tnum_aging_period; -+ -+ return E_OK; -+} -+ -+/****************************************************/ -+/* Hidden-DEBUG Only API */ -+/****************************************************/ -+ -+t_Error FM_ConfigThresholds(t_Handle h_Fm, t_FmThresholds *p_FmThresholds) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ p_Fm->p_FmDriverParam->disp_limit_tsh = p_FmThresholds->dispLimit; -+ p_Fm->p_FmDriverParam->prs_disp_tsh = p_FmThresholds->prsDispTh; -+ p_Fm->p_FmDriverParam->plcr_disp_tsh = p_FmThresholds->plcrDispTh; -+ p_Fm->p_FmDriverParam->kg_disp_tsh = p_FmThresholds->kgDispTh; -+ p_Fm->p_FmDriverParam->bmi_disp_tsh = p_FmThresholds->bmiDispTh; -+ p_Fm->p_FmDriverParam->qmi_enq_disp_tsh = p_FmThresholds->qmiEnqDispTh; -+ p_Fm->p_FmDriverParam->qmi_deq_disp_tsh = p_FmThresholds->qmiDeqDispTh; -+ p_Fm->p_FmDriverParam->fm_ctl1_disp_tsh = p_FmThresholds->fmCtl1DispTh; -+ p_Fm->p_FmDriverParam->fm_ctl2_disp_tsh = p_FmThresholds->fmCtl2DispTh; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigDmaSosEmergencyThreshold(t_Handle h_Fm, uint32_t dmaSosEmergency) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ p_Fm->p_FmDriverParam->dma_sos_emergency = dmaSosEmergency; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigDmaWriteBufThresholds(t_Handle h_Fm, t_FmDmaThresholds *p_FmDmaThresholds) -+ -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+#if (DPAA_VERSION >= 11) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("Not available for this FM revision!")); -+#else -+ p_Fm->p_FmDriverParam->dma_write_buf_tsh_asrt_emer = p_FmDmaThresholds->assertEmergency; -+ p_Fm->p_FmDriverParam->dma_write_buf_tsh_clr_emer = p_FmDmaThresholds->clearEmergency; -+ -+ return E_OK; -+#endif -+} -+ -+t_Error FM_ConfigDmaCommQThresholds(t_Handle h_Fm, t_FmDmaThresholds *p_FmDmaThresholds) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ p_Fm->p_FmDriverParam->dma_comm_qtsh_asrt_emer = p_FmDmaThresholds->assertEmergency; -+ p_Fm->p_FmDriverParam->dma_comm_qtsh_clr_emer = p_FmDmaThresholds->clearEmergency; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigDmaReadBufThresholds(t_Handle h_Fm, t_FmDmaThresholds *p_FmDmaThresholds) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+#if (DPAA_VERSION >= 11) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("Not available for this FM revision!")); -+#else -+ p_Fm->p_FmDriverParam->dma_read_buf_tsh_clr_emer = p_FmDmaThresholds->clearEmergency; -+ p_Fm->p_FmDriverParam->dma_read_buf_tsh_asrt_emer = p_FmDmaThresholds->assertEmergency; -+ -+ return E_OK; -+#endif -+} -+ -+t_Error FM_ConfigDmaWatchdog(t_Handle h_Fm, uint32_t watchdogValue) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ p_Fm->p_FmDriverParam->dma_watchdog = watchdogValue; -+ -+ return E_OK; -+} -+ -+t_Error FM_ConfigEnableCounters(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+UNUSED(p_Fm); -+ -+ return E_OK; -+} -+ -+t_Error FmGetSetParams(t_Handle h_Fm, t_FmGetSetParams *p_Params) -+{ -+ t_Fm* p_Fm = (t_Fm*)h_Fm; -+ if (p_Params->setParams.type & UPDATE_FM_CLD) -+ { -+ WRITE_UINT32(p_Fm->p_FmFpmRegs->fm_cld, GET_UINT32( -+ p_Fm->p_FmFpmRegs->fm_cld) | 0x00000800); -+ } -+ if (p_Params->setParams.type & CLEAR_IRAM_READY) -+ { -+ t_FMIramRegs *p_Iram = (t_FMIramRegs *)UINT_TO_PTR(p_Fm->baseAddr + FM_MM_IMEM); -+ WRITE_UINT32(p_Iram->iready,GET_UINT32(p_Iram->iready) & ~IRAM_READY); -+ } -+ if (p_Params->setParams.type & UPDATE_FPM_EXTC) -+ WRITE_UINT32(p_Fm->p_FmFpmRegs->fmfp_extc,0x80000000); -+ if (p_Params->setParams.type & UPDATE_FPM_EXTC_CLEAR) -+ WRITE_UINT32(p_Fm->p_FmFpmRegs->fmfp_extc,0x00800000); -+ if (p_Params->setParams.type & UPDATE_FPM_BRKC_SLP) -+ { -+ if (p_Params->setParams.sleep) -+ WRITE_UINT32(p_Fm->p_FmFpmRegs->fmfp_brkc, GET_UINT32( -+ p_Fm->p_FmFpmRegs->fmfp_brkc) | FPM_BRKC_SLP); -+ else -+ WRITE_UINT32(p_Fm->p_FmFpmRegs->fmfp_brkc, GET_UINT32( -+ p_Fm->p_FmFpmRegs->fmfp_brkc) & ~FPM_BRKC_SLP); -+ } -+ if (p_Params->getParams.type & GET_FM_CLD) -+ p_Params->getParams.fm_cld = GET_UINT32(p_Fm->p_FmFpmRegs->fm_cld); -+ if (p_Params->getParams.type & GET_FMQM_GS) -+ p_Params->getParams.fmqm_gs = GET_UINT32(p_Fm->p_FmQmiRegs->fmqm_gs); -+ if (p_Params->getParams.type & GET_FM_NPI) -+ p_Params->getParams.fm_npi = GET_UINT32(p_Fm->p_FmFpmRegs->fm_npi); -+ if (p_Params->getParams.type & GET_FMFP_EXTC) -+ p_Params->getParams.fmfp_extc = GET_UINT32(p_Fm->p_FmFpmRegs->fmfp_extc); -+ return E_OK; -+} -+ -+ -+/****************************************************/ -+/* API Run-time Control uint functions */ -+/****************************************************/ -+void FM_EventIsr(t_Handle h_Fm) -+{ -+#define FM_M_CALL_1G_MAC_ISR(_id) \ -+ { \ -+ if (p_Fm->guestId != p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_1G_MAC0+_id)].guestId) \ -+ SendIpcIsr(p_Fm, (e_FmInterModuleEvent)(e_FM_EV_1G_MAC0+_id), pending); \ -+ else \ -+ p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_1G_MAC0+_id)].f_Isr(p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_1G_MAC0+_id)].h_SrcHandle);\ -+ } -+#define FM_M_CALL_10G_MAC_ISR(_id) \ -+ { \ -+ if (p_Fm->guestId != p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_10G_MAC0+_id)].guestId) \ -+ SendIpcIsr(p_Fm, (e_FmInterModuleEvent)(e_FM_EV_10G_MAC0+_id), pending); \ -+ else \ -+ p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_10G_MAC0+_id)].f_Isr(p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_10G_MAC0+_id)].h_SrcHandle);\ -+ } -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ uint32_t pending, event; -+ struct fman_fpm_regs *fpm_rg; -+ -+ SANITY_CHECK_RETURN(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN(!p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ /* normal interrupts */ -+ pending = fman_get_normal_pending(fpm_rg); -+ if (!pending) -+ return; -+ if (pending & INTR_EN_WAKEUP) // this is a wake up from sleep interrupt -+ { -+ t_FmGetSetParams fmGetSetParams; -+ memset(&fmGetSetParams, 0, sizeof (t_FmGetSetParams)); -+ fmGetSetParams.setParams.type = UPDATE_FPM_BRKC_SLP; -+ fmGetSetParams.setParams.sleep = 0; -+ FmGetSetParams(h_Fm, &fmGetSetParams); -+ } -+ if (pending & INTR_EN_QMI) -+ QmiEvent(p_Fm); -+ if (pending & INTR_EN_PRS) -+ p_Fm->intrMng[e_FM_EV_PRS].f_Isr(p_Fm->intrMng[e_FM_EV_PRS].h_SrcHandle); -+ if (pending & INTR_EN_PLCR) -+ p_Fm->intrMng[e_FM_EV_PLCR].f_Isr(p_Fm->intrMng[e_FM_EV_PLCR].h_SrcHandle); -+ if (pending & INTR_EN_TMR) -+ p_Fm->intrMng[e_FM_EV_TMR].f_Isr(p_Fm->intrMng[e_FM_EV_TMR].h_SrcHandle); -+ -+ /* MAC events may belong to different partitions */ -+ if (pending & INTR_EN_1G_MAC0) -+ FM_M_CALL_1G_MAC_ISR(0); -+ if (pending & INTR_EN_1G_MAC1) -+ FM_M_CALL_1G_MAC_ISR(1); -+ if (pending & INTR_EN_1G_MAC2) -+ FM_M_CALL_1G_MAC_ISR(2); -+ if (pending & INTR_EN_1G_MAC3) -+ FM_M_CALL_1G_MAC_ISR(3); -+ if (pending & INTR_EN_1G_MAC4) -+ FM_M_CALL_1G_MAC_ISR(4); -+ if (pending & INTR_EN_1G_MAC5) -+ FM_M_CALL_1G_MAC_ISR(5); -+ if (pending & INTR_EN_1G_MAC6) -+ FM_M_CALL_1G_MAC_ISR(6); -+ if (pending & INTR_EN_1G_MAC7) -+ FM_M_CALL_1G_MAC_ISR(7); -+ if (pending & INTR_EN_10G_MAC0) -+ FM_M_CALL_10G_MAC_ISR(0); -+ if (pending & INTR_EN_10G_MAC1) -+ FM_M_CALL_10G_MAC_ISR(1); -+ -+ /* IM port events may belong to different partitions */ -+ if (pending & INTR_EN_REV0) -+ { -+ event = fman_get_controller_event(fpm_rg, 0); -+ if (p_Fm->guestId != p_Fm->intrMng[e_FM_EV_FMAN_CTRL_0].guestId) -+ /*TODO IPC ISR For Fman Ctrl */ -+ ASSERT_COND(0); -+ /* SendIpcIsr(p_Fm, e_FM_EV_FMAN_CTRL_0, pending); */ -+ else -+ p_Fm->fmanCtrlIntr[0].f_Isr(p_Fm->fmanCtrlIntr[0].h_SrcHandle, event); -+ -+ } -+ if (pending & INTR_EN_REV1) -+ { -+ event = fman_get_controller_event(fpm_rg, 1); -+ if (p_Fm->guestId != p_Fm->intrMng[e_FM_EV_FMAN_CTRL_1].guestId) -+ /*TODO IPC ISR For Fman Ctrl */ -+ ASSERT_COND(0); -+ /* SendIpcIsr(p_Fm, e_FM_EV_FMAN_CTRL_1, pending); */ -+ else -+ p_Fm->fmanCtrlIntr[1].f_Isr(p_Fm->fmanCtrlIntr[1].h_SrcHandle, event); -+ } -+ if (pending & INTR_EN_REV2) -+ { -+ event = fman_get_controller_event(fpm_rg, 2); -+ if (p_Fm->guestId != p_Fm->intrMng[e_FM_EV_FMAN_CTRL_2].guestId) -+ /*TODO IPC ISR For Fman Ctrl */ -+ ASSERT_COND(0); -+ /* SendIpcIsr(p_Fm, e_FM_EV_FMAN_CTRL_2, pending); */ -+ else -+ p_Fm->fmanCtrlIntr[2].f_Isr(p_Fm->fmanCtrlIntr[2].h_SrcHandle, event); -+ } -+ if (pending & INTR_EN_REV3) -+ { -+ event = fman_get_controller_event(fpm_rg, 3); -+ if (p_Fm->guestId != p_Fm->intrMng[e_FM_EV_FMAN_CTRL_3].guestId) -+ /*TODO IPC ISR For Fman Ctrl */ -+ ASSERT_COND(0); -+ /* SendIpcIsr(p_Fm, e_FM_EV_FMAN_CTRL_2, pendin3); */ -+ else -+ p_Fm->fmanCtrlIntr[3].f_Isr(p_Fm->fmanCtrlIntr[3].h_SrcHandle, event); -+ } -+#ifdef FM_MACSEC_SUPPORT -+ if (pending & INTR_EN_MACSEC_MAC0) -+ { -+ if (p_Fm->guestId != p_Fm->intrMng[e_FM_EV_MACSEC_MAC0].guestId) -+ SendIpcIsr(p_Fm, e_FM_EV_MACSEC_MAC0, pending); -+ else -+ p_Fm->intrMng[e_FM_EV_MACSEC_MAC0].f_Isr(p_Fm->intrMng[e_FM_EV_MACSEC_MAC0].h_SrcHandle); -+ } -+#endif /* FM_MACSEC_SUPPORT */ -+} -+ -+t_Error FM_ErrorIsr(t_Handle h_Fm) -+{ -+#define FM_M_CALL_1G_MAC_ERR_ISR(_id) \ -+ { \ -+ if (p_Fm->guestId != p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_ERR_1G_MAC0+_id)].guestId) \ -+ SendIpcIsr(p_Fm, (e_FmInterModuleEvent)(e_FM_EV_ERR_1G_MAC0+_id), pending); \ -+ else \ -+ p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_ERR_1G_MAC0+_id)].f_Isr(p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_ERR_1G_MAC0+_id)].h_SrcHandle);\ -+ } -+#define FM_M_CALL_10G_MAC_ERR_ISR(_id) \ -+ { \ -+ if (p_Fm->guestId != p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_ERR_10G_MAC0+_id)].guestId) \ -+ SendIpcIsr(p_Fm, (e_FmInterModuleEvent)(e_FM_EV_ERR_10G_MAC0+_id), pending); \ -+ else \ -+ p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_ERR_10G_MAC0+_id)].f_Isr(p_Fm->intrMng[(e_FmInterModuleEvent)(e_FM_EV_ERR_10G_MAC0+_id)].h_SrcHandle);\ -+ } -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ uint32_t pending; -+ struct fman_fpm_regs *fpm_rg; -+ -+ SANITY_CHECK_RETURN_ERROR(h_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ /* error interrupts */ -+ pending = fman_get_fpm_error_interrupts(fpm_rg); -+ if (!pending) -+ return ERROR_CODE(E_EMPTY); -+ -+ if (pending & ERR_INTR_EN_BMI) -+ BmiErrEvent(p_Fm); -+ if (pending & ERR_INTR_EN_QMI) -+ QmiErrEvent(p_Fm); -+ if (pending & ERR_INTR_EN_FPM) -+ FpmErrEvent(p_Fm); -+ if (pending & ERR_INTR_EN_DMA) -+ DmaErrEvent(p_Fm); -+ if (pending & ERR_INTR_EN_IRAM) -+ IramErrIntr(p_Fm); -+ if (pending & ERR_INTR_EN_MURAM) -+ MuramErrIntr(p_Fm); -+ if (pending & ERR_INTR_EN_PRS) -+ p_Fm->intrMng[e_FM_EV_ERR_PRS].f_Isr(p_Fm->intrMng[e_FM_EV_ERR_PRS].h_SrcHandle); -+ if (pending & ERR_INTR_EN_PLCR) -+ p_Fm->intrMng[e_FM_EV_ERR_PLCR].f_Isr(p_Fm->intrMng[e_FM_EV_ERR_PLCR].h_SrcHandle); -+ if (pending & ERR_INTR_EN_KG) -+ p_Fm->intrMng[e_FM_EV_ERR_KG].f_Isr(p_Fm->intrMng[e_FM_EV_ERR_KG].h_SrcHandle); -+ -+ /* MAC events may belong to different partitions */ -+ if (pending & ERR_INTR_EN_1G_MAC0) -+ FM_M_CALL_1G_MAC_ERR_ISR(0); -+ if (pending & ERR_INTR_EN_1G_MAC1) -+ FM_M_CALL_1G_MAC_ERR_ISR(1); -+ if (pending & ERR_INTR_EN_1G_MAC2) -+ FM_M_CALL_1G_MAC_ERR_ISR(2); -+ if (pending & ERR_INTR_EN_1G_MAC3) -+ FM_M_CALL_1G_MAC_ERR_ISR(3); -+ if (pending & ERR_INTR_EN_1G_MAC4) -+ FM_M_CALL_1G_MAC_ERR_ISR(4); -+ if (pending & ERR_INTR_EN_1G_MAC5) -+ FM_M_CALL_1G_MAC_ERR_ISR(5); -+ if (pending & ERR_INTR_EN_1G_MAC6) -+ FM_M_CALL_1G_MAC_ERR_ISR(6); -+ if (pending & ERR_INTR_EN_1G_MAC7) -+ FM_M_CALL_1G_MAC_ERR_ISR(7); -+ if (pending & ERR_INTR_EN_10G_MAC0) -+ FM_M_CALL_10G_MAC_ERR_ISR(0); -+ if (pending & ERR_INTR_EN_10G_MAC1) -+ FM_M_CALL_10G_MAC_ERR_ISR(1); -+ -+#ifdef FM_MACSEC_SUPPORT -+ if (pending & ERR_INTR_EN_MACSEC_MAC0) -+ { -+ if (p_Fm->guestId != p_Fm->intrMng[e_FM_EV_ERR_MACSEC_MAC0].guestId) -+ SendIpcIsr(p_Fm, e_FM_EV_ERR_MACSEC_MAC0, pending); -+ else -+ p_Fm->intrMng[e_FM_EV_ERR_MACSEC_MAC0].f_Isr(p_Fm->intrMng[e_FM_EV_ERR_MACSEC_MAC0].h_SrcHandle); -+ } -+#endif /* FM_MACSEC_SUPPORT */ -+ -+ return E_OK; -+} -+ -+t_Error FM_SetPortsBandwidth(t_Handle h_Fm, t_FmPortsBandwidthParams *p_PortsBandwidth) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ int i; -+ uint8_t sum; -+ uint8_t hardwarePortId; -+ uint8_t weights[64]; -+ uint8_t weight, maxPercent = 0; -+ struct fman_bmi_regs *bmi_rg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ bmi_rg = p_Fm->p_FmBmiRegs; -+ -+ memset(weights, 0, (sizeof(uint8_t) * 64)); -+ -+ /* check that all ports add up to 100% */ -+ sum = 0; -+ for (i=0; i < p_PortsBandwidth->numOfPorts; i++) -+ sum +=p_PortsBandwidth->portsBandwidths[i].bandwidth; -+ if (sum != 100) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Sum of ports bandwidth differ from 100%")); -+ -+ /* find highest percent */ -+ for (i=0; i < p_PortsBandwidth->numOfPorts; i++) -+ { -+ if (p_PortsBandwidth->portsBandwidths[i].bandwidth > maxPercent) -+ maxPercent = p_PortsBandwidth->portsBandwidths[i].bandwidth; -+ } -+ -+ ASSERT_COND(maxPercent > 0); /* guaranteed by sum = 100 */ -+ -+ /* calculate weight for each port */ -+ for (i=0; i < p_PortsBandwidth->numOfPorts; i++) -+ { -+ weight = (uint8_t)((p_PortsBandwidth->portsBandwidths[i].bandwidth * PORT_MAX_WEIGHT ) / maxPercent); -+ /* we want even division between 1-to-PORT_MAX_WEIGHT. so if exact division -+ is not reached, we round up so that: -+ 0 until maxPercent/PORT_MAX_WEIGHT get "1" -+ maxPercent/PORT_MAX_WEIGHT+1 until (maxPercent/PORT_MAX_WEIGHT)*2 get "2" -+ ... -+ maxPercent - maxPercent/PORT_MAX_WEIGHT until maxPercent get "PORT_MAX_WEIGHT: */ -+ if ((uint8_t)((p_PortsBandwidth->portsBandwidths[i].bandwidth * PORT_MAX_WEIGHT ) % maxPercent)) -+ weight++; -+ -+ /* find the location of this port within the register */ -+ hardwarePortId = -+ SwPortIdToHwPortId(p_PortsBandwidth->portsBandwidths[i].type, -+ p_PortsBandwidth->portsBandwidths[i].relativePortId, -+ p_Fm->p_FmStateStruct->revInfo.majorRev, -+ p_Fm->p_FmStateStruct->revInfo.minorRev); -+ -+ ASSERT_COND(IN_RANGE(1, hardwarePortId, 63)); -+ weights[hardwarePortId] = weight; -+ } -+ -+ fman_set_ports_bandwidth(bmi_rg, weights); -+ -+ return E_OK; -+} -+ -+t_Error FM_EnableRamsEcc(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ struct fman_fpm_regs *fpm_rg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ -+ fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ if (p_Fm->guestId != NCSW_MASTER_ID) -+ { -+ t_FmIpcMsg msg; -+ t_Error err; -+ -+ memset(&msg, 0, sizeof(msg)); -+ msg.msgId = FM_ENABLE_RAM_ECC; -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId), -+ NULL, -+ NULL, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ return E_OK; -+ } -+ -+ if (!p_Fm->p_FmStateStruct->internalCall) -+ p_Fm->p_FmStateStruct->explicitEnable = TRUE; -+ p_Fm->p_FmStateStruct->internalCall = FALSE; -+ -+ if (p_Fm->p_FmStateStruct->ramsEccEnable) -+ return E_OK; -+ else -+ { -+ fman_enable_rams_ecc(fpm_rg); -+ p_Fm->p_FmStateStruct->ramsEccEnable = TRUE; -+ } -+ -+ return E_OK; -+} -+ -+t_Error FM_DisableRamsEcc(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ bool explicitDisable = FALSE; -+ struct fman_fpm_regs *fpm_rg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Fm->p_FmDriverParam, E_INVALID_HANDLE); -+ -+ fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ if (p_Fm->guestId != NCSW_MASTER_ID) -+ { -+ t_Error err; -+ t_FmIpcMsg msg; -+ -+ memset(&msg, 0, sizeof(msg)); -+ msg.msgId = FM_DISABLE_RAM_ECC; -+ if ((err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId), -+ NULL, -+ NULL, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ return E_OK; -+ } -+ -+ if (!p_Fm->p_FmStateStruct->internalCall) -+ explicitDisable = TRUE; -+ p_Fm->p_FmStateStruct->internalCall = FALSE; -+ -+ /* if rams are already disabled, or if rams were explicitly enabled and are -+ currently called indirectly (not explicitly), ignore this call. */ -+ if (!p_Fm->p_FmStateStruct->ramsEccEnable || -+ (p_Fm->p_FmStateStruct->explicitEnable && !explicitDisable)) -+ return E_OK; -+ else -+ { -+ if (p_Fm->p_FmStateStruct->explicitEnable) -+ /* This is the case were both explicit are TRUE. -+ Turn off this flag for cases were following ramsEnable -+ routines are called */ -+ p_Fm->p_FmStateStruct->explicitEnable = FALSE; -+ -+ fman_enable_rams_ecc(fpm_rg); -+ p_Fm->p_FmStateStruct->ramsEccEnable = FALSE; -+ } -+ -+ return E_OK; -+} -+ -+t_Error FM_SetException(t_Handle h_Fm, e_FmExceptions exception, bool enable) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ uint32_t bitMask = 0; -+ enum fman_exceptions fslException; -+ struct fman_rg fman_rg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ -+ fman_rg.bmi_rg = p_Fm->p_FmBmiRegs; -+ fman_rg.qmi_rg = p_Fm->p_FmQmiRegs; -+ fman_rg.fpm_rg = p_Fm->p_FmFpmRegs; -+ fman_rg.dma_rg = p_Fm->p_FmDmaRegs; -+ -+ GET_EXCEPTION_FLAG(bitMask, exception); -+ if (bitMask) -+ { -+ if (enable) -+ p_Fm->p_FmStateStruct->exceptions |= bitMask; -+ else -+ p_Fm->p_FmStateStruct->exceptions &= ~bitMask; -+ -+ fslException = FmanExceptionTrans(exception); -+ -+ return (t_Error)fman_set_exception(&fman_rg, -+ fslException, -+ enable); -+ } -+ else -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); -+ -+ return E_OK; -+} -+ -+t_Error FM_GetRevision(t_Handle h_Fm, t_FmRevisionInfo *p_FmRevisionInfo) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ p_FmRevisionInfo->majorRev = p_Fm->p_FmStateStruct->revInfo.majorRev; -+ p_FmRevisionInfo->minorRev = p_Fm->p_FmStateStruct->revInfo.minorRev; -+ -+ return E_OK; -+} -+ -+t_Error FM_GetFmanCtrlCodeRevision(t_Handle h_Fm, t_FmCtrlCodeRevisionInfo *p_RevisionInfo) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ t_FMIramRegs *p_Iram; -+ uint32_t revInfo; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_RevisionInfo, E_NULL_POINTER); -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_Error err; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength; -+ t_FmIpcFmanCtrlCodeRevisionInfo ipcRevInfo; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_GET_FMAN_CTRL_CODE_REV; -+ replyLength = sizeof(uint32_t) + sizeof(t_FmCtrlCodeRevisionInfo); -+ if ((err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ if (replyLength != (sizeof(uint32_t) + sizeof(t_FmCtrlCodeRevisionInfo))) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ memcpy((uint8_t*)&ipcRevInfo, reply.replyBody, sizeof(t_FmCtrlCodeRevisionInfo)); -+ p_RevisionInfo->packageRev = ipcRevInfo.packageRev; -+ p_RevisionInfo->majorRev = ipcRevInfo.majorRev; -+ p_RevisionInfo->minorRev = ipcRevInfo.minorRev; -+ return (t_Error)(reply.error); -+ } -+ else if (p_Fm->guestId != NCSW_MASTER_ID) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("running in guest-mode without IPC!")); -+ -+ p_Iram = (t_FMIramRegs *)UINT_TO_PTR(p_Fm->baseAddr + FM_MM_IMEM); -+ WRITE_UINT32(p_Iram->iadd, 0x4); -+ while (GET_UINT32(p_Iram->iadd) != 0x4) ; -+ revInfo = GET_UINT32(p_Iram->idata); -+ p_RevisionInfo->packageRev = (uint16_t)((revInfo & 0xFFFF0000) >> 16); -+ p_RevisionInfo->majorRev = (uint8_t)((revInfo & 0x0000FF00) >> 8); -+ p_RevisionInfo->minorRev = (uint8_t)(revInfo & 0x000000FF); -+ -+ return E_OK; -+} -+ -+uint32_t FM_GetCounter(t_Handle h_Fm, e_FmCounters counter) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ t_Error err; -+ uint32_t counterValue; -+ struct fman_rg fman_rg; -+ enum fman_counters fsl_counter; -+ -+ SANITY_CHECK_RETURN_VALUE(p_Fm, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_VALUE(!p_Fm->p_FmDriverParam, E_INVALID_STATE, 0); -+ -+ fman_rg.bmi_rg = p_Fm->p_FmBmiRegs; -+ fman_rg.qmi_rg = p_Fm->p_FmQmiRegs; -+ fman_rg.fpm_rg = p_Fm->p_FmFpmRegs; -+ fman_rg.dma_rg = p_Fm->p_FmDmaRegs; -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ !p_Fm->baseAddr && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ uint32_t replyLength, outCounter; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_GET_COUNTER; -+ memcpy(msg.msgBody, (uint8_t *)&counter, sizeof(uint32_t)); -+ replyLength = sizeof(uint32_t) + sizeof(uint32_t); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId) +sizeof(counterValue), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ { -+ REPORT_ERROR(MAJOR, err, NO_MSG); -+ return 0; -+ } -+ if (replyLength != (sizeof(uint32_t) + sizeof(uint32_t))) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ return 0; -+ } -+ -+ memcpy((uint8_t*)&outCounter, reply.replyBody, sizeof(uint32_t)); -+ return outCounter; -+ } -+ else if (!p_Fm->baseAddr) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Either IPC or 'baseAddress' is required!")); -+ return 0; -+ } -+ -+ /* When applicable (when there is an 'enable counters' bit, -+ check that counters are enabled */ -+ switch (counter) -+ { -+ case (e_FM_COUNTERS_DEQ_1): -+ case (e_FM_COUNTERS_DEQ_2): -+ case (e_FM_COUNTERS_DEQ_3): -+ if ((p_Fm->p_FmStateStruct->revInfo.majorRev == 4) || -+ (p_Fm->p_FmStateStruct->revInfo.majorRev >= 6)) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Requested counter not supported")); -+ return 0; -+ } -+ case (e_FM_COUNTERS_ENQ_TOTAL_FRAME): -+ case (e_FM_COUNTERS_DEQ_TOTAL_FRAME): -+ case (e_FM_COUNTERS_DEQ_0): -+ case (e_FM_COUNTERS_DEQ_FROM_DEFAULT): -+ case (e_FM_COUNTERS_DEQ_FROM_CONTEXT): -+ case (e_FM_COUNTERS_DEQ_FROM_FD): -+ case (e_FM_COUNTERS_DEQ_CONFIRM): -+ if (!(GET_UINT32(p_Fm->p_FmQmiRegs->fmqm_gc) & QMI_CFG_EN_COUNTERS)) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Requested counter was not enabled")); -+ return 0; -+ } -+ break; -+ default: -+ break; -+ } -+ -+ FMAN_COUNTERS_TRANS(fsl_counter, counter); -+ return fman_get_counter(&fman_rg, fsl_counter); -+} -+ -+t_Error FM_ModifyCounter(t_Handle h_Fm, e_FmCounters counter, uint32_t val) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ struct fman_rg fman_rg; -+ enum fman_counters fsl_counter; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ -+ fman_rg.bmi_rg = p_Fm->p_FmBmiRegs; -+ fman_rg.qmi_rg = p_Fm->p_FmQmiRegs; -+ fman_rg.fpm_rg = p_Fm->p_FmFpmRegs; -+ fman_rg.dma_rg = p_Fm->p_FmDmaRegs; -+ -+ FMAN_COUNTERS_TRANS(fsl_counter, counter); -+ return (t_Error)fman_modify_counter(&fman_rg, fsl_counter, val); -+} -+ -+void FM_SetDmaEmergency(t_Handle h_Fm, e_FmDmaMuramPort muramPort, bool enable) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ struct fman_dma_regs *dma_rg; -+ -+ SANITY_CHECK_RETURN(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ -+ dma_rg = p_Fm->p_FmDmaRegs; -+ -+ fman_set_dma_emergency(dma_rg, !!(muramPort==e_FM_DMA_MURAM_PORT_WRITE), enable); -+} -+ -+void FM_SetDmaExtBusPri(t_Handle h_Fm, e_FmDmaExtBusPri pri) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ struct fman_dma_regs *dma_rg; -+ -+ SANITY_CHECK_RETURN(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ -+ dma_rg = p_Fm->p_FmDmaRegs; -+ -+ fman_set_dma_ext_bus_pri(dma_rg, pri); -+} -+ -+void FM_GetDmaStatus(t_Handle h_Fm, t_FmDmaStatus *p_FmDmaStatus) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ uint32_t dmaStatus; -+ struct fman_dma_regs *dma_rg; -+ -+ SANITY_CHECK_RETURN(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ -+ dma_rg = p_Fm->p_FmDmaRegs; -+ -+ if ((p_Fm->guestId != NCSW_MASTER_ID) && -+ !p_Fm->baseAddr && -+ p_Fm->h_IpcSessions[0]) -+ { -+ t_FmIpcDmaStatus ipcDmaStatus; -+ t_FmIpcMsg msg; -+ t_FmIpcReply reply; -+ t_Error err; -+ uint32_t replyLength; -+ -+ memset(&msg, 0, sizeof(msg)); -+ memset(&reply, 0, sizeof(reply)); -+ msg.msgId = FM_DMA_STAT; -+ replyLength = sizeof(uint32_t) + sizeof(t_FmIpcDmaStatus); -+ err = XX_IpcSendMessage(p_Fm->h_IpcSessions[0], -+ (uint8_t*)&msg, -+ sizeof(msg.msgId), -+ (uint8_t*)&reply, -+ &replyLength, -+ NULL, -+ NULL); -+ if (err != E_OK) -+ { -+ REPORT_ERROR(MINOR, err, NO_MSG); -+ return; -+ } -+ if (replyLength != (sizeof(uint32_t) + sizeof(t_FmIpcDmaStatus))) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); -+ return; -+ } -+ memcpy((uint8_t*)&ipcDmaStatus, reply.replyBody, sizeof(t_FmIpcDmaStatus)); -+ -+ p_FmDmaStatus->cmqNotEmpty = (bool)ipcDmaStatus.boolCmqNotEmpty; /**< Command queue is not empty */ -+ p_FmDmaStatus->busError = (bool)ipcDmaStatus.boolBusError; /**< Bus error occurred */ -+ p_FmDmaStatus->readBufEccError = (bool)ipcDmaStatus.boolReadBufEccError; /**< Double ECC error on buffer Read */ -+ p_FmDmaStatus->writeBufEccSysError =(bool)ipcDmaStatus.boolWriteBufEccSysError; /**< Double ECC error on buffer write from system side */ -+ p_FmDmaStatus->writeBufEccFmError = (bool)ipcDmaStatus.boolWriteBufEccFmError; /**< Double ECC error on buffer write from FM side */ -+ p_FmDmaStatus->singlePortEccError = (bool)ipcDmaStatus.boolSinglePortEccError; /**< Double ECC error on buffer write from FM side */ -+ return; -+ } -+ else if (!p_Fm->baseAddr) -+ { -+ REPORT_ERROR(MINOR, E_NOT_SUPPORTED, -+ ("Either IPC or 'baseAddress' is required!")); -+ return; -+ } -+ -+ dmaStatus = fman_get_dma_status(dma_rg); -+ -+ p_FmDmaStatus->cmqNotEmpty = (bool)(dmaStatus & DMA_STATUS_CMD_QUEUE_NOT_EMPTY); -+ p_FmDmaStatus->busError = (bool)(dmaStatus & DMA_STATUS_BUS_ERR); -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev >= 6) -+ p_FmDmaStatus->singlePortEccError = (bool)(dmaStatus & DMA_STATUS_FM_SPDAT_ECC); -+ else -+ { -+ p_FmDmaStatus->readBufEccError = (bool)(dmaStatus & DMA_STATUS_READ_ECC); -+ p_FmDmaStatus->writeBufEccSysError = (bool)(dmaStatus & DMA_STATUS_SYSTEM_WRITE_ECC); -+ p_FmDmaStatus->writeBufEccFmError = (bool)(dmaStatus & DMA_STATUS_FM_WRITE_ECC); -+ } -+} -+ -+void FM_Resume(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ struct fman_fpm_regs *fpm_rg; -+ -+ SANITY_CHECK_RETURN(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ fpm_rg = p_Fm->p_FmFpmRegs; -+ -+ fman_resume(fpm_rg); -+} -+ -+t_Error FM_GetSpecialOperationCoding(t_Handle h_Fm, -+ fmSpecialOperations_t spOper, -+ uint8_t *p_SpOperCoding) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ t_FmCtrlCodeRevisionInfo revInfo; -+ t_Error err; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR(p_SpOperCoding, E_NULL_POINTER); -+ -+ if (!spOper) -+ { -+ *p_SpOperCoding = 0; -+ return E_OK; -+ } -+ -+ if ((err = FM_GetFmanCtrlCodeRevision(p_Fm, &revInfo)) != E_OK) -+ { -+ DBG(WARNING, ("FM in guest-mode without IPC, can't validate firmware revision.")); -+ revInfo.packageRev = IP_OFFLOAD_PACKAGE_NUMBER; -+ } -+ else if (!IS_OFFLOAD_PACKAGE(revInfo.packageRev)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("Fman ctrl code package")); -+ -+ switch (spOper) -+ { -+ case (FM_SP_OP_CAPWAP_DTLS_DEC): -+ *p_SpOperCoding = 9; -+ break; -+ case (FM_SP_OP_CAPWAP_DTLS_ENC): -+ *p_SpOperCoding = 10; -+ break; -+ case (FM_SP_OP_IPSEC|FM_SP_OP_IPSEC_UPDATE_UDP_LEN|FM_SP_OP_IPSEC_MANIP): -+ case (FM_SP_OP_IPSEC|FM_SP_OP_IPSEC_UPDATE_UDP_LEN|FM_SP_OP_IPSEC_MANIP|FM_SP_OP_RPD): -+ *p_SpOperCoding = 5; -+ break; -+ case (FM_SP_OP_IPSEC|FM_SP_OP_IPSEC_MANIP): -+ case (FM_SP_OP_IPSEC|FM_SP_OP_IPSEC_MANIP|FM_SP_OP_RPD): -+ *p_SpOperCoding = 6; -+ break; -+ case (FM_SP_OP_IPSEC|FM_SP_OP_IPSEC_UPDATE_UDP_LEN|FM_SP_OP_RPD): -+ *p_SpOperCoding = 3; -+ break; -+ case (FM_SP_OP_IPSEC|FM_SP_OP_IPSEC_UPDATE_UDP_LEN): -+ *p_SpOperCoding = 1; -+ break; -+ case (FM_SP_OP_IPSEC|FM_SP_OP_IPSEC_UPDATE_UDP_LEN|FM_SP_OP_IPSEC_NO_ETH_HDR): -+ *p_SpOperCoding = 12; -+ break; -+ case (FM_SP_OP_IPSEC|FM_SP_OP_RPD): -+ *p_SpOperCoding = 4; -+ break; -+ case (FM_SP_OP_IPSEC): -+ *p_SpOperCoding = 2; -+ break; -+ case (FM_SP_OP_DCL4C): -+ *p_SpOperCoding = 7; -+ break; -+ case (FM_SP_OP_CLEAR_RPD): -+ *p_SpOperCoding = 8; -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, NO_MSG); -+ } -+ -+ return E_OK; -+} -+ -+t_Error FM_CtrlMonStart(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_Fm; -+ t_FmTrbRegs *p_MonRegs; -+ uint8_t i; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ WRITE_UINT32(p_Fm->p_FmFpmRegs->fmfp_brkc, -+ GET_UINT32(p_Fm->p_FmFpmRegs->fmfp_brkc) | FPM_BRKC_RDBG); -+ -+ for (i = 0; i < FM_NUM_OF_CTRL; i++) -+ { -+ p_MonRegs = (t_FmTrbRegs *)UINT_TO_PTR(p_Fm->baseAddr + FM_MM_TRB(i)); -+ -+ /* Reset control registers */ -+ WRITE_UINT32(p_MonRegs->tcrh, TRB_TCRH_RESET); -+ WRITE_UINT32(p_MonRegs->tcrl, TRB_TCRL_RESET); -+ -+ /* Configure: counter #1 counts all stalls in risc - ldsched stall -+ counter #2 counts all stalls in risc - other stall*/ -+ WRITE_UINT32(p_MonRegs->tcrl, TRB_TCRL_RESET | TRB_TCRL_UTIL); -+ -+ /* Enable monitoring */ -+ WRITE_UINT32(p_MonRegs->tcrh, TRB_TCRH_ENABLE_COUNTERS); -+ } -+ -+ return E_OK; -+} -+ -+t_Error FM_CtrlMonStop(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_Fm; -+ t_FmTrbRegs *p_MonRegs; -+ uint8_t i; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ -+ for (i = 0; i < FM_NUM_OF_CTRL; i++) -+ { -+ p_MonRegs = (t_FmTrbRegs *)UINT_TO_PTR(p_Fm->baseAddr + FM_MM_TRB(i)); -+ WRITE_UINT32(p_MonRegs->tcrh, TRB_TCRH_DISABLE_COUNTERS); -+ } -+ -+ WRITE_UINT32(p_Fm->p_FmFpmRegs->fmfp_brkc, -+ GET_UINT32(p_Fm->p_FmFpmRegs->fmfp_brkc) & ~FPM_BRKC_RDBG); -+ -+ return E_OK; -+} -+ -+t_Error FM_CtrlMonGetCounters(t_Handle h_Fm, uint8_t fmCtrlIndex, t_FmCtrlMon *p_Mon) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_Fm; -+ t_FmTrbRegs *p_MonRegs; -+ uint64_t clkCnt, utilValue, effValue; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ SANITY_CHECK_RETURN_ERROR((p_Fm->guestId == NCSW_MASTER_ID), E_NOT_SUPPORTED); -+ SANITY_CHECK_RETURN_ERROR(p_Mon, E_NULL_POINTER); -+ -+ if (fmCtrlIndex >= FM_NUM_OF_CTRL) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("FM Controller index")); -+ -+ p_MonRegs = (t_FmTrbRegs *)UINT_TO_PTR(p_Fm->baseAddr + FM_MM_TRB(fmCtrlIndex)); -+ -+ clkCnt = (uint64_t) -+ ((uint64_t)GET_UINT32(p_MonRegs->tpcch) << 32 | GET_UINT32(p_MonRegs->tpccl)); -+ -+ utilValue = (uint64_t) -+ ((uint64_t)GET_UINT32(p_MonRegs->tpc1h) << 32 | GET_UINT32(p_MonRegs->tpc1l)); -+ -+ effValue = (uint64_t) -+ ((uint64_t)GET_UINT32(p_MonRegs->tpc2h) << 32 | GET_UINT32(p_MonRegs->tpc2l)); -+ -+ p_Mon->percentCnt[0] = (uint8_t)((clkCnt - utilValue) * 100 / clkCnt); -+ if (clkCnt != utilValue) -+ p_Mon->percentCnt[1] = (uint8_t)(((clkCnt - utilValue) - effValue) * 100 / (clkCnt - utilValue)); -+ else -+ p_Mon->percentCnt[1] = 0; -+ -+ return E_OK; -+} -+ -+t_Handle FM_GetMuramHandle(t_Handle h_Fm) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ -+ SANITY_CHECK_RETURN_VALUE(p_Fm, E_INVALID_HANDLE, NULL); -+ -+ return (p_Fm->h_FmMuram); -+} -+ -+/****************************************************/ -+/* Hidden-DEBUG Only API */ -+/****************************************************/ -+t_Error FM_ForceIntr (t_Handle h_Fm, e_FmExceptions exception) -+{ -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ enum fman_exceptions fslException; -+ struct fman_rg fman_rg; -+ -+ SANITY_CHECK_RETURN_ERROR(p_Fm, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(!p_Fm->p_FmDriverParam, E_INVALID_STATE); -+ -+ fman_rg.bmi_rg = p_Fm->p_FmBmiRegs; -+ fman_rg.qmi_rg = p_Fm->p_FmQmiRegs; -+ fman_rg.fpm_rg = p_Fm->p_FmFpmRegs; -+ fman_rg.dma_rg = p_Fm->p_FmDmaRegs; -+ -+ switch (exception) -+ { -+ case e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: -+ if (!(p_Fm->p_FmStateStruct->exceptions & FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ break; -+ case e_FM_EX_QMI_SINGLE_ECC: -+ if (p_Fm->p_FmStateStruct->revInfo.majorRev >= 6) -+ RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("e_FM_EX_QMI_SINGLE_ECC not supported on this integration.")); -+ -+ if (!(p_Fm->p_FmStateStruct->exceptions & FM_EX_QMI_SINGLE_ECC)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ break; -+ case e_FM_EX_QMI_DOUBLE_ECC: -+ if (!(p_Fm->p_FmStateStruct->exceptions & FM_EX_QMI_DOUBLE_ECC)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ break; -+ case e_FM_EX_BMI_LIST_RAM_ECC: -+ if (!(p_Fm->p_FmStateStruct->exceptions & FM_EX_BMI_LIST_RAM_ECC)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ break; -+ case e_FM_EX_BMI_STORAGE_PROFILE_ECC: -+ if (!(p_Fm->p_FmStateStruct->exceptions & FM_EX_BMI_STORAGE_PROFILE_ECC)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ break; -+ case e_FM_EX_BMI_STATISTICS_RAM_ECC: -+ if (!(p_Fm->p_FmStateStruct->exceptions & FM_EX_BMI_STATISTICS_RAM_ECC)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ break; -+ case e_FM_EX_BMI_DISPATCH_RAM_ECC: -+ if (!(p_Fm->p_FmStateStruct->exceptions & FM_EX_BMI_DISPATCH_RAM_ECC)) -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception is masked")); -+ break; -+ default: -+ RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("The selected exception may not be forced")); -+ } -+ -+ fslException = FmanExceptionTrans(exception); -+ fman_force_intr (&fman_rg, fslException); -+ -+ return E_OK; -+} -+ -+t_Handle FmGetPcd(t_Handle h_Fm) -+{ -+ return ((t_Fm*)h_Fm)->h_Pcd; -+} -+#if (DPAA_VERSION >= 11) -+extern void *g_MemacRegs; -+void fm_clk_down(void); -+uint32_t fman_memac_get_event(void *regs, uint32_t ev_mask); -+void FM_ChangeClock(t_Handle h_Fm, int hardwarePortId) -+{ -+ int macId; -+ uint32_t event, rcr; -+ t_Fm *p_Fm = (t_Fm*)h_Fm; -+ rcr = GET_UINT32(p_Fm->p_FmFpmRegs->fm_rcr); -+ rcr |= 0x04000000; -+ WRITE_UINT32(p_Fm->p_FmFpmRegs->fm_rcr, rcr); -+ -+ HW_PORT_ID_TO_SW_PORT_ID(macId, hardwarePortId); -+ do -+ { -+ event = fman_memac_get_event(g_MemacRegs, 0xFFFFFFFF); -+ } while ((event & 0x00000020) == 0); -+ fm_clk_down(); -+ rcr = GET_UINT32(p_Fm->p_FmFpmRegs->fm_rcr); -+ rcr &= ~0x04000000; -+ WRITE_UINT32(p_Fm->p_FmFpmRegs->fm_rcr, rcr); -+} -+#endif ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm.h -@@ -0,0 +1,646 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm.h -+ -+ @Description FM internal structures and definitions. -+*//***************************************************************************/ -+#ifndef __FM_H -+#define __FM_H -+ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "fm_ext.h" -+#include "fm_ipc.h" -+ -+#include "fsl_fman.h" -+ -+#define __ERR_MODULE__ MODULE_FM -+ -+#define FM_MAX_NUM_OF_HW_PORT_IDS 64 -+#define FM_MAX_NUM_OF_GUESTS 100 -+ -+/**************************************************************************//** -+ @Description Exceptions -+*//***************************************************************************/ -+#define FM_EX_DMA_BUS_ERROR 0x80000000 /**< DMA bus error. */ -+#define FM_EX_DMA_READ_ECC 0x40000000 -+#define FM_EX_DMA_SYSTEM_WRITE_ECC 0x20000000 -+#define FM_EX_DMA_FM_WRITE_ECC 0x10000000 -+#define FM_EX_FPM_STALL_ON_TASKS 0x08000000 /**< Stall of tasks on FPM */ -+#define FM_EX_FPM_SINGLE_ECC 0x04000000 /**< Single ECC on FPM */ -+#define FM_EX_FPM_DOUBLE_ECC 0x02000000 -+#define FM_EX_QMI_SINGLE_ECC 0x01000000 /**< Single ECC on FPM */ -+#define FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 /**< Dequeu from default queue id */ -+#define FM_EX_QMI_DOUBLE_ECC 0x00400000 -+#define FM_EX_BMI_LIST_RAM_ECC 0x00200000 -+#define FM_EX_BMI_STORAGE_PROFILE_ECC 0x00100000 -+#define FM_EX_BMI_STATISTICS_RAM_ECC 0x00080000 -+#define FM_EX_IRAM_ECC 0x00040000 -+#define FM_EX_MURAM_ECC 0x00020000 -+#define FM_EX_BMI_DISPATCH_RAM_ECC 0x00010000 -+#define FM_EX_DMA_SINGLE_PORT_ECC 0x00008000 -+ -+#define DMA_EMSR_EMSTR_MASK 0x0000FFFF -+ -+#define DMA_THRESH_COMMQ_MASK 0xFF000000 -+#define DMA_THRESH_READ_INT_BUF_MASK 0x007F0000 -+#define DMA_THRESH_WRITE_INT_BUF_MASK 0x0000007F -+ -+#define GET_EXCEPTION_FLAG(bitMask, exception) \ -+switch (exception){ \ -+ case e_FM_EX_DMA_BUS_ERROR: \ -+ bitMask = FM_EX_DMA_BUS_ERROR; break; \ -+ case e_FM_EX_DMA_SINGLE_PORT_ECC: \ -+ bitMask = FM_EX_DMA_SINGLE_PORT_ECC; break; \ -+ case e_FM_EX_DMA_READ_ECC: \ -+ bitMask = FM_EX_DMA_READ_ECC; break; \ -+ case e_FM_EX_DMA_SYSTEM_WRITE_ECC: \ -+ bitMask = FM_EX_DMA_SYSTEM_WRITE_ECC; break; \ -+ case e_FM_EX_DMA_FM_WRITE_ECC: \ -+ bitMask = FM_EX_DMA_FM_WRITE_ECC; break; \ -+ case e_FM_EX_FPM_STALL_ON_TASKS: \ -+ bitMask = FM_EX_FPM_STALL_ON_TASKS; break; \ -+ case e_FM_EX_FPM_SINGLE_ECC: \ -+ bitMask = FM_EX_FPM_SINGLE_ECC; break; \ -+ case e_FM_EX_FPM_DOUBLE_ECC: \ -+ bitMask = FM_EX_FPM_DOUBLE_ECC; break; \ -+ case e_FM_EX_QMI_SINGLE_ECC: \ -+ bitMask = FM_EX_QMI_SINGLE_ECC; break; \ -+ case e_FM_EX_QMI_DOUBLE_ECC: \ -+ bitMask = FM_EX_QMI_DOUBLE_ECC; break; \ -+ case e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: \ -+ bitMask = FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID; break; \ -+ case e_FM_EX_BMI_LIST_RAM_ECC: \ -+ bitMask = FM_EX_BMI_LIST_RAM_ECC; break; \ -+ case e_FM_EX_BMI_STORAGE_PROFILE_ECC: \ -+ bitMask = FM_EX_BMI_STORAGE_PROFILE_ECC; break; \ -+ case e_FM_EX_BMI_STATISTICS_RAM_ECC: \ -+ bitMask = FM_EX_BMI_STATISTICS_RAM_ECC; break; \ -+ case e_FM_EX_BMI_DISPATCH_RAM_ECC: \ -+ bitMask = FM_EX_BMI_DISPATCH_RAM_ECC; break; \ -+ case e_FM_EX_IRAM_ECC: \ -+ bitMask = FM_EX_IRAM_ECC; break; \ -+ case e_FM_EX_MURAM_ECC: \ -+ bitMask = FM_EX_MURAM_ECC; break; \ -+ default: bitMask = 0;break; \ -+} -+ -+#define GET_FM_MODULE_EVENT(_mod, _id, _intrType, _event) \ -+ switch (_mod) { \ -+ case e_FM_MOD_PRS: \ -+ if (_id) _event = e_FM_EV_DUMMY_LAST; \ -+ else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PRS : e_FM_EV_PRS; \ -+ break; \ -+ case e_FM_MOD_KG: \ -+ if (_id) _event = e_FM_EV_DUMMY_LAST; \ -+ else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_KG : e_FM_EV_DUMMY_LAST; \ -+ break; \ -+ case e_FM_MOD_PLCR: \ -+ if (_id) _event = e_FM_EV_DUMMY_LAST; \ -+ else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PLCR : e_FM_EV_PLCR; \ -+ break; \ -+ case e_FM_MOD_TMR: \ -+ if (_id) _event = e_FM_EV_DUMMY_LAST; \ -+ else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_TMR; \ -+ break; \ -+ case e_FM_MOD_10G_MAC: \ -+ if (_id >= FM_MAX_NUM_OF_10G_MACS) _event = e_FM_EV_DUMMY_LAST; \ -+ else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? (e_FM_EV_ERR_10G_MAC0 + _id) : (e_FM_EV_10G_MAC0 + _id); \ -+ break; \ -+ case e_FM_MOD_1G_MAC: \ -+ if (_id >= FM_MAX_NUM_OF_1G_MACS) _event = e_FM_EV_DUMMY_LAST; \ -+ else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? (e_FM_EV_ERR_1G_MAC0 + _id) : (e_FM_EV_1G_MAC0 + _id); \ -+ break; \ -+ case e_FM_MOD_MACSEC: \ -+ switch (_id){ \ -+ case (0): _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_MACSEC_MAC0:e_FM_EV_MACSEC_MAC0; \ -+ break; \ -+ } \ -+ break; \ -+ case e_FM_MOD_FMAN_CTRL: \ -+ if (_intrType == e_FM_INTR_TYPE_ERR) _event = e_FM_EV_DUMMY_LAST; \ -+ else _event = (e_FM_EV_FMAN_CTRL_0 + _id); \ -+ break; \ -+ default: _event = e_FM_EV_DUMMY_LAST; \ -+ break; \ -+ } -+ -+#define FMAN_CACHE_OVERRIDE_TRANS(fsl_cache_override, _cache_override) \ -+ switch (_cache_override){ \ -+ case e_FM_DMA_NO_CACHE_OR: \ -+ fsl_cache_override = E_FMAN_DMA_NO_CACHE_OR; break; \ -+ case e_FM_DMA_NO_STASH_DATA: \ -+ fsl_cache_override = E_FMAN_DMA_NO_STASH_DATA; break; \ -+ case e_FM_DMA_MAY_STASH_DATA: \ -+ fsl_cache_override = E_FMAN_DMA_MAY_STASH_DATA; break; \ -+ case e_FM_DMA_STASH_DATA: \ -+ fsl_cache_override = E_FMAN_DMA_STASH_DATA; break; \ -+ default: \ -+ fsl_cache_override = E_FMAN_DMA_NO_CACHE_OR; break; \ -+ } -+ -+#define FMAN_AID_MODE_TRANS(fsl_aid_mode, _aid_mode) \ -+ switch (_aid_mode){ \ -+ case e_FM_DMA_AID_OUT_PORT_ID: \ -+ fsl_aid_mode = E_FMAN_DMA_AID_OUT_PORT_ID; break; \ -+ case e_FM_DMA_AID_OUT_TNUM: \ -+ fsl_aid_mode = E_FMAN_DMA_AID_OUT_TNUM; break; \ -+ default: \ -+ fsl_aid_mode = E_FMAN_DMA_AID_OUT_PORT_ID; break; \ -+ } -+ -+#define FMAN_DMA_DBG_CNT_TRANS(fsl_dma_dbg_cnt, _dma_dbg_cnt) \ -+ switch (_dma_dbg_cnt){ \ -+ case e_FM_DMA_DBG_NO_CNT: \ -+ fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_NO_CNT; break; \ -+ case e_FM_DMA_DBG_CNT_DONE: \ -+ fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_DONE; break; \ -+ case e_FM_DMA_DBG_CNT_COMM_Q_EM: \ -+ fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_COMM_Q_EM; break; \ -+ case e_FM_DMA_DBG_CNT_INT_READ_EM: \ -+ fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_INT_READ_EM; break; \ -+ case e_FM_DMA_DBG_CNT_INT_WRITE_EM: \ -+ fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_INT_WRITE_EM ; break; \ -+ case e_FM_DMA_DBG_CNT_FPM_WAIT: \ -+ fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_FPM_WAIT ; break; \ -+ case e_FM_DMA_DBG_CNT_SIGLE_BIT_ECC: \ -+ fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_SIGLE_BIT_ECC ; break; \ -+ case e_FM_DMA_DBG_CNT_RAW_WAR_PROT: \ -+ fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_RAW_WAR_PROT ; break; \ -+ default: \ -+ fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_NO_CNT; break; \ -+ } -+ -+#define FMAN_DMA_EMER_TRANS(fsl_dma_emer, _dma_emer) \ -+ switch (_dma_emer){ \ -+ case e_FM_DMA_EM_EBS: \ -+ fsl_dma_emer = E_FMAN_DMA_EM_EBS; break; \ -+ case e_FM_DMA_EM_SOS: \ -+ fsl_dma_emer = E_FMAN_DMA_EM_SOS; break; \ -+ default: \ -+ fsl_dma_emer = E_FMAN_DMA_EM_EBS; break; \ -+ } -+ -+#define FMAN_DMA_ERR_TRANS(fsl_dma_err, _dma_err) \ -+ switch (_dma_err){ \ -+ case e_FM_DMA_ERR_CATASTROPHIC: \ -+ fsl_dma_err = E_FMAN_DMA_ERR_CATASTROPHIC; break; \ -+ case e_FM_DMA_ERR_REPORT: \ -+ fsl_dma_err = E_FMAN_DMA_ERR_REPORT; break; \ -+ default: \ -+ fsl_dma_err = E_FMAN_DMA_ERR_CATASTROPHIC; break; \ -+ } -+ -+#define FMAN_CATASTROPHIC_ERR_TRANS(fsl_catastrophic_err, _catastrophic_err) \ -+ switch (_catastrophic_err){ \ -+ case e_FM_CATASTROPHIC_ERR_STALL_PORT: \ -+ fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_PORT; break; \ -+ case e_FM_CATASTROPHIC_ERR_STALL_TASK: \ -+ fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_TASK; break; \ -+ default: \ -+ fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_PORT; break; \ -+ } -+ -+#define FMAN_COUNTERS_TRANS(fsl_counters, _counters) \ -+ switch (_counters){ \ -+ case e_FM_COUNTERS_ENQ_TOTAL_FRAME: \ -+ fsl_counters = E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break; \ -+ case e_FM_COUNTERS_DEQ_TOTAL_FRAME: \ -+ fsl_counters = E_FMAN_COUNTERS_DEQ_TOTAL_FRAME; break; \ -+ case e_FM_COUNTERS_DEQ_0: \ -+ fsl_counters = E_FMAN_COUNTERS_DEQ_0; break; \ -+ case e_FM_COUNTERS_DEQ_1: \ -+ fsl_counters = E_FMAN_COUNTERS_DEQ_1; break; \ -+ case e_FM_COUNTERS_DEQ_2: \ -+ fsl_counters = E_FMAN_COUNTERS_DEQ_2; break; \ -+ case e_FM_COUNTERS_DEQ_3: \ -+ fsl_counters = E_FMAN_COUNTERS_DEQ_3; break; \ -+ case e_FM_COUNTERS_DEQ_FROM_DEFAULT: \ -+ fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_DEFAULT; break; \ -+ case e_FM_COUNTERS_DEQ_FROM_CONTEXT: \ -+ fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_CONTEXT; break; \ -+ case e_FM_COUNTERS_DEQ_FROM_FD: \ -+ fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_FD; break; \ -+ case e_FM_COUNTERS_DEQ_CONFIRM: \ -+ fsl_counters = E_FMAN_COUNTERS_DEQ_CONFIRM; break; \ -+ default: \ -+ fsl_counters = E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break; \ -+ } -+ -+/**************************************************************************//** -+ @Description defaults -+*//***************************************************************************/ -+#define DEFAULT_exceptions (FM_EX_DMA_BUS_ERROR |\ -+ FM_EX_DMA_READ_ECC |\ -+ FM_EX_DMA_SYSTEM_WRITE_ECC |\ -+ FM_EX_DMA_FM_WRITE_ECC |\ -+ FM_EX_FPM_STALL_ON_TASKS |\ -+ FM_EX_FPM_SINGLE_ECC |\ -+ FM_EX_FPM_DOUBLE_ECC |\ -+ FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID|\ -+ FM_EX_BMI_LIST_RAM_ECC |\ -+ FM_EX_BMI_STORAGE_PROFILE_ECC |\ -+ FM_EX_BMI_STATISTICS_RAM_ECC |\ -+ FM_EX_IRAM_ECC |\ -+ FM_EX_MURAM_ECC |\ -+ FM_EX_BMI_DISPATCH_RAM_ECC |\ -+ FM_EX_QMI_DOUBLE_ECC |\ -+ FM_EX_QMI_SINGLE_ECC) -+ -+#define DEFAULT_eccEnable FALSE -+#ifdef FM_PEDANTIC_DMA -+#define DEFAULT_aidOverride TRUE -+#else -+#define DEFAULT_aidOverride FALSE -+#endif /* FM_PEDANTIC_DMA */ -+#define DEFAULT_aidMode e_FM_DMA_AID_OUT_TNUM -+#define DEFAULT_dmaStopOnBusError FALSE -+#define DEFAULT_stopAtBusError FALSE -+#define DEFAULT_axiDbgNumOfBeats 1 -+#define DEFAULT_dmaReadIntBufLow ((DMA_THRESH_MAX_BUF+1)/2) -+#define DEFAULT_dmaReadIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4) -+#define DEFAULT_dmaWriteIntBufLow ((DMA_THRESH_MAX_BUF+1)/2) -+#define DEFAULT_dmaWriteIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4) -+#define DEFAULT_catastrophicErr e_FM_CATASTROPHIC_ERR_STALL_PORT -+#define DEFAULT_dmaErr e_FM_DMA_ERR_CATASTROPHIC -+#define DEFAULT_resetOnInit FALSE -+#define DEFAULT_haltOnExternalActivation FALSE /* do not change! if changed, must be disabled for rev1 ! */ -+#define DEFAULT_haltOnUnrecoverableEccError FALSE /* do not change! if changed, must be disabled for rev1 ! */ -+#define DEFAULT_externalEccRamsEnable FALSE -+#define DEFAULT_VerifyUcode FALSE -+ -+#if (DPAA_VERSION < 11) -+#define DEFAULT_totalFifoSize(major, minor) \ -+ (((major == 2) || (major == 5)) ? \ -+ (100*KILOBYTE) : ((major == 4) ? \ -+ (49*KILOBYTE) : (122*KILOBYTE))) -+#define DEFAULT_totalNumOfTasks(major, minor) \ -+ BMI_MAX_NUM_OF_TASKS -+ -+#define DEFAULT_dmaCommQLow ((DMA_THRESH_MAX_COMMQ+1)/2) -+#define DEFAULT_dmaCommQHigh ((DMA_THRESH_MAX_COMMQ+1)*3/4) -+#define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR -+#define DEFAULT_dmaCamNumOfEntries 32 -+#define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT -+#define DEFAULT_dmaEnEmergency FALSE -+#define DEFAULT_dmaSosEmergency 0 -+#define DEFAULT_dmaWatchdog 0 /* disabled */ -+#define DEFAULT_dmaEnEmergencySmoother FALSE -+#define DEFAULT_dmaEmergencySwitchCounter 0 -+ -+#define DEFAULT_dispLimit 0 -+#define DEFAULT_prsDispTh 16 -+#define DEFAULT_plcrDispTh 16 -+#define DEFAULT_kgDispTh 16 -+#define DEFAULT_bmiDispTh 16 -+#define DEFAULT_qmiEnqDispTh 16 -+#define DEFAULT_qmiDeqDispTh 16 -+#define DEFAULT_fmCtl1DispTh 16 -+#define DEFAULT_fmCtl2DispTh 16 -+ -+#else /* (DPAA_VERSION < 11) */ -+/* Defaults are registers' reset values */ -+#define DEFAULT_totalFifoSize(major, minor) \ -+ (((major == 6) && ((minor == 1) || (minor == 4))) ? \ -+ (156*KILOBYTE) : (295*KILOBYTE)) -+ -+/* According to the default value of FMBM_CFG2[TNTSKS] */ -+#define DEFAULT_totalNumOfTasks(major, minor) \ -+ (((major == 6) && ((minor == 1) || (minor == 4))) ? 59 : 124) -+ -+#define DEFAULT_dmaCommQLow 0x2A -+#define DEFAULT_dmaCommQHigh 0x3F -+#define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR -+#define DEFAULT_dmaCamNumOfEntries 64 -+#define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT -+#define DEFAULT_dmaEnEmergency FALSE -+#define DEFAULT_dmaSosEmergency 0 -+#define DEFAULT_dmaWatchdog 0 /* disabled */ -+#define DEFAULT_dmaEnEmergencySmoother FALSE -+#define DEFAULT_dmaEmergencySwitchCounter 0 -+ -+#define DEFAULT_dispLimit 0 -+#define DEFAULT_prsDispTh 16 -+#define DEFAULT_plcrDispTh 16 -+#define DEFAULT_kgDispTh 16 -+#define DEFAULT_bmiDispTh 16 -+#define DEFAULT_qmiEnqDispTh 16 -+#define DEFAULT_qmiDeqDispTh 16 -+#define DEFAULT_fmCtl1DispTh 16 -+#define DEFAULT_fmCtl2DispTh 16 -+#endif /* (DPAA_VERSION < 11) */ -+ -+#define FM_TIMESTAMP_1_USEC_BIT 8 -+ -+/**************************************************************************//** -+ @Collection Defines used for enabling/disabling FM interrupts -+ @{ -+*//***************************************************************************/ -+#define ERR_INTR_EN_DMA 0x00010000 -+#define ERR_INTR_EN_FPM 0x80000000 -+#define ERR_INTR_EN_BMI 0x00800000 -+#define ERR_INTR_EN_QMI 0x00400000 -+#define ERR_INTR_EN_PRS 0x00200000 -+#define ERR_INTR_EN_KG 0x00100000 -+#define ERR_INTR_EN_PLCR 0x00080000 -+#define ERR_INTR_EN_MURAM 0x00040000 -+#define ERR_INTR_EN_IRAM 0x00020000 -+#define ERR_INTR_EN_10G_MAC0 0x00008000 -+#define ERR_INTR_EN_10G_MAC1 0x00000040 -+#define ERR_INTR_EN_1G_MAC0 0x00004000 -+#define ERR_INTR_EN_1G_MAC1 0x00002000 -+#define ERR_INTR_EN_1G_MAC2 0x00001000 -+#define ERR_INTR_EN_1G_MAC3 0x00000800 -+#define ERR_INTR_EN_1G_MAC4 0x00000400 -+#define ERR_INTR_EN_1G_MAC5 0x00000200 -+#define ERR_INTR_EN_1G_MAC6 0x00000100 -+#define ERR_INTR_EN_1G_MAC7 0x00000080 -+#define ERR_INTR_EN_MACSEC_MAC0 0x00000001 -+ -+#define INTR_EN_QMI 0x40000000 -+#define INTR_EN_PRS 0x20000000 -+#define INTR_EN_WAKEUP 0x10000000 -+#define INTR_EN_PLCR 0x08000000 -+#define INTR_EN_1G_MAC0 0x00080000 -+#define INTR_EN_1G_MAC1 0x00040000 -+#define INTR_EN_1G_MAC2 0x00020000 -+#define INTR_EN_1G_MAC3 0x00010000 -+#define INTR_EN_1G_MAC4 0x00000040 -+#define INTR_EN_1G_MAC5 0x00000020 -+#define INTR_EN_1G_MAC6 0x00000008 -+#define INTR_EN_1G_MAC7 0x00000002 -+#define INTR_EN_10G_MAC0 0x00200000 -+#define INTR_EN_10G_MAC1 0x00100000 -+#define INTR_EN_REV0 0x00008000 -+#define INTR_EN_REV1 0x00004000 -+#define INTR_EN_REV2 0x00002000 -+#define INTR_EN_REV3 0x00001000 -+#define INTR_EN_BRK 0x00000080 -+#define INTR_EN_TMR 0x01000000 -+#define INTR_EN_MACSEC_MAC0 0x00000001 -+/* @} */ -+ -+/**************************************************************************//** -+ @Description Memory Mapped Registers -+*//***************************************************************************/ -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+typedef struct -+{ -+ volatile uint32_t iadd; /**< FM IRAM instruction address register */ -+ volatile uint32_t idata; /**< FM IRAM instruction data register */ -+ volatile uint32_t itcfg; /**< FM IRAM timing config register */ -+ volatile uint32_t iready; /**< FM IRAM ready register */ -+ volatile uint32_t res[0x1FFFC]; -+} t_FMIramRegs; -+ -+/* Trace buffer registers - -+ each FM Controller has its own trace buffer residing at FM_MM_TRB(fmCtrlIndex) offset */ -+typedef struct t_FmTrbRegs -+{ -+ volatile uint32_t tcrh; -+ volatile uint32_t tcrl; -+ volatile uint32_t tesr; -+ volatile uint32_t tecr0h; -+ volatile uint32_t tecr0l; -+ volatile uint32_t terf0h; -+ volatile uint32_t terf0l; -+ volatile uint32_t tecr1h; -+ volatile uint32_t tecr1l; -+ volatile uint32_t terf1h; -+ volatile uint32_t terf1l; -+ volatile uint32_t tpcch; -+ volatile uint32_t tpccl; -+ volatile uint32_t tpc1h; -+ volatile uint32_t tpc1l; -+ volatile uint32_t tpc2h; -+ volatile uint32_t tpc2l; -+ volatile uint32_t twdimr; -+ volatile uint32_t twicvr; -+ volatile uint32_t tar; -+ volatile uint32_t tdr; -+ volatile uint32_t tsnum1; -+ volatile uint32_t tsnum2; -+ volatile uint32_t tsnum3; -+ volatile uint32_t tsnum4; -+} t_FmTrbRegs; -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+/**************************************************************************//** -+ @Description General defines -+*//***************************************************************************/ -+#define FM_DEBUG_STATUS_REGISTER_OFFSET 0x000d1084UL -+#define FM_FW_DEBUG_INSTRUCTION 0x6ffff805UL -+ -+/**************************************************************************//** -+ @Description FPM defines -+*//***************************************************************************/ -+/* masks */ -+#define FPM_BRKC_RDBG 0x00000200 -+#define FPM_BRKC_SLP 0x00000800 -+/**************************************************************************//** -+ @Description BMI defines -+*//***************************************************************************/ -+/* masks */ -+#define BMI_INIT_START 0x80000000 -+#define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC 0x80000000 -+#define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000 -+#define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000 -+#define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000 -+/**************************************************************************//** -+ @Description QMI defines -+*//***************************************************************************/ -+/* masks */ -+#define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000 -+#define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000 -+#define QMI_INTR_EN_SINGLE_ECC 0x80000000 -+ -+/**************************************************************************//** -+ @Description IRAM defines -+*//***************************************************************************/ -+/* masks */ -+#define IRAM_IADD_AIE 0x80000000 -+#define IRAM_READY 0x80000000 -+ -+/**************************************************************************//** -+ @Description TRB defines -+*//***************************************************************************/ -+/* masks */ -+#define TRB_TCRH_RESET 0x04000000 -+#define TRB_TCRH_ENABLE_COUNTERS 0x84008000 -+#define TRB_TCRH_DISABLE_COUNTERS 0x8400C000 -+#define TRB_TCRL_RESET 0x20000000 -+#define TRB_TCRL_UTIL 0x00000460 -+typedef struct { -+ void (*f_Isr) (t_Handle h_Arg, uint32_t event); -+ t_Handle h_SrcHandle; -+} t_FmanCtrlIntrSrc; -+ -+ -+typedef void (t_FmanCtrlIsr)( t_Handle h_Fm, uint32_t event); -+ -+typedef struct -+{ -+/***************************/ -+/* Master/Guest parameters */ -+/***************************/ -+ uint8_t fmId; -+ e_FmPortType portsTypes[FM_MAX_NUM_OF_HW_PORT_IDS]; -+ uint16_t fmClkFreq; -+ uint16_t fmMacClkFreq; -+ t_FmRevisionInfo revInfo; -+/**************************/ -+/* Master Only parameters */ -+/**************************/ -+ bool enabledTimeStamp; -+ uint8_t count1MicroBit; -+ uint8_t totalNumOfTasks; -+ uint32_t totalFifoSize; -+ uint8_t maxNumOfOpenDmas; -+ uint8_t accumulatedNumOfTasks; -+ uint32_t accumulatedFifoSize; -+ uint8_t accumulatedNumOfOpenDmas; -+ uint8_t accumulatedNumOfDeqTnums; -+#ifdef FM_LOW_END_RESTRICTION -+ bool lowEndRestriction; -+#endif /* FM_LOW_END_RESTRICTION */ -+ uint32_t exceptions; -+ int irq; -+ int errIrq; -+ bool ramsEccEnable; -+ bool explicitEnable; -+ bool internalCall; -+ uint8_t ramsEccOwners; -+ uint32_t extraFifoPoolSize; -+ uint8_t extraTasksPoolSize; -+ uint8_t extraOpenDmasPoolSize; -+#if defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS) -+ uint16_t portMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS]; -+ uint16_t macMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS]; -+#endif /* defined(FM_MAX_NUM_OF_10G_MACS) && ... */ -+ uint16_t portMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS]; -+ uint16_t macMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS]; -+} t_FmStateStruct; -+ -+#if (DPAA_VERSION >= 11) -+typedef struct t_FmMapParam { -+ uint16_t profilesBase; -+ uint16_t numOfProfiles; -+ t_Handle h_FmPort; -+} t_FmMapParam; -+ -+typedef struct t_FmAllocMng { -+ bool allocated; -+ uint8_t ownerId; /* guestId for KG in multi-partition only, -+ portId for PLCR in any environment */ -+} t_FmAllocMng; -+ -+typedef struct t_FmPcdSpEntry { -+ bool valid; -+ t_FmAllocMng profilesMng; -+} t_FmPcdSpEntry; -+ -+typedef struct t_FmSp { -+ void *p_FmPcdStoragePrflRegs; -+ t_FmPcdSpEntry profiles[FM_VSP_MAX_NUM_OF_ENTRIES]; -+ t_FmMapParam portsMapping[FM_MAX_NUM_OF_PORTS]; -+} t_FmSp; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+typedef struct t_Fm -+{ -+/***************************/ -+/* Master/Guest parameters */ -+/***************************/ -+/* locals for recovery */ -+ uintptr_t baseAddr; -+ -+/* un-needed for recovery */ -+ t_Handle h_Pcd; -+ char fmModuleName[MODULE_NAME_SIZE]; -+ char fmIpcHandlerModuleName[FM_MAX_NUM_OF_GUESTS][MODULE_NAME_SIZE]; -+ t_Handle h_IpcSessions[FM_MAX_NUM_OF_GUESTS]; -+ t_FmIntrSrc intrMng[e_FM_EV_DUMMY_LAST]; /* FM exceptions user callback */ -+ uint8_t guestId; -+/**************************/ -+/* Master Only parameters */ -+/**************************/ -+/* locals for recovery */ -+ struct fman_fpm_regs *p_FmFpmRegs; -+ struct fman_bmi_regs *p_FmBmiRegs; -+ struct fman_qmi_regs *p_FmQmiRegs; -+ struct fman_dma_regs *p_FmDmaRegs; -+ struct fman_regs *p_FmRegs; -+ t_FmExceptionsCallback *f_Exception; -+ t_FmBusErrorCallback *f_BusError; -+ t_Handle h_App; /* Application handle */ -+ t_Handle h_Spinlock; -+ bool recoveryMode; -+ t_FmStateStruct *p_FmStateStruct; -+ uint16_t tnumAgingPeriod; -+#if (DPAA_VERSION >= 11) -+ t_FmSp *p_FmSp; -+ uint8_t partNumOfVSPs; -+ uint8_t partVSPBase; -+ uintptr_t vspBaseAddr; -+#endif /* (DPAA_VERSION >= 11) */ -+ bool portsPreFetchConfigured[FM_MAX_NUM_OF_HW_PORT_IDS]; /* Prefetch configration per Tx-port */ -+ bool portsPreFetchValue[FM_MAX_NUM_OF_HW_PORT_IDS]; /* Prefetch configration per Tx-port */ -+ -+/* un-needed for recovery */ -+ struct fman_cfg *p_FmDriverParam; -+ t_Handle h_FmMuram; -+ uint64_t fmMuramPhysBaseAddr; -+ bool independentMode; -+ bool hcPortInitialized; -+ uintptr_t camBaseAddr; /* save for freeing */ -+ uintptr_t resAddr; -+ uintptr_t fifoBaseAddr; /* save for freeing */ -+ t_FmanCtrlIntrSrc fmanCtrlIntr[FM_NUM_OF_FMAN_CTRL_EVENT_REGS]; /* FM exceptions user callback */ -+ bool usedEventRegs[FM_NUM_OF_FMAN_CTRL_EVENT_REGS]; -+ t_FmFirmwareParams firmware; -+ bool fwVerify; -+ bool resetOnInit; -+ uint32_t userSetExceptions; -+} t_Fm; -+ -+ -+#endif /* __FM_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm_ipc.h -@@ -0,0 +1,465 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File fm_ipc.h -+ -+ @Description FM Inter-Partition prototypes, structures and definitions. -+*//***************************************************************************/ -+#ifndef __FM_IPC_H -+#define __FM_IPC_H -+ -+#include "error_ext.h" -+#include "std_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group FM_grp Frame Manager API -+ -+ @Description FM API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group FM_IPC_grp FM Inter-Partition messaging Unit -+ -+ @Description FM Inter-Partition messaging unit API definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+/**************************************************************************//** -+ @Description enum for defining MAC types -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description A structure of parameters for specifying a MAC. -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ uint8_t id; -+ uint32_t enumType; -+} _PackedType t_FmIpcMacParams; -+ -+/**************************************************************************//** -+ @Description A structure of parameters for specifying a MAC. -+*//***************************************************************************/ -+typedef _Packed struct -+{ -+ t_FmIpcMacParams macParams; -+ uint16_t maxFrameLength; -+} _PackedType t_FmIpcMacMaxFrameParams; -+ -+/**************************************************************************//** -+ @Description FM physical Address -+*//***************************************************************************/ -+typedef _Packed struct t_FmIpcPhysAddr -+{ -+ volatile uint8_t high; -+ volatile uint32_t low; -+} _PackedType t_FmIpcPhysAddr; -+ -+ -+typedef _Packed struct t_FmIpcPortOutInitParams { -+ uint8_t numOfTasks; /**< OUT */ -+ uint8_t numOfExtraTasks; /**< OUT */ -+ uint8_t numOfOpenDmas; /**< OUT */ -+ uint8_t numOfExtraOpenDmas; /**< OUT */ -+ uint32_t sizeOfFifo; /**< OUT */ -+ uint32_t extraSizeOfFifo; /**< OUT */ -+ t_FmIpcPhysAddr ipcPhysAddr; /**< OUT */ -+} _PackedType t_FmIpcPortOutInitParams; -+ -+/**************************************************************************//** -+ @Description Structure for IPC communication during FM_PORT_Init. -+*//***************************************************************************/ -+typedef _Packed struct t_FmIpcPortInInitParams { -+ uint8_t hardwarePortId; /**< IN. port Id */ -+ uint32_t enumPortType; /**< IN. Port type */ -+ uint8_t boolIndependentMode;/**< IN. TRUE if FM Port operates in independent mode */ -+ uint16_t liodnOffset; /**< IN. Port's requested resource */ -+ uint8_t numOfTasks; /**< IN. Port's requested resource */ -+ uint8_t numOfExtraTasks; /**< IN. Port's requested resource */ -+ uint8_t numOfOpenDmas; /**< IN. Port's requested resource */ -+ uint8_t numOfExtraOpenDmas; /**< IN. Port's requested resource */ -+ uint32_t sizeOfFifo; /**< IN. Port's requested resource */ -+ uint32_t extraSizeOfFifo; /**< IN. Port's requested resource */ -+ uint8_t deqPipelineDepth; /**< IN. Port's requested resource */ -+ uint16_t maxFrameLength; /**< IN. Port's max frame length. */ -+ uint16_t liodnBase; /**< IN. Irrelevant for P4080 rev 1. -+ LIODN base for this port, to be -+ used together with LIODN offset. */ -+} _PackedType t_FmIpcPortInInitParams; -+ -+ -+/**************************************************************************//** -+ @Description Structure for IPC communication between port and FM -+ regarding tasks and open DMA resources management. -+*//***************************************************************************/ -+typedef _Packed struct t_FmIpcPortRsrcParams { -+ uint8_t hardwarePortId; /**< IN. port Id */ -+ uint32_t val; /**< IN. Port's requested resource */ -+ uint32_t extra; /**< IN. Port's requested resource */ -+ uint8_t boolInitialConfig; -+} _PackedType t_FmIpcPortRsrcParams; -+ -+ -+/**************************************************************************//** -+ @Description Structure for IPC communication between port and FM -+ regarding tasks and open DMA resources management. -+*//***************************************************************************/ -+typedef _Packed struct t_FmIpcPortFifoParams { -+ t_FmIpcPortRsrcParams rsrcParams; -+ uint32_t enumPortType; -+ uint8_t boolIndependentMode; -+ uint8_t deqPipelineDepth; -+ uint8_t numOfPools; -+ uint16_t secondLargestBufSize; -+ uint16_t largestBufSize; -+ uint8_t boolInitialConfig; -+} _PackedType t_FmIpcPortFifoParams; -+ -+/**************************************************************************//** -+ @Description Structure for port-FM communication during FM_PORT_Free. -+*//***************************************************************************/ -+typedef _Packed struct t_FmIpcPortFreeParams { -+ uint8_t hardwarePortId; /**< IN. port Id */ -+ uint32_t enumPortType; /**< IN. Port type */ -+ uint8_t deqPipelineDepth; /**< IN. Port's requested resource */ -+} _PackedType t_FmIpcPortFreeParams; -+ -+/**************************************************************************//** -+ @Description Structure for defining DMA status -+*//***************************************************************************/ -+typedef _Packed struct t_FmIpcDmaStatus { -+ uint8_t boolCmqNotEmpty; /**< Command queue is not empty */ -+ uint8_t boolBusError; /**< Bus error occurred */ -+ uint8_t boolReadBufEccError; /**< Double ECC error on buffer Read */ -+ uint8_t boolWriteBufEccSysError; /**< Double ECC error on buffer write from system side */ -+ uint8_t boolWriteBufEccFmError; /**< Double ECC error on buffer write from FM side */ -+ uint8_t boolSinglePortEccError; /**< Single port ECC error from FM side */ -+} _PackedType t_FmIpcDmaStatus; -+ -+typedef _Packed struct t_FmIpcRegisterIntr -+{ -+ uint8_t guestId; /* IN */ -+ uint32_t event; /* IN */ -+} _PackedType t_FmIpcRegisterIntr; -+ -+typedef _Packed struct t_FmIpcIsr -+{ -+ uint8_t boolErr; /* IN */ -+ uint32_t pendingReg; /* IN */ -+} _PackedType t_FmIpcIsr; -+ -+/**************************************************************************//** -+ @Description structure for returning FM parameters -+*//***************************************************************************/ -+typedef _Packed struct t_FmIpcParams { -+ uint16_t fmClkFreq; /**< OUT: FM Clock frequency */ -+ uint16_t fmMacClkFreq; /**< OUT: FM MAC clock frequence */ -+ uint8_t majorRev; /**< OUT: FM Major revision */ -+ uint8_t minorRev; /**< OUT: FM Minor revision */ -+} _PackedType t_FmIpcParams; -+ -+ -+/**************************************************************************//** -+ @Description structure for returning Fman Ctrl Code revision information -+*//***************************************************************************/ -+typedef _Packed struct t_FmIpcFmanCtrlCodeRevisionInfo { -+ uint16_t packageRev; /**< OUT: Package revision */ -+ uint8_t majorRev; /**< OUT: Major revision */ -+ uint8_t minorRev; /**< OUT: Minor revision */ -+} _PackedType t_FmIpcFmanCtrlCodeRevisionInfo; -+ -+/**************************************************************************//** -+ @Description Structure for defining Fm number of Fman controlers -+*//***************************************************************************/ -+typedef _Packed struct t_FmIpcPortNumOfFmanCtrls { -+ uint8_t hardwarePortId; /**< IN. port Id */ -+ uint8_t numOfFmanCtrls; /**< IN. Port type */ -+ t_FmFmanCtrl orFmanCtrl; /**< IN. fman controller for order restoration*/ -+} t_FmIpcPortNumOfFmanCtrls; -+ -+/**************************************************************************//** -+ @Description structure for setting Fman contriller events -+*//***************************************************************************/ -+typedef _Packed struct t_FmIpcFmanEvents { -+ uint8_t eventRegId; /**< IN: Fman controller event register id */ -+ uint32_t enableEvents; /**< IN/OUT: required enabled events mask */ -+} _PackedType t_FmIpcFmanEvents; -+ -+typedef _Packed struct t_FmIpcResourceAllocParams { -+ uint8_t guestId; -+ uint16_t base; -+ uint16_t num; -+}_PackedType t_FmIpcResourceAllocParams; -+ -+typedef _Packed struct t_FmIpcVspSetPortWindow { -+ uint8_t hardwarePortId; -+ uint8_t baseStorageProfile; -+ uint8_t log2NumOfProfiles; -+}_PackedType t_FmIpcVspSetPortWindow; -+ -+typedef _Packed struct t_FmIpcSetCongestionGroupPfcPriority { -+ uint32_t congestionGroupId; -+ uint8_t priorityBitMap; -+}_PackedType t_FmIpcSetCongestionGroupPfcPriority; -+ -+#define FM_IPC_MAX_REPLY_BODY_SIZE 20 -+#define FM_IPC_MAX_REPLY_SIZE (FM_IPC_MAX_REPLY_BODY_SIZE + sizeof(uint32_t)) -+#define FM_IPC_MAX_MSG_SIZE 30 -+ -+typedef _Packed struct t_FmIpcMsg -+{ -+ uint32_t msgId; -+ uint8_t msgBody[FM_IPC_MAX_MSG_SIZE]; -+} _PackedType t_FmIpcMsg; -+ -+typedef _Packed struct t_FmIpcReply -+{ -+ uint32_t error; -+ uint8_t replyBody[FM_IPC_MAX_REPLY_BODY_SIZE]; -+} _PackedType t_FmIpcReply; -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+ -+/***************************************************************************/ -+/************************ FRONT-END-TO-BACK-END*****************************/ -+/***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_GET_TIMESTAMP_SCALE -+ -+ @Description Used by FM front-end. -+ -+ @Param[out] uint32_t Pointer -+*//***************************************************************************/ -+#define FM_GET_TIMESTAMP_SCALE 1 -+ -+/**************************************************************************//** -+ @Function FM_GET_COUNTER -+ -+ @Description Used by FM front-end. -+ -+ @Param[in/out] t_FmIpcGetCounter Pointer -+*//***************************************************************************/ -+#define FM_GET_COUNTER 2 -+ -+/**************************************************************************//** -+ @Function FM_GET_SET_PORT_PARAMS -+ -+ @Description Used by FM front-end for the PORT module in order to set and get -+ parameters in/from master FM module on FM PORT initialization time. -+ -+ @Param[in/out] t_FmIcPortInitParams Pointer -+*//***************************************************************************/ -+#define FM_GET_SET_PORT_PARAMS 4 -+ -+/**************************************************************************//** -+ @Function FM_FREE_PORT -+ -+ @Description Used by FM front-end for the PORT module when a port is freed -+ to free all FM PORT resources. -+ -+ @Param[in] uint8_t Pointer -+*//***************************************************************************/ -+#define FM_FREE_PORT 5 -+ -+/**************************************************************************//** -+ @Function FM_RESET_MAC -+ -+ @Description Used by front-end for the MAC module to reset the MAC registers -+ -+ @Param[in] t_FmIpcMacParams Pointer . -+*//***************************************************************************/ -+#define FM_RESET_MAC 6 -+ -+/**************************************************************************//** -+ @Function FM_RESUME_STALLED_PORT -+ -+ @Description Used by FM front-end for the PORT module in order to -+ release a stalled FM Port. -+ -+ @Param[in] uint8_t Pointer -+*//***************************************************************************/ -+#define FM_RESUME_STALLED_PORT 7 -+ -+/**************************************************************************//** -+ @Function FM_IS_PORT_STALLED -+ -+ @Description Used by FM front-end for the PORT module in order to check whether -+ an FM port is stalled. -+ -+ @Param[in/out] t_FmIcPortIsStalled Pointer -+*//***************************************************************************/ -+#define FM_IS_PORT_STALLED 8 -+ -+/**************************************************************************//** -+ @Function FM_GET_PARAMS -+ -+ @Description Used by FM front-end for the PORT module in order to dump -+ return FM parameters. -+ -+ @Param[in] uint8_t Pointer -+*//***************************************************************************/ -+#define FM_GET_PARAMS 10 -+ -+/**************************************************************************//** -+ @Function FM_REGISTER_INTR -+ -+ @Description Used by FM front-end to register an interrupt handler to -+ be called upon interrupt for guest. -+ -+ @Param[out] t_FmIpcRegisterIntr Pointer -+*//***************************************************************************/ -+#define FM_REGISTER_INTR 11 -+ -+/**************************************************************************//** -+ @Function FM_DMA_STAT -+ -+ @Description Used by FM front-end to read the FM DMA status. -+ -+ @Param[out] t_FmIpcDmaStatus Pointer -+*//***************************************************************************/ -+#define FM_DMA_STAT 13 -+ -+/**************************************************************************//** -+ @Function FM_ALLOC_FMAN_CTRL_EVENT_REG -+ -+ @Description Used by FM front-end to allocate event register. -+ -+ @Param[out] Event register id Pointer -+*//***************************************************************************/ -+#define FM_ALLOC_FMAN_CTRL_EVENT_REG 14 -+ -+/**************************************************************************//** -+ @Function FM_FREE_FMAN_CTRL_EVENT_REG -+ -+ @Description Used by FM front-end to free locate event register. -+ -+ @Param[in] uint8_t Pointer - Event register id -+*//***************************************************************************/ -+#define FM_FREE_FMAN_CTRL_EVENT_REG 15 -+ -+/**************************************************************************//** -+ @Function FM_SET_FMAN_CTRL_EVENTS_ENABLE -+ -+ @Description Used by FM front-end to enable events in the FPM -+ Fman controller event register. -+ -+ @Param[in] t_FmIpcFmanEvents Pointer -+*//***************************************************************************/ -+#define FM_SET_FMAN_CTRL_EVENTS_ENABLE 16 -+ -+/**************************************************************************//** -+ @Function FM_SET_FMAN_CTRL_EVENTS_ENABLE -+ -+ @Description Used by FM front-end to enable events in the FPM -+ Fman controller event register. -+ -+ @Param[in/out] t_FmIpcFmanEvents Pointer -+*//***************************************************************************/ -+#define FM_GET_FMAN_CTRL_EVENTS_ENABLE 17 -+ -+/**************************************************************************//** -+ @Function FM_SET_MAC_MAX_FRAME -+ -+ @Description Used by FM front-end to set MAC's MTU/RTU's in -+ back-end. -+ -+ @Param[in/out] t_FmIpcMacMaxFrameParams Pointer -+*//***************************************************************************/ -+#define FM_SET_MAC_MAX_FRAME 18 -+ -+/**************************************************************************//** -+ @Function FM_GET_PHYS_MURAM_BASE -+ -+ @Description Used by FM front-end in order to get MURAM base address -+ -+ @Param[in/out] t_FmIpcPhysAddr Pointer -+*//***************************************************************************/ -+#define FM_GET_PHYS_MURAM_BASE 19 -+ -+/**************************************************************************//** -+ @Function FM_MASTER_IS_ALIVE -+ -+ @Description Used by FM front-end in order to verify Master is up -+ -+ @Param[in/out] bool -+*//***************************************************************************/ -+#define FM_MASTER_IS_ALIVE 20 -+ -+#define FM_ENABLE_RAM_ECC 21 -+#define FM_DISABLE_RAM_ECC 22 -+#define FM_SET_NUM_OF_FMAN_CTRL 23 -+#define FM_SET_SIZE_OF_FIFO 24 -+#define FM_SET_NUM_OF_TASKS 25 -+#define FM_SET_NUM_OF_OPEN_DMAS 26 -+#define FM_VSP_ALLOC 27 -+#define FM_VSP_FREE 28 -+#define FM_VSP_SET_PORT_WINDOW 29 -+#define FM_GET_FMAN_CTRL_CODE_REV 30 -+#define FM_SET_CONG_GRP_PFC_PRIO 31 -+#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -+#define FM_10G_TX_ECC_WA 100 -+#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ -+ -+/***************************************************************************/ -+/************************ BACK-END-TO-FRONT-END*****************************/ -+/***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_GUEST_ISR -+ -+ @Description Used by FM back-end to report an interrupt to the front-end. -+ -+ @Param[out] t_FmIpcIsr Pointer -+*//***************************************************************************/ -+#define FM_GUEST_ISR 1 -+ -+ -+ -+/** @} */ /* end of FM_IPC_grp group */ -+/** @} */ /* end of FM_grp group */ -+ -+ -+#endif /* __FM_IPC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm_muram.c -@@ -0,0 +1,174 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File FM_muram.c -+ -+ @Description FM MURAM ... -+*//***************************************************************************/ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "mm_ext.h" -+#include "string_ext.h" -+#include "sprint_ext.h" -+#include "fm_muram_ext.h" -+#include "fm_common.h" -+ -+#define __ERR_MODULE__ MODULE_FM_MURAM -+ -+ -+typedef struct -+{ -+ t_Handle h_Mem; -+ uintptr_t baseAddr; -+ uint32_t size; -+} t_FmMuram; -+ -+ -+void FmMuramClear(t_Handle h_FmMuram) -+{ -+ t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram; -+ -+ SANITY_CHECK_RETURN(h_FmMuram, E_INVALID_HANDLE); -+ IOMemSet32(UINT_TO_PTR(p_FmMuram->baseAddr), 0, p_FmMuram->size); -+} -+ -+ -+t_Handle FM_MURAM_ConfigAndInit(uintptr_t baseAddress, uint32_t size) -+{ -+ t_Handle h_Mem; -+ t_FmMuram *p_FmMuram; -+ -+ if (!baseAddress) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("baseAddress 0 is not supported")); -+ return NULL; -+ } -+ -+ if (baseAddress%4) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("baseAddress not 4 bytes aligned!")); -+ return NULL; -+ } -+ -+ /* Allocate FM MURAM structure */ -+ p_FmMuram = (t_FmMuram *) XX_Malloc(sizeof(t_FmMuram)); -+ if (!p_FmMuram) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MURAM driver structure")); -+ return NULL; -+ } -+ memset(p_FmMuram, 0, sizeof(t_FmMuram)); -+ -+ -+ if ((MM_Init(&h_Mem, baseAddress, size) != E_OK) || (!h_Mem)) -+ { -+ XX_Free(p_FmMuram); -+ REPORT_ERROR(MAJOR, E_INVALID_HANDLE, ("FM-MURAM partition!!!")); -+ return NULL; -+ } -+ -+ /* Initialize FM MURAM parameters which will be kept by the driver */ -+ p_FmMuram->baseAddr = baseAddress; -+ p_FmMuram->size = size; -+ p_FmMuram->h_Mem = h_Mem; -+ -+ return p_FmMuram; -+} -+ -+t_Error FM_MURAM_Free(t_Handle h_FmMuram) -+{ -+ t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram; -+ -+ if (p_FmMuram->h_Mem) -+ MM_Free(p_FmMuram->h_Mem); -+ -+ XX_Free(h_FmMuram); -+ -+ return E_OK; -+} -+ -+void * FM_MURAM_AllocMem(t_Handle h_FmMuram, uint32_t size, uint32_t align) -+{ -+ t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram; -+ uintptr_t addr; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmMuram, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(p_FmMuram->h_Mem, E_INVALID_HANDLE, NULL); -+ -+ addr = (uintptr_t)MM_Get(p_FmMuram->h_Mem, size, align ,"FM MURAM"); -+ -+ if (addr == ILLEGAL_BASE) -+ return NULL; -+ -+ return UINT_TO_PTR(addr); -+} -+ -+void * FM_MURAM_AllocMemForce(t_Handle h_FmMuram, uint64_t base, uint32_t size) -+{ -+ t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram; -+ uintptr_t addr; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmMuram, E_INVALID_HANDLE, NULL); -+ SANITY_CHECK_RETURN_VALUE(p_FmMuram->h_Mem, E_INVALID_HANDLE, NULL); -+ -+ addr = (uintptr_t)MM_GetForce(p_FmMuram->h_Mem, base, size, "FM MURAM"); -+ -+ if (addr == ILLEGAL_BASE) -+ return NULL; -+ -+ return UINT_TO_PTR(addr); -+} -+ -+t_Error FM_MURAM_FreeMem(t_Handle h_FmMuram, void *ptr) -+{ -+ t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram; -+ -+ SANITY_CHECK_RETURN_ERROR(h_FmMuram, E_INVALID_HANDLE); -+ SANITY_CHECK_RETURN_ERROR(p_FmMuram->h_Mem, E_INVALID_HANDLE); -+ -+ if (MM_Put(p_FmMuram->h_Mem, PTR_TO_UINT(ptr)) == 0) -+ RETURN_ERROR(MINOR, E_INVALID_ADDRESS, ("memory pointer!!!")); -+ -+ return E_OK; -+} -+ -+uint64_t FM_MURAM_GetFreeMemSize(t_Handle h_FmMuram) -+{ -+ t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram; -+ -+ SANITY_CHECK_RETURN_VALUE(h_FmMuram, E_INVALID_HANDLE, 0); -+ SANITY_CHECK_RETURN_VALUE(p_FmMuram->h_Mem, E_INVALID_HANDLE, 0); -+ -+ return MM_GetFreeMemSize(p_FmMuram->h_Mem); -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fman.c -@@ -0,0 +1,1399 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+ -+#include "fsl_fman.h" -+#include "dpaa_integration_ext.h" -+ -+uint32_t fman_get_bmi_err_event(struct fman_bmi_regs *bmi_rg) -+{ -+ uint32_t event, mask, force; -+ -+ event = ioread32be(&bmi_rg->fmbm_ievr); -+ mask = ioread32be(&bmi_rg->fmbm_ier); -+ event &= mask; -+ /* clear the forced events */ -+ force = ioread32be(&bmi_rg->fmbm_ifr); -+ if (force & event) -+ iowrite32be(force & ~event, &bmi_rg->fmbm_ifr); -+ /* clear the acknowledged events */ -+ iowrite32be(event, &bmi_rg->fmbm_ievr); -+ return event; -+} -+ -+uint32_t fman_get_qmi_err_event(struct fman_qmi_regs *qmi_rg) -+{ -+ uint32_t event, mask, force; -+ -+ event = ioread32be(&qmi_rg->fmqm_eie); -+ mask = ioread32be(&qmi_rg->fmqm_eien); -+ event &= mask; -+ -+ /* clear the forced events */ -+ force = ioread32be(&qmi_rg->fmqm_eif); -+ if (force & event) -+ iowrite32be(force & ~event, &qmi_rg->fmqm_eif); -+ /* clear the acknowledged events */ -+ iowrite32be(event, &qmi_rg->fmqm_eie); -+ return event; -+} -+ -+uint32_t fman_get_dma_com_id(struct fman_dma_regs *dma_rg) -+{ -+ return ioread32be(&dma_rg->fmdmtcid); -+} -+ -+uint64_t fman_get_dma_addr(struct fman_dma_regs *dma_rg) -+{ -+ uint64_t addr; -+ -+ addr = (uint64_t)ioread32be(&dma_rg->fmdmtal); -+ addr |= ((uint64_t)(ioread32be(&dma_rg->fmdmtah)) << 32); -+ -+ return addr; -+} -+ -+uint32_t fman_get_dma_err_event(struct fman_dma_regs *dma_rg) -+{ -+ uint32_t status, mask; -+ -+ status = ioread32be(&dma_rg->fmdmsr); -+ mask = ioread32be(&dma_rg->fmdmmr); -+ -+ /* clear DMA_STATUS_BUS_ERR if mask has no DMA_MODE_BER */ -+ if ((mask & DMA_MODE_BER) != DMA_MODE_BER) -+ status &= ~DMA_STATUS_BUS_ERR; -+ -+ /* clear relevant bits if mask has no DMA_MODE_ECC */ -+ if ((mask & DMA_MODE_ECC) != DMA_MODE_ECC) -+ status &= ~(DMA_STATUS_FM_SPDAT_ECC | -+ DMA_STATUS_READ_ECC | -+ DMA_STATUS_SYSTEM_WRITE_ECC | -+ DMA_STATUS_FM_WRITE_ECC); -+ -+ /* clear set events */ -+ iowrite32be(status, &dma_rg->fmdmsr); -+ -+ return status; -+} -+ -+uint32_t fman_get_fpm_err_event(struct fman_fpm_regs *fpm_rg) -+{ -+ uint32_t event; -+ -+ event = ioread32be(&fpm_rg->fmfp_ee); -+ /* clear the all occurred events */ -+ iowrite32be(event, &fpm_rg->fmfp_ee); -+ return event; -+} -+ -+uint32_t fman_get_muram_err_event(struct fman_fpm_regs *fpm_rg) -+{ -+ uint32_t event, mask; -+ -+ event = ioread32be(&fpm_rg->fm_rcr); -+ mask = ioread32be(&fpm_rg->fm_rie); -+ -+ /* clear MURAM event bit (do not clear IRAM event) */ -+ iowrite32be(event & ~FPM_RAM_IRAM_ECC, &fpm_rg->fm_rcr); -+ -+ if ((mask & FPM_MURAM_ECC_ERR_EX_EN)) -+ return event; -+ else -+ return 0; -+} -+ -+uint32_t fman_get_iram_err_event(struct fman_fpm_regs *fpm_rg) -+{ -+ uint32_t event, mask; -+ -+ event = ioread32be(&fpm_rg->fm_rcr) ; -+ mask = ioread32be(&fpm_rg->fm_rie); -+ /* clear IRAM event bit (do not clear MURAM event) */ -+ iowrite32be(event & ~FPM_RAM_MURAM_ECC, -+ &fpm_rg->fm_rcr); -+ -+ if ((mask & FPM_IRAM_ECC_ERR_EX_EN)) -+ return event; -+ else -+ return 0; -+} -+ -+uint32_t fman_get_qmi_event(struct fman_qmi_regs *qmi_rg) -+{ -+ uint32_t event, mask, force; -+ -+ event = ioread32be(&qmi_rg->fmqm_ie); -+ mask = ioread32be(&qmi_rg->fmqm_ien); -+ event &= mask; -+ /* clear the forced events */ -+ force = ioread32be(&qmi_rg->fmqm_if); -+ if (force & event) -+ iowrite32be(force & ~event, &qmi_rg->fmqm_if); -+ /* clear the acknowledged events */ -+ iowrite32be(event, &qmi_rg->fmqm_ie); -+ return event; -+} -+ -+void fman_enable_time_stamp(struct fman_fpm_regs *fpm_rg, -+ uint8_t count1ubit, -+ uint16_t fm_clk_freq) -+{ -+ uint32_t tmp; -+ uint64_t frac; -+ uint32_t intgr; -+ uint32_t ts_freq = (uint32_t)(1 << count1ubit); /* in Mhz */ -+ -+ /* configure timestamp so that bit 8 will count 1 microsecond -+ * Find effective count rate at TIMESTAMP least significant bits: -+ * Effective_Count_Rate = 1MHz x 2^8 = 256MHz -+ * Find frequency ratio between effective count rate and the clock: -+ * Effective_Count_Rate / CLK e.g. for 600 MHz clock: -+ * 256/600 = 0.4266666... */ -+ -+ intgr = ts_freq / fm_clk_freq; -+ /* we multiply by 2^16 to keep the fraction of the division -+ * we do not div back, since we write this value as a fraction -+ * see spec */ -+ -+ frac = (((uint64_t)ts_freq << 16) - ((uint64_t)intgr << 16) * fm_clk_freq) -+ / fm_clk_freq; -+ /* we check remainder of the division in order to round up if not int */ -+ if (((ts_freq << 16) - (intgr << 16)*fm_clk_freq) % fm_clk_freq) -+ frac++; -+ -+ tmp = (intgr << FPM_TS_INT_SHIFT) | (uint16_t)frac; -+ iowrite32be(tmp, &fpm_rg->fmfp_tsc2); -+ -+ /* enable timestamp with original clock */ -+ iowrite32be(FPM_TS_CTL_EN, &fpm_rg->fmfp_tsc1); -+} -+ -+uint32_t fman_get_fpm_error_interrupts(struct fman_fpm_regs *fpm_rg) -+{ -+ return ioread32be(&fpm_rg->fm_epi); -+} -+ -+ -+int fman_set_erratum_10gmac_a004_wa(struct fman_fpm_regs *fpm_rg) -+{ -+ int timeout = 100; -+ -+ iowrite32be(0x40000000, &fpm_rg->fmfp_extc); -+ -+ while ((ioread32be(&fpm_rg->fmfp_extc) & 0x40000000) && --timeout) -+ udelay(10); -+ -+ if (!timeout) -+ return -EBUSY; -+ return 0; -+} -+ -+void fman_set_ctrl_intr(struct fman_fpm_regs *fpm_rg, -+ uint8_t event_reg_id, -+ uint32_t enable_events) -+{ -+ iowrite32be(enable_events, &fpm_rg->fmfp_cee[event_reg_id]); -+} -+ -+uint32_t fman_get_ctrl_intr(struct fman_fpm_regs *fpm_rg, uint8_t event_reg_id) -+{ -+ return ioread32be(&fpm_rg->fmfp_cee[event_reg_id]); -+} -+ -+void fman_set_num_of_riscs_per_port(struct fman_fpm_regs *fpm_rg, -+ uint8_t port_id, -+ uint8_t num_fman_ctrls, -+ uint32_t or_fman_ctrl) -+{ -+ uint32_t tmp = 0; -+ -+ tmp = (uint32_t)(port_id << FPM_PORT_FM_CTL_PORTID_SHIFT); -+ /*TODO - maybe to put CTL# according to another criteria*/ -+ if (num_fman_ctrls == 2) -+ tmp = FPM_PRT_FM_CTL2 | FPM_PRT_FM_CTL1; -+ /* order restoration */ -+ tmp |= (or_fman_ctrl << FPM_PRC_ORA_FM_CTL_SEL_SHIFT) | or_fman_ctrl; -+ -+ iowrite32be(tmp, &fpm_rg->fmfp_prc); -+} -+ -+void fman_set_order_restoration_per_port(struct fman_fpm_regs *fpm_rg, -+ uint8_t port_id, -+ bool independent_mode, -+ bool is_rx_port) -+{ -+ uint32_t tmp = 0; -+ -+ tmp = (uint32_t)(port_id << FPM_PORT_FM_CTL_PORTID_SHIFT); -+ if (independent_mode) { -+ if (is_rx_port) -+ tmp |= (FPM_PRT_FM_CTL1 << -+ FPM_PRC_ORA_FM_CTL_SEL_SHIFT) | FPM_PRT_FM_CTL1; -+ else -+ tmp |= (FPM_PRT_FM_CTL2 << -+ FPM_PRC_ORA_FM_CTL_SEL_SHIFT) | FPM_PRT_FM_CTL2; -+ } else { -+ tmp |= (FPM_PRT_FM_CTL2|FPM_PRT_FM_CTL1); -+ -+ /* order restoration */ -+ if (port_id % 2) -+ tmp |= (FPM_PRT_FM_CTL1 << -+ FPM_PRC_ORA_FM_CTL_SEL_SHIFT); -+ else -+ tmp |= (FPM_PRT_FM_CTL2 << -+ FPM_PRC_ORA_FM_CTL_SEL_SHIFT); -+ } -+ iowrite32be(tmp, &fpm_rg->fmfp_prc); -+} -+ -+uint8_t fman_get_qmi_deq_th(struct fman_qmi_regs *qmi_rg) -+{ -+ return (uint8_t)ioread32be(&qmi_rg->fmqm_gc); -+} -+ -+uint8_t fman_get_qmi_enq_th(struct fman_qmi_regs *qmi_rg) -+{ -+ return (uint8_t)(ioread32be(&qmi_rg->fmqm_gc) >> 8); -+} -+ -+void fman_set_qmi_enq_th(struct fman_qmi_regs *qmi_rg, uint8_t val) -+{ -+ uint32_t tmp_reg; -+ -+ tmp_reg = ioread32be(&qmi_rg->fmqm_gc); -+ tmp_reg &= ~QMI_CFG_ENQ_MASK; -+ tmp_reg |= ((uint32_t)val << 8); -+ iowrite32be(tmp_reg, &qmi_rg->fmqm_gc); -+} -+ -+void fman_set_qmi_deq_th(struct fman_qmi_regs *qmi_rg, uint8_t val) -+{ -+ uint32_t tmp_reg; -+ -+ tmp_reg = ioread32be(&qmi_rg->fmqm_gc); -+ tmp_reg &= ~QMI_CFG_DEQ_MASK; -+ tmp_reg |= (uint32_t)val; -+ iowrite32be(tmp_reg, &qmi_rg->fmqm_gc); -+} -+ -+void fman_qmi_disable_dispatch_limit(struct fman_fpm_regs *fpm_rg) -+{ -+ iowrite32be(0, &fpm_rg->fmfp_mxd); -+} -+ -+void fman_set_liodn_per_port(struct fman_rg *fman_rg, uint8_t port_id, -+ uint16_t liodn_base, -+ uint16_t liodn_ofst) -+{ -+ uint32_t tmp; -+ -+ if ((port_id > 63) || (port_id < 1)) -+ return; -+ -+ /* set LIODN base for this port */ -+ tmp = ioread32be(&fman_rg->dma_rg->fmdmplr[port_id / 2]); -+ if (port_id % 2) { -+ tmp &= ~FM_LIODN_BASE_MASK; -+ tmp |= (uint32_t)liodn_base; -+ } else { -+ tmp &= ~(FM_LIODN_BASE_MASK << DMA_LIODN_SHIFT); -+ tmp |= (uint32_t)liodn_base << DMA_LIODN_SHIFT; -+ } -+ iowrite32be(tmp, &fman_rg->dma_rg->fmdmplr[port_id / 2]); -+ iowrite32be((uint32_t)liodn_ofst, -+ &fman_rg->bmi_rg->fmbm_spliodn[port_id - 1]); -+} -+ -+bool fman_is_port_stalled(struct fman_fpm_regs *fpm_rg, uint8_t port_id) -+{ -+ return (bool)!!(ioread32be(&fpm_rg->fmfp_ps[port_id]) & FPM_PS_STALLED); -+} -+ -+void fman_resume_stalled_port(struct fman_fpm_regs *fpm_rg, uint8_t port_id) -+{ -+ uint32_t tmp; -+ -+ tmp = (uint32_t)((port_id << FPM_PORT_FM_CTL_PORTID_SHIFT) | -+ FPM_PRC_REALSE_STALLED); -+ iowrite32be(tmp, &fpm_rg->fmfp_prc); -+} -+ -+int fman_reset_mac(struct fman_fpm_regs *fpm_rg, uint8_t mac_id, bool is_10g) -+{ -+ uint32_t msk, timeout = 100; -+ -+ /* Get the relevant bit mask */ -+ if (is_10g) { -+ switch (mac_id) { -+ case(0): -+ msk = FPM_RSTC_10G0_RESET; -+ break; -+ case(1): -+ msk = FPM_RSTC_10G1_RESET; -+ break; -+ default: -+ return -EINVAL; -+ } -+ } else { -+ switch (mac_id) { -+ case(0): -+ msk = FPM_RSTC_1G0_RESET; -+ break; -+ case(1): -+ msk = FPM_RSTC_1G1_RESET; -+ break; -+ case(2): -+ msk = FPM_RSTC_1G2_RESET; -+ break; -+ case(3): -+ msk = FPM_RSTC_1G3_RESET; -+ break; -+ case(4): -+ msk = FPM_RSTC_1G4_RESET; -+ break; -+ case (5): -+ msk = FPM_RSTC_1G5_RESET; -+ break; -+ case (6): -+ msk = FPM_RSTC_1G6_RESET; -+ break; -+ case (7): -+ msk = FPM_RSTC_1G7_RESET; -+ break; -+ default: -+ return -EINVAL; -+ } -+ } -+ /* reset */ -+ iowrite32be(msk, &fpm_rg->fm_rstc); -+ while ((ioread32be(&fpm_rg->fm_rstc) & msk) && --timeout) -+ udelay(10); -+ -+ if (!timeout) -+ return -EBUSY; -+ return 0; -+} -+ -+uint16_t fman_get_size_of_fifo(struct fman_bmi_regs *bmi_rg, uint8_t port_id) -+{ -+ uint32_t tmp_reg; -+ -+ if ((port_id > 63) || (port_id < 1)) -+ return 0; -+ -+ tmp_reg = ioread32be(&bmi_rg->fmbm_pfs[port_id - 1]); -+ return (uint16_t)((tmp_reg & BMI_FIFO_SIZE_MASK) + 1); -+} -+ -+uint32_t fman_get_total_fifo_size(struct fman_bmi_regs *bmi_rg) -+{ -+ uint32_t reg, res; -+ -+ reg = ioread32be(&bmi_rg->fmbm_cfg1); -+ res = (reg >> BMI_CFG1_FIFO_SIZE_SHIFT) & 0x3ff; -+ return res * FMAN_BMI_FIFO_UNITS; -+} -+ -+uint16_t fman_get_size_of_extra_fifo(struct fman_bmi_regs *bmi_rg, -+ uint8_t port_id) -+{ -+ uint32_t tmp_reg; -+ -+ if ((port_id > 63) || (port_id < 1)) -+ return 0; -+ -+ tmp_reg = ioread32be(&bmi_rg->fmbm_pfs[port_id-1]); -+ return (uint16_t)((tmp_reg & BMI_EXTRA_FIFO_SIZE_MASK) >> -+ BMI_EXTRA_FIFO_SIZE_SHIFT); -+} -+ -+void fman_set_size_of_fifo(struct fman_bmi_regs *bmi_rg, -+ uint8_t port_id, -+ uint32_t sz_fifo, -+ uint32_t extra_sz_fifo) -+{ -+ uint32_t tmp; -+ -+ if ((port_id > 63) || (port_id < 1)) -+ return; -+ -+ /* calculate reg */ -+ tmp = (uint32_t)((sz_fifo / FMAN_BMI_FIFO_UNITS - 1) | -+ ((extra_sz_fifo / FMAN_BMI_FIFO_UNITS) << -+ BMI_EXTRA_FIFO_SIZE_SHIFT)); -+ iowrite32be(tmp, &bmi_rg->fmbm_pfs[port_id - 1]); -+} -+ -+uint8_t fman_get_num_of_tasks(struct fman_bmi_regs *bmi_rg, uint8_t port_id) -+{ -+ uint32_t tmp; -+ -+ if ((port_id > 63) || (port_id < 1)) -+ return 0; -+ -+ tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); -+ return (uint8_t)(((tmp & BMI_NUM_OF_TASKS_MASK) >> -+ BMI_NUM_OF_TASKS_SHIFT) + 1); -+} -+ -+uint8_t fman_get_num_extra_tasks(struct fman_bmi_regs *bmi_rg, uint8_t port_id) -+{ -+ uint32_t tmp; -+ -+ if ((port_id > 63) || (port_id < 1)) -+ return 0; -+ -+ tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); -+ return (uint8_t)((tmp & BMI_NUM_OF_EXTRA_TASKS_MASK) >> -+ BMI_EXTRA_NUM_OF_TASKS_SHIFT); -+} -+ -+void fman_set_num_of_tasks(struct fman_bmi_regs *bmi_rg, -+ uint8_t port_id, -+ uint8_t num_tasks, -+ uint8_t num_extra_tasks) -+{ -+ uint32_t tmp; -+ -+ if ((port_id > 63) || (port_id < 1)) -+ return; -+ -+ /* calculate reg */ -+ tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) & -+ ~(BMI_NUM_OF_TASKS_MASK | BMI_NUM_OF_EXTRA_TASKS_MASK); -+ tmp |= (uint32_t)(((num_tasks - 1) << BMI_NUM_OF_TASKS_SHIFT) | -+ (num_extra_tasks << BMI_EXTRA_NUM_OF_TASKS_SHIFT)); -+ iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]); -+} -+ -+uint8_t fman_get_num_of_dmas(struct fman_bmi_regs *bmi_rg, uint8_t port_id) -+{ -+ uint32_t tmp; -+ -+ if ((port_id > 63) || (port_id < 1)) -+ return 0; -+ -+ tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); -+ return (uint8_t)(((tmp & BMI_NUM_OF_DMAS_MASK) >> -+ BMI_NUM_OF_DMAS_SHIFT) + 1); -+} -+ -+uint8_t fman_get_num_extra_dmas(struct fman_bmi_regs *bmi_rg, uint8_t port_id) -+{ -+ uint32_t tmp; -+ -+ if ((port_id > 63) || (port_id < 1)) -+ return 0; -+ -+ tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); -+ return (uint8_t)((tmp & BMI_NUM_OF_EXTRA_DMAS_MASK) >> -+ BMI_EXTRA_NUM_OF_DMAS_SHIFT); -+} -+ -+void fman_set_num_of_open_dmas(struct fman_bmi_regs *bmi_rg, -+ uint8_t port_id, -+ uint8_t num_open_dmas, -+ uint8_t num_extra_open_dmas, -+ uint8_t total_num_dmas) -+{ -+ uint32_t tmp = 0; -+ -+ if ((port_id > 63) || (port_id < 1)) -+ return; -+ -+ /* calculate reg */ -+ tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) & -+ ~(BMI_NUM_OF_DMAS_MASK | BMI_NUM_OF_EXTRA_DMAS_MASK); -+ tmp |= (uint32_t)(((num_open_dmas-1) << BMI_NUM_OF_DMAS_SHIFT) | -+ (num_extra_open_dmas << BMI_EXTRA_NUM_OF_DMAS_SHIFT)); -+ iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]); -+ -+ /* update total num of DMA's with committed number of open DMAS, -+ * and max uncommitted pool. */ -+ if (total_num_dmas) -+ { -+ tmp = ioread32be(&bmi_rg->fmbm_cfg2) & ~BMI_CFG2_DMAS_MASK; -+ tmp |= (uint32_t)(total_num_dmas - 1) << BMI_CFG2_DMAS_SHIFT; -+ iowrite32be(tmp, &bmi_rg->fmbm_cfg2); -+ } -+} -+ -+void fman_set_vsp_window(struct fman_bmi_regs *bmi_rg, -+ uint8_t port_id, -+ uint8_t base_storage_profile, -+ uint8_t log2_num_of_profiles) -+{ -+ uint32_t tmp = 0; -+ if ((port_id > 63) || (port_id < 1)) -+ return; -+ -+ tmp = ioread32be(&bmi_rg->fmbm_spliodn[port_id-1]); -+ tmp |= (uint32_t)((uint32_t)base_storage_profile & 0x3f) << 16; -+ tmp |= (uint32_t)log2_num_of_profiles << 28; -+ iowrite32be(tmp, &bmi_rg->fmbm_spliodn[port_id-1]); -+} -+ -+void fman_set_congestion_group_pfc_priority(uint32_t *cpg_rg, -+ uint32_t congestion_group_id, -+ uint8_t priority_bit_map, -+ uint32_t reg_num) -+{ -+ uint32_t offset, tmp = 0; -+ -+ offset = (congestion_group_id%4)*8; -+ -+ tmp = ioread32be(&cpg_rg[reg_num]); -+ tmp &= ~(0xFF<catastrophic_err = DEFAULT_CATASTROPHIC_ERR; -+ cfg->dma_err = DEFAULT_DMA_ERR; -+ cfg->halt_on_external_activ = DEFAULT_HALT_ON_EXTERNAL_ACTIVATION; -+ cfg->halt_on_unrecov_ecc_err = DEFAULT_HALT_ON_UNRECOVERABLE_ECC_ERROR; -+ cfg->en_iram_test_mode = FALSE; -+ cfg->en_muram_test_mode = FALSE; -+ cfg->external_ecc_rams_enable = DEFAULT_EXTERNAL_ECC_RAMS_ENABLE; -+ -+ if (!is_master) -+ return; -+ -+ cfg->dma_aid_override = DEFAULT_AID_OVERRIDE; -+ cfg->dma_aid_mode = DEFAULT_AID_MODE; -+ cfg->dma_comm_qtsh_clr_emer = DEFAULT_DMA_COMM_Q_LOW; -+ cfg->dma_comm_qtsh_asrt_emer = DEFAULT_DMA_COMM_Q_HIGH; -+ cfg->dma_cache_override = DEFAULT_CACHE_OVERRIDE; -+ cfg->dma_cam_num_of_entries = DEFAULT_DMA_CAM_NUM_OF_ENTRIES; -+ cfg->dma_dbg_cnt_mode = DEFAULT_DMA_DBG_CNT_MODE; -+ cfg->dma_en_emergency = DEFAULT_DMA_EN_EMERGENCY; -+ cfg->dma_sos_emergency = DEFAULT_DMA_SOS_EMERGENCY; -+ cfg->dma_watchdog = DEFAULT_DMA_WATCHDOG; -+ cfg->dma_en_emergency_smoother = DEFAULT_DMA_EN_EMERGENCY_SMOOTHER; -+ cfg->dma_emergency_switch_counter = DEFAULT_DMA_EMERGENCY_SWITCH_COUNTER; -+ cfg->disp_limit_tsh = DEFAULT_DISP_LIMIT; -+ cfg->prs_disp_tsh = DEFAULT_PRS_DISP_TH; -+ cfg->plcr_disp_tsh = DEFAULT_PLCR_DISP_TH; -+ cfg->kg_disp_tsh = DEFAULT_KG_DISP_TH; -+ cfg->bmi_disp_tsh = DEFAULT_BMI_DISP_TH; -+ cfg->qmi_enq_disp_tsh = DEFAULT_QMI_ENQ_DISP_TH; -+ cfg->qmi_deq_disp_tsh = DEFAULT_QMI_DEQ_DISP_TH; -+ cfg->fm_ctl1_disp_tsh = DEFAULT_FM_CTL1_DISP_TH; -+ cfg->fm_ctl2_disp_tsh = DEFAULT_FM_CTL2_DISP_TH; -+ -+ cfg->pedantic_dma = FALSE; -+ cfg->tnum_aging_period = DEFAULT_TNUM_AGING_PERIOD; -+ cfg->dma_stop_on_bus_error = FALSE; -+ cfg->qmi_deq_option_support = FALSE; -+} -+ -+void fman_regconfig(struct fman_rg *fman_rg, struct fman_cfg *cfg) -+{ -+ uint32_t tmp_reg; -+ -+ /* read the values from the registers as they are initialized by the HW with -+ * the required values. -+ */ -+ tmp_reg = ioread32be(&fman_rg->bmi_rg->fmbm_cfg1); -+ cfg->total_fifo_size = -+ (((tmp_reg & BMI_TOTAL_FIFO_SIZE_MASK) >> BMI_CFG1_FIFO_SIZE_SHIFT) + 1) * FMAN_BMI_FIFO_UNITS; -+ -+ tmp_reg = ioread32be(&fman_rg->bmi_rg->fmbm_cfg2); -+ cfg->total_num_of_tasks = -+ (uint8_t)(((tmp_reg & BMI_TOTAL_NUM_OF_TASKS_MASK) >> BMI_CFG2_TASKS_SHIFT) + 1); -+ -+ tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmtr); -+ cfg->dma_comm_qtsh_asrt_emer = (uint8_t)(tmp_reg >> DMA_THRESH_COMMQ_SHIFT); -+ -+ tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmhy); -+ cfg->dma_comm_qtsh_clr_emer = (uint8_t)(tmp_reg >> DMA_THRESH_COMMQ_SHIFT); -+ -+ tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmmr); -+ cfg->dma_cache_override = (enum fman_dma_cache_override)((tmp_reg & DMA_MODE_CACHE_OR_MASK) >> DMA_MODE_CACHE_OR_SHIFT); -+ cfg->dma_cam_num_of_entries = (uint8_t)((((tmp_reg & DMA_MODE_CEN_MASK) >> DMA_MODE_CEN_SHIFT) +1)*DMA_CAM_UNITS); -+ cfg->dma_aid_override = (bool)((tmp_reg & DMA_MODE_AID_OR)? TRUE:FALSE); -+ cfg->dma_dbg_cnt_mode = (enum fman_dma_dbg_cnt_mode)((tmp_reg & DMA_MODE_DBG_MASK) >> DMA_MODE_DBG_SHIFT); -+ cfg->dma_en_emergency = (bool)((tmp_reg & DMA_MODE_EB)? TRUE : FALSE); -+ -+ tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_mxd); -+ cfg->disp_limit_tsh = (uint8_t)((tmp_reg & FPM_DISP_LIMIT_MASK) >> FPM_DISP_LIMIT_SHIFT); -+ -+ tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_dist1); -+ cfg->prs_disp_tsh = (uint8_t)((tmp_reg & FPM_THR1_PRS_MASK ) >> FPM_THR1_PRS_SHIFT); -+ cfg->plcr_disp_tsh = (uint8_t)((tmp_reg & FPM_THR1_KG_MASK ) >> FPM_THR1_KG_SHIFT); -+ cfg->kg_disp_tsh = (uint8_t)((tmp_reg & FPM_THR1_PLCR_MASK ) >> FPM_THR1_PLCR_SHIFT); -+ cfg->bmi_disp_tsh = (uint8_t)((tmp_reg & FPM_THR1_BMI_MASK ) >> FPM_THR1_BMI_SHIFT); -+ -+ tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_dist2); -+ cfg->qmi_enq_disp_tsh = (uint8_t)((tmp_reg & FPM_THR2_QMI_ENQ_MASK ) >> FPM_THR2_QMI_ENQ_SHIFT); -+ cfg->qmi_deq_disp_tsh = (uint8_t)((tmp_reg & FPM_THR2_QMI_DEQ_MASK ) >> FPM_THR2_QMI_DEQ_SHIFT); -+ cfg->fm_ctl1_disp_tsh = (uint8_t)((tmp_reg & FPM_THR2_FM_CTL1_MASK ) >> FPM_THR2_FM_CTL1_SHIFT); -+ cfg->fm_ctl2_disp_tsh = (uint8_t)((tmp_reg & FPM_THR2_FM_CTL2_MASK ) >> FPM_THR2_FM_CTL2_SHIFT); -+ -+ tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmsetr); -+ cfg->dma_sos_emergency = tmp_reg; -+ -+ tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmwcr); -+ cfg->dma_watchdog = tmp_reg/cfg->clk_freq; -+ -+ tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmemsr); -+ cfg->dma_en_emergency_smoother = (bool)((tmp_reg & DMA_EMSR_EMSTR_MASK)? TRUE : FALSE); -+ cfg->dma_emergency_switch_counter = (tmp_reg & DMA_EMSR_EMSTR_MASK); -+} -+ -+void fman_reset(struct fman_fpm_regs *fpm_rg) -+{ -+ iowrite32be(FPM_RSTC_FM_RESET, &fpm_rg->fm_rstc); -+} -+ -+/**************************************************************************//** -+ @Function FM_Init -+ -+ @Description Initializes the FM module -+ -+ @Param[in] h_Fm - FM module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+int fman_dma_init(struct fman_dma_regs *dma_rg, struct fman_cfg *cfg) -+{ -+ uint32_t tmp_reg; -+ -+ /**********************/ -+ /* Init DMA Registers */ -+ /**********************/ -+ /* clear status reg events */ -+ /* oren - check!!! */ -+ tmp_reg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC | -+ DMA_STATUS_SYSTEM_WRITE_ECC | DMA_STATUS_FM_WRITE_ECC); -+ iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg, -+ &dma_rg->fmdmsr); -+ -+ /* configure mode register */ -+ tmp_reg = 0; -+ tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT; -+ if (cfg->dma_aid_override) -+ tmp_reg |= DMA_MODE_AID_OR; -+ if (cfg->exceptions & FMAN_EX_DMA_BUS_ERROR) -+ tmp_reg |= DMA_MODE_BER; -+ if ((cfg->exceptions & FMAN_EX_DMA_SYSTEM_WRITE_ECC) | -+ (cfg->exceptions & FMAN_EX_DMA_READ_ECC) | -+ (cfg->exceptions & FMAN_EX_DMA_FM_WRITE_ECC)) -+ tmp_reg |= DMA_MODE_ECC; -+ if (cfg->dma_stop_on_bus_error) -+ tmp_reg |= DMA_MODE_SBER; -+ if(cfg->dma_axi_dbg_num_of_beats) -+ tmp_reg |= (uint32_t)(DMA_MODE_AXI_DBG_MASK & -+ ((cfg->dma_axi_dbg_num_of_beats - 1) << DMA_MODE_AXI_DBG_SHIFT)); -+ -+ if (cfg->dma_en_emergency) { -+ tmp_reg |= cfg->dma_emergency_bus_select; -+ tmp_reg |= cfg->dma_emergency_level << DMA_MODE_EMER_LVL_SHIFT; -+ if (cfg->dma_en_emergency_smoother) -+ iowrite32be(cfg->dma_emergency_switch_counter, -+ &dma_rg->fmdmemsr); -+ } -+ tmp_reg |= ((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) << -+ DMA_MODE_CEN_SHIFT; -+ tmp_reg |= DMA_MODE_SECURE_PROT; -+ tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT; -+ tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT; -+ -+ if (cfg->pedantic_dma) -+ tmp_reg |= DMA_MODE_EMER_READ; -+ -+ iowrite32be(tmp_reg, &dma_rg->fmdmmr); -+ -+ /* configure thresholds register */ -+ tmp_reg = ((uint32_t)cfg->dma_comm_qtsh_asrt_emer << -+ DMA_THRESH_COMMQ_SHIFT) | -+ ((uint32_t)cfg->dma_read_buf_tsh_asrt_emer << -+ DMA_THRESH_READ_INT_BUF_SHIFT) | -+ ((uint32_t)cfg->dma_write_buf_tsh_asrt_emer); -+ -+ iowrite32be(tmp_reg, &dma_rg->fmdmtr); -+ -+ /* configure hysteresis register */ -+ tmp_reg = ((uint32_t)cfg->dma_comm_qtsh_clr_emer << -+ DMA_THRESH_COMMQ_SHIFT) | -+ ((uint32_t)cfg->dma_read_buf_tsh_clr_emer << -+ DMA_THRESH_READ_INT_BUF_SHIFT) | -+ ((uint32_t)cfg->dma_write_buf_tsh_clr_emer); -+ -+ iowrite32be(tmp_reg, &dma_rg->fmdmhy); -+ -+ /* configure emergency threshold */ -+ iowrite32be(cfg->dma_sos_emergency, &dma_rg->fmdmsetr); -+ -+ /* configure Watchdog */ -+ iowrite32be((cfg->dma_watchdog * cfg->clk_freq), -+ &dma_rg->fmdmwcr); -+ -+ iowrite32be(cfg->cam_base_addr, &dma_rg->fmdmebcr); -+ -+ return 0; -+} -+ -+int fman_fpm_init(struct fman_fpm_regs *fpm_rg, struct fman_cfg *cfg) -+{ -+ uint32_t tmp_reg; -+ int i; -+ -+ /**********************/ -+ /* Init FPM Registers */ -+ /**********************/ -+ tmp_reg = (uint32_t)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT); -+ iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd); -+ -+ tmp_reg = (((uint32_t)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) | -+ ((uint32_t)cfg->kg_disp_tsh << FPM_THR1_KG_SHIFT) | -+ ((uint32_t)cfg->plcr_disp_tsh << FPM_THR1_PLCR_SHIFT) | -+ ((uint32_t)cfg->bmi_disp_tsh << FPM_THR1_BMI_SHIFT)); -+ iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1); -+ -+ tmp_reg = (((uint32_t)cfg->qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) | -+ ((uint32_t)cfg->qmi_deq_disp_tsh << FPM_THR2_QMI_DEQ_SHIFT) | -+ ((uint32_t)cfg->fm_ctl1_disp_tsh << FPM_THR2_FM_CTL1_SHIFT) | -+ ((uint32_t)cfg->fm_ctl2_disp_tsh << FPM_THR2_FM_CTL2_SHIFT)); -+ iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2); -+ -+ /* define exceptions and error behavior */ -+ tmp_reg = 0; -+ /* Clear events */ -+ tmp_reg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC | -+ FPM_EV_MASK_SINGLE_ECC); -+ /* enable interrupts */ -+ if (cfg->exceptions & FMAN_EX_FPM_STALL_ON_TASKS) -+ tmp_reg |= FPM_EV_MASK_STALL_EN; -+ if (cfg->exceptions & FMAN_EX_FPM_SINGLE_ECC) -+ tmp_reg |= FPM_EV_MASK_SINGLE_ECC_EN; -+ if (cfg->exceptions & FMAN_EX_FPM_DOUBLE_ECC) -+ tmp_reg |= FPM_EV_MASK_DOUBLE_ECC_EN; -+ tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT); -+ tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT); -+ if (!cfg->halt_on_external_activ) -+ tmp_reg |= FPM_EV_MASK_EXTERNAL_HALT; -+ if (!cfg->halt_on_unrecov_ecc_err) -+ tmp_reg |= FPM_EV_MASK_ECC_ERR_HALT; -+ iowrite32be(tmp_reg, &fpm_rg->fmfp_ee); -+ -+ /* clear all fmCtls event registers */ -+ for (i = 0; i < cfg->num_of_fman_ctrl_evnt_regs; i++) -+ iowrite32be(0xFFFFFFFF, &fpm_rg->fmfp_cev[i]); -+ -+ /* RAM ECC - enable and clear events*/ -+ /* first we need to clear all parser memory, -+ * as it is uninitialized and may cause ECC errors */ -+ /* event bits */ -+ tmp_reg = (FPM_RAM_MURAM_ECC | FPM_RAM_IRAM_ECC); -+ /* Rams enable not effected by RCR bit, but by a COP configuration */ -+ if (cfg->external_ecc_rams_enable) -+ tmp_reg |= FPM_RAM_RAMS_ECC_EN_SRC_SEL; -+ -+ /* enable test mode */ -+ if (cfg->en_muram_test_mode) -+ tmp_reg |= FPM_RAM_MURAM_TEST_ECC; -+ if (cfg->en_iram_test_mode) -+ tmp_reg |= FPM_RAM_IRAM_TEST_ECC; -+ iowrite32be(tmp_reg, &fpm_rg->fm_rcr); -+ -+ tmp_reg = 0; -+ if (cfg->exceptions & FMAN_EX_IRAM_ECC) { -+ tmp_reg |= FPM_IRAM_ECC_ERR_EX_EN; -+ fman_enable_rams_ecc(fpm_rg); -+ } -+ if (cfg->exceptions & FMAN_EX_NURAM_ECC) { -+ tmp_reg |= FPM_MURAM_ECC_ERR_EX_EN; -+ fman_enable_rams_ecc(fpm_rg); -+ } -+ iowrite32be(tmp_reg, &fpm_rg->fm_rie); -+ -+ return 0; -+} -+ -+int fman_bmi_init(struct fman_bmi_regs *bmi_rg, struct fman_cfg *cfg) -+{ -+ uint32_t tmp_reg; -+ -+ /**********************/ -+ /* Init BMI Registers */ -+ /**********************/ -+ -+ /* define common resources */ -+ tmp_reg = cfg->fifo_base_addr; -+ tmp_reg = tmp_reg / BMI_FIFO_ALIGN; -+ -+ tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) << -+ BMI_CFG1_FIFO_SIZE_SHIFT); -+ iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1); -+ -+ tmp_reg = ((uint32_t)(cfg->total_num_of_tasks - 1) << -+ BMI_CFG2_TASKS_SHIFT); -+ /* num of DMA's will be dynamically updated when each port is set */ -+ iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2); -+ -+ /* define unmaskable exceptions, enable and clear events */ -+ tmp_reg = 0; -+ iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC | -+ BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC | -+ BMI_ERR_INTR_EN_STATISTICS_RAM_ECC | -+ BMI_ERR_INTR_EN_DISPATCH_RAM_ECC, -+ &bmi_rg->fmbm_ievr); -+ -+ if (cfg->exceptions & FMAN_EX_BMI_LIST_RAM_ECC) -+ tmp_reg |= BMI_ERR_INTR_EN_LIST_RAM_ECC; -+ if (cfg->exceptions & FMAN_EX_BMI_PIPELINE_ECC) -+ tmp_reg |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC; -+ if (cfg->exceptions & FMAN_EX_BMI_STATISTICS_RAM_ECC) -+ tmp_reg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC; -+ if (cfg->exceptions & FMAN_EX_BMI_DISPATCH_RAM_ECC) -+ tmp_reg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC; -+ iowrite32be(tmp_reg, &bmi_rg->fmbm_ier); -+ -+ return 0; -+} -+ -+int fman_qmi_init(struct fman_qmi_regs *qmi_rg, struct fman_cfg *cfg) -+{ -+ uint32_t tmp_reg; -+ uint16_t period_in_fm_clocks; -+ uint8_t remainder; -+ /**********************/ -+ /* Init QMI Registers */ -+ /**********************/ -+ /* Clear error interrupt events */ -+ -+ iowrite32be(QMI_ERR_INTR_EN_DOUBLE_ECC | QMI_ERR_INTR_EN_DEQ_FROM_DEF, -+ &qmi_rg->fmqm_eie); -+ tmp_reg = 0; -+ if (cfg->exceptions & FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID) -+ tmp_reg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF; -+ if (cfg->exceptions & FMAN_EX_QMI_DOUBLE_ECC) -+ tmp_reg |= QMI_ERR_INTR_EN_DOUBLE_ECC; -+ /* enable events */ -+ iowrite32be(tmp_reg, &qmi_rg->fmqm_eien); -+ -+ if (cfg->tnum_aging_period) { -+ /* tnum_aging_period is in units of usec, p_FmClockFreq in Mhz */ -+ period_in_fm_clocks = (uint16_t) -+ (cfg->tnum_aging_period * cfg->clk_freq); -+ /* period_in_fm_clocks must be a 64 multiply */ -+ remainder = (uint8_t)(period_in_fm_clocks % 64); -+ if (remainder) -+ tmp_reg = (uint32_t)((period_in_fm_clocks / 64) + 1); -+ else{ -+ tmp_reg = (uint32_t)(period_in_fm_clocks / 64); -+ if (!tmp_reg) -+ tmp_reg = 1; -+ } -+ tmp_reg <<= QMI_TAPC_TAP; -+ iowrite32be(tmp_reg, &qmi_rg->fmqm_tapc); -+ } -+ tmp_reg = 0; -+ /* Clear interrupt events */ -+ iowrite32be(QMI_INTR_EN_SINGLE_ECC, &qmi_rg->fmqm_ie); -+ if (cfg->exceptions & FMAN_EX_QMI_SINGLE_ECC) -+ tmp_reg |= QMI_INTR_EN_SINGLE_ECC; -+ /* enable events */ -+ iowrite32be(tmp_reg, &qmi_rg->fmqm_ien); -+ -+ return 0; -+} -+ -+int fman_enable(struct fman_rg *fman_rg, struct fman_cfg *cfg) -+{ -+ uint32_t cfg_reg = 0; -+ -+ /**********************/ -+ /* Enable all modules */ -+ /**********************/ -+ /* clear & enable global counters - calculate reg and save for later, -+ because it's the same reg for QMI enable */ -+ cfg_reg = QMI_CFG_EN_COUNTERS; -+ if (cfg->qmi_deq_option_support) -+ cfg_reg |= (uint32_t)(((cfg->qmi_def_tnums_thresh) << 8) | -+ (uint32_t)cfg->qmi_def_tnums_thresh); -+ -+ iowrite32be(BMI_INIT_START, &fman_rg->bmi_rg->fmbm_init); -+ iowrite32be(cfg_reg | QMI_CFG_ENQ_EN | QMI_CFG_DEQ_EN, -+ &fman_rg->qmi_rg->fmqm_gc); -+ -+ return 0; -+} -+ -+void fman_free_resources(struct fman_rg *fman_rg) -+{ -+ /* disable BMI and QMI */ -+ iowrite32be(0, &fman_rg->bmi_rg->fmbm_init); -+ iowrite32be(0, &fman_rg->qmi_rg->fmqm_gc); -+ -+ /* release BMI resources */ -+ iowrite32be(0, &fman_rg->bmi_rg->fmbm_cfg2); -+ iowrite32be(0, &fman_rg->bmi_rg->fmbm_cfg1); -+ -+ /* disable ECC */ -+ iowrite32be(0, &fman_rg->fpm_rg->fm_rcr); -+} -+ -+/****************************************************/ -+/* API Run-time Control uint functions */ -+/****************************************************/ -+uint32_t fman_get_normal_pending(struct fman_fpm_regs *fpm_rg) -+{ -+ return ioread32be(&fpm_rg->fm_npi); -+} -+ -+uint32_t fman_get_controller_event(struct fman_fpm_regs *fpm_rg, uint8_t reg_id) -+{ -+ uint32_t event; -+ -+ event = ioread32be(&fpm_rg->fmfp_fcev[reg_id]) & -+ ioread32be(&fpm_rg->fmfp_cee[reg_id]); -+ iowrite32be(event, &fpm_rg->fmfp_cev[reg_id]); -+ -+ return event; -+} -+ -+uint32_t fman_get_error_pending(struct fman_fpm_regs *fpm_rg) -+{ -+ return ioread32be(&fpm_rg->fm_epi); -+} -+ -+void fman_set_ports_bandwidth(struct fman_bmi_regs *bmi_rg, uint8_t *weights) -+{ -+ int i; -+ uint8_t shift; -+ uint32_t tmp = 0; -+ -+ for (i = 0; i < 64; i++) { -+ if (weights[i] > 1) { /* no need to write 1 since it is 0 */ -+ /* Add this port to tmp_reg */ -+ /* (each 8 ports result in one register)*/ -+ shift = (uint8_t)(32 - 4 * ((i % 8) + 1)); -+ tmp |= ((weights[i] - 1) << shift); -+ } -+ if (i % 8 == 7) { /* last in this set */ -+ iowrite32be(tmp, &bmi_rg->fmbm_arb[i / 8]); -+ tmp = 0; -+ } -+ } -+} -+ -+void fman_enable_rams_ecc(struct fman_fpm_regs *fpm_rg) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(&fpm_rg->fm_rcr); -+ if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL) -+ iowrite32be(tmp | FPM_RAM_IRAM_ECC_EN, -+ &fpm_rg->fm_rcr); -+ else -+ iowrite32be(tmp | FPM_RAM_RAMS_ECC_EN | -+ FPM_RAM_IRAM_ECC_EN, -+ &fpm_rg->fm_rcr); -+} -+ -+void fman_disable_rams_ecc(struct fman_fpm_regs *fpm_rg) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(&fpm_rg->fm_rcr); -+ if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL) -+ iowrite32be(tmp & ~FPM_RAM_IRAM_ECC_EN, -+ &fpm_rg->fm_rcr); -+ else -+ iowrite32be(tmp & ~(FPM_RAM_RAMS_ECC_EN | FPM_RAM_IRAM_ECC_EN), -+ &fpm_rg->fm_rcr); -+} -+ -+int fman_set_exception(struct fman_rg *fman_rg, -+ enum fman_exceptions exception, -+ bool enable) -+{ -+ uint32_t tmp; -+ -+ switch (exception) { -+ case(E_FMAN_EX_DMA_BUS_ERROR): -+ tmp = ioread32be(&fman_rg->dma_rg->fmdmmr); -+ if (enable) -+ tmp |= DMA_MODE_BER; -+ else -+ tmp &= ~DMA_MODE_BER; -+ /* disable bus error */ -+ iowrite32be(tmp, &fman_rg->dma_rg->fmdmmr); -+ break; -+ case(E_FMAN_EX_DMA_READ_ECC): -+ case(E_FMAN_EX_DMA_SYSTEM_WRITE_ECC): -+ case(E_FMAN_EX_DMA_FM_WRITE_ECC): -+ tmp = ioread32be(&fman_rg->dma_rg->fmdmmr); -+ if (enable) -+ tmp |= DMA_MODE_ECC; -+ else -+ tmp &= ~DMA_MODE_ECC; -+ iowrite32be(tmp, &fman_rg->dma_rg->fmdmmr); -+ break; -+ case(E_FMAN_EX_FPM_STALL_ON_TASKS): -+ tmp = ioread32be(&fman_rg->fpm_rg->fmfp_ee); -+ if (enable) -+ tmp |= FPM_EV_MASK_STALL_EN; -+ else -+ tmp &= ~FPM_EV_MASK_STALL_EN; -+ iowrite32be(tmp, &fman_rg->fpm_rg->fmfp_ee); -+ break; -+ case(E_FMAN_EX_FPM_SINGLE_ECC): -+ tmp = ioread32be(&fman_rg->fpm_rg->fmfp_ee); -+ if (enable) -+ tmp |= FPM_EV_MASK_SINGLE_ECC_EN; -+ else -+ tmp &= ~FPM_EV_MASK_SINGLE_ECC_EN; -+ iowrite32be(tmp, &fman_rg->fpm_rg->fmfp_ee); -+ break; -+ case(E_FMAN_EX_FPM_DOUBLE_ECC): -+ tmp = ioread32be(&fman_rg->fpm_rg->fmfp_ee); -+ if (enable) -+ tmp |= FPM_EV_MASK_DOUBLE_ECC_EN; -+ else -+ tmp &= ~FPM_EV_MASK_DOUBLE_ECC_EN; -+ iowrite32be(tmp, &fman_rg->fpm_rg->fmfp_ee); -+ break; -+ case(E_FMAN_EX_QMI_SINGLE_ECC): -+ tmp = ioread32be(&fman_rg->qmi_rg->fmqm_ien); -+ if (enable) -+ tmp |= QMI_INTR_EN_SINGLE_ECC; -+ else -+ tmp &= ~QMI_INTR_EN_SINGLE_ECC; -+ iowrite32be(tmp, &fman_rg->qmi_rg->fmqm_ien); -+ break; -+ case(E_FMAN_EX_QMI_DOUBLE_ECC): -+ tmp = ioread32be(&fman_rg->qmi_rg->fmqm_eien); -+ if (enable) -+ tmp |= QMI_ERR_INTR_EN_DOUBLE_ECC; -+ else -+ tmp &= ~QMI_ERR_INTR_EN_DOUBLE_ECC; -+ iowrite32be(tmp, &fman_rg->qmi_rg->fmqm_eien); -+ break; -+ case(E_FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID): -+ tmp = ioread32be(&fman_rg->qmi_rg->fmqm_eien); -+ if (enable) -+ tmp |= QMI_ERR_INTR_EN_DEQ_FROM_DEF; -+ else -+ tmp &= ~QMI_ERR_INTR_EN_DEQ_FROM_DEF; -+ iowrite32be(tmp, &fman_rg->qmi_rg->fmqm_eien); -+ break; -+ case(E_FMAN_EX_BMI_LIST_RAM_ECC): -+ tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier); -+ if (enable) -+ tmp |= BMI_ERR_INTR_EN_LIST_RAM_ECC; -+ else -+ tmp &= ~BMI_ERR_INTR_EN_LIST_RAM_ECC; -+ iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier); -+ break; -+ case(E_FMAN_EX_BMI_STORAGE_PROFILE_ECC): -+ tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier); -+ if (enable) -+ tmp |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC; -+ else -+ tmp &= ~BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC; -+ iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier); -+ break; -+ case(E_FMAN_EX_BMI_STATISTICS_RAM_ECC): -+ tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier); -+ if (enable) -+ tmp |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC; -+ else -+ tmp &= ~BMI_ERR_INTR_EN_STATISTICS_RAM_ECC; -+ iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier); -+ break; -+ case(E_FMAN_EX_BMI_DISPATCH_RAM_ECC): -+ tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier); -+ if (enable) -+ tmp |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC; -+ else -+ tmp &= ~BMI_ERR_INTR_EN_DISPATCH_RAM_ECC; -+ iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier); -+ break; -+ case(E_FMAN_EX_IRAM_ECC): -+ tmp = ioread32be(&fman_rg->fpm_rg->fm_rie); -+ if (enable) { -+ /* enable ECC if not enabled */ -+ fman_enable_rams_ecc(fman_rg->fpm_rg); -+ /* enable ECC interrupts */ -+ tmp |= FPM_IRAM_ECC_ERR_EX_EN; -+ } else { -+ /* ECC mechanism may be disabled, -+ * depending on driver status */ -+ fman_disable_rams_ecc(fman_rg->fpm_rg); -+ tmp &= ~FPM_IRAM_ECC_ERR_EX_EN; -+ } -+ iowrite32be(tmp, &fman_rg->fpm_rg->fm_rie); -+ break; -+ case(E_FMAN_EX_MURAM_ECC): -+ tmp = ioread32be(&fman_rg->fpm_rg->fm_rie); -+ if (enable) { -+ /* enable ECC if not enabled */ -+ fman_enable_rams_ecc(fman_rg->fpm_rg); -+ /* enable ECC interrupts */ -+ tmp |= FPM_MURAM_ECC_ERR_EX_EN; -+ } else { -+ /* ECC mechanism may be disabled, -+ * depending on driver status */ -+ fman_disable_rams_ecc(fman_rg->fpm_rg); -+ tmp &= ~FPM_MURAM_ECC_ERR_EX_EN; -+ } -+ iowrite32be(tmp, &fman_rg->fpm_rg->fm_rie); -+ break; -+ default: -+ return -EINVAL; -+ } -+ return 0; -+} -+ -+void fman_get_revision(struct fman_fpm_regs *fpm_rg, -+ uint8_t *major, -+ uint8_t *minor) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(&fpm_rg->fm_ip_rev_1); -+ *major = (uint8_t)((tmp & FPM_REV1_MAJOR_MASK) >> FPM_REV1_MAJOR_SHIFT); -+ *minor = (uint8_t)((tmp & FPM_REV1_MINOR_MASK) >> FPM_REV1_MINOR_SHIFT); -+ -+} -+ -+uint32_t fman_get_counter(struct fman_rg *fman_rg, -+ enum fman_counters reg_name) -+{ -+ uint32_t ret_val; -+ -+ switch (reg_name) { -+ case(E_FMAN_COUNTERS_ENQ_TOTAL_FRAME): -+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_etfc); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_TOTAL_FRAME): -+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dtfc); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_0): -+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dc0); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_1): -+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dc1); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_2): -+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dc2); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_3): -+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dc3); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_FROM_DEFAULT): -+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dfdc); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_FROM_CONTEXT): -+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dfcc); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_FROM_FD): -+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dffc); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_CONFIRM): -+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dcc); -+ break; -+ default: -+ ret_val = 0; -+ } -+ return ret_val; -+} -+ -+int fman_modify_counter(struct fman_rg *fman_rg, -+ enum fman_counters reg_name, -+ uint32_t val) -+{ -+ /* When applicable (when there is an 'enable counters' bit, -+ * check that counters are enabled */ -+ switch (reg_name) { -+ case(E_FMAN_COUNTERS_ENQ_TOTAL_FRAME): -+ case(E_FMAN_COUNTERS_DEQ_TOTAL_FRAME): -+ case(E_FMAN_COUNTERS_DEQ_0): -+ case(E_FMAN_COUNTERS_DEQ_1): -+ case(E_FMAN_COUNTERS_DEQ_2): -+ case(E_FMAN_COUNTERS_DEQ_3): -+ case(E_FMAN_COUNTERS_DEQ_FROM_DEFAULT): -+ case(E_FMAN_COUNTERS_DEQ_FROM_CONTEXT): -+ case(E_FMAN_COUNTERS_DEQ_FROM_FD): -+ case(E_FMAN_COUNTERS_DEQ_CONFIRM): -+ if (!(ioread32be(&fman_rg->qmi_rg->fmqm_gc) & -+ QMI_CFG_EN_COUNTERS)) -+ return -EINVAL; -+ break; -+ default: -+ break; -+ } -+ /* Set counter */ -+ switch (reg_name) { -+ case(E_FMAN_COUNTERS_ENQ_TOTAL_FRAME): -+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_etfc); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_TOTAL_FRAME): -+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dtfc); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_0): -+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dc0); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_1): -+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dc1); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_2): -+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dc2); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_3): -+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dc3); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_FROM_DEFAULT): -+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dfdc); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_FROM_CONTEXT): -+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dfcc); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_FROM_FD): -+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dffc); -+ break; -+ case(E_FMAN_COUNTERS_DEQ_CONFIRM): -+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dcc); -+ break; -+ case(E_FMAN_COUNTERS_SEMAPHOR_ENTRY_FULL_REJECT): -+ iowrite32be(val, &fman_rg->dma_rg->fmdmsefrc); -+ break; -+ case(E_FMAN_COUNTERS_SEMAPHOR_QUEUE_FULL_REJECT): -+ iowrite32be(val, &fman_rg->dma_rg->fmdmsqfrc); -+ break; -+ case(E_FMAN_COUNTERS_SEMAPHOR_SYNC_REJECT): -+ iowrite32be(val, &fman_rg->dma_rg->fmdmssrc); -+ break; -+ default: -+ break; -+ } -+ return 0; -+} -+ -+void fman_set_dma_emergency(struct fman_dma_regs *dma_rg, -+ bool is_write, -+ bool enable) -+{ -+ uint32_t msk; -+ -+ msk = (uint32_t)(is_write ? DMA_MODE_EMER_WRITE : DMA_MODE_EMER_READ); -+ -+ if (enable) -+ iowrite32be(ioread32be(&dma_rg->fmdmmr) | msk, -+ &dma_rg->fmdmmr); -+ else /* disable */ -+ iowrite32be(ioread32be(&dma_rg->fmdmmr) & ~msk, -+ &dma_rg->fmdmmr); -+} -+ -+void fman_set_dma_ext_bus_pri(struct fman_dma_regs *dma_rg, uint32_t pri) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(&dma_rg->fmdmmr) | -+ (pri << DMA_MODE_BUS_PRI_SHIFT); -+ -+ iowrite32be(tmp, &dma_rg->fmdmmr); -+} -+ -+uint32_t fman_get_dma_status(struct fman_dma_regs *dma_rg) -+{ -+ return ioread32be(&dma_rg->fmdmsr); -+} -+ -+void fman_force_intr(struct fman_rg *fman_rg, -+ enum fman_exceptions exception) -+{ -+ switch (exception) { -+ case E_FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: -+ iowrite32be(QMI_ERR_INTR_EN_DEQ_FROM_DEF, -+ &fman_rg->qmi_rg->fmqm_eif); -+ break; -+ case E_FMAN_EX_QMI_SINGLE_ECC: -+ iowrite32be(QMI_INTR_EN_SINGLE_ECC, -+ &fman_rg->qmi_rg->fmqm_if); -+ break; -+ case E_FMAN_EX_QMI_DOUBLE_ECC: -+ iowrite32be(QMI_ERR_INTR_EN_DOUBLE_ECC, -+ &fman_rg->qmi_rg->fmqm_eif); -+ break; -+ case E_FMAN_EX_BMI_LIST_RAM_ECC: -+ iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC, -+ &fman_rg->bmi_rg->fmbm_ifr); -+ break; -+ case E_FMAN_EX_BMI_STORAGE_PROFILE_ECC: -+ iowrite32be(BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC, -+ &fman_rg->bmi_rg->fmbm_ifr); -+ break; -+ case E_FMAN_EX_BMI_STATISTICS_RAM_ECC: -+ iowrite32be(BMI_ERR_INTR_EN_STATISTICS_RAM_ECC, -+ &fman_rg->bmi_rg->fmbm_ifr); -+ break; -+ case E_FMAN_EX_BMI_DISPATCH_RAM_ECC: -+ iowrite32be(BMI_ERR_INTR_EN_DISPATCH_RAM_ECC, -+ &fman_rg->bmi_rg->fmbm_ifr); -+ break; -+ default: -+ break; -+ } -+} -+ -+bool fman_is_qmi_halt_not_busy_state(struct fman_qmi_regs *qmi_rg) -+{ -+ return (bool)!!(ioread32be(&qmi_rg->fmqm_gs) & QMI_GS_HALT_NOT_BUSY); -+} -+void fman_resume(struct fman_fpm_regs *fpm_rg) -+{ -+ uint32_t tmp; -+ -+ tmp = ioread32be(&fpm_rg->fmfp_ee); -+ /* clear tmp_reg event bits in order not to clear standing events */ -+ tmp &= ~(FPM_EV_MASK_DOUBLE_ECC | -+ FPM_EV_MASK_STALL | -+ FPM_EV_MASK_SINGLE_ECC); -+ tmp |= FPM_EV_MASK_RELEASE_FM; -+ -+ iowrite32be(tmp, &fpm_rg->fmfp_ee); -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc/fm_common.h -@@ -0,0 +1,1203 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_common.h -+ -+ @Description FM internal structures and definitions. -+*//***************************************************************************/ -+#ifndef __FM_COMMON_H -+#define __FM_COMMON_H -+ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "fm_pcd_ext.h" -+#include "fm_ext.h" -+#include "fm_port_ext.h" -+ -+ -+#define e_FM_PORT_TYPE_OH_HOST_COMMAND e_FM_PORT_TYPE_DUMMY -+ -+#define CLS_PLAN_NUM_PER_GRP 8 -+ -+#define IP_OFFLOAD_PACKAGE_NUMBER 106 -+#define CAPWAP_OFFLOAD_PACKAGE_NUMBER 108 -+#define IS_OFFLOAD_PACKAGE(num) ((num == IP_OFFLOAD_PACKAGE_NUMBER) || (num == CAPWAP_OFFLOAD_PACKAGE_NUMBER)) -+ -+ -+ -+/**************************************************************************//** -+ @Description Modules registers offsets -+*//***************************************************************************/ -+#define FM_MM_MURAM 0x00000000 -+#define FM_MM_BMI 0x00080000 -+#define FM_MM_QMI 0x00080400 -+#define FM_MM_PRS 0x000c7000 -+#define FM_MM_KG 0x000C1000 -+#define FM_MM_DMA 0x000C2000 -+#define FM_MM_FPM 0x000C3000 -+#define FM_MM_PLCR 0x000C0000 -+#define FM_MM_IMEM 0x000C4000 -+#define FM_MM_CGP 0x000DB000 -+#define FM_MM_TRB(i) (0x000D0200 + 0x400 * (i)) -+#if (DPAA_VERSION >= 11) -+#define FM_MM_SP 0x000dc000 -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ -+/**************************************************************************//** -+ @Description Enum for inter-module interrupts registration -+*//***************************************************************************/ -+typedef enum e_FmEventModules{ -+ e_FM_MOD_PRS, /**< Parser event */ -+ e_FM_MOD_KG, /**< Keygen event */ -+ e_FM_MOD_PLCR, /**< Policer event */ -+ e_FM_MOD_10G_MAC, /**< 10G MAC event */ -+ e_FM_MOD_1G_MAC, /**< 1G MAC event */ -+ e_FM_MOD_TMR, /**< Timer event */ -+ e_FM_MOD_FMAN_CTRL, /**< FMAN Controller Timer event */ -+ e_FM_MOD_MACSEC, -+ e_FM_MOD_DUMMY_LAST -+} e_FmEventModules; -+ -+/**************************************************************************//** -+ @Description Enum for interrupts types -+*//***************************************************************************/ -+typedef enum e_FmIntrType { -+ e_FM_INTR_TYPE_ERR, -+ e_FM_INTR_TYPE_NORMAL -+} e_FmIntrType; -+ -+/**************************************************************************//** -+ @Description Enum for inter-module interrupts registration -+*//***************************************************************************/ -+typedef enum e_FmInterModuleEvent -+{ -+ e_FM_EV_PRS = 0, /**< Parser event */ -+ e_FM_EV_ERR_PRS, /**< Parser error event */ -+ e_FM_EV_KG, /**< Keygen event */ -+ e_FM_EV_ERR_KG, /**< Keygen error event */ -+ e_FM_EV_PLCR, /**< Policer event */ -+ e_FM_EV_ERR_PLCR, /**< Policer error event */ -+ e_FM_EV_ERR_10G_MAC0, /**< 10G MAC 0 error event */ -+ e_FM_EV_ERR_10G_MAC1, /**< 10G MAC 1 error event */ -+ e_FM_EV_ERR_1G_MAC0, /**< 1G MAC 0 error event */ -+ e_FM_EV_ERR_1G_MAC1, /**< 1G MAC 1 error event */ -+ e_FM_EV_ERR_1G_MAC2, /**< 1G MAC 2 error event */ -+ e_FM_EV_ERR_1G_MAC3, /**< 1G MAC 3 error event */ -+ e_FM_EV_ERR_1G_MAC4, /**< 1G MAC 4 error event */ -+ e_FM_EV_ERR_1G_MAC5, /**< 1G MAC 5 error event */ -+ e_FM_EV_ERR_1G_MAC6, /**< 1G MAC 6 error event */ -+ e_FM_EV_ERR_1G_MAC7, /**< 1G MAC 7 error event */ -+ e_FM_EV_ERR_MACSEC_MAC0, -+ e_FM_EV_TMR, /**< Timer event */ -+ e_FM_EV_10G_MAC0, /**< 10G MAC 0 event (Magic packet detection)*/ -+ e_FM_EV_10G_MAC1, /**< 10G MAC 1 event (Magic packet detection)*/ -+ e_FM_EV_1G_MAC0, /**< 1G MAC 0 event (Magic packet detection)*/ -+ e_FM_EV_1G_MAC1, /**< 1G MAC 1 event (Magic packet detection)*/ -+ e_FM_EV_1G_MAC2, /**< 1G MAC 2 (Magic packet detection)*/ -+ e_FM_EV_1G_MAC3, /**< 1G MAC 3 (Magic packet detection)*/ -+ e_FM_EV_1G_MAC4, /**< 1G MAC 4 (Magic packet detection)*/ -+ e_FM_EV_1G_MAC5, /**< 1G MAC 5 (Magic packet detection)*/ -+ e_FM_EV_1G_MAC6, /**< 1G MAC 6 (Magic packet detection)*/ -+ e_FM_EV_1G_MAC7, /**< 1G MAC 7 (Magic packet detection)*/ -+ e_FM_EV_MACSEC_MAC0, /**< MACSEC MAC 0 event */ -+ e_FM_EV_FMAN_CTRL_0, /**< Fman controller event 0 */ -+ e_FM_EV_FMAN_CTRL_1, /**< Fman controller event 1 */ -+ e_FM_EV_FMAN_CTRL_2, /**< Fman controller event 2 */ -+ e_FM_EV_FMAN_CTRL_3, /**< Fman controller event 3 */ -+ e_FM_EV_DUMMY_LAST -+} e_FmInterModuleEvent; -+ -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+/**************************************************************************//** -+ @Description PCD KG scheme registers -+*//***************************************************************************/ -+typedef _Packed struct t_FmPcdPlcrProfileRegs { -+ volatile uint32_t fmpl_pemode; /* 0x090 FMPL_PEMODE - FM Policer Profile Entry Mode*/ -+ volatile uint32_t fmpl_pegnia; /* 0x094 FMPL_PEGNIA - FM Policer Profile Entry GREEN Next Invoked Action*/ -+ volatile uint32_t fmpl_peynia; /* 0x098 FMPL_PEYNIA - FM Policer Profile Entry YELLOW Next Invoked Action*/ -+ volatile uint32_t fmpl_pernia; /* 0x09C FMPL_PERNIA - FM Policer Profile Entry RED Next Invoked Action*/ -+ volatile uint32_t fmpl_pecir; /* 0x0A0 FMPL_PECIR - FM Policer Profile Entry Committed Information Rate*/ -+ volatile uint32_t fmpl_pecbs; /* 0x0A4 FMPL_PECBS - FM Policer Profile Entry Committed Burst Size*/ -+ volatile uint32_t fmpl_pepepir_eir; /* 0x0A8 FMPL_PEPIR_EIR - FM Policer Profile Entry Peak/Excess Information Rate*/ -+ volatile uint32_t fmpl_pepbs_ebs; /* 0x0AC FMPL_PEPBS_EBS - FM Policer Profile Entry Peak/Excess Information Rate*/ -+ volatile uint32_t fmpl_pelts; /* 0x0B0 FMPL_PELTS - FM Policer Profile Entry Last TimeStamp*/ -+ volatile uint32_t fmpl_pects; /* 0x0B4 FMPL_PECTS - FM Policer Profile Entry Committed Token Status*/ -+ volatile uint32_t fmpl_pepts_ets; /* 0x0B8 FMPL_PEPTS_ETS - FM Policer Profile Entry Peak/Excess Token Status*/ -+ volatile uint32_t fmpl_pegpc; /* 0x0BC FMPL_PEGPC - FM Policer Profile Entry GREEN Packet Counter*/ -+ volatile uint32_t fmpl_peypc; /* 0x0C0 FMPL_PEYPC - FM Policer Profile Entry YELLOW Packet Counter*/ -+ volatile uint32_t fmpl_perpc; /* 0x0C4 FMPL_PERPC - FM Policer Profile Entry RED Packet Counter */ -+ volatile uint32_t fmpl_perypc; /* 0x0C8 FMPL_PERYPC - FM Policer Profile Entry Recolored YELLOW Packet Counter*/ -+ volatile uint32_t fmpl_perrpc; /* 0x0CC FMPL_PERRPC - FM Policer Profile Entry Recolored RED Packet Counter*/ -+ volatile uint32_t fmpl_res1[12]; /* 0x0D0-0x0FF Reserved */ -+} _PackedType t_FmPcdPlcrProfileRegs; -+ -+ -+typedef _Packed struct t_FmPcdCcCapwapReassmTimeoutParams { -+ volatile uint32_t portIdAndCapwapReassmTbl; -+ volatile uint32_t fqidForTimeOutFrames; -+ volatile uint32_t timeoutRequestTime; -+}_PackedType t_FmPcdCcCapwapReassmTimeoutParams; -+ -+/**************************************************************************//** -+ @Description PCD CTRL Parameters Page -+*//***************************************************************************/ -+typedef _Packed struct t_FmPcdCtrlParamsPage { -+ volatile uint8_t reserved0[16]; -+ volatile uint32_t iprIpv4Nia; -+ volatile uint32_t iprIpv6Nia; -+ volatile uint8_t reserved1[24]; -+ volatile uint32_t ipfOptionsCounter; -+ volatile uint8_t reserved2[12]; -+ volatile uint32_t misc; -+ volatile uint32_t errorsDiscardMask; -+ volatile uint32_t discardMask; -+ volatile uint8_t reserved3[4]; -+ volatile uint32_t postBmiFetchNia; -+ volatile uint8_t reserved4[172]; -+} _PackedType t_FmPcdCtrlParamsPage; -+ -+ -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+ -+/*for UNDER_CONSTRUCTION_FM_RMU_USE_SEC its defined in fm_ext.h*/ -+typedef uint32_t t_FmFmanCtrl; -+ -+#define FPM_PORT_FM_CTL1 0x00000001 -+#define FPM_PORT_FM_CTL2 0x00000002 -+ -+ -+ -+typedef struct t_FmPcdCcFragScratchPoolCmdParams { -+ uint32_t numOfBuffers; -+ uint8_t bufferPoolId; -+} t_FmPcdCcFragScratchPoolCmdParams; -+ -+typedef struct t_FmPcdCcReassmTimeoutParams { -+ bool activate; -+ uint8_t tsbs; -+ uint32_t iprcpt; -+} t_FmPcdCcReassmTimeoutParams; -+ -+typedef struct { -+ uint8_t baseEntry; -+ uint16_t numOfClsPlanEntries; -+ uint32_t vectors[FM_PCD_MAX_NUM_OF_CLS_PLANS]; -+} t_FmPcdKgInterModuleClsPlanSet; -+ -+/**************************************************************************//** -+ @Description Structure for binding a port to keygen schemes. -+*//***************************************************************************/ -+typedef struct t_FmPcdKgInterModuleBindPortToSchemes { -+ uint8_t hardwarePortId; -+ uint8_t netEnvId; -+ bool useClsPlan; /**< TRUE if this port uses the clsPlan mechanism */ -+ uint8_t numOfSchemes; -+ uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES]; -+} t_FmPcdKgInterModuleBindPortToSchemes; -+ -+typedef struct { -+ uint32_t nextCcNodeInfo; -+ t_List node; -+} t_CcNodeInfo; -+ -+typedef struct -+{ -+ t_Handle h_CcNode; -+ uint16_t index; -+ t_List node; -+}t_CcNodeInformation; -+#define CC_NODE_F_OBJECT(ptr) LIST_OBJECT(ptr, t_CcNodeInformation, node) -+ -+typedef enum e_ModifyState -+{ -+ e_MODIFY_STATE_ADD = 0, -+ e_MODIFY_STATE_REMOVE, -+ e_MODIFY_STATE_CHANGE -+} e_ModifyState; -+ -+typedef struct -+{ -+ t_Handle h_Manip; -+ t_List node; -+}t_ManipInfo; -+#define CC_NEXT_NODE_F_OBJECT(ptr) LIST_OBJECT(ptr, t_CcNodeInfo, node) -+ -+typedef struct { -+ uint32_t type; -+ uint8_t prOffset; -+ uint16_t dataOffset; -+ uint8_t internalBufferOffset; -+ uint8_t numOfTasks; -+ uint8_t numOfExtraTasks; -+ uint8_t hardwarePortId; -+ t_FmRevisionInfo revInfo; -+ uint32_t nia; -+ uint32_t discardMask; -+} t_GetCcParams; -+ -+typedef struct { -+ uint32_t type; -+ int psoSize; -+ uint32_t nia; -+ t_FmFmanCtrl orFmanCtrl; -+ bool overwrite; -+ uint8_t ofpDpde; -+} t_SetCcParams; -+ -+typedef struct { -+ t_GetCcParams getCcParams; -+ t_SetCcParams setCcParams; -+} t_FmPortGetSetCcParams; -+ -+typedef struct { -+ uint32_t type; -+ bool sleep; -+} t_FmSetParams; -+ -+typedef struct { -+ uint32_t type; -+ uint32_t fmqm_gs; -+ uint32_t fm_npi; -+ uint32_t fm_cld; -+ uint32_t fmfp_extc; -+} t_FmGetParams; -+ -+typedef struct { -+ t_FmSetParams setParams; -+ t_FmGetParams getParams; -+} t_FmGetSetParams; -+ -+t_Error FmGetSetParams(t_Handle h_Fm, t_FmGetSetParams *p_Params); -+ -+static __inline__ bool TRY_LOCK(t_Handle h_Spinlock, volatile bool *p_Flag) -+{ -+ uint32_t intFlags; -+ if (h_Spinlock) -+ intFlags = XX_LockIntrSpinlock(h_Spinlock); -+ else -+ intFlags = XX_DisableAllIntr(); -+ -+ if (*p_Flag) -+ { -+ if (h_Spinlock) -+ XX_UnlockIntrSpinlock(h_Spinlock, intFlags); -+ else -+ XX_RestoreAllIntr(intFlags); -+ return FALSE; -+ } -+ *p_Flag = TRUE; -+ -+ if (h_Spinlock) -+ XX_UnlockIntrSpinlock(h_Spinlock, intFlags); -+ else -+ XX_RestoreAllIntr(intFlags); -+ -+ return TRUE; -+} -+ -+#define RELEASE_LOCK(_flag) _flag = FALSE; -+ -+/**************************************************************************//** -+ @Collection Defines used for manipulation CC and BMI -+ @{ -+*//***************************************************************************/ -+#define INTERNAL_CONTEXT_OFFSET 0x80000000 -+#define OFFSET_OF_PR 0x40000000 -+#define MANIP_EXTRA_SPACE 0x20000000 -+#define NUM_OF_TASKS 0x10000000 -+#define OFFSET_OF_DATA 0x08000000 -+#define HW_PORT_ID 0x04000000 -+#define FM_REV 0x02000000 -+#define GET_NIA_FPNE 0x01000000 -+#define GET_NIA_PNDN 0x00800000 -+#define NUM_OF_EXTRA_TASKS 0x00400000 -+#define DISCARD_MASK 0x00200000 -+ -+#define UPDATE_NIA_PNEN 0x80000000 -+#define UPDATE_PSO 0x40000000 -+#define UPDATE_NIA_PNDN 0x20000000 -+#define UPDATE_FMFP_PRC_WITH_ONE_RISC_ONLY 0x10000000 -+#define UPDATE_OFP_DPTE 0x08000000 -+#define UPDATE_NIA_FENE 0x04000000 -+#define UPDATE_NIA_CMNE 0x02000000 -+#define UPDATE_NIA_FPNE 0x01000000 -+/* @} */ -+ -+/**************************************************************************//** -+ @Collection Defines used for manipulation CC and CC -+ @{ -+*//***************************************************************************/ -+#define UPDATE_NIA_ENQ_WITHOUT_DMA 0x80000000 -+#define UPDATE_CC_WITH_TREE 0x40000000 -+#define UPDATE_CC_WITH_DELETE_TREE 0x20000000 -+#define UPDATE_KG_NIA_CC_WA 0x10000000 -+#define UPDATE_KG_OPT_MODE 0x08000000 -+#define UPDATE_KG_NIA 0x04000000 -+#define UPDATE_CC_SHADOW_CLEAR 0x02000000 -+/* @} */ -+ -+#define UPDATE_FPM_BRKC_SLP 0x80000000 -+#define UPDATE_FPM_EXTC 0x40000000 -+#define UPDATE_FPM_EXTC_CLEAR 0x20000000 -+#define GET_FMQM_GS 0x10000000 -+#define GET_FM_NPI 0x08000000 -+#define GET_FMFP_EXTC 0x04000000 -+#define CLEAR_IRAM_READY 0x02000000 -+#define UPDATE_FM_CLD 0x01000000 -+#define GET_FM_CLD 0x00800000 -+#define FM_MAX_NUM_OF_PORTS (FM_MAX_NUM_OF_OH_PORTS + \ -+ FM_MAX_NUM_OF_1G_RX_PORTS + \ -+ FM_MAX_NUM_OF_10G_RX_PORTS + \ -+ FM_MAX_NUM_OF_1G_TX_PORTS + \ -+ FM_MAX_NUM_OF_10G_TX_PORTS) -+ -+#define MODULE_NAME_SIZE 30 -+#define DUMMY_PORT_ID 0 -+ -+#define FM_LIODN_OFFSET_MASK 0x3FF -+ -+/**************************************************************************//** -+ @Description NIA Description -+*//***************************************************************************/ -+#define NIA_ENG_MASK 0x007C0000 -+#define NIA_AC_MASK 0x0003ffff -+ -+#define NIA_ORDER_RESTOR 0x00800000 -+#define NIA_ENG_FM_CTL 0x00000000 -+#define NIA_ENG_PRS 0x00440000 -+#define NIA_ENG_KG 0x00480000 -+#define NIA_ENG_PLCR 0x004C0000 -+#define NIA_ENG_BMI 0x00500000 -+#define NIA_ENG_QMI_ENQ 0x00540000 -+#define NIA_ENG_QMI_DEQ 0x00580000 -+ -+#define NIA_FM_CTL_AC_CC 0x00000006 -+#define NIA_FM_CTL_AC_HC 0x0000000C -+#define NIA_FM_CTL_AC_IND_MODE_TX 0x00000008 -+#define NIA_FM_CTL_AC_IND_MODE_RX 0x0000000A -+#define NIA_FM_CTL_AC_POP_TO_N_STEP 0x0000000e -+#define NIA_FM_CTL_AC_PRE_BMI_FETCH_HEADER 0x00000010 -+#define NIA_FM_CTL_AC_PRE_BMI_FETCH_FULL_FRAME 0x00000018 -+#define NIA_FM_CTL_AC_POST_BMI_FETCH 0x00000012 -+#define NIA_FM_CTL_AC_PRE_BMI_ENQ_FRAME 0x0000001A -+#define NIA_FM_CTL_AC_PRE_BMI_DISCARD_FRAME 0x0000001E -+#define NIA_FM_CTL_AC_POST_BMI_ENQ_ORR 0x00000014 -+#define NIA_FM_CTL_AC_POST_BMI_ENQ 0x00000022 -+#define NIA_FM_CTL_AC_PRE_CC 0x00000020 -+#define NIA_FM_CTL_AC_POST_TX 0x00000024 -+/* V3 only */ -+#define NIA_FM_CTL_AC_NO_IPACC_PRE_BMI_ENQ_FRAME 0x00000028 -+#define NIA_FM_CTL_AC_NO_IPACC_PRE_BMI_DISCARD_FRAME 0x0000002A -+#define NIA_FM_CTL_AC_NO_IPACC_POP_TO_N_STEP 0x0000002C -+ -+#define NIA_BMI_AC_ENQ_FRAME 0x00000002 -+#define NIA_BMI_AC_TX_RELEASE 0x000002C0 -+#define NIA_BMI_AC_RELEASE 0x000000C0 -+#define NIA_BMI_AC_DISCARD 0x000000C1 -+#define NIA_BMI_AC_TX 0x00000274 -+#define NIA_BMI_AC_FETCH 0x00000208 -+#define NIA_BMI_AC_MASK 0x000003FF -+ -+#define NIA_KG_DIRECT 0x00000100 -+#define NIA_KG_CC_EN 0x00000200 -+#define NIA_PLCR_ABSOLUTE 0x00008000 -+ -+#define NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA 0x00000202 -+ -+#if defined(FM_OP_NO_VSP_NO_RELEASE_ERRATA_FMAN_A006675) || defined(FM_ERROR_VSP_NO_MATCH_SW006) -+#define GET_NIA_BMI_AC_ENQ_FRAME(h_FmPcd) \ -+ (uint32_t)((FmPcdIsAdvancedOffloadSupported(h_FmPcd)) ? \ -+ (NIA_ENG_FM_CTL | NIA_FM_CTL_AC_PRE_BMI_ENQ_FRAME) : \ -+ (NIA_ENG_FM_CTL | NIA_FM_CTL_AC_NO_IPACC_PRE_BMI_ENQ_FRAME)) -+#define GET_NIA_BMI_AC_DISCARD_FRAME(h_FmPcd) \ -+ (uint32_t)((FmPcdIsAdvancedOffloadSupported(h_FmPcd)) ? \ -+ (NIA_ENG_FM_CTL | NIA_FM_CTL_AC_PRE_BMI_DISCARD_FRAME) : \ -+ (NIA_ENG_FM_CTL | NIA_FM_CTL_AC_NO_IPACC_PRE_BMI_DISCARD_FRAME)) -+#define GET_NO_PCD_NIA_BMI_AC_ENQ_FRAME() \ -+ (NIA_ENG_FM_CTL | NIA_FM_CTL_AC_NO_IPACC_PRE_BMI_ENQ_FRAME) -+#else -+#define GET_NIA_BMI_AC_ENQ_FRAME(h_FmPcd) \ -+ (uint32_t)((FmPcdIsAdvancedOffloadSupported(h_FmPcd)) ? \ -+ (NIA_ENG_FM_CTL | NIA_FM_CTL_AC_PRE_BMI_ENQ_FRAME) : \ -+ (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME)) -+#define GET_NIA_BMI_AC_DISCARD_FRAME(h_FmPcd) \ -+ (uint32_t)((FmPcdIsAdvancedOffloadSupported(h_FmPcd)) ? \ -+ (NIA_ENG_FM_CTL | NIA_FM_CTL_AC_PRE_BMI_DISCARD_FRAME) : \ -+ (NIA_ENG_BMI | NIA_BMI_AC_DISCARD)) -+#define GET_NO_PCD_NIA_BMI_AC_ENQ_FRAME() \ -+ (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME) -+#endif /* defined(FM_OP_NO_VSP_NO_RELEASE_ERRATA_FMAN_A006675) || ... */ -+ -+/**************************************************************************//** -+ @Description CTRL Parameters Page defines -+*//***************************************************************************/ -+#define FM_CTL_PARAMS_PAGE_OP_FIX_EN 0x80000000 -+#define FM_CTL_PARAMS_PAGE_OFFLOAD_SUPPORT_EN 0x40000000 -+#define FM_CTL_PARAMS_PAGE_ALWAYS_ON 0x00000100 -+ -+#define FM_CTL_PARAMS_PAGE_ERROR_VSP_MASK 0x0000003f -+ -+/**************************************************************************//** -+ @Description Port Id defines -+*//***************************************************************************/ -+#if (DPAA_VERSION == 10) -+#define BASE_OH_PORTID 1 -+#else -+#define BASE_OH_PORTID 2 -+#endif /* (DPAA_VERSION == 10) */ -+#define BASE_1G_RX_PORTID 8 -+#define BASE_10G_RX_PORTID 0x10 -+#define BASE_1G_TX_PORTID 0x28 -+#define BASE_10G_TX_PORTID 0x30 -+ -+#define FM_PCD_PORT_OH_BASE_INDX 0 -+#define FM_PCD_PORT_1G_RX_BASE_INDX (FM_PCD_PORT_OH_BASE_INDX+FM_MAX_NUM_OF_OH_PORTS) -+#define FM_PCD_PORT_10G_RX_BASE_INDX (FM_PCD_PORT_1G_RX_BASE_INDX+FM_MAX_NUM_OF_1G_RX_PORTS) -+#define FM_PCD_PORT_1G_TX_BASE_INDX (FM_PCD_PORT_10G_RX_BASE_INDX+FM_MAX_NUM_OF_10G_RX_PORTS) -+#define FM_PCD_PORT_10G_TX_BASE_INDX (FM_PCD_PORT_1G_TX_BASE_INDX+FM_MAX_NUM_OF_1G_TX_PORTS) -+ -+#if (FM_MAX_NUM_OF_OH_PORTS > 0) -+#define CHECK_PORT_ID_OH_PORTS(_relativePortId) \ -+ if ((_relativePortId) >= FM_MAX_NUM_OF_OH_PORTS) \ -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal OH_PORT port id")) -+#else -+#define CHECK_PORT_ID_OH_PORTS(_relativePortId) \ -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal OH_PORT port id")) -+#endif -+#if (FM_MAX_NUM_OF_1G_RX_PORTS > 0) -+#define CHECK_PORT_ID_1G_RX_PORTS(_relativePortId) \ -+ if ((_relativePortId) >= FM_MAX_NUM_OF_1G_RX_PORTS) \ -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 1G_RX_PORT port id")) -+#else -+#define CHECK_PORT_ID_1G_RX_PORTS(_relativePortId) \ -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 1G_RX_PORT port id")) -+#endif -+#if (FM_MAX_NUM_OF_10G_RX_PORTS > 0) -+#define CHECK_PORT_ID_10G_RX_PORTS(_relativePortId) \ -+ if ((_relativePortId) >= FM_MAX_NUM_OF_10G_RX_PORTS) \ -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 10G_RX_PORT port id")) -+#else -+#define CHECK_PORT_ID_10G_RX_PORTS(_relativePortId) \ -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 10G_RX_PORT port id")) -+#endif -+#if (FM_MAX_NUM_OF_1G_TX_PORTS > 0) -+#define CHECK_PORT_ID_1G_TX_PORTS(_relativePortId) \ -+ if ((_relativePortId) >= FM_MAX_NUM_OF_1G_TX_PORTS) \ -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 1G_TX_PORT port id")) -+#else -+#define CHECK_PORT_ID_1G_TX_PORTS(_relativePortId) \ -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 1G_TX_PORT port id")) -+#endif -+#if (FM_MAX_NUM_OF_10G_TX_PORTS > 0) -+#define CHECK_PORT_ID_10G_TX_PORTS(_relativePortId) \ -+ if ((_relativePortId) >= FM_MAX_NUM_OF_10G_TX_PORTS) \ -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 10G_TX_PORT port id")) -+#else -+#define CHECK_PORT_ID_10G_TX_PORTS(_relativePortId) \ -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 10G_TX_PORT port id")) -+#endif -+ -+uint8_t SwPortIdToHwPortId(e_FmPortType type, uint8_t relativePortId, uint8_t majorRev, uint8_t minorRev); -+ -+#define HW_PORT_ID_TO_SW_PORT_ID(_relativePortId, hardwarePortId) \ -+{ if (((hardwarePortId) >= BASE_OH_PORTID) && \ -+ ((hardwarePortId) < BASE_OH_PORTID+FM_MAX_NUM_OF_OH_PORTS)) \ -+ _relativePortId = (uint8_t)((hardwarePortId)-BASE_OH_PORTID); \ -+ else if (((hardwarePortId) >= BASE_10G_TX_PORTID) && \ -+ ((hardwarePortId) < BASE_10G_TX_PORTID+FM_MAX_NUM_OF_10G_TX_PORTS)) \ -+ _relativePortId = (uint8_t)((hardwarePortId)-BASE_10G_TX_PORTID); \ -+ else if (((hardwarePortId) >= BASE_1G_TX_PORTID) && \ -+ ((hardwarePortId) < BASE_1G_TX_PORTID+FM_MAX_NUM_OF_1G_TX_PORTS)) \ -+ _relativePortId = (uint8_t)((hardwarePortId)-BASE_1G_TX_PORTID); \ -+ else if (((hardwarePortId) >= BASE_10G_RX_PORTID) && \ -+ ((hardwarePortId) < BASE_10G_RX_PORTID+FM_MAX_NUM_OF_10G_RX_PORTS)) \ -+ _relativePortId = (uint8_t)((hardwarePortId)-BASE_10G_RX_PORTID); \ -+ else if (((hardwarePortId) >= BASE_1G_RX_PORTID) && \ -+ ((hardwarePortId) < BASE_1G_RX_PORTID+FM_MAX_NUM_OF_1G_RX_PORTS)) \ -+ _relativePortId = (uint8_t)((hardwarePortId)-BASE_1G_RX_PORTID); \ -+ else { \ -+ _relativePortId = (uint8_t)DUMMY_PORT_ID; \ -+ ASSERT_COND(TRUE); \ -+ } \ -+} -+ -+#define HW_PORT_ID_TO_SW_PORT_INDX(swPortIndex, hardwarePortId) \ -+do { \ -+ if (((hardwarePortId) >= BASE_OH_PORTID) && ((hardwarePortId) < BASE_OH_PORTID+FM_MAX_NUM_OF_OH_PORTS)) \ -+ swPortIndex = (uint8_t)((hardwarePortId)-BASE_OH_PORTID+FM_PCD_PORT_OH_BASE_INDX); \ -+ else if (((hardwarePortId) >= BASE_1G_RX_PORTID) && \ -+ ((hardwarePortId) < BASE_1G_RX_PORTID+FM_MAX_NUM_OF_1G_RX_PORTS)) \ -+ swPortIndex = (uint8_t)((hardwarePortId)-BASE_1G_RX_PORTID+FM_PCD_PORT_1G_RX_BASE_INDX); \ -+ else if (((hardwarePortId) >= BASE_10G_RX_PORTID) && \ -+ ((hardwarePortId) < BASE_10G_RX_PORTID+FM_MAX_NUM_OF_10G_RX_PORTS)) \ -+ swPortIndex = (uint8_t)((hardwarePortId)-BASE_10G_RX_PORTID+FM_PCD_PORT_10G_RX_BASE_INDX); \ -+ else if (((hardwarePortId) >= BASE_1G_TX_PORTID) && \ -+ ((hardwarePortId) < BASE_1G_TX_PORTID+FM_MAX_NUM_OF_1G_TX_PORTS)) \ -+ swPortIndex = (uint8_t)((hardwarePortId)-BASE_1G_TX_PORTID+FM_PCD_PORT_1G_TX_BASE_INDX); \ -+ else if (((hardwarePortId) >= BASE_10G_TX_PORTID) && \ -+ ((hardwarePortId) < BASE_10G_TX_PORTID+FM_MAX_NUM_OF_10G_TX_PORTS)) \ -+ swPortIndex = (uint8_t)((hardwarePortId)-BASE_10G_TX_PORTID+FM_PCD_PORT_10G_TX_BASE_INDX); \ -+ else ASSERT_COND(FALSE); \ -+} while (0) -+ -+#define SW_PORT_INDX_TO_HW_PORT_ID(hardwarePortId, swPortIndex) \ -+do { \ -+ if (((swPortIndex) >= FM_PCD_PORT_OH_BASE_INDX) && ((swPortIndex) < FM_PCD_PORT_1G_RX_BASE_INDX)) \ -+ hardwarePortId = (uint8_t)((swPortIndex)-FM_PCD_PORT_OH_BASE_INDX+BASE_OH_PORTID); \ -+ else if (((swPortIndex) >= FM_PCD_PORT_1G_RX_BASE_INDX) && ((swPortIndex) < FM_PCD_PORT_10G_RX_BASE_INDX)) \ -+ hardwarePortId = (uint8_t)((swPortIndex)-FM_PCD_PORT_1G_RX_BASE_INDX+BASE_1G_RX_PORTID); \ -+ else if (((swPortIndex) >= FM_PCD_PORT_10G_RX_BASE_INDX) && ((swPortIndex) < FM_MAX_NUM_OF_PORTS)) \ -+ hardwarePortId = (uint8_t)((swPortIndex)-FM_PCD_PORT_10G_RX_BASE_INDX+BASE_10G_RX_PORTID); \ -+ else if (((swPortIndex) >= FM_PCD_PORT_1G_TX_BASE_INDX) && ((swPortIndex) < FM_PCD_PORT_10G_TX_BASE_INDX)) \ -+ hardwarePortId = (uint8_t)((swPortIndex)-FM_PCD_PORT_1G_TX_BASE_INDX+BASE_1G_TX_PORTID); \ -+ else if (((swPortIndex) >= FM_PCD_PORT_10G_TX_BASE_INDX) && ((swPortIndex) < FM_MAX_NUM_OF_PORTS)) \ -+ hardwarePortId = (uint8_t)((swPortIndex)-FM_PCD_PORT_10G_TX_BASE_INDX+BASE_10G_TX_PORTID); \ -+ else ASSERT_COND(FALSE); \ -+} while (0) -+ -+#define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE) -+#define BMI_FIFO_UNITS 0x100 -+ -+typedef struct { -+ void (*f_Isr) (t_Handle h_Arg); -+ t_Handle h_SrcHandle; -+ uint8_t guestId; -+} t_FmIntrSrc; -+ -+#define ILLEGAL_HDR_NUM 0xFF -+#define NO_HDR_NUM FM_PCD_PRS_NUM_OF_HDRS -+ -+#define IS_PRIVATE_HEADER(hdr) (((hdr) == HEADER_TYPE_USER_DEFINED_SHIM1) || \ -+ ((hdr) == HEADER_TYPE_USER_DEFINED_SHIM2)) -+#define IS_SPECIAL_HEADER(hdr) ((hdr) == HEADER_TYPE_MACSEC) -+ -+static __inline__ uint8_t GetPrsHdrNum(e_NetHeaderType hdr) -+{ -+ switch (hdr) -+ { case (HEADER_TYPE_ETH): return 0; -+ case (HEADER_TYPE_LLC_SNAP): return 1; -+ case (HEADER_TYPE_VLAN): return 2; -+ case (HEADER_TYPE_PPPoE): return 3; -+ case (HEADER_TYPE_PPP): return 3; -+ case (HEADER_TYPE_MPLS): return 4; -+ case (HEADER_TYPE_IPv4): return 5; -+ case (HEADER_TYPE_IPv6): return 6; -+ case (HEADER_TYPE_GRE): return 7; -+ case (HEADER_TYPE_MINENCAP): return 8; -+ case (HEADER_TYPE_USER_DEFINED_L3): return 9; -+ case (HEADER_TYPE_TCP): return 10; -+ case (HEADER_TYPE_UDP): return 11; -+ case (HEADER_TYPE_IPSEC_AH): -+ case (HEADER_TYPE_IPSEC_ESP): return 12; -+ case (HEADER_TYPE_SCTP): return 13; -+ case (HEADER_TYPE_DCCP): return 14; -+ case (HEADER_TYPE_USER_DEFINED_L4): return 15; -+ case (HEADER_TYPE_USER_DEFINED_SHIM1): -+ case (HEADER_TYPE_USER_DEFINED_SHIM2): -+ case (HEADER_TYPE_MACSEC): return NO_HDR_NUM; -+ default: -+ return ILLEGAL_HDR_NUM; -+ } -+} -+ -+#define FM_PCD_MAX_NUM_OF_OPTIONS(clsPlanEntries) ((clsPlanEntries==256)? 8:((clsPlanEntries==128)? 7: ((clsPlanEntries==64)? 6: ((clsPlanEntries==32)? 5:0)))) -+ -+ -+/**************************************************************************//** -+ @Description A structure for initializing a keygen classification plan group -+*//***************************************************************************/ -+typedef struct t_FmPcdKgInterModuleClsPlanGrpParams { -+ uint8_t netEnvId; /* IN */ -+ bool grpExists; /* OUT (unused in FmPcdKgBuildClsPlanGrp)*/ -+ uint8_t clsPlanGrpId; /* OUT */ -+ bool emptyClsPlanGrp; /* OUT */ -+ uint8_t numOfOptions; /* OUT in FmPcdGetSetClsPlanGrpParams IN in FmPcdKgBuildClsPlanGrp*/ -+ protocolOpt_t options[FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)]; -+ /* OUT in FmPcdGetSetClsPlanGrpParams IN in FmPcdKgBuildClsPlanGrp*/ -+ uint32_t optVectors[FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)]; -+ /* OUT in FmPcdGetSetClsPlanGrpParams IN in FmPcdKgBuildClsPlanGrp*/ -+} t_FmPcdKgInterModuleClsPlanGrpParams; -+ -+typedef struct t_FmPcdLock { -+ t_Handle h_Spinlock; -+ volatile bool flag; -+ t_List node; -+} t_FmPcdLock; -+#define FM_PCD_LOCK_OBJ(ptr) LIST_OBJECT(ptr, t_FmPcdLock, node) -+ -+ -+typedef t_Error (t_FmPortGetSetCcParamsCallback) (t_Handle h_FmPort, -+ t_FmPortGetSetCcParams *p_FmPortGetSetCcParams); -+ -+ -+/***********************************************************************/ -+/* Common API for FM-PCD module */ -+/***********************************************************************/ -+t_Handle FmPcdGetHcHandle(t_Handle h_FmPcd); -+uint32_t FmPcdGetSwPrsOffset(t_Handle h_FmPcd, e_NetHeaderType hdr, uint8_t indexPerHdr); -+uint32_t FmPcdGetLcv(t_Handle h_FmPcd, uint32_t netEnvId, uint8_t hdrNum); -+uint32_t FmPcdGetMacsecLcv(t_Handle h_FmPcd, uint32_t netEnvId); -+void FmPcdIncNetEnvOwners(t_Handle h_FmPcd, uint8_t netEnvId); -+void FmPcdDecNetEnvOwners(t_Handle h_FmPcd, uint8_t netEnvId); -+uint8_t FmPcdGetNetEnvId(t_Handle h_NetEnv); -+void FmPcdPortRegister(t_Handle h_FmPcd, t_Handle h_FmPort, uint8_t hardwarePortId); -+uint32_t FmPcdLock(t_Handle h_FmPcd); -+void FmPcdUnlock(t_Handle h_FmPcd, uint32_t intFlags); -+bool FmPcdNetEnvIsHdrExist(t_Handle h_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr); -+t_Error FmPcdFragHcScratchPoolInit(t_Handle h_FmPcd, uint8_t scratchBpid); -+t_Error FmPcdRegisterReassmPort(t_Handle h_FmPcd, t_Handle h_IpReasmCommonPramTbl); -+t_Error FmPcdUnregisterReassmPort(t_Handle h_FmPcd, t_Handle h_IpReasmCommonPramTbl); -+bool FmPcdIsAdvancedOffloadSupported(t_Handle h_FmPcd); -+bool FmPcdLockTryLockAll(t_Handle h_FmPcd); -+void FmPcdLockUnlockAll(t_Handle h_FmPcd); -+t_Error FmPcdHcSync(t_Handle h_FmPcd); -+t_Handle FmGetPcd(t_Handle h_Fm); -+/***********************************************************************/ -+/* Common API for FM-PCD KG module */ -+/***********************************************************************/ -+uint8_t FmPcdKgGetClsPlanGrpBase(t_Handle h_FmPcd, uint8_t clsPlanGrp); -+uint16_t FmPcdKgGetClsPlanGrpSize(t_Handle h_FmPcd, uint8_t clsPlanGrp); -+t_Error FmPcdKgBuildClsPlanGrp(t_Handle h_FmPcd, t_FmPcdKgInterModuleClsPlanGrpParams *p_Grp, t_FmPcdKgInterModuleClsPlanSet *p_ClsPlanSet); -+ -+uint8_t FmPcdKgGetSchemeId(t_Handle h_Scheme); -+#if (DPAA_VERSION >= 11) -+bool FmPcdKgGetVspe(t_Handle h_Scheme); -+#endif /* (DPAA_VERSION >= 11) */ -+uint8_t FmPcdKgGetRelativeSchemeId(t_Handle h_FmPcd, uint8_t schemeId); -+void FmPcdKgDestroyClsPlanGrp(t_Handle h_FmPcd, uint8_t grpId); -+t_Error FmPcdKgCheckInvalidateSchemeSw(t_Handle h_Scheme); -+t_Error FmPcdKgBuildBindPortToSchemes(t_Handle h_FmPcd , t_FmPcdKgInterModuleBindPortToSchemes *p_BindPortToSchemes, uint32_t *p_SpReg, bool add); -+bool FmPcdKgHwSchemeIsValid(uint32_t schemeModeReg); -+uint32_t FmPcdKgBuildWriteSchemeActionReg(uint8_t schemeId, bool updateCounter); -+uint32_t FmPcdKgBuildReadSchemeActionReg(uint8_t schemeId); -+uint32_t FmPcdKgBuildWriteClsPlanBlockActionReg(uint8_t grpId); -+uint32_t FmPcdKgBuildWritePortSchemeBindActionReg(uint8_t hardwarePortId); -+uint32_t FmPcdKgBuildReadPortSchemeBindActionReg(uint8_t hardwarePortId); -+uint32_t FmPcdKgBuildWritePortClsPlanBindActionReg(uint8_t hardwarePortId); -+bool FmPcdKgIsSchemeValidSw(t_Handle h_Scheme); -+ -+t_Error FmPcdKgBindPortToSchemes(t_Handle h_FmPcd , t_FmPcdKgInterModuleBindPortToSchemes *p_SchemeBind); -+t_Error FmPcdKgUnbindPortToSchemes(t_Handle h_FmPcd , t_FmPcdKgInterModuleBindPortToSchemes *p_SchemeBind); -+uint32_t FmPcdKgGetRequiredAction(t_Handle h_FmPcd, uint8_t schemeId); -+uint32_t FmPcdKgGetRequiredActionFlag(t_Handle h_FmPcd, uint8_t schemeId); -+e_FmPcdDoneAction FmPcdKgGetDoneAction(t_Handle h_FmPcd, uint8_t schemeId); -+e_FmPcdEngine FmPcdKgGetNextEngine(t_Handle h_FmPcd, uint8_t schemeId); -+void FmPcdKgUpdateRequiredAction(t_Handle h_Scheme, uint32_t requiredAction); -+bool FmPcdKgIsDirectPlcr(t_Handle h_FmPcd, uint8_t schemeId); -+bool FmPcdKgIsDistrOnPlcrProfile(t_Handle h_FmPcd, uint8_t schemeId); -+uint16_t FmPcdKgGetRelativeProfileId(t_Handle h_FmPcd, uint8_t schemeId); -+t_Handle FmPcdKgGetSchemeHandle(t_Handle h_FmPcd, uint8_t relativeSchemeId); -+bool FmPcdKgIsSchemeHasOwners(t_Handle h_Scheme); -+t_Error FmPcdKgCcGetSetParams(t_Handle h_FmPcd, t_Handle h_Scheme, uint32_t requiredAction, uint32_t value); -+t_Error FmPcdKgSetOrBindToClsPlanGrp(t_Handle h_FmPcd, uint8_t hardwarePortId, uint8_t netEnvId, protocolOpt_t *p_OptArray, uint8_t *p_ClsPlanGrpId, bool *p_IsEmptyClsPlanGrp); -+t_Error FmPcdKgDeleteOrUnbindPortToClsPlanGrp(t_Handle h_FmPcd, uint8_t hardwarePortId, uint8_t clsPlanGrpId); -+ -+/***********************************************************************/ -+/* Common API for FM-PCD parser module */ -+/***********************************************************************/ -+t_Error FmPcdPrsIncludePortInStatistics(t_Handle p_FmPcd, uint8_t hardwarePortId, bool include); -+ -+/***********************************************************************/ -+/* Common API for FM-PCD policer module */ -+/***********************************************************************/ -+t_Error FmPcdPlcrAllocProfiles(t_Handle h_FmPcd, uint8_t hardwarePortId, uint16_t numOfProfiles); -+t_Error FmPcdPlcrFreeProfiles(t_Handle h_FmPcd, uint8_t hardwarePortId); -+bool FmPcdPlcrIsProfileValid(t_Handle h_FmPcd, uint16_t absoluteProfileId); -+uint16_t FmPcdPlcrGetPortProfilesBase(t_Handle h_FmPcd, uint8_t hardwarePortId); -+uint16_t FmPcdPlcrGetPortNumOfProfiles(t_Handle h_FmPcd, uint8_t hardwarePortId); -+uint32_t FmPcdPlcrBuildWritePlcrActionRegs(uint16_t absoluteProfileId); -+uint32_t FmPcdPlcrBuildCounterProfileReg(e_FmPcdPlcrProfileCounters counter); -+uint32_t FmPcdPlcrBuildWritePlcrActionReg(uint16_t absoluteProfileId); -+uint32_t FmPcdPlcrBuildReadPlcrActionReg(uint16_t absoluteProfileId); -+uint16_t FmPcdPlcrProfileGetAbsoluteId(t_Handle h_Profile); -+t_Error FmPcdPlcrGetAbsoluteIdByProfileParams(t_Handle h_FmPcd, -+ e_FmPcdProfileTypeSelection profileType, -+ t_Handle h_FmPort, -+ uint16_t relativeProfile, -+ uint16_t *p_AbsoluteId); -+void FmPcdPlcrInvalidateProfileSw(t_Handle h_FmPcd, uint16_t absoluteProfileId); -+void FmPcdPlcrValidateProfileSw(t_Handle h_FmPcd, uint16_t absoluteProfileId); -+bool FmPcdPlcrHwProfileIsValid(uint32_t profileModeReg); -+uint32_t FmPcdPlcrGetRequiredAction(t_Handle h_FmPcd, uint16_t absoluteProfileId); -+uint32_t FmPcdPlcrGetRequiredActionFlag(t_Handle h_FmPcd, uint16_t absoluteProfileId); -+uint32_t FmPcdPlcrBuildNiaProfileReg(bool green, bool yellow, bool red); -+void FmPcdPlcrUpdateRequiredAction(t_Handle h_FmPcd, uint16_t absoluteProfileId, uint32_t requiredAction); -+t_Error FmPcdPlcrCcGetSetParams(t_Handle h_FmPcd, uint16_t profileIndx,uint32_t requiredAction); -+ -+/***********************************************************************/ -+/* Common API for FM-PCD CC module */ -+/***********************************************************************/ -+uint8_t FmPcdCcGetParseCode(t_Handle h_CcNode); -+uint8_t FmPcdCcGetOffset(t_Handle h_CcNode); -+t_Error FmPcdCcRemoveKey(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode, uint16_t keyIndex); -+t_Error FmPcdCcAddKey(t_Handle h_FmPcd, t_Handle h_CcNode, uint16_t keyIndex, uint8_t keySize, t_FmPcdCcKeyParams *p_FmPCdCcKeyParams); -+t_Error FmPcdCcModifyKey(t_Handle h_FmPcd, t_Handle h_CcNode, uint16_t keyIndex, uint8_t keySize, uint8_t *p_Key, uint8_t *p_Mask); -+t_Error FmPcdCcModifyKeyAndNextEngine(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode, uint16_t keyIndex, uint8_t keySize, t_FmPcdCcKeyParams *p_FmPcdCcKeyParams); -+t_Error FmPcdCcModifyMissNextEngineParamNode(t_Handle h_FmPcd,t_Handle h_FmPcdCcNode, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams); -+t_Error FmPcdCcModifyNextEngineParamTree(t_Handle h_FmPcd, t_Handle h_FmPcdCcTree, uint8_t grpId, uint8_t index, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams); -+uint32_t FmPcdCcGetNodeAddrOffsetFromNodeInfo(t_Handle h_FmPcd, t_Handle h_Pointer); -+t_Handle FmPcdCcTreeGetSavedManipParams(t_Handle h_FmTree); -+void FmPcdCcTreeSetSavedManipParams(t_Handle h_FmTree, t_Handle h_SavedManipParams); -+t_Error FmPcdCcTreeAddIPR(t_Handle h_FmPcd, t_Handle h_FmTree, t_Handle h_NetEnv, t_Handle h_ReassemblyManip, bool schemes); -+t_Error FmPcdCcTreeAddCPR(t_Handle h_FmPcd, t_Handle h_FmTree, t_Handle h_NetEnv, t_Handle h_ReassemblyManip, bool schemes); -+t_Error FmPcdCcBindTree(t_Handle h_FmPcd, t_Handle h_PcdParams, t_Handle h_CcTree, uint32_t *p_Offset,t_Handle h_FmPort); -+t_Error FmPcdCcUnbindTree(t_Handle h_FmPcd, t_Handle h_CcTree); -+ -+/***********************************************************************/ -+/* Common API for FM-PCD Manip module */ -+/***********************************************************************/ -+t_Error FmPcdManipUpdate(t_Handle h_FmPcd, t_Handle h_PcdParams, t_Handle h_FmPort, t_Handle h_Manip, t_Handle h_Ad, bool validate, int level, t_Handle h_FmTree, bool modify); -+ -+/***********************************************************************/ -+/* Common API for FM-Port module */ -+/***********************************************************************/ -+#if (DPAA_VERSION >= 11) -+typedef enum e_FmPortGprFuncType -+{ -+ e_FM_PORT_GPR_EMPTY = 0, -+ e_FM_PORT_GPR_MURAM_PAGE -+} e_FmPortGprFuncType; -+ -+t_Error FmPortSetGprFunc(t_Handle h_FmPort, e_FmPortGprFuncType gprFunc, void **p_Value); -+#endif /* DPAA_VERSION >= 11) */ -+t_Error FmGetSetParams(t_Handle h_Fm, t_FmGetSetParams *p_FmGetSetParams); -+t_Error FmPortGetSetCcParams(t_Handle h_FmPort, t_FmPortGetSetCcParams *p_FmPortGetSetCcParams); -+uint8_t FmPortGetNetEnvId(t_Handle h_FmPort); -+uint8_t FmPortGetHardwarePortId(t_Handle h_FmPort); -+uint32_t FmPortGetPcdEngines(t_Handle h_FmPort); -+void FmPortPcdKgSwUnbindClsPlanGrp (t_Handle h_FmPort); -+ -+ -+#if (DPAA_VERSION >= 11) -+t_Error FmPcdFrmReplicUpdate(t_Handle h_FmPcd, t_Handle h_FmPort, t_Handle h_FrmReplic); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Function FmRegisterIntr -+ -+ @Description Used to register an inter-module event handler to be processed by FM -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] mod The module that causes the event -+ @Param[in] modId Module id - if more than 1 instansiation of this -+ mode exists,0 otherwise. -+ @Param[in] intrType Interrupt type (error/normal) selection. -+ @Param[in] f_Isr The interrupt service routine. -+ @Param[in] h_Arg Argument to be passed to f_Isr. -+ -+ @Return None. -+*//***************************************************************************/ -+void FmRegisterIntr(t_Handle h_Fm, -+ e_FmEventModules mod, -+ uint8_t modId, -+ e_FmIntrType intrType, -+ void (*f_Isr) (t_Handle h_Arg), -+ t_Handle h_Arg); -+ -+/**************************************************************************//** -+ @Function FmUnregisterIntr -+ -+ @Description Used to un-register an inter-module event handler that was processed by FM -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] mod The module that causes the event -+ @Param[in] modId Module id - if more than 1 instansiation of this -+ mode exists,0 otherwise. -+ @Param[in] intrType Interrupt type (error/normal) selection. -+ -+ @Return None. -+*//***************************************************************************/ -+void FmUnregisterIntr(t_Handle h_Fm, -+ e_FmEventModules mod, -+ uint8_t modId, -+ e_FmIntrType intrType); -+ -+/**************************************************************************//** -+ @Function FmRegisterFmCtlIntr -+ -+ @Description Used to register to one of the fmCtl events in the FM module -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] eventRegId FmCtl event id (0-7). -+ @Param[in] f_Isr The interrupt service routine. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+void FmRegisterFmCtlIntr(t_Handle h_Fm, uint8_t eventRegId, void (*f_Isr) (t_Handle h_Fm, uint32_t event)); -+ -+ -+/**************************************************************************//** -+ @Description enum for defining MAC types -+*//***************************************************************************/ -+typedef enum e_FmMacType { -+ e_FM_MAC_10G = 0, /**< 10G MAC */ -+ e_FM_MAC_1G /**< 1G MAC */ -+} e_FmMacType; -+ -+/**************************************************************************//** -+ @Description Structure for port-FM communication during FM_PORT_Init. -+ Fields commented 'IN' are passed by the port module to be used -+ by the FM module. -+ Fields commented 'OUT' will be filled by FM before returning to port. -+ Some fields are optional (depending on configuration) and -+ will be analized by the port and FM modules accordingly. -+*//***************************************************************************/ -+typedef struct t_FmInterModulePortInitParams { -+ uint8_t hardwarePortId; /**< IN. port Id */ -+ e_FmPortType portType; /**< IN. Port type */ -+ bool independentMode; /**< IN. TRUE if FM Port operates in independent mode */ -+ uint16_t liodnOffset; /**< IN. Port's requested resource */ -+ uint8_t numOfTasks; /**< IN. Port's requested resource */ -+ uint8_t numOfExtraTasks; /**< IN. Port's requested resource */ -+ uint8_t numOfOpenDmas; /**< IN. Port's requested resource */ -+ uint8_t numOfExtraOpenDmas; /**< IN. Port's requested resource */ -+ uint32_t sizeOfFifo; /**< IN. Port's requested resource */ -+ uint32_t extraSizeOfFifo; /**< IN. Port's requested resource */ -+ uint8_t deqPipelineDepth; /**< IN. Port's requested resource */ -+ uint16_t maxFrameLength; /**< IN. Port's max frame length. */ -+ uint16_t liodnBase; /**< IN. Irrelevant for P4080 rev 1. -+ LIODN base for this port, to be -+ used together with LIODN offset. */ -+ t_FmPhysAddr fmMuramPhysBaseAddr;/**< OUT. FM-MURAM physical address*/ -+} t_FmInterModulePortInitParams; -+ -+/**************************************************************************//** -+ @Description Structure for port-FM communication during FM_PORT_Free. -+*//***************************************************************************/ -+typedef struct t_FmInterModulePortFreeParams { -+ uint8_t hardwarePortId; /**< IN. port Id */ -+ e_FmPortType portType; /**< IN. Port type */ -+ uint8_t deqPipelineDepth; /**< IN. Port's requested resource */ -+} t_FmInterModulePortFreeParams; -+ -+/**************************************************************************//** -+ @Function FmGetPcdPrsBaseAddr -+ -+ @Description Get the base address of the Parser from the FM module -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return Base address. -+*//***************************************************************************/ -+uintptr_t FmGetPcdPrsBaseAddr(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FmGetPcdKgBaseAddr -+ -+ @Description Get the base address of the Keygen from the FM module -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return Base address. -+*//***************************************************************************/ -+uintptr_t FmGetPcdKgBaseAddr(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FmGetPcdPlcrBaseAddr -+ -+ @Description Get the base address of the Policer from the FM module -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return Base address. -+*//***************************************************************************/ -+uintptr_t FmGetPcdPlcrBaseAddr(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FmGetMuramHandle -+ -+ @Description Get the handle of the MURAM from the FM module -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return MURAM module handle. -+*//***************************************************************************/ -+t_Handle FmGetMuramHandle(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FmGetPhysicalMuramBase -+ -+ @Description Get the physical base address of the MURAM from the FM module -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] fmPhysAddr Physical MURAM base -+ -+ @Return Physical base address. -+*//***************************************************************************/ -+void FmGetPhysicalMuramBase(t_Handle h_Fm, t_FmPhysAddr *fmPhysAddr); -+ -+/**************************************************************************//** -+ @Function FmGetTimeStampScale -+ -+ @Description Used internally by other modules in order to get the timeStamp -+ period as requested by the application. -+ -+ This function returns bit number that is incremented every 1 usec. -+ To calculate timestamp period in nsec, use -+ 1000 / (1 << FmGetTimeStampScale()). -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return Bit that counts 1 usec. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+uint32_t FmGetTimeStampScale(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FmResumeStalledPort -+ -+ @Description Used internally by FM port to release a stalled port. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] hardwarePortId HW port id. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+t_Error FmResumeStalledPort(t_Handle h_Fm, uint8_t hardwarePortId); -+ -+/**************************************************************************//** -+ @Function FmIsPortStalled -+ -+ @Description Used internally by FM port to read the port's status. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] hardwarePortId HW port id. -+ @Param[in] p_IsStalled A pointer to the boolean port stalled state -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+t_Error FmIsPortStalled(t_Handle h_Fm, uint8_t hardwarePortId, bool *p_IsStalled); -+ -+/**************************************************************************//** -+ @Function FmResetMac -+ -+ @Description Used by MAC driver to reset the MAC registers -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] type MAC type. -+ @Param[in] macId MAC id - according to type. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+t_Error FmResetMac(t_Handle h_Fm, e_FmMacType type, uint8_t macId); -+ -+/**************************************************************************//** -+ @Function FmGetClockFreq -+ -+ @Description Used by MAC driver to get the FM clock frequency -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return clock-freq on success; 0 otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+uint16_t FmGetClockFreq(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FmGetMacClockFreq -+ -+ @Description Used by MAC driver to get the MAC clock frequency -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return clock-freq on success; 0 otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+uint16_t FmGetMacClockFreq(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FmGetId -+ -+ @Description Used by PCD driver to read rhe FM id -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+uint8_t FmGetId(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FmGetSetPortParams -+ -+ @Description Used by FM-PORT driver to pass and receive parameters between -+ PORT and FM modules. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in,out] p_PortParams A structure of FM Port parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+t_Error FmGetSetPortParams(t_Handle h_Fm,t_FmInterModulePortInitParams *p_PortParams); -+ -+/**************************************************************************//** -+ @Function FmFreePortParams -+ -+ @Description Used by FM-PORT driver to free port's resources within the FM. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in,out] p_PortParams A structure of FM Port parameters. -+ -+ @Return None. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+void FmFreePortParams(t_Handle h_Fm,t_FmInterModulePortFreeParams *p_PortParams); -+ -+/**************************************************************************//** -+ @Function FmSetNumOfRiscsPerPort -+ -+ @Description Used by FM-PORT driver to pass parameter between -+ PORT and FM modules for working with number of RISC.. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] hardwarePortId hardware port Id. -+ @Param[in] numOfFmanCtrls number of Fman Controllers. -+ @Param[in] orFmanCtrl Fman Controller for order restoration. -+ -+ @Return None. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+t_Error FmSetNumOfRiscsPerPort(t_Handle h_Fm, uint8_t hardwarePortId, uint8_t numOfFmanCtrls, t_FmFmanCtrl orFmanCtrl); -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+/**************************************************************************//* -+ @Function FmDumpPortRegs -+ -+ @Description Dumps FM port registers which are part of FM common registers -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] hardwarePortId HW port id. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only FM_Init(). -+*//***************************************************************************/ -+t_Error FmDumpPortRegs(t_Handle h_Fm,uint8_t hardwarePortId); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+void FmRegisterPcd(t_Handle h_Fm, t_Handle h_FmPcd); -+void FmUnregisterPcd(t_Handle h_Fm); -+t_Handle FmGetPcdHandle(t_Handle h_Fm); -+t_Error FmEnableRamsEcc(t_Handle h_Fm); -+t_Error FmDisableRamsEcc(t_Handle h_Fm); -+void FmGetRevision(t_Handle h_Fm, t_FmRevisionInfo *p_FmRevisionInfo); -+t_Error FmAllocFmanCtrlEventReg(t_Handle h_Fm, uint8_t *p_EventId); -+void FmFreeFmanCtrlEventReg(t_Handle h_Fm, uint8_t eventId); -+void FmSetFmanCtrlIntr(t_Handle h_Fm, uint8_t eventRegId, uint32_t enableEvents); -+uint32_t FmGetFmanCtrlIntr(t_Handle h_Fm, uint8_t eventRegId); -+void FmRegisterFmanCtrlIntr(t_Handle h_Fm, uint8_t eventRegId, void (*f_Isr) (t_Handle h_Fm, uint32_t event), t_Handle h_Arg); -+void FmUnregisterFmanCtrlIntr(t_Handle h_Fm, uint8_t eventRegId); -+t_Error FmSetMacMaxFrame(t_Handle h_Fm, e_FmMacType type, uint8_t macId, uint16_t mtu); -+bool FmIsMaster(t_Handle h_Fm); -+uint8_t FmGetGuestId(t_Handle h_Fm); -+uint16_t FmGetTnumAgingPeriod(t_Handle h_Fm); -+t_Error FmSetPortPreFetchConfiguration(t_Handle h_Fm, uint8_t portNum, bool preFetchConfigured); -+t_Error FmGetPortPreFetchConfiguration(t_Handle h_Fm, uint8_t portNum, bool *p_PortConfigured, bool *p_PreFetchConfigured); -+ -+ -+#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -+t_Error Fm10GTxEccWorkaround(t_Handle h_Fm, uint8_t macId); -+#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ -+ -+void FmMuramClear(t_Handle h_FmMuram); -+t_Error FmSetNumOfOpenDmas(t_Handle h_Fm, -+ uint8_t hardwarePortId, -+ uint8_t *p_NumOfOpenDmas, -+ uint8_t *p_NumOfExtraOpenDmas, -+ bool initialConfig); -+t_Error FmSetNumOfTasks(t_Handle h_Fm, -+ uint8_t hardwarePortId, -+ uint8_t *p_NumOfTasks, -+ uint8_t *p_NumOfExtraTasks, -+ bool initialConfig); -+t_Error FmSetSizeOfFifo(t_Handle h_Fm, -+ uint8_t hardwarePortId, -+ uint32_t *p_SizeOfFifo, -+ uint32_t *p_ExtraSizeOfFifo, -+ bool initialConfig); -+ -+t_Error FmSetCongestionGroupPFCpriority(t_Handle h_Fm, -+ uint32_t congestionGroupId, -+ uint8_t priorityBitMap); -+ -+#if (DPAA_VERSION >= 11) -+t_Error FmVSPAllocForPort(t_Handle h_Fm, -+ e_FmPortType portType, -+ uint8_t portId, -+ uint8_t numOfStorageProfiles); -+ -+t_Error FmVSPFreeForPort(t_Handle h_Fm, -+ e_FmPortType portType, -+ uint8_t portId); -+ -+t_Error FmVSPGetAbsoluteProfileId(t_Handle h_Fm, -+ e_FmPortType portType, -+ uint8_t portId, -+ uint16_t relativeProfile, -+ uint16_t *p_AbsoluteId); -+t_Error FmVSPCheckRelativeProfile(t_Handle h_Fm, -+ e_FmPortType portType, -+ uint8_t portId, -+ uint16_t relativeProfile); -+ -+uintptr_t FmGetVSPBaseAddr(t_Handle h_Fm); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ -+#endif /* __FM_COMMON_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc/fm_hc.h -@@ -0,0 +1,93 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#ifndef __FM_HC_H -+#define __FM_HC_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "fsl_fman_kg.h" -+ -+#define __ERR_MODULE__ MODULE_FM_PCD -+ -+ -+typedef struct t_FmHcParams { -+ t_Handle h_Fm; -+ t_Handle h_FmPcd; -+ t_FmPcdHcParams params; -+} t_FmHcParams; -+ -+ -+t_Handle FmHcConfigAndInit(t_FmHcParams *p_FmHcParams); -+void FmHcFree(t_Handle h_FmHc); -+t_Error FmHcSetFramesDataMemory(t_Handle h_FmHc, -+ uint8_t memId); -+t_Error FmHcDumpRegs(t_Handle h_FmHc); -+ -+void FmHcTxConf(t_Handle h_FmHc, t_DpaaFD *p_Fd); -+ -+t_Error FmHcPcdKgSetScheme(t_Handle h_FmHc, -+ t_Handle h_Scheme, -+ struct fman_kg_scheme_regs *p_SchemeRegs, -+ bool updateCounter); -+t_Error FmHcPcdKgDeleteScheme(t_Handle h_FmHc, t_Handle h_Scheme); -+t_Error FmHcPcdCcCapwapTimeoutReassm(t_Handle h_FmHc, t_FmPcdCcCapwapReassmTimeoutParams *p_CcCapwapReassmTimeoutParams ); -+t_Error FmHcPcdCcIpFragScratchPollCmd(t_Handle h_FmHc, bool fill, t_FmPcdCcFragScratchPoolCmdParams *p_FmPcdCcFragScratchPoolCmdParams); -+t_Error FmHcPcdCcTimeoutReassm(t_Handle h_FmHc, t_FmPcdCcReassmTimeoutParams *p_CcReassmTimeoutParams, uint8_t *p_Result); -+t_Error FmHcPcdKgSetClsPlan(t_Handle h_FmHc, t_FmPcdKgInterModuleClsPlanSet *p_Set); -+t_Error FmHcPcdKgDeleteClsPlan(t_Handle h_FmHc, uint8_t clsPlanGrpId); -+ -+t_Error FmHcPcdKgSetSchemeCounter(t_Handle h_FmHc, t_Handle h_Scheme, uint32_t value); -+uint32_t FmHcPcdKgGetSchemeCounter(t_Handle h_FmHc, t_Handle h_Scheme); -+ -+t_Error FmHcPcdCcDoDynamicChange(t_Handle h_FmHc, uint32_t oldAdAddrOffset, uint32_t newAdAddrOffset); -+ -+t_Error FmHcPcdPlcrSetProfile(t_Handle h_FmHc, t_Handle h_Profile, t_FmPcdPlcrProfileRegs *p_PlcrRegs); -+t_Error FmHcPcdPlcrDeleteProfile(t_Handle h_FmHc, t_Handle h_Profile); -+ -+t_Error FmHcPcdPlcrSetProfileCounter(t_Handle h_FmHc, t_Handle h_Profile, e_FmPcdPlcrProfileCounters counter, uint32_t value); -+uint32_t FmHcPcdPlcrGetProfileCounter(t_Handle h_FmHc, t_Handle h_Profile, e_FmPcdPlcrProfileCounters counter); -+ -+t_Error FmHcKgWriteSp(t_Handle h_FmHc, uint8_t hardwarePortId, uint32_t spReg, bool add); -+t_Error FmHcKgWriteCpp(t_Handle h_FmHc, uint8_t hardwarePortId, uint32_t cppReg); -+ -+t_Error FmHcPcdKgCcGetSetParams(t_Handle h_FmHc, t_Handle h_Scheme, uint32_t requiredAction, uint32_t value); -+t_Error FmHcPcdPlcrCcGetSetParams(t_Handle h_FmHc,uint16_t absoluteProfileId, uint32_t requiredAction); -+ -+t_Error FmHcPcdSync(t_Handle h_FmHc); -+t_Handle FmHcGetPort(t_Handle h_FmHc); -+ -+ -+ -+ -+#endif /* __FM_HC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc/fm_sp_common.h -@@ -0,0 +1,117 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_sp_common.h -+ -+ @Description FM SP ... -+*//***************************************************************************/ -+#ifndef __FM_SP_COMMON_H -+#define __FM_SP_COMMON_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "list_ext.h" -+ -+#include "fm_ext.h" -+#include "fm_pcd_ext.h" -+#include "fsl_fman.h" -+ -+/**************************************************************************//** -+ @Description defaults -+*//***************************************************************************/ -+#define DEFAULT_FM_SP_bufferPrefixContent_privDataSize 0 -+#define DEFAULT_FM_SP_bufferPrefixContent_passPrsResult FALSE -+#define DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp FALSE -+#define DEFAULT_FM_SP_bufferPrefixContent_allOtherPCDInfo FALSE -+#define DEFAULT_FM_SP_bufferPrefixContent_dataAlign 64 -+ -+/**************************************************************************//** -+ @Description structure for defining internal context copying -+*//***************************************************************************/ -+typedef struct -+{ -+ uint16_t extBufOffset; /**< Offset in External buffer to which internal -+ context is copied to (Rx) or taken from (Tx, Op). */ -+ uint8_t intContextOffset; /**< Offset within internal context to copy from -+ (Rx) or to copy to (Tx, Op). */ -+ uint16_t size; /**< Internal offset size to be copied */ -+} t_FmSpIntContextDataCopy; -+ -+/**************************************************************************//** -+ @Description struct for defining external buffer margins -+*//***************************************************************************/ -+typedef struct { -+ uint16_t startMargins; /**< Number of bytes to be left at the beginning -+ of the external buffer (must be divisible by 16) */ -+ uint16_t endMargins; /**< number of bytes to be left at the end -+ of the external buffer(must be divisible by 16) */ -+} t_FmSpBufMargins; -+ -+typedef struct { -+ uint32_t dataOffset; -+ uint32_t prsResultOffset; -+ uint32_t timeStampOffset; -+ uint32_t hashResultOffset; -+ uint32_t pcdInfoOffset; -+ uint32_t manipOffset; -+} t_FmSpBufferOffsets; -+ -+ -+t_Error FmSpBuildBufferStructure(t_FmSpIntContextDataCopy *p_FmPortIntContextDataCopy, -+ t_FmBufferPrefixContent *p_BufferPrefixContent, -+ t_FmSpBufMargins *p_FmPortBufMargins, -+ t_FmSpBufferOffsets *p_FmPortBufferOffsets, -+ uint8_t *internalBufferOffset); -+ -+t_Error FmSpCheckIntContextParams(t_FmSpIntContextDataCopy *p_FmSpIntContextDataCopy); -+t_Error FmSpCheckBufPoolsParams(t_FmExtPools *p_FmExtPools, -+ t_FmBackupBmPools *p_FmBackupBmPools, -+ t_FmBufPoolDepletion *p_FmBufPoolDepletion); -+t_Error FmSpCheckBufMargins(t_FmSpBufMargins *p_FmSpBufMargins); -+void FmSpSetBufPoolsInAscOrderOfBufSizes(t_FmExtPools *p_FmExtPools, uint8_t *orderedArray, uint16_t *sizesArray); -+ -+t_Error FmPcdSpAllocProfiles(t_Handle h_FmPcd, -+ uint8_t hardwarePortId, -+ uint16_t numOfStorageProfiles, -+ uint16_t *base, -+ uint8_t *log2Num); -+t_Error FmPcdSpGetAbsoluteProfileId(t_Handle h_FmPcd, -+ t_Handle h_FmPort, -+ uint16_t relativeProfile, -+ uint16_t *p_AbsoluteId); -+void SpInvalidateProfileSw(t_Handle h_FmPcd, uint16_t absoluteProfileId); -+void SpValidateProfileSw(t_Handle h_FmPcd, uint16_t absoluteProfileId); -+ -+ -+#endif /* __FM_SP_COMMON_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/etc/Makefile -@@ -0,0 +1,12 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+ -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+ -+obj-y += fsl-ncsw-etc.o -+ -+fsl-ncsw-etc-objs := mm.o memcpy.o sprint.o list.o error.o ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/etc/error.c -@@ -0,0 +1,95 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/* -+ -+ @File error.c -+ -+ @Description General errors and events reporting utilities. -+*//***************************************************************************/ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+#include "error_ext.h" -+ -+ -+const char *dbgLevelStrings[] = -+{ -+ "CRITICAL" -+ ,"MAJOR" -+ ,"MINOR" -+ ,"WARNING" -+ ,"INFO" -+ ,"TRACE" -+}; -+ -+ -+char * ErrTypeStrings (e_ErrorType err) -+{ -+ switch (err) -+ { -+ case (E_OK): return "OK"; -+ case (E_WRITE_FAILED): return "Write Access Failed"; -+ case (E_NO_DEVICE): return "No Device"; -+ case (E_NOT_AVAILABLE): return "Resource Is Unavailable"; -+ case (E_NO_MEMORY): return "Memory Allocation Failed"; -+ case (E_INVALID_ADDRESS): return "Invalid Address"; -+ case (E_BUSY): return "Resource Is Busy"; -+ case (E_ALREADY_EXISTS): return "Resource Already Exists"; -+ case (E_INVALID_OPERATION): return "Invalid Operation"; -+ case (E_INVALID_VALUE): return "Invalid Value"; -+ case (E_NOT_IN_RANGE): return "Value Out Of Range"; -+ case (E_NOT_SUPPORTED): return "Unsupported Operation"; -+ case (E_INVALID_STATE): return "Invalid State"; -+ case (E_INVALID_HANDLE): return "Invalid Handle"; -+ case (E_INVALID_ID): return "Invalid ID"; -+ case (E_NULL_POINTER): return "Unexpected NULL Pointer"; -+ case (E_INVALID_SELECTION): return "Invalid Selection"; -+ case (E_INVALID_COMM_MODE): return "Invalid Communication Mode"; -+ case (E_INVALID_MEMORY_TYPE): return "Invalid Memory Type"; -+ case (E_INVALID_CLOCK): return "Invalid Clock"; -+ case (E_CONFLICT): return "Conflict In Settings"; -+ case (E_NOT_ALIGNED): return "Incorrect Alignment"; -+ case (E_NOT_FOUND): return "Resource Not Found"; -+ case (E_FULL): return "Resource Is Full"; -+ case (E_EMPTY): return "Resource Is Empty"; -+ case (E_ALREADY_FREE): return "Resource Already Free"; -+ case (E_READ_FAILED): return "Read Access Failed"; -+ case (E_INVALID_FRAME): return "Invalid Frame"; -+ case (E_SEND_FAILED): return "Send Operation Failed"; -+ case (E_RECEIVE_FAILED): return "Receive Operation Failed"; -+ case (E_TIMEOUT): return "Operation Timed Out"; -+ default: -+ break; -+ } -+ return NULL; -+} -+#endif /* (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/etc/list.c -@@ -0,0 +1,71 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ -+ @File list.c -+ -+ @Description Implementation of list. -+*//***************************************************************************/ -+#include "std_ext.h" -+#include "list_ext.h" -+ -+ -+void LIST_Append(t_List *p_NewList, t_List *p_Head) -+{ -+ t_List *p_First = LIST_FIRST(p_NewList); -+ -+ if (p_First != p_NewList) -+ { -+ t_List *p_Last = LIST_LAST(p_NewList); -+ t_List *p_Cur = LIST_NEXT(p_Head); -+ -+ LIST_PREV(p_First) = p_Head; -+ LIST_FIRST(p_Head) = p_First; -+ LIST_NEXT(p_Last) = p_Cur; -+ LIST_LAST(p_Cur) = p_Last; -+ } -+} -+ -+ -+int LIST_NumOfObjs(t_List *p_List) -+{ -+ t_List *p_Tmp; -+ int numOfObjs = 0; -+ -+ if (!LIST_IsEmpty(p_List)) -+ LIST_FOR_EACH(p_Tmp, p_List) -+ numOfObjs++; -+ -+ return numOfObjs; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/etc/memcpy.c -@@ -0,0 +1,620 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+ -+#include "std_ext.h" -+#include "xx_ext.h" -+#include "memcpy_ext.h" -+ -+void * MemCpy8(void* pDst, void* pSrc, uint32_t size) -+{ -+ int i; -+ -+ for(i = 0; i < size; ++i) -+ *(((uint8_t*)(pDst)) + i) = *(((uint8_t*)(pSrc)) + i); -+ -+ return pDst; -+} -+ -+void * MemSet8(void* pDst, int c, uint32_t size) -+{ -+ int i; -+ -+ for(i = 0; i < size; ++i) -+ *(((uint8_t*)(pDst)) + i) = (uint8_t)(c); -+ -+ return pDst; -+} -+ -+void * MemCpy32(void* pDst,void* pSrc, uint32_t size) -+{ -+ uint32_t leftAlign; -+ uint32_t rightAlign; -+ uint32_t lastWord; -+ uint32_t currWord; -+ uint32_t *p_Src32; -+ uint32_t *p_Dst32; -+ uint8_t *p_Src8; -+ uint8_t *p_Dst8; -+ -+ p_Src8 = (uint8_t*)(pSrc); -+ p_Dst8 = (uint8_t*)(pDst); -+ /* first copy byte by byte till the source first alignment -+ * this step is necessary to ensure we do not even try to access -+ * data which is before the source buffer, hence it is not ours. -+ */ -+ while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */ -+ { -+ *p_Dst8++ = *p_Src8++; -+ size--; -+ } -+ -+ /* align destination (possibly disaligning source)*/ -+ while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */ -+ { -+ *p_Dst8++ = *p_Src8++; -+ size--; -+ } -+ -+ /* dest is aligned and source is not necessarily aligned */ -+ leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */ -+ rightAlign = 32 - leftAlign; -+ -+ -+ if (leftAlign == 0) -+ { -+ /* source is also aligned */ -+ p_Src32 = (uint32_t*)(p_Src8); -+ p_Dst32 = (uint32_t*)(p_Dst8); -+ while (size >> 2) /* size >= 4 */ -+ { -+ *p_Dst32++ = *p_Src32++; -+ size -= 4; -+ } -+ p_Src8 = (uint8_t*)(p_Src32); -+ p_Dst8 = (uint8_t*)(p_Dst32); -+ } -+ else -+ { -+ /* source is not aligned (destination is aligned)*/ -+ p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3)); -+ p_Dst32 = (uint32_t*)(p_Dst8); -+ lastWord = *p_Src32++; -+ while(size >> 3) /* size >= 8 */ -+ { -+ currWord = *p_Src32; -+ *p_Dst32 = (lastWord << leftAlign) | (currWord >> rightAlign); -+ lastWord = currWord; -+ p_Src32++; -+ p_Dst32++; -+ size -= 4; -+ } -+ p_Dst8 = (uint8_t*)(p_Dst32); -+ p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3); -+ } -+ -+ /* complete the left overs */ -+ while (size--) -+ *p_Dst8++ = *p_Src8++; -+ -+ return pDst; -+} -+ -+void * IO2IOCpy32(void* pDst,void* pSrc, uint32_t size) -+{ -+ uint32_t leftAlign; -+ uint32_t rightAlign; -+ uint32_t lastWord; -+ uint32_t currWord; -+ uint32_t *p_Src32; -+ uint32_t *p_Dst32; -+ uint8_t *p_Src8; -+ uint8_t *p_Dst8; -+ -+ p_Src8 = (uint8_t*)(pSrc); -+ p_Dst8 = (uint8_t*)(pDst); -+ /* first copy byte by byte till the source first alignment -+ * this step is necessary to ensure we do not even try to access -+ * data which is before the source buffer, hence it is not ours. -+ */ -+ while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */ -+ { -+ WRITE_UINT8(*p_Dst8, GET_UINT8(*p_Src8)); -+ p_Dst8++;p_Src8++; -+ size--; -+ } -+ -+ /* align destination (possibly disaligning source)*/ -+ while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */ -+ { -+ WRITE_UINT8(*p_Dst8, GET_UINT8(*p_Src8)); -+ p_Dst8++;p_Src8++; -+ size--; -+ } -+ -+ /* dest is aligned and source is not necessarily aligned */ -+ leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */ -+ rightAlign = 32 - leftAlign; -+ -+ if (leftAlign == 0) -+ { -+ /* source is also aligned */ -+ p_Src32 = (uint32_t*)(p_Src8); -+ p_Dst32 = (uint32_t*)(p_Dst8); -+ while (size >> 2) /* size >= 4 */ -+ { -+ WRITE_UINT32(*p_Dst32, GET_UINT32(*p_Src32)); -+ p_Dst32++;p_Src32++; -+ size -= 4; -+ } -+ p_Src8 = (uint8_t*)(p_Src32); -+ p_Dst8 = (uint8_t*)(p_Dst32); -+ } -+ else -+ { -+ /* source is not aligned (destination is aligned)*/ -+ p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3)); -+ p_Dst32 = (uint32_t*)(p_Dst8); -+ lastWord = GET_UINT32(*p_Src32); -+ p_Src32++; -+ while(size >> 3) /* size >= 8 */ -+ { -+ currWord = GET_UINT32(*p_Src32); -+ WRITE_UINT32(*p_Dst32, (lastWord << leftAlign) | (currWord >> rightAlign)); -+ lastWord = currWord; -+ p_Src32++;p_Dst32++; -+ size -= 4; -+ } -+ p_Dst8 = (uint8_t*)(p_Dst32); -+ p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3); -+ } -+ -+ /* complete the left overs */ -+ while (size--) -+ { -+ WRITE_UINT8(*p_Dst8, GET_UINT8(*p_Src8)); -+ p_Dst8++;p_Src8++; -+ } -+ -+ return pDst; -+} -+ -+void * Mem2IOCpy32(void* pDst,void* pSrc, uint32_t size) -+{ -+ uint32_t leftAlign; -+ uint32_t rightAlign; -+ uint32_t lastWord; -+ uint32_t currWord; -+ uint32_t *p_Src32; -+ uint32_t *p_Dst32; -+ uint8_t *p_Src8; -+ uint8_t *p_Dst8; -+ -+ p_Src8 = (uint8_t*)(pSrc); -+ p_Dst8 = (uint8_t*)(pDst); -+ /* first copy byte by byte till the source first alignment -+ * this step is necessary to ensure we do not even try to access -+ * data which is before the source buffer, hence it is not ours. -+ */ -+ while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */ -+ { -+ WRITE_UINT8(*p_Dst8, *p_Src8); -+ p_Dst8++;p_Src8++; -+ size--; -+ } -+ -+ /* align destination (possibly disaligning source)*/ -+ while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */ -+ { -+ WRITE_UINT8(*p_Dst8, *p_Src8); -+ p_Dst8++;p_Src8++; -+ size--; -+ } -+ -+ /* dest is aligned and source is not necessarily aligned */ -+ leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */ -+ rightAlign = 32 - leftAlign; -+ -+ if (leftAlign == 0) -+ { -+ /* source is also aligned */ -+ p_Src32 = (uint32_t*)(p_Src8); -+ p_Dst32 = (uint32_t*)(p_Dst8); -+ while (size >> 2) /* size >= 4 */ -+ { -+ WRITE_UINT32(*p_Dst32, *p_Src32); -+ p_Dst32++;p_Src32++; -+ size -= 4; -+ } -+ p_Src8 = (uint8_t*)(p_Src32); -+ p_Dst8 = (uint8_t*)(p_Dst32); -+ } -+ else -+ { -+ /* source is not aligned (destination is aligned)*/ -+ p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3)); -+ p_Dst32 = (uint32_t*)(p_Dst8); -+ lastWord = *p_Src32++; -+ while(size >> 3) /* size >= 8 */ -+ { -+ currWord = *p_Src32; -+ WRITE_UINT32(*p_Dst32, (lastWord << leftAlign) | (currWord >> rightAlign)); -+ lastWord = currWord; -+ p_Src32++;p_Dst32++; -+ size -= 4; -+ } -+ p_Dst8 = (uint8_t*)(p_Dst32); -+ p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3); -+ } -+ -+ /* complete the left overs */ -+ while (size--) -+ { -+ WRITE_UINT8(*p_Dst8, *p_Src8); -+ p_Dst8++;p_Src8++; -+ } -+ -+ return pDst; -+} -+ -+void * IO2MemCpy32(void* pDst,void* pSrc, uint32_t size) -+{ -+ uint32_t leftAlign; -+ uint32_t rightAlign; -+ uint32_t lastWord; -+ uint32_t currWord; -+ uint32_t *p_Src32; -+ uint32_t *p_Dst32; -+ uint8_t *p_Src8; -+ uint8_t *p_Dst8; -+ -+ p_Src8 = (uint8_t*)(pSrc); -+ p_Dst8 = (uint8_t*)(pDst); -+ /* first copy byte by byte till the source first alignment -+ * this step is necessary to ensure we do not even try to access -+ * data which is before the source buffer, hence it is not ours. -+ */ -+ while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */ -+ { -+ *p_Dst8 = GET_UINT8(*p_Src8); -+ p_Dst8++;p_Src8++; -+ size--; -+ } -+ -+ /* align destination (possibly disaligning source)*/ -+ while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */ -+ { -+ *p_Dst8 = GET_UINT8(*p_Src8); -+ p_Dst8++;p_Src8++; -+ size--; -+ } -+ -+ /* dest is aligned and source is not necessarily aligned */ -+ leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */ -+ rightAlign = 32 - leftAlign; -+ -+ if (leftAlign == 0) -+ { -+ /* source is also aligned */ -+ p_Src32 = (uint32_t*)(p_Src8); -+ p_Dst32 = (uint32_t*)(p_Dst8); -+ while (size >> 2) /* size >= 4 */ -+ { -+ *p_Dst32 = GET_UINT32(*p_Src32); -+ p_Dst32++;p_Src32++; -+ size -= 4; -+ } -+ p_Src8 = (uint8_t*)(p_Src32); -+ p_Dst8 = (uint8_t*)(p_Dst32); -+ } -+ else -+ { -+ /* source is not aligned (destination is aligned)*/ -+ p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3)); -+ p_Dst32 = (uint32_t*)(p_Dst8); -+ lastWord = GET_UINT32(*p_Src32); -+ p_Src32++; -+ while(size >> 3) /* size >= 8 */ -+ { -+ currWord = GET_UINT32(*p_Src32); -+ *p_Dst32 = (lastWord << leftAlign) | (currWord >> rightAlign); -+ lastWord = currWord; -+ p_Src32++;p_Dst32++; -+ size -= 4; -+ } -+ p_Dst8 = (uint8_t*)(p_Dst32); -+ p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3); -+ } -+ -+ /* complete the left overs */ -+ while (size--) -+ { -+ *p_Dst8 = GET_UINT8(*p_Src8); -+ p_Dst8++;p_Src8++; -+ } -+ -+ return pDst; -+} -+ -+void * MemCpy64(void* pDst,void* pSrc, uint32_t size) -+{ -+ uint32_t leftAlign; -+ uint32_t rightAlign; -+ uint64_t lastWord; -+ uint64_t currWord; -+ uint64_t *pSrc64; -+ uint64_t *pDst64; -+ uint8_t *p_Src8; -+ uint8_t *p_Dst8; -+ -+ p_Src8 = (uint8_t*)(pSrc); -+ p_Dst8 = (uint8_t*)(pDst); -+ /* first copy byte by byte till the source first alignment -+ * this step is necessarily to ensure we do not even try to access -+ * data which is before the source buffer, hence it is not ours. -+ */ -+ while((PTR_TO_UINT(p_Src8) & 7) && size) /* (pSrc mod 8) > 0 and size > 0 */ -+ { -+ *p_Dst8++ = *p_Src8++; -+ size--; -+ } -+ -+ /* align destination (possibly disaligning source)*/ -+ while((PTR_TO_UINT(p_Dst8) & 7) && size) /* (pDst mod 8) > 0 and size > 0 */ -+ { -+ *p_Dst8++ = *p_Src8++; -+ size--; -+ } -+ -+ /* dest is aligned and source is not necessarily aligned */ -+ leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 7) << 3); /* leftAlign = (pSrc mod 8)*8 */ -+ rightAlign = 64 - leftAlign; -+ -+ -+ if (leftAlign == 0) -+ { -+ /* source is also aligned */ -+ pSrc64 = (uint64_t*)(p_Src8); -+ pDst64 = (uint64_t*)(p_Dst8); -+ while (size >> 3) /* size >= 8 */ -+ { -+ *pDst64++ = *pSrc64++; -+ size -= 8; -+ } -+ p_Src8 = (uint8_t*)(pSrc64); -+ p_Dst8 = (uint8_t*)(pDst64); -+ } -+ else -+ { -+ /* source is not aligned (destination is aligned)*/ -+ pSrc64 = (uint64_t*)(p_Src8 - (leftAlign >> 3)); -+ pDst64 = (uint64_t*)(p_Dst8); -+ lastWord = *pSrc64++; -+ while(size >> 4) /* size >= 16 */ -+ { -+ currWord = *pSrc64; -+ *pDst64 = (lastWord << leftAlign) | (currWord >> rightAlign); -+ lastWord = currWord; -+ pSrc64++; -+ pDst64++; -+ size -= 8; -+ } -+ p_Dst8 = (uint8_t*)(pDst64); -+ p_Src8 = (uint8_t*)(pSrc64) - 8 + (leftAlign >> 3); -+ } -+ -+ /* complete the left overs */ -+ while (size--) -+ *p_Dst8++ = *p_Src8++; -+ -+ return pDst; -+} -+ -+void * MemSet32(void* pDst, uint8_t val, uint32_t size) -+{ -+ uint32_t val32; -+ uint32_t *p_Dst32; -+ uint8_t *p_Dst8; -+ -+ p_Dst8 = (uint8_t*)(pDst); -+ -+ /* generate four 8-bit val's in 32-bit container */ -+ val32 = (uint32_t) val; -+ val32 |= (val32 << 8); -+ val32 |= (val32 << 16); -+ -+ /* align destination to 32 */ -+ while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */ -+ { -+ *p_Dst8++ = val; -+ size--; -+ } -+ -+ /* 32-bit chunks */ -+ p_Dst32 = (uint32_t*)(p_Dst8); -+ while (size >> 2) /* size >= 4 */ -+ { -+ *p_Dst32++ = val32; -+ size -= 4; -+ } -+ -+ /* complete the leftovers */ -+ p_Dst8 = (uint8_t*)(p_Dst32); -+ while (size--) -+ *p_Dst8++ = val; -+ -+ return pDst; -+} -+ -+void * IOMemSet32(void* pDst, uint8_t val, uint32_t size) -+{ -+ uint32_t val32; -+ uint32_t *p_Dst32; -+ uint8_t *p_Dst8; -+ -+ p_Dst8 = (uint8_t*)(pDst); -+ -+ /* generate four 8-bit val's in 32-bit container */ -+ val32 = (uint32_t) val; -+ val32 |= (val32 << 8); -+ val32 |= (val32 << 16); -+ -+ /* align destination to 32 */ -+ while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */ -+ { -+ WRITE_UINT8(*p_Dst8, val); -+ p_Dst8++; -+ size--; -+ } -+ -+ /* 32-bit chunks */ -+ p_Dst32 = (uint32_t*)(p_Dst8); -+ while (size >> 2) /* size >= 4 */ -+ { -+ WRITE_UINT32(*p_Dst32, val32); -+ p_Dst32++; -+ size -= 4; -+ } -+ -+ /* complete the leftovers */ -+ p_Dst8 = (uint8_t*)(p_Dst32); -+ while (size--) -+ { -+ WRITE_UINT8(*p_Dst8, val); -+ p_Dst8++; -+ } -+ -+ return pDst; -+} -+ -+void * MemSet64(void* pDst, uint8_t val, uint32_t size) -+{ -+ uint64_t val64; -+ uint64_t *pDst64; -+ uint8_t *p_Dst8; -+ -+ p_Dst8 = (uint8_t*)(pDst); -+ -+ /* generate four 8-bit val's in 32-bit container */ -+ val64 = (uint64_t) val; -+ val64 |= (val64 << 8); -+ val64 |= (val64 << 16); -+ val64 |= (val64 << 24); -+ val64 |= (val64 << 32); -+ -+ /* align destination to 64 */ -+ while((PTR_TO_UINT(p_Dst8) & 7) && size) /* (pDst mod 8) > 0 and size > 0 */ -+ { -+ *p_Dst8++ = val; -+ size--; -+ } -+ -+ /* 64-bit chunks */ -+ pDst64 = (uint64_t*)(p_Dst8); -+ while (size >> 4) /* size >= 8 */ -+ { -+ *pDst64++ = val64; -+ size -= 8; -+ } -+ -+ /* complete the leftovers */ -+ p_Dst8 = (uint8_t*)(pDst64); -+ while (size--) -+ *p_Dst8++ = val; -+ -+ return pDst; -+} -+ -+void MemDisp(uint8_t *p, int size) -+{ -+ uint32_t space = (uint32_t)(PTR_TO_UINT(p) & 0x3); -+ uint8_t *p_Limit; -+ -+ if (space) -+ { -+ p_Limit = (p - space + 4); -+ -+ XX_Print("0x%08X: ", (p - space)); -+ -+ while (space--) -+ { -+ XX_Print("--"); -+ } -+ while (size && (p < p_Limit)) -+ { -+ XX_Print("%02x", *(uint8_t*)p); -+ size--; -+ p++; -+ } -+ -+ XX_Print(" "); -+ p_Limit += 12; -+ -+ while ((size > 3) && (p < p_Limit)) -+ { -+ XX_Print("%08x ", *(uint32_t*)p); -+ size -= 4; -+ p += 4; -+ } -+ XX_Print("\r\n"); -+ } -+ -+ while (size > 15) -+ { -+ XX_Print("0x%08X: %08x %08x %08x %08x\r\n", -+ p, *(uint32_t *)p, *(uint32_t *)(p + 4), -+ *(uint32_t *)(p + 8), *(uint32_t *)(p + 12)); -+ size -= 16; -+ p += 16; -+ } -+ -+ if (size) -+ { -+ XX_Print("0x%08X: ", p); -+ -+ while (size > 3) -+ { -+ XX_Print("%08x ", *(uint32_t *)p); -+ size -= 4; -+ p += 4; -+ } -+ while (size) -+ { -+ XX_Print("%02x", *(uint8_t *)p); -+ size--; -+ p++; -+ } -+ -+ XX_Print("\r\n"); -+ } -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/etc/mm.c -@@ -0,0 +1,1155 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include "string_ext.h" -+#include "error_ext.h" -+#include "std_ext.h" -+#include "part_ext.h" -+#include "xx_ext.h" -+ -+#include "mm.h" -+ -+ -+ -+ -+/********************************************************************** -+ * MM internal routines set * -+ **********************************************************************/ -+ -+/**************************************************************** -+ * Routine: CreateBusyBlock -+ * -+ * Description: -+ * Initializes a new busy block of "size" bytes and started -+ * rom "base" address. Each busy block has a name that -+ * specified the purpose of the memory allocation. -+ * -+ * Arguments: -+ * base - base address of the busy block -+ * size - size of the busy block -+ * name - name that specified the busy block -+ * -+ * Return value: -+ * A pointer to new created structure returned on success; -+ * Otherwise, NULL. -+ ****************************************************************/ -+static t_BusyBlock * CreateBusyBlock(uint64_t base, uint64_t size, char *name) -+{ -+ t_BusyBlock *p_BusyBlock; -+ uint32_t n; -+ -+ p_BusyBlock = (t_BusyBlock *)XX_Malloc(sizeof(t_BusyBlock)); -+ if ( !p_BusyBlock ) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ return NULL; -+ } -+ -+ p_BusyBlock->base = base; -+ p_BusyBlock->end = base + size; -+ -+ n = strlen(name); -+ if (n >= MM_MAX_NAME_LEN) -+ n = MM_MAX_NAME_LEN - 1; -+ strncpy(p_BusyBlock->name, name, MM_MAX_NAME_LEN-1); -+ p_BusyBlock->name[n] = '\0'; -+ p_BusyBlock->p_Next = 0; -+ -+ return p_BusyBlock; -+} -+ -+/**************************************************************** -+ * Routine: CreateNewBlock -+ * -+ * Description: -+ * Initializes a new memory block of "size" bytes and started -+ * from "base" address. -+ * -+ * Arguments: -+ * base - base address of the memory block -+ * size - size of the memory block -+ * -+ * Return value: -+ * A pointer to new created structure returned on success; -+ * Otherwise, NULL. -+ ****************************************************************/ -+static t_MemBlock * CreateNewBlock(uint64_t base, uint64_t size) -+{ -+ t_MemBlock *p_MemBlock; -+ -+ p_MemBlock = (t_MemBlock *)XX_Malloc(sizeof(t_MemBlock)); -+ if ( !p_MemBlock ) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ return NULL; -+ } -+ -+ p_MemBlock->base = base; -+ p_MemBlock->end = base+size; -+ p_MemBlock->p_Next = 0; -+ -+ return p_MemBlock; -+} -+ -+/**************************************************************** -+ * Routine: CreateFreeBlock -+ * -+ * Description: -+ * Initializes a new free block of of "size" bytes and -+ * started from "base" address. -+ * -+ * Arguments: -+ * base - base address of the free block -+ * size - size of the free block -+ * -+ * Return value: -+ * A pointer to new created structure returned on success; -+ * Otherwise, NULL. -+ ****************************************************************/ -+static t_FreeBlock * CreateFreeBlock(uint64_t base, uint64_t size) -+{ -+ t_FreeBlock *p_FreeBlock; -+ -+ p_FreeBlock = (t_FreeBlock *)XX_Malloc(sizeof(t_FreeBlock)); -+ if ( !p_FreeBlock ) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ return NULL; -+ } -+ -+ p_FreeBlock->base = base; -+ p_FreeBlock->end = base + size; -+ p_FreeBlock->p_Next = 0; -+ -+ return p_FreeBlock; -+} -+ -+/**************************************************************** -+ * Routine: AddFree -+ * -+ * Description: -+ * Adds a new free block to the free lists. It updates each -+ * free list to include a new free block. -+ * Note, that all free block in each free list are ordered -+ * by their base address. -+ * -+ * Arguments: -+ * p_MM - pointer to the MM object -+ * base - base address of a given free block -+ * end - end address of a given free block -+ * -+ * Return value: -+ * -+ * -+ ****************************************************************/ -+static t_Error AddFree(t_MM *p_MM, uint64_t base, uint64_t end) -+{ -+ t_FreeBlock *p_PrevB, *p_CurrB, *p_NewB; -+ uint64_t alignment; -+ uint64_t alignBase; -+ int i; -+ -+ /* Updates free lists to include a just released block */ -+ for (i=0; i <= MM_MAX_ALIGNMENT; i++) -+ { -+ p_PrevB = p_NewB = 0; -+ p_CurrB = p_MM->freeBlocks[i]; -+ -+ alignment = (uint64_t)(0x1 << i); -+ alignBase = MAKE_ALIGNED(base, alignment); -+ -+ /* Goes to the next free list if there is no block to free */ -+ if (alignBase >= end) -+ continue; -+ -+ /* Looks for a free block that should be updated */ -+ while ( p_CurrB ) -+ { -+ if ( alignBase <= p_CurrB->end ) -+ { -+ if ( end > p_CurrB->end ) -+ { -+ t_FreeBlock *p_NextB; -+ while ( p_CurrB->p_Next && end > p_CurrB->p_Next->end ) -+ { -+ p_NextB = p_CurrB->p_Next; -+ p_CurrB->p_Next = p_CurrB->p_Next->p_Next; -+ XX_Free(p_NextB); -+ } -+ -+ p_NextB = p_CurrB->p_Next; -+ if ( !p_NextB || (p_NextB && end < p_NextB->base) ) -+ { -+ p_CurrB->end = end; -+ } -+ else -+ { -+ p_CurrB->end = p_NextB->end; -+ p_CurrB->p_Next = p_NextB->p_Next; -+ XX_Free(p_NextB); -+ } -+ } -+ else if ( (end < p_CurrB->base) && ((end-alignBase) >= alignment) ) -+ { -+ if ((p_NewB = CreateFreeBlock(alignBase, end-alignBase)) == NULL) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ -+ p_NewB->p_Next = p_CurrB; -+ if (p_PrevB) -+ p_PrevB->p_Next = p_NewB; -+ else -+ p_MM->freeBlocks[i] = p_NewB; -+ break; -+ } -+ -+ if ((alignBase < p_CurrB->base) && (end >= p_CurrB->base)) -+ { -+ p_CurrB->base = alignBase; -+ } -+ -+ /* if size of the free block is less then alignment -+ * deletes that free block from the free list. */ -+ if ( (p_CurrB->end - p_CurrB->base) < alignment) -+ { -+ if ( p_PrevB ) -+ p_PrevB->p_Next = p_CurrB->p_Next; -+ else -+ p_MM->freeBlocks[i] = p_CurrB->p_Next; -+ XX_Free(p_CurrB); -+ p_CurrB = NULL; -+ } -+ break; -+ } -+ else -+ { -+ p_PrevB = p_CurrB; -+ p_CurrB = p_CurrB->p_Next; -+ } -+ } -+ -+ /* If no free block found to be updated, insert a new free block -+ * to the end of the free list. -+ */ -+ if ( !p_CurrB && ((((uint64_t)(end-base)) & ((uint64_t)(alignment-1))) == 0) ) -+ { -+ if ((p_NewB = CreateFreeBlock(alignBase, end-base)) == NULL) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ -+ if (p_PrevB) -+ p_PrevB->p_Next = p_NewB; -+ else -+ p_MM->freeBlocks[i] = p_NewB; -+ } -+ -+ /* Update boundaries of the new free block */ -+ if ((alignment == 1) && !p_NewB) -+ { -+ if ( p_CurrB && base > p_CurrB->base ) -+ base = p_CurrB->base; -+ if ( p_CurrB && end < p_CurrB->end ) -+ end = p_CurrB->end; -+ } -+ } -+ -+ return (E_OK); -+} -+ -+/**************************************************************** -+ * Routine: CutFree -+ * -+ * Description: -+ * Cuts a free block from holdBase to holdEnd from the free lists. -+ * That is, it updates all free lists of the MM object do -+ * not include a block of memory from holdBase to holdEnd. -+ * For each free lists it seek for a free block that holds -+ * either holdBase or holdEnd. If such block is found it updates it. -+ * -+ * Arguments: -+ * p_MM - pointer to the MM object -+ * holdBase - base address of the allocated block -+ * holdEnd - end address of the allocated block -+ * -+ * Return value: -+ * E_OK is returned on success, -+ * otherwise returns an error code. -+ * -+ ****************************************************************/ -+static t_Error CutFree(t_MM *p_MM, uint64_t holdBase, uint64_t holdEnd) -+{ -+ t_FreeBlock *p_PrevB, *p_CurrB, *p_NewB; -+ uint64_t alignBase, base, end; -+ uint64_t alignment; -+ int i; -+ -+ for (i=0; i <= MM_MAX_ALIGNMENT; i++) -+ { -+ p_PrevB = p_NewB = 0; -+ p_CurrB = p_MM->freeBlocks[i]; -+ -+ alignment = (uint64_t)(0x1 << i); -+ alignBase = MAKE_ALIGNED(holdEnd, alignment); -+ -+ while ( p_CurrB ) -+ { -+ base = p_CurrB->base; -+ end = p_CurrB->end; -+ -+ if ( (holdBase <= base) && (holdEnd <= end) && (holdEnd > base) ) -+ { -+ if ( alignBase >= end || -+ (alignBase < end && ((end-alignBase) < alignment)) ) -+ { -+ if (p_PrevB) -+ p_PrevB->p_Next = p_CurrB->p_Next; -+ else -+ p_MM->freeBlocks[i] = p_CurrB->p_Next; -+ XX_Free(p_CurrB); -+ } -+ else -+ { -+ p_CurrB->base = alignBase; -+ } -+ break; -+ } -+ else if ( (holdBase > base) && (holdEnd <= end) ) -+ { -+ if ( (holdBase-base) >= alignment ) -+ { -+ if ( (alignBase < end) && ((end-alignBase) >= alignment) ) -+ { -+ if ((p_NewB = CreateFreeBlock(alignBase, end-alignBase)) == NULL) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ p_NewB->p_Next = p_CurrB->p_Next; -+ p_CurrB->p_Next = p_NewB; -+ } -+ p_CurrB->end = holdBase; -+ } -+ else if ( (alignBase < end) && ((end-alignBase) >= alignment) ) -+ { -+ p_CurrB->base = alignBase; -+ } -+ else -+ { -+ if (p_PrevB) -+ p_PrevB->p_Next = p_CurrB->p_Next; -+ else -+ p_MM->freeBlocks[i] = p_CurrB->p_Next; -+ XX_Free(p_CurrB); -+ } -+ break; -+ } -+ else -+ { -+ p_PrevB = p_CurrB; -+ p_CurrB = p_CurrB->p_Next; -+ } -+ } -+ } -+ -+ return (E_OK); -+} -+ -+/**************************************************************** -+ * Routine: AddBusy -+ * -+ * Description: -+ * Adds a new busy block to the list of busy blocks. Note, -+ * that all busy blocks are ordered by their base address in -+ * the busy list. -+ * -+ * Arguments: -+ * MM - handler to the MM object -+ * p_NewBusyB - pointer to the a busy block -+ * -+ * Return value: -+ * None. -+ * -+ ****************************************************************/ -+static void AddBusy(t_MM *p_MM, t_BusyBlock *p_NewBusyB) -+{ -+ t_BusyBlock *p_CurrBusyB, *p_PrevBusyB; -+ -+ /* finds a place of a new busy block in the list of busy blocks */ -+ p_PrevBusyB = 0; -+ p_CurrBusyB = p_MM->busyBlocks; -+ -+ while ( p_CurrBusyB && p_NewBusyB->base > p_CurrBusyB->base ) -+ { -+ p_PrevBusyB = p_CurrBusyB; -+ p_CurrBusyB = p_CurrBusyB->p_Next; -+ } -+ -+ /* insert the new busy block into the list of busy blocks */ -+ if ( p_CurrBusyB ) -+ p_NewBusyB->p_Next = p_CurrBusyB; -+ if ( p_PrevBusyB ) -+ p_PrevBusyB->p_Next = p_NewBusyB; -+ else -+ p_MM->busyBlocks = p_NewBusyB; -+} -+ -+/**************************************************************** -+ * Routine: CutBusy -+ * -+ * Description: -+ * Cuts a block from base to end from the list of busy blocks. -+ * This is done by updating the list of busy blocks do not -+ * include a given block, that block is going to be free. If a -+ * given block is a part of some other busy block, so that -+ * busy block is updated. If there are number of busy blocks -+ * included in the given block, so all that blocks are removed -+ * from the busy list and the end blocks are updated. -+ * If the given block devides some block into two parts, a new -+ * busy block is added to the busy list. -+ * -+ * Arguments: -+ * p_MM - pointer to the MM object -+ * base - base address of a given busy block -+ * end - end address of a given busy block -+ * -+ * Return value: -+ * E_OK on success, E_NOMEMORY otherwise. -+ * -+ ****************************************************************/ -+static t_Error CutBusy(t_MM *p_MM, uint64_t base, uint64_t end) -+{ -+ t_BusyBlock *p_CurrB, *p_PrevB, *p_NewB; -+ -+ p_CurrB = p_MM->busyBlocks; -+ p_PrevB = p_NewB = 0; -+ -+ while ( p_CurrB ) -+ { -+ if ( base < p_CurrB->end ) -+ { -+ if ( end > p_CurrB->end ) -+ { -+ t_BusyBlock *p_NextB; -+ while ( p_CurrB->p_Next && end >= p_CurrB->p_Next->end ) -+ { -+ p_NextB = p_CurrB->p_Next; -+ p_CurrB->p_Next = p_CurrB->p_Next->p_Next; -+ XX_Free(p_NextB); -+ } -+ -+ p_NextB = p_CurrB->p_Next; -+ if ( p_NextB && end > p_NextB->base ) -+ { -+ p_NextB->base = end; -+ } -+ } -+ -+ if ( base <= p_CurrB->base ) -+ { -+ if ( end < p_CurrB->end && end > p_CurrB->base ) -+ { -+ p_CurrB->base = end; -+ } -+ else if ( end >= p_CurrB->end ) -+ { -+ if ( p_PrevB ) -+ p_PrevB->p_Next = p_CurrB->p_Next; -+ else -+ p_MM->busyBlocks = p_CurrB->p_Next; -+ XX_Free(p_CurrB); -+ } -+ } -+ else -+ { -+ if ( end < p_CurrB->end && end > p_CurrB->base ) -+ { -+ if ((p_NewB = CreateBusyBlock(end, -+ p_CurrB->end-end, -+ p_CurrB->name)) == NULL) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ p_NewB->p_Next = p_CurrB->p_Next; -+ p_CurrB->p_Next = p_NewB; -+ } -+ p_CurrB->end = base; -+ } -+ break; -+ } -+ else -+ { -+ p_PrevB = p_CurrB; -+ p_CurrB = p_CurrB->p_Next; -+ } -+ } -+ -+ return (E_OK); -+} -+ -+/**************************************************************** -+ * Routine: MmGetGreaterAlignment -+ * -+ * Description: -+ * Allocates a block of memory according to the given size -+ * and the alignment. That routine is called from the MM_Get -+ * routine if the required alignment is greater then MM_MAX_ALIGNMENT. -+ * In that case, it goes over free blocks of 64 byte align list -+ * and checks if it has the required size of bytes of the required -+ * alignment. If no blocks found returns ILLEGAL_BASE. -+ * After the block is found and data is allocated, it calls -+ * the internal CutFree routine to update all free lists -+ * do not include a just allocated block. Of course, each -+ * free list contains a free blocks with the same alignment. -+ * It is also creates a busy block that holds -+ * information about an allocated block. -+ * -+ * Arguments: -+ * MM - handle to the MM object -+ * size - size of the MM -+ * alignment - index as a power of two defines -+ * a required alignment that is greater then 64. -+ * name - the name that specifies an allocated block. -+ * -+ * Return value: -+ * base address of an allocated block. -+ * ILLEGAL_BASE if can't allocate a block -+ * -+ ****************************************************************/ -+static uint64_t MmGetGreaterAlignment(t_MM *p_MM, uint64_t size, uint64_t alignment, char* name) -+{ -+ t_FreeBlock *p_FreeB; -+ t_BusyBlock *p_NewBusyB; -+ uint64_t holdBase, holdEnd, alignBase = 0; -+ -+ /* goes over free blocks of the 64 byte alignment list -+ and look for a block of the suitable size and -+ base address according to the alignment. */ -+ p_FreeB = p_MM->freeBlocks[MM_MAX_ALIGNMENT]; -+ -+ while ( p_FreeB ) -+ { -+ alignBase = MAKE_ALIGNED(p_FreeB->base, alignment); -+ -+ /* the block is found if the aligned base inside the block -+ * and has the anough size. */ -+ if ( alignBase >= p_FreeB->base && -+ alignBase < p_FreeB->end && -+ size <= (p_FreeB->end - alignBase) ) -+ break; -+ else -+ p_FreeB = p_FreeB->p_Next; -+ } -+ -+ /* If such block isn't found */ -+ if ( !p_FreeB ) -+ return (uint64_t)(ILLEGAL_BASE); -+ -+ holdBase = alignBase; -+ holdEnd = alignBase + size; -+ -+ /* init a new busy block */ -+ if ((p_NewBusyB = CreateBusyBlock(holdBase, size, name)) == NULL) -+ return (uint64_t)(ILLEGAL_BASE); -+ -+ /* calls Update routine to update a lists of free blocks */ -+ if ( CutFree ( p_MM, holdBase, holdEnd ) != E_OK ) -+ { -+ XX_Free(p_NewBusyB); -+ return (uint64_t)(ILLEGAL_BASE); -+ } -+ -+ /* insert the new busy block into the list of busy blocks */ -+ AddBusy ( p_MM, p_NewBusyB ); -+ -+ return (holdBase); -+} -+ -+ -+/********************************************************************** -+ * MM API routines set * -+ **********************************************************************/ -+ -+/*****************************************************************************/ -+t_Error MM_Init(t_Handle *h_MM, uint64_t base, uint64_t size) -+{ -+ t_MM *p_MM; -+ uint64_t newBase, newSize; -+ int i; -+ -+ if (!size) -+ { -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Size (should be positive)")); -+ } -+ -+ /* Initializes a new MM object */ -+ p_MM = (t_MM *)XX_Malloc(sizeof(t_MM)); -+ if (!p_MM) -+ { -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ } -+ -+ p_MM->h_Spinlock = XX_InitSpinlock(); -+ if (!p_MM->h_Spinlock) -+ { -+ XX_Free(p_MM); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, ("MM spinlock!")); -+ } -+ -+ /* Initializes counter of free memory to total size */ -+ p_MM->freeMemSize = size; -+ -+ /* A busy list is empty */ -+ p_MM->busyBlocks = 0; -+ -+ /* Initializes a new memory block */ -+ if ((p_MM->memBlocks = CreateNewBlock(base, size)) == NULL) -+ { -+ MM_Free(p_MM); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ } -+ -+ /* Initializes a new free block for each free list*/ -+ for (i=0; i <= MM_MAX_ALIGNMENT; i++) -+ { -+ newBase = MAKE_ALIGNED( base, (0x1 << i) ); -+ newSize = size - (newBase - base); -+ -+ if ((p_MM->freeBlocks[i] = CreateFreeBlock(newBase, newSize)) == NULL) -+ { -+ MM_Free(p_MM); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ } -+ } -+ -+ *h_MM = p_MM; -+ -+ return (E_OK); -+} -+ -+/*****************************************************************************/ -+void MM_Free(t_Handle h_MM) -+{ -+ t_MM *p_MM = (t_MM *)h_MM; -+ t_MemBlock *p_MemBlock; -+ t_BusyBlock *p_BusyBlock; -+ t_FreeBlock *p_FreeBlock; -+ void *p_Block; -+ int i; -+ -+ ASSERT_COND(p_MM); -+ -+ /* release memory allocated for busy blocks */ -+ p_BusyBlock = p_MM->busyBlocks; -+ while ( p_BusyBlock ) -+ { -+ p_Block = p_BusyBlock; -+ p_BusyBlock = p_BusyBlock->p_Next; -+ XX_Free(p_Block); -+ } -+ -+ /* release memory allocated for free blocks */ -+ for (i=0; i <= MM_MAX_ALIGNMENT; i++) -+ { -+ p_FreeBlock = p_MM->freeBlocks[i]; -+ while ( p_FreeBlock ) -+ { -+ p_Block = p_FreeBlock; -+ p_FreeBlock = p_FreeBlock->p_Next; -+ XX_Free(p_Block); -+ } -+ } -+ -+ /* release memory allocated for memory blocks */ -+ p_MemBlock = p_MM->memBlocks; -+ while ( p_MemBlock ) -+ { -+ p_Block = p_MemBlock; -+ p_MemBlock = p_MemBlock->p_Next; -+ XX_Free(p_Block); -+ } -+ -+ if (p_MM->h_Spinlock) -+ XX_FreeSpinlock(p_MM->h_Spinlock); -+ -+ /* release memory allocated for MM object itself */ -+ XX_Free(p_MM); -+} -+ -+/*****************************************************************************/ -+uint64_t MM_Get(t_Handle h_MM, uint64_t size, uint64_t alignment, char* name) -+{ -+ t_MM *p_MM = (t_MM *)h_MM; -+ t_FreeBlock *p_FreeB; -+ t_BusyBlock *p_NewBusyB; -+ uint64_t holdBase, holdEnd, j, i = 0; -+ uint32_t intFlags; -+ -+ SANITY_CHECK_RETURN_VALUE(p_MM, E_INVALID_HANDLE, (uint64_t)ILLEGAL_BASE); -+ -+ /* checks that alignment value is greater then zero */ -+ if (alignment == 0) -+ { -+ alignment = 1; -+ } -+ -+ j = alignment; -+ -+ /* checks if alignment is a power of two, if it correct and if the -+ required size is multiple of the given alignment. */ -+ while ((j & 0x1) == 0) -+ { -+ i++; -+ j = j >> 1; -+ } -+ -+ /* if the given alignment isn't power of two, returns an error */ -+ if (j != 1) -+ { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("alignment (should be power of 2)")); -+ return (uint64_t)ILLEGAL_BASE; -+ } -+ -+ if (i > MM_MAX_ALIGNMENT) -+ { -+ return (MmGetGreaterAlignment(p_MM, size, alignment, name)); -+ } -+ -+ intFlags = XX_LockIntrSpinlock(p_MM->h_Spinlock); -+ /* look for a block of the size greater or equal to the required size. */ -+ p_FreeB = p_MM->freeBlocks[i]; -+ while ( p_FreeB && (p_FreeB->end - p_FreeB->base) < size ) -+ p_FreeB = p_FreeB->p_Next; -+ -+ /* If such block is found */ -+ if ( !p_FreeB ) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ return (uint64_t)(ILLEGAL_BASE); -+ } -+ -+ holdBase = p_FreeB->base; -+ holdEnd = holdBase + size; -+ -+ /* init a new busy block */ -+ if ((p_NewBusyB = CreateBusyBlock(holdBase, size, name)) == NULL) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ return (uint64_t)(ILLEGAL_BASE); -+ } -+ -+ /* calls Update routine to update a lists of free blocks */ -+ if ( CutFree ( p_MM, holdBase, holdEnd ) != E_OK ) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ XX_Free(p_NewBusyB); -+ return (uint64_t)(ILLEGAL_BASE); -+ } -+ -+ /* Decreasing the allocated memory size from free memory size */ -+ p_MM->freeMemSize -= size; -+ -+ /* insert the new busy block into the list of busy blocks */ -+ AddBusy ( p_MM, p_NewBusyB ); -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ -+ return (holdBase); -+} -+ -+/*****************************************************************************/ -+uint64_t MM_GetForce(t_Handle h_MM, uint64_t base, uint64_t size, char* name) -+{ -+ t_MM *p_MM = (t_MM *)h_MM; -+ t_FreeBlock *p_FreeB; -+ t_BusyBlock *p_NewBusyB; -+ uint32_t intFlags; -+ bool blockIsFree = FALSE; -+ -+ ASSERT_COND(p_MM); -+ -+ intFlags = XX_LockIntrSpinlock(p_MM->h_Spinlock); -+ p_FreeB = p_MM->freeBlocks[0]; /* The biggest free blocks are in the -+ free list with alignment 1 */ -+ -+ while ( p_FreeB ) -+ { -+ if ( base >= p_FreeB->base && (base+size) <= p_FreeB->end ) -+ { -+ blockIsFree = TRUE; -+ break; -+ } -+ else -+ p_FreeB = p_FreeB->p_Next; -+ } -+ -+ if ( !blockIsFree ) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ return (uint64_t)(ILLEGAL_BASE); -+ } -+ -+ /* init a new busy block */ -+ if ((p_NewBusyB = CreateBusyBlock(base, size, name)) == NULL) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ return (uint64_t)(ILLEGAL_BASE); -+ } -+ -+ /* calls Update routine to update a lists of free blocks */ -+ if ( CutFree ( p_MM, base, base+size ) != E_OK ) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ XX_Free(p_NewBusyB); -+ return (uint64_t)(ILLEGAL_BASE); -+ } -+ -+ /* Decreasing the allocated memory size from free memory size */ -+ p_MM->freeMemSize -= size; -+ -+ /* insert the new busy block into the list of busy blocks */ -+ AddBusy ( p_MM, p_NewBusyB ); -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ -+ return (base); -+} -+ -+/*****************************************************************************/ -+uint64_t MM_GetForceMin(t_Handle h_MM, uint64_t size, uint64_t alignment, uint64_t min, char* name) -+{ -+ t_MM *p_MM = (t_MM *)h_MM; -+ t_FreeBlock *p_FreeB; -+ t_BusyBlock *p_NewBusyB; -+ uint64_t holdBase, holdEnd, j = alignment, i=0; -+ uint32_t intFlags; -+ -+ ASSERT_COND(p_MM); -+ -+ /* checks if alignment is a power of two, if it correct and if the -+ required size is multiple of the given alignment. */ -+ while ((j & 0x1) == 0) -+ { -+ i++; -+ j = j >> 1; -+ } -+ -+ if ( (j != 1) || (i > MM_MAX_ALIGNMENT) ) -+ { -+ return (uint64_t)(ILLEGAL_BASE); -+ } -+ -+ intFlags = XX_LockIntrSpinlock(p_MM->h_Spinlock); -+ p_FreeB = p_MM->freeBlocks[i]; -+ -+ /* look for the first block that contains the minimum -+ base address. If the whole required size may be fit -+ into it, use that block, otherwise look for the next -+ block of size greater or equal to the required size. */ -+ while ( p_FreeB && (min >= p_FreeB->end)) -+ p_FreeB = p_FreeB->p_Next; -+ -+ /* If such block is found */ -+ if ( !p_FreeB ) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ return (uint64_t)(ILLEGAL_BASE); -+ } -+ -+ /* if this block is large enough, use this block */ -+ holdBase = ( min <= p_FreeB->base ) ? p_FreeB->base : min; -+ if ((holdBase + size) <= p_FreeB->end ) -+ { -+ holdEnd = holdBase + size; -+ } -+ else -+ { -+ p_FreeB = p_FreeB->p_Next; -+ while ( p_FreeB && ((p_FreeB->end - p_FreeB->base) < size) ) -+ p_FreeB = p_FreeB->p_Next; -+ -+ /* If such block is found */ -+ if ( !p_FreeB ) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ return (uint64_t)(ILLEGAL_BASE); -+ } -+ -+ holdBase = p_FreeB->base; -+ holdEnd = holdBase + size; -+ } -+ -+ /* init a new busy block */ -+ if ((p_NewBusyB = CreateBusyBlock(holdBase, size, name)) == NULL) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ return (uint64_t)(ILLEGAL_BASE); -+ } -+ -+ /* calls Update routine to update a lists of free blocks */ -+ if ( CutFree( p_MM, holdBase, holdEnd ) != E_OK ) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ XX_Free(p_NewBusyB); -+ return (uint64_t)(ILLEGAL_BASE); -+ } -+ -+ /* Decreasing the allocated memory size from free memory size */ -+ p_MM->freeMemSize -= size; -+ -+ /* insert the new busy block into the list of busy blocks */ -+ AddBusy( p_MM, p_NewBusyB ); -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ -+ return (holdBase); -+} -+ -+/*****************************************************************************/ -+uint64_t MM_Put(t_Handle h_MM, uint64_t base) -+{ -+ t_MM *p_MM = (t_MM *)h_MM; -+ t_BusyBlock *p_BusyB, *p_PrevBusyB; -+ uint64_t size; -+ uint32_t intFlags; -+ -+ ASSERT_COND(p_MM); -+ -+ /* Look for a busy block that have the given base value. -+ * That block will be returned back to the memory. -+ */ -+ p_PrevBusyB = 0; -+ -+ intFlags = XX_LockIntrSpinlock(p_MM->h_Spinlock); -+ p_BusyB = p_MM->busyBlocks; -+ while ( p_BusyB && base != p_BusyB->base ) -+ { -+ p_PrevBusyB = p_BusyB; -+ p_BusyB = p_BusyB->p_Next; -+ } -+ -+ if ( !p_BusyB ) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ return (uint64_t)(0); -+ } -+ -+ if ( AddFree( p_MM, p_BusyB->base, p_BusyB->end ) != E_OK ) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ return (uint64_t)(0); -+ } -+ -+ /* removes a busy block form the list of busy blocks */ -+ if ( p_PrevBusyB ) -+ p_PrevBusyB->p_Next = p_BusyB->p_Next; -+ else -+ p_MM->busyBlocks = p_BusyB->p_Next; -+ -+ size = p_BusyB->end - p_BusyB->base; -+ -+ /* Adding the deallocated memory size to free memory size */ -+ p_MM->freeMemSize += size; -+ -+ XX_Free(p_BusyB); -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ -+ return (size); -+} -+ -+/*****************************************************************************/ -+uint64_t MM_PutForce(t_Handle h_MM, uint64_t base, uint64_t size) -+{ -+ t_MM *p_MM = (t_MM *)h_MM; -+ uint64_t end = base + size; -+ uint32_t intFlags; -+ -+ ASSERT_COND(p_MM); -+ -+ intFlags = XX_LockIntrSpinlock(p_MM->h_Spinlock); -+ -+ if ( CutBusy( p_MM, base, end ) != E_OK ) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ return (uint64_t)(0); -+ } -+ -+ if ( AddFree ( p_MM, base, end ) != E_OK ) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ return (uint64_t)(0); -+ } -+ -+ /* Adding the deallocated memory size to free memory size */ -+ p_MM->freeMemSize += size; -+ -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ -+ return (size); -+} -+ -+/*****************************************************************************/ -+t_Error MM_Add(t_Handle h_MM, uint64_t base, uint64_t size) -+{ -+ t_MM *p_MM = (t_MM *)h_MM; -+ t_MemBlock *p_MemB, *p_NewMemB; -+ t_Error errCode; -+ uint32_t intFlags; -+ -+ ASSERT_COND(p_MM); -+ -+ /* find a last block in the list of memory blocks to insert a new -+ * memory block -+ */ -+ intFlags = XX_LockIntrSpinlock(p_MM->h_Spinlock); -+ -+ p_MemB = p_MM->memBlocks; -+ while ( p_MemB->p_Next ) -+ { -+ if ( base >= p_MemB->base && base < p_MemB->end ) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ RETURN_ERROR(MAJOR, E_ALREADY_EXISTS, NO_MSG); -+ } -+ p_MemB = p_MemB->p_Next; -+ } -+ /* check for a last memory block */ -+ if ( base >= p_MemB->base && base < p_MemB->end ) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ RETURN_ERROR(MAJOR, E_ALREADY_EXISTS, NO_MSG); -+ } -+ -+ /* create a new memory block */ -+ if ((p_NewMemB = CreateNewBlock(base, size)) == NULL) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ } -+ -+ /* append a new memory block to the end of the list of memory blocks */ -+ p_MemB->p_Next = p_NewMemB; -+ -+ /* add a new free block to the free lists */ -+ errCode = AddFree(p_MM, base, base+size); -+ if (errCode) -+ { -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ p_MemB->p_Next = 0; -+ XX_Free(p_NewMemB); -+ return ((t_Error)errCode); -+ } -+ -+ /* Adding the new block size to free memory size */ -+ p_MM->freeMemSize += size; -+ -+ XX_UnlockIntrSpinlock(p_MM->h_Spinlock, intFlags); -+ -+ return (E_OK); -+} -+ -+/*****************************************************************************/ -+uint64_t MM_GetMemBlock(t_Handle h_MM, int index) -+{ -+ t_MM *p_MM = (t_MM*)h_MM; -+ t_MemBlock *p_MemBlock; -+ int i; -+ -+ ASSERT_COND(p_MM); -+ -+ p_MemBlock = p_MM->memBlocks; -+ for (i=0; i < index; i++) -+ p_MemBlock = p_MemBlock->p_Next; -+ -+ if ( p_MemBlock ) -+ return (p_MemBlock->base); -+ else -+ return (uint64_t)ILLEGAL_BASE; -+} -+ -+/*****************************************************************************/ -+uint64_t MM_GetBase(t_Handle h_MM) -+{ -+ t_MM *p_MM = (t_MM*)h_MM; -+ t_MemBlock *p_MemBlock; -+ -+ ASSERT_COND(p_MM); -+ -+ p_MemBlock = p_MM->memBlocks; -+ return p_MemBlock->base; -+} -+ -+/*****************************************************************************/ -+bool MM_InRange(t_Handle h_MM, uint64_t addr) -+{ -+ t_MM *p_MM = (t_MM*)h_MM; -+ t_MemBlock *p_MemBlock; -+ -+ ASSERT_COND(p_MM); -+ -+ p_MemBlock = p_MM->memBlocks; -+ -+ if ((addr >= p_MemBlock->base) && (addr < p_MemBlock->end)) -+ return TRUE; -+ else -+ return FALSE; -+} -+ -+/*****************************************************************************/ -+uint64_t MM_GetFreeMemSize(t_Handle h_MM) -+{ -+ t_MM *p_MM = (t_MM*)h_MM; -+ -+ ASSERT_COND(p_MM); -+ -+ return p_MM->freeMemSize; -+} -+ -+/*****************************************************************************/ -+void MM_Dump(t_Handle h_MM) -+{ -+ t_MM *p_MM = (t_MM *)h_MM; -+ t_FreeBlock *p_FreeB; -+ t_BusyBlock *p_BusyB; -+ int i; -+ -+ p_BusyB = p_MM->busyBlocks; -+ XX_Print("List of busy blocks:\n"); -+ while (p_BusyB) -+ { -+ XX_Print("\t0x%p: (%s: b=0x%llx, e=0x%llx)\n", p_BusyB, p_BusyB->name, p_BusyB->base, p_BusyB->end ); -+ p_BusyB = p_BusyB->p_Next; -+ } -+ -+ XX_Print("\nLists of free blocks according to alignment:\n"); -+ for (i=0; i <= MM_MAX_ALIGNMENT; i++) -+ { -+ XX_Print("%d alignment:\n", (0x1 << i)); -+ p_FreeB = p_MM->freeBlocks[i]; -+ while (p_FreeB) -+ { -+ XX_Print("\t0x%p: (b=0x%llx, e=0x%llx)\n", p_FreeB, p_FreeB->base, p_FreeB->end); -+ p_FreeB = p_FreeB->p_Next; -+ } -+ XX_Print("\n"); -+ } -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/etc/mm.h -@@ -0,0 +1,105 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************** -+ * -+ * File: mm.h -+ * -+ * -+ * Description: -+ * MM (Memory Management) object definitions. -+ * It also includes definitions of the Free Block, Busy Block -+ * and Memory Block structures used by the MM object. -+ * -+ ****************************************************************/ -+ -+#ifndef __MM_H -+#define __MM_H -+ -+ -+#include "mm_ext.h" -+ -+#define __ERR_MODULE__ MODULE_MM -+ -+ -+#define MAKE_ALIGNED(addr, align) \ -+ (((uint64_t)(addr) + ((align) - 1)) & (~(((uint64_t)align) - 1))) -+ -+ -+/* t_MemBlock data structure defines parameters of the Memory Block */ -+typedef struct t_MemBlock -+{ -+ struct t_MemBlock *p_Next; /* Pointer to the next memory block */ -+ -+ uint64_t base; /* Base address of the memory block */ -+ uint64_t end; /* End address of the memory block */ -+} t_MemBlock; -+ -+ -+/* t_FreeBlock data structure defines parameters of the Free Block */ -+typedef struct t_FreeBlock -+{ -+ struct t_FreeBlock *p_Next; /* Pointer to the next free block */ -+ -+ uint64_t base; /* Base address of the block */ -+ uint64_t end; /* End address of the block */ -+} t_FreeBlock; -+ -+ -+/* t_BusyBlock data structure defines parameters of the Busy Block */ -+typedef struct t_BusyBlock -+{ -+ struct t_BusyBlock *p_Next; /* Pointer to the next free block */ -+ -+ uint64_t base; /* Base address of the block */ -+ uint64_t end; /* End address of the block */ -+ char name[MM_MAX_NAME_LEN]; /* That block of memory was allocated for -+ something specified by the Name */ -+} t_BusyBlock; -+ -+ -+/* t_MM data structure defines parameters of the MM object */ -+typedef struct t_MM -+{ -+ t_Handle h_Spinlock; -+ -+ t_MemBlock *memBlocks; /* List of memory blocks (Memory list) */ -+ t_BusyBlock *busyBlocks; /* List of busy blocks (Busy list) */ -+ t_FreeBlock *freeBlocks[MM_MAX_ALIGNMENT + 1]; -+ /* Alignment lists of free blocks (Free lists) */ -+ -+ uint64_t freeMemSize; /* Total size of free memory (in bytes) */ -+} t_MM; -+ -+ -+#endif /* __MM_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/etc/sprint.c -@@ -0,0 +1,81 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/*------------------------------------------------------*/ -+/* File: sprint.c */ -+/* */ -+/* Description: */ -+/* Debug routines (externals) */ -+/*------------------------------------------------------*/ -+#include "string_ext.h" -+#include "stdlib_ext.h" -+#include "stdarg_ext.h" -+#include "sprint_ext.h" -+#include "std_ext.h" -+#include "xx_ext.h" -+ -+ -+int Sprint(char * buf, const char *fmt, ...) -+{ -+ va_list args; -+ int i; -+ -+ va_start(args, fmt); -+ i=vsprintf(buf,fmt,args); -+ va_end(args); -+ return i; -+} -+ -+int Snprint(char * buf, uint32_t size, const char *fmt, ...) -+{ -+ va_list args; -+ int i; -+ -+ va_start(args, fmt); -+ i=vsnprintf(buf,size,fmt,args); -+ va_end(args); -+ return i; -+} -+ -+#ifndef NCSW_VXWORKS -+int Sscan(const char * buf, const char * fmt, ...) -+{ -+ va_list args; -+ int i; -+ -+ va_start(args,fmt); -+ i = vsscanf(buf,fmt,args); -+ va_end(args); -+ return i; -+} -+#endif /* NCSW_VXWORKS */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/fmanv3h_dflags.h -@@ -0,0 +1,57 @@ -+/* -+ * Copyright 2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __dflags_h -+#define __dflags_h -+ -+ -+#define NCSW_LINUX -+ -+#define T4240 -+#define NCSW_PPC_CORE -+ -+#define DEBUG_ERRORS 1 -+ -+#if defined(DEBUG) -+#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_INFO -+ -+#define DEBUG_XX_MALLOC -+#define DEBUG_MEM_LEAKS -+ -+#else -+#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_WARNING -+#endif /* (DEBUG) */ -+ -+#define REPORT_EVENTS 1 -+#define EVENT_GLOBAL_LEVEL REPORT_LEVEL_MINOR -+ -+#endif /* __dflags_h */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/fmanv3l_dflags.h -@@ -0,0 +1,56 @@ -+/* -+ * Copyright 2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __dflags_h -+#define __dflags_h -+ -+ -+#define NCSW_LINUX -+ -+#define NCSW_PPC_CORE -+ -+#define DEBUG_ERRORS 1 -+ -+#if defined(DEBUG) -+#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_INFO -+ -+#define DEBUG_XX_MALLOC -+#define DEBUG_MEM_LEAKS -+ -+#else -+#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_WARNING -+#endif /* (DEBUG) */ -+ -+#define REPORT_EVENTS 1 -+#define EVENT_GLOBAL_LEVEL REPORT_LEVEL_MINOR -+ -+#endif /* __dflags_h */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/crc_mac_addr_ext.h -@@ -0,0 +1,364 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/*------------------------------------------------------*/ -+/* */ -+/* File: crc_mac_addr_ext.h */ -+/* */ -+/* Description: */ -+/* Define a macro that calculate the crc value of */ -+/* an Ethernet MAC address (48 bitd address */ -+/*------------------------------------------------------*/ -+ -+#ifndef __crc_mac_addr_ext_h -+#define __crc_mac_addr_ext_h -+ -+#include "std_ext.h" -+ -+ -+static uint32_t crc_table[256] = -+{ -+ 0x00000000, -+ 0x77073096, -+ 0xee0e612c, -+ 0x990951ba, -+ 0x076dc419, -+ 0x706af48f, -+ 0xe963a535, -+ 0x9e6495a3, -+ 0x0edb8832, -+ 0x79dcb8a4, -+ 0xe0d5e91e, -+ 0x97d2d988, -+ 0x09b64c2b, -+ 0x7eb17cbd, -+ 0xe7b82d07, -+ 0x90bf1d91, -+ 0x1db71064, -+ 0x6ab020f2, -+ 0xf3b97148, -+ 0x84be41de, -+ 0x1adad47d, -+ 0x6ddde4eb, -+ 0xf4d4b551, -+ 0x83d385c7, -+ 0x136c9856, -+ 0x646ba8c0, -+ 0xfd62f97a, -+ 0x8a65c9ec, -+ 0x14015c4f, -+ 0x63066cd9, -+ 0xfa0f3d63, -+ 0x8d080df5, -+ 0x3b6e20c8, -+ 0x4c69105e, -+ 0xd56041e4, -+ 0xa2677172, -+ 0x3c03e4d1, -+ 0x4b04d447, -+ 0xd20d85fd, -+ 0xa50ab56b, -+ 0x35b5a8fa, -+ 0x42b2986c, -+ 0xdbbbc9d6, -+ 0xacbcf940, -+ 0x32d86ce3, -+ 0x45df5c75, -+ 0xdcd60dcf, -+ 0xabd13d59, -+ 0x26d930ac, -+ 0x51de003a, -+ 0xc8d75180, -+ 0xbfd06116, -+ 0x21b4f4b5, -+ 0x56b3c423, -+ 0xcfba9599, -+ 0xb8bda50f, -+ 0x2802b89e, -+ 0x5f058808, -+ 0xc60cd9b2, -+ 0xb10be924, -+ 0x2f6f7c87, -+ 0x58684c11, -+ 0xc1611dab, -+ 0xb6662d3d, -+ 0x76dc4190, -+ 0x01db7106, -+ 0x98d220bc, -+ 0xefd5102a, -+ 0x71b18589, -+ 0x06b6b51f, -+ 0x9fbfe4a5, -+ 0xe8b8d433, -+ 0x7807c9a2, -+ 0x0f00f934, -+ 0x9609a88e, -+ 0xe10e9818, -+ 0x7f6a0dbb, -+ 0x086d3d2d, -+ 0x91646c97, -+ 0xe6635c01, -+ 0x6b6b51f4, -+ 0x1c6c6162, -+ 0x856530d8, -+ 0xf262004e, -+ 0x6c0695ed, -+ 0x1b01a57b, -+ 0x8208f4c1, -+ 0xf50fc457, -+ 0x65b0d9c6, -+ 0x12b7e950, -+ 0x8bbeb8ea, -+ 0xfcb9887c, -+ 0x62dd1ddf, -+ 0x15da2d49, -+ 0x8cd37cf3, -+ 0xfbd44c65, -+ 0x4db26158, -+ 0x3ab551ce, -+ 0xa3bc0074, -+ 0xd4bb30e2, -+ 0x4adfa541, -+ 0x3dd895d7, -+ 0xa4d1c46d, -+ 0xd3d6f4fb, -+ 0x4369e96a, -+ 0x346ed9fc, -+ 0xad678846, -+ 0xda60b8d0, -+ 0x44042d73, -+ 0x33031de5, -+ 0xaa0a4c5f, -+ 0xdd0d7cc9, -+ 0x5005713c, -+ 0x270241aa, -+ 0xbe0b1010, -+ 0xc90c2086, -+ 0x5768b525, -+ 0x206f85b3, -+ 0xb966d409, -+ 0xce61e49f, -+ 0x5edef90e, -+ 0x29d9c998, -+ 0xb0d09822, -+ 0xc7d7a8b4, -+ 0x59b33d17, -+ 0x2eb40d81, -+ 0xb7bd5c3b, -+ 0xc0ba6cad, -+ 0xedb88320, -+ 0x9abfb3b6, -+ 0x03b6e20c, -+ 0x74b1d29a, -+ 0xead54739, -+ 0x9dd277af, -+ 0x04db2615, -+ 0x73dc1683, -+ 0xe3630b12, -+ 0x94643b84, -+ 0x0d6d6a3e, -+ 0x7a6a5aa8, -+ 0xe40ecf0b, -+ 0x9309ff9d, -+ 0x0a00ae27, -+ 0x7d079eb1, -+ 0xf00f9344, -+ 0x8708a3d2, -+ 0x1e01f268, -+ 0x6906c2fe, -+ 0xf762575d, -+ 0x806567cb, -+ 0x196c3671, -+ 0x6e6b06e7, -+ 0xfed41b76, -+ 0x89d32be0, -+ 0x10da7a5a, -+ 0x67dd4acc, -+ 0xf9b9df6f, -+ 0x8ebeeff9, -+ 0x17b7be43, -+ 0x60b08ed5, -+ 0xd6d6a3e8, -+ 0xa1d1937e, -+ 0x38d8c2c4, -+ 0x4fdff252, -+ 0xd1bb67f1, -+ 0xa6bc5767, -+ 0x3fb506dd, -+ 0x48b2364b, -+ 0xd80d2bda, -+ 0xaf0a1b4c, -+ 0x36034af6, -+ 0x41047a60, -+ 0xdf60efc3, -+ 0xa867df55, -+ 0x316e8eef, -+ 0x4669be79, -+ 0xcb61b38c, -+ 0xbc66831a, -+ 0x256fd2a0, -+ 0x5268e236, -+ 0xcc0c7795, -+ 0xbb0b4703, -+ 0x220216b9, -+ 0x5505262f, -+ 0xc5ba3bbe, -+ 0xb2bd0b28, -+ 0x2bb45a92, -+ 0x5cb36a04, -+ 0xc2d7ffa7, -+ 0xb5d0cf31, -+ 0x2cd99e8b, -+ 0x5bdeae1d, -+ 0x9b64c2b0, -+ 0xec63f226, -+ 0x756aa39c, -+ 0x026d930a, -+ 0x9c0906a9, -+ 0xeb0e363f, -+ 0x72076785, -+ 0x05005713, -+ 0x95bf4a82, -+ 0xe2b87a14, -+ 0x7bb12bae, -+ 0x0cb61b38, -+ 0x92d28e9b, -+ 0xe5d5be0d, -+ 0x7cdcefb7, -+ 0x0bdbdf21, -+ 0x86d3d2d4, -+ 0xf1d4e242, -+ 0x68ddb3f8, -+ 0x1fda836e, -+ 0x81be16cd, -+ 0xf6b9265b, -+ 0x6fb077e1, -+ 0x18b74777, -+ 0x88085ae6, -+ 0xff0f6a70, -+ 0x66063bca, -+ 0x11010b5c, -+ 0x8f659eff, -+ 0xf862ae69, -+ 0x616bffd3, -+ 0x166ccf45, -+ 0xa00ae278, -+ 0xd70dd2ee, -+ 0x4e048354, -+ 0x3903b3c2, -+ 0xa7672661, -+ 0xd06016f7, -+ 0x4969474d, -+ 0x3e6e77db, -+ 0xaed16a4a, -+ 0xd9d65adc, -+ 0x40df0b66, -+ 0x37d83bf0, -+ 0xa9bcae53, -+ 0xdebb9ec5, -+ 0x47b2cf7f, -+ 0x30b5ffe9, -+ 0xbdbdf21c, -+ 0xcabac28a, -+ 0x53b39330, -+ 0x24b4a3a6, -+ 0xbad03605, -+ 0xcdd70693, -+ 0x54de5729, -+ 0x23d967bf, -+ 0xb3667a2e, -+ 0xc4614ab8, -+ 0x5d681b02, -+ 0x2a6f2b94, -+ 0xb40bbe37, -+ 0xc30c8ea1, -+ 0x5a05df1b, -+ 0x2d02ef8d -+}; -+ -+ -+#define GET_MAC_ADDR_CRC(addr, crc) \ -+{ \ -+ uint32_t i; \ -+ uint8_t data; \ -+ \ -+ /* CRC calculation */ \ -+ crc = 0xffffffff; \ -+ for (i=0; i < 6; i++) \ -+ { \ -+ data = (uint8_t)(addr >> ((5-i)*8)); \ -+ crc = crc^data; \ -+ crc = crc_table[crc&0xff] ^ (crc>>8); \ -+ } \ -+} \ -+ -+/* Define a macro for getting the mirrored value of */ -+/* a byte size number. (0x11010011 --> 0x11001011) */ -+/* Sometimes the mirrored value of the CRC is required */ -+static __inline__ uint8_t GetMirror(uint8_t n) -+{ -+ uint8_t mirror[16] = -+ { -+ 0x00, -+ 0x08, -+ 0x04, -+ 0x0c, -+ 0x02, -+ 0x0a, -+ 0x06, -+ 0x0e, -+ 0x01, -+ 0x09, -+ 0x05, -+ 0x0d, -+ 0x03, -+ 0x0b, -+ 0x07, -+ 0x0f -+ }; -+ return ((uint8_t)(((mirror[n & 0x0f] << 4) | (mirror[n >> 4])))); -+} -+ -+static __inline__ uint32_t GetMirror32(uint32_t n) -+{ -+ return (((uint32_t)GetMirror((uint8_t)(n))<<24) | -+ ((uint32_t)GetMirror((uint8_t)(n>>8))<<16) | -+ ((uint32_t)GetMirror((uint8_t)(n>>16))<<8) | -+ ((uint32_t)GetMirror((uint8_t)(n>>24)))); -+} -+ -+#define MIRROR GetMirror -+#define MIRROR_32 GetMirror32 -+ -+ -+#endif /* __crc_mac_addr_ext_h */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/dpaa_ext.h -@@ -0,0 +1,207 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File dpaa_ext.h -+ -+ @Description DPAA Application Programming Interface. -+*//***************************************************************************/ -+#ifndef __DPAA_EXT_H -+#define __DPAA_EXT_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group DPAA_grp Data Path Acceleration Architecture API -+ -+ @Description DPAA API functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+/**************************************************************************//** -+ @Description Frame descriptor -+*//***************************************************************************/ -+typedef _Packed struct t_DpaaFD { -+ volatile uint32_t id; /**< FD id */ -+ volatile uint32_t addrl; /**< Data Address */ -+ volatile uint32_t length; /**< Frame length */ -+ volatile uint32_t status; /**< FD status */ -+} _PackedType t_DpaaFD; -+ -+/**************************************************************************//** -+ @Description enum for defining frame format -+*//***************************************************************************/ -+typedef enum e_DpaaFDFormatType { -+ e_DPAA_FD_FORMAT_TYPE_SHORT_SBSF = 0x0, /**< Simple frame Single buffer; Offset and -+ small length (9b OFFSET, 20b LENGTH) */ -+ e_DPAA_FD_FORMAT_TYPE_LONG_SBSF = 0x2, /**< Simple frame, single buffer; big length -+ (29b LENGTH ,No OFFSET) */ -+ e_DPAA_FD_FORMAT_TYPE_SHORT_MBSF = 0x4, /**< Simple frame, Scatter Gather table; Offset -+ and small length (9b OFFSET, 20b LENGTH) */ -+ e_DPAA_FD_FORMAT_TYPE_LONG_MBSF = 0x6, /**< Simple frame, Scatter Gather table; -+ big length (29b LENGTH ,No OFFSET) */ -+ e_DPAA_FD_FORMAT_TYPE_COMPOUND = 0x1, /**< Compound Frame (29b CONGESTION-WEIGHT -+ No LENGTH or OFFSET) */ -+ e_DPAA_FD_FORMAT_TYPE_DUMMY -+} e_DpaaFDFormatType; -+ -+/**************************************************************************//** -+ @Collection Frame descriptor macros -+*//***************************************************************************/ -+#define DPAA_FD_DD_MASK 0xc0000000 /**< FD DD field mask */ -+#define DPAA_FD_PID_MASK 0x3f000000 /**< FD PID field mask */ -+#define DPAA_FD_ELIODN_MASK 0x0000f000 /**< FD ELIODN field mask */ -+#define DPAA_FD_BPID_MASK 0x00ff0000 /**< FD BPID field mask */ -+#define DPAA_FD_ADDRH_MASK 0x000000ff /**< FD ADDRH field mask */ -+#define DPAA_FD_ADDRL_MASK 0xffffffff /**< FD ADDRL field mask */ -+#define DPAA_FD_FORMAT_MASK 0xe0000000 /**< FD FORMAT field mask */ -+#define DPAA_FD_OFFSET_MASK 0x1ff00000 /**< FD OFFSET field mask */ -+#define DPAA_FD_LENGTH_MASK 0x000fffff /**< FD LENGTH field mask */ -+ -+#define DPAA_FD_GET_DD(fd) ((((t_DpaaFD *)fd)->id & DPAA_FD_DD_MASK) >> (31-1)) /**< Macro to get FD DD field */ -+#define DPAA_FD_GET_PID(fd) (((((t_DpaaFD *)fd)->id & DPAA_FD_PID_MASK) >> (31-7)) | \ -+ ((((t_DpaaFD *)fd)->id & DPAA_FD_ELIODN_MASK) >> (31-19-6))) /**< Macro to get FD PID field */ -+#define DPAA_FD_GET_BPID(fd) ((((t_DpaaFD *)fd)->id & DPAA_FD_BPID_MASK) >> (31-15)) /**< Macro to get FD BPID field */ -+#define DPAA_FD_GET_ADDRH(fd) (((t_DpaaFD *)fd)->id & DPAA_FD_ADDRH_MASK) /**< Macro to get FD ADDRH field */ -+#define DPAA_FD_GET_ADDRL(fd) ((t_DpaaFD *)fd)->addrl /**< Macro to get FD ADDRL field */ -+#define DPAA_FD_GET_PHYS_ADDR(fd) ((physAddress_t)(((uint64_t)DPAA_FD_GET_ADDRH(fd) << 32) | (uint64_t)DPAA_FD_GET_ADDRL(fd))) /**< Macro to get FD ADDR field */ -+#define DPAA_FD_GET_FORMAT(fd) ((((t_DpaaFD *)fd)->length & DPAA_FD_FORMAT_MASK) >> (31-2)) /**< Macro to get FD FORMAT field */ -+#define DPAA_FD_GET_OFFSET(fd) ((((t_DpaaFD *)fd)->length & DPAA_FD_OFFSET_MASK) >> (31-11)) /**< Macro to get FD OFFSET field */ -+#define DPAA_FD_GET_LENGTH(fd) (((t_DpaaFD *)fd)->length & DPAA_FD_LENGTH_MASK) /**< Macro to get FD LENGTH field */ -+#define DPAA_FD_GET_STATUS(fd) ((t_DpaaFD *)fd)->status /**< Macro to get FD STATUS field */ -+#define DPAA_FD_GET_ADDR(fd) XX_PhysToVirt(DPAA_FD_GET_PHYS_ADDR(fd)) /**< Macro to get FD ADDR (virtual) */ -+ -+#define DPAA_FD_SET_DD(fd,val) (((t_DpaaFD *)fd)->id = ((((t_DpaaFD *)fd)->id & ~DPAA_FD_DD_MASK) | (((val) << (31-1)) & DPAA_FD_DD_MASK ))) /**< Macro to set FD DD field */ -+ /**< Macro to set FD PID field or LIODN offset*/ -+#define DPAA_FD_SET_PID(fd,val) (((t_DpaaFD *)fd)->id = ((((t_DpaaFD *)fd)->id & ~(DPAA_FD_PID_MASK|DPAA_FD_ELIODN_MASK)) | ((((val) << (31-7)) & DPAA_FD_PID_MASK) | ((((val)>>6) << (31-19)) & DPAA_FD_ELIODN_MASK)))) -+#define DPAA_FD_SET_BPID(fd,val) (((t_DpaaFD *)fd)->id = ((((t_DpaaFD *)fd)->id & ~DPAA_FD_BPID_MASK) | (((val) << (31-15)) & DPAA_FD_BPID_MASK))) /**< Macro to set FD BPID field */ -+#define DPAA_FD_SET_ADDRH(fd,val) (((t_DpaaFD *)fd)->id = ((((t_DpaaFD *)fd)->id & ~DPAA_FD_ADDRH_MASK) | ((val) & DPAA_FD_ADDRH_MASK))) /**< Macro to set FD ADDRH field */ -+#define DPAA_FD_SET_ADDRL(fd,val) ((t_DpaaFD *)fd)->addrl = (val) /**< Macro to set FD ADDRL field */ -+#define DPAA_FD_SET_ADDR(fd,val) \ -+do { \ -+ uint64_t physAddr = (uint64_t)(XX_VirtToPhys(val)); \ -+ DPAA_FD_SET_ADDRH(fd, ((uint32_t)(physAddr >> 32))); \ -+ DPAA_FD_SET_ADDRL(fd, (uint32_t)physAddr); \ -+} while (0) /**< Macro to set FD ADDR field */ -+#define DPAA_FD_SET_FORMAT(fd,val) (((t_DpaaFD *)fd)->length = ((((t_DpaaFD *)fd)->length & ~DPAA_FD_FORMAT_MASK) | (((val) << (31-2))& DPAA_FD_FORMAT_MASK))) /**< Macro to set FD FORMAT field */ -+#define DPAA_FD_SET_OFFSET(fd,val) (((t_DpaaFD *)fd)->length = ((((t_DpaaFD *)fd)->length & ~DPAA_FD_OFFSET_MASK) | (((val) << (31-11))& DPAA_FD_OFFSET_MASK) )) /**< Macro to set FD OFFSET field */ -+#define DPAA_FD_SET_LENGTH(fd,val) (((t_DpaaFD *)fd)->length = (((t_DpaaFD *)fd)->length & ~DPAA_FD_LENGTH_MASK) | ((val) & DPAA_FD_LENGTH_MASK)) /**< Macro to set FD LENGTH field */ -+#define DPAA_FD_SET_STATUS(fd,val) ((t_DpaaFD *)fd)->status = (val) /**< Macro to set FD STATUS field */ -+/* @} */ -+ -+/**************************************************************************//** -+ @Description Frame Scatter/Gather Table Entry -+*//***************************************************************************/ -+typedef _Packed struct t_DpaaSGTE { -+ volatile uint32_t addrh; /**< Buffer Address high */ -+ volatile uint32_t addrl; /**< Buffer Address low */ -+ volatile uint32_t length; /**< Buffer length */ -+ volatile uint32_t offset; /**< SGTE offset */ -+} _PackedType t_DpaaSGTE; -+ -+#define DPAA_NUM_OF_SG_TABLE_ENTRY 16 -+ -+/**************************************************************************//** -+ @Description Frame Scatter/Gather Table -+*//***************************************************************************/ -+typedef _Packed struct t_DpaaSGT { -+ t_DpaaSGTE tableEntry[DPAA_NUM_OF_SG_TABLE_ENTRY]; -+ /**< Structure that holds information about -+ a single S/G entry. */ -+} _PackedType t_DpaaSGT; -+ -+/**************************************************************************//** -+ @Description Compound Frame Table -+*//***************************************************************************/ -+typedef _Packed struct t_DpaaCompTbl { -+ t_DpaaSGTE outputBuffInfo; /**< Structure that holds information about -+ the compound-frame output buffer; -+ NOTE: this may point to a S/G table */ -+ t_DpaaSGTE inputBuffInfo; /**< Structure that holds information about -+ the compound-frame input buffer; -+ NOTE: this may point to a S/G table */ -+} _PackedType t_DpaaCompTbl; -+ -+/**************************************************************************//** -+ @Collection Frame Scatter/Gather Table Entry macros -+*//***************************************************************************/ -+#define DPAA_SGTE_ADDRH_MASK 0x000000ff /**< SGTE ADDRH field mask */ -+#define DPAA_SGTE_ADDRL_MASK 0xffffffff /**< SGTE ADDRL field mask */ -+#define DPAA_SGTE_E_MASK 0x80000000 /**< SGTE Extension field mask */ -+#define DPAA_SGTE_F_MASK 0x40000000 /**< SGTE Final field mask */ -+#define DPAA_SGTE_LENGTH_MASK 0x3fffffff /**< SGTE LENGTH field mask */ -+#define DPAA_SGTE_BPID_MASK 0x00ff0000 /**< SGTE BPID field mask */ -+#define DPAA_SGTE_OFFSET_MASK 0x00001fff /**< SGTE OFFSET field mask */ -+ -+#define DPAA_SGTE_GET_ADDRH(sgte) (((t_DpaaSGTE *)sgte)->addrh & DPAA_SGTE_ADDRH_MASK) /**< Macro to get SGTE ADDRH field */ -+#define DPAA_SGTE_GET_ADDRL(sgte) ((t_DpaaSGTE *)sgte)->addrl /**< Macro to get SGTE ADDRL field */ -+#define DPAA_SGTE_GET_PHYS_ADDR(sgte) ((physAddress_t)(((uint64_t)DPAA_SGTE_GET_ADDRH(sgte) << 32) | (uint64_t)DPAA_SGTE_GET_ADDRL(sgte))) /**< Macro to get FD ADDR field */ -+#define DPAA_SGTE_GET_EXTENSION(sgte) ((((t_DpaaSGTE *)sgte)->length & DPAA_SGTE_E_MASK) >> (31-0)) /**< Macro to get SGTE EXTENSION field */ -+#define DPAA_SGTE_GET_FINAL(sgte) ((((t_DpaaSGTE *)sgte)->length & DPAA_SGTE_F_MASK) >> (31-1)) /**< Macro to get SGTE FINAL field */ -+#define DPAA_SGTE_GET_LENGTH(sgte) (((t_DpaaSGTE *)sgte)->length & DPAA_SGTE_LENGTH_MASK) /**< Macro to get SGTE LENGTH field */ -+#define DPAA_SGTE_GET_BPID(sgte) ((((t_DpaaSGTE *)sgte)->offset & DPAA_SGTE_BPID_MASK) >> (31-15)) /**< Macro to get SGTE BPID field */ -+#define DPAA_SGTE_GET_OFFSET(sgte) (((t_DpaaSGTE *)sgte)->offset & DPAA_SGTE_OFFSET_MASK) /**< Macro to get SGTE OFFSET field */ -+#define DPAA_SGTE_GET_ADDR(sgte) XX_PhysToVirt(DPAA_SGTE_GET_PHYS_ADDR(sgte)) -+ -+#define DPAA_SGTE_SET_ADDRH(sgte,val) (((t_DpaaSGTE *)sgte)->addrh = ((((t_DpaaSGTE *)sgte)->addrh & ~DPAA_SGTE_ADDRH_MASK) | ((val) & DPAA_SGTE_ADDRH_MASK))) /**< Macro to set SGTE ADDRH field */ -+#define DPAA_SGTE_SET_ADDRL(sgte,val) ((t_DpaaSGTE *)sgte)->addrl = (val) /**< Macro to set SGTE ADDRL field */ -+#define DPAA_SGTE_SET_ADDR(sgte,val) \ -+do { \ -+ uint64_t physAddr = (uint64_t)(XX_VirtToPhys(val)); \ -+ DPAA_SGTE_SET_ADDRH(sgte, ((uint32_t)(physAddr >> 32))); \ -+ DPAA_SGTE_SET_ADDRL(sgte, (uint32_t)physAddr); \ -+} while (0) /**< Macro to set SGTE ADDR field */ -+#define DPAA_SGTE_SET_EXTENSION(sgte,val) (((t_DpaaSGTE *)sgte)->length = ((((t_DpaaSGTE *)sgte)->length & ~DPAA_SGTE_E_MASK) | (((val) << (31-0))& DPAA_SGTE_E_MASK))) /**< Macro to set SGTE EXTENSION field */ -+#define DPAA_SGTE_SET_FINAL(sgte,val) (((t_DpaaSGTE *)sgte)->length = ((((t_DpaaSGTE *)sgte)->length & ~DPAA_SGTE_F_MASK) | (((val) << (31-1))& DPAA_SGTE_F_MASK))) /**< Macro to set SGTE FINAL field */ -+#define DPAA_SGTE_SET_LENGTH(sgte,val) (((t_DpaaSGTE *)sgte)->length = (((t_DpaaSGTE *)sgte)->length & ~DPAA_SGTE_LENGTH_MASK) | ((val) & DPAA_SGTE_LENGTH_MASK)) /**< Macro to set SGTE LENGTH field */ -+#define DPAA_SGTE_SET_BPID(sgte,val) (((t_DpaaSGTE *)sgte)->offset = ((((t_DpaaSGTE *)sgte)->offset & ~DPAA_SGTE_BPID_MASK) | (((val) << (31-15))& DPAA_SGTE_BPID_MASK))) /**< Macro to set SGTE BPID field */ -+#define DPAA_SGTE_SET_OFFSET(sgte,val) (((t_DpaaSGTE *)sgte)->offset = ((((t_DpaaSGTE *)sgte)->offset & ~DPAA_SGTE_OFFSET_MASK) | (((val) << (31-31))& DPAA_SGTE_OFFSET_MASK) )) /**< Macro to set SGTE OFFSET field */ -+/* @} */ -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+#define DPAA_LIODN_DONT_OVERRIDE (-1) -+ -+/** @} */ /* end of DPAA_grp group */ -+ -+ -+#endif /* __DPAA_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_ext.h -@@ -0,0 +1,1705 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File fm_ext.h -+ -+ @Description FM Application Programming Interface. -+*//***************************************************************************/ -+#ifndef __FM_EXT -+#define __FM_EXT -+ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "dpaa_ext.h" -+#include "fsl_fman_sp.h" -+ -+/**************************************************************************//** -+ @Group FM_grp Frame Manager API -+ -+ @Description FM API functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group FM_lib_grp FM library -+ -+ @Description FM API functions, definitions and enums. -+ -+ The FM module is the main driver module and is a mandatory module -+ for FM driver users. This module must be initialized first prior -+ to any other drivers modules. -+ The FM is a "singleton" module. It is responsible of the common -+ HW modules: FPM, DMA, common QMI and common BMI initializations and -+ run-time control routines. This module must be initialized always -+ when working with any of the FM modules. -+ NOTE - We assume that the FM library will be initialized only by core No. 0! -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description Enum for defining port types -+*//***************************************************************************/ -+typedef enum e_FmPortType { -+ e_FM_PORT_TYPE_OH_OFFLINE_PARSING = 0, /**< Offline parsing port */ -+ e_FM_PORT_TYPE_RX, /**< 1G Rx port */ -+ e_FM_PORT_TYPE_RX_10G, /**< 10G Rx port */ -+ e_FM_PORT_TYPE_TX, /**< 1G Tx port */ -+ e_FM_PORT_TYPE_TX_10G, /**< 10G Tx port */ -+ e_FM_PORT_TYPE_DUMMY -+} e_FmPortType; -+ -+/**************************************************************************//** -+ @Collection General FM defines -+*//***************************************************************************/ -+#define FM_MAX_NUM_OF_PARTITIONS 64 /**< Maximum number of partitions */ -+#define FM_PHYS_ADDRESS_SIZE 6 /**< FM Physical address size */ -+/* @} */ -+ -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(push,1) -+#endif /* defined(__MWERKS__) && ... */ -+ -+/**************************************************************************//** -+ @Description FM physical Address -+*//***************************************************************************/ -+typedef _Packed struct t_FmPhysAddr { -+ volatile uint8_t high; /**< High part of the physical address */ -+ volatile uint32_t low; /**< Low part of the physical address */ -+} _PackedType t_FmPhysAddr; -+ -+/**************************************************************************//** -+ @Description Parse results memory layout -+*//***************************************************************************/ -+typedef _Packed struct t_FmPrsResult { -+ volatile uint8_t lpid; /**< Logical port id */ -+ volatile uint8_t shimr; /**< Shim header result */ -+ volatile uint16_t l2r; /**< Layer 2 result */ -+ volatile uint16_t l3r; /**< Layer 3 result */ -+ volatile uint8_t l4r; /**< Layer 4 result */ -+ volatile uint8_t cplan; /**< Classification plan id */ -+ volatile uint16_t nxthdr; /**< Next Header */ -+ volatile uint16_t cksum; /**< Running-sum */ -+ volatile uint16_t flags_frag_off; /**< Flags & fragment-offset field of the last IP-header */ -+ volatile uint8_t route_type; /**< Routing type field of a IPv6 routing extension header */ -+ volatile uint8_t rhp_ip_valid; /**< Routing Extension Header Present; last bit is IP valid */ -+ volatile uint8_t shim_off[2]; /**< Shim offset */ -+ volatile uint8_t ip_pid_off; /**< IP PID (last IP-proto) offset */ -+ volatile uint8_t eth_off; /**< ETH offset */ -+ volatile uint8_t llc_snap_off; /**< LLC_SNAP offset */ -+ volatile uint8_t vlan_off[2]; /**< VLAN offset */ -+ volatile uint8_t etype_off; /**< ETYPE offset */ -+ volatile uint8_t pppoe_off; /**< PPP offset */ -+ volatile uint8_t mpls_off[2]; /**< MPLS offset */ -+ volatile uint8_t ip_off[2]; /**< IP offset */ -+ volatile uint8_t gre_off; /**< GRE offset */ -+ volatile uint8_t l4_off; /**< Layer 4 offset */ -+ volatile uint8_t nxthdr_off; /**< Parser end point */ -+} _PackedType t_FmPrsResult; -+ -+/**************************************************************************//** -+ @Collection FM Parser results -+*//***************************************************************************/ -+#define FM_PR_L2_VLAN_STACK 0x00000100 /**< Parse Result: VLAN stack */ -+#define FM_PR_L2_ETHERNET 0x00008000 /**< Parse Result: Ethernet*/ -+#define FM_PR_L2_VLAN 0x00004000 /**< Parse Result: VLAN */ -+#define FM_PR_L2_LLC_SNAP 0x00002000 /**< Parse Result: LLC_SNAP */ -+#define FM_PR_L2_MPLS 0x00001000 /**< Parse Result: MPLS */ -+#define FM_PR_L2_PPPoE 0x00000800 /**< Parse Result: PPPoE */ -+/* @} */ -+ -+/**************************************************************************//** -+ @Collection FM Frame descriptor macros -+*//***************************************************************************/ -+#define FM_FD_CMD_FCO 0x80000000 /**< Frame queue Context Override */ -+#define FM_FD_CMD_RPD 0x40000000 /**< Read Prepended Data */ -+#define FM_FD_CMD_UPD 0x20000000 /**< Update Prepended Data */ -+#define FM_FD_CMD_DTC 0x10000000 /**< Do L4 Checksum */ -+#define FM_FD_CMD_DCL4C 0x10000000 /**< Didn't calculate L4 Checksum */ -+#define FM_FD_CMD_CFQ 0x00ffffff /**< Confirmation Frame Queue */ -+ -+#define FM_FD_ERR_UNSUPPORTED_FORMAT 0x04000000 /**< Not for Rx-Port! Unsupported Format */ -+#define FM_FD_ERR_LENGTH 0x02000000 /**< Not for Rx-Port! Length Error */ -+#define FM_FD_ERR_DMA 0x01000000 /**< DMA Data error */ -+ -+#define FM_FD_IPR 0x00000001 /**< IPR frame (not error) */ -+ -+#define FM_FD_ERR_IPR_NCSP (0x00100000 | FM_FD_IPR) /**< IPR non-consistent-sp */ -+#define FM_FD_ERR_IPR (0x00200000 | FM_FD_IPR) /**< IPR error */ -+#define FM_FD_ERR_IPR_TO (0x00300000 | FM_FD_IPR) /**< IPR timeout */ -+ -+#ifdef FM_CAPWAP_SUPPORT -+#define FM_FD_ERR_CRE 0x00200000 -+#define FM_FD_ERR_CHE 0x00100000 -+#endif /* FM_CAPWAP_SUPPORT */ -+ -+#define FM_FD_ERR_PHYSICAL 0x00080000 /**< Rx FIFO overflow, FCS error, code error, running disparity -+ error (SGMII and TBI modes), FIFO parity error. PHY -+ Sequence error, PHY error control character detected. */ -+#define FM_FD_ERR_SIZE 0x00040000 /**< Frame too long OR Frame size exceeds max_length_frame */ -+#define FM_FD_ERR_CLS_DISCARD 0x00020000 /**< classification discard */ -+#define FM_FD_ERR_EXTRACTION 0x00008000 /**< Extract Out of Frame */ -+#define FM_FD_ERR_NO_SCHEME 0x00004000 /**< No Scheme Selected */ -+#define FM_FD_ERR_KEYSIZE_OVERFLOW 0x00002000 /**< Keysize Overflow */ -+#define FM_FD_ERR_COLOR_RED 0x00000800 /**< Frame color is red */ -+#define FM_FD_ERR_COLOR_YELLOW 0x00000400 /**< Frame color is yellow */ -+#define FM_FD_ERR_ILL_PLCR 0x00000200 /**< Illegal Policer Profile selected */ -+#define FM_FD_ERR_PLCR_FRAME_LEN 0x00000100 /**< Policer frame length error */ -+#define FM_FD_ERR_PRS_TIMEOUT 0x00000080 /**< Parser Time out Exceed */ -+#define FM_FD_ERR_PRS_ILL_INSTRUCT 0x00000040 /**< Invalid Soft Parser instruction */ -+#define FM_FD_ERR_PRS_HDR_ERR 0x00000020 /**< Header error was identified during parsing */ -+#define FM_FD_ERR_BLOCK_LIMIT_EXCEEDED 0x00000008 /**< Frame parsed beyind 256 first bytes */ -+ -+#define FM_FD_TX_STATUS_ERR_MASK (FM_FD_ERR_UNSUPPORTED_FORMAT | \ -+ FM_FD_ERR_LENGTH | \ -+ FM_FD_ERR_DMA) /**< TX Error FD bits */ -+ -+#define FM_FD_RX_STATUS_ERR_MASK (FM_FD_ERR_UNSUPPORTED_FORMAT | \ -+ FM_FD_ERR_LENGTH | \ -+ FM_FD_ERR_DMA | \ -+ FM_FD_ERR_IPR | \ -+ FM_FD_ERR_IPR_TO | \ -+ FM_FD_ERR_IPR_NCSP | \ -+ FM_FD_ERR_PHYSICAL | \ -+ FM_FD_ERR_SIZE | \ -+ FM_FD_ERR_CLS_DISCARD | \ -+ FM_FD_ERR_COLOR_RED | \ -+ FM_FD_ERR_COLOR_YELLOW | \ -+ FM_FD_ERR_ILL_PLCR | \ -+ FM_FD_ERR_PLCR_FRAME_LEN | \ -+ FM_FD_ERR_EXTRACTION | \ -+ FM_FD_ERR_NO_SCHEME | \ -+ FM_FD_ERR_KEYSIZE_OVERFLOW | \ -+ FM_FD_ERR_PRS_TIMEOUT | \ -+ FM_FD_ERR_PRS_ILL_INSTRUCT | \ -+ FM_FD_ERR_PRS_HDR_ERR | \ -+ FM_FD_ERR_BLOCK_LIMIT_EXCEEDED) /**< RX Error FD bits */ -+ -+#define FM_FD_RX_STATUS_ERR_NON_FM 0x00400000 /**< non Frame-Manager error */ -+/* @} */ -+ -+/**************************************************************************//** -+ @Description Context A -+*//***************************************************************************/ -+typedef _Packed struct t_FmContextA { -+ volatile uint32_t command; /**< ContextA Command */ -+ volatile uint8_t res0[4]; /**< ContextA Reserved bits */ -+} _PackedType t_FmContextA; -+ -+/**************************************************************************//** -+ @Description Context B -+*//***************************************************************************/ -+typedef uint32_t t_FmContextB; -+ -+/**************************************************************************//** -+ @Collection Special Operation options -+*//***************************************************************************/ -+typedef uint32_t fmSpecialOperations_t; /**< typedef for defining Special Operation options */ -+ -+#define FM_SP_OP_IPSEC 0x80000000 /**< activate features that related to IPSec (e.g fix Eth-type) */ -+#define FM_SP_OP_IPSEC_UPDATE_UDP_LEN 0x40000000 /**< update the UDP-Len after Encryption */ -+#define FM_SP_OP_IPSEC_MANIP 0x20000000 /**< handle the IPSec-manip options */ -+#define FM_SP_OP_RPD 0x10000000 /**< Set the RPD bit */ -+#define FM_SP_OP_DCL4C 0x08000000 /**< Set the DCL4C bit */ -+#define FM_SP_OP_CHECK_SEC_ERRORS 0x04000000 /**< Check SEC errors */ -+#define FM_SP_OP_CLEAR_RPD 0x02000000 /**< Clear the RPD bit */ -+#define FM_SP_OP_CAPWAP_DTLS_ENC 0x01000000 /**< activate features that related to CAPWAP-DTLS post Encryption */ -+#define FM_SP_OP_CAPWAP_DTLS_DEC 0x00800000 /**< activate features that related to CAPWAP-DTLS post Decryption */ -+#define FM_SP_OP_IPSEC_NO_ETH_HDR 0x00400000 /**< activate features that related to IPSec without Eth hdr */ -+/* @} */ -+ -+/**************************************************************************//** -+ @Collection Context A macros -+*//***************************************************************************/ -+#define FM_CONTEXTA_OVERRIDE_MASK 0x80000000 -+#define FM_CONTEXTA_ICMD_MASK 0x40000000 -+#define FM_CONTEXTA_A1_VALID_MASK 0x20000000 -+#define FM_CONTEXTA_MACCMD_MASK 0x00ff0000 -+#define FM_CONTEXTA_MACCMD_VALID_MASK 0x00800000 -+#define FM_CONTEXTA_MACCMD_SECURED_MASK 0x00100000 -+#define FM_CONTEXTA_MACCMD_SC_MASK 0x000f0000 -+#define FM_CONTEXTA_A1_MASK 0x0000ffff -+ -+#define FM_CONTEXTA_GET_OVERRIDE(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_OVERRIDE_MASK) >> (31-0)) -+#define FM_CONTEXTA_GET_ICMD(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_ICMD_MASK) >> (31-1)) -+#define FM_CONTEXTA_GET_A1_VALID(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_A1_VALID_MASK) >> (31-2)) -+#define FM_CONTEXTA_GET_A1(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_A1_MASK) >> (31-31)) -+#define FM_CONTEXTA_GET_MACCMD(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_MACCMD_MASK) >> (31-15)) -+#define FM_CONTEXTA_GET_MACCMD_VALID(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_MACCMD_VALID_MASK) >> (31-8)) -+#define FM_CONTEXTA_GET_MACCMD_SECURED(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_MACCMD_SECURED_MASK) >> (31-11)) -+#define FM_CONTEXTA_GET_MACCMD_SECURE_CHANNEL(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_MACCMD_SC_MASK) >> (31-15)) -+ -+#define FM_CONTEXTA_SET_OVERRIDE(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_OVERRIDE_MASK) | (((uint32_t)(val) << (31-0)) & FM_CONTEXTA_OVERRIDE_MASK) )) -+#define FM_CONTEXTA_SET_ICMD(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_ICMD_MASK) | (((val) << (31-1)) & FM_CONTEXTA_ICMD_MASK) )) -+#define FM_CONTEXTA_SET_A1_VALID(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_A1_VALID_MASK) | (((val) << (31-2)) & FM_CONTEXTA_A1_VALID_MASK) )) -+#define FM_CONTEXTA_SET_A1(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_A1_MASK) | (((val) << (31-31)) & FM_CONTEXTA_A1_MASK) )) -+#define FM_CONTEXTA_SET_MACCMD(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_MACCMD_MASK) | (((val) << (31-15)) & FM_CONTEXTA_MACCMD_MASK) )) -+#define FM_CONTEXTA_SET_MACCMD_VALID(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_MACCMD_VALID_MASK) | (((val) << (31-8)) & FM_CONTEXTA_MACCMD_VALID_MASK) )) -+#define FM_CONTEXTA_SET_MACCMD_SECURED(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_MACCMD_SECURED_MASK) | (((val) << (31-11)) & FM_CONTEXTA_MACCMD_SECURED_MASK) )) -+#define FM_CONTEXTA_SET_MACCMD_SECURE_CHANNEL(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_MACCMD_SC_MASK) | (((val) << (31-15)) & FM_CONTEXTA_MACCMD_SC_MASK) )) -+/* @} */ -+ -+/**************************************************************************//** -+ @Collection Context B macros -+*//***************************************************************************/ -+#define FM_CONTEXTB_FQID_MASK 0x00ffffff -+ -+#define FM_CONTEXTB_GET_FQID(contextB) (*((t_FmContextB *)contextB) & FM_CONTEXTB_FQID_MASK) -+#define FM_CONTEXTB_SET_FQID(contextB,val) (*((t_FmContextB *)contextB) = ((*((t_FmContextB *)contextB) & ~FM_CONTEXTB_FQID_MASK) | ((val) & FM_CONTEXTB_FQID_MASK))) -+/* @} */ -+ -+#if defined(__MWERKS__) && !defined(__GNUC__) -+#pragma pack(pop) -+#endif /* defined(__MWERKS__) && ... */ -+ -+ -+/**************************************************************************//** -+ @Description FM Exceptions -+*//***************************************************************************/ -+typedef enum e_FmExceptions { -+ e_FM_EX_DMA_BUS_ERROR = 0, /**< DMA bus error. */ -+ e_FM_EX_DMA_READ_ECC, /**< Read Buffer ECC error (Valid for FM rev < 6)*/ -+ e_FM_EX_DMA_SYSTEM_WRITE_ECC, /**< Write Buffer ECC error on system side (Valid for FM rev < 6)*/ -+ e_FM_EX_DMA_FM_WRITE_ECC, /**< Write Buffer ECC error on FM side (Valid for FM rev < 6)*/ -+ e_FM_EX_DMA_SINGLE_PORT_ECC, /**< Single Port ECC error on FM side (Valid for FM rev > 6)*/ -+ e_FM_EX_FPM_STALL_ON_TASKS, /**< Stall of tasks on FPM */ -+ e_FM_EX_FPM_SINGLE_ECC, /**< Single ECC on FPM. */ -+ e_FM_EX_FPM_DOUBLE_ECC, /**< Double ECC error on FPM ram access */ -+ e_FM_EX_QMI_SINGLE_ECC, /**< Single ECC on QMI. */ -+ e_FM_EX_QMI_DOUBLE_ECC, /**< Double bit ECC occurred on QMI */ -+ e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID,/**< Dequeue from unknown port id */ -+ e_FM_EX_BMI_LIST_RAM_ECC, /**< Linked List RAM ECC error */ -+ e_FM_EX_BMI_STORAGE_PROFILE_ECC, /**< Storage Profile ECC Error */ -+ e_FM_EX_BMI_STATISTICS_RAM_ECC, /**< Statistics Count RAM ECC Error Enable */ -+ e_FM_EX_BMI_DISPATCH_RAM_ECC, /**< Dispatch RAM ECC Error Enable */ -+ e_FM_EX_IRAM_ECC, /**< Double bit ECC occurred on IRAM*/ -+ e_FM_EX_MURAM_ECC /**< Double bit ECC occurred on MURAM*/ -+} e_FmExceptions; -+ -+/**************************************************************************//** -+ @Description Enum for defining port DMA swap mode -+*//***************************************************************************/ -+typedef enum e_FmDmaSwapOption { -+ e_FM_DMA_NO_SWP = FMAN_DMA_NO_SWP, /**< No swap, transfer data as is.*/ -+ e_FM_DMA_SWP_PPC_LE = FMAN_DMA_SWP_PPC_LE, /**< The transferred data should be swapped -+ in PowerPc Little Endian mode. */ -+ e_FM_DMA_SWP_BE = FMAN_DMA_SWP_BE /**< The transferred data should be swapped -+ in Big Endian mode */ -+} e_FmDmaSwapOption; -+ -+/**************************************************************************//** -+ @Description Enum for defining port DMA cache attributes -+*//***************************************************************************/ -+typedef enum e_FmDmaCacheOption { -+ e_FM_DMA_NO_STASH = FMAN_DMA_NO_STASH, /**< Cacheable, no Allocate (No Stashing) */ -+ e_FM_DMA_STASH = FMAN_DMA_STASH /**< Cacheable and Allocate (Stashing on) */ -+} e_FmDmaCacheOption; -+ -+ -+/**************************************************************************//** -+ @Group FM_init_grp FM Initialization Unit -+ -+ @Description FM Initialization Unit -+ -+ Initialization Flow -+ Initialization of the FM Module will be carried out by the application -+ according to the following sequence: -+ - Calling the configuration routine with basic parameters. -+ - Calling the advance initialization routines to change driver's defaults. -+ - Calling the initialization routine. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function t_FmExceptionsCallback -+ -+ @Description Exceptions user callback routine, will be called upon an -+ exception passing the exception identification. -+ -+ @Param[in] h_App - User's application descriptor. -+ @Param[in] exception - The exception. -+*//***************************************************************************/ -+typedef void (t_FmExceptionsCallback)(t_Handle h_App, -+ e_FmExceptions exception); -+ -+ -+/**************************************************************************//** -+ @Function t_FmBusErrorCallback -+ -+ @Description Bus error user callback routine, will be called upon a -+ bus error, passing parameters describing the errors and the owner. -+ -+ @Param[in] h_App - User's application descriptor. -+ @Param[in] portType - Port type (e_FmPortType) -+ @Param[in] portId - Port id - relative to type. -+ @Param[in] addr - Address that caused the error -+ @Param[in] tnum - Owner of error -+ @Param[in] liodn - Logical IO device number -+*//***************************************************************************/ -+typedef void (t_FmBusErrorCallback) (t_Handle h_App, -+ e_FmPortType portType, -+ uint8_t portId, -+ uint64_t addr, -+ uint8_t tnum, -+ uint16_t liodn); -+ -+/**************************************************************************//** -+ @Description A structure for defining buffer prefix area content. -+*//***************************************************************************/ -+typedef struct t_FmBufferPrefixContent { -+ uint16_t privDataSize; /**< Number of bytes to be left at the beginning -+ of the external buffer; Note that the private-area will -+ start from the base of the buffer address. */ -+ bool passPrsResult; /**< TRUE to pass the parse result to/from the FM; -+ User may use FM_PORT_GetBufferPrsResult() in order to -+ get the parser-result from a buffer. */ -+ bool passTimeStamp; /**< TRUE to pass the timeStamp to/from the FM -+ User may use FM_PORT_GetBufferTimeStamp() in order to -+ get the parser-result from a buffer. */ -+ bool passHashResult; /**< TRUE to pass the KG hash result to/from the FM -+ User may use FM_PORT_GetBufferHashResult() in order to -+ get the parser-result from a buffer. */ -+ bool passAllOtherPCDInfo;/**< Add all other Internal-Context information: -+ AD, hash-result, key, etc. */ -+ uint16_t dataAlign; /**< 0 to use driver's default alignment [DEFAULT_FM_SP_bufferPrefixContent_dataAlign], -+ other value for selecting a data alignment (must be a power of 2); -+ if write optimization is used, must be >= 16. */ -+ uint8_t manipExtraSpace; /**< Maximum extra size needed (insertion-size minus removal-size); -+ Note that this field impacts the size of the buffer-prefix -+ (i.e. it pushes the data offset); -+ This field is irrelevant if DPAA_VERSION==10 */ -+} t_FmBufferPrefixContent; -+ -+/**************************************************************************//** -+ @Description A structure of information about each of the external -+ buffer pools used by a port or storage-profile. -+*//***************************************************************************/ -+typedef struct t_FmExtPoolParams { -+ uint8_t id; /**< External buffer pool id */ -+ uint16_t size; /**< External buffer pool buffer size */ -+} t_FmExtPoolParams; -+ -+/**************************************************************************//** -+ @Description A structure for informing the driver about the external -+ buffer pools allocated in the BM and used by a port or a -+ storage-profile. -+*//***************************************************************************/ -+typedef struct t_FmExtPools { -+ uint8_t numOfPoolsUsed; /**< Number of pools use by this port */ -+ t_FmExtPoolParams extBufPool[FM_PORT_MAX_NUM_OF_EXT_POOLS]; -+ /**< Parameters for each port */ -+} t_FmExtPools; -+ -+/**************************************************************************//** -+ @Description A structure for defining backup BM Pools. -+*//***************************************************************************/ -+typedef struct t_FmBackupBmPools { -+ uint8_t numOfBackupPools; /**< Number of BM backup pools - -+ must be smaller than the total number of -+ pools defined for the specified port.*/ -+ uint8_t poolIds[FM_PORT_MAX_NUM_OF_EXT_POOLS]; -+ /**< numOfBackupPools pool id's, specifying which -+ pools should be used only as backup. Pool -+ id's specified here must be a subset of the -+ pools used by the specified port.*/ -+} t_FmBackupBmPools; -+ -+/**************************************************************************//** -+ @Description A structure for defining BM pool depletion criteria -+*//***************************************************************************/ -+typedef struct t_FmBufPoolDepletion { -+ bool poolsGrpModeEnable; /**< select mode in which pause frames will be sent after -+ a number of pools (all together!) are depleted */ -+ uint8_t numOfPools; /**< the number of depleted pools that will invoke -+ pause frames transmission. */ -+ bool poolsToConsider[BM_MAX_NUM_OF_POOLS]; -+ /**< For each pool, TRUE if it should be considered for -+ depletion (Note - this pool must be used by this port!). */ -+ bool singlePoolModeEnable; /**< select mode in which pause frames will be sent after -+ a single-pool is depleted; */ -+ bool poolsToConsiderForSingleMode[BM_MAX_NUM_OF_POOLS]; -+ /**< For each pool, TRUE if it should be considered for -+ depletion (Note - this pool must be used by this port!) */ -+#if (DPAA_VERSION >= 11) -+ bool pfcPrioritiesEn[FM_MAX_NUM_OF_PFC_PRIORITIES]; -+ /**< This field is used by the MAC as the Priority Enable Vector in the PFC frame which is transmitted */ -+#endif /* (DPAA_VERSION >= 11) */ -+} t_FmBufPoolDepletion; -+ -+/**************************************************************************//** -+ @Description A Structure for defining Ucode patch for loading. -+*//***************************************************************************/ -+typedef struct t_FmFirmwareParams { -+ uint32_t size; /**< Size of uCode */ -+ uint32_t *p_Code; /**< A pointer to the uCode */ -+} t_FmFirmwareParams; -+ -+/**************************************************************************//** -+ @Description A Structure for defining FM initialization parameters -+*//***************************************************************************/ -+typedef struct t_FmParams { -+ uint8_t fmId; /**< Index of the FM */ -+ uint8_t guestId; /**< FM Partition Id */ -+ uintptr_t baseAddr; /**< A pointer to base of memory mapped FM registers (virtual); -+ this field is optional when the FM runs in "guest-mode" -+ (i.e. guestId != NCSW_MASTER_ID); in that case, the driver will -+ use the memory-map instead of calling the IPC where possible; -+ NOTE that this should include ALL common registers of the FM including -+ the PCD registers area (i.e. until the VSP pages - 880KB). */ -+ t_Handle h_FmMuram; /**< A handle of an initialized MURAM object, -+ to be used by the FM. */ -+ uint16_t fmClkFreq; /**< In Mhz; -+ Relevant when FM not runs in "guest-mode". */ -+ uint16_t fmMacClkRatio; /**< FM MAC Clock ratio, for backward comparability: -+ when fmMacClkRatio = 0, ratio is 2:1 -+ when fmMacClkRatio = 1, ratio is 1:1 */ -+ t_FmExceptionsCallback *f_Exception; /**< An application callback routine to handle exceptions; -+ Relevant when FM not runs in "guest-mode". */ -+ t_FmBusErrorCallback *f_BusError; /**< An application callback routine to handle exceptions; -+ Relevant when FM not runs in "guest-mode". */ -+ t_Handle h_App; /**< A handle to an application layer object; This handle will -+ be passed by the driver upon calling the above callbacks; -+ Relevant when FM not runs in "guest-mode". */ -+ int irq; /**< FM interrupt source for normal events; -+ Relevant when FM not runs in "guest-mode". */ -+ int errIrq; /**< FM interrupt source for errors; -+ Relevant when FM not runs in "guest-mode". */ -+ t_FmFirmwareParams firmware; /**< The firmware parameters structure; -+ Relevant when FM not runs in "guest-mode". */ -+ -+#if (DPAA_VERSION >= 11) -+ uintptr_t vspBaseAddr; /**< A pointer to base of memory mapped FM VSP registers (virtual); -+ i.e. up to 24KB, depending on the specific chip. */ -+ uint8_t partVSPBase; /**< The first Virtual-Storage-Profile-id dedicated to this partition. -+ NOTE: this parameter relevant only when working with multiple partitions. */ -+ uint8_t partNumOfVSPs; /**< Number of VSPs dedicated to this partition. -+ NOTE: this parameter relevant only when working with multiple partitions. */ -+#endif /* (DPAA_VERSION >= 11) */ -+} t_FmParams; -+ -+ -+/**************************************************************************//** -+ @Function FM_Config -+ -+ @Description Creates the FM module and returns its handle (descriptor). -+ This descriptor must be passed as first parameter to all other -+ FM function calls. -+ -+ No actual initialization or configuration of FM hardware is -+ done by this routine. All FM parameters get default values that -+ may be changed by calling one or more of the advance config routines. -+ -+ @Param[in] p_FmParams - A pointer to a data structure of mandatory FM parameters -+ -+ @Return A handle to the FM object, or NULL for Failure. -+*//***************************************************************************/ -+t_Handle FM_Config(t_FmParams *p_FmParams); -+ -+/**************************************************************************//** -+ @Function FM_Init -+ -+ @Description Initializes the FM module by defining the software structure -+ and configuring the hardware registers. -+ -+ @Param[in] h_Fm - FM module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_Init(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FM_Free -+ -+ @Description Frees all resources that were assigned to FM module. -+ -+ Calling this routine invalidates the descriptor. -+ -+ @Param[in] h_Fm - FM module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_Free(t_Handle h_Fm); -+ -+ -+/**************************************************************************//** -+ @Group FM_advanced_init_grp FM Advanced Configuration Unit -+ -+ @Description Advanced configuration routines are optional routines that may -+ be called in order to change the default driver settings. -+ -+ Note: Advanced configuration routines are not available for guest partition. -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description Enum for selecting DMA debug mode -+*//***************************************************************************/ -+typedef enum e_FmDmaDbgCntMode { -+ e_FM_DMA_DBG_NO_CNT = 0, /**< No counting */ -+ e_FM_DMA_DBG_CNT_DONE, /**< Count DONE commands */ -+ e_FM_DMA_DBG_CNT_COMM_Q_EM, /**< count command queue emergency signals */ -+ e_FM_DMA_DBG_CNT_INT_READ_EM, /**< Count Internal Read buffer emergency signal */ -+ e_FM_DMA_DBG_CNT_INT_WRITE_EM, /**< Count Internal Write buffer emergency signal */ -+ e_FM_DMA_DBG_CNT_FPM_WAIT, /**< Count FPM WAIT signal */ -+ e_FM_DMA_DBG_CNT_SIGLE_BIT_ECC, /**< Single bit ECC errors. */ -+ e_FM_DMA_DBG_CNT_RAW_WAR_PROT /**< Number of times there was a need for RAW & WAR protection. */ -+} e_FmDmaDbgCntMode; -+ -+/**************************************************************************//** -+ @Description Enum for selecting DMA Cache Override -+*//***************************************************************************/ -+typedef enum e_FmDmaCacheOverride { -+ e_FM_DMA_NO_CACHE_OR = 0, /**< No override of the Cache field */ -+ e_FM_DMA_NO_STASH_DATA, /**< Data should not be stashed in system level cache */ -+ e_FM_DMA_MAY_STASH_DATA, /**< Data may be stashed in system level cache */ -+ e_FM_DMA_STASH_DATA /**< Data should be stashed in system level cache */ -+} e_FmDmaCacheOverride; -+ -+/**************************************************************************//** -+ @Description Enum for selecting DMA External Bus Priority -+*//***************************************************************************/ -+typedef enum e_FmDmaExtBusPri { -+ e_FM_DMA_EXT_BUS_NORMAL = 0, /**< Normal priority */ -+ e_FM_DMA_EXT_BUS_EBS, /**< AXI extended bus service priority */ -+ e_FM_DMA_EXT_BUS_SOS, /**< AXI sos priority */ -+ e_FM_DMA_EXT_BUS_EBS_AND_SOS /**< AXI ebs + sos priority */ -+} e_FmDmaExtBusPri; -+ -+/**************************************************************************//** -+ @Description Enum for choosing the field that will be output on AID -+*//***************************************************************************/ -+typedef enum e_FmDmaAidMode { -+ e_FM_DMA_AID_OUT_PORT_ID = 0, /**< 4 LSB of PORT_ID */ -+ e_FM_DMA_AID_OUT_TNUM /**< 4 LSB of TNUM */ -+} e_FmDmaAidMode; -+ -+/**************************************************************************//** -+ @Description Enum for selecting FPM Catastrophic error behavior -+*//***************************************************************************/ -+typedef enum e_FmCatastrophicErr { -+ e_FM_CATASTROPHIC_ERR_STALL_PORT = 0, /**< Port_ID is stalled (only reset can release it) */ -+ e_FM_CATASTROPHIC_ERR_STALL_TASK /**< Only erroneous task is stalled */ -+} e_FmCatastrophicErr; -+ -+/**************************************************************************//** -+ @Description Enum for selecting FPM DMA Error behavior -+*//***************************************************************************/ -+typedef enum e_FmDmaErr { -+ e_FM_DMA_ERR_CATASTROPHIC = 0, /**< Dma error is treated as a catastrophic -+ error (e_FmCatastrophicErr)*/ -+ e_FM_DMA_ERR_REPORT /**< Dma error is just reported */ -+} e_FmDmaErr; -+ -+/**************************************************************************//** -+ @Description Enum for selecting DMA Emergency level by BMI emergency signal -+*//***************************************************************************/ -+typedef enum e_FmDmaEmergencyLevel { -+ e_FM_DMA_EM_EBS = 0, /**< EBS emergency */ -+ e_FM_DMA_EM_SOS /**< SOS emergency */ -+} e_FmDmaEmergencyLevel; -+ -+/**************************************************************************//** -+ @Collection Enum for selecting DMA Emergency options -+*//***************************************************************************/ -+typedef uint32_t fmEmergencyBus_t; /**< DMA emergency options */ -+ -+#define FM_DMA_MURAM_READ_EMERGENCY 0x00800000 /**< Enable emergency for MURAM1 */ -+#define FM_DMA_MURAM_WRITE_EMERGENCY 0x00400000 /**< Enable emergency for MURAM2 */ -+#define FM_DMA_EXT_BUS_EMERGENCY 0x00100000 /**< Enable emergency for external bus */ -+/* @} */ -+ -+/**************************************************************************//** -+ @Description A structure for defining DMA emergency level -+*//***************************************************************************/ -+typedef struct t_FmDmaEmergency { -+ fmEmergencyBus_t emergencyBusSelect; /**< An OR of the busses where emergency -+ should be enabled */ -+ e_FmDmaEmergencyLevel emergencyLevel; /**< EBS/SOS */ -+} t_FmDmaEmergency; -+ -+/**************************************************************************//* -+ @Description structure for defining FM threshold -+*//***************************************************************************/ -+typedef struct t_FmThresholds { -+ uint8_t dispLimit; /**< The number of times a frames may -+ be passed in the FM before assumed to -+ be looping. */ -+ uint8_t prsDispTh; /**< This is the number pf packets that may be -+ queued in the parser dispatch queue*/ -+ uint8_t plcrDispTh; /**< This is the number pf packets that may be -+ queued in the policer dispatch queue*/ -+ uint8_t kgDispTh; /**< This is the number pf packets that may be -+ queued in the keygen dispatch queue*/ -+ uint8_t bmiDispTh; /**< This is the number pf packets that may be -+ queued in the BMI dispatch queue*/ -+ uint8_t qmiEnqDispTh; /**< This is the number pf packets that may be -+ queued in the QMI enqueue dispatch queue*/ -+ uint8_t qmiDeqDispTh; /**< This is the number pf packets that may be -+ queued in the QMI dequeue dispatch queue*/ -+ uint8_t fmCtl1DispTh; /**< This is the number pf packets that may be -+ queued in fmCtl1 dispatch queue*/ -+ uint8_t fmCtl2DispTh; /**< This is the number pf packets that may be -+ queued in fmCtl2 dispatch queue*/ -+} t_FmThresholds; -+ -+/**************************************************************************//* -+ @Description structure for defining DMA thresholds -+*//***************************************************************************/ -+typedef struct t_FmDmaThresholds { -+ uint8_t assertEmergency; /**< When this value is reached, -+ assert emergency (Threshold)*/ -+ uint8_t clearEmergency; /**< After emergency is asserted, it is held -+ until this value is reached (Hystheresis) */ -+} t_FmDmaThresholds; -+ -+ -+/**************************************************************************//** -+ @Function FM_ConfigResetOnInit -+ -+ @Description Define whether to reset the FM before initialization. -+ Change the default configuration [DEFAULT_resetOnInit]. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] enable When TRUE, FM will be reset before any initialization. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigResetOnInit(t_Handle h_Fm, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_ConfigTotalFifoSize -+ -+ @Description Define Total FIFO size for the whole FM. -+ Calling this routine changes the total Fifo size in the internal driver -+ data base from its default configuration [DEFAULT_totalFifoSize] -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] totalFifoSize The selected new value. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigTotalFifoSize(t_Handle h_Fm, uint32_t totalFifoSize); -+ -+ /**************************************************************************//** -+ @Function FM_ConfigDmaCacheOverride -+ -+ @Description Define cache override mode. -+ Calling this routine changes the cache override mode -+ in the internal driver data base from its default configuration [DEFAULT_cacheOverride] -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] cacheOverride The selected new value. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaCacheOverride(t_Handle h_Fm, e_FmDmaCacheOverride cacheOverride); -+ -+/**************************************************************************//** -+ @Function FM_ConfigDmaAidOverride -+ -+ @Description Define DMA AID override mode. -+ Calling this routine changes the AID override mode -+ in the internal driver data base from its default configuration [DEFAULT_aidOverride] -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] aidOverride The selected new value. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaAidOverride(t_Handle h_Fm, bool aidOverride); -+ -+/**************************************************************************//** -+ @Function FM_ConfigDmaAidMode -+ -+ @Description Define DMA AID mode. -+ Calling this routine changes the AID mode in the internal -+ driver data base from its default configuration [DEFAULT_aidMode] -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] aidMode The selected new value. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaAidMode(t_Handle h_Fm, e_FmDmaAidMode aidMode); -+ -+/**************************************************************************//** -+ @Function FM_ConfigDmaAxiDbgNumOfBeats -+ -+ @Description Define DMA AXI number of beats. -+ Calling this routine changes the AXI number of beats in the internal -+ driver data base from its default configuration [DEFAULT_axiDbgNumOfBeats] -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] axiDbgNumOfBeats The selected new value. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaAxiDbgNumOfBeats(t_Handle h_Fm, uint8_t axiDbgNumOfBeats); -+ -+/**************************************************************************//** -+ @Function FM_ConfigDmaCamNumOfEntries -+ -+ @Description Define number of CAM entries. -+ Calling this routine changes the number of CAM entries in the internal -+ driver data base from its default configuration [DEFAULT_dmaCamNumOfEntries]. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] numOfEntries The selected new value. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaCamNumOfEntries(t_Handle h_Fm, uint8_t numOfEntries); -+ -+/**************************************************************************//** -+ @Function FM_ConfigEnableCounters -+ -+ @Description Obsolete, always return E_OK. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_ConfigEnableCounters(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FM_ConfigDmaDbgCounter -+ -+ @Description Define DMA debug counter. -+ Calling this routine changes the number of the DMA debug counter in the internal -+ driver data base from its default configuration [DEFAULT_dmaDbgCntMode]. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] fmDmaDbgCntMode An enum selecting the debug counter mode. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaDbgCounter(t_Handle h_Fm, e_FmDmaDbgCntMode fmDmaDbgCntMode); -+ -+/**************************************************************************//** -+ @Function FM_ConfigDmaStopOnBusErr -+ -+ @Description Define bus error behavior. -+ Calling this routine changes the bus error behavior definition -+ in the internal driver data base from its default -+ configuration [DEFAULT_dmaStopOnBusError]. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] stop TRUE to stop on bus error, FALSE to continue. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ Only if bus error is enabled. -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaStopOnBusErr(t_Handle h_Fm, bool stop); -+ -+/**************************************************************************//** -+ @Function FM_ConfigDmaEmergency -+ -+ @Description Define DMA emergency. -+ Calling this routine changes the DMA emergency definition -+ in the internal driver data base from its default -+ configuration where's it's disabled. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] p_Emergency An OR mask of all required options. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaEmergency(t_Handle h_Fm, t_FmDmaEmergency *p_Emergency); -+ -+/**************************************************************************//** -+ @Function FM_ConfigDmaErr -+ -+ @Description DMA error treatment. -+ Calling this routine changes the DMA error treatment -+ in the internal driver data base from its default -+ configuration [DEFAULT_dmaErr]. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] dmaErr The selected new choice. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaErr(t_Handle h_Fm, e_FmDmaErr dmaErr); -+ -+/**************************************************************************//** -+ @Function FM_ConfigCatastrophicErr -+ -+ @Description Define FM behavior on catastrophic error. -+ Calling this routine changes the FM behavior on catastrophic -+ error in the internal driver data base from its default -+ [DEFAULT_catastrophicErr]. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] catastrophicErr The selected new choice. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigCatastrophicErr(t_Handle h_Fm, e_FmCatastrophicErr catastrophicErr); -+ -+/**************************************************************************//** -+ @Function FM_ConfigEnableMuramTestMode -+ -+ @Description Enable MURAM test mode. -+ Calling this routine changes the internal driver data base -+ from its default selection of test mode where it's disabled. -+ This routine is only avaiable on old FM revisions (FMan v2). -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigEnableMuramTestMode(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FM_ConfigEnableIramTestMode -+ -+ @Description Enable IRAM test mode. -+ Calling this routine changes the internal driver data base -+ from its default selection of test mode where it's disabled. -+ This routine is only avaiable on old FM revisions (FMan v2). -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigEnableIramTestMode(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FM_ConfigHaltOnExternalActivation -+ -+ @Description Define FM behavior on external halt activation. -+ Calling this routine changes the FM behavior on external halt -+ activation in the internal driver data base from its default -+ [DEFAULT_haltOnExternalActivation]. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] enable TRUE to enable halt on external halt -+ activation. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigHaltOnExternalActivation(t_Handle h_Fm, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_ConfigHaltOnUnrecoverableEccError -+ -+ @Description Define FM behavior on external halt activation. -+ Calling this routine changes the FM behavior on unrecoverable -+ ECC error in the internal driver data base from its default -+ [DEFAULT_haltOnUnrecoverableEccError]. -+ This routine is only avaiable on old FM revisions (FMan v2). -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] enable TRUE to enable halt on unrecoverable Ecc error -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigHaltOnUnrecoverableEccError(t_Handle h_Fm, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_ConfigException -+ -+ @Description Define FM exceptions. -+ Calling this routine changes the exceptions defaults in the -+ internal driver data base where all exceptions are enabled. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] exception The exception to be selected. -+ @Param[in] enable TRUE to enable interrupt, FALSE to mask it. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigException(t_Handle h_Fm, e_FmExceptions exception, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_ConfigExternalEccRamsEnable -+ -+ @Description Select external ECC enabling. -+ Calling this routine changes the ECC enabling control in the internal -+ driver data base from its default [DEFAULT_externalEccRamsEnable]. -+ When this option is enabled Rams ECC enabling is not effected -+ by FM_EnableRamsEcc/FM_DisableRamsEcc, but by a JTAG. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] enable TRUE to enable this option. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigExternalEccRamsEnable(t_Handle h_Fm, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_ConfigTnumAgingPeriod -+ -+ @Description Define Tnum aging period. -+ Calling this routine changes the Tnum aging of dequeue TNUMs -+ in the QMI in the internal driver data base from its default -+ [DEFAULT_tnumAgingPeriod]. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] tnumAgingPeriod Tnum Aging Period in microseconds. -+ Note that period is recalculated in units of -+ 64 FM clocks. Driver will pick the closest -+ possible period. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+ NOTE that if some MAC is configured for PFC, '0' value is NOT -+ allowed. -+*//***************************************************************************/ -+t_Error FM_ConfigTnumAgingPeriod(t_Handle h_Fm, uint16_t tnumAgingPeriod); -+ -+/**************************************************************************//* -+ @Function FM_ConfigDmaEmergencySmoother -+ -+ @Description Define DMA emergency smoother. -+ Calling this routine changes the definition of the minimum -+ amount of DATA beats transferred on the AXI READ and WRITE -+ ports before lowering the emergency level. -+ By default smoother is disabled. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] emergencyCnt emergency switching counter. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaEmergencySmoother(t_Handle h_Fm, uint32_t emergencyCnt); -+ -+/**************************************************************************//* -+ @Function FM_ConfigThresholds -+ -+ @Description Calling this routine changes the internal driver data base -+ from its default FM threshold configuration: -+ dispLimit: [DEFAULT_dispLimit] -+ prsDispTh: [DEFAULT_prsDispTh] -+ plcrDispTh: [DEFAULT_plcrDispTh] -+ kgDispTh: [DEFAULT_kgDispTh] -+ bmiDispTh: [DEFAULT_bmiDispTh] -+ qmiEnqDispTh: [DEFAULT_qmiEnqDispTh] -+ qmiDeqDispTh: [DEFAULT_qmiDeqDispTh] -+ fmCtl1DispTh: [DEFAULT_fmCtl1DispTh] -+ fmCtl2DispTh: [DEFAULT_fmCtl2DispTh] -+ -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] p_FmThresholds A structure of threshold parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigThresholds(t_Handle h_Fm, t_FmThresholds *p_FmThresholds); -+ -+/**************************************************************************//* -+ @Function FM_ConfigDmaSosEmergencyThreshold -+ -+ @Description Calling this routine changes the internal driver data base -+ from its default dma SOS emergency configuration [DEFAULT_dmaSosEmergency] -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] dmaSosEmergency The selected new value. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaSosEmergencyThreshold(t_Handle h_Fm, uint32_t dmaSosEmergency); -+ -+/**************************************************************************//* -+ @Function FM_ConfigDmaWriteBufThresholds -+ -+ @Description Calling this routine changes the internal driver data base -+ from its default configuration of DMA write buffer threshold -+ assertEmergency: [DEFAULT_dmaWriteIntBufLow] -+ clearEmergency: [DEFAULT_dmaWriteIntBufHigh] -+ This routine is only avaiable on old FM revisions (FMan v2). -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] p_FmDmaThresholds A structure of thresholds to define emergency behavior - -+ When 'assertEmergency' value is reached, emergency is asserted, -+ then it is held until 'clearEmergency' value is reached. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaWriteBufThresholds(t_Handle h_Fm, t_FmDmaThresholds *p_FmDmaThresholds); -+ -+ /**************************************************************************//* -+ @Function FM_ConfigDmaCommQThresholds -+ -+ @Description Calling this routine changes the internal driver data base -+ from its default configuration of DMA command queue threshold -+ assertEmergency: [DEFAULT_dmaCommQLow] -+ clearEmergency: [DEFAULT_dmaCommQHigh] -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] p_FmDmaThresholds A structure of thresholds to define emergency behavior - -+ When 'assertEmergency' value is reached, emergency is asserted, -+ then it is held until 'clearEmergency' value is reached.. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaCommQThresholds(t_Handle h_Fm, t_FmDmaThresholds *p_FmDmaThresholds); -+ -+/**************************************************************************//* -+ @Function FM_ConfigDmaReadBufThresholds -+ -+ @Description Calling this routine changes the internal driver data base -+ from its default configuration of DMA read buffer threshold -+ assertEmergency: [DEFAULT_dmaReadIntBufLow] -+ clearEmergency: [DEFAULT_dmaReadIntBufHigh] -+ This routine is only avaiable on old FM revisions (FMan v2). -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] p_FmDmaThresholds A structure of thresholds to define emergency behavior - -+ When 'assertEmergency' value is reached, emergency is asserted, -+ then it is held until 'clearEmergency' value is reached.. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaReadBufThresholds(t_Handle h_Fm, t_FmDmaThresholds *p_FmDmaThresholds); -+ -+/**************************************************************************//* -+ @Function FM_ConfigDmaWatchdog -+ -+ @Description Calling this routine changes the internal driver data base -+ from its default watchdog configuration, which is disabled -+ [DEFAULT_dmaWatchdog]. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] watchDogValue The selected new value - in microseconds. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ConfigDmaWatchdog(t_Handle h_Fm, uint32_t watchDogValue); -+ -+/** @} */ /* end of FM_advanced_init_grp group */ -+/** @} */ /* end of FM_init_grp group */ -+ -+ -+/**************************************************************************//** -+ @Group FM_runtime_control_grp FM Runtime Control Unit -+ -+ @Description FM Runtime control unit API functions, definitions and enums. -+ The FM driver provides a set of control routines. -+ These routines may only be called after the module was fully -+ initialized (both configuration and initialization routines were -+ called). They are typically used to get information from hardware -+ (status, counters/statistics, revision etc.), to modify a current -+ state or to force/enable a required action. Run-time control may -+ be called whenever necessary and as many times as needed. -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Collection General FM defines. -+*//***************************************************************************/ -+#define FM_MAX_NUM_OF_VALID_PORTS (FM_MAX_NUM_OF_OH_PORTS + \ -+ FM_MAX_NUM_OF_1G_RX_PORTS + \ -+ FM_MAX_NUM_OF_10G_RX_PORTS + \ -+ FM_MAX_NUM_OF_1G_TX_PORTS + \ -+ FM_MAX_NUM_OF_10G_TX_PORTS) /**< Number of available FM ports */ -+/* @} */ -+ -+/**************************************************************************//* -+ @Description A Structure for Port bandwidth requirement. Port is identified -+ by type and relative id. -+*//***************************************************************************/ -+typedef struct t_FmPortBandwidth { -+ e_FmPortType type; /**< FM port type */ -+ uint8_t relativePortId; /**< Type relative port id */ -+ uint8_t bandwidth; /**< bandwidth - (in term of percents) */ -+} t_FmPortBandwidth; -+ -+/**************************************************************************//* -+ @Description A Structure containing an array of Port bandwidth requirements. -+ The user should state the ports requiring bandwidth in terms of -+ percentage - i.e. all port's bandwidths in the array must add -+ up to 100. -+*//***************************************************************************/ -+typedef struct t_FmPortsBandwidthParams { -+ uint8_t numOfPorts; /**< The number of relevant ports, which is the -+ number of valid entries in the array below */ -+ t_FmPortBandwidth portsBandwidths[FM_MAX_NUM_OF_VALID_PORTS]; -+ /**< for each port, it's bandwidth (all port's -+ bandwidths must add up to 100.*/ -+} t_FmPortsBandwidthParams; -+ -+/**************************************************************************//** -+ @Description DMA Emergency control on MURAM -+*//***************************************************************************/ -+typedef enum e_FmDmaMuramPort { -+ e_FM_DMA_MURAM_PORT_WRITE, /**< MURAM write port */ -+ e_FM_DMA_MURAM_PORT_READ /**< MURAM read port */ -+} e_FmDmaMuramPort; -+ -+/**************************************************************************//** -+ @Description Enum for defining FM counters -+*//***************************************************************************/ -+typedef enum e_FmCounters { -+ e_FM_COUNTERS_ENQ_TOTAL_FRAME = 0, /**< QMI total enqueued frames counter */ -+ e_FM_COUNTERS_DEQ_TOTAL_FRAME, /**< QMI total dequeued frames counter */ -+ e_FM_COUNTERS_DEQ_0, /**< QMI 0 frames from QMan counter */ -+ e_FM_COUNTERS_DEQ_1, /**< QMI 1 frames from QMan counter */ -+ e_FM_COUNTERS_DEQ_2, /**< QMI 2 frames from QMan counter */ -+ e_FM_COUNTERS_DEQ_3, /**< QMI 3 frames from QMan counter */ -+ e_FM_COUNTERS_DEQ_FROM_DEFAULT, /**< QMI dequeue from default queue counter */ -+ e_FM_COUNTERS_DEQ_FROM_CONTEXT, /**< QMI dequeue from FQ context counter */ -+ e_FM_COUNTERS_DEQ_FROM_FD, /**< QMI dequeue from FD command field counter */ -+ e_FM_COUNTERS_DEQ_CONFIRM /**< QMI dequeue confirm counter */ -+} e_FmCounters; -+ -+/**************************************************************************//** -+ @Description A Structure for returning FM revision information -+*//***************************************************************************/ -+typedef struct t_FmRevisionInfo { -+ uint8_t majorRev; /**< Major revision */ -+ uint8_t minorRev; /**< Minor revision */ -+} t_FmRevisionInfo; -+ -+/**************************************************************************//** -+ @Description A Structure for returning FM ctrl code revision information -+*//***************************************************************************/ -+typedef struct t_FmCtrlCodeRevisionInfo { -+ uint16_t packageRev; /**< Package revision */ -+ uint8_t majorRev; /**< Major revision */ -+ uint8_t minorRev; /**< Minor revision */ -+} t_FmCtrlCodeRevisionInfo; -+ -+/**************************************************************************//** -+ @Description A Structure for defining DMA status -+*//***************************************************************************/ -+typedef struct t_FmDmaStatus { -+ bool cmqNotEmpty; /**< Command queue is not empty */ -+ bool busError; /**< Bus error occurred */ -+ bool readBufEccError; /**< Double ECC error on buffer Read (Valid for FM rev < 6)*/ -+ bool writeBufEccSysError; /**< Double ECC error on buffer write from system side (Valid for FM rev < 6)*/ -+ bool writeBufEccFmError; /**< Double ECC error on buffer write from FM side (Valid for FM rev < 6) */ -+ bool singlePortEccError; /**< Single Port ECC error from FM side (Valid for FM rev >= 6)*/ -+} t_FmDmaStatus; -+ -+/**************************************************************************//** -+ @Description A Structure for obtaining FM controller monitor values -+*//***************************************************************************/ -+typedef struct t_FmCtrlMon { -+ uint8_t percentCnt[2]; /**< Percentage value */ -+} t_FmCtrlMon; -+ -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+/**************************************************************************//** -+ @Function FM_DumpRegs -+ -+ @Description Dumps all FM registers -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return E_OK on success; -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+t_Error FM_DumpRegs(t_Handle h_Fm); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+/**************************************************************************//** -+ @Function FM_SetException -+ -+ @Description Calling this routine enables/disables the specified exception. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] exception The exception to be selected. -+ @Param[in] enable TRUE to enable interrupt, FALSE to mask it. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_SetException(t_Handle h_Fm, e_FmExceptions exception, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_EnableRamsEcc -+ -+ @Description Enables ECC mechanism for all the different FM RAM's; E.g. IRAM, -+ MURAM, Parser, Keygen, Policer, etc. -+ Note: -+ If FM_ConfigExternalEccRamsEnable was called to enable external -+ setting of ECC, this routine effects IRAM ECC only. -+ This routine is also called by the driver if an ECC exception is -+ enabled. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_EnableRamsEcc(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FM_DisableRamsEcc -+ -+ @Description Disables ECC mechanism for all the different FM RAM's; E.g. IRAM, -+ MURAM, Parser, Keygen, Policer, etc. -+ Note: -+ If FM_ConfigExternalEccRamsEnable was called to enable external -+ setting of ECC, this routine effects IRAM ECC only. -+ In opposed to FM_EnableRamsEcc, this routine must be called -+ explicitly to disable all Rams ECC. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Config() and before FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_DisableRamsEcc(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FM_GetRevision -+ -+ @Description Returns the FM revision -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[out] p_FmRevisionInfo A structure of revision information parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+t_Error FM_GetRevision(t_Handle h_Fm, t_FmRevisionInfo *p_FmRevisionInfo); -+ -+/**************************************************************************//** -+ @Function FM_GetFmanCtrlCodeRevision -+ -+ @Description Returns the Fman controller code revision -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[out] p_RevisionInfo A structure of revision information parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+t_Error FM_GetFmanCtrlCodeRevision(t_Handle h_Fm, t_FmCtrlCodeRevisionInfo *p_RevisionInfo); -+ -+/**************************************************************************//** -+ @Function FM_GetCounter -+ -+ @Description Reads one of the FM counters. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] counter The requested counter. -+ -+ @Return Counter's current value. -+ -+ @Cautions Allowed only following FM_Init(). -+ Note that it is user's responsibility to call this routine only -+ for enabled counters, and there will be no indication if a -+ disabled counter is accessed. -+*//***************************************************************************/ -+uint32_t FM_GetCounter(t_Handle h_Fm, e_FmCounters counter); -+ -+/**************************************************************************//** -+ @Function FM_ModifyCounter -+ -+ @Description Sets a value to an enabled counter. Use "0" to reset the counter. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] counter The requested counter. -+ @Param[in] val The requested value to be written into the counter. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ModifyCounter(t_Handle h_Fm, e_FmCounters counter, uint32_t val); -+ -+/**************************************************************************//** -+ @Function FM_Resume -+ -+ @Description Release FM after halt FM command or after unrecoverable ECC error. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+void FM_Resume(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FM_SetDmaEmergency -+ -+ @Description Manual emergency set -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] muramPort MURAM direction select. -+ @Param[in] enable TRUE to manually enable emergency, FALSE to disable. -+ -+ @Return None. -+ -+ @Cautions Allowed only following FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+void FM_SetDmaEmergency(t_Handle h_Fm, e_FmDmaMuramPort muramPort, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_SetDmaExtBusPri -+ -+ @Description Set the DMA external bus priority -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] pri External bus priority select -+ -+ @Return None. -+ -+ @Cautions Allowed only following FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+void FM_SetDmaExtBusPri(t_Handle h_Fm, e_FmDmaExtBusPri pri); -+ -+/**************************************************************************//** -+ @Function FM_GetDmaStatus -+ -+ @Description Reads the DMA current status -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[out] p_FmDmaStatus A structure of DMA status parameters. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+void FM_GetDmaStatus(t_Handle h_Fm, t_FmDmaStatus *p_FmDmaStatus); -+ -+/**************************************************************************//** -+ @Function FM_ErrorIsr -+ -+ @Description FM interrupt-service-routine for errors. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return E_OK on success; E_EMPTY if no errors found in register, other -+ error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ErrorIsr(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FM_EventIsr -+ -+ @Description FM interrupt-service-routine for normal events. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Cautions Allowed only following FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+void FM_EventIsr(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FM_GetSpecialOperationCoding -+ -+ @Description Return a specific coding according to the input mask. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] spOper special operation mask. -+ @Param[out] p_SpOperCoding special operation code. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+t_Error FM_GetSpecialOperationCoding(t_Handle h_Fm, -+ fmSpecialOperations_t spOper, -+ uint8_t *p_SpOperCoding); -+ -+/**************************************************************************//** -+ @Function FM_CtrlMonStart -+ -+ @Description Start monitoring utilization of all available FM controllers. -+ -+ In order to obtain FM controllers utilization the following sequence -+ should be used: -+ -# FM_CtrlMonStart() -+ -# FM_CtrlMonStop() -+ -# FM_CtrlMonGetCounters() - issued for each FM controller -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID). -+*//***************************************************************************/ -+t_Error FM_CtrlMonStart(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FM_CtrlMonStop -+ -+ @Description Stop monitoring utilization of all available FM controllers. -+ -+ In order to obtain FM controllers utilization the following sequence -+ should be used: -+ -# FM_CtrlMonStart() -+ -# FM_CtrlMonStop() -+ -# FM_CtrlMonGetCounters() - issued for each FM controller -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID). -+*//***************************************************************************/ -+t_Error FM_CtrlMonStop(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FM_CtrlMonGetCounters -+ -+ @Description Obtain FM controller utilization parameters. -+ -+ In order to obtain FM controllers utilization the following sequence -+ should be used: -+ -# FM_CtrlMonStart() -+ -# FM_CtrlMonStop() -+ -# FM_CtrlMonGetCounters() - issued for each FM controller -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] fmCtrlIndex FM Controller index for that utilization results -+ are requested. -+ @Param[in] p_Mon Pointer to utilization results structure. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID). -+*//***************************************************************************/ -+t_Error FM_CtrlMonGetCounters(t_Handle h_Fm, uint8_t fmCtrlIndex, t_FmCtrlMon *p_Mon); -+ -+ -+/**************************************************************************//* -+ @Function FM_ForceIntr -+ -+ @Description Causes an interrupt event on the requested source. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] exception An exception to be forced. -+ -+ @Return E_OK on success; Error code if the exception is not enabled, -+ or is not able to create interrupt. -+ -+ @Cautions Allowed only following FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_ForceIntr (t_Handle h_Fm, e_FmExceptions exception); -+ -+/**************************************************************************//* -+ @Function FM_SetPortsBandwidth -+ -+ @Description Sets relative weights between ports when accessing common resources. -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ @Param[in] p_PortsBandwidth A structure of ports bandwidths in percentage, i.e. -+ total must equal 100. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_SetPortsBandwidth(t_Handle h_Fm, t_FmPortsBandwidthParams *p_PortsBandwidth); -+ -+/**************************************************************************//* -+ @Function FM_GetMuramHandle -+ -+ @Description Gets the corresponding MURAM handle -+ -+ @Param[in] h_Fm A handle to an FM Module. -+ -+ @Return MURAM handle; NULL otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Handle FM_GetMuramHandle(t_Handle h_Fm); -+ -+/** @} */ /* end of FM_runtime_control_grp group */ -+/** @} */ /* end of FM_lib_grp group */ -+/** @} */ /* end of FM_grp group */ -+ -+ -+#ifdef NCSW_BACKWARD_COMPATIBLE_API -+typedef t_FmFirmwareParams t_FmPcdFirmwareParams; -+typedef t_FmBufferPrefixContent t_FmPortBufferPrefixContent; -+typedef t_FmExtPoolParams t_FmPortExtPoolParams; -+typedef t_FmExtPools t_FmPortExtPools; -+typedef t_FmBackupBmPools t_FmPortBackupBmPools; -+typedef t_FmBufPoolDepletion t_FmPortBufPoolDepletion; -+typedef e_FmDmaSwapOption e_FmPortDmaSwapOption; -+typedef e_FmDmaCacheOption e_FmPortDmaCacheOption; -+ -+#define FM_CONTEXTA_GET_OVVERIDE FM_CONTEXTA_GET_OVERRIDE -+#define FM_CONTEXTA_SET_OVVERIDE FM_CONTEXTA_SET_OVERRIDE -+ -+#define e_FM_EX_BMI_PIPELINE_ECC e_FM_EX_BMI_STORAGE_PROFILE_ECC -+#define e_FM_PORT_DMA_NO_SWP e_FM_DMA_NO_SWP -+#define e_FM_PORT_DMA_SWP_PPC_LE e_FM_DMA_SWP_PPC_LE -+#define e_FM_PORT_DMA_SWP_BE e_FM_DMA_SWP_BE -+#define e_FM_PORT_DMA_NO_STASH e_FM_DMA_NO_STASH -+#define e_FM_PORT_DMA_STASH e_FM_DMA_STASH -+#endif /* NCSW_BACKWARD_COMPATIBLE_API */ -+ -+ -+#endif /* __FM_EXT */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_mac_ext.h -@@ -0,0 +1,846 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File fm_mac_ext.h -+ -+ @Description FM MAC ... -+*//***************************************************************************/ -+#ifndef __FM_MAC_EXT_H -+#define __FM_MAC_EXT_H -+ -+#include "std_ext.h" -+#include "enet_ext.h" -+ -+ -+/**************************************************************************//** -+ -+ @Group FM_grp Frame Manager API -+ -+ @Description FM API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group FM_mac_grp FM MAC -+ -+ @Description FM MAC API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+#define FM_MAC_NO_PFC 0xff -+ -+ -+/**************************************************************************//** -+ @Description FM MAC Exceptions -+*//***************************************************************************/ -+typedef enum e_FmMacExceptions { -+ e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO = 0 /**< 10GEC MDIO scan event interrupt */ -+ ,e_FM_MAC_EX_10G_MDIO_CMD_CMPL /**< 10GEC MDIO command completion interrupt */ -+ ,e_FM_MAC_EX_10G_REM_FAULT /**< 10GEC, mEMAC Remote fault interrupt */ -+ ,e_FM_MAC_EX_10G_LOC_FAULT /**< 10GEC, mEMAC Local fault interrupt */ -+ ,e_FM_MAC_EX_10G_1TX_ECC_ER /**< 10GEC, mEMAC Transmit frame ECC error interrupt */ -+ ,e_FM_MAC_EX_10G_TX_FIFO_UNFL /**< 10GEC, mEMAC Transmit FIFO underflow interrupt */ -+ ,e_FM_MAC_EX_10G_TX_FIFO_OVFL /**< 10GEC, mEMAC Transmit FIFO overflow interrupt */ -+ ,e_FM_MAC_EX_10G_TX_ER /**< 10GEC Transmit frame error interrupt */ -+ ,e_FM_MAC_EX_10G_RX_FIFO_OVFL /**< 10GEC, mEMAC Receive FIFO overflow interrupt */ -+ ,e_FM_MAC_EX_10G_RX_ECC_ER /**< 10GEC, mEMAC Receive frame ECC error interrupt */ -+ ,e_FM_MAC_EX_10G_RX_JAB_FRM /**< 10GEC Receive jabber frame interrupt */ -+ ,e_FM_MAC_EX_10G_RX_OVRSZ_FRM /**< 10GEC Receive oversized frame interrupt */ -+ ,e_FM_MAC_EX_10G_RX_RUNT_FRM /**< 10GEC Receive runt frame interrupt */ -+ ,e_FM_MAC_EX_10G_RX_FRAG_FRM /**< 10GEC Receive fragment frame interrupt */ -+ ,e_FM_MAC_EX_10G_RX_LEN_ER /**< 10GEC Receive payload length error interrupt */ -+ ,e_FM_MAC_EX_10G_RX_CRC_ER /**< 10GEC Receive CRC error interrupt */ -+ ,e_FM_MAC_EX_10G_RX_ALIGN_ER /**< 10GEC Receive alignment error interrupt */ -+ ,e_FM_MAC_EX_1G_BAB_RX /**< dTSEC Babbling receive error */ -+ ,e_FM_MAC_EX_1G_RX_CTL /**< dTSEC Receive control (pause frame) interrupt */ -+ ,e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET /**< dTSEC Graceful transmit stop complete */ -+ ,e_FM_MAC_EX_1G_BAB_TX /**< dTSEC Babbling transmit error */ -+ ,e_FM_MAC_EX_1G_TX_CTL /**< dTSEC Transmit control (pause frame) interrupt */ -+ ,e_FM_MAC_EX_1G_TX_ERR /**< dTSEC Transmit error */ -+ ,e_FM_MAC_EX_1G_LATE_COL /**< dTSEC Late collision */ -+ ,e_FM_MAC_EX_1G_COL_RET_LMT /**< dTSEC Collision retry limit */ -+ ,e_FM_MAC_EX_1G_TX_FIFO_UNDRN /**< dTSEC Transmit FIFO underrun */ -+ ,e_FM_MAC_EX_1G_MAG_PCKT /**< dTSEC Magic Packet detection */ -+ ,e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET /**< dTSEC MII management read completion */ -+ ,e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET /**< dTSEC MII management write completion */ -+ ,e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET /**< dTSEC Graceful receive stop complete */ -+ ,e_FM_MAC_EX_1G_TX_DATA_ERR /**< dTSEC Internal data error on transmit */ -+ ,e_FM_MAC_EX_1G_RX_DATA_ERR /**< dTSEC Internal data error on receive */ -+ ,e_FM_MAC_EX_1G_1588_TS_RX_ERR /**< dTSEC Time-Stamp Receive Error */ -+ ,e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL /**< dTSEC MIB counter overflow */ -+ ,e_FM_MAC_EX_TS_FIFO_ECC_ERR /**< mEMAC Time-stamp FIFO ECC error interrupt; -+ not supported on T4240/B4860 rev1 chips */ -+ ,e_FM_MAC_EX_MAGIC_PACKET_INDICATION = e_FM_MAC_EX_1G_MAG_PCKT -+ /**< mEMAC Magic Packet Indication Interrupt */ -+} e_FmMacExceptions; -+ -+/**************************************************************************//** -+ @Description TM MAC statistics level -+*//***************************************************************************/ -+typedef enum e_FmMacStatisticsLevel { -+ e_FM_MAC_NONE_STATISTICS = 0, /**< No statistics */ -+ e_FM_MAC_PARTIAL_STATISTICS, /**< Only error counters are available; Optimized for performance */ -+ e_FM_MAC_FULL_STATISTICS /**< All counters available; Not optimized for performance */ -+} e_FmMacStatisticsLevel; -+ -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description Priority Flow Control Parameters -+*//***************************************************************************/ -+typedef struct t_FmMacPfcParams { -+ bool pfcEnable; /**< Enable/Disable PFC */ -+ -+ uint16_t pauseQuanta[FM_MAX_NUM_OF_PFC_PRIORITIES]; /**< Pause Quanta per priority to be sent in a pause frame. Each quanta represents a 512 bit-times*/ -+ -+ uint16_t pauseThresholdQuanta[FM_MAX_NUM_OF_PFC_PRIORITIES];/**< Pause threshold per priority, when timer passes this threshold time a PFC frames is sent again if the port is still congested or BM pool in depletion*/ -+ -+ -+} t_FmMacPfcParams; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Function t_FmMacExceptionCallback -+ -+ @Description Fm Mac Exception Callback from FM MAC to the user -+ -+ @Param[in] h_App - Handle to the upper layer handler -+ -+ @Param[in] exceptions - The exception that occurred -+ -+ @Return void. -+*//***************************************************************************/ -+typedef void (t_FmMacExceptionCallback)(t_Handle h_App, e_FmMacExceptions exceptions); -+ -+ -+/**************************************************************************//** -+ @Description TM MAC statistics rfc3635 -+*//***************************************************************************/ -+typedef struct t_FmMacStatistics { -+/* RMON */ -+ uint64_t eStatPkts64; /**< r-10G tr-DT 64 byte frame counter */ -+ uint64_t eStatPkts65to127; /**< r-10G 65 to 127 byte frame counter */ -+ uint64_t eStatPkts128to255; /**< r-10G 128 to 255 byte frame counter */ -+ uint64_t eStatPkts256to511; /**< r-10G 256 to 511 byte frame counter */ -+ uint64_t eStatPkts512to1023; /**< r-10G 512 to 1023 byte frame counter */ -+ uint64_t eStatPkts1024to1518; /**< r-10G 1024 to 1518 byte frame counter */ -+ uint64_t eStatPkts1519to1522; /**< r-10G 1519 to 1522 byte good frame count */ -+/* */ -+ uint64_t eStatFragments; /**< Total number of packets that were less than 64 octets long with a wrong CRC.*/ -+ uint64_t eStatJabbers; /**< Total number of packets longer than valid maximum length octets */ -+ uint64_t eStatsDropEvents; /**< number of dropped packets due to internal errors of the MAC Client (during receive). */ -+ uint64_t eStatCRCAlignErrors; /**< Incremented when frames of correct length but with CRC error are received.*/ -+ uint64_t eStatUndersizePkts; /**< Incremented for frames under 64 bytes with a valid FCS and otherwise well formed; -+ This count does not include range length errors */ -+ uint64_t eStatOversizePkts; /**< Incremented for frames which exceed 1518 (non VLAN) or 1522 (VLAN) and contains -+ a valid FCS and otherwise well formed */ -+/* Pause */ -+ uint64_t teStatPause; /**< Pause MAC Control received */ -+ uint64_t reStatPause; /**< Pause MAC Control sent */ -+/* MIB II */ -+ uint64_t ifInOctets; /**< Total number of byte received. */ -+ uint64_t ifInPkts; /**< Total number of packets received.*/ -+ uint64_t ifInUcastPkts; /**< Total number of unicast frame received; -+ NOTE: this counter is not supported on dTSEC MAC */ -+ uint64_t ifInMcastPkts; /**< Total number of multicast frame received*/ -+ uint64_t ifInBcastPkts; /**< Total number of broadcast frame received */ -+ uint64_t ifInDiscards; /**< Frames received, but discarded due to problems within the MAC RX. */ -+ uint64_t ifInErrors; /**< Number of frames received with error: -+ - FIFO Overflow Error -+ - CRC Error -+ - Frame Too Long Error -+ - Alignment Error -+ - The dedicated Error Code (0xfe, not a code error) was received */ -+ uint64_t ifOutOctets; /**< Total number of byte sent. */ -+ uint64_t ifOutPkts; /**< Total number of packets sent .*/ -+ uint64_t ifOutUcastPkts; /**< Total number of unicast frame sent; -+ NOTE: this counter is not supported on dTSEC MAC */ -+ uint64_t ifOutMcastPkts; /**< Total number of multicast frame sent */ -+ uint64_t ifOutBcastPkts; /**< Total number of multicast frame sent */ -+ uint64_t ifOutDiscards; /**< Frames received, but discarded due to problems within the MAC TX N/A!.*/ -+ uint64_t ifOutErrors; /**< Number of frames transmitted with error: -+ - FIFO Overflow Error -+ - FIFO Underflow Error -+ - Other */ -+} t_FmMacStatistics; -+ -+ -+/**************************************************************************//** -+ @Group FM_mac_init_grp FM MAC Initialization Unit -+ -+ @Description FM MAC Initialization Unit -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description FM MAC config input -+*//***************************************************************************/ -+typedef struct t_FmMacParams { -+ uintptr_t baseAddr; /**< Base of memory mapped FM MAC registers */ -+ t_EnetAddr addr; /**< MAC address of device; First octet is sent first */ -+ uint8_t macId; /**< MAC ID; -+ numbering of dTSEC and 1G-mEMAC: -+ 0 - FM_MAX_NUM_OF_1G_MACS; -+ numbering of 10G-MAC (TGEC) and 10G-mEMAC: -+ 0 - FM_MAX_NUM_OF_10G_MACS */ -+ e_EnetMode enetMode; /**< Ethernet operation mode (MAC-PHY interface and speed); -+ Note that the speed should indicate the maximum rate that -+ this MAC should support rather than the actual speed; -+ i.e. user should use the FM_MAC_AdjustLink() routine to -+ provide accurate speed; -+ In case of mEMAC RGMII mode, the MAC is configured to RGMII -+ automatic mode, where actual speed/duplex mode information -+ is provided by PHY automatically in-band; FM_MAC_AdjustLink() -+ function should be used to switch to manual RGMII speed/duplex mode -+ configuration if RGMII PHY doesn't support in-band status signaling; -+ In addition, in mEMAC, in case where user is using the higher MACs -+ (i.e. the MACs that should support 10G), user should pass here -+ speed=10000 even if the interface is not allowing that (e.g. SGMII). */ -+ t_Handle h_Fm; /**< A handle to the FM object this port related to */ -+ int mdioIrq; /**< MDIO exceptions interrupt source - not valid for all -+ MACs; MUST be set to 'NO_IRQ' for MACs that don't have -+ mdio-irq, or for polling */ -+ t_FmMacExceptionCallback *f_Event; /**< MDIO Events Callback Routine */ -+ t_FmMacExceptionCallback *f_Exception; /**< Exception Callback Routine */ -+ t_Handle h_App; /**< A handle to an application layer object; This handle will -+ be passed by the driver upon calling the above callbacks */ -+} t_FmMacParams; -+ -+ -+/**************************************************************************//** -+ @Function FM_MAC_Config -+ -+ @Description Creates descriptor for the FM MAC module. -+ -+ The routine returns a handle (descriptor) to the FM MAC object. -+ This descriptor must be passed as first parameter to all other -+ FM MAC function calls. -+ -+ No actual initialization or configuration of FM MAC hardware is -+ done by this routine. -+ -+ @Param[in] p_FmMacParam - Pointer to data structure of parameters -+ -+ @Retval Handle to FM MAC object, or NULL for Failure. -+*//***************************************************************************/ -+t_Handle FM_MAC_Config(t_FmMacParams *p_FmMacParam); -+ -+/**************************************************************************//** -+ @Function FM_MAC_Init -+ -+ @Description Initializes the FM MAC module -+ -+ @Param[in] h_FmMac - FM module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_MAC_Init(t_Handle h_FmMac); -+ -+/**************************************************************************//** -+ @Function FM_Free -+ -+ @Description Frees all resources that were assigned to FM MAC module. -+ -+ Calling this routine invalidates the descriptor. -+ -+ @Param[in] h_FmMac - FM module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_MAC_Free(t_Handle h_FmMac); -+ -+ -+/**************************************************************************//** -+ @Group FM_mac_advanced_init_grp FM MAC Advanced Configuration Unit -+ -+ @Description Configuration functions used to change default values. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_MAC_ConfigResetOnInit -+ -+ @Description Tell the driver whether to reset the FM MAC before initialization or -+ not. It changes the default configuration [DEFAULT_resetOnInit]. -+ -+ @Param[in] h_FmMac A handle to a FM MAC Module. -+ @Param[in] enable When TRUE, FM will be reset before any initialization. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_ConfigResetOnInit(t_Handle h_FmMac, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_MAC_ConfigLoopback -+ -+ @Description Enable/Disable internal loopback mode -+ -+ @Param[in] h_FmMac A handle to a FM MAC Module. -+ @Param[in] enable TRUE to enable or FALSE to disable. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_ConfigLoopback(t_Handle h_FmMac, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_MAC_ConfigMaxFrameLength -+ -+ @Description Setup maximum Rx Frame Length (in 1G MAC, effects also Tx) -+ -+ @Param[in] h_FmMac A handle to a FM MAC Module. -+ @Param[in] newVal MAX Frame length -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_ConfigMaxFrameLength(t_Handle h_FmMac, uint16_t newVal); -+ -+/**************************************************************************//** -+ @Function FM_MAC_ConfigWan -+ -+ @Description ENABLE WAN mode in 10G-MAC -+ -+ @Param[in] h_FmMac A handle to a FM MAC Module. -+ @Param[in] enable TRUE to enable or FALSE to disable. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_ConfigWan(t_Handle h_FmMac, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_MAC_ConfigPadAndCrc -+ -+ @Description Config PAD and CRC mode -+ -+ @Param[in] h_FmMac A handle to a FM MAC Module. -+ @Param[in] enable TRUE to enable or FALSE to disable. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init(). -+ Not supported on 10G-MAC (i.e. CRC & PAD are added automatically -+ by HW); on mEMAC, this routine supports only PAD (i.e. CRC is -+ added automatically by HW). -+*//***************************************************************************/ -+t_Error FM_MAC_ConfigPadAndCrc(t_Handle h_FmMac, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_MAC_ConfigHalfDuplex -+ -+ @Description Config Half Duplex Mode -+ -+ @Param[in] h_FmMac A handle to a FM MAC Module. -+ @Param[in] enable TRUE to enable or FALSE to disable. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_ConfigHalfDuplex(t_Handle h_FmMac, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_MAC_ConfigTbiPhyAddr -+ -+ @Description Configures the address of internal TBI PHY. -+ -+ @Param[in] h_FmMac A handle to a FM MAC Module. -+ @Param[in] newVal TBI PHY address (1-31). -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_ConfigTbiPhyAddr(t_Handle h_FmMac, uint8_t newVal); -+ -+/**************************************************************************//** -+ @Function FM_MAC_ConfigLengthCheck -+ -+ @Description Configure the frame length checking. -+ -+ @Param[in] h_FmMac A handle to a FM MAC Module. -+ @Param[in] enable TRUE to enable or FALSE to disable. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_ConfigLengthCheck(t_Handle h_FmMac, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_MAC_ConfigException -+ -+ @Description Change Exception selection from default -+ -+ @Param[in] h_FmMac A handle to a FM MAC Module. -+ @Param[in] ex Type of the desired exceptions -+ @Param[in] enable TRUE to enable the specified exception, FALSE to disable it. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_ConfigException(t_Handle h_FmMac, e_FmMacExceptions ex, bool enable); -+ -+#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -+t_Error FM_MAC_ConfigSkipFman11Workaround (t_Handle h_FmMac); -+#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ -+/** @} */ /* end of FM_mac_advanced_init_grp group */ -+/** @} */ /* end of FM_mac_init_grp group */ -+ -+ -+/**************************************************************************//** -+ @Group FM_mac_runtime_control_grp FM MAC Runtime Control Unit -+ -+ @Description FM MAC Runtime control unit API functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_MAC_Enable -+ -+ @Description Enable the MAC -+ -+ @Param[in] h_FmMac A handle to a FM MAC Module. -+ @Param[in] mode Mode of operation (RX, TX, Both) -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_Enable(t_Handle h_FmMac, e_CommMode mode); -+ -+/**************************************************************************//** -+ @Function FM_MAC_Disable -+ -+ @Description DISABLE the MAC -+ -+ @Param[in] h_FmMac A handle to a FM MAC Module. -+ @Param[in] mode Define what part to Disable (RX, TX or BOTH) -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_Disable(t_Handle h_FmMac, e_CommMode mode); -+ -+/**************************************************************************//** -+ @Function FM_MAC_Enable1588TimeStamp -+ -+ @Description Enables the TSU operation. -+ -+ @Param[in] h_Fm - Handle to the PTP as returned from the FM_MAC_PtpConfig. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_Enable1588TimeStamp(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FM_MAC_Disable1588TimeStamp -+ -+ @Description Disables the TSU operation. -+ -+ @Param[in] h_Fm - Handle to the PTP as returned from the FM_MAC_PtpConfig. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_Disable1588TimeStamp(t_Handle h_Fm); -+ -+/**************************************************************************//** -+ @Function FM_MAC_SetTxAutoPauseFrames -+ -+ @Description Enable/Disable transmission of Pause-Frames. -+ The routine changes the default configuration [DEFAULT_TX_PAUSE_TIME]. -+ -+ @Param[in] h_FmMac - A handle to a FM MAC Module. -+ @Param[in] pauseTime - Pause quanta value used with transmitted pause frames. -+ Each quanta represents a 512 bit-times; Note that '0' -+ as an input here will be used as disabling the -+ transmission of the pause-frames. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_SetTxAutoPauseFrames(t_Handle h_FmMac, -+ uint16_t pauseTime); -+ -+ /**************************************************************************//** -+ @Function FM_MAC_SetTxPauseFrames -+ -+ @Description Enable/Disable transmission of Pause-Frames. -+ The routine changes the default configuration: -+ pause-time - [DEFAULT_TX_PAUSE_TIME] -+ threshold-time - [0] -+ -+ @Param[in] h_FmMac - A handle to a FM MAC Module. -+ @Param[in] priority - the PFC class of service; use 'FM_MAC_NO_PFC' -+ to indicate legacy pause support (i.e. no PFC). -+ @Param[in] pauseTime - Pause quanta value used with transmitted pause frames. -+ Each quanta represents a 512 bit-times; -+ Note that '0' as an input here will be used as disabling the -+ transmission of the pause-frames. -+ @Param[in] threshTime - Pause Threshold equanta value used by the MAC to retransmit pause frame. -+ if the situation causing a pause frame to be sent didn't finish when the timer -+ reached the threshold quanta, the MAC will retransmit the pause frame. -+ Each quanta represents a 512 bit-times. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+ In order for PFC to work properly the user must configure -+ TNUM-aging in the tx-port it is recommended that pre-fetch and -+ rate limit in the tx port should be disabled; -+ PFC is supported only on new mEMAC; i.e. in MACs that don't have -+ PFC support (10G-MAC and dTSEC), user should use 'FM_MAC_NO_PFC' -+ in the 'priority' field. -+*//***************************************************************************/ -+t_Error FM_MAC_SetTxPauseFrames(t_Handle h_FmMac, -+ uint8_t priority, -+ uint16_t pauseTime, -+ uint16_t threshTime); -+ -+/**************************************************************************//** -+ @Function FM_MAC_SetRxIgnorePauseFrames -+ -+ @Description Enable/Disable ignoring of Pause-Frames. -+ -+ @Param[in] h_FmMac - A handle to a FM MAC Module. -+ @Param[in] en - boolean indicates whether to ignore the incoming pause -+ frames or not. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_SetRxIgnorePauseFrames(t_Handle h_FmMac, bool en); -+ -+/**************************************************************************//** -+ @Function FM_MAC_SetWakeOnLan -+ -+ @Description Enable/Disable Wake On Lan support -+ -+ @Param[in] h_FmMac - A handle to a FM MAC Module. -+ @Param[in] en - boolean indicates whether to enable Wake On Lan -+ support or not. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_SetWakeOnLan(t_Handle h_FmMac, bool en); -+ -+/**************************************************************************//** -+ @Function FM_MAC_ResetCounters -+ -+ @Description reset all statistics counters -+ -+ @Param[in] h_FmMac - A handle to a FM MAC Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_ResetCounters(t_Handle h_FmMac); -+ -+/**************************************************************************//** -+ @Function FM_MAC_SetException -+ -+ @Description Enable/Disable a specific Exception -+ -+ @Param[in] h_FmMac - A handle to a FM MAC Module. -+ @Param[in] ex - Type of the desired exceptions -+ @Param[in] enable - TRUE to enable the specified exception, FALSE to disable it. -+ -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_SetException(t_Handle h_FmMac, e_FmMacExceptions ex, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_MAC_SetStatistics -+ -+ @Description Define Statistics level. -+ Where applicable, the routine also enables the MIB counters -+ overflow interrupt in order to keep counters accurate -+ and account for overflows. -+ This routine is relevant only for dTSEC. -+ -+ @Param[in] h_FmMac - A handle to a FM MAC Module. -+ @Param[in] statisticsLevel - Full statistics level provides all standard counters but may -+ reduce performance. Partial statistics provides only special -+ event counters (errors etc.). If selected, regular counters (such as -+ byte/packet) will be invalid and will return -1. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_SetStatistics(t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel); -+ -+/**************************************************************************//** -+ @Function FM_MAC_GetStatistics -+ -+ @Description get all statistics counters -+ -+ @Param[in] h_FmMac - A handle to a FM MAC Module. -+ @Param[in] p_Statistics - Structure with statistics -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_GetStatistics(t_Handle h_FmMac, t_FmMacStatistics *p_Statistics); -+ -+/**************************************************************************//** -+ @Function FM_MAC_ModifyMacAddr -+ -+ @Description Replace the main MAC Address -+ -+ @Param[in] h_FmMac - A handle to a FM Module. -+ @Param[in] p_EnetAddr - Ethernet Mac address -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only after FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_ModifyMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr); -+ -+/**************************************************************************//** -+ @Function FM_MAC_AddHashMacAddr -+ -+ @Description Add an Address to the hash table. This is for filter purpose only. -+ -+ @Param[in] h_FmMac - A handle to a FM Module. -+ @Param[in] p_EnetAddr - Ethernet Mac address -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). It is a filter only address. -+ @Cautions Some address need to be filterd out in upper FM blocks. -+*//***************************************************************************/ -+t_Error FM_MAC_AddHashMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr); -+ -+/**************************************************************************//** -+ @Function FM_MAC_RemoveHashMacAddr -+ -+ @Description Delete an Address to the hash table. This is for filter purpose only. -+ -+ @Param[in] h_FmMac - A handle to a FM Module. -+ @Param[in] p_EnetAddr - Ethernet Mac address -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_RemoveHashMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr); -+ -+/**************************************************************************//** -+ @Function FM_MAC_AddExactMatchMacAddr -+ -+ @Description Add a unicast or multicast mac address for exact-match filtering -+ (8 on dTSEC, 2 for 10G-MAC) -+ -+ @Param[in] h_FmMac - A handle to a FM Module. -+ @Param[in] p_EnetAddr - MAC Address to ADD -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only after FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_AddExactMatchMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr); -+ -+/**************************************************************************//** -+ @Function FM_MAC_RemovelExactMatchMacAddr -+ -+ @Description Remove a uni cast or multi cast mac address. -+ -+ @Param[in] h_FmMac - A handle to a FM Module. -+ @Param[in] p_EnetAddr - MAC Address to remove -+ -+ @Return E_OK on success; Error code otherwise.. -+ -+ @Cautions Allowed only after FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_RemovelExactMatchMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr); -+ -+/**************************************************************************//** -+ @Function FM_MAC_SetPromiscuous -+ -+ @Description Enable/Disable MAC Promiscuous mode for ALL mac addresses. -+ -+ @Param[in] h_FmMac - A handle to a FM MAC Module. -+ @Param[in] enable - TRUE to enable or FALSE to disable. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only after FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_SetPromiscuous(t_Handle h_FmMac, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_MAC_AdjustLink -+ -+ @Description Adjusts the Ethernet link with new speed/duplex setup. -+ This routine is relevant for dTSEC and mEMAC. -+ In case of mEMAC, this routine is also used for manual -+ re-configuration of RGMII speed and duplex mode for -+ RGMII PHYs not supporting in-band status information -+ to MAC. -+ -+ @Param[in] h_FmMac - A handle to a FM Module. -+ @Param[in] speed - Ethernet speed. -+ @Param[in] fullDuplex - TRUE for full-duplex mode; -+ FALSE for half-duplex mode. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_MAC_AdjustLink(t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex); -+ -+/**************************************************************************//** -+ @Function FM_MAC_RestartAutoneg -+ -+ @Description Restarts the auto-negotiation process. -+ When auto-negotiation process is invoked under traffic the -+ auto-negotiation process between the internal SGMII PHY and the -+ external PHY does not always complete successfully. Calling this -+ function will restart the auto-negotiation process that will end -+ successfully. It is recommended to call this function after issuing -+ auto-negotiation restart command to the Eth Phy. -+ This routine is relevant only for dTSEC. -+ -+ @Param[in] h_FmMac - A handle to a FM Module. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_MAC_RestartAutoneg(t_Handle h_FmMac); -+ -+/**************************************************************************//** -+ @Function FM_MAC_GetId -+ -+ @Description Return the MAC ID -+ -+ @Param[in] h_FmMac - A handle to a FM Module. -+ @Param[out] p_MacId - MAC ID of device -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only after FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_GetId(t_Handle h_FmMac, uint32_t *p_MacId); -+ -+/**************************************************************************//** -+ @Function FM_MAC_GetVesrion -+ -+ @Description Return Mac HW chip version -+ -+ @Param[in] h_FmMac - A handle to a FM Module. -+ @Param[out] p_MacVresion - Mac version as defined by the chip -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only after FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_GetVesrion(t_Handle h_FmMac, uint32_t *p_MacVresion); -+ -+/**************************************************************************//** -+ @Function FM_MAC_MII_WritePhyReg -+ -+ @Description Write data into Phy Register -+ -+ @Param[in] h_FmMac - A handle to a FM Module. -+ @Param[in] phyAddr - Phy Address on the MII bus -+ @Param[in] reg - Register Number. -+ @Param[in] data - Data to write. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only after FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_MII_WritePhyReg(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data); -+ -+/**************************************************************************//** -+ @Function FM_MAC_MII_ReadPhyReg -+ -+ @Description Read data from Phy Register -+ -+ @Param[in] h_FmMac - A handle to a FM Module. -+ @Param[in] phyAddr - Phy Address on the MII bus -+ @Param[in] reg - Register Number. -+ @Param[out] p_Data - Data from PHY. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only after FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_MII_ReadPhyReg(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data); -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+/**************************************************************************//** -+ @Function FM_MAC_DumpRegs -+ -+ @Description Dump internal registers -+ -+ @Param[in] h_FmMac - A handle to a FM Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only after FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_DumpRegs(t_Handle h_FmMac); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+/** @} */ /* end of FM_mac_runtime_control_grp group */ -+/** @} */ /* end of FM_mac_grp group */ -+/** @} */ /* end of FM_grp group */ -+ -+ -+#endif /* __FM_MAC_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_macsec_ext.h -@@ -0,0 +1,1271 @@ -+/* -+ * Copyright 2008-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ @File fm_macsec_ext.h -+ -+ @Description FM MACSEC ... -+*//***************************************************************************/ -+#ifndef __FM_MACSEC_EXT_H -+#define __FM_MACSEC_EXT_H -+ -+#include "std_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group FM_grp Frame Manager API -+ -+ @Description FM API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group FM_MACSEC_grp FM MACSEC -+ -+ @Description FM MACSEC API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description MACSEC Exceptions -+*//***************************************************************************/ -+typedef enum e_FmMacsecExceptions { -+ e_FM_MACSEC_EX_SINGLE_BIT_ECC, /**< Single bit ECC error */ -+ e_FM_MACSEC_EX_MULTI_BIT_ECC /**< Multi bit ECC error */ -+} e_FmMacsecExceptions; -+ -+ -+/**************************************************************************//** -+ @Group FM_MACSEC_init_grp FM-MACSEC Initialization Unit -+ -+ @Description FM MACSEC Initialization Unit -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function t_FmMacsecExceptionsCallback -+ -+ @Description Exceptions user callback routine, will be called upon an -+ exception passing the exception identification. -+ -+ @Param[in] h_App A handle to an application layer object; This handle -+ will be passed by the driver upon calling this callback. -+ @Param[in] exception The exception. -+*//***************************************************************************/ -+typedef void (t_FmMacsecExceptionsCallback) ( t_Handle h_App, -+ e_FmMacsecExceptions exception); -+ -+ -+/**************************************************************************//** -+ @Description FM MACSEC config input -+*//***************************************************************************/ -+typedef struct t_FmMacsecParams { -+ t_Handle h_Fm; /**< A handle to the FM object related to */ -+ bool guestMode; /**< Partition-id */ -+ union { -+ struct { -+ uint8_t fmMacId; /**< FM MAC id */ -+ } guestParams; -+ -+ struct { -+ uintptr_t baseAddr; /**< Base of memory mapped FM MACSEC registers */ -+ t_Handle h_FmMac; /**< A handle to the FM MAC object related to */ -+ t_FmMacsecExceptionsCallback *f_Exception; /**< Exception Callback Routine */ -+ t_Handle h_App; /**< A handle to an application layer object; This handle will -+ be passed by the driver upon calling the above callbacks */ -+ } nonGuestParams; -+ }; -+} t_FmMacsecParams; -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_Config -+ -+ @Description Creates descriptor for the FM MACSEC module; -+ -+ The routine returns a handle (descriptor) to the FM MACSEC object; -+ This descriptor must be passed as first parameter to all other -+ FM MACSEC function calls; -+ -+ No actual initialization or configuration of FM MACSEC hardware is -+ done by this routine. -+ -+ @Param[in] p_FmMacsecParam Pointer to data structure of parameters. -+ -+ @Retval Handle to FM MACSEC object, or NULL for Failure. -+*//***************************************************************************/ -+t_Handle FM_MACSEC_Config(t_FmMacsecParams *p_FmMacsecParam); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_Init -+ -+ @Description Initializes the FM MACSEC module. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_MACSEC_Init(t_Handle h_FmMacsec); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_Free -+ -+ @Description Frees all resources that were assigned to FM MACSEC module; -+ -+ Calling this routine invalidates the descriptor. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_MACSEC_Free(t_Handle h_FmMacsec); -+ -+ -+/**************************************************************************//** -+ @Group FM_MACSEC_advanced_init_grp FM-MACSEC Advanced Configuration Unit -+ -+ @Description Configuration functions used to change default values. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description enum for unknown sci frame treatment -+*//***************************************************************************/ -+typedef enum e_FmMacsecUnknownSciFrameTreatment { -+ e_FM_MACSEC_UNKNOWN_SCI_FRAME_TREATMENT_DISCARD_BOTH = 0, /**< Controlled port - Strict mode */ -+ e_FM_MACSEC_UNKNOWN_SCI_FRAME_TREATMENT_DISCARD_UNCONTROLLED_DELIVER_OR_DISCARD_CONTROLLED, /**< If C bit clear deliver on controlled port, else discard -+ Controlled port - Check or Disable mode */ -+ e_FM_MACSEC_UNKNOWN_SCI_FRAME_TREATMENT_DELIVER_UNCONTROLLED_DISCARD_CONTROLLED, /**< Controlled port - Strict mode */ -+ e_FM_MACSEC_UNKNOWN_SCI_FRAME_TREATMENT_DELIVER_OR_DISCARD_UNCONTROLLED_DELIVER_OR_DISCARD_CONTROLLED /**< If C bit set deliver on uncontrolled port and discard on controlled port, -+ else discard on uncontrolled port and deliver on controlled port -+ Controlled port - Check or Disable mode */ -+} e_FmMacsecUnknownSciFrameTreatment; -+ -+/**************************************************************************//** -+ @Description enum for untag frame treatment -+*//***************************************************************************/ -+typedef enum e_FmMacsecUntagFrameTreatment { -+ e_FM_MACSEC_UNTAG_FRAME_TREATMENT_DELIVER_UNCONTROLLED_DISCARD_CONTROLLED = 0, /**< Controlled port - Strict mode */ -+ e_FM_MACSEC_UNTAG_FRAME_TREATMENT_DISCARD_BOTH, /**< Controlled port - Strict mode */ -+ e_FM_MACSEC_UNTAG_FRAME_TREATMENT_DISCARD_UNCONTROLLED_DELIVER_CONTROLLED_UNMODIFIED /**< Controlled port - Strict mode */ -+} e_FmMacsecUntagFrameTreatment; -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_ConfigUnknownSciFrameTreatment -+ -+ @Description Change the treatment for received frames with unknown sci from its default -+ configuration [DEFAULT_unknownSciFrameTreatment]. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ @Param[in] treatMode The selected mode. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_Config() and before FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_ConfigUnknownSciFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUnknownSciFrameTreatment treatMode); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_ConfigInvalidTagsFrameTreatment -+ -+ @Description Change the treatment for received frames with invalid tags or -+ a zero value PN or an invalid ICV from its default configuration -+ [DEFAULT_invalidTagsFrameTreatment]. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ @Param[in] deliverUncontrolled If True deliver on the uncontrolled port, else discard; -+ In both cases discard on the controlled port; -+ this provide Strict, Check or Disable mode. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_Config() and before FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_ConfigInvalidTagsFrameTreatment(t_Handle h_FmMacsec, bool deliverUncontrolled); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment -+ -+ @Description Change the treatment for received frames with the Encryption bit -+ set and the Changed Text bit clear from its default configuration -+ [DEFAULT_encryptWithNoChangedTextFrameTreatment]. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ @Param[in] discardUncontrolled If True discard on the uncontrolled port, else deliver; -+ In both cases discard on the controlled port; -+ this provide Strict, Check or Disable mode. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_Config() and before FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment(t_Handle h_FmMacsec, bool discardUncontrolled); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_ConfigChangedTextWithNoEncryptFrameTreatment -+ -+ @Description Change the treatment for received frames with the Encryption bit -+ clear and the Changed Text bit set from its default configuration -+ [DEFAULT_changedTextWithNoEncryptFrameTreatment]. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ @Param[in] deliverUncontrolled If True deliver on the uncontrolled port, else discard; -+ In both cases discard on the controlled port; -+ this provide Strict, Check or Disable mode. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_Config() and before FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_ConfigChangedTextWithNoEncryptFrameTreatment(t_Handle h_FmMacsec, bool deliverUncontrolled); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_ConfigUntagFrameTreatment -+ -+ @Description Change the treatment for received frames without the MAC security tag (SecTAG) -+ from its default configuration [DEFAULT_untagFrameTreatment]. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ @Param[in] treatMode The selected mode. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_Config() and before FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_ConfigUntagFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUntagFrameTreatment treatMode); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_ConfigOnlyScbIsSetFrameTreatment -+ -+ @Description Change the treatment for received frames with only SCB bit set -+ from its default configuration [DEFAULT_onlyScbIsSetFrameTreatment]. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ @Param[in] deliverUncontrolled If True deliver on the uncontrolled port, else discard; -+ In both cases discard on the controlled port; -+ this provide Strict, Check or Disable mode. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_Config() and before FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_ConfigOnlyScbIsSetFrameTreatment(t_Handle h_FmMacsec, bool deliverUncontrolled); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_ConfigPnExhaustionThreshold -+ -+ @Description It's provide the ability to configure a PN exhaustion threshold; -+ When the NextPn crosses this value an interrupt event -+ is asserted to warn that the active SA should re-key. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ @Param[in] pnExhThr If the threshold is reached, an interrupt event -+ is asserted to re-key. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_Config() and before FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_ConfigPnExhaustionThreshold(t_Handle h_FmMacsec, uint32_t pnExhThr); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_ConfigKeysUnreadable -+ -+ @Description Turn on privacy mode; All the keys and their hash values can't be read any more; -+ Can not be cleared unless hard reset. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_Config() and before FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_ConfigKeysUnreadable(t_Handle h_FmMacsec); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_ConfigSectagWithoutSCI -+ -+ @Description Promise that all generated Sectag will be without SCI included. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_Config() and before FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_ConfigSectagWithoutSCI(t_Handle h_FmMacsec); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_ConfigException -+ -+ @Description Calling this routine changes the internal driver data base -+ from its default selection of exceptions enablement; -+ By default all exceptions are enabled. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ @Param[in] exception The exception to be selected. -+ @Param[in] enable TRUE to enable interrupt, FALSE to mask it. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_Config() and before FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_ConfigException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable); -+ -+/** @} */ /* end of FM_MACSEC_advanced_init_grp group */ -+/** @} */ /* end of FM_MACSEC_init_grp group */ -+ -+ -+/**************************************************************************//** -+ @Group FM_MACSEC_runtime_control_grp FM-MACSEC Runtime Control Data Unit -+ -+ @Description FM MACSEC runtime control data unit API functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_GetRevision -+ -+ @Description Return MACSEC HW chip revision -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ @Param[out] p_MacsecRevision MACSEC revision as defined by the chip. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only after FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_GetRevision(t_Handle h_FmMacsec, uint32_t *p_MacsecRevision); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_Enable -+ -+ @Description This routine should be called after MACSEC is initialized for enabling all -+ MACSEC engines according to their existing configuration. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_Init() and when MACSEC is disabled. -+*//***************************************************************************/ -+t_Error FM_MACSEC_Enable(t_Handle h_FmMacsec); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_Disable -+ -+ @Description This routine may be called when MACSEC is enabled in order to -+ disable all MACSEC engines; The MACSEC is working in bypass mode. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_Init() and when MACSEC is enabled. -+*//***************************************************************************/ -+t_Error FM_MACSEC_Disable(t_Handle h_FmMacsec); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SetException -+ -+ @Description Calling this routine enables/disables the specified exception. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ @Param[in] exception The exception to be selected. -+ @Param[in] enable TRUE to enable interrupt, FALSE to mask it. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SetException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable); -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+/**************************************************************************//** -+ @Function FM_MACSEC_DumpRegs -+ -+ @Description Dump internal registers. -+ -+ @Param[in] h_FmMacsec - FM MACSEC module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only after FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_DumpRegs(t_Handle h_FmMacsec); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+#ifdef VERIFICATION_SUPPORT -+/********************* VERIFICATION ONLY ********************************/ -+/**************************************************************************//** -+ @Function FM_MACSEC_BackdoorSet -+ -+ @Description Set register of the MACSEC memory map -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ @Param[out] offset Register offset. -+ @Param[out] value Value to write. -+ -+ -+ @Return None -+ -+ @Cautions Allowed only following FM_MACSEC_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_BackdoorSet(t_Handle h_FmMacsec, uint32_t offset, uint32_t value); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_BackdoorGet -+ -+ @Description Read from register of the MACSEC memory map. -+ -+ @Param[in] h_FmMacsec FM MACSEC module descriptor. -+ @Param[out] offset Register offset. -+ -+ @Return Value read -+ -+ @Cautions Allowed only following FM_MACSEC_Init(). -+*//***************************************************************************/ -+uint32_t FM_MACSEC_BackdoorGet(t_Handle h_FmMacsec, uint32_t offset); -+#endif /* VERIFICATION_SUPPORT */ -+ -+/** @} */ /* end of FM_MACSEC_runtime_control_grp group */ -+ -+ -+/**************************************************************************//** -+ @Group FM_MACSEC_SECY_grp FM-MACSEC SecY -+ -+ @Description FM-MACSEC SecY API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+typedef uint8_t macsecSAKey_t[32]; -+typedef uint64_t macsecSCI_t; -+typedef uint8_t macsecAN_t; -+ -+/**************************************************************************//** -+@Description MACSEC SECY Cipher Suite -+*//***************************************************************************/ -+typedef enum e_FmMacsecSecYCipherSuite { -+ e_FM_MACSEC_SECY_GCM_AES_128 = 0, /**< GCM-AES-128 */ -+#if (DPAA_VERSION >= 11) -+ e_FM_MACSEC_SECY_GCM_AES_256 /**< GCM-AES-256 */ -+#endif /* (DPAA_VERSION >= 11) */ -+} e_FmMacsecSecYCipherSuite; -+ -+/**************************************************************************//** -+ @Description MACSEC SECY Exceptions -+*//***************************************************************************/ -+typedef enum e_FmMacsecSecYExceptions { -+ e_FM_MACSEC_SECY_EX_FRAME_DISCARDED /**< Frame Discarded */ -+} e_FmMacsecSecYExceptions; -+ -+/**************************************************************************//** -+ @Description MACSEC SECY Events -+*//***************************************************************************/ -+typedef enum e_FmMacsecSecYEvents { -+ e_FM_MACSEC_SECY_EV_NEXT_PN /**< Next Packet Number exhaustion threshold reached */ -+} e_FmMacsecSecYEvents; -+ -+/**************************************************************************//** -+ @Collection MACSEC SECY Frame Discarded Descriptor error -+*//***************************************************************************/ -+typedef uint8_t macsecTxScFrameDiscardedErrSelect_t; /**< typedef for defining Frame Discarded Descriptor errors */ -+ -+#define FM_MACSEC_SECY_TX_SC_FRM_DISCAR_ERR_NEXT_PN_ZERO 0x8000 /**< NextPn == 0 */ -+#define FM_MACSEC_SECY_TX_SC_FRM_DISCAR_ERR_SC_DISBALE 0x4000 /**< SC is disable */ -+/* @} */ -+ -+/**************************************************************************//** -+ @Function t_FmMacsecSecYExceptionsCallback -+ -+ @Description Exceptions user callback routine, will be called upon an -+ exception passing the exception identification. -+ -+ @Param[in] h_App A handle to an application layer object; This handle -+ will be passed by the driver upon calling this callback. -+ @Param[in] exception The exception. -+*//***************************************************************************/ -+typedef void (t_FmMacsecSecYExceptionsCallback) ( t_Handle h_App, -+ e_FmMacsecSecYExceptions exception); -+ -+/**************************************************************************//** -+ @Function t_FmMacsecSecYEventsCallback -+ -+ @Description Events user callback routine, will be called upon an -+ event passing the event identification. -+ -+ @Param[in] h_App A handle to an application layer object; This handle -+ will be passed by the driver upon calling this callback. -+ @Param[in] event The event. -+*//***************************************************************************/ -+typedef void (t_FmMacsecSecYEventsCallback) ( t_Handle h_App, -+ e_FmMacsecSecYEvents event); -+ -+/**************************************************************************//** -+ @Description RFC2863 MIB -+*//***************************************************************************/ -+typedef struct t_MIBStatistics { -+ uint64_t ifInOctets; /**< Total number of byte received */ -+ uint64_t ifInPkts; /**< Total number of packets received */ -+ uint64_t ifInMcastPkts; /**< Total number of multicast frame received */ -+ uint64_t ifInBcastPkts; /**< Total number of broadcast frame received */ -+ uint64_t ifInDiscards; /**< Frames received, but discarded due to problems within the MAC RX : -+ - InPktsNoTag, -+ - InPktsLate, -+ - InPktsOverrun */ -+ uint64_t ifInErrors; /**< Number of frames received with error: -+ - InPktsBadTag, -+ - InPktsNoSCI, -+ - InPktsNotUsingSA -+ - InPktsNotValid */ -+ uint64_t ifOutOctets; /**< Total number of byte sent */ -+ uint64_t ifOutPkts; /**< Total number of packets sent */ -+ uint64_t ifOutMcastPkts; /**< Total number of multicast frame sent */ -+ uint64_t ifOutBcastPkts; /**< Total number of multicast frame sent */ -+ uint64_t ifOutDiscards; /**< Frames received, but discarded due to problems within the MAC TX N/A! */ -+ uint64_t ifOutErrors; /**< Number of frames transmitted with error: -+ - FIFO Overflow Error -+ - FIFO Underflow Error -+ - Other */ -+} t_MIBStatistics; -+ -+/**************************************************************************//** -+ @Description MACSEC SecY Rx SA Statistics -+*//***************************************************************************/ -+typedef struct t_FmMacsecSecYRxSaStatistics { -+ uint32_t inPktsOK; /**< The number of frames with resolved SCI, have passed all -+ frame validation frame validation with the validateFrame not set to disable */ -+ uint32_t inPktsInvalid; /**< The number of frames with resolved SCI, that have failed frame -+ validation with the validateFrame set to check */ -+ uint32_t inPktsNotValid; /**< The number of frames with resolved SCI, discarded on the controlled port, -+ that have failed frame validation with the validateFrame set to strict or the c bit is set */ -+ uint32_t inPktsNotUsingSA; /**< The number of frames received with resolved SCI and discarded on disabled or -+ not provisioned SA with validateFrame in the strict mode or the C bit is set */ -+ uint32_t inPktsUnusedSA; /**< The number of frames received with resolved SCI on disabled or not provisioned SA -+ with validateFrame not in the strict mode and the C bit is cleared */ -+} t_FmMacsecSecYRxSaStatistics; -+ -+/**************************************************************************//** -+ @Description MACSEC SecY Tx SA Statistics -+*//***************************************************************************/ -+typedef struct t_FmMacsecSecYTxSaStatistics { -+ uint64_t outPktsProtected; /**< The number of frames, that the user of the controlled port requested to -+ be transmitted, which were integrity protected */ -+ uint64_t outPktsEncrypted; /**< The number of frames, that the user of the controlled port requested to -+ be transmitted, which were confidentiality protected */ -+} t_FmMacsecSecYTxSaStatistics; -+ -+/**************************************************************************//** -+ @Description MACSEC SecY Rx SC Statistics -+*//***************************************************************************/ -+typedef struct t_FmMacsecSecYRxScStatistics { -+ uint64_t inPktsUnchecked; /**< The number of frames with resolved SCI, delivered to the user of a controlled port, -+ that are not validated with the validateFrame set to disable */ -+ uint64_t inPktsDelayed; /**< The number of frames with resolved SCI, delivered to the user of a controlled port, -+ that have their PN smaller than the lowest_PN with the validateFrame set to -+ disable or replayProtect disabled */ -+ uint64_t inPktsLate; /**< The number of frames with resolved SCI, discarded on the controlled port, -+ that have their PN smaller than the lowest_PN with the validateFrame set to -+ Check or Strict and replayProtect enabled */ -+ uint64_t inPktsOK; /**< The number of frames with resolved SCI, have passed all -+ frame validation frame validation with the validateFrame not set to disable */ -+ uint64_t inPktsInvalid; /**< The number of frames with resolved SCI, that have failed frame -+ validation with the validateFrame set to check */ -+ uint64_t inPktsNotValid; /**< The number of frames with resolved SCI, discarded on the controlled port, -+ that have failed frame validation with the validateFrame set to strict or the c bit is set */ -+ uint64_t inPktsNotUsingSA; /**< The number of frames received with resolved SCI and discarded on disabled or -+ not provisioned SA with validateFrame in the strict mode or the C bit is set */ -+ uint64_t inPktsUnusedSA; /**< The number of frames received with resolved SCI on disabled or not provisioned SA -+ with validateFrame not in the strict mode and the C bit is cleared */ -+} t_FmMacsecSecYRxScStatistics; -+ -+/**************************************************************************//** -+ @Description MACSEC SecY Tx SC Statistics -+*//***************************************************************************/ -+typedef struct t_FmMacsecSecYTxScStatistics { -+ uint64_t outPktsProtected; /**< The number of frames, that the user of the controlled port requested to -+ be transmitted, which were integrity protected */ -+ uint64_t outPktsEncrypted; /**< The number of frames, that the user of the controlled port requested to -+ be transmitted, which were confidentiality protected */ -+} t_FmMacsecSecYTxScStatistics; -+ -+/**************************************************************************//** -+ @Description MACSEC SecY Statistics -+*//***************************************************************************/ -+typedef struct t_FmMacsecSecYStatistics { -+ t_MIBStatistics mibCtrlStatistics; /**< Controlled port MIB statistics */ -+ t_MIBStatistics mibNonCtrlStatistics; /**< Uncontrolled port MIB statistics */ -+/* Frame verification statistics */ -+ uint64_t inPktsUntagged; /**< The number of received packets without the MAC security tag -+ (SecTAG) with validateFrames which is not in the strict mode */ -+ uint64_t inPktsNoTag; /**< The number of received packets discarded without the -+ MAC security tag (SecTAG) with validateFrames which is in the strict mode */ -+ uint64_t inPktsBadTag; /**< The number of received packets discarded with an invalid -+ SecTAG or a zero value PN or an invalid ICV */ -+ uint64_t inPktsUnknownSCI; /**< The number of received packets with unknown SCI with the -+ condition : validateFrames is not in the strict mode and the -+ C bit in the SecTAG is not set */ -+ uint64_t inPktsNoSCI; /**< The number of received packets discarded with unknown SCI -+ information with the condition : validateFrames is in the strict mode -+ or the C bit in the SecTAG is set */ -+ uint64_t inPktsOverrun; /**< The number of packets discarded because the number of -+ received packets exceeded the cryptographic performance capabilities */ -+/* Frame validation statistics */ -+ uint64_t inOctetsValidated; /**< The number of octets of plaintext recovered from received frames with -+ resolved SCI that were integrity protected but not encrypted */ -+ uint64_t inOctetsDecrypted; /**< The number of octets of plaintext recovered from received frames with -+ resolved SCI that were integrity protected and encrypted */ -+/* Frame generation statistics */ -+ uint64_t outPktsUntagged; /**< The number of frames, that the user of the controlled port requested to -+ be transmitted, with protectFrame false */ -+ uint64_t outPktsTooLong; /**< The number of frames, that the user of the controlled port requested to -+ be transmitted, discarded due to length being larger than Maximum Frame Length (MACSEC_MFL) */ -+/* Frame protection statistics */ -+ uint64_t outOctetsProtected; /**< The number of octets of User Data in transmitted frames that were -+ integrity protected but not encrypted */ -+ uint64_t outOctetsEncrypted; /**< The number of octets of User Data in transmitted frames that were -+ both integrity protected and encrypted */ -+} t_FmMacsecSecYStatistics; -+ -+ -+/**************************************************************************//** -+ @Description MACSEC SecY SC Params -+*//***************************************************************************/ -+typedef struct t_FmMacsecSecYSCParams { -+ macsecSCI_t sci; /**< The secure channel identification of the SC */ -+ e_FmMacsecSecYCipherSuite cipherSuite; /**< Cipher suite to be used for the SC */ -+} t_FmMacsecSecYSCParams; -+ -+/**************************************************************************//** -+ @Group FM_MACSEC_SECY_init_grp FM-MACSEC SecY Initialization Unit -+ -+ @Description FM-MACSEC SecY Initialization Unit -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description enum for validate frames -+*//***************************************************************************/ -+typedef enum e_FmMacsecValidFrameBehavior { -+ e_FM_MACSEC_VALID_FRAME_BEHAVIOR_DISABLE = 0, /**< disable the validation function */ -+ e_FM_MACSEC_VALID_FRAME_BEHAVIOR_CHECK, /**< enable the validation function but only for checking -+ without filtering out invalid frames */ -+ e_FM_MACSEC_VALID_FRAME_BEHAVIOR_STRICT /**< enable the validation function and also strictly filter -+ out those invalid frames */ -+} e_FmMacsecValidFrameBehavior; -+ -+/**************************************************************************//** -+ @Description enum for sci insertion -+*//***************************************************************************/ -+typedef enum e_FmMacsecSciInsertionMode { -+ e_FM_MACSEC_SCI_INSERTION_MODE_EXPLICIT_SECTAG = 0, /**< explicit sci in the sectag */ -+ e_FM_MACSEC_SCI_INSERTION_MODE_EXPLICIT_MAC_SA, /**< mac sa is overwritten with the sci*/ -+ e_FM_MACSEC_SCI_INSERTION_MODE_IMPLICT_PTP /**< implicit point-to-point sci (pre-shared) */ -+} e_FmMacsecSciInsertionMode; -+ -+/**************************************************************************//** -+ @Description FM MACSEC SecY config input -+*//***************************************************************************/ -+typedef struct t_FmMacsecSecYParams { -+ t_Handle h_FmMacsec; /**< A handle to the FM MACSEC object */ -+ t_FmMacsecSecYSCParams txScParams; /**< Tx SC Params */ -+ uint32_t numReceiveChannels; /**< Number of receive channels dedicated to this SecY */ -+ t_FmMacsecSecYExceptionsCallback *f_Exception; /**< Callback routine to be called by the driver upon SecY exception */ -+ t_FmMacsecSecYEventsCallback *f_Event; /**< Callback routine to be called by the driver upon SecY event */ -+ t_Handle h_App; /**< A handle to an application layer object; This handle will -+ be passed by the driver upon calling the above callbacks */ -+} t_FmMacsecSecYParams; -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_Config -+ -+ @Description Creates descriptor for the FM MACSEC SECY module; -+ -+ The routine returns a handle (descriptor) to the FM MACSEC SECY object; -+ This descriptor must be passed as first parameter to all other -+ FM MACSEC SECY function calls; -+ No actual initialization or configuration of FM MACSEC SecY hardware is -+ done by this routine. -+ -+ @Param[in] p_FmMacsecSecYParam Pointer to data structure of parameters. -+ -+ @Return Handle to FM MACSEC SECY object, or NULL for Failure. -+*//***************************************************************************/ -+t_Handle FM_MACSEC_SECY_Config(t_FmMacsecSecYParams *p_FmMacsecSecYParam); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_Init -+ -+ @Description Initializes the FM MACSEC SECY module. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_Init(t_Handle h_FmMacsecSecY); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_Free -+ -+ @Description Frees all resources that were assigned to FM MACSEC SECY module. -+ -+ Calling this routine invalidates the descriptor. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_Free(t_Handle h_FmMacsecSecY); -+ -+/**************************************************************************//** -+ @Group FM_MACSEC_SECY_advanced_init_grp FM-MACSEC SecY Advanced Configuration Unit -+ -+ @Description Configuration functions used to change default values. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_ConfigSciInsertionMode -+ -+ @Description Calling this routine changes the SCI-insertion-mode in the -+ internal driver data base from its default configuration -+ [DEFAULT_sciInsertionMode] -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] sciInsertionMode Sci insertion mode -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Config() and before FM_MACSEC_SECY_Init(); -+ -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_ConfigSciInsertionMode(t_Handle h_FmMacsecSecY, e_FmMacsecSciInsertionMode sciInsertionMode); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_ConfigProtectFrames -+ -+ @Description Calling this routine changes the protect-frame mode in the -+ internal driver data base from its default configuration -+ [DEFAULT_protectFrames] -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] protectFrames If FALSE, frames are transmitted without modification -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Config() and before FM_MACSEC_SECY_Init(); -+ -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_ConfigProtectFrames(t_Handle h_FmMacsecSecY, bool protectFrames); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_ConfigReplayWindow -+ -+ @Description Calling this routine changes the replay-window settings in the -+ internal driver data base from its default configuration -+ [DEFAULT_replayEnable], [DEFAULT_replayWindow] -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] replayProtect; Replay protection function mode -+ @Param[in] replayWindow; The size of the replay window -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Config() and before FM_MACSEC_SECY_Init(); -+ -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_ConfigReplayWindow(t_Handle h_FmMacsecSecY, bool replayProtect, uint32_t replayWindow); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_ConfigValidationMode -+ -+ @Description Calling this routine changes the frame-validation-behavior mode -+ in the internal driver data base from its default configuration -+ [DEFAULT_validateFrames] -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] validateFrames Validation function mode -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Config() and before FM_MACSEC_SECY_Init(); -+ -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_ConfigValidationMode(t_Handle h_FmMacsecSecY, e_FmMacsecValidFrameBehavior validateFrames); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_ConfigConfidentiality -+ -+ @Description Calling this routine changes the confidentiality settings in the -+ internal driver data base from its default configuration -+ [DEFAULT_confidentialityEnable], [DEFAULT_confidentialityOffset] -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] confidentialityEnable TRUE - confidentiality protection and integrity protection -+ FALSE - no confidentiality protection, only integrity protection -+ @Param[in] confidentialityOffset The number of initial octets of each MSDU without confidentiality protection -+ common values are 0, 30, and 50 -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Config() and before FM_MACSEC_SECY_Init(); -+ -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_ConfigConfidentiality(t_Handle h_FmMacsecSecY, bool confidentialityEnable, uint16_t confidentialityOffset); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_ConfigPointToPoint -+ -+ @Description configure this SecY to work in point-to-point mode, means that -+ it will have only one rx sc; -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Config() and before FM_MACSEC_SECY_Init(); -+ Can be called only once in a system; only the first secY that will call this -+ routine will be able to operate in Point-To-Point mode. -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_ConfigPointToPoint(t_Handle h_FmMacsecSecY); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_ConfigException -+ -+ @Description Calling this routine changes the internal driver data base -+ from its default selection of exceptions enablement; -+ By default all exceptions are enabled. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] exception The exception to be selected. -+ @Param[in] enable TRUE to enable interrupt, FALSE to mask it. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Config() and before FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_ConfigException(t_Handle h_FmMacsecSecY, e_FmMacsecSecYExceptions exception, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_ConfigEvent -+ -+ @Description Calling this routine changes the internal driver data base -+ from its default selection of events enablement; -+ By default all events are enabled. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] event The event to be selected. -+ @Param[in] enable TRUE to enable interrupt, FALSE to mask it. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Config() and before FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_ConfigEvent(t_Handle h_FmMacsecSecY, e_FmMacsecSecYEvents event, bool enable); -+ -+/** @} */ /* end of FM_MACSEC_SECY_advanced_init_grp group */ -+/** @} */ /* end of FM_MACSEC_SECY_init_grp group */ -+ -+ -+/**************************************************************************//** -+ @Group FM_MACSEC_SECY_runtime_control_grp FM-MACSEC SecY Runtime Control Unit -+ -+ @Description FM MACSEC SECY Runtime control unit API functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_CreateRxSc -+ -+ @Description Create a receive secure channel. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] scParams secure channel params. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Handle FM_MACSEC_SECY_CreateRxSc(t_Handle h_FmMacsecSecY, t_FmMacsecSecYSCParams *p_ScParams); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_DeleteRxSc -+ -+ @Description Deleting an initialized secure channel. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] h_Sc SC handle as returned by FM_MACSEC_SECY_CreateRxSc. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_CreateRxSc(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_DeleteRxSc(t_Handle h_FmMacsecSecY, t_Handle h_Sc); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_CreateRxSa -+ -+ @Description Create a receive secure association for the secure channel; -+ the SA cannot be used to receive frames until FM_MACSEC_SECY_RxSaEnableReceive is called. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] h_Sc SC handle as returned by FM_MACSEC_SECY_CreateRxSc. -+ @Param[in] an association number represent the SA. -+ @Param[in] lowestPn the lowest acceptable PN value for a received frame. -+ @Param[in] key the desired key for this SA. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_CreateRxSc(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_CreateRxSa(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t lowestPn, macsecSAKey_t key); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_DeleteRxSa -+ -+ @Description Deleting an initialized secure association. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] h_Sc SC handle as returned by FM_MACSEC_SECY_CreateRxSc. -+ @Param[in] an association number represent the SA. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_DeleteRxSa(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_RxSaEnableReceive -+ -+ @Description Enabling the SA to receive frames. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] h_Sc SC handle as returned by FM_MACSEC_SECY_CreateRxSc. -+ @Param[in] an association number represent the SA. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_CreateRxSa(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_RxSaEnableReceive(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_RxSaDisableReceive -+ -+ @Description Disabling the SA from receive frames. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] h_Sc SC handle as returned by FM_MACSEC_SECY_CreateRxSc. -+ @Param[in] an association number represent the SA. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_CreateRxSa(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_RxSaDisableReceive(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_RxSaUpdateNextPn -+ -+ @Description Update the next packet number expected on RX; -+ The value of nextPN shall be set to the greater of its existing value and the -+ supplied of updtNextPN (802.1AE-2006 10.7.15). -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] h_Sc SC handle as returned by FM_MACSEC_SECY_CreateRxSc. -+ @Param[in] an association number represent the SA. -+ @Param[in] updtNextPN the next PN value for a received frame. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_CreateRxSa(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_RxSaUpdateNextPn(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t updtNextPN); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_RxSaUpdateLowestPn -+ -+ @Description Update the lowest packet number expected on RX; -+ The value of lowestPN shall be set to the greater of its existing value and the -+ supplied of updtLowestPN (802.1AE-2006 10.7.15). -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] h_Sc SC handle as returned by FM_MACSEC_SECY_CreateRxSc. -+ @Param[in] an association number represent the SA. -+ @Param[in] updtLowestPN the lowest PN acceptable value for a received frame. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_CreateRxSa(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_RxSaUpdateLowestPn(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t updtLowestPN); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_RxSaModifyKey -+ -+ @Description Modify the current key of the SA with a new one. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] h_Sc SC handle as returned by FM_MACSEC_SECY_CreateRxSc. -+ @Param[in] an association number represent the SA. -+ @Param[in] key new key to replace the current key. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_CreateRxSa(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_RxSaModifyKey(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, macsecSAKey_t key); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_CreateTxSa -+ -+ @Description Create a transmit secure association for the secure channel; -+ the SA cannot be used to transmit frames until FM_MACSEC_SECY_TxSaSetActivate is called; -+ Only one SA can be active at a time. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] an association number represent the SA. -+ @Param[in] key the desired key for this SA. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_CreateTxSa(t_Handle h_FmMacsecSecY, macsecAN_t an, macsecSAKey_t key); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_DeleteTxSa -+ -+ @Description Deleting an initialized secure association. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] an association number represent the SA. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_DeleteTxSa(t_Handle h_FmMacsecSecY, macsecAN_t an); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_TxSaModifyKey -+ -+ @Description Modify the key of the inactive SA with a new one. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] nextActiveAn association number represent the next SA to be activated. -+ @Param[in] key new key to replace the current key. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_TxSaModifyKey(t_Handle h_FmMacsecSecY, macsecAN_t nextActiveAn, macsecSAKey_t key); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_TxSaSetActive -+ -+ @Description Set this SA to the active SA to be used on TX for SC; -+ only one SA can be active at a time. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] an association number represent the SA. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_TxSaSetActive(t_Handle h_FmMacsecSecY, macsecAN_t an); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_TxSaGetActive -+ -+ @Description Get the active SA that being used for TX. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[out] p_An the active an. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_TxSaGetActive(t_Handle h_FmMacsecSecY, macsecAN_t *p_An); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_GetStatistics -+ -+ @Description get all statistics counters. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] p_Statistics Structure with statistics. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_GetStatistics(t_Handle h_FmMacsecSecY, t_FmMacsecSecYStatistics *p_Statistics); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_RxScGetStatistics -+ -+ @Description get all statistics counters. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] h_Sc Rx Sc handle. -+ @Param[in] p_Statistics Structure with statistics. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_RxScGetStatistics(t_Handle h_FmMacsecSecY, t_Handle h_Sc, t_FmMacsecSecYRxScStatistics *p_Statistics); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_RxSaGetStatistics -+ -+ @Description get all statistics counters -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] h_Sc Rx Sc handle. -+ @Param[in] an association number represent the SA. -+ @Param[in] p_Statistics Structure with statistics. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_RxSaGetStatistics(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, t_FmMacsecSecYRxSaStatistics *p_Statistics); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_TxScGetStatistics -+ -+ @Description get all statistics counters. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] p_Statistics Structure with statistics. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_TxScGetStatistics(t_Handle h_FmMacsecSecY, t_FmMacsecSecYTxScStatistics *p_Statistics); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_TxSaGetStatistics -+ -+ @Description get all statistics counters. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] an association number represent the SA. -+ @Param[in] p_Statistics Structure with statistics. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_TxSaGetStatistics(t_Handle h_FmMacsecSecY, macsecAN_t an, t_FmMacsecSecYTxSaStatistics *p_Statistics); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_SetException -+ -+ @Description Calling this routine enables/disables the specified exception. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] exception The exception to be selected. -+ @Param[in] enable TRUE to enable interrupt, FALSE to mask it. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_SetException(t_Handle h_FmMacsecSecY, e_FmMacsecExceptions exception, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_SetEvent -+ -+ @Description Calling this routine enables/disables the specified event. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] event The event to be selected. -+ @Param[in] enable TRUE to enable interrupt, FALSE to mask it. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Config() and before FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_SetEvent(t_Handle h_FmMacsecSecY, e_FmMacsecSecYEvents event, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_GetRxScPhysId -+ -+ @Description return the physical id of the Secure Channel. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[in] h_Sc SC handle as returned by FM_MACSEC_SECY_CreateRxSc. -+ @Param[out] p_ScPhysId the SC physical id. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_CreateRxSc(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_GetRxScPhysId(t_Handle h_FmMacsecSecY, t_Handle h_Sc, uint32_t *p_ScPhysId); -+ -+/**************************************************************************//** -+ @Function FM_MACSEC_SECY_GetTxScPhysId -+ -+ @Description return the physical id of the Secure Channel. -+ -+ @Param[in] h_FmMacsecSecY FM MACSEC SECY module descriptor. -+ @Param[out] p_ScPhysId the SC physical id. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MACSEC_SECY_Init(). -+*//***************************************************************************/ -+t_Error FM_MACSEC_SECY_GetTxScPhysId(t_Handle h_FmMacsecSecY, uint32_t *p_ScPhysId); -+ -+/** @} */ /* end of FM_MACSEC_SECY_runtime_control_grp group */ -+/** @} */ /* end of FM_MACSEC_SECY_grp group */ -+/** @} */ /* end of FM_MACSEC_grp group */ -+/** @} */ /* end of FM_grp group */ -+ -+ -+#endif /* __FM_MACSEC_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_muram_ext.h -@@ -0,0 +1,170 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File fm_muram_ext.h -+ -+ @Description FM MURAM Application Programming Interface. -+*//***************************************************************************/ -+#ifndef __FM_MURAM_EXT -+#define __FM_MURAM_EXT -+ -+#include "error_ext.h" -+#include "std_ext.h" -+ -+ -+/**************************************************************************//** -+ -+ @Group FM_grp Frame Manager API -+ -+ @Description FM API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group FM_muram_grp FM MURAM -+ -+ @Description FM MURAM API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group FM_muram_init_grp FM MURAM Initialization Unit -+ -+ @Description FM MURAM initialization API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_MURAM_ConfigAndInit -+ -+ @Description Creates partition in the MURAM. -+ -+ The routine returns a handle (descriptor) to the MURAM partition. -+ This descriptor must be passed as first parameter to all other -+ FM-MURAM function calls. -+ -+ No actual initialization or configuration of FM_MURAM hardware is -+ done by this routine. -+ -+ @Param[in] baseAddress - Pointer to base of memory mapped FM-MURAM. -+ @Param[in] size - Size of the FM-MURAM partition. -+ -+ @Return Handle to FM-MURAM object, or NULL for Failure. -+*//***************************************************************************/ -+t_Handle FM_MURAM_ConfigAndInit(uintptr_t baseAddress, uint32_t size); -+ -+/**************************************************************************//** -+ @Function FM_MURAM_Free -+ -+ @Description Frees all resources that were assigned to FM-MURAM module. -+ -+ Calling this routine invalidates the descriptor. -+ -+ @Param[in] h_FmMuram - FM-MURAM module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_MURAM_Free(t_Handle h_FmMuram); -+ -+/** @} */ /* end of FM_muram_init_grp group */ -+ -+ -+/**************************************************************************//** -+ @Group FM_muram_ctrl_grp FM MURAM Control Unit -+ -+ @Description FM MURAM control API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_MURAM_AllocMem -+ -+ @Description Allocate some memory from FM-MURAM partition. -+ -+ @Param[in] h_FmMuram - FM-MURAM module descriptor. -+ @Param[in] size - size of the memory to be allocated. -+ @Param[in] align - Alignment of the memory. -+ -+ @Return address of the allocated memory; NULL otherwise. -+*//***************************************************************************/ -+void * FM_MURAM_AllocMem(t_Handle h_FmMuram, uint32_t size, uint32_t align); -+ -+/**************************************************************************//** -+ @Function FM_MURAM_AllocMemForce -+ -+ @Description Allocate some specific memory from FM-MURAM partition (according -+ to base). -+ -+ @Param[in] h_FmMuram - FM-MURAM module descriptor. -+ @Param[in] base - the desired base-address to be allocated. -+ @Param[in] size - size of the memory to be allocated. -+ -+ @Return address of the allocated memory; NULL otherwise. -+*//***************************************************************************/ -+void * FM_MURAM_AllocMemForce(t_Handle h_FmMuram, uint64_t base, uint32_t size); -+ -+/**************************************************************************//** -+ @Function FM_MURAM_FreeMem -+ -+ @Description Free an allocated memory from FM-MURAM partition. -+ -+ @Param[in] h_FmMuram - FM-MURAM module descriptor. -+ @Param[in] ptr - A pointer to an allocated memory. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_MURAM_FreeMem(t_Handle h_FmMuram, void *ptr); -+ -+/**************************************************************************//** -+ @Function FM_MURAM_GetFreeMemSize -+ -+ @Description Returns the size (in bytes) of free MURAM memory. -+ -+ @Param[in] h_FmMuram - FM-MURAM module descriptor. -+ -+ @Return Free MURAM memory size in bytes. -+*//***************************************************************************/ -+uint64_t FM_MURAM_GetFreeMemSize(t_Handle h_FmMuram); -+ -+/** @} */ /* end of FM_muram_ctrl_grp group */ -+/** @} */ /* end of FM_muram_grp group */ -+/** @} */ /* end of FM_grp group */ -+ -+ -+ -+#endif /* __FM_MURAM_EXT */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_pcd_ext.h -@@ -0,0 +1,3974 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File fm_pcd_ext.h -+ -+ @Description FM PCD API definitions -+*//***************************************************************************/ -+#ifndef __FM_PCD_EXT -+#define __FM_PCD_EXT -+ -+#include "std_ext.h" -+#include "net_ext.h" -+#include "list_ext.h" -+#include "fm_ext.h" -+#include "fsl_fman_kg.h" -+ -+ -+/**************************************************************************//** -+ @Group FM_grp Frame Manager API -+ -+ @Description Frame Manager Application Programming Interface -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group FM_PCD_grp FM PCD -+ -+ @Description Frame Manager PCD (Parse-Classify-Distribute) API. -+ -+ The FM PCD module is responsible for the initialization of all -+ global classifying FM modules. This includes the parser general and -+ common registers, the key generator global and common registers, -+ and the policer global and common registers. -+ In addition, the FM PCD SW module will initialize all required -+ key generator schemes, coarse classification flows, and policer -+ profiles. When FM module is configured to work with one of these -+ entities, it will register to it using the FM PORT API. The PCD -+ module will manage the PCD resources - i.e. resource management of -+ KeyGen schemes, etc. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Collection General PCD defines -+*//***************************************************************************/ -+#define FM_PCD_MAX_NUM_OF_PRIVATE_HDRS 2 /**< Number of units/headers saved for user */ -+ -+#define FM_PCD_PRS_NUM_OF_HDRS 16 /**< Number of headers supported by HW parser */ -+#define FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS (32 - FM_PCD_MAX_NUM_OF_PRIVATE_HDRS) -+ /**< Number of distinction units is limited by -+ register size (32 bits) minus reserved bits -+ for private headers. */ -+#define FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS 4 /**< Maximum number of interchangeable headers -+ in a distinction unit */ -+#define FM_PCD_KG_NUM_OF_GENERIC_REGS FM_KG_NUM_OF_GENERIC_REGS /**< Total number of generic KeyGen registers */ -+#define FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY 35 /**< Max number allowed on any configuration; -+ For HW implementation reasons, in most -+ cases less than this will be allowed; The -+ driver will return an initialization error -+ if resource is unavailable. */ -+#define FM_PCD_KG_NUM_OF_EXTRACT_MASKS 4 /**< Total number of masks allowed on KeyGen extractions. */ -+#define FM_PCD_KG_NUM_OF_DEFAULT_GROUPS 16 /**< Number of default value logical groups */ -+ -+#define FM_PCD_PRS_NUM_OF_LABELS 32 /**< Maximum number of SW parser labels */ -+#define FM_SW_PRS_MAX_IMAGE_SIZE (FM_PCD_SW_PRS_SIZE /*- FM_PCD_PRS_SW_OFFSET -FM_PCD_PRS_SW_TAIL_SIZE*/-FM_PCD_PRS_SW_PATCHES_SIZE) -+ /**< Maximum size of SW parser code */ -+ -+#define FM_PCD_MAX_MANIP_INSRT_TEMPLATE_SIZE 128 /**< Maximum size of insertion template for -+ insert manipulation */ -+ -+#if (DPAA_VERSION >= 11) -+#define FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES 64 /**< Maximum possible entries for frame replicator group */ -+#endif /* (DPAA_VERSION >= 11) */ -+/* @} */ -+ -+ -+/**************************************************************************//** -+ @Group FM_PCD_init_grp FM PCD Initialization Unit -+ -+ @Description Frame Manager PCD Initialization Unit API -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description PCD counters -+*//***************************************************************************/ -+typedef enum e_FmPcdCounters { -+ e_FM_PCD_KG_COUNTERS_TOTAL, /**< KeyGen counter */ -+ e_FM_PCD_PLCR_COUNTERS_RED, /**< Policer counter - counts the total number of RED packets that exit the Policer. */ -+ e_FM_PCD_PLCR_COUNTERS_YELLOW, /**< Policer counter - counts the total number of YELLOW packets that exit the Policer. */ -+ e_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_RED, /**< Policer counter - counts the number of packets that changed color to RED by the Policer; -+ This is a subset of e_FM_PCD_PLCR_COUNTERS_RED packet count, indicating active color changes. */ -+ e_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_YELLOW, /**< Policer counter - counts the number of packets that changed color to YELLOW by the Policer; -+ This is a subset of e_FM_PCD_PLCR_COUNTERS_YELLOW packet count, indicating active color changes. */ -+ e_FM_PCD_PLCR_COUNTERS_TOTAL, /**< Policer counter - counts the total number of packets passed in the Policer. */ -+ e_FM_PCD_PLCR_COUNTERS_LENGTH_MISMATCH, /**< Policer counter - counts the number of packets with length mismatch. */ -+ e_FM_PCD_PRS_COUNTERS_PARSE_DISPATCH, /**< Parser counter - counts the number of times the parser block is dispatched. */ -+ e_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED, /**< Parser counter - counts the number of times L2 parse result is returned (including errors). */ -+ e_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED, /**< Parser counter - counts the number of times L3 parse result is returned (including errors). */ -+ e_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED, /**< Parser counter - counts the number of times L4 parse result is returned (including errors). */ -+ e_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED, /**< Parser counter - counts the number of times SHIM parse result is returned (including errors). */ -+ e_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED_WITH_ERR, /**< Parser counter - counts the number of times L2 parse result is returned with errors. */ -+ e_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED_WITH_ERR, /**< Parser counter - counts the number of times L3 parse result is returned with errors. */ -+ e_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED_WITH_ERR, /**< Parser counter - counts the number of times L4 parse result is returned with errors. */ -+ e_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED_WITH_ERR, /**< Parser counter - counts the number of times SHIM parse result is returned with errors. */ -+ e_FM_PCD_PRS_COUNTERS_SOFT_PRS_CYCLES, /**< Parser counter - counts the number of cycles spent executing soft parser instruction (including stall cycles). */ -+ e_FM_PCD_PRS_COUNTERS_SOFT_PRS_STALL_CYCLES, /**< Parser counter - counts the number of cycles stalled waiting for parser internal memory reads while executing soft parser instruction. */ -+ e_FM_PCD_PRS_COUNTERS_HARD_PRS_CYCLE_INCL_STALL_CYCLES, /**< Parser counter - counts the number of cycles spent executing hard parser (including stall cycles). */ -+ e_FM_PCD_PRS_COUNTERS_MURAM_READ_CYCLES, /**< MURAM counter - counts the number of cycles while performing FMan Memory read. */ -+ e_FM_PCD_PRS_COUNTERS_MURAM_READ_STALL_CYCLES, /**< MURAM counter - counts the number of cycles stalled while performing FMan Memory read. */ -+ e_FM_PCD_PRS_COUNTERS_MURAM_WRITE_CYCLES, /**< MURAM counter - counts the number of cycles while performing FMan Memory write. */ -+ e_FM_PCD_PRS_COUNTERS_MURAM_WRITE_STALL_CYCLES, /**< MURAM counter - counts the number of cycles stalled while performing FMan Memory write. */ -+ e_FM_PCD_PRS_COUNTERS_FPM_COMMAND_STALL_CYCLES /**< FPM counter - counts the number of cycles stalled while performing a FPM Command. */ -+} e_FmPcdCounters; -+ -+/**************************************************************************//** -+ @Description PCD interrupts -+*//***************************************************************************/ -+typedef enum e_FmPcdExceptions { -+ e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC, /**< KeyGen double-bit ECC error is detected on internal memory read access. */ -+ e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW, /**< KeyGen scheme configuration error indicating a key size larger than 56 bytes. */ -+ e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC, /**< Policer double-bit ECC error has been detected on PRAM read access. */ -+ e_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR, /**< Policer access to a non-initialized profile has been detected. */ -+ e_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE, /**< Policer RAM self-initialization complete */ -+ e_FM_PCD_PLCR_EXCEPTION_ATOMIC_ACTION_COMPLETE, /**< Policer atomic action complete */ -+ e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC, /**< Parser double-bit ECC error */ -+ e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC /**< Parser single-bit ECC error */ -+} e_FmPcdExceptions; -+ -+ -+/**************************************************************************//** -+ @Description Exceptions user callback routine, will be called upon an -+ exception passing the exception identification. -+ -+ @Param[in] h_App - User's application descriptor. -+ @Param[in] exception - The exception. -+ *//***************************************************************************/ -+typedef void (t_FmPcdExceptionCallback) (t_Handle h_App, e_FmPcdExceptions exception); -+ -+/**************************************************************************//** -+ @Description Exceptions user callback routine, will be called upon an exception -+ passing the exception identification. -+ -+ @Param[in] h_App - User's application descriptor. -+ @Param[in] exception - The exception. -+ @Param[in] index - id of the relevant source (may be scheme or profile id). -+ *//***************************************************************************/ -+typedef void (t_FmPcdIdExceptionCallback) ( t_Handle h_App, -+ e_FmPcdExceptions exception, -+ uint16_t index); -+ -+/**************************************************************************//** -+ @Description A callback for enqueuing frame onto a QM queue. -+ -+ @Param[in] h_QmArg - Application's handle passed to QM module on enqueue. -+ @Param[in] p_Fd - Frame descriptor for the frame. -+ -+ @Return E_OK on success; Error code otherwise. -+ *//***************************************************************************/ -+typedef t_Error (t_FmPcdQmEnqueueCallback) (t_Handle h_QmArg, void *p_Fd); -+ -+/**************************************************************************//** -+ @Description Host-Command parameters structure. -+ -+ When using Host command for PCD functionalities, a dedicated port -+ must be used. If this routine is called for a PCD in a single partition -+ environment, or it is the Master partition in a Multi-partition -+ environment, The port will be initialized by the PCD driver -+ initialization routine. -+ *//***************************************************************************/ -+typedef struct t_FmPcdHcParams { -+ uintptr_t portBaseAddr; /**< Virtual Address of Host-Command Port memory mapped registers.*/ -+ uint8_t portId; /**< Port Id (0-6 relative to Host-Command/Offline-Parsing ports); -+ NOTE: When configuring Host Command port for -+ FMANv3 devices (DPAA_VERSION 11 and higher), -+ portId=0 MUST be used. */ -+ uint16_t liodnBase; /**< LIODN base for this port, to be used together with LIODN offset -+ (irrelevant for P4080 revision 1.0) */ -+ uint32_t errFqid; /**< Host-Command Port error queue Id. */ -+ uint32_t confFqid; /**< Host-Command Port confirmation queue Id. */ -+ uint32_t qmChannel; /**< QM channel dedicated to this Host-Command port; -+ will be used by the FM for dequeue. */ -+ t_FmPcdQmEnqueueCallback *f_QmEnqueue; /**< Callback routine for enqueuing a frame to the QM */ -+ t_Handle h_QmArg; /**< Application's handle passed to QM module on enqueue */ -+} t_FmPcdHcParams; -+ -+/**************************************************************************//** -+ @Description The main structure for PCD initialization -+ *//***************************************************************************/ -+typedef struct t_FmPcdParams { -+ bool prsSupport; /**< TRUE if Parser will be used for any of the FM ports. */ -+ bool ccSupport; /**< TRUE if Coarse Classification will be used for any -+ of the FM ports. */ -+ bool kgSupport; /**< TRUE if KeyGen will be used for any of the FM ports. */ -+ bool plcrSupport; /**< TRUE if Policer will be used for any of the FM ports. */ -+ t_Handle h_Fm; /**< A handle to the FM module. */ -+ uint8_t numOfSchemes; /**< Number of schemes dedicated to this partition. -+ this parameter is relevant if 'kgSupport'=TRUE. */ -+ bool useHostCommand; /**< Optional for single partition, Mandatory for Multi partition */ -+ t_FmPcdHcParams hc; /**< Host Command parameters, relevant only if 'useHostCommand'=TRUE; -+ Relevant when FM not runs in "guest-mode". */ -+ -+ t_FmPcdExceptionCallback *f_Exception; /**< Callback routine for general PCD exceptions; -+ Relevant when FM not runs in "guest-mode". */ -+ t_FmPcdIdExceptionCallback *f_ExceptionId; /**< Callback routine for specific KeyGen scheme or -+ Policer profile exceptions; -+ Relevant when FM not runs in "guest-mode". */ -+ t_Handle h_App; /**< A handle to an application layer object; This handle will -+ be passed by the driver upon calling the above callbacks; -+ Relevant when FM not runs in "guest-mode". */ -+ uint8_t partPlcrProfilesBase; /**< The first policer-profile-id dedicated to this partition. -+ this parameter is relevant if 'plcrSupport'=TRUE. -+ NOTE: this parameter relevant only when working with multiple partitions. */ -+ uint16_t partNumOfPlcrProfiles; /**< Number of policer-profiles dedicated to this partition. -+ this parameter is relevant if 'plcrSupport'=TRUE. -+ NOTE: this parameter relevant only when working with multiple partitions. */ -+} t_FmPcdParams; -+ -+ -+/**************************************************************************//** -+ @Function FM_PCD_Config -+ -+ @Description Basic configuration of the PCD module. -+ Creates descriptor for the FM PCD module. -+ -+ @Param[in] p_FmPcdParams A structure of parameters for the initialization of PCD. -+ -+ @Return A handle to the initialized module. -+*//***************************************************************************/ -+t_Handle FM_PCD_Config(t_FmPcdParams *p_FmPcdParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_Init -+ -+ @Description Initialization of the PCD module. -+ -+ @Param[in] h_FmPcd - FM PCD module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_PCD_Init(t_Handle h_FmPcd); -+ -+/**************************************************************************//** -+ @Function FM_PCD_Free -+ -+ @Description Frees all resources that were assigned to FM module. -+ -+ Calling this routine invalidates the descriptor. -+ -+ @Param[in] h_FmPcd - FM PCD module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_PCD_Free(t_Handle h_FmPcd); -+ -+/**************************************************************************//** -+ @Group FM_PCD_advanced_cfg_grp FM PCD Advanced Configuration Unit -+ -+ @Description Frame Manager PCD Advanced Configuration API. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_PCD_ConfigException -+ -+ @Description Calling this routine changes the internal driver data base -+ from its default selection of exceptions enabling. -+ [DEFAULT_numOfSharedPlcrProfiles]. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] exception The exception to be selected. -+ @Param[in] enable TRUE to enable interrupt, FALSE to mask it. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_PCD_ConfigException(t_Handle h_FmPcd, e_FmPcdExceptions exception, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_PCD_ConfigHcFramesDataMemory -+ -+ @Description Configures memory-partition-id for FMan-Controller Host-Command -+ frames. Calling this routine changes the internal driver data -+ base from its default configuration [0]. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] memId Memory partition ID. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions This routine may be called only if 'useHostCommand' was TRUE -+ when FM_PCD_Config() routine was called. -+*//***************************************************************************/ -+t_Error FM_PCD_ConfigHcFramesDataMemory(t_Handle h_FmPcd, uint8_t memId); -+ -+/**************************************************************************//** -+ @Function FM_PCD_ConfigPlcrNumOfSharedProfiles -+ -+ @Description Calling this routine changes the internal driver data base -+ from its default selection of exceptions enablement. -+ [DEFAULT_numOfSharedPlcrProfiles]. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] numOfSharedPlcrProfiles Number of profiles to -+ be shared between ports on this partition -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_PCD_ConfigPlcrNumOfSharedProfiles(t_Handle h_FmPcd, uint16_t numOfSharedPlcrProfiles); -+ -+/**************************************************************************//** -+ @Function FM_PCD_ConfigPlcrAutoRefreshMode -+ -+ @Description Calling this routine changes the internal driver data base -+ from its default selection of exceptions enablement. -+ By default auto-refresh is [DEFAULT_plcrAutoRefresh]. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] enable TRUE to enable, FALSE to disable -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_PCD_ConfigPlcrAutoRefreshMode(t_Handle h_FmPcd, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_PCD_ConfigPrsMaxCycleLimit -+ -+ @Description Calling this routine changes the internal data structure for -+ the maximum parsing time from its default value -+ [DEFAULT_MAX_PRS_CYC_LIM]. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] value 0 to disable the mechanism, or new -+ maximum parsing time. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_PCD_ConfigPrsMaxCycleLimit(t_Handle h_FmPcd,uint16_t value); -+ -+/** @} */ /* end of FM_PCD_advanced_cfg_grp group */ -+/** @} */ /* end of FM_PCD_init_grp group */ -+ -+ -+/**************************************************************************//** -+ @Group FM_PCD_Runtime_grp FM PCD Runtime Unit -+ -+ @Description Frame Manager PCD Runtime Unit API -+ -+ The runtime control allows creation of PCD infrastructure modules -+ such as Network Environment Characteristics, Classification Plan -+ Groups and Coarse Classification Trees. -+ It also allows on-the-fly initialization, modification and removal -+ of PCD modules such as KeyGen schemes, coarse classification nodes -+ and Policer profiles. -+ -+ In order to explain the programming model of the PCD driver interface -+ a few terms should be explained, and will be used below. -+ - Distinction Header - One of the 16 protocols supported by the FM parser, -+ or one of the SHIM headers (1 or 2). May be a header with a special -+ option (see below). -+ - Interchangeable Headers Group - This is a group of Headers recognized -+ by either one of them. For example, if in a specific context the user -+ chooses to treat IPv4 and IPV6 in the same way, they may create an -+ interchangeable Headers Unit consisting of these 2 headers. -+ - A Distinction Unit - a Distinction Header or an Interchangeable Headers -+ Group. -+ - Header with special option - applies to Ethernet, MPLS, VLAN, IPv4 and -+ IPv6, includes multicast, broadcast and other protocol specific options. -+ In terms of hardware it relates to the options available in the classification -+ plan. -+ - Network Environment Characteristics - a set of Distinction Units that define -+ the total recognizable header selection for a certain environment. This is -+ NOT the list of all headers that will ever appear in a flow, but rather -+ everything that needs distinction in a flow, where distinction is made by KeyGen -+ schemes and coarse classification action descriptors. -+ -+ The PCD runtime modules initialization is done in stages. The first stage after -+ initializing the PCD module itself is to establish a Network Flows Environment -+ Definition. The application may choose to establish one or more such environments. -+ Later, when needed, the application will have to state, for some of its modules, -+ to which single environment it belongs. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description A structure for SW parser labels -+ *//***************************************************************************/ -+typedef struct t_FmPcdPrsLabelParams { -+ uint32_t instructionOffset; /**< SW parser label instruction offset (2 bytes -+ resolution), relative to Parser RAM. */ -+ e_NetHeaderType hdr; /**< The existence of this header will invoke -+ the SW parser code; Use HEADER_TYPE_NONE -+ to indicate that sw parser is to run -+ independent of the existence of any protocol -+ (run before HW parser). */ -+ uint8_t indexPerHdr; /**< Normally 0, if more than one SW parser -+ attachments for the same header, use this -+ index to distinguish between them. */ -+} t_FmPcdPrsLabelParams; -+ -+/**************************************************************************//** -+ @Description A structure for SW parser -+ *//***************************************************************************/ -+typedef struct t_FmPcdPrsSwParams { -+ bool override; /**< FALSE to invoke a check that nothing else -+ was loaded to this address, including -+ internal patches. -+ TRUE to override any existing code.*/ -+ uint32_t size; /**< SW parser code size */ -+ uint16_t base; /**< SW parser base (in instruction counts! -+ must be larger than 0x20)*/ -+ uint8_t *p_Code; /**< SW parser code */ -+ uint32_t swPrsDataParams[FM_PCD_PRS_NUM_OF_HDRS]; -+ /**< SW parser data (parameters) */ -+ uint8_t numOfLabels; /**< Number of labels for SW parser. */ -+ t_FmPcdPrsLabelParams labelsTable[FM_PCD_PRS_NUM_OF_LABELS]; -+ /**< SW parser labels table, containing -+ numOfLabels entries */ -+} t_FmPcdPrsSwParams; -+ -+ -+/**************************************************************************//** -+ @Function FM_PCD_Enable -+ -+ @Description This routine should be called after PCD is initialized for enabling all -+ PCD engines according to their existing configuration. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init() and when PCD is disabled. -+*//***************************************************************************/ -+t_Error FM_PCD_Enable(t_Handle h_FmPcd); -+ -+/**************************************************************************//** -+ @Function FM_PCD_Disable -+ -+ @Description This routine may be called when PCD is enabled in order to -+ disable all PCD engines. It may be called -+ only when none of the ports in the system are using the PCD. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init() and when PCD is enabled. -+*//***************************************************************************/ -+t_Error FM_PCD_Disable(t_Handle h_FmPcd); -+ -+/**************************************************************************//** -+ @Function FM_PCD_GetCounter -+ -+ @Description Reads one of the FM PCD counters. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] counter The requested counter. -+ -+ @Return Counter's current value. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+ Note that it is user's responsibility to call this routine only -+ for enabled counters, and there will be no indication if a -+ disabled counter is accessed. -+*//***************************************************************************/ -+uint32_t FM_PCD_GetCounter(t_Handle h_FmPcd, e_FmPcdCounters counter); -+ -+/**************************************************************************//** -+@Function FM_PCD_PrsLoadSw -+ -+@Description This routine may be called in order to load software parsing code. -+ -+ -+@Param[in] h_FmPcd FM PCD module descriptor. -+@Param[in] p_SwPrs A pointer to a structure of software -+ parser parameters, including the software -+ parser image. -+ -+@Return E_OK on success; Error code otherwise. -+ -+@Cautions Allowed only following FM_PCD_Init() and when PCD is disabled. -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_PCD_PrsLoadSw(t_Handle h_FmPcd, t_FmPcdPrsSwParams *p_SwPrs); -+ -+/**************************************************************************//** -+@Function FM_PCD_SetAdvancedOffloadSupport -+ -+@Description This routine must be called in order to support the following features: -+ IP-fragmentation, IP-reassembly, IPsec, Header-manipulation, frame-replicator. -+ -+@Param[in] h_FmPcd FM PCD module descriptor. -+ -+@Return E_OK on success; Error code otherwise. -+ -+@Cautions Allowed only following FM_PCD_Init() and when PCD is disabled. -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_PCD_SetAdvancedOffloadSupport(t_Handle h_FmPcd); -+ -+/**************************************************************************//** -+ @Function FM_PCD_KgSetDfltValue -+ -+ @Description Calling this routine sets a global default value to be used -+ by the KeyGen when parser does not recognize a required -+ field/header. -+ By default default values are 0. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] valueId 0,1 - one of 2 global default values. -+ @Param[in] value The requested default value. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init() and when PCD is disabled. -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_PCD_KgSetDfltValue(t_Handle h_FmPcd, uint8_t valueId, uint32_t value); -+ -+/**************************************************************************//** -+ @Function FM_PCD_KgSetAdditionalDataAfterParsing -+ -+ @Description Calling this routine allows the KeyGen to access data past -+ the parser finishing point. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] payloadOffset the number of bytes beyond the parser location. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init() and when PCD is disabled. -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_PCD_KgSetAdditionalDataAfterParsing(t_Handle h_FmPcd, uint8_t payloadOffset); -+ -+/**************************************************************************//** -+ @Function FM_PCD_SetException -+ -+ @Description Calling this routine enables/disables PCD interrupts. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] exception The exception to be selected. -+ @Param[in] enable TRUE to enable interrupt, FALSE to mask it. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_PCD_SetException(t_Handle h_FmPcd, e_FmPcdExceptions exception, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_PCD_ModifyCounter -+ -+ @Description Sets a value to an enabled counter. Use "0" to reset the counter. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] counter The requested counter. -+ @Param[in] value The requested value to be written into the counter. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_PCD_ModifyCounter(t_Handle h_FmPcd, e_FmPcdCounters counter, uint32_t value); -+ -+/**************************************************************************//** -+ @Function FM_PCD_SetPlcrStatistics -+ -+ @Description This routine may be used to enable/disable policer statistics -+ counter. By default the statistics is enabled. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor -+ @Param[in] enable TRUE to enable, FALSE to disable. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_PCD_SetPlcrStatistics(t_Handle h_FmPcd, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_PCD_SetPrsStatistics -+ -+ @Description Defines whether to gather parser statistics including all ports. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] enable TRUE to enable, FALSE to disable. -+ -+ @Return None -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+void FM_PCD_SetPrsStatistics(t_Handle h_FmPcd, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_PCD_HcTxConf -+ -+ @Description This routine should be called to confirm frames that were -+ received on the HC confirmation queue. -+ -+ @Param[in] h_FmPcd A handle to an FM PCD Module. -+ @Param[in] p_Fd Frame descriptor of the received frame. -+ -+ @Cautions Allowed only following FM_PCD_Init(). Allowed only if 'useHostCommand' -+ option was selected in the initialization. -+*//***************************************************************************/ -+void FM_PCD_HcTxConf(t_Handle h_FmPcd, t_DpaaFD *p_Fd); -+ -+/**************************************************************************//* -+ @Function FM_PCD_ForceIntr -+ -+ @Description Causes an interrupt event on the requested source. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] exception An exception to be forced. -+ -+ @Return E_OK on success; Error code if the exception is not enabled, -+ or is not able to create interrupt. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_PCD_ForceIntr (t_Handle h_FmPcd, e_FmPcdExceptions exception); -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+/**************************************************************************//** -+ @Function FM_PCD_DumpRegs -+ -+ @Description Dumps all PCD registers -+ -+ @Param[in] h_FmPcd A handle to an FM PCD Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+ NOTE: this routine may be called only for FM in master mode -+ (i.e. 'guestId'=NCSW_MASTER_ID) or in a case that the registers -+ are mapped. -+*//***************************************************************************/ -+t_Error FM_PCD_DumpRegs(t_Handle h_FmPcd); -+ -+/**************************************************************************//** -+ @Function FM_PCD_KgDumpRegs -+ -+ @Description Dumps all PCD KG registers -+ -+ @Param[in] h_FmPcd A handle to an FM PCD Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+ NOTE: this routine may be called only for FM in master mode -+ (i.e. 'guestId'=NCSW_MASTER_ID) or in a case that the registers -+ are mapped. -+*//***************************************************************************/ -+t_Error FM_PCD_KgDumpRegs(t_Handle h_FmPcd); -+ -+/**************************************************************************//** -+ @Function FM_PCD_PlcrDumpRegs -+ -+ @Description Dumps all PCD Policer registers -+ -+ @Param[in] h_FmPcd A handle to an FM PCD Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+ NOTE: this routine may be called only for FM in master mode -+ (i.e. 'guestId'=NCSW_MASTER_ID) or in a case that the registers -+ are mapped. -+*//***************************************************************************/ -+t_Error FM_PCD_PlcrDumpRegs(t_Handle h_FmPcd); -+ -+/**************************************************************************//** -+ @Function FM_PCD_PlcrProfileDumpRegs -+ -+ @Description Dumps all PCD Policer profile registers -+ -+ @Param[in] h_Profile A handle to a Policer profile. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+ NOTE: this routine may be called only for FM in master mode -+ (i.e. 'guestId'=NCSW_MASTER_ID) or in a case that the registers -+ are mapped. -+*//***************************************************************************/ -+t_Error FM_PCD_PlcrProfileDumpRegs(t_Handle h_Profile); -+ -+/**************************************************************************//** -+ @Function FM_PCD_PrsDumpRegs -+ -+ @Description Dumps all PCD Parser registers -+ -+ @Param[in] h_FmPcd A handle to an FM PCD Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+ NOTE: this routine may be called only for FM in master mode -+ (i.e. 'guestId'=NCSW_MASTER_ID) or in a case that the registers -+ are mapped. -+*//***************************************************************************/ -+t_Error FM_PCD_PrsDumpRegs(t_Handle h_FmPcd); -+ -+/**************************************************************************//** -+ @Function FM_PCD_HcDumpRegs -+ -+ @Description Dumps HC Port registers -+ -+ @Param[in] h_FmPcd A handle to an FM PCD Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+ NOTE: this routine may be called only for FM in master mode -+ (i.e. 'guestId'=NCSW_MASTER_ID). -+*//***************************************************************************/ -+t_Error FM_PCD_HcDumpRegs(t_Handle h_FmPcd); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+ -+ -+/**************************************************************************//** -+ KeyGen FM_PCD_Runtime_build_grp FM PCD Runtime Building Unit -+ -+ @Description Frame Manager PCD Runtime Building API -+ -+ This group contains routines for setting, deleting and modifying -+ PCD resources, for defining the total PCD tree. -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Collection Definitions of coarse classification -+ parameters as required by KeyGen (when coarse classification -+ is the next engine after this scheme). -+*//***************************************************************************/ -+#define FM_PCD_MAX_NUM_OF_CC_TREES 8 -+#define FM_PCD_MAX_NUM_OF_CC_GROUPS 16 -+#define FM_PCD_MAX_NUM_OF_CC_UNITS 4 -+#define FM_PCD_MAX_NUM_OF_KEYS 256 -+#define FM_PCD_MAX_NUM_OF_FLOWS (4*KILOBYTE) -+#define FM_PCD_MAX_SIZE_OF_KEY 56 -+#define FM_PCD_MAX_NUM_OF_CC_ENTRIES_IN_GRP 16 -+#define FM_PCD_LAST_KEY_INDEX 0xffff -+ -+#define FM_PCD_MAX_NUM_OF_CC_NODES 255 /* Obsolete, not used - will be removed in the future */ -+/* @} */ -+ -+/**************************************************************************//** -+ @Collection A set of definitions to allow protocol -+ special option description. -+*//***************************************************************************/ -+typedef uint32_t protocolOpt_t; /**< A general type to define a protocol option. */ -+ -+typedef protocolOpt_t ethProtocolOpt_t; /**< Ethernet protocol options. */ -+#define ETH_BROADCAST 0x80000000 /**< Ethernet Broadcast. */ -+#define ETH_MULTICAST 0x40000000 /**< Ethernet Multicast. */ -+ -+typedef protocolOpt_t vlanProtocolOpt_t; /**< VLAN protocol options. */ -+#define VLAN_STACKED 0x20000000 /**< Stacked VLAN. */ -+ -+typedef protocolOpt_t mplsProtocolOpt_t; /**< MPLS protocol options. */ -+#define MPLS_STACKED 0x10000000 /**< Stacked MPLS. */ -+ -+typedef protocolOpt_t ipv4ProtocolOpt_t; /**< IPv4 protocol options. */ -+#define IPV4_BROADCAST_1 0x08000000 /**< IPv4 Broadcast. */ -+#define IPV4_MULTICAST_1 0x04000000 /**< IPv4 Multicast. */ -+#define IPV4_UNICAST_2 0x02000000 /**< Tunneled IPv4 - Unicast. */ -+#define IPV4_MULTICAST_BROADCAST_2 0x01000000 /**< Tunneled IPv4 - Broadcast/Multicast. */ -+ -+#define IPV4_FRAG_1 0x00000008 /**< IPV4 reassembly option. -+ IPV4 Reassembly manipulation requires network -+ environment with IPV4 header and IPV4_FRAG_1 option */ -+ -+typedef protocolOpt_t ipv6ProtocolOpt_t; /**< IPv6 protocol options. */ -+#define IPV6_MULTICAST_1 0x00800000 /**< IPv6 Multicast. */ -+#define IPV6_UNICAST_2 0x00400000 /**< Tunneled IPv6 - Unicast. */ -+#define IPV6_MULTICAST_2 0x00200000 /**< Tunneled IPv6 - Multicast. */ -+ -+#define IPV6_FRAG_1 0x00000004 /**< IPV6 reassembly option. -+ IPV6 Reassembly manipulation requires network -+ environment with IPV6 header and IPV6_FRAG_1 option; -+ in case where fragment found, the fragment-extension offset -+ may be found at 'shim2' (in parser-result). */ -+#if (DPAA_VERSION >= 11) -+typedef protocolOpt_t capwapProtocolOpt_t; /**< CAPWAP protocol options. */ -+#define CAPWAP_FRAG_1 0x00000008 /**< CAPWAP reassembly option. -+ CAPWAP Reassembly manipulation requires network -+ environment with CAPWAP header and CAPWAP_FRAG_1 option; -+ in case where fragment found, the fragment-extension offset -+ may be found at 'shim2' (in parser-result). */ -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ -+/* @} */ -+ -+#define FM_PCD_MANIP_MAX_HDR_SIZE 256 -+#define FM_PCD_MANIP_DSCP_TO_VLAN_TRANS 64 -+ -+/**************************************************************************//** -+ @Collection A set of definitions to support Header Manipulation selection. -+*//***************************************************************************/ -+typedef uint32_t hdrManipFlags_t; /**< A general type to define a HMan update command flags. */ -+ -+typedef hdrManipFlags_t ipv4HdrManipUpdateFlags_t; /**< IPv4 protocol HMan update command flags. */ -+ -+#define HDR_MANIP_IPV4_TOS 0x80000000 /**< update TOS with the given value ('tos' field -+ of t_FmPcdManipHdrFieldUpdateIpv4) */ -+#define HDR_MANIP_IPV4_ID 0x40000000 /**< update IP ID with the given value ('id' field -+ of t_FmPcdManipHdrFieldUpdateIpv4) */ -+#define HDR_MANIP_IPV4_TTL 0x20000000 /**< Decrement TTL by 1 */ -+#define HDR_MANIP_IPV4_SRC 0x10000000 /**< update IP source address with the given value -+ ('src' field of t_FmPcdManipHdrFieldUpdateIpv4) */ -+#define HDR_MANIP_IPV4_DST 0x08000000 /**< update IP destination address with the given value -+ ('dst' field of t_FmPcdManipHdrFieldUpdateIpv4) */ -+ -+typedef hdrManipFlags_t ipv6HdrManipUpdateFlags_t; /**< IPv6 protocol HMan update command flags. */ -+ -+#define HDR_MANIP_IPV6_TC 0x80000000 /**< update Traffic Class address with the given value -+ ('trafficClass' field of t_FmPcdManipHdrFieldUpdateIpv6) */ -+#define HDR_MANIP_IPV6_HL 0x40000000 /**< Decrement Hop Limit by 1 */ -+#define HDR_MANIP_IPV6_SRC 0x20000000 /**< update IP source address with the given value -+ ('src' field of t_FmPcdManipHdrFieldUpdateIpv6) */ -+#define HDR_MANIP_IPV6_DST 0x10000000 /**< update IP destination address with the given value -+ ('dst' field of t_FmPcdManipHdrFieldUpdateIpv6) */ -+ -+typedef hdrManipFlags_t tcpUdpHdrManipUpdateFlags_t;/**< TCP/UDP protocol HMan update command flags. */ -+ -+#define HDR_MANIP_TCP_UDP_SRC 0x80000000 /**< update TCP/UDP source address with the given value -+ ('src' field of t_FmPcdManipHdrFieldUpdateTcpUdp) */ -+#define HDR_MANIP_TCP_UDP_DST 0x40000000 /**< update TCP/UDP destination address with the given value -+ ('dst' field of t_FmPcdManipHdrFieldUpdateTcpUdp) */ -+#define HDR_MANIP_TCP_UDP_CHECKSUM 0x20000000 /**< update TCP/UDP checksum */ -+ -+/* @} */ -+ -+/**************************************************************************//** -+ @Description A type used for returning the order of the key extraction. -+ each value in this array represents the index of the extraction -+ command as defined by the user in the initialization extraction array. -+ The valid size of this array is the user define number of extractions -+ required (also marked by the second '0' in this array). -+*//***************************************************************************/ -+typedef uint8_t t_FmPcdKgKeyOrder [FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY]; -+ -+/**************************************************************************//** -+ @Description All PCD engines -+*//***************************************************************************/ -+typedef enum e_FmPcdEngine { -+ e_FM_PCD_INVALID = 0, /**< Invalid PCD engine */ -+ e_FM_PCD_DONE, /**< No PCD Engine indicated */ -+ e_FM_PCD_KG, /**< KeyGen */ -+ e_FM_PCD_CC, /**< Coarse classifier */ -+ e_FM_PCD_PLCR, /**< Policer */ -+ e_FM_PCD_PRS, /**< Parser */ -+#if (DPAA_VERSION >= 11) -+ e_FM_PCD_FR, /**< Frame-Replicator */ -+#endif /* (DPAA_VERSION >= 11) */ -+ e_FM_PCD_HASH /**< Hash table */ -+} e_FmPcdEngine; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting extraction by header types -+*//***************************************************************************/ -+typedef enum e_FmPcdExtractByHdrType { -+ e_FM_PCD_EXTRACT_FROM_HDR, /**< Extract bytes from header */ -+ e_FM_PCD_EXTRACT_FROM_FIELD, /**< Extract bytes from header field */ -+ e_FM_PCD_EXTRACT_FULL_FIELD /**< Extract a full field */ -+} e_FmPcdExtractByHdrType; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting extraction source -+ (when it is not the header) -+*//***************************************************************************/ -+typedef enum e_FmPcdExtractFrom { -+ e_FM_PCD_EXTRACT_FROM_FRAME_START, /**< KG & CC: Extract from beginning of frame */ -+ e_FM_PCD_EXTRACT_FROM_DFLT_VALUE, /**< KG only: Extract from a default value */ -+ e_FM_PCD_EXTRACT_FROM_CURR_END_OF_PARSE, /**< KG & CC: Extract from the point where parsing had finished */ -+ e_FM_PCD_EXTRACT_FROM_KEY, /**< CC only: Field where saved KEY */ -+ e_FM_PCD_EXTRACT_FROM_HASH, /**< CC only: Field where saved HASH */ -+ e_FM_PCD_EXTRACT_FROM_PARSE_RESULT, /**< KG only: Extract from the parser result */ -+ e_FM_PCD_EXTRACT_FROM_ENQ_FQID, /**< KG & CC: Extract from enqueue FQID */ -+ e_FM_PCD_EXTRACT_FROM_FLOW_ID /**< CC only: Field where saved Dequeue FQID */ -+} e_FmPcdExtractFrom; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting extraction type -+*//***************************************************************************/ -+typedef enum e_FmPcdExtractType { -+ e_FM_PCD_EXTRACT_BY_HDR, /**< Extract according to header */ -+ e_FM_PCD_EXTRACT_NON_HDR, /**< Extract from data that is not the header */ -+ e_FM_PCD_KG_EXTRACT_PORT_PRIVATE_INFO /**< Extract private info as specified by user */ -+} e_FmPcdExtractType; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting default extraction value -+*//***************************************************************************/ -+typedef enum e_FmPcdKgExtractDfltSelect { -+ e_FM_PCD_KG_DFLT_GBL_0, /**< Default selection is KG register 0 */ -+ e_FM_PCD_KG_DFLT_GBL_1, /**< Default selection is KG register 1 */ -+ e_FM_PCD_KG_DFLT_PRIVATE_0, /**< Default selection is a per scheme register 0 */ -+ e_FM_PCD_KG_DFLT_PRIVATE_1, /**< Default selection is a per scheme register 1 */ -+ e_FM_PCD_KG_DFLT_ILLEGAL /**< Illegal selection */ -+} e_FmPcdKgExtractDfltSelect; -+ -+/**************************************************************************//** -+ @Description Enumeration type defining all default groups - each group shares -+ a default value, one of four user-initialized values. -+*//***************************************************************************/ -+typedef enum e_FmPcdKgKnownFieldsDfltTypes { -+ e_FM_PCD_KG_MAC_ADDR, /**< MAC Address */ -+ e_FM_PCD_KG_TCI, /**< TCI field */ -+ e_FM_PCD_KG_ENET_TYPE, /**< ENET Type */ -+ e_FM_PCD_KG_PPP_SESSION_ID, /**< PPP Session id */ -+ e_FM_PCD_KG_PPP_PROTOCOL_ID, /**< PPP Protocol id */ -+ e_FM_PCD_KG_MPLS_LABEL, /**< MPLS label */ -+ e_FM_PCD_KG_IP_ADDR, /**< IP address */ -+ e_FM_PCD_KG_PROTOCOL_TYPE, /**< Protocol type */ -+ e_FM_PCD_KG_IP_TOS_TC, /**< TOS or TC */ -+ e_FM_PCD_KG_IPV6_FLOW_LABEL, /**< IPV6 flow label */ -+ e_FM_PCD_KG_IPSEC_SPI, /**< IPSEC SPI */ -+ e_FM_PCD_KG_L4_PORT, /**< L4 Port */ -+ e_FM_PCD_KG_TCP_FLAG, /**< TCP Flag */ -+ e_FM_PCD_KG_GENERIC_FROM_DATA, /**< grouping implemented by SW, -+ any data extraction that is not the full -+ field described above */ -+ e_FM_PCD_KG_GENERIC_FROM_DATA_NO_V, /**< grouping implemented by SW, -+ any data extraction without validation */ -+ e_FM_PCD_KG_GENERIC_NOT_FROM_DATA /**< grouping implemented by SW, -+ extraction from parser result or -+ direct use of default value */ -+} e_FmPcdKgKnownFieldsDfltTypes; -+ -+/**************************************************************************//** -+ @Description Enumeration type for defining header index for scenarios with -+ multiple (tunneled) headers -+*//***************************************************************************/ -+typedef enum e_FmPcdHdrIndex { -+ e_FM_PCD_HDR_INDEX_NONE = 0, /**< used when multiple headers not used, also -+ to specify regular IP (not tunneled). */ -+ e_FM_PCD_HDR_INDEX_1, /**< may be used for VLAN, MPLS, tunneled IP */ -+ e_FM_PCD_HDR_INDEX_2, /**< may be used for MPLS, tunneled IP */ -+ e_FM_PCD_HDR_INDEX_3, /**< may be used for MPLS */ -+ e_FM_PCD_HDR_INDEX_LAST = 0xFF /**< may be used for VLAN, MPLS */ -+} e_FmPcdHdrIndex; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting the policer profile functional type -+*//***************************************************************************/ -+typedef enum e_FmPcdProfileTypeSelection { -+ e_FM_PCD_PLCR_PORT_PRIVATE, /**< Port dedicated profile */ -+ e_FM_PCD_PLCR_SHARED /**< Shared profile (shared within partition) */ -+} e_FmPcdProfileTypeSelection; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting the policer profile algorithm -+*//***************************************************************************/ -+typedef enum e_FmPcdPlcrAlgorithmSelection { -+ e_FM_PCD_PLCR_PASS_THROUGH, /**< Policer pass through */ -+ e_FM_PCD_PLCR_RFC_2698, /**< Policer algorithm RFC 2698 */ -+ e_FM_PCD_PLCR_RFC_4115 /**< Policer algorithm RFC 4115 */ -+} e_FmPcdPlcrAlgorithmSelection; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting a policer profile color mode -+*//***************************************************************************/ -+typedef enum e_FmPcdPlcrColorMode { -+ e_FM_PCD_PLCR_COLOR_BLIND, /**< Color blind */ -+ e_FM_PCD_PLCR_COLOR_AWARE /**< Color aware */ -+} e_FmPcdPlcrColorMode; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting a policer profile color -+*//***************************************************************************/ -+typedef enum e_FmPcdPlcrColor { -+ e_FM_PCD_PLCR_GREEN, /**< Green color code */ -+ e_FM_PCD_PLCR_YELLOW, /**< Yellow color code */ -+ e_FM_PCD_PLCR_RED, /**< Red color code */ -+ e_FM_PCD_PLCR_OVERRIDE /**< Color override code */ -+} e_FmPcdPlcrColor; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting the policer profile packet frame length selector -+*//***************************************************************************/ -+typedef enum e_FmPcdPlcrFrameLengthSelect { -+ e_FM_PCD_PLCR_L2_FRM_LEN, /**< L2 frame length */ -+ e_FM_PCD_PLCR_L3_FRM_LEN, /**< L3 frame length */ -+ e_FM_PCD_PLCR_L4_FRM_LEN, /**< L4 frame length */ -+ e_FM_PCD_PLCR_FULL_FRM_LEN /**< Full frame length */ -+} e_FmPcdPlcrFrameLengthSelect; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting roll-back frame -+*//***************************************************************************/ -+typedef enum e_FmPcdPlcrRollBackFrameSelect { -+ e_FM_PCD_PLCR_ROLLBACK_L2_FRM_LEN, /**< Roll-back L2 frame length */ -+ e_FM_PCD_PLCR_ROLLBACK_FULL_FRM_LEN /**< Roll-back Full frame length */ -+} e_FmPcdPlcrRollBackFrameSelect; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting the policer profile packet or byte mode -+*//***************************************************************************/ -+typedef enum e_FmPcdPlcrRateMode { -+ e_FM_PCD_PLCR_BYTE_MODE, /**< Byte mode */ -+ e_FM_PCD_PLCR_PACKET_MODE /**< Packet mode */ -+} e_FmPcdPlcrRateMode; -+ -+/**************************************************************************//** -+ @Description Enumeration type for defining action of frame -+*//***************************************************************************/ -+typedef enum e_FmPcdDoneAction { -+ e_FM_PCD_ENQ_FRAME = 0, /**< Enqueue frame */ -+ e_FM_PCD_DROP_FRAME /**< Mark this frame as error frame and continue -+ to error flow; 'FM_PORT_FRM_ERR_CLS_DISCARD' -+ flag will be set for this frame. */ -+} e_FmPcdDoneAction; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting the policer counter -+*//***************************************************************************/ -+typedef enum e_FmPcdPlcrProfileCounters { -+ e_FM_PCD_PLCR_PROFILE_GREEN_PACKET_TOTAL_COUNTER, /**< Green packets counter */ -+ e_FM_PCD_PLCR_PROFILE_YELLOW_PACKET_TOTAL_COUNTER, /**< Yellow packets counter */ -+ e_FM_PCD_PLCR_PROFILE_RED_PACKET_TOTAL_COUNTER, /**< Red packets counter */ -+ e_FM_PCD_PLCR_PROFILE_RECOLOURED_YELLOW_PACKET_TOTAL_COUNTER, /**< Recolored yellow packets counter */ -+ e_FM_PCD_PLCR_PROFILE_RECOLOURED_RED_PACKET_TOTAL_COUNTER /**< Recolored red packets counter */ -+} e_FmPcdPlcrProfileCounters; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting the PCD action after extraction -+*//***************************************************************************/ -+typedef enum e_FmPcdAction { -+ e_FM_PCD_ACTION_NONE, /**< NONE */ -+ e_FM_PCD_ACTION_EXACT_MATCH, /**< Exact match on the selected extraction */ -+ e_FM_PCD_ACTION_INDEXED_LOOKUP /**< Indexed lookup on the selected extraction */ -+} e_FmPcdAction; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of insert manipulation -+*//***************************************************************************/ -+typedef enum e_FmPcdManipHdrInsrtType { -+ e_FM_PCD_MANIP_INSRT_GENERIC, /**< Insert according to offset & size */ -+ e_FM_PCD_MANIP_INSRT_BY_HDR, /**< Insert according to protocol */ -+#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+ e_FM_PCD_MANIP_INSRT_BY_TEMPLATE /**< Insert template to start of frame */ -+#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+} e_FmPcdManipHdrInsrtType; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of remove manipulation -+*//***************************************************************************/ -+typedef enum e_FmPcdManipHdrRmvType { -+ e_FM_PCD_MANIP_RMV_GENERIC, /**< Remove according to offset & size */ -+ e_FM_PCD_MANIP_RMV_BY_HDR /**< Remove according to offset & size */ -+} e_FmPcdManipHdrRmvType; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting specific L2 fields removal -+*//***************************************************************************/ -+typedef enum e_FmPcdManipHdrRmvSpecificL2 { -+ e_FM_PCD_MANIP_HDR_RMV_ETHERNET, /**< Ethernet/802.3 MAC */ -+ e_FM_PCD_MANIP_HDR_RMV_STACKED_QTAGS, /**< stacked QTags */ -+ e_FM_PCD_MANIP_HDR_RMV_ETHERNET_AND_MPLS, /**< MPLS and Ethernet/802.3 MAC header until -+ the header which follows the MPLS header */ -+ e_FM_PCD_MANIP_HDR_RMV_MPLS, /**< Remove MPLS header (Unlimited MPLS labels) */ -+ e_FM_PCD_MANIP_HDR_RMV_PPPOE /**< Remove the PPPoE header and PPP protocol field. */ -+} e_FmPcdManipHdrRmvSpecificL2; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting specific fields updates -+*//***************************************************************************/ -+typedef enum e_FmPcdManipHdrFieldUpdateType { -+ e_FM_PCD_MANIP_HDR_FIELD_UPDATE_VLAN, /**< VLAN updates */ -+ e_FM_PCD_MANIP_HDR_FIELD_UPDATE_IPV4, /**< IPV4 updates */ -+ e_FM_PCD_MANIP_HDR_FIELD_UPDATE_IPV6, /**< IPV6 updates */ -+ e_FM_PCD_MANIP_HDR_FIELD_UPDATE_TCP_UDP, /**< TCP_UDP updates */ -+} e_FmPcdManipHdrFieldUpdateType; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting VLAN updates -+*//***************************************************************************/ -+typedef enum e_FmPcdManipHdrFieldUpdateVlan { -+ e_FM_PCD_MANIP_HDR_FIELD_UPDATE_VLAN_VPRI, /**< Replace VPri of outer most VLAN tag. */ -+ e_FM_PCD_MANIP_HDR_FIELD_UPDATE_DSCP_TO_VLAN /**< DSCP to VLAN priority bits translation */ -+} e_FmPcdManipHdrFieldUpdateVlan; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting specific L2 header insertion -+*//***************************************************************************/ -+typedef enum e_FmPcdManipHdrInsrtSpecificL2 { -+ e_FM_PCD_MANIP_HDR_INSRT_MPLS, /**< Insert MPLS header (Unlimited MPLS labels) */ -+ e_FM_PCD_MANIP_HDR_INSRT_PPPOE /**< Insert PPPOE */ -+} e_FmPcdManipHdrInsrtSpecificL2; -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description Enumeration type for selecting QoS mapping mode -+ -+ Note: In all cases except 'e_FM_PCD_MANIP_HDR_QOS_MAPPING_NONE' -+ User should instruct the port to read the hash-result -+*//***************************************************************************/ -+typedef enum e_FmPcdManipHdrQosMappingMode { -+ e_FM_PCD_MANIP_HDR_QOS_MAPPING_NONE = 0, /**< No mapping, QoS field will not be changed */ -+ e_FM_PCD_MANIP_HDR_QOS_MAPPING_AS_IS, /**< QoS field will be overwritten by the last byte in the hash-result. */ -+} e_FmPcdManipHdrQosMappingMode; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting QoS source -+ -+ Note: In all cases except 'e_FM_PCD_MANIP_HDR_QOS_SRC_NONE' -+ User should left room for the hash-result on input/output buffer -+ and instruct the port to read/write the hash-result to the buffer (RPD should be set) -+*//***************************************************************************/ -+typedef enum e_FmPcdManipHdrQosSrc { -+ e_FM_PCD_MANIP_HDR_QOS_SRC_NONE = 0, /**< TODO */ -+ e_FM_PCD_MANIP_HDR_QOS_SRC_USER_DEFINED, /**< QoS will be taken from the last byte in the hash-result. */ -+} e_FmPcdManipHdrQosSrc; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of header insertion -+*//***************************************************************************/ -+typedef enum e_FmPcdManipHdrInsrtByHdrType { -+ e_FM_PCD_MANIP_INSRT_BY_HDR_SPECIFIC_L2, /**< Specific L2 fields insertion */ -+#if (DPAA_VERSION >= 11) -+ e_FM_PCD_MANIP_INSRT_BY_HDR_IP, /**< IP insertion */ -+ e_FM_PCD_MANIP_INSRT_BY_HDR_UDP, /**< UDP insertion */ -+ e_FM_PCD_MANIP_INSRT_BY_HDR_UDP_LITE, /**< UDP lite insertion */ -+ e_FM_PCD_MANIP_INSRT_BY_HDR_CAPWAP /**< CAPWAP insertion */ -+#endif /* (DPAA_VERSION >= 11) */ -+} e_FmPcdManipHdrInsrtByHdrType; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting specific customCommand -+*//***************************************************************************/ -+typedef enum e_FmPcdManipHdrCustomType { -+ e_FM_PCD_MANIP_HDR_CUSTOM_IP_REPLACE, /**< Replace IPv4/IPv6 */ -+ e_FM_PCD_MANIP_HDR_CUSTOM_GEN_FIELD_REPLACE, /**< Replace IPv4/IPv6 */ -+} e_FmPcdManipHdrCustomType; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting specific customCommand -+*//***************************************************************************/ -+typedef enum e_FmPcdManipHdrCustomIpReplace { -+ e_FM_PCD_MANIP_HDR_CUSTOM_REPLACE_IPV4_BY_IPV6, /**< Replace IPv4 by IPv6 */ -+ e_FM_PCD_MANIP_HDR_CUSTOM_REPLACE_IPV6_BY_IPV4 /**< Replace IPv6 by IPv4 */ -+} e_FmPcdManipHdrCustomIpReplace; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of header removal -+*//***************************************************************************/ -+typedef enum e_FmPcdManipHdrRmvByHdrType { -+ e_FM_PCD_MANIP_RMV_BY_HDR_SPECIFIC_L2 = 0, /**< Specific L2 fields removal */ -+#if (DPAA_VERSION >= 11) -+ e_FM_PCD_MANIP_RMV_BY_HDR_CAPWAP, /**< CAPWAP removal */ -+#endif /* (DPAA_VERSION >= 11) */ -+#if (DPAA_VERSION >= 11) || ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+ e_FM_PCD_MANIP_RMV_BY_HDR_FROM_START, /**< Locate from data that is not the header */ -+#endif /* (DPAA_VERSION >= 11) || ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+} e_FmPcdManipHdrRmvByHdrType; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of timeout mode -+*//***************************************************************************/ -+typedef enum e_FmPcdManipReassemTimeOutMode { -+ e_FM_PCD_MANIP_TIME_OUT_BETWEEN_FRAMES, /**< Limits the time of the reassembly process -+ from the first fragment to the last */ -+ e_FM_PCD_MANIP_TIME_OUT_BETWEEN_FRAG /**< Limits the time of receiving the fragment */ -+} e_FmPcdManipReassemTimeOutMode; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of WaysNumber mode -+*//***************************************************************************/ -+typedef enum e_FmPcdManipReassemWaysNumber { -+ e_FM_PCD_MANIP_ONE_WAY_HASH = 1, /**< One way hash */ -+ e_FM_PCD_MANIP_TWO_WAYS_HASH, /**< Two ways hash */ -+ e_FM_PCD_MANIP_THREE_WAYS_HASH, /**< Three ways hash */ -+ e_FM_PCD_MANIP_FOUR_WAYS_HASH, /**< Four ways hash */ -+ e_FM_PCD_MANIP_FIVE_WAYS_HASH, /**< Five ways hash */ -+ e_FM_PCD_MANIP_SIX_WAYS_HASH, /**< Six ways hash */ -+ e_FM_PCD_MANIP_SEVEN_WAYS_HASH, /**< Seven ways hash */ -+ e_FM_PCD_MANIP_EIGHT_WAYS_HASH /**< Eight ways hash */ -+} e_FmPcdManipReassemWaysNumber; -+ -+#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of statistics mode -+*//***************************************************************************/ -+typedef enum e_FmPcdStatsType { -+ e_FM_PCD_STATS_PER_FLOWID = 0 /**< Flow ID is used as index for getting statistics */ -+} e_FmPcdStatsType; -+#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting manipulation type -+*//***************************************************************************/ -+typedef enum e_FmPcdManipType { -+ e_FM_PCD_MANIP_HDR = 0, /**< Header manipulation */ -+ e_FM_PCD_MANIP_REASSEM, /**< Reassembly */ -+ e_FM_PCD_MANIP_FRAG, /**< Fragmentation */ -+ e_FM_PCD_MANIP_SPECIAL_OFFLOAD /**< Special Offloading */ -+} e_FmPcdManipType; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of statistics mode -+*//***************************************************************************/ -+typedef enum e_FmPcdCcStatsMode { -+ e_FM_PCD_CC_STATS_MODE_NONE = 0, /**< No statistics support */ -+ e_FM_PCD_CC_STATS_MODE_FRAME, /**< Frame count statistics */ -+ e_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME, /**< Byte and frame count statistics */ -+#if (DPAA_VERSION >= 11) -+ e_FM_PCD_CC_STATS_MODE_RMON, /**< Byte and frame length range count statistics; -+ This mode is supported only on B4860 device */ -+#endif /* (DPAA_VERSION >= 11) */ -+} e_FmPcdCcStatsMode; -+ -+/**************************************************************************//** -+ @Description Enumeration type for determining the action in case an IP packet -+ is larger than MTU but its DF (Don't Fragment) bit is set. -+*//***************************************************************************/ -+typedef enum e_FmPcdManipDontFragAction { -+ e_FM_PCD_MANIP_DISCARD_PACKET = 0, /**< Discard packet */ -+ e_FM_PCD_MANIP_ENQ_TO_ERR_Q_OR_DISCARD_PACKET = e_FM_PCD_MANIP_DISCARD_PACKET, -+ /**< Obsolete, cannot enqueue to error queue; -+ In practice, selects to discard packets; -+ Will be removed in the future */ -+ e_FM_PCD_MANIP_FRAGMENT_PACKET, /**< Fragment packet and continue normal processing */ -+ e_FM_PCD_MANIP_CONTINUE_WITHOUT_FRAG /**< Continue normal processing without fragmenting the packet */ -+} e_FmPcdManipDontFragAction; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of special offload manipulation -+*//***************************************************************************/ -+typedef enum e_FmPcdManipSpecialOffloadType { -+ e_FM_PCD_MANIP_SPECIAL_OFFLOAD_IPSEC, /**< IPSec offload manipulation */ -+#if (DPAA_VERSION >= 11) -+ e_FM_PCD_MANIP_SPECIAL_OFFLOAD_CAPWAP /**< CAPWAP offload manipulation */ -+#endif /* (DPAA_VERSION >= 11) */ -+} e_FmPcdManipSpecialOffloadType; -+ -+ -+/**************************************************************************//** -+ @Description A Union of protocol dependent special options -+*//***************************************************************************/ -+typedef union u_FmPcdHdrProtocolOpt { -+ ethProtocolOpt_t ethOpt; /**< Ethernet options */ -+ vlanProtocolOpt_t vlanOpt; /**< VLAN options */ -+ mplsProtocolOpt_t mplsOpt; /**< MPLS options */ -+ ipv4ProtocolOpt_t ipv4Opt; /**< IPv4 options */ -+ ipv6ProtocolOpt_t ipv6Opt; /**< IPv6 options */ -+#if (DPAA_VERSION >= 11) -+ capwapProtocolOpt_t capwapOpt; /**< CAPWAP options */ -+#endif /* (DPAA_VERSION >= 11) */ -+} u_FmPcdHdrProtocolOpt; -+ -+/**************************************************************************//** -+ @Description A union holding protocol fields -+ -+ -+ Fields supported as "full fields": -+ HEADER_TYPE_ETH: -+ NET_HEADER_FIELD_ETH_DA -+ NET_HEADER_FIELD_ETH_SA -+ NET_HEADER_FIELD_ETH_TYPE -+ -+ HEADER_TYPE_LLC_SNAP: -+ NET_HEADER_FIELD_LLC_SNAP_TYPE -+ -+ HEADER_TYPE_VLAN: -+ NET_HEADER_FIELD_VLAN_TCI -+ (index may apply: -+ e_FM_PCD_HDR_INDEX_NONE/e_FM_PCD_HDR_INDEX_1, -+ e_FM_PCD_HDR_INDEX_LAST) -+ -+ HEADER_TYPE_MPLS: -+ NET_HEADER_FIELD_MPLS_LABEL_STACK -+ (index may apply: -+ e_FM_PCD_HDR_INDEX_NONE/e_FM_PCD_HDR_INDEX_1, -+ e_FM_PCD_HDR_INDEX_2, -+ e_FM_PCD_HDR_INDEX_LAST) -+ -+ HEADER_TYPE_IPv4: -+ NET_HEADER_FIELD_IPv4_SRC_IP -+ NET_HEADER_FIELD_IPv4_DST_IP -+ NET_HEADER_FIELD_IPv4_PROTO -+ NET_HEADER_FIELD_IPv4_TOS -+ (index may apply: -+ e_FM_PCD_HDR_INDEX_NONE/e_FM_PCD_HDR_INDEX_1, -+ e_FM_PCD_HDR_INDEX_2/e_FM_PCD_HDR_INDEX_LAST) -+ -+ HEADER_TYPE_IPv6: -+ NET_HEADER_FIELD_IPv6_SRC_IP -+ NET_HEADER_FIELD_IPv6_DST_IP -+ NET_HEADER_FIELD_IPv6_NEXT_HDR -+ NET_HEADER_FIELD_IPv6_VER | NET_HEADER_FIELD_IPv6_FL | NET_HEADER_FIELD_IPv6_TC (must come together!) -+ (index may apply: -+ e_FM_PCD_HDR_INDEX_NONE/e_FM_PCD_HDR_INDEX_1, -+ e_FM_PCD_HDR_INDEX_2/e_FM_PCD_HDR_INDEX_LAST) -+ -+ (Note that starting from DPAA 1-1, NET_HEADER_FIELD_IPv6_NEXT_HDR applies to -+ the last next header indication, meaning the next L4, which may be -+ present at the Ipv6 last extension. On earlier revisions this field -+ applies to the Next-Header field of the main IPv6 header) -+ -+ HEADER_TYPE_IP: -+ NET_HEADER_FIELD_IP_PROTO -+ (index may apply: -+ e_FM_PCD_HDR_INDEX_LAST) -+ NET_HEADER_FIELD_IP_DSCP -+ (index may apply: -+ e_FM_PCD_HDR_INDEX_NONE/e_FM_PCD_HDR_INDEX_1) -+ HEADER_TYPE_GRE: -+ NET_HEADER_FIELD_GRE_TYPE -+ -+ HEADER_TYPE_MINENCAP -+ NET_HEADER_FIELD_MINENCAP_SRC_IP -+ NET_HEADER_FIELD_MINENCAP_DST_IP -+ NET_HEADER_FIELD_MINENCAP_TYPE -+ -+ HEADER_TYPE_TCP: -+ NET_HEADER_FIELD_TCP_PORT_SRC -+ NET_HEADER_FIELD_TCP_PORT_DST -+ NET_HEADER_FIELD_TCP_FLAGS -+ -+ HEADER_TYPE_UDP: -+ NET_HEADER_FIELD_UDP_PORT_SRC -+ NET_HEADER_FIELD_UDP_PORT_DST -+ -+ HEADER_TYPE_UDP_LITE: -+ NET_HEADER_FIELD_UDP_LITE_PORT_SRC -+ NET_HEADER_FIELD_UDP_LITE_PORT_DST -+ -+ HEADER_TYPE_IPSEC_AH: -+ NET_HEADER_FIELD_IPSEC_AH_SPI -+ NET_HEADER_FIELD_IPSEC_AH_NH -+ -+ HEADER_TYPE_IPSEC_ESP: -+ NET_HEADER_FIELD_IPSEC_ESP_SPI -+ -+ HEADER_TYPE_SCTP: -+ NET_HEADER_FIELD_SCTP_PORT_SRC -+ NET_HEADER_FIELD_SCTP_PORT_DST -+ -+ HEADER_TYPE_DCCP: -+ NET_HEADER_FIELD_DCCP_PORT_SRC -+ NET_HEADER_FIELD_DCCP_PORT_DST -+ -+ HEADER_TYPE_PPPoE: -+ NET_HEADER_FIELD_PPPoE_PID -+ NET_HEADER_FIELD_PPPoE_SID -+ -+ ***************************************************************** -+ Fields supported as "from fields": -+ HEADER_TYPE_ETH (with or without validation): -+ NET_HEADER_FIELD_ETH_TYPE -+ -+ HEADER_TYPE_VLAN (with or without validation): -+ NET_HEADER_FIELD_VLAN_TCI -+ (index may apply: -+ e_FM_PCD_HDR_INDEX_NONE/e_FM_PCD_HDR_INDEX_1, -+ e_FM_PCD_HDR_INDEX_LAST) -+ -+ HEADER_TYPE_IPv4 (without validation): -+ NET_HEADER_FIELD_IPv4_PROTO -+ (index may apply: -+ e_FM_PCD_HDR_INDEX_NONE/e_FM_PCD_HDR_INDEX_1, -+ e_FM_PCD_HDR_INDEX_2/e_FM_PCD_HDR_INDEX_LAST) -+ -+ HEADER_TYPE_IPv6 (without validation): -+ NET_HEADER_FIELD_IPv6_NEXT_HDR -+ (index may apply: -+ e_FM_PCD_HDR_INDEX_NONE/e_FM_PCD_HDR_INDEX_1, -+ e_FM_PCD_HDR_INDEX_2/e_FM_PCD_HDR_INDEX_LAST) -+ -+*//***************************************************************************/ -+typedef union t_FmPcdFields { -+ headerFieldEth_t eth; /**< Ethernet */ -+ headerFieldVlan_t vlan; /**< VLAN */ -+ headerFieldLlcSnap_t llcSnap; /**< LLC SNAP */ -+ headerFieldPppoe_t pppoe; /**< PPPoE */ -+ headerFieldMpls_t mpls; /**< MPLS */ -+ headerFieldIp_t ip; /**< IP */ -+ headerFieldIpv4_t ipv4; /**< IPv4 */ -+ headerFieldIpv6_t ipv6; /**< IPv6 */ -+ headerFieldUdp_t udp; /**< UDP */ -+ headerFieldUdpLite_t udpLite; /**< UDP Lite */ -+ headerFieldTcp_t tcp; /**< TCP */ -+ headerFieldSctp_t sctp; /**< SCTP */ -+ headerFieldDccp_t dccp; /**< DCCP */ -+ headerFieldGre_t gre; /**< GRE */ -+ headerFieldMinencap_t minencap; /**< Minimal Encapsulation */ -+ headerFieldIpsecAh_t ipsecAh; /**< IPSec AH */ -+ headerFieldIpsecEsp_t ipsecEsp; /**< IPSec ESP */ -+ headerFieldUdpEncapEsp_t udpEncapEsp; /**< UDP Encapsulation ESP */ -+} t_FmPcdFields; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header extraction for key generation -+*//***************************************************************************/ -+typedef struct t_FmPcdFromHdr { -+ uint8_t size; /**< Size in byte */ -+ uint8_t offset; /**< Byte offset */ -+} t_FmPcdFromHdr; -+ -+/**************************************************************************//** -+ @Description Parameters for defining field extraction for key generation -+*//***************************************************************************/ -+typedef struct t_FmPcdFromField { -+ t_FmPcdFields field; /**< Field selection */ -+ uint8_t size; /**< Size in byte */ -+ uint8_t offset; /**< Byte offset */ -+} t_FmPcdFromField; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a single network environment unit -+ -+ A distinction unit should be defined if it will later be used -+ by one or more PCD engines to distinguish between flows. -+*//***************************************************************************/ -+typedef struct t_FmPcdDistinctionUnit { -+ struct { -+ e_NetHeaderType hdr; /**< One of the headers supported by the FM */ -+ u_FmPcdHdrProtocolOpt opt; /**< Select only one option ! */ -+ } hdrs[FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS]; -+} t_FmPcdDistinctionUnit; -+ -+/**************************************************************************//** -+ @Description Parameters for defining all different distinction units supported -+ by a specific PCD Network Environment Characteristics module. -+ -+ Each unit represent a protocol or a group of protocols that may -+ be used later by the different PCD engines to distinguish -+ between flows. -+*//***************************************************************************/ -+typedef struct t_FmPcdNetEnvParams { -+ uint8_t numOfDistinctionUnits; /**< Number of different units to be identified */ -+ t_FmPcdDistinctionUnit units[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; /**< An array of numOfDistinctionUnits of the -+ different units to be identified */ -+} t_FmPcdNetEnvParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a single extraction action when -+ creating a key -+*//***************************************************************************/ -+typedef struct t_FmPcdExtractEntry { -+ e_FmPcdExtractType type; /**< Extraction type select */ -+ union { -+ struct { -+ e_NetHeaderType hdr; /**< Header selection */ -+ bool ignoreProtocolValidation; -+ /**< Ignore protocol validation */ -+ e_FmPcdHdrIndex hdrIndex; /**< Relevant only for MPLS, VLAN and tunneled -+ IP. Otherwise should be cleared. */ -+ e_FmPcdExtractByHdrType type; /**< Header extraction type select */ -+ union { -+ t_FmPcdFromHdr fromHdr; /**< Extract bytes from header parameters */ -+ t_FmPcdFromField fromField; /**< Extract bytes from field parameters */ -+ t_FmPcdFields fullField; /**< Extract full filed parameters */ -+ } extractByHdrType; -+ } extractByHdr; /**< used when type = e_FM_PCD_KG_EXTRACT_BY_HDR */ -+ struct { -+ e_FmPcdExtractFrom src; /**< Non-header extraction source */ -+ e_FmPcdAction action; /**< Relevant for CC Only */ -+ uint16_t icIndxMask; /**< Relevant only for CC when -+ action = e_FM_PCD_ACTION_INDEXED_LOOKUP; -+ Note that the number of bits that are set within -+ this mask must be log2 of the CC-node 'numOfKeys'. -+ Note that the mask cannot be set on the lower bits. */ -+ uint8_t offset; /**< Byte offset */ -+ uint8_t size; /**< Size in byte */ -+ } extractNonHdr; /**< used when type = e_FM_PCD_KG_EXTRACT_NON_HDR */ -+ }; -+} t_FmPcdExtractEntry; -+ -+/**************************************************************************//** -+ @Description Parameters for defining masks for each extracted field in the key. -+*//***************************************************************************/ -+typedef struct t_FmPcdKgExtractMask { -+ uint8_t extractArrayIndex; /**< Index in the extraction array, as initialized by user */ -+ uint8_t offset; /**< Byte offset */ -+ uint8_t mask; /**< A byte mask (selected bits will be used) */ -+} t_FmPcdKgExtractMask; -+ -+/**************************************************************************//** -+ @Description Parameters for defining default selection per groups of fields -+*//***************************************************************************/ -+typedef struct t_FmPcdKgExtractDflt { -+ e_FmPcdKgKnownFieldsDfltTypes type; /**< Default type select */ -+ e_FmPcdKgExtractDfltSelect dfltSelect; /**< Default register select */ -+} t_FmPcdKgExtractDflt; -+ -+/**************************************************************************//** -+ @Description Parameters for defining key extraction and hashing -+*//***************************************************************************/ -+typedef struct t_FmPcdKgKeyExtractAndHashParams { -+ uint32_t privateDflt0; /**< Scheme default register 0 */ -+ uint32_t privateDflt1; /**< Scheme default register 1 */ -+ uint8_t numOfUsedExtracts; /**< defines the valid size of the following array */ -+ t_FmPcdExtractEntry extractArray [FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY]; /**< An array of extractions definition. */ -+ uint8_t numOfUsedDflts; /**< defines the valid size of the following array */ -+ t_FmPcdKgExtractDflt dflts[FM_PCD_KG_NUM_OF_DEFAULT_GROUPS]; -+ /**< For each extraction used in this scheme, specify the required -+ default register to be used when header is not found. -+ types not specified in this array will get undefined value. */ -+ uint8_t numOfUsedMasks; /**< defines the valid size of the following array */ -+ t_FmPcdKgExtractMask masks[FM_PCD_KG_NUM_OF_EXTRACT_MASKS]; -+ uint8_t hashShift; /**< hash result right shift. Select the 24 bits out of the 64 hash -+ result. 0 means using the 24 LSB's, otherwise use the -+ 24 LSB's after shifting right.*/ -+ uint32_t hashDistributionNumOfFqids; /**< must be > 1 and a power of 2. Represents the range -+ of queues for the key and hash functionality */ -+ uint8_t hashDistributionFqidsShift; /**< selects the FQID bits that will be effected by the hash */ -+ bool symmetricHash; /**< TRUE to generate the same hash for frames with swapped source and -+ destination fields on all layers; If TRUE, driver will check that for -+ all layers, if SRC extraction is selected, DST extraction must also be -+ selected, and vice versa. */ -+} t_FmPcdKgKeyExtractAndHashParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a single FQID mask (extracted OR). -+*//***************************************************************************/ -+typedef struct t_FmPcdKgExtractedOrParams { -+ e_FmPcdExtractType type; /**< Extraction type select */ -+ union { -+ struct { /**< used when type = e_FM_PCD_KG_EXTRACT_BY_HDR */ -+ e_NetHeaderType hdr; -+ e_FmPcdHdrIndex hdrIndex; /**< Relevant only for MPLS, VLAN and tunneled -+ IP. Otherwise should be cleared.*/ -+ bool ignoreProtocolValidation; -+ /**< continue extraction even if protocol is not recognized */ -+ } extractByHdr; /**< Header to extract by */ -+ e_FmPcdExtractFrom src; /**< used when type = e_FM_PCD_KG_EXTRACT_NON_HDR */ -+ }; -+ uint8_t extractionOffset; /**< Offset for extraction (in bytes). */ -+ e_FmPcdKgExtractDfltSelect dfltValue; /**< Select register from which extraction is taken if -+ field not found */ -+ uint8_t mask; /**< Extraction mask (specified bits are used) */ -+ uint8_t bitOffsetInFqid; /**< 0-31, Selects which bits of the 24 FQID bits to effect using -+ the extracted byte; Assume byte is placed as the 8 MSB's in -+ a 32 bit word where the lower bits -+ are the FQID; i.e if bitOffsetInFqid=1 than its LSB -+ will effect the FQID MSB, if bitOffsetInFqid=24 than the -+ extracted byte will effect the 8 LSB's of the FQID, -+ if bitOffsetInFqid=31 than the byte's MSB will effect -+ the FQID's LSB; 0 means - no effect on FQID; -+ Note that one, and only one of -+ bitOffsetInFqid or bitOffsetInPlcrProfile must be set (i.e, -+ extracted byte must effect either FQID or Policer profile).*/ -+ uint8_t bitOffsetInPlcrProfile; -+ /**< 0-15, Selects which bits of the 8 policer profile id bits to -+ effect using the extracted byte; Assume byte is placed -+ as the 8 MSB's in a 16 bit word where the lower bits -+ are the policer profile id; i.e if bitOffsetInPlcrProfile=1 -+ than its LSB will effect the profile MSB, if bitOffsetInFqid=8 -+ than the extracted byte will effect the whole policer profile id, -+ if bitOffsetInFqid=15 than the byte's MSB will effect -+ the Policer Profile id's LSB; -+ 0 means - no effect on policer profile; Note that one, and only one of -+ bitOffsetInFqid or bitOffsetInPlcrProfile must be set (i.e, -+ extracted byte must effect either FQID or Policer profile).*/ -+} t_FmPcdKgExtractedOrParams; -+ -+/**************************************************************************//** -+ @Description Parameters for configuring a scheme counter -+*//***************************************************************************/ -+typedef struct t_FmPcdKgSchemeCounter { -+ bool update; /**< FALSE to keep the current counter state -+ and continue from that point, TRUE to update/reset -+ the counter when the scheme is written. */ -+ uint32_t value; /**< If update=TRUE, this value will be written into the -+ counter. clear this field to reset the counter. */ -+} t_FmPcdKgSchemeCounter; -+ -+/**************************************************************************//** -+ @Description Parameters for configuring a policer profile for a KeyGen scheme -+ (when policer is the next engine after this scheme). -+*//***************************************************************************/ -+typedef struct t_FmPcdKgPlcrProfile { -+ bool sharedProfile; /**< TRUE if this profile is shared between ports -+ (managed by master partition); Must not be TRUE -+ if profile is after Coarse Classification*/ -+ bool direct; /**< if TRUE, directRelativeProfileId only selects the profile -+ id, if FALSE fqidOffsetRelativeProfileIdBase is used -+ together with fqidOffsetShift and numOfProfiles -+ parameters, to define a range of profiles from -+ which the KeyGen result will determine the -+ destination policer profile. */ -+ union { -+ uint16_t directRelativeProfileId; /**< Used if 'direct' is TRUE, to select policer profile. -+ should indicate the policer profile offset within the -+ port's policer profiles or shared window. */ -+ struct { -+ uint8_t fqidOffsetShift; /**< Shift on the KeyGen create FQID offset (i.e. not the -+ final FQID - without the FQID base). */ -+ uint8_t fqidOffsetRelativeProfileIdBase; -+ /**< The base of the FMan Port's relative Storage-Profile ID; -+ this value will be "OR'ed" with the KeyGen create FQID -+ offset (i.e. not the final FQID - without the FQID base); -+ the final result should indicate the Storage-Profile offset -+ within the FMan Port's relative Storage-Profiles window/ -+ (or the SHARED window depends on 'sharedProfile'). */ -+ uint8_t numOfProfiles; /**< Range of profiles starting at base */ -+ } indirectProfile; /**< Indirect profile parameters */ -+ } profileSelect; /**< Direct/indirect profile selection and parameters */ -+} t_FmPcdKgPlcrProfile; -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description Parameters for configuring a storage profile for a KeyGen scheme. -+*//***************************************************************************/ -+typedef struct t_FmPcdKgStorageProfile { -+ bool direct; /**< If TRUE, directRelativeProfileId only selects the -+ profile id; -+ If FALSE, fqidOffsetRelativeProfileIdBase is used -+ together with fqidOffsetShift and numOfProfiles -+ parameters to define a range of profiles from which -+ the KeyGen result will determine the destination -+ storage profile. */ -+ union { -+ uint16_t directRelativeProfileId; /**< Used when 'direct' is TRUE, to select a storage profile; -+ should indicate the storage profile offset within the -+ port's storage profiles window. */ -+ struct { -+ uint8_t fqidOffsetShift; /**< Shift on the KeyGen create FQID offset (i.e. not the -+ final FQID - without the FQID base). */ -+ uint8_t fqidOffsetRelativeProfileIdBase; -+ /**< The base of the FMan Port's relative Storage-Profile ID; -+ this value will be "OR'ed" with the KeyGen create FQID -+ offset (i.e. not the final FQID - without the FQID base); -+ the final result should indicate the Storage-Profile offset -+ within the FMan Port's relative Storage-Profiles window. */ -+ uint8_t numOfProfiles; /**< Range of profiles starting at base. */ -+ } indirectProfile; /**< Indirect profile parameters. */ -+ } profileSelect; /**< Direct/indirect profile selection and parameters. */ -+} t_FmPcdKgStorageProfile; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Description Parameters for defining CC as the next engine after KeyGen -+*//***************************************************************************/ -+typedef struct t_FmPcdKgCc { -+ t_Handle h_CcTree; /**< A handle to a CC Tree */ -+ uint8_t grpId; /**< CC group id within the CC tree */ -+ bool plcrNext; /**< TRUE if after CC, in case of data frame, -+ policing is required. */ -+ bool bypassPlcrProfileGeneration; /**< TRUE to bypass KeyGen policer profile generation; -+ selected profile is the one set at port initialization. */ -+ t_FmPcdKgPlcrProfile plcrProfile; /**< Valid only if plcrNext = TRUE and -+ bypassPlcrProfileGeneration = FALSE */ -+} t_FmPcdKgCc; -+ -+/**************************************************************************//** -+ @Description Parameters for defining initializing a KeyGen scheme -+*//***************************************************************************/ -+typedef struct t_FmPcdKgSchemeParams { -+ bool modify; /**< TRUE to change an existing scheme */ -+ union -+ { -+ uint8_t relativeSchemeId; /**< if modify=FALSE:Partition relative scheme id */ -+ t_Handle h_Scheme; /**< if modify=TRUE: a handle of the existing scheme */ -+ } id; -+ bool alwaysDirect; /**< This scheme is reached only directly, i.e. no need -+ for match vector; KeyGen will ignore it when matching */ -+ struct { /**< HL Relevant only if alwaysDirect = FALSE */ -+ t_Handle h_NetEnv; /**< A handle to the Network environment as returned -+ by FM_PCD_NetEnvCharacteristicsSet() */ -+ uint8_t numOfDistinctionUnits; /**< Number of NetEnv units listed in unitIds array */ -+ uint8_t unitIds[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; -+ /**< Indexes as passed to SetNetEnvCharacteristics array*/ -+ } netEnvParams; -+ bool useHash; /**< use the KeyGen Hash functionality */ -+ t_FmPcdKgKeyExtractAndHashParams keyExtractAndHashParams; -+ /**< used only if useHash = TRUE */ -+ bool bypassFqidGeneration; /**< Normally - FALSE, TRUE to avoid FQID update in the IC; -+ In such a case FQID after KeyGen will be the default FQID -+ defined for the relevant port, or the FQID defined by CC -+ in cases where CC was the previous engine. */ -+ uint32_t baseFqid; /**< Base FQID; Relevant only if bypassFqidGeneration = FALSE; -+ If hash is used and an even distribution is expected -+ according to hashDistributionNumOfFqids, baseFqid must be aligned to -+ hashDistributionNumOfFqids. */ -+ uint8_t numOfUsedExtractedOrs; /**< Number of FQID masks listed in extractedOrs array */ -+ t_FmPcdKgExtractedOrParams extractedOrs[FM_PCD_KG_NUM_OF_GENERIC_REGS]; -+ /**< FM_PCD_KG_NUM_OF_GENERIC_REGS -+ registers are shared between qidMasks -+ functionality and some of the extraction -+ actions; Normally only some will be used -+ for qidMask. Driver will return error if -+ resource is full at initialization time. */ -+ -+#if (DPAA_VERSION >= 11) -+ bool overrideStorageProfile; /**< TRUE if KeyGen override previously decided storage profile */ -+ t_FmPcdKgStorageProfile storageProfile; /**< Used when overrideStorageProfile TRUE */ -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ e_FmPcdEngine nextEngine; /**< may be BMI, PLCR or CC */ -+ union { /**< depends on nextEngine */ -+ e_FmPcdDoneAction doneAction; /**< Used when next engine is BMI (done) */ -+ t_FmPcdKgPlcrProfile plcrProfile; /**< Used when next engine is PLCR */ -+ t_FmPcdKgCc cc; /**< Used when next engine is CC */ -+ } kgNextEngineParams; -+ t_FmPcdKgSchemeCounter schemeCounter; /**< A structure of parameters for updating -+ the scheme counter */ -+} t_FmPcdKgSchemeParams; -+ -+/**************************************************************************//** -+ @Collection Definitions for CC statistics -+*//***************************************************************************/ -+#if (DPAA_VERSION >= 11) -+#define FM_PCD_CC_STATS_MAX_NUM_OF_FLR 10 /* Maximal supported number of frame length ranges */ -+#define FM_PCD_CC_STATS_FLR_SIZE 2 /* Size in bytes of a frame length range limit */ -+#endif /* (DPAA_VERSION >= 11) */ -+#define FM_PCD_CC_STATS_COUNTER_SIZE 4 /* Size in bytes of a frame length range counter */ -+/* @} */ -+ -+/**************************************************************************//** -+ @Description Parameters for defining CC as the next engine after a CC node. -+*//***************************************************************************/ -+typedef struct t_FmPcdCcNextCcParams { -+ t_Handle h_CcNode; /**< A handle of the next CC node */ -+} t_FmPcdCcNextCcParams; -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description Parameters for defining Frame replicator as the next engine after a CC node. -+*//***************************************************************************/ -+typedef struct t_FmPcdCcNextFrParams { -+ t_Handle h_FrmReplic; /**< A handle of the next frame replicator group */ -+} t_FmPcdCcNextFrParams; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Description Parameters for defining Policer as the next engine after a CC node. -+*//***************************************************************************/ -+typedef struct t_FmPcdCcNextPlcrParams { -+ bool overrideParams; /**< TRUE if CC override previously decided parameters*/ -+ bool sharedProfile; /**< Relevant only if overrideParams=TRUE: -+ TRUE if this profile is shared between ports */ -+ uint16_t newRelativeProfileId; /**< Relevant only if overrideParams=TRUE: -+ (otherwise profile id is taken from KeyGen); -+ This parameter should indicate the policer -+ profile offset within the port's -+ policer profiles or from SHARED window.*/ -+ uint32_t newFqid; /**< Relevant only if overrideParams=TRUE: -+ FQID for enqueuing the frame; -+ In earlier chips if policer next engine is KEYGEN, -+ this parameter can be 0, because the KEYGEN -+ always decides the enqueue FQID.*/ -+#if (DPAA_VERSION >= 11) -+ uint8_t newRelativeStorageProfileId; -+ /**< Indicates the relative storage profile offset within -+ the port's storage profiles window; -+ Relevant only if the port was configured with VSP. */ -+#endif /* (DPAA_VERSION >= 11) */ -+} t_FmPcdCcNextPlcrParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining enqueue as the next action after a CC node. -+*//***************************************************************************/ -+typedef struct t_FmPcdCcNextEnqueueParams { -+ e_FmPcdDoneAction action; /**< Action - when next engine is BMI (done) */ -+ bool overrideFqid; /**< TRUE if CC override previously decided fqid and vspid, -+ relevant if action = e_FM_PCD_ENQ_FRAME */ -+ uint32_t newFqid; /**< Valid if overrideFqid=TRUE, FQID for enqueuing the frame -+ (otherwise FQID is taken from KeyGen), -+ relevant if action = e_FM_PCD_ENQ_FRAME */ -+#if (DPAA_VERSION >= 11) -+ uint8_t newRelativeStorageProfileId; -+ /**< Valid if overrideFqid=TRUE, Indicates the relative virtual -+ storage profile offset within the port's storage profiles -+ window; Relevant only if the port was configured with VSP. */ -+#endif /* (DPAA_VERSION >= 11) */ -+} t_FmPcdCcNextEnqueueParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining KeyGen as the next engine after a CC node. -+*//***************************************************************************/ -+typedef struct t_FmPcdCcNextKgParams { -+ bool overrideFqid; /**< TRUE if CC override previously decided fqid and vspid, -+ Note - this parameters irrelevant for earlier chips */ -+ uint32_t newFqid; /**< Valid if overrideFqid=TRUE, FQID for enqueuing the frame -+ (otherwise FQID is taken from KeyGen), -+ Note - this parameters irrelevant for earlier chips */ -+#if (DPAA_VERSION >= 11) -+ uint8_t newRelativeStorageProfileId; -+ /**< Valid if overrideFqid=TRUE, Indicates the relative virtual -+ storage profile offset within the port's storage profiles -+ window; Relevant only if the port was configured with VSP. */ -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ t_Handle h_DirectScheme; /**< Direct scheme handle to go to. */ -+} t_FmPcdCcNextKgParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining the next engine after a CC node. -+*//***************************************************************************/ -+typedef struct t_FmPcdCcNextEngineParams { -+ e_FmPcdEngine nextEngine; /**< User has to initialize parameters -+ according to nextEngine definition */ -+ union { -+ t_FmPcdCcNextCcParams ccParams; /**< Parameters in case next engine is CC */ -+ t_FmPcdCcNextPlcrParams plcrParams; /**< Parameters in case next engine is PLCR */ -+ t_FmPcdCcNextEnqueueParams enqueueParams; /**< Parameters in case next engine is BMI */ -+ t_FmPcdCcNextKgParams kgParams; /**< Parameters in case next engine is KG */ -+#if (DPAA_VERSION >= 11) -+ t_FmPcdCcNextFrParams frParams; /**< Parameters in case next engine is FR */ -+#endif /* (DPAA_VERSION >= 11) */ -+ } params; /**< union used for all the next-engine parameters options */ -+ -+ t_Handle h_Manip; /**< Handle to Manipulation object. -+ Relevant if next engine is of type result -+ (e_FM_PCD_PLCR, e_FM_PCD_KG, e_FM_PCD_DONE) */ -+ -+ bool statisticsEn; /**< If TRUE, statistics counters are incremented -+ for each frame passing through this -+ Coarse Classification entry. */ -+} t_FmPcdCcNextEngineParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a single CC key -+*//***************************************************************************/ -+typedef struct t_FmPcdCcKeyParams { -+ uint8_t *p_Key; /**< Relevant only if 'action' = e_FM_PCD_ACTION_EXACT_MATCH; -+ pointer to the key of the size defined in keySize */ -+ uint8_t *p_Mask; /**< Relevant only if 'action' = e_FM_PCD_ACTION_EXACT_MATCH; -+ pointer to the Mask per key of the size defined -+ in keySize. p_Key and p_Mask (if defined) has to be -+ of the same size defined in the keySize; -+ NOTE that if this value is equal for all entries whithin -+ this table, the driver will automatically use global-mask -+ (i.e. one common mask for all entries) instead of private -+ one; that is done in order to spare some memory and for -+ better performance. */ -+ t_FmPcdCcNextEngineParams ccNextEngineParams; -+ /**< parameters for the next for the defined Key in -+ the p_Key */ -+} t_FmPcdCcKeyParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining CC keys parameters -+ The driver supports two methods for CC node allocation: dynamic and static. -+ Static mode was created in order to prevent runtime alloc/free -+ of FMan memory (MURAM), which may cause fragmentation; in this mode, -+ the driver automatically allocates the memory according to -+ 'maxNumOfKeys' parameter. The driver calculates the maximal memory -+ size that may be used for this CC-Node taking into consideration -+ 'maskSupport' and 'statisticsMode' parameters. -+ When 'action' = e_FM_PCD_ACTION_INDEXED_LOOKUP in the extraction -+ parameters of this node, 'maxNumOfKeys' must be equal to 'numOfKeys'. -+ In dynamic mode, 'maxNumOfKeys' must be zero. At initialization, -+ all required structures are allocated according to 'numOfKeys' -+ parameter. During runtime modification, these structures are -+ re-allocated according to the updated number of keys. -+ -+ Please note that 'action' and 'icIndxMask' mentioned in the -+ specific parameter explanations are passed in the extraction -+ parameters of the node (fields of extractCcParams.extractNonHdr). -+*//***************************************************************************/ -+typedef struct t_KeysParams { -+ uint16_t maxNumOfKeys; /**< Maximum number of keys that will (ever) be used in this CC-Node; -+ A value of zero may be used for dynamic memory allocation. */ -+ bool maskSupport; /**< This parameter is relevant only if a node is initialized with -+ 'action' = e_FM_PCD_ACTION_EXACT_MATCH and maxNumOfKeys > 0; -+ Should be TRUE to reserve table memory for key masks, even if -+ initial keys do not contain masks, or if the node was initialized -+ as 'empty' (without keys); this will allow user to add keys with -+ masks at runtime. -+ NOTE that if user want to use only global-masks (i.e. one common mask -+ for all the entries within this table, this parameter should set to 'FALSE'. */ -+ e_FmPcdCcStatsMode statisticsMode; /**< Determines the supported statistics mode for all node's keys. -+ To enable statistics gathering, statistics should be enabled per -+ every key, using 'statisticsEn' in next engine parameters structure -+ of that key; -+ If 'maxNumOfKeys' is set, all required structures will be -+ preallocated for all keys. */ -+#if (DPAA_VERSION >= 11) -+ uint16_t frameLengthRanges[FM_PCD_CC_STATS_MAX_NUM_OF_FLR]; -+ /**< Relevant only for 'RMON' statistics mode -+ (this feature is supported only on B4860 device); -+ Holds a list of programmable thresholds - for each received frame, -+ its length in bytes is examined against these range thresholds and -+ the appropriate counter is incremented by 1 - for example, to belong -+ to range i, the following should hold: -+ range i-1 threshold < frame length <= range i threshold -+ Each range threshold must be larger then its preceding range -+ threshold, and last range threshold must be 0xFFFF. */ -+#endif /* (DPAA_VERSION >= 11) */ -+ uint16_t numOfKeys; /**< Number of initial keys; -+ Note that in case of 'action' = e_FM_PCD_ACTION_INDEXED_LOOKUP, -+ this field should be power-of-2 of the number of bits that are -+ set in 'icIndxMask'. */ -+ uint8_t keySize; /**< Size of key - for extraction of type FULL_FIELD, 'keySize' has -+ to be the standard size of the selected key; For other extraction -+ types, 'keySize' has to be as size of extraction; When 'action' = -+ e_FM_PCD_ACTION_INDEXED_LOOKUP, 'keySize' must be 2. */ -+ t_FmPcdCcKeyParams keyParams[FM_PCD_MAX_NUM_OF_KEYS]; -+ /**< An array with 'numOfKeys' entries, each entry specifies the -+ corresponding key parameters; -+ When 'action' = e_FM_PCD_ACTION_EXACT_MATCH, this value must not -+ exceed 255 (FM_PCD_MAX_NUM_OF_KEYS-1) as the last entry is saved -+ for the 'miss' entry. */ -+ t_FmPcdCcNextEngineParams ccNextEngineParamsForMiss; -+ /**< Parameters for defining the next engine when a key is not matched; -+ Not relevant if action = e_FM_PCD_ACTION_INDEXED_LOOKUP. */ -+} t_KeysParams; -+ -+ -+/**************************************************************************//** -+ @Description Parameters for defining a CC node -+*//***************************************************************************/ -+typedef struct t_FmPcdCcNodeParams { -+ t_FmPcdExtractEntry extractCcParams; /**< Extraction parameters */ -+ t_KeysParams keysParams; /**< Keys definition matching the selected extraction */ -+} t_FmPcdCcNodeParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a hash table -+*//***************************************************************************/ -+typedef struct t_FmPcdHashTableParams { -+ uint16_t maxNumOfKeys; /**< Maximum Number Of Keys that will (ever) be used in this Hash-table */ -+ e_FmPcdCcStatsMode statisticsMode; /**< If not e_FM_PCD_CC_STATS_MODE_NONE, the required structures for the -+ requested statistics mode will be allocated according to maxNumOfKeys. */ -+ uint8_t kgHashShift; /**< KG-Hash-shift as it was configured in the KG-scheme -+ that leads to this hash-table. */ -+ uint16_t hashResMask; /**< Mask that will be used on the hash-result; -+ The number-of-sets for this hash will be calculated -+ as (2^(number of bits set in 'hashResMask')); -+ The 4 lower bits must be cleared. */ -+ uint8_t hashShift; /**< Byte offset from the beginning of the KeyGen hash result to the -+ 2-bytes to be used as hash index. */ -+ uint8_t matchKeySize; /**< Size of the exact match keys held by the hash buckets */ -+ -+ t_FmPcdCcNextEngineParams ccNextEngineParamsForMiss; /**< Parameters for defining the next engine when a key is not matched */ -+ -+} t_FmPcdHashTableParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a CC tree group. -+ -+ This structure defines a CC group in terms of NetEnv units -+ and the action to be taken in each case. The unitIds list must -+ be given in order from low to high indices. -+ -+ t_FmPcdCcNextEngineParams is a list of 2^numOfDistinctionUnits -+ structures where each defines the next action to be taken for -+ each units combination. for example: -+ numOfDistinctionUnits = 2 -+ unitIds = {1,3} -+ p_NextEnginePerEntriesInGrp[0] = t_FmPcdCcNextEngineParams for the case that -+ unit 1 - not found; unit 3 - not found; -+ p_NextEnginePerEntriesInGrp[1] = t_FmPcdCcNextEngineParams for the case that -+ unit 1 - not found; unit 3 - found; -+ p_NextEnginePerEntriesInGrp[2] = t_FmPcdCcNextEngineParams for the case that -+ unit 1 - found; unit 3 - not found; -+ p_NextEnginePerEntriesInGrp[3] = t_FmPcdCcNextEngineParams for the case that -+ unit 1 - found; unit 3 - found; -+*//***************************************************************************/ -+typedef struct t_FmPcdCcGrpParams { -+ uint8_t numOfDistinctionUnits; /**< Up to 4 */ -+ uint8_t unitIds[FM_PCD_MAX_NUM_OF_CC_UNITS]; -+ /**< Indices of the units as defined in -+ FM_PCD_NetEnvCharacteristicsSet() */ -+ t_FmPcdCcNextEngineParams nextEnginePerEntriesInGrp[FM_PCD_MAX_NUM_OF_CC_ENTRIES_IN_GRP]; -+ /**< Maximum entries per group is 16 */ -+} t_FmPcdCcGrpParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining CC tree groups -+*//***************************************************************************/ -+typedef struct t_FmPcdCcTreeParams { -+ t_Handle h_NetEnv; /**< A handle to the Network environment as returned -+ by FM_PCD_NetEnvCharacteristicsSet() */ -+ uint8_t numOfGrps; /**< Number of CC groups within the CC tree */ -+ t_FmPcdCcGrpParams ccGrpParams[FM_PCD_MAX_NUM_OF_CC_GROUPS]; -+ /**< Parameters for each group. */ -+} t_FmPcdCcTreeParams; -+ -+ -+/**************************************************************************//** -+ @Description CC key statistics structure -+*//***************************************************************************/ -+typedef struct t_FmPcdCcKeyStatistics { -+ uint32_t byteCount; /**< This counter reflects byte count of frames that -+ were matched by this key. */ -+ uint32_t frameCount; /**< This counter reflects count of frames that -+ were matched by this key. */ -+#if (DPAA_VERSION >= 11) -+ uint32_t frameLengthRangeCount[FM_PCD_CC_STATS_MAX_NUM_OF_FLR]; -+ /**< These counters reflect how many frames matched -+ this key in 'RMON' statistics mode: -+ Each counter holds the number of frames of a -+ specific frames length range, according to the -+ ranges provided at initialization. */ -+#endif /* (DPAA_VERSION >= 11) */ -+} t_FmPcdCcKeyStatistics; -+ -+/**************************************************************************//** -+ @Description Parameters for defining policer byte rate -+*//***************************************************************************/ -+typedef struct t_FmPcdPlcrByteRateModeParams { -+ e_FmPcdPlcrFrameLengthSelect frameLengthSelection; /**< Frame length selection */ -+ e_FmPcdPlcrRollBackFrameSelect rollBackFrameSelection; /**< relevant option only e_FM_PCD_PLCR_L2_FRM_LEN, -+ e_FM_PCD_PLCR_FULL_FRM_LEN */ -+} t_FmPcdPlcrByteRateModeParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining the policer profile (based on -+ RFC-2698 or RFC-4115 attributes). -+*//***************************************************************************/ -+typedef struct t_FmPcdPlcrNonPassthroughAlgParams { -+ e_FmPcdPlcrRateMode rateMode; /**< Byte mode or Packet mode */ -+ t_FmPcdPlcrByteRateModeParams byteModeParams; /**< Valid for Byte NULL for Packet */ -+ uint32_t committedInfoRate; /**< KBits/Second or Packets/Second */ -+ uint32_t committedBurstSize; /**< Bytes/Packets */ -+ uint32_t peakOrExcessInfoRate; /**< KBits/Second or Packets/Second */ -+ uint32_t peakOrExcessBurstSize; /**< Bytes/Packets */ -+} t_FmPcdPlcrNonPassthroughAlgParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining the next engine after policer -+*//***************************************************************************/ -+typedef union u_FmPcdPlcrNextEngineParams { -+ e_FmPcdDoneAction action; /**< Action - when next engine is BMI (done) */ -+ t_Handle h_Profile; /**< Policer profile handle - used when next engine -+ is Policer, must be a SHARED profile */ -+ t_Handle h_DirectScheme; /**< Direct scheme select - when next engine is KeyGen */ -+} u_FmPcdPlcrNextEngineParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining the policer profile entry -+*//***************************************************************************/ -+typedef struct t_FmPcdPlcrProfileParams { -+ bool modify; /**< TRUE to change an existing profile */ -+ union { -+ struct { -+ e_FmPcdProfileTypeSelection profileType; /**< Type of policer profile */ -+ t_Handle h_FmPort; /**< Relevant for per-port profiles only */ -+ uint16_t relativeProfileId; /**< Profile id - relative to shared group or to port */ -+ } newParams; /**< use it when modify = FALSE */ -+ t_Handle h_Profile; /**< A handle to a profile - use it when modify=TRUE */ -+ } id; -+ e_FmPcdPlcrAlgorithmSelection algSelection; /**< Profile Algorithm PASS_THROUGH, RFC_2698, RFC_4115 */ -+ e_FmPcdPlcrColorMode colorMode; /**< COLOR_BLIND, COLOR_AWARE */ -+ -+ union { -+ e_FmPcdPlcrColor dfltColor; /**< For Color-Blind Pass-Through mode; the policer will re-color -+ any incoming packet with the default value. */ -+ e_FmPcdPlcrColor override; /**< For Color-Aware modes; the profile response to a -+ pre-color value of 2'b11. */ -+ } color; -+ -+ t_FmPcdPlcrNonPassthroughAlgParams nonPassthroughAlgParams; /**< RFC2698 or RFC4115 parameters */ -+ -+ e_FmPcdEngine nextEngineOnGreen; /**< Next engine for green-colored frames */ -+ u_FmPcdPlcrNextEngineParams paramsOnGreen; /**< Next engine parameters for green-colored frames */ -+ -+ e_FmPcdEngine nextEngineOnYellow; /**< Next engine for yellow-colored frames */ -+ u_FmPcdPlcrNextEngineParams paramsOnYellow; /**< Next engine parameters for yellow-colored frames */ -+ -+ e_FmPcdEngine nextEngineOnRed; /**< Next engine for red-colored frames */ -+ u_FmPcdPlcrNextEngineParams paramsOnRed; /**< Next engine parameters for red-colored frames */ -+ -+ bool trapProfileOnFlowA; /**< Obsolete - do not use */ -+ bool trapProfileOnFlowB; /**< Obsolete - do not use */ -+ bool trapProfileOnFlowC; /**< Obsolete - do not use */ -+} t_FmPcdPlcrProfileParams; -+ -+/**************************************************************************//** -+ @Description Parameters for selecting a location for requested manipulation -+*//***************************************************************************/ -+typedef struct t_FmManipHdrInfo { -+ e_NetHeaderType hdr; /**< Header selection */ -+ e_FmPcdHdrIndex hdrIndex; /**< Relevant only for MPLS, VLAN and tunneled IP. Otherwise should be cleared. */ -+ bool byField; /**< TRUE if the location of manipulation is according to some field in the specific header*/ -+ t_FmPcdFields fullField; /**< Relevant only when byField = TRUE: Extract field */ -+} t_FmManipHdrInfo; -+ -+#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+/**************************************************************************//** -+ @Description Parameters for defining an insertion manipulation -+ of type e_FM_PCD_MANIP_INSRT_TO_START_OF_FRAME_TEMPLATE -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrInsrtByTemplateParams { -+ uint8_t size; /**< Size of insert template to the start of the frame. */ -+ uint8_t hdrTemplate[FM_PCD_MAX_MANIP_INSRT_TEMPLATE_SIZE]; -+ /**< Array of the insertion template. */ -+ -+ bool modifyOuterIp; /**< TRUE if user want to modify some fields in outer IP. */ -+ struct { -+ uint16_t ipOuterOffset; /**< Offset of outer IP in the insert template, relevant if modifyOuterIp = TRUE.*/ -+ uint16_t dscpEcn; /**< value of dscpEcn in IP outer, relevant if modifyOuterIp = TRUE. -+ in IPV4 dscpEcn only byte - it has to be adjusted to the right*/ -+ bool udpPresent; /**< TRUE if UDP is present in the insert template, relevant if modifyOuterIp = TRUE.*/ -+ uint8_t udpOffset; /**< Offset in the insert template of UDP, relevant if modifyOuterIp = TRUE and udpPresent=TRUE.*/ -+ uint8_t ipIdentGenId; /**< Used by FMan-CTRL to calculate IP-identification field,relevant if modifyOuterIp = TRUE.*/ -+ bool recalculateLength; /**< TRUE if recalculate length has to be performed due to the engines in the path which can change the frame later, relevant if modifyOuterIp = TRUE.*/ -+ struct { -+ uint8_t blockSize; /**< The CAAM block-size; Used by FMan-CTRL to calculate the IP Total Length field.*/ -+ uint8_t extraBytesAddedAlignedToBlockSize; /**< Used by FMan-CTRL to calculate the IP Total Length field and UDP length*/ -+ uint8_t extraBytesAddedNotAlignedToBlockSize;/**< Used by FMan-CTRL to calculate the IP Total Length field and UDP length.*/ -+ } recalculateLengthParams; /**< Recalculate length parameters - relevant if modifyOuterIp = TRUE and recalculateLength = TRUE */ -+ } modifyOuterIpParams; /**< Outer IP modification parameters - ignored if modifyOuterIp is FALSE */ -+ -+ bool modifyOuterVlan; /**< TRUE if user wants to modify VPri field in the outer VLAN header*/ -+ struct { -+ uint8_t vpri; /**< Value of VPri, relevant if modifyOuterVlan = TRUE -+ VPri only 3 bits, it has to be adjusted to the right*/ -+ } modifyOuterVlanParams; -+} t_FmPcdManipHdrInsrtByTemplateParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining CAPWAP fragmentation -+*//***************************************************************************/ -+typedef struct t_CapwapFragmentationParams { -+ uint16_t sizeForFragmentation; /**< if length of the frame is greater than this value, CAPWAP fragmentation will be executed.*/ -+ bool headerOptionsCompr; /**< TRUE - first fragment include the CAPWAP header options field, -+ and all other fragments exclude the CAPWAP options field, -+ FALSE - all fragments include CAPWAP header options field. */ -+} t_CapwapFragmentationParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining CAPWAP reassembly -+*//***************************************************************************/ -+typedef struct t_CapwapReassemblyParams { -+ uint16_t maxNumFramesInProcess; /**< Number of frames which can be reassembled concurrently; must be power of 2. -+ In case numOfFramesPerHashEntry == e_FM_PCD_MANIP_FOUR_WAYS_HASH, -+ maxNumFramesInProcess has to be in the range of 4 - 512, -+ In case numOfFramesPerHashEntry == e_FM_PCD_MANIP_EIGHT_WAYS_HASH, -+ maxNumFramesInProcess has to be in the range of 8 - 2048 */ -+ bool haltOnDuplicationFrag; /**< If TRUE, reassembly process will be halted due to duplicated fragment, -+ and all processed fragments will be enqueued with error indication; -+ If FALSE, only duplicated fragments will be enqueued with error indication. */ -+ -+ e_FmPcdManipReassemTimeOutMode timeOutMode; /**< Expiration delay initialized by the reassembly process */ -+ uint32_t fqidForTimeOutFrames; /**< FQID in which time out frames will enqueue during Time Out Process */ -+ uint32_t timeoutRoutineRequestTime; -+ /**< Represents the time interval in microseconds between consecutive -+ timeout routine requests It has to be power of 2. */ -+ uint32_t timeoutThresholdForReassmProcess; -+ /**< Time interval (microseconds) for marking frames in process as too old; -+ Frames in process are those for which at least one fragment was received -+ but not all fragments. */ -+ -+ e_FmPcdManipReassemWaysNumber numOfFramesPerHashEntry;/**< Number of frames per hash entry (needed for the reassembly process) */ -+} t_CapwapReassemblyParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining fragmentation/reassembly manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipFragOrReasmParams { -+ bool frag; /**< TRUE if using the structure for fragmentation, -+ otherwise this structure is used for reassembly */ -+ uint8_t sgBpid; /**< Scatter/Gather buffer pool id; -+ Same LIODN number is used for these buffers as for -+ the received frames buffers, so buffers of this pool -+ need to be allocated in the same memory area as the -+ received buffers. If the received buffers arrive -+ from different sources, the Scatter/Gather BP id -+ should be mutual to all these sources. */ -+ e_NetHeaderType hdr; /**< Header selection */ -+ union { -+ t_CapwapFragmentationParams capwapFragParams; /**< Structure for CAPWAP fragmentation, -+ relevant if 'frag' = TRUE, 'hdr' = HEADER_TYPE_CAPWAP */ -+ t_CapwapReassemblyParams capwapReasmParams; /**< Structure for CAPWAP reassembly, -+ relevant if 'frag' = FALSE, 'hdr' = HEADER_TYPE_CAPWAP */ -+ } u; -+} t_FmPcdManipFragOrReasmParams; -+#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+ -+ -+/**************************************************************************//** -+ @Description Parameters for defining header removal by header type -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrRmvByHdrParams { -+ e_FmPcdManipHdrRmvByHdrType type; /**< Selection of header removal location */ -+ union { -+#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+ struct { -+ bool include; /**< If FALSE, remove until the specified header (not including the header); -+ If TRUE, remove also the specified header. */ -+ t_FmManipHdrInfo hdrInfo; -+ } fromStartByHdr; /**< Relevant when type = e_FM_PCD_MANIP_RMV_BY_HDR_FROM_START */ -+#endif /* (DPAA_VERSION >= 11) || ... */ -+#if (DPAA_VERSION >= 11) -+ t_FmManipHdrInfo hdrInfo; /**< Relevant when type = e_FM_PCD_MANIP_RMV_BY_HDR_FROM_START */ -+#endif /* (DPAA_VERSION >= 11) */ -+ e_FmPcdManipHdrRmvSpecificL2 specificL2; /**< Relevant when type = e_FM_PCD_MANIP_BY_HDR_SPECIFIC_L2; -+ Defines which L2 headers to remove. */ -+ } u; -+} t_FmPcdManipHdrRmvByHdrParams; -+ -+/**************************************************************************//** -+ @Description Parameters for configuring IP fragmentation manipulation -+ -+ Restrictions: -+ - IP Fragmentation output fragments must not be forwarded to application directly. -+ - Maximum number of fragments per frame is 16. -+ - Fragmentation of IP fragments is not supported. -+ - IPv4 packets containing header Option fields are fragmented by copying all option -+ fields to each fragment, regardless of the copy bit value. -+ - Transmit confirmation is not supported. -+ - Fragmentation after SEC can't handle S/G frames. -+ - Fragmentation nodes must be set as the last PCD action (i.e. the -+ corresponding CC node key must have next engine set to e_FM_PCD_DONE). -+ - Only BMan buffers shall be used for frames to be fragmented. -+ - IPF does not support VSP. Therefore, on the same port where we have IPF -+ we cannot support VSP. -+ - NOTE: The following comment is relevant only for FMAN v3 devices: IPF -+ does not support VSP. Therefore, on the same port where we have IPF we -+ cannot support VSP. -+*//***************************************************************************/ -+typedef struct t_FmPcdManipFragIpParams { -+ uint16_t sizeForFragmentation; /**< If length of the frame is greater than this value, -+ IP fragmentation will be executed.*/ -+#if (DPAA_VERSION == 10) -+ uint8_t scratchBpid; /**< Absolute buffer pool id according to BM configuration.*/ -+#endif /* (DPAA_VERSION == 10) */ -+ bool sgBpidEn; /**< Enable a dedicated buffer pool id for the Scatter/Gather buffer allocation; -+ If disabled, the Scatter/Gather buffer will be allocated from the same pool as the -+ received frame's buffer. */ -+ uint8_t sgBpid; /**< Scatter/Gather buffer pool id; -+ This parameters is relevant when 'sgBpidEn=TRUE'; -+ Same LIODN number is used for these buffers as for the received frames buffers, so buffers -+ of this pool need to be allocated in the same memory area as the received buffers. -+ If the received buffers arrive from different sources, the Scatter/Gather BP id should be -+ mutual to all these sources. */ -+ e_FmPcdManipDontFragAction dontFragAction; /**< Don't Fragment Action - If an IP packet is larger -+ than MTU and its DF bit is set, then this field will -+ determine the action to be taken.*/ -+} t_FmPcdManipFragIpParams; -+ -+/**************************************************************************//** -+ @Description Parameters for configuring IP reassembly manipulation. -+ -+ This is a common structure for both IPv4 and IPv6 reassembly -+ manipulation. For reassembly of both IPv4 and IPv6, make sure to -+ set the 'hdr' field in t_FmPcdManipReassemParams to HEADER_TYPE_IPv6. -+ -+ Restrictions: -+ - Application must define at least one scheme to catch the reassembled frames. -+ - Maximum number of fragments per frame is 16. -+ - Reassembly of IPv4 fragments containing Option fields is supported. -+ -+*//***************************************************************************/ -+typedef struct t_FmPcdManipReassemIpParams { -+ uint8_t relativeSchemeId[2]; /**< Partition relative scheme id: -+ relativeSchemeId[0] - Relative scheme ID for IPV4 Reassembly manipulation; -+ relativeSchemeId[1] - Relative scheme ID for IPV6 Reassembly manipulation; -+ NOTE: The following comment is relevant only for FMAN v2 devices: -+ Relative scheme ID for IPv4/IPv6 Reassembly manipulation must be smaller than -+ the user schemes id to ensure that the reassembly schemes will be first match; -+ Rest schemes, if defined, should have higher relative scheme ID. */ -+#if (DPAA_VERSION >= 11) -+ uint32_t nonConsistentSpFqid; /**< In case that other fragments of the frame corresponds to different storage -+ profile than the opening fragment (Non-Consistent-SP state) -+ then one of two possible scenarios occurs: -+ if 'nonConsistentSpFqid != 0', the reassembled frame will be enqueued to -+ this fqid, otherwise a 'Non Consistent SP' bit will be set in the FD[status].*/ -+#else -+ uint8_t sgBpid; /**< Buffer pool id for the S/G frame created by the reassembly process */ -+#endif /* (DPAA_VERSION >= 11) */ -+ uint8_t dataMemId; /**< Memory partition ID for the IPR's external tables structure */ -+ uint16_t dataLiodnOffset; /**< LIODN offset for access the IPR's external tables structure. */ -+ uint16_t minFragSize[2]; /**< Minimum fragment size: -+ minFragSize[0] - for ipv4, minFragSize[1] - for ipv6 */ -+ e_FmPcdManipReassemWaysNumber numOfFramesPerHashEntry[2]; -+ /**< Number of frames per hash entry needed for reassembly process: -+ numOfFramesPerHashEntry[0] - for ipv4 (max value is e_FM_PCD_MANIP_EIGHT_WAYS_HASH); -+ numOfFramesPerHashEntry[1] - for ipv6 (max value is e_FM_PCD_MANIP_SIX_WAYS_HASH). */ -+ uint16_t maxNumFramesInProcess; /**< Number of frames which can be processed by Reassembly in the same time; -+ Must be power of 2; -+ In the case numOfFramesPerHashEntry == e_FM_PCD_MANIP_FOUR_WAYS_HASH, -+ maxNumFramesInProcess has to be in the range of 4 - 512; -+ In the case numOfFramesPerHashEntry == e_FM_PCD_MANIP_EIGHT_WAYS_HASH, -+ maxNumFramesInProcess has to be in the range of 8 - 2048. */ -+ e_FmPcdManipReassemTimeOutMode timeOutMode; /**< Expiration delay initialized by Reassembly process */ -+ uint32_t fqidForTimeOutFrames; /**< FQID in which time out frames will enqueue during Time Out Process; -+ Recommended value for this field is 0; in this way timed-out frames will be discarded */ -+ uint32_t timeoutThresholdForReassmProcess; -+ /**< Represents the time interval in microseconds which defines -+ if opened frame (at least one fragment was processed but not all the fragments)is found as too old*/ -+} t_FmPcdManipReassemIpParams; -+ -+/**************************************************************************//** -+ @Description structure for defining IPSEC manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipSpecialOffloadIPSecParams { -+ bool decryption; /**< TRUE if being used in decryption direction; -+ FALSE if being used in encryption direction. */ -+ bool ecnCopy; /**< TRUE to copy the ECN bits from inner/outer to outer/inner -+ (direction depends on the 'decryption' field). */ -+ bool dscpCopy; /**< TRUE to copy the DSCP bits from inner/outer to outer/inner -+ (direction depends on the 'decryption' field). */ -+ bool variableIpHdrLen; /**< TRUE for supporting variable IP header length in decryption. */ -+ bool variableIpVersion; /**< TRUE for supporting both IP version on the same SA in encryption */ -+ uint8_t outerIPHdrLen; /**< if 'variableIpVersion == TRUE' then this field must be set to non-zero value; -+ It is specifies the length of the outer IP header that was configured in the -+ corresponding SA. */ -+ uint16_t arwSize; /**< if <> '0' then will perform ARW check for this SA; -+ The value must be a multiplication of 16 */ -+ uintptr_t arwAddr; /**< if arwSize <> '0' then this field must be set to non-zero value; -+ MUST be allocated from FMAN's MURAM that the post-sec op-port belongs to; -+ Must be 4B aligned. Required MURAM size is 'NEXT_POWER_OF_2(arwSize+32))/8+4' Bytes */ -+} t_FmPcdManipSpecialOffloadIPSecParams; -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description Parameters for configuring CAPWAP fragmentation manipulation -+ -+ Restrictions: -+ - Maximum number of fragments per frame is 16. -+ - Transmit confirmation is not supported. -+ - Fragmentation nodes must be set as the last PCD action (i.e. the -+ corresponding CC node key must have next engine set to e_FM_PCD_DONE). -+ - Only BMan buffers shall be used for frames to be fragmented. -+ - NOTE: The following comment is relevant only for FMAN v3 devices: IPF -+ does not support VSP. Therefore, on the same port where we have IPF we -+ cannot support VSP. -+*//***************************************************************************/ -+typedef struct t_FmPcdManipFragCapwapParams { -+ uint16_t sizeForFragmentation; /**< If length of the frame is greater than this value, -+ CAPWAP fragmentation will be executed.*/ -+ bool sgBpidEn; /**< Enable a dedicated buffer pool id for the Scatter/Gather buffer allocation; -+ If disabled, the Scatter/Gather buffer will be allocated from the same pool as the -+ received frame's buffer. */ -+ uint8_t sgBpid; /**< Scatter/Gather buffer pool id; -+ This parameters is relevant when 'sgBpidEn=TRUE'; -+ Same LIODN number is used for these buffers as for the received frames buffers, so buffers -+ of this pool need to be allocated in the same memory area as the received buffers. -+ If the received buffers arrive from different sources, the Scatter/Gather BP id should be -+ mutual to all these sources. */ -+ bool compressModeEn; /**< CAPWAP Header Options Compress Enable mode; -+ When this mode is enabled then only the first fragment include the CAPWAP header options -+ field (if user provides it in the input frame) and all other fragments exclude the CAPWAP -+ options field (CAPWAP header is updated accordingly).*/ -+} t_FmPcdManipFragCapwapParams; -+ -+/**************************************************************************//** -+ @Description Parameters for configuring CAPWAP reassembly manipulation. -+ -+ Restrictions: -+ - Application must define one scheme to catch the reassembled frames. -+ - Maximum number of fragments per frame is 16. -+ -+*//***************************************************************************/ -+typedef struct t_FmPcdManipReassemCapwapParams { -+ uint8_t relativeSchemeId; /**< Partition relative scheme id; -+ NOTE: this id must be smaller than the user schemes id to ensure that the reassembly scheme will be first match; -+ Rest schemes, if defined, should have higher relative scheme ID. */ -+ uint8_t dataMemId; /**< Memory partition ID for the IPR's external tables structure */ -+ uint16_t dataLiodnOffset; /**< LIODN offset for access the IPR's external tables structure. */ -+ uint16_t maxReassembledFrameLength;/**< The maximum CAPWAP reassembled frame length in bytes; -+ If maxReassembledFrameLength == 0, any successful reassembled frame length is -+ considered as a valid length; -+ if maxReassembledFrameLength > 0, a successful reassembled frame which its length -+ exceeds this value is considered as an error frame (FD status[CRE] bit is set). */ -+ e_FmPcdManipReassemWaysNumber numOfFramesPerHashEntry; -+ /**< Number of frames per hash entry needed for reassembly process */ -+ uint16_t maxNumFramesInProcess; /**< Number of frames which can be processed by reassembly in the same time; -+ Must be power of 2; -+ In the case numOfFramesPerHashEntry == e_FM_PCD_MANIP_FOUR_WAYS_HASH, -+ maxNumFramesInProcess has to be in the range of 4 - 512; -+ In the case numOfFramesPerHashEntry == e_FM_PCD_MANIP_EIGHT_WAYS_HASH, -+ maxNumFramesInProcess has to be in the range of 8 - 2048. */ -+ e_FmPcdManipReassemTimeOutMode timeOutMode; /**< Expiration delay initialized by Reassembly process */ -+ uint32_t fqidForTimeOutFrames; /**< FQID in which time out frames will enqueue during Time Out Process; -+ Recommended value for this field is 0; in this way timed-out frames will be discarded */ -+ uint32_t timeoutThresholdForReassmProcess; -+ /**< Represents the time interval in microseconds which defines -+ if opened frame (at least one fragment was processed but not all the fragments)is found as too old*/ -+} t_FmPcdManipReassemCapwapParams; -+ -+/**************************************************************************//** -+ @Description structure for defining CAPWAP manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipSpecialOffloadCapwapParams { -+ bool dtls; /**< TRUE if continue to SEC DTLS encryption */ -+ e_FmPcdManipHdrQosSrc qosSrc; /**< TODO */ -+} t_FmPcdManipSpecialOffloadCapwapParams; -+ -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ -+/**************************************************************************//** -+ @Description Parameters for defining special offload manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipSpecialOffloadParams { -+ e_FmPcdManipSpecialOffloadType type; /**< Type of special offload manipulation */ -+ union -+ { -+ t_FmPcdManipSpecialOffloadIPSecParams ipsec; /**< Parameters for IPSec; Relevant when -+ type = e_FM_PCD_MANIP_SPECIAL_OFFLOAD_IPSEC */ -+#if (DPAA_VERSION >= 11) -+ t_FmPcdManipSpecialOffloadCapwapParams capwap; /**< Parameters for CAPWAP; Relevant when -+ type = e_FM_PCD_MANIP_SPECIAL_OFFLOAD_CAPWAP */ -+#endif /* (DPAA_VERSION >= 11) */ -+ } u; -+} t_FmPcdManipSpecialOffloadParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining insertion manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrInsrt { -+ uint8_t size; /**< size of inserted section */ -+ uint8_t *p_Data; /**< data to be inserted */ -+} t_FmPcdManipHdrInsrt; -+ -+ -+/**************************************************************************//** -+ @Description Parameters for defining generic removal manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrRmvGenericParams { -+ uint8_t offset; /**< Offset from beginning of header to the start -+ location of the removal */ -+ uint8_t size; /**< Size of removed section */ -+} t_FmPcdManipHdrRmvGenericParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining generic insertion manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrInsrtGenericParams { -+ uint8_t offset; /**< Offset from beginning of header to the start -+ location of the insertion */ -+ uint8_t size; /**< Size of inserted section */ -+ bool replace; /**< TRUE to override (replace) existing data at -+ 'offset', FALSE to insert */ -+ uint8_t *p_Data; /**< Pointer to data to be inserted */ -+} t_FmPcdManipHdrInsrtGenericParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation VLAN DSCP To Vpri translation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrFieldUpdateVlanDscpToVpri { -+ uint8_t dscpToVpriTable[FM_PCD_MANIP_DSCP_TO_VLAN_TRANS]; -+ /**< A table of VPri values for each DSCP value; -+ The index is the DSCP value (0-0x3F) and the -+ value is the corresponding VPRI (0-15). */ -+ uint8_t vpriDefVal; /**< 0-7, Relevant only if if updateType = -+ e_FM_PCD_MANIP_HDR_FIELD_UPDATE_DSCP_TO_VLAN, -+ this field is the Q Tag default value if the -+ IP header is not found. */ -+} t_FmPcdManipHdrFieldUpdateVlanDscpToVpri; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation VLAN fields updates -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrFieldUpdateVlan { -+ e_FmPcdManipHdrFieldUpdateVlan updateType; /**< Selects VLAN update type */ -+ union { -+ uint8_t vpri; /**< 0-7, Relevant only if If updateType = -+ e_FM_PCD_MANIP_HDR_FIELD_UPDATE_VLAN_PRI, this -+ is the new VLAN pri. */ -+ t_FmPcdManipHdrFieldUpdateVlanDscpToVpri dscpToVpri; /**< Parameters structure, Relevant only if updateType -+ = e_FM_PCD_MANIP_HDR_FIELD_UPDATE_DSCP_TO_VLAN. */ -+ } u; -+} t_FmPcdManipHdrFieldUpdateVlan; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation IPV4 fields updates -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrFieldUpdateIpv4 { -+ ipv4HdrManipUpdateFlags_t validUpdates; /**< ORed flag, selecting the required updates */ -+ uint8_t tos; /**< 8 bit New TOS; Relevant if validUpdates contains -+ HDR_MANIP_IPV4_TOS */ -+ uint16_t id; /**< 16 bit New IP ID; Relevant only if validUpdates -+ contains HDR_MANIP_IPV4_ID */ -+ uint32_t src; /**< 32 bit New IP SRC; Relevant only if validUpdates -+ contains HDR_MANIP_IPV4_SRC */ -+ uint32_t dst; /**< 32 bit New IP DST; Relevant only if validUpdates -+ contains HDR_MANIP_IPV4_DST */ -+} t_FmPcdManipHdrFieldUpdateIpv4; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation IPV6 fields updates -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrFieldUpdateIpv6 { -+ ipv6HdrManipUpdateFlags_t validUpdates; /**< ORed flag, selecting the required updates */ -+ uint8_t trafficClass; /**< 8 bit New Traffic Class; Relevant if validUpdates contains -+ HDR_MANIP_IPV6_TC */ -+ uint8_t src[NET_HEADER_FIELD_IPv6_ADDR_SIZE]; -+ /**< 16 byte new IP SRC; Relevant only if validUpdates -+ contains HDR_MANIP_IPV6_SRC */ -+ uint8_t dst[NET_HEADER_FIELD_IPv6_ADDR_SIZE]; -+ /**< 16 byte new IP DST; Relevant only if validUpdates -+ contains HDR_MANIP_IPV6_DST */ -+} t_FmPcdManipHdrFieldUpdateIpv6; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation TCP/UDP fields updates -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrFieldUpdateTcpUdp { -+ tcpUdpHdrManipUpdateFlags_t validUpdates; /**< ORed flag, selecting the required updates */ -+ uint16_t src; /**< 16 bit New TCP/UDP SRC; Relevant only if validUpdates -+ contains HDR_MANIP_TCP_UDP_SRC */ -+ uint16_t dst; /**< 16 bit New TCP/UDP DST; Relevant only if validUpdates -+ contains HDR_MANIP_TCP_UDP_DST */ -+} t_FmPcdManipHdrFieldUpdateTcpUdp; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation fields updates -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrFieldUpdateParams { -+ e_FmPcdManipHdrFieldUpdateType type; /**< Type of header field update manipulation */ -+ union { -+ t_FmPcdManipHdrFieldUpdateVlan vlan; /**< Parameters for VLAN update. Relevant when -+ type = e_FM_PCD_MANIP_HDR_FIELD_UPDATE_VLAN */ -+ t_FmPcdManipHdrFieldUpdateIpv4 ipv4; /**< Parameters for IPv4 update. Relevant when -+ type = e_FM_PCD_MANIP_HDR_FIELD_UPDATE_IPV4 */ -+ t_FmPcdManipHdrFieldUpdateIpv6 ipv6; /**< Parameters for IPv6 update. Relevant when -+ type = e_FM_PCD_MANIP_HDR_FIELD_UPDATE_IPV6 */ -+ t_FmPcdManipHdrFieldUpdateTcpUdp tcpUdp; /**< Parameters for TCP/UDP update. Relevant when -+ type = e_FM_PCD_MANIP_HDR_FIELD_UPDATE_TCP_UDP */ -+ } u; -+} t_FmPcdManipHdrFieldUpdateParams; -+ -+ -+ -+/**************************************************************************//** -+ @Description Parameters for defining custom header manipulation for generic field replacement -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrCustomGenFieldReplace { -+ uint8_t srcOffset; /**< Location of new data - Offset from -+ Parse Result (>= 16, srcOffset+size <= 32, ) */ -+ uint8_t dstOffset; /**< Location of data to be overwritten - Offset from -+ start of frame (dstOffset + size <= 256). */ -+ uint8_t size; /**< The number of bytes (<=16) to be replaced */ -+ uint8_t mask; /**< Optional 1 byte mask. Set to select bits for -+ replacement (1 - bit will be replaced); -+ Clear to use field as is. */ -+ uint8_t maskOffset; /**< Relevant if mask != 0; -+ Mask offset within the replaces "size" */ -+} t_FmPcdManipHdrCustomGenFieldReplace; -+ -+/**************************************************************************//** -+ @Description Parameters for defining custom header manipulation for IP replacement -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrCustomIpHdrReplace { -+ e_FmPcdManipHdrCustomIpReplace replaceType; /**< Selects replace update type */ -+ bool decTtlHl; /**< Decrement TTL (IPV4) or Hop limit (IPV6) by 1 */ -+ bool updateIpv4Id; /**< Relevant when replaceType = -+ e_FM_PCD_MANIP_HDR_CUSTOM_REPLACE_IPV6_BY_IPV4 */ -+ uint16_t id; /**< 16 bit New IP ID; Relevant only if -+ updateIpv4Id = TRUE */ -+ uint8_t hdrSize; /**< The size of the new IP header */ -+ uint8_t hdr[FM_PCD_MANIP_MAX_HDR_SIZE]; -+ /**< The new IP header */ -+} t_FmPcdManipHdrCustomIpHdrReplace; -+ -+/**************************************************************************//** -+ @Description Parameters for defining custom header manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrCustomParams { -+ e_FmPcdManipHdrCustomType type; /**< Type of header field update manipulation */ -+ union { -+ t_FmPcdManipHdrCustomIpHdrReplace ipHdrReplace; /**< Parameters IP header replacement */ -+ t_FmPcdManipHdrCustomGenFieldReplace genFieldReplace; /**< Parameters IP header replacement */ -+ } u; -+} t_FmPcdManipHdrCustomParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining specific L2 insertion manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrInsrtSpecificL2Params { -+ e_FmPcdManipHdrInsrtSpecificL2 specificL2; /**< Selects which L2 headers to insert */ -+ bool update; /**< TRUE to update MPLS header */ -+ uint8_t size; /**< size of inserted section */ -+ uint8_t *p_Data; /**< data to be inserted */ -+} t_FmPcdManipHdrInsrtSpecificL2Params; -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description Parameters for defining IP insertion manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrInsrtIpParams { -+ bool calcL4Checksum; /**< Calculate L4 checksum. */ -+ e_FmPcdManipHdrQosMappingMode mappingMode; /**< TODO */ -+ uint8_t lastPidOffset; /**< the offset of the last Protocol within -+ the inserted header */ -+ uint16_t id; /**< 16 bit New IP ID */ -+ bool dontFragOverwrite; -+ /**< IPv4 only. DF is overwritten with the hash-result next-to-last byte. -+ * This byte is configured to be overwritten when RPD is set. */ -+ uint8_t lastDstOffset; -+ /**< IPv6 only. if routing extension exist, user should set the offset of the destination address -+ * in order to calculate UDP checksum pseudo header; -+ * Otherwise set it to '0'. */ -+ t_FmPcdManipHdrInsrt insrt; /**< size and data to be inserted. */ -+} t_FmPcdManipHdrInsrtIpParams; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Description Parameters for defining header insertion manipulation by header type -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrInsrtByHdrParams { -+ e_FmPcdManipHdrInsrtByHdrType type; /**< Selects manipulation type */ -+ union { -+ -+ t_FmPcdManipHdrInsrtSpecificL2Params specificL2Params; -+ /**< Used when type = e_FM_PCD_MANIP_INSRT_BY_HDR_SPECIFIC_L2: -+ Selects which L2 headers to insert */ -+#if (DPAA_VERSION >= 11) -+ t_FmPcdManipHdrInsrtIpParams ipParams; /**< Used when type = e_FM_PCD_MANIP_INSRT_BY_HDR_IP */ -+ t_FmPcdManipHdrInsrt insrt; /**< Used when type is one of e_FM_PCD_MANIP_INSRT_BY_HDR_UDP, -+ e_FM_PCD_MANIP_INSRT_BY_HDR_UDP_LITE, or -+ e_FM_PCD_MANIP_INSRT_BY_HDR_CAPWAP */ -+#endif /* (DPAA_VERSION >= 11) */ -+ } u; -+} t_FmPcdManipHdrInsrtByHdrParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header insertion manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrInsrtParams { -+ e_FmPcdManipHdrInsrtType type; /**< Type of insertion manipulation */ -+ union { -+ t_FmPcdManipHdrInsrtByHdrParams byHdr; /**< Parameters for defining header insertion manipulation by header type, -+ relevant if 'type' = e_FM_PCD_MANIP_INSRT_BY_HDR */ -+ t_FmPcdManipHdrInsrtGenericParams generic; /**< Parameters for defining generic header insertion manipulation, -+ relevant if 'type' = e_FM_PCD_MANIP_INSRT_GENERIC */ -+#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+ t_FmPcdManipHdrInsrtByTemplateParams byTemplate; /**< Parameters for defining header insertion manipulation by template, -+ relevant if 'type' = e_FM_PCD_MANIP_INSRT_BY_TEMPLATE */ -+#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+ } u; -+} t_FmPcdManipHdrInsrtParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header removal manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrRmvParams { -+ e_FmPcdManipHdrRmvType type; /**< Type of header removal manipulation */ -+ union { -+ t_FmPcdManipHdrRmvByHdrParams byHdr; /**< Parameters for defining header removal manipulation by header type, -+ relevant if type = e_FM_PCD_MANIP_RMV_BY_HDR */ -+ t_FmPcdManipHdrRmvGenericParams generic; /**< Parameters for defining generic header removal manipulation, -+ relevant if type = e_FM_PCD_MANIP_RMV_GENERIC */ -+ } u; -+} t_FmPcdManipHdrRmvParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation node -+*//***************************************************************************/ -+typedef struct t_FmPcdManipHdrParams { -+ bool rmv; /**< TRUE, to define removal manipulation */ -+ t_FmPcdManipHdrRmvParams rmvParams; /**< Parameters for removal manipulation, relevant if 'rmv' = TRUE */ -+ -+ bool insrt; /**< TRUE, to define insertion manipulation */ -+ t_FmPcdManipHdrInsrtParams insrtParams; /**< Parameters for insertion manipulation, relevant if 'insrt' = TRUE */ -+ -+ bool fieldUpdate; /**< TRUE, to define field update manipulation */ -+ t_FmPcdManipHdrFieldUpdateParams fieldUpdateParams; /**< Parameters for field update manipulation, relevant if 'fieldUpdate' = TRUE */ -+ -+ bool custom; /**< TRUE, to define custom manipulation */ -+ t_FmPcdManipHdrCustomParams customParams; /**< Parameters for custom manipulation, relevant if 'custom' = TRUE */ -+ -+ bool dontParseAfterManip;/**< TRUE to de-activate the parser after the manipulation defined in this node. -+ Restrictions: -+ 1. MUST be set if the next engine after the CC is not another CC node -+ (but rather Policer or Keygen), and this is the last (no h_NextManip) in a chain -+ of manipulation nodes. This includes single nodes (i.e. no h_NextManip and -+ also never pointed as h_NextManip of other manipulation nodes) -+ 2. MUST be set if the next engine after the CC is another CC node, and -+ this is NOT the last manipulation node (i.e. it has h_NextManip).*/ -+} t_FmPcdManipHdrParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining fragmentation manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipFragParams { -+ e_NetHeaderType hdr; /**< Header selection */ -+ union { -+#if (DPAA_VERSION >= 11) -+ t_FmPcdManipFragCapwapParams capwapFrag; /**< Parameters for defining CAPWAP fragmentation, -+ relevant if 'hdr' = HEADER_TYPE_CAPWAP */ -+#endif /* (DPAA_VERSION >= 11) */ -+ t_FmPcdManipFragIpParams ipFrag; /**< Parameters for defining IP fragmentation, -+ relevant if 'hdr' = HEADER_TYPE_Ipv4 or HEADER_TYPE_Ipv6 */ -+ } u; -+} t_FmPcdManipFragParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining reassembly manipulation -+*//***************************************************************************/ -+typedef struct t_FmPcdManipReassemParams { -+ e_NetHeaderType hdr; /**< Header selection */ -+ union { -+#if (DPAA_VERSION >= 11) -+ t_FmPcdManipReassemCapwapParams capwapReassem; /**< Parameters for defining CAPWAP reassembly, -+ relevant if 'hdr' = HEADER_TYPE_CAPWAP */ -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ t_FmPcdManipReassemIpParams ipReassem; /**< Parameters for defining IP reassembly, -+ relevant if 'hdr' = HEADER_TYPE_Ipv4 or HEADER_TYPE_Ipv6 */ -+ } u; -+} t_FmPcdManipReassemParams; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a manipulation node -+*//***************************************************************************/ -+typedef struct t_FmPcdManipParams { -+ e_FmPcdManipType type; /**< Selects type of manipulation node */ -+ union{ -+ t_FmPcdManipHdrParams hdr; /**< Parameters for defining header manipulation node */ -+ t_FmPcdManipReassemParams reassem; /**< Parameters for defining reassembly manipulation node */ -+ t_FmPcdManipFragParams frag; /**< Parameters for defining fragmentation manipulation node */ -+ t_FmPcdManipSpecialOffloadParams specialOffload; /**< Parameters for defining special offload manipulation node */ -+ } u; -+ -+ t_Handle h_NextManip; /**< Supported for Header Manipulation only; -+ Handle to another (previously defined) manipulation node; -+ Allows concatenation of manipulation actions; -+ This parameter is optional and may be NULL. */ -+#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+ bool fragOrReasm; /**< TRUE, if defined fragmentation/reassembly manipulation */ -+ t_FmPcdManipFragOrReasmParams fragOrReasmParams; /**< Parameters for fragmentation/reassembly manipulation, -+ relevant if fragOrReasm = TRUE */ -+#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+} t_FmPcdManipParams; -+ -+/**************************************************************************//** -+ @Description Structure for retrieving IP reassembly statistics -+*//***************************************************************************/ -+typedef struct t_FmPcdManipReassemIpStats { -+ /* common counters for both IPv4 and IPv6 */ -+ uint32_t timeout; /**< Counts the number of timeout occurrences */ -+ uint32_t rfdPoolBusy; /**< Counts the number of failed attempts to allocate -+ a Reassembly Frame Descriptor */ -+ uint32_t internalBufferBusy; /**< Counts the number of times an internal buffer busy occurred */ -+ uint32_t externalBufferBusy; /**< Counts the number of times external buffer busy occurred */ -+ uint32_t sgFragments; /**< Counts the number of Scatter/Gather fragments */ -+ uint32_t dmaSemaphoreDepletion; /**< Counts the number of failed attempts to allocate a DMA semaphore */ -+#if (DPAA_VERSION >= 11) -+ uint32_t nonConsistentSp; /**< Counts the number of Non Consistent Storage Profile events for -+ successfully reassembled frames */ -+#endif /* (DPAA_VERSION >= 11) */ -+ struct { -+ uint32_t successfullyReassembled; /**< Counts the number of successfully reassembled frames */ -+ uint32_t validFragments; /**< Counts the total number of valid fragments that -+ have been processed for all frames */ -+ uint32_t processedFragments; /**< Counts the number of processed fragments -+ (valid and error fragments) for all frames */ -+ uint32_t malformedFragments; /**< Counts the number of malformed fragments processed for all frames */ -+ uint32_t discardedFragments; /**< Counts the number of fragments discarded by the reassembly process */ -+ uint32_t autoLearnBusy; /**< Counts the number of times a busy condition occurs when attempting -+ to access an IP-Reassembly Automatic Learning Hash set */ -+ uint32_t moreThan16Fragments; /**< Counts the fragment occurrences in which the number of fragments-per-frame -+ exceeds 16 */ -+ } specificHdrStatistics[2]; /**< slot '0' is for IPv4, slot '1' is for IPv6 */ -+} t_FmPcdManipReassemIpStats; -+ -+/**************************************************************************//** -+ @Description Structure for retrieving IP fragmentation statistics -+*//***************************************************************************/ -+typedef struct t_FmPcdManipFragIpStats { -+ uint32_t totalFrames; /**< Number of frames that passed through the manipulation node */ -+ uint32_t fragmentedFrames; /**< Number of frames that were fragmented */ -+ uint32_t generatedFragments; /**< Number of fragments that were generated */ -+} t_FmPcdManipFragIpStats; -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description Structure for retrieving CAPWAP reassembly statistics -+*//***************************************************************************/ -+typedef struct t_FmPcdManipReassemCapwapStats { -+ uint32_t timeout; /**< Counts the number of timeout occurrences */ -+ uint32_t rfdPoolBusy; /**< Counts the number of failed attempts to allocate -+ a Reassembly Frame Descriptor */ -+ uint32_t internalBufferBusy; /**< Counts the number of times an internal buffer busy occurred */ -+ uint32_t externalBufferBusy; /**< Counts the number of times external buffer busy occurred */ -+ uint32_t sgFragments; /**< Counts the number of Scatter/Gather fragments */ -+ uint32_t dmaSemaphoreDepletion; /**< Counts the number of failed attempts to allocate a DMA semaphore */ -+ uint32_t successfullyReassembled; /**< Counts the number of successfully reassembled frames */ -+ uint32_t validFragments; /**< Counts the total number of valid fragments that -+ have been processed for all frames */ -+ uint32_t processedFragments; /**< Counts the number of processed fragments -+ (valid and error fragments) for all frames */ -+ uint32_t malformedFragments; /**< Counts the number of malformed fragments processed for all frames */ -+ uint32_t autoLearnBusy; /**< Counts the number of times a busy condition occurs when attempting -+ to access an Reassembly Automatic Learning Hash set */ -+ uint32_t discardedFragments; /**< Counts the number of fragments discarded by the reassembly process */ -+ uint32_t moreThan16Fragments; /**< Counts the fragment occurrences in which the number of fragments-per-frame -+ exceeds 16 */ -+ uint32_t exceedMaxReassemblyFrameLen;/**< ounts the number of times that a successful reassembled frame -+ length exceeds MaxReassembledFrameLength value */ -+} t_FmPcdManipReassemCapwapStats; -+ -+/**************************************************************************//** -+ @Description Structure for retrieving CAPWAP fragmentation statistics -+*//***************************************************************************/ -+typedef struct t_FmPcdManipFragCapwapStats { -+ uint32_t totalFrames; /**< Number of frames that passed through the manipulation node */ -+ uint32_t fragmentedFrames; /**< Number of frames that were fragmented */ -+ uint32_t generatedFragments; /**< Number of fragments that were generated */ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ uint8_t sgAllocationFailure; /**< Number of allocation failure of s/g buffers */ -+#endif /* (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) */ -+} t_FmPcdManipFragCapwapStats; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Description Structure for retrieving reassembly statistics -+*//***************************************************************************/ -+typedef struct t_FmPcdManipReassemStats { -+ union { -+ t_FmPcdManipReassemIpStats ipReassem; /**< Structure for IP reassembly statistics */ -+#if (DPAA_VERSION >= 11) -+ t_FmPcdManipReassemCapwapStats capwapReassem; /**< Structure for CAPWAP reassembly statistics */ -+#endif /* (DPAA_VERSION >= 11) */ -+ } u; -+} t_FmPcdManipReassemStats; -+ -+/**************************************************************************//** -+ @Description Structure for retrieving fragmentation statistics -+*//***************************************************************************/ -+typedef struct t_FmPcdManipFragStats { -+ union { -+ t_FmPcdManipFragIpStats ipFrag; /**< Structure for IP fragmentation statistics */ -+#if (DPAA_VERSION >= 11) -+ t_FmPcdManipFragCapwapStats capwapFrag; /**< Structure for CAPWAP fragmentation statistics */ -+#endif /* (DPAA_VERSION >= 11) */ -+ } u; -+} t_FmPcdManipFragStats; -+ -+/**************************************************************************//** -+ @Description Structure for selecting manipulation statistics -+*//***************************************************************************/ -+typedef struct t_FmPcdManipStats { -+ union { -+ t_FmPcdManipReassemStats reassem; /**< Structure for reassembly statistics */ -+ t_FmPcdManipFragStats frag; /**< Structure for fragmentation statistics */ -+ } u; -+} t_FmPcdManipStats; -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description Parameters for defining frame replicator group and its members -+*//***************************************************************************/ -+typedef struct t_FmPcdFrmReplicGroupParams { -+ uint8_t maxNumOfEntries; /**< Maximal number of members in the group; -+ Must be at least 2. */ -+ uint8_t numOfEntries; /**< Number of members in the group; -+ Must be at least 1. */ -+ t_FmPcdCcNextEngineParams nextEngineParams[FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES]; -+ /**< Array of members' parameters */ -+} t_FmPcdFrmReplicGroupParams; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+/**************************************************************************//** -+ @Description structure for defining statistics node -+*//***************************************************************************/ -+typedef struct t_FmPcdStatsParams { -+ e_FmPcdStatsType type; /**< type of statistics node */ -+} t_FmPcdStatsParams; -+#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+ -+/**************************************************************************//** -+ @Function FM_PCD_NetEnvCharacteristicsSet -+ -+ @Description Define a set of Network Environment Characteristics. -+ -+ When setting an environment it is important to understand its -+ application. It is not meant to describe the flows that will run -+ on the ports using this environment, but what the user means TO DO -+ with the PCD mechanisms in order to parse-classify-distribute those -+ frames. -+ By specifying a distinction unit, the user means it would use that option -+ for distinction between frames at either a KeyGen scheme or a coarse -+ classification action descriptor. Using interchangeable headers to define a -+ unit means that the user is indifferent to which of the interchangeable -+ headers is present in the frame, and wants the distinction to be based -+ on the presence of either one of them. -+ -+ Depending on context, there are limitations to the use of environments. A -+ port using the PCD functionality is bound to an environment. Some or even -+ all ports may share an environment but also an environment per port is -+ possible. When initializing a scheme, a classification plan group (see below), -+ or a coarse classification tree, one of the initialized environments must be -+ stated and related to. When a port is bound to a scheme, a classification -+ plan group, or a coarse classification tree, it MUST be bound to the same -+ environment. -+ -+ The different PCD modules, may relate (for flows definition) ONLY on -+ distinction units as defined by their environment. When initializing a -+ scheme for example, it may not choose to select IPV4 as a match for -+ recognizing flows unless it was defined in the relating environment. In -+ fact, to guide the user through the configuration of the PCD, each module's -+ characterization in terms of flows is not done using protocol names, but using -+ environment indexes. -+ -+ In terms of HW implementation, the list of distinction units sets the LCV vectors -+ and later used for match vector, classification plan vectors and coarse classification -+ indexing. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] p_NetEnvParams A structure of parameters for the initialization of -+ the network environment. -+ -+ @Return A handle to the initialized object on success; NULL code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Handle FM_PCD_NetEnvCharacteristicsSet(t_Handle h_FmPcd, t_FmPcdNetEnvParams *p_NetEnvParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_NetEnvCharacteristicsDelete -+ -+ @Description Deletes a set of Network Environment Characteristics. -+ -+ @Param[in] h_NetEnv A handle to the Network environment. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_PCD_NetEnvCharacteristicsDelete(t_Handle h_NetEnv); -+ -+/**************************************************************************//** -+ @Function FM_PCD_KgSchemeSet -+ -+ @Description Initializing or modifying and enabling a scheme for the KeyGen. -+ This routine should be called for adding or modifying a scheme. -+ When a scheme needs modifying, the API requires that it will be -+ rewritten. In such a case 'modify' should be TRUE. If the -+ routine is called for a valid scheme and 'modify' is FALSE, -+ it will return error. -+ -+ @Param[in] h_FmPcd If this is a new scheme - A handle to an FM PCD Module. -+ Otherwise NULL (ignored by driver). -+ @Param[in,out] p_SchemeParams A structure of parameters for defining the scheme -+ -+ @Return A handle to the initialized scheme on success; NULL code otherwise. -+ When used as "modify" (rather than for setting a new scheme), -+ p_SchemeParams->id.h_Scheme will return NULL if action fails due to scheme -+ BUSY state. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Handle FM_PCD_KgSchemeSet(t_Handle h_FmPcd, -+ t_FmPcdKgSchemeParams *p_SchemeParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_KgSchemeDelete -+ -+ @Description Deleting an initialized scheme. -+ -+ @Param[in] h_Scheme scheme handle as returned by FM_PCD_KgSchemeSet() -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init() & FM_PCD_KgSchemeSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_KgSchemeDelete(t_Handle h_Scheme); -+ -+/**************************************************************************//** -+ @Function FM_PCD_KgSchemeGetCounter -+ -+ @Description Reads scheme packet counter. -+ -+ @Param[in] h_Scheme scheme handle as returned by FM_PCD_KgSchemeSet(). -+ -+ @Return Counter's current value. -+ -+ @Cautions Allowed only following FM_PCD_Init() & FM_PCD_KgSchemeSet(). -+*//***************************************************************************/ -+uint32_t FM_PCD_KgSchemeGetCounter(t_Handle h_Scheme); -+ -+/**************************************************************************//** -+ @Function FM_PCD_KgSchemeSetCounter -+ -+ @Description Writes scheme packet counter. -+ -+ @Param[in] h_Scheme scheme handle as returned by FM_PCD_KgSchemeSet(). -+ @Param[in] value New scheme counter value - typically '0' for -+ resetting the counter. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init() & FM_PCD_KgSchemeSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_KgSchemeSetCounter(t_Handle h_Scheme, uint32_t value); -+ -+/**************************************************************************//** -+ @Function FM_PCD_PlcrProfileSet -+ -+ @Description Sets a profile entry in the policer profile table. -+ The routine overrides any existing value. -+ -+ @Param[in] h_FmPcd A handle to an FM PCD Module. -+ @Param[in] p_Profile A structure of parameters for defining a -+ policer profile entry. -+ -+ @Return A handle to the initialized object on success; NULL code otherwise. -+ When used as "modify" (rather than for setting a new profile), -+ p_Profile->id.h_Profile will return NULL if action fails due to profile -+ BUSY state. -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Handle FM_PCD_PlcrProfileSet(t_Handle h_FmPcd, -+ t_FmPcdPlcrProfileParams *p_Profile); -+ -+/**************************************************************************//** -+ @Function FM_PCD_PlcrProfileDelete -+ -+ @Description Delete a profile entry in the policer profile table. -+ The routine set entry to invalid. -+ -+ @Param[in] h_Profile A handle to the profile. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Error FM_PCD_PlcrProfileDelete(t_Handle h_Profile); -+ -+/**************************************************************************//** -+ @Function FM_PCD_PlcrProfileGetCounter -+ -+ @Description Sets an entry in the classification plan. -+ The routine overrides any existing value. -+ -+ @Param[in] h_Profile A handle to the profile. -+ @Param[in] counter Counter selector. -+ -+ @Return specific counter value. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+uint32_t FM_PCD_PlcrProfileGetCounter(t_Handle h_Profile, -+ e_FmPcdPlcrProfileCounters counter); -+ -+/**************************************************************************//** -+ @Function FM_PCD_PlcrProfileSetCounter -+ -+ @Description Sets an entry in the classification plan. -+ The routine overrides any existing value. -+ -+ @Param[in] h_Profile A handle to the profile. -+ @Param[in] counter Counter selector. -+ @Param[in] value value to set counter with. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Error FM_PCD_PlcrProfileSetCounter(t_Handle h_Profile, -+ e_FmPcdPlcrProfileCounters counter, -+ uint32_t value); -+ -+/**************************************************************************//** -+ @Function FM_PCD_CcRootBuild -+ -+ @Description This routine must be called to define a complete coarse -+ classification tree. This is the way to define coarse -+ classification to a certain flow - the KeyGen schemes -+ may point only to trees defined in this way. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] p_Params A structure of parameters to define the tree. -+ -+ @Return A handle to the initialized object on success; NULL code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Handle FM_PCD_CcRootBuild (t_Handle h_FmPcd, -+ t_FmPcdCcTreeParams *p_Params); -+ -+/**************************************************************************//** -+ @Function FM_PCD_CcRootDelete -+ -+ @Description Deleting an built tree. -+ -+ @Param[in] h_CcTree A handle to a CC tree. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Error FM_PCD_CcRootDelete(t_Handle h_CcTree); -+ -+/**************************************************************************//** -+ @Function FM_PCD_CcRootModifyNextEngine -+ -+ @Description Modify the Next Engine Parameters in the entry of the tree. -+ -+ @Param[in] h_CcTree A handle to the tree -+ @Param[in] grpId A Group index in the tree -+ @Param[in] index Entry index in the group defined by grpId -+ @Param[in] p_FmPcdCcNextEngineParams Pointer to new next engine parameters -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_CcBuildTree(). -+*//***************************************************************************/ -+t_Error FM_PCD_CcRootModifyNextEngine(t_Handle h_CcTree, -+ uint8_t grpId, -+ uint8_t index, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableSet -+ -+ @Description This routine should be called for each CC (coarse classification) -+ node. The whole CC tree should be built bottom up so that each -+ node points to already defined nodes. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] p_Param A structure of parameters defining the CC node -+ -+ @Return A handle to the initialized object on success; NULL code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Handle FM_PCD_MatchTableSet(t_Handle h_FmPcd, t_FmPcdCcNodeParams *p_Param); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableDelete -+ -+ @Description Deleting an built node. -+ -+ @Param[in] h_CcNode A handle to a CC node. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableDelete(t_Handle h_CcNode); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableModifyMissNextEngine -+ -+ @Description Modify the Next Engine Parameters of the Miss key case of the node. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] p_FmPcdCcNextEngineParams Parameters for defining next engine -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet(); -+ Not relevant in the case the node is of type 'INDEXED_LOOKUP'. -+ When configuring nextEngine = e_FM_PCD_CC, note that -+ p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different -+ from the currently changed table. -+ -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableModifyMissNextEngine(t_Handle h_CcNode, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableRemoveKey -+ -+ @Description Remove the key (including next engine parameters of this key) -+ defined by the index of the relevant node. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] keyIndex Key index for removing -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet() was called for this -+ node and the nodes that lead to it. -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableRemoveKey(t_Handle h_CcNode, uint16_t keyIndex); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableAddKey -+ -+ @Description Add the key (including next engine parameters of this key in the -+ index defined by the keyIndex. Note that 'FM_PCD_LAST_KEY_INDEX' -+ may be used by user that don't care about the position of the -+ key in the table - in that case, the key will be automatically -+ added by the driver in the last available entry. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] keyIndex Key index for adding. -+ @Param[in] keySize Key size of added key -+ @Param[in] p_KeyParams A pointer to the parameters includes -+ new key with Next Engine Parameters -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet() was called for this -+ node and the nodes that lead to it. -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableAddKey(t_Handle h_CcNode, -+ uint16_t keyIndex, -+ uint8_t keySize, -+ t_FmPcdCcKeyParams *p_KeyParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableModifyNextEngine -+ -+ @Description Modify the Next Engine Parameters in the relevant key entry of the node. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] keyIndex Key index for Next Engine modifications -+ @Param[in] p_FmPcdCcNextEngineParams Parameters for defining next engine -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet(). -+ When configuring nextEngine = e_FM_PCD_CC, note that -+ p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different -+ from the currently changed table. -+ -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableModifyNextEngine(t_Handle h_CcNode, -+ uint16_t keyIndex, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableModifyKeyAndNextEngine -+ -+ @Description Modify the key and Next Engine Parameters of this key in the -+ index defined by the keyIndex. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] keyIndex Key index for adding -+ @Param[in] keySize Key size of added key -+ @Param[in] p_KeyParams A pointer to the parameters includes -+ modified key and modified Next Engine Parameters -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet() was called for this -+ node and the nodes that lead to it. -+ When configuring nextEngine = e_FM_PCD_CC, note that -+ p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different -+ from the currently changed table. -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableModifyKeyAndNextEngine(t_Handle h_CcNode, -+ uint16_t keyIndex, -+ uint8_t keySize, -+ t_FmPcdCcKeyParams *p_KeyParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableModifyKey -+ -+ @Description Modify the key in the index defined by the keyIndex. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] keyIndex Key index for adding -+ @Param[in] keySize Key size of added key -+ @Param[in] p_Key A pointer to the new key -+ @Param[in] p_Mask A pointer to the new mask if relevant, -+ otherwise pointer to NULL -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet() was called for this -+ node and the nodes that lead to it. -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableModifyKey(t_Handle h_CcNode, -+ uint16_t keyIndex, -+ uint8_t keySize, -+ uint8_t *p_Key, -+ uint8_t *p_Mask); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableFindNRemoveKey -+ -+ @Description Remove the key (including next engine parameters of this key) -+ defined by the key and mask. Note that this routine will search -+ the node to locate the index of the required key (& mask) to remove. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] keySize Key size of the one to remove. -+ @Param[in] p_Key A pointer to the requested key to remove. -+ @Param[in] p_Mask A pointer to the mask if relevant, -+ otherwise pointer to NULL -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet() was called for this -+ node and the nodes that lead to it. -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableFindNRemoveKey(t_Handle h_CcNode, -+ uint8_t keySize, -+ uint8_t *p_Key, -+ uint8_t *p_Mask); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableFindNModifyNextEngine -+ -+ @Description Modify the Next Engine Parameters in the relevant key entry of -+ the node. Note that this routine will search the node to locate -+ the index of the required key (& mask) to modify. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] keySize Key size of the one to modify. -+ @Param[in] p_Key A pointer to the requested key to modify. -+ @Param[in] p_Mask A pointer to the mask if relevant, -+ otherwise pointer to NULL -+ @Param[in] p_FmPcdCcNextEngineParams Parameters for defining next engine -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet(). -+ When configuring nextEngine = e_FM_PCD_CC, note that -+ p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different -+ from the currently changed table. -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableFindNModifyNextEngine(t_Handle h_CcNode, -+ uint8_t keySize, -+ uint8_t *p_Key, -+ uint8_t *p_Mask, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableFindNModifyKeyAndNextEngine -+ -+ @Description Modify the key and Next Engine Parameters of this key in the -+ index defined by the keyIndex. Note that this routine will search -+ the node to locate the index of the required key (& mask) to modify. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] keySize Key size of the one to modify. -+ @Param[in] p_Key A pointer to the requested key to modify. -+ @Param[in] p_Mask A pointer to the mask if relevant, -+ otherwise pointer to NULL -+ @Param[in] p_KeyParams A pointer to the parameters includes -+ modified key and modified Next Engine Parameters -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet() was called for this -+ node and the nodes that lead to it. -+ When configuring nextEngine = e_FM_PCD_CC, note that -+ p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different -+ from the currently changed table. -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableFindNModifyKeyAndNextEngine(t_Handle h_CcNode, -+ uint8_t keySize, -+ uint8_t *p_Key, -+ uint8_t *p_Mask, -+ t_FmPcdCcKeyParams *p_KeyParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableFindNModifyKey -+ -+ @Description Modify the key in the index defined by the keyIndex. Note that -+ this routine will search the node to locate the index of the -+ required key (& mask) to modify. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] keySize Key size of the one to modify. -+ @Param[in] p_Key A pointer to the requested key to modify. -+ @Param[in] p_Mask A pointer to the mask if relevant, -+ otherwise pointer to NULL -+ @Param[in] p_NewKey A pointer to the new key -+ @Param[in] p_NewMask A pointer to the new mask if relevant, -+ otherwise pointer to NULL -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet() was called for this -+ node and the nodes that lead to it. -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableFindNModifyKey(t_Handle h_CcNode, -+ uint8_t keySize, -+ uint8_t *p_Key, -+ uint8_t *p_Mask, -+ uint8_t *p_NewKey, -+ uint8_t *p_NewMask); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableGetKeyCounter -+ -+ @Description This routine may be used to get a counter of specific key in a CC -+ Node; This counter reflects how many frames passed that were matched -+ this key. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] keyIndex Key index for adding -+ -+ @Return The specific key counter. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet(). -+*//***************************************************************************/ -+uint32_t FM_PCD_MatchTableGetKeyCounter(t_Handle h_CcNode, uint16_t keyIndex); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableGetKeyStatistics -+ -+ @Description This routine may be used to get statistics counters of specific key -+ in a CC Node. -+ -+ If 'e_FM_PCD_CC_STATS_MODE_FRAME' and -+ 'e_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME' were set for this node, -+ these counters reflect how many frames passed that were matched -+ this key; The total frames count will be returned in the counter -+ of the first range (as only one frame length range was defined). -+ If 'e_FM_PCD_CC_STATS_MODE_RMON' was set for this node, the total -+ frame count will be separated to frame length counters, based on -+ provided frame length ranges. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] keyIndex Key index for adding -+ @Param[out] p_KeyStatistics Key statistics counters -+ -+ @Return The specific key statistics. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableGetKeyStatistics(t_Handle h_CcNode, -+ uint16_t keyIndex, -+ t_FmPcdCcKeyStatistics *p_KeyStatistics); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableGetMissStatistics -+ -+ @Description This routine may be used to get statistics counters of miss entry -+ in a CC Node. -+ -+ If 'e_FM_PCD_CC_STATS_MODE_FRAME' and -+ 'e_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME' were set for this node, -+ these counters reflect how many frames were not matched to any -+ existing key and therefore passed through the miss entry; The -+ total frames count will be returned in the counter of the -+ first range (as only one frame length range was defined). -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[out] p_MissStatistics Statistics counters for 'miss' -+ -+ @Return The statistics for 'miss'. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableGetMissStatistics(t_Handle h_CcNode, -+ t_FmPcdCcKeyStatistics *p_MissStatistics); -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableFindNGetKeyStatistics -+ -+ @Description This routine may be used to get statistics counters of specific key -+ in a CC Node. -+ -+ If 'e_FM_PCD_CC_STATS_MODE_FRAME' and -+ 'e_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME' were set for this node, -+ these counters reflect how many frames passed that were matched -+ this key; The total frames count will be returned in the counter -+ of the first range (as only one frame length range was defined). -+ If 'e_FM_PCD_CC_STATS_MODE_RMON' was set for this node, the total -+ frame count will be separated to frame length counters, based on -+ provided frame length ranges. -+ Note that this routine will search the node to locate the index -+ of the required key based on received key parameters. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] keySize Size of the requested key -+ @Param[in] p_Key A pointer to the requested key -+ @Param[in] p_Mask A pointer to the mask if relevant, -+ otherwise pointer to NULL -+ @Param[out] p_KeyStatistics Key statistics counters -+ -+ @Return The specific key statistics. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableFindNGetKeyStatistics(t_Handle h_CcNode, -+ uint8_t keySize, -+ uint8_t *p_Key, -+ uint8_t *p_Mask, -+ t_FmPcdCcKeyStatistics *p_KeyStatistics); -+ -+/**************************************************************************//* -+ @Function FM_PCD_MatchTableGetNextEngine -+ -+ @Description Gets NextEngine of the relevant keyIndex. -+ -+ @Param[in] h_CcNode A handle to the node. -+ @Param[in] keyIndex keyIndex in the relevant node. -+ @Param[out] p_FmPcdCcNextEngineParams here updated nextEngine parameters for -+ the relevant keyIndex of the CC Node -+ received as parameter to this function -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableGetNextEngine(t_Handle h_CcNode, -+ uint16_t keyIndex, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams); -+ -+/**************************************************************************//* -+ @Function FM_PCD_MatchTableGetIndexedHashBucket -+ -+ @Description This routine simulates KeyGen operation on the provided key and -+ calculates to which hash bucket it will be mapped. -+ -+ @Param[in] h_CcNode A handle to the node. -+ @Param[in] kgKeySize Key size as it was configured in the KG -+ scheme that leads to this hash. -+ @Param[in] p_KgKey Pointer to the key; must be like the key -+ that the KG is generated, i.e. the same -+ extraction and with mask if exist. -+ @Param[in] kgHashShift Hash-shift as it was configured in the KG -+ scheme that leads to this hash. -+ @Param[out] p_CcNodeBucketHandle Pointer to the bucket of the provided key. -+ @Param[out] p_BucketIndex Index to the bucket of the provided key -+ @Param[out] p_LastIndex Pointer to last index in the bucket of the -+ provided key. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_HashTableSet() -+*//***************************************************************************/ -+t_Error FM_PCD_MatchTableGetIndexedHashBucket(t_Handle h_CcNode, -+ uint8_t kgKeySize, -+ uint8_t *p_KgKey, -+ uint8_t kgHashShift, -+ t_Handle *p_CcNodeBucketHandle, -+ uint8_t *p_BucketIndex, -+ uint16_t *p_LastIndex); -+ -+/**************************************************************************//** -+ @Function FM_PCD_HashTableSet -+ -+ @Description This routine initializes a hash table structure. -+ KeyGen hash result determines the hash bucket. -+ Next, KeyGen key is compared against all keys of this -+ bucket (exact match). -+ Number of sets (number of buckets) of the hash equals to the -+ number of 1-s in 'hashResMask' in the provided parameters. -+ Number of hash table ways is then calculated by dividing -+ 'maxNumOfKeys' equally between the hash sets. This is the maximal -+ number of keys that a hash bucket may hold. -+ The hash table is initialized empty and keys may be -+ added to it following the initialization. Keys masks are not -+ supported in current hash table implementation. -+ The initialized hash table can be integrated as a node in a -+ CC tree. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] p_Param A structure of parameters defining the hash table -+ -+ @Return A handle to the initialized object on success; NULL code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Handle FM_PCD_HashTableSet(t_Handle h_FmPcd, t_FmPcdHashTableParams *p_Param); -+ -+/**************************************************************************//** -+ @Function FM_PCD_HashTableDelete -+ -+ @Description This routine deletes the provided hash table and released all -+ its allocated resources. -+ -+ @Param[in] h_HashTbl A handle to a hash table -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_HashTableSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_HashTableDelete(t_Handle h_HashTbl); -+ -+/**************************************************************************//** -+ @Function FM_PCD_HashTableAddKey -+ -+ @Description This routine adds the provided key (including next engine -+ parameters of this key) to the hash table. -+ The key is added as the last key of the bucket that it is -+ mapped to. -+ -+ @Param[in] h_HashTbl A handle to a hash table -+ @Param[in] keySize Key size of added key -+ @Param[in] p_KeyParams A pointer to the parameters includes -+ new key with next engine parameters; The pointer -+ to the key mask must be NULL, as masks are not -+ supported in hash table implementation. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_HashTableSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_HashTableAddKey(t_Handle h_HashTbl, -+ uint8_t keySize, -+ t_FmPcdCcKeyParams *p_KeyParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_HashTableRemoveKey -+ -+ @Description This routine removes the requested key (including next engine -+ parameters of this key) from the hash table. -+ -+ @Param[in] h_HashTbl A handle to a hash table -+ @Param[in] keySize Key size of the one to remove. -+ @Param[in] p_Key A pointer to the requested key to remove. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_HashTableSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_HashTableRemoveKey(t_Handle h_HashTbl, -+ uint8_t keySize, -+ uint8_t *p_Key); -+ -+/**************************************************************************//** -+ @Function FM_PCD_HashTableModifyNextEngine -+ -+ @Description This routine modifies the next engine for the provided key. The -+ key should be previously added to the hash table. -+ -+ @Param[in] h_HashTbl A handle to a hash table -+ @Param[in] keySize Key size of the key to modify. -+ @Param[in] p_Key A pointer to the requested key to modify. -+ @Param[in] p_FmPcdCcNextEngineParams A structure for defining new next engine -+ parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_HashTableSet(). -+ When configuring nextEngine = e_FM_PCD_CC, note that -+ p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different -+ from the currently changed table. -+*//***************************************************************************/ -+t_Error FM_PCD_HashTableModifyNextEngine(t_Handle h_HashTbl, -+ uint8_t keySize, -+ uint8_t *p_Key, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_HashTableModifyMissNextEngine -+ -+ @Description This routine modifies the next engine on key match miss. -+ -+ @Param[in] h_HashTbl A handle to a hash table -+ @Param[in] p_FmPcdCcNextEngineParams A structure for defining new next engine -+ parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_HashTableSet(). -+ When configuring nextEngine = e_FM_PCD_CC, note that -+ p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different -+ from the currently changed table. -+*//***************************************************************************/ -+t_Error FM_PCD_HashTableModifyMissNextEngine(t_Handle h_HashTbl, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams); -+ -+/**************************************************************************//* -+ @Function FM_PCD_HashTableGetMissNextEngine -+ -+ @Description Gets NextEngine in case of key match miss. -+ -+ @Param[in] h_HashTbl A handle to a hash table -+ @Param[out] p_FmPcdCcNextEngineParams Next engine parameters for the specified -+ hash table. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_HashTableSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_HashTableGetMissNextEngine(t_Handle h_HashTbl, -+ t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_HashTableFindNGetKeyStatistics -+ -+ @Description This routine may be used to get statistics counters of specific key -+ in a hash table. -+ -+ If 'e_FM_PCD_CC_STATS_MODE_FRAME' and -+ 'e_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME' were set for this node, -+ these counters reflect how many frames passed that were matched -+ this key; The total frames count will be returned in the counter -+ of the first range (as only one frame length range was defined). -+ If 'e_FM_PCD_CC_STATS_MODE_RMON' was set for this node, the total -+ frame count will be separated to frame length counters, based on -+ provided frame length ranges. -+ Note that this routine will identify the bucket of this key in -+ the hash table and will search the bucket to locate the index -+ of the required key based on received key parameters. -+ -+ @Param[in] h_HashTbl A handle to a hash table -+ @Param[in] keySize Size of the requested key -+ @Param[in] p_Key A pointer to the requested key -+ @Param[out] p_KeyStatistics Key statistics counters -+ -+ @Return The specific key statistics. -+ -+ @Cautions Allowed only following FM_PCD_HashTableSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_HashTableFindNGetKeyStatistics(t_Handle h_HashTbl, -+ uint8_t keySize, -+ uint8_t *p_Key, -+ t_FmPcdCcKeyStatistics *p_KeyStatistics); -+ -+/**************************************************************************//** -+ @Function FM_PCD_HashTableGetMissStatistics -+ -+ @Description This routine may be used to get statistics counters of 'miss' -+ entry of the a hash table. -+ -+ If 'e_FM_PCD_CC_STATS_MODE_FRAME' and -+ 'e_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME' were set for this node, -+ these counters reflect how many frames were not matched to any -+ existing key and therefore passed through the miss entry; -+ -+ @Param[in] h_HashTbl A handle to a hash table -+ @Param[out] p_MissStatistics Statistics counters for 'miss' -+ -+ @Return The statistics for 'miss'. -+ -+ @Cautions Allowed only following FM_PCD_HashTableSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_HashTableGetMissStatistics(t_Handle h_HashTbl, -+ t_FmPcdCcKeyStatistics *p_MissStatistics); -+ -+/**************************************************************************//** -+ @Function FM_PCD_ManipNodeSet -+ -+ @Description This routine should be called for defining a manipulation -+ node. A manipulation node must be defined before the CC node -+ that precedes it. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] p_FmPcdManipParams A structure of parameters defining the manipulation -+ -+ @Return A handle to the initialized object on success; NULL code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Handle FM_PCD_ManipNodeSet(t_Handle h_FmPcd, t_FmPcdManipParams *p_FmPcdManipParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_ManipNodeDelete -+ -+ @Description Delete an existing manipulation node. -+ -+ @Param[in] h_ManipNode A handle to a manipulation node. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_ManipNodeSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_ManipNodeDelete(t_Handle h_ManipNode); -+ -+/**************************************************************************//** -+ @Function FM_PCD_ManipGetStatistics -+ -+ @Description Retrieve the manipulation statistics. -+ -+ @Param[in] h_ManipNode A handle to a manipulation node. -+ @Param[out] p_FmPcdManipStats A structure for retrieving the manipulation statistics -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_ManipNodeSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_ManipGetStatistics(t_Handle h_ManipNode, t_FmPcdManipStats *p_FmPcdManipStats); -+ -+/**************************************************************************//** -+ @Function FM_PCD_ManipNodeReplace -+ -+ @Description Change existing manipulation node to be according to new requirement. -+ -+ @Param[in] h_ManipNode A handle to a manipulation node. -+ @Param[out] p_ManipParams A structure of parameters defining the change requirement -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_ManipNodeSet(). -+*//***************************************************************************/ -+t_Error FM_PCD_ManipNodeReplace(t_Handle h_ManipNode, t_FmPcdManipParams *p_ManipParams); -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Function FM_PCD_FrmReplicSetGroup -+ -+ @Description Initialize a Frame Replicator group. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] p_FrmReplicGroupParam A structure of parameters for the initialization of -+ the frame replicator group. -+ -+ @Return A handle to the initialized object on success; NULL code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Handle FM_PCD_FrmReplicSetGroup(t_Handle h_FmPcd, t_FmPcdFrmReplicGroupParams *p_FrmReplicGroupParam); -+ -+/**************************************************************************//** -+ @Function FM_PCD_FrmReplicDeleteGroup -+ -+ @Description Delete a Frame Replicator group. -+ -+ @Param[in] h_FrmReplicGroup A handle to the frame replicator group. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_FrmReplicSetGroup(). -+*//***************************************************************************/ -+t_Error FM_PCD_FrmReplicDeleteGroup(t_Handle h_FrmReplicGroup); -+ -+/**************************************************************************//** -+ @Function FM_PCD_FrmReplicAddMember -+ -+ @Description Add the member in the index defined by the memberIndex. -+ -+ @Param[in] h_FrmReplicGroup A handle to the frame replicator group. -+ @Param[in] memberIndex member index for adding. -+ @Param[in] p_MemberParams A pointer to the new member parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_FrmReplicSetGroup() of this group. -+*//***************************************************************************/ -+t_Error FM_PCD_FrmReplicAddMember(t_Handle h_FrmReplicGroup, -+ uint16_t memberIndex, -+ t_FmPcdCcNextEngineParams *p_MemberParams); -+ -+/**************************************************************************//** -+ @Function FM_PCD_FrmReplicRemoveMember -+ -+ @Description Remove the member defined by the index from the relevant group. -+ -+ @Param[in] h_FrmReplicGroup A handle to the frame replicator group. -+ @Param[in] memberIndex member index for removing. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_FrmReplicSetGroup() of this group. -+*//***************************************************************************/ -+t_Error FM_PCD_FrmReplicRemoveMember(t_Handle h_FrmReplicGroup, -+ uint16_t memberIndex); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+/**************************************************************************//** -+ @Function FM_PCD_StatisticsSetNode -+ -+ @Description This routine should be called for defining a statistics node. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] p_FmPcdstatsParams A structure of parameters defining the statistics -+ -+ @Return A handle to the initialized object on success; NULL code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+t_Handle FM_PCD_StatisticsSetNode(t_Handle h_FmPcd, t_FmPcdStatsParams *p_FmPcdstatsParams); -+#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+ -+/** @} */ /* end of FM_PCD_Runtime_build_grp group */ -+/** @} */ /* end of FM_PCD_Runtime_grp group */ -+/** @} */ /* end of FM_PCD_grp group */ -+/** @} */ /* end of FM_grp group */ -+ -+ -+#ifdef NCSW_BACKWARD_COMPATIBLE_API -+#define FM_PCD_MAX_NUM_OF_INTERCHANGABLE_HDRS FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS -+#define e_FM_PCD_MANIP_ONE_WAYS_HASH e_FM_PCD_MANIP_ONE_WAY_HASH -+#define e_FM_PCD_MANIP_TOW_WAYS_HASH e_FM_PCD_MANIP_TWO_WAYS_HASH -+ -+#define e_FM_PCD_MANIP_FRAGMENT_PACKECT e_FM_PCD_MANIP_FRAGMENT_PACKET /* Feb13 */ -+ -+#define FM_PCD_SetNetEnvCharacteristics(_pcd, _params) \ -+ FM_PCD_NetEnvCharacteristicsSet(_pcd, _params) -+#define FM_PCD_KgSetScheme(_pcd, _params) FM_PCD_KgSchemeSet(_pcd, _params) -+#define FM_PCD_CcBuildTree(_pcd, _params) FM_PCD_CcRootBuild(_pcd, _params) -+#define FM_PCD_CcSetNode(_pcd, _params) FM_PCD_MatchTableSet(_pcd, _params) -+#define FM_PCD_PlcrSetProfile(_pcd, _params) FM_PCD_PlcrProfileSet(_pcd, _params) -+#define FM_PCD_ManipSetNode(_pcd, _params) FM_PCD_ManipNodeSet(_pcd, _params) -+ -+#define FM_PCD_DeleteNetEnvCharacteristics(_pcd, ...) \ -+ FM_PCD_NetEnvCharacteristicsDelete(__VA_ARGS__) -+#define FM_PCD_KgDeleteScheme(_pcd, ...) \ -+ FM_PCD_KgSchemeDelete(__VA_ARGS__) -+#define FM_PCD_KgGetSchemeCounter(_pcd, ...) \ -+ FM_PCD_KgSchemeGetCounter(__VA_ARGS__) -+#define FM_PCD_KgSetSchemeCounter(_pcd, ...) \ -+ FM_PCD_KgSchemeSetCounter(__VA_ARGS__) -+#define FM_PCD_PlcrDeleteProfile(_pcd, ...) \ -+ FM_PCD_PlcrProfileDelete(__VA_ARGS__) -+#define FM_PCD_PlcrGetProfileCounter(_pcd, ...) \ -+ FM_PCD_PlcrProfileGetCounter(__VA_ARGS__) -+#define FM_PCD_PlcrSetProfileCounter(_pcd, ...) \ -+ FM_PCD_PlcrProfileSetCounter(__VA_ARGS__) -+#define FM_PCD_CcDeleteTree(_pcd, ...) \ -+ FM_PCD_CcRootDelete(__VA_ARGS__) -+#define FM_PCD_CcTreeModifyNextEngine(_pcd, ...) \ -+ FM_PCD_CcRootModifyNextEngine(__VA_ARGS__) -+#define FM_PCD_CcDeleteNode(_pcd, ...) \ -+ FM_PCD_MatchTableDelete(__VA_ARGS__) -+#define FM_PCD_CcNodeModifyMissNextEngine(_pcd, ...) \ -+ FM_PCD_MatchTableModifyMissNextEngine(__VA_ARGS__) -+#define FM_PCD_CcNodeRemoveKey(_pcd, ...) \ -+ FM_PCD_MatchTableRemoveKey(__VA_ARGS__) -+#define FM_PCD_CcNodeAddKey(_pcd, ...) \ -+ FM_PCD_MatchTableAddKey(__VA_ARGS__) -+#define FM_PCD_CcNodeModifyNextEngine(_pcd, ...) \ -+ FM_PCD_MatchTableModifyNextEngine(__VA_ARGS__) -+#define FM_PCD_CcNodeModifyKeyAndNextEngine(_pcd, ...) \ -+ FM_PCD_MatchTableModifyKeyAndNextEngine(__VA_ARGS__) -+#define FM_PCD_CcNodeModifyKey(_pcd, ...) \ -+ FM_PCD_MatchTableModifyKey(__VA_ARGS__) -+#define FM_PCD_CcNodeFindNRemoveKey(_pcd, ...) \ -+ FM_PCD_MatchTableFindNRemoveKey(__VA_ARGS__) -+#define FM_PCD_CcNodeFindNModifyNextEngine(_pcd, ...) \ -+ FM_PCD_MatchTableFindNModifyNextEngine(__VA_ARGS__) -+#define FM_PCD_CcNodeFindNModifyKeyAndNextEngine(_pcd, ...) \ -+ FM_PCD_MatchTableFindNModifyKeyAndNextEngine(__VA_ARGS__) -+#define FM_PCD_CcNodeFindNModifyKey(_pcd, ...) \ -+ FM_PCD_MatchTableFindNModifyKey(__VA_ARGS__) -+#define FM_PCD_CcIndexedHashNodeGetBucket(_pcd, ...) \ -+ FM_PCD_MatchTableGetIndexedHashBucket(__VA_ARGS__) -+#define FM_PCD_CcNodeGetNextEngine(_pcd, ...) \ -+ FM_PCD_MatchTableGetNextEngine(__VA_ARGS__) -+#define FM_PCD_CcNodeGetKeyCounter(_pcd, ...) \ -+ FM_PCD_MatchTableGetKeyCounter(__VA_ARGS__) -+#define FM_PCD_ManipDeleteNode(_pcd, ...) \ -+ FM_PCD_ManipNodeDelete(__VA_ARGS__) -+#endif /* NCSW_BACKWARD_COMPATIBLE_API */ -+ -+ -+#endif /* __FM_PCD_EXT */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_port_ext.h -@@ -0,0 +1,2608 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File fm_port_ext.h -+ -+ @Description FM-Port Application Programming Interface. -+*//***************************************************************************/ -+#ifndef __FM_PORT_EXT -+#define __FM_PORT_EXT -+ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "fm_pcd_ext.h" -+#include "fm_ext.h" -+#include "net_ext.h" -+ -+ -+/**************************************************************************//** -+ -+ @Group FM_grp Frame Manager API -+ -+ @Description FM API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group FM_PORT_grp FM Port -+ -+ @Description FM Port API -+ -+ The FM uses a general module called "port" to represent a Tx port -+ (MAC), an Rx port (MAC) or Offline Parsing port. -+ The number of ports in an FM varies between SOCs. -+ The SW driver manages these ports as sub-modules of the FM, i.e. -+ after an FM is initialized, its ports may be initialized and -+ operated upon. -+ -+ The port is initialized aware of its type, but other functions on -+ a port may be indifferent to its type. When necessary, the driver -+ verifies coherence and returns error if applicable. -+ -+ On initialization, user specifies the port type and it's index -+ (relative to the port's type) - always starting at 0. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description An enum for defining port PCD modes. -+ This enum defines the superset of PCD engines support - i.e. not -+ all engines have to be used, but all have to be enabled. The real -+ flow of a specific frame depends on the PCD configuration and the -+ frame headers and payload. -+ Note: the first engine and the first engine after the parser (if -+ exists) should be in order, the order is important as it will -+ define the flow of the port. However, as for the rest engines -+ (the ones that follows), the order is not important anymore as -+ it is defined by the PCD graph itself. -+*//***************************************************************************/ -+typedef enum e_FmPortPcdSupport { -+ e_FM_PORT_PCD_SUPPORT_NONE = 0 /**< BMI to BMI, PCD is not used */ -+ , e_FM_PORT_PCD_SUPPORT_PRS_ONLY /**< Use only Parser */ -+ , e_FM_PORT_PCD_SUPPORT_PLCR_ONLY /**< Use only Policer */ -+ , e_FM_PORT_PCD_SUPPORT_PRS_AND_PLCR /**< Use Parser and Policer */ -+ , e_FM_PORT_PCD_SUPPORT_PRS_AND_KG /**< Use Parser and Keygen */ -+ , e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_CC /**< Use Parser, Keygen and Coarse Classification */ -+ , e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_CC_AND_PLCR -+ /**< Use all PCD engines */ -+ , e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_PLCR /**< Use Parser, Keygen and Policer */ -+ , e_FM_PORT_PCD_SUPPORT_PRS_AND_CC /**< Use Parser and Coarse Classification */ -+ , e_FM_PORT_PCD_SUPPORT_PRS_AND_CC_AND_PLCR /**< Use Parser and Coarse Classification and Policer */ -+ , e_FM_PORT_PCD_SUPPORT_CC_ONLY /**< Use only Coarse Classification */ -+#ifdef FM_CAPWAP_SUPPORT -+ , e_FM_PORT_PCD_SUPPORT_CC_AND_KG /**< Use Coarse Classification,and Keygen */ -+ , e_FM_PORT_PCD_SUPPORT_CC_AND_KG_AND_PLCR /**< Use Coarse Classification, Keygen and Policer */ -+#endif /* FM_CAPWAP_SUPPORT */ -+} e_FmPortPcdSupport; -+ -+/**************************************************************************//** -+ @Description Port interrupts -+*//***************************************************************************/ -+typedef enum e_FmPortExceptions { -+ e_FM_PORT_EXCEPTION_IM_BUSY /**< Independent-Mode Rx-BUSY */ -+} e_FmPortExceptions; -+ -+ -+/**************************************************************************//** -+ @Collection General FM Port defines -+*//***************************************************************************/ -+#define FM_PORT_PRS_RESULT_NUM_OF_WORDS 8 /**< Number of 4 bytes words in parser result */ -+/* @} */ -+ -+/**************************************************************************//** -+ @Collection FM Frame error -+*//***************************************************************************/ -+typedef uint32_t fmPortFrameErrSelect_t; /**< typedef for defining Frame Descriptor errors */ -+ -+#define FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT FM_FD_ERR_UNSUPPORTED_FORMAT /**< Not for Rx-Port! Unsupported Format */ -+#define FM_PORT_FRM_ERR_LENGTH FM_FD_ERR_LENGTH /**< Not for Rx-Port! Length Error */ -+#define FM_PORT_FRM_ERR_DMA FM_FD_ERR_DMA /**< DMA Data error */ -+#define FM_PORT_FRM_ERR_NON_FM FM_FD_RX_STATUS_ERR_NON_FM /**< non Frame-Manager error; probably come from SEC that -+ was chained to FM */ -+ -+#define FM_PORT_FRM_ERR_IPRE (FM_FD_ERR_IPR & ~FM_FD_IPR) /**< IPR error */ -+#define FM_PORT_FRM_ERR_IPR_NCSP (FM_FD_ERR_IPR_NCSP & ~FM_FD_IPR) /**< IPR non-consistent-sp */ -+ -+#define FM_PORT_FRM_ERR_IPFE 0 /**< Obsolete; will be removed in the future */ -+ -+#ifdef FM_CAPWAP_SUPPORT -+#define FM_PORT_FRM_ERR_CRE FM_FD_ERR_CRE -+#define FM_PORT_FRM_ERR_CHE FM_FD_ERR_CHE -+#endif /* FM_CAPWAP_SUPPORT */ -+ -+#define FM_PORT_FRM_ERR_PHYSICAL FM_FD_ERR_PHYSICAL /**< Rx FIFO overflow, FCS error, code error, running disparity -+ error (SGMII and TBI modes), FIFO parity error. PHY -+ Sequence error, PHY error control character detected. */ -+#define FM_PORT_FRM_ERR_SIZE FM_FD_ERR_SIZE /**< Frame too long OR Frame size exceeds max_length_frame */ -+#define FM_PORT_FRM_ERR_CLS_DISCARD FM_FD_ERR_CLS_DISCARD /**< indicates a classifier "drop" operation */ -+#define FM_PORT_FRM_ERR_EXTRACTION FM_FD_ERR_EXTRACTION /**< Extract Out of Frame */ -+#define FM_PORT_FRM_ERR_NO_SCHEME FM_FD_ERR_NO_SCHEME /**< No Scheme Selected */ -+#define FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW FM_FD_ERR_KEYSIZE_OVERFLOW /**< Keysize Overflow */ -+#define FM_PORT_FRM_ERR_COLOR_RED FM_FD_ERR_COLOR_RED /**< Frame color is red */ -+#define FM_PORT_FRM_ERR_COLOR_YELLOW FM_FD_ERR_COLOR_YELLOW /**< Frame color is yellow */ -+#define FM_PORT_FRM_ERR_ILL_PLCR FM_FD_ERR_ILL_PLCR /**< Illegal Policer Profile selected */ -+#define FM_PORT_FRM_ERR_PLCR_FRAME_LEN FM_FD_ERR_PLCR_FRAME_LEN /**< Policer frame length error */ -+#define FM_PORT_FRM_ERR_PRS_TIMEOUT FM_FD_ERR_PRS_TIMEOUT /**< Parser Time out Exceed */ -+#define FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT FM_FD_ERR_PRS_ILL_INSTRUCT /**< Invalid Soft Parser instruction */ -+#define FM_PORT_FRM_ERR_PRS_HDR_ERR FM_FD_ERR_PRS_HDR_ERR /**< Header error was identified during parsing */ -+#define FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED FM_FD_ERR_BLOCK_LIMIT_EXCEEDED /**< Frame parsed beyind 256 first bytes */ -+#define FM_PORT_FRM_ERR_PROCESS_TIMEOUT 0x00000001 /**< FPM Frame Processing Timeout Exceeded */ -+/* @} */ -+ -+ -+ -+/**************************************************************************//** -+ @Group FM_PORT_init_grp FM Port Initialization Unit -+ -+ @Description FM Port Initialization Unit -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description Exceptions user callback routine, will be called upon an -+ exception passing the exception identification. -+ -+ @Param[in] h_App - User's application descriptor. -+ @Param[in] exception - The exception. -+ *//***************************************************************************/ -+typedef void (t_FmPortExceptionCallback) (t_Handle h_App, e_FmPortExceptions exception); -+ -+/**************************************************************************//** -+ @Description User callback function called by driver with received data. -+ -+ User provides this function. Driver invokes it. -+ -+ @Param[in] h_App Application's handle originally specified to -+ the API Config function -+ @Param[in] p_Data A pointer to data received -+ @Param[in] length length of received data -+ @Param[in] status receive status and errors -+ @Param[in] position position of buffer in frame -+ @Param[in] h_BufContext A handle of the user acossiated with this buffer -+ -+ @Retval e_RX_STORE_RESPONSE_CONTINUE - order the driver to continue Rx -+ operation for all ready data. -+ @Retval e_RX_STORE_RESPONSE_PAUSE - order the driver to stop Rx operation. -+*//***************************************************************************/ -+typedef e_RxStoreResponse (t_FmPortImRxStoreCallback) (t_Handle h_App, -+ uint8_t *p_Data, -+ uint16_t length, -+ uint16_t status, -+ uint8_t position, -+ t_Handle h_BufContext); -+ -+/**************************************************************************//** -+ @Description User callback function called by driver when transmit completed. -+ -+ User provides this function. Driver invokes it. -+ -+ @Param[in] h_App Application's handle originally specified to -+ the API Config function -+ @Param[in] p_Data A pointer to data received -+ @Param[in] status transmit status and errors -+ @Param[in] lastBuffer is last buffer in frame -+ @Param[in] h_BufContext A handle of the user acossiated with this buffer -+ *//***************************************************************************/ -+typedef void (t_FmPortImTxConfCallback) (t_Handle h_App, -+ uint8_t *p_Data, -+ uint16_t status, -+ t_Handle h_BufContext); -+ -+/**************************************************************************//** -+ @Description A structure for additional Rx port parameters -+*//***************************************************************************/ -+typedef struct t_FmPortRxParams { -+ uint32_t errFqid; /**< Error Queue Id. */ -+ uint32_t dfltFqid; /**< Default Queue Id. */ -+ uint16_t liodnOffset; /**< Port's LIODN offset. */ -+ t_FmExtPools extBufPools; /**< Which external buffer pools are used -+ (up to FM_PORT_MAX_NUM_OF_EXT_POOLS), and their sizes. */ -+} t_FmPortRxParams; -+ -+/**************************************************************************//** -+ @Description A structure for additional non-Rx port parameters -+*//***************************************************************************/ -+typedef struct t_FmPortNonRxParams { -+ uint32_t errFqid; /**< Error Queue Id. */ -+ uint32_t dfltFqid; /**< For Tx - Default Confirmation queue, -+ 0 means no Tx confirmation for processed -+ frames. For OP port - default Rx queue. */ -+ uint32_t qmChannel; /**< QM-channel dedicated to this port; will be used -+ by the FM for dequeue. */ -+} t_FmPortNonRxParams; -+ -+/**************************************************************************//** -+ @Description A structure for additional Rx port parameters -+*//***************************************************************************/ -+typedef struct t_FmPortImRxTxParams { -+ t_Handle h_FmMuram; /**< A handle of the FM-MURAM partition */ -+ uint16_t liodnOffset; /**< For Rx ports only. Port's LIODN Offset. */ -+ uint8_t dataMemId; /**< Memory partition ID for data buffers */ -+ uint32_t dataMemAttributes; /**< Memory attributes for data buffers */ -+ t_BufferPoolInfo rxPoolParams; /**< For Rx ports only. */ -+ t_FmPortImRxStoreCallback *f_RxStore; /**< For Rx ports only. */ -+ t_FmPortImTxConfCallback *f_TxConf; /**< For Tx ports only. */ -+} t_FmPortImRxTxParams; -+ -+/**************************************************************************//** -+ @Description A union for additional parameters depending on port type -+*//***************************************************************************/ -+typedef union u_FmPortSpecificParams { -+ t_FmPortImRxTxParams imRxTxParams; /**< Rx/Tx Independent-Mode port parameter structure */ -+ t_FmPortRxParams rxParams; /**< Rx port parameters structure */ -+ t_FmPortNonRxParams nonRxParams; /**< Non-Rx port parameters structure */ -+} u_FmPortSpecificParams; -+ -+/**************************************************************************//** -+ @Description A structure representing FM initialization parameters -+*//***************************************************************************/ -+typedef struct t_FmPortParams { -+ uintptr_t baseAddr; /**< Virtual Address of memory mapped FM Port registers.*/ -+ t_Handle h_Fm; /**< A handle to the FM object this port related to */ -+ e_FmPortType portType; /**< Port type */ -+ uint8_t portId; /**< Port Id - relative to type; -+ NOTE: When configuring Offline Parsing port for -+ FMANv3 devices (DPAA_VERSION 11 and higher), -+ it is highly recommended NOT to use portId=0 due to lack -+ of HW resources on portId=0. */ -+ bool independentModeEnable; -+ /**< This port is Independent-Mode - Used for Rx/Tx ports only! */ -+ uint16_t liodnBase; /**< Irrelevant for P4080 rev 1. LIODN base for this port, to be -+ used together with LIODN offset. */ -+ u_FmPortSpecificParams specificParams; /**< Additional parameters depending on port -+ type. */ -+ -+ t_FmPortExceptionCallback *f_Exception; /**< Relevant for IM only Callback routine to be called on BUSY exception */ -+ t_Handle h_App; /**< A handle to an application layer object; This handle will -+ be passed by the driver upon calling the above callbacks */ -+} t_FmPortParams; -+ -+ -+/**************************************************************************//** -+ @Function FM_PORT_Config -+ -+ @Description Creates a descriptor for the FM PORT module. -+ -+ The routine returns a handle (descriptor) to the FM PORT object. -+ This descriptor must be passed as first parameter to all other -+ FM PORT function calls. -+ -+ No actual initialization or configuration of FM hardware is -+ done by this routine. -+ -+ @Param[in] p_FmPortParams - Pointer to data structure of parameters -+ -+ @Retval Handle to FM object, or NULL for Failure. -+*//***************************************************************************/ -+t_Handle FM_PORT_Config(t_FmPortParams *p_FmPortParams); -+ -+/**************************************************************************//** -+ @Function FM_PORT_Init -+ -+ @Description Initializes the FM PORT module by defining the software structure -+ and configuring the hardware registers. -+ -+ @Param[in] h_FmPort - FM PORT module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_PORT_Init(t_Handle h_FmPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_Free -+ -+ @Description Frees all resources that were assigned to FM PORT module. -+ -+ Calling this routine invalidates the descriptor. -+ -+ @Param[in] h_FmPort - FM PORT module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_PORT_Free(t_Handle h_FmPort); -+ -+ -+/**************************************************************************//** -+ @Group FM_PORT_advanced_init_grp FM Port Advanced Configuration Unit -+ -+ @Description Configuration functions used to change default values. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description enum for defining QM frame dequeue -+*//***************************************************************************/ -+typedef enum e_FmPortDeqType { -+ e_FM_PORT_DEQ_TYPE1, /**< Dequeue from the SP channel - with priority precedence, -+ and Intra-Class Scheduling respected. */ -+ e_FM_PORT_DEQ_TYPE2, /**< Dequeue from the SP channel - with active FQ precedence, -+ and Intra-Class Scheduling respected. */ -+ e_FM_PORT_DEQ_TYPE3 /**< Dequeue from the SP channel - with active FQ precedence, -+ and override Intra-Class Scheduling */ -+} e_FmPortDeqType; -+ -+/**************************************************************************//** -+ @Description enum for defining QM frame dequeue -+*//***************************************************************************/ -+typedef enum e_FmPortDeqPrefetchOption { -+ e_FM_PORT_DEQ_NO_PREFETCH, /**< QMI preforms a dequeue action for a single frame -+ only when a dedicated portID Tnum is waiting. */ -+ e_FM_PORT_DEQ_PARTIAL_PREFETCH, /**< QMI preforms a dequeue action for 3 frames when -+ one dedicated portId tnum is waiting. */ -+ e_FM_PORT_DEQ_FULL_PREFETCH /**< QMI preforms a dequeue action for 3 frames when -+ no dedicated portId tnums are waiting. */ -+ -+} e_FmPortDeqPrefetchOption; -+ -+/**************************************************************************//** -+ @Description enum for defining port default color -+*//***************************************************************************/ -+typedef enum e_FmPortColor { -+ e_FM_PORT_COLOR_GREEN, /**< Default port color is green */ -+ e_FM_PORT_COLOR_YELLOW, /**< Default port color is yellow */ -+ e_FM_PORT_COLOR_RED, /**< Default port color is red */ -+ e_FM_PORT_COLOR_OVERRIDE /**< Ignore color */ -+} e_FmPortColor; -+ -+/**************************************************************************//** -+ @Description A structure for defining Dual Tx rate limiting scale -+*//***************************************************************************/ -+typedef enum e_FmPortDualRateLimiterScaleDown { -+ e_FM_PORT_DUAL_RATE_LIMITER_NONE = 0, /**< Use only single rate limiter */ -+ e_FM_PORT_DUAL_RATE_LIMITER_SCALE_DOWN_BY_2, /**< Divide high rate limiter by 2 */ -+ e_FM_PORT_DUAL_RATE_LIMITER_SCALE_DOWN_BY_4, /**< Divide high rate limiter by 4 */ -+ e_FM_PORT_DUAL_RATE_LIMITER_SCALE_DOWN_BY_8 /**< Divide high rate limiter by 8 */ -+} e_FmPortDualRateLimiterScaleDown; -+ -+ -+/**************************************************************************//** -+ @Description A structure for defining FM port resources -+*//***************************************************************************/ -+typedef struct t_FmPortRsrc { -+ uint32_t num; /**< Committed required resource */ -+ uint32_t extra; /**< Extra (not committed) required resource */ -+} t_FmPortRsrc; -+ -+/**************************************************************************//** -+ @Description A structure for defining observed pool depletion -+*//***************************************************************************/ -+typedef struct t_FmPortObservedBufPoolDepletion { -+ t_FmBufPoolDepletion poolDepletionParams;/**< parameters to define pool depletion */ -+ t_FmExtPools poolsParams; /**< Which external buffer pools are observed -+ (up to FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS), -+ and their sizes. */ -+} t_FmPortObservedBufPoolDepletion; -+ -+/**************************************************************************//** -+ @Description A structure for defining Tx rate limiting -+*//***************************************************************************/ -+typedef struct t_FmPortRateLimit { -+ uint16_t maxBurstSize; /**< in KBytes for Tx ports, in frames -+ for OP ports. (note that -+ for early chips burst size is -+ rounded up to a multiply of 1000 frames).*/ -+ uint32_t rateLimit; /**< in Kb/sec for Tx ports, in frame/sec for -+ OP ports. Rate limit refers to -+ data rate (rather than line rate). */ -+ e_FmPortDualRateLimiterScaleDown rateLimitDivider; /**< For OP ports only. Not-valid -+ for some earlier chip revisions */ -+} t_FmPortRateLimit; -+ -+/**************************************************************************//** -+ @Description A structure for defining the parameters of -+ the Rx port performance counters -+*//***************************************************************************/ -+typedef struct t_FmPortPerformanceCnt { -+ uint8_t taskCompVal; /**< Task compare value */ -+ uint8_t queueCompVal; /**< Rx queue/Tx confirm queue compare -+ value (unused for H/O) */ -+ uint8_t dmaCompVal; /**< Dma compare value */ -+ uint32_t fifoCompVal; /**< Fifo compare value (in bytes) */ -+} t_FmPortPerformanceCnt; -+ -+ -+/**************************************************************************//** -+ @Description A structure for defining the sizes of the Deep Sleep -+ the Auto Response tables -+*//***************************************************************************/ -+typedef struct t_FmPortDsarTablesSizes -+{ -+ uint16_t maxNumOfArpEntries; -+ uint16_t maxNumOfEchoIpv4Entries; -+ uint16_t maxNumOfNdpEntries; -+ uint16_t maxNumOfEchoIpv6Entries; -+ uint16_t maxNumOfSnmpIPV4Entries; -+ uint16_t maxNumOfSnmpIPV6Entries; -+ uint16_t maxNumOfSnmpOidEntries; -+ uint16_t maxNumOfSnmpOidChar; /* total amount of character needed for the snmp table */ -+ -+ uint16_t maxNumOfIpProtFiltering; -+ uint16_t maxNumOfTcpPortFiltering; -+ uint16_t maxNumOfUdpPortFiltering; -+} t_FmPortDsarTablesSizes; -+ -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigDsarSupport -+ -+ @Description This function will allocate the amount of MURAM needed for -+ this max number of entries for Deep Sleep Auto Response. -+ it will calculate all needed MURAM for autoresponse including -+ necesary common stuff. -+ -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] params A pointer to a structure containing the maximum -+ sizes of the auto response tables -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigDsarSupport(t_Handle h_FmPortRx, t_FmPortDsarTablesSizes *params); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigNumOfOpenDmas -+ -+ @Description Calling this routine changes the max number of open DMA's -+ available for this port. It changes this parameter in the -+ internal driver data base from its default configuration -+ [OP: 1] -+ [1G-RX, 1G-TX: 1 (+1)] -+ [10G-RX, 10G-TX: 8 (+8)] -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_OpenDmas A pointer to a structure of parameters defining -+ the open DMA allocation. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigNumOfOpenDmas(t_Handle h_FmPort, t_FmPortRsrc *p_OpenDmas); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigNumOfTasks -+ -+ @Description Calling this routine changes the max number of tasks -+ available for this port. It changes this parameter in the -+ internal driver data base from its default configuration -+ [OP: 1] -+ [1G-RX, 1G-TX: 3 (+2)] -+ [10G-RX, 10G-TX: 16 (+8)] -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_NumOfTasks A pointer to a structure of parameters defining -+ the tasks allocation. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigNumOfTasks(t_Handle h_FmPort, t_FmPortRsrc *p_NumOfTasks); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigSizeOfFifo -+ -+ @Description Calling this routine changes the max FIFO size configured for this port. -+ -+ This function changes the internal driver data base from its -+ default configuration. Please refer to the driver's User Guide for -+ information on default FIFO sizes in the various devices. -+ [OP: 2KB] -+ [1G-RX, 1G-TX: 11KB] -+ [10G-RX, 10G-TX: 12KB] -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_SizeOfFifo A pointer to a structure of parameters defining -+ the FIFO allocation. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigSizeOfFifo(t_Handle h_FmPort, t_FmPortRsrc *p_SizeOfFifo); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigDeqHighPriority -+ -+ @Description Calling this routine changes the dequeue priority in the -+ internal driver data base from its default configuration -+ 1G: [DEFAULT_PORT_deqHighPriority_1G] -+ 10G: [DEFAULT_PORT_deqHighPriority_10G] -+ -+ May be used for Non-Rx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] highPri TRUE to select high priority, FALSE for normal operation. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigDeqHighPriority(t_Handle h_FmPort, bool highPri); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigDeqType -+ -+ @Description Calling this routine changes the dequeue type parameter in the -+ internal driver data base from its default configuration -+ [DEFAULT_PORT_deqType]. -+ -+ May be used for Non-Rx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] deqType According to QM definition. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigDeqType(t_Handle h_FmPort, e_FmPortDeqType deqType); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigDeqPrefetchOption -+ -+ @Description Calling this routine changes the dequeue prefetch option parameter in the -+ internal driver data base from its default configuration -+ [DEFAULT_PORT_deqPrefetchOption] -+ Note: Available for some chips only -+ -+ May be used for Non-Rx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] deqPrefetchOption New option -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigDeqPrefetchOption(t_Handle h_FmPort, e_FmPortDeqPrefetchOption deqPrefetchOption); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigDeqByteCnt -+ -+ @Description Calling this routine changes the dequeue byte count parameter in -+ the internal driver data base from its default configuration -+ 1G:[DEFAULT_PORT_deqByteCnt_1G]. -+ 10G:[DEFAULT_PORT_deqByteCnt_10G]. -+ -+ May be used for Non-Rx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] deqByteCnt New byte count -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigDeqByteCnt(t_Handle h_FmPort, uint16_t deqByteCnt); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigBufferPrefixContent -+ -+ @Description Defines the structure, size and content of the application buffer. -+ The prefix will -+ In Tx ports, if 'passPrsResult', the application -+ should set a value to their offsets in the prefix of -+ the FM will save the first 'privDataSize', than, -+ depending on 'passPrsResult' and 'passTimeStamp', copy parse result -+ and timeStamp, and the packet itself (in this order), to the -+ application buffer, and to offset. -+ Calling this routine changes the buffer margins definitions -+ in the internal driver data base from its default -+ configuration: Data size: [DEFAULT_PORT_bufferPrefixContent_privDataSize] -+ Pass Parser result: [DEFAULT_PORT_bufferPrefixContent_passPrsResult]. -+ Pass timestamp: [DEFAULT_PORT_bufferPrefixContent_passTimeStamp]. -+ -+ May be used for all ports -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in,out] p_FmBufferPrefixContent A structure of parameters describing the -+ structure of the buffer. -+ Out parameter: Start margin - offset -+ of data from start of external buffer. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigBufferPrefixContent(t_Handle h_FmPort, -+ t_FmBufferPrefixContent *p_FmBufferPrefixContent); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigCheksumLastBytesIgnore -+ -+ @Description Calling this routine changes the number of checksum bytes to ignore -+ parameter in the internal driver data base from its default configuration -+ [DEFAULT_PORT_cheksumLastBytesIgnore] -+ -+ May be used by Tx & Rx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] cheksumLastBytesIgnore New value -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigCheksumLastBytesIgnore(t_Handle h_FmPort, uint8_t cheksumLastBytesIgnore); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigCutBytesFromEnd -+ -+ @Description Calling this routine changes the number of bytes to cut from a -+ frame's end parameter in the internal driver data base -+ from its default configuration [DEFAULT_PORT_cutBytesFromEnd] -+ Note that if the result of (frame length before chop - cutBytesFromEnd) is -+ less than 14 bytes, the chop operation is not executed. -+ -+ May be used for Rx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] cutBytesFromEnd New value -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigCutBytesFromEnd(t_Handle h_FmPort, uint8_t cutBytesFromEnd); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigPoolDepletion -+ -+ @Description Calling this routine enables pause frame generation depending on the -+ depletion status of BM pools. It also defines the conditions to activate -+ this functionality. By default, this functionality is disabled. -+ -+ May be used for Rx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_BufPoolDepletion A structure of pool depletion parameters -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigPoolDepletion(t_Handle h_FmPort, t_FmBufPoolDepletion *p_BufPoolDepletion); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigObservedPoolDepletion -+ -+ @Description Calling this routine enables a mechanism to stop port enqueue -+ depending on the depletion status of selected BM pools. -+ It also defines the conditions to activate -+ this functionality. By default, this functionality is disabled. -+ -+ Note: Available for some chips only -+ -+ May be used for OP ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_FmPortObservedBufPoolDepletion A structure of parameters for pool depletion. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigObservedPoolDepletion(t_Handle h_FmPort, -+ t_FmPortObservedBufPoolDepletion *p_FmPortObservedBufPoolDepletion); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigExtBufPools -+ -+ @Description This routine should be called for OP ports -+ that internally use BM buffer pools. In such cases, e.g. for fragmentation and -+ re-assembly, the FM needs new BM buffers. By calling this routine the user -+ specifies the BM buffer pools that should be used. -+ -+ Note: Available for some chips only -+ -+ May be used for OP ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_FmExtPools A structure of parameters for the external pools. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigExtBufPools(t_Handle h_FmPort, t_FmExtPools *p_FmExtPools); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigBackupPools -+ -+ @Description Calling this routine allows the configuration of some of the BM pools -+ defined for this port as backup pools. -+ A pool configured to be a backup pool will be used only if all other -+ enabled non-backup pools are depleted. -+ -+ May be used for Rx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_FmPortBackupBmPools An array of pool id's. All pools specified here will -+ be defined as backup pools. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigBackupPools(t_Handle h_FmPort, t_FmBackupBmPools *p_FmPortBackupBmPools); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigFrmDiscardOverride -+ -+ @Description Calling this routine changes the error frames destination parameter -+ in the internal driver data base from its default configuration: -+ override = [DEFAULT_PORT_frmDiscardOverride] -+ -+ May be used for Rx and OP ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] override TRUE to override discarding of error frames and -+ enqueueing them to error queue. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigFrmDiscardOverride(t_Handle h_FmPort, bool override); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigErrorsToDiscard -+ -+ @Description Calling this routine changes the behaviour on error parameter -+ in the internal driver data base from its default configuration: -+ [DEFAULT_PORT_errorsToDiscard]. -+ If a requested error was previously defined as "ErrorsToEnqueue" it's -+ definition will change and the frame will be discarded. -+ Errors that were not defined either as "ErrorsToEnqueue" nor as -+ "ErrorsToDiscard", will be forwarded to CPU. -+ -+ May be used for Rx and OP ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] errs A list of errors to discard -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigErrorsToDiscard(t_Handle h_FmPort, fmPortFrameErrSelect_t errs); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigDmaSwapData -+ -+ @Description Calling this routine changes the DMA swap data aparameter -+ in the internal driver data base from its default -+ configuration [DEFAULT_PORT_dmaSwapData] -+ -+ May be used for all port types -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] swapData New selection -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigDmaSwapData(t_Handle h_FmPort, e_FmDmaSwapOption swapData); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigDmaIcCacheAttr -+ -+ @Description Calling this routine changes the internal context cache -+ attribute parameter in the internal driver data base -+ from its default configuration [DEFAULT_PORT_dmaIntContextCacheAttr] -+ -+ May be used for all port types -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] intContextCacheAttr New selection -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigDmaIcCacheAttr(t_Handle h_FmPort, e_FmDmaCacheOption intContextCacheAttr); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigDmaHdrAttr -+ -+ @Description Calling this routine changes the header cache -+ attribute parameter in the internal driver data base -+ from its default configuration [DEFAULT_PORT_dmaHeaderCacheAttr] -+ -+ May be used for all port types -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] headerCacheAttr New selection -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigDmaHdrAttr(t_Handle h_FmPort, e_FmDmaCacheOption headerCacheAttr); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigDmaScatterGatherAttr -+ -+ @Description Calling this routine changes the scatter gather cache -+ attribute parameter in the internal driver data base -+ from its default configuration [DEFAULT_PORT_dmaScatterGatherCacheAttr] -+ -+ May be used for all port types -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] scatterGatherCacheAttr New selection -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigDmaScatterGatherAttr(t_Handle h_FmPort, e_FmDmaCacheOption scatterGatherCacheAttr); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigDmaWriteOptimize -+ -+ @Description Calling this routine changes the write optimization -+ parameter in the internal driver data base -+ from its default configuration: By default optimize = [DEFAULT_PORT_dmaWriteOptimize]. -+ Note: -+ -+ 1. For head optimization, data alignment must be >= 16 (supported by default). -+ -+ 3. For tail optimization, note that the optimization is performed by extending the write transaction -+ of the frame payload at the tail as needed to achieve optimal bus transfers, so that the last write -+ is extended to be on 16/64 bytes aligned block (chip dependent). -+ -+ Relevant for non-Tx port types -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] optimize TRUE to enable optimization, FALSE for normal operation -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigDmaWriteOptimize(t_Handle h_FmPort, bool optimize); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigNoScatherGather -+ -+ @Description Calling this routine changes the noScatherGather parameter in internal driver data base -+ from its default configuration. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] noScatherGather (TRUE - frame is discarded if can not be stored in single buffer, -+ FALSE - frame can be stored in scatter gather (S/G) format). -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigNoScatherGather(t_Handle h_FmPort, bool noScatherGather); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigDfltColor -+ -+ @Description Calling this routine changes the internal default color parameter -+ in the internal driver data base -+ from its default configuration [DEFAULT_PORT_color] -+ -+ May be used for all port types -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] color New selection -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigDfltColor(t_Handle h_FmPort, e_FmPortColor color); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigSyncReq -+ -+ @Description Calling this routine changes the synchronization attribute parameter -+ in the internal driver data base from its default configuration: -+ syncReq = [DEFAULT_PORT_syncReq] -+ -+ May be used for all port types -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] syncReq TRUE to request synchronization, FALSE otherwize. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigSyncReq(t_Handle h_FmPort, bool syncReq); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigForwardReuseIntContext -+ -+ @Description This routine is relevant for Rx ports that are routed to OP port. -+ It changes the internal context reuse option in the internal -+ driver data base from its default configuration: -+ reuse = [DEFAULT_PORT_forwardIntContextReuse] -+ -+ May be used for Rx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] reuse TRUE to reuse internal context on frames -+ forwarded to OP port. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigForwardReuseIntContext(t_Handle h_FmPort, bool reuse); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigDontReleaseTxBufToBM -+ -+ @Description This routine should be called if no Tx confirmation -+ is done, and yet buffers should not be released to the BM. -+ Normally, buffers are returned using the Tx confirmation -+ process. When Tx confirmation is not used (defFqid=0), -+ buffers are typically released to the BM. This routine -+ may be called to avoid this behavior and not release the -+ buffers. -+ -+ May be used for Tx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigDontReleaseTxBufToBM(t_Handle h_FmPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigIMMaxRxBufLength -+ -+ @Description Changes the maximum receive buffer length from its default -+ configuration: Closest rounded down power of 2 value of the -+ data buffer size. -+ -+ The maximum receive buffer length directly affects the structure -+ of received frames (single- or multi-buffered) and the performance -+ of both the FM and the driver. -+ -+ The selection between single- or multi-buffered frames should be -+ done according to the characteristics of the specific application. -+ The recommended mode is to use a single data buffer per packet, -+ as this mode provides the best performance. However, the user can -+ select to use multiple data buffers per packet. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] newVal Maximum receive buffer length (in bytes). -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+ This routine is to be used only if Independent-Mode is enabled. -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigIMMaxRxBufLength(t_Handle h_FmPort, uint16_t newVal); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigIMRxBdRingLength -+ -+ @Description Changes the receive BD ring length from its default -+ configuration:[DEFAULT_PORT_rxBdRingLength] -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] newVal The desired BD ring length. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+ This routine is to be used only if Independent-Mode is enabled. -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigIMRxBdRingLength(t_Handle h_FmPort, uint16_t newVal); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigIMTxBdRingLength -+ -+ @Description Changes the transmit BD ring length from its default -+ configuration:[DEFAULT_PORT_txBdRingLength] -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] newVal The desired BD ring length. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+ This routine is to be used only if Independent-Mode is enabled. -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigIMTxBdRingLength(t_Handle h_FmPort, uint16_t newVal); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigIMFmanCtrlExternalStructsMemory -+ -+ @Description Configures memory partition and attributes for FMan-Controller -+ data structures (e.g. BD rings). -+ Calling this routine changes the internal driver data base -+ from its default configuration -+ [DEFAULT_PORT_ImfwExtStructsMemId, DEFAULT_PORT_ImfwExtStructsMemAttr]. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] memId Memory partition ID. -+ @Param[in] memAttributes Memory attributes mask (a combination of MEMORY_ATTR_x flags). -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigIMFmanCtrlExternalStructsMemory(t_Handle h_FmPort, -+ uint8_t memId, -+ uint32_t memAttributes); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigIMPolling -+ -+ @Description Changes the Rx flow from interrupt driven (default) to polling. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+ This routine is to be used only if Independent-Mode is enabled. -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigIMPolling(t_Handle h_FmPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigMaxFrameLength -+ -+ @Description Changes the definition of the max size of frame that should be -+ transmitted/received on this port from its default value [DEFAULT_PORT_maxFrameLength]. -+ This parameter is used for confirmation of the minimum Fifo -+ size calculations and only for Tx ports or ports working in -+ independent mode. This should be larger than the maximum possible -+ MTU that will be used for this port (i.e. its MAC). -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] length Max size of frame -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+ This routine is to be used only if Independent-Mode is enabled. -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigMaxFrameLength(t_Handle h_FmPort, uint16_t length); -+ -+/**************************************************************************//* -+ @Function FM_PORT_ConfigTxFifoMinFillLevel -+ -+ @Description Calling this routine changes the fifo minimum -+ fill level parameter in the internal driver data base -+ from its default configuration [DEFAULT_PORT_txFifoMinFillLevel] -+ -+ May be used for Tx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] minFillLevel New value -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigTxFifoMinFillLevel(t_Handle h_FmPort, uint32_t minFillLevel); -+ -+/**************************************************************************//* -+ @Function FM_PORT_ConfigFifoDeqPipelineDepth -+ -+ @Description Calling this routine changes the fifo dequeue -+ pipeline depth parameter in the internal driver data base -+ -+ from its default configuration: 1G ports: [DEFAULT_PORT_fifoDeqPipelineDepth_1G], -+ 10G port: [DEFAULT_PORT_fifoDeqPipelineDepth_10G], -+ OP port: [DEFAULT_PORT_fifoDeqPipelineDepth_OH] -+ -+ May be used for Tx/OP ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] deqPipelineDepth New value -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigFifoDeqPipelineDepth(t_Handle h_FmPort, uint8_t deqPipelineDepth); -+ -+/**************************************************************************//* -+ @Function FM_PORT_ConfigTxFifoLowComfLevel -+ -+ @Description Calling this routine changes the fifo low comfort level -+ parameter in internal driver data base -+ from its default configuration [DEFAULT_PORT_txFifoLowComfLevel] -+ -+ May be used for Tx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] fifoLowComfLevel New value -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigTxFifoLowComfLevel(t_Handle h_FmPort, uint32_t fifoLowComfLevel); -+ -+/**************************************************************************//* -+ @Function FM_PORT_ConfigRxFifoThreshold -+ -+ @Description Calling this routine changes the threshold of the FIFO -+ fill level parameter in the internal driver data base -+ from its default configuration [DEFAULT_PORT_rxFifoThreshold] -+ -+ If the total number of buffers which are -+ currently in use and associated with the -+ specific RX port exceed this threshold, the -+ BMI will signal the MAC to send a pause frame -+ over the link. -+ -+ May be used for Rx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] fifoThreshold New value -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigRxFifoThreshold(t_Handle h_FmPort, uint32_t fifoThreshold); -+ -+/**************************************************************************//* -+ @Function FM_PORT_ConfigRxFifoPriElevationLevel -+ -+ @Description Calling this routine changes the priority elevation level -+ parameter in the internal driver data base from its default -+ configuration [DEFAULT_PORT_rxFifoPriElevationLevel] -+ -+ If the total number of buffers which are currently in use and -+ associated with the specific RX port exceed the amount specified -+ in priElevationLevel, BMI will signal the main FM's DMA to -+ elevate the FM priority on the system bus. -+ -+ May be used for Rx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] priElevationLevel New value -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigRxFifoPriElevationLevel(t_Handle h_FmPort, uint32_t priElevationLevel); -+ -+#ifdef FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 -+/**************************************************************************//* -+ @Function FM_PORT_ConfigBCBWorkaround -+ -+ @Description Configures BCB errata workaround. -+ -+ When BCB errata is applicable, the workaround is always -+ performed by FM Controller. Thus, this functions doesn't -+ actually enable errata workaround but rather allows driver -+ to perform adjustments required due to errata workaround -+ execution in FM controller. -+ -+ Applying BCB workaround also configures FM_PORT_FRM_ERR_PHYSICAL -+ errors to be discarded. Thus FM_PORT_FRM_ERR_PHYSICAL can't be -+ set by FM_PORT_SetErrorsRoute() function. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigBCBWorkaround(t_Handle h_FmPort); -+#endif /* FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 */ -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//* -+ @Function FM_PORT_ConfigInternalBuffOffset -+ -+ @Description Configures internal buffer offset. -+ -+ May be used for Rx and OP ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] val New value -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ConfigInternalBuffOffset(t_Handle h_FmPort, uint8_t val); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/** @} */ /* end of FM_PORT_advanced_init_grp group */ -+/** @} */ /* end of FM_PORT_init_grp group */ -+ -+ -+/**************************************************************************//** -+ @Group FM_PORT_runtime_control_grp FM Port Runtime Control Unit -+ -+ @Description FM Port Runtime control unit API functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description enum for defining FM Port counters -+*//***************************************************************************/ -+typedef enum e_FmPortCounters { -+ e_FM_PORT_COUNTERS_CYCLE, /**< BMI performance counter */ -+ e_FM_PORT_COUNTERS_TASK_UTIL, /**< BMI performance counter */ -+ e_FM_PORT_COUNTERS_QUEUE_UTIL, /**< BMI performance counter */ -+ e_FM_PORT_COUNTERS_DMA_UTIL, /**< BMI performance counter */ -+ e_FM_PORT_COUNTERS_FIFO_UTIL, /**< BMI performance counter */ -+ e_FM_PORT_COUNTERS_RX_PAUSE_ACTIVATION, /**< BMI Rx only performance counter */ -+ e_FM_PORT_COUNTERS_FRAME, /**< BMI statistics counter */ -+ e_FM_PORT_COUNTERS_DISCARD_FRAME, /**< BMI statistics counter */ -+ e_FM_PORT_COUNTERS_DEALLOC_BUF, /**< BMI deallocate buffer statistics counter */ -+ e_FM_PORT_COUNTERS_RX_BAD_FRAME, /**< BMI Rx only statistics counter */ -+ e_FM_PORT_COUNTERS_RX_LARGE_FRAME, /**< BMI Rx only statistics counter */ -+ e_FM_PORT_COUNTERS_RX_FILTER_FRAME, /**< BMI Rx & OP only statistics counter */ -+ e_FM_PORT_COUNTERS_RX_LIST_DMA_ERR, /**< BMI Rx, OP & HC only statistics counter */ -+ e_FM_PORT_COUNTERS_RX_OUT_OF_BUFFERS_DISCARD, /**< BMI Rx, OP & HC statistics counter */ -+ e_FM_PORT_COUNTERS_PREPARE_TO_ENQUEUE_COUNTER, /**< BMI Rx, OP & HC only statistics counter */ -+ e_FM_PORT_COUNTERS_WRED_DISCARD, /**< BMI OP & HC only statistics counter */ -+ e_FM_PORT_COUNTERS_LENGTH_ERR, /**< BMI non-Rx statistics counter */ -+ e_FM_PORT_COUNTERS_UNSUPPRTED_FORMAT, /**< BMI non-Rx statistics counter */ -+ e_FM_PORT_COUNTERS_DEQ_TOTAL, /**< QMI total QM dequeues counter */ -+ e_FM_PORT_COUNTERS_ENQ_TOTAL, /**< QMI total QM enqueues counter */ -+ e_FM_PORT_COUNTERS_DEQ_FROM_DEFAULT, /**< QMI counter */ -+ e_FM_PORT_COUNTERS_DEQ_CONFIRM /**< QMI counter */ -+} e_FmPortCounters; -+ -+typedef struct t_FmPortBmiStats { -+ uint32_t cntCycle; -+ uint32_t cntTaskUtil; -+ uint32_t cntQueueUtil; -+ uint32_t cntDmaUtil; -+ uint32_t cntFifoUtil; -+ uint32_t cntRxPauseActivation; -+ uint32_t cntFrame; -+ uint32_t cntDiscardFrame; -+ uint32_t cntDeallocBuf; -+ uint32_t cntRxBadFrame; -+ uint32_t cntRxLargeFrame; -+ uint32_t cntRxFilterFrame; -+ uint32_t cntRxListDmaErr; -+ uint32_t cntRxOutOfBuffersDiscard; -+ uint32_t cntWredDiscard; -+ uint32_t cntLengthErr; -+ uint32_t cntUnsupportedFormat; -+} t_FmPortBmiStats; -+ -+/**************************************************************************//** -+ @Description Structure for Port id parameters. -+ Fields commented 'IN' are passed by the port module to be used -+ by the FM module. -+ Fields commented 'OUT' will be filled by FM before returning to port. -+*//***************************************************************************/ -+typedef struct t_FmPortCongestionGrps { -+ uint16_t numOfCongestionGrpsToConsider; /**< The number of required CGs -+ to define the size of the following array */ -+ uint8_t congestionGrpsToConsider[FM_PORT_NUM_OF_CONGESTION_GRPS]; -+ /**< An array of CG indexes; -+ Note that the size of the array should be -+ 'numOfCongestionGrpsToConsider'. */ -+#if (DPAA_VERSION >= 11) -+ bool pfcPrioritiesEn[FM_PORT_NUM_OF_CONGESTION_GRPS][FM_MAX_NUM_OF_PFC_PRIORITIES]; -+ /**< a matrix that represents the map between the CG ids -+ defined in 'congestionGrpsToConsider' to the priorties -+ mapping array. */ -+#endif /* (DPAA_VERSION >= 11) */ -+} t_FmPortCongestionGrps; -+ -+/**************************************************************************//** -+ @Description Structure for Deep Sleep Auto Response ARP Entry -+*//***************************************************************************/ -+typedef struct t_FmPortDsarArpEntry -+{ -+ uint32_t ipAddress; -+ uint8_t mac[6]; -+ bool isVlan; -+ uint16_t vid; -+} t_FmPortDsarArpEntry; -+ -+/**************************************************************************//** -+ @Description Structure for Deep Sleep Auto Response ARP info -+*//***************************************************************************/ -+typedef struct t_FmPortDsarArpInfo -+{ -+ uint8_t tableSize; -+ t_FmPortDsarArpEntry *p_AutoResTable; -+ bool enableConflictDetection; /* when TRUE Conflict Detection will be checked and wake the host if needed */ -+} t_FmPortDsarArpInfo; -+ -+/**************************************************************************//** -+ @Description Structure for Deep Sleep Auto Response NDP Entry -+*//***************************************************************************/ -+typedef struct t_FmPortDsarNdpEntry -+{ -+ uint32_t ipAddress[4]; -+ uint8_t mac[6]; -+ bool isVlan; -+ uint16_t vid; -+} t_FmPortDsarNdpEntry; -+ -+/**************************************************************************//** -+ @Description Structure for Deep Sleep Auto Response NDP info -+*//***************************************************************************/ -+typedef struct t_FmPortDsarNdpInfo -+{ -+ uint32_t multicastGroup; -+ -+ uint8_t tableSizeAssigned; -+ t_FmPortDsarNdpEntry *p_AutoResTableAssigned; /* This list refer to solicitation IP addresses. -+ Note that all IP adresses must be from the same multicast group. -+ This will be checked and if not operation will fail. */ -+ uint8_t tableSizeTmp; -+ t_FmPortDsarNdpEntry *p_AutoResTableTmp; /* This list refer to temp IP addresses. -+ Note that all temp IP adresses must be from the same multicast group. -+ This will be checked and if not operation will fail. */ -+ -+ bool enableConflictDetection; /* when TRUE Conflict Detection will be checked and wake the host if needed */ -+ -+} t_FmPortDsarNdpInfo; -+ -+/**************************************************************************//** -+ @Description Structure for Deep Sleep Auto Response ICMPV4 info -+*//***************************************************************************/ -+typedef struct t_FmPortDsarEchoIpv4Info -+{ -+ uint8_t tableSize; -+ t_FmPortDsarArpEntry *p_AutoResTable; -+} t_FmPortDsarEchoIpv4Info; -+ -+/**************************************************************************//** -+ @Description Structure for Deep Sleep Auto Response ICMPV6 info -+*//***************************************************************************/ -+typedef struct t_FmPortDsarEchoIpv6Info -+{ -+ uint8_t tableSize; -+ t_FmPortDsarNdpEntry *p_AutoResTable; -+} t_FmPortDsarEchoIpv6Info; -+ -+/**************************************************************************//** -+@Description Deep Sleep Auto Response SNMP OIDs table entry -+ -+*//***************************************************************************/ -+typedef struct { -+ uint16_t oidSize; -+ uint8_t *oidVal; /* only the oid string */ -+ uint16_t resSize; -+ uint8_t *resVal; /* resVal will be the entire reply, -+ i.e. "Type|Length|Value" */ -+} t_FmPortDsarOidsEntry; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response SNMP IPv4 Addresses Table Entry -+ Refer to the FMan Controller spec for more details. -+*//***************************************************************************/ -+typedef struct -+{ -+ uint32_t ipv4Addr; /*!< 32 bit IPv4 Address. */ -+ bool isVlan; -+ uint16_t vid; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */ -+ /*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */ -+} t_FmPortDsarSnmpIpv4AddrTblEntry; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response SNMP IPv6 Addresses Table Entry -+ Refer to the FMan Controller spec for more details. -+*//***************************************************************************/ -+typedef struct -+{ -+ uint32_t ipv6Addr[4]; /*!< 4 * 32 bit IPv6 Address. */ -+ bool isVlan; -+ uint16_t vid; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */ -+ /*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */ -+} t_FmPortDsarSnmpIpv6AddrTblEntry; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response SNMP Descriptor -+ -+*//***************************************************************************/ -+typedef struct -+{ -+ uint16_t control; /**< Control bits [0-15]. */ -+ uint16_t maxSnmpMsgLength; /**< Maximal allowed SNMP message length. */ -+ uint16_t numOfIpv4Addresses; /**< Number of entries in IPv4 addresses table. */ -+ uint16_t numOfIpv6Addresses; /**< Number of entries in IPv6 addresses table. */ -+ t_FmPortDsarSnmpIpv4AddrTblEntry *p_Ipv4AddrTbl; /**< Pointer to IPv4 addresses table. */ -+ t_FmPortDsarSnmpIpv6AddrTblEntry *p_Ipv6AddrTbl; /**< Pointer to IPv6 addresses table. */ -+ uint8_t *p_RdOnlyCommunityStr; /**< Pointer to the Read Only Community String. */ -+ uint8_t *p_RdWrCommunityStr; /**< Pointer to the Read Write Community String. */ -+ t_FmPortDsarOidsEntry *p_OidsTbl; /**< Pointer to OIDs table. */ -+ uint32_t oidsTblSize; /**< Number of entries in OIDs table. */ -+} t_FmPortDsarSnmpInfo; -+ -+/**************************************************************************//** -+ @Description Structure for Deep Sleep Auto Response filtering Entry -+*//***************************************************************************/ -+typedef struct t_FmPortDsarFilteringEntry -+{ -+ uint16_t srcPort; -+ uint16_t dstPort; -+ uint16_t srcPortMask; -+ uint16_t dstPortMask; -+} t_FmPortDsarFilteringEntry; -+ -+/**************************************************************************//** -+ @Description Structure for Deep Sleep Auto Response filtering info -+*//***************************************************************************/ -+typedef struct t_FmPortDsarFilteringInfo -+{ -+ /* IP protocol filtering parameters */ -+ uint8_t ipProtTableSize; -+ uint8_t *p_IpProtTablePtr; -+ bool ipProtPassOnHit; /* when TRUE, miss in the table will cause the packet to be droped, -+ hit will pass the packet to UDP/TCP filters if needed and if not -+ to the classification tree. If the classification tree will pass -+ the packet to a queue it will cause a wake interupt. -+ When FALSE it the other way around. */ -+ /* UDP port filtering parameters */ -+ uint8_t udpPortsTableSize; -+ t_FmPortDsarFilteringEntry *p_UdpPortsTablePtr; -+ bool udpPortPassOnHit; /* when TRUE, miss in the table will cause the packet to be droped, -+ hit will pass the packet to classification tree. -+ If the classification tree will pass the packet to a queue it -+ will cause a wake interupt. -+ When FALSE it the other way around. */ -+ /* TCP port filtering parameters */ -+ uint16_t tcpFlagsMask; -+ uint8_t tcpPortsTableSize; -+ t_FmPortDsarFilteringEntry *p_TcpPortsTablePtr; -+ bool tcpPortPassOnHit; /* when TRUE, miss in the table will cause the packet to be droped, -+ hit will pass the packet to classification tree. -+ If the classification tree will pass the packet to a queue it -+ will cause a wake interupt. -+ When FALSE it the other way around. */ -+} t_FmPortDsarFilteringInfo; -+ -+/**************************************************************************//** -+ @Description Structure for Deep Sleep Auto Response parameters -+*//***************************************************************************/ -+typedef struct t_FmPortDsarParams -+{ -+ t_Handle h_FmPortTx; -+ t_FmPortDsarArpInfo *p_AutoResArpInfo; -+ t_FmPortDsarEchoIpv4Info *p_AutoResEchoIpv4Info; -+ t_FmPortDsarNdpInfo *p_AutoResNdpInfo; -+ t_FmPortDsarEchoIpv6Info *p_AutoResEchoIpv6Info; -+ t_FmPortDsarSnmpInfo *p_AutoResSnmpInfo; -+ t_FmPortDsarFilteringInfo *p_AutoResFilteringInfo; -+} t_FmPortDsarParams; -+ -+/**************************************************************************//** -+ @Function FM_PORT_EnterDsar -+ -+ @Description Enter Deep Sleep Auto Response mode. -+ This function write the apropriate values to in the relevant -+ tables in the MURAM. -+ -+ @Param[in] h_FmPortRx - FM PORT module descriptor -+ @Param[in] params - Auto Response parameters -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_EnterDsar(t_Handle h_FmPortRx, t_FmPortDsarParams *params); -+ -+/**************************************************************************//** -+ @Function FM_PORT_EnterDsarFinal -+ -+ @Description Enter Deep Sleep Auto Response mode. -+ This function sets the Tx port in independent mode as needed -+ and redirect the receive flow to go through the -+ Dsar Fman-ctrl code -+ -+ @Param[in] h_DsarRxPort - FM Rx PORT module descriptor -+ @Param[in] h_DsarTxPort - FM Tx PORT module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_EnterDsarFinal(t_Handle h_DsarRxPort, t_Handle h_DsarTxPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ExitDsar -+ -+ @Description Exit Deep Sleep Auto Response mode. -+ This function reverse the AR mode and put the ports back into -+ their original wake mode -+ -+ @Param[in] h_FmPortRx - FM PORT Rx module descriptor -+ @Param[in] h_FmPortTx - FM PORT Tx module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_EnterDsar(). -+*//***************************************************************************/ -+void FM_PORT_ExitDsar(t_Handle h_FmPortRx, t_Handle h_FmPortTx); -+ -+/**************************************************************************//** -+ @Function FM_PORT_IsInDsar -+ -+ @Description This function returns TRUE if the port was set as Auto Response -+ and FALSE if not. Once Exit AR mode it will return FALSE as well -+ until re-enabled once more. -+ -+ @Param[in] h_FmPort - FM PORT module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+bool FM_PORT_IsInDsar(t_Handle h_FmPort); -+ -+typedef struct t_FmPortDsarStats -+{ -+ uint32_t arpArCnt; -+ uint32_t echoIcmpv4ArCnt; -+ uint32_t ndpArCnt; -+ uint32_t echoIcmpv6ArCnt; -+ uint32_t snmpGetCnt; -+ uint32_t snmpGetNextCnt; -+} t_FmPortDsarStats; -+ -+/**************************************************************************//** -+ @Function FM_PORT_GetDsarStats -+ -+ @Description Return statistics for Deep Sleep Auto Response -+ -+ @Param[in] h_FmPortRx - FM PORT module descriptor -+ @Param[out] stats - structure containing the statistics counters -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_PORT_GetDsarStats(t_Handle h_FmPortRx, t_FmPortDsarStats *stats); -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+/**************************************************************************//** -+ @Function FM_PORT_DumpRegs -+ -+ @Description Dump all regs. -+ -+ Calling this routine invalidates the descriptor. -+ -+ @Param[in] h_FmPort - FM PORT module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_DumpRegs(t_Handle h_FmPort); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+/**************************************************************************//** -+ @Function FM_PORT_GetBufferDataOffset -+ -+ @Description Relevant for Rx ports. -+ Returns the data offset from the beginning of the data buffer -+ -+ @Param[in] h_FmPort - FM PORT module descriptor -+ -+ @Return data offset. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+uint32_t FM_PORT_GetBufferDataOffset(t_Handle h_FmPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_GetBufferICInfo -+ -+ @Description Returns the Internal Context offset from the beginning of the data buffer -+ -+ @Param[in] h_FmPort - FM PORT module descriptor -+ @Param[in] p_Data - A pointer to the data buffer. -+ -+ @Return Internal context info pointer on success, NULL if 'allOtherInfo' was not -+ configured for this port. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+uint8_t * FM_PORT_GetBufferICInfo(t_Handle h_FmPort, char *p_Data); -+ -+/**************************************************************************//** -+ @Function FM_PORT_GetBufferPrsResult -+ -+ @Description Returns the pointer to the parse result in the data buffer. -+ In Rx ports this is relevant after reception, if parse -+ result is configured to be part of the data passed to the -+ application. For non Rx ports it may be used to get the pointer -+ of the area in the buffer where parse result should be -+ initialized - if so configured. -+ See FM_PORT_ConfigBufferPrefixContent for data buffer prefix -+ configuration. -+ -+ @Param[in] h_FmPort - FM PORT module descriptor -+ @Param[in] p_Data - A pointer to the data buffer. -+ -+ @Return Parse result pointer on success, NULL if parse result was not -+ configured for this port. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_FmPrsResult * FM_PORT_GetBufferPrsResult(t_Handle h_FmPort, char *p_Data); -+ -+/**************************************************************************//** -+ @Function FM_PORT_GetBufferTimeStamp -+ -+ @Description Returns the time stamp in the data buffer. -+ Relevant for Rx ports for getting the buffer time stamp. -+ See FM_PORT_ConfigBufferPrefixContent for data buffer prefix -+ configuration. -+ -+ @Param[in] h_FmPort - FM PORT module descriptor -+ @Param[in] p_Data - A pointer to the data buffer. -+ -+ @Return A pointer to the hash result on success, NULL otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+uint64_t * FM_PORT_GetBufferTimeStamp(t_Handle h_FmPort, char *p_Data); -+ -+/**************************************************************************//** -+ @Function FM_PORT_GetBufferHashResult -+ -+ @Description Given a data buffer, on the condition that hash result was defined -+ as a part of the buffer content (see FM_PORT_ConfigBufferPrefixContent) -+ this routine will return the pointer to the hash result location in the -+ buffer prefix. -+ -+ @Param[in] h_FmPort - FM PORT module descriptor -+ @Param[in] p_Data - A pointer to the data buffer. -+ -+ @Return A pointer to the hash result on success, NULL otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+uint8_t * FM_PORT_GetBufferHashResult(t_Handle h_FmPort, char *p_Data); -+ -+/**************************************************************************//** -+ @Function FM_PORT_Disable -+ -+ @Description Gracefully disable an FM port. The port will not start new tasks after all -+ tasks associated with the port are terminated. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+ This is a blocking routine, it returns after port is -+ gracefully stopped, i.e. the port will not except new frames, -+ but it will finish all frames or tasks which were already began -+*//***************************************************************************/ -+t_Error FM_PORT_Disable(t_Handle h_FmPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_Enable -+ -+ @Description A runtime routine provided to allow disable/enable of port. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_Enable(t_Handle h_FmPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_SetRateLimit -+ -+ @Description Calling this routine enables rate limit algorithm. -+ By default, this functionality is disabled. -+ Note that rate-limit mechanism uses the FM time stamp. -+ The selected rate limit specified here would be -+ rounded DOWN to the nearest 16M. -+ -+ May be used for Tx and OP ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_RateLimit A structure of rate limit parameters -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+ If rate limit is set on a port that need to send PFC frames, -+ it might violate the stop transmit timing. -+*//***************************************************************************/ -+t_Error FM_PORT_SetRateLimit(t_Handle h_FmPort, t_FmPortRateLimit *p_RateLimit); -+ -+/**************************************************************************//** -+ @Function FM_PORT_DeleteRateLimit -+ -+ @Description Calling this routine disables and clears rate limit -+ initialization. -+ -+ May be used for Tx and OP ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_DeleteRateLimit(t_Handle h_FmPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_SetPfcPrioritiesMappingToQmanWQ -+ -+ @Description Calling this routine maps each PFC received priority to the transmit WQ. -+ This WQ will be blocked upon receiving a PFC frame with this priority. -+ -+ May be used for Tx ports only. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] prio PFC priority (0-7). -+ @Param[in] wq Work Queue (0-7). -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_SetPfcPrioritiesMappingToQmanWQ(t_Handle h_FmPort, uint8_t prio, uint8_t wq); -+ -+/**************************************************************************//** -+ @Function FM_PORT_SetStatisticsCounters -+ -+ @Description Calling this routine enables/disables port's statistics counters. -+ By default, counters are enabled. -+ -+ May be used for all port types -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] enable TRUE to enable, FALSE to disable. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_SetStatisticsCounters(t_Handle h_FmPort, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_PORT_SetFrameQueueCounters -+ -+ @Description Calling this routine enables/disables port's enqueue/dequeue counters. -+ By default, counters are enabled. -+ -+ May be used for all ports -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] enable TRUE to enable, FALSE to disable. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_SetFrameQueueCounters(t_Handle h_FmPort, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_PORT_AnalyzePerformanceParams -+ -+ @Description User may call this routine to so the driver will analyze if the -+ basic performance parameters are correct and also the driver may -+ suggest of improvements; The basic parameters are FIFO sizes, number -+ of DMAs and number of TNUMs for the port. -+ -+ May be used for all port types -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_AnalyzePerformanceParams(t_Handle h_FmPort); -+ -+ -+/**************************************************************************//** -+ @Function FM_PORT_SetAllocBufCounter -+ -+ @Description Calling this routine enables/disables BM pool allocate -+ buffer counters. -+ By default, counters are enabled. -+ -+ May be used for Rx ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] poolId BM pool id. -+ @Param[in] enable TRUE to enable, FALSE to disable. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_SetAllocBufCounter(t_Handle h_FmPort, uint8_t poolId, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_PORT_GetBmiCounters -+ -+ @Description Read port's BMI stat counters and place them into -+ a designated structure of counters. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[out] p_BmiStats counters structure -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_GetBmiCounters(t_Handle h_FmPort, t_FmPortBmiStats *p_BmiStats); -+ -+/**************************************************************************//** -+ @Function FM_PORT_GetCounter -+ -+ @Description Reads one of the FM PORT counters. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] fmPortCounter The requested counter. -+ -+ @Return Counter's current value. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+ Note that it is user's responsibility to call this routine only -+ for enabled counters, and there will be no indication if a -+ disabled counter is accessed. -+*//***************************************************************************/ -+uint32_t FM_PORT_GetCounter(t_Handle h_FmPort, e_FmPortCounters fmPortCounter); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ModifyCounter -+ -+ @Description Sets a value to an enabled counter. Use "0" to reset the counter. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] fmPortCounter The requested counter. -+ @Param[in] value The requested value to be written into the counter. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ModifyCounter(t_Handle h_FmPort, e_FmPortCounters fmPortCounter, uint32_t value); -+ -+/**************************************************************************//** -+ @Function FM_PORT_GetAllocBufCounter -+ -+ @Description Reads one of the FM PORT buffer counters. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] poolId The requested pool. -+ -+ @Return Counter's current value. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+ Note that it is user's responsibility to call this routine only -+ for enabled counters, and there will be no indication if a -+ disabled counter is accessed. -+*//***************************************************************************/ -+uint32_t FM_PORT_GetAllocBufCounter(t_Handle h_FmPort, uint8_t poolId); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ModifyAllocBufCounter -+ -+ @Description Sets a value to an enabled counter. Use "0" to reset the counter. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] poolId The requested pool. -+ @Param[in] value The requested value to be written into the counter. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ModifyAllocBufCounter(t_Handle h_FmPort, uint8_t poolId, uint32_t value); -+ -+/**************************************************************************//** -+ @Function FM_PORT_AddCongestionGrps -+ -+ @Description This routine effects the corresponding Tx port. -+ It should be called in order to enable pause -+ frame transmission in case of congestion in one or more -+ of the congestion groups relevant to this port. -+ Each call to this routine may add one or more congestion -+ groups to be considered relevant to this port. -+ -+ May be used for Rx, or RX+OP ports only (depending on chip) -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_CongestionGrps A pointer to an array of congestion groups -+ id's to consider. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_AddCongestionGrps(t_Handle h_FmPort, t_FmPortCongestionGrps *p_CongestionGrps); -+ -+/**************************************************************************//** -+ @Function FM_PORT_RemoveCongestionGrps -+ -+ @Description This routine effects the corresponding Tx port. It should be -+ called when congestion groups were -+ defined for this port and are no longer relevant, or pause -+ frames transmitting is not required on their behalf. -+ Each call to this routine may remove one or more congestion -+ groups to be considered relevant to this port. -+ -+ May be used for Rx, or RX+OP ports only (depending on chip) -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_CongestionGrps A pointer to an array of congestion groups -+ id's to consider. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_RemoveCongestionGrps(t_Handle h_FmPort, t_FmPortCongestionGrps *p_CongestionGrps); -+ -+/**************************************************************************//** -+ @Function FM_PORT_IsStalled -+ -+ @Description A routine for checking whether the specified port is stalled. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return TRUE if port is stalled, FALSE otherwize -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+bool FM_PORT_IsStalled(t_Handle h_FmPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ReleaseStalled -+ -+ @Description This routine may be called in case the port was stalled and may -+ now be released. -+ Note that this routine is available only on older FMan revisions -+ (FMan v2, DPAA v1.0 only). -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_ReleaseStalled(t_Handle h_FmPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_SetRxL4ChecksumVerify -+ -+ @Description This routine is relevant for Rx ports (1G and 10G). The routine -+ set/clear the L3/L4 checksum verification (on RX side). -+ Note that this takes affect only if hw-parser is enabled! -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] l4Checksum boolean indicates whether to do L3/L4 checksum -+ on frames or not. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_SetRxL4ChecksumVerify(t_Handle h_FmPort, bool l4Checksum); -+ -+/**************************************************************************//** -+ @Function FM_PORT_SetErrorsRoute -+ -+ @Description Errors selected for this routine will cause a frame with that error -+ to be enqueued to error queue. -+ Errors not selected for this routine will cause a frame with that error -+ to be enqueued to the one of the other port queues. -+ By default all errors are defined to be enqueued to error queue. -+ Errors that were configured to be discarded (at initialization) -+ may not be selected here. -+ -+ May be used for Rx and OP ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] errs A list of errors to enqueue to error queue -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_SetErrorsRoute(t_Handle h_FmPort, fmPortFrameErrSelect_t errs); -+ -+/**************************************************************************//** -+ @Function FM_PORT_SetIMExceptions -+ -+ @Description Calling this routine enables/disables FM PORT interrupts. -+ -+ @Param[in] h_FmPort FM PORT module descriptor. -+ @Param[in] exception The exception to be selected. -+ @Param[in] enable TRUE to enable interrupt, FALSE to mask it. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+ This routine should NOT be called from guest-partition -+ (i.e. guestId != NCSW_MASTER_ID) -+*//***************************************************************************/ -+t_Error FM_PORT_SetIMExceptions(t_Handle h_FmPort, e_FmPortExceptions exception, bool enable); -+ -+/**************************************************************************//* -+ @Function FM_PORT_SetPerformanceCounters -+ -+ @Description Calling this routine enables/disables port's performance counters. -+ By default, counters are enabled. -+ -+ May be used for all port types -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] enable TRUE to enable, FALSE to disable. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_SetPerformanceCounters(t_Handle h_FmPort, bool enable); -+ -+/**************************************************************************//* -+ @Function FM_PORT_SetPerformanceCountersParams -+ -+ @Description Calling this routine defines port's performance -+ counters parameters. -+ -+ May be used for all port types -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_FmPortPerformanceCnt A pointer to a structure of performance -+ counters parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_SetPerformanceCountersParams(t_Handle h_FmPort, t_FmPortPerformanceCnt *p_FmPortPerformanceCnt); -+ -+/**************************************************************************//** -+ @Group FM_PORT_pcd_runtime_control_grp FM Port PCD Runtime Control Unit -+ -+ @Description FM Port PCD Runtime control unit API functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description A structure defining the KG scheme after the parser. -+ This is relevant only to change scheme selection mode - from -+ direct to indirect and vice versa, or when the scheme is selected directly, -+ to select the scheme id. -+ -+*//***************************************************************************/ -+typedef struct t_FmPcdKgSchemeSelect { -+ bool direct; /**< TRUE to use 'h_Scheme' directly, FALSE to use LCV. */ -+ t_Handle h_DirectScheme; /**< Scheme handle, selects the scheme after parser; -+ Relevant only when 'direct' is TRUE. */ -+} t_FmPcdKgSchemeSelect; -+ -+/**************************************************************************//** -+ @Description A structure of scheme parameters -+*//***************************************************************************/ -+typedef struct t_FmPcdPortSchemesParams { -+ uint8_t numOfSchemes; /**< Number of schemes for port to be bound to. */ -+ t_Handle h_Schemes[FM_PCD_KG_NUM_OF_SCHEMES]; /**< Array of 'numOfSchemes' schemes for the -+ port to be bound to */ -+} t_FmPcdPortSchemesParams; -+ -+/**************************************************************************//** -+ @Description Union for defining port protocol parameters for parser -+*//***************************************************************************/ -+typedef union u_FmPcdHdrPrsOpts { -+ /* MPLS */ -+ struct { -+ bool labelInterpretationEnable; /**< When this bit is set, the last MPLS label will be -+ interpreted as described in HW spec table. When the bit -+ is cleared, the parser will advance to MPLS next parse */ -+ e_NetHeaderType nextParse; /**< must be equal or higher than IPv4 */ -+ } mplsPrsOptions; -+ /* VLAN */ -+ struct { -+ uint16_t tagProtocolId1; /**< User defined Tag Protocol Identifier, to be recognized -+ on VLAN TAG on top of 0x8100 and 0x88A8 */ -+ uint16_t tagProtocolId2; /**< User defined Tag Protocol Identifier, to be recognized -+ on VLAN TAG on top of 0x8100 and 0x88A8 */ -+ } vlanPrsOptions; -+ /* PPP */ -+ struct{ -+ bool enableMTUCheck; /**< Check validity of MTU according to RFC2516 */ -+ } pppoePrsOptions; -+ -+ /* IPV6 */ -+ struct{ -+ bool routingHdrEnable; /**< TRUE to enable routing header, otherwise ignore */ -+ } ipv6PrsOptions; -+ -+ /* UDP */ -+ struct{ -+ bool padIgnoreChecksum; /**< TRUE to ignore pad in checksum */ -+ } udpPrsOptions; -+ -+ /* TCP */ -+ struct { -+ bool padIgnoreChecksum; /**< TRUE to ignore pad in checksum */ -+ } tcpPrsOptions; -+} u_FmPcdHdrPrsOpts; -+ -+/**************************************************************************//** -+ @Description A structure for defining each header for the parser -+*//***************************************************************************/ -+typedef struct t_FmPcdPrsAdditionalHdrParams { -+ e_NetHeaderType hdr; /**< Selected header; use HEADER_TYPE_NONE -+ to indicate that sw parser is to run first -+ (before HW parser, and independent of the -+ existence of any protocol), in this case, -+ swPrsEnable must be set, and all other -+ parameters are irrelevant. */ -+ bool errDisable; /**< TRUE to disable error indication */ -+ bool swPrsEnable; /**< Enable jump to SW parser when this -+ header is recognized by the HW parser. */ -+ uint8_t indexPerHdr; /**< Normally 0, if more than one sw parser -+ attachments exists for the same header, -+ (in the main sw parser code) use this -+ index to distinguish between them. */ -+ bool usePrsOpts; /**< TRUE to use parser options. */ -+ u_FmPcdHdrPrsOpts prsOpts; /**< A union according to header type, -+ defining the parser options selected.*/ -+} t_FmPcdPrsAdditionalHdrParams; -+ -+/**************************************************************************//** -+ @Description struct for defining port PCD parameters -+*//***************************************************************************/ -+typedef struct t_FmPortPcdPrsParams { -+ uint8_t prsResultPrivateInfo; /**< The private info provides a method of inserting -+ port information into the parser result. This information -+ may be extracted by Keygen and be used for frames -+ distribution when a per-port distinction is required, -+ it may also be used as a port logical id for analyzing -+ incoming frames. */ -+ uint8_t parsingOffset; /**< Number of bytes from beginning of packet to start parsing */ -+ e_NetHeaderType firstPrsHdr; /**< The type of the first header expected at 'parsingOffset' */ -+ bool includeInPrsStatistics; /**< TRUE to include this port in the parser statistics; -+ NOTE: this field is not valid when the FM is in "guest" mode -+ and IPC is not available. */ -+ uint8_t numOfHdrsWithAdditionalParams; /**< Normally 0, some headers may get -+ special parameters */ -+ t_FmPcdPrsAdditionalHdrParams additionalParams[FM_PCD_PRS_NUM_OF_HDRS]; -+ /**< 'numOfHdrsWithAdditionalParams' structures -+ of additional parameters -+ for each header that requires them */ -+ bool setVlanTpid1; /**< TRUE to configure user selection of Ethertype to -+ indicate a VLAN tag (in addition to the TPID values -+ 0x8100 and 0x88A8). */ -+ uint16_t vlanTpid1; /**< extra tag to use if setVlanTpid1=TRUE. */ -+ bool setVlanTpid2; /**< TRUE to configure user selection of Ethertype to -+ indicate a VLAN tag (in addition to the TPID values -+ 0x8100 and 0x88A8). */ -+ uint16_t vlanTpid2; /**< extra tag to use if setVlanTpid1=TRUE. */ -+} t_FmPortPcdPrsParams; -+ -+/**************************************************************************//** -+ @Description struct for defining coarse alassification parameters -+*//***************************************************************************/ -+typedef struct t_FmPortPcdCcParams { -+ t_Handle h_CcTree; /**< A handle to a CC tree */ -+} t_FmPortPcdCcParams; -+ -+/**************************************************************************//** -+ @Description struct for defining keygen parameters -+*//***************************************************************************/ -+typedef struct t_FmPortPcdKgParams { -+ uint8_t numOfSchemes; /**< Number of schemes for port to be bound to. */ -+ t_Handle h_Schemes[FM_PCD_KG_NUM_OF_SCHEMES]; -+ /**< Array of 'numOfSchemes' schemes handles for the -+ port to be bound to */ -+ bool directScheme; /**< TRUE for going from parser to a specific scheme, -+ regardless of parser result */ -+ t_Handle h_DirectScheme; /**< relevant only if direct == TRUE, Scheme handle, -+ as returned by FM_PCD_KgSetScheme */ -+} t_FmPortPcdKgParams; -+ -+/**************************************************************************//** -+ @Description struct for defining policer parameters -+*//***************************************************************************/ -+typedef struct t_FmPortPcdPlcrParams { -+ t_Handle h_Profile; /**< Selected profile handle */ -+} t_FmPortPcdPlcrParams; -+ -+/**************************************************************************//** -+ @Description struct for defining port PCD parameters -+*//***************************************************************************/ -+typedef struct t_FmPortPcdParams { -+ e_FmPortPcdSupport pcdSupport; /**< Relevant for Rx and offline ports only. -+ Describes the active PCD engines for this port. */ -+ t_Handle h_NetEnv; /**< HL Unused in PLCR only mode */ -+ t_FmPortPcdPrsParams *p_PrsParams; /**< Parser parameters for this port */ -+ t_FmPortPcdCcParams *p_CcParams; /**< Coarse classification parameters for this port */ -+ t_FmPortPcdKgParams *p_KgParams; /**< Keygen parameters for this port */ -+ t_FmPortPcdPlcrParams *p_PlcrParams; /**< Policer parameters for this port; Relevant for one of -+ following cases: -+ e_FM_PORT_PCD_SUPPORT_PLCR_ONLY or -+ e_FM_PORT_PCD_SUPPORT_PRS_AND_PLCR were selected, -+ or if any flow uses a KG scheme were policer -+ profile is not generated -+ ('bypassPlcrProfileGeneration selected'). */ -+ t_Handle h_IpReassemblyManip; /**< IP Reassembly manipulation */ -+#if (DPAA_VERSION >= 11) -+ t_Handle h_CapwapReassemblyManip;/**< CAPWAP Reassembly manipulation */ -+#endif /* (DPAA_VERSION >= 11) */ -+} t_FmPortPcdParams; -+ -+/**************************************************************************//** -+ @Description A structure for defining the Parser starting point -+*//***************************************************************************/ -+typedef struct t_FmPcdPrsStart { -+ uint8_t parsingOffset; /**< Number of bytes from beginning of packet to -+ start parsing */ -+ e_NetHeaderType firstPrsHdr; /**< The type of the first header axpected at -+ 'parsingOffset' */ -+} t_FmPcdPrsStart; -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description struct for defining external buffer margins -+*//***************************************************************************/ -+typedef struct t_FmPortVSPAllocParams { -+ uint8_t numOfProfiles; /**< Number of Virtual Storage Profiles; must be a power of 2 */ -+ uint8_t dfltRelativeId; /**< The default Virtual-Storage-Profile-id dedicated to Rx/OP port -+ The same default Virtual-Storage-Profile-id will be for coupled Tx port -+ if relevant function called for Rx port */ -+ t_Handle h_FmTxPort; /**< Handle to coupled Tx Port; not relevant for OP port. */ -+} t_FmPortVSPAllocParams; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ -+/**************************************************************************//** -+ @Function FM_PORT_SetPCD -+ -+ @Description Calling this routine defines the port's PCD configuration. -+ It changes it from its default configuration which is PCD -+ disabled (BMI to BMI) and configures it according to the passed -+ parameters. -+ -+ May be used for Rx and OP ports only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_FmPortPcd A Structure of parameters defining the port's PCD -+ configuration. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_SetPCD(t_Handle h_FmPort, t_FmPortPcdParams *p_FmPortPcd); -+ -+/**************************************************************************//** -+ @Function FM_PORT_DeletePCD -+ -+ @Description Calling this routine releases the port's PCD configuration. -+ The port returns to its default configuration which is PCD -+ disabled (BMI to BMI) and all PCD configuration is removed. -+ -+ May be used for Rx and OP ports which are -+ in PCD mode only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_DeletePCD(t_Handle h_FmPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_AttachPCD -+ -+ @Description This routine may be called after FM_PORT_DetachPCD was called, -+ to return to the originally configured PCD support flow. -+ The couple of routines are used to allow PCD configuration changes -+ that demand that PCD will not be used while changes take place. -+ -+ May be used for Rx and OP ports which are -+ in PCD mode only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+t_Error FM_PORT_AttachPCD(t_Handle h_FmPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_DetachPCD -+ -+ @Description Calling this routine detaches the port from its PCD functionality. -+ The port returns to its default flow which is BMI to BMI. -+ -+ May be used for Rx and OP ports which are -+ in PCD mode only -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_AttachPCD(). -+*//***************************************************************************/ -+t_Error FM_PORT_DetachPCD(t_Handle h_FmPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdPlcrAllocProfiles -+ -+ @Description This routine may be called only for ports that use the Policer in -+ order to allocate private policer profiles. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] numOfProfiles The number of required policer profiles -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init() and FM_PCD_Init(), -+ and before FM_PORT_SetPCD(). -+*//***************************************************************************/ -+t_Error FM_PORT_PcdPlcrAllocProfiles(t_Handle h_FmPort, uint16_t numOfProfiles); -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdPlcrFreeProfiles -+ -+ @Description This routine should be called for freeing private policer profiles. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init() and FM_PCD_Init(), -+ and before FM_PORT_SetPCD(). -+*//***************************************************************************/ -+t_Error FM_PORT_PcdPlcrFreeProfiles(t_Handle h_FmPort); -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Function FM_PORT_VSPAlloc -+ -+ @Description This routine allocated VSPs per port and forces the port to work -+ in VSP mode. Note that the port is initialized by default with the -+ physical-storage-profile only. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_Params A structure of parameters for allocation VSP's per port -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(), and before FM_PORT_SetPCD() -+ and also before FM_PORT_Enable(); i.e. the port should be disabled. -+*//***************************************************************************/ -+t_Error FM_PORT_VSPAlloc(t_Handle h_FmPort, t_FmPortVSPAllocParams *p_Params); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdKgModifyInitialScheme -+ -+ @Description This routine may be called only for ports that use the keygen in -+ order to change the initial scheme frame should be routed to. -+ The change may be of a scheme id (in case of direct mode), -+ from direct to indirect, or from indirect to direct - specifying the scheme id. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_FmPcdKgScheme A structure of parameters for defining whether -+ a scheme is direct/indirect, and if direct - scheme id. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init() and FM_PORT_SetPCD(). -+*//***************************************************************************/ -+t_Error FM_PORT_PcdKgModifyInitialScheme (t_Handle h_FmPort, t_FmPcdKgSchemeSelect *p_FmPcdKgScheme); -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdPlcrModifyInitialProfile -+ -+ @Description This routine may be called for ports with flows -+ e_FM_PORT_PCD_SUPPORT_PLCR_ONLY or e_FM_PORT_PCD_SUPPORT_PRS_AND_PLCR -+ only, to change the initial Policer profile frame should be -+ routed to. The change may be of a profile and/or absolute/direct -+ mode selection. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] h_Profile Policer profile handle -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init() and FM_PORT_SetPCD(). -+*//***************************************************************************/ -+t_Error FM_PORT_PcdPlcrModifyInitialProfile (t_Handle h_FmPort, t_Handle h_Profile); -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdCcModifyTree -+ -+ @Description This routine may be called for ports that use coarse classification tree -+ if the user wishes to replace the tree. The routine may not be called while port -+ receives packets using the PCD functionalities, therefor port must be first detached -+ from the PCD, only than the routine may be called, and than port be attached to PCD again. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] h_CcTree A CC tree that was already built. The tree id as returned from -+ the BuildTree routine. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(), FM_PORT_SetPCD() and FM_PORT_DetachPCD() -+*//***************************************************************************/ -+t_Error FM_PORT_PcdCcModifyTree (t_Handle h_FmPort, t_Handle h_CcTree); -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdKgBindSchemes -+ -+ @Description These routines may be called for adding more schemes for the -+ port to be bound to. The selected schemes are not added, -+ just this specific port starts using them. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_PortScheme A structure defining the list of schemes to be added. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init() and FM_PORT_SetPCD(). -+*//***************************************************************************/ -+t_Error FM_PORT_PcdKgBindSchemes (t_Handle h_FmPort, t_FmPcdPortSchemesParams *p_PortScheme); -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdKgUnbindSchemes -+ -+ @Description These routines may be called for adding more schemes for the -+ port to be bound to. The selected schemes are not removed or invalidated, -+ just this specific port stops using them. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_PortScheme A structure defining the list of schemes to be added. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init() and FM_PORT_SetPCD(). -+*//***************************************************************************/ -+t_Error FM_PORT_PcdKgUnbindSchemes (t_Handle h_FmPort, t_FmPcdPortSchemesParams *p_PortScheme); -+ -+/**************************************************************************//** -+ @Function FM_PORT_GetIPv4OptionsCount -+ -+ @Description TODO -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[out] p_Ipv4OptionsCount will hold the counter value -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init() -+*//***************************************************************************/ -+t_Error FM_PORT_GetIPv4OptionsCount(t_Handle h_FmPort, uint32_t *p_Ipv4OptionsCount); -+ -+/** @} */ /* end of FM_PORT_pcd_runtime_control_grp group */ -+/** @} */ /* end of FM_PORT_runtime_control_grp group */ -+ -+ -+/**************************************************************************//** -+ @Group FM_PORT_runtime_data_grp FM Port Runtime Data-path Unit -+ -+ @Description FM Port Runtime data unit API functions, definitions and enums. -+ This API is valid only if working in Independent-Mode. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_PORT_ImTx -+ -+ @Description Tx function, called to transmit a data buffer on the port. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_Data A pointer to an LCP data buffer. -+ @Param[in] length Size of data for transmission. -+ @Param[in] lastBuffer Buffer position - TRUE for the last buffer -+ of a frame, including a single buffer frame -+ @Param[in] h_BufContext A handle of the user acossiated with this buffer -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+ NOTE - This routine can be used only when working in -+ Independent-Mode mode. -+*//***************************************************************************/ -+t_Error FM_PORT_ImTx( t_Handle h_FmPort, -+ uint8_t *p_Data, -+ uint16_t length, -+ bool lastBuffer, -+ t_Handle h_BufContext); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ImTxConf -+ -+ @Description Tx port confirmation routine, optional, may be called to verify -+ transmission of all frames. The procedure performed by this -+ routine will be performed automatically on next buffer transmission, -+ but if desired, calling this routine will invoke this action on -+ demand. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+ NOTE - This routine can be used only when working in -+ Independent-Mode mode. -+*//***************************************************************************/ -+void FM_PORT_ImTxConf(t_Handle h_FmPort); -+ -+/**************************************************************************//** -+ @Function FM_PORT_ImRx -+ -+ @Description Rx function, may be called to poll for received buffers. -+ Normally, Rx process is invoked by the driver on Rx interrupt. -+ Alternatively, this routine may be called on demand. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+ NOTE - This routine can be used only when working in -+ Independent-Mode mode. -+*//***************************************************************************/ -+t_Error FM_PORT_ImRx(t_Handle h_FmPort); -+ -+/** @} */ /* end of FM_PORT_runtime_data_grp group */ -+/** @} */ /* end of FM_PORT_grp group */ -+/** @} */ /* end of FM_grp group */ -+ -+ -+ -+#ifdef NCSW_BACKWARD_COMPATIBLE_API -+#define FM_PORT_ConfigTxFifoDeqPipelineDepth FM_PORT_ConfigFifoDeqPipelineDepth -+#endif /* NCSW_BACKWARD_COMPATIBLE_API */ -+ -+ -+#endif /* __FM_PORT_EXT */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_rtc_ext.h -@@ -0,0 +1,619 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File fm_rtc_ext.h -+ -+ @Description External definitions and API for FM RTC IEEE1588 Timer Module. -+ -+ @Cautions None. -+*//***************************************************************************/ -+ -+#ifndef __FM_RTC_EXT_H__ -+#define __FM_RTC_EXT_H__ -+ -+ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "fsl_fman_rtc.h" -+ -+/**************************************************************************//** -+ -+ @Group FM_grp Frame Manager API -+ -+ @Description FM API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group fm_rtc_grp FM RTC -+ -+ @Description FM RTC functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group fm_rtc_init_grp FM RTC Initialization Unit -+ -+ @Description FM RTC initialization API. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description FM RTC Alarm Polarity Options. -+*//***************************************************************************/ -+typedef enum e_FmRtcAlarmPolarity -+{ -+ e_FM_RTC_ALARM_POLARITY_ACTIVE_HIGH = E_FMAN_RTC_ALARM_POLARITY_ACTIVE_HIGH, /**< Active-high output polarity */ -+ e_FM_RTC_ALARM_POLARITY_ACTIVE_LOW = E_FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW /**< Active-low output polarity */ -+} e_FmRtcAlarmPolarity; -+ -+/**************************************************************************//** -+ @Description FM RTC Trigger Polarity Options. -+*//***************************************************************************/ -+typedef enum e_FmRtcTriggerPolarity -+{ -+ e_FM_RTC_TRIGGER_ON_RISING_EDGE = E_FMAN_RTC_TRIGGER_ON_RISING_EDGE, /**< Trigger on rising edge */ -+ e_FM_RTC_TRIGGER_ON_FALLING_EDGE = E_FMAN_RTC_TRIGGER_ON_FALLING_EDGE /**< Trigger on falling edge */ -+} e_FmRtcTriggerPolarity; -+ -+/**************************************************************************//** -+ @Description IEEE1588 Timer Module FM RTC Optional Clock Sources. -+*//***************************************************************************/ -+typedef enum e_FmSrcClock -+{ -+ e_FM_RTC_SOURCE_CLOCK_EXTERNAL = E_FMAN_RTC_SOURCE_CLOCK_EXTERNAL, /**< external high precision timer reference clock */ -+ e_FM_RTC_SOURCE_CLOCK_SYSTEM = E_FMAN_RTC_SOURCE_CLOCK_SYSTEM, /**< MAC system clock */ -+ e_FM_RTC_SOURCE_CLOCK_OSCILATOR = E_FMAN_RTC_SOURCE_CLOCK_OSCILATOR /**< RTC clock oscilator */ -+}e_FmSrcClk; -+ -+/**************************************************************************//** -+ @Description FM RTC configuration parameters structure. -+ -+ This structure should be passed to FM_RTC_Config(). -+*//***************************************************************************/ -+typedef struct t_FmRtcParams -+{ -+ t_Handle h_Fm; /**< FM Handle*/ -+ uintptr_t baseAddress; /**< Base address of FM RTC registers */ -+ t_Handle h_App; /**< A handle to an application layer object; This handle will -+ be passed by the driver upon calling the above callbacks */ -+} t_FmRtcParams; -+ -+ -+/**************************************************************************//** -+ @Function FM_RTC_Config -+ -+ @Description Configures the FM RTC module according to user's parameters. -+ -+ The driver assigns default values to some FM RTC parameters. -+ These parameters can be overwritten using the advanced -+ configuration routines. -+ -+ @Param[in] p_FmRtcParam - FM RTC configuration parameters. -+ -+ @Return Handle to the new FM RTC object; NULL pointer on failure. -+ -+ @Cautions None -+*//***************************************************************************/ -+t_Handle FM_RTC_Config(t_FmRtcParams *p_FmRtcParam); -+ -+/**************************************************************************//** -+ @Function FM_RTC_Init -+ -+ @Description Initializes the FM RTC driver and hardware. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously created using FM_RTC_Config(). -+*//***************************************************************************/ -+t_Error FM_RTC_Init(t_Handle h_FmRtc); -+ -+/**************************************************************************//** -+ @Function FM_RTC_Free -+ -+ @Description Frees the FM RTC object and all allocated resources. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously created using FM_RTC_Config(). -+*//***************************************************************************/ -+t_Error FM_RTC_Free(t_Handle h_FmRtc); -+ -+ -+/**************************************************************************//** -+ @Group fm_rtc_adv_config_grp FM RTC Advanced Configuration Unit -+ -+ @Description FM RTC advanced configuration functions. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_RTC_ConfigPeriod -+ -+ @Description Configures the period of the timestamp if different than -+ default [DEFAULT_clockPeriod]. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] period - Period in nano-seconds. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously created using FM_RTC_Config(). -+*//***************************************************************************/ -+t_Error FM_RTC_ConfigPeriod(t_Handle h_FmRtc, uint32_t period); -+ -+/**************************************************************************//** -+ @Function FM_RTC_ConfigSourceClock -+ -+ @Description Configures the source clock of the RTC. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] srcClk - Source clock selection. -+ @Param[in] freqInMhz - the source-clock frequency (in MHz). -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously created using FM_RTC_Config(). -+*//***************************************************************************/ -+t_Error FM_RTC_ConfigSourceClock(t_Handle h_FmRtc, -+ e_FmSrcClk srcClk, -+ uint32_t freqInMhz); -+ -+/**************************************************************************//** -+ @Function FM_RTC_ConfigPulseRealignment -+ -+ @Description Configures the RTC to automatic FIPER pulse realignment in -+ response to timer adjustments [DEFAULT_pulseRealign] -+ -+ In this mode, the RTC clock is identical to the source clock. -+ This feature can be useful when the system contains an external -+ RTC with inherent frequency compensation. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] enable - TRUE to enable automatic realignment. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously created using FM_RTC_Config(). -+*//***************************************************************************/ -+t_Error FM_RTC_ConfigPulseRealignment(t_Handle h_FmRtc, bool enable); -+ -+/**************************************************************************//** -+ @Function FM_RTC_ConfigFrequencyBypass -+ -+ @Description Configures the RTC to bypass the frequency compensation -+ mechanism. [DEFAULT_bypass] -+ -+ In this mode, the RTC clock is identical to the source clock. -+ This feature can be useful when the system contains an external -+ RTC with inherent frequency compensation. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] enabled - TRUE to bypass frequency compensation; -+ FALSE otherwise. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously created using FM_RTC_Config(). -+*//***************************************************************************/ -+t_Error FM_RTC_ConfigFrequencyBypass(t_Handle h_FmRtc, bool enabled); -+ -+/**************************************************************************//** -+ @Function FM_RTC_ConfigInvertedInputClockPhase -+ -+ @Description Configures the RTC to invert the source clock phase on input. -+ [DEFAULT_invertInputClkPhase] -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] inverted - TRUE to invert the source clock phase on input. -+ FALSE otherwise. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously created using FM_RTC_Config(). -+*//***************************************************************************/ -+t_Error FM_RTC_ConfigInvertedInputClockPhase(t_Handle h_FmRtc, bool inverted); -+ -+/**************************************************************************//** -+ @Function FM_RTC_ConfigInvertedOutputClockPhase -+ -+ @Description Configures the RTC to invert the output clock phase. -+ [DEFAULT_invertOutputClkPhase] -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] inverted - TRUE to invert the output clock phase. -+ FALSE otherwise. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously created using FM_RTC_Config(). -+*//***************************************************************************/ -+t_Error FM_RTC_ConfigInvertedOutputClockPhase(t_Handle h_FmRtc, bool inverted); -+ -+/**************************************************************************//** -+ @Function FM_RTC_ConfigOutputClockDivisor -+ -+ @Description Configures the divisor for generating the output clock from -+ the RTC clock. [DEFAULT_outputClockDivisor] -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] divisor - Divisor for generation of the output clock. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously created using FM_RTC_Config(). -+*//***************************************************************************/ -+t_Error FM_RTC_ConfigOutputClockDivisor(t_Handle h_FmRtc, uint16_t divisor); -+ -+/**************************************************************************//** -+ @Function FM_RTC_ConfigAlarmPolarity -+ -+ @Description Configures the polarity (active-high/active-low) of a specific -+ alarm signal. [DEFAULT_alarmPolarity] -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] alarmId - Alarm ID. -+ @Param[in] alarmPolarity - Alarm polarity. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously created using FM_RTC_Config(). -+*//***************************************************************************/ -+t_Error FM_RTC_ConfigAlarmPolarity(t_Handle h_FmRtc, -+ uint8_t alarmId, -+ e_FmRtcAlarmPolarity alarmPolarity); -+ -+/**************************************************************************//** -+ @Function FM_RTC_ConfigExternalTriggerPolarity -+ -+ @Description Configures the polarity (rising/falling edge) of a specific -+ external trigger signal. [DEFAULT_triggerPolarity] -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] triggerId - Trigger ID. -+ @Param[in] triggerPolarity - Trigger polarity. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously created using FM_RTC_Config(). -+*//***************************************************************************/ -+t_Error FM_RTC_ConfigExternalTriggerPolarity(t_Handle h_FmRtc, -+ uint8_t triggerId, -+ e_FmRtcTriggerPolarity triggerPolarity); -+ -+/** @} */ /* end of fm_rtc_adv_config_grp */ -+/** @} */ /* end of fm_rtc_init_grp */ -+ -+ -+/**************************************************************************//** -+ @Group fm_rtc_control_grp FM RTC Control Unit -+ -+ @Description FM RTC runtime control API. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function t_FmRtcExceptionsCallback -+ -+ @Description Exceptions user callback routine, used for RTC different mechanisms. -+ -+ @Param[in] h_App - User's application descriptor. -+ @Param[in] id - source id. -+*//***************************************************************************/ -+typedef void (t_FmRtcExceptionsCallback) ( t_Handle h_App, uint8_t id); -+ -+/**************************************************************************//** -+ @Description FM RTC alarm parameters. -+*//***************************************************************************/ -+typedef struct t_FmRtcAlarmParams { -+ uint8_t alarmId; /**< 0 or 1 */ -+ uint64_t alarmTime; /**< In nanoseconds, the time when the alarm -+ should go off - must be a multiple of -+ the RTC period */ -+ t_FmRtcExceptionsCallback *f_AlarmCallback; /**< This routine will be called when RTC -+ reaches alarmTime */ -+ bool clearOnExpiration; /**< TRUE to turn off the alarm once expired. */ -+} t_FmRtcAlarmParams; -+ -+/**************************************************************************//** -+ @Description FM RTC Periodic Pulse parameters. -+*//***************************************************************************/ -+typedef struct t_FmRtcPeriodicPulseParams { -+ uint8_t periodicPulseId; /**< 0 or 1 */ -+ uint64_t periodicPulsePeriod; /**< In Nanoseconds. Must be -+ a multiple of the RTC period */ -+ t_FmRtcExceptionsCallback *f_PeriodicPulseCallback; /**< This routine will be called every -+ periodicPulsePeriod. */ -+} t_FmRtcPeriodicPulseParams; -+ -+/**************************************************************************//** -+ @Description FM RTC Periodic Pulse parameters. -+*//***************************************************************************/ -+typedef struct t_FmRtcExternalTriggerParams { -+ uint8_t externalTriggerId; /**< 0 or 1 */ -+ bool usePulseAsInput; /**< Use the pulse interrupt instead of -+ an external signal */ -+ t_FmRtcExceptionsCallback *f_ExternalTriggerCallback; /**< This routine will be called every -+ periodicPulsePeriod. */ -+} t_FmRtcExternalTriggerParams; -+ -+ -+/**************************************************************************//** -+ @Function FM_RTC_Enable -+ -+ @Description Enable the RTC (time count is started). -+ -+ The user can select to resume the time count from previous -+ point, or to restart the time count. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] resetClock - Restart the time count from zero. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously initialized using FM_RTC_Init(). -+*//***************************************************************************/ -+t_Error FM_RTC_Enable(t_Handle h_FmRtc, bool resetClock); -+ -+/**************************************************************************//** -+ @Function FM_RTC_Disable -+ -+ @Description Disables the RTC (time count is stopped). -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously initialized using FM_RTC_Init(). -+*//***************************************************************************/ -+t_Error FM_RTC_Disable(t_Handle h_FmRtc); -+ -+/**************************************************************************//** -+ @Function FM_RTC_SetClockOffset -+ -+ @Description Sets the clock offset (usually relative to another clock). -+ -+ The user can pass a negative offset value. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] offset - New clock offset (in nanoseconds). -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously initialized using FM_RTC_Init(). -+*//***************************************************************************/ -+t_Error FM_RTC_SetClockOffset(t_Handle h_FmRtc, int64_t offset); -+ -+/**************************************************************************//** -+ @Function FM_RTC_SetAlarm -+ -+ @Description Schedules an alarm event to a given RTC time. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] p_FmRtcAlarmParams - Alarm parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously initialized using FM_RTC_Init(). -+ Must be called only prior to FM_RTC_Enable(). -+*//***************************************************************************/ -+t_Error FM_RTC_SetAlarm(t_Handle h_FmRtc, t_FmRtcAlarmParams *p_FmRtcAlarmParams); -+ -+/**************************************************************************//** -+ @Function FM_RTC_SetPeriodicPulse -+ -+ @Description Sets a periodic pulse. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] p_FmRtcPeriodicPulseParams - Periodic pulse parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously initialized using FM_RTC_Init(). -+ Must be called only prior to FM_RTC_Enable(). -+*//***************************************************************************/ -+t_Error FM_RTC_SetPeriodicPulse(t_Handle h_FmRtc, t_FmRtcPeriodicPulseParams *p_FmRtcPeriodicPulseParams); -+ -+/**************************************************************************//** -+ @Function FM_RTC_ClearPeriodicPulse -+ -+ @Description Clears a periodic pulse. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] periodicPulseId - Periodic pulse id. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously initialized using FM_RTC_Init(). -+*//***************************************************************************/ -+t_Error FM_RTC_ClearPeriodicPulse(t_Handle h_FmRtc, uint8_t periodicPulseId); -+ -+/**************************************************************************//** -+ @Function FM_RTC_SetExternalTrigger -+ -+ @Description Sets an external trigger indication and define a callback -+ routine to be called on such event. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] p_FmRtcExternalTriggerParams - External Trigger parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously initialized using FM_RTC_Init(). -+*//***************************************************************************/ -+t_Error FM_RTC_SetExternalTrigger(t_Handle h_FmRtc, t_FmRtcExternalTriggerParams *p_FmRtcExternalTriggerParams); -+ -+/**************************************************************************//** -+ @Function FM_RTC_ClearExternalTrigger -+ -+ @Description Clears external trigger indication. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] id - External Trigger id. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously initialized using FM_RTC_Init(). -+*//***************************************************************************/ -+t_Error FM_RTC_ClearExternalTrigger(t_Handle h_FmRtc, uint8_t id); -+ -+/**************************************************************************//** -+ @Function FM_RTC_GetExternalTriggerTimeStamp -+ -+ @Description Reads the External Trigger TimeStamp. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] triggerId - External Trigger id. -+ @Param[out] p_TimeStamp - External Trigger timestamp (in nanoseconds). -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously initialized using FM_RTC_Init(). -+*//***************************************************************************/ -+t_Error FM_RTC_GetExternalTriggerTimeStamp(t_Handle h_FmRtc, -+ uint8_t triggerId, -+ uint64_t *p_TimeStamp); -+ -+/**************************************************************************//** -+ @Function FM_RTC_GetCurrentTime -+ -+ @Description Returns the current RTC time. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[out] p_Ts - returned time stamp (in nanoseconds). -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously initialized using FM_RTC_Init(). -+*//***************************************************************************/ -+t_Error FM_RTC_GetCurrentTime(t_Handle h_FmRtc, uint64_t *p_Ts); -+ -+/**************************************************************************//** -+ @Function FM_RTC_SetCurrentTime -+ -+ @Description Sets the current RTC time. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] ts - The new time stamp (in nanoseconds). -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously initialized using FM_RTC_Init(). -+*//***************************************************************************/ -+t_Error FM_RTC_SetCurrentTime(t_Handle h_FmRtc, uint64_t ts); -+ -+/**************************************************************************//** -+ @Function FM_RTC_GetFreqCompensation -+ -+ @Description Retrieves the frequency compensation value -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[out] p_Compensation - A pointer to the returned value of compensation. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously initialized using FM_RTC_Init(). -+*//***************************************************************************/ -+t_Error FM_RTC_GetFreqCompensation(t_Handle h_FmRtc, uint32_t *p_Compensation); -+ -+/**************************************************************************//** -+ @Function FM_RTC_SetFreqCompensation -+ -+ @Description Sets a new frequency compensation value. -+ -+ @Param[in] h_FmRtc - Handle to FM RTC object. -+ @Param[in] freqCompensation - The new frequency compensation value to set. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions h_FmRtc must have been previously initialized using FM_RTC_Init(). -+*//***************************************************************************/ -+t_Error FM_RTC_SetFreqCompensation(t_Handle h_FmRtc, uint32_t freqCompensation); -+ -+#ifdef CONFIG_PTP_1588_CLOCK_DPAA -+/**************************************************************************//** -+*@Function FM_RTC_EnableInterrupt -+* -+*@Description Enable interrupt of FM RTC. -+* -+*@Param[in] h_FmRtc - Handle to FM RTC object. -+*@Param[in] events - Interrupt events. -+* -+*@Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_RTC_EnableInterrupt(t_Handle h_FmRtc, uint32_t events); -+ -+/**************************************************************************//** -+*@Function FM_RTC_DisableInterrupt -+* -+*@Description Disable interrupt of FM RTC. -+* -+*@Param[in] h_FmRtc - Handle to FM RTC object. -+*@Param[in] events - Interrupt events. -+* -+*@Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_RTC_DisableInterrupt(t_Handle h_FmRtc, uint32_t events); -+#endif -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+/**************************************************************************//** -+ @Function FM_RTC_DumpRegs -+ -+ @Description Dumps all FM registers -+ -+ @Param[in] h_FmRtc A handle to an FM RTC Module. -+ -+ @Return E_OK on success; -+ -+ @Cautions Allowed only FM_Init(). -+*//***************************************************************************/ -+t_Error FM_RTC_DumpRegs(t_Handle h_FmRtc); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+/** @} */ /* end of fm_rtc_control_grp */ -+/** @} */ /* end of fm_rtc_grp */ -+/** @} */ /* end of FM_grp group */ -+ -+ -+#endif /* __FM_RTC_EXT_H__ */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_vsp_ext.h -@@ -0,0 +1,411 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File fm_vsp_ext.h -+ -+ @Description FM Virtual Storage-Profile ... -+*//***************************************************************************/ -+#ifndef __FM_VSP_EXT_H -+#define __FM_VSP_EXT_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "string_ext.h" -+#include "debug_ext.h" -+ -+#include "fm_ext.h" -+ -+ -+/**************************************************************************//** -+ -+ @Group FM_grp Frame Manager API -+ -+ @Description FM API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group FM_VSP_grp FM Virtual-Storage-Profile -+ -+ @Description FM Virtual-Storage-Profile API -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group FM_VSP_init_grp FM VSP Initialization Unit -+ -+ @Description FM VSP initialization API. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description Virtual Storage Profile -+*//***************************************************************************/ -+typedef struct t_FmVspParams { -+ t_Handle h_Fm; /**< A handle to the FM object this VSP related to */ -+ t_FmExtPools extBufPools; /**< Which external buffer pools are used -+ (up to FM_PORT_MAX_NUM_OF_EXT_POOLS), and their sizes. -+ parameter associated with Rx / OP port */ -+ uint16_t liodnOffset; /**< VSP's LIODN offset */ -+ struct { -+ e_FmPortType portType; /**< Port type */ -+ uint8_t portId; /**< Port Id - relative to type */ -+ } portParams; -+ uint8_t relativeProfileId; /**< VSP Id - relative to VSP's range -+ defined in relevant FM object */ -+} t_FmVspParams; -+ -+ -+/**************************************************************************//** -+ @Function FM_VSP_Config -+ -+ @Description Creates descriptor for the FM VSP module. -+ -+ The routine returns a handle (descriptor) to the FM VSP object. -+ This descriptor must be passed as first parameter to all other -+ FM VSP function calls. -+ -+ No actual initialization or configuration of FM hardware is -+ done by this routine. -+ -+@Param[in] p_FmVspParams Pointer to data structure of parameters -+ -+ @Retval Handle to FM VSP object, or NULL for Failure. -+*//***************************************************************************/ -+t_Handle FM_VSP_Config(t_FmVspParams *p_FmVspParams); -+ -+/**************************************************************************//** -+ @Function FM_VSP_Init -+ -+ @Description Initializes the FM VSP module -+ -+ @Param[in] h_FmVsp - FM VSP module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_VSP_Init(t_Handle h_FmVsp); -+ -+/**************************************************************************//** -+ @Function FM_VSP_Free -+ -+ @Description Frees all resources that were assigned to FM VSP module. -+ -+ Calling this routine invalidates the descriptor. -+ -+ @Param[in] h_FmVsp - FM VSP module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error FM_VSP_Free(t_Handle h_FmVsp); -+ -+ -+/**************************************************************************//** -+ @Group FM_VSP_adv_config_grp FM VSP Advanced Configuration Unit -+ -+ @Description FM VSP advanced configuration functions. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_VSP_ConfigBufferPrefixContent -+ -+ @Description Defines the structure, size and content of the application buffer. -+ -+ The prefix will -+ In VSPs defined for Tx ports, if 'passPrsResult', the application -+ should set a value to their offsets in the prefix of -+ the FM will save the first 'privDataSize', than, -+ depending on 'passPrsResult' and 'passTimeStamp', copy parse result -+ and timeStamp, and the packet itself (in this order), to the -+ application buffer, and to offset. -+ -+ Calling this routine changes the buffer margins definitions -+ in the internal driver data base from its default -+ configuration: Data size: [DEFAULT_FM_SP_bufferPrefixContent_privDataSize] -+ Pass Parser result: [DEFAULT_FM_SP_bufferPrefixContent_passPrsResult]. -+ Pass timestamp: [DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp]. -+ -+ @Param[in] h_FmVsp A handle to a FM VSP module. -+ @Param[in,out] p_FmBufferPrefixContent A structure of parameters describing the -+ structure of the buffer. -+ Out parameter: Start margin - offset -+ of data from start of external buffer. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init(). -+*//***************************************************************************/ -+t_Error FM_VSP_ConfigBufferPrefixContent(t_Handle h_FmVsp, -+ t_FmBufferPrefixContent *p_FmBufferPrefixContent); -+ -+/**************************************************************************//** -+ @Function FM_VSP_ConfigDmaSwapData -+ -+ @Description Calling this routine changes the DMA swap data parameter -+ in the internal driver data base from its default -+ configuration [DEFAULT_FM_SP_dmaSwapData] -+ -+ @Param[in] h_FmVsp A handle to a FM VSP module. -+ @Param[in] swapData New selection -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init(). -+*//***************************************************************************/ -+t_Error FM_VSP_ConfigDmaSwapData(t_Handle h_FmVsp, e_FmDmaSwapOption swapData); -+ -+/**************************************************************************//** -+ @Function FM_VSP_ConfigDmaIcCacheAttr -+ -+ @Description Calling this routine changes the internal context cache -+ attribute parameter in the internal driver data base -+ from its default configuration [DEFAULT_FM_SP_dmaIntContextCacheAttr] -+ -+ @Param[in] h_FmVsp A handle to a FM VSP module. -+ @Param[in] intContextCacheAttr New selection -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init(). -+*//***************************************************************************/ -+t_Error FM_VSP_ConfigDmaIcCacheAttr(t_Handle h_FmVsp, -+ e_FmDmaCacheOption intContextCacheAttr); -+ -+/**************************************************************************//** -+ @Function FM_VSP_ConfigDmaHdrAttr -+ -+ @Description Calling this routine changes the header cache -+ attribute parameter in the internal driver data base -+ from its default configuration [DEFAULT_FM_SP_dmaHeaderCacheAttr] -+ -+ @Param[in] h_FmVsp A handle to a FM VSP module. -+ @Param[in] headerCacheAttr New selection -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init(). -+*//***************************************************************************/ -+t_Error FM_VSP_ConfigDmaHdrAttr(t_Handle h_FmVsp, e_FmDmaCacheOption headerCacheAttr); -+ -+/**************************************************************************//** -+ @Function FM_VSP_ConfigDmaScatterGatherAttr -+ -+ @Description Calling this routine changes the scatter gather cache -+ attribute parameter in the internal driver data base -+ from its default configuration [DEFAULT_FM_SP_dmaScatterGatherCacheAttr] -+ -+ @Param[in] h_FmVsp A handle to a FM VSP module. -+ @Param[in] scatterGatherCacheAttr New selection -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init(). -+*//***************************************************************************/ -+t_Error FM_VSP_ConfigDmaScatterGatherAttr(t_Handle h_FmVsp, -+ e_FmDmaCacheOption scatterGatherCacheAttr); -+ -+/**************************************************************************//** -+ @Function FM_VSP_ConfigDmaWriteOptimize -+ -+ @Description Calling this routine changes the write optimization -+ parameter in the internal driver data base -+ from its default configuration: optimize = [DEFAULT_FM_SP_dmaWriteOptimize] -+ -+ @Param[in] h_FmVsp A handle to a FM VSP module. -+ @Param[in] optimize TRUE to enable optimization, FALSE for normal operation -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init(). -+*//***************************************************************************/ -+t_Error FM_VSP_ConfigDmaWriteOptimize(t_Handle h_FmVsp, bool optimize); -+ -+/**************************************************************************//** -+ @Function FM_VSP_ConfigNoScatherGather -+ -+ @Description Calling this routine changes the possibility to receive S/G frame -+ in the internal driver data base -+ from its default configuration: optimize = [DEFAULT_FM_SP_noScatherGather] -+ -+ @Param[in] h_FmVsp A handle to a FM VSP module. -+ @Param[in] noScatherGather TRUE to operate without scatter/gather capability. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init(). -+*//***************************************************************************/ -+t_Error FM_VSP_ConfigNoScatherGather(t_Handle h_FmVsp, bool noScatherGather); -+ -+/**************************************************************************//** -+ @Function FM_VSP_ConfigPoolDepletion -+ -+ @Description Calling this routine enables pause frame generation depending on the -+ depletion status of BM pools. It also defines the conditions to activate -+ this functionality. By default, this functionality is disabled. -+ -+ @Param[in] h_FmVsp A handle to a FM VSP module. -+ @Param[in] p_BufPoolDepletion A structure of pool depletion parameters -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init(). -+*//***************************************************************************/ -+t_Error FM_VSP_ConfigPoolDepletion(t_Handle h_FmVsp, t_FmBufPoolDepletion *p_BufPoolDepletion); -+ -+/**************************************************************************//** -+ @Function FM_VSP_ConfigBackupPools -+ -+ @Description Calling this routine allows the configuration of some of the BM pools -+ defined for this port as backup pools. -+ A pool configured to be a backup pool will be used only if all other -+ enabled non-backup pools are depleted. -+ -+ @Param[in] h_FmVsp A handle to a FM VSP module. -+ @Param[in] p_BackupBmPools An array of pool id's. All pools specified here will -+ be defined as backup pools. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init(). -+*//***************************************************************************/ -+t_Error FM_VSP_ConfigBackupPools(t_Handle h_FmVsp, t_FmBackupBmPools *p_BackupBmPools); -+ -+/** @} */ /* end of FM_VSP_adv_config_grp group */ -+/** @} */ /* end of FM_VSP_init_grp group */ -+ -+ -+/**************************************************************************//** -+ @Group FM_VSP_control_grp FM VSP Control Unit -+ -+ @Description FM VSP runtime control API. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function FM_VSP_GetBufferDataOffset -+ -+ @Description Relevant for Rx ports. -+ Returns the data offset from the beginning of the data buffer -+ -+ @Param[in] h_FmVsp - FM PORT module descriptor -+ -+ @Return data offset. -+ -+ @Cautions Allowed only following FM_VSP_Init(). -+*//***************************************************************************/ -+uint32_t FM_VSP_GetBufferDataOffset(t_Handle h_FmVsp); -+ -+/**************************************************************************//** -+ @Function FM_VSP_GetBufferICInfo -+ -+ @Description Returns the Internal Context offset from the beginning of the data buffer -+ -+ @Param[in] h_FmVsp - FM PORT module descriptor -+ @Param[in] p_Data - A pointer to the data buffer. -+ -+ @Return Internal context info pointer on success, NULL if 'allOtherInfo' was not -+ configured for this port. -+ -+ @Cautions Allowed only following FM_VSP_Init(). -+*//***************************************************************************/ -+uint8_t * FM_VSP_GetBufferICInfo(t_Handle h_FmVsp, char *p_Data); -+ -+/**************************************************************************//** -+ @Function FM_VSP_GetBufferPrsResult -+ -+ @Description Returns the pointer to the parse result in the data buffer. -+ In Rx ports this is relevant after reception, if parse -+ result is configured to be part of the data passed to the -+ application. For non Rx ports it may be used to get the pointer -+ of the area in the buffer where parse result should be -+ initialized - if so configured. -+ See FM_VSP_ConfigBufferPrefixContent for data buffer prefix -+ configuration. -+ -+ @Param[in] h_FmVsp - FM PORT module descriptor -+ @Param[in] p_Data - A pointer to the data buffer. -+ -+ @Return Parse result pointer on success, NULL if parse result was not -+ configured for this port. -+ -+ @Cautions Allowed only following FM_VSP_Init(). -+*//***************************************************************************/ -+t_FmPrsResult * FM_VSP_GetBufferPrsResult(t_Handle h_FmVsp, char *p_Data); -+ -+/**************************************************************************//** -+ @Function FM_VSP_GetBufferTimeStamp -+ -+ @Description Returns the time stamp in the data buffer. -+ Relevant for Rx ports for getting the buffer time stamp. -+ See FM_VSP_ConfigBufferPrefixContent for data buffer prefix -+ configuration. -+ -+ @Param[in] h_FmVsp - FM PORT module descriptor -+ @Param[in] p_Data - A pointer to the data buffer. -+ -+ @Return A pointer to the hash result on success, NULL otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Init(). -+*//***************************************************************************/ -+uint64_t * FM_VSP_GetBufferTimeStamp(t_Handle h_FmVsp, char *p_Data); -+ -+/**************************************************************************//** -+ @Function FM_VSP_GetBufferHashResult -+ -+ @Description Given a data buffer, on the condition that hash result was defined -+ as a part of the buffer content (see FM_VSP_ConfigBufferPrefixContent) -+ this routine will return the pointer to the hash result location in the -+ buffer prefix. -+ -+ @Param[in] h_FmVsp - FM PORT module descriptor -+ @Param[in] p_Data - A pointer to the data buffer. -+ -+ @Return A pointer to the hash result on success, NULL otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Init(). -+*//***************************************************************************/ -+uint8_t * FM_VSP_GetBufferHashResult(t_Handle h_FmVsp, char *p_Data); -+ -+ -+/** @} */ /* end of FM_VSP_control_grp group */ -+/** @} */ /* end of FM_VSP_grp group */ -+/** @} */ /* end of FM_grp group */ -+ -+ -+#endif /* __FM_VSP_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/mii_acc_ext.h -@@ -0,0 +1,76 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+ -+#ifndef __MII_ACC_EXT_H -+#define __MII_ACC_EXT_H -+ -+ -+/**************************************************************************//** -+ @Function MII_ReadPhyReg -+ -+ @Description This routine is called to read a specified PHY -+ register value. -+ -+ @Param[in] h_MiiAccess - Handle to MII configuration access registers -+ @Param[in] phyAddr - PHY address (0-31). -+ @Param[in] reg - PHY register to read -+ @Param[out] p_Data - Gets the register value. -+ -+ @Return Always zero (success). -+*//***************************************************************************/ -+int MII_ReadPhyReg(t_Handle h_MiiAccess, -+ uint8_t phyAddr, -+ uint8_t reg, -+ uint16_t *p_Data); -+ -+/**************************************************************************//** -+ @Function MII_WritePhyReg -+ -+ @Description This routine is called to write data to a specified PHY -+ register. -+ -+ @Param[in] h_MiiAccess - Handle to MII configuration access registers -+ @Param[in] phyAddr - PHY address (0-31). -+ @Param[in] reg - PHY register to write -+ @Param[in] data - Data to write in register. -+ -+ @Return Always zero (success). -+*//***************************************************************************/ -+int MII_WritePhyReg(t_Handle h_MiiAccess, -+ uint8_t phyAddr, -+ uint8_t reg, -+ uint16_t data); -+ -+ -+#endif /* __MII_ACC_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/core_ext.h -@@ -0,0 +1,90 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File core_ext.h -+ -+ @Description Generic interface to basic core operations. -+ -+ The system integrator must ensure that this interface is -+ mapped to a specific core implementation, by including the -+ appropriate header file. -+*//***************************************************************************/ -+#ifndef __CORE_EXT_H -+#define __CORE_EXT_H -+ -+#ifdef CONFIG_FMAN_ARM -+#include "arm_ext.h" -+#include -+#else -+#ifdef NCSW_PPC_CORE -+#include "ppc_ext.h" -+#elif defined(NCSW_VXWORKS) -+#include "core_vxw_ext.h" -+#else -+#error "Core is not defined!" -+#endif /* NCSW_CORE */ -+ -+#if (!defined(CORE_IS_LITTLE_ENDIAN) && !defined(CORE_IS_BIG_ENDIAN)) -+#error "Must define core as little-endian or big-endian!" -+#endif /* (!defined(CORE_IS_LITTLE_ENDIAN) && ... */ -+ -+#ifndef CORE_CACHELINE_SIZE -+#error "Must define the core cache-line size!" -+#endif /* !CORE_CACHELINE_SIZE */ -+ -+#endif /* CONFIG_FMAN_ARM */ -+ -+ -+/**************************************************************************//** -+ @Function CORE_GetId -+ -+ @Description Returns the core ID in the system. -+ -+ @Return Core ID. -+*//***************************************************************************/ -+uint32_t CORE_GetId(void); -+ -+/**************************************************************************//** -+ @Function CORE_MemoryBarrier -+ -+ @Description This routine will cause the core to stop executing any commands -+ until all previous memory read/write commands are completely out -+ of the core's pipeline. -+ -+ @Return None. -+*//***************************************************************************/ -+void CORE_MemoryBarrier(void); -+#define fsl_mem_core_barrier() CORE_MemoryBarrier() -+ -+#endif /* __CORE_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/cores/arm_ext.h -@@ -0,0 +1,55 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File arm_ext.h -+ -+ @Description Core API for ARM cores -+ -+ These routines must be implemented by each specific PowerPC -+ core driver. -+*//***************************************************************************/ -+#ifndef __ARM_EXT_H -+#define __ARM_EXT_H -+ -+#include "part_ext.h" -+ -+ -+#define CORE_IS_LITTLE_ENDIAN -+ -+static __inline__ void CORE_MemoryBarrier(void) -+{ -+ mb(); -+} -+ -+#endif /* __PPC_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/cores/e500v2_ext.h -@@ -0,0 +1,476 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File e500v2_ext.h -+ -+ @Description E500 external definitions prototypes -+ This file is not included by the E500 -+ source file as it is an assembly file. It is used -+ only for prototypes exposure, for inclusion -+ by user and other modules. -+*//***************************************************************************/ -+ -+#ifndef __E500V2_EXT_H -+#define __E500V2_EXT_H -+ -+#include "std_ext.h" -+ -+ -+/* Layer 1 Cache Manipulations -+ *============================== -+ * Should not be called directly by the user. -+ */ -+void L1DCache_Invalidate (void); -+void L1ICache_Invalidate(void); -+void L1DCache_Enable(void); -+void L1ICache_Enable(void); -+void L1DCache_Disable(void); -+void L1ICache_Disable(void); -+void L1DCache_Flush(void); -+void L1ICache_Flush(void); -+uint32_t L1ICache_IsEnabled(void); -+uint32_t L1DCache_IsEnabled(void); -+/* -+ * -+ */ -+uint32_t L1DCache_LineLock(uint32_t addr); -+uint32_t L1ICache_LineLock(uint32_t addr); -+void L1Cache_BroadCastEnable(void); -+void L1Cache_BroadCastDisable(void); -+ -+ -+#define CORE_DCacheEnable E500_DCacheEnable -+#define CORE_ICacheEnable E500_ICacheEnable -+#define CORE_DCacheDisable E500_DCacheDisable -+#define CORE_ICacheDisable E500_ICacheDisable -+#define CORE_GetId E500_GetId -+#define CORE_TestAndSet E500_TestAndSet -+#define CORE_MemoryBarrier E500_MemoryBarrier -+#define CORE_InstructionSync E500_InstructionSync -+ -+#define CORE_SetDozeMode E500_SetDozeMode -+#define CORE_SetNapMode E500_SetNapMode -+#define CORE_SetSleepMode E500_SetSleepMode -+#define CORE_SetJogMode E500_SetJogMode -+#define CORE_SetDeepSleepMode E500_SetDeepSleepMode -+ -+#define CORE_RecoverDozeMode E500_RecoverDozeMode -+#define CORE_RecoverNapMode E500_RecoverNapMode -+#define CORE_RecoverSleepMode E500_RecoverSleepMode -+#define CORE_RecoverJogMode E500_RecoverJogMode -+ -+void E500_SetDozeMode(void); -+void E500_SetNapMode(void); -+void E500_SetSleepMode(void); -+void E500_SetJogMode(void); -+t_Error E500_SetDeepSleepMode(uint32_t bptrAddress); -+ -+void E500_RecoverDozeMode(void); -+void E500_RecoverNapMode(void); -+void E500_RecoverSleepMode(void); -+void E500_RecoverJogMode(void); -+ -+ -+/**************************************************************************//** -+ @Group E500_id E500 Application Programming Interface -+ -+ @Description E500 API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group E500_init_grp E500 Initialization Unit -+ -+ @Description E500 initialization unit API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+ -+/**************************************************************************//** -+ @Function E500_DCacheEnable -+ -+ @Description Enables the data cache for memory pages that are -+ not cache inhibited. -+ -+ @Return None. -+*//***************************************************************************/ -+void E500_DCacheEnable(void); -+ -+/**************************************************************************//** -+ @Function E500_ICacheEnable -+ -+ @Description Enables the instruction cache for memory pages that are -+ not cache inhibited. -+ -+ @Return None. -+*//***************************************************************************/ -+void E500_ICacheEnable(void); -+ -+/**************************************************************************//** -+ @Function E500_DCacheDisable -+ -+ @Description Disables the data cache. -+ -+ @Return None. -+*//***************************************************************************/ -+void E500_DCacheDisable(void); -+ -+/**************************************************************************//** -+ @Function E500_ICacheDisable -+ -+ @Description Disables the instruction cache. -+ -+ @Return None. -+*//***************************************************************************/ -+void E500_ICacheDisable(void); -+ -+/**************************************************************************//** -+ @Function E500_DCacheFlush -+ -+ @Description Flushes the data cache -+ -+ @Return None. -+*//***************************************************************************/ -+void E500_DCacheFlush(void); -+ -+/**************************************************************************//** -+ @Function E500_ICacheFlush -+ -+ @Description Flushes the instruction cache. -+ -+ @Return None. -+*//***************************************************************************/ -+void E500_ICacheFlush(void); -+ -+/**************************************************************************//** -+ @Function E500_DCacheSetStashId -+ -+ @Description Set Stash Id for data cache -+ -+ @Param[in] stashId the stash id to be set. -+ -+ @Return None. -+*//***************************************************************************/ -+void E500_DCacheSetStashId(uint8_t stashId); -+ -+/**************************************************************************//** -+ @Description E500mc L2 Cache Operation Mode -+*//***************************************************************************/ -+typedef enum e_E500mcL2CacheMode -+{ -+ e_L2_CACHE_MODE_DATA_ONLY = 0x00000001, /**< Cache data only */ -+ e_L2_CACHE_MODE_INST_ONLY = 0x00000002, /**< Cache instructions only */ -+ e_L2_CACHE_MODE_DATA_AND_INST = 0x00000003 /**< Cache data and instructions */ -+} e_E500mcL2CacheMode; -+ -+#if defined(CORE_E500MC) || defined(CORE_E5500) -+/**************************************************************************//** -+ @Function E500_L2CacheEnable -+ -+ @Description Enables the cache for memory pages that are not cache inhibited. -+ -+ @param[in] mode - L2 cache mode: data only, instruction only or instruction and data. -+ -+ @Return None. -+ -+ @Cautions This routine must be call only ONCE for both caches. I.e. it is -+ not possible to call this routine for i-cache and than to call -+ again for d-cache; The second call will override the first one. -+*//***************************************************************************/ -+void E500_L2CacheEnable(e_E500mcL2CacheMode mode); -+ -+/**************************************************************************//** -+ @Function E500_L2CacheDisable -+ -+ @Description Disables the cache (data instruction or both). -+ -+ @Return None. -+ -+*//***************************************************************************/ -+void E500_L2CacheDisable(void); -+ -+/**************************************************************************//** -+ @Function E500_L2CacheFlush -+ -+ @Description Flushes the cache. -+ -+ @Return None. -+*//***************************************************************************/ -+void E500_L2CacheFlush(void); -+ -+/**************************************************************************//** -+ @Function E500_L2SetStashId -+ -+ @Description Set Stash Id -+ -+ @Param[in] stashId the stash id to be set. -+ -+ @Return None. -+*//***************************************************************************/ -+void E500_L2SetStashId(uint8_t stashId); -+#endif /* defined(CORE_E500MC) || defined(CORE_E5500) */ -+ -+#ifdef CORE_E6500 -+/**************************************************************************//** -+ @Function E6500_L2CacheEnable -+ -+ @Description Enables the cache for memory pages that are not cache inhibited. -+ -+ @param[in] mode - L2 cache mode: support data & instruction only. -+ -+ @Return None. -+ -+ @Cautions This routine must be call only ONCE for both caches. I.e. it is -+ not possible to call this routine for i-cache and than to call -+ again for d-cache; The second call will override the first one. -+*//***************************************************************************/ -+void E6500_L2CacheEnable(uintptr_t clusterBase); -+ -+/**************************************************************************//** -+ @Function E6500_L2CacheDisable -+ -+ @Description Disables the cache (data instruction or both). -+ -+ @Return None. -+ -+*//***************************************************************************/ -+void E6500_L2CacheDisable(uintptr_t clusterBase); -+ -+/**************************************************************************//** -+ @Function E6500_L2CacheFlush -+ -+ @Description Flushes the cache. -+ -+ @Return None. -+*//***************************************************************************/ -+void E6500_L2CacheFlush(uintptr_t clusterBase); -+ -+/**************************************************************************//** -+ @Function E6500_L2SetStashId -+ -+ @Description Set Stash Id -+ -+ @Param[in] stashId the stash id to be set. -+ -+ @Return None. -+*//***************************************************************************/ -+void E6500_L2SetStashId(uintptr_t clusterBase, uint8_t stashId); -+ -+/**************************************************************************//** -+ @Function E6500_GetCcsrBase -+ -+ @Description Obtain SoC CCSR base address -+ -+ @Param[in] None. -+ -+ @Return Physical CCSR base address. -+*//***************************************************************************/ -+physAddress_t E6500_GetCcsrBase(void); -+#endif /* CORE_E6500 */ -+ -+/**************************************************************************//** -+ @Function E500_AddressBusStreamingEnable -+ -+ @Description Enables address bus streaming on the CCB. -+ -+ This setting, along with the ECM streaming configuration -+ parameters, enables address bus streaming on the CCB. -+ -+ @Return None. -+*//***************************************************************************/ -+void E500_AddressBusStreamingEnable(void); -+ -+/**************************************************************************//** -+ @Function E500_AddressBusStreamingDisable -+ -+ @Description Disables address bus streaming on the CCB. -+ -+ @Return None. -+*//***************************************************************************/ -+void E500_AddressBusStreamingDisable(void); -+ -+/**************************************************************************//** -+ @Function E500_AddressBroadcastEnable -+ -+ @Description Enables address broadcast. -+ -+ The e500 broadcasts cache management instructions (dcbst, dcblc -+ (CT = 1), icblc (CT = 1), dcbf, dcbi, mbar, msync, tlbsync, icbi) -+ based on ABE. ABE must be set to allow management of external -+ L2 caches. -+ -+ @Return None. -+*//***************************************************************************/ -+void E500_AddressBroadcastEnable(void); -+ -+/**************************************************************************//** -+ @Function E500_AddressBroadcastDisable -+ -+ @Description Disables address broadcast. -+ -+ The e500 broadcasts cache management instructions (dcbst, dcblc -+ (CT = 1), icblc (CT = 1), dcbf, dcbi, mbar, msync, tlbsync, icbi) -+ based on ABE. ABE must be set to allow management of external -+ L2 caches. -+ -+ @Return None. -+*//***************************************************************************/ -+void E500_AddressBroadcastDisable(void); -+ -+/**************************************************************************//** -+ @Function E500_IsTaskletSupported -+ -+ @Description Checks if tasklets are supported by the e500 interrupt handler. -+ -+ @Retval TRUE - Tasklets are supported. -+ @Retval FALSE - Tasklets are not supported. -+*//***************************************************************************/ -+bool E500_IsTaskletSupported(void); -+ -+void E500_EnableTimeBase(void); -+void E500_DisableTimeBase(void); -+ -+uint64_t E500_GetTimeBaseTime(void); -+ -+void E500_GenericIntrInit(void); -+ -+t_Error E500_SetIntr(int ppcIntrSrc, -+ void (* Isr)(t_Handle handle), -+ t_Handle handle); -+ -+t_Error E500_ClearIntr(int ppcIntrSrc); -+ -+/**************************************************************************//** -+ @Function E500_GenericIntrHandler -+ -+ @Description This is the general e500 interrupt handler. -+ -+ It is called by the main assembly interrupt handler -+ when an exception occurs and no other function has been -+ assigned to this exception. -+ -+ @Param intrEntry - (In) The exception interrupt vector entry. -+*//***************************************************************************/ -+void E500_GenericIntrHandler(uint32_t intrEntry); -+ -+/**************************************************************************//** -+ @Function CriticalIntr -+ -+ @Description This is the specific critical e500 interrupt handler. -+ -+ It is called by the main assembly interrupt handler -+ when an critical interrupt. -+ -+ @Param intrEntry - (In) The exception interrupt vector entry. -+*//***************************************************************************/ -+void CriticalIntr(uint32_t intrEntry); -+ -+ -+/**************************************************************************//** -+ @Function E500_GetId -+ -+ @Description Returns the core ID in the system. -+ -+ @Return Core ID. -+*//***************************************************************************/ -+uint32_t E500_GetId(void); -+ -+/**************************************************************************//** -+ @Function E500_TestAndSet -+ -+ @Description This routine tries to atomically test-and-set an integer -+ in memory to a non-zero value. -+ -+ The memory will be set only if it is tested as zero, in which -+ case the routine returns the new non-zero value; otherwise the -+ routine returns zero. -+ -+ @Param[in] p - pointer to a volatile int in memory, on which test-and-set -+ operation should be made. -+ -+ @Retval Zero - Operation failed - memory was already set. -+ @Retval Non-zero - Operation succeeded - memory has been set. -+*//***************************************************************************/ -+int E500_TestAndSet(volatile int *p); -+ -+/**************************************************************************//** -+ @Function E500_MemoryBarrier -+ -+ @Description This routine will cause the core to stop executing any commands -+ until all previous memory read/write commands are completely out -+ of the core's pipeline. -+ -+ @Return None. -+*//***************************************************************************/ -+static __inline__ void E500_MemoryBarrier(void) -+{ -+#ifndef CORE_E500V2 -+ __asm__ ("mbar 1"); -+#else /* CORE_E500V2 */ -+ /**** ERRATA WORK AROUND START ****/ -+ /* ERRATA num: CPU1 */ -+ /* Description: "mbar MO = 1" instruction fails to order caching-inhibited -+ guarded loads and stores. */ -+ -+ /* "msync" instruction is used instead */ -+ -+ __asm__ ("msync"); -+ -+ /**** ERRATA WORK AROUND END ****/ -+#endif /* CORE_E500V2 */ -+} -+ -+/**************************************************************************//** -+ @Function E500_InstructionSync -+ -+ @Description This routine will cause the core to wait for previous instructions -+ (including any interrupts they generate) to complete before the -+ synchronization command executes, which purges all instructions -+ from the processor's pipeline and refetches the next instruction. -+ -+ @Return None. -+*//***************************************************************************/ -+static __inline__ void E500_InstructionSync(void) -+{ -+ __asm__ ("isync"); -+} -+ -+ -+/** @} */ /* end of E500_init_grp group */ -+/** @} */ /* end of E500_grp group */ -+ -+ -+#endif /* __E500V2_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/cores/ppc_ext.h -@@ -0,0 +1,141 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File ppc_ext.h -+ -+ @Description Core API for PowerPC cores -+ -+ These routines must be implemented by each specific PowerPC -+ core driver. -+*//***************************************************************************/ -+#ifndef __PPC_EXT_H -+#define __PPC_EXT_H -+ -+#include "part_ext.h" -+ -+ -+#define CORE_IS_BIG_ENDIAN -+ -+#if defined(CORE_E300) || defined(CORE_E500V2) -+#define CORE_CACHELINE_SIZE 32 -+#elif defined(CORE_E500MC) || defined(CORE_E5500) || defined(CORE_E6500) -+#define CORE_CACHELINE_SIZE 64 -+#else -+#error "Core not defined!" -+#endif /* defined(CORE_E300) || ... */ -+ -+ -+/**************************************************************************//** -+ @Function CORE_TestAndSet -+ -+ @Description This routine tries to atomically test-and-set an integer -+ in memory to a non-zero value. -+ -+ The memory will be set only if it is tested as zero, in which -+ case the routine returns the new non-zero value; otherwise the -+ routine returns zero. -+ -+ @Param[in] p - pointer to a volatile int in memory, on which test-and-set -+ operation should be made. -+ -+ @Retval Zero - Operation failed - memory was already set. -+ @Retval Non-zero - Operation succeeded - memory has been set. -+*//***************************************************************************/ -+int CORE_TestAndSet(volatile int *p); -+ -+/**************************************************************************//** -+ @Function CORE_InstructionSync -+ -+ @Description This routine will cause the core to wait for previous instructions -+ (including any interrupts they generate) to complete before the -+ synchronization command executes, which purges all instructions -+ from the processor's pipeline and refetches the next instruction. -+ -+ @Return None. -+*//***************************************************************************/ -+void CORE_InstructionSync(void); -+ -+/**************************************************************************//** -+ @Function CORE_DCacheEnable -+ -+ @Description Enables the data cache for memory pages that are -+ not cache inhibited. -+ -+ @Return None. -+*//***************************************************************************/ -+void CORE_DCacheEnable(void); -+ -+/**************************************************************************//** -+ @Function CORE_ICacheEnable -+ -+ @Description Enables the instruction cache for memory pages that are -+ not cache inhibited. -+ -+ @Return None. -+*//***************************************************************************/ -+void CORE_ICacheEnable(void); -+ -+/**************************************************************************//** -+ @Function CORE_DCacheDisable -+ -+ @Description Disables the data cache. -+ -+ @Return None. -+*//***************************************************************************/ -+void CORE_DCacheDisable(void); -+ -+/**************************************************************************//** -+ @Function CORE_ICacheDisable -+ -+ @Description Disables the instruction cache. -+ -+ @Return None. -+*//***************************************************************************/ -+void CORE_ICacheDisable(void); -+ -+ -+ -+#if defined(CORE_E300) -+#include "e300_ext.h" -+#elif defined(CORE_E500V2) || defined(CORE_E500MC) || defined(CORE_E5500) || defined(CORE_E6500) -+#include "e500v2_ext.h" -+#if !defined(NCSW_LINUX) -+#include "e500v2_asm_ext.h" -+#endif -+#else -+#error "Core not defined!" -+#endif -+ -+ -+#endif /* __PPC_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/ddr_std_ext.h -@@ -0,0 +1,77 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __DDR_SDT_EXT_H -+#define __DDR_SDT_EXT_H -+ -+ -+/**************************************************************************//** -+ @Group ddr_Generic_Resources -+ -+ @Description ddr generic functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+ -+/**************************************************************************//** -+ @Description SPD maximum size -+*//***************************************************************************/ -+#define SPD_MAX_SIZE 256 -+ -+/**************************************************************************//** -+ @Description DDR types select -+*//***************************************************************************/ -+typedef enum e_DdrType -+{ -+ e_DDR_DDR1, -+ e_DDR_DDR2, -+ e_DDR_DDR3, -+ e_DDR_DDR3L, -+ e_DDR_DDR4 -+} e_DdrType; -+ -+/**************************************************************************//** -+ @Description DDR Mode. -+*//***************************************************************************/ -+typedef enum e_DdrMode -+{ -+ e_DDR_BUS_WIDTH_32BIT, -+ e_DDR_BUS_WIDTH_64BIT -+} e_DdrMode; -+ -+/** @} */ /* end of ddr_Generic_Resources group */ -+ -+ -+ -+#endif /* __DDR_SDT_EXT_H */ -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/debug_ext.h -@@ -0,0 +1,233 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File debug_ext.h -+ -+ @Description Debug mode definitions. -+*//***************************************************************************/ -+ -+#ifndef __DEBUG_EXT_H -+#define __DEBUG_EXT_H -+ -+#include "std_ext.h" -+#include "xx_ext.h" -+#include "memcpy_ext.h" -+#if (DEBUG_ERRORS > 0) -+#include "sprint_ext.h" -+#include "string_ext.h" -+#endif /* DEBUG_ERRORS > 0 */ -+ -+ -+#if (DEBUG_ERRORS > 0) -+ -+/* Internally used macros */ -+ -+#define DUMP_Print XX_Print -+#define DUMP_MAX_LEVELS 6 -+#define DUMP_IDX_LEN 6 -+#define DUMP_MAX_STR 64 -+ -+ -+#define _CREATE_DUMP_SUBSTR(phrase) \ -+ dumpTmpLevel = 0; dumpSubStr[0] = '\0'; \ -+ snprintf(dumpTmpStr, DUMP_MAX_STR, "%s", #phrase); \ -+ p_DumpToken = strtok(dumpTmpStr, (dumpIsArr[0] ? "[" : ".")); \ -+ while ((p_DumpToken != NULL) && (dumpTmpLevel < DUMP_MAX_LEVELS)) \ -+ { \ -+ strlcat(dumpSubStr, p_DumpToken, DUMP_MAX_STR); \ -+ if (dumpIsArr[dumpTmpLevel]) \ -+ { \ -+ strlcat(dumpSubStr, dumpIdxStr[dumpTmpLevel], DUMP_MAX_STR); \ -+ p_DumpToken = strtok(NULL, "."); \ -+ } \ -+ if ((p_DumpToken != NULL) && \ -+ ((p_DumpToken = strtok(NULL, (dumpIsArr[++dumpTmpLevel] ? "[" : "."))) != NULL)) \ -+ strlcat(dumpSubStr, ".", DUMP_MAX_STR); \ -+ } -+ -+ -+/**************************************************************************//** -+ @Group gen_id General Drivers Utilities -+ -+ @Description External routines. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group dump_id Memory and Registers Dump Mechanism -+ -+ @Description Macros for dumping memory mapped structures. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description Declaration of dump mechanism variables. -+ -+ This macro must be declared at the beginning of each routine -+ which uses the dump mechanism macros, before the routine's code -+ starts. -+*//***************************************************************************/ -+#define DECLARE_DUMP \ -+ char dumpIdxStr[DUMP_MAX_LEVELS + 1][DUMP_IDX_LEN] = { "", }; \ -+ char dumpSubStr[DUMP_MAX_STR] = ""; \ -+ char dumpTmpStr[DUMP_MAX_STR] = ""; \ -+ char *p_DumpToken = NULL; \ -+ int dumpArrIdx = 0, dumpArrSize = 0, dumpLevel = 0, dumpTmpLevel = 0; \ -+ uint8_t dumpIsArr[DUMP_MAX_LEVELS + 1] = { 0 }; \ -+ /* Prevent warnings if not all used */ \ -+ UNUSED(dumpIdxStr[0][0]); \ -+ UNUSED(dumpSubStr[0]); \ -+ UNUSED(dumpTmpStr[0]); \ -+ UNUSED(p_DumpToken); \ -+ UNUSED(dumpArrIdx); \ -+ UNUSED(dumpArrSize); \ -+ UNUSED(dumpLevel); \ -+ UNUSED(dumpTmpLevel); \ -+ UNUSED(dumpIsArr[0]); -+ -+ -+/**************************************************************************//** -+ @Description Prints a title for a subsequent dumped structure or memory. -+ -+ The inputs for this macro are the structure/memory title and -+ its base addresses. -+*//***************************************************************************/ -+#define DUMP_TITLE(addr, msg) \ -+ DUMP_Print("\r\n"); DUMP_Print msg; \ -+ if (addr) \ -+ DUMP_Print(" (%p)", (addr)); \ -+ DUMP_Print("\r\n---------------------------------------------------------\r\n"); -+ -+/**************************************************************************//** -+ @Description Prints a subtitle for a subsequent dumped sub-structure (optional). -+ -+ The inputs for this macro are the sub-structure subtitle. -+ A separating line with this subtitle will be printed. -+*//***************************************************************************/ -+#define DUMP_SUBTITLE(subtitle) \ -+ DUMP_Print("----------- "); DUMP_Print subtitle; DUMP_Print("\r\n") -+ -+ -+/**************************************************************************//** -+ @Description Dumps a memory region in 4-bytes aligned format. -+ -+ The inputs for this macro are the base addresses and size -+ (in bytes) of the memory region. -+*//***************************************************************************/ -+#define DUMP_MEMORY(addr, size) \ -+ MemDisp((uint8_t *)(addr), (int)(size)) -+ -+ -+/**************************************************************************//** -+ @Description Declares a dump loop, for dumping a sub-structure array. -+ -+ The inputs for this macro are: -+ - idx: an index variable, for indexing the sub-structure items -+ inside the loop. This variable must be declared separately -+ in the beginning of the routine. -+ - cnt: the number of times to repeat the loop. This number should -+ equal the number of items in the sub-structures array. -+ -+ Note, that the body of the loop must be written inside brackets. -+*//***************************************************************************/ -+#define DUMP_SUBSTRUCT_ARRAY(idx, cnt) \ -+ for (idx=0, dumpIsArr[dumpLevel++] = 1; \ -+ (idx < cnt) && (dumpLevel > 0) && snprintf(dumpIdxStr[dumpLevel-1], DUMP_IDX_LEN, "[%d]", idx); \ -+ idx++, ((idx < cnt) || (dumpIsArr[--dumpLevel] = 0))) -+ -+ -+/**************************************************************************//** -+ @Description Dumps a structure's member variable. -+ -+ The input for this macro is the full reference for the member -+ variable, where the structure is referenced using a pointer. -+ -+ Note, that a members array must be dumped using DUMP_ARR macro, -+ rather than using this macro. -+ -+ If the member variable is part of a sub-structure hierarchy, -+ the full hierarchy (including array indexing) must be specified. -+ -+ Examples: p_Struct->member -+ p_Struct->sub.member -+ p_Struct->sub[i].member -+*//***************************************************************************/ -+#define DUMP_VAR(st, phrase) \ -+ do { \ -+ void *addr = (void *)&((st)->phrase); \ -+ physAddress_t physAddr = XX_VirtToPhys(addr); \ -+ _CREATE_DUMP_SUBSTR(phrase); \ -+ DUMP_Print("0x%010llX: 0x%08x%8s\t%s\r\n", \ -+ physAddr, GET_UINT32(*(uint32_t*)addr), "", dumpSubStr); \ -+ } while (0) -+ -+ -+/**************************************************************************//** -+ @Description Dumps a structure's members array. -+ -+ The input for this macro is the full reference for the members -+ array, where the structure is referenced using a pointer. -+ -+ If the members array is part of a sub-structure hierarchy, -+ the full hierarchy (including array indexing) must be specified. -+ -+ Examples: p_Struct->array -+ p_Struct->sub.array -+ p_Struct->sub[i].array -+*//***************************************************************************/ -+#define DUMP_ARR(st, phrase) \ -+ do { \ -+ physAddress_t physAddr; \ -+ _CREATE_DUMP_SUBSTR(phrase); \ -+ dumpArrSize = ARRAY_SIZE((st)->phrase); \ -+ for (dumpArrIdx=0; dumpArrIdx < dumpArrSize; dumpArrIdx++) { \ -+ physAddr = XX_VirtToPhys((void *)&((st)->phrase[dumpArrIdx])); \ -+ DUMP_Print("0x%010llX: 0x%08x%8s\t%s[%d]\r\n", \ -+ physAddr, GET_UINT32((st)->phrase[dumpArrIdx]), "", dumpSubStr, dumpArrIdx); \ -+ } \ -+ } while (0) -+ -+ -+ -+#endif /* DEBUG_ERRORS > 0 */ -+ -+ -+/** @} */ /* end of dump_id group */ -+/** @} */ /* end of gen_id group */ -+ -+ -+#endif /* __DEBUG_EXT_H */ -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/endian_ext.h -@@ -0,0 +1,447 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ -+ @File endian_ext.h -+ -+ @Description Big/little endian swapping routines. -+*//***************************************************************************/ -+ -+#ifndef __ENDIAN_EXT_H -+#define __ENDIAN_EXT_H -+ -+#include "std_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group gen_id General Drivers Utilities -+ -+ @Description General usage API. This API is intended for usage by both the -+ internal modules and the user's application. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group endian_id Big/Little-Endian Conversion -+ -+ @Description Routines and macros for Big/Little-Endian conversion and -+ general byte swapping. -+ -+ All routines and macros are expecting unsigned values as -+ parameters, but will generate the correct result also for -+ signed values. Therefore, signed/unsigned casting is allowed. -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Collection Byte-Swap Macros -+ -+ Macros for swapping byte order. -+ -+ @Cautions The parameters of these macros are evaluated multiple times. -+ For calculated expressions or expressions that contain function -+ calls it is recommended to use the byte-swap routines. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description Swaps the byte order of a given 16-bit value. -+ -+ @Param[in] val - The 16-bit value to swap. -+ -+ @Return The byte-swapped value.. -+ -+ @Cautions The given value is evaluated multiple times by this macro. -+ For calculated expressions or expressions that contain function -+ calls it is recommended to use the SwapUint16() routine. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define SWAP_UINT16(val) \ -+ ((uint16_t)((((val) & 0x00FF) << 8) | (((val) & 0xFF00) >> 8))) -+ -+/**************************************************************************//** -+ @Description Swaps the byte order of a given 32-bit value. -+ -+ @Param[in] val - The 32-bit value to swap. -+ -+ @Return The byte-swapped value.. -+ -+ @Cautions The given value is evaluated multiple times by this macro. -+ For calculated expressions or expressions that contain function -+ calls it is recommended to use the SwapUint32() routine. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define SWAP_UINT32(val) \ -+ ((uint32_t)((((val) & 0x000000FF) << 24) | \ -+ (((val) & 0x0000FF00) << 8) | \ -+ (((val) & 0x00FF0000) >> 8) | \ -+ (((val) & 0xFF000000) >> 24))) -+ -+/**************************************************************************//** -+ @Description Swaps the byte order of a given 64-bit value. -+ -+ @Param[in] val - The 64-bit value to swap. -+ -+ @Return The byte-swapped value.. -+ -+ @Cautions The given value is evaluated multiple times by this macro. -+ For calculated expressions or expressions that contain function -+ calls it is recommended to use the SwapUint64() routine. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define SWAP_UINT64(val) \ -+ ((uint64_t)((((val) & 0x00000000000000FFULL) << 56) | \ -+ (((val) & 0x000000000000FF00ULL) << 40) | \ -+ (((val) & 0x0000000000FF0000ULL) << 24) | \ -+ (((val) & 0x00000000FF000000ULL) << 8) | \ -+ (((val) & 0x000000FF00000000ULL) >> 8) | \ -+ (((val) & 0x0000FF0000000000ULL) >> 24) | \ -+ (((val) & 0x00FF000000000000ULL) >> 40) | \ -+ (((val) & 0xFF00000000000000ULL) >> 56))) -+ -+/* @} */ -+ -+/**************************************************************************//** -+ @Collection Byte-Swap Routines -+ -+ Routines for swapping the byte order of a given parameter and -+ returning the swapped value. -+ -+ These inline routines are safer than the byte-swap macros, -+ because they evaluate the parameter expression only once. -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function SwapUint16 -+ -+ @Description Returns the byte-swapped value of a given 16-bit value. -+ -+ @Param[in] val - The 16-bit value. -+ -+ @Return The byte-swapped value of the parameter. -+*//***************************************************************************/ -+static __inline__ uint16_t SwapUint16(uint16_t val) -+{ -+ return (uint16_t)(((val & 0x00FF) << 8) | -+ ((val & 0xFF00) >> 8)); -+} -+ -+/**************************************************************************//** -+ @Function SwapUint32 -+ -+ @Description Returns the byte-swapped value of a given 32-bit value. -+ -+ @Param[in] val - The 32-bit value. -+ -+ @Return The byte-swapped value of the parameter. -+*//***************************************************************************/ -+static __inline__ uint32_t SwapUint32(uint32_t val) -+{ -+ return (uint32_t)(((val & 0x000000FF) << 24) | -+ ((val & 0x0000FF00) << 8) | -+ ((val & 0x00FF0000) >> 8) | -+ ((val & 0xFF000000) >> 24)); -+} -+ -+/**************************************************************************//** -+ @Function SwapUint64 -+ -+ @Description Returns the byte-swapped value of a given 64-bit value. -+ -+ @Param[in] val - The 64-bit value. -+ -+ @Return The byte-swapped value of the parameter. -+*//***************************************************************************/ -+static __inline__ uint64_t SwapUint64(uint64_t val) -+{ -+ return (uint64_t)(((val & 0x00000000000000FFULL) << 56) | -+ ((val & 0x000000000000FF00ULL) << 40) | -+ ((val & 0x0000000000FF0000ULL) << 24) | -+ ((val & 0x00000000FF000000ULL) << 8) | -+ ((val & 0x000000FF00000000ULL) >> 8) | -+ ((val & 0x0000FF0000000000ULL) >> 24) | -+ ((val & 0x00FF000000000000ULL) >> 40) | -+ ((val & 0xFF00000000000000ULL) >> 56)); -+} -+ -+/* @} */ -+ -+/**************************************************************************//** -+ @Collection In-place Byte-Swap-And-Set Routines -+ -+ Routines for swapping the byte order of a given variable and -+ setting the swapped value back to the same variable. -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function SwapUint16P -+ -+ @Description Swaps the byte order of a given 16-bit variable. -+ -+ @Param[in] p_Val - Pointer to the 16-bit variable. -+ -+ @Return None. -+*//***************************************************************************/ -+static __inline__ void SwapUint16P(uint16_t *p_Val) -+{ -+ *p_Val = SwapUint16(*p_Val); -+} -+ -+/**************************************************************************//** -+ @Function SwapUint32P -+ -+ @Description Swaps the byte order of a given 32-bit variable. -+ -+ @Param[in] p_Val - Pointer to the 32-bit variable. -+ -+ @Return None. -+*//***************************************************************************/ -+static __inline__ void SwapUint32P(uint32_t *p_Val) -+{ -+ *p_Val = SwapUint32(*p_Val); -+} -+ -+/**************************************************************************//** -+ @Function SwapUint64P -+ -+ @Description Swaps the byte order of a given 64-bit variable. -+ -+ @Param[in] p_Val - Pointer to the 64-bit variable. -+ -+ @Return None. -+*//***************************************************************************/ -+static __inline__ void SwapUint64P(uint64_t *p_Val) -+{ -+ *p_Val = SwapUint64(*p_Val); -+} -+ -+/* @} */ -+ -+ -+/**************************************************************************//** -+ @Collection Little-Endian Conversion Macros -+ -+ These macros convert given parameters to or from Little-Endian -+ format. Use these macros when you want to read or write a specific -+ Little-Endian value in memory, without a-priori knowing the CPU -+ byte order. -+ -+ These macros use the byte-swap routines. For conversion of -+ constants in initialization structures, you may use the CONST -+ versions of these macros (see below), which are using the -+ byte-swap macros instead. -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description Converts a given 16-bit value from CPU byte order to -+ Little-Endian byte order. -+ -+ @Param[in] val - The 16-bit value to convert. -+ -+ @Return The converted value. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define CPU_TO_LE16(val) SwapUint16(val) -+ -+/**************************************************************************//** -+ @Description Converts a given 32-bit value from CPU byte order to -+ Little-Endian byte order. -+ -+ @Param[in] val - The 32-bit value to convert. -+ -+ @Return The converted value. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define CPU_TO_LE32(val) SwapUint32(val) -+ -+/**************************************************************************//** -+ @Description Converts a given 64-bit value from CPU byte order to -+ Little-Endian byte order. -+ -+ @Param[in] val - The 64-bit value to convert. -+ -+ @Return The converted value. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define CPU_TO_LE64(val) SwapUint64(val) -+ -+ -+/**************************************************************************//** -+ @Description Converts a given 16-bit value from Little-Endian byte order to -+ CPU byte order. -+ -+ @Param[in] val - The 16-bit value to convert. -+ -+ @Return The converted value. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define LE16_TO_CPU(val) CPU_TO_LE16(val) -+ -+/**************************************************************************//** -+ @Description Converts a given 32-bit value from Little-Endian byte order to -+ CPU byte order. -+ -+ @Param[in] val - The 32-bit value to convert. -+ -+ @Return The converted value. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define LE32_TO_CPU(val) CPU_TO_LE32(val) -+ -+/**************************************************************************//** -+ @Description Converts a given 64-bit value from Little-Endian byte order to -+ CPU byte order. -+ -+ @Param[in] val - The 64-bit value to convert. -+ -+ @Return The converted value. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define LE64_TO_CPU(val) CPU_TO_LE64(val) -+ -+/* @} */ -+ -+/**************************************************************************//** -+ @Collection Little-Endian Constant Conversion Macros -+ -+ These macros convert given constants to or from Little-Endian -+ format. Use these macros when you want to read or write a specific -+ Little-Endian constant in memory, without a-priori knowing the -+ CPU byte order. -+ -+ These macros use the byte-swap macros, therefore can be used for -+ conversion of constants in initialization structures. -+ -+ @Cautions The parameters of these macros are evaluated multiple times. -+ For non-constant expressions, use the non-CONST macro versions. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description Converts a given 16-bit constant from CPU byte order to -+ Little-Endian byte order. -+ -+ @Param[in] val - The 16-bit value to convert. -+ -+ @Return The converted value. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define CONST_CPU_TO_LE16(val) SWAP_UINT16(val) -+ -+/**************************************************************************//** -+ @Description Converts a given 32-bit constant from CPU byte order to -+ Little-Endian byte order. -+ -+ @Param[in] val - The 32-bit value to convert. -+ -+ @Return The converted value. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define CONST_CPU_TO_LE32(val) SWAP_UINT32(val) -+ -+/**************************************************************************//** -+ @Description Converts a given 64-bit constant from CPU byte order to -+ Little-Endian byte order. -+ -+ @Param[in] val - The 64-bit value to convert. -+ -+ @Return The converted value. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define CONST_CPU_TO_LE64(val) SWAP_UINT64(val) -+ -+ -+/**************************************************************************//** -+ @Description Converts a given 16-bit constant from Little-Endian byte order -+ to CPU byte order. -+ -+ @Param[in] val - The 16-bit value to convert. -+ -+ @Return The converted value. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define CONST_LE16_TO_CPU(val) CONST_CPU_TO_LE16(val) -+ -+/**************************************************************************//** -+ @Description Converts a given 32-bit constant from Little-Endian byte order -+ to CPU byte order. -+ -+ @Param[in] val - The 32-bit value to convert. -+ -+ @Return The converted value. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define CONST_LE32_TO_CPU(val) CONST_CPU_TO_LE32(val) -+ -+/**************************************************************************//** -+ @Description Converts a given 64-bit constant from Little-Endian byte order -+ to CPU byte order. -+ -+ @Param[in] val - The 64-bit value to convert. -+ -+ @Return The converted value. -+ -+ @hideinitializer -+*//***************************************************************************/ -+#define CONST_LE64_TO_CPU(val) CONST_CPU_TO_LE64(val) -+ -+/* @} */ -+ -+ -+/** @} */ /* end of endian_id group */ -+/** @} */ /* end of gen_id group */ -+ -+ -+#endif /* __ENDIAN_EXT_H */ -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/enet_ext.h -@@ -0,0 +1,205 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File enet_ext.h -+ -+ @Description Ethernet generic definitions and enums. -+*//***************************************************************************/ -+ -+#ifndef __ENET_EXT_H -+#define __ENET_EXT_H -+ -+#include "fsl_enet.h" -+ -+#define ENET_NUM_OCTETS_PER_ADDRESS 6 /**< Number of octets (8-bit bytes) in an ethernet address */ -+#define ENET_GROUP_ADDR 0x01 /**< Group address mask for ethernet addresses */ -+ -+ -+/**************************************************************************//** -+ @Description Ethernet Address -+*//***************************************************************************/ -+typedef uint8_t t_EnetAddr[ENET_NUM_OCTETS_PER_ADDRESS]; -+ -+/**************************************************************************//** -+ @Description Ethernet Address Type. -+*//***************************************************************************/ -+typedef enum e_EnetAddrType -+{ -+ e_ENET_ADDR_TYPE_INDIVIDUAL, /**< Individual (unicast) address */ -+ e_ENET_ADDR_TYPE_GROUP, /**< Group (multicast) address */ -+ e_ENET_ADDR_TYPE_BROADCAST /**< Broadcast address */ -+} e_EnetAddrType; -+ -+/**************************************************************************//** -+ @Description Ethernet MAC-PHY Interface -+*//***************************************************************************/ -+typedef enum e_EnetInterface -+{ -+ e_ENET_IF_MII = E_ENET_IF_MII, /**< MII interface */ -+ e_ENET_IF_RMII = E_ENET_IF_RMII, /**< RMII interface */ -+ e_ENET_IF_SMII = E_ENET_IF_SMII, /**< SMII interface */ -+ e_ENET_IF_GMII = E_ENET_IF_GMII, /**< GMII interface */ -+ e_ENET_IF_RGMII = E_ENET_IF_RGMII, /**< RGMII interface */ -+ e_ENET_IF_TBI = E_ENET_IF_TBI, /**< TBI interface */ -+ e_ENET_IF_RTBI = E_ENET_IF_RTBI, /**< RTBI interface */ -+ e_ENET_IF_SGMII = E_ENET_IF_SGMII, /**< SGMII interface */ -+ e_ENET_IF_XGMII = E_ENET_IF_XGMII, /**< XGMII interface */ -+ e_ENET_IF_QSGMII= E_ENET_IF_QSGMII, /**< QSGMII interface */ -+ e_ENET_IF_XFI = E_ENET_IF_XFI /**< XFI interface */ -+} e_EnetInterface; -+ -+#define ENET_IF_SGMII_BASEX 0x80000000 /**< SGMII/QSGII interface with 1000BaseX -+ auto-negotiation between MAC and phy -+ or backplane; -+ Note: 1000BaseX auto-negotiation relates -+ only to interface between MAC and phy/backplane, -+ SGMII phy can still synchronize with far-end phy -+ at 10Mbps, 100Mbps or 1000Mbps */ -+ -+/**************************************************************************//** -+ @Description Ethernet Duplex Mode -+*//***************************************************************************/ -+typedef enum e_EnetDuplexMode -+{ -+ e_ENET_HALF_DUPLEX, /**< Half-Duplex mode */ -+ e_ENET_FULL_DUPLEX /**< Full-Duplex mode */ -+} e_EnetDuplexMode; -+ -+/**************************************************************************//** -+ @Description Ethernet Speed (nominal data rate) -+*//***************************************************************************/ -+typedef enum e_EnetSpeed -+{ -+ e_ENET_SPEED_10 = E_ENET_SPEED_10, /**< 10 Mbps */ -+ e_ENET_SPEED_100 = E_ENET_SPEED_100, /**< 100 Mbps */ -+ e_ENET_SPEED_1000 = E_ENET_SPEED_1000, /**< 1000 Mbps = 1 Gbps */ -+ e_ENET_SPEED_2500 = E_ENET_SPEED_2500, /**< 2500 Mbps = 2.5 Gbps */ -+ e_ENET_SPEED_10000 = E_ENET_SPEED_10000 /**< 10000 Mbps = 10 Gbps */ -+} e_EnetSpeed; -+ -+/**************************************************************************//** -+ @Description Ethernet mode (combination of MAC-PHY interface and speed) -+*//***************************************************************************/ -+typedef enum e_EnetMode -+{ -+ e_ENET_MODE_INVALID = 0, /**< Invalid Ethernet mode */ -+ e_ENET_MODE_MII_10 = (e_ENET_IF_MII | e_ENET_SPEED_10), /**< 10 Mbps MII */ -+ e_ENET_MODE_MII_100 = (e_ENET_IF_MII | e_ENET_SPEED_100), /**< 100 Mbps MII */ -+ e_ENET_MODE_RMII_10 = (e_ENET_IF_RMII | e_ENET_SPEED_10), /**< 10 Mbps RMII */ -+ e_ENET_MODE_RMII_100 = (e_ENET_IF_RMII | e_ENET_SPEED_100), /**< 100 Mbps RMII */ -+ e_ENET_MODE_SMII_10 = (e_ENET_IF_SMII | e_ENET_SPEED_10), /**< 10 Mbps SMII */ -+ e_ENET_MODE_SMII_100 = (e_ENET_IF_SMII | e_ENET_SPEED_100), /**< 100 Mbps SMII */ -+ e_ENET_MODE_GMII_1000 = (e_ENET_IF_GMII | e_ENET_SPEED_1000), /**< 1000 Mbps GMII */ -+ e_ENET_MODE_RGMII_10 = (e_ENET_IF_RGMII | e_ENET_SPEED_10), /**< 10 Mbps RGMII */ -+ e_ENET_MODE_RGMII_100 = (e_ENET_IF_RGMII | e_ENET_SPEED_100), /**< 100 Mbps RGMII */ -+ e_ENET_MODE_RGMII_1000 = (e_ENET_IF_RGMII | e_ENET_SPEED_1000), /**< 1000 Mbps RGMII */ -+ e_ENET_MODE_TBI_1000 = (e_ENET_IF_TBI | e_ENET_SPEED_1000), /**< 1000 Mbps TBI */ -+ e_ENET_MODE_RTBI_1000 = (e_ENET_IF_RTBI | e_ENET_SPEED_1000), /**< 1000 Mbps RTBI */ -+ e_ENET_MODE_SGMII_10 = (e_ENET_IF_SGMII | e_ENET_SPEED_10), -+ /**< 10 Mbps SGMII with auto-negotiation between MAC and -+ SGMII phy according to Cisco SGMII specification */ -+ e_ENET_MODE_SGMII_100 = (e_ENET_IF_SGMII | e_ENET_SPEED_100), -+ /**< 100 Mbps SGMII with auto-negotiation between MAC and -+ SGMII phy according to Cisco SGMII specification */ -+ e_ENET_MODE_SGMII_1000 = (e_ENET_IF_SGMII | e_ENET_SPEED_1000), -+ /**< 1000 Mbps SGMII with auto-negotiation between MAC and -+ SGMII phy according to Cisco SGMII specification */ -+ e_ENET_MODE_SGMII_2500 = (e_ENET_IF_SGMII | e_ENET_SPEED_2500), -+ e_ENET_MODE_SGMII_BASEX_10 = (ENET_IF_SGMII_BASEX | e_ENET_IF_SGMII | e_ENET_SPEED_10), -+ /**< 10 Mbps SGMII with 1000BaseX auto-negotiation between -+ MAC and SGMII phy or backplane */ -+ e_ENET_MODE_SGMII_BASEX_100 = (ENET_IF_SGMII_BASEX | e_ENET_IF_SGMII | e_ENET_SPEED_100), -+ /**< 100 Mbps SGMII with 1000BaseX auto-negotiation between -+ MAC and SGMII phy or backplane */ -+ e_ENET_MODE_SGMII_BASEX_1000 = (ENET_IF_SGMII_BASEX | e_ENET_IF_SGMII | e_ENET_SPEED_1000), -+ /**< 1000 Mbps SGMII with 1000BaseX auto-negotiation between -+ MAC and SGMII phy or backplane */ -+ e_ENET_MODE_QSGMII_1000 = (e_ENET_IF_QSGMII| e_ENET_SPEED_1000), -+ /**< 1000 Mbps QSGMII with auto-negotiation between MAC and -+ QSGMII phy according to Cisco QSGMII specification */ -+ e_ENET_MODE_QSGMII_BASEX_1000 = (ENET_IF_SGMII_BASEX | e_ENET_IF_QSGMII| e_ENET_SPEED_1000), -+ /**< 1000 Mbps QSGMII with 1000BaseX auto-negotiation between -+ MAC and QSGMII phy or backplane */ -+ e_ENET_MODE_XGMII_10000 = (e_ENET_IF_XGMII | e_ENET_SPEED_10000), /**< 10000 Mbps XGMII */ -+ e_ENET_MODE_XFI_10000 = (e_ENET_IF_XFI | e_ENET_SPEED_10000) /**< 10000 Mbps XFI */ -+} e_EnetMode; -+ -+ -+#define IS_ENET_MODE_VALID(mode) \ -+ (((mode) == e_ENET_MODE_MII_10 ) || \ -+ ((mode) == e_ENET_MODE_MII_100 ) || \ -+ ((mode) == e_ENET_MODE_RMII_10 ) || \ -+ ((mode) == e_ENET_MODE_RMII_100 ) || \ -+ ((mode) == e_ENET_MODE_SMII_10 ) || \ -+ ((mode) == e_ENET_MODE_SMII_100 ) || \ -+ ((mode) == e_ENET_MODE_GMII_1000 ) || \ -+ ((mode) == e_ENET_MODE_RGMII_10 ) || \ -+ ((mode) == e_ENET_MODE_RGMII_100 ) || \ -+ ((mode) == e_ENET_MODE_RGMII_1000 ) || \ -+ ((mode) == e_ENET_MODE_TBI_1000 ) || \ -+ ((mode) == e_ENET_MODE_RTBI_1000 ) || \ -+ ((mode) == e_ENET_MODE_SGMII_10 ) || \ -+ ((mode) == e_ENET_MODE_SGMII_100 ) || \ -+ ((mode) == e_ENET_MODE_SGMII_1000 ) || \ -+ ((mode) == e_ENET_MODE_SGMII_BASEX_10 ) || \ -+ ((mode) == e_ENET_MODE_SGMII_BASEX_100 ) || \ -+ ((mode) == e_ENET_MODE_SGMII_BASEX_1000 ) || \ -+ ((mode) == e_ENET_MODE_XGMII_10000) || \ -+ ((mode) == e_ENET_MODE_QSGMII_1000) || \ -+ ((mode) == e_ENET_MODE_QSGMII_BASEX_1000) || \ -+ ((mode) == e_ENET_MODE_XFI_10000)) -+ -+ -+#define MAKE_ENET_MODE(_interface, _speed) (e_EnetMode)((_interface) | (_speed)) -+ -+#define ENET_INTERFACE_FROM_MODE(mode) (e_EnetInterface)((mode) & 0x0FFF0000) -+#define ENET_SPEED_FROM_MODE(mode) (e_EnetSpeed)((mode) & 0x0000FFFF) -+ -+#define ENET_ADDR_TO_UINT64(_enetAddr) \ -+ (uint64_t)(((uint64_t)(_enetAddr)[0] << 40) | \ -+ ((uint64_t)(_enetAddr)[1] << 32) | \ -+ ((uint64_t)(_enetAddr)[2] << 24) | \ -+ ((uint64_t)(_enetAddr)[3] << 16) | \ -+ ((uint64_t)(_enetAddr)[4] << 8) | \ -+ ((uint64_t)(_enetAddr)[5])) -+ -+#define MAKE_ENET_ADDR_FROM_UINT64(_addr64, _enetAddr) \ -+ do { \ -+ int i; \ -+ for (i=0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++) \ -+ (_enetAddr)[i] = (uint8_t)((_addr64) >> ((5-i)*8)); \ -+ } while (0) -+ -+ -+#endif /* __ENET_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/error_ext.h -@@ -0,0 +1,529 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File error_ext.h -+ -+ @Description Error definitions. -+*//***************************************************************************/ -+ -+#ifndef __ERROR_EXT_H -+#define __ERROR_EXT_H -+ -+#if !defined(NCSW_LINUX) -+#include -+#endif -+ -+#include "std_ext.h" -+#include "xx_ext.h" -+#include "core_ext.h" -+ -+ -+ -+ -+/**************************************************************************//** -+ @Group gen_id General Drivers Utilities -+ -+ @Description External routines. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group gen_error_id Errors, Events and Debug -+ -+ @Description External routines. -+ -+ @{ -+*//***************************************************************************/ -+ -+/****************************************************************************** -+The scheme below provides the bits description for error codes: -+ -+ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -+| Reserved (should be zero) | Module ID | -+ -+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -+| Error Type | -+******************************************************************************/ -+ -+#define ERROR_CODE(_err) ((((uint32_t)_err) & 0x0000FFFF) | __ERR_MODULE__) -+ -+#define GET_ERROR_TYPE(_errcode) ((_errcode) & 0x0000FFFF) -+ /**< Extract module code from error code (#t_Error) */ -+ -+#define GET_ERROR_MODULE(_errcode) ((_errcode) & 0x00FF0000) -+ /**< Extract error type (#e_ErrorType) from -+ error code (#t_Error) */ -+ -+ -+/**************************************************************************//** -+ @Description Error Type Enumeration -+*//***************************************************************************/ -+typedef enum e_ErrorType /* Comments / Associated Message Strings */ -+{ /* ------------------------------------------------------------ */ -+ E_OK = 0 /* Never use "RETURN_ERROR" with E_OK; Use "return E_OK;" */ -+ ,E_WRITE_FAILED = EIO /**< Write access failed on memory/device. */ -+ /* String: none, or device name. */ -+ ,E_NO_DEVICE = ENXIO /**< The associated device is not initialized. */ -+ /* String: none. */ -+ ,E_NOT_AVAILABLE = EAGAIN -+ /**< Resource is unavailable. */ -+ /* String: none, unless the operation is not the main goal -+ of the function (in this case add resource description). */ -+ ,E_NO_MEMORY = ENOMEM /**< External memory allocation failed. */ -+ /* String: description of item for which allocation failed. */ -+ ,E_INVALID_ADDRESS = EFAULT -+ /**< Invalid address. */ -+ /* String: description of the specific violation. */ -+ ,E_BUSY = EBUSY /**< Resource or module is busy. */ -+ /* String: none, unless the operation is not the main goal -+ of the function (in this case add resource description). */ -+ ,E_ALREADY_EXISTS = EEXIST -+ /**< Requested resource or item already exists. */ -+ /* Use when resource duplication or sharing are not allowed. -+ String: none, unless the operation is not the main goal -+ of the function (in this case add item description). */ -+ ,E_INVALID_OPERATION = ENODEV -+ /**< The operation/command is invalid (unrecognized). */ -+ /* String: none. */ -+ ,E_INVALID_VALUE = EDOM /**< Invalid value. */ -+ /* Use for non-enumeration parameters, and -+ only when other error types are not suitable. -+ String: parameter description + "(should be )", -+ e.g: "Maximum Rx buffer length (should be divisible by 8)", -+ "Channel number (should be even)". */ -+ ,E_NOT_IN_RANGE = ERANGE/**< Parameter value is out of range. */ -+ /* Don't use this error for enumeration parameters. -+ String: parameter description + "(should be %d-%d)", -+ e.g: "Number of pad characters (should be 0-15)". */ -+ ,E_NOT_SUPPORTED = ENOSYS -+ /**< The function is not supported or not implemented. */ -+ /* String: none. */ -+ ,E_INVALID_STATE /**< The operation is not allowed in current module state. */ -+ /* String: none. */ -+ ,E_INVALID_HANDLE /**< Invalid handle of module or object. */ -+ /* String: none, unless the function takes in more than one -+ handle (in this case add the handle description) */ -+ ,E_INVALID_ID /**< Invalid module ID (usually enumeration or index). */ -+ /* String: none, unless the function takes in more than one -+ ID (in this case add the ID description) */ -+ ,E_NULL_POINTER /**< Unexpected NULL pointer. */ -+ /* String: pointer description. */ -+ ,E_INVALID_SELECTION /**< Invalid selection or mode. */ -+ /* Use for enumeration values, only when other error types -+ are not suitable. -+ String: parameter description. */ -+ ,E_INVALID_COMM_MODE /**< Invalid communication mode. */ -+ /* String: none, unless the function takes in more than one -+ communication mode indications (in this case add -+ parameter description). */ -+ ,E_INVALID_MEMORY_TYPE /**< Invalid memory type. */ -+ /* String: none, unless the function takes in more than one -+ memory types (in this case add memory description, -+ e.g: "Data memory", "Buffer descriptors memory"). */ -+ ,E_INVALID_CLOCK /**< Invalid clock. */ -+ /* String: none, unless the function takes in more than one -+ clocks (in this case add clock description, -+ e.g: "Rx clock", "Tx clock"). */ -+ ,E_CONFLICT /**< Some setting conflicts with another setting. */ -+ /* String: description of the conflicting settings. */ -+ ,E_NOT_ALIGNED /**< Non-aligned address. */ -+ /* String: parameter description + "(should be %d-bytes aligned)", -+ e.g: "Rx data buffer (should be 32-bytes aligned)". */ -+ ,E_NOT_FOUND /**< Requested resource or item was not found. */ -+ /* Use only when the resource/item is uniquely identified. -+ String: none, unless the operation is not the main goal -+ of the function (in this case add item description). */ -+ ,E_FULL /**< Resource is full. */ -+ /* String: none, unless the operation is not the main goal -+ of the function (in this case add resource description). */ -+ ,E_EMPTY /**< Resource is empty. */ -+ /* String: none, unless the operation is not the main goal -+ of the function (in this case add resource description). */ -+ ,E_ALREADY_FREE /**< Specified resource or item is already free or deleted. */ -+ /* String: none, unless the operation is not the main goal -+ of the function (in this case add item description). */ -+ ,E_READ_FAILED /**< Read access failed on memory/device. */ -+ /* String: none, or device name. */ -+ ,E_INVALID_FRAME /**< Invalid frame object (NULL handle or missing buffers). */ -+ /* String: none. */ -+ ,E_SEND_FAILED /**< Send operation failed on device. */ -+ /* String: none, or device name. */ -+ ,E_RECEIVE_FAILED /**< Receive operation failed on device. */ -+ /* String: none, or device name. */ -+ ,E_TIMEOUT/* = ETIMEDOUT*/ /**< The operation timed out. */ -+ /* String: none. */ -+ -+ ,E_DUMMY_LAST /* NEVER USED */ -+ -+} e_ErrorType; -+ -+/**************************************************************************//** -+ @Description Event Type Enumeration -+*//***************************************************************************/ -+typedef enum e_Event /* Comments / Associated Flags and Message Strings */ -+{ /* ------------------------------------------------------------ */ -+ EV_NO_EVENT = 0 /**< No event; Never used. */ -+ -+ ,EV_RX_DISCARD /**< Received packet discarded (by the driver, and only for -+ complete packets); -+ Flags: error flags in case of error, zero otherwise. */ -+ /* String: reason for discard, e.g: "Error in frame", -+ "Disordered frame", "Incomplete frame", "No frame object". */ -+ ,EV_RX_ERROR /**< Receive error (by hardware/firmware); -+ Flags: usually status flags from the buffer descriptor. */ -+ /* String: none. */ -+ ,EV_TX_ERROR /**< Transmit error (by hardware/firmware); -+ Flags: usually status flags from the buffer descriptor. */ -+ /* String: none. */ -+ ,EV_NO_BUFFERS /**< System ran out of buffer objects; -+ Flags: zero. */ -+ /* String: none. */ -+ ,EV_NO_MB_FRAMES /**< System ran out of multi-buffer frame objects; -+ Flags: zero. */ -+ /* String: none. */ -+ ,EV_NO_SB_FRAMES /**< System ran out of single-buffer frame objects; -+ Flags: zero. */ -+ /* String: none. */ -+ ,EV_TX_QUEUE_FULL /**< Transmit queue is full; -+ Flags: zero. */ -+ /* String: none. */ -+ ,EV_RX_QUEUE_FULL /**< Receive queue is full; -+ Flags: zero. */ -+ /* String: none. */ -+ ,EV_INTR_QUEUE_FULL /**< Interrupt queue overflow; -+ Flags: zero. */ -+ /* String: none. */ -+ ,EV_NO_DATA_BUFFER /**< Data buffer allocation (from higher layer) failed; -+ Flags: zero. */ -+ /* String: none. */ -+ ,EV_OBJ_POOL_EMPTY /**< Objects pool is empty; -+ Flags: zero. */ -+ /* String: object description (name). */ -+ ,EV_BUS_ERROR /**< Illegal access on bus; -+ Flags: the address (if available) or bus identifier */ -+ /* String: bus/address/module description. */ -+ ,EV_PTP_TXTS_QUEUE_FULL /**< PTP Tx timestamps queue is full; -+ Flags: zero. */ -+ /* String: none. */ -+ ,EV_PTP_RXTS_QUEUE_FULL /**< PTP Rx timestamps queue is full; -+ Flags: zero. */ -+ /* String: none. */ -+ ,EV_DUMMY_LAST -+ -+} e_Event; -+ -+ -+/**************************************************************************//** -+ @Collection Debug Levels for Errors and Events -+ -+ The level description refers to errors only. -+ For events, classification is done by the user. -+ -+ The TRACE, INFO and WARNING levels are allowed only when using -+ the DBG macro, and are not allowed when using the error macros -+ (RETURN_ERROR or REPORT_ERROR). -+ @{ -+*//***************************************************************************/ -+#define REPORT_LEVEL_CRITICAL 1 /**< Crasher: Incorrect flow, NULL pointers/handles. */ -+#define REPORT_LEVEL_MAJOR 2 /**< Cannot proceed: Invalid operation, parameters or -+ configuration. */ -+#define REPORT_LEVEL_MINOR 3 /**< Recoverable problem: a repeating call with the same -+ parameters may be successful. */ -+#define REPORT_LEVEL_WARNING 4 /**< Something is not exactly right, yet it is not an error. */ -+#define REPORT_LEVEL_INFO 5 /**< Messages which may be of interest to user/programmer. */ -+#define REPORT_LEVEL_TRACE 6 /**< Program flow messages. */ -+ -+#define EVENT_DISABLED 0xFF /**< Disabled event (not reported at all) */ -+ -+/* @} */ -+ -+ -+ -+#define NO_MSG ("") -+ -+#ifndef DEBUG_GLOBAL_LEVEL -+#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_WARNING -+#endif /* DEBUG_GLOBAL_LEVEL */ -+ -+#ifndef ERROR_GLOBAL_LEVEL -+#define ERROR_GLOBAL_LEVEL DEBUG_GLOBAL_LEVEL -+#endif /* ERROR_GLOBAL_LEVEL */ -+ -+#ifndef EVENT_GLOBAL_LEVEL -+#define EVENT_GLOBAL_LEVEL REPORT_LEVEL_MINOR -+#endif /* EVENT_GLOBAL_LEVEL */ -+ -+#ifdef EVENT_LOCAL_LEVEL -+#define EVENT_DYNAMIC_LEVEL EVENT_LOCAL_LEVEL -+#else -+#define EVENT_DYNAMIC_LEVEL EVENT_GLOBAL_LEVEL -+#endif /* EVENT_LOCAL_LEVEL */ -+ -+ -+#ifndef DEBUG_DYNAMIC_LEVEL -+#define DEBUG_USING_STATIC_LEVEL -+ -+#ifdef DEBUG_STATIC_LEVEL -+#define DEBUG_DYNAMIC_LEVEL DEBUG_STATIC_LEVEL -+#else -+#define DEBUG_DYNAMIC_LEVEL DEBUG_GLOBAL_LEVEL -+#endif /* DEBUG_STATIC_LEVEL */ -+ -+#else /* DEBUG_DYNAMIC_LEVEL */ -+#ifdef DEBUG_STATIC_LEVEL -+#error "Please use either DEBUG_STATIC_LEVEL or DEBUG_DYNAMIC_LEVEL (not both)" -+#else -+int DEBUG_DYNAMIC_LEVEL = DEBUG_GLOBAL_LEVEL; -+#endif /* DEBUG_STATIC_LEVEL */ -+#endif /* !DEBUG_DYNAMIC_LEVEL */ -+ -+ -+#ifndef ERROR_DYNAMIC_LEVEL -+ -+#ifdef ERROR_STATIC_LEVEL -+#define ERROR_DYNAMIC_LEVEL ERROR_STATIC_LEVEL -+#else -+#define ERROR_DYNAMIC_LEVEL ERROR_GLOBAL_LEVEL -+#endif /* ERROR_STATIC_LEVEL */ -+ -+#else /* ERROR_DYNAMIC_LEVEL */ -+#ifdef ERROR_STATIC_LEVEL -+#error "Please use either ERROR_STATIC_LEVEL or ERROR_DYNAMIC_LEVEL (not both)" -+#else -+int ERROR_DYNAMIC_LEVEL = ERROR_GLOBAL_LEVEL; -+#endif /* ERROR_STATIC_LEVEL */ -+#endif /* !ERROR_DYNAMIC_LEVEL */ -+ -+#define PRINT_FORMAT "[CPU%02d, %s:%d %s]" -+#define PRINT_FMT_PARAMS raw_smp_processor_id(), __FILE__, __LINE__, __FUNCTION__ -+ -+#if (!(defined(DEBUG_ERRORS)) || (DEBUG_ERRORS == 0)) -+/* No debug/error/event messages at all */ -+#define DBG(_level, _vmsg) -+ -+#define REPORT_ERROR(_level, _err, _vmsg) -+ -+#define RETURN_ERROR(_level, _err, _vmsg) \ -+ return ERROR_CODE(_err) -+ -+#if (REPORT_EVENTS > 0) -+ -+#define REPORT_EVENT(_ev, _appId, _flg, _vmsg) \ -+ do { \ -+ if (_ev##_LEVEL <= EVENT_DYNAMIC_LEVEL) { \ -+ XX_EventById((uint32_t)(_ev), (t_Handle)(_appId), (uint16_t)(_flg), NO_MSG); \ -+ } \ -+ } while (0) -+ -+#else -+ -+#define REPORT_EVENT(_ev, _appId, _flg, _vmsg) -+ -+#endif /* (REPORT_EVENTS > 0) */ -+ -+ -+#else /* DEBUG_ERRORS > 0 */ -+ -+extern const char *dbgLevelStrings[]; -+extern const char *moduleStrings[]; -+#if (REPORT_EVENTS > 0) -+extern const char *eventStrings[]; -+#endif /* (REPORT_EVENTS > 0) */ -+ -+char * ErrTypeStrings (e_ErrorType err); -+ -+ -+#if ((defined(DEBUG_USING_STATIC_LEVEL)) && (DEBUG_DYNAMIC_LEVEL < REPORT_LEVEL_WARNING)) -+/* No need for DBG macro - debug level is higher anyway */ -+#define DBG(_level, _vmsg) -+#else -+#define DBG(_level, _vmsg) \ -+ do { \ -+ if (REPORT_LEVEL_##_level <= DEBUG_DYNAMIC_LEVEL) { \ -+ XX_Print("> %s (%s) " PRINT_FORMAT ": ", \ -+ dbgLevelStrings[REPORT_LEVEL_##_level - 1], \ -+ moduleStrings[__ERR_MODULE__ >> 16], \ -+ PRINT_FMT_PARAMS); \ -+ XX_Print _vmsg; \ -+ XX_Print("\r\n"); \ -+ } \ -+ } while (0) -+#endif /* (defined(DEBUG_USING_STATIC_LEVEL) && (DEBUG_DYNAMIC_LEVEL < WARNING)) */ -+ -+ -+#define REPORT_ERROR(_level, _err, _vmsg) \ -+ do { \ -+ if (REPORT_LEVEL_##_level <= ERROR_DYNAMIC_LEVEL) { \ -+ XX_Print("! %s %s Error " PRINT_FORMAT ": %s; ", \ -+ dbgLevelStrings[REPORT_LEVEL_##_level - 1], \ -+ moduleStrings[__ERR_MODULE__ >> 16], \ -+ PRINT_FMT_PARAMS, \ -+ ErrTypeStrings((e_ErrorType)GET_ERROR_TYPE(_err))); \ -+ XX_Print _vmsg; \ -+ XX_Print("\r\n"); \ -+ } \ -+ } while (0) -+ -+ -+#define RETURN_ERROR(_level, _err, _vmsg) \ -+ do { \ -+ REPORT_ERROR(_level, (_err), _vmsg); \ -+ return ERROR_CODE(_err); \ -+ } while (0) -+ -+ -+#if (REPORT_EVENTS > 0) -+ -+#define REPORT_EVENT(_ev, _appId, _flg, _vmsg) \ -+ do { \ -+ if (_ev##_LEVEL <= EVENT_DYNAMIC_LEVEL) { \ -+ XX_Print("~ %s %s Event " PRINT_FORMAT ": %s (flags: 0x%04x); ", \ -+ dbgLevelStrings[_ev##_LEVEL - 1], \ -+ moduleStrings[__ERR_MODULE__ >> 16], \ -+ PRINT_FMT_PARAMS, \ -+ eventStrings[((_ev) - EV_NO_EVENT - 1)], \ -+ (uint16_t)(_flg)); \ -+ XX_Print _vmsg; \ -+ XX_Print("\r\n"); \ -+ XX_EventById((uint32_t)(_ev), (t_Handle)(_appId), (uint16_t)(_flg), NO_MSG); \ -+ } \ -+ } while (0) -+ -+#else /* not REPORT_EVENTS */ -+ -+#define REPORT_EVENT(_ev, _appId, _flg, _vmsg) -+ -+#endif /* (REPORT_EVENTS > 0) */ -+ -+#endif /* (DEBUG_ERRORS > 0) */ -+ -+ -+/**************************************************************************//** -+ @Function ASSERT_COND -+ -+ @Description Assertion macro. -+ -+ @Param[in] _cond - The condition being checked, in positive form; -+ Failure of the condition triggers the assert. -+*//***************************************************************************/ -+#ifdef DISABLE_ASSERTIONS -+#define ASSERT_COND(_cond) -+#else -+#define ASSERT_COND(_cond) \ -+ do { \ -+ if (!(_cond)) { \ -+ XX_Print("*** ASSERT_COND failed " PRINT_FORMAT "\r\n", \ -+ PRINT_FMT_PARAMS); \ -+ XX_Exit(1); \ -+ } \ -+ } while (0) -+#endif /* DISABLE_ASSERTIONS */ -+ -+ -+#ifdef DISABLE_INIT_PARAMETERS_CHECK -+ -+#define CHECK_INIT_PARAMETERS(handle, f_check) -+#define CHECK_INIT_PARAMETERS_RETURN_VALUE(handle, f_check, retval) -+ -+#else -+ -+#define CHECK_INIT_PARAMETERS(handle, f_check) \ -+ do { \ -+ t_Error err = f_check(handle); \ -+ if (err != E_OK) { \ -+ RETURN_ERROR(MAJOR, err, NO_MSG); \ -+ } \ -+ } while (0) -+ -+#define CHECK_INIT_PARAMETERS_RETURN_VALUE(handle, f_check, retval) \ -+ do { \ -+ t_Error err = f_check(handle); \ -+ if (err != E_OK) { \ -+ REPORT_ERROR(MAJOR, err, NO_MSG); \ -+ return (retval); \ -+ } \ -+ } while (0) -+ -+#endif /* DISABLE_INIT_PARAMETERS_CHECK */ -+ -+#ifdef DISABLE_SANITY_CHECKS -+ -+#define SANITY_CHECK_RETURN_ERROR(_cond, _err) -+#define SANITY_CHECK_RETURN_VALUE(_cond, _err, retval) -+#define SANITY_CHECK_RETURN(_cond, _err) -+#define SANITY_CHECK_EXIT(_cond, _err) -+ -+#else /* DISABLE_SANITY_CHECKS */ -+ -+#define SANITY_CHECK_RETURN_ERROR(_cond, _err) \ -+ do { \ -+ if (!(_cond)) { \ -+ RETURN_ERROR(CRITICAL, (_err), NO_MSG); \ -+ } \ -+ } while (0) -+ -+#define SANITY_CHECK_RETURN_VALUE(_cond, _err, retval) \ -+ do { \ -+ if (!(_cond)) { \ -+ REPORT_ERROR(CRITICAL, (_err), NO_MSG); \ -+ return (retval); \ -+ } \ -+ } while (0) -+ -+#define SANITY_CHECK_RETURN(_cond, _err) \ -+ do { \ -+ if (!(_cond)) { \ -+ REPORT_ERROR(CRITICAL, (_err), NO_MSG); \ -+ return; \ -+ } \ -+ } while (0) -+ -+#define SANITY_CHECK_EXIT(_cond, _err) \ -+ do { \ -+ if (!(_cond)) { \ -+ REPORT_ERROR(CRITICAL, (_err), NO_MSG); \ -+ XX_Exit(1); \ -+ } \ -+ } while (0) -+ -+#endif /* DISABLE_SANITY_CHECKS */ -+ -+/** @} */ /* end of Debug/error Utils group */ -+ -+/** @} */ /* end of General Utils group */ -+ -+#endif /* __ERROR_EXT_H */ -+ -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/etc/list_ext.h -@@ -0,0 +1,358 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ -+ @File list_ext.h -+ -+ @Description External prototypes for list.c -+*//***************************************************************************/ -+ -+#ifndef __LIST_EXT_H -+#define __LIST_EXT_H -+ -+ -+#include "std_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group etc_id Utility Library Application Programming Interface -+ -+ @Description External routines. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group list_id List -+ -+ @Description List module functions,definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description List structure. -+*//***************************************************************************/ -+typedef struct List -+{ -+ struct List *p_Next; /**< A pointer to the next list object */ -+ struct List *p_Prev; /**< A pointer to the previous list object */ -+} t_List; -+ -+ -+/**************************************************************************//** -+ @Function LIST_FIRST/LIST_LAST/LIST_NEXT/LIST_PREV -+ -+ @Description Macro to get first/last/next/previous entry in a list. -+ -+ @Param[in] p_List - A pointer to a list. -+*//***************************************************************************/ -+#define LIST_FIRST(p_List) (p_List)->p_Next -+#define LIST_LAST(p_List) (p_List)->p_Prev -+#define LIST_NEXT LIST_FIRST -+#define LIST_PREV LIST_LAST -+ -+ -+/**************************************************************************//** -+ @Function LIST_INIT -+ -+ @Description Macro for initialization of a list struct. -+ -+ @Param[in] lst - The t_List object to initialize. -+*//***************************************************************************/ -+#define LIST_INIT(lst) {&(lst), &(lst)} -+ -+ -+/**************************************************************************//** -+ @Function LIST -+ -+ @Description Macro to declare of a list. -+ -+ @Param[in] listName - The list object name. -+*//***************************************************************************/ -+#define LIST(listName) t_List listName = LIST_INIT(listName) -+ -+ -+/**************************************************************************//** -+ @Function INIT_LIST -+ -+ @Description Macro to initialize a list pointer. -+ -+ @Param[in] p_List - The list pointer. -+*//***************************************************************************/ -+#define INIT_LIST(p_List) LIST_FIRST(p_List) = LIST_LAST(p_List) = (p_List) -+ -+ -+/**************************************************************************//** -+ @Function LIST_OBJECT -+ -+ @Description Macro to get the struct (object) for this entry. -+ -+ @Param[in] type - The type of the struct (object) this list is embedded in. -+ @Param[in] member - The name of the t_List object within the struct. -+ -+ @Return The structure pointer for this entry. -+*//***************************************************************************/ -+#define MEMBER_OFFSET(type, member) (PTR_TO_UINT(&((type *)0)->member)) -+#define LIST_OBJECT(p_List, type, member) \ -+ ((type *)((char *)(p_List)-MEMBER_OFFSET(type, member))) -+ -+ -+/**************************************************************************//** -+ @Function LIST_FOR_EACH -+ -+ @Description Macro to iterate over a list. -+ -+ @Param[in] p_Pos - A pointer to a list to use as a loop counter. -+ @Param[in] p_Head - A pointer to the head for your list pointer. -+ -+ @Cautions You can't delete items with this routine. -+ For deletion use LIST_FOR_EACH_SAFE(). -+*//***************************************************************************/ -+#define LIST_FOR_EACH(p_Pos, p_Head) \ -+ for (p_Pos = LIST_FIRST(p_Head); p_Pos != (p_Head); p_Pos = LIST_NEXT(p_Pos)) -+ -+ -+/**************************************************************************//** -+ @Function LIST_FOR_EACH_SAFE -+ -+ @Description Macro to iterate over a list safe against removal of list entry. -+ -+ @Param[in] p_Pos - A pointer to a list to use as a loop counter. -+ @Param[in] p_Tmp - Another pointer to a list to use as temporary storage. -+ @Param[in] p_Head - A pointer to the head for your list pointer. -+*//***************************************************************************/ -+#define LIST_FOR_EACH_SAFE(p_Pos, p_Tmp, p_Head) \ -+ for (p_Pos = LIST_FIRST(p_Head), p_Tmp = LIST_FIRST(p_Pos); \ -+ p_Pos != (p_Head); \ -+ p_Pos = p_Tmp, p_Tmp = LIST_NEXT(p_Pos)) -+ -+ -+/**************************************************************************//** -+ @Function LIST_FOR_EACH_OBJECT_SAFE -+ -+ @Description Macro to iterate over list of given type safely. -+ -+ @Param[in] p_Pos - A pointer to a list to use as a loop counter. -+ @Param[in] p_Tmp - Another pointer to a list to use as temporary storage. -+ @Param[in] type - The type of the struct this is embedded in. -+ @Param[in] p_Head - A pointer to the head for your list pointer. -+ @Param[in] member - The name of the list_struct within the struct. -+ -+ @Cautions You can't delete items with this routine. -+ For deletion use LIST_FOR_EACH_SAFE(). -+*//***************************************************************************/ -+#define LIST_FOR_EACH_OBJECT_SAFE(p_Pos, p_Tmp, p_Head, type, member) \ -+ for (p_Pos = LIST_OBJECT(LIST_FIRST(p_Head), type, member), \ -+ p_Tmp = LIST_OBJECT(LIST_FIRST(&p_Pos->member), type, member); \ -+ &p_Pos->member != (p_Head); \ -+ p_Pos = p_Tmp, \ -+ p_Tmp = LIST_OBJECT(LIST_FIRST(&p_Pos->member), type, member)) -+ -+/**************************************************************************//** -+ @Function LIST_FOR_EACH_OBJECT -+ -+ @Description Macro to iterate over list of given type. -+ -+ @Param[in] p_Pos - A pointer to a list to use as a loop counter. -+ @Param[in] type - The type of the struct this is embedded in. -+ @Param[in] p_Head - A pointer to the head for your list pointer. -+ @Param[in] member - The name of the list_struct within the struct. -+ -+ @Cautions You can't delete items with this routine. -+ For deletion use LIST_FOR_EACH_SAFE(). -+*//***************************************************************************/ -+#define LIST_FOR_EACH_OBJECT(p_Pos, type, p_Head, member) \ -+ for (p_Pos = LIST_OBJECT(LIST_FIRST(p_Head), type, member); \ -+ &p_Pos->member != (p_Head); \ -+ p_Pos = LIST_OBJECT(LIST_FIRST(&(p_Pos->member)), type, member)) -+ -+ -+/**************************************************************************//** -+ @Function LIST_Add -+ -+ @Description Add a new entry to a list. -+ -+ Insert a new entry after the specified head. -+ This is good for implementing stacks. -+ -+ @Param[in] p_New - A pointer to a new list entry to be added. -+ @Param[in] p_Head - A pointer to a list head to add it after. -+ -+ @Return none. -+*//***************************************************************************/ -+static __inline__ void LIST_Add(t_List *p_New, t_List *p_Head) -+{ -+ LIST_PREV(LIST_NEXT(p_Head)) = p_New; -+ LIST_NEXT(p_New) = LIST_NEXT(p_Head); -+ LIST_PREV(p_New) = p_Head; -+ LIST_NEXT(p_Head) = p_New; -+} -+ -+ -+/**************************************************************************//** -+ @Function LIST_AddToTail -+ -+ @Description Add a new entry to a list. -+ -+ Insert a new entry before the specified head. -+ This is useful for implementing queues. -+ -+ @Param[in] p_New - A pointer to a new list entry to be added. -+ @Param[in] p_Head - A pointer to a list head to add it before. -+ -+ @Return none. -+*//***************************************************************************/ -+static __inline__ void LIST_AddToTail(t_List *p_New, t_List *p_Head) -+{ -+ LIST_NEXT(LIST_PREV(p_Head)) = p_New; -+ LIST_PREV(p_New) = LIST_PREV(p_Head); -+ LIST_NEXT(p_New) = p_Head; -+ LIST_PREV(p_Head) = p_New; -+} -+ -+ -+/**************************************************************************//** -+ @Function LIST_Del -+ -+ @Description Deletes entry from a list. -+ -+ @Param[in] p_Entry - A pointer to the element to delete from the list. -+ -+ @Return none. -+ -+ @Cautions LIST_IsEmpty() on entry does not return true after this, -+ the entry is in an undefined state. -+*//***************************************************************************/ -+static __inline__ void LIST_Del(t_List *p_Entry) -+{ -+ LIST_PREV(LIST_NEXT(p_Entry)) = LIST_PREV(p_Entry); -+ LIST_NEXT(LIST_PREV(p_Entry)) = LIST_NEXT(p_Entry); -+} -+ -+ -+/**************************************************************************//** -+ @Function LIST_DelAndInit -+ -+ @Description Deletes entry from list and reinitialize it. -+ -+ @Param[in] p_Entry - A pointer to the element to delete from the list. -+ -+ @Return none. -+*//***************************************************************************/ -+static __inline__ void LIST_DelAndInit(t_List *p_Entry) -+{ -+ LIST_Del(p_Entry); -+ INIT_LIST(p_Entry); -+} -+ -+ -+/**************************************************************************//** -+ @Function LIST_Move -+ -+ @Description Delete from one list and add as another's head. -+ -+ @Param[in] p_Entry - A pointer to the list entry to move. -+ @Param[in] p_Head - A pointer to the list head that will precede our entry. -+ -+ @Return none. -+*//***************************************************************************/ -+static __inline__ void LIST_Move(t_List *p_Entry, t_List *p_Head) -+{ -+ LIST_Del(p_Entry); -+ LIST_Add(p_Entry, p_Head); -+} -+ -+ -+/**************************************************************************//** -+ @Function LIST_MoveToTail -+ -+ @Description Delete from one list and add as another's tail. -+ -+ @Param[in] p_Entry - A pointer to the entry to move. -+ @Param[in] p_Head - A pointer to the list head that will follow our entry. -+ -+ @Return none. -+*//***************************************************************************/ -+static __inline__ void LIST_MoveToTail(t_List *p_Entry, t_List *p_Head) -+{ -+ LIST_Del(p_Entry); -+ LIST_AddToTail(p_Entry, p_Head); -+} -+ -+ -+/**************************************************************************//** -+ @Function LIST_IsEmpty -+ -+ @Description Tests whether a list is empty. -+ -+ @Param[in] p_List - A pointer to the list to test. -+ -+ @Return 1 if the list is empty, 0 otherwise. -+*//***************************************************************************/ -+static __inline__ int LIST_IsEmpty(t_List *p_List) -+{ -+ return (LIST_FIRST(p_List) == p_List); -+} -+ -+ -+/**************************************************************************//** -+ @Function LIST_Append -+ -+ @Description Join two lists. -+ -+ @Param[in] p_NewList - A pointer to the new list to add. -+ @Param[in] p_Head - A pointer to the place to add it in the first list. -+ -+ @Return none. -+*//***************************************************************************/ -+void LIST_Append(t_List *p_NewList, t_List *p_Head); -+ -+ -+/**************************************************************************//** -+ @Function LIST_NumOfObjs -+ -+ @Description Counts number of objects in the list -+ -+ @Param[in] p_List - A pointer to the list which objects are to be counted. -+ -+ @Return Number of objects in the list. -+*//***************************************************************************/ -+int LIST_NumOfObjs(t_List *p_List); -+ -+/** @} */ /* end of list_id group */ -+/** @} */ /* end of etc_id group */ -+ -+ -+#endif /* __LIST_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/etc/mem_ext.h -@@ -0,0 +1,318 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ -+ @File mem_ext.h -+ -+ @Description External prototypes for the memory manager object -+*//***************************************************************************/ -+ -+#ifndef __MEM_EXT_H -+#define __MEM_EXT_H -+ -+#include "std_ext.h" -+#include "part_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group etc_id Utility Library Application Programming Interface -+ -+ @Description External routines. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group mem_id Slab Memory Manager -+ -+ @Description Slab Memory Manager module functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/* Each block is of the following structure: -+ * -+ * -+ * +-----------+----------+---------------------------+-----------+-----------+ -+ * | Alignment | Prefix | Data | Postfix | Alignment | -+ * | field | field | field | field | Padding | -+ * | | | | | | -+ * +-----------+----------+---------------------------+-----------+-----------+ -+ * and at the beginning of all bytes, an additional optional padding might reside -+ * to ensure that the first blocks data field is aligned as requested. -+ */ -+ -+ -+#define MEM_MAX_NAME_LENGTH 8 -+ -+/**************************************************************************//* -+ @Description Memory Segment structure -+*//***************************************************************************/ -+ -+typedef struct -+{ -+ char name[MEM_MAX_NAME_LENGTH]; -+ /* The segment's name */ -+ uint8_t **p_Bases; /* Base addresses of the segments */ -+ uint8_t **p_BlocksStack; /* Array of pointers to blocks */ -+ t_Handle h_Spinlock; -+ uint16_t dataSize; /* Size of each data block */ -+ uint16_t prefixSize; /* How many bytes to reserve before the data */ -+ uint16_t postfixSize; /* How many bytes to reserve after the data */ -+ uint16_t alignment; /* Requested alignment for the data field */ -+ int allocOwner; /* Memory allocation owner */ -+ uint32_t getFailures; /* Number of times get failed */ -+ uint32_t num; /* Number of blocks in segment */ -+ uint32_t current; /* Current block */ -+ bool consecutiveMem; /* Allocate consecutive data blocks memory */ -+#ifdef DEBUG_MEM_LEAKS -+ void *p_MemDbg; /* MEM debug database (MEM leaks detection) */ -+ uint32_t blockOffset; -+ uint32_t blockSize; -+#endif /* DEBUG_MEM_LEAKS */ -+} t_MemorySegment; -+ -+ -+ -+/**************************************************************************//** -+ @Function MEM_Init -+ -+ @Description Create a new memory segment. -+ -+ @Param[in] name - Name of memory partition. -+ @Param[in] p_Handle - Handle to new segment is returned through here. -+ @Param[in] num - Number of blocks in new segment. -+ @Param[in] dataSize - Size of blocks in segment. -+ @Param[in] prefixSize - How many bytes to allocate before the data. -+ @Param[in] postfixSize - How many bytes to allocate after the data. -+ @Param[in] alignment - Requested alignment for data field (in bytes). -+ -+ @Return E_OK - success, E_NO_MEMORY - out of memory. -+*//***************************************************************************/ -+t_Error MEM_Init(char name[], -+ t_Handle *p_Handle, -+ uint32_t num, -+ uint16_t dataSize, -+ uint16_t prefixSize, -+ uint16_t postfixSize, -+ uint16_t alignment); -+ -+/**************************************************************************//** -+ @Function MEM_InitSmart -+ -+ @Description Create a new memory segment. -+ -+ @Param[in] name - Name of memory partition. -+ @Param[in] p_Handle - Handle to new segment is returned through here. -+ @Param[in] num - Number of blocks in new segment. -+ @Param[in] dataSize - Size of blocks in segment. -+ @Param[in] prefixSize - How many bytes to allocate before the data. -+ @Param[in] postfixSize - How many bytes to allocate after the data. -+ @Param[in] alignment - Requested alignment for data field (in bytes). -+ @Param[in] memPartitionId - Memory partition ID for allocation. -+ @Param[in] consecutiveMem - Whether to allocate the memory blocks -+ continuously or not. -+ -+ @Return E_OK - success, E_NO_MEMORY - out of memory. -+*//***************************************************************************/ -+t_Error MEM_InitSmart(char name[], -+ t_Handle *p_Handle, -+ uint32_t num, -+ uint16_t dataSize, -+ uint16_t prefixSize, -+ uint16_t postfixSize, -+ uint16_t alignment, -+ uint8_t memPartitionId, -+ bool consecutiveMem); -+ -+/**************************************************************************//** -+ @Function MEM_InitByAddress -+ -+ @Description Create a new memory segment with a specified base address. -+ -+ @Param[in] name - Name of memory partition. -+ @Param[in] p_Handle - Handle to new segment is returned through here. -+ @Param[in] num - Number of blocks in new segment. -+ @Param[in] dataSize - Size of blocks in segment. -+ @Param[in] prefixSize - How many bytes to allocate before the data. -+ @Param[in] postfixSize - How many bytes to allocate after the data. -+ @Param[in] alignment - Requested alignment for data field (in bytes). -+ @Param[in] address - The required base address. -+ -+ @Return E_OK - success, E_NO_MEMORY - out of memory. -+ *//***************************************************************************/ -+t_Error MEM_InitByAddress(char name[], -+ t_Handle *p_Handle, -+ uint32_t num, -+ uint16_t dataSize, -+ uint16_t prefixSize, -+ uint16_t postfixSize, -+ uint16_t alignment, -+ uint8_t *address); -+ -+/**************************************************************************//** -+ @Function MEM_Free -+ -+ @Description Free a specific memory segment. -+ -+ @Param[in] h_Mem - Handle to memory segment. -+ -+ @Return None. -+*//***************************************************************************/ -+void MEM_Free(t_Handle h_Mem); -+ -+/**************************************************************************//** -+ @Function MEM_Get -+ -+ @Description Get a block of memory from a segment. -+ -+ @Param[in] h_Mem - Handle to memory segment. -+ -+ @Return Pointer to new memory block on success,0 otherwise. -+*//***************************************************************************/ -+void * MEM_Get(t_Handle h_Mem); -+ -+/**************************************************************************//** -+ @Function MEM_GetN -+ -+ @Description Get up to N blocks of memory from a segment. -+ -+ The blocks are assumed to be of a fixed size (one size per segment). -+ -+ @Param[in] h_Mem - Handle to memory segment. -+ @Param[in] num - Number of blocks to allocate. -+ @Param[out] array - Array of at least num pointers to which the addresses -+ of the allocated blocks are written. -+ -+ @Return The number of blocks actually allocated. -+ -+ @Cautions Interrupts are disabled for all of the allocation loop. -+ Although this loop is very short for each block (several machine -+ instructions), you should not allocate a very large number -+ of blocks via this routine. -+*//***************************************************************************/ -+uint16_t MEM_GetN(t_Handle h_Mem, uint32_t num, void *array[]); -+ -+/**************************************************************************//** -+ @Function MEM_Put -+ -+ @Description Put a block of memory back to a segment. -+ -+ @Param[in] h_Mem - Handle to memory segment. -+ @Param[in] p_Block - The block to return. -+ -+ @Return Pointer to new memory block on success,0 otherwise. -+*//***************************************************************************/ -+t_Error MEM_Put(t_Handle h_Mem, void *p_Block); -+ -+/**************************************************************************//** -+ @Function MEM_ComputePartitionSize -+ -+ @Description calculate a tight upper boundary of the size of a partition with -+ given attributes. -+ -+ The returned value is suitable if one wants to use MEM_InitByAddress(). -+ -+ @Param[in] num - The number of blocks in the segment. -+ @Param[in] dataSize - Size of block to get. -+ @Param[in] prefixSize - The prefix size -+ @Param postfixSize - The postfix size -+ @Param[in] alignment - The requested alignment value (in bytes) -+ -+ @Return The memory block size a segment with the given attributes needs. -+*//***************************************************************************/ -+uint32_t MEM_ComputePartitionSize(uint32_t num, -+ uint16_t dataSize, -+ uint16_t prefixSize, -+ uint16_t postfixSize, -+ uint16_t alignment); -+ -+#ifdef DEBUG_MEM_LEAKS -+#if !((defined(__MWERKS__) || defined(__GNUC__)) && (__dest_os == __ppc_eabi)) -+#error "Memory-Leaks-Debug option is supported only for freescale CodeWarrior" -+#endif /* !(defined(__MWERKS__) && ... */ -+ -+/**************************************************************************//** -+ @Function MEM_CheckLeaks -+ -+ @Description Report MEM object leaks. -+ -+ This routine is automatically called by the MEM_Free() routine, -+ but it can also be invoked while the MEM object is alive. -+ -+ @Param[in] h_Mem - Handle to memory segment. -+ -+ @Return None. -+*//***************************************************************************/ -+void MEM_CheckLeaks(t_Handle h_Mem); -+ -+#else /* not DEBUG_MEM_LEAKS */ -+#define MEM_CheckLeaks(h_Mem) -+#endif /* not DEBUG_MEM_LEAKS */ -+ -+/**************************************************************************//** -+ @Description Get base of MEM -+*//***************************************************************************/ -+#define MEM_GetBase(h_Mem) ((t_MemorySegment *)(h_Mem))->p_Bases[0] -+ -+/**************************************************************************//** -+ @Description Get size of MEM block -+*//***************************************************************************/ -+#define MEM_GetSize(h_Mem) ((t_MemorySegment *)(h_Mem))->dataSize -+ -+/**************************************************************************//** -+ @Description Get prefix size of MEM block -+*//***************************************************************************/ -+#define MEM_GetPrefixSize(h_Mem) ((t_MemorySegment *)(h_Mem))->prefixSize -+ -+/**************************************************************************//** -+ @Description Get postfix size of MEM block -+*//***************************************************************************/ -+#define MEM_GetPostfixSize(h_Mem) ((t_MemorySegment *)(h_Mem))->postfixSize -+ -+/**************************************************************************//** -+ @Description Get alignment of MEM block (in bytes) -+*//***************************************************************************/ -+#define MEM_GetAlignment(h_Mem) ((t_MemorySegment *)(h_Mem))->alignment -+ -+/**************************************************************************//** -+ @Description Get the number of blocks in the segment -+*//***************************************************************************/ -+#define MEM_GetNumOfBlocks(h_Mem) ((t_MemorySegment *)(h_Mem))->num -+ -+/** @} */ /* end of MEM group */ -+/** @} */ /* end of etc_id group */ -+ -+ -+#endif /* __MEM_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/etc/memcpy_ext.h -@@ -0,0 +1,208 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ -+ @File memcpy_ext.h -+ -+ @Description Efficient functions for copying and setting blocks of memory. -+*//***************************************************************************/ -+ -+#ifndef __MEMCPY_EXT_H -+#define __MEMCPY_EXT_H -+ -+#include "std_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group etc_id Utility Library Application Programming Interface -+ -+ @Description External routines. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group mem_cpy Memory Copy -+ -+ @Description Memory Copy module functions,definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function MemCpy32 -+ -+ @Description Copies one memory buffer into another one in 4-byte chunks! -+ Which should be more efficient than byte by byte. -+ -+ For large buffers (over 60 bytes) this function is about 4 times -+ more efficient than the trivial memory copy. For short buffers -+ it is reduced to the trivial copy and may be a bit worse. -+ -+ @Param[in] pDst - The address of the destination buffer. -+ @Param[in] pSrc - The address of the source buffer. -+ @Param[in] size - The number of bytes that will be copied from pSrc to pDst. -+ -+ @Return pDst (the address of the destination buffer). -+ -+ @Cautions There is no parameter or boundary checking! It is up to the user -+ to supply non-null parameters as source & destination and size -+ that actually fits into the destination buffer. -+*//***************************************************************************/ -+void * MemCpy32(void* pDst,void* pSrc, uint32_t size); -+void * IO2IOCpy32(void* pDst,void* pSrc, uint32_t size); -+void * IO2MemCpy32(void* pDst,void* pSrc, uint32_t size); -+void * Mem2IOCpy32(void* pDst,void* pSrc, uint32_t size); -+ -+/**************************************************************************//** -+ @Function MemCpy64 -+ -+ @Description Copies one memory buffer into another one in 8-byte chunks! -+ Which should be more efficient than byte by byte. -+ -+ For large buffers (over 60 bytes) this function is about 8 times -+ more efficient than the trivial memory copy. For short buffers -+ it is reduced to the trivial copy and may be a bit worse. -+ -+ Some testing suggests that MemCpy32() preforms better than -+ MemCpy64() over small buffers. On average they break even at -+ 100 byte buffers. For buffers larger than that MemCpy64 is -+ superior. -+ -+ @Param[in] pDst - The address of the destination buffer. -+ @Param[in] pSrc - The address of the source buffer. -+ @Param[in] size - The number of bytes that will be copied from pSrc to pDst. -+ -+ @Return pDst (the address of the destination buffer). -+ -+ @Cautions There is no parameter or boundary checking! It is up to the user -+ to supply non null parameters as source & destination and size -+ that actually fits into their buffer. -+ -+ Do not use under Linux. -+*//***************************************************************************/ -+void * MemCpy64(void* pDst,void* pSrc, uint32_t size); -+ -+/**************************************************************************//** -+ @Function MemSet32 -+ -+ @Description Sets all bytes of a memory buffer to a specific value, in -+ 4-byte chunks. -+ -+ @Param[in] pDst - The address of the destination buffer. -+ @Param[in] val - Value to set destination bytes to. -+ @Param[in] size - The number of bytes that will be set to val. -+ -+ @Return pDst (the address of the destination buffer). -+ -+ @Cautions There is no parameter or boundary checking! It is up to the user -+ to supply non null parameter as destination and size -+ that actually fits into the destination buffer. -+*//***************************************************************************/ -+void * MemSet32(void* pDst, uint8_t val, uint32_t size); -+void * IOMemSet32(void* pDst, uint8_t val, uint32_t size); -+ -+/**************************************************************************//** -+ @Function MemSet64 -+ -+ @Description Sets all bytes of a memory buffer to a specific value, in -+ 8-byte chunks. -+ -+ @Param[in] pDst - The address of the destination buffer. -+ @Param[in] val - Value to set destination bytes to. -+ @Param[in] size - The number of bytes that will be set to val. -+ -+ @Return pDst (the address of the destination buffer). -+ -+ @Cautions There is no parameter or boundary checking! It is up to the user -+ to supply non null parameter as destination and size -+ that actually fits into the destination buffer. -+*//***************************************************************************/ -+void * MemSet64(void* pDst, uint8_t val, uint32_t size); -+ -+/**************************************************************************//** -+ @Function MemDisp -+ -+ @Description Displays a block of memory in chunks of 32 bits. -+ -+ @Param[in] addr - The address of the memory to display. -+ @Param[in] size - The number of bytes that will be displayed. -+ -+ @Return None. -+ -+ @Cautions There is no parameter or boundary checking! It is up to the user -+ to supply non null parameter as destination and size -+ that actually fits into the destination buffer. -+*//***************************************************************************/ -+void MemDisp(uint8_t *addr, int size); -+ -+/**************************************************************************//** -+ @Function MemCpy8 -+ -+ @Description Trivial copy one memory buffer into another byte by byte -+ -+ @Param[in] pDst - The address of the destination buffer. -+ @Param[in] pSrc - The address of the source buffer. -+ @Param[in] size - The number of bytes that will be copied from pSrc to pDst. -+ -+ @Return pDst (the address of the destination buffer). -+ -+ @Cautions There is no parameter or boundary checking! It is up to the user -+ to supply non-null parameters as source & destination and size -+ that actually fits into the destination buffer. -+*//***************************************************************************/ -+void * MemCpy8(void* pDst,void* pSrc, uint32_t size); -+ -+/**************************************************************************//** -+ @Function MemSet8 -+ -+ @Description Sets all bytes of a memory buffer to a specific value byte by byte. -+ -+ @Param[in] pDst - The address of the destination buffer. -+ @Param[in] c - Value to set destination bytes to. -+ @Param[in] size - The number of bytes that will be set to val. -+ -+ @Return pDst (the address of the destination buffer). -+ -+ @Cautions There is no parameter or boundary checking! It is up to the user -+ to supply non null parameter as destination and size -+ that actually fits into the destination buffer. -+*//***************************************************************************/ -+void * MemSet8(void* pDst, int c, uint32_t size); -+ -+/** @} */ /* end of mem_cpy group */ -+/** @} */ /* end of etc_id group */ -+ -+ -+#endif /* __MEMCPY_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/etc/mm_ext.h -@@ -0,0 +1,310 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File mm_ext.h -+ -+ @Description Memory Manager Application Programming Interface -+*//***************************************************************************/ -+#ifndef __MM_EXT -+#define __MM_EXT -+ -+#include "std_ext.h" -+ -+#define MM_MAX_ALIGNMENT 20 /* Alignments from 2 to 128 are available -+ where maximum alignment defined as -+ MM_MAX_ALIGNMENT power of 2 */ -+ -+#define MM_MAX_NAME_LEN 32 -+ -+/**************************************************************************//** -+ @Group etc_id Utility Library Application Programming Interface -+ -+ @Description External routines. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group mm_grp Flexible Memory Manager -+ -+ @Description Flexible Memory Manager module functions,definitions and enums. -+ (All of the following functions,definitions and enums can be found in mm_ext.h) -+ -+ @{ -+*//***************************************************************************/ -+ -+ -+/**************************************************************************//** -+ @Function MM_Init -+ -+ @Description Initializes a new MM object. -+ -+ It initializes a new memory block consisting of base address -+ and size of the available memory by calling to MemBlock_Init -+ routine. It is also initializes a new free block for each -+ by calling FreeBlock_Init routine, which is pointed to -+ the almost all memory started from the required alignment -+ from the base address and to the end of the memory. -+ The handle to the new MM object is returned via "MM" -+ argument (passed by reference). -+ -+ @Param[in] h_MM - Handle to the MM object. -+ @Param[in] base - Base address of the MM. -+ @Param[in] size - Size of the MM. -+ -+ @Return E_OK is returned on success. E_NOMEMORY is returned if the new MM object or a new free block can not be initialized. -+*//***************************************************************************/ -+t_Error MM_Init(t_Handle *h_MM, uint64_t base, uint64_t size); -+ -+/**************************************************************************//** -+ @Function MM_Get -+ -+ @Description Allocates a block of memory according to the given size and the alignment. -+ -+ The Alignment argument tells from which -+ free list allocate a block of memory. 2^alignment indicates -+ the alignment that the base address of the allocated block -+ should have. So, the only values 1, 2, 4, 8, 16, 32 and 64 -+ are available for the alignment argument. -+ The routine passes through the specific free list of free -+ blocks and seeks for a first block that have anough memory -+ that is required (best fit). -+ After the block is found and data is allocated, it calls -+ the internal MM_CutFree routine to update all free lists -+ do not include a just allocated block. Of course, each -+ free list contains a free blocks with the same alignment. -+ It is also creates a busy block that holds -+ information about an allocated block. -+ -+ @Param[in] h_MM - Handle to the MM object. -+ @Param[in] size - Size of the MM. -+ @Param[in] alignment - Index as a power of two defines a required -+ alignment (in bytes); Should be 1, 2, 4, 8, 16, 32 or 64 -+ @Param[in] name - The name that specifies an allocated block. -+ -+ @Return base address of an allocated block ILLEGAL_BASE if can't allocate a block -+*//***************************************************************************/ -+uint64_t MM_Get(t_Handle h_MM, uint64_t size, uint64_t alignment, char *name); -+ -+/**************************************************************************//** -+ @Function MM_GetBase -+ -+ @Description Gets the base address of the required MM objects. -+ -+ @Param[in] h_MM - Handle to the MM object. -+ -+ @Return base address of the block. -+*//***************************************************************************/ -+uint64_t MM_GetBase(t_Handle h_MM); -+ -+/**************************************************************************//** -+ @Function MM_GetForce -+ -+ @Description Force memory allocation. -+ -+ It means to allocate a block of memory of the given -+ size from the given base address. -+ The routine checks if the required block can be allocated -+ (that is it is free) and then, calls the internal MM_CutFree -+ routine to update all free lists do not include that block. -+ -+ @Param[in] h_MM - Handle to the MM object. -+ @Param[in] base - Base address of the MM. -+ @Param[in] size - Size of the MM. -+ @Param[in] name - Name that specifies an allocated block. -+ -+ @Return base address of an allocated block, ILLEGAL_BASE if can't allocate a block. -+*//***************************************************************************/ -+uint64_t MM_GetForce(t_Handle h_MM, uint64_t base, uint64_t size, char *name); -+ -+/**************************************************************************//** -+ @Function MM_GetForceMin -+ -+ @Description Allocates a block of memory according to the given size, the alignment and minimum base address. -+ -+ The Alignment argument tells from which -+ free list allocate a block of memory. 2^alignment indicates -+ the alignment that the base address of the allocated block -+ should have. So, the only values 1, 2, 4, 8, 16, 32 and 64 -+ are available for the alignment argument. -+ The minimum baser address forces the location of the block -+ to be from a given address onward. -+ The routine passes through the specific free list of free -+ blocks and seeks for the first base address equal or smaller -+ than the required minimum address and end address larger than -+ than the required base + its size - i.e. that may contain -+ the required block. -+ After the block is found and data is allocated, it calls -+ the internal MM_CutFree routine to update all free lists -+ do not include a just allocated block. Of course, each -+ free list contains a free blocks with the same alignment. -+ It is also creates a busy block that holds -+ information about an allocated block. -+ -+ @Param[in] h_MM - Handle to the MM object. -+ @Param[in] size - Size of the MM. -+ @Param[in] alignment - Index as a power of two defines a required -+ alignment (in bytes); Should be 1, 2, 4, 8, 16, 32 or 64 -+ @Param[in] min - The minimum base address of the block. -+ @Param[in] name - Name that specifies an allocated block. -+ -+ @Return base address of an allocated block,ILLEGAL_BASE if can't allocate a block. -+*//***************************************************************************/ -+uint64_t MM_GetForceMin(t_Handle h_MM, -+ uint64_t size, -+ uint64_t alignment, -+ uint64_t min, -+ char *name); -+ -+/**************************************************************************//** -+ @Function MM_Put -+ -+ @Description Puts a block of memory of the given base address back to the memory. -+ -+ It checks if there is a busy block with the -+ given base address. If not, it returns 0, that -+ means can't free a block. Otherwise, it gets parameters of -+ the busy block and after it updates lists of free blocks, -+ removes that busy block from the list by calling to MM_CutBusy -+ routine. -+ After that it calls to MM_AddFree routine to add a new free -+ block to the free lists. -+ -+ @Param[in] h_MM - Handle to the MM object. -+ @Param[in] base - Base address of the MM. -+ -+ @Return The size of bytes released, 0 if failed. -+*//***************************************************************************/ -+uint64_t MM_Put(t_Handle h_MM, uint64_t base); -+ -+/**************************************************************************//** -+ @Function MM_PutForce -+ -+ @Description Releases a block of memory of the required size from the required base address. -+ -+ First, it calls to MM_CutBusy routine -+ to cut a free block from the busy list. And then, calls to -+ MM_AddFree routine to add the free block to the free lists. -+ -+ @Param[in] h_MM - Handle to the MM object. -+ @Param[in] base - Base address of of a block to free. -+ @Param[in] size - Size of a block to free. -+ -+ @Return The number of bytes released, 0 on failure. -+*//***************************************************************************/ -+uint64_t MM_PutForce(t_Handle h_MM, uint64_t base, uint64_t size); -+ -+/**************************************************************************//** -+ @Function MM_Add -+ -+ @Description Adds a new memory block for memory allocation. -+ -+ When a new memory block is initialized and added to the -+ memory list, it calls to MM_AddFree routine to add the -+ new free block to the free lists. -+ -+ @Param[in] h_MM - Handle to the MM object. -+ @Param[in] base - Base address of the memory block. -+ @Param[in] size - Size of the memory block. -+ -+ @Return E_OK on success, otherwise returns an error code. -+*//***************************************************************************/ -+t_Error MM_Add(t_Handle h_MM, uint64_t base, uint64_t size); -+ -+/**************************************************************************//** -+ @Function MM_Dump -+ -+ @Description Prints results of free and busy lists. -+ -+ @Param[in] h_MM - Handle to the MM object. -+*//***************************************************************************/ -+void MM_Dump(t_Handle h_MM); -+ -+/**************************************************************************//** -+ @Function MM_Free -+ -+ @Description Releases memory allocated for MM object. -+ -+ @Param[in] h_MM - Handle of the MM object. -+*//***************************************************************************/ -+void MM_Free(t_Handle h_MM); -+ -+/**************************************************************************//** -+ @Function MM_GetMemBlock -+ -+ @Description Returns base address of the memory block specified by the index. -+ -+ If index is 0, returns base address -+ of the first memory block, 1 - returns base address -+ of the second memory block, etc. -+ Note, those memory blocks are allocated by the -+ application before MM_Init or MM_Add and have to -+ be released by the application before or after invoking -+ the MM_Free routine. -+ -+ @Param[in] h_MM - Handle to the MM object. -+ @Param[in] index - Index of the memory block. -+ -+ @Return valid base address or ILLEGAL_BASE if no memory block specified by the index. -+*//***************************************************************************/ -+uint64_t MM_GetMemBlock(t_Handle h_MM, int index); -+ -+/**************************************************************************//** -+ @Function MM_InRange -+ -+ @Description Checks if a specific address is in the memory range of the passed MM object. -+ -+ @Param[in] h_MM - Handle to the MM object. -+ @Param[in] addr - The address to be checked. -+ -+ @Return TRUE if the address is in the address range of the block, FALSE otherwise. -+*//***************************************************************************/ -+bool MM_InRange(t_Handle h_MM, uint64_t addr); -+ -+/**************************************************************************//** -+ @Function MM_GetFreeMemSize -+ -+ @Description Returns the size (in bytes) of free memory. -+ -+ @Param[in] h_MM - Handle to the MM object. -+ -+ @Return Free memory size in bytes. -+*//***************************************************************************/ -+uint64_t MM_GetFreeMemSize(t_Handle h_MM); -+ -+ -+/** @} */ /* end of mm_grp group */ -+/** @} */ /* end of etc_id group */ -+ -+#endif /* __MM_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/etc/sprint_ext.h -@@ -0,0 +1,118 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File sprint_ext.h -+ -+ @Description Debug routines (externals). -+ -+*//***************************************************************************/ -+ -+#ifndef __SPRINT_EXT_H -+#define __SPRINT_EXT_H -+ -+ -+#if defined(NCSW_LINUX) && defined(__KERNEL__) -+#include -+ -+#elif defined(NCSW_VXWORKS) -+#include "private/stdioP.h" -+ -+#else -+#include -+#endif /* defined(NCSW_LINUX) && defined(__KERNEL__) */ -+ -+#include "std_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group etc_id Utility Library Application Programming Interface -+ -+ @Description External routines. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group sprint_id Sprint -+ -+ @Description Sprint & Sscan module functions,definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Function Sprint -+ -+ @Description Format a string and place it in a buffer. -+ -+ @Param[in] buff - The buffer to place the result into. -+ @Param[in] str - The format string to use. -+ @Param[in] ... - Arguments for the format string. -+ -+ @Return Number of bytes formatted. -+*//***************************************************************************/ -+int Sprint(char *buff, const char *str, ...); -+ -+/**************************************************************************//** -+ @Function Snprint -+ -+ @Description Format a string and place it in a buffer. -+ -+ @Param[in] buf - The buffer to place the result into. -+ @Param[in] size - The size of the buffer, including the trailing null space. -+ @Param[in] fmt - The format string to use. -+ @Param[in] ... - Arguments for the format string. -+ -+ @Return Number of bytes formatted. -+*//***************************************************************************/ -+int Snprint(char * buf, uint32_t size, const char *fmt, ...); -+ -+/**************************************************************************//** -+ @Function Sscan -+ -+ @Description Unformat a buffer into a list of arguments. -+ -+ @Param[in] buf - input buffer. -+ @Param[in] fmt - formatting of buffer. -+ @Param[out] ... - resulting arguments. -+ -+ @Return Number of bytes unformatted. -+*//***************************************************************************/ -+int Sscan(const char * buf, const char * fmt, ...); -+ -+/** @} */ /* end of sprint_id group */ -+/** @} */ /* end of etc_id group */ -+ -+ -+#endif /* __SPRINT_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/common/arch/ppc_access.h -@@ -0,0 +1,37 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef FL_E500_MACROS_H -+#define FL_E500_MACROS_H -+ -+#endif /* FL_E500_MACROS_H */ -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/common/general.h -@@ -0,0 +1,52 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __GENERAL_H -+#define __GENERAL_H -+ -+#include "std_ext.h" -+#if !defined(NCSW_LINUX) -+#include "errno.h" -+#endif -+ -+ -+extern uint32_t get_mac_addr_crc(uint64_t _addr); -+ -+#ifndef CONFIG_FMAN_ARM -+#define iowrite32be(val, addr) WRITE_UINT32(*addr, val) -+#define ioread32be(addr) GET_UINT32(*addr) -+#endif -+ -+#define ether_crc(len, addr) get_mac_addr_crc(*(uint64_t *)(addr)>>16) -+ -+ -+#endif /* __GENERAL_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/fman_common.h -@@ -0,0 +1,78 @@ -+/* -+ * Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#ifndef __FMAN_COMMON_H -+#define __FMAN_COMMON_H -+ -+/**************************************************************************//** -+ @Description NIA Description -+*//***************************************************************************/ -+#define NIA_ORDER_RESTOR 0x00800000 -+#define NIA_ENG_FM_CTL 0x00000000 -+#define NIA_ENG_PRS 0x00440000 -+#define NIA_ENG_KG 0x00480000 -+#define NIA_ENG_PLCR 0x004C0000 -+#define NIA_ENG_BMI 0x00500000 -+#define NIA_ENG_QMI_ENQ 0x00540000 -+#define NIA_ENG_QMI_DEQ 0x00580000 -+#define NIA_ENG_MASK 0x007C0000 -+ -+#define NIA_FM_CTL_AC_CC 0x00000006 -+#define NIA_FM_CTL_AC_HC 0x0000000C -+#define NIA_FM_CTL_AC_IND_MODE_TX 0x00000008 -+#define NIA_FM_CTL_AC_IND_MODE_RX 0x0000000A -+#define NIA_FM_CTL_AC_FRAG 0x0000000e -+#define NIA_FM_CTL_AC_PRE_FETCH 0x00000010 -+#define NIA_FM_CTL_AC_POST_FETCH_PCD 0x00000012 -+#define NIA_FM_CTL_AC_POST_FETCH_PCD_UDP_LEN 0x00000018 -+#define NIA_FM_CTL_AC_POST_FETCH_NO_PCD 0x00000012 -+#define NIA_FM_CTL_AC_FRAG_CHECK 0x00000014 -+#define NIA_FM_CTL_AC_PRE_CC 0x00000020 -+ -+ -+#define NIA_BMI_AC_ENQ_FRAME 0x00000002 -+#define NIA_BMI_AC_TX_RELEASE 0x000002C0 -+#define NIA_BMI_AC_RELEASE 0x000000C0 -+#define NIA_BMI_AC_DISCARD 0x000000C1 -+#define NIA_BMI_AC_TX 0x00000274 -+#define NIA_BMI_AC_FETCH 0x00000208 -+#define NIA_BMI_AC_MASK 0x000003FF -+ -+#define NIA_KG_DIRECT 0x00000100 -+#define NIA_KG_CC_EN 0x00000200 -+#define NIA_PLCR_ABSOLUTE 0x00008000 -+ -+#define NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA 0x00000202 -+#define NIA_BMI_AC_FETCH_ALL_FRAME 0x0000020c -+ -+#endif /* __FMAN_COMMON_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_enet.h -@@ -0,0 +1,273 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __FSL_ENET_H -+#define __FSL_ENET_H -+ -+/** -+ @Description Ethernet MAC-PHY Interface -+*/ -+ -+enum enet_interface { -+ E_ENET_IF_MII = 0x00010000, /**< MII interface */ -+ E_ENET_IF_RMII = 0x00020000, /**< RMII interface */ -+ E_ENET_IF_SMII = 0x00030000, /**< SMII interface */ -+ E_ENET_IF_GMII = 0x00040000, /**< GMII interface */ -+ E_ENET_IF_RGMII = 0x00050000, /**< RGMII interface */ -+ E_ENET_IF_TBI = 0x00060000, /**< TBI interface */ -+ E_ENET_IF_RTBI = 0x00070000, /**< RTBI interface */ -+ E_ENET_IF_SGMII = 0x00080000, /**< SGMII interface */ -+ E_ENET_IF_XGMII = 0x00090000, /**< XGMII interface */ -+ E_ENET_IF_QSGMII = 0x000a0000, /**< QSGMII interface */ -+ E_ENET_IF_XFI = 0x000b0000 /**< XFI interface */ -+}; -+ -+/** -+ @Description Ethernet Speed (nominal data rate) -+*/ -+enum enet_speed { -+ E_ENET_SPEED_10 = 10, /**< 10 Mbps */ -+ E_ENET_SPEED_100 = 100, /**< 100 Mbps */ -+ E_ENET_SPEED_1000 = 1000, /**< 1000 Mbps = 1 Gbps */ -+ E_ENET_SPEED_2500 = 2500, /**< 2500 Mbps = 2.5 Gbps */ -+ E_ENET_SPEED_10000 = 10000 /**< 10000 Mbps = 10 Gbps */ -+}; -+ -+enum mac_type { -+ E_MAC_DTSEC, -+ E_MAC_TGEC, -+ E_MAC_MEMAC -+}; -+ -+/**************************************************************************//** -+ @Description Enum for inter-module interrupts registration -+*//***************************************************************************/ -+enum fman_event_modules { -+ E_FMAN_MOD_PRS, /**< Parser event */ -+ E_FMAN_MOD_KG, /**< Keygen event */ -+ E_FMAN_MOD_PLCR, /**< Policer event */ -+ E_FMAN_MOD_10G_MAC, /**< 10G MAC event */ -+ E_FMAN_MOD_1G_MAC, /**< 1G MAC event */ -+ E_FMAN_MOD_TMR, /**< Timer event */ -+ E_FMAN_MOD_FMAN_CTRL, /**< FMAN Controller Timer event */ -+ E_FMAN_MOD_MACSEC, -+ E_FMAN_MOD_DUMMY_LAST -+}; -+ -+/**************************************************************************//** -+ @Description Enum for interrupts types -+*//***************************************************************************/ -+enum fman_intr_type { -+ E_FMAN_INTR_TYPE_ERR, -+ E_FMAN_INTR_TYPE_NORMAL -+}; -+ -+/**************************************************************************//** -+ @Description enum for defining MAC types -+*//***************************************************************************/ -+enum fman_mac_type { -+ E_FMAN_MAC_10G = 0, /**< 10G MAC */ -+ E_FMAN_MAC_1G /**< 1G MAC */ -+}; -+ -+enum fman_mac_exceptions { -+ E_FMAN_MAC_EX_10G_MDIO_SCAN_EVENTMDIO = 0, -+ /**< 10GEC MDIO scan event interrupt */ -+ E_FMAN_MAC_EX_10G_MDIO_CMD_CMPL, -+ /**< 10GEC MDIO command completion interrupt */ -+ E_FMAN_MAC_EX_10G_REM_FAULT, -+ /**< 10GEC, mEMAC Remote fault interrupt */ -+ E_FMAN_MAC_EX_10G_LOC_FAULT, -+ /**< 10GEC, mEMAC Local fault interrupt */ -+ E_FMAN_MAC_EX_10G_1TX_ECC_ER, -+ /**< 10GEC, mEMAC Transmit frame ECC error interrupt */ -+ E_FMAN_MAC_EX_10G_TX_FIFO_UNFL, -+ /**< 10GEC, mEMAC Transmit FIFO underflow interrupt */ -+ E_FMAN_MAC_EX_10G_TX_FIFO_OVFL, -+ /**< 10GEC, mEMAC Transmit FIFO overflow interrupt */ -+ E_FMAN_MAC_EX_10G_TX_ER, -+ /**< 10GEC Transmit frame error interrupt */ -+ E_FMAN_MAC_EX_10G_RX_FIFO_OVFL, -+ /**< 10GEC, mEMAC Receive FIFO overflow interrupt */ -+ E_FMAN_MAC_EX_10G_RX_ECC_ER, -+ /**< 10GEC, mEMAC Receive frame ECC error interrupt */ -+ E_FMAN_MAC_EX_10G_RX_JAB_FRM, -+ /**< 10GEC Receive jabber frame interrupt */ -+ E_FMAN_MAC_EX_10G_RX_OVRSZ_FRM, -+ /**< 10GEC Receive oversized frame interrupt */ -+ E_FMAN_MAC_EX_10G_RX_RUNT_FRM, -+ /**< 10GEC Receive runt frame interrupt */ -+ E_FMAN_MAC_EX_10G_RX_FRAG_FRM, -+ /**< 10GEC Receive fragment frame interrupt */ -+ E_FMAN_MAC_EX_10G_RX_LEN_ER, -+ /**< 10GEC Receive payload length error interrupt */ -+ E_FMAN_MAC_EX_10G_RX_CRC_ER, -+ /**< 10GEC Receive CRC error interrupt */ -+ E_FMAN_MAC_EX_10G_RX_ALIGN_ER, -+ /**< 10GEC Receive alignment error interrupt */ -+ E_FMAN_MAC_EX_1G_BAB_RX, -+ /**< dTSEC Babbling receive error */ -+ E_FMAN_MAC_EX_1G_RX_CTL, -+ /**< dTSEC Receive control (pause frame) interrupt */ -+ E_FMAN_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET, -+ /**< dTSEC Graceful transmit stop complete */ -+ E_FMAN_MAC_EX_1G_BAB_TX, -+ /**< dTSEC Babbling transmit error */ -+ E_FMAN_MAC_EX_1G_TX_CTL, -+ /**< dTSEC Transmit control (pause frame) interrupt */ -+ E_FMAN_MAC_EX_1G_TX_ERR, -+ /**< dTSEC Transmit error */ -+ E_FMAN_MAC_EX_1G_LATE_COL, -+ /**< dTSEC Late collision */ -+ E_FMAN_MAC_EX_1G_COL_RET_LMT, -+ /**< dTSEC Collision retry limit */ -+ E_FMAN_MAC_EX_1G_TX_FIFO_UNDRN, -+ /**< dTSEC Transmit FIFO underrun */ -+ E_FMAN_MAC_EX_1G_MAG_PCKT, -+ /**< dTSEC Magic Packet detection */ -+ E_FMAN_MAC_EX_1G_MII_MNG_RD_COMPLET, -+ /**< dTSEC MII management read completion */ -+ E_FMAN_MAC_EX_1G_MII_MNG_WR_COMPLET, -+ /**< dTSEC MII management write completion */ -+ E_FMAN_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET, -+ /**< dTSEC Graceful receive stop complete */ -+ E_FMAN_MAC_EX_1G_TX_DATA_ERR, -+ /**< dTSEC Internal data error on transmit */ -+ E_FMAN_MAC_EX_1G_RX_DATA_ERR, -+ /**< dTSEC Internal data error on receive */ -+ E_FMAN_MAC_EX_1G_1588_TS_RX_ERR, -+ /**< dTSEC Time-Stamp Receive Error */ -+ E_FMAN_MAC_EX_1G_RX_MIB_CNT_OVFL, -+ /**< dTSEC MIB counter overflow */ -+ E_FMAN_MAC_EX_TS_FIFO_ECC_ERR, -+ /**< mEMAC Time-stamp FIFO ECC error interrupt; -+ not supported on T4240/B4860 rev1 chips */ -+}; -+ -+#define ENET_IF_SGMII_BASEX 0x80000000 -+ /**< SGMII/QSGII interface with 1000BaseX auto-negotiation between MAC -+ and phy or backplane; -+ Note: 1000BaseX auto-negotiation relates only to interface between MAC -+ and phy/backplane, SGMII phy can still synchronize with far-end phy at -+ 10Mbps, 100Mbps or 1000Mbps */ -+ -+enum enet_mode { -+ E_ENET_MODE_INVALID = 0, -+ /**< Invalid Ethernet mode */ -+ E_ENET_MODE_MII_10 = (E_ENET_IF_MII | E_ENET_SPEED_10), -+ /**< 10 Mbps MII */ -+ E_ENET_MODE_MII_100 = (E_ENET_IF_MII | E_ENET_SPEED_100), -+ /**< 100 Mbps MII */ -+ E_ENET_MODE_RMII_10 = (E_ENET_IF_RMII | E_ENET_SPEED_10), -+ /**< 10 Mbps RMII */ -+ E_ENET_MODE_RMII_100 = (E_ENET_IF_RMII | E_ENET_SPEED_100), -+ /**< 100 Mbps RMII */ -+ E_ENET_MODE_SMII_10 = (E_ENET_IF_SMII | E_ENET_SPEED_10), -+ /**< 10 Mbps SMII */ -+ E_ENET_MODE_SMII_100 = (E_ENET_IF_SMII | E_ENET_SPEED_100), -+ /**< 100 Mbps SMII */ -+ E_ENET_MODE_GMII_1000 = (E_ENET_IF_GMII | E_ENET_SPEED_1000), -+ /**< 1000 Mbps GMII */ -+ E_ENET_MODE_RGMII_10 = (E_ENET_IF_RGMII | E_ENET_SPEED_10), -+ /**< 10 Mbps RGMII */ -+ E_ENET_MODE_RGMII_100 = (E_ENET_IF_RGMII | E_ENET_SPEED_100), -+ /**< 100 Mbps RGMII */ -+ E_ENET_MODE_RGMII_1000 = (E_ENET_IF_RGMII | E_ENET_SPEED_1000), -+ /**< 1000 Mbps RGMII */ -+ E_ENET_MODE_TBI_1000 = (E_ENET_IF_TBI | E_ENET_SPEED_1000), -+ /**< 1000 Mbps TBI */ -+ E_ENET_MODE_RTBI_1000 = (E_ENET_IF_RTBI | E_ENET_SPEED_1000), -+ /**< 1000 Mbps RTBI */ -+ E_ENET_MODE_SGMII_10 = (E_ENET_IF_SGMII | E_ENET_SPEED_10), -+ /**< 10 Mbps SGMII with auto-negotiation between MAC and -+ SGMII phy according to Cisco SGMII specification */ -+ E_ENET_MODE_SGMII_100 = (E_ENET_IF_SGMII | E_ENET_SPEED_100), -+ /**< 100 Mbps SGMII with auto-negotiation between MAC and -+ SGMII phy according to Cisco SGMII specification */ -+ E_ENET_MODE_SGMII_1000 = (E_ENET_IF_SGMII | E_ENET_SPEED_1000), -+ /**< 1000 Mbps SGMII with auto-negotiation between MAC and -+ SGMII phy according to Cisco SGMII specification */ -+ E_ENET_MODE_SGMII_BASEX_10 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII -+ | E_ENET_SPEED_10), -+ /**< 10 Mbps SGMII with 1000BaseX auto-negotiation between -+ MAC and SGMII phy or backplane */ -+ E_ENET_MODE_SGMII_BASEX_100 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII -+ | E_ENET_SPEED_100), -+ /**< 100 Mbps SGMII with 1000BaseX auto-negotiation between -+ MAC and SGMII phy or backplane */ -+ E_ENET_MODE_SGMII_BASEX_1000 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII -+ | E_ENET_SPEED_1000), -+ /**< 1000 Mbps SGMII with 1000BaseX auto-negotiation between -+ MAC and SGMII phy or backplane */ -+ E_ENET_MODE_QSGMII_1000 = (E_ENET_IF_QSGMII | E_ENET_SPEED_1000), -+ /**< 1000 Mbps QSGMII with auto-negotiation between MAC and -+ QSGMII phy according to Cisco QSGMII specification */ -+ E_ENET_MODE_QSGMII_BASEX_1000 = (ENET_IF_SGMII_BASEX | E_ENET_IF_QSGMII -+ | E_ENET_SPEED_1000), -+ /**< 1000 Mbps QSGMII with 1000BaseX auto-negotiation between -+ MAC and QSGMII phy or backplane */ -+ E_ENET_MODE_XGMII_10000 = (E_ENET_IF_XGMII | E_ENET_SPEED_10000), -+ /**< 10000 Mbps XGMII */ -+ E_ENET_MODE_XFI_10000 = (E_ENET_IF_XFI | E_ENET_SPEED_10000) -+ /**< 10000 Mbps XFI */ -+}; -+ -+enum fmam_mac_statistics_level { -+ E_FMAN_MAC_NONE_STATISTICS, /**< No statistics */ -+ E_FMAN_MAC_PARTIAL_STATISTICS, /**< Only error counters are available; -+ Optimized for performance */ -+ E_FMAN_MAC_FULL_STATISTICS /**< All counters available; Not -+ optimized for performance */ -+}; -+ -+#define _MAKE_ENET_MODE(_interface, _speed) (enum enet_mode)((_interface) \ -+ | (_speed)) -+ -+#define _ENET_INTERFACE_FROM_MODE(mode) (enum enet_interface) \ -+ ((mode) & 0x0FFF0000) -+#define _ENET_SPEED_FROM_MODE(mode) (enum enet_speed)((mode) & 0x0000FFFF) -+#define _ENET_ADDR_TO_UINT64(_enet_addr) \ -+ (uint64_t)(((uint64_t)(_enet_addr)[0] << 40) | \ -+ ((uint64_t)(_enet_addr)[1] << 32) | \ -+ ((uint64_t)(_enet_addr)[2] << 24) | \ -+ ((uint64_t)(_enet_addr)[3] << 16) | \ -+ ((uint64_t)(_enet_addr)[4] << 8) | \ -+ ((uint64_t)(_enet_addr)[5])) -+ -+#define _MAKE_ENET_ADDR_FROM_UINT64(_addr64, _enet_addr) \ -+ do { \ -+ int i; \ -+ for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++) \ -+ (_enet_addr)[i] = (uint8_t)((_addr64) >> ((5-i)*8));\ -+ } while (0) -+ -+#endif /* __FSL_ENET_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman.h -@@ -0,0 +1,825 @@ -+/* -+ * Copyright 2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __FSL_FMAN_H -+#define __FSL_FMAN_H -+ -+#include "common/general.h" -+ -+struct fman_ext_pool_params { -+ uint8_t id; /**< External buffer pool id */ -+ uint16_t size; /**< External buffer pool buffer size */ -+}; -+ -+struct fman_ext_pools { -+ uint8_t num_pools_used; /**< Number of pools use by this port */ -+ struct fman_ext_pool_params *ext_buf_pool; -+ /**< Parameters for each port */ -+}; -+ -+struct fman_backup_bm_pools { -+ uint8_t num_backup_pools; /**< Number of BM backup pools - -+ must be smaller than the total number -+ of pools defined for the specified -+ port.*/ -+ uint8_t *pool_ids; /**< numOfBackupPools pool id's, -+ specifying which pools should be used -+ only as backup. Pool id's specified -+ here must be a subset of the pools -+ used by the specified port.*/ -+}; -+ -+/**************************************************************************//** -+ @Description A structure for defining BM pool depletion criteria -+*//***************************************************************************/ -+struct fman_buf_pool_depletion { -+ bool buf_pool_depletion_enabled; -+ bool pools_grp_mode_enable; /**< select mode in which pause frames -+ will be sent after a number of pools -+ (all together!) are depleted */ -+ uint8_t num_pools; /**< the number of depleted pools that -+ will invoke pause frames transmission. -+ */ -+ bool *pools_to_consider; /**< For each pool, TRUE if it should be -+ considered for depletion (Note - this -+ pool must be used by this port!). */ -+ bool single_pool_mode_enable; /**< select mode in which pause frames -+ will be sent after a single-pool -+ is depleted; */ -+ bool *pools_to_consider_for_single_mode; -+ /**< For each pool, TRUE if it should be -+ considered for depletion (Note - this -+ pool must be used by this port!) */ -+ bool has_pfc_priorities; -+ bool *pfc_priorities_en; /**< This field is used by the MAC as -+ the Priority Enable Vector in the PFC -+ frame which is transmitted */ -+}; -+ -+/**************************************************************************//** -+ @Description Enum for defining port DMA swap mode -+*//***************************************************************************/ -+enum fman_dma_swap_option { -+ FMAN_DMA_NO_SWP, /**< No swap, transfer data as is.*/ -+ FMAN_DMA_SWP_PPC_LE, /**< The transferred data should be swapped -+ in PowerPc Little Endian mode. */ -+ FMAN_DMA_SWP_BE /**< The transferred data should be swapped -+ in Big Endian mode */ -+}; -+ -+/**************************************************************************//** -+ @Description Enum for defining port DMA cache attributes -+*//***************************************************************************/ -+enum fman_dma_cache_option { -+ FMAN_DMA_NO_STASH = 0, /**< Cacheable, no Allocate (No Stashing) */ -+ FMAN_DMA_STASH = 1 /**< Cacheable and Allocate (Stashing on) */ -+}; -+ -+typedef struct t_FmPrsResult fm_prs_result_t; -+typedef enum e_EnetMode enet_mode_t; -+typedef t_Handle handle_t; -+ -+struct fman_revision_info { -+ uint8_t majorRev; /**< Major revision */ -+ uint8_t minorRev; /**< Minor revision */ -+}; -+ -+/* sizes */ -+#define CAPWAP_FRAG_EXTRA_SPACE 32 -+#define OFFSET_UNITS 16 -+#define MAX_INT_OFFSET 240 -+#define MAX_IC_SIZE 256 -+#define MAX_EXT_OFFSET 496 -+#define MAX_EXT_BUFFER_OFFSET 511 -+ -+/************************************************************************** -+ @Description Memory Mapped Registers -+***************************************************************************/ -+#define FMAN_LIODN_TBL 64 /* size of LIODN table */ -+ -+struct fman_fpm_regs { -+ uint32_t fmfp_tnc; /**< FPM TNUM Control 0x00 */ -+ uint32_t fmfp_prc; /**< FPM Port_ID FmCtl Association 0x04 */ -+ uint32_t fmfp_brkc; /**< FPM Breakpoint Control 0x08 */ -+ uint32_t fmfp_mxd; /**< FPM Flush Control 0x0c */ -+ uint32_t fmfp_dist1; /**< FPM Dispatch Thresholds1 0x10 */ -+ uint32_t fmfp_dist2; /**< FPM Dispatch Thresholds2 0x14 */ -+ uint32_t fm_epi; /**< FM Error Pending Interrupts 0x18 */ -+ uint32_t fm_rie; /**< FM Error Interrupt Enable 0x1c */ -+ uint32_t fmfp_fcev[4]; /**< FPM FMan-Controller Event 1-4 0x20-0x2f */ -+ uint32_t res0030[4]; /**< res 0x30 - 0x3f */ -+ uint32_t fmfp_cee[4]; /**< PM FMan-Controller Event 1-4 0x40-0x4f */ -+ uint32_t res0050[4]; /**< res 0x50-0x5f */ -+ uint32_t fmfp_tsc1; /**< FPM TimeStamp Control1 0x60 */ -+ uint32_t fmfp_tsc2; /**< FPM TimeStamp Control2 0x64 */ -+ uint32_t fmfp_tsp; /**< FPM Time Stamp 0x68 */ -+ uint32_t fmfp_tsf; /**< FPM Time Stamp Fraction 0x6c */ -+ uint32_t fm_rcr; /**< FM Rams Control 0x70 */ -+ uint32_t fmfp_extc; /**< FPM External Requests Control 0x74 */ -+ uint32_t fmfp_ext1; /**< FPM External Requests Config1 0x78 */ -+ uint32_t fmfp_ext2; /**< FPM External Requests Config2 0x7c */ -+ uint32_t fmfp_drd[16]; /**< FPM Data_Ram Data 0-15 0x80 - 0xbf */ -+ uint32_t fmfp_dra; /**< FPM Data Ram Access 0xc0 */ -+ uint32_t fm_ip_rev_1; /**< FM IP Block Revision 1 0xc4 */ -+ uint32_t fm_ip_rev_2; /**< FM IP Block Revision 2 0xc8 */ -+ uint32_t fm_rstc; /**< FM Reset Command 0xcc */ -+ uint32_t fm_cld; /**< FM Classifier Debug 0xd0 */ -+ uint32_t fm_npi; /**< FM Normal Pending Interrupts 0xd4 */ -+ uint32_t fmfp_exte; /**< FPM External Requests Enable 0xd8 */ -+ uint32_t fmfp_ee; /**< FPM Event & Mask 0xdc */ -+ uint32_t fmfp_cev[4]; /**< FPM CPU Event 1-4 0xe0-0xef */ -+ uint32_t res00f0[4]; /**< res 0xf0-0xff */ -+ uint32_t fmfp_ps[64]; /**< FPM Port Status 0x100-0x1ff */ -+ uint32_t fmfp_clfabc; /**< FPM CLFABC 0x200 */ -+ uint32_t fmfp_clfcc; /**< FPM CLFCC 0x204 */ -+ uint32_t fmfp_clfaval; /**< FPM CLFAVAL 0x208 */ -+ uint32_t fmfp_clfbval; /**< FPM CLFBVAL 0x20c */ -+ uint32_t fmfp_clfcval; /**< FPM CLFCVAL 0x210 */ -+ uint32_t fmfp_clfamsk; /**< FPM CLFAMSK 0x214 */ -+ uint32_t fmfp_clfbmsk; /**< FPM CLFBMSK 0x218 */ -+ uint32_t fmfp_clfcmsk; /**< FPM CLFCMSK 0x21c */ -+ uint32_t fmfp_clfamc; /**< FPM CLFAMC 0x220 */ -+ uint32_t fmfp_clfbmc; /**< FPM CLFBMC 0x224 */ -+ uint32_t fmfp_clfcmc; /**< FPM CLFCMC 0x228 */ -+ uint32_t fmfp_decceh; /**< FPM DECCEH 0x22c */ -+ uint32_t res0230[116]; /**< res 0x230 - 0x3ff */ -+ uint32_t fmfp_ts[128]; /**< 0x400: FPM Task Status 0x400 - 0x5ff */ -+ uint32_t res0600[0x400 - 384]; -+}; -+ -+struct fman_bmi_regs { -+ uint32_t fmbm_init; /**< BMI Initialization 0x00 */ -+ uint32_t fmbm_cfg1; /**< BMI Configuration 1 0x04 */ -+ uint32_t fmbm_cfg2; /**< BMI Configuration 2 0x08 */ -+ uint32_t res000c[5]; /**< 0x0c - 0x1f */ -+ uint32_t fmbm_ievr; /**< Interrupt Event Register 0x20 */ -+ uint32_t fmbm_ier; /**< Interrupt Enable Register 0x24 */ -+ uint32_t fmbm_ifr; /**< Interrupt Force Register 0x28 */ -+ uint32_t res002c[5]; /**< 0x2c - 0x3f */ -+ uint32_t fmbm_arb[8]; /**< BMI Arbitration 0x40 - 0x5f */ -+ uint32_t res0060[12]; /**<0x60 - 0x8f */ -+ uint32_t fmbm_dtc[3]; /**< Debug Trap Counter 0x90 - 0x9b */ -+ uint32_t res009c; /**< 0x9c */ -+ uint32_t fmbm_dcv[3][4]; /**< Debug Compare val 0xa0-0xcf */ -+ uint32_t fmbm_dcm[3][4]; /**< Debug Compare Mask 0xd0-0xff */ -+ uint32_t fmbm_gde; /**< BMI Global Debug Enable 0x100 */ -+ uint32_t fmbm_pp[63]; /**< BMI Port Parameters 0x104 - 0x1ff */ -+ uint32_t res0200; /**< 0x200 */ -+ uint32_t fmbm_pfs[63]; /**< BMI Port FIFO Size 0x204 - 0x2ff */ -+ uint32_t res0300; /**< 0x300 */ -+ uint32_t fmbm_spliodn[63]; /**< Port Partition ID 0x304 - 0x3ff */ -+}; -+ -+struct fman_qmi_regs { -+ uint32_t fmqm_gc; /**< General Configuration Register 0x00 */ -+ uint32_t res0004; /**< 0x04 */ -+ uint32_t fmqm_eie; /**< Error Interrupt Event Register 0x08 */ -+ uint32_t fmqm_eien; /**< Error Interrupt Enable Register 0x0c */ -+ uint32_t fmqm_eif; /**< Error Interrupt Force Register 0x10 */ -+ uint32_t fmqm_ie; /**< Interrupt Event Register 0x14 */ -+ uint32_t fmqm_ien; /**< Interrupt Enable Register 0x18 */ -+ uint32_t fmqm_if; /**< Interrupt Force Register 0x1c */ -+ uint32_t fmqm_gs; /**< Global Status Register 0x20 */ -+ uint32_t fmqm_ts; /**< Task Status Register 0x24 */ -+ uint32_t fmqm_etfc; /**< Enqueue Total Frame Counter 0x28 */ -+ uint32_t fmqm_dtfc; /**< Dequeue Total Frame Counter 0x2c */ -+ uint32_t fmqm_dc0; /**< Dequeue Counter 0 0x30 */ -+ uint32_t fmqm_dc1; /**< Dequeue Counter 1 0x34 */ -+ uint32_t fmqm_dc2; /**< Dequeue Counter 2 0x38 */ -+ uint32_t fmqm_dc3; /**< Dequeue Counter 3 0x3c */ -+ uint32_t fmqm_dfdc; /**< Dequeue FQID from Default Counter 0x40 */ -+ uint32_t fmqm_dfcc; /**< Dequeue FQID from Context Counter 0x44 */ -+ uint32_t fmqm_dffc; /**< Dequeue FQID from FD Counter 0x48 */ -+ uint32_t fmqm_dcc; /**< Dequeue Confirm Counter 0x4c */ -+ uint32_t res0050[7]; /**< 0x50 - 0x6b */ -+ uint32_t fmqm_tapc; /**< Tnum Aging Period Control 0x6c */ -+ uint32_t fmqm_dmcvc; /**< Dequeue MAC Command Valid Counter 0x70 */ -+ uint32_t fmqm_difdcc; /**< Dequeue Invalid FD Command Counter 0x74 */ -+ uint32_t fmqm_da1v; /**< Dequeue A1 Valid Counter 0x78 */ -+ uint32_t res007c; /**< 0x7c */ -+ uint32_t fmqm_dtc; /**< 0x80 Debug Trap Counter 0x80 */ -+ uint32_t fmqm_efddd; /**< 0x84 Enqueue Frame desc Dynamic dbg 0x84 */ -+ uint32_t res0088[2]; /**< 0x88 - 0x8f */ -+ struct { -+ uint32_t fmqm_dtcfg1; /**< 0x90 dbg trap cfg 1 Register 0x00 */ -+ uint32_t fmqm_dtval1; /**< Debug Trap Value 1 Register 0x04 */ -+ uint32_t fmqm_dtm1; /**< Debug Trap Mask 1 Register 0x08 */ -+ uint32_t fmqm_dtc1; /**< Debug Trap Counter 1 Register 0x0c */ -+ uint32_t fmqm_dtcfg2; /**< dbg Trap cfg 2 Register 0x10 */ -+ uint32_t fmqm_dtval2; /**< Debug Trap Value 2 Register 0x14 */ -+ uint32_t fmqm_dtm2; /**< Debug Trap Mask 2 Register 0x18 */ -+ uint32_t res001c; /**< 0x1c */ -+ } dbg_traps[3]; /**< 0x90 - 0xef */ -+ uint8_t res00f0[0x400 - 0xf0]; /**< 0xf0 - 0x3ff */ -+}; -+ -+struct fman_dma_regs { -+ uint32_t fmdmsr; /**< FM DMA status register 0x00 */ -+ uint32_t fmdmmr; /**< FM DMA mode register 0x04 */ -+ uint32_t fmdmtr; /**< FM DMA bus threshold register 0x08 */ -+ uint32_t fmdmhy; /**< FM DMA bus hysteresis register 0x0c */ -+ uint32_t fmdmsetr; /**< FM DMA SOS emergency Threshold Register 0x10 */ -+ uint32_t fmdmtah; /**< FM DMA transfer bus address high reg 0x14 */ -+ uint32_t fmdmtal; /**< FM DMA transfer bus address low reg 0x18 */ -+ uint32_t fmdmtcid; /**< FM DMA transfer bus communication ID reg 0x1c */ -+ uint32_t fmdmra; /**< FM DMA bus internal ram address register 0x20 */ -+ uint32_t fmdmrd; /**< FM DMA bus internal ram data register 0x24 */ -+ uint32_t fmdmwcr; /**< FM DMA CAM watchdog counter value 0x28 */ -+ uint32_t fmdmebcr; /**< FM DMA CAM base in MURAM register 0x2c */ -+ uint32_t fmdmccqdr; /**< FM DMA CAM and CMD Queue Debug reg 0x30 */ -+ uint32_t fmdmccqvr1; /**< FM DMA CAM and CMD Queue Value reg #1 0x34 */ -+ uint32_t fmdmccqvr2; /**< FM DMA CAM and CMD Queue Value reg #2 0x38 */ -+ uint32_t fmdmcqvr3; /**< FM DMA CMD Queue Value register #3 0x3c */ -+ uint32_t fmdmcqvr4; /**< FM DMA CMD Queue Value register #4 0x40 */ -+ uint32_t fmdmcqvr5; /**< FM DMA CMD Queue Value register #5 0x44 */ -+ uint32_t fmdmsefrc; /**< FM DMA Semaphore Entry Full Reject Cntr 0x48 */ -+ uint32_t fmdmsqfrc; /**< FM DMA Semaphore Queue Full Reject Cntr 0x4c */ -+ uint32_t fmdmssrc; /**< FM DMA Semaphore SYNC Reject Counter 0x50 */ -+ uint32_t fmdmdcr; /**< FM DMA Debug Counter 0x54 */ -+ uint32_t fmdmemsr; /**< FM DMA Emergency Smoother Register 0x58 */ -+ uint32_t res005c; /**< 0x5c */ -+ uint32_t fmdmplr[FMAN_LIODN_TBL / 2]; /**< DMA LIODN regs 0x60-0xdf */ -+ uint32_t res00e0[0x400 - 56]; -+}; -+ -+struct fman_rg { -+ struct fman_fpm_regs *fpm_rg; -+ struct fman_dma_regs *dma_rg; -+ struct fman_bmi_regs *bmi_rg; -+ struct fman_qmi_regs *qmi_rg; -+}; -+ -+enum fman_dma_cache_override { -+ E_FMAN_DMA_NO_CACHE_OR = 0, /**< No override of the Cache field */ -+ E_FMAN_DMA_NO_STASH_DATA, /**< No data stashing in system level cache */ -+ E_FMAN_DMA_MAY_STASH_DATA, /**< Stashing allowed in sys level cache */ -+ E_FMAN_DMA_STASH_DATA /**< Stashing performed in system level cache */ -+}; -+ -+enum fman_dma_aid_mode { -+ E_FMAN_DMA_AID_OUT_PORT_ID = 0, /**< 4 LSB of PORT_ID */ -+ E_FMAN_DMA_AID_OUT_TNUM /**< 4 LSB of TNUM */ -+}; -+ -+enum fman_dma_dbg_cnt_mode { -+ E_FMAN_DMA_DBG_NO_CNT = 0, /**< No counting */ -+ E_FMAN_DMA_DBG_CNT_DONE, /**< Count DONE commands */ -+ E_FMAN_DMA_DBG_CNT_COMM_Q_EM, /**< command Q emergency signal */ -+ E_FMAN_DMA_DBG_CNT_INT_READ_EM, /**< Read buf emergency signal */ -+ E_FMAN_DMA_DBG_CNT_INT_WRITE_EM, /**< Write buf emergency signal */ -+ E_FMAN_DMA_DBG_CNT_FPM_WAIT, /**< FPM WAIT signal */ -+ E_FMAN_DMA_DBG_CNT_SIGLE_BIT_ECC, /**< Single bit ECC errors */ -+ E_FMAN_DMA_DBG_CNT_RAW_WAR_PROT /**< RAW & WAR protection counter */ -+}; -+ -+enum fman_dma_emergency_level { -+ E_FMAN_DMA_EM_EBS = 0, /**< EBS emergency */ -+ E_FMAN_DMA_EM_SOS /**< SOS emergency */ -+}; -+ -+enum fman_catastrophic_err { -+ E_FMAN_CATAST_ERR_STALL_PORT = 0, /**< Port_ID stalled reset required */ -+ E_FMAN_CATAST_ERR_STALL_TASK /**< Only erroneous task is stalled */ -+}; -+ -+enum fman_dma_err { -+ E_FMAN_DMA_ERR_CATASTROPHIC = 0, /**< Catastrophic DMA error */ -+ E_FMAN_DMA_ERR_REPORT /**< Reported DMA error */ -+}; -+ -+struct fman_cfg { -+ uint16_t liodn_bs_pr_port[FMAN_LIODN_TBL];/* base per port */ -+ bool en_counters; -+ uint8_t disp_limit_tsh; -+ uint8_t prs_disp_tsh; -+ uint8_t plcr_disp_tsh; -+ uint8_t kg_disp_tsh; -+ uint8_t bmi_disp_tsh; -+ uint8_t qmi_enq_disp_tsh; -+ uint8_t qmi_deq_disp_tsh; -+ uint8_t fm_ctl1_disp_tsh; -+ uint8_t fm_ctl2_disp_tsh; -+ enum fman_dma_cache_override dma_cache_override; -+ enum fman_dma_aid_mode dma_aid_mode; -+ bool dma_aid_override; -+ uint8_t dma_axi_dbg_num_of_beats; -+ uint8_t dma_cam_num_of_entries; -+ uint32_t dma_watchdog; -+ uint8_t dma_comm_qtsh_asrt_emer; -+ uint8_t dma_write_buf_tsh_asrt_emer; -+ uint8_t dma_read_buf_tsh_asrt_emer; -+ uint8_t dma_comm_qtsh_clr_emer; -+ uint8_t dma_write_buf_tsh_clr_emer; -+ uint8_t dma_read_buf_tsh_clr_emer; -+ uint32_t dma_sos_emergency; -+ enum fman_dma_dbg_cnt_mode dma_dbg_cnt_mode; -+ bool dma_stop_on_bus_error; -+ bool dma_en_emergency; -+ uint32_t dma_emergency_bus_select; -+ enum fman_dma_emergency_level dma_emergency_level; -+ bool dma_en_emergency_smoother; -+ uint32_t dma_emergency_switch_counter; -+ bool halt_on_external_activ; -+ bool halt_on_unrecov_ecc_err; -+ enum fman_catastrophic_err catastrophic_err; -+ enum fman_dma_err dma_err; -+ bool en_muram_test_mode; -+ bool en_iram_test_mode; -+ bool external_ecc_rams_enable; -+ uint16_t tnum_aging_period; -+ uint32_t exceptions; -+ uint16_t clk_freq; -+ bool pedantic_dma; -+ uint32_t cam_base_addr; -+ uint32_t fifo_base_addr; -+ uint32_t total_fifo_size; -+ uint8_t total_num_of_tasks; -+ bool qmi_deq_option_support; -+ uint32_t qmi_def_tnums_thresh; -+ bool fman_partition_array; -+ uint8_t num_of_fman_ctrl_evnt_regs; -+}; -+ -+/**************************************************************************//** -+ @Description Exceptions -+*//***************************************************************************/ -+#define FMAN_EX_DMA_BUS_ERROR 0x80000000 -+#define FMAN_EX_DMA_READ_ECC 0x40000000 -+#define FMAN_EX_DMA_SYSTEM_WRITE_ECC 0x20000000 -+#define FMAN_EX_DMA_FM_WRITE_ECC 0x10000000 -+#define FMAN_EX_FPM_STALL_ON_TASKS 0x08000000 -+#define FMAN_EX_FPM_SINGLE_ECC 0x04000000 -+#define FMAN_EX_FPM_DOUBLE_ECC 0x02000000 -+#define FMAN_EX_QMI_SINGLE_ECC 0x01000000 -+#define FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 -+#define FMAN_EX_QMI_DOUBLE_ECC 0x00400000 -+#define FMAN_EX_BMI_LIST_RAM_ECC 0x00200000 -+#define FMAN_EX_BMI_PIPELINE_ECC 0x00100000 -+#define FMAN_EX_BMI_STATISTICS_RAM_ECC 0x00080000 -+#define FMAN_EX_IRAM_ECC 0x00040000 -+#define FMAN_EX_NURAM_ECC 0x00020000 -+#define FMAN_EX_BMI_DISPATCH_RAM_ECC 0x00010000 -+ -+enum fman_exceptions { -+ E_FMAN_EX_DMA_BUS_ERROR = 0, /**< DMA bus error. */ -+ E_FMAN_EX_DMA_READ_ECC, /**< Read Buffer ECC error */ -+ E_FMAN_EX_DMA_SYSTEM_WRITE_ECC, /**< Write Buffer ECC err on sys side */ -+ E_FMAN_EX_DMA_FM_WRITE_ECC, /**< Write Buffer ECC error on FM side */ -+ E_FMAN_EX_FPM_STALL_ON_TASKS, /**< Stall of tasks on FPM */ -+ E_FMAN_EX_FPM_SINGLE_ECC, /**< Single ECC on FPM. */ -+ E_FMAN_EX_FPM_DOUBLE_ECC, /**< Double ECC error on FPM ram access */ -+ E_FMAN_EX_QMI_SINGLE_ECC, /**< Single ECC on QMI. */ -+ E_FMAN_EX_QMI_DOUBLE_ECC, /**< Double bit ECC occurred on QMI */ -+ E_FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID,/**< DeQ from unknown port id */ -+ E_FMAN_EX_BMI_LIST_RAM_ECC, /**< Linked List RAM ECC error */ -+ E_FMAN_EX_BMI_STORAGE_PROFILE_ECC, /**< storage profile */ -+ E_FMAN_EX_BMI_STATISTICS_RAM_ECC, /**< Statistics RAM ECC Err Enable */ -+ E_FMAN_EX_BMI_DISPATCH_RAM_ECC, /**< Dispatch RAM ECC Error Enable */ -+ E_FMAN_EX_IRAM_ECC, /**< Double bit ECC occurred on IRAM*/ -+ E_FMAN_EX_MURAM_ECC /**< Double bit ECC occurred on MURAM*/ -+}; -+ -+enum fman_counters { -+ E_FMAN_COUNTERS_ENQ_TOTAL_FRAME = 0, /**< QMI tot enQ frames counter */ -+ E_FMAN_COUNTERS_DEQ_TOTAL_FRAME, /**< QMI tot deQ frames counter */ -+ E_FMAN_COUNTERS_DEQ_0, /**< QMI 0 frames from QMan counter */ -+ E_FMAN_COUNTERS_DEQ_1, /**< QMI 1 frames from QMan counter */ -+ E_FMAN_COUNTERS_DEQ_2, /**< QMI 2 frames from QMan counter */ -+ E_FMAN_COUNTERS_DEQ_3, /**< QMI 3 frames from QMan counter */ -+ E_FMAN_COUNTERS_DEQ_FROM_DEFAULT, /**< QMI deQ from dflt queue cntr */ -+ E_FMAN_COUNTERS_DEQ_FROM_CONTEXT, /**< QMI deQ from FQ context cntr */ -+ E_FMAN_COUNTERS_DEQ_FROM_FD, /**< QMI deQ from FD command field cntr */ -+ E_FMAN_COUNTERS_DEQ_CONFIRM, /**< QMI dequeue confirm counter */ -+ E_FMAN_COUNTERS_SEMAPHOR_ENTRY_FULL_REJECT, /**< DMA full entry cntr */ -+ E_FMAN_COUNTERS_SEMAPHOR_QUEUE_FULL_REJECT, /**< DMA full CAM Q cntr */ -+ E_FMAN_COUNTERS_SEMAPHOR_SYNC_REJECT /**< DMA sync counter */ -+}; -+ -+#define FPM_PRT_FM_CTL1 0x00000001 -+#define FPM_PRT_FM_CTL2 0x00000002 -+ -+/**************************************************************************//** -+ @Description DMA definitions -+*//***************************************************************************/ -+ -+/* masks */ -+#define DMA_MODE_AID_OR 0x20000000 -+#define DMA_MODE_SBER 0x10000000 -+#define DMA_MODE_BER 0x00200000 -+#define DMA_MODE_EB 0x00100000 -+#define DMA_MODE_ECC 0x00000020 -+#define DMA_MODE_PRIVILEGE_PROT 0x00001000 -+#define DMA_MODE_SECURE_PROT 0x00000800 -+#define DMA_MODE_EMER_READ 0x00080000 -+#define DMA_MODE_EMER_WRITE 0x00040000 -+#define DMA_MODE_CACHE_OR_MASK 0xC0000000 -+#define DMA_MODE_CEN_MASK 0x0000E000 -+#define DMA_MODE_DBG_MASK 0x00000380 -+#define DMA_MODE_AXI_DBG_MASK 0x0F000000 -+ -+#define DMA_EMSR_EMSTR_MASK 0x0000FFFF -+ -+#define DMA_TRANSFER_PORTID_MASK 0xFF000000 -+#define DMA_TRANSFER_TNUM_MASK 0x00FF0000 -+#define DMA_TRANSFER_LIODN_MASK 0x00000FFF -+ -+#define DMA_HIGH_LIODN_MASK 0x0FFF0000 -+#define DMA_LOW_LIODN_MASK 0x00000FFF -+ -+#define DMA_STATUS_CMD_QUEUE_NOT_EMPTY 0x10000000 -+#define DMA_STATUS_BUS_ERR 0x08000000 -+#define DMA_STATUS_READ_ECC 0x04000000 -+#define DMA_STATUS_SYSTEM_WRITE_ECC 0x02000000 -+#define DMA_STATUS_FM_WRITE_ECC 0x01000000 -+#define DMA_STATUS_SYSTEM_DPEXT_ECC 0x00800000 -+#define DMA_STATUS_FM_DPEXT_ECC 0x00400000 -+#define DMA_STATUS_SYSTEM_DPDAT_ECC 0x00200000 -+#define DMA_STATUS_FM_DPDAT_ECC 0x00100000 -+#define DMA_STATUS_FM_SPDAT_ECC 0x00080000 -+ -+#define FM_LIODN_BASE_MASK 0x00000FFF -+ -+/* shifts */ -+#define DMA_MODE_CACHE_OR_SHIFT 30 -+#define DMA_MODE_BUS_PRI_SHIFT 16 -+#define DMA_MODE_AXI_DBG_SHIFT 24 -+#define DMA_MODE_CEN_SHIFT 13 -+#define DMA_MODE_BUS_PROT_SHIFT 10 -+#define DMA_MODE_DBG_SHIFT 7 -+#define DMA_MODE_EMER_LVL_SHIFT 6 -+#define DMA_MODE_AID_MODE_SHIFT 4 -+#define DMA_MODE_MAX_AXI_DBG_NUM_OF_BEATS 16 -+#define DMA_MODE_MAX_CAM_NUM_OF_ENTRIES 32 -+ -+#define DMA_THRESH_COMMQ_SHIFT 24 -+#define DMA_THRESH_READ_INT_BUF_SHIFT 16 -+ -+#define DMA_LIODN_SHIFT 16 -+ -+#define DMA_TRANSFER_PORTID_SHIFT 24 -+#define DMA_TRANSFER_TNUM_SHIFT 16 -+ -+/* sizes */ -+#define DMA_MAX_WATCHDOG 0xffffffff -+ -+/* others */ -+#define DMA_CAM_SIZEOF_ENTRY 0x40 -+#define DMA_CAM_ALIGN 0x1000 -+#define DMA_CAM_UNITS 8 -+ -+/**************************************************************************//** -+ @Description General defines -+*//***************************************************************************/ -+ -+#define FM_DEBUG_STATUS_REGISTER_OFFSET 0x000d1084UL -+#define FM_UCODE_DEBUG_INSTRUCTION 0x6ffff805UL -+ -+/**************************************************************************//** -+ @Description FPM defines -+*//***************************************************************************/ -+ -+/* masks */ -+#define FPM_EV_MASK_DOUBLE_ECC 0x80000000 -+#define FPM_EV_MASK_STALL 0x40000000 -+#define FPM_EV_MASK_SINGLE_ECC 0x20000000 -+#define FPM_EV_MASK_RELEASE_FM 0x00010000 -+#define FPM_EV_MASK_DOUBLE_ECC_EN 0x00008000 -+#define FPM_EV_MASK_STALL_EN 0x00004000 -+#define FPM_EV_MASK_SINGLE_ECC_EN 0x00002000 -+#define FPM_EV_MASK_EXTERNAL_HALT 0x00000008 -+#define FPM_EV_MASK_ECC_ERR_HALT 0x00000004 -+ -+#define FPM_RAM_RAMS_ECC_EN 0x80000000 -+#define FPM_RAM_IRAM_ECC_EN 0x40000000 -+#define FPM_RAM_MURAM_ECC 0x00008000 -+#define FPM_RAM_IRAM_ECC 0x00004000 -+#define FPM_RAM_MURAM_TEST_ECC 0x20000000 -+#define FPM_RAM_IRAM_TEST_ECC 0x10000000 -+#define FPM_RAM_RAMS_ECC_EN_SRC_SEL 0x08000000 -+ -+#define FPM_IRAM_ECC_ERR_EX_EN 0x00020000 -+#define FPM_MURAM_ECC_ERR_EX_EN 0x00040000 -+ -+#define FPM_REV1_MAJOR_MASK 0x0000FF00 -+#define FPM_REV1_MINOR_MASK 0x000000FF -+ -+#define FPM_REV2_INTEG_MASK 0x00FF0000 -+#define FPM_REV2_ERR_MASK 0x0000FF00 -+#define FPM_REV2_CFG_MASK 0x000000FF -+ -+#define FPM_TS_FRACTION_MASK 0x0000FFFF -+#define FPM_TS_CTL_EN 0x80000000 -+ -+#define FPM_PRC_REALSE_STALLED 0x00800000 -+ -+#define FPM_PS_STALLED 0x00800000 -+#define FPM_PS_FM_CTL1_SEL 0x80000000 -+#define FPM_PS_FM_CTL2_SEL 0x40000000 -+#define FPM_PS_FM_CTL_SEL_MASK (FPM_PS_FM_CTL1_SEL | FPM_PS_FM_CTL2_SEL) -+ -+#define FPM_RSTC_FM_RESET 0x80000000 -+#define FPM_RSTC_10G0_RESET 0x04000000 -+#define FPM_RSTC_1G0_RESET 0x40000000 -+#define FPM_RSTC_1G1_RESET 0x20000000 -+#define FPM_RSTC_1G2_RESET 0x10000000 -+#define FPM_RSTC_1G3_RESET 0x08000000 -+#define FPM_RSTC_1G4_RESET 0x02000000 -+ -+ -+#define FPM_DISP_LIMIT_MASK 0x1F000000 -+#define FPM_THR1_PRS_MASK 0xFF000000 -+#define FPM_THR1_KG_MASK 0x00FF0000 -+#define FPM_THR1_PLCR_MASK 0x0000FF00 -+#define FPM_THR1_BMI_MASK 0x000000FF -+ -+#define FPM_THR2_QMI_ENQ_MASK 0xFF000000 -+#define FPM_THR2_QMI_DEQ_MASK 0x000000FF -+#define FPM_THR2_FM_CTL1_MASK 0x00FF0000 -+#define FPM_THR2_FM_CTL2_MASK 0x0000FF00 -+ -+/* shifts */ -+#define FPM_DISP_LIMIT_SHIFT 24 -+ -+#define FPM_THR1_PRS_SHIFT 24 -+#define FPM_THR1_KG_SHIFT 16 -+#define FPM_THR1_PLCR_SHIFT 8 -+#define FPM_THR1_BMI_SHIFT 0 -+ -+#define FPM_THR2_QMI_ENQ_SHIFT 24 -+#define FPM_THR2_QMI_DEQ_SHIFT 0 -+#define FPM_THR2_FM_CTL1_SHIFT 16 -+#define FPM_THR2_FM_CTL2_SHIFT 8 -+ -+#define FPM_EV_MASK_CAT_ERR_SHIFT 1 -+#define FPM_EV_MASK_DMA_ERR_SHIFT 0 -+ -+#define FPM_REV1_MAJOR_SHIFT 8 -+#define FPM_REV1_MINOR_SHIFT 0 -+ -+#define FPM_REV2_INTEG_SHIFT 16 -+#define FPM_REV2_ERR_SHIFT 8 -+#define FPM_REV2_CFG_SHIFT 0 -+ -+#define FPM_TS_INT_SHIFT 16 -+ -+#define FPM_PORT_FM_CTL_PORTID_SHIFT 24 -+ -+#define FPM_PS_FM_CTL_SEL_SHIFT 30 -+#define FPM_PRC_ORA_FM_CTL_SEL_SHIFT 16 -+ -+#define FPM_DISP_LIMIT_SHIFT 24 -+ -+/* Interrupts defines */ -+#define FPM_EVENT_FM_CTL_0 0x00008000 -+#define FPM_EVENT_FM_CTL 0x0000FF00 -+#define FPM_EVENT_FM_CTL_BRK 0x00000080 -+ -+/* others */ -+#define FPM_MAX_DISP_LIMIT 31 -+#define FPM_RSTC_FM_RESET 0x80000000 -+#define FPM_RSTC_1G0_RESET 0x40000000 -+#define FPM_RSTC_1G1_RESET 0x20000000 -+#define FPM_RSTC_1G2_RESET 0x10000000 -+#define FPM_RSTC_1G3_RESET 0x08000000 -+#define FPM_RSTC_10G0_RESET 0x04000000 -+#define FPM_RSTC_1G4_RESET 0x02000000 -+#define FPM_RSTC_1G5_RESET 0x01000000 -+#define FPM_RSTC_1G6_RESET 0x00800000 -+#define FPM_RSTC_1G7_RESET 0x00400000 -+#define FPM_RSTC_10G1_RESET 0x00200000 -+/**************************************************************************//** -+ @Description BMI defines -+*//***************************************************************************/ -+/* masks */ -+#define BMI_INIT_START 0x80000000 -+#define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC 0x80000000 -+#define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000 -+#define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000 -+#define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000 -+#define BMI_NUM_OF_TASKS_MASK 0x3F000000 -+#define BMI_NUM_OF_EXTRA_TASKS_MASK 0x000F0000 -+#define BMI_NUM_OF_DMAS_MASK 0x00000F00 -+#define BMI_NUM_OF_EXTRA_DMAS_MASK 0x0000000F -+#define BMI_FIFO_SIZE_MASK 0x000003FF -+#define BMI_EXTRA_FIFO_SIZE_MASK 0x03FF0000 -+#define BMI_CFG2_DMAS_MASK 0x0000003F -+#define BMI_TOTAL_FIFO_SIZE_MASK 0x07FF0000 -+#define BMI_TOTAL_NUM_OF_TASKS_MASK 0x007F0000 -+ -+/* shifts */ -+#define BMI_CFG2_TASKS_SHIFT 16 -+#define BMI_CFG2_DMAS_SHIFT 0 -+#define BMI_CFG1_FIFO_SIZE_SHIFT 16 -+#define BMI_FIFO_SIZE_SHIFT 0 -+#define BMI_EXTRA_FIFO_SIZE_SHIFT 16 -+#define BMI_NUM_OF_TASKS_SHIFT 24 -+#define BMI_EXTRA_NUM_OF_TASKS_SHIFT 16 -+#define BMI_NUM_OF_DMAS_SHIFT 8 -+#define BMI_EXTRA_NUM_OF_DMAS_SHIFT 0 -+ -+/* others */ -+#define BMI_FIFO_ALIGN 0x100 -+#define FMAN_BMI_FIFO_UNITS 0x100 -+ -+ -+/**************************************************************************//** -+ @Description QMI defines -+*//***************************************************************************/ -+/* masks */ -+#define QMI_CFG_ENQ_EN 0x80000000 -+#define QMI_CFG_DEQ_EN 0x40000000 -+#define QMI_CFG_EN_COUNTERS 0x10000000 -+#define QMI_CFG_SOFT_RESET 0x01000000 -+#define QMI_CFG_DEQ_MASK 0x0000003F -+#define QMI_CFG_ENQ_MASK 0x00003F00 -+ -+#define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000 -+#define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000 -+#define QMI_INTR_EN_SINGLE_ECC 0x80000000 -+ -+/* shifts */ -+#define QMI_CFG_ENQ_SHIFT 8 -+#define QMI_TAPC_TAP 22 -+ -+#define QMI_GS_HALT_NOT_BUSY 0x00000002 -+ -+/**************************************************************************//** -+ @Description IRAM defines -+*//***************************************************************************/ -+/* masks */ -+#define IRAM_IADD_AIE 0x80000000 -+#define IRAM_READY 0x80000000 -+ -+uint32_t fman_get_bmi_err_event(struct fman_bmi_regs *bmi_rg); -+uint32_t fman_get_qmi_err_event(struct fman_qmi_regs *qmi_rg); -+uint32_t fman_get_dma_com_id(struct fman_dma_regs *dma_rg); -+uint64_t fman_get_dma_addr(struct fman_dma_regs *dma_rg); -+uint32_t fman_get_dma_err_event(struct fman_dma_regs *dma_rg); -+uint32_t fman_get_fpm_err_event(struct fman_fpm_regs *fpm_rg); -+uint32_t fman_get_muram_err_event(struct fman_fpm_regs *fpm_rg); -+uint32_t fman_get_iram_err_event(struct fman_fpm_regs *fpm_rg); -+uint32_t fman_get_qmi_event(struct fman_qmi_regs *qmi_rg); -+uint32_t fman_get_fpm_error_interrupts(struct fman_fpm_regs *fpm_rg); -+uint32_t fman_get_ctrl_intr(struct fman_fpm_regs *fpm_rg, -+ uint8_t event_reg_id); -+uint8_t fman_get_qmi_deq_th(struct fman_qmi_regs *qmi_rg); -+uint8_t fman_get_qmi_enq_th(struct fman_qmi_regs *qmi_rg); -+uint16_t fman_get_size_of_fifo(struct fman_bmi_regs *bmi_rg, uint8_t port_id); -+uint32_t fman_get_total_fifo_size(struct fman_bmi_regs *bmi_rg); -+uint16_t fman_get_size_of_extra_fifo(struct fman_bmi_regs *bmi_rg, -+ uint8_t port_id); -+uint8_t fman_get_num_of_tasks(struct fman_bmi_regs *bmi_rg, uint8_t port_id); -+uint8_t fman_get_num_extra_tasks(struct fman_bmi_regs *bmi_rg, -+ uint8_t port_id); -+uint8_t fman_get_num_of_dmas(struct fman_bmi_regs *bmi_rg, uint8_t port_id); -+uint8_t fman_get_num_extra_dmas(struct fman_bmi_regs *bmi_rg, -+ uint8_t port_id); -+uint32_t fman_get_normal_pending(struct fman_fpm_regs *fpm_rg); -+uint32_t fman_get_controller_event(struct fman_fpm_regs *fpm_rg, -+ uint8_t reg_id); -+uint32_t fman_get_error_pending(struct fman_fpm_regs *fpm_rg); -+void fman_get_revision(struct fman_fpm_regs *fpm_rg, uint8_t *major, -+ uint8_t *minor); -+uint32_t fman_get_counter(struct fman_rg *fman_rg, -+ enum fman_counters reg_name); -+uint32_t fman_get_dma_status(struct fman_dma_regs *dma_rg); -+ -+ -+int fman_set_erratum_10gmac_a004_wa(struct fman_fpm_regs *fpm_rg); -+void fman_set_ctrl_intr(struct fman_fpm_regs *fpm_rg, uint8_t event_reg_id, -+ uint32_t enable_events); -+void fman_set_num_of_riscs_per_port(struct fman_fpm_regs *fpm_rg, -+ uint8_t port_id, -+ uint8_t num_fman_ctrls, -+ uint32_t or_fman_ctrl); -+void fman_set_order_restoration_per_port(struct fman_fpm_regs *fpm_rg, -+ uint8_t port_id, -+ bool independent_mode, -+ bool is_rx_port); -+void fman_set_qmi_enq_th(struct fman_qmi_regs *qmi_rg, uint8_t val); -+void fman_set_qmi_deq_th(struct fman_qmi_regs *qmi_rg, uint8_t val); -+void fman_set_liodn_per_port(struct fman_rg *fman_rg, -+ uint8_t port_id, -+ uint16_t liodn_base, -+ uint16_t liodn_offset); -+void fman_set_size_of_fifo(struct fman_bmi_regs *bmi_rg, -+ uint8_t port_id, -+ uint32_t size_of_fifo, -+ uint32_t extra_size_of_fifo); -+void fman_set_num_of_tasks(struct fman_bmi_regs *bmi_rg, -+ uint8_t port_id, -+ uint8_t num_of_tasks, -+ uint8_t num_of_extra_tasks); -+void fman_set_num_of_open_dmas(struct fman_bmi_regs *bmi_rg, -+ uint8_t port_id, -+ uint8_t num_of_open_dmas, -+ uint8_t num_of_extra_open_dmas, -+ uint8_t total_num_of_dmas); -+void fman_set_ports_bandwidth(struct fman_bmi_regs *bmi_rg, uint8_t *weights); -+int fman_set_exception(struct fman_rg *fman_rg, -+ enum fman_exceptions exception, -+ bool enable); -+void fman_set_dma_emergency(struct fman_dma_regs *dma_rg, bool is_write, -+ bool enable); -+void fman_set_dma_ext_bus_pri(struct fman_dma_regs *dma_rg, uint32_t pri); -+void fman_set_congestion_group_pfc_priority(uint32_t *cpg_rg, -+ uint32_t congestion_group_id, -+ uint8_t piority_bit_map, -+ uint32_t reg_num); -+ -+ -+void fman_defconfig(struct fman_cfg *cfg, bool is_master); -+void fman_regconfig(struct fman_rg *fman_rg, struct fman_cfg *cfg); -+int fman_fpm_init(struct fman_fpm_regs *fpm_rg, struct fman_cfg *cfg); -+int fman_bmi_init(struct fman_bmi_regs *bmi_rg, struct fman_cfg *cfg); -+int fman_qmi_init(struct fman_qmi_regs *qmi_rg, struct fman_cfg *cfg); -+int fman_dma_init(struct fman_dma_regs *dma_rg, struct fman_cfg *cfg); -+void fman_free_resources(struct fman_rg *fman_rg); -+int fman_enable(struct fman_rg *fman_rg, struct fman_cfg *cfg); -+void fman_reset(struct fman_fpm_regs *fpm_rg); -+void fman_resume(struct fman_fpm_regs *fpm_rg); -+ -+ -+void fman_enable_time_stamp(struct fman_fpm_regs *fpm_rg, -+ uint8_t count1ubit, -+ uint16_t fm_clk_freq); -+void fman_enable_rams_ecc(struct fman_fpm_regs *fpm_rg); -+void fman_qmi_disable_dispatch_limit(struct fman_fpm_regs *fpm_rg); -+void fman_disable_rams_ecc(struct fman_fpm_regs *fpm_rg); -+void fman_resume_stalled_port(struct fman_fpm_regs *fpm_rg, uint8_t port_id); -+int fman_reset_mac(struct fman_fpm_regs *fpm_rg, uint8_t macId, bool is_10g); -+bool fman_is_port_stalled(struct fman_fpm_regs *fpm_rg, uint8_t port_id); -+bool fman_rams_ecc_is_external_ctl(struct fman_fpm_regs *fpm_rg); -+bool fman_is_qmi_halt_not_busy_state(struct fman_qmi_regs *qmi_rg); -+int fman_modify_counter(struct fman_rg *fman_rg, -+ enum fman_counters reg_name, -+ uint32_t val); -+void fman_force_intr(struct fman_rg *fman_rg, -+ enum fman_exceptions exception); -+void fman_set_vsp_window(struct fman_bmi_regs *bmi_rg, -+ uint8_t port_id, -+ uint8_t base_storage_profile, -+ uint8_t log2_num_of_profiles); -+ -+/**************************************************************************//** -+ @Description default values -+*//***************************************************************************/ -+#define DEFAULT_CATASTROPHIC_ERR E_FMAN_CATAST_ERR_STALL_PORT -+#define DEFAULT_DMA_ERR E_FMAN_DMA_ERR_CATASTROPHIC -+#define DEFAULT_HALT_ON_EXTERNAL_ACTIVATION FALSE /* do not change! if changed, must be disabled for rev1 ! */ -+#define DEFAULT_HALT_ON_UNRECOVERABLE_ECC_ERROR FALSE /* do not change! if changed, must be disabled for rev1 ! */ -+#define DEFAULT_EXTERNAL_ECC_RAMS_ENABLE FALSE -+#define DEFAULT_AID_OVERRIDE FALSE -+#define DEFAULT_AID_MODE E_FMAN_DMA_AID_OUT_TNUM -+#define DEFAULT_DMA_COMM_Q_LOW 0x2A -+#define DEFAULT_DMA_COMM_Q_HIGH 0x3F -+#define DEFAULT_CACHE_OVERRIDE E_FMAN_DMA_NO_CACHE_OR -+#define DEFAULT_DMA_CAM_NUM_OF_ENTRIES 64 -+#define DEFAULT_DMA_DBG_CNT_MODE E_FMAN_DMA_DBG_NO_CNT -+#define DEFAULT_DMA_EN_EMERGENCY FALSE -+#define DEFAULT_DMA_SOS_EMERGENCY 0 -+#define DEFAULT_DMA_WATCHDOG 0 /* disabled */ -+#define DEFAULT_DMA_EN_EMERGENCY_SMOOTHER FALSE -+#define DEFAULT_DMA_EMERGENCY_SWITCH_COUNTER 0 -+#define DEFAULT_DISP_LIMIT 0 -+#define DEFAULT_PRS_DISP_TH 16 -+#define DEFAULT_PLCR_DISP_TH 16 -+#define DEFAULT_KG_DISP_TH 16 -+#define DEFAULT_BMI_DISP_TH 16 -+#define DEFAULT_QMI_ENQ_DISP_TH 16 -+#define DEFAULT_QMI_DEQ_DISP_TH 16 -+#define DEFAULT_FM_CTL1_DISP_TH 16 -+#define DEFAULT_FM_CTL2_DISP_TH 16 -+#define DEFAULT_TNUM_AGING_PERIOD 4 -+ -+ -+#endif /* __FSL_FMAN_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_dtsec.h -@@ -0,0 +1,1096 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __FSL_FMAN_DTSEC_H -+#define __FSL_FMAN_DTSEC_H -+ -+#include "common/general.h" -+#include "fsl_enet.h" -+ -+/** -+ * DOC: dTSEC Init sequence -+ * -+ * To prepare dTSEC block for transfer use the following call sequence: -+ * -+ * - fman_dtsec_defconfig() - This step is optional and yet recommended. Its -+ * use is to obtain the default dTSEC configuration parameters. -+ * -+ * - Change dtsec configuration in &dtsec_cfg. This structure will be used -+ * to customize the dTSEC behavior. -+ * -+ * - fman_dtsec_init() - Applies the configuration on dTSEC hardware. Note that -+ * dTSEC is initialized while both Tx and Rx are disabled. -+ * -+ * - fman_dtsec_set_mac_address() - Set the station address (mac address). -+ * This is used by dTSEC to match against received packets. -+ * -+ * - fman_dtsec_adjust_link() - Set the link speed and duplex parameters -+ * after the PHY establishes the link. -+ * -+ * - dtsec_enable_tx() and dtsec_enable_rx() to enable transmission and -+ * reception. -+ */ -+ -+/** -+ * DOC: dTSEC Graceful stop -+ * -+ * To temporary stop dTSEC activity use fman_dtsec_stop_tx() and -+ * fman_dtsec_stop_rx(). Note that these functions request dTSEC graceful stop -+ * but return before this stop is complete. To query for graceful stop -+ * completion use fman_dtsec_get_event() and check DTSEC_IEVENT_GTSC and -+ * DTSEC_IEVENT_GRSC bits. Alternatively the dTSEC interrupt mask can be set to -+ * enable graceful stop interrupts. -+ * -+ * To resume operation after graceful stop use fman_dtsec_start_tx() and -+ * fman_dtsec_start_rx(). -+ */ -+ -+/** -+ * DOC: dTSEC interrupt handling -+ * -+ * This code does not provide an interrupt handler for dTSEC. Instead this -+ * handler should be implemented and registered to the operating system by the -+ * caller. Some primitives for accessing the event status and mask registers -+ * are provided. -+ * -+ * See "dTSEC Events" section for a list of events that dTSEC can generate. -+ */ -+ -+/** -+ * DOC: dTSEC Events -+ * -+ * Interrupt events cause dTSEC event bits to be set. Software may poll the -+ * event register at any time to check for pending interrupts. If an event -+ * occurs and its corresponding enable bit is set in the interrupt mask -+ * register, the event also causes a hardware interrupt at the PIC. -+ * -+ * To poll for event status use the fman_dtsec_get_event() function. -+ * To configure the interrupt mask use fman_dtsec_enable_interrupt() and -+ * fman_dtsec_disable_interrupt() functions. -+ * After servicing a dTSEC interrupt use fman_dtsec_ack_event to reset the -+ * serviced event bit. -+ * -+ * The following events may be signaled by dTSEC hardware: -+ * -+ * %DTSEC_IEVENT_BABR - Babbling receive error. This bit indicates that -+ * a frame was received with length in excess of the MAC's maximum frame length -+ * register. -+ * -+ * %DTSEC_IEVENT_RXC - Receive control (pause frame) interrupt. A pause -+ * control frame was received while Rx pause frame handling is enabled. -+ * Also see fman_dtsec_handle_rx_pause(). -+ * -+ * %DTSEC_IEVENT_MSRO - MIB counter overflow. The count for one of the MIB -+ * counters has exceeded the size of its register. -+ * -+ * %DTSEC_IEVENT_GTSC - Graceful transmit stop complete. Graceful stop is now -+ * complete. The transmitter is in a stopped state, in which only pause frames -+ * can be transmitted. -+ * Also see fman_dtsec_stop_tx(). -+ * -+ * %DTSEC_IEVENT_BABT - Babbling transmit error. The transmitted frame length -+ * has exceeded the value in the MAC's Maximum Frame Length register. -+ * -+ * %DTSEC_IEVENT_TXC - Transmit control (pause frame) interrupt. his bit -+ * indicates that a control frame was transmitted. -+ * -+ * %DTSEC_IEVENT_TXE - Transmit error. This bit indicates that an error -+ * occurred on the transmitted channel. This bit is set whenever any transmit -+ * error occurs which causes the dTSEC to discard all or part of a frame -+ * (LC, CRL, XFUN). -+ * -+ * %DTSEC_IEVENT_LC - Late collision. This bit indicates that a collision -+ * occurred beyond the collision window (slot time) in half-duplex mode. -+ * The frame is truncated with a bad CRC and the remainder of the frame -+ * is discarded. -+ * -+ * %DTSEC_IEVENT_CRL - Collision retry limit. is bit indicates that the number -+ * of successive transmission collisions has exceeded the MAC's half-duplex -+ * register's retransmission maximum count. The frame is discarded without -+ * being transmitted and transmission of the next frame commences. This only -+ * occurs while in half-duplex mode. -+ * The number of retransmit attempts can be set in -+ * &dtsec_halfdup_cfg.@retransmit before calling fman_dtsec_init(). -+ * -+ * %DTSEC_IEVENT_XFUN - Transmit FIFO underrun. This bit indicates that the -+ * transmit FIFO became empty before the complete frame was transmitted. -+ * The frame is truncated with a bad CRC and the remainder of the frame is -+ * discarded. -+ * -+ * %DTSEC_IEVENT_MAG - TBD -+ * -+ * %DTSEC_IEVENT_MMRD - MII management read completion. -+ * -+ * %DTSEC_IEVENT_MMWR - MII management write completion. -+ * -+ * %DTSEC_IEVENT_GRSC - Graceful receive stop complete. It allows the user to -+ * know if the system has completed the stop and it is safe to write to receive -+ * registers (status, control or configuration registers) that are used by the -+ * system during normal operation. -+ * -+ * %DTSEC_IEVENT_TDPE - Internal data error on transmit. This bit indicates -+ * that the dTSEC has detected a parity error on its stored transmit data, which -+ * is likely to compromise the validity of recently transferred frames. -+ * -+ * %DTSEC_IEVENT_RDPE - Internal data error on receive. This bit indicates that -+ * the dTSEC has detected a parity error on its stored receive data, which is -+ * likely to compromise the validity of recently transferred frames. -+ */ -+/* Interrupt Mask Register (IMASK) */ -+#define DTSEC_IMASK_BREN 0x80000000 -+#define DTSEC_IMASK_RXCEN 0x40000000 -+#define DTSEC_IMASK_MSROEN 0x04000000 -+#define DTSEC_IMASK_GTSCEN 0x02000000 -+#define DTSEC_IMASK_BTEN 0x01000000 -+#define DTSEC_IMASK_TXCEN 0x00800000 -+#define DTSEC_IMASK_TXEEN 0x00400000 -+#define DTSEC_IMASK_LCEN 0x00040000 -+#define DTSEC_IMASK_CRLEN 0x00020000 -+#define DTSEC_IMASK_XFUNEN 0x00010000 -+#define DTSEC_IMASK_ABRTEN 0x00008000 -+#define DTSEC_IMASK_IFERREN 0x00004000 -+#define DTSEC_IMASK_MAGEN 0x00000800 -+#define DTSEC_IMASK_MMRDEN 0x00000400 -+#define DTSEC_IMASK_MMWREN 0x00000200 -+#define DTSEC_IMASK_GRSCEN 0x00000100 -+#define DTSEC_IMASK_TDPEEN 0x00000002 -+#define DTSEC_IMASK_RDPEEN 0x00000001 -+ -+#define DTSEC_EVENTS_MASK \ -+ ((uint32_t)(DTSEC_IMASK_BREN | \ -+ DTSEC_IMASK_RXCEN | \ -+ DTSEC_IMASK_BTEN | \ -+ DTSEC_IMASK_TXCEN | \ -+ DTSEC_IMASK_TXEEN | \ -+ DTSEC_IMASK_ABRTEN | \ -+ DTSEC_IMASK_LCEN | \ -+ DTSEC_IMASK_CRLEN | \ -+ DTSEC_IMASK_XFUNEN | \ -+ DTSEC_IMASK_IFERREN | \ -+ DTSEC_IMASK_MAGEN | \ -+ DTSEC_IMASK_TDPEEN | \ -+ DTSEC_IMASK_RDPEEN)) -+ -+/* dtsec timestamp event bits */ -+#define TMR_PEMASK_TSREEN 0x00010000 -+#define TMR_PEVENT_TSRE 0x00010000 -+ -+/* Group address bit indication */ -+#define MAC_GROUP_ADDRESS 0x0000010000000000ULL -+/* size in bytes of L2 address */ -+#define MAC_ADDRLEN 6 -+ -+#define DEFAULT_HALFDUP_ON FALSE -+#define DEFAULT_HALFDUP_RETRANSMIT 0xf -+#define DEFAULT_HALFDUP_COLL_WINDOW 0x37 -+#define DEFAULT_HALFDUP_EXCESS_DEFER TRUE -+#define DEFAULT_HALFDUP_NO_BACKOFF FALSE -+#define DEFAULT_HALFDUP_BP_NO_BACKOFF FALSE -+#define DEFAULT_HALFDUP_ALT_BACKOFF_VAL 0x0A -+#define DEFAULT_HALFDUP_ALT_BACKOFF_EN FALSE -+#define DEFAULT_RX_DROP_BCAST FALSE -+#define DEFAULT_RX_SHORT_FRM TRUE -+#define DEFAULT_RX_LEN_CHECK FALSE -+#define DEFAULT_TX_PAD_CRC TRUE -+#define DEFAULT_TX_CRC FALSE -+#define DEFAULT_RX_CTRL_ACC FALSE -+#define DEFAULT_TX_PAUSE_TIME 0xf000 -+#define DEFAULT_TBIPA 5 -+#define DEFAULT_RX_PREPEND 0 -+#define DEFAULT_PTP_TSU_EN TRUE -+#define DEFAULT_PTP_EXCEPTION_EN TRUE -+#define DEFAULT_PREAMBLE_LEN 7 -+#define DEFAULT_RX_PREAMBLE FALSE -+#define DEFAULT_TX_PREAMBLE FALSE -+#define DEFAULT_LOOPBACK FALSE -+#define DEFAULT_RX_TIME_STAMP_EN FALSE -+#define DEFAULT_TX_TIME_STAMP_EN FALSE -+#define DEFAULT_RX_FLOW TRUE -+#define DEFAULT_TX_FLOW TRUE -+#define DEFAULT_RX_GROUP_HASH_EXD FALSE -+#define DEFAULT_TX_PAUSE_TIME_EXTD 0 -+#define DEFAULT_RX_PROMISC FALSE -+#define DEFAULT_NON_BACK_TO_BACK_IPG1 0x40 -+#define DEFAULT_NON_BACK_TO_BACK_IPG2 0x60 -+#define DEFAULT_MIN_IFG_ENFORCEMENT 0x50 -+#define DEFAULT_BACK_TO_BACK_IPG 0x60 -+#define DEFAULT_MAXIMUM_FRAME 0x600 -+#define DEFAULT_TBI_PHY_ADDR 5 -+#define DEFAULT_WAKE_ON_LAN FALSE -+ -+/* register related defines (bits, field offsets..) */ -+#define DTSEC_ID1_ID 0xffff0000 -+#define DTSEC_ID1_REV_MJ 0x0000FF00 -+#define DTSEC_ID1_REV_MN 0x000000ff -+ -+#define DTSEC_ID2_INT_REDUCED_OFF 0x00010000 -+#define DTSEC_ID2_INT_NORMAL_OFF 0x00020000 -+ -+#define DTSEC_ECNTRL_CLRCNT 0x00004000 -+#define DTSEC_ECNTRL_AUTOZ 0x00002000 -+#define DTSEC_ECNTRL_STEN 0x00001000 -+#define DTSEC_ECNTRL_CFG_RO 0x80000000 -+#define DTSEC_ECNTRL_GMIIM 0x00000040 -+#define DTSEC_ECNTRL_TBIM 0x00000020 -+#define DTSEC_ECNTRL_SGMIIM 0x00000002 -+#define DTSEC_ECNTRL_RPM 0x00000010 -+#define DTSEC_ECNTRL_R100M 0x00000008 -+#define DTSEC_ECNTRL_RMM 0x00000004 -+#define DTSEC_ECNTRL_QSGMIIM 0x00000001 -+ -+#define DTSEC_TCTRL_THDF 0x00000800 -+#define DTSEC_TCTRL_TTSE 0x00000040 -+#define DTSEC_TCTRL_GTS 0x00000020 -+#define DTSEC_TCTRL_TFC_PAUSE 0x00000010 -+ -+/* PTV offsets */ -+#define PTV_PTE_OFST 16 -+ -+#define RCTRL_CFA 0x00008000 -+#define RCTRL_GHTX 0x00000400 -+#define RCTRL_RTSE 0x00000040 -+#define RCTRL_GRS 0x00000020 -+#define RCTRL_BC_REJ 0x00000010 -+#define RCTRL_MPROM 0x00000008 -+#define RCTRL_RSF 0x00000004 -+#define RCTRL_UPROM 0x00000001 -+#define RCTRL_PROM (RCTRL_UPROM | RCTRL_MPROM) -+ -+#define TMR_CTL_ESFDP 0x00000800 -+#define TMR_CTL_ESFDE 0x00000400 -+ -+#define MACCFG1_SOFT_RESET 0x80000000 -+#define MACCFG1_LOOPBACK 0x00000100 -+#define MACCFG1_RX_FLOW 0x00000020 -+#define MACCFG1_TX_FLOW 0x00000010 -+#define MACCFG1_TX_EN 0x00000001 -+#define MACCFG1_RX_EN 0x00000004 -+#define MACCFG1_RESET_RxMC 0x00080000 -+#define MACCFG1_RESET_TxMC 0x00040000 -+#define MACCFG1_RESET_RxFUN 0x00020000 -+#define MACCFG1_RESET_TxFUN 0x00010000 -+ -+#define MACCFG2_NIBBLE_MODE 0x00000100 -+#define MACCFG2_BYTE_MODE 0x00000200 -+#define MACCFG2_PRE_AM_Rx_EN 0x00000080 -+#define MACCFG2_PRE_AM_Tx_EN 0x00000040 -+#define MACCFG2_LENGTH_CHECK 0x00000010 -+#define MACCFG2_MAGIC_PACKET_EN 0x00000008 -+#define MACCFG2_PAD_CRC_EN 0x00000004 -+#define MACCFG2_CRC_EN 0x00000002 -+#define MACCFG2_FULL_DUPLEX 0x00000001 -+ -+#define PREAMBLE_LENGTH_SHIFT 12 -+ -+#define IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT 24 -+#define IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT 16 -+#define IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT 8 -+ -+#define IPGIFG_NON_BACK_TO_BACK_IPG_1 0x7F000000 -+#define IPGIFG_NON_BACK_TO_BACK_IPG_2 0x007F0000 -+#define IPGIFG_MIN_IFG_ENFORCEMENT 0x0000FF00 -+#define IPGIFG_BACK_TO_BACK_IPG 0x0000007F -+ -+#define HAFDUP_ALT_BEB 0x00080000 -+#define HAFDUP_BP_NO_BACKOFF 0x00040000 -+#define HAFDUP_NO_BACKOFF 0x00020000 -+#define HAFDUP_EXCESS_DEFER 0x00010000 -+#define HAFDUP_COLLISION_WINDOW 0x000003ff -+ -+#define HAFDUP_ALTERNATE_BEB_TRUNCATION_SHIFT 20 -+#define HAFDUP_RETRANSMISSION_MAX_SHIFT 12 -+#define HAFDUP_RETRANSMISSION_MAX 0x0000f000 -+ -+#define NUM_OF_HASH_REGS 8 /* Number of hash table registers */ -+ -+/* CAR1/2 bits */ -+#define DTSEC_CAR1_TR64 0x80000000 -+#define DTSEC_CAR1_TR127 0x40000000 -+#define DTSEC_CAR1_TR255 0x20000000 -+#define DTSEC_CAR1_TR511 0x10000000 -+#define DTSEC_CAR1_TRK1 0x08000000 -+#define DTSEC_CAR1_TRMAX 0x04000000 -+#define DTSEC_CAR1_TRMGV 0x02000000 -+ -+#define DTSEC_CAR1_RBYT 0x00010000 -+#define DTSEC_CAR1_RPKT 0x00008000 -+#define DTSEC_CAR1_RFCS 0x00004000 -+#define DTSEC_CAR1_RMCA 0x00002000 -+#define DTSEC_CAR1_RBCA 0x00001000 -+#define DTSEC_CAR1_RXCF 0x00000800 -+#define DTSEC_CAR1_RXPF 0x00000400 -+#define DTSEC_CAR1_RXUO 0x00000200 -+#define DTSEC_CAR1_RALN 0x00000100 -+#define DTSEC_CAR1_RFLR 0x00000080 -+#define DTSEC_CAR1_RCDE 0x00000040 -+#define DTSEC_CAR1_RCSE 0x00000020 -+#define DTSEC_CAR1_RUND 0x00000010 -+#define DTSEC_CAR1_ROVR 0x00000008 -+#define DTSEC_CAR1_RFRG 0x00000004 -+#define DTSEC_CAR1_RJBR 0x00000002 -+#define DTSEC_CAR1_RDRP 0x00000001 -+ -+#define DTSEC_CAR2_TJBR 0x00080000 -+#define DTSEC_CAR2_TFCS 0x00040000 -+#define DTSEC_CAR2_TXCF 0x00020000 -+#define DTSEC_CAR2_TOVR 0x00010000 -+#define DTSEC_CAR2_TUND 0x00008000 -+#define DTSEC_CAR2_TFRG 0x00004000 -+#define DTSEC_CAR2_TBYT 0x00002000 -+#define DTSEC_CAR2_TPKT 0x00001000 -+#define DTSEC_CAR2_TMCA 0x00000800 -+#define DTSEC_CAR2_TBCA 0x00000400 -+#define DTSEC_CAR2_TXPF 0x00000200 -+#define DTSEC_CAR2_TDFR 0x00000100 -+#define DTSEC_CAR2_TEDF 0x00000080 -+#define DTSEC_CAR2_TSCL 0x00000040 -+#define DTSEC_CAR2_TMCL 0x00000020 -+#define DTSEC_CAR2_TLCL 0x00000010 -+#define DTSEC_CAR2_TXCL 0x00000008 -+#define DTSEC_CAR2_TNCL 0x00000004 -+#define DTSEC_CAR2_TDRP 0x00000001 -+ -+#define CAM1_ERRORS_ONLY \ -+ (DTSEC_CAR1_RXPF | DTSEC_CAR1_RALN | DTSEC_CAR1_RFLR \ -+ | DTSEC_CAR1_RCDE | DTSEC_CAR1_RCSE | DTSEC_CAR1_RUND \ -+ | DTSEC_CAR1_ROVR | DTSEC_CAR1_RFRG | DTSEC_CAR1_RJBR \ -+ | DTSEC_CAR1_RDRP) -+ -+#define CAM2_ERRORS_ONLY (DTSEC_CAR2_TFCS | DTSEC_CAR2_TXPF | DTSEC_CAR2_TDRP) -+ -+/* -+ * Group of dTSEC specific counters relating to the standard RMON MIB Group 1 -+ * (or Ethernet) statistics. -+ */ -+#define CAM1_MIB_GRP_1 \ -+ (DTSEC_CAR1_RDRP | DTSEC_CAR1_RBYT | DTSEC_CAR1_RPKT | DTSEC_CAR1_RMCA\ -+ | DTSEC_CAR1_RBCA | DTSEC_CAR1_RALN | DTSEC_CAR1_RUND | DTSEC_CAR1_ROVR\ -+ | DTSEC_CAR1_RFRG | DTSEC_CAR1_RJBR \ -+ | DTSEC_CAR1_TR64 | DTSEC_CAR1_TR127 | DTSEC_CAR1_TR255 \ -+ | DTSEC_CAR1_TR511 | DTSEC_CAR1_TRMAX) -+ -+#define CAM2_MIB_GRP_1 (DTSEC_CAR2_TNCL | DTSEC_CAR2_TDRP) -+ -+/* memory map */ -+ -+struct dtsec_regs { -+ /* dTSEC General Control and Status Registers */ -+ uint32_t tsec_id; /* 0x000 ETSEC_ID register */ -+ uint32_t tsec_id2; /* 0x004 ETSEC_ID2 register */ -+ uint32_t ievent; /* 0x008 Interrupt event register */ -+ uint32_t imask; /* 0x00C Interrupt mask register */ -+ uint32_t reserved0010[1]; -+ uint32_t ecntrl; /* 0x014 E control register */ -+ uint32_t ptv; /* 0x018 Pause time value register */ -+ uint32_t tbipa; /* 0x01C TBI PHY address register */ -+ uint32_t tmr_ctrl; /* 0x020 Time-stamp Control register */ -+ uint32_t tmr_pevent; /* 0x024 Time-stamp event register */ -+ uint32_t tmr_pemask; /* 0x028 Timer event mask register */ -+ uint32_t reserved002c[5]; -+ uint32_t tctrl; /* 0x040 Transmit control register */ -+ uint32_t reserved0044[3]; -+ uint32_t rctrl; /* 0x050 Receive control register */ -+ uint32_t reserved0054[11]; -+ uint32_t igaddr[8]; /* 0x080-0x09C Individual/group address */ -+ uint32_t gaddr[8]; /* 0x0A0-0x0BC Group address registers 0-7 */ -+ uint32_t reserved00c0[16]; -+ uint32_t maccfg1; /* 0x100 MAC configuration #1 */ -+ uint32_t maccfg2; /* 0x104 MAC configuration #2 */ -+ uint32_t ipgifg; /* 0x108 IPG/IFG */ -+ uint32_t hafdup; /* 0x10C Half-duplex */ -+ uint32_t maxfrm; /* 0x110 Maximum frame */ -+ uint32_t reserved0114[10]; -+ uint32_t ifstat; /* 0x13C Interface status */ -+ uint32_t macstnaddr1; /* 0x140 Station Address,part 1 */ -+ uint32_t macstnaddr2; /* 0x144 Station Address,part 2 */ -+ struct { -+ uint32_t exact_match1; /* octets 1-4 */ -+ uint32_t exact_match2; /* octets 5-6 */ -+ } macaddr[15]; /* 0x148-0x1BC mac exact match addresses 1-15 */ -+ uint32_t reserved01c0[16]; -+ uint32_t tr64; /* 0x200 transmit and receive 64 byte frame counter */ -+ uint32_t tr127; /* 0x204 transmit and receive 65 to 127 byte frame -+ * counter */ -+ uint32_t tr255; /* 0x208 transmit and receive 128 to 255 byte frame -+ * counter */ -+ uint32_t tr511; /* 0x20C transmit and receive 256 to 511 byte frame -+ * counter */ -+ uint32_t tr1k; /* 0x210 transmit and receive 512 to 1023 byte frame -+ * counter */ -+ uint32_t trmax; /* 0x214 transmit and receive 1024 to 1518 byte frame -+ * counter */ -+ uint32_t trmgv; /* 0x218 transmit and receive 1519 to 1522 byte good -+ * VLAN frame count */ -+ uint32_t rbyt; /* 0x21C receive byte counter */ -+ uint32_t rpkt; /* 0x220 receive packet counter */ -+ uint32_t rfcs; /* 0x224 receive FCS error counter */ -+ uint32_t rmca; /* 0x228 RMCA receive multicast packet counter */ -+ uint32_t rbca; /* 0x22C receive broadcast packet counter */ -+ uint32_t rxcf; /* 0x230 receive control frame packet counter */ -+ uint32_t rxpf; /* 0x234 receive pause frame packet counter */ -+ uint32_t rxuo; /* 0x238 receive unknown OP code counter */ -+ uint32_t raln; /* 0x23C receive alignment error counter */ -+ uint32_t rflr; /* 0x240 receive frame length error counter */ -+ uint32_t rcde; /* 0x244 receive code error counter */ -+ uint32_t rcse; /* 0x248 receive carrier sense error counter */ -+ uint32_t rund; /* 0x24C receive undersize packet counter */ -+ uint32_t rovr; /* 0x250 receive oversize packet counter */ -+ uint32_t rfrg; /* 0x254 receive fragments counter */ -+ uint32_t rjbr; /* 0x258 receive jabber counter */ -+ uint32_t rdrp; /* 0x25C receive drop */ -+ uint32_t tbyt; /* 0x260 transmit byte counter */ -+ uint32_t tpkt; /* 0x264 transmit packet counter */ -+ uint32_t tmca; /* 0x268 transmit multicast packet counter */ -+ uint32_t tbca; /* 0x26C transmit broadcast packet counter */ -+ uint32_t txpf; /* 0x270 transmit pause control frame counter */ -+ uint32_t tdfr; /* 0x274 transmit deferral packet counter */ -+ uint32_t tedf; /* 0x278 transmit excessive deferral packet counter */ -+ uint32_t tscl; /* 0x27C transmit single collision packet counter */ -+ uint32_t tmcl; /* 0x280 transmit multiple collision packet counter */ -+ uint32_t tlcl; /* 0x284 transmit late collision packet counter */ -+ uint32_t txcl; /* 0x288 transmit excessive collision packet counter */ -+ uint32_t tncl; /* 0x28C transmit total collision counter */ -+ uint32_t reserved0290[1]; -+ uint32_t tdrp; /* 0x294 transmit drop frame counter */ -+ uint32_t tjbr; /* 0x298 transmit jabber frame counter */ -+ uint32_t tfcs; /* 0x29C transmit FCS error counter */ -+ uint32_t txcf; /* 0x2A0 transmit control frame counter */ -+ uint32_t tovr; /* 0x2A4 transmit oversize frame counter */ -+ uint32_t tund; /* 0x2A8 transmit undersize frame counter */ -+ uint32_t tfrg; /* 0x2AC transmit fragments frame counter */ -+ uint32_t car1; /* 0x2B0 carry register one register* */ -+ uint32_t car2; /* 0x2B4 carry register two register* */ -+ uint32_t cam1; /* 0x2B8 carry register one mask register */ -+ uint32_t cam2; /* 0x2BC carry register two mask register */ -+ uint32_t reserved02c0[848]; -+}; -+ -+/** -+ * struct dtsec_mib_grp_1_counters - MIB counter overflows -+ * -+ * @tr64: Transmit and Receive 64 byte frame count. Increment for each -+ * good or bad frame, of any type, transmitted or received, which -+ * is 64 bytes in length. -+ * @tr127: Transmit and Receive 65 to 127 byte frame count. Increments for -+ * each good or bad frame of any type, transmitted or received, -+ * which is 65-127 bytes in length. -+ * @tr255: Transmit and Receive 128 to 255 byte frame count. Increments -+ * for each good or bad frame, of any type, transmitted or -+ * received, which is 128-255 bytes in length. -+ * @tr511: Transmit and Receive 256 to 511 byte frame count. Increments -+ * for each good or bad frame, of any type, transmitted or -+ * received, which is 256-511 bytes in length. -+ * @tr1k: Transmit and Receive 512 to 1023 byte frame count. Increments -+ * for each good or bad frame, of any type, transmitted or -+ * received, which is 512-1023 bytes in length. -+ * @trmax: Transmit and Receive 1024 to 1518 byte frame count. Increments -+ * for each good or bad frame, of any type, transmitted or -+ * received, which is 1024-1518 bytes in length. -+ * @rfrg: Receive fragments count. Increments for each received frame -+ * which is less than 64 bytes in length and contains an invalid -+ * FCS. This includes integral and non-integral lengths. -+ * @rjbr: Receive jabber count. Increments for received frames which -+ * exceed 1518 (non VLAN) or 1522 (VLAN) bytes and contain an -+ * invalid FCS. This includes alignment errors. -+ * @rdrp: Receive dropped packets count. Increments for received frames -+ * which are streamed to system but are later dropped due to lack -+ * of system resources. Does not increment for frames rejected due -+ * to address filtering. -+ * @raln: Receive alignment error count. Increments for each received -+ * frame from 64 to 1518 (non VLAN) or 1522 (VLAN) which contains -+ * an invalid FCS and is not an integral number of bytes. -+ * @rund: Receive undersize packet count. Increments each time a frame is -+ * received which is less than 64 bytes in length and contains a -+ * valid FCS and is otherwise well formed. This count does not -+ * include range length errors. -+ * @rovr: Receive oversize packet count. Increments each time a frame is -+ * received which exceeded 1518 (non VLAN) or 1522 (VLAN) and -+ * contains a valid FCS and is otherwise well formed. -+ * @rbyt: Receive byte count. Increments by the byte count of frames -+ * received, including those in bad packets, excluding preamble and -+ * SFD but including FCS bytes. -+ * @rpkt: Receive packet count. Increments for each received frame -+ * (including bad packets, all unicast, broadcast, and multicast -+ * packets). -+ * @rmca: Receive multicast packet count. Increments for each multicast -+ * frame with valid CRC and of lengths 64 to 1518 (non VLAN) or -+ * 1522 (VLAN), excluding broadcast frames. This count does not -+ * include range/length errors. -+ * @rbca: Receive broadcast packet count. Increments for each broadcast -+ * frame with valid CRC and of lengths 64 to 1518 (non VLAN) or -+ * 1522 (VLAN), excluding multicast frames. Does not include -+ * range/length errors. -+ * @tdrp: Transmit drop frame count. Increments each time a memory error -+ * or an underrun has occurred. -+ * @tncl: Transmit total collision counter. Increments by the number of -+ * collisions experienced during the transmission of a frame. Does -+ * not increment for aborted frames. -+ * -+ * The structure contains a group of dTSEC HW specific counters relating to the -+ * standard RMON MIB Group 1 (or Ethernet statistics) counters. This structure -+ * is counting only the carry events of the corresponding HW counters. -+ * -+ * tr64 to trmax notes: Frame sizes specified are considered excluding preamble -+ * and SFD but including FCS bytes. -+ */ -+struct dtsec_mib_grp_1_counters { -+ uint64_t rdrp; -+ uint64_t tdrp; -+ uint64_t rbyt; -+ uint64_t rpkt; -+ uint64_t rbca; -+ uint64_t rmca; -+ uint64_t raln; -+ uint64_t rund; -+ uint64_t rovr; -+ uint64_t rfrg; -+ uint64_t rjbr; -+ uint64_t tncl; -+ uint64_t tr64; -+ uint64_t tr127; -+ uint64_t tr255; -+ uint64_t tr511; -+ uint64_t tr1k; -+ uint64_t trmax; -+}; -+ -+enum dtsec_stat_counters { -+ E_DTSEC_STAT_TR64, -+ E_DTSEC_STAT_TR127, -+ E_DTSEC_STAT_TR255, -+ E_DTSEC_STAT_TR511, -+ E_DTSEC_STAT_TR1K, -+ E_DTSEC_STAT_TRMAX, -+ E_DTSEC_STAT_TRMGV, -+ E_DTSEC_STAT_RBYT, -+ E_DTSEC_STAT_RPKT, -+ E_DTSEC_STAT_RMCA, -+ E_DTSEC_STAT_RBCA, -+ E_DTSEC_STAT_RXPF, -+ E_DTSEC_STAT_RALN, -+ E_DTSEC_STAT_RFLR, -+ E_DTSEC_STAT_RCDE, -+ E_DTSEC_STAT_RCSE, -+ E_DTSEC_STAT_RUND, -+ E_DTSEC_STAT_ROVR, -+ E_DTSEC_STAT_RFRG, -+ E_DTSEC_STAT_RJBR, -+ E_DTSEC_STAT_RDRP, -+ E_DTSEC_STAT_TFCS, -+ E_DTSEC_STAT_TBYT, -+ E_DTSEC_STAT_TPKT, -+ E_DTSEC_STAT_TMCA, -+ E_DTSEC_STAT_TBCA, -+ E_DTSEC_STAT_TXPF, -+ E_DTSEC_STAT_TNCL, -+ E_DTSEC_STAT_TDRP -+}; -+ -+enum dtsec_stat_level { -+ /* No statistics */ -+ E_MAC_STAT_NONE = 0, -+ /* Only RMON MIB group 1 (ether stats). Optimized for performance */ -+ E_MAC_STAT_MIB_GRP1, -+ /* Only error counters are available. Optimized for performance */ -+ E_MAC_STAT_PARTIAL, -+ /* All counters available. Not optimized for performance */ -+ E_MAC_STAT_FULL -+}; -+ -+ -+/** -+ * struct dtsec_cfg - dTSEC configuration -+ * -+ * @halfdup_on: Transmit half-duplex flow control, under software -+ * control for 10/100-Mbps half-duplex media. If set, -+ * back pressure is applied to media by raising carrier. -+ * @halfdup_retransmit: Number of retransmission attempts following a collision. -+ * If this is exceeded dTSEC aborts transmission due to -+ * excessive collisions. The standard specifies the -+ * attempt limit to be 15. -+ * @halfdup_coll_window:The number of bytes of the frame during which -+ * collisions may occur. The default value of 55 -+ * corresponds to the frame byte at the end of the -+ * standard 512-bit slot time window. If collisions are -+ * detected after this byte, the late collision event is -+ * asserted and transmission of current frame is aborted. -+ * @rx_drop_bcast: Discard broadcast frames. If set, all broadcast frames -+ * will be discarded by dTSEC. -+ * @rx_short_frm: Accept short frames. If set, dTSEC will accept frames -+ * of length 14..63 bytes. -+ * @rx_len_check: Length check for received frames. If set, the MAC -+ * checks the frame's length field on receive to ensure it -+ * matches the actual data field length. This only works -+ * for received frames with length field less than 1500. -+ * No check is performed for larger frames. -+ * @tx_pad_crc: Pad and append CRC. If set, the MAC pads all -+ * transmitted short frames and appends a CRC to every -+ * frame regardless of padding requirement. -+ * @tx_crc: Transmission CRC enable. If set, the MAC appends a CRC -+ * to all frames. If frames presented to the MAC have a -+ * valid length and contain a valid CRC, @tx_crc should be -+ * reset. -+ * This field is ignored if @tx_pad_crc is set. -+ * @rx_ctrl_acc: Control frame accept. If set, this overrides 802.3 -+ * standard control frame behavior, and all Ethernet frames -+ * that have an ethertype of 0x8808 are treated as normal -+ * Ethernet frames and passed up to the packet interface on -+ * a DA match. Received pause control frames are passed to -+ * the packet interface only if Rx flow control is also -+ * disabled. See fman_dtsec_handle_rx_pause() function. -+ * @tx_pause_time: Transmit pause time value. This pause value is used as -+ * part of the pause frame to be sent when a transmit pause -+ * frame is initiated. If set to 0 this disables -+ * transmission of pause frames. -+ * @rx_preamble: Receive preamble enable. If set, the MAC recovers the -+ * received Ethernet 7-byte preamble and passes it to the -+ * packet interface at the start of each received frame. -+ * This field should be reset for internal MAC loop-back -+ * mode. -+ * @tx_preamble: User defined preamble enable for transmitted frames. -+ * If set, a user-defined preamble must passed to the MAC -+ * and it is transmitted instead of the standard preamble. -+ * @preamble_len: Length, in bytes, of the preamble field preceding each -+ * Ethernet start-of-frame delimiter byte. The default -+ * value of 0x7 should be used in order to guarantee -+ * reliable operation with IEEE 802.3 compliant hardware. -+ * @rx_prepend: Packet alignment padding length. The specified number -+ * of bytes (1-31) of zero padding are inserted before the -+ * start of each received frame. For Ethernet, where -+ * optional preamble extraction is enabled, the padding -+ * appears before the preamble, otherwise the padding -+ * precedes the layer 2 header. -+ * -+ * This structure contains basic dTSEC configuration and must be passed to -+ * fman_dtsec_init() function. A default set of configuration values can be -+ * obtained by calling fman_dtsec_defconfig(). -+ */ -+struct dtsec_cfg { -+ bool halfdup_on; -+ bool halfdup_alt_backoff_en; -+ bool halfdup_excess_defer; -+ bool halfdup_no_backoff; -+ bool halfdup_bp_no_backoff; -+ uint8_t halfdup_alt_backoff_val; -+ uint16_t halfdup_retransmit; -+ uint16_t halfdup_coll_window; -+ bool rx_drop_bcast; -+ bool rx_short_frm; -+ bool rx_len_check; -+ bool tx_pad_crc; -+ bool tx_crc; -+ bool rx_ctrl_acc; -+ unsigned short tx_pause_time; -+ unsigned short tbipa; -+ bool ptp_tsu_en; -+ bool ptp_exception_en; -+ bool rx_preamble; -+ bool tx_preamble; -+ unsigned char preamble_len; -+ unsigned char rx_prepend; -+ bool loopback; -+ bool rx_time_stamp_en; -+ bool tx_time_stamp_en; -+ bool rx_flow; -+ bool tx_flow; -+ bool rx_group_hash_exd; -+ bool rx_promisc; -+ uint8_t tbi_phy_addr; -+ uint16_t tx_pause_time_extd; -+ uint16_t maximum_frame; -+ uint32_t non_back_to_back_ipg1; -+ uint32_t non_back_to_back_ipg2; -+ uint32_t min_ifg_enforcement; -+ uint32_t back_to_back_ipg; -+ bool wake_on_lan; -+}; -+ -+ -+/** -+ * fman_dtsec_defconfig() - Get default dTSEC configuration -+ * @cfg: pointer to configuration structure. -+ * -+ * Call this function to obtain a default set of configuration values for -+ * initializing dTSEC. The user can overwrite any of the values before calling -+ * fman_dtsec_init(), if specific configuration needs to be applied. -+ */ -+void fman_dtsec_defconfig(struct dtsec_cfg *cfg); -+ -+/** -+ * fman_dtsec_init() - Init dTSEC hardware block -+ * @regs: Pointer to dTSEC register block -+ * @cfg: dTSEC configuration data -+ * @iface_mode: dTSEC interface mode, the type of MAC - PHY interface. -+ * @iface_speed: 1G or 10G -+ * @macaddr: MAC station address to be assigned to the device -+ * @fm_rev_maj: major rev number -+ * @fm_rev_min: minor rev number -+ * @exceptions_mask: initial exceptions mask -+ * -+ * This function initializes dTSEC and applies basic configuration. -+ * -+ * dTSEC initialization sequence: -+ * Before enabling Rx/Tx call dtsec_set_address() to set MAC address, -+ * fman_dtsec_adjust_link() to configure interface speed and duplex and finally -+ * dtsec_enable_tx()/dtsec_enable_rx() to start transmission and reception. -+ * -+ * Returns: 0 if successful, an error code otherwise. -+ */ -+int fman_dtsec_init(struct dtsec_regs *regs, struct dtsec_cfg *cfg, -+ enum enet_interface iface_mode, -+ enum enet_speed iface_speed, -+ uint8_t *macaddr, uint8_t fm_rev_maj, -+ uint8_t fm_rev_min, -+ uint32_t exception_mask); -+ -+/** -+ * fman_dtsec_enable() - Enable dTSEC Tx and Tx -+ * @regs: Pointer to dTSEC register block -+ * @apply_rx: enable rx side -+ * @apply_tx: enable tx side -+ * -+ * This function resets Tx and Rx graceful stop bit and enables dTSEC Tx and Rx. -+ */ -+void fman_dtsec_enable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx); -+ -+/** -+ * fman_dtsec_disable() - Disable dTSEC Tx and Rx -+ * @regs: Pointer to dTSEC register block -+ * @apply_rx: disable rx side -+ * @apply_tx: disable tx side -+ * -+ * This function disables Tx and Rx in dTSEC. -+ */ -+void fman_dtsec_disable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx); -+ -+/** -+ * fman_dtsec_get_revision() - Get dTSEC hardware revision -+ * @regs: Pointer to dTSEC register block -+ * -+ * Returns dtsec_id content -+ * -+ * Call this function to obtain the dTSEC hardware version. -+ */ -+uint32_t fman_dtsec_get_revision(struct dtsec_regs *regs); -+ -+/** -+ * fman_dtsec_set_mac_address() - Set MAC station address -+ * @regs: Pointer to dTSEC register block -+ * @macaddr: MAC address array -+ * -+ * This function sets MAC station address. To enable unicast reception call -+ * this after fman_dtsec_init(). While promiscuous mode is disabled dTSEC will -+ * match the destination address of received unicast frames against this -+ * address. -+ */ -+void fman_dtsec_set_mac_address(struct dtsec_regs *regs, uint8_t *macaddr); -+ -+/** -+ * fman_dtsec_get_mac_address() - Query MAC station address -+ * @regs: Pointer to dTSEC register block -+ * @macaddr: MAC address array -+ */ -+void fman_dtsec_get_mac_address(struct dtsec_regs *regs, uint8_t *macaddr); -+ -+/** -+ * fman_dtsec_set_uc_promisc() - Sets unicast promiscuous mode -+ * @regs: Pointer to dTSEC register block -+ * @enable: Enable unicast promiscuous mode -+ * -+ * Use this function to enable/disable dTSEC L2 address filtering. If the -+ * address filtering is disabled all unicast packets are accepted. -+ * To set dTSEC in promiscuous mode call both fman_dtsec_set_uc_promisc() and -+ * fman_dtsec_set_mc_promisc() to disable filtering for both unicast and -+ * multicast addresses. -+ */ -+void fman_dtsec_set_uc_promisc(struct dtsec_regs *regs, bool enable); -+ -+/** -+ * fman_dtsec_set_wol() - Enable/Disable wake on lan -+ * (magic packet support) -+ * @regs: Pointer to dTSEC register block -+ * @en: Enable Wake On Lan support in dTSEC -+ * -+ */ -+void fman_dtsec_set_wol(struct dtsec_regs *regs, bool en); -+ -+/** -+ * fman_dtsec_adjust_link() - Adjust dTSEC speed/duplex settings -+ * @regs: Pointer to dTSEC register block -+ * @iface_mode: dTSEC interface mode -+ * @speed: Link speed -+ * @full_dx: True for full-duplex, false for half-duplex. -+ * -+ * This function configures the MAC to function and the desired rates. Use it -+ * to configure dTSEC after fman_dtsec_init() and whenever the link speed -+ * changes (for instance following PHY auto-negociation). -+ * -+ * Returns: 0 if successful, an error code otherwise. -+ */ -+int fman_dtsec_adjust_link(struct dtsec_regs *regs, -+ enum enet_interface iface_mode, -+ enum enet_speed speed, bool full_dx); -+ -+/** -+ * fman_dtsec_set_tbi_phy_addr() - Updates TBI address field -+ * @regs: Pointer to dTSEC register block -+ * @address: Valid PHY address in the range of 1 to 31. 0 is reserved. -+ * -+ * In SGMII mode, the dTSEC's TBIPA field must contain a valid TBI PHY address -+ * so that the associated TBI PHY (i.e. the link) may be initialized. -+ * -+ * Returns: 0 if successful, an error code otherwise. -+ */ -+int fman_dtsec_set_tbi_phy_addr(struct dtsec_regs *regs, -+ uint8_t addr); -+ -+/** -+ * fman_dtsec_set_max_frame_len() - Set max frame length -+ * @regs: Pointer to dTSEC register block -+ * @length: Max frame length. -+ * -+ * Sets maximum frame length for received and transmitted frames. Frames that -+ * exceeds this length are truncated. -+ */ -+void fman_dtsec_set_max_frame_len(struct dtsec_regs *regs, uint16_t length); -+ -+/** -+ * fman_dtsec_get_max_frame_len() - Query max frame length -+ * @regs: Pointer to dTSEC register block -+ * -+ * Returns: the current value of the maximum frame length. -+ */ -+uint16_t fman_dtsec_get_max_frame_len(struct dtsec_regs *regs); -+ -+/** -+ * fman_dtsec_handle_rx_pause() - Configure pause frame handling -+ * @regs: Pointer to dTSEC register block -+ * @en: Enable pause frame handling in dTSEC -+ * -+ * If enabled, dTSEC will handle pause frames internally. This must be disabled -+ * if dTSEC is set in half-duplex mode. -+ * If pause frame handling is disabled and &dtsec_cfg.rx_ctrl_acc is set, pause -+ * frames will be transferred to the packet interface just like regular Ethernet -+ * frames. -+ */ -+void fman_dtsec_handle_rx_pause(struct dtsec_regs *regs, bool en); -+ -+/** -+ * fman_dtsec_set_tx_pause_frames() - Configure Tx pause time -+ * @regs: Pointer to dTSEC register block -+ * @time: Time value included in pause frames -+ * -+ * Call this function to set the time value used in transmitted pause frames. -+ * If time is 0, transmission of pause frames is disabled -+ */ -+void fman_dtsec_set_tx_pause_frames(struct dtsec_regs *regs, uint16_t time); -+ -+/** -+ * fman_dtsec_ack_event() - Acknowledge handled events -+ * @regs: Pointer to dTSEC register block -+ * @ev_mask: Events to acknowledge -+ * -+ * After handling events signaled by dTSEC in either polling or interrupt mode, -+ * call this function to reset the associated status bits in dTSEC event -+ * register. -+ */ -+void fman_dtsec_ack_event(struct dtsec_regs *regs, uint32_t ev_mask); -+ -+/** -+ * fman_dtsec_get_event() - Returns currently asserted events -+ * @regs: Pointer to dTSEC register block -+ * @ev_mask: Mask of relevant events -+ * -+ * Call this function to obtain a bit-mask of events that are currently asserted -+ * in dTSEC, taken from IEVENT register. -+ * -+ * Returns: a bit-mask of events asserted in dTSEC. -+ */ -+uint32_t fman_dtsec_get_event(struct dtsec_regs *regs, uint32_t ev_mask); -+ -+/** -+ * fman_dtsec_get_interrupt_mask() - Returns a bit-mask of enabled interrupts -+ * @regs: Pointer to dTSEC register block -+ * -+ * Call this function to obtain a bit-mask of enabled interrupts -+ * in dTSEC, taken from IMASK register. -+ * -+ * Returns: a bit-mask of enabled interrupts in dTSEC. -+ */ -+uint32_t fman_dtsec_get_interrupt_mask(struct dtsec_regs *regs); -+ -+void fman_dtsec_clear_addr_in_paddr(struct dtsec_regs *regs, -+ uint8_t paddr_num); -+ -+void fman_dtsec_add_addr_in_paddr(struct dtsec_regs *regs, -+ uint64_t addr, -+ uint8_t paddr_num); -+ -+void fman_dtsec_enable_tmr_interrupt (struct dtsec_regs *regs); -+ -+void fman_dtsec_disable_tmr_interrupt(struct dtsec_regs *regs); -+ -+/** -+ * fman_dtsec_disable_interrupt() - Disables interrupts for the specified events -+ * @regs: Pointer to dTSEC register block -+ * @ev_mask: Mask of relevant events -+ * -+ * Call this function to disable interrupts in dTSEC for the specified events. -+ * To enable interrupts use fman_dtsec_enable_interrupt(). -+ */ -+void fman_dtsec_disable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask); -+ -+/** -+ * fman_dtsec_enable_interrupt() - Enable interrupts for the specified events -+ * @regs: Pointer to dTSEC register block -+ * @ev_mask: Mask of relevant events -+ * -+ * Call this function to enable interrupts in dTSEC for the specified events. -+ * To disable interrupts use fman_dtsec_disable_interrupt(). -+ */ -+void fman_dtsec_enable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask); -+ -+/** -+ * fman_dtsec_set_ts() - Enables dTSEC timestamps -+ * @regs: Pointer to dTSEC register block -+ * @en: true to enable timestamps, false to disable them -+ * -+ * Call this function to enable/disable dTSEC timestamps. This affects both -+ * Tx and Rx. -+ */ -+void fman_dtsec_set_ts(struct dtsec_regs *regs, bool en); -+ -+/** -+ * fman_dtsec_set_bucket() - Enables/disables a filter bucket -+ * @regs: Pointer to dTSEC register block -+ * @bucket: Bucket index -+ * @enable: true/false to enable/disable this bucket -+ * -+ * This function enables or disables the specified bucket. Enabling a bucket -+ * associated with an address configures dTSEC to accept received packets -+ * with that destination address. -+ * Multiple addresses may be associated with the same bucket. Disabling a -+ * bucket will affect all addresses associated with that bucket. A bucket that -+ * is enabled requires further filtering and verification in the upper layers -+ * -+ */ -+void fman_dtsec_set_bucket(struct dtsec_regs *regs, int bucket, bool enable); -+ -+/** -+ * dtsec_set_hash_table() - insert a crc code into thr filter table -+ * @regs: Pointer to dTSEC register block -+ * @crc: crc to insert -+ * @mcast: true is this is a multicast address -+ * @ghtx: true if we are in ghtx mode -+ * -+ * This function inserts a crc code into the filter table. -+ */ -+void fman_dtsec_set_hash_table(struct dtsec_regs *regs, uint32_t crc, -+ bool mcast, bool ghtx); -+ -+/** -+ * fman_dtsec_reset_filter_table() - Resets the address filtering table -+ * @regs: Pointer to dTSEC register block -+ * @mcast: Reset multicast entries -+ * @ucast: Reset unicast entries -+ * -+ * Resets all entries in L2 address filter table. After calling this function -+ * all buckets enabled using fman_dtsec_set_bucket() will be disabled. -+ * If dtsec_init_filter_table() was called with @unicast_hash set to false, -+ * @ucast argument is ignored. -+ * This does not affect the primary nor the 15 additional addresses configured -+ * using dtsec_set_address() or dtsec_set_match_address(). -+ */ -+void fman_dtsec_reset_filter_table(struct dtsec_regs *regs, bool mcast, -+ bool ucast); -+ -+/** -+ * fman_dtsec_set_mc_promisc() - Set multicast promiscuous mode -+ * @regs: Pointer to dTSEC register block -+ * @enable: Enable multicast promiscuous mode -+ * -+ * Call this to enable/disable L2 address filtering for multicast packets. -+ */ -+void fman_dtsec_set_mc_promisc(struct dtsec_regs *regs, bool enable); -+ -+/* statistics APIs */ -+ -+/** -+ * fman_dtsec_set_stat_level() - Enable a group of MIB statistics counters -+ * @regs: Pointer to dTSEC register block -+ * @level: Specifies a certain group of dTSEC MIB HW counters or _all_, -+ * to specify all the existing counters. -+ * If set to _none_, it disables all the counters. -+ * -+ * Enables the MIB statistics hw counters and sets up the carry interrupt -+ * masks for the counters corresponding to the @level input parameter. -+ * -+ * Returns: error if invalid @level value given. -+ */ -+int fman_dtsec_set_stat_level(struct dtsec_regs *regs, -+ enum dtsec_stat_level level); -+ -+/** -+ * fman_dtsec_reset_stat() - Completely resets all dTSEC HW counters -+ * @regs: Pointer to dTSEC register block -+ */ -+void fman_dtsec_reset_stat(struct dtsec_regs *regs); -+ -+/** -+ * fman_dtsec_get_clear_carry_regs() - Read and clear carry bits (CAR1-2 registers) -+ * @regs: Pointer to dTSEC register block -+ * @car1: car1 register value -+ * @car2: car2 register value -+ * -+ * When set, the carry bits signal that an overflow occurred on the -+ * corresponding counters. -+ * Note that the carry bits (CAR1-2 registers) will assert the -+ * %DTSEC_IEVENT_MSRO interrupt if unmasked (via CAM1-2 regs). -+ * -+ * Returns: true if overflow occurred, otherwise - false -+ */ -+bool fman_dtsec_get_clear_carry_regs(struct dtsec_regs *regs, -+ uint32_t *car1, uint32_t *car2); -+ -+uint32_t fman_dtsec_check_and_clear_tmr_event(struct dtsec_regs *regs); -+ -+uint32_t fman_dtsec_get_stat_counter(struct dtsec_regs *regs, -+ enum dtsec_stat_counters reg_name); -+ -+void fman_dtsec_start_tx(struct dtsec_regs *regs); -+void fman_dtsec_start_rx(struct dtsec_regs *regs); -+void fman_dtsec_stop_tx(struct dtsec_regs *regs); -+void fman_dtsec_stop_rx(struct dtsec_regs *regs); -+uint32_t fman_dtsec_get_rctrl(struct dtsec_regs *regs); -+ -+ -+#endif /* __FSL_FMAN_DTSEC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_dtsec_mii_acc.h -@@ -0,0 +1,107 @@ -+/* -+ * Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __FSL_FMAN_DTSEC_MII_ACC_H -+#define __FSL_FMAN_DTSEC_MII_ACC_H -+ -+#include "common/general.h" -+ -+ -+/* MII Management Configuration Register */ -+#define MIIMCFG_RESET_MGMT 0x80000000 -+#define MIIMCFG_MGNTCLK_MASK 0x00000007 -+#define MIIMCFG_MGNTCLK_SHIFT 0 -+ -+/* MII Management Command Register */ -+#define MIIMCOM_SCAN_CYCLE 0x00000002 -+#define MIIMCOM_READ_CYCLE 0x00000001 -+ -+/* MII Management Address Register */ -+#define MIIMADD_PHY_ADDR_SHIFT 8 -+#define MIIMADD_PHY_ADDR_MASK 0x00001f00 -+ -+#define MIIMADD_REG_ADDR_SHIFT 0 -+#define MIIMADD_REG_ADDR_MASK 0x0000001f -+ -+/* MII Management Indicator Register */ -+#define MIIMIND_BUSY 0x00000001 -+ -+ -+/* PHY Control Register */ -+#define PHY_CR_PHY_RESET 0x8000 -+#define PHY_CR_LOOPBACK 0x4000 -+#define PHY_CR_SPEED0 0x2000 -+#define PHY_CR_ANE 0x1000 -+#define PHY_CR_RESET_AN 0x0200 -+#define PHY_CR_FULLDUPLEX 0x0100 -+#define PHY_CR_SPEED1 0x0040 -+ -+#define PHY_TBICON_SRESET 0x8000 -+#define PHY_TBICON_SPEED2 0x0020 -+#define PHY_TBICON_CLK_SEL 0x0020 -+#define PHY_TBIANA_SGMII 0x4001 -+#define PHY_TBIANA_1000X 0x01a0 -+/* register map */ -+ -+/* MII Configuration Control Memory Map Registers */ -+struct dtsec_mii_reg { -+ uint32_t reserved1[72]; -+ uint32_t miimcfg; /* MII Mgmt:configuration */ -+ uint32_t miimcom; /* MII Mgmt:command */ -+ uint32_t miimadd; /* MII Mgmt:address */ -+ uint32_t miimcon; /* MII Mgmt:control 3 */ -+ uint32_t miimstat; /* MII Mgmt:status */ -+ uint32_t miimind; /* MII Mgmt:indicators */ -+}; -+ -+/* dTSEC MII API */ -+ -+/* functions to access the mii registers for phy configuration. -+ * this functionality may not be available for all dtsecs in the system. -+ * consult the reference manual for details */ -+void fman_dtsec_mii_reset(struct dtsec_mii_reg *regs); -+/* frequency is in MHz. -+ * note that dtsec clock is 1/2 of fman clock */ -+void fman_dtsec_mii_init(struct dtsec_mii_reg *regs, uint16_t dtsec_freq); -+int fman_dtsec_mii_write_reg(struct dtsec_mii_reg *regs, -+ uint8_t addr, -+ uint8_t reg, -+ uint16_t data, -+ uint16_t dtsec_freq); -+ -+int fman_dtsec_mii_read_reg(struct dtsec_mii_reg *regs, -+ uint8_t addr, -+ uint8_t reg, -+ uint16_t *data, -+ uint16_t dtsec_freq); -+ -+#endif /* __FSL_FMAN_DTSEC_MII_ACC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_kg.h -@@ -0,0 +1,514 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __FSL_FMAN_KG_H -+#define __FSL_FMAN_KG_H -+ -+#include "common/general.h" -+ -+#define FM_KG_NUM_OF_GENERIC_REGS 8 /**< Num of generic KeyGen regs */ -+#define FMAN_MAX_NUM_OF_HW_PORTS 64 -+/**< Total num of masks allowed on KG extractions */ -+#define FM_KG_EXTRACT_MASKS_NUM 4 -+#define FM_KG_NUM_CLS_PLAN_ENTR 8 /**< Num of class. plan regs */ -+#define FM_KG_CLS_PLAN_GRPS_NUM 32 /**< Max num of class. groups */ -+ -+struct fman_kg_regs { -+ uint32_t fmkg_gcr; -+ uint32_t res004; -+ uint32_t res008; -+ uint32_t fmkg_eer; -+ uint32_t fmkg_eeer; -+ uint32_t res014; -+ uint32_t res018; -+ uint32_t fmkg_seer; -+ uint32_t fmkg_seeer; -+ uint32_t fmkg_gsr; -+ uint32_t fmkg_tpc; -+ uint32_t fmkg_serc; -+ uint32_t res030[4]; -+ uint32_t fmkg_fdor; -+ uint32_t fmkg_gdv0r; -+ uint32_t fmkg_gdv1r; -+ uint32_t res04c[6]; -+ uint32_t fmkg_feer; -+ uint32_t res068[38]; -+ uint32_t fmkg_indirect[63]; -+ uint32_t fmkg_ar; -+}; -+ -+struct fman_kg_scheme_regs { -+ uint32_t kgse_mode; /**< MODE */ -+ uint32_t kgse_ekfc; /**< Extract Known Fields Command */ -+ uint32_t kgse_ekdv; /**< Extract Known Default Value */ -+ uint32_t kgse_bmch; /**< Bit Mask Command High */ -+ uint32_t kgse_bmcl; /**< Bit Mask Command Low */ -+ uint32_t kgse_fqb; /**< Frame Queue Base */ -+ uint32_t kgse_hc; /**< Hash Command */ -+ uint32_t kgse_ppc; /**< Policer Profile Command */ -+ uint32_t kgse_gec[FM_KG_NUM_OF_GENERIC_REGS]; -+ /**< Generic Extract Command */ -+ uint32_t kgse_spc; /**< KeyGen Scheme Entry Statistic Packet Counter */ -+ uint32_t kgse_dv0; /**< KeyGen Scheme Entry Default Value 0 */ -+ uint32_t kgse_dv1; /**< KeyGen Scheme Entry Default Value 1 */ -+ uint32_t kgse_ccbs; /**< KeyGen Scheme Entry Coarse Classification Bit*/ -+ uint32_t kgse_mv; /**< KeyGen Scheme Entry Match vector */ -+ uint32_t kgse_om; /**< KeyGen Scheme Entry Operation Mode bits */ -+ uint32_t kgse_vsp; /**< KeyGen Scheme Entry Virtual Storage Profile */ -+}; -+ -+struct fman_kg_pe_regs{ -+ uint32_t fmkg_pe_sp; -+ uint32_t fmkg_pe_cpp; -+}; -+ -+struct fman_kg_cp_regs { -+ uint32_t kgcpe[FM_KG_NUM_CLS_PLAN_ENTR]; -+}; -+ -+ -+#define FM_KG_KGAR_GO 0x80000000 -+#define FM_KG_KGAR_READ 0x40000000 -+#define FM_KG_KGAR_WRITE 0x00000000 -+#define FM_KG_KGAR_SEL_SCHEME_ENTRY 0x00000000 -+#define FM_KG_KGAR_SCM_WSEL_UPDATE_CNT 0x00008000 -+ -+#define KG_SCH_PP_SHIFT_HIGH 0x80000000 -+#define KG_SCH_PP_NO_GEN 0x10000000 -+#define KG_SCH_PP_SHIFT_LOW 0x0000F000 -+#define KG_SCH_MODE_NIA_PLCR 0x40000000 -+#define KG_SCH_GEN_EXTRACT_TYPE 0x00008000 -+#define KG_SCH_BITMASK_MASK 0x000000FF -+#define KG_SCH_GEN_VALID 0x80000000 -+#define KG_SCH_GEN_MASK 0x00FF0000 -+#define FM_PCD_KG_KGAR_ERR 0x20000000 -+#define FM_PCD_KG_KGAR_SEL_CLS_PLAN_ENTRY 0x01000000 -+#define FM_PCD_KG_KGAR_SEL_PORT_ENTRY 0x02000000 -+#define FM_PCD_KG_KGAR_SEL_PORT_WSEL_SP 0x00008000 -+#define FM_PCD_KG_KGAR_SEL_PORT_WSEL_CPP 0x00004000 -+#define FM_PCD_KG_KGAR_WSEL_MASK 0x0000FF00 -+#define KG_SCH_HASH_CONFIG_NO_FQID 0x80000000 -+#define KG_SCH_HASH_CONFIG_SYM 0x40000000 -+ -+#define FM_EX_KG_DOUBLE_ECC 0x80000000 -+#define FM_EX_KG_KEYSIZE_OVERFLOW 0x40000000 -+ -+/* ECC capture register */ -+#define KG_FMKG_SERC_CAP 0x80000000 -+#define KG_FMKG_SERC_CET 0x40000000 -+#define KG_FMKG_SERC_CNT_MSK 0x00FF0000 -+#define KG_FMKG_SERC_CNT_SHIFT 16 -+#define KG_FMKG_SERC_ADDR_MSK 0x000003FF -+ -+/* Masks */ -+#define FM_KG_KGGCR_EN 0x80000000 -+#define KG_SCH_GEN_VALID 0x80000000 -+#define KG_SCH_GEN_EXTRACT_TYPE 0x00008000 -+#define KG_ERR_TYPE_DOUBLE 0x40000000 -+#define KG_ERR_ADDR_MASK 0x00000FFF -+#define KG_SCH_MODE_EN 0x80000000 -+ -+/* shifts */ -+#define FM_KG_KGAR_NUM_SHIFT 16 -+#define FM_KG_PE_CPP_MASK_SHIFT 16 -+#define FM_KG_KGAR_WSEL_SHIFT 8 -+ -+#define FM_KG_SCH_GEN_HT_INVALID 0 -+ -+#define FM_KG_MASK_SEL_GEN_BASE 0x20 -+ -+#define KG_GET_MASK_SEL_SHIFT(shift, i) \ -+switch (i) \ -+{ \ -+ case 0: (shift) = 26; break; \ -+ case 1: (shift) = 20; break; \ -+ case 2: (shift) = 10; break; \ -+ case 3: (shift) = 4; break; \ -+ default: (shift) = 0; \ -+} -+ -+#define KG_GET_MASK_OFFSET_SHIFT(shift, i) \ -+switch (i) \ -+{ \ -+ case 0: (shift) = 16; break; \ -+ case 1: (shift) = 0; break; \ -+ case 2: (shift) = 28; break; \ -+ case 3: (shift) = 24; break; \ -+ default: (shift) = 0; \ -+} -+ -+#define KG_GET_MASK_SHIFT(shift, i) \ -+switch (i) \ -+{ \ -+ case 0: shift = 24; break; \ -+ case 1: shift = 16; break; \ -+ case 2: shift = 8; break; \ -+ case 3: shift = 0; break; \ -+ default: shift = 0; \ -+} -+ -+/* Port entry CPP register */ -+#define FMAN_KG_PE_CPP_MASK_SHIFT 16 -+ -+/* Scheme registers */ -+#define FMAN_KG_SCH_MODE_EN 0x80000000 -+#define FMAN_KG_SCH_MODE_NIA_PLCR 0x40000000 -+#define FMAN_KG_SCH_MODE_CCOBASE_SHIFT 24 -+ -+#define FMAN_KG_SCH_DEF_MAC_ADDR_SHIFT 30 -+#define FMAN_KG_SCH_DEF_VLAN_TCI_SHIFT 28 -+#define FMAN_KG_SCH_DEF_ETYPE_SHIFT 26 -+#define FMAN_KG_SCH_DEF_PPP_SID_SHIFT 24 -+#define FMAN_KG_SCH_DEF_PPP_PID_SHIFT 22 -+#define FMAN_KG_SCH_DEF_MPLS_SHIFT 20 -+#define FMAN_KG_SCH_DEF_IP_ADDR_SHIFT 18 -+#define FMAN_KG_SCH_DEF_PTYPE_SHIFT 16 -+#define FMAN_KG_SCH_DEF_IP_TOS_TC_SHIFT 14 -+#define FMAN_KG_SCH_DEF_IPv6_FL_SHIFT 12 -+#define FMAN_KG_SCH_DEF_IPSEC_SPI_SHIFT 10 -+#define FMAN_KG_SCH_DEF_L4_PORT_SHIFT 8 -+#define FMAN_KG_SCH_DEF_TCP_FLG_SHIFT 6 -+ -+#define FMAN_KG_SCH_GEN_VALID 0x80000000 -+#define FMAN_KG_SCH_GEN_SIZE_MAX 16 -+#define FMAN_KG_SCH_GEN_OR 0x00008000 -+ -+#define FMAN_KG_SCH_GEN_DEF_SHIFT 29 -+#define FMAN_KG_SCH_GEN_SIZE_SHIFT 24 -+#define FMAN_KG_SCH_GEN_MASK_SHIFT 16 -+#define FMAN_KG_SCH_GEN_HT_SHIFT 8 -+ -+#define FMAN_KG_SCH_HASH_HSHIFT_SHIFT 24 -+#define FMAN_KG_SCH_HASH_HSHIFT_MAX 0x28 -+#define FMAN_KG_SCH_HASH_SYM 0x40000000 -+#define FMAN_KG_SCH_HASH_NO_FQID_GEN 0x80000000 -+ -+#define FMAN_KG_SCH_PP_SH_SHIFT 27 -+#define FMAN_KG_SCH_PP_SL_SHIFT 12 -+#define FMAN_KG_SCH_PP_SH_MASK 0x80000000 -+#define FMAN_KG_SCH_PP_SL_MASK 0x0000F000 -+#define FMAN_KG_SCH_PP_SHIFT_MAX 0x17 -+#define FMAN_KG_SCH_PP_MASK_SHIFT 16 -+#define FMAN_KG_SCH_PP_NO_GEN 0x10000000 -+ -+enum fman_kg_gen_extract_src { -+ E_FMAN_KG_GEN_EXTRACT_ETH, -+ E_FMAN_KG_GEN_EXTRACT_ETYPE, -+ E_FMAN_KG_GEN_EXTRACT_SNAP, -+ E_FMAN_KG_GEN_EXTRACT_VLAN_TCI_1, -+ E_FMAN_KG_GEN_EXTRACT_VLAN_TCI_N, -+ E_FMAN_KG_GEN_EXTRACT_PPPoE, -+ E_FMAN_KG_GEN_EXTRACT_MPLS_1, -+ E_FMAN_KG_GEN_EXTRACT_MPLS_2, -+ E_FMAN_KG_GEN_EXTRACT_MPLS_3, -+ E_FMAN_KG_GEN_EXTRACT_MPLS_N, -+ E_FMAN_KG_GEN_EXTRACT_IPv4_1, -+ E_FMAN_KG_GEN_EXTRACT_IPv6_1, -+ E_FMAN_KG_GEN_EXTRACT_IPv4_2, -+ E_FMAN_KG_GEN_EXTRACT_IPv6_2, -+ E_FMAN_KG_GEN_EXTRACT_MINENCAP, -+ E_FMAN_KG_GEN_EXTRACT_IP_PID, -+ E_FMAN_KG_GEN_EXTRACT_GRE, -+ E_FMAN_KG_GEN_EXTRACT_TCP, -+ E_FMAN_KG_GEN_EXTRACT_UDP, -+ E_FMAN_KG_GEN_EXTRACT_SCTP, -+ E_FMAN_KG_GEN_EXTRACT_DCCP, -+ E_FMAN_KG_GEN_EXTRACT_IPSEC_AH, -+ E_FMAN_KG_GEN_EXTRACT_IPSEC_ESP, -+ E_FMAN_KG_GEN_EXTRACT_SHIM_1, -+ E_FMAN_KG_GEN_EXTRACT_SHIM_2, -+ E_FMAN_KG_GEN_EXTRACT_FROM_DFLT, -+ E_FMAN_KG_GEN_EXTRACT_FROM_FRAME_START, -+ E_FMAN_KG_GEN_EXTRACT_FROM_PARSE_RESULT, -+ E_FMAN_KG_GEN_EXTRACT_FROM_END_OF_PARSE, -+ E_FMAN_KG_GEN_EXTRACT_FROM_FQID -+}; -+ -+struct fman_kg_ex_ecc_attr -+{ -+ bool valid; -+ bool double_ecc; -+ uint16_t addr; -+ uint8_t single_ecc_count; -+}; -+ -+enum fman_kg_def_select -+{ -+ E_FMAN_KG_DEF_GLOBAL_0, -+ E_FMAN_KG_DEF_GLOBAL_1, -+ E_FMAN_KG_DEF_SCHEME_0, -+ E_FMAN_KG_DEF_SCHEME_1 -+}; -+ -+struct fman_kg_extract_def -+{ -+ enum fman_kg_def_select mac_addr; -+ enum fman_kg_def_select vlan_tci; -+ enum fman_kg_def_select etype; -+ enum fman_kg_def_select ppp_sid; -+ enum fman_kg_def_select ppp_pid; -+ enum fman_kg_def_select mpls; -+ enum fman_kg_def_select ip_addr; -+ enum fman_kg_def_select ptype; -+ enum fman_kg_def_select ip_tos_tc; -+ enum fman_kg_def_select ipv6_fl; -+ enum fman_kg_def_select ipsec_spi; -+ enum fman_kg_def_select l4_port; -+ enum fman_kg_def_select tcp_flg; -+}; -+ -+enum fman_kg_gen_extract_type -+{ -+ E_FMAN_KG_HASH_EXTRACT, -+ E_FMAN_KG_OR_EXTRACT -+}; -+ -+struct fman_kg_gen_extract_params -+{ -+ /* Hash or Or-ed extract */ -+ enum fman_kg_gen_extract_type type; -+ enum fman_kg_gen_extract_src src; -+ bool no_validation; -+ /* Extraction offset from the header location specified above */ -+ uint8_t offset; -+ /* Size of extraction for FMAN_KG_HASH_EXTRACT, -+ * hash result shift for FMAN_KG_OR_EXTRACT */ -+ uint8_t extract; -+ uint8_t mask; -+ /* Default value to use when header specified -+ * by fman_kg_gen_extract_src doesn't present */ -+ enum fman_kg_def_select def_val; -+}; -+ -+struct fman_kg_extract_mask -+{ -+ /**< Indication if mask is on known field extraction or -+ * on general extraction; TRUE for known field */ -+ bool is_known; -+ /**< One of FMAN_KG_EXTRACT_xxx defines for known fields mask and -+ * generic register index for generic extracts mask */ -+ uint32_t field_or_gen_idx; -+ /**< Byte offset from start of the extracted data specified -+ * by field_or_gen_idx */ -+ uint8_t offset; -+ /**< Byte mask (selected bits will be used) */ -+ uint8_t mask; -+}; -+ -+struct fman_kg_extract_params -+{ -+ /* Or-ed mask of FMAN_KG_EXTRACT_xxx defines */ -+ uint32_t known_fields; -+ struct fman_kg_extract_def known_fields_def; -+ /* Number of entries in gen_extract */ -+ uint8_t gen_extract_num; -+ struct fman_kg_gen_extract_params gen_extract[FM_KG_NUM_OF_GENERIC_REGS]; -+ /* Number of entries in masks */ -+ uint8_t masks_num; -+ struct fman_kg_extract_mask masks[FM_KG_EXTRACT_MASKS_NUM]; -+ uint32_t def_scheme_0; -+ uint32_t def_scheme_1; -+}; -+ -+struct fman_kg_hash_params -+{ -+ bool use_hash; -+ uint8_t shift_r; -+ uint32_t mask; /**< 24-bit mask */ -+ bool sym; /**< Symmetric hash for src and dest pairs */ -+}; -+ -+struct fman_kg_pp_params -+{ -+ uint8_t base; -+ uint8_t shift; -+ uint8_t mask; -+ bool bypass_pp_gen; -+}; -+ -+struct fman_kg_cc_params -+{ -+ uint8_t base_offset; -+ uint32_t qlcv_bits_sel; -+}; -+ -+enum fman_pcd_engine -+{ -+ E_FMAN_PCD_INVALID = 0, /**< Invalid PCD engine indicated*/ -+ E_FMAN_PCD_DONE, /**< No PCD Engine indicated */ -+ E_FMAN_PCD_KG, /**< Keygen indicated */ -+ E_FMAN_PCD_CC, /**< Coarse classification indicated */ -+ E_FMAN_PCD_PLCR, /**< Policer indicated */ -+ E_FMAN_PCD_PRS /**< Parser indicated */ -+}; -+ -+struct fman_kg_cls_plan_params -+{ -+ uint8_t entries_mask; -+ uint32_t mask_vector[FM_KG_NUM_CLS_PLAN_ENTR]; -+}; -+ -+struct fman_kg_scheme_params -+{ -+ uint32_t match_vector; -+ struct fman_kg_extract_params extract_params; -+ struct fman_kg_hash_params hash_params; -+ uint32_t base_fqid; -+ /* What we do w/features supported per FM version ?? */ -+ bool bypass_fqid_gen; -+ struct fman_kg_pp_params policer_params; -+ struct fman_kg_cc_params cc_params; -+ bool update_counter; -+ /**< counter_value: Set scheme counter to the specified value; -+ * relevant only when update_counter = TRUE. */ -+ uint32_t counter_value; -+ enum fman_pcd_engine next_engine; -+ /**< Next engine action code */ -+ uint32_t next_engine_action; -+}; -+ -+ -+ -+int fman_kg_write_ar_wait(struct fman_kg_regs *regs, uint32_t fmkg_ar); -+void fman_kg_write_sp(struct fman_kg_regs *regs, uint32_t sp, bool add); -+void fman_kg_write_cpp(struct fman_kg_regs *regs, uint32_t cpp); -+void fman_kg_get_event(struct fman_kg_regs *regs, -+ uint32_t *event, -+ uint32_t *scheme_idx); -+void fman_kg_init(struct fman_kg_regs *regs, -+ uint32_t exceptions, -+ uint32_t dflt_nia); -+void fman_kg_enable_scheme_interrupts(struct fman_kg_regs *regs); -+void fman_kg_enable(struct fman_kg_regs *regs); -+void fman_kg_disable(struct fman_kg_regs *regs); -+int fman_kg_write_bind_cls_plans(struct fman_kg_regs *regs, -+ uint8_t hwport_id, -+ uint32_t bind_cls_plans); -+int fman_kg_build_bind_cls_plans(uint8_t grp_base, -+ uint8_t grp_mask, -+ uint32_t *bind_cls_plans); -+int fman_kg_write_bind_schemes(struct fman_kg_regs *regs, -+ uint8_t hwport_id, -+ uint32_t schemes); -+int fman_kg_write_cls_plan(struct fman_kg_regs *regs, -+ uint8_t grp_id, -+ uint8_t entries_mask, -+ uint8_t hwport_id, -+ struct fman_kg_cp_regs *cls_plan_regs); -+int fman_kg_build_cls_plan(struct fman_kg_cls_plan_params *params, -+ struct fman_kg_cp_regs *cls_plan_regs); -+uint32_t fman_kg_get_schemes_total_counter(struct fman_kg_regs *regs); -+int fman_kg_set_scheme_counter(struct fman_kg_regs *regs, -+ uint8_t scheme_id, -+ uint8_t hwport_id, -+ uint32_t counter); -+int fman_kg_get_scheme_counter(struct fman_kg_regs *regs, -+ uint8_t scheme_id, -+ uint8_t hwport_id, -+ uint32_t *counter); -+int fman_kg_delete_scheme(struct fman_kg_regs *regs, -+ uint8_t scheme_id, -+ uint8_t hwport_id); -+int fman_kg_write_scheme(struct fman_kg_regs *regs, -+ uint8_t scheme_id, -+ uint8_t hwport_id, -+ struct fman_kg_scheme_regs *scheme_regs, -+ bool update_counter); -+int fman_kg_build_scheme(struct fman_kg_scheme_params *params, -+ struct fman_kg_scheme_regs *scheme_regs); -+void fman_kg_get_capture(struct fman_kg_regs *regs, -+ struct fman_kg_ex_ecc_attr *ecc_attr, -+ bool clear); -+void fman_kg_get_exception(struct fman_kg_regs *regs, -+ uint32_t *events, -+ uint32_t *scheme_ids, -+ bool clear); -+void fman_kg_set_exception(struct fman_kg_regs *regs, -+ uint32_t exception, -+ bool enable); -+void fman_kg_set_dflt_val(struct fman_kg_regs *regs, -+ uint8_t def_id, -+ uint32_t val); -+void fman_kg_set_data_after_prs(struct fman_kg_regs *regs, uint8_t offset); -+ -+ -+ -+/**************************************************************************//** -+ @Description NIA Description -+*//***************************************************************************/ -+#define KG_NIA_ORDER_RESTOR 0x00800000 -+#define KG_NIA_ENG_FM_CTL 0x00000000 -+#define KG_NIA_ENG_PRS 0x00440000 -+#define KG_NIA_ENG_KG 0x00480000 -+#define KG_NIA_ENG_PLCR 0x004C0000 -+#define KG_NIA_ENG_BMI 0x00500000 -+#define KG_NIA_ENG_QMI_ENQ 0x00540000 -+#define KG_NIA_ENG_QMI_DEQ 0x00580000 -+#define KG_NIA_ENG_MASK 0x007C0000 -+ -+#define KG_NIA_AC_MASK 0x0003FFFF -+ -+#define KG_NIA_INVALID 0xFFFFFFFF -+ -+static __inline__ uint32_t fm_kg_build_nia(enum fman_pcd_engine next_engine, -+ uint32_t next_engine_action) -+{ -+ uint32_t nia; -+ -+ if (next_engine_action & ~KG_NIA_AC_MASK) -+ return KG_NIA_INVALID; -+ -+ switch (next_engine) { -+ case E_FMAN_PCD_DONE: -+ nia = KG_NIA_ENG_BMI | next_engine_action; -+ break; -+ -+ case E_FMAN_PCD_KG: -+ nia = KG_NIA_ENG_KG | next_engine_action; -+ break; -+ -+ case E_FMAN_PCD_CC: -+ nia = KG_NIA_ENG_FM_CTL | next_engine_action; -+ break; -+ -+ case E_FMAN_PCD_PLCR: -+ nia = KG_NIA_ENG_PLCR | next_engine_action; -+ break; -+ -+ default: -+ nia = KG_NIA_INVALID; -+ } -+ -+ return nia; -+} -+ -+#endif /* __FSL_FMAN_KG_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_memac.h -@@ -0,0 +1,427 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#ifndef __FSL_FMAN_MEMAC_H -+#define __FSL_FMAN_MEMAC_H -+ -+#include "common/general.h" -+#include "fsl_enet.h" -+ -+ -+#define MEMAC_NUM_OF_PADDRS 7 /* Num of additional exact match MAC adr regs */ -+ -+/* Control and Configuration Register (COMMAND_CONFIG) */ -+#define CMD_CFG_MG 0x80000000 /* 00 Magic Packet detection */ -+#define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */ -+#define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */ -+#define CMD_CFG_SFD_ANY 0x00200000 /* 10 Disable SFD check */ -+#define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */ -+#define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */ -+#define CMD_CFG_SEND_IDLE 0x00010000 /* 15 Force idle generation */ -+#define CMD_CFG_CNT_FRM_EN 0x00002000 /* 18 Control frame rx enable */ -+#define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */ -+#define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */ -+#define CMD_CFG_LOOPBACK_EN 0x00000400 /* 21 XGMII/GMII loopback enable */ -+#define CMD_CFG_TX_ADDR_INS 0x00000200 /* 22 Tx source MAC addr insertion */ -+#define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 Ignore Pause frame quanta */ -+#define CMD_CFG_PAUSE_FWD 0x00000080 /* 24 Terminate/frwd Pause frames */ -+#define CMD_CFG_CRC_FWD 0x00000040 /* 25 Terminate/frwd CRC of frames */ -+#define CMD_CFG_PAD_EN 0x00000020 /* 26 Frame padding removal */ -+#define CMD_CFG_PROMIS_EN 0x00000010 /* 27 Promiscuous operation enable */ -+#define CMD_CFG_WAN_MODE 0x00000008 /* 28 WAN mode enable */ -+#define CMD_CFG_RX_EN 0x00000002 /* 30 MAC receive path enable */ -+#define CMD_CFG_TX_EN 0x00000001 /* 31 MAC transmit path enable */ -+ -+/* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */ -+#define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF0000 -+#define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF -+#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x00400000 -+#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x00100000 -+#define TX_FIFO_SECTIONS_TX_EMPTY_PFC_10G 0x00360000 -+#define TX_FIFO_SECTIONS_TX_EMPTY_PFC_1G 0x00040000 -+#define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x00000019 -+#define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x00000020 -+#define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G 0x00000060 -+ -+#define GET_TX_EMPTY_DEFAULT_VALUE(_val) \ -+_val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \ -+((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \ -+ (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) : \ -+ (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G)); -+ -+#define GET_TX_EMPTY_PFC_VALUE(_val) \ -+_val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \ -+((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \ -+ (_val |= TX_FIFO_SECTIONS_TX_EMPTY_PFC_10G) : \ -+ (_val |= TX_FIFO_SECTIONS_TX_EMPTY_PFC_1G)); -+ -+/* Interface Mode Register (IF_MODE) */ -+#define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */ -+#define IF_MODE_XGMII 0x00000000 /* 30-31 XGMII (10G) interface */ -+#define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */ -+#define IF_MODE_RGMII 0x00000004 -+#define IF_MODE_RGMII_AUTO 0x00008000 -+#define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */ -+#define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */ -+#define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */ -+#define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */ -+#define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */ -+#define IF_MODE_HD 0x00000040 /* Half duplex operation */ -+ -+/* Hash table Control Register (HASHTABLE_CTRL) */ -+#define HASH_CTRL_MCAST_SHIFT 26 -+#define HASH_CTRL_MCAST_EN 0x00000100 /* 23 Mcast frame rx for hash */ -+#define HASH_CTRL_ADDR_MASK 0x0000003F /* 26-31 Hash table address code */ -+ -+#define GROUP_ADDRESS 0x0000010000000000LL /* MAC mcast indication */ -+#define HASH_TABLE_SIZE 64 /* Hash tbl size */ -+ -+/* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */ -+#define MEMAC_TX_IPG_LENGTH_MASK 0x0000003F -+ -+/* Statistics Configuration Register (STATN_CONFIG) */ -+#define STATS_CFG_CLR 0x00000004 /* 29 Reset all counters */ -+#define STATS_CFG_CLR_ON_RD 0x00000002 /* 30 Clear on read */ -+#define STATS_CFG_SATURATE 0x00000001 /* 31 Saturate at the maximum val */ -+ -+/* Interrupt Mask Register (IMASK) */ -+#define MEMAC_IMASK_MGI 0x40000000 /* 1 Magic pkt detect indication */ -+#define MEMAC_IMASK_TSECC_ER 0x20000000 /* 2 Timestamp FIFO ECC error evnt */ -+#define MEMAC_IMASK_TECC_ER 0x02000000 /* 6 Transmit frame ECC error evnt */ -+#define MEMAC_IMASK_RECC_ER 0x01000000 /* 7 Receive frame ECC error evnt */ -+ -+#define MEMAC_ALL_ERRS_IMASK \ -+ ((uint32_t)(MEMAC_IMASK_TSECC_ER | \ -+ MEMAC_IMASK_TECC_ER | \ -+ MEMAC_IMASK_RECC_ER | \ -+ MEMAC_IMASK_MGI)) -+ -+#define MEMAC_IEVNT_PCS 0x80000000 /* PCS (XG). Link sync (G) */ -+#define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */ -+#define MEMAC_IEVNT_LT 0x20000000 /* Link Training/New page */ -+#define MEMAC_IEVNT_MGI 0x00004000 /* Magic pkt detection */ -+#define MEMAC_IEVNT_TS_ECC_ER 0x00002000 /* Timestamp FIFO ECC error */ -+#define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000 /* Rx FIFO overflow */ -+#define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ -+#define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400 /* Tx FIFO overflow */ -+#define MEMAC_IEVNT_TX_ECC_ER 0x00000200 /* Tx frame ECC error */ -+#define MEMAC_IEVNT_RX_ECC_ER 0x00000100 /* Rx frame ECC error */ -+#define MEMAC_IEVNT_LI_FAULT 0x00000080 /* Link Interruption flt */ -+#define MEMAC_IEVNT_RX_EMPTY 0x00000040 /* Rx FIFO empty */ -+#define MEMAC_IEVNT_TX_EMPTY 0x00000020 /* Tx FIFO empty */ -+#define MEMAC_IEVNT_RX_LOWP 0x00000010 /* Low Power Idle */ -+#define MEMAC_IEVNT_PHY_LOS 0x00000004 /* Phy loss of signal */ -+#define MEMAC_IEVNT_REM_FAULT 0x00000002 /* Remote fault (XGMII) */ -+#define MEMAC_IEVNT_LOC_FAULT 0x00000001 /* Local fault (XGMII) */ -+ -+enum memac_counters { -+ E_MEMAC_COUNTER_R64, -+ E_MEMAC_COUNTER_R127, -+ E_MEMAC_COUNTER_R255, -+ E_MEMAC_COUNTER_R511, -+ E_MEMAC_COUNTER_R1023, -+ E_MEMAC_COUNTER_R1518, -+ E_MEMAC_COUNTER_R1519X, -+ E_MEMAC_COUNTER_RFRG, -+ E_MEMAC_COUNTER_RJBR, -+ E_MEMAC_COUNTER_RDRP, -+ E_MEMAC_COUNTER_RALN, -+ E_MEMAC_COUNTER_TUND, -+ E_MEMAC_COUNTER_ROVR, -+ E_MEMAC_COUNTER_RXPF, -+ E_MEMAC_COUNTER_TXPF, -+ E_MEMAC_COUNTER_ROCT, -+ E_MEMAC_COUNTER_RMCA, -+ E_MEMAC_COUNTER_RBCA, -+ E_MEMAC_COUNTER_RPKT, -+ E_MEMAC_COUNTER_RUCA, -+ E_MEMAC_COUNTER_RERR, -+ E_MEMAC_COUNTER_TOCT, -+ E_MEMAC_COUNTER_TMCA, -+ E_MEMAC_COUNTER_TBCA, -+ E_MEMAC_COUNTER_TUCA, -+ E_MEMAC_COUNTER_TERR -+}; -+ -+#define DEFAULT_PAUSE_QUANTA 0xf000 -+#define DEFAULT_FRAME_LENGTH 0x600 -+#define DEFAULT_TX_IPG_LENGTH 12 -+ -+/* -+ * memory map -+ */ -+ -+struct mac_addr { -+ uint32_t mac_addr_l; /* Lower 32 bits of 48-bit MAC address */ -+ uint32_t mac_addr_u; /* Upper 16 bits of 48-bit MAC address */ -+}; -+ -+struct memac_regs { -+ /* General Control and Status */ -+ uint32_t res0000[2]; -+ uint32_t command_config; /* 0x008 Ctrl and cfg */ -+ struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */ -+ uint32_t maxfrm; /* 0x014 Max frame length */ -+ uint32_t res0018[1]; -+ uint32_t rx_fifo_sections; /* Receive FIFO configuration reg */ -+ uint32_t tx_fifo_sections; /* Transmit FIFO configuration reg */ -+ uint32_t res0024[2]; -+ uint32_t hashtable_ctrl; /* 0x02C Hash table control */ -+ uint32_t res0030[4]; -+ uint32_t ievent; /* 0x040 Interrupt event */ -+ uint32_t tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */ -+ uint32_t res0048; -+ uint32_t imask; /* 0x04C Interrupt mask */ -+ uint32_t res0050; -+ uint32_t pause_quanta[4]; /* 0x054 Pause quanta */ -+ uint32_t pause_thresh[4]; /* 0x064 Pause quanta threshold */ -+ uint32_t rx_pause_status; /* 0x074 Receive pause status */ -+ uint32_t res0078[2]; -+ struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS]; /* 0x80-0x0B4 mac padr */ -+ uint32_t lpwake_timer; /* 0x0B8 Low Power Wakeup Timer */ -+ uint32_t sleep_timer; /* 0x0BC Transmit EEE Low Power Timer */ -+ uint32_t res00c0[8]; -+ uint32_t statn_config; /* 0x0E0 Statistics configuration */ -+ uint32_t res00e4[7]; -+ /* Rx Statistics Counter */ -+ uint32_t reoct_l; -+ uint32_t reoct_u; -+ uint32_t roct_l; -+ uint32_t roct_u; -+ uint32_t raln_l; -+ uint32_t raln_u; -+ uint32_t rxpf_l; -+ uint32_t rxpf_u; -+ uint32_t rfrm_l; -+ uint32_t rfrm_u; -+ uint32_t rfcs_l; -+ uint32_t rfcs_u; -+ uint32_t rvlan_l; -+ uint32_t rvlan_u; -+ uint32_t rerr_l; -+ uint32_t rerr_u; -+ uint32_t ruca_l; -+ uint32_t ruca_u; -+ uint32_t rmca_l; -+ uint32_t rmca_u; -+ uint32_t rbca_l; -+ uint32_t rbca_u; -+ uint32_t rdrp_l; -+ uint32_t rdrp_u; -+ uint32_t rpkt_l; -+ uint32_t rpkt_u; -+ uint32_t rund_l; -+ uint32_t rund_u; -+ uint32_t r64_l; -+ uint32_t r64_u; -+ uint32_t r127_l; -+ uint32_t r127_u; -+ uint32_t r255_l; -+ uint32_t r255_u; -+ uint32_t r511_l; -+ uint32_t r511_u; -+ uint32_t r1023_l; -+ uint32_t r1023_u; -+ uint32_t r1518_l; -+ uint32_t r1518_u; -+ uint32_t r1519x_l; -+ uint32_t r1519x_u; -+ uint32_t rovr_l; -+ uint32_t rovr_u; -+ uint32_t rjbr_l; -+ uint32_t rjbr_u; -+ uint32_t rfrg_l; -+ uint32_t rfrg_u; -+ uint32_t rcnp_l; -+ uint32_t rcnp_u; -+ uint32_t rdrntp_l; -+ uint32_t rdrntp_u; -+ uint32_t res01d0[12]; -+ /* Tx Statistics Counter */ -+ uint32_t teoct_l; -+ uint32_t teoct_u; -+ uint32_t toct_l; -+ uint32_t toct_u; -+ uint32_t res0210[2]; -+ uint32_t txpf_l; -+ uint32_t txpf_u; -+ uint32_t tfrm_l; -+ uint32_t tfrm_u; -+ uint32_t tfcs_l; -+ uint32_t tfcs_u; -+ uint32_t tvlan_l; -+ uint32_t tvlan_u; -+ uint32_t terr_l; -+ uint32_t terr_u; -+ uint32_t tuca_l; -+ uint32_t tuca_u; -+ uint32_t tmca_l; -+ uint32_t tmca_u; -+ uint32_t tbca_l; -+ uint32_t tbca_u; -+ uint32_t res0258[2]; -+ uint32_t tpkt_l; -+ uint32_t tpkt_u; -+ uint32_t tund_l; -+ uint32_t tund_u; -+ uint32_t t64_l; -+ uint32_t t64_u; -+ uint32_t t127_l; -+ uint32_t t127_u; -+ uint32_t t255_l; -+ uint32_t t255_u; -+ uint32_t t511_l; -+ uint32_t t511_u; -+ uint32_t t1023_l; -+ uint32_t t1023_u; -+ uint32_t t1518_l; -+ uint32_t t1518_u; -+ uint32_t t1519x_l; -+ uint32_t t1519x_u; -+ uint32_t res02a8[6]; -+ uint32_t tcnp_l; -+ uint32_t tcnp_u; -+ uint32_t res02c8[14]; -+ /* Line Interface Control */ -+ uint32_t if_mode; /* 0x300 Interface Mode Control */ -+ uint32_t if_status; /* 0x304 Interface Status */ -+ uint32_t res0308[14]; -+ /* HiGig/2 */ -+ uint32_t hg_config; /* 0x340 Control and cfg */ -+ uint32_t res0344[3]; -+ uint32_t hg_pause_quanta; /* 0x350 Pause quanta */ -+ uint32_t res0354[3]; -+ uint32_t hg_pause_thresh; /* 0x360 Pause quanta threshold */ -+ uint32_t res0364[3]; -+ uint32_t hgrx_pause_status; /* 0x370 Receive pause status */ -+ uint32_t hg_fifos_status; /* 0x374 fifos status */ -+ uint32_t rhm; /* 0x378 rx messages counter */ -+ uint32_t thm; /* 0x37C tx messages counter */ -+}; -+ -+struct memac_cfg { -+ bool reset_on_init; -+ bool rx_error_discard; -+ bool pause_ignore; -+ bool pause_forward_enable; -+ bool no_length_check_enable; -+ bool cmd_frame_enable; -+ bool send_idle_enable; -+ bool wan_mode_enable; -+ bool promiscuous_mode_enable; -+ bool tx_addr_ins_enable; -+ bool loopback_enable; -+ bool lgth_check_nostdr; -+ bool time_stamp_enable; -+ bool pad_enable; -+ bool phy_tx_ena_on; -+ bool rx_sfd_any; -+ bool rx_pbl_fwd; -+ bool tx_pbl_fwd; -+ bool debug_mode; -+ bool wake_on_lan; -+ uint16_t max_frame_length; -+ uint16_t pause_quanta; -+ uint32_t tx_ipg_length; -+}; -+ -+ -+/** -+ * fman_memac_defconfig() - Get default MEMAC configuration -+ * @cfg: pointer to configuration structure. -+ * -+ * Call this function to obtain a default set of configuration values for -+ * initializing MEMAC. The user can overwrite any of the values before calling -+ * fman_memac_init(), if specific configuration needs to be applied. -+ */ -+void fman_memac_defconfig(struct memac_cfg *cfg); -+ -+int fman_memac_init(struct memac_regs *regs, -+ struct memac_cfg *cfg, -+ enum enet_interface enet_interface, -+ enum enet_speed enet_speed, -+ bool slow_10g_if, -+ uint32_t exceptions); -+ -+void fman_memac_enable(struct memac_regs *regs, bool apply_rx, bool apply_tx); -+ -+void fman_memac_disable(struct memac_regs *regs, bool apply_rx, bool apply_tx); -+ -+void fman_memac_set_promiscuous(struct memac_regs *regs, bool val); -+ -+void fman_memac_add_addr_in_paddr(struct memac_regs *regs, -+ uint8_t *adr, -+ uint8_t paddr_num); -+ -+void fman_memac_clear_addr_in_paddr(struct memac_regs *regs, -+ uint8_t paddr_num); -+ -+uint64_t fman_memac_get_counter(struct memac_regs *regs, -+ enum memac_counters reg_name); -+ -+void fman_memac_set_tx_pause_frames(struct memac_regs *regs, -+ uint8_t priority, uint16_t pauseTime, uint16_t threshTime); -+ -+uint16_t fman_memac_get_max_frame_len(struct memac_regs *regs); -+ -+void fman_memac_set_exception(struct memac_regs *regs, uint32_t val, -+ bool enable); -+ -+void fman_memac_reset_stat(struct memac_regs *regs); -+ -+void fman_memac_reset(struct memac_regs *regs); -+ -+void fman_memac_reset_filter_table(struct memac_regs *regs); -+ -+void fman_memac_set_hash_table_entry(struct memac_regs *regs, uint32_t crc); -+ -+void fman_memac_set_hash_table(struct memac_regs *regs, uint32_t val); -+ -+void fman_memac_set_rx_ignore_pause_frames(struct memac_regs *regs, -+ bool enable); -+ -+void fman_memac_set_wol(struct memac_regs *regs, bool enable); -+ -+uint32_t fman_memac_get_event(struct memac_regs *regs, uint32_t ev_mask); -+ -+void fman_memac_ack_event(struct memac_regs *regs, uint32_t ev_mask); -+ -+uint32_t fman_memac_get_interrupt_mask(struct memac_regs *regs); -+ -+void fman_memac_adjust_link(struct memac_regs *regs, -+ enum enet_interface iface_mode, -+ enum enet_speed speed, bool full_dx); -+ -+ -+ -+#endif /*__FSL_FMAN_MEMAC_H*/ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_memac_mii_acc.h -@@ -0,0 +1,78 @@ -+/* -+ * Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __FSL_FMAN_MEMAC_MII_ACC_H -+#define __FSL_FMAN_MEMAC_MII_ACC_H -+ -+#include "common/general.h" -+#include "fsl_enet.h" -+/* MII Management Registers */ -+#define MDIO_CFG_CLK_DIV_MASK 0x0080ff80 -+#define MDIO_CFG_CLK_DIV_SHIFT 7 -+#define MDIO_CFG_HOLD_MASK 0x0000001c -+#define MDIO_CFG_ENC45 0x00000040 -+#define MDIO_CFG_READ_ERR 0x00000002 -+#define MDIO_CFG_BSY 0x00000001 -+ -+#define MDIO_CTL_PHY_ADDR_SHIFT 5 -+#define MDIO_CTL_READ 0x00008000 -+ -+#define MDIO_DATA_BSY 0x80000000 -+ -+/*MEMAC Internal PHY Registers - SGMII */ -+#define PHY_SGMII_CR_PHY_RESET 0x8000 -+#define PHY_SGMII_CR_RESET_AN 0x0200 -+#define PHY_SGMII_CR_DEF_VAL 0x1140 -+#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001 -+#define PHY_SGMII_DEV_ABILITY_1000X 0x01A0 -+#define PHY_SGMII_IF_MODE_AN 0x0002 -+#define PHY_SGMII_IF_MODE_SGMII 0x0001 -+#define PHY_SGMII_IF_MODE_1000X 0x0000 -+ -+/*----------------------------------------------------*/ -+/* MII Configuration Control Memory Map Registers */ -+/*----------------------------------------------------*/ -+struct memac_mii_access_mem_map { -+ uint32_t mdio_cfg; /* 0x030 */ -+ uint32_t mdio_ctrl; /* 0x034 */ -+ uint32_t mdio_data; /* 0x038 */ -+ uint32_t mdio_addr; /* 0x03c */ -+}; -+ -+int fman_memac_mii_read_phy_reg(struct memac_mii_access_mem_map *mii_regs, -+ uint8_t phy_addr, uint8_t reg, uint16_t *data, -+ enum enet_speed enet_speed); -+int fman_memac_mii_write_phy_reg(struct memac_mii_access_mem_map *mii_regs, -+ uint8_t phy_addr, uint8_t reg, uint16_t data, -+ enum enet_speed enet_speed); -+ -+#endif /* __MAC_API_MEMAC_MII_ACC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_port.h -@@ -0,0 +1,593 @@ -+/* -+ * Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __FSL_FMAN_PORT_H -+#define __FSL_FMAN_PORT_H -+ -+#include "fsl_fman_sp.h" -+ -+/** @Collection Registers bit fields */ -+ -+/** @Description BMI defines */ -+#define BMI_EBD_EN 0x80000000 -+ -+#define BMI_PORT_CFG_EN 0x80000000 -+#define BMI_PORT_CFG_FDOVR 0x02000000 -+#define BMI_PORT_CFG_IM 0x01000000 -+ -+#define BMI_PORT_STATUS_BSY 0x80000000 -+ -+#define BMI_DMA_ATTR_SWP_SHIFT FMAN_SP_DMA_ATTR_SWP_SHIFT -+#define BMI_DMA_ATTR_IC_STASH_ON 0x10000000 -+#define BMI_DMA_ATTR_HDR_STASH_ON 0x04000000 -+#define BMI_DMA_ATTR_SG_STASH_ON 0x01000000 -+#define BMI_DMA_ATTR_WRITE_OPTIMIZE FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE -+ -+#define BMI_RX_FIFO_PRI_ELEVATION_SHIFT 16 -+#define BMI_RX_FIFO_THRESHOLD_ETHE 0x80000000 -+ -+#define BMI_TX_FRAME_END_CS_IGNORE_SHIFT 24 -+#define BMI_RX_FRAME_END_CS_IGNORE_SHIFT 24 -+#define BMI_RX_FRAME_END_CUT_SHIFT 16 -+ -+#define BMI_IC_TO_EXT_SHIFT FMAN_SP_IC_TO_EXT_SHIFT -+#define BMI_IC_FROM_INT_SHIFT FMAN_SP_IC_FROM_INT_SHIFT -+ -+#define BMI_INT_BUF_MARG_SHIFT 28 -+#define BMI_EXT_BUF_MARG_START_SHIFT FMAN_SP_EXT_BUF_MARG_START_SHIFT -+ -+#define BMI_CMD_MR_LEAC 0x00200000 -+#define BMI_CMD_MR_SLEAC 0x00100000 -+#define BMI_CMD_MR_MA 0x00080000 -+#define BMI_CMD_MR_DEAS 0x00040000 -+#define BMI_CMD_RX_MR_DEF (BMI_CMD_MR_LEAC | \ -+ BMI_CMD_MR_SLEAC | \ -+ BMI_CMD_MR_MA | \ -+ BMI_CMD_MR_DEAS) -+#define BMI_CMD_TX_MR_DEF 0 -+#define BMI_CMD_OP_MR_DEF (BMI_CMD_MR_DEAS | \ -+ BMI_CMD_MR_MA) -+ -+#define BMI_CMD_ATTR_ORDER 0x80000000 -+#define BMI_CMD_ATTR_SYNC 0x02000000 -+#define BMI_CMD_ATTR_COLOR_SHIFT 26 -+ -+#define BMI_FIFO_PIPELINE_DEPTH_SHIFT 12 -+#define BMI_NEXT_ENG_FD_BITS_SHIFT 24 -+#define BMI_FRAME_END_CS_IGNORE_SHIFT 24 -+ -+#define BMI_COUNTERS_EN 0x80000000 -+ -+#define BMI_EXT_BUF_POOL_VALID FMAN_SP_EXT_BUF_POOL_VALID -+#define BMI_EXT_BUF_POOL_EN_COUNTER FMAN_SP_EXT_BUF_POOL_EN_COUNTER -+#define BMI_EXT_BUF_POOL_BACKUP FMAN_SP_EXT_BUF_POOL_BACKUP -+#define BMI_EXT_BUF_POOL_ID_SHIFT 16 -+#define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000 -+#define BMI_POOL_DEP_NUM_OF_POOLS_SHIFT 16 -+ -+#define BMI_TX_FIFO_MIN_FILL_SHIFT 16 -+#define BMI_TX_FIFO_PIPELINE_DEPTH_SHIFT 12 -+ -+#define MAX_PERFORMANCE_TASK_COMP 64 -+#define MAX_PERFORMANCE_RX_QUEUE_COMP 64 -+#define MAX_PERFORMANCE_TX_QUEUE_COMP 8 -+#define MAX_PERFORMANCE_DMA_COMP 16 -+#define MAX_PERFORMANCE_FIFO_COMP 1024 -+ -+#define BMI_PERFORMANCE_TASK_COMP_SHIFT 24 -+#define BMI_PERFORMANCE_QUEUE_COMP_SHIFT 16 -+#define BMI_PERFORMANCE_DMA_COMP_SHIFT 12 -+ -+#define BMI_RATE_LIMIT_GRAN_TX 16000 /* In Kbps */ -+#define BMI_RATE_LIMIT_GRAN_OP 10000 /* In frames */ -+#define BMI_RATE_LIMIT_MAX_RATE_IN_GRAN_UNITS 1024 -+#define BMI_RATE_LIMIT_MAX_BURST_SIZE 1024 /* In KBytes */ -+#define BMI_RATE_LIMIT_MAX_BURST_SHIFT 16 -+#define BMI_RATE_LIMIT_HIGH_BURST_SIZE_GRAN 0x80000000 -+#define BMI_RATE_LIMIT_SCALE_TSBS_SHIFT 16 -+#define BMI_RATE_LIMIT_SCALE_EN 0x80000000 -+#define BMI_SG_DISABLE FMAN_SP_SG_DISABLE -+ -+/** @Description QMI defines */ -+#define QMI_PORT_CFG_EN 0x80000000 -+#define QMI_PORT_CFG_EN_COUNTERS 0x10000000 -+ -+#define QMI_PORT_STATUS_DEQ_TNUM_BSY 0x80000000 -+#define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000 -+ -+#define QMI_DEQ_CFG_PRI 0x80000000 -+#define QMI_DEQ_CFG_TYPE1 0x10000000 -+#define QMI_DEQ_CFG_TYPE2 0x20000000 -+#define QMI_DEQ_CFG_TYPE3 0x30000000 -+#define QMI_DEQ_CFG_PREFETCH_PARTIAL 0x01000000 -+#define QMI_DEQ_CFG_PREFETCH_FULL 0x03000000 -+#define QMI_DEQ_CFG_SP_MASK 0xf -+#define QMI_DEQ_CFG_SP_SHIFT 20 -+ -+ -+/** @Description General port defines */ -+#define FMAN_PORT_EXT_POOLS_NUM(fm_rev_maj) \ -+ (((fm_rev_maj) == 4) ? 4 : 8) -+#define FMAN_PORT_MAX_EXT_POOLS_NUM 8 -+#define FMAN_PORT_OBS_EXT_POOLS_NUM 2 -+#define FMAN_PORT_CG_MAP_NUM 8 -+#define FMAN_PORT_PRS_RESULT_WORDS_NUM 8 -+#define FMAN_PORT_BMI_FIFO_UNITS 0x100 -+#define FMAN_PORT_IC_OFFSET_UNITS 0x10 -+ -+ -+/** @Collection FM Port Register Map */ -+ -+/** @Description BMI Rx port register map */ -+struct fman_port_rx_bmi_regs { -+ uint32_t fmbm_rcfg; /**< Rx Configuration */ -+ uint32_t fmbm_rst; /**< Rx Status */ -+ uint32_t fmbm_rda; /**< Rx DMA attributes*/ -+ uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/ -+ uint32_t fmbm_rfed; /**< Rx Frame End Data*/ -+ uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/ -+ uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/ -+ uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/ -+ uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/ -+ uint32_t fmbm_rfca; /**< Rx Frame Command Attributes.*/ -+ uint32_t fmbm_rfpne; /**< Rx Frame Parser Next Engine*/ -+ uint32_t fmbm_rpso; /**< Rx Parse Start Offset*/ -+ uint32_t fmbm_rpp; /**< Rx Policer Profile */ -+ uint32_t fmbm_rccb; /**< Rx Coarse Classification Base */ -+ uint32_t fmbm_reth; /**< Rx Excessive Threshold */ -+ uint32_t reserved003c[1]; /**< (0x03C 0x03F) */ -+ uint32_t fmbm_rprai[FMAN_PORT_PRS_RESULT_WORDS_NUM]; -+ /**< Rx Parse Results Array Init*/ -+ uint32_t fmbm_rfqid; /**< Rx Frame Queue ID*/ -+ uint32_t fmbm_refqid; /**< Rx Error Frame Queue ID*/ -+ uint32_t fmbm_rfsdm; /**< Rx Frame Status Discard Mask*/ -+ uint32_t fmbm_rfsem; /**< Rx Frame Status Error Mask*/ -+ uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */ -+ uint32_t reserved0074[0x2]; /**< (0x074-0x07C) */ -+ uint32_t fmbm_rcmne; /**< Rx Frame Continuous Mode Next Engine */ -+ uint32_t reserved0080[0x20];/**< (0x080 0x0FF) */ -+ uint32_t fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM]; -+ /**< Buffer Manager pool Information-*/ -+ uint32_t fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM]; -+ /**< Allocate Counter-*/ -+ uint32_t reserved0130[8]; -+ /**< 0x130/0x140 - 0x15F reserved -*/ -+ uint32_t fmbm_rcgm[FMAN_PORT_CG_MAP_NUM]; -+ /**< Congestion Group Map*/ -+ uint32_t fmbm_mpd; /**< BM Pool Depletion */ -+ uint32_t reserved0184[0x1F]; /**< (0x184 0x1FF) */ -+ uint32_t fmbm_rstc; /**< Rx Statistics Counters*/ -+ uint32_t fmbm_rfrc; /**< Rx Frame Counter*/ -+ uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/ -+ uint32_t fmbm_rlfc; /**< Rx Large Frames Counter*/ -+ uint32_t fmbm_rffc; /**< Rx Filter Frames Counter*/ -+ uint32_t fmbm_rfdc; /**< Rx Frame Discard Counter*/ -+ uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/ -+ uint32_t fmbm_rodc; /**< Rx Out of Buffers Discard nntr*/ -+ uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter*/ -+ uint32_t reserved0224[0x17]; /**< (0x224 0x27F) */ -+ uint32_t fmbm_rpc; /**< Rx Performance Counters*/ -+ uint32_t fmbm_rpcp; /**< Rx Performance Count Parameters*/ -+ uint32_t fmbm_rccn; /**< Rx Cycle Counter*/ -+ uint32_t fmbm_rtuc; /**< Rx Tasks Utilization Counter*/ -+ uint32_t fmbm_rrquc; /**< Rx Receive Queue Utilization cntr*/ -+ uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/ -+ uint32_t fmbm_rfuc; /**< Rx FIFO Utilization Counter*/ -+ uint32_t fmbm_rpac; /**< Rx Pause Activation Counter*/ -+ uint32_t reserved02a0[0x18]; /**< (0x2A0 0x2FF) */ -+ uint32_t fmbm_rdbg; /**< Rx Debug-*/ -+}; -+ -+/** @Description BMI Tx port register map */ -+struct fman_port_tx_bmi_regs { -+ uint32_t fmbm_tcfg; /**< Tx Configuration */ -+ uint32_t fmbm_tst; /**< Tx Status */ -+ uint32_t fmbm_tda; /**< Tx DMA attributes */ -+ uint32_t fmbm_tfp; /**< Tx FIFO Parameters */ -+ uint32_t fmbm_tfed; /**< Tx Frame End Data */ -+ uint32_t fmbm_ticp; /**< Tx Internal Context Parameters */ -+ uint32_t fmbm_tfdne; /**< Tx Frame Dequeue Next Engine. */ -+ uint32_t fmbm_tfca; /**< Tx Frame Command attribute. */ -+ uint32_t fmbm_tcfqid; /**< Tx Confirmation Frame Queue ID. */ -+ uint32_t fmbm_tefqid; /**< Tx Frame Error Queue ID */ -+ uint32_t fmbm_tfene; /**< Tx Frame Enqueue Next Engine */ -+ uint32_t fmbm_trlmts; /**< Tx Rate Limiter Scale */ -+ uint32_t fmbm_trlmt; /**< Tx Rate Limiter */ -+ uint32_t reserved0034[0x0e]; /**< (0x034-0x6c) */ -+ uint32_t fmbm_tccb; /**< Tx Coarse Classification base */ -+ uint32_t fmbm_tfne; /**< Tx Frame Next Engine */ -+ uint32_t fmbm_tpfcm[0x02]; /**< Tx Priority based Flow Control (PFC) Mapping */ -+ uint32_t fmbm_tcmne; /**< Tx Frame Continuous Mode Next Engine */ -+ uint32_t reserved0080[0x60]; /**< (0x080-0x200) */ -+ uint32_t fmbm_tstc; /**< Tx Statistics Counters */ -+ uint32_t fmbm_tfrc; /**< Tx Frame Counter */ -+ uint32_t fmbm_tfdc; /**< Tx Frames Discard Counter */ -+ uint32_t fmbm_tfledc; /**< Tx Frame len error discard cntr */ -+ uint32_t fmbm_tfufdc; /**< Tx Frame unsprt frmt discard cntr*/ -+ uint32_t fmbm_tbdc; /**< Tx Buffers Deallocate Counter */ -+ uint32_t reserved0218[0x1A]; /**< (0x218-0x280) */ -+ uint32_t fmbm_tpc; /**< Tx Performance Counters*/ -+ uint32_t fmbm_tpcp; /**< Tx Performance Count Parameters*/ -+ uint32_t fmbm_tccn; /**< Tx Cycle Counter*/ -+ uint32_t fmbm_ttuc; /**< Tx Tasks Utilization Counter*/ -+ uint32_t fmbm_ttcquc; /**< Tx Transmit conf Q util Counter*/ -+ uint32_t fmbm_tduc; /**< Tx DMA Utilization Counter*/ -+ uint32_t fmbm_tfuc; /**< Tx FIFO Utilization Counter*/ -+}; -+ -+/** @Description BMI O/H port register map */ -+struct fman_port_oh_bmi_regs { -+ uint32_t fmbm_ocfg; /**< O/H Configuration */ -+ uint32_t fmbm_ost; /**< O/H Status */ -+ uint32_t fmbm_oda; /**< O/H DMA attributes */ -+ uint32_t fmbm_oicp; /**< O/H Internal Context Parameters */ -+ uint32_t fmbm_ofdne; /**< O/H Frame Dequeue Next Engine */ -+ uint32_t fmbm_ofne; /**< O/H Frame Next Engine */ -+ uint32_t fmbm_ofca; /**< O/H Frame Command Attributes. */ -+ uint32_t fmbm_ofpne; /**< O/H Frame Parser Next Engine */ -+ uint32_t fmbm_opso; /**< O/H Parse Start Offset */ -+ uint32_t fmbm_opp; /**< O/H Policer Profile */ -+ uint32_t fmbm_occb; /**< O/H Coarse Classification base */ -+ uint32_t fmbm_oim; /**< O/H Internal margins*/ -+ uint32_t fmbm_ofp; /**< O/H Fifo Parameters*/ -+ uint32_t fmbm_ofed; /**< O/H Frame End Data*/ -+ uint32_t reserved0030[2]; /**< (0x038 - 0x03F) */ -+ uint32_t fmbm_oprai[FMAN_PORT_PRS_RESULT_WORDS_NUM]; -+ /**< O/H Parse Results Array Initialization */ -+ uint32_t fmbm_ofqid; /**< O/H Frame Queue ID */ -+ uint32_t fmbm_oefqid; /**< O/H Error Frame Queue ID */ -+ uint32_t fmbm_ofsdm; /**< O/H Frame Status Discard Mask */ -+ uint32_t fmbm_ofsem; /**< O/H Frame Status Error Mask */ -+ uint32_t fmbm_ofene; /**< O/H Frame Enqueue Next Engine */ -+ uint32_t fmbm_orlmts; /**< O/H Rate Limiter Scale */ -+ uint32_t fmbm_orlmt; /**< O/H Rate Limiter */ -+ uint32_t fmbm_ocmne; /**< O/H Continuous Mode Next Engine */ -+ uint32_t reserved0080[0x20]; /**< 0x080 - 0x0FF Reserved */ -+ uint32_t fmbm_oebmpi[2]; /**< Buf Mngr Observed Pool Info */ -+ uint32_t reserved0108[0x16]; /**< 0x108 - 0x15F Reserved */ -+ uint32_t fmbm_ocgm[FMAN_PORT_CG_MAP_NUM]; /**< Observed Congestion Group Map */ -+ uint32_t fmbm_ompd; /**< Observed BMan Pool Depletion */ -+ uint32_t reserved0184[0x1F]; /**< 0x184 - 0x1FF Reserved */ -+ uint32_t fmbm_ostc; /**< O/H Statistics Counters */ -+ uint32_t fmbm_ofrc; /**< O/H Frame Counter */ -+ uint32_t fmbm_ofdc; /**< O/H Frames Discard Counter */ -+ uint32_t fmbm_ofledc; /**< O/H Frames Len Err Discard Cntr */ -+ uint32_t fmbm_ofufdc; /**< O/H Frames Unsprtd Discard Cutr */ -+ uint32_t fmbm_offc; /**< O/H Filter Frames Counter */ -+ uint32_t fmbm_ofwdc; /**< Rx Frames WRED Discard Counter */ -+ uint32_t fmbm_ofldec; /**< O/H Frames List DMA Error Cntr */ -+ uint32_t fmbm_obdc; /**< O/H Buffers Deallocate Counter */ -+ uint32_t reserved0218[0x17]; /**< (0x218 - 0x27F) */ -+ uint32_t fmbm_opc; /**< O/H Performance Counters */ -+ uint32_t fmbm_opcp; /**< O/H Performance Count Parameters */ -+ uint32_t fmbm_occn; /**< O/H Cycle Counter */ -+ uint32_t fmbm_otuc; /**< O/H Tasks Utilization Counter */ -+ uint32_t fmbm_oduc; /**< O/H DMA Utilization Counter */ -+ uint32_t fmbm_ofuc; /**< O/H FIFO Utilization Counter */ -+}; -+ -+/** @Description BMI port register map */ -+union fman_port_bmi_regs { -+ struct fman_port_rx_bmi_regs rx; -+ struct fman_port_tx_bmi_regs tx; -+ struct fman_port_oh_bmi_regs oh; -+}; -+ -+/** @Description QMI port register map */ -+struct fman_port_qmi_regs { -+ uint32_t fmqm_pnc; /**< PortID n Configuration Register */ -+ uint32_t fmqm_pns; /**< PortID n Status Register */ -+ uint32_t fmqm_pnts; /**< PortID n Task Status Register */ -+ uint32_t reserved00c[4]; /**< 0xn00C - 0xn01B */ -+ uint32_t fmqm_pnen; /**< PortID n Enqueue NIA Register */ -+ uint32_t fmqm_pnetfc; /**< PortID n Enq Total Frame Counter */ -+ uint32_t reserved024[2]; /**< 0xn024 - 0x02B */ -+ uint32_t fmqm_pndn; /**< PortID n Dequeue NIA Register */ -+ uint32_t fmqm_pndc; /**< PortID n Dequeue Config Register */ -+ uint32_t fmqm_pndtfc; /**< PortID n Dequeue tot Frame cntr */ -+ uint32_t fmqm_pndfdc; /**< PortID n Dequeue FQID Dflt Cntr */ -+ uint32_t fmqm_pndcc; /**< PortID n Dequeue Confirm Counter */ -+}; -+ -+ -+enum fman_port_dma_swap { -+ E_FMAN_PORT_DMA_NO_SWAP, /**< No swap, transfer data as is */ -+ E_FMAN_PORT_DMA_SWAP_LE, -+ /**< The transferred data should be swapped in PPC Little Endian mode */ -+ E_FMAN_PORT_DMA_SWAP_BE -+ /**< The transferred data should be swapped in Big Endian mode */ -+}; -+ -+/* Default port color */ -+enum fman_port_color { -+ E_FMAN_PORT_COLOR_GREEN, /**< Default port color is green */ -+ E_FMAN_PORT_COLOR_YELLOW, /**< Default port color is yellow */ -+ E_FMAN_PORT_COLOR_RED, /**< Default port color is red */ -+ E_FMAN_PORT_COLOR_OVERRIDE /**< Ignore color */ -+}; -+ -+/* QMI dequeue from the SP channel - types */ -+enum fman_port_deq_type { -+ E_FMAN_PORT_DEQ_BY_PRI, -+ /**< Priority precedence and Intra-Class scheduling */ -+ E_FMAN_PORT_DEQ_ACTIVE_FQ, -+ /**< Active FQ precedence and Intra-Class scheduling */ -+ E_FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS -+ /**< Active FQ precedence and override Intra-Class scheduling */ -+}; -+ -+/* QMI dequeue prefetch modes */ -+enum fman_port_deq_prefetch { -+ E_FMAN_PORT_DEQ_NO_PREFETCH, /**< No prefetch mode */ -+ E_FMAN_PORT_DEQ_PART_PREFETCH, /**< Partial prefetch mode */ -+ E_FMAN_PORT_DEQ_FULL_PREFETCH /**< Full prefetch mode */ -+}; -+ -+/* Parameters for defining performance counters behavior */ -+struct fman_port_perf_cnt_params { -+ uint8_t task_val; /**< Task compare value */ -+ uint8_t queue_val; -+ /**< Rx or Tx conf queue compare value (unused for O/H ports) */ -+ uint8_t dma_val; /**< Dma compare value */ -+ uint32_t fifo_val; /**< Fifo compare value (in bytes) */ -+}; -+ -+/** @Description FM Port configuration structure, used at init */ -+struct fman_port_cfg { -+ struct fman_port_perf_cnt_params perf_cnt_params; -+ /* BMI parameters */ -+ enum fman_port_dma_swap dma_swap_data; -+ bool dma_ic_stash_on; -+ bool dma_header_stash_on; -+ bool dma_sg_stash_on; -+ bool dma_write_optimize; -+ uint16_t ic_ext_offset; -+ uint8_t ic_int_offset; -+ uint16_t ic_size; -+ enum fman_port_color color; -+ bool sync_req; -+ bool discard_override; -+ uint8_t checksum_bytes_ignore; -+ uint8_t rx_cut_end_bytes; -+ uint32_t rx_pri_elevation; -+ uint32_t rx_fifo_thr; -+ uint8_t rx_fd_bits; -+ uint8_t int_buf_start_margin; -+ uint16_t ext_buf_start_margin; -+ uint16_t ext_buf_end_margin; -+ uint32_t tx_fifo_min_level; -+ uint32_t tx_fifo_low_comf_level; -+ uint8_t tx_fifo_deq_pipeline_depth; -+ bool stats_counters_enable; -+ bool perf_counters_enable; -+ /* QMI parameters */ -+ bool deq_high_pri; -+ enum fman_port_deq_type deq_type; -+ enum fman_port_deq_prefetch deq_prefetch_opt; -+ uint16_t deq_byte_cnt; -+ bool queue_counters_enable; -+ bool no_scatter_gather; -+ int errata_A006675; -+ int errata_A006320; -+ int excessive_threshold_register; -+ int fmbm_rebm_has_sgd; -+ int fmbm_tfne_has_features; -+ int qmi_deq_options_support; -+}; -+ -+enum fman_port_type { -+ E_FMAN_PORT_TYPE_OP = 0, -+ /**< Offline parsing port, shares id-s with -+ * host command, so must have exclusive id-s */ -+ E_FMAN_PORT_TYPE_RX, /**< 1G Rx port */ -+ E_FMAN_PORT_TYPE_RX_10G, /**< 10G Rx port */ -+ E_FMAN_PORT_TYPE_TX, /**< 1G Tx port */ -+ E_FMAN_PORT_TYPE_TX_10G, /**< 10G Tx port */ -+ E_FMAN_PORT_TYPE_DUMMY, -+ E_FMAN_PORT_TYPE_HC = E_FMAN_PORT_TYPE_DUMMY -+ /**< Host command port, shares id-s with -+ * offline parsing ports, so must have exclusive id-s */ -+}; -+ -+struct fman_port_params { -+ uint32_t discard_mask; -+ uint32_t err_mask; -+ uint32_t dflt_fqid; -+ uint32_t err_fqid; -+ uint8_t deq_sp; -+ bool dont_release_buf; -+}; -+ -+/* Port context - used by most API functions */ -+struct fman_port { -+ enum fman_port_type type; -+ uint8_t fm_rev_maj; -+ uint8_t fm_rev_min; -+ union fman_port_bmi_regs *bmi_regs; -+ struct fman_port_qmi_regs *qmi_regs; -+ bool im_en; -+ uint8_t ext_pools_num; -+}; -+ -+/** @Description External buffer pools configuration */ -+struct fman_port_bpools { -+ uint8_t count; /**< Num of pools to set up */ -+ bool counters_enable; /**< Enable allocate counters */ -+ uint8_t grp_bp_depleted_num; -+ /**< Number of depleted pools - if reached the BMI indicates -+ * the MAC to send a pause frame */ -+ struct { -+ uint8_t bpid; /**< BM pool ID */ -+ uint16_t size; -+ /**< Pool's size - must be in ascending order */ -+ bool is_backup; -+ /**< If this is a backup pool */ -+ bool grp_bp_depleted; -+ /**< Consider this buffer in multiple pools depletion criteria*/ -+ bool single_bp_depleted; -+ /**< Consider this buffer in single pool depletion criteria */ -+ bool pfc_priorities_en; -+ } bpool[FMAN_PORT_MAX_EXT_POOLS_NUM]; -+}; -+ -+enum fman_port_rate_limiter_scale_down { -+ E_FMAN_PORT_RATE_DOWN_NONE, -+ E_FMAN_PORT_RATE_DOWN_BY_2, -+ E_FMAN_PORT_RATE_DOWN_BY_4, -+ E_FMAN_PORT_RATE_DOWN_BY_8 -+}; -+ -+/* Rate limiter configuration */ -+struct fman_port_rate_limiter { -+ uint8_t count_1micro_bit; -+ bool high_burst_size_gran; -+ /**< Defines burst_size granularity for OP ports; when TRUE, -+ * burst_size below counts in frames, otherwise in 10^3 frames */ -+ uint16_t burst_size; -+ /**< Max burst size, in KBytes for Tx port, according to -+ * high_burst_size_gran definition for OP port */ -+ uint32_t rate; -+ /**< In Kbps for Tx port, in frames/sec for OP port */ -+ enum fman_port_rate_limiter_scale_down rate_factor; -+}; -+ -+/* BMI statistics counters */ -+enum fman_port_stats_counters { -+ E_FMAN_PORT_STATS_CNT_FRAME, -+ /**< Number of processed frames; valid for all ports */ -+ E_FMAN_PORT_STATS_CNT_DISCARD, -+ /**< For Rx ports - frames discarded by QMAN, for Tx or O/H ports - -+ * frames discarded due to DMA error; valid for all ports */ -+ E_FMAN_PORT_STATS_CNT_DEALLOC_BUF, -+ /**< Number of buffer deallocate operations; valid for all ports */ -+ E_FMAN_PORT_STATS_CNT_RX_BAD_FRAME, -+ /**< Number of bad Rx frames, like CRC error, Rx FIFO overflow etc; -+ * valid for Rx ports only */ -+ E_FMAN_PORT_STATS_CNT_RX_LARGE_FRAME, -+ /**< Number of Rx oversized frames, that is frames exceeding max frame -+ * size configured for the corresponding ETH controller; -+ * valid for Rx ports only */ -+ E_FMAN_PORT_STATS_CNT_RX_OUT_OF_BUF, -+ /**< Frames discarded due to lack of external buffers; valid for -+ * Rx ports only */ -+ E_FMAN_PORT_STATS_CNT_LEN_ERR, -+ /**< Frames discarded due to frame length error; valid for Tx and -+ * O/H ports only */ -+ E_FMAN_PORT_STATS_CNT_UNSUPPORTED_FORMAT, -+ /**< Frames discarded due to unsupported FD format; valid for Tx -+ * and O/H ports only */ -+ E_FMAN_PORT_STATS_CNT_FILTERED_FRAME, -+ /**< Number of frames filtered out by PCD module; valid for -+ * Rx and OP ports only */ -+ E_FMAN_PORT_STATS_CNT_DMA_ERR, -+ /**< Frames rejected by QMAN that were not able to release their -+ * buffers due to DMA error; valid for Rx and O/H ports only */ -+ E_FMAN_PORT_STATS_CNT_WRED_DISCARD -+ /**< Frames going through O/H port that were not able to to enter the -+ * return queue due to WRED algorithm; valid for O/H ports only */ -+}; -+ -+/* BMI performance counters */ -+enum fman_port_perf_counters { -+ E_FMAN_PORT_PERF_CNT_CYCLE, /**< Cycle counter */ -+ E_FMAN_PORT_PERF_CNT_TASK_UTIL, /**< Tasks utilization counter */ -+ E_FMAN_PORT_PERF_CNT_QUEUE_UTIL, -+ /**< For Rx ports - Rx queue utilization, for Tx ports - Tx conf queue -+ * utilization; not valid for O/H ports */ -+ E_FMAN_PORT_PERF_CNT_DMA_UTIL, /**< DMA utilization counter */ -+ E_FMAN_PORT_PERF_CNT_FIFO_UTIL, /**< FIFO utilization counter */ -+ E_FMAN_PORT_PERF_CNT_RX_PAUSE -+ /**< Number of cycles in which Rx pause activation control is on; -+ * valid for Rx ports only */ -+}; -+ -+/* QMI counters */ -+enum fman_port_qmi_counters { -+ E_FMAN_PORT_ENQ_TOTAL, /**< EnQ tot frame cntr */ -+ E_FMAN_PORT_DEQ_TOTAL, /**< DeQ tot frame cntr; invalid for Rx ports */ -+ E_FMAN_PORT_DEQ_FROM_DFLT, -+ /**< Dequeue from default FQID counter not valid for Rx ports */ -+ E_FMAN_PORT_DEQ_CONFIRM /**< DeQ confirm cntr invalid for Rx ports */ -+}; -+ -+ -+/** @Collection FM Port API */ -+void fman_port_defconfig(struct fman_port_cfg *cfg, enum fman_port_type type); -+int fman_port_init(struct fman_port *port, -+ struct fman_port_cfg *cfg, -+ struct fman_port_params *params); -+int fman_port_enable(struct fman_port *port); -+int fman_port_disable(const struct fman_port *port); -+int fman_port_set_bpools(const struct fman_port *port, -+ const struct fman_port_bpools *bp); -+int fman_port_set_rate_limiter(struct fman_port *port, -+ struct fman_port_rate_limiter *rate_limiter); -+int fman_port_delete_rate_limiter(struct fman_port *port); -+int fman_port_set_err_mask(struct fman_port *port, uint32_t err_mask); -+int fman_port_set_discard_mask(struct fman_port *port, uint32_t discard_mask); -+int fman_port_modify_rx_fd_bits(struct fman_port *port, -+ uint8_t rx_fd_bits, -+ bool add); -+int fman_port_set_perf_cnt_params(struct fman_port *port, -+ struct fman_port_perf_cnt_params *params); -+int fman_port_set_stats_cnt_mode(struct fman_port *port, bool enable); -+int fman_port_set_perf_cnt_mode(struct fman_port *port, bool enable); -+int fman_port_set_queue_cnt_mode(struct fman_port *port, bool enable); -+int fman_port_set_bpool_cnt_mode(struct fman_port *port, -+ uint8_t bpid, -+ bool enable); -+uint32_t fman_port_get_stats_counter(struct fman_port *port, -+ enum fman_port_stats_counters counter); -+void fman_port_set_stats_counter(struct fman_port *port, -+ enum fman_port_stats_counters counter, -+ uint32_t value); -+uint32_t fman_port_get_perf_counter(struct fman_port *port, -+ enum fman_port_perf_counters counter); -+void fman_port_set_perf_counter(struct fman_port *port, -+ enum fman_port_perf_counters counter, -+ uint32_t value); -+uint32_t fman_port_get_qmi_counter(struct fman_port *port, -+ enum fman_port_qmi_counters counter); -+void fman_port_set_qmi_counter(struct fman_port *port, -+ enum fman_port_qmi_counters counter, -+ uint32_t value); -+uint32_t fman_port_get_bpool_counter(struct fman_port *port, uint8_t bpid); -+void fman_port_set_bpool_counter(struct fman_port *port, -+ uint8_t bpid, -+ uint32_t value); -+int fman_port_add_congestion_grps(struct fman_port *port, -+ uint32_t grps_map[FMAN_PORT_CG_MAP_NUM]); -+int fman_port_remove_congestion_grps(struct fman_port *port, -+ uint32_t grps_map[FMAN_PORT_CG_MAP_NUM]); -+ -+ -+#endif /* __FSL_FMAN_PORT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_prs.h -@@ -0,0 +1,102 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __FSL_FMAN_PRS_H -+#define __FSL_FMAN_PRS_H -+ -+#include "common/general.h" -+ -+#define FM_PCD_EX_PRS_DOUBLE_ECC 0x02000000 -+#define FM_PCD_EX_PRS_SINGLE_ECC 0x01000000 -+ -+#define FM_PCD_PRS_PPSC_ALL_PORTS 0xffff0000 -+#define FM_PCD_PRS_RPIMAC_EN 0x00000001 -+#define FM_PCD_PRS_PORT_IDLE_STS 0xffff0000 -+#define FM_PCD_PRS_SINGLE_ECC 0x00004000 -+#define FM_PCD_PRS_DOUBLE_ECC 0x00004000 -+#define PRS_MAX_CYCLE_LIMIT 8191 -+ -+#define DEFAULT_MAX_PRS_CYC_LIM 0 -+ -+struct fman_prs_regs { -+ uint32_t fmpr_rpclim; -+ uint32_t fmpr_rpimac; -+ uint32_t pmeec; -+ uint32_t res00c[5]; -+ uint32_t fmpr_pevr; -+ uint32_t fmpr_pever; -+ uint32_t res028; -+ uint32_t fmpr_perr; -+ uint32_t fmpr_perer; -+ uint32_t res034; -+ uint32_t res038[10]; -+ uint32_t fmpr_ppsc; -+ uint32_t res064; -+ uint32_t fmpr_pds; -+ uint32_t fmpr_l2rrs; -+ uint32_t fmpr_l3rrs; -+ uint32_t fmpr_l4rrs; -+ uint32_t fmpr_srrs; -+ uint32_t fmpr_l2rres; -+ uint32_t fmpr_l3rres; -+ uint32_t fmpr_l4rres; -+ uint32_t fmpr_srres; -+ uint32_t fmpr_spcs; -+ uint32_t fmpr_spscs; -+ uint32_t fmpr_hxscs; -+ uint32_t fmpr_mrcs; -+ uint32_t fmpr_mwcs; -+ uint32_t fmpr_mrscs; -+ uint32_t fmpr_mwscs; -+ uint32_t fmpr_fcscs; -+}; -+ -+struct fman_prs_cfg { -+ uint32_t port_id_stat; -+ uint16_t max_prs_cyc_lim; -+ uint32_t prs_exceptions; -+}; -+ -+uint32_t fman_prs_get_err_event(struct fman_prs_regs *regs, uint32_t ev_mask); -+uint32_t fman_prs_get_err_ev_mask(struct fman_prs_regs *regs); -+void fman_prs_ack_err_event(struct fman_prs_regs *regs, uint32_t event); -+uint32_t fman_prs_get_expt_event(struct fman_prs_regs *regs, uint32_t ev_mask); -+uint32_t fman_prs_get_expt_ev_mask(struct fman_prs_regs *regs); -+void fman_prs_ack_expt_event(struct fman_prs_regs *regs, uint32_t event); -+void fman_prs_defconfig(struct fman_prs_cfg *cfg); -+int fman_prs_init(struct fman_prs_regs *regs, struct fman_prs_cfg *cfg); -+void fman_prs_enable(struct fman_prs_regs *regs); -+void fman_prs_disable(struct fman_prs_regs *regs); -+int fman_prs_is_enabled(struct fman_prs_regs *regs); -+void fman_prs_set_stst_port_msk(struct fman_prs_regs *regs, uint32_t pid_msk); -+void fman_prs_set_stst(struct fman_prs_regs *regs, bool enable); -+#endif /* __FSL_FMAN_PRS_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_rtc.h -@@ -0,0 +1,449 @@ -+/* -+ * Copyright 2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __FSL_FMAN_RTC_H -+#define __FSL_FMAN_RTC_H -+ -+#include "common/general.h" -+ -+/* FM RTC Registers definitions */ -+#define FMAN_RTC_TMR_CTRL_ALMP1 0x80000000 -+#define FMAN_RTC_TMR_CTRL_ALMP2 0x40000000 -+#define FMAN_RTC_TMR_CTRL_FS 0x10000000 -+#define FMAN_RTC_TMR_CTRL_PP1L 0x08000000 -+#define FMAN_RTC_TMR_CTRL_PP2L 0x04000000 -+#define FMAN_RTC_TMR_CTRL_TCLK_PERIOD_MASK 0x03FF0000 -+#define FMAN_RTC_TMR_CTRL_FRD 0x00004000 -+#define FMAN_RTC_TMR_CTRL_SLV 0x00002000 -+#define FMAN_RTC_TMR_CTRL_ETEP1 0x00000100 -+#define FMAN_RTC_TMR_CTRL_COPH 0x00000080 -+#define FMAN_RTC_TMR_CTRL_CIPH 0x00000040 -+#define FMAN_RTC_TMR_CTRL_TMSR 0x00000020 -+#define FMAN_RTC_TMR_CTRL_DBG 0x00000010 -+#define FMAN_RTC_TMR_CTRL_BYP 0x00000008 -+#define FMAN_RTC_TMR_CTRL_TE 0x00000004 -+#define FMAN_RTC_TMR_CTRL_CKSEL_OSC_CLK 0x00000003 -+#define FMAN_RTC_TMR_CTRL_CKSEL_MAC_CLK 0x00000001 -+#define FMAN_RTC_TMR_CTRL_CKSEL_EXT_CLK 0x00000000 -+#define FMAN_RTC_TMR_CTRL_TCLK_PERIOD_SHIFT 16 -+ -+#define FMAN_RTC_TMR_TEVENT_ETS2 0x02000000 -+#define FMAN_RTC_TMR_TEVENT_ETS1 0x01000000 -+#define FMAN_RTC_TMR_TEVENT_ALM2 0x00020000 -+#define FMAN_RTC_TMR_TEVENT_ALM1 0x00010000 -+#define FMAN_RTC_TMR_TEVENT_PP1 0x00000080 -+#define FMAN_RTC_TMR_TEVENT_PP2 0x00000040 -+#define FMAN_RTC_TMR_TEVENT_PP3 0x00000020 -+#define FMAN_RTC_TMR_TEVENT_ALL (FMAN_RTC_TMR_TEVENT_ETS2 |\ -+ FMAN_RTC_TMR_TEVENT_ETS1 |\ -+ FMAN_RTC_TMR_TEVENT_ALM2 |\ -+ FMAN_RTC_TMR_TEVENT_ALM1 |\ -+ FMAN_RTC_TMR_TEVENT_PP1 |\ -+ FMAN_RTC_TMR_TEVENT_PP2 |\ -+ FMAN_RTC_TMR_TEVENT_PP3) -+ -+#define FMAN_RTC_TMR_PRSC_OCK_MASK 0x0000FFFF -+ -+/**************************************************************************//** -+ @Description FM RTC Alarm Polarity Options. -+*//***************************************************************************/ -+enum fman_rtc_alarm_polarity { -+ E_FMAN_RTC_ALARM_POLARITY_ACTIVE_HIGH, /**< Active-high output polarity */ -+ E_FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW /**< Active-low output polarity */ -+}; -+ -+/**************************************************************************//** -+ @Description FM RTC Trigger Polarity Options. -+*//***************************************************************************/ -+enum fman_rtc_trigger_polarity { -+ E_FMAN_RTC_TRIGGER_ON_RISING_EDGE, /**< Trigger on rising edge */ -+ E_FMAN_RTC_TRIGGER_ON_FALLING_EDGE /**< Trigger on falling edge */ -+}; -+ -+/**************************************************************************//** -+ @Description IEEE1588 Timer Module FM RTC Optional Clock Sources. -+*//***************************************************************************/ -+enum fman_src_clock { -+ E_FMAN_RTC_SOURCE_CLOCK_EXTERNAL, /**< external high precision timer -+ reference clock */ -+ E_FMAN_RTC_SOURCE_CLOCK_SYSTEM, /**< MAC system clock */ -+ E_FMAN_RTC_SOURCE_CLOCK_OSCILATOR /**< RTC clock oscilator */ -+}; -+ -+/* RTC default values */ -+#define DEFAULT_SRC_CLOCK E_FMAN_RTC_SOURCE_CLOCK_SYSTEM -+#define DEFAULT_INVERT_INPUT_CLK_PHASE FALSE -+#define DEFAULT_INVERT_OUTPUT_CLK_PHASE FALSE -+#define DEFAULT_ALARM_POLARITY E_FMAN_RTC_ALARM_POLARITY_ACTIVE_HIGH -+#define DEFAULT_TRIGGER_POLARITY E_FMAN_RTC_TRIGGER_ON_FALLING_EDGE -+#define DEFAULT_PULSE_REALIGN FALSE -+ -+#define FMAN_RTC_MAX_NUM_OF_ALARMS 3 -+#define FMAN_RTC_MAX_NUM_OF_PERIODIC_PULSES 4 -+#define FMAN_RTC_MAX_NUM_OF_EXT_TRIGGERS 3 -+ -+/**************************************************************************//** -+ @Description FM RTC timer alarm -+*//***************************************************************************/ -+struct t_tmr_alarm{ -+ uint32_t tmr_alarm_h; /**< */ -+ uint32_t tmr_alarm_l; /**< */ -+}; -+ -+/**************************************************************************//** -+ @Description FM RTC timer Ex trigger -+*//***************************************************************************/ -+struct t_tmr_ext_trigger{ -+ uint32_t tmr_etts_h; /**< */ -+ uint32_t tmr_etts_l; /**< */ -+}; -+ -+struct rtc_regs { -+ uint32_t tmr_id; /* 0x000 Module ID register */ -+ uint32_t tmr_id2; /* 0x004 Controller ID register */ -+ uint32_t reserved0008[30]; -+ uint32_t tmr_ctrl; /* 0x0080 timer control register */ -+ uint32_t tmr_tevent; /* 0x0084 timer event register */ -+ uint32_t tmr_temask; /* 0x0088 timer event mask register */ -+ uint32_t reserved008c[3]; -+ uint32_t tmr_cnt_h; /* 0x0098 timer counter high register */ -+ uint32_t tmr_cnt_l; /* 0x009c timer counter low register */ -+ uint32_t tmr_add; /* 0x00a0 timer drift compensation addend register */ -+ uint32_t tmr_acc; /* 0x00a4 timer accumulator register */ -+ uint32_t tmr_prsc; /* 0x00a8 timer prescale */ -+ uint32_t reserved00ac; -+ uint32_t tmr_off_h; /* 0x00b0 timer offset high */ -+ uint32_t tmr_off_l; /* 0x00b4 timer offset low */ -+ struct t_tmr_alarm tmr_alarm[FMAN_RTC_MAX_NUM_OF_ALARMS]; /* 0x00b8 timer -+ alarm */ -+ uint32_t tmr_fiper[FMAN_RTC_MAX_NUM_OF_PERIODIC_PULSES]; /* 0x00d0 timer -+ fixed period interval */ -+ struct t_tmr_ext_trigger tmr_etts[FMAN_RTC_MAX_NUM_OF_EXT_TRIGGERS]; -+ /* 0x00e0 time stamp general purpose external */ -+ uint32_t reserved00f0[4]; -+}; -+ -+struct rtc_cfg { -+ enum fman_src_clock src_clk; -+ uint32_t ext_src_clk_freq; -+ uint32_t rtc_freq_hz; -+ bool timer_slave_mode; -+ bool invert_input_clk_phase; -+ bool invert_output_clk_phase; -+ uint32_t events_mask; -+ bool bypass; /**< Indicates if frequency compensation -+ is bypassed */ -+ bool pulse_realign; -+ enum fman_rtc_alarm_polarity alarm_polarity[FMAN_RTC_MAX_NUM_OF_ALARMS]; -+ enum fman_rtc_trigger_polarity trigger_polarity -+ [FMAN_RTC_MAX_NUM_OF_EXT_TRIGGERS]; -+}; -+ -+/** -+ * fman_rtc_defconfig() - Get default RTC configuration -+ * @cfg: pointer to configuration structure. -+ * -+ * Call this function to obtain a default set of configuration values for -+ * initializing RTC. The user can overwrite any of the values before calling -+ * fman_rtc_init(), if specific configuration needs to be applied. -+ */ -+void fman_rtc_defconfig(struct rtc_cfg *cfg); -+ -+/** -+ * fman_rtc_get_events() - Get the events -+ * @regs: Pointer to RTC register block -+ * -+ * Returns: The events -+ */ -+uint32_t fman_rtc_get_events(struct rtc_regs *regs); -+ -+/** -+ * fman_rtc_get_interrupt_mask() - Get the events mask -+ * @regs: Pointer to RTC register block -+ * -+ * Returns: The events mask -+ */ -+uint32_t fman_rtc_get_interrupt_mask(struct rtc_regs *regs); -+ -+ -+/** -+ * fman_rtc_set_interrupt_mask() - Set the events mask -+ * @regs: Pointer to RTC register block -+ * @mask: The mask to set -+ */ -+void fman_rtc_set_interrupt_mask(struct rtc_regs *regs, uint32_t mask); -+ -+/** -+ * fman_rtc_get_event() - Check if specific events occurred -+ * @regs: Pointer to RTC register block -+ * @ev_mask: a mask of the events to check -+ * -+ * Returns: 0 if the events did not occur. Non zero if one of the events occurred -+ */ -+uint32_t fman_rtc_get_event(struct rtc_regs *regs, uint32_t ev_mask); -+ -+/** -+ * fman_rtc_check_and_clear_event() - Clear events which are on -+ * @regs: Pointer to RTC register block -+ * -+ * Returns: A mask of the events which were cleared -+ */ -+uint32_t fman_rtc_check_and_clear_event(struct rtc_regs *regs); -+ -+/** -+ * fman_rtc_ack_event() - Clear events -+ * @regs: Pointer to RTC register block -+ * @events: The events to disable -+ */ -+void fman_rtc_ack_event(struct rtc_regs *regs, uint32_t events); -+ -+/** -+ * fman_rtc_enable_interupt() - Enable events interrupts -+ * @regs: Pointer to RTC register block -+ * @mask: The events to disable -+ */ -+void fman_rtc_enable_interupt(struct rtc_regs *regs, uint32_t mask); -+ -+/** -+ * fman_rtc_disable_interupt() - Disable events interrupts -+ * @regs: Pointer to RTC register block -+ * @mask: The events to disable -+ */ -+void fman_rtc_disable_interupt(struct rtc_regs *regs, uint32_t mask); -+ -+/** -+ * fman_rtc_get_timer_ctrl() - Get the control register -+ * @regs: Pointer to RTC register block -+ * -+ * Returns: The control register value -+ */ -+uint32_t fman_rtc_get_timer_ctrl(struct rtc_regs *regs); -+ -+/** -+ * fman_rtc_set_timer_ctrl() - Set timer control register -+ * @regs: Pointer to RTC register block -+ * @val: The value to set -+ */ -+void fman_rtc_set_timer_ctrl(struct rtc_regs *regs, uint32_t val); -+ -+/** -+ * fman_rtc_get_frequency_compensation() - Get the frequency compensation -+ * @regs: Pointer to RTC register block -+ * -+ * Returns: The timer counter -+ */ -+uint32_t fman_rtc_get_frequency_compensation(struct rtc_regs *regs); -+ -+/** -+ * fman_rtc_set_frequency_compensation() - Set frequency compensation -+ * @regs: Pointer to RTC register block -+ * @val: The value to set -+ */ -+void fman_rtc_set_frequency_compensation(struct rtc_regs *regs, uint32_t val); -+ -+/** -+ * fman_rtc_get_trigger_stamp() - Get a trigger stamp -+ * @regs: Pointer to RTC register block -+ * @id: The id of the trigger stamp -+ * -+ * Returns: The time stamp -+ */ -+uint64_t fman_rtc_get_trigger_stamp(struct rtc_regs *regs, int id); -+ -+/** -+ * fman_rtc_set_timer_alarm_l() - Set timer alarm low register -+ * @regs: Pointer to RTC register block -+ * @index: The index of alarm to set -+ * @val: The value to set -+ */ -+void fman_rtc_set_timer_alarm_l(struct rtc_regs *regs, int index, -+ uint32_t val); -+ -+/** -+ * fman_rtc_set_timer_alarm() - Set timer alarm -+ * @regs: Pointer to RTC register block -+ * @index: The index of alarm to set -+ * @val: The value to set -+ */ -+void fman_rtc_set_timer_alarm(struct rtc_regs *regs, int index, int64_t val); -+ -+/** -+ * fman_rtc_set_timer_fiper() - Set timer fiper -+ * @regs: Pointer to RTC register block -+ * @index: The index of fiper to set -+ * @val: The value to set -+ */ -+void fman_rtc_set_timer_fiper(struct rtc_regs *regs, int index, uint32_t val); -+ -+/** -+ * fman_rtc_set_timer_offset() - Set timer offset -+ * @regs: Pointer to RTC register block -+ * @val: The value to set -+ */ -+void fman_rtc_set_timer_offset(struct rtc_regs *regs, int64_t val); -+ -+/** -+ * fman_rtc_get_timer() - Get the timer counter -+ * @regs: Pointer to RTC register block -+ * -+ * Returns: The timer counter -+ */ -+static inline uint64_t fman_rtc_get_timer(struct rtc_regs *regs) -+{ -+ uint64_t time; -+ /* TMR_CNT_L must be read first to get an accurate value */ -+ time = (uint64_t)ioread32be(®s->tmr_cnt_l); -+ time |= ((uint64_t)ioread32be(®s->tmr_cnt_h) << 32); -+ -+ return time; -+} -+ -+/** -+ * fman_rtc_set_timer() - Set timer counter -+ * @regs: Pointer to RTC register block -+ * @val: The value to set -+ */ -+static inline void fman_rtc_set_timer(struct rtc_regs *regs, int64_t val) -+{ -+ iowrite32be((uint32_t)val, ®s->tmr_cnt_l); -+ iowrite32be((uint32_t)(val >> 32), ®s->tmr_cnt_h); -+} -+ -+/** -+ * fman_rtc_timers_soft_reset() - Soft reset -+ * @regs: Pointer to RTC register block -+ * -+ * Resets all the timer registers and state machines for the 1588 IP and -+ * the attached client 1588 -+ */ -+void fman_rtc_timers_soft_reset(struct rtc_regs *regs); -+ -+/** -+ * fman_rtc_clear_external_trigger() - Clear an external trigger -+ * @regs: Pointer to RTC register block -+ * @id: The id of the trigger to clear -+ */ -+void fman_rtc_clear_external_trigger(struct rtc_regs *regs, int id); -+ -+/** -+ * fman_rtc_clear_periodic_pulse() - Clear periodic pulse -+ * @regs: Pointer to RTC register block -+ * @id: The id of the fiper to clear -+ */ -+void fman_rtc_clear_periodic_pulse(struct rtc_regs *regs, int id); -+ -+/** -+ * fman_rtc_enable() - Enable RTC hardware block -+ * @regs: Pointer to RTC register block -+ */ -+void fman_rtc_enable(struct rtc_regs *regs, bool reset_clock); -+ -+/** -+ * fman_rtc_is_enabled() - Is RTC hardware block enabled -+ * @regs: Pointer to RTC register block -+ * -+ * Return: TRUE if enabled -+ */ -+bool fman_rtc_is_enabled(struct rtc_regs *regs); -+ -+/** -+ * fman_rtc_disable() - Disable RTC hardware block -+ * @regs: Pointer to RTC register block -+ */ -+void fman_rtc_disable(struct rtc_regs *regs); -+ -+/** -+ * fman_rtc_init() - Init RTC hardware block -+ * @cfg: RTC configuration data -+ * @regs: Pointer to RTC register block -+ * @num_alarms: Number of alarms in RTC -+ * @num_fipers: Number of fipers in RTC -+ * @num_ext_triggers: Number of external triggers in RTC -+ * @freq_compensation: Frequency compensation -+ * @output_clock_divisor: Output clock divisor -+ * -+ * This function initializes RTC and applies basic configuration. -+ */ -+void fman_rtc_init(struct rtc_cfg *cfg, struct rtc_regs *regs, int num_alarms, -+ int num_fipers, int num_ext_triggers, bool init_freq_comp, -+ uint32_t freq_compensation, uint32_t output_clock_divisor); -+ -+/** -+ * fman_rtc_set_alarm() - Set an alarm -+ * @regs: Pointer to RTC register block -+ * @id: id of alarm -+ * @val: value to write -+ * @enable: should interrupt be enabled -+ */ -+void fman_rtc_set_alarm(struct rtc_regs *regs, int id, uint32_t val, bool enable); -+ -+/** -+ * fman_rtc_set_periodic_pulse() - Set an alarm -+ * @regs: Pointer to RTC register block -+ * @id: id of fiper -+ * @val: value to write -+ * @enable: should interrupt be enabled -+ */ -+void fman_rtc_set_periodic_pulse(struct rtc_regs *regs, int id, uint32_t val, -+ bool enable); -+ -+/** -+ * fman_rtc_set_ext_trigger() - Set an external trigger -+ * @regs: Pointer to RTC register block -+ * @id: id of trigger -+ * @enable: should interrupt be enabled -+ * @use_pulse_as_input: use the pulse as input -+ */ -+void fman_rtc_set_ext_trigger(struct rtc_regs *regs, int id, bool enable, -+ bool use_pulse_as_input); -+ -+struct fm_rtc_alarm_params { -+ uint8_t alarm_id; /**< 0 or 1 */ -+ uint64_t alarm_time; /**< In nanoseconds, the time when the -+ alarm should go off - must be a -+ multiple of the RTC period */ -+ void (*f_alarm_callback)(void* app, uint8_t id); /**< This routine will -+ be called when RTC reaches alarmTime */ -+ bool clear_on_expiration; /**< TRUE to turn off the alarm once -+ expired.*/ -+}; -+ -+struct fm_rtc_periodic_pulse_params { -+ uint8_t periodic_pulse_id; /**< 0 or 1 */ -+ uint64_t periodic_pulse_period; /**< In Nanoseconds. Must be a multiple -+ of the RTC period */ -+ void (*f_periodic_pulse_callback)(void* app, uint8_t id); /**< This -+ routine will be called every -+ periodicPulsePeriod. */ -+}; -+ -+#endif /* __FSL_FMAN_RTC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_sp.h -@@ -0,0 +1,138 @@ -+/* -+ * Copyright 2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __FSL_FMAN_SP_H -+#define __FSL_FMAN_SP_H -+ -+#include "common/general.h" -+#include "fsl_fman.h" -+ -+ -+struct fm_pcd_storage_profile_regs{ -+ uint32_t fm_sp_ebmpi[8]; -+ /*offset 0 - 0xc*/ -+ /**< Buffer Manager pool Information */ -+ -+ uint32_t fm_sp_acnt; /*offset 0x20*/ -+ uint32_t fm_sp_ebm; /*offset 0x24*/ -+ uint32_t fm_sp_da; /*offset 0x28*/ -+ uint32_t fm_sp_icp; /*offset 0x2c*/ -+ uint32_t fm_sp_mpd; /*offset 0x30*/ -+ uint32_t res1[2]; /*offset 0x34 - 0x38*/ -+ uint32_t fm_sp_spliodn; /*offset 0x3c*/ -+}; -+ -+/**************************************************************************//** -+ @Description structure for defining internal context copying -+*//***************************************************************************/ -+struct fman_sp_int_context_data_copy{ -+ uint16_t ext_buf_offset; /**< Offset in External buffer to which -+ internal context is copied to (Rx) -+ or taken from (Tx, Op). */ -+ uint8_t int_context_offset; /**< Offset within internal context to copy -+ from (Rx) or to copy to (Tx, Op).*/ -+ uint16_t size; /**< Internal offset size to be copied */ -+}; -+ -+/**************************************************************************//** -+ @Description struct for defining external buffer margins -+*//***************************************************************************/ -+struct fman_sp_buf_margins{ -+ uint16_t start_margins; /**< Number of bytes to be left at the -+ beginning of the external buffer (must be -+ divisible by 16) */ -+ uint16_t end_margins; /**< number of bytes to be left at the end of -+ the external buffer(must be divisible by 16)*/ -+}; -+ -+struct fm_storage_profile_params { -+ struct fman_ext_pools fm_ext_pools; -+ struct fman_backup_bm_pools backup_pools; -+ struct fman_sp_int_context_data_copy *int_context; -+ struct fman_sp_buf_margins *buf_margins; -+ enum fman_dma_swap_option dma_swap_data; -+ enum fman_dma_cache_option int_context_cache_attr; -+ enum fman_dma_cache_option header_cache_attr; -+ enum fman_dma_cache_option scatter_gather_cache_attr; -+ bool dma_write_optimize; -+ uint16_t liodn_offset; -+ bool no_scather_gather; -+ struct fman_buf_pool_depletion buf_pool_depletion; -+}; -+ -+/**************************************************************************//** -+ @Description Registers bit fields -+*//***************************************************************************/ -+#define FMAN_SP_EXT_BUF_POOL_EN_COUNTER 0x40000000 -+#define FMAN_SP_EXT_BUF_POOL_VALID 0x80000000 -+#define FMAN_SP_EXT_BUF_POOL_BACKUP 0x20000000 -+#define FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE 0x00100000 -+#define FMAN_SP_SG_DISABLE 0x80000000 -+ -+/* shifts */ -+#define FMAN_SP_EXT_BUF_POOL_ID_SHIFT 16 -+#define FMAN_SP_POOL_DEP_NUM_OF_POOLS_SHIFT 16 -+#define FMAN_SP_EXT_BUF_MARG_START_SHIFT 16 -+#define FMAN_SP_EXT_BUF_MARG_END_SHIFT 0 -+#define FMAN_SP_DMA_ATTR_SWP_SHIFT 30 -+#define FMAN_SP_DMA_ATTR_IC_CACHE_SHIFT 28 -+#define FMAN_SP_DMA_ATTR_HDR_CACHE_SHIFT 26 -+#define FMAN_SP_DMA_ATTR_SG_CACHE_SHIFT 24 -+#define FMAN_SP_IC_TO_EXT_SHIFT 16 -+#define FMAN_SP_IC_FROM_INT_SHIFT 8 -+#define FMAN_SP_IC_SIZE_SHIFT 0 -+ -+/**************************************************************************//** -+ @Description defaults -+*//***************************************************************************/ -+#define DEFAULT_FMAN_SP_DMA_SWAP_DATA FMAN_DMA_NO_SWP -+#define DEFAULT_FMAN_SP_DMA_INT_CONTEXT_CACHE_ATTR FMAN_DMA_NO_STASH -+#define DEFAULT_FMAN_SP_DMA_HEADER_CACHE_ATTR FMAN_DMA_NO_STASH -+#define DEFAULT_FMAN_SP_DMA_SCATTER_GATHER_CACHE_ATTR FMAN_DMA_NO_STASH -+#define DEFAULT_FMAN_SP_DMA_WRITE_OPTIMIZE TRUE -+#define DEFAULT_FMAN_SP_NO_SCATTER_GATHER FALSE -+ -+void fman_vsp_defconfig(struct fm_storage_profile_params *cfg); -+ -+void fman_vsp_init(struct fm_pcd_storage_profile_regs *regs, -+ uint16_t index, struct fm_storage_profile_params *fm_vsp_params, -+ int port_max_num_of_ext_pools, int bm_max_num_of_pools, -+ int max_num_of_pfc_priorities); -+ -+uint32_t fman_vsp_get_statistics(struct fm_pcd_storage_profile_regs *regs, -+ uint16_t index); -+ -+void fman_vsp_set_statistics(struct fm_pcd_storage_profile_regs *regs, -+ uint16_t index, uint32_t value); -+ -+ -+#endif /* __FSL_FMAN_SP_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/flib/fsl_fman_tgec.h -@@ -0,0 +1,479 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __FSL_FMAN_TGEC_H -+#define __FSL_FMAN_TGEC_H -+ -+#include "common/general.h" -+#include "fsl_enet.h" -+ -+ -+/* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */ -+#define TGEC_TX_IPG_LENGTH_MASK 0x000003ff -+ -+enum tgec_counters { -+ E_TGEC_COUNTER_R64, -+ E_TGEC_COUNTER_R127, -+ E_TGEC_COUNTER_R255, -+ E_TGEC_COUNTER_R511, -+ E_TGEC_COUNTER_R1023, -+ E_TGEC_COUNTER_R1518, -+ E_TGEC_COUNTER_R1519X, -+ E_TGEC_COUNTER_TRFRG, -+ E_TGEC_COUNTER_TRJBR, -+ E_TGEC_COUNTER_RDRP, -+ E_TGEC_COUNTER_RALN, -+ E_TGEC_COUNTER_TRUND, -+ E_TGEC_COUNTER_TROVR, -+ E_TGEC_COUNTER_RXPF, -+ E_TGEC_COUNTER_TXPF, -+ E_TGEC_COUNTER_ROCT, -+ E_TGEC_COUNTER_RMCA, -+ E_TGEC_COUNTER_RBCA, -+ E_TGEC_COUNTER_RPKT, -+ E_TGEC_COUNTER_RUCA, -+ E_TGEC_COUNTER_RERR, -+ E_TGEC_COUNTER_TOCT, -+ E_TGEC_COUNTER_TMCA, -+ E_TGEC_COUNTER_TBCA, -+ E_TGEC_COUNTER_TUCA, -+ E_TGEC_COUNTER_TERR -+}; -+ -+/* Command and Configuration Register (COMMAND_CONFIG) */ -+#define CMD_CFG_EN_TIMESTAMP 0x00100000 -+#define CMD_CFG_TX_ADDR_INS_SEL 0x00080000 -+#define CMD_CFG_NO_LEN_CHK 0x00020000 -+#define CMD_CFG_SEND_IDLE 0x00010000 -+#define CMD_CFG_RX_ER_DISC 0x00004000 -+#define CMD_CFG_CMD_FRM_EN 0x00002000 -+#define CMD_CFG_STAT_CLR 0x00001000 -+#define CMD_CFG_LOOPBACK_EN 0x00000400 -+#define CMD_CFG_TX_ADDR_INS 0x00000200 -+#define CMD_CFG_PAUSE_IGNORE 0x00000100 -+#define CMD_CFG_PAUSE_FWD 0x00000080 -+#define CMD_CFG_PROMIS_EN 0x00000010 -+#define CMD_CFG_WAN_MODE 0x00000008 -+#define CMD_CFG_RX_EN 0x00000002 -+#define CMD_CFG_TX_EN 0x00000001 -+ -+/* Interrupt Mask Register (IMASK) */ -+#define TGEC_IMASK_MDIO_SCAN_EVENT 0x00010000 -+#define TGEC_IMASK_MDIO_CMD_CMPL 0x00008000 -+#define TGEC_IMASK_REM_FAULT 0x00004000 -+#define TGEC_IMASK_LOC_FAULT 0x00002000 -+#define TGEC_IMASK_TX_ECC_ER 0x00001000 -+#define TGEC_IMASK_TX_FIFO_UNFL 0x00000800 -+#define TGEC_IMASK_TX_FIFO_OVFL 0x00000400 -+#define TGEC_IMASK_TX_ER 0x00000200 -+#define TGEC_IMASK_RX_FIFO_OVFL 0x00000100 -+#define TGEC_IMASK_RX_ECC_ER 0x00000080 -+#define TGEC_IMASK_RX_JAB_FRM 0x00000040 -+#define TGEC_IMASK_RX_OVRSZ_FRM 0x00000020 -+#define TGEC_IMASK_RX_RUNT_FRM 0x00000010 -+#define TGEC_IMASK_RX_FRAG_FRM 0x00000008 -+#define TGEC_IMASK_RX_LEN_ER 0x00000004 -+#define TGEC_IMASK_RX_CRC_ER 0x00000002 -+#define TGEC_IMASK_RX_ALIGN_ER 0x00000001 -+ -+#define TGEC_EVENTS_MASK \ -+ ((uint32_t)(TGEC_IMASK_MDIO_SCAN_EVENT | \ -+ TGEC_IMASK_MDIO_CMD_CMPL | \ -+ TGEC_IMASK_REM_FAULT | \ -+ TGEC_IMASK_LOC_FAULT | \ -+ TGEC_IMASK_TX_ECC_ER | \ -+ TGEC_IMASK_TX_FIFO_UNFL | \ -+ TGEC_IMASK_TX_FIFO_OVFL | \ -+ TGEC_IMASK_TX_ER | \ -+ TGEC_IMASK_RX_FIFO_OVFL | \ -+ TGEC_IMASK_RX_ECC_ER | \ -+ TGEC_IMASK_RX_JAB_FRM | \ -+ TGEC_IMASK_RX_OVRSZ_FRM | \ -+ TGEC_IMASK_RX_RUNT_FRM | \ -+ TGEC_IMASK_RX_FRAG_FRM | \ -+ TGEC_IMASK_RX_LEN_ER | \ -+ TGEC_IMASK_RX_CRC_ER | \ -+ TGEC_IMASK_RX_ALIGN_ER)) -+ -+/* Hashtable Control Register (HASHTABLE_CTRL) */ -+#define TGEC_HASH_MCAST_SHIFT 23 -+#define TGEC_HASH_MCAST_EN 0x00000200 -+#define TGEC_HASH_ADR_MSK 0x000001ff -+ -+#define DEFAULT_WAN_MODE_ENABLE FALSE -+#define DEFAULT_PROMISCUOUS_MODE_ENABLE FALSE -+#define DEFAULT_PAUSE_FORWARD_ENABLE FALSE -+#define DEFAULT_PAUSE_IGNORE FALSE -+#define DEFAULT_TX_ADDR_INS_ENABLE FALSE -+#define DEFAULT_LOOPBACK_ENABLE FALSE -+#define DEFAULT_CMD_FRAME_ENABLE FALSE -+#define DEFAULT_RX_ERROR_DISCARD FALSE -+#define DEFAULT_SEND_IDLE_ENABLE FALSE -+#define DEFAULT_NO_LENGTH_CHECK_ENABLE TRUE -+#define DEFAULT_LGTH_CHECK_NOSTDR FALSE -+#define DEFAULT_TIME_STAMP_ENABLE FALSE -+#define DEFAULT_TX_IPG_LENGTH 12 -+#define DEFAULT_MAX_FRAME_LENGTH 0x600 -+#define DEFAULT_PAUSE_QUANT 0xf000 -+ -+/* -+ * 10G memory map -+ */ -+struct tgec_regs { -+ uint32_t tgec_id; /* 0x000 Controller ID */ -+ uint32_t reserved001[1]; /* 0x004 */ -+ uint32_t command_config; /* 0x008 Control and configuration */ -+ uint32_t mac_addr_0; /* 0x00c Lower 32 bits of the MAC adr */ -+ uint32_t mac_addr_1; /* 0x010 Upper 16 bits of the MAC adr */ -+ uint32_t maxfrm; /* 0x014 Maximum frame length */ -+ uint32_t pause_quant; /* 0x018 Pause quanta */ -+ uint32_t rx_fifo_sections; /* 0x01c */ -+ uint32_t tx_fifo_sections; /* 0x020 */ -+ uint32_t rx_fifo_almost_f_e; /* 0x024 */ -+ uint32_t tx_fifo_almost_f_e; /* 0x028 */ -+ uint32_t hashtable_ctrl; /* 0x02c Hash table control*/ -+ uint32_t mdio_cfg_status; /* 0x030 */ -+ uint32_t mdio_command; /* 0x034 */ -+ uint32_t mdio_data; /* 0x038 */ -+ uint32_t mdio_regaddr; /* 0x03c */ -+ uint32_t status; /* 0x040 */ -+ uint32_t tx_ipg_len; /* 0x044 Transmitter inter-packet-gap */ -+ uint32_t mac_addr_2; /* 0x048 Lower 32 bits of 2nd MAC adr */ -+ uint32_t mac_addr_3; /* 0x04c Upper 16 bits of 2nd MAC adr */ -+ uint32_t rx_fifo_ptr_rd; /* 0x050 */ -+ uint32_t rx_fifo_ptr_wr; /* 0x054 */ -+ uint32_t tx_fifo_ptr_rd; /* 0x058 */ -+ uint32_t tx_fifo_ptr_wr; /* 0x05c */ -+ uint32_t imask; /* 0x060 Interrupt mask */ -+ uint32_t ievent; /* 0x064 Interrupt event */ -+ uint32_t udp_port; /* 0x068 Defines a UDP Port number */ -+ uint32_t type_1588v2; /* 0x06c Type field for 1588v2 */ -+ uint32_t reserved070[4]; /* 0x070 */ -+ /*10Ge Statistics Counter */ -+ uint32_t tfrm_u; /* 80 aFramesTransmittedOK */ -+ uint32_t tfrm_l; /* 84 aFramesTransmittedOK */ -+ uint32_t rfrm_u; /* 88 aFramesReceivedOK */ -+ uint32_t rfrm_l; /* 8c aFramesReceivedOK */ -+ uint32_t rfcs_u; /* 90 aFrameCheckSequenceErrors */ -+ uint32_t rfcs_l; /* 94 aFrameCheckSequenceErrors */ -+ uint32_t raln_u; /* 98 aAlignmentErrors */ -+ uint32_t raln_l; /* 9c aAlignmentErrors */ -+ uint32_t txpf_u; /* A0 aPAUSEMACCtrlFramesTransmitted */ -+ uint32_t txpf_l; /* A4 aPAUSEMACCtrlFramesTransmitted */ -+ uint32_t rxpf_u; /* A8 aPAUSEMACCtrlFramesReceived */ -+ uint32_t rxpf_l; /* Ac aPAUSEMACCtrlFramesReceived */ -+ uint32_t rlong_u; /* B0 aFrameTooLongErrors */ -+ uint32_t rlong_l; /* B4 aFrameTooLongErrors */ -+ uint32_t rflr_u; /* B8 aInRangeLengthErrors */ -+ uint32_t rflr_l; /* Bc aInRangeLengthErrors */ -+ uint32_t tvlan_u; /* C0 VLANTransmittedOK */ -+ uint32_t tvlan_l; /* C4 VLANTransmittedOK */ -+ uint32_t rvlan_u; /* C8 VLANReceivedOK */ -+ uint32_t rvlan_l; /* Cc VLANReceivedOK */ -+ uint32_t toct_u; /* D0 ifOutOctets */ -+ uint32_t toct_l; /* D4 ifOutOctets */ -+ uint32_t roct_u; /* D8 ifInOctets */ -+ uint32_t roct_l; /* Dc ifInOctets */ -+ uint32_t ruca_u; /* E0 ifInUcastPkts */ -+ uint32_t ruca_l; /* E4 ifInUcastPkts */ -+ uint32_t rmca_u; /* E8 ifInMulticastPkts */ -+ uint32_t rmca_l; /* Ec ifInMulticastPkts */ -+ uint32_t rbca_u; /* F0 ifInBroadcastPkts */ -+ uint32_t rbca_l; /* F4 ifInBroadcastPkts */ -+ uint32_t terr_u; /* F8 ifOutErrors */ -+ uint32_t terr_l; /* Fc ifOutErrors */ -+ uint32_t reserved100[2]; /* 100-108*/ -+ uint32_t tuca_u; /* 108 ifOutUcastPkts */ -+ uint32_t tuca_l; /* 10c ifOutUcastPkts */ -+ uint32_t tmca_u; /* 110 ifOutMulticastPkts */ -+ uint32_t tmca_l; /* 114 ifOutMulticastPkts */ -+ uint32_t tbca_u; /* 118 ifOutBroadcastPkts */ -+ uint32_t tbca_l; /* 11c ifOutBroadcastPkts */ -+ uint32_t rdrp_u; /* 120 etherStatsDropEvents */ -+ uint32_t rdrp_l; /* 124 etherStatsDropEvents */ -+ uint32_t reoct_u; /* 128 etherStatsOctets */ -+ uint32_t reoct_l; /* 12c etherStatsOctets */ -+ uint32_t rpkt_u; /* 130 etherStatsPkts */ -+ uint32_t rpkt_l; /* 134 etherStatsPkts */ -+ uint32_t trund_u; /* 138 etherStatsUndersizePkts */ -+ uint32_t trund_l; /* 13c etherStatsUndersizePkts */ -+ uint32_t r64_u; /* 140 etherStatsPkts64Octets */ -+ uint32_t r64_l; /* 144 etherStatsPkts64Octets */ -+ uint32_t r127_u; /* 148 etherStatsPkts65to127Octets */ -+ uint32_t r127_l; /* 14c etherStatsPkts65to127Octets */ -+ uint32_t r255_u; /* 150 etherStatsPkts128to255Octets */ -+ uint32_t r255_l; /* 154 etherStatsPkts128to255Octets */ -+ uint32_t r511_u; /* 158 etherStatsPkts256to511Octets */ -+ uint32_t r511_l; /* 15c etherStatsPkts256to511Octets */ -+ uint32_t r1023_u; /* 160 etherStatsPkts512to1023Octets */ -+ uint32_t r1023_l; /* 164 etherStatsPkts512to1023Octets */ -+ uint32_t r1518_u; /* 168 etherStatsPkts1024to1518Octets */ -+ uint32_t r1518_l; /* 16c etherStatsPkts1024to1518Octets */ -+ uint32_t r1519x_u; /* 170 etherStatsPkts1519toX */ -+ uint32_t r1519x_l; /* 174 etherStatsPkts1519toX */ -+ uint32_t trovr_u; /* 178 etherStatsOversizePkts */ -+ uint32_t trovr_l; /* 17c etherStatsOversizePkts */ -+ uint32_t trjbr_u; /* 180 etherStatsJabbers */ -+ uint32_t trjbr_l; /* 184 etherStatsJabbers */ -+ uint32_t trfrg_u; /* 188 etherStatsFragments */ -+ uint32_t trfrg_l; /* 18C etherStatsFragments */ -+ uint32_t rerr_u; /* 190 ifInErrors */ -+ uint32_t rerr_l; /* 194 ifInErrors */ -+}; -+ -+/** -+ * struct tgec_cfg - TGEC configuration -+ * -+ * @rx_error_discard: Receive Erroneous Frame Discard Enable. When set to 1 -+ * any frame received with an error is discarded in the -+ * Core and not forwarded to the Client interface. -+ * When set to 0 (Reset value), erroneous Frames are -+ * forwarded to the Client interface with ff_rx_err -+ * asserted. -+ * @pause_ignore: Ignore Pause Frame Quanta. If set to 1 received pause -+ * frames are ignored by the MAC. When set to 0 -+ * (Reset value) the transmit process is stopped for the -+ * amount of time specified in the pause quanta received -+ * within a pause frame. -+ * @pause_forward_enable: -+ * Terminate / Forward Pause Frames. If set to 1 pause -+ * frames are forwarded to the user application. When set -+ * to 0 (Reset value) pause frames are terminated and -+ * discarded within the MAC. -+ * @no_length_check_enable: -+ * Payload Length Check Disable. When set to 0 -+ * (Reset value), the Core checks the frame's payload -+ * length with the Frame Length/Type field, when set to 1 -+ * the payload length check is disabled. -+ * @cmd_frame_enable: Enables reception of all command frames. When set to 1 -+ * all Command Frames are accepted, when set to 0 -+ * (Reset Value) only Pause Frames are accepted and all -+ * other Command Frames are rejected. -+ * @send_idle_enable: Force Idle Generation. When set to 1, the MAC -+ * permanently sends XGMII Idle sequences even when faults -+ * are received. -+ * @wan_mode_enable: WAN Mode Enable. Sets WAN mode (1) or LAN mode -+ * (0, default) of operation. -+ * @promiscuous_mode_enable: -+ * Enables MAC promiscuous operation. When set to 1, all -+ * frames are received without any MAC address filtering, -+ * when set to 0 (Reset value) Unicast Frames with a -+ * destination address not matching the Core MAC Address -+ * (MAC Address programmed in Registers MAC_ADDR_0 and -+ * MAC_ADDR_1 or the MAC address programmed in Registers -+ * MAC_ADDR_2 and MAC_ADDR_3) are rejected. -+ * @tx_addr_ins_enable: Set Source MAC Address on Transmit. If set to 1 the -+ * MAC overwrites the source MAC address received from the -+ * Client Interface with one of the MAC addresses. If set -+ * to 0 (Reset value), the source MAC address from the -+ * Client Interface is transmitted unmodified to the line. -+ * @loopback_enable: PHY Interface Loopback. When set to 1, the signal -+ * loop_ena is set to '1', when set to 0 (Reset value) -+ * the signal loop_ena is set to 0. -+ * @lgth_check_nostdr: The Core interprets the Length/Type field differently -+ * depending on the value of this Bit -+ * @time_stamp_enable: This bit selects between enabling and disabling the -+ * IEEE 1588 functionality. 1: IEEE 1588 is enabled -+ * 0: IEEE 1588 is disabled -+ * @max_frame_length: Maximum supported received frame length. -+ * The 10GEC MAC supports reception of any frame size up -+ * to 16,352 bytes (0x3FE0). Typical settings are -+ * 0x05EE (1,518 bytes) for standard frames. -+ * Default setting is 0x0600 (1,536 bytes). -+ * Received frames that exceed this stated maximum -+ * are truncated. -+ * @pause_quant: Pause quanta value used with transmitted pause frames. -+ * Each quanta represents a 512 bit-times. -+ * @tx_ipg_length: Transmit Inter-Packet-Gap (IPG) value. A 6-bit value: -+ * Depending on LAN or WAN mode of operation the value has -+ * the following meaning: - LAN Mode: Number of octets in -+ * steps of 4. Valid values are 8, 12, 16, ... 100. DIC is -+ * fully supported (see 10.6.1 page 49) for any setting. A -+ * default of 12 (reset value) must be set to conform to -+ * IEEE802.3ae. Warning: When set to 8, PCS layers may not -+ * be able to perform clock rate compensation. - WAN Mode: -+ * Stretch factor. Valid values are 4..15. The stretch -+ * factor is calculated as (value+1)*8. A default of 12 -+ * (reset value) must be set to conform to IEEE 802.3ae -+ * (i.e. 13*8=104). A larger value shrinks the IPG -+ * (increasing bandwidth). -+ * -+ * This structure contains basic TGEC configuration and must be passed to -+ * fman_tgec_init() function. A default set of configuration values can be -+ * obtained by calling fman_tgec_defconfig(). -+ */ -+struct tgec_cfg { -+ bool rx_error_discard; -+ bool pause_ignore; -+ bool pause_forward_enable; -+ bool no_length_check_enable; -+ bool cmd_frame_enable; -+ bool send_idle_enable; -+ bool wan_mode_enable; -+ bool promiscuous_mode_enable; -+ bool tx_addr_ins_enable; -+ bool loopback_enable; -+ bool lgth_check_nostdr; -+ bool time_stamp_enable; -+ uint16_t max_frame_length; -+ uint16_t pause_quant; -+ uint32_t tx_ipg_length; -+ bool skip_fman11_workaround; -+}; -+ -+ -+void fman_tgec_defconfig(struct tgec_cfg *cfg); -+ -+/** -+ * fman_tgec_init() - Init tgec hardware block -+ * @regs: Pointer to tgec register block -+ * @cfg: tgec configuration data -+ * @exceptions_mask: initial exceptions mask -+ * -+ * This function initializes the tgec controller and applies its -+ * basic configuration. -+ * -+ * Returns: 0 if successful, an error code otherwise. -+ */ -+ -+int fman_tgec_init(struct tgec_regs *regs, struct tgec_cfg *cfg, -+ uint32_t exception_mask); -+ -+void fman_tgec_enable(struct tgec_regs *regs, bool apply_rx, bool apply_tx); -+ -+void fman_tgec_disable(struct tgec_regs *regs, bool apply_rx, bool apply_tx); -+ -+uint32_t fman_tgec_get_revision(struct tgec_regs *regs); -+ -+void fman_tgec_set_mac_address(struct tgec_regs *regs, uint8_t *macaddr); -+ -+void fman_tgec_set_promiscuous(struct tgec_regs *regs, bool val); -+ -+/** -+ * fman_tgec_reset_stat() - Completely resets all TGEC HW counters -+ * @regs: Pointer to TGEC register block -+ */ -+void fman_tgec_reset_stat(struct tgec_regs *regs); -+ -+/** -+ * fman_tgec_get_counter() - Reads TGEC HW counters -+ * @regs: Pointer to TGEC register block -+ * @reg_name: Counter name according to the appropriate enum -+ * -+ * Returns: Required counter value -+ */ -+uint64_t fman_tgec_get_counter(struct tgec_regs *regs, -+ enum tgec_counters reg_name); -+ -+/** -+ * fman_tgec_set_hash_table() - Sets the Hashtable Control Register -+ * @regs: Pointer to TGEC register block -+ * @value: Value to be written in Hashtable Control Register -+ */ -+void fman_tgec_set_hash_table(struct tgec_regs *regs, uint32_t value); -+ -+/** -+ * fman_tgec_set_tx_pause_frames() - Sets the Pause Quanta Register -+ * @regs: Pointer to TGEC register block -+ * @pause_time: Pause quanta value used with transmitted pause frames. -+ * Each quanta represents a 512 bit-times -+ */ -+void fman_tgec_set_tx_pause_frames(struct tgec_regs *regs, uint16_t pause_time); -+ -+/** -+ * fman_tgec_set_rx_ignore_pause_frames() - Changes the policy WRT pause frames -+ * @regs: Pointer to TGEC register block -+ * @en: Ignore/Respond to pause frame quanta -+ * -+ * Sets the value of PAUSE_IGNORE field in the COMMAND_CONFIG Register -+ * 0 - MAC stops transmit process for the duration specified -+ * in the Pause frame quanta of a received Pause frame. -+ * 1 - MAC ignores received Pause frames. -+ */ -+void fman_tgec_set_rx_ignore_pause_frames(struct tgec_regs *regs, bool en); -+ -+/** -+ * fman_tgec_enable_1588_time_stamp() - change timestamp functionality -+ * @regs: Pointer to TGEC register block -+ * @en: enable/disable timestamp functionality -+ * -+ * Sets the value of EN_TIMESTAMP field in the COMMAND_CONFIG Register -+ * IEEE 1588 timestamp functionality control: -+ * 0 disabled, 1 enabled -+ */ -+ -+void fman_tgec_enable_1588_time_stamp(struct tgec_regs *regs, bool en); -+ -+uint32_t fman_tgec_get_event(struct tgec_regs *regs, uint32_t ev_mask); -+ -+void fman_tgec_ack_event(struct tgec_regs *regs, uint32_t ev_mask); -+ -+uint32_t fman_tgec_get_interrupt_mask(struct tgec_regs *regs); -+ -+/** -+ * fman_tgec_add_addr_in_paddr() - Sets additional exact match MAC address -+ * @regs: Pointer to TGEC register block -+ * @addr_ptr: Pointer to 6-byte array containing the MAC address -+ * -+ * Sets the additional station MAC address -+ */ -+void fman_tgec_add_addr_in_paddr(struct tgec_regs *regs, uint8_t *addr_ptr); -+ -+void fman_tgec_clear_addr_in_paddr(struct tgec_regs *regs); -+ -+void fman_tgec_enable_interrupt(struct tgec_regs *regs, uint32_t ev_mask); -+ -+void fman_tgec_disable_interrupt(struct tgec_regs *regs, uint32_t ev_mask); -+ -+void fman_tgec_reset_filter_table(struct tgec_regs *regs); -+ -+void fman_tgec_set_hash_table_entry(struct tgec_regs *regs, uint32_t crc); -+ -+ -+/** -+ * fman_tgec_get_max_frame_len() - Returns the maximum frame length value -+ * @regs: Pointer to TGEC register block -+ */ -+uint16_t fman_tgec_get_max_frame_len(struct tgec_regs *regs); -+ -+/** -+ * fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007() - Initialize the -+ * main tgec configuration parameters -+ * @regs: Pointer to TGEC register block -+ * -+ * TODO -+ */ -+void fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(struct tgec_regs -+ *regs); -+ -+ -+#endif /* __FSL_FMAN_TGEC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3H/dpaa_integration_ext.h -@@ -0,0 +1,290 @@ -+/* -+ * Copyright 2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/** -+ -+ @File dpaa_integration_ext.h -+ -+ @Description T4240 FM external definitions and structures. -+*//***************************************************************************/ -+#ifndef __DPAA_INTEGRATION_EXT_H -+#define __DPAA_INTEGRATION_EXT_H -+ -+#include "std_ext.h" -+ -+ -+#define DPAA_VERSION 11 -+ -+/**************************************************************************//** -+ @Description DPAA SW Portals Enumeration. -+*//***************************************************************************/ -+typedef enum -+{ -+ e_DPAA_SWPORTAL0 = 0, -+ e_DPAA_SWPORTAL1, -+ e_DPAA_SWPORTAL2, -+ e_DPAA_SWPORTAL3, -+ e_DPAA_SWPORTAL4, -+ e_DPAA_SWPORTAL5, -+ e_DPAA_SWPORTAL6, -+ e_DPAA_SWPORTAL7, -+ e_DPAA_SWPORTAL8, -+ e_DPAA_SWPORTAL9, -+ e_DPAA_SWPORTAL10, -+ e_DPAA_SWPORTAL11, -+ e_DPAA_SWPORTAL12, -+ e_DPAA_SWPORTAL13, -+ e_DPAA_SWPORTAL14, -+ e_DPAA_SWPORTAL15, -+ e_DPAA_SWPORTAL16, -+ e_DPAA_SWPORTAL17, -+ e_DPAA_SWPORTAL18, -+ e_DPAA_SWPORTAL19, -+ e_DPAA_SWPORTAL20, -+ e_DPAA_SWPORTAL21, -+ e_DPAA_SWPORTAL22, -+ e_DPAA_SWPORTAL23, -+ e_DPAA_SWPORTAL24, -+ e_DPAA_SWPORTAL_DUMMY_LAST -+} e_DpaaSwPortal; -+ -+/**************************************************************************//** -+ @Description DPAA Direct Connect Portals Enumeration. -+*//***************************************************************************/ -+typedef enum -+{ -+ e_DPAA_DCPORTAL0 = 0, -+ e_DPAA_DCPORTAL1, -+ e_DPAA_DCPORTAL2, -+ e_DPAA_DCPORTAL_DUMMY_LAST -+} e_DpaaDcPortal; -+ -+#define DPAA_MAX_NUM_OF_SW_PORTALS e_DPAA_SWPORTAL_DUMMY_LAST -+#define DPAA_MAX_NUM_OF_DC_PORTALS e_DPAA_DCPORTAL_DUMMY_LAST -+ -+/***************************************************************************** -+ QMan INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define QM_MAX_NUM_OF_POOL_CHANNELS 15 /**< Total number of channels, dedicated and pool */ -+#define QM_MAX_NUM_OF_WQ 8 /**< Number of work queues per channel */ -+#define QM_MAX_NUM_OF_CGS 256 /**< Congestion groups number */ -+#define QM_MAX_NUM_OF_FQIDS (16 * MEGABYTE) -+ /**< FQIDs range - 24 bits */ -+ -+/**************************************************************************//** -+ @Description Work Queue Channel assignments in QMan. -+*//***************************************************************************/ -+typedef enum -+{ -+ e_QM_FQ_CHANNEL_SWPORTAL0 = 0x0, /**< Dedicated channels serviced by software portals 0 to 24 */ -+ e_QM_FQ_CHANNEL_SWPORTAL1, -+ e_QM_FQ_CHANNEL_SWPORTAL2, -+ e_QM_FQ_CHANNEL_SWPORTAL3, -+ e_QM_FQ_CHANNEL_SWPORTAL4, -+ e_QM_FQ_CHANNEL_SWPORTAL5, -+ e_QM_FQ_CHANNEL_SWPORTAL6, -+ e_QM_FQ_CHANNEL_SWPORTAL7, -+ e_QM_FQ_CHANNEL_SWPORTAL8, -+ e_QM_FQ_CHANNEL_SWPORTAL9, -+ e_QM_FQ_CHANNEL_SWPORTAL10, -+ e_QM_FQ_CHANNEL_SWPORTAL11, -+ e_QM_FQ_CHANNEL_SWPORTAL12, -+ e_QM_FQ_CHANNEL_SWPORTAL13, -+ e_QM_FQ_CHANNEL_SWPORTAL14, -+ e_QM_FQ_CHANNEL_SWPORTAL15, -+ e_QM_FQ_CHANNEL_SWPORTAL16, -+ e_QM_FQ_CHANNEL_SWPORTAL17, -+ e_QM_FQ_CHANNEL_SWPORTAL18, -+ e_QM_FQ_CHANNEL_SWPORTAL19, -+ e_QM_FQ_CHANNEL_SWPORTAL20, -+ e_QM_FQ_CHANNEL_SWPORTAL21, -+ e_QM_FQ_CHANNEL_SWPORTAL22, -+ e_QM_FQ_CHANNEL_SWPORTAL23, -+ e_QM_FQ_CHANNEL_SWPORTAL24, -+ -+ e_QM_FQ_CHANNEL_POOL1 = 0x401, /**< Pool channels that can be serviced by any of the software portals */ -+ e_QM_FQ_CHANNEL_POOL2, -+ e_QM_FQ_CHANNEL_POOL3, -+ e_QM_FQ_CHANNEL_POOL4, -+ e_QM_FQ_CHANNEL_POOL5, -+ e_QM_FQ_CHANNEL_POOL6, -+ e_QM_FQ_CHANNEL_POOL7, -+ e_QM_FQ_CHANNEL_POOL8, -+ e_QM_FQ_CHANNEL_POOL9, -+ e_QM_FQ_CHANNEL_POOL10, -+ e_QM_FQ_CHANNEL_POOL11, -+ e_QM_FQ_CHANNEL_POOL12, -+ e_QM_FQ_CHANNEL_POOL13, -+ e_QM_FQ_CHANNEL_POOL14, -+ e_QM_FQ_CHANNEL_POOL15, -+ -+ e_QM_FQ_CHANNEL_FMAN0_SP0 = 0x800, /**< Dedicated channels serviced by Direct Connect Portal 0: -+ connected to FMan 0; assigned in incrementing order to -+ each sub-portal (SP) in the portal */ -+ e_QM_FQ_CHANNEL_FMAN0_SP1, -+ e_QM_FQ_CHANNEL_FMAN0_SP2, -+ e_QM_FQ_CHANNEL_FMAN0_SP3, -+ e_QM_FQ_CHANNEL_FMAN0_SP4, -+ e_QM_FQ_CHANNEL_FMAN0_SP5, -+ e_QM_FQ_CHANNEL_FMAN0_SP6, -+ e_QM_FQ_CHANNEL_FMAN0_SP7, -+ e_QM_FQ_CHANNEL_FMAN0_SP8, -+ e_QM_FQ_CHANNEL_FMAN0_SP9, -+ e_QM_FQ_CHANNEL_FMAN0_SP10, -+ e_QM_FQ_CHANNEL_FMAN0_SP11, -+ e_QM_FQ_CHANNEL_FMAN0_SP12, -+ e_QM_FQ_CHANNEL_FMAN0_SP13, -+ e_QM_FQ_CHANNEL_FMAN0_SP14, -+ e_QM_FQ_CHANNEL_FMAN0_SP15, -+ -+ e_QM_FQ_CHANNEL_RMAN_SP0 = 0x820, /**< Dedicated channels serviced by Direct Connect Portal 1: connected to RMan */ -+ e_QM_FQ_CHANNEL_RMAN_SP1, -+ -+ e_QM_FQ_CHANNEL_CAAM = 0x840 /**< Dedicated channel serviced by Direct Connect Portal 2: -+ connected to SEC */ -+} e_QmFQChannel; -+ -+/***************************************************************************** -+ BMan INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define BM_MAX_NUM_OF_POOLS 64 /**< Number of buffers pools */ -+ -+/***************************************************************************** -+ SEC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define SEC_NUM_OF_DECOS 3 -+#define SEC_ALL_DECOS_MASK 0x00000003 -+ -+ -+/***************************************************************************** -+ FM INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define INTG_MAX_NUM_OF_FM 2 -+/* Ports defines */ -+#define FM_MAX_NUM_OF_1G_MACS 6 -+#define FM_MAX_NUM_OF_10G_MACS 2 -+#define FM_MAX_NUM_OF_MACS (FM_MAX_NUM_OF_1G_MACS + FM_MAX_NUM_OF_10G_MACS) -+#define FM_MAX_NUM_OF_OH_PORTS 6 -+ -+#define FM_MAX_NUM_OF_1G_RX_PORTS FM_MAX_NUM_OF_1G_MACS -+#define FM_MAX_NUM_OF_10G_RX_PORTS FM_MAX_NUM_OF_10G_MACS -+#define FM_MAX_NUM_OF_RX_PORTS (FM_MAX_NUM_OF_10G_RX_PORTS + FM_MAX_NUM_OF_1G_RX_PORTS) -+ -+#define FM_MAX_NUM_OF_1G_TX_PORTS FM_MAX_NUM_OF_1G_MACS -+#define FM_MAX_NUM_OF_10G_TX_PORTS FM_MAX_NUM_OF_10G_MACS -+#define FM_MAX_NUM_OF_TX_PORTS (FM_MAX_NUM_OF_10G_TX_PORTS + FM_MAX_NUM_OF_1G_TX_PORTS) -+ -+#define FM_PORT_MAX_NUM_OF_EXT_POOLS 4 /**< Number of external BM pools per Rx port */ -+#define FM_PORT_NUM_OF_CONGESTION_GRPS 256 /**< Total number of congestion groups in QM */ -+#define FM_MAX_NUM_OF_SUB_PORTALS 16 -+#define FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS 0 -+ -+#define FM_VSP_MAX_NUM_OF_ENTRIES 64 -+#define FM_MAX_NUM_OF_PFC_PRIORITIES 8 -+ -+/* RAMs defines */ -+#define FM_MURAM_SIZE (384 * KILOBYTE) -+#define FM_IRAM_SIZE(major, minor) (64 * KILOBYTE) -+#define FM_NUM_OF_CTRL 4 -+ -+/* PCD defines */ -+#define FM_PCD_PLCR_NUM_ENTRIES 256 /**< Total number of policer profiles */ -+#define FM_PCD_KG_NUM_OF_SCHEMES 32 /**< Total number of KG schemes */ -+#define FM_PCD_MAX_NUM_OF_CLS_PLANS 256 /**< Number of classification plan entries. */ -+#define FM_PCD_PRS_SW_PATCHES_SIZE 0x00000600 /**< Number of bytes saved for patches */ -+#define FM_PCD_SW_PRS_SIZE 0x00000800 /**< Total size of SW parser area */ -+ -+/* RTC defines */ -+#define FM_RTC_NUM_OF_ALARMS 2 /**< RTC number of alarms */ -+#define FM_RTC_NUM_OF_PERIODIC_PULSES 3 /**< RTC number of periodic pulses */ -+#define FM_RTC_NUM_OF_EXT_TRIGGERS 2 /**< RTC number of external triggers */ -+ -+/* QMI defines */ -+#define QMI_MAX_NUM_OF_TNUMS 64 -+#define QMI_DEF_TNUMS_THRESH 32 -+/* FPM defines */ -+#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4 -+ -+/* DMA defines */ -+#define DMA_THRESH_MAX_COMMQ 83 -+#define DMA_THRESH_MAX_BUF 127 -+ -+/* BMI defines */ -+#define BMI_MAX_NUM_OF_TASKS 128 -+#define BMI_MAX_NUM_OF_DMAS 84 -+ -+#define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE) -+#define PORT_MAX_WEIGHT 16 -+ -+#define FM_CHECK_PORT_RESTRICTIONS(__validPorts, __newPortIndx) TRUE -+ -+/* Unique T4240 */ -+#define FM_OP_OPEN_DMA_MIN_LIMIT -+#define FM_NO_RESTRICT_ON_ACCESS_RSRC -+#define FM_NO_OP_OBSERVED_POOLS -+#define FM_FRAME_END_PARAMS_FOR_OP -+#define FM_DEQ_PIPELINE_PARAMS_FOR_OP -+#define FM_QMI_NO_SINGLE_ECC_EXCEPTION -+ -+#define FM_NO_GUARANTEED_RESET_VALUES -+ -+/* FM errata */ -+#define FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 -+#define FM_WRONG_RESET_VALUES_ERRATA_FMAN_A005127 -+#define FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 -+#define FM_OP_NO_VSP_NO_RELEASE_ERRATA_FMAN_A006675 -+#define FM_HEAVY_TRAFFIC_SEQUENCER_HANG_ERRATA_FMAN_A006981 -+ -+#define FM_BCB_ERRATA_BMI_SW001 -+#define FM_LEN_CHECK_ERRATA_FMAN_SW002 -+#define FM_AID_MODE_NO_TNUM_SW005 /* refer to pdm TKT068794 - only support of port_id on aid */ -+#define FM_ERROR_VSP_NO_MATCH_SW006 /* refer to pdm TKT174304 - no match between errorQ and VSP */ -+ -+/***************************************************************************** -+ RMan INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define RM_MAX_NUM_OF_IB 4 /**< Number of inbound blocks */ -+#define RM_NUM_OF_IBCU 8 /**< NUmber of classification units in an inbound block */ -+ -+/* RMan erratas */ -+#define RM_ERRONEOUS_ACK_ERRATA_RMAN_A006756 -+ -+/***************************************************************************** -+ FM MACSEC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define NUM_OF_RX_SC 16 -+#define NUM_OF_TX_SC 16 -+ -+#define NUM_OF_SA_PER_RX_SC 2 -+#define NUM_OF_SA_PER_TX_SC 2 -+ -+#endif /* __DPAA_INTEGRATION_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3H/part_ext.h -@@ -0,0 +1,71 @@ -+/* -+ * Copyright 2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ -+ @File part_ext.h -+ -+ @Description Definitions for the part (integration) module. -+*//***************************************************************************/ -+ -+#ifndef __PART_EXT_H -+#define __PART_EXT_H -+ -+#include "std_ext.h" -+#include "part_integration_ext.h" -+ -+#if !(defined(P1023) || \ -+ defined(P2041) || \ -+ defined(P3041) || \ -+ defined(P4080) || \ -+ defined(P5020) || \ -+ defined(P5040) || \ -+ defined(B4860) || \ -+ defined(T4240)) -+#error "unable to proceed without chip-definition" -+#endif -+ -+ -+/**************************************************************************//* -+ @Description Part data structure - must be contained in any integration -+ data structure. -+*//***************************************************************************/ -+typedef struct t_Part -+{ -+ uintptr_t (* f_GetModuleBase)(t_Handle h_Part, e_ModuleId moduleId); -+ /**< Returns the address of the module's memory map base. */ -+ e_ModuleId (* f_GetModuleIdByBase)(t_Handle h_Part, uintptr_t baseAddress); -+ /**< Returns the module's ID according to its memory map base. */ -+} t_Part; -+ -+ -+#endif /* __PART_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3H/part_integration_ext.h -@@ -0,0 +1,304 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/** -+ -+ @File part_integration_ext.h -+ -+ @Description T4240 external definitions and structures. -+*//***************************************************************************/ -+#ifndef __PART_INTEGRATION_EXT_H -+#define __PART_INTEGRATION_EXT_H -+ -+#include "std_ext.h" -+#include "ddr_std_ext.h" -+#include "enet_ext.h" -+#include "dpaa_integration_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group T4240_chip_id T4240 Application Programming Interface -+ -+ @Description T4240 Chip functions,definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+#define CORE_E6500 -+ -+#define INTG_MAX_NUM_OF_CORES 24 -+ -+ -+/**************************************************************************//** -+ @Description Module types. -+*//***************************************************************************/ -+typedef enum e_ModuleId -+{ -+ e_MODULE_ID_DUART_1 = 0, -+ e_MODULE_ID_DUART_2, -+ e_MODULE_ID_DUART_3, -+ e_MODULE_ID_DUART_4, -+ e_MODULE_ID_LAW, -+ e_MODULE_ID_IFC, -+ e_MODULE_ID_PAMU, -+ e_MODULE_ID_QM, /**< Queue manager module */ -+ e_MODULE_ID_BM, /**< Buffer manager module */ -+ e_MODULE_ID_QM_CE_PORTAL_0, -+ e_MODULE_ID_QM_CI_PORTAL_0, -+ e_MODULE_ID_QM_CE_PORTAL_1, -+ e_MODULE_ID_QM_CI_PORTAL_1, -+ e_MODULE_ID_QM_CE_PORTAL_2, -+ e_MODULE_ID_QM_CI_PORTAL_2, -+ e_MODULE_ID_QM_CE_PORTAL_3, -+ e_MODULE_ID_QM_CI_PORTAL_3, -+ e_MODULE_ID_QM_CE_PORTAL_4, -+ e_MODULE_ID_QM_CI_PORTAL_4, -+ e_MODULE_ID_QM_CE_PORTAL_5, -+ e_MODULE_ID_QM_CI_PORTAL_5, -+ e_MODULE_ID_QM_CE_PORTAL_6, -+ e_MODULE_ID_QM_CI_PORTAL_6, -+ e_MODULE_ID_QM_CE_PORTAL_7, -+ e_MODULE_ID_QM_CI_PORTAL_7, -+ e_MODULE_ID_QM_CE_PORTAL_8, -+ e_MODULE_ID_QM_CI_PORTAL_8, -+ e_MODULE_ID_QM_CE_PORTAL_9, -+ e_MODULE_ID_QM_CI_PORTAL_9, -+ e_MODULE_ID_BM_CE_PORTAL_0, -+ e_MODULE_ID_BM_CI_PORTAL_0, -+ e_MODULE_ID_BM_CE_PORTAL_1, -+ e_MODULE_ID_BM_CI_PORTAL_1, -+ e_MODULE_ID_BM_CE_PORTAL_2, -+ e_MODULE_ID_BM_CI_PORTAL_2, -+ e_MODULE_ID_BM_CE_PORTAL_3, -+ e_MODULE_ID_BM_CI_PORTAL_3, -+ e_MODULE_ID_BM_CE_PORTAL_4, -+ e_MODULE_ID_BM_CI_PORTAL_4, -+ e_MODULE_ID_BM_CE_PORTAL_5, -+ e_MODULE_ID_BM_CI_PORTAL_5, -+ e_MODULE_ID_BM_CE_PORTAL_6, -+ e_MODULE_ID_BM_CI_PORTAL_6, -+ e_MODULE_ID_BM_CE_PORTAL_7, -+ e_MODULE_ID_BM_CI_PORTAL_7, -+ e_MODULE_ID_BM_CE_PORTAL_8, -+ e_MODULE_ID_BM_CI_PORTAL_8, -+ e_MODULE_ID_BM_CE_PORTAL_9, -+ e_MODULE_ID_BM_CI_PORTAL_9, -+ e_MODULE_ID_FM, /**< Frame manager module */ -+ e_MODULE_ID_FM_RTC, /**< FM Real-Time-Clock */ -+ e_MODULE_ID_FM_MURAM, /**< FM Multi-User-RAM */ -+ e_MODULE_ID_FM_BMI, /**< FM BMI block */ -+ e_MODULE_ID_FM_QMI, /**< FM QMI block */ -+ e_MODULE_ID_FM_PARSER, /**< FM parser block */ -+ e_MODULE_ID_FM_PORT_HO1, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO2, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO3, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO4, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO5, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO6, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO7, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_1GRx1, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx2, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx3, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx4, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx5, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx6, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_10GRx1, /**< FM Rx 10G MAC port block */ -+ e_MODULE_ID_FM_PORT_10GRx2, /**< FM Rx 10G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx1, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx2, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx3, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx4, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx5, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx6, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_10GTx1, /**< FM Tx 10G MAC port block */ -+ e_MODULE_ID_FM_PORT_10GTx2, /**< FM Tx 10G MAC port block */ -+ e_MODULE_ID_FM_PLCR, /**< FM Policer */ -+ e_MODULE_ID_FM_KG, /**< FM Keygen */ -+ e_MODULE_ID_FM_DMA, /**< FM DMA */ -+ e_MODULE_ID_FM_FPM, /**< FM FPM */ -+ e_MODULE_ID_FM_IRAM, /**< FM Instruction-RAM */ -+ e_MODULE_ID_FM_1GMDIO, /**< FM 1G MDIO MAC */ -+ e_MODULE_ID_FM_10GMDIO, /**< FM 10G MDIO */ -+ e_MODULE_ID_FM_PRS_IRAM, /**< FM SW-parser Instruction-RAM */ -+ e_MODULE_ID_FM_1GMAC1, /**< FM 1G MAC #1 */ -+ e_MODULE_ID_FM_1GMAC2, /**< FM 1G MAC #2 */ -+ e_MODULE_ID_FM_1GMAC3, /**< FM 1G MAC #3 */ -+ e_MODULE_ID_FM_1GMAC4, /**< FM 1G MAC #4 */ -+ e_MODULE_ID_FM_1GMAC5, /**< FM 1G MAC #5 */ -+ e_MODULE_ID_FM_1GMAC6, /**< FM 1G MAC #6 */ -+ e_MODULE_ID_FM_10GMAC1, /**< FM 10G MAC */ -+ e_MODULE_ID_FM_10GMAC2, /**< FM 10G MAC */ -+ -+ e_MODULE_ID_SEC_GEN, /**< SEC 4.0 General registers */ -+ e_MODULE_ID_SEC_QI, /**< SEC 4.0 QI registers */ -+ e_MODULE_ID_SEC_JQ0, /**< SEC 4.0 JQ-0 registers */ -+ e_MODULE_ID_SEC_JQ1, /**< SEC 4.0 JQ-1 registers */ -+ e_MODULE_ID_SEC_JQ2, /**< SEC 4.0 JQ-2 registers */ -+ e_MODULE_ID_SEC_JQ3, /**< SEC 4.0 JQ-3 registers */ -+ e_MODULE_ID_SEC_RTIC, /**< SEC 4.0 RTIC registers */ -+ e_MODULE_ID_SEC_DECO0_CCB0, /**< SEC 4.0 DECO-0/CCB-0 registers */ -+ e_MODULE_ID_SEC_DECO1_CCB1, /**< SEC 4.0 DECO-1/CCB-1 registers */ -+ e_MODULE_ID_SEC_DECO2_CCB2, /**< SEC 4.0 DECO-2/CCB-2 registers */ -+ e_MODULE_ID_SEC_DECO3_CCB3, /**< SEC 4.0 DECO-3/CCB-3 registers */ -+ e_MODULE_ID_SEC_DECO4_CCB4, /**< SEC 4.0 DECO-4/CCB-4 registers */ -+ -+ e_MODULE_ID_PIC, /**< PIC */ -+ e_MODULE_ID_GPIO, /**< GPIO */ -+ e_MODULE_ID_SERDES, /**< SERDES */ -+ e_MODULE_ID_CPC_1, /**< CoreNet-Platform-Cache 1 */ -+ e_MODULE_ID_CPC_2, /**< CoreNet-Platform-Cache 2 */ -+ -+ e_MODULE_ID_SRIO_PORTS, /**< RapidIO controller */ -+ -+ e_MODULE_ID_DUMMY_LAST -+} e_ModuleId; -+ -+#define NUM_OF_MODULES e_MODULE_ID_DUMMY_LAST -+ -+#if 0 /* using unified values */ -+/***************************************************************************** -+ INTEGRATION-SPECIFIC MODULE CODES -+******************************************************************************/ -+#define MODULE_UNKNOWN 0x00000000 -+#define MODULE_MEM 0x00010000 -+#define MODULE_MM 0x00020000 -+#define MODULE_CORE 0x00030000 -+#define MODULE_T4240 0x00040000 -+#define MODULE_T4240_PLATFORM 0x00050000 -+#define MODULE_PM 0x00060000 -+#define MODULE_MMU 0x00070000 -+#define MODULE_PIC 0x00080000 -+#define MODULE_CPC 0x00090000 -+#define MODULE_DUART 0x000a0000 -+#define MODULE_SERDES 0x000b0000 -+#define MODULE_PIO 0x000c0000 -+#define MODULE_QM 0x000d0000 -+#define MODULE_BM 0x000e0000 -+#define MODULE_SEC 0x000f0000 -+#define MODULE_LAW 0x00100000 -+#define MODULE_LBC 0x00110000 -+#define MODULE_PAMU 0x00120000 -+#define MODULE_FM 0x00130000 -+#define MODULE_FM_MURAM 0x00140000 -+#define MODULE_FM_PCD 0x00150000 -+#define MODULE_FM_RTC 0x00160000 -+#define MODULE_FM_MAC 0x00170000 -+#define MODULE_FM_PORT 0x00180000 -+#define MODULE_FM_SP 0x00190000 -+#define MODULE_DPA_PORT 0x001a0000 -+#define MODULE_MII 0x001b0000 -+#define MODULE_I2C 0x001c0000 -+#define MODULE_DMA 0x001d0000 -+#define MODULE_DDR 0x001e0000 -+#define MODULE_ESPI 0x001f0000 -+#define MODULE_DPAA_IPSEC 0x00200000 -+#endif /* using unified values */ -+ -+/***************************************************************************** -+ PAMU INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define PAMU_NUM_OF_PARTITIONS 4 -+ -+/***************************************************************************** -+ LAW INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define LAW_NUM_OF_WINDOWS 32 -+#define LAW_MIN_WINDOW_SIZE 0x0000000000001000LL /**< 4 Kbytes */ -+#define LAW_MAX_WINDOW_SIZE 0x0000010000000000LL /**< 1 Tbytes for 40-bit address space */ -+ -+ -+/***************************************************************************** -+ LBC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+/**************************************************************************//** -+ @Group lbc_exception_grp LBC Exception Unit -+ -+ @Description LBC Exception unit API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Anchor lbc_exbm -+ -+ @Collection LBC Errors Bit Mask -+ -+ These errors are reported through the exceptions callback.. -+ The values can be or'ed in any combination in the errors mask -+ parameter of the errors report structure. -+ -+ These errors can also be passed as a bit-mask to -+ LBC_EnableErrorChecking() or LBC_DisableErrorChecking(), -+ for enabling or disabling error checking. -+ @{ -+*//***************************************************************************/ -+#define LBC_ERR_BUS_MONITOR 0x80000000 /**< Bus monitor error */ -+#define LBC_ERR_PARITY_ECC 0x20000000 /**< Parity error for GPCM/UPM */ -+#define LBC_ERR_WRITE_PROTECT 0x04000000 /**< Write protection error */ -+#define LBC_ERR_CHIP_SELECT 0x00080000 /**< Unrecognized chip select */ -+ -+#define LBC_ERR_ALL (LBC_ERR_BUS_MONITOR | LBC_ERR_PARITY_ECC | \ -+ LBC_ERR_WRITE_PROTECT | LBC_ERR_CHIP_SELECT) -+ /**< All possible errors */ -+/* @} */ -+/** @} */ /* end of lbc_exception_grp group */ -+ -+#define LBC_INCORRECT_ERROR_REPORT_ERRATA -+ -+#define LBC_NUM_OF_BANKS 8 -+#define LBC_MAX_CS_SIZE 0x0000000100000000LL /* Up to 4G memory block size */ -+#define LBC_PARITY_SUPPORT -+#define LBC_ADDRESS_HOLD_TIME_CTRL -+#define LBC_HIGH_CLK_DIVIDERS -+#define LBC_FCM_AVAILABLE -+ -+/***************************************************************************** -+ GPIO INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define GPIO_PORT_OFFSET_0x1000 -+ -+#define GPIO_NUM_OF_PORTS 3 /**< Number of ports in GPIO module; -+ Each port contains up to 32 I/O pins. */ -+ -+#define GPIO_VALID_PIN_MASKS \ -+ { /* Port A */ 0xFFFFFFFF, \ -+ /* Port B */ 0xFFFFFFFF, \ -+ /* Port C */ 0xFFFFFFFF } -+ -+#define GPIO_VALID_INTR_MASKS \ -+ { /* Port A */ 0xFFFFFFFF, \ -+ /* Port B */ 0xFFFFFFFF, \ -+ /* Port C */ 0xFFFFFFFF } -+ -+ -+ -+#endif /* __PART_INTEGRATION_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3L/dpaa_integration_ext.h -@@ -0,0 +1,292 @@ -+/* -+ * Copyright 2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/** -+ -+ @File dpaa_integration_ext.h -+ -+ @Description T4240 FM external definitions and structures. -+*//***************************************************************************/ -+#ifndef __DPAA_INTEGRATION_EXT_H -+#define __DPAA_INTEGRATION_EXT_H -+ -+#include "std_ext.h" -+ -+ -+#define DPAA_VERSION 11 -+ -+/**************************************************************************//** -+ @Description DPAA SW Portals Enumeration. -+*//***************************************************************************/ -+typedef enum -+{ -+ e_DPAA_SWPORTAL0 = 0, -+ e_DPAA_SWPORTAL1, -+ e_DPAA_SWPORTAL2, -+ e_DPAA_SWPORTAL3, -+ e_DPAA_SWPORTAL4, -+ e_DPAA_SWPORTAL5, -+ e_DPAA_SWPORTAL6, -+ e_DPAA_SWPORTAL7, -+ e_DPAA_SWPORTAL8, -+ e_DPAA_SWPORTAL9, -+ e_DPAA_SWPORTAL10, -+ e_DPAA_SWPORTAL11, -+ e_DPAA_SWPORTAL12, -+ e_DPAA_SWPORTAL13, -+ e_DPAA_SWPORTAL14, -+ e_DPAA_SWPORTAL15, -+ e_DPAA_SWPORTAL16, -+ e_DPAA_SWPORTAL17, -+ e_DPAA_SWPORTAL18, -+ e_DPAA_SWPORTAL19, -+ e_DPAA_SWPORTAL20, -+ e_DPAA_SWPORTAL21, -+ e_DPAA_SWPORTAL22, -+ e_DPAA_SWPORTAL23, -+ e_DPAA_SWPORTAL24, -+ e_DPAA_SWPORTAL_DUMMY_LAST -+} e_DpaaSwPortal; -+ -+/**************************************************************************//** -+ @Description DPAA Direct Connect Portals Enumeration. -+*//***************************************************************************/ -+typedef enum -+{ -+ e_DPAA_DCPORTAL0 = 0, -+ e_DPAA_DCPORTAL1, -+ e_DPAA_DCPORTAL2, -+ e_DPAA_DCPORTAL_DUMMY_LAST -+} e_DpaaDcPortal; -+ -+#define DPAA_MAX_NUM_OF_SW_PORTALS e_DPAA_SWPORTAL_DUMMY_LAST -+#define DPAA_MAX_NUM_OF_DC_PORTALS e_DPAA_DCPORTAL_DUMMY_LAST -+ -+/***************************************************************************** -+ QMan INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define QM_MAX_NUM_OF_POOL_CHANNELS 15 /**< Total number of channels, dedicated and pool */ -+#define QM_MAX_NUM_OF_WQ 8 /**< Number of work queues per channel */ -+#define QM_MAX_NUM_OF_CGS 256 /**< Congestion groups number */ -+#define QM_MAX_NUM_OF_FQIDS (16 * MEGABYTE) -+ /**< FQIDs range - 24 bits */ -+ -+/**************************************************************************//** -+ @Description Work Queue Channel assignments in QMan. -+*//***************************************************************************/ -+typedef enum -+{ -+ e_QM_FQ_CHANNEL_SWPORTAL0 = 0x0, /**< Dedicated channels serviced by software portals 0 to 24 */ -+ e_QM_FQ_CHANNEL_SWPORTAL1, -+ e_QM_FQ_CHANNEL_SWPORTAL2, -+ e_QM_FQ_CHANNEL_SWPORTAL3, -+ e_QM_FQ_CHANNEL_SWPORTAL4, -+ e_QM_FQ_CHANNEL_SWPORTAL5, -+ e_QM_FQ_CHANNEL_SWPORTAL6, -+ e_QM_FQ_CHANNEL_SWPORTAL7, -+ e_QM_FQ_CHANNEL_SWPORTAL8, -+ e_QM_FQ_CHANNEL_SWPORTAL9, -+ e_QM_FQ_CHANNEL_SWPORTAL10, -+ e_QM_FQ_CHANNEL_SWPORTAL11, -+ e_QM_FQ_CHANNEL_SWPORTAL12, -+ e_QM_FQ_CHANNEL_SWPORTAL13, -+ e_QM_FQ_CHANNEL_SWPORTAL14, -+ e_QM_FQ_CHANNEL_SWPORTAL15, -+ e_QM_FQ_CHANNEL_SWPORTAL16, -+ e_QM_FQ_CHANNEL_SWPORTAL17, -+ e_QM_FQ_CHANNEL_SWPORTAL18, -+ e_QM_FQ_CHANNEL_SWPORTAL19, -+ e_QM_FQ_CHANNEL_SWPORTAL20, -+ e_QM_FQ_CHANNEL_SWPORTAL21, -+ e_QM_FQ_CHANNEL_SWPORTAL22, -+ e_QM_FQ_CHANNEL_SWPORTAL23, -+ e_QM_FQ_CHANNEL_SWPORTAL24, -+ -+ e_QM_FQ_CHANNEL_POOL1 = 0x401, /**< Pool channels that can be serviced by any of the software portals */ -+ e_QM_FQ_CHANNEL_POOL2, -+ e_QM_FQ_CHANNEL_POOL3, -+ e_QM_FQ_CHANNEL_POOL4, -+ e_QM_FQ_CHANNEL_POOL5, -+ e_QM_FQ_CHANNEL_POOL6, -+ e_QM_FQ_CHANNEL_POOL7, -+ e_QM_FQ_CHANNEL_POOL8, -+ e_QM_FQ_CHANNEL_POOL9, -+ e_QM_FQ_CHANNEL_POOL10, -+ e_QM_FQ_CHANNEL_POOL11, -+ e_QM_FQ_CHANNEL_POOL12, -+ e_QM_FQ_CHANNEL_POOL13, -+ e_QM_FQ_CHANNEL_POOL14, -+ e_QM_FQ_CHANNEL_POOL15, -+ -+ e_QM_FQ_CHANNEL_FMAN0_SP0 = 0x800, /**< Dedicated channels serviced by Direct Connect Portal 0: -+ connected to FMan 0; assigned in incrementing order to -+ each sub-portal (SP) in the portal */ -+ e_QM_FQ_CHANNEL_FMAN0_SP1, -+ e_QM_FQ_CHANNEL_FMAN0_SP2, -+ e_QM_FQ_CHANNEL_FMAN0_SP3, -+ e_QM_FQ_CHANNEL_FMAN0_SP4, -+ e_QM_FQ_CHANNEL_FMAN0_SP5, -+ e_QM_FQ_CHANNEL_FMAN0_SP6, -+ e_QM_FQ_CHANNEL_FMAN0_SP7, -+ e_QM_FQ_CHANNEL_FMAN0_SP8, -+ e_QM_FQ_CHANNEL_FMAN0_SP9, -+ e_QM_FQ_CHANNEL_FMAN0_SP10, -+ e_QM_FQ_CHANNEL_FMAN0_SP11, -+ e_QM_FQ_CHANNEL_FMAN0_SP12, -+ e_QM_FQ_CHANNEL_FMAN0_SP13, -+ e_QM_FQ_CHANNEL_FMAN0_SP14, -+ e_QM_FQ_CHANNEL_FMAN0_SP15, -+ -+ e_QM_FQ_CHANNEL_RMAN_SP0 = 0x820, /**< Dedicated channels serviced by Direct Connect Portal 1: connected to RMan */ -+ e_QM_FQ_CHANNEL_RMAN_SP1, -+ -+ e_QM_FQ_CHANNEL_CAAM = 0x840 /**< Dedicated channel serviced by Direct Connect Portal 2: -+ connected to SEC */ -+} e_QmFQChannel; -+ -+/***************************************************************************** -+ BMan INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define BM_MAX_NUM_OF_POOLS 64 /**< Number of buffers pools */ -+ -+/***************************************************************************** -+ SEC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define SEC_NUM_OF_DECOS 3 -+#define SEC_ALL_DECOS_MASK 0x00000003 -+ -+ -+/***************************************************************************** -+ FM INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define INTG_MAX_NUM_OF_FM 1 -+/* Ports defines */ -+#define FM_MAX_NUM_OF_1G_MACS 5 -+#define FM_MAX_NUM_OF_10G_MACS 1 -+#define FM_MAX_NUM_OF_MACS (FM_MAX_NUM_OF_1G_MACS + FM_MAX_NUM_OF_10G_MACS) -+#define FM_MAX_NUM_OF_OH_PORTS 4 -+ -+#define FM_MAX_NUM_OF_1G_RX_PORTS FM_MAX_NUM_OF_1G_MACS -+#define FM_MAX_NUM_OF_10G_RX_PORTS FM_MAX_NUM_OF_10G_MACS -+#define FM_MAX_NUM_OF_RX_PORTS (FM_MAX_NUM_OF_10G_RX_PORTS + FM_MAX_NUM_OF_1G_RX_PORTS) -+ -+#define FM_MAX_NUM_OF_1G_TX_PORTS FM_MAX_NUM_OF_1G_MACS -+#define FM_MAX_NUM_OF_10G_TX_PORTS FM_MAX_NUM_OF_10G_MACS -+#define FM_MAX_NUM_OF_TX_PORTS (FM_MAX_NUM_OF_10G_TX_PORTS + FM_MAX_NUM_OF_1G_TX_PORTS) -+ -+#define FM_MAX_NUM_OF_MACSECS 1 /* Should be updated */ -+ -+#define FM_PORT_MAX_NUM_OF_EXT_POOLS 4 /**< Number of external BM pools per Rx port */ -+#define FM_PORT_NUM_OF_CONGESTION_GRPS 256 /**< Total number of congestion groups in QM */ -+#define FM_MAX_NUM_OF_SUB_PORTALS 16 -+#define FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS 0 -+ -+#define FM_VSP_MAX_NUM_OF_ENTRIES 32 -+#define FM_MAX_NUM_OF_PFC_PRIORITIES 8 -+ -+/* RAMs defines */ -+#define FM_MURAM_SIZE (192 * KILOBYTE) -+#define FM_IRAM_SIZE(major, minor) \ -+ (((major == 6) && ((minor == 4) )) ? (64 * KILOBYTE) : (32 * KILOBYTE)) -+#define FM_NUM_OF_CTRL 2 -+ -+/* PCD defines */ -+#define FM_PCD_PLCR_NUM_ENTRIES 256 /**< Total number of policer profiles */ -+#define FM_PCD_KG_NUM_OF_SCHEMES 32 /**< Total number of KG schemes */ -+#define FM_PCD_MAX_NUM_OF_CLS_PLANS 256 /**< Number of classification plan entries. */ -+#define FM_PCD_PRS_SW_PATCHES_SIZE 0x00000600 /**< Number of bytes saved for patches */ -+#define FM_PCD_SW_PRS_SIZE 0x00000800 /**< Total size of SW parser area */ -+ -+/* RTC defines */ -+#define FM_RTC_NUM_OF_ALARMS 2 /**< RTC number of alarms */ -+#define FM_RTC_NUM_OF_PERIODIC_PULSES 3 /**< RTC number of periodic pulses */ -+#define FM_RTC_NUM_OF_EXT_TRIGGERS 2 /**< RTC number of external triggers */ -+ -+/* QMI defines */ -+#define QMI_MAX_NUM_OF_TNUMS 64 -+#define QMI_DEF_TNUMS_THRESH 32 -+/* FPM defines */ -+#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4 -+ -+/* DMA defines */ -+#define DMA_THRESH_MAX_COMMQ 83 -+#define DMA_THRESH_MAX_BUF 127 -+ -+/* BMI defines */ -+#define BMI_MAX_NUM_OF_TASKS 64 -+#define BMI_MAX_NUM_OF_DMAS 32 -+ -+#define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE) -+#define PORT_MAX_WEIGHT 16 -+ -+#define FM_CHECK_PORT_RESTRICTIONS(__validPorts, __newPortIndx) TRUE -+ -+/* Unique T4240 */ -+#define FM_OP_OPEN_DMA_MIN_LIMIT -+#define FM_NO_RESTRICT_ON_ACCESS_RSRC -+#define FM_NO_OP_OBSERVED_POOLS -+#define FM_FRAME_END_PARAMS_FOR_OP -+#define FM_DEQ_PIPELINE_PARAMS_FOR_OP -+#define FM_QMI_NO_SINGLE_ECC_EXCEPTION -+ -+#define FM_NO_GUARANTEED_RESET_VALUES -+ -+/* FM errata */ -+#define FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 -+#define FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 -+#define FM_OP_NO_VSP_NO_RELEASE_ERRATA_FMAN_A006675 -+#define FM_HEAVY_TRAFFIC_SEQUENCER_HANG_ERRATA_FMAN_A006981 -+ -+#define FM_BCB_ERRATA_BMI_SW001 -+#define FM_LEN_CHECK_ERRATA_FMAN_SW002 -+#define FM_AID_MODE_NO_TNUM_SW005 /* refer to pdm TKT068794 - only support of port_id on aid */ -+#define FM_ERROR_VSP_NO_MATCH_SW006 /* refer to pdm TKT174304 - no match between errorQ and VSP */ -+ -+/***************************************************************************** -+ RMan INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define RM_MAX_NUM_OF_IB 4 /**< Number of inbound blocks */ -+#define RM_NUM_OF_IBCU 8 /**< NUmber of classification units in an inbound block */ -+ -+/* RMan erratas */ -+#define RM_ERRONEOUS_ACK_ERRATA_RMAN_A006756 -+ -+/***************************************************************************** -+ FM MACSEC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define NUM_OF_RX_SC 16 -+#define NUM_OF_TX_SC 16 -+ -+#define NUM_OF_SA_PER_RX_SC 2 -+#define NUM_OF_SA_PER_TX_SC 2 -+ -+#endif /* __DPAA_INTEGRATION_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3L/part_ext.h -@@ -0,0 +1,59 @@ -+/* -+ * Copyright 2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ -+ @File part_ext.h -+ -+ @Description Definitions for the part (integration) module. -+*//***************************************************************************/ -+ -+#ifndef __PART_EXT_H -+#define __PART_EXT_H -+ -+#include "std_ext.h" -+#include "part_integration_ext.h" -+ -+/**************************************************************************//* -+ @Description Part data structure - must be contained in any integration -+ data structure. -+*//***************************************************************************/ -+typedef struct t_Part -+{ -+ uintptr_t (* f_GetModuleBase)(t_Handle h_Part, e_ModuleId moduleId); -+ /**< Returns the address of the module's memory map base. */ -+ e_ModuleId (* f_GetModuleIdByBase)(t_Handle h_Part, uintptr_t baseAddress); -+ /**< Returns the module's ID according to its memory map base. */ -+} t_Part; -+ -+ -+#endif /* __PART_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/FMANV3L/part_integration_ext.h -@@ -0,0 +1,304 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/** -+ -+ @File part_integration_ext.h -+ -+ @Description T4240 external definitions and structures. -+*//***************************************************************************/ -+#ifndef __PART_INTEGRATION_EXT_H -+#define __PART_INTEGRATION_EXT_H -+ -+#include "std_ext.h" -+#include "ddr_std_ext.h" -+#include "enet_ext.h" -+#include "dpaa_integration_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group T4240_chip_id T4240 Application Programming Interface -+ -+ @Description T4240 Chip functions,definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+#define CORE_E6500 -+ -+#define INTG_MAX_NUM_OF_CORES 24 -+ -+ -+/**************************************************************************//** -+ @Description Module types. -+*//***************************************************************************/ -+typedef enum e_ModuleId -+{ -+ e_MODULE_ID_DUART_1 = 0, -+ e_MODULE_ID_DUART_2, -+ e_MODULE_ID_DUART_3, -+ e_MODULE_ID_DUART_4, -+ e_MODULE_ID_LAW, -+ e_MODULE_ID_IFC, -+ e_MODULE_ID_PAMU, -+ e_MODULE_ID_QM, /**< Queue manager module */ -+ e_MODULE_ID_BM, /**< Buffer manager module */ -+ e_MODULE_ID_QM_CE_PORTAL_0, -+ e_MODULE_ID_QM_CI_PORTAL_0, -+ e_MODULE_ID_QM_CE_PORTAL_1, -+ e_MODULE_ID_QM_CI_PORTAL_1, -+ e_MODULE_ID_QM_CE_PORTAL_2, -+ e_MODULE_ID_QM_CI_PORTAL_2, -+ e_MODULE_ID_QM_CE_PORTAL_3, -+ e_MODULE_ID_QM_CI_PORTAL_3, -+ e_MODULE_ID_QM_CE_PORTAL_4, -+ e_MODULE_ID_QM_CI_PORTAL_4, -+ e_MODULE_ID_QM_CE_PORTAL_5, -+ e_MODULE_ID_QM_CI_PORTAL_5, -+ e_MODULE_ID_QM_CE_PORTAL_6, -+ e_MODULE_ID_QM_CI_PORTAL_6, -+ e_MODULE_ID_QM_CE_PORTAL_7, -+ e_MODULE_ID_QM_CI_PORTAL_7, -+ e_MODULE_ID_QM_CE_PORTAL_8, -+ e_MODULE_ID_QM_CI_PORTAL_8, -+ e_MODULE_ID_QM_CE_PORTAL_9, -+ e_MODULE_ID_QM_CI_PORTAL_9, -+ e_MODULE_ID_BM_CE_PORTAL_0, -+ e_MODULE_ID_BM_CI_PORTAL_0, -+ e_MODULE_ID_BM_CE_PORTAL_1, -+ e_MODULE_ID_BM_CI_PORTAL_1, -+ e_MODULE_ID_BM_CE_PORTAL_2, -+ e_MODULE_ID_BM_CI_PORTAL_2, -+ e_MODULE_ID_BM_CE_PORTAL_3, -+ e_MODULE_ID_BM_CI_PORTAL_3, -+ e_MODULE_ID_BM_CE_PORTAL_4, -+ e_MODULE_ID_BM_CI_PORTAL_4, -+ e_MODULE_ID_BM_CE_PORTAL_5, -+ e_MODULE_ID_BM_CI_PORTAL_5, -+ e_MODULE_ID_BM_CE_PORTAL_6, -+ e_MODULE_ID_BM_CI_PORTAL_6, -+ e_MODULE_ID_BM_CE_PORTAL_7, -+ e_MODULE_ID_BM_CI_PORTAL_7, -+ e_MODULE_ID_BM_CE_PORTAL_8, -+ e_MODULE_ID_BM_CI_PORTAL_8, -+ e_MODULE_ID_BM_CE_PORTAL_9, -+ e_MODULE_ID_BM_CI_PORTAL_9, -+ e_MODULE_ID_FM, /**< Frame manager module */ -+ e_MODULE_ID_FM_RTC, /**< FM Real-Time-Clock */ -+ e_MODULE_ID_FM_MURAM, /**< FM Multi-User-RAM */ -+ e_MODULE_ID_FM_BMI, /**< FM BMI block */ -+ e_MODULE_ID_FM_QMI, /**< FM QMI block */ -+ e_MODULE_ID_FM_PARSER, /**< FM parser block */ -+ e_MODULE_ID_FM_PORT_HO1, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO2, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO3, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO4, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO5, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO6, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO7, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_1GRx1, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx2, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx3, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx4, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx5, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx6, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_10GRx1, /**< FM Rx 10G MAC port block */ -+ e_MODULE_ID_FM_PORT_10GRx2, /**< FM Rx 10G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx1, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx2, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx3, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx4, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx5, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx6, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_10GTx1, /**< FM Tx 10G MAC port block */ -+ e_MODULE_ID_FM_PORT_10GTx2, /**< FM Tx 10G MAC port block */ -+ e_MODULE_ID_FM_PLCR, /**< FM Policer */ -+ e_MODULE_ID_FM_KG, /**< FM Keygen */ -+ e_MODULE_ID_FM_DMA, /**< FM DMA */ -+ e_MODULE_ID_FM_FPM, /**< FM FPM */ -+ e_MODULE_ID_FM_IRAM, /**< FM Instruction-RAM */ -+ e_MODULE_ID_FM_1GMDIO, /**< FM 1G MDIO MAC */ -+ e_MODULE_ID_FM_10GMDIO, /**< FM 10G MDIO */ -+ e_MODULE_ID_FM_PRS_IRAM, /**< FM SW-parser Instruction-RAM */ -+ e_MODULE_ID_FM_1GMAC1, /**< FM 1G MAC #1 */ -+ e_MODULE_ID_FM_1GMAC2, /**< FM 1G MAC #2 */ -+ e_MODULE_ID_FM_1GMAC3, /**< FM 1G MAC #3 */ -+ e_MODULE_ID_FM_1GMAC4, /**< FM 1G MAC #4 */ -+ e_MODULE_ID_FM_1GMAC5, /**< FM 1G MAC #5 */ -+ e_MODULE_ID_FM_1GMAC6, /**< FM 1G MAC #6 */ -+ e_MODULE_ID_FM_10GMAC1, /**< FM 10G MAC */ -+ e_MODULE_ID_FM_10GMAC2, /**< FM 10G MAC */ -+ -+ e_MODULE_ID_SEC_GEN, /**< SEC 4.0 General registers */ -+ e_MODULE_ID_SEC_QI, /**< SEC 4.0 QI registers */ -+ e_MODULE_ID_SEC_JQ0, /**< SEC 4.0 JQ-0 registers */ -+ e_MODULE_ID_SEC_JQ1, /**< SEC 4.0 JQ-1 registers */ -+ e_MODULE_ID_SEC_JQ2, /**< SEC 4.0 JQ-2 registers */ -+ e_MODULE_ID_SEC_JQ3, /**< SEC 4.0 JQ-3 registers */ -+ e_MODULE_ID_SEC_RTIC, /**< SEC 4.0 RTIC registers */ -+ e_MODULE_ID_SEC_DECO0_CCB0, /**< SEC 4.0 DECO-0/CCB-0 registers */ -+ e_MODULE_ID_SEC_DECO1_CCB1, /**< SEC 4.0 DECO-1/CCB-1 registers */ -+ e_MODULE_ID_SEC_DECO2_CCB2, /**< SEC 4.0 DECO-2/CCB-2 registers */ -+ e_MODULE_ID_SEC_DECO3_CCB3, /**< SEC 4.0 DECO-3/CCB-3 registers */ -+ e_MODULE_ID_SEC_DECO4_CCB4, /**< SEC 4.0 DECO-4/CCB-4 registers */ -+ -+ e_MODULE_ID_PIC, /**< PIC */ -+ e_MODULE_ID_GPIO, /**< GPIO */ -+ e_MODULE_ID_SERDES, /**< SERDES */ -+ e_MODULE_ID_CPC_1, /**< CoreNet-Platform-Cache 1 */ -+ e_MODULE_ID_CPC_2, /**< CoreNet-Platform-Cache 2 */ -+ -+ e_MODULE_ID_SRIO_PORTS, /**< RapidIO controller */ -+ -+ e_MODULE_ID_DUMMY_LAST -+} e_ModuleId; -+ -+#define NUM_OF_MODULES e_MODULE_ID_DUMMY_LAST -+ -+#if 0 /* using unified values */ -+/***************************************************************************** -+ INTEGRATION-SPECIFIC MODULE CODES -+******************************************************************************/ -+#define MODULE_UNKNOWN 0x00000000 -+#define MODULE_MEM 0x00010000 -+#define MODULE_MM 0x00020000 -+#define MODULE_CORE 0x00030000 -+#define MODULE_T4240 0x00040000 -+#define MODULE_T4240_PLATFORM 0x00050000 -+#define MODULE_PM 0x00060000 -+#define MODULE_MMU 0x00070000 -+#define MODULE_PIC 0x00080000 -+#define MODULE_CPC 0x00090000 -+#define MODULE_DUART 0x000a0000 -+#define MODULE_SERDES 0x000b0000 -+#define MODULE_PIO 0x000c0000 -+#define MODULE_QM 0x000d0000 -+#define MODULE_BM 0x000e0000 -+#define MODULE_SEC 0x000f0000 -+#define MODULE_LAW 0x00100000 -+#define MODULE_LBC 0x00110000 -+#define MODULE_PAMU 0x00120000 -+#define MODULE_FM 0x00130000 -+#define MODULE_FM_MURAM 0x00140000 -+#define MODULE_FM_PCD 0x00150000 -+#define MODULE_FM_RTC 0x00160000 -+#define MODULE_FM_MAC 0x00170000 -+#define MODULE_FM_PORT 0x00180000 -+#define MODULE_FM_SP 0x00190000 -+#define MODULE_DPA_PORT 0x001a0000 -+#define MODULE_MII 0x001b0000 -+#define MODULE_I2C 0x001c0000 -+#define MODULE_DMA 0x001d0000 -+#define MODULE_DDR 0x001e0000 -+#define MODULE_ESPI 0x001f0000 -+#define MODULE_DPAA_IPSEC 0x00200000 -+#endif /* using unified values */ -+ -+/***************************************************************************** -+ PAMU INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define PAMU_NUM_OF_PARTITIONS 4 -+ -+/***************************************************************************** -+ LAW INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define LAW_NUM_OF_WINDOWS 32 -+#define LAW_MIN_WINDOW_SIZE 0x0000000000001000LL /**< 4 Kbytes */ -+#define LAW_MAX_WINDOW_SIZE 0x0000010000000000LL /**< 1 Tbytes for 40-bit address space */ -+ -+ -+/***************************************************************************** -+ LBC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+/**************************************************************************//** -+ @Group lbc_exception_grp LBC Exception Unit -+ -+ @Description LBC Exception unit API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Anchor lbc_exbm -+ -+ @Collection LBC Errors Bit Mask -+ -+ These errors are reported through the exceptions callback.. -+ The values can be or'ed in any combination in the errors mask -+ parameter of the errors report structure. -+ -+ These errors can also be passed as a bit-mask to -+ LBC_EnableErrorChecking() or LBC_DisableErrorChecking(), -+ for enabling or disabling error checking. -+ @{ -+*//***************************************************************************/ -+#define LBC_ERR_BUS_MONITOR 0x80000000 /**< Bus monitor error */ -+#define LBC_ERR_PARITY_ECC 0x20000000 /**< Parity error for GPCM/UPM */ -+#define LBC_ERR_WRITE_PROTECT 0x04000000 /**< Write protection error */ -+#define LBC_ERR_CHIP_SELECT 0x00080000 /**< Unrecognized chip select */ -+ -+#define LBC_ERR_ALL (LBC_ERR_BUS_MONITOR | LBC_ERR_PARITY_ECC | \ -+ LBC_ERR_WRITE_PROTECT | LBC_ERR_CHIP_SELECT) -+ /**< All possible errors */ -+/* @} */ -+/** @} */ /* end of lbc_exception_grp group */ -+ -+#define LBC_INCORRECT_ERROR_REPORT_ERRATA -+ -+#define LBC_NUM_OF_BANKS 8 -+#define LBC_MAX_CS_SIZE 0x0000000100000000LL /* Up to 4G memory block size */ -+#define LBC_PARITY_SUPPORT -+#define LBC_ADDRESS_HOLD_TIME_CTRL -+#define LBC_HIGH_CLK_DIVIDERS -+#define LBC_FCM_AVAILABLE -+ -+/***************************************************************************** -+ GPIO INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define GPIO_PORT_OFFSET_0x1000 -+ -+#define GPIO_NUM_OF_PORTS 3 /**< Number of ports in GPIO module; -+ Each port contains up to 32 I/O pins. */ -+ -+#define GPIO_VALID_PIN_MASKS \ -+ { /* Port A */ 0xFFFFFFFF, \ -+ /* Port B */ 0xFFFFFFFF, \ -+ /* Port C */ 0xFFFFFFFF } -+ -+#define GPIO_VALID_INTR_MASKS \ -+ { /* Port A */ 0xFFFFFFFF, \ -+ /* Port B */ 0xFFFFFFFF, \ -+ /* Port C */ 0xFFFFFFFF } -+ -+ -+ -+#endif /* __PART_INTEGRATION_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/LS1043/dpaa_integration_ext.h -@@ -0,0 +1,291 @@ -+/* -+ * Copyright 2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/** -+ -+ @File dpaa_integration_ext.h -+ -+ @Description T4240 FM external definitions and structures. -+*//***************************************************************************/ -+#ifndef __DPAA_INTEGRATION_EXT_H -+#define __DPAA_INTEGRATION_EXT_H -+ -+#include "std_ext.h" -+ -+ -+#define DPAA_VERSION 11 -+ -+/**************************************************************************//** -+ @Description DPAA SW Portals Enumeration. -+*//***************************************************************************/ -+typedef enum -+{ -+ e_DPAA_SWPORTAL0 = 0, -+ e_DPAA_SWPORTAL1, -+ e_DPAA_SWPORTAL2, -+ e_DPAA_SWPORTAL3, -+ e_DPAA_SWPORTAL4, -+ e_DPAA_SWPORTAL5, -+ e_DPAA_SWPORTAL6, -+ e_DPAA_SWPORTAL7, -+ e_DPAA_SWPORTAL8, -+ e_DPAA_SWPORTAL9, -+ e_DPAA_SWPORTAL10, -+ e_DPAA_SWPORTAL11, -+ e_DPAA_SWPORTAL12, -+ e_DPAA_SWPORTAL13, -+ e_DPAA_SWPORTAL14, -+ e_DPAA_SWPORTAL15, -+ e_DPAA_SWPORTAL16, -+ e_DPAA_SWPORTAL17, -+ e_DPAA_SWPORTAL18, -+ e_DPAA_SWPORTAL19, -+ e_DPAA_SWPORTAL20, -+ e_DPAA_SWPORTAL21, -+ e_DPAA_SWPORTAL22, -+ e_DPAA_SWPORTAL23, -+ e_DPAA_SWPORTAL24, -+ e_DPAA_SWPORTAL_DUMMY_LAST -+} e_DpaaSwPortal; -+ -+/**************************************************************************//** -+ @Description DPAA Direct Connect Portals Enumeration. -+*//***************************************************************************/ -+typedef enum -+{ -+ e_DPAA_DCPORTAL0 = 0, -+ e_DPAA_DCPORTAL1, -+ e_DPAA_DCPORTAL2, -+ e_DPAA_DCPORTAL_DUMMY_LAST -+} e_DpaaDcPortal; -+ -+#define DPAA_MAX_NUM_OF_SW_PORTALS e_DPAA_SWPORTAL_DUMMY_LAST -+#define DPAA_MAX_NUM_OF_DC_PORTALS e_DPAA_DCPORTAL_DUMMY_LAST -+ -+/***************************************************************************** -+ QMan INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define QM_MAX_NUM_OF_POOL_CHANNELS 15 /**< Total number of channels, dedicated and pool */ -+#define QM_MAX_NUM_OF_WQ 8 /**< Number of work queues per channel */ -+#define QM_MAX_NUM_OF_CGS 256 /**< Congestion groups number */ -+#define QM_MAX_NUM_OF_FQIDS (16 * MEGABYTE) -+ /**< FQIDs range - 24 bits */ -+ -+/**************************************************************************//** -+ @Description Work Queue Channel assignments in QMan. -+*//***************************************************************************/ -+typedef enum -+{ -+ e_QM_FQ_CHANNEL_SWPORTAL0 = 0x0, /**< Dedicated channels serviced by software portals 0 to 24 */ -+ e_QM_FQ_CHANNEL_SWPORTAL1, -+ e_QM_FQ_CHANNEL_SWPORTAL2, -+ e_QM_FQ_CHANNEL_SWPORTAL3, -+ e_QM_FQ_CHANNEL_SWPORTAL4, -+ e_QM_FQ_CHANNEL_SWPORTAL5, -+ e_QM_FQ_CHANNEL_SWPORTAL6, -+ e_QM_FQ_CHANNEL_SWPORTAL7, -+ e_QM_FQ_CHANNEL_SWPORTAL8, -+ e_QM_FQ_CHANNEL_SWPORTAL9, -+ e_QM_FQ_CHANNEL_SWPORTAL10, -+ e_QM_FQ_CHANNEL_SWPORTAL11, -+ e_QM_FQ_CHANNEL_SWPORTAL12, -+ e_QM_FQ_CHANNEL_SWPORTAL13, -+ e_QM_FQ_CHANNEL_SWPORTAL14, -+ e_QM_FQ_CHANNEL_SWPORTAL15, -+ e_QM_FQ_CHANNEL_SWPORTAL16, -+ e_QM_FQ_CHANNEL_SWPORTAL17, -+ e_QM_FQ_CHANNEL_SWPORTAL18, -+ e_QM_FQ_CHANNEL_SWPORTAL19, -+ e_QM_FQ_CHANNEL_SWPORTAL20, -+ e_QM_FQ_CHANNEL_SWPORTAL21, -+ e_QM_FQ_CHANNEL_SWPORTAL22, -+ e_QM_FQ_CHANNEL_SWPORTAL23, -+ e_QM_FQ_CHANNEL_SWPORTAL24, -+ -+ e_QM_FQ_CHANNEL_POOL1 = 0x401, /**< Pool channels that can be serviced by any of the software portals */ -+ e_QM_FQ_CHANNEL_POOL2, -+ e_QM_FQ_CHANNEL_POOL3, -+ e_QM_FQ_CHANNEL_POOL4, -+ e_QM_FQ_CHANNEL_POOL5, -+ e_QM_FQ_CHANNEL_POOL6, -+ e_QM_FQ_CHANNEL_POOL7, -+ e_QM_FQ_CHANNEL_POOL8, -+ e_QM_FQ_CHANNEL_POOL9, -+ e_QM_FQ_CHANNEL_POOL10, -+ e_QM_FQ_CHANNEL_POOL11, -+ e_QM_FQ_CHANNEL_POOL12, -+ e_QM_FQ_CHANNEL_POOL13, -+ e_QM_FQ_CHANNEL_POOL14, -+ e_QM_FQ_CHANNEL_POOL15, -+ -+ e_QM_FQ_CHANNEL_FMAN0_SP0 = 0x800, /**< Dedicated channels serviced by Direct Connect Portal 0: -+ connected to FMan 0; assigned in incrementing order to -+ each sub-portal (SP) in the portal */ -+ e_QM_FQ_CHANNEL_FMAN0_SP1, -+ e_QM_FQ_CHANNEL_FMAN0_SP2, -+ e_QM_FQ_CHANNEL_FMAN0_SP3, -+ e_QM_FQ_CHANNEL_FMAN0_SP4, -+ e_QM_FQ_CHANNEL_FMAN0_SP5, -+ e_QM_FQ_CHANNEL_FMAN0_SP6, -+ e_QM_FQ_CHANNEL_FMAN0_SP7, -+ e_QM_FQ_CHANNEL_FMAN0_SP8, -+ e_QM_FQ_CHANNEL_FMAN0_SP9, -+ e_QM_FQ_CHANNEL_FMAN0_SP10, -+ e_QM_FQ_CHANNEL_FMAN0_SP11, -+ e_QM_FQ_CHANNEL_FMAN0_SP12, -+ e_QM_FQ_CHANNEL_FMAN0_SP13, -+ e_QM_FQ_CHANNEL_FMAN0_SP14, -+ e_QM_FQ_CHANNEL_FMAN0_SP15, -+ -+ e_QM_FQ_CHANNEL_RMAN_SP0 = 0x820, /**< Dedicated channels serviced by Direct Connect Portal 1: connected to RMan */ -+ e_QM_FQ_CHANNEL_RMAN_SP1, -+ -+ e_QM_FQ_CHANNEL_CAAM = 0x840 /**< Dedicated channel serviced by Direct Connect Portal 2: -+ connected to SEC */ -+} e_QmFQChannel; -+ -+/***************************************************************************** -+ BMan INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define BM_MAX_NUM_OF_POOLS 64 /**< Number of buffers pools */ -+ -+/***************************************************************************** -+ SEC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define SEC_NUM_OF_DECOS 3 -+#define SEC_ALL_DECOS_MASK 0x00000003 -+ -+ -+/***************************************************************************** -+ FM INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define INTG_MAX_NUM_OF_FM 2 -+ -+/* Ports defines */ -+#define FM_MAX_NUM_OF_1G_MACS 6 -+#define FM_MAX_NUM_OF_10G_MACS 2 -+#define FM_MAX_NUM_OF_MACS (FM_MAX_NUM_OF_1G_MACS + FM_MAX_NUM_OF_10G_MACS) -+#define FM_MAX_NUM_OF_OH_PORTS 6 -+ -+#define FM_MAX_NUM_OF_1G_RX_PORTS FM_MAX_NUM_OF_1G_MACS -+#define FM_MAX_NUM_OF_10G_RX_PORTS FM_MAX_NUM_OF_10G_MACS -+#define FM_MAX_NUM_OF_RX_PORTS (FM_MAX_NUM_OF_10G_RX_PORTS + FM_MAX_NUM_OF_1G_RX_PORTS) -+ -+#define FM_MAX_NUM_OF_1G_TX_PORTS FM_MAX_NUM_OF_1G_MACS -+#define FM_MAX_NUM_OF_10G_TX_PORTS FM_MAX_NUM_OF_10G_MACS -+#define FM_MAX_NUM_OF_TX_PORTS (FM_MAX_NUM_OF_10G_TX_PORTS + FM_MAX_NUM_OF_1G_TX_PORTS) -+ -+#define FM_PORT_MAX_NUM_OF_EXT_POOLS 4 /**< Number of external BM pools per Rx port */ -+#define FM_PORT_NUM_OF_CONGESTION_GRPS 256 /**< Total number of congestion groups in QM */ -+#define FM_MAX_NUM_OF_SUB_PORTALS 16 -+#define FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS 0 -+ -+#define FM_VSP_MAX_NUM_OF_ENTRIES 64 -+#define FM_MAX_NUM_OF_PFC_PRIORITIES 8 -+ -+/* RAMs defines */ -+#define FM_MURAM_SIZE (384 * KILOBYTE) -+#define FM_IRAM_SIZE(major, minor) (64 * KILOBYTE) -+#define FM_NUM_OF_CTRL 4 -+ -+/* PCD defines */ -+#define FM_PCD_PLCR_NUM_ENTRIES 256 /**< Total number of policer profiles */ -+#define FM_PCD_KG_NUM_OF_SCHEMES 32 /**< Total number of KG schemes */ -+#define FM_PCD_MAX_NUM_OF_CLS_PLANS 256 /**< Number of classification plan entries. */ -+#define FM_PCD_PRS_SW_PATCHES_SIZE 0x00000600 /**< Number of bytes saved for patches */ -+#define FM_PCD_SW_PRS_SIZE 0x00000800 /**< Total size of SW parser area */ -+ -+/* RTC defines */ -+#define FM_RTC_NUM_OF_ALARMS 2 /**< RTC number of alarms */ -+#define FM_RTC_NUM_OF_PERIODIC_PULSES 3 /**< RTC number of periodic pulses */ -+#define FM_RTC_NUM_OF_EXT_TRIGGERS 2 /**< RTC number of external triggers */ -+ -+/* QMI defines */ -+#define QMI_MAX_NUM_OF_TNUMS 64 -+#define QMI_DEF_TNUMS_THRESH 32 -+/* FPM defines */ -+#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4 -+ -+/* DMA defines */ -+#define DMA_THRESH_MAX_COMMQ 83 -+#define DMA_THRESH_MAX_BUF 127 -+ -+/* BMI defines */ -+#define BMI_MAX_NUM_OF_TASKS 128 -+#define BMI_MAX_NUM_OF_DMAS 84 -+ -+#define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE) -+#define PORT_MAX_WEIGHT 16 -+ -+#define FM_CHECK_PORT_RESTRICTIONS(__validPorts, __newPortIndx) TRUE -+ -+/* Unique T4240 */ -+#define FM_OP_OPEN_DMA_MIN_LIMIT -+#define FM_NO_RESTRICT_ON_ACCESS_RSRC -+#define FM_NO_OP_OBSERVED_POOLS -+#define FM_FRAME_END_PARAMS_FOR_OP -+#define FM_DEQ_PIPELINE_PARAMS_FOR_OP -+#define FM_QMI_NO_SINGLE_ECC_EXCEPTION -+ -+#define FM_NO_GUARANTEED_RESET_VALUES -+ -+/* FM errata */ -+#define FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 -+#define FM_WRONG_RESET_VALUES_ERRATA_FMAN_A005127 -+#define FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 -+#define FM_OP_NO_VSP_NO_RELEASE_ERRATA_FMAN_A006675 -+#define FM_HEAVY_TRAFFIC_SEQUENCER_HANG_ERRATA_FMAN_A006981 -+ -+#define FM_BCB_ERRATA_BMI_SW001 -+#define FM_LEN_CHECK_ERRATA_FMAN_SW002 -+#define FM_AID_MODE_NO_TNUM_SW005 /* refer to pdm TKT068794 - only support of port_id on aid */ -+#define FM_ERROR_VSP_NO_MATCH_SW006 /* refer to pdm TKT174304 - no match between errorQ and VSP */ -+ -+/***************************************************************************** -+ RMan INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define RM_MAX_NUM_OF_IB 4 /**< Number of inbound blocks */ -+#define RM_NUM_OF_IBCU 8 /**< NUmber of classification units in an inbound block */ -+ -+/* RMan erratas */ -+#define RM_ERRONEOUS_ACK_ERRATA_RMAN_A006756 -+ -+/***************************************************************************** -+ FM MACSEC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define NUM_OF_RX_SC 16 -+#define NUM_OF_TX_SC 16 -+ -+#define NUM_OF_SA_PER_RX_SC 2 -+#define NUM_OF_SA_PER_TX_SC 2 -+ -+#endif /* __DPAA_INTEGRATION_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/LS1043/part_ext.h -@@ -0,0 +1,64 @@ -+/* -+ * Copyright 2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ -+ @File part_ext.h -+ -+ @Description Definitions for the part (integration) module. -+*//***************************************************************************/ -+ -+#ifndef __PART_EXT_H -+#define __PART_EXT_H -+ -+#include "std_ext.h" -+#include "part_integration_ext.h" -+ -+#if !(defined(LS1043)) -+#error "unable to proceed without chip-definition" -+#endif -+ -+ -+/**************************************************************************//* -+ @Description Part data structure - must be contained in any integration -+ data structure. -+*//***************************************************************************/ -+typedef struct t_Part -+{ -+ uintptr_t (* f_GetModuleBase)(t_Handle h_Part, e_ModuleId moduleId); -+ /**< Returns the address of the module's memory map base. */ -+ e_ModuleId (* f_GetModuleIdByBase)(t_Handle h_Part, uintptr_t baseAddress); -+ /**< Returns the module's ID according to its memory map base. */ -+} t_Part; -+ -+ -+#endif /* __PART_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/LS1043/part_integration_ext.h -@@ -0,0 +1,185 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/** -+ -+ @File part_integration_ext.h -+ -+ @Description T4240 external definitions and structures. -+*//***************************************************************************/ -+#ifndef __PART_INTEGRATION_EXT_H -+#define __PART_INTEGRATION_EXT_H -+ -+#include "std_ext.h" -+#include "ddr_std_ext.h" -+#include "enet_ext.h" -+#include "dpaa_integration_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group T4240_chip_id T4240 Application Programming Interface -+ -+ @Description T4240 Chip functions,definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+#define INTG_MAX_NUM_OF_CORES 4 -+ -+/**************************************************************************//** -+ @Description Module types. -+*//***************************************************************************/ -+typedef enum e_ModuleId -+{ -+ e_MODULE_ID_DUART_1 = 0, -+ e_MODULE_ID_DUART_2, -+ e_MODULE_ID_DUART_3, -+ e_MODULE_ID_DUART_4, -+ e_MODULE_ID_LAW, -+ e_MODULE_ID_IFC, -+ e_MODULE_ID_PAMU, -+ e_MODULE_ID_QM, /**< Queue manager module */ -+ e_MODULE_ID_BM, /**< Buffer manager module */ -+ e_MODULE_ID_QM_CE_PORTAL_0, -+ e_MODULE_ID_QM_CI_PORTAL_0, -+ e_MODULE_ID_QM_CE_PORTAL_1, -+ e_MODULE_ID_QM_CI_PORTAL_1, -+ e_MODULE_ID_QM_CE_PORTAL_2, -+ e_MODULE_ID_QM_CI_PORTAL_2, -+ e_MODULE_ID_QM_CE_PORTAL_3, -+ e_MODULE_ID_QM_CI_PORTAL_3, -+ e_MODULE_ID_QM_CE_PORTAL_4, -+ e_MODULE_ID_QM_CI_PORTAL_4, -+ e_MODULE_ID_QM_CE_PORTAL_5, -+ e_MODULE_ID_QM_CI_PORTAL_5, -+ e_MODULE_ID_QM_CE_PORTAL_6, -+ e_MODULE_ID_QM_CI_PORTAL_6, -+ e_MODULE_ID_QM_CE_PORTAL_7, -+ e_MODULE_ID_QM_CI_PORTAL_7, -+ e_MODULE_ID_QM_CE_PORTAL_8, -+ e_MODULE_ID_QM_CI_PORTAL_8, -+ e_MODULE_ID_QM_CE_PORTAL_9, -+ e_MODULE_ID_QM_CI_PORTAL_9, -+ e_MODULE_ID_BM_CE_PORTAL_0, -+ e_MODULE_ID_BM_CI_PORTAL_0, -+ e_MODULE_ID_BM_CE_PORTAL_1, -+ e_MODULE_ID_BM_CI_PORTAL_1, -+ e_MODULE_ID_BM_CE_PORTAL_2, -+ e_MODULE_ID_BM_CI_PORTAL_2, -+ e_MODULE_ID_BM_CE_PORTAL_3, -+ e_MODULE_ID_BM_CI_PORTAL_3, -+ e_MODULE_ID_BM_CE_PORTAL_4, -+ e_MODULE_ID_BM_CI_PORTAL_4, -+ e_MODULE_ID_BM_CE_PORTAL_5, -+ e_MODULE_ID_BM_CI_PORTAL_5, -+ e_MODULE_ID_BM_CE_PORTAL_6, -+ e_MODULE_ID_BM_CI_PORTAL_6, -+ e_MODULE_ID_BM_CE_PORTAL_7, -+ e_MODULE_ID_BM_CI_PORTAL_7, -+ e_MODULE_ID_BM_CE_PORTAL_8, -+ e_MODULE_ID_BM_CI_PORTAL_8, -+ e_MODULE_ID_BM_CE_PORTAL_9, -+ e_MODULE_ID_BM_CI_PORTAL_9, -+ e_MODULE_ID_FM, /**< Frame manager module */ -+ e_MODULE_ID_FM_RTC, /**< FM Real-Time-Clock */ -+ e_MODULE_ID_FM_MURAM, /**< FM Multi-User-RAM */ -+ e_MODULE_ID_FM_BMI, /**< FM BMI block */ -+ e_MODULE_ID_FM_QMI, /**< FM QMI block */ -+ e_MODULE_ID_FM_PARSER, /**< FM parser block */ -+ e_MODULE_ID_FM_PORT_HO1, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO2, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO3, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO4, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO5, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO6, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO7, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_1GRx1, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx2, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx3, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx4, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx5, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx6, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_10GRx1, /**< FM Rx 10G MAC port block */ -+ e_MODULE_ID_FM_PORT_10GRx2, /**< FM Rx 10G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx1, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx2, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx3, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx4, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx5, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx6, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_10GTx1, /**< FM Tx 10G MAC port block */ -+ e_MODULE_ID_FM_PORT_10GTx2, /**< FM Tx 10G MAC port block */ -+ e_MODULE_ID_FM_PLCR, /**< FM Policer */ -+ e_MODULE_ID_FM_KG, /**< FM Keygen */ -+ e_MODULE_ID_FM_DMA, /**< FM DMA */ -+ e_MODULE_ID_FM_FPM, /**< FM FPM */ -+ e_MODULE_ID_FM_IRAM, /**< FM Instruction-RAM */ -+ e_MODULE_ID_FM_1GMDIO, /**< FM 1G MDIO MAC */ -+ e_MODULE_ID_FM_10GMDIO, /**< FM 10G MDIO */ -+ e_MODULE_ID_FM_PRS_IRAM, /**< FM SW-parser Instruction-RAM */ -+ e_MODULE_ID_FM_1GMAC1, /**< FM 1G MAC #1 */ -+ e_MODULE_ID_FM_1GMAC2, /**< FM 1G MAC #2 */ -+ e_MODULE_ID_FM_1GMAC3, /**< FM 1G MAC #3 */ -+ e_MODULE_ID_FM_1GMAC4, /**< FM 1G MAC #4 */ -+ e_MODULE_ID_FM_1GMAC5, /**< FM 1G MAC #5 */ -+ e_MODULE_ID_FM_1GMAC6, /**< FM 1G MAC #6 */ -+ e_MODULE_ID_FM_10GMAC1, /**< FM 10G MAC */ -+ e_MODULE_ID_FM_10GMAC2, /**< FM 10G MAC */ -+ -+ e_MODULE_ID_SEC_GEN, /**< SEC 4.0 General registers */ -+ e_MODULE_ID_SEC_QI, /**< SEC 4.0 QI registers */ -+ e_MODULE_ID_SEC_JQ0, /**< SEC 4.0 JQ-0 registers */ -+ e_MODULE_ID_SEC_JQ1, /**< SEC 4.0 JQ-1 registers */ -+ e_MODULE_ID_SEC_JQ2, /**< SEC 4.0 JQ-2 registers */ -+ e_MODULE_ID_SEC_JQ3, /**< SEC 4.0 JQ-3 registers */ -+ e_MODULE_ID_SEC_RTIC, /**< SEC 4.0 RTIC registers */ -+ e_MODULE_ID_SEC_DECO0_CCB0, /**< SEC 4.0 DECO-0/CCB-0 registers */ -+ e_MODULE_ID_SEC_DECO1_CCB1, /**< SEC 4.0 DECO-1/CCB-1 registers */ -+ e_MODULE_ID_SEC_DECO2_CCB2, /**< SEC 4.0 DECO-2/CCB-2 registers */ -+ e_MODULE_ID_SEC_DECO3_CCB3, /**< SEC 4.0 DECO-3/CCB-3 registers */ -+ e_MODULE_ID_SEC_DECO4_CCB4, /**< SEC 4.0 DECO-4/CCB-4 registers */ -+ -+ e_MODULE_ID_PIC, /**< PIC */ -+ e_MODULE_ID_GPIO, /**< GPIO */ -+ e_MODULE_ID_SERDES, /**< SERDES */ -+ e_MODULE_ID_CPC_1, /**< CoreNet-Platform-Cache 1 */ -+ e_MODULE_ID_CPC_2, /**< CoreNet-Platform-Cache 2 */ -+ -+ e_MODULE_ID_SRIO_PORTS, /**< RapidIO controller */ -+ -+ e_MODULE_ID_DUMMY_LAST -+} e_ModuleId; -+ -+#define NUM_OF_MODULES e_MODULE_ID_DUMMY_LAST -+ -+ -+#endif /* __PART_INTEGRATION_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P1023/dpaa_integration_ext.h -@@ -0,0 +1,213 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/** -+ -+ @File dpaa_integration_ext.h -+ -+ @Description P1023 FM external definitions and structures. -+*//***************************************************************************/ -+#ifndef __DPAA_INTEGRATION_EXT_H -+#define __DPAA_INTEGRATION_EXT_H -+ -+#include "std_ext.h" -+ -+ -+#define DPAA_VERSION 10 -+ -+typedef enum e_DpaaSwPortal { -+ e_DPAA_SWPORTAL0 = 0, -+ e_DPAA_SWPORTAL1, -+ e_DPAA_SWPORTAL2, -+ e_DPAA_SWPORTAL_DUMMY_LAST -+} e_DpaaSwPortal; -+ -+typedef enum { -+ e_DPAA_DCPORTAL0 = 0, -+ e_DPAA_DCPORTAL2, -+ e_DPAA_DCPORTAL_DUMMY_LAST -+} e_DpaaDcPortal; -+ -+#define DPAA_MAX_NUM_OF_SW_PORTALS e_DPAA_SWPORTAL_DUMMY_LAST -+#define DPAA_MAX_NUM_OF_DC_PORTALS e_DPAA_DCPORTAL_DUMMY_LAST -+ -+/***************************************************************************** -+ QMAN INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define QM_MAX_NUM_OF_POOL_CHANNELS 3 -+#define QM_MAX_NUM_OF_WQ 8 -+#define QM_MAX_NUM_OF_SWP_AS 2 -+#define QM_MAX_NUM_OF_CGS 64 -+#define QM_MAX_NUM_OF_FQIDS (16*MEGABYTE) -+ -+typedef enum { -+ e_QM_FQ_CHANNEL_SWPORTAL0 = 0, -+ e_QM_FQ_CHANNEL_SWPORTAL1, -+ e_QM_FQ_CHANNEL_SWPORTAL2, -+ -+ e_QM_FQ_CHANNEL_POOL1 = 0x21, -+ e_QM_FQ_CHANNEL_POOL2, -+ e_QM_FQ_CHANNEL_POOL3, -+ -+ e_QM_FQ_CHANNEL_FMAN0_SP0 = 0x40, -+ e_QM_FQ_CHANNEL_FMAN0_SP1, -+ e_QM_FQ_CHANNEL_FMAN0_SP2, -+ e_QM_FQ_CHANNEL_FMAN0_SP3, -+ e_QM_FQ_CHANNEL_FMAN0_SP4, -+ e_QM_FQ_CHANNEL_FMAN0_SP5, -+ e_QM_FQ_CHANNEL_FMAN0_SP6, -+ -+ -+ e_QM_FQ_CHANNEL_CAAM = 0x80 -+} e_QmFQChannel; -+ -+/***************************************************************************** -+ BMAN INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define BM_MAX_NUM_OF_POOLS 8 -+ -+/***************************************************************************** -+ SEC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define SEC_NUM_OF_DECOS 2 -+#define SEC_ALL_DECOS_MASK 0x00000003 -+#define SEC_RNGB -+#define SEC_NO_ESP_TRAILER_REMOVAL -+ -+/***************************************************************************** -+ FM INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define INTG_MAX_NUM_OF_FM 1 -+ -+/* Ports defines */ -+#define FM_MAX_NUM_OF_1G_MACS 2 -+#define FM_MAX_NUM_OF_10G_MACS 0 -+#define FM_MAX_NUM_OF_MACS (FM_MAX_NUM_OF_1G_MACS + FM_MAX_NUM_OF_10G_MACS) -+#define FM_MAX_NUM_OF_OH_PORTS 5 -+ -+#define FM_MAX_NUM_OF_1G_RX_PORTS FM_MAX_NUM_OF_1G_MACS -+#define FM_MAX_NUM_OF_10G_RX_PORTS FM_MAX_NUM_OF_10G_MACS -+#define FM_MAX_NUM_OF_RX_PORTS (FM_MAX_NUM_OF_10G_RX_PORTS + FM_MAX_NUM_OF_1G_RX_PORTS) -+ -+#define FM_MAX_NUM_OF_1G_TX_PORTS FM_MAX_NUM_OF_1G_MACS -+#define FM_MAX_NUM_OF_10G_TX_PORTS FM_MAX_NUM_OF_10G_MACS -+#define FM_MAX_NUM_OF_TX_PORTS (FM_MAX_NUM_OF_10G_TX_PORTS + FM_MAX_NUM_OF_1G_TX_PORTS) -+ -+#define FM_MAX_NUM_OF_MACSECS 1 -+ -+#define FM_MACSEC_SUPPORT -+ -+#define FM_LOW_END_RESTRICTION /* prevents the use of TX port 1 with OP port 0 */ -+ -+#define FM_PORT_MAX_NUM_OF_EXT_POOLS 4 /**< Number of external BM pools per Rx port */ -+#define FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS 2 /**< Number of Offline parsing port external BM pools per Rx port */ -+#define FM_PORT_NUM_OF_CONGESTION_GRPS 32 /**< Total number of congestion groups in QM */ -+#define FM_MAX_NUM_OF_SUB_PORTALS 7 -+ -+/* Rams defines */ -+#define FM_MURAM_SIZE (64*KILOBYTE) -+#define FM_IRAM_SIZE(major, minor) (32 * KILOBYTE) -+#define FM_NUM_OF_CTRL 2 -+ -+/* PCD defines */ -+#define FM_PCD_PLCR_NUM_ENTRIES 32 /**< Total number of policer profiles */ -+#define FM_PCD_KG_NUM_OF_SCHEMES 16 /**< Total number of KG schemes */ -+#define FM_PCD_MAX_NUM_OF_CLS_PLANS 128 /**< Number of classification plan entries. */ -+#define FM_PCD_PRS_SW_PATCHES_SIZE 0x00000240 /**< Number of bytes saved for patches */ -+#define FM_PCD_SW_PRS_SIZE 0x00000800 /**< Total size of SW parser area */ -+ -+/* RTC defines */ -+#define FM_RTC_NUM_OF_ALARMS 2 -+#define FM_RTC_NUM_OF_PERIODIC_PULSES 2 -+#define FM_RTC_NUM_OF_EXT_TRIGGERS 2 -+ -+/* QMI defines */ -+#define QMI_MAX_NUM_OF_TNUMS 15 -+ -+/* FPM defines */ -+#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4 -+ -+/* DMA defines */ -+#define DMA_THRESH_MAX_COMMQ 15 -+#define DMA_THRESH_MAX_BUF 7 -+ -+/* BMI defines */ -+#define BMI_MAX_NUM_OF_TASKS 64 -+#define BMI_MAX_NUM_OF_DMAS 16 -+#define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE) -+#define PORT_MAX_WEIGHT 4 -+ -+/***************************************************************************** -+ FM MACSEC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define NUM_OF_RX_SC 16 -+#define NUM_OF_TX_SC 16 -+ -+#define NUM_OF_SA_PER_RX_SC 2 -+#define NUM_OF_SA_PER_TX_SC 2 -+ -+/**************************************************************************//** -+ @Description Enum for inter-module interrupts registration -+*//***************************************************************************/ -+ -+/* 1023 unique features */ -+#define FM_QMI_NO_ECC_EXCEPTIONS -+#define FM_CSI_CFED_LIMIT -+#define FM_PEDANTIC_DMA -+#define FM_QMI_NO_DEQ_OPTIONS_SUPPORT -+#define FM_FIFO_ALLOCATION_ALG -+#define FM_DEQ_PIPELINE_PARAMS_FOR_OP -+#define FM_HAS_TOTAL_DMAS -+#define FM_KG_NO_IPPID_SUPPORT -+#define FM_NO_GUARANTEED_RESET_VALUES -+#define FM_MAC_RESET -+ -+/* FM erratas */ -+#define FM_RX_PREAM_4_ERRATA_DTSEC_A001 -+#define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */ -+ -+#define FM_DEBUG_TRACE_FMAN_A004 /* No implementation, Out of LLD scope */ -+#define FM_INT_BUF_LEAK_FMAN_A005 /* No implementation, Out of LLD scope. App must avoid S/G */ -+ -+#define FM_GTS_AFTER_DROPPED_FRAME_ERRATA_DTSEC_A004839 -+ -+/* #define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 */ -+ -+/* -+TKT056919 - axi12axi0 can hang if read request follows the single byte write on the very next cycle -+TKT038900 - FM dma lockup occur due to AXI slave protocol violation -+*/ -+#define FM_LOCKUP_ALIGNMENT_ERRATA_FMAN_SW004 -+ -+ -+#endif /* __DPAA_INTEGRATION_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P1023/part_ext.h -@@ -0,0 +1,82 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ -+ @File part_ext.h -+ -+ @Description Definitions for the part (integration) module. -+*//***************************************************************************/ -+ -+#ifndef __PART_EXT_H -+#define __PART_EXT_H -+ -+#include "std_ext.h" -+#include "part_integration_ext.h" -+ -+ -+#if !(defined(MPC8306) || \ -+ defined(MPC8309) || \ -+ defined(MPC834x) || \ -+ defined(MPC836x) || \ -+ defined(MPC832x) || \ -+ defined(MPC837x) || \ -+ defined(MPC8568) || \ -+ defined(MPC8569) || \ -+ defined(P1020) || \ -+ defined(P1021) || \ -+ defined(P1022) || \ -+ defined(P1023) || \ -+ defined(P2020) || \ -+ defined(P3041) || \ -+ defined(P4080) || \ -+ defined(P5020) || \ -+ defined(MSC814x)) -+#error "unable to proceed without chip-definition" -+#endif -+ -+ -+/**************************************************************************//* -+ @Description Part data structure - must be contained in any integration -+ data structure. -+*//***************************************************************************/ -+typedef struct t_Part -+{ -+ uint64_t (* f_GetModuleBase)(t_Handle h_Part, e_ModuleId moduleId); -+ /**< Returns the address of the module's memory map base. */ -+ e_ModuleId (* f_GetModuleIdByBase)(t_Handle h_Part, uint64_t baseAddress); -+ /**< Returns the module's ID according to its memory map base. */ -+} t_Part; -+ -+ -+#endif /* __PART_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P1023/part_integration_ext.h -@@ -0,0 +1,635 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ @File part_integration_ext.h -+ -+ @Description P1023 external definitions and structures. -+*//***************************************************************************/ -+#ifndef __PART_INTEGRATION_EXT_H -+#define __PART_INTEGRATION_EXT_H -+ -+#include "std_ext.h" -+#include "dpaa_integration_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group 1023_chip_id P1023 Application Programming Interface -+ -+ @Description P1023 Chip functions,definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+#define INTG_MAX_NUM_OF_CORES 2 -+ -+ -+/**************************************************************************//** -+ @Description Module types. -+*//***************************************************************************/ -+typedef enum e_ModuleId -+{ -+ e_MODULE_ID_LAW, /**< Local Access module */ -+ e_MODULE_ID_ECM, /**< e500 Coherency Module */ -+ e_MODULE_ID_DDR, /**< DDR memory controller */ -+ e_MODULE_ID_I2C_1, /**< I2C 1 */ -+ e_MODULE_ID_I2C_2, /**< I2C 1 */ -+ e_MODULE_ID_DUART_1, /**< DUART module 1 */ -+ e_MODULE_ID_DUART_2, /**< DUART module 2 */ -+ e_MODULE_ID_LBC, /**< Local bus memory controller module */ -+ e_MODULE_ID_PCIE_1, /**< PCI Express 1 controller module */ -+ e_MODULE_ID_PCIE_ATMU_1, /**< PCI 1 ATMU Window */ -+ e_MODULE_ID_PCIE_2, /**< PCI Express 2 controller module */ -+ e_MODULE_ID_PCIE_ATMU_2, /**< PCI 2 ATMU Window */ -+ e_MODULE_ID_PCIE_3, /**< PCI Express 3 controller module */ -+ e_MODULE_ID_PCIE_ATMU_3, /**< PCI 3 ATMU Window */ -+ e_MODULE_ID_MSI, /**< MSI registers */ -+ e_MODULE_ID_L2_SRAM, /**< L2/SRAM Memory-Mapped controller module */ -+ e_MODULE_ID_DMA_1, /**< DMA controller 1 */ -+ e_MODULE_ID_DMA_2, /**< DMA controller 2 */ -+ e_MODULE_ID_EPIC, /**< Programmable interrupt controller */ -+ e_MODULE_ID_ESPI, /**< ESPI module */ -+ e_MODULE_ID_GPIO, /**< General Purpose I/O */ -+ e_MODULE_ID_SEC_GEN, /**< SEC 4.0 General registers */ -+ e_MODULE_ID_SEC_QI, /**< SEC 4.0 QI registers */ -+ e_MODULE_ID_SEC_JQ0, /**< SEC 4.0 JQ-0 registers */ -+ e_MODULE_ID_SEC_JQ1, /**< SEC 4.0 JQ-1 registers */ -+ e_MODULE_ID_SEC_JQ2, /**< SEC 4.0 JQ-2 registers */ -+ e_MODULE_ID_SEC_JQ3, /**< SEC 4.0 JQ-3 registers */ -+ e_MODULE_ID_SEC_RTIC, /**< SEC 4.0 RTIC registers */ -+ e_MODULE_ID_SEC_DECO0_CCB0, /**< SEC 4.0 DECO-0/CCB-0 registers */ -+ e_MODULE_ID_SEC_DECO1_CCB1, /**< SEC 4.0 DECO-1/CCB-1 registers */ -+ e_MODULE_ID_SEC_DECO2_CCB2, /**< SEC 4.0 DECO-2/CCB-2 registers */ -+ e_MODULE_ID_SEC_DECO3_CCB3, /**< SEC 4.0 DECO-3/CCB-3 registers */ -+ e_MODULE_ID_SEC_DECO4_CCB4, /**< SEC 4.0 DECO-4/CCB-4 registers */ -+ e_MODULE_ID_USB_DR_1, /**< USB 2.0 module 1 */ -+ e_MODULE_ID_USB_DR_2, /**< USB 2.0 module 2 */ -+ e_MODULE_ID_ETSEC_MII_MNG, /**< MII MNG registers */ -+ e_MODULE_ID_ETSEC_1, /**< ETSEC module 1 */ -+ e_MODULE_ID_ETSEC_2, /**< ETSEC module 2 */ -+ e_MODULE_ID_GUTS, /**< Serial DMA */ -+ e_MODULE_ID_PM, /**< Performance Monitor module */ -+ e_MODULE_ID_QM, /**< Queue manager module */ -+ e_MODULE_ID_BM, /**< Buffer manager module */ -+ e_MODULE_ID_QM_CE_PORTAL, -+ e_MODULE_ID_QM_CI_PORTAL, -+ e_MODULE_ID_BM_CE_PORTAL, -+ e_MODULE_ID_BM_CI_PORTAL, -+ e_MODULE_ID_FM, /**< Frame manager #1 module */ -+ e_MODULE_ID_FM_RTC, /**< FM Real-Time-Clock */ -+ e_MODULE_ID_FM_MURAM, /**< FM Multi-User-RAM */ -+ e_MODULE_ID_FM_BMI, /**< FM BMI block */ -+ e_MODULE_ID_FM_QMI, /**< FM QMI block */ -+ e_MODULE_ID_FM_PRS, /**< FM parser block */ -+ e_MODULE_ID_FM_PORT_HO0, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO1, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO2, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO3, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_HO4, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM_PORT_1GRx0, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GRx1, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx0, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PORT_1GTx1, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM_PLCR, /**< FM Policer */ -+ e_MODULE_ID_FM_KG, /**< FM Keygen */ -+ e_MODULE_ID_FM_DMA, /**< FM DMA */ -+ e_MODULE_ID_FM_FPM, /**< FM FPM */ -+ e_MODULE_ID_FM_IRAM, /**< FM Instruction-RAM */ -+ e_MODULE_ID_FM_1GMDIO0, /**< FM 1G MDIO MAC 0*/ -+ e_MODULE_ID_FM_1GMDIO1, /**< FM 1G MDIO MAC 1*/ -+ e_MODULE_ID_FM_PRS_IRAM, /**< FM SW-parser Instruction-RAM */ -+ e_MODULE_ID_FM_RISC0, /**< FM risc #0 */ -+ e_MODULE_ID_FM_RISC1, /**< FM risc #1 */ -+ e_MODULE_ID_FM_1GMAC0, /**< FM 1G MAC #0 */ -+ e_MODULE_ID_FM_1GMAC1, /**< FM 1G MAC #1 */ -+ e_MODULE_ID_FM_MACSEC, /**< FM MACSEC */ -+ -+ e_MODULE_ID_DUMMY_LAST -+} e_ModuleId; -+ -+#define NUM_OF_MODULES e_MODULE_ID_DUMMY_LAST -+ -+ -+#define P1023_OFFSET_LAW 0x00000C08 -+#define P1023_OFFSET_ECM 0x00001000 -+#define P1023_OFFSET_DDR 0x00002000 -+#define P1023_OFFSET_I2C1 0x00003000 -+#define P1023_OFFSET_I2C2 0x00003100 -+#define P1023_OFFSET_DUART1 0x00004500 -+#define P1023_OFFSET_DUART2 0x00004600 -+#define P1023_OFFSET_LBC 0x00005000 -+#define P1023_OFFSET_ESPI 0x00007000 -+#define P1023_OFFSET_PCIE2 0x00009000 -+#define P1023_OFFSET_PCIE2_ATMU 0x00009C00 -+#define P1023_OFFSET_PCIE1 0x0000A000 -+#define P1023_OFFSET_PCIE1_ATMU 0x0000AC00 -+#define P1023_OFFSET_PCIE3 0x0000B000 -+#define P1023_OFFSET_PCIE3_ATMU 0x0000BC00 -+#define P1023_OFFSET_DMA2 0x0000C100 -+#define P1023_OFFSET_GPIO 0x0000F000 -+#define P1023_OFFSET_L2_SRAM 0x00020000 -+#define P1023_OFFSET_DMA1 0x00021100 -+#define P1023_OFFSET_USB1 0x00022000 -+#define P1023_OFFSET_SEC_GEN 0x00030000 -+#define P1023_OFFSET_SEC_JQ0 0x00031000 -+#define P1023_OFFSET_SEC_JQ1 0x00032000 -+#define P1023_OFFSET_SEC_JQ2 0x00033000 -+#define P1023_OFFSET_SEC_JQ3 0x00034000 -+#define P1023_OFFSET_SEC_RTIC 0x00036000 -+#define P1023_OFFSET_SEC_QI 0x00037000 -+#define P1023_OFFSET_SEC_DECO0_CCB0 0x00038000 -+#define P1023_OFFSET_SEC_DECO1_CCB1 0x00039000 -+#define P1023_OFFSET_SEC_DECO2_CCB2 0x0003a000 -+#define P1023_OFFSET_SEC_DECO3_CCB3 0x0003b000 -+#define P1023_OFFSET_SEC_DECO4_CCB4 0x0003c000 -+#define P1023_OFFSET_PIC 0x00040000 -+#define P1023_OFFSET_MSI 0x00041600 -+#define P1023_OFFSET_AXI 0x00081000 -+#define P1023_OFFSET_QM 0x00088000 -+#define P1023_OFFSET_BM 0x0008A000 -+#define P1022_OFFSET_PM 0x000E1000 -+ -+#define P1023_OFFSET_GUTIL 0x000E0000 -+#define P1023_OFFSET_PM 0x000E1000 -+#define P1023_OFFSET_DEBUG 0x000E2000 -+#define P1023_OFFSET_SERDES 0x000E3000 -+#define P1023_OFFSET_ROM 0x000F0000 -+#define P1023_OFFSET_FM 0x00100000 -+ -+#define P1023_OFFSET_FM_MURAM (P1023_OFFSET_FM + 0x00000000) -+#define P1023_OFFSET_FM_BMI (P1023_OFFSET_FM + 0x00080000) -+#define P1023_OFFSET_FM_QMI (P1023_OFFSET_FM + 0x00080400) -+#define P1023_OFFSET_FM_PRS (P1023_OFFSET_FM + 0x00080800) -+#define P1023_OFFSET_FM_PORT_HO0 (P1023_OFFSET_FM + 0x00081000) -+#define P1023_OFFSET_FM_PORT_HO1 (P1023_OFFSET_FM + 0x00082000) -+#define P1023_OFFSET_FM_PORT_HO2 (P1023_OFFSET_FM + 0x00083000) -+#define P1023_OFFSET_FM_PORT_HO3 (P1023_OFFSET_FM + 0x00084000) -+#define P1023_OFFSET_FM_PORT_HO4 (P1023_OFFSET_FM + 0x00085000) -+#define P1023_OFFSET_FM_PORT_1GRX0 (P1023_OFFSET_FM + 0x00088000) -+#define P1023_OFFSET_FM_PORT_1GRX1 (P1023_OFFSET_FM + 0x00089000) -+#define P1023_OFFSET_FM_PORT_1GTX0 (P1023_OFFSET_FM + 0x000A8000) -+#define P1023_OFFSET_FM_PORT_1GTX1 (P1023_OFFSET_FM + 0x000A9000) -+#define P1023_OFFSET_FM_PLCR (P1023_OFFSET_FM + 0x000C0000) -+#define P1023_OFFSET_FM_KG (P1023_OFFSET_FM + 0x000C1000) -+#define P1023_OFFSET_FM_DMA (P1023_OFFSET_FM + 0x000C2000) -+#define P1023_OFFSET_FM_FPM (P1023_OFFSET_FM + 0x000C3000) -+#define P1023_OFFSET_FM_IRAM (P1023_OFFSET_FM + 0x000C4000) -+#define P1023_OFFSET_FM_PRS_IRAM (P1023_OFFSET_FM + 0x000C7000) -+#define P1023_OFFSET_FM_RISC0 (P1023_OFFSET_FM + 0x000D0000) -+#define P1023_OFFSET_FM_RISC1 (P1023_OFFSET_FM + 0x000D0400) -+#define P1023_OFFSET_FM_MACSEC (P1023_OFFSET_FM + 0x000D8000) -+#define P1023_OFFSET_FM_1GMAC0 (P1023_OFFSET_FM + 0x000E0000) -+#define P1023_OFFSET_FM_1GMDIO0 (P1023_OFFSET_FM + 0x000E1120) -+#define P1023_OFFSET_FM_1GMAC1 (P1023_OFFSET_FM + 0x000E2000) -+#define P1023_OFFSET_FM_1GMDIO1 (P1023_OFFSET_FM + 0x000E3000) -+#define P1023_OFFSET_FM_RTC (P1023_OFFSET_FM + 0x000FE000) -+ -+/* Offsets relative to QM or BM portals base */ -+#define P1023_OFFSET_PORTALS_CE_AREA 0x00000000 /* cache enabled area */ -+#define P1023_OFFSET_PORTALS_CI_AREA 0x00100000 /* cache inhibited area */ -+ -+#define P1023_OFFSET_PORTALS_CE(portal) (P1023_OFFSET_PORTALS_CE_AREA + 0x4000 * (portal)) -+#define P1023_OFFSET_PORTALS_CI(portal) (P1023_OFFSET_PORTALS_CI_AREA + 0x1000 * (portal)) -+ -+/**************************************************************************//** -+ @Description Transaction source ID (for memory controllers error reporting). -+*//***************************************************************************/ -+typedef enum e_TransSrc -+{ -+ e_TRANS_SRC_PCIE_2 = 0x01, /**< PCIe port 2 */ -+ e_TRANS_SRC_PCIE_1 = 0x02, /**< PCIe port 1 */ -+ e_TRANS_SRC_PCIE_3 = 0x03, /**< PCIe port 3 */ -+ e_TRANS_SRC_LBC = 0x04, /**< Enhanced local bus */ -+ e_TRANS_SRC_DPAA_SW_PORTALS = 0x0E, /**< DPAA software portals or SRAM */ -+ e_TRANS_SRC_DDR = 0x0F, /**< DDR controller */ -+ e_TRANS_SRC_CORE_INS_FETCH = 0x10, /**< Processor (instruction) */ -+ e_TRANS_SRC_CORE_DATA = 0x11, /**< Processor (data) */ -+ e_TRANS_SRC_DMA = 0x15 /**< DMA */ -+} e_TransSrc; -+ -+/**************************************************************************//** -+ @Description Local Access Window Target interface ID -+*//***************************************************************************/ -+typedef enum e_P1023LawTargetId -+{ -+ e_P1023_LAW_TARGET_PCIE_2 = 0x01, /**< PCI Express 2 target interface */ -+ e_P1023_LAW_TARGET_PCIE_1 = 0x02, /**< PCI Express 1 target interface */ -+ e_P1023_LAW_TARGET_PCIE_3 = 0x03, /**< PCI Express 3 target interface */ -+ e_P1023_LAW_TARGET_LBC = 0x04, /**< Local bus target interface */ -+ e_P1023_LAW_TARGET_QM_PORTALS = 0x0E, /**< Queue Manager Portals */ -+ e_P1023_LAW_TARGET_BM_PORTALS = 0x0E, /**< Buffer Manager Portals */ -+ e_P1023_LAW_TARGET_SRAM = 0x0E, /**< SRAM scratchpad */ -+ e_P1023_LAW_TARGET_DDR = 0x0F, /**< DDR target interface */ -+ e_P1023_LAW_TARGET_NONE = 0xFF /**< Invalid target interface */ -+} e_P1023LawTargetId; -+ -+ -+/**************************************************************************//** -+ @Group 1023_init_grp P1023 Initialization Unit -+ -+ @Description P1023 initialization unit API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description Part ID and revision number -+*//***************************************************************************/ -+typedef enum e_P1023DeviceName -+{ -+ e_P1023_REV_INVALID = 0x00000000, /**< Invalid revision */ -+ e_SC1023_REV_1_0 = (int)0x80FC0010, /**< SC1023 rev 1.0 */ -+ e_SC1023_REV_1_1 = (int)0x80FC0011, /**< SC1023 rev 1.1 */ -+ e_P1023_REV_1_0 = (int)0x80FE0010, /**< P1023 rev 1.0 with security */ -+ e_P1023_REV_1_1 = (int)0x80FE0011, /**< P1023 rev 1.1 with security */ -+ e_P1017_REV_1_1 = (int)0x80FF0011, /**< P1017 rev 1.1 with security */ -+ e_P1023_REV_1_0_NO_SEC = (int)0x80F60010, /**< P1023 rev 1.0 without security */ -+ e_P1023_REV_1_1_NO_SEC = (int)0x80F60011, /**< P1023 rev 1.1 without security */ -+ e_P1017_REV_1_1_NO_SEC = (int)0x80F70011 /**< P1017 rev 1.1 without security */ -+} e_P1023DeviceName; -+ -+/**************************************************************************//** -+ @Description structure representing P1023 initialization parameters -+*//***************************************************************************/ -+typedef struct t_P1023Params -+{ -+ uintptr_t ccsrBaseAddress; /**< CCSR base address (virtual) */ -+ uintptr_t bmPortalsBaseAddress; /**< Portals base address (virtual) */ -+ uintptr_t qmPortalsBaseAddress; /**< Portals base address (virtual) */ -+} t_P1023Params; -+ -+/**************************************************************************//** -+ @Function P1023_ConfigAndInit -+ -+ @Description General initiation of the chip registers. -+ -+ @Param[in] p_P1023Params - A pointer to data structure of parameters -+ -+ @Return A handle to the P1023 data structure. -+*//***************************************************************************/ -+t_Handle P1023_ConfigAndInit(t_P1023Params *p_P1023Params); -+ -+/**************************************************************************//** -+ @Function P1023_Free -+ -+ @Description Free all resources. -+ -+ @Param h_P1023 - (In) The handle of the initialized P1023 object. -+ -+ @Return E_OK on success; Other value otherwise. -+*//***************************************************************************/ -+t_Error P1023_Free(t_Handle h_P1023); -+ -+/**************************************************************************//** -+ @Function P1023_GetRevInfo -+ -+ @Description This routine enables access to chip and revision information. -+ -+ @Param[in] gutilBase - Base address of P1023 GUTIL registers. -+ -+ @Return Part ID and revision. -+*//***************************************************************************/ -+e_P1023DeviceName P1023_GetRevInfo(uintptr_t gutilBase); -+ -+/**************************************************************************//** -+ @Function P1023_GetE500Factor -+ -+ @Description Returns E500 core clock multiplication factor. -+ -+ @Param[in] gutilBase - Base address of P1023 GUTIL registers. -+ @Param[in] coreId - Id of the requested core. -+ @Param[out] p_E500MulFactor - Returns E500 to CCB multification factor. -+ @Param[out] p_E500DivFactor - Returns E500 to CCB division factor. -+ -+ @Return E_OK on success; Other value otherwise. -+* -+*//***************************************************************************/ -+t_Error P1023_GetE500Factor(uintptr_t gutilBase, -+ uint32_t coreId, -+ uint32_t *p_E500MulFactor, -+ uint32_t *p_E500DivFactor); -+ -+/**************************************************************************//** -+ @Function P1023_GetFmFactor -+ -+ @Description returns FM multiplication factors. (This value is returned using -+ two parameters to avoid using float parameter). -+ -+ @Param[in] gutilBase - Base address of P1023 GUTIL registers. -+ @Param[out] p_FmMulFactor - returns E500 to CCB multification factor. -+ @Param[out] p_FmDivFactor - returns E500 to CCB division factor. -+ -+ @Return E_OK on success; Other value otherwise. -+*//***************************************************************************/ -+t_Error P1023_GetFmFactor(uintptr_t gutilBase, uint32_t *p_FmMulFactor, uint32_t *p_FmDivFactor); -+ -+/**************************************************************************//** -+ @Function P1023_GetCcbFactor -+ -+ @Description returns system multiplication factor. -+ -+ @Param[in] gutilBase - Base address of P1023 GUTIL registers. -+ -+ @Return System multiplication factor. -+*//***************************************************************************/ -+uint32_t P1023_GetCcbFactor(uintptr_t gutilBase); -+ -+#if 0 -+/**************************************************************************//** -+ @Function P1023_GetDdrFactor -+ -+ @Description returns the multiplication factor of the clock in for the DDR clock . -+ Note: assumes the ddr_in_clk is identical to the sys_in_clk -+ -+ @Param[in] gutilBase - Base address of P1023 GUTIL registers. -+ @Param p_DdrMulFactor - returns DDR in clk multification factor. -+ @Param p_DdrDivFactor - returns DDR division factor. -+ -+ @Return E_OK on success; Other value otherwise.. -+*//***************************************************************************/ -+t_Error P1023_GetDdrFactor( uintptr_t gutilBase, -+ uint32_t *p_DdrMulFactor, -+ uint32_t *p_DdrDivFactor); -+ -+/**************************************************************************//** -+ @Function P1023_GetDdrType -+ -+ @Description returns the multiplication factor of the clock in for the DDR clock . -+ -+ @Param[in] gutilBase - Base address of P1023 GUTIL registers. -+ @Param p_DdrType - (Out) returns DDR type DDR1/DDR2/DDR3. -+ -+ @Return E_OK on success; Other value otherwise. -+*//***************************************************************************/ -+t_Error P1023_GetDdrType(uintptr_t gutilBase, e_DdrType *p_DdrType ); -+#endif -+ -+/** @} */ /* end of 1023_init_grp group */ -+/** @} */ /* end of 1023_grp group */ -+ -+#define CORE_E500V2 -+ -+#if 0 /* using unified values */ -+/***************************************************************************** -+ INTEGRATION-SPECIFIC MODULE CODES -+******************************************************************************/ -+#define MODULE_UNKNOWN 0x00000000 -+#define MODULE_MEM 0x00010000 -+#define MODULE_MM 0x00020000 -+#define MODULE_CORE 0x00030000 -+#define MODULE_P1023 0x00040000 -+#define MODULE_MII 0x00050000 -+#define MODULE_PM 0x00060000 -+#define MODULE_MMU 0x00070000 -+#define MODULE_PIC 0x00080000 -+#define MODULE_L2_CACHE 0x00090000 -+#define MODULE_DUART 0x000a0000 -+#define MODULE_SERDES 0x000b0000 -+#define MODULE_PIO 0x000c0000 -+#define MODULE_QM 0x000d0000 -+#define MODULE_BM 0x000e0000 -+#define MODULE_SEC 0x000f0000 -+#define MODULE_FM 0x00100000 -+#define MODULE_FM_MURAM 0x00110000 -+#define MODULE_FM_PCD 0x00120000 -+#define MODULE_FM_RTC 0x00130000 -+#define MODULE_FM_MAC 0x00140000 -+#define MODULE_FM_PORT 0x00150000 -+#define MODULE_FM_MACSEC 0x00160000 -+#define MODULE_FM_MACSEC_SECY 0x00170000 -+#define MODULE_FM_SP 0x00280000 -+#define MODULE_ECM 0x00190000 -+#define MODULE_DMA 0x001a0000 -+#define MODULE_DDR 0x001b0000 -+#define MODULE_LAW 0x001c0000 -+#define MODULE_LBC 0x001d0000 -+#define MODULE_I2C 0x001e0000 -+#define MODULE_ESPI 0x001f0000 -+#define MODULE_PCI 0x00200000 -+#define MODULE_DPA_PORT 0x00210000 -+#define MODULE_USB 0x00220000 -+#endif /* using unified values */ -+ -+/***************************************************************************** -+ LBC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+/**************************************************************************//** -+ @Group lbc_exception_grp LBC Exception Unit -+ -+ @Description LBC Exception unit API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Anchor lbc_exbm -+ -+ @Collection LBC Errors Bit Mask -+ -+ These errors are reported through the exceptions callback.. -+ The values can be or'ed in any combination in the errors mask -+ parameter of the errors report structure. -+ -+ These errors can also be passed as a bit-mask to -+ LBC_EnableErrorChecking() or LBC_DisableErrorChecking(), -+ for enabling or disabling error checking. -+ @{ -+*//***************************************************************************/ -+#define LBC_ERR_BUS_MONITOR 0x80000000 /**< Bus monitor error */ -+#define LBC_ERR_PARITY_ECC 0x20000000 /**< Parity error for GPCM/UPM */ -+#define LBC_ERR_WRITE_PROTECT 0x04000000 /**< Write protection error */ -+#define LBC_ERR_CHIP_SELECT 0x00080000 /**< Unrecognized chip select */ -+ -+#define LBC_ERR_ALL (LBC_ERR_BUS_MONITOR | LBC_ERR_PARITY_ECC | \ -+ LBC_ERR_WRITE_PROTECT | LBC_ERR_CHIP_SELECT) -+ /**< All possible errors */ -+/* @} */ -+/** @} */ /* end of lbc_exception_grp group */ -+ -+#define LBC_NUM_OF_BANKS 2 -+#define LBC_MAX_CS_SIZE 0x0000000100000000LL -+#define LBC_ATOMIC_OPERATION_SUPPORT -+#define LBC_PARITY_SUPPORT -+#define LBC_ADDRESS_SHIFT_SUPPORT -+#define LBC_ADDRESS_HOLD_TIME_CTRL -+#define LBC_HIGH_CLK_DIVIDERS -+#define LBC_FCM_AVAILABLE -+ -+ -+/***************************************************************************** -+ LAW INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define LAW_ARCH_CCB -+#define LAW_NUM_OF_WINDOWS 12 -+#define LAW_MIN_WINDOW_SIZE 0x0000000000001000LL /**< 4KB */ -+#define LAW_MAX_WINDOW_SIZE 0x0000001000000000LL /**< 32GB */ -+ -+ -+/***************************************************************************** -+ SPI INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define SPI_NUM_OF_CONTROLLERS 1 -+ -+/***************************************************************************** -+ PCI/PCIe INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+ -+#define PCI_MAX_INBOUND_WINDOWS_NUM 4 -+#define PCI_MAX_OUTBOUND_WINDOWS_NUM 5 -+ -+/**************************************************************************//** -+ @Description Target interface of an inbound window -+*//***************************************************************************/ -+typedef enum e_PciTargetInterface -+{ -+ e_PCI_TARGET_PCIE_2 = 0x1, /**< PCI Express target interface 2 */ -+ e_PCI_TARGET_PCIE_1 = 0x2, /**< PCI Express target interface 1 */ -+ e_PCI_TARGET_PCIE_3 = 0x3, /**< PCI Express target interface 3 */ -+ e_PCI_TARGET_LOCAL_MEMORY = 0xF /**< Local Memory (DDR SDRAM, Local Bus, SRAM) target interface */ -+ -+} e_PciTargetInterface; -+ -+/***************************************************************************** -+ DDR INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define DDR_NUM_OF_VALID_CS 2 -+ -+/***************************************************************************** -+ SEC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define SEC_ERRATA_STAT_REGS_UNUSABLE -+ -+/***************************************************************************** -+ DMA INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define DMA_NUM_OF_CONTROLLERS 2 -+ -+ -+ -+ -+/***************************************************************************** -+ 1588 INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define PTP_V2 -+ -+/**************************************************************************//** -+ @Function P1023_GetMuxControlReg -+ -+ @Description Returns the value of PMUXCR (Alternate Function Signal Multiplex -+ Control Register) -+ -+ @Param[in] gutilBase - Base address of P1023 GUTIL registers. -+ -+ @Return Value of PMUXCR -+*//***************************************************************************/ -+uint32_t P1023_GetMuxControlReg(uintptr_t gutilBase); -+ -+/**************************************************************************//** -+ @Function P1023_SetMuxControlReg -+ -+ @Description Sets the value of PMUXCR (Alternate Function Signal Multiplex -+ Control Register) -+ -+ @Param[in] gutilBase - Base address of P1023 GUTIL registers. -+ @Param[in] val - the new value for PMUXCR. -+ -+ @Return None -+*//***************************************************************************/ -+void P1023_SetMuxControlReg(uintptr_t gutilBase, uint32_t val); -+ -+/**************************************************************************//** -+ @Function P1023_GetDeviceDisableStatusRegister -+ -+ @Description Returns the value of DEVDISR (Device Disable Register) -+ -+ @Param[in] gutilBase - Base address of P1023 GUTIL registers. -+ -+ @Return Value of DEVDISR -+*//***************************************************************************/ -+uint32_t P1023_GetDeviceDisableStatusRegister(uintptr_t gutilBase); -+ -+/**************************************************************************//** -+ @Function P1023_GetPorDeviceStatusRegister -+ -+ @Description Returns the value of POR Device Status Register -+ -+ @Param[in] gutilBase - Base address of P1023 GUTIL registers. -+ -+ @Return POR Device Status Register -+*//***************************************************************************/ -+uint32_t P1023_GetPorDeviceStatusRegister(uintptr_t gutilBase); -+ -+/**************************************************************************//** -+ @Function P1023_GetPorBootModeStatusRegister -+ -+ @Description Returns the value of POR Boot Mode Status Register -+ -+ @Param[in] gutilBase - Base address of P1023 GUTIL registers. -+ -+ @Return POR Boot Mode Status Register value -+*//***************************************************************************/ -+uint32_t P1023_GetPorBootModeStatusRegister(uintptr_t gutilBase); -+ -+ -+#define PORDEVSR_SGMII1_DIS 0x10000000 -+#define PORDEVSR_SGMII2_DIS 0x08000000 -+#define PORDEVSR_ECP1 0x02000000 -+#define PORDEVSR_IO_SEL 0x00780000 -+#define PORDEVSR_IO_SEL_SHIFT 19 -+#define PORBMSR_HA 0x00070000 -+#define PORBMSR_HA_SHIFT 16 -+ -+#define DEVDISR_QM_BM 0x80000000 -+#define DEVDISR_FM 0x40000000 -+#define DEVDISR_PCIE1 0x20000000 -+#define DEVDISR_MAC_SEC 0x10000000 -+#define DEVDISR_ELBC 0x08000000 -+#define DEVDISR_PCIE2 0x04000000 -+#define DEVDISR_PCIE3 0x02000000 -+#define DEVDISR_CAAM 0x01000000 -+#define DEVDISR_USB0 0x00800000 -+#define DEVDISR_1588 0x00020000 -+#define DEVDISR_CORE0 0x00008000 -+#define DEVDISR_TB0 0x00004000 -+#define DEVDISR_CORE1 0x00002000 -+#define DEVDISR_TB1 0x00001000 -+#define DEVDISR_DMA1 0x00000400 -+#define DEVDISR_DMA2 0x00000200 -+#define DEVDISR_DDR 0x00000010 -+#define DEVDISR_TSEC1 0x00000080 -+#define DEVDISR_TSEC2 0x00000040 -+#define DEVDISR_SPI 0x00000008 -+#define DEVDISR_I2C 0x00000004 -+#define DEVDISR_DUART 0x00000002 -+ -+ -+#endif /* __PART_INTEGRATION_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P3040_P4080_P5020/dpaa_integration_ext.h -@@ -0,0 +1,276 @@ -+/* Copyright (c) 2009-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ @File dpaa_integration_ext.h -+ -+ @Description P3040/P4080/P5020 FM external definitions and structures. -+*//***************************************************************************/ -+#ifndef __DPAA_INTEGRATION_EXT_H -+#define __DPAA_INTEGRATION_EXT_H -+ -+#include "std_ext.h" -+ -+ -+#define DPAA_VERSION 10 -+ -+typedef enum { -+ e_DPAA_SWPORTAL0 = 0, -+ e_DPAA_SWPORTAL1, -+ e_DPAA_SWPORTAL2, -+ e_DPAA_SWPORTAL3, -+ e_DPAA_SWPORTAL4, -+ e_DPAA_SWPORTAL5, -+ e_DPAA_SWPORTAL6, -+ e_DPAA_SWPORTAL7, -+ e_DPAA_SWPORTAL8, -+ e_DPAA_SWPORTAL9, -+ e_DPAA_SWPORTAL_DUMMY_LAST -+} e_DpaaSwPortal; -+ -+typedef enum { -+ e_DPAA_DCPORTAL0 = 0, -+ e_DPAA_DCPORTAL1, -+ e_DPAA_DCPORTAL2, -+ e_DPAA_DCPORTAL3, -+ e_DPAA_DCPORTAL4, -+ e_DPAA_DCPORTAL_DUMMY_LAST -+} e_DpaaDcPortal; -+ -+#define DPAA_MAX_NUM_OF_SW_PORTALS e_DPAA_SWPORTAL_DUMMY_LAST -+#define DPAA_MAX_NUM_OF_DC_PORTALS e_DPAA_DCPORTAL_DUMMY_LAST -+ -+/***************************************************************************** -+ QMan INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define QM_MAX_NUM_OF_POOL_CHANNELS 15 /**< Total number of channels, dedicated and pool */ -+#define QM_MAX_NUM_OF_WQ 8 /**< Number of work queues per channel */ -+#define QM_MAX_NUM_OF_SWP_AS 4 -+#define QM_MAX_NUM_OF_CGS 256 /**< Number of congestion groups */ -+#define QM_MAX_NUM_OF_FQIDS (16 * MEGABYTE) /**< FQIDs range - 24 bits */ -+ -+/**************************************************************************//** -+ @Description Work Queue Channel assignments in QMan. -+*//***************************************************************************/ -+typedef enum -+{ -+ e_QM_FQ_CHANNEL_SWPORTAL0 = 0, /**< Dedicated channels serviced by software portals 0 to 9 */ -+ e_QM_FQ_CHANNEL_SWPORTAL1, -+ e_QM_FQ_CHANNEL_SWPORTAL2, -+ e_QM_FQ_CHANNEL_SWPORTAL3, -+ e_QM_FQ_CHANNEL_SWPORTAL4, -+ e_QM_FQ_CHANNEL_SWPORTAL5, -+ e_QM_FQ_CHANNEL_SWPORTAL6, -+ e_QM_FQ_CHANNEL_SWPORTAL7, -+ e_QM_FQ_CHANNEL_SWPORTAL8, -+ e_QM_FQ_CHANNEL_SWPORTAL9, -+ -+ e_QM_FQ_CHANNEL_POOL1 = 0x21, /**< Pool channels that can be serviced by any of the software portals */ -+ e_QM_FQ_CHANNEL_POOL2, -+ e_QM_FQ_CHANNEL_POOL3, -+ e_QM_FQ_CHANNEL_POOL4, -+ e_QM_FQ_CHANNEL_POOL5, -+ e_QM_FQ_CHANNEL_POOL6, -+ e_QM_FQ_CHANNEL_POOL7, -+ e_QM_FQ_CHANNEL_POOL8, -+ e_QM_FQ_CHANNEL_POOL9, -+ e_QM_FQ_CHANNEL_POOL10, -+ e_QM_FQ_CHANNEL_POOL11, -+ e_QM_FQ_CHANNEL_POOL12, -+ e_QM_FQ_CHANNEL_POOL13, -+ e_QM_FQ_CHANNEL_POOL14, -+ e_QM_FQ_CHANNEL_POOL15, -+ -+ e_QM_FQ_CHANNEL_FMAN0_SP0 = 0x40, /**< Dedicated channels serviced by Direct Connect Portal 0: -+ connected to FMan 0; assigned in incrementing order to -+ each sub-portal (SP) in the portal */ -+ e_QM_FQ_CHANNEL_FMAN0_SP1, -+ e_QM_FQ_CHANNEL_FMAN0_SP2, -+ e_QM_FQ_CHANNEL_FMAN0_SP3, -+ e_QM_FQ_CHANNEL_FMAN0_SP4, -+ e_QM_FQ_CHANNEL_FMAN0_SP5, -+ e_QM_FQ_CHANNEL_FMAN0_SP6, -+ e_QM_FQ_CHANNEL_FMAN0_SP7, -+ e_QM_FQ_CHANNEL_FMAN0_SP8, -+ e_QM_FQ_CHANNEL_FMAN0_SP9, -+ e_QM_FQ_CHANNEL_FMAN0_SP10, -+ e_QM_FQ_CHANNEL_FMAN0_SP11, -+/* difference between 5020 and 4080 :) */ -+ e_QM_FQ_CHANNEL_FMAN1_SP0 = 0x60, -+ e_QM_FQ_CHANNEL_FMAN1_SP1, -+ e_QM_FQ_CHANNEL_FMAN1_SP2, -+ e_QM_FQ_CHANNEL_FMAN1_SP3, -+ e_QM_FQ_CHANNEL_FMAN1_SP4, -+ e_QM_FQ_CHANNEL_FMAN1_SP5, -+ e_QM_FQ_CHANNEL_FMAN1_SP6, -+ e_QM_FQ_CHANNEL_FMAN1_SP7, -+ e_QM_FQ_CHANNEL_FMAN1_SP8, -+ e_QM_FQ_CHANNEL_FMAN1_SP9, -+ e_QM_FQ_CHANNEL_FMAN1_SP10, -+ e_QM_FQ_CHANNEL_FMAN1_SP11, -+ -+ e_QM_FQ_CHANNEL_CAAM = 0x80, /**< Dedicated channel serviced by Direct Connect Portal 2: -+ connected to SEC 4.x */ -+ -+ e_QM_FQ_CHANNEL_PME = 0xA0, /**< Dedicated channel serviced by Direct Connect Portal 3: -+ connected to PME */ -+ e_QM_FQ_CHANNEL_RAID = 0xC0 /**< Dedicated channel serviced by Direct Connect Portal 4: -+ connected to RAID */ -+} e_QmFQChannel; -+ -+/***************************************************************************** -+ BMan INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define BM_MAX_NUM_OF_POOLS 64 /**< Number of buffers pools */ -+ -+ -+/***************************************************************************** -+ FM INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define INTG_MAX_NUM_OF_FM 2 -+ -+/* Ports defines */ -+#define FM_MAX_NUM_OF_1G_MACS 5 -+#define FM_MAX_NUM_OF_10G_MACS 1 -+#define FM_MAX_NUM_OF_MACS (FM_MAX_NUM_OF_1G_MACS + FM_MAX_NUM_OF_10G_MACS) -+#define FM_MAX_NUM_OF_OH_PORTS 7 -+ -+#define FM_MAX_NUM_OF_1G_RX_PORTS FM_MAX_NUM_OF_1G_MACS -+#define FM_MAX_NUM_OF_10G_RX_PORTS FM_MAX_NUM_OF_10G_MACS -+#define FM_MAX_NUM_OF_RX_PORTS (FM_MAX_NUM_OF_10G_RX_PORTS + FM_MAX_NUM_OF_1G_RX_PORTS) -+ -+#define FM_MAX_NUM_OF_1G_TX_PORTS FM_MAX_NUM_OF_1G_MACS -+#define FM_MAX_NUM_OF_10G_TX_PORTS FM_MAX_NUM_OF_10G_MACS -+#define FM_MAX_NUM_OF_TX_PORTS (FM_MAX_NUM_OF_10G_TX_PORTS + FM_MAX_NUM_OF_1G_TX_PORTS) -+ -+#define FM_PORT_MAX_NUM_OF_EXT_POOLS 8 /**< Number of external BM pools per Rx port */ -+#define FM_PORT_NUM_OF_CONGESTION_GRPS 256 /**< Total number of congestion groups in QM */ -+#define FM_MAX_NUM_OF_SUB_PORTALS 12 -+#define FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS 0 -+ -+/* Rams defines */ -+#define FM_MURAM_SIZE (160*KILOBYTE) -+#define FM_IRAM_SIZE(major, minor) (64 * KILOBYTE) -+#define FM_NUM_OF_CTRL 2 -+ -+/* PCD defines */ -+#define FM_PCD_PLCR_NUM_ENTRIES 256 /**< Total number of policer profiles */ -+#define FM_PCD_KG_NUM_OF_SCHEMES 32 /**< Total number of KG schemes */ -+#define FM_PCD_MAX_NUM_OF_CLS_PLANS 256 /**< Number of classification plan entries. */ -+#define FM_PCD_PRS_SW_PATCHES_SIZE 0x00000200 /**< Number of bytes saved for patches */ -+#define FM_PCD_SW_PRS_SIZE 0x00000800 /**< Total size of SW parser area */ -+ -+/* RTC defines */ -+#define FM_RTC_NUM_OF_ALARMS 2 /**< RTC number of alarms */ -+#define FM_RTC_NUM_OF_PERIODIC_PULSES 2 /**< RTC number of periodic pulses */ -+#define FM_RTC_NUM_OF_EXT_TRIGGERS 2 /**< RTC number of external triggers */ -+ -+/* QMI defines */ -+#define QMI_MAX_NUM_OF_TNUMS 64 -+#define QMI_DEF_TNUMS_THRESH 48 -+ -+/* FPM defines */ -+#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4 -+ -+/* DMA defines */ -+#define DMA_THRESH_MAX_COMMQ 31 -+#define DMA_THRESH_MAX_BUF 127 -+ -+/* BMI defines */ -+#define BMI_MAX_NUM_OF_TASKS 128 -+#define BMI_MAX_NUM_OF_DMAS 32 -+#define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE) -+#define PORT_MAX_WEIGHT 16 -+ -+ -+#define FM_CHECK_PORT_RESTRICTIONS(__validPorts, __newPortIndx) TRUE -+ -+/* p4080-rev1 unique features */ -+#define QM_CGS_NO_FRAME_MODE -+ -+/* p4080 unique features */ -+#define FM_NO_DISPATCH_RAM_ECC -+#define FM_NO_WATCHDOG -+#define FM_NO_TNUM_AGING -+#define FM_KG_NO_BYPASS_FQID_GEN -+#define FM_KG_NO_BYPASS_PLCR_PROFILE_GEN -+#define FM_NO_BACKUP_POOLS -+#define FM_NO_OP_OBSERVED_POOLS -+#define FM_NO_ADVANCED_RATE_LIMITER -+#define FM_NO_OP_OBSERVED_CGS -+#define FM_HAS_TOTAL_DMAS -+#define FM_KG_NO_IPPID_SUPPORT -+#define FM_NO_GUARANTEED_RESET_VALUES -+#define FM_MAC_RESET -+ -+/* FM erratas */ -+#define FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 -+#define FM_TX_SHORT_FRAME_BAD_TS_ERRATA_10GMAC_A006 /* No implementation, Out of LLD scope */ -+#define FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007 -+#define FM_ECC_HALT_NO_SYNC_ERRATA_10GMAC_A008 -+#define FM_TX_INVALID_ECC_ERRATA_10GMAC_A009 /* Out of LLD scope, user may disable ECC exceptions using FM_DisableRamsEcc */ -+#define FM_BAD_VLAN_DETECT_ERRATA_10GMAC_A010 -+ -+#define FM_RX_PREAM_4_ERRATA_DTSEC_A001 -+#define FM_GRS_ERRATA_DTSEC_A002 -+#define FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 -+#define FM_GTS_ERRATA_DTSEC_A004 -+#define FM_GTS_AFTER_MAC_ABORTED_FRAME_ERRATA_DTSEC_A0012 -+#define FM_GTS_UNDERRUN_ERRATA_DTSEC_A0014 -+#define FM_GTS_AFTER_DROPPED_FRAME_ERRATA_DTSEC_A004839 -+ -+#define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */ -+#define FM_TX_LOCKUP_ERRATA_DTSEC6 -+ -+#define FM_HC_DEF_FQID_ONLY_ERRATA_FMAN_A003 /* Implemented by ucode */ -+#define FM_DEBUG_TRACE_FMAN_A004 /* No implementation, Out of LLD scope */ -+ -+#define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 -+ -+#define FM_10G_REM_N_LCL_FLT_EX_10GMAC_ERRATA_SW005 -+ -+#define FM_LEN_CHECK_ERRATA_FMAN_SW002 -+ -+#define FM_NO_CTXA_COPY_ERRATA_FMAN_SW001 -+#define FM_KG_ERASE_FLOW_ID_ERRATA_FMAN_SW004 -+ -+/***************************************************************************** -+ FM MACSEC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define NUM_OF_RX_SC 16 -+#define NUM_OF_TX_SC 16 -+ -+#define NUM_OF_SA_PER_RX_SC 2 -+#define NUM_OF_SA_PER_TX_SC 2 -+ -+ -+#endif /* __DPAA_INTEGRATION_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P3040_P4080_P5020/part_ext.h -@@ -0,0 +1,83 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ -+ @File part_ext.h -+ -+ @Description Definitions for the part (integration) module. -+*//***************************************************************************/ -+ -+#ifndef __PART_EXT_H -+#define __PART_EXT_H -+ -+#include "std_ext.h" -+#include "part_integration_ext.h" -+ -+ -+#if !(defined(MPC8306) || \ -+ defined(MPC8309) || \ -+ defined(MPC834x) || \ -+ defined(MPC836x) || \ -+ defined(MPC832x) || \ -+ defined(MPC837x) || \ -+ defined(MPC8568) || \ -+ defined(MPC8569) || \ -+ defined(P1020) || \ -+ defined(P1021) || \ -+ defined(P1022) || \ -+ defined(P1023) || \ -+ defined(P2020) || \ -+ defined(P2040) || \ -+ defined(P3041) || \ -+ defined(P4080) || \ -+ defined(SC4080) || \ -+ defined(P5020) || \ -+ defined(MSC814x)) -+#error "unable to proceed without chip-definition" -+#endif /* !(defined(MPC834x) || ... */ -+ -+ -+/**************************************************************************//* -+ @Description Part data structure - must be contained in any integration -+ data structure. -+*//***************************************************************************/ -+typedef struct t_Part -+{ -+ uintptr_t (* f_GetModuleBase)(t_Handle h_Part, e_ModuleId moduleId); -+ /**< Returns the address of the module's memory map base. */ -+ e_ModuleId (* f_GetModuleIdByBase)(t_Handle h_Part, uintptr_t baseAddress); -+ /**< Returns the module's ID according to its memory map base. */ -+} t_Part; -+ -+ -+#endif /* __PART_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/integrations/P3040_P4080_P5020/part_integration_ext.h -@@ -0,0 +1,336 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ @File part_integration_ext.h -+ -+ @Description P3040/P4080/P5020 external definitions and structures. -+*//***************************************************************************/ -+#ifndef __PART_INTEGRATION_EXT_H -+#define __PART_INTEGRATION_EXT_H -+ -+#include "std_ext.h" -+#include "dpaa_integration_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group P3040/P4080/P5020_chip_id P5020 Application Programming Interface -+ -+ @Description P3040/P4080/P5020 Chip functions,definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+#define CORE_E500MC -+ -+#define INTG_MAX_NUM_OF_CORES 1 -+ -+ -+/**************************************************************************//** -+ @Description Module types. -+*//***************************************************************************/ -+typedef enum e_ModuleId -+{ -+ e_MODULE_ID_DUART_1 = 0, -+ e_MODULE_ID_DUART_2, -+ e_MODULE_ID_DUART_3, -+ e_MODULE_ID_DUART_4, -+ e_MODULE_ID_LAW, -+ e_MODULE_ID_LBC, -+ e_MODULE_ID_PAMU, -+ e_MODULE_ID_QM, /**< Queue manager module */ -+ e_MODULE_ID_BM, /**< Buffer manager module */ -+ e_MODULE_ID_QM_CE_PORTAL_0, -+ e_MODULE_ID_QM_CI_PORTAL_0, -+ e_MODULE_ID_QM_CE_PORTAL_1, -+ e_MODULE_ID_QM_CI_PORTAL_1, -+ e_MODULE_ID_QM_CE_PORTAL_2, -+ e_MODULE_ID_QM_CI_PORTAL_2, -+ e_MODULE_ID_QM_CE_PORTAL_3, -+ e_MODULE_ID_QM_CI_PORTAL_3, -+ e_MODULE_ID_QM_CE_PORTAL_4, -+ e_MODULE_ID_QM_CI_PORTAL_4, -+ e_MODULE_ID_QM_CE_PORTAL_5, -+ e_MODULE_ID_QM_CI_PORTAL_5, -+ e_MODULE_ID_QM_CE_PORTAL_6, -+ e_MODULE_ID_QM_CI_PORTAL_6, -+ e_MODULE_ID_QM_CE_PORTAL_7, -+ e_MODULE_ID_QM_CI_PORTAL_7, -+ e_MODULE_ID_QM_CE_PORTAL_8, -+ e_MODULE_ID_QM_CI_PORTAL_8, -+ e_MODULE_ID_QM_CE_PORTAL_9, -+ e_MODULE_ID_QM_CI_PORTAL_9, -+ e_MODULE_ID_BM_CE_PORTAL_0, -+ e_MODULE_ID_BM_CI_PORTAL_0, -+ e_MODULE_ID_BM_CE_PORTAL_1, -+ e_MODULE_ID_BM_CI_PORTAL_1, -+ e_MODULE_ID_BM_CE_PORTAL_2, -+ e_MODULE_ID_BM_CI_PORTAL_2, -+ e_MODULE_ID_BM_CE_PORTAL_3, -+ e_MODULE_ID_BM_CI_PORTAL_3, -+ e_MODULE_ID_BM_CE_PORTAL_4, -+ e_MODULE_ID_BM_CI_PORTAL_4, -+ e_MODULE_ID_BM_CE_PORTAL_5, -+ e_MODULE_ID_BM_CI_PORTAL_5, -+ e_MODULE_ID_BM_CE_PORTAL_6, -+ e_MODULE_ID_BM_CI_PORTAL_6, -+ e_MODULE_ID_BM_CE_PORTAL_7, -+ e_MODULE_ID_BM_CI_PORTAL_7, -+ e_MODULE_ID_BM_CE_PORTAL_8, -+ e_MODULE_ID_BM_CI_PORTAL_8, -+ e_MODULE_ID_BM_CE_PORTAL_9, -+ e_MODULE_ID_BM_CI_PORTAL_9, -+ e_MODULE_ID_FM1, /**< Frame manager #1 module */ -+ e_MODULE_ID_FM1_RTC, /**< FM Real-Time-Clock */ -+ e_MODULE_ID_FM1_MURAM, /**< FM Multi-User-RAM */ -+ e_MODULE_ID_FM1_BMI, /**< FM BMI block */ -+ e_MODULE_ID_FM1_QMI, /**< FM QMI block */ -+ e_MODULE_ID_FM1_PRS, /**< FM parser block */ -+ e_MODULE_ID_FM1_PORT_HO0, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM1_PORT_HO1, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM1_PORT_HO2, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM1_PORT_HO3, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM1_PORT_HO4, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM1_PORT_HO5, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM1_PORT_HO6, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM1_PORT_1GRx0, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM1_PORT_1GRx1, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM1_PORT_1GRx2, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM1_PORT_1GRx3, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM1_PORT_1GRx4, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM1_PORT_10GRx0, /**< FM Rx 10G MAC port block */ -+ e_MODULE_ID_FM1_PORT_1GTx0, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM1_PORT_1GTx1, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM1_PORT_1GTx2, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM1_PORT_1GTx3, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM1_PORT_1GTx4, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM1_PORT_10GTx0, /**< FM Tx 10G MAC port block */ -+ e_MODULE_ID_FM1_PLCR, /**< FM Policer */ -+ e_MODULE_ID_FM1_KG, /**< FM Keygen */ -+ e_MODULE_ID_FM1_DMA, /**< FM DMA */ -+ e_MODULE_ID_FM1_FPM, /**< FM FPM */ -+ e_MODULE_ID_FM1_IRAM, /**< FM Instruction-RAM */ -+ e_MODULE_ID_FM1_1GMDIO0, /**< FM 1G MDIO MAC 0*/ -+ e_MODULE_ID_FM1_1GMDIO1, /**< FM 1G MDIO MAC 1*/ -+ e_MODULE_ID_FM1_1GMDIO2, /**< FM 1G MDIO MAC 2*/ -+ e_MODULE_ID_FM1_1GMDIO3, /**< FM 1G MDIO MAC 3*/ -+ e_MODULE_ID_FM1_10GMDIO, /**< FM 10G MDIO */ -+ e_MODULE_ID_FM1_PRS_IRAM, /**< FM SW-parser Instruction-RAM */ -+ e_MODULE_ID_FM1_1GMAC0, /**< FM 1G MAC #0 */ -+ e_MODULE_ID_FM1_1GMAC1, /**< FM 1G MAC #1 */ -+ e_MODULE_ID_FM1_1GMAC2, /**< FM 1G MAC #2 */ -+ e_MODULE_ID_FM1_1GMAC3, /**< FM 1G MAC #3 */ -+ e_MODULE_ID_FM1_10GMAC0, /**< FM 10G MAC #0 */ -+ -+ e_MODULE_ID_FM2, /**< Frame manager #2 module */ -+ e_MODULE_ID_FM2_RTC, /**< FM Real-Time-Clock */ -+ e_MODULE_ID_FM2_MURAM, /**< FM Multi-User-RAM */ -+ e_MODULE_ID_FM2_BMI, /**< FM BMI block */ -+ e_MODULE_ID_FM2_QMI, /**< FM QMI block */ -+ e_MODULE_ID_FM2_PRS, /**< FM parser block */ -+ e_MODULE_ID_FM2_PORT_HO0, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM2_PORT_HO1, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM2_PORT_HO2, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM2_PORT_HO3, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM2_PORT_HO4, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM2_PORT_HO5, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM2_PORT_HO6, /**< FM Host-command/offline-parsing port block */ -+ e_MODULE_ID_FM2_PORT_1GRx0, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM2_PORT_1GRx1, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM2_PORT_1GRx2, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM2_PORT_1GRx3, /**< FM Rx 1G MAC port block */ -+ e_MODULE_ID_FM2_PORT_10GRx0, /**< FM Rx 10G MAC port block */ -+ e_MODULE_ID_FM2_PORT_1GTx0, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM2_PORT_1GTx1, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM2_PORT_1GTx2, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM2_PORT_1GTx3, /**< FM Tx 1G MAC port block */ -+ e_MODULE_ID_FM2_PORT_10GTx0, /**< FM Tx 10G MAC port block */ -+ e_MODULE_ID_FM2_PLCR, /**< FM Policer */ -+ e_MODULE_ID_FM2_KG, /**< FM Keygen */ -+ e_MODULE_ID_FM2_DMA, /**< FM DMA */ -+ e_MODULE_ID_FM2_FPM, /**< FM FPM */ -+ e_MODULE_ID_FM2_IRAM, /**< FM Instruction-RAM */ -+ e_MODULE_ID_FM2_1GMDIO0, /**< FM 1G MDIO MAC 0*/ -+ e_MODULE_ID_FM2_1GMDIO1, /**< FM 1G MDIO MAC 1*/ -+ e_MODULE_ID_FM2_1GMDIO2, /**< FM 1G MDIO MAC 2*/ -+ e_MODULE_ID_FM2_1GMDIO3, /**< FM 1G MDIO MAC 3*/ -+ e_MODULE_ID_FM2_10GMDIO, /**< FM 10G MDIO */ -+ e_MODULE_ID_FM2_PRS_IRAM, /**< FM SW-parser Instruction-RAM */ -+ e_MODULE_ID_FM2_1GMAC0, /**< FM 1G MAC #0 */ -+ e_MODULE_ID_FM2_1GMAC1, /**< FM 1G MAC #1 */ -+ e_MODULE_ID_FM2_1GMAC2, /**< FM 1G MAC #2 */ -+ e_MODULE_ID_FM2_1GMAC3, /**< FM 1G MAC #3 */ -+ e_MODULE_ID_FM2_10GMAC0, /**< FM 10G MAC #0 */ -+ -+ e_MODULE_ID_SEC_GEN, /**< SEC 4.0 General registers */ -+ e_MODULE_ID_SEC_QI, /**< SEC 4.0 QI registers */ -+ e_MODULE_ID_SEC_JQ0, /**< SEC 4.0 JQ-0 registers */ -+ e_MODULE_ID_SEC_JQ1, /**< SEC 4.0 JQ-1 registers */ -+ e_MODULE_ID_SEC_JQ2, /**< SEC 4.0 JQ-2 registers */ -+ e_MODULE_ID_SEC_JQ3, /**< SEC 4.0 JQ-3 registers */ -+ e_MODULE_ID_SEC_RTIC, /**< SEC 4.0 RTIC registers */ -+ e_MODULE_ID_SEC_DECO0_CCB0, /**< SEC 4.0 DECO-0/CCB-0 registers */ -+ e_MODULE_ID_SEC_DECO1_CCB1, /**< SEC 4.0 DECO-1/CCB-1 registers */ -+ e_MODULE_ID_SEC_DECO2_CCB2, /**< SEC 4.0 DECO-2/CCB-2 registers */ -+ e_MODULE_ID_SEC_DECO3_CCB3, /**< SEC 4.0 DECO-3/CCB-3 registers */ -+ e_MODULE_ID_SEC_DECO4_CCB4, /**< SEC 4.0 DECO-4/CCB-4 registers */ -+ -+ e_MODULE_ID_MPIC, /**< MPIC */ -+ e_MODULE_ID_GPIO, /**< GPIO */ -+ e_MODULE_ID_SERDES, /**< SERDES */ -+ e_MODULE_ID_CPC_1, /**< CoreNet-Platform-Cache 1 */ -+ e_MODULE_ID_CPC_2, /**< CoreNet-Platform-Cache 2 */ -+ -+ e_MODULE_ID_SRIO_PORTS, /**< RapidIO controller */ -+ e_MODULE_ID_SRIO_MU, /**< RapidIO messaging unit module */ -+ -+ e_MODULE_ID_DUMMY_LAST -+} e_ModuleId; -+ -+#define NUM_OF_MODULES e_MODULE_ID_DUMMY_LAST -+ -+#if 0 /* using unified values */ -+/***************************************************************************** -+ INTEGRATION-SPECIFIC MODULE CODES -+******************************************************************************/ -+#define MODULE_UNKNOWN 0x00000000 -+#define MODULE_MEM 0x00010000 -+#define MODULE_MM 0x00020000 -+#define MODULE_CORE 0x00030000 -+#define MODULE_CHIP 0x00040000 -+#define MODULE_PLTFRM 0x00050000 -+#define MODULE_PM 0x00060000 -+#define MODULE_MMU 0x00070000 -+#define MODULE_PIC 0x00080000 -+#define MODULE_CPC 0x00090000 -+#define MODULE_DUART 0x000a0000 -+#define MODULE_SERDES 0x000b0000 -+#define MODULE_PIO 0x000c0000 -+#define MODULE_QM 0x000d0000 -+#define MODULE_BM 0x000e0000 -+#define MODULE_SEC 0x000f0000 -+#define MODULE_LAW 0x00100000 -+#define MODULE_LBC 0x00110000 -+#define MODULE_PAMU 0x00120000 -+#define MODULE_FM 0x00130000 -+#define MODULE_FM_MURAM 0x00140000 -+#define MODULE_FM_PCD 0x00150000 -+#define MODULE_FM_RTC 0x00160000 -+#define MODULE_FM_MAC 0x00170000 -+#define MODULE_FM_PORT 0x00180000 -+#define MODULE_FM_SP 0x00190000 -+#define MODULE_DPA_PORT 0x001a0000 -+#define MODULE_MII 0x001b0000 -+#define MODULE_I2C 0x001c0000 -+#define MODULE_DMA 0x001d0000 -+#define MODULE_DDR 0x001e0000 -+#define MODULE_ESPI 0x001f0000 -+#define MODULE_DPAA_IPSEC 0x00200000 -+#endif /* using unified values */ -+ -+/***************************************************************************** -+ PAMU INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define PAMU_NUM_OF_PARTITIONS 5 -+ -+#define PAMU_PICS_AVICS_ERRATA_PAMU3 -+ -+/***************************************************************************** -+ LAW INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define LAW_NUM_OF_WINDOWS 32 -+#define LAW_MIN_WINDOW_SIZE 0x0000000000001000LL /**< 4KB */ -+#define LAW_MAX_WINDOW_SIZE 0x0000002000000000LL /**< 64GB */ -+ -+ -+/***************************************************************************** -+ LBC INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+/**************************************************************************//** -+ @Group lbc_exception_grp LBC Exception Unit -+ -+ @Description LBC Exception unit API functions, definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Anchor lbc_exbm -+ -+ @Collection LBC Errors Bit Mask -+ -+ These errors are reported through the exceptions callback.. -+ The values can be or'ed in any combination in the errors mask -+ parameter of the errors report structure. -+ -+ These errors can also be passed as a bit-mask to -+ LBC_EnableErrorChecking() or LBC_DisableErrorChecking(), -+ for enabling or disabling error checking. -+ @{ -+*//***************************************************************************/ -+#define LBC_ERR_BUS_MONITOR 0x80000000 /**< Bus monitor error */ -+#define LBC_ERR_PARITY_ECC 0x20000000 /**< Parity error for GPCM/UPM */ -+#define LBC_ERR_WRITE_PROTECT 0x04000000 /**< Write protection error */ -+#define LBC_ERR_ATOMIC_WRITE 0x00800000 /**< Atomic write error */ -+#define LBC_ERR_ATOMIC_READ 0x00400000 /**< Atomic read error */ -+#define LBC_ERR_CHIP_SELECT 0x00080000 /**< Unrecognized chip select */ -+ -+#define LBC_ERR_ALL (LBC_ERR_BUS_MONITOR | LBC_ERR_PARITY_ECC | \ -+ LBC_ERR_WRITE_PROTECT | LBC_ERR_ATOMIC_WRITE | \ -+ LBC_ERR_ATOMIC_READ | LBC_ERR_CHIP_SELECT) -+ /**< All possible errors */ -+/* @} */ -+/** @} */ /* end of lbc_exception_grp group */ -+ -+#define LBC_INCORRECT_ERROR_REPORT_ERRATA -+ -+#define LBC_NUM_OF_BANKS 8 -+#define LBC_MAX_CS_SIZE 0x0000000100000000LL -+#define LBC_ATOMIC_OPERATION_SUPPORT -+#define LBC_PARITY_SUPPORT -+#define LBC_ADDRESS_HOLD_TIME_CTRL -+#define LBC_HIGH_CLK_DIVIDERS -+#define LBC_FCM_AVAILABLE -+ -+/***************************************************************************** -+ GPIO INTEGRATION-SPECIFIC DEFINITIONS -+******************************************************************************/ -+#define GPIO_NUM_OF_PORTS 1 /**< Number of ports in GPIO module; -+ Each port contains up to 32 i/O pins. */ -+ -+#define GPIO_VALID_PIN_MASKS \ -+ { /* Port A */ 0xFFFFFFFF } -+ -+#define GPIO_VALID_INTR_MASKS \ -+ { /* Port A */ 0xFFFFFFFF } -+ -+#endif /* __PART_INTEGRATION_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/math_ext.h -@@ -0,0 +1,99 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#ifndef __MATH_EXT_H -+#define __MATH_EXT_H -+ -+ -+#if defined(NCSW_LINUX) && defined(__KERNEL__) -+#include -+ -+#elif defined(__MWERKS__) -+#define LOW(x) ( sizeof(x)==8 ? *(1+(int32_t*)&x) : (*(int32_t*)&x)) -+#define HIGH(x) (*(int32_t*)&x) -+#define ULOW(x) ( sizeof(x)==8 ? *(1+(uint32_t*)&x) : (*(uint32_t*)&x)) -+#define UHIGH(x) (*(uint32_t*)&x) -+ -+static const double big = 1.0e300; -+ -+/* Macro for checking if a number is a power of 2 */ -+static __inline__ double ceil(double x) -+{ -+ int32_t i0,i1,j0; /*- cc 020130 -*/ -+ uint32_t i,j; /*- cc 020130 -*/ -+ i0 = HIGH(x); -+ i1 = LOW(x); -+ j0 = ((i0>>20)&0x7ff)-0x3ff; -+ if(j0<20) { -+ if(j0<0) { /* raise inexact if x != 0 */ -+ if(big+x>0.0) {/* return 0*sign(x) if |x|<1 */ -+ if(i0<0) {i0=0x80000000;i1=0;} -+ else if((i0|i1)!=0) { i0=0x3ff00000;i1=0;} -+ } -+ } else { -+ i = (uint32_t)(0x000fffff)>>j0; -+ if(((i0&i)|i1)==0) return x; /* x is integral */ -+ if(big+x>0.0) { /* raise inexact flag */ -+ if(i0>0) i0 += (0x00100000)>>j0; -+ i0 &= (~i); i1=0; -+ } -+ } -+ } else if (j0>51) { -+ if(j0==0x400) return x+x; /* inf or NaN */ -+ else return x; /* x is integral */ -+ } else { -+ i = ((uint32_t)(0xffffffff))>>(j0-20); /*- cc 020130 -*/ -+ if((i1&i)==0) return x; /* x is integral */ -+ if(big+x>0.0) { /* raise inexact flag */ -+ if(i0>0) { -+ if(j0==20) i0+=1; -+ else { -+ j = (uint32_t)(i1 + (1<<(52-j0))); -+ if(j -+#endif /* defined(NCSW_LINUX) && defined(__KERNEL__) */ -+ -+ -+#endif /* __MATH_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/ncsw_ext.h -@@ -0,0 +1,435 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File ncsw_ext.h -+ -+ @Description General NetCommSw Standard Definitions -+*//***************************************************************************/ -+ -+#ifndef __NCSW_EXT_H -+#define __NCSW_EXT_H -+ -+ -+#include "memcpy_ext.h" -+ -+#define WRITE_BLOCK IOMemSet32 /* include memcpy_ext.h */ -+#define COPY_BLOCK Mem2IOCpy32 /* include memcpy_ext.h */ -+ -+#define PTR_TO_UINT(_ptr) ((uintptr_t)(_ptr)) -+#define UINT_TO_PTR(_val) ((void*)(uintptr_t)(_val)) -+ -+#define PTR_MOVE(_ptr, _offset) (void*)((uint8_t*)(_ptr) + (_offset)) -+ -+ -+#define WRITE_UINT8_UINT24(arg, data08, data24) \ -+ WRITE_UINT32(arg,((uint32_t)(data08)<<24)|((uint32_t)(data24)&0x00FFFFFF)) -+#define WRITE_UINT24_UINT8(arg, data24, data08) \ -+ WRITE_UINT32(arg,((uint32_t)(data24)<< 8)|((uint32_t)(data08)&0x000000FF)) -+ -+/* Little-Endian access macros */ -+ -+#define WRITE_UINT16_LE(arg, data) \ -+ WRITE_UINT16((arg), SwapUint16(data)) -+ -+#define WRITE_UINT32_LE(arg, data) \ -+ WRITE_UINT32((arg), SwapUint32(data)) -+ -+#define WRITE_UINT64_LE(arg, data) \ -+ WRITE_UINT64((arg), SwapUint64(data)) -+ -+#define GET_UINT16_LE(arg) \ -+ SwapUint16(GET_UINT16(arg)) -+ -+#define GET_UINT32_LE(arg) \ -+ SwapUint32(GET_UINT32(arg)) -+ -+#define GET_UINT64_LE(arg) \ -+ SwapUint64(GET_UINT64(arg)) -+ -+/* Write and Read again macros */ -+#define WRITE_UINT_SYNC(size, arg, data) \ -+ do { \ -+ WRITE_UINT##size((arg), (data)); \ -+ CORE_MemoryBarrier(); \ -+ } while (0) -+ -+#define WRITE_UINT8_SYNC(arg, data) WRITE_UINT_SYNC(8, (arg), (data)) -+ -+#define WRITE_UINT16_SYNC(arg, data) WRITE_UINT_SYNC(16, (arg), (data)) -+#define WRITE_UINT32_SYNC(arg, data) WRITE_UINT_SYNC(32, (arg), (data)) -+ -+#define MAKE_UINT64(high32, low32) (((uint64_t)high32 << 32) | (low32)) -+ -+ -+/*----------------------*/ -+/* Miscellaneous macros */ -+/*----------------------*/ -+ -+#define UNUSED(_x) ((void)(_x)) -+ -+#define KILOBYTE 0x400UL /* 1024 */ -+#define MEGABYTE (KILOBYTE * KILOBYTE) /* 1024*1024 */ -+#define GIGABYTE ((uint64_t)(KILOBYTE * MEGABYTE)) /* 1024*1024*1024 */ -+#define TERABYTE ((uint64_t)(KILOBYTE * GIGABYTE)) /* 1024*1024*1024*1024 */ -+ -+#ifndef NO_IRQ -+#define NO_IRQ (0) -+#endif -+#define NCSW_MASTER_ID (0) -+ -+/* Macro for checking if a number is a power of 2 */ -+#define POWER_OF_2(n) (!((n) & ((n)-1))) -+ -+/* Macro for calculating log of base 2 */ -+#define LOG2(num, log2Num) \ -+ do \ -+ { \ -+ uint64_t tmp = (num); \ -+ log2Num = 0; \ -+ while (tmp > 1) \ -+ { \ -+ log2Num++; \ -+ tmp >>= 1; \ -+ } \ -+ } while (0) -+ -+#define NEXT_POWER_OF_2(_num, _nextPow) \ -+do \ -+{ \ -+ if (POWER_OF_2(_num)) \ -+ _nextPow = (_num); \ -+ else \ -+ { \ -+ uint64_t tmp = (_num); \ -+ _nextPow = 1; \ -+ while (tmp) \ -+ { \ -+ _nextPow <<= 1; \ -+ tmp >>= 1; \ -+ } \ -+ } \ -+} while (0) -+ -+/* Ceiling division - not the fastest way, but safer in terms of overflow */ -+#define DIV_CEIL(x,y) (((x)/(y)) + ((((((x)/(y)))*(y)) == (x)) ? 0 : 1)) -+ -+/* Round up a number to be a multiple of a second number */ -+#define ROUND_UP(x,y) ((((x) + (y) - 1) / (y)) * (y)) -+ -+/* Timing macro for converting usec units to number of ticks. */ -+/* (number of usec * clock_Hz) / 1,000,000) - since */ -+/* clk is in MHz units, no division needed. */ -+#define USEC_TO_CLK(usec,clk) ((usec) * (clk)) -+#define CYCLES_TO_USEC(cycles,clk) ((cycles) / (clk)) -+ -+/* Timing macros for converting between nsec units and number of clocks. */ -+#define NSEC_TO_CLK(nsec,clk) DIV_CEIL(((nsec) * (clk)), 1000) -+#define CYCLES_TO_NSEC(cycles,clk) (((cycles) * 1000) / (clk)) -+ -+/* Timing macros for converting between psec units and number of clocks. */ -+#define PSEC_TO_CLK(psec,clk) DIV_CEIL(((psec) * (clk)), 1000000) -+#define CYCLES_TO_PSEC(cycles,clk) (((cycles) * 1000000) / (clk)) -+ -+/* Min, Max macros */ -+#define MIN(a,b) ((a) < (b) ? (a) : (b)) -+#define MAX(a,b) ((a) > (b) ? (a) : (b)) -+#define IN_RANGE(min,val,max) ((min)<=(val) && (val)<=(max)) -+ -+#define ABS(a) ((a<0)?(a*-1):a) -+ -+#if !(defined(ARRAY_SIZE)) -+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) -+#endif /* !defined(ARRAY_SIZE) */ -+ -+ -+/* possible alignments */ -+#define HALF_WORD_ALIGNMENT 2 -+#define WORD_ALIGNMENT 4 -+#define DOUBLE_WORD_ALIGNMENT 8 -+#define BURST_ALIGNMENT 32 -+ -+#define HALF_WORD_ALIGNED 0x00000001 -+#define WORD_ALIGNED 0x00000003 -+#define DOUBLE_WORD_ALIGNED 0x00000007 -+#define BURST_ALIGNED 0x0000001f -+#ifndef IS_ALIGNED -+#define IS_ALIGNED(n,align) (!((uint32_t)(n) & (align - 1))) -+#endif /* IS_ALIGNED */ -+ -+ -+#define LAST_BUF 1 -+#define FIRST_BUF 2 -+#define SINGLE_BUF (LAST_BUF | FIRST_BUF) -+#define MIDDLE_BUF 4 -+ -+#define ARRAY_END -1 -+ -+#define ILLEGAL_BASE (~0) -+ -+#define BUF_POSITION(first, last) state[(!!(last))<<1 | !!(first)] -+#define DECLARE_POSITION static uint8_t state[4] = { (uint8_t)MIDDLE_BUF, (uint8_t)FIRST_BUF, (uint8_t)LAST_BUF, (uint8_t)SINGLE_BUF }; -+ -+ -+/**************************************************************************//** -+ @Description Timers operation mode -+*//***************************************************************************/ -+typedef enum e_TimerMode -+{ -+ e_TIMER_MODE_INVALID = 0, -+ e_TIMER_MODE_FREE_RUN, /**< Free run - counter continues to increase -+ after reaching the reference value. */ -+ e_TIMER_MODE_PERIODIC, /**< Periodic - counter restarts counting from 0 -+ after reaching the reference value. */ -+ e_TIMER_MODE_SINGLE /**< Single (one-shot) - counter stops counting -+ after reaching the reference value. */ -+} e_TimerMode; -+ -+ -+/**************************************************************************//** -+ @Description Enumeration (bit flags) of communication modes (Transmit, -+ receive or both). -+*//***************************************************************************/ -+typedef enum e_CommMode -+{ -+ e_COMM_MODE_NONE = 0, /**< No transmit/receive communication */ -+ e_COMM_MODE_RX = 1, /**< Only receive communication */ -+ e_COMM_MODE_TX = 2, /**< Only transmit communication */ -+ e_COMM_MODE_RX_AND_TX = 3 /**< Both transmit and receive communication */ -+} e_CommMode; -+ -+/**************************************************************************//** -+ @Description General Diagnostic Mode -+*//***************************************************************************/ -+typedef enum e_DiagMode -+{ -+ e_DIAG_MODE_NONE = 0, /**< Normal operation; no diagnostic mode */ -+ e_DIAG_MODE_CTRL_LOOPBACK, /**< Loopback in the controller */ -+ e_DIAG_MODE_CHIP_LOOPBACK, /**< Loopback in the chip but not in the -+ controller; e.g. IO-pins, SerDes, etc. */ -+ e_DIAG_MODE_PHY_LOOPBACK, /**< Loopback in the external PHY */ -+ e_DIAG_MODE_EXT_LOOPBACK, /**< Loopback in the external line (beyond the PHY) */ -+ e_DIAG_MODE_CTRL_ECHO, /**< Echo incoming data by the controller */ -+ e_DIAG_MODE_PHY_ECHO /**< Echo incoming data by the PHY */ -+} e_DiagMode; -+ -+/**************************************************************************//** -+ @Description Possible RxStore callback responses. -+*//***************************************************************************/ -+typedef enum e_RxStoreResponse -+{ -+ e_RX_STORE_RESPONSE_PAUSE /**< Pause invoking callback with received data; -+ in polling mode, start again invoking callback -+ only next time user invokes the receive routine; -+ in interrupt mode, start again invoking callback -+ only next time a receive event triggers an interrupt; -+ in all cases, received data that are pending are not -+ lost, rather, their processing is temporarily deferred; -+ in all cases, received data are processed in the order -+ in which they were received. */ -+ , e_RX_STORE_RESPONSE_CONTINUE /**< Continue invoking callback with received data. */ -+} e_RxStoreResponse; -+ -+ -+/**************************************************************************//** -+ @Description General Handle -+*//***************************************************************************/ -+typedef void * t_Handle; /**< handle, used as object's descriptor */ -+ -+/**************************************************************************//** -+ @Description MUTEX type -+*//***************************************************************************/ -+typedef uint32_t t_Mutex; -+ -+/**************************************************************************//** -+ @Description Error Code. -+ -+ The high word of the error code is the code of the software -+ module (driver). The low word is the error type (e_ErrorType). -+ To get the values from the error code, use GET_ERROR_TYPE() -+ and GET_ERROR_MODULE(). -+*//***************************************************************************/ -+typedef uint32_t t_Error; -+ -+/**************************************************************************//** -+ @Description General prototype of interrupt service routine (ISR). -+ -+ @Param[in] handle - Optional handle of the module handling the interrupt. -+ -+ @Return None -+ *//***************************************************************************/ -+typedef void (t_Isr)(t_Handle handle); -+ -+/**************************************************************************//** -+ @Anchor mem_attr -+ -+ @Collection Memory Attributes -+ -+ Various attributes of memory partitions. These values may be -+ or'ed together to create a mask of all memory attributes. -+ @{ -+*//***************************************************************************/ -+#define MEMORY_ATTR_CACHEABLE 0x00000001 -+ /**< Memory is cacheable */ -+#define MEMORY_ATTR_QE_2ND_BUS_ACCESS 0x00000002 -+ /**< Memory can be accessed by QUICC Engine -+ through its secondary bus interface */ -+ -+/* @} */ -+ -+ -+/**************************************************************************//** -+ @Function t_GetBufFunction -+ -+ @Description User callback function called by driver to get data buffer. -+ -+ User provides this function. Driver invokes it. -+ -+ @Param[in] h_BufferPool - A handle to buffer pool manager -+ @Param[out] p_BufContextHandle - Returns the user's private context that -+ should be associated with the buffer -+ -+ @Return Pointer to data buffer, NULL if error -+ *//***************************************************************************/ -+typedef uint8_t * (t_GetBufFunction)(t_Handle h_BufferPool, -+ t_Handle *p_BufContextHandle); -+ -+/**************************************************************************//** -+ @Function t_PutBufFunction -+ -+ @Description User callback function called by driver to return data buffer. -+ -+ User provides this function. Driver invokes it. -+ -+ @Param[in] h_BufferPool - A handle to buffer pool manager -+ @Param[in] p_Buffer - A pointer to buffer to return -+ @Param[in] h_BufContext - The user's private context associated with -+ the returned buffer -+ -+ @Return E_OK on success; Error code otherwise -+ *//***************************************************************************/ -+typedef t_Error (t_PutBufFunction)(t_Handle h_BufferPool, -+ uint8_t *p_Buffer, -+ t_Handle h_BufContext); -+ -+/**************************************************************************//** -+ @Function t_PhysToVirt -+ -+ @Description Translates a physical address to the matching virtual address. -+ -+ @Param[in] addr - The physical address to translate. -+ -+ @Return Virtual address. -+*//***************************************************************************/ -+typedef void * t_PhysToVirt(physAddress_t addr); -+ -+/**************************************************************************//** -+ @Function t_VirtToPhys -+ -+ @Description Translates a virtual address to the matching physical address. -+ -+ @Param[in] addr - The virtual address to translate. -+ -+ @Return Physical address. -+*//***************************************************************************/ -+typedef physAddress_t t_VirtToPhys(void *addr); -+ -+/**************************************************************************//** -+ @Description Buffer Pool Information Structure. -+*//***************************************************************************/ -+typedef struct t_BufferPoolInfo -+{ -+ t_Handle h_BufferPool; /**< A handle to the buffer pool manager */ -+ t_GetBufFunction *f_GetBuf; /**< User callback to get a free buffer */ -+ t_PutBufFunction *f_PutBuf; /**< User callback to return a buffer */ -+ uint16_t bufferSize; /**< Buffer size (in bytes) */ -+ -+ t_PhysToVirt *f_PhysToVirt; /**< User callback to translate pool buffers -+ physical addresses to virtual addresses */ -+ t_VirtToPhys *f_VirtToPhys; /**< User callback to translate pool buffers -+ virtual addresses to physical addresses */ -+} t_BufferPoolInfo; -+ -+ -+/**************************************************************************//** -+ @Description User callback function called by driver when transmit completed. -+ -+ User provides this function. Driver invokes it. -+ -+ @Param[in] h_App - Application's handle, as was provided to the -+ driver by the user -+ @Param[in] queueId - Transmit queue ID -+ @Param[in] p_Data - Pointer to the data buffer -+ @Param[in] h_BufContext - The user's private context associated with -+ the given data buffer -+ @Param[in] status - Transmit status and errors -+ @Param[in] flags - Driver-dependent information -+ *//***************************************************************************/ -+typedef void (t_TxConfFunction)(t_Handle h_App, -+ uint32_t queueId, -+ uint8_t *p_Data, -+ t_Handle h_BufContext, -+ uint16_t status, -+ uint32_t flags); -+ -+/**************************************************************************//** -+ @Description User callback function called by driver with receive data. -+ -+ User provides this function. Driver invokes it. -+ -+ @Param[in] h_App - Application's handle, as was provided to the -+ driver by the user -+ @Param[in] queueId - Receive queue ID -+ @Param[in] p_Data - Pointer to the buffer with received data -+ @Param[in] h_BufContext - The user's private context associated with -+ the given data buffer -+ @Param[in] length - Length of received data -+ @Param[in] status - Receive status and errors -+ @Param[in] position - Position of buffer in frame -+ @Param[in] flags - Driver-dependent information -+ -+ @Retval e_RX_STORE_RESPONSE_CONTINUE - order the driver to continue Rx -+ operation for all ready data. -+ @Retval e_RX_STORE_RESPONSE_PAUSE - order the driver to stop Rx operation. -+ *//***************************************************************************/ -+typedef e_RxStoreResponse (t_RxStoreFunction)(t_Handle h_App, -+ uint32_t queueId, -+ uint8_t *p_Data, -+ t_Handle h_BufContext, -+ uint32_t length, -+ uint16_t status, -+ uint8_t position, -+ uint32_t flags); -+ -+ -+#endif /* __NCSW_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/net_ext.h -@@ -0,0 +1,430 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File net_ext.h -+ -+ @Description This file contains common and general netcomm headers definitions. -+*//***************************************************************************/ -+#ifndef __NET_EXT_H -+#define __NET_EXT_H -+ -+#include "std_ext.h" -+ -+ -+typedef uint8_t headerFieldPpp_t; -+ -+#define NET_HEADER_FIELD_PPP_PID (1) -+#define NET_HEADER_FIELD_PPP_COMPRESSED (NET_HEADER_FIELD_PPP_PID << 1) -+#define NET_HEADER_FIELD_PPP_ALL_FIELDS ((NET_HEADER_FIELD_PPP_PID << 2) - 1) -+ -+ -+typedef uint8_t headerFieldPppoe_t; -+ -+#define NET_HEADER_FIELD_PPPoE_VER (1) -+#define NET_HEADER_FIELD_PPPoE_TYPE (NET_HEADER_FIELD_PPPoE_VER << 1) -+#define NET_HEADER_FIELD_PPPoE_CODE (NET_HEADER_FIELD_PPPoE_VER << 2) -+#define NET_HEADER_FIELD_PPPoE_SID (NET_HEADER_FIELD_PPPoE_VER << 3) -+#define NET_HEADER_FIELD_PPPoE_LEN (NET_HEADER_FIELD_PPPoE_VER << 4) -+#define NET_HEADER_FIELD_PPPoE_SESSION (NET_HEADER_FIELD_PPPoE_VER << 5) -+#define NET_HEADER_FIELD_PPPoE_PID (NET_HEADER_FIELD_PPPoE_VER << 6) -+#define NET_HEADER_FIELD_PPPoE_ALL_FIELDS ((NET_HEADER_FIELD_PPPoE_VER << 7) - 1) -+ -+#define NET_HEADER_FIELD_PPPMUX_PID (1) -+#define NET_HEADER_FIELD_PPPMUX_CKSUM (NET_HEADER_FIELD_PPPMUX_PID << 1) -+#define NET_HEADER_FIELD_PPPMUX_COMPRESSED (NET_HEADER_FIELD_PPPMUX_PID << 2) -+#define NET_HEADER_FIELD_PPPMUX_ALL_FIELDS ((NET_HEADER_FIELD_PPPMUX_PID << 3) - 1) -+ -+#define NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF (1) -+#define NET_HEADER_FIELD_PPPMUX_SUBFRAME_LXT (NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 1) -+#define NET_HEADER_FIELD_PPPMUX_SUBFRAME_LEN (NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 2) -+#define NET_HEADER_FIELD_PPPMUX_SUBFRAME_PID (NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 3) -+#define NET_HEADER_FIELD_PPPMUX_SUBFRAME_USE_PID (NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 4) -+#define NET_HEADER_FIELD_PPPMUX_SUBFRAME_ALL_FIELDS ((NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 5) - 1) -+ -+ -+typedef uint8_t headerFieldEth_t; -+ -+#define NET_HEADER_FIELD_ETH_DA (1) -+#define NET_HEADER_FIELD_ETH_SA (NET_HEADER_FIELD_ETH_DA << 1) -+#define NET_HEADER_FIELD_ETH_LENGTH (NET_HEADER_FIELD_ETH_DA << 2) -+#define NET_HEADER_FIELD_ETH_TYPE (NET_HEADER_FIELD_ETH_DA << 3) -+#define NET_HEADER_FIELD_ETH_FINAL_CKSUM (NET_HEADER_FIELD_ETH_DA << 4) -+#define NET_HEADER_FIELD_ETH_PADDING (NET_HEADER_FIELD_ETH_DA << 5) -+#define NET_HEADER_FIELD_ETH_ALL_FIELDS ((NET_HEADER_FIELD_ETH_DA << 6) - 1) -+ -+#define NET_HEADER_FIELD_ETH_ADDR_SIZE 6 -+ -+typedef uint16_t headerFieldIp_t; -+ -+#define NET_HEADER_FIELD_IP_VER (1) -+#define NET_HEADER_FIELD_IP_DSCP (NET_HEADER_FIELD_IP_VER << 2) -+#define NET_HEADER_FIELD_IP_ECN (NET_HEADER_FIELD_IP_VER << 3) -+#define NET_HEADER_FIELD_IP_PROTO (NET_HEADER_FIELD_IP_VER << 4) -+ -+#define NET_HEADER_FIELD_IP_PROTO_SIZE 1 -+ -+typedef uint16_t headerFieldIpv4_t; -+ -+#define NET_HEADER_FIELD_IPv4_VER (1) -+#define NET_HEADER_FIELD_IPv4_HDR_LEN (NET_HEADER_FIELD_IPv4_VER << 1) -+#define NET_HEADER_FIELD_IPv4_TOS (NET_HEADER_FIELD_IPv4_VER << 2) -+#define NET_HEADER_FIELD_IPv4_TOTAL_LEN (NET_HEADER_FIELD_IPv4_VER << 3) -+#define NET_HEADER_FIELD_IPv4_ID (NET_HEADER_FIELD_IPv4_VER << 4) -+#define NET_HEADER_FIELD_IPv4_FLAG_D (NET_HEADER_FIELD_IPv4_VER << 5) -+#define NET_HEADER_FIELD_IPv4_FLAG_M (NET_HEADER_FIELD_IPv4_VER << 6) -+#define NET_HEADER_FIELD_IPv4_OFFSET (NET_HEADER_FIELD_IPv4_VER << 7) -+#define NET_HEADER_FIELD_IPv4_TTL (NET_HEADER_FIELD_IPv4_VER << 8) -+#define NET_HEADER_FIELD_IPv4_PROTO (NET_HEADER_FIELD_IPv4_VER << 9) -+#define NET_HEADER_FIELD_IPv4_CKSUM (NET_HEADER_FIELD_IPv4_VER << 10) -+#define NET_HEADER_FIELD_IPv4_SRC_IP (NET_HEADER_FIELD_IPv4_VER << 11) -+#define NET_HEADER_FIELD_IPv4_DST_IP (NET_HEADER_FIELD_IPv4_VER << 12) -+#define NET_HEADER_FIELD_IPv4_OPTS (NET_HEADER_FIELD_IPv4_VER << 13) -+#define NET_HEADER_FIELD_IPv4_OPTS_COUNT (NET_HEADER_FIELD_IPv4_VER << 14) -+#define NET_HEADER_FIELD_IPv4_ALL_FIELDS ((NET_HEADER_FIELD_IPv4_VER << 15) - 1) -+ -+#define NET_HEADER_FIELD_IPv4_ADDR_SIZE 4 -+#define NET_HEADER_FIELD_IPv4_PROTO_SIZE 1 -+ -+ -+typedef uint8_t headerFieldIpv6_t; -+ -+#define NET_HEADER_FIELD_IPv6_VER (1) -+#define NET_HEADER_FIELD_IPv6_TC (NET_HEADER_FIELD_IPv6_VER << 1) -+#define NET_HEADER_FIELD_IPv6_SRC_IP (NET_HEADER_FIELD_IPv6_VER << 2) -+#define NET_HEADER_FIELD_IPv6_DST_IP (NET_HEADER_FIELD_IPv6_VER << 3) -+#define NET_HEADER_FIELD_IPv6_NEXT_HDR (NET_HEADER_FIELD_IPv6_VER << 4) -+#define NET_HEADER_FIELD_IPv6_FL (NET_HEADER_FIELD_IPv6_VER << 5) -+#define NET_HEADER_FIELD_IPv6_HOP_LIMIT (NET_HEADER_FIELD_IPv6_VER << 6) -+#define NET_HEADER_FIELD_IPv6_ALL_FIELDS ((NET_HEADER_FIELD_IPv6_VER << 7) - 1) -+ -+#define NET_HEADER_FIELD_IPv6_ADDR_SIZE 16 -+#define NET_HEADER_FIELD_IPv6_NEXT_HDR_SIZE 1 -+ -+#define NET_HEADER_FIELD_ICMP_TYPE (1) -+#define NET_HEADER_FIELD_ICMP_CODE (NET_HEADER_FIELD_ICMP_TYPE << 1) -+#define NET_HEADER_FIELD_ICMP_CKSUM (NET_HEADER_FIELD_ICMP_TYPE << 2) -+#define NET_HEADER_FIELD_ICMP_ID (NET_HEADER_FIELD_ICMP_TYPE << 3) -+#define NET_HEADER_FIELD_ICMP_SQ_NUM (NET_HEADER_FIELD_ICMP_TYPE << 4) -+#define NET_HEADER_FIELD_ICMP_ALL_FIELDS ((NET_HEADER_FIELD_ICMP_TYPE << 5) - 1) -+ -+#define NET_HEADER_FIELD_ICMP_CODE_SIZE 1 -+#define NET_HEADER_FIELD_ICMP_TYPE_SIZE 1 -+ -+#define NET_HEADER_FIELD_IGMP_VERSION (1) -+#define NET_HEADER_FIELD_IGMP_TYPE (NET_HEADER_FIELD_IGMP_VERSION << 1) -+#define NET_HEADER_FIELD_IGMP_CKSUM (NET_HEADER_FIELD_IGMP_VERSION << 2) -+#define NET_HEADER_FIELD_IGMP_DATA (NET_HEADER_FIELD_IGMP_VERSION << 3) -+#define NET_HEADER_FIELD_IGMP_ALL_FIELDS ((NET_HEADER_FIELD_IGMP_VERSION << 4) - 1) -+ -+ -+typedef uint16_t headerFieldTcp_t; -+ -+#define NET_HEADER_FIELD_TCP_PORT_SRC (1) -+#define NET_HEADER_FIELD_TCP_PORT_DST (NET_HEADER_FIELD_TCP_PORT_SRC << 1) -+#define NET_HEADER_FIELD_TCP_SEQ (NET_HEADER_FIELD_TCP_PORT_SRC << 2) -+#define NET_HEADER_FIELD_TCP_ACK (NET_HEADER_FIELD_TCP_PORT_SRC << 3) -+#define NET_HEADER_FIELD_TCP_OFFSET (NET_HEADER_FIELD_TCP_PORT_SRC << 4) -+#define NET_HEADER_FIELD_TCP_FLAGS (NET_HEADER_FIELD_TCP_PORT_SRC << 5) -+#define NET_HEADER_FIELD_TCP_WINDOW (NET_HEADER_FIELD_TCP_PORT_SRC << 6) -+#define NET_HEADER_FIELD_TCP_CKSUM (NET_HEADER_FIELD_TCP_PORT_SRC << 7) -+#define NET_HEADER_FIELD_TCP_URGPTR (NET_HEADER_FIELD_TCP_PORT_SRC << 8) -+#define NET_HEADER_FIELD_TCP_OPTS (NET_HEADER_FIELD_TCP_PORT_SRC << 9) -+#define NET_HEADER_FIELD_TCP_OPTS_COUNT (NET_HEADER_FIELD_TCP_PORT_SRC << 10) -+#define NET_HEADER_FIELD_TCP_ALL_FIELDS ((NET_HEADER_FIELD_TCP_PORT_SRC << 11) - 1) -+ -+#define NET_HEADER_FIELD_TCP_PORT_SIZE 2 -+ -+ -+typedef uint8_t headerFieldSctp_t; -+ -+#define NET_HEADER_FIELD_SCTP_PORT_SRC (1) -+#define NET_HEADER_FIELD_SCTP_PORT_DST (NET_HEADER_FIELD_SCTP_PORT_SRC << 1) -+#define NET_HEADER_FIELD_SCTP_VER_TAG (NET_HEADER_FIELD_SCTP_PORT_SRC << 2) -+#define NET_HEADER_FIELD_SCTP_CKSUM (NET_HEADER_FIELD_SCTP_PORT_SRC << 3) -+#define NET_HEADER_FIELD_SCTP_ALL_FIELDS ((NET_HEADER_FIELD_SCTP_PORT_SRC << 4) - 1) -+ -+#define NET_HEADER_FIELD_SCTP_PORT_SIZE 2 -+ -+typedef uint8_t headerFieldDccp_t; -+ -+#define NET_HEADER_FIELD_DCCP_PORT_SRC (1) -+#define NET_HEADER_FIELD_DCCP_PORT_DST (NET_HEADER_FIELD_DCCP_PORT_SRC << 1) -+#define NET_HEADER_FIELD_DCCP_ALL_FIELDS ((NET_HEADER_FIELD_DCCP_PORT_SRC << 2) - 1) -+ -+#define NET_HEADER_FIELD_DCCP_PORT_SIZE 2 -+ -+ -+typedef uint8_t headerFieldUdp_t; -+ -+#define NET_HEADER_FIELD_UDP_PORT_SRC (1) -+#define NET_HEADER_FIELD_UDP_PORT_DST (NET_HEADER_FIELD_UDP_PORT_SRC << 1) -+#define NET_HEADER_FIELD_UDP_LEN (NET_HEADER_FIELD_UDP_PORT_SRC << 2) -+#define NET_HEADER_FIELD_UDP_CKSUM (NET_HEADER_FIELD_UDP_PORT_SRC << 3) -+#define NET_HEADER_FIELD_UDP_ALL_FIELDS ((NET_HEADER_FIELD_UDP_PORT_SRC << 4) - 1) -+ -+#define NET_HEADER_FIELD_UDP_PORT_SIZE 2 -+ -+typedef uint8_t headerFieldUdpLite_t; -+ -+#define NET_HEADER_FIELD_UDP_LITE_PORT_SRC (1) -+#define NET_HEADER_FIELD_UDP_LITE_PORT_DST (NET_HEADER_FIELD_UDP_LITE_PORT_SRC << 1) -+#define NET_HEADER_FIELD_UDP_LITE_ALL_FIELDS ((NET_HEADER_FIELD_UDP_LITE_PORT_SRC << 2) - 1) -+ -+#define NET_HEADER_FIELD_UDP_LITE_PORT_SIZE 2 -+ -+typedef uint8_t headerFieldUdpEncapEsp_t; -+ -+#define NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC (1) -+#define NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_DST (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 1) -+#define NET_HEADER_FIELD_UDP_ENCAP_ESP_LEN (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 2) -+#define NET_HEADER_FIELD_UDP_ENCAP_ESP_CKSUM (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 3) -+#define NET_HEADER_FIELD_UDP_ENCAP_ESP_SPI (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 4) -+#define NET_HEADER_FIELD_UDP_ENCAP_ESP_SEQUENCE_NUM (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 5) -+#define NET_HEADER_FIELD_UDP_ENCAP_ESP_ALL_FIELDS ((NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 6) - 1) -+ -+#define NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SIZE 2 -+#define NET_HEADER_FIELD_UDP_ENCAP_ESP_SPI_SIZE 4 -+ -+#define NET_HEADER_FIELD_IPHC_CID (1) -+#define NET_HEADER_FIELD_IPHC_CID_TYPE (NET_HEADER_FIELD_IPHC_CID << 1) -+#define NET_HEADER_FIELD_IPHC_HCINDEX (NET_HEADER_FIELD_IPHC_CID << 2) -+#define NET_HEADER_FIELD_IPHC_GEN (NET_HEADER_FIELD_IPHC_CID << 3) -+#define NET_HEADER_FIELD_IPHC_D_BIT (NET_HEADER_FIELD_IPHC_CID << 4) -+#define NET_HEADER_FIELD_IPHC_ALL_FIELDS ((NET_HEADER_FIELD_IPHC_CID << 5) - 1) -+ -+#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE (1) -+#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_FLAGS (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 1) -+#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_LENGTH (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 2) -+#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_TSN (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 3) -+#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_STREAM_ID (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 4) -+#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_STREAM_SQN (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 5) -+#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_PAYLOAD_PID (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 6) -+#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_UNORDERED (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 7) -+#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_BEGGINING (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 8) -+#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_END (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 9) -+#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_ALL_FIELDS ((NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 10) - 1) -+ -+#define NET_HEADER_FIELD_L2TPv2_TYPE_BIT (1) -+#define NET_HEADER_FIELD_L2TPv2_LENGTH_BIT (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 1) -+#define NET_HEADER_FIELD_L2TPv2_SEQUENCE_BIT (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 2) -+#define NET_HEADER_FIELD_L2TPv2_OFFSET_BIT (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 3) -+#define NET_HEADER_FIELD_L2TPv2_PRIORITY_BIT (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 4) -+#define NET_HEADER_FIELD_L2TPv2_VERSION (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 5) -+#define NET_HEADER_FIELD_L2TPv2_LEN (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 6) -+#define NET_HEADER_FIELD_L2TPv2_TUNNEL_ID (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 7) -+#define NET_HEADER_FIELD_L2TPv2_SESSION_ID (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 8) -+#define NET_HEADER_FIELD_L2TPv2_NS (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 9) -+#define NET_HEADER_FIELD_L2TPv2_NR (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 10) -+#define NET_HEADER_FIELD_L2TPv2_OFFSET_SIZE (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 11) -+#define NET_HEADER_FIELD_L2TPv2_FIRST_BYTE (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 12) -+#define NET_HEADER_FIELD_L2TPv2_ALL_FIELDS ((NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 13) - 1) -+ -+#define NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT (1) -+#define NET_HEADER_FIELD_L2TPv3_CTRL_LENGTH_BIT (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 1) -+#define NET_HEADER_FIELD_L2TPv3_CTRL_SEQUENCE_BIT (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 2) -+#define NET_HEADER_FIELD_L2TPv3_CTRL_VERSION (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 3) -+#define NET_HEADER_FIELD_L2TPv3_CTRL_LENGTH (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 4) -+#define NET_HEADER_FIELD_L2TPv3_CTRL_CONTROL (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 5) -+#define NET_HEADER_FIELD_L2TPv3_CTRL_SENT (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 6) -+#define NET_HEADER_FIELD_L2TPv3_CTRL_RECV (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 7) -+#define NET_HEADER_FIELD_L2TPv3_CTRL_FIRST_BYTE (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 8) -+#define NET_HEADER_FIELD_L2TPv3_CTRL_ALL_FIELDS ((NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 9) - 1) -+ -+#define NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT (1) -+#define NET_HEADER_FIELD_L2TPv3_SESS_VERSION (NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT << 1) -+#define NET_HEADER_FIELD_L2TPv3_SESS_ID (NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT << 2) -+#define NET_HEADER_FIELD_L2TPv3_SESS_COOKIE (NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT << 3) -+#define NET_HEADER_FIELD_L2TPv3_SESS_ALL_FIELDS ((NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT << 4) - 1) -+ -+ -+typedef uint8_t headerFieldVlan_t; -+ -+#define NET_HEADER_FIELD_VLAN_VPRI (1) -+#define NET_HEADER_FIELD_VLAN_CFI (NET_HEADER_FIELD_VLAN_VPRI << 1) -+#define NET_HEADER_FIELD_VLAN_VID (NET_HEADER_FIELD_VLAN_VPRI << 2) -+#define NET_HEADER_FIELD_VLAN_LENGTH (NET_HEADER_FIELD_VLAN_VPRI << 3) -+#define NET_HEADER_FIELD_VLAN_TYPE (NET_HEADER_FIELD_VLAN_VPRI << 4) -+#define NET_HEADER_FIELD_VLAN_ALL_FIELDS ((NET_HEADER_FIELD_VLAN_VPRI << 5) - 1) -+ -+#define NET_HEADER_FIELD_VLAN_TCI (NET_HEADER_FIELD_VLAN_VPRI | \ -+ NET_HEADER_FIELD_VLAN_CFI | \ -+ NET_HEADER_FIELD_VLAN_VID) -+ -+ -+typedef uint8_t headerFieldLlc_t; -+ -+#define NET_HEADER_FIELD_LLC_DSAP (1) -+#define NET_HEADER_FIELD_LLC_SSAP (NET_HEADER_FIELD_LLC_DSAP << 1) -+#define NET_HEADER_FIELD_LLC_CTRL (NET_HEADER_FIELD_LLC_DSAP << 2) -+#define NET_HEADER_FIELD_LLC_ALL_FIELDS ((NET_HEADER_FIELD_LLC_DSAP << 3) - 1) -+ -+#define NET_HEADER_FIELD_NLPID_NLPID (1) -+#define NET_HEADER_FIELD_NLPID_ALL_FIELDS ((NET_HEADER_FIELD_NLPID_NLPID << 1) - 1) -+ -+ -+typedef uint8_t headerFieldSnap_t; -+ -+#define NET_HEADER_FIELD_SNAP_OUI (1) -+#define NET_HEADER_FIELD_SNAP_PID (NET_HEADER_FIELD_SNAP_OUI << 1) -+#define NET_HEADER_FIELD_SNAP_ALL_FIELDS ((NET_HEADER_FIELD_SNAP_OUI << 2) - 1) -+ -+ -+typedef uint8_t headerFieldLlcSnap_t; -+ -+#define NET_HEADER_FIELD_LLC_SNAP_TYPE (1) -+#define NET_HEADER_FIELD_LLC_SNAP_ALL_FIELDS ((NET_HEADER_FIELD_LLC_SNAP_TYPE << 1) - 1) -+ -+#define NET_HEADER_FIELD_ARP_HTYPE (1) -+#define NET_HEADER_FIELD_ARP_PTYPE (NET_HEADER_FIELD_ARP_HTYPE << 1) -+#define NET_HEADER_FIELD_ARP_HLEN (NET_HEADER_FIELD_ARP_HTYPE << 2) -+#define NET_HEADER_FIELD_ARP_PLEN (NET_HEADER_FIELD_ARP_HTYPE << 3) -+#define NET_HEADER_FIELD_ARP_OPER (NET_HEADER_FIELD_ARP_HTYPE << 4) -+#define NET_HEADER_FIELD_ARP_SHA (NET_HEADER_FIELD_ARP_HTYPE << 5) -+#define NET_HEADER_FIELD_ARP_SPA (NET_HEADER_FIELD_ARP_HTYPE << 6) -+#define NET_HEADER_FIELD_ARP_THA (NET_HEADER_FIELD_ARP_HTYPE << 7) -+#define NET_HEADER_FIELD_ARP_TPA (NET_HEADER_FIELD_ARP_HTYPE << 8) -+#define NET_HEADER_FIELD_ARP_ALL_FIELDS ((NET_HEADER_FIELD_ARP_HTYPE << 9) - 1) -+ -+#define NET_HEADER_FIELD_RFC2684_LLC (1) -+#define NET_HEADER_FIELD_RFC2684_NLPID (NET_HEADER_FIELD_RFC2684_LLC << 1) -+#define NET_HEADER_FIELD_RFC2684_OUI (NET_HEADER_FIELD_RFC2684_LLC << 2) -+#define NET_HEADER_FIELD_RFC2684_PID (NET_HEADER_FIELD_RFC2684_LLC << 3) -+#define NET_HEADER_FIELD_RFC2684_VPN_OUI (NET_HEADER_FIELD_RFC2684_LLC << 4) -+#define NET_HEADER_FIELD_RFC2684_VPN_IDX (NET_HEADER_FIELD_RFC2684_LLC << 5) -+#define NET_HEADER_FIELD_RFC2684_ALL_FIELDS ((NET_HEADER_FIELD_RFC2684_LLC << 6) - 1) -+ -+#define NET_HEADER_FIELD_USER_DEFINED_SRCPORT (1) -+#define NET_HEADER_FIELD_USER_DEFINED_PCDID (NET_HEADER_FIELD_USER_DEFINED_SRCPORT << 1) -+#define NET_HEADER_FIELD_USER_DEFINED_ALL_FIELDS ((NET_HEADER_FIELD_USER_DEFINED_SRCPORT << 2) - 1) -+ -+#define NET_HEADER_FIELD_PAYLOAD_BUFFER (1) -+#define NET_HEADER_FIELD_PAYLOAD_SIZE (NET_HEADER_FIELD_PAYLOAD_BUFFER << 1) -+#define NET_HEADER_FIELD_MAX_FRM_SIZE (NET_HEADER_FIELD_PAYLOAD_BUFFER << 2) -+#define NET_HEADER_FIELD_MIN_FRM_SIZE (NET_HEADER_FIELD_PAYLOAD_BUFFER << 3) -+#define NET_HEADER_FIELD_PAYLOAD_TYPE (NET_HEADER_FIELD_PAYLOAD_BUFFER << 4) -+#define NET_HEADER_FIELD_FRAME_SIZE (NET_HEADER_FIELD_PAYLOAD_BUFFER << 5) -+#define NET_HEADER_FIELD_PAYLOAD_ALL_FIELDS ((NET_HEADER_FIELD_PAYLOAD_BUFFER << 6) - 1) -+ -+ -+typedef uint8_t headerFieldGre_t; -+ -+#define NET_HEADER_FIELD_GRE_TYPE (1) -+#define NET_HEADER_FIELD_GRE_ALL_FIELDS ((NET_HEADER_FIELD_GRE_TYPE << 1) - 1) -+ -+ -+typedef uint8_t headerFieldMinencap_t; -+ -+#define NET_HEADER_FIELD_MINENCAP_SRC_IP (1) -+#define NET_HEADER_FIELD_MINENCAP_DST_IP (NET_HEADER_FIELD_MINENCAP_SRC_IP << 1) -+#define NET_HEADER_FIELD_MINENCAP_TYPE (NET_HEADER_FIELD_MINENCAP_SRC_IP << 2) -+#define NET_HEADER_FIELD_MINENCAP_ALL_FIELDS ((NET_HEADER_FIELD_MINENCAP_SRC_IP << 3) - 1) -+ -+ -+typedef uint8_t headerFieldIpsecAh_t; -+ -+#define NET_HEADER_FIELD_IPSEC_AH_SPI (1) -+#define NET_HEADER_FIELD_IPSEC_AH_NH (NET_HEADER_FIELD_IPSEC_AH_SPI << 1) -+#define NET_HEADER_FIELD_IPSEC_AH_ALL_FIELDS ((NET_HEADER_FIELD_IPSEC_AH_SPI << 2) - 1) -+ -+ -+typedef uint8_t headerFieldIpsecEsp_t; -+ -+#define NET_HEADER_FIELD_IPSEC_ESP_SPI (1) -+#define NET_HEADER_FIELD_IPSEC_ESP_SEQUENCE_NUM (NET_HEADER_FIELD_IPSEC_ESP_SPI << 1) -+#define NET_HEADER_FIELD_IPSEC_ESP_ALL_FIELDS ((NET_HEADER_FIELD_IPSEC_ESP_SPI << 2) - 1) -+ -+#define NET_HEADER_FIELD_IPSEC_ESP_SPI_SIZE 4 -+ -+ -+typedef uint8_t headerFieldMpls_t; -+ -+#define NET_HEADER_FIELD_MPLS_LABEL_STACK (1) -+#define NET_HEADER_FIELD_MPLS_LABEL_STACK_ALL_FIELDS ((NET_HEADER_FIELD_MPLS_LABEL_STACK << 1) - 1) -+ -+ -+typedef uint8_t headerFieldMacsec_t; -+ -+#define NET_HEADER_FIELD_MACSEC_SECTAG (1) -+#define NET_HEADER_FIELD_MACSEC_ALL_FIELDS ((NET_HEADER_FIELD_MACSEC_SECTAG << 1) - 1) -+ -+ -+typedef enum { -+ HEADER_TYPE_NONE = 0, -+ HEADER_TYPE_PAYLOAD, -+ HEADER_TYPE_ETH, -+ HEADER_TYPE_VLAN, -+ HEADER_TYPE_IPv4, -+ HEADER_TYPE_IPv6, -+ HEADER_TYPE_IP, -+ HEADER_TYPE_TCP, -+ HEADER_TYPE_UDP, -+ HEADER_TYPE_UDP_LITE, -+ HEADER_TYPE_IPHC, -+ HEADER_TYPE_SCTP, -+ HEADER_TYPE_SCTP_CHUNK_DATA, -+ HEADER_TYPE_PPPoE, -+ HEADER_TYPE_PPP, -+ HEADER_TYPE_PPPMUX, -+ HEADER_TYPE_PPPMUX_SUBFRAME, -+ HEADER_TYPE_L2TPv2, -+ HEADER_TYPE_L2TPv3_CTRL, -+ HEADER_TYPE_L2TPv3_SESS, -+ HEADER_TYPE_LLC, -+ HEADER_TYPE_LLC_SNAP, -+ HEADER_TYPE_NLPID, -+ HEADER_TYPE_SNAP, -+ HEADER_TYPE_MPLS, -+ HEADER_TYPE_IPSEC_AH, -+ HEADER_TYPE_IPSEC_ESP, -+ HEADER_TYPE_UDP_ENCAP_ESP, /* RFC 3948 */ -+ HEADER_TYPE_MACSEC, -+ HEADER_TYPE_GRE, -+ HEADER_TYPE_MINENCAP, -+ HEADER_TYPE_DCCP, -+ HEADER_TYPE_ICMP, -+ HEADER_TYPE_IGMP, -+ HEADER_TYPE_ARP, -+ HEADER_TYPE_CAPWAP, -+ HEADER_TYPE_CAPWAP_DTLS, -+ HEADER_TYPE_RFC2684, -+ HEADER_TYPE_USER_DEFINED_L2, -+ HEADER_TYPE_USER_DEFINED_L3, -+ HEADER_TYPE_USER_DEFINED_L4, -+ HEADER_TYPE_USER_DEFINED_SHIM1, -+ HEADER_TYPE_USER_DEFINED_SHIM2, -+ MAX_HEADER_TYPE_COUNT -+} e_NetHeaderType; -+ -+ -+#endif /* __NET_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/std_ext.h -@@ -0,0 +1,48 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File std_ext.h -+ -+ @Description General Standard Definitions -+*//***************************************************************************/ -+ -+#ifndef __STD_EXT_H -+#define __STD_EXT_H -+ -+ -+#include "types_ext.h" -+#include "ncsw_ext.h" -+ -+ -+#endif /* __STD_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/stdarg_ext.h -@@ -0,0 +1,49 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#ifndef __STDARG_EXT_H -+#define __STDARG_EXT_H -+ -+ -+#if defined(NCSW_LINUX) && defined(__KERNEL__) -+#include -+ -+#else -+#include -+ -+#endif /* defined(NCSW_LINUX) && defined(__KERNEL__) */ -+ -+#include "std_ext.h" -+ -+ -+#endif /* __STDARG_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/stdlib_ext.h -@@ -0,0 +1,162 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+ -+#ifndef __STDLIB_EXT_H -+#define __STDLIB_EXT_H -+ -+ -+#if (defined(NCSW_LINUX)) && defined(__KERNEL__) -+#include "stdarg_ext.h" -+#include "std_ext.h" -+ -+ -+/** -+ * strtoul - convert a string to an uint32_t -+ * @cp: The start of the string -+ * @endp: A pointer to the end of the parsed string will be placed here -+ * @base: The number base to use -+ */ -+uint32_t strtoul(const char *cp,char **endp,uint32_t base); -+ -+/** -+ * strtol - convert a string to a int32_t -+ * @cp: The start of the string -+ * @endp: A pointer to the end of the parsed string will be placed here -+ * @base: The number base to use -+ */ -+long strtol(const char *cp,char **endp,uint32_t base); -+ -+/** -+ * strtoull - convert a string to an uint64_t -+ * @cp: The start of the string -+ * @endp: A pointer to the end of the parsed string will be placed here -+ * @base: The number base to use -+ */ -+uint64_t strtoull(const char *cp,char **endp,uint32_t base); -+ -+/** -+ * strtoll - convert a string to a int64 long -+ * @cp: The start of the string -+ * @endp: A pointer to the end of the parsed string will be placed here -+ * @base: The number base to use -+ */ -+long long strtoll(const char *cp,char **endp,uint32_t base); -+ -+/** -+ * atoi - convert a character to a int -+ * @s: The start of the string -+ */ -+int atoi(const char *s); -+ -+/** -+ * strnlen - Find the length of a length-limited string -+ * @s: The string to be sized -+ * @count: The maximum number of bytes to search -+ */ -+size_t strnlen(const char * s, size_t count); -+ -+/** -+ * strlen - Find the length of a string -+ * @s: The string to be sized -+ */ -+size_t strlen(const char * s); -+ -+/** -+ * strtok - Split a string into tokens -+ * @s: The string to be searched -+ * @ct: The characters to search for -+ * -+ * WARNING: strtok is deprecated, use strsep instead. -+ */ -+char * strtok(char * s,const char * ct); -+ -+/** -+ * strncpy - Copy a length-limited, %NUL-terminated string -+ * @dest: Where to copy the string to -+ * @src: Where to copy the string from -+ * @count: The maximum number of bytes to copy -+ * -+ * Note that unlike userspace strncpy, this does not %NUL-pad the buffer. -+ * However, the result is not %NUL-terminated if the source exceeds -+ * @count bytes. -+ */ -+char * strncpy(char * dest,const char *src,size_t count); -+ -+/** -+ * strcpy - Copy a %NUL terminated string -+ * @dest: Where to copy the string to -+ * @src: Where to copy the string from -+ */ -+char * strcpy(char * dest,const char *src); -+ -+/** -+ * vsscanf - Unformat a buffer into a list of arguments -+ * @buf: input buffer -+ * @fmt: format of buffer -+ * @args: arguments -+ */ -+int vsscanf(const char * buf, const char * fmt, va_list args); -+ -+/** -+ * vsnprintf - Format a string and place it in a buffer -+ * @buf: The buffer to place the result into -+ * @size: The size of the buffer, including the trailing null space -+ * @fmt: The format string to use -+ * @args: Arguments for the format string -+ * -+ * Call this function if you are already dealing with a va_list. -+ * You probably want snprintf instead. -+ */ -+int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); -+ -+/** -+ * vsprintf - Format a string and place it in a buffer -+ * @buf: The buffer to place the result into -+ * @fmt: The format string to use -+ * @args: Arguments for the format string -+ * -+ * Call this function if you are already dealing with a va_list. -+ * You probably want sprintf instead. -+ */ -+int vsprintf(char *buf, const char *fmt, va_list args); -+ -+#else -+#include -+#include -+#endif /* defined(NCSW_LINUX) && defined(__KERNEL__) */ -+ -+#include "std_ext.h" -+ -+ -+#endif /* __STDLIB_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/string_ext.h -@@ -0,0 +1,56 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#ifndef __STRING_EXT_H -+#define __STRING_EXT_H -+ -+ -+#if defined(NCSW_LINUX) && defined(__KERNEL__) -+#include -+#include -+extern char * strtok ( char * str, const char * delimiters ); -+ -+#elif defined(__KERNEL__) -+#include "linux/types.h" -+#include "linux/posix_types.h" -+#include "linux/string.h" -+ -+#else -+#include -+ -+#endif /* defined(NCSW_LINUX) && defined(__KERNEL__) */ -+ -+#include "std_ext.h" -+ -+ -+#endif /* __STRING_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/types_ext.h -@@ -0,0 +1,62 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File types_ext.h -+ -+ @Description General types Standard Definitions -+*//***************************************************************************/ -+ -+#ifndef __TYPES_EXT_H -+#define __TYPES_EXT_H -+ -+#if defined(NCSW_LINUX) -+#include "types_linux.h" -+ -+#elif defined(NCSW_VXWORKS) -+#include "types_vxworks.h" -+ -+#elif defined(__GNUC__) && defined(__cplusplus) -+#include "types_bb_gpp.h" -+ -+#elif defined(__GNUC__) -+#include "types_bb_gcc.h" -+ -+#elif defined(__ghs__) -+#include "types_ghs.h" -+ -+#else -+#include "types_dflt.h" -+#endif /* defined (__ROCOO__) */ -+ -+#endif /* __TYPES_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/xx_common.h -@@ -0,0 +1,56 @@ -+/* -+ * Copyright 2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File debug_ext.h -+ -+ @Description Debug mode definitions. -+*//***************************************************************************/ -+ -+#ifndef __XX_COMMON_H -+#define __XX_COMMON_H -+ -+/***************************************************************************** -+ * UNIFIED MODULE CODES -+ *****************************************************************************/ -+#define MODULE_UNKNOWN 0x00000000 -+#define MODULE_FM 0x00010000 -+#define MODULE_FM_MURAM 0x00020000 -+#define MODULE_FM_PCD 0x00030000 -+#define MODULE_FM_RTC 0x00040000 -+#define MODULE_FM_MAC 0x00050000 -+#define MODULE_FM_PORT 0x00060000 -+#define MODULE_MM 0x00070000 -+#define MODULE_FM_SP 0x00080000 -+#define MODULE_FM_MACSEC 0x00090000 -+#endif /* __XX_COMMON_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/xx_ext.h -@@ -0,0 +1,791 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File xx_ext.h -+ -+ @Description Prototypes, externals and typedefs for system-supplied -+ (external) routines -+*//***************************************************************************/ -+ -+#ifndef __XX_EXT_H -+#define __XX_EXT_H -+ -+#include "std_ext.h" -+#include "xx_common.h" -+#include "part_ext.h" -+ -+ -+ -+/**************************************************************************//** -+ @Group xx_id XX Interface (System call hooks) -+ -+ @Description Prototypes, externals and typedefs for system-supplied -+ (external) routines -+ -+ @{ -+*//***************************************************************************/ -+ -+#ifdef DEBUG_XX_MALLOC -+void * XX_MallocDebug(uint32_t size, char *fname, int line); -+ -+void * XX_MallocSmartDebug(uint32_t size, -+ int memPartitionId, -+ uint32_t alignment, -+ char *fname, -+ int line); -+ -+#define XX_Malloc(sz) \ -+ XX_MallocDebug((sz), __FILE__, __LINE__) -+ -+#define XX_MallocSmart(sz, memt, al) \ -+ XX_MallocSmartDebug((sz), (memt), (al), __FILE__, __LINE__) -+ -+#else /* not DEBUG_XX_MALLOC */ -+/**************************************************************************//** -+ @Function XX_Malloc -+ -+ @Description allocates contiguous block of memory. -+ -+ @Param[in] size - Number of bytes to allocate. -+ -+ @Return The address of the newly allocated block on success, NULL on failure. -+*//***************************************************************************/ -+void * XX_Malloc(uint32_t size); -+ -+/**************************************************************************//** -+ @Function XX_MallocSmart -+ -+ @Description Allocates contiguous block of memory in a specified -+ alignment and from the specified segment. -+ -+ @Param[in] size - Number of bytes to allocate. -+ @Param[in] memPartitionId - Memory partition ID; The value zero must -+ be mapped to the default heap partition. -+ @Param[in] alignment - Required memory alignment (in bytes). -+ -+ @Return The address of the newly allocated block on success, NULL on failure. -+*//***************************************************************************/ -+void * XX_MallocSmart(uint32_t size, int memPartitionId, uint32_t alignment); -+#endif /* not DEBUG_XX_MALLOC */ -+ -+/**************************************************************************//** -+ @Function XX_FreeSmart -+ -+ @Description Frees the memory block pointed to by "p". -+ Only for memory allocated by XX_MallocSmart -+ -+ @Param[in] p_Memory - pointer to the memory block. -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_FreeSmart(void *p_Memory); -+ -+/**************************************************************************//** -+ @Function XX_Free -+ -+ @Description frees the memory block pointed to by "p". -+ -+ @Param[in] p_Memory - pointer to the memory block. -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_Free(void *p_Memory); -+ -+/**************************************************************************//** -+ @Function XX_Print -+ -+ @Description print a string. -+ -+ @Param[in] str - string to print. -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_Print(char *str, ...); -+ -+/**************************************************************************//** -+ @Function XX_SetIntr -+ -+ @Description Set an interrupt service routine for a specific interrupt source. -+ -+ @Param[in] irq - Interrupt ID (system-specific number). -+ @Param[in] f_Isr - Callback routine that will be called when the interrupt occurs. -+ @Param[in] handle - The argument for the user callback routine. -+ -+ @Return E_OK on success; error code otherwise.. -+*//***************************************************************************/ -+t_Error XX_SetIntr(int irq, t_Isr *f_Isr, t_Handle handle); -+ -+/**************************************************************************//** -+ @Function XX_FreeIntr -+ -+ @Description Free a specific interrupt and a specific callback routine. -+ -+ @Param[in] irq - Interrupt ID (system-specific number). -+ -+ @Return E_OK on success; error code otherwise.. -+*//***************************************************************************/ -+t_Error XX_FreeIntr(int irq); -+ -+/**************************************************************************//** -+ @Function XX_EnableIntr -+ -+ @Description Enable a specific interrupt. -+ -+ @Param[in] irq - Interrupt ID (system-specific number). -+ -+ @Return E_OK on success; error code otherwise.. -+*//***************************************************************************/ -+t_Error XX_EnableIntr(int irq); -+ -+/**************************************************************************//** -+ @Function XX_DisableIntr -+ -+ @Description Disable a specific interrupt. -+ -+ @Param[in] irq - Interrupt ID (system-specific number). -+ -+ @Return E_OK on success; error code otherwise.. -+*//***************************************************************************/ -+t_Error XX_DisableIntr(int irq); -+ -+/**************************************************************************//** -+ @Function XX_DisableAllIntr -+ -+ @Description Disable all interrupts by masking them at the CPU. -+ -+ @Return A value that represents the interrupts state before the -+ operation, and should be passed to the matching -+ XX_RestoreAllIntr() call. -+*//***************************************************************************/ -+uint32_t XX_DisableAllIntr(void); -+ -+/**************************************************************************//** -+ @Function XX_RestoreAllIntr -+ -+ @Description Restore previous state of interrupts level at the CPU. -+ -+ @Param[in] flags - A value that represents the interrupts state to restore, -+ as returned by the matching call for XX_DisableAllIntr(). -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_RestoreAllIntr(uint32_t flags); -+ -+ -+/**************************************************************************//** -+ @Function XX_Exit -+ -+ @Description Stop execution and report status (where it is applicable) -+ -+ @Param[in] status - exit status -+*//***************************************************************************/ -+void XX_Exit(int status); -+ -+ -+/*****************************************************************************/ -+/* Tasklet Service Routines */ -+/*****************************************************************************/ -+typedef t_Handle t_TaskletHandle; -+ -+/**************************************************************************//** -+ @Function XX_InitTasklet -+ -+ @Description Create and initialize a tasklet object. -+ -+ @Param[in] routine - A routine to be ran as a tasklet. -+ @Param[in] data - An argument to pass to the tasklet. -+ -+ @Return Tasklet handle is returned on success. NULL is returned otherwise. -+*//***************************************************************************/ -+t_TaskletHandle XX_InitTasklet (void (*routine)(void *), void *data); -+ -+/**************************************************************************//** -+ @Function XX_FreeTasklet -+ -+ @Description Free a tasklet object. -+ -+ @Param[in] h_Tasklet - A handle to a tasklet to be free. -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_FreeTasklet (t_TaskletHandle h_Tasklet); -+ -+/**************************************************************************//** -+ @Function XX_ScheduleTask -+ -+ @Description Schedule a tasklet object. -+ -+ @Param[in] h_Tasklet - A handle to a tasklet to be scheduled. -+ @Param[in] immediate - Indicate whether to schedule this tasklet on -+ the immediate queue or on the delayed one. -+ -+ @Return 0 - on success. Error code - otherwise. -+*//***************************************************************************/ -+int XX_ScheduleTask(t_TaskletHandle h_Tasklet, int immediate); -+ -+/**************************************************************************//** -+ @Function XX_FlushScheduledTasks -+ -+ @Description Flush all tasks there are in the scheduled tasks queue. -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_FlushScheduledTasks(void); -+ -+/**************************************************************************//** -+ @Function XX_TaskletIsQueued -+ -+ @Description Check if task is queued. -+ -+ @Param[in] h_Tasklet - A handle to a tasklet to be scheduled. -+ -+ @Return 1 - task is queued. 0 - otherwise. -+*//***************************************************************************/ -+int XX_TaskletIsQueued(t_TaskletHandle h_Tasklet); -+ -+/**************************************************************************//** -+ @Function XX_SetTaskletData -+ -+ @Description Set data to a scheduled task. Used to change data of already -+ scheduled task. -+ -+ @Param[in] h_Tasklet - A handle to a tasklet to be scheduled. -+ @Param[in] data - Data to be set. -+*//***************************************************************************/ -+void XX_SetTaskletData(t_TaskletHandle h_Tasklet, t_Handle data); -+ -+/**************************************************************************//** -+ @Function XX_GetTaskletData -+ -+ @Description Get the data of scheduled task. -+ -+ @Param[in] h_Tasklet - A handle to a tasklet to be scheduled. -+ -+ @Return handle to the data of the task. -+*//***************************************************************************/ -+t_Handle XX_GetTaskletData(t_TaskletHandle h_Tasklet); -+ -+/**************************************************************************//** -+ @Function XX_BottomHalf -+ -+ @Description Bottom half implementation, invoked by the interrupt handler. -+ -+ This routine handles all bottom-half tasklets with interrupts -+ enabled. -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_BottomHalf(void); -+ -+ -+/*****************************************************************************/ -+/* Spinlock Service Routines */ -+/*****************************************************************************/ -+ -+/**************************************************************************//** -+ @Function XX_InitSpinlock -+ -+ @Description Creates a spinlock. -+ -+ @Return Spinlock handle is returned on success; NULL otherwise. -+*//***************************************************************************/ -+t_Handle XX_InitSpinlock(void); -+ -+/**************************************************************************//** -+ @Function XX_FreeSpinlock -+ -+ @Description Frees the memory allocated for the spinlock creation. -+ -+ @Param[in] h_Spinlock - A handle to a spinlock. -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_FreeSpinlock(t_Handle h_Spinlock); -+ -+/**************************************************************************//** -+ @Function XX_LockSpinlock -+ -+ @Description Locks a spinlock. -+ -+ @Param[in] h_Spinlock - A handle to a spinlock. -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_LockSpinlock(t_Handle h_Spinlock); -+ -+/**************************************************************************//** -+ @Function XX_UnlockSpinlock -+ -+ @Description Unlocks a spinlock. -+ -+ @Param[in] h_Spinlock - A handle to a spinlock. -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_UnlockSpinlock(t_Handle h_Spinlock); -+ -+/**************************************************************************//** -+ @Function XX_LockIntrSpinlock -+ -+ @Description Locks a spinlock (interrupt safe). -+ -+ @Param[in] h_Spinlock - A handle to a spinlock. -+ -+ @Return A value that represents the interrupts state before the -+ operation, and should be passed to the matching -+ XX_UnlockIntrSpinlock() call. -+*//***************************************************************************/ -+uint32_t XX_LockIntrSpinlock(t_Handle h_Spinlock); -+ -+/**************************************************************************//** -+ @Function XX_UnlockIntrSpinlock -+ -+ @Description Unlocks a spinlock (interrupt safe). -+ -+ @Param[in] h_Spinlock - A handle to a spinlock. -+ @Param[in] intrFlags - A value that represents the interrupts state to -+ restore, as returned by the matching call for -+ XX_LockIntrSpinlock(). -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_UnlockIntrSpinlock(t_Handle h_Spinlock, uint32_t intrFlags); -+ -+ -+/*****************************************************************************/ -+/* Timers Service Routines */ -+/*****************************************************************************/ -+ -+/**************************************************************************//** -+ @Function XX_CurrentTime -+ -+ @Description Returns current system time. -+ -+ @Return Current system time (in milliseconds). -+*//***************************************************************************/ -+uint32_t XX_CurrentTime(void); -+ -+/**************************************************************************//** -+ @Function XX_CreateTimer -+ -+ @Description Creates a timer. -+ -+ @Return Timer handle is returned on success; NULL otherwise. -+*//***************************************************************************/ -+t_Handle XX_CreateTimer(void); -+ -+/**************************************************************************//** -+ @Function XX_FreeTimer -+ -+ @Description Frees the memory allocated for the timer creation. -+ -+ @Param[in] h_Timer - A handle to a timer. -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_FreeTimer(t_Handle h_Timer); -+ -+/**************************************************************************//** -+ @Function XX_StartTimer -+ -+ @Description Starts a timer. -+ -+ The user can select to start the timer as periodic timer or as -+ one-shot timer. The user should provide a callback routine that -+ will be called when the timer expires. -+ -+ @Param[in] h_Timer - A handle to a timer. -+ @Param[in] msecs - Timer expiration period (in milliseconds). -+ @Param[in] periodic - TRUE for a periodic timer; -+ FALSE for a one-shot timer.. -+ @Param[in] f_TimerExpired - A callback routine to be called when the -+ timer expires. -+ @Param[in] h_Arg - The argument to pass in the timer-expired -+ callback routine. -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_StartTimer(t_Handle h_Timer, -+ uint32_t msecs, -+ bool periodic, -+ void (*f_TimerExpired)(t_Handle h_Arg), -+ t_Handle h_Arg); -+ -+/**************************************************************************//** -+ @Function XX_StopTimer -+ -+ @Description Frees the memory allocated for the timer creation. -+ -+ @Param[in] h_Timer - A handle to a timer. -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_StopTimer(t_Handle h_Timer); -+ -+/**************************************************************************//** -+ @Function XX_ModTimer -+ -+ @Description Updates the expiration time of a timer. -+ -+ This routine adds the given time to the current system time, -+ and sets this value as the new expiration time of the timer. -+ -+ @Param[in] h_Timer - A handle to a timer. -+ @Param[in] msecs - The new interval until timer expiration -+ (in milliseconds). -+ -+ @Return None. -+*//***************************************************************************/ -+void XX_ModTimer(t_Handle h_Timer, uint32_t msecs); -+ -+/**************************************************************************//** -+ @Function XX_Sleep -+ -+ @Description Non-busy wait until the desired time (in milliseconds) has passed. -+ -+ @Param[in] msecs - The requested sleep time (in milliseconds). -+ -+ @Return Zero if the requested time has elapsed; Otherwise, the value -+ returned will be the unslept amount) in milliseconds. -+ -+ @Cautions This routine enables interrupts during its wait time. -+*//***************************************************************************/ -+uint32_t XX_Sleep(uint32_t msecs); -+ -+/**************************************************************************//** -+ @Function XX_UDelay -+ -+ @Description Busy-wait until the desired time (in microseconds) has passed. -+ -+ @Param[in] usecs - The requested delay time (in microseconds). -+ -+ @Return None. -+ -+ @Cautions It is highly unrecommended to call this routine during interrupt -+ time, because the system time may not be updated properly during -+ the delay loop. The behavior of this routine during interrupt -+ time is unexpected. -+*//***************************************************************************/ -+void XX_UDelay(uint32_t usecs); -+ -+ -+/*****************************************************************************/ -+/* Other Service Routines */ -+/*****************************************************************************/ -+ -+/**************************************************************************//** -+ @Function XX_PhysToVirt -+ -+ @Description Translates a physical address to the matching virtual address. -+ -+ @Param[in] addr - The physical address to translate. -+ -+ @Return Virtual address. -+*//***************************************************************************/ -+void * XX_PhysToVirt(physAddress_t addr); -+ -+/**************************************************************************//** -+ @Function XX_VirtToPhys -+ -+ @Description Translates a virtual address to the matching physical address. -+ -+ @Param[in] addr - The virtual address to translate. -+ -+ @Return Physical address. -+*//***************************************************************************/ -+physAddress_t XX_VirtToPhys(void *addr); -+ -+ -+/**************************************************************************//** -+ @Group xx_ipc XX Inter-Partition-Communication API -+ -+ @Description The following API is to be used when working with multiple -+ partitions configuration. -+ -+ @{ -+*//***************************************************************************/ -+ -+#define XX_IPC_MAX_ADDR_NAME_LENGTH 16 /**< Maximum length of an endpoint name string; -+ The IPC service can use this constant to limit -+ the storage space for IPC endpoint names. */ -+ -+ -+/**************************************************************************//** -+ @Function t_IpcMsgCompletion -+ -+ @Description Callback function used upon IPC non-blocking transaction completion -+ to return message buffer to the caller and to forward reply if available. -+ -+ This callback function may be attached by the source endpoint to any outgoing -+ IPC message to indicate a non-blocking send (see also XX_IpcSendMessage() routine). -+ Upon completion of an IPC transaction (consisting of a message and an optional reply), -+ the IPC service invokes this callback routine to return the message buffer to the sender -+ and to provide the received reply, if requested. -+ -+ User provides this function. Driver invokes it. -+ -+ @Param[in] h_Module - Abstract handle to the sending module - the same handle as was passed -+ in the XX_IpcSendMessage() function; This handle is typically used to point -+ to the internal data structure of the source endpoint. -+ @Param[in] p_Msg - Pointer to original (sent) message buffer; -+ The source endpoint can free (or reuse) this buffer when message -+ completion callback is called. -+ @Param[in] p_Reply - Pointer to (received) reply buffer; -+ This pointer is the same as was provided by the source endpoint in -+ XX_IpcSendMessage(). -+ @Param[in] replyLength - Length (in bytes) of actual data in the reply buffer. -+ @Param[in] status - Completion status - E_OK or failure indication, e.g. IPC transaction completion -+ timeout. -+ -+ @Return None -+ *//***************************************************************************/ -+typedef void (t_IpcMsgCompletion)(t_Handle h_Module, -+ uint8_t *p_Msg, -+ uint8_t *p_Reply, -+ uint32_t replyLength, -+ t_Error status); -+ -+/**************************************************************************//** -+ @Function t_IpcMsgHandler -+ -+ @Description Callback function used as IPC message handler. -+ -+ The IPC service invokes message handlers for each IPC message received. -+ The actual function pointer should be registered by each destination endpoint -+ via the XX_IpcRegisterMsgHandler() routine. -+ -+ User provides this function. Driver invokes it. -+ -+ @Param[in] h_Module - Abstract handle to the message handling module - the same handle as -+ was passed in the XX_IpcRegisterMsgHandler() function; this handle is -+ typically used to point to the internal data structure of the destination -+ endpoint. -+ @Param[in] p_Msg - Pointer to message buffer with data received from peer. -+ @Param[in] msgLength - Length (in bytes) of message data. -+ @Param[in] p_Reply - Pointer to reply buffer, to be filled by the message handler and then sent -+ by the IPC service; -+ The reply buffer is allocated by the IPC service with size equals to the -+ replyLength parameter provided in message handler registration (see -+ XX_IpcRegisterMsgHandler() function); -+ If replyLength was initially specified as zero during message handler registration, -+ the IPC service may set this pointer to NULL and assume that a reply is not needed; -+ The IPC service is also responsible for freeing the reply buffer after the -+ reply has been sent or dismissed. -+ @Param[in,out] p_ReplyLength - Pointer to reply length, which has a dual role in this function: -+ [In] equals the replyLength parameter provided in message handler -+ registration (see XX_IpcRegisterMsgHandler() function), and -+ [Out] should be updated by message handler to the actual reply length; if -+ this value is set to zero, the IPC service must assume that a reply should -+ not be sent; -+ Note: If p_Reply is not NULL, p_ReplyLength must not be NULL as well. -+ -+ @Return E_OK on success; Error code otherwise. -+ *//***************************************************************************/ -+typedef t_Error (t_IpcMsgHandler)(t_Handle h_Module, -+ uint8_t *p_Msg, -+ uint32_t msgLength, -+ uint8_t *p_Reply, -+ uint32_t *p_ReplyLength); -+ -+/**************************************************************************//** -+ @Function XX_IpcRegisterMsgHandler -+ -+ @Description IPC mailbox registration. -+ -+ This function is used for registering an IPC message handler in the IPC service. -+ This function is called by each destination endpoint to indicate that it is ready -+ to handle incoming messages. The IPC service invokes the message handler upon receiving -+ a message addressed to the specified destination endpoint. -+ -+ @Param[in] addr - The address name string associated with the destination endpoint; -+ This address must be unique across the IPC service domain to ensure -+ correct message routing. -+ @Param[in] f_MsgHandler - Pointer to the message handler callback for processing incoming -+ message; invoked by the IPC service upon receiving a message -+ addressed to the destination endpoint specified by the addr -+ parameter. -+ @Param[in] h_Module - Abstract handle to the message handling module, passed unchanged -+ to f_MsgHandler callback function. -+ @Param[in] replyLength - The maximal data length (in bytes) of any reply that the specified message handler -+ may generate; the IPC service provides the message handler with buffer -+ for reply according to the length specified here (refer also to the description -+ of #t_IpcMsgHandler callback function type); -+ This size shall be zero if the message handler never generates replies. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error XX_IpcRegisterMsgHandler(char addr[XX_IPC_MAX_ADDR_NAME_LENGTH], -+ t_IpcMsgHandler *f_MsgHandler, -+ t_Handle h_Module, -+ uint32_t replyLength); -+ -+/**************************************************************************//** -+ @Function XX_IpcUnregisterMsgHandler -+ -+ @Description Release IPC mailbox routine. -+ -+ This function is used for unregistering an IPC message handler from the IPC service. -+ This function is called by each destination endpoint to indicate that it is no longer -+ capable of handling incoming messages. -+ -+ @Param[in] addr - The address name string associated with the destination endpoint; -+ This address is the same as was used when the message handler was -+ registered via XX_IpcRegisterMsgHandler(). -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error XX_IpcUnregisterMsgHandler(char addr[XX_IPC_MAX_ADDR_NAME_LENGTH]); -+ -+/**************************************************************************//** -+ @Function XX_IpcInitSession -+ -+ @Description This function is used for creating an IPC session between the source endpoint -+ and the destination endpoint. -+ -+ The actual implementation and representation of a session is left for the IPC service. -+ The function returns an abstract handle to the created session. This handle shall be used -+ by the source endpoint in subsequent calls to XX_IpcSendMessage(). -+ The IPC service assumes that before this function is called, no messages are sent from -+ the specified source endpoint to the specified destination endpoint. -+ -+ The IPC service may use a connection-oriented approach or a connectionless approach (or both) -+ as described below. -+ -+ @par Connection-Oriented Approach -+ -+ The IPC service may implement a session in a connection-oriented approach - when this function is called, -+ the IPC service should take the necessary steps to bring up a source-to-destination channel for messages -+ and a destination-to-source channel for replies. The returned handle should represent the internal -+ representation of these channels. -+ -+ @par Connectionless Approach -+ -+ The IPC service may implement a session in a connectionless approach - when this function is called, the -+ IPC service should not perform any particular steps, but it must store the pair of source and destination -+ addresses in some session representation and return it as a handle. When XX_IpcSendMessage() shall be -+ called, the IPC service may use this handle to provide the necessary identifiers for routing the messages -+ through the connectionless medium. -+ -+ @Param[in] destAddr - The address name string associated with the destination endpoint. -+ @Param[in] srcAddr - The address name string associated with the source endpoint. -+ -+ @Return Abstract handle to the initialized session, or NULL on error. -+*//***************************************************************************/ -+t_Handle XX_IpcInitSession(char destAddr[XX_IPC_MAX_ADDR_NAME_LENGTH], -+ char srcAddr[XX_IPC_MAX_ADDR_NAME_LENGTH]); -+ -+/**************************************************************************//** -+ @Function XX_IpcFreeSession -+ -+ @Description This function is used for terminating an existing IPC session between a source endpoint -+ and a destination endpoint. -+ -+ The IPC service assumes that after this function is called, no messages shall be sent from -+ the associated source endpoint to the associated destination endpoint. -+ -+ @Param[in] h_Session - Abstract handle to the IPC session - the same handle as was originally -+ returned by the XX_IpcInitSession() function. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error XX_IpcFreeSession(t_Handle h_Session); -+ -+/**************************************************************************//** -+ @Function XX_IpcSendMessage -+ -+ @Description IPC message send routine. -+ -+ This function may be used by a source endpoint to send an IPC message to a destination -+ endpoint. The source endpoint cannot send a message to the destination endpoint without -+ first initiating a session with that destination endpoint via XX_IpcInitSession() routine. -+ -+ The source endpoint must provide the buffer pointer and length of the outgoing message. -+ Optionally, it may also provide a buffer for an expected reply. In the latter case, the -+ transaction is not considered complete by the IPC service until the reply has been received. -+ If the source endpoint does not provide a reply buffer, the transaction is considered -+ complete after the message has been sent. The source endpoint must keep the message (and -+ optional reply) buffers valid until the transaction is complete. -+ -+ @par Non-blocking mode -+ -+ The source endpoint may request a non-blocking send by providing a non-NULL pointer to a message -+ completion callback function (f_Completion). Upon completion of the IPC transaction (consisting of a -+ message and an optional reply), the IPC service invokes this callback routine to return the message -+ buffer to the sender and to provide the received reply, if requested. -+ -+ @par Blocking mode -+ -+ The source endpoint may request a blocking send by setting f_Completion to NULL. The function is -+ expected to block until the IPC transaction is complete - either the reply has been received or (if no reply -+ was requested) the message has been sent. -+ -+ @Param[in] h_Session - Abstract handle to the IPC session - the same handle as was originally -+ returned by the XX_IpcInitSession() function. -+ @Param[in] p_Msg - Pointer to message buffer to send. -+ @Param[in] msgLength - Length (in bytes) of actual data in the message buffer. -+ @Param[in] p_Reply - Pointer to reply buffer - if this buffer is not NULL, the IPC service -+ fills this buffer with the received reply data; -+ In blocking mode, the reply data must be valid when the function returns; -+ In non-blocking mode, the reply data is valid when f_Completion is called; -+ If this pointer is NULL, no reply is expected. -+ @Param[in,out] p_ReplyLength - Pointer to reply length, which has a dual role in this function: -+ [In] specifies the maximal length (in bytes) of the reply buffer pointed by -+ p_Reply, and -+ [Out] in non-blocking mode this value is updated by the IPC service to the -+ actual reply length (in bytes). -+ @Param[in] f_Completion - Pointer to a completion callback to be used in non-blocking send mode; -+ The completion callback is invoked by the IPC service upon -+ completion of the IPC transaction (consisting of a message and an optional -+ reply); -+ If this pointer is NULL, the function is expected to block until the IPC -+ transaction is complete. -+ @Param[in] h_Arg - Abstract handle to the sending module; passed unchanged to the f_Completion -+ callback function as the first argument. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error XX_IpcSendMessage(t_Handle h_Session, -+ uint8_t *p_Msg, -+ uint32_t msgLength, -+ uint8_t *p_Reply, -+ uint32_t *p_ReplyLength, -+ t_IpcMsgCompletion *f_Completion, -+ t_Handle h_Arg); -+ -+ -+/** @} */ /* end of xx_ipc group */ -+/** @} */ /* end of xx_id group */ -+ -+ -+#endif /* __XX_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/ls1043_dflags.h -@@ -0,0 +1,56 @@ -+/* -+ * Copyright 2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __dflags_h -+#define __dflags_h -+ -+ -+#define NCSW_LINUX -+ -+#define LS1043 -+ -+#define DEBUG_ERRORS 1 -+ -+#if defined(DEBUG) -+#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_INFO -+ -+#define DEBUG_XX_MALLOC -+#define DEBUG_MEM_LEAKS -+ -+#else -+#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_WARNING -+#endif /* (DEBUG) */ -+ -+#define REPORT_EVENTS 1 -+#define EVENT_GLOBAL_LEVEL REPORT_LEVEL_MINOR -+ -+#endif /* __dflags_h */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -@@ -0,0 +1,53 @@ -+# -+# Makefile config for the Freescale NetcommSW -+# -+NET_DPA = $(srctree)/drivers/net -+DRV_DPA = $(srctree)/drivers/net/ethernet/freescale/sdk_dpaa -+FMAN = $(srctree)/drivers/net/ethernet/freescale/sdk_fman -+ -+ifeq ("$(CONFIG_FMAN_P3040_P4080_P5020)", "y") -+ccflags-y +=-include $(FMAN)/p3040_4080_5020_dflags.h -+endif -+ifeq ("$(CONFIG_FMAN_P1023)", "y") -+ccflags-y +=-include $(FMAN)/p1023_dflags.h -+endif -+ifdef CONFIG_FMAN_V3H -+ccflags-y +=-include $(FMAN)/fmanv3h_dflags.h -+endif -+ifdef CONFIG_FMAN_V3L -+ccflags-y +=-include $(FMAN)/fmanv3l_dflags.h -+endif -+ifdef CONFIG_FMAN_ARM -+ccflags-y +=-include $(FMAN)/ls1043_dflags.h -+endif -+ -+ccflags-y += -I$(DRV_DPA)/ -+ccflags-y += -I$(FMAN)/inc -+ccflags-y += -I$(FMAN)/inc/cores -+ccflags-y += -I$(FMAN)/inc/etc -+ccflags-y += -I$(FMAN)/inc/Peripherals -+ccflags-y += -I$(FMAN)/inc/flib -+ -+ifeq ("$(CONFIG_FMAN_P3040_P4080_P5020)", "y") -+ccflags-y += -I$(FMAN)/inc/integrations/P3040_P4080_P5020 -+endif -+ifeq ("$(CONFIG_FMAN_P1023)", "y") -+ccflags-y += -I$(FMAN)/inc/integrations/P1023 -+endif -+ifdef CONFIG_FMAN_V3H -+ccflags-y += -I$(FMAN)/inc/integrations/FMANV3H -+endif -+ifdef CONFIG_FMAN_V3L -+ccflags-y += -I$(FMAN)/inc/integrations/FMANV3L -+endif -+ifdef CONFIG_FMAN_ARM -+ccflags-y += -I$(FMAN)/inc/integrations/LS1043 -+endif -+ -+ccflags-y += -I$(FMAN)/src/inc -+ccflags-y += -I$(FMAN)/src/inc/system -+ccflags-y += -I$(FMAN)/src/inc/wrapper -+ccflags-y += -I$(FMAN)/src/inc/xx -+ccflags-y += -I$(srctree)/include/uapi/linux/fmd -+ccflags-y += -I$(srctree)/include/uapi/linux/fmd/Peripherals -+ccflags-y += -I$(srctree)/include/uapi/linux/fmd/integrations ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/p1023_dflags.h -@@ -0,0 +1,65 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __dflags_h -+#define __dflags_h -+ -+ -+#define NCSW_LINUX -+#if 0 -+#define DEBUG -+#endif -+ -+#define P1023 -+#define NCSW_PPC_CORE -+ -+#define DEBUG_ERRORS 1 -+ -+#if defined(DEBUG) -+#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_INFO -+ -+#define DEBUG_XX_MALLOC -+#define DEBUG_MEM_LEAKS -+ -+#else -+#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_WARNING -+#endif /* (DEBUG) */ -+ -+#define REPORT_EVENTS 1 -+#define EVENT_GLOBAL_LEVEL REPORT_LEVEL_MINOR -+ -+#ifdef CONFIG_P4080_SIM -+#error "Do not define CONFIG_P4080_SIM..." -+#endif -+ -+ -+#endif /* __dflags_h */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/p3040_4080_5020_dflags.h -@@ -0,0 +1,62 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __dflags_h -+#define __dflags_h -+ -+ -+#define NCSW_LINUX -+ -+#define P4080 -+#define NCSW_PPC_CORE -+ -+#define DEBUG_ERRORS 1 -+ -+#if defined(DEBUG) -+#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_INFO -+ -+#define DEBUG_XX_MALLOC -+#define DEBUG_MEM_LEAKS -+ -+#else -+#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_WARNING -+#endif /* (DEBUG) */ -+ -+#define REPORT_EVENTS 1 -+#define EVENT_GLOBAL_LEVEL REPORT_LEVEL_MINOR -+ -+#ifdef CONFIG_P4080_SIM -+#define SIMULATOR -+#endif /* CONFIG_P4080_SIM */ -+ -+ -+#endif /* __dflags_h */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/Makefile -@@ -0,0 +1,11 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+# -+obj-y += system/ -+obj-y += wrapper/ -+obj-y += xx/ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/inc/system/sys_ext.h -@@ -0,0 +1,118 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __SYS_EXT_H -+#define __SYS_EXT_H -+ -+#include "std_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group sys_grp System Interfaces -+ -+ @Description Linux system programming interfaces. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group sys_gen_grp System General Interface -+ -+ @Description General definitions, structures and routines of the linux -+ system programming interface. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Collection Macros for Advanced Configuration Requests -+ @{ -+*//***************************************************************************/ -+#define SYS_MAX_ADV_CONFIG_ARGS 4 -+ /**< Maximum number of arguments in -+ an advanced configuration entry */ -+/* @} */ -+ -+/**************************************************************************//** -+ @Description System Object Advanced Configuration Entry -+ -+ This structure represents a single request for an advanced -+ configuration call on the initialized object. An array of such -+ requests may be contained in the settings structure of the -+ corresponding object. -+ -+ The maximum number of arguments is limited to #SYS_MAX_ADV_CONFIG_ARGS. -+*//***************************************************************************/ -+typedef struct t_SysObjectAdvConfigEntry -+{ -+ void *p_Function; /**< Pointer to advanced configuration routine */ -+ -+ uintptr_t args[SYS_MAX_ADV_CONFIG_ARGS]; -+ /**< Array of arguments for the specified routine; -+ All arguments should be casted to uint32_t. */ -+} t_SysObjectAdvConfigEntry; -+ -+ -+/** @} */ /* end of sys_gen_grp */ -+/** @} */ /* end of sys_grp */ -+ -+#define NCSW_PARAMS(_num, _params) ADV_CONFIG_PARAMS_##_num _params -+ -+#define ADV_CONFIG_PARAMS_1(_type) \ -+ , (_type)p_Entry->args[0] -+ -+#define SET_ADV_CONFIG_ARGS_1(_arg0) \ -+ p_Entry->args[0] = (uintptr_t )(_arg0); \ -+ -+#define ARGS(_num, _params) SET_ADV_CONFIG_ARGS_##_num _params -+ -+#define ADD_ADV_CONFIG_START(_p_Entries, _maxEntries) \ -+ { \ -+ t_SysObjectAdvConfigEntry *p_Entry; \ -+ t_SysObjectAdvConfigEntry *p_Entrys = (_p_Entries); \ -+ int i=0, max = (_maxEntries); \ -+ -+#define ADD_ADV_CONFIG_END \ -+ } -+ -+#define ADV_CONFIG_CHECK_START(_p_Entry) \ -+ { \ -+ t_SysObjectAdvConfigEntry *p_Entry = _p_Entry; \ -+ t_Error errCode; \ -+ -+#define ADV_CONFIG_CHECK(_handle, _func, _params) \ -+ if (p_Entry->p_Function == _func) \ -+ { \ -+ errCode = _func(_handle _params); \ -+ } else -+ -+#endif /* __SYS_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/inc/system/sys_io_ext.h -@@ -0,0 +1,46 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __SYS_IO_EXT_H -+#define __SYS_IO_EXT_H -+ -+#include "std_ext.h" -+#include "error_ext.h" -+ -+ -+t_Error SYS_RegisterIoMap (uint64_t virtAddr, uint64_t physAddr, uint32_t size); -+t_Error SYS_UnregisterIoMap (uint64_t virtAddr); -+uint64_t SYS_PhysToVirt (uint64_t addr); -+uint64_t SYS_VirtToPhys (uint64_t addr); -+ -+ -+#endif /* __SYS_IO_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/inc/types_linux.h -@@ -0,0 +1,208 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __TYPES_LINUX_H__ -+#define __TYPES_LINUX_H__ -+ -+#include -+ -+#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS) -+#define MODVERSIONS -+#endif -+#ifdef MODVERSIONS -+#include -+#endif /* MODVERSIONS */ -+ -+#include -+#include -+#include -+#include -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) -+ #error "This kernel is probably not supported!!!" -+#elif (!((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)) || \ -+ (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)) || \ -+ (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,30)))) -+ #warning "This kernel is probably not supported!!! You may need to add some fixes." -+#endif /* LINUX_VERSION_CODE */ -+ -+ -+typedef float float_t; /* Single precision floating point */ -+typedef double double_t; /* Double precision floating point */ -+ -+ -+#define _Packed -+#define _PackedType __attribute__ ((packed)) -+ -+typedef phys_addr_t physAddress_t; -+ -+#define UINT8_MAX 0xFF -+#define UINT8_MIN 0 -+#define UINT16_MAX 0xFFFF -+#define UINT16_MIN 0 -+#define UINT32_MAX 0xFFFFFFFF -+#define UINT32_MIN 0 -+#define UINT64_MAX 0xFFFFFFFFFFFFFFFFLL -+#define UINT64_MIN 0 -+#define INT8_MAX 0x7F -+#define INT8_MIN 0x80 -+#define INT16_MAX 0x7FFF -+#define INT16_MIN 0x8000 -+#define INT32_MAX 0x7FFFFFFF -+#define INT32_MIN 0x80000000 -+#define INT64_MAX 0x7FFFFFFFFFFFFFFFLL -+#define INT64_MIN 0x8000000000000000LL -+ -+#define ON 1 -+#define OFF 0 -+ -+#define FALSE false -+#define TRUE true -+ -+ -+/************************/ -+/* memory access macros */ -+/************************/ -+#ifdef CONFIG_FMAN_ARM -+#define in_be16(a) __be16_to_cpu(__raw_readw(a)) -+#define in_be32(a) __be32_to_cpu(__raw_readl(a)) -+#define out_be16(a, v) __raw_writew(__cpu_to_be16(v), a) -+#define out_be32(a, v) __raw_writel(__cpu_to_be32(v), a) -+#endif -+ -+#define GET_UINT8(arg) *(volatile uint8_t *)(&(arg)) -+#define GET_UINT16(arg) in_be16(&(arg))//*(volatile uint16_t*)(&(arg)) -+#define GET_UINT32(arg) in_be32(&(arg))//*(volatile uint32_t*)(&(arg)) -+#define GET_UINT64(arg) *(volatile uint64_t*)(&(arg)) -+ -+#ifdef VERBOSE_WRITE -+void XX_Print(char *str, ...); -+#define WRITE_UINT8(arg, data) \ -+ do { XX_Print("ADDR: 0x%08x, VAL: 0x%02x\r\n", (uint32_t)&(arg), (data)); *(volatile uint8_t *)(&(arg)) = (data); } while (0) -+#define WRITE_UINT16(arg, data) \ -+ do { XX_Print("ADDR: 0x%08x, VAL: 0x%04x\r\n", (uint32_t)&(arg), (data)); out_be16(&(arg), data); /* *(volatile uint16_t*)(&(arg)) = (data);*/ } while (0) -+#define WRITE_UINT32(arg, data) \ -+ do { XX_Print("ADDR: 0x%08x, VAL: 0x%08x\r\n", (uint32_t)&(arg), (data)); out_be32(&(arg), data); /* *(volatile uint32_t*)(&(arg)) = (data);*/ } while (0) -+#define WRITE_UINT64(arg, data) \ -+ do { XX_Print("ADDR: 0x%08x, VAL: 0x%016llx\r\n", (uint32_t)&(arg), (data)); *(volatile uint64_t*)(&(arg)) = (data); } while (0) -+ -+#else /* not VERBOSE_WRITE */ -+#define WRITE_UINT8(arg, data) *(volatile uint8_t *)(&(arg)) = (data) -+#define WRITE_UINT16(arg, data) out_be16(&(arg), data)//*(volatile uint16_t*)(&(arg)) = (data) -+#define WRITE_UINT32(arg, data) out_be32(&(arg), data)//*(volatile unsigned int *)(&(arg)) = (data) -+#define WRITE_UINT64(arg, data) *(volatile uint64_t*)(&(arg)) = (data) -+#endif /* not VERBOSE_WRITE */ -+ -+ -+/*****************************************************************************/ -+/* General stuff */ -+/*****************************************************************************/ -+#ifdef ARRAY_SIZE -+#undef ARRAY_SIZE -+#endif /* ARRAY_SIZE */ -+ -+#ifdef MAJOR -+#undef MAJOR -+#endif /* MAJOR */ -+ -+#ifdef MINOR -+#undef MINOR -+#endif /* MINOR */ -+ -+#ifdef QE_SIZEOF_BD -+#undef QE_SIZEOF_BD -+#endif /* QE_SIZEOF_BD */ -+ -+#ifdef BD_BUFFER_CLEAR -+#undef BD_BUFFER_CLEAR -+#endif /* BD_BUFFER_CLEAR */ -+ -+#ifdef BD_BUFFER -+#undef BD_BUFFER -+#endif /* BD_BUFFER */ -+ -+#ifdef BD_STATUS_AND_LENGTH_SET -+#undef BD_STATUS_AND_LENGTH_SET -+#endif /* BD_STATUS_AND_LENGTH_SET */ -+ -+#ifdef BD_STATUS_AND_LENGTH -+#undef BD_STATUS_AND_LENGTH -+#endif /* BD_STATUS_AND_LENGTH */ -+ -+#ifdef BD_BUFFER_ARG -+#undef BD_BUFFER_ARG -+#endif /* BD_BUFFER_ARG */ -+ -+#ifdef BD_GET_NEXT -+#undef BD_GET_NEXT -+#endif /* BD_GET_NEXT */ -+ -+#ifdef QE_SDEBCR_BA_MASK -+#undef QE_SDEBCR_BA_MASK -+#endif /* QE_SDEBCR_BA_MASK */ -+ -+#ifdef BD_BUFFER_SET -+#undef BD_BUFFER_SET -+#endif /* BD_BUFFER_SET */ -+ -+#ifdef UPGCR_PROTOCOL -+#undef UPGCR_PROTOCOL -+#endif /* UPGCR_PROTOCOL */ -+ -+#ifdef UPGCR_TMS -+#undef UPGCR_TMS -+#endif /* UPGCR_TMS */ -+ -+#ifdef UPGCR_RMS -+#undef UPGCR_RMS -+#endif /* UPGCR_RMS */ -+ -+#ifdef UPGCR_ADDR -+#undef UPGCR_ADDR -+#endif /* UPGCR_ADDR */ -+ -+#ifdef UPGCR_DIAG -+#undef UPGCR_DIAG -+#endif /* UPGCR_DIAG */ -+ -+#ifdef NCSW_PARAMS -+#undef NCSW_PARAMS -+#endif /* NCSW_PARAMS */ -+ -+#ifdef NO_IRQ -+#undef NO_IRQ -+#endif /* NO_IRQ */ -+ -+#define PRINT_LINE XX_Print("%s:\n %s [%d]\n",__FILE__,__FUNCTION__,__LINE__); -+ -+ -+#endif /* __TYPES_LINUX_H__ */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/fsl_fman_test.h -@@ -0,0 +1,84 @@ -+/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/****************************************************************************** -+ @File fsl_fman_test.h -+ -+ @Description -+*//***************************************************************************/ -+ -+#ifndef __FSL_FMAN_TEST_H -+#define __FSL_FMAN_TEST_H -+ -+#include -+#include /* raw_smp_processor_id() */ -+ -+//#define FMT_K_DBG -+//#define FMT_K_DBG_RUNTIME -+ -+#define _fmt_prk(stage, format, arg...) \ -+ printk(stage "fmt (cpu:%u): " format, raw_smp_processor_id(), ##arg) -+ -+#define _fmt_inf(format, arg...) _fmt_prk(KERN_INFO, format, ##arg) -+#define _fmt_wrn(format, arg...) _fmt_prk(KERN_WARNING, format, ##arg) -+#define _fmt_err(format, arg...) _fmt_prk(KERN_ERR, format, ##arg) -+ -+/* there are two macros for debugging: for runtime and generic. -+ * Helps when the runtime functions are not targeted for debugging, -+ * thus all the unnecessary information will be skipped. -+ */ -+/* used for generic debugging */ -+#if defined(FMT_K_DBG) -+ #define _fmt_dbg(format, arg...) \ -+ printk("fmt [%s:%u](cpu:%u) - " format, \ -+ __func__, __LINE__, raw_smp_processor_id(), ##arg) -+#else -+# define _fmt_dbg(arg...) -+#endif -+ -+/* used for debugging runtime functions */ -+#if defined(FMT_K_DBG_RUNTIME) -+ #define _fmt_dbgr(format, arg...) \ -+ printk("fmt [%s:%u](cpu:%u) - " format, \ -+ __func__, __LINE__, raw_smp_processor_id(), ##arg) -+#else -+# define _fmt_dbgr(arg...) -+#endif -+ -+#define FMT_RX_ERR_Q 0xffffffff -+#define FMT_RX_DFLT_Q 0xfffffffe -+#define FMT_TX_ERR_Q 0xfffffffd -+#define FMT_TX_CONF_Q 0xfffffffc -+ -+#define FMAN_TEST_MAX_TX_FQS 8 -+ -+#endif /* __FSL_FMAN_TEST_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/lnxwrp_exp_sym.h -@@ -0,0 +1,127 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ @File lnxwrp_exp_sym.h -+ @Description FMan exported routines -+*/ -+ -+#ifndef __LNXWRP_EXP_SYM_H -+#define __LNXWRP_EXP_SYM_H -+ -+#include "fm_port_ext.h" -+#include "fm_pcd_ext.h" -+#include "fm_mac_ext.h" -+ -+ -+/* FMAN Port exported routines */ -+EXPORT_SYMBOL(FM_PORT_Disable); -+EXPORT_SYMBOL(FM_PORT_Enable); -+EXPORT_SYMBOL(FM_PORT_SetPCD); -+ -+/* Runtime PCD exported routines */ -+EXPORT_SYMBOL(FM_PCD_Enable); -+EXPORT_SYMBOL(FM_PCD_Disable); -+EXPORT_SYMBOL(FM_PCD_GetCounter); -+EXPORT_SYMBOL(FM_PCD_PrsLoadSw); -+EXPORT_SYMBOL(FM_PCD_KgSetDfltValue); -+EXPORT_SYMBOL(FM_PCD_KgSetAdditionalDataAfterParsing); -+EXPORT_SYMBOL(FM_PCD_SetException); -+EXPORT_SYMBOL(FM_PCD_ModifyCounter); -+EXPORT_SYMBOL(FM_PCD_SetPlcrStatistics); -+EXPORT_SYMBOL(FM_PCD_SetPrsStatistics); -+EXPORT_SYMBOL(FM_PCD_ForceIntr); -+EXPORT_SYMBOL(FM_PCD_HcTxConf); -+ -+EXPORT_SYMBOL(FM_PCD_NetEnvCharacteristicsSet); -+EXPORT_SYMBOL(FM_PCD_NetEnvCharacteristicsDelete); -+EXPORT_SYMBOL(FM_PCD_KgSchemeSet); -+EXPORT_SYMBOL(FM_PCD_KgSchemeDelete); -+EXPORT_SYMBOL(FM_PCD_KgSchemeGetCounter); -+EXPORT_SYMBOL(FM_PCD_KgSchemeSetCounter); -+EXPORT_SYMBOL(FM_PCD_CcRootBuild); -+EXPORT_SYMBOL(FM_PCD_CcRootDelete); -+EXPORT_SYMBOL(FM_PCD_MatchTableSet); -+EXPORT_SYMBOL(FM_PCD_MatchTableDelete); -+EXPORT_SYMBOL(FM_PCD_CcRootModifyNextEngine); -+EXPORT_SYMBOL(FM_PCD_MatchTableModifyNextEngine); -+EXPORT_SYMBOL(FM_PCD_MatchTableFindNModifyNextEngine); -+EXPORT_SYMBOL(FM_PCD_MatchTableModifyMissNextEngine); -+EXPORT_SYMBOL(FM_PCD_MatchTableRemoveKey); -+EXPORT_SYMBOL(FM_PCD_MatchTableFindNRemoveKey); -+EXPORT_SYMBOL(FM_PCD_MatchTableAddKey); -+EXPORT_SYMBOL(FM_PCD_MatchTableModifyKeyAndNextEngine); -+EXPORT_SYMBOL(FM_PCD_MatchTableFindNModifyKeyAndNextEngine); -+EXPORT_SYMBOL(FM_PCD_MatchTableModifyKey); -+EXPORT_SYMBOL(FM_PCD_MatchTableFindNModifyKey); -+EXPORT_SYMBOL(FM_PCD_MatchTableGetIndexedHashBucket); -+EXPORT_SYMBOL(FM_PCD_MatchTableGetNextEngine); -+EXPORT_SYMBOL(FM_PCD_MatchTableGetKeyCounter); -+EXPORT_SYMBOL(FM_PCD_MatchTableGetKeyStatistics); -+EXPORT_SYMBOL(FM_PCD_MatchTableFindNGetKeyStatistics); -+EXPORT_SYMBOL(FM_PCD_MatchTableGetMissStatistics); -+EXPORT_SYMBOL(FM_PCD_HashTableGetMissStatistics); -+EXPORT_SYMBOL(FM_PCD_HashTableSet); -+EXPORT_SYMBOL(FM_PCD_HashTableDelete); -+EXPORT_SYMBOL(FM_PCD_HashTableAddKey); -+EXPORT_SYMBOL(FM_PCD_HashTableRemoveKey); -+EXPORT_SYMBOL(FM_PCD_HashTableModifyNextEngine); -+EXPORT_SYMBOL(FM_PCD_HashTableModifyMissNextEngine); -+EXPORT_SYMBOL(FM_PCD_HashTableGetMissNextEngine); -+EXPORT_SYMBOL(FM_PCD_HashTableFindNGetKeyStatistics); -+EXPORT_SYMBOL(FM_PCD_PlcrProfileSet); -+EXPORT_SYMBOL(FM_PCD_PlcrProfileDelete); -+EXPORT_SYMBOL(FM_PCD_PlcrProfileGetCounter); -+EXPORT_SYMBOL(FM_PCD_PlcrProfileSetCounter); -+EXPORT_SYMBOL(FM_PCD_ManipNodeSet); -+EXPORT_SYMBOL(FM_PCD_ManipNodeDelete); -+EXPORT_SYMBOL(FM_PCD_ManipGetStatistics); -+EXPORT_SYMBOL(FM_PCD_ManipNodeReplace); -+#if (DPAA_VERSION >= 11) -+EXPORT_SYMBOL(FM_PCD_FrmReplicSetGroup); -+EXPORT_SYMBOL(FM_PCD_FrmReplicDeleteGroup); -+EXPORT_SYMBOL(FM_PCD_FrmReplicAddMember); -+EXPORT_SYMBOL(FM_PCD_FrmReplicRemoveMember); -+#endif /* DPAA_VERSION >= 11 */ -+ -+#ifdef FM_CAPWAP_SUPPORT -+EXPORT_SYMBOL(FM_PCD_StatisticsSetNode); -+#endif /* FM_CAPWAP_SUPPORT */ -+ -+EXPORT_SYMBOL(FM_PCD_SetAdvancedOffloadSupport); -+ -+/* FMAN MAC exported routines */ -+EXPORT_SYMBOL(FM_MAC_GetStatistics); -+ -+EXPORT_SYMBOL(FM_GetSpecialOperationCoding); -+ -+#endif /* __LNXWRP_EXP_SYM_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/lnxwrp_fm_ext.h -@@ -0,0 +1,163 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/****************************************************************************** -+ @File lnxwrp_fm_ext.h -+ -+ @Description TODO -+*//***************************************************************************/ -+ -+#ifndef __LNXWRP_FM_EXT_H -+#define __LNXWRP_FM_EXT_H -+ -+#include "std_ext.h" -+#include "sys_ext.h" -+#include "fm_ext.h" -+#include "fm_muram_ext.h" -+#include "fm_pcd_ext.h" -+#include "fm_port_ext.h" -+#include "fm_mac_ext.h" -+#include "fm_rtc_ext.h" -+ -+ -+/**************************************************************************//** -+ @Group FM_LnxKern_grp Frame Manager Linux wrapper API -+ -+ @Description FM API functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group FM_LnxKern_init_grp Initialization Unit -+ -+ @Description Initialization Unit -+ -+ Initialization Flow: -+ Initialization of the FM Module will be carried out by the Linux -+ kernel according to the following sequence: -+ a. Calling the initialization routine with no parameters. -+ b. The driver will register to the Device-Tree. -+ c. The Linux Device-Tree will initiate a call to the driver for -+ initialization. -+ d. The driver will read the appropriate information from the Device-Tree -+ e. [Optional] Calling the advance initialization routines to change -+ driver's defaults. -+ f. Initialization of the device will be automatically upon using it. -+ -+ @{ -+*//***************************************************************************/ -+ -+typedef struct t_WrpFmDevSettings -+{ -+ t_FmParams param; -+ t_SysObjectAdvConfigEntry *advConfig; -+} t_WrpFmDevSettings; -+ -+typedef struct t_WrpFmPcdDevSettings -+{ -+ t_FmPcdParams param; -+ t_SysObjectAdvConfigEntry *advConfig; -+} t_WrpFmPcdDevSettings; -+ -+typedef struct t_WrpFmPortDevSettings -+{ -+ bool frag_enabled; -+ t_FmPortParams param; -+ t_SysObjectAdvConfigEntry *advConfig; -+} t_WrpFmPortDevSettings; -+ -+typedef struct t_WrpFmMacDevSettings -+{ -+ t_FmMacParams param; -+ t_SysObjectAdvConfigEntry *advConfig; -+} t_WrpFmMacDevSettings; -+ -+ -+/**************************************************************************//** -+ @Function LNXWRP_FM_Init -+ -+ @Description Initialize the FM linux wrapper. -+ -+ @Return A handle (descriptor) of the newly created FM Linux wrapper -+ structure. -+*//***************************************************************************/ -+t_Handle LNXWRP_FM_Init(void); -+ -+/**************************************************************************//** -+ @Function LNXWRP_FM_Free -+ -+ @Description Free the FM linux wrapper. -+ -+ @Param[in] h_LnxWrpFm - A handle to the FM linux wrapper. -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+t_Error LNXWRP_FM_Free(t_Handle h_LnxWrpFm); -+ -+/**************************************************************************//** -+ @Function LNXWRP_FM_GetMacHandle -+ -+ @Description Get the FM-MAC LLD handle from the FM linux wrapper. -+ -+ @Param[in] h_LnxWrpFm - A handle to the FM linux wrapper. -+ @Param[in] fmId - Index of the FM device to get the MAC handle from. -+ @Param[in] macId - Index of the mac handle. -+ -+ @Return A handle of the LLD compressor. -+*//***************************************************************************/ -+t_Handle LNXWRP_FM_GetMacHandle(t_Handle h_LnxWrpFm, uint8_t fmId, uint8_t macId); -+ -+#ifdef CONFIG_FSL_SDK_FMAN_TEST -+t_Handle LNXWRP_FM_TEST_Init(void); -+t_Error LNXWRP_FM_TEST_Free(t_Handle h_FmTestLnxWrp); -+#endif /* CONFIG_FSL_SDK_FMAN_TEST */ -+ -+/** @} */ /* end of FM_LnxKern_init_grp group */ -+ -+ -+/**************************************************************************//** -+ @Group FM_LnxKern_ctrl_grp Control Unit -+ -+ @Description Control Unit -+ -+ TODO -+ @{ -+*//***************************************************************************/ -+ -+#include "lnxwrp_fsl_fman.h" -+ -+/** @} */ /* end of FM_LnxKern_ctrl_grp group */ -+/** @} */ /* end of FM_LnxKern_grp group */ -+ -+ -+#endif /* __LNXWRP_FM_EXT_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/lnxwrp_fsl_fman.h -@@ -0,0 +1,919 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/****************************************************************************** -+ @File lnxwrp_fsl_fman.h -+ -+ @Description Linux internal kernel API -+*//***************************************************************************/ -+ -+#ifndef __LNXWRP_FSL_FMAN_H -+#define __LNXWRP_FSL_FMAN_H -+ -+#include -+#include /* struct device */ -+#include /* struct qman_fq */ -+#include "dpaa_integration_ext.h" -+#include "fm_port_ext.h" -+#include "fm_mac_ext.h" -+#include "fm_macsec_ext.h" -+#include "fm_rtc_ext.h" -+ -+/**************************************************************************//** -+ @Group FM_LnxKern_grp Frame Manager Linux wrapper API -+ -+ @Description FM API functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group FM_LnxKern_ctrl_grp Control Unit -+ -+ @Description Control Unit -+ -+ Internal Kernel Control Unit API -+ @{ -+*//***************************************************************************/ -+ -+/*****************************************************************************/ -+/* Internal Linux kernel routines */ -+/*****************************************************************************/ -+ -+/**************************************************************************//** -+ @Description MACSEC Exceptions wrapper -+*//***************************************************************************/ -+typedef enum fm_macsec_exception { -+ SINGLE_BIT_ECC = e_FM_MACSEC_EX_SINGLE_BIT_ECC, -+ MULTI_BIT_ECC = e_FM_MACSEC_EX_MULTI_BIT_ECC -+} fm_macsec_exception; -+ -+/**************************************************************************//** -+ @Description Unknown sci frame treatment wrapper -+*//***************************************************************************/ -+typedef enum fm_macsec_unknown_sci_frame_treatment { -+ SCI_DISCARD_BOTH = e_FM_MACSEC_UNKNOWN_SCI_FRAME_TREATMENT_DISCARD_BOTH, -+ SCI_DISCARD_UNCTRL_DELIVER_DISCARD_CTRL = \ -+ e_FM_MACSEC_UNKNOWN_SCI_FRAME_TREATMENT_DISCARD_UNCONTROLLED_DELIVER_OR_DISCARD_CONTROLLED, -+ SCI_DELIVER_UNCTRL_DISCARD_CTRL = \ -+ e_FM_MACSEC_UNKNOWN_SCI_FRAME_TREATMENT_DELIVER_UNCONTROLLED_DISCARD_CONTROLLED, -+ SCI_DELIVER_DISCARD_UNCTRL_DELIVER_DISCARD_CTRL = \ -+ e_FM_MACSEC_UNKNOWN_SCI_FRAME_TREATMENT_DELIVER_OR_DISCARD_UNCONTROLLED_DELIVER_OR_DISCARD_CONTROLLED -+} fm_macsec_unknown_sci_frame_treatment; -+ -+/**************************************************************************//** -+ @Description Untag frame treatment wrapper -+*//***************************************************************************/ -+typedef enum fm_macsec_untag_frame_treatment { -+ UNTAG_DELIVER_UNCTRL_DISCARD_CTRL = \ -+ e_FM_MACSEC_UNTAG_FRAME_TREATMENT_DELIVER_UNCONTROLLED_DISCARD_CONTROLLED, -+ UNTAG_DISCARD_BOTH = e_FM_MACSEC_UNTAG_FRAME_TREATMENT_DISCARD_BOTH, -+ UNTAG_DISCARD_UNCTRL_DELIVER_CTRL_UNMODIFIED = \ -+ e_FM_MACSEC_UNTAG_FRAME_TREATMENT_DISCARD_UNCONTROLLED_DELIVER_CONTROLLED_UNMODIFIED -+} fm_macsec_untag_frame_treatment; -+ -+/**************************************************************************//** -+@Description MACSEC SECY Cipher Suite wrapper -+*//***************************************************************************/ -+typedef enum fm_macsec_secy_cipher_suite { -+ SECY_GCM_AES_128 = e_FM_MACSEC_SECY_GCM_AES_128, /**< GCM-AES-128 */ -+#if (DPAA_VERSION >= 11) -+ SECY_GCM_AES_256 = e_FM_MACSEC_SECY_GCM_AES_256 /**< GCM-AES-256 */ -+#endif /* (DPAA_VERSION >= 11) */ -+} fm_macsec_secy_cipher_suite; -+ -+/**************************************************************************//** -+ @Description MACSEC SECY Exceptions wrapper -+*//***************************************************************************/ -+typedef enum fm_macsec_secy_exception { -+ SECY_EX_FRAME_DISCARDED = e_FM_MACSEC_SECY_EX_FRAME_DISCARDED -+} fm_macsec_secy_exception; -+ -+/**************************************************************************//** -+ @Description MACSEC SECY Events wrapper -+*//***************************************************************************/ -+typedef enum fm_macsec_secy_event { -+ SECY_EV_NEXT_PN = e_FM_MACSEC_SECY_EV_NEXT_PN -+} fm_macsec_secy_event; -+ -+/**************************************************************************//** -+ @Description Valid frame behaviors wrapper -+*//***************************************************************************/ -+typedef enum fm_macsec_valid_frame_behavior { -+ VALID_FRAME_BEHAVIOR_DISABLE = e_FM_MACSEC_VALID_FRAME_BEHAVIOR_DISABLE, -+ VALID_FRAME_BEHAVIOR_CHECK = e_FM_MACSEC_VALID_FRAME_BEHAVIOR_CHECK, -+ VALID_FRAME_BEHAVIOR_STRICT = e_FM_MACSEC_VALID_FRAME_BEHAVIOR_STRICT -+} fm_macsec_valid_frame_behavior; -+ -+/**************************************************************************//** -+ @Description SCI insertion modes wrapper -+*//***************************************************************************/ -+typedef enum fm_macsec_sci_insertion_mode { -+ SCI_INSERTION_MODE_EXPLICIT_SECTAG = \ -+ e_FM_MACSEC_SCI_INSERTION_MODE_EXPLICIT_SECTAG, -+ SCI_INSERTION_MODE_EXPLICIT_MAC_SA = \ -+ e_FM_MACSEC_SCI_INSERTION_MODE_EXPLICIT_MAC_SA, -+ SCI_INSERTION_MODE_IMPLICT_PTP = e_FM_MACSEC_SCI_INSERTION_MODE_IMPLICT_PTP -+} fm_macsec_sci_insertion_mode; -+ -+typedef macsecSAKey_t macsec_sa_key_t; -+typedef macsecSCI_t macsec_sci_t; -+typedef macsecAN_t macsec_an_t; -+typedef t_Handle handle_t; -+ -+/**************************************************************************//** -+ @Function fm_macsec_secy_exception_callback wrapper -+ @Description Exceptions user callback routine, will be called upon an -+ exception passing the exception identification. -+ @Param[in] app_h A handle to an application layer object; This handle -+ will be passed by the driver upon calling this callback. -+ @Param[in] exception The exception. -+*//***************************************************************************/ -+typedef void (fm_macsec_secy_exception_callback) (handle_t app_h, -+ fm_macsec_secy_exception exception); -+ -+/**************************************************************************//** -+ @Function fm_macsec_secy_event_callback wrapper -+ @Description Events user callback routine, will be called upon an -+ event passing the event identification. -+ @Param[in] app_h A handle to an application layer object; This handle -+ will be passed by the driver upon calling this callback. -+ @Param[in] event The event. -+*//***************************************************************************/ -+typedef void (fm_macsec_secy_event_callback) (handle_t app_h, -+ fm_macsec_secy_event event); -+ -+/**************************************************************************//** -+ @Function fm_macsec_exception_callback wrapper -+ @Description Exceptions user callback routine, will be called upon an -+ exception passing the exception identification. -+ @Param[in] app_h A handle to an application layer object; This handle -+ will be passed by the driver upon calling this callback. -+ @Param[in] exception The exception. -+*//***************************************************************************/ -+typedef void (fm_macsec_exception_callback) (handle_t app_h, -+ fm_macsec_exception exception); -+ -+/**************************************************************************//** -+ @Description MACSEC SecY SC Params wrapper -+*//***************************************************************************/ -+struct fm_macsec_secy_sc_params { -+ macsec_sci_t sci; -+ fm_macsec_secy_cipher_suite cipher_suite; -+}; -+ -+/**************************************************************************//** -+ @Description FM MACSEC SecY config input wrapper -+*//***************************************************************************/ -+struct fm_macsec_secy_params { -+ handle_t fm_macsec_h; -+ struct fm_macsec_secy_sc_params tx_sc_params; -+ uint32_t num_receive_channels; -+ fm_macsec_secy_exception_callback *exception_f; -+ fm_macsec_secy_event_callback *event_f; -+ handle_t app_h; -+}; -+ -+/**************************************************************************//** -+ @Description FM MACSEC config input wrapper -+*//***************************************************************************/ -+struct fm_macsec_params { -+ handle_t fm_h; -+ bool guest_mode; -+ -+ union { -+ struct { -+ uint8_t fm_mac_id; -+ } guest_params; -+ -+ struct { -+ uintptr_t base_addr; -+ handle_t fm_mac_h; -+ fm_macsec_exception_callback *exception_f; -+ handle_t app_h; -+ } non_guest_params; -+ }; -+ -+}; -+ -+/**************************************************************************//** -+ @Description FM device opaque structure used for type checking -+*//***************************************************************************/ -+struct fm; -+ -+/**************************************************************************//** -+ @Description FM MAC device opaque structure used for type checking -+*//***************************************************************************/ -+struct fm_mac_dev; -+ -+/**************************************************************************//** -+ @Description FM MACSEC device opaque structure used for type checking -+*//***************************************************************************/ -+struct fm_macsec_dev; -+struct fm_macsec_secy_dev; -+ -+/**************************************************************************//** -+ @Description A structure .., -+*//***************************************************************************/ -+struct fm_port; -+ -+typedef int (*alloc_pcd_fqids)(struct device *dev, uint32_t num, -+ uint8_t alignment, uint32_t *base_fqid); -+ -+typedef int (*free_pcd_fqids)(struct device *dev, uint32_t base_fqid); -+ -+struct fm_port_pcd_param { -+ alloc_pcd_fqids cba; -+ free_pcd_fqids cbf; -+ struct device *dev; -+}; -+ -+/**************************************************************************//** -+ @Description A structure of information about each of the external -+ buffer pools used by the port, -+*//***************************************************************************/ -+struct fm_port_pool_param { -+ uint8_t id; /**< External buffer pool id */ -+ uint16_t size; /**< External buffer pool buffer size */ -+}; -+ -+/**************************************************************************//** -+ @Description structure for additional port parameters -+*//***************************************************************************/ -+struct fm_port_params { -+ uint32_t errq; /**< Error Queue Id. */ -+ uint32_t defq; /**< For Tx and HC - Default Confirmation queue, -+ 0 means no Tx conf for processed frames. -+ For Rx and OP - default Rx queue. */ -+ uint8_t num_pools; /**< Number of pools use by this port */ -+ struct fm_port_pool_param pool_param[FM_PORT_MAX_NUM_OF_EXT_POOLS]; -+ /**< Parameters for each pool */ -+ uint16_t priv_data_size; /**< Area that user may save for his own -+ need (E.g. save the SKB) */ -+ bool parse_results; /**< Put the parser-results in the Rx/Tx buffer */ -+ bool hash_results; /**< Put the hash-results in the Rx/Tx buffer */ -+ bool time_stamp; /**< Put the time-stamp in the Rx/Tx buffer */ -+ bool frag_enable; /**< Fragmentation support, for OP only */ -+ uint16_t data_align; /**< value for selecting a data alignment (must be a power of 2); -+ if write optimization is used, must be >= 16. */ -+ uint8_t manip_extra_space; /**< Maximum extra size needed (insertion-size minus removal-size); -+ Note that this field impacts the size of the buffer-prefix -+ (i.e. it pushes the data offset); */ -+}; -+ -+/**************************************************************************//** -+ @Function fm_bind -+ -+ @Description Bind to a specific FM device. -+ -+ @Param[in] fm_dev - the OF handle of the FM device. -+ -+ @Return A handle of the FM device. -+ -+ @Cautions Allowed only after the port was created. -+*//***************************************************************************/ -+struct fm *fm_bind(struct device *fm_dev); -+ -+/**************************************************************************//** -+ @Function fm_unbind -+ -+ @Description Un-bind from a specific FM device. -+ -+ @Param[in] fm - A handle of the FM device. -+ -+ @Cautions Allowed only after the port was created. -+*//***************************************************************************/ -+void fm_unbind(struct fm *fm); -+ -+void *fm_get_handle(struct fm *fm); -+void *fm_get_rtc_handle(struct fm *fm); -+struct resource *fm_get_mem_region(struct fm *fm); -+ -+/**************************************************************************//** -+ @Function fm_port_bind -+ -+ @Description Bind to a specific FM-port device (may be Rx or Tx port). -+ -+ @Param[in] fm_port_dev - the OF handle of the FM port device. -+ -+ @Return A handle of the FM port device. -+ -+ @Cautions Allowed only after the port was created. -+*//***************************************************************************/ -+struct fm_port *fm_port_bind(struct device *fm_port_dev); -+ -+/**************************************************************************//** -+ @Function fm_port_unbind -+ -+ @Description Un-bind from a specific FM-port device (may be Rx or Tx port). -+ -+ @Param[in] port - A handle of the FM port device. -+ -+ @Cautions Allowed only after the port was created. -+*//***************************************************************************/ -+void fm_port_unbind(struct fm_port *port); -+ -+/**************************************************************************//** -+ @Function fm_set_rx_port_params -+ -+ @Description Configure parameters for a specific Rx FM-port device. -+ -+ @Param[in] port - A handle of the FM port device. -+ @Param[in] params - Rx port parameters -+ -+ @Cautions Allowed only after the port is binded. -+*//***************************************************************************/ -+void fm_set_rx_port_params(struct fm_port *port, -+ struct fm_port_params *params); -+ -+/**************************************************************************//** -+ @Function fm_port_pcd_bind -+ -+ @Description Bind as a listener on a port PCD. -+ -+ @Param[in] port - A handle of the FM port device. -+ @Param[in] params - PCD port parameters -+ -+ @Cautions Allowed only after the port is binded. -+*//***************************************************************************/ -+void fm_port_pcd_bind (struct fm_port *port, struct fm_port_pcd_param *params); -+ -+/**************************************************************************//** -+ @Function fm_port_get_buff_layout_ext_params -+ -+ @Description Get data_align and manip_extra_space from the device tree -+ chosen node if applied. -+ This function will only update these two parameters. -+ When this port has no such parameters in the device tree -+ values will be set to 0. -+ -+ @Param[in] port - A handle of the FM port device. -+ @Param[in] params - PCD port parameters -+ -+ @Cautions Allowed only after the port is binded. -+*//***************************************************************************/ -+void fm_port_get_buff_layout_ext_params(struct fm_port *port, struct fm_port_params *params); -+ -+/**************************************************************************//** -+ @Function fm_get_tx_port_channel -+ -+ @Description Get qman-channel number for this Tx port. -+ -+ @Param[in] port - A handle of the FM port device. -+ -+ @Return qman-channel number for this Tx port. -+ -+ @Cautions Allowed only after the port is binded. -+*//***************************************************************************/ -+uint16_t fm_get_tx_port_channel(struct fm_port *port); -+ -+/**************************************************************************//** -+ @Function fm_set_tx_port_params -+ -+ @Description Configure parameters for a specific Tx FM-port device -+ -+ @Param[in] port - A handle of the FM port device. -+ @Param[in] params - Tx port parameters -+ -+ @Cautions Allowed only after the port is binded. -+*//***************************************************************************/ -+void fm_set_tx_port_params(struct fm_port *port, struct fm_port_params *params); -+ -+ -+/**************************************************************************//** -+ @Function fm_mac_set_handle -+ -+ @Description Set mac handle -+ -+ @Param[in] h_lnx_wrp_fm_dev - A handle of the LnxWrp FM device. -+ @Param[in] h_fm_mac - A handle of the LnxWrp FM MAC device. -+ @Param[in] mac_id - MAC id. -+*//***************************************************************************/ -+void fm_mac_set_handle(t_Handle h_lnx_wrp_fm_dev, t_Handle h_fm_mac, -+ int mac_id); -+ -+/**************************************************************************//** -+ @Function fm_port_enable -+ -+ @Description Enable specific FM-port device (may be Rx or Tx port). -+ -+ @Param[in] port - A handle of the FM port device. -+ -+ @Cautions Allowed only after the port is initialized. -+*//***************************************************************************/ -+int fm_port_enable(struct fm_port *port); -+ -+/**************************************************************************//** -+ @Function fm_port_disable -+ -+ @Description Disable specific FM-port device (may be Rx or Tx port). -+ -+ @Param[in] port - A handle of the FM port device. -+ -+ @Cautions Allowed only after the port is initialized. -+*//***************************************************************************/ -+int fm_port_disable(struct fm_port *port); -+ -+void *fm_port_get_handle(const struct fm_port *port); -+ -+u64 *fm_port_get_buffer_time_stamp(const struct fm_port *port, -+ const void *data); -+ -+/**************************************************************************//** -+ @Function fm_port_get_base_address -+ -+ @Description Get base address of this port. Useful for accessing -+ port-specific registers (i.e., not common ones). -+ -+ @Param[in] port - A handle of the FM port device. -+ -+ @Param[out] base_addr - The port's base addr (virtual address). -+*//***************************************************************************/ -+void fm_port_get_base_addr(const struct fm_port *port, uint64_t *base_addr); -+ -+/**************************************************************************//** -+ @Function fm_mutex_lock -+ -+ @Description Lock function required before any FMD/LLD call. -+*//***************************************************************************/ -+void fm_mutex_lock(void); -+ -+/**************************************************************************//** -+ @Function fm_mutex_unlock -+ -+ @Description Unlock function required after any FMD/LLD call. -+*//***************************************************************************/ -+void fm_mutex_unlock(void); -+ -+/**************************************************************************//** -+ @Function fm_get_max_frm -+ -+ @Description Get the maximum frame size -+*//***************************************************************************/ -+int fm_get_max_frm(void); -+ -+/**************************************************************************//** -+ @Function fm_get_rx_extra_headroom -+ -+ @Description Get the extra headroom size -+*//***************************************************************************/ -+int fm_get_rx_extra_headroom(void); -+ -+/**************************************************************************//** -+@Function fm_port_set_rate_limit -+ -+@Description Configure Shaper parameter on FM-port device (Tx port). -+ -+@Param[in] port - A handle of the FM port device. -+@Param[in] max_burst_size - Value of maximum burst size allowed. -+@Param[in] rate_limit - The required rate value. -+ -+@Cautions Allowed only after the port is initialized. -+*//***************************************************************************/ -+int fm_port_set_rate_limit(struct fm_port *port, -+ uint16_t max_burst_size, -+ uint32_t rate_limit); -+/**************************************************************************//** -+@Function fm_port_set_rate_limit -+ -+@Description Delete Shaper configuration on FM-port device (Tx port). -+ -+@Param[in] port - A handle of the FM port device. -+ -+@Cautions Allowed only after the port is initialized. -+*//***************************************************************************/ -+int fm_port_del_rate_limit(struct fm_port *port); -+ -+struct auto_res_tables_sizes -+{ -+ uint16_t max_num_of_arp_entries; -+ uint16_t max_num_of_echo_ipv4_entries; -+ uint16_t max_num_of_ndp_entries; -+ uint16_t max_num_of_echo_ipv6_entries; -+ uint16_t max_num_of_snmp_ipv4_entries; -+ uint16_t max_num_of_snmp_ipv6_entries; -+ uint16_t max_num_of_snmp_oid_entries; -+ uint16_t max_num_of_snmp_char; /* total amount of character needed -+ for the snmp table */ -+ uint16_t max_num_of_ip_prot_filtering; -+ uint16_t max_num_of_tcp_port_filtering; -+ uint16_t max_num_of_udp_port_filtering; -+}; -+/* ARP */ -+struct auto_res_arp_entry -+{ -+ uint32_t ip_address; -+ uint8_t mac[6]; -+ bool is_vlan; -+ uint16_t vid; -+}; -+struct auto_res_arp_info -+{ -+ uint8_t table_size; -+ struct auto_res_arp_entry *auto_res_table; -+ bool enable_conflict_detection; /* when TRUE -+ Conflict Detection will be checked and wake the host if -+ needed */ -+}; -+ -+/* NDP */ -+struct auto_res_ndp_entry -+{ -+ uint32_t ip_address[4]; -+ uint8_t mac[6]; -+ bool is_vlan; -+ uint16_t vid; -+}; -+struct auto_res_ndp_info -+{ -+ uint32_t multicast_group; -+ uint8_t table_size_assigned; -+ struct auto_res_ndp_entry *auto_res_table_assigned; /* This list -+ refer to solicitation IP addresses. Note that all IP adresses -+ must be from the same multicast group. This will be checked and -+ if not operation will fail. */ -+ uint8_t table_size_tmp; -+ struct auto_res_ndp_entry *auto_res_table_tmp; /* This list -+ refer to temp IP addresses. Note that all temp IP adresses must -+ be from the same multicast group. This will be checked and if -+ not operation will fail. */ -+ -+ bool enable_conflict_detection; /* when TRUE -+ Conflict Detection will be checked and wake the host if -+ needed */ -+}; -+ -+/* ICMP ECHO */ -+struct auto_res_echo_ipv4_info -+{ -+ uint8_t table_size; -+ struct auto_res_arp_entry *auto_res_table; -+}; -+ -+struct auto_res_echo_ipv6_info -+{ -+ uint8_t table_size; -+ struct auto_res_ndp_entry *auto_res_table; -+}; -+ -+/* SNMP */ -+struct auto_res_snmp_entry -+{ -+ uint16_t oidSize; -+ uint8_t *oidVal; /* only the oid string */ -+ uint16_t resSize; -+ uint8_t *resVal; /* resVal will be the entire reply, -+ i.e. "Type|Length|Value" */ -+}; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response SNMP IPv4 Addresses Table Entry -+ Refer to the FMan Controller spec for more details. -+*//***************************************************************************/ -+struct auto_res_snmp_ipv4addr_tbl_entry -+{ -+ uint32_t ipv4addr; /*!< 32 bit IPv4 Address. */ -+ bool is_vlan; -+ uint16_t vid; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */ -+ /*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */ -+}; -+ -+/**************************************************************************//** -+ @Description Deep Sleep Auto Response SNMP IPv6 Addresses Table Entry -+ Refer to the FMan Controller spec for more details. -+*//***************************************************************************/ -+struct auto_res_snmp_ipv6addr_tbl_entry -+{ -+ uint32_t ipv6Addr[4]; /*!< 4 * 32 bit IPv6 Address. */ -+ bool isVlan; -+ uint16_t vid; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */ -+ /*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */ -+}; -+ -+struct auto_res_snmp_info -+{ -+ uint16_t control; /**< Control bits [0-15]. */ -+ uint16_t max_snmp_msg_length; /**< Maximal allowed SNMP message length. */ -+ uint16_t num_ipv4_addresses; /**< Number of entries in IPv4 addresses table. */ -+ uint16_t num_ipv6_addresses; /**< Number of entries in IPv6 addresses table. */ -+ struct auto_res_snmp_ipv4addr_tbl_entry *ipv4addr_tbl; /**< Pointer to IPv4 addresses table. */ -+ struct auto_res_snmp_ipv6addr_tbl_entry *ipv6addr_tbl; /**< Pointer to IPv6 addresses table. */ -+ char *community_read_write_string; -+ char *community_read_only_string; -+ struct auto_res_snmp_entry *oid_table; -+ uint32_t oid_table_size; -+ uint32_t *statistics; -+}; -+ -+/* Filtering */ -+struct auto_res_port_filtering_entry -+{ -+ uint16_t src_port; -+ uint16_t dst_port; -+ uint16_t src_port_mask; -+ uint16_t dst_port_mask; -+}; -+struct auto_res_filtering_info -+{ -+ /* IP protocol filtering parameters */ -+ uint8_t ip_prot_table_size; -+ uint8_t *ip_prot_table_ptr; -+ bool ip_prot_pass_on_hit; /* when TRUE, miss in the table will -+ cause the packet to be droped, hit will pass the packet to -+ UDP/TCP filters if needed and if not to the classification -+ tree. If the classification tree will pass the packet to a -+ queue it will cause a wake interupt. When FALSE it the other -+ way around. */ -+ /* UDP port filtering parameters */ -+ uint8_t udp_ports_table_size; -+ struct auto_res_port_filtering_entry *udp_ports_table_ptr; -+ bool udp_port_pass_on_hit; /* when TRUE, miss in the table will -+ cause the packet to be droped, hit will pass the packet to -+ classification tree. If the classification tree will pass the -+ packet to a queue it will cause a wake interupt. When FALSE it -+ the other way around. */ -+ /* TCP port filtering parameters */ -+ uint16_t tcp_flags_mask; -+ uint8_t tcp_ports_table_size; -+ struct auto_res_port_filtering_entry *tcp_ports_table_ptr; -+ bool tcp_port_pass_on_hit; /* when TRUE, miss in the table will -+ cause the packet to be droped, hit will pass the packet to -+ classification tree. If the classification tree will pass the -+ packet to a queue it will cause a wake interupt. When FALSE it -+ the other way around. */ -+}; -+ -+struct auto_res_port_params -+{ -+ t_Handle h_FmPortTx; -+ struct auto_res_arp_info *p_auto_res_arp_info; -+ struct auto_res_echo_ipv4_info *p_auto_res_echo_ipv4_info; -+ struct auto_res_ndp_info *p_auto_res_ndp_info; -+ struct auto_res_echo_ipv6_info *p_auto_res_echo_ipv6_info; -+ struct auto_res_snmp_info *p_auto_res_snmp_info; -+ struct auto_res_filtering_info *p_auto_res_filtering_info; -+}; -+ -+struct auto_res_port_stats -+{ -+ uint32_t arp_ar_cnt; -+ uint32_t echo_icmpv4_ar_cnt; -+ uint32_t ndp_ar_cnt; -+ uint32_t echo_icmpv6_ar_cnt; -+}; -+ -+int fm_port_config_autores_for_deepsleep_support(struct fm_port *port, -+ struct auto_res_tables_sizes *params); -+ -+int fm_port_enter_autores_for_deepsleep(struct fm_port *port, -+ struct auto_res_port_params *params); -+ -+void fm_port_exit_auto_res_for_deep_sleep(struct fm_port *port_rx, -+ struct fm_port *port_tx); -+ -+bool fm_port_is_in_auto_res_mode(struct fm_port *port); -+ -+struct auto_res_tables_sizes *fm_port_get_autores_maxsize( -+ struct fm_port *port); -+ -+int fm_port_get_autores_stats(struct fm_port *port, struct auto_res_port_stats -+ *stats); -+ -+int fm_port_resume(struct fm_port *port); -+ -+int fm_port_suspend(struct fm_port *port); -+ -+#ifdef CONFIG_FMAN_PFC -+/**************************************************************************//** -+@Function fm_port_set_pfc_priorities_mapping_to_qman_wq -+ -+@Description Associate a QMan Work Queue with a PFC priority on this -+ FM-port device (Tx port). -+ -+@Param[in] port - A handle of the FM port device. -+ -+@Param[in] prio - The PFC priority. -+ -+@Param[in] wq - The Work Queue associated with the PFC priority. -+ -+@Cautions Allowed only after the port is initialized. -+*//***************************************************************************/ -+int fm_port_set_pfc_priorities_mapping_to_qman_wq(struct fm_port *port, -+ uint8_t prio, uint8_t wq); -+#endif -+ -+/**************************************************************************//** -+@Function fm_mac_set_exception -+ -+@Description Set MAC exception state. -+ -+@Param[in] fm_mac_dev - A handle of the FM MAC device. -+@Param[in] exception - FM MAC exception type. -+@Param[in] enable - new state. -+ -+*//***************************************************************************/ -+int fm_mac_set_exception(struct fm_mac_dev *fm_mac_dev, -+ e_FmMacExceptions exception, bool enable); -+ -+int fm_mac_free(struct fm_mac_dev *fm_mac_dev); -+ -+struct fm_mac_dev *fm_mac_config(t_FmMacParams *params); -+ -+int fm_mac_config_max_frame_length(struct fm_mac_dev *fm_mac_dev, -+ int len); -+ -+int fm_mac_config_pad_and_crc(struct fm_mac_dev *fm_mac_dev, bool enable); -+ -+int fm_mac_config_half_duplex(struct fm_mac_dev *fm_mac_dev, bool enable); -+ -+int fm_mac_config_reset_on_init(struct fm_mac_dev *fm_mac_dev, bool enable); -+ -+int fm_mac_init(struct fm_mac_dev *fm_mac_dev); -+ -+int fm_mac_get_version(struct fm_mac_dev *fm_mac_dev, uint32_t *version); -+ -+int fm_mac_enable(struct fm_mac_dev *fm_mac_dev); -+ -+int fm_mac_disable(struct fm_mac_dev *fm_mac_dev); -+ -+int fm_mac_set_promiscuous(struct fm_mac_dev *fm_mac_dev, -+ bool enable); -+ -+int fm_mac_remove_hash_mac_addr(struct fm_mac_dev *fm_mac_dev, -+ t_EnetAddr *mac_addr); -+ -+int fm_mac_add_hash_mac_addr(struct fm_mac_dev *fm_mac_dev, -+ t_EnetAddr *mac_addr); -+ -+int fm_mac_modify_mac_addr(struct fm_mac_dev *fm_mac_dev, -+ uint8_t *addr); -+ -+int fm_mac_adjust_link(struct fm_mac_dev *fm_mac_dev, -+ bool link, int speed, bool duplex); -+ -+int fm_mac_enable_1588_time_stamp(struct fm_mac_dev *fm_mac_dev); -+ -+int fm_mac_disable_1588_time_stamp(struct fm_mac_dev *fm_mac_dev); -+ -+int fm_mac_set_rx_pause_frames( -+ struct fm_mac_dev *fm_mac_dev, bool en); -+ -+int fm_mac_set_tx_pause_frames(struct fm_mac_dev *fm_mac_dev, -+ bool en); -+ -+int fm_rtc_enable(struct fm *fm_dev); -+ -+int fm_rtc_disable(struct fm *fm_dev); -+ -+int fm_rtc_get_cnt(struct fm *fm_dev, uint64_t *ts); -+ -+int fm_rtc_set_cnt(struct fm *fm_dev, uint64_t ts); -+ -+int fm_rtc_get_drift(struct fm *fm_dev, uint32_t *drift); -+ -+int fm_rtc_set_drift(struct fm *fm_dev, uint32_t drift); -+ -+int fm_rtc_set_alarm(struct fm *fm_dev, uint32_t id, -+ uint64_t time); -+ -+int fm_rtc_set_fiper(struct fm *fm_dev, uint32_t id, -+ uint64_t fiper); -+ -+int fm_mac_set_wol(struct fm_port *port, struct fm_mac_dev *fm_mac_dev, -+ bool en); -+ -+/**************************************************************************//** -+@Function fm_macsec_set_exception -+ -+@Description Set MACSEC exception state. -+ -+@Param[in] fm_macsec_dev - A handle of the FM MACSEC device. -+@Param[in] exception - FM MACSEC exception type. -+@Param[in] enable - new state. -+ -+*//***************************************************************************/ -+ -+int fm_macsec_set_exception(struct fm_macsec_dev *fm_macsec_dev, -+ fm_macsec_exception exception, bool enable); -+int fm_macsec_free(struct fm_macsec_dev *fm_macsec_dev); -+struct fm_macsec_dev *fm_macsec_config(struct fm_macsec_params *fm_params); -+int fm_macsec_init(struct fm_macsec_dev *fm_macsec_dev); -+int fm_macsec_config_unknown_sci_frame_treatment(struct fm_macsec_dev -+ *fm_macsec_dev, -+ fm_macsec_unknown_sci_frame_treatment treat_mode); -+int fm_macsec_config_invalid_tags_frame_treatment(struct fm_macsec_dev *fm_macsec_dev, -+ bool deliver_uncontrolled); -+int fm_macsec_config_kay_frame_treatment(struct fm_macsec_dev *fm_macsec_dev, -+ bool discard_uncontrolled); -+int fm_macsec_config_untag_frame_treatment(struct fm_macsec_dev *fm_macsec_dev, -+ fm_macsec_untag_frame_treatment treat_mode); -+int fm_macsec_config_pn_exhaustion_threshold(struct fm_macsec_dev *fm_macsec_dev, -+ uint32_t pnExhThr); -+int fm_macsec_config_keys_unreadable(struct fm_macsec_dev *fm_macsec_dev); -+int fm_macsec_config_sectag_without_sci(struct fm_macsec_dev *fm_macsec_dev); -+int fm_macsec_config_exception(struct fm_macsec_dev *fm_macsec_dev, -+ fm_macsec_exception exception, bool enable); -+int fm_macsec_get_revision(struct fm_macsec_dev *fm_macsec_dev, -+ int *macsec_revision); -+int fm_macsec_enable(struct fm_macsec_dev *fm_macsec_dev); -+int fm_macsec_disable(struct fm_macsec_dev *fm_macsec_dev); -+ -+ -+int fm_macsec_secy_config_exception(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ fm_macsec_secy_exception exception, -+ bool enable); -+int fm_macsec_secy_free(struct fm_macsec_secy_dev *fm_macsec_secy_dev); -+struct fm_macsec_secy_dev *fm_macsec_secy_config(struct fm_macsec_secy_params *secy_params); -+int fm_macsec_secy_init(struct fm_macsec_secy_dev *fm_macsec_secy_dev); -+int fm_macsec_secy_config_sci_insertion_mode(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ fm_macsec_sci_insertion_mode sci_insertion_mode); -+int fm_macsec_secy_config_protect_frames(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ bool protect_frames); -+int fm_macsec_secy_config_replay_window(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ bool replay_protect, uint32_t replay_window); -+int fm_macsec_secy_config_validation_mode(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ fm_macsec_valid_frame_behavior validate_frames); -+int fm_macsec_secy_config_confidentiality(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ bool confidentiality_enable, -+ uint32_t confidentiality_offset); -+int fm_macsec_secy_config_point_to_point(struct fm_macsec_secy_dev *fm_macsec_secy_dev); -+int fm_macsec_secy_config_event(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ fm_macsec_secy_event event, -+ bool enable); -+struct rx_sc_dev *fm_macsec_secy_create_rxsc(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct fm_macsec_secy_sc_params *params); -+int fm_macsec_secy_delete_rxsc(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc); -+int fm_macsec_secy_create_rx_sa(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, macsec_an_t an, -+ uint32_t lowest_pn, macsec_sa_key_t key); -+int fm_macsec_secy_delete_rx_sa(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, macsec_an_t an); -+int fm_macsec_secy_rxsa_enable_receive(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, -+ macsec_an_t an); -+int fm_macsec_secy_rxsa_disable_receive(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, -+ macsec_an_t an); -+int fm_macsec_secy_rxsa_update_next_pn(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, -+ macsec_an_t an, uint32_t updt_next_pn); -+int fm_macsec_secy_rxsa_update_lowest_pn(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, -+ macsec_an_t an, uint32_t updt_lowest_pn); -+int fm_macsec_secy_rxsa_modify_key(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, -+ macsec_an_t an, macsec_sa_key_t key); -+int fm_macsec_secy_create_tx_sa(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ macsec_an_t an, macsec_sa_key_t key); -+int fm_macsec_secy_delete_tx_sa(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ macsec_an_t an); -+int fm_macsec_secy_txsa_modify_key(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ macsec_an_t next_active_an, -+ macsec_sa_key_t key); -+int fm_macsec_secy_txsa_set_active(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ macsec_an_t an); -+int fm_macsec_secy_txsa_get_active(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ macsec_an_t *p_an); -+int fm_macsec_secy_get_rxsc_phys_id(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, uint32_t *sc_phys_id); -+int fm_macsec_secy_get_txsc_phys_id(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ uint32_t *sc_phys_id); -+ -+/** @} */ /* end of FM_LnxKern_ctrl_grp group */ -+/** @} */ /* end of FM_LnxKern_grp group */ -+ -+/* default values for initializing PTP 1588 timer clock */ -+#define DPA_PTP_NOMINAL_FREQ_PERIOD_SHIFT 2 /* power of 2 for better performance */ -+#define DPA_PTP_NOMINAL_FREQ_PERIOD_NS (1 << DPA_PTP_NOMINAL_FREQ_PERIOD_SHIFT) /* 4ns,250MHz */ -+ -+#endif /* __LNXWRP_FSL_FMAN_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/inc/xx/xx.h -@@ -0,0 +1,50 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __XX_H -+#define __XX_H -+ -+#include "xx_ext.h" -+ -+void * xx_Malloc(uint32_t n); -+void xx_Free(void *p); -+ -+void *xx_MallocSmart(uint32_t size, int memPartitionId, uint32_t align); -+void xx_FreeSmart(void *p); -+ -+/* never used: */ -+#define GetDeviceName(irq) ((char *)NULL) -+ -+int GetDeviceIrqNum(int irq); -+ -+ -+#endif /* __XX_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/system/Makefile -@@ -0,0 +1,10 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+# -+ -+obj-y += sys_io.o ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/system/sys_io.c -@@ -0,0 +1,171 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+ -+#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS) -+#define MODVERSIONS -+#endif -+#ifdef MODVERSIONS -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#include -+#else -+#include -+#endif /* LINUX_VERSION_CODE */ -+#endif /* MODVERSIONS */ -+ -+#include -+#include -+ -+#include -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "string_ext.h" -+#include "list_ext.h" -+#include "sys_io_ext.h" -+ -+ -+#define __ERR_MODULE__ MODULE_UNKNOWN -+ -+ -+typedef struct { -+ uint64_t virtAddr; -+ uint64_t physAddr; -+ uint32_t size; -+ t_List node; -+} t_IoMap; -+#define IOMAP_OBJECT(ptr) LIST_OBJECT(ptr, t_IoMap, node) -+ -+LIST(mapsList); -+ -+ -+static void EnqueueIoMap(t_IoMap *p_IoMap) -+{ -+ uint32_t intFlags; -+ -+ intFlags = XX_DisableAllIntr(); -+ LIST_AddToTail(&p_IoMap->node, &mapsList); -+ XX_RestoreAllIntr(intFlags); -+} -+ -+static t_IoMap * FindIoMapByVirtAddr(uint64_t addr) -+{ -+ t_IoMap *p_IoMap; -+ t_List *p_Pos; -+ -+ LIST_FOR_EACH(p_Pos, &mapsList) -+ { -+ p_IoMap = IOMAP_OBJECT(p_Pos); -+ if ((addr >= p_IoMap->virtAddr) && (addr < p_IoMap->virtAddr+p_IoMap->size)) -+ return p_IoMap; -+ } -+ -+ return NULL; -+} -+ -+static t_IoMap * FindIoMapByPhysAddr(uint64_t addr) -+{ -+ t_IoMap *p_IoMap; -+ t_List *p_Pos; -+ -+ LIST_FOR_EACH(p_Pos, &mapsList) -+ { -+ p_IoMap = IOMAP_OBJECT(p_Pos); -+ if ((addr >= p_IoMap->physAddr) && (addr < p_IoMap->physAddr+p_IoMap->size)) -+ return p_IoMap; -+ } -+ -+ return NULL; -+} -+ -+t_Error SYS_RegisterIoMap (uint64_t virtAddr, uint64_t physAddr, uint32_t size) -+{ -+ t_IoMap *p_IoMap; -+ -+ p_IoMap = (t_IoMap*)XX_Malloc(sizeof(t_IoMap)); -+ if (!p_IoMap) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("message handler object!!!")); -+ memset(p_IoMap, 0, sizeof(t_IoMap)); -+ -+ p_IoMap->virtAddr = virtAddr; -+ p_IoMap->physAddr = physAddr; -+ p_IoMap->size = size; -+ -+ INIT_LIST(&p_IoMap->node); -+ EnqueueIoMap(p_IoMap); -+ -+ return E_OK; -+} -+ -+t_Error SYS_UnregisterIoMap (uint64_t virtAddr) -+{ -+ t_IoMap *p_IoMap = FindIoMapByVirtAddr(virtAddr); -+ if (!p_IoMap) -+ RETURN_ERROR(MINOR, E_NO_DEVICE, ("message handler not found in list!!!")); -+ -+ LIST_Del(&p_IoMap->node); -+ XX_Free(p_IoMap); -+ -+ return E_OK; -+} -+ -+uint64_t SYS_PhysToVirt(uint64_t addr) -+{ -+ t_IoMap *p_IoMap = FindIoMapByPhysAddr(addr); -+ if (p_IoMap) -+ { -+ /* This is optimization - put the latest in the list-head - like a cache */ -+ if (mapsList.p_Next != &p_IoMap->node) -+ { -+ uint32_t intFlags = XX_DisableAllIntr(); -+ LIST_DelAndInit(&p_IoMap->node); -+ LIST_Add(&p_IoMap->node, &mapsList); -+ XX_RestoreAllIntr(intFlags); -+ } -+ return (uint64_t)(addr - p_IoMap->physAddr + p_IoMap->virtAddr); -+ } -+ return PTR_TO_UINT(phys_to_virt((unsigned long)addr)); -+} -+ -+uint64_t SYS_VirtToPhys(uint64_t addr) -+{ -+ t_IoMap *p_IoMap; -+ -+ if (addr == 0) -+ return 0; -+ -+ p_IoMap = FindIoMapByVirtAddr(addr); -+ if (p_IoMap) -+ return (uint64_t)(addr - p_IoMap->virtAddr + p_IoMap->physAddr); -+ return (uint64_t)virt_to_phys(UINT_TO_PTR(addr)); -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/Makefile -@@ -0,0 +1,19 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+ -+NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc -+ -+ccflags-y += -I$(NCSW_FM_INC) -+ccflags-y += -I$(NET_DPA) -+ -+obj-y += fsl-ncsw-PFM.o -+obj-$(CONFIG_FSL_SDK_FMAN_TEST) += fman_test.o -+ -+fsl-ncsw-PFM-objs := lnxwrp_fm.o lnxwrp_fm_port.o lnxwrp_ioctls_fm.o \ -+ lnxwrp_sysfs.o lnxwrp_sysfs_fm.o lnxwrp_sysfs_fm_port.o -+obj-$(CONFIG_COMPAT) += lnxwrp_ioctls_fm_compat.o ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/fman_test.c -@@ -0,0 +1,1665 @@ -+/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ @File fman_test.c -+ @Authors Pistirica Sorin Andrei -+ @Description FM Linux test environment -+*/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* private headers */ -+#include "fm_ext.h" -+#include "lnxwrp_fsl_fman.h" -+#include "fm_port_ext.h" -+#if (DPAA_VERSION == 11) -+#include "../../Peripherals/FM/MAC/memac.h" -+#endif -+#include "fm_test_ioctls.h" -+#include "fsl_fman_test.h" -+ -+#include "dpaa_eth.h" -+#include "dpaa_eth_common.h" -+ -+#define FMT_FRM_WATERMARK 0xdeadbeefdeadbeeaLL -+ -+struct fmt_frame_s { -+ ioc_fmt_buff_desc_t buff; -+ struct list_head list; -+}; -+ -+struct fmt_fqs_s { -+ struct qman_fq fq_base; -+ bool init; -+ struct fmt_port_s *fmt_port_priv; -+}; -+ -+struct fmt_port_pcd_s { -+ int num_queues; -+ struct fmt_fqs_s *fmt_pcd_fqs; -+ uint32_t fqid_base; -+}; -+ -+/* char dev structure: fm test port */ -+struct fmt_port_s { -+ bool valid; -+ uint8_t id; -+ ioc_fmt_port_type port_type; -+ ioc_diag_mode diag; -+ bool compat_test_type; -+ -+ /* fm ports */ -+ /* ! for oh ports p_tx_fm_port_dev == p_rx_fm_port_dev && -+ * p_tx_port == p_rx_port */ -+ /* t_LnxWrpFmPortDev */ -+ struct fm_port *p_tx_port; -+ /* t_LnxWrpFmPortDev->h_Dev: t_FmPort */ -+ void *p_tx_fm_port_dev; -+ /* t_LnxWrpFmPortDev */ -+ struct fm_port *p_rx_port; -+ /* t_LnxWrpFmPortDev->h_Dev: t_FmPort */ -+ void *p_rx_fm_port_dev; -+ -+ void *p_mac_dev; -+ uint64_t fm_phys_base_addr; -+ -+ /* read/write queue manipulation */ -+ spinlock_t rx_q_lock; -+ struct list_head rx_q; -+ -+ /* tx queuee for injecting traffic */ -+ int num_of_tx_fqs; -+ struct fmt_fqs_s p_tx_fqs[FMAN_TEST_MAX_TX_FQS]; -+ -+ /* pcd private queues manipulation */ -+ struct fmt_port_pcd_s fmt_port_pcd; -+ -+ /* debugging stuff */ -+ -+#if defined(FMT_K_DBG) || defined(FMT_K_DBG_RUNTIME) -+ atomic_t enqueue_to_qman_frm; -+ atomic_t enqueue_to_rxq; -+ atomic_t dequeue_from_rxq; -+ atomic_t not_enqueue_to_rxq_wrong_frm; -+#endif -+ -+}; -+ -+/* The devices. */ -+struct fmt_s { -+ int major; -+ struct fmt_port_s ports[IOC_FMT_MAX_NUM_OF_PORTS]; -+ struct class *fmt_class; -+}; -+ -+/* fm test structure */ -+static struct fmt_s fm_test; -+ -+#if (DPAA_VERSION == 11) -+struct mac_priv_s { -+ t_Handle mac; -+}; -+#endif -+ -+#define DTSEC_BASE_ADDR 0x000e0000 -+#define DTSEC_MEM_RANGE 0x00002000 -+#define MAC_1G_MACCFG1 0x00000100 -+#define MAC_1G_LOOP_MASK 0x00000100 -+static int set_1gmac_loopback( -+ struct fmt_port_s *fmt_port, -+ bool en) -+{ -+#if (DPAA_VERSION <= 10) -+ uint32_t dtsec_idx = fmt_port->id; /* dtsec for which port */ -+ uint32_t dtsec_idx_off = dtsec_idx * DTSEC_MEM_RANGE; -+ phys_addr_t maccfg1_hw; -+ void *maccfg1_map; -+ uint32_t maccfg1_val; -+ -+ /* compute the maccfg1 register address */ -+ maccfg1_hw = fmt_port->fm_phys_base_addr + -+ (phys_addr_t)(DTSEC_BASE_ADDR + -+ dtsec_idx_off + -+ MAC_1G_MACCFG1); -+ -+ /* map register */ -+ maccfg1_map = ioremap(maccfg1_hw, sizeof(u32)); -+ -+ /* set register */ -+ maccfg1_val = in_be32(maccfg1_map); -+ if (en) -+ maccfg1_val |= MAC_1G_LOOP_MASK; -+ else -+ maccfg1_val &= ~MAC_1G_LOOP_MASK; -+ out_be32(maccfg1_map, maccfg1_val); -+ -+ /* unmap register */ -+ iounmap(maccfg1_map); -+#else -+ struct mac_device *mac_dev; -+ struct mac_priv_s *priv; -+ t_Memac *p_memac; -+ -+ if (!fmt_port) -+ return -EINVAL; -+ -+ mac_dev = (struct mac_device *)fmt_port->p_mac_dev; -+ -+ if (!mac_dev) -+ return -EINVAL; -+ -+ priv = macdev_priv(mac_dev); -+ -+ if (!priv) -+ return -EINVAL; -+ -+ p_memac = priv->mac; -+ -+ if (!p_memac) -+ return -EINVAL; -+ -+ memac_set_loopback(p_memac->p_MemMap, en); -+#endif -+ return 0; -+} -+ -+/* TODO: re-write this function */ -+static int set_10gmac_int_loopback( -+ struct fmt_port_s *fmt_port, -+ bool en) -+{ -+#ifndef FM_10G_MAC_NO_CTRL_LOOPBACK -+#define FM_10GMAC0_OFFSET 0x000f0000 -+#define FM_10GMAC_CMD_CONF_CTRL_OFFSET 0x8 -+#define CMD_CFG_LOOPBACK_EN 0x00000400 -+ -+ uint64_t base_addr, reg_addr; -+ uint32_t tmp_val; -+ -+ base_addr = fmt_port->fm_phys_base_addr + (FM_10GMAC0_OFFSET + -+ ((fmt_port->id-FM_MAX_NUM_OF_1G_RX_PORTS)*0x2000)); -+ -+ base_addr = PTR_TO_UINT(ioremap(base_addr, 0x1000)); -+ -+ reg_addr = base_addr + FM_10GMAC_CMD_CONF_CTRL_OFFSET; -+ tmp_val = GET_UINT32(*((uint32_t *)UINT_TO_PTR(reg_addr))); -+ if (en) -+ tmp_val |= CMD_CFG_LOOPBACK_EN; -+ else -+ tmp_val &= ~CMD_CFG_LOOPBACK_EN; -+ WRITE_UINT32(*((uint32_t *)UINT_TO_PTR(reg_addr)), tmp_val); -+ -+ iounmap(UINT_TO_PTR(base_addr)); -+ -+ return 0; -+#else -+ _fmt_err("TGEC don't have internal-loopback.\n"); -+ return -EPERM; -+#endif -+} -+ -+static int set_mac_int_loopback(struct fmt_port_s *fmt_port, bool en) -+{ -+ int _err = 0; -+ -+ switch (fmt_port->port_type) { -+ -+ case e_IOC_FMT_PORT_T_RXTX: -+ /* 1G port */ -+ if (fmt_port->id < FM_MAX_NUM_OF_1G_RX_PORTS) -+ _err = set_1gmac_loopback(fmt_port, en); -+ /* 10g port */ -+ else if ((fmt_port->id >= FM_MAX_NUM_OF_1G_RX_PORTS) && -+ (fmt_port->id < FM_MAX_NUM_OF_1G_RX_PORTS + -+ FM_MAX_NUM_OF_10G_RX_PORTS)) { -+ -+ _err = set_10gmac_int_loopback(fmt_port, en); -+ } else -+ _err = -EINVAL; -+ break; -+ /* op port does not have MAC (loopback mode) */ -+ case e_IOC_FMT_PORT_T_OP: -+ -+ _err = 0; -+ break; -+ default: -+ -+ _err = -EPERM; -+ break; -+ } -+ -+ return _err; -+} -+ -+static void enqueue_fmt_frame( -+ struct fmt_port_s *fmt_port, -+ struct fmt_frame_s *p_fmt_frame) -+{ -+ spinlock_t *rx_q_lock = NULL; -+ -+ rx_q_lock = &fmt_port->rx_q_lock; -+ -+ spin_lock(rx_q_lock); -+ list_add_tail(&p_fmt_frame->list, &fmt_port->rx_q); -+ spin_unlock(rx_q_lock); -+ -+#if defined(FMT_K_DBG) || defined(FMT_K_DBG_RUNTIME) -+ atomic_inc(&fmt_port->enqueue_to_rxq); -+#endif -+} -+ -+static struct fmt_frame_s *dequeue_fmt_frame( -+ struct fmt_port_s *fmt_port) -+{ -+ struct fmt_frame_s *p_fmt_frame = NULL; -+ spinlock_t *rx_q_lock = NULL; -+ -+ rx_q_lock = &fmt_port->rx_q_lock; -+ -+ spin_lock(rx_q_lock); -+ -+#define list_last_entry(ptr, type, member) list_entry((ptr)->prev, type, member) -+ -+ if (!list_empty(&fmt_port->rx_q)) { -+ p_fmt_frame = list_last_entry(&fmt_port->rx_q, -+ struct fmt_frame_s, -+ list); -+ list_del(&p_fmt_frame->list); -+ -+#if defined(FMT_K_DBG) || defined(FMT_K_DBG_RUNTIME) -+ atomic_inc(&fmt_port->dequeue_from_rxq); -+#endif -+ } -+ -+ spin_unlock(rx_q_lock); -+ -+ return p_fmt_frame; -+} -+ -+/* eth-dev -to- fmt port association */ -+struct fmt_port_s *match_dpa_to_fmt_port( -+ struct dpa_priv_s *dpa_priv) { -+ struct mac_device *mac_dev = dpa_priv->mac_dev; -+ struct fm_port *fm_port = (struct fm_port *) mac_dev; -+ struct fmt_port_s *fmt_port = NULL; -+ int i; -+ -+ _fmt_dbgr("calling...\n"); -+ -+ /* find the FM-test-port object */ -+ for (i = 0; i < IOC_FMT_MAX_NUM_OF_PORTS; i++) -+ if ((fm_test.ports[i].p_mac_dev && -+ mac_dev == fm_test.ports[i].p_mac_dev) || -+ fm_port == fm_test.ports[i].p_tx_port) { -+ -+ fmt_port = &fm_test.ports[i]; -+ break; -+ } -+ -+ _fmt_dbgr("called\n"); -+ return fmt_port; -+} -+ -+void dump_frame( -+ uint8_t *buffer, -+ uint32_t size) -+{ -+#if defined(FMT_K_DBG) || defined(FMT_K_DBG_RUNTIME) -+ unsigned int i; -+ -+ for (i = 0; i < size; i++) { -+ if (i%16 == 0) -+ printk(KERN_DEBUG "\n"); -+ printk(KERN_DEBUG "%2x ", *(buffer+i)); -+ } -+#endif -+ return; -+} -+ -+bool test_and_steal_frame(struct fmt_port_s *fmt_port, -+ uint32_t fqid, -+ uint8_t *buffer, -+ uint32_t size) -+{ -+ struct fmt_frame_s *p_fmt_frame = NULL; -+ bool test_and_steal_frame_frame; -+ uint32_t data_offset; -+ uint32_t i; -+ -+ _fmt_dbgr("calling...\n"); -+ -+ if (!fmt_port || !fmt_port->p_rx_fm_port_dev) -+ return false; -+ -+ /* check watermark */ -+ test_and_steal_frame_frame = false; -+ for (i = 0; i < size; i++) { -+ uint64_t temp = *((uint64_t *)(buffer + i)); -+ -+ if (temp == (uint64_t) FMT_FRM_WATERMARK) { -+ _fmt_dbgr("watermark found!\n"); -+ test_and_steal_frame_frame = true; -+ break; -+ } -+ } -+ -+ if (!test_and_steal_frame_frame) { -+#if defined(FMT_K_DBG) || defined(FMT_K_DBG_RUNTIME) -+ atomic_inc(&fmt_port->not_enqueue_to_rxq_wrong_frm); -+#endif -+ _fmt_dbgr("NOT watermark found!\n"); -+ return false; -+ } -+ -+ /* do not enqueue the tx conf/err frames */ -+ if ((fqid == FMT_TX_CONF_Q) || (fqid == FMT_TX_ERR_Q)) -+ goto _test_and_steal_frame_return_true; -+ -+ _fmt_dbgr("on port %d got FMUC frame\n", fmt_port->id); -+ data_offset = FM_PORT_GetBufferDataOffset( -+ fmt_port->p_rx_fm_port_dev); -+ -+ p_fmt_frame = kmalloc(sizeof(struct fmt_frame_s), GFP_KERNEL); -+ -+ /* dump frame... no more space left on device */ -+ if (p_fmt_frame == NULL) { -+ _fmt_err("no space left on device!\n"); -+ goto _test_and_steal_frame_return_true; -+ } -+ -+ memset(p_fmt_frame, 0, sizeof(struct fmt_frame_s)); -+ p_fmt_frame->buff.p_data = kmalloc(size * sizeof(uint8_t), GFP_KERNEL); -+ -+ /* No more space left on device*/ -+ if (p_fmt_frame->buff.p_data == NULL) { -+ _fmt_err("no space left on device!\n"); -+ kfree(p_fmt_frame); -+ goto _test_and_steal_frame_return_true; -+ } -+ -+ p_fmt_frame->buff.size = size-data_offset; -+ p_fmt_frame->buff.qid = fqid; -+ -+ memcpy(p_fmt_frame->buff.p_data, -+ (uint8_t *)PTR_MOVE(buffer, data_offset), -+ p_fmt_frame->buff.size); -+ -+ memcpy(p_fmt_frame->buff.buff_context.fm_prs_res, -+ FM_PORT_GetBufferPrsResult(fmt_port->p_rx_fm_port_dev, -+ (char *)buffer), -+ 32); -+ -+ /* enqueue frame - this frame will go to us */ -+ enqueue_fmt_frame(fmt_port, p_fmt_frame); -+ -+_test_and_steal_frame_return_true: -+ return true; -+} -+ -+static int fmt_fq_release(const struct qm_fd *fd) -+{ -+ struct dpa_bp *_dpa_bp; -+ struct bm_buffer _bmb; -+ -+ if (fd->format == qm_fd_contig) { -+ _dpa_bp = dpa_bpid2pool(fd->bpid); -+ BUG_ON(IS_ERR(_dpa_bp)); -+ -+ _bmb.hi = fd->addr_hi; -+ _bmb.lo = fd->addr_lo; -+ -+ while (bman_release(_dpa_bp->pool, &_bmb, 1, 0)) -+ cpu_relax(); -+ -+ } else { -+ _fmt_err("frame not supported !\n"); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+/* sync it w/ dpaa_eth.c: DPA_BP_HEAD */ -+#define DPA_BP_HEADROOM (DPA_TX_PRIV_DATA_SIZE + \ -+ fm_get_rx_extra_headroom() + \ -+ DPA_PARSE_RESULTS_SIZE + \ -+ DPA_HASH_RESULTS_SIZE) -+#define MAC_HEADER_LENGTH 14 -+#define L2_AND_HEADROOM_OFF ((DPA_BP_HEADROOM) + (MAC_HEADER_LENGTH)) -+ -+/* dpa ingress hooks definition */ -+enum dpaa_eth_hook_result fmt_rx_default_hook( -+ struct sk_buff *skb, -+ struct net_device *net_dev, -+ u32 fqid) -+{ -+ struct dpa_priv_s *dpa_priv = NULL; -+ struct fmt_port_s *fmt_port = NULL; -+ uint8_t *buffer; -+ uint32_t buffer_len; -+ -+ _fmt_dbgr("calling...\n"); -+ -+ dpa_priv = netdev_priv(net_dev); -+ fmt_port = match_dpa_to_fmt_port(dpa_priv); -+ -+ /* conversion from skb to fd: -+ * skb cames processed for L3, so we need to go back for -+ * layer 2 offset */ -+ buffer = (uint8_t *)(skb->data - ((int)L2_AND_HEADROOM_OFF)); -+ buffer_len = skb->len + ((int)L2_AND_HEADROOM_OFF); -+ -+ /* if is not out frame let dpa to handle it */ -+ if (test_and_steal_frame(fmt_port, -+ FMT_RX_DFLT_Q, -+ buffer, -+ buffer_len)) -+ goto _fmt_rx_default_hook_stolen; -+ -+ _fmt_dbgr("called:DPAA_ETH_CONTINUE.\n"); -+ return DPAA_ETH_CONTINUE; -+ -+_fmt_rx_default_hook_stolen: -+ dev_kfree_skb(skb); -+ -+ _fmt_dbgr("called:DPAA_ETH_STOLEN.\n"); -+ return DPAA_ETH_STOLEN; -+} -+ -+enum dpaa_eth_hook_result fmt_rx_error_hook( -+ struct net_device *net_dev, -+ const struct qm_fd *fd, -+ u32 fqid) -+{ -+ struct dpa_priv_s *dpa_priv = NULL; -+ struct dpa_bp *dpa_bp = NULL; -+ struct fmt_port_s *fmt_port = NULL; -+ void *fd_virt_addr = NULL; -+ dma_addr_t addr = qm_fd_addr(fd); -+ -+ _fmt_dbgr("calling...\n"); -+ -+ dpa_priv = netdev_priv(net_dev); -+ fmt_port = match_dpa_to_fmt_port(dpa_priv); -+ -+ /* dpaa doesn't do this... we have to do it here */ -+ dpa_bp = dpa_bpid2pool(fd->bpid); -+ dma_unmap_single(dpa_bp->dev, addr, dpa_bp->size, DMA_BIDIRECTIONAL); -+ -+ fd_virt_addr = phys_to_virt(addr); -+ /* if is not out frame let dpa to handle it */ -+ if (test_and_steal_frame(fmt_port, -+ FMT_RX_ERR_Q, -+ fd_virt_addr, -+ fd->length20 + fd->offset)) { -+ goto _fmt_rx_error_hook_stolen; -+ } -+ -+ _fmt_dbgr("called:DPAA_ETH_CONTINUE.\n"); -+ return DPAA_ETH_CONTINUE; -+ -+_fmt_rx_error_hook_stolen: -+ /* the frame data doesn't matter, -+ * so, no mapping is needed */ -+ fmt_fq_release(fd); -+ -+ _fmt_dbgr("called:DPAA_ETH_STOLEN.\n"); -+ return DPAA_ETH_STOLEN; -+} -+ -+enum dpaa_eth_hook_result fmt_tx_confirm_hook( -+ struct net_device *net_dev, -+ const struct qm_fd *fd, -+ u32 fqid) -+{ -+ struct dpa_priv_s *dpa_priv = NULL; -+ struct fmt_port_s *fmt_port = NULL; -+ dma_addr_t addr = qm_fd_addr(fd); -+ void *fd_virt_addr = NULL; -+ uint32_t fd_len = 0; -+ -+ _fmt_dbgr("calling...\n"); -+ -+ dpa_priv = netdev_priv(net_dev); -+ fmt_port = match_dpa_to_fmt_port(dpa_priv); -+ -+ fd_virt_addr = phys_to_virt(addr); -+ fd_len = fd->length20 + fd->offset; -+ -+ if (fd_len > fm_get_max_frm()) { -+ _fmt_err("tx confirm bad frame size: %u!\n", fd_len); -+ goto _fmt_tx_confirm_hook_continue; -+ } -+ -+ if (test_and_steal_frame(fmt_port, -+ FMT_TX_CONF_Q, -+ fd_virt_addr, -+ fd_len)) -+ goto _fmt_tx_confirm_hook_stolen; -+ -+_fmt_tx_confirm_hook_continue: -+ _fmt_dbgr("called:DPAA_ETH_CONTINUE.\n"); -+ return DPAA_ETH_CONTINUE; -+ -+_fmt_tx_confirm_hook_stolen: -+ kfree(fd_virt_addr); -+ -+ _fmt_dbgr("called:DPAA_ETH_STOLEN.\n"); -+ return DPAA_ETH_STOLEN; -+} -+ -+enum dpaa_eth_hook_result fmt_tx_confirm_error_hook( -+ struct net_device *net_dev, -+ const struct qm_fd *fd, -+ u32 fqid) -+{ -+ struct dpa_priv_s *dpa_priv = NULL; -+ struct fmt_port_s *fmt_port = NULL; -+ dma_addr_t addr = qm_fd_addr(fd); -+ void *fd_virt_addr = NULL; -+ uint32_t fd_len = 0; -+ -+ _fmt_dbgr("calling...\n"); -+ -+ dpa_priv = netdev_priv(net_dev); -+ fmt_port = match_dpa_to_fmt_port(dpa_priv); -+ -+ fd_virt_addr = phys_to_virt(addr); -+ fd_len = fd->length20 + fd->offset; -+ -+ if (fd_len > fm_get_max_frm()) { -+ _fmt_err("tx confirm err bad frame size: %u !\n", fd_len); -+ goto _priv_ingress_tx_err_continue; -+ } -+ -+ if (test_and_steal_frame(fmt_port, FMT_TX_ERR_Q, fd_virt_addr, fd_len)) -+ goto _priv_ingress_tx_err_stolen; -+ -+_priv_ingress_tx_err_continue: -+ _fmt_dbgr("called:DPAA_ETH_CONTINUE.\n"); -+ return DPAA_ETH_CONTINUE; -+ -+_priv_ingress_tx_err_stolen: -+ kfree(fd_virt_addr); -+ -+ _fmt_dbgr("called:DPAA_ETH_STOLEN.\n"); -+ return DPAA_ETH_STOLEN; -+} -+ -+/* egress callbacks definition */ -+enum qman_cb_dqrr_result fmt_egress_dqrr( -+ struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dqrr) -+{ -+ /* this callback should never be called */ -+ BUG(); -+ return qman_cb_dqrr_consume; -+} -+ -+static void fmt_egress_error_dqrr( -+ struct qman_portal *p, -+ struct qman_fq *fq, -+ const struct qm_mr_entry *msg) -+{ -+ uint8_t *fd_virt_addr = NULL; -+ -+ /* tx failure, on the ern callback - release buffer */ -+ fd_virt_addr = (uint8_t *)phys_to_virt(qm_fd_addr(&msg->ern.fd)); -+ kfree(fd_virt_addr); -+ -+ return; -+} -+ -+static const struct qman_fq fmt_egress_fq = { -+ .cb = { .dqrr = fmt_egress_dqrr, -+ .ern = fmt_egress_error_dqrr, -+ .fqs = NULL} -+}; -+ -+int fmt_fq_alloc( -+ struct fmt_fqs_s *fmt_fqs, -+ const struct qman_fq *qman_fq, -+ uint32_t fqid, uint32_t flags, -+ uint16_t channel, uint8_t wq) -+{ -+ int _errno = 0; -+ -+ _fmt_dbg("calling...\n"); -+ -+ fmt_fqs->fq_base = *qman_fq; -+ -+ if (fqid == 0) { -+ flags |= QMAN_FQ_FLAG_DYNAMIC_FQID; -+ flags &= ~QMAN_FQ_FLAG_NO_MODIFY; -+ } else -+ flags &= ~QMAN_FQ_FLAG_DYNAMIC_FQID; -+ -+ fmt_fqs->init = !(flags & QMAN_FQ_FLAG_NO_MODIFY); -+ -+ _errno = qman_create_fq(fqid, flags, &fmt_fqs->fq_base); -+ if (_errno < 0) { -+ _fmt_err("frame queues create failed.\n"); -+ return -EINVAL; -+ } -+ -+ if (fmt_fqs->init) { -+ struct qm_mcc_initfq initfq; -+ -+ initfq.we_mask = QM_INITFQ_WE_DESTWQ; -+ initfq.fqd.dest.channel = channel; -+ initfq.fqd.dest.wq = wq; -+ -+ _errno = qman_init_fq(&fmt_fqs->fq_base, -+ QMAN_INITFQ_FLAG_SCHED, -+ &initfq); -+ if (_errno < 0) { -+ _fmt_err("frame queues init erorr.\n"); -+ qman_destroy_fq(&fmt_fqs->fq_base, 0); -+ return -EINVAL; -+ } -+ } -+ -+ _fmt_dbg("called.\n"); -+ return 0; -+} -+ -+static int fmt_fq_free(struct fmt_fqs_s *fmt_fq) -+{ -+ int _err = 0; -+ -+ _fmt_dbg("calling...\n"); -+ -+ if (fmt_fq->init) { -+ _err = qman_retire_fq(&fmt_fq->fq_base, NULL); -+ if (unlikely(_err < 0)) -+ _fmt_err("qman_retire_fq(%u) = %d\n", -+ qman_fq_fqid(&fmt_fq->fq_base), _err); -+ -+ _err = qman_oos_fq(&fmt_fq->fq_base); -+ if (unlikely(_err < 0)) -+ _fmt_err("qman_oos_fq(%u) = %d\n", -+ qman_fq_fqid(&fmt_fq->fq_base), _err); -+ } -+ -+ qman_destroy_fq(&fmt_fq->fq_base, 0); -+ -+ _fmt_dbg("called.\n"); -+ return _err; -+} -+ -+/* private pcd dqrr calbacks */ -+static enum qman_cb_dqrr_result fmt_pcd_dqrr( -+ struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq) -+{ -+ struct dpa_bp *dpa_bp = NULL; -+ dma_addr_t addr = qm_fd_addr(&dq->fd); -+ uint8_t *fd_virt_addr = NULL; -+ struct fmt_port_s *fmt_port; -+ struct fmt_port_pcd_s *fmt_port_pcd; -+ uint32_t relative_fqid = 0; -+ uint32_t fd_len = 0; -+ -+ _fmt_dbgr("calling...\n"); -+ -+ /* upcast - from pcd_alloc_fq */ -+ fmt_port = ((struct fmt_fqs_s *)fq)->fmt_port_priv; -+ if (!fmt_port) { -+ _fmt_err(" wrong fmt port -to- fq match.\n"); -+ goto _fmt_pcd_dqrr_return; -+ } -+ fmt_port_pcd = &fmt_port->fmt_port_pcd; -+ -+ relative_fqid = dq->fqid - fmt_port_pcd->fqid_base; -+ _fmt_dbgr("pcd dqrr got frame on relative fq:%u@base:%u\n", -+ relative_fqid, fmt_port_pcd->fqid_base); -+ -+ fd_len = dq->fd.length20 + dq->fd.offset; -+ -+ if (fd_len > fm_get_max_frm()) { -+ _fmt_err("pcd dqrr wrong frame size: %u (%u:%u)!\n", -+ fd_len, dq->fd.length20, dq->fd.offset); -+ goto _fmt_pcd_dqrr_return; -+ } -+ -+ dpa_bp = dpa_bpid2pool(dq->fd.bpid); -+ dma_unmap_single(dpa_bp->dev, addr, dpa_bp->size, DMA_BIDIRECTIONAL); -+ -+ fd_virt_addr = phys_to_virt(addr); -+ if (!test_and_steal_frame(fmt_port, relative_fqid, fd_virt_addr, -+ fd_len)) { -+ -+#if defined(FMT_K_DBG) || defined(FMT_K_DBG_RUNTIME) -+ atomic_inc(&fmt_port->not_enqueue_to_rxq_wrong_frm); -+#endif -+ _fmt_wrn("pcd dqrr unrecognized frame@fqid: %u," -+ " frame len: %u (dropped).\n", -+ dq->fqid, dq->fd.length20); -+ dump_frame(fd_virt_addr, fd_len); -+ } -+ -+_fmt_pcd_dqrr_return: -+ /* no need to map again here */ -+ fmt_fq_release(&dq->fd); -+ -+ _fmt_dbgr("calle.\n"); -+ return qman_cb_dqrr_consume; -+} -+ -+static void fmt_pcd_err_dqrr( -+ struct qman_portal *qm, -+ struct qman_fq *fq, -+ const struct qm_mr_entry *msg) -+{ -+ _fmt_err("this callback should never be called.\n"); -+ BUG(); -+ return; -+} -+ -+static void fmt_pcd_fqs_dqrr( -+ struct qman_portal *qm, -+ struct qman_fq *fq, -+ const struct qm_mr_entry *msg) -+{ -+ _fmt_dbg(" fq state(0x%x)@fqid(%u.\n", msg->fq.fqs, msg->fq.fqid); -+ return; -+} -+ -+/* private pcd queue template */ -+static const struct qman_fq pcd_fq = { -+ .cb = { .dqrr = fmt_pcd_dqrr, -+ .ern = fmt_pcd_err_dqrr, -+ .fqs = fmt_pcd_fqs_dqrr} -+}; -+ -+/* defined as weak in dpaa driver. */ -+/* ! parameters come from IOCTL call - US */ -+int dpa_alloc_pcd_fqids( -+ struct device *dev, -+ uint32_t num, uint8_t alignment, -+ uint32_t *base_fqid) -+{ -+ int _err = 0, i; -+ struct net_device *net_dev = NULL; -+ struct dpa_priv_s *dpa_priv = NULL; -+ struct fmt_port_pcd_s *fmt_port_pcd = NULL; -+ struct fmt_fqs_s *fmt_fqs = NULL; -+ struct fmt_port_s *fmt_port = NULL; -+ int num_allocated = 0; -+ -+ _fmt_dbg("calling...\n"); -+ -+ net_dev = (typeof(net_dev))dev_get_drvdata(dev); -+ dpa_priv = (typeof(dpa_priv))netdev_priv(net_dev); -+ -+ if (!netif_msg_probe(dpa_priv)) { -+ _fmt_err("dpa not probe.\n"); -+ _err = -ENODEV; -+ goto _pcd_alloc_fqs_err; -+ } -+ -+ fmt_port = match_dpa_to_fmt_port(dpa_priv); -+ if (!fmt_port) { -+ _fmt_err("fmt port not found."); -+ _err = -EINVAL; -+ goto _pcd_alloc_fqs_err; -+ } -+ -+ fmt_port_pcd = &fmt_port->fmt_port_pcd; -+ -+ num_allocated = qman_alloc_fqid_range(base_fqid, num, alignment, 0); -+ -+ if ((num_allocated <= 0) || -+ (num_allocated < num) || -+ (alignment && (*base_fqid) % alignment)) { -+ *base_fqid = 0; -+ _fmt_err("Failed to alloc pcd fqs rang.\n"); -+ _err = -EINVAL; -+ goto _pcd_alloc_fqs_err; -+ } -+ -+ _fmt_dbg("wanted %d fqs(align %d), got %d fqids@%u.\n", -+ num, alignment, num_allocated, *base_fqid); -+ -+ /* alloc pcd queues */ -+ fmt_port_pcd->fmt_pcd_fqs = kmalloc(num_allocated * -+ sizeof(struct fmt_fqs_s), -+ GFP_KERNEL); -+ fmt_port_pcd->num_queues = num_allocated; -+ fmt_port_pcd->fqid_base = *base_fqid; -+ fmt_fqs = fmt_port_pcd->fmt_pcd_fqs; -+ -+ /* alloc the pcd queues */ -+ for (i = 0; i < num_allocated; i++, fmt_fqs++) { -+ _err = fmt_fq_alloc( -+ fmt_fqs, -+ &pcd_fq, -+ (*base_fqid) + i, QMAN_FQ_FLAG_NO_ENQUEUE, -+ dpa_priv->channel, 7); -+ -+ if (_err < 0) -+ goto _pcd_alloc_fqs_err; -+ -+ /* upcast to identify from where the frames came from */ -+ fmt_fqs->fmt_port_priv = fmt_port; -+ } -+ -+ _fmt_dbg("called.\n"); -+ return _err; -+_pcd_alloc_fqs_err: -+ if (num_allocated > 0) -+ qman_release_fqid_range(*base_fqid, num_allocated); -+ /*TODO: free fmt_pcd_fqs if are any */ -+ -+ _fmt_dbg("called(_err:%d).\n", _err); -+ return _err; -+} -+ -+/* defined as weak in dpaa driver. */ -+int dpa_free_pcd_fqids( -+ struct device *dev, -+ uint32_t base_fqid) -+{ -+ -+ int _err = 0, i; -+ struct net_device *net_dev = NULL; -+ struct dpa_priv_s *dpa_priv = NULL; -+ struct fmt_port_pcd_s *fmt_port_pcd = NULL; -+ struct fmt_fqs_s *fmt_fqs = NULL; -+ struct fmt_port_s *fmt_port = NULL; -+ int num_allocated = 0; -+ -+ _fmt_dbg("calling...\n"); -+ -+ net_dev = (typeof(net_dev))dev_get_drvdata(dev); -+ dpa_priv = (typeof(dpa_priv))netdev_priv(net_dev); -+ -+ if (!netif_msg_probe(dpa_priv)) { -+ _fmt_err("dpa not probe.\n"); -+ _err = -ENODEV; -+ goto _pcd_free_fqs_err; -+ } -+ -+ fmt_port = match_dpa_to_fmt_port(dpa_priv); -+ if (!fmt_port) { -+ _fmt_err("fmt port not found."); -+ _err = -EINVAL; -+ goto _pcd_free_fqs_err; -+ } -+ -+ fmt_port_pcd = &fmt_port->fmt_port_pcd; -+ num_allocated = fmt_port_pcd->num_queues; -+ fmt_fqs = fmt_port_pcd->fmt_pcd_fqs; -+ -+ for (i = 0; i < num_allocated; i++, fmt_fqs++) -+ fmt_fq_free(fmt_fqs); -+ -+ qman_release_fqid_range(base_fqid,num_allocated); -+ -+ kfree(fmt_port_pcd->fmt_pcd_fqs); -+ memset(fmt_port_pcd, 0, sizeof(*fmt_port_pcd)); -+ -+ /* debugging stuff */ -+#if defined(FMT_K_DBG) || defined(FMT_K_DBG_RUNTIME) -+ _fmt_dbg(" portid: %u.\n", fmt_port->id); -+ _fmt_dbg(" frames enqueue to qman: %u.\n", -+ atomic_read(&fmt_port->enqueue_to_qman_frm)); -+ _fmt_dbg(" frames enqueue to rxq: %u.\n", -+ atomic_read(&fmt_port->enqueue_to_rxq)); -+ _fmt_dbg(" frames dequeue from rxq: %u.\n", -+ atomic_read(&fmt_port->dequeue_from_rxq)); -+ _fmt_dbg(" frames not enqueue to rxq - wrong frm: %u.\n", -+ atomic_read(&fmt_port->not_enqueue_to_rxq_wrong_frm)); -+ atomic_set(&fmt_port->enqueue_to_qman_frm, 0); -+ atomic_set(&fmt_port->enqueue_to_rxq, 0); -+ atomic_set(&fmt_port->dequeue_from_rxq, 0); -+ atomic_set(&fmt_port->not_enqueue_to_rxq_wrong_frm, 0); -+#endif -+ return 0; -+ -+_pcd_free_fqs_err: -+ return _err; -+} -+ -+static int fmt_port_init( -+ struct fmt_port_s *fmt_port, -+ ioc_fmt_port_param_t *p_Params) -+{ -+ struct device_node *fm_node, *fm_port_node; -+ const uint32_t *uint32_prop; -+ int _errno = 0, lenp = 0, i; -+ static struct of_device_id fm_node_of_match[] = { -+ { .compatible = "fsl,fman", }, -+ { /* end of list */ }, -+ }; -+ -+ _fmt_dbg("calling...\n"); -+ -+ /* init send/receive tu US list */ -+ INIT_LIST_HEAD(&fmt_port->rx_q); -+ -+ /* check parameters */ -+ if (p_Params->num_tx_queues > FMAN_TEST_MAX_TX_FQS || -+ p_Params->fm_port_id > IOC_FMT_MAX_NUM_OF_PORTS) { -+ _fmt_dbg("wrong test parameters.\n"); -+ return -EINVAL; -+ } -+ -+ /* set port parameters */ -+ fmt_port->num_of_tx_fqs = p_Params->num_tx_queues; -+ fmt_port->id = p_Params->fm_port_id; -+ fmt_port->port_type = p_Params->fm_port_type; -+ fmt_port->diag = e_IOC_DIAG_MODE_NONE; -+ -+ /* init debugging stuff */ -+#if defined(FMT_K_DBG) || defined(FMT_K_DBG_RUNTIME) -+ atomic_set(&fmt_port->enqueue_to_qman_frm, 0); -+ atomic_set(&fmt_port->enqueue_to_rxq, 0); -+ atomic_set(&fmt_port->dequeue_from_rxq, 0); -+ atomic_set(&fmt_port->not_enqueue_to_rxq_wrong_frm, 0); -+#endif -+ -+ /* TODO: This should be done at probe time not at runtime -+ * very ugly function */ -+ /* fill fmt port properties from dts */ -+ for_each_matching_node(fm_node, fm_node_of_match) { -+ -+ uint32_prop = (uint32_t *)of_get_property(fm_node, -+ "cell-index", &lenp); -+ if (unlikely(uint32_prop == NULL)) { -+ _fmt_wrn("of_get_property(%s, cell-index) invalid", -+ fm_node->full_name); -+ return -EINVAL; -+ } -+ if (WARN_ON(lenp != sizeof(uint32_t))) { -+ _fmt_wrn("of_get_property(%s, cell-index) invalid", -+ fm_node->full_name); -+ return -EINVAL; -+ } -+ -+ if (*uint32_prop == p_Params->fm_id) { -+ struct resource res; -+ -+ /* Get the FM address */ -+ _errno = of_address_to_resource(fm_node, 0, &res); -+ if (unlikely(_errno < 0)) { -+ _fmt_wrn("of_address_to_resource() = %u.\n", _errno); -+ return -EINVAL; -+ } -+ -+ fmt_port->fm_phys_base_addr = res.start; -+ -+ for_each_child_of_node(fm_node, fm_port_node) { -+ struct platform_device *of_dev; -+ -+ if (!of_device_is_available(fm_port_node)) -+ continue; -+ -+ uint32_prop = (uint32_t *)of_get_property( -+ fm_port_node, -+ "cell-index", -+ &lenp); -+ if (uint32_prop == NULL) -+ continue; -+ -+ if (of_device_is_compatible(fm_port_node, -+ "fsl,fman-port-oh") && -+ (fmt_port->port_type == e_IOC_FMT_PORT_T_OP)) { -+ -+ if (*uint32_prop == fmt_port->id) { -+ of_dev = of_find_device_by_node(fm_port_node); -+ if (unlikely(of_dev == NULL)) { -+ _fmt_wrn("fm id invalid\n"); -+ return -EINVAL; -+ } -+ -+ fmt_port->p_tx_port = -+ fm_port_bind(&of_dev->dev); -+ fmt_port->p_tx_fm_port_dev = -+ (void *)fm_port_get_handle( -+ fmt_port->p_tx_port); -+ fmt_port->p_rx_port = -+ fmt_port->p_tx_port; -+ fmt_port->p_rx_fm_port_dev = -+ fmt_port->p_tx_fm_port_dev; -+ fmt_port->p_mac_dev = NULL; -+ break; -+ } -+ } else if ((*uint32_prop == fmt_port->id) && -+ fmt_port->port_type == e_IOC_FMT_PORT_T_RXTX) { -+ -+ of_dev = of_find_device_by_node(fm_port_node); -+ if (unlikely(of_dev == NULL)) { -+ _fmt_wrn("dtb fm id invalid value"); -+ return -EINVAL; -+ } -+ -+ if (of_device_is_compatible(fm_port_node, -+ "fsl,fman-port-1g-tx")) { -+ fmt_port->p_tx_port = -+ fm_port_bind(&of_dev->dev); -+ fmt_port->p_tx_fm_port_dev = (void *) -+ fm_port_get_handle( -+ fmt_port->p_tx_port); -+ } else if (of_device_is_compatible(fm_port_node, -+ "fsl,fman-port-1g-rx")) { -+ fmt_port->p_rx_port = -+ fm_port_bind(&of_dev->dev); -+ fmt_port->p_rx_fm_port_dev = (void *) -+ fm_port_get_handle( -+ fmt_port->p_rx_port); -+ } else if (of_device_is_compatible(fm_port_node, -+ "fsl,fman-1g-mac") || -+ of_device_is_compatible(fm_port_node, -+ "fsl,fman-memac")) -+ fmt_port->p_mac_dev = -+ (typeof(fmt_port->p_mac_dev)) -+ dev_get_drvdata(&of_dev->dev); -+ else -+ continue; -+ -+ if (fmt_port->p_tx_fm_port_dev && -+ fmt_port->p_rx_fm_port_dev && fmt_port->p_mac_dev) -+ break; -+ } else if (((*uint32_prop + FM_MAX_NUM_OF_1G_RX_PORTS) == -+ fmt_port->id) && -+ fmt_port->port_type == e_IOC_FMT_PORT_T_RXTX) { -+ -+ of_dev = of_find_device_by_node(fm_port_node); -+ if (unlikely(of_dev == NULL)) { -+ _fmt_wrn("dtb fm id invalid value\n"); -+ return -EINVAL; -+ } -+ -+ if (of_device_is_compatible(fm_port_node, -+ "fsl,fman-port-10g-tx")) { -+ fmt_port->p_tx_port = -+ fm_port_bind(&of_dev->dev); -+ fmt_port->p_tx_fm_port_dev = (void *) -+ fm_port_get_handle( -+ fmt_port->p_tx_port); -+ } else if (of_device_is_compatible(fm_port_node, -+ "fsl,fman-port-10g-rx")) { -+ fmt_port->p_rx_port = -+ fm_port_bind(&of_dev->dev); -+ fmt_port->p_rx_fm_port_dev = (void *) -+ fm_port_get_handle( -+ fmt_port->p_rx_port); -+ } else if (of_device_is_compatible(fm_port_node, -+ "fsl,fman-10g-mac") || -+ of_device_is_compatible(fm_port_node, -+ "fsl,fman-memac")) -+ fmt_port->p_mac_dev = -+ (typeof(fmt_port->p_mac_dev)) -+ dev_get_drvdata(&of_dev->dev); -+ else -+ continue; -+ -+ if (fmt_port->p_tx_fm_port_dev && -+ fmt_port->p_rx_fm_port_dev && fmt_port->p_mac_dev) -+ break; -+ } -+ } /* for_each_child */ -+ } -+ } /* for each matching node */ -+ -+ if (fmt_port->p_tx_fm_port_dev == 0 || -+ fmt_port->p_rx_fm_port_dev == 0) { -+ -+ _fmt_err("bad fm port pointers.\n"); -+ return -EINVAL; -+ } -+ -+ _fmt_dbg("alloc %u tx queues.\n", fmt_port->num_of_tx_fqs); -+ -+ /* init fman test egress dynamic frame queues */ -+ for (i = 0; i < fmt_port->num_of_tx_fqs; i++) { -+ int _errno; -+ _errno = fmt_fq_alloc( -+ &fmt_port->p_tx_fqs[i], -+ &fmt_egress_fq, -+ 0, -+ QMAN_FQ_FLAG_TO_DCPORTAL, -+ fm_get_tx_port_channel(fmt_port->p_tx_port), -+ i); -+ -+ if (_errno < 0) { -+ _fmt_err("tx queues allocation failed.\n"); -+ /* TODO: memory leak here if 1 queue is allocated and -+ * next queues are failing ... */ -+ return -EINVAL; -+ } -+ } -+ -+ /* port is valid and ready to use. */ -+ fmt_port->valid = TRUE; -+ -+ _fmt_dbg("called.\n"); -+ return 0; -+} -+ -+/* fm test chardev functions */ -+static int fmt_open(struct inode *inode, struct file *file) -+{ -+ unsigned int minor = iminor(inode); -+ -+ _fmt_dbg("calling...\n"); -+ -+ if (file->private_data != NULL) -+ return 0; -+ -+ /* The minor represent the port number. -+ * Set the port structure accordingly, thus all the operations -+ * will be done on this port. */ -+ if ((minor >= DEV_FM_TEST_PORTS_MINOR_BASE) && -+ (minor < DEV_FM_TEST_MAX_MINORS)) -+ file->private_data = &fm_test.ports[minor]; -+ else -+ return -ENXIO; -+ -+ _fmt_dbg("called.\n"); -+ return 0; -+} -+ -+static int fmt_close(struct inode *inode, struct file *file) -+{ -+ struct fmt_port_s *fmt_port = NULL; -+ struct fmt_frame_s *fmt_frame = NULL; -+ -+ int err = 0; -+ -+ _fmt_dbg("calling...\n"); -+ -+ fmt_port = file->private_data; -+ if (!fmt_port) -+ return -ENODEV; -+ -+ /* Close the current test port by invalidating it. */ -+ fmt_port->valid = FALSE; -+ -+ /* clean the fmt port queue */ -+ while ((fmt_frame = dequeue_fmt_frame(fmt_port)) != NULL) { -+ if (fmt_frame && fmt_frame->buff.p_data){ -+ kfree(fmt_frame->buff.p_data); -+ kfree(fmt_frame); -+ } -+ } -+ -+ /* !!! the qman queues are cleaning from fm_ioctl... -+ * - very ugly */ -+ -+ _fmt_dbg("called.\n"); -+ return err; -+} -+ -+static int fmt_ioctls(unsigned int minor, -+ struct file *file, -+ unsigned int cmd, -+ unsigned long arg, -+ bool compat) -+{ -+ struct fmt_port_s *fmt_port = NULL; -+ -+ _fmt_dbg("IOCTL minor:%u " -+ " arg:0x%08lx ioctl cmd (0x%08x):(0x%02x:0x%02x.\n", -+ minor, arg, cmd, _IOC_TYPE(cmd), _IOC_NR(cmd)); -+ -+ fmt_port = file->private_data; -+ if (!fmt_port) { -+ _fmt_err("invalid fmt port.\n"); -+ return -ENODEV; -+ } -+ -+ /* set test type properly */ -+ if (compat) -+ fmt_port->compat_test_type = true; -+ else -+ fmt_port->compat_test_type = false; -+ -+ switch (cmd) { -+ case FMT_PORT_IOC_INIT: -+ { -+ ioc_fmt_port_param_t param; -+ -+ if (fmt_port->valid) { -+ _fmt_wrn("port is already initialized.\n"); -+ return -EFAULT; -+ } -+#if defined(CONFIG_COMPAT) -+ if (compat) { -+ if (copy_from_user(¶m, -+ (ioc_fmt_port_param_t *)compat_ptr(arg), -+ sizeof(ioc_fmt_port_param_t))) -+ -+ return -EFAULT; -+ } else -+#endif -+ { -+ if (copy_from_user(¶m, -+ (ioc_fmt_port_param_t *) arg, -+ sizeof(ioc_fmt_port_param_t))) -+ -+ return -EFAULT; -+ } -+ -+ return fmt_port_init(fmt_port, ¶m); -+ } -+ -+ case FMT_PORT_IOC_SET_DIAG_MODE: -+ if (get_user(fmt_port->diag, (ioc_diag_mode *)arg)) -+ return -EFAULT; -+ -+ if (fmt_port->diag == e_IOC_DIAG_MODE_CTRL_LOOPBACK) -+ return set_mac_int_loopback(fmt_port, TRUE); -+ else -+ return set_mac_int_loopback(fmt_port, FALSE); -+ break; -+ -+ case FMT_PORT_IOC_SET_DPAECHO_MODE: -+ case FMT_PORT_IOC_SET_IP_HEADER_MANIP: -+ default: -+ _fmt_wrn("ioctl unimplemented minor:%u@ioctl" -+ " cmd:0x%08x(type:0x%02x, nr:0x%02x.\n", -+ minor, cmd, _IOC_TYPE(cmd), _IOC_NR(cmd)); -+ return -EFAULT; -+ } -+ -+ return 0; -+} -+ -+#ifdef CONFIG_COMPAT -+static long fmt_compat_ioctl( -+ struct file *file, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ unsigned int minor = iminor(file->f_path.dentry->d_inode); -+ -+ _fmt_dbg("calling...\n"); -+ return fmt_ioctls(minor, file, cmd, arg, true); -+} -+#endif -+ -+static long fmt_ioctl( -+ struct file *file, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ unsigned int minor = iminor(file->f_path.dentry->d_inode); -+ unsigned int res; -+ -+ _fmt_dbg("calling...\n"); -+ -+ fm_mutex_lock(); -+ res = fmt_ioctls(minor, file, cmd, arg, false); -+ fm_mutex_unlock(); -+ -+ _fmt_dbg("called.\n"); -+ -+ return res; -+} -+ -+#ifdef CONFIG_COMPAT -+void copy_compat_test_frame_buffer( -+ ioc_fmt_buff_desc_t *buff, -+ ioc_fmt_compat_buff_desc_t *compat_buff) -+{ -+ compat_buff->qid = buff->qid; -+ compat_buff->p_data = ptr_to_compat(buff->p_data); -+ compat_buff->size = buff->size; -+ compat_buff->status = buff->status; -+ -+ compat_buff->buff_context.p_user_priv = -+ ptr_to_compat(buff->buff_context.p_user_priv); -+ memcpy(compat_buff->buff_context.fm_prs_res, -+ buff->buff_context.fm_prs_res, -+ FM_PRS_MAX * sizeof(uint8_t)); -+ memcpy(compat_buff->buff_context.fm_time_stamp, -+ buff->buff_context.fm_time_stamp, -+ FM_TIME_STAMP_MAX * sizeof(uint8_t)); -+} -+#endif -+ -+ssize_t fmt_read( -+ struct file *file, -+ char __user *buf, -+ size_t size, -+ loff_t *ppos) -+{ -+ struct fmt_port_s *fmt_port = NULL; -+ struct fmt_frame_s *p_fmt_frame = NULL; -+ ssize_t cnt = 0; -+ -+ fmt_port = file->private_data; -+ if (!fmt_port || !fmt_port->valid) { -+ _fmt_err("fmt port not valid!\n"); -+ return -ENODEV; -+ } -+ -+ p_fmt_frame = dequeue_fmt_frame(fmt_port); -+ if (p_fmt_frame == NULL) -+ return 0; -+ -+ _fmt_dbgr("calling...\n"); -+ -+#ifdef CONFIG_COMPAT -+ if (fmt_port->compat_test_type){ -+ cnt = sizeof(ioc_fmt_compat_buff_desc_t); -+ } -+ else -+#endif -+ { -+ cnt = sizeof(ioc_fmt_buff_desc_t); -+ } -+ -+ if (size < cnt) { -+ _fmt_err("illegal buffer-size!\n"); -+ cnt = 0; -+ goto _fmt_read_return; -+ } -+ -+ /* Copy structure */ -+#ifdef CONFIG_COMPAT -+ if (fmt_port->compat_test_type) { -+ { -+ ioc_fmt_compat_buff_desc_t compat_buff; -+ copy_compat_test_frame_buffer(&p_fmt_frame->buff, -+ &compat_buff); -+ -+ if (copy_to_user(buf, &compat_buff, cnt)) { -+ _fmt_err("copy_to_user failed!\n"); -+ goto _fmt_read_return; -+ } -+ } -+ -+ ((ioc_fmt_compat_buff_desc_t *)buf)->p_data = -+ ptr_to_compat(buf+sizeof(ioc_fmt_compat_buff_desc_t)); -+ cnt += MIN(p_fmt_frame->buff.size, size-cnt); -+ } else -+#endif -+ { -+ if (copy_to_user(buf, &p_fmt_frame->buff, cnt)) { -+ _fmt_err("copy_to_user failed!\n"); -+ goto _fmt_read_return; -+ } -+ -+ ((ioc_fmt_buff_desc_t *)buf)->p_data = -+ buf + sizeof(ioc_fmt_buff_desc_t); -+ cnt += MIN(p_fmt_frame->buff.size, size-cnt); -+ } -+ -+ if (size < cnt) { -+ _fmt_err("illegal buffer-size!\n"); -+ goto _fmt_read_return; -+ } -+ -+ /* copy frame */ -+#ifdef CONFIG_COMPAT -+ if (fmt_port->compat_test_type) { -+ if (copy_to_user(buf+sizeof(ioc_fmt_compat_buff_desc_t), -+ p_fmt_frame->buff.p_data, cnt)) { -+ _fmt_err("copy_to_user failed!\n"); -+ goto _fmt_read_return; -+ } -+ } else -+#endif -+ { -+ if (copy_to_user(buf+sizeof(ioc_fmt_buff_desc_t), -+ p_fmt_frame->buff.p_data, cnt)) { -+ _fmt_err("copy_to_user failed!\n"); -+ goto _fmt_read_return; -+ } -+ } -+ -+_fmt_read_return: -+ kfree(p_fmt_frame->buff.p_data); -+ kfree(p_fmt_frame); -+ -+ _fmt_dbgr("called.\n"); -+ return cnt; -+} -+ -+ssize_t fmt_write( -+ struct file *file, -+ const char __user *buf, -+ size_t size, -+ loff_t *ppos) -+{ -+ struct fmt_port_s *fmt_port = NULL; -+ ioc_fmt_buff_desc_t buff_desc; -+#ifdef CONFIG_COMPAT -+ ioc_fmt_compat_buff_desc_t buff_desc_compat; -+#endif -+ uint8_t *p_data = NULL; -+ uint32_t data_offset; -+ int _errno; -+ t_DpaaFD fd; -+ -+ _fmt_dbgr("calling...\n"); -+ -+ fmt_port = file->private_data; -+ if (!fmt_port || !fmt_port->valid) { -+ _fmt_err("fmt port not valid.\n"); -+ return -EINVAL; -+ } -+ -+ /* If Compat (32B UserSpace - 64B KernelSpace) */ -+#ifdef CONFIG_COMPAT -+ if (fmt_port->compat_test_type) { -+ if (size < sizeof(ioc_fmt_compat_buff_desc_t)) { -+ _fmt_err("invalid buff_desc size.\n"); -+ return -EFAULT; -+ } -+ -+ if (copy_from_user(&buff_desc_compat, buf, -+ sizeof(ioc_fmt_compat_buff_desc_t))) -+ return -EFAULT; -+ -+ buff_desc.qid = buff_desc_compat.qid; -+ buff_desc.p_data = compat_ptr(buff_desc_compat.p_data); -+ buff_desc.size = buff_desc_compat.size; -+ buff_desc.status = buff_desc_compat.status; -+ -+ buff_desc.buff_context.p_user_priv = -+ compat_ptr(buff_desc_compat.buff_context.p_user_priv); -+ memcpy(buff_desc.buff_context.fm_prs_res, -+ buff_desc_compat.buff_context.fm_prs_res, -+ FM_PRS_MAX * sizeof(uint8_t)); -+ memcpy(buff_desc.buff_context.fm_time_stamp, -+ buff_desc_compat.buff_context.fm_time_stamp, -+ FM_TIME_STAMP_MAX * sizeof(uint8_t)); -+ } else -+#endif -+ { -+ if (size < sizeof(ioc_fmt_buff_desc_t)) { -+ _fmt_err("invalid buff_desc size.\n"); -+ return -EFAULT; -+ } -+ -+ if (copy_from_user(&buff_desc, (ioc_fmt_buff_desc_t *)buf, -+ sizeof(ioc_fmt_buff_desc_t))) -+ return -EFAULT; -+ } -+ -+ data_offset = FM_PORT_GetBufferDataOffset(fmt_port->p_tx_fm_port_dev); -+ p_data = kmalloc(buff_desc.size+data_offset, GFP_KERNEL); -+ if (!p_data) -+ return -ENOMEM; -+ -+ /* If Compat (32UserSpace - 64KernelSpace) the buff_desc.p_data is ok */ -+ if (copy_from_user((uint8_t *)PTR_MOVE(p_data, data_offset), -+ buff_desc.p_data, -+ buff_desc.size)) { -+ kfree(p_data); -+ return -EFAULT; -+ } -+ -+ /* TODO: dma_map_single here (cannot access the bpool struct) */ -+ -+ /* prepare fd */ -+ memset(&fd, 0, sizeof(fd)); -+ DPAA_FD_SET_ADDR(&fd, p_data); -+ DPAA_FD_SET_OFFSET(&fd, data_offset); -+ DPAA_FD_SET_LENGTH(&fd, buff_desc.size); -+ -+ _errno = qman_enqueue(&fmt_port->p_tx_fqs[buff_desc.qid].fq_base, -+ (struct qm_fd *)&fd, 0); -+ if (_errno) { -+ buff_desc.status = (uint32_t)_errno; -+ if (copy_to_user((ioc_fmt_buff_desc_t *)buf, &buff_desc, -+ sizeof(ioc_fmt_buff_desc_t))) { -+ kfree(p_data); -+ return -EFAULT; -+ } -+ } -+ -+ /* for debugging */ -+#if defined(FMT_K_DBG) || defined(FMT_K_DBG_RUNTIME) -+ atomic_inc(&fmt_port->enqueue_to_qman_frm); -+#endif -+ _fmt_dbgr("called.\n"); -+ return buff_desc.size; -+} -+ -+/* fm test character device definition */ -+static const struct file_operations fmt_fops = -+{ -+ .owner = THIS_MODULE, -+#ifdef CONFIG_COMPAT -+ .compat_ioctl = fmt_compat_ioctl, -+#endif -+ .unlocked_ioctl = fmt_ioctl, -+ .open = fmt_open, -+ .release = fmt_close, -+ .read = fmt_read, -+ .write = fmt_write, -+}; -+ -+static int fmt_init(void) -+{ -+ int id; -+ -+ _fmt_dbg("calling...\n"); -+ -+ /* Register to the /dev for IOCTL API */ -+ /* Register dynamically a new major number for the character device: */ -+ fm_test.major = register_chrdev(0, DEV_FM_TEST_NAME, &fmt_fops); -+ if (fm_test.major <= 0) { -+ _fmt_wrn("Failed to allocate major number for device %s.\n", -+ DEV_FM_TEST_NAME); -+ return -ENODEV; -+ } -+ -+ /* Creating class for FMan_test */ -+ fm_test.fmt_class = class_create(THIS_MODULE, DEV_FM_TEST_NAME); -+ if (IS_ERR(fm_test.fmt_class)) { -+ unregister_chrdev(fm_test.major, DEV_FM_TEST_NAME); -+ _fmt_wrn("Error creating %s class.\n", DEV_FM_TEST_NAME); -+ return -ENODEV; -+ } -+ -+ for (id = 0; id < IOC_FMT_MAX_NUM_OF_PORTS; id++) -+ if (NULL == device_create(fm_test.fmt_class, NULL, -+ MKDEV(fm_test.major, -+ DEV_FM_TEST_PORTS_MINOR_BASE + id), NULL, -+ DEV_FM_TEST_NAME "%d", id)) { -+ -+ _fmt_err("Error creating %s device.\n", -+ DEV_FM_TEST_NAME); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+static void fmt_free(void) -+{ -+ int id; -+ -+ for (id = 0; id < IOC_FMT_MAX_NUM_OF_PORTS; id++) -+ device_destroy(fm_test.fmt_class, MKDEV(fm_test.major, -+ DEV_FM_TEST_PORTS_MINOR_BASE + id)); -+ class_destroy(fm_test.fmt_class); -+} -+ -+static int __init __cold fmt_load(void) -+{ -+ struct dpaa_eth_hooks_s priv_dpaa_eth_hooks; -+ -+ /* set dpaa hooks for default queues */ -+ memset(&priv_dpaa_eth_hooks, 0, sizeof(priv_dpaa_eth_hooks)); -+ priv_dpaa_eth_hooks.rx_default = fmt_rx_default_hook; -+ priv_dpaa_eth_hooks.rx_error = fmt_rx_error_hook; -+ priv_dpaa_eth_hooks.tx_confirm = fmt_tx_confirm_hook; -+ priv_dpaa_eth_hooks.tx_error = fmt_tx_confirm_error_hook; -+ -+ fsl_dpaa_eth_set_hooks(&priv_dpaa_eth_hooks); -+ -+ /* initialize the fman test environment */ -+ if (fmt_init() < 0) { -+ _fmt_err("Failed to init FM-test modul.\n"); -+ fmt_free(); -+ return -ENODEV; -+ } -+ -+ _fmt_inf("FSL FM test module loaded.\n"); -+ -+ return 0; -+} -+ -+static void __exit __cold fmt_unload(void) -+{ -+ fmt_free(); -+ _fmt_inf("FSL FM test module unloaded.\n"); -+} -+ -+module_init(fmt_load); -+module_exit(fmt_unload); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_fm.c -@@ -0,0 +1,2795 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ @File lnxwrp_fm.c -+ @Author Shlomi Gridish -+ @Description FM Linux wrapper functions. -+*/ -+ -+#include -+#include -+#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS) -+#define MODVERSIONS -+#endif -+#ifdef MODVERSIONS -+#include -+#endif /* MODVERSIONS */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include /* For struct qe_firmware */ -+#ifndef CONFIG_FMAN_ARM -+#include -+#include -+#endif -+#include /* For file access mask */ -+#include -+#include -+ -+/* NetCommSw Headers --------------- */ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "sprint_ext.h" -+#include "debug_ext.h" -+#include "sys_io_ext.h" -+ -+#include "fm_ioctls.h" -+ -+#include "lnxwrp_fm.h" -+#include "lnxwrp_resources.h" -+#include "lnxwrp_sysfs_fm.h" -+#include "lnxwrp_sysfs_fm_port.h" -+#include "lnxwrp_exp_sym.h" -+#include "fm_common.h" -+#include "../../sdk_fman/Peripherals/FM/fm.h" -+#define __ERR_MODULE__ MODULE_FM -+ -+extern struct device_node *GetFmPortAdvArgsDevTreeNode (struct device_node *fm_node, -+ e_FmPortType portType, -+ uint8_t portId); -+ -+#define PROC_PRINT(args...) offset += sprintf(buf+offset,args) -+ -+#define ADD_ADV_CONFIG_NO_RET(_func, _param) \ -+ do { \ -+ if (ip_Function = _func; \ -+ _param \ -+ i++; \ -+ } \ -+ else \ -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE,\ -+ ("Number of advanced-configuration entries exceeded"));\ -+ } while (0) -+ -+/* Bootarg used to override the Kconfig FSL_FM_MAX_FRAME_SIZE value */ -+#define FSL_FM_MAX_FRM_BOOTARG "fsl_fm_max_frm" -+ -+/* Bootarg used to override FSL_FM_RX_EXTRA_HEADROOM Kconfig value */ -+#define FSL_FM_RX_EXTRA_HEADROOM_BOOTARG "fsl_fm_rx_extra_headroom" -+ -+/* Minimum and maximum value for the fsl_fm_rx_extra_headroom bootarg */ -+#define FSL_FM_RX_EXTRA_HEADROOM_MIN 16 -+#define FSL_FM_RX_EXTRA_HEADROOM_MAX 384 -+ -+#define FSL_FM_PAUSE_TIME_ENABLE 0xf000 -+#define FSL_FM_PAUSE_TIME_DISABLE 0 -+#define FSL_FM_PAUSE_THRESH_DEFAULT 0 -+ -+/* -+ * Max frame size, across all interfaces. -+ * Configurable from Kconfig or bootargs, to avoid allocating -+ * oversized (socket) buffers when not using jumbo frames. -+ * Must be large enough to accommodate the network MTU, but small enough -+ * to avoid wasting skb memory. -+ * -+ * Could be overridden once, at boot-time, via the -+ * fm_set_max_frm() callback. -+ */ -+int fsl_fm_max_frm = CONFIG_FSL_FM_MAX_FRAME_SIZE; -+ -+/* -+ * Extra headroom for Rx buffers. -+ * FMan is instructed to allocate, on the Rx path, this amount of -+ * space at the beginning of a data buffer, beside the DPA private -+ * data area and the IC fields. -+ * Does not impact Tx buffer layout. -+ * -+ * Configurable from Kconfig or bootargs. Zero by default, it's needed -+ * on particular forwarding scenarios that add extra headers to the -+ * forwarded frame. -+ */ -+int fsl_fm_rx_extra_headroom = CONFIG_FSL_FM_RX_EXTRA_HEADROOM; -+ -+#ifdef CONFIG_FMAN_PFC -+static int fsl_fm_pfc_quanta[] = { -+ CONFIG_FMAN_PFC_QUANTA_0, -+ CONFIG_FMAN_PFC_QUANTA_1, -+ CONFIG_FMAN_PFC_QUANTA_2, -+ CONFIG_FMAN_PFC_QUANTA_3 -+}; -+#endif -+ -+static t_LnxWrpFm lnxWrpFm; -+ -+int fm_get_max_frm() -+{ -+ return fsl_fm_max_frm; -+} -+EXPORT_SYMBOL(fm_get_max_frm); -+ -+int fm_get_rx_extra_headroom() -+{ -+ return ALIGN(fsl_fm_rx_extra_headroom, 16); -+} -+EXPORT_SYMBOL(fm_get_rx_extra_headroom); -+ -+static int __init fm_set_max_frm(char *str) -+{ -+ int ret = 0; -+ -+ ret = get_option(&str, &fsl_fm_max_frm); -+ if (ret != 1) { -+ /* -+ * This will only work if CONFIG_EARLY_PRINTK is compiled in, -+ * and something like "earlyprintk=serial,uart0,115200" is -+ * specified in the bootargs -+ */ -+ printk(KERN_WARNING "No suitable %s= prop in bootargs; " -+ "will use the default FSL_FM_MAX_FRAME_SIZE (%d) " -+ "from Kconfig.\n", FSL_FM_MAX_FRM_BOOTARG, -+ CONFIG_FSL_FM_MAX_FRAME_SIZE); -+ -+ fsl_fm_max_frm = CONFIG_FSL_FM_MAX_FRAME_SIZE; -+ return 1; -+ } -+ -+ /* Don't allow invalid bootargs; fallback to the Kconfig value */ -+ if (fsl_fm_max_frm < 64 || fsl_fm_max_frm > 9600) { -+ printk(KERN_WARNING "Invalid %s=%d in bootargs, valid range is " -+ "64-9600. Falling back to the FSL_FM_MAX_FRAME_SIZE (%d) " -+ "from Kconfig.\n", -+ FSL_FM_MAX_FRM_BOOTARG, fsl_fm_max_frm, -+ CONFIG_FSL_FM_MAX_FRAME_SIZE); -+ -+ fsl_fm_max_frm = CONFIG_FSL_FM_MAX_FRAME_SIZE; -+ return 1; -+ } -+ -+ printk(KERN_INFO "Using fsl_fm_max_frm=%d from bootargs\n", -+ fsl_fm_max_frm); -+ return 0; -+} -+early_param(FSL_FM_MAX_FRM_BOOTARG, fm_set_max_frm); -+ -+static int __init fm_set_rx_extra_headroom(char *str) -+{ -+ int ret; -+ -+ ret = get_option(&str, &fsl_fm_rx_extra_headroom); -+ -+ if (ret != 1) { -+ printk(KERN_WARNING "No suitable %s= prop in bootargs; " -+ "will use the default FSL_FM_RX_EXTRA_HEADROOM (%d) " -+ "from Kconfig.\n", FSL_FM_RX_EXTRA_HEADROOM_BOOTARG, -+ CONFIG_FSL_FM_RX_EXTRA_HEADROOM); -+ fsl_fm_rx_extra_headroom = CONFIG_FSL_FM_RX_EXTRA_HEADROOM; -+ -+ return 1; -+ } -+ -+ if (fsl_fm_rx_extra_headroom < FSL_FM_RX_EXTRA_HEADROOM_MIN || -+ fsl_fm_rx_extra_headroom > FSL_FM_RX_EXTRA_HEADROOM_MAX) { -+ printk(KERN_WARNING "Invalid value for %s=%d prop in " -+ "bootargs; will use the default " -+ "FSL_FM_RX_EXTRA_HEADROOM (%d) from Kconfig.\n", -+ FSL_FM_RX_EXTRA_HEADROOM_BOOTARG, -+ fsl_fm_rx_extra_headroom, -+ CONFIG_FSL_FM_RX_EXTRA_HEADROOM); -+ fsl_fm_rx_extra_headroom = CONFIG_FSL_FM_RX_EXTRA_HEADROOM; -+ } -+ -+ printk(KERN_INFO "Using fsl_fm_rx_extra_headroom=%d from bootargs\n", -+ fsl_fm_rx_extra_headroom); -+ -+ return 0; -+} -+early_param(FSL_FM_RX_EXTRA_HEADROOM_BOOTARG, fm_set_rx_extra_headroom); -+ -+static irqreturn_t fm_irq(int irq, void *_dev) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = (t_LnxWrpFmDev *)_dev; -+#ifdef CONFIG_PM_SLEEP -+ t_Fm *p_Fm = (t_Fm*)p_LnxWrpFmDev->h_Dev; -+#endif -+ if (!p_LnxWrpFmDev || !p_LnxWrpFmDev->h_Dev) -+ return IRQ_NONE; -+ -+#ifdef CONFIG_PM_SLEEP -+ if (fman_get_normal_pending(p_Fm->p_FmFpmRegs) & INTR_EN_WAKEUP) -+ { -+ pm_wakeup_event(p_LnxWrpFmDev->dev, 200); -+ } -+#endif -+ FM_EventIsr(p_LnxWrpFmDev->h_Dev); -+ return IRQ_HANDLED; -+} -+ -+static irqreturn_t fm_err_irq(int irq, void *_dev) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = (t_LnxWrpFmDev *)_dev; -+ -+ if (!p_LnxWrpFmDev || !p_LnxWrpFmDev->h_Dev) -+ return IRQ_NONE; -+ -+ if (FM_ErrorIsr(p_LnxWrpFmDev->h_Dev) == E_OK) -+ return IRQ_HANDLED; -+ -+ return IRQ_NONE; -+} -+ -+/* used to protect FMD/LLD from concurrent calls in functions fm_mutex_lock / fm_mutex_unlock */ -+static struct mutex lnxwrp_mutex; -+ -+static t_LnxWrpFmDev * CreateFmDev(uint8_t id) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev; -+ int j; -+ -+ p_LnxWrpFmDev = (t_LnxWrpFmDev *)XX_Malloc(sizeof(t_LnxWrpFmDev)); -+ if (!p_LnxWrpFmDev) -+ { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ return NULL; -+ } -+ -+ memset(p_LnxWrpFmDev, 0, sizeof(t_LnxWrpFmDev)); -+ p_LnxWrpFmDev->fmDevSettings.advConfig = (t_SysObjectAdvConfigEntry*)XX_Malloc(FM_MAX_NUM_OF_ADV_SETTINGS*sizeof(t_SysObjectAdvConfigEntry)); -+ memset(p_LnxWrpFmDev->fmDevSettings.advConfig, 0, (FM_MAX_NUM_OF_ADV_SETTINGS*sizeof(t_SysObjectAdvConfigEntry))); -+ p_LnxWrpFmDev->fmPcdDevSettings.advConfig = (t_SysObjectAdvConfigEntry*)XX_Malloc(FM_MAX_NUM_OF_ADV_SETTINGS*sizeof(t_SysObjectAdvConfigEntry)); -+ memset(p_LnxWrpFmDev->fmPcdDevSettings.advConfig, 0, (FM_MAX_NUM_OF_ADV_SETTINGS*sizeof(t_SysObjectAdvConfigEntry))); -+ p_LnxWrpFmDev->hcPort.settings.advConfig = (t_SysObjectAdvConfigEntry*)XX_Malloc(FM_MAX_NUM_OF_ADV_SETTINGS*sizeof(t_SysObjectAdvConfigEntry)); -+ memset(p_LnxWrpFmDev->hcPort.settings.advConfig, 0, (FM_MAX_NUM_OF_ADV_SETTINGS*sizeof(t_SysObjectAdvConfigEntry))); -+ for (j=0; jrxPorts[j].settings.advConfig = (t_SysObjectAdvConfigEntry*)XX_Malloc(FM_MAX_NUM_OF_ADV_SETTINGS*sizeof(t_SysObjectAdvConfigEntry)); -+ memset(p_LnxWrpFmDev->rxPorts[j].settings.advConfig, 0, (FM_MAX_NUM_OF_ADV_SETTINGS*sizeof(t_SysObjectAdvConfigEntry))); -+ } -+ for (j=0; jtxPorts[j].settings.advConfig = (t_SysObjectAdvConfigEntry*)XX_Malloc(FM_MAX_NUM_OF_ADV_SETTINGS*sizeof(t_SysObjectAdvConfigEntry)); -+ memset(p_LnxWrpFmDev->txPorts[j].settings.advConfig, 0, (FM_MAX_NUM_OF_ADV_SETTINGS*sizeof(t_SysObjectAdvConfigEntry))); -+ } -+ for (j=0; jopPorts[j].settings.advConfig = (t_SysObjectAdvConfigEntry*)XX_Malloc(FM_MAX_NUM_OF_ADV_SETTINGS*sizeof(t_SysObjectAdvConfigEntry)); -+ memset(p_LnxWrpFmDev->opPorts[j].settings.advConfig, 0, (FM_MAX_NUM_OF_ADV_SETTINGS*sizeof(t_SysObjectAdvConfigEntry))); -+ } -+ -+ return p_LnxWrpFmDev; -+} -+ -+static void DestroyFmDev(t_LnxWrpFmDev *p_LnxWrpFmDev) -+{ -+ int j; -+ -+ for (j=0; jopPorts[j].settings.advConfig) -+ XX_Free(p_LnxWrpFmDev->opPorts[j].settings.advConfig); -+ for (j=0; jtxPorts[j].settings.advConfig) -+ XX_Free(p_LnxWrpFmDev->txPorts[j].settings.advConfig); -+ for (j=0; jrxPorts[j].settings.advConfig) -+ XX_Free(p_LnxWrpFmDev->rxPorts[j].settings.advConfig); -+ if (p_LnxWrpFmDev->hcPort.settings.advConfig) -+ XX_Free(p_LnxWrpFmDev->hcPort.settings.advConfig); -+ if (p_LnxWrpFmDev->fmPcdDevSettings.advConfig) -+ XX_Free(p_LnxWrpFmDev->fmPcdDevSettings.advConfig); -+ if (p_LnxWrpFmDev->fmDevSettings.advConfig) -+ XX_Free(p_LnxWrpFmDev->fmDevSettings.advConfig); -+ -+ XX_Free(p_LnxWrpFmDev); -+} -+ -+static t_Error FillRestFmInfo(t_LnxWrpFmDev *p_LnxWrpFmDev) -+{ -+#define FM_BMI_PPIDS_OFFSET 0x00080304 -+#define FM_DMA_PLR_OFFSET 0x000c2060 -+#define FM_FPM_IP_REV_1_OFFSET 0x000c30c4 -+#define DMA_HIGH_LIODN_MASK 0x0FFF0000 -+#define DMA_LOW_LIODN_MASK 0x00000FFF -+#define DMA_LIODN_SHIFT 16 -+ -+typedef _Packed struct { -+ uint32_t plr[32]; -+} _PackedType t_Plr; -+ -+typedef _Packed struct { -+ volatile uint32_t fmbm_ppid[63]; -+} _PackedType t_Ppids; -+ -+ t_Plr *p_Plr; -+ t_Ppids *p_Ppids; -+ int i,j; -+ uint32_t fmRev; -+ -+ static const uint8_t phys1GRxPortId[] = {0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf}; -+ static const uint8_t phys10GRxPortId[] = {0x10,0x11}; -+#if (DPAA_VERSION >= 11) -+ static const uint8_t physOhPortId[] = {/* 0x1, */0x2,0x3,0x4,0x5,0x6,0x7}; -+#else -+ static const uint8_t physOhPortId[] = {0x1,0x2,0x3,0x4,0x5,0x6,0x7}; -+#endif -+ static const uint8_t phys1GTxPortId[] = {0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f}; -+ static const uint8_t phys10GTxPortId[] = {0x30,0x31}; -+ -+ fmRev = (uint32_t)(*((volatile uint32_t *)UINT_TO_PTR(p_LnxWrpFmDev->fmBaseAddr+FM_FPM_IP_REV_1_OFFSET))); -+ fmRev &= 0xffff; -+ -+ p_Plr = (t_Plr *)UINT_TO_PTR(p_LnxWrpFmDev->fmBaseAddr+FM_DMA_PLR_OFFSET); -+#ifdef MODULE -+ for (i=0;iplr[i] = 0; -+#endif /* MODULE */ -+ -+ for (i=0; iplr[i/2] & DMA_LOW_LIODN_MASK) : -+ ((p_Plr->plr[i/2] & DMA_HIGH_LIODN_MASK) >> DMA_LIODN_SHIFT)); -+#ifdef FM_PARTITION_ARRAY -+ /* TODO: this was .liodnPerPartition[i] = liodnBase; is the index meaning the same? */ -+ p_LnxWrpFmDev->fmDevSettings.param.liodnBasePerPort[i] = liodnBase; -+#endif /* FM_PARTITION_ARRAY */ -+ -+ if ((i >= phys1GRxPortId[0]) && -+ (i <= phys1GRxPortId[FM_MAX_NUM_OF_1G_RX_PORTS-1])) -+ { -+ for (j=0; jrxPorts[j].settings.param.liodnBase = liodnBase; -+ } -+ else if (FM_MAX_NUM_OF_10G_RX_PORTS && -+ (i >= phys10GRxPortId[0]) && -+ (i <= phys10GRxPortId[FM_MAX_NUM_OF_10G_RX_PORTS-1])) -+ { -+ for (j=0; jrxPorts[FM_MAX_NUM_OF_1G_RX_PORTS+j].settings.param.liodnBase = liodnBase; -+ } -+ else if ((i >= physOhPortId[0]) && -+ (i <= physOhPortId[FM_MAX_NUM_OF_OH_PORTS-1])) -+ { -+ for (j=0; jhcPort.settings.param.liodnBase = liodnBase; -+ else -+ p_LnxWrpFmDev->opPorts[j - 1].settings.param.liodnBase = liodnBase; -+ } -+ else if ((i >= phys1GTxPortId[0]) && -+ (i <= phys1GTxPortId[FM_MAX_NUM_OF_1G_TX_PORTS-1])) -+ { -+ for (j=0; jtxPorts[j].settings.param.liodnBase = liodnBase; -+ } -+ else if (FM_MAX_NUM_OF_10G_TX_PORTS && -+ (i >= phys10GTxPortId[0]) && -+ (i <= phys10GTxPortId[FM_MAX_NUM_OF_10G_TX_PORTS-1])) -+ { -+ for (j=0; jtxPorts[FM_MAX_NUM_OF_1G_TX_PORTS+j].settings.param.liodnBase = liodnBase; -+ } -+ } -+ -+ p_Ppids = (t_Ppids *)UINT_TO_PTR(p_LnxWrpFmDev->fmBaseAddr+FM_BMI_PPIDS_OFFSET); -+ -+ for (i=0; irxPorts[i].settings.param.specificParams.rxParams.liodnOffset = -+ p_Ppids->fmbm_ppid[phys1GRxPortId[i]-1]; -+ -+ for (i=0; irxPorts[FM_MAX_NUM_OF_1G_RX_PORTS+i].settings.param.specificParams.rxParams.liodnOffset = -+ p_Ppids->fmbm_ppid[phys10GRxPortId[i]-1]; -+ -+ return E_OK; -+} -+ -+/** -+ * FindFmanMicrocode - find the Fman microcode -+ * -+ * This function returns a pointer to the QE Firmware blob that holds -+ * the Fman microcode. We use the QE Firmware structure because Fman microcode -+ * is similar to QE microcode, so there's no point in defining a new layout. -+ * -+ * Current versions of U-Boot embed the Fman firmware into the device tree, -+ * so we check for that first. Each Fman node in the device tree contains a -+ * node or a pointer to node that holds the firmware. Technically, we should -+ * be fetching the firmware node for the current Fman, but we don't have that -+ * information any more, so we assume that there is only one firmware node in -+ * the device tree, and that all Fmen use the same firmware. -+ */ -+static const struct qe_firmware *FindFmanMicrocode(void) -+{ -+ static const struct qe_firmware *P4080_UCPatch; -+ struct device_node *np; -+ -+ if (P4080_UCPatch) -+ return P4080_UCPatch; -+ -+ /* The firmware should be inside the device tree. */ -+ np = of_find_compatible_node(NULL, NULL, "fsl,fman-firmware"); -+ if (np) { -+ P4080_UCPatch = of_get_property(np, "fsl,firmware", NULL); -+ of_node_put(np); -+ if (P4080_UCPatch) -+ return P4080_UCPatch; -+ else -+ REPORT_ERROR(WARNING, E_NOT_FOUND, ("firmware node is incomplete")); -+ } -+ -+ /* Returning NULL here forces the reuse of the IRAM content */ -+ return NULL; -+} -+#define SVR_SECURITY_MASK 0x00080000 -+#define SVR_PERSONALITY_MASK 0x0000FF00 -+#define SVR_VER_IGNORE_MASK (SVR_SECURITY_MASK | SVR_PERSONALITY_MASK) -+#define SVR_B4860_REV1_VALUE 0x86800010 -+#define SVR_B4860_REV2_VALUE 0x86800020 -+#define SVR_T4240_VALUE 0x82400000 -+#define SVR_T4120_VALUE 0x82400100 -+#define SVR_T4160_VALUE 0x82410000 -+#define SVR_T4080_VALUE 0x82410200 -+#define SVR_T4_DEVICE_ID 0x82400000 -+#define SVR_DEVICE_ID_MASK 0xFFF00000 -+ -+static t_LnxWrpFmDev * ReadFmDevTreeNode (struct platform_device *of_dev) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev; -+ struct device_node *fm_node, *dev_node; -+ struct of_device_id name; -+ struct resource res; -+ struct clk *clk; -+ u32 clk_rate; -+ const uint32_t *uint32_prop; -+ int _errno=0, lenp; -+ uint32_t tmp_prop; -+ -+ fm_node = of_node_get(of_dev->dev.of_node); -+ -+ uint32_prop = (uint32_t *)of_get_property(fm_node, "cell-index", &lenp); -+ if (unlikely(uint32_prop == NULL)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("of_get_property(%s, cell-index) failed", fm_node->full_name)); -+ return NULL; -+ } -+ tmp_prop = be32_to_cpu(*uint32_prop); -+ -+ if (WARN_ON(lenp != sizeof(uint32_t))) -+ return NULL; -+ -+ if (tmp_prop > INTG_MAX_NUM_OF_FM) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("fm id!")); -+ return NULL; -+ } -+ p_LnxWrpFmDev = CreateFmDev(tmp_prop); -+ if (!p_LnxWrpFmDev) { -+ REPORT_ERROR(MAJOR, E_NULL_POINTER, NO_MSG); -+ return NULL; -+ } -+ p_LnxWrpFmDev->dev = &of_dev->dev; -+ p_LnxWrpFmDev->id = tmp_prop; -+ -+ /* Get the FM interrupt */ -+ p_LnxWrpFmDev->irq = of_irq_to_resource(fm_node, 0, NULL); -+ if (unlikely(p_LnxWrpFmDev->irq == /*NO_IRQ*/0)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("of_irq_to_resource() = %d", NO_IRQ)); -+ return NULL; -+ } -+ -+ /* Get the FM error interrupt */ -+ p_LnxWrpFmDev->err_irq = of_irq_to_resource(fm_node, 1, NULL); -+ -+ if (unlikely(p_LnxWrpFmDev->err_irq == /*NO_IRQ*/0)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("of_irq_to_resource() = %d", NO_IRQ)); -+ return NULL; -+ } -+ -+ /* Get the FM address */ -+ _errno = of_address_to_resource(fm_node, 0, &res); -+ if (unlikely(_errno < 0)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("of_address_to_resource() = %d", _errno)); -+ return NULL; -+ } -+ -+ -+ p_LnxWrpFmDev->fmBaseAddr = 0; -+ p_LnxWrpFmDev->fmPhysBaseAddr = res.start; -+ p_LnxWrpFmDev->fmMemSize = res.end + 1 - res.start; -+ -+ clk = of_clk_get(fm_node, 0); -+ if (IS_ERR(clk)) { -+ dev_err(&of_dev->dev, "%s: Failed to get FM clock structure\n", -+ __func__); -+ of_node_put(fm_node); -+ return NULL; -+ } -+ -+ clk_rate = clk_get_rate(clk); -+ if (!clk_rate) { -+ dev_err(&of_dev->dev, "%s: Failed to determine FM clock rate\n", -+ __func__); -+ of_node_put(fm_node); -+ return NULL; -+ } -+ -+ p_LnxWrpFmDev->fmDevSettings.param.fmClkFreq = DIV_ROUND_UP(clk_rate, 1000000); /* In MHz, rounded */ -+ /* Get the MURAM base address and size */ -+ memset(&name, 0, sizeof(struct of_device_id)); -+ if (WARN_ON(strlen("muram") >= sizeof(name.name))) -+ return NULL; -+ strcpy(name.name, "muram"); -+ if (WARN_ON(strlen("fsl,fman-muram") >= sizeof(name.compatible))) -+ return NULL; -+ strcpy(name.compatible, "fsl,fman-muram"); -+ for_each_child_of_node(fm_node, dev_node) { -+ if (likely(of_match_node(&name, dev_node) != NULL)) { -+ _errno = of_address_to_resource(dev_node, 0, &res); -+ if (unlikely(_errno < 0)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("of_address_to_resource() = %d", _errno)); -+ return NULL; -+ } -+ -+ p_LnxWrpFmDev->fmMuramBaseAddr = 0; -+ p_LnxWrpFmDev->fmMuramPhysBaseAddr = res.start; -+ p_LnxWrpFmDev->fmMuramMemSize = res.end + 1 - res.start; -+ -+#ifndef CONFIG_FMAN_ARM -+ { -+ uint32_t svr; -+ svr = mfspr(SPRN_SVR); -+ -+ if ((svr & ~SVR_VER_IGNORE_MASK) >= SVR_B4860_REV2_VALUE) -+ p_LnxWrpFmDev->fmMuramMemSize = 0x80000; -+ } -+#endif -+ } -+ } -+ -+ /* Get the RTC base address and size */ -+ memset(&name, 0, sizeof(struct of_device_id)); -+ if (WARN_ON(strlen("rtc") >= sizeof(name.name))) -+ return NULL; -+ strcpy(name.name, "rtc"); -+ if (WARN_ON(strlen("fsl,fman-rtc") >= sizeof(name.compatible))) -+ return NULL; -+ strcpy(name.compatible, "fsl,fman-rtc"); -+ for_each_child_of_node(fm_node, dev_node) { -+ if (likely(of_match_node(&name, dev_node) != NULL)) { -+ _errno = of_address_to_resource(dev_node, 0, &res); -+ if (unlikely(_errno < 0)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("of_address_to_resource() = %d", _errno)); -+ return NULL; -+ } -+ -+ p_LnxWrpFmDev->fmRtcBaseAddr = 0; -+ p_LnxWrpFmDev->fmRtcPhysBaseAddr = res.start; -+ p_LnxWrpFmDev->fmRtcMemSize = res.end + 1 - res.start; -+ } -+ } -+ -+#if (DPAA_VERSION >= 11) -+ /* Get the VSP base address */ -+ for_each_child_of_node(fm_node, dev_node) { -+ if (of_device_is_compatible(dev_node, "fsl,fman-vsps")) { -+ _errno = of_address_to_resource(dev_node, 0, &res); -+ if (unlikely(_errno < 0)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("of_address_to_resource() = %d", _errno)); -+ return NULL; -+ } -+ p_LnxWrpFmDev->fmVspBaseAddr = 0; -+ p_LnxWrpFmDev->fmVspPhysBaseAddr = res.start; -+ p_LnxWrpFmDev->fmVspMemSize = res.end + 1 - res.start; -+ } -+ } -+#endif -+ -+ /* Get all PCD nodes */ -+ memset(&name, 0, sizeof(struct of_device_id)); -+ if (WARN_ON(strlen("parser") >= sizeof(name.name))) -+ return NULL; -+ strcpy(name.name, "parser"); -+ if (WARN_ON(strlen("fsl,fman-parser") >= sizeof(name.compatible))) -+ return NULL; -+ strcpy(name.compatible, "fsl,fman-parser"); -+ for_each_child_of_node(fm_node, dev_node) -+ if (likely(of_match_node(&name, dev_node) != NULL)) -+ p_LnxWrpFmDev->prsActive = TRUE; -+ -+ memset(&name, 0, sizeof(struct of_device_id)); -+ if (WARN_ON(strlen("keygen") >= sizeof(name.name))) -+ return NULL; -+ strcpy(name.name, "keygen"); -+ if (WARN_ON(strlen("fsl,fman-keygen") >= sizeof(name.compatible))) -+ return NULL; -+ strcpy(name.compatible, "fsl,fman-keygen"); -+ for_each_child_of_node(fm_node, dev_node) -+ if (likely(of_match_node(&name, dev_node) != NULL)) -+ p_LnxWrpFmDev->kgActive = TRUE; -+ -+ memset(&name, 0, sizeof(struct of_device_id)); -+ if (WARN_ON(strlen("cc") >= sizeof(name.name))) -+ return NULL; -+ strcpy(name.name, "cc"); -+ if (WARN_ON(strlen("fsl,fman-cc") >= sizeof(name.compatible))) -+ return NULL; -+ strcpy(name.compatible, "fsl,fman-cc"); -+ for_each_child_of_node(fm_node, dev_node) -+ if (likely(of_match_node(&name, dev_node) != NULL)) -+ p_LnxWrpFmDev->ccActive = TRUE; -+ -+ memset(&name, 0, sizeof(struct of_device_id)); -+ if (WARN_ON(strlen("policer") >= sizeof(name.name))) -+ return NULL; -+ strcpy(name.name, "policer"); -+ if (WARN_ON(strlen("fsl,fman-policer") >= sizeof(name.compatible))) -+ return NULL; -+ strcpy(name.compatible, "fsl,fman-policer"); -+ for_each_child_of_node(fm_node, dev_node) -+ if (likely(of_match_node(&name, dev_node) != NULL)) -+ p_LnxWrpFmDev->plcrActive = TRUE; -+ -+ if (p_LnxWrpFmDev->prsActive || p_LnxWrpFmDev->kgActive || -+ p_LnxWrpFmDev->ccActive || p_LnxWrpFmDev->plcrActive) -+ p_LnxWrpFmDev->pcdActive = TRUE; -+ -+ if (p_LnxWrpFmDev->pcdActive) -+ { -+ const char *str_prop = (char *)of_get_property(fm_node, "fsl,default-pcd", &lenp); -+ if (str_prop) { -+ if (strncmp(str_prop, "3-tuple", strlen("3-tuple")) == 0) -+ p_LnxWrpFmDev->defPcd = e_FM_PCD_3_TUPLE; -+ } -+ else -+ p_LnxWrpFmDev->defPcd = e_NO_PCD; -+ } -+ -+ of_node_put(fm_node); -+ -+ p_LnxWrpFmDev->hcCh = -+ qman_affine_channel(cpumask_first(qman_affine_cpus())); -+ -+ p_LnxWrpFmDev->active = TRUE; -+ -+ return p_LnxWrpFmDev; -+} -+ -+struct device_node *GetFmAdvArgsDevTreeNode (uint8_t fmIndx) -+{ -+ struct device_node *dev_node; -+ const uint32_t *uint32_prop; -+ int lenp; -+ uint32_t tmp_prop; -+ -+ for_each_compatible_node(dev_node, NULL, "fsl,fman-extended-args") { -+ uint32_prop = (uint32_t *)of_get_property(dev_node, "cell-index", &lenp); -+ if (unlikely(uint32_prop == NULL)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("of_get_property(%s, cell-index) failed", -+ dev_node->full_name)); -+ return NULL; -+ } -+ tmp_prop = be32_to_cpu(*uint32_prop); -+ if (WARN_ON(lenp != sizeof(uint32_t))) -+ return NULL; -+ if (tmp_prop > INTG_MAX_NUM_OF_FM) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("fm id!")); -+ return NULL; -+ } -+ if (fmIndx == tmp_prop) -+ return dev_node; -+ } -+ -+ return NULL; -+} -+ -+static t_Error CheckNConfigFmAdvArgs (t_LnxWrpFmDev *p_LnxWrpFmDev) -+{ -+ struct device_node *dev_node; -+ t_Error err = E_INVALID_VALUE; -+ const uint32_t *uint32_prop; -+ const char *str_prop; -+ int lenp; -+ uint32_t tmp_prop; -+ -+ dev_node = GetFmAdvArgsDevTreeNode(p_LnxWrpFmDev->id); -+ if (!dev_node) /* no advance parameters for FMan */ -+ return E_OK; -+ -+ str_prop = (char *)of_get_property(dev_node, "dma-aid-mode", &lenp); -+ if (str_prop) { -+ if (strcmp(str_prop, "port") == 0) -+ err = FM_ConfigDmaAidMode(p_LnxWrpFmDev->h_Dev, e_FM_DMA_AID_OUT_PORT_ID); -+ else if (strcmp(str_prop, "tnum") == 0) -+ err = FM_ConfigDmaAidMode(p_LnxWrpFmDev->h_Dev, e_FM_DMA_AID_OUT_TNUM); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ uint32_prop = (uint32_t *)of_get_property(dev_node, -+ "total-fifo-size", &lenp); -+ if (uint32_prop) { -+ tmp_prop = be32_to_cpu(*uint32_prop); -+ if (WARN_ON(lenp != sizeof(uint32_t))) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, NO_MSG); -+ -+ if (FM_ConfigTotalFifoSize(p_LnxWrpFmDev->h_Dev, -+ tmp_prop) != E_OK) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, NO_MSG); -+ } -+ -+ uint32_prop = (uint32_t *)of_get_property(dev_node, "tnum-aging-period", -+ &lenp); -+ if (uint32_prop) { -+ tmp_prop = be32_to_cpu(*uint32_prop); -+ if (WARN_ON(lenp != sizeof(uint32_t))) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, NO_MSG); -+ -+ err = FM_ConfigTnumAgingPeriod(p_LnxWrpFmDev->h_Dev, -+ (uint16_t)tmp_prop/*tnumAgingPeriod*/); -+ -+ if (err != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ of_node_put(dev_node); -+ -+ return E_OK; -+} -+ -+static void LnxwrpFmDevExceptionsCb(t_Handle h_App, e_FmExceptions exception) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = (t_LnxWrpFmDev *)h_App; -+ -+ ASSERT_COND(p_LnxWrpFmDev); -+ -+ DBG(INFO, ("got fm exception %d", exception)); -+ -+ /* do nothing */ -+ UNUSED(exception); -+} -+ -+static void LnxwrpFmDevBusErrorCb(t_Handle h_App, -+ e_FmPortType portType, -+ uint8_t portId, -+ uint64_t addr, -+ uint8_t tnum, -+ uint16_t liodn) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = (t_LnxWrpFmDev *)h_App; -+ -+ ASSERT_COND(p_LnxWrpFmDev); -+ -+ /* do nothing */ -+ UNUSED(portType);UNUSED(portId);UNUSED(addr);UNUSED(tnum);UNUSED(liodn); -+} -+ -+static t_Error ConfigureFmDev(t_LnxWrpFmDev *p_LnxWrpFmDev) -+{ -+ struct resource *dev_res; -+ int _errno; -+ -+ if (!p_LnxWrpFmDev->active) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("FM not configured!!!")); -+ -+#ifndef MODULE -+ _errno = can_request_irq(p_LnxWrpFmDev->irq, 0); -+ if (unlikely(_errno < 0)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("can_request_irq() = %d", _errno)); -+#endif -+ _errno = devm_request_irq(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->irq, fm_irq, 0, "fman", p_LnxWrpFmDev); -+ if (unlikely(_errno < 0)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("request_irq(%d) = %d", p_LnxWrpFmDev->irq, _errno)); -+ -+ enable_irq_wake(p_LnxWrpFmDev->irq); -+ -+ if (p_LnxWrpFmDev->err_irq != 0) { -+#ifndef MODULE -+ _errno = can_request_irq(p_LnxWrpFmDev->err_irq, 0); -+ if (unlikely(_errno < 0)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("can_request_irq() = %d", _errno)); -+#endif -+ _errno = devm_request_irq(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->err_irq, fm_err_irq, IRQF_SHARED, "fman-err", p_LnxWrpFmDev); -+ if (unlikely(_errno < 0)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("request_irq(%d) = %d", p_LnxWrpFmDev->err_irq, _errno)); -+ -+ enable_irq_wake(p_LnxWrpFmDev->err_irq); -+ } -+ -+ p_LnxWrpFmDev->res = devm_request_mem_region(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->fmPhysBaseAddr, p_LnxWrpFmDev->fmMemSize, "fman"); -+ if (unlikely(p_LnxWrpFmDev->res == NULL)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("request_mem_region() failed")); -+ -+ p_LnxWrpFmDev->fmBaseAddr = PTR_TO_UINT(devm_ioremap(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->fmPhysBaseAddr, p_LnxWrpFmDev->fmMemSize)); -+ if (unlikely(p_LnxWrpFmDev->fmBaseAddr == 0)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("devm_ioremap() failed")); -+ -+ if (SYS_RegisterIoMap((uint64_t)p_LnxWrpFmDev->fmBaseAddr, (uint64_t)p_LnxWrpFmDev->fmPhysBaseAddr, p_LnxWrpFmDev->fmMemSize) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("FM memory map")); -+ -+ dev_res = __devm_request_region(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->res, p_LnxWrpFmDev->fmMuramPhysBaseAddr, p_LnxWrpFmDev->fmMuramMemSize, "fman-muram"); -+ if (unlikely(dev_res == NULL)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("__devm_request_region() failed")); -+ -+ p_LnxWrpFmDev->fmMuramBaseAddr = PTR_TO_UINT(devm_ioremap(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->fmMuramPhysBaseAddr, p_LnxWrpFmDev->fmMuramMemSize)); -+ if (unlikely(p_LnxWrpFmDev->fmMuramBaseAddr == 0)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("devm_ioremap() failed")); -+ -+ if (SYS_RegisterIoMap((uint64_t)p_LnxWrpFmDev->fmMuramBaseAddr, (uint64_t)p_LnxWrpFmDev->fmMuramPhysBaseAddr, p_LnxWrpFmDev->fmMuramMemSize) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("FM MURAM memory map")); -+ -+ if (p_LnxWrpFmDev->fmRtcPhysBaseAddr) -+ { -+ dev_res = __devm_request_region(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->res, p_LnxWrpFmDev->fmRtcPhysBaseAddr, p_LnxWrpFmDev->fmRtcMemSize, "fman-rtc"); -+ if (unlikely(dev_res == NULL)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("__devm_request_region() failed")); -+ -+ p_LnxWrpFmDev->fmRtcBaseAddr = PTR_TO_UINT(devm_ioremap(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->fmRtcPhysBaseAddr, p_LnxWrpFmDev->fmRtcMemSize)); -+ if (unlikely(p_LnxWrpFmDev->fmRtcBaseAddr == 0)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("devm_ioremap() failed")); -+ -+ if (SYS_RegisterIoMap((uint64_t)p_LnxWrpFmDev->fmRtcBaseAddr, (uint64_t)p_LnxWrpFmDev->fmRtcPhysBaseAddr, p_LnxWrpFmDev->fmRtcMemSize) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("FM-RTC memory map")); -+ } -+ -+#if (DPAA_VERSION >= 11) -+ if (p_LnxWrpFmDev->fmVspPhysBaseAddr) { -+ dev_res = __devm_request_region(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->res, p_LnxWrpFmDev->fmVspPhysBaseAddr, p_LnxWrpFmDev->fmVspMemSize, "fman-vsp"); -+ if (unlikely(dev_res == NULL)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("__devm_request_region() failed")); -+ -+ p_LnxWrpFmDev->fmVspBaseAddr = PTR_TO_UINT(devm_ioremap(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->fmVspPhysBaseAddr, p_LnxWrpFmDev->fmVspMemSize)); -+ if (unlikely(p_LnxWrpFmDev->fmVspBaseAddr == 0)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("devm_ioremap() failed")); -+ } -+#endif -+ -+ p_LnxWrpFmDev->fmDevSettings.param.baseAddr = p_LnxWrpFmDev->fmBaseAddr; -+ p_LnxWrpFmDev->fmDevSettings.param.fmId = p_LnxWrpFmDev->id; -+ p_LnxWrpFmDev->fmDevSettings.param.irq = NO_IRQ; -+ p_LnxWrpFmDev->fmDevSettings.param.errIrq = NO_IRQ; -+ p_LnxWrpFmDev->fmDevSettings.param.f_Exception = LnxwrpFmDevExceptionsCb; -+ p_LnxWrpFmDev->fmDevSettings.param.f_BusError = LnxwrpFmDevBusErrorCb; -+ p_LnxWrpFmDev->fmDevSettings.param.h_App = p_LnxWrpFmDev; -+ -+ return FillRestFmInfo(p_LnxWrpFmDev); -+} -+ -+#ifndef CONFIG_FMAN_ARM -+/* -+ * Table for matching compatible strings, for device tree -+ * guts node, for QorIQ SOCs. -+ * "fsl,qoriq-device-config-2.0" corresponds to T4 & B4 -+ * SOCs. For the older SOCs "fsl,qoriq-device-config-1.0" -+ * string would be used. -+*/ -+static const struct of_device_id guts_device_ids[] = { -+ { .compatible = "fsl,qoriq-device-config-1.0", }, -+ { .compatible = "fsl,qoriq-device-config-2.0", }, -+ {} -+}; -+ -+static unsigned int get_rcwsr(int regnum) -+{ -+ struct ccsr_guts __iomem *guts_regs = NULL; -+ struct device_node *guts_node; -+ -+ guts_node = of_find_matching_node(NULL, guts_device_ids); -+ if (!guts_node) { -+ pr_err("could not find GUTS node\n"); -+ return 0; -+ } -+ guts_regs = of_iomap(guts_node, 0); -+ of_node_put(guts_node); -+ if (!guts_regs) { -+ pr_err("ioremap of GUTS node failed\n"); -+ return 0; -+ } -+ -+ return ioread32be(&guts_regs->rcwsr[regnum]); -+} -+#endif -+ -+static t_Error InitFmDev(t_LnxWrpFmDev *p_LnxWrpFmDev) -+{ -+ const struct qe_firmware *fw; -+ -+ if (!p_LnxWrpFmDev->active) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("FM not configured!!!")); -+ -+ if ((p_LnxWrpFmDev->h_MuramDev = FM_MURAM_ConfigAndInit(p_LnxWrpFmDev->fmMuramBaseAddr, p_LnxWrpFmDev->fmMuramMemSize)) == NULL) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("FM-MURAM!")); -+ -+ /* Loading the fman-controller code */ -+ fw = FindFmanMicrocode(); -+ -+ if (!fw) { -+ /* this forces the reuse of the current IRAM content */ -+ p_LnxWrpFmDev->fmDevSettings.param.firmware.size = 0; -+ p_LnxWrpFmDev->fmDevSettings.param.firmware.p_Code = NULL; -+ } else { -+ p_LnxWrpFmDev->fmDevSettings.param.firmware.p_Code = -+ (void *) fw + be32_to_cpu(fw->microcode[0].code_offset); -+ p_LnxWrpFmDev->fmDevSettings.param.firmware.size = -+ sizeof(u32) * be32_to_cpu(fw->microcode[0].count); -+ DBG(INFO, ("Loading fman-controller code version %d.%d.%d", -+ fw->microcode[0].major, -+ fw->microcode[0].minor, -+ fw->microcode[0].revision)); -+ } -+ -+#ifdef CONFIG_FMAN_ARM -+ { /* endianness adjustments: byteswap the ucode retrieved from the f/w blob */ -+ int i; -+ int usz = p_LnxWrpFmDev->fmDevSettings.param.firmware.size; -+ void * p_Code = p_LnxWrpFmDev->fmDevSettings.param.firmware.p_Code; -+ -+ for(i=0; i < usz / 4; ++i) -+ ((u32 *)p_Code)[i] = be32_to_cpu(((u32 *)p_Code)[i]); -+ } -+#endif -+ -+ p_LnxWrpFmDev->fmDevSettings.param.h_FmMuram = p_LnxWrpFmDev->h_MuramDev; -+ -+#if (DPAA_VERSION >= 11) -+ if (p_LnxWrpFmDev->fmVspBaseAddr) { -+ p_LnxWrpFmDev->fmDevSettings.param.vspBaseAddr = p_LnxWrpFmDev->fmVspBaseAddr; -+ p_LnxWrpFmDev->fmDevSettings.param.partVSPBase = 0; -+ p_LnxWrpFmDev->fmDevSettings.param.partNumOfVSPs = FM_VSP_MAX_NUM_OF_ENTRIES; -+ } -+#endif -+ -+#ifdef CONFIG_FMAN_ARM -+ p_LnxWrpFmDev->fmDevSettings.param.fmMacClkRatio = 1; -+#else -+ if(p_LnxWrpFmDev->fmDevSettings.param.fmId == 0) -+ p_LnxWrpFmDev->fmDevSettings.param.fmMacClkRatio = -+ !!(get_rcwsr(4) & 0x2); /* RCW[FM_MAC_RAT0] */ -+ else -+ p_LnxWrpFmDev->fmDevSettings.param.fmMacClkRatio = -+ !!(get_rcwsr(4) & 0x1); /* RCW[FM_MAC_RAT1] */ -+ -+ { -+ /* T4 Devices ClkRatio is always 1 regardless of RCW[FM_MAC_RAT1] */ -+ uint32_t svr; -+ svr = mfspr(SPRN_SVR); -+ -+ if ((svr & SVR_DEVICE_ID_MASK) == SVR_T4_DEVICE_ID) -+ p_LnxWrpFmDev->fmDevSettings.param.fmMacClkRatio = 1; -+ } -+#endif /* CONFIG_FMAN_ARM */ -+ -+ if ((p_LnxWrpFmDev->h_Dev = FM_Config(&p_LnxWrpFmDev->fmDevSettings.param)) == NULL) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("FM")); -+ -+ -+ if (FM_ConfigResetOnInit(p_LnxWrpFmDev->h_Dev, TRUE) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("FM")); -+ -+#ifdef CONFIG_FMAN_P1023 -+ if (FM_ConfigDmaAidOverride(p_LnxWrpFmDev->h_Dev, TRUE) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("FM")); -+#endif -+ -+ -+ CheckNConfigFmAdvArgs(p_LnxWrpFmDev); -+ -+ if (FM_Init(p_LnxWrpFmDev->h_Dev) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("FM")); -+ -+ /* TODO: Why we mask these interrupts? */ -+ if (p_LnxWrpFmDev->err_irq == 0) { -+ FM_SetException(p_LnxWrpFmDev->h_Dev, e_FM_EX_DMA_BUS_ERROR,FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_DMA_READ_ECC,FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_DMA_SYSTEM_WRITE_ECC,FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_DMA_FM_WRITE_ECC,FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_DMA_SINGLE_PORT_ECC, FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_FPM_STALL_ON_TASKS , FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_FPM_SINGLE_ECC, FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_FPM_DOUBLE_ECC,FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_QMI_SINGLE_ECC, FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_QMI_DOUBLE_ECC,FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID,FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_BMI_LIST_RAM_ECC,FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_BMI_STORAGE_PROFILE_ECC, FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_BMI_STATISTICS_RAM_ECC, FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_BMI_DISPATCH_RAM_ECC, FALSE); -+ FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_IRAM_ECC,FALSE); -+ /* TODO: FmDisableRamsEcc assert for ramsEccOwners. -+ * FM_SetException(p_LnxWrpFmDev->h_Dev,e_FM_EX_MURAM_ECC,FALSE);*/ -+ } -+ -+ if (p_LnxWrpFmDev->fmRtcBaseAddr) -+ { -+ t_FmRtcParams fmRtcParam; -+ -+ memset(&fmRtcParam, 0, sizeof(fmRtcParam)); -+ fmRtcParam.h_App = p_LnxWrpFmDev; -+ fmRtcParam.h_Fm = p_LnxWrpFmDev->h_Dev; -+ fmRtcParam.baseAddress = p_LnxWrpFmDev->fmRtcBaseAddr; -+ -+ if(!(p_LnxWrpFmDev->h_RtcDev = FM_RTC_Config(&fmRtcParam))) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("FM-RTC")); -+ -+ if (FM_RTC_ConfigPeriod(p_LnxWrpFmDev->h_RtcDev, DPA_PTP_NOMINAL_FREQ_PERIOD_NS) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("FM-RTC")); -+ -+ if (FM_RTC_Init(p_LnxWrpFmDev->h_RtcDev) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, ("FM-RTC")); -+ } -+ -+ return E_OK; -+} -+ -+/* TODO: to be moved back here */ -+extern void FreeFmPcdDev(t_LnxWrpFmDev *p_LnxWrpFmDev); -+ -+static void FreeFmDev(t_LnxWrpFmDev *p_LnxWrpFmDev) -+{ -+ if (!p_LnxWrpFmDev->active) -+ return; -+ -+ FreeFmPcdDev(p_LnxWrpFmDev); -+ -+ if (p_LnxWrpFmDev->h_RtcDev) -+ FM_RTC_Free(p_LnxWrpFmDev->h_RtcDev); -+ -+ if (p_LnxWrpFmDev->h_Dev) -+ FM_Free(p_LnxWrpFmDev->h_Dev); -+ -+ if (p_LnxWrpFmDev->h_MuramDev) -+ FM_MURAM_Free(p_LnxWrpFmDev->h_MuramDev); -+ -+ if (p_LnxWrpFmDev->fmRtcBaseAddr) -+ { -+ SYS_UnregisterIoMap(p_LnxWrpFmDev->fmRtcBaseAddr); -+ devm_iounmap(p_LnxWrpFmDev->dev, UINT_TO_PTR(p_LnxWrpFmDev->fmRtcBaseAddr)); -+ __devm_release_region(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->res, p_LnxWrpFmDev->fmRtcPhysBaseAddr, p_LnxWrpFmDev->fmRtcMemSize); -+ } -+ SYS_UnregisterIoMap(p_LnxWrpFmDev->fmMuramBaseAddr); -+ devm_iounmap(p_LnxWrpFmDev->dev, UINT_TO_PTR(p_LnxWrpFmDev->fmMuramBaseAddr)); -+ __devm_release_region(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->res, p_LnxWrpFmDev->fmMuramPhysBaseAddr, p_LnxWrpFmDev->fmMuramMemSize); -+ SYS_UnregisterIoMap(p_LnxWrpFmDev->fmBaseAddr); -+ devm_iounmap(p_LnxWrpFmDev->dev, UINT_TO_PTR(p_LnxWrpFmDev->fmBaseAddr)); -+ devm_release_mem_region(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->fmPhysBaseAddr, p_LnxWrpFmDev->fmMemSize); -+ if (p_LnxWrpFmDev->err_irq != 0) { -+ devm_free_irq(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->err_irq, p_LnxWrpFmDev); -+ } -+ -+ devm_free_irq(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->irq, p_LnxWrpFmDev); -+} -+ -+/* FMan character device file operations */ -+extern struct file_operations fm_fops; -+ -+static int /*__devinit*/ fm_probe(struct platform_device *of_dev) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev; -+ -+ if ((p_LnxWrpFmDev = ReadFmDevTreeNode(of_dev)) == NULL) -+ return -EIO; -+ if (ConfigureFmDev(p_LnxWrpFmDev) != E_OK) -+ return -EIO; -+ if (InitFmDev(p_LnxWrpFmDev) != E_OK) -+ return -EIO; -+ -+ /* IOCTL ABI checking */ -+ LnxWrpPCDIOCTLEnumChecking(); -+ LnxWrpPCDIOCTLTypeChecking(); -+ -+ Sprint (p_LnxWrpFmDev->name, "%s%d", DEV_FM_NAME, p_LnxWrpFmDev->id); -+ -+ /* Register to the /dev for IOCTL API */ -+ /* Register dynamically a new major number for the character device: */ -+ if ((p_LnxWrpFmDev->major = register_chrdev(0, p_LnxWrpFmDev->name, &fm_fops)) <= 0) { -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Failed to allocate a major number for device \"%s\"", p_LnxWrpFmDev->name)); -+ return -EIO; -+ } -+ -+ /* Creating classes for FM */ -+ DBG(TRACE ,("class_create fm_class")); -+ p_LnxWrpFmDev->fm_class = class_create(THIS_MODULE, p_LnxWrpFmDev->name); -+ if (IS_ERR(p_LnxWrpFmDev->fm_class)) { -+ unregister_chrdev(p_LnxWrpFmDev->major, p_LnxWrpFmDev->name); -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("class_create error fm_class")); -+ return -EIO; -+ } -+ -+ device_create(p_LnxWrpFmDev->fm_class, NULL, MKDEV(p_LnxWrpFmDev->major, DEV_FM_MINOR_BASE), NULL, -+ "fm%d", p_LnxWrpFmDev->id); -+ device_create(p_LnxWrpFmDev->fm_class, NULL, MKDEV(p_LnxWrpFmDev->major, DEV_FM_PCD_MINOR_BASE), NULL, -+ "fm%d-pcd", p_LnxWrpFmDev->id); -+ dev_set_drvdata(p_LnxWrpFmDev->dev, p_LnxWrpFmDev); -+ -+ /* create sysfs entries for stats and regs */ -+ if ( fm_sysfs_create(p_LnxWrpFmDev->dev) !=0 ) -+ { -+ FreeFmDev(p_LnxWrpFmDev); -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Unable to create sysfs entry - fm!!!")); -+ return -EIO; -+ } -+ -+#ifdef CONFIG_PM -+ device_set_wakeup_capable(p_LnxWrpFmDev->dev, true); -+#endif -+ -+ DBG(TRACE, ("FM%d probed", p_LnxWrpFmDev->id)); -+ -+ return 0; -+} -+ -+static int fm_remove(struct platform_device *of_dev) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev; -+ struct device *dev; -+ -+ dev = &of_dev->dev; -+ p_LnxWrpFmDev = dev_get_drvdata(dev); -+ -+ fm_sysfs_destroy(dev); -+ -+ DBG(TRACE, ("destroy fm_class")); -+ device_destroy(p_LnxWrpFmDev->fm_class, MKDEV(p_LnxWrpFmDev->major, DEV_FM_MINOR_BASE)); -+ device_destroy(p_LnxWrpFmDev->fm_class, MKDEV(p_LnxWrpFmDev->major, DEV_FM_PCD_MINOR_BASE)); -+ class_destroy(p_LnxWrpFmDev->fm_class); -+ -+ /* Destroy chardev */ -+ unregister_chrdev(p_LnxWrpFmDev->major, p_LnxWrpFmDev->name); -+ -+ FreeFmDev(p_LnxWrpFmDev); -+ -+ DestroyFmDev(p_LnxWrpFmDev); -+ -+ dev_set_drvdata(dev, NULL); -+ -+ return 0; -+} -+ -+static const struct of_device_id fm_match[] = { -+ { -+ .compatible = "fsl,fman" -+ }, -+ {} -+}; -+#ifndef MODULE -+MODULE_DEVICE_TABLE(of, fm_match); -+#endif /* !MODULE */ -+ -+#ifdef CONFIG_PM -+ -+#define SCFG_FMCLKDPSLPCR_ADDR 0xFFE0FC00C -+#define SCFG_FMCLKDPSLPCR_DS_VAL 0x48402000 -+#define SCFG_FMCLKDPSLPCR_NORMAL_VAL 0x00402000 -+ -+struct device *g_fm_dev; -+ -+static int fm_soc_suspend(struct device *dev) -+{ -+ int err = 0; -+ uint32_t *fmclk; -+ t_LnxWrpFmDev *p_LnxWrpFmDev = dev_get_drvdata(get_device(dev)); -+ g_fm_dev = dev; -+ fmclk = ioremap(SCFG_FMCLKDPSLPCR_ADDR, 4); -+ WRITE_UINT32(*fmclk, SCFG_FMCLKDPSLPCR_DS_VAL); -+ if (p_LnxWrpFmDev->h_DsarRxPort) -+ { -+#ifdef CONFIG_FSL_QORIQ_PM -+ device_set_wakeup_enable(p_LnxWrpFmDev->dev, 1); -+#endif -+ err = FM_PORT_EnterDsarFinal(p_LnxWrpFmDev->h_DsarRxPort, -+ p_LnxWrpFmDev->h_DsarTxPort); -+ } -+ return err; -+} -+ -+static int fm_soc_resume(struct device *dev) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = dev_get_drvdata(get_device(dev)); -+ uint32_t *fmclk; -+ fmclk = ioremap(SCFG_FMCLKDPSLPCR_ADDR, 4); -+ WRITE_UINT32(*fmclk, SCFG_FMCLKDPSLPCR_NORMAL_VAL); -+ if (p_LnxWrpFmDev->h_DsarRxPort) -+ { -+#ifdef CONFIG_FSL_QORIQ_PM -+ device_set_wakeup_enable(p_LnxWrpFmDev->dev, 0); -+#endif -+ FM_PORT_ExitDsar(p_LnxWrpFmDev->h_DsarRxPort, -+ p_LnxWrpFmDev->h_DsarTxPort); -+ p_LnxWrpFmDev->h_DsarRxPort = 0; -+ p_LnxWrpFmDev->h_DsarTxPort = 0; -+ } -+ return 0; -+} -+ -+static const struct dev_pm_ops fm_pm_ops = { -+ .suspend = fm_soc_suspend, -+ .resume = fm_soc_resume, -+}; -+ -+#define FM_PM_OPS (&fm_pm_ops) -+ -+#else /* CONFIG_PM */ -+ -+#define FM_PM_OPS NULL -+ -+#endif /* CONFIG_PM */ -+ -+static struct platform_driver fm_driver = { -+ .driver = { -+ .name = "fsl-fman", -+ .of_match_table = fm_match, -+ .owner = THIS_MODULE, -+ .pm = FM_PM_OPS, -+ }, -+ .probe = fm_probe, -+ .remove = fm_remove -+}; -+ -+t_Handle LNXWRP_FM_Init(void) -+{ -+ memset(&lnxWrpFm, 0, sizeof(lnxWrpFm)); -+ mutex_init(&lnxwrp_mutex); -+ -+ /* Register to the DTB for basic FM API */ -+ platform_driver_register(&fm_driver); -+ -+ return &lnxWrpFm; -+} -+ -+t_Error LNXWRP_FM_Free(t_Handle h_LnxWrpFm) -+{ -+ platform_driver_unregister(&fm_driver); -+ mutex_destroy(&lnxwrp_mutex); -+ -+ return E_OK; -+} -+ -+ -+struct fm * fm_bind(struct device *fm_dev) -+{ -+ return (struct fm *)(dev_get_drvdata(get_device(fm_dev))); -+} -+EXPORT_SYMBOL(fm_bind); -+ -+void fm_unbind(struct fm *fm) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = (t_LnxWrpFmDev*)fm; -+ -+ put_device(p_LnxWrpFmDev->dev); -+} -+EXPORT_SYMBOL(fm_unbind); -+ -+struct resource * fm_get_mem_region(struct fm *fm) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = (t_LnxWrpFmDev*)fm; -+ -+ return p_LnxWrpFmDev->res; -+} -+EXPORT_SYMBOL(fm_get_mem_region); -+ -+void * fm_get_handle(struct fm *fm) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = (t_LnxWrpFmDev*)fm; -+ -+ return (void *)p_LnxWrpFmDev->h_Dev; -+} -+EXPORT_SYMBOL(fm_get_handle); -+ -+void * fm_get_rtc_handle(struct fm *fm) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = (t_LnxWrpFmDev*)fm; -+ -+ return (void *)p_LnxWrpFmDev->h_RtcDev; -+} -+EXPORT_SYMBOL(fm_get_rtc_handle); -+ -+struct fm_port * fm_port_bind (struct device *fm_port_dev) -+{ -+ return (struct fm_port *)(dev_get_drvdata(get_device(fm_port_dev))); -+} -+EXPORT_SYMBOL(fm_port_bind); -+ -+void fm_port_unbind(struct fm_port *port) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev*)port; -+ -+ put_device(p_LnxWrpFmPortDev->dev); -+} -+EXPORT_SYMBOL(fm_port_unbind); -+ -+void *fm_port_get_handle(const struct fm_port *port) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev*)port; -+ -+ return (void *)p_LnxWrpFmPortDev->h_Dev; -+} -+EXPORT_SYMBOL(fm_port_get_handle); -+ -+u64 *fm_port_get_buffer_time_stamp(const struct fm_port *port, -+ const void *data) -+{ -+ return FM_PORT_GetBufferTimeStamp(fm_port_get_handle(port), -+ (void *)data); -+} -+EXPORT_SYMBOL(fm_port_get_buffer_time_stamp); -+ -+void fm_port_get_base_addr(const struct fm_port *port, uint64_t *base_addr) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *)port; -+ -+ *base_addr = p_LnxWrpFmPortDev->settings.param.baseAddr; -+} -+EXPORT_SYMBOL(fm_port_get_base_addr); -+ -+void fm_port_pcd_bind (struct fm_port *port, struct fm_port_pcd_param *params) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev*)port; -+ -+ p_LnxWrpFmPortDev->pcd_owner_params.cba = params->cba; -+ p_LnxWrpFmPortDev->pcd_owner_params.cbf = params->cbf; -+ p_LnxWrpFmPortDev->pcd_owner_params.dev = params->dev; -+} -+EXPORT_SYMBOL(fm_port_pcd_bind); -+ -+void fm_port_get_buff_layout_ext_params(struct fm_port *port, struct fm_port_params *params) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *)port; -+ struct device_node *fm_node, *port_node; -+ const uint32_t *uint32_prop; -+ int lenp; -+ -+ params->data_align = 0; -+ params->manip_extra_space = 0; -+ -+ fm_node = GetFmAdvArgsDevTreeNode(((t_LnxWrpFmDev *) p_LnxWrpFmPortDev->h_LnxWrpFmDev)->id); -+ if (!fm_node) /* no advance parameters for FMan */ -+ return; -+ -+ port_node = GetFmPortAdvArgsDevTreeNode(fm_node, -+ p_LnxWrpFmPortDev->settings.param.portType, -+ p_LnxWrpFmPortDev->settings.param.portId); -+ if (!port_node) /* no advance parameters for FMan-Port */ -+ return; -+ -+ uint32_prop = (uint32_t *)of_get_property(port_node, "buffer-layout", &lenp); -+ if (uint32_prop) { -+ if (WARN_ON(lenp != sizeof(uint32_t)*2)) -+ return; -+ -+ params->manip_extra_space = (uint8_t)be32_to_cpu(uint32_prop[0]); -+ params->data_align = (uint16_t)be32_to_cpu(uint32_prop[1]); -+ } -+ -+ of_node_put(port_node); -+ of_node_put(fm_node); -+} -+EXPORT_SYMBOL(fm_port_get_buff_layout_ext_params); -+ -+uint16_t fm_get_tx_port_channel(struct fm_port *port) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev*)port; -+ -+ return p_LnxWrpFmPortDev->txCh; -+} -+EXPORT_SYMBOL(fm_get_tx_port_channel); -+ -+int fm_port_enable (struct fm_port *port) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev*)port; -+ t_Error err = FM_PORT_Enable(p_LnxWrpFmPortDev->h_Dev); -+ -+ return GET_ERROR_TYPE(err); -+} -+EXPORT_SYMBOL(fm_port_enable); -+ -+int fm_port_disable(struct fm_port *port) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev*)port; -+ t_Error err = FM_PORT_Disable(p_LnxWrpFmPortDev->h_Dev); -+ -+ return GET_ERROR_TYPE(err); -+} -+EXPORT_SYMBOL(fm_port_disable); -+ -+int fm_port_set_rate_limit(struct fm_port *port, -+ uint16_t max_burst_size, -+ uint32_t rate_limit) -+{ -+ t_FmPortRateLimit param; -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *)port; -+ int err = 0; -+ -+ param.maxBurstSize = max_burst_size; -+ param.rateLimit = rate_limit; -+ param.rateLimitDivider = 0; -+ -+ err = FM_PORT_SetRateLimit(p_LnxWrpFmPortDev->h_Dev, ¶m); -+ return err; -+} -+EXPORT_SYMBOL(fm_port_set_rate_limit); -+ -+int fm_port_del_rate_limit(struct fm_port *port) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *)port; -+ -+ FM_PORT_DeleteRateLimit(p_LnxWrpFmPortDev->h_Dev); -+ return 0; -+} -+EXPORT_SYMBOL(fm_port_del_rate_limit); -+ -+void FM_PORT_Dsar_DumpRegs(void); -+int ar_showmem(struct file *file, const char __user *buffer, -+ unsigned long count, void *data) -+{ -+ FM_PORT_Dsar_DumpRegs(); -+ return 2; -+} -+ -+struct auto_res_tables_sizes *fm_port_get_autores_maxsize( -+ struct fm_port *port) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *)port; -+ return &p_LnxWrpFmPortDev->dsar_table_sizes; -+} -+EXPORT_SYMBOL(fm_port_get_autores_maxsize); -+ -+int fm_port_enter_autores_for_deepsleep(struct fm_port *port, -+ struct auto_res_port_params *params) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *)port; -+ t_LnxWrpFmDev* p_LnxWrpFmDev = (t_LnxWrpFmDev*)p_LnxWrpFmPortDev->h_LnxWrpFmDev; -+ p_LnxWrpFmDev->h_DsarRxPort = p_LnxWrpFmPortDev->h_Dev; -+ p_LnxWrpFmDev->h_DsarTxPort = params->h_FmPortTx; -+ -+ /*Register other under /proc/autoresponse */ -+ if (WARN_ON(sizeof(t_FmPortDsarParams) != sizeof(struct auto_res_port_params))) -+ return -EFAULT; -+ -+ FM_PORT_EnterDsar(p_LnxWrpFmPortDev->h_Dev, (t_FmPortDsarParams*)params); -+ return 0; -+} -+EXPORT_SYMBOL(fm_port_enter_autores_for_deepsleep); -+ -+void fm_port_exit_auto_res_for_deep_sleep(struct fm_port *port_rx, -+ struct fm_port *port_tx) -+{ -+} -+EXPORT_SYMBOL(fm_port_exit_auto_res_for_deep_sleep); -+ -+int fm_port_get_autores_stats(struct fm_port *port, -+ struct auto_res_port_stats *stats) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *)port; -+ if (WARN_ON(sizeof(t_FmPortDsarStats) != sizeof(struct auto_res_port_stats))) -+ return -EFAULT; -+ return FM_PORT_GetDsarStats(p_LnxWrpFmPortDev->h_Dev, (t_FmPortDsarStats*)stats); -+} -+EXPORT_SYMBOL(fm_port_get_autores_stats); -+ -+int fm_port_suspend(struct fm_port *port) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *)port; -+ if (!FM_PORT_IsInDsar(p_LnxWrpFmPortDev->h_Dev)) -+ return FM_PORT_Disable(p_LnxWrpFmPortDev->h_Dev); -+ else -+ return 0; -+} -+EXPORT_SYMBOL(fm_port_suspend); -+ -+int fm_port_resume(struct fm_port *port) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *)port; -+ if (!FM_PORT_IsInDsar(p_LnxWrpFmPortDev->h_Dev)) -+ return FM_PORT_Enable(p_LnxWrpFmPortDev->h_Dev); -+ else -+ return 0; -+} -+EXPORT_SYMBOL(fm_port_resume); -+ -+bool fm_port_is_in_auto_res_mode(struct fm_port *port) -+{ -+ return FM_PORT_IsInDsar(port); -+} -+EXPORT_SYMBOL(fm_port_is_in_auto_res_mode); -+ -+#ifdef CONFIG_FMAN_PFC -+int fm_port_set_pfc_priorities_mapping_to_qman_wq(struct fm_port *port, -+ uint8_t prio, uint8_t wq) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *)port; -+ int err; -+ int _errno; -+ -+ err = FM_PORT_SetPfcPrioritiesMappingToQmanWQ(p_LnxWrpFmPortDev->h_Dev, -+ prio, wq); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_PORT_SetPfcPrioritiesMappingToQmanWQ() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_port_set_pfc_priorities_mapping_to_qman_wq); -+#endif -+ -+int fm_mac_set_exception(struct fm_mac_dev *fm_mac_dev, -+ e_FmMacExceptions exception, bool enable) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MAC_SetException(fm_mac_dev, exception, enable); -+ -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_SetException() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_set_exception); -+ -+int fm_mac_free(struct fm_mac_dev *fm_mac_dev) -+{ -+ int err; -+ int _error; -+ -+ err = FM_MAC_Free(fm_mac_dev); -+ _error = -GET_ERROR_TYPE(err); -+ -+ if (unlikely(_error < 0)) -+ pr_err("FM_MAC_Free() = 0x%08x\n", err); -+ -+ return _error; -+} -+EXPORT_SYMBOL(fm_mac_free); -+ -+struct fm_mac_dev *fm_mac_config(t_FmMacParams *params) -+{ -+ struct fm_mac_dev *fm_mac_dev; -+ -+ fm_mac_dev = FM_MAC_Config(params); -+ if (unlikely(fm_mac_dev == NULL)) -+ pr_err("FM_MAC_Config() failed\n"); -+ -+ return fm_mac_dev; -+} -+EXPORT_SYMBOL(fm_mac_config); -+ -+int fm_mac_config_max_frame_length(struct fm_mac_dev *fm_mac_dev, -+ int len) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MAC_ConfigMaxFrameLength(fm_mac_dev, len); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_ConfigMaxFrameLength() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_config_max_frame_length); -+ -+int fm_mac_config_pad_and_crc(struct fm_mac_dev *fm_mac_dev, bool enable) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MAC_ConfigPadAndCrc(fm_mac_dev, enable); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_ConfigPadAndCrc() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_config_pad_and_crc); -+ -+int fm_mac_config_half_duplex(struct fm_mac_dev *fm_mac_dev, bool enable) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MAC_ConfigHalfDuplex(fm_mac_dev, enable); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_ConfigHalfDuplex() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_config_half_duplex); -+ -+int fm_mac_config_reset_on_init(struct fm_mac_dev *fm_mac_dev, bool enable) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MAC_ConfigResetOnInit(fm_mac_dev, enable); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_ConfigResetOnInit() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_config_reset_on_init); -+ -+int fm_mac_init(struct fm_mac_dev *fm_mac_dev) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MAC_Init(fm_mac_dev); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_Init() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_init); -+ -+int fm_mac_get_version(struct fm_mac_dev *fm_mac_dev, uint32_t *version) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MAC_GetVesrion(fm_mac_dev, version); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_GetVesrion() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_get_version); -+ -+int fm_mac_enable(struct fm_mac_dev *fm_mac_dev) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_MAC_Enable(fm_mac_dev, e_COMM_MODE_RX_AND_TX); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_Enable() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_enable); -+ -+int fm_mac_disable(struct fm_mac_dev *fm_mac_dev) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_MAC_Disable(fm_mac_dev, e_COMM_MODE_RX_AND_TX); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_Disable() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_disable); -+ -+int fm_mac_set_promiscuous(struct fm_mac_dev *fm_mac_dev, -+ bool enable) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_MAC_SetPromiscuous(fm_mac_dev, enable); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_SetPromiscuous() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_set_promiscuous); -+ -+int fm_mac_remove_hash_mac_addr(struct fm_mac_dev *fm_mac_dev, -+ t_EnetAddr *mac_addr) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_MAC_RemoveHashMacAddr(fm_mac_dev, mac_addr); -+ _errno = -GET_ERROR_TYPE(err); -+ if (_errno < 0) { -+ pr_err("FM_MAC_RemoveHashMacAddr() = 0x%08x\n", err); -+ return _errno; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(fm_mac_remove_hash_mac_addr); -+ -+int fm_mac_add_hash_mac_addr(struct fm_mac_dev *fm_mac_dev, -+ t_EnetAddr *mac_addr) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_MAC_AddHashMacAddr(fm_mac_dev, mac_addr); -+ _errno = -GET_ERROR_TYPE(err); -+ if (_errno < 0) { -+ pr_err("FM_MAC_AddHashMacAddr() = 0x%08x\n", err); -+ return _errno; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(fm_mac_add_hash_mac_addr); -+ -+int fm_mac_modify_mac_addr(struct fm_mac_dev *fm_mac_dev, -+ uint8_t *addr) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_MAC_ModifyMacAddr(fm_mac_dev, (t_EnetAddr *)addr); -+ _errno = -GET_ERROR_TYPE(err); -+ if (_errno < 0) -+ pr_err("FM_MAC_ModifyMacAddr() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_modify_mac_addr); -+ -+int fm_mac_adjust_link(struct fm_mac_dev *fm_mac_dev, -+ bool link, int speed, bool duplex) -+{ -+ int _errno; -+ t_Error err; -+ -+ if (!link) { -+#if (DPAA_VERSION < 11) -+ FM_MAC_RestartAutoneg(fm_mac_dev); -+#endif -+ return 0; -+ } -+ -+ err = FM_MAC_AdjustLink(fm_mac_dev, speed, duplex); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_AdjustLink() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_adjust_link); -+ -+int fm_mac_enable_1588_time_stamp(struct fm_mac_dev *fm_mac_dev) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_MAC_Enable1588TimeStamp(fm_mac_dev); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_Enable1588TimeStamp() = 0x%08x\n", err); -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_enable_1588_time_stamp); -+ -+int fm_mac_disable_1588_time_stamp(struct fm_mac_dev *fm_mac_dev) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_MAC_Disable1588TimeStamp(fm_mac_dev); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_Disable1588TimeStamp() = 0x%08x\n", err); -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_disable_1588_time_stamp); -+ -+int fm_mac_set_rx_pause_frames( -+ struct fm_mac_dev *fm_mac_dev, bool en) -+{ -+ int _errno; -+ t_Error err; -+ -+ /* if rx pause is enabled, do NOT ignore pause frames */ -+ err = FM_MAC_SetRxIgnorePauseFrames(fm_mac_dev, !en); -+ -+ _errno = -GET_ERROR_TYPE(err); -+ if (_errno < 0) -+ pr_err("FM_MAC_SetRxIgnorePauseFrames() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_set_rx_pause_frames); -+ -+#ifdef CONFIG_FMAN_PFC -+int fm_mac_set_tx_pause_frames(struct fm_mac_dev *fm_mac_dev, -+ bool en) -+{ -+ int _errno, i; -+ t_Error err; -+ -+ if (en) -+ for (i = 0; i < CONFIG_FMAN_PFC_COS_COUNT; i++) { -+ err = FM_MAC_SetTxPauseFrames(fm_mac_dev, -+ i, fsl_fm_pfc_quanta[i], -+ FSL_FM_PAUSE_THRESH_DEFAULT); -+ _errno = -GET_ERROR_TYPE(err); -+ if (_errno < 0) { -+ pr_err("FM_MAC_SetTxPauseFrames() = 0x%08x\n", err); -+ return _errno; -+ } -+ } -+ else -+ for (i = 0; i < CONFIG_FMAN_PFC_COS_COUNT; i++) { -+ err = FM_MAC_SetTxPauseFrames(fm_mac_dev, -+ i, FSL_FM_PAUSE_TIME_DISABLE, -+ FSL_FM_PAUSE_THRESH_DEFAULT); -+ _errno = -GET_ERROR_TYPE(err); -+ if (_errno < 0) { -+ pr_err("FM_MAC_SetTxPauseFrames() = 0x%08x\n", err); -+ return _errno; -+ } -+ } -+ -+ return _errno; -+} -+#else -+int fm_mac_set_tx_pause_frames(struct fm_mac_dev *fm_mac_dev, -+ bool en) -+{ -+ int _errno; -+ t_Error err; -+ -+ if (en) -+ err = FM_MAC_SetTxAutoPauseFrames(fm_mac_dev, -+ FSL_FM_PAUSE_TIME_ENABLE); -+ else -+ err = FM_MAC_SetTxAutoPauseFrames(fm_mac_dev, -+ FSL_FM_PAUSE_TIME_DISABLE); -+ -+ _errno = -GET_ERROR_TYPE(err); -+ if (_errno < 0) -+ pr_err("FM_MAC_SetTxAutoPauseFrames() = 0x%08x\n", err); -+ -+ return _errno; -+} -+#endif -+EXPORT_SYMBOL(fm_mac_set_tx_pause_frames); -+ -+int fm_rtc_enable(struct fm *fm_dev) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_RTC_Enable(fm_get_rtc_handle(fm_dev), 0); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_RTC_Enable = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_rtc_enable); -+ -+int fm_rtc_disable(struct fm *fm_dev) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_RTC_Disable(fm_get_rtc_handle(fm_dev)); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_RTC_Disable = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_rtc_disable); -+ -+int fm_rtc_get_cnt(struct fm *fm_dev, uint64_t *ts) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_RTC_GetCurrentTime(fm_get_rtc_handle(fm_dev), ts); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_RTC_GetCurrentTime = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_rtc_get_cnt); -+ -+int fm_rtc_set_cnt(struct fm *fm_dev, uint64_t ts) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_RTC_SetCurrentTime(fm_get_rtc_handle(fm_dev), ts); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_RTC_SetCurrentTime = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_rtc_set_cnt); -+ -+int fm_rtc_get_drift(struct fm *fm_dev, uint32_t *drift) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_RTC_GetFreqCompensation(fm_get_rtc_handle(fm_dev), -+ drift); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_RTC_GetFreqCompensation = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_rtc_get_drift); -+ -+int fm_rtc_set_drift(struct fm *fm_dev, uint32_t drift) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_RTC_SetFreqCompensation(fm_get_rtc_handle(fm_dev), -+ drift); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_RTC_SetFreqCompensation = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_rtc_set_drift); -+ -+int fm_rtc_set_alarm(struct fm *fm_dev, uint32_t id, -+ uint64_t time) -+{ -+ t_FmRtcAlarmParams alarm; -+ int _errno; -+ t_Error err; -+ -+ alarm.alarmId = id; -+ alarm.alarmTime = time; -+ alarm.f_AlarmCallback = NULL; -+ err = FM_RTC_SetAlarm(fm_get_rtc_handle(fm_dev), -+ &alarm); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_RTC_SetAlarm = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_rtc_set_alarm); -+ -+int fm_rtc_set_fiper(struct fm *fm_dev, uint32_t id, -+ uint64_t fiper) -+{ -+ t_FmRtcPeriodicPulseParams pp; -+ int _errno; -+ t_Error err; -+ -+ pp.periodicPulseId = id; -+ pp.periodicPulsePeriod = fiper; -+ pp.f_PeriodicPulseCallback = NULL; -+ err = FM_RTC_SetPeriodicPulse(fm_get_rtc_handle(fm_dev), &pp); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_RTC_SetPeriodicPulse = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_rtc_set_fiper); -+ -+#ifdef CONFIG_PTP_1588_CLOCK_DPAA -+int fm_rtc_enable_interrupt(struct fm *fm_dev, uint32_t events) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_RTC_EnableInterrupt(fm_get_rtc_handle(fm_dev), -+ events); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_RTC_EnableInterrupt = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_rtc_enable_interrupt); -+ -+int fm_rtc_disable_interrupt(struct fm *fm_dev, uint32_t events) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_RTC_DisableInterrupt(fm_get_rtc_handle(fm_dev), -+ events); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_RTC_DisableInterrupt = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_rtc_disable_interrupt); -+#endif -+ -+int fm_mac_set_wol(struct fm_port *port, struct fm_mac_dev *fm_mac_dev, bool en) -+{ -+ int _errno; -+ t_Error err; -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *)port; -+ -+ /* Do not set WoL on AR ports */ -+ if (FM_PORT_IsInDsar(p_LnxWrpFmPortDev->h_Dev)) { -+ printk(KERN_WARNING "Port is AutoResponse enabled! WoL will not be set on this port!\n"); -+ return 0; -+ } -+ -+ err = FM_MAC_SetWakeOnLan(fm_mac_dev, en); -+ -+ _errno = -GET_ERROR_TYPE(err); -+ if (_errno < 0) -+ pr_err("FM_MAC_SetWakeOnLan() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_set_wol); -+ -+void fm_mutex_lock(void) -+{ -+ mutex_lock(&lnxwrp_mutex); -+} -+EXPORT_SYMBOL(fm_mutex_lock); -+ -+void fm_mutex_unlock(void) -+{ -+ mutex_unlock(&lnxwrp_mutex); -+} -+EXPORT_SYMBOL(fm_mutex_unlock); -+ -+/*Macsec wrapper functions*/ -+struct fm_macsec_dev *fm_macsec_config(struct fm_macsec_params *fm_params) -+{ -+ struct fm_macsec_dev *fm_macsec_dev; -+ -+ fm_macsec_dev = FM_MACSEC_Config((t_FmMacsecParams *)fm_params); -+ if (unlikely(fm_macsec_dev == NULL)) -+ pr_err("FM_MACSEC_Config() failed\n"); -+ -+ return fm_macsec_dev; -+} -+EXPORT_SYMBOL(fm_macsec_config); -+ -+int fm_macsec_init(struct fm_macsec_dev *fm_macsec_dev) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_Init(fm_macsec_dev); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_Init() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_init); -+ -+int fm_macsec_free(struct fm_macsec_dev *fm_macsec_dev) -+{ -+ int err; -+ int _error; -+ -+ err = FM_MACSEC_Free(fm_macsec_dev); -+ _error = -GET_ERROR_TYPE(err); -+ -+ if (unlikely(_error < 0)) -+ pr_err("FM_MACSEC_Free() = 0x%08x\n", err); -+ -+ return _error; -+} -+EXPORT_SYMBOL(fm_macsec_free); -+ -+int fm_macsec_config_unknown_sci_frame_treatment(struct fm_macsec_dev -+ *fm_macsec_dev, -+ fm_macsec_unknown_sci_frame_treatment treat_mode) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_ConfigUnknownSciFrameTreatment(fm_macsec_dev, -+ treat_mode); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_ConfigUnknownSciFrameTreatmen() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_config_unknown_sci_frame_treatment); -+ -+int fm_macsec_config_invalid_tags_frame_treatment(struct fm_macsec_dev *fm_macsec_dev, -+ bool deliver_uncontrolled) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_ConfigInvalidTagsFrameTreatment(fm_macsec_dev, -+ deliver_uncontrolled); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_ConfigMaxFrameLength() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_config_invalid_tags_frame_treatment); -+ -+int fm_macsec_config_kay_frame_treatment(struct fm_macsec_dev *fm_macsec_dev, -+ bool discard_uncontrolled) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment(fm_macsec_dev, -+ discard_uncontrolled); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatmen() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_config_kay_frame_treatment); -+ -+int fm_macsec_config_untag_frame_treatment(struct fm_macsec_dev *fm_macsec_dev, -+ fm_macsec_untag_frame_treatment treat_mode) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_ConfigUntagFrameTreatment(fm_macsec_dev, treat_mode); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_ConfigUntagFrameTreatment() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_config_untag_frame_treatment); -+ -+int fm_macsec_config_pn_exhaustion_threshold(struct fm_macsec_dev *fm_macsec_dev, -+ uint32_t pn_exh_thr) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_ConfigPnExhaustionThreshold(fm_macsec_dev, pn_exh_thr); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_ConfigPnExhaustionThreshold() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_config_pn_exhaustion_threshold); -+ -+int fm_macsec_config_keys_unreadable(struct fm_macsec_dev *fm_macsec_dev) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_ConfigKeysUnreadable(fm_macsec_dev); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_ConfigKeysUnreadable() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_config_keys_unreadable); -+ -+int fm_macsec_config_sectag_without_sci(struct fm_macsec_dev *fm_macsec_dev) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_ConfigSectagWithoutSCI(fm_macsec_dev); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_ConfigSectagWithoutSCI() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_config_sectag_without_sci); -+ -+int fm_macsec_config_exception(struct fm_macsec_dev *fm_macsec_dev, -+ fm_macsec_exception exception, bool enable) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_ConfigException(fm_macsec_dev, exception, enable); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_ConfigException() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_config_exception); -+ -+int fm_macsec_get_revision(struct fm_macsec_dev *fm_macsec_dev, -+ int *macsec_revision) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_GetRevision(fm_macsec_dev, macsec_revision); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_GetRevision() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_get_revision); -+ -+int fm_macsec_enable(struct fm_macsec_dev *fm_macsec_dev) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_Enable(fm_macsec_dev); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_Enable() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_enable); -+ -+int fm_macsec_disable(struct fm_macsec_dev *fm_macsec_dev) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_Disable(fm_macsec_dev); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_Disable() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_disable); -+ -+int fm_macsec_set_exception(struct fm_macsec_dev *fm_macsec_dev, -+ fm_macsec_exception exception, bool enable) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SetException(fm_macsec_dev, exception, enable); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SetException() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_set_exception); -+ -+/* Macsec SECY wrapper API */ -+struct fm_macsec_secy_dev *fm_macsec_secy_config(struct fm_macsec_secy_params *secy_params) -+{ -+ struct fm_macsec_secy_dev *fm_macsec_secy; -+ -+ fm_macsec_secy = FM_MACSEC_SECY_Config((t_FmMacsecSecYParams *)secy_params); -+ if (unlikely(fm_macsec_secy < 0)) -+ pr_err("FM_MACSEC_SECY_Config() failed\n"); -+ -+ return fm_macsec_secy; -+} -+EXPORT_SYMBOL(fm_macsec_secy_config); -+ -+int fm_macsec_secy_init(struct fm_macsec_secy_dev *fm_macsec_secy_dev) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_Init(fm_macsec_secy_dev); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_Init() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_init); -+ -+int fm_macsec_secy_free(struct fm_macsec_secy_dev *fm_macsec_secy_dev) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_Free(fm_macsec_secy_dev); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_Free() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_free); -+ -+int fm_macsec_secy_config_sci_insertion_mode(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ fm_macsec_sci_insertion_mode sci_insertion_mode) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_ConfigSciInsertionMode(fm_macsec_secy_dev, -+ sci_insertion_mode); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_ConfigSciInsertionMode() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_config_sci_insertion_mode); -+ -+int fm_macsec_secy_config_protect_frames(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ bool protect_frames) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_ConfigProtectFrames(fm_macsec_secy_dev, -+ protect_frames); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_ConfigProtectFrames() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_config_protect_frames); -+ -+int fm_macsec_secy_config_replay_window(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ bool replay_protect, uint32_t replay_window) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_ConfigReplayWindow(fm_macsec_secy_dev, -+ replay_protect, replay_window); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_ConfigReplayWindow() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_config_replay_window); -+ -+int fm_macsec_secy_config_validation_mode(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ fm_macsec_valid_frame_behavior validate_frames) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_ConfigValidationMode(fm_macsec_secy_dev, -+ validate_frames); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_ConfigValidationMode() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_config_validation_mode); -+ -+int fm_macsec_secy_config_confidentiality(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ bool confidentiality_enable, -+ uint32_t confidentiality_offset) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_ConfigConfidentiality(fm_macsec_secy_dev, -+ confidentiality_enable, -+ confidentiality_offset); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_ConfigConfidentiality() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_config_confidentiality); -+ -+int fm_macsec_secy_config_point_to_point(struct fm_macsec_secy_dev *fm_macsec_secy_dev) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_ConfigPointToPoint(fm_macsec_secy_dev); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_ConfigPointToPoint() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_config_point_to_point); -+ -+int fm_macsec_secy_config_exception(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ fm_macsec_secy_exception exception, -+ bool enable) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_ConfigException(fm_macsec_secy_dev, exception, -+ enable); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_ConfigException() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_config_exception); -+ -+int fm_macsec_secy_config_event(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ fm_macsec_secy_event event, -+ bool enable) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_ConfigEvent(fm_macsec_secy_dev, event, enable); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_ConfigEvent() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_config_event); -+ -+struct rx_sc_dev *fm_macsec_secy_create_rxsc(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct fm_macsec_secy_sc_params *params) -+{ -+ struct rx_sc_dev *rx_sc_dev; -+ -+ rx_sc_dev = FM_MACSEC_SECY_CreateRxSc(fm_macsec_secy_dev, (t_FmMacsecSecYSCParams *)params); -+ if (unlikely(rx_sc_dev == NULL)) -+ pr_err("FM_MACSEC_SECY_CreateRxSc() failed\n"); -+ -+ return rx_sc_dev; -+} -+EXPORT_SYMBOL(fm_macsec_secy_create_rxsc); -+ -+int fm_macsec_secy_delete_rxsc(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_DeleteRxSc(fm_macsec_secy_dev, sc); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_DeleteRxSc() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_delete_rxsc); -+ -+int fm_macsec_secy_create_rx_sa(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, macsec_an_t an, -+ uint32_t lowest_pn, macsec_sa_key_t key) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_CreateRxSa(fm_macsec_secy_dev, sc, an, -+ lowest_pn, key); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_CreateRxSa() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_create_rx_sa); -+ -+int fm_macsec_secy_delete_rx_sa(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, macsec_an_t an) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_DeleteRxSa(fm_macsec_secy_dev, sc, an); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_DeleteRxSa() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_delete_rx_sa); -+ -+int fm_macsec_secy_rxsa_enable_receive(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, -+ macsec_an_t an) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_RxSaEnableReceive(fm_macsec_secy_dev, sc, an); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_RxSaEnableReceive() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_rxsa_enable_receive); -+ -+int fm_macsec_secy_rxsa_disable_receive(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, -+ macsec_an_t an) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_RxSaDisableReceive(fm_macsec_secy_dev, sc, an); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_RxSaDisableReceive() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_rxsa_disable_receive); -+ -+int fm_macsec_secy_rxsa_update_next_pn(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, -+ macsec_an_t an, uint32_t updt_next_pn) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_RxSaUpdateNextPn(fm_macsec_secy_dev, sc, an, -+ updt_next_pn); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_RxSaUpdateNextPn() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_rxsa_update_next_pn); -+ -+int fm_macsec_secy_rxsa_update_lowest_pn(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, -+ macsec_an_t an, uint32_t updt_lowest_pn) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_RxSaUpdateLowestPn(fm_macsec_secy_dev, sc, an, -+ updt_lowest_pn); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_RxSaUpdateLowestPn() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_rxsa_update_lowest_pn); -+ -+int fm_macsec_secy_rxsa_modify_key(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, -+ macsec_an_t an, macsec_sa_key_t key) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_RxSaModifyKey(fm_macsec_secy_dev, sc, an, key); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_RxSaModifyKey() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_rxsa_modify_key); -+ -+int fm_macsec_secy_create_tx_sa(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ macsec_an_t an, macsec_sa_key_t key) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_CreateTxSa(fm_macsec_secy_dev, an, key); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_CreateTxSa() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_create_tx_sa); -+ -+int fm_macsec_secy_delete_tx_sa(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ macsec_an_t an) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_DeleteTxSa(fm_macsec_secy_dev, an); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_DeleteTxSa() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_delete_tx_sa); -+ -+int fm_macsec_secy_txsa_modify_key(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ macsec_an_t next_active_an, -+ macsec_sa_key_t key) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_TxSaModifyKey(fm_macsec_secy_dev, next_active_an, -+ key); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_TxSaModifyKey() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_txsa_modify_key); -+ -+int fm_macsec_secy_txsa_set_active(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ macsec_an_t an) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_TxSaSetActive(fm_macsec_secy_dev, an); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_TxSaSetActive() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_txsa_set_active); -+ -+int fm_macsec_secy_txsa_get_active(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ macsec_an_t *p_an) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_TxSaGetActive(fm_macsec_secy_dev, p_an); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_TxSaGetActive() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_txsa_get_active); -+ -+int fm_macsec_secy_get_rxsc_phys_id(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ struct rx_sc_dev *sc, uint32_t *sc_phys_id) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_GetRxScPhysId(fm_macsec_secy_dev, sc, sc_phys_id); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_GetRxScPhysId() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_get_rxsc_phys_id); -+ -+int fm_macsec_secy_get_txsc_phys_id(struct fm_macsec_secy_dev *fm_macsec_secy_dev, -+ uint32_t *sc_phys_id) -+{ -+ int err; -+ int _errno; -+ -+ err = FM_MACSEC_SECY_GetTxScPhysId(fm_macsec_secy_dev, sc_phys_id); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MACSEC_SECY_GetTxScPhysId() = 0x%08x\n", -+ err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_macsec_secy_get_txsc_phys_id); -+ -+static t_Handle h_FmLnxWrp; -+ -+static int __init __cold fm_load (void) -+{ -+ if ((h_FmLnxWrp = LNXWRP_FM_Init()) == NULL) -+ { -+ printk("Failed to init FM wrapper!\n"); -+ return -ENODEV; -+ } -+ -+ printk(KERN_CRIT "Freescale FM module," \ -+ " FMD API version %d.%d.%d\n", -+ FMD_API_VERSION_MAJOR, -+ FMD_API_VERSION_MINOR, -+ FMD_API_VERSION_RESPIN); -+ return 0; -+} -+ -+static void __exit __cold fm_unload (void) -+{ -+ if (h_FmLnxWrp) -+ LNXWRP_FM_Free(h_FmLnxWrp); -+} -+ -+module_init (fm_load); -+module_exit (fm_unload); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_fm.h -@@ -0,0 +1,294 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ @File lnxwrp_fm.h -+ -+ @Author Shlomi Gridish -+ -+ @Description FM Linux wrapper functions. -+ -+*/ -+ -+#ifndef __LNXWRP_FM_H__ -+#define __LNXWRP_FM_H__ -+ -+#include /* struct qman_fq */ -+ -+#include "std_ext.h" -+#include "error_ext.h" -+#include "list_ext.h" -+ -+#include "lnxwrp_fm_ext.h" -+ -+#define FM_MAX_NUM_OF_ADV_SETTINGS 10 -+ -+#define LNXWRP_FM_NUM_OF_SHARED_PROFILES 16 -+ -+#if defined(CONFIG_FMAN_DISABLE_OH_TO_REUSE_RESOURCES) -+#define FM_10G_OPENDMA_MIN_TRESHOLD 8 /* 10g minimum treshold if only HC is enabled and no OH port enabled */ -+#define FM_OPENDMA_RX_TX_RAPORT 2 /* RX = 2*TX */ -+#else -+#define FM_10G_OPENDMA_MIN_TRESHOLD 7 /* 10g minimum treshold if 7 OH ports are enabled */ -+#define FM_OPENDMA_RX_TX_RAPORT 1 /* RX = TX */ -+#endif -+#define FM_DEFAULT_TX10G_OPENDMA 8 /* default TX 10g open dmas */ -+#define FM_DEFAULT_RX10G_OPENDMA 8 /* default RX 10g open dmas */ -+ -+#define FRAG_MANIP_SPACE 128 -+#define FRAG_DATA_ALIGN 64 -+ -+#ifndef CONFIG_FSL_FM_MAX_FRAME_SIZE -+#define CONFIG_FSL_FM_MAX_FRAME_SIZE 0 -+#endif -+ -+#ifndef CONFIG_FSL_FM_RX_EXTRA_HEADROOM -+#define CONFIG_FSL_FM_RX_EXTRA_HEADROOM 16 -+#endif -+ -+typedef enum { -+ e_NO_PCD = 0, -+ e_FM_PCD_3_TUPLE -+} e_LnxWrpFmPortPcdDefUseCase; -+ -+ -+typedef struct t_FmTestFq { -+ struct qman_fq fq_base; -+ t_Handle h_Arg; -+} t_FmTestFq; -+ -+typedef struct { -+ uint8_t id; /* sw port id, see SW_PORT_ID_TO_HW_PORT_ID() in fm_common.h */ -+ int minor; -+ char name[20]; -+ bool active; -+ uint64_t phys_baseAddr; -+ uint64_t baseAddr; /* Port's *virtual* address */ -+ uint32_t memSize; -+ t_WrpFmPortDevSettings settings; -+ t_FmExtPools opExtPools; -+ uint8_t totalNumOfSchemes; -+ uint8_t schemesBase; -+ uint8_t numOfSchemesUsed; -+ uint32_t pcdBaseQ; -+ uint16_t pcdNumOfQs; -+ struct fm_port_pcd_param pcd_owner_params; -+ e_LnxWrpFmPortPcdDefUseCase defPcd; -+ t_Handle h_DefNetEnv; -+ t_Handle h_Schemes[FM_PCD_KG_NUM_OF_SCHEMES]; -+ t_FmBufferPrefixContent buffPrefixContent; -+ t_Handle h_Dev; -+ t_Handle h_DfltVsp; -+ t_Handle h_LnxWrpFmDev; -+ uint16_t txCh; -+ struct device *dev; -+ struct device_attribute *dev_attr_stats; -+ struct device_attribute *dev_attr_regs; -+ struct device_attribute *dev_attr_bmi_regs; -+ struct device_attribute *dev_attr_qmi_regs; -+#if (DPAA_VERSION >= 11) -+ struct device_attribute *dev_attr_ipv4_opt; -+#endif -+ struct device_attribute *dev_attr_dsar_regs; -+ struct device_attribute *dev_attr_dsar_mem; -+ struct auto_res_tables_sizes dsar_table_sizes; -+} t_LnxWrpFmPortDev; -+ -+typedef struct { -+ uint8_t id; -+ bool active; -+ uint64_t baseAddr; -+ uint32_t memSize; -+ t_WrpFmMacDevSettings settings; -+ t_Handle h_Dev; -+ t_Handle h_LnxWrpFmDev; -+} t_LnxWrpFmMacDev; -+ -+/* information about all active ports for an FMan. -+ * !Some ports may be disabled by u-boot, thus will not be available */ -+struct fm_active_ports { -+ uint32_t num_oh_ports; -+ uint32_t num_tx_ports; -+ uint32_t num_rx_ports; -+ uint32_t num_tx25_ports; -+ uint32_t num_rx25_ports; -+ uint32_t num_tx10_ports; -+ uint32_t num_rx10_ports; -+}; -+ -+/* FMan resources precalculated at fm probe based -+ * on available FMan port. */ -+struct fm_resource_settings { -+ /* buffers - fifo sizes */ -+ uint32_t tx1g_num_buffers; -+ uint32_t rx1g_num_buffers; -+ uint32_t tx2g5_num_buffers; /* Not supported yet by LLD */ -+ uint32_t rx2g5_num_buffers; /* Not supported yet by LLD */ -+ uint32_t tx10g_num_buffers; -+ uint32_t rx10g_num_buffers; -+ uint32_t oh_num_buffers; -+ uint32_t shared_ext_buffers; -+ -+ /* open DMAs */ -+ uint32_t tx_1g_dmas; -+ uint32_t rx_1g_dmas; -+ uint32_t tx_2g5_dmas; /* Not supported yet by LLD */ -+ uint32_t rx_2g5_dmas; /* Not supported yet by LLD */ -+ uint32_t tx_10g_dmas; -+ uint32_t rx_10g_dmas; -+ uint32_t oh_dmas; -+ uint32_t shared_ext_open_dma; -+ -+ /* Tnums */ -+ uint32_t tx_1g_tnums; -+ uint32_t rx_1g_tnums; -+ uint32_t tx_2g5_tnums; /* Not supported yet by LLD */ -+ uint32_t rx_2g5_tnums; /* Not supported yet by LLD */ -+ uint32_t tx_10g_tnums; -+ uint32_t rx_10g_tnums; -+ uint32_t oh_tnums; -+ uint32_t shared_ext_tnums; -+}; -+ -+typedef struct { -+ uint8_t id; -+ char name[10]; -+ bool active; -+ bool pcdActive; -+ bool prsActive; -+ bool kgActive; -+ bool ccActive; -+ bool plcrActive; -+ e_LnxWrpFmPortPcdDefUseCase defPcd; -+ uint32_t usedSchemes; -+ uint8_t totalNumOfSharedSchemes; -+ uint8_t sharedSchemesBase; -+ uint8_t numOfSchemesUsed; -+ uint8_t defNetEnvId; -+ uint64_t fmPhysBaseAddr; -+ uint64_t fmBaseAddr; -+ uint32_t fmMemSize; -+ uint64_t fmMuramPhysBaseAddr; -+ uint64_t fmMuramBaseAddr; -+ uint32_t fmMuramMemSize; -+ uint64_t fmRtcPhysBaseAddr; -+ uint64_t fmRtcBaseAddr; -+ uint32_t fmRtcMemSize; -+ uint64_t fmVspPhysBaseAddr; -+ uint64_t fmVspBaseAddr; -+ uint32_t fmVspMemSize; -+ int irq; -+ int err_irq; -+ t_WrpFmDevSettings fmDevSettings; -+ t_WrpFmPcdDevSettings fmPcdDevSettings; -+ t_Handle h_Dev; -+ uint16_t hcCh; -+ -+ t_Handle h_MuramDev; -+ t_Handle h_PcdDev; -+ t_Handle h_RtcDev; -+ -+ t_Handle h_DsarRxPort; -+ t_Handle h_DsarTxPort; -+ -+ t_LnxWrpFmPortDev hcPort; -+ t_LnxWrpFmPortDev opPorts[FM_MAX_NUM_OF_OH_PORTS-1]; -+ t_LnxWrpFmPortDev rxPorts[FM_MAX_NUM_OF_RX_PORTS]; -+ t_LnxWrpFmPortDev txPorts[FM_MAX_NUM_OF_TX_PORTS]; -+ t_LnxWrpFmMacDev macs[FM_MAX_NUM_OF_MACS]; -+ struct fm_active_ports fm_active_ports_info; -+ struct fm_resource_settings fm_resource_settings_info; -+ -+ struct device *dev; -+ struct resource *res; -+ int major; -+ struct class *fm_class; -+ struct device_attribute *dev_attr_stats; -+ struct device_attribute *dev_attr_regs; -+ struct device_attribute *dev_attr_risc_load; -+ -+ struct device_attribute *dev_pcd_attr_stats; -+ struct device_attribute *dev_plcr_attr_regs; -+ struct device_attribute *dev_prs_attr_regs; -+ struct device_attribute *dev_fm_fpm_attr_regs; -+ struct device_attribute *dev_fm_kg_attr_regs; -+ struct device_attribute *dev_fm_kg_pe_attr_regs; -+ struct device_attribute *dev_attr_muram_free_size; -+ struct device_attribute *dev_attr_fm_ctrl_code_ver; -+ -+ -+ struct qman_fq *hc_tx_conf_fq, *hc_tx_err_fq, *hc_tx_fq; -+} t_LnxWrpFmDev; -+ -+typedef struct { -+ t_LnxWrpFmDev *p_FmDevs[INTG_MAX_NUM_OF_FM]; -+} t_LnxWrpFm; -+#define LNXWRP_FM_OBJECT(ptr) LIST_OBJECT(ptr, t_LnxWrpFm, fms[((t_LnxWrpFmDev *)ptr)->id]) -+ -+ -+t_Error LnxwrpFmIOCTL(t_LnxWrpFmDev *p_LnxWrpFmDev, unsigned int cmd, unsigned long arg, bool compat); -+t_Error LnxwrpFmPortIOCTL(t_LnxWrpFmPortDev *p_LnxWrpFmPortDev, unsigned int cmd, unsigned long arg, bool compat); -+ -+ -+#if 0 -+static __inline__ t_Error AllocSchemesForPort(t_LnxWrpFmDev *p_LnxWrpFmDev, uint8_t numSchemes, uint8_t *p_BaseSchemeNum) -+{ -+ uint32_t schemeMask; -+ uint8_t i; -+ -+ if (!numSchemes) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, NO_MSG); -+ -+ schemeMask = 0x80000000; -+ *p_BaseSchemeNum = 0xff; -+ -+ for (i=0; schemeMask && numSchemes; schemeMask>>=1, i++) -+ if ((p_LnxWrpFmDev->usedSchemes & schemeMask) == 0) -+ { -+ p_LnxWrpFmDev->usedSchemes |= schemeMask; -+ numSchemes--; -+ if (*p_BaseSchemeNum==0xff) -+ *p_BaseSchemeNum = i; -+ } -+ else if (*p_BaseSchemeNum!=0xff) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("Fragmentation on schemes array!!!")); -+ -+ if (numSchemes) -+ RETURN_ERROR(MINOR, E_FULL, ("schemes!!!")); -+ return E_OK; -+} -+#endif -+ -+void LnxWrpPCDIOCTLTypeChecking(void); -+void LnxWrpPCDIOCTLEnumChecking(void); -+ -+#endif /* __LNXWRP_FM_H__ */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_fm_port.c -@@ -0,0 +1,1507 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ @File lnxwrp_fm_port.c -+ -+ @Description FMD wrapper - FMan port functions. -+ -+*/ -+ -+#include -+#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS) -+#define MODVERSIONS -+#endif -+#ifdef MODVERSIONS -+#include -+#endif /* MODVERSIONS */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#ifndef CONFIG_FMAN_ARM -+#include -+#endif -+#include -+ -+#include "sprint_ext.h" -+#include "fm_common.h" -+#include "lnxwrp_fsl_fman.h" -+#include "fm_port_ext.h" -+#if (DPAA_VERSION >= 11) -+#include "fm_vsp_ext.h" -+#endif /* DPAA_VERSION >= 11 */ -+#include "fm_ioctls.h" -+#include "lnxwrp_resources.h" -+#include "lnxwrp_sysfs_fm_port.h" -+ -+#define __ERR_MODULE__ MODULE_FM -+ -+extern struct device_node *GetFmAdvArgsDevTreeNode (uint8_t fmIndx); -+ -+/* TODO: duplicated, see lnxwrp_fm.c */ -+#define ADD_ADV_CONFIG_NO_RET(_func, _param)\ -+do {\ -+ if (i < max) {\ -+ p_Entry = &p_Entrys[i];\ -+ p_Entry->p_Function = _func;\ -+ _param\ -+ i++;\ -+ } else {\ -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE,\ -+ ("Number of advanced-configuration entries exceeded"));\ -+ } \ -+} while (0) -+ -+#ifndef CONFIG_FMAN_ARM -+#define IS_T1023_T1024 (SVR_SOC_VER(mfspr(SPRN_SVR)) == SVR_T1024 || \ -+ SVR_SOC_VER(mfspr(SPRN_SVR)) == SVR_T1023) -+#endif -+ -+static volatile int hcFrmRcv/* = 0 */; -+static spinlock_t lock; -+ -+static enum qman_cb_dqrr_result qm_tx_conf_dqrr_cb(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry -+ *dq) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = ((t_FmTestFq *) fq)->h_Arg; -+ unsigned long flags; -+ -+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ -+{ -+ /* extract the HC frame address */ -+#ifdef CONFIG_ARM -+ uint32_t *hcf_va = XX_PhysToVirt(((struct qm_fd *)&dq->fd)->addr); -+#else -+ uint64_t hcf_va = (uint64_t)XX_PhysToVirt(((struct qm_fd *)&dq->fd)->addr); -+#endif -+ int hcf_l = ((struct qm_fd *)&dq->fd)->length20; -+ int i; -+ -+ /* 32b byteswap of all data in the HC Frame */ -+ for(i = 0; i < hcf_l / 4; ++i) -+ ((uint32_t *)(hcf_va))[i] = -+ ___constant_swab32(((uint32_t *)(hcf_va))[i]); -+} -+{ -+ /* byteswap FD's 40bit address field LE to BE*/ -+ uint8_t t; -+ -+ t = ((uint8_t*)&dq->fd)[6]; -+ ((uint8_t*)&dq->fd)[6] = ((uint8_t*)&dq->fd)[5]; -+ ((uint8_t*)&dq->fd)[5] = ((uint8_t*)&dq->fd)[4]; -+ ((uint8_t*)&dq->fd)[4] = ((uint8_t*)&dq->fd)[3]; -+ ((uint8_t*)&dq->fd)[3] = ((uint8_t*)&dq->fd)[7]; -+ ((uint8_t*)&dq->fd)[7] = t; -+} -+ -+#endif -+ FM_PCD_HcTxConf(p_LnxWrpFmDev->h_PcdDev, (t_DpaaFD *)&dq->fd); -+ spin_lock_irqsave(&lock, flags); -+ hcFrmRcv--; -+ spin_unlock_irqrestore(&lock, flags); -+ -+ return qman_cb_dqrr_consume; -+} -+ -+static enum qman_cb_dqrr_result qm_tx_dqrr_cb(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq) -+{ -+ WARN(1, "FMD: failure at %s:%d/%s()!\n", __FILE__, __LINE__, -+ __func__); -+ return qman_cb_dqrr_consume; -+} -+ -+static void qm_err_cb(struct qman_portal *portal, -+ struct qman_fq *fq, const struct qm_mr_entry *msg) -+{ -+ WARN(1, "FMD: failure at %s:%d/%s()!\n", __FILE__, __LINE__, -+ __func__); -+} -+ -+static struct qman_fq *FqAlloc(t_LnxWrpFmDev * p_LnxWrpFmDev, -+ uint32_t fqid, -+ uint32_t flags, uint16_t channel, uint8_t wq) -+{ -+ int _errno; -+ struct qman_fq *fq = NULL; -+ t_FmTestFq *p_FmtFq; -+ struct qm_mcc_initfq initfq; -+ -+ p_FmtFq = (t_FmTestFq *) XX_Malloc(sizeof(t_FmTestFq)); -+ if (!p_FmtFq) { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FQ obj!!!")); -+ return NULL; -+ } -+ -+ p_FmtFq->fq_base.cb.dqrr = ((flags & QMAN_FQ_FLAG_NO_ENQUEUE) -+ ? qm_tx_conf_dqrr_cb -+ : qm_tx_dqrr_cb); -+ p_FmtFq->fq_base.cb.ern = qm_err_cb; -+ /* p_FmtFq->fq_base.cb.fqs = qm_err_cb; */ -+ /* qm_err_cb wrongly called when the FQ is parked */ -+ p_FmtFq->fq_base.cb.fqs = NULL; -+ p_FmtFq->h_Arg = (t_Handle) p_LnxWrpFmDev; -+ if (fqid == 0) { -+ flags |= QMAN_FQ_FLAG_DYNAMIC_FQID; -+ flags &= ~QMAN_FQ_FLAG_NO_MODIFY; -+ } else { -+ flags &= ~QMAN_FQ_FLAG_DYNAMIC_FQID; -+ } -+ -+ if (qman_create_fq(fqid, flags, &p_FmtFq->fq_base)) { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FQ obj - qman_new_fq!!!")); -+ XX_Free(p_FmtFq); -+ return NULL; -+ } -+ fq = &p_FmtFq->fq_base; -+ -+ if (!(flags & QMAN_FQ_FLAG_NO_MODIFY)) { -+ initfq.we_mask = QM_INITFQ_WE_DESTWQ; -+ initfq.fqd.dest.channel = channel; -+ initfq.fqd.dest.wq = wq; -+ -+ _errno = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq); -+ if (unlikely(_errno < 0)) { -+ REPORT_ERROR(MAJOR, E_NO_MEMORY, -+ ("FQ obj - qman_init_fq!!!")); -+ qman_destroy_fq(fq, 0); -+ XX_Free(p_FmtFq); -+ return NULL; -+ } -+ } -+ -+ DBG(TRACE, -+ ("fqid %d, flags 0x%08x, channel %d, wq %d", qman_fq_fqid(fq), -+ flags, channel, wq)); -+ -+ return fq; -+} -+ -+static void FqFree(struct qman_fq *fq) -+{ -+ int _errno; -+ -+ _errno = qman_retire_fq(fq, NULL); -+ if (unlikely(_errno < 0)) -+ printk(KERN_WARNING "qman_retire_fq(%u) = %d\n", qman_fq_fqid(fq), _errno); -+ -+ _errno = qman_oos_fq(fq); -+ if (unlikely(_errno < 0)) -+ printk(KERN_WARNING "qman_oos_fq(%u) = %d\n", qman_fq_fqid(fq), _errno); -+ -+ qman_destroy_fq(fq, 0); -+ XX_Free((t_FmTestFq *) fq); -+} -+ -+static t_Error QmEnqueueCB(t_Handle h_Arg, void *p_Fd) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = (t_LnxWrpFmDev *) h_Arg; -+ int _errno, timeout = 1000000; -+ unsigned long flags; -+ -+ ASSERT_COND(p_LnxWrpFmDev); -+ -+ spin_lock_irqsave(&lock, flags); -+ hcFrmRcv++; -+ spin_unlock_irqrestore(&lock, flags); -+ -+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ -+{ -+ /* byteswap FD's 40bit address field */ -+ uint8_t t; -+ -+ t = ((uint8_t*)p_Fd)[7]; -+ ((uint8_t*)p_Fd)[7] = ((uint8_t*)p_Fd)[3]; -+ ((uint8_t*)p_Fd)[3] = ((uint8_t*)p_Fd)[4]; -+ ((uint8_t*)p_Fd)[4] = ((uint8_t*)p_Fd)[5]; -+ ((uint8_t*)p_Fd)[5] = ((uint8_t*)p_Fd)[6]; -+ ((uint8_t*)p_Fd)[6] = t; -+} -+{ -+ /* extract the HC frame address */ -+#ifdef CONFIG_ARM -+ uint32_t *hcf_va = XX_PhysToVirt(((struct qm_fd *) p_Fd)->addr); -+#else -+ uint64_t hcf_va = (uint64_t)XX_PhysToVirt(((struct qm_fd *) p_Fd)->addr); -+#endif -+ int hcf_l = ((struct qm_fd *)p_Fd)->length20; -+ int i; -+ -+ /* 32b byteswap of all data in the HC Frame */ -+ for(i = 0; i < hcf_l / 4; ++i) -+ ((uint32_t *)(hcf_va))[i] = -+ ___constant_swab32(((uint32_t *)(hcf_va))[i]); -+} -+#endif -+ -+ _errno = qman_enqueue(p_LnxWrpFmDev->hc_tx_fq, (struct qm_fd *) p_Fd, -+ 0); -+ if (_errno) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, -+ ("qman_enqueue() failed")); -+ -+ while (hcFrmRcv && --timeout) { -+ udelay(1); -+ cpu_relax(); -+ } -+ if (timeout == 0) { -+ dump_stack(); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, -+ ("timeout waiting for Tx confirmation")); -+ return E_WRITE_FAILED; -+ } -+ -+ return E_OK; -+} -+ -+static t_LnxWrpFmPortDev *ReadFmPortDevTreeNode(struct platform_device -+ *of_dev) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev; -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev; -+ struct device_node *fm_node, *port_node; -+ struct resource res; -+ const uint32_t *uint32_prop; -+ int _errno = 0, lenp; -+ uint32_t tmp_prop; -+ -+#ifdef CONFIG_FMAN_P1023 -+ static unsigned char have_oh_port/* = 0 */; -+#endif -+ -+ port_node = of_node_get(of_dev->dev.of_node); -+ -+ /* Get the FM node */ -+ fm_node = of_get_parent(port_node); -+ if (unlikely(fm_node == NULL)) { -+ REPORT_ERROR(MAJOR, E_NO_DEVICE, -+ ("of_get_parent() = %d", _errno)); -+ return NULL; -+ } -+ -+ p_LnxWrpFmDev = -+ dev_get_drvdata(&of_find_device_by_node(fm_node)->dev); -+ of_node_put(fm_node); -+ -+ /* if fm_probe() failed, no point in going further with port probing */ -+ if (p_LnxWrpFmDev == NULL) -+ return NULL; -+ -+ uint32_prop = -+ (uint32_t *) of_get_property(port_node, "cell-index", &lenp); -+ if (unlikely(uint32_prop == NULL)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("of_get_property(%s, cell-index) failed", -+ port_node->full_name)); -+ return NULL; -+ } -+ tmp_prop = be32_to_cpu(*uint32_prop); -+ if (WARN_ON(lenp != sizeof(uint32_t))) -+ return NULL; -+ if (of_device_is_compatible(port_node, "fsl,fman-port-oh")) { -+ if (unlikely(tmp_prop >= FM_MAX_NUM_OF_OH_PORTS)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("of_get_property(%s, cell-index) failed", -+ port_node->full_name)); -+ return NULL; -+ } -+ -+#ifdef CONFIG_FMAN_P1023 -+ /* Beware, this can be done when there is only -+ one FMan to be initialized */ -+ if (!have_oh_port) { -+ have_oh_port = 1; /* first OP/HC port -+ is used for host command */ -+#else -+ /* Here it is hardcoded the use of the OH port 1 -+ (with cell-index 0) */ -+ if (tmp_prop == 0) { -+#endif -+ p_LnxWrpFmPortDev = &p_LnxWrpFmDev->hcPort; -+ p_LnxWrpFmPortDev->id = 0; -+ /* -+ p_LnxWrpFmPortDev->id = *uint32_prop-1; -+ p_LnxWrpFmPortDev->id = *uint32_prop; -+ */ -+ p_LnxWrpFmPortDev->settings.param.portType = -+ e_FM_PORT_TYPE_OH_HOST_COMMAND; -+ } else { -+ p_LnxWrpFmPortDev = -+ &p_LnxWrpFmDev->opPorts[tmp_prop - 1]; -+ p_LnxWrpFmPortDev->id = tmp_prop- 1; -+ p_LnxWrpFmPortDev->settings.param.portType = -+ e_FM_PORT_TYPE_OH_OFFLINE_PARSING; -+ } -+ p_LnxWrpFmPortDev->settings.param.portId = tmp_prop; -+ -+ uint32_prop = -+ (uint32_t *) of_get_property(port_node, -+ "fsl,qman-channel-id", -+ &lenp); -+ if (uint32_prop == NULL) { -+ /* -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("missing fsl,qman-channel-id")); -+ */ -+ XX_Print("FM warning: missing fsl,qman-channel-id" -+ " for OH port.\n"); -+ return NULL; -+ } -+ tmp_prop = be32_to_cpu(*uint32_prop); -+ if (WARN_ON(lenp != sizeof(uint32_t))) -+ return NULL; -+ p_LnxWrpFmPortDev->txCh = tmp_prop; -+ -+ p_LnxWrpFmPortDev->settings.param.specificParams.nonRxParams. -+ qmChannel = p_LnxWrpFmPortDev->txCh; -+ } else if (of_device_is_compatible(port_node, "fsl,fman-port-1g-tx")) { -+ if (unlikely(tmp_prop >= FM_MAX_NUM_OF_1G_TX_PORTS)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("of_get_property(%s, cell-index) failed", -+ port_node->full_name)); -+ return NULL; -+ } -+ p_LnxWrpFmPortDev = &p_LnxWrpFmDev->txPorts[tmp_prop]; -+ -+ p_LnxWrpFmPortDev->id = tmp_prop; -+ p_LnxWrpFmPortDev->settings.param.portId = -+ p_LnxWrpFmPortDev->id; -+ p_LnxWrpFmPortDev->settings.param.portType = e_FM_PORT_TYPE_TX; -+ -+ uint32_prop = (uint32_t *) of_get_property(port_node, -+ "fsl,qman-channel-id", &lenp); -+ if (uint32_prop == NULL) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("missing fsl,qman-channel-id")); -+ return NULL; -+ } -+ tmp_prop = be32_to_cpu(*uint32_prop); -+ if (WARN_ON(lenp != sizeof(uint32_t))) -+ return NULL; -+ p_LnxWrpFmPortDev->txCh = tmp_prop; -+ p_LnxWrpFmPortDev-> -+ settings.param.specificParams.nonRxParams.qmChannel = -+ p_LnxWrpFmPortDev->txCh; -+ } else if (of_device_is_compatible(port_node, "fsl,fman-port-10g-tx")) { -+ if (unlikely(tmp_prop>= FM_MAX_NUM_OF_10G_TX_PORTS)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("of_get_property(%s, cell-index) failed", -+ port_node->full_name)); -+ return NULL; -+ } -+ p_LnxWrpFmPortDev = &p_LnxWrpFmDev->txPorts[tmp_prop + -+ FM_MAX_NUM_OF_1G_TX_PORTS]; -+#ifndef CONFIG_FMAN_ARM -+ if (IS_T1023_T1024) -+ p_LnxWrpFmPortDev = &p_LnxWrpFmDev->txPorts[*uint32_prop]; -+#endif -+ -+ p_LnxWrpFmPortDev->id = tmp_prop; -+ p_LnxWrpFmPortDev->settings.param.portId = -+ p_LnxWrpFmPortDev->id; -+ p_LnxWrpFmPortDev->settings.param.portType = -+ e_FM_PORT_TYPE_TX_10G; -+ uint32_prop = (uint32_t *) of_get_property(port_node, -+ "fsl,qman-channel-id", &lenp); -+ if (uint32_prop == NULL) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("missing fsl,qman-channel-id")); -+ return NULL; -+ } -+ tmp_prop = be32_to_cpu(*uint32_prop); -+ if (WARN_ON(lenp != sizeof(uint32_t))) -+ return NULL; -+ p_LnxWrpFmPortDev->txCh = tmp_prop; -+ p_LnxWrpFmPortDev->settings.param.specificParams.nonRxParams. -+ qmChannel = p_LnxWrpFmPortDev->txCh; -+ } else if (of_device_is_compatible(port_node, "fsl,fman-port-1g-rx")) { -+ if (unlikely(tmp_prop >= FM_MAX_NUM_OF_1G_RX_PORTS)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("of_get_property(%s, cell-index) failed", -+ port_node->full_name)); -+ return NULL; -+ } -+ p_LnxWrpFmPortDev = &p_LnxWrpFmDev->rxPorts[tmp_prop]; -+ -+ p_LnxWrpFmPortDev->id = tmp_prop; -+ p_LnxWrpFmPortDev->settings.param.portId = -+ p_LnxWrpFmPortDev->id; -+ p_LnxWrpFmPortDev->settings.param.portType = e_FM_PORT_TYPE_RX; -+ if (p_LnxWrpFmDev->pcdActive) -+ p_LnxWrpFmPortDev->defPcd = p_LnxWrpFmDev->defPcd; -+ } else if (of_device_is_compatible(port_node, "fsl,fman-port-10g-rx")) { -+ if (unlikely(tmp_prop >= FM_MAX_NUM_OF_10G_RX_PORTS)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("of_get_property(%s, cell-index) failed", -+ port_node->full_name)); -+ return NULL; -+ } -+ p_LnxWrpFmPortDev = &p_LnxWrpFmDev->rxPorts[tmp_prop + -+ FM_MAX_NUM_OF_1G_RX_PORTS]; -+ -+#ifndef CONFIG_FMAN_ARM -+ if (IS_T1023_T1024) -+ p_LnxWrpFmPortDev = &p_LnxWrpFmDev->rxPorts[*uint32_prop]; -+#endif -+ -+ p_LnxWrpFmPortDev->id = tmp_prop; -+ p_LnxWrpFmPortDev->settings.param.portId = -+ p_LnxWrpFmPortDev->id; -+ p_LnxWrpFmPortDev->settings.param.portType = -+ e_FM_PORT_TYPE_RX_10G; -+ if (p_LnxWrpFmDev->pcdActive) -+ p_LnxWrpFmPortDev->defPcd = p_LnxWrpFmDev->defPcd; -+ } else { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal port type")); -+ return NULL; -+ } -+ -+ _errno = of_address_to_resource(port_node, 0, &res); -+ if (unlikely(_errno < 0)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("of_address_to_resource() = %d", _errno)); -+ return NULL; -+ } -+ -+ p_LnxWrpFmPortDev->dev = &of_dev->dev; -+ p_LnxWrpFmPortDev->baseAddr = 0; -+ p_LnxWrpFmPortDev->phys_baseAddr = res.start; -+ p_LnxWrpFmPortDev->memSize = res.end + 1 - res.start; -+ p_LnxWrpFmPortDev->settings.param.h_Fm = p_LnxWrpFmDev->h_Dev; -+ p_LnxWrpFmPortDev->h_LnxWrpFmDev = (t_Handle) p_LnxWrpFmDev; -+ -+ of_node_put(port_node); -+ -+ p_LnxWrpFmPortDev->active = TRUE; -+ -+#if defined(CONFIG_FMAN_DISABLE_OH_TO_REUSE_RESOURCES) -+ /* for performance mode no OH port available. */ -+ if (p_LnxWrpFmPortDev->settings.param.portType == -+ e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ p_LnxWrpFmPortDev->active = FALSE; -+#endif -+ -+ return p_LnxWrpFmPortDev; -+} -+ -+struct device_node * GetFmPortAdvArgsDevTreeNode (struct device_node *fm_node, -+ e_FmPortType portType, -+ uint8_t portId) -+{ -+ struct device_node *port_node; -+ const uint32_t *uint32_prop; -+ int lenp; -+ char *portTypeString; -+ uint32_t tmp_prop; -+ -+ switch(portType) { -+ case e_FM_PORT_TYPE_OH_OFFLINE_PARSING: -+ portTypeString = "fsl,fman-port-op-extended-args"; -+ break; -+ case e_FM_PORT_TYPE_TX: -+ portTypeString = "fsl,fman-port-1g-tx-extended-args"; -+ break; -+ case e_FM_PORT_TYPE_TX_10G: -+ portTypeString = "fsl,fman-port-10g-tx-extended-args"; -+ break; -+ case e_FM_PORT_TYPE_RX: -+ portTypeString = "fsl,fman-port-1g-rx-extended-args"; -+ break; -+ case e_FM_PORT_TYPE_RX_10G: -+ portTypeString = "fsl,fman-port-10g-rx-extended-args"; -+ break; -+ default: -+ return NULL; -+ } -+ -+ for_each_child_of_node(fm_node, port_node) { -+ uint32_prop = (uint32_t *)of_get_property(port_node, "cell-index", &lenp); -+ if (unlikely(uint32_prop == NULL)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, -+ ("of_get_property(%s, cell-index) failed", -+ port_node->full_name)); -+ return NULL; -+ } -+ tmp_prop = be32_to_cpu(*uint32_prop); -+ if (WARN_ON(lenp != sizeof(uint32_t))) -+ return NULL; -+ if ((portId == tmp_prop) && -+ (of_device_is_compatible(port_node, portTypeString))) { -+ return port_node; -+ } -+ } -+ -+ return NULL; -+} -+ -+static t_Error CheckNConfigFmPortAdvArgs (t_LnxWrpFmPortDev *p_LnxWrpFmPortDev) -+{ -+ struct device_node *fm_node, *port_node; -+ t_Error err; -+ t_FmPortRsrc portRsrc; -+ const uint32_t *uint32_prop; -+ /*const char *str_prop;*/ -+ int lenp; -+#ifdef CONFIG_FMAN_PFC -+ uint8_t i, id, num_pools; -+ t_FmBufPoolDepletion poolDepletion; -+ -+ if (p_LnxWrpFmPortDev->settings.param.portType == e_FM_PORT_TYPE_RX || -+ p_LnxWrpFmPortDev->settings.param.portType == e_FM_PORT_TYPE_RX_10G) { -+ memset(&poolDepletion, 0, sizeof(t_FmBufPoolDepletion)); -+ poolDepletion.singlePoolModeEnable = true; -+ num_pools = p_LnxWrpFmPortDev->settings.param.specificParams.rxParams. -+ extBufPools.numOfPoolsUsed; -+ for (i = 0; i < num_pools; i++) { -+ id = p_LnxWrpFmPortDev->settings.param.specificParams.rxParams. -+ extBufPools.extBufPool[i].id; -+ poolDepletion.poolsToConsiderForSingleMode[id] = true; -+ } -+ -+ for (i = 0; i < CONFIG_FMAN_PFC_COS_COUNT; i++) -+ poolDepletion.pfcPrioritiesEn[i] = true; -+ -+ err = FM_PORT_ConfigPoolDepletion(p_LnxWrpFmPortDev->h_Dev, -+ &poolDepletion); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, ("FM_PORT_ConfigPoolDepletion() failed")); -+ } -+#endif -+ -+ fm_node = GetFmAdvArgsDevTreeNode(((t_LnxWrpFmDev *) p_LnxWrpFmPortDev->h_LnxWrpFmDev)->id); -+ if (!fm_node) /* no advance parameters for FMan */ -+ return E_OK; -+ -+ port_node = GetFmPortAdvArgsDevTreeNode(fm_node, -+ p_LnxWrpFmPortDev->settings.param.portType, -+ p_LnxWrpFmPortDev->settings.param.portId); -+ if (!port_node) /* no advance parameters for FMan-Port */ -+ return E_OK; -+ -+ uint32_prop = (uint32_t *)of_get_property(port_node, "num-tnums", &lenp); -+ if (uint32_prop) { -+ if (WARN_ON(lenp != sizeof(uint32_t)*2)) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, NO_MSG); -+ -+ portRsrc.num = be32_to_cpu(uint32_prop[0]); -+ portRsrc.extra = be32_to_cpu(uint32_prop[1]); -+ -+ if ((err = FM_PORT_ConfigNumOfTasks(p_LnxWrpFmPortDev->h_Dev, -+ &portRsrc)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ uint32_prop = (uint32_t *)of_get_property(port_node, "num-dmas", &lenp); -+ if (uint32_prop) { -+ if (WARN_ON(lenp != sizeof(uint32_t)*2)) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, NO_MSG); -+ -+ portRsrc.num = be32_to_cpu(uint32_prop[0]); -+ portRsrc.extra = be32_to_cpu(uint32_prop[1]); -+ -+ if ((err = FM_PORT_ConfigNumOfOpenDmas(p_LnxWrpFmPortDev->h_Dev, -+ &portRsrc)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ uint32_prop = (uint32_t *)of_get_property(port_node, "fifo-size", &lenp); -+ if (uint32_prop) { -+ if (WARN_ON(lenp != sizeof(uint32_t)*2)) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, NO_MSG); -+ -+ portRsrc.num = be32_to_cpu(uint32_prop[0]); -+ portRsrc.extra = be32_to_cpu(uint32_prop[1]); -+ -+ if ((err = FM_PORT_ConfigSizeOfFifo(p_LnxWrpFmPortDev->h_Dev, -+ &portRsrc)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ uint32_prop = (uint32_t *)of_get_property(port_node, "errors-to-discard", &lenp); -+ if (uint32_prop) { -+ if (WARN_ON(lenp != sizeof(uint32_t))) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, NO_MSG); -+ if ((err = FM_PORT_ConfigErrorsToDiscard(p_LnxWrpFmPortDev->h_Dev, -+ be32_to_cpu(uint32_prop[0]))) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ uint32_prop = (uint32_t *)of_get_property(port_node, "ar-tables-sizes", -+ &lenp); -+ if (uint32_prop) { -+ -+ if (WARN_ON(lenp != sizeof(uint32_t)*8)) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, NO_MSG); -+ if (WARN_ON(p_LnxWrpFmPortDev->settings.param.portType != -+ e_FM_PORT_TYPE_RX) && -+ (p_LnxWrpFmPortDev->settings.param.portType != -+ e_FM_PORT_TYPE_RX_10G)) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, -+ ("Auto Response is an Rx port atribute.")); -+ -+ memset(&p_LnxWrpFmPortDev->dsar_table_sizes, 0, sizeof(struct auto_res_tables_sizes)); -+ -+ p_LnxWrpFmPortDev->dsar_table_sizes.max_num_of_arp_entries = -+ (uint16_t)be32_to_cpu(uint32_prop[0]); -+ p_LnxWrpFmPortDev->dsar_table_sizes.max_num_of_echo_ipv4_entries = -+ (uint16_t)be32_to_cpu(uint32_prop[1]); -+ p_LnxWrpFmPortDev->dsar_table_sizes.max_num_of_ndp_entries = -+ (uint16_t)be32_to_cpu(uint32_prop[2]); -+ p_LnxWrpFmPortDev->dsar_table_sizes.max_num_of_echo_ipv6_entries = -+ (uint16_t)be32_to_cpu(uint32_prop[3]); -+ p_LnxWrpFmPortDev->dsar_table_sizes.max_num_of_snmp_ipv4_entries = -+ (uint16_t)be32_to_cpu(uint32_prop[4]); -+ p_LnxWrpFmPortDev->dsar_table_sizes.max_num_of_snmp_ipv6_entries = -+ (uint16_t)be32_to_cpu(uint32_prop[5]); -+ p_LnxWrpFmPortDev->dsar_table_sizes.max_num_of_snmp_oid_entries = -+ (uint16_t)be32_to_cpu(uint32_prop[6]); -+ p_LnxWrpFmPortDev->dsar_table_sizes.max_num_of_snmp_char = -+ (uint16_t)be32_to_cpu(uint32_prop[7]); -+ -+ uint32_prop = (uint32_t *)of_get_property(port_node, -+ "ar-filters-sizes", &lenp); -+ if (uint32_prop) { -+ if (WARN_ON(lenp != sizeof(uint32_t)*3)) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, NO_MSG); -+ -+ p_LnxWrpFmPortDev->dsar_table_sizes.max_num_of_ip_prot_filtering = -+ (uint16_t)be32_to_cpu(uint32_prop[0]); -+ p_LnxWrpFmPortDev->dsar_table_sizes.max_num_of_tcp_port_filtering = -+ (uint16_t)be32_to_cpu(uint32_prop[1]); -+ p_LnxWrpFmPortDev->dsar_table_sizes.max_num_of_udp_port_filtering = -+ (uint16_t)be32_to_cpu(uint32_prop[2]); -+ } -+ -+ if ((err = FM_PORT_ConfigDsarSupport(p_LnxWrpFmPortDev->h_Dev, -+ (t_FmPortDsarTablesSizes*)&p_LnxWrpFmPortDev->dsar_table_sizes)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+ -+ of_node_put(port_node); -+ of_node_put(fm_node); -+ -+ return E_OK; -+} -+ -+static t_Error CheckNSetFmPortAdvArgs (t_LnxWrpFmPortDev *p_LnxWrpFmPortDev) -+{ -+ struct device_node *fm_node, *port_node; -+ t_Error err; -+ const uint32_t *uint32_prop; -+ /*const char *str_prop;*/ -+ int lenp; -+ -+ fm_node = GetFmAdvArgsDevTreeNode(((t_LnxWrpFmDev *) p_LnxWrpFmPortDev->h_LnxWrpFmDev)->id); -+ if (!fm_node) /* no advance parameters for FMan */ -+ return E_OK; -+ -+ port_node = GetFmPortAdvArgsDevTreeNode(fm_node, -+ p_LnxWrpFmPortDev->settings.param.portType, -+ p_LnxWrpFmPortDev->settings.param.portId); -+ if (!port_node) /* no advance parameters for FMan-Port */ -+ return E_OK; -+ -+#if (DPAA_VERSION >= 11) -+ uint32_prop = (uint32_t *)of_get_property(port_node, "vsp-window", &lenp); -+ if (uint32_prop) { -+ t_FmPortVSPAllocParams portVSPAllocParams; -+ t_FmVspParams fmVspParams; -+ t_LnxWrpFmDev *p_LnxWrpFmDev; -+ uint8_t portId; -+ -+ p_LnxWrpFmDev = ((t_LnxWrpFmDev *)p_LnxWrpFmPortDev->h_LnxWrpFmDev); -+ -+ if (WARN_ON(lenp != sizeof(uint32_t)*2)) -+ RETURN_ERROR(MINOR, E_INVALID_VALUE, NO_MSG); -+ -+ if ((p_LnxWrpFmPortDev->settings.param.portType == e_FM_PORT_TYPE_TX) || -+ (p_LnxWrpFmPortDev->settings.param.portType == e_FM_PORT_TYPE_TX_10G) || -+ ((p_LnxWrpFmPortDev->settings.param.portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) && -+ p_LnxWrpFmPortDev->settings.frag_enabled)) -+ return E_OK; -+ -+ memset(&portVSPAllocParams, 0, sizeof(portVSPAllocParams)); -+ memset(&fmVspParams, 0, sizeof(fmVspParams)); -+ -+ portVSPAllocParams.numOfProfiles = (uint8_t)be32_to_cpu(uint32_prop[0]); -+ portVSPAllocParams.dfltRelativeId = (uint8_t)be32_to_cpu(uint32_prop[1]); -+ fmVspParams.h_Fm = p_LnxWrpFmDev->h_Dev; -+ -+ fmVspParams.portParams.portType = p_LnxWrpFmPortDev->settings.param.portType; -+ fmVspParams.portParams.portId = p_LnxWrpFmPortDev->settings.param.portId; -+ fmVspParams.relativeProfileId = portVSPAllocParams.dfltRelativeId; -+ -+ if (p_LnxWrpFmPortDev->settings.param.portType != e_FM_PORT_TYPE_OH_OFFLINE_PARSING) -+ { -+ portId = fmVspParams.portParams.portId; -+ if (p_LnxWrpFmPortDev->settings.param.portType == e_FM_PORT_TYPE_RX_10G){ -+#ifndef CONFIG_FMAN_ARM -+ if (!(IS_T1023_T1024)) -+#endif -+ portId += FM_MAX_NUM_OF_1G_RX_PORTS; -+ } -+ portVSPAllocParams.h_FmTxPort = -+ p_LnxWrpFmDev->txPorts[portId].h_Dev; -+ fmVspParams.liodnOffset = -+ p_LnxWrpFmDev->rxPorts[portId].settings.param.specificParams.rxParams.liodnOffset; -+ memcpy(&fmVspParams.extBufPools, -+ &p_LnxWrpFmPortDev->settings.param.specificParams.rxParams.extBufPools, -+ sizeof(t_FmExtPools)); -+ } -+ else -+ { -+ memcpy(&fmVspParams.extBufPools, -+ &p_LnxWrpFmPortDev->opExtPools, -+ sizeof(t_FmExtPools)); -+ } -+ -+ if ((err = FM_PORT_VSPAlloc(p_LnxWrpFmPortDev->h_Dev, -+ &portVSPAllocParams)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ /* We're initializing only the default VSP that are being used by the Linux-Ethernet-driver */ -+ if ((p_LnxWrpFmPortDev->settings.param.portType == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) && -+ !p_LnxWrpFmPortDev->opExtPools.numOfPoolsUsed) -+ return E_OK; -+ -+ p_LnxWrpFmPortDev->h_DfltVsp = FM_VSP_Config(&fmVspParams); -+ if (!p_LnxWrpFmPortDev->h_DfltVsp) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("default-VSP for port!")); -+ -+ if ((err = FM_VSP_ConfigBufferPrefixContent(p_LnxWrpFmPortDev->h_DfltVsp, -+ &p_LnxWrpFmPortDev->buffPrefixContent)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ -+ if ((err = FM_VSP_Init(p_LnxWrpFmPortDev->h_DfltVsp)) != E_OK) -+ RETURN_ERROR(MINOR, err, NO_MSG); -+ } -+#else -+UNUSED(err); UNUSED(uint32_prop); UNUSED(lenp); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ of_node_put(port_node); -+ of_node_put(fm_node); -+ -+ return E_OK; -+} -+ -+static t_Error ConfigureFmPortDev(t_LnxWrpFmPortDev *p_LnxWrpFmPortDev) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = -+ (t_LnxWrpFmDev *) p_LnxWrpFmPortDev->h_LnxWrpFmDev; -+ struct resource *dev_res; -+ -+ if (!p_LnxWrpFmPortDev->active) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("FM port not configured!!!")); -+ -+ dev_res = -+ __devm_request_region(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->res, -+ p_LnxWrpFmPortDev->phys_baseAddr, -+ p_LnxWrpFmPortDev->memSize, -+ "fman-port-hc"); -+ if (unlikely(dev_res == NULL)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, -+ ("__devm_request_region() failed")); -+ p_LnxWrpFmPortDev->baseAddr = -+ PTR_TO_UINT(devm_ioremap -+ (p_LnxWrpFmDev->dev, -+ p_LnxWrpFmPortDev->phys_baseAddr, -+ p_LnxWrpFmPortDev->memSize)); -+ if (unlikely(p_LnxWrpFmPortDev->baseAddr == 0)) -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, -+ ("devm_ioremap() failed")); -+ -+ p_LnxWrpFmPortDev->settings.param.baseAddr = -+ p_LnxWrpFmPortDev->baseAddr; -+ -+ return E_OK; -+} -+ -+static t_Error InitFmPortDev(t_LnxWrpFmPortDev *p_LnxWrpFmPortDev) -+{ -+#define MY_ADV_CONFIG_CHECK_END \ -+ RETURN_ERROR(MAJOR, E_INVALID_SELECTION,\ -+ ("Advanced configuration routine"));\ -+ if (errCode != E_OK)\ -+ RETURN_ERROR(MAJOR, errCode, NO_MSG);\ -+ } -+ -+ int i = 0; -+ -+ if (!p_LnxWrpFmPortDev->active || p_LnxWrpFmPortDev->h_Dev) -+ return E_INVALID_STATE; -+ -+ p_LnxWrpFmPortDev->h_Dev = -+ FM_PORT_Config(&p_LnxWrpFmPortDev->settings.param); -+ if (p_LnxWrpFmPortDev->h_Dev == NULL) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("FM-port")); -+ -+#ifndef FM_QMI_NO_DEQ_OPTIONS_SUPPORT -+ if ((p_LnxWrpFmPortDev->settings.param.portType == -+ e_FM_PORT_TYPE_TX_10G) -+ || (p_LnxWrpFmPortDev->settings.param.portType == -+ e_FM_PORT_TYPE_TX)) { -+ t_Error errCode = E_OK; -+ errCode = -+ FM_PORT_ConfigDeqHighPriority(p_LnxWrpFmPortDev->h_Dev, -+ TRUE); -+ if (errCode != E_OK) -+ RETURN_ERROR(MAJOR, errCode, NO_MSG); -+ errCode = -+ FM_PORT_ConfigDeqPrefetchOption(p_LnxWrpFmPortDev->h_Dev, -+ e_FM_PORT_DEQ_FULL_PREFETCH); -+ if (errCode -+ != E_OK) -+ RETURN_ERROR(MAJOR, errCode, NO_MSG); -+ } -+#endif /* !FM_QMI_NO_DEQ_OPTIONS_SUPPORT */ -+ -+#ifndef CONFIG_FMAN_ARM -+#ifdef FM_BCB_ERRATA_BMI_SW001 -+/* Configure BCB workaround on Rx ports, only for B4860 rev1 */ -+#define SVR_SECURITY_MASK 0x00080000 -+#define SVR_PERSONALITY_MASK 0x0000FF00 -+#define SVR_VER_IGNORE_MASK (SVR_SECURITY_MASK | SVR_PERSONALITY_MASK) -+#define SVR_B4860_REV1_VALUE 0x86800010 -+ -+ if ((p_LnxWrpFmPortDev->settings.param.portType == -+ e_FM_PORT_TYPE_RX_10G) || -+ (p_LnxWrpFmPortDev->settings.param.portType == -+ e_FM_PORT_TYPE_RX)) { -+ unsigned int svr; -+ -+ svr = mfspr(SPRN_SVR); -+ -+ if ((svr & ~SVR_VER_IGNORE_MASK) == SVR_B4860_REV1_VALUE) -+ FM_PORT_ConfigBCBWorkaround(p_LnxWrpFmPortDev->h_Dev); -+ } -+#endif /* FM_BCB_ERRATA_BMI_SW001 */ -+#endif /* CONFIG_FMAN_ARM */ -+/* Call the driver's advanced configuration routines, if requested: -+ Compare the function pointer of each entry to the available routines, -+ and invoke the matching routine with proper casting of arguments. */ -+ while (p_LnxWrpFmPortDev->settings.advConfig[i].p_Function -+ && (i < FM_MAX_NUM_OF_ADV_SETTINGS)) { -+ -+/* TODO: Change this MACRO */ -+ ADV_CONFIG_CHECK_START( -+ &(p_LnxWrpFmPortDev->settings.advConfig[i])) -+ -+ ADV_CONFIG_CHECK(p_LnxWrpFmPortDev->h_Dev, -+ FM_PORT_ConfigBufferPrefixContent, -+ NCSW_PARAMS(1, -+ (t_FmBufferPrefixContent *))) -+ -+ if ((p_LnxWrpFmPortDev->settings.param.portType == -+ e_FM_PORT_TYPE_OH_OFFLINE_PARSING) && -+ (p_LnxWrpFmPortDev->settings.frag_enabled == TRUE)) { -+ -+ ADV_CONFIG_CHECK(p_LnxWrpFmPortDev->h_Dev, -+ FM_PORT_ConfigExtBufPools, -+ NCSW_PARAMS(1, (t_FmExtPools *))) -+ -+ /* this define contains an else */ -+ MY_ADV_CONFIG_CHECK_END -+ } -+ -+ /* Advance to next advanced configuration entry */ -+ i++; -+ } -+ -+ -+ if ((p_LnxWrpFmPortDev->settings.param.portType != e_FM_PORT_TYPE_TX) && -+ (p_LnxWrpFmPortDev->settings.param.portType != e_FM_PORT_TYPE_TX_10G)) { -+ if (FM_PORT_ConfigErrorsToDiscard(p_LnxWrpFmPortDev->h_Dev, (FM_PORT_FRM_ERR_IPRE | -+ FM_PORT_FRM_ERR_IPR_NCSP | -+ FM_PORT_FRM_ERR_CLS_DISCARD)) !=E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ } -+ -+ if (CheckNConfigFmPortAdvArgs(p_LnxWrpFmPortDev) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ -+ if (FM_PORT_Init(p_LnxWrpFmPortDev->h_Dev) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ -+ if (CheckNSetFmPortAdvArgs(p_LnxWrpFmPortDev) != E_OK) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+ -+/* FMan Fifo sizes behind the scene": -+ * Using the following formulae (*), under a set of simplifying assumptions (.): -+ * . all ports are configured in Normal Mode (rather than Independent Mode) -+ * . the DPAA Eth driver allocates buffers of size: -+ * . MAXFRM + NET_IP_ALIGN + DPA_PRIV_DATA_SIZE + DPA_PARSE_RESULTS_SIZE -+ * + DPA_HASH_RESULTS_SIZE, i.e.: -+ * MAXFRM + 2 + 16 + sizeof(t_FmPrsResult) + 16, i.e.: -+ * MAXFRM + 66 -+ * . excessive buffer pools not accounted for -+ * -+ * * for Rx ports on P4080: -+ * . IFSZ = ceil(max(FMBM_EBMPI[PBS]) / 256) * 256 + 7 * 256 -+ * . no internal frame offset (FMBM_RIM[FOF] == 0) - otherwise, -+ * add up to 256 to the above -+ * -+ * * for Rx ports on P1023: -+ * . IFSZ = ceil(second_largest(FMBM_EBMPI[PBS] / 256)) * 256 + 7 * 256, -+ * if at least 2 bpools are configured -+ * . IFSZ = 8 * 256, if only a single bpool is configured -+ * -+ * * for Tx ports: -+ * . IFSZ = ceil(frame_size / 256) * 256 + 3 * 256 -+ * + FMBM_TFP[DPDE] * 256, i.e.: -+ * IFSZ = ceil(MAXFRM / 256) * 256 + 3 x 256 + FMBM_TFP[DPDE] * 256 -+ * -+ * * for OH ports on P4080: -+ * . IFSZ = ceil(frame_size / 256) * 256 + 1 * 256 + FMBM_PP[MXT] * 256 -+ * * for OH ports on P1023: -+ * . IFSZ = ceil(frame_size / 256) * 256 + 3 * 256 + FMBM_TFP[DPDE] * 256 -+ * * for both P4080 and P1023: -+ * . (conservative decisions, assuming that BMI must bring the entire -+ * frame, not only the frame header) -+ * . no internal frame offset (FMBM_OIM[FOF] == 0) - otherwise, -+ * add up to 256 to the above -+ * -+ * . for P4080/P5020/P3041/P2040, DPDE is: -+ * > 0 or 1, for 1Gb ports, HW default: 0 -+ * > 2..7 (recommended: 3..7) for 10Gb ports, HW default: 3 -+ * . for P1023, DPDE should be 1 -+ * -+ * . for P1023, MXT is in range (0..31) -+ * . for P4080, MXT is in range (0..63) -+ * -+ */ -+#if 0 -+ if ((p_LnxWrpFmPortDev->defPcd != e_NO_PCD) && -+ (InitFmPort3TupleDefPcd(p_LnxWrpFmPortDev) != E_OK)) -+ RETURN_ERROR(MAJOR, E_INVALID_STATE, NO_MSG); -+#endif -+ return E_OK; -+} -+ -+void fm_set_rx_port_params(struct fm_port *port, -+ struct fm_port_params *params) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *) port; -+ int i; -+ -+ p_LnxWrpFmPortDev->settings.param.specificParams.rxParams.errFqid = -+ params->errq; -+ p_LnxWrpFmPortDev->settings.param.specificParams.rxParams.dfltFqid = -+ params->defq; -+ p_LnxWrpFmPortDev->settings.param.specificParams.rxParams.extBufPools. -+ numOfPoolsUsed = params->num_pools; -+ for (i = 0; i < params->num_pools; i++) { -+ p_LnxWrpFmPortDev->settings.param.specificParams.rxParams. -+ extBufPools.extBufPool[i].id = -+ params->pool_param[i].id; -+ p_LnxWrpFmPortDev->settings.param.specificParams.rxParams. -+ extBufPools.extBufPool[i].size = -+ params->pool_param[i].size; -+ } -+ -+ p_LnxWrpFmPortDev->buffPrefixContent.privDataSize = -+ params->priv_data_size; -+ p_LnxWrpFmPortDev->buffPrefixContent.passPrsResult = -+ params->parse_results; -+ p_LnxWrpFmPortDev->buffPrefixContent.passHashResult = -+ params->hash_results; -+ p_LnxWrpFmPortDev->buffPrefixContent.passTimeStamp = -+ params->time_stamp; -+ p_LnxWrpFmPortDev->buffPrefixContent.dataAlign = -+ params->data_align; -+ p_LnxWrpFmPortDev->buffPrefixContent.manipExtraSpace = -+ params->manip_extra_space; -+ -+ ADD_ADV_CONFIG_START(p_LnxWrpFmPortDev->settings.advConfig, -+ FM_MAX_NUM_OF_ADV_SETTINGS) -+ -+ ADD_ADV_CONFIG_NO_RET(FM_PORT_ConfigBufferPrefixContent, -+ ARGS(1, -+ (&p_LnxWrpFmPortDev-> -+ buffPrefixContent))); -+ -+ ADD_ADV_CONFIG_END InitFmPortDev(p_LnxWrpFmPortDev); -+} -+EXPORT_SYMBOL(fm_set_rx_port_params); -+ -+/* this function is called from oh_probe as well, thus it contains oh port -+ * specific parameters (make sure everything is checked) */ -+void fm_set_tx_port_params(struct fm_port *port, -+ struct fm_port_params *params) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *) port; -+ -+ p_LnxWrpFmPortDev->settings.param.specificParams.nonRxParams.errFqid = -+ params->errq; -+ p_LnxWrpFmPortDev->settings.param.specificParams.nonRxParams. -+ dfltFqid = params->defq; -+ -+ p_LnxWrpFmPortDev->buffPrefixContent.privDataSize = -+ params->priv_data_size; -+ p_LnxWrpFmPortDev->buffPrefixContent.passPrsResult = -+ params->parse_results; -+ p_LnxWrpFmPortDev->buffPrefixContent.passHashResult = -+ params->hash_results; -+ p_LnxWrpFmPortDev->buffPrefixContent.passTimeStamp = -+ params->time_stamp; -+ p_LnxWrpFmPortDev->settings.frag_enabled = -+ params->frag_enable; -+ p_LnxWrpFmPortDev->buffPrefixContent.dataAlign = -+ params->data_align; -+ p_LnxWrpFmPortDev->buffPrefixContent.manipExtraSpace = -+ params->manip_extra_space; -+ -+ ADD_ADV_CONFIG_START(p_LnxWrpFmPortDev->settings.advConfig, -+ FM_MAX_NUM_OF_ADV_SETTINGS) -+ -+ ADD_ADV_CONFIG_NO_RET(FM_PORT_ConfigBufferPrefixContent, -+ ARGS(1, -+ (&p_LnxWrpFmPortDev-> -+ buffPrefixContent))); -+ -+ /* oh port specific parameter (for fragmentation only) */ -+ if ((p_LnxWrpFmPortDev->settings.param.portType == -+ e_FM_PORT_TYPE_OH_OFFLINE_PARSING) && -+ params->num_pools) { -+ int i; -+ -+ p_LnxWrpFmPortDev->opExtPools.numOfPoolsUsed = params->num_pools; -+ for (i = 0; i < params->num_pools; i++) { -+ p_LnxWrpFmPortDev->opExtPools.extBufPool[i].id = params->pool_param[i].id; -+ p_LnxWrpFmPortDev->opExtPools.extBufPool[i].size = params->pool_param[i].size; -+ } -+ -+ if (p_LnxWrpFmPortDev->settings.frag_enabled) -+ ADD_ADV_CONFIG_NO_RET(FM_PORT_ConfigExtBufPools, -+ ARGS(1, (&p_LnxWrpFmPortDev->opExtPools))); -+ } -+ -+ ADD_ADV_CONFIG_END InitFmPortDev(p_LnxWrpFmPortDev); -+} -+EXPORT_SYMBOL(fm_set_tx_port_params); -+ -+void fm_mac_set_handle(t_Handle h_lnx_wrp_fm_dev, -+ t_Handle h_fm_mac, -+ int mac_id) -+{ -+ t_LnxWrpFmDev *p_lnx_wrp_fm_dev = (t_LnxWrpFmDev *)h_lnx_wrp_fm_dev; -+ -+ p_lnx_wrp_fm_dev->macs[mac_id].h_Dev = h_fm_mac; -+ p_lnx_wrp_fm_dev->macs[mac_id].h_LnxWrpFmDev = h_lnx_wrp_fm_dev; -+} -+EXPORT_SYMBOL(fm_mac_set_handle); -+ -+static void LnxwrpFmPcdDevExceptionsCb(t_Handle h_App, -+ e_FmPcdExceptions exception) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = (t_LnxWrpFmDev *) h_App; -+ -+ ASSERT_COND(p_LnxWrpFmDev); -+ -+ DBG(INFO, ("got fm-pcd exception %d", exception)); -+ -+ /* do nothing */ -+ UNUSED(exception); -+} -+ -+static void LnxwrpFmPcdDevIndexedExceptionsCb(t_Handle h_App, -+ e_FmPcdExceptions exception, -+ uint16_t index) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = (t_LnxWrpFmDev *) h_App; -+ -+ ASSERT_COND(p_LnxWrpFmDev); -+ -+ DBG(INFO, -+ ("got fm-pcd-indexed exception %d, indx %d", exception, index)); -+ -+ /* do nothing */ -+ UNUSED(exception); -+ UNUSED(index); -+} -+ -+static t_Error InitFmPcdDev(t_LnxWrpFmDev *p_LnxWrpFmDev) -+{ -+ spin_lock_init(&lock); -+ -+ if (p_LnxWrpFmDev->pcdActive) { -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = &p_LnxWrpFmDev->hcPort; -+ t_FmPcdParams fmPcdParams; -+ t_Error err; -+ -+ memset(&fmPcdParams, 0, sizeof(fmPcdParams)); -+ fmPcdParams.h_Fm = p_LnxWrpFmDev->h_Dev; -+ fmPcdParams.prsSupport = p_LnxWrpFmDev->prsActive; -+ fmPcdParams.kgSupport = p_LnxWrpFmDev->kgActive; -+ fmPcdParams.plcrSupport = p_LnxWrpFmDev->plcrActive; -+ fmPcdParams.ccSupport = p_LnxWrpFmDev->ccActive; -+ fmPcdParams.numOfSchemes = FM_PCD_KG_NUM_OF_SCHEMES; -+ -+#ifndef CONFIG_GUEST_PARTITION -+ fmPcdParams.f_Exception = LnxwrpFmPcdDevExceptionsCb; -+ if (fmPcdParams.kgSupport) -+ fmPcdParams.f_ExceptionId = -+ LnxwrpFmPcdDevIndexedExceptionsCb; -+ fmPcdParams.h_App = p_LnxWrpFmDev; -+#endif /* !CONFIG_GUEST_PARTITION */ -+ -+#ifdef CONFIG_MULTI_PARTITION_SUPPORT -+ fmPcdParams.numOfSchemes = 0; -+ fmPcdParams.numOfClsPlanEntries = 0; -+ fmPcdParams.partitionId = 0; -+#endif /* CONFIG_MULTI_PARTITION_SUPPORT */ -+ fmPcdParams.useHostCommand = TRUE; -+ -+ p_LnxWrpFmDev->hc_tx_fq = -+ FqAlloc(p_LnxWrpFmDev, -+ 0, -+ QMAN_FQ_FLAG_TO_DCPORTAL, -+ p_LnxWrpFmPortDev->txCh, 0); -+ if (!p_LnxWrpFmDev->hc_tx_fq) -+ RETURN_ERROR(MAJOR, E_NULL_POINTER, -+ ("Frame queue allocation failed...")); -+ -+ p_LnxWrpFmDev->hc_tx_conf_fq = -+ FqAlloc(p_LnxWrpFmDev, -+ 0, -+ QMAN_FQ_FLAG_NO_ENQUEUE, -+ p_LnxWrpFmDev->hcCh, 7); -+ if (!p_LnxWrpFmDev->hc_tx_conf_fq) -+ RETURN_ERROR(MAJOR, E_NULL_POINTER, -+ ("Frame queue allocation failed...")); -+ -+ p_LnxWrpFmDev->hc_tx_err_fq = -+ FqAlloc(p_LnxWrpFmDev, -+ 0, -+ QMAN_FQ_FLAG_NO_ENQUEUE, -+ p_LnxWrpFmDev->hcCh, 7); -+ if (!p_LnxWrpFmDev->hc_tx_err_fq) -+ RETURN_ERROR(MAJOR, E_NULL_POINTER, -+ ("Frame queue allocation failed...")); -+ -+ fmPcdParams.hc.portBaseAddr = p_LnxWrpFmPortDev->baseAddr; -+ fmPcdParams.hc.portId = -+ p_LnxWrpFmPortDev->settings.param.portId; -+ fmPcdParams.hc.liodnBase = -+ p_LnxWrpFmPortDev->settings.param.liodnBase; -+ fmPcdParams.hc.errFqid = -+ qman_fq_fqid(p_LnxWrpFmDev->hc_tx_err_fq); -+ fmPcdParams.hc.confFqid = -+ qman_fq_fqid(p_LnxWrpFmDev->hc_tx_conf_fq); -+ fmPcdParams.hc.qmChannel = p_LnxWrpFmPortDev->txCh; -+ fmPcdParams.hc.f_QmEnqueue = QmEnqueueCB; -+ fmPcdParams.hc.h_QmArg = (t_Handle) p_LnxWrpFmDev; -+ -+ p_LnxWrpFmDev->h_PcdDev = FM_PCD_Config(&fmPcdParams); -+ if (!p_LnxWrpFmDev->h_PcdDev) -+ RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("FM PCD!")); -+ -+ err = -+ FM_PCD_ConfigPlcrNumOfSharedProfiles(p_LnxWrpFmDev->h_PcdDev, -+ LNXWRP_FM_NUM_OF_SHARED_PROFILES); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ err = FM_PCD_Init(p_LnxWrpFmDev->h_PcdDev); -+ if (err != E_OK) -+ RETURN_ERROR(MAJOR, err, NO_MSG); -+ -+ if (p_LnxWrpFmDev->err_irq == 0) { -+ FM_PCD_SetException(p_LnxWrpFmDev->h_PcdDev, -+ e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC, -+ FALSE); -+ FM_PCD_SetException(p_LnxWrpFmDev->h_PcdDev, -+ e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW, -+ FALSE); -+ FM_PCD_SetException(p_LnxWrpFmDev->h_PcdDev, -+ e_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR, -+ FALSE); -+ FM_PCD_SetException(p_LnxWrpFmDev->h_PcdDev, -+ e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC, -+ FALSE); -+ FM_PCD_SetException(p_LnxWrpFmDev->h_PcdDev, -+ e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC, -+ FALSE); -+ FM_PCD_SetException(p_LnxWrpFmDev->h_PcdDev, -+ e_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE, -+ FALSE); -+ FM_PCD_SetException(p_LnxWrpFmDev->h_PcdDev, -+ e_FM_PCD_PLCR_EXCEPTION_ATOMIC_ACTION_COMPLETE, -+ FALSE); -+ FM_PCD_SetException(p_LnxWrpFmDev->h_PcdDev, -+ e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC, -+ FALSE); -+ } -+ } -+ -+ return E_OK; -+} -+ -+void FreeFmPcdDev(t_LnxWrpFmDev *p_LnxWrpFmDev) -+{ -+ -+ if (p_LnxWrpFmDev->h_PcdDev) -+ FM_PCD_Free(p_LnxWrpFmDev->h_PcdDev); -+ -+ if (p_LnxWrpFmDev->hc_tx_err_fq) -+ FqFree(p_LnxWrpFmDev->hc_tx_err_fq); -+ -+ if (p_LnxWrpFmDev->hc_tx_conf_fq) -+ FqFree(p_LnxWrpFmDev->hc_tx_conf_fq); -+ -+ if (p_LnxWrpFmDev->hc_tx_fq) -+ FqFree(p_LnxWrpFmDev->hc_tx_fq); -+} -+ -+static void FreeFmPortDev(t_LnxWrpFmPortDev *p_LnxWrpFmPortDev) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = -+ (t_LnxWrpFmDev *) p_LnxWrpFmPortDev->h_LnxWrpFmDev; -+ -+ if (!p_LnxWrpFmPortDev->active) -+ return; -+ -+ if (p_LnxWrpFmPortDev->h_Dev) -+ FM_PORT_Free(p_LnxWrpFmPortDev->h_Dev); -+ -+ devm_iounmap(p_LnxWrpFmDev->dev, -+ UINT_TO_PTR(p_LnxWrpFmPortDev->baseAddr)); -+ __devm_release_region(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->res, -+ p_LnxWrpFmPortDev->phys_baseAddr, -+ p_LnxWrpFmPortDev->memSize); -+} -+ -+static int /*__devinit*/ fm_port_probe(struct platform_device *of_dev) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev; -+ t_LnxWrpFmDev *p_LnxWrpFmDev; -+ struct device *dev; -+ -+ dev = &of_dev->dev; -+ -+ p_LnxWrpFmPortDev = ReadFmPortDevTreeNode(of_dev); -+ if (p_LnxWrpFmPortDev == NULL) -+ return -EIO; -+ /* Port can be inactive, thus will not be probed: -+ - in performance mode, OH ports are disabled -+ ... -+ */ -+ if (!p_LnxWrpFmPortDev->active) -+ return 0; -+ -+ if (ConfigureFmPortDev(p_LnxWrpFmPortDev) != E_OK) -+ return -EIO; -+ -+ dev_set_drvdata(dev, p_LnxWrpFmPortDev); -+ -+ if (p_LnxWrpFmPortDev->settings.param.portType == -+ e_FM_PORT_TYPE_OH_HOST_COMMAND) -+ InitFmPcdDev((t_LnxWrpFmDev *) p_LnxWrpFmPortDev->h_LnxWrpFmDev); -+ -+ p_LnxWrpFmDev = (t_LnxWrpFmDev *) p_LnxWrpFmPortDev->h_LnxWrpFmDev; -+ -+ if (p_LnxWrpFmPortDev->settings.param.portType == e_FM_PORT_TYPE_RX) { -+ Sprint(p_LnxWrpFmPortDev->name, "%s-port-rx%d", -+ p_LnxWrpFmDev->name, p_LnxWrpFmPortDev->id); -+ p_LnxWrpFmPortDev->minor = -+ p_LnxWrpFmPortDev->id + DEV_FM_RX_PORTS_MINOR_BASE; -+ } else if (p_LnxWrpFmPortDev->settings.param.portType == -+ e_FM_PORT_TYPE_RX_10G) { -+ Sprint(p_LnxWrpFmPortDev->name, "%s-port-rx%d", -+ p_LnxWrpFmDev->name, -+ p_LnxWrpFmPortDev->id + FM_MAX_NUM_OF_1G_RX_PORTS); -+ p_LnxWrpFmPortDev->minor = -+ p_LnxWrpFmPortDev->id + FM_MAX_NUM_OF_1G_RX_PORTS + -+ DEV_FM_RX_PORTS_MINOR_BASE; -+#ifndef CONFIG_FMAN_ARM -+ if (IS_T1023_T1024) { -+ Sprint(p_LnxWrpFmPortDev->name, "%s-port-rx%d", -+ p_LnxWrpFmDev->name, -+ p_LnxWrpFmPortDev->id); -+ p_LnxWrpFmPortDev->minor = -+ p_LnxWrpFmPortDev->id + -+ DEV_FM_RX_PORTS_MINOR_BASE; -+ } -+#endif -+ } else if (p_LnxWrpFmPortDev->settings.param.portType == -+ e_FM_PORT_TYPE_TX) { -+ Sprint(p_LnxWrpFmPortDev->name, "%s-port-tx%d", -+ p_LnxWrpFmDev->name, p_LnxWrpFmPortDev->id); -+ p_LnxWrpFmPortDev->minor = -+ p_LnxWrpFmPortDev->id + DEV_FM_TX_PORTS_MINOR_BASE; -+ } else if (p_LnxWrpFmPortDev->settings.param.portType == -+ e_FM_PORT_TYPE_TX_10G) { -+ Sprint(p_LnxWrpFmPortDev->name, "%s-port-tx%d", -+ p_LnxWrpFmDev->name, -+ p_LnxWrpFmPortDev->id + FM_MAX_NUM_OF_1G_TX_PORTS); -+ p_LnxWrpFmPortDev->minor = -+ p_LnxWrpFmPortDev->id + FM_MAX_NUM_OF_1G_TX_PORTS + -+ DEV_FM_TX_PORTS_MINOR_BASE; -+#ifndef CONFIG_FMAN_ARM -+ if (IS_T1023_T1024) { -+ Sprint(p_LnxWrpFmPortDev->name, "%s-port-tx%d", -+ p_LnxWrpFmDev->name, -+ p_LnxWrpFmPortDev->id); -+ p_LnxWrpFmPortDev->minor = -+ p_LnxWrpFmPortDev->id + -+ DEV_FM_TX_PORTS_MINOR_BASE; -+ } -+#endif -+ } else if (p_LnxWrpFmPortDev->settings.param.portType == -+ e_FM_PORT_TYPE_OH_HOST_COMMAND) { -+ Sprint(p_LnxWrpFmPortDev->name, "%s-port-oh%d", -+ p_LnxWrpFmDev->name, p_LnxWrpFmPortDev->id); -+ p_LnxWrpFmPortDev->minor = -+ p_LnxWrpFmPortDev->id + DEV_FM_OH_PORTS_MINOR_BASE; -+ } else if (p_LnxWrpFmPortDev->settings.param.portType == -+ e_FM_PORT_TYPE_OH_OFFLINE_PARSING) { -+ Sprint(p_LnxWrpFmPortDev->name, "%s-port-oh%d", -+ p_LnxWrpFmDev->name, p_LnxWrpFmPortDev->id + 1); -+ p_LnxWrpFmPortDev->minor = -+ p_LnxWrpFmPortDev->id + 1 + -+ DEV_FM_OH_PORTS_MINOR_BASE; -+ } -+ -+ device_create(p_LnxWrpFmDev->fm_class, NULL, -+ MKDEV(p_LnxWrpFmDev->major, p_LnxWrpFmPortDev->minor), -+ NULL, p_LnxWrpFmPortDev->name); -+ -+ /* create sysfs entries for stats and regs */ -+ -+ if (fm_port_sysfs_create(dev) != 0) { -+ FreeFmPortDev(p_LnxWrpFmPortDev); -+ REPORT_ERROR(MAJOR, E_INVALID_STATE, -+ ("Unable to create sys entry - fm port!!!")); -+ return -EIO; -+ } -+ -+#ifdef FM_TX_INVALID_ECC_ERRATA_10GMAC_A009 -+ FM_DisableRamsEcc(p_LnxWrpFmDev->h_Dev); -+#endif /* FM_TX_INVALID_ECC_ERRATA_10GMAC_A009 */ -+ -+ DBG(TRACE, ("%s probed", p_LnxWrpFmPortDev->name)); -+ -+ return 0; -+} -+ -+static int fm_port_remove(struct platform_device *of_dev) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev; -+ t_LnxWrpFmDev *p_LnxWrpFmDev; -+ struct device *dev; -+ -+ dev = &of_dev->dev; -+ p_LnxWrpFmPortDev = dev_get_drvdata(dev); -+ -+ fm_port_sysfs_destroy(dev); -+ -+ p_LnxWrpFmDev = (t_LnxWrpFmDev *) p_LnxWrpFmPortDev->h_LnxWrpFmDev; -+ device_destroy(p_LnxWrpFmDev->fm_class, -+ MKDEV(p_LnxWrpFmDev->major, p_LnxWrpFmPortDev->minor)); -+ -+ FreeFmPortDev(p_LnxWrpFmPortDev); -+ -+ dev_set_drvdata(dev, NULL); -+ -+ return 0; -+} -+ -+static const struct of_device_id fm_port_match[] = { -+ { -+ .compatible = "fsl,fman-port-oh"}, -+ { -+ .compatible = "fsl,fman-port-1g-rx"}, -+ { -+ .compatible = "fsl,fman-port-10g-rx"}, -+ { -+ .compatible = "fsl,fman-port-1g-tx"}, -+ { -+ .compatible = "fsl,fman-port-10g-tx"}, -+ {} -+}; -+ -+#ifndef MODULE -+MODULE_DEVICE_TABLE(of, fm_port_match); -+#endif /* !MODULE */ -+ -+static struct platform_driver fm_port_driver = { -+ -+ .driver = { -+ .name = "fsl-fman-port", -+ .of_match_table = fm_port_match, -+ .owner = THIS_MODULE, -+ }, -+ .probe = fm_port_probe, -+ .remove = fm_port_remove -+}; -+ -+ -+t_Error LNXWRP_FM_Port_Init(void) -+{ -+ /* Register to the DTB for basic FM port API */ -+ if (platform_driver_register(&fm_port_driver)) -+ return E_NO_DEVICE; -+ -+ return E_OK; -+} -+ -+void LNXWRP_FM_Port_Free(void) -+{ -+ platform_driver_unregister(&fm_port_driver); -+} -+ -+static int __init __cold fm_port_load(void) -+{ -+ if (LNXWRP_FM_Port_Init() != E_OK) { -+ printk(KERN_CRIT "Failed to init FM Ports wrapper!\n"); -+ return -ENODEV; -+ } -+ -+ printk(KERN_CRIT "Freescale FM Ports module\n"); -+ -+ return 0; -+} -+ -+static void __exit __cold fm_port_unload(void) -+{ -+ LNXWRP_FM_Port_Free(); -+} -+ -+module_init(fm_port_load); -+module_exit(fm_port_unload); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_ioctls_fm.c -@@ -0,0 +1,4813 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ @File lnxwrp_ioctls_fm.c -+ @Author Shlomi Gridish -+ @Description FM Linux wrapper functions. -+*/ -+ -+/* Linux Headers ------------------- */ -+#include -+ -+#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS) -+#define MODVERSIONS -+#endif -+#ifdef MODVERSIONS -+#include -+#endif /* MODVERSIONS */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#ifndef CONFIG_FMAN_ARM -+#include -+#include -+#endif -+ -+#if defined(CONFIG_COMPAT) -+#include -+#endif -+ -+#include "part_ext.h" -+#include "fm_ioctls.h" -+#include "fm_pcd_ioctls.h" -+#include "fm_port_ioctls.h" -+#include "fm_vsp_ext.h" -+ -+#ifndef CONFIG_FMAN_ARM -+#define IS_T1023_T1024 (SVR_SOC_VER(mfspr(SPRN_SVR)) == SVR_T1024 || \ -+ SVR_SOC_VER(mfspr(SPRN_SVR)) == SVR_T1023) -+#endif -+ -+#define __ERR_MODULE__ MODULE_FM -+ -+#if defined(CONFIG_COMPAT) -+#include "lnxwrp_ioctls_fm_compat.h" -+#endif -+ -+#include "lnxwrp_fm.h" -+ -+#define CMP_IOC_DEFINE(def) (IOC_##def != def) -+ -+/* fm_pcd_ioctls.h === fm_pcd_ext.h assertions */ -+#if CMP_IOC_DEFINE(FM_PCD_MAX_NUM_OF_PRIVATE_HDRS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_PRS_NUM_OF_HDRS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_KG_NUM_OF_GENERIC_REGS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_KG_NUM_OF_EXTRACT_MASKS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_KG_NUM_OF_DEFAULT_GROUPS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_PRS_NUM_OF_LABELS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_SW_PRS_SIZE) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_MAX_MANIP_INSRT_TEMPLATE_SIZE) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if DPAA_VERSION >= 11 -+#if CMP_IOC_DEFINE(FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES) -+#error Error: please synchronize IOC_ defines! -+#endif -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_MAX_NUM_OF_CC_TREES) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_MAX_NUM_OF_CC_GROUPS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_MAX_NUM_OF_CC_UNITS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_MAX_NUM_OF_KEYS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_MAX_SIZE_OF_KEY) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_MAX_NUM_OF_CC_ENTRIES_IN_GRP) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(FM_PCD_LAST_KEY_INDEX) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+/* net_ioctls.h === net_ext.h assertions */ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_PPP_PID) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_PPP_COMPRESSED) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_PPP_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_PPPoE_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_PPPMUX_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_PPPMUX_SUBFRAME_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_ETH_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_IPv4_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_IPv6_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_ICMP_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_IGMP_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_TCP_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_SCTP_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_DCCP_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_UDP_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_UDP_ENCAP_ESP_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_IPHC_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_SCTP_CHUNK_DATA_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_L2TPv2_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_L2TPv3_CTRL_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_L2TPv3_SESS_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_VLAN_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_LLC_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_NLPID_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_SNAP_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_LLC_SNAP_ALL_FIELDS) -+#warning Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_ARP_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_RFC2684_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_USER_DEFINED_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_PAYLOAD_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_GRE_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_MINENCAP_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_IPSEC_AH_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_IPSEC_ESP_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_MPLS_LABEL_STACK_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+#if CMP_IOC_DEFINE(NET_HEADER_FIELD_MACSEC_ALL_FIELDS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+/* fm_ioctls.h === fm_ext.h assertions */ -+#if CMP_IOC_DEFINE(FM_MAX_NUM_OF_VALID_PORTS) -+#error Error: please synchronize IOC_ defines! -+#endif -+ -+void LnxWrpPCDIOCTLTypeChecking(void) -+{ -+ /* fm_ext.h == fm_ioctls.h */ -+ ASSERT_COND(sizeof(ioc_fm_port_bandwidth_params) == sizeof(t_FmPortsBandwidthParams)); -+ ASSERT_COND(sizeof(ioc_fm_revision_info_t) == sizeof(t_FmRevisionInfo)); -+ -+ /* fm_pcd_ext.h == fm_pcd_ioctls.h */ -+ /*ioc_fm_pcd_counters_params_t : NOT USED */ -+ /*ioc_fm_pcd_exception_params_t : private */ -+#if (DPAA_VERSION >= 11) -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_frag_capwap_params_t) == sizeof(t_FmPcdManipFragCapwapParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_reassem_capwap_params_t) == sizeof(t_FmPcdManipReassemCapwapParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_hdr_insrt_by_hdr_params_t) == sizeof(t_FmPcdManipHdrInsrtByHdrParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_hdr_insrt_ip_params_t) == sizeof(t_FmPcdManipHdrInsrtIpParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_hdr_insrt_t) == sizeof(t_FmPcdManipHdrInsrt)); -+ ASSERT_COND(sizeof(ioc_fm_manip_hdr_info_t) == sizeof(t_FmManipHdrInfo)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_hdr_rmv_by_hdr_params_t) == sizeof(t_FmPcdManipHdrRmvByHdrParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_special_offload_capwap_params_t) == sizeof(t_FmPcdManipSpecialOffloadCapwapParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_frag_capwap_stats_t) == sizeof(t_FmPcdManipFragCapwapStats)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_reassem_capwap_stats_t) == sizeof(t_FmPcdManipReassemCapwapStats)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_frag_params_t) == sizeof(t_FmPcdManipFragParams)); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ ASSERT_COND(sizeof(ioc_fm_pcd_prs_label_params_t) == sizeof(t_FmPcdPrsLabelParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_prs_sw_params_t) == sizeof(t_FmPcdPrsSwParams)); -+ /*ioc_fm_pcd_kg_dflt_value_params_t : private */ -+ ASSERT_COND(sizeof(ioc_fm_pcd_hdr_protocol_opt_u) == sizeof(u_FmPcdHdrProtocolOpt)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_fields_u) == sizeof(t_FmPcdFields)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_from_hdr_t) == sizeof(t_FmPcdFromHdr)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_from_field_t) == sizeof(t_FmPcdFromField)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_distinction_unit_t) == sizeof(t_FmPcdDistinctionUnit)); -+ -+#if defined(CONFIG_ARM64) -+ /* different alignment */ -+ ASSERT_COND(sizeof(ioc_fm_pcd_net_env_params_t) == sizeof(t_FmPcdNetEnvParams) + sizeof(void *) + 4); -+#else -+#if !defined(CONFIG_COMPAT) -+ /* different alignment */ -+ ASSERT_COND(sizeof(ioc_fm_pcd_net_env_params_t) == sizeof(t_FmPcdNetEnvParams) + sizeof(void *)); -+#endif -+#endif -+ ASSERT_COND(sizeof(ioc_fm_pcd_extract_entry_t) == sizeof(t_FmPcdExtractEntry)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_kg_extract_mask_t) == sizeof(t_FmPcdKgExtractMask)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_kg_extract_dflt_t) == sizeof(t_FmPcdKgExtractDflt)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_kg_key_extract_and_hash_params_t) == sizeof(t_FmPcdKgKeyExtractAndHashParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_kg_extracted_or_params_t) == sizeof(t_FmPcdKgExtractedOrParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_kg_scheme_counter_t) == sizeof(t_FmPcdKgSchemeCounter)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_kg_plcr_profile_t) == sizeof(t_FmPcdKgPlcrProfile)); -+#if (DPAA_VERSION >= 11) -+ ASSERT_COND(sizeof(ioc_fm_pcd_kg_storage_profile_t) == sizeof(t_FmPcdKgStorageProfile)); -+#endif -+ ASSERT_COND(sizeof(ioc_fm_pcd_kg_cc_t) == sizeof(t_FmPcdKgCc)); -+#if !defined(CONFIG_COMPAT) -+ /* different alignment */ -+ ASSERT_COND(sizeof(ioc_fm_pcd_kg_scheme_params_t) == sizeof(t_FmPcdKgSchemeParams) + sizeof(void *)); -+#endif -+ ASSERT_COND(sizeof(ioc_fm_pcd_cc_next_cc_params_t) == sizeof(t_FmPcdCcNextCcParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_cc_next_plcr_params_t) == sizeof(t_FmPcdCcNextPlcrParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_cc_next_enqueue_params_t) == sizeof(t_FmPcdCcNextEnqueueParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_cc_next_kg_params_t) == sizeof(t_FmPcdCcNextKgParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_cc_next_engine_params_t) == sizeof(t_FmPcdCcNextEngineParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_cc_key_params_t) == sizeof(t_FmPcdCcKeyParams)); -+ ASSERT_COND(sizeof(ioc_keys_params_t) == sizeof(t_KeysParams)); -+#if !defined(CONFIG_COMPAT) -+ /* different alignment */ -+ ASSERT_COND(sizeof(ioc_fm_pcd_cc_node_params_t) == sizeof(t_FmPcdCcNodeParams) + sizeof(void *)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_hash_table_params_t) == sizeof(t_FmPcdHashTableParams) + sizeof(void *)); -+#endif -+ ASSERT_COND(sizeof(ioc_fm_pcd_cc_grp_params_t) == sizeof(t_FmPcdCcGrpParams)); -+#if !defined(CONFIG_COMPAT) -+ /* different alignment */ -+ ASSERT_COND(sizeof(ioc_fm_pcd_cc_tree_params_t) == sizeof(t_FmPcdCcTreeParams) + sizeof(void *)); -+#endif -+ ASSERT_COND(sizeof(ioc_fm_pcd_plcr_byte_rate_mode_param_t) == sizeof(t_FmPcdPlcrByteRateModeParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_plcr_non_passthrough_alg_param_t) == sizeof(t_FmPcdPlcrNonPassthroughAlgParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_plcr_next_engine_params_u) == sizeof(u_FmPcdPlcrNextEngineParams)); -+ /*ioc_fm_pcd_port_params_t : private */ -+ ASSERT_COND(sizeof(ioc_fm_pcd_plcr_profile_params_t) == sizeof(t_FmPcdPlcrProfileParams) + sizeof(void *)); -+ /*ioc_fm_pcd_cc_tree_modify_next_engine_params_t : private */ -+ -+#ifdef FM_CAPWAP_SUPPORT -+#error TODO: unsupported feature -+/* -+ ASSERT_COND(sizeof(TODO) == sizeof(t_FmPcdManipHdrInsrtByTemplateParams)); -+ ASSERT_COND(sizeof(TODO) == sizeof(t_CapwapFragmentationParams)); -+ ASSERT_COND(sizeof(TODO) == sizeof(t_CapwapReassemblyParams)); -+*/ -+#endif -+ -+ /*ioc_fm_pcd_cc_node_modify_next_engine_params_t : private */ -+ /*ioc_fm_pcd_cc_node_remove_key_params_t : private */ -+ /*ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t : private */ -+ /*ioc_fm_pcd_cc_node_modify_key_params_t : private */ -+ /*ioc_fm_manip_hdr_info_t : private */ -+ /*ioc_fm_pcd_hash_table_set_t : private */ -+ -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_frag_ip_params_t) == sizeof(t_FmPcdManipFragIpParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_reassem_ip_params_t) == sizeof(t_FmPcdManipReassemIpParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_special_offload_ipsec_params_t) == sizeof(t_FmPcdManipSpecialOffloadIPSecParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_special_offload_params_t) == sizeof(t_FmPcdManipSpecialOffloadParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_hdr_rmv_generic_params_t) == sizeof(t_FmPcdManipHdrRmvGenericParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_hdr_insrt_generic_params_t) == sizeof(t_FmPcdManipHdrInsrtGenericParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_hdr_insrt_params_t) == sizeof(t_FmPcdManipHdrInsrtParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_hdr_rmv_params_t) == sizeof(t_FmPcdManipHdrRmvParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_hdr_params_t) == sizeof(t_FmPcdManipHdrParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_frag_params_t) == sizeof(t_FmPcdManipFragParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_reassem_params_t) == sizeof(t_FmPcdManipReassemParams)); -+#if !defined(CONFIG_COMPAT) -+ /* different alignment */ -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_params_t) == sizeof(t_FmPcdManipParams) + sizeof(void *)); -+#endif -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_reassem_ip_stats_t) == sizeof(t_FmPcdManipReassemIpStats)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_frag_ip_stats_t) == sizeof(t_FmPcdManipFragIpStats)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_reassem_stats_t) == sizeof(t_FmPcdManipReassemStats)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_frag_stats_t) == sizeof(t_FmPcdManipFragStats)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_manip_stats_t) == sizeof(t_FmPcdManipStats)); -+#if DPAA_VERSION >= 11 -+ ASSERT_COND(sizeof(ioc_fm_pcd_frm_replic_group_params_t) == sizeof(t_FmPcdFrmReplicGroupParams) + sizeof(void *)); -+#endif -+ -+ /* fm_port_ext.h == fm_port_ioctls.h */ -+ ASSERT_COND(sizeof(ioc_fm_port_rate_limit_t) == sizeof(t_FmPortRateLimit)); -+ ASSERT_COND(sizeof(ioc_fm_port_pcd_params_t) == sizeof(t_FmPortPcdParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_kg_scheme_select_t) == sizeof(t_FmPcdKgSchemeSelect)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_port_schemes_params_t) == sizeof(t_FmPcdPortSchemesParams)); -+ ASSERT_COND(sizeof(ioc_fm_pcd_prs_start_t) == sizeof(t_FmPcdPrsStart)); -+ -+ return; -+} -+ -+#define ASSERT_IOC_NET_ENUM(def) ASSERT_COND((unsigned long)e_IOC_NET_##def == (unsigned long)def) -+ -+void LnxWrpPCDIOCTLEnumChecking(void) -+{ -+ /* net_ext.h == net_ioctls.h : sampling checks */ -+ ASSERT_IOC_NET_ENUM(HEADER_TYPE_MACSEC); -+ ASSERT_IOC_NET_ENUM(HEADER_TYPE_PPP); -+ ASSERT_IOC_NET_ENUM(MAX_HEADER_TYPE_COUNT); -+ -+ /* fm_ext.h == fm_ioctls.h */ -+ ASSERT_COND((unsigned long)e_IOC_FM_PORT_TYPE_DUMMY == (unsigned long)e_FM_PORT_TYPE_DUMMY); -+ ASSERT_COND((unsigned long)e_IOC_EX_MURAM_ECC == (unsigned long)e_FM_EX_MURAM_ECC); -+ ASSERT_COND((unsigned long)e_IOC_FM_COUNTERS_DEQ_CONFIRM == (unsigned long)e_FM_COUNTERS_DEQ_CONFIRM); -+ -+ /* fm_pcd_ext.h == fm_pcd_ioctls.h */ -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_PRS_COUNTERS_FPM_COMMAND_STALL_CYCLES == (unsigned long)e_FM_PCD_PRS_COUNTERS_FPM_COMMAND_STALL_CYCLES); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_PRS_EXCEPTION_SINGLE_ECC == (unsigned long)e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_PRS == (unsigned long)e_FM_PCD_PRS); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_EXTRACT_FULL_FIELD == (unsigned long)e_FM_PCD_EXTRACT_FULL_FIELD); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_EXTRACT_FROM_FLOW_ID == (unsigned long)e_FM_PCD_EXTRACT_FROM_FLOW_ID); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_KG_EXTRACT_PORT_PRIVATE_INFO == (unsigned long)e_FM_PCD_KG_EXTRACT_PORT_PRIVATE_INFO); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_KG_DFLT_ILLEGAL == (unsigned long)e_FM_PCD_KG_DFLT_ILLEGAL); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_KG_GENERIC_NOT_FROM_DATA == (unsigned long)e_FM_PCD_KG_GENERIC_NOT_FROM_DATA); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_HDR_INDEX_LAST == (unsigned long)e_FM_PCD_HDR_INDEX_LAST); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_PLCR_SHARED == (unsigned long)e_FM_PCD_PLCR_SHARED); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_PLCR_RFC_4115 == (unsigned long)e_FM_PCD_PLCR_RFC_4115); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_PLCR_COLOR_AWARE == (unsigned long)e_FM_PCD_PLCR_COLOR_AWARE); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_PLCR_OVERRIDE == (unsigned long)e_FM_PCD_PLCR_OVERRIDE); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_PLCR_FULL_FRM_LEN == (unsigned long)e_FM_PCD_PLCR_FULL_FRM_LEN); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_PLCR_ROLLBACK_FULL_FRM_LEN == (unsigned long)e_FM_PCD_PLCR_ROLLBACK_FULL_FRM_LEN); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_PLCR_PACKET_MODE == (unsigned long)e_FM_PCD_PLCR_PACKET_MODE); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_DROP_FRAME == (unsigned long)e_FM_PCD_DROP_FRAME); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_PLCR_PROFILE_RECOLOURED_RED_PACKET_TOTAL_COUNTER == (unsigned long)e_FM_PCD_PLCR_PROFILE_RECOLOURED_RED_PACKET_TOTAL_COUNTER); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_ACTION_INDEXED_LOOKUP == (unsigned long)e_FM_PCD_ACTION_INDEXED_LOOKUP); -+ ASSERT_COND((unsigned long)e_IOC_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_PLCR == (unsigned long)e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_PLCR); -+#if !defined(FM_CAPWAP_SUPPORT) -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_MANIP_INSRT_GENERIC == (unsigned long)e_FM_PCD_MANIP_INSRT_GENERIC); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_MANIP_RMV_GENERIC == (unsigned long)e_FM_PCD_MANIP_RMV_GENERIC); -+#else -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_MANIP_INSRT_BY_TEMPLATE == (unsigned long)e_FM_PCD_MANIP_INSRT_BY_TEMPLATE); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_MANIP_RMV_BY_HDR == (unsigned long)e_FM_PCD_MANIP_RMV_BY_HDR); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_MANIP_RMV_BY_HDR_FROM_START == (unsigned long)e_FM_PCD_MANIP_RMV_BY_HDR_FROM_START); -+#endif -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_MANIP_TIME_OUT_BETWEEN_FRAG == (unsigned long)e_FM_PCD_MANIP_TIME_OUT_BETWEEN_FRAG); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_MANIP_EIGHT_WAYS_HASH == (unsigned long)e_FM_PCD_MANIP_EIGHT_WAYS_HASH); -+ -+#ifdef FM_CAPWAP_SUPPORT -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_STATS_PER_FLOWID == (unsigned long)e_FM_PCD_STATS_PER_FLOWID); -+#endif -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_MANIP_SPECIAL_OFFLOAD == (unsigned long)e_FM_PCD_MANIP_SPECIAL_OFFLOAD); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_CC_STATS_MODE_FRAME == (unsigned long)e_FM_PCD_CC_STATS_MODE_FRAME); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_MANIP_CONTINUE_WITHOUT_FRAG == (unsigned long)e_FM_PCD_MANIP_CONTINUE_WITHOUT_FRAG); -+ ASSERT_COND((unsigned long)e_IOC_FM_PCD_MANIP_SPECIAL_OFFLOAD_IPSEC == (unsigned long)e_FM_PCD_MANIP_SPECIAL_OFFLOAD_IPSEC); -+ -+ /* fm_port_ext.h == fm_port_ioctls.h */ -+#if !defined(FM_CAPWAP_SUPPORT) -+ ASSERT_COND((unsigned long)e_IOC_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_PLCR == (unsigned long)e_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_PLCR); -+#else -+ ASSERT_COND((unsigned long)e_IOC_FM_PORT_PCD_SUPPORT_CC_AND_KG_AND_PLCR == (unsigned long)e_FM_PORT_PCD_SUPPORT_CC_AND_KG_AND_PLCR); -+#endif -+ ASSERT_COND((unsigned long)e_IOC_FM_PORT_COUNTERS_DEQ_CONFIRM == (unsigned long)e_FM_PORT_COUNTERS_DEQ_CONFIRM); -+ ASSERT_COND((unsigned long)e_IOC_FM_PORT_DUAL_RATE_LIMITER_SCALE_DOWN_BY_8 == (unsigned long)e_FM_PORT_DUAL_RATE_LIMITER_SCALE_DOWN_BY_8); -+ -+ return; -+} -+ -+static t_Error LnxwrpFmPcdIOCTL(t_LnxWrpFmDev *p_LnxWrpFmDev, unsigned int cmd, unsigned long arg, bool compat) -+{ -+ t_Error err = E_OK; -+ -+/* -+Status: PCD API to fmlib (file: drivers/net/dpa/NetCommSw/inc/Peripherals/fm_pcd_ext.h): -+ -+ FM_PCD_PrsLoadSw -+ FM_PCD_SetAdvancedOffloadSupport -+ FM_PCD_Enable -+ FM_PCD_Disable -+ FM_PCD_ForceIntr -+ FM_PCD_SetException -+ FM_PCD_KgSetAdditionalDataAfterParsing -+ FM_PCD_KgSetDfltValue -+ FM_PCD_NetEnvCharacteristicsSet -+ FM_PCD_NetEnvCharacteristicsDelete -+ FM_PCD_KgSchemeSet -+ FM_PCD_KgSchemeDelete -+ FM_PCD_MatchTableSet -+ FM_PCD_MatchTableDelete -+ FM_PCD_CcRootBuild -+ FM_PCD_CcRootDelete -+ FM_PCD_PlcrProfileSet -+ FM_PCD_PlcrProfileDelete -+ FM_PCD_CcRootModifyNextEngine -+ FM_PCD_MatchTableModifyNextEngine -+ FM_PCD_MatchTableModifyMissNextEngine -+ FM_PCD_MatchTableRemoveKey -+ FM_PCD_MatchTableAddKey -+ FM_PCD_MatchTableModifyKeyAndNextEngine -+ FM_PCD_HashTableSet -+ FM_PCD_HashTableDelete -+ FM_PCD_HashTableAddKey -+ FM_PCD_HashTableRemoveKey -+ FM_PCD_MatchTableModifyKey -+ FM_PCD_ManipNodeReplace -+ FM_PCD_ManipNodeSet -+ FM_PCD_ManipNodeDelete -+ -+Status: not exported, should be thru sysfs -+ FM_PCD_KgSchemeGetCounter -+ FM_PCD_KgSchemeSetCounter -+ FM_PCD_PlcrProfileGetCounter -+ FM_PCD_PlcrProfileSetCounter -+ -+Status: not exported -+ FM_PCD_MatchTableFindNRemoveKey -+ FM_PCD_MatchTableFindNModifyNextEngine -+ FM_PCD_MatchTableFindNModifyKeyAndNextEngine -+ FM_PCD_MatchTableFindNModifyKey -+ FM_PCD_MatchTableGetIndexedHashBucket -+ FM_PCD_MatchTableGetNextEngine -+ FM_PCD_MatchTableGetKeyCounter -+ -+Status: not exported, would be nice to have -+ FM_PCD_HashTableModifyNextEngine -+ FM_PCD_HashTableModifyMissNextEngine -+ FM_PCD_HashTableGetMissNextEngine -+ FM_PCD_ManipGetStatistics -+ -+Status: not exported -+#if DPAA_VERSION >= 11 -+ -+ FM_VSP_GetStatistics -- it's not available yet -+#endif -+ -+Status: feature not supported -+#ifdef FM_CAPWAP_SUPPORT -+#error unsupported feature -+ FM_PCD_StatisticsSetNode -+#endif -+ -+ */ -+ _fm_ioctl_dbg("cmd:0x%08x(type:0x%02x, nr:%u).\n", -+ cmd, _IOC_TYPE(cmd), _IOC_NR(cmd) - 20); -+ -+ switch (cmd) -+ { -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_PRS_LOAD_SW_COMPAT: -+#endif -+ case FM_PCD_IOC_PRS_LOAD_SW: -+ { -+ ioc_fm_pcd_prs_sw_params_t *param; -+ uint8_t *p_code; -+ -+ param = (ioc_fm_pcd_prs_sw_params_t *) XX_Malloc(sizeof(ioc_fm_pcd_prs_sw_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_prs_sw_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_prs_sw_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_prs_sw_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_prs_sw_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_prs_sw_params_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_prs_sw_params_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_prs_sw_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_fm_pcd_prs_sw(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_prs_sw_params_t *)arg, -+ sizeof(ioc_fm_pcd_prs_sw_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ if (!param->p_code || !param->size) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ p_code = (uint8_t *) XX_Malloc(param->size); -+ if (!p_code) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(p_code, 0, param->size); -+ if (copy_from_user(p_code, param->p_code, param->size)) -+ { -+ XX_Free(p_code); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ param->p_code = p_code; -+ -+ err = FM_PCD_PrsLoadSw(p_LnxWrpFmDev->h_PcdDev, (t_FmPcdPrsSwParams*)param); -+ -+ XX_Free(p_code); -+ XX_Free(param); -+ break; -+ } -+ -+ case FM_PCD_IOC_SET_ADVANCED_OFFLOAD_SUPPORT: -+ err = FM_PCD_SetAdvancedOffloadSupport(p_LnxWrpFmDev->h_PcdDev); -+ break; -+ -+ case FM_PCD_IOC_ENABLE: -+ err = FM_PCD_Enable(p_LnxWrpFmDev->h_PcdDev); -+ break; -+ -+ case FM_PCD_IOC_DISABLE: -+ err = FM_PCD_Disable(p_LnxWrpFmDev->h_PcdDev); -+ break; -+ -+ case FM_PCD_IOC_FORCE_INTR: -+ { -+ int exception; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (get_user(exception, (int *) compat_ptr(arg))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ else -+#endif -+ { -+ if (get_user(exception, (int *)arg)) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_PCD_ForceIntr(p_LnxWrpFmDev->h_PcdDev, (e_FmPcdExceptions)exception); -+ break; -+ } -+ -+ case FM_PCD_IOC_SET_EXCEPTION: -+ { -+ ioc_fm_pcd_exception_params_t *param; -+ -+ param = (ioc_fm_pcd_exception_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_exception_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_exception_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_exception_params_t *)compat_ptr(arg), -+ sizeof(ioc_fm_pcd_exception_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_exception_params_t *)arg, -+ sizeof(ioc_fm_pcd_exception_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = FM_PCD_SetException(p_LnxWrpFmDev->h_PcdDev, param->exception, param->enable); -+ -+ XX_Free(param); -+ break; -+ } -+ -+ case FM_PCD_IOC_KG_SET_ADDITIONAL_DATA_AFTER_PARSING: -+ { -+ uint8_t payloadOffset; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (get_user(payloadOffset, (uint8_t*) compat_ptr(arg))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ else -+#endif -+ { -+ if (get_user(payloadOffset, (uint8_t*) arg)) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_PCD_KgSetAdditionalDataAfterParsing(p_LnxWrpFmDev->h_PcdDev, payloadOffset); -+ break; -+ } -+ -+ case FM_PCD_IOC_KG_SET_DFLT_VALUE: -+ { -+ ioc_fm_pcd_kg_dflt_value_params_t *param; -+ -+ param = (ioc_fm_pcd_kg_dflt_value_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_kg_dflt_value_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_kg_dflt_value_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_kg_dflt_value_params_t *)compat_ptr(arg), -+ sizeof(ioc_fm_pcd_kg_dflt_value_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_kg_dflt_value_params_t *)arg, -+ sizeof(ioc_fm_pcd_kg_dflt_value_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = FM_PCD_KgSetDfltValue(p_LnxWrpFmDev->h_PcdDev, param->valueId, param->value); -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_NET_ENV_CHARACTERISTICS_SET_COMPAT: -+#endif -+ case FM_PCD_IOC_NET_ENV_CHARACTERISTICS_SET: -+ { -+ ioc_fm_pcd_net_env_params_t *param; -+ -+ param = (ioc_fm_pcd_net_env_params_t *) XX_Malloc(sizeof(ioc_fm_pcd_net_env_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_net_env_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_net_env_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_net_env_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_net_env_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_net_env_params_t)); -+ if (copy_from_user(compat_param, (ioc_compat_fm_pcd_net_env_params_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_net_env_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_net_env(compat_param, param, COMPAT_US_TO_K); -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_net_env_params_t *) arg, -+ sizeof(ioc_fm_pcd_net_env_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ param->id = FM_PCD_NetEnvCharacteristicsSet(p_LnxWrpFmDev->h_PcdDev, (t_FmPcdNetEnvParams*)param); -+ -+ if (!param->id) -+ { -+ XX_Free(param); -+ err = E_INVALID_VALUE; -+ /* Since the LLD has no errno-style error reporting, -+ we're left here with no other option than to report -+ a generic E_INVALID_VALUE */ -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_net_env_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_net_env_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_net_env_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_net_env_params_t)); -+ compat_copy_fm_pcd_net_env(compat_param, param, COMPAT_K_TO_US); -+ -+ if (copy_to_user((ioc_compat_fm_pcd_net_env_params_t *) compat_ptr(arg), -+ compat_param, -+ sizeof(ioc_compat_fm_pcd_net_env_params_t))) -+ err = E_READ_FAILED; -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_pcd_net_env_params_t *)arg, -+ param, -+ sizeof(ioc_fm_pcd_net_env_params_t))) -+ err = E_READ_FAILED; -+ } -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_NET_ENV_CHARACTERISTICS_DELETE_COMPAT: -+#endif -+ case FM_PCD_IOC_NET_ENV_CHARACTERISTICS_DELETE: -+ { -+ ioc_fm_obj_t id; -+ -+ memset(&id, 0 , sizeof(ioc_fm_obj_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_obj_t compat_id; -+ -+ if (copy_from_user(&compat_id, (ioc_compat_fm_obj_t *) compat_ptr(arg), sizeof(ioc_compat_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_obj_delete(&compat_id, &id); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(&id, (ioc_fm_obj_t *) arg, sizeof(ioc_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_PCD_NetEnvCharacteristicsDelete(id.obj); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_KG_SCHEME_SET_COMPAT: -+#endif -+ case FM_PCD_IOC_KG_SCHEME_SET: -+ { -+ ioc_fm_pcd_kg_scheme_params_t *param; -+ -+ param = (ioc_fm_pcd_kg_scheme_params_t *) XX_Malloc(sizeof(ioc_fm_pcd_kg_scheme_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_kg_scheme_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_kg_scheme_params_t *compat_param = NULL; -+ -+ compat_param = (ioc_compat_fm_pcd_kg_scheme_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_kg_scheme_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_kg_scheme_params_t)); -+ -+ if (copy_from_user(compat_param, (ioc_compat_fm_pcd_kg_scheme_params_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_kg_scheme_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_kg_scheme(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_kg_scheme_params_t *)arg, -+ sizeof(ioc_fm_pcd_kg_scheme_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ param->id = FM_PCD_KgSchemeSet(p_LnxWrpFmDev->h_PcdDev, (t_FmPcdKgSchemeParams*)param); -+ -+ if (!param->id) -+ { -+ XX_Free(param); -+ err = E_INVALID_VALUE; -+ /* Since the LLD has no errno-style error reporting, -+ we're left here with no other option than to report -+ a generic E_INVALID_VALUE */ -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_kg_scheme_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_kg_scheme_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_kg_scheme_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_kg_scheme_params_t)); -+ compat_copy_fm_pcd_kg_scheme(compat_param, param, COMPAT_K_TO_US); -+ if (copy_to_user((ioc_compat_fm_pcd_kg_scheme_params_t *)compat_ptr(arg), -+ compat_param, -+ sizeof(ioc_compat_fm_pcd_kg_scheme_params_t))) -+ err = E_READ_FAILED; -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_pcd_kg_scheme_params_t *)arg, -+ param, -+ sizeof(ioc_fm_pcd_kg_scheme_params_t))) -+ err = E_READ_FAILED; -+ } -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_KG_SCHEME_GET_CNTR_COMPAT: -+#endif -+ case FM_PCD_IOC_KG_SCHEME_GET_CNTR: -+ { -+ ioc_fm_pcd_kg_scheme_spc_t *param; -+ -+ param = (ioc_fm_pcd_kg_scheme_spc_t *) XX_Malloc(sizeof(ioc_fm_pcd_kg_scheme_spc_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_kg_scheme_spc_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_kg_scheme_spc_t *compat_param = NULL; -+ -+ compat_param = (ioc_compat_fm_pcd_kg_scheme_spc_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_kg_scheme_spc_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_kg_scheme_spc_t)); -+ -+ if (copy_from_user(compat_param, (ioc_compat_fm_pcd_kg_scheme_spc_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_kg_scheme_spc_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_kg_scheme_spc(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_kg_scheme_spc_t *)arg, -+ sizeof(ioc_fm_pcd_kg_scheme_spc_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ param->val = FM_PCD_KgSchemeGetCounter((t_Handle)param->id); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_kg_scheme_spc_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_kg_scheme_spc_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_kg_scheme_spc_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_kg_scheme_spc_t)); -+ compat_copy_fm_pcd_kg_scheme_spc(compat_param, param, COMPAT_K_TO_US); -+ if (copy_to_user((ioc_compat_fm_pcd_kg_scheme_spc_t *)compat_ptr(arg), -+ compat_param, -+ sizeof(ioc_compat_fm_pcd_kg_scheme_spc_t))) -+ err = E_READ_FAILED; -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_pcd_kg_scheme_spc_t *)arg, -+ param, -+ sizeof(ioc_fm_pcd_kg_scheme_spc_t))) -+ err = E_READ_FAILED; -+ } -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_KG_SCHEME_DELETE_COMPAT: -+#endif -+ case FM_PCD_IOC_KG_SCHEME_DELETE: -+ { -+ ioc_fm_obj_t id; -+ -+ memset(&id, 0 , sizeof(ioc_fm_obj_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_obj_t compat_id; -+ -+ if (copy_from_user(&compat_id, (ioc_compat_fm_obj_t *) compat_ptr(arg), sizeof(ioc_compat_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_obj_delete(&compat_id, &id); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(&id, (ioc_fm_obj_t *) arg, sizeof(ioc_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_PCD_KgSchemeDelete(id.obj); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_MATCH_TABLE_SET_COMPAT: -+#endif -+ case FM_PCD_IOC_MATCH_TABLE_SET: -+ { -+ ioc_fm_pcd_cc_node_params_t *param; -+ uint8_t *keys; -+ uint8_t *masks; -+ int i,k; -+ -+ param = (ioc_fm_pcd_cc_node_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_cc_node_params_t) + -+ 2 * IOC_FM_PCD_MAX_NUM_OF_KEYS * IOC_FM_PCD_MAX_SIZE_OF_KEY); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_cc_node_params_t) + -+ 2 * IOC_FM_PCD_MAX_NUM_OF_KEYS * IOC_FM_PCD_MAX_SIZE_OF_KEY); -+ -+ keys = (uint8_t *) (param + 1); -+ masks = keys + IOC_FM_PCD_MAX_NUM_OF_KEYS * IOC_FM_PCD_MAX_SIZE_OF_KEY; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_node_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_node_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_node_params_t) + -+ 2 * IOC_FM_PCD_MAX_NUM_OF_KEYS * IOC_FM_PCD_MAX_SIZE_OF_KEY); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_node_params_t) + -+ 2 * IOC_FM_PCD_MAX_NUM_OF_KEYS * IOC_FM_PCD_MAX_SIZE_OF_KEY); -+ -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_cc_node_params_t *)compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_cc_node_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_cc_node(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_cc_node_params_t *)arg, sizeof(ioc_fm_pcd_cc_node_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ ASSERT_COND(param->keys_params.num_of_keys <= IOC_FM_PCD_MAX_NUM_OF_KEYS); -+ ASSERT_COND(param->keys_params.key_size <= IOC_FM_PCD_MAX_SIZE_OF_KEY); -+ -+ /* support for indexed lookup */ -+ if( !(param->extract_cc_params.type == e_IOC_FM_PCD_EXTRACT_NON_HDR && -+ param->extract_cc_params.extract_params.extract_non_hdr.src == e_IOC_FM_PCD_EXTRACT_FROM_HASH && -+ param->extract_cc_params.extract_params.extract_non_hdr.action == e_IOC_FM_PCD_ACTION_INDEXED_LOOKUP)) -+ { -+ for (i=0, k=0; -+ i < param->keys_params.num_of_keys; -+ i++, k += IOC_FM_PCD_MAX_SIZE_OF_KEY) -+ { -+ if (param->keys_params.key_params[i].p_key && -+ param->keys_params.key_size) -+ { -+ if (copy_from_user(&keys[k], -+ param->keys_params.key_params[i].p_key, -+ param->keys_params.key_size)) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ param->keys_params.key_params[i].p_key = &keys[k]; -+ } -+ -+ if (param->keys_params.key_params[i].p_mask) -+ { -+ if (copy_from_user(&masks[k], -+ param->keys_params.key_params[i].p_mask, -+ param->keys_params.key_size)) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ param->keys_params.key_params[i].p_mask = &masks[k]; -+ } -+ } -+ } -+ -+ param->id = FM_PCD_MatchTableSet(p_LnxWrpFmDev->h_PcdDev, (t_FmPcdCcNodeParams*)param); -+ -+ if (!param->id) { -+ XX_Free(param); -+ err = E_INVALID_VALUE; -+ /* Since the LLD has no errno-style error reporting, -+ we're left here with no other option than to report -+ a generic E_INVALID_VALUE */ -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_node_params_t *compat_param; -+ compat_param = (ioc_compat_fm_pcd_cc_node_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_node_params_t) + -+ 2 * IOC_FM_PCD_MAX_NUM_OF_KEYS * IOC_FM_PCD_MAX_SIZE_OF_KEY); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_node_params_t) + -+ 2 * IOC_FM_PCD_MAX_NUM_OF_KEYS * IOC_FM_PCD_MAX_SIZE_OF_KEY); -+ compat_copy_fm_pcd_cc_node(compat_param, param, COMPAT_K_TO_US); -+ -+ if (copy_to_user((ioc_compat_fm_pcd_cc_node_params_t *)compat_ptr(arg), -+ compat_param, -+ sizeof(ioc_compat_fm_pcd_cc_node_params_t))) -+ err = E_READ_FAILED; -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_pcd_cc_node_params_t *)arg, -+ param, -+ sizeof(ioc_fm_pcd_cc_node_params_t))) -+ err = E_READ_FAILED; -+ } -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_MATCH_TABLE_DELETE_COMPAT: -+#endif -+ case FM_PCD_IOC_MATCH_TABLE_DELETE: -+ { -+ ioc_fm_obj_t id; -+ -+ memset(&id, 0 , sizeof(ioc_fm_obj_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_obj_t compat_id; -+ -+ if (copy_from_user(&compat_id, (ioc_compat_fm_obj_t *) compat_ptr(arg), sizeof(ioc_compat_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_obj_delete(&compat_id, &id); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(&id, (ioc_fm_obj_t *) arg, sizeof(ioc_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_PCD_MatchTableDelete(id.obj); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_CC_ROOT_BUILD_COMPAT: -+#endif -+ case FM_PCD_IOC_CC_ROOT_BUILD: -+ { -+ ioc_fm_pcd_cc_tree_params_t *param; -+ -+ param = (ioc_fm_pcd_cc_tree_params_t *) XX_Malloc(sizeof(ioc_fm_pcd_cc_tree_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_cc_tree_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_tree_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_tree_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_tree_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_tree_params_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_cc_tree_params_t *)compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_cc_tree_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_cc_tree(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_cc_tree_params_t *)arg, -+ sizeof(ioc_fm_pcd_cc_tree_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ param->id = FM_PCD_CcRootBuild(p_LnxWrpFmDev->h_PcdDev, (t_FmPcdCcTreeParams*)param); -+ -+ if (!param->id) { -+ XX_Free(param); -+ err = E_INVALID_VALUE; -+ /* Since the LLD has no errno-style error reporting, -+ we're left here with no other option than to report -+ a generic E_INVALID_VALUE */ -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_tree_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_tree_params_t *) XX_Malloc(sizeof(ioc_compat_fm_pcd_cc_tree_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_tree_params_t)); -+ -+ compat_copy_fm_pcd_cc_tree(compat_param, param, COMPAT_K_TO_US); -+ -+ if (copy_to_user((ioc_compat_fm_pcd_cc_tree_params_t *)compat_ptr(arg), -+ compat_param, -+ sizeof(ioc_compat_fm_pcd_cc_tree_params_t))) -+ err = E_READ_FAILED; -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_pcd_cc_tree_params_t *)arg, -+ param, -+ sizeof(ioc_fm_pcd_cc_tree_params_t))) -+ err = E_READ_FAILED; -+ } -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_CC_ROOT_DELETE_COMPAT: -+#endif -+ case FM_PCD_IOC_CC_ROOT_DELETE: -+ { -+ ioc_fm_obj_t id; -+ -+ memset(&id, 0 , sizeof(ioc_fm_obj_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_obj_t compat_id; -+ -+ if (copy_from_user(&compat_id, (ioc_compat_fm_obj_t *) compat_ptr(arg), sizeof(ioc_compat_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_obj_delete(&compat_id, &id); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(&id, (ioc_fm_obj_t *) arg, sizeof(ioc_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_PCD_CcRootDelete(id.obj); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_PLCR_PROFILE_SET_COMPAT: -+#endif -+ case FM_PCD_IOC_PLCR_PROFILE_SET: -+ { -+ ioc_fm_pcd_plcr_profile_params_t *param; -+ -+ param = (ioc_fm_pcd_plcr_profile_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_plcr_profile_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_plcr_profile_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_plcr_profile_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_plcr_profile_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_plcr_profile_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_plcr_profile_params_t)); -+ if (copy_from_user(compat_param, ( -+ ioc_compat_fm_pcd_plcr_profile_params_t *)compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_plcr_profile_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_plcr_profile(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_plcr_profile_params_t *)arg, -+ sizeof(ioc_fm_pcd_plcr_profile_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ if (!param->modify && -+ (((t_FmPcdPlcrProfileParams*)param)->id.newParams.profileType != e_FM_PCD_PLCR_SHARED)) -+ { -+ t_Handle h_Port; -+ ioc_fm_pcd_port_params_t *port_params; -+ -+ port_params = (ioc_fm_pcd_port_params_t*) XX_Malloc(sizeof(ioc_fm_pcd_port_params_t)); -+ if (!port_params) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(port_params, 0, sizeof(ioc_fm_pcd_port_params_t)); -+ if (copy_from_user(port_params, (ioc_fm_pcd_port_params_t*)((t_FmPcdPlcrProfileParams*)param)->id.newParams.h_FmPort, -+ sizeof(ioc_fm_pcd_port_params_t))) -+ { -+ XX_Free(port_params); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ switch(port_params->port_type) -+ { -+ case (e_IOC_FM_PORT_TYPE_RX): -+ if (port_params->port_id < FM_MAX_NUM_OF_1G_RX_PORTS) { -+ h_Port = p_LnxWrpFmDev->rxPorts[port_params->port_id].h_Dev; -+ break; -+ } -+ goto invalid_port_id; -+ -+ case (e_IOC_FM_PORT_TYPE_RX_10G): -+ if (port_params->port_id < FM_MAX_NUM_OF_10G_RX_PORTS) { -+#ifndef CONFIG_FMAN_ARM -+ if (IS_T1023_T1024) { -+ h_Port = p_LnxWrpFmDev->rxPorts[port_params->port_id].h_Dev; -+ } else { -+#else -+ { -+#endif -+ h_Port = p_LnxWrpFmDev->rxPorts[port_params->port_id + FM_MAX_NUM_OF_1G_RX_PORTS].h_Dev; -+ } -+ break; -+ } -+ goto invalid_port_id; -+ -+ case (e_IOC_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ if (port_params->port_id && port_params->port_id < FM_MAX_NUM_OF_OH_PORTS) { -+ h_Port = p_LnxWrpFmDev->opPorts[port_params->port_id - 1].h_Dev; -+ break; -+ } -+ goto invalid_port_id; -+ -+ default: -+invalid_port_id: -+ XX_Free(port_params); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, NO_MSG); -+ } -+ -+ ((t_FmPcdPlcrProfileParams*)param)->id.newParams.h_FmPort = h_Port; -+ XX_Free(port_params); -+ } -+ -+ param->id = FM_PCD_PlcrProfileSet(p_LnxWrpFmDev->h_PcdDev, (t_FmPcdPlcrProfileParams*)param); -+ -+ if (!param->id) { -+ XX_Free(param); -+ err = E_INVALID_VALUE; -+ /* Since the LLD has no errno-style error reporting, -+ we're left here with no other option than to report -+ a generic E_INVALID_VALUE */ -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_plcr_profile_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_plcr_profile_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_plcr_profile_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_plcr_profile_params_t)); -+ compat_copy_fm_pcd_plcr_profile(compat_param, param, COMPAT_K_TO_US); -+ if (copy_to_user((ioc_compat_fm_pcd_plcr_profile_params_t *) compat_ptr(arg), -+ compat_param, -+ sizeof(ioc_compat_fm_pcd_plcr_profile_params_t))) -+ err = E_READ_FAILED; -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_pcd_plcr_profile_params_t *)arg, -+ param, -+ sizeof(ioc_fm_pcd_plcr_profile_params_t))) -+ err = E_READ_FAILED; -+ } -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_PLCR_PROFILE_DELETE_COMPAT: -+#endif -+ case FM_PCD_IOC_PLCR_PROFILE_DELETE: -+ { -+ ioc_fm_obj_t id; -+ -+ memset(&id, 0 , sizeof(ioc_fm_obj_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_obj_t compat_id; -+ -+ if (copy_from_user(&compat_id, (ioc_compat_fm_obj_t *) compat_ptr(arg), sizeof(ioc_compat_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_obj_delete(&compat_id, &id); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(&id, (ioc_fm_obj_t *) arg, sizeof(ioc_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_PCD_PlcrProfileDelete(id.obj); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_CC_ROOT_MODIFY_NEXT_ENGINE_COMPAT: -+#endif -+ case FM_PCD_IOC_CC_ROOT_MODIFY_NEXT_ENGINE: -+ { -+ ioc_fm_pcd_cc_tree_modify_next_engine_params_t *param; -+ -+ param = (ioc_fm_pcd_cc_tree_modify_next_engine_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_cc_tree_modify_next_engine_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_cc_tree_modify_next_engine_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_tree_modify_next_engine_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_tree_modify_next_engine_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_tree_modify_next_engine_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_tree_modify_next_engine_params_t)); -+ if (copy_from_user(compat_param, (ioc_compat_fm_pcd_cc_tree_modify_next_engine_params_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_cc_tree_modify_next_engine_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_fm_pcd_cc_tree_modify_next_engine(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_cc_tree_modify_next_engine_params_t *)arg, -+ sizeof(ioc_fm_pcd_cc_tree_modify_next_engine_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = FM_PCD_CcRootModifyNextEngine(param->id, -+ param->grp_indx, -+ param->indx, -+ (t_FmPcdCcNextEngineParams*)(¶m->cc_next_engine_params)); -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_MATCH_TABLE_MODIFY_NEXT_ENGINE_COMPAT: -+#endif -+ case FM_PCD_IOC_MATCH_TABLE_MODIFY_NEXT_ENGINE: -+ { -+ ioc_fm_pcd_cc_node_modify_next_engine_params_t *param; -+ -+ param = (ioc_fm_pcd_cc_node_modify_next_engine_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_cc_node_modify_next_engine_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_cc_node_modify_next_engine_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t)); -+ if (copy_from_user(compat_param, (ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_cc_node_modify_next_engine(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_cc_node_modify_next_engine_params_t *)arg, -+ sizeof(ioc_fm_pcd_cc_node_modify_next_engine_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = FM_PCD_MatchTableModifyNextEngine(param->id, -+ param->key_indx, -+ (t_FmPcdCcNextEngineParams*)(¶m->cc_next_engine_params)); -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_MATCH_TABLE_MODIFY_MISS_NEXT_ENGINE_COMPAT: -+#endif -+ case FM_PCD_IOC_MATCH_TABLE_MODIFY_MISS_NEXT_ENGINE: -+ { -+ ioc_fm_pcd_cc_node_modify_next_engine_params_t *param; -+ -+ param = (ioc_fm_pcd_cc_node_modify_next_engine_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_cc_node_modify_next_engine_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_cc_node_modify_next_engine_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t)); -+ if (copy_from_user(compat_param, (ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_cc_node_modify_next_engine(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_cc_node_modify_next_engine_params_t *) arg, -+ sizeof(ioc_fm_pcd_cc_node_modify_next_engine_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = FM_PCD_MatchTableModifyMissNextEngine(param->id, -+ (t_FmPcdCcNextEngineParams*)(¶m->cc_next_engine_params)); -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_MATCH_TABLE_REMOVE_KEY_COMPAT: -+#endif -+ case FM_PCD_IOC_MATCH_TABLE_REMOVE_KEY: -+ { -+ ioc_fm_pcd_cc_node_remove_key_params_t *param; -+ -+ param = (ioc_fm_pcd_cc_node_remove_key_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_cc_node_remove_key_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_cc_node_remove_key_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_node_remove_key_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_node_remove_key_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_node_remove_key_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_node_remove_key_params_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_cc_node_remove_key_params_t *)compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_cc_node_remove_key_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ param->id = compat_ptr(compat_param->id); -+ param->key_indx = compat_param->key_indx; -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_cc_node_remove_key_params_t *) arg, -+ sizeof(ioc_fm_pcd_cc_node_remove_key_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = FM_PCD_MatchTableRemoveKey(param->id, param->key_indx); -+ -+ XX_Free(param); -+ break; -+ } -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_MATCH_TABLE_ADD_KEY_COMPAT: -+#endif -+ case FM_PCD_IOC_MATCH_TABLE_ADD_KEY: -+ { -+ ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t *param; -+ -+ param = (ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t *)compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_cc_node_modify_key_and_next_engine(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t *)arg, -+ sizeof(ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ if (param->key_size) -+ { -+ int size = 0; -+ -+ if (param->key_params.p_key) size += param->key_size; -+ if (param->key_params.p_mask) size += param->key_size; -+ -+ if (size) -+ { -+ uint8_t *p_tmp; -+ -+ p_tmp = (uint8_t*) XX_Malloc(size); -+ if (!p_tmp) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD key/mask")); -+ } -+ -+ if (param->key_params.p_key) -+ { -+ if (copy_from_user(p_tmp, param->key_params.p_key, param->key_size)) -+ { -+ XX_Free(p_tmp); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ param->key_params.p_key = p_tmp; -+ } -+ -+ if (param->key_params.p_mask) -+ { -+ p_tmp += param->key_size; -+ if (copy_from_user(p_tmp, param->key_params.p_mask, param->key_size)) -+ { -+ XX_Free(p_tmp - param->key_size); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ param->key_params.p_mask = p_tmp; -+ } -+ } -+ } -+ -+ err = FM_PCD_MatchTableAddKey( -+ param->id, -+ param->key_indx, -+ param->key_size, -+ (t_FmPcdCcKeyParams*)¶m->key_params); -+ -+ if (param->key_params.p_key) -+ XX_Free(param->key_params.p_key); -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_MATCH_TABLE_MODIFY_KEY_AND_NEXT_ENGINE_COMPAT: -+#endif -+ case FM_PCD_IOC_MATCH_TABLE_MODIFY_KEY_AND_NEXT_ENGINE: -+ { -+ ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t *param; -+ -+ param = (ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t *)compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_cc_node_modify_key_and_next_engine(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t *)arg, -+ sizeof(ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = FM_PCD_MatchTableModifyKeyAndNextEngine(param->id, -+ param->key_indx, -+ param->key_size, -+ (t_FmPcdCcKeyParams*)(¶m->key_params)); -+ -+ XX_Free(param); -+ break; -+ } -+ -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_MATCH_TABLE_GET_KEY_STAT_COMPAT: -+#endif -+ case FM_PCD_IOC_MATCH_TABLE_GET_KEY_STAT: -+ { -+ ioc_fm_pcd_cc_tbl_get_stats_t param; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_tbl_get_stats_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_tbl_get_stats_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t)); -+ if (!compat_param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_cc_tbl_get_stats_t *)compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t))) -+ { -+ XX_Free(compat_param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_cc_tbl_get_stats(compat_param, ¶m, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(¶m, (ioc_fm_pcd_cc_tbl_get_stats_t *)arg, -+ sizeof(ioc_fm_pcd_cc_tbl_get_stats_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ -+ err = FM_PCD_MatchTableGetKeyStatistics((t_Handle) param.id, -+ param.key_index, -+ (t_FmPcdCcKeyStatistics *) ¶m.statistics); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_tbl_get_stats_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_tbl_get_stats_t*) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t)); -+ if (!compat_param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t)); -+ compat_copy_fm_pcd_cc_tbl_get_stats(compat_param, ¶m, COMPAT_K_TO_US); -+ if (copy_to_user((ioc_compat_fm_pcd_cc_tbl_get_stats_t*) compat_ptr(arg), -+ compat_param, -+ sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t))){ -+ XX_Free(compat_param); -+ RETURN_ERROR(MINOR, E_READ_FAILED, NO_MSG); -+ } -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_pcd_cc_tbl_get_stats_t *)arg, -+ ¶m, -+ sizeof(ioc_fm_pcd_cc_tbl_get_stats_t))) -+ RETURN_ERROR(MINOR, E_READ_FAILED, NO_MSG); -+ } -+ -+ break; -+ } -+ -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_MATCH_TABLE_GET_MISS_STAT_COMPAT: -+#endif -+ case FM_PCD_IOC_MATCH_TABLE_GET_MISS_STAT: -+ { -+ ioc_fm_pcd_cc_tbl_get_stats_t param; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_tbl_get_stats_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_tbl_get_stats_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t)); -+ if (!compat_param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_cc_tbl_get_stats_t *)compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t))) -+ { -+ XX_Free(compat_param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_cc_tbl_get_stats(compat_param, ¶m, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(¶m, (ioc_fm_pcd_cc_tbl_get_stats_t *)arg, -+ sizeof(ioc_fm_pcd_cc_tbl_get_stats_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ -+ err = FM_PCD_MatchTableGetMissStatistics((t_Handle) param.id, -+ (t_FmPcdCcKeyStatistics *) ¶m.statistics); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_tbl_get_stats_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_tbl_get_stats_t*) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t)); -+ if (!compat_param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t)); -+ compat_copy_fm_pcd_cc_tbl_get_stats(compat_param, ¶m, COMPAT_K_TO_US); -+ if (copy_to_user((ioc_compat_fm_pcd_cc_tbl_get_stats_t*) compat_ptr(arg), -+ compat_param, -+ sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t))){ -+ XX_Free(compat_param); -+ RETURN_ERROR(MINOR, E_READ_FAILED, NO_MSG); -+ } -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_pcd_cc_tbl_get_stats_t *)arg, -+ ¶m, -+ sizeof(ioc_fm_pcd_cc_tbl_get_stats_t))) -+ RETURN_ERROR(MINOR, E_READ_FAILED, NO_MSG); -+ } -+ -+ break; -+ } -+ -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_HASH_TABLE_GET_MISS_STAT_COMPAT: -+#endif -+ case FM_PCD_IOC_HASH_TABLE_GET_MISS_STAT: -+ { -+ ioc_fm_pcd_cc_tbl_get_stats_t param; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_tbl_get_stats_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_tbl_get_stats_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t)); -+ if (!compat_param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_cc_tbl_get_stats_t *)compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t))) -+ { -+ XX_Free(compat_param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_cc_tbl_get_stats(compat_param, ¶m, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(¶m, (ioc_fm_pcd_cc_tbl_get_stats_t *)arg, -+ sizeof(ioc_fm_pcd_cc_tbl_get_stats_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ -+ err = FM_PCD_HashTableGetMissStatistics((t_Handle) param.id, -+ (t_FmPcdCcKeyStatistics *) ¶m.statistics); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_tbl_get_stats_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_tbl_get_stats_t*) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t)); -+ if (!compat_param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t)); -+ compat_copy_fm_pcd_cc_tbl_get_stats(compat_param, ¶m, COMPAT_K_TO_US); -+ if (copy_to_user((ioc_compat_fm_pcd_cc_tbl_get_stats_t*) compat_ptr(arg), -+ compat_param, -+ sizeof(ioc_compat_fm_pcd_cc_tbl_get_stats_t))){ -+ XX_Free(compat_param); -+ RETURN_ERROR(MINOR, E_READ_FAILED, NO_MSG); -+ } -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_pcd_cc_tbl_get_stats_t *)arg, -+ ¶m, -+ sizeof(ioc_fm_pcd_cc_tbl_get_stats_t))) -+ RETURN_ERROR(MINOR, E_READ_FAILED, NO_MSG); -+ } -+ -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_HASH_TABLE_SET_COMPAT: -+#endif -+ case FM_PCD_IOC_HASH_TABLE_SET: -+ { -+ ioc_fm_pcd_hash_table_params_t *param; -+ -+ param = (ioc_fm_pcd_hash_table_params_t*) XX_Malloc( -+ sizeof(ioc_fm_pcd_hash_table_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_hash_table_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_hash_table_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_hash_table_params_t*) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_hash_table_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_hash_table_params_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_hash_table_params_t*)compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_hash_table_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_hash_table(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_hash_table_params_t *)arg, -+ sizeof(ioc_fm_pcd_hash_table_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ param->id = FM_PCD_HashTableSet(p_LnxWrpFmDev->h_PcdDev, (t_FmPcdHashTableParams *) param); -+ -+ if (!param->id) -+ { -+ XX_Free(param); -+ err = E_INVALID_VALUE; -+ /* Since the LLD has no errno-style error reporting, -+ we're left here with no other option than to report -+ a generic E_INVALID_VALUE */ -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_hash_table_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_hash_table_params_t*) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_hash_table_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_hash_table_params_t)); -+ compat_copy_fm_pcd_hash_table(compat_param, param, COMPAT_K_TO_US); -+ if (copy_to_user((ioc_compat_fm_pcd_hash_table_params_t*) compat_ptr(arg), -+ compat_param, -+ sizeof(ioc_compat_fm_pcd_hash_table_params_t))) -+ err = E_READ_FAILED; -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_pcd_hash_table_params_t *)arg, -+ param, -+ sizeof(ioc_fm_pcd_hash_table_params_t))) -+ err = E_READ_FAILED; -+ } -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_HASH_TABLE_DELETE_COMPAT: -+#endif -+ case FM_PCD_IOC_HASH_TABLE_DELETE: -+ { -+ ioc_fm_obj_t id; -+ -+ memset(&id, 0, sizeof(ioc_fm_obj_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_obj_t compat_id; -+ -+ if (copy_from_user(&compat_id, (ioc_compat_fm_obj_t *) compat_ptr(arg), sizeof(ioc_compat_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ id.obj = compat_pcd_id2ptr(compat_id.obj); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(&id, (ioc_fm_obj_t *) arg, sizeof(ioc_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_PCD_HashTableDelete(id.obj); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_HASH_TABLE_ADD_KEY_COMPAT: -+#endif -+ case FM_PCD_IOC_HASH_TABLE_ADD_KEY: -+ { -+ ioc_fm_pcd_hash_table_add_key_params_t *param = NULL; -+ -+ param = (ioc_fm_pcd_hash_table_add_key_params_t*) XX_Malloc( -+ sizeof(ioc_fm_pcd_hash_table_add_key_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_hash_table_add_key_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_hash_table_add_key_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_hash_table_add_key_params_t*) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_hash_table_add_key_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_hash_table_add_key_params_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_hash_table_add_key_params_t*) compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_hash_table_add_key_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ if (compat_param->key_size) -+ { -+ param->p_hash_tbl = compat_pcd_id2ptr(compat_param->p_hash_tbl); -+ param->key_size = compat_param->key_size; -+ -+ compat_copy_fm_pcd_cc_key(&compat_param->key_params, ¶m->key_params, COMPAT_US_TO_K); -+ } -+ else -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ err = E_INVALID_VALUE; -+ break; -+ } -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_hash_table_add_key_params_t*) arg, -+ sizeof(ioc_fm_pcd_hash_table_add_key_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ if (param->key_size) -+ { -+ int size = 0; -+ -+ if (param->key_params.p_key) size += param->key_size; -+ if (param->key_params.p_mask) size += param->key_size; -+ -+ if (size) -+ { -+ uint8_t *p_tmp; -+ -+ p_tmp = (uint8_t*) XX_Malloc(size); -+ if (!p_tmp) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD key/mask")); -+ } -+ -+ if (param->key_params.p_key) -+ { -+ if (copy_from_user(p_tmp, param->key_params.p_key, param->key_size)) -+ { -+ XX_Free(p_tmp); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ param->key_params.p_key = p_tmp; -+ } -+ -+ if (param->key_params.p_mask) -+ { -+ p_tmp += param->key_size; -+ if (copy_from_user(p_tmp, param->key_params.p_mask, param->key_size)) -+ { -+ XX_Free(p_tmp - param->key_size); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ param->key_params.p_mask = p_tmp; -+ } -+ } -+ } -+ -+ err = FM_PCD_HashTableAddKey( -+ param->p_hash_tbl, -+ param->key_size, -+ (t_FmPcdCcKeyParams*)¶m->key_params); -+ -+ if (param->key_params.p_key) -+ XX_Free(param->key_params.p_key); -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_HASH_TABLE_REMOVE_KEY_COMPAT: -+#endif -+ case FM_PCD_IOC_HASH_TABLE_REMOVE_KEY: -+ { -+ ioc_fm_pcd_hash_table_remove_key_params_t *param = NULL; -+ -+ param = (ioc_fm_pcd_hash_table_remove_key_params_t*) XX_Malloc( -+ sizeof(ioc_fm_pcd_hash_table_remove_key_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_hash_table_remove_key_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_hash_table_remove_key_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_hash_table_remove_key_params_t*) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_hash_table_remove_key_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_hash_table_remove_key_params_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_hash_table_remove_key_params_t*) compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_hash_table_remove_key_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ param->p_hash_tbl = compat_pcd_id2ptr(compat_param->p_hash_tbl); -+ param->key_size = compat_param->key_size; -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_hash_table_remove_key_params_t*)arg, -+ sizeof(ioc_fm_pcd_hash_table_remove_key_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ if (param->key_size) -+ { -+ uint8_t *p_key; -+ -+ p_key = (uint8_t*) XX_Malloc(param->key_size); -+ if (!p_key) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ if (param->p_key && copy_from_user(p_key, param->p_key, param->key_size)) -+ { -+ XX_Free(p_key); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ param->p_key = p_key; -+ } -+ -+ err = FM_PCD_HashTableRemoveKey( -+ param->p_hash_tbl, -+ param->key_size, -+ param->p_key); -+ -+ if (param->p_key) -+ XX_Free(param->p_key); -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_MATCH_TABLE_MODIFY_KEY_COMPAT: -+#endif -+ case FM_PCD_IOC_MATCH_TABLE_MODIFY_KEY: -+ { -+ ioc_fm_pcd_cc_node_modify_key_params_t *param; -+ -+ param = (ioc_fm_pcd_cc_node_modify_key_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_cc_node_modify_key_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_cc_node_modify_key_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_cc_node_modify_key_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_cc_node_modify_key_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_cc_node_modify_key_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_cc_node_modify_key_params_t)); -+ if (copy_from_user(compat_param, (ioc_compat_fm_pcd_cc_node_modify_key_params_t *)compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_cc_node_modify_key_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_cc_node_modify_key(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_cc_node_modify_key_params_t *)arg, -+ sizeof(ioc_fm_pcd_cc_node_modify_key_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ if (param->key_size) -+ { -+ int size = 0; -+ -+ if (param->p_key) size += param->key_size; -+ if (param->p_mask) size += param->key_size; -+ -+ if (size) -+ { -+ uint8_t *p_tmp; -+ -+ p_tmp = (uint8_t*) XX_Malloc(size); -+ if (!p_tmp) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD key/mask")); -+ } -+ -+ if (param->p_key) -+ { -+ if (copy_from_user(p_tmp, param->p_key, param->key_size)) -+ { -+ XX_Free(p_tmp); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ param->p_key = p_tmp; -+ } -+ -+ if (param->p_mask) -+ { -+ p_tmp += param->key_size; -+ if (copy_from_user(p_tmp, param->p_mask, param->key_size)) -+ { -+ XX_Free(p_tmp - param->key_size); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ param->p_mask = p_tmp; -+ } -+ } -+ } -+ -+ err = FM_PCD_MatchTableModifyKey(param->id, -+ param->key_indx, -+ param->key_size, -+ param->p_key, -+ param->p_mask); -+ -+ if (param->p_key) -+ XX_Free(param->p_key); -+ else if (param->p_mask) -+ XX_Free(param->p_mask); -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_MANIP_NODE_SET_COMPAT: -+#endif -+ case FM_PCD_IOC_MANIP_NODE_SET: -+ { -+ ioc_fm_pcd_manip_params_t *param; -+ uint8_t *p_data = NULL; -+ uint8_t size; -+ -+ param = (ioc_fm_pcd_manip_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_manip_params_t)); -+ -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_manip_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_manip_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_manip_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_manip_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_manip_params_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_manip_params_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_manip_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_fm_pcd_manip_set_node(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_manip_params_t *)arg, -+ sizeof(ioc_fm_pcd_manip_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ if (param->type == e_IOC_FM_PCD_MANIP_HDR) -+ { -+ size = param->u.hdr.insrt_params.u.generic.size; -+ p_data = (uint8_t *) XX_Malloc(size); -+ if (!p_data ) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, NO_MSG); -+ } -+ -+ if (param->u.hdr.insrt_params.u.generic.p_data && -+ copy_from_user(p_data, -+ param->u.hdr.insrt_params.u.generic.p_data, size)) -+ { -+ XX_Free(p_data); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ param->u.hdr.insrt_params.u.generic.p_data = p_data; -+ } -+ -+ if (param->id) -+ { -+ /* Security Hole: the user can pass any piece of garbage -+ in 'param->id', and that will go straight through to the LLD, -+ no checks being done by the wrapper! */ -+ err = FM_PCD_ManipNodeReplace( -+ (t_Handle) param->id, -+ (t_FmPcdManipParams*) param); -+ if (err) -+ { -+ if (p_data) -+ XX_Free(p_data); -+ XX_Free(param); -+ break; -+ } -+ } -+ else -+ { -+ param->id = FM_PCD_ManipNodeSet( -+ p_LnxWrpFmDev->h_PcdDev, -+ (t_FmPcdManipParams*) param); -+ if (!param->id) -+ { -+ if (p_data) -+ XX_Free(p_data); -+ XX_Free(param); -+ err = E_INVALID_VALUE; -+ /* Since the LLD has no errno-style error reporting, -+ we're left here with no other option than to report -+ a generic E_INVALID_VALUE */ -+ break; -+ } -+ } -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_manip_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_manip_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_manip_params_t)); -+ if (!compat_param) -+ { -+ if (p_data) -+ XX_Free(p_data); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_manip_params_t)); -+ -+ compat_fm_pcd_manip_set_node(compat_param, param, COMPAT_K_TO_US); -+ -+ if (copy_to_user((ioc_compat_fm_pcd_manip_params_t *) compat_ptr(arg), -+ compat_param, -+ sizeof(ioc_compat_fm_pcd_manip_params_t))) -+ err = E_READ_FAILED; -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_pcd_manip_params_t *)arg, -+ param, sizeof(ioc_fm_pcd_manip_params_t))) -+ err = E_READ_FAILED; -+ } -+ -+ if (p_data) -+ XX_Free(p_data); -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_MANIP_NODE_DELETE_COMPAT: -+#endif -+ case FM_PCD_IOC_MANIP_NODE_DELETE: -+ { -+ ioc_fm_obj_t id; -+ -+ memset(&id, 0, sizeof(ioc_fm_obj_t)); -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_obj_t compat_id; -+ -+ if (copy_from_user(&compat_id, (ioc_compat_fm_obj_t *) compat_ptr(arg), sizeof(ioc_compat_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_obj_delete(&compat_id, &id); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(&id, (ioc_fm_obj_t *) arg, sizeof(ioc_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_PCD_ManipNodeDelete(id.obj); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_MANIP_GET_STATS_COMPAT: -+#endif -+ case FM_PCD_IOC_MANIP_GET_STATS: -+ { -+ ioc_fm_pcd_manip_get_stats_t param; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_manip_get_stats_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_manip_get_stats_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_manip_get_stats_t)); -+ if (!compat_param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_manip_get_stats_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_manip_get_stats_t *)compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_manip_get_stats_t))) -+ { -+ XX_Free(compat_param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_manip_get_stats(compat_param, ¶m, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(¶m, (ioc_fm_pcd_manip_get_stats_t *)arg, -+ sizeof(ioc_fm_pcd_manip_get_stats_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_PCD_ManipGetStatistics((t_Handle) param.id, -+ (t_FmPcdManipStats*) ¶m.stats); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_manip_get_stats_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_manip_get_stats_t*) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_manip_get_stats_t)); -+ if (!compat_param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_manip_get_stats_t)); -+ compat_copy_fm_pcd_manip_get_stats(compat_param, ¶m, COMPAT_K_TO_US); -+ if (copy_to_user((ioc_compat_fm_pcd_manip_get_stats_t*) compat_ptr(arg), -+ compat_param, -+ sizeof(ioc_compat_fm_pcd_manip_get_stats_t))){ -+ XX_Free(compat_param); -+ RETURN_ERROR(MINOR, E_READ_FAILED, NO_MSG); -+ } -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ if (copy_to_user((ioc_fm_pcd_manip_get_stats_t *)arg, -+ ¶m, -+ sizeof(ioc_fm_pcd_manip_get_stats_t))) -+ RETURN_ERROR(MINOR, E_READ_FAILED, NO_MSG); -+ -+ break; -+ } -+ -+#if (DPAA_VERSION >= 11) -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_FRM_REPLIC_GROUP_SET_COMPAT: -+#endif -+ case FM_PCD_IOC_FRM_REPLIC_GROUP_SET: -+ { -+ ioc_fm_pcd_frm_replic_group_params_t *param; -+ -+ param = (ioc_fm_pcd_frm_replic_group_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_frm_replic_group_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_frm_replic_group_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_frm_replic_group_params_t -+ *compat_param; -+ -+ compat_param = -+ (ioc_compat_fm_pcd_frm_replic_group_params_t *) -+ XX_Malloc(sizeof(ioc_compat_fm_pcd_frm_replic_group_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, -+ ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_frm_replic_group_params_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_frm_replic_group_params_t *) -+ compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_frm_replic_group_params_t))) { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_READ_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_frm_replic_group_params(compat_param, -+ param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, -+ (ioc_fm_pcd_frm_replic_group_params_t *)arg, -+ sizeof(ioc_fm_pcd_frm_replic_group_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_READ_FAILED, NO_MSG); -+ } -+ } -+ -+ param->id = FM_PCD_FrmReplicSetGroup(p_LnxWrpFmDev->h_PcdDev, -+ (t_FmPcdFrmReplicGroupParams*)param); -+ -+ if (!param->id) { -+ XX_Free(param); -+ err = E_INVALID_VALUE; -+ /* -+ * Since the LLD has no errno-style error reporting, -+ * we're left here with no other option than to report -+ * a generic E_INVALID_VALUE -+ */ -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_frm_replic_group_params_t -+ *compat_param; -+ -+ compat_param = -+ (ioc_compat_fm_pcd_frm_replic_group_params_t *) -+ XX_Malloc(sizeof(ioc_compat_fm_pcd_frm_replic_group_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, -+ ("IOCTL FM PCD")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_frm_replic_group_params_t)); -+ compat_copy_fm_pcd_frm_replic_group_params(compat_param, -+ param, COMPAT_K_TO_US); -+ if (copy_to_user( -+ (ioc_compat_fm_pcd_frm_replic_group_params_t *) -+ compat_ptr(arg), -+ compat_param, -+ sizeof(ioc_compat_fm_pcd_frm_replic_group_params_t))) -+ err = E_WRITE_FAILED; -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_to_user( -+ (ioc_fm_pcd_frm_replic_group_params_t *)arg, -+ param, -+ sizeof(ioc_fm_pcd_frm_replic_group_params_t))) -+ err = E_WRITE_FAILED; -+ } -+ -+ XX_Free(param); -+ break; -+ } -+ break; -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_FRM_REPLIC_GROUP_DELETE_COMPAT: -+#endif -+ case FM_PCD_IOC_FRM_REPLIC_GROUP_DELETE: -+ { -+ ioc_fm_obj_t id; -+ -+ memset(&id, 0, sizeof(ioc_fm_obj_t)); -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_obj_t compat_id; -+ -+ if (copy_from_user(&compat_id, -+ (ioc_compat_fm_obj_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_obj_t))) -+ break; -+ compat_obj_delete(&compat_id, &id); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(&id, (ioc_fm_obj_t *) arg, -+ sizeof(ioc_fm_obj_t))) -+ break; -+ } -+ -+ return FM_PCD_FrmReplicDeleteGroup(id.obj); -+ } -+ break; -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_FRM_REPLIC_MEMBER_ADD_COMPAT: -+#endif -+ case FM_PCD_IOC_FRM_REPLIC_MEMBER_ADD: -+ { -+ ioc_fm_pcd_frm_replic_member_params_t param; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_frm_replic_member_params_t compat_param; -+ -+ if (copy_from_user(&compat_param, compat_ptr(arg), sizeof(compat_param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_copy_fm_pcd_frm_replic_member_params(&compat_param, ¶m, COMPAT_US_TO_K); -+ } -+ else -+#endif -+ if (copy_from_user(¶m, (void *)arg, sizeof(param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ return FM_PCD_FrmReplicAddMember(param.member.h_replic_group, -+ param.member.member_index, -+ (t_FmPcdCcNextEngineParams*)¶m.next_engine_params); -+ } -+ break; -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_FRM_REPLIC_MEMBER_REMOVE_COMPAT: -+#endif -+ case FM_PCD_IOC_FRM_REPLIC_MEMBER_REMOVE: -+ { -+ ioc_fm_pcd_frm_replic_member_t param; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_frm_replic_member_t compat_param; -+ -+ if (copy_from_user(&compat_param, compat_ptr(arg), sizeof(compat_param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_copy_fm_pcd_frm_replic_member(&compat_param, ¶m, COMPAT_US_TO_K); -+ } -+ else -+#endif -+ if (copy_from_user(¶m, (void *)arg, sizeof(param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ return FM_PCD_FrmReplicRemoveMember(param.h_replic_group, param.member_index); -+ } -+ break; -+ -+#if defined(CONFIG_COMPAT) -+ case FM_IOC_VSP_CONFIG_COMPAT: -+#endif -+ case FM_IOC_VSP_CONFIG: -+ { -+ ioc_fm_vsp_params_t param; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_vsp_params_t compat_param; -+ -+ if (copy_from_user(&compat_param, compat_ptr(arg), sizeof(compat_param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_copy_fm_vsp_params(&compat_param, ¶m, COMPAT_US_TO_K); -+ } -+ else -+#endif -+ if (copy_from_user(¶m, (void *)arg, sizeof(param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ { -+ uint8_t portId = param.port_params.port_id; -+ param.p_fm = p_LnxWrpFmDev->h_Dev; -+ param.liodn_offset = -+ p_LnxWrpFmDev->rxPorts[portId].settings.param.specificParams.rxParams.liodnOffset; -+ } -+ param.id = FM_VSP_Config((t_FmVspParams *)¶m); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_vsp_params_t compat_param; -+ -+ memset(&compat_param, 0, sizeof(compat_param)); -+ compat_copy_fm_vsp_params(&compat_param, ¶m, COMPAT_K_TO_US); -+ -+ if (copy_to_user(compat_ptr(arg), &compat_param, sizeof(compat_param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ else -+#endif -+ if (copy_to_user((void *)arg, ¶m, sizeof(param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_IOC_VSP_INIT_COMPAT: -+#endif -+ case FM_IOC_VSP_INIT: -+ { -+ ioc_fm_obj_t id; -+ -+ memset(&id, 0, sizeof(ioc_fm_obj_t)); -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_obj_t compat_id; -+ -+ if (copy_from_user(&compat_id, -+ (ioc_compat_fm_obj_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_obj_t))) -+ break; -+ id.obj = compat_pcd_id2ptr(compat_id.obj); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(&id, (ioc_fm_obj_t *) arg, -+ sizeof(ioc_fm_obj_t))) -+ break; -+ } -+ -+ return FM_VSP_Init(id.obj); -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_IOC_VSP_FREE_COMPAT: -+#endif -+ case FM_IOC_VSP_FREE: -+ { -+ ioc_fm_obj_t id; -+ -+ memset(&id, 0, sizeof(ioc_fm_obj_t)); -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_obj_t compat_id; -+ -+ if (copy_from_user(&compat_id, -+ (ioc_compat_fm_obj_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_obj_t))) -+ break; -+ compat_obj_delete(&compat_id, &id); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(&id, (ioc_fm_obj_t *) arg, -+ sizeof(ioc_fm_obj_t))) -+ break; -+ } -+ -+ return FM_VSP_Free(id.obj); -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_IOC_VSP_CONFIG_POOL_DEPLETION_COMPAT: -+#endif -+ case FM_IOC_VSP_CONFIG_POOL_DEPLETION: -+ { -+ ioc_fm_buf_pool_depletion_params_t param; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_buf_pool_depletion_params_t compat_param; -+ -+ if (copy_from_user(&compat_param, compat_ptr(arg), sizeof(compat_param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_copy_fm_buf_pool_depletion_params(&compat_param, ¶m, COMPAT_US_TO_K); -+ } -+ else -+#endif -+ if (copy_from_user(¶m, (void *)arg, sizeof(param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ if (FM_VSP_ConfigPoolDepletion(param.p_fm_vsp, -+ (t_FmBufPoolDepletion *)¶m.fm_buf_pool_depletion)) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ break; -+ } -+ -+ -+#if defined(CONFIG_COMPAT) -+ case FM_IOC_VSP_CONFIG_BUFFER_PREFIX_CONTENT_COMPAT: -+#endif -+ case FM_IOC_VSP_CONFIG_BUFFER_PREFIX_CONTENT: -+ { -+ ioc_fm_buffer_prefix_content_params_t param; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_buffer_prefix_content_params_t compat_param; -+ -+ if (copy_from_user(&compat_param, compat_ptr(arg), sizeof(compat_param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_copy_fm_buffer_prefix_content_params(&compat_param, ¶m, COMPAT_US_TO_K); -+ } -+ else -+#endif -+ if (copy_from_user(¶m, (void *)arg, sizeof(param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ if (FM_VSP_ConfigBufferPrefixContent(param.p_fm_vsp, -+ (t_FmBufferPrefixContent *)¶m.fm_buffer_prefix_content)) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_IOC_VSP_CONFIG_NO_SG_COMPAT: -+#endif -+ case FM_IOC_VSP_CONFIG_NO_SG: -+ { -+ ioc_fm_vsp_config_no_sg_params_t param; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_vsp_config_no_sg_params_t compat_param; -+ -+ if (copy_from_user(&compat_param, compat_ptr(arg), sizeof(compat_param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_copy_fm_vsp_config_no_sg_params(&compat_param, ¶m, COMPAT_US_TO_K); -+ } -+ else -+#endif -+ if (copy_from_user(¶m, (void *)arg, sizeof(param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ if (FM_VSP_ConfigNoScatherGather(param.p_fm_vsp, param.no_sg)) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_IOC_VSP_GET_BUFFER_PRS_RESULT_COMPAT: -+#endif -+ case FM_IOC_VSP_GET_BUFFER_PRS_RESULT: -+ { -+ ioc_fm_vsp_prs_result_params_t param; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_vsp_prs_result_params_t compat_param; -+ -+ if (copy_from_user(&compat_param, compat_ptr(arg), sizeof(compat_param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_copy_fm_vsp_prs_result_params(&compat_param, ¶m, COMPAT_US_TO_K); -+ } -+ else -+#endif -+ if (copy_from_user(¶m, (void *)arg, sizeof(param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ /* this call just adds the parse results offset to p_data */ -+ param.p_data = FM_VSP_GetBufferPrsResult(param.p_fm_vsp, param.p_data); -+ -+ if (!param.p_data) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_vsp_prs_result_params_t compat_param; -+ -+ memset(&compat_param, 0, sizeof(compat_param)); -+ compat_copy_fm_vsp_prs_result_params(&compat_param, ¶m, COMPAT_K_TO_US); -+ -+ if (copy_to_user(compat_ptr(arg), &compat_param, sizeof(compat_param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ else -+#endif -+ if (copy_to_user((void *)arg, ¶m, sizeof(param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ break; -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+#ifdef FM_CAPWAP_SUPPORT -+#warning "feature not supported!" -+#if defined(CONFIG_COMPAT) -+ case FM_PCD_IOC_STATISTICS_SET_NODE_COMPAT: -+#endif -+ case FM_PCD_IOC_STATISTICS_SET_NODE: -+ { -+/* ioc_fm_pcd_stats_params_t param; -+ ... -+ param->id = FM_PCD_StatisticsSetNode(p_LnxWrpFmDev->h_PcdDev, -+ (t_FmPcdStatsParams *)¶m); -+*/ -+ err = E_NOT_SUPPORTED; -+ break; -+ } -+#endif /* FM_CAPWAP_SUPPORT */ -+ -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, -+ ("invalid ioctl: cmd:0x%08x(type:0x%02x, nr: %d.\n", -+ cmd, _IOC_TYPE(cmd), _IOC_NR(cmd))); -+ } -+ -+ if (err) -+ RETURN_ERROR(MINOR, err, ("IOCTL FM PCD")); -+ -+ return E_OK; -+} -+ -+void FM_Get_Api_Version(ioc_fm_api_version_t *p_version) -+{ -+ p_version->version.major = FMD_API_VERSION_MAJOR; -+ p_version->version.minor = FMD_API_VERSION_MINOR; -+ p_version->version.respin = FMD_API_VERSION_RESPIN; -+ p_version->version.reserved = 0; -+} -+ -+t_Error LnxwrpFmIOCTL(t_LnxWrpFmDev *p_LnxWrpFmDev, unsigned int cmd, unsigned long arg, bool compat) -+{ -+ t_Error err = E_OK; -+ -+ switch (cmd) -+ { -+ case FM_IOC_SET_PORTS_BANDWIDTH: -+ { -+ ioc_fm_port_bandwidth_params *param; -+ -+ param = (ioc_fm_port_bandwidth_params*) XX_Malloc(sizeof(ioc_fm_port_bandwidth_params)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_port_bandwidth_params)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (copy_from_user(param, (ioc_fm_port_bandwidth_params*)compat_ptr(arg), sizeof(ioc_fm_port_bandwidth_params))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_port_bandwidth_params*)arg, sizeof(ioc_fm_port_bandwidth_params))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = FM_SetPortsBandwidth(p_LnxWrpFmDev->h_Dev, (t_FmPortsBandwidthParams*) param); -+ -+ XX_Free(param); -+ break; -+ } -+ -+ case FM_IOC_GET_REVISION: -+ { -+ ioc_fm_revision_info_t *param; -+ -+ param = (ioc_fm_revision_info_t *) XX_Malloc(sizeof(ioc_fm_revision_info_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ FM_GetRevision(p_LnxWrpFmDev->h_Dev, (t_FmRevisionInfo*)param); -+ /* This one never returns anything other than E_OK */ -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (copy_to_user((ioc_fm_revision_info_t *)compat_ptr(arg), -+ param, -+ sizeof(ioc_fm_revision_info_t))){ -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_READ_FAILED, NO_MSG); -+ } -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_revision_info_t *)arg, -+ param, -+ sizeof(ioc_fm_revision_info_t))){ -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_READ_FAILED, NO_MSG); -+ } -+ } -+ XX_Free(param); -+ break; -+ } -+ -+ case FM_IOC_SET_COUNTER: -+ { -+ ioc_fm_counters_params_t *param; -+ -+ param = (ioc_fm_counters_params_t *) XX_Malloc(sizeof(ioc_fm_counters_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_counters_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (copy_from_user(param, (ioc_fm_counters_params_t *)compat_ptr(arg), sizeof(ioc_fm_counters_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_counters_params_t *)arg, sizeof(ioc_fm_counters_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = FM_ModifyCounter(p_LnxWrpFmDev->h_Dev, param->cnt, param->val); -+ -+ XX_Free(param); -+ break; -+ } -+ -+ case FM_IOC_GET_COUNTER: -+ { -+ ioc_fm_counters_params_t *param; -+ -+ param = (ioc_fm_counters_params_t *) XX_Malloc(sizeof(ioc_fm_counters_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PCD")); -+ -+ memset(param, 0, sizeof(ioc_fm_counters_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (copy_from_user(param, (ioc_fm_counters_params_t *)compat_ptr(arg), sizeof(ioc_fm_counters_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_counters_params_t *)arg, sizeof(ioc_fm_counters_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ param->val = FM_GetCounter(p_LnxWrpFmDev->h_Dev, param->cnt); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (copy_to_user((ioc_fm_counters_params_t *)compat_ptr(arg), param, sizeof(ioc_fm_counters_params_t))) -+ err = E_READ_FAILED; -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_counters_params_t *)arg, param, sizeof(ioc_fm_counters_params_t))) -+ err = E_READ_FAILED; -+ } -+ -+ XX_Free(param); -+ break; -+ } -+ -+ case FM_IOC_FORCE_INTR: -+ { -+ ioc_fm_exceptions param; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (get_user(param, (ioc_fm_exceptions*) compat_ptr(arg))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ else -+#endif -+ { -+ if (get_user(param, (ioc_fm_exceptions*)arg)) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_ForceIntr(p_LnxWrpFmDev->h_Dev, (e_FmExceptions)param); -+ break; -+ } -+ -+ case FM_IOC_GET_API_VERSION: -+ { -+ ioc_fm_api_version_t version; -+ -+ FM_Get_Api_Version(&version); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (copy_to_user( -+ (ioc_fm_api_version_t *)compat_ptr(arg), -+ &version, sizeof(version))) -+ err = E_READ_FAILED; -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_api_version_t *)arg, -+ &version, sizeof(version))) -+ err = E_READ_FAILED; -+ } -+ } -+ break; -+ -+ case FM_IOC_CTRL_MON_START: -+ { -+ FM_CtrlMonStart(p_LnxWrpFmDev->h_Dev); -+ } -+ break; -+ -+ case FM_IOC_CTRL_MON_STOP: -+ { -+ FM_CtrlMonStop(p_LnxWrpFmDev->h_Dev); -+ } -+ break; -+ -+#if defined(CONFIG_COMPAT) -+ case FM_IOC_CTRL_MON_GET_COUNTERS_COMPAT: -+#endif -+ case FM_IOC_CTRL_MON_GET_COUNTERS: -+ { -+ ioc_fm_ctrl_mon_counters_params_t param; -+ t_FmCtrlMon mon; -+ -+#if defined(CONFIG_COMPAT) -+ ioc_compat_fm_ctrl_mon_counters_params_t compat_param; -+ -+ if (compat) -+ { -+ if (copy_from_user(&compat_param, (void *)compat_ptr(arg), -+ sizeof(compat_param))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ param.fm_ctrl_index = compat_param.fm_ctrl_index; -+ param.p_mon = (fm_ctrl_mon_t *)compat_ptr(compat_param.p_mon); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(¶m, (void *)arg, sizeof(ioc_fm_ctrl_mon_counters_params_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ if (FM_CtrlMonGetCounters(p_LnxWrpFmDev->h_Dev, param.fm_ctrl_index, &mon)) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ if (copy_to_user(param.p_mon, &mon, sizeof(t_FmCtrlMon))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ break; -+ -+ default: -+ return LnxwrpFmPcdIOCTL(p_LnxWrpFmDev, cmd, arg, compat); -+ } -+ -+ if (err) -+ RETURN_ERROR(MINOR, E_INVALID_OPERATION, ("IOCTL FM")); -+ -+ return E_OK; -+} -+ -+t_Error LnxwrpFmPortIOCTL(t_LnxWrpFmPortDev *p_LnxWrpFmPortDev, unsigned int cmd, unsigned long arg, bool compat) -+{ -+ t_Error err = E_OK; -+ -+ _fm_ioctl_dbg("cmd:0x%08x(type:0x%02x, nr:%u).\n", -+ cmd, _IOC_TYPE(cmd), _IOC_NR(cmd) - 70); -+ -+ switch (cmd) -+ { -+ case FM_PORT_IOC_DISABLE: -+ FM_PORT_Disable(p_LnxWrpFmPortDev->h_Dev); -+ /* deliberately ignoring error codes here */ -+ return E_OK; -+ -+ case FM_PORT_IOC_ENABLE: -+ FM_PORT_Enable(p_LnxWrpFmPortDev->h_Dev); -+ /* deliberately ignoring error codes here */ -+ return E_OK; -+ -+ case FM_PORT_IOC_SET_ERRORS_ROUTE: -+ { -+ ioc_fm_port_frame_err_select_t errs; -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (get_user(errs, (ioc_fm_port_frame_err_select_t*)compat_ptr(arg))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ else -+#endif -+ { -+ if (get_user(errs, (ioc_fm_port_frame_err_select_t*)arg)) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_PORT_SetErrorsRoute(p_LnxWrpFmPortDev->h_Dev, (fmPortFrameErrSelect_t)errs); -+ break; -+ } -+ -+ case FM_PORT_IOC_SET_RATE_LIMIT: -+ { -+ ioc_fm_port_rate_limit_t *param; -+ -+ param = (ioc_fm_port_rate_limit_t *) XX_Malloc(sizeof(ioc_fm_port_rate_limit_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PORT")); -+ -+ memset(param, 0, sizeof(ioc_fm_port_rate_limit_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (copy_from_user(param, (ioc_fm_port_rate_limit_t *)compat_ptr(arg), sizeof(ioc_fm_port_rate_limit_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_port_rate_limit_t *)arg, sizeof(ioc_fm_port_rate_limit_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = FM_PORT_SetRateLimit(p_LnxWrpFmPortDev->h_Dev, (t_FmPortRateLimit *)param); -+ -+ XX_Free(param); -+ break; -+ } -+ -+ case FM_PORT_IOC_REMOVE_RATE_LIMIT: -+ FM_PORT_DeleteRateLimit(p_LnxWrpFmPortDev->h_Dev); -+ /* deliberately ignoring error codes here */ -+ return E_OK; -+ -+ case FM_PORT_IOC_ALLOC_PCD_FQIDS: -+ { -+ ioc_fm_port_pcd_fqids_params_t *param; -+ -+ if (!p_LnxWrpFmPortDev->pcd_owner_params.cba) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("No one to listen on this PCD!!!")); -+ -+ param = (ioc_fm_port_pcd_fqids_params_t *) XX_Malloc(sizeof(ioc_fm_port_pcd_fqids_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PORT")); -+ -+ memset(param, 0, sizeof(ioc_fm_port_pcd_fqids_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (copy_from_user(param, (ioc_fm_port_pcd_fqids_params_t *)compat_ptr(arg), -+ sizeof(ioc_fm_port_pcd_fqids_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_port_pcd_fqids_params_t *)arg, -+ sizeof(ioc_fm_port_pcd_fqids_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ if (p_LnxWrpFmPortDev->pcd_owner_params.cba(p_LnxWrpFmPortDev->pcd_owner_params.dev, -+ param->num_fqids, -+ param->alignment, -+ ¶m->base_fqid)) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("can't allocate fqids for PCD!!!")); -+ } -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (copy_to_user((ioc_fm_port_pcd_fqids_params_t *)compat_ptr(arg), -+ param, sizeof(ioc_fm_port_pcd_fqids_params_t))) -+ err = E_READ_FAILED; -+ } -+ else -+#endif -+ { -+ if (copy_to_user((ioc_fm_port_pcd_fqids_params_t *)arg, -+ param, sizeof(ioc_fm_port_pcd_fqids_params_t))) -+ err = E_READ_FAILED; -+ } -+ -+ XX_Free(param); -+ break; -+ } -+ -+ case FM_PORT_IOC_FREE_PCD_FQIDS: -+ { -+ uint32_t base_fqid; -+ -+ if (!p_LnxWrpFmPortDev->pcd_owner_params.cbf) -+ RETURN_ERROR(MINOR, E_INVALID_STATE, ("No one to listen on this PCD!!!")); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (get_user(base_fqid, (uint32_t*) compat_ptr(arg))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ else -+#endif -+ { -+ if (get_user(base_fqid, (uint32_t*)arg)) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ if (p_LnxWrpFmPortDev->pcd_owner_params.cbf(p_LnxWrpFmPortDev->pcd_owner_params.dev, base_fqid)) -+ err = E_WRITE_FAILED; -+ -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PORT_IOC_SET_PCD_COMPAT: -+#endif -+ case FM_PORT_IOC_SET_PCD: -+ { -+ ioc_fm_port_pcd_params_t *port_pcd_params; -+ ioc_fm_port_pcd_prs_params_t *port_pcd_prs_params; -+ ioc_fm_port_pcd_cc_params_t *port_pcd_cc_params; -+ ioc_fm_port_pcd_kg_params_t *port_pcd_kg_params; -+ ioc_fm_port_pcd_plcr_params_t *port_pcd_plcr_params; -+ -+ port_pcd_params = (ioc_fm_port_pcd_params_t *) XX_Malloc( -+ sizeof(ioc_fm_port_pcd_params_t) + -+ sizeof(ioc_fm_port_pcd_prs_params_t) + -+ sizeof(ioc_fm_port_pcd_cc_params_t) + -+ sizeof(ioc_fm_port_pcd_kg_params_t) + -+ sizeof(ioc_fm_port_pcd_plcr_params_t)); -+ if (!port_pcd_params) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PORT")); -+ -+ memset(port_pcd_params, 0, -+ sizeof(ioc_fm_port_pcd_params_t) + -+ sizeof(ioc_fm_port_pcd_prs_params_t) + -+ sizeof(ioc_fm_port_pcd_cc_params_t) + -+ sizeof(ioc_fm_port_pcd_kg_params_t) + -+ sizeof(ioc_fm_port_pcd_plcr_params_t)); -+ -+ port_pcd_prs_params = (ioc_fm_port_pcd_prs_params_t *) (port_pcd_params + 1); -+ port_pcd_cc_params = (ioc_fm_port_pcd_cc_params_t *) (port_pcd_prs_params + 1); -+ port_pcd_kg_params = (ioc_fm_port_pcd_kg_params_t *) (port_pcd_cc_params + 1); -+ port_pcd_plcr_params = (ioc_fm_port_pcd_plcr_params_t *) (port_pcd_kg_params + 1); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_port_pcd_params_t *compat_port_pcd_params; -+ ioc_fm_port_pcd_prs_params_t *same_port_pcd_prs_params; -+ ioc_compat_fm_port_pcd_cc_params_t *compat_port_pcd_cc_params; -+ ioc_compat_fm_port_pcd_kg_params_t *compat_port_pcd_kg_params; -+ ioc_compat_fm_port_pcd_plcr_params_t *compat_port_pcd_plcr_params; -+ -+ compat_port_pcd_params = (ioc_compat_fm_port_pcd_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_port_pcd_params_t) + -+ sizeof(ioc_fm_port_pcd_prs_params_t) + -+ sizeof(ioc_compat_fm_port_pcd_cc_params_t) + -+ sizeof(ioc_compat_fm_port_pcd_kg_params_t) + -+ sizeof(ioc_compat_fm_port_pcd_plcr_params_t)); -+ if (!compat_port_pcd_params) -+ { -+ XX_Free(port_pcd_params); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PORT")); -+ } -+ -+ memset(compat_port_pcd_params, 0, -+ sizeof(ioc_compat_fm_port_pcd_params_t) + -+ sizeof(ioc_fm_port_pcd_prs_params_t) + -+ sizeof(ioc_compat_fm_port_pcd_cc_params_t) + -+ sizeof(ioc_compat_fm_port_pcd_kg_params_t) + -+ sizeof(ioc_compat_fm_port_pcd_plcr_params_t)); -+ same_port_pcd_prs_params = (ioc_fm_port_pcd_prs_params_t *) (compat_port_pcd_params + 1); -+ compat_port_pcd_cc_params = (ioc_compat_fm_port_pcd_cc_params_t *) (same_port_pcd_prs_params + 1); -+ compat_port_pcd_kg_params = (ioc_compat_fm_port_pcd_kg_params_t *) (compat_port_pcd_cc_params + 1); -+ compat_port_pcd_plcr_params = (ioc_compat_fm_port_pcd_plcr_params_t *) (compat_port_pcd_kg_params + 1); -+ -+ if (copy_from_user(compat_port_pcd_params, -+ (ioc_compat_fm_port_pcd_params_t*) compat_ptr(arg), -+ sizeof(ioc_compat_fm_port_pcd_params_t))) -+ err = E_WRITE_FAILED; -+ -+ while (!err) /* pseudo-while */ -+ { -+ /* set pointers from where to copy from: */ -+ port_pcd_params->p_prs_params = compat_ptr(compat_port_pcd_params->p_prs_params); /* same structure */ -+ port_pcd_params->p_cc_params = compat_ptr(compat_port_pcd_params->p_cc_params); -+ port_pcd_params->p_kg_params = compat_ptr(compat_port_pcd_params->p_kg_params); -+ port_pcd_params->p_plcr_params = compat_ptr(compat_port_pcd_params->p_plcr_params); -+ port_pcd_params->p_ip_reassembly_manip = compat_ptr(compat_port_pcd_params->p_ip_reassembly_manip); -+#if (DPAA_VERSION >= 11) -+ port_pcd_params->p_capwap_reassembly_manip = compat_ptr(compat_port_pcd_params->p_capwap_reassembly_manip); -+#endif -+ /* the prs member is the same, no compat structure...memcpy only */ -+ if (port_pcd_params->p_prs_params) -+ { -+ if (copy_from_user(same_port_pcd_prs_params, -+ port_pcd_params->p_prs_params, -+ sizeof(ioc_fm_port_pcd_prs_params_t))) -+ { -+ err = E_WRITE_FAILED; -+ break; /* from pseudo-while */ -+ } -+ -+ memcpy(port_pcd_prs_params, same_port_pcd_prs_params, sizeof(ioc_fm_port_pcd_prs_params_t)); -+ port_pcd_params->p_prs_params = port_pcd_prs_params; -+ } -+ -+ if (port_pcd_params->p_cc_params) -+ { -+ if (copy_from_user(compat_port_pcd_cc_params, -+ port_pcd_params->p_cc_params, -+ sizeof(ioc_compat_fm_port_pcd_cc_params_t))) -+ { -+ err = E_WRITE_FAILED; -+ break; /* from pseudo-while */ -+ } -+ -+ port_pcd_params->p_cc_params = port_pcd_cc_params; -+ } -+ -+ if (port_pcd_params->p_kg_params) -+ { -+ if (copy_from_user(compat_port_pcd_kg_params, -+ port_pcd_params->p_kg_params, -+ sizeof(ioc_compat_fm_port_pcd_kg_params_t))) -+ { -+ err = E_WRITE_FAILED; -+ break; /* from pseudo-while */ -+ } -+ -+ port_pcd_params->p_kg_params = port_pcd_kg_params; -+ } -+ -+ if (port_pcd_params->p_plcr_params) -+ { -+ if (copy_from_user(compat_port_pcd_plcr_params, -+ port_pcd_params->p_plcr_params, -+ sizeof(ioc_compat_fm_port_pcd_plcr_params_t))) -+ { -+ err = E_WRITE_FAILED; -+ break; /* from pseudo-while */ -+ } -+ -+ port_pcd_params->p_plcr_params = port_pcd_plcr_params; -+ } -+ -+ break; /* pseudo-while: always run once! */ -+ } -+ -+ if (!err) -+ compat_copy_fm_port_pcd(compat_port_pcd_params, port_pcd_params, COMPAT_US_TO_K); -+ -+ XX_Free(compat_port_pcd_params); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(port_pcd_params, -+ (ioc_fm_port_pcd_params_t*) arg, -+ sizeof(ioc_fm_port_pcd_params_t))) -+ err = E_WRITE_FAILED; -+ -+ while (!err) /* pseudo-while */ -+ { -+ if (port_pcd_params->p_prs_params) -+ { -+ if (copy_from_user(port_pcd_prs_params, -+ port_pcd_params->p_prs_params, -+ sizeof(ioc_fm_port_pcd_prs_params_t))) -+ { -+ err = E_WRITE_FAILED; -+ break; /* from pseudo-while */ -+ } -+ -+ port_pcd_params->p_prs_params = port_pcd_prs_params; -+ } -+ -+ if (port_pcd_params->p_cc_params) -+ { -+ if (copy_from_user(port_pcd_cc_params, -+ port_pcd_params->p_cc_params, -+ sizeof(ioc_fm_port_pcd_cc_params_t))) -+ { -+ err = E_WRITE_FAILED; -+ break; /* from pseudo-while */ -+ } -+ -+ port_pcd_params->p_cc_params = port_pcd_cc_params; -+ } -+ -+ if (port_pcd_params->p_kg_params) -+ { -+ if (copy_from_user(port_pcd_kg_params, -+ port_pcd_params->p_kg_params, -+ sizeof(ioc_fm_port_pcd_kg_params_t))) -+ { -+ err = E_WRITE_FAILED; -+ break; /* from pseudo-while */ -+ } -+ -+ port_pcd_params->p_kg_params = port_pcd_kg_params; -+ } -+ -+ if (port_pcd_params->p_plcr_params) -+ { -+ if (copy_from_user(port_pcd_plcr_params, -+ port_pcd_params->p_plcr_params, -+ sizeof(ioc_fm_port_pcd_plcr_params_t))) -+ { -+ err = E_WRITE_FAILED; -+ break; /* from pseudo-while */ -+ } -+ -+ port_pcd_params->p_plcr_params = port_pcd_plcr_params; -+ } -+ -+ break; /* pseudo-while: always run once! */ -+ } -+ } -+ -+ if (!err) -+ err = FM_PORT_SetPCD(p_LnxWrpFmPortDev->h_Dev, (t_FmPortPcdParams*) port_pcd_params); -+ -+ XX_Free(port_pcd_params); -+ break; -+ } -+ -+ case FM_PORT_IOC_DELETE_PCD: -+ err = FM_PORT_DeletePCD(p_LnxWrpFmPortDev->h_Dev); -+ break; -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PORT_IOC_PCD_KG_MODIFY_INITIAL_SCHEME_COMPAT: -+#endif -+ case FM_PORT_IOC_PCD_KG_MODIFY_INITIAL_SCHEME: -+ { -+ ioc_fm_pcd_kg_scheme_select_t *param; -+ -+ param = (ioc_fm_pcd_kg_scheme_select_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_kg_scheme_select_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PORT")); -+ -+ memset(param, 0, sizeof(ioc_fm_pcd_kg_scheme_select_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_kg_scheme_select_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_pcd_kg_scheme_select_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_pcd_kg_scheme_select_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PORT")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_pcd_kg_scheme_select_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_pcd_kg_scheme_select_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_kg_scheme_select_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_kg_scheme_select(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_kg_scheme_select_t *)arg, -+ sizeof(ioc_fm_pcd_kg_scheme_select_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = FM_PORT_PcdKgModifyInitialScheme(p_LnxWrpFmPortDev->h_Dev, (t_FmPcdKgSchemeSelect *)param); -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PORT_IOC_PCD_PLCR_MODIFY_INITIAL_PROFILE_COMPAT: -+#endif -+ case FM_PORT_IOC_PCD_PLCR_MODIFY_INITIAL_PROFILE: -+ { -+ ioc_fm_obj_t id; -+ -+ memset(&id, 0 , sizeof(ioc_fm_obj_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_obj_t compat_id; -+ -+ if (copy_from_user(&compat_id, (ioc_compat_fm_obj_t *) compat_ptr(arg), sizeof(ioc_compat_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ id.obj = compat_ptr(compat_id.obj); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(&id, (ioc_fm_obj_t *) arg, sizeof(ioc_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_PORT_PcdPlcrModifyInitialProfile(p_LnxWrpFmPortDev->h_Dev, id.obj); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PORT_IOC_PCD_KG_BIND_SCHEMES_COMPAT: -+#endif -+ case FM_PORT_IOC_PCD_KG_BIND_SCHEMES: -+ { -+ ioc_fm_pcd_port_schemes_params_t *param; -+ -+ param = (ioc_fm_pcd_port_schemes_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_port_schemes_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PORT")); -+ -+ memset(param, 0 , sizeof(ioc_fm_pcd_port_schemes_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_port_schemes_params_t compat_param; -+ -+ if (copy_from_user(&compat_param, -+ (ioc_compat_fm_pcd_port_schemes_params_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_port_schemes_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_kg_schemes_params(&compat_param, param, COMPAT_US_TO_K); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_port_schemes_params_t *) arg, -+ sizeof(ioc_fm_pcd_port_schemes_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = FM_PORT_PcdKgBindSchemes(p_LnxWrpFmPortDev->h_Dev, (t_FmPcdPortSchemesParams *)param); -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PORT_IOC_PCD_KG_UNBIND_SCHEMES_COMPAT: -+#endif -+ case FM_PORT_IOC_PCD_KG_UNBIND_SCHEMES: -+ { -+ ioc_fm_pcd_port_schemes_params_t *param; -+ -+ param = (ioc_fm_pcd_port_schemes_params_t *) XX_Malloc( -+ sizeof(ioc_fm_pcd_port_schemes_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PORT")); -+ -+ memset(param, 0 , sizeof(ioc_fm_pcd_port_schemes_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_pcd_port_schemes_params_t compat_param; -+ -+ if (copy_from_user(&compat_param, -+ (ioc_compat_fm_pcd_port_schemes_params_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_pcd_port_schemes_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_pcd_kg_schemes_params(&compat_param, param, COMPAT_US_TO_K); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_pcd_port_schemes_params_t *) arg, -+ sizeof(ioc_fm_pcd_port_schemes_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = FM_PORT_PcdKgUnbindSchemes(p_LnxWrpFmPortDev->h_Dev, (t_FmPcdPortSchemesParams *)param); -+ -+ XX_Free(param); -+ break; -+ } -+ -+ case FM_PORT_IOC_PCD_PLCR_ALLOC_PROFILES: -+ { -+ uint16_t num; -+ if (get_user(num, (uint16_t*) arg)) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ err = FM_PORT_PcdPlcrAllocProfiles(p_LnxWrpFmPortDev->h_Dev, num); -+ break; -+ } -+ -+ case FM_PORT_IOC_PCD_PLCR_FREE_PROFILES: -+ err = FM_PORT_PcdPlcrFreeProfiles(p_LnxWrpFmPortDev->h_Dev); -+ break; -+ -+ case FM_PORT_IOC_DETACH_PCD: -+ err = FM_PORT_DetachPCD(p_LnxWrpFmPortDev->h_Dev); -+ break; -+ -+ case FM_PORT_IOC_ATTACH_PCD: -+ err = FM_PORT_AttachPCD(p_LnxWrpFmPortDev->h_Dev); -+ break; -+ -+#if defined(CONFIG_COMPAT) -+ case FM_PORT_IOC_PCD_CC_MODIFY_TREE_COMPAT: -+#endif -+ case FM_PORT_IOC_PCD_CC_MODIFY_TREE: -+ { -+ ioc_fm_obj_t id; -+ -+ memset(&id, 0 , sizeof(ioc_fm_obj_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_obj_t compat_id; -+ -+ if (copy_from_user(&compat_id, (ioc_compat_fm_obj_t *) compat_ptr(arg), sizeof(ioc_compat_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ compat_copy_fm_port_pcd_modify_tree(&compat_id, &id, COMPAT_US_TO_K); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(&id, (ioc_fm_obj_t *) arg, sizeof(ioc_fm_obj_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ err = FM_PORT_PcdCcModifyTree(p_LnxWrpFmPortDev->h_Dev, id.obj); -+ break; -+ } -+ -+ case FM_PORT_IOC_ADD_CONGESTION_GRPS: -+ case FM_PORT_IOC_REMOVE_CONGESTION_GRPS: -+ { -+ ioc_fm_port_congestion_groups_t *param; -+ -+ param = (ioc_fm_port_congestion_groups_t*) XX_Malloc(sizeof(ioc_fm_port_congestion_groups_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PORT")); -+ -+ memset(param, 0, sizeof(ioc_fm_port_congestion_groups_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (copy_from_user(param, (t_FmPortCongestionGrps*) compat_ptr(arg), -+ sizeof(t_FmPortCongestionGrps))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ else -+#endif /* CONFIG_COMPAT */ -+ { -+ if (copy_from_user(param, (t_FmPortCongestionGrps*) arg, -+ sizeof(t_FmPortCongestionGrps))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ err = (cmd == FM_PORT_IOC_ADD_CONGESTION_GRPS) -+ ? FM_PORT_AddCongestionGrps(p_LnxWrpFmPortDev->h_Dev, (t_FmPortCongestionGrps*) param) -+ : FM_PORT_RemoveCongestionGrps(p_LnxWrpFmPortDev->h_Dev, (t_FmPortCongestionGrps*) param) -+ ; -+ -+ XX_Free(param); -+ break; -+ } -+ -+ case FM_PORT_IOC_ADD_RX_HASH_MAC_ADDR: -+ case FM_PORT_IOC_REMOVE_RX_HASH_MAC_ADDR: -+ { -+ ioc_fm_port_mac_addr_params_t *param; -+ -+ param = (ioc_fm_port_mac_addr_params_t*) XX_Malloc( -+ sizeof(ioc_fm_port_mac_addr_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PORT")); -+ -+ memset(param, 0, sizeof(ioc_fm_port_mac_addr_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ if (copy_from_user(param, (ioc_fm_port_mac_addr_params_t*) compat_ptr(arg), -+ sizeof(ioc_fm_port_mac_addr_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ else -+#endif /* CONFIG_COMPAT */ -+ { -+ if (copy_from_user(param, (ioc_fm_port_mac_addr_params_t*) arg, -+ sizeof(ioc_fm_port_mac_addr_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ if (p_LnxWrpFmPortDev->pcd_owner_params.dev) -+ { -+ int id = -1; -+ -+ switch(p_LnxWrpFmPortDev->settings.param.portType) -+ { -+ case e_FM_PORT_TYPE_RX: -+ case e_FM_PORT_TYPE_TX: -+ id = p_LnxWrpFmPortDev->id; -+ break; -+ case e_FM_PORT_TYPE_RX_10G: -+ case e_FM_PORT_TYPE_TX_10G: -+ id = p_LnxWrpFmPortDev->id + FM_MAX_NUM_OF_1G_MACS; -+ break; -+ default: -+ err = E_NOT_AVAILABLE; -+ REPORT_ERROR(MINOR, err, ("Attempt to add/remove hash MAC addr. to/from MAC-less port!")); -+ } -+ if (id >= 0) -+ { -+ t_LnxWrpFmDev *fm = (t_LnxWrpFmDev *)p_LnxWrpFmPortDev->h_LnxWrpFmDev; -+ t_Handle mac_handle = fm->macs[id].h_Dev; -+ -+ err = (cmd == FM_PORT_IOC_ADD_RX_HASH_MAC_ADDR) -+ ? FM_MAC_AddHashMacAddr(mac_handle, (t_EnetAddr*) param) -+ : FM_MAC_RemoveHashMacAddr(mac_handle, (t_EnetAddr*) param); -+ } -+ } -+ else -+ { -+ err = E_NOT_AVAILABLE; -+ REPORT_ERROR(MINOR, err, ("Port not initialized or other error!?!?")); -+ } -+ -+ XX_Free(param); -+ break; -+ } -+ -+ case FM_PORT_IOC_SET_TX_PAUSE_FRAMES: -+ { -+ t_LnxWrpFmDev *p_LnxWrpFmDev = -+ (t_LnxWrpFmDev *)p_LnxWrpFmPortDev->h_LnxWrpFmDev; -+ ioc_fm_port_tx_pause_frames_params_t param; -+ int mac_id = p_LnxWrpFmPortDev->id; -+ -+ if(&p_LnxWrpFmDev->txPorts[mac_id] != p_LnxWrpFmPortDev) -+ mac_id += FM_MAX_NUM_OF_1G_MACS; /* 10G port */ -+ -+ if (copy_from_user(¶m, (ioc_fm_port_tx_pause_frames_params_t *)arg, -+ sizeof(ioc_fm_port_tx_pause_frames_params_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ if (p_LnxWrpFmDev && p_LnxWrpFmDev->macs[mac_id].h_Dev) -+ { -+ FM_MAC_SetTxPauseFrames(p_LnxWrpFmDev->macs[mac_id].h_Dev, -+ param.priority, -+ param.pause_time, -+ param.thresh_time); -+ } -+ else -+ { -+ err = E_NOT_AVAILABLE; -+ REPORT_ERROR(MINOR, err, ("Port not initialized or other error!")); -+ } -+ -+ break; -+ } -+ -+ case FM_PORT_IOC_CONFIG_BUFFER_PREFIX_CONTENT: -+ { -+ ioc_fm_buffer_prefix_content_t *param; -+ -+ param = (ioc_fm_buffer_prefix_content_t*) XX_Malloc(sizeof(ioc_fm_buffer_prefix_content_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PORT")); -+ -+ memset(param, 0, sizeof(ioc_fm_buffer_prefix_content_t)); -+ -+ if (copy_from_user(param, (ioc_fm_buffer_prefix_content_t*) arg, -+ sizeof(ioc_fm_buffer_prefix_content_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ if (FM_PORT_ConfigBufferPrefixContent(p_LnxWrpFmPortDev->h_Dev, -+ (t_FmBufferPrefixContent *)param)) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ XX_Free(param); -+ break; -+ } -+ -+#if (DPAA_VERSION >= 11) -+#if defined(CONFIG_COMPAT) -+ case FM_PORT_IOC_VSP_ALLOC_COMPAT: -+#endif -+ case FM_PORT_IOC_VSP_ALLOC: -+ { -+ ioc_fm_port_vsp_alloc_params_t *param; -+ t_LnxWrpFmDev *p_LnxWrpFmDev; -+ t_LnxWrpFmPortDev *p_LnxWrpFmTxPortDev; -+ -+ param = (ioc_fm_port_vsp_alloc_params_t *) XX_Malloc( -+ sizeof(ioc_fm_port_vsp_alloc_params_t)); -+ if (!param) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PORT")); -+ -+ memset(param, 0, sizeof(ioc_fm_port_vsp_alloc_params_t)); -+ -+#if defined(CONFIG_COMPAT) -+ if (compat) -+ { -+ ioc_compat_fm_port_vsp_alloc_params_t *compat_param; -+ -+ compat_param = (ioc_compat_fm_port_vsp_alloc_params_t *) XX_Malloc( -+ sizeof(ioc_compat_fm_port_vsp_alloc_params_t)); -+ if (!compat_param) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("IOCTL FM PORT")); -+ } -+ -+ memset(compat_param, 0, sizeof(ioc_compat_fm_port_vsp_alloc_params_t)); -+ if (copy_from_user(compat_param, -+ (ioc_compat_fm_port_vsp_alloc_params_t *) compat_ptr(arg), -+ sizeof(ioc_compat_fm_port_vsp_alloc_params_t))) -+ { -+ XX_Free(compat_param); -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ compat_copy_fm_port_vsp_alloc_params(compat_param, param, COMPAT_US_TO_K); -+ -+ XX_Free(compat_param); -+ } -+ else -+#endif -+ { -+ if (copy_from_user(param, (ioc_fm_port_vsp_alloc_params_t *)arg, -+ sizeof(ioc_fm_port_vsp_alloc_params_t))) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ } -+ -+ /* Userspace may not have the Tx port t_handle when issuing the IOCTL */ -+ if (p_LnxWrpFmPortDev->settings.param.portType == e_FM_PORT_TYPE_RX || -+ p_LnxWrpFmPortDev->settings.param.portType == e_FM_PORT_TYPE_RX_10G) -+ { -+ /* Determine the Tx port t_Handle from the Rx port id */ -+ p_LnxWrpFmDev = p_LnxWrpFmPortDev->h_LnxWrpFmDev; -+ p_LnxWrpFmTxPortDev = &p_LnxWrpFmDev->txPorts[p_LnxWrpFmPortDev->id]; -+ param->p_fm_tx_port = p_LnxWrpFmTxPortDev->h_Dev; -+ } -+ -+ if (FM_PORT_VSPAlloc(p_LnxWrpFmPortDev->h_Dev, (t_FmPortVSPAllocParams *)param)) -+ { -+ XX_Free(param); -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ } -+ -+ XX_Free(param); -+ break; -+ } -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ case FM_PORT_IOC_GET_MAC_STATISTICS: -+ { -+ t_LnxWrpFmDev *p_LnxWrpFmDev = -+ (t_LnxWrpFmDev *)p_LnxWrpFmPortDev->h_LnxWrpFmDev; -+ ioc_fm_port_mac_statistics_t param; -+ int mac_id = p_LnxWrpFmPortDev->id; -+ -+ if (!p_LnxWrpFmDev) -+ RETURN_ERROR(MINOR, E_NOT_AVAILABLE, ("Port not initialized or other error!")); -+ -+ if (&p_LnxWrpFmDev->txPorts[mac_id] != p_LnxWrpFmPortDev && -+ &p_LnxWrpFmDev->rxPorts[mac_id] != p_LnxWrpFmPortDev) -+ mac_id += FM_MAX_NUM_OF_1G_MACS; /* 10G port */ -+ -+ if (!p_LnxWrpFmDev->macs[mac_id].h_Dev) -+ RETURN_ERROR(MINOR, E_NOT_AVAILABLE, ("Port not initialized or other error!")); -+ -+ if (FM_MAC_GetStatistics(p_LnxWrpFmDev->macs[mac_id].h_Dev, -+ (t_FmMacStatistics *)¶m)) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ if (copy_to_user((ioc_fm_port_mac_statistics_t *)arg, ¶m, -+ sizeof(ioc_fm_port_mac_statistics_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ break; -+ } -+ -+ case FM_PORT_IOC_GET_BMI_COUNTERS: -+ { -+ t_LnxWrpFmDev *p_LnxWrpFmDev = -+ (t_LnxWrpFmDev *)p_LnxWrpFmPortDev->h_LnxWrpFmDev; -+ ioc_fm_port_bmi_stats_t param; -+ -+ if (!p_LnxWrpFmDev) -+ RETURN_ERROR(MINOR, E_NOT_AVAILABLE, ("Port not initialized or other error!")); -+ -+ if (FM_PORT_GetBmiCounters(p_LnxWrpFmPortDev->h_Dev, -+ (t_FmPortBmiStats *)¶m)) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ if (copy_to_user((ioc_fm_port_bmi_stats_t *)arg, ¶m, -+ sizeof(ioc_fm_port_bmi_stats_t))) -+ RETURN_ERROR(MINOR, E_WRITE_FAILED, NO_MSG); -+ -+ break; -+ } -+ -+ default: -+ RETURN_ERROR(MINOR, E_INVALID_SELECTION, -+ ("invalid ioctl: cmd:0x%08x(type:0x%02x, nr:0x%02x.\n", -+ cmd, _IOC_TYPE(cmd), _IOC_NR(cmd))); -+ } -+ -+ if (err) -+ RETURN_ERROR(MINOR, E_INVALID_OPERATION, ("IOCTL FM PORT")); -+ -+ return E_OK; -+} -+ -+/*****************************************************************************/ -+/* API routines for the FM Linux Device */ -+/*****************************************************************************/ -+ -+static int fm_open(struct inode *inode, struct file *file) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev = NULL; -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = NULL; -+ unsigned int major = imajor(inode); -+ unsigned int minor = iminor(inode); -+ struct device_node *fm_node; -+ static struct of_device_id fm_node_of_match[] = { -+ { .compatible = "fsl,fman", }, -+ { /* end of list */ }, -+ }; -+ -+ DBG(TRACE, ("Opening minor - %d - ", minor)); -+ -+ if (file->private_data != NULL) -+ return 0; -+ -+ /* Get all the FM nodes */ -+ for_each_matching_node(fm_node, fm_node_of_match) { -+ struct platform_device *of_dev; -+ -+ of_dev = of_find_device_by_node(fm_node); -+ if (unlikely(of_dev == NULL)) { -+ REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("fm id!")); -+ return -ENXIO; -+ } -+ -+ p_LnxWrpFmDev = (t_LnxWrpFmDev *)fm_bind(&of_dev->dev); -+ if (p_LnxWrpFmDev->major == major) -+ break; -+ fm_unbind((struct fm *)p_LnxWrpFmDev); -+ p_LnxWrpFmDev = NULL; -+ } -+ -+ if (!p_LnxWrpFmDev) -+ return -ENODEV; -+ -+ if (minor == DEV_FM_MINOR_BASE) -+ file->private_data = p_LnxWrpFmDev; -+ else if (minor == DEV_FM_PCD_MINOR_BASE) -+ file->private_data = p_LnxWrpFmDev; -+ else { -+ if (minor == DEV_FM_OH_PORTS_MINOR_BASE) -+ p_LnxWrpFmPortDev = &p_LnxWrpFmDev->hcPort; -+ else if ((minor > DEV_FM_OH_PORTS_MINOR_BASE) && (minor < DEV_FM_RX_PORTS_MINOR_BASE)) -+ p_LnxWrpFmPortDev = &p_LnxWrpFmDev->opPorts[minor-DEV_FM_OH_PORTS_MINOR_BASE-1]; -+ else if ((minor >= DEV_FM_RX_PORTS_MINOR_BASE) && (minor < DEV_FM_TX_PORTS_MINOR_BASE)) -+ p_LnxWrpFmPortDev = &p_LnxWrpFmDev->rxPorts[minor-DEV_FM_RX_PORTS_MINOR_BASE]; -+ else if ((minor >= DEV_FM_TX_PORTS_MINOR_BASE) && (minor < DEV_FM_MAX_MINORS)) -+ p_LnxWrpFmPortDev = &p_LnxWrpFmDev->txPorts[minor-DEV_FM_TX_PORTS_MINOR_BASE]; -+ else -+ return -EINVAL; -+ -+ /* if trying to open port, check if it initialized */ -+ if (!p_LnxWrpFmPortDev->h_Dev) -+ return -ENODEV; -+ -+ p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *)fm_port_bind(p_LnxWrpFmPortDev->dev); -+ file->private_data = p_LnxWrpFmPortDev; -+ fm_unbind((struct fm *)p_LnxWrpFmDev); -+ } -+ -+ if (file->private_data == NULL) -+ return -ENXIO; -+ -+ return 0; -+} -+ -+static int fm_close(struct inode *inode, struct file *file) -+{ -+ t_LnxWrpFmDev *p_LnxWrpFmDev; -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev; -+ unsigned int minor = iminor(inode); -+ int err = 0; -+ -+ DBG(TRACE, ("Closing minor - %d - ", minor)); -+ -+ if ((minor == DEV_FM_MINOR_BASE) || -+ (minor == DEV_FM_PCD_MINOR_BASE)) -+ { -+ p_LnxWrpFmDev = (t_LnxWrpFmDev*)file->private_data; -+ if (!p_LnxWrpFmDev) -+ return -ENODEV; -+ fm_unbind((struct fm *)p_LnxWrpFmDev); -+ } -+ else if (((minor >= DEV_FM_OH_PORTS_MINOR_BASE) && (minor < DEV_FM_RX_PORTS_MINOR_BASE)) || -+ ((minor >= DEV_FM_RX_PORTS_MINOR_BASE) && (minor < DEV_FM_TX_PORTS_MINOR_BASE)) || -+ ((minor >= DEV_FM_TX_PORTS_MINOR_BASE) && (minor < DEV_FM_MAX_MINORS))) -+ { -+ p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev*)file->private_data; -+ if (!p_LnxWrpFmPortDev) -+ return -ENODEV; -+ fm_port_unbind((struct fm_port *)p_LnxWrpFmPortDev); -+ } -+ -+ return err; -+} -+ -+static int fm_ioctls(unsigned int minor, struct file *file, unsigned int cmd, unsigned long arg, bool compat) -+{ -+ DBG(TRACE, ("IOCTL minor - %u, cmd - 0x%08x, arg - 0x%08lx \n", minor, cmd, arg)); -+ -+ if ((minor == DEV_FM_MINOR_BASE) || -+ (minor == DEV_FM_PCD_MINOR_BASE)) -+ { -+ t_LnxWrpFmDev *p_LnxWrpFmDev = ((t_LnxWrpFmDev*)file->private_data); -+ if (!p_LnxWrpFmDev) -+ return -ENODEV; -+ if (LnxwrpFmIOCTL(p_LnxWrpFmDev, cmd, arg, compat)) -+ return -EFAULT; -+ } -+ else if (((minor >= DEV_FM_OH_PORTS_MINOR_BASE) && (minor < DEV_FM_RX_PORTS_MINOR_BASE)) || -+ ((minor >= DEV_FM_RX_PORTS_MINOR_BASE) && (minor < DEV_FM_TX_PORTS_MINOR_BASE)) || -+ ((minor >= DEV_FM_TX_PORTS_MINOR_BASE) && (minor < DEV_FM_MAX_MINORS))) -+ { -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = ((t_LnxWrpFmPortDev*)file->private_data); -+ if (!p_LnxWrpFmPortDev) -+ return -ENODEV; -+ if (LnxwrpFmPortIOCTL(p_LnxWrpFmPortDev, cmd, arg, compat)) -+ return -EFAULT; -+ } -+ else -+ { -+ REPORT_ERROR(MINOR, E_INVALID_VALUE, ("minor")); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+#ifdef CONFIG_COMPAT -+static long fm_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ unsigned int minor = iminor(file->f_path.dentry->d_inode); -+ long res; -+ -+ fm_mutex_lock(); -+ res = fm_ioctls(minor, file, cmd, arg, true); -+ fm_mutex_unlock(); -+ -+ return res; -+} -+#endif -+ -+static long fm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ unsigned int minor = iminor(file->f_path.dentry->d_inode); -+ long res; -+ -+ fm_mutex_lock(); -+ res = fm_ioctls(minor, file, cmd, arg, false); -+ fm_mutex_unlock(); -+ -+ return res; -+} -+ -+/* Globals for FM character device */ -+struct file_operations fm_fops = -+{ -+ .owner = THIS_MODULE, -+ .unlocked_ioctl = fm_ioctl, -+#ifdef CONFIG_COMPAT -+ .compat_ioctl = fm_compat_ioctl, -+#endif -+ .open = fm_open, -+ .release = fm_close, -+}; ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_ioctls_fm_compat.c -@@ -0,0 +1,1300 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ @File lnxwrp_fm_compat_ioctls.c -+ -+ @Description FM PCD compat functions -+ -+*/ -+ -+#if !defined(CONFIG_COMPAT) -+#error "missing COMPAT layer..." -+#endif -+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#ifndef CONFIG_FMAN_ARM -+#include -+#endif -+ -+#include "part_ext.h" -+#include "fm_ioctls.h" -+#include "fm_pcd_ioctls.h" -+#include "fm_port_ioctls.h" -+#include "lnxwrp_ioctls_fm_compat.h" -+ -+#if defined(FM_COMPAT_DBG) -+static void hex_dump(void * p_addr, unsigned int size) -+{ -+ int i; -+ -+ for(i=0; i\n", p); -+ -+ if(!p) -+ return 0; -+ -+ for(k=1; k < COMPAT_PTR2ID_ARRAY_MAX; k++) -+ if(compat_ptr2id_array[k].ptr == NULL) -+ { -+ compat_ptr2id_array[k].ptr = p; -+ compat_ptr2id_array[k].node_type = node_type; -+ _fm_cpt_dbg(COMPAT_GENERIC, "0x%08x \n", k | COMPAT_PTR2ID_WATERMARK); -+ return k | COMPAT_PTR2ID_WATERMARK; -+ } -+ -+ printk(KERN_WARNING "FMan map list full! No more PCD space on kernel!\n"); -+ return 0; -+} -+EXPORT_SYMBOL(compat_add_ptr2id); -+ -+compat_uptr_t compat_get_ptr2id(void *p, enum fm_map_node_type node_type) -+{ -+ compat_uptr_t k; -+ -+ _fm_cpt_dbg(COMPAT_GENERIC, " (%p) get -> \n", p); -+ -+ for(k=1; k < COMPAT_PTR2ID_ARRAY_MAX; k++) -+ if(compat_ptr2id_array[k].ptr == p && -+ compat_ptr2id_array[k].node_type == node_type) { -+ -+ _fm_cpt_dbg(COMPAT_GENERIC, "0x%08x\n", k | COMPAT_PTR2ID_WATERMARK); -+ return k | COMPAT_PTR2ID_WATERMARK; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(compat_get_ptr2id); -+ -+void *compat_get_id2ptr(compat_uptr_t comp, enum fm_map_node_type node_type) -+{ -+ -+ _fm_cpt_dbg(COMPAT_GENERIC, " (0x%08x) get -> \n", comp); -+ -+ if((COMPAT_PTR2ID_WM_MASK & comp) != COMPAT_PTR2ID_WATERMARK) { -+ _fm_cpt_dbg(COMPAT_GENERIC, "Error, invalid watermark (0x%08x)!\n\n", comp); -+ dump_stack(); -+ return compat_ptr(comp); -+ } -+ -+ comp &= ~COMPAT_PTR2ID_WM_MASK; -+ -+ if(((0 < comp) && (comp < COMPAT_PTR2ID_ARRAY_MAX) && (compat_ptr2id_array[comp].ptr != NULL) -+ && compat_ptr2id_array[comp].node_type == node_type)) { -+ _fm_cpt_dbg(COMPAT_GENERIC, "%p\n", compat_ptr2id_array[comp].ptr); -+ return compat_ptr2id_array[comp].ptr; -+ } -+ return NULL; -+} -+EXPORT_SYMBOL(compat_get_id2ptr); -+/* } maping kernel pointers w/ UserSpace id's */ -+ -+void compat_obj_delete( -+ ioc_compat_fm_obj_t *compat_id, -+ ioc_fm_obj_t *id) -+{ -+ id->obj = compat_pcd_id2ptr(compat_id->obj); -+ compat_del_ptr2id(id->obj, FM_MAP_TYPE_PCD_NODE); -+} -+ -+static inline void compat_copy_fm_pcd_plcr_next_engine( -+ ioc_compat_fm_pcd_plcr_next_engine_params_u *compat_param, -+ ioc_fm_pcd_plcr_next_engine_params_u *param, -+ ioc_fm_pcd_engine next_engine, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ switch (next_engine) -+ { -+ case e_IOC_FM_PCD_PLCR: -+ if (compat == COMPAT_US_TO_K) -+ param->p_profile = compat_pcd_id2ptr(compat_param->p_profile); -+ else -+ compat_param->p_profile = compat_pcd_ptr2id(param->p_profile); -+ break; -+ case e_IOC_FM_PCD_KG: -+ if (compat == COMPAT_US_TO_K) -+ param->p_direct_scheme = compat_pcd_id2ptr(compat_param->p_direct_scheme); -+ else -+ compat_param->p_direct_scheme = compat_pcd_ptr2id(param->p_direct_scheme); -+ break; -+ default: -+ if (compat == COMPAT_US_TO_K) -+ param->action = compat_param->action; -+ else -+ compat_param->action = param->action; -+ break; -+ } -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+void compat_copy_fm_pcd_plcr_profile( -+ ioc_compat_fm_pcd_plcr_profile_params_t *compat_param, -+ ioc_fm_pcd_plcr_profile_params_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->modify = compat_param->modify; -+ -+ /* profile_select */ -+ if (!compat_param->modify) -+ { -+ param->profile_select.new_params.profile_type = -+ compat_param->profile_select.new_params.profile_type; -+ param->profile_select.new_params.p_fm_port = -+ compat_ptr(compat_param->profile_select.new_params.p_fm_port); -+ param->profile_select.new_params.relative_profile_id = -+ compat_param->profile_select.new_params.relative_profile_id; -+ } -+ else -+ param->profile_select.p_profile = -+ compat_pcd_id2ptr(compat_param->profile_select.p_profile); -+ -+ param->alg_selection = compat_param->alg_selection; -+ param->color_mode = compat_param->color_mode; -+ -+ /* both parameters in the union has the same size, so memcpy works */ -+ memcpy(¶m->color, &compat_param->color, sizeof(param->color)); -+ -+ memcpy(¶m->non_passthrough_alg_param, -+ &compat_param->non_passthrough_alg_param, -+ sizeof(ioc_fm_pcd_plcr_non_passthrough_alg_param_t)); -+ -+ param->next_engine_on_green = compat_param->next_engine_on_green; -+ param->next_engine_on_yellow = compat_param->next_engine_on_yellow; -+ param->next_engine_on_red = compat_param->next_engine_on_red; -+ -+ param->trap_profile_on_flow_A = compat_param->trap_profile_on_flow_A; -+ param->trap_profile_on_flow_B = compat_param->trap_profile_on_flow_B; -+ param->trap_profile_on_flow_C = compat_param->trap_profile_on_flow_C; -+ } -+ else -+ { -+ compat_param->modify = param->modify; -+ -+ /* profile_select */ -+ if (!param->modify) -+ { -+ compat_param->profile_select.new_params.profile_type = -+ param->profile_select.new_params.profile_type; -+ compat_param->profile_select.new_params.p_fm_port = -+ ptr_to_compat(param->profile_select.new_params.p_fm_port); -+ compat_param->profile_select.new_params.relative_profile_id = -+ param->profile_select.new_params.relative_profile_id; -+ } -+ else -+ compat_param->profile_select.p_profile = -+ compat_pcd_ptr2id(param->profile_select.p_profile); -+ -+ compat_param->alg_selection = param->alg_selection; -+ compat_param->color_mode = param->color_mode; -+ -+ /* both parameters in the union has the same size, so memcpy works */ -+ memcpy(&compat_param->color, ¶m->color, sizeof(compat_param->color)); -+ -+ memcpy(&compat_param->non_passthrough_alg_param, -+ ¶m->non_passthrough_alg_param, -+ sizeof(ioc_fm_pcd_plcr_non_passthrough_alg_param_t)); -+ -+ compat_param->next_engine_on_green = param->next_engine_on_green; -+ compat_param->next_engine_on_yellow = param->next_engine_on_yellow; -+ compat_param->next_engine_on_red = param->next_engine_on_red; -+ -+ compat_param->trap_profile_on_flow_A = param->trap_profile_on_flow_A; -+ compat_param->trap_profile_on_flow_B = param->trap_profile_on_flow_B; -+ compat_param->trap_profile_on_flow_C = param->trap_profile_on_flow_C; -+ -+ compat_param->id = compat_add_ptr2id(param->id, FM_MAP_TYPE_PCD_NODE); -+ } -+ -+ compat_copy_fm_pcd_plcr_next_engine(&compat_param->params_on_green, -+ ¶m->params_on_green, param->next_engine_on_green, compat); -+ -+ compat_copy_fm_pcd_plcr_next_engine(&compat_param->params_on_yellow, -+ ¶m->params_on_yellow, param->next_engine_on_yellow, compat); -+ -+ compat_copy_fm_pcd_plcr_next_engine(&compat_param->params_on_red, -+ ¶m->params_on_red, param->next_engine_on_red, compat); -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+static inline void compat_copy_fm_pcd_cc_next_kg( -+ ioc_compat_fm_pcd_cc_next_kg_params_t *compat_param, -+ ioc_fm_pcd_cc_next_kg_params_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->new_fqid = compat_param->new_fqid; -+ param->override_fqid = compat_param->override_fqid; -+#if DPAA_VERSION >= 11 -+ param->new_relative_storage_profile_id = compat_param->new_relative_storage_profile_id; -+#endif -+ param->p_direct_scheme = compat_pcd_id2ptr(compat_param->p_direct_scheme); -+ } -+ else -+ { -+ compat_param->new_fqid = param->new_fqid; -+ compat_param->override_fqid = param->override_fqid; -+#if DPAA_VERSION >= 11 -+ compat_param->new_relative_storage_profile_id = param->new_relative_storage_profile_id; -+#endif -+ compat_param->p_direct_scheme = compat_pcd_ptr2id(param->p_direct_scheme); -+ } -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+static inline void compat_copy_fm_pcd_cc_next_cc( -+ ioc_compat_fm_pcd_cc_next_cc_params_t *compat_param, -+ ioc_fm_pcd_cc_next_cc_params_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ param->cc_node_id = compat_pcd_id2ptr(compat_param->cc_node_id); -+ else -+ compat_param->cc_node_id = compat_pcd_ptr2id(param->cc_node_id); -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+static inline void compat_copy_fm_pcd_cc_next_engine( -+ ioc_compat_fm_pcd_cc_next_engine_params_t *compat_param, -+ ioc_fm_pcd_cc_next_engine_params_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->next_engine = compat_param->next_engine; -+ if (param->next_engine != e_IOC_FM_PCD_INVALID ) -+ _fm_cpt_dbg(compat, " param->next_engine = %i \n", param->next_engine); -+ -+ switch (param->next_engine) -+ { -+#if DPAA_VERSION >= 11 -+ case e_IOC_FM_PCD_FR: -+ param->params.fr_params.frm_replic_id = compat_pcd_id2ptr(compat_param->params.fr_params.frm_replic_id); -+ break; -+#endif /* DPAA_VERSION >= 11 */ -+ case e_IOC_FM_PCD_CC: -+ param->manip_id = compat_pcd_id2ptr(compat_param->manip_id); -+ compat_copy_fm_pcd_cc_next_cc(&compat_param->params.cc_params, ¶m->params.cc_params, compat); -+ break; -+ case e_IOC_FM_PCD_KG: -+ param->manip_id = compat_pcd_id2ptr(compat_param->manip_id); -+ compat_copy_fm_pcd_cc_next_kg(&compat_param->params.kg_params, ¶m->params.kg_params, compat); -+ break; -+ case e_IOC_FM_PCD_DONE: -+ case e_IOC_FM_PCD_PLCR: -+ param->manip_id = compat_pcd_id2ptr(compat_param->manip_id); -+ default: -+ memcpy(¶m->params, &compat_param->params, sizeof(param->params)); -+ } -+ param->statistics_en = compat_param->statistics_en; -+ } -+ else -+ { -+ compat_param->next_engine = param->next_engine; -+ -+ switch (compat_param->next_engine) -+ { -+#if DPAA_VERSION >= 11 -+ case e_IOC_FM_PCD_FR: -+ compat_param->params.fr_params.frm_replic_id = compat_pcd_ptr2id(param->params.fr_params.frm_replic_id); -+ break; -+#endif /* DPAA_VERSION >= 11 */ -+ case e_IOC_FM_PCD_CC: -+ compat_param->manip_id = compat_pcd_ptr2id(param->manip_id); -+ compat_copy_fm_pcd_cc_next_cc(&compat_param->params.cc_params, ¶m->params.cc_params, compat); -+ break; -+ case e_IOC_FM_PCD_KG: -+ compat_param->manip_id = compat_pcd_ptr2id(param->manip_id); -+ compat_copy_fm_pcd_cc_next_kg(&compat_param->params.kg_params, ¶m->params.kg_params, compat); -+ break; -+ case e_IOC_FM_PCD_DONE: -+ case e_IOC_FM_PCD_PLCR: -+ compat_param->manip_id = compat_pcd_ptr2id(param->manip_id); -+ default: -+ memcpy(&compat_param->params, ¶m->params, sizeof(compat_param->params)); -+ } -+ compat_param->statistics_en = param->statistics_en; -+ } -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+void compat_copy_fm_pcd_cc_key( -+ ioc_compat_fm_pcd_cc_key_params_t *compat_param, -+ ioc_fm_pcd_cc_key_params_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->p_key = compat_ptr(compat_param->p_key); -+ param->p_mask = compat_ptr(compat_param->p_mask); -+ } -+ else -+ { -+ compat_param->p_key = ptr_to_compat(param->p_key); -+ compat_param->p_mask = ptr_to_compat(param->p_mask); -+ } -+ -+ compat_copy_fm_pcd_cc_next_engine( -+ &compat_param->cc_next_engine_params, -+ ¶m->cc_next_engine_params, -+ compat); -+} -+ -+void compat_copy_fm_pcd_cc_node_modify_key_and_next_engine( -+ ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t *compat_param, -+ ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->id = compat_pcd_id2ptr(compat_param->id); -+ param->key_indx = compat_param->key_indx; -+ param->key_size = compat_param->key_size; -+ compat_copy_fm_pcd_cc_key( -+ &compat_param->key_params, -+ ¶m->key_params, -+ compat); -+ } -+ else -+ { -+ compat_param->id = compat_pcd_ptr2id(param->id); -+ compat_param->key_indx = param->key_indx; -+ compat_param->key_size = param->key_size; -+ compat_copy_fm_pcd_cc_key( -+ &compat_param->key_params, -+ ¶m->key_params, -+ compat); -+ } -+} -+ -+void compat_copy_fm_pcd_cc_node_modify_next_engine( -+ ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t *compat_param, -+ ioc_fm_pcd_cc_node_modify_next_engine_params_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->id = compat_pcd_id2ptr(compat_param->id); -+ param->key_indx = compat_param->key_indx; -+ param->key_size = compat_param->key_size; -+ } -+ else -+ { -+ compat_param->id = compat_pcd_ptr2id(param->id); -+ compat_param->key_indx = param->key_indx; -+ compat_param->key_size = param->key_size; -+ } -+ -+ compat_copy_fm_pcd_cc_next_engine( -+ &compat_param->cc_next_engine_params, -+ ¶m->cc_next_engine_params, -+ compat); -+} -+ -+void compat_fm_pcd_cc_tree_modify_next_engine( -+ ioc_compat_fm_pcd_cc_tree_modify_next_engine_params_t *compat_param, -+ ioc_fm_pcd_cc_tree_modify_next_engine_params_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->id = compat_pcd_id2ptr(compat_param->id); -+ param->grp_indx = compat_param->grp_indx; -+ param->indx = compat_param->indx; -+ } -+ else -+ { -+ compat_param->id = compat_pcd_ptr2id(param->id); -+ compat_param->grp_indx = param->grp_indx; -+ compat_param->indx = param->indx; -+ } -+ -+ compat_copy_fm_pcd_cc_next_engine( -+ &compat_param->cc_next_engine_params, -+ ¶m->cc_next_engine_params, -+ compat); -+} -+ -+void compat_copy_fm_pcd_hash_table( -+ ioc_compat_fm_pcd_hash_table_params_t *compat_param, -+ ioc_fm_pcd_hash_table_params_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->max_num_of_keys = compat_param->max_num_of_keys; -+ param->statistics_mode = compat_param->statistics_mode; -+ param->kg_hash_shift = compat_param->kg_hash_shift; -+ param->hash_res_mask = compat_param->hash_res_mask; -+ param->hash_shift = compat_param->hash_shift; -+ param->match_key_size = compat_param->match_key_size; -+ param->id = compat_pcd_id2ptr(compat_param->id); -+ } -+ else -+ { -+ compat_param->max_num_of_keys = param->max_num_of_keys; -+ compat_param->statistics_mode = param->statistics_mode; -+ compat_param->kg_hash_shift = param->kg_hash_shift; -+ compat_param->hash_res_mask = param->hash_res_mask; -+ compat_param->hash_shift = param->hash_shift; -+ compat_param->match_key_size = param->match_key_size; -+ -+ compat_param->id = compat_add_ptr2id(param->id, FM_MAP_TYPE_PCD_NODE); -+ } -+ -+ compat_copy_fm_pcd_cc_next_engine( -+ &compat_param->cc_next_engine_params_for_miss, -+ ¶m->cc_next_engine_params_for_miss, -+ compat); -+} -+ -+void compat_copy_fm_pcd_cc_grp( -+ ioc_compat_fm_pcd_cc_grp_params_t *compat_param, -+ ioc_fm_pcd_cc_grp_params_t *param, -+ uint8_t compat) -+{ -+ int k; -+ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->num_of_distinction_units = compat_param->num_of_distinction_units; -+ memcpy(param->unit_ids, compat_param->unit_ids, IOC_FM_PCD_MAX_NUM_OF_CC_UNITS); -+ } -+ else -+ { -+ compat_param->num_of_distinction_units = param->num_of_distinction_units; -+ memcpy(compat_param->unit_ids, param->unit_ids, IOC_FM_PCD_MAX_NUM_OF_CC_UNITS); -+ } -+ -+ for (k=0; k < IOC_FM_PCD_MAX_NUM_OF_CC_ENTRIES_IN_GRP; k++) -+ compat_copy_fm_pcd_cc_next_engine( -+ &compat_param->next_engine_per_entries_in_grp[k], -+ ¶m->next_engine_per_entries_in_grp[k], -+ compat); -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+void compat_copy_fm_pcd_cc_tree( -+ ioc_compat_fm_pcd_cc_tree_params_t *compat_param, -+ ioc_fm_pcd_cc_tree_params_t *param, -+ uint8_t compat) -+{ -+ int k; -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->net_env_id = compat_pcd_id2ptr(compat_param->net_env_id); -+ param->num_of_groups = compat_param->num_of_groups; -+ } -+ else -+ { -+ compat_param->net_env_id = compat_pcd_ptr2id(param->net_env_id); -+ compat_param->num_of_groups = param->num_of_groups; -+ -+ compat_param->id = compat_add_ptr2id(param->id, FM_MAP_TYPE_PCD_NODE); -+ } -+ -+ for (k=0; k < IOC_FM_PCD_MAX_NUM_OF_CC_GROUPS; k++) -+ compat_copy_fm_pcd_cc_grp( -+ &compat_param->fm_pcd_cc_group_params[k], -+ ¶m->fm_pcd_cc_group_params[k], -+ compat); -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+void compat_fm_pcd_prs_sw( -+ ioc_compat_fm_pcd_prs_sw_params_t *compat_param, -+ ioc_fm_pcd_prs_sw_params_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->override = compat_param->override; -+ param->size = compat_param->size; -+ param->base = compat_param->base; -+ param->p_code = compat_ptr(compat_param->p_code); -+ memcpy(param->sw_prs_data_params,compat_param->sw_prs_data_params,IOC_FM_PCD_PRS_NUM_OF_HDRS*sizeof(uint32_t)); -+ param->num_of_labels = compat_param->num_of_labels; -+ memcpy(param->labels_table,compat_param->labels_table,IOC_FM_PCD_PRS_NUM_OF_LABELS*sizeof(ioc_fm_pcd_prs_label_params_t)); -+ } -+} -+ -+void compat_copy_fm_pcd_kg_scheme( -+ ioc_compat_fm_pcd_kg_scheme_params_t *compat_param, -+ ioc_fm_pcd_kg_scheme_params_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg(compat," {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->modify = compat_param->modify; -+ -+ /* scm_id */ -+ if (compat_param->modify) -+ { -+ param->scm_id.scheme_id = compat_pcd_id2ptr(compat_param->scm_id.scheme_id); -+ _fm_cpt_dbg(compat," param->scm_id.scheme_id = %p \n", param->scm_id.scheme_id); -+ } -+ else -+ param->scm_id.relative_scheme_id = compat_param->scm_id.relative_scheme_id; -+ -+ param->always_direct = compat_param->always_direct; -+ /* net_env_params */ -+ param->net_env_params.net_env_id = compat_pcd_id2ptr(compat_param->net_env_params.net_env_id); -+ param->net_env_params.num_of_distinction_units = compat_param->net_env_params.num_of_distinction_units; -+ memcpy(param->net_env_params.unit_ids, -+ compat_param->net_env_params.unit_ids, -+ IOC_FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS); -+ -+ param->use_hash = compat_param->use_hash; -+ memcpy(¶m->key_extract_and_hash_params, -+ &compat_param->key_extract_and_hash_params, -+ sizeof(ioc_fm_pcd_kg_key_extract_and_hash_params_t)); -+ param->bypass_fqid_generation = compat_param->bypass_fqid_generation; -+ param->base_fqid = compat_param->base_fqid; -+#if DPAA_VERSION >= 11 -+ param->override_storage_profile = -+ compat_param->override_storage_profile; -+ param->storage_profile = compat_param->storage_profile; -+#endif -+ param->num_of_used_extracted_ors = compat_param->num_of_used_extracted_ors; -+ memcpy(param->extracted_ors, -+ compat_param->extracted_ors, -+ IOC_FM_PCD_KG_NUM_OF_GENERIC_REGS * sizeof(ioc_fm_pcd_kg_extracted_or_params_t)); -+ param->next_engine = compat_param->next_engine; -+ -+ /* kg_next_engine_params */ -+ if (param->next_engine == e_IOC_FM_PCD_CC) -+ { -+ param->kg_next_engine_params.cc.tree_id = compat_pcd_id2ptr(compat_param->kg_next_engine_params.cc.tree_id); -+ param->kg_next_engine_params.cc.grp_id = compat_param->kg_next_engine_params.cc.grp_id; -+ param->kg_next_engine_params.cc.plcr_next = compat_param->kg_next_engine_params.cc.plcr_next; -+ param->kg_next_engine_params.cc.bypass_plcr_profile_generation -+ = compat_param->kg_next_engine_params.cc.bypass_plcr_profile_generation; -+ memcpy(¶m->kg_next_engine_params.cc.plcr_profile, -+ &compat_param->kg_next_engine_params.cc.plcr_profile, -+ sizeof(ioc_fm_pcd_kg_plcr_profile_t)); -+ } -+ else -+ memcpy(¶m->kg_next_engine_params, -+ &compat_param->kg_next_engine_params, -+ sizeof(param->kg_next_engine_params)); -+ -+ memcpy(¶m->scheme_counter, -+ &compat_param->scheme_counter, -+ sizeof(ioc_fm_pcd_kg_scheme_counter_t)); -+ } -+ else -+ { -+ compat_param->modify = param->modify; -+ -+ /* scm_id */ -+ if (param->modify) -+ compat_param->scm_id.scheme_id = compat_pcd_ptr2id(param->scm_id.scheme_id); -+ else -+ compat_param->scm_id.relative_scheme_id = param->scm_id.relative_scheme_id; -+ -+ compat_param->always_direct = param->always_direct; -+ -+ /* net_env_params */ -+ compat_param->net_env_params.net_env_id = compat_pcd_ptr2id(param->net_env_params.net_env_id); -+ compat_param->net_env_params.num_of_distinction_units = param->net_env_params.num_of_distinction_units; -+ memcpy(compat_param->net_env_params.unit_ids, param->net_env_params.unit_ids, IOC_FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS); -+ -+ compat_param->use_hash = param->use_hash; -+ memcpy(&compat_param->key_extract_and_hash_params, ¶m->key_extract_and_hash_params, sizeof(ioc_fm_pcd_kg_key_extract_and_hash_params_t)); -+ compat_param->bypass_fqid_generation = param->bypass_fqid_generation; -+ compat_param->base_fqid = param->base_fqid; -+#if DPAA_VERSION >= 11 -+ compat_param->override_storage_profile = -+ param->override_storage_profile; -+ compat_param->storage_profile = param->storage_profile; -+#endif -+ compat_param->num_of_used_extracted_ors = param->num_of_used_extracted_ors; -+ memcpy(compat_param->extracted_ors, param->extracted_ors, IOC_FM_PCD_KG_NUM_OF_GENERIC_REGS * sizeof(ioc_fm_pcd_kg_extracted_or_params_t)); -+ compat_param->next_engine = param->next_engine; -+ -+ /* kg_next_engine_params */ -+ if (compat_param->next_engine == e_IOC_FM_PCD_CC) -+ { -+ compat_param->kg_next_engine_params.cc.tree_id = compat_pcd_ptr2id(param->kg_next_engine_params.cc.tree_id); -+ compat_param->kg_next_engine_params.cc.grp_id = param->kg_next_engine_params.cc.grp_id; -+ compat_param->kg_next_engine_params.cc.plcr_next = param->kg_next_engine_params.cc.plcr_next; -+ compat_param->kg_next_engine_params.cc.bypass_plcr_profile_generation -+ = param->kg_next_engine_params.cc.bypass_plcr_profile_generation; -+ memcpy(&compat_param->kg_next_engine_params.cc.plcr_profile, -+ ¶m->kg_next_engine_params.cc.plcr_profile, -+ sizeof(ioc_fm_pcd_kg_plcr_profile_t)); -+ } -+ else -+ memcpy(¶m->kg_next_engine_params, &compat_param->kg_next_engine_params, sizeof(compat_param->kg_next_engine_params)); -+ -+ memcpy(&compat_param->scheme_counter, ¶m->scheme_counter, sizeof(ioc_fm_pcd_kg_scheme_counter_t)); -+ -+ compat_param->id = compat_add_ptr2id(param->id, FM_MAP_TYPE_PCD_NODE); -+ } -+ -+ _fm_cpt_dbg(compat," ...->}\n"); -+} -+ -+void compat_copy_fm_pcd_kg_scheme_spc( -+ ioc_compat_fm_pcd_kg_scheme_spc_t *compat_param, -+ ioc_fm_pcd_kg_scheme_spc_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->id = compat_pcd_id2ptr(compat_param->id); -+ param->val = compat_param->val; -+ } else { -+ compat_param->id = compat_pcd_ptr2id(param->id); -+ compat_param->val = param->val; -+ } -+} -+ -+ -+void compat_copy_fm_pcd_kg_scheme_select( -+ ioc_compat_fm_pcd_kg_scheme_select_t *compat_param, -+ ioc_fm_pcd_kg_scheme_select_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->direct = compat_param->direct; -+ if (param->direct) -+ param->scheme_id = compat_pcd_id2ptr(compat_param->scheme_id); -+ } -+} -+ -+void compat_copy_fm_pcd_kg_schemes_params( -+ ioc_compat_fm_pcd_port_schemes_params_t *compat_param, -+ ioc_fm_pcd_port_schemes_params_t *param, -+ uint8_t compat) -+{ -+ int k; -+ -+ if (compat == COMPAT_US_TO_K) { -+ param->num_of_schemes = compat_param->num_of_schemes; -+ for(k=0; k < compat_param->num_of_schemes; k++) -+ param->scheme_ids[k] = compat_pcd_id2ptr(compat_param->scheme_ids[k]); -+ } -+} -+ -+void compat_copy_fm_port_pcd_cc( -+ ioc_compat_fm_port_pcd_cc_params_t *compat_cc_params , -+ ioc_fm_port_pcd_cc_params_t *p_cc_params, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K){ -+ p_cc_params->cc_tree_id = compat_pcd_id2ptr(compat_cc_params->cc_tree_id); -+ } -+} -+ -+void compat_copy_fm_port_pcd_kg( -+ ioc_compat_fm_port_pcd_kg_params_t *compat_param, -+ ioc_fm_port_pcd_kg_params_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K){ -+ uint8_t k; -+ -+ param->num_of_schemes = compat_param->num_of_schemes; -+ for(k=0; knum_of_schemes; k++) -+ param->scheme_ids[k] = compat_pcd_id2ptr(compat_param->scheme_ids[k]); -+ -+ param->direct_scheme = compat_param->direct_scheme; -+ if (param->direct_scheme) -+ param->direct_scheme_id = compat_pcd_id2ptr(compat_param->direct_scheme_id); -+ } -+} -+ -+void compat_copy_fm_port_pcd( -+ ioc_compat_fm_port_pcd_params_t *compat_param, -+ ioc_fm_port_pcd_params_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ { -+ ioc_fm_port_pcd_prs_params_t *same_port_pcd_prs_params; -+ ioc_compat_fm_port_pcd_cc_params_t *compat_port_pcd_cc_params; -+ ioc_compat_fm_port_pcd_kg_params_t *compat_port_pcd_kg_params; -+ ioc_compat_fm_port_pcd_plcr_params_t *compat_port_pcd_plcr_params; -+ -+ same_port_pcd_prs_params = (ioc_fm_port_pcd_prs_params_t *) (compat_param + 1); -+ compat_port_pcd_cc_params = (ioc_compat_fm_port_pcd_cc_params_t *) (same_port_pcd_prs_params + 1); -+ compat_port_pcd_kg_params = (ioc_compat_fm_port_pcd_kg_params_t *) (compat_port_pcd_cc_params + 1); -+ compat_port_pcd_plcr_params = (ioc_compat_fm_port_pcd_plcr_params_t *) (compat_port_pcd_kg_params + 1); -+ -+ _fm_cpt_dbg(compat,"\n param->p_prs_params=%p \n", param->p_prs_params); -+ _fm_cpt_dbg(compat," param->p_cc_params=%p \n", param->p_cc_params); -+ _fm_cpt_dbg(compat," param->p_kg_params=%p \n", param->p_kg_params); -+ _fm_cpt_dbg(compat," param->p_plcr_params=%p \n", param->p_plcr_params); -+ _fm_cpt_dbg(compat," param->p_ip_reassembly_manip=%p \n", param->p_ip_reassembly_manip); -+#if (DPAA_VERSION >= 11) -+ _fm_cpt_dbg(compat," param->p_capwap_reassembly_manip=%p \n", param->p_capwap_reassembly_manip); -+#endif -+ param->pcd_support = compat_param->pcd_support; -+ param->net_env_id = compat_pcd_id2ptr(compat_param->net_env_id); -+ -+ if (param->p_cc_params) -+ compat_copy_fm_port_pcd_cc(compat_port_pcd_cc_params, param->p_cc_params, COMPAT_US_TO_K); -+ if (param->p_kg_params) -+ compat_copy_fm_port_pcd_kg(compat_port_pcd_kg_params, param->p_kg_params, COMPAT_US_TO_K); -+ if (param->p_plcr_params) -+ param->p_plcr_params->plcr_profile_id = compat_pcd_id2ptr(compat_port_pcd_plcr_params->plcr_profile_id); -+ param->p_ip_reassembly_manip = compat_pcd_id2ptr(compat_param->p_ip_reassembly_manip); -+#if (DPAA_VERSION >= 11) -+ param->p_capwap_reassembly_manip = compat_pcd_id2ptr(compat_param->p_capwap_reassembly_manip); -+#endif -+ } -+} -+ -+void compat_copy_fm_port_pcd_modify_tree( -+ ioc_compat_fm_obj_t *compat_id, -+ ioc_fm_obj_t *id, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ id->obj = compat_pcd_id2ptr(compat_id->obj); -+} -+ -+#if (DPAA_VERSION >= 11) -+void compat_copy_fm_port_vsp_alloc_params( -+ ioc_compat_fm_port_vsp_alloc_params_t *compat_param, -+ ioc_fm_port_vsp_alloc_params_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ { -+ _fm_cpt_dbg(compat," param->p_fm_tx_port=%p \n", param->p_fm_tx_port); -+ -+ param->dflt_relative_id = compat_param->dflt_relative_id; -+ param->num_of_profiles = compat_param->num_of_profiles; -+ param->p_fm_tx_port = compat_pcd_id2ptr(compat_param->p_fm_tx_port); -+ } -+} -+#endif /* (DPAA_VERSION >= 11) */ -+ -+void compat_copy_fm_pcd_cc_tbl_get_stats( -+ ioc_compat_fm_pcd_cc_tbl_get_stats_t *compat_param, -+ ioc_fm_pcd_cc_tbl_get_stats_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->id = compat_pcd_id2ptr(compat_param->id); -+ param->key_index = compat_param->key_index; -+ memcpy(¶m->statistics, &compat_param->statistics, sizeof(ioc_fm_pcd_cc_key_statistics_t)); -+ } else { -+ compat_param->id = compat_add_ptr2id(param->id, FM_MAP_TYPE_PCD_NODE); -+ compat_param->key_index = param->key_index; -+ memcpy(&compat_param->statistics, ¶m->statistics, sizeof(ioc_fm_pcd_cc_key_statistics_t)); -+ } -+} -+ -+ -+void compat_copy_fm_pcd_net_env( -+ ioc_compat_fm_pcd_net_env_params_t *compat_param, -+ ioc_fm_pcd_net_env_params_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->num_of_distinction_units = compat_param->num_of_distinction_units; -+ memcpy(param->units, compat_param->units, sizeof(ioc_fm_pcd_distinction_unit_t)*IOC_FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS); -+ param->id = NULL; /* to avoid passing garbage to the kernel */ -+ } -+ else -+ { -+ compat_param->num_of_distinction_units = param->num_of_distinction_units; -+ memcpy(compat_param->units, param->units, sizeof(ioc_fm_pcd_distinction_unit_t)*IOC_FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS); -+ -+ compat_param->id = compat_add_ptr2id(param->id, FM_MAP_TYPE_PCD_NODE); -+ } -+} -+ -+void compat_copy_fm_pcd_cc_node_modify_key( -+ ioc_compat_fm_pcd_cc_node_modify_key_params_t *compat_param, -+ ioc_fm_pcd_cc_node_modify_key_params_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->key_indx = compat_param->key_indx; -+ param->key_size = compat_param->key_size; -+ param->p_key = (uint8_t *)compat_ptr(compat_param->p_key); -+ _fm_cpt_dbg(compat," param->p_key = %p \n", param->p_key); -+ param->p_mask = (uint8_t *)compat_ptr(compat_param->p_mask); -+ _fm_cpt_dbg(compat," param->p_mask = %p\n", param->p_mask); -+ param->id = compat_pcd_id2ptr(compat_param->id); -+ _fm_cpt_dbg(compat," param->id = %p \n", param->id); -+ } -+ else -+ { -+ compat_param->key_indx = param->key_indx; -+ compat_param->key_size = param->key_size; -+ compat_param->p_key = ptr_to_compat((void *)param->p_key); -+ compat_param->p_mask = ptr_to_compat((void *)param->p_mask); -+ -+ compat_param->id = compat_add_ptr2id(param->id, FM_MAP_TYPE_PCD_NODE); -+ } -+} -+ -+void compat_copy_keys( -+ ioc_compat_keys_params_t *compat_param, -+ ioc_keys_params_t *param, -+ uint8_t compat) -+{ -+ int k = 0; -+ -+ _fm_cpt_dbg(compat," {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) { -+ param->max_num_of_keys = compat_param->max_num_of_keys; -+ param->mask_support = compat_param->mask_support; -+ param->statistics_mode = compat_param->statistics_mode; -+ param->num_of_keys = compat_param->num_of_keys; -+ param->key_size = compat_param->key_size; -+#if (DPAA_VERSION >= 11) -+ memcpy(¶m->frame_length_ranges, -+ &compat_param->frame_length_ranges, -+ sizeof(param->frame_length_ranges[0]) * -+ IOC_FM_PCD_CC_STATS_MAX_NUM_OF_FLR); -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ else { -+ compat_param->max_num_of_keys = param->max_num_of_keys; -+ compat_param->mask_support = param->mask_support; -+ compat_param->statistics_mode = param->statistics_mode; -+ compat_param->num_of_keys = param->num_of_keys; -+ compat_param->key_size = param->key_size; -+#if (DPAA_VERSION >= 11) -+ memcpy(&compat_param->frame_length_ranges, -+ ¶m->frame_length_ranges, -+ sizeof(compat_param->frame_length_ranges[0]) * -+ IOC_FM_PCD_CC_STATS_MAX_NUM_OF_FLR); -+#endif /* (DPAA_VERSION >= 11) */ -+ } -+ -+ for (k=0; k < IOC_FM_PCD_MAX_NUM_OF_KEYS; k++) -+ compat_copy_fm_pcd_cc_key( -+ &compat_param->key_params[k], -+ ¶m->key_params[k], -+ compat); -+ -+ compat_copy_fm_pcd_cc_next_engine( -+ &compat_param->cc_next_engine_params_for_miss, -+ ¶m->cc_next_engine_params_for_miss, -+ compat); -+ -+ _fm_cpt_dbg(compat," ...->}\n"); -+} -+ -+void compat_copy_fm_pcd_cc_node( -+ ioc_compat_fm_pcd_cc_node_params_t *compat_param, -+ ioc_fm_pcd_cc_node_params_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg(compat," {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ memcpy(¶m->extract_cc_params, &compat_param->extract_cc_params, sizeof(ioc_fm_pcd_extract_entry_t)); -+ -+ else -+ { -+ compat_copy_keys(&compat_param->keys_params, ¶m->keys_params, compat); -+ -+ compat_param->id = compat_add_ptr2id(param->id, FM_MAP_TYPE_PCD_NODE); -+ _fm_cpt_dbg(compat," param->id = %p \n", param->id); -+ } -+ -+ compat_copy_keys(&compat_param->keys_params, ¶m->keys_params, compat); -+ -+ _fm_cpt_dbg(compat," ...->}\n"); -+} -+ -+void compat_fm_pcd_manip_set_node( -+ ioc_compat_fm_pcd_manip_params_t *compat_param, -+ ioc_fm_pcd_manip_params_t *param, -+ uint8_t compat) -+{ -+ if (compat == COMPAT_US_TO_K) { -+ param->type = compat_param->type; -+ switch (param->type) { -+ case e_IOC_FM_PCD_MANIP_HDR: -+ param->u.hdr.rmv = compat_param->u.hdr.rmv; -+ memcpy(¶m->u.hdr.rmv_params, -+ &compat_param->u.hdr.rmv_params, -+ sizeof(param->u.hdr.rmv_params)); -+ -+ param->u.hdr.insrt = compat_param->u.hdr.insrt; -+ param->u.hdr.insrt_params.type = -+ compat_param->u.hdr.insrt_params.type; -+ switch (compat_param->u.hdr.insrt_params.type) -+ { -+ case e_IOC_FM_PCD_MANIP_INSRT_GENERIC: -+ param->u.hdr.insrt_params.u.generic.offset = -+ compat_param->u.hdr.insrt_params.u.generic.offset; -+ param->u.hdr.insrt_params.u.generic.size = -+ compat_param->u.hdr.insrt_params.u.generic.size; -+ param->u.hdr.insrt_params.u.generic.replace = -+ compat_param->u.hdr.insrt_params.u.generic.replace; -+ param->u.hdr.insrt_params.u.generic.p_data = -+ compat_ptr(compat_param->u.hdr.insrt_params.u.generic.p_data); -+ break; -+ case e_IOC_FM_PCD_MANIP_INSRT_BY_HDR: -+ param->u.hdr.insrt_params.u.by_hdr.type = -+ compat_param->u.hdr.insrt_params.u.by_hdr.type; -+ param->u.hdr.insrt_params.u.by_hdr.u.specific_l2_params.specific_l2 = -+ compat_param->u.hdr.insrt_params.u.by_hdr.u.specific_l2_params.specific_l2; -+ param->u.hdr.insrt_params.u.by_hdr.u.specific_l2_params.update = -+ compat_param->u.hdr.insrt_params.u.by_hdr.u.specific_l2_params.update; -+ param->u.hdr.insrt_params.u.by_hdr.u.specific_l2_params.size = -+ compat_param->u.hdr.insrt_params.u.by_hdr.u.specific_l2_params.size; -+ param->u.hdr.insrt_params.u.by_hdr.u.specific_l2_params.p_data = -+ compat_ptr(compat_param->u.hdr.insrt_params.u.by_hdr.u.specific_l2_params.p_data); -+ break; -+ default: -+ _fm_cpt_err("Unsupported type: %d", compat_param->u.hdr.insrt_params.type); -+ } -+ -+ param->u.hdr.field_update = compat_param->u.hdr.field_update; -+ memcpy(¶m->u.hdr.field_update_params, -+ &compat_param->u.hdr.field_update_params, -+ sizeof(param->u.hdr.field_update_params)); -+ -+ param->u.hdr.custom = compat_param->u.hdr.custom; -+ memcpy(¶m->u.hdr.custom_params, -+ &compat_param->u.hdr.custom_params, -+ sizeof(param->u.hdr.custom_params)); -+ -+ param->u.hdr.dont_parse_after_manip = -+ compat_param->u.hdr.dont_parse_after_manip; -+ break; -+ case e_IOC_FM_PCD_MANIP_REASSEM: -+ memcpy(¶m->u.reassem, &compat_param->u.reassem, sizeof(param->u.reassem)); -+ break; -+ case e_IOC_FM_PCD_MANIP_FRAG: -+ memcpy(¶m->u.frag, &compat_param->u.frag, sizeof(param->u.frag)); -+ break; -+ case e_IOC_FM_PCD_MANIP_SPECIAL_OFFLOAD: -+ memcpy(¶m->u.special_offload, -+ &compat_param->u.special_offload, -+ sizeof(param->u.special_offload)); -+ break; -+ } -+ -+ param->p_next_manip = compat_pcd_id2ptr(compat_param->p_next_manip); -+ param->id = compat_pcd_id2ptr(compat_param->id); -+ } -+ else { -+ compat_param->type = param->type; -+ memcpy(&compat_param->u, ¶m->u, sizeof(compat_param->u)); -+ -+ if (param->type == e_IOC_FM_PCD_MANIP_HDR && -+ param->u.hdr.insrt_params.type == e_IOC_FM_PCD_MANIP_INSRT_GENERIC) -+ compat_param->u.hdr.insrt_params.u.generic.p_data = -+ ptr_to_compat(param->u.hdr.insrt_params.u.generic.p_data); -+ -+ compat_param->p_next_manip = compat_pcd_ptr2id(param->id); -+ /* ... should be one that was added previously by the very call to -+ compat_add_ptr2id() below: */ -+ compat_param->id = compat_add_ptr2id(param->id, FM_MAP_TYPE_PCD_NODE); -+ } -+} -+ -+void compat_copy_fm_pcd_manip_get_stats( -+ ioc_compat_fm_pcd_manip_get_stats_t *compat_param, -+ ioc_fm_pcd_manip_get_stats_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->id = compat_pcd_id2ptr(compat_param->id); -+ memcpy(¶m->stats, &compat_param->stats, -+ sizeof(ioc_fm_pcd_manip_stats_t)); -+ } -+ else -+ { -+ compat_param->id = compat_add_ptr2id(param->id, -+ FM_MAP_TYPE_PCD_NODE); -+ memcpy(&compat_param->stats, ¶m->stats, -+ sizeof(ioc_fm_pcd_manip_stats_t)); -+ } -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+#if (DPAA_VERSION >= 11) -+void compat_copy_fm_pcd_frm_replic_group_params( -+ ioc_compat_fm_pcd_frm_replic_group_params_t *compat_param, -+ ioc_fm_pcd_frm_replic_group_params_t *param, -+ uint8_t compat) -+{ -+ int k; -+ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->max_num_of_entries = compat_param->max_num_of_entries; -+ param->num_of_entries = compat_param->num_of_entries; -+ param->id = compat_pcd_id2ptr(compat_param->id); -+ } -+ else -+ { -+ compat_param->max_num_of_entries = param->max_num_of_entries; -+ compat_param->num_of_entries = param->num_of_entries; -+ compat_param->id = compat_add_ptr2id(param->id, -+ FM_MAP_TYPE_PCD_NODE); -+ } -+ -+ for (k=0; k < IOC_FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES; k++) -+ compat_copy_fm_pcd_cc_next_engine( -+ &compat_param->next_engine_params[k], -+ ¶m->next_engine_params[k], -+ compat); -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+void compat_copy_fm_pcd_frm_replic_member( -+ ioc_compat_fm_pcd_frm_replic_member_t *compat_param, -+ ioc_fm_pcd_frm_replic_member_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->h_replic_group = compat_pcd_id2ptr(compat_param->h_replic_group); -+ param->member_index = compat_param->member_index; -+ } -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+void compat_copy_fm_pcd_frm_replic_member_params( -+ ioc_compat_fm_pcd_frm_replic_member_params_t *compat_param, -+ ioc_fm_pcd_frm_replic_member_params_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ compat_copy_fm_pcd_frm_replic_member(&compat_param->member, -+ ¶m->member, compat); -+ -+ compat_copy_fm_pcd_cc_next_engine(&compat_param->next_engine_params, -+ ¶m->next_engine_params, compat); -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+void compat_copy_fm_vsp_params( -+ ioc_compat_fm_vsp_params_t *compat_param, -+ ioc_fm_vsp_params_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->p_fm = compat_pcd_id2ptr(compat_param->p_fm); -+ memcpy(¶m->ext_buf_pools, &compat_param->ext_buf_pools, sizeof(ioc_fm_ext_pools)); -+ param->liodn_offset = compat_param->liodn_offset; -+ param->port_params.port_id = compat_param->port_params.port_id; -+ param->port_params.port_type = compat_param->port_params.port_type; -+ param->relative_profile_id = compat_param->relative_profile_id; -+ param->id = compat_pcd_id2ptr(compat_param->id); -+ } -+ else -+ { -+ compat_param->p_fm = compat_pcd_ptr2id(param->p_fm); -+ memcpy(&compat_param->ext_buf_pools, ¶m->ext_buf_pools, sizeof(ioc_fm_ext_pools)); -+ compat_param->liodn_offset = param->liodn_offset; -+ compat_param->port_params.port_id = param->port_params.port_id; -+ compat_param->port_params.port_type = param->port_params.port_type; -+ compat_param->relative_profile_id = param->relative_profile_id; -+ compat_param->id = compat_add_ptr2id(param->id, FM_MAP_TYPE_PCD_NODE); -+ } -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+void compat_copy_fm_buf_pool_depletion_params( -+ ioc_compat_fm_buf_pool_depletion_params_t *compat_param, -+ ioc_fm_buf_pool_depletion_params_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->p_fm_vsp = compat_pcd_id2ptr(compat_param->p_fm_vsp); -+ memcpy(¶m->fm_buf_pool_depletion, -+ &compat_param->fm_buf_pool_depletion, -+ sizeof(ioc_fm_buf_pool_depletion_t)); -+ } -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+void compat_copy_fm_buffer_prefix_content_params( -+ ioc_compat_fm_buffer_prefix_content_params_t *compat_param, -+ ioc_fm_buffer_prefix_content_params_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->p_fm_vsp = compat_pcd_id2ptr(compat_param->p_fm_vsp); -+ memcpy(¶m->fm_buffer_prefix_content, -+ &compat_param->fm_buffer_prefix_content, -+ sizeof(ioc_fm_buffer_prefix_content_t)); -+ } -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+void compat_copy_fm_vsp_config_no_sg_params( -+ ioc_compat_fm_vsp_config_no_sg_params_t *compat_param, -+ ioc_fm_vsp_config_no_sg_params_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->p_fm_vsp = compat_pcd_id2ptr(compat_param->p_fm_vsp); -+ param->no_sg = compat_param->no_sg; -+ } -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+ -+void compat_copy_fm_vsp_prs_result_params( -+ ioc_compat_fm_vsp_prs_result_params_t *compat_param, -+ ioc_fm_vsp_prs_result_params_t *param, -+ uint8_t compat) -+{ -+ _fm_cpt_dbg (compat, " {->...\n"); -+ -+ if (compat == COMPAT_US_TO_K) -+ { -+ param->p_fm_vsp = compat_pcd_id2ptr(compat_param->p_fm_vsp); -+ /* p_data is an user-space pointer that needs to remain unmodified */ -+ param->p_data = (void *)(unsigned long long)compat_param->p_data; -+ } -+ else -+ { -+ compat_param->p_fm_vsp = compat_pcd_ptr2id(param->p_fm_vsp); -+ /* p_data is an user-space pointer that needs to remain unmodified */ -+ compat_param->p_data = (compat_uptr_t)((unsigned long long)param->p_data & 0xFFFFFFFF); -+ } -+ -+ _fm_cpt_dbg (compat, " ...->}\n"); -+} -+#endif /* (DPAA_VERSION >= 11) */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_ioctls_fm_compat.h -@@ -0,0 +1,755 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ @File lnxwrp_ioctls_fm_compat.h -+ -+ @Description FM PCD compat structures definition. -+ -+*/ -+ -+#ifndef __FM_COMPAT_IOCTLS_H -+#define __FM_COMPAT_IOCTLS_H -+ -+#include -+ -+#define COMPAT_K_TO_US 0 /* copy from Kernel to User */ -+#define COMPAT_US_TO_K 1 /* copy from User to Kernel */ -+#define COMPAT_GENERIC 2 -+ -+#define COMPAT_COPY_K2US(dest, src, type) compat_copy_##type(src, dest, 0) -+#define COMPAT_COPY_US2K(dest, src, type) compat_copy_##type(dest, src, 1) -+ -+/* mapping kernel pointers w/ UserSpace id's { */ -+/* Because compat_ptr(ptr_to_compat(X)) != X, this way we cannot exchange pointers -+ back and forth (US - KS). compat_ptr is a cast and pointers are broken. */ -+#define COMPAT_PTR2ID_ARRAY_MAX (512+1) /* first location is not used */ -+#define COMPAT_PTR2ID_WATERMARK 0xface0000 -+#define COMPAT_PTR2ID_WM_MASK 0xffff0000 -+ -+/* define it for debug trace */ -+/*#define FM_COMPAT_DBG*/ -+ -+#define _fm_cpt_prk(stage, format, arg...) \ -+ printk(stage "fm_cpt (cpu:%u): " format, raw_smp_processor_id(), ##arg) -+ -+#define _fm_cpt_inf(format, arg...) _fm_cpt_prk(KERN_INFO, format, ##arg) -+#define _fm_cpt_wrn(format, arg...) _fm_cpt_prk(KERN_WARNING, format, ##arg) -+#define _fm_cpt_err(format, arg...) _fm_cpt_prk(KERN_ERR, format, ##arg) -+ -+/* used for compat IOCTL debugging */ -+#if defined(FM_COMPAT_DBG) -+ #define _fm_cpt_dbg(from, format, arg...) \ -+ do{ \ -+ if (from == COMPAT_US_TO_K) \ -+ printk("fm_cpt to KS [%s:%u](cpu:%u) - " format, \ -+ __func__, __LINE__, raw_smp_processor_id(), ##arg); \ -+ else if (from == COMPAT_K_TO_US) \ -+ printk("fm_cpt to US [%s:%u](cpu:%u) - " format, \ -+ __func__, __LINE__, raw_smp_processor_id(), ##arg); \ -+ else \ -+ printk("fm_cpt [%s:%u](cpu:%u) - " format, \ -+ __func__, __LINE__, raw_smp_processor_id(), ##arg); \ -+ }while(0) -+#else -+# define _fm_cpt_dbg(arg...) -+#endif -+ -+/*TODO: per FMan module: -+ * -+ * Parser: FM_MAP_TYPE_PARSER_NODE, -+ * Kg: FM_MAP_TYPE_KG_NODE, -+ * Policer: FM_MAP_TYPE_POLICER_NODE -+ * Manip: FM_MAP_TYPE_MANIP_NODE -+ **/ -+enum fm_map_node_type { -+ FM_MAP_TYPE_UNSPEC = 0, -+ FM_MAP_TYPE_PCD_NODE, -+ -+ /* add types here, update the policy */ -+ -+ __FM_MAP_TYPE_AFTER_LAST, -+ FM_MAP_TYPE_MAX = __FM_MAP_TYPE_AFTER_LAST - 1 -+}; -+ -+void compat_del_ptr2id(void *p, enum fm_map_node_type); -+compat_uptr_t compat_add_ptr2id(void *p, enum fm_map_node_type); -+compat_uptr_t compat_get_ptr2id(void *p, enum fm_map_node_type); -+void *compat_get_id2ptr(compat_uptr_t comp, enum fm_map_node_type); -+ -+static inline compat_uptr_t compat_pcd_ptr2id(void *ptr) { -+ return (ptr)? compat_get_ptr2id(ptr, FM_MAP_TYPE_PCD_NODE) -+ : (compat_uptr_t) 0; -+} -+ -+static inline void *compat_pcd_id2ptr(compat_uptr_t id) { -+ return (id) ? compat_get_id2ptr(id, FM_MAP_TYPE_PCD_NODE) -+ : NULL; -+} -+ -+/* other similar inlines may be added as new nodes are added -+ to enum fm_map_node_type above... */ -+/* } mapping kernel pointers w/ UserSpace id's */ -+ -+/* pcd compat structures { */ -+typedef struct ioc_compat_fm_pcd_cc_node_remove_key_params_t { -+ compat_uptr_t id; -+ uint16_t key_indx; -+} ioc_compat_fm_pcd_cc_node_remove_key_params_t; -+ -+typedef union ioc_compat_fm_pcd_plcr_next_engine_params_u { -+ ioc_fm_pcd_done_action action; -+ compat_uptr_t p_profile; -+ compat_uptr_t p_direct_scheme; -+} ioc_compat_fm_pcd_plcr_next_engine_params_u; -+ -+typedef struct ioc_compat_fm_pcd_plcr_profile_params_t { -+ bool modify; -+ union { -+ struct { -+ ioc_fm_pcd_profile_type_selection profile_type; -+ compat_uptr_t p_fm_port; -+ uint16_t relative_profile_id; -+ } new_params; -+ compat_uptr_t p_profile; -+ } profile_select; -+ ioc_fm_pcd_plcr_algorithm_selection alg_selection; -+ ioc_fm_pcd_plcr_color_mode color_mode; -+ -+ union { -+ ioc_fm_pcd_plcr_color dflt_color; -+ ioc_fm_pcd_plcr_color override; -+ } color; -+ -+ ioc_fm_pcd_plcr_non_passthrough_alg_param_t non_passthrough_alg_param; -+ -+ ioc_fm_pcd_engine next_engine_on_green; -+ ioc_compat_fm_pcd_plcr_next_engine_params_u params_on_green; -+ -+ ioc_fm_pcd_engine next_engine_on_yellow; -+ ioc_compat_fm_pcd_plcr_next_engine_params_u params_on_yellow; -+ -+ ioc_fm_pcd_engine next_engine_on_red; -+ ioc_compat_fm_pcd_plcr_next_engine_params_u params_on_red; -+ -+ bool trap_profile_on_flow_A; -+ bool trap_profile_on_flow_B; -+ bool trap_profile_on_flow_C; -+ compat_uptr_t id; -+} ioc_compat_fm_pcd_plcr_profile_params_t; -+ -+typedef struct ioc_compat_fm_obj_t { -+ compat_uptr_t obj; -+} ioc_compat_fm_obj_t; -+ -+typedef struct ioc_compat_fm_pcd_kg_scheme_select_t { -+ bool direct; -+ compat_uptr_t scheme_id; -+} ioc_compat_fm_pcd_kg_scheme_select_t; -+ -+typedef struct ioc_compat_fm_pcd_port_schemes_params_t { -+ uint8_t num_of_schemes; -+ compat_uptr_t scheme_ids[FM_PCD_KG_NUM_OF_SCHEMES]; -+} ioc_compat_fm_pcd_port_schemes_params_t; -+ -+#if (DPAA_VERSION >= 11) -+typedef struct ioc_compat_fm_port_vsp_alloc_params_t { -+ uint8_t num_of_profiles; /**< Number of Virtual Storage Profiles */ -+ uint8_t dflt_relative_id; /**< The default Virtual-Storage-Profile-id dedicated to Rx/OP port -+ The same default Virtual-Storage-Profile-id will be for coupled Tx port -+ if relevant function called for Rx port */ -+ compat_uptr_t p_fm_tx_port; /**< Handle to coupled Tx Port; not relevant for OP port. */ -+}ioc_compat_fm_port_vsp_alloc_params_t; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+typedef struct ioc_compat_fm_pcd_net_env_params_t { -+ uint8_t num_of_distinction_units; -+ ioc_fm_pcd_distinction_unit_t units[IOC_FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; /* same structure*/ -+ compat_uptr_t id; -+} ioc_compat_fm_pcd_net_env_params_t; -+ -+typedef struct ioc_compat_fm_pcd_prs_sw_params_t { -+ bool override; -+ uint32_t size; -+ uint16_t base; -+ compat_uptr_t p_code; -+ uint32_t sw_prs_data_params[IOC_FM_PCD_PRS_NUM_OF_HDRS]; -+ uint8_t num_of_labels; -+ ioc_fm_pcd_prs_label_params_t labels_table[IOC_FM_PCD_PRS_NUM_OF_LABELS]; -+} ioc_compat_fm_pcd_prs_sw_params_t; -+ -+typedef struct ioc_compat_fm_pcd_cc_next_kg_params_t { -+ bool override_fqid; -+ uint32_t new_fqid; -+#if DPAA_VERSION >= 11 -+ uint8_t new_relative_storage_profile_id; -+#endif -+ compat_uptr_t p_direct_scheme; -+} ioc_compat_fm_pcd_cc_next_kg_params_t; -+ -+typedef struct ioc_compat_fm_pcd_cc_next_cc_params_t { -+ compat_uptr_t cc_node_id; -+} ioc_compat_fm_pcd_cc_next_cc_params_t; -+ -+#if DPAA_VERSION >= 11 -+typedef struct ioc_compat_fm_pcd_cc_next_fr_params_t { -+ compat_uptr_t frm_replic_id; -+} ioc_compat_fm_pcd_cc_next_fr_params_t; -+#endif /* DPAA_VERSION >= 11 */ -+ -+typedef struct ioc_compat_fm_pcd_cc_next_engine_params_t { -+ ioc_fm_pcd_engine next_engine; -+ union { -+ ioc_compat_fm_pcd_cc_next_cc_params_t cc_params; /**< compat structure*/ -+ ioc_fm_pcd_cc_next_plcr_params_t plcr_params; /**< same structure*/ -+ ioc_fm_pcd_cc_next_enqueue_params_t enqueue_params; /**< same structure*/ -+ ioc_compat_fm_pcd_cc_next_kg_params_t kg_params; /**< compat structure*/ -+#if DPAA_VERSION >= 11 -+ ioc_compat_fm_pcd_cc_next_fr_params_t fr_params; /**< compat structure*/ -+#endif /* DPAA_VERSION >= 11 */ -+ } params; -+ compat_uptr_t manip_id; -+ bool statistics_en; -+} ioc_compat_fm_pcd_cc_next_engine_params_t; -+ -+typedef struct ioc_compat_fm_pcd_cc_grp_params_t { -+ uint8_t num_of_distinction_units; -+ uint8_t unit_ids [IOC_FM_PCD_MAX_NUM_OF_CC_UNITS]; -+ ioc_compat_fm_pcd_cc_next_engine_params_t next_engine_per_entries_in_grp[IOC_FM_PCD_MAX_NUM_OF_CC_ENTRIES_IN_GRP]; -+} ioc_compat_fm_pcd_cc_grp_params_t; -+ -+typedef struct ioc_compat_fm_pcd_cc_tree_params_t { -+ compat_uptr_t net_env_id; -+ uint8_t num_of_groups; -+ ioc_compat_fm_pcd_cc_grp_params_t fm_pcd_cc_group_params [IOC_FM_PCD_MAX_NUM_OF_CC_GROUPS]; -+ compat_uptr_t id; -+} ioc_compat_fm_pcd_cc_tree_params_t; -+ -+typedef struct ioc_compat_fm_pcd_cc_tree_modify_next_engine_params_t { -+ compat_uptr_t id; -+ uint8_t grp_indx; -+ uint8_t indx; -+ ioc_compat_fm_pcd_cc_next_engine_params_t cc_next_engine_params; -+} ioc_compat_fm_pcd_cc_tree_modify_next_engine_params_t; -+ -+typedef struct ioc_compat_fm_pcd_cc_key_params_t { -+ compat_uptr_t p_key; -+ compat_uptr_t p_mask; -+ ioc_compat_fm_pcd_cc_next_engine_params_t cc_next_engine_params; /**< compat structure*/ -+} ioc_compat_fm_pcd_cc_key_params_t; -+ -+typedef struct ioc_compat_keys_params_t { -+ uint16_t max_num_of_keys; -+ bool mask_support; -+ ioc_fm_pcd_cc_stats_mode statistics_mode; -+#if (DPAA_VERSION >= 11) -+ uint16_t frame_length_ranges[IOC_FM_PCD_CC_STATS_MAX_NUM_OF_FLR]; -+#endif /* (DPAA_VERSION >= 11) */ -+ uint16_t num_of_keys; -+ uint8_t key_size; -+ ioc_compat_fm_pcd_cc_key_params_t key_params[IOC_FM_PCD_MAX_NUM_OF_KEYS]; /**< compat structure*/ -+ ioc_compat_fm_pcd_cc_next_engine_params_t cc_next_engine_params_for_miss; /**< compat structure*/ -+} ioc_compat_keys_params_t; -+ -+typedef struct ioc_compat_fm_pcd_cc_node_params_t { -+ ioc_fm_pcd_extract_entry_t extract_cc_params; /**< same structure*/ -+ ioc_compat_keys_params_t keys_params; /**< compat structure*/ -+ compat_uptr_t id; -+} ioc_compat_fm_pcd_cc_node_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a hash table -+*//***************************************************************************/ -+typedef struct ioc_compat_fm_pcd_hash_table_params_t { -+ uint16_t max_num_of_keys; -+ ioc_fm_pcd_cc_stats_mode statistics_mode; -+ uint8_t kg_hash_shift; -+ uint16_t hash_res_mask; -+ uint8_t hash_shift; -+ uint8_t match_key_size; -+ ioc_compat_fm_pcd_cc_next_engine_params_t cc_next_engine_params_for_miss; -+ compat_uptr_t id; -+} ioc_compat_fm_pcd_hash_table_params_t; -+ -+typedef struct ioc_compat_fm_pcd_hash_table_add_key_params_t { -+ compat_uptr_t p_hash_tbl; -+ uint8_t key_size; -+ ioc_compat_fm_pcd_cc_key_params_t key_params; -+} ioc_compat_fm_pcd_hash_table_add_key_params_t; -+ -+typedef struct ioc_compat_fm_pcd_cc_node_modify_key_params_t { -+ compat_uptr_t id; -+ uint16_t key_indx; -+ uint8_t key_size; -+ compat_uptr_t p_key; -+ compat_uptr_t p_mask; -+} ioc_compat_fm_pcd_cc_node_modify_key_params_t; -+ -+typedef struct ioc_compat_fm_pcd_hash_table_remove_key_params_t { -+ compat_uptr_t p_hash_tbl; -+ uint8_t key_size; -+ compat_uptr_t p_key; -+} ioc_compat_fm_pcd_hash_table_remove_key_params_t; -+ -+typedef struct ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t { -+ compat_uptr_t id; -+ uint16_t key_indx; -+ uint8_t key_size; -+ ioc_compat_fm_pcd_cc_key_params_t key_params; -+} ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t; -+ -+typedef struct ioc_compat_fm_port_pcd_plcr_params_t { -+ compat_uptr_t plcr_profile_id; -+} ioc_compat_fm_port_pcd_plcr_params_t; -+ -+typedef struct ioc_compat_fm_port_pcd_cc_params_t { -+ compat_uptr_t cc_tree_id; -+} ioc_compat_fm_port_pcd_cc_params_t; -+ -+typedef struct ioc_compat_fm_port_pcd_kg_params_t { -+ uint8_t num_of_schemes; -+ compat_uptr_t scheme_ids[FM_PCD_KG_NUM_OF_SCHEMES]; -+ bool direct_scheme; -+ compat_uptr_t direct_scheme_id; -+} ioc_compat_fm_port_pcd_kg_params_t; -+ -+typedef struct ioc_compat_fm_port_pcd_params_t { -+ ioc_fm_port_pcd_support pcd_support; -+ compat_uptr_t net_env_id; -+ compat_uptr_t p_prs_params; -+ compat_uptr_t p_cc_params; -+ compat_uptr_t p_kg_params; -+ compat_uptr_t p_plcr_params; -+ compat_uptr_t p_ip_reassembly_manip; -+#if DPAA_VERSION >= 11 -+ compat_uptr_t p_capwap_reassembly_manip; -+#endif -+} ioc_compat_fm_port_pcd_params_t; -+ -+typedef struct ioc_compat_fm_pcd_kg_cc_t { -+ compat_uptr_t tree_id; -+ uint8_t grp_id; -+ bool plcr_next; -+ bool bypass_plcr_profile_generation; -+ ioc_fm_pcd_kg_plcr_profile_t plcr_profile; -+} ioc_compat_fm_pcd_kg_cc_t; -+ -+typedef struct ioc_compat_fm_pcd_kg_scheme_params_t { -+ bool modify; -+ union { -+ uint8_t relative_scheme_id; -+ compat_uptr_t scheme_id; -+ } scm_id; -+ bool always_direct; -+ struct { -+ compat_uptr_t net_env_id; -+ uint8_t num_of_distinction_units; -+ uint8_t unit_ids[IOC_FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; -+ } net_env_params; -+ bool use_hash; -+ ioc_fm_pcd_kg_key_extract_and_hash_params_t key_extract_and_hash_params; -+ bool bypass_fqid_generation; -+ uint32_t base_fqid; -+ uint8_t num_of_used_extracted_ors; -+ ioc_fm_pcd_kg_extracted_or_params_t extracted_ors[IOC_FM_PCD_KG_NUM_OF_GENERIC_REGS]; -+#if DPAA_VERSION >= 11 -+ bool override_storage_profile; -+ ioc_fm_pcd_kg_storage_profile_t storage_profile; -+#endif /* DPAA_VERSION >= 11 */ -+ ioc_fm_pcd_engine next_engine; -+ union{ -+ ioc_fm_pcd_done_action done_action; -+ ioc_fm_pcd_kg_plcr_profile_t plcr_profile; -+ ioc_compat_fm_pcd_kg_cc_t cc; -+ } kg_next_engine_params; -+ ioc_fm_pcd_kg_scheme_counter_t scheme_counter; -+ compat_uptr_t id; -+} ioc_compat_fm_pcd_kg_scheme_params_t; -+ -+typedef struct ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t { -+ compat_uptr_t id; -+ uint16_t key_indx; -+ uint8_t key_size; -+ ioc_compat_fm_pcd_cc_next_engine_params_t cc_next_engine_params; -+} ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t; -+ -+typedef struct ioc_compat_fm_pcd_manip_hdr_insrt_generic_params_t { -+ uint8_t offset; -+ uint8_t size; -+ bool replace; -+ compat_uptr_t p_data; -+} ioc_compat_fm_pcd_manip_hdr_insrt_generic_params_t; -+ -+typedef struct ioc_compat_fm_pcd_manip_hdr_insrt_specific_l2_params_t { -+ ioc_fm_pcd_manip_hdr_insrt_specific_l2 specific_l2; -+ bool update; -+ uint8_t size; -+ compat_uptr_t p_data; -+} ioc_compat_fm_pcd_manip_hdr_insrt_specific_l2_params_t; -+ -+typedef struct ioc_compat_fm_pcd_manip_hdr_insrt_t { -+ uint8_t size; /**< size of inserted section */ -+ compat_uptr_t p_data; /**< data to be inserted */ -+} ioc_compat_fm_pcd_manip_hdr_insrt_t; -+ -+#if (DPAA_VERSION >= 11) -+typedef struct ioc_compat_fm_pcd_manip_hdr_insrt_ip_params_t { -+ bool calc_l4_checksum; /**< Calculate L4 checksum. */ -+ ioc_fm_pcd_manip_hdr_qos_mapping_mode mapping_mode; /**< TODO */ -+ uint8_t last_pid_offset; /**< the offset of the last Protocol within -+ the inserted header */ -+ uint16_t id; /**< 16 bit New IP ID */ -+ bool dont_frag_overwrite; -+ /**< IPv4 only. DF is overwritten with the hash-result next-to-last byte. -+ * This byte is configured to be overwritten when RPD is set. */ -+ uint8_t last_dst_offset; -+ /**< IPv6 only. if routing extension exist, user should set the offset of the destination address -+ * in order to calculate UDP checksum pseudo header; -+ * Otherwise set it to '0'. */ -+ ioc_compat_fm_pcd_manip_hdr_insrt_t insrt; /**< size and data to be inserted. */ -+} ioc_compat_fm_pcd_manip_hdr_insrt_ip_params_t; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+typedef struct ioc_compat_fm_pcd_manip_hdr_insrt_by_hdr_params_t { -+ ioc_fm_pcd_manip_hdr_insrt_by_hdr_type type; -+ union { -+ ioc_compat_fm_pcd_manip_hdr_insrt_specific_l2_params_t specific_l2_params; -+#if (DPAA_VERSION >= 11) -+ ioc_compat_fm_pcd_manip_hdr_insrt_ip_params_t ip_params; -+ ioc_compat_fm_pcd_manip_hdr_insrt_t insrt; -+#endif /* (DPAA_VERSION >= 11) */ -+ } u; -+} ioc_compat_fm_pcd_manip_hdr_insrt_by_hdr_params_t; -+ -+typedef struct ioc_compat_fm_pcd_manip_hdr_insrt_params_t { -+ ioc_fm_pcd_manip_hdr_insrt_type type; -+ union { -+ ioc_compat_fm_pcd_manip_hdr_insrt_by_hdr_params_t by_hdr; -+ ioc_compat_fm_pcd_manip_hdr_insrt_generic_params_t generic; -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+#error "FM_CAPWAP_SUPPORT feature not supported!" -+ ioc_fm_pcd_manip_hdr_insrt_by_template_params_t by_template; -+#endif /* FM_CAPWAP_SUPPORT */ -+ } u; -+} ioc_compat_fm_pcd_manip_hdr_insrt_params_t; -+ -+typedef struct ioc_compat_fm_pcd_manip_hdr_params_t { -+ bool rmv; -+ ioc_fm_pcd_manip_hdr_rmv_params_t rmv_params; -+ bool insrt; -+ ioc_compat_fm_pcd_manip_hdr_insrt_params_t insrt_params; -+ bool field_update; -+ ioc_fm_pcd_manip_hdr_field_update_params_t field_update_params; -+ bool custom; -+ ioc_fm_pcd_manip_hdr_custom_params_t custom_params; -+ bool dont_parse_after_manip; -+} ioc_compat_fm_pcd_manip_hdr_params_t; -+ -+typedef struct ioc_compat_fm_pcd_manip_special_offload_params_t { -+ bool decryption; -+ bool ecn_copy; -+ bool dscp_copy; -+ bool variable_ip_hdr_len; -+ bool variable_ip_version; -+ uint8_t outer_ip_hdr_len; -+ uint16_t arw_size; -+ compat_uptr_t arw_addr; -+} ioc_compat_fm_pcd_manip_special_offload_params_t; -+ -+typedef struct ioc_compat_fm_pcd_manip_params_t { -+ ioc_fm_pcd_manip_type type; -+ union { -+ ioc_compat_fm_pcd_manip_hdr_params_t hdr; -+ ioc_fm_pcd_manip_reassem_params_t reassem; -+ ioc_fm_pcd_manip_frag_params_t frag; -+ ioc_compat_fm_pcd_manip_special_offload_params_t special_offload; -+ } u; -+ compat_uptr_t p_next_manip; -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+#error "FM_CAPWAP_SUPPORT feature not supported!" -+ bool frag_or_reasm; -+ ioc_fm_pcd_manip_frag_or_reasm_params_t frag_or_reasm_params; -+#endif /* FM_CAPWAP_SUPPORT */ -+ compat_uptr_t id; -+} ioc_compat_fm_pcd_manip_params_t; -+ -+typedef struct ioc_compat_fm_pcd_manip_get_stats_t { -+ compat_uptr_t id; -+ ioc_fm_pcd_manip_stats_t stats; -+} ioc_compat_fm_pcd_manip_get_stats_t; -+ -+#if (DPAA_VERSION >= 11) -+typedef struct ioc_compat_fm_pcd_frm_replic_group_params_t { -+ uint8_t max_num_of_entries; -+ uint8_t num_of_entries; -+ ioc_compat_fm_pcd_cc_next_engine_params_t -+ next_engine_params[IOC_FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES]; -+ compat_uptr_t id; -+} ioc_compat_fm_pcd_frm_replic_group_params_t; -+ -+typedef struct ioc_compat_fm_pcd_frm_replic_member_t { -+ compat_uptr_t h_replic_group; -+ uint16_t member_index; -+} ioc_compat_fm_pcd_frm_replic_member_t; -+ -+typedef struct ioc_compat_fm_pcd_frm_replic_member_params_t { -+ ioc_compat_fm_pcd_frm_replic_member_t member; -+ ioc_compat_fm_pcd_cc_next_engine_params_t next_engine_params; -+} ioc_compat_fm_pcd_frm_replic_member_params_t; -+ -+typedef struct ioc_compat_fm_vsp_params_t { -+ compat_uptr_t p_fm; /**< A handle to the FM object this VSP related to */ -+ ioc_fm_ext_pools ext_buf_pools; /**< Which external buffer pools are used -+ (up to FM_PORT_MAX_NUM_OF_EXT_POOLS), and their sizes. -+ parameter associated with Rx / OP port */ -+ uint16_t liodn_offset; /**< VSP's LIODN offset */ -+ struct { -+ ioc_fm_port_type port_type; /**< Port type */ -+ uint8_t port_id; /**< Port Id - relative to type */ -+ } port_params; -+ uint8_t relative_profile_id; /**< VSP Id - relative to VSP's range -+ defined in relevant FM object */ -+ compat_uptr_t id; /**< return value */ -+} ioc_compat_fm_vsp_params_t; -+ -+typedef struct ioc_compat_fm_buf_pool_depletion_params_t { -+ compat_uptr_t p_fm_vsp; -+ ioc_fm_buf_pool_depletion_t fm_buf_pool_depletion; -+} ioc_compat_fm_buf_pool_depletion_params_t; -+ -+typedef struct ioc_compat_fm_buffer_prefix_content_params_t { -+ compat_uptr_t p_fm_vsp; -+ ioc_fm_buffer_prefix_content_t fm_buffer_prefix_content; -+} ioc_compat_fm_buffer_prefix_content_params_t; -+ -+typedef struct ioc_compat_fm_vsp_config_no_sg_params_t { -+ compat_uptr_t p_fm_vsp; -+ bool no_sg; -+} ioc_compat_fm_vsp_config_no_sg_params_t; -+ -+typedef struct ioc_compat_fm_vsp_prs_result_params_t { -+ compat_uptr_t p_fm_vsp; -+ compat_uptr_t p_data; -+} ioc_compat_fm_vsp_prs_result_params_t; -+ -+#endif /* (DPAA_VERSION >= 11) */ -+typedef struct ioc_compat_fm_pcd_kg_scheme_spc_t { -+ uint32_t val; -+ compat_uptr_t id; -+} ioc_compat_fm_pcd_kg_scheme_spc_t; -+ -+typedef struct ioc_compat_fm_ctrl_mon_counters_params_t { -+ uint8_t fm_ctrl_index; -+ compat_uptr_t p_mon; -+} ioc_compat_fm_ctrl_mon_counters_params_t; -+ -+typedef struct ioc_compat_fm_pcd_cc_tbl_get_stats_t { -+ compat_uptr_t id; -+ uint16_t key_index; -+ ioc_fm_pcd_cc_key_statistics_t statistics; -+} ioc_compat_fm_pcd_cc_tbl_get_stats_t; -+ -+ -+/* } pcd compat structures */ -+ -+void compat_obj_delete( -+ ioc_compat_fm_obj_t *compat_id, -+ ioc_fm_obj_t *id); -+ -+/* pcd compat functions { */ -+void compat_copy_fm_pcd_plcr_profile( -+ ioc_compat_fm_pcd_plcr_profile_params_t *compat_param, -+ ioc_fm_pcd_plcr_profile_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_cc_key( -+ ioc_compat_fm_pcd_cc_key_params_t *compat_param, -+ ioc_fm_pcd_cc_key_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_cc_node_modify_key_and_next_engine( -+ ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t *compat_param, -+ ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_cc_node_modify_next_engine( -+ ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t *compat_param, -+ ioc_fm_pcd_cc_node_modify_next_engine_params_t *param, -+ uint8_t compat); -+ -+void compat_fm_pcd_cc_tree_modify_next_engine( -+ ioc_compat_fm_pcd_cc_tree_modify_next_engine_params_t *compat_param, -+ ioc_fm_pcd_cc_tree_modify_next_engine_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_hash_table( -+ ioc_compat_fm_pcd_hash_table_params_t *compat_param, -+ ioc_fm_pcd_hash_table_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_cc_grp( -+ ioc_compat_fm_pcd_cc_grp_params_t *compat_param, -+ ioc_fm_pcd_cc_grp_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_cc_tree( -+ ioc_compat_fm_pcd_cc_tree_params_t *compat_param, -+ ioc_fm_pcd_cc_tree_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_cc_tbl_get_stats( -+ ioc_compat_fm_pcd_cc_tbl_get_stats_t *compat_param, -+ ioc_fm_pcd_cc_tbl_get_stats_t *param, -+ uint8_t compat); -+ -+void compat_fm_pcd_prs_sw( -+ ioc_compat_fm_pcd_prs_sw_params_t *compat_param, -+ ioc_fm_pcd_prs_sw_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_kg_scheme( -+ ioc_compat_fm_pcd_kg_scheme_params_t *compat_param, -+ ioc_fm_pcd_kg_scheme_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_kg_scheme_select( -+ ioc_compat_fm_pcd_kg_scheme_select_t *compat_param, -+ ioc_fm_pcd_kg_scheme_select_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_kg_schemes_params( -+ ioc_compat_fm_pcd_port_schemes_params_t *compat_param, -+ ioc_fm_pcd_port_schemes_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_port_pcd_kg( -+ ioc_compat_fm_port_pcd_kg_params_t *compat_param, -+ ioc_fm_port_pcd_kg_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_port_pcd( -+ ioc_compat_fm_port_pcd_params_t *compat_param, -+ ioc_fm_port_pcd_params_t *param, -+ uint8_t compat); -+ -+#if (DPAA_VERSION >= 11) -+void compat_copy_fm_port_vsp_alloc_params( -+ ioc_compat_fm_port_vsp_alloc_params_t *compat_param, -+ ioc_fm_port_vsp_alloc_params_t *param, -+ uint8_t compat); -+#endif /* (DPAA_VERSION >= 11) */ -+ -+void compat_copy_fm_pcd_net_env( -+ ioc_compat_fm_pcd_net_env_params_t *compat_param, -+ ioc_fm_pcd_net_env_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_cc_node_modify_key( -+ ioc_compat_fm_pcd_cc_node_modify_key_params_t *compat_param, -+ ioc_fm_pcd_cc_node_modify_key_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_keys( -+ ioc_compat_keys_params_t *compat_param, -+ ioc_keys_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_cc_node( -+ ioc_compat_fm_pcd_cc_node_params_t *compat_param, -+ ioc_fm_pcd_cc_node_params_t *param, -+ uint8_t compat); -+ -+void compat_fm_pcd_manip_set_node( -+ ioc_compat_fm_pcd_manip_params_t *compat_param, -+ ioc_fm_pcd_manip_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_manip_get_stats( -+ ioc_compat_fm_pcd_manip_get_stats_t *compat_param, -+ ioc_fm_pcd_manip_get_stats_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_port_pcd_modify_tree( -+ ioc_compat_fm_obj_t *compat_id, -+ ioc_fm_obj_t *id, -+ uint8_t compat); -+ -+#if (DPAA_VERSION >= 11) -+void compat_copy_fm_pcd_frm_replic_group_params( -+ ioc_compat_fm_pcd_frm_replic_group_params_t *compat_param, -+ ioc_fm_pcd_frm_replic_group_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_frm_replic_member( -+ ioc_compat_fm_pcd_frm_replic_member_t *compat_param, -+ ioc_fm_pcd_frm_replic_member_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_pcd_frm_replic_member_params( -+ ioc_compat_fm_pcd_frm_replic_member_params_t *compat_param, -+ ioc_fm_pcd_frm_replic_member_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_vsp_params( -+ ioc_compat_fm_vsp_params_t *compat_param, -+ ioc_fm_vsp_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_buf_pool_depletion_params( -+ ioc_compat_fm_buf_pool_depletion_params_t *compat_param, -+ ioc_fm_buf_pool_depletion_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_buffer_prefix_content_params( -+ ioc_compat_fm_buffer_prefix_content_params_t *compat_param, -+ ioc_fm_buffer_prefix_content_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_vsp_config_no_sg_params( -+ ioc_compat_fm_vsp_config_no_sg_params_t *compat_param, -+ ioc_fm_vsp_config_no_sg_params_t *param, -+ uint8_t compat); -+ -+void compat_copy_fm_vsp_prs_result_params( -+ ioc_compat_fm_vsp_prs_result_params_t *compat_param, -+ ioc_fm_vsp_prs_result_params_t *param, -+ uint8_t compat); -+ -+#endif /* (DPAA_VERSION >= 11) */ -+ -+void compat_copy_fm_pcd_kg_scheme_spc( -+ ioc_compat_fm_pcd_kg_scheme_spc_t *compat_param, -+ ioc_fm_pcd_kg_scheme_spc_t *param, -+ uint8_t compat); -+ -+/* } pcd compat functions */ -+#endif ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_resources.h -@@ -0,0 +1,121 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ @File lnxwrp_resources.h -+ -+ @Description FMD wrapper resource allocation functions. -+ -+*/ -+ -+#ifndef LNXWRP_RESOURCES_H_ -+#define LNXWRP_RESOURCES_H_ -+ -+#if !defined(FMAN_RESOURCES_UNIT_TEST) -+#include "lnxwrp_fm.h" -+#else -+#include "lnxwrp_resources_ut.h" -+#endif -+ -+#define ROUND(X) ((2*(X)+1)/2) -+#define CEIL(X) ((X)+1) -+/* #define ROUND_DIV(X, Y) (((X)+(Y)/2)/(Y)) */ -+#define ROUND_DIV(X, Y) ((2*(X)+(Y))/(2*(Y))) -+#define CEIL_DIV(X, Y) (((X)+(Y)-1)/(Y)) -+ -+/* used for resource calculus */ -+#define DPDE_1G 2 /* DQDP 1g - from LLD: -+ DEFAULT_PORT_txFifoDeqPipelineDepth_1G */ -+#define DPDE_10G 8 /* DQDP 10g - from LLD: -+ DEFAULT_PORT_txFifoDeqPipelineDepth_10G */ -+ -+int fm_set_active_fman_ports(struct platform_device *of_dev, -+ t_LnxWrpFmDev *p_LnxWrpFmDev); -+ -+/* Calculate the fifosize based on MURAM allocation, number of ports, dpde -+ * value and s/g software support (! Kernel does not suport s/g). -+ * -+ * Algorithm summary: -+ * - Calculate the the minimum fifosize required for every type of port -+ * (TX,RX for 1G, 2.5G and 10G). -+ * - Set TX the minimum fifosize required. -+ * - Distribute the remaining buffers (after all TX were set) to RX ports -+ * based on: -+ * 1G RX = Remaining_buffers * 1/(1+2.5+10) -+ * 2.5G RX = Remaining_buffers * 2.5/(1+2.5+10) -+ * 10G RX = Remaining_buffers * 10/(1+2.5+10) -+ * - if the RX is smaller than the minimum required, then set the minimum -+ * required -+ * - In the end distribuite the leftovers if there are any (due to -+ * unprecise calculus) or if over allocation cat some buffers from all RX -+ * ports w/o pass over minimum required treshold, but if there must be -+ * pass the treshold in order to cat the over allocation ,then this -+ * configuration can not be set - KERN_ALERT. -+*/ -+int fm_precalculate_fifosizes(t_LnxWrpFmDev *p_LnxWrpFmDev, -+ int muram_fifo_size); -+ -+#if !defined(FMAN_RESOURCES_UNIT_TEST) -+int fm_config_precalculate_fifosize(t_LnxWrpFmPortDev *p_LnxWrpFmPortDev); -+#endif -+ -+/* Compute FMan open DMA based on total number of open DMAs and -+ * number of available fman ports. -+ * -+ * By default 10g ports are set to input parameters. The other ports -+ * tries to keep the proportion rx=2tx open dmas or tresholds. -+ * -+ * If leftovers, then those will be set as shared. -+ * -+ * If after computing overflow appears, then it decrements open dma -+ * for all ports w/o cross the tresholds. If the tresholds are meet -+ * and is still overflow, then it returns error. -+*/ -+int fm_precalculate_open_dma(t_LnxWrpFmDev *p_LnxWrpFmDev, -+ int max_fm_open_dma, -+ int default_tx_10g_dmas, -+ int default_rx_10g_dmas, -+ int min_tx_10g_treshold, int min_rx_10g_treshold); -+ -+#if !defined(FMAN_RESOURCES_UNIT_TEST) -+int fm_config_precalculate_open_dma(t_LnxWrpFmPortDev *p_LnxWrpFmPortDev); -+#endif -+ -+/* Compute FMan tnums based on available tnums and number of ports. -+ * Set defaults (minim tresholds) and then distribute leftovers.*/ -+int fm_precalculate_tnums(t_LnxWrpFmDev *p_LnxWrpFmDev, int max_fm_tnums); -+ -+#if !defined(FMAN_RESOURCES_UNIT_TEST) -+int fm_config_precalculate_tnums(t_LnxWrpFmPortDev *p_LnxWrpFmPortDev); -+#endif -+ -+#endif /* LNXWRP_RESOURCES_H_ */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_resources_ut.c -@@ -0,0 +1,191 @@ -+/* Copyright (c) 2012 Freescale Semiconductor, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "lnxwrp_resources.h" -+#include "lnxwrp_resources_ut.h" -+ -+#define KILOBYTE 0x400 /* 1024 */ -+ -+typedef enum e_board_type { -+ e_p3041, -+ e_p4080, -+ e_p5020, -+ e_p1023 -+} e_board_type; -+ -+uint8_t board_type; -+uint32_t muram_size = 0; -+uint32_t dmas_num = 0; -+uint32_t task_num = 0; -+uint32_t frame_size = 0; -+uint32_t oh_num = 0; -+uint32_t num_ports_1g = 0; -+uint32_t num_ports_10g = 0; -+uint32_t num_ports_2g5 = 0; -+uint32_t fsl_fman_phy_maxfrm = 0; -+uint32_t dpa_rx_extra_headroom = 0; -+ -+void show_help(void){ -+ printf(" help: \n"); -+ printf(" -b -f -o -g1" -+ " -g10 -g25 \n"); -+ printf(" Maxim num of DMAS availbale: P3/P4/P5:32 , P1023:16 \n"); -+ printf(" Maxim num of TNUMs availbale: P3/P4/P5:128, P1023:32 \n"); -+ printf(" Muram size: P3/P4/P5:160K, P1023:64K \n"); -+ printf(" Number of ports:\n"); -+ printf(" P3/P5: 5p 1g, 1p 10g, 7p oh \n"); -+ printf(" P4 : 4p 1g, 1p 10g, 7p oh \n"); -+ printf(" P1 : 2p 1g, 0p 10g, 4p oh \n"); -+ printf(" MTU: Default:1522, Jumbo:9600 \n"); -+} -+ -+int fm_set_param(t_LnxWrpFmDev *p_LnxWrpFmDev) { -+ struct fm_active_ports *fm_active_ports_info = NULL; -+ fm_active_ports_info = &p_LnxWrpFmDev->fm_active_ports_info; -+ -+ switch(board_type){ -+ case e_p3041: -+ case e_p5020: -+ muram_size = 160*KILOBYTE; -+ dmas_num = 32; -+ task_num = 128; -+ if ((num_ports_1g+num_ports_2g5) > 5 || num_ports_10g > 1 || oh_num > 7) -+ goto err_fm_set_param; -+ break; -+ case e_p4080: -+ muram_size = 160*KILOBYTE; -+ dmas_num = 32; -+ task_num = 128; -+ if ((num_ports_1g+num_ports_2g5) > 4 || num_ports_10g > 1 || oh_num > 7) -+ goto err_fm_set_param; -+ break; -+ case e_p1023: -+ muram_size = 64*KILOBYTE; -+ dmas_num = 16; -+ task_num = 128; -+ if ((num_ports_1g+num_ports_2g5) > 2 || oh_num > 4) -+ goto err_fm_set_param; -+ break; -+ default: -+ goto err_fm_set_param; -+ break; -+ } -+ -+ p_LnxWrpFmDev->id = 0; -+ fsl_fman_phy_maxfrm = frame_size; -+ dpa_rx_extra_headroom = 0; /* ATTENTION: can be != 0 */ -+ fm_active_ports_info->num_oh_ports = oh_num; -+ fm_active_ports_info->num_tx_ports = num_ports_1g; -+ fm_active_ports_info->num_rx_ports = num_ports_1g; -+ fm_active_ports_info->num_tx25_ports = num_ports_2g5; -+ fm_active_ports_info->num_rx25_ports = num_ports_2g5; -+ fm_active_ports_info->num_tx10_ports = num_ports_10g; -+ fm_active_ports_info->num_rx10_ports = num_ports_10g; -+ -+ return 0; -+ -+err_fm_set_param: -+ printf(" ERR: To many ports!!! \n"); -+ return -1; -+} -+ -+int main (int argc, char *argv[]){ -+ t_LnxWrpFmDev LnxWrpFmDev; -+ t_LnxWrpFmDev *p_LnxWrpFmDev = &LnxWrpFmDev; -+ int tokens_cnt = 1; -+ -+ char *token = NULL; -+ -+ while(tokens_cnt < argc) -+ { -+ token = argv[tokens_cnt++]; -+ if (strcmp(token, "-b") == 0){ -+ if(strcmp(argv[tokens_cnt],"p3") == 0) -+ board_type = e_p3041; -+ else if(strcmp(argv[tokens_cnt],"p4") == 0) -+ board_type = e_p4080; -+ else if(strcmp(argv[tokens_cnt],"p5") == 0) -+ board_type = e_p5020; -+ else if(strcmp(argv[tokens_cnt],"p1") == 0) -+ board_type = e_p1023; -+ else -+ show_help(); -+ tokens_cnt++; -+ } -+ else if(strcmp(token, "-d") == 0){ -+ dmas_num = atoi(argv[tokens_cnt++]); -+ } -+ else if(strcmp(token, "-t") == 0) -+ task_num = atoi(argv[tokens_cnt++]); -+ else if(strcmp(token, "-f") == 0) -+ frame_size = atoi(argv[tokens_cnt++]); -+ else if(strcmp(token, "-o") == 0) -+ oh_num = atoi(argv[tokens_cnt++]); -+ else if(strcmp(token, "-g1") == 0) -+ num_ports_1g = atoi(argv[tokens_cnt++]); -+ else if(strcmp(token, "-g10") == 0) -+ num_ports_10g = atoi(argv[tokens_cnt++]); -+ else if(strcmp(token, "-g25") == 0) -+ num_ports_2g5 = atoi(argv[tokens_cnt++]); -+ else { -+ show_help(); -+ return -1; -+ } -+ } -+ -+ if(fm_set_param(p_LnxWrpFmDev) < 0){ -+ show_help(); -+ return -1; -+ } -+ -+ if(fm_precalculate_fifosizes( -+ p_LnxWrpFmDev, -+ 128*KILOBYTE) -+ != 0) -+ return -1; -+ if(fm_precalculate_open_dma( -+ p_LnxWrpFmDev, -+ dmas_num, /* max open dmas:dpaa_integration_ext.h */ -+ FM_DEFAULT_TX10G_OPENDMA, /* default TX 10g open dmas */ -+ FM_DEFAULT_RX10G_OPENDMA, /* default RX 10g open dmas */ -+ FM_10G_OPENDMA_MIN_TRESHOLD,/* TX 10g minimum treshold */ -+ FM_10G_OPENDMA_MIN_TRESHOLD)/* RX 10g minimum treshold */ -+ != 0) -+ return -1; -+ if(fm_precalculate_tnums( -+ p_LnxWrpFmDev, -+ task_num) /* max TNUMS: dpa integration file. */ -+ != 0) -+ return -1; -+ -+ return 0; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_resources_ut.h -@@ -0,0 +1,144 @@ -+/* Copyright (c) 2012 Freescale Semiconductor, Inc -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef FM_RESS_TEST_H_ -+#define FM_RESS_TEST_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define _Packed -+#define _PackedType __attribute__ ((packed)) -+#define MAX(x, y) (((x) > (y)) ? (x) : (y)) -+#define MIN(x, y) (((x) < (y)) ? (x) : (y)) -+#define KERN_ALERT "" -+#define KERN_INFO "" -+#define ASSERT_COND assert -+#define printk printf -+#define NET_IP_ALIGN 0 -+#define FM_FIFO_ALLOCATION_OLD_ALG -+ -+#if defined(CONFIG_FMAN_DISABLE_OH_AND_DISTRIBUTE_RESOURCES) -+#define FM_10G_OPENDMA_MIN_TRESHOLD 8 /* 10g minimum treshold if only HC is enabled and no OH port enabled */ -+#define FM_OPENDMA_RX_TX_RAPORT 2 /* RX = 2*TX */ -+#else -+#define FM_10G_OPENDMA_MIN_TRESHOLD 7 /* 10g minimum treshold if 7 OH ports are enabled */ -+#define FM_OPENDMA_RX_TX_RAPORT 1 /* RX = TX */ -+#endif -+#define FM_DEFAULT_TX10G_OPENDMA 8 /* default TX 10g open dmas */ -+#define FM_DEFAULT_RX10G_OPENDMA 8 /* default RX 10g open dmas */ -+ -+/* information about all active ports for an FMan. -+ * !Some ports may be disabled by u-boot, thus will not be available */ -+struct fm_active_ports { -+ uint32_t num_oh_ports; -+ uint32_t num_tx_ports; -+ uint32_t num_rx_ports; -+ uint32_t num_tx25_ports; -+ uint32_t num_rx25_ports; -+ uint32_t num_tx10_ports; -+ uint32_t num_rx10_ports; -+}; -+ -+/* FMan resources precalculated at fm probe based -+ * on available FMan port. */ -+struct fm_resource_settings { -+ /* buffers - fifo sizes */ -+ uint32_t tx1g_num_buffers; -+ uint32_t rx1g_num_buffers; -+ uint32_t tx2g5_num_buffers; /* Not supported yet by LLD */ -+ uint32_t rx2g5_num_buffers; /* Not supported yet by LLD */ -+ uint32_t tx10g_num_buffers; -+ uint32_t rx10g_num_buffers; -+ uint32_t oh_num_buffers; -+ uint32_t shared_ext_buffers; -+ -+ -+ /* open DMAs */ -+ uint32_t tx_1g_dmas; -+ uint32_t rx_1g_dmas; -+ uint32_t tx_2g5_dmas; /* Not supported yet by LLD */ -+ uint32_t rx_2g5_dmas; /* Not supported yet by LLD */ -+ uint32_t tx_10g_dmas; -+ uint32_t rx_10g_dmas; -+ uint32_t oh_dmas; -+ uint32_t shared_ext_open_dma; -+ -+ /* Tnums */ -+ uint32_t tx_1g_tnums; -+ uint32_t rx_1g_tnums; -+ uint32_t tx_2g5_tnums; /* Not supported yet by LLD */ -+ uint32_t rx_2g5_tnums; /* Not supported yet by LLD */ -+ uint32_t tx_10g_tnums; -+ uint32_t rx_10g_tnums; -+ uint32_t oh_tnums; -+ uint32_t shared_ext_tnums; -+}; -+ -+typedef struct { -+ uint8_t id; -+ struct fm_active_ports fm_active_ports_info; -+ struct fm_resource_settings fm_resource_settings_info; -+} t_LnxWrpFmDev; -+ -+typedef struct { -+ uint8_t id; -+} t_LnxWrpFmPortDev; -+ -+typedef _Packed struct t_FmPrsResult { -+ volatile uint8_t lpid; /**< Logical port id */ -+ volatile uint8_t shimr; /**< Shim header result */ -+ volatile uint16_t l2r; /**< Layer 2 result */ -+ volatile uint16_t l3r; /**< Layer 3 result */ -+ volatile uint8_t l4r; /**< Layer 4 result */ -+ volatile uint8_t cplan; /**< Classification plan id */ -+ volatile uint16_t nxthdr; /**< Next Header */ -+ volatile uint16_t cksum; /**< Checksum */ -+ volatile uint32_t lcv; /**< LCV */ -+ volatile uint8_t shim_off[3]; /**< Shim offset */ -+ volatile uint8_t eth_off; /**< ETH offset */ -+ volatile uint8_t llc_snap_off; /**< LLC_SNAP offset */ -+ volatile uint8_t vlan_off[2]; /**< VLAN offset */ -+ volatile uint8_t etype_off; /**< ETYPE offset */ -+ volatile uint8_t pppoe_off; /**< PPP offset */ -+ volatile uint8_t mpls_off[2]; /**< MPLS offset */ -+ volatile uint8_t ip_off[2]; /**< IP offset */ -+ volatile uint8_t gre_off; /**< GRE offset */ -+ volatile uint8_t l4_off; /**< Layer 4 offset */ -+ volatile uint8_t nxthdr_off; /**< Parser end point */ -+} _PackedType t_FmPrsResult; -+ -+#endif ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_resources_ut.make -@@ -0,0 +1,28 @@ -+CC=gcc -+ -+LNXWRP_RESS_UT=lnxwrp_resources_ut -+OBJ=lnxwrp_resources -+ -+INC_PATH= -+LIB_PATH= -+ -+INC=$(addprefix -I,$(INC_PATH)) -+LIB=$(addprefix -L,$(LIB_PATH)) -+ -+CFLAGS= -gdwarf-2 -g -O0 -Wall -+XFLAGS= -DFMAN_RESOURCES_UNIT_TEST -+ -+all: $(LNXWRP_RESS_UT) -+ -+$(LNXWRP_RESS_UT):$(addsuffix .o,$(OBJ)) $(LNXWRP_RESS_UT).o -+ $(CC) -o $(LNXWRP_RESS_UT) $(LNXWRP_RESS_UT).o $(addsuffix .o,$(OBJ)) -+ -+%.o: %.c -+ @(echo " (CC) $@") -+ @($(CC) $(INC) $(CFLAGS) $(XFLAGS) -o $(@) -c $<) -+ -+.PHONY: clean -+ -+clean: -+ rm -f *.o -+ rm -f $(LNXWRP_RESS_UT) ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs.c -@@ -0,0 +1,60 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ @File lnxwrp_sysfs.c -+ -+ @Description FM wrapper sysfs related functions. -+ -+*/ -+ -+#include -+#include "lnxwrp_sysfs.h" -+ -+uint8_t fm_find_statistic_counter_by_name(const char *attr_name, -+ const struct sysfs_stats_t *sysfs_stats, -+ uint8_t *offset) -+{ -+ int i = 0; -+ -+ while (sysfs_stats[i].stat_name != NULL) { -+ if (strcmp(sysfs_stats[i].stat_name, attr_name) == 0) { -+ if (offset != NULL) -+ *offset = i; -+ return sysfs_stats[i].stat_counter; -+ } -+ -+ i++; -+ } -+ WARN(1, "FMD: Should never get here!"); -+ return 0; -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs.h -@@ -0,0 +1,60 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef LNXWRP_SYSFS_H_ -+#define LNXWRP_SYSFS_H_ -+ -+/* Linux Headers ------------------- */ -+#include -+ -+#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS) -+#define MODVERSIONS -+#endif -+#ifdef MODVERSIONS -+#include -+#endif /* MODVERSIONS */ -+ -+#include -+#include -+#include -+#include -+ -+struct sysfs_stats_t { -+ const char *stat_name; -+ uint8_t stat_counter; -+}; -+ -+uint8_t fm_find_statistic_counter_by_name(const char *attr_name, -+ const struct sysfs_stats_t *sysfs_stats, -+ uint8_t *offset); -+ -+#endif /* LNXWRP_SYSFS_H_ */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs_fm.c -@@ -0,0 +1,1855 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "lnxwrp_sysfs.h" -+#include "lnxwrp_sysfs_fm.h" -+#include "lnxwrp_fm.h" -+ -+#include "../../sdk_fman/Peripherals/FM/inc/fm_common.h" -+#include "../../sdk_fman/Peripherals/FM/Pcd/fm_pcd.h" -+#include "../../sdk_fman/Peripherals/FM/Pcd/fm_kg.h" -+#include "../../sdk_fman/Peripherals/FM/Pcd/fm_plcr.h" -+ -+#if defined(__ERR_MODULE__) -+#undef __ERR_MODULE__ -+#endif -+ -+#include "../../sdk_fman/Peripherals/FM/fm.h" -+#include -+ -+ -+static int fm_get_counter(void *h_fm, e_FmCounters cnt_e, uint32_t *cnt_val); -+ -+enum fm_dma_match_stats { -+ FM_DMA_COUNTERS_CMQ_NOT_EMPTY, -+ FM_DMA_COUNTERS_BUS_ERROR, -+ FM_DMA_COUNTERS_READ_BUF_ECC_ERROR, -+ FM_DMA_COUNTERS_WRITE_BUF_ECC_SYS_ERROR, -+ FM_DMA_COUNTERS_WRITE_BUF_ECC_FM_ERROR -+}; -+ -+static const struct sysfs_stats_t fm_sysfs_stats[] = { -+ /* FM statistics */ -+ { -+ .stat_name = "enq_total_frame", -+ .stat_counter = e_FM_COUNTERS_ENQ_TOTAL_FRAME, -+ }, -+ { -+ .stat_name = "deq_total_frame", -+ .stat_counter = e_FM_COUNTERS_DEQ_TOTAL_FRAME, -+ }, -+ { -+ .stat_name = "deq_0", -+ .stat_counter = e_FM_COUNTERS_DEQ_0, -+ }, -+ { -+ .stat_name = "deq_1", -+ .stat_counter = e_FM_COUNTERS_DEQ_1, -+ }, -+ { -+ .stat_name = "deq_2", -+ .stat_counter = e_FM_COUNTERS_DEQ_2, -+ }, -+ { -+ .stat_name = "deq_3", -+ .stat_counter = e_FM_COUNTERS_DEQ_3, -+ }, -+ { -+ .stat_name = "deq_from_default", -+ .stat_counter = e_FM_COUNTERS_DEQ_FROM_DEFAULT, -+ }, -+ { -+ .stat_name = "deq_from_context", -+ .stat_counter = e_FM_COUNTERS_DEQ_FROM_CONTEXT, -+ }, -+ { -+ .stat_name = "deq_from_fd", -+ .stat_counter = e_FM_COUNTERS_DEQ_FROM_FD, -+ }, -+ { -+ .stat_name = "deq_confirm", -+ .stat_counter = e_FM_COUNTERS_DEQ_CONFIRM, -+ }, -+ /* FM:DMA statistics */ -+ { -+ .stat_name = "cmq_not_empty", -+ .stat_counter = FM_DMA_COUNTERS_CMQ_NOT_EMPTY, -+ }, -+ { -+ .stat_name = "bus_error", -+ .stat_counter = FM_DMA_COUNTERS_BUS_ERROR, -+ }, -+ { -+ .stat_name = "read_buf_ecc_error", -+ .stat_counter = FM_DMA_COUNTERS_READ_BUF_ECC_ERROR, -+ }, -+ { -+ .stat_name = "write_buf_ecc_sys_error", -+ .stat_counter = FM_DMA_COUNTERS_WRITE_BUF_ECC_SYS_ERROR, -+ }, -+ { -+ .stat_name = "write_buf_ecc_fm_error", -+ .stat_counter = FM_DMA_COUNTERS_WRITE_BUF_ECC_FM_ERROR, -+ }, -+ /* FM:PCD statistics */ -+ { -+ .stat_name = "pcd_kg_total", -+ .stat_counter = e_FM_PCD_KG_COUNTERS_TOTAL, -+ }, -+ { -+ .stat_name = "pcd_plcr_yellow", -+ .stat_counter = e_FM_PCD_PLCR_COUNTERS_YELLOW, -+ }, -+ { -+ .stat_name = "pcd_plcr_red", -+ .stat_counter = e_FM_PCD_PLCR_COUNTERS_RED, -+ }, -+ { -+ .stat_name = "pcd_plcr_recolored_to_red", -+ .stat_counter = e_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_RED, -+ }, -+ { -+ .stat_name = "pcd_plcr_recolored_to_yellow", -+ .stat_counter = e_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_YELLOW, -+ }, -+ { -+ .stat_name = "pcd_plcr_total", -+ .stat_counter = e_FM_PCD_PLCR_COUNTERS_TOTAL, -+ }, -+ { -+ .stat_name = "pcd_plcr_length_mismatch", -+ .stat_counter = e_FM_PCD_PLCR_COUNTERS_LENGTH_MISMATCH, -+ }, -+ { -+ .stat_name = "pcd_prs_parse_dispatch", -+ .stat_counter = e_FM_PCD_PRS_COUNTERS_PARSE_DISPATCH, -+ }, -+ { -+ .stat_name = "pcd_prs_l2_parse_result_returned", -+ .stat_counter = e_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED, -+ }, -+ { -+ .stat_name = "pcd_prs_l3_parse_result_returned", -+ .stat_counter = e_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED, -+ }, -+ { -+ .stat_name = "pcd_prs_l4_parse_result_returned", -+ .stat_counter = e_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED, -+ }, -+ { -+ .stat_name = "pcd_prs_shim_parse_result_returned", -+ .stat_counter = e_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED, -+ }, -+ { -+ .stat_name = "pcd_prs_l2_parse_result_returned_with_err", -+ .stat_counter = -+ e_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED_WITH_ERR, -+ }, -+ { -+ .stat_name = "pcd_prs_l3_parse_result_returned_with_err", -+ .stat_counter = -+ e_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED_WITH_ERR, -+ }, -+ { -+ .stat_name = "pcd_prs_l4_parse_result_returned_with_err", -+ .stat_counter = -+ e_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED_WITH_ERR, -+ }, -+ { -+ .stat_name = "pcd_prs_shim_parse_result_returned_with_err", -+ .stat_counter = -+ e_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED_WITH_ERR, -+ }, -+ { -+ .stat_name = "pcd_prs_soft_prs_cycles", -+ .stat_counter = e_FM_PCD_PRS_COUNTERS_SOFT_PRS_CYCLES, -+ }, -+ { -+ .stat_name = "pcd_prs_soft_prs_stall_cycles", -+ .stat_counter = e_FM_PCD_PRS_COUNTERS_SOFT_PRS_STALL_CYCLES, -+ }, -+ { -+ .stat_name = "pcd_prs_hard_prs_cycle_incl_stall_cycles", -+ .stat_counter = -+ e_FM_PCD_PRS_COUNTERS_HARD_PRS_CYCLE_INCL_STALL_CYCLES, -+ }, -+ { -+ .stat_name = "pcd_prs_muram_read_cycles", -+ .stat_counter = e_FM_PCD_PRS_COUNTERS_MURAM_READ_CYCLES, -+ }, -+ { -+ .stat_name = "pcd_prs_muram_read_stall_cycles", -+ .stat_counter = e_FM_PCD_PRS_COUNTERS_MURAM_READ_STALL_CYCLES, -+ }, -+ { -+ .stat_name = "pcd_prs_muram_write_cycles", -+ .stat_counter = e_FM_PCD_PRS_COUNTERS_MURAM_WRITE_CYCLES, -+ }, -+ { -+ .stat_name = "pcd_prs_muram_write_stall_cycles", -+ .stat_counter = e_FM_PCD_PRS_COUNTERS_MURAM_WRITE_STALL_CYCLES, -+ }, -+ { -+ .stat_name = "pcd_prs_fpm_command_stall_cycles", -+ .stat_counter = e_FM_PCD_PRS_COUNTERS_FPM_COMMAND_STALL_CYCLES, -+ }, -+ {} -+}; -+ -+ -+static ssize_t show_fm_risc_load(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+ unsigned long flags; -+ int m =0; -+ int err =0; -+ unsigned n = 0; -+ t_FmCtrlMon util; -+ uint8_t i =0 ; -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_Dev) -+ return -EIO; -+ -+ local_irq_save(flags); -+ -+ /* Calculate risc load */ -+ FM_CtrlMonStart(p_wrp_fm_dev->h_Dev); -+ msleep(1000); -+ FM_CtrlMonStop(p_wrp_fm_dev->h_Dev); -+ -+ for (i = 0; i < FM_NUM_OF_CTRL; i++) { -+ err |= FM_CtrlMonGetCounters(p_wrp_fm_dev->h_Dev, i, &util); -+ m = snprintf(&buf[n],PAGE_SIZE,"\tRisc%u: util-%u%%, efficiency-%u%%\n", -+ i, util.percentCnt[0], util.percentCnt[1]); -+ n=m+n; -+ } -+ -+ local_irq_restore(flags); -+ -+ return n; -+} -+ -+/* Fm stats and regs dumps via sysfs */ -+static ssize_t show_fm_dma_stats(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+ t_FmDmaStatus dma_status; -+ unsigned long flags = 0; -+ unsigned n = 0; -+ uint8_t counter_value = 0, counter = 0; -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_Dev) -+ return -EIO; -+ -+ counter = fm_find_statistic_counter_by_name( -+ attr->attr.name, -+ fm_sysfs_stats, NULL); -+ -+ local_irq_save(flags); -+ -+ memset(&dma_status, 0, sizeof(dma_status)); -+ FM_GetDmaStatus(p_wrp_fm_dev->h_Dev, &dma_status); -+ -+ switch (counter) { -+ case FM_DMA_COUNTERS_CMQ_NOT_EMPTY: -+ counter_value = dma_status.cmqNotEmpty; -+ break; -+ case FM_DMA_COUNTERS_BUS_ERROR: -+ counter_value = dma_status.busError; -+ break; -+ case FM_DMA_COUNTERS_READ_BUF_ECC_ERROR: -+ counter_value = dma_status.readBufEccError; -+ break; -+ case FM_DMA_COUNTERS_WRITE_BUF_ECC_SYS_ERROR: -+ counter_value = dma_status.writeBufEccSysError; -+ break; -+ case FM_DMA_COUNTERS_WRITE_BUF_ECC_FM_ERROR: -+ counter_value = dma_status.writeBufEccFmError; -+ break; -+ default: -+ WARN(1, "FMD: failure at %s:%d/%s()!\n", __FILE__, __LINE__, -+ __func__); -+ break; -+ }; -+ -+ n = snprintf(buf, PAGE_SIZE, "\tFM %u counter: %c\n", -+ p_wrp_fm_dev->id, counter_value ? 'T' : 'F'); -+ -+ local_irq_restore(flags); -+ -+ return n; -+} -+ -+static ssize_t show_fm_stats(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+ unsigned long flags = 0; -+ unsigned n = 0, cnt_e = 0; -+ uint32_t cnt_val; -+ int err; -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_Dev) -+ return -EIO; -+ -+ cnt_e = fm_find_statistic_counter_by_name( -+ attr->attr.name, -+ fm_sysfs_stats, NULL); -+ -+ err = fm_get_counter(p_wrp_fm_dev->h_Dev, -+ (e_FmCounters) cnt_e, &cnt_val); -+ -+ if (err) -+ return err; -+ -+ local_irq_save(flags); -+ -+ n = snprintf(buf, PAGE_SIZE, "\tFM %d counter: %d\n", -+ p_wrp_fm_dev->id, cnt_val); -+ -+ local_irq_restore(flags); -+ -+ return n; -+} -+ -+static ssize_t show_fm_muram_free_sz(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+ unsigned long flags = 0; -+ unsigned n = 0; -+ uint64_t muram_free_size = 0; -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_Dev) -+ return -EIO; -+ -+ muram_free_size = FM_MURAM_GetFreeMemSize(p_wrp_fm_dev->h_MuramDev); -+ -+ local_irq_save(flags); -+ -+ n = snprintf(buf, PAGE_SIZE, "\tFM %d muram_free_size: %lld\n", -+ p_wrp_fm_dev->id, muram_free_size); -+ -+ local_irq_restore(flags); -+ -+ return n; -+} -+ -+static ssize_t show_fm_ctrl_code_ver(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+ unsigned long flags = 0; -+ unsigned n = 0; -+ t_FmCtrlCodeRevisionInfo rv_info; -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_Dev) -+ return -EIO; -+ -+ FM_GetFmanCtrlCodeRevision((t_Fm *)p_wrp_fm_dev->h_Dev, &rv_info); -+ -+ local_irq_save(flags); -+ -+ FM_DMP_LN(buf, n, "- FM %d ctrl code pkg info:\n", p_wrp_fm_dev->id); -+ FM_DMP_LN(buf, n, "Package rev: %d\n", rv_info.packageRev); -+ FM_DMP_LN(buf, n, "major rev: %d\n", rv_info.majorRev); -+ FM_DMP_LN(buf, n, "minor rev: %d\n", rv_info.minorRev); -+ -+ local_irq_restore(flags); -+ -+ return n; -+} -+ -+static ssize_t show_fm_pcd_stats(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+ unsigned long flags = 0; -+ unsigned n = 0, counter = 0; -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_Dev || -+ !p_wrp_fm_dev->h_PcdDev) -+ return -EIO; -+ -+ counter = fm_find_statistic_counter_by_name( -+ attr->attr.name, -+ fm_sysfs_stats, NULL); -+ -+ local_irq_save(flags); -+ -+ n = snprintf(buf, PAGE_SIZE, "\tFM %d counter: %d\n", -+ p_wrp_fm_dev->id, -+ FM_PCD_GetCounter(p_wrp_fm_dev->h_PcdDev, -+ (e_FmPcdCounters) counter)); -+ -+ local_irq_restore(flags); -+ -+ return n; -+} -+ -+static ssize_t show_fm_tnum_dbg(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+#endif -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ local_irq_save(flags); -+ -+ if (!p_wrp_fm_dev->active) -+ return -EIO; -+ else { -+ int tn_s; -+ -+ if (!sscanf(attr->attr.name, "tnum_dbg_%d", &tn_s)) -+ return -EINVAL; -+ -+ n = fm_dump_tnum_dbg(p_wrp_fm_dev->h_Dev, -+ tn_s, tn_s + 15, buf, n); -+ } -+ local_irq_restore(flags); -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+ return n; -+} -+ -+static ssize_t show_fm_cls_plan(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+#endif -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ local_irq_save(flags); -+ -+ n = snprintf(buf, PAGE_SIZE, "\n FM-KG classification plan dump.\n"); -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_PcdDev) -+ return -EIO; -+ else { -+ int cpn; -+ -+ if (!sscanf(attr->attr.name, "cls_plan_%d", &cpn)) -+ return -EINVAL; -+ -+ n = fm_dump_cls_plan(p_wrp_fm_dev->h_PcdDev, cpn, buf, n); -+ } -+ local_irq_restore(flags); -+#else -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+ return n; -+} -+ -+static ssize_t show_fm_profiles(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+#endif -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ local_irq_save(flags); -+ -+ n = snprintf(buf, PAGE_SIZE, "FM policer profile dump.\n"); -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_PcdDev) -+ return -EIO; -+ else { -+ int pn; -+ -+ if (!sscanf(attr->attr.name, "profile_%d", &pn)) -+ return -EINVAL; -+ -+ n = fm_profile_dump_regs(p_wrp_fm_dev->h_PcdDev, pn, buf, n); -+ } -+ local_irq_restore(flags); -+#else -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+ return n; -+} -+ -+static ssize_t show_fm_schemes(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+#endif -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ local_irq_save(flags); -+ -+ n = snprintf(buf, PAGE_SIZE, "FM-KG driver schemes dump.\n"); -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_PcdDev) -+ return -EIO; -+ else { -+ int sn; -+ -+ if (!sscanf(attr->attr.name, "scheme_%d", &sn)) -+ return -EINVAL; -+ -+ n = fm_dump_scheme(p_wrp_fm_dev->h_PcdDev, sn, buf, n); -+ } -+ local_irq_restore(flags); -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+ return n; -+} -+ -+/* FM */ -+static DEVICE_ATTR(enq_total_frame, S_IRUGO, show_fm_stats, NULL); -+static DEVICE_ATTR(deq_total_frame, S_IRUGO, show_fm_stats, NULL); -+static DEVICE_ATTR(fm_risc_load_val, S_IRUGO, show_fm_risc_load, NULL); -+static DEVICE_ATTR(deq_0, S_IRUGO, show_fm_stats, NULL); -+static DEVICE_ATTR(deq_1, S_IRUGO, show_fm_stats, NULL); -+static DEVICE_ATTR(deq_2, S_IRUGO, show_fm_stats, NULL); -+static DEVICE_ATTR(deq_3, S_IRUGO, show_fm_stats, NULL); -+static DEVICE_ATTR(deq_from_default, S_IRUGO, show_fm_stats, NULL); -+static DEVICE_ATTR(deq_from_context, S_IRUGO, show_fm_stats, NULL); -+static DEVICE_ATTR(deq_from_fd, S_IRUGO, show_fm_stats, NULL); -+static DEVICE_ATTR(deq_confirm, S_IRUGO, show_fm_stats, NULL); -+/* FM:DMA */ -+static DEVICE_ATTR(cmq_not_empty, S_IRUGO, show_fm_dma_stats, NULL); -+static DEVICE_ATTR(bus_error, S_IRUGO, show_fm_dma_stats, NULL); -+static DEVICE_ATTR(read_buf_ecc_error, S_IRUGO, show_fm_dma_stats, NULL); -+static DEVICE_ATTR(write_buf_ecc_sys_error, S_IRUGO, show_fm_dma_stats, NULL); -+static DEVICE_ATTR(write_buf_ecc_fm_error, S_IRUGO, show_fm_dma_stats, NULL); -+/* FM:PCD */ -+static DEVICE_ATTR(pcd_kg_total, S_IRUGO, show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_plcr_yellow, S_IRUGO, show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_plcr_red, S_IRUGO, show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_plcr_recolored_to_red, S_IRUGO, show_fm_pcd_stats, -+ NULL); -+static DEVICE_ATTR(pcd_plcr_recolored_to_yellow, S_IRUGO, show_fm_pcd_stats, -+ NULL); -+static DEVICE_ATTR(pcd_plcr_total, S_IRUGO, show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_plcr_length_mismatch, S_IRUGO, show_fm_pcd_stats, -+ NULL); -+static DEVICE_ATTR(pcd_prs_parse_dispatch, S_IRUGO, show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_prs_l2_parse_result_returned, S_IRUGO, -+ show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_prs_l3_parse_result_returned, S_IRUGO, -+ show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_prs_l4_parse_result_returned, S_IRUGO, -+ show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_prs_shim_parse_result_returned, S_IRUGO, -+ show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_prs_l2_parse_result_returned_with_err, S_IRUGO, -+ show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_prs_l3_parse_result_returned_with_err, S_IRUGO, -+ show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_prs_l4_parse_result_returned_with_err, S_IRUGO, -+ show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_prs_shim_parse_result_returned_with_err, S_IRUGO, -+ show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_prs_soft_prs_cycles, S_IRUGO, show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_prs_soft_prs_stall_cycles, S_IRUGO, show_fm_pcd_stats, -+ NULL); -+static DEVICE_ATTR(pcd_prs_hard_prs_cycle_incl_stall_cycles, S_IRUGO, -+ show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_prs_muram_read_cycles, S_IRUGO, show_fm_pcd_stats, -+ NULL); -+static DEVICE_ATTR(pcd_prs_muram_read_stall_cycles, S_IRUGO, -+ show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_prs_muram_write_cycles, S_IRUGO, show_fm_pcd_stats, -+ NULL); -+static DEVICE_ATTR(pcd_prs_muram_write_stall_cycles, S_IRUGO, -+ show_fm_pcd_stats, NULL); -+static DEVICE_ATTR(pcd_prs_fpm_command_stall_cycles, S_IRUGO, -+ show_fm_pcd_stats, NULL); -+ -+static DEVICE_ATTR(tnum_dbg_0, S_IRUGO, show_fm_tnum_dbg, NULL); -+static DEVICE_ATTR(tnum_dbg_16, S_IRUGO, show_fm_tnum_dbg, NULL); -+static DEVICE_ATTR(tnum_dbg_32, S_IRUGO, show_fm_tnum_dbg, NULL); -+static DEVICE_ATTR(tnum_dbg_48, S_IRUGO, show_fm_tnum_dbg, NULL); -+static DEVICE_ATTR(tnum_dbg_64, S_IRUGO, show_fm_tnum_dbg, NULL); -+static DEVICE_ATTR(tnum_dbg_80, S_IRUGO, show_fm_tnum_dbg, NULL); -+static DEVICE_ATTR(tnum_dbg_96, S_IRUGO, show_fm_tnum_dbg, NULL); -+static DEVICE_ATTR(tnum_dbg_112, S_IRUGO, show_fm_tnum_dbg, NULL); -+ -+static DEVICE_ATTR(cls_plan_0, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_1, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_2, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_3, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_4, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_5, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_6, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_7, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_8, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_9, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_10, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_11, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_12, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_13, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_14, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_15, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_16, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_17, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_18, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_19, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_20, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_21, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_22, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_23, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_24, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_25, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_26, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_27, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_28, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_29, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_30, S_IRUGO, show_fm_cls_plan, NULL); -+static DEVICE_ATTR(cls_plan_31, S_IRUGO, show_fm_cls_plan, NULL); -+ -+static DEVICE_ATTR(profile_0, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_1, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_2, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_3, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_4, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_5, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_6, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_7, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_8, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_9, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_10, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_11, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_12, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_13, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_14, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_15, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_16, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_17, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_18, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_19, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_20, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_21, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_22, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_23, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_24, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_25, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_26, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_27, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_28, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_29, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_30, S_IRUGO, show_fm_profiles, NULL); -+static DEVICE_ATTR(profile_31, S_IRUGO, show_fm_profiles, NULL); -+ -+static DEVICE_ATTR(scheme_0, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_1, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_2, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_3, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_4, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_5, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_6, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_7, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_8, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_9, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_10, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_11, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_12, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_13, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_14, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_15, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_16, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_17, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_18, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_19, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_20, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_21, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_22, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_23, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_24, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_25, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_26, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_27, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_28, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_29, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_30, S_IRUGO, show_fm_schemes, NULL); -+static DEVICE_ATTR(scheme_31, S_IRUGO, show_fm_schemes, NULL); -+ -+ -+static struct attribute *fm_dev_stats_attributes[] = { -+ &dev_attr_enq_total_frame.attr, -+ &dev_attr_deq_total_frame.attr, -+ &dev_attr_deq_0.attr, -+ &dev_attr_deq_1.attr, -+ &dev_attr_deq_2.attr, -+ &dev_attr_deq_3.attr, -+ &dev_attr_deq_from_default.attr, -+ &dev_attr_deq_from_context.attr, -+ &dev_attr_deq_from_fd.attr, -+ &dev_attr_deq_confirm.attr, -+ &dev_attr_cmq_not_empty.attr, -+ &dev_attr_bus_error.attr, -+ &dev_attr_read_buf_ecc_error.attr, -+ &dev_attr_write_buf_ecc_sys_error.attr, -+ &dev_attr_write_buf_ecc_fm_error.attr, -+ &dev_attr_pcd_kg_total.attr, -+ &dev_attr_pcd_plcr_yellow.attr, -+ &dev_attr_pcd_plcr_red.attr, -+ &dev_attr_pcd_plcr_recolored_to_red.attr, -+ &dev_attr_pcd_plcr_recolored_to_yellow.attr, -+ &dev_attr_pcd_plcr_total.attr, -+ &dev_attr_pcd_plcr_length_mismatch.attr, -+ &dev_attr_pcd_prs_parse_dispatch.attr, -+ &dev_attr_pcd_prs_l2_parse_result_returned.attr, -+ &dev_attr_pcd_prs_l3_parse_result_returned.attr, -+ &dev_attr_pcd_prs_l4_parse_result_returned.attr, -+ &dev_attr_pcd_prs_shim_parse_result_returned.attr, -+ &dev_attr_pcd_prs_l2_parse_result_returned_with_err.attr, -+ &dev_attr_pcd_prs_l3_parse_result_returned_with_err.attr, -+ &dev_attr_pcd_prs_l4_parse_result_returned_with_err.attr, -+ &dev_attr_pcd_prs_shim_parse_result_returned_with_err.attr, -+ &dev_attr_pcd_prs_soft_prs_cycles.attr, -+ &dev_attr_pcd_prs_soft_prs_stall_cycles.attr, -+ &dev_attr_pcd_prs_hard_prs_cycle_incl_stall_cycles.attr, -+ &dev_attr_pcd_prs_muram_read_cycles.attr, -+ &dev_attr_pcd_prs_muram_read_stall_cycles.attr, -+ &dev_attr_pcd_prs_muram_write_cycles.attr, -+ &dev_attr_pcd_prs_muram_write_stall_cycles.attr, -+ &dev_attr_pcd_prs_fpm_command_stall_cycles.attr, -+ NULL -+}; -+ -+static struct attribute *fm_dev_tnums_dbg_attributes[] = { -+ &dev_attr_tnum_dbg_0.attr, -+ &dev_attr_tnum_dbg_16.attr, -+ &dev_attr_tnum_dbg_32.attr, -+ &dev_attr_tnum_dbg_48.attr, -+ &dev_attr_tnum_dbg_64.attr, -+ &dev_attr_tnum_dbg_80.attr, -+ &dev_attr_tnum_dbg_96.attr, -+ &dev_attr_tnum_dbg_112.attr, -+ NULL -+}; -+ -+static struct attribute *fm_dev_cls_plans_attributes[] = { -+ &dev_attr_cls_plan_0.attr, -+ &dev_attr_cls_plan_1.attr, -+ &dev_attr_cls_plan_2.attr, -+ &dev_attr_cls_plan_3.attr, -+ &dev_attr_cls_plan_4.attr, -+ &dev_attr_cls_plan_5.attr, -+ &dev_attr_cls_plan_6.attr, -+ &dev_attr_cls_plan_7.attr, -+ &dev_attr_cls_plan_8.attr, -+ &dev_attr_cls_plan_9.attr, -+ &dev_attr_cls_plan_10.attr, -+ &dev_attr_cls_plan_11.attr, -+ &dev_attr_cls_plan_12.attr, -+ &dev_attr_cls_plan_13.attr, -+ &dev_attr_cls_plan_14.attr, -+ &dev_attr_cls_plan_15.attr, -+ &dev_attr_cls_plan_16.attr, -+ &dev_attr_cls_plan_17.attr, -+ &dev_attr_cls_plan_18.attr, -+ &dev_attr_cls_plan_19.attr, -+ &dev_attr_cls_plan_20.attr, -+ &dev_attr_cls_plan_21.attr, -+ &dev_attr_cls_plan_22.attr, -+ &dev_attr_cls_plan_23.attr, -+ &dev_attr_cls_plan_24.attr, -+ &dev_attr_cls_plan_25.attr, -+ &dev_attr_cls_plan_26.attr, -+ &dev_attr_cls_plan_27.attr, -+ &dev_attr_cls_plan_28.attr, -+ &dev_attr_cls_plan_29.attr, -+ &dev_attr_cls_plan_30.attr, -+ &dev_attr_cls_plan_31.attr, -+ NULL -+}; -+ -+static struct attribute *fm_dev_profiles_attributes[] = { -+ &dev_attr_profile_0.attr, -+ &dev_attr_profile_1.attr, -+ &dev_attr_profile_2.attr, -+ &dev_attr_profile_3.attr, -+ &dev_attr_profile_4.attr, -+ &dev_attr_profile_5.attr, -+ &dev_attr_profile_6.attr, -+ &dev_attr_profile_7.attr, -+ &dev_attr_profile_8.attr, -+ &dev_attr_profile_9.attr, -+ &dev_attr_profile_10.attr, -+ &dev_attr_profile_11.attr, -+ &dev_attr_profile_12.attr, -+ &dev_attr_profile_13.attr, -+ &dev_attr_profile_14.attr, -+ &dev_attr_profile_15.attr, -+ &dev_attr_profile_16.attr, -+ &dev_attr_profile_17.attr, -+ &dev_attr_profile_18.attr, -+ &dev_attr_profile_19.attr, -+ &dev_attr_profile_20.attr, -+ &dev_attr_profile_21.attr, -+ &dev_attr_profile_22.attr, -+ &dev_attr_profile_23.attr, -+ &dev_attr_profile_24.attr, -+ &dev_attr_profile_25.attr, -+ &dev_attr_profile_26.attr, -+ &dev_attr_profile_27.attr, -+ &dev_attr_profile_28.attr, -+ &dev_attr_profile_29.attr, -+ &dev_attr_profile_30.attr, -+ &dev_attr_profile_31.attr, -+ NULL -+}; -+ -+static struct attribute *fm_dev_schemes_attributes[] = { -+ &dev_attr_scheme_0.attr, -+ &dev_attr_scheme_1.attr, -+ &dev_attr_scheme_2.attr, -+ &dev_attr_scheme_3.attr, -+ &dev_attr_scheme_4.attr, -+ &dev_attr_scheme_5.attr, -+ &dev_attr_scheme_6.attr, -+ &dev_attr_scheme_7.attr, -+ &dev_attr_scheme_8.attr, -+ &dev_attr_scheme_9.attr, -+ &dev_attr_scheme_10.attr, -+ &dev_attr_scheme_11.attr, -+ &dev_attr_scheme_12.attr, -+ &dev_attr_scheme_13.attr, -+ &dev_attr_scheme_14.attr, -+ &dev_attr_scheme_15.attr, -+ &dev_attr_scheme_16.attr, -+ &dev_attr_scheme_17.attr, -+ &dev_attr_scheme_18.attr, -+ &dev_attr_scheme_19.attr, -+ &dev_attr_scheme_20.attr, -+ &dev_attr_scheme_21.attr, -+ &dev_attr_scheme_22.attr, -+ &dev_attr_scheme_23.attr, -+ &dev_attr_scheme_24.attr, -+ &dev_attr_scheme_25.attr, -+ &dev_attr_scheme_26.attr, -+ &dev_attr_scheme_27.attr, -+ &dev_attr_scheme_28.attr, -+ &dev_attr_scheme_29.attr, -+ &dev_attr_scheme_30.attr, -+ &dev_attr_scheme_31.attr, -+ NULL -+}; -+ -+static const struct attribute_group fm_dev_stats_attr_grp = { -+ .name = "statistics", -+ .attrs = fm_dev_stats_attributes -+}; -+ -+static const struct attribute_group fm_dev_tnums_dbg_attr_grp = { -+ .name = "tnums_dbg", -+ .attrs = fm_dev_tnums_dbg_attributes -+}; -+ -+static const struct attribute_group fm_dev_cls_plans_attr_grp = { -+ .name = "cls_plans", -+ .attrs = fm_dev_cls_plans_attributes -+}; -+ -+static const struct attribute_group fm_dev_schemes_attr_grp = { -+ .name = "schemes", -+ .attrs = fm_dev_schemes_attributes -+}; -+ -+static const struct attribute_group fm_dev_profiles_attr_grp = { -+ .name = "profiles", -+ .attrs = fm_dev_profiles_attributes -+}; -+ -+static ssize_t show_fm_regs(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+#endif -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ local_irq_save(flags); -+ -+ n = snprintf(buf, PAGE_SIZE, "FM driver registers dump.\n"); -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_Dev) -+ return -EIO; -+ else -+ n = fm_dump_regs(p_wrp_fm_dev->h_Dev, buf, n); -+ -+ local_irq_restore(flags); -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+ return n; -+} -+ -+static ssize_t show_fm_kg_pe_regs(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+#endif -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ local_irq_save(flags); -+ -+ n = snprintf(buf, PAGE_SIZE, -+ "\n FM-KG Port Partition Config registers dump.\n"); -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_PcdDev) -+ return -EIO; -+ else -+ n = fm_kg_pe_dump_regs(p_wrp_fm_dev->h_PcdDev, buf, n); -+ -+ local_irq_restore(flags); -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+ return n; -+} -+ -+static ssize_t show_fm_kg_regs(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+#endif -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ local_irq_save(flags); -+ -+ n = snprintf(buf, PAGE_SIZE, "FM-KG registers dump.\n"); -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_PcdDev) -+ return -EIO; -+ else -+ n = fm_kg_dump_regs(p_wrp_fm_dev->h_PcdDev, buf, n); -+ -+ local_irq_restore(flags); -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+ return n; -+} -+ -+ -+static ssize_t show_fm_fpm_regs(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+#endif -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ local_irq_save(flags); -+ -+ n = snprintf(buf, PAGE_SIZE, "FM-FPM registers dump.\n"); -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_Dev) -+ return -EIO; -+ else -+ n = fm_fpm_dump_regs(p_wrp_fm_dev->h_Dev, buf, n); -+ -+ local_irq_restore(flags); -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+ return n; -+} -+ -+static ssize_t show_prs_regs(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+#endif -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, "FM Policer registers dump.\n"); -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_PcdDev) -+ return -EIO; -+ else -+ n = fm_prs_dump_regs(p_wrp_fm_dev->h_PcdDev, buf, n); -+ -+ local_irq_restore(flags); -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+ -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+ return n; -+} -+ -+static ssize_t show_plcr_regs(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+#endif -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return -EINVAL; -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, "FM Policer registers dump.\n"); -+ -+ if (!p_wrp_fm_dev->active || !p_wrp_fm_dev->h_PcdDev) -+ return -EIO; -+ else -+ n = fm_plcr_dump_regs(p_wrp_fm_dev->h_PcdDev, buf, n); -+ -+ local_irq_restore(flags); -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+ -+#endif /* (defined(DEBUG_ERRORS) && ... */ -+ -+ return n; -+} -+ -+static DEVICE_ATTR(fm_regs, S_IRUGO, show_fm_regs, NULL); -+static DEVICE_ATTR(fm_fpm_regs, S_IRUGO, show_fm_fpm_regs, NULL); -+static DEVICE_ATTR(fm_kg_regs, S_IRUGO, show_fm_kg_regs, NULL); -+static DEVICE_ATTR(fm_kg_pe_regs, S_IRUGO, show_fm_kg_pe_regs, NULL); -+static DEVICE_ATTR(fm_plcr_regs, S_IRUGO, show_plcr_regs, NULL); -+static DEVICE_ATTR(fm_prs_regs, S_IRUGO, show_prs_regs, NULL); -+static DEVICE_ATTR(fm_muram_free_size, S_IRUGO, show_fm_muram_free_sz, NULL); -+static DEVICE_ATTR(fm_ctrl_code_ver, S_IRUGO, show_fm_ctrl_code_ver, NULL); -+ -+int fm_sysfs_create(struct device *dev) -+{ -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+ -+ if (dev == NULL) -+ return -EIO; -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ -+ /* store to remove them when module is disabled */ -+ p_wrp_fm_dev->dev_attr_regs = &dev_attr_fm_regs; -+ p_wrp_fm_dev->dev_attr_risc_load = &dev_attr_fm_risc_load_val; -+ p_wrp_fm_dev->dev_fm_fpm_attr_regs = &dev_attr_fm_fpm_regs; -+ p_wrp_fm_dev->dev_fm_kg_attr_regs = &dev_attr_fm_kg_regs; -+ p_wrp_fm_dev->dev_fm_kg_pe_attr_regs = &dev_attr_fm_kg_pe_regs; -+ p_wrp_fm_dev->dev_plcr_attr_regs = &dev_attr_fm_plcr_regs; -+ p_wrp_fm_dev->dev_prs_attr_regs = &dev_attr_fm_prs_regs; -+ p_wrp_fm_dev->dev_attr_muram_free_size = &dev_attr_fm_muram_free_size; -+ p_wrp_fm_dev->dev_attr_fm_ctrl_code_ver = &dev_attr_fm_ctrl_code_ver; -+ -+ /* Create sysfs statistics group for FM module */ -+ if (sysfs_create_group(&dev->kobj, &fm_dev_stats_attr_grp) != 0) -+ return -EIO; -+ -+ if (sysfs_create_group(&dev->kobj, &fm_dev_schemes_attr_grp) != 0) -+ return -EIO; -+ -+ if (sysfs_create_group(&dev->kobj, &fm_dev_profiles_attr_grp) != 0) -+ return -EIO; -+ -+ if (sysfs_create_group(&dev->kobj, &fm_dev_tnums_dbg_attr_grp) != 0) -+ return -EIO; -+ -+ if (sysfs_create_group(&dev->kobj, &fm_dev_cls_plans_attr_grp) != 0) -+ return -EIO; -+ -+ /* Registers dump entry - in future will be moved to debugfs */ -+ if (device_create_file(dev, &dev_attr_fm_regs) != 0) -+ return -EIO; -+ -+ if (device_create_file(dev, &dev_attr_fm_risc_load_val) != 0) -+ return -EIO; -+ -+ if (device_create_file(dev, &dev_attr_fm_fpm_regs) != 0) -+ return -EIO; -+ -+ if (device_create_file(dev, &dev_attr_fm_kg_regs) != 0) -+ return -EIO; -+ -+ if (device_create_file(dev, &dev_attr_fm_kg_pe_regs) != 0) -+ return -EIO; -+ -+ if (device_create_file(dev, &dev_attr_fm_plcr_regs) != 0) -+ return -EIO; -+ -+ if (device_create_file(dev, &dev_attr_fm_prs_regs) != 0) -+ return -EIO; -+ -+ /* muram free size */ -+ if (device_create_file(dev, &dev_attr_fm_muram_free_size) != 0) -+ return -EIO; -+ -+ /* fm ctrl code version */ -+ if (device_create_file(dev, &dev_attr_fm_ctrl_code_ver) != 0) -+ return -EIO; -+ -+ return 0; -+} -+ -+void fm_sysfs_destroy(struct device *dev) -+{ -+ t_LnxWrpFmDev *p_wrp_fm_dev = NULL; -+ -+ if (WARN_ON(dev == NULL)) -+ return; -+ -+ p_wrp_fm_dev = (t_LnxWrpFmDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_wrp_fm_dev == NULL)) -+ return; -+ -+ sysfs_remove_group(&dev->kobj, &fm_dev_stats_attr_grp); -+ sysfs_remove_group(&dev->kobj, &fm_dev_schemes_attr_grp); -+ sysfs_remove_group(&dev->kobj, &fm_dev_profiles_attr_grp); -+ sysfs_remove_group(&dev->kobj, &fm_dev_cls_plans_attr_grp); -+ sysfs_remove_group(&dev->kobj, &fm_dev_tnums_dbg_attr_grp); -+ device_remove_file(dev, p_wrp_fm_dev->dev_attr_regs); -+ device_remove_file(dev, p_wrp_fm_dev->dev_fm_fpm_attr_regs); -+ device_remove_file(dev, p_wrp_fm_dev->dev_fm_kg_attr_regs); -+ device_remove_file(dev, p_wrp_fm_dev->dev_fm_kg_pe_attr_regs); -+ device_remove_file(dev, p_wrp_fm_dev->dev_plcr_attr_regs); -+ device_remove_file(dev, p_wrp_fm_dev->dev_prs_attr_regs); -+ device_remove_file(dev, p_wrp_fm_dev->dev_attr_muram_free_size); -+ device_remove_file(dev, p_wrp_fm_dev->dev_attr_fm_ctrl_code_ver); -+} -+ -+int fm_dump_regs(void *h_fm, char *buf, int nn) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_fm; -+ uint8_t i = 0; -+ int n = nn; -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ -+ FM_DMP_TITLE(buf, n, p_Fm->p_FmDmaRegs, "FM-DMA Regs"); -+ -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmsr); -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmemsr); -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmmr); -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmtr); -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmhy); -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmsetr); -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmtah); -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmtal); -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmtcid); -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmra); -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmrd); -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmwcr); -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmebcr); -+ FM_DMP_V32(buf, n, p_Fm->p_FmDmaRegs, fmdmdcr); -+ -+ FM_DMP_TITLE(buf, n, &p_Fm->p_FmDmaRegs->fmdmplr, "fmdmplr"); -+ -+ for (i = 0; i < FM_MAX_NUM_OF_HW_PORT_IDS / 2 ; ++i) -+ FM_DMP_MEM_32(buf, n, &p_Fm->p_FmDmaRegs->fmdmplr[i]); -+ -+ FM_DMP_TITLE(buf, n, p_Fm->p_FmBmiRegs, "FM-BMI COMMON Regs"); -+ FM_DMP_V32(buf, n, p_Fm->p_FmBmiRegs, fmbm_init); -+ FM_DMP_V32(buf, n, p_Fm->p_FmBmiRegs, fmbm_cfg1); -+ FM_DMP_V32(buf, n, p_Fm->p_FmBmiRegs, fmbm_cfg2); -+ FM_DMP_V32(buf, n, p_Fm->p_FmBmiRegs, fmbm_ievr); -+ FM_DMP_V32(buf, n, p_Fm->p_FmBmiRegs, fmbm_ier); -+ -+ FM_DMP_TITLE(buf, n, &p_Fm->p_FmBmiRegs->fmbm_arb, "fmbm_arb"); -+ for (i = 0; i < 8 ; ++i) -+ FM_DMP_MEM_32(buf, n, &p_Fm->p_FmBmiRegs->fmbm_arb[i]); -+ -+ FM_DMP_TITLE(buf, n, p_Fm->p_FmQmiRegs, "FM-QMI COMMON Regs"); -+ FM_DMP_V32(buf, n, p_Fm->p_FmQmiRegs, fmqm_gc); -+ FM_DMP_V32(buf, n, p_Fm->p_FmQmiRegs, fmqm_eie); -+ FM_DMP_V32(buf, n, p_Fm->p_FmQmiRegs, fmqm_eien); -+ FM_DMP_V32(buf, n, p_Fm->p_FmQmiRegs, fmqm_eif); -+ FM_DMP_V32(buf, n, p_Fm->p_FmQmiRegs, fmqm_ie); -+ FM_DMP_V32(buf, n, p_Fm->p_FmQmiRegs, fmqm_ien); -+ FM_DMP_V32(buf, n, p_Fm->p_FmQmiRegs, fmqm_if); -+ FM_DMP_V32(buf, n, p_Fm->p_FmQmiRegs, fmqm_gs); -+ FM_DMP_V32(buf, n, p_Fm->p_FmQmiRegs, fmqm_etfc); -+ -+ return n; -+} -+ -+int fm_dump_tnum_dbg(void *h_fm, int tn_s, int tn_e, char *buf, int nn) -+{ -+ t_Fm *p_Fm = (t_Fm *)h_fm; -+ uint8_t i, j = 0; -+ int n = nn; -+ -+ FM_DMP_TITLE(buf, n, NULL, "Tnums and Tnum dbg regs %d - %d", -+ tn_s, tn_e); -+ -+ iowrite32be(tn_s << 24, &p_Fm->p_FmFpmRegs->fmfp_dra); -+ -+ mb(); -+ -+ for (j = tn_s; j <= tn_e; j++) { -+ FM_DMP_LN(buf, n, "> fmfp_ts[%d]\n", j); -+ FM_DMP_MEM_32(buf, n, &p_Fm->p_FmFpmRegs->fmfp_ts[j]); -+ FM_DMP_V32(buf, n, p_Fm->p_FmFpmRegs, fmfp_dra); -+ FM_DMP_LN(buf, n, "> fmfp_drd[0-3]\n"); -+ -+ for (i = 0; i < 4 ; ++i) -+ FM_DMP_MEM_32(buf, n, &p_Fm->p_FmFpmRegs->fmfp_drd[i]); -+ -+ FM_DMP_LN(buf, n, "\n"); -+ -+ } -+ -+ return n; -+} -+ -+int fm_dump_cls_plan(void *h_fm_pcd, int cpn, char *buf, int nn) -+{ -+ t_FmPcd *p_pcd = (t_FmPcd *)h_fm_pcd; -+ int i = 0; -+ uint32_t tmp; -+ unsigned long i_flg; -+ int n = nn; -+ u_FmPcdKgIndirectAccessRegs *idac; -+ spinlock_t *p_lk; -+ -+ p_lk = (spinlock_t *)p_pcd->p_FmPcdKg->h_HwSpinlock; -+ idac = p_pcd->p_FmPcdKg->p_IndirectAccessRegs; -+ -+ spin_lock_irqsave(p_lk, i_flg); -+ -+ /* Read ClsPlan Block Action Regs */ -+ tmp = (uint32_t)(FM_KG_KGAR_GO | -+ FM_KG_KGAR_READ | -+ FM_PCD_KG_KGAR_SEL_CLS_PLAN_ENTRY | -+ DUMMY_PORT_ID | -+ ((uint32_t)cpn << FM_PCD_KG_KGAR_NUM_SHIFT) | -+ FM_PCD_KG_KGAR_WSEL_MASK); -+ -+ if (fman_kg_write_ar_wait(p_pcd->p_FmPcdKg->p_FmPcdKgRegs, tmp)) { -+ FM_DMP_LN(buf, nn, "Keygen scheme access violation"); -+ spin_unlock_irqrestore(p_lk, i_flg); -+ return nn; -+ } -+ FM_DMP_TITLE(buf, n, &idac->clsPlanRegs, -+ "ClsPlan %d Indirect Access Regs", cpn); -+ -+ for (i = 0; i < 8; i++) -+ FM_DMP_MEM_32(buf, n, &idac->clsPlanRegs.kgcpe[i]); -+ -+ spin_unlock_irqrestore(p_lk, i_flg); -+ -+ return n; -+} -+ -+int fm_profile_dump_regs(void *h_fm_pcd, int ppn, char *buf, int nn) -+{ -+ t_FmPcd *p_pcd = (t_FmPcd *)h_fm_pcd; -+ t_FmPcdPlcrProfileRegs *p_prof_regs; -+ t_FmPcdPlcrRegs *p_plcr_regs; -+ t_FmPcdPlcr *p_plcr; -+ uint32_t tmp; -+ unsigned long i_flg; -+ int n = nn; -+ int toc = 10; -+ spinlock_t *p_lk; -+ -+ p_plcr = p_pcd->p_FmPcdPlcr; -+ p_prof_regs = &p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->profileRegs; -+ p_plcr_regs = p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs; -+ -+ p_lk = (spinlock_t *)((t_FmPcdPlcr *)p_plcr)->h_HwSpinlock; -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_TITLE(buf, n, p_plcr_regs, "FM-PCD policer-profile regs"); -+ -+ tmp = (uint32_t)(FM_PCD_PLCR_PAR_GO | -+ FM_PCD_PLCR_PAR_R | -+ ((uint32_t)ppn << FM_PCD_PLCR_PAR_PNUM_SHIFT) | -+ FM_PCD_PLCR_PAR_PWSEL_MASK); -+ -+ spin_lock_irqsave(p_lk, i_flg); -+ -+ iowrite32be(tmp, &p_plcr_regs->fmpl_par); -+ -+ mb(); -+ -+ /* wait for the porfile regs to be present */ -+ do { -+ --toc; -+ udelay(10); -+ if (!toc) { -+ /* looks like PLCR_PAR_GO refuses to clear */ -+ spin_unlock_irqrestore(p_lk, i_flg); -+ FM_DMP_LN(buf, n, "Profile regs not accessible -"); -+ FM_DMP_LN(buf, n, " check profile init process\n"); -+ return n; -+ } -+ } while ((ioread32be(&p_plcr_regs->fmpl_par) & FM_PCD_PLCR_PAR_GO)); -+ -+ FM_DMP_TITLE(buf, n, p_prof_regs, "Profile %d regs", ppn); -+ -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_pemode); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_pegnia); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_peynia); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_pernia); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_pecir); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_pecbs); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_pepepir_eir); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_pepbs_ebs); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_pelts); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_pects); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_pepts_ets); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_pegpc); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_peypc); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_perpc); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_perypc); -+ FM_DMP_V32(buf, n, p_prof_regs, fmpl_perrpc); -+ -+ spin_unlock_irqrestore(p_lk, i_flg); -+ -+ return n; -+} -+ -+int fm_dump_scheme(void *h_fm_pcd, int scnum, char *buf, int nn) -+{ -+ t_FmPcd *p_pcd = (t_FmPcd *)h_fm_pcd; -+ uint32_t tmp_ar; -+ unsigned long i_flg; -+ int i, n = nn; -+ spinlock_t *p_lk; -+ u_FmPcdKgIndirectAccessRegs *idac; -+ -+ idac = p_pcd->p_FmPcdKg->p_IndirectAccessRegs; -+ p_lk = (spinlock_t *)p_pcd->p_FmPcdKg->h_HwSpinlock; -+ -+ spin_lock_irqsave(p_lk, i_flg); -+ -+ tmp_ar = FmPcdKgBuildReadSchemeActionReg((uint8_t)scnum); -+ if (fman_kg_write_ar_wait(p_pcd->p_FmPcdKg->p_FmPcdKgRegs, tmp_ar)) { -+ FM_DMP_LN(buf, nn, -+ "Keygen scheme access violation or no such scheme"); -+ spin_unlock_irqrestore(p_lk, i_flg); -+ return nn; -+ } -+ -+ FM_DMP_TITLE(buf, n, &idac->schemeRegs, -+ "Scheme %d Indirect Access Regs", scnum); -+ -+ FM_DMP_V32(buf, n, &idac->schemeRegs, kgse_mode); -+ FM_DMP_V32(buf, n, &idac->schemeRegs, kgse_ekfc); -+ FM_DMP_V32(buf, n, &idac->schemeRegs, kgse_ekdv); -+ FM_DMP_V32(buf, n, &idac->schemeRegs, kgse_bmch); -+ FM_DMP_V32(buf, n, &idac->schemeRegs, kgse_bmcl); -+ FM_DMP_V32(buf, n, &idac->schemeRegs, kgse_fqb); -+ FM_DMP_V32(buf, n, &idac->schemeRegs, kgse_hc); -+ FM_DMP_V32(buf, n, &idac->schemeRegs, kgse_ppc); -+ -+ FM_DMP_TITLE(buf, n, &idac->schemeRegs.kgse_gec, "kgse_gec"); -+ -+ for (i = 0; i < FM_KG_NUM_OF_GENERIC_REGS; i++) -+ FM_DMP_MEM_32(buf, n, &idac->schemeRegs.kgse_gec[i]); -+ -+ FM_DMP_V32(buf, n, &idac->schemeRegs, kgse_spc); -+ FM_DMP_V32(buf, n, &idac->schemeRegs, kgse_dv0); -+ FM_DMP_V32(buf, n, &idac->schemeRegs, kgse_dv1); -+ FM_DMP_V32(buf, n, &idac->schemeRegs, kgse_ccbs); -+ FM_DMP_V32(buf, n, &idac->schemeRegs, kgse_mv); -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ -+ spin_unlock_irqrestore(p_lk, i_flg); -+ -+ return n; -+} -+ -+int fm_kg_pe_dump_regs(void *h_fm_pcd, char *buf, int nn) -+{ -+ t_FmPcd *p_pcd = (t_FmPcd *)h_fm_pcd; -+ int i = 0; -+ uint8_t prt_id = 0; -+ uint32_t tmp_ar; -+ unsigned long i_flg; -+ int n = nn; -+ u_FmPcdKgIndirectAccessRegs *idac; -+ t_FmPcdKg *p_kg; -+ spinlock_t *p_lk; -+ -+ p_kg = p_pcd->p_FmPcdKg; -+ idac = p_pcd->p_FmPcdKg->p_IndirectAccessRegs; -+ p_lk = (spinlock_t *)p_kg->h_HwSpinlock; -+ -+ spin_lock_irqsave(p_lk, i_flg); -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ -+ for (i = 0; i < FM_MAX_NUM_OF_PORTS; i++) { -+ SW_PORT_INDX_TO_HW_PORT_ID(prt_id, i); -+ -+ tmp_ar = FmPcdKgBuildReadPortSchemeBindActionReg(prt_id); -+ -+ if (fman_kg_write_ar_wait(p_kg->p_FmPcdKgRegs, tmp_ar)) { -+ FM_DMP_LN(buf, nn, "Keygen scheme access violation"); -+ spin_unlock_irqrestore(p_lk, i_flg); -+ return nn; -+ } -+ FM_DMP_TITLE(buf, n, &idac->portRegs, "Port %d regs", prt_id); -+ FM_DMP_V32(buf, n, &idac->portRegs, fmkg_pe_sp); -+ FM_DMP_V32(buf, n, &idac->portRegs, fmkg_pe_cpp); -+ } -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ -+ spin_unlock_irqrestore(p_lk, i_flg); -+ -+ return n; -+} -+ -+int fm_kg_dump_regs(void *h_fm_pcd, char *buf, int nn) -+{ -+ t_FmPcd *p_pcd = (t_FmPcd *)h_fm_pcd; -+ int n = nn; -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_TITLE(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, -+ "FmPcdKgRegs Regs"); -+ -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, fmkg_gcr); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, fmkg_eer); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, fmkg_eeer); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, fmkg_seer); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, fmkg_seeer); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, fmkg_gsr); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, fmkg_tpc); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, fmkg_serc); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, fmkg_fdor); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, fmkg_gdv0r); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, fmkg_gdv1r); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, fmkg_feer); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdKg->p_FmPcdKgRegs, fmkg_ar); -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ -+ return n; -+} -+ -+ -+int fm_fpm_dump_regs(void *h_fm, char *buf, int nn) -+{ -+ t_Fm *p_fm = (t_Fm *)h_fm; -+ uint8_t i; -+ int n = nn; -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ -+ FM_DMP_TITLE(buf, n, p_fm->p_FmFpmRegs, "FM-FPM Regs"); -+ -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_tnc); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_prc); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_brkc); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_mxd); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_dist1); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_dist2); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fm_epi); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fm_rie); -+ -+ FM_DMP_TITLE(buf, n, &p_fm->p_FmFpmRegs->fmfp_fcev, "fmfp_fcev"); -+ for (i = 0; i < 4; ++i) -+ FM_DMP_MEM_32(buf, n, &p_fm->p_FmFpmRegs->fmfp_fcev[i]); -+ -+ FM_DMP_TITLE(buf, n, &p_fm->p_FmFpmRegs->fmfp_cee, "fmfp_cee"); -+ for (i = 0; i < 4; ++i) -+ FM_DMP_MEM_32(buf, n, &p_fm->p_FmFpmRegs->fmfp_cee[i]); -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_tsc1); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_tsc2); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_tsp); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_tsf); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fm_rcr); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_extc); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_ext1); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_ext2); -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fm_ip_rev_1); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fm_ip_rev_2); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fm_rstc); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fm_cld); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fm_npi); -+ FM_DMP_V32(buf, n, p_fm->p_FmFpmRegs, fmfp_ee); -+ -+ FM_DMP_TITLE(buf, n, &p_fm->p_FmFpmRegs->fmfp_cev, "fmfp_cev"); -+ for (i = 0; i < 4; ++i) -+ FM_DMP_MEM_32(buf, n, &p_fm->p_FmFpmRegs->fmfp_cev[i]); -+ -+ FM_DMP_TITLE(buf, n, &p_fm->p_FmFpmRegs->fmfp_ps, "fmfp_ps"); -+ for (i = 0; i < 64; ++i) -+ FM_DMP_MEM_32(buf, n, &p_fm->p_FmFpmRegs->fmfp_ps[i]); -+ -+ return n; -+} -+ -+int fm_prs_dump_regs(void *h_fm_pcd, char *buf, int nn) -+{ -+ t_FmPcd *p_pcd = (t_FmPcd *)h_fm_pcd; -+ int n = nn; -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ -+ FM_DMP_TITLE(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, -+ "FM-PCD parser regs"); -+ -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_rpclim); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_rpimac); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, pmeec); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_pevr); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_pever); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_perr); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_perer); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_ppsc); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_pds); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_l2rrs); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_l3rrs); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_l4rrs); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_srrs); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_l2rres); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_l3rres); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_l4rres); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_srres); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_spcs); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_spscs); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_hxscs); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_mrcs); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_mwcs); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_mrscs); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_mwscs); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPrs->p_FmPcdPrsRegs, fmpr_fcscs); -+ -+ return n; -+} -+ -+int fm_plcr_dump_regs(void *h_fm_pcd, char *buf, int nn) -+{ -+ t_FmPcd *p_pcd = (t_FmPcd *)h_fm_pcd; -+ int i = 0; -+ int n = nn; -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ -+ FM_DMP_TITLE(buf, n, -+ p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, -+ "FM policer regs"); -+ -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_gcr); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_gsr); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_evr); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_ier); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_ifr); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_eevr); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_eier); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_eifr); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_rpcnt); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_ypcnt); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_rrpcnt); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_rypcnt); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_tpcnt); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_flmcnt); -+ -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_serc); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_upcr); -+ FM_DMP_V32(buf, n, p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs, fmpl_dpmr); -+ -+ FM_DMP_TITLE(buf, n, -+ &p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_pmr, -+ "fmpl_pmr"); -+ -+ for (i = 0; i < 63; ++i) -+ FM_DMP_MEM_32(buf, n, -+ &p_pcd->p_FmPcdPlcr->p_FmPcdPlcrRegs->fmpl_pmr[i]); -+ -+ return n; -+} -+ -+int fm_get_counter(void *h_fm, e_FmCounters cnt_e, uint32_t *cnt_val) -+{ -+ t_Fm *p_fm = (t_Fm *)h_fm; -+ -+ /* When applicable (when there is an "enable counters" bit), -+ check that counters are enabled */ -+ -+ switch (cnt_e) { -+ case (e_FM_COUNTERS_DEQ_1): -+ case (e_FM_COUNTERS_DEQ_2): -+ case (e_FM_COUNTERS_DEQ_3): -+ if (p_fm->p_FmStateStruct->revInfo.majorRev >= 6) -+ return -EINVAL; /* counter not available */ -+ -+ case (e_FM_COUNTERS_ENQ_TOTAL_FRAME): -+ case (e_FM_COUNTERS_DEQ_TOTAL_FRAME): -+ case (e_FM_COUNTERS_DEQ_0): -+ case (e_FM_COUNTERS_DEQ_FROM_DEFAULT): -+ case (e_FM_COUNTERS_DEQ_FROM_CONTEXT): -+ case (e_FM_COUNTERS_DEQ_FROM_FD): -+ case (e_FM_COUNTERS_DEQ_CONFIRM): -+ if (!(ioread32be(&p_fm->p_FmQmiRegs->fmqm_gc) & -+ QMI_CFG_EN_COUNTERS)) -+ return -EINVAL; /* Requested counter not available */ -+ break; -+ default: -+ break; -+ } -+ -+ switch (cnt_e) { -+ case (e_FM_COUNTERS_ENQ_TOTAL_FRAME): -+ *cnt_val = ioread32be(&p_fm->p_FmQmiRegs->fmqm_etfc); -+ return 0; -+ case (e_FM_COUNTERS_DEQ_TOTAL_FRAME): -+ *cnt_val = ioread32be(&p_fm->p_FmQmiRegs->fmqm_dtfc); -+ return 0; -+ case (e_FM_COUNTERS_DEQ_0): -+ *cnt_val = ioread32be(&p_fm->p_FmQmiRegs->fmqm_dc0); -+ return 0; -+ case (e_FM_COUNTERS_DEQ_1): -+ *cnt_val = ioread32be(&p_fm->p_FmQmiRegs->fmqm_dc1); -+ return 0; -+ case (e_FM_COUNTERS_DEQ_2): -+ *cnt_val = ioread32be(&p_fm->p_FmQmiRegs->fmqm_dc2); -+ return 0; -+ case (e_FM_COUNTERS_DEQ_3): -+ *cnt_val = ioread32be(&p_fm->p_FmQmiRegs->fmqm_dc3); -+ return 0; -+ case (e_FM_COUNTERS_DEQ_FROM_DEFAULT): -+ *cnt_val = ioread32be(&p_fm->p_FmQmiRegs->fmqm_dfdc); -+ return 0; -+ case (e_FM_COUNTERS_DEQ_FROM_CONTEXT): -+ *cnt_val = ioread32be(&p_fm->p_FmQmiRegs->fmqm_dfcc); -+ return 0; -+ case (e_FM_COUNTERS_DEQ_FROM_FD): -+ *cnt_val = ioread32be(&p_fm->p_FmQmiRegs->fmqm_dffc); -+ return 0; -+ case (e_FM_COUNTERS_DEQ_CONFIRM): -+ *cnt_val = ioread32be(&p_fm->p_FmQmiRegs->fmqm_dcc); -+ return 0; -+ } -+ /* should never get here */ -+ return -EINVAL; /* counter not available */ -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs_fm.h -@@ -0,0 +1,136 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#ifndef LNXWRP_SYSFS_FM_H_ -+#define LNXWRP_SYSFS_FM_H_ -+ -+#include "lnxwrp_sysfs.h" -+ -+int fm_sysfs_create(struct device *dev); -+void fm_sysfs_destroy(struct device *dev); -+int fm_dump_regs(void *h_dev, char *buf, int nn); -+int fm_fpm_dump_regs(void *h_dev, char *buf, int nn); -+int fm_kg_dump_regs(void *h_pcd, char *buf, int nn); -+int fm_kg_pe_dump_regs(void *h_pcd, char *buf, int nn); -+int fm_dump_scheme(void *h_pcd, int scnum, char *buf, int nn); -+int fm_dump_tnum_dbg(void *h_fm, int tn_s, int tn_e, char *buf, int nn); -+int fm_dump_cls_plan(void *h_pcd, int cpn, char *buf, int nn); -+int fm_plcr_dump_regs(void *h_pcd, char *buf, int nn); -+int fm_prs_dump_regs(void *h_pcd, char *buf, int nn); -+int fm_profile_dump_regs(void *h_pcd, int ppnum, char *buf, int nn); -+ -+#define FM_DMP_PGSZ_ERR { \ -+ snprintf(&buf[PAGE_SIZE - 80], 70, \ -+ "\n Err: current sysfs buffer reached PAGE_SIZE\n");\ -+ n = PAGE_SIZE - 2; \ -+ } -+ -+#define FM_DMP_LN(buf, n, ...) \ -+ do { \ -+ int k, m = n; \ -+ m += k = snprintf(&buf[m], PAGE_SIZE - m, __VA_ARGS__); \ -+ if (k < 0 || m > PAGE_SIZE - 90) \ -+ FM_DMP_PGSZ_ERR \ -+ n = m; \ -+ } while (0) -+ -+#define FM_DMP_TITLE(buf, n, addr, ...) \ -+ do { \ -+ int k, m = n; \ -+ m += k = snprintf(&buf[m], PAGE_SIZE - m, "\n"); \ -+ if (k < 0 || m > PAGE_SIZE - 90) \ -+ FM_DMP_PGSZ_ERR \ -+ m += k = snprintf(&buf[m], PAGE_SIZE - m, __VA_ARGS__); \ -+ if (k < 0 || m > PAGE_SIZE - 90) \ -+ FM_DMP_PGSZ_ERR \ -+ if (addr) { \ -+ phys_addr_t pa; \ -+ pa = virt_to_phys(addr); \ -+ m += k = \ -+ snprintf(&buf[m], PAGE_SIZE - m, " (0x%lX)", \ -+ (long unsigned int)(pa)); \ -+ if (k < 0 || m > PAGE_SIZE - 90) \ -+ FM_DMP_PGSZ_ERR \ -+ } \ -+ m += k = snprintf(&buf[m], PAGE_SIZE - m, \ -+ "\n----------------------------------------\n\n"); \ -+ if (k < 0 || m > PAGE_SIZE - 90) \ -+ FM_DMP_PGSZ_ERR \ -+ n = m; \ -+ } while (0) -+ -+#define FM_DMP_SUBTITLE(buf, n, ...) \ -+ do { \ -+ int k, m = n; \ -+ m += k = snprintf(&buf[m], PAGE_SIZE - m, "------- "); \ -+ if (k < 0 || m > PAGE_SIZE - 90) \ -+ FM_DMP_PGSZ_ERR \ -+ m += k = snprintf(&buf[m], PAGE_SIZE - m, __VA_ARGS__); \ -+ if (k < 0 || m > PAGE_SIZE - 90) \ -+ FM_DMP_PGSZ_ERR \ -+ m += k = snprintf(&buf[m], PAGE_SIZE - m, "\n"); \ -+ if (k < 0 || m > PAGE_SIZE - 90) \ -+ FM_DMP_PGSZ_ERR \ -+ n = m; \ -+ } while (0) -+ -+#define FM_DMP_MEM_32(buf, n, addr) \ -+ { \ -+ uint32_t val; \ -+ phys_addr_t pa; \ -+ int k, m = n; \ -+ pa = virt_to_phys(addr); \ -+ val = ioread32be((addr)); \ -+ do { \ -+ m += k = snprintf(&buf[m], \ -+ PAGE_SIZE - m, "0x%010llX: 0x%08x\n", \ -+ pa, val); \ -+ if (k < 0 || m > PAGE_SIZE - 90) \ -+ FM_DMP_PGSZ_ERR \ -+ n += k; \ -+ } while (0) ;\ -+ } -+ -+#define FM_DMP_V32(buf, n, st, phrase) \ -+ do { \ -+ int k, m = n; \ -+ phys_addr_t pa = virt_to_phys(&((st)->phrase)); \ -+ k = snprintf(&buf[m], PAGE_SIZE - m, \ -+ "0x%010llX: 0x%08x%8s\t%s\n", (unsigned long long) pa, \ -+ ioread32be((uint32_t *)&((st)->phrase)), "", #phrase); \ -+ if (k < 0 || m > PAGE_SIZE - 90) \ -+ FM_DMP_PGSZ_ERR \ -+ n += k; \ -+ } while (0) -+ -+#endif /* LNXWRP_SYSFS_FM_H_ */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs_fm_port.c -@@ -0,0 +1,1255 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "lnxwrp_sysfs.h" -+#include "lnxwrp_fm.h" -+#include "debug_ext.h" -+#include "lnxwrp_sysfs_fm_port.h" -+#include "lnxwrp_sysfs_fm.h" -+ -+#include "../../sdk_fman/Peripherals/FM/Port/fm_port.h" -+#include "../../sdk_fman/Peripherals/FM/Port/fm_port_dsar.h" -+ -+#if defined(__ERR_MODULE__) -+#undef __ERR_MODULE__ -+#endif -+ -+#include "../../sdk_fman/Peripherals/FM/fm.h" -+ -+static const struct sysfs_stats_t portSysfsStats[] = { -+ /* RX/TX/OH common statistics */ -+ { -+ .stat_name = "port_frame", -+ .stat_counter = e_FM_PORT_COUNTERS_FRAME, -+ }, -+ { -+ .stat_name = "port_discard_frame", -+ .stat_counter = e_FM_PORT_COUNTERS_DISCARD_FRAME, -+ }, -+ { -+ .stat_name = "port_dealloc_buf", -+ .stat_counter = e_FM_PORT_COUNTERS_DEALLOC_BUF, -+ }, -+ { -+ .stat_name = "port_enq_total", -+ .stat_counter = e_FM_PORT_COUNTERS_ENQ_TOTAL, -+ }, -+ /* TX/OH */ -+ { -+ .stat_name = "port_length_err", -+ .stat_counter = e_FM_PORT_COUNTERS_LENGTH_ERR, -+ }, -+ { -+ .stat_name = "port_unsupprted_format", -+ .stat_counter = e_FM_PORT_COUNTERS_UNSUPPRTED_FORMAT, -+ }, -+ { -+ .stat_name = "port_deq_total", -+ .stat_counter = e_FM_PORT_COUNTERS_DEQ_TOTAL, -+ }, -+ { -+ .stat_name = "port_deq_from_default", -+ .stat_counter = e_FM_PORT_COUNTERS_DEQ_FROM_DEFAULT, -+ }, -+ { -+ .stat_name = "port_deq_confirm", -+ .stat_counter = e_FM_PORT_COUNTERS_DEQ_CONFIRM, -+ }, -+ /* RX/OH */ -+ { -+ .stat_name = "port_rx_bad_frame", -+ .stat_counter = e_FM_PORT_COUNTERS_RX_BAD_FRAME, -+ }, -+ { -+ .stat_name = "port_rx_large_frame", -+ .stat_counter = e_FM_PORT_COUNTERS_RX_LARGE_FRAME, -+ }, -+ { -+ .stat_name = "port_rx_out_of_buffers_discard", -+ .stat_counter = e_FM_PORT_COUNTERS_RX_OUT_OF_BUFFERS_DISCARD, -+ }, -+ { -+ .stat_name = "port_rx_filter_frame", -+ .stat_counter = e_FM_PORT_COUNTERS_RX_FILTER_FRAME, -+ }, -+ /* TODO: Particular statistics for OH ports */ -+ {} -+}; -+ -+static ssize_t show_fm_port_stats(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev; -+ t_LnxWrpFmDev *p_LnxWrpFmDev; -+ unsigned long flags; -+ int n = 0; -+ uint8_t counter = 0; -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+ p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_LnxWrpFmPortDev == NULL)) -+ return -EINVAL; -+ -+ p_LnxWrpFmDev = (t_LnxWrpFmDev *) p_LnxWrpFmPortDev->h_LnxWrpFmDev; -+ if (WARN_ON(p_LnxWrpFmDev == NULL)) -+ return -EINVAL; -+ -+ if (!p_LnxWrpFmDev->active || !p_LnxWrpFmDev->h_Dev) -+ return -EIO; -+ -+ if (!p_LnxWrpFmPortDev->h_Dev) { -+ n = snprintf(buf, PAGE_SIZE, "\tFM Port not configured...\n"); -+ return n; -+ } -+ -+ counter = fm_find_statistic_counter_by_name( -+ attr->attr.name, -+ portSysfsStats, NULL); -+ -+ if (counter == e_FM_PORT_COUNTERS_RX_LIST_DMA_ERR) { -+ uint32_t fmRev = 0; -+ fmRev = 0xffff & -+ ioread32(UINT_TO_PTR(p_LnxWrpFmDev->fmBaseAddr + -+ 0x000c30c4)); -+ -+ if (fmRev == 0x0100) { -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "counter not available for revision 1\n"); -+ local_irq_restore(flags); -+ } -+ return n; -+ } -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, "\t%s counter: %u\n", -+ p_LnxWrpFmPortDev->name, -+ FM_PORT_GetCounter(p_LnxWrpFmPortDev->h_Dev, -+ (e_FmPortCounters) counter)); -+ local_irq_restore(flags); -+ -+ return n; -+} -+ -+/* FM PORT RX/TX/OH statistics */ -+static DEVICE_ATTR(port_frame, S_IRUGO, show_fm_port_stats, NULL); -+static DEVICE_ATTR(port_discard_frame, S_IRUGO, show_fm_port_stats, NULL); -+static DEVICE_ATTR(port_dealloc_buf, S_IRUGO, show_fm_port_stats, NULL); -+static DEVICE_ATTR(port_enq_total, S_IRUGO, show_fm_port_stats, NULL); -+/* FM PORT TX/OH statistics */ -+static DEVICE_ATTR(port_length_err, S_IRUGO, show_fm_port_stats, NULL); -+static DEVICE_ATTR(port_unsupprted_format, S_IRUGO, show_fm_port_stats, NULL); -+static DEVICE_ATTR(port_deq_total, S_IRUGO, show_fm_port_stats, NULL); -+static DEVICE_ATTR(port_deq_from_default, S_IRUGO, show_fm_port_stats, NULL); -+static DEVICE_ATTR(port_deq_confirm, S_IRUGO, show_fm_port_stats, NULL); -+/* FM PORT RX/OH statistics */ -+static DEVICE_ATTR(port_rx_bad_frame, S_IRUGO, show_fm_port_stats, NULL); -+static DEVICE_ATTR(port_rx_large_frame, S_IRUGO, show_fm_port_stats, NULL); -+static DEVICE_ATTR(port_rx_out_of_buffers_discard, S_IRUGO, -+ show_fm_port_stats, NULL); -+static DEVICE_ATTR(port_rx_filter_frame, S_IRUGO, show_fm_port_stats, NULL); -+ -+/* FM PORT TX statistics */ -+static struct attribute *fm_tx_port_dev_stats_attributes[] = { -+ &dev_attr_port_frame.attr, -+ &dev_attr_port_discard_frame.attr, -+ &dev_attr_port_dealloc_buf.attr, -+ &dev_attr_port_enq_total.attr, -+ &dev_attr_port_length_err.attr, -+ &dev_attr_port_unsupprted_format.attr, -+ &dev_attr_port_deq_total.attr, -+ &dev_attr_port_deq_from_default.attr, -+ &dev_attr_port_deq_confirm.attr, -+ NULL -+}; -+ -+static const struct attribute_group fm_tx_port_dev_stats_attr_grp = { -+ .name = "statistics", -+ .attrs = fm_tx_port_dev_stats_attributes -+}; -+ -+/* FM PORT RX statistics */ -+static struct attribute *fm_rx_port_dev_stats_attributes[] = { -+ &dev_attr_port_frame.attr, -+ &dev_attr_port_discard_frame.attr, -+ &dev_attr_port_dealloc_buf.attr, -+ &dev_attr_port_enq_total.attr, -+ &dev_attr_port_rx_bad_frame.attr, -+ &dev_attr_port_rx_large_frame.attr, -+ &dev_attr_port_rx_out_of_buffers_discard.attr, -+ &dev_attr_port_rx_filter_frame.attr, -+ NULL -+}; -+ -+static const struct attribute_group fm_rx_port_dev_stats_attr_grp = { -+ .name = "statistics", -+ .attrs = fm_rx_port_dev_stats_attributes -+}; -+ -+/* TODO: add particular OH ports statistics */ -+static struct attribute *fm_oh_port_dev_stats_attributes[] = { -+ &dev_attr_port_frame.attr, -+ &dev_attr_port_discard_frame.attr, -+ &dev_attr_port_dealloc_buf.attr, -+ &dev_attr_port_enq_total.attr, -+ /*TX*/ &dev_attr_port_length_err.attr, -+ &dev_attr_port_unsupprted_format.attr, -+ &dev_attr_port_deq_total.attr, -+ &dev_attr_port_deq_from_default.attr, -+ &dev_attr_port_deq_confirm.attr, -+ /* &dev_attr_port_rx_bad_frame.attr, */ -+ /* &dev_attr_port_rx_large_frame.attr, */ -+ &dev_attr_port_rx_out_of_buffers_discard.attr, -+ /*&dev_attr_port_rx_filter_frame.attr, */ -+ NULL -+}; -+ -+static const struct attribute_group fm_oh_port_dev_stats_attr_grp = { -+ .name = "statistics", -+ .attrs = fm_oh_port_dev_stats_attributes -+}; -+ -+static ssize_t show_fm_port_regs(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = -+ (t_LnxWrpFmPortDev *) dev_get_drvdata(dev); -+#endif -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ local_irq_save(flags); -+ -+ if (!p_LnxWrpFmPortDev->h_Dev) { -+ n = snprintf(buf, PAGE_SIZE, "\tFM Port not configured...\n"); -+ return n; -+ } else { -+ n = snprintf(buf, PAGE_SIZE, -+ "FM port driver registers dump.\n"); -+ n = fm_port_dump_regs(p_LnxWrpFmPortDev->h_Dev, buf, n); -+ } -+ -+ local_irq_restore(flags); -+ -+ return n; -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+ -+ return n; -+#endif -+} -+static int fm_port_dsar_dump_mem(void *h_dev, char *buf, int nn) -+{ -+ t_FmPort *p_FmPort; -+ t_Fm *p_Fm; -+ uint8_t hardwarePortId; -+ uint32_t *param_page; -+ t_ArCommonDesc *ArCommonDescPtr; -+ uint32_t *mem; -+ int i, n = nn; -+ -+ p_FmPort = (t_FmPort *)h_dev; -+ hardwarePortId = p_FmPort->hardwarePortId; -+ p_Fm = (t_Fm *)p_FmPort->h_Fm; -+ -+ if (!FM_PORT_IsInDsar(p_FmPort)) -+ { -+ FM_DMP_LN(buf, n, "port %u is not a DSAR port\n", -+ hardwarePortId); -+ return n; -+ } -+ FM_DMP_LN(buf, n, "port %u DSAR mem\n", hardwarePortId); -+ FM_DMP_LN(buf, n, "========================\n"); -+ -+ /* do I need request_mem_region here? */ -+ param_page = ioremap(p_FmPort->fmMuramPhysBaseAddr + ioread32be(&p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rgpr), 4); -+ ArCommonDescPtr = (t_ArCommonDesc*)(ioremap(p_FmPort->fmMuramPhysBaseAddr + ioread32be(param_page), 300*4)); /* this should be changed*/ -+ mem = (uint32_t*)ArCommonDescPtr; -+ for (i = 0; i < 300; i+=4) -+ FM_DMP_LN(buf, n, "%08x: %08x %08x %08x %08x\n", i*4, mem[i], mem[i + 1], mem[i + 2], mem[i + 3]); -+ iounmap(ArCommonDescPtr); -+ iounmap(param_page); -+ return n; -+} -+ -+static int fm_port_dsar_dump_regs(void *h_dev, char *buf, int nn) -+{ -+ t_FmPort *p_FmPort; -+ t_Fm *p_Fm; -+ uint8_t hardwarePortId; -+ uint32_t *param_page; -+ t_ArCommonDesc *ArCommonDescPtr; -+ int i, n = nn; -+ -+ p_FmPort = (t_FmPort *)h_dev; -+ hardwarePortId = p_FmPort->hardwarePortId; -+ p_Fm = (t_Fm *)p_FmPort->h_Fm; -+ -+ if (!FM_PORT_IsInDsar(p_FmPort)) -+ { -+ FM_DMP_LN(buf, n, "port %u is not a DSAR port\n", -+ hardwarePortId); -+ return n; -+ } -+ FM_DMP_LN(buf, n, "port %u DSAR information\n", hardwarePortId); -+ FM_DMP_LN(buf, n, "========================\n"); -+ -+ /* do I need request_mem_region here? */ -+ param_page = ioremap(p_FmPort->fmMuramPhysBaseAddr + ioread32be(&p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rgpr), 4); -+ ArCommonDescPtr = (t_ArCommonDesc*)(ioremap(p_FmPort->fmMuramPhysBaseAddr + ioread32be(param_page), sizeof(t_ArCommonDesc))); /* this should be changed*/ -+ FM_DMP_LN(buf, n, "Tx port: 0x%x\n", ArCommonDescPtr->arTxPort); -+ FM_DMP_LN(buf, n, "Active HPNIA: 0x%08x\n", ArCommonDescPtr->activeHPNIA); -+ FM_DMP_LN(buf, n, "Snmp port: 0x%x\n", ArCommonDescPtr->snmpPort); -+ FM_DMP_LN(buf, n, "MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n", ArCommonDescPtr->macStationAddr[0], -+ ArCommonDescPtr->macStationAddr[1], ArCommonDescPtr->macStationAddr[2], -+ ArCommonDescPtr->macStationAddr[3], ArCommonDescPtr->macStationAddr[4], -+ ArCommonDescPtr->macStationAddr[5]); -+ FM_DMP_LN(buf, n, "filterControl: 0x%02x\n", ArCommonDescPtr->filterControl); -+ FM_DMP_LN(buf, n, "tcpControlPass: 0x%04x\n", ArCommonDescPtr->tcpControlPass); -+ FM_DMP_LN(buf, n, "ipProtocolTblSize: 0x%x\n", ArCommonDescPtr->ipProtocolTblSize); -+ FM_DMP_LN(buf, n, "udpPortTblSize: 0x%x\n", ArCommonDescPtr->udpPortTblSize); -+ FM_DMP_LN(buf, n, "tcpPortTblSize: 0x%x\n", ArCommonDescPtr->tcpPortTblSize); -+ if (ArCommonDescPtr->p_ArStats) -+ { -+ t_ArStatistics *arStatistics = (t_ArStatistics*) -+ ioremap(ioread32be(&ArCommonDescPtr->p_ArStats) + -+ p_FmPort->fmMuramPhysBaseAddr, -+ sizeof (t_ArStatistics)); -+ FM_DMP_LN(buf, n, "\nDSAR statistics\n"); -+ FM_DMP_LN(buf, n, "DSAR_Discarded: 0x%x\n", arStatistics->dsarDiscarded); -+ FM_DMP_LN(buf, n, "DSAR_Err_Discarded: 0x%x\n", arStatistics->dsarErrDiscarded); -+ FM_DMP_LN(buf, n, "DSAR_Frag_Discarded: 0x%x\n", arStatistics->dsarFragDiscarded); -+ FM_DMP_LN(buf, n, "DSAR_Tunnel_Discarded: 0x%x\n", arStatistics->dsarTunnelDiscarded); -+ FM_DMP_LN(buf, n, "DSAR_ARP_Discarded: 0x%x\n", arStatistics->dsarArpDiscarded); -+ FM_DMP_LN(buf, n, "DSAR_IP_Discarded: 0x%x\n", arStatistics->dsarIpDiscarded); -+ FM_DMP_LN(buf, n, "DSAR_TCP_Discarded: 0x%x\n", arStatistics->dsarTcpDiscarded); -+ FM_DMP_LN(buf, n, "DSAR_UDP_Discarded: 0x%x\n", arStatistics->dsarUdpDiscarded); -+ FM_DMP_LN(buf, n, "DSAR_ICMPv6_Checksum_Err: 0x%x\n", arStatistics->dsarIcmpV6ChecksumErr); -+ FM_DMP_LN(buf, n, "DSAR_ICMPv6_Other_Type: 0x%x\n", arStatistics->dsarIcmpV6OtherType); -+ FM_DMP_LN(buf, n, "DSAR_ICMPv4_Other_Type: 0x%x\n", arStatistics->dsarIcmpV4OtherType); -+ -+ iounmap(arStatistics); -+ } -+ if (ArCommonDescPtr->p_ArpDescriptor) -+ { -+ t_DsarArpDescriptor* ArpDescriptor = (t_DsarArpDescriptor*) -+ ioremap(ioread32be(&ArCommonDescPtr->p_ArpDescriptor) + -+ p_FmPort->fmMuramPhysBaseAddr, -+ sizeof (t_DsarArpDescriptor)); -+ FM_DMP_LN(buf, n, "\nARP\n"); -+ FM_DMP_LN(buf, n, "===\n"); -+ FM_DMP_LN(buf, n, "control bits 0x%04x\n", ArpDescriptor->control); -+ if (ArpDescriptor->numOfBindings) -+ { -+ char ip_str[100]; -+ t_DsarArpBindingEntry* bindings = ioremap( -+ ioread32be(&ArpDescriptor->p_Bindings) + -+ p_FmPort->fmMuramPhysBaseAddr, -+ ArpDescriptor->numOfBindings * -+ sizeof(t_DsarArpBindingEntry)); -+ uint8_t* ip_addr = (uint8_t*)&bindings->ipv4Addr; -+ FM_DMP_LN(buf, n, " ip vlan id\n"); -+ for (i = 0; i < ArpDescriptor->numOfBindings; i++) -+ { -+ n += snprintf(ip_str, 100, "%d.%d.%d.%d", -+ ip_addr[0], ip_addr[1], -+ ip_addr[2], ip_addr[3]); -+ FM_DMP_LN(buf, n, "%-15s 0x%x\n", -+ ip_str, bindings->vlanId); -+ } -+ iounmap(bindings); -+ } -+ if (ArpDescriptor->p_Statistics) -+ { -+ t_DsarArpStatistics* arpStats = ioremap( -+ ioread32be(&ArpDescriptor->p_Statistics) + -+ p_FmPort->fmMuramPhysBaseAddr, -+ sizeof(t_DsarArpStatistics)); -+ FM_DMP_LN(buf, n, "statistics\n"); -+ FM_DMP_LN(buf, n, "INVAL_CNT: 0x%x\n", arpStats->invalCnt); -+ FM_DMP_LN(buf, n, "ECHO_CNT: 0x%x\n", arpStats->echoCnt); -+ FM_DMP_LN(buf, n, "CD_CNT: 0x%x\n", arpStats->cdCnt); -+ FM_DMP_LN(buf, n, "AR_CNT: 0x%x\n", arpStats->arCnt); -+ FM_DMP_LN(buf, n, "RATM_CNT: 0x%x\n", arpStats->ratmCnt); -+ FM_DMP_LN(buf, n, "UKOP_CNT: 0x%x\n", arpStats->ukopCnt); -+ FM_DMP_LN(buf, n, "NMTP_CNT: 0x%x\n", arpStats->nmtpCnt); -+ FM_DMP_LN(buf, n, "NMVLAN_CNT: 0x%x\n", arpStats->nmVlanCnt); -+ iounmap(arpStats); -+ } -+ -+ iounmap(ArpDescriptor); -+ } -+ if (ArCommonDescPtr->p_IcmpV4Descriptor) -+ { -+ t_DsarIcmpV4Descriptor* ICMPV4Descriptor = -+ (t_DsarIcmpV4Descriptor*)ioremap(ioread32be( -+ &ArCommonDescPtr->p_IcmpV4Descriptor) + -+ p_FmPort->fmMuramPhysBaseAddr, -+ sizeof (t_DsarIcmpV4Descriptor)); -+ FM_DMP_LN(buf, n, "\nEcho ICMPv4\n"); -+ FM_DMP_LN(buf, n, "===========\n"); -+ FM_DMP_LN(buf, n, "control bits 0x%04x\n", ICMPV4Descriptor->control); -+ if (ICMPV4Descriptor->numOfBindings) -+ { -+ char ip_str[100]; -+ t_DsarArpBindingEntry* bindings = ioremap( -+ ioread32be(&ICMPV4Descriptor->p_Bindings) + -+ p_FmPort->fmMuramPhysBaseAddr, -+ ICMPV4Descriptor->numOfBindings * -+ sizeof(t_DsarArpBindingEntry)); -+ uint8_t* ip_addr = (uint8_t*)&bindings->ipv4Addr; -+ FM_DMP_LN(buf, n, " ip vlan id\n"); -+ for (i = 0; i < ICMPV4Descriptor->numOfBindings; i++) -+ { -+ n += snprintf(ip_str, 100, "%d.%d.%d.%d", -+ ip_addr[0], ip_addr[1], -+ ip_addr[2], ip_addr[3]); -+ FM_DMP_LN(buf, n, "%-15s 0x%x\n", -+ ip_str, bindings->vlanId); -+ } -+ iounmap(bindings); -+ } -+ if (ICMPV4Descriptor->p_Statistics) -+ { -+ t_DsarIcmpV4Statistics* icmpv4Stats = ioremap( -+ ioread32be(&ICMPV4Descriptor->p_Statistics) + -+ p_FmPort->fmMuramPhysBaseAddr, -+ sizeof(t_DsarIcmpV4Statistics)); -+ FM_DMP_LN(buf, n, "statistics\n"); -+ FM_DMP_LN(buf, n, "INVAL_CNT: 0x%x\n", icmpv4Stats->invalCnt); -+ FM_DMP_LN(buf, n, "NMVLAN_CNT: 0x%x\n", icmpv4Stats->nmVlanCnt); -+ FM_DMP_LN(buf, n, "NMIP_CNT: 0x%x\n", icmpv4Stats->nmIpCnt); -+ FM_DMP_LN(buf, n, "AR_CNT: 0x%x\n", icmpv4Stats->arCnt); -+ FM_DMP_LN(buf, n, "CSERR_CNT: 0x%x\n", icmpv4Stats->cserrCnt); -+ iounmap(icmpv4Stats); -+ } -+ iounmap(ICMPV4Descriptor); -+ } -+ if (ArCommonDescPtr->p_NdDescriptor) -+ { -+ t_DsarNdDescriptor *NDDescriptor = -+ (t_DsarNdDescriptor*)ioremap(ioread32be( -+ &ArCommonDescPtr->p_NdDescriptor) + p_FmPort-> -+ fmMuramPhysBaseAddr, sizeof (t_DsarNdDescriptor)); -+ FM_DMP_LN(buf, n, "\nNDP\n"); -+ FM_DMP_LN(buf, n, "===\n"); -+ FM_DMP_LN(buf, n, "control bits 0x%04x\n", NDDescriptor->control); -+ FM_DMP_LN(buf, n, "solicited address 0x%08x\n", NDDescriptor->solicitedAddr); -+ if (NDDescriptor->numOfBindings) -+ { -+ char ip_str[100]; -+ t_DsarIcmpV6BindingEntry* bindings = ioremap( -+ ioread32be(&NDDescriptor->p_Bindings) + -+ p_FmPort->fmMuramPhysBaseAddr, -+ NDDescriptor->numOfBindings * -+ sizeof(t_DsarIcmpV6BindingEntry)); -+ uint16_t* ip_addr = (uint16_t*)&bindings->ipv6Addr; -+ FM_DMP_LN(buf, n, " ip vlan id\n"); -+ for (i = 0; i < NDDescriptor->numOfBindings; i++) -+ { -+ n += snprintf(ip_str, 100, -+ "%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x", -+ ip_addr[0], ip_addr[1], ip_addr[2], ip_addr[3], -+ ip_addr[4], ip_addr[5], ip_addr[6], ip_addr[7]); -+ FM_DMP_LN(buf, n, "%s 0x%x\n", ip_str, bindings->vlanId); -+ } -+ iounmap(bindings); -+ } -+ if (NDDescriptor->p_Statistics) -+ { -+ t_NdStatistics* ndStats = ioremap( -+ ioread32be(&NDDescriptor->p_Statistics) + -+ p_FmPort->fmMuramPhysBaseAddr, -+ sizeof(t_NdStatistics)); -+ FM_DMP_LN(buf, n, "statistics\n"); -+ FM_DMP_LN(buf, n, "INVAL_CNT: 0x%x\n", ndStats->invalCnt); -+ FM_DMP_LN(buf, n, "NMVLAN_CNT: 0x%x\n", ndStats->nmVlanCnt); -+ FM_DMP_LN(buf, n, "NMIP_CNT: 0x%x\n", ndStats->nmIpCnt); -+ FM_DMP_LN(buf, n, "AR_CNT: 0x%x\n", ndStats->arCnt); -+ FM_DMP_LN(buf, n, "USADVERT_CNT: 0x%x\n", ndStats->usadvertCnt); -+ FM_DMP_LN(buf, n, "NMMCAST_CNT: 0x%x\n", ndStats->nmmcastCnt); -+ FM_DMP_LN(buf, n, "NSLLA_CNT: 0x%x\n", ndStats->nsllaCnt); -+ iounmap(ndStats); -+ } -+ iounmap(NDDescriptor); -+ } -+ if (ArCommonDescPtr->p_IcmpV6Descriptor) -+ { -+ t_DsarIcmpV6Descriptor *ICMPV6Descriptor = -+ (t_DsarIcmpV6Descriptor*)ioremap(ioread32be( -+ &ArCommonDescPtr->p_IcmpV6Descriptor) + p_FmPort-> -+ fmMuramPhysBaseAddr, sizeof (t_DsarIcmpV6Descriptor)); -+ FM_DMP_LN(buf, n, "\nEcho ICMPv6\n"); -+ FM_DMP_LN(buf, n, "===========\n"); -+ FM_DMP_LN(buf, n, "control bits 0x%04x\n", ICMPV6Descriptor->control); -+ if (ICMPV6Descriptor->numOfBindings) -+ { -+ char ip_str[100]; -+ t_DsarIcmpV6BindingEntry* bindings = ioremap( -+ ioread32be(&ICMPV6Descriptor->p_Bindings) + -+ p_FmPort->fmMuramPhysBaseAddr, -+ ICMPV6Descriptor->numOfBindings * -+ sizeof(t_DsarIcmpV6BindingEntry)); -+ uint16_t* ip_addr = (uint16_t*)&bindings->ipv6Addr; -+ FM_DMP_LN(buf, n, " ip vlan id\n"); -+ for (i = 0; i < ICMPV6Descriptor->numOfBindings; i++) -+ { -+ n += snprintf(ip_str, 100, -+ "%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x", -+ ip_addr[0], ip_addr[1], ip_addr[2], ip_addr[3], -+ ip_addr[4], ip_addr[5], ip_addr[6], ip_addr[7]); -+ FM_DMP_LN(buf, n, "%s 0x%x\n", ip_str, bindings->vlanId); -+ } -+ iounmap(bindings); -+ } -+ if (ICMPV6Descriptor->p_Statistics) -+ { -+ t_DsarIcmpV6Statistics* icmpv6Stats = ioremap( -+ ioread32be(&ICMPV6Descriptor->p_Statistics) + -+ p_FmPort->fmMuramPhysBaseAddr, -+ sizeof(t_DsarIcmpV6Statistics)); -+ FM_DMP_LN(buf, n, "statistics\n"); -+ FM_DMP_LN(buf, n, "INVAL_CNT: 0x%x\n", icmpv6Stats->invalCnt); -+ FM_DMP_LN(buf, n, "NMVLAN_CNT: 0x%x\n", icmpv6Stats->nmVlanCnt); -+ FM_DMP_LN(buf, n, "NMIP_CNT: 0x%x\n", icmpv6Stats->nmIpCnt); -+ FM_DMP_LN(buf, n, "AR_CNT: 0x%x\n", icmpv6Stats->arCnt); -+ iounmap(icmpv6Stats); -+ } -+ iounmap(ICMPV6Descriptor); -+ } -+ if (ArCommonDescPtr->p_SnmpDescriptor) -+ { -+ t_DsarSnmpDescriptor *SnmpDescriptor = -+ (t_DsarSnmpDescriptor*)ioremap(ioread32be( -+ &ArCommonDescPtr->p_SnmpDescriptor) + p_FmPort-> -+ fmMuramPhysBaseAddr, sizeof (t_DsarSnmpDescriptor)); -+ FM_DMP_LN(buf, n, "\nSNMP\n"); -+ FM_DMP_LN(buf, n, "===========\n"); -+ FM_DMP_LN(buf, n, "control bits 0x%04x\n", SnmpDescriptor->control); -+ FM_DMP_LN(buf, n, "max message length 0x%04x\n", SnmpDescriptor->maxSnmpMsgLength); -+ if (SnmpDescriptor->numOfIpv4Addresses) -+ { -+ char ip_str[100]; -+ t_DsarSnmpIpv4AddrTblEntry* addrs = ioremap( -+ ioread32be(&SnmpDescriptor->p_Ipv4AddrTbl) + -+ p_FmPort->fmMuramPhysBaseAddr, -+ SnmpDescriptor->numOfIpv4Addresses * -+ sizeof(t_DsarSnmpIpv4AddrTblEntry)); -+ uint8_t* ip_addr = (uint8_t*)&addrs->ipv4Addr; -+ FM_DMP_LN(buf, n, " ip vlan id\n"); -+ for (i = 0; i < SnmpDescriptor->numOfIpv4Addresses; i++) -+ { -+ n += snprintf(ip_str, 100, "%d.%d.%d.%d", -+ ip_addr[0], ip_addr[1], -+ ip_addr[2], ip_addr[3]); -+ FM_DMP_LN(buf, n, "%-15s 0x%x\n", ip_str, addrs->vlanId); -+ } -+ iounmap(addrs); -+ } -+ if (SnmpDescriptor->p_Statistics) -+ { -+ t_DsarSnmpStatistics* snmpStats = ioremap( -+ ioread32be(&SnmpDescriptor->p_Statistics) + -+ p_FmPort->fmMuramPhysBaseAddr, -+ sizeof(t_DsarSnmpStatistics)); -+ FM_DMP_LN(buf, n, "statistics\n"); -+ FM_DMP_LN(buf, n, "snmpErrCnt: 0x%x\n", snmpStats->snmpErrCnt); -+ FM_DMP_LN(buf, n, "snmpCommunityErrCnt: 0x%x\n", snmpStats->snmpCommunityErrCnt); -+ FM_DMP_LN(buf, n, "snmpTotalDiscardCnt: 0x%x\n", snmpStats->snmpTotalDiscardCnt); -+ FM_DMP_LN(buf, n, "snmpGetReqCnt: 0x%x\n", snmpStats->snmpGetReqCnt); -+ FM_DMP_LN(buf, n, "snmpGetNextReqCnt: 0x%x\n", snmpStats->snmpGetNextReqCnt); -+ iounmap(snmpStats); -+ } -+ iounmap(SnmpDescriptor); -+ } -+ iounmap(ArCommonDescPtr); -+ iounmap(param_page); -+ return n; -+} -+ -+static ssize_t show_fm_port_dsar_mem(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = -+ (t_LnxWrpFmPortDev *) dev_get_drvdata(dev); -+#endif -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ local_irq_save(flags); -+ -+ if (!p_LnxWrpFmPortDev->h_Dev) { -+ n = snprintf(buf, PAGE_SIZE, "\tFM Port not configured...\n"); -+ return n; -+ } else { -+ n = snprintf(buf, PAGE_SIZE, -+ "FM port driver registers dump.\n"); -+ n = fm_port_dsar_dump_mem(p_LnxWrpFmPortDev->h_Dev, buf, n); -+ } -+ -+ local_irq_restore(flags); -+ -+ return n; -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+ -+ return n; -+#endif -+} -+ -+static ssize_t show_fm_port_dsar_regs(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = -+ (t_LnxWrpFmPortDev *) dev_get_drvdata(dev); -+#endif -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ local_irq_save(flags); -+ -+ if (!p_LnxWrpFmPortDev->h_Dev) { -+ n = snprintf(buf, PAGE_SIZE, "\tFM Port not configured...\n"); -+ return n; -+ } else { -+ n = snprintf(buf, PAGE_SIZE, -+ "FM port driver registers dump.\n"); -+ n = fm_port_dsar_dump_regs(p_LnxWrpFmPortDev->h_Dev, buf, n); -+ } -+ -+ local_irq_restore(flags); -+ -+ return n; -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+ -+ return n; -+#endif -+} -+ -+#if (DPAA_VERSION >= 11) -+static ssize_t show_fm_port_ipv4_options(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = -+ (t_LnxWrpFmPortDev *) dev_get_drvdata(dev); -+#endif -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ local_irq_save(flags); -+ -+ if (!p_LnxWrpFmPortDev->h_Dev) { -+ n = snprintf(buf, PAGE_SIZE, "\tFM Port not configured...\n"); -+ return n; -+ } else if (((t_FmPort *)p_LnxWrpFmPortDev->h_Dev)->p_ParamsPage -+ == NULL) { -+ n = snprintf(buf, PAGE_SIZE, -+ "\tPort: FMan-controller params page not set\n"); -+ return n; -+ } else { -+ n = snprintf(buf, PAGE_SIZE, -+ "Counter for fragmented pkt with IP header options\n"); -+ n = fm_port_dump_ipv4_opt(p_LnxWrpFmPortDev->h_Dev, buf, n); -+ } -+ -+ local_irq_restore(flags); -+ -+ return n; -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+ -+ return n; -+#endif -+} -+ -+#endif -+ -+static ssize_t show_fm_port_bmi_regs(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = -+ (t_LnxWrpFmPortDev *) dev_get_drvdata(dev); -+#endif -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ local_irq_save(flags); -+ -+ if (!p_LnxWrpFmPortDev->h_Dev) { -+ n = snprintf(buf, PAGE_SIZE, "\tFM Port not configured...\n"); -+ return n; -+ } else { -+ n = snprintf(buf, PAGE_SIZE, -+ "FM port driver registers dump.\n"); -+ n = fm_port_dump_regs_bmi(p_LnxWrpFmPortDev->h_Dev, buf, n); -+ } -+ -+ local_irq_restore(flags); -+ -+ return n; -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+ -+ return n; -+#endif -+} -+ -+static ssize_t show_fm_port_qmi_regs(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ unsigned long flags; -+ unsigned n = 0; -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = -+ (t_LnxWrpFmPortDev *) dev_get_drvdata(dev); -+#endif -+ -+ if (attr == NULL || buf == NULL || dev == NULL) -+ return -EINVAL; -+ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ local_irq_save(flags); -+ -+ if (!p_LnxWrpFmPortDev->h_Dev) { -+ n = snprintf(buf, PAGE_SIZE, "\tFM Port not configured...\n"); -+ return n; -+ } else { -+ n = snprintf(buf, PAGE_SIZE, -+ "FM port driver registers dump.\n"); -+ n = fm_port_dump_regs_qmi(p_LnxWrpFmPortDev->h_Dev, buf, n); -+ } -+ -+ local_irq_restore(flags); -+ -+ return n; -+#else -+ -+ local_irq_save(flags); -+ n = snprintf(buf, PAGE_SIZE, -+ "Debug level is too low to dump registers!!!\n"); -+ local_irq_restore(flags); -+ -+ return n; -+#endif -+} -+ -+static DEVICE_ATTR(fm_port_regs, S_IRUGO | S_IRUSR, show_fm_port_regs, NULL); -+static DEVICE_ATTR(fm_port_qmi_regs, S_IRUGO | S_IRUSR, show_fm_port_qmi_regs, NULL); -+static DEVICE_ATTR(fm_port_bmi_regs, S_IRUGO | S_IRUSR, show_fm_port_bmi_regs, NULL); -+#if (DPAA_VERSION >= 11) -+static DEVICE_ATTR(fm_port_ipv4_opt, S_IRUGO | S_IRUSR, show_fm_port_ipv4_options, NULL); -+#endif -+static DEVICE_ATTR(fm_port_dsar_regs, S_IRUGO | S_IRUSR, show_fm_port_dsar_regs, NULL); -+static DEVICE_ATTR(fm_port_dsar_mem, S_IRUGO | S_IRUSR, show_fm_port_dsar_mem, NULL); -+ -+int fm_port_sysfs_create(struct device *dev) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev; -+ -+ if (dev == NULL) -+ return -EINVAL; -+ -+ p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_LnxWrpFmPortDev == NULL)) -+ return -EINVAL; -+ -+ /* store to remove them when module is disabled */ -+ p_LnxWrpFmPortDev->dev_attr_regs = &dev_attr_fm_port_regs; -+ p_LnxWrpFmPortDev->dev_attr_qmi_regs = &dev_attr_fm_port_qmi_regs; -+ p_LnxWrpFmPortDev->dev_attr_bmi_regs = &dev_attr_fm_port_bmi_regs; -+#if (DPAA_VERSION >= 11) -+ p_LnxWrpFmPortDev->dev_attr_ipv4_opt = &dev_attr_fm_port_ipv4_opt; -+#endif -+ p_LnxWrpFmPortDev->dev_attr_dsar_regs = &dev_attr_fm_port_dsar_regs; -+ p_LnxWrpFmPortDev->dev_attr_dsar_mem = &dev_attr_fm_port_dsar_mem; -+ /* Registers dump entry - in future will be moved to debugfs */ -+ if (device_create_file(dev, &dev_attr_fm_port_regs) != 0) -+ return -EIO; -+ if (device_create_file(dev, &dev_attr_fm_port_qmi_regs) != 0) -+ return -EIO; -+ if (device_create_file(dev, &dev_attr_fm_port_bmi_regs) != 0) -+ return -EIO; -+#if (DPAA_VERSION >= 11) -+ if (device_create_file(dev, &dev_attr_fm_port_ipv4_opt) != 0) -+ return -EIO; -+#endif -+ if (device_create_file(dev, &dev_attr_fm_port_dsar_regs) != 0) -+ return -EIO; -+ if (device_create_file(dev, &dev_attr_fm_port_dsar_mem) != 0) -+ return -EIO; -+ -+ /* FM Ports statistics */ -+ switch (p_LnxWrpFmPortDev->settings.param.portType) { -+ case e_FM_PORT_TYPE_TX: -+ case e_FM_PORT_TYPE_TX_10G: -+ if (sysfs_create_group -+ (&dev->kobj, &fm_tx_port_dev_stats_attr_grp) != 0) -+ return -EIO; -+ break; -+ case e_FM_PORT_TYPE_RX: -+ case e_FM_PORT_TYPE_RX_10G: -+ if (sysfs_create_group -+ (&dev->kobj, &fm_rx_port_dev_stats_attr_grp) != 0) -+ return -EIO; -+ break; -+ case e_FM_PORT_TYPE_DUMMY: -+ case e_FM_PORT_TYPE_OH_OFFLINE_PARSING: -+ if (sysfs_create_group -+ (&dev->kobj, &fm_oh_port_dev_stats_attr_grp) != 0) -+ return -EIO; -+ break; -+ default: -+ WARN(1, "FMD: failure at %s:%d/%s()!\n", __FILE__, __LINE__, -+ __func__); -+ return -EINVAL; -+ break; -+ }; -+ -+ return 0; -+} -+ -+void fm_port_sysfs_destroy(struct device *dev) -+{ -+ t_LnxWrpFmPortDev *p_LnxWrpFmPortDev = NULL; -+ -+ /* this function has never been tested !!! */ -+ -+ if (WARN_ON(dev == NULL)) -+ return; -+ -+ p_LnxWrpFmPortDev = (t_LnxWrpFmPortDev *) dev_get_drvdata(dev); -+ if (WARN_ON(p_LnxWrpFmPortDev == NULL)) -+ return; -+ -+ /* The name attribute will be freed also by these 2 functions? */ -+ switch (p_LnxWrpFmPortDev->settings.param.portType) { -+ case e_FM_PORT_TYPE_TX: -+ case e_FM_PORT_TYPE_TX_10G: -+ sysfs_remove_group(&dev->kobj, &fm_tx_port_dev_stats_attr_grp); -+ break; -+ case e_FM_PORT_TYPE_RX: -+ case e_FM_PORT_TYPE_RX_10G: -+ sysfs_remove_group(&dev->kobj, &fm_rx_port_dev_stats_attr_grp); -+ break; -+ case e_FM_PORT_TYPE_DUMMY: -+ case e_FM_PORT_TYPE_OH_OFFLINE_PARSING: -+ sysfs_remove_group(&dev->kobj, &fm_oh_port_dev_stats_attr_grp); -+ break; -+ default: -+ WARN(1, "FMD: failure at %s:%d/%s()!\n", __FILE__, __LINE__, -+ __func__); -+ break; -+ }; -+ -+ device_remove_file(dev, p_LnxWrpFmPortDev->dev_attr_regs); -+ device_remove_file(dev, p_LnxWrpFmPortDev->dev_attr_qmi_regs); -+ device_remove_file(dev, p_LnxWrpFmPortDev->dev_attr_bmi_regs); -+#if (DPAA_VERSION >= 11) -+ device_remove_file(dev, p_LnxWrpFmPortDev->dev_attr_ipv4_opt); -+#endif -+ device_remove_file(dev, p_LnxWrpFmPortDev->dev_attr_dsar_regs); -+ device_remove_file(dev, p_LnxWrpFmPortDev->dev_attr_dsar_mem); -+} -+ -+ -+int fm_port_dump_regs(void *h_dev, char *buf, int nn) -+{ -+ t_FmPort *p_FmPort; -+ t_Fm *p_Fm; -+ uint8_t hardwarePortId; -+ int n = nn; -+ -+ p_FmPort = (t_FmPort *)h_dev; -+ hardwarePortId = p_FmPort->hardwarePortId; -+ p_Fm = (t_Fm *)p_FmPort->h_Fm; -+ -+ FM_DMP_TITLE(buf, n, &p_Fm->p_FmBmiRegs->fmbm_pp[hardwarePortId - 1], -+ "fmbm_pp for port %u", hardwarePortId); -+ FM_DMP_MEM_32(buf, n, -+ &p_Fm->p_FmBmiRegs->fmbm_pp[hardwarePortId - 1]); -+ -+ FM_DMP_TITLE(buf, n, &p_Fm->p_FmBmiRegs->fmbm_pfs[hardwarePortId - 1], -+ "fmbm_pfs for port %u", hardwarePortId); -+ FM_DMP_MEM_32(buf, n, -+ &p_Fm->p_FmBmiRegs->fmbm_pfs[hardwarePortId - 1]); -+ -+ FM_DMP_TITLE(buf, n, -+ &p_Fm->p_FmBmiRegs->fmbm_spliodn[hardwarePortId - 1], -+ "fmbm_spliodn for port %u", hardwarePortId); -+ FM_DMP_MEM_32(buf, n, -+ &p_Fm->p_FmBmiRegs->fmbm_spliodn[hardwarePortId - 1]); -+ -+ FM_DMP_TITLE(buf, n, &p_Fm->p_FmFpmRegs->fmfp_ps[hardwarePortId], -+ "fmfp_psfor port %u", hardwarePortId); -+ FM_DMP_MEM_32(buf, n, &p_Fm->p_FmFpmRegs->fmfp_ps[hardwarePortId]); -+ -+ FM_DMP_TITLE(buf, n, &p_Fm->p_FmDmaRegs->fmdmplr[hardwarePortId / 2], -+ "fmdmplrfor port %u", hardwarePortId); -+ FM_DMP_MEM_32(buf, n, -+ &p_Fm->p_FmDmaRegs->fmdmplr[hardwarePortId / 2]); -+ return n; -+} -+ -+#if (DPAA_VERSION >= 11) -+ -+int fm_port_dump_ipv4_opt(void *h_dev, char *buf, int nn) -+{ -+ t_FmPort *p_FmPort; -+ int n = nn; -+ -+ p_FmPort = (t_FmPort *)h_dev; -+ -+ FM_DMP_V32(buf, n, p_FmPort->p_ParamsPage, ipfOptionsCounter); -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ -+ return n; -+} -+#endif -+ -+int fm_port_dump_regs_bmi(void *h_dev, char *buf, int nn) -+{ -+ t_FmPort *p_FmPort; -+ u_FmPortBmiRegs *p_bmi; -+ -+ char arr[20]; -+ uint8_t flag; -+ int i = 0; -+ int n = nn; -+ -+ p_FmPort = (t_FmPort *)h_dev; -+ p_bmi = p_FmPort->p_FmPortBmiRegs; -+ -+ memset(arr, 0, sizeof(arr)); -+ switch (p_FmPort->portType) { -+ case (e_FM_PORT_TYPE_OH_OFFLINE_PARSING): -+ strcpy(arr, "OFFLINE-PARSING"); -+ flag = 0; -+ break; -+ case (e_FM_PORT_TYPE_OH_HOST_COMMAND): -+ strcpy(arr, "HOST-COMMAND"); -+ flag = 0; -+ break; -+ case (e_FM_PORT_TYPE_RX): -+ strcpy(arr, "RX"); -+ flag = 1; -+ break; -+ case (e_FM_PORT_TYPE_RX_10G): -+ strcpy(arr, "RX-10G"); -+ flag = 1; -+ break; -+ case (e_FM_PORT_TYPE_TX): -+ strcpy(arr, "TX"); -+ flag = 2; -+ break; -+ case (e_FM_PORT_TYPE_TX_10G): -+ strcpy(arr, "TX-10G"); -+ flag = 2; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ FM_DMP_TITLE(buf, n, NULL, -+ "FMan-Port (%s #%d) registers:", -+ arr, p_FmPort->portId); -+ -+ FM_DMP_TITLE(buf, n, p_bmi, "Bmi Port Regs"); -+ -+ switch (flag) { -+ case (0): -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ocfg); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ost); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_oda); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_oicp); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofdne); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofne); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofca); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofpne); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_opso); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_opp); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_occb); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_oim); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofp); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofed); -+ -+ FM_DMP_TITLE(buf, n, -+ &(p_bmi->ohPortBmiRegs.fmbm_oprai), "fmbm_oprai"); -+ for (i = 0; i < FM_PORT_PRS_RESULT_NUM_OF_WORDS; ++i) { -+ FM_DMP_MEM_32(buf, n, -+ &(p_bmi->ohPortBmiRegs.fmbm_oprai[i])); -+ } -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofqid); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_oefqid); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofsdm); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofsem); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofene); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_orlmts); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_orlmt); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ocmne); -+ { -+#ifndef FM_NO_OP_OBSERVED_POOLS -+ if (p_FmPort->fmRevInfo.majorRev == 4) { -+ FM_DMP_TITLE(buf, n, -+ &p_bmi->ohPortBmiRegs.fmbm_oebmpi, -+ "fmbm_oebmpi"); -+ -+ for (i = 0; i < FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS; ++i) { -+ FM_DMP_MEM_32(buf, n, -+ &(p_bmi->ohPortBmiRegs.fmbm_oebmpi[i])); -+ } -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ocgm); -+ } -+#endif /* !FM_NO_OP_OBSERVED_POOLS */ -+ } -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ostc); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofrc); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofdc); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofledc); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofufdc); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_offc); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofwdc); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofldec); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_opc); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_opcp); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_occn); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_otuc); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_oduc); -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ofuc); -+ FM_DMP_TITLE(buf, n, &(p_bmi->ohPortBmiRegs.fmbm_odcfg), -+ "fmbm_odcfg"); -+ for (i = 0; i < 3; ++i) { -+ FM_DMP_MEM_32(buf, n, -+ &(p_bmi->ohPortBmiRegs.fmbm_odcfg[i])); -+ } -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ -+ FM_DMP_V32(buf, n, &p_bmi->ohPortBmiRegs, fmbm_ogpr); -+ break; -+ case (1): -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rcfg); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rst); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rda); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfp); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_reth); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfed); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_ricp); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rebm); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfne); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfca); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfpne); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rpso); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rpp); -+ FM_DMP_TITLE(buf, n, &(p_bmi->rxPortBmiRegs.fmbm_rprai), -+ "fmbm_rprai"); -+ for (i = 0; i < FM_PORT_PRS_RESULT_NUM_OF_WORDS; ++i) { -+ FM_DMP_MEM_32(buf, n, -+ &(p_bmi->rxPortBmiRegs.fmbm_rprai[i])); -+ } -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfqid); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_refqid); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfsdm); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfsem); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfene); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rcmne); -+ FM_DMP_TITLE(buf, n, &p_bmi->rxPortBmiRegs.fmbm_ebmpi, -+ "fmbm_ebmpi"); -+ for (i = 0; i < FM_PORT_MAX_NUM_OF_EXT_POOLS; ++i) { -+ FM_DMP_MEM_32(buf, n, -+ &(p_bmi->rxPortBmiRegs.fmbm_ebmpi[i])); -+ } -+ FM_DMP_TITLE(buf, n, &p_bmi->rxPortBmiRegs.fmbm_acnt, -+ "fmbm_acnt"); -+ for (i = 0; i < FM_PORT_MAX_NUM_OF_EXT_POOLS; ++i) { -+ FM_DMP_MEM_32(buf, n, -+ &(p_bmi->rxPortBmiRegs.fmbm_acnt[i])); -+ } -+ FM_DMP_TITLE(buf, n, &p_bmi->rxPortBmiRegs.fmbm_rcgm, -+ "fmbm_rcgm"); -+ for (i = 0; i < FM_PORT_NUM_OF_CONGESTION_GRPS / 32; ++i) { -+ FM_DMP_MEM_32(buf, n, -+ &(p_bmi->rxPortBmiRegs.fmbm_rcgm[i])); -+ } -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rmpd); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rstc); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfrc); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfbc); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rlfc); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rffc); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfcd); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfldec); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rodc); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rpc); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rpcp); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rccn); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rtuc); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rrquc); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rduc); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rfuc); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rpac); -+ FM_DMP_TITLE(buf, n, &(p_bmi->rxPortBmiRegs.fmbm_rdcfg), -+ "fmbm_rdcfg"); -+ for (i = 0; i < 3; ++i) { -+ FM_DMP_MEM_32(buf, n, -+ &(p_bmi->rxPortBmiRegs.fmbm_rdcfg[i])); -+ } -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_V32(buf, n, &p_bmi->rxPortBmiRegs, fmbm_rgpr); -+ break; -+ case (2): -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tcfg); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tst); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tda); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tfp); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tfed); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_ticp); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tfdne); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tfca); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tcfqid); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tfeqid); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tfene); -+#if (DPAA_VERSION >= 11) -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tfne); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tcmne); -+#endif /* (DPAA_VERSION >= 11) */ -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_trlmts); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_trlmt); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tstc); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tfrc); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tfdc); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tfledc); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tfufdc); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tpc); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tpcp); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tccn); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_ttuc); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_ttcquc); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tduc); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tfuc); -+ FM_DMP_TITLE(buf, n, &(p_bmi->txPortBmiRegs.fmbm_tdcfg), -+ "fmbm_tdcfg"); -+ for (i = 0; i < 3 ; ++i) { -+ FM_DMP_MEM_32(buf, n, -+ &(p_bmi->txPortBmiRegs.fmbm_tdcfg[i])); -+ } -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_V32(buf, n, &p_bmi->txPortBmiRegs, fmbm_tgpr); -+ break; -+ } -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ -+ return n; -+} -+ -+int fm_port_dump_regs_qmi(void *h_dev, char *buf, int nn) -+{ -+ t_FmPort *p_FmPort; -+ int n = nn; -+ -+ p_FmPort = (t_FmPort *)h_dev; -+ -+ FM_DMP_TITLE(buf, n, p_FmPort->p_FmPortQmiRegs, "Qmi Port Regs"); -+ -+ FM_DMP_V32(buf, n, p_FmPort->p_FmPortQmiRegs, fmqm_pnc); -+ FM_DMP_V32(buf, n, p_FmPort->p_FmPortQmiRegs, fmqm_pns); -+ FM_DMP_V32(buf, n, p_FmPort->p_FmPortQmiRegs, fmqm_pnts); -+ FM_DMP_V32(buf, n, p_FmPort->p_FmPortQmiRegs, fmqm_pnen); -+ FM_DMP_V32(buf, n, p_FmPort->p_FmPortQmiRegs, fmqm_pnetfc); -+ FM_DMP_V32(buf, n, -+ &p_FmPort->p_FmPortQmiRegs->nonRxQmiRegs, fmqm_pndn); -+ FM_DMP_V32(buf, n, -+ &p_FmPort->p_FmPortQmiRegs->nonRxQmiRegs, fmqm_pndc); -+ FM_DMP_V32(buf, n, -+ &p_FmPort->p_FmPortQmiRegs->nonRxQmiRegs, fmqm_pndtfc); -+ FM_DMP_V32(buf, n, -+ &p_FmPort->p_FmPortQmiRegs->nonRxQmiRegs, fmqm_pndfdc); -+ FM_DMP_V32(buf, n, -+ &p_FmPort->p_FmPortQmiRegs->nonRxQmiRegs, fmqm_pndcc); -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ -+ return n; -+} -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_sysfs_fm_port.h -@@ -0,0 +1,56 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ @File lnxwrp_sysfs_fm_port.h -+ -+ @Description FM port sysfs functions. -+ -+*/ -+ -+#ifndef LNXWRP_SYSFS_FM_PORT_H_ -+#define LNXWRP_SYSFS_FM_PORT_H_ -+ -+#include "lnxwrp_sysfs.h" -+ -+int fm_port_sysfs_create(struct device *dev); -+void fm_port_sysfs_destroy(struct device *dev); -+ -+int fm_port_dump_regs(void *h_dev, char *buf, int n); -+int fm_port_dump_regs_bmi(void *h_dev, char *buf, int n); -+int fm_port_dump_regs_qmi(void *h_dev, char *buf, int n); -+ -+#if (DPAA_VERSION >= 11) -+int fm_port_dump_ipv4_opt(void *h_dev, char *buf, int n); -+#endif -+ -+#endif /* LNXWRP_SYSFS_FM_PORT_H_ */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/xx/Makefile -@@ -0,0 +1,18 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+#Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+ -+obj-y += fsl-ncsw-xx.o -+ -+ifneq ($(CONFIG_FMAN_ARM),y) -+fsl-ncsw-xx-objs := xx_linux.o udivdi3.o \ -+ module_strings.o -+else -+fsl-ncsw-xx-objs := xx_arm_linux.o udivdi3.o \ -+ module_strings.o -+endif -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/xx/module_strings.c -@@ -0,0 +1,45 @@ -+/* -+ * Copyright 2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* Module names for debug messages */ -+const char *moduleStrings[] = -+{ -+ "", /* MODULE_UNKNOWN */ -+ "FM", /* MODULE_FM */ -+ "FM-MURAM", /* MODULE_FM_MURAM */ -+ "FM-PCD", /* MODULE_FM_PCD */ -+ "FM-RTC", /* MODULE_FM_RTC */ -+ "FM-MAC", /* MODULE_FM_MAC */ -+ "FM-Port", /* MODULE_FM_PORT */ -+ "MM", /* MODULE_MM */ -+ "FM-SP" /* MODULE_FM_SP */ -+}; ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/xx/udivdi3.c -@@ -0,0 +1,132 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+ -+#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS) -+#define MODVERSIONS -+#endif -+#ifdef MODVERSIONS -+#include -+#endif /* MODVERSIONS */ -+ -+#include -+#include -+#include -+ -+ -+#define BITS_PER_UNIT 8 -+#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT) -+ -+ -+typedef unsigned int UQItype __attribute__ ((mode (QI))); -+typedef int SItype __attribute__ ((mode (SI))); -+typedef unsigned int USItype __attribute__ ((mode (SI))); -+typedef int DItype __attribute__ ((mode (DI))); -+typedef int word_type __attribute__ ((mode (__word__))); -+typedef unsigned int UDItype __attribute__ ((mode (DI))); -+ -+struct DIstruct {SItype low, high;}; -+ -+typedef union -+{ -+ struct DIstruct s; -+ DItype ll; -+} DIunion; -+ -+ -+/* bit divisor, dividend and result. dynamic precision */ -+static __inline__ uint64_t _div64_64(uint64_t dividend, uint64_t divisor) -+{ -+ uint32_t d = divisor; -+ -+ if (divisor > 0xffffffffULL) -+ { -+ unsigned int shift = fls(divisor >> 32); -+ -+ d = divisor >> shift; -+ dividend >>= shift; -+ } -+ -+ /* avoid 64 bit division if possible */ -+ if (dividend >> 32) -+ do_div(dividend, d); -+ else -+ dividend = (uint32_t) dividend / d; -+ -+ return dividend; -+} -+ -+UDItype __udivdi3 (UDItype n, UDItype d) -+{ -+ return _div64_64(n, d); -+} -+ -+DItype __divdi3 (DItype n, DItype d) -+{ -+ DItype sign = 1; -+ if (n<0) -+ { -+ sign *= -1; -+ n *= -1; -+ } -+ if (d<0) -+ { -+ sign *= -1; -+ d *= -1; -+ } -+ return sign*_div64_64((UDItype)n, (UDItype)d); -+} -+ -+UDItype __umoddi3 (UDItype n, UDItype d) -+{ -+ return n-(_div64_64(n, d)*d); -+} -+ -+#ifdef MODULE -+word_type __ucmpdi2 (DItype a, DItype b) -+{ -+ DIunion au, bu; -+ -+ au.ll = a, bu.ll = b; -+ -+ if ((USItype) au.s.high < (USItype) bu.s.high) -+ return 0; -+ else if ((USItype) au.s.high > (USItype) bu.s.high) -+ return 2; -+ if ((USItype) au.s.low < (USItype) bu.s.low) -+ return 0; -+ else if ((USItype) au.s.low > (USItype) bu.s.low) -+ return 2; -+ return 1; -+} -+#endif /* MODULE */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/xx/xx_arm_linux.c -@@ -0,0 +1,905 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ @File xx_arm_linux.c -+ -+ @Description XX routines implementation for Linux. -+*//***************************************************************************/ -+#include -+ -+#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS) -+#define MODVERSIONS -+#endif -+#ifdef MODVERSIONS -+#include -+#endif /* MODVERSIONS */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#ifdef BIGPHYSAREA_ENABLE -+#include -+#endif /* BIGPHYSAREA_ENABLE */ -+ -+//#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "list_ext.h" -+#include "mm_ext.h" -+#include "sys_io_ext.h" -+#include "xx.h" -+ -+ -+#define __ERR_MODULE__ MODULE_UNKNOWN -+ -+#ifdef BIGPHYSAREA_ENABLE -+#define MAX_ALLOCATION_SIZE 128 * 1024 /* Maximum size allocated with kmalloc is 128K */ -+ -+ -+/* TODO: large allocations => use big phys area */ -+/****************************************************************************** -+ * routine: get_nr_pages -+ * -+ * description: -+ * calculates the number of memory pages for a given size (in bytes) -+ * -+ * arguments: -+ * size - the number of bytes -+ * -+ * return code: -+ * The number of pages -+ * -+ *****************************************************************************/ -+static __inline__ uint32_t get_nr_pages (uint32_t size) -+{ -+ return (uint32_t)((size >> PAGE_SHIFT) + (size & PAGE_SHIFT ? 1 : 0)); -+} -+ -+static bool in_big_phys_area (uint32_t addr) -+{ -+ uint32_t base, size; -+ -+ bigphysarea_get_details (&base, &size); -+ return ((addr >= base) && (addr < base + size)); -+} -+#endif /* BIGPHYSAREA_ENABLE */ -+ -+void * xx_Malloc(uint32_t n) -+{ -+ void *a; -+ uint32_t flags; -+ -+ flags = XX_DisableAllIntr(); -+#ifdef BIGPHYSAREA_ENABLE -+ if (n >= MAX_ALLOCATION_SIZE) -+ a = (void*)bigphysarea_alloc_pages(get_nr_pages(n), 0, GFP_ATOMIC); -+ else -+#endif /* BIGPHYSAREA_ENABLE */ -+ a = (void *)kmalloc((uint32_t)n, GFP_ATOMIC); -+ if (!a) -+ XX_Print("No memory for XX_Malloc\n"); -+ XX_RestoreAllIntr(flags); -+ -+ return a; -+} -+ -+void xx_Free(void *p) -+{ -+#ifdef BIGPHYSAREA_ENABLE -+ if (in_big_phys_area ((uint32_t)p)) -+ bigphysarea_free_pages(p); -+ else -+#endif /* BIGPHYSAREA_ENABLE */ -+ kfree(p); -+} -+ -+void XX_Exit(int status) -+{ -+ WARN(1, "\n\nFMD: fatal error, driver can't go on!!!\n\n"); -+} -+ -+#define BUF_SIZE 512 -+void XX_Print(char *str, ...) -+{ -+ va_list args; -+#ifdef CONFIG_SMP -+ char buf[BUF_SIZE]; -+#endif /* CONFIG_SMP */ -+ -+ va_start(args, str); -+#ifdef CONFIG_SMP -+ if (vsnprintf (buf, BUF_SIZE, str, args) >= BUF_SIZE) -+ printk(KERN_WARNING "Illegal string to print!\n more than %d characters.\n\tString was not printed completelly.\n", BUF_SIZE); -+ printk(KERN_CRIT "cpu %d: %s", raw_smp_processor_id(), buf); -+#else -+ vprintk(str, args); -+#endif /* CONFIG_SMP */ -+ va_end(args); -+} -+ -+void XX_Fprint(void *file, char *str, ...) -+{ -+ va_list args; -+#ifdef CONFIG_SMP -+ char buf[BUF_SIZE]; -+#endif /* CONFIG_SMP */ -+ -+ va_start(args, str); -+#ifdef CONFIG_SMP -+ if (vsnprintf (buf, BUF_SIZE, str, args) >= BUF_SIZE) -+ printk(KERN_WARNING "Illegal string to print!\n more than %d characters.\n\tString was not printed completelly.\n", BUF_SIZE); -+ printk (KERN_CRIT "cpu %d: %s", smp_processor_id(), buf); -+ -+#else -+ vprintk(str, args); -+#endif /* CONFIG_SMP */ -+ va_end(args); -+} -+ -+#ifdef DEBUG_XX_MALLOC -+typedef void (*t_ffn)(void *); -+typedef struct { -+ t_ffn f_free; -+ void *mem; -+ char *fname; -+ int fline; -+ uint32_t size; -+ t_List node; -+} t_MemDebug; -+#define MEMDBG_OBJECT(p_List) LIST_OBJECT(p_List, t_MemDebug, node) -+ -+LIST(memDbgLst); -+ -+ -+void * XX_MallocDebug(uint32_t size, char *fname, int line) -+{ -+ void *mem; -+ t_MemDebug *p_MemDbg; -+ -+ p_MemDbg = (t_MemDebug *)xx_Malloc(sizeof(t_MemDebug)); -+ if (p_MemDbg == NULL) -+ return NULL; -+ -+ mem = xx_Malloc(size); -+ if (mem == NULL) -+ { -+ XX_Free(p_MemDbg); -+ return NULL; -+ } -+ -+ INIT_LIST(&p_MemDbg->node); -+ p_MemDbg->f_free = xx_Free; -+ p_MemDbg->mem = mem; -+ p_MemDbg->fname = fname; -+ p_MemDbg->fline = line; -+ p_MemDbg->size = size+sizeof(t_MemDebug); -+ LIST_AddToTail(&p_MemDbg->node, &memDbgLst); -+ -+ return mem; -+} -+ -+void * XX_MallocSmartDebug(uint32_t size, -+ int memPartitionId, -+ uint32_t align, -+ char *fname, -+ int line) -+{ -+ void *mem; -+ t_MemDebug *p_MemDbg; -+ -+ p_MemDbg = (t_MemDebug *)XX_Malloc(sizeof(t_MemDebug)); -+ if (p_MemDbg == NULL) -+ return NULL; -+ -+ mem = xx_MallocSmart((uint32_t)size, memPartitionId, align); -+ if (mem == NULL) -+ { -+ XX_Free(p_MemDbg); -+ return NULL; -+ } -+ -+ INIT_LIST(&p_MemDbg->node); -+ p_MemDbg->f_free = xx_FreeSmart; -+ p_MemDbg->mem = mem; -+ p_MemDbg->fname = fname; -+ p_MemDbg->fline = line; -+ p_MemDbg->size = size+sizeof(t_MemDebug); -+ LIST_AddToTail(&p_MemDbg->node, &memDbgLst); -+ -+ return mem; -+} -+ -+static void debug_free(void *mem) -+{ -+ t_List *p_MemDbgLh = NULL; -+ t_MemDebug *p_MemDbg; -+ bool found = FALSE; -+ -+ if (LIST_IsEmpty(&memDbgLst)) -+ { -+ REPORT_ERROR(MAJOR, E_ALREADY_FREE, ("Unbalanced free (0x%08x)", mem)); -+ return; -+ } -+ -+ LIST_FOR_EACH(p_MemDbgLh, &memDbgLst) -+ { -+ p_MemDbg = MEMDBG_OBJECT(p_MemDbgLh); -+ if (p_MemDbg->mem == mem) -+ { -+ found = TRUE; -+ break; -+ } -+ } -+ -+ if (!found) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_FOUND, -+ ("Attempt to free unallocated address (0x%08x)",mem)); -+ dump_stack(); -+ return; -+ } -+ -+ LIST_Del(p_MemDbgLh); -+ p_MemDbg->f_free(mem); -+ p_MemDbg->f_free(p_MemDbg); -+} -+ -+void XX_FreeSmart(void *p) -+{ -+ debug_free(p); -+} -+ -+ -+void XX_Free(void *p) -+{ -+ debug_free(p); -+} -+ -+#else /* not DEBUG_XX_MALLOC */ -+void * XX_Malloc(uint32_t size) -+{ -+ return xx_Malloc(size); -+} -+ -+void * XX_MallocSmart(uint32_t size, int memPartitionId, uint32_t alignment) -+{ -+ return xx_MallocSmart(size,memPartitionId, alignment); -+} -+ -+void XX_FreeSmart(void *p) -+{ -+ xx_FreeSmart(p); -+} -+ -+ -+void XX_Free(void *p) -+{ -+ xx_Free(p); -+} -+#endif /* not DEBUG_XX_MALLOC */ -+ -+ -+#if (defined(REPORT_EVENTS) && (REPORT_EVENTS > 0)) -+void XX_EventById(uint32_t event, t_Handle appId, uint16_t flags, char *msg) -+{ -+ e_Event eventCode = (e_Event)event; -+ -+ UNUSED(eventCode); -+ UNUSED(appId); -+ UNUSED(flags); -+ UNUSED(msg); -+} -+#endif /* (defined(REPORT_EVENTS) && ... */ -+ -+ -+uint32_t XX_DisableAllIntr(void) -+{ -+ unsigned long flags; -+ -+#ifdef local_irq_save_nort -+ local_irq_save_nort(flags); -+#else -+ local_irq_save(flags); -+#endif -+ -+ return (uint32_t)flags; -+} -+ -+void XX_RestoreAllIntr(uint32_t flags) -+{ -+#ifdef local_irq_restore_nort -+ local_irq_restore_nort((unsigned long)flags); -+#else -+ local_irq_restore((unsigned long)flags); -+#endif -+} -+ -+t_Error XX_Call( uint32_t qid, t_Error (* f)(t_Handle), t_Handle id, t_Handle appId, uint16_t flags ) -+{ -+ UNUSED(qid); -+ UNUSED(appId); -+ UNUSED(flags); -+ -+ return f(id); -+} -+ -+int XX_IsICacheEnable(void) -+{ -+ return TRUE; -+} -+ -+int XX_IsDCacheEnable(void) -+{ -+ return TRUE; -+} -+ -+ -+typedef struct { -+ t_Isr *f_Isr; -+ t_Handle handle; -+} t_InterruptHandler; -+ -+ -+t_Handle interruptHandlers[0x00010000]; -+ -+static irqreturn_t LinuxInterruptHandler (int irq, void *dev_id) -+{ -+ t_InterruptHandler *p_IntrHndl = (t_InterruptHandler *)dev_id; -+ p_IntrHndl->f_Isr(p_IntrHndl->handle); -+ return IRQ_HANDLED; -+} -+ -+t_Error XX_SetIntr(int irq, t_Isr *f_Isr, t_Handle handle) -+{ -+ const char *device; -+ t_InterruptHandler *p_IntrHndl; -+ -+ device = GetDeviceName(irq); -+ if (device == NULL) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Interrupt source - %d", irq)); -+ -+ p_IntrHndl = (t_InterruptHandler *)XX_Malloc(sizeof(t_InterruptHandler)); -+ if (p_IntrHndl == NULL) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ p_IntrHndl->f_Isr = f_Isr; -+ p_IntrHndl->handle = handle; -+ interruptHandlers[irq] = p_IntrHndl; -+ -+ if (request_irq(GetDeviceIrqNum(irq), LinuxInterruptHandler, 0, device, p_IntrHndl) < 0) -+ RETURN_ERROR(MAJOR, E_BUSY, ("Can't get IRQ %s\n", device)); -+ disable_irq(GetDeviceIrqNum(irq)); -+ -+ return E_OK; -+} -+ -+t_Error XX_FreeIntr(int irq) -+{ -+ t_InterruptHandler *p_IntrHndl = interruptHandlers[irq]; -+ free_irq(GetDeviceIrqNum(irq), p_IntrHndl); -+ XX_Free(p_IntrHndl); -+ interruptHandlers[irq] = 0; -+ return E_OK; -+} -+ -+t_Error XX_EnableIntr(int irq) -+{ -+ enable_irq(GetDeviceIrqNum(irq)); -+ return E_OK; -+} -+ -+t_Error XX_DisableIntr(int irq) -+{ -+ disable_irq(GetDeviceIrqNum(irq)); -+ return E_OK; -+} -+ -+ -+/*****************************************************************************/ -+/* Tasklet Service Routines */ -+/*****************************************************************************/ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+typedef struct -+{ -+ t_Handle h_Data; -+ void (*f_Callback) (void *); -+ struct delayed_work dwork; -+} t_Tasklet; -+ -+static void GenericTaskletCallback(struct work_struct *p_Work) -+{ -+ t_Tasklet *p_Task = container_of(p_Work, t_Tasklet, dwork.work); -+ -+ p_Task->f_Callback(p_Task->h_Data); -+} -+#endif /* LINUX_VERSION_CODE */ -+ -+ -+t_TaskletHandle XX_InitTasklet (void (*routine)(void *), void *data) -+{ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ struct work_struct *p_Task; -+ p_Task = (struct work_struct *)XX_Malloc(sizeof(struct work_struct)); -+ INIT_WORK(p_Task, routine, data); -+#else -+ t_Tasklet *p_Task = (t_Tasklet *)XX_Malloc(sizeof(t_Tasklet)); -+ p_Task->h_Data = data; -+ p_Task->f_Callback = routine; -+ INIT_DELAYED_WORK(&p_Task->dwork, GenericTaskletCallback); -+#endif /* LINUX_VERSION_CODE */ -+ -+ return (t_TaskletHandle)p_Task; -+} -+ -+ -+void XX_FreeTasklet (t_TaskletHandle h_Tasklet) -+{ -+ if (h_Tasklet) -+ XX_Free(h_Tasklet); -+} -+ -+int XX_ScheduleTask(t_TaskletHandle h_Tasklet, int immediate) -+{ -+ int ans; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ if (immediate) -+ ans = schedule_work(h_Tasklet); -+ else -+ ans = schedule_delayed_work(h_Tasklet, 1); -+#else -+ if (immediate) -+ ans = schedule_delayed_work(&((t_Tasklet *)h_Tasklet)->dwork, 0); -+ else -+ ans = schedule_delayed_work(&((t_Tasklet *)h_Tasklet)->dwork, HZ); -+#endif /* LINUX_VERSION_CODE */ -+ -+ return ans; -+} -+ -+void XX_FlushScheduledTasks(void) -+{ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ flush_scheduled_tasks(); -+#else -+ flush_scheduled_work(); -+#endif /* LINUX_VERSION_CODE */ -+} -+ -+int XX_TaskletIsQueued(t_TaskletHandle h_Tasklet) -+{ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ return (int)(((struct work_struct *)h_Tasklet)->pending); -+#else -+ return (int)delayed_work_pending(&((t_Tasklet *)h_Tasklet)->dwork); -+#endif /* LINUX_VERSION_CODE */ -+} -+ -+void XX_SetTaskletData(t_TaskletHandle h_Tasklet, t_Handle data) -+{ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ ((struct tq_struct *)h_Tasklet)->data = data; -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ ((struct work_struct *)h_Tasklet)->data = data; -+#else -+ ((t_Tasklet *)h_Tasklet)->h_Data = data; -+#endif /* LINUX_VERSION_CODE */ -+} -+ -+t_Handle XX_GetTaskletData(t_TaskletHandle h_Tasklet) -+{ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ return (t_Handle)(((struct work_struct *)h_Tasklet)->data); -+#else -+ return ((t_Tasklet *)h_Tasklet)->h_Data; -+#endif /* LINUX_VERSION_CODE */ -+} -+ -+ -+/*****************************************************************************/ -+/* Spinlock Service Routines */ -+/*****************************************************************************/ -+ -+t_Handle XX_InitSpinlock(void) -+{ -+ spinlock_t *p_Spinlock = (spinlock_t *)XX_Malloc(sizeof(spinlock_t)); -+ if (!p_Spinlock) -+ return NULL; -+ -+ spin_lock_init(p_Spinlock); -+ -+ return (t_Handle)p_Spinlock; -+} -+ -+void XX_FreeSpinlock(t_Handle h_Spinlock) -+{ -+ if (h_Spinlock) -+ XX_Free(h_Spinlock); -+} -+ -+void XX_LockSpinlock(t_Handle h_Spinlock) -+{ -+ spin_lock((spinlock_t *)h_Spinlock); -+} -+ -+void XX_UnlockSpinlock(t_Handle h_Spinlock) -+{ -+ spin_unlock((spinlock_t *)h_Spinlock); -+} -+ -+uint32_t XX_LockIntrSpinlock(t_Handle h_Spinlock) -+{ -+ unsigned long intrFlags; -+ spin_lock_irqsave((spinlock_t *)h_Spinlock, intrFlags); -+ return intrFlags; -+} -+ -+void XX_UnlockIntrSpinlock(t_Handle h_Spinlock, uint32_t intrFlags) -+{ -+ spin_unlock_irqrestore((spinlock_t *)h_Spinlock, (unsigned long)intrFlags); -+} -+ -+ -+/*****************************************************************************/ -+/* Timers Service Routines */ -+/*****************************************************************************/ -+/* The time now is in mili sec. resolution */ -+uint32_t XX_CurrentTime(void) -+{ -+ return (jiffies*1000)/HZ; -+} -+ -+ -+t_Handle XX_CreateTimer(void) -+{ -+ struct timer_list *p_Timer = (struct timer_list *)XX_Malloc(sizeof(struct timer_list)); -+ if (p_Timer) -+ { -+ memset(p_Timer, 0, sizeof(struct timer_list)); -+ init_timer(p_Timer); -+ } -+ return (t_Handle)p_Timer; -+} -+ -+void XX_FreeTimer(t_Handle h_Timer) -+{ -+ if (h_Timer) -+ XX_Free(h_Timer); -+} -+ -+void XX_StartTimer(t_Handle h_Timer, -+ uint32_t msecs, -+ bool periodic, -+ void (*f_TimerExpired)(t_Handle), -+ t_Handle h_Arg) -+{ -+ int tmp_jiffies = (msecs*HZ)/1000; -+ struct timer_list *p_Timer = (struct timer_list *)h_Timer; -+ -+ SANITY_CHECK_RETURN((periodic == FALSE), E_NOT_SUPPORTED); -+ -+ p_Timer->function = (void (*)(unsigned long))f_TimerExpired; -+ p_Timer->data = (unsigned long)h_Arg; -+ if ((msecs*HZ)%1000) -+ tmp_jiffies++; -+ p_Timer->expires = (jiffies + tmp_jiffies); -+ -+ add_timer((struct timer_list *)h_Timer); -+} -+ -+void XX_SetTimerData(t_Handle h_Timer, t_Handle data) -+{ -+ struct timer_list *p_Timer = (struct timer_list *)h_Timer; -+ -+ p_Timer->data = (unsigned long)data; -+} -+ -+t_Handle XX_GetTimerData(t_Handle h_Timer) -+{ -+ struct timer_list *p_Timer = (struct timer_list *)h_Timer; -+ -+ return (t_Handle)p_Timer->data; -+} -+ -+uint32_t XX_GetExpirationTime(t_Handle h_Timer) -+{ -+ struct timer_list *p_Timer = (struct timer_list *)h_Timer; -+ -+ return (uint32_t)p_Timer->expires; -+} -+ -+void XX_StopTimer(t_Handle h_Timer) -+{ -+ del_timer((struct timer_list *)h_Timer); -+} -+ -+void XX_ModTimer(t_Handle h_Timer, uint32_t msecs) -+{ -+ int tmp_jiffies = (msecs*HZ)/1000; -+ -+ if ((msecs*HZ)%1000) -+ tmp_jiffies++; -+ mod_timer((struct timer_list *)h_Timer, jiffies + tmp_jiffies); -+} -+ -+int XX_TimerIsActive(t_Handle h_Timer) -+{ -+ return timer_pending((struct timer_list *)h_Timer); -+} -+ -+uint32_t XX_Sleep(uint32_t msecs) -+{ -+ int tmp_jiffies = (msecs*HZ)/1000; -+ -+ if ((msecs*HZ)%1000) -+ tmp_jiffies++; -+ return schedule_timeout(tmp_jiffies); -+} -+ -+/*BEWARE!!!!! UDelay routine is BUSY WAITTING!!!!!*/ -+void XX_UDelay(uint32_t usecs) -+{ -+ udelay(usecs); -+} -+ -+/* TODO: verify that these are correct */ -+#define MSG_BODY_SIZE 512 -+typedef t_Error (t_MsgHandler) (t_Handle h_Mod, uint32_t msgId, uint8_t msgBody[MSG_BODY_SIZE]); -+typedef void (t_MsgCompletionCB) (t_Handle h_Arg, uint8_t msgBody[MSG_BODY_SIZE]); -+t_Error XX_SendMessage(char *p_DestAddr, -+ uint32_t msgId, -+ uint8_t msgBody[MSG_BODY_SIZE], -+ t_MsgCompletionCB *f_CompletionCB, -+ t_Handle h_CBArg); -+ -+typedef struct { -+ char *p_Addr; -+ t_MsgHandler *f_MsgHandlerCB; -+ t_Handle h_Mod; -+ t_List node; -+} t_MsgHndlr; -+#define MSG_HNDLR_OBJECT(ptr) LIST_OBJECT(ptr, t_MsgHndlr, node) -+ -+LIST(msgHndlrList); -+ -+static void EnqueueMsgHndlr(t_MsgHndlr *p_MsgHndlr) -+{ -+ uint32_t intFlags; -+ -+ intFlags = XX_DisableAllIntr(); -+ LIST_AddToTail(&p_MsgHndlr->node, &msgHndlrList); -+ XX_RestoreAllIntr(intFlags); -+} -+/* TODO: add this for multi-platform support -+static t_MsgHndlr * DequeueMsgHndlr(void) -+{ -+ t_MsgHndlr *p_MsgHndlr = NULL; -+ uint32_t intFlags; -+ -+ intFlags = XX_DisableAllIntr(); -+ if (!LIST_IsEmpty(&msgHndlrList)) -+ { -+ p_MsgHndlr = MSG_HNDLR_OBJECT(msgHndlrList.p_Next); -+ LIST_DelAndInit(&p_MsgHndlr->node); -+ } -+ XX_RestoreAllIntr(intFlags); -+ -+ return p_MsgHndlr; -+} -+*/ -+static t_MsgHndlr * FindMsgHndlr(char *p_Addr) -+{ -+ t_MsgHndlr *p_MsgHndlr; -+ t_List *p_Pos; -+ -+ LIST_FOR_EACH(p_Pos, &msgHndlrList) -+ { -+ p_MsgHndlr = MSG_HNDLR_OBJECT(p_Pos); -+ if (strstr(p_MsgHndlr->p_Addr, p_Addr)) -+ return p_MsgHndlr; -+ } -+ -+ return NULL; -+} -+ -+t_Error XX_RegisterMessageHandler (char *p_Addr, t_MsgHandler *f_MsgHandlerCB, t_Handle h_Mod) -+{ -+ t_MsgHndlr *p_MsgHndlr; -+ uint32_t len; -+ -+ p_MsgHndlr = (t_MsgHndlr*)XX_Malloc(sizeof(t_MsgHndlr)); -+ if (!p_MsgHndlr) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("message handler object!!!")); -+ memset(p_MsgHndlr, 0, sizeof(t_MsgHndlr)); -+ -+ len = strlen(p_Addr); -+ p_MsgHndlr->p_Addr = (char*)XX_Malloc(len+1); -+ strncpy(p_MsgHndlr->p_Addr,p_Addr, (uint32_t)(len+1)); -+ -+ p_MsgHndlr->f_MsgHandlerCB = f_MsgHandlerCB; -+ p_MsgHndlr->h_Mod = h_Mod; -+ INIT_LIST(&p_MsgHndlr->node); -+ EnqueueMsgHndlr(p_MsgHndlr); -+ -+ return E_OK; -+} -+ -+t_Error XX_UnregisterMessageHandler (char *p_Addr) -+{ -+ t_MsgHndlr *p_MsgHndlr = FindMsgHndlr(p_Addr); -+ if (!p_MsgHndlr) -+ RETURN_ERROR(MINOR, E_NO_DEVICE, ("message handler not found in list!!!")); -+ -+ LIST_Del(&p_MsgHndlr->node); -+ XX_Free(p_MsgHndlr->p_Addr); -+ XX_Free(p_MsgHndlr); -+ -+ return E_OK; -+} -+ -+t_Error XX_SendMessage(char *p_DestAddr, -+ uint32_t msgId, -+ uint8_t msgBody[MSG_BODY_SIZE], -+ t_MsgCompletionCB *f_CompletionCB, -+ t_Handle h_CBArg) -+{ -+ t_Error ans; -+ t_MsgHndlr *p_MsgHndlr = FindMsgHndlr(p_DestAddr); -+ if (!p_MsgHndlr) -+ RETURN_ERROR(MINOR, E_NO_DEVICE, ("message handler not found in list!!!")); -+ -+ ans = p_MsgHndlr->f_MsgHandlerCB(p_MsgHndlr->h_Mod, msgId, msgBody); -+ -+ if (f_CompletionCB) -+ f_CompletionCB(h_CBArg, msgBody); -+ -+ return ans; -+} -+ -+t_Error XX_IpcRegisterMsgHandler(char addr[XX_IPC_MAX_ADDR_NAME_LENGTH], -+ t_IpcMsgHandler *f_MsgHandler, -+ t_Handle h_Module, -+ uint32_t replyLength) -+{ -+ UNUSED(addr);UNUSED(f_MsgHandler);UNUSED(h_Module);UNUSED(replyLength); -+ return E_OK; -+} -+ -+t_Error XX_IpcUnregisterMsgHandler(char addr[XX_IPC_MAX_ADDR_NAME_LENGTH]) -+{ -+ UNUSED(addr); -+ return E_OK; -+} -+ -+ -+t_Error XX_IpcSendMessage(t_Handle h_Session, -+ uint8_t *p_Msg, -+ uint32_t msgLength, -+ uint8_t *p_Reply, -+ uint32_t *p_ReplyLength, -+ t_IpcMsgCompletion *f_Completion, -+ t_Handle h_Arg) -+{ -+ UNUSED(h_Session); UNUSED(p_Msg); UNUSED(msgLength); UNUSED(p_Reply); -+ UNUSED(p_ReplyLength); UNUSED(f_Completion); UNUSED(h_Arg); -+ return E_OK; -+} -+ -+t_Handle XX_IpcInitSession(char destAddr[XX_IPC_MAX_ADDR_NAME_LENGTH], -+ char srcAddr[XX_IPC_MAX_ADDR_NAME_LENGTH]) -+{ -+ UNUSED(destAddr); UNUSED(srcAddr); -+ return E_OK; -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) -+int GetDeviceIrqNum(int irq) -+{ -+ struct device_node *iPar; -+ struct irq_domain *irqHost; -+ uint32_t hwIrq; -+ -+ /* Get the interrupt controller */ -+ iPar = of_find_node_by_name(NULL, "mpic"); -+ hwIrq = 0; -+ -+ ASSERT_COND(iPar != NULL); -+ /* Get the irq host */ -+ irqHost = irq_find_host(iPar); -+ of_node_put(iPar); -+ -+ /* Create irq mapping */ -+ return irq_create_mapping(irqHost, hwIrq); -+} -+#else -+#error "kernel not supported!!!" -+#endif /* LINUX_VERSION_CODE */ -+ -+void * XX_PhysToVirt(physAddress_t addr) -+{ -+ return UINT_TO_PTR(SYS_PhysToVirt((uint64_t)addr)); -+} -+ -+physAddress_t XX_VirtToPhys(void * addr) -+{ -+ return (physAddress_t)SYS_VirtToPhys(PTR_TO_UINT(addr)); -+} -+ -+void * xx_MallocSmart(uint32_t size, int memPartitionId, uint32_t alignment) -+{ -+ uintptr_t *returnCode, tmp; -+ -+ if (alignment < sizeof(uintptr_t)) -+ alignment = sizeof(uintptr_t); -+ size += alignment + sizeof(returnCode); -+ tmp = (uintptr_t)xx_Malloc(size); -+ if (tmp == 0) -+ return NULL; -+ returnCode = (uintptr_t*)((tmp + alignment + sizeof(returnCode)) & ~((uintptr_t)alignment - 1)); -+ *(returnCode - 1) = tmp; -+ -+ return (void*)returnCode; -+} -+ -+void xx_FreeSmart(void *p) -+{ -+ xx_Free((void*)(*((uintptr_t *)(p) - 1))); -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/xx/xx_linux.c -@@ -0,0 +1,918 @@ -+/* -+ * Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ @File xx_linux.c -+ -+ @Description XX routines implementation for Linux. -+*//***************************************************************************/ -+#include -+ -+#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS) -+#define MODVERSIONS -+#endif -+#ifdef MODVERSIONS -+#include -+#endif /* MODVERSIONS */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#ifdef CONFIG_FMAN_ARM -+#include -+#endif -+ -+#include -+ -+#ifdef BIGPHYSAREA_ENABLE -+#include -+#endif /* BIGPHYSAREA_ENABLE */ -+ -+#ifndef CONFIG_FMAN_ARM -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "error_ext.h" -+#include "std_ext.h" -+#include "list_ext.h" -+#include "mm_ext.h" -+#include "sys_io_ext.h" -+#include "xx.h" -+ -+ -+#define __ERR_MODULE__ MODULE_UNKNOWN -+ -+#ifdef BIGPHYSAREA_ENABLE -+#define MAX_ALLOCATION_SIZE 128 * 1024 /* Maximum size allocated with kmalloc is 128K */ -+ -+ -+/* TODO: large allocations => use big phys area */ -+/****************************************************************************** -+ * routine: get_nr_pages -+ * -+ * description: -+ * calculates the number of memory pages for a given size (in bytes) -+ * -+ * arguments: -+ * size - the number of bytes -+ * -+ * return code: -+ * The number of pages -+ * -+ *****************************************************************************/ -+static __inline__ uint32_t get_nr_pages (uint32_t size) -+{ -+ return (uint32_t)((size >> PAGE_SHIFT) + (size & PAGE_SHIFT ? 1 : 0)); -+} -+ -+static bool in_big_phys_area (uint32_t addr) -+{ -+ uint32_t base, size; -+ -+ bigphysarea_get_details (&base, &size); -+ return ((addr >= base) && (addr < base + size)); -+} -+#endif /* BIGPHYSAREA_ENABLE */ -+ -+void * xx_Malloc(uint32_t n) -+{ -+ void *a; -+ uint32_t flags; -+ -+ flags = XX_DisableAllIntr(); -+#ifdef BIGPHYSAREA_ENABLE -+ if (n >= MAX_ALLOCATION_SIZE) -+ a = (void*)bigphysarea_alloc_pages(get_nr_pages(n), 0, GFP_ATOMIC); -+ else -+#endif /* BIGPHYSAREA_ENABLE */ -+ a = (void *)kmalloc((uint32_t)n, GFP_ATOMIC); -+ if (!a) -+ XX_Print("No memory for XX_Malloc\n"); -+ XX_RestoreAllIntr(flags); -+ -+ return a; -+} -+ -+void xx_Free(void *p) -+{ -+#ifdef BIGPHYSAREA_ENABLE -+ if (in_big_phys_area ((uint32_t)p)) -+ bigphysarea_free_pages(p); -+ else -+#endif /* BIGPHYSAREA_ENABLE */ -+ kfree(p); -+} -+ -+void XX_Exit(int status) -+{ -+ WARN(1, "\n\nFMD: fatal error, driver can't go on!!!\n\n"); -+} -+ -+#define BUF_SIZE 512 -+void XX_Print(char *str, ...) -+{ -+ va_list args; -+#ifdef CONFIG_SMP -+ char buf[BUF_SIZE]; -+#endif /* CONFIG_SMP */ -+ -+ va_start(args, str); -+#ifdef CONFIG_SMP -+ if (vsnprintf (buf, BUF_SIZE, str, args) >= BUF_SIZE) -+ printk(KERN_WARNING "Illegal string to print!\n more than %d characters.\n\tString was not printed completelly.\n", BUF_SIZE); -+ printk(KERN_CRIT "cpu%d/%d: %s", raw_smp_processor_id(), NR_CPUS, buf); -+#else -+ vprintk(str, args); -+#endif /* CONFIG_SMP */ -+ va_end(args); -+} -+ -+void XX_Fprint(void *file, char *str, ...) -+{ -+ va_list args; -+#ifdef CONFIG_SMP -+ char buf[BUF_SIZE]; -+#endif /* CONFIG_SMP */ -+ -+ va_start(args, str); -+#ifdef CONFIG_SMP -+ if (vsnprintf (buf, BUF_SIZE, str, args) >= BUF_SIZE) -+ printk(KERN_WARNING "Illegal string to print!\n more than %d characters.\n\tString was not printed completelly.\n", BUF_SIZE); -+ printk (KERN_CRIT "cpu%d/%d: %s", raw_smp_processor_id(), NR_CPUS, buf); -+ -+#else -+ vprintk(str, args); -+#endif /* CONFIG_SMP */ -+ va_end(args); -+} -+ -+#ifdef DEBUG_XX_MALLOC -+typedef void (*t_ffn)(void *); -+typedef struct { -+ t_ffn f_free; -+ void *mem; -+ char *fname; -+ int fline; -+ uint32_t size; -+ t_List node; -+} t_MemDebug; -+#define MEMDBG_OBJECT(p_List) LIST_OBJECT(p_List, t_MemDebug, node) -+ -+LIST(memDbgLst); -+ -+ -+void * XX_MallocDebug(uint32_t size, char *fname, int line) -+{ -+ void *mem; -+ t_MemDebug *p_MemDbg; -+ -+ p_MemDbg = (t_MemDebug *)xx_Malloc(sizeof(t_MemDebug)); -+ if (p_MemDbg == NULL) -+ return NULL; -+ -+ mem = xx_Malloc(size); -+ if (mem == NULL) -+ { -+ XX_Free(p_MemDbg); -+ return NULL; -+ } -+ -+ INIT_LIST(&p_MemDbg->node); -+ p_MemDbg->f_free = xx_Free; -+ p_MemDbg->mem = mem; -+ p_MemDbg->fname = fname; -+ p_MemDbg->fline = line; -+ p_MemDbg->size = size+sizeof(t_MemDebug); -+ LIST_AddToTail(&p_MemDbg->node, &memDbgLst); -+ -+ return mem; -+} -+ -+void * XX_MallocSmartDebug(uint32_t size, -+ int memPartitionId, -+ uint32_t align, -+ char *fname, -+ int line) -+{ -+ void *mem; -+ t_MemDebug *p_MemDbg; -+ -+ p_MemDbg = (t_MemDebug *)XX_Malloc(sizeof(t_MemDebug)); -+ if (p_MemDbg == NULL) -+ return NULL; -+ -+ mem = xx_MallocSmart((uint32_t)size, memPartitionId, align); -+ if (mem == NULL) -+ { -+ XX_Free(p_MemDbg); -+ return NULL; -+ } -+ -+ INIT_LIST(&p_MemDbg->node); -+ p_MemDbg->f_free = xx_FreeSmart; -+ p_MemDbg->mem = mem; -+ p_MemDbg->fname = fname; -+ p_MemDbg->fline = line; -+ p_MemDbg->size = size+sizeof(t_MemDebug); -+ LIST_AddToTail(&p_MemDbg->node, &memDbgLst); -+ -+ return mem; -+} -+ -+static void debug_free(void *mem) -+{ -+ t_List *p_MemDbgLh = NULL; -+ t_MemDebug *p_MemDbg; -+ bool found = FALSE; -+ -+ if (LIST_IsEmpty(&memDbgLst)) -+ { -+ REPORT_ERROR(MAJOR, E_ALREADY_FREE, ("Unbalanced free (0x%08x)", mem)); -+ return; -+ } -+ -+ LIST_FOR_EACH(p_MemDbgLh, &memDbgLst) -+ { -+ p_MemDbg = MEMDBG_OBJECT(p_MemDbgLh); -+ if (p_MemDbg->mem == mem) -+ { -+ found = TRUE; -+ break; -+ } -+ } -+ -+ if (!found) -+ { -+ REPORT_ERROR(MAJOR, E_NOT_FOUND, -+ ("Attempt to free unallocated address (0x%08x)",mem)); -+ dump_stack(); -+ return; -+ } -+ -+ LIST_Del(p_MemDbgLh); -+ p_MemDbg->f_free(mem); -+ p_MemDbg->f_free(p_MemDbg); -+} -+ -+void XX_FreeSmart(void *p) -+{ -+ debug_free(p); -+} -+ -+ -+void XX_Free(void *p) -+{ -+ debug_free(p); -+} -+ -+#else /* not DEBUG_XX_MALLOC */ -+void * XX_Malloc(uint32_t size) -+{ -+ return xx_Malloc(size); -+} -+ -+void * XX_MallocSmart(uint32_t size, int memPartitionId, uint32_t alignment) -+{ -+ return xx_MallocSmart(size,memPartitionId, alignment); -+} -+ -+void XX_FreeSmart(void *p) -+{ -+ xx_FreeSmart(p); -+} -+ -+ -+void XX_Free(void *p) -+{ -+ xx_Free(p); -+} -+#endif /* not DEBUG_XX_MALLOC */ -+ -+ -+#if (defined(REPORT_EVENTS) && (REPORT_EVENTS > 0)) -+void XX_EventById(uint32_t event, t_Handle appId, uint16_t flags, char *msg) -+{ -+ e_Event eventCode = (e_Event)event; -+ -+ UNUSED(eventCode); -+ UNUSED(appId); -+ UNUSED(flags); -+ UNUSED(msg); -+} -+#endif /* (defined(REPORT_EVENTS) && ... */ -+ -+ -+uint32_t XX_DisableAllIntr(void) -+{ -+ unsigned long flags; -+ -+#ifdef local_irq_save_nort -+ local_irq_save_nort(flags); -+#else -+ local_irq_save(flags); -+#endif -+ -+ return (uint32_t)flags; -+} -+ -+void XX_RestoreAllIntr(uint32_t flags) -+{ -+#ifdef local_irq_restore_nort -+ local_irq_restore_nort((unsigned long)flags); -+#else -+ local_irq_restore((unsigned long)flags); -+#endif -+} -+ -+t_Error XX_Call( uint32_t qid, t_Error (* f)(t_Handle), t_Handle id, t_Handle appId, uint16_t flags ) -+{ -+ UNUSED(qid); -+ UNUSED(appId); -+ UNUSED(flags); -+ -+ return f(id); -+} -+ -+int XX_IsICacheEnable(void) -+{ -+ return TRUE; -+} -+ -+int XX_IsDCacheEnable(void) -+{ -+ return TRUE; -+} -+ -+ -+typedef struct { -+ t_Isr *f_Isr; -+ t_Handle handle; -+} t_InterruptHandler; -+ -+ -+t_Handle interruptHandlers[0x00010000]; -+ -+#ifdef CONFIG_FMAN_ARM -+static irqreturn_t LinuxInterruptHandler (int irq, void *dev_id) -+{ -+ t_InterruptHandler *p_IntrHndl = (t_InterruptHandler *)dev_id; -+ p_IntrHndl->f_Isr(p_IntrHndl->handle); -+ return IRQ_HANDLED; -+} -+#endif -+ -+t_Error XX_SetIntr(int irq, t_Isr *f_Isr, t_Handle handle) -+{ -+#ifdef CONFIG_FMAN_ARM -+ const char *device; -+ t_InterruptHandler *p_IntrHndl; -+ -+ device = GetDeviceName(irq); -+ if (device == NULL) -+ RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Interrupt source - %d", irq)); -+ -+ p_IntrHndl = (t_InterruptHandler *)XX_Malloc(sizeof(t_InterruptHandler)); -+ if (p_IntrHndl == NULL) -+ RETURN_ERROR(MAJOR, E_NO_MEMORY, NO_MSG); -+ p_IntrHndl->f_Isr = f_Isr; -+ p_IntrHndl->handle = handle; -+ interruptHandlers[irq] = p_IntrHndl; -+ -+ if (request_irq(GetDeviceIrqNum(irq), LinuxInterruptHandler, 0, device, p_IntrHndl) < 0) -+ RETURN_ERROR(MAJOR, E_BUSY, ("Can't get IRQ %s\n", device)); -+ disable_irq(GetDeviceIrqNum(irq)); -+#endif -+ return E_OK; -+} -+ -+t_Error XX_FreeIntr(int irq) -+{ -+ t_InterruptHandler *p_IntrHndl = interruptHandlers[irq]; -+ free_irq(GetDeviceIrqNum(irq), p_IntrHndl); -+ XX_Free(p_IntrHndl); -+ interruptHandlers[irq] = 0; -+ return E_OK; -+} -+ -+t_Error XX_EnableIntr(int irq) -+{ -+ enable_irq(GetDeviceIrqNum(irq)); -+ return E_OK; -+} -+ -+t_Error XX_DisableIntr(int irq) -+{ -+ disable_irq(GetDeviceIrqNum(irq)); -+ return E_OK; -+} -+ -+ -+/*****************************************************************************/ -+/* Tasklet Service Routines */ -+/*****************************************************************************/ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+typedef struct -+{ -+ t_Handle h_Data; -+ void (*f_Callback) (void *); -+ struct delayed_work dwork; -+} t_Tasklet; -+ -+static void GenericTaskletCallback(struct work_struct *p_Work) -+{ -+ t_Tasklet *p_Task = container_of(p_Work, t_Tasklet, dwork.work); -+ -+ p_Task->f_Callback(p_Task->h_Data); -+} -+#endif /* LINUX_VERSION_CODE */ -+ -+ -+t_TaskletHandle XX_InitTasklet (void (*routine)(void *), void *data) -+{ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ struct work_struct *p_Task; -+ p_Task = (struct work_struct *)XX_Malloc(sizeof(struct work_struct)); -+ INIT_WORK(p_Task, routine, data); -+#else -+ t_Tasklet *p_Task = (t_Tasklet *)XX_Malloc(sizeof(t_Tasklet)); -+ p_Task->h_Data = data; -+ p_Task->f_Callback = routine; -+ INIT_DELAYED_WORK(&p_Task->dwork, GenericTaskletCallback); -+#endif /* LINUX_VERSION_CODE */ -+ -+ return (t_TaskletHandle)p_Task; -+} -+ -+ -+void XX_FreeTasklet (t_TaskletHandle h_Tasklet) -+{ -+ if (h_Tasklet) -+ XX_Free(h_Tasklet); -+} -+ -+int XX_ScheduleTask(t_TaskletHandle h_Tasklet, int immediate) -+{ -+ int ans; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ if (immediate) -+ ans = schedule_work(h_Tasklet); -+ else -+ ans = schedule_delayed_work(h_Tasklet, 1); -+#else -+ if (immediate) -+ ans = schedule_delayed_work(&((t_Tasklet *)h_Tasklet)->dwork, 0); -+ else -+ ans = schedule_delayed_work(&((t_Tasklet *)h_Tasklet)->dwork, HZ); -+#endif /* LINUX_VERSION_CODE */ -+ -+ return ans; -+} -+ -+void XX_FlushScheduledTasks(void) -+{ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ flush_scheduled_tasks(); -+#else -+ flush_scheduled_work(); -+#endif /* LINUX_VERSION_CODE */ -+} -+ -+int XX_TaskletIsQueued(t_TaskletHandle h_Tasklet) -+{ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ return (int)(((struct work_struct *)h_Tasklet)->pending); -+#else -+ return (int)delayed_work_pending(&((t_Tasklet *)h_Tasklet)->dwork); -+#endif /* LINUX_VERSION_CODE */ -+} -+ -+void XX_SetTaskletData(t_TaskletHandle h_Tasklet, t_Handle data) -+{ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ ((struct tq_struct *)h_Tasklet)->data = data; -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ ((struct work_struct *)h_Tasklet)->data = data; -+#else -+ ((t_Tasklet *)h_Tasklet)->h_Data = data; -+#endif /* LINUX_VERSION_CODE */ -+} -+ -+t_Handle XX_GetTaskletData(t_TaskletHandle h_Tasklet) -+{ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ return (t_Handle)(((struct work_struct *)h_Tasklet)->data); -+#else -+ return ((t_Tasklet *)h_Tasklet)->h_Data; -+#endif /* LINUX_VERSION_CODE */ -+} -+ -+ -+/*****************************************************************************/ -+/* Spinlock Service Routines */ -+/*****************************************************************************/ -+ -+t_Handle XX_InitSpinlock(void) -+{ -+ spinlock_t *p_Spinlock = (spinlock_t *)XX_Malloc(sizeof(spinlock_t)); -+ if (!p_Spinlock) -+ return NULL; -+ -+ spin_lock_init(p_Spinlock); -+ -+ return (t_Handle)p_Spinlock; -+} -+ -+void XX_FreeSpinlock(t_Handle h_Spinlock) -+{ -+ if (h_Spinlock) -+ XX_Free(h_Spinlock); -+} -+ -+void XX_LockSpinlock(t_Handle h_Spinlock) -+{ -+ spin_lock((spinlock_t *)h_Spinlock); -+} -+ -+void XX_UnlockSpinlock(t_Handle h_Spinlock) -+{ -+ spin_unlock((spinlock_t *)h_Spinlock); -+} -+ -+uint32_t XX_LockIntrSpinlock(t_Handle h_Spinlock) -+{ -+ unsigned long intrFlags; -+ spin_lock_irqsave((spinlock_t *)h_Spinlock, intrFlags); -+ return intrFlags; -+} -+ -+void XX_UnlockIntrSpinlock(t_Handle h_Spinlock, uint32_t intrFlags) -+{ -+ spin_unlock_irqrestore((spinlock_t *)h_Spinlock, (unsigned long)intrFlags); -+} -+ -+ -+/*****************************************************************************/ -+/* Timers Service Routines */ -+/*****************************************************************************/ -+/* The time now is in mili sec. resolution */ -+uint32_t XX_CurrentTime(void) -+{ -+ return (jiffies*1000)/HZ; -+} -+ -+ -+t_Handle XX_CreateTimer(void) -+{ -+ struct timer_list *p_Timer = (struct timer_list *)XX_Malloc(sizeof(struct timer_list)); -+ if (p_Timer) -+ { -+ memset(p_Timer, 0, sizeof(struct timer_list)); -+ init_timer(p_Timer); -+ } -+ return (t_Handle)p_Timer; -+} -+ -+void XX_FreeTimer(t_Handle h_Timer) -+{ -+ if (h_Timer) -+ XX_Free(h_Timer); -+} -+ -+void XX_StartTimer(t_Handle h_Timer, -+ uint32_t msecs, -+ bool periodic, -+ void (*f_TimerExpired)(t_Handle), -+ t_Handle h_Arg) -+{ -+ int tmp_jiffies = (msecs*HZ)/1000; -+ struct timer_list *p_Timer = (struct timer_list *)h_Timer; -+ -+ SANITY_CHECK_RETURN((periodic == FALSE), E_NOT_SUPPORTED); -+ -+ p_Timer->function = (void (*)(unsigned long))f_TimerExpired; -+ p_Timer->data = (unsigned long)h_Arg; -+ if ((msecs*HZ)%1000) -+ tmp_jiffies++; -+ p_Timer->expires = (jiffies + tmp_jiffies); -+ -+ add_timer((struct timer_list *)h_Timer); -+} -+ -+void XX_SetTimerData(t_Handle h_Timer, t_Handle data) -+{ -+ struct timer_list *p_Timer = (struct timer_list *)h_Timer; -+ -+ p_Timer->data = (unsigned long)data; -+} -+ -+t_Handle XX_GetTimerData(t_Handle h_Timer) -+{ -+ struct timer_list *p_Timer = (struct timer_list *)h_Timer; -+ -+ return (t_Handle)p_Timer->data; -+} -+ -+uint32_t XX_GetExpirationTime(t_Handle h_Timer) -+{ -+ struct timer_list *p_Timer = (struct timer_list *)h_Timer; -+ -+ return (uint32_t)p_Timer->expires; -+} -+ -+void XX_StopTimer(t_Handle h_Timer) -+{ -+ del_timer((struct timer_list *)h_Timer); -+} -+ -+void XX_ModTimer(t_Handle h_Timer, uint32_t msecs) -+{ -+ int tmp_jiffies = (msecs*HZ)/1000; -+ -+ if ((msecs*HZ)%1000) -+ tmp_jiffies++; -+ mod_timer((struct timer_list *)h_Timer, jiffies + tmp_jiffies); -+} -+ -+int XX_TimerIsActive(t_Handle h_Timer) -+{ -+ return timer_pending((struct timer_list *)h_Timer); -+} -+ -+uint32_t XX_Sleep(uint32_t msecs) -+{ -+ int tmp_jiffies = (msecs*HZ)/1000; -+ -+ if ((msecs*HZ)%1000) -+ tmp_jiffies++; -+ return schedule_timeout(tmp_jiffies); -+} -+ -+/*BEWARE!!!!! UDelay routine is BUSY WAITTING!!!!!*/ -+void XX_UDelay(uint32_t usecs) -+{ -+ udelay(usecs); -+} -+ -+/* TODO: verify that these are correct */ -+#define MSG_BODY_SIZE 512 -+typedef t_Error (t_MsgHandler) (t_Handle h_Mod, uint32_t msgId, uint8_t msgBody[MSG_BODY_SIZE]); -+typedef void (t_MsgCompletionCB) (t_Handle h_Arg, uint8_t msgBody[MSG_BODY_SIZE]); -+t_Error XX_SendMessage(char *p_DestAddr, -+ uint32_t msgId, -+ uint8_t msgBody[MSG_BODY_SIZE], -+ t_MsgCompletionCB *f_CompletionCB, -+ t_Handle h_CBArg); -+ -+typedef struct { -+ char *p_Addr; -+ t_MsgHandler *f_MsgHandlerCB; -+ t_Handle h_Mod; -+ t_List node; -+} t_MsgHndlr; -+#define MSG_HNDLR_OBJECT(ptr) LIST_OBJECT(ptr, t_MsgHndlr, node) -+ -+LIST(msgHndlrList); -+ -+static void EnqueueMsgHndlr(t_MsgHndlr *p_MsgHndlr) -+{ -+ uint32_t intFlags; -+ -+ intFlags = XX_DisableAllIntr(); -+ LIST_AddToTail(&p_MsgHndlr->node, &msgHndlrList); -+ XX_RestoreAllIntr(intFlags); -+} -+/* TODO: add this for multi-platform support -+static t_MsgHndlr * DequeueMsgHndlr(void) -+{ -+ t_MsgHndlr *p_MsgHndlr = NULL; -+ uint32_t intFlags; -+ -+ intFlags = XX_DisableAllIntr(); -+ if (!LIST_IsEmpty(&msgHndlrList)) -+ { -+ p_MsgHndlr = MSG_HNDLR_OBJECT(msgHndlrList.p_Next); -+ LIST_DelAndInit(&p_MsgHndlr->node); -+ } -+ XX_RestoreAllIntr(intFlags); -+ -+ return p_MsgHndlr; -+} -+*/ -+static t_MsgHndlr * FindMsgHndlr(char *p_Addr) -+{ -+ t_MsgHndlr *p_MsgHndlr; -+ t_List *p_Pos; -+ -+ LIST_FOR_EACH(p_Pos, &msgHndlrList) -+ { -+ p_MsgHndlr = MSG_HNDLR_OBJECT(p_Pos); -+ if (strstr(p_MsgHndlr->p_Addr, p_Addr)) -+ return p_MsgHndlr; -+ } -+ -+ return NULL; -+} -+ -+t_Error XX_RegisterMessageHandler (char *p_Addr, t_MsgHandler *f_MsgHandlerCB, t_Handle h_Mod) -+{ -+ t_MsgHndlr *p_MsgHndlr; -+ uint32_t len; -+ -+ p_MsgHndlr = (t_MsgHndlr*)XX_Malloc(sizeof(t_MsgHndlr)); -+ if (!p_MsgHndlr) -+ RETURN_ERROR(MINOR, E_NO_MEMORY, ("message handler object!!!")); -+ memset(p_MsgHndlr, 0, sizeof(t_MsgHndlr)); -+ -+ len = strlen(p_Addr); -+ p_MsgHndlr->p_Addr = (char*)XX_Malloc(len+1); -+ strncpy(p_MsgHndlr->p_Addr,p_Addr, (uint32_t)(len+1)); -+ -+ p_MsgHndlr->f_MsgHandlerCB = f_MsgHandlerCB; -+ p_MsgHndlr->h_Mod = h_Mod; -+ INIT_LIST(&p_MsgHndlr->node); -+ EnqueueMsgHndlr(p_MsgHndlr); -+ -+ return E_OK; -+} -+ -+t_Error XX_UnregisterMessageHandler (char *p_Addr) -+{ -+ t_MsgHndlr *p_MsgHndlr = FindMsgHndlr(p_Addr); -+ if (!p_MsgHndlr) -+ RETURN_ERROR(MINOR, E_NO_DEVICE, ("message handler not found in list!!!")); -+ -+ LIST_Del(&p_MsgHndlr->node); -+ XX_Free(p_MsgHndlr->p_Addr); -+ XX_Free(p_MsgHndlr); -+ -+ return E_OK; -+} -+ -+t_Error XX_SendMessage(char *p_DestAddr, -+ uint32_t msgId, -+ uint8_t msgBody[MSG_BODY_SIZE], -+ t_MsgCompletionCB *f_CompletionCB, -+ t_Handle h_CBArg) -+{ -+ t_Error ans; -+ t_MsgHndlr *p_MsgHndlr = FindMsgHndlr(p_DestAddr); -+ if (!p_MsgHndlr) -+ RETURN_ERROR(MINOR, E_NO_DEVICE, ("message handler not found in list!!!")); -+ -+ ans = p_MsgHndlr->f_MsgHandlerCB(p_MsgHndlr->h_Mod, msgId, msgBody); -+ -+ if (f_CompletionCB) -+ f_CompletionCB(h_CBArg, msgBody); -+ -+ return ans; -+} -+ -+t_Error XX_IpcRegisterMsgHandler(char addr[XX_IPC_MAX_ADDR_NAME_LENGTH], -+ t_IpcMsgHandler *f_MsgHandler, -+ t_Handle h_Module, -+ uint32_t replyLength) -+{ -+ UNUSED(addr);UNUSED(f_MsgHandler);UNUSED(h_Module);UNUSED(replyLength); -+ return E_OK; -+} -+ -+t_Error XX_IpcUnregisterMsgHandler(char addr[XX_IPC_MAX_ADDR_NAME_LENGTH]) -+{ -+ UNUSED(addr); -+ return E_OK; -+} -+ -+ -+t_Error XX_IpcSendMessage(t_Handle h_Session, -+ uint8_t *p_Msg, -+ uint32_t msgLength, -+ uint8_t *p_Reply, -+ uint32_t *p_ReplyLength, -+ t_IpcMsgCompletion *f_Completion, -+ t_Handle h_Arg) -+{ -+ UNUSED(h_Session); UNUSED(p_Msg); UNUSED(msgLength); UNUSED(p_Reply); -+ UNUSED(p_ReplyLength); UNUSED(f_Completion); UNUSED(h_Arg); -+ return E_OK; -+} -+ -+t_Handle XX_IpcInitSession(char destAddr[XX_IPC_MAX_ADDR_NAME_LENGTH], -+ char srcAddr[XX_IPC_MAX_ADDR_NAME_LENGTH]) -+{ -+ UNUSED(destAddr); UNUSED(srcAddr); -+ return E_OK; -+} -+ -+/*Forced to introduce due to PRINT_FMT_PARAMS define*/ -+uint32_t E500_GetId(void) -+{ -+ return raw_smp_processor_id(); -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) -+int GetDeviceIrqNum(int irq) -+{ -+ struct device_node *iPar; -+ struct irq_domain *irqHost; -+ uint32_t hwIrq; -+ -+ /* Get the interrupt controller */ -+ iPar = of_find_node_by_name(NULL, "mpic"); -+ hwIrq = 0; -+ -+ ASSERT_COND(iPar != NULL); -+ /* Get the irq host */ -+ irqHost = irq_find_host(iPar); -+ of_node_put(iPar); -+ -+ /* Create irq mapping */ -+ return irq_create_mapping(irqHost, hwIrq); -+} -+#else -+#error "kernel not supported!!!" -+#endif /* LINUX_VERSION_CODE */ -+ -+void * XX_PhysToVirt(physAddress_t addr) -+{ -+ return UINT_TO_PTR(SYS_PhysToVirt((uint64_t)addr)); -+} -+ -+physAddress_t XX_VirtToPhys(void * addr) -+{ -+ return (physAddress_t)SYS_VirtToPhys(PTR_TO_UINT(addr)); -+} -+ -+void * xx_MallocSmart(uint32_t size, int memPartitionId, uint32_t alignment) -+{ -+ uintptr_t *returnCode, tmp; -+ -+ if (alignment < sizeof(uintptr_t)) -+ alignment = sizeof(uintptr_t); -+ size += alignment + sizeof(returnCode); -+ tmp = (uintptr_t)xx_Malloc(size); -+ if (tmp == 0) -+ return NULL; -+ returnCode = (uintptr_t*)((tmp + alignment + sizeof(returnCode)) & ~((uintptr_t)alignment - 1)); -+ *(returnCode - 1) = tmp; -+ -+ return (void*)returnCode; -+} -+ -+void xx_FreeSmart(void *p) -+{ -+ xx_Free((void*)(*((uintptr_t *)(p) - 1))); -+} ---- /dev/null -+++ b/include/uapi/linux/fmd/Kbuild -@@ -0,0 +1,5 @@ -+header-y += integrations/ -+header-y += Peripherals/ -+ -+header-y += ioctls.h -+header-y += net_ioctls.h ---- /dev/null -+++ b/include/uapi/linux/fmd/Peripherals/Kbuild -@@ -0,0 +1,4 @@ -+header-y += fm_ioctls.h -+header-y += fm_port_ioctls.h -+header-y += fm_pcd_ioctls.h -+header-y += fm_test_ioctls.h ---- /dev/null -+++ b/include/uapi/linux/fmd/Peripherals/fm_ioctls.h -@@ -0,0 +1,628 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ @File fm_ioctls.h -+ -+ @Description FM Char device ioctls -+*//***************************************************************************/ -+#ifndef __FM_IOCTLS_H -+#define __FM_IOCTLS_H -+ -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_FM_grp Frame Manager Linux IOCTL API -+ -+ @Description FM Linux ioctls definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Collection FM IOCTL device ('/dev') definitions -+*//***************************************************************************/ -+#define DEV_FM_NAME "fm" /**< Name of the FM chardev */ -+ -+#define DEV_FM_MINOR_BASE 0 -+#define DEV_FM_PCD_MINOR_BASE (DEV_FM_MINOR_BASE + 1) /*/dev/fmx-pcd */ -+#define DEV_FM_OH_PORTS_MINOR_BASE (DEV_FM_PCD_MINOR_BASE + 1) /*/dev/fmx-port-ohy */ -+#define DEV_FM_RX_PORTS_MINOR_BASE (DEV_FM_OH_PORTS_MINOR_BASE + FM_MAX_NUM_OF_OH_PORTS) /*/dev/fmx-port-rxy */ -+#define DEV_FM_TX_PORTS_MINOR_BASE (DEV_FM_RX_PORTS_MINOR_BASE + FM_MAX_NUM_OF_RX_PORTS) /*/dev/fmx-port-txy */ -+#define DEV_FM_MAX_MINORS (DEV_FM_TX_PORTS_MINOR_BASE + FM_MAX_NUM_OF_TX_PORTS) -+ -+#define FM_IOC_NUM(n) (n) -+#define FM_PCD_IOC_NUM(n) (n+20) -+#define FM_PORT_IOC_NUM(n) (n+70) -+/* @} */ -+ -+#define IOC_FM_MAX_NUM_OF_PORTS 64 -+ -+ -+/**************************************************************************//** -+ @Description Enum for defining port types -+ (must match enum e_FmPortType defined in fm_ext.h) -+*//***************************************************************************/ -+typedef enum ioc_fm_port_type { -+ e_IOC_FM_PORT_TYPE_OH_OFFLINE_PARSING = 0, /**< Offline parsing port */ -+ e_IOC_FM_PORT_TYPE_RX, /**< 1G Rx port */ -+ e_IOC_FM_PORT_TYPE_RX_10G, /**< 10G Rx port */ -+ e_IOC_FM_PORT_TYPE_TX, /**< 1G Tx port */ -+ e_IOC_FM_PORT_TYPE_TX_10G, /**< 10G Tx port */ -+ e_IOC_FM_PORT_TYPE_DUMMY -+} ioc_fm_port_type; -+ -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_FM_lib_grp FM library -+ -+ @Description FM API functions, definitions and enums -+ The FM module is the main driver module and is a mandatory module -+ for FM driver users. Before any further module initialization, -+ this module must be initialized. -+ The FM is a "single-tone" module. It is responsible of the common -+ HW modules: FPM, DMA, common QMI, common BMI initializations and -+ run-time control routines. This module must be initialized always -+ when working with any of the FM modules. -+ NOTE - We assumes that the FML will be initialize only by core No. 0! -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description FM Exceptions -+*//***************************************************************************/ -+typedef enum ioc_fm_exceptions { -+ e_IOC_FM_EX_DMA_BUS_ERROR, /**< DMA bus error. */ -+ e_IOC_EX_DMA_READ_ECC, /**< Read Buffer ECC error (Valid for FM rev < 6)*/ -+ e_IOC_EX_DMA_SYSTEM_WRITE_ECC, /**< Write Buffer ECC error on system side (Valid for FM rev < 6)*/ -+ e_IOC_EX_DMA_FM_WRITE_ECC, /**< Write Buffer ECC error on FM side (Valid for FM rev < 6)*/ -+ e_IOC_EX_DMA_SINGLE_PORT_ECC, /**< Single Port ECC error on FM side (Valid for FM rev > 6)*/ -+ e_IOC_EX_FPM_STALL_ON_TASKS, /**< Stall of tasks on FPM */ -+ e_IOC_EX_FPM_SINGLE_ECC, /**< Single ECC on FPM. */ -+ e_IOC_EX_FPM_DOUBLE_ECC, /**< Double ECC error on FPM ram access */ -+ e_IOC_EX_QMI_SINGLE_ECC, /**< Single ECC on QMI. */ -+ e_IOC_EX_QMI_DOUBLE_ECC, /**< Double bit ECC occurred on QMI */ -+ e_IOC_EX_QMI_DEQ_FROM_UNKNOWN_PORTID,/**< Dequeue from unknown port id */ -+ e_IOC_EX_BMI_LIST_RAM_ECC, /**< Linked List RAM ECC error */ -+ e_IOC_EX_BMI_STORAGE_PROFILE_ECC, /**< Storage Profile ECC Error */ -+ e_IOC_EX_BMI_STATISTICS_RAM_ECC, /**< Statistics Count RAM ECC Error Enable */ -+ e_IOC_EX_BMI_DISPATCH_RAM_ECC, /**< Dispatch RAM ECC Error Enable */ -+ e_IOC_EX_IRAM_ECC, /**< Double bit ECC occurred on IRAM*/ -+ e_IOC_EX_MURAM_ECC /**< Double bit ECC occurred on MURAM*/ -+} ioc_fm_exceptions; -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_FM_runtime_control_grp FM Runtime Control Unit -+ -+ @Description FM Runtime control unit API functions, definitions and enums. -+ The FM driver provides a set of control routines for each module. -+ These routines may only be called after the module was fully -+ initialized (both configuration and initialization routines were -+ called). They are typically used to get information from hardware -+ (status, counters/statistics, revision etc.), to modify a current -+ state or to force/enable a required action. Run-time control may -+ be called whenever necessary and as many times as needed. -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Collection General FM defines. -+ *//***************************************************************************/ -+#define IOC_FM_MAX_NUM_OF_VALID_PORTS (FM_MAX_NUM_OF_OH_PORTS + \ -+ FM_MAX_NUM_OF_1G_RX_PORTS + \ -+ FM_MAX_NUM_OF_10G_RX_PORTS + \ -+ FM_MAX_NUM_OF_1G_TX_PORTS + \ -+ FM_MAX_NUM_OF_10G_TX_PORTS) -+/* @} */ -+ -+/**************************************************************************//** -+ @Description Structure for Port bandwidth requirement. Port is identified -+ by type and relative id. -+ (must be identical to t_FmPortBandwidth defined in fm_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_port_bandwidth_t { -+ ioc_fm_port_type type; /**< FM port type */ -+ uint8_t relative_port_id; /**< Type relative port id */ -+ uint8_t bandwidth; /**< bandwidth - (in term of percents) */ -+} ioc_fm_port_bandwidth_t; -+ -+/**************************************************************************//** -+ @Description A Structure containing an array of Port bandwidth requirements. -+ The user should state the ports requiring bandwidth in terms of -+ percentage - i.e. all port's bandwidths in the array must add -+ up to 100. -+ (must be identical to t_FmPortsBandwidthParams defined in fm_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_port_bandwidth_params { -+ uint8_t num_of_ports; -+ /**< num of ports listed in the array below */ -+ ioc_fm_port_bandwidth_t ports_bandwidths[IOC_FM_MAX_NUM_OF_VALID_PORTS]; -+ /**< for each port, it's bandwidth (all port's -+ bandwidths must add up to 100.*/ -+} ioc_fm_port_bandwidth_params; -+ -+/**************************************************************************//** -+ @Description enum for defining FM counters -+*//***************************************************************************/ -+typedef enum ioc_fm_counters { -+ e_IOC_FM_COUNTERS_ENQ_TOTAL_FRAME, /**< QMI total enqueued frames counter */ -+ e_IOC_FM_COUNTERS_DEQ_TOTAL_FRAME, /**< QMI total dequeued frames counter */ -+ e_IOC_FM_COUNTERS_DEQ_0, /**< QMI 0 frames from QMan counter */ -+ e_IOC_FM_COUNTERS_DEQ_1, /**< QMI 1 frames from QMan counter */ -+ e_IOC_FM_COUNTERS_DEQ_2, /**< QMI 2 frames from QMan counter */ -+ e_IOC_FM_COUNTERS_DEQ_3, /**< QMI 3 frames from QMan counter */ -+ e_IOC_FM_COUNTERS_DEQ_FROM_DEFAULT, /**< QMI dequeue from default queue counter */ -+ e_IOC_FM_COUNTERS_DEQ_FROM_CONTEXT, /**< QMI dequeue from FQ context counter */ -+ e_IOC_FM_COUNTERS_DEQ_FROM_FD, /**< QMI dequeue from FD command field counter */ -+ e_IOC_FM_COUNTERS_DEQ_CONFIRM, /**< QMI dequeue confirm counter */ -+} ioc_fm_counters; -+ -+typedef struct ioc_fm_obj_t { -+ void *obj; -+} ioc_fm_obj_t; -+ -+/**************************************************************************//** -+ @Description A structure for returning revision information -+ (must match struct t_FmRevisionInfo declared in fm_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_revision_info_t { -+ uint8_t major; /**< Major revision */ -+ uint8_t minor; /**< Minor revision */ -+} ioc_fm_revision_info_t; -+ -+/**************************************************************************//** -+ @Description A structure for FM counters -+*//***************************************************************************/ -+typedef struct ioc_fm_counters_params_t { -+ ioc_fm_counters cnt; /**< The requested counter */ -+ uint32_t val; /**< The requested value to get/set from/into the counter */ -+} ioc_fm_counters_params_t; -+ -+typedef union ioc_fm_api_version_t { -+ struct { -+ uint8_t major; -+ uint8_t minor; -+ uint8_t respin; -+ uint8_t reserved; -+ } version; -+ uint32_t ver; -+} ioc_fm_api_version_t; -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description A structure of information about each of the external -+ buffer pools used by a port or storage-profile. -+ (must be identical to t_FmExtPoolParams defined in fm_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_ext_pool_params { -+ uint8_t id; /**< External buffer pool id */ -+ uint16_t size; /**< External buffer pool buffer size */ -+} ioc_fm_ext_pool_params; -+ -+/**************************************************************************//** -+ @Description A structure for informing the driver about the external -+ buffer pools allocated in the BM and used by a port or a -+ storage-profile. -+ (must be identical to t_FmExtPools defined in fm_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_ext_pools { -+ uint8_t num_of_pools_used; /**< Number of pools use by this port */ -+ ioc_fm_ext_pool_params ext_buf_pool[FM_PORT_MAX_NUM_OF_EXT_POOLS]; -+ /**< Parameters for each port */ -+} ioc_fm_ext_pools; -+ -+typedef struct ioc_fm_vsp_params_t { -+ void *p_fm; /**< A handle to the FM object this VSP related to */ -+ ioc_fm_ext_pools ext_buf_pools; /**< Which external buffer pools are used -+ (up to FM_PORT_MAX_NUM_OF_EXT_POOLS), and their sizes. -+ parameter associated with Rx / OP port */ -+ uint16_t liodn_offset; /**< VSP's LIODN offset */ -+ struct { -+ ioc_fm_port_type port_type; /**< Port type */ -+ uint8_t port_id; /**< Port Id - relative to type */ -+ } port_params; -+ uint8_t relative_profile_id; /**< VSP Id - relative to VSP's range -+ defined in relevant FM object */ -+ void *id; /**< return value */ -+} ioc_fm_vsp_params_t; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Description A structure for defining BM pool depletion criteria -+*//***************************************************************************/ -+typedef struct ioc_fm_buf_pool_depletion_t { -+ bool pools_grp_mode_enable; /**< select mode in which pause frames will be sent after -+ a number of pools (all together!) are depleted */ -+ uint8_t num_of_pools; /**< the number of depleted pools that will invoke -+ pause frames transmission. */ -+ bool pools_to_consider[BM_MAX_NUM_OF_POOLS]; -+ /**< For each pool, TRUE if it should be considered for -+ depletion (Note - this pool must be used by this port!). */ -+ bool single_pool_mode_enable; /**< select mode in which pause frames will be sent after -+ a single-pool is depleted; */ -+ bool pools_to_consider_for_single_mode[BM_MAX_NUM_OF_POOLS]; -+ /**< For each pool, TRUE if it should be considered for -+ depletion (Note - this pool must be used by this port!) */ -+#if (DPAA_VERSION >= 11) -+ bool pfc_priorities_en[FM_MAX_NUM_OF_PFC_PRIORITIES]; -+ /**< This field is used by the MAC as the Priority Enable Vector in the PFC frame -+ which is transmitted */ -+#endif /* (DPAA_VERSION >= 11) */ -+} ioc_fm_buf_pool_depletion_t; -+ -+#if (DPAA_VERSION >= 11) -+typedef struct ioc_fm_buf_pool_depletion_params_t { -+ void *p_fm_vsp; -+ ioc_fm_buf_pool_depletion_t fm_buf_pool_depletion; -+} ioc_fm_buf_pool_depletion_params_t; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+typedef struct ioc_fm_buffer_prefix_content_t { -+ uint16_t priv_data_size; /**< Number of bytes to be left at the beginning -+ of the external buffer; Note that the private-area will -+ start from the base of the buffer address. */ -+ bool pass_prs_result; /**< TRUE to pass the parse result to/from the FM; -+ User may use FM_PORT_GetBufferPrsResult() in order to -+ get the parser-result from a buffer. */ -+ bool pass_time_stamp; /**< TRUE to pass the timeStamp to/from the FM -+ User may use FM_PORT_GetBufferTimeStamp() in order to -+ get the parser-result from a buffer. */ -+ bool pass_hash_result; /**< TRUE to pass the KG hash result to/from the FM -+ User may use FM_PORT_GetBufferHashResult() in order to -+ get the parser-result from a buffer. */ -+ bool pass_all_other_pcd_info; /**< Add all other Internal-Context information: -+ AD, hash-result, key, etc. */ -+ uint16_t data_align; /**< 0 to use driver's default alignment [64], -+ other value for selecting a data alignment (must be a power of 2); -+ if write optimization is used, must be >= 16. */ -+ uint8_t manip_extra_space; /**< Maximum extra size needed (insertion-size minus removal-size); -+ Note that this field impacts the size of the buffer-prefix -+ (i.e. it pushes the data offset); -+ This field is irrelevant if DPAA_VERSION==10 */ -+} ioc_fm_buffer_prefix_content_t; -+ -+typedef struct ioc_fm_buffer_prefix_content_params_t { -+ void *p_fm_vsp; -+ ioc_fm_buffer_prefix_content_t fm_buffer_prefix_content; -+} ioc_fm_buffer_prefix_content_params_t; -+ -+#if (DPAA_VERSION >= 11) -+typedef struct ioc_fm_vsp_config_no_sg_params_t { -+ void *p_fm_vsp; -+ bool no_sg; -+} ioc_fm_vsp_config_no_sg_params_t; -+ -+typedef struct ioc_fm_vsp_prs_result_params_t { -+ void *p_fm_vsp; -+ void *p_data; -+} ioc_fm_vsp_prs_result_params_t; -+#endif -+ -+typedef struct fm_ctrl_mon_t { -+ uint8_t percent_cnt[2]; -+} fm_ctrl_mon_t; -+ -+typedef struct ioc_fm_ctrl_mon_counters_params_t { -+ uint8_t fm_ctrl_index; -+ fm_ctrl_mon_t *p_mon; -+} ioc_fm_ctrl_mon_counters_params_t; -+ -+/**************************************************************************//** -+ @Function FM_IOC_SET_PORTS_BANDWIDTH -+ -+ @Description Sets relative weights between ports when accessing common resources. -+ -+ @Param[in] ioc_fm_port_bandwidth_params Port bandwidth percentages, -+ their sum must equal 100. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+#define FM_IOC_SET_PORTS_BANDWIDTH _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(2), ioc_fm_port_bandwidth_params) -+ -+/**************************************************************************//** -+ @Function FM_IOC_GET_REVISION -+ -+ @Description Returns the FM revision -+ -+ @Param[out] ioc_fm_revision_info_t A structure of revision information parameters. -+ -+ @Return None. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+#define FM_IOC_GET_REVISION _IOR(FM_IOC_TYPE_BASE, FM_IOC_NUM(3), ioc_fm_revision_info_t) -+ -+/**************************************************************************//** -+ @Function FM_IOC_GET_COUNTER -+ -+ @Description Reads one of the FM counters. -+ -+ @Param[in,out] ioc_fm_counters_params_t The requested counter parameters. -+ -+ @Return Counter's current value. -+ -+ @Cautions Allowed only following FM_Init(). -+ Note that it is user's responsibilty to call this routine only -+ for enabled counters, and there will be no indication if a -+ disabled counter is accessed. -+*//***************************************************************************/ -+#define FM_IOC_GET_COUNTER _IOWR(FM_IOC_TYPE_BASE, FM_IOC_NUM(4), ioc_fm_counters_params_t) -+ -+/**************************************************************************//** -+ @Function FM_IOC_SET_COUNTER -+ -+ @Description Sets a value to an enabled counter. Use "0" to reset the counter. -+ -+ @Param[in] ioc_fm_counters_params_t The requested counter parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+#define FM_IOC_SET_COUNTER _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(5), ioc_fm_counters_params_t) -+ -+/**************************************************************************//** -+ @Function FM_IOC_FORCE_INTR -+ -+ @Description Causes an interrupt event on the requested source. -+ -+ @Param[in] ioc_fm_exceptions An exception to be forced. -+ -+ @Return E_OK on success; Error code if the exception is not enabled, -+ or is not able to create interrupt. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+#define FM_IOC_FORCE_INTR _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(6), ioc_fm_exceptions) -+ -+/**************************************************************************//** -+ @Function FM_IOC_GET_API_VERSION -+ -+ @Description Reads the FMD IOCTL API version. -+ -+ @Param[in,out] ioc_fm_api_version_t The requested counter parameters. -+ -+ @Return Version's value. -+*//***************************************************************************/ -+#define FM_IOC_GET_API_VERSION _IOR(FM_IOC_TYPE_BASE, FM_IOC_NUM(7), ioc_fm_api_version_t) -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Function FM_VSP_Config -+ -+ @Description Creates descriptor for the FM VSP module. -+ -+ The routine returns a handle (descriptor) to the FM VSP object. -+ This descriptor must be passed as first parameter to all other -+ FM VSP function calls. -+ -+ No actual initialization or configuration of FM hardware is -+ done by this routine. -+ -+@Param[in] p_FmVspParams Pointer to data structure of parameters -+ -+ @Retval Handle to FM VSP object, or NULL for Failure. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_IOC_VSP_CONFIG_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_IOC_NUM(8), ioc_compat_fm_vsp_params_t) -+#endif -+#define FM_IOC_VSP_CONFIG _IOWR(FM_IOC_TYPE_BASE, FM_IOC_NUM(8), ioc_fm_vsp_params_t) -+ -+/**************************************************************************//** -+ @Function FM_VSP_Init -+ -+ @Description Initializes the FM VSP module -+ -+ @Param[in] h_FmVsp - FM VSP module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_IOC_VSP_INIT_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(9), ioc_compat_fm_obj_t) -+#endif -+#define FM_IOC_VSP_INIT _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(9), ioc_fm_obj_t) -+ -+/**************************************************************************//** -+ @Function FM_VSP_Free -+ -+ @Description Frees all resources that were assigned to FM VSP module. -+ -+ Calling this routine invalidates the descriptor. -+ -+ @Param[in] h_FmVsp - FM VSP module descriptor -+ -+ @Return E_OK on success; Error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_IOC_VSP_FREE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(10), ioc_compat_fm_obj_t) -+#endif -+#define FM_IOC_VSP_FREE _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(10), ioc_fm_obj_t) -+ -+/**************************************************************************//** -+ @Function FM_VSP_ConfigPoolDepletion -+ -+ @Description Calling this routine enables pause frame generation depending on the -+ depletion status of BM pools. It also defines the conditions to activate -+ this functionality. By default, this functionality is disabled. -+ -+ @Param[in] ioc_fm_buf_pool_depletion_params_t A structure holding the required parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_IOC_VSP_CONFIG_POOL_DEPLETION_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(11), ioc_compat_fm_buf_pool_depletion_params_t) -+#endif -+#define FM_IOC_VSP_CONFIG_POOL_DEPLETION _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(11), ioc_fm_buf_pool_depletion_params_t) -+ -+/**************************************************************************//** -+ @Function FM_VSP_ConfigBufferPrefixContent -+ -+ @Description Defines the structure, size and content of the application buffer. -+ -+ The prefix will -+ In VSPs defined for Tx ports, if 'passPrsResult', the application -+ should set a value to their offsets in the prefix of -+ the FM will save the first 'privDataSize', than, -+ depending on 'passPrsResult' and 'passTimeStamp', copy parse result -+ and timeStamp, and the packet itself (in this order), to the -+ application buffer, and to offset. -+ -+ Calling this routine changes the buffer margins definitions -+ in the internal driver data base from its default -+ configuration: Data size: [DEFAULT_FM_SP_bufferPrefixContent_privDataSize] -+ Pass Parser result: [DEFAULT_FM_SP_bufferPrefixContent_passPrsResult]. -+ Pass timestamp: [DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp]. -+ -+ @Param[in] ioc_fm_buffer_prefix_content_params_t A structure holding the required parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_IOC_VSP_CONFIG_BUFFER_PREFIX_CONTENT_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(12), ioc_compat_fm_buffer_prefix_content_params_t) -+#endif -+#define FM_IOC_VSP_CONFIG_BUFFER_PREFIX_CONTENT _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(12), ioc_fm_buffer_prefix_content_params_t) -+ -+/**************************************************************************//** -+ @Function FM_VSP_ConfigNoScatherGather -+ -+ @Description Calling this routine changes the possibility to receive S/G frame -+ in the internal driver data base -+ from its default configuration: optimize = [DEFAULT_FM_SP_noScatherGather] -+ -+ @Param[in] ioc_fm_vsp_config_no_sg_params_t A structure holding the required parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_IOC_VSP_CONFIG_NO_SG_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(13), ioc_compat_fm_vsp_config_no_sg_params_t) -+#endif -+#define FM_IOC_VSP_CONFIG_NO_SG _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(13), ioc_fm_vsp_config_no_sg_params_t) -+ -+/**************************************************************************//** -+ @Function FM_VSP_GetBufferPrsResult -+ -+ @Description Returns the pointer to the parse result in the data buffer. -+ In Rx ports this is relevant after reception, if parse -+ result is configured to be part of the data passed to the -+ application. For non Rx ports it may be used to get the pointer -+ of the area in the buffer where parse result should be -+ initialized - if so configured. -+ See FM_VSP_ConfigBufferPrefixContent for data buffer prefix -+ configuration. -+ -+ @Param[in] ioc_fm_vsp_prs_result_params_t A structure holding the required parameters. -+ -+ @Return Parse result pointer on success, NULL if parse result was not -+ configured for this port. -+ -+ @Cautions Allowed only following FM_VSP_Init(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_IOC_VSP_GET_BUFFER_PRS_RESULT_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_IOC_NUM(14), ioc_compat_fm_vsp_prs_result_params_t) -+#endif -+#define FM_IOC_VSP_GET_BUFFER_PRS_RESULT _IOWR(FM_IOC_TYPE_BASE, FM_IOC_NUM(14), ioc_fm_vsp_prs_result_params_t) -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Function FM_CtrlMonStart -+ -+ @Description Start monitoring utilization of all available FM controllers. -+ -+ In order to obtain FM controllers utilization the following sequence -+ should be used: -+ -# FM_CtrlMonStart() -+ -# FM_CtrlMonStop() -+ -# FM_CtrlMonGetCounters() - issued for each FM controller -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+#define FM_IOC_CTRL_MON_START _IO(FM_IOC_TYPE_BASE, FM_IOC_NUM(15)) -+ -+ -+/**************************************************************************//** -+ @Function FM_CtrlMonStop -+ -+ @Description Stop monitoring utilization of all available FM controllers. -+ -+ In order to obtain FM controllers utilization the following sequence -+ should be used: -+ -# FM_CtrlMonStart() -+ -# FM_CtrlMonStop() -+ -# FM_CtrlMonGetCounters() - issued for each FM controller -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+#define FM_IOC_CTRL_MON_STOP _IO(FM_IOC_TYPE_BASE, FM_IOC_NUM(16)) -+ -+/**************************************************************************//** -+ @Function FM_CtrlMonGetCounters -+ -+ @Description Obtain FM controller utilization parameters. -+ -+ In order to obtain FM controllers utilization the following sequence -+ should be used: -+ -# FM_CtrlMonStart() -+ -# FM_CtrlMonStop() -+ -# FM_CtrlMonGetCounters() - issued for each FM controller -+ -+ @Param[in] ioc_fm_ctrl_mon_counters_params_t A structure holding the required parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_IOC_CTRL_MON_GET_COUNTERS_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(17), ioc_compat_fm_ctrl_mon_counters_params_t) -+#endif -+#define FM_IOC_CTRL_MON_GET_COUNTERS _IOW(FM_IOC_TYPE_BASE, FM_IOC_NUM(17), ioc_fm_ctrl_mon_counters_params_t) -+ -+/** @} */ /* end of lnx_ioctl_FM_runtime_control_grp group */ -+/** @} */ /* end of lnx_ioctl_FM_lib_grp group */ -+/** @} */ /* end of lnx_ioctl_FM_grp */ -+ -+#define FMD_API_VERSION_MAJOR 21 -+#define FMD_API_VERSION_MINOR 1 -+#define FMD_API_VERSION_RESPIN 0 -+ -+#endif /* __FM_IOCTLS_H */ ---- /dev/null -+++ b/include/uapi/linux/fmd/Peripherals/fm_pcd_ioctls.h -@@ -0,0 +1,3084 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/****************************************************************************** -+ @File fm_pcd_ioctls.h -+ -+ @Description FM PCD ... -+*//***************************************************************************/ -+#ifndef __FM_PCD_IOCTLS_H -+#define __FM_PCD_IOCTLS_H -+ -+#include "net_ioctls.h" -+#include "fm_ioctls.h" -+ -+ -+/**************************************************************************//** -+ -+ @Group lnx_ioctl_FM_grp Frame Manager Linux IOCTL API -+ -+ @Description Frame Manager Linux ioctls definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_FM_PCD_grp FM PCD -+ -+ @Description Frame Manager PCD API functions, definitions and enums -+ -+ The FM PCD module is responsible for the initialization of all -+ global classifying FM modules. This includes the parser general and -+ common registers, the key generator global and common registers, -+ and the policer global and common registers. -+ In addition, the FM PCD SW module will initialize all required -+ key generator schemes, coarse classification flows, and policer -+ profiles. When an FM module is configured to work with one of these -+ entities, it will register to it using the FM PORT API. The PCD -+ module will manage the PCD resources - i.e. resource management of -+ KeyGen schemes, etc. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Collection General PCD defines -+*//***************************************************************************/ -+#define IOC_FM_PCD_MAX_NUM_OF_PRIVATE_HDRS 2 /**< Number of units/headers saved for user */ -+ -+#define IOC_FM_PCD_PRS_NUM_OF_HDRS 16 /**< Number of headers supported by HW parser */ -+#define IOC_FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS (32 - IOC_FM_PCD_MAX_NUM_OF_PRIVATE_HDRS) -+ /**< Number of distinction units is limited by -+ register size (32 bits) minus reserved bits -+ for private headers. */ -+#define IOC_FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS 4 /**< Maximum number of interchangeable headers -+ in a distinction unit */ -+#define IOC_FM_PCD_KG_NUM_OF_GENERIC_REGS 8 /**< Total number of generic KeyGen registers */ -+#define IOC_FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY 35 /**< Max number allowed on any configuration; -+ For HW implementation reasons, in most -+ cases less than this will be allowed; The -+ driver will return an initialization error -+ if resource is unavailable. */ -+#define IOC_FM_PCD_KG_NUM_OF_EXTRACT_MASKS 4 /**< Total number of masks allowed on KeyGen extractions. */ -+#define IOC_FM_PCD_KG_NUM_OF_DEFAULT_GROUPS 16 /**< Number of default value logical groups */ -+ -+#define IOC_FM_PCD_PRS_NUM_OF_LABELS 32 /**< Maximum number of SW parser labels */ -+#define IOC_FM_PCD_SW_PRS_SIZE 0x00000800 /**< Total size of SW parser area */ -+ -+#define IOC_FM_PCD_MAX_MANIP_INSRT_TEMPLATE_SIZE 128 /**< Maximum size of insertion template for -+ insert manipulation */ -+ -+#if DPAA_VERSION >= 11 -+#define IOC_FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES 64 /**< Maximum possible entries for frame replicator group */ -+#endif /* DPAA_VERSION >= 11 */ -+/* @} */ -+ -+#ifdef FM_CAPWAP_SUPPORT -+#error "FM_CAPWAP_SUPPORT not implemented!" -+#endif -+ -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_FM_PCD_init_grp FM PCD Initialization Unit -+ -+ @Description Frame Manager PCD Initialization Unit API -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description PCD counters -+ (must match enum e_FmPcdCounters defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_counters { -+ e_IOC_FM_PCD_KG_COUNTERS_TOTAL, /**< KeyGen counter */ -+ e_IOC_FM_PCD_PLCR_COUNTERS_RED, /**< Policer counter - counts the total number of RED packets that exit the Policer. */ -+ e_IOC_FM_PCD_PLCR_COUNTERS_YELLOW, /**< Policer counter - counts the total number of YELLOW packets that exit the Policer. */ -+ e_IOC_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_RED, /**< Policer counter - counts the number of packets that changed color to RED by the Policer; -+ This is a subset of e_IOC_FM_PCD_PLCR_COUNTERS_RED packet count, indicating active color changes. */ -+ e_IOC_FM_PCD_PLCR_COUNTERS_RECOLORED_TO_YELLOW, /**< Policer counter - counts the number of packets that changed color to YELLOW by the Policer; -+ This is a subset of e_IOC_FM_PCD_PLCR_COUNTERS_YELLOW packet count, indicating active color changes. */ -+ e_IOC_FM_PCD_PLCR_COUNTERS_TOTAL, /**< Policer counter - counts the total number of packets passed in the Policer. */ -+ e_IOC_FM_PCD_PLCR_COUNTERS_LENGTH_MISMATCH, /**< Policer counter - counts the number of packets with length mismatch. */ -+ e_IOC_FM_PCD_PRS_COUNTERS_PARSE_DISPATCH, /**< Parser counter - counts the number of times the parser block is dispatched. */ -+ e_IOC_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED, /**< Parser counter - counts the number of times L2 parse result is returned (including errors). */ -+ e_IOC_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED, /**< Parser counter - counts the number of times L3 parse result is returned (including errors). */ -+ e_IOC_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED, /**< Parser counter - counts the number of times L4 parse result is returned (including errors). */ -+ e_IOC_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED, /**< Parser counter - counts the number of times SHIM parse result is returned (including errors). */ -+ e_IOC_FM_PCD_PRS_COUNTERS_L2_PARSE_RESULT_RETURNED_WITH_ERR, /**< Parser counter - counts the number of times L2 parse result is returned with errors. */ -+ e_IOC_FM_PCD_PRS_COUNTERS_L3_PARSE_RESULT_RETURNED_WITH_ERR, /**< Parser counter - counts the number of times L3 parse result is returned with errors. */ -+ e_IOC_FM_PCD_PRS_COUNTERS_L4_PARSE_RESULT_RETURNED_WITH_ERR, /**< Parser counter - counts the number of times L4 parse result is returned with errors. */ -+ e_IOC_FM_PCD_PRS_COUNTERS_SHIM_PARSE_RESULT_RETURNED_WITH_ERR, /**< Parser counter - counts the number of times SHIM parse result is returned with errors. */ -+ e_IOC_FM_PCD_PRS_COUNTERS_SOFT_PRS_CYCLES, /**< Parser counter - counts the number of cycles spent executing soft parser instruction (including stall cycles). */ -+ e_IOC_FM_PCD_PRS_COUNTERS_SOFT_PRS_STALL_CYCLES, /**< Parser counter - counts the number of cycles stalled waiting for parser internal memory reads while executing soft parser instruction. */ -+ e_IOC_FM_PCD_PRS_COUNTERS_HARD_PRS_CYCLE_INCL_STALL_CYCLES, /**< Parser counter - counts the number of cycles spent executing hard parser (including stall cycles). */ -+ e_IOC_FM_PCD_PRS_COUNTERS_MURAM_READ_CYCLES, /**< MURAM counter - counts the number of cycles while performing FMan Memory read. */ -+ e_IOC_FM_PCD_PRS_COUNTERS_MURAM_READ_STALL_CYCLES, /**< MURAM counter - counts the number of cycles stalled while performing FMan Memory read. */ -+ e_IOC_FM_PCD_PRS_COUNTERS_MURAM_WRITE_CYCLES, /**< MURAM counter - counts the number of cycles while performing FMan Memory write. */ -+ e_IOC_FM_PCD_PRS_COUNTERS_MURAM_WRITE_STALL_CYCLES, /**< MURAM counter - counts the number of cycles stalled while performing FMan Memory write. */ -+ e_IOC_FM_PCD_PRS_COUNTERS_FPM_COMMAND_STALL_CYCLES /**< FPM counter - counts the number of cycles stalled while performing a FPM Command. */ -+} ioc_fm_pcd_counters; -+ -+/**************************************************************************//** -+ @Description PCD interrupts -+ (must match enum e_FmPcdExceptions defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_exceptions { -+ e_IOC_FM_PCD_KG_EXCEPTION_DOUBLE_ECC, /**< KeyGen double-bit ECC error is detected on internal memory read access. */ -+ e_IOC_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW, /**< KeyGen scheme configuration error indicating a key size larger than 56 bytes. */ -+ e_IOC_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC, /**< Policer double-bit ECC error has been detected on PRAM read access. */ -+ e_IOC_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR, /**< Policer access to a non-initialized profile has been detected. */ -+ e_IOC_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE, /**< Policer RAM self-initialization complete */ -+ e_IOC_FM_PCD_PLCR_EXCEPTION_ATOMIC_ACTION_COMPLETE, /**< Policer atomic action complete */ -+ e_IOC_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC, /**< Parser double-bit ECC error */ -+ e_IOC_FM_PCD_PRS_EXCEPTION_SINGLE_ECC /**< Parser single-bit ECC error */ -+} ioc_fm_pcd_exceptions; -+ -+/** @} */ /* end of lnx_ioctl_FM_PCD_init_grp group */ -+ -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_FM_PCD_Runtime_grp FM PCD Runtime Unit -+ -+ @Description Frame Manager PCD Runtime Unit -+ -+ The runtime control allows creation of PCD infrastructure modules -+ such as Network Environment Characteristics, Classification Plan -+ Groups and Coarse Classification Trees. -+ It also allows on-the-fly initialization, modification and removal -+ of PCD modules such as KeyGen schemes, coarse classification nodes -+ and Policer profiles. -+ -+ In order to explain the programming model of the PCD driver interface -+ a few terms should be explained, and will be used below. -+ - Distinction Header - One of the 16 protocols supported by the FM parser, -+ or one of the SHIM headers (1 or 2). May be a header with a special -+ option (see below). -+ - Interchangeable Headers Group - This is a group of Headers recognized -+ by either one of them. For example, if in a specific context the user -+ chooses to treat IPv4 and IPV6 in the same way, they may create an -+ interchangeable Headers Unit consisting of these 2 headers. -+ - A Distinction Unit - a Distinction Header or an Interchangeable Headers -+ Group. -+ - Header with special option - applies to Ethernet, MPLS, VLAN, IPv4 and -+ IPv6, includes multicast, broadcast and other protocol specific options. -+ In terms of hardware it relates to the options available in the classification -+ plan. -+ - Network Environment Characteristics - a set of Distinction Units that define -+ the total recognizable header selection for a certain environment. This is -+ NOT the list of all headers that will ever appear in a flow, but rather -+ everything that needs distinction in a flow, where distinction is made by KeyGen -+ schemes and coarse classification action descriptors. -+ -+ The PCD runtime modules initialization is done in stages. The first stage after -+ initializing the PCD module itself is to establish a Network Flows Environment -+ Definition. The application may choose to establish one or more such environments. -+ Later, when needed, the application will have to state, for some of its modules, -+ to which single environment it belongs. -+ -+ @{ -+*//***************************************************************************/ -+ -+ -+/**************************************************************************//** -+ @Description structure for FM counters -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_counters_params_t { -+ ioc_fm_pcd_counters cnt; /**< The requested counter */ -+ uint32_t val; /**< The requested value to get/set from/into the counter */ -+} ioc_fm_pcd_counters_params_t; -+ -+/**************************************************************************//** -+ @Description structure for FM exception definitios -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_exception_params_t { -+ ioc_fm_pcd_exceptions exception; /**< The requested exception */ -+ bool enable; /**< TRUE to enable interrupt, FALSE to mask it. */ -+} ioc_fm_pcd_exception_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for SW parser labels -+ (must be identical to struct t_FmPcdPrsLabelParams defined in fm_pcd_ext.h) -+ *//***************************************************************************/ -+typedef struct ioc_fm_pcd_prs_label_params_t { -+ uint32_t instruction_offset; /**< SW parser label instruction offset (2 bytes -+ resolution), relative to Parser RAM. */ -+ ioc_net_header_type hdr; /**< The existence of this header will invoke -+ the SW parser code. */ -+ uint8_t index_per_hdr; /**< Normally 0, if more than one SW parser -+ attachments for the same header, use this -+ index to distinguish between them. */ -+} ioc_fm_pcd_prs_label_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for SW parser -+ (Must match struct t_FmPcdPrsSwParams defined in fm_pcd_ext.h) -+ *//***************************************************************************/ -+typedef struct ioc_fm_pcd_prs_sw_params_t { -+ bool override; /**< FALSE to invoke a check that nothing else -+ was loaded to this address, including -+ internal patches. -+ TRUE to override any existing code.*/ -+ uint32_t size; /**< SW parser code size */ -+ uint16_t base; /**< SW parser base (in instruction counts! -+ must be larger than 0x20)*/ -+ uint8_t *p_code; /**< SW parser code */ -+ uint32_t sw_prs_data_params[IOC_FM_PCD_PRS_NUM_OF_HDRS]; -+ /**< SW parser data (parameters) */ -+ uint8_t num_of_labels; /**< Number of labels for SW parser. */ -+ ioc_fm_pcd_prs_label_params_t labels_table[IOC_FM_PCD_PRS_NUM_OF_LABELS]; -+ /**< SW parser labels table, -+ containing num_of_labels entries */ -+} ioc_fm_pcd_prs_sw_params_t; -+ -+/**************************************************************************//** -+ @Description A structure to set the a KeyGen default value -+ *//***************************************************************************/ -+typedef struct ioc_fm_pcd_kg_dflt_value_params_t { -+ uint8_t valueId; /**< 0,1 - one of 2 global default values */ -+ uint32_t value; /**< The requested default value */ -+} ioc_fm_pcd_kg_dflt_value_params_t; -+ -+ -+/**************************************************************************//** -+ @Function FM_PCD_Enable -+ -+ @Description This routine should be called after PCD is initialized for enabling all -+ PCD engines according to their existing configuration. -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only when PCD is disabled. -+*//***************************************************************************/ -+#define FM_PCD_IOC_ENABLE _IO(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(1)) -+ -+/**************************************************************************//** -+ @Function FM_PCD_Disable -+ -+ @Description This routine may be called when PCD is enabled in order to -+ disable all PCD engines. It may be called -+ only when none of the ports in the system are using the PCD. -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only when PCD is enabled. -+*//***************************************************************************/ -+#define FM_PCD_IOC_DISABLE _IO(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(2)) -+ -+ /**************************************************************************//** -+ @Function FM_PCD_PrsLoadSw -+ -+ @Description This routine may be called only when all ports in the -+ system are actively using the classification plan scheme. -+ In such cases it is recommended in order to save resources. -+ The driver automatically saves 8 classification plans for -+ ports that do NOT use the classification plan mechanism, to -+ avoid this (in order to save those entries) this routine may -+ be called. -+ -+ @Param[in] ioc_fm_pcd_prs_sw_params_t A pointer to the image of the software parser code. -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only when PCD is disabled. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_PRS_LOAD_SW_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(3), ioc_compat_fm_pcd_prs_sw_params_t) -+#endif -+#define FM_PCD_IOC_PRS_LOAD_SW _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(3), ioc_fm_pcd_prs_sw_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_KgSetDfltValue -+ -+ @Description Calling this routine sets a global default value to be used -+ by the KeyGen when parser does not recognize a required -+ field/header. -+ By default default values are 0. -+ -+ @Param[in] ioc_fm_pcd_kg_dflt_value_params_t A pointer to a structure with the relevant parameters -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only when PCD is disabled. -+*//***************************************************************************/ -+#define FM_PCD_IOC_KG_SET_DFLT_VALUE _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(6), ioc_fm_pcd_kg_dflt_value_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_KgSetAdditionalDataAfterParsing -+ -+ @Description Calling this routine allows the keygen to access data past -+ the parser finishing point. -+ -+ @Param[in] uint8_t payload-offset; the number of bytes beyond the parser location. -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only when PCD is disabled. -+*//***************************************************************************/ -+#define FM_PCD_IOC_KG_SET_ADDITIONAL_DATA_AFTER_PARSING _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(7), uint8_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_SetException -+ -+ @Description Calling this routine enables/disables PCD interrupts. -+ -+ @Param[in] ioc_fm_pcd_exception_params_t Arguments struct with exception to be enabled/disabled. -+ -+ @Return 0 on success; Error code otherwise. -+*//***************************************************************************/ -+#define FM_PCD_IOC_SET_EXCEPTION _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(8), ioc_fm_pcd_exception_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_GetCounter -+ -+ @Description Reads one of the FM PCD counters. -+ -+ @Param[in,out] ioc_fm_pcd_counters_params_t The requested counter parameters. -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Note that it is user's responsibilty to call this routine only -+ for enabled counters, and there will be no indication if a -+ disabled counter is accessed. -+*//***************************************************************************/ -+#define FM_PCD_IOC_GET_COUNTER _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(9), ioc_fm_pcd_counters_params_t) -+ -+/**************************************************************************//** -+ -+ @Function FM_PCD_KgSchemeGetCounter -+ -+ @Description Reads scheme packet counter. -+ -+ @Param[in] h_Scheme scheme handle as returned by FM_PCD_KgSchemeSet(). -+ -+ @Return Counter's current value. -+ -+ @Cautions Allowed only following FM_PCD_Init() & FM_PCD_KgSchemeSet(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_KG_SCHEME_GET_CNTR_COMPAT _IOR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(4), ioc_compat_fm_pcd_kg_scheme_spc_t) -+#endif -+#define FM_PCD_IOC_KG_SCHEME_GET_CNTR _IOR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(4), ioc_fm_pcd_kg_scheme_spc_t) -+ -+#if 0 -+TODO: unused IOCTL -+/**************************************************************************//** -+ @Function FM_PCD_ModifyCounter -+ -+ @Description Writes a value to an enabled counter. Use "0" to reset the counter. -+ -+ @Param[in] ioc_fm_pcd_counters_params_t - The requested counter parameters. -+ -+ @Return 0 on success; Error code otherwise. -+*//***************************************************************************/ -+#define FM_PCD_IOC_MODIFY_COUNTER _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(10), ioc_fm_pcd_counters_params_t) -+#define FM_PCD_IOC_SET_COUNTER FM_PCD_IOC_MODIFY_COUNTER -+#endif -+ -+/**************************************************************************//** -+ @Function FM_PCD_ForceIntr -+ -+ @Description Causes an interrupt event on the requested source. -+ -+ @Param[in] ioc_fm_pcd_exceptions - An exception to be forced. -+ -+ @Return 0 on success; error code if the exception is not enabled, -+ or is not able to create interrupt. -+*//***************************************************************************/ -+#define FM_PCD_IOC_FORCE_INTR _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(11), ioc_fm_pcd_exceptions) -+ -+/**************************************************************************//** -+ @Collection Definitions of coarse classification parameters as required by KeyGen -+ (when coarse classification is the next engine after this scheme). -+*//***************************************************************************/ -+#define IOC_FM_PCD_MAX_NUM_OF_CC_TREES 8 -+#define IOC_FM_PCD_MAX_NUM_OF_CC_GROUPS 16 -+#define IOC_FM_PCD_MAX_NUM_OF_CC_UNITS 4 -+#define IOC_FM_PCD_MAX_NUM_OF_KEYS 256 -+#define IOC_FM_PCD_MAX_NUM_OF_FLOWS (4*KILOBYTE) -+#define IOC_FM_PCD_MAX_SIZE_OF_KEY 56 -+#define IOC_FM_PCD_MAX_NUM_OF_CC_ENTRIES_IN_GRP 16 -+#define IOC_FM_PCD_LAST_KEY_INDEX 0xffff -+#define IOC_FM_PCD_MANIP_DSCP_VALUES 64 -+/* @} */ -+ -+/**************************************************************************//** -+ @Collection A set of definitions to allow protocol -+ special option description. -+*//***************************************************************************/ -+typedef uint32_t ioc_protocol_opt_t; /**< A general type to define a protocol option. */ -+ -+typedef ioc_protocol_opt_t ioc_eth_protocol_opt_t; /**< Ethernet protocol options. */ -+#define IOC_ETH_BROADCAST 0x80000000 /**< Ethernet Broadcast. */ -+#define IOC_ETH_MULTICAST 0x40000000 /**< Ethernet Multicast. */ -+ -+typedef ioc_protocol_opt_t ioc_vlan_protocol_opt_t; /**< Vlan protocol options. */ -+#define IOC_VLAN_STACKED 0x20000000 /**< Stacked VLAN. */ -+ -+typedef ioc_protocol_opt_t ioc_mpls_protocol_opt_t; /**< MPLS protocol options. */ -+#define IOC_MPLS_STACKED 0x10000000 /**< Stacked MPLS. */ -+ -+typedef ioc_protocol_opt_t ioc_ipv4_protocol_opt_t; /**< IPv4 protocol options. */ -+#define IOC_IPV4_BROADCAST_1 0x08000000 /**< IPv4 Broadcast. */ -+#define IOC_IPV4_MULTICAST_1 0x04000000 /**< IPv4 Multicast. */ -+#define IOC_IPV4_UNICAST_2 0x02000000 /**< Tunneled IPv4 - Unicast. */ -+#define IOC_IPV4_MULTICAST_BROADCAST_2 0x01000000 /**< Tunneled IPv4 - Broadcast/Multicast. */ -+ -+#define IOC_IPV4_FRAG_1 0x00000008 /**< IPV4 reassembly option. -+ IPV4 Reassembly manipulation requires network -+ environment with IPV4 header and IPV4_FRAG_1 option */ -+ -+typedef ioc_protocol_opt_t ioc_ipv6_protocol_opt_t; /**< IPv6 protocol options. */ -+#define IOC_IPV6_MULTICAST_1 0x00800000 /**< IPv6 Multicast. */ -+#define IOC_IPV6_UNICAST_2 0x00400000 /**< Tunneled IPv6 - Unicast. */ -+#define IOC_IPV6_MULTICAST_2 0x00200000 /**< Tunneled IPv6 - Multicast. */ -+ -+#define IOC_IPV6_FRAG_1 0x00000004 /**< IPV6 reassembly option. -+ IPV6 Reassembly manipulation requires network -+ environment with IPV6 header and IPV6_FRAG_1 option */ -+#if (DPAA_VERSION >= 11) -+typedef ioc_protocol_opt_t ioc_capwap_protocol_opt_t; /**< CAPWAP protocol options. */ -+#define CAPWAP_FRAG_1 0x00000008 /**< CAPWAP reassembly option. -+ CAPWAP Reassembly manipulation requires network -+ environment with CAPWAP header and CAPWAP_FRAG_1 option; -+ in case where fragment found, the fragment-extension offset -+ may be found at 'shim2' (in parser-result). */ -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/* @} */ -+ -+#define IOC_FM_PCD_MANIP_MAX_HDR_SIZE 256 -+#define IOC_FM_PCD_MANIP_DSCP_TO_VLAN_TRANS 64 -+/**************************************************************************//** -+ @Collection A set of definitions to support Header Manipulation selection. -+*//***************************************************************************/ -+typedef uint32_t ioc_hdr_manip_flags_t; /**< A general type to define a HMan update command flags. */ -+ -+typedef ioc_hdr_manip_flags_t ioc_ipv4_hdr_manip_update_flags_t; /**< IPv4 protocol HMan update command flags. */ -+ -+#define IOC_HDR_MANIP_IPV4_TOS 0x80000000 /**< update TOS with the given value ('tos' field -+ of ioc_fm_pcd_manip_hdr_field_update_ipv4_t) */ -+#define IOC_HDR_MANIP_IPV4_ID 0x40000000 /**< update IP ID with the given value ('id' field -+ of ioc_fm_pcd_manip_hdr_field_update_ipv4_t) */ -+#define IOC_HDR_MANIP_IPV4_TTL 0x20000000 /**< Decrement TTL by 1 */ -+#define IOC_HDR_MANIP_IPV4_SRC 0x10000000 /**< update IP source address with the given value -+ ('src' field of ioc_fm_pcd_manip_hdr_field_update_ipv4_t) */ -+#define IOC_HDR_MANIP_IPV4_DST 0x08000000 /**< update IP destination address with the given value -+ ('dst' field of ioc_fm_pcd_manip_hdr_field_update_ipv4_t) */ -+ -+typedef ioc_hdr_manip_flags_t ioc_ipv6_hdr_manip_update_flags_t; /**< IPv6 protocol HMan update command flags. */ -+ -+#define IOC_HDR_MANIP_IPV6_TC 0x80000000 /**< update Traffic Class address with the given value -+ ('traffic_class' field of ioc_fm_pcd_manip_hdr_field_update_ipv6_t) */ -+#define IOC_HDR_MANIP_IPV6_HL 0x40000000 /**< Decrement Hop Limit by 1 */ -+#define IOC_HDR_MANIP_IPV6_SRC 0x20000000 /**< update IP source address with the given value -+ ('src' field of ioc_fm_pcd_manip_hdr_field_update_ipv6_t) */ -+#define IOC_HDR_MANIP_IPV6_DST 0x10000000 /**< update IP destination address with the given value -+ ('dst' field of ioc_fm_pcd_manip_hdr_field_update_ipv6_t) */ -+ -+typedef ioc_hdr_manip_flags_t ioc_tcp_udp_hdr_manip_update_flags_t;/**< TCP/UDP protocol HMan update command flags. */ -+ -+#define IOC_HDR_MANIP_TCP_UDP_SRC 0x80000000 /**< update TCP/UDP source address with the given value -+ ('src' field of ioc_fm_pcd_manip_hdr_field_update_tcp_udp_t) */ -+#define IOC_HDR_MANIP_TCP_UDP_DST 0x40000000 /**< update TCP/UDP destination address with the given value -+ ('dst' field of ioc_fm_pcd_manip_hdr_field_update_tcp_udp_t) */ -+#define IOC_HDR_MANIP_TCP_UDP_CHECKSUM 0x20000000 /**< update TCP/UDP checksum */ -+ -+/* @} */ -+ -+/**************************************************************************//** -+ @Description A type used for returning the order of the key extraction. -+ each value in this array represents the index of the extraction -+ command as defined by the user in the initialization extraction array. -+ The valid size of this array is the user define number of extractions -+ required (also marked by the second '0' in this array). -+*//***************************************************************************/ -+typedef uint8_t ioc_fm_pcd_kg_key_order_t [IOC_FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY]; -+ -+/**************************************************************************//** -+ @Description All PCD engines -+ (must match enum e_FmPcdEngine defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_engine { -+ e_IOC_FM_PCD_INVALID = 0, /**< Invalid PCD engine */ -+ e_IOC_FM_PCD_DONE, /**< No PCD Engine indicated */ -+ e_IOC_FM_PCD_KG, /**< KeyGen */ -+ e_IOC_FM_PCD_CC, /**< Coarse Classifier */ -+ e_IOC_FM_PCD_PLCR, /**< Policer */ -+ e_IOC_FM_PCD_PRS, /**< Parser */ -+#if DPAA_VERSION >= 11 -+ e_IOC_FM_PCD_FR, /**< Frame Replicator */ -+#endif /* DPAA_VERSION >= 11 */ -+ e_IOC_FM_PCD_HASH /**< Hash Table */ -+} ioc_fm_pcd_engine; -+ -+/**************************************************************************//** -+ @Description An enum for selecting extraction by header types -+ (Must match enum e_FmPcdExtractByHdrType defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_extract_by_hdr_type { -+ e_IOC_FM_PCD_EXTRACT_FROM_HDR, /**< Extract bytes from header */ -+ e_IOC_FM_PCD_EXTRACT_FROM_FIELD, /**< Extract bytes from header field */ -+ e_IOC_FM_PCD_EXTRACT_FULL_FIELD /**< Extract a full field */ -+} ioc_fm_pcd_extract_by_hdr_type; -+ -+/**************************************************************************//** -+ @Description An enum for selecting extraction source (when it is not the header) -+ (Must match enum e_FmPcdExtractFrom defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_extract_from { -+ e_IOC_FM_PCD_EXTRACT_FROM_FRAME_START, /**< KG & CC: Extract from beginning of frame */ -+ e_IOC_FM_PCD_EXTRACT_FROM_DFLT_VALUE, /**< KG only: Extract from a default value */ -+ e_IOC_FM_PCD_EXTRACT_FROM_CURR_END_OF_PARSE, /**< KG only: Extract from the point where parsing had finished */ -+ e_IOC_FM_PCD_EXTRACT_FROM_KEY, /**< CC only: Field where saved KEY */ -+ e_IOC_FM_PCD_EXTRACT_FROM_HASH, /**< CC only: Field where saved HASH */ -+ e_IOC_FM_PCD_EXTRACT_FROM_PARSE_RESULT, /**< KG & CC: Extract from the parser result */ -+ e_IOC_FM_PCD_EXTRACT_FROM_ENQ_FQID, /**< KG & CC: Extract from enqueue FQID */ -+ e_IOC_FM_PCD_EXTRACT_FROM_FLOW_ID /**< CC only: Field where saved Dequeue FQID */ -+} ioc_fm_pcd_extract_from; -+ -+/**************************************************************************//** -+ @Description An enum for selecting extraction type -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_extract_type { -+ e_IOC_FM_PCD_EXTRACT_BY_HDR, /**< Extract according to header */ -+ e_IOC_FM_PCD_EXTRACT_NON_HDR, /**< Extract from data that is not the header */ -+ e_IOC_FM_PCD_KG_EXTRACT_PORT_PRIVATE_INFO /**< Extract private info as specified by user */ -+} ioc_fm_pcd_extract_type; -+ -+/**************************************************************************//** -+ @Description An enum for selecting a default -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_kg_extract_dflt_select { -+ e_IOC_FM_PCD_KG_DFLT_GBL_0, /**< Default selection is KG register 0 */ -+ e_IOC_FM_PCD_KG_DFLT_GBL_1, /**< Default selection is KG register 1 */ -+ e_IOC_FM_PCD_KG_DFLT_PRIVATE_0, /**< Default selection is a per scheme register 0 */ -+ e_IOC_FM_PCD_KG_DFLT_PRIVATE_1, /**< Default selection is a per scheme register 1 */ -+ e_IOC_FM_PCD_KG_DFLT_ILLEGAL /**< Illegal selection */ -+} ioc_fm_pcd_kg_extract_dflt_select; -+ -+/**************************************************************************//** -+ @Description Enumeration type defining all default groups - each group shares -+ a default value, one of four user-initialized values. -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_kg_known_fields_dflt_types { -+ e_IOC_FM_PCD_KG_MAC_ADDR, /**< MAC Address */ -+ e_IOC_FM_PCD_KG_TCI, /**< TCI field */ -+ e_IOC_FM_PCD_KG_ENET_TYPE, /**< ENET Type */ -+ e_IOC_FM_PCD_KG_PPP_SESSION_ID, /**< PPP Session id */ -+ e_IOC_FM_PCD_KG_PPP_PROTOCOL_ID, /**< PPP Protocol id */ -+ e_IOC_FM_PCD_KG_MPLS_LABEL, /**< MPLS label */ -+ e_IOC_FM_PCD_KG_IP_ADDR, /**< IP addr */ -+ e_IOC_FM_PCD_KG_PROTOCOL_TYPE, /**< Protocol type */ -+ e_IOC_FM_PCD_KG_IP_TOS_TC, /**< TOS or TC */ -+ e_IOC_FM_PCD_KG_IPV6_FLOW_LABEL, /**< IPV6 flow label */ -+ e_IOC_FM_PCD_KG_IPSEC_SPI, /**< IPSEC SPI */ -+ e_IOC_FM_PCD_KG_L4_PORT, /**< L4 Port */ -+ e_IOC_FM_PCD_KG_TCP_FLAG, /**< TCP Flag */ -+ e_IOC_FM_PCD_KG_GENERIC_FROM_DATA, /**< grouping implemented by SW, -+ any data extraction that is not the full -+ field described above */ -+ e_IOC_FM_PCD_KG_GENERIC_FROM_DATA_NO_V, /**< grouping implemented by SW, -+ any data extraction without validation */ -+ e_IOC_FM_PCD_KG_GENERIC_NOT_FROM_DATA /**< grouping implemented by SW, -+ extraction from parser result or -+ direct use of default value */ -+} ioc_fm_pcd_kg_known_fields_dflt_types; -+ -+/**************************************************************************//** -+ @Description Enumeration type for defining header index for scenarios with -+ multiple (tunneled) headers -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_hdr_index { -+ e_IOC_FM_PCD_HDR_INDEX_NONE = 0, /**< used when multiple headers not used, also -+ to specify regular IP (not tunneled). */ -+ e_IOC_FM_PCD_HDR_INDEX_1, /**< may be used for VLAN, MPLS, tunneled IP */ -+ e_IOC_FM_PCD_HDR_INDEX_2, /**< may be used for MPLS, tunneled IP */ -+ e_IOC_FM_PCD_HDR_INDEX_3, /**< may be used for MPLS */ -+ e_IOC_FM_PCD_HDR_INDEX_LAST = 0xFF /**< may be used for VLAN, MPLS */ -+} ioc_fm_pcd_hdr_index; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting the policer profile functional type -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_profile_type_selection { -+ e_IOC_FM_PCD_PLCR_PORT_PRIVATE, /**< Port dedicated profile */ -+ e_IOC_FM_PCD_PLCR_SHARED /**< Shared profile (shared within partition) */ -+} ioc_fm_pcd_profile_type_selection; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting the policer profile algorithm -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_plcr_algorithm_selection { -+ e_IOC_FM_PCD_PLCR_PASS_THROUGH, /**< Policer pass through */ -+ e_IOC_FM_PCD_PLCR_RFC_2698, /**< Policer algorithm RFC 2698 */ -+ e_IOC_FM_PCD_PLCR_RFC_4115 /**< Policer algorithm RFC 4115 */ -+} ioc_fm_pcd_plcr_algorithm_selection; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting a policer profile color mode -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_plcr_color_mode { -+ e_IOC_FM_PCD_PLCR_COLOR_BLIND, /**< Color blind */ -+ e_IOC_FM_PCD_PLCR_COLOR_AWARE /**< Color aware */ -+} ioc_fm_pcd_plcr_color_mode; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting a policer profile color -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_plcr_color { -+ e_IOC_FM_PCD_PLCR_GREEN, /**< Green */ -+ e_IOC_FM_PCD_PLCR_YELLOW, /**< Yellow */ -+ e_IOC_FM_PCD_PLCR_RED, /**< Red */ -+ e_IOC_FM_PCD_PLCR_OVERRIDE /**< Color override */ -+} ioc_fm_pcd_plcr_color; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting the policer profile packet frame length selector -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_plcr_frame_length_select { -+ e_IOC_FM_PCD_PLCR_L2_FRM_LEN, /**< L2 frame length */ -+ e_IOC_FM_PCD_PLCR_L3_FRM_LEN, /**< L3 frame length */ -+ e_IOC_FM_PCD_PLCR_L4_FRM_LEN, /**< L4 frame length */ -+ e_IOC_FM_PCD_PLCR_FULL_FRM_LEN /**< Full frame length */ -+} ioc_fm_pcd_plcr_frame_length_select; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting roll-back frame -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_plcr_roll_back_frame_select { -+ e_IOC_FM_PCD_PLCR_ROLLBACK_L2_FRM_LEN, /**< Rollback L2 frame length */ -+ e_IOC_FM_PCD_PLCR_ROLLBACK_FULL_FRM_LEN /**< Rollback Full frame length */ -+} ioc_fm_pcd_plcr_roll_back_frame_select; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting the policer profile packet or byte mode -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_plcr_rate_mode { -+ e_IOC_FM_PCD_PLCR_BYTE_MODE, /**< Byte mode */ -+ e_IOC_FM_PCD_PLCR_PACKET_MODE /**< Packet mode */ -+} ioc_fm_pcd_plcr_rate_mode; -+ -+/**************************************************************************//** -+ @Description Enumeration type for defining action of frame -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_done_action { -+ e_IOC_FM_PCD_ENQ_FRAME = 0, /**< Enqueue frame */ -+ e_IOC_FM_PCD_DROP_FRAME /**< Drop frame */ -+} ioc_fm_pcd_done_action; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting the policer counter -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_plcr_profile_counters { -+ e_IOC_FM_PCD_PLCR_PROFILE_GREEN_PACKET_TOTAL_COUNTER, /**< Green packets counter */ -+ e_IOC_FM_PCD_PLCR_PROFILE_YELLOW_PACKET_TOTAL_COUNTER, /**< Yellow packets counter */ -+ e_IOC_FM_PCD_PLCR_PROFILE_RED_PACKET_TOTAL_COUNTER, /**< Red packets counter */ -+ e_IOC_FM_PCD_PLCR_PROFILE_RECOLOURED_YELLOW_PACKET_TOTAL_COUNTER, /**< Recolored yellow packets counter */ -+ e_IOC_FM_PCD_PLCR_PROFILE_RECOLOURED_RED_PACKET_TOTAL_COUNTER /**< Recolored red packets counter */ -+} ioc_fm_pcd_plcr_profile_counters; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting the PCD action after extraction -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_action { -+ e_IOC_FM_PCD_ACTION_NONE, /**< NONE */ -+ e_IOC_FM_PCD_ACTION_EXACT_MATCH, /**< Exact match on the selected extraction*/ -+ e_IOC_FM_PCD_ACTION_INDEXED_LOOKUP /**< Indexed lookup on the selected extraction*/ -+} ioc_fm_pcd_action; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of insert manipulation -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_hdr_insrt_type { -+ e_IOC_FM_PCD_MANIP_INSRT_GENERIC, /**< Insert according to offset & size */ -+ e_IOC_FM_PCD_MANIP_INSRT_BY_HDR, /**< Insert according to protocol */ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ e_IOC_FM_PCD_MANIP_INSRT_BY_TEMPLATE /**< Insert template to start of frame */ -+#endif /* FM_CAPWAP_SUPPORT */ -+} ioc_fm_pcd_manip_hdr_insrt_type; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of remove manipulation -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_hdr_rmv_type { -+ e_IOC_FM_PCD_MANIP_RMV_GENERIC, /**< Remove according to offset & size */ -+ e_IOC_FM_PCD_MANIP_RMV_BY_HDR /**< Remove according to offset & size */ -+} ioc_fm_pcd_manip_hdr_rmv_type; -+ -+/**************************************************************************//** -+ @Description An enum for selecting specific L2 fields removal -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_hdr_rmv_specific_l2 { -+ e_IOC_FM_PCD_MANIP_HDR_RMV_ETHERNET, /**< Ethernet/802.3 MAC */ -+ e_IOC_FM_PCD_MANIP_HDR_RMV_STACKED_QTAGS, /**< stacked QTags */ -+ e_IOC_FM_PCD_MANIP_HDR_RMV_ETHERNET_AND_MPLS, /**< MPLS and Ethernet/802.3 MAC header until -+ the header which follows the MPLS header */ -+ e_IOC_FM_PCD_MANIP_HDR_RMV_MPLS /**< Remove MPLS header (Unlimited MPLS labels) */ -+} ioc_fm_pcd_manip_hdr_rmv_specific_l2; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting specific fields updates -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_hdr_field_update_type { -+ e_IOC_FM_PCD_MANIP_HDR_FIELD_UPDATE_VLAN, /**< VLAN updates */ -+ e_IOC_FM_PCD_MANIP_HDR_FIELD_UPDATE_IPV4, /**< IPV4 updates */ -+ e_IOC_FM_PCD_MANIP_HDR_FIELD_UPDATE_IPV6, /**< IPV6 updates */ -+ e_IOC_FM_PCD_MANIP_HDR_FIELD_UPDATE_TCP_UDP, /**< TCP_UDP updates */ -+} ioc_fm_pcd_manip_hdr_field_update_type; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting VLAN updates -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_hdr_field_update_vlan { -+ e_IOC_FM_PCD_MANIP_HDR_FIELD_UPDATE_VLAN_VPRI, /**< Replace VPri of outer most VLAN tag. */ -+ e_IOC_FM_PCD_MANIP_HDR_FIELD_UPDATE_DSCP_TO_VLAN /**< DSCP to VLAN priority bits translation */ -+} ioc_fm_pcd_manip_hdr_field_update_vlan; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting specific L2 fields removal -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_hdr_insrt_specific_l2 { -+ e_IOC_FM_PCD_MANIP_HDR_INSRT_MPLS /**< Insert MPLS header (Unlimited MPLS labels) */ -+} ioc_fm_pcd_manip_hdr_insrt_specific_l2; -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description Enumeration type for selecting QoS mapping mode -+ -+ Note: In all cases except 'e_FM_PCD_MANIP_HDR_QOS_MAPPING_NONE' -+ User should instruct the port to read the parser-result -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_hdr_qos_mapping_mode { -+ e_IOC_FM_PCD_MANIP_HDR_QOS_MAPPING_NONE = 0, /**< No mapping, QoS field will not be changed */ -+ e_IOC_FM_PCD_MANIP_HDR_QOS_MAPPING_AS_IS, /**< QoS field will be overwritten by the last byte in the parser-result. */ -+} ioc_fm_pcd_manip_hdr_qos_mapping_mode; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting QoS source -+ -+ Note: In all cases except 'e_FM_PCD_MANIP_HDR_QOS_SRC_NONE' -+ User should left room for the parser-result on input/output buffer -+ and instruct the port to read/write the parser-result to the buffer (RPD should be set) -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_hdr_qos_src { -+ e_IOC_FM_PCD_MANIP_HDR_QOS_SRC_NONE = 0, /**< TODO */ -+ e_IOC_FM_PCD_MANIP_HDR_QOS_SRC_USER_DEFINED, /**< QoS will be taken from the last byte in the parser-result. */ -+} ioc_fm_pcd_manip_hdr_qos_src; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of header insertion -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_hdr_insrt_by_hdr_type { -+ e_IOC_FM_PCD_MANIP_INSRT_BY_HDR_SPECIFIC_L2, /**< Specific L2 fields insertion */ -+#if (DPAA_VERSION >= 11) -+ e_IOC_FM_PCD_MANIP_INSRT_BY_HDR_IP, /**< IP insertion */ -+ e_IOC_FM_PCD_MANIP_INSRT_BY_HDR_UDP, /**< UDP insertion */ -+ e_IOC_FM_PCD_MANIP_INSRT_BY_HDR_UDP_LITE, /**< UDP lite insertion */ -+ e_IOC_FM_PCD_MANIP_INSRT_BY_HDR_CAPWAP /**< CAPWAP insertion */ -+#endif /* (DPAA_VERSION >= 11) */ -+} ioc_fm_pcd_manip_hdr_insrt_by_hdr_type; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting specific custom command -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_hdr_custom_type { -+ e_IOC_FM_PCD_MANIP_HDR_CUSTOM_IP_REPLACE, /**< Replace IPv4/IPv6 */ -+} ioc_fm_pcd_manip_hdr_custom_type; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting specific custom command -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_hdr_custom_ip_replace { -+ e_IOC_FM_PCD_MANIP_HDR_CUSTOM_REPLACE_IPV4_BY_IPV6, /**< Replace IPv4 by IPv6 */ -+ e_IOC_FM_PCD_MANIP_HDR_CUSTOM_REPLACE_IPV6_BY_IPV4 /**< Replace IPv6 by IPv4 */ -+} ioc_fm_pcd_manip_hdr_custom_ip_replace; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of header removal -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_hdr_rmv_by_hdr_type { -+ e_IOC_FM_PCD_MANIP_RMV_BY_HDR_SPECIFIC_L2 = 0, /**< Specific L2 fields removal */ -+#if (DPAA_VERSION >= 11) -+ e_IOC_FM_PCD_MANIP_RMV_BY_HDR_CAPWAP, /**< CAPWAP removal */ -+#endif /* (DPAA_VERSION >= 11) */ -+#if (DPAA_VERSION >= 11) || ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+ e_IOC_FM_PCD_MANIP_RMV_BY_HDR_FROM_START, /**< Locate from data that is not the header */ -+#endif /* (DPAA_VERSION >= 11) || ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */ -+} ioc_fm_pcd_manip_hdr_rmv_by_hdr_type; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of timeout mode -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_reassem_time_out_mode { -+ e_IOC_FM_PCD_MANIP_TIME_OUT_BETWEEN_FRAMES, /**< Limits the time of the reassembly process -+ from the first fragment to the last */ -+ e_IOC_FM_PCD_MANIP_TIME_OUT_BETWEEN_FRAG /**< Limits the time of receiving the fragment */ -+} ioc_fm_pcd_manip_reassem_time_out_mode; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of WaysNumber mode -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_reassem_ways_number { -+ e_IOC_FM_PCD_MANIP_ONE_WAY_HASH = 1, /**< One way hash */ -+ e_IOC_FM_PCD_MANIP_TWO_WAYS_HASH, /**< Two ways hash */ -+ e_IOC_FM_PCD_MANIP_THREE_WAYS_HASH, /**< Three ways hash */ -+ e_IOC_FM_PCD_MANIP_FOUR_WAYS_HASH, /**< Four ways hash */ -+ e_IOC_FM_PCD_MANIP_FIVE_WAYS_HASH, /**< Five ways hash */ -+ e_IOC_FM_PCD_MANIP_SIX_WAYS_HASH, /**< Six ways hash */ -+ e_IOC_FM_PCD_MANIP_SEVEN_WAYS_HASH, /**< Seven ways hash */ -+ e_IOC_FM_PCD_MANIP_EIGHT_WAYS_HASH /**< Eight ways hash */ -+} ioc_fm_pcd_manip_reassem_ways_number; -+ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of statistics mode -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_stats { -+ e_IOC_FM_PCD_STATS_PER_FLOWID = 0 /**< Flow ID is used as index for getting statistics */ -+} ioc_fm_pcd_stats; -+#endif -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting manipulation type -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_type { -+ e_IOC_FM_PCD_MANIP_HDR = 0, /**< Header manipulation */ -+ e_IOC_FM_PCD_MANIP_REASSEM, /**< Reassembly */ -+ e_IOC_FM_PCD_MANIP_FRAG, /**< Fragmentation */ -+ e_IOC_FM_PCD_MANIP_SPECIAL_OFFLOAD /**< Special Offloading */ -+} ioc_fm_pcd_manip_type; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of statistics mode -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_cc_stats_mode { -+ e_IOC_FM_PCD_CC_STATS_MODE_NONE = 0, /**< No statistics support */ -+ e_IOC_FM_PCD_CC_STATS_MODE_FRAME, /**< Frame count statistics */ -+ e_IOC_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME, /**< Byte and frame count statistics */ -+#if (DPAA_VERSION >= 11) -+ e_IOC_FM_PCD_CC_STATS_MODE_RMON, /**< Byte and frame length range count statistics */ -+#endif /* (DPAA_VERSION >= 11) */ -+} ioc_fm_pcd_cc_stats_mode; -+ -+/**************************************************************************//** -+ @Description Enumeration type for determining the action in case an IP packet -+ is larger than MTU but its DF (Don't Fragment) bit is set. -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_dont_frag_action { -+ e_IOC_FM_PCD_MANIP_DISCARD_PACKET = 0, /**< Discard packet */ -+ e_IOC_FM_PCD_MANIP_ENQ_TO_ERR_Q_OR_DISCARD_PACKET = e_IOC_FM_PCD_MANIP_DISCARD_PACKET, -+ /**< Obsolete, cannot enqueue to error queue; -+ In practice, selects to discard packets; -+ Will be removed in the future */ -+ e_IOC_FM_PCD_MANIP_FRAGMENT_PACKECT, /**< Fragment packet and continue normal processing */ -+ e_IOC_FM_PCD_MANIP_CONTINUE_WITHOUT_FRAG /**< Continue normal processing without fragmenting the packet */ -+} ioc_fm_pcd_manip_dont_frag_action; -+ -+/**************************************************************************//** -+ @Description Enumeration type for selecting type of special offload manipulation -+*//***************************************************************************/ -+typedef enum ioc_fm_pcd_manip_special_offload_type { -+ e_IOC_FM_PCD_MANIP_SPECIAL_OFFLOAD_IPSEC, /**< IPSec offload manipulation */ -+#if (DPAA_VERSION >= 11) -+ e_IOC_FM_PCD_MANIP_SPECIAL_OFFLOAD_CAPWAP /**< CAPWAP offload manipulation */ -+#endif /* (DPAA_VERSION >= 11) */ -+} ioc_fm_pcd_manip_special_offload_type; -+ -+/**************************************************************************//** -+ @Description A union of protocol dependent special options -+ (Must match union u_FmPcdHdrProtocolOpt defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef union ioc_fm_pcd_hdr_protocol_opt_u { -+ ioc_eth_protocol_opt_t eth_opt; /**< Ethernet options */ -+ ioc_vlan_protocol_opt_t vlan_opt; /**< Vlan options */ -+ ioc_mpls_protocol_opt_t mpls_opt; /**< MPLS options */ -+ ioc_ipv4_protocol_opt_t ipv4_opt; /**< IPv4 options */ -+ ioc_ipv6_protocol_opt_t ipv6_opt; /**< IPv6 options */ -+#if (DPAA_VERSION >= 11) -+ ioc_capwap_protocol_opt_t capwap_opt; /**< CAPWAP options */ -+#endif /* (DPAA_VERSION >= 11) */ -+} ioc_fm_pcd_hdr_protocol_opt_u; -+ -+/**************************************************************************//** -+ @Description A union holding all known protocol fields -+*//***************************************************************************/ -+typedef union ioc_fm_pcd_fields_u { -+ ioc_header_field_eth_t eth; /**< Ethernet */ -+ ioc_header_field_vlan_t vlan; /**< VLAN */ -+ ioc_header_field_llc_snap_t llc_snap; /**< LLC SNAP */ -+ ioc_header_field_pppoe_t pppoe; /**< PPPoE */ -+ ioc_header_field_mpls_t mpls; /**< MPLS */ -+ ioc_header_field_ip_t ip; /**< IP */ -+ ioc_header_field_ipv4_t ipv4; /**< IPv4 */ -+ ioc_header_field_ipv6_t ipv6; /**< IPv6 */ -+ ioc_header_field_udp_t udp; /**< UDP */ -+ ioc_header_field_udp_lite_t udp_lite; /**< UDP_Lite */ -+ ioc_header_field_tcp_t tcp; /**< TCP */ -+ ioc_header_field_sctp_t sctp; /**< SCTP */ -+ ioc_header_field_dccp_t dccp; /**< DCCP */ -+ ioc_header_field_gre_t gre; /**< GRE */ -+ ioc_header_field_minencap_t minencap; /**< Minimal Encapsulation */ -+ ioc_header_field_ipsec_ah_t ipsec_ah; /**< IPSec AH */ -+ ioc_header_field_ipsec_esp_t ipsec_esp; /**< IPSec ESP */ -+ ioc_header_field_udp_encap_esp_t udp_encap_esp; /**< UDP Encapsulation ESP */ -+} ioc_fm_pcd_fields_u; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header extraction for key generation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_from_hdr_t { -+ uint8_t size; /**< Size in byte */ -+ uint8_t offset; /**< Byte offset */ -+} ioc_fm_pcd_from_hdr_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining field extraction for key generation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_from_field_t { -+ ioc_fm_pcd_fields_u field; /**< Field selection */ -+ uint8_t size; /**< Size in byte */ -+ uint8_t offset; /**< Byte offset */ -+} ioc_fm_pcd_from_field_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a single network environment unit -+ A distinction unit should be defined if it will later be used -+ by one or more PCD engines to distinguish between flows. -+ (Must match struct t_FmPcdDistinctionUnit defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_distinction_unit_t { -+ struct { -+ ioc_net_header_type hdr; /**< One of the headers supported by the FM */ -+ ioc_fm_pcd_hdr_protocol_opt_u opt; /**< Select only one option! */ -+ } hdrs[IOC_FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS]; -+} ioc_fm_pcd_distinction_unit_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining all different distinction units supported -+ by a specific PCD Network Environment Characteristics module. -+ -+ Each unit represent a protocol or a group of protocols that may -+ be used later by the different PCD engines to distinguish between flows. -+ (Must match struct t_FmPcdNetEnvParams defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_net_env_params_t { -+ uint8_t num_of_distinction_units;/**< Number of different units to be identified */ -+ ioc_fm_pcd_distinction_unit_t units[IOC_FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; -+ /**< An array of num_of_distinction_units of the -+ different units to be identified */ -+ void *id; /**< Output parameter; Returns the net-env Id to be used */ -+} ioc_fm_pcd_net_env_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a single extraction action when -+ creating a key -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_extract_entry_t { -+ ioc_fm_pcd_extract_type type; /**< Extraction type select */ -+ union { -+ struct { -+ ioc_net_header_type hdr; /**< Header selection */ -+ bool ignore_protocol_validation; -+ /**< Ignore protocol validation */ -+ ioc_fm_pcd_hdr_index hdr_index; /**< Relevant only for MPLS, VLAN and tunneled -+ IP. Otherwise should be cleared.*/ -+ ioc_fm_pcd_extract_by_hdr_type type; /**< Header extraction type select */ -+ union { -+ ioc_fm_pcd_from_hdr_t from_hdr; /**< Extract bytes from header parameters */ -+ ioc_fm_pcd_from_field_t from_field; /**< Extract bytes from field parameters */ -+ ioc_fm_pcd_fields_u full_field; /**< Extract full field parameters */ -+ } extract_by_hdr_type; -+ } extract_by_hdr; /**< Used when type = e_IOC_FM_PCD_KG_EXTRACT_BY_HDR */ -+ struct { -+ ioc_fm_pcd_extract_from src; /**< Non-header extraction source */ -+ ioc_fm_pcd_action action; /**< Relevant for CC Only */ -+ uint16_t ic_indx_mask; /**< Relevant only for CC when -+ action = e_IOC_FM_PCD_ACTION_INDEXED_LOOKUP; -+ Note that the number of bits that are set within -+ this mask must be log2 of the CC-node 'num_of_keys'. -+ Note that the mask cannot be set on the lower bits. */ -+ uint8_t offset; /**< Byte offset */ -+ uint8_t size; /**< Size in bytes */ -+ } extract_non_hdr; /**< Used when type = e_IOC_FM_PCD_KG_EXTRACT_NON_HDR */ -+ } extract_params; -+} ioc_fm_pcd_extract_entry_t; -+ -+/**************************************************************************//** -+ @Description A structure for defining masks for each extracted -+ field in the key. -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_kg_extract_mask_t { -+ uint8_t extract_array_index; /**< Index in the extraction array, as initialized by user */ -+ uint8_t offset; /**< Byte offset */ -+ uint8_t mask; /**< A byte mask (selected bits will be ignored) */ -+} ioc_fm_pcd_kg_extract_mask_t; -+ -+/**************************************************************************//** -+ @Description A structure for defining default selection per groups -+ of fields -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_kg_extract_dflt_t { -+ ioc_fm_pcd_kg_known_fields_dflt_types type; /**< Default type select*/ -+ ioc_fm_pcd_kg_extract_dflt_select dflt_select; /**< Default register select */ -+} ioc_fm_pcd_kg_extract_dflt_t; -+ -+ -+/**************************************************************************//** -+ @Description A structure for defining all parameters needed for -+ generation a key and using a hash function -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_kg_key_extract_and_hash_params_t { -+ uint32_t private_dflt0; /**< Scheme default register 0 */ -+ uint32_t private_dflt1; /**< Scheme default register 1 */ -+ uint8_t num_of_used_extracts; /**< defines the valid size of the following array */ -+ ioc_fm_pcd_extract_entry_t extract_array [IOC_FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY]; -+ /**< An array of extraction definitions. */ -+ uint8_t num_of_used_dflts; /**< defines the valid size of the following array */ -+ ioc_fm_pcd_kg_extract_dflt_t dflts[IOC_FM_PCD_KG_NUM_OF_DEFAULT_GROUPS]; -+ /**< For each extraction used in this scheme, specify the required -+ default register to be used when header is not found. -+ types not specified in this array will get undefined value. */ -+ uint8_t num_of_used_masks; /**< Defines the valid size of the following array */ -+ ioc_fm_pcd_kg_extract_mask_t masks[IOC_FM_PCD_KG_NUM_OF_EXTRACT_MASKS]; -+ uint8_t hash_shift; /**< Hash result right shift. -+ Selects the 24 bits out of the 64 hash result. -+ 0 means using the 24 LSB's, otherwise use the -+ 24 LSB's after shifting right.*/ -+ uint32_t hash_distribution_num_of_fqids; /**< must be > 1 and a power of 2. Represents the range -+ of queues for the key and hash functionality */ -+ uint8_t hash_distribution_fqids_shift; /**< selects the FQID bits that will be effected by the hash */ -+ bool symmetric_hash; /**< TRUE to generate the same hash for frames with swapped source and -+ destination fields on all layers; If TRUE, driver will check that for -+ all layers, if SRC extraction is selected, DST extraction must also be -+ selected, and vice versa. */ -+} ioc_fm_pcd_kg_key_extract_and_hash_params_t; -+ -+/**************************************************************************//** -+ @Description A structure of parameters for defining a single -+ Qid mask (extracted OR). -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_kg_extracted_or_params_t { -+ ioc_fm_pcd_extract_type type; /**< Extraction type select */ -+ union { -+ struct { /**< used when type = e_IOC_FM_PCD_KG_EXTRACT_BY_HDR */ -+ ioc_net_header_type hdr; -+ ioc_fm_pcd_hdr_index hdr_index; /**< Relevant only for MPLS, VLAN and tunneled -+ IP. Otherwise should be cleared.*/ -+ bool ignore_protocol_validation; -+ -+ } extract_by_hdr; -+ ioc_fm_pcd_extract_from src; /**< used when type = e_IOC_FM_PCD_KG_EXTRACT_NON_HDR */ -+ } extract_params; -+ uint8_t extraction_offset; /**< Offset for extraction */ -+ ioc_fm_pcd_kg_extract_dflt_select dflt_value; /**< Select register from which extraction is taken if -+ field not found */ -+ uint8_t mask; /**< Mask LSB byte of extraction (specified bits are ignored) */ -+ uint8_t bit_offset_in_fqid; /**< 0-31, Selects which bits of the 24 FQID bits to effect using -+ the extracted byte; Assume byte is placed as the 8 MSB's in -+ a 32 bit word where the lower bits -+ are the FQID; i.e if bitOffsetInFqid=1 than its LSB -+ will effect the FQID MSB, if bitOffsetInFqid=24 than the -+ extracted byte will effect the 8 LSB's of the FQID, -+ if bitOffsetInFqid=31 than the byte's MSB will effect -+ the FQID's LSB; 0 means - no effect on FQID; -+ Note that one, and only one of -+ bitOffsetInFqid or bitOffsetInPlcrProfile must be set (i.e, -+ extracted byte must effect either FQID or Policer profile).*/ -+ uint8_t bit_offset_in_plcr_profile; -+ /**< 0-15, Selects which bits of the 8 policer profile id bits to -+ effect using the extracted byte; Assume byte is placed -+ as the 8 MSB's in a 16 bit word where the lower bits -+ are the policer profile id; i.e if bitOffsetInPlcrProfile=1 -+ than its LSB will effect the profile MSB, if bitOffsetInFqid=8 -+ than the extracted byte will effect the whole policer profile id, -+ if bitOffsetInFqid=15 than the byte's MSB will effect -+ the Policer Profile id's LSB; -+ 0 means - no effect on policer profile; Note that one, and only one of -+ bitOffsetInFqid or bitOffsetInPlcrProfile must be set (i.e, -+ extracted byte must effect either FQID or Policer profile).*/ -+} ioc_fm_pcd_kg_extracted_or_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for configuring scheme counter -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_kg_scheme_counter_t { -+ bool update; /**< FALSE to keep the current counter state -+ and continue from that point, TRUE to update/reset -+ the counter when the scheme is written. */ -+ uint32_t value; /**< If update=TRUE, this value will be written into the -+ counter; clear this field to reset the counter. */ -+} ioc_fm_pcd_kg_scheme_counter_t; -+ -+ -+/**************************************************************************//** -+ @Description A structure for retrieving FMKG_SE_SPC -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_kg_scheme_spc_t { -+ uint32_t val; /**< return value */ -+ void *id; /**< scheme handle */ -+} ioc_fm_pcd_kg_scheme_spc_t; -+ -+/**************************************************************************//** -+ @Description A structure for defining policer profile parameters as required by keygen -+ (when policer is the next engine after this scheme). -+ (Must match struct t_FmPcdKgPlcrProfile defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_kg_plcr_profile_t { -+ bool shared_profile; /**< TRUE if this profile is shared between ports -+ (i.e. managed by master partition) May not be TRUE -+ if profile is after Coarse Classification*/ -+ bool direct; /**< If TRUE, direct_relative_profile_id only selects the profile -+ id, if FALSE fqid_offset_relative_profile_id_base is used -+ together with fqid_offset_shift and num_of_profiles -+ parameters, to define a range of profiles from -+ which the KeyGen result will determine the -+ destination policer profile. */ -+ union { -+ uint16_t direct_relative_profile_id; /**< Used if 'direct' is TRUE, to select policer profile. -+ This parameter should indicate the policer profile offset within the port's -+ policer profiles or SHARED window. */ -+ struct { -+ uint8_t fqid_offset_shift; /**< Shift of KG results without the qid base */ -+ uint8_t fqid_offset_relative_profile_id_base; -+ /**< OR of KG results without the qid base -+ This parameter should indicate the policer profile -+ offset within the port's policer profiles window -+ or SHARED window depends on shared_profile */ -+ uint8_t num_of_profiles; /**< Range of profiles starting at base */ -+ } indirect_profile; /**< Indirect profile parameters */ -+ } profile_select; /**< Direct/indirect profile selection and parameters */ -+} ioc_fm_pcd_kg_plcr_profile_t; -+ -+#if DPAA_VERSION >= 11 -+/**************************************************************************//** -+ @Description Parameters for configuring a storage profile for a KeyGen scheme. -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_kg_storage_profile_t { -+ bool direct; /**< If TRUE, directRelativeProfileId only selects the -+ profile id; -+ If FALSE, fqidOffsetRelativeProfileIdBase is used -+ together with fqidOffsetShift and numOfProfiles -+ parameters to define a range of profiles from which -+ the KeyGen result will determine the destination -+ storage profile. */ -+ union { -+ uint16_t direct_relative_profileId; /**< Used when 'direct' is TRUE, to select a storage profile; -+ should indicate the storage profile offset within the -+ port's storage profiles window. */ -+ struct { -+ uint8_t fqid_offset_shift; /**< Shift of KeyGen results without the FQID base */ -+ uint8_t fqid_offset_relative_profile_id_base; -+ /**< OR of KeyGen results without the FQID base; -+ should indicate the policer profile offset within the -+ port's storage profiles window. */ -+ uint8_t num_of_profiles; /**< Range of profiles starting at base. */ -+ } indirect_profile; /**< Indirect profile parameters. */ -+ } profile_select; /**< Direct/indirect profile selection and parameters. */ -+} ioc_fm_pcd_kg_storage_profile_t; -+#endif /* DPAA_VERSION >= 11 */ -+ -+/**************************************************************************//** -+ @Description Parameters for defining CC as the next engine after KeyGen -+ (Must match struct t_FmPcdKgCc defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_kg_cc_t { -+ void *tree_id; /**< CC Tree id */ -+ uint8_t grp_id; /**< CC group id within the CC tree */ -+ bool plcr_next; /**< TRUE if after CC, in case of data frame, -+ policing is required. */ -+ bool bypass_plcr_profile_generation; -+ /**< TRUE to bypass KeyGen policer profile generation; -+ selected profile is the one set at port initialization. */ -+ ioc_fm_pcd_kg_plcr_profile_t plcr_profile; /**< Valid only if plcr_next = TRUE and -+ bypass_plcr_profile_generation = FALSE */ -+} ioc_fm_pcd_kg_cc_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining initializing a KeyGen scheme -+ (Must match struct t_FmPcdKgSchemeParams defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_kg_scheme_params_t { -+ bool modify; /**< TRUE to change an existing scheme */ -+ union { -+ uint8_t relative_scheme_id; -+ /**< if modify=FALSE: partition-relative scheme id */ -+ void *scheme_id; /**< if modify=TRUE: the id of an existing scheme */ -+ } scm_id; -+ bool always_direct; /**< This scheme is reached only directly, i.e. no need -+ for match vector; KeyGen will ignore it when matching */ -+ struct { /**< HL relevant only if always_direct=FALSE */ -+ void *net_env_id; /**< The id of the Network Environment as returned -+ by FM_PCD_NetEnvCharacteristicsSet() */ -+ uint8_t num_of_distinction_units; -+ /**< Number of NetEnv units listed in unit_ids array */ -+ uint8_t unit_ids[IOC_FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; -+ /**< Indexes as passed to SetNetEnvCharacteristics (?) array */ -+ } net_env_params; -+ bool use_hash; /**< use the KG Hash functionality */ -+ ioc_fm_pcd_kg_key_extract_and_hash_params_t key_extract_and_hash_params; -+ /**< used only if useHash = TRUE */ -+ bool bypass_fqid_generation; -+ /**< Normally - FALSE, TRUE to avoid FQID update in the IC; -+ In such a case FQID after KG will be the default FQID -+ defined for the relevant port, or the FQID defined by CC -+ in cases where CC was the previous engine. */ -+ uint32_t base_fqid; /**< Base FQID; Relevant only if bypass_fqid_generation = FALSE; -+ If hash is used and an even distribution is expected -+ according to hash_distribution_num_of_fqids, base_fqid must be aligned to -+ hash_distribution_num_of_fqids. */ -+ uint8_t num_of_used_extracted_ors; -+ /**< Number of FQID masks listed in extracted_ors array*/ -+ ioc_fm_pcd_kg_extracted_or_params_t extracted_ors[IOC_FM_PCD_KG_NUM_OF_GENERIC_REGS]; -+ /**< IOC_FM_PCD_KG_NUM_OF_GENERIC_REGS -+ registers are shared between qid_masks -+ functionality and some of the extraction -+ actions; Normally only some will be used -+ for qid_mask. Driver will return error if -+ resource is full at initialization time. */ -+#if DPAA_VERSION >= 11 -+ bool override_storage_profile; -+ /**< TRUE if KeyGen override previously decided storage profile */ -+ ioc_fm_pcd_kg_storage_profile_t storage_profile;/**< Used when override_storage_profile=TRUE */ -+#endif /* DPAA_VERSION >= 11 */ -+ ioc_fm_pcd_engine next_engine; /**< may be BMI, PLCR or CC */ -+ union { /**< depends on nextEngine */ -+ ioc_fm_pcd_done_action done_action; /**< Used when next engine is BMI (done) */ -+ ioc_fm_pcd_kg_plcr_profile_t plcr_profile; /**< Used when next engine is PLCR */ -+ ioc_fm_pcd_kg_cc_t cc; /**< Used when next engine is CC */ -+ } kg_next_engine_params; -+ ioc_fm_pcd_kg_scheme_counter_t scheme_counter; /**< A structure of parameters for updating -+ the scheme counter */ -+ void *id; /**< Returns the scheme Id to be used */ -+} ioc_fm_pcd_kg_scheme_params_t; -+ -+/**************************************************************************//** -+ @Collection -+*//***************************************************************************/ -+#if DPAA_VERSION >= 11 -+#define IOC_FM_PCD_CC_STATS_MAX_NUM_OF_FLR 10 /* Maximal supported number of frame length ranges */ -+#define IOC_FM_PCD_CC_STATS_FLR_SIZE 2 /* Size in bytes of a frame length range limit */ -+#endif /* DPAA_VERSION >= 11 */ -+#define IOC_FM_PCD_CC_STATS_FLR_COUNT_SIZE 4 /* Size in bytes of a frame length range counter */ -+/* @} */ -+ -+/**************************************************************************//** -+ @Description Parameters for defining CC as the next engine after a CC node. -+ (Must match struct t_FmPcdCcNextCcParams defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_next_cc_params_t { -+ void *cc_node_id; /**< Id of the next CC node */ -+} ioc_fm_pcd_cc_next_cc_params_t; -+ -+#if DPAA_VERSION >= 11 -+/**************************************************************************//** -+ @Description A structure for defining Frame Replicator as the next engine after a CC node. -+ (Must match struct t_FmPcdCcNextFrParams defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_next_fr_params_t { -+ void* frm_replic_id; /**< The id of the next frame replicator group */ -+} ioc_fm_pcd_cc_next_fr_params_t; -+#endif /* DPAA_VERSION >= 11 */ -+ -+/**************************************************************************//** -+ @Description A structure for defining PLCR params when PLCR is the -+ next engine after a CC node -+ (Must match struct t_FmPcdCcNextPlcrParams defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_next_plcr_params_t { -+ bool override_params; /**< TRUE if CC override previously decided parameters*/ -+ bool shared_profile; /**< Relevant only if overrideParams=TRUE: -+ TRUE if this profile is shared between ports */ -+ uint16_t new_relative_profile_id; /**< Relevant only if overrideParams=TRUE: -+ (otherwise profile id is taken from keygen); -+ This parameter should indicate the policer -+ profile offset within the port's -+ policer profiles or from SHARED window.*/ -+ uint32_t new_fqid; /**< Relevant only if overrideParams=TRUE: -+ FQID for enquing the frame; -+ In earlier chips if policer next engine is KEYGEN, -+ this parameter can be 0, because the KEYGEN always decides -+ the enqueue FQID.*/ -+#if DPAA_VERSION >= 11 -+ uint8_t new_relative_storage_profile_id; -+ /**< Indicates the relative storage profile offset within -+ the port's storage profiles window; -+ Relevant only if the port was configured with VSP. */ -+#endif /* DPAA_VERSION >= 11 */ -+} ioc_fm_pcd_cc_next_plcr_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for defining enqueue params when BMI is the -+ next engine after a CC node -+ (Must match struct t_FmPcdCcNextEnqueueParams defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_next_enqueue_params_t { -+ ioc_fm_pcd_done_action action; /**< Action - when next engine is BMI (done) */ -+ bool override_fqid; /**< TRUE if CC override previously decided fqid and vspid, -+ relevant if action = e_IOC_FM_PCD_ENQ_FRAME */ -+ uint32_t new_fqid; /**< Valid if overrideFqid=TRUE, FQID for enqueuing the frame -+ (otherwise FQID is taken from KeyGen), -+ relevant if action = e_IOC_FM_PCD_ENQ_FRAME*/ -+#if DPAA_VERSION >= 11 -+ uint8_t new_relative_storage_profile_id; -+ /**< Valid if override_fqid=TRUE, Indicates the relative virtual -+ storage profile offset within the port's storage profiles -+ window; Relevant only if the port was configured with VSP. */ -+#endif /* DPAA_VERSION >= 11 */ -+ -+} ioc_fm_pcd_cc_next_enqueue_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for defining KG params when KG is the next engine after a CC node -+ (Must match struct t_FmPcdCcNextKgParams defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_next_kg_params_t { -+ bool override_fqid; /**< TRUE if CC override previously decided fqid and vspid, -+ Note - this parameters are irrelevant for earlier chips */ -+ uint32_t new_fqid; /**< Valid if overrideFqid=TRUE, FQID for enqueuing the frame -+ (otherwise FQID is taken from KeyGen), -+ Note - this parameters are irrelevant for earlier chips */ -+#if DPAA_VERSION >= 11 -+ uint8_t new_relative_storage_profile_id; -+ /**< Valid if override_fqid=TRUE, Indicates the relative virtual -+ storage profile offset within the port's storage profiles -+ window; Relevant only if the port was configured with VSP. */ -+#endif /* DPAA_VERSION >= 11 */ -+ void *p_direct_scheme; /**< Direct scheme id to go to. */ -+} ioc_fm_pcd_cc_next_kg_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining the next engine after a CC node. -+ (Must match struct t_FmPcdCcNextEngineParams defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_next_engine_params_t { -+ ioc_fm_pcd_engine next_engine; /**< User has to initialize parameters -+ according to nextEngine definition */ -+ union { -+ ioc_fm_pcd_cc_next_cc_params_t cc_params; /**< Parameters in case next engine is CC */ -+ ioc_fm_pcd_cc_next_plcr_params_t plcr_params; /**< Parameters in case next engine is PLCR */ -+ ioc_fm_pcd_cc_next_enqueue_params_t enqueue_params; /**< Parameters in case next engine is BMI */ -+ ioc_fm_pcd_cc_next_kg_params_t kg_params; /**< Parameters in case next engine is KG */ -+#if DPAA_VERSION >= 11 -+ ioc_fm_pcd_cc_next_fr_params_t fr_params; /**< Parameters in case next engine is FR */ -+#endif /* DPAA_VERSION >= 11 */ -+ } params; /**< Union used for all the next-engine parameters options */ -+ void *manip_id; /**< Handle to Manipulation object. -+ Relevant if next engine is of type result -+ (e_IOC_FM_PCD_PLCR, e_IOC_FM_PCD_KG, e_IOC_FM_PCD_DONE) */ -+ bool statistics_en; /**< If TRUE, statistics counters are incremented -+ for each frame passing through this -+ Coarse Classification entry. */ -+} ioc_fm_pcd_cc_next_engine_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a single CC key -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_key_params_t { -+ uint8_t *p_key; /**< pointer to the key of the size defined in key_size */ -+ uint8_t *p_mask; /**< pointer to the Mask per key of the size defined -+ in keySize. p_key and p_mask (if defined) has to be -+ of the same size defined in the key_size */ -+ ioc_fm_pcd_cc_next_engine_params_t cc_next_engine_params; -+ /**< parameters for the next for the defined Key in p_key */ -+ -+} ioc_fm_pcd_cc_key_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining CC keys parameters -+ The driver supports two methods for CC node allocation: dynamic and static. -+ Static mode was created in order to prevent runtime alloc/free -+ of FMan memory (MURAM), which may cause fragmentation; in this mode, -+ the driver automatically allocates the memory according to -+ 'max_num_of_keys' parameter. The driver calculates the maximal memory -+ size that may be used for this CC-Node taking into consideration -+ 'mask_support' and 'statistics_mode' parameters. -+ When 'action' = e_IOC_FM_PCD_ACTION_INDEXED_LOOKUP in the extraction -+ parameters of this node, 'max_num_of_keys' must be equal to 'num_of_keys'. -+ In dynamic mode, 'max_num_of_keys' must be zero. At initialization, -+ all required structures are allocated according to 'num_of_keys' -+ parameter. During runtime modification, these structures are -+ re-allocated according to the updated number of keys. -+ -+ Please note that 'action' and 'ic_indx_mask' mentioned in the -+ specific parameter explanations are passed in the extraction -+ parameters of the node (fields of extractccparams.extractnonhdr). -+*//***************************************************************************/ -+typedef struct ioc_keys_params_t { -+ uint16_t max_num_of_keys;/**< Maximum number of keys that will (ever) be used in this CC-Node; -+ A value of zero may be used for dynamic memory allocation. */ -+ bool mask_support; /**< This parameter is relevant only if a node is initialized with -+ action = e_IOC_FM_PCD_ACTION_EXACT_MATCH and max_num_of_keys > 0; -+ Should be TRUE to reserve table memory for key masks, even if -+ initial keys do not contain masks, or if the node was initialized -+ as 'empty' (without keys); this will allow user to add keys with -+ masks at runtime. */ -+ ioc_fm_pcd_cc_stats_mode statistics_mode;/**< Determines the supported statistics mode for all node's keys. -+ To enable statistics gathering, statistics should be enabled per -+ every key, using 'statistics_en' in next engine parameters structure -+ of that key; -+ If 'max_num_of_keys' is set, all required structures will be -+ preallocated for all keys. */ -+#if (DPAA_VERSION >= 11) -+ uint16_t frame_length_ranges[IOC_FM_PCD_CC_STATS_MAX_NUM_OF_FLR]; -+ /**< Relevant only for 'RMON' statistics mode -+ (this feature is supported only on B4860 device); -+ Holds a list of programmable thresholds. For each received frame, -+ its length in bytes is examined against these range thresholds and -+ the appropriate counter is incremented by 1. For example, to belong -+ to range i, the following should hold: -+ range i-1 threshold < frame length <= range i threshold -+ Each range threshold must be larger then its preceding range -+ threshold. Last range threshold must be 0xFFFF. */ -+#endif /* (DPAA_VERSION >= 11) */ -+ uint16_t num_of_keys; /**< Number of initial keys; -+ Note that in case of 'action' = e_IOC_FM_PCD_ACTION_INDEXED_LOOKUP, -+ this field should be power-of-2 of the number of bits that are -+ set in 'ic_indx_mask'. */ -+ uint8_t key_size; /**< Size of key - for extraction of type FULL_FIELD, 'key_size' has -+ to be the standard size of the selected key; For other extraction -+ types, 'key_size' has to be as size of extraction; When 'action' = -+ e_IOC_FM_PCD_ACTION_INDEXED_LOOKUP, 'keySize' must be 2. */ -+ ioc_fm_pcd_cc_key_params_t key_params[IOC_FM_PCD_MAX_NUM_OF_KEYS]; -+ /**< An array with 'num_of_keys' entries, each entry specifies the -+ corresponding key parameters; -+ When 'action' = e_IOC_FM_PCD_ACTION_EXACT_MATCH, this value must not -+ exceed 255 (IOC_FM_PCD_MAX_NUM_OF_KEYS-1) as the last entry is saved -+ for the 'miss' entry. */ -+ ioc_fm_pcd_cc_next_engine_params_t cc_next_engine_params_for_miss; -+ /**< Parameters for defining the next engine when a key is not matched; -+ Not relevant if action = e_IOC_FM_PCD_ACTION_INDEXED_LOOKUP. */ -+} ioc_keys_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a CC node -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_node_params_t { -+ ioc_fm_pcd_extract_entry_t extract_cc_params; /**< Extraction parameters */ -+ ioc_keys_params_t keys_params; /**< Keys definition matching the selected extraction */ -+ void *id; /**< Output parameter; returns the CC node Id to be used */ -+} ioc_fm_pcd_cc_node_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a hash table -+ (Must match struct t_FmPcdHashTableParams defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_hash_table_params_t { -+ uint16_t max_num_of_keys; /**< Maximum Number Of Keys that will (ever) be used in this Hash-table */ -+ ioc_fm_pcd_cc_stats_mode statistics_mode; /**< If not e_IOC_FM_PCD_CC_STATS_MODE_NONE, the required structures for the -+ requested statistics mode will be allocated according to max_num_of_keys. */ -+ uint8_t kg_hash_shift; /**< KG-Hash-shift as it was configured in the KG-scheme -+ that leads to this hash-table. */ -+ uint16_t hash_res_mask; /**< Mask that will be used on the hash-result; -+ The number-of-sets for this hash will be calculated -+ as (2^(number of bits set in 'hash_res_mask')); -+ The 4 lower bits must be cleared. */ -+ uint8_t hash_shift; /**< Byte offset from the beginning of the KeyGen hash result to the -+ 2-bytes to be used as hash index. */ -+ uint8_t match_key_size; /**< Size of the exact match keys held by the hash buckets */ -+ -+ ioc_fm_pcd_cc_next_engine_params_t cc_next_engine_params_for_miss; -+ /**< Parameters for defining the next engine when a key is not matched */ -+ void *id; -+} ioc_fm_pcd_hash_table_params_t; -+ -+/**************************************************************************//** -+ @Description A structure with the arguments for the FM_PCD_HashTableAddKey ioctl() call -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_hash_table_add_key_params_t { -+ void *p_hash_tbl; -+ uint8_t key_size; -+ ioc_fm_pcd_cc_key_params_t key_params; -+} ioc_fm_pcd_hash_table_add_key_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a CC tree group. -+ -+ This structure defines a CC group in terms of NetEnv units -+ and the action to be taken in each case. The unit_ids list must -+ be given in order from low to high indices. -+ -+ ioc_fm_pcd_cc_next_engine_params_t is a list of 2^num_of_distinction_units -+ structures where each defines the next action to be taken for -+ each units combination. for example: -+ num_of_distinction_units = 2 -+ unit_ids = {1,3} -+ next_engine_per_entries_in_grp[0] = ioc_fm_pcd_cc_next_engine_params_t for the case that -+ unit 1 - not found; unit 3 - not found; -+ next_engine_per_entries_in_grp[1] = ioc_fm_pcd_cc_next_engine_params_t for the case that -+ unit 1 - not found; unit 3 - found; -+ next_engine_per_entries_in_grp[2] = ioc_fm_pcd_cc_next_engine_params_t for the case that -+ unit 1 - found; unit 3 - not found; -+ next_engine_per_entries_in_grp[3] = ioc_fm_pcd_cc_next_engine_params_t for the case that -+ unit 1 - found; unit 3 - found; -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_grp_params_t { -+ uint8_t num_of_distinction_units; /**< Up to 4 */ -+ uint8_t unit_ids [IOC_FM_PCD_MAX_NUM_OF_CC_UNITS]; -+ /**< Indexes of the units as defined in -+ FM_PCD_NetEnvCharacteristicsSet() */ -+ ioc_fm_pcd_cc_next_engine_params_t next_engine_per_entries_in_grp[IOC_FM_PCD_MAX_NUM_OF_CC_ENTRIES_IN_GRP]; -+ /**< Maximum entries per group is 16 */ -+} ioc_fm_pcd_cc_grp_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining the CC tree groups -+ (Must match struct t_FmPcdCcTreeParams defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_tree_params_t { -+ void *net_env_id; /**< Id of the Network Environment as returned -+ by FM_PCD_NetEnvCharacteristicsSet() */ -+ uint8_t num_of_groups; /**< Number of CC groups within the CC tree */ -+ ioc_fm_pcd_cc_grp_params_t fm_pcd_cc_group_params [IOC_FM_PCD_MAX_NUM_OF_CC_GROUPS]; -+ /**< Parameters for each group. */ -+ void *id; /**< Output parameter; Returns the tree Id to be used */ -+} ioc_fm_pcd_cc_tree_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining policer byte rate -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_plcr_byte_rate_mode_param_t { -+ ioc_fm_pcd_plcr_frame_length_select frame_length_selection; /**< Frame length selection */ -+ ioc_fm_pcd_plcr_roll_back_frame_select roll_back_frame_selection; /**< relevant option only e_IOC_FM_PCD_PLCR_L2_FRM_LEN, -+ e_IOC_FM_PCD_PLCR_FULL_FRM_LEN */ -+} ioc_fm_pcd_plcr_byte_rate_mode_param_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining the policer profile (based on -+ RFC-2698 or RFC-4115 attributes). -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_plcr_non_passthrough_alg_param_t { -+ ioc_fm_pcd_plcr_rate_mode rate_mode; /**< Byte / Packet */ -+ ioc_fm_pcd_plcr_byte_rate_mode_param_t byte_mode_param; /**< Valid for Byte NULL for Packet */ -+ uint32_t committed_info_rate; /**< KBits/Sec or Packets/Sec */ -+ uint32_t committed_burst_size; /**< KBits or Packets */ -+ uint32_t peak_or_excess_info_rate; /**< KBits/Sec or Packets/Sec */ -+ uint32_t peak_or_excess_burst_size; /**< KBits or Packets */ -+} ioc_fm_pcd_plcr_non_passthrough_alg_param_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining the next engine after policer -+*//***************************************************************************/ -+typedef union ioc_fm_pcd_plcr_next_engine_params_u { -+ ioc_fm_pcd_done_action action; /**< Action - when next engine is BMI (done) */ -+ void *p_profile; /**< Policer profile handle - used when next engine -+ is PLCR, must be a SHARED profile */ -+ void *p_direct_scheme; /**< Direct scheme select - when next engine is Keygen */ -+} ioc_fm_pcd_plcr_next_engine_params_u; -+ -+typedef struct ioc_fm_pcd_port_params_t { -+ ioc_fm_port_type port_type; /**< Type of port for this profile */ -+ uint8_t port_id; /**< FM-Port id of port for this profile */ -+} ioc_fm_pcd_port_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining the policer profile entry -+ (Must match struct t_FmPcdPlcrProfileParams defined in fm_pcd_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_plcr_profile_params_t { -+ bool modify; /**< TRUE to change an existing profile */ -+ union { -+ struct { -+ ioc_fm_pcd_profile_type_selection profile_type; /**< Type of policer profile */ -+ ioc_fm_pcd_port_params_t *p_fm_port; /**< Relevant for per-port profiles only */ -+ uint16_t relative_profile_id; /**< Profile id - relative to shared group or to port */ -+ } new_params; /**< Use it when modify = FALSE */ -+ void *p_profile; /**< A handle to a profile - use it when modify=TRUE */ -+ } profile_select; -+ ioc_fm_pcd_plcr_algorithm_selection alg_selection; /**< Profile Algorithm PASS_THROUGH, RFC_2698, RFC_4115 */ -+ ioc_fm_pcd_plcr_color_mode color_mode; /**< COLOR_BLIND, COLOR_AWARE */ -+ -+ union { -+ ioc_fm_pcd_plcr_color dflt_color; /**< For Color-Blind Pass-Through mode; the policer will re-color -+ any incoming packet with the default value. */ -+ ioc_fm_pcd_plcr_color override; /**< For Color-Aware modes; the profile response to a -+ pre-color value of 2'b11. */ -+ } color; -+ -+ ioc_fm_pcd_plcr_non_passthrough_alg_param_t non_passthrough_alg_param; /**< RFC2698 or RFC4115 parameters */ -+ -+ ioc_fm_pcd_engine next_engine_on_green; /**< Next engine for green-colored frames */ -+ ioc_fm_pcd_plcr_next_engine_params_u params_on_green; /**< Next engine parameters for green-colored frames */ -+ -+ ioc_fm_pcd_engine next_engine_on_yellow; /**< Next engine for yellow-colored frames */ -+ ioc_fm_pcd_plcr_next_engine_params_u params_on_yellow; /**< Next engine parameters for yellow-colored frames */ -+ -+ ioc_fm_pcd_engine next_engine_on_red; /**< Next engine for red-colored frames */ -+ ioc_fm_pcd_plcr_next_engine_params_u params_on_red; /**< Next engine parameters for red-colored frames */ -+ -+ bool trap_profile_on_flow_A; /**< Obsolete - do not use */ -+ bool trap_profile_on_flow_B; /**< Obsolete - do not use */ -+ bool trap_profile_on_flow_C; /**< Obsolete - do not use */ -+ -+ void *id; /**< output parameter; Returns the profile Id to be used */ -+} ioc_fm_pcd_plcr_profile_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for modifying CC tree next engine -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_tree_modify_next_engine_params_t { -+ void *id; /**< CC tree Id to be used */ -+ uint8_t grp_indx; /**< A Group index in the tree */ -+ uint8_t indx; /**< Entry index in the group defined by grp_index */ -+ ioc_fm_pcd_cc_next_engine_params_t cc_next_engine_params; -+ /**< Parameters for the next for the defined Key in the p_Key */ -+} ioc_fm_pcd_cc_tree_modify_next_engine_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for modifying CC node next engine -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_node_modify_next_engine_params_t { -+ void *id; /**< CC node Id to be used */ -+ uint16_t key_indx; /**< Key index for Next Engine Params modifications; -+ NOTE: This parameter is IGNORED for miss-key! */ -+ uint8_t key_size; /**< Key size of added key */ -+ ioc_fm_pcd_cc_next_engine_params_t cc_next_engine_params; -+ /**< parameters for the next for the defined Key in the p_Key */ -+} ioc_fm_pcd_cc_node_modify_next_engine_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for remove CC node key -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_node_remove_key_params_t { -+ void *id; /**< CC node Id to be used */ -+ uint16_t key_indx; /**< Key index for Next Engine Params modifications; -+ NOTE: This parameter is IGNORED for miss-key! */ -+} ioc_fm_pcd_cc_node_remove_key_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for modifying CC node key and next engine -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t { -+ void *id; /**< CC node Id to be used */ -+ uint16_t key_indx; /**< Key index for Next Engine Params modifications; -+ NOTE: This parameter is IGNORED for miss-key! */ -+ uint8_t key_size; /**< Key size of added key */ -+ ioc_fm_pcd_cc_key_params_t key_params; /**< it's array with numOfKeys entries each entry in -+ the array of the type ioc_fm_pcd_cc_key_params_t */ -+} ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for modifying CC node key -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_cc_node_modify_key_params_t { -+ void *id; /**< CC node Id to be used */ -+ uint16_t key_indx; /**< Key index for Next Engine Params modifications; -+ NOTE: This parameter is IGNORED for miss-key! */ -+ uint8_t key_size; /**< Key size of added key */ -+ uint8_t *p_key; /**< Pointer to the key of the size defined in key_size */ -+ uint8_t *p_mask; /**< Pointer to the Mask per key of the size defined -+ in keySize. p_Key and p_Mask (if defined) have to be -+ of the same size as defined in the key_size */ -+} ioc_fm_pcd_cc_node_modify_key_params_t; -+ -+/**************************************************************************//** -+ @Description A structure with the arguments for the FM_PCD_HashTableRemoveKey ioctl() call -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_hash_table_remove_key_params_t { -+ void *p_hash_tbl; /**< The id of the hash table */ -+ uint8_t key_size; /**< The size of the key to remove */ -+ uint8_t *p_key; /**< Pointer to the key to remove */ -+} ioc_fm_pcd_hash_table_remove_key_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for selecting a location for requested manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_manip_hdr_info_t { -+ ioc_net_header_type hdr; /**< Header selection */ -+ ioc_fm_pcd_hdr_index hdr_index; /**< Relevant only for MPLS, VLAN and tunneled IP. Otherwise should be cleared. */ -+ bool by_field; /**< TRUE if the location of manipulation is according to some field in the specific header*/ -+ ioc_fm_pcd_fields_u full_field; /**< Relevant only when by_field = TRUE: Extract field */ -+} ioc_fm_manip_hdr_info_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header removal by header type -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_rmv_by_hdr_params_t { -+ ioc_fm_pcd_manip_hdr_rmv_by_hdr_type type; /**< Selection of header removal location */ -+ union { -+#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) -+ struct { -+ bool include;/**< If FALSE, remove until the specified header (not including the header); -+ If TRUE, remove also the specified header. */ -+ ioc_fm_manip_hdr_info_t hdr_info; -+ } from_start_by_hdr; /**< Relevant when type = e_IOC_FM_PCD_MANIP_RMV_BY_HDR_FROM_START */ -+#endif /* FM_CAPWAP_SUPPORT */ -+#if (DPAA_VERSION >= 11) -+ ioc_fm_manip_hdr_info_t hdr_info; /**< Relevant when type = e_FM_PCD_MANIP_RMV_BY_HDR_FROM_START */ -+#endif /* (DPAA_VERSION >= 11) */ -+ ioc_fm_pcd_manip_hdr_rmv_specific_l2 specific_l2;/**< Relevant when type = e_IOC_FM_PCD_MANIP_BY_HDR_SPECIFIC_L2; -+ Defines which L2 headers to remove. */ -+ } u; -+} ioc_fm_pcd_manip_hdr_rmv_by_hdr_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for configuring IP fragmentation manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_frag_ip_params_t { -+ uint16_t size_for_fragmentation; /**< If length of the frame is greater than this value, -+ IP fragmentation will be executed.*/ -+#if DPAA_VERSION == 10 -+ uint8_t scratch_bpid; /**< Absolute buffer pool id according to BM configuration.*/ -+#endif /* DPAA_VERSION == 10 */ -+ bool sg_bpid_en; /**< Enable a dedicated buffer pool id for the Scatter/Gather buffer allocation; -+ If disabled, the Scatter/Gather buffer will be allocated from the same pool as the -+ received frame's buffer. */ -+ uint8_t sg_bpid; /**< Scatter/Gather buffer pool id; -+ This parameter is relevant when 'sg_bpid_en=TRUE'; -+ Same LIODN number is used for these buffers as for the received frames buffers, so buffers -+ of this pool need to be allocated in the same memory area as the received buffers. -+ If the received buffers arrive from different sources, the Scatter/Gather BP id should be -+ mutual to all these sources. */ -+ ioc_fm_pcd_manip_dont_frag_action dont_frag_action; /**< Dont Fragment Action - If an IP packet is larger -+ than MTU and its DF bit is set, then this field will -+ determine the action to be taken.*/ -+} ioc_fm_pcd_manip_frag_ip_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for configuring IP reassembly manipulation. -+ -+ This is a common structure for both IPv4 and IPv6 reassembly -+ manipulation. For reassembly of both IPv4 and IPv6, make sure to -+ set the 'hdr' field in ioc_fm_pcd_manip_reassem_params_t to IOC_HEADER_TYPE_IPv6. -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_reassem_ip_params_t { -+ uint8_t relative_scheme_id[2]; /**< Partition relative scheme id: -+ relativeSchemeId[0] - Relative scheme ID for IPV4 Reassembly manipulation; -+ relativeSchemeId[1] - Relative scheme ID for IPV6 Reassembly manipulation; -+ NOTE: The following comment is relevant only for FMAN v2 devices: -+ Relative scheme ID for IPv4/IPv6 Reassembly manipulation must be smaller than -+ the user schemes id to ensure that the reassembly's schemes will be first match. -+ The remaining schemes, if defined, should have higher relative scheme ID. */ -+#if DPAA_VERSION >= 11 -+ uint32_t non_consistent_sp_fqid; /**< In case that other fragments of the frame corresponds to different storage -+ profile than the opening fragment (Non-Consistent-SP state) -+ then one of two possible scenarios occurs: -+ if 'nonConsistentSpFqid != 0', the reassembled frame will be enqueued to -+ this fqid, otherwise a 'Non Consistent SP' bit will be set in the FD[status].*/ -+#else -+ uint8_t sg_bpid; /**< Buffer pool id for the S/G frame created by the reassembly process */ -+#endif /* DPAA_VERSION >= 11 */ -+ uint8_t data_mem_id; /**< Memory partition ID for the IPR's external tables structure */ -+ uint16_t data_liodn_offset; /**< LIODN offset for access the IPR's external tables structure. */ -+ uint16_t min_frag_size[2]; /**< Minimum fragment size: -+ minFragSize[0] - for ipv4, minFragSize[1] - for ipv6 */ -+ ioc_fm_pcd_manip_reassem_ways_number num_of_frames_per_hash_entry[2]; -+ /**< Number of frames per hash entry needed for reassembly process: -+ numOfFramesPerHashEntry[0] - for ipv4 (max value is e_IOC_FM_PCD_MANIP_EIGHT_WAYS_HASH); -+ numOfFramesPerHashEntry[1] - for ipv6 (max value is e_IOC_FM_PCD_MANIP_SIX_WAYS_HASH). */ -+ uint16_t max_num_frames_in_process;/**< Number of frames which can be processed by Reassembly in the same time; -+ Must be power of 2; -+ In the case numOfFramesPerHashEntry == e_IOC_FM_PCD_MANIP_FOUR_WAYS_HASH, -+ maxNumFramesInProcess has to be in the range of 4 - 512; -+ In the case numOfFramesPerHashEntry == e_IOC_FM_PCD_MANIP_EIGHT_WAYS_HASH, -+ maxNumFramesInProcess has to be in the range of 8 - 2048. */ -+ ioc_fm_pcd_manip_reassem_time_out_mode time_out_mode; /**< Expiration delay initialized by Reassembly process */ -+ uint32_t fqid_for_time_out_frames;/**< FQID in which time out frames will enqueue during Time Out Process */ -+ uint32_t timeout_threshold_for_reassm_process; -+ /**< Represents the time interval in microseconds which defines -+ if opened frame (at least one fragment was processed but not all the fragments)is found as too old*/ -+} ioc_fm_pcd_manip_reassem_ip_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining IPSEC manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_special_offload_ipsec_params_t { -+ bool decryption; /**< TRUE if being used in decryption direction; -+ FALSE if being used in encryption direction. */ -+ bool ecn_copy; /**< TRUE to copy the ECN bits from inner/outer to outer/inner -+ (direction depends on the 'decryption' field). */ -+ bool dscp_copy; /**< TRUE to copy the DSCP bits from inner/outer to outer/inner -+ (direction depends on the 'decryption' field). */ -+ bool variable_ip_hdr_len; /**< TRUE for supporting variable IP header length in decryption. */ -+ bool variable_ip_version; /**< TRUE for supporting both IP version on the same SA in encryption */ -+ uint8_t outer_ip_hdr_len; /**< If 'variable_ip_version == TRUE' than this field must be set to non-zero value; -+ It is specifies the length of the outer IP header that was configured in the -+ corresponding SA. */ -+ uint16_t arw_size; /**< if <> '0' then will perform ARW check for this SA; -+ The value must be a multiplication of 16 */ -+ void *arw_addr; /**< if arwSize <> '0' then this field must be set to non-zero value; -+ MUST be allocated from FMAN's MURAM that the post-sec op-port belong -+ Must be 4B aligned. Required MURAM size is '(NEXT_POWER_OF_2(arwSize+32))/8+4' Bytes */ -+} ioc_fm_pcd_manip_special_offload_ipsec_params_t; -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description Parameters for configuring CAPWAP fragmentation manipulation -+ -+ Restrictions: -+ - Maximum number of fragments per frame is 16. -+ - Transmit confirmation is not supported. -+ - Fragmentation nodes must be set as the last PCD action (i.e. the -+ corresponding CC node key must have next engine set to e_FM_PCD_DONE). -+ - Only BMan buffers shall be used for frames to be fragmented. -+ - NOTE: The following comment is relevant only for FMAN v3 devices: IPF -+ does not support VSP. Therefore, on the same port where we have IPF we -+ cannot support VSP. -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_frag_capwap_params_t { -+ uint16_t size_for_fragmentation; /**< If length of the frame is greater than this value, -+ CAPWAP fragmentation will be executed.*/ -+ bool sg_bpid_en; /**< Enable a dedicated buffer pool id for the Scatter/Gather buffer allocation; -+ If disabled, the Scatter/Gather buffer will be allocated from the same pool as the -+ received frame's buffer. */ -+ uint8_t sg_bpid; /**< Scatter/Gather buffer pool id; -+ This parameters is relevant when 'sgBpidEn=TRUE'; -+ Same LIODN number is used for these buffers as for the received frames buffers, so buffers -+ of this pool need to be allocated in the same memory area as the received buffers. -+ If the received buffers arrive from different sources, the Scatter/Gather BP id should be -+ mutual to all these sources. */ -+ bool compress_mode_en; /**< CAPWAP Header Options Compress Enable mode; -+ When this mode is enabled then only the first fragment include the CAPWAP header options -+ field (if user provides it in the input frame) and all other fragments exclude the CAPWAP -+ options field (CAPWAP header is updated accordingly).*/ -+} ioc_fm_pcd_manip_frag_capwap_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for configuring CAPWAP reassembly manipulation. -+ -+ Restrictions: -+ - Application must define one scheme to catch the reassembled frames. -+ - Maximum number of fragments per frame is 16. -+ -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_reassem_capwap_params_t { -+ uint8_t relative_scheme_id; /**< Partition relative scheme id; -+ NOTE: this id must be smaller than the user schemes id to ensure that the reassembly scheme will be first match; -+ Rest schemes, if defined, should have higher relative scheme ID. */ -+ uint8_t data_mem_id; /**< Memory partition ID for the IPR's external tables structure */ -+ uint16_t data_liodn_offset; /**< LIODN offset for access the IPR's external tables structure. */ -+ uint16_t max_reassembled_frame_length;/**< The maximum CAPWAP reassembled frame length in bytes; -+ If maxReassembledFrameLength == 0, any successful reassembled frame length is -+ considered as a valid length; -+ if maxReassembledFrameLength > 0, a successful reassembled frame which its length -+ exceeds this value is considered as an error frame (FD status[CRE] bit is set). */ -+ ioc_fm_pcd_manip_reassem_ways_number num_of_frames_per_hash_entry; -+ /**< Number of frames per hash entry needed for reassembly process */ -+ uint16_t max_num_frames_in_process; /**< Number of frames which can be processed by reassembly in the same time; -+ Must be power of 2; -+ In the case numOfFramesPerHashEntry == e_FM_PCD_MANIP_FOUR_WAYS_HASH, -+ maxNumFramesInProcess has to be in the range of 4 - 512; -+ In the case numOfFramesPerHashEntry == e_FM_PCD_MANIP_EIGHT_WAYS_HASH, -+ maxNumFramesInProcess has to be in the range of 8 - 2048. */ -+ ioc_fm_pcd_manip_reassem_time_out_mode time_out_mode; /**< Expiration delay initialized by Reassembly process */ -+ uint32_t fqid_for_time_out_frames; /**< FQID in which time out frames will enqueue during Time Out Process; -+ Recommended value for this field is 0; in this way timed-out frames will be discarded */ -+ uint32_t timeout_threshold_for_reassm_process; -+ /**< Represents the time interval in microseconds which defines -+ if opened frame (at least one fragment was processed but not all the fragments)is found as too old*/ -+} ioc_fm_pcd_manip_reassem_capwap_params_t; -+ -+/**************************************************************************//** -+ @Description structure for defining CAPWAP manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_special_offload_capwap_params_t { -+ bool dtls; /**< TRUE if continue to SEC DTLS encryption */ -+ ioc_fm_pcd_manip_hdr_qos_src qos_src; /**< TODO */ -+} ioc_fm_pcd_manip_special_offload_capwap_params_t; -+ -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Description Parameters for defining special offload manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_special_offload_params_t { -+ ioc_fm_pcd_manip_special_offload_type type; /**< Type of special offload manipulation */ -+ union -+ { -+ ioc_fm_pcd_manip_special_offload_ipsec_params_t ipsec; /**< Parameters for IPSec; Relevant when -+ type = e_IOC_FM_PCD_MANIP_SPECIAL_OFFLOAD_IPSEC */ -+ -+#if (DPAA_VERSION >= 11) -+ ioc_fm_pcd_manip_special_offload_capwap_params_t capwap; /**< Parameters for CAPWAP; Relevant when -+ type = e_FM_PCD_MANIP_SPECIAL_OFFLOAD_CAPWAP */ -+#endif /* (DPAA_VERSION >= 11) */ -+ } u; -+} ioc_fm_pcd_manip_special_offload_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining generic removal manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_rmv_generic_params_t { -+ uint8_t offset; /**< Offset from beginning of header to the start -+ location of the removal */ -+ uint8_t size; /**< Size of removed section */ -+} ioc_fm_pcd_manip_hdr_rmv_generic_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining insertion manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_insrt_t { -+ uint8_t size; /**< size of inserted section */ -+ uint8_t *p_data; /**< data to be inserted */ -+} ioc_fm_pcd_manip_hdr_insrt_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining generic insertion manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_insrt_generic_params_t { -+ uint8_t offset; /**< Offset from beginning of header to the start -+ location of the insertion */ -+ uint8_t size; /**< Size of inserted section */ -+ bool replace; /**< TRUE to override (replace) existing data at -+ 'offset', FALSE to insert */ -+ uint8_t *p_data; /**< Pointer to data to be inserted */ -+} ioc_fm_pcd_manip_hdr_insrt_generic_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation VLAN DSCP To Vpri translation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_field_update_vlan_dscp_to_vpri_t { -+ uint8_t dscp_to_vpri_table[IOC_FM_PCD_MANIP_DSCP_TO_VLAN_TRANS]; -+ /**< A table of VPri values for each DSCP value; -+ The index is the D_SCP value (0-0x3F) and the -+ value is the corresponding VPRI (0-15). */ -+ uint8_t vpri_def_val; /**< 0-7, Relevant only if if update_type = -+ e_IOC_FM_PCD_MANIP_HDR_FIELD_UPDATE_DSCP_TO_VLAN, -+ this field is the Q Tag default value if the -+ IP header is not found. */ -+} ioc_fm_pcd_manip_hdr_field_update_vlan_dscp_to_vpri_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation VLAN fields updates -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_field_update_vlan_t { -+ ioc_fm_pcd_manip_hdr_field_update_vlan update_type; /**< Selects VLAN update type */ -+ union { -+ uint8_t vpri; /**< 0-7, Relevant only if If update_type = -+ e_IOC_FM_PCD_MANIP_HDR_FIELD_UPDATE_VLAN_PRI, this -+ is the new VLAN pri. */ -+ ioc_fm_pcd_manip_hdr_field_update_vlan_dscp_to_vpri_t dscp_to_vpri; -+ /**< Parameters structure, Relevant only if update_type = -+ e_IOC_FM_PCD_MANIP_HDR_FIELD_UPDATE_DSCP_TO_VLAN. */ -+ } u; -+} ioc_fm_pcd_manip_hdr_field_update_vlan_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation IPV4 fields updates -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_field_update_ipv4_t { -+ ioc_ipv4_hdr_manip_update_flags_t valid_updates; /**< ORed flag, selecting the required updates */ -+ uint8_t tos; /**< 8 bit New TOS; Relevant if valid_updates contains -+ IOC_HDR_MANIP_IPV4_TOS */ -+ uint16_t id; /**< 16 bit New IP ID; Relevant only if valid_updates -+ contains IOC_HDR_MANIP_IPV4_ID */ -+ uint32_t src; /**< 32 bit New IP SRC; Relevant only if valid_updates -+ contains IOC_HDR_MANIP_IPV4_SRC */ -+ uint32_t dst; /**< 32 bit New IP DST; Relevant only if valid_updates -+ contains IOC_HDR_MANIP_IPV4_DST */ -+} ioc_fm_pcd_manip_hdr_field_update_ipv4_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation IPV6 fields updates -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_field_update_ipv6_t { -+ ioc_ipv6_hdr_manip_update_flags_t valid_updates; /**< ORed flag, selecting the required updates */ -+ uint8_t traffic_class; /**< 8 bit New Traffic Class; Relevant if valid_updates contains -+ IOC_HDR_MANIP_IPV6_TC */ -+ uint8_t src[IOC_NET_HEADER_FIELD_IPv6_ADDR_SIZE]; -+ /**< 16 byte new IP SRC; Relevant only if valid_updates -+ contains IOC_HDR_MANIP_IPV6_SRC */ -+ uint8_t dst[IOC_NET_HEADER_FIELD_IPv6_ADDR_SIZE]; -+ /**< 16 byte new IP DST; Relevant only if valid_updates -+ contains IOC_HDR_MANIP_IPV6_DST */ -+} ioc_fm_pcd_manip_hdr_field_update_ipv6_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation TCP/UDP fields updates -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_field_update_tcp_udp_t { -+ ioc_tcp_udp_hdr_manip_update_flags_t valid_updates; /**< ORed flag, selecting the required updates */ -+ uint16_t src; /**< 16 bit New TCP/UDP SRC; Relevant only if valid_updates -+ contains IOC_HDR_MANIP_TCP_UDP_SRC */ -+ uint16_t dst; /**< 16 bit New TCP/UDP DST; Relevant only if valid_updates -+ contains IOC_HDR_MANIP_TCP_UDP_DST */ -+} ioc_fm_pcd_manip_hdr_field_update_tcp_udp_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation fields updates -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_field_update_params_t { -+ ioc_fm_pcd_manip_hdr_field_update_type type; /**< Type of header field update manipulation */ -+ union { -+ ioc_fm_pcd_manip_hdr_field_update_vlan_t vlan; /**< Parameters for VLAN update. Relevant when -+ type = e_IOC_FM_PCD_MANIP_HDR_FIELD_UPDATE_VLAN */ -+ ioc_fm_pcd_manip_hdr_field_update_ipv4_t ipv4; /**< Parameters for IPv4 update. Relevant when -+ type = e_IOC_FM_PCD_MANIP_HDR_FIELD_UPDATE_IPV4 */ -+ ioc_fm_pcd_manip_hdr_field_update_ipv6_t ipv6; /**< Parameters for IPv6 update. Relevant when -+ type = e_IOC_FM_PCD_MANIP_HDR_FIELD_UPDATE_IPV6 */ -+ ioc_fm_pcd_manip_hdr_field_update_tcp_udp_t tcp_udp;/**< Parameters for TCP/UDP update. Relevant when -+ type = e_IOC_FM_PCD_MANIP_HDR_FIELD_UPDATE_TCP_UDP */ -+ } u; -+} ioc_fm_pcd_manip_hdr_field_update_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining custom header manipulation for IP replacement -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_custom_ip_hdr_replace_t { -+ ioc_fm_pcd_manip_hdr_custom_ip_replace replace_type; /**< Selects replace update type */ -+ bool dec_ttl_hl; /**< Decrement TTL (IPV4) or Hop limit (IPV6) by 1 */ -+ bool update_ipv4_id; /**< Relevant when replace_type = -+ e_IOC_FM_PCD_MANIP_HDR_CUSTOM_REPLACE_IPV6_BY_IPV4 */ -+ uint16_t id; /**< 16 bit New IP ID; Relevant only if -+ update_ipv4_id = TRUE */ -+ uint8_t hdr_size; /**< The size of the new IP header */ -+ uint8_t hdr[IOC_FM_PCD_MANIP_MAX_HDR_SIZE]; -+ /**< The new IP header */ -+} ioc_fm_pcd_manip_hdr_custom_ip_hdr_replace_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining custom header manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_custom_params_t { -+ ioc_fm_pcd_manip_hdr_custom_type type; /**< Type of header field update manipulation */ -+ union { -+ ioc_fm_pcd_manip_hdr_custom_ip_hdr_replace_t ip_hdr_replace; -+ /**< Parameters IP header replacement */ -+ } u; -+} ioc_fm_pcd_manip_hdr_custom_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining specific L2 insertion manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_insrt_specific_l2_params_t { -+ ioc_fm_pcd_manip_hdr_insrt_specific_l2 specific_l2; /**< Selects which L2 headers to insert */ -+ bool update; /**< TRUE to update MPLS header */ -+ uint8_t size; /**< size of inserted section */ -+ uint8_t *p_data; /**< data to be inserted */ -+} ioc_fm_pcd_manip_hdr_insrt_specific_l2_params_t; -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description Parameters for defining IP insertion manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_insrt_ip_params_t { -+ bool calc_l4_checksum; /**< Calculate L4 checksum. */ -+ ioc_fm_pcd_manip_hdr_qos_mapping_mode mapping_mode; /**< TODO */ -+ uint8_t last_pid_offset; /**< the offset of the last Protocol within -+ the inserted header */ -+ uint16_t id; /**< 16 bit New IP ID */ -+ bool dont_frag_overwrite; -+ /**< IPv4 only. DF is overwritten with the hash-result next-to-last byte. -+ * This byte is configured to be overwritten when RPD is set. */ -+ uint8_t last_dst_offset; -+ /**< IPv6 only. if routing extension exist, user should set the offset of the destination address -+ * in order to calculate UDP checksum pseudo header; -+ * Otherwise set it to '0'. */ -+ ioc_fm_pcd_manip_hdr_insrt_t insrt; /**< size and data to be inserted. */ -+} ioc_fm_pcd_manip_hdr_insrt_ip_params_t; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Description Parameters for defining header insertion manipulation by header type -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_insrt_by_hdr_params_t { -+ ioc_fm_pcd_manip_hdr_insrt_by_hdr_type type; /**< Selects manipulation type */ -+ union { -+ ioc_fm_pcd_manip_hdr_insrt_specific_l2_params_t specific_l2_params; -+ /**< Used when type = e_IOC_FM_PCD_MANIP_INSRT_BY_HDR_SPECIFIC_L2: -+ Selects which L2 headers to remove */ -+#if (DPAA_VERSION >= 11) -+ ioc_fm_pcd_manip_hdr_insrt_ip_params_t ip_params; /**< Used when type = e_FM_PCD_MANIP_INSRT_BY_HDR_IP */ -+ ioc_fm_pcd_manip_hdr_insrt_t insrt; /**< Used when type is one of e_FM_PCD_MANIP_INSRT_BY_HDR_UDP, -+ e_FM_PCD_MANIP_INSRT_BY_HDR_UDP_LITE, or -+ e_FM_PCD_MANIP_INSRT_BY_HDR_CAPWAP */ -+#endif /* (DPAA_VERSION >= 11) */ -+ } u; -+} ioc_fm_pcd_manip_hdr_insrt_by_hdr_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header insertion manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_insrt_params_t { -+ ioc_fm_pcd_manip_hdr_insrt_type type; /**< Type of insertion manipulation */ -+ union { -+ ioc_fm_pcd_manip_hdr_insrt_by_hdr_params_t by_hdr; /**< Parameters for defining header insertion manipulation by header type, -+ relevant if 'type' = e_IOC_FM_PCD_MANIP_INSRT_BY_HDR */ -+ ioc_fm_pcd_manip_hdr_insrt_generic_params_t generic;/**< Parameters for defining generic header insertion manipulation, -+ relevant if type = e_IOC_FM_PCD_MANIP_INSRT_GENERIC */ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ ioc_fm_pcd_manip_hdr_insrt_by_template_params_t by_template; -+ /**< Parameters for defining header insertion manipulation by template, -+ relevant if 'type' = e_IOC_FM_PCD_MANIP_INSRT_BY_TEMPLATE */ -+#endif /* FM_CAPWAP_SUPPORT */ -+ } u; -+} ioc_fm_pcd_manip_hdr_insrt_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header removal manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_rmv_params_t { -+ ioc_fm_pcd_manip_hdr_rmv_type type; /**< Type of header removal manipulation */ -+ union { -+ ioc_fm_pcd_manip_hdr_rmv_by_hdr_params_t by_hdr; /**< Parameters for defining header removal manipulation by header type, -+ relevant if type = e_IOC_FM_PCD_MANIP_RMV_BY_HDR */ -+ ioc_fm_pcd_manip_hdr_rmv_generic_params_t generic; /**< Parameters for defining generic header removal manipulation, -+ relevant if type = e_IOC_FM_PCD_MANIP_RMV_GENERIC */ -+ } u; -+} ioc_fm_pcd_manip_hdr_rmv_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining header manipulation node -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_hdr_params_t { -+ bool rmv; /**< TRUE, to define removal manipulation */ -+ ioc_fm_pcd_manip_hdr_rmv_params_t rmv_params; /**< Parameters for removal manipulation, relevant if 'rmv' = TRUE */ -+ -+ bool insrt; /**< TRUE, to define insertion manipulation */ -+ ioc_fm_pcd_manip_hdr_insrt_params_t insrt_params; /**< Parameters for insertion manipulation, relevant if 'insrt' = TRUE */ -+ -+ bool field_update; /**< TRUE, to define field update manipulation */ -+ ioc_fm_pcd_manip_hdr_field_update_params_t field_update_params; /**< Parameters for field update manipulation, relevant if 'fieldUpdate' = TRUE */ -+ -+ bool custom; /**< TRUE, to define custom manipulation */ -+ ioc_fm_pcd_manip_hdr_custom_params_t custom_params; /**< Parameters for custom manipulation, relevant if 'custom' = TRUE */ -+ -+ bool dont_parse_after_manip;/**< FALSE to activate the parser a second time after -+ completing the manipulation on the frame */ -+} ioc_fm_pcd_manip_hdr_params_t; -+ -+ -+/**************************************************************************//** -+ @Description structure for defining fragmentation manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_frag_params_t { -+ ioc_net_header_type hdr; /**< Header selection */ -+ union { -+#if (DPAA_VERSION >= 11) -+ ioc_fm_pcd_manip_frag_capwap_params_t capwap_frag; /**< Parameters for defining CAPWAP fragmentation, -+ relevant if 'hdr' = HEADER_TYPE_CAPWAP */ -+#endif /* (DPAA_VERSION >= 11) */ -+ ioc_fm_pcd_manip_frag_ip_params_t ip_frag; /**< Parameters for defining IP fragmentation, -+ relevant if 'hdr' = HEADER_TYPE_Ipv4 or HEADER_TYPE_Ipv6 */ -+ } u; -+} ioc_fm_pcd_manip_frag_params_t; -+ -+/**************************************************************************//** -+ @Description structure for defining reassemble manipulation -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_reassem_params_t { -+ ioc_net_header_type hdr; /**< Header selection */ -+ union { -+#if (DPAA_VERSION >= 11) -+ ioc_fm_pcd_manip_reassem_capwap_params_t capwap_reassem; /**< Parameters for defining CAPWAP reassembly, -+ relevant if 'hdr' = HEADER_TYPE_CAPWAP */ -+#endif /* (DPAA_VERSION >= 11) */ -+ ioc_fm_pcd_manip_reassem_ip_params_t ip_reassem; /**< Parameters for defining IP reassembly, -+ relevant if 'hdr' = HEADER_TYPE_Ipv4 or HEADER_TYPE_Ipv6 */ -+ } u; -+} ioc_fm_pcd_manip_reassem_params_t; -+ -+/**************************************************************************//** -+ @Description Parameters for defining a manipulation node -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_params_t { -+ ioc_fm_pcd_manip_type type; /**< Selects type of manipulation node */ -+ union { -+ ioc_fm_pcd_manip_hdr_params_t hdr; /**< Parameters for defining header manipulation node */ -+ ioc_fm_pcd_manip_reassem_params_t reassem;/**< Parameters for defining reassembly manipulation node */ -+ ioc_fm_pcd_manip_frag_params_t frag; /**< Parameters for defining fragmentation manipulation node */ -+ ioc_fm_pcd_manip_special_offload_params_t special_offload;/**< Parameters for defining special offload manipulation node */ -+ } u; -+ void *p_next_manip;/**< Handle to another (previously defined) manipulation node; -+ Allows concatenation of manipulation actions -+ This parameter is optional and may be NULL. */ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ bool frag_or_reasm;/**< TRUE, if defined fragmentation/reassembly manipulation */ -+ ioc_fm_pcd_manip_frag_or_reasm_params_t frag_or_reasm_params;/**< Parameters for fragmentation/reassembly manipulation, -+ relevant if frag_or_reasm = TRUE */ -+#endif /* FM_CAPWAP_SUPPORT */ -+ void *id; -+} ioc_fm_pcd_manip_params_t; -+ -+/**************************************************************************//** -+ @Description Structure for retrieving IP reassembly statistics -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_reassem_ip_stats_t { -+ /* common counters for both IPv4 and IPv6 */ -+ uint32_t timeout; /**< Counts the number of TimeOut occurrences */ -+ uint32_t rfd_pool_busy; /**< Counts the number of failed attempts to allocate -+ a Reassembly Frame Descriptor */ -+ uint32_t internal_buffer_busy; /**< Counts the number of times an internal buffer busy occurred */ -+ uint32_t external_buffer_busy; /**< Counts the number of times external buffer busy occurred */ -+ uint32_t sg_fragments; /**< Counts the number of Scatter/Gather fragments */ -+ uint32_t dma_semaphore_depletion; /**< Counts the number of failed attempts to allocate a DMA semaphore */ -+#if (DPAA_VERSION >= 11) -+ uint32_t non_consistent_sp; /**< Counts the number of Non Consistent Storage Profile events for -+ successfully reassembled frames */ -+#endif /* (DPAA_VERSION >= 11) */ -+struct { -+ uint32_t successfully_reassembled; /**< Counts the number of successfully reassembled frames */ -+ uint32_t valid_fragments; /**< Counts the total number of valid fragments that -+ have been processed for all frames */ -+ uint32_t processed_fragments; /**< Counts the number of processed fragments -+ (valid and error fragments) for all frames */ -+ uint32_t malformed_fragments; /**< Counts the number of malformed fragments processed for all frames */ -+ uint32_t discarded_fragments; /**< Counts the number of fragments discarded by the reassembly process */ -+ uint32_t auto_learn_busy; /**< Counts the number of times a busy condition occurs when attempting -+ to access an IP-Reassembly Automatic Learning Hash set */ -+ uint32_t more_than16fragments; /**< Counts the fragment occurrences in which the number of fragments-per-frame -+ exceeds 16 */ -+ } specific_hdr_statistics[2]; /**< slot '0' is for IPv4, slot '1' is for IPv6 */ -+} ioc_fm_pcd_manip_reassem_ip_stats_t; -+ -+/**************************************************************************//** -+ @Description Structure for retrieving IP fragmentation statistics -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_frag_ip_stats_t { -+ uint32_t total_frames; /**< Number of frames that passed through the manipulation node */ -+ uint32_t fragmented_frames; /**< Number of frames that were fragmented */ -+ uint32_t generated_fragments; /**< Number of fragments that were generated */ -+} ioc_fm_pcd_manip_frag_ip_stats_t; -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Description Structure for retrieving CAPWAP reassembly statistics -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_reassem_capwap_stats_t { -+ uint32_t timeout; /**< Counts the number of timeout occurrences */ -+ uint32_t rfd_pool_busy; /**< Counts the number of failed attempts to allocate -+ a Reassembly Frame Descriptor */ -+ uint32_t internal_buffer_busy; /**< Counts the number of times an internal buffer busy occurred */ -+ uint32_t external_buffer_busy; /**< Counts the number of times external buffer busy occurred */ -+ uint32_t sg_fragments; /**< Counts the number of Scatter/Gather fragments */ -+ uint32_t dma_semaphore_depletion; /**< Counts the number of failed attempts to allocate a DMA semaphore */ -+ uint32_t successfully_reassembled; /**< Counts the number of successfully reassembled frames */ -+ uint32_t valid_fragments; /**< Counts the total number of valid fragments that -+ have been processed for all frames */ -+ uint32_t processed_fragments; /**< Counts the number of processed fragments -+ (valid and error fragments) for all frames */ -+ uint32_t malformed_fragments; /**< Counts the number of malformed fragments processed for all frames */ -+ uint32_t autoLearn_busy; /**< Counts the number of times a busy condition occurs when attempting -+ to access an Reassembly Automatic Learning Hash set */ -+ uint32_t discarded_fragments; /**< Counts the number of fragments discarded by the reassembly process */ -+ uint32_t more_than16fragments; /**< Counts the fragment occurrences in which the number of fragments-per-frame -+ exceeds 16 */ -+ uint32_t exceed_max_reassembly_frame_len;/**< ounts the number of times that a successful reassembled frame -+ length exceeds MaxReassembledFrameLength value */ -+} ioc_fm_pcd_manip_reassem_capwap_stats_t; -+ -+/**************************************************************************//** -+ @Description Structure for retrieving CAPWAP fragmentation statistics -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_frag_capwap_stats_t { -+ uint32_t total_frames; /**< Number of frames that passed through the manipulation node */ -+ uint32_t fragmented_frames; /**< Number of frames that were fragmented */ -+ uint32_t generated_fragments; /**< Number of fragments that were generated */ -+#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) -+ uint8_t sg_allocation_failure; /**< Number of allocation failure of s/g buffers */ -+#endif /* (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) */ -+} ioc_fm_pcd_manip_frag_capwap_stats_t; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Description Structure for retrieving reassembly statistics -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_reassem_stats_t { -+ union { -+ ioc_fm_pcd_manip_reassem_ip_stats_t ip_reassem; /**< Structure for IP reassembly statistics */ -+#if (DPAA_VERSION >= 11) -+ ioc_fm_pcd_manip_reassem_capwap_stats_t capwap_reassem; /**< Structure for CAPWAP reassembly statistics */ -+#endif /* (DPAA_VERSION >= 11) */ -+ } u; -+} ioc_fm_pcd_manip_reassem_stats_t; -+ -+/**************************************************************************//** -+ @Description structure for retrieving fragmentation statistics -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_frag_stats_t { -+ union { -+ ioc_fm_pcd_manip_frag_ip_stats_t ip_frag; /**< Structure for IP fragmentation statistics */ -+#if (DPAA_VERSION >= 11) -+ ioc_fm_pcd_manip_frag_capwap_stats_t capwap_frag; /**< Structure for CAPWAP fragmentation statistics */ -+#endif /* (DPAA_VERSION >= 11) */ -+ } u; -+} ioc_fm_pcd_manip_frag_stats_t; -+ -+/**************************************************************************//** -+ @Description structure for defining manipulation statistics -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_stats_t { -+ union { -+ ioc_fm_pcd_manip_reassem_stats_t reassem; /**< Structure for reassembly statistics */ -+ ioc_fm_pcd_manip_frag_stats_t frag; /**< Structure for fragmentation statistics */ -+ } u; -+} ioc_fm_pcd_manip_stats_t; -+ -+/**************************************************************************//** -+ @Description Parameters for acquiring manipulation statistics -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_manip_get_stats_t { -+ void *id; -+ ioc_fm_pcd_manip_stats_t stats; -+} ioc_fm_pcd_manip_get_stats_t; -+ -+#if DPAA_VERSION >= 11 -+/**************************************************************************//** -+ @Description Parameters for defining frame replicator group and its members -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_frm_replic_group_params_t { -+ uint8_t max_num_of_entries; /**< Maximal number of members in the group - must be at least two */ -+ uint8_t num_of_entries; /**< Number of members in the group - must be at least 1 */ -+ ioc_fm_pcd_cc_next_engine_params_t next_engine_params[IOC_FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES]; -+ /**< Array of members' parameters */ -+ void *id; -+} ioc_fm_pcd_frm_replic_group_params_t; -+ -+typedef struct ioc_fm_pcd_frm_replic_member_t { -+ void *h_replic_group; -+ uint16_t member_index; -+} ioc_fm_pcd_frm_replic_member_t; -+ -+typedef struct ioc_fm_pcd_frm_replic_member_params_t { -+ ioc_fm_pcd_frm_replic_member_t member; -+ ioc_fm_pcd_cc_next_engine_params_t next_engine_params; -+} ioc_fm_pcd_frm_replic_member_params_t; -+#endif /* DPAA_VERSION >= 11 */ -+ -+ -+typedef struct ioc_fm_pcd_cc_key_statistics_t { -+ uint32_t byte_count; /**< This counter reflects byte count of frames that -+ were matched by this key. */ -+ uint32_t frame_count; /**< This counter reflects count of frames that -+ were matched by this key. */ -+#if (DPAA_VERSION >= 11) -+ uint32_t frame_length_range_count[IOC_FM_PCD_CC_STATS_MAX_NUM_OF_FLR]; -+ /**< These counters reflect how many frames matched -+ this key in 'RMON' statistics mode: -+ Each counter holds the number of frames of a -+ specific frames length range, according to the -+ ranges provided at initialization. */ -+#endif /* (DPAA_VERSION >= 11) */ -+} ioc_fm_pcd_cc_key_statistics_t; -+ -+ -+typedef struct ioc_fm_pcd_cc_tbl_get_stats_t { -+ void *id; -+ uint16_t key_index; -+ ioc_fm_pcd_cc_key_statistics_t statistics; -+} ioc_fm_pcd_cc_tbl_get_stats_t; -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableGetKeyStatistics -+ -+ @Description This routine may be used to get statistics counters of specific key -+ in a CC Node. -+ -+ If 'e_FM_PCD_CC_STATS_MODE_FRAME' and -+ 'e_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME' were set for this node, -+ these counters reflect how many frames passed that were matched -+ this key; The total frames count will be returned in the counter -+ of the first range (as only one frame length range was defined). -+ If 'e_FM_PCD_CC_STATS_MODE_RMON' was set for this node, the total -+ frame count will be separated to frame length counters, based on -+ provided frame length ranges. -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[in] keyIndex Key index for adding -+ @Param[out] p_KeyStatistics Key statistics counters -+ -+ @Return The specific key statistics. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet(). -+*//***************************************************************************/ -+ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MATCH_TABLE_GET_KEY_STAT_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(12), ioc_compat_fm_pcd_cc_tbl_get_stats_t) -+#endif -+#define FM_PCD_IOC_MATCH_TABLE_GET_KEY_STAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(12), ioc_fm_pcd_cc_tbl_get_stats_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableGetMissStatistics -+ -+ @Description This routine may be used to get statistics counters of miss entry -+ in a CC Node. -+ -+ If 'e_FM_PCD_CC_STATS_MODE_FRAME' and -+ 'e_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME' were set for this node, -+ these counters reflect how many frames were not matched to any -+ existing key and therefore passed through the miss entry; The -+ total frames count will be returned in the counter of the -+ first range (as only one frame length range was defined). -+ -+ @Param[in] h_CcNode A handle to the node -+ @Param[out] p_MissStatistics Statistics counters for 'miss' -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet(). -+*//***************************************************************************/ -+ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MATCH_TABLE_GET_MISS_STAT_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(13), ioc_compat_fm_pcd_cc_tbl_get_stats_t) -+#endif -+#define FM_PCD_IOC_MATCH_TABLE_GET_MISS_STAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(13), ioc_fm_pcd_cc_tbl_get_stats_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_HashTableGetMissStatistics -+ -+ @Description This routine may be used to get statistics counters of 'miss' -+ entry of the a hash table. -+ -+ If 'e_FM_PCD_CC_STATS_MODE_FRAME' and -+ 'e_FM_PCD_CC_STATS_MODE_BYTE_AND_FRAME' were set for this node, -+ these counters reflect how many frames were not matched to any -+ existing key and therefore passed through the miss entry; -+ -+ @Param[in] h_HashTbl A handle to a hash table -+ @Param[out] p_MissStatistics Statistics counters for 'miss' -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_HashTableSet(). -+*//***************************************************************************/ -+ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_HASH_TABLE_GET_MISS_STAT_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(14), ioc_compat_fm_pcd_cc_tbl_get_stats_t) -+#endif -+#define FM_PCD_IOC_HASH_TABLE_GET_MISS_STAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(14), ioc_fm_pcd_cc_tbl_get_stats_t) -+ -+ -+/**************************************************************************//** -+ @Function FM_PCD_NetEnvCharacteristicsSet -+ -+ @Description Define a set of Network Environment Characteristics. -+ -+ When setting an environment it is important to understand its -+ application. It is not meant to describe the flows that will run -+ on the ports using this environment, but what the user means TO DO -+ with the PCD mechanisms in order to parse-classify-distribute those -+ frames. -+ By specifying a distinction unit, the user means it would use that option -+ for distinction between frames at either a KeyGen scheme or a coarse -+ classification action descriptor. Using interchangeable headers to define a -+ unit means that the user is indifferent to which of the interchangeable -+ headers is present in the frame, and wants the distinction to be based -+ on the presence of either one of them. -+ -+ Depending on context, there are limitations to the use of environments. A -+ port using the PCD functionality is bound to an environment. Some or even -+ all ports may share an environment but also an environment per port is -+ possible. When initializing a scheme, a classification plan group (see below), -+ or a coarse classification tree, one of the initialized environments must be -+ stated and related to. When a port is bound to a scheme, a classification -+ plan group, or a coarse classification tree, it MUST be bound to the same -+ environment. -+ -+ The different PCD modules, may relate (for flows definition) ONLY on -+ distinction units as defined by their environment. When initializing a -+ scheme for example, it may not choose to select IPV4 as a match for -+ recognizing flows unless it was defined in the relating environment. In -+ fact, to guide the user through the configuration of the PCD, each module's -+ characterization in terms of flows is not done using protocol names, but using -+ environment indexes. -+ -+ In terms of HW implementation, the list of distinction units sets the LCV vectors -+ and later used for match vector, classification plan vectors and coarse classification -+ indexing. -+ -+ @Param[in,out] ioc_fm_pcd_net_env_params_t A structure defining the distiction units for this configuration. -+ -+ @Return 0 on success; Error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_NET_ENV_CHARACTERISTICS_SET_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(20), ioc_compat_fm_pcd_net_env_params_t) -+#endif -+#define FM_PCD_IOC_NET_ENV_CHARACTERISTICS_SET _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(20), ioc_fm_pcd_net_env_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_NetEnvCharacteristicsDelete -+ -+ @Description Deletes a set of Network Environment Charecteristics. -+ -+ @Param[in] ioc_fm_obj_t - The id of a Network Environment object. -+ -+ @Return 0 on success; Error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_NET_ENV_CHARACTERISTICS_DELETE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(21), ioc_compat_fm_obj_t) -+#endif -+#define FM_PCD_IOC_NET_ENV_CHARACTERISTICS_DELETE _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(21), ioc_fm_obj_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_KgSchemeSet -+ -+ @Description Initializing or modifying and enabling a scheme for the KeyGen. -+ This routine should be called for adding or modifying a scheme. -+ When a scheme needs modifying, the API requires that it will be -+ rewritten. In such a case 'modify' should be TRUE. If the -+ routine is called for a valid scheme and 'modify' is FALSE, -+ it will return error. -+ -+ @Param[in,out] ioc_fm_pcd_kg_scheme_params_t A structure of parameters for defining the scheme -+ -+ @Return 0 on success; Error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_KG_SCHEME_SET_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(24), ioc_compat_fm_pcd_kg_scheme_params_t) -+#endif -+#define FM_PCD_IOC_KG_SCHEME_SET _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(24), ioc_fm_pcd_kg_scheme_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_KgSchemeDelete -+ -+ @Description Deleting an initialized scheme. -+ -+ @Param[in] ioc_fm_obj_t scheme id as initalized by application at FM_PCD_IOC_KG_SET_SCHEME -+ -+ @Return 0 on success; Error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_KG_SCHEME_DELETE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(25), ioc_compat_fm_obj_t) -+#endif -+#define FM_PCD_IOC_KG_SCHEME_DELETE _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(25), ioc_fm_obj_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_CcRootBuild -+ -+ @Description This routine must be called to define a complete coarse -+ classification tree. This is the way to define coarse -+ classification to a certain flow - the KeyGen schemes -+ may point only to trees defined in this way. -+ -+ @Param[in,out] ioc_fm_pcd_cc_tree_params_t A structure of parameters to define the tree. -+ -+ @Return 0 on success; Error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_CC_ROOT_BUILD_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(26), compat_uptr_t) -+#endif -+#define FM_PCD_IOC_CC_ROOT_BUILD _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(26), void *) /* workaround ...*/ -+ -+/**************************************************************************//** -+ @Function FM_PCD_CcRootDelete -+ -+ @Description Deleting a built tree. -+ -+ @Param[in] ioc_fm_obj_t - The id of a CC tree. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_CC_ROOT_DELETE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(27), ioc_compat_fm_obj_t) -+#endif -+#define FM_PCD_IOC_CC_ROOT_DELETE _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(27), ioc_fm_obj_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableSet -+ -+ @Description This routine should be called for each CC (coarse classification) -+ node. The whole CC tree should be built bottom up so that each -+ node points to already defined nodes. p_NodeId returns the node -+ Id to be used by other nodes. -+ -+ @Param[in,out] ioc_fm_pcd_cc_node_params_t A structure for defining the CC node params -+ -+ @Return 0 on success; Error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MATCH_TABLE_SET_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(28), compat_uptr_t) -+#endif -+#define FM_PCD_IOC_MATCH_TABLE_SET _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(28), void *) /* workaround ...*/ -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableDelete -+ -+ @Description Deleting a built node. -+ -+ @Param[in] ioc_fm_obj_t - The id of a CC node. -+ -+ @Return 0 on success; Error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MATCH_TABLE_DELETE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(29), ioc_compat_fm_obj_t) -+#endif -+#define FM_PCD_IOC_MATCH_TABLE_DELETE _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(29), ioc_fm_obj_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_CcRootModifyNextEngine -+ -+ @Description Modify the Next Engine Parameters in the entry of the tree. -+ -+ @Param[in] ioc_fm_pcd_cc_tree_modify_next_engine_params_t - Pointer to a structure with the relevant parameters -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_CcRootBuild(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_CC_ROOT_MODIFY_NEXT_ENGINE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(30), ioc_compat_fm_pcd_cc_tree_modify_next_engine_params_t) -+#endif -+#define FM_PCD_IOC_CC_ROOT_MODIFY_NEXT_ENGINE _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(30), ioc_fm_pcd_cc_tree_modify_next_engine_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableModifyNextEngine -+ -+ @Description Modify the Next Engine Parameters in the relevant key entry of the node. -+ -+ @Param[in] ioc_fm_pcd_cc_node_modify_next_engine_params_t A pointer to a structure with the relevant parameters -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MATCH_TABLE_MODIFY_NEXT_ENGINE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(31), ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t) -+#endif -+#define FM_PCD_IOC_MATCH_TABLE_MODIFY_NEXT_ENGINE _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(31), ioc_fm_pcd_cc_node_modify_next_engine_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableModifyMissNextEngine -+ -+ @Description Modify the Next Engine Parameters of the Miss key case of the node. -+ -+ @Param[in] ioc_fm_pcd_cc_node_modify_next_engine_params_t - Pointer to a structure with the relevant parameters -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MATCH_TABLE_MODIFY_MISS_NEXT_ENGINE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(32), ioc_compat_fm_pcd_cc_node_modify_next_engine_params_t) -+#endif -+#define FM_PCD_IOC_MATCH_TABLE_MODIFY_MISS_NEXT_ENGINE _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(32), ioc_fm_pcd_cc_node_modify_next_engine_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableRemoveKey -+ -+ @Description Remove the key (including next engine parameters of this key) -+ defined by the index of the relevant node. -+ -+ @Param[in] ioc_fm_pcd_cc_node_remove_key_params_t A pointer to a structure with the relevant parameters -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only after FM_PCD_MatchTableSet() has been called for this -+ node and for all of the nodes that lead to it. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MATCH_TABLE_REMOVE_KEY_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(33), ioc_compat_fm_pcd_cc_node_remove_key_params_t) -+#endif -+#define FM_PCD_IOC_MATCH_TABLE_REMOVE_KEY _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(33), ioc_fm_pcd_cc_node_remove_key_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableAddKey -+ -+ @Description Add the key (including next engine parameters of this key in the -+ index defined by the keyIndex. Note that 'FM_PCD_LAST_KEY_INDEX' -+ may be used when the user doesn't care about the position of the -+ key in the table - in that case, the key will be automatically -+ added by the driver in the last available entry. -+ -+ @Param[in] ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t A pointer to a structure with the relevant parameters -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only after FM_PCD_MatchTableSet() has been called for this -+ node and for all of the nodes that lead to it. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MATCH_TABLE_ADD_KEY_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(34), ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t) -+#endif -+#define FM_PCD_IOC_MATCH_TABLE_ADD_KEY _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(34), ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableModifyKeyAndNextEngine -+ -+ @Description Modify the key and Next Engine Parameters of this key in the index defined by key_index. -+ -+ @Param[in] ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t A pointer to a structure with the relevant parameters -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_MatchTableSet() not only of the relevnt node but also -+ the node that points to this node -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MATCH_TABLE_MODIFY_KEY_AND_NEXT_ENGINE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(35), ioc_compat_fm_pcd_cc_node_modify_key_and_next_engine_params_t) -+#endif -+#define FM_PCD_IOC_MATCH_TABLE_MODIFY_KEY_AND_NEXT_ENGINE _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(35), ioc_fm_pcd_cc_node_modify_key_and_next_engine_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_MatchTableModifyKey -+ -+ @Description Modify the key at the index defined by key_index. -+ -+ @Param[in] ioc_fm_pcd_cc_node_modify_key_params_t - Pointer to a structure with the relevant parameters -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only after FM_PCD_MatchTableSet() has been called for this -+ node and for all of the nodes that lead to it. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MATCH_TABLE_MODIFY_KEY_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(36), ioc_compat_fm_pcd_cc_node_modify_key_params_t) -+#endif -+#define FM_PCD_IOC_MATCH_TABLE_MODIFY_KEY _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(36), ioc_fm_pcd_cc_node_modify_key_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_HashTableSet -+ -+ @Description This routine initializes a hash table structure. -+ KeyGen hash result determines the hash bucket. -+ Next, KeyGen key is compared against all keys of this -+ bucket (exact match). -+ Number of sets (number of buckets) of the hash equals to the -+ number of 1-s in 'hash_res_mask' in the provided parameters. -+ Number of hash table ways is then calculated by dividing -+ 'max_num_of_keys' equally between the hash sets. This is the maximal -+ number of keys that a hash bucket may hold. -+ The hash table is initialized empty and keys may be -+ added to it following the initialization. Keys masks are not -+ supported in current hash table implementation. -+ The initialized hash table can be integrated as a node in a -+ CC tree. -+ -+ @Param[in,out] ioc_fm_pcd_hash_table_params_t - Pointer to a structure with the relevant parameters -+ -+ @Return 0 on success; Error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_HASH_TABLE_SET_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(37), ioc_compat_fm_pcd_hash_table_params_t) -+#endif -+#define FM_PCD_IOC_HASH_TABLE_SET _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(37), ioc_fm_pcd_hash_table_params_t) -+ -+ -+/**************************************************************************//** -+ @Function FM_PCD_HashTableDelete -+ -+ @Description This routine deletes the provided hash table and released all -+ its allocated resources. -+ -+ @Param[in] ioc_fm_obj_t - The ID of a hash table. -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_HashTableSet(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_HASH_TABLE_DELETE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(37), ioc_compat_fm_obj_t) -+#endif -+#define FM_PCD_IOC_HASH_TABLE_DELETE _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(37), ioc_fm_obj_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_HashTableAddKey -+ -+ @Description This routine adds the provided key (including next engine -+ parameters of this key) to the hash table. -+ The key is added as the last key of the bucket that it is -+ mapped to. -+ -+ @Param[in] ioc_fm_pcd_hash_table_add_key_params_t - Pointer to a structure with the relevant parameters -+ -+ @Return 0 on success; error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_HashTableSet(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_HASH_TABLE_ADD_KEY_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(39), ioc_compat_fm_pcd_hash_table_add_key_params_t) -+#endif -+#define FM_PCD_IOC_HASH_TABLE_ADD_KEY _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(39), ioc_fm_pcd_hash_table_add_key_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_HashTableRemoveKey -+ -+ @Description This routine removes the requested key (including next engine -+ parameters of this key) from the hash table. -+ -+ @Param[in] ioc_fm_pcd_hash_table_remove_key_params_t - Pointer to a structure with the relevant parameters -+ -+ @Return 0 on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_HashTableSet(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_HASH_TABLE_REMOVE_KEY_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(40), ioc_compat_fm_pcd_hash_table_remove_key_params_t) -+#endif -+#define FM_PCD_IOC_HASH_TABLE_REMOVE_KEY _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(40), ioc_fm_pcd_hash_table_remove_key_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_PlcrProfileSet -+ -+ @Description Sets a profile entry in the policer profile table. -+ The routine overrides any existing value. -+ -+ @Param[in,out] ioc_fm_pcd_plcr_profile_params_t A structure of parameters for defining a -+ policer profile entry. -+ -+ @Return 0 on success; Error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_PLCR_PROFILE_SET_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(41), ioc_compat_fm_pcd_plcr_profile_params_t) -+#endif -+#define FM_PCD_IOC_PLCR_PROFILE_SET _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(41), ioc_fm_pcd_plcr_profile_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_PlcrProfileDelete -+ -+ @Description Delete a profile entry in the policer profile table. -+ The routine set entry to invalid. -+ -+ @Param[in] ioc_fm_obj_t The id of a policer profile. -+ -+ @Return 0 on success; Error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_PLCR_PROFILE_DELETE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(41), ioc_compat_fm_obj_t) -+#endif -+#define FM_PCD_IOC_PLCR_PROFILE_DELETE _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(41), ioc_fm_obj_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_ManipNodeSet -+ -+ @Description This routine should be called for defining a manipulation -+ node. A manipulation node must be defined before the CC node -+ that precedes it. -+ -+ @Param[in] ioc_fm_pcd_manip_params_t - A structure of parameters defining the manipulation -+ -+ @Return A handle to the initialized object on success; NULL code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MANIP_NODE_SET_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(43), ioc_compat_fm_pcd_manip_params_t) -+#endif -+#define FM_PCD_IOC_MANIP_NODE_SET _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(43), ioc_fm_pcd_manip_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_ManipNodeReplace -+ -+ @Description Change existing manipulation node to be according to new requirement. -+ (Here, it's implemented as a variant of the same IOCTL as for -+ FM_PCD_ManipNodeSet(), and one that when called, the 'id' member -+ in its 'ioc_fm_pcd_manip_params_t' argument is set to contain -+ the manip node's handle) -+ -+ @Param[in] ioc_fm_pcd_manip_params_t - A structure of parameters defining the manipulation -+ -+ @Return 0 on success; error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_ManipNodeSet(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MANIP_NODE_REPLACE_COMPAT FM_PCD_IOC_MANIP_NODE_SET_COMPAT -+#endif -+#define FM_PCD_IOC_MANIP_NODE_REPLACE FM_PCD_IOC_MANIP_NODE_SET -+ -+/**************************************************************************//** -+ @Function FM_PCD_ManipNodeDelete -+ -+ @Description Delete an existing manipulation node. -+ -+ @Param[in] ioc_fm_obj_t The id of the manipulation node to delete. -+ -+ @Return 0 on success; error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_ManipNodeSet(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MANIP_NODE_DELETE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(44), ioc_compat_fm_obj_t) -+#endif -+#define FM_PCD_IOC_MANIP_NODE_DELETE _IOW(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(44), ioc_fm_obj_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_ManipGetStatistics -+ -+ @Description Retrieve the manipulation statistics. -+ -+ @Param[in] h_ManipNode A handle to a manipulation node. -+ @Param[out] p_FmPcdManipStats A structure for retrieving the manipulation statistics -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_ManipNodeSet(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_MANIP_GET_STATS_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(50), ioc_compat_fm_pcd_manip_get_stats_t) -+#endif -+#define FM_PCD_IOC_MANIP_GET_STATS _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(50), ioc_fm_pcd_manip_get_stats_t) -+ -+/**************************************************************************//** -+@Function FM_PCD_SetAdvancedOffloadSupport -+ -+@Description This routine must be called in order to support the following features: -+ IP-fragmentation, IP-reassembly, IPsec, Header-manipulation, frame-replicator. -+ -+@Param[in] h_FmPcd FM PCD module descriptor. -+ -+@Return 0 on success; error code otherwise. -+ -+@Cautions Allowed only when PCD is disabled. -+*//***************************************************************************/ -+#define FM_PCD_IOC_SET_ADVANCED_OFFLOAD_SUPPORT _IO(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(45)) -+ -+#if (DPAA_VERSION >= 11) -+/**************************************************************************//** -+ @Function FM_PCD_FrmReplicSetGroup -+ -+ @Description Initialize a Frame Replicator group. -+ -+ @Param[in] h_FmPcd FM PCD module descriptor. -+ @Param[in] p_FrmReplicGroupParam A structure of parameters for the initialization of -+ the frame replicator group. -+ -+ @Return A handle to the initialized object on success; NULL code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_Init(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_FRM_REPLIC_GROUP_SET_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(46), ioc_compat_fm_pcd_frm_replic_group_params_t) -+#endif -+#define FM_PCD_IOC_FRM_REPLIC_GROUP_SET _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(46), ioc_fm_pcd_frm_replic_group_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_FrmReplicDeleteGroup -+ -+ @Description Delete a Frame Replicator group. -+ -+ @Param[in] h_FrmReplicGroup A handle to the frame replicator group. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_FrmReplicSetGroup(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_FRM_REPLIC_GROUP_DELETE_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(47), ioc_compat_fm_obj_t) -+#endif -+#define FM_PCD_IOC_FRM_REPLIC_GROUP_DELETE _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(47), ioc_fm_obj_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_FrmReplicAddMember -+ -+ @Description Add the member in the index defined by the memberIndex. -+ -+ @Param[in] h_FrmReplicGroup A handle to the frame replicator group. -+ @Param[in] memberIndex member index for adding. -+ @Param[in] p_MemberParams A pointer to the new member parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_FrmReplicSetGroup() of this group. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_FRM_REPLIC_MEMBER_ADD_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(48), ioc_compat_fm_pcd_frm_replic_member_params_t) -+#endif -+#define FM_PCD_IOC_FRM_REPLIC_MEMBER_ADD _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(48), ioc_fm_pcd_frm_replic_member_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PCD_FrmReplicRemoveMember -+ -+ @Description Remove the member defined by the index from the relevant group. -+ -+ @Param[in] h_FrmReplicGroup A handle to the frame replicator group. -+ @Param[in] memberIndex member index for removing. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PCD_FrmReplicSetGroup() of this group. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_FRM_REPLIC_MEMBER_REMOVE_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(49), ioc_compat_fm_pcd_frm_replic_member_t) -+#endif -+#define FM_PCD_IOC_FRM_REPLIC_MEMBER_REMOVE _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(49), ioc_fm_pcd_frm_replic_member_t) -+ -+#endif -+ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+/**************************************************************************//** -+ @Function FM_PCD_StatisticsSetNode -+ -+ @Description This routine should be called for defining a statistics node. -+ -+ @Param[in,out] ioc_fm_pcd_stats_params_t A structure of parameters defining the statistics -+ -+ @Return 0 on success; Error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_STATISTICS_SET_NODE_COMPAT _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(45), void *) -+#endif -+#define FM_PCD_IOC_STATISTICS_SET_NODE _IOWR(FM_IOC_TYPE_BASE, FM_PCD_IOC_NUM(45), void *) -+ -+#endif /* FM_CAPWAP_SUPPORT */ -+ -+#ifdef NCSW_BACKWARD_COMPATIBLE_API -+#if defined(CONFIG_COMPAT) -+#define FM_PCD_IOC_SET_NET_ENV_CHARACTERISTICS_COMPAT \ -+ FM_PCD_IOC_NET_ENV_CHARACTERISTICS_SET_COMPAT -+#define FM_PCD_IOC_DELETE_NET_ENV_CHARACTERISTICS_COMPAT \ -+ FM_PCD_IOC_NET_ENV_CHARACTERISTICS_DELETE_COMPAT -+#define FM_PCD_IOC_KG_SET_SCHEME_COMPAT FM_PCD_IOC_KG_SCHEME_SET_COMPAT -+#define FM_PCD_IOC_KG_DEL_SCHEME_COMPAT FM_PCD_IOC_KG_SCHEME_DELETE_COMPAT -+#define FM_PCD_IOC_CC_BUILD_TREE_COMPAT FM_PCD_IOC_CC_ROOT_BUILD_COMPAT -+#define FM_PCD_IOC_CC_DELETE_TREE_COMPAT FM_PCD_IOC_CC_ROOT_DELETE_COMPAT -+#define FM_PCD_IOC_CC_DELETE_NODE_COMPAT FM_PCD_IOC_MATCH_TABLE_DELETE_COMPAT -+#define FM_PCD_IOC_CC_TREE_MODIFY_NEXT_ENGINE_COMPAT \ -+ FM_PCD_IOC_CC_ROOT_MODIFY_NEXT_ENGINE_COMPAT -+#define FM_PCD_IOC_CC_NODE_MODIFY_NEXT_ENGINE_COMPAT \ -+ FM_PCD_IOC_MATCH_TABLE_MODIFY_NEXT_ENGINE_COMPAT -+#define FM_PCD_IOC_CC_NODE_MODIFY_MISS_NEXT_ENGINE_COMPAT \ -+ FM_PCD_IOC_MATCH_TABLE_MODIFY_MISS_NEXT_ENGINE_COMPAT -+#define FM_PCD_IOC_CC_NODE_REMOVE_KEY_COMPAT FM_PCD_IOC_MATCH_TABLE_REMOVE_KEY_COMPAT -+#define FM_PCD_IOC_CC_NODE_ADD_KEY_COMPAT FM_PCD_IOC_MATCH_TABLE_ADD_KEY_COMPAT -+#define FM_PCD_IOC_CC_NODE_MODIFY_KEY_AND_NEXT_ENGINE_COMPAT \ -+ FM_PCD_IOC_MATCH_TABLE_MODIFY_KEY_AND_NEXT_ENGINE_COMPAT -+#define FM_PCD_IOC_CC_NODE_MODIFY_KEY_COMPAT FM_PCD_IOC_MATCH_TABLE_MODIFY_KEY_COMPAT -+#define FM_PCD_IOC_PLCR_SET_PROFILE_COMPAT FM_PCD_IOC_PLCR_PROFILE_SET_COMPAT -+#define FM_PCD_IOC_PLCR_DEL_PROFILE_COMPAT FM_PCD_IOC_PLCR_PROFILE_DELETE_COMPAT -+#define FM_PCD_IOC_MANIP_SET_NODE_COMPAT FM_PCD_IOC_MANIP_NODE_SET_COMPAT -+#define FM_PCD_IOC_MANIP_DELETE_NODE_COMPAT FM_PCD_IOC_MANIP_NODE_DELETE_COMPAT -+#endif -+#define FM_PCD_IOC_SET_NET_ENV_CHARACTERISTICS FM_PCD_IOC_NET_ENV_CHARACTERISTICS_SET -+#define FM_PCD_IOC_DELETE_NET_ENV_CHARACTERISTICS \ -+ FM_PCD_IOC_NET_ENV_CHARACTERISTICS_DELETE -+#define FM_PCD_IOC_KG_SET_SCHEME FM_PCD_IOC_KG_SCHEME_SET -+#define FM_PCD_IOC_KG_DEL_SCHEME FM_PCD_IOC_KG_SCHEME_DELETE -+#define FM_PCD_IOC_CC_BUILD_TREE FM_PCD_IOC_CC_ROOT_BUILD -+#define FM_PCD_IOC_CC_DELETE_TREE FM_PCD_IOC_CC_ROOT_DELETE -+#define FM_PCD_IOC_CC_DELETE_NODE FM_PCD_IOC_MATCH_TABLE_DELETE -+#define FM_PCD_IOC_CC_TREE_MODIFY_NEXT_ENGINE FM_PCD_IOC_CC_ROOT_MODIFY_NEXT_ENGINE -+#define FM_PCD_IOC_CC_NODE_MODIFY_NEXT_ENGINE FM_PCD_IOC_MATCH_TABLE_MODIFY_NEXT_ENGINE -+#define FM_PCD_IOC_CC_NODE_MODIFY_MISS_NEXT_ENGINE \ -+ FM_PCD_IOC_MATCH_TABLE_MODIFY_MISS_NEXT_ENGINE -+#define FM_PCD_IOC_CC_NODE_REMOVE_KEY FM_PCD_IOC_MATCH_TABLE_REMOVE_KEY -+#define FM_PCD_IOC_CC_NODE_ADD_KEY FM_PCD_IOC_MATCH_TABLE_ADD_KEY -+#define FM_PCD_IOC_CC_NODE_MODIFY_KEY_AND_NEXT_ENGINE \ -+ FM_PCD_IOC_MATCH_TABLE_MODIFY_KEY_AND_NEXT_ENGINE -+#define FM_PCD_IOC_CC_NODE_MODIFY_KEY FM_PCD_IOC_MATCH_TABLE_MODIFY_KEY -+#define FM_PCD_IOC_PLCR_SET_PROFILE FM_PCD_IOC_PLCR_PROFILE_SET -+#define FM_PCD_IOC_PLCR_DEL_PROFILE FM_PCD_IOC_PLCR_PROFILE_DELETE -+#define FM_PCD_IOC_MANIP_SET_NODE FM_PCD_IOC_MANIP_NODE_SET -+#define FM_PCD_IOC_MANIP_DELETE_NODE FM_PCD_IOC_MANIP_NODE_DELETE -+#endif /* NCSW_BACKWARD_COMPATIBLE_API */ -+ -+#endif /* __FM_PCD_IOCTLS_H */ -+/** @} */ /* end of lnx_ioctl_FM_PCD_Runtime_grp group */ -+/** @} */ /* end of lnx_ioctl_FM_PCD_grp group */ -+/** @} */ /* end of lnx_ioctl_FM_grp group */ ---- /dev/null -+++ b/include/uapi/linux/fmd/Peripherals/fm_port_ioctls.h -@@ -0,0 +1,948 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/****************************************************************************** -+ @File fm_port_ioctls.h -+ -+ @Description FM Port routines -+*//***************************************************************************/ -+#ifndef __FM_PORT_IOCTLS_H -+#define __FM_PORT_IOCTLS_H -+ -+#include "enet_ext.h" -+#include "net_ioctls.h" -+#include "fm_ioctls.h" -+#include "fm_pcd_ioctls.h" -+ -+ -+/**************************************************************************//** -+ -+ @Group lnx_ioctl_FM_grp Frame Manager Linux IOCTL API -+ -+ @Description FM Linux ioctls definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_FM_PORT_grp FM Port -+ -+ @Description FM Port API -+ -+ The FM uses a general module called "port" to represent a Tx port -+ (MAC), an Rx port (MAC), offline parsing flow or host command -+ flow. There may be up to 17 (may change) ports in an FM - 5 Tx -+ ports (4 for the 1G MACs, 1 for the 10G MAC), 5 Rx Ports, and 7 -+ Host command/Offline parsing ports. The SW driver manages these -+ ports as sub-modules of the FM, i.e. after an FM is initialized, -+ its ports may be initialized and operated upon. -+ -+ The port is initialized aware of its type, but other functions on -+ a port may be indifferent to its type. When necessary, the driver -+ verifies coherency and returns error if applicable. -+ -+ On initialization, user specifies the port type and it's index -+ (relative to the port's type). Host command and Offline parsing -+ ports share the same id range, I.e user may not initialized host -+ command port 0 and offline parsing port 0. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description An enum for defining port PCD modes. -+ (Must match enum e_FmPortPcdSupport defined in fm_port_ext.h) -+ -+ This enum defines the superset of PCD engines support - i.e. not -+ all engines have to be used, but all have to be enabled. The real -+ flow of a specific frame depends on the PCD configuration and the -+ frame headers and payload. -+ Note: the first engine and the first engine after the parser (if -+ exists) should be in order, the order is important as it will -+ define the flow of the port. However, as for the rest engines -+ (the ones that follows), the order is not important anymore as -+ it is defined by the PCD graph itself. -+*//***************************************************************************/ -+typedef enum ioc_fm_port_pcd_support { -+ e_IOC_FM_PORT_PCD_SUPPORT_NONE = 0 /**< BMI to BMI, PCD is not used */ -+ , e_IOC_FM_PORT_PCD_SUPPORT_PRS_ONLY /**< Use only Parser */ -+ , e_IOC_FM_PORT_PCD_SUPPORT_PLCR_ONLY /**< Use only Policer */ -+ , e_IOC_FM_PORT_PCD_SUPPORT_PRS_AND_PLCR /**< Use Parser and Policer */ -+ , e_IOC_FM_PORT_PCD_SUPPORT_PRS_AND_KG /**< Use Parser and Keygen */ -+ , e_IOC_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_CC /**< Use Parser, Keygen and Coarse Classification */ -+ , e_IOC_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_CC_AND_PLCR -+ /**< Use all PCD engines */ -+ , e_IOC_FM_PORT_PCD_SUPPORT_PRS_AND_KG_AND_PLCR /**< Use Parser, Keygen and Policer */ -+ , e_IOC_FM_PORT_PCD_SUPPORT_PRS_AND_CC /**< Use Parser and Coarse Classification */ -+ , e_IOC_FM_PORT_PCD_SUPPORT_PRS_AND_CC_AND_PLCR /**< Use Parser and Coarse Classification and Policer */ -+ , e_IOC_FM_PORT_PCD_SUPPORT_CC_ONLY /**< Use only Coarse Classification */ -+#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) -+ , e_IOC_FM_PORT_PCD_SUPPORT_CC_AND_KG /**< Use Coarse Classification,and Keygen */ -+ , e_IOC_FM_PORT_PCD_SUPPORT_CC_AND_KG_AND_PLCR /**< Use Coarse Classification, Keygen and Policer */ -+#endif /* FM_CAPWAP_SUPPORT */ -+} ioc_fm_port_pcd_support; -+ -+ -+/**************************************************************************//** -+ @Collection FM Frame error -+*//***************************************************************************/ -+typedef uint32_t ioc_fm_port_frame_err_select_t; /**< typedef for defining Frame Descriptor errors */ -+ -+/* @} */ -+ -+ -+/**************************************************************************//** -+ @Description An enum for defining Dual Tx rate limiting scale. -+ (Must match e_FmPortDualRateLimiterScaleDown defined in fm_port_ext.h) -+*//***************************************************************************/ -+typedef enum ioc_fm_port_dual_rate_limiter_scale_down { -+ e_IOC_FM_PORT_DUAL_RATE_LIMITER_NONE = 0, /**< Use only single rate limiter */ -+ e_IOC_FM_PORT_DUAL_RATE_LIMITER_SCALE_DOWN_BY_2, /**< Divide high rate limiter by 2 */ -+ e_IOC_FM_PORT_DUAL_RATE_LIMITER_SCALE_DOWN_BY_4, /**< Divide high rate limiter by 4 */ -+ e_IOC_FM_PORT_DUAL_RATE_LIMITER_SCALE_DOWN_BY_8 /**< Divide high rate limiter by 8 */ -+} ioc_fm_port_dual_rate_limiter_scale_down; -+ -+/**************************************************************************//** -+ @Description A structure for defining Tx rate limiting -+ (Must match struct t_FmPortRateLimit defined in fm_port_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_port_rate_limit_t { -+ uint16_t max_burst_size; /**< in KBytes for Tx ports, in frames -+ for offline parsing ports. (note that -+ for early chips burst size is -+ rounded up to a multiply of 1000 frames).*/ -+ uint32_t rate_limit; /**< in Kb/sec for Tx ports, in frame/sec for -+ offline parsing ports. Rate limit refers to -+ data rate (rather than line rate). */ -+ ioc_fm_port_dual_rate_limiter_scale_down rate_limit_divider; /**< For offline parsing ports only. Not-valid -+ for some earlier chip revisions */ -+} ioc_fm_port_rate_limit_t; -+ -+ -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_FM_PORT_runtime_control_grp FM Port Runtime Control Unit -+ -+ @Description FM Port Runtime control unit API functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description An enum for defining FM Port counters. -+ (Must match enum e_FmPortCounters defined in fm_port_ext.h) -+*//***************************************************************************/ -+typedef enum ioc_fm_port_counters { -+ e_IOC_FM_PORT_COUNTERS_CYCLE, /**< BMI performance counter */ -+ e_IOC_FM_PORT_COUNTERS_TASK_UTIL, /**< BMI performance counter */ -+ e_IOC_FM_PORT_COUNTERS_QUEUE_UTIL, /**< BMI performance counter */ -+ e_IOC_FM_PORT_COUNTERS_DMA_UTIL, /**< BMI performance counter */ -+ e_IOC_FM_PORT_COUNTERS_FIFO_UTIL, /**< BMI performance counter */ -+ e_IOC_FM_PORT_COUNTERS_RX_PAUSE_ACTIVATION, /**< BMI Rx only performance counter */ -+ e_IOC_FM_PORT_COUNTERS_FRAME, /**< BMI statistics counter */ -+ e_IOC_FM_PORT_COUNTERS_DISCARD_FRAME, /**< BMI statistics counter */ -+ e_IOC_FM_PORT_COUNTERS_DEALLOC_BUF, /**< BMI deallocate buffer statistics counter */ -+ e_IOC_FM_PORT_COUNTERS_RX_BAD_FRAME, /**< BMI Rx only statistics counter */ -+ e_IOC_FM_PORT_COUNTERS_RX_LARGE_FRAME, /**< BMI Rx only statistics counter */ -+ e_IOC_FM_PORT_COUNTERS_RX_FILTER_FRAME, /**< BMI Rx & OP only statistics counter */ -+ e_IOC_FM_PORT_COUNTERS_RX_LIST_DMA_ERR, /**< BMI Rx, OP & HC only statistics counter */ -+ e_IOC_FM_PORT_COUNTERS_RX_OUT_OF_BUFFERS_DISCARD, /**< BMI Rx, OP & HC statistics counter */ -+ e_IOC_FM_PORT_COUNTERS_PREPARE_TO_ENQUEUE_COUNTER, /**< BMI Rx, OP & HC only statistics counter */ -+ e_IOC_FM_PORT_COUNTERS_WRED_DISCARD, /**< BMI OP & HC only statistics counter */ -+ e_IOC_FM_PORT_COUNTERS_LENGTH_ERR, /**< BMI non-Rx statistics counter */ -+ e_IOC_FM_PORT_COUNTERS_UNSUPPRTED_FORMAT, /**< BMI non-Rx statistics counter */ -+ e_IOC_FM_PORT_COUNTERS_DEQ_TOTAL, /**< QMI total QM dequeues counter */ -+ e_IOC_FM_PORT_COUNTERS_ENQ_TOTAL, /**< QMI total QM enqueues counter */ -+ e_IOC_FM_PORT_COUNTERS_DEQ_FROM_DEFAULT, /**< QMI counter */ -+ e_IOC_FM_PORT_COUNTERS_DEQ_CONFIRM /**< QMI counter */ -+} ioc_fm_port_counters; -+ -+typedef struct ioc_fm_port_bmi_stats_t { -+ uint32_t cnt_cycle; -+ uint32_t cnt_task_util; -+ uint32_t cnt_queue_util; -+ uint32_t cnt_dma_util; -+ uint32_t cnt_fifo_util; -+ uint32_t cnt_rx_pause_activation; -+ uint32_t cnt_frame; -+ uint32_t cnt_discard_frame; -+ uint32_t cnt_dealloc_buf; -+ uint32_t cnt_rx_bad_frame; -+ uint32_t cnt_rx_large_frame; -+ uint32_t cnt_rx_filter_frame; -+ uint32_t cnt_rx_list_dma_err; -+ uint32_t cnt_rx_out_of_buffers_discard; -+ uint32_t cnt_wred_discard; -+ uint32_t cnt_length_err; -+ uint32_t cnt_unsupported_format; -+} ioc_fm_port_bmi_stats_t; -+ -+/**************************************************************************//** -+ @Description Structure for Port id parameters. -+ (Description may be inaccurate; -+ must match struct t_FmPortCongestionGrps defined in fm_port_ext.h) -+ -+ Fields commented 'IN' are passed by the port module to be used -+ by the FM module. -+ Fields commented 'OUT' will be filled by FM before returning to port. -+*//***************************************************************************/ -+typedef struct ioc_fm_port_congestion_groups_t { -+ uint16_t num_of_congestion_grps_to_consider; /**< The number of required congestion groups -+ to define the size of the following array */ -+ uint8_t congestion_grps_to_consider [FM_PORT_NUM_OF_CONGESTION_GRPS]; -+ /**< An array of CG indexes; -+ Note that the size of the array should be -+ 'num_of_congestion_grps_to_consider'. */ -+#if DPAA_VERSION >= 11 -+ bool pfc_priorities_enable[FM_PORT_NUM_OF_CONGESTION_GRPS][FM_MAX_NUM_OF_PFC_PRIORITIES]; -+ /**< A matrix that represents the map between the CG ids -+ defined in 'congestion_grps_to_consider' to the priorities -+ mapping array. */ -+#endif /* DPAA_VERSION >= 11 */ -+} ioc_fm_port_congestion_groups_t; -+ -+ -+ -+/**************************************************************************//** -+ @Function FM_PORT_Disable -+ -+ @Description Gracefully disable an FM port. The port will not start new tasks after all -+ tasks associated with the port are terminated. -+ -+ @Return 0 on success; error code otherwise. -+ -+ @Cautions This is a blocking routine, it returns after port is -+ gracefully stopped, i.e. the port will not except new frames, -+ but it will finish all frames or tasks which were already began -+*//***************************************************************************/ -+#define FM_PORT_IOC_DISABLE _IO(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(1)) -+ -+/**************************************************************************//** -+ @Function FM_PORT_Enable -+ -+ @Description A runtime routine provided to allow disable/enable of port. -+ -+ @Return 0 on success; error code otherwise. -+*//***************************************************************************/ -+#define FM_PORT_IOC_ENABLE _IO(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(2)) -+ -+/**************************************************************************//** -+ @Function FM_PORT_SetRateLimit -+ -+ @Description Calling this routine enables rate limit algorithm. -+ By default, this functionality is disabled. -+ Note that rate-limit mechanism uses the FM time stamp. -+ The selected rate limit specified here would be -+ rounded DOWN to the nearest 16M. -+ -+ May be used for Tx and offline parsing ports only -+ -+ @Param[in] ioc_fm_port_rate_limit A structure of rate limit parameters -+ -+ @Return 0 on success; error code otherwise. -+*//***************************************************************************/ -+#define FM_PORT_IOC_SET_RATE_LIMIT _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(3), ioc_fm_port_rate_limit_t) -+ -+/**************************************************************************//** -+ @Function FM_PORT_DeleteRateLimit -+ -+ @Description Calling this routine disables the previously enabled rate limit. -+ -+ May be used for Tx and offline parsing ports only -+ -+ @Return 0 on success; error code otherwise. -+*//***************************************************************************/ -+#define FM_PORT_IOC_DELETE_RATE_LIMIT _IO(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(5)) -+#define FM_PORT_IOC_REMOVE_RATE_LIMIT FM_PORT_IOC_DELETE_RATE_LIMIT -+ -+ -+/**************************************************************************//** -+ @Function FM_PORT_AddCongestionGrps -+ -+ @Description This routine effects the corresponding Tx port. -+ It should be called in order to enable pause -+ frame transmission in case of congestion in one or more -+ of the congestion groups relevant to this port. -+ Each call to this routine may add one or more congestion -+ groups to be considered relevant to this port. -+ -+ May be used for Rx, or RX+OP ports only (depending on chip) -+ -+ @Param[in] ioc_fm_port_congestion_groups_t - A pointer to an array of -+ congestion group ids to consider. -+ -+ @Return 0 on success; error code otherwise. -+*//***************************************************************************/ -+#define FM_PORT_IOC_ADD_CONGESTION_GRPS _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(34), ioc_fm_port_congestion_groups_t) -+ -+/**************************************************************************//** -+ @Function FM_PORT_RemoveCongestionGrps -+ -+ @Description This routine effects the corresponding Tx port. It should be -+ called when congestion groups were -+ defined for this port and are no longer relevant, or pause -+ frames transmitting is not required on their behalf. -+ Each call to this routine may remove one or more congestion -+ groups to be considered relevant to this port. -+ -+ May be used for Rx, or RX+OP ports only (depending on chip) -+ -+ @Param[in] ioc_fm_port_congestion_groups_t - A pointer to an array of -+ congestion group ids to consider. -+ -+ @Return 0 on success; error code otherwise. -+*//***************************************************************************/ -+#define FM_PORT_IOC_REMOVE_CONGESTION_GRPS _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(35), ioc_fm_port_congestion_groups_t) -+ -+/**************************************************************************//** -+ @Function FM_PORT_SetErrorsRoute -+ -+ @Description Errors selected for this routine will cause a frame with that error -+ to be enqueued to error queue. -+ Errors not selected for this routine will cause a frame with that error -+ to be enqueued to the one of the other port queues. -+ By default all errors are defined to be enqueued to error queue. -+ Errors that were configured to be discarded (at initialization) -+ may not be selected here. -+ -+ May be used for Rx and offline parsing ports only -+ -+ @Param[in] ioc_fm_port_frame_err_select_t A list of errors to enqueue to error queue -+ -+ @Return 0 on success; error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+ (szbs001: How is it possible to have one function that needs to be -+ called BEFORE FM_PORT_Init() implemented as an ioctl, -+ which will ALWAYS be called AFTER the FM_PORT_Init() -+ for that port!?!?!?!???!?!??!?!?) -+*//***************************************************************************/ -+#define FM_PORT_IOC_SET_ERRORS_ROUTE _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(4), ioc_fm_port_frame_err_select_t) -+ -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_FM_PORT_pcd_runtime_control_grp FM Port PCD Runtime Control Unit -+ -+ @Description FM Port PCD Runtime control unit API functions, definitions and enums. -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description A structure defining the KG scheme after the parser. -+ (Must match struct t_FmPcdKgSchemeSelect defined in fm_port_ext.h) -+ -+ This is relevant only to change scheme selection mode - from -+ direct to indirect and vice versa, or when the scheme is selected directly, -+ to select the scheme id. -+ -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_kg_scheme_select_t { -+ bool direct; /**< TRUE to use 'scheme_id' directly, FALSE to use LCV.*/ -+ void *scheme_id; /**< Relevant for 'direct'=TRUE only. -+ 'scheme_id' selects the scheme after parser. */ -+} ioc_fm_pcd_kg_scheme_select_t; -+ -+/**************************************************************************//** -+ @Description Scheme IDs structure -+ (Must match struct t_FmPcdPortSchemesParams defined in fm_port_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_port_schemes_params_t { -+ uint8_t num_of_schemes; /**< Number of schemes for port to be bound to. */ -+ void *scheme_ids[FM_PCD_KG_NUM_OF_SCHEMES]; /**< Array of 'num_of_schemes' schemes for the -+ port to be bound to */ -+} ioc_fm_pcd_port_schemes_params_t; -+ -+/**************************************************************************//** -+ @Description A union for defining port protocol parameters for parser -+ (Must match union u_FmPcdHdrPrsOpts defined in fm_port_ext.h) -+*//***************************************************************************/ -+typedef union ioc_fm_pcd_hdr_prs_opts_u { -+ /* MPLS */ -+ struct { -+ bool label_interpretation_enable;/**< When this bit is set, the last MPLS label will be -+ interpreted as described in HW spec table. When the bit -+ is cleared, the parser will advance to MPLS next parse */ -+ ioc_net_header_type next_parse; /**< must be equal or higher than IPv4 */ -+ } mpls_prs_options; -+ -+ /* VLAN */ -+ struct { -+ uint16_t tag_protocol_id1; /**< User defined Tag Protocol Identifier, to be recognized -+ on VLAN TAG on top of 0x8100 and 0x88A8 */ -+ uint16_t tag_protocol_id2; /**< User defined Tag Protocol Identifier, to be recognized -+ on VLAN TAG on top of 0x8100 and 0x88A8 */ -+ } vlan_prs_options; -+ -+ /* PPP */ -+ struct{ -+ bool enable_mtu_check; /**< Check validity of MTU according to RFC2516 */ -+ } pppoe_prs_options; -+ -+ /* IPV6 */ -+ struct { -+ bool routing_hdr_disable; /**< Disable routing header */ -+ } ipv6_prs_options; -+ -+ /* UDP */ -+ struct { -+ bool pad_ignore_checksum; /**< TRUE to ignore pad in checksum */ -+ } udp_prs_options; -+ -+ /* TCP */ -+ struct { -+ bool pad_ignore_checksum; /**< TRUE to ignore pad in checksum */ -+ } tcp_prs_options; -+} ioc_fm_pcd_hdr_prs_opts_u; -+ -+/**************************************************************************//** -+ @Description A structure for defining each header for the parser -+ (must match struct t_FmPcdPrsAdditionalHdrParams defined in fm_port_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_prs_additional_hdr_params_t { -+ ioc_net_header_type hdr; /**< Selected header */ -+ bool err_disable; /**< TRUE to disable error indication */ -+ bool soft_prs_enable; /**< Enable jump to SW parser when this -+ header is recognized by the HW parser. */ -+ uint8_t index_per_hdr; /**< Normally 0, if more than one sw parser -+ attachments exists for the same header, -+ (in the main sw parser code) use this -+ index to distinguish between them. */ -+ bool use_prs_opts; /**< TRUE to use parser options. */ -+ ioc_fm_pcd_hdr_prs_opts_u prs_opts; /**< A unuion according to header type, -+ defining the parser options selected.*/ -+} ioc_fm_pcd_prs_additional_hdr_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for defining port PCD parameters -+ (Must match t_FmPortPcdPrsParams defined in fm_port_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_port_pcd_prs_params_t { -+ uint8_t prs_res_priv_info; /**< The private info provides a method of inserting -+ port information into the parser result. This information -+ may be extracted by KeyGen and be used for frames -+ distribution when a per-port distinction is required, -+ it may also be used as a port logical id for analyzing -+ incoming frames. */ -+ uint8_t parsing_offset; /**< Number of bytes from begining of packet to start parsing */ -+ ioc_net_header_type first_prs_hdr; /**< The type of the first header axpected at 'parsing_offset' */ -+ bool include_in_prs_statistics; /**< TRUE to include this port in the parser statistics */ -+ uint8_t num_of_hdrs_with_additional_params; -+ /**< Normally 0, some headers may get special parameters */ -+ ioc_fm_pcd_prs_additional_hdr_params_t additional_params[IOC_FM_PCD_PRS_NUM_OF_HDRS]; -+ /**< 'num_of_hdrs_with_additional_params' structures -+ additional parameters for each header that requires them */ -+ bool set_vlan_tpid1; /**< TRUE to configure user selection of Ethertype to -+ indicate a VLAN tag (in addition to the TPID values -+ 0x8100 and 0x88A8). */ -+ uint16_t vlan_tpid1; /**< extra tag to use if set_vlan_tpid1=TRUE. */ -+ bool set_vlan_tpid2; /**< TRUE to configure user selection of Ethertype to -+ indicate a VLAN tag (in addition to the TPID values -+ 0x8100 and 0x88A8). */ -+ uint16_t vlan_tpid2; /**< extra tag to use if set_vlan_tpid1=TRUE. */ -+} ioc_fm_port_pcd_prs_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for defining coarse alassification parameters -+ (Must match t_FmPortPcdCcParams defined in fm_port_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_port_pcd_cc_params_t { -+ void *cc_tree_id; /**< CC tree id */ -+} ioc_fm_port_pcd_cc_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for defining keygen parameters -+ (Must match t_FmPortPcdKgParams defined in fm_port_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_port_pcd_kg_params_t { -+ uint8_t num_of_schemes; /**< Number of schemes for port to be bound to. */ -+ void *scheme_ids[FM_PCD_KG_NUM_OF_SCHEMES]; -+ /**< Array of 'num_of_schemes' schemes for the -+ port to be bound to */ -+ bool direct_scheme; /**< TRUE for going from parser to a specific scheme, -+ regardless of parser result */ -+ void *direct_scheme_id; /**< Scheme id, as returned by FM_PCD_KgSetScheme; -+ relevant only if direct=TRUE. */ -+} ioc_fm_port_pcd_kg_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for defining policer parameters -+ (Must match t_FmPortPcdPlcrParams defined in fm_port_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_port_pcd_plcr_params_t { -+ void *plcr_profile_id; /**< Selected profile handle; -+ relevant in one of the following cases: -+ e_IOC_FM_PORT_PCD_SUPPORT_PLCR_ONLY or -+ e_IOC_FM_PORT_PCD_SUPPORT_PRS_AND_PLCR were selected, -+ or if any flow uses a KG scheme where policer -+ profile is not generated (bypass_plcr_profile_generation selected) */ -+} ioc_fm_port_pcd_plcr_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for defining port PCD parameters -+ (Must match struct t_FmPortPcdParams defined in fm_port_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_port_pcd_params_t { -+ ioc_fm_port_pcd_support pcd_support; /**< Relevant for Rx and offline ports only. -+ Describes the active PCD engines for this port. */ -+ void *net_env_id; /**< HL Unused in PLCR only mode */ -+ ioc_fm_port_pcd_prs_params_t *p_prs_params; /**< Parser parameters for this port */ -+ ioc_fm_port_pcd_cc_params_t *p_cc_params; /**< Coarse classification parameters for this port */ -+ ioc_fm_port_pcd_kg_params_t *p_kg_params; /**< Keygen parameters for this port */ -+ ioc_fm_port_pcd_plcr_params_t *p_plcr_params; /**< Policer parameters for this port */ -+ void *p_ip_reassembly_manip;/**< IP Reassembly manipulation */ -+#if (DPAA_VERSION >= 11) -+ void *p_capwap_reassembly_manip;/**< CAPWAP Reassembly manipulation */ -+#endif /* (DPAA_VERSION >= 11) */ -+} ioc_fm_port_pcd_params_t; -+ -+/**************************************************************************//** -+ @Description A structure for defining the Parser starting point -+ (Must match struct t_FmPcdPrsStart defined in fm_port_ext.h) -+*//***************************************************************************/ -+typedef struct ioc_fm_pcd_prs_start_t { -+ uint8_t parsing_offset; /**< Number of bytes from begining of packet to -+ start parsing */ -+ ioc_net_header_type first_prs_hdr; /**< The type of the first header axpected at -+ 'parsing_offset' */ -+} ioc_fm_pcd_prs_start_t; -+ -+ -+/**************************************************************************//** -+ @Description FQID parameters structure -+*//***************************************************************************/ -+typedef struct ioc_fm_port_pcd_fqids_params_t { -+ uint32_t num_fqids; /**< Number of fqids to be allocated for the port */ -+ uint8_t alignment; /**< Alignment required for this port */ -+ uint32_t base_fqid; /**< output parameter - the base fqid */ -+} ioc_fm_port_pcd_fqids_params_t; -+ -+ -+/**************************************************************************//** -+ @Function FM_PORT_IOC_ALLOC_PCD_FQIDS -+ -+ @Description Allocates FQID's -+ -+ May be used for Rx and offline parsing ports only -+ -+ @Param[in,out] ioc_fm_port_pcd_fqids_params_t Parameters for allocating FQID's -+ -+ @Return 0 on success; error code otherwise. -+*//***************************************************************************/ -+#define FM_PORT_IOC_ALLOC_PCD_FQIDS _IOWR(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(19), ioc_fm_port_pcd_fqids_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PORT_IOC_FREE_PCD_FQIDS -+ -+ @Description Frees previously-allocated FQIDs -+ -+ May be used for Rx and offline parsing ports only -+ -+ @Param[in] uint32_t Base FQID of previously allocated range. -+ -+ @Return 0 on success; error code otherwise. -+*//***************************************************************************/ -+#define FM_PORT_IOC_FREE_PCD_FQIDS _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(19), uint32_t) -+ -+ -+/**************************************************************************//** -+ @Function FM_PORT_SetPCD -+ -+ @Description Calling this routine defines the port's PCD configuration. -+ It changes it from its default configuration which is PCD -+ disabled (BMI to BMI) and configures it according to the passed -+ parameters. -+ -+ May be used for Rx and offline parsing ports only -+ -+ @Param[in] ioc_fm_port_pcd_params_t A Structure of parameters defining the port's PCD -+ configuration. -+ -+ @Return 0 on success; error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PORT_IOC_SET_PCD_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(20), ioc_compat_fm_port_pcd_params_t) -+#endif -+#define FM_PORT_IOC_SET_PCD _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(20), ioc_fm_port_pcd_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PORT_DeletePCD -+ -+ @Description Calling this routine releases the port's PCD configuration. -+ The port returns to its default configuration which is PCD -+ disabled (BMI to BMI) and all PCD configuration is removed. -+ -+ May be used for Rx and offline parsing ports which are -+ in PCD mode only -+ -+ @Return 0 on success; error code otherwise. -+*//***************************************************************************/ -+#define FM_PORT_IOC_DELETE_PCD _IO(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(21)) -+ -+/**************************************************************************//** -+ @Function FM_PORT_AttachPCD -+ -+ @Description This routine may be called after FM_PORT_DetachPCD was called, -+ to return to the originally configured PCD support flow. -+ The couple of routines are used to allow PCD configuration changes -+ that demand that PCD will not be used while changes take place. -+ -+ May be used for Rx and offline parsing ports which are -+ in PCD mode only -+ -+ @Return 0 on success; error code otherwise. -+*//***************************************************************************/ -+#define FM_PORT_IOC_ATTACH_PCD _IO(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(23)) -+ -+/**************************************************************************//** -+ @Function FM_PORT_DetachPCD -+ -+ @Description Calling this routine detaches the port from its PCD functionality. -+ The port returns to its default flow which is BMI to BMI. -+ -+ May be used for Rx and offline parsing ports which are -+ in PCD mode only -+ -+ @Return 0 on success; error code otherwise. -+*//***************************************************************************/ -+#define FM_PORT_IOC_DETACH_PCD _IO(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(22)) -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdPlcrAllocProfiles -+ -+ @Description This routine may be called only for ports that use the Policer in -+ order to allocate private policer profiles. -+ -+ @Param[in] uint16_t The number of required policer profiles -+ -+ @Return 0 on success; error code otherwise. -+ -+ @Cautions Allowed before FM_PORT_SetPCD() only. -+*//***************************************************************************/ -+#define FM_PORT_IOC_PCD_PLCR_ALLOC_PROFILES _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(24), uint16_t) -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdPlcrFreeProfiles -+ -+ @Description This routine should be called for freeing private policer profiles. -+ -+ @Return 0 on success; error code otherwise. -+ -+ @Cautions Allowed before FM_PORT_SetPCD() only. -+*//***************************************************************************/ -+#define FM_PORT_IOC_PCD_PLCR_FREE_PROFILES _IO(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(25)) -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdKgModifyInitialScheme -+ -+ @Description This routine may be called only for ports that use the keygen in -+ order to change the initial scheme frame should be routed to. -+ The change may be of a scheme id (in case of direct mode), -+ from direct to indirect, or from indirect to direct - specifying the scheme id. -+ -+ @Param[in] ioc_fm_pcd_kg_scheme_select_t A structure of parameters for defining whether -+ a scheme is direct/indirect, and if direct - scheme id. -+ -+ @Return 0 on success; error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PORT_IOC_PCD_KG_MODIFY_INITIAL_SCHEME_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(26), ioc_compat_fm_pcd_kg_scheme_select_t) -+#endif -+#define FM_PORT_IOC_PCD_KG_MODIFY_INITIAL_SCHEME _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(26), ioc_fm_pcd_kg_scheme_select_t) -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdPlcrModifyInitialProfile -+ -+ @Description This routine may be called for ports with flows -+ e_IOC_FM_PCD_SUPPORT_PLCR_ONLY or e_IOC_FM_PCD_SUPPORT_PRS_AND_PLCR only, -+ to change the initial Policer profile frame should be routed to. -+ The change may be of a profile and/or absolute/direct mode selection. -+ -+ @Param[in] ioc_fm_obj_t Policer profile Id as returned from FM_PCD_PlcrSetProfile. -+ -+ @Return 0 on success; error code otherwise. -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PORT_IOC_PCD_PLCR_MODIFY_INITIAL_PROFILE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(27), ioc_compat_fm_obj_t) -+#endif -+#define FM_PORT_IOC_PCD_PLCR_MODIFY_INITIAL_PROFILE _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(27), ioc_fm_obj_t) -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdCcModifyTree -+ -+ @Description This routine may be called to change this port connection to -+ a pre-initializes coarse classification Tree. -+ -+ @Param[in] ioc_fm_obj_t Id of new coarse classification tree selected for this port. -+ -+ @Return 0 on success; error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_SetPCD() and FM_PORT_DetachPCD() -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PORT_IOC_PCD_CC_MODIFY_TREE_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(28), ioc_compat_fm_obj_t) -+#endif -+#define FM_PORT_IOC_PCD_CC_MODIFY_TREE _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(28), ioc_fm_obj_t) -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdKgBindSchemes -+ -+ @Description These routines may be called for modifying the binding of ports -+ to schemes. The scheme itself is not added, -+ just this specific port starts using it. -+ -+ @Param[in] ioc_fm_pcd_port_schemes_params_t Schemes parameters structre -+ -+ @Return 0 on success; error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_SetPCD(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PORT_IOC_PCD_KG_BIND_SCHEMES_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(30), ioc_compat_fm_pcd_port_schemes_params_t) -+#endif -+#define FM_PORT_IOC_PCD_KG_BIND_SCHEMES _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(30), ioc_fm_pcd_port_schemes_params_t) -+ -+/**************************************************************************//** -+ @Function FM_PORT_PcdKgUnbindSchemes -+ -+ @Description These routines may be called for modifying the binding of ports -+ to schemes. The scheme itself is not removed or invalidated, -+ just this specific port stops using it. -+ -+ @Param[in] ioc_fm_pcd_port_schemes_params_t Schemes parameters structre -+ -+ @Return 0 on success; error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_SetPCD(). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PORT_IOC_PCD_KG_UNBIND_SCHEMES_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(31), ioc_compat_fm_pcd_port_schemes_params_t) -+#endif -+#define FM_PORT_IOC_PCD_KG_UNBIND_SCHEMES _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(31), ioc_fm_pcd_port_schemes_params_t) -+ -+typedef struct ioc_fm_port_mac_addr_params_t { -+ uint8_t addr[ENET_NUM_OCTETS_PER_ADDRESS]; -+} ioc_fm_port_mac_addr_params_t; -+ -+/**************************************************************************//** -+ @Function FM_MAC_AddHashMacAddr -+ -+ @Description Add an Address to the hash table. This is for filter purpose only. -+ -+ @Param[in] ioc_fm_port_mac_addr_params_t - Ethernet Mac address -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). It is a filter only address. -+ @Cautions Some address need to be filtered out in upper FM blocks. -+*//***************************************************************************/ -+#define FM_PORT_IOC_ADD_RX_HASH_MAC_ADDR _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(36), ioc_fm_port_mac_addr_params_t) -+ -+/**************************************************************************//** -+ @Function FM_MAC_RemoveHashMacAddr -+ -+ @Description Delete an Address to the hash table. This is for filter purpose only. -+ -+ @Param[in] ioc_fm_port_mac_addr_params_t - Ethernet Mac address -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+*//***************************************************************************/ -+#define FM_PORT_IOC_REMOVE_RX_HASH_MAC_ADDR _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(37), ioc_fm_port_mac_addr_params_t) -+ -+typedef struct ioc_fm_port_tx_pause_frames_params_t { -+ uint8_t priority; -+ uint16_t pause_time; -+ uint16_t thresh_time; -+} ioc_fm_port_tx_pause_frames_params_t; -+ -+/**************************************************************************//** -+ @Function FM_MAC_SetTxPauseFrames -+ -+ @Description Enable/Disable transmission of Pause-Frames. -+ The routine changes the default configuration: -+ pause-time - [0xf000] -+ threshold-time - [0] -+ -+ @Param[in] ioc_fm_port_tx_pause_frames_params_t A structure holding the required parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+ PFC is supported only on new mEMAC; i.e. in MACs that don't have -+ PFC support (10G-MAC and dTSEC), user should use 'FM_MAC_NO_PFC' -+ in the 'priority' field. -+*//***************************************************************************/ -+#define FM_PORT_IOC_SET_TX_PAUSE_FRAMES _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(40), ioc_fm_port_tx_pause_frames_params_t) -+ -+typedef struct ioc_fm_port_mac_statistics_t { -+ /* RMON */ -+ uint64_t e_stat_pkts_64; /**< r-10G tr-DT 64 byte frame counter */ -+ uint64_t e_stat_pkts_65_to_127; /**< r-10G 65 to 127 byte frame counter */ -+ uint64_t e_stat_pkts_128_to_255; /**< r-10G 128 to 255 byte frame counter */ -+ uint64_t e_stat_pkts_256_to_511; /**< r-10G 256 to 511 byte frame counter */ -+ uint64_t e_stat_pkts_512_to_1023; /**< r-10G 512 to 1023 byte frame counter */ -+ uint64_t e_stat_pkts_1024_to_1518; /**< r-10G 1024 to 1518 byte frame counter */ -+ uint64_t e_stat_pkts_1519_to_1522; /**< r-10G 1519 to 1522 byte good frame count */ -+ /* */ -+ uint64_t e_stat_fragments; /**< Total number of packets that were less than 64 octets long with a wrong CRC.*/ -+ uint64_t e_stat_jabbers; /**< Total number of packets longer than valid maximum length octets */ -+ uint64_t e_stat_drop_events; /**< number of dropped packets due to internal errors of the MAC Client (during recieve). */ -+ uint64_t e_stat_CRC_align_errors; /**< Incremented when frames of correct length but with CRC error are received.*/ -+ uint64_t e_stat_undersize_pkts; /**< Incremented for frames under 64 bytes with a valid FCS and otherwise well formed; -+ This count does not include range length errors */ -+ uint64_t e_stat_oversize_pkts; /**< Incremented for frames which exceed 1518 (non VLAN) or 1522 (VLAN) and contains -+ a valid FCS and otherwise well formed */ -+ /* Pause */ -+ uint64_t te_stat_pause; /**< Pause MAC Control received */ -+ uint64_t re_stat_pause; /**< Pause MAC Control sent */ -+ /* MIB II */ -+ uint64_t if_in_octets; /**< Total number of byte received. */ -+ uint64_t if_in_pkts; /**< Total number of packets received.*/ -+ uint64_t if_in_ucast_pkts; /**< Total number of unicast frame received; -+ NOTE: this counter is not supported on dTSEC MAC */ -+ uint64_t if_in_mcast_pkts; /**< Total number of multicast frame received*/ -+ uint64_t if_in_bcast_pkts; /**< Total number of broadcast frame received */ -+ uint64_t if_in_discards; /**< Frames received, but discarded due to problems within the MAC RX. */ -+ uint64_t if_in_errors; /**< Number of frames received with error: -+ - FIFO Overflow Error -+ - CRC Error -+ - Frame Too Long Error -+ - Alignment Error -+ - The dedicated Error Code (0xfe, not a code error) was received */ -+ uint64_t if_out_octets; /**< Total number of byte sent. */ -+ uint64_t if_out_pkts; /**< Total number of packets sent .*/ -+ uint64_t if_out_ucast_pkts; /**< Total number of unicast frame sent; -+ NOTE: this counter is not supported on dTSEC MAC */ -+ uint64_t if_out_mcast_pkts; /**< Total number of multicast frame sent */ -+ uint64_t if_out_bcast_pkts; /**< Total number of multicast frame sent */ -+ uint64_t if_out_discards; /**< Frames received, but discarded due to problems within the MAC TX N/A!.*/ -+ uint64_t if_out_errors; /**< Number of frames transmitted with error: -+ - FIFO Overflow Error -+ - FIFO Underflow Error -+ - Other */ -+} ioc_fm_port_mac_statistics_t; -+ -+/**************************************************************************//** -+ @Function FM_MAC_GetStatistics -+ -+ @Description get all MAC statistics counters -+ -+ @Param[out] ioc_fm_port_mac_statistics_t A structure holding the statistics -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_Init(). -+*//***************************************************************************/ -+#define FM_PORT_IOC_GET_MAC_STATISTICS _IOR(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(41), ioc_fm_port_mac_statistics_t) -+ -+/**************************************************************************//** -+ @Function FM_PORT_ConfigBufferPrefixContent -+ -+ @Description Defines the structure, size and content of the application buffer. -+ The prefix will -+ In Tx ports, if 'passPrsResult', the application -+ should set a value to their offsets in the prefix of -+ the FM will save the first 'privDataSize', than, -+ depending on 'passPrsResult' and 'passTimeStamp', copy parse result -+ and timeStamp, and the packet itself (in this order), to the -+ application buffer, and to offset. -+ Calling this routine changes the buffer margins definitions -+ in the internal driver data base from its default -+ configuration: Data size: [DEFAULT_FM_SP_bufferPrefixContent_privDataSize] -+ Pass Parser result: [DEFAULT_FM_SP_bufferPrefixContent_passPrsResult]. -+ Pass timestamp: [DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp]. -+ -+ May be used for all ports -+ -+ @Param[in] ioc_fm_buffer_prefix_content_t A structure holding the required parameters. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Config() and before FM_PORT_Init(). -+*//***************************************************************************/ -+#define FM_PORT_IOC_CONFIG_BUFFER_PREFIX_CONTENT _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(39), ioc_fm_buffer_prefix_content_t) -+ -+#if (DPAA_VERSION >= 11) -+typedef struct ioc_fm_port_vsp_alloc_params_t { -+ uint8_t num_of_profiles; /**< Number of Virtual Storage Profiles */ -+ uint8_t dflt_relative_id; /**< The default Virtual-Storage-Profile-id dedicated to Rx/OP port -+ The same default Virtual-Storage-Profile-id will be for coupled Tx port -+ if relevant function called for Rx port */ -+ void *p_fm_tx_port; /**< Handle to coupled Tx Port; not relevant for OP port. */ -+}ioc_fm_port_vsp_alloc_params_t; -+ -+/**************************************************************************//** -+ @Function FM_PORT_VSPAlloc -+ -+ @Description This routine allocated VSPs per port and forces the port to work -+ in VSP mode. Note that the port is initialized by default with the -+ physical-storage-profile only. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[in] p_Params A structure of parameters for allocation VSP's per port -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(), and before FM_PORT_SetPCD() -+ and also before FM_PORT_Enable() (i.e. the port should be disabled). -+*//***************************************************************************/ -+#if defined(CONFIG_COMPAT) -+#define FM_PORT_IOC_VSP_ALLOC_COMPAT _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(38), ioc_compat_fm_port_vsp_alloc_params_t) -+#endif -+#define FM_PORT_IOC_VSP_ALLOC _IOW(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(38), ioc_fm_port_vsp_alloc_params_t) -+#endif /* (DPAA_VERSION >= 11) */ -+ -+/**************************************************************************//** -+ @Function FM_PORT_GetBmiCounters -+ -+ @Description Read port's BMI stat counters and place them into -+ a designated structure of counters. -+ -+ @Param[in] h_FmPort A handle to a FM Port module. -+ @Param[out] p_BmiStats counters structure -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_PORT_Init(). -+*//***************************************************************************/ -+ -+#define FM_PORT_IOC_GET_BMI_COUNTERS _IOR(FM_IOC_TYPE_BASE, FM_PORT_IOC_NUM(42), ioc_fm_port_bmi_stats_t) -+ -+ -+/** @} */ /* end of lnx_ioctl_FM_PORT_pcd_runtime_control_grp group */ -+/** @} */ /* end of lnx_ioctl_FM_PORT_runtime_control_grp group */ -+ -+/** @} */ /* end of lnx_ioctl_FM_PORT_grp group */ -+/** @} */ /* end of lnx_ioctl_FM_grp group */ -+#endif /* __FM_PORT_IOCTLS_H */ ---- /dev/null -+++ b/include/uapi/linux/fmd/Peripherals/fm_test_ioctls.h -@@ -0,0 +1,208 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ @File fm_test_ioctls.h -+ -+ @Description FM Char device ioctls -+*//***************************************************************************/ -+#ifndef __FM_TEST_IOCTLS_H -+#define __FM_TEST_IOCTLS_H -+ -+#include "ioctls.h" -+ -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_FMT_grp Frame Manager Test Linux IOCTL API -+ -+ @Description FM-Test Linux ioctls definitions and enums -+ -+ @{ -+*//***************************************************************************/ -+ -+#define IOC_FMT_MAX_NUM_OF_PORTS 26 -+ -+/**************************************************************************//** -+ @Collection TEST Parameters -+*//***************************************************************************/ -+/**************************************************************************//** -+ @Description: Name of the FM-Test chardev -+*//***************************************************************************/ -+#define DEV_FM_TEST_NAME "fm-test-port" -+ -+#define DEV_FM_TEST_PORTS_MINOR_BASE 0 -+#define DEV_FM_TEST_MAX_MINORS (DEV_FM_TEST_PORTS_MINOR_BASE + IOC_FMT_MAX_NUM_OF_PORTS) -+ -+#define FMT_PORT_IOC_NUM(n) n -+/* @} */ -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_FMT_lib_grp FM-Test library -+ -+ @Description TODO -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description TODO -+*//***************************************************************************/ -+typedef uint8_t ioc_fmt_xxx_t; -+ -+#define FM_PRS_MAX 32 -+#define FM_TIME_STAMP_MAX 8 -+ -+/**************************************************************************//** -+ @Description FM Port buffer content description -+*//***************************************************************************/ -+typedef struct ioc_fmt_buff_context_t { -+ void *p_user_priv; -+ uint8_t fm_prs_res[FM_PRS_MAX]; -+ uint8_t fm_time_stamp[FM_TIME_STAMP_MAX]; -+} ioc_fmt_buff_context_t; -+ -+#if defined(__KERNEL__) && defined(CONFIG_COMPAT) -+typedef struct ioc_fmt_compat_buff_context_t { -+ compat_uptr_t p_user_priv; -+ uint8_t fm_prs_res[FM_PRS_MAX]; -+ uint8_t fm_time_stamp[FM_TIME_STAMP_MAX]; -+} ioc_fmt_compat_buff_context_t; -+#endif -+ -+/**************************************************************************//** -+ @Description Buffer descriptor -+*//***************************************************************************/ -+typedef struct ioc_fmt_buff_desc_t { -+ uint32_t qid; -+ void *p_data; -+ uint32_t size; -+ uint32_t status; -+ ioc_fmt_buff_context_t buff_context; -+} ioc_fmt_buff_desc_t; -+ -+#if defined(__KERNEL__) && defined(CONFIG_COMPAT) -+typedef struct ioc_fmt_compat_buff_desc_t { -+ uint32_t qid; -+ compat_uptr_t p_data; -+ uint32_t size; -+ uint32_t status; -+ ioc_fmt_compat_buff_context_t buff_context; -+} ioc_fmt_compat_buff_desc_t; -+#endif -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_FMT_runtime_control_grp FM-Test Runtime Control Unit -+ -+ @Description TODO -+ @{ -+*//***************************************************************************/ -+ -+/** @} */ /* end of lnx_ioctl_FMT_runtime_control_grp group */ -+ -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_FMTP_lib_grp FM-Port-Test library -+ -+ @Description TODO -+ -+ @{ -+*//***************************************************************************/ -+ -+/**************************************************************************//** -+ @Description FM-Test FM port type -+*//***************************************************************************/ -+typedef enum ioc_fmt_port_type { -+ e_IOC_FMT_PORT_T_RXTX, /**< Standard port */ -+ e_IOC_FMT_PORT_T_OP, /**< Offline-parsing port */ -+} ioc_fmt_port_type; -+ -+/**************************************************************************//** -+ @Description TODO -+*//***************************************************************************/ -+typedef struct ioc_fmt_port_param_t { -+ uint8_t fm_id; -+ ioc_fmt_port_type fm_port_type; -+ uint8_t fm_port_id; -+ uint32_t num_tx_queues; -+} ioc_fmt_port_param_t; -+ -+ -+/**************************************************************************//** -+ @Function FMT_PORT_IOC_INIT -+ -+ @Description TODO -+ -+ @Param[in] ioc_fmt_port_param_t TODO -+ -+ @Cautions Allowed only after the FM equivalent port is already initialized. -+*//***************************************************************************/ -+#define FMT_PORT_IOC_INIT _IOW(FMT_IOC_TYPE_BASE, FMT_PORT_IOC_NUM(0), ioc_fmt_port_param_t) -+ -+/**************************************************************************//** -+ @Function FMT_PORT_IOC_SET_DIAG_MODE -+ -+ @Description TODO -+ -+ @Param[in] ioc_diag_mode TODO -+ -+ @Cautions Allowed only following FMT_PORT_IOC_INIT(). -+*//***************************************************************************/ -+#define FMT_PORT_IOC_SET_DIAG_MODE _IOW(FMT_IOC_TYPE_BASE, FMT_PORT_IOC_NUM(1), ioc_diag_mode) -+ -+/**************************************************************************//** -+ @Function FMT_PORT_IOC_SET_IP_HEADER_MANIP -+ -+ @Description Set IP header manipulations for this port. -+ -+ @Param[in] int 1 to enable; 0 to disable -+ -+ @Cautions Allowed only following FMT_PORT_IOC_INIT(). -+*//***************************************************************************/ -+#define FMT_PORT_IOC_SET_IP_HEADER_MANIP _IOW(FMT_IOC_TYPE_BASE, FMT_PORT_IOC_NUM(2), int) -+ -+/**************************************************************************//** -+ @Function FMT_PORT_IOC_SET_DPAECHO_MODE -+ -+ @Description Set DPA in echo mode - all frame are sent back. -+ -+ @Param[in] int 1 to enable; 0 to disable -+ -+ @Cautions Allowed only following FMT_PORT_IOC_INIT(). -+*//***************************************************************************/ -+#define FMT_PORT_IOC_SET_DPAECHO_MODE _IOW(FMT_IOC_TYPE_BASE, FMT_PORT_IOC_NUM(3), int) -+ -+/** @} */ /* end of lnx_ioctl_FMTP_lib_grp group */ -+/** @} */ /* end of lnx_ioctl_FMT_lib_grp group */ -+/** @} */ /* end of lnx_ioctl_FMT_grp */ -+ -+ -+#endif /* __FM_TEST_IOCTLS_H */ ---- /dev/null -+++ b/include/uapi/linux/fmd/integrations/Kbuild -@@ -0,0 +1 @@ -+header-y += integration_ioctls.h ---- /dev/null -+++ b/include/uapi/linux/fmd/integrations/integration_ioctls.h -@@ -0,0 +1,56 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ @File integration_ioctls.h -+ -+ @Description External header file for Integration unit routines. -+*//***************************************************************************/ -+ -+#ifndef __INTG_IOCTLS_H -+#define __INTG_IOCTLS_H -+ -+ -+#define FM_IOC_TYPE_BASE (NCSW_IOC_TYPE_BASE+1) -+#define FMT_IOC_TYPE_BASE (NCSW_IOC_TYPE_BASE+3) -+ -+/*#define FM_IOCTL_DBG*/ -+ -+#if defined(FM_IOCTL_DBG) -+ #define _fm_ioctl_dbg(format, arg...) \ -+ printk("fm ioctl [%s:%u](cpu:%u) - " format, \ -+ __func__, __LINE__, smp_processor_id(), ##arg) -+#else -+# define _fm_ioctl_dbg(arg...) -+#endif -+ -+#endif /* __INTG_IOCTLS_H */ ---- /dev/null -+++ b/include/uapi/linux/fmd/ioctls.h -@@ -0,0 +1,96 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/**************************************************************************//** -+ @File ioctls.h -+ -+ @Description Structures and definitions for Command Relay Ioctls -+*//***************************************************************************/ -+ -+#ifndef __IOCTLS_H__ -+#define __IOCTLS_H__ -+ -+#include -+ -+#include "integration_ioctls.h" -+ -+ -+/**************************************************************************//** -+ @Group lnx_ioctl_ncsw_grp NetCommSw Linux User-Space (IOCTL) API -+ @{ -+*//***************************************************************************/ -+ -+#define NCSW_IOC_TYPE_BASE 0xe0 /**< defines the IOCTL type for all -+ the NCSW Linux module commands */ -+ -+ -+/**************************************************************************//** -+ @Description IOCTL Memory allocation types. -+*//***************************************************************************/ -+typedef enum ioc_mem_type { -+ e_IOC_MEM_INVALID = 0x00000000, /**< Invalid memory type (error) */ -+ e_IOC_MEM_CACHABLE_SYS = 0x00000001, /**< Primary DDR, cacheable segment */ -+ e_IOC_MEM_NOCACHE_SYS = 0x00000004, /**< Primary DDR, non-cacheable segment */ -+ e_IOC_MEM_SECONDARY = 0x00000002, /**< Either secondary DDR or SDRAM */ -+ e_IOC_MEM_PRAM = 0x00000008 /**< Multi-user RAM identifier */ -+} ioc_mem_type; -+ -+/**************************************************************************//** -+ @Description Enumeration (bit flags) of communication modes (Transmit, -+ receive or both). -+*//***************************************************************************/ -+typedef enum ioc_comm_mode { -+ e_IOC_COMM_MODE_NONE = 0 /**< No transmit/receive communication */ -+ , e_IOC_COMM_MODE_RX = 1 /**< Only receive communication */ -+ , e_IOC_COMM_MODE_TX = 2 /**< Only transmit communication */ -+ , e_IOC_COMM_MODE_RX_AND_TX = 3 /**< Both transmit and receive communication */ -+} ioc_comm_mode; -+ -+/**************************************************************************//** -+ @Description General Diagnostic Mode -+*//***************************************************************************/ -+typedef enum ioc_diag_mode -+{ -+ e_IOC_DIAG_MODE_NONE = 0, -+ e_IOC_DIAG_MODE_CTRL_LOOPBACK, /**< loopback in the controller; E.g. MAC, TDM, etc. */ -+ e_IOC_DIAG_MODE_CHIP_LOOPBACK, /**< loopback in the chip but not in controller; -+ E.g. IO-pins, SerDes, etc. */ -+ e_IOC_DIAG_MODE_PHY_LOOPBACK, /**< loopback in the external PHY */ -+ e_IOC_DIAG_MODE_LINE_LOOPBACK, /**< loopback in the external line */ -+ e_IOC_DIAG_MODE_CTRL_ECHO, /**< */ -+ e_IOC_DIAG_MODE_PHY_ECHO /**< */ -+} ioc_diag_mode; -+ -+/** @} */ /* end of lnx_ioctl_ncsw_grp */ -+ -+ -+#endif /* __IOCTLS_H__ */ ---- /dev/null -+++ b/include/uapi/linux/fmd/net_ioctls.h -@@ -0,0 +1,430 @@ -+/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/**************************************************************************//** -+ @File net_ioctls.h -+ -+ @Description This file contains common and general netcomm headers definitions. -+*//***************************************************************************/ -+#ifndef __NET_IOCTLS_H -+#define __NET_IOCTLS_H -+ -+#include "ioctls.h" -+ -+ -+typedef uint8_t ioc_header_field_ppp_t; -+ -+#define IOC_NET_HEADER_FIELD_PPP_PID (1) -+#define IOC_NET_HEADER_FIELD_PPP_COMPRESSED (IOC_NET_HEADER_FIELD_PPP_PID << 1) -+#define IOC_NET_HEADER_FIELD_PPP_ALL_FIELDS ((IOC_NET_HEADER_FIELD_PPP_PID << 2) - 1) -+ -+ -+typedef uint8_t ioc_header_field_pppoe_t; -+ -+#define IOC_NET_HEADER_FIELD_PPPoE_VER (1) -+#define IOC_NET_HEADER_FIELD_PPPoE_TYPE (IOC_NET_HEADER_FIELD_PPPoE_VER << 1) -+#define IOC_NET_HEADER_FIELD_PPPoE_CODE (IOC_NET_HEADER_FIELD_PPPoE_VER << 2) -+#define IOC_NET_HEADER_FIELD_PPPoE_SID (IOC_NET_HEADER_FIELD_PPPoE_VER << 3) -+#define IOC_NET_HEADER_FIELD_PPPoE_LEN (IOC_NET_HEADER_FIELD_PPPoE_VER << 4) -+#define IOC_NET_HEADER_FIELD_PPPoE_SESSION (IOC_NET_HEADER_FIELD_PPPoE_VER << 5) -+#define IOC_NET_HEADER_FIELD_PPPoE_PID (IOC_NET_HEADER_FIELD_PPPoE_VER << 6) -+#define IOC_NET_HEADER_FIELD_PPPoE_ALL_FIELDS ((IOC_NET_HEADER_FIELD_PPPoE_VER << 7) - 1) -+ -+#define IOC_NET_HEADER_FIELD_PPPMUX_PID (1) -+#define IOC_NET_HEADER_FIELD_PPPMUX_CKSUM (IOC_NET_HEADER_FIELD_PPPMUX_PID << 1) -+#define IOC_NET_HEADER_FIELD_PPPMUX_COMPRESSED (IOC_NET_HEADER_FIELD_PPPMUX_PID << 2) -+#define IOC_NET_HEADER_FIELD_PPPMUX_ALL_FIELDS ((IOC_NET_HEADER_FIELD_PPPMUX_PID << 3) - 1) -+ -+#define IOC_NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF (1) -+#define IOC_NET_HEADER_FIELD_PPPMUX_SUBFRAME_LXT (IOC_NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 1) -+#define IOC_NET_HEADER_FIELD_PPPMUX_SUBFRAME_LEN (IOC_NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 2) -+#define IOC_NET_HEADER_FIELD_PPPMUX_SUBFRAME_PID (IOC_NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 3) -+#define IOC_NET_HEADER_FIELD_PPPMUX_SUBFRAME_USE_PID (IOC_NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 4) -+#define IOC_NET_HEADER_FIELD_PPPMUX_SUBFRAME_ALL_FIELDS ((IOC_NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 5) - 1) -+ -+ -+typedef uint8_t ioc_header_field_eth_t; -+ -+#define IOC_NET_HEADER_FIELD_ETH_DA (1) -+#define IOC_NET_HEADER_FIELD_ETH_SA (IOC_NET_HEADER_FIELD_ETH_DA << 1) -+#define IOC_NET_HEADER_FIELD_ETH_LENGTH (IOC_NET_HEADER_FIELD_ETH_DA << 2) -+#define IOC_NET_HEADER_FIELD_ETH_TYPE (IOC_NET_HEADER_FIELD_ETH_DA << 3) -+#define IOC_NET_HEADER_FIELD_ETH_FINAL_CKSUM (IOC_NET_HEADER_FIELD_ETH_DA << 4) -+#define IOC_NET_HEADER_FIELD_ETH_PADDING (IOC_NET_HEADER_FIELD_ETH_DA << 5) -+#define IOC_NET_HEADER_FIELD_ETH_ALL_FIELDS ((IOC_NET_HEADER_FIELD_ETH_DA << 6) - 1) -+ -+#define IOC_NET_HEADER_FIELD_ETH_ADDR_SIZE 6 -+ -+typedef uint16_t ioc_header_field_ip_t; -+ -+#define IOC_NET_HEADER_FIELD_IP_VER (1) -+#define IOC_NET_HEADER_FIELD_IP_DSCP (IOC_NET_HEADER_FIELD_IP_VER << 2) -+#define IOC_NET_HEADER_FIELD_IP_ECN (IOC_NET_HEADER_FIELD_IP_VER << 3) -+#define IOC_NET_HEADER_FIELD_IP_PROTO (IOC_NET_HEADER_FIELD_IP_VER << 4) -+ -+#define IOC_NET_HEADER_FIELD_IP_PROTO_SIZE 1 -+ -+typedef uint16_t ioc_header_field_ipv4_t; -+ -+#define IOC_NET_HEADER_FIELD_IPv4_VER (1) -+#define IOC_NET_HEADER_FIELD_IPv4_HDR_LEN (IOC_NET_HEADER_FIELD_IPv4_VER << 1) -+#define IOC_NET_HEADER_FIELD_IPv4_TOS (IOC_NET_HEADER_FIELD_IPv4_VER << 2) -+#define IOC_NET_HEADER_FIELD_IPv4_TOTAL_LEN (IOC_NET_HEADER_FIELD_IPv4_VER << 3) -+#define IOC_NET_HEADER_FIELD_IPv4_ID (IOC_NET_HEADER_FIELD_IPv4_VER << 4) -+#define IOC_NET_HEADER_FIELD_IPv4_FLAG_D (IOC_NET_HEADER_FIELD_IPv4_VER << 5) -+#define IOC_NET_HEADER_FIELD_IPv4_FLAG_M (IOC_NET_HEADER_FIELD_IPv4_VER << 6) -+#define IOC_NET_HEADER_FIELD_IPv4_OFFSET (IOC_NET_HEADER_FIELD_IPv4_VER << 7) -+#define IOC_NET_HEADER_FIELD_IPv4_TTL (IOC_NET_HEADER_FIELD_IPv4_VER << 8) -+#define IOC_NET_HEADER_FIELD_IPv4_PROTO (IOC_NET_HEADER_FIELD_IPv4_VER << 9) -+#define IOC_NET_HEADER_FIELD_IPv4_CKSUM (IOC_NET_HEADER_FIELD_IPv4_VER << 10) -+#define IOC_NET_HEADER_FIELD_IPv4_SRC_IP (IOC_NET_HEADER_FIELD_IPv4_VER << 11) -+#define IOC_NET_HEADER_FIELD_IPv4_DST_IP (IOC_NET_HEADER_FIELD_IPv4_VER << 12) -+#define IOC_NET_HEADER_FIELD_IPv4_OPTS (IOC_NET_HEADER_FIELD_IPv4_VER << 13) -+#define IOC_NET_HEADER_FIELD_IPv4_OPTS_COUNT (IOC_NET_HEADER_FIELD_IPv4_VER << 14) -+#define IOC_NET_HEADER_FIELD_IPv4_ALL_FIELDS ((IOC_NET_HEADER_FIELD_IPv4_VER << 15) - 1) -+ -+#define IOC_NET_HEADER_FIELD_IPv4_ADDR_SIZE 4 -+#define IOC_NET_HEADER_FIELD_IPv4_PROTO_SIZE 1 -+ -+ -+typedef uint8_t ioc_header_field_ipv6_t; -+ -+#define IOC_NET_HEADER_FIELD_IPv6_VER (1) -+#define IOC_NET_HEADER_FIELD_IPv6_TC (IOC_NET_HEADER_FIELD_IPv6_VER << 1) -+#define IOC_NET_HEADER_FIELD_IPv6_SRC_IP (IOC_NET_HEADER_FIELD_IPv6_VER << 2) -+#define IOC_NET_HEADER_FIELD_IPv6_DST_IP (IOC_NET_HEADER_FIELD_IPv6_VER << 3) -+#define IOC_NET_HEADER_FIELD_IPv6_NEXT_HDR (IOC_NET_HEADER_FIELD_IPv6_VER << 4) -+#define IOC_NET_HEADER_FIELD_IPv6_FL (IOC_NET_HEADER_FIELD_IPv6_VER << 5) -+#define IOC_NET_HEADER_FIELD_IPv6_HOP_LIMIT (IOC_NET_HEADER_FIELD_IPv6_VER << 6) -+#define IOC_NET_HEADER_FIELD_IPv6_ALL_FIELDS ((IOC_NET_HEADER_FIELD_IPv6_VER << 7) - 1) -+ -+#define IOC_NET_HEADER_FIELD_IPv6_ADDR_SIZE 16 -+#define IOC_NET_HEADER_FIELD_IPv6_NEXT_HDR_SIZE 1 -+ -+#define IOC_NET_HEADER_FIELD_ICMP_TYPE (1) -+#define IOC_NET_HEADER_FIELD_ICMP_CODE (IOC_NET_HEADER_FIELD_ICMP_TYPE << 1) -+#define IOC_NET_HEADER_FIELD_ICMP_CKSUM (IOC_NET_HEADER_FIELD_ICMP_TYPE << 2) -+#define IOC_NET_HEADER_FIELD_ICMP_ID (IOC_NET_HEADER_FIELD_ICMP_TYPE << 3) -+#define IOC_NET_HEADER_FIELD_ICMP_SQ_NUM (IOC_NET_HEADER_FIELD_ICMP_TYPE << 4) -+#define IOC_NET_HEADER_FIELD_ICMP_ALL_FIELDS ((IOC_NET_HEADER_FIELD_ICMP_TYPE << 5) - 1) -+ -+#define IOC_NET_HEADER_FIELD_ICMP_CODE_SIZE 1 -+#define IOC_NET_HEADER_FIELD_ICMP_TYPE_SIZE 1 -+ -+#define IOC_NET_HEADER_FIELD_IGMP_VERSION (1) -+#define IOC_NET_HEADER_FIELD_IGMP_TYPE (IOC_NET_HEADER_FIELD_IGMP_VERSION << 1) -+#define IOC_NET_HEADER_FIELD_IGMP_CKSUM (IOC_NET_HEADER_FIELD_IGMP_VERSION << 2) -+#define IOC_NET_HEADER_FIELD_IGMP_DATA (IOC_NET_HEADER_FIELD_IGMP_VERSION << 3) -+#define IOC_NET_HEADER_FIELD_IGMP_ALL_FIELDS ((IOC_NET_HEADER_FIELD_IGMP_VERSION << 4) - 1) -+ -+ -+typedef uint16_t ioc_header_field_tcp_t; -+ -+#define IOC_NET_HEADER_FIELD_TCP_PORT_SRC (1) -+#define IOC_NET_HEADER_FIELD_TCP_PORT_DST (IOC_NET_HEADER_FIELD_TCP_PORT_SRC << 1) -+#define IOC_NET_HEADER_FIELD_TCP_SEQ (IOC_NET_HEADER_FIELD_TCP_PORT_SRC << 2) -+#define IOC_NET_HEADER_FIELD_TCP_ACK (IOC_NET_HEADER_FIELD_TCP_PORT_SRC << 3) -+#define IOC_NET_HEADER_FIELD_TCP_OFFSET (IOC_NET_HEADER_FIELD_TCP_PORT_SRC << 4) -+#define IOC_NET_HEADER_FIELD_TCP_FLAGS (IOC_NET_HEADER_FIELD_TCP_PORT_SRC << 5) -+#define IOC_NET_HEADER_FIELD_TCP_WINDOW (IOC_NET_HEADER_FIELD_TCP_PORT_SRC << 6) -+#define IOC_NET_HEADER_FIELD_TCP_CKSUM (IOC_NET_HEADER_FIELD_TCP_PORT_SRC << 7) -+#define IOC_NET_HEADER_FIELD_TCP_URGPTR (IOC_NET_HEADER_FIELD_TCP_PORT_SRC << 8) -+#define IOC_NET_HEADER_FIELD_TCP_OPTS (IOC_NET_HEADER_FIELD_TCP_PORT_SRC << 9) -+#define IOC_NET_HEADER_FIELD_TCP_OPTS_COUNT (IOC_NET_HEADER_FIELD_TCP_PORT_SRC << 10) -+#define IOC_NET_HEADER_FIELD_TCP_ALL_FIELDS ((IOC_NET_HEADER_FIELD_TCP_PORT_SRC << 11) - 1) -+ -+#define IOC_NET_HEADER_FIELD_TCP_PORT_SIZE 2 -+ -+ -+typedef uint8_t ioc_header_field_sctp_t; -+ -+#define IOC_NET_HEADER_FIELD_SCTP_PORT_SRC (1) -+#define IOC_NET_HEADER_FIELD_SCTP_PORT_DST (IOC_NET_HEADER_FIELD_SCTP_PORT_SRC << 1) -+#define IOC_NET_HEADER_FIELD_SCTP_VER_TAG (IOC_NET_HEADER_FIELD_SCTP_PORT_SRC << 2) -+#define IOC_NET_HEADER_FIELD_SCTP_CKSUM (IOC_NET_HEADER_FIELD_SCTP_PORT_SRC << 3) -+#define IOC_NET_HEADER_FIELD_SCTP_ALL_FIELDS ((IOC_NET_HEADER_FIELD_SCTP_PORT_SRC << 4) - 1) -+ -+#define IOC_NET_HEADER_FIELD_SCTP_PORT_SIZE 2 -+ -+typedef uint8_t ioc_header_field_dccp_t; -+ -+#define IOC_NET_HEADER_FIELD_DCCP_PORT_SRC (1) -+#define IOC_NET_HEADER_FIELD_DCCP_PORT_DST (IOC_NET_HEADER_FIELD_DCCP_PORT_SRC << 1) -+#define IOC_NET_HEADER_FIELD_DCCP_ALL_FIELDS ((IOC_NET_HEADER_FIELD_DCCP_PORT_SRC << 2) - 1) -+ -+#define IOC_NET_HEADER_FIELD_DCCP_PORT_SIZE 2 -+ -+ -+typedef uint8_t ioc_header_field_udp_t; -+ -+#define IOC_NET_HEADER_FIELD_UDP_PORT_SRC (1) -+#define IOC_NET_HEADER_FIELD_UDP_PORT_DST (IOC_NET_HEADER_FIELD_UDP_PORT_SRC << 1) -+#define IOC_NET_HEADER_FIELD_UDP_LEN (IOC_NET_HEADER_FIELD_UDP_PORT_SRC << 2) -+#define IOC_NET_HEADER_FIELD_UDP_CKSUM (IOC_NET_HEADER_FIELD_UDP_PORT_SRC << 3) -+#define IOC_NET_HEADER_FIELD_UDP_ALL_FIELDS ((IOC_NET_HEADER_FIELD_UDP_PORT_SRC << 4) - 1) -+ -+#define IOC_NET_HEADER_FIELD_UDP_PORT_SIZE 2 -+ -+typedef uint8_t ioc_header_field_udp_lite_t; -+ -+#define IOC_NET_HEADER_FIELD_UDP_LITE_PORT_SRC (1) -+#define IOC_NET_HEADER_FIELD_UDP_LITE_PORT_DST (IOC_NET_HEADER_FIELD_UDP_LITE_PORT_SRC << 1) -+#define IOC_NET_HEADER_FIELD_UDP_LITE_ALL_FIELDS ((IOC_NET_HEADER_FIELD_UDP_LITE_PORT_SRC << 2) - 1) -+ -+#define IOC_NET_HEADER_FIELD_UDP_LITE_PORT_SIZE 2 -+ -+typedef uint8_t ioc_header_field_udp_encap_esp_t; -+ -+#define IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC (1) -+#define IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_DST (IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 1) -+#define IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_LEN (IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 2) -+#define IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_CKSUM (IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 3) -+#define IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_SPI (IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 4) -+#define IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_SEQUENCE_NUM (IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 5) -+#define IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_ALL_FIELDS ((IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 6) - 1) -+ -+#define IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SIZE 2 -+#define IOC_NET_HEADER_FIELD_UDP_ENCAP_ESP_SPI_SIZE 4 -+ -+#define IOC_NET_HEADER_FIELD_IPHC_CID (1) -+#define IOC_NET_HEADER_FIELD_IPHC_CID_TYPE (IOC_NET_HEADER_FIELD_IPHC_CID << 1) -+#define IOC_NET_HEADER_FIELD_IPHC_HCINDEX (IOC_NET_HEADER_FIELD_IPHC_CID << 2) -+#define IOC_NET_HEADER_FIELD_IPHC_GEN (IOC_NET_HEADER_FIELD_IPHC_CID << 3) -+#define IOC_NET_HEADER_FIELD_IPHC_D_BIT (IOC_NET_HEADER_FIELD_IPHC_CID << 4) -+#define IOC_NET_HEADER_FIELD_IPHC_ALL_FIELDS ((IOC_NET_HEADER_FIELD_IPHC_CID << 5) - 1) -+ -+#define IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE (1) -+#define IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_FLAGS (IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 1) -+#define IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_LENGTH (IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 2) -+#define IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_TSN (IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 3) -+#define IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_STREAM_ID (IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 4) -+#define IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_STREAM_SQN (IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 5) -+#define IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_PAYLOAD_PID (IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 6) -+#define IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_UNORDERED (IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 7) -+#define IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_BEGGINING (IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 8) -+#define IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_END (IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 9) -+#define IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_ALL_FIELDS ((IOC_NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 10) - 1) -+ -+#define IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT (1) -+#define IOC_NET_HEADER_FIELD_L2TPv2_LENGTH_BIT (IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 1) -+#define IOC_NET_HEADER_FIELD_L2TPv2_SEQUENCE_BIT (IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 2) -+#define IOC_NET_HEADER_FIELD_L2TPv2_OFFSET_BIT (IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 3) -+#define IOC_NET_HEADER_FIELD_L2TPv2_PRIORITY_BIT (IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 4) -+#define IOC_NET_HEADER_FIELD_L2TPv2_VERSION (IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 5) -+#define IOC_NET_HEADER_FIELD_L2TPv2_LEN (IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 6) -+#define IOC_NET_HEADER_FIELD_L2TPv2_TUNNEL_ID (IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 7) -+#define IOC_NET_HEADER_FIELD_L2TPv2_SESSION_ID (IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 8) -+#define IOC_NET_HEADER_FIELD_L2TPv2_NS (IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 9) -+#define IOC_NET_HEADER_FIELD_L2TPv2_NR (IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 10) -+#define IOC_NET_HEADER_FIELD_L2TPv2_OFFSET_SIZE (IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 11) -+#define IOC_NET_HEADER_FIELD_L2TPv2_FIRST_BYTE (IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 12) -+#define IOC_NET_HEADER_FIELD_L2TPv2_ALL_FIELDS ((IOC_NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 13) - 1) -+ -+#define IOC_NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT (1) -+#define IOC_NET_HEADER_FIELD_L2TPv3_CTRL_LENGTH_BIT (IOC_NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 1) -+#define IOC_NET_HEADER_FIELD_L2TPv3_CTRL_SEQUENCE_BIT (IOC_NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 2) -+#define IOC_NET_HEADER_FIELD_L2TPv3_CTRL_VERSION (IOC_NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 3) -+#define IOC_NET_HEADER_FIELD_L2TPv3_CTRL_LENGTH (IOC_NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 4) -+#define IOC_NET_HEADER_FIELD_L2TPv3_CTRL_CONTROL (IOC_NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 5) -+#define IOC_NET_HEADER_FIELD_L2TPv3_CTRL_SENT (IOC_NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 6) -+#define IOC_NET_HEADER_FIELD_L2TPv3_CTRL_RECV (IOC_NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 7) -+#define IOC_NET_HEADER_FIELD_L2TPv3_CTRL_FIRST_BYTE (IOC_NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 8) -+#define IOC_NET_HEADER_FIELD_L2TPv3_CTRL_ALL_FIELDS ((IOC_NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 9) - 1) -+ -+#define IOC_NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT (1) -+#define IOC_NET_HEADER_FIELD_L2TPv3_SESS_VERSION (IOC_NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT << 1) -+#define IOC_NET_HEADER_FIELD_L2TPv3_SESS_ID (IOC_NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT << 2) -+#define IOC_NET_HEADER_FIELD_L2TPv3_SESS_COOKIE (IOC_NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT << 3) -+#define IOC_NET_HEADER_FIELD_L2TPv3_SESS_ALL_FIELDS ((IOC_NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT << 4) - 1) -+ -+ -+typedef uint8_t ioc_header_field_vlan_t; -+ -+#define IOC_NET_HEADER_FIELD_VLAN_VPRI (1) -+#define IOC_NET_HEADER_FIELD_VLAN_CFI (IOC_NET_HEADER_FIELD_VLAN_VPRI << 1) -+#define IOC_NET_HEADER_FIELD_VLAN_VID (IOC_NET_HEADER_FIELD_VLAN_VPRI << 2) -+#define IOC_NET_HEADER_FIELD_VLAN_LENGTH (IOC_NET_HEADER_FIELD_VLAN_VPRI << 3) -+#define IOC_NET_HEADER_FIELD_VLAN_TYPE (IOC_NET_HEADER_FIELD_VLAN_VPRI << 4) -+#define IOC_NET_HEADER_FIELD_VLAN_ALL_FIELDS ((IOC_NET_HEADER_FIELD_VLAN_VPRI << 5) - 1) -+ -+#define IOC_NET_HEADER_FIELD_VLAN_TCI (IOC_NET_HEADER_FIELD_VLAN_VPRI | \ -+ IOC_NET_HEADER_FIELD_VLAN_CFI | \ -+ IOC_NET_HEADER_FIELD_VLAN_VID) -+ -+ -+typedef uint8_t ioc_header_field_llc_t; -+ -+#define IOC_NET_HEADER_FIELD_LLC_DSAP (1) -+#define IOC_NET_HEADER_FIELD_LLC_SSAP (IOC_NET_HEADER_FIELD_LLC_DSAP << 1) -+#define IOC_NET_HEADER_FIELD_LLC_CTRL (IOC_NET_HEADER_FIELD_LLC_DSAP << 2) -+#define IOC_NET_HEADER_FIELD_LLC_ALL_FIELDS ((IOC_NET_HEADER_FIELD_LLC_DSAP << 3) - 1) -+ -+#define IOC_NET_HEADER_FIELD_NLPID_NLPID (1) -+#define IOC_NET_HEADER_FIELD_NLPID_ALL_FIELDS ((IOC_NET_HEADER_FIELD_NLPID_NLPID << 1) - 1) -+ -+ -+typedef uint8_t ioc_header_field_snap_t; -+ -+#define IOC_NET_HEADER_FIELD_SNAP_OUI (1) -+#define IOC_NET_HEADER_FIELD_SNAP_PID (IOC_NET_HEADER_FIELD_SNAP_OUI << 1) -+#define IOC_NET_HEADER_FIELD_SNAP_ALL_FIELDS ((IOC_NET_HEADER_FIELD_SNAP_OUI << 2) - 1) -+ -+ -+typedef uint8_t ioc_header_field_llc_snap_t; -+ -+#define IOC_NET_HEADER_FIELD_LLC_SNAP_TYPE (1) -+#define IOC_NET_HEADER_FIELD_LLC_SNAP_ALL_FIELDS ((IOC_NET_HEADER_FIELD_LLC_SNAP_TYPE << 1) - 1) -+ -+#define IOC_NET_HEADER_FIELD_ARP_HTYPE (1) -+#define IOC_NET_HEADER_FIELD_ARP_PTYPE (IOC_NET_HEADER_FIELD_ARP_HTYPE << 1) -+#define IOC_NET_HEADER_FIELD_ARP_HLEN (IOC_NET_HEADER_FIELD_ARP_HTYPE << 2) -+#define IOC_NET_HEADER_FIELD_ARP_PLEN (IOC_NET_HEADER_FIELD_ARP_HTYPE << 3) -+#define IOC_NET_HEADER_FIELD_ARP_OPER (IOC_NET_HEADER_FIELD_ARP_HTYPE << 4) -+#define IOC_NET_HEADER_FIELD_ARP_SHA (IOC_NET_HEADER_FIELD_ARP_HTYPE << 5) -+#define IOC_NET_HEADER_FIELD_ARP_SPA (IOC_NET_HEADER_FIELD_ARP_HTYPE << 6) -+#define IOC_NET_HEADER_FIELD_ARP_THA (IOC_NET_HEADER_FIELD_ARP_HTYPE << 7) -+#define IOC_NET_HEADER_FIELD_ARP_TPA (IOC_NET_HEADER_FIELD_ARP_HTYPE << 8) -+#define IOC_NET_HEADER_FIELD_ARP_ALL_FIELDS ((IOC_NET_HEADER_FIELD_ARP_HTYPE << 9) - 1) -+ -+#define IOC_NET_HEADER_FIELD_RFC2684_LLC (1) -+#define IOC_NET_HEADER_FIELD_RFC2684_NLPID (IOC_NET_HEADER_FIELD_RFC2684_LLC << 1) -+#define IOC_NET_HEADER_FIELD_RFC2684_OUI (IOC_NET_HEADER_FIELD_RFC2684_LLC << 2) -+#define IOC_NET_HEADER_FIELD_RFC2684_PID (IOC_NET_HEADER_FIELD_RFC2684_LLC << 3) -+#define IOC_NET_HEADER_FIELD_RFC2684_VPN_OUI (IOC_NET_HEADER_FIELD_RFC2684_LLC << 4) -+#define IOC_NET_HEADER_FIELD_RFC2684_VPN_IDX (IOC_NET_HEADER_FIELD_RFC2684_LLC << 5) -+#define IOC_NET_HEADER_FIELD_RFC2684_ALL_FIELDS ((IOC_NET_HEADER_FIELD_RFC2684_LLC << 6) - 1) -+ -+#define IOC_NET_HEADER_FIELD_USER_DEFINED_SRCPORT (1) -+#define IOC_NET_HEADER_FIELD_USER_DEFINED_PCDID (IOC_NET_HEADER_FIELD_USER_DEFINED_SRCPORT << 1) -+#define IOC_NET_HEADER_FIELD_USER_DEFINED_ALL_FIELDS ((IOC_NET_HEADER_FIELD_USER_DEFINED_SRCPORT << 2) - 1) -+ -+#define IOC_NET_HEADER_FIELD_PAYLOAD_BUFFER (1) -+#define IOC_NET_HEADER_FIELD_PAYLOAD_SIZE (IOC_NET_HEADER_FIELD_PAYLOAD_BUFFER << 1) -+#define IOC_NET_HEADER_FIELD_MAX_FRM_SIZE (IOC_NET_HEADER_FIELD_PAYLOAD_BUFFER << 2) -+#define IOC_NET_HEADER_FIELD_MIN_FRM_SIZE (IOC_NET_HEADER_FIELD_PAYLOAD_BUFFER << 3) -+#define IOC_NET_HEADER_FIELD_PAYLOAD_TYPE (IOC_NET_HEADER_FIELD_PAYLOAD_BUFFER << 4) -+#define IOC_NET_HEADER_FIELD_FRAME_SIZE (IOC_NET_HEADER_FIELD_PAYLOAD_BUFFER << 5) -+#define IOC_NET_HEADER_FIELD_PAYLOAD_ALL_FIELDS ((IOC_NET_HEADER_FIELD_PAYLOAD_BUFFER << 6) - 1) -+ -+ -+typedef uint8_t ioc_header_field_gre_t; -+ -+#define IOC_NET_HEADER_FIELD_GRE_TYPE (1) -+#define IOC_NET_HEADER_FIELD_GRE_ALL_FIELDS ((IOC_NET_HEADER_FIELD_GRE_TYPE << 1) - 1) -+ -+ -+typedef uint8_t ioc_header_field_minencap_t; -+ -+#define IOC_NET_HEADER_FIELD_MINENCAP_SRC_IP (1) -+#define IOC_NET_HEADER_FIELD_MINENCAP_DST_IP (IOC_NET_HEADER_FIELD_MINENCAP_SRC_IP << 1) -+#define IOC_NET_HEADER_FIELD_MINENCAP_TYPE (IOC_NET_HEADER_FIELD_MINENCAP_SRC_IP << 2) -+#define IOC_NET_HEADER_FIELD_MINENCAP_ALL_FIELDS ((IOC_NET_HEADER_FIELD_MINENCAP_SRC_IP << 3) - 1) -+ -+ -+typedef uint8_t ioc_header_field_ipsec_ah_t; -+ -+#define IOC_NET_HEADER_FIELD_IPSEC_AH_SPI (1) -+#define IOC_NET_HEADER_FIELD_IPSEC_AH_NH (IOC_NET_HEADER_FIELD_IPSEC_AH_SPI << 1) -+#define IOC_NET_HEADER_FIELD_IPSEC_AH_ALL_FIELDS ((IOC_NET_HEADER_FIELD_IPSEC_AH_SPI << 2) - 1) -+ -+ -+typedef uint8_t ioc_header_field_ipsec_esp_t; -+ -+#define IOC_NET_HEADER_FIELD_IPSEC_ESP_SPI (1) -+#define IOC_NET_HEADER_FIELD_IPSEC_ESP_SEQUENCE_NUM (IOC_NET_HEADER_FIELD_IPSEC_ESP_SPI << 1) -+#define IOC_NET_HEADER_FIELD_IPSEC_ESP_ALL_FIELDS ((IOC_NET_HEADER_FIELD_IPSEC_ESP_SPI << 2) - 1) -+ -+#define IOC_NET_HEADER_FIELD_IPSEC_ESP_SPI_SIZE 4 -+ -+ -+typedef uint8_t ioc_header_field_mpls_t; -+ -+#define IOC_NET_HEADER_FIELD_MPLS_LABEL_STACK (1) -+#define IOC_NET_HEADER_FIELD_MPLS_LABEL_STACK_ALL_FIELDS ((IOC_NET_HEADER_FIELD_MPLS_LABEL_STACK << 1) - 1) -+ -+ -+typedef uint8_t ioc_header_field_macsec_t; -+ -+#define IOC_NET_HEADER_FIELD_MACSEC_SECTAG (1) -+#define IOC_NET_HEADER_FIELD_MACSEC_ALL_FIELDS ((IOC_NET_HEADER_FIELD_MACSEC_SECTAG << 1) - 1) -+ -+ -+typedef enum { -+ e_IOC_NET_HEADER_TYPE_NONE = 0, -+ e_IOC_NET_HEADER_TYPE_PAYLOAD, -+ e_IOC_NET_HEADER_TYPE_ETH, -+ e_IOC_NET_HEADER_TYPE_VLAN, -+ e_IOC_NET_HEADER_TYPE_IPv4, -+ e_IOC_NET_HEADER_TYPE_IPv6, -+ e_IOC_NET_HEADER_TYPE_IP, -+ e_IOC_NET_HEADER_TYPE_TCP, -+ e_IOC_NET_HEADER_TYPE_UDP, -+ e_IOC_NET_HEADER_TYPE_UDP_LITE, -+ e_IOC_NET_HEADER_TYPE_IPHC, -+ e_IOC_NET_HEADER_TYPE_SCTP, -+ e_IOC_NET_HEADER_TYPE_SCTP_CHUNK_DATA, -+ e_IOC_NET_HEADER_TYPE_PPPoE, -+ e_IOC_NET_HEADER_TYPE_PPP, -+ e_IOC_NET_HEADER_TYPE_PPPMUX, -+ e_IOC_NET_HEADER_TYPE_PPPMUX_SUBFRAME, -+ e_IOC_NET_HEADER_TYPE_L2TPv2, -+ e_IOC_NET_HEADER_TYPE_L2TPv3_CTRL, -+ e_IOC_NET_HEADER_TYPE_L2TPv3_SESS, -+ e_IOC_NET_HEADER_TYPE_LLC, -+ e_IOC_NET_HEADER_TYPE_LLC_SNAP, -+ e_IOC_NET_HEADER_TYPE_NLPID, -+ e_IOC_NET_HEADER_TYPE_SNAP, -+ e_IOC_NET_HEADER_TYPE_MPLS, -+ e_IOC_NET_HEADER_TYPE_IPSEC_AH, -+ e_IOC_NET_HEADER_TYPE_IPSEC_ESP, -+ e_IOC_NET_HEADER_TYPE_UDP_ENCAP_ESP, /* RFC 3948 */ -+ e_IOC_NET_HEADER_TYPE_MACSEC, -+ e_IOC_NET_HEADER_TYPE_GRE, -+ e_IOC_NET_HEADER_TYPE_MINENCAP, -+ e_IOC_NET_HEADER_TYPE_DCCP, -+ e_IOC_NET_HEADER_TYPE_ICMP, -+ e_IOC_NET_HEADER_TYPE_IGMP, -+ e_IOC_NET_HEADER_TYPE_ARP, -+ e_IOC_NET_HEADER_TYPE_CAPWAP, -+ e_IOC_NET_HEADER_TYPE_CAPWAP_DTLS, -+ e_IOC_NET_HEADER_TYPE_RFC2684, -+ e_IOC_NET_HEADER_TYPE_USER_DEFINED_L2, -+ e_IOC_NET_HEADER_TYPE_USER_DEFINED_L3, -+ e_IOC_NET_HEADER_TYPE_USER_DEFINED_L4, -+ e_IOC_NET_HEADER_TYPE_USER_DEFINED_SHIM1, -+ e_IOC_NET_HEADER_TYPE_USER_DEFINED_SHIM2, -+ e_IOC_NET_MAX_HEADER_TYPE_COUNT -+} ioc_net_header_type; -+ -+ -+#endif /* __NET_IOCTLS_H */ diff --git a/target/linux/layerscape/patches-4.4/7016-dpa-add-dpaa_eth-driver.patch b/target/linux/layerscape/patches-4.4/7016-dpa-add-dpaa_eth-driver.patch deleted file mode 100644 index 1c48adadeb..0000000000 --- a/target/linux/layerscape/patches-4.4/7016-dpa-add-dpaa_eth-driver.patch +++ /dev/null @@ -1,19160 +0,0 @@ -From 2af9b49c7e6bad2dee75960ddf61fd52a4d3748f Mon Sep 17 00:00:00 2001 -From: Zhao Qiang -Date: Wed, 16 Dec 2015 22:00:36 +0200 -Subject: [PATCH 16/70] dpa: add dpaa_eth driver - -Dpaa is Datapatch Acceleration Architecture, this architecture provides -the infrastructure to support simplified sharing of networking -interfaces and accelerators by multiple CPUs. - -Signed-off-by: Madalin Bucur -Signed-off-by: Camelia Groza -Signed-off-by: Alex Porosanu -Signed-off-by: Pan Jiafei -Signed-off-by: Shaohui Xie -Signed-off-by: Zhao Qiang ---- - drivers/net/ethernet/freescale/Kconfig | 2 + - drivers/net/ethernet/freescale/Makefile | 1 + - drivers/net/ethernet/freescale/sdk_dpaa/Kconfig | 187 ++ - drivers/net/ethernet/freescale/sdk_dpaa/Makefile | 59 + - .../net/ethernet/freescale/sdk_dpaa/dpaa_1588.c | 580 ++++++ - .../net/ethernet/freescale/sdk_dpaa/dpaa_1588.h | 138 ++ - .../net/ethernet/freescale/sdk_dpaa/dpaa_debugfs.c | 180 ++ - .../net/ethernet/freescale/sdk_dpaa/dpaa_debugfs.h | 43 + - drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.c | 1183 +++++++++++ - drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.h | 695 +++++++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_base.c | 263 +++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_base.h | 50 + - .../ethernet/freescale/sdk_dpaa/dpaa_eth_ceetm.c | 1719 ++++++++++++++++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_ceetm.h | 230 +++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_common.c | 1787 ++++++++++++++++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_common.h | 227 +++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_generic.c | 1735 ++++++++++++++++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_generic.h | 90 + - .../freescale/sdk_dpaa/dpaa_eth_generic_sysfs.c | 201 ++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_macless.c | 499 +++++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_macsec.c | 2156 ++++++++++++++++++++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_macsec.h | 294 +++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_proxy.c | 381 ++++ - .../net/ethernet/freescale/sdk_dpaa/dpaa_eth_sg.c | 1128 ++++++++++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_shared.c | 914 +++++++++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_sysfs.c | 278 +++ - .../ethernet/freescale/sdk_dpaa/dpaa_eth_trace.h | 144 ++ - .../net/ethernet/freescale/sdk_dpaa/dpaa_ethtool.c | 544 +++++ - .../freescale/sdk_dpaa/dpaa_generic_ethtool.c | 286 +++ - .../freescale/sdk_dpaa/dpaa_macsec_ethtool.c | 250 +++ - drivers/net/ethernet/freescale/sdk_dpaa/dpaa_ptp.c | 287 +++ - drivers/net/ethernet/freescale/sdk_dpaa/mac-api.c | 915 +++++++++ - drivers/net/ethernet/freescale/sdk_dpaa/mac.c | 470 +++++ - drivers/net/ethernet/freescale/sdk_dpaa/mac.h | 134 ++ - .../net/ethernet/freescale/sdk_dpaa/offline_port.c | 848 ++++++++ - .../net/ethernet/freescale/sdk_dpaa/offline_port.h | 59 + - 36 files changed, 18957 insertions(+) - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/Kconfig - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/Makefile - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_1588.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_1588.h - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_debugfs.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_debugfs.h - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.h - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_base.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_base.h - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_ceetm.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_ceetm.h - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_common.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_common.h - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_generic.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_generic.h - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_generic_sysfs.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_macless.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_macsec.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_macsec.h - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_proxy.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_sg.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_shared.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_sysfs.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_trace.h - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_ethtool.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_generic_ethtool.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_macsec_ethtool.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_ptp.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/mac-api.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/mac.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/mac.h - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/offline_port.c - create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/offline_port.h - ---- a/drivers/net/ethernet/freescale/Kconfig -+++ b/drivers/net/ethernet/freescale/Kconfig -@@ -93,4 +93,6 @@ config GIANFAR - on the 8540. - - source "drivers/net/ethernet/freescale/sdk_fman/Kconfig" -+source "drivers/net/ethernet/freescale/sdk_dpaa/Kconfig" -+ - endif # NET_VENDOR_FREESCALE ---- a/drivers/net/ethernet/freescale/Makefile -+++ b/drivers/net/ethernet/freescale/Makefile -@@ -18,3 +18,4 @@ gianfar_driver-objs := gianfar.o \ - obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o - ucc_geth_driver-objs := ucc_geth.o ucc_geth_ethtool.o - obj-$(if $(CONFIG_FSL_SDK_FMAN),y) += sdk_fman/ -+obj-$(if $(CONFIG_FSL_SDK_DPAA_ETH),y) += sdk_dpaa/ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/Kconfig -@@ -0,0 +1,187 @@ -+menuconfig FSL_SDK_DPAA_ETH -+ tristate "DPAA Ethernet" -+ depends on (FSL_SOC || ARM64 || ARM) && FSL_BMAN && FSL_QMAN && FSL_SDK_FMAN -+ select PHYLIB -+ ---help--- -+ Data Path Acceleration Architecture Ethernet driver, -+ supporting the Freescale QorIQ chips. -+ Depends on Freescale Buffer Manager and Queue Manager -+ driver and Frame Manager Driver. -+ -+if FSL_SDK_DPAA_ETH -+ -+config FSL_DPAA_HOOKS -+ bool "DPAA Ethernet driver hooks" -+ -+config FSL_DPAA_MACSEC -+ tristate "DPAA MACSEC" -+ select FSL_DPAA_HOOKS -+ ---help--- -+ Enable MACSEC support in DPAA. -+ -+config FSL_DPAA_CEETM -+ bool "DPAA CEETM QoS" -+ select NET_SCHED -+ default n -+ ---help--- -+ Enable QoS offloading support through the CEETM hardware block. -+ -+config FSL_DPAA_OFFLINE_PORTS -+ bool "Offline Ports support" -+ depends on FSL_SDK_DPAA_ETH -+ default y -+ ---help--- -+ The Offline Parsing / Host Command ports (short: OH ports, of Offline ports) provide -+ most of the functionality of the regular, online ports, except they receive their -+ frames from a core or an accelerator on the SoC, via QMan frame queues, -+ rather than directly from the network. -+ Offline ports are configured via PCD (Parse-Classify-Distribute) schemes, just like -+ any online FMan port. They deliver the processed frames to frame queues, according -+ to the applied PCD configurations. -+ -+ Choosing this feature will not impact the functionality and/or performance of the system, -+ so it is safe to have it. -+ -+config FSL_DPAA_ADVANCED_DRIVERS -+ bool "Advanced DPAA Ethernet drivers" -+ depends on FSL_SDK_DPAA_ETH -+ default y -+ ---help--- -+ Besides the standard DPAA Ethernet driver there are available other flavours -+ of DPAA drivers that support advanced scenarios: -+ - DPAA Shared MAC driver -+ - DPAA MAC-less driver -+ - DPAA Proxy initialization driver (for USDPAA) -+ Select this to also build the advanced drivers. -+ -+config FSL_DPAA_GENERIC_DRIVER -+ bool "Generic DPAA Ethernet driver" -+ depends on FSL_SDK_DPAA_ETH -+ default y -+ ---help--- -+ This enables the DPAA Generic driver (oNIC). -+ -+config FSL_DPAA_ETH_JUMBO_FRAME -+ bool "Optimize for jumbo frames" -+ depends on !ARM64 && !ARM -+ default n -+ ---help--- -+ Optimize the DPAA Ethernet driver throughput for large frames -+ termination traffic (e.g. 4K and above). -+ NOTE: This option can only be used if FSL_FM_MAX_FRAME_SIZE -+ is set to 9600 bytes. -+ Using this option in combination with small frames increases -+ significantly the driver's memory footprint and may even deplete -+ the system memory. -+ This option is not available on LS1043. -+ -+config FSL_DPAA_TS -+ bool "Linux compliant timestamping" -+ depends on FSL_SDK_DPAA_ETH -+ default n -+ ---help--- -+ Enable Linux API compliant timestamping support. -+ -+config FSL_DPAA_1588 -+ bool "IEEE 1588-compliant timestamping" -+ depends on FSL_SDK_DPAA_ETH -+ select FSL_DPAA_TS -+ default n -+ ---help--- -+ Enable IEEE1588 support code. -+ -+config FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE -+ bool "Use driver's Tx queue selection mechanism" -+ default y -+ depends on FSL_SDK_DPAA_ETH -+ ---help--- -+ The DPAA-Ethernet driver defines a ndo_select_queue() callback for optimal selection -+ of the egress FQ. That will override the XPS support for this netdevice. -+ If for whatever reason you want to be in control of the egress FQ-to-CPU selection and mapping, -+ or simply don't want to use the driver's ndo_select_queue() callback, then unselect this -+ and use the standard XPS support instead. -+ -+config FSL_DPAA_ETH_MAX_BUF_COUNT -+ int "Maximum nuber of buffers in private bpool" -+ depends on FSL_SDK_DPAA_ETH -+ range 64 2048 -+ default "128" -+ ---help--- -+ The maximum number of buffers to be by default allocated in the DPAA-Ethernet private port's -+ buffer pool. One needn't normally modify this, as it has probably been tuned for performance -+ already. This cannot be lower than DPAA_ETH_REFILL_THRESHOLD. -+ -+config FSL_DPAA_ETH_REFILL_THRESHOLD -+ int "Private bpool refill threshold" -+ depends on FSL_SDK_DPAA_ETH -+ range 32 FSL_DPAA_ETH_MAX_BUF_COUNT -+ default "80" -+ ---help--- -+ The DPAA-Ethernet driver will start replenishing buffer pools whose count -+ falls below this threshold. This must be related to DPAA_ETH_MAX_BUF_COUNT. One needn't normally -+ modify this value unless one has very specific performance reasons. -+ -+config FSL_DPAA_CS_THRESHOLD_1G -+ hex "Egress congestion threshold on 1G ports" -+ depends on FSL_SDK_DPAA_ETH -+ range 0x1000 0x10000000 -+ default "0x06000000" -+ ---help--- -+ The size in bytes of the egress Congestion State notification threshold on 1G ports. -+ The 1G dTSECs can quite easily be flooded by cores doing Tx in a tight loop -+ (e.g. by sending UDP datagrams at "while(1) speed"), -+ and the larger the frame size, the more acute the problem. -+ So we have to find a balance between these factors: -+ - avoiding the device staying congested for a prolonged time (risking -+ the netdev watchdog to fire - see also the tx_timeout module param); -+ - affecting performance of protocols such as TCP, which otherwise -+ behave well under the congestion notification mechanism; -+ - preventing the Tx cores from tightly-looping (as if the congestion -+ threshold was too low to be effective); -+ - running out of memory if the CS threshold is set too high. -+ -+config FSL_DPAA_CS_THRESHOLD_10G -+ hex "Egress congestion threshold on 10G ports" -+ depends on FSL_SDK_DPAA_ETH -+ range 0x1000 0x20000000 -+ default "0x10000000" -+ -+config FSL_DPAA_INGRESS_CS_THRESHOLD -+ hex "Ingress congestion threshold on FMan ports" -+ depends on FSL_SDK_DPAA_ETH -+ default "0x10000000" -+ ---help--- -+ The size in bytes of the ingress tail-drop threshold on FMan ports. -+ Traffic piling up above this value will be rejected by QMan and discarded by FMan. -+ -+config FSL_DPAA_ETH_DEBUGFS -+ bool "DPAA Ethernet debugfs interface" -+ depends on DEBUG_FS && FSL_SDK_DPAA_ETH -+ default y -+ ---help--- -+ This option compiles debugfs code for the DPAA Ethernet driver. -+ -+config FSL_DPAA_ETH_DEBUG -+ bool "DPAA Ethernet Debug Support" -+ depends on FSL_SDK_DPAA_ETH -+ default n -+ ---help--- -+ This option compiles debug code for the DPAA Ethernet driver. -+ -+config FSL_DPAA_DBG_LOOP -+ bool "DPAA Ethernet Debug loopback" -+ depends on FSL_DPAA_ETH_DEBUGFS && FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE -+ default n -+ ---help--- -+ This option allows to divert all received traffic on a certain interface A towards a -+ selected interface B. This option is used to benchmark the HW + Ethernet driver in -+ isolation from the Linux networking stack. The loops are controlled by debugfs entries, -+ one for each interface. By default all loops are disabled (target value is -1). I.e. to -+ change the loop setting for interface 4 and divert all received traffic to interface 5 -+ write Tx interface number in the receive interface debugfs file: -+ # cat /sys/kernel/debug/powerpc/fsl_dpa/eth4_loop -+ 4->-1 -+ # echo 5 > /sys/kernel/debug/powerpc/fsl_dpa/eth4_loop -+ # cat /sys/kernel/debug/powerpc/fsl_dpa/eth4_loop -+ 4->5 -+endif # FSL_SDK_DPAA_ETH ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/Makefile -@@ -0,0 +1,59 @@ -+# -+# Makefile for the Freescale Ethernet controllers -+# -+ccflags-y += -DVERSION=\"\" -+# -+# Include netcomm SW specific definitions -+include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk -+ -+ccflags-y += -I$(NET_DPA) -+ -+obj-$(CONFIG_FSL_SDK_DPAA_ETH) += fsl_mac.o fsl_dpa.o -+obj-$(CONFIG_PTP_1588_CLOCK_DPAA) += dpaa_ptp.o -+ -+fsl_dpa-objs += dpaa_ethtool.o dpaa_eth_sysfs.o dpaa_eth.o dpaa_eth_sg.o dpaa_eth_common.o -+ifeq ($(CONFIG_FSL_DPAA_DBG_LOOP),y) -+fsl_dpa-objs += dpaa_debugfs.o -+endif -+ifeq ($(CONFIG_FSL_DPAA_1588),y) -+fsl_dpa-objs += dpaa_1588.o -+endif -+ifeq ($(CONFIG_FSL_DPAA_CEETM),y) -+ccflags-y += -Idrivers/net/ethernet/freescale/sdk_fman/src/wrapper -+fsl_dpa-objs += dpaa_eth_ceetm.o -+endif -+ -+fsl_mac-objs += mac.o mac-api.o -+ -+# Advanced drivers -+ifeq ($(CONFIG_FSL_DPAA_ADVANCED_DRIVERS),y) -+obj-$(CONFIG_FSL_SDK_DPAA_ETH) += fsl_advanced.o -+obj-$(CONFIG_FSL_SDK_DPAA_ETH) += fsl_proxy.o -+obj-$(CONFIG_FSL_SDK_DPAA_ETH) += fsl_dpa_shared.o -+obj-$(CONFIG_FSL_SDK_DPAA_ETH) += fsl_dpa_macless.o -+obj-$(CONFIG_FSL_DPAA_MACSEC) += fsl_dpa_macsec.o -+ -+fsl_advanced-objs += dpaa_eth_base.o -+# suport for multiple drivers per kernel module comes in kernel 3.14 -+# so we are forced to generate several modules for the advanced drivers -+fsl_proxy-objs += dpaa_eth_proxy.o -+fsl_dpa_shared-objs += dpaa_eth_shared.o -+fsl_dpa_macless-objs += dpaa_eth_macless.o -+fsl_dpa_macsec-objs += dpaa_eth_macsec.o dpaa_macsec_ethtool.o -+ -+ifeq ($(CONFIG_FSL_DPAA_OFFLINE_PORTS),y) -+obj-$(CONFIG_FSL_SDK_DPAA_ETH) += fsl_oh.o -+ -+fsl_oh-objs += offline_port.o -+endif -+endif -+ -+# Generic driver -+ifeq ($(CONFIG_FSL_DPAA_GENERIC_DRIVER),y) -+obj-$(CONFIG_FSL_SDK_DPAA_ETH) += fsl_generic.o -+ -+fsl_generic-objs += dpaa_eth_generic.o dpaa_eth_generic_sysfs.o dpaa_generic_ethtool.o -+endif -+ -+# Needed by the tracing framework -+CFLAGS_dpaa_eth.o := -I$(src) ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_1588.c -@@ -0,0 +1,580 @@ -+/* Copyright (C) 2011 Freescale Semiconductor, Inc. -+ * Copyright (C) 2009 IXXAT Automation, GmbH -+ * -+ * DPAA Ethernet Driver -- IEEE 1588 interface functionality -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "dpaa_eth.h" -+#include "dpaa_eth_common.h" -+#include "dpaa_1588.h" -+#include "mac.h" -+ -+static int dpa_ptp_init_circ(struct dpa_ptp_circ_buf *ptp_buf, u32 size) -+{ -+ struct circ_buf *circ_buf = &ptp_buf->circ_buf; -+ -+ circ_buf->buf = vmalloc(sizeof(struct dpa_ptp_data) * size); -+ if (!circ_buf->buf) -+ return 1; -+ -+ circ_buf->head = 0; -+ circ_buf->tail = 0; -+ ptp_buf->size = size; -+ spin_lock_init(&ptp_buf->ptp_lock); -+ -+ return 0; -+} -+ -+static void dpa_ptp_reset_circ(struct dpa_ptp_circ_buf *ptp_buf, u32 size) -+{ -+ struct circ_buf *circ_buf = &ptp_buf->circ_buf; -+ -+ circ_buf->head = 0; -+ circ_buf->tail = 0; -+ ptp_buf->size = size; -+} -+ -+static int dpa_ptp_insert(struct dpa_ptp_circ_buf *ptp_buf, -+ struct dpa_ptp_data *data) -+{ -+ struct circ_buf *circ_buf = &ptp_buf->circ_buf; -+ int size = ptp_buf->size; -+ struct dpa_ptp_data *tmp; -+ unsigned long flags; -+ int head, tail; -+ -+ spin_lock_irqsave(&ptp_buf->ptp_lock, flags); -+ -+ head = circ_buf->head; -+ tail = circ_buf->tail; -+ -+ if (CIRC_SPACE(head, tail, size) <= 0) -+ circ_buf->tail = (tail + 1) & (size - 1); -+ -+ tmp = (struct dpa_ptp_data *)(circ_buf->buf) + head; -+ memcpy(tmp, data, sizeof(struct dpa_ptp_data)); -+ -+ circ_buf->head = (head + 1) & (size - 1); -+ -+ spin_unlock_irqrestore(&ptp_buf->ptp_lock, flags); -+ -+ return 0; -+} -+ -+static int dpa_ptp_is_ident_match(struct dpa_ptp_ident *dst, -+ struct dpa_ptp_ident *src) -+{ -+ int ret; -+ -+ if ((dst->version != src->version) || (dst->msg_type != src->msg_type)) -+ return 0; -+ -+ if ((dst->netw_prot == src->netw_prot) -+ || src->netw_prot == DPA_PTP_PROT_DONTCARE) { -+ if (dst->seq_id != src->seq_id) -+ return 0; -+ -+ ret = memcmp(dst->snd_port_id, src->snd_port_id, -+ DPA_PTP_SOURCE_PORT_LENGTH); -+ if (ret) -+ return 0; -+ else -+ return 1; -+ } -+ -+ return 0; -+} -+ -+static int dpa_ptp_find_and_remove(struct dpa_ptp_circ_buf *ptp_buf, -+ struct dpa_ptp_ident *ident, -+ struct dpa_ptp_time *ts) -+{ -+ struct circ_buf *circ_buf = &ptp_buf->circ_buf; -+ int size = ptp_buf->size; -+ int head, tail, idx; -+ unsigned long flags; -+ struct dpa_ptp_data *tmp, *tmp2; -+ struct dpa_ptp_ident *tmp_ident; -+ -+ spin_lock_irqsave(&ptp_buf->ptp_lock, flags); -+ -+ head = circ_buf->head; -+ tail = idx = circ_buf->tail; -+ -+ if (CIRC_CNT(head, tail, size) == 0) { -+ spin_unlock_irqrestore(&ptp_buf->ptp_lock, flags); -+ return 1; -+ } -+ -+ while (idx != head) { -+ tmp = (struct dpa_ptp_data *)(circ_buf->buf) + idx; -+ tmp_ident = &tmp->ident; -+ if (dpa_ptp_is_ident_match(tmp_ident, ident)) -+ break; -+ idx = (idx + 1) & (size - 1); -+ } -+ -+ if (idx == head) { -+ spin_unlock_irqrestore(&ptp_buf->ptp_lock, flags); -+ return 1; -+ } -+ -+ ts->sec = tmp->ts.sec; -+ ts->nsec = tmp->ts.nsec; -+ -+ if (idx != tail) { -+ if (CIRC_CNT(idx, tail, size) > TS_ACCUMULATION_THRESHOLD) { -+ tail = circ_buf->tail = -+ (idx - TS_ACCUMULATION_THRESHOLD) & (size - 1); -+ } -+ -+ while (CIRC_CNT(idx, tail, size) > 0) { -+ tmp = (struct dpa_ptp_data *)(circ_buf->buf) + idx; -+ idx = (idx - 1) & (size - 1); -+ tmp2 = (struct dpa_ptp_data *)(circ_buf->buf) + idx; -+ *tmp = *tmp2; -+ } -+ } -+ circ_buf->tail = (tail + 1) & (size - 1); -+ -+ spin_unlock_irqrestore(&ptp_buf->ptp_lock, flags); -+ -+ return 0; -+} -+ -+/* Parse the PTP packets -+ * -+ * The PTP header can be found in an IPv4 packet, IPv6 patcket or in -+ * an IEEE802.3 ethernet frame. This function returns the position of -+ * the PTP packet or NULL if no PTP found -+ */ -+static u8 *dpa_ptp_parse_packet(struct sk_buff *skb, u16 *eth_type) -+{ -+ u8 *pos = skb->data + ETH_ALEN + ETH_ALEN; -+ u8 *ptp_loc = NULL; -+ u8 msg_type; -+ u32 access_len = ETH_ALEN + ETH_ALEN + DPA_ETYPE_LEN; -+ struct iphdr *iph; -+ struct udphdr *udph; -+ struct ipv6hdr *ipv6h; -+ -+ /* when we can receive S/G frames we need to check the data we want to -+ * access is in the linear skb buffer -+ */ -+ if (!pskb_may_pull(skb, access_len)) -+ return NULL; -+ -+ *eth_type = *((u16 *)pos); -+ -+ /* Check if inner tag is here */ -+ if (*eth_type == ETH_P_8021Q) { -+ access_len += DPA_VLAN_TAG_LEN; -+ -+ if (!pskb_may_pull(skb, access_len)) -+ return NULL; -+ -+ pos += DPA_VLAN_TAG_LEN; -+ *eth_type = *((u16 *)pos); -+ } -+ -+ pos += DPA_ETYPE_LEN; -+ -+ switch (*eth_type) { -+ /* Transport of PTP over Ethernet */ -+ case ETH_P_1588: -+ ptp_loc = pos; -+ -+ if (!pskb_may_pull(skb, access_len + PTP_OFFS_MSG_TYPE + 1)) -+ return NULL; -+ -+ msg_type = *((u8 *)(ptp_loc + PTP_OFFS_MSG_TYPE)) & 0xf; -+ if ((msg_type == PTP_MSGTYPE_SYNC) -+ || (msg_type == PTP_MSGTYPE_DELREQ) -+ || (msg_type == PTP_MSGTYPE_PDELREQ) -+ || (msg_type == PTP_MSGTYPE_PDELRESP)) -+ return ptp_loc; -+ break; -+ /* Transport of PTP over IPv4 */ -+ case ETH_P_IP: -+ iph = (struct iphdr *)pos; -+ access_len += sizeof(struct iphdr); -+ -+ if (!pskb_may_pull(skb, access_len)) -+ return NULL; -+ -+ if (ntohs(iph->protocol) != IPPROTO_UDP) -+ return NULL; -+ -+ access_len += iph->ihl * 4 - sizeof(struct iphdr) + -+ sizeof(struct udphdr); -+ -+ if (!pskb_may_pull(skb, access_len)) -+ return NULL; -+ -+ pos += iph->ihl * 4; -+ udph = (struct udphdr *)pos; -+ if (ntohs(udph->dest) != 319) -+ return NULL; -+ ptp_loc = pos + sizeof(struct udphdr); -+ break; -+ /* Transport of PTP over IPv6 */ -+ case ETH_P_IPV6: -+ ipv6h = (struct ipv6hdr *)pos; -+ -+ access_len += sizeof(struct ipv6hdr) + sizeof(struct udphdr); -+ -+ if (ntohs(ipv6h->nexthdr) != IPPROTO_UDP) -+ return NULL; -+ -+ pos += sizeof(struct ipv6hdr); -+ udph = (struct udphdr *)pos; -+ if (ntohs(udph->dest) != 319) -+ return NULL; -+ ptp_loc = pos + sizeof(struct udphdr); -+ break; -+ default: -+ break; -+ } -+ -+ return ptp_loc; -+} -+ -+static int dpa_ptp_store_stamp(const struct dpa_priv_s *priv, -+ struct sk_buff *skb, void *data, enum port_type rx_tx, -+ struct dpa_ptp_data *ptp_data) -+{ -+ u64 nsec; -+ u32 mod; -+ u8 *ptp_loc; -+ u16 eth_type; -+ -+ ptp_loc = dpa_ptp_parse_packet(skb, ð_type); -+ if (!ptp_loc) -+ return -EINVAL; -+ -+ switch (eth_type) { -+ case ETH_P_IP: -+ ptp_data->ident.netw_prot = DPA_PTP_PROT_IPV4; -+ break; -+ case ETH_P_IPV6: -+ ptp_data->ident.netw_prot = DPA_PTP_PROT_IPV6; -+ break; -+ case ETH_P_1588: -+ ptp_data->ident.netw_prot = DPA_PTP_PROT_802_3; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (!pskb_may_pull(skb, ptp_loc - skb->data + PTP_OFFS_SEQ_ID + 2)) -+ return -EINVAL; -+ -+ ptp_data->ident.version = *(ptp_loc + PTP_OFFS_VER_PTP) & 0xf; -+ ptp_data->ident.msg_type = *(ptp_loc + PTP_OFFS_MSG_TYPE) & 0xf; -+ ptp_data->ident.seq_id = *((u16 *)(ptp_loc + PTP_OFFS_SEQ_ID)); -+ memcpy(ptp_data->ident.snd_port_id, ptp_loc + PTP_OFFS_SRCPRTID, -+ DPA_PTP_SOURCE_PORT_LENGTH); -+ -+ nsec = dpa_get_timestamp_ns(priv, rx_tx, data); -+ mod = do_div(nsec, NANOSEC_PER_SECOND); -+ ptp_data->ts.sec = nsec; -+ ptp_data->ts.nsec = mod; -+ -+ return 0; -+} -+ -+void dpa_ptp_store_txstamp(const struct dpa_priv_s *priv, -+ struct sk_buff *skb, void *data) -+{ -+ struct dpa_ptp_tsu *tsu = priv->tsu; -+ struct dpa_ptp_data ptp_tx_data; -+ -+ if (dpa_ptp_store_stamp(priv, skb, data, TX, &ptp_tx_data)) -+ return; -+ -+ dpa_ptp_insert(&tsu->tx_timestamps, &ptp_tx_data); -+} -+ -+void dpa_ptp_store_rxstamp(const struct dpa_priv_s *priv, -+ struct sk_buff *skb, void *data) -+{ -+ struct dpa_ptp_tsu *tsu = priv->tsu; -+ struct dpa_ptp_data ptp_rx_data; -+ -+ if (dpa_ptp_store_stamp(priv, skb, data, RX, &ptp_rx_data)) -+ return; -+ -+ dpa_ptp_insert(&tsu->rx_timestamps, &ptp_rx_data); -+} -+ -+static uint8_t dpa_get_tx_timestamp(struct dpa_ptp_tsu *ptp_tsu, -+ struct dpa_ptp_ident *ident, -+ struct dpa_ptp_time *ts) -+{ -+ struct dpa_ptp_tsu *tsu = ptp_tsu; -+ struct dpa_ptp_time tmp; -+ int flag; -+ -+ flag = dpa_ptp_find_and_remove(&tsu->tx_timestamps, ident, &tmp); -+ if (!flag) { -+ ts->sec = tmp.sec; -+ ts->nsec = tmp.nsec; -+ return 0; -+ } -+ -+ return -1; -+} -+ -+static uint8_t dpa_get_rx_timestamp(struct dpa_ptp_tsu *ptp_tsu, -+ struct dpa_ptp_ident *ident, -+ struct dpa_ptp_time *ts) -+{ -+ struct dpa_ptp_tsu *tsu = ptp_tsu; -+ struct dpa_ptp_time tmp; -+ int flag; -+ -+ flag = dpa_ptp_find_and_remove(&tsu->rx_timestamps, ident, &tmp); -+ if (!flag) { -+ ts->sec = tmp.sec; -+ ts->nsec = tmp.nsec; -+ return 0; -+ } -+ -+ return -1; -+} -+ -+static void dpa_set_fiper_alarm(struct dpa_ptp_tsu *tsu, -+ struct dpa_ptp_time *cnt_time) -+{ -+ struct mac_device *mac_dev = tsu->dpa_priv->mac_dev; -+ u64 tmp, fiper; -+ -+ if (mac_dev->fm_rtc_disable) -+ mac_dev->fm_rtc_disable(get_fm_handle(tsu->dpa_priv->net_dev)); -+ -+ /* TMR_FIPER1 will pulse every second after ALARM1 expired */ -+ tmp = (u64)cnt_time->sec * NANOSEC_PER_SECOND + (u64)cnt_time->nsec; -+ fiper = NANOSEC_PER_SECOND - DPA_PTP_NOMINAL_FREQ_PERIOD_NS; -+ if (mac_dev->fm_rtc_set_alarm) -+ mac_dev->fm_rtc_set_alarm(get_fm_handle(tsu->dpa_priv->net_dev), -+ 0, tmp); -+ if (mac_dev->fm_rtc_set_fiper) -+ mac_dev->fm_rtc_set_fiper(get_fm_handle(tsu->dpa_priv->net_dev), -+ 0, fiper); -+ -+ if (mac_dev->fm_rtc_enable) -+ mac_dev->fm_rtc_enable(get_fm_handle(tsu->dpa_priv->net_dev)); -+} -+ -+static void dpa_get_curr_cnt(struct dpa_ptp_tsu *tsu, -+ struct dpa_ptp_time *curr_time) -+{ -+ struct mac_device *mac_dev = tsu->dpa_priv->mac_dev; -+ u64 tmp; -+ u32 mod; -+ -+ if (mac_dev->fm_rtc_get_cnt) -+ mac_dev->fm_rtc_get_cnt(get_fm_handle(tsu->dpa_priv->net_dev), -+ &tmp); -+ -+ mod = do_div(tmp, NANOSEC_PER_SECOND); -+ curr_time->sec = (u32)tmp; -+ curr_time->nsec = mod; -+} -+ -+static void dpa_set_1588cnt(struct dpa_ptp_tsu *tsu, -+ struct dpa_ptp_time *cnt_time) -+{ -+ struct mac_device *mac_dev = tsu->dpa_priv->mac_dev; -+ u64 tmp; -+ -+ tmp = (u64)cnt_time->sec * NANOSEC_PER_SECOND + (u64)cnt_time->nsec; -+ -+ if (mac_dev->fm_rtc_set_cnt) -+ mac_dev->fm_rtc_set_cnt(get_fm_handle(tsu->dpa_priv->net_dev), -+ tmp); -+ -+ /* Restart fiper two seconds later */ -+ cnt_time->sec += 2; -+ cnt_time->nsec = 0; -+ dpa_set_fiper_alarm(tsu, cnt_time); -+} -+ -+static void dpa_get_drift(struct dpa_ptp_tsu *tsu, u32 *addend) -+{ -+ struct mac_device *mac_dev = tsu->dpa_priv->mac_dev; -+ u32 drift; -+ -+ if (mac_dev->fm_rtc_get_drift) -+ mac_dev->fm_rtc_get_drift(get_fm_handle(tsu->dpa_priv->net_dev), -+ &drift); -+ -+ *addend = drift; -+} -+ -+static void dpa_set_drift(struct dpa_ptp_tsu *tsu, u32 addend) -+{ -+ struct mac_device *mac_dev = tsu->dpa_priv->mac_dev; -+ -+ if (mac_dev->fm_rtc_set_drift) -+ mac_dev->fm_rtc_set_drift(get_fm_handle(tsu->dpa_priv->net_dev), -+ addend); -+} -+ -+static void dpa_flush_timestamp(struct dpa_ptp_tsu *tsu) -+{ -+ dpa_ptp_reset_circ(&tsu->rx_timestamps, DEFAULT_PTP_RX_BUF_SZ); -+ dpa_ptp_reset_circ(&tsu->tx_timestamps, DEFAULT_PTP_TX_BUF_SZ); -+} -+ -+int dpa_ioctl_1588(struct net_device *dev, struct ifreq *ifr, int cmd) -+{ -+ struct dpa_priv_s *priv = netdev_priv(dev); -+ struct dpa_ptp_tsu *tsu = priv->tsu; -+ struct mac_device *mac_dev = priv->mac_dev; -+ struct dpa_ptp_data ptp_data; -+ struct dpa_ptp_data *ptp_data_user; -+ struct dpa_ptp_time act_time; -+ u32 addend; -+ int retval = 0; -+ -+ if (!tsu || !tsu->valid) -+ return -ENODEV; -+ -+ switch (cmd) { -+ case PTP_ENBL_TXTS_IOCTL: -+ tsu->hwts_tx_en_ioctl = 1; -+ if (mac_dev->fm_rtc_enable) -+ mac_dev->fm_rtc_enable(get_fm_handle(dev)); -+ if (mac_dev->ptp_enable) -+ mac_dev->ptp_enable(mac_dev->get_mac_handle(mac_dev)); -+ break; -+ case PTP_DSBL_TXTS_IOCTL: -+ tsu->hwts_tx_en_ioctl = 0; -+ if (mac_dev->fm_rtc_disable) -+ mac_dev->fm_rtc_disable(get_fm_handle(dev)); -+ if (mac_dev->ptp_disable) -+ mac_dev->ptp_disable(mac_dev->get_mac_handle(mac_dev)); -+ break; -+ case PTP_ENBL_RXTS_IOCTL: -+ tsu->hwts_rx_en_ioctl = 1; -+ break; -+ case PTP_DSBL_RXTS_IOCTL: -+ tsu->hwts_rx_en_ioctl = 0; -+ break; -+ case PTP_GET_RX_TIMESTAMP: -+ ptp_data_user = (struct dpa_ptp_data *)ifr->ifr_data; -+ if (copy_from_user(&ptp_data.ident, -+ &ptp_data_user->ident, sizeof(ptp_data.ident))) -+ return -EINVAL; -+ -+ if (dpa_get_rx_timestamp(tsu, &ptp_data.ident, &ptp_data.ts)) -+ return -EAGAIN; -+ -+ if (copy_to_user((void __user *)&ptp_data_user->ts, -+ &ptp_data.ts, sizeof(ptp_data.ts))) -+ return -EFAULT; -+ break; -+ case PTP_GET_TX_TIMESTAMP: -+ ptp_data_user = (struct dpa_ptp_data *)ifr->ifr_data; -+ if (copy_from_user(&ptp_data.ident, -+ &ptp_data_user->ident, sizeof(ptp_data.ident))) -+ return -EINVAL; -+ -+ if (dpa_get_tx_timestamp(tsu, &ptp_data.ident, &ptp_data.ts)) -+ return -EAGAIN; -+ -+ if (copy_to_user((void __user *)&ptp_data_user->ts, -+ &ptp_data.ts, sizeof(ptp_data.ts))) -+ return -EFAULT; -+ break; -+ case PTP_GET_TIME: -+ dpa_get_curr_cnt(tsu, &act_time); -+ if (copy_to_user(ifr->ifr_data, &act_time, sizeof(act_time))) -+ return -EFAULT; -+ break; -+ case PTP_SET_TIME: -+ if (copy_from_user(&act_time, ifr->ifr_data, sizeof(act_time))) -+ return -EINVAL; -+ dpa_set_1588cnt(tsu, &act_time); -+ break; -+ case PTP_GET_ADJ: -+ dpa_get_drift(tsu, &addend); -+ if (copy_to_user(ifr->ifr_data, &addend, sizeof(addend))) -+ return -EFAULT; -+ break; -+ case PTP_SET_ADJ: -+ if (copy_from_user(&addend, ifr->ifr_data, sizeof(addend))) -+ return -EINVAL; -+ dpa_set_drift(tsu, addend); -+ break; -+ case PTP_SET_FIPER_ALARM: -+ if (copy_from_user(&act_time, ifr->ifr_data, sizeof(act_time))) -+ return -EINVAL; -+ dpa_set_fiper_alarm(tsu, &act_time); -+ break; -+ case PTP_CLEANUP_TS: -+ dpa_flush_timestamp(tsu); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return retval; -+} -+ -+int dpa_ptp_init(struct dpa_priv_s *priv) -+{ -+ struct dpa_ptp_tsu *tsu; -+ -+ /* Allocate memory for PTP structure */ -+ tsu = kzalloc(sizeof(struct dpa_ptp_tsu), GFP_KERNEL); -+ if (!tsu) -+ return -ENOMEM; -+ -+ tsu->valid = TRUE; -+ tsu->dpa_priv = priv; -+ -+ dpa_ptp_init_circ(&tsu->rx_timestamps, DEFAULT_PTP_RX_BUF_SZ); -+ dpa_ptp_init_circ(&tsu->tx_timestamps, DEFAULT_PTP_TX_BUF_SZ); -+ -+ priv->tsu = tsu; -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpa_ptp_init); -+ -+void dpa_ptp_cleanup(struct dpa_priv_s *priv) -+{ -+ struct dpa_ptp_tsu *tsu = priv->tsu; -+ -+ tsu->valid = FALSE; -+ vfree(tsu->rx_timestamps.circ_buf.buf); -+ vfree(tsu->tx_timestamps.circ_buf.buf); -+ -+ kfree(tsu); -+} -+EXPORT_SYMBOL(dpa_ptp_cleanup); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_1588.h -@@ -0,0 +1,138 @@ -+/* Copyright (C) 2011 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ */ -+#ifndef __DPAA_1588_H__ -+#define __DPAA_1588_H__ -+ -+#include -+#include -+#include -+#include -+ -+#define DEFAULT_PTP_RX_BUF_SZ 256 -+#define DEFAULT_PTP_TX_BUF_SZ 256 -+ -+/* 1588 private ioctl calls */ -+#define PTP_ENBL_TXTS_IOCTL SIOCDEVPRIVATE -+#define PTP_DSBL_TXTS_IOCTL (SIOCDEVPRIVATE + 1) -+#define PTP_ENBL_RXTS_IOCTL (SIOCDEVPRIVATE + 2) -+#define PTP_DSBL_RXTS_IOCTL (SIOCDEVPRIVATE + 3) -+#define PTP_GET_TX_TIMESTAMP (SIOCDEVPRIVATE + 4) -+#define PTP_GET_RX_TIMESTAMP (SIOCDEVPRIVATE + 5) -+#define PTP_SET_TIME (SIOCDEVPRIVATE + 6) -+#define PTP_GET_TIME (SIOCDEVPRIVATE + 7) -+#define PTP_SET_FIPER_ALARM (SIOCDEVPRIVATE + 8) -+#define PTP_SET_ADJ (SIOCDEVPRIVATE + 9) -+#define PTP_GET_ADJ (SIOCDEVPRIVATE + 10) -+#define PTP_CLEANUP_TS (SIOCDEVPRIVATE + 11) -+ -+/* PTP V2 message type */ -+enum { -+ PTP_MSGTYPE_SYNC = 0x0, -+ PTP_MSGTYPE_DELREQ = 0x1, -+ PTP_MSGTYPE_PDELREQ = 0x2, -+ PTP_MSGTYPE_PDELRESP = 0x3, -+ PTP_MSGTYPE_FLWUP = 0x8, -+ PTP_MSGTYPE_DELRESP = 0x9, -+ PTP_MSGTYPE_PDELRES_FLWUP = 0xA, -+ PTP_MSGTYPE_ANNOUNCE = 0xB, -+ PTP_MSGTYPE_SGNLNG = 0xC, -+ PTP_MSGTYPE_MNGMNT = 0xD, -+}; -+ -+/* Byte offset of data in the PTP V2 headers */ -+#define PTP_OFFS_MSG_TYPE 0 -+#define PTP_OFFS_VER_PTP 1 -+#define PTP_OFFS_MSG_LEN 2 -+#define PTP_OFFS_DOM_NMB 4 -+#define PTP_OFFS_FLAGS 6 -+#define PTP_OFFS_CORFIELD 8 -+#define PTP_OFFS_SRCPRTID 20 -+#define PTP_OFFS_SEQ_ID 30 -+#define PTP_OFFS_CTRL 32 -+#define PTP_OFFS_LOGMEAN 33 -+ -+#define PTP_IP_OFFS 14 -+#define PTP_UDP_OFFS 34 -+#define PTP_HEADER_OFFS 42 -+#define PTP_MSG_TYPE_OFFS (PTP_HEADER_OFFS + PTP_OFFS_MSG_TYPE) -+#define PTP_SPORT_ID_OFFS (PTP_HEADER_OFFS + PTP_OFFS_SRCPRTID) -+#define PTP_SEQ_ID_OFFS (PTP_HEADER_OFFS + PTP_OFFS_SEQ_ID) -+#define PTP_CTRL_OFFS (PTP_HEADER_OFFS + PTP_OFFS_CTRL) -+ -+/* 1588-2008 network protocol enumeration values */ -+#define DPA_PTP_PROT_IPV4 1 -+#define DPA_PTP_PROT_IPV6 2 -+#define DPA_PTP_PROT_802_3 3 -+#define DPA_PTP_PROT_DONTCARE 0xFFFF -+ -+#define DPA_PTP_SOURCE_PORT_LENGTH 10 -+#define DPA_PTP_HEADER_SZE 34 -+#define DPA_ETYPE_LEN 2 -+#define DPA_VLAN_TAG_LEN 4 -+#define NANOSEC_PER_SECOND 1000000000 -+ -+/* The threshold between the current found one and the oldest one */ -+#define TS_ACCUMULATION_THRESHOLD 50 -+ -+/* Struct needed to identify a timestamp */ -+struct dpa_ptp_ident { -+ u8 version; -+ u8 msg_type; -+ u16 netw_prot; -+ u16 seq_id; -+ u8 snd_port_id[DPA_PTP_SOURCE_PORT_LENGTH]; -+}; -+ -+/* Timestamp format in 1588-2008 */ -+struct dpa_ptp_time { -+ u64 sec; /* just 48 bit used */ -+ u32 nsec; -+}; -+ -+/* needed for timestamp data over ioctl */ -+struct dpa_ptp_data { -+ struct dpa_ptp_ident ident; -+ struct dpa_ptp_time ts; -+}; -+ -+struct dpa_ptp_circ_buf { -+ struct circ_buf circ_buf; -+ u32 size; -+ spinlock_t ptp_lock; -+}; -+ -+/* PTP TSU control structure */ -+struct dpa_ptp_tsu { -+ struct dpa_priv_s *dpa_priv; -+ bool valid; -+ struct dpa_ptp_circ_buf rx_timestamps; -+ struct dpa_ptp_circ_buf tx_timestamps; -+ -+ /* HW timestamping over ioctl enabled flag */ -+ int hwts_tx_en_ioctl; -+ int hwts_rx_en_ioctl; -+}; -+ -+extern int dpa_ptp_init(struct dpa_priv_s *priv); -+extern void dpa_ptp_cleanup(struct dpa_priv_s *priv); -+extern void dpa_ptp_store_txstamp(const struct dpa_priv_s *priv, -+ struct sk_buff *skb, void *data); -+extern void dpa_ptp_store_rxstamp(const struct dpa_priv_s *priv, -+ struct sk_buff *skb, void *data); -+extern int dpa_ioctl_1588(struct net_device *dev, struct ifreq *ifr, int cmd); -+#endif ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_debugfs.c -@@ -0,0 +1,180 @@ -+/* Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include /* struct qm_mcr_querycgr */ -+#include -+#include "dpaa_debugfs.h" -+#include "dpaa_eth.h" /* struct dpa_priv_s, dpa_percpu_priv_s, dpa_bp */ -+ -+#define DPA_DEBUGFS_DESCRIPTION "FSL DPAA Ethernet debugfs entries" -+#define DPA_ETH_DEBUGFS_ROOT "fsl_dpa" -+ -+static struct dentry *dpa_debugfs_root; -+ -+static int __cold dpa_debugfs_loop_open(struct inode *inode, struct file *file); -+static ssize_t dpa_loop_write(struct file *f, -+ const char __user *buf, size_t count, loff_t *off); -+ -+static const struct file_operations dpa_debugfs_lp_fops = { -+ .open = dpa_debugfs_loop_open, -+ .write = dpa_loop_write, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static int dpa_debugfs_loop_show(struct seq_file *file, void *offset) -+{ -+ struct dpa_priv_s *priv; -+ -+ BUG_ON(offset == NULL); -+ -+ priv = netdev_priv((struct net_device *)file->private); -+ seq_printf(file, "%d->%d\n", priv->loop_id, priv->loop_to); -+ -+ return 0; -+} -+ -+static int user_input_convert(const char __user *user_buf, size_t count, -+ long *val) -+{ -+ char buf[12]; -+ -+ if (count > sizeof(buf) - 1) -+ return -EINVAL; -+ if (copy_from_user(buf, user_buf, count)) -+ return -EFAULT; -+ buf[count] = '\0'; -+ if (kstrtol(buf, 0, val)) -+ return -EINVAL; -+ return 0; -+} -+ -+static ssize_t dpa_loop_write(struct file *f, -+ const char __user *buf, size_t count, loff_t *off) -+{ -+ struct dpa_priv_s *priv; -+ struct net_device *netdev; -+ struct seq_file *sf; -+ int ret; -+ long val; -+ -+ ret = user_input_convert(buf, count, &val); -+ if (ret) -+ return ret; -+ -+ sf = (struct seq_file *)f->private_data; -+ netdev = (struct net_device *)sf->private; -+ priv = netdev_priv(netdev); -+ -+ priv->loop_to = ((val < 0) || (val > 20)) ? -1 : val; -+ -+ return count; -+} -+ -+static int __cold dpa_debugfs_loop_open(struct inode *inode, struct file *file) -+{ -+ int _errno; -+ const struct net_device *net_dev; -+ -+ _errno = single_open(file, dpa_debugfs_loop_show, inode->i_private); -+ if (unlikely(_errno < 0)) { -+ net_dev = (struct net_device *)inode->i_private; -+ -+ if (netif_msg_drv((struct dpa_priv_s *)netdev_priv(net_dev))) -+ netdev_err(net_dev, "single_open() = %d\n", -+ _errno); -+ } -+ -+ return _errno; -+} -+ -+ -+int dpa_netdev_debugfs_create(struct net_device *net_dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ static int cnt; -+ char loop_file_name[100]; -+ -+ if (unlikely(dpa_debugfs_root == NULL)) { -+ pr_err(KBUILD_MODNAME ": %s:%hu:%s(): \t%s\n", -+ KBUILD_BASENAME".c", __LINE__, __func__, -+ "root debugfs missing, possible module ordering issue"); -+ return -ENOMEM; -+ } -+ -+ sprintf(loop_file_name, "eth%d_loop", ++cnt); -+ priv->debugfs_loop_file = debugfs_create_file(loop_file_name, -+ S_IRUGO, -+ dpa_debugfs_root, -+ net_dev, -+ &dpa_debugfs_lp_fops); -+ if (unlikely(priv->debugfs_loop_file == NULL)) { -+ netdev_err(net_dev, "debugfs_create_file(%s/%s)", -+ dpa_debugfs_root->d_iname, -+ loop_file_name); -+ -+ return -ENOMEM; -+ } -+ return 0; -+} -+ -+void dpa_netdev_debugfs_remove(struct net_device *net_dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ -+ debugfs_remove(priv->debugfs_loop_file); -+} -+ -+int __init dpa_debugfs_module_init(void) -+{ -+ int _errno = 0; -+ -+ pr_info(KBUILD_MODNAME ": " DPA_DEBUGFS_DESCRIPTION "\n"); -+ -+ dpa_debugfs_root = debugfs_create_dir(DPA_ETH_DEBUGFS_ROOT, NULL); -+ -+ if (unlikely(dpa_debugfs_root == NULL)) { -+ _errno = -ENOMEM; -+ pr_err(KBUILD_MODNAME ": %s:%hu:%s():\n", -+ KBUILD_BASENAME".c", __LINE__, __func__); -+ pr_err("\tdebugfs_create_dir(%s/"KBUILD_MODNAME") = %d\n", -+ DPA_ETH_DEBUGFS_ROOT, _errno); -+ } -+ -+ return _errno; -+} -+ -+void __exit dpa_debugfs_module_exit(void) -+{ -+ debugfs_remove(dpa_debugfs_root); -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_debugfs.h -@@ -0,0 +1,43 @@ -+/* Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef DPAA_DEBUGFS_H_ -+#define DPAA_DEBUGFS_H_ -+ -+#include -+#include /* struct dentry needed in dpaa_eth.h */ -+ -+int dpa_netdev_debugfs_create(struct net_device *net_dev); -+void dpa_netdev_debugfs_remove(struct net_device *net_dev); -+int __init dpa_debugfs_module_init(void); -+void __exit dpa_debugfs_module_exit(void); -+ -+#endif /* DPAA_DEBUGFS_H_ */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.c -@@ -0,0 +1,1183 @@ -+/* Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifdef CONFIG_FSL_DPAA_ETH_DEBUG -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": %s:%hu:%s() " fmt, \ -+ KBUILD_BASENAME".c", __LINE__, __func__ -+#else -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": " fmt -+#endif -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include /* arp_hdr_len() */ -+#include /* VLAN_HLEN */ -+#include /* struct icmphdr */ -+#include /* struct iphdr */ -+#include /* struct ipv6hdr */ -+#include /* struct udphdr */ -+#include /* struct tcphdr */ -+#include /* net_ratelimit() */ -+#include /* ETH_P_IP and ETH_P_IPV6 */ -+#include -+#include -+#include -+#include -+ -+#include "fsl_fman.h" -+#include "fm_ext.h" -+#include "fm_port_ext.h" -+ -+#include "mac.h" -+#include "dpaa_eth.h" -+#include "dpaa_eth_common.h" -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+#include "dpaa_debugfs.h" -+#endif /* CONFIG_FSL_DPAA_DBG_LOOP */ -+ -+/* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files -+ * using trace events only need to #include -+ */ -+#define CREATE_TRACE_POINTS -+#include "dpaa_eth_trace.h" -+ -+#define DPA_NAPI_WEIGHT 64 -+ -+/* Valid checksum indication */ -+#define DPA_CSUM_VALID 0xFFFF -+ -+#define DPA_DESCRIPTION "FSL DPAA Ethernet driver" -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+ -+MODULE_AUTHOR("Andy Fleming "); -+ -+MODULE_DESCRIPTION(DPA_DESCRIPTION); -+ -+static uint8_t debug = -1; -+module_param(debug, byte, S_IRUGO); -+MODULE_PARM_DESC(debug, "Module/Driver verbosity level"); -+ -+/* This has to work in tandem with the DPA_CS_THRESHOLD_xxx values. */ -+static uint16_t tx_timeout = 1000; -+module_param(tx_timeout, ushort, S_IRUGO); -+MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms"); -+ -+static const char rtx[][3] = { -+ [RX] = "RX", -+ [TX] = "TX" -+}; -+ -+/* BM */ -+ -+#define DPAA_ETH_MAX_PAD (L1_CACHE_BYTES * 8) -+ -+static uint8_t dpa_priv_common_bpid; -+ -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+struct net_device *dpa_loop_netdevs[20]; -+#endif -+ -+#ifdef CONFIG_PM -+ -+static int dpaa_suspend(struct device *dev) -+{ -+ struct net_device *net_dev; -+ struct dpa_priv_s *priv; -+ struct mac_device *mac_dev; -+ int err = 0; -+ -+ net_dev = dev_get_drvdata(dev); -+ -+ if (net_dev->flags & IFF_UP) { -+ priv = netdev_priv(net_dev); -+ mac_dev = priv->mac_dev; -+ -+ if (priv->wol & DPAA_WOL_MAGIC) { -+ err = priv->mac_dev->set_wol(mac_dev->port_dev[RX], -+ priv->mac_dev->get_mac_handle(mac_dev), true); -+ if (err) { -+ netdev_err(net_dev, "set_wol() = %d\n", err); -+ goto set_wol_failed; -+ } -+ } -+ -+ err = fm_port_suspend(mac_dev->port_dev[RX]); -+ if (err) { -+ netdev_err(net_dev, "fm_port_suspend(RX) = %d\n", err); -+ goto rx_port_suspend_failed; -+ } -+ -+ err = fm_port_suspend(mac_dev->port_dev[TX]); -+ if (err) { -+ netdev_err(net_dev, "fm_port_suspend(TX) = %d\n", err); -+ goto tx_port_suspend_failed; -+ } -+ } -+ -+ return 0; -+ -+tx_port_suspend_failed: -+ fm_port_resume(mac_dev->port_dev[RX]); -+rx_port_suspend_failed: -+ if (priv->wol & DPAA_WOL_MAGIC) { -+ priv->mac_dev->set_wol(mac_dev->port_dev[RX], -+ priv->mac_dev->get_mac_handle(mac_dev), false); -+ } -+set_wol_failed: -+ return err; -+} -+ -+static int dpaa_resume(struct device *dev) -+{ -+ struct net_device *net_dev; -+ struct dpa_priv_s *priv; -+ struct mac_device *mac_dev; -+ int err = 0; -+ -+ net_dev = dev_get_drvdata(dev); -+ -+ if (net_dev->flags & IFF_UP) { -+ priv = netdev_priv(net_dev); -+ mac_dev = priv->mac_dev; -+ -+ err = fm_port_resume(mac_dev->port_dev[TX]); -+ if (err) { -+ netdev_err(net_dev, "fm_port_resume(TX) = %d\n", err); -+ goto resume_failed; -+ } -+ -+ err = fm_port_resume(mac_dev->port_dev[RX]); -+ if (err) { -+ netdev_err(net_dev, "fm_port_resume(RX) = %d\n", err); -+ goto resume_failed; -+ } -+ -+ if (priv->wol & DPAA_WOL_MAGIC) { -+ err = priv->mac_dev->set_wol(mac_dev->port_dev[RX], -+ priv->mac_dev->get_mac_handle(mac_dev), false); -+ if (err) { -+ netdev_err(net_dev, "set_wol() = %d\n", err); -+ goto resume_failed; -+ } -+ } -+ } -+ -+ return 0; -+ -+resume_failed: -+ return err; -+} -+ -+static const struct dev_pm_ops dpaa_pm_ops = { -+ .suspend = dpaa_suspend, -+ .resume = dpaa_resume, -+}; -+ -+#define DPAA_PM_OPS (&dpaa_pm_ops) -+ -+#else /* CONFIG_PM */ -+ -+#define DPAA_PM_OPS NULL -+ -+#endif /* CONFIG_PM */ -+ -+/* Checks whether the checksum field in Parse Results array is valid -+ * (equals 0xFFFF) and increments the .cse counter otherwise -+ */ -+static inline void -+dpa_csum_validation(const struct dpa_priv_s *priv, -+ struct dpa_percpu_priv_s *percpu_priv, -+ const struct qm_fd *fd) -+{ -+ dma_addr_t addr = qm_fd_addr(fd); -+ struct dpa_bp *dpa_bp = priv->dpa_bp; -+ void *frm = phys_to_virt(addr); -+ fm_prs_result_t *parse_result; -+ -+ if (unlikely(!frm)) -+ return; -+ -+ dma_sync_single_for_cpu(dpa_bp->dev, addr, DPA_RX_PRIV_DATA_SIZE + -+ DPA_PARSE_RESULTS_SIZE, DMA_BIDIRECTIONAL); -+ -+ parse_result = (fm_prs_result_t *)(frm + DPA_RX_PRIV_DATA_SIZE); -+ -+ if (parse_result->cksum != DPA_CSUM_VALID) -+ percpu_priv->rx_errors.cse++; -+} -+ -+static void _dpa_rx_error(struct net_device *net_dev, -+ const struct dpa_priv_s *priv, -+ struct dpa_percpu_priv_s *percpu_priv, -+ const struct qm_fd *fd, -+ u32 fqid) -+{ -+ /* limit common, possibly innocuous Rx FIFO Overflow errors' -+ * interference with zero-loss convergence benchmark results. -+ */ -+ if (likely(fd->status & FM_FD_STAT_ERR_PHYSICAL)) -+ pr_warn_once("fsl-dpa: non-zero error counters in fman statistics (sysfs)\n"); -+ else -+ if (netif_msg_hw(priv) && net_ratelimit()) -+ netdev_dbg(net_dev, "Err FD status = 0x%08x\n", -+ fd->status & FM_FD_STAT_RX_ERRORS); -+#ifdef CONFIG_FSL_DPAA_HOOKS -+ if (dpaa_eth_hooks.rx_error && -+ dpaa_eth_hooks.rx_error(net_dev, fd, fqid) == DPAA_ETH_STOLEN) -+ /* it's up to the hook to perform resource cleanup */ -+ return; -+#endif -+ percpu_priv->stats.rx_errors++; -+ -+ if (fd->status & FM_PORT_FRM_ERR_DMA) -+ percpu_priv->rx_errors.dme++; -+ if (fd->status & FM_PORT_FRM_ERR_PHYSICAL) -+ percpu_priv->rx_errors.fpe++; -+ if (fd->status & FM_PORT_FRM_ERR_SIZE) -+ percpu_priv->rx_errors.fse++; -+ if (fd->status & FM_PORT_FRM_ERR_PRS_HDR_ERR) -+ percpu_priv->rx_errors.phe++; -+ if (fd->status & FM_FD_STAT_L4CV) -+ dpa_csum_validation(priv, percpu_priv, fd); -+ -+ dpa_fd_release(net_dev, fd); -+} -+ -+static void _dpa_tx_error(struct net_device *net_dev, -+ const struct dpa_priv_s *priv, -+ struct dpa_percpu_priv_s *percpu_priv, -+ const struct qm_fd *fd, -+ u32 fqid) -+{ -+ struct sk_buff *skb; -+ -+ if (netif_msg_hw(priv) && net_ratelimit()) -+ netdev_warn(net_dev, "FD status = 0x%08x\n", -+ fd->status & FM_FD_STAT_TX_ERRORS); -+#ifdef CONFIG_FSL_DPAA_HOOKS -+ if (dpaa_eth_hooks.tx_error && -+ dpaa_eth_hooks.tx_error(net_dev, fd, fqid) == DPAA_ETH_STOLEN) -+ /* now the hook must ensure proper cleanup */ -+ return; -+#endif -+ percpu_priv->stats.tx_errors++; -+ -+ /* If we intended the buffers from this frame to go into the bpools -+ * when the FMan transmit was done, we need to put it in manually. -+ */ -+ if (fd->bpid != 0xff) { -+ dpa_fd_release(net_dev, fd); -+ return; -+ } -+ -+ skb = _dpa_cleanup_tx_fd(priv, fd); -+ dev_kfree_skb(skb); -+} -+ -+/* Helper function to factor out frame validation logic on all Rx paths. Its -+ * purpose is to extract from the Parse Results structure information about -+ * the integrity of the frame, its checksum, the length of the parsed headers -+ * and whether the frame is suitable for GRO. -+ * -+ * Assumes no parser errors, since any error frame is dropped before this -+ * function is called. -+ * -+ * @skb will have its ip_summed field overwritten; -+ * @use_gro will only be written with 0, if the frame is definitely not -+ * GRO-able; otherwise, it will be left unchanged; -+ * @hdr_size will be written with a safe value, at least the size of the -+ * headers' length. -+ */ -+void __hot _dpa_process_parse_results(const fm_prs_result_t *parse_results, -+ const struct qm_fd *fd, -+ struct sk_buff *skb, int *use_gro) -+{ -+ if (fd->status & FM_FD_STAT_L4CV) { -+ /* The parser has run and performed L4 checksum validation. -+ * We know there were no parser errors (and implicitly no -+ * L4 csum error), otherwise we wouldn't be here. -+ */ -+ skb->ip_summed = CHECKSUM_UNNECESSARY; -+ -+ /* Don't go through GRO for certain types of traffic that -+ * we know are not GRO-able, such as dgram-based protocols. -+ * In the worst-case scenarios, such as small-pkt terminating -+ * UDP, the extra GRO processing would be overkill. -+ * -+ * The only protocol the Parser supports that is also GRO-able -+ * is currently TCP. -+ */ -+ if (!fm_l4_frame_is_tcp(parse_results)) -+ *use_gro = 0; -+ -+ return; -+ } -+ -+ /* We're here because either the parser didn't run or the L4 checksum -+ * was not verified. This may include the case of a UDP frame with -+ * checksum zero or an L4 proto other than TCP/UDP -+ */ -+ skb->ip_summed = CHECKSUM_NONE; -+ -+ /* Bypass GRO for unknown traffic or if no PCDs are applied */ -+ *use_gro = 0; -+} -+ -+int dpaa_eth_poll(struct napi_struct *napi, int budget) -+{ -+ struct dpa_napi_portal *np = -+ container_of(napi, struct dpa_napi_portal, napi); -+ -+ int cleaned = qman_p_poll_dqrr(np->p, budget); -+ -+ if (cleaned < budget) { -+ int tmp; -+ napi_complete(napi); -+ tmp = qman_p_irqsource_add(np->p, QM_PIRQ_DQRI); -+ DPA_BUG_ON(tmp); -+ } -+ -+ return cleaned; -+} -+EXPORT_SYMBOL(dpaa_eth_poll); -+ -+static void __hot _dpa_tx_conf(struct net_device *net_dev, -+ const struct dpa_priv_s *priv, -+ struct dpa_percpu_priv_s *percpu_priv, -+ const struct qm_fd *fd, -+ u32 fqid) -+{ -+ struct sk_buff *skb; -+ -+ /* do we need the timestamp for the error frames? */ -+ -+ if (unlikely(fd->status & FM_FD_STAT_TX_ERRORS) != 0) { -+ if (netif_msg_hw(priv) && net_ratelimit()) -+ netdev_warn(net_dev, "FD status = 0x%08x\n", -+ fd->status & FM_FD_STAT_TX_ERRORS); -+ -+ percpu_priv->stats.tx_errors++; -+ } -+ -+ /* hopefully we need not get the timestamp before the hook */ -+#ifdef CONFIG_FSL_DPAA_HOOKS -+ if (dpaa_eth_hooks.tx_confirm && dpaa_eth_hooks.tx_confirm(net_dev, -+ fd, fqid) == DPAA_ETH_STOLEN) -+ /* it's the hook that must now perform cleanup */ -+ return; -+#endif -+ /* This might not perfectly reflect the reality, if the core dequeuing -+ * the Tx confirmation is different from the one that did the enqueue, -+ * but at least it'll show up in the total count. -+ */ -+ percpu_priv->tx_confirm++; -+ -+ skb = _dpa_cleanup_tx_fd(priv, fd); -+ -+ dev_kfree_skb(skb); -+} -+ -+enum qman_cb_dqrr_result -+priv_rx_error_dqrr(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq) -+{ -+ struct net_device *net_dev; -+ struct dpa_priv_s *priv; -+ struct dpa_percpu_priv_s *percpu_priv; -+ int *count_ptr; -+ -+ net_dev = ((struct dpa_fq *)fq)->net_dev; -+ priv = netdev_priv(net_dev); -+ -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ count_ptr = raw_cpu_ptr(priv->dpa_bp->percpu_count); -+ -+ if (dpaa_eth_napi_schedule(percpu_priv, portal)) -+ return qman_cb_dqrr_stop; -+ -+ if (unlikely(dpaa_eth_refill_bpools(priv->dpa_bp, count_ptr))) -+ /* Unable to refill the buffer pool due to insufficient -+ * system memory. Just release the frame back into the pool, -+ * otherwise we'll soon end up with an empty buffer pool. -+ */ -+ dpa_fd_release(net_dev, &dq->fd); -+ else -+ _dpa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); -+ -+ return qman_cb_dqrr_consume; -+} -+ -+ -+enum qman_cb_dqrr_result __hot -+priv_rx_default_dqrr(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq) -+{ -+ struct net_device *net_dev; -+ struct dpa_priv_s *priv; -+ struct dpa_percpu_priv_s *percpu_priv; -+ int *count_ptr; -+ struct dpa_bp *dpa_bp; -+ -+ net_dev = ((struct dpa_fq *)fq)->net_dev; -+ priv = netdev_priv(net_dev); -+ dpa_bp = priv->dpa_bp; -+ -+ /* Trace the Rx fd */ -+ trace_dpa_rx_fd(net_dev, fq, &dq->fd); -+ -+ /* IRQ handler, non-migratable; safe to use raw_cpu_ptr here */ -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ count_ptr = raw_cpu_ptr(dpa_bp->percpu_count); -+ -+ if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal))) -+ return qman_cb_dqrr_stop; -+ -+ /* Vale of plenty: make sure we didn't run out of buffers */ -+ -+ if (unlikely(dpaa_eth_refill_bpools(dpa_bp, count_ptr))) -+ /* Unable to refill the buffer pool due to insufficient -+ * system memory. Just release the frame back into the pool, -+ * otherwise we'll soon end up with an empty buffer pool. -+ */ -+ dpa_fd_release(net_dev, &dq->fd); -+ else -+ _dpa_rx(net_dev, portal, priv, percpu_priv, &dq->fd, fq->fqid, -+ count_ptr); -+ -+ return qman_cb_dqrr_consume; -+} -+ -+enum qman_cb_dqrr_result -+priv_tx_conf_error_dqrr(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq) -+{ -+ struct net_device *net_dev; -+ struct dpa_priv_s *priv; -+ struct dpa_percpu_priv_s *percpu_priv; -+ -+ net_dev = ((struct dpa_fq *)fq)->net_dev; -+ priv = netdev_priv(net_dev); -+ -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ -+ if (dpaa_eth_napi_schedule(percpu_priv, portal)) -+ return qman_cb_dqrr_stop; -+ -+ _dpa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); -+ -+ return qman_cb_dqrr_consume; -+} -+ -+enum qman_cb_dqrr_result __hot -+priv_tx_conf_default_dqrr(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq) -+{ -+ struct net_device *net_dev; -+ struct dpa_priv_s *priv; -+ struct dpa_percpu_priv_s *percpu_priv; -+ -+ net_dev = ((struct dpa_fq *)fq)->net_dev; -+ priv = netdev_priv(net_dev); -+ -+ /* Trace the fd */ -+ trace_dpa_tx_conf_fd(net_dev, fq, &dq->fd); -+ -+ /* Non-migratable context, safe to use raw_cpu_ptr */ -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ -+ if (dpaa_eth_napi_schedule(percpu_priv, portal)) -+ return qman_cb_dqrr_stop; -+ -+ _dpa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); -+ -+ return qman_cb_dqrr_consume; -+} -+ -+void priv_ern(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_mr_entry *msg) -+{ -+ struct net_device *net_dev; -+ const struct dpa_priv_s *priv; -+ struct sk_buff *skb; -+ struct dpa_percpu_priv_s *percpu_priv; -+ struct qm_fd fd = msg->ern.fd; -+ -+ net_dev = ((struct dpa_fq *)fq)->net_dev; -+ priv = netdev_priv(net_dev); -+ /* Non-migratable context, safe to use raw_cpu_ptr */ -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ -+ percpu_priv->stats.tx_dropped++; -+ percpu_priv->stats.tx_fifo_errors++; -+ count_ern(percpu_priv, msg); -+ -+ /* If we intended this buffer to go into the pool -+ * when the FM was done, we need to put it in -+ * manually. -+ */ -+ if (msg->ern.fd.bpid != 0xff) { -+ dpa_fd_release(net_dev, &fd); -+ return; -+ } -+ -+ skb = _dpa_cleanup_tx_fd(priv, &fd); -+ dev_kfree_skb_any(skb); -+} -+ -+const struct dpa_fq_cbs_t private_fq_cbs = { -+ .rx_defq = { .cb = { .dqrr = priv_rx_default_dqrr } }, -+ .tx_defq = { .cb = { .dqrr = priv_tx_conf_default_dqrr } }, -+ .rx_errq = { .cb = { .dqrr = priv_rx_error_dqrr } }, -+ .tx_errq = { .cb = { .dqrr = priv_tx_conf_error_dqrr } }, -+ .egress_ern = { .cb = { .ern = priv_ern } } -+}; -+EXPORT_SYMBOL(private_fq_cbs); -+ -+static void dpaa_eth_napi_enable(struct dpa_priv_s *priv) -+{ -+ struct dpa_percpu_priv_s *percpu_priv; -+ int i, j; -+ -+ for_each_possible_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ -+ for (j = 0; j < qman_portal_max; j++) -+ napi_enable(&percpu_priv->np[j].napi); -+ } -+} -+ -+static void dpaa_eth_napi_disable(struct dpa_priv_s *priv) -+{ -+ struct dpa_percpu_priv_s *percpu_priv; -+ int i, j; -+ -+ for_each_possible_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ -+ for (j = 0; j < qman_portal_max; j++) -+ napi_disable(&percpu_priv->np[j].napi); -+ } -+} -+ -+static int __cold dpa_eth_priv_start(struct net_device *net_dev) -+{ -+ int err; -+ struct dpa_priv_s *priv; -+ -+ priv = netdev_priv(net_dev); -+ -+ dpaa_eth_napi_enable(priv); -+ -+ err = dpa_start(net_dev); -+ if (err < 0) -+ dpaa_eth_napi_disable(priv); -+ -+ return err; -+} -+ -+ -+ -+static int __cold dpa_eth_priv_stop(struct net_device *net_dev) -+{ -+ int _errno; -+ struct dpa_priv_s *priv; -+ -+ _errno = dpa_stop(net_dev); -+ /* Allow NAPI to consume any frame still in the Rx/TxConfirm -+ * ingress queues. This is to avoid a race between the current -+ * context and ksoftirqd which could leave NAPI disabled while -+ * in fact there's still Rx traffic to be processed. -+ */ -+ usleep_range(5000, 10000); -+ -+ priv = netdev_priv(net_dev); -+ dpaa_eth_napi_disable(priv); -+ -+ return _errno; -+} -+ -+#ifdef CONFIG_NET_POLL_CONTROLLER -+static void dpaa_eth_poll_controller(struct net_device *net_dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ struct dpa_percpu_priv_s *percpu_priv = -+ raw_cpu_ptr(priv->percpu_priv); -+ struct qman_portal *p; -+ const struct qman_portal_config *pc; -+ struct dpa_napi_portal *np; -+ -+ p = (struct qman_portal *)qman_get_affine_portal(smp_processor_id()); -+ pc = qman_p_get_portal_config(p); -+ np = &percpu_priv->np[pc->index]; -+ -+ qman_p_irqsource_remove(np->p, QM_PIRQ_DQRI); -+ qman_p_poll_dqrr(np->p, np->napi.weight); -+ qman_p_irqsource_add(np->p, QM_PIRQ_DQRI); -+} -+#endif -+ -+static const struct net_device_ops dpa_private_ops = { -+ .ndo_open = dpa_eth_priv_start, -+ .ndo_start_xmit = dpa_tx, -+ .ndo_stop = dpa_eth_priv_stop, -+ .ndo_tx_timeout = dpa_timeout, -+ .ndo_get_stats64 = dpa_get_stats64, -+ .ndo_set_mac_address = dpa_set_mac_address, -+ .ndo_validate_addr = eth_validate_addr, -+#ifdef CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE -+ .ndo_select_queue = dpa_select_queue, -+#endif -+ .ndo_change_mtu = dpa_change_mtu, -+ .ndo_set_rx_mode = dpa_set_rx_mode, -+ .ndo_init = dpa_ndo_init, -+ .ndo_set_features = dpa_set_features, -+ .ndo_fix_features = dpa_fix_features, -+ .ndo_do_ioctl = dpa_ioctl, -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ .ndo_poll_controller = dpaa_eth_poll_controller, -+#endif -+}; -+ -+static int dpa_private_napi_add(struct net_device *net_dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ struct dpa_percpu_priv_s *percpu_priv; -+ int i, cpu; -+ -+ for_each_possible_cpu(cpu) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu); -+ -+ percpu_priv->np = devm_kzalloc(net_dev->dev.parent, -+ qman_portal_max * sizeof(struct dpa_napi_portal), -+ GFP_KERNEL); -+ -+ if (unlikely(percpu_priv->np == NULL)) { -+ dev_err(net_dev->dev.parent, "devm_kzalloc() failed\n"); -+ return -ENOMEM; -+ } -+ -+ for (i = 0; i < qman_portal_max; i++) -+ netif_napi_add(net_dev, &percpu_priv->np[i].napi, -+ dpaa_eth_poll, DPA_NAPI_WEIGHT); -+ } -+ -+ return 0; -+} -+ -+void dpa_private_napi_del(struct net_device *net_dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ struct dpa_percpu_priv_s *percpu_priv; -+ int i, cpu; -+ -+ for_each_possible_cpu(cpu) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu); -+ -+ if (percpu_priv->np) { -+ for (i = 0; i < qman_portal_max; i++) -+ netif_napi_del(&percpu_priv->np[i].napi); -+ -+ devm_kfree(net_dev->dev.parent, percpu_priv->np); -+ } -+ } -+} -+EXPORT_SYMBOL(dpa_private_napi_del); -+ -+static int dpa_private_netdev_init(struct net_device *net_dev) -+{ -+ int i; -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ struct dpa_percpu_priv_s *percpu_priv; -+ const uint8_t *mac_addr; -+ -+ /* Although we access another CPU's private data here -+ * we do it at initialization so it is safe -+ */ -+ for_each_possible_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ percpu_priv->net_dev = net_dev; -+ } -+ -+ net_dev->netdev_ops = &dpa_private_ops; -+ mac_addr = priv->mac_dev->addr; -+ -+ net_dev->mem_start = priv->mac_dev->res->start; -+ net_dev->mem_end = priv->mac_dev->res->end; -+ -+ net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | -+ NETIF_F_LLTX); -+ -+ /* Advertise S/G and HIGHDMA support for private interfaces */ -+ net_dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA; -+ /* Recent kernels enable GSO automatically, if -+ * we declare NETIF_F_SG. For conformity, we'll -+ * still declare GSO explicitly. -+ */ -+ net_dev->features |= NETIF_F_GSO; -+ -+ /* Advertise GRO support */ -+ net_dev->features |= NETIF_F_GRO; -+ -+ return dpa_netdev_init(net_dev, mac_addr, tx_timeout); -+} -+ -+static struct dpa_bp * __cold -+dpa_priv_bp_probe(struct device *dev) -+{ -+ struct dpa_bp *dpa_bp; -+ -+ dpa_bp = devm_kzalloc(dev, sizeof(*dpa_bp), GFP_KERNEL); -+ if (unlikely(dpa_bp == NULL)) { -+ dev_err(dev, "devm_kzalloc() failed\n"); -+ return ERR_PTR(-ENOMEM); -+ } -+ -+ dpa_bp->percpu_count = devm_alloc_percpu(dev, *dpa_bp->percpu_count); -+ dpa_bp->target_count = CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT; -+ -+ dpa_bp->seed_cb = dpa_bp_priv_seed; -+ dpa_bp->free_buf_cb = _dpa_bp_free_pf; -+ -+ return dpa_bp; -+} -+ -+/* Place all ingress FQs (Rx Default, Rx Error, PCD FQs) in a dedicated CGR. -+ * We won't be sending congestion notifications to FMan; for now, we just use -+ * this CGR to generate enqueue rejections to FMan in order to drop the frames -+ * before they reach our ingress queues and eat up memory. -+ */ -+static int dpaa_eth_priv_ingress_cgr_init(struct dpa_priv_s *priv) -+{ -+ struct qm_mcc_initcgr initcgr; -+ u32 cs_th; -+ int err; -+ -+ err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid); -+ if (err < 0) { -+ pr_err("Error %d allocating CGR ID\n", err); -+ goto out_error; -+ } -+ -+ /* Enable CS TD, but disable Congestion State Change Notifications. */ -+ initcgr.we_mask = QM_CGR_WE_CS_THRES; -+ initcgr.cgr.cscn_en = QM_CGR_EN; -+ cs_th = CONFIG_FSL_DPAA_INGRESS_CS_THRESHOLD; -+ qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1); -+ -+ initcgr.we_mask |= QM_CGR_WE_CSTD_EN; -+ initcgr.cgr.cstd_en = QM_CGR_EN; -+ -+ /* This is actually a hack, because this CGR will be associated with -+ * our affine SWP. However, we'll place our ingress FQs in it. -+ */ -+ err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT, -+ &initcgr); -+ if (err < 0) { -+ pr_err("Error %d creating ingress CGR with ID %d\n", err, -+ priv->ingress_cgr.cgrid); -+ qman_release_cgrid(priv->ingress_cgr.cgrid); -+ goto out_error; -+ } -+ pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n", -+ priv->ingress_cgr.cgrid, priv->mac_dev->addr); -+ -+ /* struct qman_cgr allows special cgrid values (i.e. outside the 0..255 -+ * range), but we have no common initialization path between the -+ * different variants of the DPAA Eth driver, so we do it here rather -+ * than modifying every other variant than "private Eth". -+ */ -+ priv->use_ingress_cgr = true; -+ -+out_error: -+ return err; -+} -+ -+static int dpa_priv_bp_create(struct net_device *net_dev, struct dpa_bp *dpa_bp, -+ size_t count) -+{ -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ int i; -+ -+ if (netif_msg_probe(priv)) -+ dev_dbg(net_dev->dev.parent, -+ "Using private BM buffer pools\n"); -+ -+ priv->bp_count = count; -+ -+ for (i = 0; i < count; i++) { -+ int err; -+ err = dpa_bp_alloc(&dpa_bp[i]); -+ if (err < 0) { -+ dpa_bp_free(priv); -+ priv->dpa_bp = NULL; -+ return err; -+ } -+ -+ priv->dpa_bp = &dpa_bp[i]; -+ } -+ -+ dpa_priv_common_bpid = priv->dpa_bp->bpid; -+ return 0; -+} -+ -+static const struct of_device_id dpa_match[]; -+ -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+static int dpa_new_loop_id(void) -+{ -+ static int if_id; -+ -+ return if_id++; -+} -+#endif -+ -+static int -+dpaa_eth_priv_probe(struct platform_device *_of_dev) -+{ -+ int err = 0, i, channel; -+ struct device *dev; -+ struct device_node *dpa_node; -+ struct dpa_bp *dpa_bp; -+ struct dpa_fq *dpa_fq, *tmp; -+ size_t count = 1; -+ struct net_device *net_dev = NULL; -+ struct dpa_priv_s *priv = NULL; -+ struct dpa_percpu_priv_s *percpu_priv; -+ struct fm_port_fqs port_fqs; -+ struct dpa_buffer_layout_s *buf_layout = NULL; -+ struct mac_device *mac_dev; -+ struct task_struct *kth; -+ -+ dev = &_of_dev->dev; -+ -+ dpa_node = dev->of_node; -+ -+ if (!of_device_is_available(dpa_node)) -+ return -ENODEV; -+ -+ /* Get the buffer pools assigned to this interface; -+ * run only once the default pool probing code -+ */ -+ dpa_bp = (dpa_bpid2pool(dpa_priv_common_bpid)) ? : -+ dpa_priv_bp_probe(dev); -+ if (IS_ERR(dpa_bp)) -+ return PTR_ERR(dpa_bp); -+ -+ /* Allocate this early, so we can store relevant information in -+ * the private area (needed by 1588 code in dpa_mac_probe) -+ */ -+ net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TX_QUEUES); -+ if (!net_dev) { -+ dev_err(dev, "alloc_etherdev_mq() failed\n"); -+ goto alloc_etherdev_mq_failed; -+ } -+ -+ /* Do this here, so we can be verbose early */ -+ SET_NETDEV_DEV(net_dev, dev); -+ dev_set_drvdata(dev, net_dev); -+ -+ priv = netdev_priv(net_dev); -+ priv->net_dev = net_dev; -+ strcpy(priv->if_type, "private"); -+ -+ priv->msg_enable = netif_msg_init(debug, -1); -+ -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+ priv->loop_id = dpa_new_loop_id(); -+ priv->loop_to = -1; /* disabled by default */ -+ dpa_loop_netdevs[priv->loop_id] = net_dev; -+#endif -+ -+ mac_dev = dpa_mac_probe(_of_dev); -+ if (IS_ERR(mac_dev) || !mac_dev) { -+ err = PTR_ERR(mac_dev); -+ goto mac_probe_failed; -+ } -+ -+ /* We have physical ports, so we need to establish -+ * the buffer layout. -+ */ -+ buf_layout = devm_kzalloc(dev, 2 * sizeof(*buf_layout), -+ GFP_KERNEL); -+ if (!buf_layout) { -+ dev_err(dev, "devm_kzalloc() failed\n"); -+ goto alloc_failed; -+ } -+ dpa_set_buffers_layout(mac_dev, buf_layout); -+ -+ /* For private ports, need to compute the size of the default -+ * buffer pool, based on FMan port buffer layout;also update -+ * the maximum buffer size for private ports if necessary -+ */ -+ dpa_bp->size = dpa_bp_size(&buf_layout[RX]); -+ -+#ifdef CONFIG_FSL_DPAA_ETH_JUMBO_FRAME -+ /* We only want to use jumbo frame optimization if we actually have -+ * L2 MAX FRM set for jumbo frames as well. -+ */ -+ if (fm_get_max_frm() < 9600) -+ dev_warn(dev, -+ "Invalid configuration: if jumbo frames support is on, FSL_FM_MAX_FRAME_SIZE should be set to 9600\n"); -+#endif -+ -+ INIT_LIST_HEAD(&priv->dpa_fq_list); -+ -+ memset(&port_fqs, 0, sizeof(port_fqs)); -+ -+ err = dpa_fq_probe_mac(dev, &priv->dpa_fq_list, &port_fqs, true, RX); -+ if (!err) -+ err = dpa_fq_probe_mac(dev, &priv->dpa_fq_list, -+ &port_fqs, true, TX); -+ -+ if (err < 0) -+ goto fq_probe_failed; -+ -+ /* bp init */ -+ -+ err = dpa_priv_bp_create(net_dev, dpa_bp, count); -+ -+ if (err < 0) -+ goto bp_create_failed; -+ -+ priv->mac_dev = mac_dev; -+ -+ channel = dpa_get_channel(); -+ -+ if (channel < 0) { -+ err = channel; -+ goto get_channel_failed; -+ } -+ -+ priv->channel = (uint16_t)channel; -+ -+ /* Start a thread that will walk the cpus with affine portals -+ * and add this pool channel to each's dequeue mask. -+ */ -+ kth = kthread_run(dpaa_eth_add_channel, -+ (void *)(unsigned long)priv->channel, -+ "dpaa_%p:%d", net_dev, priv->channel); -+ if (!kth) { -+ err = -ENOMEM; -+ goto add_channel_failed; -+ } -+ -+ dpa_fq_setup(priv, &private_fq_cbs, priv->mac_dev->port_dev[TX]); -+ -+ /* Create a congestion group for this netdev, with -+ * dynamically-allocated CGR ID. -+ * Must be executed after probing the MAC, but before -+ * assigning the egress FQs to the CGRs. -+ */ -+ err = dpaa_eth_cgr_init(priv); -+ if (err < 0) { -+ dev_err(dev, "Error initializing CGR\n"); -+ goto tx_cgr_init_failed; -+ } -+ err = dpaa_eth_priv_ingress_cgr_init(priv); -+ if (err < 0) { -+ dev_err(dev, "Error initializing ingress CGR\n"); -+ goto rx_cgr_init_failed; -+ } -+ -+ /* Add the FQs to the interface, and make them active */ -+ list_for_each_entry_safe(dpa_fq, tmp, &priv->dpa_fq_list, list) { -+ err = dpa_fq_init(dpa_fq, false); -+ if (err < 0) -+ goto fq_alloc_failed; -+ } -+ -+ priv->buf_layout = buf_layout; -+ priv->tx_headroom = dpa_get_headroom(&priv->buf_layout[TX]); -+ priv->rx_headroom = dpa_get_headroom(&priv->buf_layout[RX]); -+ -+ /* All real interfaces need their ports initialized */ -+ dpaa_eth_init_ports(mac_dev, dpa_bp, count, &port_fqs, -+ buf_layout, dev); -+ -+#ifdef CONFIG_FMAN_PFC -+ for (i = 0; i < CONFIG_FMAN_PFC_COS_COUNT; i++) { -+ err = fm_port_set_pfc_priorities_mapping_to_qman_wq( -+ mac_dev->port_dev[TX], i, i); -+ if (unlikely(err != 0)) { -+ dev_err(dev, "Error maping PFC %u to WQ %u\n", i, i); -+ goto pfc_mapping_failed; -+ } -+ } -+#endif -+ -+ priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv); -+ -+ if (priv->percpu_priv == NULL) { -+ dev_err(dev, "devm_alloc_percpu() failed\n"); -+ err = -ENOMEM; -+ goto alloc_percpu_failed; -+ } -+ for_each_possible_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ memset(percpu_priv, 0, sizeof(*percpu_priv)); -+ } -+ -+ /* Initialize NAPI */ -+ err = dpa_private_napi_add(net_dev); -+ -+ if (err < 0) -+ goto napi_add_failed; -+ -+ err = dpa_private_netdev_init(net_dev); -+ -+ if (err < 0) -+ goto netdev_init_failed; -+ -+ dpaa_eth_sysfs_init(&net_dev->dev); -+ -+#ifdef CONFIG_PM -+ device_set_wakeup_capable(dev, true); -+#endif -+ -+ pr_info("fsl_dpa: Probed interface %s\n", net_dev->name); -+ -+ return 0; -+ -+netdev_init_failed: -+napi_add_failed: -+ dpa_private_napi_del(net_dev); -+alloc_percpu_failed: -+#ifdef CONFIG_FMAN_PFC -+pfc_mapping_failed: -+#endif -+ dpa_fq_free(dev, &priv->dpa_fq_list); -+fq_alloc_failed: -+ qman_delete_cgr_safe(&priv->ingress_cgr); -+ qman_release_cgrid(priv->ingress_cgr.cgrid); -+rx_cgr_init_failed: -+ qman_delete_cgr_safe(&priv->cgr_data.cgr); -+ qman_release_cgrid(priv->cgr_data.cgr.cgrid); -+tx_cgr_init_failed: -+add_channel_failed: -+get_channel_failed: -+ dpa_bp_free(priv); -+bp_create_failed: -+fq_probe_failed: -+alloc_failed: -+mac_probe_failed: -+ dev_set_drvdata(dev, NULL); -+ free_netdev(net_dev); -+alloc_etherdev_mq_failed: -+ if (atomic_read(&dpa_bp->refs) == 0) -+ devm_kfree(dev, dpa_bp); -+ -+ return err; -+} -+ -+static const struct of_device_id dpa_match[] = { -+ { -+ .compatible = "fsl,dpa-ethernet" -+ }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, dpa_match); -+ -+static struct platform_driver dpa_driver = { -+ .driver = { -+ .name = KBUILD_MODNAME, -+ .of_match_table = dpa_match, -+ .owner = THIS_MODULE, -+ .pm = DPAA_PM_OPS, -+ }, -+ .probe = dpaa_eth_priv_probe, -+ .remove = dpa_remove -+}; -+ -+static int __init __cold dpa_load(void) -+{ -+ int _errno; -+ -+ pr_info(DPA_DESCRIPTION "\n"); -+ -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+ dpa_debugfs_module_init(); -+#endif /* CONFIG_FSL_DPAA_DBG_LOOP */ -+ -+ /* initialise dpaa_eth mirror values */ -+ dpa_rx_extra_headroom = fm_get_rx_extra_headroom(); -+ dpa_max_frm = fm_get_max_frm(); -+ dpa_num_cpus = num_possible_cpus(); -+ -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+ memset(dpa_loop_netdevs, 0, sizeof(dpa_loop_netdevs)); -+#endif -+ -+ _errno = platform_driver_register(&dpa_driver); -+ if (unlikely(_errno < 0)) { -+ pr_err(KBUILD_MODNAME -+ ": %s:%hu:%s(): platform_driver_register() = %d\n", -+ KBUILD_BASENAME".c", __LINE__, __func__, _errno); -+ } -+ -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+ -+ return _errno; -+} -+module_init(dpa_load); -+ -+static void __exit __cold dpa_unload(void) -+{ -+ pr_debug(KBUILD_MODNAME ": -> %s:%s()\n", -+ KBUILD_BASENAME".c", __func__); -+ -+ platform_driver_unregister(&dpa_driver); -+ -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+ dpa_debugfs_module_exit(); -+#endif /* CONFIG_FSL_DPAA_DBG_LOOP */ -+ -+ /* Only one channel is used and needs to be relased after all -+ * interfaces are removed -+ */ -+ dpa_release_channel(); -+ -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+} -+module_exit(dpa_unload); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.h -@@ -0,0 +1,695 @@ -+/* Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __DPA_H -+#define __DPA_H -+ -+#include -+#include /* struct qman_fq */ -+ -+#include "fm_ext.h" -+#include "dpaa_eth_trace.h" -+ -+extern int dpa_rx_extra_headroom; -+extern int dpa_max_frm; -+extern int dpa_num_cpus; -+ -+#define dpa_get_rx_extra_headroom() dpa_rx_extra_headroom -+#define dpa_get_max_frm() dpa_max_frm -+ -+#define dpa_get_max_mtu() \ -+ (dpa_get_max_frm() - (VLAN_ETH_HLEN + ETH_FCS_LEN)) -+ -+#define __hot -+ -+/* Simple enum of FQ types - used for array indexing */ -+enum port_type {RX, TX}; -+ -+/* TODO: This structure should be renamed & moved to the FMD wrapper */ -+struct dpa_buffer_layout_s { -+ uint16_t priv_data_size; -+ bool parse_results; -+ bool time_stamp; -+ bool hash_results; -+ uint8_t manip_extra_space; -+ uint16_t data_align; -+}; -+ -+#ifdef CONFIG_FSL_DPAA_ETH_DEBUG -+#define DPA_BUG_ON(cond) BUG_ON(cond) -+#else -+#define DPA_BUG_ON(cond) -+#endif -+ -+#define DPA_TX_PRIV_DATA_SIZE 16 -+#define DPA_PARSE_RESULTS_SIZE sizeof(fm_prs_result_t) -+#define DPA_TIME_STAMP_SIZE 8 -+#define DPA_HASH_RESULTS_SIZE 8 -+#define DPA_RX_PRIV_DATA_SIZE (DPA_TX_PRIV_DATA_SIZE + \ -+ dpa_get_rx_extra_headroom()) -+ -+#define FM_FD_STAT_RX_ERRORS \ -+ (FM_PORT_FRM_ERR_DMA | FM_PORT_FRM_ERR_PHYSICAL | \ -+ FM_PORT_FRM_ERR_SIZE | FM_PORT_FRM_ERR_CLS_DISCARD | \ -+ FM_PORT_FRM_ERR_EXTRACTION | FM_PORT_FRM_ERR_NO_SCHEME | \ -+ FM_PORT_FRM_ERR_ILL_PLCR | FM_PORT_FRM_ERR_PRS_TIMEOUT | \ -+ FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT | FM_PORT_FRM_ERR_PRS_HDR_ERR) -+ -+#define FM_FD_STAT_TX_ERRORS \ -+ (FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT | \ -+ FM_PORT_FRM_ERR_LENGTH | FM_PORT_FRM_ERR_DMA) -+ -+#ifndef CONFIG_FSL_DPAA_ETH_JUMBO_FRAME -+/* The raw buffer size must be cacheline aligned. -+ * Normally we use 2K buffers. -+ */ -+#define DPA_BP_RAW_SIZE 2048 -+#else -+/* For jumbo frame optimizations, use buffers large enough to accommodate -+ * 9.6K frames, FD maximum offset, skb sh_info overhead and some extra -+ * space to account for further alignments. -+ */ -+#define DPA_MAX_FRM_SIZE 9600 -+#define DPA_BP_RAW_SIZE \ -+ ((DPA_MAX_FRM_SIZE + DPA_MAX_FD_OFFSET + \ -+ sizeof(struct skb_shared_info) + 128) & ~(SMP_CACHE_BYTES - 1)) -+#endif -+ -+/* This is what FMan is ever allowed to use. -+ * FMan-DMA requires 16-byte alignment for Rx buffers, but SKB_DATA_ALIGN is -+ * even stronger (SMP_CACHE_BYTES-aligned), so we just get away with that, -+ * via SKB_WITH_OVERHEAD(). We can't rely on netdev_alloc_frag() giving us -+ * half-page-aligned buffers (can we?), so we reserve some more space -+ * for start-of-buffer alignment. -+ */ -+#define dpa_bp_size(buffer_layout) (SKB_WITH_OVERHEAD(DPA_BP_RAW_SIZE) - \ -+ SMP_CACHE_BYTES) -+/* We must ensure that skb_shinfo is always cacheline-aligned. */ -+#define DPA_SKB_SIZE(size) ((size) & ~(SMP_CACHE_BYTES - 1)) -+ -+/* Maximum size of a buffer for which recycling is allowed. -+ * We need an upper limit such that forwarded skbs that get reallocated on Tx -+ * aren't allowed to grow unboundedly. On the other hand, we need to make sure -+ * that skbs allocated by us will not fail to be recycled due to their size. -+ * -+ * For a requested size, the kernel allocator provides the next power of two -+ * sized block, which the stack will use as is, regardless of the actual size -+ * it required; since we must accommodate at most 9.6K buffers (L2 maximum -+ * supported frame size), set the recycling upper limit to 16K. -+ */ -+#define DPA_RECYCLE_MAX_SIZE 16384 -+ -+#if defined(CONFIG_FSL_SDK_FMAN_TEST) -+/*TODO: temporary for fman pcd testing */ -+#define FMAN_PCD_TESTS_MAX_NUM_RANGES 20 -+#endif -+ -+#define DPAA_ETH_FQ_DELTA 0x10000 -+ -+#define DPAA_ETH_PCD_FQ_BASE(device_addr) \ -+ (((device_addr) & 0x1fffff) >> 6) -+ -+#define DPAA_ETH_PCD_FQ_HI_PRIO_BASE(device_addr) \ -+ (DPAA_ETH_FQ_DELTA + DPAA_ETH_PCD_FQ_BASE(device_addr)) -+ -+/* Largest value that the FQD's OAL field can hold. -+ * This is DPAA-1.x specific. -+ * TODO: This rather belongs in fsl_qman.h -+ */ -+#define FSL_QMAN_MAX_OAL 127 -+ -+/* Maximum offset value for a contig or sg FD (represented on 9 bits) */ -+#define DPA_MAX_FD_OFFSET ((1 << 9) - 1) -+ -+/* Default alignment for start of data in an Rx FD */ -+#define DPA_FD_DATA_ALIGNMENT 16 -+ -+/* Values for the L3R field of the FM Parse Results -+ */ -+/* L3 Type field: First IP Present IPv4 */ -+#define FM_L3_PARSE_RESULT_IPV4 0x8000 -+/* L3 Type field: First IP Present IPv6 */ -+#define FM_L3_PARSE_RESULT_IPV6 0x4000 -+ -+/* Values for the L4R field of the FM Parse Results -+ * See $8.8.4.7.20 - L4 HXS - L4 Results from DPAA-Rev2 Reference Manual. -+ */ -+/* L4 Type field: UDP */ -+#define FM_L4_PARSE_RESULT_UDP 0x40 -+/* L4 Type field: TCP */ -+#define FM_L4_PARSE_RESULT_TCP 0x20 -+/* FD status field indicating whether the FM Parser has attempted to validate -+ * the L4 csum of the frame. -+ * Note that having this bit set doesn't necessarily imply that the checksum -+ * is valid. One would have to check the parse results to find that out. -+ */ -+#define FM_FD_STAT_L4CV 0x00000004 -+ -+ -+#define FM_FD_STAT_ERR_PHYSICAL FM_PORT_FRM_ERR_PHYSICAL -+ -+/* Check if the parsed frame was found to be a TCP segment. -+ * -+ * @parse_result_ptr must be of type (fm_prs_result_t *). -+ */ -+#define fm_l4_frame_is_tcp(parse_result_ptr) \ -+ ((parse_result_ptr)->l4r & FM_L4_PARSE_RESULT_TCP) -+ -+/* number of Tx queues to FMan */ -+#ifdef CONFIG_FMAN_PFC -+#define DPAA_ETH_TX_QUEUES (NR_CPUS * CONFIG_FMAN_PFC_COS_COUNT) -+#else -+#define DPAA_ETH_TX_QUEUES NR_CPUS -+#endif -+ -+#define DPAA_ETH_RX_QUEUES 128 -+ -+/* Convenience macros for storing/retrieving the skb back-pointers. They must -+ * accommodate both recycling and confirmation paths - i.e. cases when the buf -+ * was allocated by ourselves, respectively by the stack. In the former case, -+ * we could store the skb at negative offset; in the latter case, we can't, -+ * so we'll use 0 as offset. -+ * -+ * NB: @off is an offset from a (struct sk_buff **) pointer! -+ */ -+#define DPA_WRITE_SKB_PTR(skb, skbh, addr, off) \ -+{ \ -+ skbh = (struct sk_buff **)addr; \ -+ *(skbh + (off)) = skb; \ -+} -+#define DPA_READ_SKB_PTR(skb, skbh, addr, off) \ -+{ \ -+ skbh = (struct sk_buff **)addr; \ -+ skb = *(skbh + (off)); \ -+} -+ -+#ifdef CONFIG_PM -+/* Magic Packet wakeup */ -+#define DPAA_WOL_MAGIC 0x00000001 -+#endif -+ -+#if defined(CONFIG_FSL_SDK_FMAN_TEST) -+struct pcd_range { -+ uint32_t base; -+ uint32_t count; -+}; -+#endif -+ -+/* More detailed FQ types - used for fine-grained WQ assignments */ -+enum dpa_fq_type { -+ FQ_TYPE_RX_DEFAULT = 1, /* Rx Default FQs */ -+ FQ_TYPE_RX_ERROR, /* Rx Error FQs */ -+ FQ_TYPE_RX_PCD, /* User-defined PCDs */ -+ FQ_TYPE_TX, /* "Real" Tx FQs */ -+ FQ_TYPE_TX_CONFIRM, /* Tx default Conf FQ (actually an Rx FQ) */ -+ FQ_TYPE_TX_CONF_MQ, /* Tx conf FQs (one for each Tx FQ) */ -+ FQ_TYPE_TX_ERROR, /* Tx Error FQs (these are actually Rx FQs) */ -+ FQ_TYPE_RX_PCD_HI_PRIO, /* User-defined high-priority PCDs */ -+}; -+ -+struct dpa_fq { -+ struct qman_fq fq_base; -+ struct list_head list; -+ struct net_device *net_dev; -+ bool init; -+ uint32_t fqid; -+ uint32_t flags; -+ uint16_t channel; -+ uint8_t wq; -+ enum dpa_fq_type fq_type; -+}; -+ -+struct dpa_fq_cbs_t { -+ struct qman_fq rx_defq; -+ struct qman_fq tx_defq; -+ struct qman_fq rx_errq; -+ struct qman_fq tx_errq; -+ struct qman_fq egress_ern; -+}; -+ -+struct fqid_cell { -+ uint32_t start; -+ uint32_t count; -+}; -+ -+struct dpa_bp { -+ struct bman_pool *pool; -+ uint8_t bpid; -+ struct device *dev; -+ union { -+ /* The buffer pools used for the private ports are initialized -+ * with target_count buffers for each CPU; at runtime the -+ * number of buffers per CPU is constantly brought back to this -+ * level -+ */ -+ int target_count; -+ /* The configured value for the number of buffers in the pool, -+ * used for shared port buffer pools -+ */ -+ int config_count; -+ }; -+ size_t size; -+ bool seed_pool; -+ /* physical address of the contiguous memory used by the pool to store -+ * the buffers -+ */ -+ dma_addr_t paddr; -+ /* virtual address of the contiguous memory used by the pool to store -+ * the buffers -+ */ -+ void __iomem *vaddr; -+ /* current number of buffers in the bpool alloted to this CPU */ -+ int __percpu *percpu_count; -+ atomic_t refs; -+ /* some bpools need to be seeded before use by this cb */ -+ int (*seed_cb)(struct dpa_bp *); -+ /* some bpools need to be emptied before freeing; this cb is used -+ * for freeing of individual buffers taken from the pool -+ */ -+ void (*free_buf_cb)(void *addr); -+}; -+ -+struct dpa_rx_errors { -+ u64 dme; /* DMA Error */ -+ u64 fpe; /* Frame Physical Error */ -+ u64 fse; /* Frame Size Error */ -+ u64 phe; /* Header Error */ -+ u64 cse; /* Checksum Validation Error */ -+}; -+ -+/* Counters for QMan ERN frames - one counter per rejection code */ -+struct dpa_ern_cnt { -+ u64 cg_tdrop; /* Congestion group taildrop */ -+ u64 wred; /* WRED congestion */ -+ u64 err_cond; /* Error condition */ -+ u64 early_window; /* Order restoration, frame too early */ -+ u64 late_window; /* Order restoration, frame too late */ -+ u64 fq_tdrop; /* FQ taildrop */ -+ u64 fq_retired; /* FQ is retired */ -+ u64 orp_zero; /* ORP disabled */ -+}; -+ -+struct dpa_napi_portal { -+ struct napi_struct napi; -+ struct qman_portal *p; -+}; -+ -+struct dpa_percpu_priv_s { -+ struct net_device *net_dev; -+ struct dpa_napi_portal *np; -+ u64 in_interrupt; -+ u64 tx_returned; -+ u64 tx_confirm; -+ /* fragmented (non-linear) skbuffs received from the stack */ -+ u64 tx_frag_skbuffs; -+ /* number of S/G frames received */ -+ u64 rx_sg; -+ -+ struct rtnl_link_stats64 stats; -+ struct dpa_rx_errors rx_errors; -+ struct dpa_ern_cnt ern_cnt; -+}; -+ -+struct dpa_priv_s { -+ struct dpa_percpu_priv_s __percpu *percpu_priv; -+ struct dpa_bp *dpa_bp; -+ /* Store here the needed Tx headroom for convenience and speed -+ * (even though it can be computed based on the fields of buf_layout) -+ */ -+ uint16_t tx_headroom; -+ struct net_device *net_dev; -+ struct mac_device *mac_dev; -+ struct qman_fq *egress_fqs[DPAA_ETH_TX_QUEUES]; -+ struct qman_fq *conf_fqs[DPAA_ETH_TX_QUEUES]; -+ -+ size_t bp_count; -+ -+ uint16_t channel; /* "fsl,qman-channel-id" */ -+ struct list_head dpa_fq_list; -+ -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+ struct dentry *debugfs_loop_file; -+#endif -+ -+ uint32_t msg_enable; /* net_device message level */ -+#ifdef CONFIG_FSL_DPAA_1588 -+ struct dpa_ptp_tsu *tsu; -+#endif -+ -+#if defined(CONFIG_FSL_SDK_FMAN_TEST) -+/* TODO: this is temporary until pcd support is implemented in dpaa */ -+ int priv_pcd_num_ranges; -+ struct pcd_range priv_pcd_ranges[FMAN_PCD_TESTS_MAX_NUM_RANGES]; -+#endif -+ -+ struct { -+ /** -+ * All egress queues to a given net device belong to one -+ * (and the same) congestion group. -+ */ -+ struct qman_cgr cgr; -+ /* If congested, when it began. Used for performance stats. */ -+ u32 congestion_start_jiffies; -+ /* Number of jiffies the Tx port was congested. */ -+ u32 congested_jiffies; -+ /** -+ * Counter for the number of times the CGR -+ * entered congestion state -+ */ -+ u32 cgr_congested_count; -+ } cgr_data; -+ /* Use a per-port CGR for ingress traffic. */ -+ bool use_ingress_cgr; -+ struct qman_cgr ingress_cgr; -+ -+#ifdef CONFIG_FSL_DPAA_TS -+ bool ts_tx_en; /* Tx timestamping enabled */ -+ bool ts_rx_en; /* Rx timestamping enabled */ -+#endif /* CONFIG_FSL_DPAA_TS */ -+ -+ struct dpa_buffer_layout_s *buf_layout; -+ uint16_t rx_headroom; -+ char if_type[30]; -+ -+ void *peer; -+#ifdef CONFIG_PM -+ u32 wol; -+#endif -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+ int loop_id; -+ int loop_to; -+#endif -+#ifdef CONFIG_FSL_DPAA_CEETM -+ bool ceetm_en; /* CEETM QoS enabled */ -+#endif -+}; -+ -+struct fm_port_fqs { -+ struct dpa_fq *tx_defq; -+ struct dpa_fq *tx_errq; -+ struct dpa_fq *rx_defq; -+ struct dpa_fq *rx_errq; -+}; -+ -+ -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+extern struct net_device *dpa_loop_netdevs[20]; -+#endif -+ -+/* functions with different implementation for SG and non-SG: */ -+int dpa_bp_priv_seed(struct dpa_bp *dpa_bp); -+int dpaa_eth_refill_bpools(struct dpa_bp *dpa_bp, int *count_ptr); -+void __hot _dpa_rx(struct net_device *net_dev, -+ struct qman_portal *portal, -+ const struct dpa_priv_s *priv, -+ struct dpa_percpu_priv_s *percpu_priv, -+ const struct qm_fd *fd, -+ u32 fqid, -+ int *count_ptr); -+int __hot dpa_tx(struct sk_buff *skb, struct net_device *net_dev); -+int __hot dpa_tx_extended(struct sk_buff *skb, struct net_device *net_dev, -+ struct qman_fq *egress_fq, struct qman_fq *conf_fq); -+struct sk_buff *_dpa_cleanup_tx_fd(const struct dpa_priv_s *priv, -+ const struct qm_fd *fd); -+void __hot _dpa_process_parse_results(const fm_prs_result_t *parse_results, -+ const struct qm_fd *fd, -+ struct sk_buff *skb, -+ int *use_gro); -+#ifndef CONFIG_FSL_DPAA_TS -+bool dpa_skb_is_recyclable(struct sk_buff *skb); -+bool dpa_buf_is_recyclable(struct sk_buff *skb, -+ uint32_t min_size, -+ uint16_t min_offset, -+ unsigned char **new_buf_start); -+#endif -+int __hot skb_to_contig_fd(struct dpa_priv_s *priv, -+ struct sk_buff *skb, struct qm_fd *fd, -+ int *count_ptr, int *offset); -+int __hot skb_to_sg_fd(struct dpa_priv_s *priv, -+ struct sk_buff *skb, struct qm_fd *fd); -+int __cold __attribute__((nonnull)) -+ _dpa_fq_free(struct device *dev, struct qman_fq *fq); -+ -+/* Turn on HW checksum computation for this outgoing frame. -+ * If the current protocol is not something we support in this regard -+ * (or if the stack has already computed the SW checksum), we do nothing. -+ * -+ * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value -+ * otherwise. -+ * -+ * Note that this function may modify the fd->cmd field and the skb data buffer -+ * (the Parse Results area). -+ */ -+int dpa_enable_tx_csum(struct dpa_priv_s *priv, -+ struct sk_buff *skb, struct qm_fd *fd, char *parse_results); -+ -+static inline int dpaa_eth_napi_schedule(struct dpa_percpu_priv_s *percpu_priv, -+ struct qman_portal *portal) -+{ -+ /* In case of threaded ISR for RT enable kernel, -+ * in_irq() does not return appropriate value, so use -+ * in_serving_softirq to distinguish softirq or irq context. -+ */ -+ if (unlikely(in_irq() || !in_serving_softirq())) { -+ /* Disable QMan IRQ and invoke NAPI */ -+ int ret = qman_p_irqsource_remove(portal, QM_PIRQ_DQRI); -+ if (likely(!ret)) { -+ const struct qman_portal_config *pc = -+ qman_p_get_portal_config(portal); -+ struct dpa_napi_portal *np = -+ &percpu_priv->np[pc->index]; -+ -+ np->p = portal; -+ napi_schedule(&np->napi); -+ percpu_priv->in_interrupt++; -+ return 1; -+ } -+ } -+ return 0; -+} -+ -+static inline ssize_t __const __must_check __attribute__((nonnull)) -+dpa_fd_length(const struct qm_fd *fd) -+{ -+ return fd->length20; -+} -+ -+static inline ssize_t __const __must_check __attribute__((nonnull)) -+dpa_fd_offset(const struct qm_fd *fd) -+{ -+ return fd->offset; -+} -+ -+/* Verifies if the skb length is below the interface MTU */ -+static inline int dpa_check_rx_mtu(struct sk_buff *skb, int mtu) -+{ -+ if (unlikely(skb->len > mtu)) -+ if ((skb->protocol != htons(ETH_P_8021Q)) -+ || (skb->len > mtu + 4)) -+ return -1; -+ -+ return 0; -+} -+ -+static inline uint16_t dpa_get_headroom(struct dpa_buffer_layout_s *bl) -+{ -+ uint16_t headroom; -+ /* The frame headroom must accommodate: -+ * - the driver private data area -+ * - parse results, hash results, timestamp if selected -+ * - manip extra space -+ * If either hash results or time stamp are selected, both will -+ * be copied to/from the frame headroom, as TS is located between PR and -+ * HR in the IC and IC copy size has a granularity of 16bytes -+ * (see description of FMBM_RICP and FMBM_TICP registers in DPAARM) -+ * -+ * Also make sure the headroom is a multiple of data_align bytes -+ */ -+ headroom = (uint16_t)(bl->priv_data_size + -+ (bl->parse_results ? DPA_PARSE_RESULTS_SIZE : 0) + -+ (bl->hash_results || bl->time_stamp ? -+ DPA_TIME_STAMP_SIZE + DPA_HASH_RESULTS_SIZE : 0) + -+ bl->manip_extra_space); -+ -+ return bl->data_align ? ALIGN(headroom, bl->data_align) : headroom; -+} -+ -+int fm_mac_dump_regs(struct mac_device *h_dev, char *buf, int n); -+int fm_mac_dump_rx_stats(struct mac_device *h_dev, char *buf, int n); -+int fm_mac_dump_tx_stats(struct mac_device *h_dev, char *buf, int n); -+ -+void dpaa_eth_sysfs_remove(struct device *dev); -+void dpaa_eth_sysfs_init(struct device *dev); -+int dpaa_eth_poll(struct napi_struct *napi, int budget); -+ -+void dpa_private_napi_del(struct net_device *net_dev); -+ -+/* Equivalent to a memset(0), but works faster */ -+static inline void clear_fd(struct qm_fd *fd) -+{ -+ fd->opaque_addr = 0; -+ fd->opaque = 0; -+ fd->cmd = 0; -+} -+ -+static inline int _dpa_tx_fq_to_id(const struct dpa_priv_s *priv, -+ struct qman_fq *tx_fq) -+{ -+ int i; -+ -+ for (i = 0; i < DPAA_ETH_TX_QUEUES; i++) -+ if (priv->egress_fqs[i] == tx_fq) -+ return i; -+ -+ return -EINVAL; -+} -+ -+static inline int __hot dpa_xmit(struct dpa_priv_s *priv, -+ struct rtnl_link_stats64 *percpu_stats, -+ struct qm_fd *fd, struct qman_fq *egress_fq, -+ struct qman_fq *conf_fq) -+{ -+ int err, i; -+ -+ if (fd->bpid == 0xff) -+ fd->cmd |= qman_fq_fqid(conf_fq); -+ -+ /* Trace this Tx fd */ -+ trace_dpa_tx_fd(priv->net_dev, egress_fq, fd); -+ -+ for (i = 0; i < 100000; i++) { -+ err = qman_enqueue(egress_fq, fd, 0); -+ if (err != -EBUSY) -+ break; -+ } -+ -+ if (unlikely(err < 0)) { -+ /* TODO differentiate b/w -EBUSY (EQCR full) and other codes? */ -+ percpu_stats->tx_errors++; -+ percpu_stats->tx_fifo_errors++; -+ return err; -+ } -+ -+ percpu_stats->tx_packets++; -+ percpu_stats->tx_bytes += dpa_fd_length(fd); -+ -+ return 0; -+} -+ -+/* Use multiple WQs for FQ assignment: -+ * - Tx Confirmation queues go to WQ1. -+ * - Rx Default, Tx and PCD queues go to WQ3 (no differentiation between -+ * Rx and Tx traffic, or between Rx Default and Rx PCD frames). -+ * - Rx Error and Tx Error queues go to WQ2 (giving them a better chance -+ * to be scheduled, in case there are many more FQs in WQ3). -+ * This ensures that Tx-confirmed buffers are timely released. In particular, -+ * it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they -+ * are greatly outnumbered by other FQs in the system (usually PCDs), while -+ * dequeue scheduling is round-robin. -+ */ -+static inline void _dpa_assign_wq(struct dpa_fq *fq) -+{ -+ switch (fq->fq_type) { -+ case FQ_TYPE_TX_CONFIRM: -+ case FQ_TYPE_TX_CONF_MQ: -+ fq->wq = 1; -+ break; -+ case FQ_TYPE_RX_DEFAULT: -+ case FQ_TYPE_TX: -+ fq->wq = 3; -+ break; -+ case FQ_TYPE_RX_ERROR: -+ case FQ_TYPE_TX_ERROR: -+ case FQ_TYPE_RX_PCD_HI_PRIO: -+ fq->wq = 2; -+ break; -+ case FQ_TYPE_RX_PCD: -+ fq->wq = 5; -+ break; -+ default: -+ WARN(1, "Invalid FQ type %d for FQID %d!\n", -+ fq->fq_type, fq->fqid); -+ } -+} -+ -+#ifdef CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE -+/* Use in lieu of skb_get_queue_mapping() */ -+#ifdef CONFIG_FMAN_PFC -+#define dpa_get_queue_mapping(skb) \ -+ (((skb)->priority < CONFIG_FMAN_PFC_COS_COUNT) ? \ -+ ((skb)->priority * dpa_num_cpus + smp_processor_id()) : \ -+ ((CONFIG_FMAN_PFC_COS_COUNT - 1) * \ -+ dpa_num_cpus + smp_processor_id())); -+ -+#else -+#define dpa_get_queue_mapping(skb) \ -+ raw_smp_processor_id() -+#endif -+#else -+/* Use the queue selected by XPS */ -+#define dpa_get_queue_mapping(skb) \ -+ skb_get_queue_mapping(skb) -+#endif -+ -+#ifdef CONFIG_PTP_1588_CLOCK_DPAA -+struct ptp_priv_s { -+ struct device_node *node; -+ struct platform_device *of_dev; -+ struct mac_device *mac_dev; -+}; -+extern struct ptp_priv_s ptp_priv; -+#endif -+ -+static inline void _dpa_bp_free_pf(void *addr) -+{ -+ put_page(virt_to_head_page(addr)); -+} -+ -+/* TODO: LS1043A SoC has a HW issue regarding FMan DMA transactions; The issue -+ * manifests itself at high traffic rates when frames exceed 4K memory -+ * boundaries; For the moment, we use a SW workaround to avoid frames larger -+ * than 4K or that exceed 4K alignements. -+ */ -+ -+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) -+#define DPAA_LS1043A_DMA_4K_ISSUE 1 -+#endif -+ -+#ifdef DPAA_LS1043A_DMA_4K_ISSUE -+#define HAS_DMA_ISSUE(start, size) \ -+ (((unsigned long)(start) ^ ((unsigned long)(start) + \ -+ (unsigned long)(size))) & ~0xFFF) -+ -+#define BOUNDARY_4K(start, size) (((unsigned long)(start) + \ -+ (unsigned long)(size)) & ~0xFFF) -+#endif /* DPAA_LS1043A_DMA_4K_ISSUE */ -+ -+#endif /* __DPA_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_base.c -@@ -0,0 +1,263 @@ -+/* Copyright 2008-2013 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifdef CONFIG_FSL_DPAA_ETH_DEBUG -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": %s:%hu:%s() " fmt, \ -+ KBUILD_BASENAME".c", __LINE__, __func__ -+#else -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": " fmt -+#endif -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "dpaa_eth.h" -+#include "dpaa_eth_common.h" -+#include "dpaa_eth_base.h" -+ -+#define DPA_DESCRIPTION "FSL DPAA Advanced drivers:" -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+ -+uint8_t advanced_debug = -1; -+module_param(advanced_debug, byte, S_IRUGO); -+MODULE_PARM_DESC(advanced_debug, "Module/Driver verbosity level"); -+EXPORT_SYMBOL(advanced_debug); -+ -+static int dpa_bp_cmp(const void *dpa_bp0, const void *dpa_bp1) -+{ -+ return ((struct dpa_bp *)dpa_bp0)->size - -+ ((struct dpa_bp *)dpa_bp1)->size; -+} -+ -+struct dpa_bp * __cold __must_check /* __attribute__((nonnull)) */ -+dpa_bp_probe(struct platform_device *_of_dev, size_t *count) -+{ -+ int i, lenp, na, ns, err; -+ struct device *dev; -+ struct device_node *dev_node; -+ const __be32 *bpool_cfg; -+ struct dpa_bp *dpa_bp; -+ u32 bpid; -+ -+ dev = &_of_dev->dev; -+ -+ *count = of_count_phandle_with_args(dev->of_node, -+ "fsl,bman-buffer-pools", NULL); -+ if (*count < 1) { -+ dev_err(dev, "missing fsl,bman-buffer-pools device tree entry\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ dpa_bp = devm_kzalloc(dev, *count * sizeof(*dpa_bp), GFP_KERNEL); -+ if (dpa_bp == NULL) { -+ dev_err(dev, "devm_kzalloc() failed\n"); -+ return ERR_PTR(-ENOMEM); -+ } -+ -+ dev_node = of_find_node_by_path("/"); -+ if (unlikely(dev_node == NULL)) { -+ dev_err(dev, "of_find_node_by_path(/) failed\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ na = of_n_addr_cells(dev_node); -+ ns = of_n_size_cells(dev_node); -+ -+ for (i = 0; i < *count; i++) { -+ of_node_put(dev_node); -+ -+ dev_node = of_parse_phandle(dev->of_node, -+ "fsl,bman-buffer-pools", i); -+ if (dev_node == NULL) { -+ dev_err(dev, "of_find_node_by_phandle() failed\n"); -+ return ERR_PTR(-EFAULT); -+ } -+ -+ if (unlikely(!of_device_is_compatible(dev_node, "fsl,bpool"))) { -+ dev_err(dev, -+ "!of_device_is_compatible(%s, fsl,bpool)\n", -+ dev_node->full_name); -+ dpa_bp = ERR_PTR(-EINVAL); -+ goto _return_of_node_put; -+ } -+ -+ err = of_property_read_u32(dev_node, "fsl,bpid", &bpid); -+ if (err) { -+ dev_err(dev, "Cannot find buffer pool ID in the device tree\n"); -+ dpa_bp = ERR_PTR(-EINVAL); -+ goto _return_of_node_put; -+ } -+ dpa_bp[i].bpid = (uint8_t)bpid; -+ -+ bpool_cfg = of_get_property(dev_node, "fsl,bpool-ethernet-cfg", -+ &lenp); -+ if (bpool_cfg && (lenp == (2 * ns + na) * sizeof(*bpool_cfg))) { -+ const uint32_t *seed_pool; -+ -+ dpa_bp[i].config_count = -+ (int)of_read_number(bpool_cfg, ns); -+ dpa_bp[i].size = -+ (size_t)of_read_number(bpool_cfg + ns, ns); -+ dpa_bp[i].paddr = -+ of_read_number(bpool_cfg + 2 * ns, na); -+ -+ seed_pool = of_get_property(dev_node, -+ "fsl,bpool-ethernet-seeds", &lenp); -+ dpa_bp[i].seed_pool = !!seed_pool; -+ -+ } else { -+ dev_err(dev, -+ "Missing/invalid fsl,bpool-ethernet-cfg device tree entry for node %s\n", -+ dev_node->full_name); -+ dpa_bp = ERR_PTR(-EINVAL); -+ goto _return_of_node_put; -+ } -+ } -+ -+ sort(dpa_bp, *count, sizeof(*dpa_bp), dpa_bp_cmp, NULL); -+ -+ return dpa_bp; -+ -+_return_of_node_put: -+ if (dev_node) -+ of_node_put(dev_node); -+ -+ return dpa_bp; -+} -+EXPORT_SYMBOL(dpa_bp_probe); -+ -+int dpa_bp_shared_port_seed(struct dpa_bp *bp) -+{ -+ void __iomem **ptr; -+ -+ /* In MAC-less and Shared-MAC scenarios the physical -+ * address of the buffer pool in device tree is set -+ * to 0 to specify that another entity (USDPAA) will -+ * allocate and seed the buffers -+ */ -+ if (!bp->paddr) -+ return 0; -+ -+ /* allocate memory region for buffers */ -+ devm_request_mem_region(bp->dev, bp->paddr, -+ bp->size * bp->config_count, KBUILD_MODNAME); -+ /* managed ioremap unmapping */ -+ ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL); -+ if (!ptr) -+ return -EIO; -+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) -+ bp->vaddr = ioremap_cache_ns(bp->paddr, bp->size * bp->config_count); -+#else -+ bp->vaddr = ioremap_prot(bp->paddr, bp->size * bp->config_count, 0); -+#endif -+ if (bp->vaddr == NULL) { -+ pr_err("Could not map memory for pool %d\n", bp->bpid); -+ devres_free(ptr); -+ return -EIO; -+ } -+ *ptr = bp->vaddr; -+ devres_add(bp->dev, ptr); -+ -+ /* seed pool with buffers from that memory region */ -+ if (bp->seed_pool) { -+ int count = bp->target_count; -+ dma_addr_t addr = bp->paddr; -+ -+ while (count) { -+ struct bm_buffer bufs[8]; -+ uint8_t num_bufs = 0; -+ -+ do { -+ BUG_ON(addr > 0xffffffffffffull); -+ bufs[num_bufs].bpid = bp->bpid; -+ bm_buffer_set64(&bufs[num_bufs++], addr); -+ addr += bp->size; -+ -+ } while (--count && (num_bufs < 8)); -+ -+ while (bman_release(bp->pool, bufs, num_bufs, 0)) -+ cpu_relax(); -+ } -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpa_bp_shared_port_seed); -+ -+int dpa_bp_create(struct net_device *net_dev, struct dpa_bp *dpa_bp, -+ size_t count) -+{ -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ int i; -+ -+ priv->dpa_bp = dpa_bp; -+ priv->bp_count = count; -+ -+ for (i = 0; i < count; i++) { -+ int err; -+ err = dpa_bp_alloc(&dpa_bp[i]); -+ if (err < 0) { -+ dpa_bp_free(priv); -+ priv->dpa_bp = NULL; -+ return err; -+ } -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpa_bp_create); -+ -+static int __init __cold dpa_advanced_load(void) -+{ -+ pr_info(DPA_DESCRIPTION "\n"); -+ -+ return 0; -+} -+module_init(dpa_advanced_load); -+ -+static void __exit __cold dpa_advanced_unload(void) -+{ -+ pr_debug(KBUILD_MODNAME ": -> %s:%s()\n", -+ KBUILD_BASENAME".c", __func__); -+ -+} -+module_exit(dpa_advanced_unload); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_base.h -@@ -0,0 +1,50 @@ -+/* Copyright 2008-2013 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __DPAA_ETH_BASE_H -+#define __DPAA_ETH_BASE_H -+ -+#include /* struct net_device */ -+#include /* struct bm_buffer */ -+#include /* struct platform_device */ -+#include /* struct hwtstamp_config */ -+ -+extern uint8_t advanced_debug; -+extern const struct dpa_fq_cbs_t shared_fq_cbs; -+extern int __hot dpa_shared_tx(struct sk_buff *skb, struct net_device *net_dev); -+ -+struct dpa_bp * __cold __must_check /* __attribute__((nonnull)) */ -+dpa_bp_probe(struct platform_device *_of_dev, size_t *count); -+int dpa_bp_create(struct net_device *net_dev, struct dpa_bp *dpa_bp, -+ size_t count); -+int dpa_bp_shared_port_seed(struct dpa_bp *bp); -+ -+#endif /* __DPAA_ETH_BASE_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_ceetm.c -@@ -0,0 +1,1719 @@ -+/* Copyright 2008-2016 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include "dpaa_eth_ceetm.h" -+ -+#define DPA_CEETM_DESCRIPTION "FSL DPAA CEETM qdisc" -+ -+const struct nla_policy ceetm_policy[TCA_CEETM_MAX + 1] = { -+ [TCA_CEETM_COPT] = { .len = sizeof(struct tc_ceetm_copt) }, -+ [TCA_CEETM_QOPS] = { .len = sizeof(struct tc_ceetm_qopt) }, -+}; -+ -+struct Qdisc_ops ceetm_qdisc_ops; -+ -+/* Obtain the DCP and the SP ids from the FMan port */ -+static void get_dcp_and_sp(struct net_device *dev, enum qm_dc_portal *dcp_id, -+ unsigned int *sp_id) -+{ -+ uint32_t channel; -+ t_LnxWrpFmPortDev *port_dev; -+ struct dpa_priv_s *dpa_priv = netdev_priv(dev); -+ struct mac_device *mac_dev = dpa_priv->mac_dev; -+ -+ port_dev = (t_LnxWrpFmPortDev *)mac_dev->port_dev[TX]; -+ channel = port_dev->txCh; -+ -+ *sp_id = channel & CHANNEL_SP_MASK; -+ pr_debug(KBUILD_BASENAME " : FM sub-portal ID %d\n", *sp_id); -+ -+ if (channel < DCP0_MAX_CHANNEL) { -+ *dcp_id = qm_dc_portal_fman0; -+ pr_debug(KBUILD_BASENAME " : DCP ID 0\n"); -+ } else { -+ *dcp_id = qm_dc_portal_fman1; -+ pr_debug(KBUILD_BASENAME " : DCP ID 1\n"); -+ } -+} -+ -+/* Enqueue Rejection Notification callback */ -+static void ceetm_ern(struct qman_portal *portal, struct qman_fq *fq, -+ const struct qm_mr_entry *msg) -+{ -+ struct net_device *net_dev; -+ struct ceetm_class *cls; -+ struct ceetm_class_stats *cstats = NULL; -+ const struct dpa_priv_s *dpa_priv; -+ struct dpa_percpu_priv_s *dpa_percpu_priv; -+ struct sk_buff *skb; -+ struct qm_fd fd = msg->ern.fd; -+ -+ net_dev = ((struct ceetm_fq *)fq)->net_dev; -+ dpa_priv = netdev_priv(net_dev); -+ dpa_percpu_priv = raw_cpu_ptr(dpa_priv->percpu_priv); -+ -+ /* Increment DPA counters */ -+ dpa_percpu_priv->stats.tx_dropped++; -+ dpa_percpu_priv->stats.tx_fifo_errors++; -+ -+ /* Increment CEETM counters */ -+ cls = ((struct ceetm_fq *)fq)->ceetm_cls; -+ switch (cls->type) { -+ case CEETM_PRIO: -+ cstats = this_cpu_ptr(cls->prio.cstats); -+ break; -+ case CEETM_WBFS: -+ cstats = this_cpu_ptr(cls->wbfs.cstats); -+ break; -+ } -+ -+ if (cstats) -+ cstats->ern_drop_count++; -+ -+ if (fd.bpid != 0xff) { -+ dpa_fd_release(net_dev, &fd); -+ return; -+ } -+ -+ skb = _dpa_cleanup_tx_fd(dpa_priv, &fd); -+ dev_kfree_skb_any(skb); -+} -+ -+/* Congestion State Change Notification callback */ -+static void ceetm_cscn(struct qm_ceetm_ccg *ccg, void *cb_ctx, int congested) -+{ -+ struct ceetm_fq *ceetm_fq = (struct ceetm_fq *)cb_ctx; -+ struct dpa_priv_s *dpa_priv = netdev_priv(ceetm_fq->net_dev); -+ struct ceetm_class *cls = ceetm_fq->ceetm_cls; -+ struct ceetm_class_stats *cstats = NULL; -+ -+ switch (cls->type) { -+ case CEETM_PRIO: -+ cstats = this_cpu_ptr(cls->prio.cstats); -+ break; -+ case CEETM_WBFS: -+ cstats = this_cpu_ptr(cls->wbfs.cstats); -+ break; -+ } -+ -+ if (congested) { -+ dpa_priv->cgr_data.congestion_start_jiffies = jiffies; -+ netif_tx_stop_all_queues(dpa_priv->net_dev); -+ dpa_priv->cgr_data.cgr_congested_count++; -+ if (cstats) -+ cstats->cgr_congested_count++; -+ } else { -+ dpa_priv->cgr_data.congested_jiffies += -+ (jiffies - dpa_priv->cgr_data.congestion_start_jiffies); -+ netif_tx_wake_all_queues(dpa_priv->net_dev); -+ } -+} -+ -+/* Allocate a ceetm fq */ -+static int ceetm_alloc_fq(struct ceetm_fq **fq, -+ struct net_device *dev, -+ struct ceetm_class *cls) -+{ -+ *fq = kzalloc(sizeof(**fq), GFP_KERNEL); -+ if (!*fq) -+ return -ENOMEM; -+ -+ (*fq)->net_dev = dev; -+ (*fq)->ceetm_cls = cls; -+ return 0; -+} -+ -+/* Configure a ceetm Class Congestion Group */ -+static int ceetm_config_ccg(struct qm_ceetm_ccg **ccg, -+ struct qm_ceetm_channel *channel, -+ unsigned int id, -+ struct ceetm_fq *fq, -+ u32 if_support) -+{ -+ int err; -+ u32 cs_th; -+ u16 ccg_mask; -+ struct qm_ceetm_ccg_params ccg_params; -+ -+ err = qman_ceetm_ccg_claim(ccg, channel, id, ceetm_cscn, fq); -+ if (err) -+ return err; -+ -+ /* Configure the count mode (frames/bytes), enable -+ * notifications, enable tail-drop, and configure the tail-drop -+ * mode and threshold */ -+ ccg_mask = QM_CCGR_WE_MODE | QM_CCGR_WE_CSCN_EN | -+ QM_CCGR_WE_TD_EN | QM_CCGR_WE_TD_MODE | -+ QM_CCGR_WE_TD_THRES; -+ -+ ccg_params.mode = 0; /* count bytes */ -+ ccg_params.cscn_en = 1; /* generate notifications */ -+ ccg_params.td_en = 1; /* enable tail-drop */ -+ ccg_params.td_mode = 1; /* tail-drop on threshold */ -+ -+ /* Configure the tail-drop threshold according to the link -+ * speed */ -+ if (if_support & SUPPORTED_10000baseT_Full) -+ cs_th = CONFIG_FSL_DPAA_CS_THRESHOLD_10G; -+ else -+ cs_th = CONFIG_FSL_DPAA_CS_THRESHOLD_1G; -+ qm_cgr_cs_thres_set64(&ccg_params.td_thres, cs_th, 1); -+ -+ err = qman_ceetm_ccg_set(*ccg, ccg_mask, &ccg_params); -+ if (err) -+ return err; -+ -+ return 0; -+} -+ -+/* Configure a ceetm Logical Frame Queue */ -+static int ceetm_config_lfq(struct qm_ceetm_cq *cq, struct ceetm_fq *fq, -+ struct qm_ceetm_lfq **lfq) -+{ -+ int err; -+ u64 context_a; -+ u32 context_b; -+ -+ err = qman_ceetm_lfq_claim(lfq, cq); -+ if (err) -+ return err; -+ -+ /* Get the former contexts in order to preserve context B */ -+ err = qman_ceetm_lfq_get_context(*lfq, &context_a, &context_b); -+ if (err) -+ return err; -+ -+ context_a = CEETM_CONTEXT_A; -+ err = qman_ceetm_lfq_set_context(*lfq, context_a, context_b); -+ if (err) -+ return err; -+ -+ (*lfq)->ern = ceetm_ern; -+ -+ err = qman_ceetm_create_fq(*lfq, &fq->fq); -+ if (err) -+ return err; -+ -+ return 0; -+} -+ -+/* Configure a prio ceetm class */ -+static int ceetm_config_prio_cls(struct ceetm_class *cls, struct net_device *dev, -+ struct qm_ceetm_channel *channel, unsigned int id) -+{ -+ int err; -+ struct dpa_priv_s *dpa_priv = netdev_priv(dev); -+ -+ err = ceetm_alloc_fq(&cls->prio.fq, dev, cls); -+ if (err) -+ return err; -+ -+ /* Claim and configure the CCG */ -+ err = ceetm_config_ccg(&cls->prio.ccg, channel, id, cls->prio.fq, -+ dpa_priv->mac_dev->if_support); -+ if (err) -+ return err; -+ -+ /* Claim and configure the CQ */ -+ err = qman_ceetm_cq_claim(&cls->prio.cq, channel, id, cls->prio.ccg); -+ if (err) -+ return err; -+ -+ if (cls->shaped) { -+ err = qman_ceetm_channel_set_cq_cr_eligibility(channel, id, 1); -+ if (err) -+ return err; -+ -+ err = qman_ceetm_channel_set_cq_er_eligibility(channel, id, 1); -+ if (err) -+ return err; -+ } -+ -+ /* Claim and configure a LFQ */ -+ err = ceetm_config_lfq(cls->prio.cq, cls->prio.fq, &cls->prio.lfq); -+ if (err) -+ return err; -+ -+ return 0; -+} -+ -+/* Configure a wbfs ceetm class */ -+static int ceetm_config_wbfs_cls(struct ceetm_class *cls, struct net_device *dev, -+ struct qm_ceetm_channel *channel, unsigned int id, int type) -+{ -+ int err; -+ struct dpa_priv_s *dpa_priv = netdev_priv(dev); -+ -+ err = ceetm_alloc_fq(&cls->wbfs.fq, dev, cls); -+ if (err) -+ return err; -+ -+ /* Claim and configure the CCG */ -+ err = ceetm_config_ccg(&cls->wbfs.ccg, channel, id, cls->wbfs.fq, -+ dpa_priv->mac_dev->if_support); -+ if (err) -+ return err; -+ -+ /* Claim and configure the CQ */ -+ if (type == WBFS_GRP_B) -+ err = qman_ceetm_cq_claim_B(&cls->wbfs.cq, channel, id, -+ cls->wbfs.ccg); -+ else -+ err = qman_ceetm_cq_claim_A(&cls->wbfs.cq, channel, id, -+ cls->wbfs.ccg); -+ if (err) -+ return err; -+ -+ /* Configure the CQ weight: real number mutiplied by 100 to get rid -+ * of the fraction */ -+ err = qman_ceetm_set_queue_weight_in_ratio(cls->wbfs.cq, -+ cls->wbfs.weight * 100); -+ if (err) -+ return err; -+ -+ /* Claim and configure a LFQ */ -+ err = ceetm_config_lfq(cls->wbfs.cq, cls->wbfs.fq, &cls->wbfs.lfq); -+ if (err) -+ return err; -+ -+ return 0; -+} -+ -+/* Find class in qdisc hash table using given handle */ -+static inline struct ceetm_class *ceetm_find(u32 handle, struct Qdisc *sch) -+{ -+ struct ceetm_qdisc *priv = qdisc_priv(sch); -+ struct Qdisc_class_common *clc; -+ -+ pr_debug(KBUILD_BASENAME " : %s : find class %X in qdisc %X\n", -+ __func__, handle, sch->handle); -+ -+ clc = qdisc_class_find(&priv->clhash, handle); -+ return clc ? container_of(clc, struct ceetm_class, common) : NULL; -+} -+ -+/* Insert a class in the qdisc's class hash */ -+static void ceetm_link_class(struct Qdisc *sch, -+ struct Qdisc_class_hash *clhash, -+ struct Qdisc_class_common *common) -+{ -+ sch_tree_lock(sch); -+ qdisc_class_hash_insert(clhash, common); -+ sch_tree_unlock(sch); -+ qdisc_class_hash_grow(sch, clhash); -+} -+ -+/* Destroy a ceetm class */ -+static void ceetm_cls_destroy(struct Qdisc *sch, struct ceetm_class *cl) -+{ -+ if (!cl) -+ return; -+ -+ pr_debug(KBUILD_BASENAME " : %s : destroy class %X from under %X\n", -+ __func__, cl->common.classid, sch->handle); -+ -+ switch (cl->type) { -+ case CEETM_ROOT: -+ if (cl->root.child) { -+ qdisc_destroy(cl->root.child); -+ cl->root.child = NULL; -+ } -+ -+ if (cl->root.ch && qman_ceetm_channel_release(cl->root.ch)) -+ pr_err(KBUILD_BASENAME -+ " : %s : error releasing the channel %d\n", -+ __func__, cl->root.ch->idx); -+ -+ break; -+ -+ case CEETM_PRIO: -+ if (cl->prio.child) { -+ qdisc_destroy(cl->prio.child); -+ cl->prio.child = NULL; -+ } -+ -+ if (cl->prio.lfq && qman_ceetm_lfq_release(cl->prio.lfq)) -+ pr_err(KBUILD_BASENAME -+ " : %s : error releasing the LFQ %d\n", -+ __func__, cl->prio.lfq->idx); -+ -+ if (cl->prio.cq && qman_ceetm_cq_release(cl->prio.cq)) -+ pr_err(KBUILD_BASENAME -+ " : %s : error releasing the CQ %d\n", -+ __func__, cl->prio.cq->idx); -+ -+ if (cl->prio.ccg && qman_ceetm_ccg_release(cl->prio.ccg)) -+ pr_err(KBUILD_BASENAME -+ " : %s : error releasing the CCG %d\n", -+ __func__, cl->prio.ccg->idx); -+ -+ if (cl->prio.fq) -+ kfree(cl->prio.fq); -+ -+ if (cl->prio.cstats) -+ free_percpu(cl->prio.cstats); -+ -+ break; -+ -+ case CEETM_WBFS: -+ if (cl->wbfs.lfq && qman_ceetm_lfq_release(cl->wbfs.lfq)) -+ pr_err(KBUILD_BASENAME -+ " : %s : error releasing the LFQ %d\n", -+ __func__, cl->wbfs.lfq->idx); -+ -+ if (cl->wbfs.cq && qman_ceetm_cq_release(cl->wbfs.cq)) -+ pr_err(KBUILD_BASENAME -+ " : %s : error releasing the CQ %d\n", -+ __func__, cl->wbfs.cq->idx); -+ -+ if (cl->wbfs.ccg && qman_ceetm_ccg_release(cl->wbfs.ccg)) -+ pr_err(KBUILD_BASENAME -+ " : %s : error releasing the CCG %d\n", -+ __func__, cl->wbfs.ccg->idx); -+ -+ if (cl->wbfs.fq) -+ kfree(cl->wbfs.fq); -+ -+ if (cl->wbfs.cstats) -+ free_percpu(cl->wbfs.cstats); -+ } -+ -+ tcf_destroy_chain(&cl->filter_list); -+ kfree(cl); -+} -+ -+/* Destroy a ceetm qdisc */ -+static void ceetm_destroy(struct Qdisc *sch) -+{ -+ unsigned int ntx, i; -+ struct hlist_node *next; -+ struct ceetm_class *cl; -+ struct ceetm_qdisc *priv = qdisc_priv(sch); -+ struct net_device *dev = qdisc_dev(sch); -+ -+ pr_debug(KBUILD_BASENAME " : %s : destroy qdisc %X\n", -+ __func__, sch->handle); -+ -+ /* All filters need to be removed before destroying the classes */ -+ tcf_destroy_chain(&priv->filter_list); -+ -+ for (i = 0; i < priv->clhash.hashsize; i++) { -+ hlist_for_each_entry(cl, &priv->clhash.hash[i], common.hnode) -+ tcf_destroy_chain(&cl->filter_list); -+ } -+ -+ for (i = 0; i < priv->clhash.hashsize; i++) { -+ hlist_for_each_entry_safe(cl, next, &priv->clhash.hash[i], -+ common.hnode) -+ ceetm_cls_destroy(sch, cl); -+ } -+ -+ qdisc_class_hash_destroy(&priv->clhash); -+ -+ switch (priv->type) { -+ case CEETM_ROOT: -+ dpa_disable_ceetm(dev); -+ -+ if (priv->root.lni && qman_ceetm_lni_release(priv->root.lni)) -+ pr_err(KBUILD_BASENAME -+ " : %s : error releasing the LNI %d\n", -+ __func__, priv->root.lni->idx); -+ -+ if (priv->root.sp && qman_ceetm_sp_release(priv->root.sp)) -+ pr_err(KBUILD_BASENAME -+ " : %s : error releasing the SP %d\n", -+ __func__, priv->root.sp->idx); -+ -+ if (priv->root.qstats) -+ free_percpu(priv->root.qstats); -+ -+ if (!priv->root.qdiscs) -+ break; -+ -+ /* Remove the pfifo qdiscs */ -+ for (ntx = 0; ntx < dev->num_tx_queues; ntx++) -+ if (priv->root.qdiscs[ntx]) -+ qdisc_destroy(priv->root.qdiscs[ntx]); -+ -+ kfree(priv->root.qdiscs); -+ break; -+ -+ case CEETM_PRIO: -+ if (priv->prio.parent) -+ priv->prio.parent->root.child = NULL; -+ break; -+ -+ case CEETM_WBFS: -+ if (priv->wbfs.parent) -+ priv->wbfs.parent->prio.child = NULL; -+ break; -+ } -+} -+ -+static int ceetm_dump(struct Qdisc *sch, struct sk_buff *skb) -+{ -+ struct Qdisc *qdisc; -+ unsigned int ntx, i; -+ struct nlattr *nest; -+ struct tc_ceetm_qopt qopt; -+ struct ceetm_qdisc_stats *qstats; -+ struct net_device *dev = qdisc_dev(sch); -+ struct ceetm_qdisc *priv = qdisc_priv(sch); -+ -+ pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle); -+ -+ sch_tree_lock(sch); -+ memset(&qopt, 0, sizeof(qopt)); -+ qopt.type = priv->type; -+ qopt.shaped = priv->shaped; -+ -+ switch (priv->type) { -+ case CEETM_ROOT: -+ /* Gather statistics from the underlying pfifo qdiscs */ -+ sch->q.qlen = 0; -+ memset(&sch->bstats, 0, sizeof(sch->bstats)); -+ memset(&sch->qstats, 0, sizeof(sch->qstats)); -+ -+ for (ntx = 0; ntx < dev->num_tx_queues; ntx++) { -+ qdisc = netdev_get_tx_queue(dev, ntx)->qdisc_sleeping; -+ sch->q.qlen += qdisc->q.qlen; -+ sch->bstats.bytes += qdisc->bstats.bytes; -+ sch->bstats.packets += qdisc->bstats.packets; -+ sch->qstats.qlen += qdisc->qstats.qlen; -+ sch->qstats.backlog += qdisc->qstats.backlog; -+ sch->qstats.drops += qdisc->qstats.drops; -+ sch->qstats.requeues += qdisc->qstats.requeues; -+ sch->qstats.overlimits += qdisc->qstats.overlimits; -+ } -+ -+ for_each_online_cpu(i) { -+ qstats = per_cpu_ptr(priv->root.qstats, i); -+ sch->qstats.drops += qstats->drops; -+ } -+ -+ qopt.rate = priv->root.rate; -+ qopt.ceil = priv->root.ceil; -+ qopt.overhead = priv->root.overhead; -+ break; -+ -+ case CEETM_PRIO: -+ qopt.qcount = priv->prio.qcount; -+ break; -+ -+ case CEETM_WBFS: -+ qopt.qcount = priv->wbfs.qcount; -+ qopt.cr = priv->wbfs.cr; -+ qopt.er = priv->wbfs.er; -+ break; -+ -+ default: -+ pr_err(KBUILD_BASENAME " : %s : invalid qdisc\n", __func__); -+ sch_tree_unlock(sch); -+ return -EINVAL; -+ } -+ -+ nest = nla_nest_start(skb, TCA_OPTIONS); -+ if (nest == NULL) -+ goto nla_put_failure; -+ if (nla_put(skb, TCA_CEETM_QOPS, sizeof(qopt), &qopt)) -+ goto nla_put_failure; -+ nla_nest_end(skb, nest); -+ -+ sch_tree_unlock(sch); -+ return skb->len; -+ -+nla_put_failure: -+ sch_tree_unlock(sch); -+ nla_nest_cancel(skb, nest); -+ return -EMSGSIZE; -+} -+ -+/* Configure a root ceetm qdisc */ -+static int ceetm_init_root(struct Qdisc *sch, struct ceetm_qdisc *priv, -+ struct tc_ceetm_qopt *qopt) -+{ -+ struct netdev_queue *dev_queue; -+ struct Qdisc *qdisc; -+ enum qm_dc_portal dcp_id; -+ unsigned int i, sp_id; -+ int err; -+ u64 bps; -+ struct qm_ceetm_sp *sp; -+ struct qm_ceetm_lni *lni; -+ struct net_device *dev = qdisc_dev(sch); -+ struct dpa_priv_s *dpa_priv = netdev_priv(dev); -+ struct mac_device *mac_dev = dpa_priv->mac_dev; -+ -+ pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle); -+ -+ /* Validate inputs */ -+ if (sch->parent != TC_H_ROOT) { -+ pr_err("CEETM: a root ceetm qdisc can not be attached to a class\n"); -+ tcf_destroy_chain(&priv->filter_list); -+ qdisc_class_hash_destroy(&priv->clhash); -+ return -EINVAL; -+ } -+ -+ if (!mac_dev) { -+ pr_err("CEETM: the interface is lacking a mac\n"); -+ err = -EINVAL; -+ goto err_init_root; -+ } -+ -+ /* pre-allocate underlying pfifo qdiscs */ -+ priv->root.qdiscs = kcalloc(dev->num_tx_queues, -+ sizeof(priv->root.qdiscs[0]), -+ GFP_KERNEL); -+ if (priv->root.qdiscs == NULL) { -+ err = -ENOMEM; -+ goto err_init_root; -+ } -+ -+ for (i = 0; i < dev->num_tx_queues; i++) { -+ dev_queue = netdev_get_tx_queue(dev, i); -+ qdisc = qdisc_create_dflt(dev_queue, &pfifo_qdisc_ops, -+ TC_H_MAKE(TC_H_MAJ(sch->handle), -+ TC_H_MIN(i + PFIFO_MIN_OFFSET))); -+ if (qdisc == NULL) { -+ err = -ENOMEM; -+ goto err_init_root; -+ } -+ -+ priv->root.qdiscs[i] = qdisc; -+ qdisc->flags |= TCQ_F_ONETXQUEUE; -+ } -+ -+ sch->flags |= TCQ_F_MQROOT; -+ -+ priv->root.qstats = alloc_percpu(struct ceetm_qdisc_stats); -+ if (!priv->root.qstats) { -+ pr_err(KBUILD_BASENAME " : %s : alloc_percpu() failed\n", -+ __func__); -+ err = -ENOMEM; -+ goto err_init_root; -+ } -+ -+ priv->shaped = qopt->shaped; -+ priv->root.rate = qopt->rate; -+ priv->root.ceil = qopt->ceil; -+ priv->root.overhead = qopt->overhead; -+ -+ /* Claim the SP */ -+ get_dcp_and_sp(dev, &dcp_id, &sp_id); -+ err = qman_ceetm_sp_claim(&sp, dcp_id, sp_id); -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to claim the SP\n", -+ __func__); -+ goto err_init_root; -+ } -+ -+ priv->root.sp = sp; -+ -+ /* Claim the LNI - will use the same id as the SP id since SPs 0-7 -+ * are connected to the TX FMan ports */ -+ err = qman_ceetm_lni_claim(&lni, dcp_id, sp_id); -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to claim the LNI\n", -+ __func__); -+ goto err_init_root; -+ } -+ -+ priv->root.lni = lni; -+ -+ err = qman_ceetm_sp_set_lni(sp, lni); -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to link the SP and " -+ "LNI\n", __func__); -+ goto err_init_root; -+ } -+ -+ lni->sp = sp; -+ -+ /* Configure the LNI shaper */ -+ if (priv->shaped) { -+ err = qman_ceetm_lni_enable_shaper(lni, 1, priv->root.overhead); -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to configure " -+ "the LNI shaper\n", __func__); -+ goto err_init_root; -+ } -+ -+ bps = priv->root.rate << 3; /* Bps -> bps */ -+ err = qman_ceetm_lni_set_commit_rate_bps(lni, bps, dev->mtu); -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to configure " -+ "the LNI shaper\n", __func__); -+ goto err_init_root; -+ } -+ -+ bps = priv->root.ceil << 3; /* Bps -> bps */ -+ err = qman_ceetm_lni_set_excess_rate_bps(lni, bps, dev->mtu); -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to configure " -+ "the LNI shaper\n", __func__); -+ goto err_init_root; -+ } -+ } -+ -+ /* TODO default configuration */ -+ -+ dpa_enable_ceetm(dev); -+ return 0; -+ -+err_init_root: -+ ceetm_destroy(sch); -+ return err; -+} -+ -+/* Configure a prio ceetm qdisc */ -+static int ceetm_init_prio(struct Qdisc *sch, struct ceetm_qdisc *priv, -+ struct tc_ceetm_qopt *qopt) -+{ -+ int err; -+ unsigned int i; -+ struct ceetm_class *parent_cl, *child_cl; -+ struct Qdisc *parent_qdisc; -+ struct net_device *dev = qdisc_dev(sch); -+ -+ pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle); -+ -+ if (sch->parent == TC_H_ROOT) { -+ pr_err("CEETM: a prio ceetm qdisc can not be root\n"); -+ err = -EINVAL; -+ goto err_init_prio; -+ } -+ -+ parent_qdisc = qdisc_lookup(dev, TC_H_MAJ(sch->parent)); -+ if (strcmp(parent_qdisc->ops->id, ceetm_qdisc_ops.id)) { -+ pr_err("CEETM: a ceetm qdisc can not be attached to other " -+ "qdisc/class types\n"); -+ err = -EINVAL; -+ goto err_init_prio; -+ } -+ -+ /* Obtain the parent root ceetm_class */ -+ parent_cl = ceetm_find(sch->parent, parent_qdisc); -+ -+ if (!parent_cl || parent_cl->type != CEETM_ROOT) { -+ pr_err("CEETM: a prio ceetm qdiscs can be added only under a " -+ "root ceetm class\n"); -+ err = -EINVAL; -+ goto err_init_prio; -+ } -+ -+ priv->prio.parent = parent_cl; -+ parent_cl->root.child = sch; -+ -+ priv->shaped = parent_cl->shaped; -+ priv->prio.qcount = qopt->qcount; -+ -+ /* Create and configure qcount child classes */ -+ for (i = 0; i < priv->prio.qcount; i++) { -+ child_cl = kzalloc(sizeof(*child_cl), GFP_KERNEL); -+ if (!child_cl) { -+ pr_err(KBUILD_BASENAME " : %s : kzalloc() failed\n", -+ __func__); -+ err = -ENOMEM; -+ goto err_init_prio; -+ } -+ -+ child_cl->prio.cstats = alloc_percpu(struct ceetm_class_stats); -+ if (!child_cl->prio.cstats) { -+ pr_err(KBUILD_BASENAME " : %s : alloc_percpu() failed\n", -+ __func__); -+ err = -ENOMEM; -+ goto err_init_prio_cls; -+ } -+ -+ child_cl->common.classid = TC_H_MAKE(sch->handle, (i + 1)); -+ child_cl->refcnt = 1; -+ child_cl->parent = sch; -+ child_cl->type = CEETM_PRIO; -+ child_cl->shaped = priv->shaped; -+ child_cl->prio.child = NULL; -+ -+ /* All shaped CQs have CR and ER enabled by default */ -+ child_cl->prio.cr = child_cl->shaped; -+ child_cl->prio.er = child_cl->shaped; -+ child_cl->prio.fq = NULL; -+ child_cl->prio.cq = NULL; -+ -+ /* Configure the corresponding hardware CQ */ -+ err = ceetm_config_prio_cls(child_cl, dev, -+ parent_cl->root.ch, i); -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to configure " -+ "the ceetm prio class %X\n", -+ __func__, -+ child_cl->common.classid); -+ goto err_init_prio_cls; -+ } -+ -+ /* Add class handle in Qdisc */ -+ ceetm_link_class(sch, &priv->clhash, &child_cl->common); -+ pr_debug(KBUILD_BASENAME " : %s : added ceetm prio class %X " -+ "associated with CQ %d and CCG %d\n", -+ __func__, -+ child_cl->common.classid, -+ child_cl->prio.cq->idx, -+ child_cl->prio.ccg->idx); -+ } -+ -+ return 0; -+ -+err_init_prio_cls: -+ ceetm_cls_destroy(sch, child_cl); -+err_init_prio: -+ ceetm_destroy(sch); -+ return err; -+} -+ -+/* Configure a wbfs ceetm qdisc */ -+static int ceetm_init_wbfs(struct Qdisc *sch, struct ceetm_qdisc *priv, -+ struct tc_ceetm_qopt *qopt) -+{ -+ int err, group_b, small_group; -+ unsigned int i, id, prio_a, prio_b; -+ struct ceetm_class *parent_cl, *child_cl, *root_cl; -+ struct Qdisc *parent_qdisc; -+ struct ceetm_qdisc *parent_priv; -+ struct qm_ceetm_channel *channel; -+ struct net_device *dev = qdisc_dev(sch); -+ -+ pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle); -+ -+ /* Validate inputs */ -+ if (sch->parent == TC_H_ROOT) { -+ pr_err("CEETM: a wbfs ceetm qdiscs can not be root\n"); -+ err = -EINVAL; -+ goto err_init_wbfs; -+ } -+ -+ /* Obtain the parent prio ceetm qdisc */ -+ parent_qdisc = qdisc_lookup(dev, TC_H_MAJ(sch->parent)); -+ if (strcmp(parent_qdisc->ops->id, ceetm_qdisc_ops.id)) { -+ pr_err("CEETM: a ceetm qdisc can not be attached to other " -+ "qdisc/class types\n"); -+ err = -EINVAL; -+ goto err_init_wbfs; -+ } -+ -+ /* Obtain the parent prio ceetm class */ -+ parent_cl = ceetm_find(sch->parent, parent_qdisc); -+ parent_priv = qdisc_priv(parent_qdisc); -+ -+ if (!parent_cl || parent_cl->type != CEETM_PRIO) { -+ pr_err("CEETM: a wbfs ceetm qdiscs can be added only under a " -+ "prio ceetm class\n"); -+ err = -EINVAL; -+ goto err_init_wbfs; -+ } -+ -+ priv->shaped = parent_cl->shaped; -+ -+ if (!priv->shaped && (qopt->cr || qopt->er)) { -+ pr_err("CEETM: CR/ER can be enabled only for shaped wbfs " -+ "ceetm qdiscs\n"); -+ err = -EINVAL; -+ goto err_init_wbfs; -+ } -+ -+ if (priv->shaped && !(qopt->cr || qopt->er)) { -+ pr_err("CEETM: either CR or ER must be enabled for shaped " -+ "wbfs ceetm qdiscs\n"); -+ err = -EINVAL; -+ goto err_init_wbfs; -+ } -+ -+ /* Obtain the parent root ceetm class */ -+ root_cl = parent_priv->prio.parent; -+ if ((root_cl->root.wbfs_grp_a && root_cl->root.wbfs_grp_b) -+ || root_cl->root.wbfs_grp_large) { -+ pr_err("CEETM: no more wbfs classes are available\n"); -+ err = -EINVAL; -+ goto err_init_wbfs; -+ } -+ -+ if ((root_cl->root.wbfs_grp_a || root_cl->root.wbfs_grp_b) -+ && qopt->qcount == CEETM_MAX_WBFS_QCOUNT) { -+ pr_err("CEETM: only %d wbfs classes are available\n", -+ CEETM_MIN_WBFS_QCOUNT); -+ err = -EINVAL; -+ goto err_init_wbfs; -+ } -+ -+ priv->wbfs.parent = parent_cl; -+ parent_cl->prio.child = sch; -+ -+ priv->wbfs.qcount = qopt->qcount; -+ priv->wbfs.cr = qopt->cr; -+ priv->wbfs.er = qopt->er; -+ -+ channel = root_cl->root.ch; -+ -+ /* Configure the hardware wbfs channel groups */ -+ if (priv->wbfs.qcount == CEETM_MAX_WBFS_QCOUNT) { -+ /* Configure the large group A */ -+ priv->wbfs.group_type = WBFS_GRP_LARGE; -+ small_group = false; -+ group_b = false; -+ prio_a = TC_H_MIN(parent_cl->common.classid) - 1; -+ prio_b = prio_a; -+ -+ } else if (root_cl->root.wbfs_grp_a) { -+ /* Configure the group B */ -+ priv->wbfs.group_type = WBFS_GRP_B; -+ -+ err = qman_ceetm_channel_get_group(channel, &small_group, -+ &prio_a, &prio_b); -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to get group " -+ "details\n", __func__); -+ goto err_init_wbfs; -+ } -+ -+ small_group = true; -+ group_b = true; -+ prio_b = TC_H_MIN(parent_cl->common.classid) - 1; -+ /* If group A isn't configured, configure it as group B */ -+ prio_a = prio_a ? : prio_b; -+ -+ } else { -+ /* Configure the small group A */ -+ priv->wbfs.group_type = WBFS_GRP_A; -+ -+ err = qman_ceetm_channel_get_group(channel, &small_group, -+ &prio_a, &prio_b); -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to get group " -+ "details\n", __func__); -+ goto err_init_wbfs; -+ } -+ -+ small_group = true; -+ group_b = false; -+ prio_a = TC_H_MIN(parent_cl->common.classid) - 1; -+ /* If group B isn't configured, configure it as group A */ -+ prio_b = prio_b ? : prio_a; -+ } -+ -+ err = qman_ceetm_channel_set_group(channel, small_group, prio_a, prio_b); -+ if (err) -+ goto err_init_wbfs; -+ -+ if (priv->shaped) { -+ err = qman_ceetm_channel_set_group_cr_eligibility(channel, -+ group_b, -+ priv->wbfs.cr); -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to set group " -+ "CR eligibility\n", __func__); -+ goto err_init_wbfs; -+ } -+ -+ err = qman_ceetm_channel_set_group_er_eligibility(channel, -+ group_b, -+ priv->wbfs.er); -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to set group " -+ "ER eligibility\n", __func__); -+ goto err_init_wbfs; -+ } -+ } -+ -+ /* Create qcount child classes */ -+ for (i = 0; i < priv->wbfs.qcount; i++) { -+ child_cl = kzalloc(sizeof(*child_cl), GFP_KERNEL); -+ if (!child_cl) { -+ pr_err(KBUILD_BASENAME " : %s : kzalloc() failed\n", -+ __func__); -+ err = -ENOMEM; -+ goto err_init_wbfs; -+ } -+ -+ child_cl->wbfs.cstats = alloc_percpu(struct ceetm_class_stats); -+ if (!child_cl->wbfs.cstats) { -+ pr_err(KBUILD_BASENAME " : %s : alloc_percpu() failed\n", -+ __func__); -+ err = -ENOMEM; -+ goto err_init_wbfs_cls; -+ } -+ -+ child_cl->common.classid = TC_H_MAKE(sch->handle, (i + 1)); -+ child_cl->refcnt = 1; -+ child_cl->parent = sch; -+ child_cl->type = CEETM_WBFS; -+ child_cl->shaped = priv->shaped; -+ child_cl->wbfs.fq = NULL; -+ child_cl->wbfs.cq = NULL; -+ child_cl->wbfs.weight = qopt->qweight[i]; -+ -+ if (priv->wbfs.group_type == WBFS_GRP_B) -+ id = WBFS_GRP_B_OFFSET + i; -+ else -+ id = WBFS_GRP_A_OFFSET + i; -+ -+ err = ceetm_config_wbfs_cls(child_cl, dev, channel, id, -+ priv->wbfs.group_type); -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to configure " -+ "the ceetm wbfs class %X\n", -+ __func__, -+ child_cl->common.classid); -+ goto err_init_wbfs_cls; -+ } -+ -+ /* Add class handle in Qdisc */ -+ ceetm_link_class(sch, &priv->clhash, &child_cl->common); -+ pr_debug(KBUILD_BASENAME " : %s : added ceetm wbfs class %X " -+ "associated with CQ %d and CCG %d\n", -+ __func__, -+ child_cl->common.classid, -+ child_cl->wbfs.cq->idx, -+ child_cl->wbfs.ccg->idx); -+ } -+ -+ /* Signal the root class that a group has been configured */ -+ switch (priv->wbfs.group_type) { -+ case WBFS_GRP_LARGE: -+ root_cl->root.wbfs_grp_large = true; -+ break; -+ case WBFS_GRP_A: -+ root_cl->root.wbfs_grp_a = true; -+ break; -+ case WBFS_GRP_B: -+ root_cl->root.wbfs_grp_b = true; -+ break; -+ } -+ -+ return 0; -+ -+err_init_wbfs_cls: -+ ceetm_cls_destroy(sch, child_cl); -+err_init_wbfs: -+ ceetm_destroy(sch); -+ return err; -+} -+ -+/* Configure a generic ceetm qdisc */ -+static int ceetm_init(struct Qdisc *sch, struct nlattr *opt) -+{ -+ struct tc_ceetm_qopt *qopt; -+ struct nlattr *tb[TCA_CEETM_QOPS + 1]; -+ int ret; -+ struct ceetm_qdisc *priv = qdisc_priv(sch); -+ struct net_device *dev = qdisc_dev(sch); -+ -+ pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle); -+ -+ if (!netif_is_multiqueue(dev)) -+ return -EOPNOTSUPP; -+ -+ ret = nla_parse_nested(tb, TCA_CEETM_QOPS, opt, ceetm_policy); -+ if (ret < 0) { -+ pr_err(KBUILD_BASENAME " : %s : tc error\n", __func__); -+ return ret; -+ } -+ -+ if (tb[TCA_CEETM_QOPS] == NULL) { -+ pr_err(KBUILD_BASENAME " : %s : tc error\n", __func__); -+ return -EINVAL; -+ } -+ -+ if (TC_H_MIN(sch->handle)) { -+ pr_err("CEETM: a qdisc should not have a minor\n"); -+ return -EINVAL; -+ } -+ -+ qopt = nla_data(tb[TCA_CEETM_QOPS]); -+ -+ /* Initialize the class hash list. Each qdisc has its own class hash */ -+ ret = qdisc_class_hash_init(&priv->clhash); -+ if (ret < 0) { -+ pr_err(KBUILD_BASENAME " : %s : qdisc_class_hash_init " -+ "failed\n", __func__); -+ return ret; -+ } -+ -+ priv->type = qopt->type; -+ -+ switch (priv->type) { -+ case CEETM_ROOT: -+ ret = ceetm_init_root(sch, priv, qopt); -+ break; -+ case CEETM_PRIO: -+ ret = ceetm_init_prio(sch, priv, qopt); -+ break; -+ case CEETM_WBFS: -+ ret = ceetm_init_wbfs(sch, priv, qopt); -+ break; -+ default: -+ pr_err(KBUILD_BASENAME " : %s : invalid qdisc\n", __func__); -+ ceetm_destroy(sch); -+ ret = -EINVAL; -+ } -+ -+ return ret; -+} -+ -+/* Attach the underlying pfifo qdiscs */ -+static void ceetm_attach(struct Qdisc *sch) -+{ -+ struct net_device *dev = qdisc_dev(sch); -+ struct ceetm_qdisc *priv = qdisc_priv(sch); -+ struct Qdisc *qdisc, *old_qdisc; -+ unsigned int i; -+ -+ pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle); -+ -+ for (i = 0; i < dev->num_tx_queues; i++) { -+ qdisc = priv->root.qdiscs[i]; -+ old_qdisc = dev_graft_qdisc(qdisc->dev_queue, qdisc); -+ if (old_qdisc) -+ qdisc_destroy(old_qdisc); -+ } -+} -+ -+static unsigned long ceetm_cls_get(struct Qdisc *sch, u32 classid) -+{ -+ struct ceetm_class *cl; -+ pr_debug(KBUILD_BASENAME " : %s : classid %X from qdisc %X\n", -+ __func__, classid, sch->handle); -+ cl = ceetm_find(classid, sch); -+ -+ if (cl) -+ cl->refcnt++; /* Will decrement in put() */ -+ return (unsigned long)cl; -+} -+ -+static void ceetm_cls_put(struct Qdisc *sch, unsigned long arg) -+{ -+ struct ceetm_class *cl = (struct ceetm_class *)arg; -+ pr_debug(KBUILD_BASENAME " : %s : classid %X from qdisc %X\n", -+ __func__, cl->common.classid, sch->handle); -+ cl->refcnt--; -+ -+ if (cl->refcnt == 0) -+ ceetm_cls_destroy(sch, cl); -+} -+ -+/* Add a ceetm root class or configure a ceetm prio class */ -+static int ceetm_cls_change(struct Qdisc *sch, u32 classid, -+ u32 parentid, struct nlattr **tca, -+ unsigned long *arg) -+{ -+ int err; -+ u64 bps; -+ struct ceetm_qdisc *priv; -+ struct ceetm_class *cl = (struct ceetm_class *)*arg; -+ struct nlattr *opt = tca[TCA_OPTIONS]; -+ struct nlattr *tb[__TCA_CEETM_MAX]; -+ struct tc_ceetm_copt *copt; -+ struct qm_ceetm_channel *channel; -+ struct net_device *dev = qdisc_dev(sch); -+ -+ pr_debug(KBUILD_BASENAME " : %s : classid %X under qdisc %X\n", -+ __func__, classid, sch->handle); -+ -+ if (strcmp(sch->ops->id, ceetm_qdisc_ops.id)) { -+ pr_err("CEETM: a ceetm class can not be attached to other " -+ "qdisc/class types\n"); -+ return -EINVAL; -+ } -+ -+ priv = qdisc_priv(sch); -+ -+ if (!opt) { -+ pr_err(KBUILD_BASENAME " : %s : tc error\n", __func__); -+ return -EINVAL; -+ } -+ -+ if (!cl && sch->handle != parentid) { -+ pr_err("CEETM: classes can be attached to the root ceetm " -+ "qdisc only\n"); -+ return -EINVAL; -+ } -+ -+ if (!cl && priv->type != CEETM_ROOT) { -+ pr_err("CEETM: only root ceetm classes can be attached to the " -+ "root ceetm qdisc\n"); -+ return -EINVAL; -+ } -+ -+ err = nla_parse_nested(tb, TCA_CEETM_COPT, opt, ceetm_policy); -+ if (err < 0) { -+ pr_err(KBUILD_BASENAME " : %s : tc error\n", __func__); -+ return -EINVAL; -+ } -+ -+ if (tb[TCA_CEETM_COPT] == NULL) { -+ pr_err(KBUILD_BASENAME " : %s : tc error\n", __func__); -+ return -EINVAL; -+ } -+ -+ if (TC_H_MIN(classid) >= PFIFO_MIN_OFFSET) { -+ pr_err("CEETM: only minors 0x01 to 0x20 can be used for ceetm " -+ "root classes\n"); -+ return -EINVAL; -+ } -+ -+ copt = nla_data(tb[TCA_CEETM_COPT]); -+ -+ /* Configure an existing ceetm prio class */ -+ if (cl) { -+ if (copt->type != CEETM_PRIO) { -+ pr_err("CEETM: only prio ceetm classes can be changed\n"); -+ return -EINVAL; -+ } -+ -+ if (!cl->shaped && (copt->cr || copt->er)) { -+ pr_err("CEETM: only shaped classes can have CR and " -+ "ER enabled\n"); -+ return -EINVAL; -+ } -+ -+ if (cl->prio.cr != (bool)copt->cr) -+ err = qman_ceetm_channel_set_cq_cr_eligibility( -+ cl->prio.cq->parent, -+ cl->prio.cq->idx, -+ copt->cr); -+ -+ if (!err && cl->prio.er != (bool)copt->er) -+ err = qman_ceetm_channel_set_cq_er_eligibility( -+ cl->prio.cq->parent, -+ cl->prio.cq->idx, -+ copt->er); -+ -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to configure " -+ "the ceetm prio class %X\n", -+ __func__, -+ cl->common.classid); -+ return err; -+ } -+ -+ cl->prio.cr = copt->cr; -+ cl->prio.er = copt->er; -+ return 0; -+ } -+ -+ /* Add a new root ceetm class */ -+ if (copt->type != CEETM_ROOT) { -+ pr_err("CEETM: only root ceetm classes can be attached to the " -+ "root ceetm qdisc\n"); -+ return -EINVAL; -+ } -+ -+ if (copt->shaped && !priv->shaped) { -+ pr_err("CEETM: can not add a shaped ceetm root class under an " -+ "unshaped ceetm root qdisc\n"); -+ return -EINVAL; -+ } -+ -+ cl = kzalloc(sizeof(*cl), GFP_KERNEL); -+ if (!cl) { -+ pr_err(KBUILD_BASENAME " : %s : kzalloc() failed\n", __func__); -+ return -ENOMEM; -+ } -+ -+ cl->type = copt->type; -+ cl->shaped = copt->shaped; -+ cl->root.rate = copt->rate; -+ cl->root.ceil = copt->ceil; -+ cl->root.tbl = copt->tbl; -+ -+ cl->common.classid = classid; -+ cl->refcnt = 1; -+ cl->parent = sch; -+ cl->root.child = NULL; -+ cl->root.wbfs_grp_a = false; -+ cl->root.wbfs_grp_b = false; -+ cl->root.wbfs_grp_large = false; -+ -+ /* Claim a CEETM channel */ -+ err = qman_ceetm_channel_claim(&channel, priv->root.lni); -+ if (err) { -+ pr_err(KBUILD_BASENAME " : %s : failed to claim a channel\n", -+ __func__); -+ goto claim_err; -+ } -+ -+ cl->root.ch = channel; -+ -+ if (cl->shaped) { -+ /* Configure the channel shaper */ -+ err = qman_ceetm_channel_enable_shaper(channel, 1); -+ if (err) -+ goto channel_err; -+ -+ bps = cl->root.rate << 3; /* Bps -> bps */ -+ err = qman_ceetm_channel_set_commit_rate_bps(channel, bps, -+ dev->mtu); -+ if (err) -+ goto channel_err; -+ -+ bps = cl->root.ceil << 3; /* Bps -> bps */ -+ err = qman_ceetm_channel_set_excess_rate_bps(channel, bps, -+ dev->mtu); -+ if (err) -+ goto channel_err; -+ -+ } else { -+ /* Configure the uFQ algorithm */ -+ err = qman_ceetm_channel_set_weight(channel, cl->root.tbl); -+ if (err) -+ goto channel_err; -+ } -+ -+ /* Add class handle in Qdisc */ -+ ceetm_link_class(sch, &priv->clhash, &cl->common); -+ -+ pr_debug(KBUILD_BASENAME " : %s : configured class %X associated with " -+ "channel %d\n", __func__, classid, channel->idx); -+ *arg = (unsigned long)cl; -+ return 0; -+ -+channel_err: -+ pr_err(KBUILD_BASENAME " : %s : failed to configure the channel %d\n", -+ __func__, channel->idx); -+ if (qman_ceetm_channel_release(channel)) -+ pr_err(KBUILD_BASENAME " : %s : failed to release the channel " -+ "%d\n", __func__, channel->idx); -+claim_err: -+ if (cl) { -+ kfree(cl); -+ } -+ return err; -+} -+ -+static void ceetm_cls_walk(struct Qdisc *sch, struct qdisc_walker *arg) -+{ -+ struct ceetm_qdisc *priv = qdisc_priv(sch); -+ struct ceetm_class *cl; -+ unsigned int i; -+ -+ pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle); -+ -+ if (arg->stop) -+ return; -+ -+ for (i = 0; i < priv->clhash.hashsize; i++) { -+ hlist_for_each_entry(cl, &priv->clhash.hash[i], common.hnode) { -+ if (arg->count < arg->skip) { -+ arg->count++; -+ continue; -+ } -+ if (arg->fn(sch, (unsigned long)cl, arg) < 0) { -+ arg->stop = 1; -+ return; -+ } -+ arg->count++; -+ } -+ } -+} -+ -+static int ceetm_cls_dump(struct Qdisc *sch, unsigned long arg, -+ struct sk_buff *skb, struct tcmsg *tcm) -+{ -+ struct ceetm_class *cl = (struct ceetm_class *)arg; -+ struct nlattr *nest; -+ struct tc_ceetm_copt copt; -+ -+ pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n", -+ __func__, cl->common.classid, sch->handle); -+ -+ sch_tree_lock(sch); -+ -+ tcm->tcm_parent = ((struct Qdisc *)cl->parent)->handle; -+ tcm->tcm_handle = cl->common.classid; -+ -+ memset(&copt, 0, sizeof(copt)); -+ -+ copt.shaped = cl->shaped; -+ copt.type = cl->type; -+ -+ switch (cl->type) { -+ case CEETM_ROOT: -+ if (cl->root.child) -+ tcm->tcm_info = cl->root.child->handle; -+ -+ copt.rate = cl->root.rate; -+ copt.ceil = cl->root.ceil; -+ copt.tbl = cl->root.tbl; -+ break; -+ -+ case CEETM_PRIO: -+ if (cl->prio.child) -+ tcm->tcm_info = cl->prio.child->handle; -+ -+ copt.cr = cl->prio.cr; -+ copt.er = cl->prio.er; -+ break; -+ -+ case CEETM_WBFS: -+ copt.weight = cl->wbfs.weight; -+ break; -+ } -+ -+ nest = nla_nest_start(skb, TCA_OPTIONS); -+ if (nest == NULL) -+ goto nla_put_failure; -+ if (nla_put(skb, TCA_CEETM_COPT, sizeof(copt), &copt)) -+ goto nla_put_failure; -+ nla_nest_end(skb, nest); -+ sch_tree_unlock(sch); -+ return skb->len; -+ -+nla_put_failure: -+ sch_tree_unlock(sch); -+ nla_nest_cancel(skb, nest); -+ return -EMSGSIZE; -+} -+ -+static int ceetm_cls_delete(struct Qdisc *sch, unsigned long arg) -+{ -+ struct ceetm_qdisc *priv = qdisc_priv(sch); -+ struct ceetm_class *cl = (struct ceetm_class *)arg; -+ -+ pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n", -+ __func__, cl->common.classid, sch->handle); -+ -+ sch_tree_lock(sch); -+ qdisc_class_hash_remove(&priv->clhash, &cl->common); -+ cl->refcnt--; -+ -+ /* The refcnt should be at least 1 since we have incremented it in -+ get(). Will decrement again in put() where we will call destroy() -+ to actually free the memory if it reaches 0. */ -+ BUG_ON(cl->refcnt == 0); -+ -+ sch_tree_unlock(sch); -+ return 0; -+} -+ -+/* Get the class' child qdisc, if any */ -+static struct Qdisc *ceetm_cls_leaf(struct Qdisc *sch, unsigned long arg) -+{ -+ struct ceetm_class *cl = (struct ceetm_class *)arg; -+ -+ pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n", -+ __func__, cl->common.classid, sch->handle); -+ -+ switch (cl->type) { -+ case CEETM_ROOT: -+ return cl->root.child; -+ break; -+ -+ case CEETM_PRIO: -+ return cl->prio.child; -+ break; -+ } -+ -+ return NULL; -+} -+ -+static int ceetm_cls_graft(struct Qdisc *sch, unsigned long arg, -+ struct Qdisc *new, struct Qdisc **old) -+{ -+ if (new && strcmp(new->ops->id, ceetm_qdisc_ops.id)) { -+ pr_err("CEETM: only ceetm qdiscs can be attached to ceetm " -+ "classes\n"); -+ return -EOPNOTSUPP; -+ } -+ -+ return 0; -+} -+ -+static int ceetm_cls_dump_stats(struct Qdisc *sch, unsigned long arg, -+ struct gnet_dump *d) -+{ -+ unsigned int i; -+ struct ceetm_class *cl = (struct ceetm_class *)arg; -+ struct gnet_stats_basic_packed tmp_bstats; -+ struct ceetm_class_stats *cstats = NULL; -+ struct qm_ceetm_cq *cq = NULL; -+ struct tc_ceetm_xstats xstats; -+ -+ memset(&xstats, 0, sizeof(xstats)); -+ memset(&tmp_bstats, 0, sizeof(tmp_bstats)); -+ -+ switch (cl->type) { -+ case CEETM_ROOT: -+ return 0; -+ case CEETM_PRIO: -+ cq = cl->prio.cq; -+ break; -+ case CEETM_WBFS: -+ cq = cl->wbfs.cq; -+ break; -+ } -+ -+ for_each_online_cpu(i) { -+ switch (cl->type) { -+ case CEETM_PRIO: -+ cstats = per_cpu_ptr(cl->prio.cstats, i); -+ break; -+ case CEETM_WBFS: -+ cstats = per_cpu_ptr(cl->wbfs.cstats, i); -+ break; -+ } -+ -+ if (cstats) { -+ xstats.ern_drop_count += cstats->ern_drop_count; -+ xstats.cgr_congested_count += cstats->cgr_congested_count; -+ tmp_bstats.bytes += cstats->bstats.bytes; -+ tmp_bstats.packets += cstats->bstats.packets; -+ } -+ } -+ -+ if (gnet_stats_copy_basic(d, NULL, &tmp_bstats) < 0) -+ return -1; -+ -+ if (cq && qman_ceetm_cq_get_dequeue_statistics(cq, 0, -+ &xstats.frame_count, &xstats.byte_count)) -+ return -1; -+ -+ return gnet_stats_copy_app(d, &xstats, sizeof(xstats)); -+} -+ -+static struct tcf_proto **ceetm_tcf_chain(struct Qdisc *sch, unsigned long arg) -+{ -+ struct ceetm_qdisc *priv = qdisc_priv(sch); -+ struct ceetm_class *cl = (struct ceetm_class *)arg; -+ struct tcf_proto **fl = cl ? &cl->filter_list : &priv->filter_list; -+ -+ pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n", __func__, -+ cl ? cl->common.classid : 0, sch->handle); -+ return fl; -+} -+ -+static unsigned long ceetm_tcf_bind(struct Qdisc *sch, unsigned long parent, -+ u32 classid) -+{ -+ struct ceetm_class *cl = ceetm_find(classid, sch); -+ pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n", __func__, -+ cl ? cl->common.classid : 0, sch->handle); -+ return (unsigned long)cl; -+} -+ -+static void ceetm_tcf_unbind(struct Qdisc *sch, unsigned long arg) -+{ -+ struct ceetm_class *cl = (struct ceetm_class *)arg; -+ pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n", __func__, -+ cl ? cl->common.classid : 0, sch->handle); -+} -+ -+const struct Qdisc_class_ops ceetm_cls_ops = { -+ .graft = ceetm_cls_graft, -+ .leaf = ceetm_cls_leaf, -+ .get = ceetm_cls_get, -+ .put = ceetm_cls_put, -+ .change = ceetm_cls_change, -+ .delete = ceetm_cls_delete, -+ .walk = ceetm_cls_walk, -+ .tcf_chain = ceetm_tcf_chain, -+ .bind_tcf = ceetm_tcf_bind, -+ .unbind_tcf = ceetm_tcf_unbind, -+ .dump = ceetm_cls_dump, -+ .dump_stats = ceetm_cls_dump_stats, -+}; -+ -+struct Qdisc_ops ceetm_qdisc_ops __read_mostly = { -+ .id = "ceetm", -+ .priv_size = sizeof(struct ceetm_qdisc), -+ .cl_ops = &ceetm_cls_ops, -+ .init = ceetm_init, -+ .destroy = ceetm_destroy, -+ .dump = ceetm_dump, -+ .attach = ceetm_attach, -+ .owner = THIS_MODULE, -+}; -+ -+/* Run the filters and classifiers attached to the qdisc on the provided skb */ -+static struct ceetm_class *ceetm_classify(struct sk_buff *skb, struct Qdisc *sch, -+ int *qerr, bool *act_drop) -+{ -+ struct ceetm_qdisc *priv = qdisc_priv(sch); -+ struct ceetm_class *cl = NULL, *wbfs_cl; -+ struct tcf_result res; -+ struct tcf_proto *tcf; -+ int result; -+ -+ *qerr = NET_XMIT_SUCCESS | __NET_XMIT_BYPASS; -+ tcf = priv->filter_list; -+ while (tcf && (result = tc_classify(skb, tcf, &res)) >= 0) { -+#ifdef CONFIG_NET_CLS_ACT -+ switch (result) { -+ case TC_ACT_QUEUED: -+ case TC_ACT_STOLEN: -+ *qerr = NET_XMIT_SUCCESS | __NET_XMIT_STOLEN; -+ case TC_ACT_SHOT: -+ /* No valid class found due to action */ -+ *act_drop = true; -+ return NULL; -+ } -+#endif -+ cl = (void *)res.class; -+ if (!cl) { -+ if (res.classid == sch->handle) { -+ /* The filter leads to the qdisc */ -+ /* TODO default qdisc */ -+ return NULL; -+ } -+ -+ cl = ceetm_find(res.classid, sch); -+ if (!cl) -+ /* The filter leads to an invalid class */ -+ break; -+ } -+ -+ /* The class might have its own filters attached */ -+ tcf = cl->filter_list; -+ } -+ -+ if (!cl) { -+ /* No valid class found */ -+ /* TODO default qdisc */ -+ return NULL; -+ } -+ -+ switch (cl->type) { -+ case CEETM_ROOT: -+ if (cl->root.child) { -+ /* Run the prio qdisc classifiers */ -+ return ceetm_classify(skb, cl->root.child, qerr, -+ act_drop); -+ } else { -+ /* The root class does not have a child prio qdisc */ -+ /* TODO default qdisc */ -+ return NULL; -+ } -+ case CEETM_PRIO: -+ if (cl->prio.child) { -+ /* If filters lead to a wbfs class, return it. -+ * Otherwise, return the prio class */ -+ wbfs_cl = ceetm_classify(skb, cl->prio.child, qerr, -+ act_drop); -+ /* A NULL result might indicate either an erroneous -+ * filter, or no filters at all. We will assume the -+ * latter */ -+ return wbfs_cl ? : cl; -+ } -+ } -+ -+ /* For wbfs and childless prio classes, return the class directly */ -+ return cl; -+} -+ -+int __hot ceetm_tx(struct sk_buff *skb, struct net_device *net_dev) -+{ -+ int ret; -+ bool act_drop = false; -+ struct Qdisc *sch = net_dev->qdisc; -+ struct ceetm_class *cl; -+ struct dpa_priv_s *priv_dpa; -+ struct qman_fq *egress_fq, *conf_fq; -+ struct ceetm_qdisc *priv = qdisc_priv(sch); -+ struct ceetm_qdisc_stats *qstats = this_cpu_ptr(priv->root.qstats); -+ struct ceetm_class_stats *cstats; -+ const int queue_mapping = dpa_get_queue_mapping(skb); -+ spinlock_t *root_lock = qdisc_lock(sch); -+ -+ spin_lock(root_lock); -+ cl = ceetm_classify(skb, sch, &ret, &act_drop); -+ spin_unlock(root_lock); -+ -+#ifdef CONFIG_NET_CLS_ACT -+ if (act_drop) { -+ if (ret & __NET_XMIT_BYPASS) -+ qstats->drops++; -+ goto drop; -+ } -+#endif -+ /* TODO default class */ -+ if (unlikely(!cl)) { -+ qstats->drops++; -+ goto drop; -+ } -+ -+ priv_dpa = netdev_priv(net_dev); -+ conf_fq = priv_dpa->conf_fqs[queue_mapping]; -+ -+ /* Choose the proper tx fq and update the basic stats (bytes and -+ * packets sent by the class) */ -+ switch (cl->type) { -+ case CEETM_PRIO: -+ egress_fq = &(cl->prio.fq->fq); -+ cstats = this_cpu_ptr(cl->prio.cstats); -+ break; -+ case CEETM_WBFS: -+ egress_fq = &(cl->wbfs.fq->fq); -+ cstats = this_cpu_ptr(cl->wbfs.cstats); -+ break; -+ default: -+ qstats->drops++; -+ goto drop; -+ } -+ -+ bstats_update(&cstats->bstats, skb); -+ return dpa_tx_extended(skb, net_dev, egress_fq, conf_fq); -+ -+drop: -+ dev_kfree_skb_any(skb); -+ return NET_XMIT_SUCCESS; -+} -+ -+static int __init ceetm_register(void) -+{ -+ int _errno = 0; -+ -+ pr_info(KBUILD_MODNAME ": " DPA_CEETM_DESCRIPTION "\n"); -+ -+ _errno = register_qdisc(&ceetm_qdisc_ops); -+ if (unlikely(_errno)) -+ pr_err(KBUILD_MODNAME -+ ": %s:%hu:%s(): register_qdisc() = %d\n", -+ KBUILD_BASENAME".c", __LINE__, __func__, _errno); -+ -+ return _errno; -+} -+ -+static void __exit ceetm_unregister(void) -+{ -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+ -+ unregister_qdisc(&ceetm_qdisc_ops); -+} -+ -+module_init(ceetm_register); -+module_exit(ceetm_unregister); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_ceetm.h -@@ -0,0 +1,230 @@ -+/* Copyright 2008-2016 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __DPAA_ETH_CEETM_H -+#define __DPAA_ETH_CEETM_H -+ -+#include -+#include -+#include -+ -+#include "mac.h" -+#include "dpaa_eth_common.h" -+ -+/* Mask to determine the sub-portal id from a channel number */ -+#define CHANNEL_SP_MASK 0x1f -+/* The number of the last channel that services DCP0, connected to FMan 0. -+ * Value validated for B4 and T series platforms. -+ */ -+#define DCP0_MAX_CHANNEL 0x80f -+/* A2V=1 - field A2 is valid -+ * A0V=1 - field A0 is valid - enables frame confirmation -+ * OVOM=1 - override operation mode bits with values from A2 -+ * EBD=1 - external buffers are deallocated at the end of the FMan flow -+ * NL=0 - the BMI releases all the internal buffers -+ */ -+#define CEETM_CONTEXT_A 0x1a00000080000000 -+ -+/* For functional purposes, there are num_tx_queues pfifo qdiscs through which -+ * frames reach the driver. Their handles start from 1:21. Handles 1:1 to 1:20 -+ * are reserved for the maximum 32 CEETM channels (majors and minors are in -+ * hex). -+ */ -+#define PFIFO_MIN_OFFSET 0x21 -+ -+/* A maximum of 8 CQs can be linked to a CQ channel or to a WBFS scheduler. */ -+#define CEETM_MAX_PRIO_QCOUNT 8 -+#define CEETM_MAX_WBFS_QCOUNT 8 -+#define CEETM_MIN_WBFS_QCOUNT 4 -+ -+/* The id offsets of the CQs belonging to WBFS groups (ids 8-11/15 for group A -+ * and/or 12-15 for group B). -+ */ -+#define WBFS_GRP_A_OFFSET 8 -+#define WBFS_GRP_B_OFFSET 12 -+ -+#define WBFS_GRP_A 1 -+#define WBFS_GRP_B 2 -+#define WBFS_GRP_LARGE 3 -+ -+enum { -+ TCA_CEETM_UNSPEC, -+ TCA_CEETM_COPT, -+ TCA_CEETM_QOPS, -+ __TCA_CEETM_MAX, -+}; -+ -+/* CEETM configuration types */ -+enum { -+ CEETM_ROOT = 1, -+ CEETM_PRIO, -+ CEETM_WBFS -+}; -+ -+#define TCA_CEETM_MAX (__TCA_CEETM_MAX - 1) -+extern const struct nla_policy ceetm_policy[TCA_CEETM_MAX + 1]; -+ -+struct ceetm_class; -+struct ceetm_qdisc_stats; -+struct ceetm_class_stats; -+ -+struct ceetm_fq { -+ struct qman_fq fq; -+ struct net_device *net_dev; -+ struct ceetm_class *ceetm_cls; -+}; -+ -+struct root_q { -+ struct Qdisc **qdiscs; -+ __u16 overhead; -+ __u32 rate; -+ __u32 ceil; -+ struct qm_ceetm_sp *sp; -+ struct qm_ceetm_lni *lni; -+ struct ceetm_qdisc_stats __percpu *qstats; -+}; -+ -+struct prio_q { -+ __u16 qcount; -+ struct ceetm_class *parent; -+}; -+ -+struct wbfs_q { -+ __u16 qcount; -+ int group_type; -+ struct ceetm_class *parent; -+ __u16 cr; -+ __u16 er; -+}; -+ -+struct ceetm_qdisc { -+ int type; /* LNI/CHNL/WBFS */ -+ bool shaped; -+ union { -+ struct root_q root; -+ struct prio_q prio; -+ struct wbfs_q wbfs; -+ }; -+ struct Qdisc_class_hash clhash; -+ struct tcf_proto *filter_list; /* qdisc attached filters */ -+}; -+ -+/* CEETM Qdisc configuration parameters */ -+struct tc_ceetm_qopt { -+ __u32 type; -+ __u16 shaped; -+ __u16 qcount; -+ __u16 overhead; -+ __u32 rate; -+ __u32 ceil; -+ __u16 cr; -+ __u16 er; -+ __u8 qweight[CEETM_MAX_WBFS_QCOUNT]; -+}; -+ -+struct root_c { -+ unsigned int rate; -+ unsigned int ceil; -+ unsigned int tbl; -+ bool wbfs_grp_a; -+ bool wbfs_grp_b; -+ bool wbfs_grp_large; -+ struct Qdisc *child; -+ struct qm_ceetm_channel *ch; -+}; -+ -+struct prio_c { -+ bool cr; -+ bool er; -+ struct ceetm_fq *fq; /* Hardware FQ instance Handle */ -+ struct qm_ceetm_lfq *lfq; -+ struct qm_ceetm_cq *cq; /* Hardware Class Queue instance Handle */ -+ struct qm_ceetm_ccg *ccg; -+ /* only one wbfs can be linked to one priority CQ */ -+ struct Qdisc *child; -+ struct ceetm_class_stats __percpu *cstats; -+}; -+ -+struct wbfs_c { -+ __u8 weight; /* The weight of the class between 1 and 248 */ -+ struct ceetm_fq *fq; /* Hardware FQ instance Handle */ -+ struct qm_ceetm_lfq *lfq; -+ struct qm_ceetm_cq *cq; /* Hardware Class Queue instance Handle */ -+ struct qm_ceetm_ccg *ccg; -+ struct ceetm_class_stats __percpu *cstats; -+}; -+ -+struct ceetm_class { -+ struct Qdisc_class_common common; -+ int refcnt; /* usage count of this class */ -+ struct tcf_proto *filter_list; /* class attached filters */ -+ struct Qdisc *parent; -+ bool shaped; -+ int type; /* ROOT/PRIO/WBFS */ -+ union { -+ struct root_c root; -+ struct prio_c prio; -+ struct wbfs_c wbfs; -+ }; -+}; -+ -+/* CEETM Class configuration parameters */ -+struct tc_ceetm_copt { -+ __u32 type; -+ __u16 shaped; -+ __u32 rate; -+ __u32 ceil; -+ __u16 tbl; -+ __u16 cr; -+ __u16 er; -+ __u8 weight; -+}; -+ -+/* CEETM stats */ -+struct ceetm_qdisc_stats { -+ __u32 drops; -+}; -+ -+struct ceetm_class_stats { -+ struct gnet_stats_basic_packed bstats; -+ __u32 ern_drop_count; -+ __u32 cgr_congested_count; -+}; -+ -+struct tc_ceetm_xstats { -+ __u32 ern_drop_count; -+ __u32 cgr_congested_count; -+ __u64 frame_count; -+ __u64 byte_count; -+}; -+ -+int __hot ceetm_tx(struct sk_buff *skb, struct net_device *net_dev); -+#endif ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_common.c -@@ -0,0 +1,1787 @@ -+/* Copyright 2008-2013 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include /* vlan_eth_hdr */ -+#include "dpaa_eth.h" -+#include "dpaa_eth_common.h" -+#ifdef CONFIG_FSL_DPAA_1588 -+#include "dpaa_1588.h" -+#endif -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+#include "dpaa_debugfs.h" -+#endif /* CONFIG_FSL_DPAA_DBG_LOOP */ -+#include "mac.h" -+ -+/* DPAA platforms benefit from hardware-assisted queue management */ -+#define DPA_NETIF_FEATURES NETIF_F_HW_ACCEL_MQ -+ -+/* Size in bytes of the FQ taildrop threshold */ -+#define DPA_FQ_TD 0x200000 -+ -+#ifdef CONFIG_PTP_1588_CLOCK_DPAA -+struct ptp_priv_s ptp_priv; -+#endif -+ -+static struct dpa_bp *dpa_bp_array[64]; -+ -+int dpa_max_frm; -+EXPORT_SYMBOL(dpa_max_frm); -+ -+int dpa_rx_extra_headroom; -+EXPORT_SYMBOL(dpa_rx_extra_headroom); -+ -+int dpa_num_cpus = NR_CPUS; -+ -+static const struct fqid_cell tx_confirm_fqids[] = { -+ {0, DPAA_ETH_TX_QUEUES} -+}; -+ -+static struct fqid_cell default_fqids[][3] = { -+ [RX] = { {0, 1}, {0, 1}, {0, DPAA_ETH_RX_QUEUES} }, -+ [TX] = { {0, 1}, {0, 1}, {0, DPAA_ETH_TX_QUEUES} } -+}; -+ -+static const char fsl_qman_frame_queues[][25] = { -+ [RX] = "fsl,qman-frame-queues-rx", -+ [TX] = "fsl,qman-frame-queues-tx" -+}; -+#ifdef CONFIG_FSL_DPAA_HOOKS -+/* A set of callbacks for hooking into the fastpath at different points. */ -+struct dpaa_eth_hooks_s dpaa_eth_hooks; -+EXPORT_SYMBOL(dpaa_eth_hooks); -+/* This function should only be called on the probe paths, since it makes no -+ * effort to guarantee consistency of the destination hooks structure. -+ */ -+void fsl_dpaa_eth_set_hooks(struct dpaa_eth_hooks_s *hooks) -+{ -+ if (hooks) -+ dpaa_eth_hooks = *hooks; -+ else -+ pr_err("NULL pointer to hooks!\n"); -+} -+EXPORT_SYMBOL(fsl_dpaa_eth_set_hooks); -+#endif -+ -+int dpa_netdev_init(struct net_device *net_dev, -+ const uint8_t *mac_addr, -+ uint16_t tx_timeout) -+{ -+ int err; -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ struct device *dev = net_dev->dev.parent; -+ -+ net_dev->hw_features |= DPA_NETIF_FEATURES; -+ -+ net_dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; -+ -+ net_dev->features |= net_dev->hw_features; -+ net_dev->vlan_features = net_dev->features; -+ -+ memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len); -+ memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len); -+ -+ net_dev->ethtool_ops = &dpa_ethtool_ops; -+ -+ net_dev->needed_headroom = priv->tx_headroom; -+ net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout); -+ -+ err = register_netdev(net_dev); -+ if (err < 0) { -+ dev_err(dev, "register_netdev() = %d\n", err); -+ return err; -+ } -+ -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+ /* create debugfs entry for this net_device */ -+ err = dpa_netdev_debugfs_create(net_dev); -+ if (err) { -+ unregister_netdev(net_dev); -+ return err; -+ } -+#endif /* CONFIG_FSL_DPAA_DBG_LOOP */ -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpa_netdev_init); -+ -+int __cold dpa_start(struct net_device *net_dev) -+{ -+ int err, i; -+ struct dpa_priv_s *priv; -+ struct mac_device *mac_dev; -+ -+ priv = netdev_priv(net_dev); -+ mac_dev = priv->mac_dev; -+ -+ err = mac_dev->init_phy(net_dev, priv->mac_dev); -+ if (err < 0) { -+ if (netif_msg_ifup(priv)) -+ netdev_err(net_dev, "init_phy() = %d\n", err); -+ return err; -+ } -+ -+ for_each_port_device(i, mac_dev->port_dev) { -+ err = fm_port_enable(mac_dev->port_dev[i]); -+ if (err) -+ goto mac_start_failed; -+ } -+ -+ err = priv->mac_dev->start(mac_dev); -+ if (err < 0) { -+ if (netif_msg_ifup(priv)) -+ netdev_err(net_dev, "mac_dev->start() = %d\n", err); -+ goto mac_start_failed; -+ } -+ -+ netif_tx_start_all_queues(net_dev); -+ -+ return 0; -+ -+mac_start_failed: -+ for_each_port_device(i, mac_dev->port_dev) -+ fm_port_disable(mac_dev->port_dev[i]); -+ -+ return err; -+} -+EXPORT_SYMBOL(dpa_start); -+ -+int __cold dpa_stop(struct net_device *net_dev) -+{ -+ int _errno, i, err; -+ struct dpa_priv_s *priv; -+ struct mac_device *mac_dev; -+ -+ priv = netdev_priv(net_dev); -+ mac_dev = priv->mac_dev; -+ -+ netif_tx_stop_all_queues(net_dev); -+ /* Allow the Fman (Tx) port to process in-flight frames before we -+ * try switching it off. -+ */ -+ usleep_range(5000, 10000); -+ -+ _errno = mac_dev->stop(mac_dev); -+ if (unlikely(_errno < 0)) -+ if (netif_msg_ifdown(priv)) -+ netdev_err(net_dev, "mac_dev->stop() = %d\n", -+ _errno); -+ -+ for_each_port_device(i, mac_dev->port_dev) { -+ err = fm_port_disable(mac_dev->port_dev[i]); -+ _errno = err ? err : _errno; -+ } -+ -+ if (mac_dev->phy_dev) -+ phy_disconnect(mac_dev->phy_dev); -+ mac_dev->phy_dev = NULL; -+ -+ return _errno; -+} -+EXPORT_SYMBOL(dpa_stop); -+ -+void __cold dpa_timeout(struct net_device *net_dev) -+{ -+ const struct dpa_priv_s *priv; -+ struct dpa_percpu_priv_s *percpu_priv; -+ -+ priv = netdev_priv(net_dev); -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ -+ if (netif_msg_timer(priv)) -+ netdev_crit(net_dev, "Transmit timeout latency: %u ms\n", -+ jiffies_to_msecs(jiffies - net_dev->trans_start)); -+ -+ percpu_priv->stats.tx_errors++; -+} -+EXPORT_SYMBOL(dpa_timeout); -+ -+/* net_device */ -+ -+/** -+ * @param net_dev the device for which statistics are calculated -+ * @param stats the function fills this structure with the device's statistics -+ * @return the address of the structure containing the statistics -+ * -+ * Calculates the statistics for the given device by adding the statistics -+ * collected by each CPU. -+ */ -+struct rtnl_link_stats64 * __cold -+dpa_get_stats64(struct net_device *net_dev, -+ struct rtnl_link_stats64 *stats) -+{ -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ u64 *cpustats; -+ u64 *netstats = (u64 *)stats; -+ int i, j; -+ struct dpa_percpu_priv_s *percpu_priv; -+ int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64); -+ -+ for_each_possible_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ -+ cpustats = (u64 *)&percpu_priv->stats; -+ -+ for (j = 0; j < numstats; j++) -+ netstats[j] += cpustats[j]; -+ } -+ -+ return stats; -+} -+EXPORT_SYMBOL(dpa_get_stats64); -+ -+int dpa_change_mtu(struct net_device *net_dev, int new_mtu) -+{ -+ const int max_mtu = dpa_get_max_mtu(); -+ -+ /* Make sure we don't exceed the Ethernet controller's MAXFRM */ -+ if (new_mtu < 68 || new_mtu > max_mtu) { -+ netdev_err(net_dev, "Invalid L3 mtu %d (must be between %d and %d).\n", -+ new_mtu, 68, max_mtu); -+ return -EINVAL; -+ } -+ net_dev->mtu = new_mtu; -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpa_change_mtu); -+ -+/* .ndo_init callback */ -+int dpa_ndo_init(struct net_device *net_dev) -+{ -+ /* If fsl_fm_max_frm is set to a higher value than the all-common 1500, -+ * we choose conservatively and let the user explicitly set a higher -+ * MTU via ifconfig. Otherwise, the user may end up with different MTUs -+ * in the same LAN. -+ * If on the other hand fsl_fm_max_frm has been chosen below 1500, -+ * start with the maximum allowed. -+ */ -+ int init_mtu = min(dpa_get_max_mtu(), ETH_DATA_LEN); -+ -+ pr_debug("Setting initial MTU on net device: %d\n", init_mtu); -+ net_dev->mtu = init_mtu; -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpa_ndo_init); -+ -+int dpa_set_features(struct net_device *dev, netdev_features_t features) -+{ -+ /* Not much to do here for now */ -+ dev->features = features; -+ return 0; -+} -+EXPORT_SYMBOL(dpa_set_features); -+ -+netdev_features_t dpa_fix_features(struct net_device *dev, -+ netdev_features_t features) -+{ -+ netdev_features_t unsupported_features = 0; -+ -+ /* In theory we should never be requested to enable features that -+ * we didn't set in netdev->features and netdev->hw_features at probe -+ * time, but double check just to be on the safe side. -+ * We don't support enabling Rx csum through ethtool yet -+ */ -+ unsupported_features |= NETIF_F_RXCSUM; -+ -+ features &= ~unsupported_features; -+ -+ return features; -+} -+EXPORT_SYMBOL(dpa_fix_features); -+ -+#ifdef CONFIG_FSL_DPAA_TS -+u64 dpa_get_timestamp_ns(const struct dpa_priv_s *priv, enum port_type rx_tx, -+ const void *data) -+{ -+ u64 *ts, ns; -+ -+ ts = fm_port_get_buffer_time_stamp(priv->mac_dev->port_dev[rx_tx], -+ data); -+ -+ if (!ts || *ts == 0) -+ return 0; -+ -+ be64_to_cpus(ts); -+ -+ /* multiple DPA_PTP_NOMINAL_FREQ_PERIOD_NS for case of non power of 2 */ -+ ns = *ts << DPA_PTP_NOMINAL_FREQ_PERIOD_SHIFT; -+ -+ return ns; -+} -+ -+int dpa_get_ts(const struct dpa_priv_s *priv, enum port_type rx_tx, -+ struct skb_shared_hwtstamps *shhwtstamps, const void *data) -+{ -+ u64 ns; -+ -+ ns = dpa_get_timestamp_ns(priv, rx_tx, data); -+ -+ if (ns == 0) -+ return -EINVAL; -+ -+ memset(shhwtstamps, 0, sizeof(*shhwtstamps)); -+ shhwtstamps->hwtstamp = ns_to_ktime(ns); -+ -+ return 0; -+} -+ -+static void dpa_ts_tx_enable(struct net_device *dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(dev); -+ struct mac_device *mac_dev = priv->mac_dev; -+ -+ if (mac_dev->fm_rtc_enable) -+ mac_dev->fm_rtc_enable(get_fm_handle(dev)); -+ if (mac_dev->ptp_enable) -+ mac_dev->ptp_enable(mac_dev->get_mac_handle(mac_dev)); -+ -+ priv->ts_tx_en = true; -+} -+ -+static void dpa_ts_tx_disable(struct net_device *dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(dev); -+ -+#if 0 -+/* the RTC might be needed by the Rx Ts, cannot disable here -+ * no separate ptp_disable API for Rx/Tx, cannot disable here -+ */ -+ struct mac_device *mac_dev = priv->mac_dev; -+ -+ if (mac_dev->fm_rtc_disable) -+ mac_dev->fm_rtc_disable(get_fm_handle(dev)); -+ -+ if (mac_dev->ptp_disable) -+ mac_dev->ptp_disable(mac_dev->get_mac_handle(mac_dev)); -+#endif -+ -+ priv->ts_tx_en = false; -+} -+ -+static void dpa_ts_rx_enable(struct net_device *dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(dev); -+ struct mac_device *mac_dev = priv->mac_dev; -+ -+ if (mac_dev->fm_rtc_enable) -+ mac_dev->fm_rtc_enable(get_fm_handle(dev)); -+ if (mac_dev->ptp_enable) -+ mac_dev->ptp_enable(mac_dev->get_mac_handle(mac_dev)); -+ -+ priv->ts_rx_en = true; -+} -+ -+static void dpa_ts_rx_disable(struct net_device *dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(dev); -+ -+#if 0 -+/* the RTC might be needed by the Tx Ts, cannot disable here -+ * no separate ptp_disable API for Rx/Tx, cannot disable here -+ */ -+ struct mac_device *mac_dev = priv->mac_dev; -+ -+ if (mac_dev->fm_rtc_disable) -+ mac_dev->fm_rtc_disable(get_fm_handle(dev)); -+ -+ if (mac_dev->ptp_disable) -+ mac_dev->ptp_disable(mac_dev->get_mac_handle(mac_dev)); -+#endif -+ -+ priv->ts_rx_en = false; -+} -+ -+static int dpa_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -+{ -+ struct hwtstamp_config config; -+ -+ if (copy_from_user(&config, rq->ifr_data, sizeof(config))) -+ return -EFAULT; -+ -+ switch (config.tx_type) { -+ case HWTSTAMP_TX_OFF: -+ dpa_ts_tx_disable(dev); -+ break; -+ case HWTSTAMP_TX_ON: -+ dpa_ts_tx_enable(dev); -+ break; -+ default: -+ return -ERANGE; -+ } -+ -+ if (config.rx_filter == HWTSTAMP_FILTER_NONE) -+ dpa_ts_rx_disable(dev); -+ else { -+ dpa_ts_rx_enable(dev); -+ /* TS is set for all frame types, not only those requested */ -+ config.rx_filter = HWTSTAMP_FILTER_ALL; -+ } -+ -+ return copy_to_user(rq->ifr_data, &config, sizeof(config)) ? -+ -EFAULT : 0; -+} -+#endif /* CONFIG_FSL_DPAA_TS */ -+ -+int dpa_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -+{ -+#ifdef CONFIG_FSL_DPAA_1588 -+ struct dpa_priv_s *priv = netdev_priv(dev); -+#endif -+ int ret = 0; -+ -+ /* at least one timestamping feature must be enabled */ -+#ifdef CONFIG_FSL_DPAA_TS -+ if (!netif_running(dev)) -+#endif -+ return -EINVAL; -+ -+#ifdef CONFIG_FSL_DPAA_TS -+ if (cmd == SIOCSHWTSTAMP) -+ return dpa_ts_ioctl(dev, rq, cmd); -+#endif /* CONFIG_FSL_DPAA_TS */ -+ -+#ifdef CONFIG_FSL_DPAA_1588 -+ if ((cmd >= PTP_ENBL_TXTS_IOCTL) && (cmd <= PTP_CLEANUP_TS)) { -+ if (priv->tsu && priv->tsu->valid) -+ ret = dpa_ioctl_1588(dev, rq, cmd); -+ else -+ ret = -ENODEV; -+ } -+#endif -+ -+ return ret; -+} -+EXPORT_SYMBOL(dpa_ioctl); -+ -+int __cold dpa_remove(struct platform_device *of_dev) -+{ -+ int err; -+ struct device *dev; -+ struct net_device *net_dev; -+ struct dpa_priv_s *priv; -+ -+ dev = &of_dev->dev; -+ net_dev = dev_get_drvdata(dev); -+ -+ priv = netdev_priv(net_dev); -+ -+ dpaa_eth_sysfs_remove(dev); -+ -+ dev_set_drvdata(dev, NULL); -+ unregister_netdev(net_dev); -+ -+ err = dpa_fq_free(dev, &priv->dpa_fq_list); -+ -+ qman_delete_cgr_safe(&priv->ingress_cgr); -+ qman_release_cgrid(priv->ingress_cgr.cgrid); -+ qman_delete_cgr_safe(&priv->cgr_data.cgr); -+ qman_release_cgrid(priv->cgr_data.cgr.cgrid); -+ -+ dpa_private_napi_del(net_dev); -+ -+ dpa_bp_free(priv); -+ -+ if (priv->buf_layout) -+ devm_kfree(dev, priv->buf_layout); -+ -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+ /* remove debugfs entry for this net_device */ -+ dpa_netdev_debugfs_remove(net_dev); -+#endif /* CONFIG_FSL_DPAA_DBG_LOOP */ -+ -+#ifdef CONFIG_FSL_DPAA_1588 -+ if (priv->tsu && priv->tsu->valid) -+ dpa_ptp_cleanup(priv); -+#endif -+ -+ free_netdev(net_dev); -+ -+ return err; -+} -+EXPORT_SYMBOL(dpa_remove); -+ -+struct mac_device * __cold __must_check -+__attribute__((nonnull)) -+dpa_mac_probe(struct platform_device *_of_dev) -+{ -+ struct device *dpa_dev, *dev; -+ struct device_node *mac_node; -+ struct platform_device *of_dev; -+ struct mac_device *mac_dev; -+#ifdef CONFIG_FSL_DPAA_1588 -+ int lenp; -+ const phandle *phandle_prop; -+ struct net_device *net_dev = NULL; -+ struct dpa_priv_s *priv = NULL; -+ struct device_node *timer_node; -+#endif -+ dpa_dev = &_of_dev->dev; -+ -+ mac_node = of_parse_phandle(_of_dev->dev.of_node, "fsl,fman-mac", 0); -+ if (unlikely(mac_node == NULL)) { -+ dev_err(dpa_dev, "Cannot find MAC device device tree node\n"); -+ return ERR_PTR(-EFAULT); -+ } -+ -+ of_dev = of_find_device_by_node(mac_node); -+ if (unlikely(of_dev == NULL)) { -+ dev_err(dpa_dev, "of_find_device_by_node(%s) failed\n", -+ mac_node->full_name); -+ of_node_put(mac_node); -+ return ERR_PTR(-EINVAL); -+ } -+ of_node_put(mac_node); -+ -+ dev = &of_dev->dev; -+ -+ mac_dev = dev_get_drvdata(dev); -+ if (unlikely(mac_dev == NULL)) { -+ dev_err(dpa_dev, "dev_get_drvdata(%s) failed\n", -+ dev_name(dev)); -+ return ERR_PTR(-EINVAL); -+ } -+ -+#ifdef CONFIG_FSL_DPAA_1588 -+ phandle_prop = of_get_property(mac_node, "ptimer-handle", &lenp); -+ if (phandle_prop && ((mac_dev->phy_if != PHY_INTERFACE_MODE_SGMII) || -+ ((mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII) && -+ (mac_dev->speed == SPEED_1000)))) { -+ timer_node = of_find_node_by_phandle(*phandle_prop); -+ if (timer_node) -+ net_dev = dev_get_drvdata(dpa_dev); -+ if (timer_node && net_dev) { -+ priv = netdev_priv(net_dev); -+ if (!dpa_ptp_init(priv)) -+ dev_info(dev, "%s: ptp 1588 is initialized.\n", -+ mac_node->full_name); -+ } -+ } -+#endif -+ -+#ifdef CONFIG_PTP_1588_CLOCK_DPAA -+ if ((mac_dev->phy_if != PHY_INTERFACE_MODE_SGMII) || -+ ((mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII) && -+ (mac_dev->speed == SPEED_1000))) { -+ ptp_priv.node = of_parse_phandle(mac_node, "ptimer-handle", 0); -+ if (ptp_priv.node) { -+ ptp_priv.of_dev = of_find_device_by_node(ptp_priv.node); -+ if (unlikely(ptp_priv.of_dev == NULL)) { -+ dev_err(dpa_dev, -+ "Cannot find device represented by timer_node\n"); -+ of_node_put(ptp_priv.node); -+ return ERR_PTR(-EINVAL); -+ } -+ ptp_priv.mac_dev = mac_dev; -+ } -+ } -+#endif -+ return mac_dev; -+} -+EXPORT_SYMBOL(dpa_mac_probe); -+ -+int dpa_set_mac_address(struct net_device *net_dev, void *addr) -+{ -+ const struct dpa_priv_s *priv; -+ int _errno; -+ struct mac_device *mac_dev; -+ -+ priv = netdev_priv(net_dev); -+ -+ _errno = eth_mac_addr(net_dev, addr); -+ if (_errno < 0) { -+ if (netif_msg_drv(priv)) -+ netdev_err(net_dev, -+ "eth_mac_addr() = %d\n", -+ _errno); -+ return _errno; -+ } -+ -+ mac_dev = priv->mac_dev; -+ -+ _errno = mac_dev->change_addr(mac_dev->get_mac_handle(mac_dev), -+ net_dev->dev_addr); -+ if (_errno < 0) { -+ if (netif_msg_drv(priv)) -+ netdev_err(net_dev, -+ "mac_dev->change_addr() = %d\n", -+ _errno); -+ return _errno; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpa_set_mac_address); -+ -+void dpa_set_rx_mode(struct net_device *net_dev) -+{ -+ int _errno; -+ const struct dpa_priv_s *priv; -+ -+ priv = netdev_priv(net_dev); -+ -+ if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) { -+ priv->mac_dev->promisc = !priv->mac_dev->promisc; -+ _errno = priv->mac_dev->set_promisc( -+ priv->mac_dev->get_mac_handle(priv->mac_dev), -+ priv->mac_dev->promisc); -+ if (unlikely(_errno < 0) && netif_msg_drv(priv)) -+ netdev_err(net_dev, -+ "mac_dev->set_promisc() = %d\n", -+ _errno); -+ } -+ -+ _errno = priv->mac_dev->set_multi(net_dev, priv->mac_dev); -+ if (unlikely(_errno < 0) && netif_msg_drv(priv)) -+ netdev_err(net_dev, "mac_dev->set_multi() = %d\n", _errno); -+} -+EXPORT_SYMBOL(dpa_set_rx_mode); -+ -+void dpa_set_buffers_layout(struct mac_device *mac_dev, -+ struct dpa_buffer_layout_s *layout) -+{ -+ struct fm_port_params params; -+ -+ /* Rx */ -+ layout[RX].priv_data_size = (uint16_t)DPA_RX_PRIV_DATA_SIZE; -+ layout[RX].parse_results = true; -+ layout[RX].hash_results = true; -+#ifdef CONFIG_FSL_DPAA_TS -+ layout[RX].time_stamp = true; -+#endif -+ fm_port_get_buff_layout_ext_params(mac_dev->port_dev[RX], ¶ms); -+ layout[RX].manip_extra_space = params.manip_extra_space; -+ /* a value of zero for data alignment means "don't care", so align to -+ * a non-zero value to prevent FMD from using its own default -+ */ -+ layout[RX].data_align = params.data_align ? : DPA_FD_DATA_ALIGNMENT; -+ -+ /* Tx */ -+ layout[TX].priv_data_size = DPA_TX_PRIV_DATA_SIZE; -+ layout[TX].parse_results = true; -+ layout[TX].hash_results = true; -+#ifdef CONFIG_FSL_DPAA_TS -+ layout[TX].time_stamp = true; -+#endif -+ fm_port_get_buff_layout_ext_params(mac_dev->port_dev[TX], ¶ms); -+ layout[TX].manip_extra_space = params.manip_extra_space; -+ layout[TX].data_align = params.data_align ? : DPA_FD_DATA_ALIGNMENT; -+} -+EXPORT_SYMBOL(dpa_set_buffers_layout); -+ -+int __attribute__((nonnull)) -+dpa_bp_alloc(struct dpa_bp *dpa_bp) -+{ -+ int err; -+ struct bman_pool_params bp_params; -+ struct platform_device *pdev; -+ -+ if (dpa_bp->size == 0 || dpa_bp->config_count == 0) { -+ pr_err("Buffer pool is not properly initialized! Missing size or initial number of buffers"); -+ return -EINVAL; -+ } -+ -+ memset(&bp_params, 0, sizeof(struct bman_pool_params)); -+#ifdef CONFIG_FMAN_PFC -+ bp_params.flags = BMAN_POOL_FLAG_THRESH; -+ bp_params.thresholds[0] = bp_params.thresholds[2] = -+ CONFIG_FSL_DPAA_ETH_REFILL_THRESHOLD; -+ bp_params.thresholds[1] = bp_params.thresholds[3] = -+ CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT; -+#endif -+ -+ /* If the pool is already specified, we only create one per bpid */ -+ if (dpa_bpid2pool_use(dpa_bp->bpid)) -+ return 0; -+ -+ if (dpa_bp->bpid == 0) -+ bp_params.flags |= BMAN_POOL_FLAG_DYNAMIC_BPID; -+ else -+ bp_params.bpid = dpa_bp->bpid; -+ -+ dpa_bp->pool = bman_new_pool(&bp_params); -+ if (unlikely(dpa_bp->pool == NULL)) { -+ pr_err("bman_new_pool() failed\n"); -+ return -ENODEV; -+ } -+ -+ dpa_bp->bpid = (uint8_t)bman_get_params(dpa_bp->pool)->bpid; -+ -+ pdev = platform_device_register_simple("dpaa_eth_bpool", -+ dpa_bp->bpid, NULL, 0); -+ if (IS_ERR(pdev)) { -+ err = PTR_ERR(pdev); -+ goto pdev_register_failed; -+ } -+ -+ err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(40)); -+ if (err) -+ goto pdev_mask_failed; -+ if (!pdev->dev.dma_mask) -+ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; -+ else { -+ err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)); -+ if (err) -+ goto pdev_mask_failed; -+ } -+ -+#ifdef CONFIG_FMAN_ARM -+ /* force coherency */ -+ pdev->dev.archdata.dma_coherent = true; -+ arch_setup_dma_ops(&pdev->dev, 0, 0, NULL, true); -+#endif -+ -+ dpa_bp->dev = &pdev->dev; -+ -+ if (dpa_bp->seed_cb) { -+ err = dpa_bp->seed_cb(dpa_bp); -+ if (err) -+ goto pool_seed_failed; -+ } -+ -+ dpa_bpid2pool_map(dpa_bp->bpid, dpa_bp); -+ -+ return 0; -+ -+pool_seed_failed: -+pdev_mask_failed: -+ platform_device_unregister(pdev); -+pdev_register_failed: -+ bman_free_pool(dpa_bp->pool); -+ -+ return err; -+} -+EXPORT_SYMBOL(dpa_bp_alloc); -+ -+void dpa_bp_drain(struct dpa_bp *bp) -+{ -+ int ret, num = 8; -+ -+ do { -+ struct bm_buffer bmb[8]; -+ int i; -+ -+ ret = bman_acquire(bp->pool, bmb, num, 0); -+ if (ret < 0) { -+ if (num == 8) { -+ /* we have less than 8 buffers left; -+ * drain them one by one -+ */ -+ num = 1; -+ ret = 1; -+ continue; -+ } else { -+ /* Pool is fully drained */ -+ break; -+ } -+ } -+ -+ for (i = 0; i < num; i++) { -+ dma_addr_t addr = bm_buf_addr(&bmb[i]); -+ -+ dma_unmap_single(bp->dev, addr, bp->size, -+ DMA_BIDIRECTIONAL); -+ -+ bp->free_buf_cb(phys_to_virt(addr)); -+ } -+ } while (ret > 0); -+} -+EXPORT_SYMBOL(dpa_bp_drain); -+ -+static void __cold __attribute__((nonnull)) -+_dpa_bp_free(struct dpa_bp *dpa_bp) -+{ -+ struct dpa_bp *bp = dpa_bpid2pool(dpa_bp->bpid); -+ -+ /* the mapping between bpid and dpa_bp is done very late in the -+ * allocation procedure; if something failed before the mapping, the bp -+ * was not configured, therefore we don't need the below instructions -+ */ -+ if (!bp) -+ return; -+ -+ if (!atomic_dec_and_test(&bp->refs)) -+ return; -+ -+ if (bp->free_buf_cb) -+ dpa_bp_drain(bp); -+ -+ dpa_bp_array[bp->bpid] = NULL; -+ bman_free_pool(bp->pool); -+ -+ if (bp->dev) -+ platform_device_unregister(to_platform_device(bp->dev)); -+} -+ -+void __cold __attribute__((nonnull)) -+dpa_bp_free(struct dpa_priv_s *priv) -+{ -+ int i; -+ -+ for (i = 0; i < priv->bp_count; i++) -+ _dpa_bp_free(&priv->dpa_bp[i]); -+} -+EXPORT_SYMBOL(dpa_bp_free); -+ -+struct dpa_bp *dpa_bpid2pool(int bpid) -+{ -+ return dpa_bp_array[bpid]; -+} -+EXPORT_SYMBOL(dpa_bpid2pool); -+ -+void dpa_bpid2pool_map(int bpid, struct dpa_bp *dpa_bp) -+{ -+ dpa_bp_array[bpid] = dpa_bp; -+ atomic_set(&dpa_bp->refs, 1); -+} -+ -+bool dpa_bpid2pool_use(int bpid) -+{ -+ if (dpa_bpid2pool(bpid)) { -+ atomic_inc(&dpa_bp_array[bpid]->refs); -+ return true; -+ } -+ -+ return false; -+} -+ -+#ifdef CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE -+u16 dpa_select_queue(struct net_device *net_dev, struct sk_buff *skb, -+ void *accel_priv, select_queue_fallback_t fallback) -+{ -+ return dpa_get_queue_mapping(skb); -+} -+EXPORT_SYMBOL(dpa_select_queue); -+#endif -+ -+struct dpa_fq *dpa_fq_alloc(struct device *dev, -+ u32 fq_start, -+ u32 fq_count, -+ struct list_head *list, -+ enum dpa_fq_type fq_type) -+{ -+ int i; -+ struct dpa_fq *dpa_fq; -+ -+ dpa_fq = devm_kzalloc(dev, sizeof(*dpa_fq) * fq_count, GFP_KERNEL); -+ if (dpa_fq == NULL) -+ return NULL; -+ -+ for (i = 0; i < fq_count; i++) { -+ dpa_fq[i].fq_type = fq_type; -+ if (fq_type == FQ_TYPE_RX_PCD_HI_PRIO) -+ dpa_fq[i].fqid = fq_start ? -+ DPAA_ETH_FQ_DELTA + fq_start + i : 0; -+ else -+ dpa_fq[i].fqid = fq_start ? fq_start + i : 0; -+ -+ list_add_tail(&dpa_fq[i].list, list); -+ } -+ -+#ifdef CONFIG_FMAN_PFC -+ if (fq_type == FQ_TYPE_TX) -+ for (i = 0; i < fq_count; i++) -+ dpa_fq[i].wq = i / dpa_num_cpus; -+ else -+#endif -+ for (i = 0; i < fq_count; i++) -+ _dpa_assign_wq(dpa_fq + i); -+ -+ return dpa_fq; -+} -+EXPORT_SYMBOL(dpa_fq_alloc); -+ -+/* Probing of FQs for MACful ports */ -+int dpa_fq_probe_mac(struct device *dev, struct list_head *list, -+ struct fm_port_fqs *port_fqs, -+ bool alloc_tx_conf_fqs, -+ enum port_type ptype) -+{ -+ struct fqid_cell *fqids = NULL; -+ const void *fqids_off = NULL; -+ struct dpa_fq *dpa_fq = NULL; -+ struct device_node *np = dev->of_node; -+ int num_ranges; -+ int i, lenp; -+ -+ if (ptype == TX && alloc_tx_conf_fqs) { -+ if (!dpa_fq_alloc(dev, tx_confirm_fqids->start, -+ tx_confirm_fqids->count, list, -+ FQ_TYPE_TX_CONF_MQ)) -+ goto fq_alloc_failed; -+ } -+ -+ fqids_off = of_get_property(np, fsl_qman_frame_queues[ptype], &lenp); -+ if (fqids_off == NULL) { -+ /* No dts definition, so use the defaults. */ -+ fqids = default_fqids[ptype]; -+ num_ranges = 3; -+ } else { -+ num_ranges = lenp / sizeof(*fqids); -+ -+ fqids = devm_kzalloc(dev, sizeof(*fqids) * num_ranges, -+ GFP_KERNEL); -+ if (fqids == NULL) -+ goto fqids_alloc_failed; -+ -+ /* convert to CPU endianess */ -+ for (i = 0; i < num_ranges; i++) { -+ fqids[i].start = be32_to_cpup(fqids_off + -+ i * sizeof(*fqids)); -+ fqids[i].count = be32_to_cpup(fqids_off + -+ i * sizeof(*fqids) + sizeof(__be32)); -+ } -+ } -+ -+ for (i = 0; i < num_ranges; i++) { -+ switch (i) { -+ case 0: -+ /* The first queue is the error queue */ -+ if (fqids[i].count != 1) -+ goto invalid_error_queue; -+ -+ dpa_fq = dpa_fq_alloc(dev, fqids[i].start, -+ fqids[i].count, list, -+ ptype == RX ? -+ FQ_TYPE_RX_ERROR : -+ FQ_TYPE_TX_ERROR); -+ if (dpa_fq == NULL) -+ goto fq_alloc_failed; -+ -+ if (ptype == RX) -+ port_fqs->rx_errq = &dpa_fq[0]; -+ else -+ port_fqs->tx_errq = &dpa_fq[0]; -+ break; -+ case 1: -+ /* the second queue is the default queue */ -+ if (fqids[i].count != 1) -+ goto invalid_default_queue; -+ -+ dpa_fq = dpa_fq_alloc(dev, fqids[i].start, -+ fqids[i].count, list, -+ ptype == RX ? -+ FQ_TYPE_RX_DEFAULT : -+ FQ_TYPE_TX_CONFIRM); -+ if (dpa_fq == NULL) -+ goto fq_alloc_failed; -+ -+ if (ptype == RX) -+ port_fqs->rx_defq = &dpa_fq[0]; -+ else -+ port_fqs->tx_defq = &dpa_fq[0]; -+ break; -+ default: -+ /* all subsequent queues are either RX* PCD or Tx */ -+ if (ptype == RX) { -+ if (!dpa_fq_alloc(dev, fqids[i].start, -+ fqids[i].count, list, -+ FQ_TYPE_RX_PCD) || -+ !dpa_fq_alloc(dev, fqids[i].start, -+ fqids[i].count, list, -+ FQ_TYPE_RX_PCD_HI_PRIO)) -+ goto fq_alloc_failed; -+ } else { -+ if (!dpa_fq_alloc(dev, fqids[i].start, -+ fqids[i].count, list, -+ FQ_TYPE_TX)) -+ goto fq_alloc_failed; -+ } -+ break; -+ } -+ } -+ -+ return 0; -+ -+fq_alloc_failed: -+fqids_alloc_failed: -+ dev_err(dev, "Cannot allocate memory for frame queues\n"); -+ return -ENOMEM; -+ -+invalid_default_queue: -+invalid_error_queue: -+ dev_err(dev, "Too many default or error queues\n"); -+ return -EINVAL; -+} -+EXPORT_SYMBOL(dpa_fq_probe_mac); -+ -+static u32 rx_pool_channel; -+static DEFINE_SPINLOCK(rx_pool_channel_init); -+ -+int dpa_get_channel(void) -+{ -+ spin_lock(&rx_pool_channel_init); -+ if (!rx_pool_channel) { -+ u32 pool; -+ int ret = qman_alloc_pool(&pool); -+ if (!ret) -+ rx_pool_channel = pool; -+ } -+ spin_unlock(&rx_pool_channel_init); -+ if (!rx_pool_channel) -+ return -ENOMEM; -+ return rx_pool_channel; -+} -+EXPORT_SYMBOL(dpa_get_channel); -+ -+void dpa_release_channel(void) -+{ -+ qman_release_pool(rx_pool_channel); -+} -+EXPORT_SYMBOL(dpa_release_channel); -+ -+int dpaa_eth_add_channel(void *__arg) -+{ -+ const cpumask_t *cpus = qman_affine_cpus(); -+ u32 pool = QM_SDQCR_CHANNELS_POOL_CONV((u16)(unsigned long)__arg); -+ int cpu; -+ struct qman_portal *portal; -+ -+ for_each_cpu(cpu, cpus) { -+ portal = (struct qman_portal *)qman_get_affine_portal(cpu); -+ qman_p_static_dequeue_add(portal, pool); -+ } -+ return 0; -+} -+EXPORT_SYMBOL(dpaa_eth_add_channel); -+ -+/** -+ * Congestion group state change notification callback. -+ * Stops the device's egress queues while they are congested and -+ * wakes them upon exiting congested state. -+ * Also updates some CGR-related stats. -+ */ -+static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr, -+ -+ int congested) -+{ -+ struct dpa_priv_s *priv = (struct dpa_priv_s *)container_of(cgr, -+ struct dpa_priv_s, cgr_data.cgr); -+ -+ if (congested) { -+ priv->cgr_data.congestion_start_jiffies = jiffies; -+ netif_tx_stop_all_queues(priv->net_dev); -+ priv->cgr_data.cgr_congested_count++; -+ } else { -+ priv->cgr_data.congested_jiffies += -+ (jiffies - priv->cgr_data.congestion_start_jiffies); -+ netif_tx_wake_all_queues(priv->net_dev); -+ } -+} -+ -+int dpaa_eth_cgr_init(struct dpa_priv_s *priv) -+{ -+ struct qm_mcc_initcgr initcgr; -+ u32 cs_th; -+ int err; -+ -+ err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid); -+ if (err < 0) { -+ pr_err("Error %d allocating CGR ID\n", err); -+ goto out_error; -+ } -+ priv->cgr_data.cgr.cb = dpaa_eth_cgscn; -+ -+ /* Enable Congestion State Change Notifications and CS taildrop */ -+ initcgr.we_mask = QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES; -+ initcgr.cgr.cscn_en = QM_CGR_EN; -+ -+ /* Set different thresholds based on the MAC speed. -+ * TODO: this may turn suboptimal if the MAC is reconfigured at a speed -+ * lower than its max, e.g. if a dTSEC later negotiates a 100Mbps link. -+ * In such cases, we ought to reconfigure the threshold, too. -+ */ -+ if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full) -+ cs_th = CONFIG_FSL_DPAA_CS_THRESHOLD_10G; -+ else -+ cs_th = CONFIG_FSL_DPAA_CS_THRESHOLD_1G; -+ qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1); -+ -+ initcgr.we_mask |= QM_CGR_WE_CSTD_EN; -+ initcgr.cgr.cstd_en = QM_CGR_EN; -+ -+ err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT, -+ &initcgr); -+ if (err < 0) { -+ pr_err("Error %d creating CGR with ID %d\n", err, -+ priv->cgr_data.cgr.cgrid); -+ qman_release_cgrid(priv->cgr_data.cgr.cgrid); -+ goto out_error; -+ } -+ pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n", -+ priv->cgr_data.cgr.cgrid, priv->mac_dev->addr, -+ priv->cgr_data.cgr.chan); -+ -+out_error: -+ return err; -+} -+EXPORT_SYMBOL(dpaa_eth_cgr_init); -+ -+static inline void dpa_setup_ingress(const struct dpa_priv_s *priv, -+ struct dpa_fq *fq, -+ const struct qman_fq *template) -+{ -+ fq->fq_base = *template; -+ fq->net_dev = priv->net_dev; -+ -+ fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE; -+ fq->channel = priv->channel; -+} -+ -+static inline void dpa_setup_egress(const struct dpa_priv_s *priv, -+ struct dpa_fq *fq, -+ struct fm_port *port, -+ const struct qman_fq *template) -+{ -+ fq->fq_base = *template; -+ fq->net_dev = priv->net_dev; -+ -+ if (port) { -+ fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL; -+ fq->channel = (uint16_t)fm_get_tx_port_channel(port); -+ } else { -+ fq->flags = QMAN_FQ_FLAG_NO_MODIFY; -+ } -+} -+ -+void dpa_fq_setup(struct dpa_priv_s *priv, const struct dpa_fq_cbs_t *fq_cbs, -+ struct fm_port *tx_port) -+{ -+ struct dpa_fq *fq; -+ uint16_t portals[NR_CPUS]; -+ int cpu, portal_cnt = 0, num_portals = 0; -+ uint32_t pcd_fqid, pcd_fqid_hi_prio; -+ const cpumask_t *affine_cpus = qman_affine_cpus(); -+ int egress_cnt = 0, conf_cnt = 0; -+ -+ /* Prepare for PCD FQs init */ -+ for_each_cpu(cpu, affine_cpus) -+ portals[num_portals++] = qman_affine_channel(cpu); -+ if (num_portals == 0) -+ dev_err(priv->net_dev->dev.parent, -+ "No Qman software (affine) channels found"); -+ -+ pcd_fqid = (priv->mac_dev) ? -+ DPAA_ETH_PCD_FQ_BASE(priv->mac_dev->res->start) : 0; -+ pcd_fqid_hi_prio = (priv->mac_dev) ? -+ DPAA_ETH_PCD_FQ_HI_PRIO_BASE(priv->mac_dev->res->start) : 0; -+ -+ /* Initialize each FQ in the list */ -+ list_for_each_entry(fq, &priv->dpa_fq_list, list) { -+ switch (fq->fq_type) { -+ case FQ_TYPE_RX_DEFAULT: -+ BUG_ON(!priv->mac_dev); -+ dpa_setup_ingress(priv, fq, &fq_cbs->rx_defq); -+ break; -+ case FQ_TYPE_RX_ERROR: -+ BUG_ON(!priv->mac_dev); -+ dpa_setup_ingress(priv, fq, &fq_cbs->rx_errq); -+ break; -+ case FQ_TYPE_RX_PCD: -+ /* For MACless we can't have dynamic Rx queues */ -+ BUG_ON(!priv->mac_dev && !fq->fqid); -+ dpa_setup_ingress(priv, fq, &fq_cbs->rx_defq); -+ if (!fq->fqid) -+ fq->fqid = pcd_fqid++; -+ fq->channel = portals[portal_cnt]; -+ portal_cnt = (portal_cnt + 1) % num_portals; -+ break; -+ case FQ_TYPE_RX_PCD_HI_PRIO: -+ /* For MACless we can't have dynamic Hi Pri Rx queues */ -+ BUG_ON(!priv->mac_dev && !fq->fqid); -+ dpa_setup_ingress(priv, fq, &fq_cbs->rx_defq); -+ if (!fq->fqid) -+ fq->fqid = pcd_fqid_hi_prio++; -+ fq->channel = portals[portal_cnt]; -+ portal_cnt = (portal_cnt + 1) % num_portals; -+ break; -+ case FQ_TYPE_TX: -+ dpa_setup_egress(priv, fq, tx_port, -+ &fq_cbs->egress_ern); -+ /* If we have more Tx queues than the number of cores, -+ * just ignore the extra ones. -+ */ -+ if (egress_cnt < DPAA_ETH_TX_QUEUES) -+ priv->egress_fqs[egress_cnt++] = &fq->fq_base; -+ break; -+ case FQ_TYPE_TX_CONFIRM: -+ BUG_ON(!priv->mac_dev); -+ dpa_setup_ingress(priv, fq, &fq_cbs->tx_defq); -+ break; -+ case FQ_TYPE_TX_CONF_MQ: -+ BUG_ON(!priv->mac_dev); -+ dpa_setup_ingress(priv, fq, &fq_cbs->tx_defq); -+ priv->conf_fqs[conf_cnt++] = &fq->fq_base; -+ break; -+ case FQ_TYPE_TX_ERROR: -+ BUG_ON(!priv->mac_dev); -+ dpa_setup_ingress(priv, fq, &fq_cbs->tx_errq); -+ break; -+ default: -+ dev_warn(priv->net_dev->dev.parent, -+ "Unknown FQ type detected!\n"); -+ break; -+ } -+ } -+ -+ /* The number of Tx queues may be smaller than the number of cores, if -+ * the Tx queue range is specified in the device tree instead of being -+ * dynamically allocated. -+ * Make sure all CPUs receive a corresponding Tx queue. -+ */ -+ while (egress_cnt < DPAA_ETH_TX_QUEUES) { -+ list_for_each_entry(fq, &priv->dpa_fq_list, list) { -+ if (fq->fq_type != FQ_TYPE_TX) -+ continue; -+ priv->egress_fqs[egress_cnt++] = &fq->fq_base; -+ if (egress_cnt == DPAA_ETH_TX_QUEUES) -+ break; -+ } -+ } -+} -+EXPORT_SYMBOL(dpa_fq_setup); -+ -+int dpa_fq_init(struct dpa_fq *dpa_fq, bool td_enable) -+{ -+ int _errno; -+ const struct dpa_priv_s *priv; -+ struct device *dev; -+ struct qman_fq *fq; -+ struct qm_mcc_initfq initfq; -+ struct qman_fq *confq; -+ int queue_id; -+ -+ priv = netdev_priv(dpa_fq->net_dev); -+ dev = dpa_fq->net_dev->dev.parent; -+ -+ if (dpa_fq->fqid == 0) -+ dpa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID; -+ -+ dpa_fq->init = !(dpa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY); -+ -+ _errno = qman_create_fq(dpa_fq->fqid, dpa_fq->flags, &dpa_fq->fq_base); -+ if (_errno) { -+ dev_err(dev, "qman_create_fq() failed\n"); -+ return _errno; -+ } -+ fq = &dpa_fq->fq_base; -+ -+ if (dpa_fq->init) { -+ memset(&initfq, 0, sizeof(initfq)); -+ -+ initfq.we_mask = QM_INITFQ_WE_FQCTRL; -+ /* FIXME: why would we want to keep an empty FQ in cache? */ -+ initfq.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; -+ -+ /* Try to reduce the number of portal interrupts for -+ * Tx Confirmation FQs. -+ */ -+ if (dpa_fq->fq_type == FQ_TYPE_TX_CONFIRM) -+ initfq.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; -+ -+ /* FQ placement */ -+ initfq.we_mask |= QM_INITFQ_WE_DESTWQ; -+ -+ initfq.fqd.dest.channel = dpa_fq->channel; -+ initfq.fqd.dest.wq = dpa_fq->wq; -+ -+ /* Put all egress queues in a congestion group of their own. -+ * Sensu stricto, the Tx confirmation queues are Rx FQs, -+ * rather than Tx - but they nonetheless account for the -+ * memory footprint on behalf of egress traffic. We therefore -+ * place them in the netdev's CGR, along with the Tx FQs. -+ */ -+ if (dpa_fq->fq_type == FQ_TYPE_TX || -+ dpa_fq->fq_type == FQ_TYPE_TX_CONFIRM || -+ dpa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) { -+ initfq.we_mask |= QM_INITFQ_WE_CGID; -+ initfq.fqd.fq_ctrl |= QM_FQCTRL_CGE; -+ initfq.fqd.cgid = (uint8_t)priv->cgr_data.cgr.cgrid; -+ /* Set a fixed overhead accounting, in an attempt to -+ * reduce the impact of fixed-size skb shells and the -+ * driver's needed headroom on system memory. This is -+ * especially the case when the egress traffic is -+ * composed of small datagrams. -+ * Unfortunately, QMan's OAL value is capped to an -+ * insufficient value, but even that is better than -+ * no overhead accounting at all. -+ */ -+ initfq.we_mask |= QM_INITFQ_WE_OAC; -+ initfq.fqd.oac_init.oac = QM_OAC_CG; -+ initfq.fqd.oac_init.oal = -+ (signed char)(min(sizeof(struct sk_buff) + -+ priv->tx_headroom, (size_t)FSL_QMAN_MAX_OAL)); -+ } -+ -+ if (td_enable) { -+ initfq.we_mask |= QM_INITFQ_WE_TDTHRESH; -+ qm_fqd_taildrop_set(&initfq.fqd.td, -+ DPA_FQ_TD, 1); -+ initfq.fqd.fq_ctrl = QM_FQCTRL_TDE; -+ } -+ -+ /* Configure the Tx confirmation queue, now that we know -+ * which Tx queue it pairs with. -+ */ -+ if (dpa_fq->fq_type == FQ_TYPE_TX) { -+ queue_id = _dpa_tx_fq_to_id(priv, &dpa_fq->fq_base); -+ if (queue_id >= 0) { -+ confq = priv->conf_fqs[queue_id]; -+ if (confq) { -+ initfq.we_mask |= QM_INITFQ_WE_CONTEXTA; -+ /* ContextA: OVOM=1 (use contextA2 bits instead of ICAD) -+ * A2V=1 (contextA A2 field is valid) -+ * A0V=1 (contextA A0 field is valid) -+ * B0V=1 (contextB field is valid) -+ * ContextA A2: EBD=1 (deallocate buffers inside FMan) -+ * ContextB B0(ASPID): 0 (absolute Virtual Storage ID) -+ */ -+ initfq.fqd.context_a.hi = 0x1e000000; -+ initfq.fqd.context_a.lo = 0x80000000; -+ } -+ } -+ } -+ -+ /* Put all *private* ingress queues in our "ingress CGR". */ -+ if (priv->use_ingress_cgr && -+ (dpa_fq->fq_type == FQ_TYPE_RX_DEFAULT || -+ dpa_fq->fq_type == FQ_TYPE_RX_ERROR || -+ dpa_fq->fq_type == FQ_TYPE_RX_PCD || -+ dpa_fq->fq_type == FQ_TYPE_RX_PCD_HI_PRIO)) { -+ initfq.we_mask |= QM_INITFQ_WE_CGID; -+ initfq.fqd.fq_ctrl |= QM_FQCTRL_CGE; -+ initfq.fqd.cgid = (uint8_t)priv->ingress_cgr.cgrid; -+ /* Set a fixed overhead accounting, just like for the -+ * egress CGR. -+ */ -+ initfq.we_mask |= QM_INITFQ_WE_OAC; -+ initfq.fqd.oac_init.oac = QM_OAC_CG; -+ initfq.fqd.oac_init.oal = -+ (signed char)(min(sizeof(struct sk_buff) + -+ priv->tx_headroom, (size_t)FSL_QMAN_MAX_OAL)); -+ } -+ -+ /* Initialization common to all ingress queues */ -+ if (dpa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) { -+ initfq.we_mask |= QM_INITFQ_WE_CONTEXTA; -+ initfq.fqd.fq_ctrl |= -+ QM_FQCTRL_CTXASTASHING | QM_FQCTRL_AVOIDBLOCK; -+ initfq.fqd.context_a.stashing.exclusive = -+ QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX | -+ QM_STASHING_EXCL_ANNOTATION; -+ initfq.fqd.context_a.stashing.data_cl = 2; -+ initfq.fqd.context_a.stashing.annotation_cl = 1; -+ initfq.fqd.context_a.stashing.context_cl = -+ DIV_ROUND_UP(sizeof(struct qman_fq), 64); -+ } -+ -+ _errno = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq); -+ if (_errno < 0) { -+ dev_err(dev, "qman_init_fq(%u) = %d\n", -+ qman_fq_fqid(fq), _errno); -+ qman_destroy_fq(fq, 0); -+ return _errno; -+ } -+ } -+ -+ dpa_fq->fqid = qman_fq_fqid(fq); -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpa_fq_init); -+ -+int __cold __attribute__((nonnull)) -+_dpa_fq_free(struct device *dev, struct qman_fq *fq) -+{ -+ int _errno, __errno; -+ struct dpa_fq *dpa_fq; -+ const struct dpa_priv_s *priv; -+ -+ _errno = 0; -+ -+ dpa_fq = container_of(fq, struct dpa_fq, fq_base); -+ priv = netdev_priv(dpa_fq->net_dev); -+ -+ if (dpa_fq->init) { -+ _errno = qman_retire_fq(fq, NULL); -+ if (unlikely(_errno < 0) && netif_msg_drv(priv)) -+ dev_err(dev, "qman_retire_fq(%u) = %d\n", -+ qman_fq_fqid(fq), _errno); -+ -+ __errno = qman_oos_fq(fq); -+ if (unlikely(__errno < 0) && netif_msg_drv(priv)) { -+ dev_err(dev, "qman_oos_fq(%u) = %d\n", -+ qman_fq_fqid(fq), __errno); -+ if (_errno >= 0) -+ _errno = __errno; -+ } -+ } -+ -+ qman_destroy_fq(fq, 0); -+ list_del(&dpa_fq->list); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(_dpa_fq_free); -+ -+int __cold __attribute__((nonnull)) -+dpa_fq_free(struct device *dev, struct list_head *list) -+{ -+ int _errno, __errno; -+ struct dpa_fq *dpa_fq, *tmp; -+ -+ _errno = 0; -+ list_for_each_entry_safe(dpa_fq, tmp, list, list) { -+ __errno = _dpa_fq_free(dev, (struct qman_fq *)dpa_fq); -+ if (unlikely(__errno < 0) && _errno >= 0) -+ _errno = __errno; -+ } -+ -+ return _errno; -+} -+EXPORT_SYMBOL(dpa_fq_free); -+ -+static void -+dpaa_eth_init_tx_port(struct fm_port *port, struct dpa_fq *errq, -+ struct dpa_fq *defq, struct dpa_buffer_layout_s *buf_layout) -+{ -+ struct fm_port_params tx_port_param; -+ bool frag_enabled = false; -+ -+ memset(&tx_port_param, 0, sizeof(tx_port_param)); -+ dpaa_eth_init_port(tx, port, tx_port_param, errq->fqid, defq->fqid, -+ buf_layout, frag_enabled); -+} -+ -+static void -+dpaa_eth_init_rx_port(struct fm_port *port, struct dpa_bp *bp, size_t count, -+ struct dpa_fq *errq, struct dpa_fq *defq, -+ struct dpa_buffer_layout_s *buf_layout) -+{ -+ struct fm_port_params rx_port_param; -+ int i; -+ bool frag_enabled = false; -+ -+ memset(&rx_port_param, 0, sizeof(rx_port_param)); -+ count = min(ARRAY_SIZE(rx_port_param.pool_param), count); -+ rx_port_param.num_pools = (uint8_t)count; -+ for (i = 0; i < count; i++) { -+ if (i >= rx_port_param.num_pools) -+ break; -+ rx_port_param.pool_param[i].id = bp[i].bpid; -+ rx_port_param.pool_param[i].size = (uint16_t)bp[i].size; -+ } -+ -+ dpaa_eth_init_port(rx, port, rx_port_param, errq->fqid, defq->fqid, -+ buf_layout, frag_enabled); -+} -+ -+#if defined(CONFIG_FSL_SDK_FMAN_TEST) -+/* Defined as weak, to be implemented by fman pcd tester. */ -+int dpa_alloc_pcd_fqids(struct device *, uint32_t, uint8_t, uint32_t *) -+__attribute__((weak)); -+ -+int dpa_free_pcd_fqids(struct device *, uint32_t) __attribute__((weak)); -+#else -+int dpa_alloc_pcd_fqids(struct device *, uint32_t, uint8_t, uint32_t *); -+ -+int dpa_free_pcd_fqids(struct device *, uint32_t); -+ -+#endif /* CONFIG_FSL_SDK_FMAN_TEST */ -+ -+ -+int dpa_alloc_pcd_fqids(struct device *dev, uint32_t num, -+ uint8_t alignment, uint32_t *base_fqid) -+{ -+ dev_crit(dev, "callback not implemented!\n"); -+ -+ return 0; -+} -+ -+int dpa_free_pcd_fqids(struct device *dev, uint32_t base_fqid) -+{ -+ -+ dev_crit(dev, "callback not implemented!\n"); -+ -+ return 0; -+} -+ -+void dpaa_eth_init_ports(struct mac_device *mac_dev, -+ struct dpa_bp *bp, size_t count, -+ struct fm_port_fqs *port_fqs, -+ struct dpa_buffer_layout_s *buf_layout, -+ struct device *dev) -+{ -+ struct fm_port_pcd_param rx_port_pcd_param; -+ struct fm_port *rxport = mac_dev->port_dev[RX]; -+ struct fm_port *txport = mac_dev->port_dev[TX]; -+ -+ dpaa_eth_init_tx_port(txport, port_fqs->tx_errq, -+ port_fqs->tx_defq, &buf_layout[TX]); -+ dpaa_eth_init_rx_port(rxport, bp, count, port_fqs->rx_errq, -+ port_fqs->rx_defq, &buf_layout[RX]); -+ -+ rx_port_pcd_param.cba = dpa_alloc_pcd_fqids; -+ rx_port_pcd_param.cbf = dpa_free_pcd_fqids; -+ rx_port_pcd_param.dev = dev; -+ fm_port_pcd_bind(rxport, &rx_port_pcd_param); -+} -+EXPORT_SYMBOL(dpaa_eth_init_ports); -+ -+void dpa_release_sgt(struct qm_sg_entry *sgt) -+{ -+ struct dpa_bp *dpa_bp; -+ struct bm_buffer bmb[DPA_BUFF_RELEASE_MAX]; -+ uint8_t i = 0, j; -+ -+ memset(bmb, 0, DPA_BUFF_RELEASE_MAX * sizeof(struct bm_buffer)); -+ -+ do { -+ dpa_bp = dpa_bpid2pool(qm_sg_entry_get_bpid(&sgt[i])); -+ DPA_BUG_ON(!dpa_bp); -+ -+ j = 0; -+ do { -+ DPA_BUG_ON(qm_sg_entry_get_ext(&sgt[i])); -+ bm_buffer_set64(&bmb[j], qm_sg_addr(&sgt[i])); -+ -+ j++; i++; -+ } while (j < ARRAY_SIZE(bmb) && -+ !qm_sg_entry_get_final(&sgt[i-1]) && -+ qm_sg_entry_get_bpid(&sgt[i-1]) == -+ qm_sg_entry_get_bpid(&sgt[i])); -+ -+ while (bman_release(dpa_bp->pool, bmb, j, 0)) -+ cpu_relax(); -+ } while (!qm_sg_entry_get_final(&sgt[i-1])); -+} -+EXPORT_SYMBOL(dpa_release_sgt); -+ -+void __attribute__((nonnull)) -+dpa_fd_release(const struct net_device *net_dev, const struct qm_fd *fd) -+{ -+ struct qm_sg_entry *sgt; -+ struct dpa_bp *dpa_bp; -+ struct bm_buffer bmb; -+ dma_addr_t addr; -+ void *vaddr; -+ -+ memset(&bmb, 0, sizeof(struct bm_buffer)); -+ bm_buffer_set64(&bmb, fd->addr); -+ -+ dpa_bp = dpa_bpid2pool(fd->bpid); -+ DPA_BUG_ON(!dpa_bp); -+ -+ if (fd->format == qm_fd_sg) { -+ vaddr = phys_to_virt(fd->addr); -+ sgt = vaddr + dpa_fd_offset(fd); -+ -+ dma_unmap_single(dpa_bp->dev, qm_fd_addr(fd), dpa_bp->size, -+ DMA_BIDIRECTIONAL); -+ -+ dpa_release_sgt(sgt); -+ addr = dma_map_single(dpa_bp->dev, vaddr, dpa_bp->size, -+ DMA_BIDIRECTIONAL); -+ if (unlikely(dma_mapping_error(dpa_bp->dev, addr))) { -+ dev_err(dpa_bp->dev, "DMA mapping failed"); -+ return; -+ } -+ bm_buffer_set64(&bmb, addr); -+ } -+ -+ while (bman_release(dpa_bp->pool, &bmb, 1, 0)) -+ cpu_relax(); -+} -+EXPORT_SYMBOL(dpa_fd_release); -+ -+void count_ern(struct dpa_percpu_priv_s *percpu_priv, -+ const struct qm_mr_entry *msg) -+{ -+ switch (msg->ern.rc & QM_MR_RC_MASK) { -+ case QM_MR_RC_CGR_TAILDROP: -+ percpu_priv->ern_cnt.cg_tdrop++; -+ break; -+ case QM_MR_RC_WRED: -+ percpu_priv->ern_cnt.wred++; -+ break; -+ case QM_MR_RC_ERROR: -+ percpu_priv->ern_cnt.err_cond++; -+ break; -+ case QM_MR_RC_ORPWINDOW_EARLY: -+ percpu_priv->ern_cnt.early_window++; -+ break; -+ case QM_MR_RC_ORPWINDOW_LATE: -+ percpu_priv->ern_cnt.late_window++; -+ break; -+ case QM_MR_RC_FQ_TAILDROP: -+ percpu_priv->ern_cnt.fq_tdrop++; -+ break; -+ case QM_MR_RC_ORPWINDOW_RETIRED: -+ percpu_priv->ern_cnt.fq_retired++; -+ break; -+ case QM_MR_RC_ORP_ZERO: -+ percpu_priv->ern_cnt.orp_zero++; -+ break; -+ } -+} -+EXPORT_SYMBOL(count_ern); -+ -+/** -+ * Turn on HW checksum computation for this outgoing frame. -+ * If the current protocol is not something we support in this regard -+ * (or if the stack has already computed the SW checksum), we do nothing. -+ * -+ * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value -+ * otherwise. -+ * -+ * Note that this function may modify the fd->cmd field and the skb data buffer -+ * (the Parse Results area). -+ */ -+int dpa_enable_tx_csum(struct dpa_priv_s *priv, -+ struct sk_buff *skb, struct qm_fd *fd, char *parse_results) -+{ -+ fm_prs_result_t *parse_result; -+ struct iphdr *iph; -+ struct ipv6hdr *ipv6h = NULL; -+ u8 l4_proto; -+ u16 ethertype = ntohs(skb->protocol); -+ int retval = 0; -+ -+ if (skb->ip_summed != CHECKSUM_PARTIAL) -+ return 0; -+ -+ /* Note: L3 csum seems to be already computed in sw, but we can't choose -+ * L4 alone from the FM configuration anyway. -+ */ -+ -+ /* Fill in some fields of the Parse Results array, so the FMan -+ * can find them as if they came from the FMan Parser. -+ */ -+ parse_result = (fm_prs_result_t *)parse_results; -+ -+ /* If we're dealing with VLAN, get the real Ethernet type */ -+ if (ethertype == ETH_P_8021Q) { -+ /* We can't always assume the MAC header is set correctly -+ * by the stack, so reset to beginning of skb->data -+ */ -+ skb_reset_mac_header(skb); -+ ethertype = ntohs(vlan_eth_hdr(skb)->h_vlan_encapsulated_proto); -+ } -+ -+ /* Fill in the relevant L3 parse result fields -+ * and read the L4 protocol type -+ */ -+ switch (ethertype) { -+ case ETH_P_IP: -+ parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4); -+ iph = ip_hdr(skb); -+ DPA_BUG_ON(iph == NULL); -+ l4_proto = iph->protocol; -+ break; -+ case ETH_P_IPV6: -+ parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6); -+ ipv6h = ipv6_hdr(skb); -+ DPA_BUG_ON(ipv6h == NULL); -+ l4_proto = ipv6h->nexthdr; -+ break; -+ default: -+ /* We shouldn't even be here */ -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_alert(priv->net_dev, -+ "Can't compute HW csum for L3 proto 0x%x\n", -+ ntohs(skb->protocol)); -+ retval = -EIO; -+ goto return_error; -+ } -+ -+ /* Fill in the relevant L4 parse result fields */ -+ switch (l4_proto) { -+ case IPPROTO_UDP: -+ parse_result->l4r = FM_L4_PARSE_RESULT_UDP; -+ break; -+ case IPPROTO_TCP: -+ parse_result->l4r = FM_L4_PARSE_RESULT_TCP; -+ break; -+ default: -+ /* This can as well be a BUG() */ -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_alert(priv->net_dev, -+ "Can't compute HW csum for L4 proto 0x%x\n", -+ l4_proto); -+ retval = -EIO; -+ goto return_error; -+ } -+ -+ /* At index 0 is IPOffset_1 as defined in the Parse Results */ -+ parse_result->ip_off[0] = (uint8_t)skb_network_offset(skb); -+ parse_result->l4_off = (uint8_t)skb_transport_offset(skb); -+ -+ /* Enable L3 (and L4, if TCP or UDP) HW checksum. */ -+ fd->cmd |= FM_FD_CMD_RPD | FM_FD_CMD_DTC; -+ -+ /* On P1023 and similar platforms fd->cmd interpretation could -+ * be disabled by setting CONTEXT_A bit ICMD; currently this bit -+ * is not set so we do not need to check; in the future, if/when -+ * using context_a we need to check this bit -+ */ -+ -+return_error: -+ return retval; -+} -+EXPORT_SYMBOL(dpa_enable_tx_csum); -+ -+#ifdef CONFIG_FSL_DPAA_CEETM -+void dpa_enable_ceetm(struct net_device *dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(dev); -+ priv->ceetm_en = true; -+} -+EXPORT_SYMBOL(dpa_enable_ceetm); -+ -+void dpa_disable_ceetm(struct net_device *dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(dev); -+ priv->ceetm_en = false; -+} -+EXPORT_SYMBOL(dpa_disable_ceetm); -+#endif ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_common.h -@@ -0,0 +1,227 @@ -+/* Copyright 2008-2013 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __DPAA_ETH_COMMON_H -+#define __DPAA_ETH_COMMON_H -+ -+#include /* struct net_device */ -+#include /* struct bm_buffer */ -+#include /* struct platform_device */ -+#include /* struct hwtstamp_config */ -+ -+#include "dpaa_eth.h" -+#include "lnxwrp_fsl_fman.h" -+ -+#define dpaa_eth_init_port(type, port, param, errq_id, defq_id, buf_layout,\ -+ frag_enabled) \ -+{ \ -+ param.errq = errq_id; \ -+ param.defq = defq_id; \ -+ param.priv_data_size = buf_layout->priv_data_size; \ -+ param.parse_results = buf_layout->parse_results; \ -+ param.hash_results = buf_layout->hash_results; \ -+ param.frag_enable = frag_enabled; \ -+ param.time_stamp = buf_layout->time_stamp; \ -+ param.manip_extra_space = buf_layout->manip_extra_space; \ -+ param.data_align = buf_layout->data_align; \ -+ fm_set_##type##_port_params(port, ¶m); \ -+} -+ -+#define DPA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */ -+ -+#ifdef DPAA_LS1043A_DMA_4K_ISSUE -+/* each S/G entry can be divided into two S/G entries */ -+#define DPA_SGT_ENTRIES_THRESHOLD 7 -+#else -+#define DPA_SGT_ENTRIES_THRESHOLD DPA_SGT_MAX_ENTRIES -+#endif /* DPAA_LS1043A_DMA_4K_ISSUE */ -+ -+ -+#define DPA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */ -+ -+/* return codes for the dpaa-eth hooks */ -+enum dpaa_eth_hook_result { -+ /* fd/skb was retained by the hook. -+ * -+ * On the Rx path, this means the Ethernet driver will _not_ -+ * deliver the skb to the stack. Instead, the hook implementation -+ * is expected to properly dispose of the skb. -+ * -+ * On the Tx path, the Ethernet driver's dpa_tx() function will -+ * immediately return NETDEV_TX_OK. The hook implementation is expected -+ * to free the skb. *DO*NOT* release it to BMan, or enqueue it to FMan, -+ * unless you know exactly what you're doing! -+ * -+ * On the confirmation/error paths, the Ethernet driver will _not_ -+ * perform any fd cleanup, nor update the interface statistics. -+ */ -+ DPAA_ETH_STOLEN, -+ /* fd/skb was returned to the Ethernet driver for regular processing. -+ * The hook is not allowed to, for instance, reallocate the skb (as if -+ * by linearizing, copying, cloning or reallocating the headroom). -+ */ -+ DPAA_ETH_CONTINUE -+}; -+ -+typedef enum dpaa_eth_hook_result (*dpaa_eth_ingress_hook_t)( -+ struct sk_buff *skb, struct net_device *net_dev, u32 fqid); -+typedef enum dpaa_eth_hook_result (*dpaa_eth_egress_hook_t)( -+ struct sk_buff *skb, struct net_device *net_dev); -+typedef enum dpaa_eth_hook_result (*dpaa_eth_confirm_hook_t)( -+ struct net_device *net_dev, const struct qm_fd *fd, u32 fqid); -+ -+/* used in napi related functions */ -+extern u16 qman_portal_max; -+ -+/* from dpa_ethtool.c */ -+extern const struct ethtool_ops dpa_ethtool_ops; -+ -+#ifdef CONFIG_FSL_DPAA_HOOKS -+/* Various hooks used for unit-testing and/or fastpath optimizations. -+ * Currently only one set of such hooks is supported. -+ */ -+struct dpaa_eth_hooks_s { -+ /* Invoked on the Tx private path, immediately after receiving the skb -+ * from the stack. -+ */ -+ dpaa_eth_egress_hook_t tx; -+ -+ /* Invoked on the Rx private path, right before passing the skb -+ * up the stack. At that point, the packet's protocol id has already -+ * been set. The skb's data pointer is now at the L3 header, and -+ * skb->mac_header points to the L2 header. skb->len has been adjusted -+ * to be the length of L3+payload (i.e., the length of the -+ * original frame minus the L2 header len). -+ * For more details on what the skb looks like, see eth_type_trans(). -+ */ -+ dpaa_eth_ingress_hook_t rx_default; -+ -+ /* Driver hook for the Rx error private path. */ -+ dpaa_eth_confirm_hook_t rx_error; -+ /* Driver hook for the Tx confirmation private path. */ -+ dpaa_eth_confirm_hook_t tx_confirm; -+ /* Driver hook for the Tx error private path. */ -+ dpaa_eth_confirm_hook_t tx_error; -+}; -+ -+void fsl_dpaa_eth_set_hooks(struct dpaa_eth_hooks_s *hooks); -+ -+extern struct dpaa_eth_hooks_s dpaa_eth_hooks; -+#endif -+ -+int dpa_netdev_init(struct net_device *net_dev, -+ const uint8_t *mac_addr, -+ uint16_t tx_timeout); -+int __cold dpa_start(struct net_device *net_dev); -+int __cold dpa_stop(struct net_device *net_dev); -+void __cold dpa_timeout(struct net_device *net_dev); -+struct rtnl_link_stats64 * __cold -+dpa_get_stats64(struct net_device *net_dev, -+ struct rtnl_link_stats64 *stats); -+int dpa_change_mtu(struct net_device *net_dev, int new_mtu); -+int dpa_ndo_init(struct net_device *net_dev); -+int dpa_set_features(struct net_device *dev, netdev_features_t features); -+netdev_features_t dpa_fix_features(struct net_device *dev, -+ netdev_features_t features); -+#ifdef CONFIG_FSL_DPAA_TS -+u64 dpa_get_timestamp_ns(const struct dpa_priv_s *priv, -+ enum port_type rx_tx, const void *data); -+/* Updates the skb shared hw timestamp from the hardware timestamp */ -+int dpa_get_ts(const struct dpa_priv_s *priv, enum port_type rx_tx, -+ struct skb_shared_hwtstamps *shhwtstamps, const void *data); -+#endif /* CONFIG_FSL_DPAA_TS */ -+int dpa_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); -+int __cold dpa_remove(struct platform_device *of_dev); -+struct mac_device * __cold __must_check -+__attribute__((nonnull)) dpa_mac_probe(struct platform_device *_of_dev); -+int dpa_set_mac_address(struct net_device *net_dev, void *addr); -+void dpa_set_rx_mode(struct net_device *net_dev); -+void dpa_set_buffers_layout(struct mac_device *mac_dev, -+ struct dpa_buffer_layout_s *layout); -+int __attribute__((nonnull)) -+dpa_bp_alloc(struct dpa_bp *dpa_bp); -+void __cold __attribute__((nonnull)) -+dpa_bp_free(struct dpa_priv_s *priv); -+struct dpa_bp *dpa_bpid2pool(int bpid); -+void dpa_bpid2pool_map(int bpid, struct dpa_bp *dpa_bp); -+bool dpa_bpid2pool_use(int bpid); -+void dpa_bp_drain(struct dpa_bp *bp); -+#ifdef CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE -+u16 dpa_select_queue(struct net_device *net_dev, struct sk_buff *skb, -+ void *accel_priv, select_queue_fallback_t fallback); -+#endif -+struct dpa_fq *dpa_fq_alloc(struct device *dev, -+ u32 fq_start, -+ u32 fq_count, -+ struct list_head *list, -+ enum dpa_fq_type fq_type); -+int dpa_fq_probe_mac(struct device *dev, struct list_head *list, -+ struct fm_port_fqs *port_fqs, -+ bool tx_conf_fqs_per_core, -+ enum port_type ptype); -+int dpa_get_channel(void); -+void dpa_release_channel(void); -+int dpaa_eth_add_channel(void *__arg); -+int dpaa_eth_cgr_init(struct dpa_priv_s *priv); -+void dpa_fq_setup(struct dpa_priv_s *priv, const struct dpa_fq_cbs_t *fq_cbs, -+ struct fm_port *tx_port); -+int dpa_fq_init(struct dpa_fq *dpa_fq, bool td_enable); -+int __cold __attribute__((nonnull)) -+dpa_fq_free(struct device *dev, struct list_head *list); -+void dpaa_eth_init_ports(struct mac_device *mac_dev, -+ struct dpa_bp *bp, size_t count, -+ struct fm_port_fqs *port_fqs, -+ struct dpa_buffer_layout_s *buf_layout, -+ struct device *dev); -+void dpa_release_sgt(struct qm_sg_entry *sgt); -+void __attribute__((nonnull)) -+dpa_fd_release(const struct net_device *net_dev, const struct qm_fd *fd); -+void count_ern(struct dpa_percpu_priv_s *percpu_priv, -+ const struct qm_mr_entry *msg); -+int dpa_enable_tx_csum(struct dpa_priv_s *priv, -+ struct sk_buff *skb, struct qm_fd *fd, char *parse_results); -+#ifdef CONFIG_FSL_DPAA_CEETM -+void dpa_enable_ceetm(struct net_device *dev); -+void dpa_disable_ceetm(struct net_device *dev); -+#endif -+struct proxy_device { -+ struct mac_device *mac_dev; -+}; -+ -+/* mac device control functions exposed by proxy interface*/ -+int dpa_proxy_start(struct net_device *net_dev); -+int dpa_proxy_stop(struct proxy_device *proxy_dev, struct net_device *net_dev); -+int dpa_proxy_set_mac_address(struct proxy_device *proxy_dev, -+ struct net_device *net_dev); -+int dpa_proxy_set_rx_mode(struct proxy_device *proxy_dev, -+ struct net_device *net_dev); -+ -+#endif /* __DPAA_ETH_COMMON_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_generic.c -@@ -0,0 +1,1735 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dpaa_eth.h" -+#include "dpaa_eth_common.h" -+#include "dpaa_eth_base.h" -+#include "dpaa_eth_generic.h" -+ -+#define DPA_DEFAULT_TX_HEADROOM 64 -+#define DPA_GENERIC_SKB_COPY_MAX_SIZE 256 -+#define DPA_GENERIC_NAPI_WEIGHT 64 -+#define DPA_GENERIC_DESCRIPTION "FSL DPAA Generic Ethernet driver" -+#define DPA_GENERIC_BUFFER_QUOTA 4 -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION(DPA_GENERIC_DESCRIPTION); -+ -+static uint8_t generic_debug = -1; -+module_param(generic_debug, byte, S_IRUGO); -+MODULE_PARM_DESC(generic_debug, "Module/Driver verbosity level"); -+ -+/* This has to work in tandem with the DPA_CS_THRESHOLD_xxx values. */ -+static uint16_t tx_timeout = 1000; -+module_param(tx_timeout, ushort, S_IRUGO); -+MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms"); -+ -+struct rtnl_link_stats64 *__cold -+dpa_generic_get_stats64(struct net_device *netdev, -+ struct rtnl_link_stats64 *stats); -+static int dpa_generic_set_mac_address(struct net_device *net_dev, -+ void *addr); -+static int __cold dpa_generic_start(struct net_device *netdev); -+static int __cold dpa_generic_stop(struct net_device *netdev); -+static int dpa_generic_eth_probe(struct platform_device *_of_dev); -+static int dpa_generic_remove(struct platform_device *of_dev); -+static void dpa_generic_ern(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_mr_entry *msg); -+static int __hot dpa_generic_tx(struct sk_buff *skb, -+ struct net_device *netdev); -+static void dpa_generic_drain_bp(struct dpa_bp *bp, u8 nbuf); -+static void dpa_generic_drain_sg_bp(struct dpa_bp *sg_bp, u8 nbuf); -+ -+static const struct net_device_ops dpa_generic_ops = { -+ .ndo_open = dpa_generic_start, -+ .ndo_start_xmit = dpa_generic_tx, -+ .ndo_stop = dpa_generic_stop, -+ .ndo_set_mac_address = dpa_generic_set_mac_address, -+ .ndo_tx_timeout = dpa_timeout, -+ .ndo_get_stats64 = dpa_generic_get_stats64, -+ .ndo_init = dpa_ndo_init, -+ .ndo_set_features = dpa_set_features, -+ .ndo_fix_features = dpa_fix_features, -+ .ndo_change_mtu = dpa_change_mtu, -+}; -+ -+static void dpa_generic_draining_timer(unsigned long arg) -+{ -+ struct dpa_generic_priv_s *priv = (struct dpa_generic_priv_s *)arg; -+ -+ dpa_generic_drain_bp(priv->draining_tx_bp, DPA_GENERIC_BUFFER_QUOTA); -+ dpa_generic_drain_sg_bp(priv->draining_tx_sg_bp, -+ DPA_GENERIC_BUFFER_QUOTA); -+ -+ if (priv->net_dev->flags & IFF_UP) -+ mod_timer(&(priv->timer), jiffies + 1); -+} -+ -+struct rtnl_link_stats64 *__cold -+dpa_generic_get_stats64(struct net_device *netdev, -+ struct rtnl_link_stats64 *stats) -+{ -+ struct dpa_generic_priv_s *priv = netdev_priv(netdev); -+ u64 *cpustats; -+ u64 *netstats = (u64 *)stats; -+ int i, j; -+ struct dpa_percpu_priv_s *percpu_priv; -+ int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64); -+ -+ for_each_online_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ -+ cpustats = (u64 *)&percpu_priv->stats; -+ -+ for (j = 0; j < numstats; j++) -+ netstats[j] += cpustats[j]; -+ } -+ -+ return stats; -+} -+ -+static int dpa_generic_set_mac_address(struct net_device *net_dev, -+ void *addr) -+{ -+ const struct dpa_generic_priv_s *priv = netdev_priv(net_dev); -+ int _errno; -+ -+ _errno = eth_mac_addr(net_dev, addr); -+ if (_errno < 0) { -+ if (netif_msg_drv(priv)) -+ netdev_err(net_dev, "eth_mac_addr() = %d\n", _errno); -+ return _errno; -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id dpa_generic_match[] = { -+ { -+ .compatible = "fsl,dpa-ethernet-generic" -+ }, -+ {} -+}; -+ -+MODULE_DEVICE_TABLE(of, dpa_generic_match); -+ -+static struct platform_driver dpa_generic_driver = { -+ .driver = { -+ .name = KBUILD_MODNAME, -+ .of_match_table = dpa_generic_match, -+ .owner = THIS_MODULE, -+ }, -+ .probe = dpa_generic_eth_probe, -+ .remove = dpa_generic_remove -+}; -+ -+static int get_port_ref(struct device_node *dev_node, -+ struct fm_port **port) -+{ -+ struct platform_device *port_of_dev = NULL; -+ struct device *op_dev = NULL; -+ struct device_node *port_node = NULL; -+ -+ port_node = of_parse_phandle(dev_node, "fsl,fman-oh-port", 0); -+ if (port_node == NULL) -+ return -EINVAL; -+ -+ port_of_dev = of_find_device_by_node(port_node); -+ of_node_put(port_node); -+ -+ if (port_of_dev == NULL) -+ return -EINVAL; -+ -+ /* get the reference to oh port from FMD */ -+ op_dev = &port_of_dev->dev; -+ *port = fm_port_bind(op_dev); -+ -+ if (*port == NULL) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static void dpaa_generic_napi_enable(struct dpa_generic_priv_s *priv) -+{ -+ struct dpa_percpu_priv_s *percpu_priv; -+ int i, j; -+ -+ for_each_possible_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ -+ for (j = 0; j < qman_portal_max; j++) -+ napi_enable(&percpu_priv->np[j].napi); -+ } -+} -+ -+static void dpaa_generic_napi_disable(struct dpa_generic_priv_s *priv) -+{ -+ struct dpa_percpu_priv_s *percpu_priv; -+ int i, j; -+ -+ for_each_possible_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ -+ for (j = 0; j < qman_portal_max; j++) -+ napi_disable(&percpu_priv->np[j].napi); -+ } -+} -+ -+static struct device_node *get_rx_op_port_node(struct platform_device *_of_dev) -+{ -+ struct device *dev = &_of_dev->dev; -+ struct device_node *port_node = NULL; -+ struct device_node *onic_node = NULL; -+ int num_ports = 0; -+ -+ onic_node = dev->of_node; -+ -+ num_ports = of_count_phandle_with_args(onic_node, "fsl,oh-ports", NULL); -+ if (num_ports != 2) { -+ dev_err(dev, "There should be two O/H port handles in the device tree\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ port_node = of_parse_phandle(onic_node, "fsl,oh-ports", 0); -+ if (port_node == NULL) { -+ dev_err(dev, "Cannot find O/H port node in the device tree\n"); -+ return ERR_PTR(-EFAULT); -+ } -+ -+ return port_node; -+} -+ -+static int __cold dpa_generic_start(struct net_device *netdev) -+{ -+ struct dpa_generic_priv_s *priv = netdev_priv(netdev); -+ -+ /* seed default buffer pool */ -+ dpa_bp_priv_seed(priv->rx_bp); -+ -+ dpaa_generic_napi_enable(priv); -+ netif_tx_start_all_queues(netdev); -+ -+ mod_timer(&priv->timer, jiffies + 100); -+ -+ return 0; -+} -+ -+static int __cold dpa_generic_stop(struct net_device *netdev) -+{ -+ struct dpa_generic_priv_s *priv = netdev_priv(netdev); -+ -+ netif_tx_stop_all_queues(netdev); -+ dpaa_generic_napi_disable(priv); -+ -+ return 0; -+} -+ -+static enum qman_cb_dqrr_result __hot -+dpa_generic_rx_err_dqrr(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq) -+{ -+ struct net_device *netdev; -+ struct dpa_generic_priv_s *priv; -+ struct dpa_percpu_priv_s *percpu_priv; -+ const struct qm_fd *fd; -+ int *countptr; -+ -+ netdev = ((struct dpa_fq *)fq)->net_dev; -+ priv = netdev_priv(netdev); -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ countptr = raw_cpu_ptr(priv->rx_bp->percpu_count); -+ fd = &dq->fd; -+ -+ /* TODO: extract bpid from the fd; when multiple bps are supported -+ * there won't be a default bp -+ */ -+ -+ if (dpaa_eth_napi_schedule(percpu_priv, portal)) -+ return qman_cb_dqrr_stop; -+ -+ if (unlikely(dpaa_eth_refill_bpools(priv->rx_bp, countptr))) { -+ /* Unable to refill the buffer pool due to insufficient -+ * system memory. Just release the frame back into the pool, -+ * otherwise we'll soon end up with an empty buffer pool. -+ */ -+ dpa_fd_release(netdev, fd); -+ goto qman_consume; -+ } -+ -+ /* limit common, possibly innocuous Rx FIFO Overflow errors' -+ * interference with zero-loss convergence benchmark results. -+ */ -+ if (likely(fd->status & FM_FD_STAT_ERR_PHYSICAL)) -+ pr_warn_once("fsl-dpa: non-zero error counters in fman statistics (sysfs)\n"); -+ else -+ if (netif_msg_hw(priv) && net_ratelimit()) -+ netdev_err(netdev, "Err FD status 2 = 0x%08x\n", -+ fd->status & FM_FD_STAT_RX_ERRORS); -+ -+ -+ percpu_priv->stats.rx_errors++; -+ -+ if (fd->status & FM_PORT_FRM_ERR_DMA) -+ percpu_priv->rx_errors.dme++; -+ if (fd->status & FM_PORT_FRM_ERR_PHYSICAL) -+ percpu_priv->rx_errors.fpe++; -+ if (fd->status & FM_PORT_FRM_ERR_SIZE) -+ percpu_priv->rx_errors.fse++; -+ if (fd->status & FM_PORT_FRM_ERR_PRS_HDR_ERR) -+ percpu_priv->rx_errors.phe++; -+ -+ /* TODO dpa_csum_validation */ -+ -+ dpa_fd_release(netdev, fd); -+ -+qman_consume: -+ return qman_cb_dqrr_consume; -+} -+ -+ -+static enum qman_cb_dqrr_result __hot -+dpa_generic_rx_dqrr(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq) -+{ -+ struct net_device *netdev; -+ struct dpa_generic_priv_s *priv; -+ struct dpa_bp *bp; -+ struct dpa_percpu_priv_s *percpu_priv; -+ struct sk_buff **skbh; -+ struct sk_buff *skb; -+ const struct qm_fd *fd = &dq->fd; -+ unsigned int skb_len; -+ u32 fd_status = fd->status; -+ u64 pad; -+ dma_addr_t addr = qm_fd_addr(fd); -+ unsigned int data_start; -+ unsigned long skb_addr; -+ int *countptr; -+ -+ netdev = ((struct dpa_fq *)fq)->net_dev; -+ priv = netdev_priv(netdev); -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ countptr = raw_cpu_ptr(priv->rx_bp->percpu_count); -+ -+ /* This is needed for TCP traffic as draining only on TX is not -+ * enough -+ */ -+ dpa_generic_drain_bp(priv->draining_tx_bp, 1); -+ dpa_generic_drain_sg_bp(priv->draining_tx_sg_bp, 1); -+ -+ if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal))) -+ return qman_cb_dqrr_stop; -+ -+ if (unlikely(dpaa_eth_refill_bpools(priv->rx_bp, countptr))) { -+ /* Unable to refill the buffer pool due to insufficient -+ * system memory. Just release the frame back into the pool, -+ * otherwise we'll soon end up with an empty buffer pool. -+ */ -+ dpa_fd_release(netdev, fd); -+ goto qman_consume; -+ } -+ -+ DPA_READ_SKB_PTR(skb, skbh, phys_to_virt(addr), -1); -+ -+ if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) { -+ if (netif_msg_hw(priv) && net_ratelimit()) -+ netdev_warn(netdev, "FD status = 0x%08x\n", -+ fd->status & FM_FD_STAT_RX_ERRORS); -+ -+ percpu_priv->stats.rx_errors++; -+ dpa_fd_release(netdev, fd); -+ goto qman_consume; -+ } -+ if (unlikely(fd->format != qm_fd_contig)) { -+ percpu_priv->stats.rx_dropped++; -+ if (netif_msg_rx_status(priv) && net_ratelimit()) -+ netdev_warn(netdev, "Dropping a SG frame\n"); -+ dpa_fd_release(netdev, fd); -+ goto qman_consume; -+ } -+ -+ bp = dpa_bpid2pool(fd->bpid); -+ -+ /* find out the pad */ -+ skb_addr = virt_to_phys(skb->head); -+ pad = addr - skb_addr; -+ -+ dma_unmap_single(bp->dev, addr, bp->size, DMA_BIDIRECTIONAL); -+ -+ countptr = raw_cpu_ptr(bp->percpu_count); -+ (*countptr)--; -+ -+ /* The skb is currently pointed at head + headroom. The packet -+ * starts at skb->head + pad + fd offset. -+ */ -+ data_start = (unsigned int)(pad + dpa_fd_offset(fd) - -+ skb_headroom(skb)); -+ skb_put(skb, dpa_fd_length(fd) + data_start); -+ skb_pull(skb, data_start); -+ skb->protocol = eth_type_trans(skb, netdev); -+ if (unlikely(dpa_check_rx_mtu(skb, netdev->mtu))) { -+ percpu_priv->stats.rx_dropped++; -+ dev_kfree_skb(skb); -+ goto qman_consume; -+ } -+ -+ skb_len = skb->len; -+ -+ if (fd->status & FM_FD_STAT_L4CV) -+ skb->ip_summed = CHECKSUM_UNNECESSARY; -+ else -+ skb->ip_summed = CHECKSUM_NONE; -+ -+ if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) -+ goto qman_consume; -+ -+ percpu_priv->stats.rx_packets++; -+ percpu_priv->stats.rx_bytes += skb_len; -+ -+qman_consume: -+ return qman_cb_dqrr_consume; -+} -+ -+static void dpa_generic_drain_sg_bp(struct dpa_bp *sgbp, u8 nbuf) -+{ -+ int ret; -+ struct bm_buffer bmb[8]; -+ -+ do { -+ ret = bman_acquire(sgbp->pool, bmb, nbuf, 0); -+ } while (ret >= 0); -+} -+ -+inline void dpa_release_sg(struct sk_buff *skb, dma_addr_t addr, -+ struct dpa_bp *bp) -+{ -+ struct qm_sg_entry *sgt = phys_to_virt(addr + DPA_DEFAULT_TX_HEADROOM); -+ int nr_frags = skb_shinfo(skb)->nr_frags; -+ dma_addr_t sg_addr; -+ int j; -+ -+ dma_unmap_single(bp->dev, addr, DPA_DEFAULT_TX_HEADROOM + -+ sizeof(struct qm_sg_entry) * (1 + nr_frags), -+ DMA_BIDIRECTIONAL); -+ -+ for (j = 0; j <= nr_frags; j++) { -+ DPA_BUG_ON(sgt[j].extension); -+ sg_addr = qm_sg_addr(&sgt[j]); -+ dma_unmap_page(bp->dev, sg_addr, -+ sgt[j].length, DMA_BIDIRECTIONAL); -+ } -+ -+ dev_kfree_skb_any(skb); -+} -+ -+inline void dpa_release_contig(struct sk_buff *skb, dma_addr_t addr, -+ struct dpa_bp *bp) -+{ -+ dma_unmap_single(bp->dev, addr, bp->size, DMA_BIDIRECTIONAL); -+ dev_kfree_skb_any(skb); -+} -+ -+static void dpa_generic_drain_bp(struct dpa_bp *bp, u8 nbuf) -+{ -+ int ret, i; -+ struct bm_buffer bmb[8]; -+ dma_addr_t addr; -+ int *countptr = raw_cpu_ptr(bp->percpu_count); -+ int count = *countptr; -+ struct sk_buff **skbh; -+ -+ do { -+ /* bman_acquire will fail if nbuf > 8 */ -+ ret = bman_acquire(bp->pool, bmb, nbuf, 0); -+ if (ret > 0) { -+ for (i = 0; i < nbuf; i++) { -+ addr = bm_buf_addr(&bmb[i]); -+ skbh = (struct sk_buff **)phys_to_virt(addr); -+ dma_unmap_single(bp->dev, addr, bp->size, -+ DMA_TO_DEVICE); -+ -+ if (skb_is_nonlinear(*skbh)) -+ dpa_release_sg(*skbh, addr, bp); -+ else -+ dpa_release_contig(*skbh, addr, bp); -+ } -+ count -= i; -+ } -+ } while (ret > 0); -+ -+ *countptr = count; -+} -+ -+/** -+ * Turn on HW checksum computation for this outgoing frame. -+ * If the current protocol is not something we support in this regard -+ * (or if the stack has already computed the SW checksum), we do nothing. -+ * -+ * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value -+ * otherwise. -+ * -+ * Note that this function may modify the fd->cmd field and the skb data buffer -+ * (the Parse Results area). -+ */ -+static int dpa_generic_tx_csum(struct dpa_generic_priv_s *priv, -+ struct sk_buff *skb, -+ struct qm_fd *fd, -+ char *parse_results) -+{ -+ fm_prs_result_t *parse_result; -+ struct iphdr *iph; -+ struct ipv6hdr *ipv6h = NULL; -+ int l4_proto; -+ int ethertype = ntohs(skb->protocol); -+ int retval = 0; -+ -+ if (skb->ip_summed != CHECKSUM_PARTIAL) -+ return 0; -+ -+ /* Note: L3 csum seems to be already computed in sw, but we can't choose -+ * L4 alone from the FM configuration anyway. -+ */ -+ -+ /* Fill in some fields of the Parse Results array, so the FMan -+ * can find them as if they came from the FMan Parser. -+ */ -+ parse_result = (fm_prs_result_t *)parse_results; -+ -+ /* If we're dealing with VLAN, get the real Ethernet type */ -+ if (ethertype == ETH_P_8021Q) { -+ /* We can't always assume the MAC header is set correctly -+ * by the stack, so reset to beginning of skb->data -+ */ -+ skb_reset_mac_header(skb); -+ ethertype = ntohs(vlan_eth_hdr(skb)->h_vlan_encapsulated_proto); -+ } -+ -+ /* Fill in the relevant L3 parse result fields -+ * and read the L4 protocol type -+ */ -+ switch (ethertype) { -+ case ETH_P_IP: -+ parse_result->l3r = FM_L3_PARSE_RESULT_IPV4; -+ iph = ip_hdr(skb); -+ BUG_ON(iph == NULL); -+ l4_proto = iph->protocol; -+ break; -+ case ETH_P_IPV6: -+ parse_result->l3r = FM_L3_PARSE_RESULT_IPV6; -+ ipv6h = ipv6_hdr(skb); -+ BUG_ON(ipv6h == NULL); -+ l4_proto = ipv6h->nexthdr; -+ break; -+ default: -+ /* We shouldn't even be here */ -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_alert(priv->net_dev, -+ "Can't compute HW csum for L3 proto 0x%x\n", -+ ntohs(skb->protocol)); -+ retval = -EIO; -+ goto return_error; -+ } -+ -+ /* Fill in the relevant L4 parse result fields */ -+ switch (l4_proto) { -+ case IPPROTO_UDP: -+ parse_result->l4r = FM_L4_PARSE_RESULT_UDP; -+ break; -+ case IPPROTO_TCP: -+ parse_result->l4r = FM_L4_PARSE_RESULT_TCP; -+ break; -+ default: -+ /* This can as well be a BUG() */ -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_alert(priv->net_dev, -+ "Can't compute HW csum for L4 proto 0x%x\n", -+ l4_proto); -+ retval = -EIO; -+ goto return_error; -+ } -+ -+ /* At index 0 is IPOffset_1 as defined in the Parse Results */ -+ parse_result->ip_off[0] = (uint8_t)skb_network_offset(skb); -+ parse_result->l4_off = (uint8_t)skb_transport_offset(skb); -+ -+ /* Enable L3 (and L4, if TCP or UDP) HW checksum. */ -+ fd->cmd |= FM_FD_CMD_RPD | FM_FD_CMD_DTC; -+ -+ /* On P1023 and similar platforms fd->cmd interpretation could -+ * be disabled by setting CONTEXT_A bit ICMD; currently this bit -+ * is not set so we do not need to check; in the future, if/when -+ * using context_a we need to check this bit -+ */ -+ -+return_error: -+ return retval; -+} -+ -+static inline int generic_skb_to_sg_fd(struct dpa_generic_priv_s *priv, -+ struct sk_buff *skb, struct qm_fd *fd) -+{ -+ struct dpa_bp *dpa_bp = priv->draining_tx_bp; -+ struct dpa_bp *dpa_sg_bp = priv->draining_tx_sg_bp; -+ dma_addr_t addr; -+ struct sk_buff **skbh; -+ struct net_device *net_dev = priv->net_dev; -+ int err; -+ -+ struct qm_sg_entry *sgt; -+ void *sgt_buf; -+ void *buffer_start; -+ skb_frag_t *frag; -+ int i, j; -+ const enum dma_data_direction dma_dir = DMA_BIDIRECTIONAL; -+ const int nr_frags = skb_shinfo(skb)->nr_frags; -+ -+ memset(fd, 0, sizeof(*fd)); -+ fd->format = qm_fd_sg; -+ -+ /* get a page frag to store the SGTable */ -+ sgt_buf = netdev_alloc_frag(priv->tx_headroom + -+ sizeof(struct qm_sg_entry) * (1 + nr_frags)); -+ if (unlikely(!sgt_buf)) { -+ dev_err(dpa_bp->dev, "netdev_alloc_frag() failed\n"); -+ return -ENOMEM; -+ } -+ -+ memset(sgt_buf, 0, priv->tx_headroom + -+ sizeof(struct qm_sg_entry) * (1 + nr_frags)); -+ -+ /* do this before dma_map_single(DMA_TO_DEVICE), because we may need to -+ * write into the skb. -+ */ -+ err = dpa_generic_tx_csum(priv, skb, fd, -+ sgt_buf + DPA_TX_PRIV_DATA_SIZE); -+ if (unlikely(err < 0)) { -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_err(net_dev, "HW csum error: %d\n", err); -+ goto csum_failed; -+ } -+ -+ sgt = (struct qm_sg_entry *)(sgt_buf + priv->tx_headroom); -+ sgt[0].bpid = dpa_sg_bp->bpid; -+ sgt[0].offset = 0; -+ sgt[0].length = skb_headlen(skb); -+ sgt[0].extension = 0; -+ sgt[0].final = 0; -+ -+ addr = dma_map_single(dpa_sg_bp->dev, skb->data, sgt[0].length, -+ dma_dir); -+ if (unlikely(dma_mapping_error(dpa_sg_bp->dev, addr))) { -+ dev_err(dpa_sg_bp->dev, "DMA mapping failed"); -+ err = -EINVAL; -+ goto sg0_map_failed; -+ } -+ -+ sgt[0].addr_hi = (uint8_t)upper_32_bits(addr); -+ sgt[0].addr_lo = cpu_to_be32(lower_32_bits(addr)); -+ -+ /* populate the rest of SGT entries */ -+ for (i = 1; i <= nr_frags; i++) { -+ frag = &skb_shinfo(skb)->frags[i - 1]; -+ sgt[i].bpid = dpa_sg_bp->bpid; -+ sgt[i].offset = 0; -+ sgt[i].length = frag->size; -+ sgt[i].extension = 0; -+ sgt[i].final = 0; -+ -+ DPA_BUG_ON(!skb_frag_page(frag)); -+ addr = skb_frag_dma_map(dpa_bp->dev, frag, 0, sgt[i].length, -+ dma_dir); -+ if (unlikely(dma_mapping_error(dpa_sg_bp->dev, addr))) { -+ dev_err(dpa_sg_bp->dev, "DMA mapping failed"); -+ err = -EINVAL; -+ goto sg_map_failed; -+ } -+ -+ /* keep the offset in the address */ -+ sgt[i].addr_hi = (uint8_t)upper_32_bits(addr); -+ sgt[i].addr_lo = cpu_to_be32(lower_32_bits(addr)); -+ } -+ sgt[i - 1].final = 1; -+ -+ fd->length20 = skb->len; -+ fd->offset = priv->tx_headroom; -+ -+ /* DMA map the SGT page */ -+ buffer_start = (void *)sgt - dpa_fd_offset(fd); -+ /* Can't write at "negative" offset in buffer_start, because this skb -+ * may not have been allocated by us. -+ */ -+ DPA_WRITE_SKB_PTR(skb, skbh, buffer_start, 0); -+ -+ addr = dma_map_single(dpa_bp->dev, buffer_start, -+ priv->tx_headroom + sizeof(struct qm_sg_entry) * (1 + nr_frags), -+ dma_dir); -+ if (unlikely(dma_mapping_error(dpa_bp->dev, addr))) { -+ dev_err(dpa_bp->dev, "DMA mapping failed"); -+ err = -EINVAL; -+ goto sgt_map_failed; -+ } -+ -+ fd->bpid = dpa_bp->bpid; -+ fd->addr_hi = (uint8_t)upper_32_bits(addr); -+ fd->addr_lo = lower_32_bits(addr); -+ -+ return 0; -+ -+sgt_map_failed: -+sg_map_failed: -+ for (j = 0; j < i; j++) -+ dma_unmap_page(dpa_sg_bp->dev, qm_sg_addr(&sgt[j]), -+ be32_to_cpu(sgt[j].length), dma_dir); -+sg0_map_failed: -+csum_failed: -+ put_page(virt_to_head_page(sgt_buf)); -+ -+ return err; -+} -+ -+static int __hot dpa_generic_tx(struct sk_buff *skb, struct net_device *netdev) -+{ -+ struct dpa_generic_priv_s *priv = netdev_priv(netdev); -+ struct dpa_percpu_priv_s *percpu_priv = -+ raw_cpu_ptr(priv->percpu_priv); -+ struct rtnl_link_stats64 *percpu_stats = &percpu_priv->stats; -+ struct dpa_bp *bp = priv->draining_tx_bp; -+ struct dpa_bp *sg_bp = priv->draining_tx_sg_bp; -+ struct sk_buff **skbh = NULL; -+ dma_addr_t addr; -+ struct qm_fd fd; -+ int queue_mapping; -+ struct qman_fq *egress_fq; -+ const bool nonlinear = skb_is_nonlinear(skb); -+ int i = 0, err = 0; -+ int *countptr; -+ -+ if (nonlinear && skb_shinfo(skb)->nr_frags < DPA_SGT_MAX_ENTRIES) { -+ err = generic_skb_to_sg_fd(priv, skb, &fd); -+ if (unlikely(err < 0)) -+ goto sg_failed; -+ percpu_priv->tx_frag_skbuffs++; -+ addr = qm_fd_addr(&fd); -+ } else { -+ if (unlikely(skb_headroom(skb) < priv->tx_headroom)) { -+ struct sk_buff *skb_new; -+ -+ skb_new = skb_realloc_headroom(skb, priv->tx_headroom); -+ if (unlikely(!skb_new)) { -+ percpu_stats->tx_errors++; -+ kfree_skb(skb); -+ goto done; -+ } -+ -+ kfree_skb(skb); -+ skb = skb_new; -+ } -+ -+ clear_fd(&fd); -+ -+ /* store skb backpointer to release the skb later */ -+ skbh = (struct sk_buff **)(skb->data - priv->tx_headroom); -+ *skbh = skb; -+ -+ /* do this before dma_map_single(), because we may need to write -+ * into the skb. -+ */ -+ err = dpa_generic_tx_csum(priv, skb, &fd, -+ ((char *)skbh) + DPA_TX_PRIV_DATA_SIZE); -+ if (unlikely(err < 0)) { -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_err(netdev, "HW csum error: %d\n", err); -+ return err; -+ } -+ -+ addr = dma_map_single(bp->dev, skbh, -+ skb->len + priv->tx_headroom, DMA_TO_DEVICE); -+ if (unlikely(dma_mapping_error(bp->dev, addr))) { -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_err(netdev, "dma_map_single() failed\n"); -+ goto dma_mapping_failed; -+ } -+ -+ fd.format = qm_fd_contig; -+ fd.length20 = skb->len; -+ fd.offset = priv->tx_headroom; -+ fd.addr_hi = (uint8_t)upper_32_bits(addr); -+ fd.addr_lo = lower_32_bits(addr); -+ /* fd.cmd |= FM_FD_CMD_FCO; */ -+ fd.bpid = bp->bpid; -+ } -+ -+ dpa_generic_drain_bp(bp, 1); -+ dpa_generic_drain_sg_bp(sg_bp, 1); -+ -+ queue_mapping = dpa_get_queue_mapping(skb); -+ egress_fq = priv->egress_fqs[queue_mapping]; -+ -+ for (i = 0; i < 100000; i++) { -+ err = qman_enqueue(egress_fq, &fd, 0); -+ if (err != -EBUSY) -+ break; -+ } -+ -+ if (unlikely(err < 0)) { -+ percpu_stats->tx_fifo_errors++; -+ goto xmit_failed; -+ } -+ -+ countptr = raw_cpu_ptr(bp->percpu_count); -+ (*countptr)++; -+ -+ percpu_stats->tx_packets++; -+ percpu_stats->tx_bytes += fd.length20; -+ netdev->trans_start = jiffies; -+ -+ goto done; -+ -+xmit_failed: -+ dma_unmap_single(bp->dev, addr, fd.offset + fd.length20, DMA_TO_DEVICE); -+sg_failed: -+dma_mapping_failed: -+ percpu_stats->tx_errors++; -+ dev_kfree_skb(skb); -+done: -+ return NETDEV_TX_OK; -+} -+ -+static int dpa_generic_napi_add(struct net_device *net_dev) -+{ -+ struct dpa_generic_priv_s *priv = netdev_priv(net_dev); -+ struct dpa_percpu_priv_s *percpu_priv; -+ int i, cpu; -+ -+ for_each_possible_cpu(cpu) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu); -+ -+ percpu_priv->np = devm_kzalloc(net_dev->dev.parent, -+ qman_portal_max * sizeof(struct dpa_napi_portal), -+ GFP_KERNEL); -+ -+ if (unlikely(percpu_priv->np == NULL)) { -+ dev_err(net_dev->dev.parent, "devm_kzalloc() failed\n"); -+ return -ENOMEM; -+ } -+ -+ for (i = 0; i < qman_portal_max; i++) -+ netif_napi_add(net_dev, &percpu_priv->np[i].napi, -+ dpaa_eth_poll, DPA_GENERIC_NAPI_WEIGHT); -+ } -+ -+ return 0; -+} -+ -+static void dpa_generic_napi_del(struct net_device *net_dev) -+{ -+ struct dpa_generic_priv_s *priv = netdev_priv(net_dev); -+ struct dpa_percpu_priv_s *percpu_priv; -+ int i, cpu; -+ -+ for_each_possible_cpu(cpu) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu); -+ -+ if (percpu_priv->np) { -+ for (i = 0; i < qman_portal_max; i++) -+ netif_napi_del(&percpu_priv->np[i].napi); -+ -+ devm_kfree(net_dev->dev.parent, percpu_priv->np); -+ } -+ } -+} -+ -+ -+static int dpa_generic_netdev_init(struct device_node *dpa_node, -+ struct net_device *netdev) -+{ -+ struct dpa_generic_priv_s *priv = netdev_priv(netdev); -+ struct device *dev = netdev->dev.parent; -+ const uint8_t *mac_addr; -+ int err; -+ -+ netdev->netdev_ops = &dpa_generic_ops; -+ -+ mac_addr = of_get_mac_address(dpa_node); -+ if (mac_addr == NULL) { -+ if (netif_msg_probe(priv)) -+ dev_err(dev, "No virtual MAC address found!\n"); -+ return -EINVAL; -+ } -+ -+ netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG; -+ netdev->priv_flags |= IFF_LIVE_ADDR_CHANGE; -+ netdev->features |= netdev->hw_features; -+ netdev->vlan_features = netdev->features; -+ -+ memcpy(netdev->perm_addr, mac_addr, netdev->addr_len); -+ memcpy(netdev->dev_addr, mac_addr, netdev->addr_len); -+ -+ netdev->ethtool_ops = &dpa_generic_ethtool_ops; -+ -+ netdev->needed_headroom = priv->tx_headroom; -+ netdev->watchdog_timeo = msecs_to_jiffies(tx_timeout); -+ -+ err = register_netdev(netdev); -+ if (err < 0) { -+ dev_err(dev, "register_netdev() = %d\n", err); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static struct dpa_fq_cbs_t generic_fq_cbs = { -+ .rx_defq = { .cb = { .dqrr = dpa_generic_rx_dqrr } }, -+ .rx_errq = { .cb = { .dqrr = dpa_generic_rx_err_dqrr } }, -+ .egress_ern = { .cb = { .ern = dpa_generic_ern } } -+}; -+ -+static struct fqid_cell *__fq_alloc(struct device *dev, -+ int num_ranges, -+ const void *fqids_off) -+{ -+ struct fqid_cell *fqids; -+ int i; -+ -+ fqids = kzalloc(sizeof(*fqids) * num_ranges, GFP_KERNEL); -+ if (fqids == NULL) -+ return NULL; -+ -+ /* convert to CPU endianess */ -+ for (i = 0; i < num_ranges; i++) { -+ fqids[i].start = be32_to_cpup(fqids_off + -+ i * sizeof(*fqids)); -+ fqids[i].count = be32_to_cpup(fqids_off + -+ i * sizeof(*fqids) + sizeof(__be32)); -+ } -+ -+ return fqids; -+} -+ -+static struct list_head *dpa_generic_fq_probe(struct platform_device *_of_dev, -+ struct fm_port *tx_port) -+{ -+ struct device *dev = &_of_dev->dev; -+ struct device_node *oh_node = NULL; -+ struct device_node *onic_node = NULL; -+ struct fqid_cell *fqids; -+ const void *fqids_off; -+ struct dpa_fq *fq, *tmp; -+ struct list_head *list; -+ int num_ranges; -+ int i, lenp; -+ -+ onic_node = dev->of_node; -+ -+ list = devm_kzalloc(dev, sizeof(*list), GFP_KERNEL); -+ if (!list) { -+ dev_err(dev, "Cannot allocate space for frame queues list\n"); -+ return ERR_PTR(-ENOMEM); -+ } -+ -+ INIT_LIST_HEAD(list); -+ -+ /* RX queues (RX error, RX default) are specified in Rx O/H port node */ -+ oh_node = get_rx_op_port_node(_of_dev); -+ fqids_off = of_get_property(oh_node, "fsl,qman-frame-queues-oh", &lenp); -+ if (fqids_off == NULL) { -+ dev_err(dev, "Need Rx FQ definition in dts for generic devices\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ of_node_put(oh_node); -+ -+ num_ranges = lenp / sizeof(*fqids); -+ if (num_ranges != 2) { -+ dev_err(dev, "Need 2 Rx FQ definitions in dts for generic devices\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ fqids = __fq_alloc(dev, num_ranges, fqids_off); -+ if (!dpa_fq_alloc(dev, fqids[0].start, fqids[0].count, list, -+ FQ_TYPE_RX_ERROR) || -+ !dpa_fq_alloc(dev, fqids[1].start, fqids[1].count, -+ list, FQ_TYPE_RX_DEFAULT)) { -+ dev_err(dev, "Cannot allocate space for default frame queues\n"); -+ return ERR_PTR(-ENOMEM); -+ } -+ kfree(fqids); -+ -+ /* TX queues */ -+ fqids_off = of_get_property(onic_node, "fsl,qman-frame-queues-tx", -+ &lenp); -+ if (fqids_off == NULL) { -+ dev_err(dev, "Need Tx FQ definition in dts for generic devices\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ num_ranges = lenp / sizeof(*fqids); -+ fqids = __fq_alloc(dev, num_ranges, fqids_off); -+ for (i = 0; i < num_ranges; i++) { -+ if (!dpa_fq_alloc(dev, fqids[i].start, fqids[i].count, list, -+ FQ_TYPE_TX)) { -+ dev_err(dev, "_dpa_fq_alloc() failed\n"); -+ return ERR_PTR(-ENOMEM); -+ } -+ } -+ kfree(fqids); -+ -+ /* optional RX PCD queues */ -+ lenp = 0; -+ fqids_off = of_get_property(onic_node, -+ "fsl,qman-frame-queues-rx", &lenp); -+ num_ranges = lenp / sizeof(*fqids); -+ fqids = __fq_alloc(dev, num_ranges, fqids_off); -+ for (i = 0; i < num_ranges; i++) { -+ if (!dpa_fq_alloc(dev, fqids[i].start, fqids[i].count, list, -+ FQ_TYPE_RX_PCD)) { -+ dev_err(dev, "_dpa_fq_alloc() failed\n"); -+ return ERR_PTR(-ENOMEM); -+ } -+ } -+ kfree(fqids); -+ -+ list_for_each_entry_safe(fq, tmp, list, list) { -+ if (fq->fq_type == FQ_TYPE_TX) -+ fq->channel = fm_get_tx_port_channel(tx_port); -+ } -+ -+ return list; -+} -+ -+static void dpa_generic_ern(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_mr_entry *msg) -+{ -+ struct net_device *netdev; -+ const struct dpa_generic_priv_s *priv; -+ struct dpa_percpu_priv_s *percpu_priv; -+ struct qm_fd fd = msg->ern.fd; -+ -+ netdev = ((struct dpa_fq *)fq)->net_dev; -+ priv = netdev_priv(netdev); -+ /* Non-migratable context, safe to use raw_cpu_ptr */ -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ percpu_priv->stats.tx_dropped++; -+ percpu_priv->stats.tx_fifo_errors++; -+ count_ern(percpu_priv, msg); -+ -+ /* release this buffer into the draining buffer pool */ -+ dpa_fd_release(netdev, &fd); -+} -+ -+static int dpa_generic_rx_bp_probe(struct platform_device *_of_dev, -+ struct fm_port *rx_port, -+ int *rx_bp_count, -+ struct dpa_bp **rx_bp, -+ struct dpa_buffer_layout_s **rx_buf_layout) -+{ -+ struct device *dev = &_of_dev->dev; -+ struct fm_port_params params; -+ struct dpa_bp *bp = NULL; -+ int bp_count = 0; -+ int bpid; -+ const __be32 *bpool_cfg = NULL; -+ struct device_node *dev_node = NULL; -+ struct device_node *oh_node = NULL; -+ struct dpa_buffer_layout_s *buf_layout = NULL; -+ int lenp = 0; -+ int na = 0, ns = 0; -+ int err = 0, i = 0; -+ -+ oh_node = get_rx_op_port_node(_of_dev); -+ -+ bp_count = of_count_phandle_with_args(oh_node, -+ "fsl,bman-buffer-pools", NULL); -+ if (bp_count <= 0) { -+ dev_err(dev, "Missing buffer pool handles from onic node from device tree\n"); -+ return -EINVAL; -+ } -+ -+ bp = devm_kzalloc(dev, bp_count * sizeof(*bp), GFP_KERNEL); -+ if (unlikely(bp == NULL)) { -+ dev_err(dev, "devm_kzalloc() failed\n"); -+ err = -ENOMEM; -+ goto _return_of_node_put; -+ } -+ -+ dev_node = of_find_node_by_path("/"); -+ if (unlikely(dev_node == NULL)) { -+ dev_err(dev, "of_find_node_by_path(/) failed\n"); -+ err = -EINVAL; -+ goto _return_of_node_put; -+ } -+ -+ na = of_n_addr_cells(dev_node); -+ ns = of_n_size_cells(dev_node); -+ -+ of_node_put(dev_node); -+ -+ for (i = 0; i < bp_count; i++) { -+ dev_node = of_parse_phandle(oh_node, -+ "fsl,bman-buffer-pools", i); -+ if (dev_node == NULL) { -+ dev_err(dev, "Cannot find buffer pool node in the device tree\n"); -+ err = -EINVAL; -+ goto _return_of_node_put; -+ } -+ -+ err = of_property_read_u32(dev_node, "fsl,bpid", &bpid); -+ if (err) { -+ dev_err(dev, "Cannot find buffer pool ID in the buffer pool node in the device tree\n"); -+ goto _return_of_node_put; -+ } -+ -+ bp[i].bpid = (uint8_t)bpid; -+ -+ bpool_cfg = of_get_property(dev_node, "fsl,bpool-ethernet-cfg", -+ &lenp); -+ if (bpool_cfg && (lenp == (2 * ns + na) * sizeof(*bpool_cfg))) { -+ bp[i].config_count = (int)of_read_number(bpool_cfg, ns); -+ bp[i].size = of_read_number(bpool_cfg + ns, ns); -+ bp[i].paddr = 0; -+ bp[i].seed_pool = false; -+ } else { -+ dev_err(dev, "Missing/invalid fsl,bpool-ethernet-cfg device tree entry for node %s\n", -+ dev_node->full_name); -+ err = -EINVAL; -+ goto _return_of_node_put; -+ } -+ -+ bp[i].percpu_count = devm_alloc_percpu(dev, -+ *bp[i].percpu_count); -+ } -+ -+ of_node_put(oh_node); -+ -+ buf_layout = devm_kzalloc(dev, sizeof(*buf_layout), GFP_KERNEL); -+ if (!buf_layout) { -+ dev_err(dev, "devm_kzalloc() failed\n"); -+ err = -ENOMEM; -+ goto _return_of_node_put; -+ } -+ -+ buf_layout->priv_data_size = DPA_TX_PRIV_DATA_SIZE; -+ buf_layout->parse_results = false; -+ buf_layout->hash_results = false; -+ buf_layout->time_stamp = false; -+ fm_port_get_buff_layout_ext_params(rx_port, ¶ms); -+ buf_layout->manip_extra_space = params.manip_extra_space; -+ /* a value of zero for data alignment means "don't care", so align to -+ * a non-zero value to prevent FMD from using its own default -+ */ -+ buf_layout->data_align = params.data_align ? : DPA_FD_DATA_ALIGNMENT; -+ -+ *rx_buf_layout = buf_layout; -+ *rx_bp = bp; -+ *rx_bp_count = bp_count; -+ -+ return 0; -+ -+_return_of_node_put: -+ if (dev_node) -+ of_node_put(dev_node); -+ -+ return err; -+} -+ -+static int dpa_generic_tx_bp_probe(struct platform_device *_of_dev, -+ struct fm_port *tx_port, -+ struct dpa_bp **draining_tx_bp, -+ struct dpa_bp **draining_tx_sg_bp, -+ struct dpa_buffer_layout_s **tx_buf_layout) -+{ -+ struct device *dev = &_of_dev->dev; -+ struct fm_port_params params; -+ struct dpa_bp *bp = NULL; -+ struct dpa_bp *bp_sg = NULL; -+ struct dpa_buffer_layout_s *buf_layout = NULL; -+ -+ buf_layout = devm_kzalloc(dev, sizeof(*buf_layout), GFP_KERNEL); -+ if (!buf_layout) { -+ dev_err(dev, "devm_kzalloc() failed\n"); -+ return -ENOMEM; -+ } -+ -+ buf_layout->priv_data_size = DPA_TX_PRIV_DATA_SIZE; -+ buf_layout->parse_results = true; -+ buf_layout->hash_results = true; -+ buf_layout->time_stamp = false; -+ -+ fm_port_get_buff_layout_ext_params(tx_port, ¶ms); -+ buf_layout->manip_extra_space = params.manip_extra_space; -+ buf_layout->data_align = params.data_align ? : DPA_FD_DATA_ALIGNMENT; -+ -+ bp = devm_kzalloc(dev, sizeof(*bp), GFP_KERNEL); -+ if (unlikely(bp == NULL)) { -+ dev_err(dev, "devm_kzalloc() failed\n"); -+ return -ENOMEM; -+ } -+ -+ bp->size = dpa_bp_size(buf_layout); -+ bp->percpu_count = devm_alloc_percpu(dev, *bp->percpu_count); -+ bp->target_count = CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT; -+ -+ *draining_tx_bp = bp; -+ -+ bp_sg = devm_kzalloc(dev, sizeof(*bp_sg), GFP_KERNEL); -+ if (unlikely(bp_sg == NULL)) { -+ dev_err(dev, "devm_kzalloc() failed\n"); -+ return -ENOMEM; -+ } -+ -+ bp_sg->size = dpa_bp_size(buf_layout); -+ bp_sg->percpu_count = alloc_percpu(*bp_sg->percpu_count); -+ bp_sg->target_count = CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT; -+ -+ *draining_tx_sg_bp = bp_sg; -+ -+ *tx_buf_layout = buf_layout; -+ -+ return 0; -+} -+ -+static int dpa_generic_buff_dealloc_probe(struct platform_device *_of_dev, -+ int *disable_buff_dealloc) -+{ -+ struct device *dev = &_of_dev->dev; -+ const phandle *disable_handle = NULL; -+ int lenp = 0; -+ int err = 0; -+ -+ disable_handle = of_get_property(dev->of_node, -+ "fsl,disable_buff_dealloc", &lenp); -+ if (disable_handle != NULL) -+ *disable_buff_dealloc = 1; -+ -+ return err; -+} -+ -+static int dpa_generic_port_probe(struct platform_device *_of_dev, -+ struct fm_port **rx_port, -+ struct fm_port **tx_port) -+{ -+ struct device *dev = &_of_dev->dev; -+ struct device_node *dev_node = NULL; -+ struct device_node *onic_node = NULL; -+ int num_ports = 0; -+ int err = 0; -+ -+ onic_node = dev->of_node; -+ -+ num_ports = of_count_phandle_with_args(onic_node, "fsl,oh-ports", NULL); -+ if (num_ports != 2) { -+ dev_err(dev, "There should be two OH ports in device tree (one for RX, one for TX\n"); -+ return -EINVAL; -+ } -+ -+ dev_node = of_parse_phandle(onic_node, "fsl,oh-ports", RX); -+ if (dev_node == NULL) { -+ dev_err(dev, "Cannot find Rx OH port node in device tree\n"); -+ return err; -+ } -+ -+ err = get_port_ref(dev_node, rx_port); -+ if (err) { -+ dev_err(dev, "Cannot read Rx OH port node in device tree\n"); -+ return err; -+ } -+ -+ dev_node = of_parse_phandle(onic_node, "fsl,oh-ports", TX); -+ if (dev_node == NULL) { -+ dev_err(dev, "Cannot find Tx OH port node in device tree\n"); -+ return -EFAULT; -+ } -+ -+ err = get_port_ref(dev_node, tx_port); -+ if (err) { -+ dev_err(dev, "Cannot read Tx OH port node in device tree\n"); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static inline void dpa_generic_setup_ingress( -+ const struct dpa_generic_priv_s *priv, -+ struct dpa_fq *fq, -+ const struct qman_fq *template) -+{ -+ fq->fq_base = *template; -+ fq->net_dev = priv->net_dev; -+ -+ fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE; -+ fq->channel = priv->channel; -+} -+ -+static inline void dpa_generic_setup_egress( -+ const struct dpa_generic_priv_s *priv, -+ struct dpa_fq *fq, -+ struct fm_port *port, -+ const struct qman_fq *template) -+{ -+ fq->fq_base = *template; -+ fq->net_dev = priv->net_dev; -+ -+ fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL; -+ fq->channel = fm_get_tx_port_channel(port); -+} -+ -+static void dpa_generic_fq_setup(struct dpa_generic_priv_s *priv, -+ const struct dpa_fq_cbs_t *fq_cbs, -+ struct fm_port *tx_port) -+{ -+ struct dpa_fq *fq; -+ int egress_cnt = 0; -+ -+ /* Initialize each FQ in the list */ -+ list_for_each_entry(fq, &priv->dpa_fq_list, list) { -+ switch (fq->fq_type) { -+ case FQ_TYPE_RX_DEFAULT: -+ dpa_generic_setup_ingress(priv, fq, &fq_cbs->rx_defq); -+ break; -+ case FQ_TYPE_RX_ERROR: -+ dpa_generic_setup_ingress(priv, fq, &fq_cbs->rx_errq); -+ break; -+ case FQ_TYPE_RX_PCD: -+ dpa_generic_setup_ingress(priv, fq, &fq_cbs->rx_defq); -+ break; -+ case FQ_TYPE_TX: -+ dpa_generic_setup_egress(priv, fq, -+ tx_port, &fq_cbs->egress_ern); -+ /* If we have more Tx queues than the number of cores, -+ * just ignore the extra ones. -+ */ -+ if (egress_cnt < DPAA_ETH_TX_QUEUES) -+ priv->egress_fqs[egress_cnt++] = &fq->fq_base; -+ break; -+ default: -+ dev_warn(priv->net_dev->dev.parent, -+ "Unknown FQ type detected!\n"); -+ break; -+ } -+ } -+ -+ /* The number of Tx queues may be smaller than the number of cores, if -+ * the Tx queue range is specified in the device tree instead of being -+ * dynamically allocated. -+ * Make sure all CPUs receive a corresponding Tx queue. -+ */ -+ while (egress_cnt < DPAA_ETH_TX_QUEUES) { -+ list_for_each_entry(fq, &priv->dpa_fq_list, list) { -+ if (fq->fq_type != FQ_TYPE_TX) -+ continue; -+ priv->egress_fqs[egress_cnt++] = &fq->fq_base; -+ if (egress_cnt == DPAA_ETH_TX_QUEUES) -+ break; -+ } -+ } -+} -+ -+static int dpa_generic_fq_init(struct dpa_fq *dpa_fq, int disable_buff_dealloc) -+{ -+ int _errno; -+ struct device *dev; -+ struct qman_fq *fq; -+ struct qm_mcc_initfq initfq; -+ -+ dev = dpa_fq->net_dev->dev.parent; -+ -+ if (dpa_fq->fqid == 0) -+ dpa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID; -+ -+ _errno = qman_create_fq(dpa_fq->fqid, dpa_fq->flags, &dpa_fq->fq_base); -+ if (_errno) { -+ dev_err(dev, "qman_create_fq() failed\n"); -+ return _errno; -+ } -+ fq = &dpa_fq->fq_base; -+ -+ initfq.we_mask = QM_INITFQ_WE_FQCTRL; -+ /* FIXME: why would we want to keep an empty FQ in cache? */ -+ initfq.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; -+ -+ /* FQ placement */ -+ initfq.we_mask |= QM_INITFQ_WE_DESTWQ; -+ -+ initfq.fqd.dest.channel = dpa_fq->channel; -+ initfq.fqd.dest.wq = dpa_fq->wq; -+ -+ if (dpa_fq->fq_type == FQ_TYPE_TX && !disable_buff_dealloc) { -+ initfq.we_mask |= QM_INITFQ_WE_CONTEXTA; -+ /* ContextA: A2V=1 (contextA A2 field is valid) -+ * ContextA A2: EBD=1 (deallocate buffers inside FMan) -+ */ -+ initfq.fqd.context_a.hi = 0x10000000; -+ initfq.fqd.context_a.lo = 0x80000000; -+ } -+ -+ /* Initialization common to all ingress queues */ -+ if (dpa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) { -+ initfq.we_mask |= QM_INITFQ_WE_CONTEXTA; -+ initfq.fqd.fq_ctrl |= -+ QM_FQCTRL_CTXASTASHING | QM_FQCTRL_AVOIDBLOCK; -+ initfq.fqd.context_a.stashing.exclusive = -+ QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX | -+ QM_STASHING_EXCL_ANNOTATION; -+ initfq.fqd.context_a.stashing.data_cl = 2; -+ initfq.fqd.context_a.stashing.annotation_cl = 1; -+ initfq.fqd.context_a.stashing.context_cl = -+ DIV_ROUND_UP(sizeof(struct qman_fq), 64); -+ } -+ -+ _errno = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq); -+ if (_errno < 0) { -+ dev_err(dev, "qman_init_fq(%u) = %d\n", -+ qman_fq_fqid(fq), _errno); -+ qman_destroy_fq(fq, 0); -+ return _errno; -+ } -+ -+ dpa_fq->fqid = qman_fq_fqid(fq); -+ -+ return 0; -+} -+ -+static int dpa_generic_fq_create(struct net_device *netdev, -+ struct list_head *dpa_fq_list, -+ struct fm_port *tx_port) -+{ -+ struct dpa_generic_priv_s *priv = netdev_priv(netdev); -+ struct dpa_fq *fqs = NULL, *tmp = NULL; -+ struct task_struct *kth; -+ int err = 0; -+ int channel; -+ -+ INIT_LIST_HEAD(&priv->dpa_fq_list); -+ -+ list_replace_init(dpa_fq_list, &priv->dpa_fq_list); -+ -+ channel = dpa_get_channel(); -+ if (channel < 0) -+ return channel; -+ priv->channel = (uint16_t)channel; -+ -+ /* Start a thread that will walk the cpus with affine portals -+ * and add this pool channel to each's dequeue mask. -+ */ -+ kth = kthread_run(dpaa_eth_add_channel, -+ (void *)(unsigned long)priv->channel, -+ "dpaa_%p:%d", netdev, priv->channel); -+ if (!kth) -+ return -ENOMEM; -+ -+ dpa_generic_fq_setup(priv, &generic_fq_cbs, tx_port); -+ -+ /* Add the FQs to the interface, and make them active */ -+ list_for_each_entry_safe(fqs, tmp, &priv->dpa_fq_list, list) { -+ err = dpa_generic_fq_init(fqs, priv->disable_buff_dealloc); -+ if (err) -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int dpa_generic_bp_create(struct net_device *net_dev, -+ int rx_bp_count, -+ struct dpa_bp *rx_bp, -+ struct dpa_buffer_layout_s *rx_buf_layout, -+ struct dpa_bp *draining_tx_bp, -+ struct dpa_bp *draining_tx_sg_bp, -+ struct dpa_buffer_layout_s *tx_buf_layout) -+{ -+ struct dpa_generic_priv_s *priv = netdev_priv(net_dev); -+ int err = 0; -+ -+ /* TODO: multiple Rx bps */ -+ priv->rx_bp_count = rx_bp_count; -+ priv->rx_bp = rx_bp; -+ priv->rx_buf_layout = rx_buf_layout; -+ priv->draining_tx_bp = draining_tx_bp; -+ priv->draining_tx_sg_bp = draining_tx_sg_bp; -+ priv->tx_buf_layout = tx_buf_layout; -+ -+ err = dpa_bp_alloc(priv->rx_bp); -+ if (err < 0) { -+ priv->rx_bp = NULL; -+ return err; -+ } -+ -+ err = dpa_bp_alloc(priv->draining_tx_bp); -+ if (err < 0) { -+ priv->draining_tx_bp = NULL; -+ return err; -+ } -+ -+ err = dpa_bp_alloc(priv->draining_tx_sg_bp); -+ if (err < 0) { -+ priv->draining_tx_sg_bp = NULL; -+ return err; -+ } -+ -+ return 0; -+} -+ -+static void dpa_generic_relase_bp(struct dpa_bp *bp) -+{ -+ if (!bp) -+ return; -+ -+ if (!atomic_dec_and_test(&bp->refs)) -+ return; -+ -+ if (bp->free_buf_cb) -+ dpa_bp_drain(bp); -+ -+ bman_free_pool(bp->pool); -+ -+ if (bp->dev) -+ platform_device_unregister(to_platform_device(bp->dev)); -+} -+ -+static void dpa_generic_bp_free(struct dpa_generic_priv_s *priv) -+{ -+ int i = 0; -+ -+ /* release the rx bpools */ -+ for (i = 0; i < priv->rx_bp_count; i++) -+ dpa_generic_relase_bp(&priv->rx_bp[i]); -+ -+ /* release the tx draining bpools */ -+ dpa_generic_relase_bp(priv->draining_tx_bp); -+ dpa_generic_relase_bp(priv->draining_tx_sg_bp); -+} -+ -+static int dpa_generic_remove(struct platform_device *of_dev) -+{ -+ int err; -+ struct device *dev; -+ struct net_device *net_dev; -+ struct dpa_generic_priv_s *priv; -+ -+ dev = &of_dev->dev; -+ net_dev = dev_get_drvdata(dev); -+ priv = netdev_priv(net_dev); -+ -+ dpaa_eth_generic_sysfs_remove(dev); -+ -+ dev_set_drvdata(dev, NULL); -+ unregister_netdev(net_dev); -+ -+ err = dpa_fq_free(dev, &priv->dpa_fq_list); -+ -+ dpa_generic_napi_del(net_dev); -+ -+ dpa_generic_bp_free(priv); -+ -+ free_netdev(net_dev); -+ -+ return err; -+} -+ -+static int dpa_generic_eth_probe(struct platform_device *_of_dev) -+{ -+ struct device *dev = &_of_dev->dev; -+ struct device_node *dpa_node = dev->of_node; -+ struct net_device *netdev = NULL; -+ struct dpa_generic_priv_s *priv; -+ struct fm_port *rx_port = NULL; -+ struct fm_port *tx_port = NULL; -+ struct dpa_percpu_priv_s *percpu_priv; -+ int rx_bp_count = 0; -+ int disable_buff_dealloc = 0; -+ struct dpa_bp *rx_bp = NULL, *draining_tx_bp = NULL; -+ struct dpa_bp *draining_tx_sg_bp = NULL; -+ struct dpa_buffer_layout_s *rx_buf_layout = NULL, *tx_buf_layout = NULL; -+ struct list_head *dpa_fq_list; -+ static u8 generic_idx; -+ int err = 0; -+ int i = 0; -+ -+ if (!of_device_is_available(dpa_node)) -+ return -ENODEV; -+ -+ err = dpa_generic_port_probe(_of_dev, &tx_port, &rx_port); -+ if (err < 0) -+ return err; -+ -+ err = dpa_generic_rx_bp_probe(_of_dev, rx_port, &rx_bp_count, -+ &rx_bp, &rx_buf_layout); -+ if (err < 0) -+ return err; -+ -+ err = dpa_generic_tx_bp_probe(_of_dev, tx_port, &draining_tx_bp, -+ &draining_tx_sg_bp, &tx_buf_layout); -+ if (err < 0) -+ return err; -+ -+ dpa_fq_list = dpa_generic_fq_probe(_of_dev, tx_port); -+ if (IS_ERR(dpa_fq_list)) -+ return PTR_ERR(dpa_fq_list); -+ -+ err = dpa_generic_buff_dealloc_probe(_of_dev, &disable_buff_dealloc); -+ if (err < 0) -+ return err; -+ -+ /* just one queue for now */ -+ netdev = alloc_etherdev_mq(sizeof(*priv), 1); -+ if (!netdev) { -+ dev_err(dev, "alloc_etherdev_mq() failed\n"); -+ return -ENOMEM; -+ } -+ -+ SET_NETDEV_DEV(netdev, dev); -+ dev_set_drvdata(dev, netdev); -+ priv = netdev_priv(netdev); -+ priv->net_dev = netdev; -+ sprintf(priv->if_type, "generic%d", generic_idx++); -+ priv->msg_enable = netif_msg_init(generic_debug, -1); -+ priv->tx_headroom = DPA_DEFAULT_TX_HEADROOM; -+ -+ init_timer(&priv->timer); -+ priv->timer.data = (unsigned long)priv; -+ priv->timer.function = dpa_generic_draining_timer; -+ -+ err = dpa_generic_bp_create(netdev, rx_bp_count, rx_bp, rx_buf_layout, -+ draining_tx_bp, draining_tx_sg_bp, tx_buf_layout); -+ if (err < 0) -+ goto bp_create_failed; -+ -+ priv->disable_buff_dealloc = disable_buff_dealloc; -+ -+ err = dpa_generic_fq_create(netdev, dpa_fq_list, rx_port); -+ if (err < 0) -+ goto fq_create_failed; -+ -+ priv->tx_headroom = dpa_get_headroom(tx_buf_layout); -+ priv->rx_headroom = dpa_get_headroom(rx_buf_layout); -+ priv->rx_port = rx_port; -+ priv->tx_port = tx_port; -+ priv->mac_dev = NULL; -+ -+ -+ priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv); -+ if (priv->percpu_priv == NULL) { -+ dev_err(dev, "devm_alloc_percpu() failed\n"); -+ err = -ENOMEM; -+ goto alloc_percpu_failed; -+ } -+ for_each_online_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ memset(percpu_priv, 0, sizeof(*percpu_priv)); -+ } -+ -+ /* Initialize NAPI */ -+ err = dpa_generic_napi_add(netdev); -+ if (err < 0) -+ goto napi_add_failed; -+ -+ err = dpa_generic_netdev_init(dpa_node, netdev); -+ if (err < 0) -+ goto netdev_init_failed; -+ -+ dpaa_eth_generic_sysfs_init(&netdev->dev); -+ -+ pr_info("fsl_dpa_generic: Probed %s interface as %s\n", -+ priv->if_type, netdev->name); -+ -+ return 0; -+ -+netdev_init_failed: -+napi_add_failed: -+ dpa_generic_napi_del(netdev); -+alloc_percpu_failed: -+ if (netdev) -+ dpa_fq_free(dev, &priv->dpa_fq_list); -+fq_create_failed: -+bp_create_failed: -+ if (netdev) -+ dpa_generic_bp_free(priv); -+ dev_set_drvdata(dev, NULL); -+ if (netdev) -+ free_netdev(netdev); -+ -+ return err; -+} -+ -+static int __init __cold dpa_generic_load(void) -+{ -+ int _errno; -+ -+ pr_info(KBUILD_MODNAME ": " DPA_GENERIC_DESCRIPTION "\n"); -+ -+ /* initialise dpaa_eth mirror values */ -+ dpa_rx_extra_headroom = fm_get_rx_extra_headroom(); -+ dpa_max_frm = fm_get_max_frm(); -+ -+ _errno = platform_driver_register(&dpa_generic_driver); -+ if (unlikely(_errno < 0)) { -+ pr_err(KBUILD_MODNAME -+ ": %s:%hu:%s(): platform_driver_register() = %d\n", -+ KBUILD_BASENAME".c", __LINE__, __func__, _errno); -+ } -+ -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+ -+ return _errno; -+} -+ -+/* waiting for all referenced ports to be initialized -+ * by other kernel modules (proxy ethernet, offline_port) -+ */ -+late_initcall(dpa_generic_load); -+ -+static void __exit __cold dpa_generic_unload(void) -+{ -+ pr_debug(KBUILD_MODNAME ": -> %s:%s()\n", -+ KBUILD_BASENAME".c", __func__); -+ -+ platform_driver_unregister(&dpa_generic_driver); -+ -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+} -+module_exit(dpa_generic_unload); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_generic.h -@@ -0,0 +1,90 @@ -+/* Copyright 2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __DPA_ETH_GENERIC_H -+#define __DPA_ETH_GENERIC_H -+ -+#include "lnxwrp_fsl_fman.h" -+#include "dpaa_eth.h" -+ -+struct dpa_generic_priv_s { -+ struct net_device *net_dev; -+ /* use the same percpu_priv as other DPAA Ethernet drivers */ -+ struct dpa_percpu_priv_s __percpu *percpu_priv; -+ -+ /* up to 4 bps supported for RX */ -+ int rx_bp_count; -+ struct dpa_bp *rx_bp; -+ struct dpa_buffer_layout_s *rx_buf_layout; -+ -+ struct dpa_bp *draining_tx_bp; -+ struct dpa_bp *draining_tx_sg_bp; -+ struct dpa_buffer_layout_s *tx_buf_layout; -+ -+ /* Store here the needed Tx headroom for convenience and speed -+ * (even though it can be computed based on the fields of buf_layout) -+ */ -+ uint16_t tx_headroom; -+ uint16_t rx_headroom; -+ -+ /* In some scenarios, when VSP are not enabled on the Tx O/H port, -+ * the buffers will be released by other hardware modules -+ */ -+ int disable_buff_dealloc; -+ -+ struct qman_fq *egress_fqs[DPAA_ETH_TX_QUEUES]; -+ -+ struct fm_port *rx_port; -+ struct fm_port *tx_port; -+ -+ /* oNIC can have limited control capabilities over a MAC device */ -+ struct mac_device *mac_dev; -+ -+ uint16_t channel; /* "fsl,qman-channel-id" */ -+ struct list_head dpa_fq_list; -+ -+ uint32_t msg_enable; /* net_device message level */ -+ -+ struct dpa_buffer_layout_s *buf_layout; -+ char if_type[30]; -+ -+ /* periodic drain */ -+ struct timer_list timer; -+}; -+ -+extern const struct ethtool_ops dpa_generic_ethtool_ops; -+ -+void dpaa_eth_generic_sysfs_init(struct device *dev); -+void dpaa_eth_generic_sysfs_remove(struct device *dev); -+int __init dpa_generic_debugfs_module_init(void); -+void __exit dpa_generic_debugfs_module_exit(void); -+ -+#endif /* __DPA_ETH_GENERIC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_generic_sysfs.c -@@ -0,0 +1,201 @@ -+/* Copyright 2014 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "dpaa_eth_generic.h" -+#include "mac.h" /* struct mac_device */ -+ -+static ssize_t dpaa_eth_generic_show_addr(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct dpa_generic_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ struct mac_device *mac_dev = priv->mac_dev; -+ -+ if (mac_dev) -+ return sprintf(buf, "%llx\n", -+ (unsigned long long)mac_dev->res->start); -+ else -+ return sprintf(buf, "none\n"); -+} -+ -+static ssize_t dpaa_eth_generic_show_type(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t res = 0; -+ res = sprintf(buf, "generic\n"); -+ -+ return res; -+} -+ -+static ssize_t dpaa_eth_generic_show_fqids(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct dpa_generic_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ ssize_t bytes = 0; -+ int i = 0; -+ char *str; -+ struct dpa_fq *fq; -+ struct dpa_fq *tmp; -+ struct dpa_fq *prev = NULL; -+ u32 first_fqid = 0; -+ u32 last_fqid = 0; -+ char *prevstr = NULL; -+ -+ list_for_each_entry_safe(fq, tmp, &priv->dpa_fq_list, list) { -+ switch (fq->fq_type) { -+ case FQ_TYPE_RX_DEFAULT: -+ str = "Rx default"; -+ break; -+ case FQ_TYPE_RX_ERROR: -+ str = "Rx error"; -+ break; -+ case FQ_TYPE_RX_PCD: -+ str = "Rx PCD"; -+ break; -+ case FQ_TYPE_TX_CONFIRM: -+ str = "Tx default confirmation"; -+ break; -+ case FQ_TYPE_TX_CONF_MQ: -+ str = "Tx confirmation (mq)"; -+ break; -+ case FQ_TYPE_TX_ERROR: -+ str = "Tx error"; -+ break; -+ case FQ_TYPE_TX: -+ str = "Tx"; -+ break; -+ default: -+ str = "Unknown"; -+ } -+ -+ if (prev && (abs(fq->fqid - prev->fqid) != 1 || -+ str != prevstr)) { -+ if (last_fqid == first_fqid) -+ bytes += sprintf(buf + bytes, -+ "%s: %d\n", prevstr, prev->fqid); -+ else -+ bytes += sprintf(buf + bytes, -+ "%s: %d - %d\n", prevstr, -+ first_fqid, last_fqid); -+ } -+ -+ if (prev && abs(fq->fqid - prev->fqid) == 1 && str == prevstr) -+ last_fqid = fq->fqid; -+ else -+ first_fqid = last_fqid = fq->fqid; -+ -+ prev = fq; -+ prevstr = str; -+ i++; -+ } -+ -+ if (prev) { -+ if (last_fqid == first_fqid) -+ bytes += sprintf(buf + bytes, "%s: %d\n", prevstr, -+ prev->fqid); -+ else -+ bytes += sprintf(buf + bytes, "%s: %d - %d\n", prevstr, -+ first_fqid, last_fqid); -+ } -+ -+ return bytes; -+} -+ -+static ssize_t dpaa_eth_generic_show_bpids(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t bytes = 0; -+ struct dpa_generic_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ struct dpa_bp *rx_bp = priv->rx_bp; -+ struct dpa_bp *draining_tx_bp = priv->draining_tx_bp; -+ int i = 0; -+ -+ bytes += snprintf(buf + bytes, PAGE_SIZE, "Rx buffer pools:\n"); -+ for (i = 0; i < priv->rx_bp_count; i++) -+ bytes += snprintf(buf + bytes, PAGE_SIZE, "%u ", -+ rx_bp[i].bpid); -+ -+ bytes += snprintf(buf + bytes, PAGE_SIZE, "\n"); -+ bytes += snprintf(buf + bytes, PAGE_SIZE, "Draining buffer pool:\n"); -+ bytes += snprintf(buf + bytes, PAGE_SIZE, "%u\n", draining_tx_bp->bpid); -+ -+ return bytes; -+} -+ -+static ssize_t dpaa_eth_generic_show_mac_regs(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct dpa_generic_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ struct mac_device *mac_dev = priv->mac_dev; -+ int n = 0; -+ -+ if (mac_dev) -+ n = fm_mac_dump_regs(mac_dev, buf, n); -+ else -+ return sprintf(buf, "no mac control\n"); -+ -+ return n; -+} -+ -+static struct device_attribute dpaa_eth_generic_attrs[] = { -+ __ATTR(device_addr, S_IRUGO, dpaa_eth_generic_show_addr, NULL), -+ __ATTR(device_type, S_IRUGO, dpaa_eth_generic_show_type, NULL), -+ __ATTR(fqids, S_IRUGO, dpaa_eth_generic_show_fqids, NULL), -+ __ATTR(bpids, S_IRUGO, dpaa_eth_generic_show_bpids, NULL), -+ __ATTR(mac_regs, S_IRUGO, dpaa_eth_generic_show_mac_regs, NULL), -+}; -+ -+void dpaa_eth_generic_sysfs_init(struct device *dev) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(dpaa_eth_generic_attrs); i++) -+ if (device_create_file(dev, &dpaa_eth_generic_attrs[i])) { -+ dev_err(dev, "Error creating sysfs file\n"); -+ while (i > 0) -+ device_remove_file(dev, -+ &dpaa_eth_generic_attrs[--i]); -+ return; -+ } -+} -+ -+void dpaa_eth_generic_sysfs_remove(struct device *dev) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(dpaa_eth_generic_attrs); i++) -+ device_remove_file(dev, &dpaa_eth_generic_attrs[i]); -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_macless.c -@@ -0,0 +1,499 @@ -+/* Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifdef CONFIG_FSL_DPAA_ETH_DEBUG -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": %s:%hu:%s() " fmt, \ -+ KBUILD_BASENAME".c", __LINE__, __func__ -+#else -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": " fmt -+#endif -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "dpaa_eth.h" -+#include "dpaa_eth_common.h" -+#include "dpaa_eth_base.h" -+#include "lnxwrp_fsl_fman.h" /* fm_get_rx_extra_headroom(), fm_get_max_frm() */ -+#include "mac.h" -+ -+/* For MAC-based interfaces, we compute the tx needed headroom from the -+ * associated Tx port's buffer layout settings. -+ * For MACless interfaces just use a default value. -+ */ -+#define DPA_DEFAULT_TX_HEADROOM 64 -+ -+#define DPA_DESCRIPTION "FSL DPAA MACless Ethernet driver" -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+ -+MODULE_DESCRIPTION(DPA_DESCRIPTION); -+ -+/* This has to work in tandem with the DPA_CS_THRESHOLD_xxx values. */ -+static uint16_t macless_tx_timeout = 1000; -+module_param(macless_tx_timeout, ushort, S_IRUGO); -+MODULE_PARM_DESC(macless_tx_timeout, "The MACless Tx timeout in ms"); -+ -+/* forward declarations */ -+static int __cold dpa_macless_start(struct net_device *net_dev); -+static int __cold dpa_macless_stop(struct net_device *net_dev); -+static int __cold dpa_macless_set_address(struct net_device *net_dev, -+ void *addr); -+static void __cold dpa_macless_set_rx_mode(struct net_device *net_dev); -+ -+static int dpaa_eth_macless_probe(struct platform_device *_of_dev); -+static netdev_features_t -+dpa_macless_fix_features(struct net_device *dev, netdev_features_t features); -+ -+static const struct net_device_ops dpa_macless_ops = { -+ .ndo_open = dpa_macless_start, -+ .ndo_start_xmit = dpa_shared_tx, -+ .ndo_stop = dpa_macless_stop, -+ .ndo_tx_timeout = dpa_timeout, -+ .ndo_get_stats64 = dpa_get_stats64, -+ .ndo_set_mac_address = dpa_macless_set_address, -+ .ndo_set_rx_mode = dpa_macless_set_rx_mode, -+ .ndo_validate_addr = eth_validate_addr, -+#ifdef CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE -+ .ndo_select_queue = dpa_select_queue, -+#endif -+ .ndo_change_mtu = dpa_change_mtu, -+ .ndo_init = dpa_ndo_init, -+ .ndo_set_features = dpa_set_features, -+ .ndo_fix_features = dpa_macless_fix_features, -+}; -+ -+static const struct of_device_id dpa_macless_match[] = { -+ { -+ .compatible = "fsl,dpa-ethernet-macless" -+ }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, dpa_macless_match); -+ -+static struct platform_driver dpa_macless_driver = { -+ .driver = { -+ .name = KBUILD_MODNAME "-macless", -+ .of_match_table = dpa_macless_match, -+ .owner = THIS_MODULE, -+ }, -+ .probe = dpaa_eth_macless_probe, -+ .remove = dpa_remove -+}; -+ -+static const char macless_frame_queues[][25] = { -+ [RX] = "fsl,qman-frame-queues-rx", -+ [TX] = "fsl,qman-frame-queues-tx" -+}; -+ -+static int __cold dpa_macless_start(struct net_device *net_dev) -+{ -+ const struct dpa_priv_s *priv = netdev_priv(net_dev); -+ struct proxy_device *proxy_dev = (struct proxy_device *)priv->peer; -+ -+ netif_tx_start_all_queues(net_dev); -+ -+ if (proxy_dev) -+ dpa_proxy_start(net_dev); -+ -+ -+ return 0; -+} -+ -+static int __cold dpa_macless_stop(struct net_device *net_dev) -+{ -+ const struct dpa_priv_s *priv = netdev_priv(net_dev); -+ struct proxy_device *proxy_dev = (struct proxy_device *)priv->peer; -+ -+ netif_tx_stop_all_queues(net_dev); -+ -+ if (proxy_dev) -+ dpa_proxy_stop(proxy_dev, net_dev); -+ -+ return 0; -+} -+ -+static int dpa_macless_set_address(struct net_device *net_dev, void *addr) -+{ -+ const struct dpa_priv_s *priv = netdev_priv(net_dev); -+ struct proxy_device *proxy_dev = (struct proxy_device *)priv->peer; -+ int _errno; -+ -+ _errno = eth_mac_addr(net_dev, addr); -+ if (_errno < 0) { -+ if (netif_msg_drv(priv)) -+ netdev_err(net_dev, "eth_mac_addr() = %d\n", _errno); -+ return _errno; -+ } -+ -+ if (proxy_dev) { -+ _errno = dpa_proxy_set_mac_address(proxy_dev, net_dev); -+ if (_errno < 0) { -+ if (netif_msg_drv(priv)) -+ netdev_err(net_dev, "proxy_set_mac_address() = %d\n", -+ _errno); -+ return _errno; -+ } -+ } -+ -+ return 0; -+} -+ -+static void __cold dpa_macless_set_rx_mode(struct net_device *net_dev) -+{ -+ const struct dpa_priv_s *priv = netdev_priv(net_dev); -+ struct proxy_device *proxy_dev = (struct proxy_device *)priv->peer; -+ -+ if (proxy_dev) -+ dpa_proxy_set_rx_mode(proxy_dev, net_dev); -+} -+ -+static netdev_features_t -+dpa_macless_fix_features(struct net_device *dev, netdev_features_t features) -+{ -+ netdev_features_t unsupported_features = 0; -+ -+ /* In theory we should never be requested to enable features that -+ * we didn't set in netdev->features and netdev->hw_features at probe -+ * time, but double check just to be on the safe side. -+ */ -+ unsupported_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; -+ /* We don't support enabling Rx csum through ethtool yet */ -+ unsupported_features |= NETIF_F_RXCSUM; -+ -+ features &= ~unsupported_features; -+ -+ return features; -+} -+ -+static int dpa_macless_netdev_init(struct device_node *dpa_node, -+ struct net_device *net_dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ struct proxy_device *proxy_dev = (struct proxy_device *)priv->peer; -+ struct device *dev = net_dev->dev.parent; -+ const uint8_t *mac_addr; -+ -+ net_dev->netdev_ops = &dpa_macless_ops; -+ -+ if (proxy_dev) { -+ struct mac_device *mac_dev = proxy_dev->mac_dev; -+ net_dev->mem_start = mac_dev->res->start; -+ net_dev->mem_end = mac_dev->res->end; -+ -+ return dpa_netdev_init(net_dev, mac_dev->addr, -+ macless_tx_timeout); -+ } else { -+ /* Get the MAC address from device tree */ -+ mac_addr = of_get_mac_address(dpa_node); -+ -+ if (mac_addr == NULL) { -+ if (netif_msg_probe(priv)) -+ dev_err(dev, "No MAC address found!\n"); -+ return -EINVAL; -+ } -+ -+ return dpa_netdev_init(net_dev, mac_addr, -+ macless_tx_timeout); -+ } -+} -+ -+/* Probing of FQs for MACless ports */ -+static int dpa_fq_probe_macless(struct device *dev, struct list_head *list, -+ enum port_type ptype) -+{ -+ struct device_node *np = dev->of_node; -+ const struct fqid_cell *fqids; -+ int num_ranges; -+ int i, lenp; -+ -+ fqids = of_get_property(np, macless_frame_queues[ptype], &lenp); -+ if (fqids == NULL) { -+ dev_err(dev, "Need FQ definition in dts for MACless devices\n"); -+ return -EINVAL; -+ } -+ -+ num_ranges = lenp / sizeof(*fqids); -+ -+ /* All ranges defined in the device tree are used as Rx/Tx queues */ -+ for (i = 0; i < num_ranges; i++) { -+ if (!dpa_fq_alloc(dev, be32_to_cpu(fqids[i].start), -+ be32_to_cpu(fqids[i].count), list, -+ ptype == RX ? FQ_TYPE_RX_PCD : FQ_TYPE_TX)) { -+ dev_err(dev, "_dpa_fq_alloc() failed\n"); -+ return -ENOMEM; -+ } -+ } -+ -+ return 0; -+} -+ -+ static struct proxy_device * -+dpa_macless_proxy_probe(struct platform_device *_of_dev) -+{ -+ struct device *dev; -+ const phandle *proxy_prop; -+ struct proxy_device *proxy_dev; -+ struct device_node *proxy_node; -+ struct platform_device *proxy_pdev; -+ int lenp; -+ -+ dev = &_of_dev->dev; -+ -+ proxy_prop = of_get_property(dev->of_node, "proxy", &lenp); -+ if (!proxy_prop) -+ return NULL; -+ -+ proxy_node = of_find_node_by_phandle(*proxy_prop); -+ if (!proxy_node) { -+ dev_err(dev, "Cannot find proxy node\n"); -+ return NULL; -+ } -+ -+ proxy_pdev = of_find_device_by_node(proxy_node); -+ if (!proxy_pdev) { -+ of_node_put(proxy_node); -+ dev_err(dev, "Cannot find device represented by proxy node\n"); -+ return NULL; -+ } -+ -+ proxy_dev = dev_get_drvdata(&proxy_pdev->dev); -+ -+ of_node_put(proxy_node); -+ -+ return proxy_dev; -+} -+ -+static int dpaa_eth_macless_probe(struct platform_device *_of_dev) -+{ -+ int err = 0, i, channel; -+ struct device *dev; -+ struct device_node *dpa_node; -+ struct dpa_bp *dpa_bp; -+ struct dpa_fq *dpa_fq, *tmp; -+ size_t count; -+ struct net_device *net_dev = NULL; -+ struct dpa_priv_s *priv = NULL; -+ struct dpa_percpu_priv_s *percpu_priv; -+ static struct proxy_device *proxy_dev; -+ struct task_struct *kth; -+ static u8 macless_idx; -+ -+ dev = &_of_dev->dev; -+ -+ dpa_node = dev->of_node; -+ -+ if (!of_device_is_available(dpa_node)) -+ return -ENODEV; -+ -+ /* Get the buffer pools assigned to this interface */ -+ dpa_bp = dpa_bp_probe(_of_dev, &count); -+ if (IS_ERR(dpa_bp)) -+ return PTR_ERR(dpa_bp); -+ -+ for (i = 0; i < count; i++) -+ dpa_bp[i].seed_cb = dpa_bp_shared_port_seed; -+ -+ proxy_dev = dpa_macless_proxy_probe(_of_dev); -+ -+ -+ /* Allocate this early, so we can store relevant information in -+ * the private area (needed by 1588 code in dpa_mac_probe) -+ */ -+ net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TX_QUEUES); -+ if (!net_dev) { -+ dev_err(dev, "alloc_etherdev_mq() failed\n"); -+ return -ENOMEM; -+ } -+ -+ /* Do this here, so we can be verbose early */ -+ SET_NETDEV_DEV(net_dev, dev); -+ dev_set_drvdata(dev, net_dev); -+ -+ priv = netdev_priv(net_dev); -+ priv->net_dev = net_dev; -+ sprintf(priv->if_type, "macless%d", macless_idx++); -+ -+ priv->msg_enable = netif_msg_init(advanced_debug, -1); -+ -+ priv->peer = NULL; -+ priv->mac_dev = NULL; -+ if (proxy_dev) { -+ /* This is a temporary solution for the need of -+ * having main driver upstreamability: adjust_link -+ * is a general function that should work for both -+ * private driver and macless driver with MAC device -+ * control capabilities even if the last will not be -+ * upstreamable. -+ * TODO: find a convenient solution (wrapper over -+ * main priv structure, etc.) -+ */ -+ priv->mac_dev = proxy_dev->mac_dev; -+ -+ /* control over proxy's mac device */ -+ priv->peer = (void *)proxy_dev; -+ } -+ -+ INIT_LIST_HEAD(&priv->dpa_fq_list); -+ -+ err = dpa_fq_probe_macless(dev, &priv->dpa_fq_list, RX); -+ if (!err) -+ err = dpa_fq_probe_macless(dev, &priv->dpa_fq_list, -+ TX); -+ if (err < 0) -+ goto fq_probe_failed; -+ -+ /* bp init */ -+ priv->bp_count = count; -+ err = dpa_bp_create(net_dev, dpa_bp, count); -+ if (err < 0) -+ goto bp_create_failed; -+ -+ channel = dpa_get_channel(); -+ -+ if (channel < 0) { -+ err = channel; -+ goto get_channel_failed; -+ } -+ -+ priv->channel = (uint16_t)channel; -+ -+ /* Start a thread that will walk the cpus with affine portals -+ * and add this pool channel to each's dequeue mask. -+ */ -+ kth = kthread_run(dpaa_eth_add_channel, -+ (void *)(unsigned long)priv->channel, -+ "dpaa_%p:%d", net_dev, priv->channel); -+ if (!kth) { -+ err = -ENOMEM; -+ goto add_channel_failed; -+ } -+ -+ dpa_fq_setup(priv, &shared_fq_cbs, NULL); -+ -+ /* Add the FQs to the interface, and make them active */ -+ list_for_each_entry_safe(dpa_fq, tmp, &priv->dpa_fq_list, list) { -+ /* For MAC-less devices we only get here for RX frame queues -+ * initialization, which are the TX queues of the other -+ * partition. -+ * It is safe to rely on one partition to set the FQ taildrop -+ * threshold for the TX queues of the other partition -+ * because the ERN notifications will be received by the -+ * partition doing qman_enqueue. -+ */ -+ err = dpa_fq_init(dpa_fq, true); -+ if (err < 0) -+ goto fq_alloc_failed; -+ } -+ -+ priv->tx_headroom = DPA_DEFAULT_TX_HEADROOM; -+ -+ priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv); -+ -+ if (priv->percpu_priv == NULL) { -+ dev_err(dev, "devm_alloc_percpu() failed\n"); -+ err = -ENOMEM; -+ goto alloc_percpu_failed; -+ } -+ for_each_possible_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ memset(percpu_priv, 0, sizeof(*percpu_priv)); -+ } -+ -+ err = dpa_macless_netdev_init(dpa_node, net_dev); -+ if (err < 0) -+ goto netdev_init_failed; -+ -+ dpaa_eth_sysfs_init(&net_dev->dev); -+ -+ pr_info("fsl_dpa_macless: Probed %s interface as %s\n", -+ priv->if_type, net_dev->name); -+ -+ return 0; -+ -+netdev_init_failed: -+alloc_percpu_failed: -+fq_alloc_failed: -+ if (net_dev) -+ dpa_fq_free(dev, &priv->dpa_fq_list); -+add_channel_failed: -+get_channel_failed: -+ if (net_dev) -+ dpa_bp_free(priv); -+bp_create_failed: -+fq_probe_failed: -+ dev_set_drvdata(dev, NULL); -+ if (net_dev) -+ free_netdev(net_dev); -+ -+ return err; -+} -+ -+static int __init __cold dpa_macless_load(void) -+{ -+ int _errno; -+ -+ pr_info(DPA_DESCRIPTION "\n"); -+ -+ /* Initialize dpaa_eth mirror values */ -+ dpa_rx_extra_headroom = fm_get_rx_extra_headroom(); -+ dpa_max_frm = fm_get_max_frm(); -+ -+ _errno = platform_driver_register(&dpa_macless_driver); -+ if (unlikely(_errno < 0)) { -+ pr_err(KBUILD_MODNAME -+ ": %s:%hu:%s(): platform_driver_register() = %d\n", -+ KBUILD_BASENAME".c", __LINE__, __func__, _errno); -+ } -+ -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+ -+ return _errno; -+} -+module_init(dpa_macless_load); -+ -+static void __exit __cold dpa_macless_unload(void) -+{ -+ platform_driver_unregister(&dpa_macless_driver); -+ -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+} -+module_exit(dpa_macless_unload); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_macsec.c -@@ -0,0 +1,2156 @@ -+/* Copyright 2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "dpaa_eth_macsec.h" -+#include "dpaa_eth_common.h" -+ -+#ifdef CONFIG_FSL_DPAA_1588 -+#include "dpaa_1588.h" -+#endif -+ -+static struct sock *nl_sk; -+static struct macsec_priv_s *macsec_priv[FM_MAX_NUM_OF_MACS]; -+static char *macsec_ifs[FM_MAX_NUM_OF_MACS]; -+static int macsec_ifs_cnt; -+ -+static char ifs[MAX_LEN]; -+const struct ethtool_ops *dpa_ethtool_ops_prev; -+static struct ethtool_ops dpa_macsec_ethtool_ops; -+ -+module_param_string(ifs, ifs, MAX_LEN, 0000); -+MODULE_PARM_DESC(ifs, "Comma separated interface list"); -+ -+struct macsec_priv_s *dpa_macsec_get_priv(struct net_device *net_dev) -+{ -+ return macsec_priv[net_dev->ifindex - 1]; -+} -+ -+static void macsec_setup_ethtool_ops(struct net_device *net_dev) -+{ -+ /* remember private driver's ethtool ops just once */ -+ if (!dpa_ethtool_ops_prev) { -+ dpa_ethtool_ops_prev = net_dev->ethtool_ops; -+ -+ memcpy(&dpa_macsec_ethtool_ops, net_dev->ethtool_ops, -+ sizeof(struct ethtool_ops)); -+ dpa_macsec_ethtool_ops.get_sset_count = -+ dpa_macsec_get_sset_count; -+ dpa_macsec_ethtool_ops.get_ethtool_stats = -+ dpa_macsec_get_ethtool_stats; -+ dpa_macsec_ethtool_ops.get_strings = -+ dpa_macsec_get_strings; -+ } -+ -+ net_dev->ethtool_ops = &dpa_macsec_ethtool_ops; -+} -+ -+static void macsec_restore_ethtool_ops(struct net_device *net_dev) -+{ -+ net_dev->ethtool_ops = dpa_ethtool_ops_prev; -+} -+ -+ -+static int ifname_to_id(char *ifname) -+{ -+ int i; -+ -+ for (i = 0; i < FM_MAX_NUM_OF_MACS; i++) { -+ if (macsec_priv[i]->net_dev && -+ (strcmp(ifname, macsec_priv[i]->net_dev->name) == 0)) { -+ return i; -+ } -+ } -+ -+ return -1; -+} -+ -+static void deinit_macsec(int macsec_id) -+{ -+ struct macsec_priv_s *selected_macsec_priv; -+ int i; -+ -+ selected_macsec_priv = macsec_priv[macsec_id]; -+ -+ if (selected_macsec_priv->en_state == SECY_ENABLED) { -+ for (i = 0; i < NUM_OF_RX_SC; i++) { -+ if (!selected_macsec_priv->rx_sc_dev[i]) -+ continue; -+ fm_macsec_secy_rxsa_disable_receive( -+ selected_macsec_priv->fm_ms_secy, -+ selected_macsec_priv->rx_sc_dev[i], -+ selected_macsec_priv->an); -+ pr_debug("disable rx_sa done\n"); -+ -+ fm_macsec_secy_delete_rx_sa( -+ selected_macsec_priv->fm_ms_secy, -+ selected_macsec_priv->rx_sc_dev[i], -+ selected_macsec_priv->an); -+ pr_debug("delete rx_sa done\n"); -+ -+ fm_macsec_secy_delete_rxsc( -+ selected_macsec_priv->fm_ms_secy, -+ selected_macsec_priv->rx_sc_dev[i]); -+ pr_debug("delete rx_sc done\n"); -+ } -+ -+ fm_macsec_secy_delete_tx_sa(selected_macsec_priv->fm_ms_secy, -+ selected_macsec_priv->an); -+ pr_debug("delete tx_sa done\n"); -+ -+ fm_macsec_secy_free(selected_macsec_priv->fm_ms_secy); -+ selected_macsec_priv->fm_ms_secy = NULL; -+ pr_debug("secy free done\n"); -+ } -+ -+ if (selected_macsec_priv->en_state != MACSEC_DISABLED) { -+ fm_macsec_disable(selected_macsec_priv->fm_macsec); -+ fm_macsec_free(selected_macsec_priv->fm_macsec); -+ selected_macsec_priv->fm_macsec = NULL; -+ pr_debug("macsec disable and free done\n"); -+ } -+} -+ -+static void parse_ifs(void) -+{ -+ char *token, *strpos = ifs; -+ -+ while ((token = strsep(&strpos, ","))) { -+ if (strlen(token) == 0) -+ return; -+ else -+ macsec_ifs[macsec_ifs_cnt] = token; -+ macsec_ifs_cnt++; -+ } -+} -+ -+static void macsec_exception(handle_t _macsec_priv_s, -+ fm_macsec_exception exception) -+{ -+ struct macsec_priv_s *priv; -+ priv = (struct macsec_priv_s *)_macsec_priv_s; -+ -+ switch (exception) { -+ case (SINGLE_BIT_ECC): -+ dev_warn(priv->mac_dev->dev, "%s:%s SINGLE_BIT_ECC exception\n", -+ KBUILD_BASENAME".c", __func__); -+ break; -+ case (MULTI_BIT_ECC): -+ dev_warn(priv->mac_dev->dev, "%s:%s MULTI_BIT_ECC exception\n", -+ KBUILD_BASENAME".c", __func__); -+ break; -+ default: -+ dev_warn(priv->mac_dev->dev, "%s:%s exception %d\n", -+ KBUILD_BASENAME".c", __func__, exception); -+ break; -+ } -+} -+ -+ -+static void macsec_secy_exception(handle_t _macsec_priv_s, -+ fm_macsec_secy_exception exception) -+{ -+ struct macsec_priv_s *priv; -+ priv = (struct macsec_priv_s *)_macsec_priv_s; -+ -+ switch (exception) { -+ case (SECY_EX_FRAME_DISCARDED): -+ dev_warn(priv->mac_dev->dev, -+ "%s:%s SECY_EX_FRAME_DISCARDED exception\n", -+ KBUILD_BASENAME".c", __func__); -+ break; -+ default: -+ dev_warn(priv->mac_dev->dev, "%s:%s exception %d\n", -+ KBUILD_BASENAME".c", __func__, exception); -+ break; -+ } -+} -+ -+static void macsec_secy_events(handle_t _macsec_priv_s, -+ fm_macsec_secy_event event) -+{ -+ struct macsec_priv_s *priv; -+ priv = (struct macsec_priv_s *)_macsec_priv_s; -+ -+ switch (event) { -+ case (SECY_EV_NEXT_PN): -+ dev_dbg(priv->mac_dev->dev, "%s:%s SECY_EV_NEXT_PN event\n", -+ KBUILD_BASENAME".c", __func__); -+ break; -+ default: -+ dev_dbg(priv->mac_dev->dev, "%s:%s event %d\n", -+ KBUILD_BASENAME".c", __func__, event); -+ break; -+ } -+} -+ -+static struct qman_fq *macsec_get_tx_conf_queue( -+ const struct macsec_priv_s *macsec_priv, -+ struct qman_fq *tx_fq) -+{ -+ int i; -+ -+ for (i = 0; i < MACSEC_ETH_TX_QUEUES; i++) -+ if (macsec_priv->egress_fqs[i] == tx_fq) -+ return macsec_priv->conf_fqs[i]; -+ return NULL; -+} -+ -+/* Initialize qman fqs. Still need to set context_a, specifically the bits -+ * that identify the secure channel. -+ */ -+static int macsec_fq_init(struct dpa_fq *dpa_fq) -+{ -+ struct qman_fq *fq; -+ struct device *dev; -+ struct qm_mcc_initfq initfq; -+ uint32_t sc_phys_id; -+ int _errno, macsec_id; -+ -+ dev = dpa_fq->net_dev->dev.parent; -+ macsec_id = dpa_fq->net_dev->ifindex - 1; -+ -+ if (dpa_fq->fqid == 0) -+ dpa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID; -+ -+ dpa_fq->init = !(dpa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY); -+ _errno = qman_create_fq(dpa_fq->fqid, dpa_fq->flags, &dpa_fq->fq_base); -+ -+ if (_errno) { -+ dev_err(dev, "qman_create_fq() failed\n"); -+ return _errno; -+ } -+ -+ fq = &dpa_fq->fq_base; -+ -+ if (dpa_fq->init) { -+ initfq.we_mask = QM_INITFQ_WE_FQCTRL; -+ initfq.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; -+ -+ if (dpa_fq->fq_type == FQ_TYPE_TX_CONFIRM) -+ initfq.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; -+ -+ initfq.we_mask |= QM_INITFQ_WE_DESTWQ; -+ -+ initfq.fqd.dest.channel = dpa_fq->channel; -+ initfq.fqd.dest.wq = dpa_fq->wq; -+ -+ if (dpa_fq->fq_type == FQ_TYPE_TX) { -+ initfq.we_mask |= QM_INITFQ_WE_CONTEXTA; -+ -+ /* Obtain the TX scId from fman */ -+ _errno = fm_macsec_secy_get_txsc_phys_id( -+ macsec_priv[macsec_id]->fm_ms_secy, -+ &sc_phys_id); -+ if (unlikely(_errno < 0)) { -+ dev_err(dev, "fm_macsec_secy_get_txsc_phys_id = %d\n", -+ _errno); -+ return _errno; -+ } -+ -+ /* Write the TX SC-ID in the context of the FQ. -+ * A2V=1 (use the A2 field) -+ * A0V=1 (use the A0 field) -+ * OVOM=1 -+ * MCV=1 (MACsec controlled frames) -+ * MACCMD=the TX scId -+ */ -+ initfq.fqd.context_a.hi = 0x1a100000 | -+ sc_phys_id << 16; -+ initfq.fqd.context_a.lo = 0x80000000; -+ } -+ -+ _errno = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq); -+ if (_errno < 0) { -+ dev_err(dev, "qman_init_fq(%u) = %d\n", -+ qman_fq_fqid(fq), _errno); -+ qman_destroy_fq(fq, 0); -+ return _errno; -+ } -+ } -+ -+ dpa_fq->fqid = qman_fq_fqid(fq); -+ -+ return 0; -+} -+ -+/* Configure and enable secy. */ -+static int enable_secy(struct generic_msg *gen, int *macsec_id) -+{ -+ struct enable_secy *sec; -+ int _errno; -+ struct fm_macsec_secy_params secy_params; -+ struct dpa_fq *dpa_fq, *tmp; -+ struct macsec_priv_s *selected_macsec_priv; -+ -+ sec = &gen->payload.secy; -+ -+ if (sec->macsec_id < 0 || sec->macsec_id >= FM_MAX_NUM_OF_MACS) { -+ _errno = -EINVAL; -+ goto _return; -+ } -+ *macsec_id = sec->macsec_id; -+ selected_macsec_priv = macsec_priv[sec->macsec_id]; -+ -+ if (selected_macsec_priv->fm_ms_secy) { -+ pr_err("Secy has already been enabled\n"); -+ return -EINVAL; -+ } -+ -+ memset(&secy_params, 0, sizeof(secy_params)); -+ secy_params.fm_macsec_h = selected_macsec_priv->fm_macsec; -+ secy_params.num_receive_channels = NUM_OF_RX_SC; -+ secy_params.tx_sc_params.sci = sec->sci; -+ -+ /* Set encryption method */ -+ secy_params.tx_sc_params.cipher_suite = SECY_GCM_AES_128; -+#if (DPAA_VERSION >= 11) -+ secy_params.tx_sc_params.cipher_suite = SECY_GCM_AES_256; -+#endif /* (DPAA_VERSION >= 11) */ -+ secy_params.exception_f = macsec_secy_exception; -+ secy_params.event_f = macsec_secy_events; -+ secy_params.app_h = selected_macsec_priv; -+ -+ selected_macsec_priv->fm_ms_secy = -+ fm_macsec_secy_config(&secy_params); -+ -+ if (unlikely(selected_macsec_priv->fm_ms_secy == NULL)) { -+ _errno = -EINVAL; -+ goto _return; -+ } -+ -+ /* Configure the insertion mode */ -+ if (sec->config_insertion_mode) { -+ _errno = fm_macsec_secy_config_sci_insertion_mode( -+ selected_macsec_priv->fm_ms_secy, -+ sec->sci_insertion_mode); -+ if (unlikely(_errno < 0)) -+ goto _return; -+ } -+ -+ /* Configure the frame protection */ -+ if (sec->config_protect_frames) { -+ _errno = fm_macsec_secy_config_protect_frames( -+ selected_macsec_priv->fm_ms_secy, -+ sec->protect_frames); -+ if (unlikely(_errno < 0)) -+ goto _return; -+ } -+ -+ /* Configure the replay window */ -+ if (sec->config_replay_window) { -+ _errno = fm_macsec_secy_config_replay_window( -+ selected_macsec_priv->fm_ms_secy, -+ sec->replay_protect, -+ sec->replay_window); -+ if (unlikely(_errno < 0)) -+ goto _return; -+ } -+ -+ /* Configure the validation mode */ -+ if (sec->config_validation_mode) { -+ _errno = fm_macsec_secy_config_validation_mode( -+ selected_macsec_priv->fm_ms_secy, -+ sec->validate_frames); -+ if (unlikely(_errno < 0)) -+ goto _return; -+ } -+ -+ /* Select the exceptions that will be signaled */ -+ if (sec->config_exception) { -+ _errno = fm_macsec_secy_config_exception( -+ selected_macsec_priv->fm_ms_secy, -+ sec->exception, -+ sec->enable_exception); -+ if (unlikely(_errno < 0)) -+ goto _return; -+ } -+ -+ /* Select the events that will be signaled */ -+ if (sec->config_event) { -+ _errno = fm_macsec_secy_config_event( -+ selected_macsec_priv->fm_ms_secy, -+ sec->event, -+ sec->enable_event); -+ if (unlikely(_errno < 0)) -+ goto _return; -+ } -+ -+ /* Configure a point-to-point connection */ -+ if (sec->config_point_to_point) { -+ _errno = fm_macsec_secy_config_point_to_point( -+ selected_macsec_priv->fm_ms_secy); -+ if (unlikely(_errno < 0)) -+ goto _return; -+ } -+ -+ /* Configure the connection's confidentiality state */ -+ if (sec->config_confidentiality) { -+ _errno = fm_macsec_secy_config_confidentiality( -+ selected_macsec_priv->fm_ms_secy, -+ sec->confidentiality_enable, -+ sec->confidentiality_offset); -+ if (unlikely(_errno < 0)) -+ goto _return; -+ } -+ -+ _errno = fm_macsec_secy_init(selected_macsec_priv->fm_ms_secy); -+ if (unlikely(_errno < 0)) -+ goto _return_fm_macsec_secy_free; -+ -+ list_for_each_entry_safe(dpa_fq, -+ tmp, -+ &selected_macsec_priv->dpa_fq_list, -+ list) { -+ _errno = macsec_fq_init(dpa_fq); -+ if (_errno < 0) -+ goto _return; -+ } -+ -+ return 0; -+ -+_return_fm_macsec_secy_free: -+ fm_macsec_secy_free(selected_macsec_priv->fm_ms_secy); -+ selected_macsec_priv->fm_ms_secy = NULL; -+_return: -+ return _errno; -+} -+ -+static int set_macsec_exception(struct generic_msg *gen) -+{ -+ struct set_exception *set_ex; -+ struct macsec_priv_s *selected_macsec_priv; -+ int rv; -+ -+ set_ex = &(gen->payload.set_ex); -+ -+ selected_macsec_priv = macsec_priv[set_ex->macsec_id]; -+ -+ rv = fm_macsec_set_exception(selected_macsec_priv->fm_macsec, -+ set_ex->exception, -+ set_ex->enable_exception); -+ if (unlikely(rv < 0)) -+ pr_err("error when setting the macsec exception mask\n"); -+ -+ return rv; -+} -+ -+static int create_tx_sa(struct generic_msg *gen) -+{ -+ struct create_tx_sa *c_tx_sa; -+ macsec_sa_key_t sa_key; -+ int rv; -+ struct macsec_priv_s *selected_macsec_priv; -+ -+ c_tx_sa = &(gen->payload.c_tx_sa); -+ -+ if (c_tx_sa->macsec_id < 0 || -+ c_tx_sa->macsec_id >= FM_MAX_NUM_OF_MACS) { -+ kfree(c_tx_sa); -+ return -EINVAL; -+ } -+ selected_macsec_priv = macsec_priv[c_tx_sa->macsec_id]; -+ -+ /* set macsec_priv field */ -+ selected_macsec_priv->an = c_tx_sa->an; -+ -+ /* because of the algorithms used */ -+ if (unlikely(c_tx_sa->sak_len > 32)) { -+ pr_warn("size of secure key is greater than 32 bytes!\n"); -+ kfree(c_tx_sa); -+ return -EINVAL; -+ } -+ -+ rv = copy_from_user(&sa_key, -+ c_tx_sa->sak, -+ c_tx_sa->sak_len); -+ if (unlikely(rv != 0)) { -+ pr_err("copy_from_user could not copy %i bytes\n", rv); -+ return -EFAULT; -+ } -+ -+ rv = fm_macsec_secy_create_tx_sa(selected_macsec_priv->fm_ms_secy, -+ c_tx_sa->an, -+ sa_key); -+ if (unlikely(rv < 0)) -+ pr_err("error when creating tx sa\n"); -+ -+ return rv; -+} -+ -+static int modify_tx_sa_key(struct generic_msg *gen) -+{ -+ struct modify_tx_sa_key *tx_sa_key; -+ struct macsec_priv_s *selected_macsec_priv; -+ macsec_sa_key_t sa_key; -+ int rv; -+ -+ tx_sa_key = &(gen->payload.modify_tx_sa_key); -+ -+ if (tx_sa_key->macsec_id < 0 || -+ tx_sa_key->macsec_id >= FM_MAX_NUM_OF_MACS) -+ return -EINVAL; -+ selected_macsec_priv = macsec_priv[tx_sa_key->macsec_id]; -+ -+ /* set macsec_priv field */ -+ selected_macsec_priv->an = tx_sa_key->an; -+ -+ if (unlikely(tx_sa_key->sak_len > 32)) { -+ pr_warn("size of secure key is greater than 32 bytes!\n"); -+ kfree(tx_sa_key); -+ return -EINVAL; -+ } -+ -+ rv = copy_from_user(&sa_key, -+ tx_sa_key->sak, -+ tx_sa_key->sak_len); -+ if (unlikely(rv != 0)) { -+ pr_err("copy_from_user could not copy %i bytes\n", rv); -+ return -EFAULT; -+ } -+ -+ rv = fm_macsec_secy_txsa_modify_key(selected_macsec_priv->fm_ms_secy, -+ tx_sa_key->an, -+ sa_key); -+ if (unlikely(rv < 0)) -+ pr_err("error while modifying the tx sa key\n"); -+ -+ return rv; -+} -+ -+static int activate_tx_sa(struct generic_msg *gen) -+{ -+ struct activate_tx_sa *a_tx_sa; -+ struct macsec_priv_s *selected_macsec_priv; -+ int rv; -+ -+ a_tx_sa = &(gen->payload.a_tx_sa); -+ -+ if (a_tx_sa->macsec_id < 0 || -+ a_tx_sa->macsec_id >= FM_MAX_NUM_OF_MACS) { -+ kfree(a_tx_sa); -+ return -EINVAL; -+ } -+ selected_macsec_priv = macsec_priv[a_tx_sa->macsec_id]; -+ -+ rv = fm_macsec_secy_txsa_set_active(selected_macsec_priv->fm_ms_secy, -+ a_tx_sa->an); -+ if (unlikely(rv < 0)) -+ pr_err("error when creating tx sa\n"); -+ -+ return rv; -+} -+ -+static int get_tx_sa_an(struct generic_msg *gen, macsec_an_t *an) -+{ -+ struct macsec_priv_s *selected_macsec_priv; -+ -+ if (gen->payload.macsec_id < 0 || -+ gen->payload.macsec_id >= FM_MAX_NUM_OF_MACS) -+ return -EINVAL; -+ -+ selected_macsec_priv = macsec_priv[gen->payload.macsec_id]; -+ -+ fm_macsec_secy_txsa_get_active(selected_macsec_priv->fm_ms_secy, an); -+ -+ return 0; -+} -+ -+static int create_rx_sc(struct generic_msg *gen) -+{ -+ struct fm_macsec_secy_sc_params params; -+ struct macsec_priv_s *selected_macsec_priv; -+ struct rx_sc_dev *rx_sc_dev; -+ uint32_t sc_phys_id; -+ int i; -+ -+ if (gen->payload.c_rx_sc.macsec_id < 0 || -+ gen->payload.c_rx_sc.macsec_id >= FM_MAX_NUM_OF_MACS) -+ return -EINVAL; -+ selected_macsec_priv = macsec_priv[gen->payload.c_rx_sc.macsec_id]; -+ -+ for (i = 0; i < NUM_OF_RX_SC; i++) -+ if (!selected_macsec_priv->rx_sc_dev[i]) -+ break; -+ if (i == NUM_OF_RX_SC) { -+ pr_err("number of maximum RX_SC's has been reached\n"); -+ return -EINVAL; -+ } -+ -+ params.sci = gen->payload.c_rx_sc.sci; -+ params.cipher_suite = SECY_GCM_AES_128; -+#if (DPAA_VERSION >= 11) -+ params.cipher_suite = SECY_GCM_AES_256; -+#endif /* (DPAA_VERSION >= 11) */ -+ -+ rx_sc_dev = fm_macsec_secy_create_rxsc(selected_macsec_priv->fm_ms_secy, -+ ¶ms); -+ -+ fm_macsec_secy_get_rxsc_phys_id(selected_macsec_priv->fm_ms_secy, -+ rx_sc_dev, -+ &sc_phys_id); -+ -+ selected_macsec_priv->rx_sc_dev[sc_phys_id] = rx_sc_dev; -+ -+ return sc_phys_id; -+} -+ -+static int create_rx_sa(struct generic_msg *gen) -+{ -+ struct create_rx_sa *c_rx_sa; -+ struct macsec_priv_s *selected_macsec_priv; -+ struct rx_sc_dev *selected_rx_sc_dev; -+ macsec_sa_key_t sak; -+ int rv; -+ -+ c_rx_sa = &(gen->payload.c_rx_sa); -+ -+ if (unlikely(c_rx_sa->sak_len > 32)) { -+ pr_warn("size of secure key is greater than 32 bytes!\n"); -+ return -EINVAL; -+ } -+ rv = copy_from_user(&sak, -+ c_rx_sa->sak, -+ c_rx_sa->sak_len); -+ if (unlikely(rv != 0)) { -+ pr_err("copy_from_user could not copy %i bytes\n", rv); -+ return -EFAULT; -+ } -+ -+ if (c_rx_sa->macsec_id < 0 || -+ c_rx_sa->macsec_id >= FM_MAX_NUM_OF_MACS) -+ return -EINVAL; -+ -+ selected_macsec_priv = macsec_priv[c_rx_sa->macsec_id]; -+ -+ if (c_rx_sa->rx_sc_id < 0 || c_rx_sa->rx_sc_id >= NUM_OF_RX_SC) -+ return -EINVAL; -+ -+ selected_rx_sc_dev = selected_macsec_priv->rx_sc_dev[c_rx_sa->rx_sc_id]; -+ -+ rv = fm_macsec_secy_create_rx_sa(selected_macsec_priv->fm_ms_secy, -+ selected_rx_sc_dev, -+ c_rx_sa->an, -+ c_rx_sa->lpn, -+ sak); -+ if (unlikely(rv < 0)) { -+ pr_err("fm_macsec_secy_create_rx_sa failed\n"); -+ return -EBUSY; -+ } -+ -+ return 0; -+} -+ -+static int modify_rx_sa_key(struct generic_msg *gen) -+{ -+ struct modify_rx_sa_key *rx_sa_key; -+ struct macsec_priv_s *selected_macsec_priv; -+ struct rx_sc_dev *selected_rx_sc; -+ macsec_sa_key_t sa_key; -+ int rv; -+ -+ rx_sa_key = &(gen->payload.modify_rx_sa_key); -+ -+ if (rx_sa_key->macsec_id < 0 || -+ rx_sa_key->macsec_id >= FM_MAX_NUM_OF_MACS) -+ return -EINVAL; -+ selected_macsec_priv = macsec_priv[rx_sa_key->macsec_id]; -+ -+ if (rx_sa_key->rx_sc_id < 0 || rx_sa_key->rx_sc_id >= NUM_OF_RX_SC) -+ return -EINVAL; -+ selected_rx_sc = selected_macsec_priv->rx_sc_dev[rx_sa_key->rx_sc_id]; -+ -+ /* set macsec_priv field */ -+ selected_macsec_priv->an = rx_sa_key->an; -+ -+ if (unlikely(rx_sa_key->sak_len > 32)) { -+ pr_warn("size of secure key is greater than 32 bytes!\n"); -+ kfree(rx_sa_key); -+ return -EINVAL; -+ } -+ -+ rv = copy_from_user(&sa_key, -+ rx_sa_key->sak, -+ rx_sa_key->sak_len); -+ if (unlikely(rv != 0)) { -+ pr_err("copy_from_user could not copy %i bytes\n", rv); -+ return -EFAULT; -+ } -+ -+ rv = fm_macsec_secy_rxsa_modify_key(selected_macsec_priv->fm_ms_secy, -+ selected_rx_sc, -+ rx_sa_key->an, -+ sa_key); -+ if (unlikely(rv < 0)) -+ pr_err("error while modifying the rx sa key\n"); -+ -+ return rv; -+} -+ -+static int update_npn(struct generic_msg *gen) -+{ -+ struct update_npn *update_npn; -+ struct macsec_priv_s *selected_macsec_priv; -+ struct rx_sc_dev *selected_rx_sc_dev; -+ int err; -+ -+ update_npn = &(gen->payload.update_npn); -+ -+ if (update_npn->macsec_id < 0 || -+ update_npn->macsec_id >= FM_MAX_NUM_OF_MACS) -+ return -EINVAL; -+ selected_macsec_priv = macsec_priv[update_npn->macsec_id]; -+ -+ if (update_npn->rx_sc_id < 0 || update_npn->rx_sc_id >= NUM_OF_RX_SC) -+ return -EINVAL; -+ -+ selected_rx_sc_dev = -+ selected_macsec_priv->rx_sc_dev[update_npn->rx_sc_id]; -+ -+ err = fm_macsec_secy_rxsa_update_next_pn( -+ selected_macsec_priv->fm_ms_secy, -+ selected_rx_sc_dev, -+ update_npn->an, -+ update_npn->pn); -+ if (unlikely(err < 0)) { -+ pr_err("fm_macsec_secy_rxsa_update_next_pn failed\n"); -+ return -EBUSY; -+ } -+ -+ return 0; -+} -+ -+static int update_lpn(struct generic_msg *gen) -+{ -+ struct update_lpn *update_lpn; -+ struct macsec_priv_s *selected_macsec_priv; -+ struct rx_sc_dev *selected_rx_sc_dev; -+ int err; -+ -+ update_lpn = &(gen->payload.update_lpn); -+ -+ if (update_lpn->macsec_id < 0 || -+ update_lpn->macsec_id >= FM_MAX_NUM_OF_MACS) -+ return -EINVAL; -+ selected_macsec_priv = macsec_priv[update_lpn->macsec_id]; -+ -+ if (update_lpn->rx_sc_id < 0 || update_lpn->rx_sc_id >= NUM_OF_RX_SC) -+ return -EINVAL; -+ selected_rx_sc_dev = -+ selected_macsec_priv->rx_sc_dev[update_lpn->rx_sc_id]; -+ -+ err = fm_macsec_secy_rxsa_update_lowest_pn( -+ selected_macsec_priv->fm_ms_secy, -+ selected_rx_sc_dev, -+ update_lpn->an, -+ update_lpn->pn); -+ if (unlikely(err < 0)) { -+ pr_err("fm_macsec_secy_rxsa_update_lowest_pn failed\n"); -+ return -EBUSY; -+ } -+ -+ return 0; -+} -+ -+static int activate_rx_sa(struct generic_msg *gen) -+{ -+ struct activate_rx_sa *a_rx_sa; -+ struct macsec_priv_s *selected_macsec_priv; -+ struct rx_sc_dev *selected_rx_sc_dev; -+ int err; -+ -+ a_rx_sa = &(gen->payload.a_rx_sa); -+ -+ if (a_rx_sa->macsec_id < 0 || -+ a_rx_sa->macsec_id >= FM_MAX_NUM_OF_MACS) { -+ return -EINVAL; -+ } -+ selected_macsec_priv = macsec_priv[a_rx_sa->macsec_id]; -+ -+ if (a_rx_sa->rx_sc_id < 0 || a_rx_sa->rx_sc_id >= NUM_OF_RX_SC) -+ return -EINVAL; -+ selected_rx_sc_dev = selected_macsec_priv->rx_sc_dev[a_rx_sa->rx_sc_id]; -+ -+ err = fm_macsec_secy_rxsa_enable_receive( -+ selected_macsec_priv->fm_ms_secy, -+ selected_rx_sc_dev, -+ a_rx_sa->an); -+ if (unlikely(err < 0)) { -+ pr_err("fm_macsec_secy_rxsa_enable_receive failed\n"); -+ return -EBUSY; -+ } -+ -+ return 0; -+} -+ -+static int get_tx_sc_phys_id(struct generic_msg *gen, uint32_t *sc_id) -+{ -+ struct macsec_priv_s *selected_macsec_priv; -+ int err; -+ -+ if (gen->payload.macsec_id < 0 || -+ gen->payload.macsec_id >= FM_MAX_NUM_OF_MACS) { -+ return -EINVAL; -+ } -+ selected_macsec_priv = macsec_priv[gen->payload.macsec_id]; -+ -+ err = fm_macsec_secy_get_txsc_phys_id(selected_macsec_priv->fm_ms_secy, -+ sc_id); -+ -+ if (unlikely(err < 0)) { -+ pr_err("fm_macsec_secy_get_txsc_phys_id failed\n"); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int get_rx_sc_phys_id(struct generic_msg *gen, uint32_t *sc_id) -+{ -+ struct get_rx_sc_id *get_rx_sc_id; -+ struct macsec_priv_s *selected_macsec_priv; -+ struct rx_sc_dev *selected_rx_sc_dev; -+ int err; -+ -+ get_rx_sc_id = &(gen->payload.get_rx_sc_id); -+ -+ if (get_rx_sc_id->macsec_id < 0 || -+ get_rx_sc_id->macsec_id >= FM_MAX_NUM_OF_MACS) { -+ return -EINVAL; -+ } -+ selected_macsec_priv = macsec_priv[get_rx_sc_id->macsec_id]; -+ -+ if (get_rx_sc_id->rx_sc_id < 0 || -+ get_rx_sc_id->rx_sc_id >= NUM_OF_RX_SC) -+ return -EINVAL; -+ selected_rx_sc_dev = -+ selected_macsec_priv->rx_sc_dev[get_rx_sc_id->rx_sc_id]; -+ -+ err = fm_macsec_secy_get_rxsc_phys_id(selected_macsec_priv->fm_ms_secy, -+ selected_rx_sc_dev, -+ sc_id); -+ if (unlikely(err < 0)) { -+ pr_err("fm_macsec_secy_get_rxsc_phys_id failed\n"); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int get_macsec_revision(struct generic_msg *gen, int *macsec_revision) -+{ -+ struct macsec_priv_s *selected_macsec_priv; -+ int err; -+ -+ if (gen->payload.macsec_id < 0 || -+ gen->payload.macsec_id >= FM_MAX_NUM_OF_MACS) { -+ return -EINVAL; -+ } -+ selected_macsec_priv = macsec_priv[gen->payload.macsec_id]; -+ -+ err = fm_macsec_get_revision(selected_macsec_priv->fm_macsec, -+ macsec_revision); -+ if (unlikely(err < 0)) { -+ pr_err("fm_macsec_get_revision failed\n"); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int rx_sa_disable(struct generic_msg *gen) -+{ -+ struct disable_rx_sa *disable_rx_sa; -+ struct macsec_priv_s *selected_macsec_priv; -+ struct rx_sc_dev *selected_rx_sc_dev; -+ int err; -+ -+ disable_rx_sa = &(gen->payload.d_rx_sa); -+ -+ if (disable_rx_sa->macsec_id < 0 || -+ disable_rx_sa->macsec_id >= FM_MAX_NUM_OF_MACS) { -+ return -EINVAL; -+ } -+ selected_macsec_priv = macsec_priv[disable_rx_sa->macsec_id]; -+ -+ if (disable_rx_sa->rx_sc_id < 0 || -+ disable_rx_sa->rx_sc_id >= NUM_OF_RX_SC) -+ return -EINVAL; -+ selected_rx_sc_dev = -+ selected_macsec_priv->rx_sc_dev[disable_rx_sa->rx_sc_id]; -+ -+ err = fm_macsec_secy_rxsa_disable_receive( -+ selected_macsec_priv->fm_ms_secy, -+ selected_rx_sc_dev, -+ selected_macsec_priv->an); -+ -+ if (unlikely(err < 0)) { -+ pr_err("fm_macsec_secy_rxsa_disable_receive failed\n"); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int rx_sa_delete(struct generic_msg *gen) -+{ -+ struct delete_rx_sa *delete_rx_sa; -+ struct macsec_priv_s *selected_macsec_priv; -+ struct rx_sc_dev *selected_rx_sc_dev; -+ int err; -+ -+ delete_rx_sa = &(gen->payload.del_rx_sa); -+ -+ if (delete_rx_sa->macsec_id < 0 || -+ delete_rx_sa->macsec_id >= FM_MAX_NUM_OF_MACS) { -+ return -EINVAL; -+ } -+ selected_macsec_priv = macsec_priv[delete_rx_sa->macsec_id]; -+ -+ if (delete_rx_sa->rx_sc_id < 0 || -+ delete_rx_sa->rx_sc_id >= NUM_OF_RX_SC) -+ return -EINVAL; -+ selected_rx_sc_dev = -+ selected_macsec_priv->rx_sc_dev[delete_rx_sa->rx_sc_id]; -+ -+ err = fm_macsec_secy_delete_rx_sa(selected_macsec_priv->fm_ms_secy, -+ selected_rx_sc_dev, -+ selected_macsec_priv->an); -+ -+ if (unlikely(err < 0)) { -+ pr_err("fm_macsec_secy_delete_rx_sa failed\n"); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int rx_sc_delete(struct generic_msg *gen) -+{ -+ struct delete_rx_sc *delete_rx_sc; -+ struct macsec_priv_s *selected_macsec_priv; -+ struct rx_sc_dev *selected_rx_sc_dev; -+ int err; -+ -+ delete_rx_sc = &(gen->payload.del_rx_sc); -+ -+ if (delete_rx_sc->macsec_id < 0 || -+ delete_rx_sc->macsec_id >= FM_MAX_NUM_OF_MACS) { -+ return -EINVAL; -+ } -+ selected_macsec_priv = macsec_priv[delete_rx_sc->macsec_id]; -+ -+ if (delete_rx_sc->rx_sc_id < 0 || -+ delete_rx_sc->rx_sc_id >= NUM_OF_RX_SC) -+ return -EINVAL; -+ selected_rx_sc_dev = -+ selected_macsec_priv->rx_sc_dev[delete_rx_sc->rx_sc_id]; -+ -+ err = fm_macsec_secy_delete_rxsc(selected_macsec_priv->fm_ms_secy, -+ selected_rx_sc_dev); -+ -+ if (unlikely(err < 0)) { -+ pr_err("fm_macsec_secy_delete_rxsc failed\n"); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int tx_sa_delete(struct generic_msg *gen) -+{ -+ struct macsec_priv_s *selected_macsec_priv; -+ int err; -+ -+ if (gen->payload.del_tx_sa.macsec_id < 0 || -+ gen->payload.del_tx_sa.macsec_id >= FM_MAX_NUM_OF_MACS) { -+ return -EINVAL; -+ } -+ selected_macsec_priv = macsec_priv[gen->payload.del_tx_sa.macsec_id]; -+ -+ err = fm_macsec_secy_delete_tx_sa(selected_macsec_priv->fm_ms_secy, -+ selected_macsec_priv->an); -+ -+ if (unlikely(err < 0)) { -+ pr_err("fm_macsec_secy_delete_tx_sa failed\n"); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int disable_secy(struct generic_msg *gen, int *macsec_id) -+{ -+ struct macsec_priv_s *selected_macsec_priv; -+ int err; -+ -+ if (gen->payload.macsec_id < 0 || -+ gen->payload.macsec_id >= FM_MAX_NUM_OF_MACS) { -+ return -EINVAL; -+ } -+ selected_macsec_priv = macsec_priv[gen->payload.macsec_id]; -+ *macsec_id = gen->payload.macsec_id; -+ -+ err = fm_macsec_secy_free(selected_macsec_priv->fm_ms_secy); -+ selected_macsec_priv->fm_ms_secy = NULL; -+ -+ if (unlikely(err < 0)) { -+ pr_err("fm_macsec_secy_free failed\n"); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int disable_macsec(struct generic_msg *gen, int *macsec_id) -+{ -+ struct macsec_priv_s *selected_macsec_priv; -+ int err; -+ -+ if (gen->payload.macsec_id < 0 || -+ gen->payload.macsec_id >= FM_MAX_NUM_OF_MACS) { -+ return -EINVAL; -+ } -+ -+ selected_macsec_priv = -+ macsec_priv[gen->payload.macsec_id]; -+ *macsec_id = gen->payload.macsec_id; -+ -+ err = fm_macsec_disable(selected_macsec_priv->fm_macsec); -+ err += fm_macsec_free(selected_macsec_priv->fm_macsec); -+ selected_macsec_priv->fm_macsec = NULL; -+ -+ if (unlikely(err < 0)) { -+ pr_err("macsec disable failed\n"); -+ return err; -+ } -+ -+ return 0; -+ -+} -+ -+static int disable_all(struct generic_msg *gen, int *macsec_id) -+{ -+ struct macsec_priv_s *selected_macsec_priv; -+ struct rx_sc_dev *selected_rx_sc_dev; -+ int err = 0, i; -+ -+ if (gen->payload.macsec_id < 0 || -+ gen->payload.macsec_id >= FM_MAX_NUM_OF_MACS) { -+ return -EINVAL; -+ } -+ -+ selected_macsec_priv = macsec_priv[gen->payload.macsec_id]; -+ *macsec_id = gen->payload.macsec_id; -+ -+ for (i = 0; i < NUM_OF_RX_SC; i++) { -+ selected_rx_sc_dev = selected_macsec_priv->rx_sc_dev[i]; -+ -+ if (!selected_rx_sc_dev) -+ continue; -+ -+ err += fm_macsec_secy_rxsa_disable_receive( -+ selected_macsec_priv->fm_ms_secy, -+ selected_rx_sc_dev, -+ selected_macsec_priv->an); -+ -+ err += fm_macsec_secy_delete_rx_sa( -+ selected_macsec_priv->fm_ms_secy, -+ selected_rx_sc_dev, -+ selected_macsec_priv->an); -+ -+ err += fm_macsec_secy_delete_rxsc( -+ selected_macsec_priv->fm_ms_secy, -+ selected_rx_sc_dev); -+ } -+ -+ err += fm_macsec_secy_delete_tx_sa( -+ selected_macsec_priv->fm_ms_secy, -+ selected_macsec_priv->an); -+ -+ err += fm_macsec_secy_free(selected_macsec_priv->fm_ms_secy); -+ selected_macsec_priv->fm_ms_secy = NULL; -+ -+ err += fm_macsec_disable(selected_macsec_priv->fm_macsec); -+ -+ err += fm_macsec_free(selected_macsec_priv->fm_macsec); -+ selected_macsec_priv->fm_macsec = NULL; -+ -+ if (unlikely(err < 0)) { -+ pr_err("macsec disable failed\n"); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static inline void macsec_setup_ingress(struct macsec_priv_s *macsec_priv, -+ struct dpa_fq *fq, -+ const struct qman_fq *template) -+{ -+ fq->fq_base = *template; -+ fq->net_dev = macsec_priv->net_dev; -+ -+ fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE; -+ fq->channel = macsec_priv->channel; -+} -+ -+static inline void macsec_setup_egress(struct macsec_priv_s *macsec_priv, -+ struct dpa_fq *fq, -+ struct fm_port *port, -+ const struct qman_fq *template) -+{ -+ fq->fq_base = *template; -+ fq->net_dev = macsec_priv->net_dev; -+ -+ if (port) { -+ fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL; -+ fq->channel = (uint16_t)fm_get_tx_port_channel(port); -+ } else { -+ fq->flags = QMAN_FQ_FLAG_NO_MODIFY; -+ } -+} -+ -+/* At the moment, we don't create recycle queues. */ -+static void macsec_fq_setup(struct macsec_priv_s *macsec_priv, -+ const struct dpa_fq_cbs_t *fq_cbs, -+ struct fm_port *tx_port) -+{ -+ struct dpa_fq *fq; -+ int egress_cnt = 0, conf_cnt = 0; -+ -+ /* Initialize each FQ in the list */ -+ list_for_each_entry(fq, &macsec_priv->dpa_fq_list, list) { -+ switch (fq->fq_type) { -+ /* Normal TX queues */ -+ case FQ_TYPE_TX: -+ macsec_setup_egress(macsec_priv, fq, tx_port, -+ &fq_cbs->egress_ern); -+ /* If we have more Tx queues than the number of cores, -+ * just ignore the extra ones. -+ */ -+ if (egress_cnt < MACSEC_ETH_TX_QUEUES) -+ macsec_priv->egress_fqs[egress_cnt++] = -+ &fq->fq_base; -+ break; -+ case FQ_TYPE_TX_CONFIRM: -+ BUG_ON(!macsec_priv->mac_dev); -+ macsec_setup_ingress(macsec_priv, fq, &fq_cbs->tx_defq); -+ break; -+ /* TX confirm multiple queues */ -+ case FQ_TYPE_TX_CONF_MQ: -+ BUG_ON(!macsec_priv->mac_dev); -+ macsec_setup_ingress(macsec_priv, fq, &fq_cbs->tx_defq); -+ macsec_priv->conf_fqs[conf_cnt++] = &fq->fq_base; -+ break; -+ case FQ_TYPE_TX_ERROR: -+ BUG_ON(!macsec_priv->mac_dev); -+ macsec_setup_ingress(macsec_priv, fq, &fq_cbs->tx_errq); -+ break; -+ default: -+ dev_warn(macsec_priv->net_dev->dev.parent, -+ "Unknown FQ type detected!\n"); -+ break; -+ } -+ } -+ -+ /* The number of Tx queues may be smaller than the number of cores, if -+ * the Tx queue range is specified in the device tree instead of being -+ * dynamically allocated. -+ * Make sure all CPUs receive a corresponding Tx queue. -+ */ -+ while (egress_cnt < MACSEC_ETH_TX_QUEUES) { -+ list_for_each_entry(fq, &macsec_priv->dpa_fq_list, list) { -+ if (fq->fq_type != FQ_TYPE_TX) -+ continue; -+ macsec_priv->egress_fqs[egress_cnt++] = &fq->fq_base; -+ if (egress_cnt == MACSEC_ETH_TX_QUEUES) -+ break; -+ } -+ } -+ -+} -+ -+static const struct fqid_cell tx_fqids[] = { -+ {0, MACSEC_ETH_TX_QUEUES} -+}; -+ -+static const struct fqid_cell tx_confirm_fqids[] = { -+ {0, MACSEC_ETH_TX_QUEUES} -+}; -+ -+/* Allocate percpu priv. This is used to keep track of rx and tx packets on -+ * each cpu (take into consideration that the number of queues is equal to the -+ * number of cpus, so there is one queue/cpu). -+ */ -+static void alloc_priv(struct macsec_percpu_priv_s *percpu_priv, -+ struct macsec_priv_s *macsec_priv, struct device *dev) -+{ -+ int i, err; -+ -+ macsec_priv->percpu_priv = alloc_percpu(*macsec_priv->percpu_priv); -+ -+ if (unlikely(macsec_priv->percpu_priv == NULL)) { -+ dev_err(dev, "alloc_percpu() failed\n"); -+ err = -ENOMEM; -+ dpa_fq_free(dev, &macsec_priv->dpa_fq_list); -+ } -+ -+ for_each_possible_cpu(i) { -+ percpu_priv = per_cpu_ptr(macsec_priv->percpu_priv, i); -+ memset(percpu_priv, 0, sizeof(*percpu_priv)); -+ } -+ -+} -+ -+/* On RX, we only need to retain the information about frames, if they were -+ * encrypted or not. Statistics regarding this will be printed in a log file. -+ */ -+static int macsec_rx_hook(void *ptr, struct net_device *net_dev, u32 fqid) -+{ -+ -+ struct qm_fd *rx_fd = (struct qm_fd *)ptr; -+ struct macsec_percpu_priv_s *percpu_priv_m; -+ struct macsec_priv_s *selected_macsec_priv; -+ -+ selected_macsec_priv = macsec_priv[net_dev->ifindex - 1]; -+ -+ percpu_priv_m = raw_cpu_ptr(selected_macsec_priv->percpu_priv); -+ -+ if ((rx_fd->status & FM_FD_STAT_RX_MACSEC) != 0) { -+ if (netif_msg_hw(selected_macsec_priv) && net_ratelimit()) -+ netdev_warn(net_dev, "FD status = 0x%u\n", -+ rx_fd->status & FM_FD_STAT_RX_MACSEC); -+ percpu_priv_m->rx_macsec++; -+ } -+ -+ return DPAA_ETH_CONTINUE; -+} -+ -+/* Split TX traffic. If encryption enabled, send packets on specific QMAN frame -+ * queues. Other way, let them be handled by dpa eth. Also, keep track of the -+ * number of packets that are walking away through "macsec" queues. -+ */ -+static enum dpaa_eth_hook_result macsec_tx_hook(struct sk_buff *skb, -+ struct net_device *net_dev) -+{ -+ struct dpa_priv_s *dpa_priv; -+ struct qm_fd fd; -+ struct macsec_percpu_priv_s *macsec_percpu_priv; -+ struct dpa_percpu_priv_s *dpa_percpu_priv; -+ int i, err = 0; -+ int *countptr, offset = 0; -+ const bool nonlinear = skb_is_nonlinear(skb); -+ struct qman_fq *egress_fq; -+ struct macsec_priv_s *selected_macsec_priv; -+ -+ selected_macsec_priv = macsec_priv[net_dev->ifindex - 1]; -+ -+ if (!selected_macsec_priv->net_dev || -+ (selected_macsec_priv->en_state != SECY_ENABLED) || -+ (ntohs(skb->protocol) == ETH_P_PAE)) -+ return DPAA_ETH_CONTINUE; -+ -+ dpa_priv = netdev_priv(net_dev); -+ /* Non-migratable context, safe to use raw_cpu_ptr */ -+ macsec_percpu_priv = raw_cpu_ptr(selected_macsec_priv->percpu_priv); -+ dpa_percpu_priv = raw_cpu_ptr(dpa_priv->percpu_priv); -+ -+ countptr = raw_cpu_ptr(dpa_priv->dpa_bp->percpu_count); -+ -+ clear_fd(&fd); -+ -+#ifdef CONFIG_FSL_DPAA_1588 -+ if (dpa_priv->tsu && dpa_priv->tsu->valid && -+ dpa_priv->tsu->hwts_tx_en_ioctl) -+ fd.cmd |= FM_FD_CMD_UPD; -+#endif -+#ifdef CONFIG_FSL_DPAA_TS -+ if (unlikely(dpa_priv->ts_tx_en && -+ skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) -+ fd.cmd |= FM_FD_CMD_UPD; -+ skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; -+#endif /* CONFIG_FSL_DPAA_TS */ -+ -+ /* MAX_SKB_FRAGS is larger than our DPA_SGT_MAX_ENTRIES; make sure -+ * we don't feed FMan with more fragments than it supports. -+ * Btw, we're using the first sgt entry to store the linear part of -+ * the skb, so we're one extra frag short. -+ */ -+ if (nonlinear && -+ likely(skb_shinfo(skb)->nr_frags < DPA_SGT_MAX_ENTRIES)) { -+ /* Just create a S/G fd based on the skb */ -+ err = skb_to_sg_fd(dpa_priv, skb, &fd); -+ dpa_percpu_priv->tx_frag_skbuffs++; -+ } else { -+ /* Make sure we have enough headroom to accommodate private -+ * data, parse results, etc. Normally this shouldn't happen if -+ * we're here via the standard kernel stack. -+ */ -+ if (unlikely(skb_headroom(skb) < dpa_priv->tx_headroom)) { -+ struct sk_buff *skb_new; -+ -+ skb_new = skb_realloc_headroom(skb, -+ dpa_priv->tx_headroom); -+ if (unlikely(!skb_new)) { -+ dev_kfree_skb(skb); -+ dpa_percpu_priv->stats.tx_errors++; -+ return DPAA_ETH_STOLEN; -+ } -+ dev_kfree_skb(skb); -+ skb = skb_new; -+ } -+ -+ /* We're going to store the skb backpointer at the beginning -+ * of the data buffer, so we need a privately owned skb -+ */ -+ -+ /* Code borrowed from skb_unshare(). */ -+ if (skb_cloned(skb)) { -+ struct sk_buff *nskb = skb_copy(skb, GFP_ATOMIC); -+ kfree_skb(skb); -+ skb = nskb; -+ /* skb_copy() has now linearized the skbuff. */ -+ } else if (unlikely(nonlinear)) { -+ /* We are here because the egress skb contains -+ * more fragments than we support. In this case, -+ * we have no choice but to linearize it ourselves. -+ */ -+ err = __skb_linearize(skb); -+ } -+ if (unlikely(!skb || err < 0)) { -+ /* Common out-of-memory error path */ -+ goto enomem; -+ } -+ -+ /* Finally, create a contig FD from this skb */ -+ err = skb_to_contig_fd(dpa_priv, skb, &fd, countptr, &offset); -+ } -+ if (unlikely(err < 0)) -+ goto skb_to_fd_failed; -+ -+ if (fd.bpid != 0xff) { -+ skb_recycle(skb); -+ /* skb_recycle() reserves NET_SKB_PAD as skb headroom, -+ * but we need the skb to look as if returned by build_skb(). -+ * We need to manually adjust the tailptr as well. -+ */ -+ skb->data = skb->head + offset; -+ skb_reset_tail_pointer(skb); -+ -+ (*countptr)++; -+ dpa_percpu_priv->tx_returned++; -+ } -+ -+ egress_fq = selected_macsec_priv->egress_fqs[smp_processor_id()]; -+ if (fd.bpid == 0xff) -+ fd.cmd |= qman_fq_fqid(macsec_get_tx_conf_queue( -+ selected_macsec_priv, -+ egress_fq)); -+ -+ for (i = 0; i < 100000; i++) { -+ err = qman_enqueue(egress_fq, &fd, 0); -+ if (err != -EBUSY) -+ break; -+ } -+ -+ if (unlikely(err < 0)) { -+ dpa_percpu_priv->stats.tx_errors++; -+ dpa_percpu_priv->stats.tx_fifo_errors++; -+ goto xmit_failed; -+ } -+ -+ macsec_percpu_priv->tx_macsec++; -+ dpa_percpu_priv->stats.tx_packets++; -+ dpa_percpu_priv->stats.tx_bytes += dpa_fd_length(&fd); -+ -+ net_dev->trans_start = jiffies; -+ return DPAA_ETH_STOLEN; -+ -+xmit_failed: -+ if (fd.bpid != 0xff) { -+ (*countptr)--; -+ dpa_percpu_priv->tx_returned--; -+ dpa_fd_release(net_dev, &fd); -+ dpa_percpu_priv->stats.tx_errors++; -+ return DPAA_ETH_STOLEN; -+ } -+ _dpa_cleanup_tx_fd(dpa_priv, &fd); -+skb_to_fd_failed: -+enomem: -+ dpa_percpu_priv->stats.tx_errors++; -+ dev_kfree_skb(skb); -+ return DPAA_ETH_STOLEN; -+} -+ -+/* Allocate and initialize macsec priv and fqs. Also, create debugfs entry for -+ * a spcific interface. Iterate thourgh existing devices in order to find the -+ * one we want to have macsec for. -+ */ -+static int macsec_setup(void) -+{ -+ struct net_device *net_dev; -+ struct macsec_percpu_priv_s *percpu_priv = NULL; -+ struct dpa_priv_s *dpa_priv = NULL; -+ struct dpa_fq *dpa_fq; -+ struct device *dev = NULL; -+ int err, i, j, macsec_id; -+ -+ pr_debug("Entering: %s\n", __func__); -+ -+ for (i = 0; i < FM_MAX_NUM_OF_MACS; i++) { -+ macsec_priv[i] = kzalloc(sizeof(*(macsec_priv[i])), GFP_KERNEL); -+ -+ if (unlikely(macsec_priv[i] == NULL)) { -+ int j; -+ for (j = 0; j < i; j++) -+ kfree(macsec_priv[j]); -+ pr_err("could not allocate\n"); -+ return -ENOMEM; -+ } -+ } -+ -+ for (i = 0; i < macsec_ifs_cnt; i++) { -+ net_dev = first_net_device(&init_net); -+ macsec_id = net_dev->ifindex - 1; -+ while (net_dev) { -+ macsec_id = net_dev->ifindex - 1; -+ -+ /* to maintain code readability and less than -+ * 80 characters per line -+ */ -+ if (strcmp(net_dev->name, macsec_ifs[i]) != 0) { -+ net_dev = next_net_device(net_dev); -+ continue; -+ } -+ -+ /* strcmp(net_dev->name, macsec_ifs[i]) == 0 */ -+ macsec_priv[macsec_id]->en_state = MACSEC_DISABLED; -+ macsec_priv[macsec_id]->net_dev = net_dev; -+ dpa_priv = netdev_priv(net_dev); -+ macsec_priv[macsec_id]->mac_dev = dpa_priv->mac_dev; -+ macsec_priv[macsec_id]->channel = dpa_priv->channel; -+ dev = net_dev->dev.parent; -+ -+ INIT_LIST_HEAD(&macsec_priv[macsec_id]->dpa_fq_list); -+ -+ dpa_fq = dpa_fq_alloc(dev, -+ tx_fqids->start, tx_fqids->count, -+ &macsec_priv[macsec_id]->dpa_fq_list, -+ FQ_TYPE_TX); -+ if (unlikely(dpa_fq == NULL)) { -+ dev_err(dev, "dpa_fq_alloc() failed\n"); -+ return -ENOMEM; -+ } -+ -+ dpa_fq = dpa_fq_alloc(dev, -+ tx_confirm_fqids->start, -+ tx_confirm_fqids->count, -+ &macsec_priv[macsec_id]->dpa_fq_list, -+ FQ_TYPE_TX_CONF_MQ); -+ if (unlikely(dpa_fq == NULL)) { -+ dev_err(dev, "dpa_fq_alloc() failed\n"); -+ return -ENOMEM; -+ } -+ -+ macsec_fq_setup(macsec_priv[macsec_id], &private_fq_cbs, -+ macsec_priv[macsec_id]->mac_dev->port_dev[TX]); -+ -+ alloc_priv(percpu_priv, macsec_priv[macsec_id], dev); -+ -+ break; -+ } -+ if (macsec_priv[macsec_id]->net_dev == NULL) { -+ pr_err("Interface unknown\n"); -+ err = -EINVAL; -+ goto _error; -+ } -+ -+ /* setup specific ethtool ops for macsec */ -+ macsec_setup_ethtool_ops(net_dev); -+ } -+ return 0; -+ -+_error: -+ for (j = 0; j < i; i++) { -+ net_dev = first_net_device(&init_net); -+ while (net_dev) { -+ macsec_id = net_dev->ifindex - 1; -+ if (strcmp(net_dev->name, macsec_ifs[j]) != 0) { -+ net_dev = next_net_device(net_dev); -+ continue; -+ } -+ dpa_fq_free(net_dev->dev.parent, -+ &macsec_priv[macsec_id]->dpa_fq_list); -+ break; -+ } -+ macsec_restore_ethtool_ops(macsec_priv[j]->net_dev); -+ kfree(macsec_priv[j]); -+ } -+ for (j = i; j < FM_MAX_NUM_OF_MACS; j++) -+ kfree(macsec_priv[j]); -+ return err; -+} -+ -+static int enable_macsec(struct generic_msg *gen) -+{ -+ struct fm_macsec_params macsec_params; -+ int rv, macsec_id; -+ void __iomem *mac_dev_base_addr; -+ uintptr_t macsec_reg_addr; -+ struct macsec_data *mdata; -+ char if_name[IFNAMSIZ]; -+ struct macsec_priv_s *selected_macsec_priv; -+ -+ mdata = &gen->payload.en_macsec; -+ -+ if (unlikely(mdata->if_name_length > IFNAMSIZ)) { -+ pr_err("interface name too long\n"); -+ return -EINVAL; -+ } -+ -+ rv = copy_from_user(if_name, mdata->if_name, mdata->if_name_length); -+ if (unlikely(rv != 0)) { -+ pr_err("copy_from_user could not copy %i bytes\n", rv); -+ return -EFAULT; -+ } -+ -+ macsec_id = ifname_to_id(if_name); -+ if (macsec_id < 0 || macsec_id >= FM_MAX_NUM_OF_MACS) { -+ pr_err("error on converting to macsec_id\n"); -+ return -ENXIO; -+ } -+ -+ selected_macsec_priv = macsec_priv[macsec_id]; -+ -+ if (selected_macsec_priv->fm_macsec) { -+ pr_err("macsec has already been configured\n"); -+ return -EINVAL; -+ } -+ -+ mac_dev_base_addr = selected_macsec_priv->mac_dev->vaddr; -+ -+ macsec_reg_addr = (uintptr_t)(mac_dev_base_addr + MACSEC_REG_OFFSET); -+ -+ memset(&macsec_params, 0, sizeof(macsec_params)); -+ macsec_params.fm_h = (handle_t)selected_macsec_priv->mac_dev->fm; -+ macsec_params.guest_mode = FALSE; -+ /* The MACsec offset relative to the memory mapped MAC device */ -+ macsec_params.non_guest_params.base_addr = macsec_reg_addr; -+ macsec_params.non_guest_params.fm_mac_h = -+ (handle_t)selected_macsec_priv->mac_dev->get_mac_handle( -+ selected_macsec_priv->mac_dev); -+ macsec_params.non_guest_params.exception_f = macsec_exception; -+ macsec_params.non_guest_params.app_h = selected_macsec_priv->mac_dev; -+ -+ selected_macsec_priv->fm_macsec = fm_macsec_config(&macsec_params); -+ if (unlikely(selected_macsec_priv->fm_macsec == NULL)) -+ return -EINVAL; -+ -+ if (mdata->config_unknown_sci_treatment) { -+ rv = fm_macsec_config_unknown_sci_frame_treatment( -+ selected_macsec_priv->fm_macsec, -+ mdata->unknown_sci_treatment); -+ if (unlikely(rv < 0)) -+ goto _return_fm_macsec_free; -+ } -+ -+ if (mdata->config_invalid_tag_treatment) { -+ rv = fm_macsec_config_invalid_tags_frame_treatment( -+ selected_macsec_priv->fm_macsec, -+ mdata->deliver_uncontrolled); -+ if (unlikely(rv < 0)) -+ goto _return_fm_macsec_free; -+ } -+ -+ if (mdata->config_kay_frame_treatment) { -+ rv = fm_macsec_config_kay_frame_treatment( -+ selected_macsec_priv->fm_macsec, -+ mdata->discard_uncontrolled); -+ if (unlikely(rv < 0)) -+ goto _return_fm_macsec_free; -+ } -+ -+ if (mdata->config_untag_treatment) { -+ rv = fm_macsec_config_untag_frame_treatment( -+ selected_macsec_priv->fm_macsec, -+ mdata->untag_treatment); -+ if (unlikely(rv < 0)) -+ goto _return_fm_macsec_free; -+ } -+ -+ if (mdata->config_pn_exhaustion_threshold) { -+ rv = fm_macsec_config_pn_exhaustion_threshold( -+ selected_macsec_priv->fm_macsec, -+ mdata->pn_threshold); -+ if (unlikely(rv < 0)) -+ goto _return_fm_macsec_free; -+ } -+ -+ if (mdata->config_keys_unreadable) { -+ rv = fm_macsec_config_keys_unreadable( -+ selected_macsec_priv->fm_macsec); -+ if (unlikely(rv < 0)) -+ goto _return_fm_macsec_free; -+ } -+ -+ if (mdata->config_sectag_without_sci) { -+ rv = fm_macsec_config_sectag_without_sci( -+ selected_macsec_priv->fm_macsec); -+ if (unlikely(rv < 0)) -+ goto _return_fm_macsec_free; -+ } -+ -+ if (mdata->config_exception) { -+ rv = fm_macsec_config_exception(selected_macsec_priv->fm_macsec, -+ mdata->exception, -+ mdata->enable_exception); -+ if (unlikely(rv < 0)) -+ goto _return_fm_macsec_free; -+ } -+ -+ rv = fm_macsec_init(selected_macsec_priv->fm_macsec); -+ if (unlikely(rv < 0)) -+ goto _return_fm_macsec_free; -+ -+ rv = fm_macsec_enable(selected_macsec_priv->fm_macsec); -+ if (unlikely(rv < 0)) -+ goto _return_fm_macsec_free; -+ -+ return macsec_id; -+ -+_return_fm_macsec_free: -+ fm_macsec_free(selected_macsec_priv->fm_macsec); -+ selected_macsec_priv->fm_macsec = NULL; -+ return rv; -+} -+ -+static int send_result(struct nlmsghdr *nlh, int pid, int result) -+{ -+ int res; -+ struct sk_buff *skb_out; -+ size_t msg_size = sizeof(result); -+ -+ skb_out = nlmsg_new(msg_size, 0); -+ if (unlikely(!skb_out)) { -+ pr_err("Failed to allocate new skb\n"); -+ goto _ret_err; -+ } -+ -+ nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, msg_size, 0); -+ if (unlikely(!nlh)) { -+ pr_err("Failed to send\n"); -+ goto _ret_err; -+ } -+ -+ NETLINK_CB(skb_out).dst_group = 0; /* not in mcast group */ -+ memcpy(nlmsg_data(nlh), &result, msg_size); -+ -+ res = nlmsg_unicast(nl_sk, skb_out, pid); -+ if (unlikely(res < 0)) { -+ pr_err("Error while sending back to user\n"); -+ goto _ret_err; -+ } -+ -+ return 0; -+ -+_ret_err: -+ return -1; -+} -+ -+/* Kernel communicates with user space through netlink sockets. This function -+ * implements the responses of the kernel. The generic struct is used for -+ * easier handling of the code, which otherwise would have been duplicated. -+ */ -+static void switch_messages(struct sk_buff *skb) -+{ -+ struct nlmsghdr *nlh; -+ int pid, rv; -+ enum msg_type cmd; -+ -+ struct dpa_fq *dpa_fq, *tmp; -+ struct device *dev; -+ -+ struct dpaa_eth_hooks_s macsec_dpaa_eth_hooks; -+ -+ struct generic_msg *check; -+ int macsec_id = 0; -+ uint32_t sc_id, macsec_revision; -+ macsec_an_t ret_an; -+ int i; -+ -+ pr_debug("Entering: %s\n", __func__); -+ -+ if (unlikely(!skb)) { -+ pr_err("skb null\n"); -+ return; -+ } -+ -+ nlh = (struct nlmsghdr *)skb->data; -+ check = kmalloc(sizeof(*check), GFP_KERNEL); -+ memcpy(check, nlmsg_data(nlh), sizeof(*check)); -+ pid = nlh->nlmsg_pid; /*pid of sending process */ -+ cmd = check->chf; -+ -+ switch (cmd) { -+ case ENABLE_MACSEC: -+ pr_debug("ENABLE_MACSEC\n"); -+ -+ macsec_id = enable_macsec(check); -+ -+ if (macsec_id >= 0) -+ macsec_priv[macsec_id]->en_state = MACSEC_ENABLED; -+ -+ rv = send_result(nlh, pid, (macsec_id < 0) ? NACK : macsec_id); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case SET_EXCEPTION: -+ pr_debug("SET_EXCEPTION\n"); -+ -+ rv = set_macsec_exception(check); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case ENABLE_SECY: -+ pr_debug("ENABLE_SECY\n"); -+ -+ rv = enable_secy(check, &macsec_id); -+ -+ if (rv == 0) -+ macsec_priv[macsec_id]->en_state = SECY_ENABLED; -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case GET_REVISION: -+ pr_debug("GET_REVISION\n"); -+ -+ rv = get_macsec_revision(check, &macsec_revision); -+ -+ rv = send_result(nlh, pid, -+ (rv < 0) ? NACK : (int)macsec_revision); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case GET_TXSC_PHYS_ID: -+ pr_debug("GET_TXSC_PHYS_ID\n"); -+ -+ rv = get_tx_sc_phys_id(check, &sc_id); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : (int)sc_id); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case TX_SA_CREATE: -+ pr_debug("TX_SA_CREATE\n"); -+ -+ rv = create_tx_sa(check); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case MODIFY_TXSA_KEY: -+ pr_debug("MODIFY_TXSA_KEY\n"); -+ -+ rv = modify_tx_sa_key(check); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case TX_SA_ACTIVATE: -+ pr_debug("TX_SA_ACTIVATE\n"); -+ -+ rv = activate_tx_sa(check); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case GET_TXSA_AN: -+ pr_debug("GET_TXSA_AN\n"); -+ -+ rv = get_tx_sa_an(check, &ret_an); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : (int)ret_an); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case RX_SC_CREATE: -+ pr_debug("RX_SC_CREATE\n"); -+ -+ sc_id = create_rx_sc(check); -+ -+ rv = send_result(nlh, pid, (sc_id < 0) ? NACK : (int)sc_id); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case GET_RXSC_PHYS_ID: -+ pr_debug("GET_RXSC_PHYS_ID\n"); -+ -+ rv = get_rx_sc_phys_id(check, &sc_id); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : (int)sc_id); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case RX_SA_CREATE: -+ pr_debug("RX_SA_CREATE\n"); -+ -+ rv = create_rx_sa(check); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case MODIFY_RXSA_KEY: -+ pr_debug("MODIFY_RXSA_KEY\n"); -+ -+ rv = modify_rx_sa_key(check); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case UPDATE_NPN: -+ pr_debug("UPDATE_NPN\n"); -+ -+ rv = update_npn(check); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case UPDATE_LPN: -+ pr_debug("UPDATE_LPN\n"); -+ -+ rv = update_lpn(check); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case RX_SA_ACTIVATE: -+ pr_debug("RX_SA_ACTIVATE\n"); -+ -+ rv = activate_rx_sa(check); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case RX_SA_DISABLE: -+ pr_debug("RX_SA_DISABLE\n"); -+ -+ rv = rx_sa_disable(check); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case RX_SA_DELETE: -+ pr_debug("RX_SA_DELETE\n"); -+ -+ rv = rx_sa_delete(check); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case RX_SC_DELETE: -+ pr_debug("RX_SC_DELETE\n"); -+ -+ rv = rx_sc_delete(check); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case TX_SA_DELETE: -+ pr_debug("TX_SA_DELETE\n"); -+ -+ rv = tx_sa_delete(check); -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case DISABLE_SECY: -+ pr_debug("DISABLE_SECY\n"); -+ -+ rv = disable_secy(check, &macsec_id); -+ -+ if (unlikely(rv < 0)) -+ macsec_priv[macsec_id]->en_state = SECY_ENABLED; -+ else -+ macsec_priv[macsec_id]->en_state = MACSEC_ENABLED; -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case DISABLE_MACSEC: -+ pr_debug("DISABLE_MACSEC\n"); -+ -+ rv = disable_macsec(check, &macsec_id); -+ -+ macsec_priv[macsec_id]->en_state = MACSEC_DISABLED; -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ -+ break; -+ -+ case DISABLE_ALL: -+ pr_debug("DISABLE_ALL\n"); -+ -+ rv = disable_all(check, &macsec_id); -+ -+ macsec_priv[macsec_id]->en_state = MACSEC_DISABLED; -+ -+ rv = send_result(nlh, pid, (rv < 0) ? NACK : ACK); -+ if (unlikely(rv < 0)) -+ goto _release; -+ break; -+ -+ default: -+ /* should never get here */ -+ pr_err("not a state\n"); -+ break; -+ } -+ -+ return; -+ -+_release: -+ for (i = 0; i < FM_MAX_NUM_OF_MACS; i++) -+ deinit_macsec(i); -+ -+ /* Reset the TX hooks */ -+ memset(&macsec_dpaa_eth_hooks, 0, sizeof(macsec_dpaa_eth_hooks)); -+ fsl_dpaa_eth_set_hooks(&macsec_dpaa_eth_hooks); -+ -+ for (i = 0; i < FM_MAX_NUM_OF_MACS; i++) { -+ -+ if (!macsec_priv[i]->net_dev) -+ continue; -+ -+ free_percpu(macsec_priv[i]->percpu_priv); -+ -+ /* Delete the fman queues */ -+ list_for_each_entry_safe(dpa_fq, -+ tmp, -+ &macsec_priv[i]->dpa_fq_list, -+ list) { -+ dev = dpa_fq->net_dev->dev.parent; -+ rv = _dpa_fq_free(dev, (struct qman_fq *)dpa_fq); -+ if (unlikely(rv < 0)) -+ pr_err("_dpa_fq_fre=%d\n", rv); -+ } -+ -+ macsec_restore_ethtool_ops(macsec_priv[i]->net_dev); -+ kfree(macsec_priv[i]); -+ macsec_priv[i] = NULL; -+ } -+ -+ kfree(check); -+ -+ netlink_kernel_release(nl_sk); -+} -+ -+struct netlink_kernel_cfg ms_cfg = { -+ .groups = 1, -+ .input = switch_messages, -+}; -+ -+static int __init macsec_init(void) -+{ -+ struct dpaa_eth_hooks_s macsec_dpaa_eth_hooks; -+ int ret, i; -+ -+ pr_debug("Entering: %s\n", __func__); -+ -+ /* If there is no interface we want macsec on, just exit. */ -+ parse_ifs(); -+ for (i = 0; i < macsec_ifs_cnt; i++) { -+ if (!macsec_ifs[i]) { -+ pr_err("Interface unknown\n"); -+ return -EINVAL; -+ } -+ } -+ -+ /* Actually send the info to the user through a given socket. */ -+ nl_sk = netlink_kernel_create(&init_net, NETLINK_USER, &ms_cfg); -+ if (unlikely(!nl_sk)) { -+ pr_err("Error creating socket.\n"); -+ ret = -ENOMEM; -+ goto _release; -+ } -+ -+ ret = macsec_setup(); -+ if (unlikely(ret != 0)) { -+ pr_err("Setup of macsec failed\n"); -+ goto _release; -+ } -+ -+ /* set dpaa hooks for default queues */ -+ memset(&macsec_dpaa_eth_hooks, 0, sizeof(macsec_dpaa_eth_hooks)); -+ macsec_dpaa_eth_hooks.tx = (dpaa_eth_egress_hook_t)(macsec_tx_hook); -+ macsec_dpaa_eth_hooks.rx_default = -+ (dpaa_eth_ingress_hook_t)(macsec_rx_hook); -+ -+ fsl_dpaa_eth_set_hooks(&macsec_dpaa_eth_hooks); -+ -+ return 0; -+ -+_release: -+ memset(&macsec_dpaa_eth_hooks, 0, sizeof(macsec_dpaa_eth_hooks)); -+ fsl_dpaa_eth_set_hooks(&macsec_dpaa_eth_hooks); -+ netlink_kernel_release(nl_sk); -+ return ret; -+} -+ -+static void __exit macsec_exit(void) -+{ -+ int _errno; -+ struct dpa_fq *dpa_fq, *tmp; -+ struct device *dev; -+ struct dpaa_eth_hooks_s macsec_dpaa_eth_hooks; -+ int i; -+ -+ pr_debug("exiting macsec module\n"); -+ -+ for (i = 0; i < FM_MAX_NUM_OF_MACS; i++) { -+ /* release has already been done, due to errors, -+ * in switch_messages we will return to exit the module properly -+ */ -+ if (!macsec_priv[i]->net_dev) { -+ pr_debug("no release needed\n"); -+ continue; -+ } -+ deinit_macsec(i); -+ } -+ -+ /* Reset the TX hooks before exiting */ -+ memset(&macsec_dpaa_eth_hooks, 0, sizeof(macsec_dpaa_eth_hooks)); -+ fsl_dpaa_eth_set_hooks(&macsec_dpaa_eth_hooks); -+ -+ for (i = 0; i < FM_MAX_NUM_OF_MACS; i++) { -+ -+ if (!macsec_priv[i]->net_dev) { -+ pr_debug("no release needed\n"); -+ continue; -+ } -+ -+ free_percpu(macsec_priv[i]->percpu_priv); -+ -+ /* Delete the fman queues */ -+ list_for_each_entry_safe(dpa_fq, tmp, -+ &macsec_priv[i]->dpa_fq_list, list) { -+ if (dpa_fq) { -+ dev = dpa_fq->net_dev->dev.parent; -+ _errno = _dpa_fq_free(dev, -+ (struct qman_fq *)dpa_fq); -+ if (unlikely(_errno < 0)) -+ pr_err("_dpa_fq_fre=%d\n", _errno); -+ } -+ } -+ -+ /* restore ethtool ops to the previous private ones */ -+ macsec_restore_ethtool_ops(macsec_priv[i]->net_dev); -+ -+ kfree(macsec_priv[i]); -+ } -+ -+ netlink_kernel_release(nl_sk); -+ -+ pr_debug("exited macsec module\n"); -+} -+ -+module_init(macsec_init); -+module_exit(macsec_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_macsec.h -@@ -0,0 +1,294 @@ -+/* Copyright 2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __DPAA_ETH_MACSEC_H -+#define __DPAA_ETH_MACSEC_H -+ -+#include "mac.h" -+ -+#define NETLINK_USER 31 -+#define MAX_NUM_OF_SECY 1 -+#define MAX_LEN 100 -+#define FM_FD_STAT_RX_MACSEC 0x00800000 -+#define MACSEC_ETH_TX_QUEUES NR_CPUS -+#define MACSEC_REG_OFFSET 0x800 -+#define ACK 0 -+#define NACK -1 -+ -+extern const struct dpa_fq_cbs_t private_fq_cbs; -+ -+extern int dpa_macsec_get_sset_count(struct net_device *net_dev, int type); -+extern void -+dpa_macsec_get_ethtool_stats(struct net_device *net_dev, -+ struct ethtool_stats *stats, u64 *data); -+extern void -+dpa_macsec_get_strings(struct net_device *net_dev, -+ u32 stringset, u8 *data); -+ -+enum msg_type {ENABLE_MACSEC, -+ SET_EXCEPTION, -+ ENABLE_SECY, -+ TX_SA_CREATE, -+ TX_SA_ACTIVATE, -+ RX_SC_CREATE, -+ RX_SA_CREATE, -+ RX_SA_ACTIVATE, -+ RX_SA_DISABLE, -+ RX_SA_DELETE, -+ RX_SC_DELETE, -+ TX_SA_DELETE, -+ DISABLE_MACSEC, -+ DISABLE_SECY, -+ DISABLE_ALL, -+ GET_REVISION, -+ UPDATE_NPN, -+ UPDATE_LPN, -+ GET_TXSC_PHYS_ID, -+ GET_RXSC_PHYS_ID, -+ GET_TXSA_AN, -+ MODIFY_TXSA_KEY, -+ MODIFY_RXSA_KEY, -+}; -+ -+enum macsec_enablement {MACSEC_DISABLED, MACSEC_ENABLED, SECY_ENABLED}; -+ -+struct enable_secy { -+ int macsec_id; -+ -+ u64 sci; /* MAC address(48b) + port_id(16b) */ -+ -+ bool config_insertion_mode; -+ fm_macsec_sci_insertion_mode sci_insertion_mode; -+ -+ bool config_protect_frames; -+ bool protect_frames; -+ -+ bool config_replay_window; -+ bool replay_protect; -+ uint32_t replay_window; -+ -+ bool config_validation_mode; -+ fm_macsec_valid_frame_behavior validate_frames; -+ -+ bool config_confidentiality; -+ bool confidentiality_enable; -+ uint32_t confidentiality_offset; -+ -+ bool config_point_to_point; -+ -+ bool config_exception; -+ bool enable_exception; -+ fm_macsec_secy_exception exception; -+ -+ bool config_event; -+ bool enable_event; -+ fm_macsec_secy_event event; -+}; -+ -+struct macsec_data { -+ char *if_name; -+ size_t if_name_length; /* including string terminator */ -+ -+ bool config_unknown_sci_treatment; -+ fm_macsec_unknown_sci_frame_treatment unknown_sci_treatment; -+ -+ bool config_invalid_tag_treatment; -+ bool deliver_uncontrolled; -+ -+ bool config_kay_frame_treatment; -+ bool discard_uncontrolled; -+ -+ bool config_untag_treatment; -+ fm_macsec_untag_frame_treatment untag_treatment; -+ -+ bool config_pn_exhaustion_threshold; -+ uint32_t pn_threshold; -+ -+ bool config_keys_unreadable; -+ -+ bool config_sectag_without_sci; -+ -+ bool config_exception; -+ bool enable_exception; -+ fm_macsec_exception exception; -+}; -+ -+struct set_exception { -+ int macsec_id; -+ bool enable_exception; -+ fm_macsec_exception exception; -+}; -+ -+struct create_tx_sa { -+ int macsec_id; -+ u8 an; /* association number */ -+ u8 *sak; /* secure assoc key */ -+ u32 sak_len; /* assoc key length */ -+}; -+ -+struct modify_tx_sa_key { -+ int macsec_id; -+ u8 an; /* association number */ -+ u8 *sak; /* secure assoc key */ -+ u32 sak_len; /* assoc key length */ -+}; -+ -+struct activate_tx_sa { -+ int macsec_id; -+ u8 an; /* association number */ -+}; -+ -+struct create_rx_sc { -+ int macsec_id; -+ u64 sci; -+}; -+ -+struct delete_rx_sc { -+ int macsec_id; -+ u32 rx_sc_id; -+}; -+ -+struct get_rx_sc_id { -+ int macsec_id; -+ u32 rx_sc_id; -+}; -+ -+struct create_rx_sa { -+ int macsec_id; -+ u32 rx_sc_id; -+ u8 an; -+ u32 lpn; -+ u8 *sak; -+ u32 sak_len; -+}; -+ -+struct activate_rx_sa { -+ int macsec_id; -+ u32 rx_sc_id; -+ u8 an; -+}; -+ -+struct disable_rx_sa { -+ int macsec_id; -+ u32 rx_sc_id; -+ u8 an; -+}; -+ -+struct delete_rx_sa { -+ int macsec_id; -+ u32 rx_sc_id; -+ u8 an; -+}; -+ -+struct delete_tx_sa { -+ int macsec_id; -+ u32 rx_sc_id; -+ u8 an; -+}; -+ -+struct update_npn { -+ int macsec_id; -+ u32 rx_sc_id; -+ u8 an; -+ u32 pn; -+}; -+ -+struct update_lpn { -+ int macsec_id; -+ u32 rx_sc_id; -+ u8 an; -+ u32 pn; -+}; -+ -+struct modify_rx_sa_key { -+ int macsec_id; -+ u32 rx_sc_id; -+ u8 an; -+ u8 *sak; -+ u32 sak_len; -+}; -+ -+struct generic_msg { -+ enum msg_type chf; -+ union { -+ int macsec_id; -+ struct macsec_data en_macsec; -+ struct enable_secy secy; -+ struct create_tx_sa c_tx_sa; -+ struct activate_tx_sa a_tx_sa; -+ struct create_rx_sc c_rx_sc; -+ struct get_rx_sc_id get_rx_sc_id; -+ struct create_rx_sa c_rx_sa; -+ struct activate_rx_sa a_rx_sa; -+ struct disable_rx_sa d_rx_sa; -+ struct delete_rx_sa del_rx_sa; -+ struct delete_rx_sc del_rx_sc; -+ struct delete_tx_sa del_tx_sa; -+ struct update_npn update_npn; -+ struct update_lpn update_lpn; -+ struct modify_tx_sa_key modify_tx_sa_key; -+ struct modify_rx_sa_key modify_rx_sa_key; -+ struct set_exception set_ex; -+ } payload; -+}; -+ -+struct macsec_percpu_priv_s { -+ u64 rx_macsec; -+ u64 tx_macsec; -+}; -+ -+struct macsec_priv_s { -+ struct macsec_percpu_priv_s __percpu *percpu_priv; -+ -+ struct net_device *net_dev; -+ struct mac_device *mac_dev; -+ -+ struct qman_fq *egress_fqs[MACSEC_ETH_TX_QUEUES]; -+ struct qman_fq *conf_fqs[MACSEC_ETH_TX_QUEUES]; -+ struct list_head dpa_fq_list; -+ uint32_t msg_enable; /* net_device message level */ -+ uint16_t channel; -+ struct fm_macsec_dev *fm_macsec; -+ -+ struct fm_macsec_secy_dev *fm_ms_secy; -+ uint8_t an; -+ -+ struct rx_sc_dev *rx_sc_dev[NUM_OF_RX_SC]; -+ uint8_t *sa_key; -+ enum macsec_enablement en_state; -+ -+ uintptr_t vaddr; -+ struct resource *fman_resource; -+}; -+ -+struct macsec_priv_s *dpa_macsec_get_priv(struct net_device *net_dev); -+ -+#endif /* __DPAA_ETH_MACSEC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_proxy.c -@@ -0,0 +1,381 @@ -+/* Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifdef CONFIG_FSL_DPAA_ETH_DEBUG -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": %s:%hu:%s() " fmt, \ -+ KBUILD_BASENAME".c", __LINE__, __func__ -+#else -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": " fmt -+#endif -+ -+#include -+#include -+#include -+#include "dpaa_eth.h" -+#include "dpaa_eth_common.h" -+#include "dpaa_eth_base.h" -+#include "lnxwrp_fsl_fman.h" /* fm_get_rx_extra_headroom(), fm_get_max_frm() */ -+#include "mac.h" -+ -+#define DPA_DESCRIPTION "FSL DPAA Proxy initialization driver" -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+ -+MODULE_DESCRIPTION(DPA_DESCRIPTION); -+ -+static int __cold dpa_eth_proxy_remove(struct platform_device *of_dev); -+#ifdef CONFIG_PM -+ -+static int proxy_suspend(struct device *dev) -+{ -+ struct proxy_device *proxy_dev = dev_get_drvdata(dev); -+ struct mac_device *mac_dev = proxy_dev->mac_dev; -+ int err = 0; -+ -+ err = fm_port_suspend(mac_dev->port_dev[RX]); -+ if (err) -+ goto port_suspend_failed; -+ -+ err = fm_port_suspend(mac_dev->port_dev[TX]); -+ if (err) -+ err = fm_port_resume(mac_dev->port_dev[RX]); -+ -+port_suspend_failed: -+ return err; -+} -+ -+static int proxy_resume(struct device *dev) -+{ -+ struct proxy_device *proxy_dev = dev_get_drvdata(dev); -+ struct mac_device *mac_dev = proxy_dev->mac_dev; -+ int err = 0; -+ -+ err = fm_port_resume(mac_dev->port_dev[TX]); -+ if (err) -+ goto port_resume_failed; -+ -+ err = fm_port_resume(mac_dev->port_dev[RX]); -+ if (err) -+ err = fm_port_suspend(mac_dev->port_dev[TX]); -+ -+port_resume_failed: -+ return err; -+} -+ -+static const struct dev_pm_ops proxy_pm_ops = { -+ .suspend = proxy_suspend, -+ .resume = proxy_resume, -+}; -+ -+#define PROXY_PM_OPS (&proxy_pm_ops) -+ -+#else /* CONFIG_PM */ -+ -+#define PROXY_PM_OPS NULL -+ -+#endif /* CONFIG_PM */ -+ -+static int dpaa_eth_proxy_probe(struct platform_device *_of_dev) -+{ -+ int err = 0, i; -+ struct device *dev; -+ struct device_node *dpa_node; -+ struct dpa_bp *dpa_bp; -+ struct list_head proxy_fq_list; -+ size_t count; -+ struct fm_port_fqs port_fqs; -+ struct dpa_buffer_layout_s *buf_layout = NULL; -+ struct mac_device *mac_dev; -+ struct proxy_device *proxy_dev; -+ -+ dev = &_of_dev->dev; -+ -+ dpa_node = dev->of_node; -+ -+ if (!of_device_is_available(dpa_node)) -+ return -ENODEV; -+ -+ /* Get the buffer pools assigned to this interface */ -+ dpa_bp = dpa_bp_probe(_of_dev, &count); -+ if (IS_ERR(dpa_bp)) -+ return PTR_ERR(dpa_bp); -+ -+ mac_dev = dpa_mac_probe(_of_dev); -+ if (IS_ERR(mac_dev)) -+ return PTR_ERR(mac_dev); -+ -+ proxy_dev = devm_kzalloc(dev, sizeof(*proxy_dev), GFP_KERNEL); -+ if (!proxy_dev) { -+ dev_err(dev, "devm_kzalloc() failed\n"); -+ return -ENOMEM; -+ } -+ -+ proxy_dev->mac_dev = mac_dev; -+ dev_set_drvdata(dev, proxy_dev); -+ -+ /* We have physical ports, so we need to establish -+ * the buffer layout. -+ */ -+ buf_layout = devm_kzalloc(dev, 2 * sizeof(*buf_layout), -+ GFP_KERNEL); -+ if (!buf_layout) { -+ dev_err(dev, "devm_kzalloc() failed\n"); -+ return -ENOMEM; -+ } -+ dpa_set_buffers_layout(mac_dev, buf_layout); -+ -+ INIT_LIST_HEAD(&proxy_fq_list); -+ -+ memset(&port_fqs, 0, sizeof(port_fqs)); -+ -+ err = dpa_fq_probe_mac(dev, &proxy_fq_list, &port_fqs, true, RX); -+ if (!err) -+ err = dpa_fq_probe_mac(dev, &proxy_fq_list, &port_fqs, true, -+ TX); -+ if (err < 0) { -+ devm_kfree(dev, buf_layout); -+ return err; -+ } -+ -+ /* Proxy initializer - Just configures the MAC on behalf of -+ * another partition. -+ */ -+ dpaa_eth_init_ports(mac_dev, dpa_bp, count, &port_fqs, -+ buf_layout, dev); -+ -+ /* Proxy interfaces need to be started, and the allocated -+ * memory freed -+ */ -+ devm_kfree(dev, buf_layout); -+ devm_kfree(dev, dpa_bp); -+ -+ /* Free FQ structures */ -+ devm_kfree(dev, port_fqs.rx_defq); -+ devm_kfree(dev, port_fqs.rx_errq); -+ devm_kfree(dev, port_fqs.tx_defq); -+ devm_kfree(dev, port_fqs.tx_errq); -+ -+ for_each_port_device(i, mac_dev->port_dev) { -+ err = fm_port_enable(mac_dev->port_dev[i]); -+ if (err) -+ goto port_enable_fail; -+ } -+ -+ dev_info(dev, "probed MAC device with MAC address: %02hx:%02hx:%02hx:%02hx:%02hx:%02hx\n", -+ mac_dev->addr[0], mac_dev->addr[1], mac_dev->addr[2], -+ mac_dev->addr[3], mac_dev->addr[4], mac_dev->addr[5]); -+ -+ return 0; /* Proxy interface initialization ended */ -+ -+port_enable_fail: -+ for_each_port_device(i, mac_dev->port_dev) -+ fm_port_disable(mac_dev->port_dev[i]); -+ dpa_eth_proxy_remove(_of_dev); -+ -+ return err; -+} -+ -+int dpa_proxy_set_mac_address(struct proxy_device *proxy_dev, -+ struct net_device *net_dev) -+{ -+ struct mac_device *mac_dev; -+ int _errno; -+ -+ mac_dev = proxy_dev->mac_dev; -+ -+ _errno = mac_dev->change_addr(mac_dev->get_mac_handle(mac_dev), -+ net_dev->dev_addr); -+ if (_errno < 0) -+ return _errno; -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpa_proxy_set_mac_address); -+ -+int dpa_proxy_set_rx_mode(struct proxy_device *proxy_dev, -+ struct net_device *net_dev) -+{ -+ struct mac_device *mac_dev = proxy_dev->mac_dev; -+ int _errno; -+ -+ if (!!(net_dev->flags & IFF_PROMISC) != mac_dev->promisc) { -+ mac_dev->promisc = !mac_dev->promisc; -+ _errno = mac_dev->set_promisc(mac_dev->get_mac_handle(mac_dev), -+ mac_dev->promisc); -+ if (unlikely(_errno < 0)) -+ netdev_err(net_dev, "mac_dev->set_promisc() = %d\n", -+ _errno); -+ } -+ -+ _errno = mac_dev->set_multi(net_dev, mac_dev); -+ if (unlikely(_errno < 0)) -+ return _errno; -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpa_proxy_set_rx_mode); -+ -+int dpa_proxy_start(struct net_device *net_dev) -+{ -+ struct mac_device *mac_dev; -+ const struct dpa_priv_s *priv; -+ struct proxy_device *proxy_dev; -+ int _errno; -+ int i; -+ -+ priv = netdev_priv(net_dev); -+ proxy_dev = (struct proxy_device *)priv->peer; -+ mac_dev = proxy_dev->mac_dev; -+ -+ _errno = mac_dev->init_phy(net_dev, mac_dev); -+ if (_errno < 0) { -+ if (netif_msg_drv(priv)) -+ netdev_err(net_dev, "init_phy() = %d\n", -+ _errno); -+ return _errno; -+ } -+ -+ for_each_port_device(i, mac_dev->port_dev) { -+ _errno = fm_port_enable(mac_dev->port_dev[i]); -+ if (_errno) -+ goto port_enable_fail; -+ } -+ -+ _errno = mac_dev->start(mac_dev); -+ if (_errno < 0) { -+ if (netif_msg_drv(priv)) -+ netdev_err(net_dev, "mac_dev->start() = %d\n", -+ _errno); -+ goto port_enable_fail; -+ } -+ -+ return _errno; -+ -+port_enable_fail: -+ for_each_port_device(i, mac_dev->port_dev) -+ fm_port_disable(mac_dev->port_dev[i]); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(dpa_proxy_start); -+ -+int dpa_proxy_stop(struct proxy_device *proxy_dev, struct net_device *net_dev) -+{ -+ struct mac_device *mac_dev = proxy_dev->mac_dev; -+ const struct dpa_priv_s *priv = netdev_priv(net_dev); -+ int _errno, i, err; -+ -+ _errno = mac_dev->stop(mac_dev); -+ if (_errno < 0) { -+ if (netif_msg_drv(priv)) -+ netdev_err(net_dev, "mac_dev->stop() = %d\n", -+ _errno); -+ return _errno; -+ } -+ -+ for_each_port_device(i, mac_dev->port_dev) { -+ err = fm_port_disable(mac_dev->port_dev[i]); -+ _errno = err ? err : _errno; -+ } -+ -+ if (mac_dev->phy_dev) -+ phy_disconnect(mac_dev->phy_dev); -+ mac_dev->phy_dev = NULL; -+ -+ return _errno; -+} -+EXPORT_SYMBOL(dpa_proxy_stop); -+ -+static int __cold dpa_eth_proxy_remove(struct platform_device *of_dev) -+{ -+ struct device *dev = &of_dev->dev; -+ struct proxy_device *proxy_dev = dev_get_drvdata(dev); -+ -+ kfree(proxy_dev); -+ -+ dev_set_drvdata(dev, NULL); -+ -+ return 0; -+} -+ -+static const struct of_device_id dpa_proxy_match[] = { -+ { -+ .compatible = "fsl,dpa-ethernet-init" -+ }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, dpa_proxy_match); -+ -+static struct platform_driver dpa_proxy_driver = { -+ .driver = { -+ .name = KBUILD_MODNAME "-proxy", -+ .of_match_table = dpa_proxy_match, -+ .owner = THIS_MODULE, -+ .pm = PROXY_PM_OPS, -+ }, -+ .probe = dpaa_eth_proxy_probe, -+ .remove = dpa_eth_proxy_remove -+}; -+ -+static int __init __cold dpa_proxy_load(void) -+{ -+ int _errno; -+ -+ pr_info(DPA_DESCRIPTION "\n"); -+ -+ /* Initialize dpaa_eth mirror values */ -+ dpa_rx_extra_headroom = fm_get_rx_extra_headroom(); -+ dpa_max_frm = fm_get_max_frm(); -+ -+ _errno = platform_driver_register(&dpa_proxy_driver); -+ if (unlikely(_errno < 0)) { -+ pr_err(KBUILD_MODNAME -+ ": %s:%hu:%s(): platform_driver_register() = %d\n", -+ KBUILD_BASENAME".c", __LINE__, __func__, _errno); -+ } -+ -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+ -+ return _errno; -+} -+module_init(dpa_proxy_load); -+ -+static void __exit __cold dpa_proxy_unload(void) -+{ -+ platform_driver_unregister(&dpa_proxy_driver); -+ -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+} -+module_exit(dpa_proxy_unload); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_sg.c -@@ -0,0 +1,1128 @@ -+/* Copyright 2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifdef CONFIG_FSL_DPAA_ETH_DEBUG -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": %s:%hu:%s() " fmt, \ -+ KBUILD_BASENAME".c", __LINE__, __func__ -+#else -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": " fmt -+#endif -+ -+#include -+#include -+#include -+#include -+ -+#include "dpaa_eth.h" -+#include "dpaa_eth_common.h" -+#ifdef CONFIG_FSL_DPAA_1588 -+#include "dpaa_1588.h" -+#endif -+#ifdef CONFIG_FSL_DPAA_CEETM -+#include "dpaa_eth_ceetm.h" -+#endif -+ -+/* DMA map and add a page frag back into the bpool. -+ * @vaddr fragment must have been allocated with netdev_alloc_frag(), -+ * specifically for fitting into @dpa_bp. -+ */ -+static void dpa_bp_recycle_frag(struct dpa_bp *dpa_bp, unsigned long vaddr, -+ int *count_ptr) -+{ -+ struct bm_buffer bmb; -+ dma_addr_t addr; -+ -+ memset(&bmb, 0, sizeof(struct bm_buffer)); -+ -+ addr = dma_map_single(dpa_bp->dev, (void *)vaddr, dpa_bp->size, -+ DMA_BIDIRECTIONAL); -+ if (unlikely(dma_mapping_error(dpa_bp->dev, addr))) { -+ dev_err(dpa_bp->dev, "DMA mapping failed"); -+ return; -+ } -+ -+ bm_buffer_set64(&bmb, addr); -+ -+ while (bman_release(dpa_bp->pool, &bmb, 1, 0)) -+ cpu_relax(); -+ -+ (*count_ptr)++; -+} -+ -+static int _dpa_bp_add_8_bufs(const struct dpa_bp *dpa_bp) -+{ -+ struct bm_buffer bmb[8]; -+ void *new_buf; -+ dma_addr_t addr; -+ uint8_t i; -+ struct device *dev = dpa_bp->dev; -+ struct sk_buff *skb, **skbh; -+ -+ memset(bmb, 0, sizeof(struct bm_buffer) * 8); -+ -+ for (i = 0; i < 8; i++) { -+ /* We'll prepend the skb back-pointer; can't use the DPA -+ * priv space, because FMan will overwrite it (from offset 0) -+ * if it ends up being the second, third, etc. fragment -+ * in a S/G frame. -+ * -+ * We only need enough space to store a pointer, but allocate -+ * an entire cacheline for performance reasons. -+ */ -+#ifdef DPAA_LS1043A_DMA_4K_ISSUE -+ new_buf = page_address(alloc_page(GFP_ATOMIC)); -+#else -+ new_buf = netdev_alloc_frag(SMP_CACHE_BYTES + DPA_BP_RAW_SIZE); -+#endif -+ if (unlikely(!new_buf)) -+ goto netdev_alloc_failed; -+ new_buf = PTR_ALIGN(new_buf + SMP_CACHE_BYTES, SMP_CACHE_BYTES); -+ -+ skb = build_skb(new_buf, DPA_SKB_SIZE(dpa_bp->size) + -+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); -+ if (unlikely(!skb)) { -+ put_page(virt_to_head_page(new_buf)); -+ goto build_skb_failed; -+ } -+ DPA_WRITE_SKB_PTR(skb, skbh, new_buf, -1); -+ -+ addr = dma_map_single(dev, new_buf, -+ dpa_bp->size, DMA_BIDIRECTIONAL); -+ if (unlikely(dma_mapping_error(dev, addr))) -+ goto dma_map_failed; -+ -+ bm_buffer_set64(&bmb[i], addr); -+ } -+ -+release_bufs: -+ /* Release the buffers. In case bman is busy, keep trying -+ * until successful. bman_release() is guaranteed to succeed -+ * in a reasonable amount of time -+ */ -+ while (unlikely(bman_release(dpa_bp->pool, bmb, i, 0))) -+ cpu_relax(); -+ return i; -+ -+dma_map_failed: -+ kfree_skb(skb); -+ -+build_skb_failed: -+netdev_alloc_failed: -+ net_err_ratelimited("dpa_bp_add_8_bufs() failed\n"); -+ WARN_ONCE(1, "Memory allocation failure on Rx\n"); -+ -+ bm_buffer_set64(&bmb[i], 0); -+ /* Avoid releasing a completely null buffer; bman_release() requires -+ * at least one buffer. -+ */ -+ if (likely(i)) -+ goto release_bufs; -+ -+ return 0; -+} -+ -+/* Cold path wrapper over _dpa_bp_add_8_bufs(). */ -+static void dpa_bp_add_8_bufs(const struct dpa_bp *dpa_bp, int cpu) -+{ -+ int *count_ptr = per_cpu_ptr(dpa_bp->percpu_count, cpu); -+ *count_ptr += _dpa_bp_add_8_bufs(dpa_bp); -+} -+ -+int dpa_bp_priv_seed(struct dpa_bp *dpa_bp) -+{ -+ int i; -+ -+ /* Give each CPU an allotment of "config_count" buffers */ -+ for_each_possible_cpu(i) { -+ int j; -+ -+ /* Although we access another CPU's counters here -+ * we do it at boot time so it is safe -+ */ -+ for (j = 0; j < dpa_bp->config_count; j += 8) -+ dpa_bp_add_8_bufs(dpa_bp, i); -+ } -+ return 0; -+} -+EXPORT_SYMBOL(dpa_bp_priv_seed); -+ -+/* Add buffers/(pages) for Rx processing whenever bpool count falls below -+ * REFILL_THRESHOLD. -+ */ -+int dpaa_eth_refill_bpools(struct dpa_bp *dpa_bp, int *countptr) -+{ -+ int count = *countptr; -+ int new_bufs; -+ -+ if (unlikely(count < CONFIG_FSL_DPAA_ETH_REFILL_THRESHOLD)) { -+ do { -+ new_bufs = _dpa_bp_add_8_bufs(dpa_bp); -+ if (unlikely(!new_bufs)) { -+ /* Avoid looping forever if we've temporarily -+ * run out of memory. We'll try again at the -+ * next NAPI cycle. -+ */ -+ break; -+ } -+ count += new_bufs; -+ } while (count < CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT); -+ -+ *countptr = count; -+ if (unlikely(count < CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT)) -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpaa_eth_refill_bpools); -+ -+/* Cleanup function for outgoing frame descriptors that were built on Tx path, -+ * either contiguous frames or scatter/gather ones. -+ * Skb freeing is not handled here. -+ * -+ * This function may be called on error paths in the Tx function, so guard -+ * against cases when not all fd relevant fields were filled in. -+ * -+ * Return the skb backpointer, since for S/G frames the buffer containing it -+ * gets freed here. -+ */ -+struct sk_buff *_dpa_cleanup_tx_fd(const struct dpa_priv_s *priv, -+ const struct qm_fd *fd) -+{ -+ const struct qm_sg_entry *sgt; -+ int i; -+ struct dpa_bp *dpa_bp = priv->dpa_bp; -+ dma_addr_t addr = qm_fd_addr(fd); -+ dma_addr_t sg_addr; -+ struct sk_buff **skbh; -+ struct sk_buff *skb = NULL; -+ const enum dma_data_direction dma_dir = DMA_TO_DEVICE; -+ int nr_frags; -+ int sg_len; -+ -+ /* retrieve skb back pointer */ -+ DPA_READ_SKB_PTR(skb, skbh, phys_to_virt(addr), 0); -+ -+ if (unlikely(fd->format == qm_fd_sg)) { -+ nr_frags = skb_shinfo(skb)->nr_frags; -+#ifdef DPAA_LS1043A_DMA_4K_ISSUE -+/* addressing the 4k DMA issue can yield a larger number of fragments than -+ * the skb had -+ */ -+ dma_unmap_single(dpa_bp->dev, addr, dpa_fd_offset(fd) + -+ sizeof(struct qm_sg_entry) * DPA_SGT_MAX_ENTRIES, -+ dma_dir); -+#else -+ dma_unmap_single(dpa_bp->dev, addr, dpa_fd_offset(fd) + -+ sizeof(struct qm_sg_entry) * (1 + nr_frags), -+ dma_dir); -+#endif -+ /* The sgt buffer has been allocated with netdev_alloc_frag(), -+ * it's from lowmem. -+ */ -+ sgt = phys_to_virt(addr + dpa_fd_offset(fd)); -+#ifdef CONFIG_FSL_DPAA_1588 -+ if (priv->tsu && priv->tsu->valid && -+ priv->tsu->hwts_tx_en_ioctl) -+ dpa_ptp_store_txstamp(priv, skb, (void *)skbh); -+#endif -+#ifdef CONFIG_FSL_DPAA_TS -+ if (unlikely(priv->ts_tx_en && -+ skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { -+ struct skb_shared_hwtstamps shhwtstamps; -+ -+ dpa_get_ts(priv, TX, &shhwtstamps, (void *)skbh); -+ skb_tstamp_tx(skb, &shhwtstamps); -+ } -+#endif /* CONFIG_FSL_DPAA_TS */ -+ -+ /* sgt[0] is from lowmem, was dma_map_single()-ed */ -+ sg_addr = qm_sg_addr(&sgt[0]); -+ sg_len = qm_sg_entry_get_len(&sgt[0]); -+ dma_unmap_single(dpa_bp->dev, sg_addr, sg_len, dma_dir); -+#ifdef DPAA_LS1043A_DMA_4K_ISSUE -+ i = 1; -+ do { -+ DPA_BUG_ON(qm_sg_entry_get_ext(&sgt[i])); -+ sg_addr = qm_sg_addr(&sgt[i]); -+ sg_len = qm_sg_entry_get_len(&sgt[i]); -+ dma_unmap_page(dpa_bp->dev, sg_addr, sg_len, dma_dir); -+ } while (!qm_sg_entry_get_final(&sgt[i++])); -+#else -+ /* remaining pages were mapped with dma_map_page() */ -+ for (i = 1; i <= nr_frags; i++) { -+ DPA_BUG_ON(qm_sg_entry_get_ext(&sgt[i])); -+ sg_addr = qm_sg_addr(&sgt[i]); -+ sg_len = qm_sg_entry_get_len(&sgt[i]); -+ dma_unmap_page(dpa_bp->dev, sg_addr, sg_len, dma_dir); -+ } -+#endif -+ -+ /* Free the page frag that we allocated on Tx */ -+ put_page(virt_to_head_page(sgt)); -+ } else { -+ dma_unmap_single(dpa_bp->dev, addr, -+ skb_tail_pointer(skb) - (u8 *)skbh, dma_dir); -+#ifdef CONFIG_FSL_DPAA_TS -+ /* get the timestamp for non-SG frames */ -+#ifdef CONFIG_FSL_DPAA_1588 -+ if (priv->tsu && priv->tsu->valid && -+ priv->tsu->hwts_tx_en_ioctl) -+ dpa_ptp_store_txstamp(priv, skb, (void *)skbh); -+#endif -+ if (unlikely(priv->ts_tx_en && -+ skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { -+ struct skb_shared_hwtstamps shhwtstamps; -+ -+ dpa_get_ts(priv, TX, &shhwtstamps, (void *)skbh); -+ skb_tstamp_tx(skb, &shhwtstamps); -+ } -+#endif -+ } -+ -+ return skb; -+} -+EXPORT_SYMBOL(_dpa_cleanup_tx_fd); -+ -+#ifndef CONFIG_FSL_DPAA_TS -+bool dpa_skb_is_recyclable(struct sk_buff *skb) -+{ -+ /* No recycling possible if skb buffer is kmalloc'ed */ -+ if (skb->head_frag == 0) -+ return false; -+ -+ /* or if it's an userspace buffer */ -+ if (skb_shinfo(skb)->tx_flags & SKBTX_DEV_ZEROCOPY) -+ return false; -+ -+ /* or if it's cloned or shared */ -+ if (skb_shared(skb) || skb_cloned(skb) || -+ skb->fclone != SKB_FCLONE_UNAVAILABLE) -+ return false; -+ -+ return true; -+} -+EXPORT_SYMBOL(dpa_skb_is_recyclable); -+ -+bool dpa_buf_is_recyclable(struct sk_buff *skb, -+ uint32_t min_size, -+ uint16_t min_offset, -+ unsigned char **new_buf_start) -+{ -+ unsigned char *new; -+ -+ /* In order to recycle a buffer, the following conditions must be met: -+ * - buffer size no less than the buffer pool size -+ * - buffer size no higher than an upper limit (to avoid moving too much -+ * system memory to the buffer pools) -+ * - buffer address aligned to cacheline bytes -+ * - offset of data from start of buffer no lower than a minimum value -+ * - offset of data from start of buffer no higher than a maximum value -+ */ -+ new = min(skb_end_pointer(skb) - min_size, skb->data - min_offset); -+ -+ /* left align to the nearest cacheline */ -+ new = (unsigned char *)((unsigned long)new & ~(SMP_CACHE_BYTES - 1)); -+ -+ if (likely(new >= skb->head && -+ new >= (skb->data - DPA_MAX_FD_OFFSET) && -+ skb_end_pointer(skb) - new <= DPA_RECYCLE_MAX_SIZE)) { -+ *new_buf_start = new; -+ return true; -+ } -+ -+ return false; -+} -+EXPORT_SYMBOL(dpa_buf_is_recyclable); -+#endif -+ -+/* Build a linear skb around the received buffer. -+ * We are guaranteed there is enough room at the end of the data buffer to -+ * accommodate the shared info area of the skb. -+ */ -+static struct sk_buff *__hot contig_fd_to_skb(const struct dpa_priv_s *priv, -+ const struct qm_fd *fd, int *use_gro) -+{ -+ dma_addr_t addr = qm_fd_addr(fd); -+ ssize_t fd_off = dpa_fd_offset(fd); -+ void *vaddr; -+ const fm_prs_result_t *parse_results; -+ struct sk_buff *skb = NULL, **skbh; -+ -+ vaddr = phys_to_virt(addr); -+ DPA_BUG_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES)); -+ -+ /* Retrieve the skb and adjust data and tail pointers, to make sure -+ * forwarded skbs will have enough space on Tx if extra headers -+ * are added. -+ */ -+ DPA_READ_SKB_PTR(skb, skbh, vaddr, -1); -+ -+#ifdef CONFIG_FSL_DPAA_ETH_JUMBO_FRAME -+ /* When using jumbo Rx buffers, we risk having frames dropped due to -+ * the socket backlog reaching its maximum allowed size. -+ * Use the frame length for the skb truesize instead of the buffer -+ * size, as this is the size of the data that actually gets copied to -+ * userspace. -+ */ -+ skb->truesize = SKB_TRUESIZE(dpa_fd_length(fd)); -+#endif -+ -+ DPA_BUG_ON(fd_off != priv->rx_headroom); -+ skb_reserve(skb, fd_off); -+ skb_put(skb, dpa_fd_length(fd)); -+ -+ /* Peek at the parse results for csum validation */ -+ parse_results = (const fm_prs_result_t *)(vaddr + -+ DPA_RX_PRIV_DATA_SIZE); -+ _dpa_process_parse_results(parse_results, fd, skb, use_gro); -+ -+#ifdef CONFIG_FSL_DPAA_1588 -+ if (priv->tsu && priv->tsu->valid && priv->tsu->hwts_rx_en_ioctl) -+ dpa_ptp_store_rxstamp(priv, skb, vaddr); -+#endif -+#ifdef CONFIG_FSL_DPAA_TS -+ if (priv->ts_rx_en) -+ dpa_get_ts(priv, RX, skb_hwtstamps(skb), vaddr); -+#endif /* CONFIG_FSL_DPAA_TS */ -+ -+ return skb; -+} -+ -+ -+/* Build an skb with the data of the first S/G entry in the linear portion and -+ * the rest of the frame as skb fragments. -+ * -+ * The page fragment holding the S/G Table is recycled here. -+ */ -+static struct sk_buff *__hot sg_fd_to_skb(const struct dpa_priv_s *priv, -+ const struct qm_fd *fd, int *use_gro, -+ int *count_ptr) -+{ -+ const struct qm_sg_entry *sgt; -+ dma_addr_t addr = qm_fd_addr(fd); -+ ssize_t fd_off = dpa_fd_offset(fd); -+ dma_addr_t sg_addr; -+ void *vaddr, *sg_vaddr; -+ struct dpa_bp *dpa_bp; -+ struct page *page, *head_page; -+ int frag_offset, frag_len; -+ int page_offset; -+ int i; -+ const fm_prs_result_t *parse_results; -+ struct sk_buff *skb = NULL, *skb_tmp, **skbh; -+ -+ vaddr = phys_to_virt(addr); -+ DPA_BUG_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES)); -+ -+ dpa_bp = priv->dpa_bp; -+ /* Iterate through the SGT entries and add data buffers to the skb */ -+ sgt = vaddr + fd_off; -+ for (i = 0; i < DPA_SGT_MAX_ENTRIES; i++) { -+ /* Extension bit is not supported */ -+ DPA_BUG_ON(qm_sg_entry_get_ext(&sgt[i])); -+ -+ /* We use a single global Rx pool */ -+ DPA_BUG_ON(dpa_bp != -+ dpa_bpid2pool(qm_sg_entry_get_bpid(&sgt[i]))); -+ -+ sg_addr = qm_sg_addr(&sgt[i]); -+ sg_vaddr = phys_to_virt(sg_addr); -+ DPA_BUG_ON(!IS_ALIGNED((unsigned long)sg_vaddr, -+ SMP_CACHE_BYTES)); -+ -+ dma_unmap_single(dpa_bp->dev, sg_addr, dpa_bp->size, -+ DMA_BIDIRECTIONAL); -+ if (i == 0) { -+ DPA_READ_SKB_PTR(skb, skbh, sg_vaddr, -1); -+ DPA_BUG_ON(skb->head != sg_vaddr); -+#ifdef CONFIG_FSL_DPAA_1588 -+ if (priv->tsu && priv->tsu->valid && -+ priv->tsu->hwts_rx_en_ioctl) -+ dpa_ptp_store_rxstamp(priv, skb, vaddr); -+#endif -+#ifdef CONFIG_FSL_DPAA_TS -+ if (priv->ts_rx_en) -+ dpa_get_ts(priv, RX, skb_hwtstamps(skb), vaddr); -+#endif /* CONFIG_FSL_DPAA_TS */ -+ -+ /* In the case of a SG frame, FMan stores the Internal -+ * Context in the buffer containing the sgt. -+ * Inspect the parse results before anything else. -+ */ -+ parse_results = (const fm_prs_result_t *)(vaddr + -+ DPA_RX_PRIV_DATA_SIZE); -+ _dpa_process_parse_results(parse_results, fd, skb, -+ use_gro); -+ -+ /* Make sure forwarded skbs will have enough space -+ * on Tx, if extra headers are added. -+ */ -+ DPA_BUG_ON(fd_off != priv->rx_headroom); -+ skb_reserve(skb, fd_off); -+ skb_put(skb, qm_sg_entry_get_len(&sgt[i])); -+ } else { -+ /* Not the first S/G entry; all data from buffer will -+ * be added in an skb fragment; fragment index is offset -+ * by one since first S/G entry was incorporated in the -+ * linear part of the skb. -+ * -+ * Caution: 'page' may be a tail page. -+ */ -+ DPA_READ_SKB_PTR(skb_tmp, skbh, sg_vaddr, -1); -+ page = virt_to_page(sg_vaddr); -+ head_page = virt_to_head_page(sg_vaddr); -+ -+ /* Free (only) the skbuff shell because its data buffer -+ * is already a frag in the main skb. -+ */ -+ get_page(head_page); -+ dev_kfree_skb(skb_tmp); -+ -+ /* Compute offset in (possibly tail) page */ -+ page_offset = ((unsigned long)sg_vaddr & -+ (PAGE_SIZE - 1)) + -+ (page_address(page) - page_address(head_page)); -+ /* page_offset only refers to the beginning of sgt[i]; -+ * but the buffer itself may have an internal offset. -+ */ -+ frag_offset = qm_sg_entry_get_offset(&sgt[i]) + -+ page_offset; -+ frag_len = qm_sg_entry_get_len(&sgt[i]); -+ /* skb_add_rx_frag() does no checking on the page; if -+ * we pass it a tail page, we'll end up with -+ * bad page accounting and eventually with segafults. -+ */ -+ skb_add_rx_frag(skb, i - 1, head_page, frag_offset, -+ frag_len, dpa_bp->size); -+ } -+ /* Update the pool count for the current {cpu x bpool} */ -+ (*count_ptr)--; -+ -+ if (qm_sg_entry_get_final(&sgt[i])) -+ break; -+ } -+ WARN_ONCE(i == DPA_SGT_MAX_ENTRIES, "No final bit on SGT\n"); -+ -+ /* recycle the SGT fragment */ -+ DPA_BUG_ON(dpa_bp != dpa_bpid2pool(fd->bpid)); -+ dpa_bp_recycle_frag(dpa_bp, (unsigned long)vaddr, count_ptr); -+ return skb; -+} -+ -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+static inline int dpa_skb_loop(const struct dpa_priv_s *priv, -+ struct sk_buff *skb) -+{ -+ if (unlikely(priv->loop_to < 0)) -+ return 0; /* loop disabled by default */ -+ -+ skb_push(skb, ETH_HLEN); /* compensate for eth_type_trans */ -+ dpa_tx(skb, dpa_loop_netdevs[priv->loop_to]); -+ -+ return 1; /* Frame Tx on the selected interface */ -+} -+#endif -+ -+void __hot _dpa_rx(struct net_device *net_dev, -+ struct qman_portal *portal, -+ const struct dpa_priv_s *priv, -+ struct dpa_percpu_priv_s *percpu_priv, -+ const struct qm_fd *fd, -+ u32 fqid, -+ int *count_ptr) -+{ -+ struct dpa_bp *dpa_bp; -+ struct sk_buff *skb; -+ dma_addr_t addr = qm_fd_addr(fd); -+ u32 fd_status = fd->status; -+ unsigned int skb_len; -+ struct rtnl_link_stats64 *percpu_stats = &percpu_priv->stats; -+ int use_gro = net_dev->features & NETIF_F_GRO; -+ -+ if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) { -+ if (netif_msg_hw(priv) && net_ratelimit()) -+ netdev_warn(net_dev, "FD status = 0x%08x\n", -+ fd_status & FM_FD_STAT_RX_ERRORS); -+ -+ percpu_stats->rx_errors++; -+ goto _release_frame; -+ } -+ -+ dpa_bp = priv->dpa_bp; -+ DPA_BUG_ON(dpa_bp != dpa_bpid2pool(fd->bpid)); -+ -+ /* prefetch the first 64 bytes of the frame or the SGT start */ -+ dma_unmap_single(dpa_bp->dev, addr, dpa_bp->size, DMA_BIDIRECTIONAL); -+ prefetch(phys_to_virt(addr) + dpa_fd_offset(fd)); -+ -+ /* The only FD types that we may receive are contig and S/G */ -+ DPA_BUG_ON((fd->format != qm_fd_contig) && (fd->format != qm_fd_sg)); -+ -+ if (likely(fd->format == qm_fd_contig)) { -+#ifdef CONFIG_FSL_DPAA_HOOKS -+ /* Execute the Rx processing hook, if it exists. */ -+ if (dpaa_eth_hooks.rx_default && -+ dpaa_eth_hooks.rx_default((void *)fd, net_dev, -+ fqid) == DPAA_ETH_STOLEN) { -+ /* won't count the rx bytes in */ -+ return; -+ } -+#endif -+ skb = contig_fd_to_skb(priv, fd, &use_gro); -+ } else { -+ skb = sg_fd_to_skb(priv, fd, &use_gro, count_ptr); -+ percpu_priv->rx_sg++; -+ } -+ -+ /* Account for either the contig buffer or the SGT buffer (depending on -+ * which case we were in) having been removed from the pool. -+ */ -+ (*count_ptr)--; -+ skb->protocol = eth_type_trans(skb, net_dev); -+ -+ /* IP Reassembled frames are allowed to be larger than MTU */ -+ if (unlikely(dpa_check_rx_mtu(skb, net_dev->mtu) && -+ !(fd_status & FM_FD_IPR))) { -+ percpu_stats->rx_dropped++; -+ goto drop_bad_frame; -+ } -+ -+ skb_len = skb->len; -+ -+#ifdef CONFIG_FSL_DPAA_DBG_LOOP -+ if (dpa_skb_loop(priv, skb)) { -+ percpu_stats->rx_packets++; -+ percpu_stats->rx_bytes += skb_len; -+ return; -+ } -+#endif -+ -+ if (use_gro) { -+ gro_result_t gro_result; -+ const struct qman_portal_config *pc = -+ qman_p_get_portal_config(portal); -+ struct dpa_napi_portal *np = &percpu_priv->np[pc->index]; -+ -+ np->p = portal; -+ gro_result = napi_gro_receive(&np->napi, skb); -+ /* If frame is dropped by the stack, rx_dropped counter is -+ * incremented automatically, so no need for us to update it -+ */ -+ if (unlikely(gro_result == GRO_DROP)) -+ goto packet_dropped; -+ } else if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) -+ goto packet_dropped; -+ -+ percpu_stats->rx_packets++; -+ percpu_stats->rx_bytes += skb_len; -+ -+packet_dropped: -+ return; -+ -+drop_bad_frame: -+ dev_kfree_skb(skb); -+ return; -+ -+_release_frame: -+ dpa_fd_release(net_dev, fd); -+} -+ -+int __hot skb_to_contig_fd(struct dpa_priv_s *priv, -+ struct sk_buff *skb, struct qm_fd *fd, -+ int *count_ptr, int *offset) -+{ -+ struct sk_buff **skbh; -+ dma_addr_t addr; -+ struct dpa_bp *dpa_bp = priv->dpa_bp; -+ struct net_device *net_dev = priv->net_dev; -+ int err; -+ enum dma_data_direction dma_dir; -+ unsigned char *buffer_start; -+ -+#ifndef CONFIG_FSL_DPAA_TS -+ /* Check recycling conditions; only if timestamp support is not -+ * enabled, otherwise we need the fd back on tx confirmation -+ */ -+ -+ /* We can recycle the buffer if: -+ * - the pool is not full -+ * - the buffer meets the skb recycling conditions -+ * - the buffer meets our own (size, offset, align) conditions -+ */ -+ if (likely((*count_ptr < dpa_bp->target_count) && -+ dpa_skb_is_recyclable(skb) && -+ dpa_buf_is_recyclable(skb, dpa_bp->size, -+ priv->tx_headroom, &buffer_start))) { -+ /* Buffer is recyclable; use the new start address -+ * and set fd parameters and DMA mapping direction -+ */ -+ fd->bpid = dpa_bp->bpid; -+ DPA_BUG_ON(skb->data - buffer_start > DPA_MAX_FD_OFFSET); -+ fd->offset = (uint16_t)(skb->data - buffer_start); -+ dma_dir = DMA_BIDIRECTIONAL; -+ -+ DPA_WRITE_SKB_PTR(skb, skbh, buffer_start, -1); -+ *offset = skb_headroom(skb) - fd->offset; -+ } else -+#endif -+ { -+ /* Not recyclable. -+ * We are guaranteed to have at least tx_headroom bytes -+ * available, so just use that for offset. -+ */ -+ fd->bpid = 0xff; -+ buffer_start = skb->data - priv->tx_headroom; -+ fd->offset = priv->tx_headroom; -+ dma_dir = DMA_TO_DEVICE; -+ -+ /* The buffer will be Tx-confirmed, but the TxConf cb must -+ * necessarily look at our Tx private data to retrieve the -+ * skbuff. (In short: can't use DPA_WRITE_SKB_PTR() here.) -+ */ -+ DPA_WRITE_SKB_PTR(skb, skbh, buffer_start, 0); -+ } -+ -+ /* Enable L3/L4 hardware checksum computation. -+ * -+ * We must do this before dma_map_single(DMA_TO_DEVICE), because we may -+ * need to write into the skb. -+ */ -+ err = dpa_enable_tx_csum(priv, skb, fd, -+ ((char *)skbh) + DPA_TX_PRIV_DATA_SIZE); -+ if (unlikely(err < 0)) { -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_err(net_dev, "HW csum error: %d\n", err); -+ return err; -+ } -+ -+ /* Fill in the rest of the FD fields */ -+ fd->format = qm_fd_contig; -+ fd->length20 = skb->len; -+ fd->cmd |= FM_FD_CMD_FCO; -+ -+ /* Map the entire buffer size that may be seen by FMan, but no more */ -+ addr = dma_map_single(dpa_bp->dev, skbh, -+ skb_tail_pointer(skb) - buffer_start, dma_dir); -+ if (unlikely(dma_mapping_error(dpa_bp->dev, addr))) { -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_err(net_dev, "dma_map_single() failed\n"); -+ return -EINVAL; -+ } -+ fd->addr = addr; -+ -+ -+ return 0; -+} -+EXPORT_SYMBOL(skb_to_contig_fd); -+ -+int __hot skb_to_sg_fd(struct dpa_priv_s *priv, -+ struct sk_buff *skb, struct qm_fd *fd) -+{ -+ struct dpa_bp *dpa_bp = priv->dpa_bp; -+ dma_addr_t addr; -+ dma_addr_t sg_addr; -+ struct sk_buff **skbh; -+ struct net_device *net_dev = priv->net_dev; -+ int sg_len; -+ int err; -+#ifdef DPAA_LS1043A_DMA_4K_ISSUE -+ unsigned long boundary; -+ int k; -+#endif -+ -+ struct qm_sg_entry *sgt; -+ void *sgt_buf; -+ void *buffer_start; -+ skb_frag_t *frag; -+ int i, j; -+ const enum dma_data_direction dma_dir = DMA_TO_DEVICE; -+ const int nr_frags = skb_shinfo(skb)->nr_frags; -+ -+ fd->format = qm_fd_sg; -+#ifdef DPAA_LS1043A_DMA_4K_ISSUE -+ /* get a page frag to store the SGTable */ -+ sgt_buf = netdev_alloc_frag(priv->tx_headroom + -+ sizeof(struct qm_sg_entry) * DPA_SGT_MAX_ENTRIES); -+ if (unlikely(!sgt_buf)) { -+ dev_err(dpa_bp->dev, "netdev_alloc_frag() failed\n"); -+ return -ENOMEM; -+ } -+ -+ /* it seems that the memory allocator does not zero the allocated mem */ -+ memset(sgt_buf, 0, priv->tx_headroom + -+ sizeof(struct qm_sg_entry) * DPA_SGT_MAX_ENTRIES); -+#else -+ /* get a page frag to store the SGTable */ -+ sgt_buf = netdev_alloc_frag(priv->tx_headroom + -+ sizeof(struct qm_sg_entry) * (1 + nr_frags)); -+ if (unlikely(!sgt_buf)) { -+ dev_err(dpa_bp->dev, "netdev_alloc_frag() failed\n"); -+ return -ENOMEM; -+ } -+ -+ memset(sgt_buf, 0, priv->tx_headroom + -+ sizeof(struct qm_sg_entry) * (1 + nr_frags)); -+#endif -+ -+ /* Enable L3/L4 hardware checksum computation. -+ * -+ * We must do this before dma_map_single(DMA_TO_DEVICE), because we may -+ * need to write into the skb. -+ */ -+ err = dpa_enable_tx_csum(priv, skb, fd, -+ sgt_buf + DPA_TX_PRIV_DATA_SIZE); -+ if (unlikely(err < 0)) { -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_err(net_dev, "HW csum error: %d\n", err); -+ goto csum_failed; -+ } -+ -+ sgt = (struct qm_sg_entry *)(sgt_buf + priv->tx_headroom); -+ sg_len = skb_headlen(skb); -+ qm_sg_entry_set_bpid(&sgt[0], 0xff); -+ qm_sg_entry_set_offset(&sgt[0], 0); -+ qm_sg_entry_set_len(&sgt[0], sg_len); -+ qm_sg_entry_set_ext(&sgt[0], 0); -+ qm_sg_entry_set_final(&sgt[0], 0); -+ -+ addr = dma_map_single(dpa_bp->dev, skb->data, sg_len, dma_dir); -+ if (unlikely(dma_mapping_error(dpa_bp->dev, addr))) { -+ dev_err(dpa_bp->dev, "DMA mapping failed"); -+ err = -EINVAL; -+ goto sg0_map_failed; -+ -+ } -+ -+ qm_sg_entry_set64(&sgt[0], addr); -+ -+#ifdef DPAA_LS1043A_DMA_4K_ISSUE -+ j = 0; -+ if (unlikely(HAS_DMA_ISSUE(skb->data, sg_len))) { -+ boundary = BOUNDARY_4K(skb->data, sg_len); -+ qm_sg_entry_set_len(&sgt[j], boundary - -+ (unsigned long)skb->data); -+ -+ j++; -+ qm_sg_entry_set_bpid(&sgt[j], 0xff); -+ qm_sg_entry_set_offset(&sgt[j], 0); -+ qm_sg_entry_set_len(&sgt[j], -+ ((unsigned long)skb->data + (unsigned long)sg_len) - -+ boundary); -+ qm_sg_entry_set_ext(&sgt[j], 0); -+ qm_sg_entry_set_final(&sgt[j], 0); -+ -+ /* keep the offset in the address */ -+ qm_sg_entry_set64(&sgt[j], addr + -+ (boundary - -+ (unsigned long)skb->data)); -+ } -+ j++; -+ -+ /* populate the rest of SGT entries */ -+ for (i = 1; i <= nr_frags; i++, j++) { -+ frag = &skb_shinfo(skb)->frags[i - 1]; -+ qm_sg_entry_set_bpid(&sgt[j], 0xff); -+ qm_sg_entry_set_offset(&sgt[j], 0); -+ qm_sg_entry_set_len(&sgt[j], frag->size); -+ qm_sg_entry_set_ext(&sgt[j], 0); -+ -+ DPA_BUG_ON(!skb_frag_page(frag)); -+ addr = skb_frag_dma_map(dpa_bp->dev, frag, 0, frag->size, -+ dma_dir); -+ if (unlikely(dma_mapping_error(dpa_bp->dev, addr))) { -+ dev_err(dpa_bp->dev, "DMA mapping failed"); -+ err = -EINVAL; -+ goto sg_map_failed; -+ } -+ -+ /* keep the offset in the address */ -+ qm_sg_entry_set64(&sgt[j], addr); -+ -+ if (unlikely(HAS_DMA_ISSUE(frag, frag->size))) { -+ boundary = BOUNDARY_4K(frag, frag->size); -+ qm_sg_entry_set_len(&sgt[j], boundary - -+ (unsigned long)frag); -+ -+ j++; -+ qm_sg_entry_set_bpid(&sgt[j], 0xff); -+ qm_sg_entry_set_offset(&sgt[j], 0); -+ qm_sg_entry_set_len(&sgt[j], -+ ((unsigned long)frag->size - -+ (boundary - (unsigned long)frag))); -+ qm_sg_entry_set_ext(&sgt[j], 0); -+ -+ /* keep the offset in the address */ -+ qm_sg_entry_set64(&sgt[j], addr + -+ (boundary - (unsigned long)frag)); -+ } -+ -+ if (i == nr_frags) -+ qm_sg_entry_set_final(&sgt[j], 1); -+ else -+ qm_sg_entry_set_final(&sgt[j], 0); -+#else -+ -+ /* populate the rest of SGT entries */ -+ for (i = 1; i <= nr_frags; i++) { -+ frag = &skb_shinfo(skb)->frags[i - 1]; -+ qm_sg_entry_set_bpid(&sgt[i], 0xff); -+ qm_sg_entry_set_offset(&sgt[i], 0); -+ qm_sg_entry_set_len(&sgt[i], frag->size); -+ qm_sg_entry_set_ext(&sgt[i], 0); -+ -+ if (i == nr_frags) -+ qm_sg_entry_set_final(&sgt[i], 1); -+ else -+ qm_sg_entry_set_final(&sgt[i], 0); -+ -+ DPA_BUG_ON(!skb_frag_page(frag)); -+ addr = skb_frag_dma_map(dpa_bp->dev, frag, 0, frag->size, -+ dma_dir); -+ if (unlikely(dma_mapping_error(dpa_bp->dev, addr))) { -+ dev_err(dpa_bp->dev, "DMA mapping failed"); -+ err = -EINVAL; -+ goto sg_map_failed; -+ } -+ -+ /* keep the offset in the address */ -+ qm_sg_entry_set64(&sgt[i], addr); -+#endif -+ } -+ -+ fd->length20 = skb->len; -+ fd->offset = priv->tx_headroom; -+ -+ /* DMA map the SGT page */ -+ buffer_start = (void *)sgt - priv->tx_headroom; -+ DPA_WRITE_SKB_PTR(skb, skbh, buffer_start, 0); -+#ifdef DPAA_LS1043A_DMA_4K_ISSUE -+ addr = dma_map_single(dpa_bp->dev, buffer_start, priv->tx_headroom + -+ sizeof(struct qm_sg_entry) * DPA_SGT_MAX_ENTRIES, -+ dma_dir); -+#else -+ addr = dma_map_single(dpa_bp->dev, buffer_start, priv->tx_headroom + -+ sizeof(struct qm_sg_entry) * (1 + nr_frags), -+ dma_dir); -+#endif -+ if (unlikely(dma_mapping_error(dpa_bp->dev, addr))) { -+ dev_err(dpa_bp->dev, "DMA mapping failed"); -+ err = -EINVAL; -+ goto sgt_map_failed; -+ } -+ -+ fd->bpid = 0xff; -+ fd->cmd |= FM_FD_CMD_FCO; -+ fd->addr = addr; -+ -+ return 0; -+ -+sgt_map_failed: -+sg_map_failed: -+#ifdef DPAA_LS1043A_DMA_4K_ISSUE -+ for (k = 0; k < j; k++) { -+ sg_addr = qm_sg_addr(&sgt[k]); -+ dma_unmap_page(dpa_bp->dev, sg_addr, -+ qm_sg_entry_get_len(&sgt[k]), dma_dir); -+ } -+#else -+ for (j = 0; j < i; j++) { -+ sg_addr = qm_sg_addr(&sgt[j]); -+ dma_unmap_page(dpa_bp->dev, sg_addr, -+ qm_sg_entry_get_len(&sgt[j]), dma_dir); -+ } -+#endif -+sg0_map_failed: -+csum_failed: -+ put_page(virt_to_head_page(sgt_buf)); -+ -+ return err; -+} -+EXPORT_SYMBOL(skb_to_sg_fd); -+ -+int __hot dpa_tx(struct sk_buff *skb, struct net_device *net_dev) -+{ -+ struct dpa_priv_s *priv; -+ const int queue_mapping = dpa_get_queue_mapping(skb); -+ struct qman_fq *egress_fq, *conf_fq; -+ -+#ifdef CONFIG_FSL_DPAA_HOOKS -+ /* If there is a Tx hook, run it. */ -+ if (dpaa_eth_hooks.tx && -+ dpaa_eth_hooks.tx(skb, net_dev) == DPAA_ETH_STOLEN) -+ /* won't update any Tx stats */ -+ return NETDEV_TX_OK; -+#endif -+ -+ priv = netdev_priv(net_dev); -+ -+#ifdef CONFIG_FSL_DPAA_CEETM -+ if (priv->ceetm_en) -+ return ceetm_tx(skb, net_dev); -+#endif -+ -+ egress_fq = priv->egress_fqs[queue_mapping]; -+ conf_fq = priv->conf_fqs[queue_mapping]; -+ -+ return dpa_tx_extended(skb, net_dev, egress_fq, conf_fq); -+} -+ -+int __hot dpa_tx_extended(struct sk_buff *skb, struct net_device *net_dev, -+ struct qman_fq *egress_fq, struct qman_fq *conf_fq) -+{ -+ struct dpa_priv_s *priv; -+ struct qm_fd fd; -+ struct dpa_percpu_priv_s *percpu_priv; -+ struct rtnl_link_stats64 *percpu_stats; -+ int err = 0; -+ const bool nonlinear = skb_is_nonlinear(skb); -+ int *countptr, offset = 0; -+ -+ priv = netdev_priv(net_dev); -+ /* Non-migratable context, safe to use raw_cpu_ptr */ -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ percpu_stats = &percpu_priv->stats; -+ countptr = raw_cpu_ptr(priv->dpa_bp->percpu_count); -+ -+ clear_fd(&fd); -+ -+#ifdef CONFIG_FSL_DPAA_1588 -+ if (priv->tsu && priv->tsu->valid && priv->tsu->hwts_tx_en_ioctl) -+ fd.cmd |= FM_FD_CMD_UPD; -+#endif -+#ifdef CONFIG_FSL_DPAA_TS -+ if (unlikely(priv->ts_tx_en && -+ skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) -+ fd.cmd |= FM_FD_CMD_UPD; -+ skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; -+#endif /* CONFIG_FSL_DPAA_TS */ -+ -+ /* MAX_SKB_FRAGS is larger than our DPA_SGT_MAX_ENTRIES; make sure -+ * we don't feed FMan with more fragments than it supports. -+ * Btw, we're using the first sgt entry to store the linear part of -+ * the skb, so we're one extra frag short. -+ */ -+ if (nonlinear && -+ likely(skb_shinfo(skb)->nr_frags < DPA_SGT_ENTRIES_THRESHOLD)) { -+ /* Just create a S/G fd based on the skb */ -+ err = skb_to_sg_fd(priv, skb, &fd); -+ percpu_priv->tx_frag_skbuffs++; -+ } else { -+ /* Make sure we have enough headroom to accommodate private -+ * data, parse results, etc. Normally this shouldn't happen if -+ * we're here via the standard kernel stack. -+ */ -+ if (unlikely(skb_headroom(skb) < priv->tx_headroom)) { -+ struct sk_buff *skb_new; -+ -+ skb_new = skb_realloc_headroom(skb, priv->tx_headroom); -+ if (unlikely(!skb_new)) { -+ dev_kfree_skb(skb); -+ percpu_stats->tx_errors++; -+ return NETDEV_TX_OK; -+ } -+ dev_kfree_skb(skb); -+ skb = skb_new; -+ } -+ -+ /* We're going to store the skb backpointer at the beginning -+ * of the data buffer, so we need a privately owned skb -+ */ -+ -+ /* Code borrowed from skb_unshare(). */ -+ if (skb_cloned(skb)) { -+ struct sk_buff *nskb = skb_copy(skb, GFP_ATOMIC); -+ kfree_skb(skb); -+ skb = nskb; -+ /* skb_copy() has now linearized the skbuff. */ -+ } else if (unlikely(nonlinear)) { -+ /* We are here because the egress skb contains -+ * more fragments than we support. In this case, -+ * we have no choice but to linearize it ourselves. -+ */ -+ err = __skb_linearize(skb); -+ } -+ if (unlikely(!skb || err < 0)) -+ /* Common out-of-memory error path */ -+ goto enomem; -+ -+#ifdef DPAA_LS1043A_DMA_4K_ISSUE -+ if (unlikely(HAS_DMA_ISSUE(skb->data, skb->len))) { -+ err = skb_to_sg_fd(priv, skb, &fd); -+ percpu_priv->tx_frag_skbuffs++; -+ } else { -+ err = skb_to_contig_fd(priv, skb, &fd, countptr, &offset); -+ } -+#else -+ /* Finally, create a contig FD from this skb */ -+ err = skb_to_contig_fd(priv, skb, &fd, countptr, &offset); -+#endif -+ } -+ if (unlikely(err < 0)) -+ goto skb_to_fd_failed; -+ -+ if (fd.bpid != 0xff) { -+ skb_recycle(skb); -+ /* skb_recycle() reserves NET_SKB_PAD as skb headroom, -+ * but we need the skb to look as if returned by build_skb(). -+ * We need to manually adjust the tailptr as well. -+ */ -+ skb->data = skb->head + offset; -+ skb_reset_tail_pointer(skb); -+ -+ (*countptr)++; -+ percpu_priv->tx_returned++; -+ } -+ -+ if (unlikely(dpa_xmit(priv, percpu_stats, &fd, egress_fq, conf_fq) < 0)) -+ goto xmit_failed; -+ -+ net_dev->trans_start = jiffies; -+ return NETDEV_TX_OK; -+ -+xmit_failed: -+ if (fd.bpid != 0xff) { -+ (*countptr)--; -+ percpu_priv->tx_returned--; -+ dpa_fd_release(net_dev, &fd); -+ percpu_stats->tx_errors++; -+ return NETDEV_TX_OK; -+ } -+ _dpa_cleanup_tx_fd(priv, &fd); -+skb_to_fd_failed: -+enomem: -+ percpu_stats->tx_errors++; -+ dev_kfree_skb(skb); -+ return NETDEV_TX_OK; -+} -+EXPORT_SYMBOL(dpa_tx_extended); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_shared.c -@@ -0,0 +1,914 @@ -+/* Copyright 2008-2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifdef CONFIG_FSL_DPAA_ETH_DEBUG -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": %s:%hu:%s() " fmt, \ -+ KBUILD_BASENAME".c", __LINE__, __func__ -+#else -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": " fmt -+#endif -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "dpaa_eth.h" -+#include "dpaa_eth_common.h" -+#include "dpaa_eth_base.h" -+#include "lnxwrp_fsl_fman.h" /* fm_get_rx_extra_headroom(), fm_get_max_frm() */ -+#include "mac.h" -+ -+/* forward declarations */ -+static enum qman_cb_dqrr_result __hot -+shared_rx_dqrr(struct qman_portal *portal, struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq); -+static enum qman_cb_dqrr_result __hot -+shared_tx_default_dqrr(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq); -+static enum qman_cb_dqrr_result -+shared_tx_error_dqrr(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq); -+static void shared_ern(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_mr_entry *msg); -+ -+#define DPA_DESCRIPTION "FSL DPAA Shared Ethernet driver" -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+ -+MODULE_DESCRIPTION(DPA_DESCRIPTION); -+ -+/* This has to work in tandem with the DPA_CS_THRESHOLD_xxx values. */ -+static uint16_t shared_tx_timeout = 1000; -+module_param(shared_tx_timeout, ushort, S_IRUGO); -+MODULE_PARM_DESC(shared_tx_timeout, "The Tx timeout in ms"); -+ -+static const struct of_device_id dpa_shared_match[]; -+ -+static const struct net_device_ops dpa_shared_ops = { -+ .ndo_open = dpa_start, -+ .ndo_start_xmit = dpa_shared_tx, -+ .ndo_stop = dpa_stop, -+ .ndo_tx_timeout = dpa_timeout, -+ .ndo_get_stats64 = dpa_get_stats64, -+ .ndo_set_mac_address = dpa_set_mac_address, -+ .ndo_validate_addr = eth_validate_addr, -+#ifdef CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE -+ .ndo_select_queue = dpa_select_queue, -+#endif -+ .ndo_change_mtu = dpa_change_mtu, -+ .ndo_set_rx_mode = dpa_set_rx_mode, -+ .ndo_init = dpa_ndo_init, -+ .ndo_set_features = dpa_set_features, -+ .ndo_fix_features = dpa_fix_features, -+ .ndo_do_ioctl = dpa_ioctl, -+}; -+ -+const struct dpa_fq_cbs_t shared_fq_cbs = { -+ .rx_defq = { .cb = { .dqrr = shared_rx_dqrr } }, -+ .tx_defq = { .cb = { .dqrr = shared_tx_default_dqrr } }, -+ .rx_errq = { .cb = { .dqrr = shared_rx_dqrr } }, -+ .tx_errq = { .cb = { .dqrr = shared_tx_error_dqrr } }, -+ .egress_ern = { .cb = { .ern = shared_ern } } -+}; -+EXPORT_SYMBOL(shared_fq_cbs); -+ -+static inline void * __must_check __attribute__((nonnull)) -+dpa_phys2virt(const struct dpa_bp *dpa_bp, dma_addr_t addr) -+{ -+ return dpa_bp->vaddr + (addr - dpa_bp->paddr); -+} -+ -+static struct dpa_bp *dpa_size2pool(struct dpa_priv_s *priv, size_t size) -+{ -+ int i; -+ -+ for (i = 0; i < priv->bp_count; i++) -+ if ((size + priv->tx_headroom) <= priv->dpa_bp[i].size) -+ return dpa_bpid2pool(priv->dpa_bp[i].bpid); -+ return ERR_PTR(-ENODEV); -+} -+ -+/* Copy to a memory region that requires kmapping from a linear buffer, -+ * taking into account page boundaries in the destination -+ */ -+static void -+copy_to_unmapped_area(dma_addr_t phys_start, void *src, size_t buf_size) -+{ -+ struct page *page; -+ size_t size, offset; -+ void *page_vaddr; -+ -+ while (buf_size > 0) { -+ offset = offset_in_page(phys_start); -+ size = (offset + buf_size > PAGE_SIZE) ? -+ PAGE_SIZE - offset : buf_size; -+ -+ page = pfn_to_page(phys_start >> PAGE_SHIFT); -+ page_vaddr = kmap_atomic(page); -+ -+ memcpy(page_vaddr + offset, src, size); -+ -+ kunmap_atomic(page_vaddr); -+ -+ phys_start += size; -+ src += size; -+ buf_size -= size; -+ } -+} -+ -+/* Copy from a memory region that requires kmapping to a linear buffer, -+ * taking into account page boundaries in the source -+ */ -+static void -+copy_from_unmapped_area(void *dest, dma_addr_t phys_start, size_t buf_size) -+{ -+ struct page *page; -+ size_t size, offset; -+ void *page_vaddr; -+ -+ while (buf_size > 0) { -+ offset = offset_in_page(phys_start); -+ size = (offset + buf_size > PAGE_SIZE) ? -+ PAGE_SIZE - offset : buf_size; -+ -+ page = pfn_to_page(phys_start >> PAGE_SHIFT); -+ page_vaddr = kmap_atomic(page); -+ -+ memcpy(dest, page_vaddr + offset, size); -+ -+ kunmap_atomic(page_vaddr); -+ -+ phys_start += size; -+ dest += size; -+ buf_size -= size; -+ } -+} -+ -+static void -+dpa_fd_release_sg(const struct net_device *net_dev, -+ const struct qm_fd *fd) -+{ -+ const struct dpa_priv_s *priv; -+ struct qm_sg_entry *sgt; -+ struct dpa_bp *_dpa_bp; -+ struct bm_buffer _bmb; -+ -+ priv = netdev_priv(net_dev); -+ -+ _bmb.hi = fd->addr_hi; -+ _bmb.lo = fd->addr_lo; -+ -+ _dpa_bp = dpa_bpid2pool(fd->bpid); -+ BUG_ON(!_dpa_bp); -+ -+ if (_dpa_bp->vaddr) { -+ sgt = dpa_phys2virt(_dpa_bp, bm_buf_addr(&_bmb)) + -+ dpa_fd_offset(fd); -+ dpa_release_sgt(sgt); -+ } else { -+ sgt = kmalloc(DPA_SGT_MAX_ENTRIES * sizeof(*sgt), GFP_ATOMIC); -+ if (sgt == NULL) { -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_err(net_dev, -+ "Memory allocation failed\n"); -+ return; -+ } -+ -+ copy_from_unmapped_area(sgt, bm_buf_addr(&_bmb) + -+ dpa_fd_offset(fd), -+ min(DPA_SGT_MAX_ENTRIES * sizeof(*sgt), -+ _dpa_bp->size)); -+ dpa_release_sgt(sgt); -+ kfree(sgt); -+ } -+ -+ while (bman_release(_dpa_bp->pool, &_bmb, 1, 0)) -+ cpu_relax(); -+} -+ -+static enum qman_cb_dqrr_result __hot -+shared_rx_dqrr(struct qman_portal *portal, struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq) -+{ -+ struct net_device *net_dev; -+ struct dpa_priv_s *priv; -+ struct dpa_percpu_priv_s *percpu_priv; -+ const struct qm_fd *fd = &dq->fd; -+ struct dpa_bp *dpa_bp; -+ struct sk_buff *skb; -+ struct qm_sg_entry *sgt; -+ int i; -+ void *frag_addr; -+ u32 frag_length; -+ u32 offset; -+ -+ net_dev = ((struct dpa_fq *)fq)->net_dev; -+ priv = netdev_priv(net_dev); -+ -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ -+ dpa_bp = dpa_bpid2pool(fd->bpid); -+ BUG_ON(!dpa_bp); -+ -+ if (unlikely(fd->status & FM_FD_STAT_RX_ERRORS) != 0) { -+ if (netif_msg_hw(priv) && net_ratelimit()) -+ netdev_warn(net_dev, "FD status = 0x%08x\n", -+ fd->status & FM_FD_STAT_RX_ERRORS); -+ -+ percpu_priv->stats.rx_errors++; -+ -+ goto out; -+ } -+ -+ skb = __netdev_alloc_skb(net_dev, -+ priv->tx_headroom + dpa_fd_length(fd), -+ GFP_ATOMIC); -+ if (unlikely(skb == NULL)) { -+ if (netif_msg_rx_err(priv) && net_ratelimit()) -+ netdev_err(net_dev, "Could not alloc skb\n"); -+ -+ percpu_priv->stats.rx_dropped++; -+ -+ goto out; -+ } -+ -+ skb_reserve(skb, priv->tx_headroom); -+ -+ if (fd->format == qm_fd_sg) { -+ if (dpa_bp->vaddr) { -+ sgt = dpa_phys2virt(dpa_bp, -+ qm_fd_addr(fd)) + dpa_fd_offset(fd); -+ -+ for (i = 0; i < DPA_SGT_MAX_ENTRIES; i++) { -+ offset = qm_sg_entry_get_offset(&sgt[i]); -+ frag_addr = dpa_phys2virt(dpa_bp, -+ qm_sg_addr(&sgt[i]) + -+ offset); -+ DPA_BUG_ON(qm_sg_entry_get_ext(&sgt[i])); -+ frag_length = qm_sg_entry_get_len(&sgt[i]); -+ -+ /* copy from sgt[i] */ -+ memcpy(skb_put(skb, frag_length), frag_addr, -+ frag_length); -+ if (qm_sg_entry_get_final(&sgt[i])) -+ break; -+ } -+ } else { -+ sgt = kmalloc(DPA_SGT_MAX_ENTRIES * sizeof(*sgt), -+ GFP_ATOMIC); -+ if (unlikely(sgt == NULL)) { -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_err(net_dev, -+ "Memory allocation failed\n"); -+ return -ENOMEM; -+ } -+ -+ copy_from_unmapped_area(sgt, -+ qm_fd_addr(fd) + dpa_fd_offset(fd), -+ min(DPA_SGT_MAX_ENTRIES * sizeof(*sgt), -+ dpa_bp->size)); -+ -+ for (i = 0; i < DPA_SGT_MAX_ENTRIES; i++) { -+ DPA_BUG_ON(qm_sg_entry_get_ext(&sgt[i])); -+ frag_length = qm_sg_entry_get_len(&sgt[i]); -+ copy_from_unmapped_area( -+ skb_put(skb, frag_length), -+ qm_sg_addr(&sgt[i]) + -+ qm_sg_entry_get_offset(&sgt[i]), -+ frag_length); -+ -+ if (qm_sg_entry_get_final(&sgt[i])) -+ break; -+ } -+ -+ kfree(sgt); -+ } -+ goto skb_copied; -+ } -+ -+ /* otherwise fd->format == qm_fd_contig */ -+ if (dpa_bp->vaddr) { -+ /* Fill the SKB */ -+ memcpy(skb_put(skb, dpa_fd_length(fd)), -+ dpa_phys2virt(dpa_bp, qm_fd_addr(fd)) + -+ dpa_fd_offset(fd), dpa_fd_length(fd)); -+ } else { -+ copy_from_unmapped_area(skb_put(skb, dpa_fd_length(fd)), -+ qm_fd_addr(fd) + dpa_fd_offset(fd), -+ dpa_fd_length(fd)); -+ } -+ -+skb_copied: -+ skb->protocol = eth_type_trans(skb, net_dev); -+ -+ /* IP Reassembled frames are allowed to be larger than MTU */ -+ if (unlikely(dpa_check_rx_mtu(skb, net_dev->mtu) && -+ !(fd->status & FM_FD_IPR))) { -+ percpu_priv->stats.rx_dropped++; -+ dev_kfree_skb_any(skb); -+ goto out; -+ } -+ -+ if (unlikely(netif_rx(skb) != NET_RX_SUCCESS)) -+ goto out; -+ else { -+ percpu_priv->stats.rx_packets++; -+ percpu_priv->stats.rx_bytes += dpa_fd_length(fd); -+ } -+ -+out: -+ if (fd->format == qm_fd_sg) -+ dpa_fd_release_sg(net_dev, fd); -+ else -+ dpa_fd_release(net_dev, fd); -+ -+ return qman_cb_dqrr_consume; -+} -+ -+static enum qman_cb_dqrr_result -+shared_tx_error_dqrr(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq) -+{ -+ struct net_device *net_dev; -+ struct dpa_priv_s *priv; -+ struct dpa_percpu_priv_s *percpu_priv; -+ struct dpa_bp *dpa_bp; -+ const struct qm_fd *fd = &dq->fd; -+ -+ net_dev = ((struct dpa_fq *)fq)->net_dev; -+ priv = netdev_priv(net_dev); -+ -+ dpa_bp = dpa_bpid2pool(fd->bpid); -+ BUG_ON(!dpa_bp); -+ -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ -+ if (netif_msg_hw(priv) && net_ratelimit()) -+ netdev_warn(net_dev, "FD status = 0x%08x\n", -+ fd->status & FM_FD_STAT_TX_ERRORS); -+ -+ if ((fd->format == qm_fd_sg) && (!dpa_bp->vaddr)) -+ dpa_fd_release_sg(net_dev, fd); -+ else -+ dpa_fd_release(net_dev, fd); -+ -+ percpu_priv->stats.tx_errors++; -+ -+ return qman_cb_dqrr_consume; -+} -+ -+static enum qman_cb_dqrr_result __hot -+shared_tx_default_dqrr(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq) -+{ -+ struct net_device *net_dev; -+ struct dpa_priv_s *priv; -+ struct dpa_percpu_priv_s *percpu_priv; -+ struct dpa_bp *dpa_bp; -+ const struct qm_fd *fd = &dq->fd; -+ -+ net_dev = ((struct dpa_fq *)fq)->net_dev; -+ priv = netdev_priv(net_dev); -+ -+ dpa_bp = dpa_bpid2pool(fd->bpid); -+ BUG_ON(!dpa_bp); -+ -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ -+ if (unlikely(fd->status & FM_FD_STAT_TX_ERRORS) != 0) { -+ if (netif_msg_hw(priv) && net_ratelimit()) -+ netdev_warn(net_dev, "FD status = 0x%08x\n", -+ fd->status & FM_FD_STAT_TX_ERRORS); -+ -+ percpu_priv->stats.tx_errors++; -+ } -+ -+ if ((fd->format == qm_fd_sg) && (!dpa_bp->vaddr)) -+ dpa_fd_release_sg(net_dev, fd); -+ else -+ dpa_fd_release(net_dev, fd); -+ -+ percpu_priv->tx_confirm++; -+ -+ return qman_cb_dqrr_consume; -+} -+ -+static void shared_ern(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_mr_entry *msg) -+{ -+ struct net_device *net_dev; -+ const struct dpa_priv_s *priv; -+ struct dpa_percpu_priv_s *percpu_priv; -+ struct dpa_fq *dpa_fq = (struct dpa_fq *)fq; -+ -+ net_dev = dpa_fq->net_dev; -+ priv = netdev_priv(net_dev); -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ -+ dpa_fd_release(net_dev, &msg->ern.fd); -+ -+ percpu_priv->stats.tx_dropped++; -+ percpu_priv->stats.tx_fifo_errors++; -+ count_ern(percpu_priv, msg); -+} -+ -+int __hot dpa_shared_tx(struct sk_buff *skb, struct net_device *net_dev) -+{ -+ struct dpa_bp *dpa_bp; -+ struct bm_buffer bmb; -+ struct dpa_percpu_priv_s *percpu_priv; -+ struct dpa_priv_s *priv; -+ struct qm_fd fd; -+ int queue_mapping; -+ int err; -+ void *dpa_bp_vaddr; -+ fm_prs_result_t parse_results; -+ fm_prs_result_t *parse_results_ref; -+ struct qman_fq *egress_fq, *conf_fq; -+ -+ priv = netdev_priv(net_dev); -+ percpu_priv = raw_cpu_ptr(priv->percpu_priv); -+ -+ memset(&fd, 0, sizeof(fd)); -+ fd.format = qm_fd_contig; -+ -+ queue_mapping = smp_processor_id(); -+ -+ dpa_bp = dpa_size2pool(priv, skb_headlen(skb)); -+ if (unlikely(!dpa_bp)) { -+ percpu_priv->stats.tx_errors++; -+ err = PTR_ERR(dpa_bp); -+ goto bpools_too_small_error; -+ } -+ -+ err = bman_acquire(dpa_bp->pool, &bmb, 1, 0); -+ if (unlikely(err <= 0)) { -+ percpu_priv->stats.tx_errors++; -+ if (err == 0) -+ err = -ENOMEM; -+ goto buf_acquire_failed; -+ } -+ fd.bpid = dpa_bp->bpid; -+ -+ fd.length20 = skb_headlen(skb); -+ fd.addr_hi = (uint8_t)bmb.hi; -+ fd.addr_lo = bmb.lo; -+ fd.offset = priv->tx_headroom; -+ -+ /* The virtual address of the buffer pool is expected to be NULL -+ * in scenarios like MAC-less or Shared-MAC between Linux and -+ * USDPAA. In this case the buffers are dynamically mapped/unmapped. -+ */ -+ if (dpa_bp->vaddr) { -+ dpa_bp_vaddr = dpa_phys2virt(dpa_bp, bm_buf_addr(&bmb)); -+ -+ /* Copy the packet payload */ -+ skb_copy_from_linear_data(skb, -+ dpa_bp_vaddr + dpa_fd_offset(&fd), -+ dpa_fd_length(&fd)); -+ -+ /* if no mac device or peer set it's macless */ -+ if (!priv->mac_dev || priv->peer) { -+ parse_results_ref = (fm_prs_result_t *) (dpa_bp_vaddr + -+ DPA_TX_PRIV_DATA_SIZE); -+ /* Default values; FMan will not generate/validate -+ * CSUM; -+ */ -+ parse_results_ref->l3r = 0; -+ parse_results_ref->l4r = 0; -+ parse_results_ref->ip_off[0] = 0xff; -+ parse_results_ref->ip_off[1] = 0xff; -+ parse_results_ref->l4_off = 0xff; -+ -+ fd.cmd |= FM_FD_CMD_DTC | FM_FD_CMD_RPD; -+ } else { -+ /* Enable L3/L4 hardware checksum computation, -+ * if applicable -+ */ -+ err = dpa_enable_tx_csum(priv, skb, &fd, -+ dpa_bp_vaddr + DPA_TX_PRIV_DATA_SIZE); -+ -+ if (unlikely(err < 0)) { -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_err(net_dev, -+ "Tx HW csum error: %d\n", err); -+ percpu_priv->stats.tx_errors++; -+ goto l3_l4_csum_failed; -+ } -+ } -+ -+ } else { -+ if (!priv->mac_dev || priv->peer) { -+ /* Default values; FMan will not generate/validate -+ * CSUM; -+ */ -+ parse_results.l3r = 0; -+ parse_results.l4r = 0; -+ parse_results.ip_off[0] = 0xff; -+ parse_results.ip_off[1] = 0xff; -+ parse_results.l4_off = 0xff; -+ -+ fd.cmd |= FM_FD_CMD_DTC | FM_FD_CMD_RPD; -+ } else { -+ /* Enable L3/L4 hardware checksum computation, -+ * if applicable -+ */ -+ err = dpa_enable_tx_csum(priv, skb, &fd, -+ (char *)&parse_results); -+ -+ if (unlikely(err < 0)) { -+ if (netif_msg_tx_err(priv) && net_ratelimit()) -+ netdev_err(net_dev, -+ "Tx HW csum error: %d\n", err); -+ percpu_priv->stats.tx_errors++; -+ goto l3_l4_csum_failed; -+ } -+ -+ } -+ -+ copy_to_unmapped_area(bm_buf_addr(&bmb) + DPA_TX_PRIV_DATA_SIZE, -+ &parse_results, -+ DPA_PARSE_RESULTS_SIZE); -+ -+ copy_to_unmapped_area(bm_buf_addr(&bmb) + dpa_fd_offset(&fd), -+ skb->data, -+ dpa_fd_length(&fd)); -+ } -+ -+ egress_fq = priv->egress_fqs[queue_mapping]; -+ conf_fq = priv->conf_fqs[queue_mapping]; -+ -+ err = dpa_xmit(priv, &percpu_priv->stats, &fd, egress_fq, conf_fq); -+ -+l3_l4_csum_failed: -+bpools_too_small_error: -+buf_acquire_failed: -+ /* We're done with the skb */ -+ dev_kfree_skb(skb); -+ -+ /* err remains unused, NETDEV_TX_OK must be returned here */ -+ return NETDEV_TX_OK; -+} -+EXPORT_SYMBOL(dpa_shared_tx); -+ -+static int dpa_shared_netdev_init(struct device_node *dpa_node, -+ struct net_device *net_dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ const uint8_t *mac_addr; -+ -+ net_dev->netdev_ops = &dpa_shared_ops; -+ -+ net_dev->mem_start = priv->mac_dev->res->start; -+ net_dev->mem_end = priv->mac_dev->res->end; -+ -+ mac_addr = priv->mac_dev->addr; -+ -+ net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | -+ NETIF_F_LLTX); -+ -+ return dpa_netdev_init(net_dev, mac_addr, shared_tx_timeout); -+} -+ -+#ifdef CONFIG_PM -+ -+static int dpa_shared_suspend(struct device *dev) -+{ -+ struct net_device *net_dev; -+ struct dpa_priv_s *priv; -+ struct mac_device *mac_dev; -+ int err = 0; -+ -+ net_dev = dev_get_drvdata(dev); -+ if (net_dev->flags & IFF_UP) { -+ priv = netdev_priv(net_dev); -+ mac_dev = priv->mac_dev; -+ -+ err = fm_port_suspend(mac_dev->port_dev[RX]); -+ if (err) -+ goto port_suspend_failed; -+ -+ err = fm_port_suspend(mac_dev->port_dev[TX]); -+ if (err) -+ err = fm_port_resume(mac_dev->port_dev[RX]); -+ } -+ -+port_suspend_failed: -+ return err; -+} -+ -+static int dpa_shared_resume(struct device *dev) -+{ -+ struct net_device *net_dev; -+ struct dpa_priv_s *priv; -+ struct mac_device *mac_dev; -+ int err = 0; -+ -+ net_dev = dev_get_drvdata(dev); -+ if (net_dev->flags & IFF_UP) { -+ priv = netdev_priv(net_dev); -+ mac_dev = priv->mac_dev; -+ -+ err = fm_port_resume(mac_dev->port_dev[TX]); -+ if (err) -+ goto port_resume_failed; -+ -+ err = fm_port_resume(mac_dev->port_dev[RX]); -+ if (err) -+ err = fm_port_suspend(mac_dev->port_dev[TX]); -+ } -+ -+port_resume_failed: -+ return err; -+} -+ -+static const struct dev_pm_ops shared_pm_ops = { -+ .suspend = dpa_shared_suspend, -+ .resume = dpa_shared_resume, -+}; -+ -+#define SHARED_PM_OPS (&shared_pm_ops) -+ -+#else /* CONFIG_PM */ -+ -+#define SHARED_PM_OPS NULL -+ -+#endif /* CONFIG_PM */ -+ -+static int -+dpaa_eth_shared_probe(struct platform_device *_of_dev) -+{ -+ int err = 0, i, channel; -+ struct device *dev; -+ struct device_node *dpa_node; -+ struct dpa_bp *dpa_bp; -+ struct dpa_fq *dpa_fq, *tmp; -+ size_t count; -+ struct net_device *net_dev = NULL; -+ struct dpa_priv_s *priv = NULL; -+ struct dpa_percpu_priv_s *percpu_priv; -+ struct fm_port_fqs port_fqs; -+ struct dpa_buffer_layout_s *buf_layout = NULL; -+ struct mac_device *mac_dev; -+ struct task_struct *kth; -+ -+ dev = &_of_dev->dev; -+ -+ dpa_node = dev->of_node; -+ -+ if (!of_device_is_available(dpa_node)) -+ return -ENODEV; -+ -+ /* Get the buffer pools assigned to this interface */ -+ dpa_bp = dpa_bp_probe(_of_dev, &count); -+ if (IS_ERR(dpa_bp)) -+ return PTR_ERR(dpa_bp); -+ -+ for (i = 0; i < count; i++) -+ dpa_bp[i].seed_cb = dpa_bp_shared_port_seed; -+ -+ /* Allocate this early, so we can store relevant information in -+ * the private area (needed by 1588 code in dpa_mac_probe) -+ */ -+ net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TX_QUEUES); -+ if (!net_dev) { -+ dev_err(dev, "alloc_etherdev_mq() failed\n"); -+ return -ENOMEM; -+ } -+ -+ /* Do this here, so we can be verbose early */ -+ SET_NETDEV_DEV(net_dev, dev); -+ dev_set_drvdata(dev, net_dev); -+ -+ priv = netdev_priv(net_dev); -+ priv->net_dev = net_dev; -+ strcpy(priv->if_type, "shared"); -+ -+ priv->msg_enable = netif_msg_init(advanced_debug, -1); -+ -+ mac_dev = dpa_mac_probe(_of_dev); -+ if (IS_ERR(mac_dev) || !mac_dev) { -+ err = PTR_ERR(mac_dev); -+ goto mac_probe_failed; -+ } -+ -+ /* We have physical ports, so we need to establish -+ * the buffer layout. -+ */ -+ buf_layout = devm_kzalloc(dev, 2 * sizeof(*buf_layout), -+ GFP_KERNEL); -+ if (!buf_layout) { -+ dev_err(dev, "devm_kzalloc() failed\n"); -+ goto alloc_failed; -+ } -+ dpa_set_buffers_layout(mac_dev, buf_layout); -+ -+ INIT_LIST_HEAD(&priv->dpa_fq_list); -+ -+ memset(&port_fqs, 0, sizeof(port_fqs)); -+ -+ err = dpa_fq_probe_mac(dev, &priv->dpa_fq_list, &port_fqs, -+ false, RX); -+ if (!err) -+ err = dpa_fq_probe_mac(dev, &priv->dpa_fq_list, -+ &port_fqs, false, TX); -+ if (err < 0) -+ goto fq_probe_failed; -+ -+ /* bp init */ -+ priv->bp_count = count; -+ err = dpa_bp_create(net_dev, dpa_bp, count); -+ if (err < 0) -+ goto bp_create_failed; -+ -+ priv->mac_dev = mac_dev; -+ -+ channel = dpa_get_channel(); -+ -+ if (channel < 0) { -+ err = channel; -+ goto get_channel_failed; -+ } -+ -+ priv->channel = (uint16_t)channel; -+ -+ /* Start a thread that will walk the cpus with affine portals -+ * and add this pool channel to each's dequeue mask. -+ */ -+ kth = kthread_run(dpaa_eth_add_channel, -+ (void *)(unsigned long)priv->channel, -+ "dpaa_%p:%d", net_dev, priv->channel); -+ if (!kth) { -+ err = -ENOMEM; -+ goto add_channel_failed; -+ } -+ -+ dpa_fq_setup(priv, &shared_fq_cbs, priv->mac_dev->port_dev[TX]); -+ -+ /* Create a congestion group for this netdev, with -+ * dynamically-allocated CGR ID. -+ * Must be executed after probing the MAC, but before -+ * assigning the egress FQs to the CGRs. -+ */ -+ err = dpaa_eth_cgr_init(priv); -+ if (err < 0) { -+ dev_err(dev, "Error initializing CGR\n"); -+ goto cgr_init_failed; -+ } -+ -+ /* Add the FQs to the interface, and make them active */ -+ list_for_each_entry_safe(dpa_fq, tmp, &priv->dpa_fq_list, list) { -+ err = dpa_fq_init(dpa_fq, false); -+ if (err < 0) -+ goto fq_alloc_failed; -+ } -+ -+ priv->buf_layout = buf_layout; -+ priv->tx_headroom = -+ dpa_get_headroom(&priv->buf_layout[TX]); -+ -+ /* All real interfaces need their ports initialized */ -+ dpaa_eth_init_ports(mac_dev, dpa_bp, count, &port_fqs, -+ buf_layout, dev); -+ -+ /* Now we need to initialize either a private or shared interface */ -+ priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv); -+ -+ if (priv->percpu_priv == NULL) { -+ dev_err(dev, "devm_alloc_percpu() failed\n"); -+ err = -ENOMEM; -+ goto alloc_percpu_failed; -+ } -+ for_each_possible_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ memset(percpu_priv, 0, sizeof(*percpu_priv)); -+ } -+ -+ err = dpa_shared_netdev_init(dpa_node, net_dev); -+ -+ if (err < 0) -+ goto netdev_init_failed; -+ -+ dpaa_eth_sysfs_init(&net_dev->dev); -+ -+ pr_info("fsl_dpa_shared: Probed shared interface %s\n", -+ net_dev->name); -+ -+ return 0; -+ -+netdev_init_failed: -+alloc_percpu_failed: -+fq_alloc_failed: -+ if (net_dev) { -+ dpa_fq_free(dev, &priv->dpa_fq_list); -+ qman_release_cgrid(priv->cgr_data.cgr.cgrid); -+ qman_delete_cgr(&priv->cgr_data.cgr); -+ } -+cgr_init_failed: -+add_channel_failed: -+get_channel_failed: -+ if (net_dev) -+ dpa_bp_free(priv); -+bp_create_failed: -+fq_probe_failed: -+ devm_kfree(dev, buf_layout); -+alloc_failed: -+mac_probe_failed: -+ dev_set_drvdata(dev, NULL); -+ if (net_dev) -+ free_netdev(net_dev); -+ -+ return err; -+} -+ -+static const struct of_device_id dpa_shared_match[] = { -+ { -+ .compatible = "fsl,dpa-ethernet-shared" -+ }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, dpa_shared_match); -+ -+static struct platform_driver dpa_shared_driver = { -+ .driver = { -+ .name = KBUILD_MODNAME "-shared", -+ .of_match_table = dpa_shared_match, -+ .owner = THIS_MODULE, -+ .pm = SHARED_PM_OPS, -+ }, -+ .probe = dpaa_eth_shared_probe, -+ .remove = dpa_remove -+}; -+ -+static int __init __cold dpa_shared_load(void) -+{ -+ int _errno; -+ -+ pr_info(DPA_DESCRIPTION "\n"); -+ -+ /* Initialize dpaa_eth mirror values */ -+ dpa_rx_extra_headroom = fm_get_rx_extra_headroom(); -+ dpa_max_frm = fm_get_max_frm(); -+ -+ _errno = platform_driver_register(&dpa_shared_driver); -+ if (unlikely(_errno < 0)) { -+ pr_err(KBUILD_MODNAME -+ ": %s:%hu:%s(): platform_driver_register() = %d\n", -+ KBUILD_BASENAME".c", __LINE__, __func__, _errno); -+ } -+ -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+ -+ return _errno; -+} -+module_init(dpa_shared_load); -+ -+static void __exit __cold dpa_shared_unload(void) -+{ -+ pr_debug(KBUILD_MODNAME ": -> %s:%s()\n", -+ KBUILD_BASENAME".c", __func__); -+ -+ platform_driver_unregister(&dpa_shared_driver); -+} -+module_exit(dpa_shared_unload); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_sysfs.c -@@ -0,0 +1,278 @@ -+/* Copyright 2008-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "dpaa_eth.h" -+#include "mac.h" /* struct mac_device */ -+#ifdef CONFIG_FSL_DPAA_1588 -+#include "dpaa_1588.h" -+#endif -+ -+static ssize_t dpaa_eth_show_addr(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct dpa_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ struct mac_device *mac_dev = priv->mac_dev; -+ -+ if (mac_dev) -+ return sprintf(buf, "%llx", -+ (unsigned long long)mac_dev->res->start); -+ else -+ return sprintf(buf, "none"); -+} -+ -+static ssize_t dpaa_eth_show_type(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct dpa_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ ssize_t res = 0; -+ -+ if (priv) -+ res = sprintf(buf, "%s", priv->if_type); -+ -+ return res; -+} -+ -+static ssize_t dpaa_eth_show_fqids(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct dpa_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ ssize_t bytes = 0; -+ int i = 0; -+ char *str; -+ struct dpa_fq *fq; -+ struct dpa_fq *tmp; -+ struct dpa_fq *prev = NULL; -+ u32 first_fqid = 0; -+ u32 last_fqid = 0; -+ char *prevstr = NULL; -+ -+ list_for_each_entry_safe(fq, tmp, &priv->dpa_fq_list, list) { -+ switch (fq->fq_type) { -+ case FQ_TYPE_RX_DEFAULT: -+ str = "Rx default"; -+ break; -+ case FQ_TYPE_RX_ERROR: -+ str = "Rx error"; -+ break; -+ case FQ_TYPE_RX_PCD: -+ str = "Rx PCD"; -+ break; -+ case FQ_TYPE_TX_CONFIRM: -+ str = "Tx default confirmation"; -+ break; -+ case FQ_TYPE_TX_CONF_MQ: -+ str = "Tx confirmation (mq)"; -+ break; -+ case FQ_TYPE_TX_ERROR: -+ str = "Tx error"; -+ break; -+ case FQ_TYPE_TX: -+ str = "Tx"; -+ break; -+ case FQ_TYPE_RX_PCD_HI_PRIO: -+ str ="Rx PCD High Priority"; -+ break; -+ default: -+ str = "Unknown"; -+ } -+ -+ if (prev && (abs(fq->fqid - prev->fqid) != 1 || -+ str != prevstr)) { -+ if (last_fqid == first_fqid) -+ bytes += sprintf(buf + bytes, -+ "%s: %d\n", prevstr, prev->fqid); -+ else -+ bytes += sprintf(buf + bytes, -+ "%s: %d - %d\n", prevstr, -+ first_fqid, last_fqid); -+ } -+ -+ if (prev && abs(fq->fqid - prev->fqid) == 1 && str == prevstr) -+ last_fqid = fq->fqid; -+ else -+ first_fqid = last_fqid = fq->fqid; -+ -+ prev = fq; -+ prevstr = str; -+ i++; -+ } -+ -+ if (prev) { -+ if (last_fqid == first_fqid) -+ bytes += sprintf(buf + bytes, "%s: %d\n", prevstr, -+ prev->fqid); -+ else -+ bytes += sprintf(buf + bytes, "%s: %d - %d\n", prevstr, -+ first_fqid, last_fqid); -+ } -+ -+ return bytes; -+} -+ -+static ssize_t dpaa_eth_show_bpids(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t bytes = 0; -+ struct dpa_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ struct dpa_bp *dpa_bp = priv->dpa_bp; -+ int i = 0; -+ -+ for (i = 0; i < priv->bp_count; i++) -+ bytes += snprintf(buf + bytes, PAGE_SIZE, "%u\n", -+ dpa_bp[i].bpid); -+ -+ return bytes; -+} -+ -+static ssize_t dpaa_eth_show_mac_regs(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct dpa_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ struct mac_device *mac_dev = priv->mac_dev; -+ int n = 0; -+ -+ if (mac_dev) -+ n = fm_mac_dump_regs(mac_dev, buf, n); -+ else -+ return sprintf(buf, "no mac registers\n"); -+ -+ return n; -+} -+ -+static ssize_t dpaa_eth_show_mac_rx_stats(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct dpa_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ struct mac_device *mac_dev = priv->mac_dev; -+ int n = 0; -+ -+ if (mac_dev) -+ n = fm_mac_dump_rx_stats(mac_dev, buf, n); -+ else -+ return sprintf(buf, "no mac rx stats\n"); -+ -+ return n; -+} -+ -+static ssize_t dpaa_eth_show_mac_tx_stats(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct dpa_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ struct mac_device *mac_dev = priv->mac_dev; -+ int n = 0; -+ -+ if (mac_dev) -+ n = fm_mac_dump_tx_stats(mac_dev, buf, n); -+ else -+ return sprintf(buf, "no mac tx stats\n"); -+ -+ return n; -+} -+ -+#ifdef CONFIG_FSL_DPAA_1588 -+static ssize_t dpaa_eth_show_ptp_1588(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct dpa_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ -+ if (priv->tsu && priv->tsu->valid) -+ return sprintf(buf, "1\n"); -+ else -+ return sprintf(buf, "0\n"); -+} -+ -+static ssize_t dpaa_eth_set_ptp_1588(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct dpa_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ unsigned int num; -+ unsigned long flags; -+ -+ if (kstrtouint(buf, 0, &num) < 0) -+ return -EINVAL; -+ -+ local_irq_save(flags); -+ -+ if (num) { -+ if (priv->tsu) -+ priv->tsu->valid = TRUE; -+ } else { -+ if (priv->tsu) -+ priv->tsu->valid = FALSE; -+ } -+ -+ local_irq_restore(flags); -+ -+ return count; -+} -+#endif -+ -+static struct device_attribute dpaa_eth_attrs[] = { -+ __ATTR(device_addr, S_IRUGO, dpaa_eth_show_addr, NULL), -+ __ATTR(device_type, S_IRUGO, dpaa_eth_show_type, NULL), -+ __ATTR(fqids, S_IRUGO, dpaa_eth_show_fqids, NULL), -+ __ATTR(bpids, S_IRUGO, dpaa_eth_show_bpids, NULL), -+ __ATTR(mac_regs, S_IRUGO, dpaa_eth_show_mac_regs, NULL), -+ __ATTR(mac_rx_stats, S_IRUGO, dpaa_eth_show_mac_rx_stats, NULL), -+ __ATTR(mac_tx_stats, S_IRUGO, dpaa_eth_show_mac_tx_stats, NULL), -+#ifdef CONFIG_FSL_DPAA_1588 -+ __ATTR(ptp_1588, S_IRUGO | S_IWUSR, dpaa_eth_show_ptp_1588, -+ dpaa_eth_set_ptp_1588), -+#endif -+}; -+ -+void dpaa_eth_sysfs_init(struct device *dev) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(dpaa_eth_attrs); i++) -+ if (device_create_file(dev, &dpaa_eth_attrs[i])) { -+ dev_err(dev, "Error creating sysfs file\n"); -+ while (i > 0) -+ device_remove_file(dev, &dpaa_eth_attrs[--i]); -+ return; -+ } -+} -+EXPORT_SYMBOL(dpaa_eth_sysfs_init); -+ -+void dpaa_eth_sysfs_remove(struct device *dev) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(dpaa_eth_attrs); i++) -+ device_remove_file(dev, &dpaa_eth_attrs[i]); -+} ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_trace.h -@@ -0,0 +1,144 @@ -+/* Copyright 2013 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#undef TRACE_SYSTEM -+#define TRACE_SYSTEM dpaa_eth -+ -+#if !defined(_DPAA_ETH_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) -+#define _DPAA_ETH_TRACE_H -+ -+#include -+#include -+#include "dpaa_eth.h" -+#include -+ -+#define fd_format_name(format) { qm_fd_##format, #format } -+#define fd_format_list \ -+ fd_format_name(contig), \ -+ fd_format_name(sg) -+#define TR_FMT "[%s] fqid=%d, fd: addr=0x%llx, format=%s, off=%u, len=%u," \ -+ " status=0x%08x" -+ -+/* This is used to declare a class of events. -+ * individual events of this type will be defined below. -+ */ -+ -+/* Store details about a frame descriptor and the FQ on which it was -+ * transmitted/received. -+ */ -+DECLARE_EVENT_CLASS(dpaa_eth_fd, -+ /* Trace function prototype */ -+ TP_PROTO(struct net_device *netdev, -+ struct qman_fq *fq, -+ const struct qm_fd *fd), -+ -+ /* Repeat argument list here */ -+ TP_ARGS(netdev, fq, fd), -+ -+ /* A structure containing the relevant information we want to record. -+ * Declare name and type for each normal element, name, type and size -+ * for arrays. Use __string for variable length strings. -+ */ -+ TP_STRUCT__entry( -+ __field(u32, fqid) -+ __field(u64, fd_addr) -+ __field(u8, fd_format) -+ __field(u16, fd_offset) -+ __field(u32, fd_length) -+ __field(u32, fd_status) -+ __string(name, netdev->name) -+ ), -+ -+ /* The function that assigns values to the above declared fields */ -+ TP_fast_assign( -+ __entry->fqid = fq->fqid; -+ __entry->fd_addr = qm_fd_addr_get64(fd); -+ __entry->fd_format = fd->format; -+ __entry->fd_offset = dpa_fd_offset(fd); -+ __entry->fd_length = dpa_fd_length(fd); -+ __entry->fd_status = fd->status; -+ __assign_str(name, netdev->name); -+ ), -+ -+ /* This is what gets printed when the trace event is triggered */ -+ /* TODO: print the status using __print_flags() */ -+ TP_printk(TR_FMT, -+ __get_str(name), __entry->fqid, __entry->fd_addr, -+ __print_symbolic(__entry->fd_format, fd_format_list), -+ __entry->fd_offset, __entry->fd_length, __entry->fd_status) -+); -+ -+/* Now declare events of the above type. Format is: -+ * DEFINE_EVENT(class, name, proto, args), with proto and args same as for class -+ */ -+ -+/* Tx (egress) fd */ -+DEFINE_EVENT(dpaa_eth_fd, dpa_tx_fd, -+ -+ TP_PROTO(struct net_device *netdev, -+ struct qman_fq *fq, -+ const struct qm_fd *fd), -+ -+ TP_ARGS(netdev, fq, fd) -+); -+ -+/* Rx fd */ -+DEFINE_EVENT(dpaa_eth_fd, dpa_rx_fd, -+ -+ TP_PROTO(struct net_device *netdev, -+ struct qman_fq *fq, -+ const struct qm_fd *fd), -+ -+ TP_ARGS(netdev, fq, fd) -+); -+ -+/* Tx confirmation fd */ -+DEFINE_EVENT(dpaa_eth_fd, dpa_tx_conf_fd, -+ -+ TP_PROTO(struct net_device *netdev, -+ struct qman_fq *fq, -+ const struct qm_fd *fd), -+ -+ TP_ARGS(netdev, fq, fd) -+); -+ -+/* If only one event of a certain type needs to be declared, use TRACE_EVENT(). -+ * The syntax is the same as for DECLARE_EVENT_CLASS(). -+ */ -+ -+#endif /* _DPAA_ETH_TRACE_H */ -+ -+/* This must be outside ifdef _DPAA_ETH_TRACE_H */ -+#undef TRACE_INCLUDE_PATH -+#define TRACE_INCLUDE_PATH . -+#undef TRACE_INCLUDE_FILE -+#define TRACE_INCLUDE_FILE dpaa_eth_trace -+#include ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_ethtool.c -@@ -0,0 +1,544 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifdef CONFIG_FSL_DPAA_ETH_DEBUG -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": %s:%hu:%s() " fmt, \ -+ KBUILD_BASENAME".c", __LINE__, __func__ -+#else -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": " fmt -+#endif -+ -+#include -+ -+#include "dpaa_eth.h" -+#include "mac.h" /* struct mac_device */ -+#include "dpaa_eth_common.h" -+ -+static const char dpa_stats_percpu[][ETH_GSTRING_LEN] = { -+ "interrupts", -+ "rx packets", -+ "tx packets", -+ "tx recycled", -+ "tx confirm", -+ "tx S/G", -+ "rx S/G", -+ "tx error", -+ "rx error", -+ "bp count" -+}; -+ -+static char dpa_stats_global[][ETH_GSTRING_LEN] = { -+ /* dpa rx errors */ -+ "rx dma error", -+ "rx frame physical error", -+ "rx frame size error", -+ "rx header error", -+ "rx csum error", -+ -+ /* demultiplexing errors */ -+ "qman cg_tdrop", -+ "qman wred", -+ "qman error cond", -+ "qman early window", -+ "qman late window", -+ "qman fq tdrop", -+ "qman fq retired", -+ "qman orp disabled", -+ -+ /* congestion related stats */ -+ "congestion time (ms)", -+ "entered congestion", -+ "congested (0/1)" -+}; -+ -+#define DPA_STATS_PERCPU_LEN ARRAY_SIZE(dpa_stats_percpu) -+#define DPA_STATS_GLOBAL_LEN ARRAY_SIZE(dpa_stats_global) -+ -+static int __cold dpa_get_settings(struct net_device *net_dev, -+ struct ethtool_cmd *et_cmd) -+{ -+ int _errno; -+ struct dpa_priv_s *priv; -+ -+ priv = netdev_priv(net_dev); -+ -+ if (priv->mac_dev == NULL) { -+ netdev_info(net_dev, "This is a MAC-less interface\n"); -+ return -ENODEV; -+ } -+ if (unlikely(priv->mac_dev->phy_dev == NULL)) { -+ netdev_dbg(net_dev, "phy device not initialized\n"); -+ return 0; -+ } -+ -+ _errno = phy_ethtool_gset(priv->mac_dev->phy_dev, et_cmd); -+ if (unlikely(_errno < 0)) -+ netdev_err(net_dev, "phy_ethtool_gset() = %d\n", _errno); -+ -+ return _errno; -+} -+ -+static int __cold dpa_set_settings(struct net_device *net_dev, -+ struct ethtool_cmd *et_cmd) -+{ -+ int _errno; -+ struct dpa_priv_s *priv; -+ -+ priv = netdev_priv(net_dev); -+ -+ if (priv->mac_dev == NULL) { -+ netdev_info(net_dev, "This is a MAC-less interface\n"); -+ return -ENODEV; -+ } -+ if (unlikely(priv->mac_dev->phy_dev == NULL)) { -+ netdev_err(net_dev, "phy device not initialized\n"); -+ return -ENODEV; -+ } -+ -+ _errno = phy_ethtool_sset(priv->mac_dev->phy_dev, et_cmd); -+ if (unlikely(_errno < 0)) -+ netdev_err(net_dev, "phy_ethtool_sset() = %d\n", _errno); -+ -+ return _errno; -+} -+ -+static void __cold dpa_get_drvinfo(struct net_device *net_dev, -+ struct ethtool_drvinfo *drvinfo) -+{ -+ int _errno; -+ -+ strncpy(drvinfo->driver, KBUILD_MODNAME, -+ sizeof(drvinfo->driver) - 1)[sizeof(drvinfo->driver)-1] = 0; -+ _errno = snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), -+ "%X", 0); -+ -+ if (unlikely(_errno >= sizeof(drvinfo->fw_version))) { -+ /* Truncated output */ -+ netdev_notice(net_dev, "snprintf() = %d\n", _errno); -+ } else if (unlikely(_errno < 0)) { -+ netdev_warn(net_dev, "snprintf() = %d\n", _errno); -+ memset(drvinfo->fw_version, 0, sizeof(drvinfo->fw_version)); -+ } -+ strncpy(drvinfo->bus_info, dev_name(net_dev->dev.parent->parent), -+ sizeof(drvinfo->bus_info)-1)[sizeof(drvinfo->bus_info)-1] = 0; -+} -+ -+static uint32_t __cold dpa_get_msglevel(struct net_device *net_dev) -+{ -+ return ((struct dpa_priv_s *)netdev_priv(net_dev))->msg_enable; -+} -+ -+static void __cold dpa_set_msglevel(struct net_device *net_dev, -+ uint32_t msg_enable) -+{ -+ ((struct dpa_priv_s *)netdev_priv(net_dev))->msg_enable = msg_enable; -+} -+ -+static int __cold dpa_nway_reset(struct net_device *net_dev) -+{ -+ int _errno; -+ struct dpa_priv_s *priv; -+ -+ priv = netdev_priv(net_dev); -+ -+ if (priv->mac_dev == NULL) { -+ netdev_info(net_dev, "This is a MAC-less interface\n"); -+ return -ENODEV; -+ } -+ if (unlikely(priv->mac_dev->phy_dev == NULL)) { -+ netdev_err(net_dev, "phy device not initialized\n"); -+ return -ENODEV; -+ } -+ -+ _errno = 0; -+ if (priv->mac_dev->phy_dev->autoneg) { -+ _errno = phy_start_aneg(priv->mac_dev->phy_dev); -+ if (unlikely(_errno < 0)) -+ netdev_err(net_dev, "phy_start_aneg() = %d\n", -+ _errno); -+ } -+ -+ return _errno; -+} -+ -+static void __cold dpa_get_pauseparam(struct net_device *net_dev, -+ struct ethtool_pauseparam *epause) -+{ -+ struct dpa_priv_s *priv; -+ struct mac_device *mac_dev; -+ struct phy_device *phy_dev; -+ -+ priv = netdev_priv(net_dev); -+ mac_dev = priv->mac_dev; -+ -+ if (mac_dev == NULL) { -+ netdev_info(net_dev, "This is a MAC-less interface\n"); -+ return; -+ } -+ -+ phy_dev = mac_dev->phy_dev; -+ if (unlikely(phy_dev == NULL)) { -+ netdev_err(net_dev, "phy device not initialized\n"); -+ return; -+ } -+ -+ epause->autoneg = mac_dev->autoneg_pause; -+ epause->rx_pause = mac_dev->rx_pause_active; -+ epause->tx_pause = mac_dev->tx_pause_active; -+} -+ -+static int __cold dpa_set_pauseparam(struct net_device *net_dev, -+ struct ethtool_pauseparam *epause) -+{ -+ struct dpa_priv_s *priv; -+ struct mac_device *mac_dev; -+ struct phy_device *phy_dev; -+ int _errno; -+ u32 newadv, oldadv; -+ bool rx_pause, tx_pause; -+ -+ priv = netdev_priv(net_dev); -+ mac_dev = priv->mac_dev; -+ -+ if (mac_dev == NULL) { -+ netdev_info(net_dev, "This is a MAC-less interface\n"); -+ return -ENODEV; -+ } -+ -+ phy_dev = mac_dev->phy_dev; -+ if (unlikely(phy_dev == NULL)) { -+ netdev_err(net_dev, "phy device not initialized\n"); -+ return -ENODEV; -+ } -+ -+ if (!(phy_dev->supported & SUPPORTED_Pause) || -+ (!(phy_dev->supported & SUPPORTED_Asym_Pause) && -+ (epause->rx_pause != epause->tx_pause))) -+ return -EINVAL; -+ -+ /* The MAC should know how to handle PAUSE frame autonegotiation before -+ * adjust_link is triggered by a forced renegotiation of sym/asym PAUSE -+ * settings. -+ */ -+ mac_dev->autoneg_pause = !!epause->autoneg; -+ mac_dev->rx_pause_req = !!epause->rx_pause; -+ mac_dev->tx_pause_req = !!epause->tx_pause; -+ -+ /* Determine the sym/asym advertised PAUSE capabilities from the desired -+ * rx/tx pause settings. -+ */ -+ newadv = 0; -+ if (epause->rx_pause) -+ newadv = ADVERTISED_Pause | ADVERTISED_Asym_Pause; -+ if (epause->tx_pause) -+ newadv |= ADVERTISED_Asym_Pause; -+ -+ oldadv = phy_dev->advertising & -+ (ADVERTISED_Pause | ADVERTISED_Asym_Pause); -+ -+ /* If there are differences between the old and the new advertised -+ * values, restart PHY autonegotiation and advertise the new values. -+ */ -+ if (oldadv != newadv) { -+ phy_dev->advertising &= ~(ADVERTISED_Pause -+ | ADVERTISED_Asym_Pause); -+ phy_dev->advertising |= newadv; -+ if (phy_dev->autoneg) { -+ _errno = phy_start_aneg(phy_dev); -+ if (unlikely(_errno < 0)) -+ netdev_err(net_dev, "phy_start_aneg() = %d\n", -+ _errno); -+ } -+ } -+ -+ get_pause_cfg(mac_dev, &rx_pause, &tx_pause); -+ _errno = set_mac_active_pause(mac_dev, rx_pause, tx_pause); -+ if (unlikely(_errno < 0)) -+ netdev_err(net_dev, "set_mac_active_pause() = %d\n", _errno); -+ -+ return _errno; -+} -+ -+#ifdef CONFIG_PM -+static void dpa_get_wol(struct net_device *net_dev, struct ethtool_wolinfo *wol) -+{ -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ -+ wol->supported = 0; -+ wol->wolopts = 0; -+ -+ if (!priv->wol || !device_can_wakeup(net_dev->dev.parent)) -+ return; -+ -+ if (priv->wol & DPAA_WOL_MAGIC) { -+ wol->supported = WAKE_MAGIC; -+ wol->wolopts = WAKE_MAGIC; -+ } -+} -+ -+static int dpa_set_wol(struct net_device *net_dev, struct ethtool_wolinfo *wol) -+{ -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ -+ if (priv->mac_dev == NULL) { -+ netdev_info(net_dev, "This is a MAC-less interface\n"); -+ return -ENODEV; -+ } -+ -+ if (unlikely(priv->mac_dev->phy_dev == NULL)) { -+ netdev_dbg(net_dev, "phy device not initialized\n"); -+ return -ENODEV; -+ } -+ -+ if (!device_can_wakeup(net_dev->dev.parent) || -+ (wol->wolopts & ~WAKE_MAGIC)) -+ return -EOPNOTSUPP; -+ -+ priv->wol = 0; -+ -+ if (wol->wolopts & WAKE_MAGIC) { -+ priv->wol = DPAA_WOL_MAGIC; -+ device_set_wakeup_enable(net_dev->dev.parent, 1); -+ } else { -+ device_set_wakeup_enable(net_dev->dev.parent, 0); -+ } -+ -+ return 0; -+} -+#endif -+ -+static int dpa_get_eee(struct net_device *net_dev, struct ethtool_eee *et_eee) -+{ -+ struct dpa_priv_s *priv; -+ -+ priv = netdev_priv(net_dev); -+ if (priv->mac_dev == NULL) { -+ netdev_info(net_dev, "This is a MAC-less interface\n"); -+ return -ENODEV; -+ } -+ -+ if (unlikely(priv->mac_dev->phy_dev == NULL)) { -+ netdev_err(net_dev, "phy device not initialized\n"); -+ return -ENODEV; -+ } -+ -+ return phy_ethtool_get_eee(priv->mac_dev->phy_dev, et_eee); -+} -+ -+static int dpa_set_eee(struct net_device *net_dev, struct ethtool_eee *et_eee) -+{ -+ struct dpa_priv_s *priv; -+ -+ priv = netdev_priv(net_dev); -+ if (priv->mac_dev == NULL) { -+ netdev_info(net_dev, "This is a MAC-less interface\n"); -+ return -ENODEV; -+ } -+ -+ if (unlikely(priv->mac_dev->phy_dev == NULL)) { -+ netdev_err(net_dev, "phy device not initialized\n"); -+ return -ENODEV; -+ } -+ -+ return phy_ethtool_set_eee(priv->mac_dev->phy_dev, et_eee); -+} -+ -+static int dpa_get_sset_count(struct net_device *net_dev, int type) -+{ -+ unsigned int total_stats, num_stats; -+ -+ num_stats = num_online_cpus() + 1; -+ total_stats = num_stats * DPA_STATS_PERCPU_LEN + DPA_STATS_GLOBAL_LEN; -+ -+ switch (type) { -+ case ETH_SS_STATS: -+ return total_stats; -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+static void copy_stats(struct dpa_percpu_priv_s *percpu_priv, int num_cpus, -+ int crr_cpu, u64 bp_count, u64 *data) -+{ -+ int num_stat_values = num_cpus + 1; -+ int crr_stat = 0; -+ -+ /* update current CPU's stats and also add them to the total values */ -+ data[crr_stat * num_stat_values + crr_cpu] = percpu_priv->in_interrupt; -+ data[crr_stat++ * num_stat_values + num_cpus] += percpu_priv->in_interrupt; -+ -+ data[crr_stat * num_stat_values + crr_cpu] = percpu_priv->stats.rx_packets; -+ data[crr_stat++ * num_stat_values + num_cpus] += percpu_priv->stats.rx_packets; -+ -+ data[crr_stat * num_stat_values + crr_cpu] = percpu_priv->stats.tx_packets; -+ data[crr_stat++ * num_stat_values + num_cpus] += percpu_priv->stats.tx_packets; -+ -+ data[crr_stat * num_stat_values + crr_cpu] = percpu_priv->tx_returned; -+ data[crr_stat++ * num_stat_values + num_cpus] += percpu_priv->tx_returned; -+ -+ data[crr_stat * num_stat_values + crr_cpu] = percpu_priv->tx_confirm; -+ data[crr_stat++ * num_stat_values + num_cpus] += percpu_priv->tx_confirm; -+ -+ data[crr_stat * num_stat_values + crr_cpu] = percpu_priv->tx_frag_skbuffs; -+ data[crr_stat++ * num_stat_values + num_cpus] += percpu_priv->tx_frag_skbuffs; -+ -+ data[crr_stat * num_stat_values + crr_cpu] = percpu_priv->rx_sg; -+ data[crr_stat++ * num_stat_values + num_cpus] += percpu_priv->rx_sg; -+ -+ data[crr_stat * num_stat_values + crr_cpu] = percpu_priv->stats.tx_errors; -+ data[crr_stat++ * num_stat_values + num_cpus] += percpu_priv->stats.tx_errors; -+ -+ data[crr_stat * num_stat_values + crr_cpu] = percpu_priv->stats.rx_errors; -+ data[crr_stat++ * num_stat_values + num_cpus] += percpu_priv->stats.rx_errors; -+ -+ data[crr_stat * num_stat_values + crr_cpu] = bp_count; -+ data[crr_stat++ * num_stat_values + num_cpus] += bp_count; -+} -+ -+static void dpa_get_ethtool_stats(struct net_device *net_dev, -+ struct ethtool_stats *stats, u64 *data) -+{ -+ u64 bp_count, cg_time, cg_num, cg_status; -+ struct dpa_percpu_priv_s *percpu_priv; -+ struct qm_mcr_querycgr query_cgr; -+ struct dpa_rx_errors rx_errors; -+ struct dpa_ern_cnt ern_cnt; -+ struct dpa_priv_s *priv; -+ unsigned int num_cpus, offset; -+ struct dpa_bp *dpa_bp; -+ int total_stats, i; -+ -+ total_stats = dpa_get_sset_count(net_dev, ETH_SS_STATS); -+ priv = netdev_priv(net_dev); -+ dpa_bp = priv->dpa_bp; -+ num_cpus = num_online_cpus(); -+ bp_count = 0; -+ -+ memset(&rx_errors, 0, sizeof(struct dpa_rx_errors)); -+ memset(&ern_cnt, 0, sizeof(struct dpa_ern_cnt)); -+ memset(data, 0, total_stats * sizeof(u64)); -+ -+ for_each_online_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ -+ if (dpa_bp->percpu_count) -+ bp_count = *(per_cpu_ptr(dpa_bp->percpu_count, i)); -+ -+ rx_errors.dme += percpu_priv->rx_errors.dme; -+ rx_errors.fpe += percpu_priv->rx_errors.fpe; -+ rx_errors.fse += percpu_priv->rx_errors.fse; -+ rx_errors.phe += percpu_priv->rx_errors.phe; -+ rx_errors.cse += percpu_priv->rx_errors.cse; -+ -+ ern_cnt.cg_tdrop += percpu_priv->ern_cnt.cg_tdrop; -+ ern_cnt.wred += percpu_priv->ern_cnt.wred; -+ ern_cnt.err_cond += percpu_priv->ern_cnt.err_cond; -+ ern_cnt.early_window += percpu_priv->ern_cnt.early_window; -+ ern_cnt.late_window += percpu_priv->ern_cnt.late_window; -+ ern_cnt.fq_tdrop += percpu_priv->ern_cnt.fq_tdrop; -+ ern_cnt.fq_retired += percpu_priv->ern_cnt.fq_retired; -+ ern_cnt.orp_zero += percpu_priv->ern_cnt.orp_zero; -+ -+ copy_stats(percpu_priv, num_cpus, i, bp_count, data); -+ } -+ -+ offset = (num_cpus + 1) * DPA_STATS_PERCPU_LEN; -+ memcpy(data + offset, &rx_errors, sizeof(struct dpa_rx_errors)); -+ -+ offset += sizeof(struct dpa_rx_errors) / sizeof(u64); -+ memcpy(data + offset, &ern_cnt, sizeof(struct dpa_ern_cnt)); -+ -+ /* gather congestion related counters */ -+ cg_num = 0; -+ cg_status = 0; -+ cg_time = jiffies_to_msecs(priv->cgr_data.congested_jiffies); -+ if (qman_query_cgr(&priv->cgr_data.cgr, &query_cgr) == 0) { -+ cg_num = priv->cgr_data.cgr_congested_count; -+ cg_status = query_cgr.cgr.cs; -+ -+ /* reset congestion stats (like QMan API does */ -+ priv->cgr_data.congested_jiffies = 0; -+ priv->cgr_data.cgr_congested_count = 0; -+ } -+ -+ offset += sizeof(struct dpa_ern_cnt) / sizeof(u64); -+ data[offset++] = cg_time; -+ data[offset++] = cg_num; -+ data[offset++] = cg_status; -+} -+ -+static void dpa_get_strings(struct net_device *net_dev, u32 stringset, u8 *data) -+{ -+ unsigned int i, j, num_cpus, size; -+ char stat_string_cpu[ETH_GSTRING_LEN]; -+ u8 *strings; -+ -+ strings = data; -+ num_cpus = num_online_cpus(); -+ size = DPA_STATS_GLOBAL_LEN * ETH_GSTRING_LEN; -+ -+ for (i = 0; i < DPA_STATS_PERCPU_LEN; i++) { -+ for (j = 0; j < num_cpus; j++) { -+ snprintf(stat_string_cpu, ETH_GSTRING_LEN, "%s [CPU %d]", dpa_stats_percpu[i], j); -+ memcpy(strings, stat_string_cpu, ETH_GSTRING_LEN); -+ strings += ETH_GSTRING_LEN; -+ } -+ snprintf(stat_string_cpu, ETH_GSTRING_LEN, "%s [TOTAL]", dpa_stats_percpu[i]); -+ memcpy(strings, stat_string_cpu, ETH_GSTRING_LEN); -+ strings += ETH_GSTRING_LEN; -+ } -+ memcpy(strings, dpa_stats_global, size); -+} -+ -+const struct ethtool_ops dpa_ethtool_ops = { -+ .get_settings = dpa_get_settings, -+ .set_settings = dpa_set_settings, -+ .get_drvinfo = dpa_get_drvinfo, -+ .get_msglevel = dpa_get_msglevel, -+ .set_msglevel = dpa_set_msglevel, -+ .nway_reset = dpa_nway_reset, -+ .get_pauseparam = dpa_get_pauseparam, -+ .set_pauseparam = dpa_set_pauseparam, -+ .self_test = NULL, /* TODO invoke the cold-boot unit-test? */ -+ .get_link = ethtool_op_get_link, -+ .get_eee = dpa_get_eee, -+ .set_eee = dpa_set_eee, -+ .get_sset_count = dpa_get_sset_count, -+ .get_ethtool_stats = dpa_get_ethtool_stats, -+ .get_strings = dpa_get_strings, -+#ifdef CONFIG_PM -+ .get_wol = dpa_get_wol, -+ .set_wol = dpa_set_wol, -+#endif -+}; ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_generic_ethtool.c -@@ -0,0 +1,286 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifdef CONFIG_FSL_DPAA_ETH_DEBUG -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": %s:%hu:%s() " fmt, \ -+ KBUILD_BASENAME".c", __LINE__, __func__ -+#else -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": " fmt -+#endif -+ -+#include -+ -+#include "dpaa_eth.h" -+#include "dpaa_eth_common.h" -+#include "dpaa_eth_generic.h" -+ -+static const char dpa_stats_percpu[][ETH_GSTRING_LEN] = { -+ "interrupts", -+ "rx packets", -+ "tx packets", -+ "tx recycled", -+ "tx confirm", -+ "tx S/G", -+ "rx S/G (N/A)", -+ "tx error", -+ "rx error", -+ "bp count", -+ "bp draining count" -+}; -+ -+static char dpa_stats_global[][ETH_GSTRING_LEN] = { -+ /* dpa rx errors */ -+ "rx dma error", -+ "rx frame physical error", -+ "rx frame size error", -+ "rx header error", -+ "rx csum error", -+ -+ /* demultiplexing errors */ -+ "qman cg_tdrop", -+ "qman wred", -+ "qman error cond", -+ "qman early window", -+ "qman late window", -+ "qman fq tdrop", -+ "qman fq retired", -+ "qman orp disabled", -+}; -+ -+#define DPA_STATS_PERCPU_LEN ARRAY_SIZE(dpa_stats_percpu) -+#define DPA_STATS_GLOBAL_LEN ARRAY_SIZE(dpa_stats_global) -+ -+static int __cold dpa_generic_get_settings(struct net_device *net_dev, -+ struct ethtool_cmd *et_cmd) -+{ -+ netdev_info(net_dev, "This interface does not have a MAC device in its control\n"); -+ return -ENODEV; -+} -+ -+static int __cold dpa_generic_set_settings(struct net_device *net_dev, -+ struct ethtool_cmd *et_cmd) -+{ -+ netdev_info(net_dev, "This interface does not have a MAC device in its control\n"); -+ return -ENODEV; -+} -+ -+static void __cold dpa_generic_get_drvinfo(struct net_device *net_dev, -+ struct ethtool_drvinfo *drvinfo) -+{ -+ int _errno; -+ -+ strncpy(drvinfo->driver, KBUILD_MODNAME, -+ sizeof(drvinfo->driver) - 1)[sizeof(drvinfo->driver)-1] = 0; -+ _errno = snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), -+ "%X", 0); -+ -+ if (unlikely(_errno >= sizeof(drvinfo->fw_version))) { -+ /* Truncated output */ -+ netdev_notice(net_dev, "snprintf() = %d\n", _errno); -+ } else if (unlikely(_errno < 0)) { -+ netdev_warn(net_dev, "snprintf() = %d\n", _errno); -+ memset(drvinfo->fw_version, 0, sizeof(drvinfo->fw_version)); -+ } -+ strncpy(drvinfo->bus_info, dev_name(net_dev->dev.parent->parent), -+ sizeof(drvinfo->bus_info)-1)[sizeof(drvinfo->bus_info)-1] = 0; -+} -+ -+static uint32_t __cold dpa_generic_get_msglevel(struct net_device *net_dev) -+{ -+ return ((struct dpa_generic_priv_s *)netdev_priv(net_dev))->msg_enable; -+} -+ -+static void __cold dpa_generic_set_msglevel(struct net_device *net_dev, -+ uint32_t msg_enable) -+{ -+ ((struct dpa_generic_priv_s *)netdev_priv(net_dev))->msg_enable = -+ msg_enable; -+} -+ -+static int __cold dpa_generic_nway_reset(struct net_device *net_dev) -+{ -+ netdev_info(net_dev, "This interface does not have a MAC device in its control\n"); -+ return -ENODEV; -+} -+ -+static int dpa_generic_get_sset_count(struct net_device *net_dev, int type) -+{ -+ unsigned int total_stats, num_stats; -+ -+ num_stats = num_online_cpus() + 1; -+ total_stats = num_stats * DPA_STATS_PERCPU_LEN + DPA_STATS_GLOBAL_LEN; -+ -+ switch (type) { -+ case ETH_SS_STATS: -+ return total_stats; -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+static void copy_stats(struct dpa_percpu_priv_s *percpu_priv, -+ int num_cpus, int crr_cpu, u64 bp_count, -+ u64 bp_drain_count, u64 *data) -+{ -+ int num_values = num_cpus + 1; -+ int crr = 0; -+ -+ /* update current CPU's stats and also add them to the total values */ -+ data[crr * num_values + crr_cpu] = percpu_priv->in_interrupt; -+ data[crr++ * num_values + num_cpus] += percpu_priv->in_interrupt; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->stats.rx_packets; -+ data[crr++ * num_values + num_cpus] += percpu_priv->stats.rx_packets; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->stats.tx_packets; -+ data[crr++ * num_values + num_cpus] += percpu_priv->stats.tx_packets; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->tx_returned; -+ data[crr++ * num_values + num_cpus] += percpu_priv->tx_returned; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->tx_confirm; -+ data[crr++ * num_values + num_cpus] += percpu_priv->tx_confirm; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->tx_frag_skbuffs; -+ data[crr++ * num_values + num_cpus] += percpu_priv->tx_frag_skbuffs; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->stats.tx_errors; -+ data[crr++ * num_values + num_cpus] += percpu_priv->stats.tx_errors; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->stats.rx_errors; -+ data[crr++ * num_values + num_cpus] += percpu_priv->stats.rx_errors; -+ -+ data[crr * num_values + crr_cpu] = bp_count; -+ data[crr++ * num_values + num_cpus] += bp_count; -+ -+ data[crr * num_values + crr_cpu] = bp_drain_count; -+ data[crr++ * num_values + num_cpus] += bp_drain_count; -+} -+ -+static void dpa_generic_get_ethtool_stats(struct net_device *net_dev, -+ struct ethtool_stats *stats, -+ u64 *data) -+{ -+ struct dpa_percpu_priv_s *percpu_priv; -+ struct dpa_bp *dpa_bp, *drain_bp; -+ struct dpa_generic_priv_s *priv; -+ struct dpa_rx_errors rx_errors; -+ struct dpa_ern_cnt ern_cnt; -+ unsigned int num_cpus, offset; -+ u64 bp_cnt, drain_cnt; -+ int total_stats, i; -+ -+ total_stats = dpa_generic_get_sset_count(net_dev, ETH_SS_STATS); -+ priv = netdev_priv(net_dev); -+ drain_bp = priv->draining_tx_bp; -+ dpa_bp = priv->rx_bp; -+ num_cpus = num_online_cpus(); -+ drain_cnt = 0; -+ bp_cnt = 0; -+ -+ memset(&rx_errors, 0, sizeof(struct dpa_rx_errors)); -+ memset(&ern_cnt, 0, sizeof(struct dpa_ern_cnt)); -+ memset(data, 0, total_stats * sizeof(u64)); -+ -+ for_each_online_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ -+ if (dpa_bp->percpu_count) -+ bp_cnt = *(per_cpu_ptr(dpa_bp->percpu_count, i)); -+ -+ if (drain_bp->percpu_count) -+ drain_cnt = *(per_cpu_ptr(drain_bp->percpu_count, i)); -+ -+ rx_errors.dme += percpu_priv->rx_errors.dme; -+ rx_errors.fpe += percpu_priv->rx_errors.fpe; -+ rx_errors.fse += percpu_priv->rx_errors.fse; -+ rx_errors.phe += percpu_priv->rx_errors.phe; -+ rx_errors.cse += percpu_priv->rx_errors.cse; -+ -+ ern_cnt.cg_tdrop += percpu_priv->ern_cnt.cg_tdrop; -+ ern_cnt.wred += percpu_priv->ern_cnt.wred; -+ ern_cnt.err_cond += percpu_priv->ern_cnt.err_cond; -+ ern_cnt.early_window += percpu_priv->ern_cnt.early_window; -+ ern_cnt.late_window += percpu_priv->ern_cnt.late_window; -+ ern_cnt.fq_tdrop += percpu_priv->ern_cnt.fq_tdrop; -+ ern_cnt.fq_retired += percpu_priv->ern_cnt.fq_retired; -+ ern_cnt.orp_zero += percpu_priv->ern_cnt.orp_zero; -+ -+ copy_stats(percpu_priv, num_cpus, i, bp_cnt, drain_cnt, data); -+ } -+ -+ offset = (num_cpus + 1) * DPA_STATS_PERCPU_LEN; -+ memcpy(data + offset, &rx_errors, sizeof(struct dpa_rx_errors)); -+ -+ offset += sizeof(struct dpa_rx_errors) / sizeof(u64); -+ memcpy(data + offset, &ern_cnt, sizeof(struct dpa_ern_cnt)); -+} -+ -+static void dpa_generic_get_strings(struct net_device *net_dev, -+ u32 stringset, u8 *data) -+{ -+ unsigned int i, j, num_cpus, size; -+ char string_cpu[ETH_GSTRING_LEN]; -+ u8 *strings; -+ -+ strings = data; -+ num_cpus = num_online_cpus(); -+ size = DPA_STATS_GLOBAL_LEN * ETH_GSTRING_LEN; -+ -+ for (i = 0; i < DPA_STATS_PERCPU_LEN; i++) { -+ for (j = 0; j < num_cpus; j++) { -+ snprintf(string_cpu, ETH_GSTRING_LEN, "%s [CPU %d]", -+ dpa_stats_percpu[i], j); -+ memcpy(strings, string_cpu, ETH_GSTRING_LEN); -+ strings += ETH_GSTRING_LEN; -+ } -+ snprintf(string_cpu, ETH_GSTRING_LEN, "%s [TOTAL]", -+ dpa_stats_percpu[i]); -+ memcpy(strings, string_cpu, ETH_GSTRING_LEN); -+ strings += ETH_GSTRING_LEN; -+ } -+ memcpy(strings, dpa_stats_global, size); -+} -+ -+const struct ethtool_ops dpa_generic_ethtool_ops = { -+ .get_settings = dpa_generic_get_settings, -+ .set_settings = dpa_generic_set_settings, -+ .get_drvinfo = dpa_generic_get_drvinfo, -+ .get_msglevel = dpa_generic_get_msglevel, -+ .set_msglevel = dpa_generic_set_msglevel, -+ .nway_reset = dpa_generic_nway_reset, -+ .get_link = ethtool_op_get_link, -+ .get_sset_count = dpa_generic_get_sset_count, -+ .get_ethtool_stats = dpa_generic_get_ethtool_stats, -+ .get_strings = dpa_generic_get_strings, -+}; ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_macsec_ethtool.c -@@ -0,0 +1,250 @@ -+/* Copyright 2015 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+ -+#include "dpaa_eth.h" -+#include "dpaa_eth_macsec.h" -+ -+static const char dpa_macsec_stats_percpu[][ETH_GSTRING_LEN] = { -+ "interrupts", -+ "rx packets", -+ "tx packets", -+ "tx recycled", -+ "tx confirm", -+ "tx S/G", -+ "rx S/G", -+ "tx error", -+ "rx error", -+ "bp count", -+ "tx macsec", -+ "rx macsec" -+}; -+ -+static char dpa_macsec_stats_global[][ETH_GSTRING_LEN] = { -+ /* dpa rx errors */ -+ "rx dma error", -+ "rx frame physical error", -+ "rx frame size error", -+ "rx header error", -+ "rx csum error", -+ -+ /* demultiplexing errors */ -+ "qman cg_tdrop", -+ "qman wred", -+ "qman error cond", -+ "qman early window", -+ "qman late window", -+ "qman fq tdrop", -+ "qman fq retired", -+ "qman orp disabled", -+ -+ /* congestion related stats */ -+ "congestion time (ms)", -+ "entered congestion", -+ "congested (0/1)" -+}; -+ -+#define DPA_MACSEC_STATS_PERCPU_LEN ARRAY_SIZE(dpa_macsec_stats_percpu) -+#define DPA_MACSEC_STATS_GLOBAL_LEN ARRAY_SIZE(dpa_macsec_stats_global) -+ -+static void copy_stats(struct dpa_percpu_priv_s *percpu_priv, int num_cpus, -+ int crr_cpu, u64 bp_count, u64 tx_macsec, -+ u64 rx_macsec, u64 *data) -+{ -+ int num_values = num_cpus + 1; -+ int crr = 0; -+ -+ /* update current CPU's stats and also add them to the total values */ -+ data[crr * num_values + crr_cpu] = percpu_priv->in_interrupt; -+ data[crr++ * num_values + num_cpus] += percpu_priv->in_interrupt; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->stats.rx_packets; -+ data[crr++ * num_values + num_cpus] += percpu_priv->stats.rx_packets; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->stats.tx_packets; -+ data[crr++ * num_values + num_cpus] += percpu_priv->stats.tx_packets; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->tx_returned; -+ data[crr++ * num_values + num_cpus] += percpu_priv->tx_returned; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->tx_confirm; -+ data[crr++ * num_values + num_cpus] += percpu_priv->tx_confirm; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->tx_frag_skbuffs; -+ data[crr++ * num_values + num_cpus] += percpu_priv->tx_frag_skbuffs; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->rx_sg; -+ data[crr++ * num_values + num_cpus] += percpu_priv->rx_sg; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->stats.tx_errors; -+ data[crr++ * num_values + num_cpus] += percpu_priv->stats.tx_errors; -+ -+ data[crr * num_values + crr_cpu] = percpu_priv->stats.rx_errors; -+ data[crr++ * num_values + num_cpus] += percpu_priv->stats.rx_errors; -+ -+ data[crr * num_values + crr_cpu] = bp_count; -+ data[crr++ * num_values + num_cpus] += bp_count; -+ -+ data[crr * num_values + crr_cpu] = tx_macsec; -+ data[crr++ * num_values + num_cpus] += tx_macsec; -+ -+ data[crr * num_values + crr_cpu] = rx_macsec; -+ data[crr++ * num_values + num_cpus] += rx_macsec; -+} -+ -+int dpa_macsec_get_sset_count(struct net_device *net_dev, int type) -+{ -+ unsigned int total_stats, num_stats; -+ -+ num_stats = num_online_cpus() + 1; -+ total_stats = num_stats * DPA_MACSEC_STATS_PERCPU_LEN + -+ DPA_MACSEC_STATS_GLOBAL_LEN; -+ -+ switch (type) { -+ case ETH_SS_STATS: -+ return total_stats; -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+void dpa_macsec_get_ethtool_stats(struct net_device *net_dev, -+ struct ethtool_stats *stats, u64 *data) -+{ -+ u64 bp_count, bp_total, cg_time, cg_num, cg_status; -+ struct macsec_percpu_priv_s *percpu_priv_macsec; -+ struct dpa_percpu_priv_s *percpu_priv; -+ struct macsec_priv_s *macsec_priv; -+ struct qm_mcr_querycgr query_cgr; -+ struct dpa_rx_errors rx_errors; -+ struct dpa_ern_cnt ern_cnt; -+ struct dpa_priv_s *priv; -+ unsigned int num_cpus, offset; -+ struct dpa_bp *dpa_bp; -+ int total_stats, i; -+ -+ macsec_priv = dpa_macsec_get_priv(net_dev); -+ if (unlikely(!macsec_priv)) { -+ pr_err("selected macsec_priv is NULL\n"); -+ return; -+ } -+ -+ total_stats = dpa_macsec_get_sset_count(net_dev, ETH_SS_STATS); -+ priv = netdev_priv(net_dev); -+ dpa_bp = priv->dpa_bp; -+ num_cpus = num_online_cpus(); -+ bp_count = 0; -+ bp_total = 0; -+ -+ memset(&rx_errors, 0, sizeof(struct dpa_rx_errors)); -+ memset(&ern_cnt, 0, sizeof(struct dpa_ern_cnt)); -+ memset(data, 0, total_stats * sizeof(u64)); -+ -+ for_each_online_cpu(i) { -+ percpu_priv = per_cpu_ptr(priv->percpu_priv, i); -+ percpu_priv_macsec = per_cpu_ptr(macsec_priv->percpu_priv, i); -+ -+ if (dpa_bp->percpu_count) -+ bp_count = *(per_cpu_ptr(dpa_bp->percpu_count, i)); -+ -+ rx_errors.dme += percpu_priv->rx_errors.dme; -+ rx_errors.fpe += percpu_priv->rx_errors.fpe; -+ rx_errors.fse += percpu_priv->rx_errors.fse; -+ rx_errors.phe += percpu_priv->rx_errors.phe; -+ rx_errors.cse += percpu_priv->rx_errors.cse; -+ -+ ern_cnt.cg_tdrop += percpu_priv->ern_cnt.cg_tdrop; -+ ern_cnt.wred += percpu_priv->ern_cnt.wred; -+ ern_cnt.err_cond += percpu_priv->ern_cnt.err_cond; -+ ern_cnt.early_window += percpu_priv->ern_cnt.early_window; -+ ern_cnt.late_window += percpu_priv->ern_cnt.late_window; -+ ern_cnt.fq_tdrop += percpu_priv->ern_cnt.fq_tdrop; -+ ern_cnt.fq_retired += percpu_priv->ern_cnt.fq_retired; -+ ern_cnt.orp_zero += percpu_priv->ern_cnt.orp_zero; -+ -+ copy_stats(percpu_priv, num_cpus, i, bp_count, -+ percpu_priv_macsec->tx_macsec, -+ percpu_priv_macsec->rx_macsec, -+ data); -+ } -+ -+ offset = (num_cpus + 1) * DPA_MACSEC_STATS_PERCPU_LEN; -+ memcpy(data + offset, &rx_errors, sizeof(struct dpa_rx_errors)); -+ -+ offset += sizeof(struct dpa_rx_errors) / sizeof(u64); -+ memcpy(data + offset, &ern_cnt, sizeof(struct dpa_ern_cnt)); -+ -+ /* gather congestion related counters */ -+ cg_num = 0; -+ cg_status = 0; -+ cg_time = jiffies_to_msecs(priv->cgr_data.congested_jiffies); -+ if (qman_query_cgr(&priv->cgr_data.cgr, &query_cgr) == 0) { -+ cg_num = priv->cgr_data.cgr_congested_count; -+ cg_status = query_cgr.cgr.cs; -+ -+ /* reset congestion stats (like QMan API does */ -+ priv->cgr_data.congested_jiffies = 0; -+ priv->cgr_data.cgr_congested_count = 0; -+ } -+ -+ offset += sizeof(struct dpa_ern_cnt) / sizeof(u64); -+ data[offset++] = cg_time; -+ data[offset++] = cg_num; -+ data[offset++] = cg_status; -+} -+ -+void dpa_macsec_get_strings(struct net_device *net_dev, -+ u32 stringset, u8 *data) -+{ -+ unsigned int i, j, num_cpus, size; -+ char string_cpu[ETH_GSTRING_LEN]; -+ u8 *strings; -+ -+ strings = data; -+ num_cpus = num_online_cpus(); -+ size = DPA_MACSEC_STATS_GLOBAL_LEN * ETH_GSTRING_LEN; -+ -+ for (i = 0; i < DPA_MACSEC_STATS_PERCPU_LEN; i++) { -+ for (j = 0; j < num_cpus; j++) { -+ snprintf(string_cpu, ETH_GSTRING_LEN, "%s [CPU %d]", -+ dpa_macsec_stats_percpu[i], j); -+ memcpy(strings, string_cpu, ETH_GSTRING_LEN); -+ strings += ETH_GSTRING_LEN; -+ } -+ snprintf(string_cpu, ETH_GSTRING_LEN, "%s [TOTAL]", -+ dpa_macsec_stats_percpu[i]); -+ memcpy(strings, string_cpu, ETH_GSTRING_LEN); -+ strings += ETH_GSTRING_LEN; -+ } -+ memcpy(strings, dpa_macsec_stats_global, size); -+} -+ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_ptp.c -@@ -0,0 +1,287 @@ -+/* -+ * DPAA Ethernet Driver -- PTP 1588 clock using the dTSEC -+ * -+ * Author: Yangbo Lu -+ * -+ * Copyright 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+*/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "dpaa_eth.h" -+#include "mac.h" -+ -+struct ptp_clock *clock; -+ -+static struct mac_device *mac_dev; -+static u32 freqCompensation; -+ -+/* Bit definitions for the TMR_CTRL register */ -+#define ALM1P (1<<31) /* Alarm1 output polarity */ -+#define ALM2P (1<<30) /* Alarm2 output polarity */ -+#define FS (1<<28) /* FIPER start indication */ -+#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */ -+#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */ -+#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */ -+#define TCLK_PERIOD_MASK (0x3ff) -+#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */ -+#define FRD (1<<14) /* FIPER Realignment Disable */ -+#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */ -+#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */ -+#define ETEP2 (1<<9) /* External trigger 2 edge polarity */ -+#define ETEP1 (1<<8) /* External trigger 1 edge polarity */ -+#define COPH (1<<7) /* Generated clock output phase. */ -+#define CIPH (1<<6) /* External oscillator input clock phase */ -+#define TMSR (1<<5) /* Timer soft reset. */ -+#define BYP (1<<3) /* Bypass drift compensated clock */ -+#define TE (1<<2) /* 1588 timer enable. */ -+#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */ -+#define CKSEL_MASK (0x3) -+ -+/* Bit definitions for the TMR_TEVENT register */ -+#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */ -+#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */ -+#define ALM2 (1<<17) /* Current time = alarm time register 2 */ -+#define ALM1 (1<<16) /* Current time = alarm time register 1 */ -+#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */ -+#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */ -+#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */ -+ -+/* Bit definitions for the TMR_TEMASK register */ -+#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */ -+#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */ -+#define ALM2EN (1<<17) /* Timer ALM2 event enable */ -+#define ALM1EN (1<<16) /* Timer ALM1 event enable */ -+#define PP1EN (1<<7) /* Periodic pulse event 1 enable */ -+#define PP2EN (1<<6) /* Periodic pulse event 2 enable */ -+ -+/* Bit definitions for the TMR_PEVENT register */ -+#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */ -+#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */ -+#define RXP (1<<0) /* PTP frame has been received */ -+ -+/* Bit definitions for the TMR_PEMASK register */ -+#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */ -+#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */ -+#define RXPEN (1<<0) /* Receive PTP packet event enable */ -+ -+/* Bit definitions for the TMR_STAT register */ -+#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */ -+#define STAT_VEC_MASK (0x3f) -+ -+/* Bit definitions for the TMR_PRSC register */ -+#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */ -+#define PRSC_OCK_MASK (0xffff) -+ -+ -+#define N_EXT_TS 2 -+ -+static void set_alarm(void) -+{ -+ u64 ns; -+ -+ if (mac_dev->fm_rtc_get_cnt) -+ mac_dev->fm_rtc_get_cnt(mac_dev->fm_dev, &ns); -+ ns += 1500000000ULL; -+ ns = div_u64(ns, 1000000000UL) * 1000000000ULL; -+ ns -= DPA_PTP_NOMINAL_FREQ_PERIOD_NS; -+ if (mac_dev->fm_rtc_set_alarm) -+ mac_dev->fm_rtc_set_alarm(mac_dev->fm_dev, 0, ns); -+} -+ -+static void set_fipers(void) -+{ -+ u64 fiper; -+ -+ if (mac_dev->fm_rtc_disable) -+ mac_dev->fm_rtc_disable(mac_dev->fm_dev); -+ -+ set_alarm(); -+ fiper = 1000000000ULL - DPA_PTP_NOMINAL_FREQ_PERIOD_NS; -+ if (mac_dev->fm_rtc_set_fiper) -+ mac_dev->fm_rtc_set_fiper(mac_dev->fm_dev, 0, fiper); -+ -+ if (mac_dev->fm_rtc_enable) -+ mac_dev->fm_rtc_enable(mac_dev->fm_dev); -+} -+ -+/* PTP clock operations */ -+ -+static int ptp_dpa_adjfreq(struct ptp_clock_info *ptp, s32 ppb) -+{ -+ u64 adj; -+ u32 diff, tmr_add; -+ int neg_adj = 0; -+ -+ if (ppb < 0) { -+ neg_adj = 1; -+ ppb = -ppb; -+ } -+ -+ tmr_add = freqCompensation; -+ adj = tmr_add; -+ adj *= ppb; -+ diff = div_u64(adj, 1000000000ULL); -+ -+ tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff; -+ -+ if (mac_dev->fm_rtc_set_drift) -+ mac_dev->fm_rtc_set_drift(mac_dev->fm_dev, tmr_add); -+ -+ return 0; -+} -+ -+static int ptp_dpa_adjtime(struct ptp_clock_info *ptp, s64 delta) -+{ -+ s64 now; -+ -+ if (mac_dev->fm_rtc_get_cnt) -+ mac_dev->fm_rtc_get_cnt(mac_dev->fm_dev, &now); -+ -+ now += delta; -+ -+ if (mac_dev->fm_rtc_set_cnt) -+ mac_dev->fm_rtc_set_cnt(mac_dev->fm_dev, now); -+ set_fipers(); -+ -+ return 0; -+} -+ -+static int ptp_dpa_gettime(struct ptp_clock_info *ptp, struct timespec *ts) -+{ -+ u64 ns; -+ u32 remainder; -+ -+ if (mac_dev->fm_rtc_get_cnt) -+ mac_dev->fm_rtc_get_cnt(mac_dev->fm_dev, &ns); -+ -+ ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder); -+ ts->tv_nsec = remainder; -+ return 0; -+} -+ -+static int ptp_dpa_settime(struct ptp_clock_info *ptp, -+ const struct timespec *ts) -+{ -+ u64 ns; -+ -+ ns = ts->tv_sec * 1000000000ULL; -+ ns += ts->tv_nsec; -+ -+ if (mac_dev->fm_rtc_set_cnt) -+ mac_dev->fm_rtc_set_cnt(mac_dev->fm_dev, ns); -+ set_fipers(); -+ return 0; -+} -+ -+static int ptp_dpa_enable(struct ptp_clock_info *ptp, -+ struct ptp_clock_request *rq, int on) -+{ -+ u32 bit; -+ -+ switch (rq->type) { -+ case PTP_CLK_REQ_EXTTS: -+ switch (rq->extts.index) { -+ case 0: -+ bit = ETS1EN; -+ break; -+ case 1: -+ bit = ETS2EN; -+ break; -+ default: -+ return -EINVAL; -+ } -+ if (on) { -+ if (mac_dev->fm_rtc_enable_interrupt) -+ mac_dev->fm_rtc_enable_interrupt( -+ mac_dev->fm_dev, bit); -+ } else { -+ if (mac_dev->fm_rtc_disable_interrupt) -+ mac_dev->fm_rtc_disable_interrupt( -+ mac_dev->fm_dev, bit); -+ } -+ return 0; -+ -+ case PTP_CLK_REQ_PPS: -+ if (on) { -+ if (mac_dev->fm_rtc_enable_interrupt) -+ mac_dev->fm_rtc_enable_interrupt( -+ mac_dev->fm_dev, PP1EN); -+ } else { -+ if (mac_dev->fm_rtc_disable_interrupt) -+ mac_dev->fm_rtc_disable_interrupt( -+ mac_dev->fm_dev, PP1EN); -+ } -+ return 0; -+ -+ default: -+ break; -+ } -+ -+ return -EOPNOTSUPP; -+} -+ -+static struct ptp_clock_info ptp_dpa_caps = { -+ .owner = THIS_MODULE, -+ .name = "dpaa clock", -+ .max_adj = 512000, -+ .n_alarm = 0, -+ .n_ext_ts = N_EXT_TS, -+ .n_per_out = 0, -+ .pps = 1, -+ .adjfreq = ptp_dpa_adjfreq, -+ .adjtime = ptp_dpa_adjtime, -+ .gettime = ptp_dpa_gettime, -+ .settime = ptp_dpa_settime, -+ .enable = ptp_dpa_enable, -+}; -+ -+static int __init __cold dpa_ptp_load(void) -+{ -+ struct device *ptp_dev; -+ struct timespec now; -+ int dpa_phc_index; -+ int err; -+ -+ ptp_dev = &ptp_priv.of_dev->dev; -+ mac_dev = ptp_priv.mac_dev; -+ -+ if (mac_dev->fm_rtc_get_drift) -+ mac_dev->fm_rtc_get_drift(mac_dev->fm_dev, &freqCompensation); -+ -+ getnstimeofday(&now); -+ ptp_dpa_settime(&ptp_dpa_caps, &now); -+ -+ clock = ptp_clock_register(&ptp_dpa_caps, ptp_dev); -+ if (IS_ERR(clock)) { -+ err = PTR_ERR(clock); -+ return err; -+ } -+ dpa_phc_index = ptp_clock_index(clock); -+ return 0; -+} -+module_init(dpa_ptp_load); -+ -+static void __exit __cold dpa_ptp_unload(void) -+{ -+ if (mac_dev->fm_rtc_disable_interrupt) -+ mac_dev->fm_rtc_disable_interrupt(mac_dev->fm_dev, 0xffffffff); -+ ptp_clock_unregister(clock); -+} -+module_exit(dpa_ptp_unload); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac-api.c -@@ -0,0 +1,915 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifdef CONFIG_FSL_DPAA_ETH_DEBUG -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": %s:%hu:%s() " fmt, \ -+ KBUILD_BASENAME".c", __LINE__, __func__ -+#else -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": " fmt -+#endif -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dpaa_eth.h" -+#include "mac.h" -+#include "lnxwrp_fsl_fman.h" -+ -+#include "error_ext.h" /* GET_ERROR_TYPE, E_OK */ -+ -+#include "fsl_fman_dtsec.h" -+#include "fsl_fman_tgec.h" -+#include "fsl_fman_memac.h" -+#include "../sdk_fman/src/wrapper/lnxwrp_sysfs_fm.h" -+ -+#define MAC_DESCRIPTION "FSL FMan MAC API based driver" -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+ -+MODULE_AUTHOR("Emil Medve "); -+ -+MODULE_DESCRIPTION(MAC_DESCRIPTION); -+ -+struct mac_priv_s { -+ struct fm_mac_dev *fm_mac; -+}; -+ -+const char *mac_driver_description __initconst = MAC_DESCRIPTION; -+const size_t mac_sizeof_priv[] = { -+ [DTSEC] = sizeof(struct mac_priv_s), -+ [XGMAC] = sizeof(struct mac_priv_s), -+ [MEMAC] = sizeof(struct mac_priv_s) -+}; -+ -+static const enet_mode_t _100[] = { -+ [PHY_INTERFACE_MODE_MII] = e_ENET_MODE_MII_100, -+ [PHY_INTERFACE_MODE_RMII] = e_ENET_MODE_RMII_100 -+}; -+ -+static const enet_mode_t _1000[] = { -+ [PHY_INTERFACE_MODE_GMII] = e_ENET_MODE_GMII_1000, -+ [PHY_INTERFACE_MODE_SGMII] = e_ENET_MODE_SGMII_1000, -+ [PHY_INTERFACE_MODE_QSGMII] = e_ENET_MODE_QSGMII_1000, -+ [PHY_INTERFACE_MODE_TBI] = e_ENET_MODE_TBI_1000, -+ [PHY_INTERFACE_MODE_RGMII] = e_ENET_MODE_RGMII_1000, -+ [PHY_INTERFACE_MODE_RGMII_ID] = e_ENET_MODE_RGMII_1000, -+ [PHY_INTERFACE_MODE_RGMII_RXID] = e_ENET_MODE_RGMII_1000, -+ [PHY_INTERFACE_MODE_RGMII_TXID] = e_ENET_MODE_RGMII_1000, -+ [PHY_INTERFACE_MODE_RTBI] = e_ENET_MODE_RTBI_1000 -+}; -+ -+static enet_mode_t __cold __attribute__((nonnull)) -+macdev2enetinterface(const struct mac_device *mac_dev) -+{ -+ switch (mac_dev->max_speed) { -+ case SPEED_100: -+ return _100[mac_dev->phy_if]; -+ case SPEED_1000: -+ return _1000[mac_dev->phy_if]; -+ case SPEED_2500: -+ return e_ENET_MODE_SGMII_2500; -+ case SPEED_10000: -+ return e_ENET_MODE_XGMII_10000; -+ default: -+ return e_ENET_MODE_MII_100; -+ } -+} -+ -+static void mac_exception(handle_t _mac_dev, e_FmMacExceptions exception) -+{ -+ struct mac_device *mac_dev; -+ -+ mac_dev = (struct mac_device *)_mac_dev; -+ -+ if (e_FM_MAC_EX_10G_RX_FIFO_OVFL == exception) { -+ /* don't flag RX FIFO after the first */ -+ fm_mac_set_exception(mac_dev->get_mac_handle(mac_dev), -+ e_FM_MAC_EX_10G_RX_FIFO_OVFL, false); -+ dev_err(mac_dev->dev, "10G MAC got RX FIFO Error = %x\n", -+ exception); -+ } -+ -+ dev_dbg(mac_dev->dev, "%s:%s() -> %d\n", KBUILD_BASENAME".c", __func__, -+ exception); -+} -+ -+static int __cold init(struct mac_device *mac_dev) -+{ -+ int _errno; -+ struct mac_priv_s *priv; -+ t_FmMacParams param; -+ uint32_t version; -+ -+ priv = macdev_priv(mac_dev); -+ -+ param.baseAddr = (typeof(param.baseAddr))(uintptr_t)devm_ioremap( -+ mac_dev->dev, mac_dev->res->start, 0x2000); -+ param.enetMode = macdev2enetinterface(mac_dev); -+ memcpy(¶m.addr, mac_dev->addr, min(sizeof(param.addr), -+ sizeof(mac_dev->addr))); -+ param.macId = mac_dev->cell_index; -+ param.h_Fm = (handle_t)mac_dev->fm; -+ param.mdioIrq = NO_IRQ; -+ param.f_Exception = mac_exception; -+ param.f_Event = mac_exception; -+ param.h_App = mac_dev; -+ -+ priv->fm_mac = fm_mac_config(¶m); -+ if (unlikely(priv->fm_mac == NULL)) { -+ _errno = -EINVAL; -+ goto _return; -+ } -+ -+ fm_mac_set_handle(mac_dev->fm_dev, priv->fm_mac, -+ (macdev2enetinterface(mac_dev) != e_ENET_MODE_XGMII_10000) ? -+ param.macId : param.macId + FM_MAX_NUM_OF_1G_MACS); -+ -+ _errno = fm_mac_config_max_frame_length(priv->fm_mac, -+ fm_get_max_frm()); -+ if (unlikely(_errno < 0)) -+ goto _return_fm_mac_free; -+ -+ if (macdev2enetinterface(mac_dev) != e_ENET_MODE_XGMII_10000) { -+ /* 10G always works with pad and CRC */ -+ _errno = fm_mac_config_pad_and_crc(priv->fm_mac, true); -+ if (unlikely(_errno < 0)) -+ goto _return_fm_mac_free; -+ -+ _errno = fm_mac_config_half_duplex(priv->fm_mac, -+ mac_dev->half_duplex); -+ if (unlikely(_errno < 0)) -+ goto _return_fm_mac_free; -+ } else { -+ _errno = fm_mac_config_reset_on_init(priv->fm_mac, true); -+ if (unlikely(_errno < 0)) -+ goto _return_fm_mac_free; -+ } -+ -+ _errno = fm_mac_init(priv->fm_mac); -+ if (unlikely(_errno < 0)) -+ goto _return_fm_mac_free; -+ -+#ifndef CONFIG_FMAN_MIB_CNT_OVF_IRQ_EN -+ /* For 1G MAC, disable by default the MIB counters overflow interrupt */ -+ if (macdev2enetinterface(mac_dev) != e_ENET_MODE_XGMII_10000) { -+ _errno = fm_mac_set_exception(mac_dev->get_mac_handle(mac_dev), -+ e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL, FALSE); -+ if (unlikely(_errno < 0)) -+ goto _return_fm_mac_free; -+ } -+#endif /* !CONFIG_FMAN_MIB_CNT_OVF_IRQ_EN */ -+ -+ /* For 10G MAC, disable Tx ECC exception */ -+ if (macdev2enetinterface(mac_dev) == e_ENET_MODE_XGMII_10000) { -+ _errno = fm_mac_set_exception(mac_dev->get_mac_handle(mac_dev), -+ e_FM_MAC_EX_10G_1TX_ECC_ER, FALSE); -+ if (unlikely(_errno < 0)) -+ goto _return_fm_mac_free; -+ } -+ -+ _errno = fm_mac_get_version(priv->fm_mac, &version); -+ if (unlikely(_errno < 0)) -+ goto _return_fm_mac_free; -+ -+ dev_info(mac_dev->dev, "FMan %s version: 0x%08x\n", -+ ((macdev2enetinterface(mac_dev) != e_ENET_MODE_XGMII_10000) ? -+ "dTSEC" : "XGEC"), version); -+ -+ goto _return; -+ -+ -+_return_fm_mac_free: -+ fm_mac_free(mac_dev->get_mac_handle(mac_dev)); -+ -+_return: -+ return _errno; -+} -+ -+static int __cold memac_init(struct mac_device *mac_dev) -+{ -+ int _errno; -+ struct mac_priv_s *priv; -+ t_FmMacParams param; -+ -+ priv = macdev_priv(mac_dev); -+ -+ param.baseAddr = (typeof(param.baseAddr))(uintptr_t)devm_ioremap( -+ mac_dev->dev, mac_dev->res->start, 0x2000); -+ param.enetMode = macdev2enetinterface(mac_dev); -+ memcpy(¶m.addr, mac_dev->addr, sizeof(mac_dev->addr)); -+ param.macId = mac_dev->cell_index; -+ param.h_Fm = (handle_t)mac_dev->fm; -+ param.mdioIrq = NO_IRQ; -+ param.f_Exception = mac_exception; -+ param.f_Event = mac_exception; -+ param.h_App = mac_dev; -+ -+ priv->fm_mac = fm_mac_config(¶m); -+ if (unlikely(priv->fm_mac == NULL)) { -+ _errno = -EINVAL; -+ goto _return; -+ } -+ -+ fm_mac_set_handle(mac_dev->fm_dev, priv->fm_mac, -+ (macdev2enetinterface(mac_dev) != e_ENET_MODE_XGMII_10000) ? -+ param.macId : param.macId + FM_MAX_NUM_OF_1G_MACS); -+ -+ _errno = fm_mac_config_max_frame_length(priv->fm_mac, fm_get_max_frm()); -+ if (unlikely(_errno < 0)) -+ goto _return_fm_mac_free; -+ -+ _errno = fm_mac_config_reset_on_init(priv->fm_mac, true); -+ if (unlikely(_errno < 0)) -+ goto _return_fm_mac_free; -+ -+ _errno = fm_mac_init(priv->fm_mac); -+ if (unlikely(_errno < 0)) -+ goto _return_fm_mac_free; -+ -+ dev_info(mac_dev->dev, "FMan MEMAC\n"); -+ -+ goto _return; -+ -+_return_fm_mac_free: -+ fm_mac_free(priv->fm_mac); -+ -+_return: -+ return _errno; -+} -+ -+static int __cold start(struct mac_device *mac_dev) -+{ -+ int _errno; -+ struct phy_device *phy_dev = mac_dev->phy_dev; -+ -+ _errno = fm_mac_enable(mac_dev->get_mac_handle(mac_dev)); -+ -+ if (!_errno && phy_dev) { -+ if (macdev2enetinterface(mac_dev) != e_ENET_MODE_XGMII_10000) -+ phy_start(phy_dev); -+ else if (phy_dev->drv->read_status) -+ phy_dev->drv->read_status(phy_dev); -+ } -+ -+ return _errno; -+} -+ -+static int __cold stop(struct mac_device *mac_dev) -+{ -+ if (mac_dev->phy_dev && -+ (macdev2enetinterface(mac_dev) != e_ENET_MODE_XGMII_10000)) -+ phy_stop(mac_dev->phy_dev); -+ -+ return fm_mac_disable(mac_dev->get_mac_handle(mac_dev)); -+} -+ -+static int __cold set_multi(struct net_device *net_dev, -+ struct mac_device *mac_dev) -+{ -+ struct mac_priv_s *mac_priv; -+ struct mac_address *old_addr, *tmp; -+ struct netdev_hw_addr *ha; -+ int _errno; -+ -+ mac_priv = macdev_priv(mac_dev); -+ -+ /* Clear previous address list */ -+ list_for_each_entry_safe(old_addr, tmp, &mac_dev->mc_addr_list, list) { -+ _errno = fm_mac_remove_hash_mac_addr(mac_priv->fm_mac, -+ (t_EnetAddr *)old_addr->addr); -+ if (_errno < 0) -+ return _errno; -+ -+ list_del(&old_addr->list); -+ kfree(old_addr); -+ } -+ -+ /* Add all the addresses from the new list */ -+ netdev_for_each_mc_addr(ha, net_dev) { -+ _errno = fm_mac_add_hash_mac_addr(mac_priv->fm_mac, -+ (t_EnetAddr *)ha->addr); -+ if (_errno < 0) -+ return _errno; -+ -+ tmp = kmalloc(sizeof(struct mac_address), GFP_ATOMIC); -+ if (!tmp) { -+ dev_err(mac_dev->dev, "Out of memory\n"); -+ return -ENOMEM; -+ } -+ memcpy(tmp->addr, ha->addr, ETH_ALEN); -+ list_add(&tmp->list, &mac_dev->mc_addr_list); -+ } -+ return 0; -+} -+ -+/* Avoid redundant calls to FMD, if the MAC driver already contains the desired -+ * active PAUSE settings. Otherwise, the new active settings should be reflected -+ * in FMan. -+ */ -+int set_mac_active_pause(struct mac_device *mac_dev, bool rx, bool tx) -+{ -+ struct fm_mac_dev *fm_mac_dev = mac_dev->get_mac_handle(mac_dev); -+ int _errno = 0; -+ -+ if (unlikely(rx != mac_dev->rx_pause_active)) { -+ _errno = fm_mac_set_rx_pause_frames(fm_mac_dev, rx); -+ if (likely(_errno == 0)) -+ mac_dev->rx_pause_active = rx; -+ } -+ -+ if (unlikely(tx != mac_dev->tx_pause_active)) { -+ _errno = fm_mac_set_tx_pause_frames(fm_mac_dev, tx); -+ if (likely(_errno == 0)) -+ mac_dev->tx_pause_active = tx; -+ } -+ -+ return _errno; -+} -+EXPORT_SYMBOL(set_mac_active_pause); -+ -+/* Determine the MAC RX/TX PAUSE frames settings based on PHY -+ * autonegotiation or values set by eththool. -+ */ -+void get_pause_cfg(struct mac_device *mac_dev, bool *rx_pause, bool *tx_pause) -+{ -+ struct phy_device *phy_dev = mac_dev->phy_dev; -+ u16 lcl_adv, rmt_adv; -+ u8 flowctrl; -+ -+ *rx_pause = *tx_pause = false; -+ -+ if (!phy_dev->duplex) -+ return; -+ -+ /* If PAUSE autonegotiation is disabled, the TX/RX PAUSE settings -+ * are those set by ethtool. -+ */ -+ if (!mac_dev->autoneg_pause) { -+ *rx_pause = mac_dev->rx_pause_req; -+ *tx_pause = mac_dev->tx_pause_req; -+ return; -+ } -+ -+ /* Else if PAUSE autonegotiation is enabled, the TX/RX PAUSE -+ * settings depend on the result of the link negotiation. -+ */ -+ -+ /* get local capabilities */ -+ lcl_adv = 0; -+ if (phy_dev->advertising & ADVERTISED_Pause) -+ lcl_adv |= ADVERTISE_PAUSE_CAP; -+ if (phy_dev->advertising & ADVERTISED_Asym_Pause) -+ lcl_adv |= ADVERTISE_PAUSE_ASYM; -+ -+ /* get link partner capabilities */ -+ rmt_adv = 0; -+ if (phy_dev->pause) -+ rmt_adv |= LPA_PAUSE_CAP; -+ if (phy_dev->asym_pause) -+ rmt_adv |= LPA_PAUSE_ASYM; -+ -+ /* Calculate TX/RX settings based on local and peer advertised -+ * symmetric/asymmetric PAUSE capabilities. -+ */ -+ flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); -+ if (flowctrl & FLOW_CTRL_RX) -+ *rx_pause = true; -+ if (flowctrl & FLOW_CTRL_TX) -+ *tx_pause = true; -+} -+EXPORT_SYMBOL(get_pause_cfg); -+ -+static void adjust_link(struct net_device *net_dev) -+{ -+ struct dpa_priv_s *priv = netdev_priv(net_dev); -+ struct mac_device *mac_dev = priv->mac_dev; -+ struct phy_device *phy_dev = mac_dev->phy_dev; -+ struct fm_mac_dev *fm_mac_dev; -+ bool rx_pause, tx_pause; -+ int _errno; -+ -+ fm_mac_dev = mac_dev->get_mac_handle(mac_dev); -+ fm_mac_adjust_link(fm_mac_dev, phy_dev->link, phy_dev->speed, -+ phy_dev->duplex); -+ -+ get_pause_cfg(mac_dev, &rx_pause, &tx_pause); -+ _errno = set_mac_active_pause(mac_dev, rx_pause, tx_pause); -+ if (unlikely(_errno < 0)) -+ netdev_err(net_dev, "set_mac_active_pause() = %d\n", _errno); -+} -+ -+/* Initializes driver's PHY state, and attaches to the PHY. -+ * Returns 0 on success. -+ */ -+static int dtsec_init_phy(struct net_device *net_dev, -+ struct mac_device *mac_dev) -+{ -+ struct phy_device *phy_dev; -+ -+ if (!mac_dev->phy_node) -+ phy_dev = phy_connect(net_dev, mac_dev->fixed_bus_id, -+ &adjust_link, mac_dev->phy_if); -+ else -+ phy_dev = of_phy_connect(net_dev, mac_dev->phy_node, -+ &adjust_link, 0, mac_dev->phy_if); -+ if (unlikely(phy_dev == NULL) || IS_ERR(phy_dev)) { -+ netdev_err(net_dev, "Could not connect to PHY %s\n", -+ mac_dev->phy_node ? -+ mac_dev->phy_node->full_name : -+ mac_dev->fixed_bus_id); -+ return phy_dev == NULL ? -ENODEV : PTR_ERR(phy_dev); -+ } -+ -+ /* Remove any features not supported by the controller */ -+ phy_dev->supported &= mac_dev->if_support; -+ /* Enable the symmetric and asymmetric PAUSE frame advertisements, -+ * as most of the PHY drivers do not enable them by default. -+ */ -+ phy_dev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause); -+ phy_dev->advertising = phy_dev->supported; -+ -+ mac_dev->phy_dev = phy_dev; -+ -+ return 0; -+} -+ -+static int xgmac_init_phy(struct net_device *net_dev, -+ struct mac_device *mac_dev) -+{ -+ struct phy_device *phy_dev; -+ -+ if (!mac_dev->phy_node) -+ phy_dev = phy_attach(net_dev, mac_dev->fixed_bus_id, -+ mac_dev->phy_if); -+ else -+ phy_dev = of_phy_attach(net_dev, mac_dev->phy_node, 0, -+ mac_dev->phy_if); -+ if (unlikely(phy_dev == NULL) || IS_ERR(phy_dev)) { -+ netdev_err(net_dev, "Could not attach to PHY %s\n", -+ mac_dev->phy_node ? -+ mac_dev->phy_node->full_name : -+ mac_dev->fixed_bus_id); -+ return phy_dev == NULL ? -ENODEV : PTR_ERR(phy_dev); -+ } -+ -+ phy_dev->supported &= mac_dev->if_support; -+ /* Enable the symmetric and asymmetric PAUSE frame advertisements, -+ * as most of the PHY drivers do not enable them by default. -+ */ -+ phy_dev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause); -+ phy_dev->advertising = phy_dev->supported; -+ -+ mac_dev->phy_dev = phy_dev; -+ -+ return 0; -+} -+ -+static int memac_init_phy(struct net_device *net_dev, -+ struct mac_device *mac_dev) -+{ -+ struct phy_device *phy_dev; -+ -+ if ((macdev2enetinterface(mac_dev) == e_ENET_MODE_XGMII_10000) || -+ (macdev2enetinterface(mac_dev) == e_ENET_MODE_SGMII_2500)){ -+ if (!mac_dev->phy_node) { -+ mac_dev->phy_dev = NULL; -+ return 0; -+ } else -+ phy_dev = of_phy_attach(net_dev, mac_dev->phy_node, 0, -+ mac_dev->phy_if); -+ } else { -+ if (!mac_dev->phy_node) -+ phy_dev = phy_connect(net_dev, mac_dev->fixed_bus_id, -+ &adjust_link, mac_dev->phy_if); -+ else -+ phy_dev = of_phy_connect(net_dev, mac_dev->phy_node, -+ &adjust_link, 0, -+ mac_dev->phy_if); -+ } -+ -+ if (unlikely(phy_dev == NULL) || IS_ERR(phy_dev)) { -+ netdev_err(net_dev, "Could not connect to PHY %s\n", -+ mac_dev->phy_node ? -+ mac_dev->phy_node->full_name : -+ mac_dev->fixed_bus_id); -+ return phy_dev == NULL ? -ENODEV : PTR_ERR(phy_dev); -+ } -+ -+ /* Remove any features not supported by the controller */ -+ phy_dev->supported &= mac_dev->if_support; -+ /* Enable the symmetric and asymmetric PAUSE frame advertisements, -+ * as most of the PHY drivers do not enable them by default. -+ */ -+ phy_dev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause); -+ phy_dev->advertising = phy_dev->supported; -+ -+ mac_dev->phy_dev = phy_dev; -+ -+ return 0; -+} -+ -+static int __cold uninit(struct fm_mac_dev *fm_mac_dev) -+{ -+ int _errno, __errno; -+ -+ _errno = fm_mac_disable(fm_mac_dev); -+ __errno = fm_mac_free(fm_mac_dev); -+ -+ if (unlikely(__errno < 0)) -+ _errno = __errno; -+ -+ return _errno; -+} -+ -+static struct fm_mac_dev *get_mac_handle(struct mac_device *mac_dev) -+{ -+ const struct mac_priv_s *priv; -+ priv = macdev_priv(mac_dev); -+ return priv->fm_mac; -+} -+ -+static int dtsec_dump_regs(struct mac_device *h_mac, char *buf, int nn) -+{ -+ struct dtsec_regs *p_mm = (struct dtsec_regs *) h_mac->vaddr; -+ int i = 0, n = nn; -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ -+ FM_DMP_TITLE(buf, n, p_mm, "FM MAC - DTSEC-%d", h_mac->cell_index); -+ -+ FM_DMP_V32(buf, n, p_mm, tsec_id); -+ FM_DMP_V32(buf, n, p_mm, tsec_id2); -+ FM_DMP_V32(buf, n, p_mm, ievent); -+ FM_DMP_V32(buf, n, p_mm, imask); -+ FM_DMP_V32(buf, n, p_mm, ecntrl); -+ FM_DMP_V32(buf, n, p_mm, ptv); -+ FM_DMP_V32(buf, n, p_mm, tmr_ctrl); -+ FM_DMP_V32(buf, n, p_mm, tmr_pevent); -+ FM_DMP_V32(buf, n, p_mm, tmr_pemask); -+ FM_DMP_V32(buf, n, p_mm, tctrl); -+ FM_DMP_V32(buf, n, p_mm, rctrl); -+ FM_DMP_V32(buf, n, p_mm, maccfg1); -+ FM_DMP_V32(buf, n, p_mm, maccfg2); -+ FM_DMP_V32(buf, n, p_mm, ipgifg); -+ FM_DMP_V32(buf, n, p_mm, hafdup); -+ FM_DMP_V32(buf, n, p_mm, maxfrm); -+ -+ FM_DMP_V32(buf, n, p_mm, macstnaddr1); -+ FM_DMP_V32(buf, n, p_mm, macstnaddr2); -+ -+ for (i = 0; i < 7; ++i) { -+ FM_DMP_V32(buf, n, p_mm, macaddr[i].exact_match1); -+ FM_DMP_V32(buf, n, p_mm, macaddr[i].exact_match2); -+ } -+ -+ FM_DMP_V32(buf, n, p_mm, car1); -+ FM_DMP_V32(buf, n, p_mm, car2); -+ -+ return n; -+} -+ -+static int xgmac_dump_regs(struct mac_device *h_mac, char *buf, int nn) -+{ -+ struct tgec_regs *p_mm = (struct tgec_regs *) h_mac->vaddr; -+ int n = nn; -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_TITLE(buf, n, p_mm, "FM MAC - TGEC -%d", h_mac->cell_index); -+ -+ FM_DMP_V32(buf, n, p_mm, tgec_id); -+ FM_DMP_V32(buf, n, p_mm, command_config); -+ FM_DMP_V32(buf, n, p_mm, mac_addr_0); -+ FM_DMP_V32(buf, n, p_mm, mac_addr_1); -+ FM_DMP_V32(buf, n, p_mm, maxfrm); -+ FM_DMP_V32(buf, n, p_mm, pause_quant); -+ FM_DMP_V32(buf, n, p_mm, rx_fifo_sections); -+ FM_DMP_V32(buf, n, p_mm, tx_fifo_sections); -+ FM_DMP_V32(buf, n, p_mm, rx_fifo_almost_f_e); -+ FM_DMP_V32(buf, n, p_mm, tx_fifo_almost_f_e); -+ FM_DMP_V32(buf, n, p_mm, hashtable_ctrl); -+ FM_DMP_V32(buf, n, p_mm, mdio_cfg_status); -+ FM_DMP_V32(buf, n, p_mm, mdio_command); -+ FM_DMP_V32(buf, n, p_mm, mdio_data); -+ FM_DMP_V32(buf, n, p_mm, mdio_regaddr); -+ FM_DMP_V32(buf, n, p_mm, status); -+ FM_DMP_V32(buf, n, p_mm, tx_ipg_len); -+ FM_DMP_V32(buf, n, p_mm, mac_addr_2); -+ FM_DMP_V32(buf, n, p_mm, mac_addr_3); -+ FM_DMP_V32(buf, n, p_mm, rx_fifo_ptr_rd); -+ FM_DMP_V32(buf, n, p_mm, rx_fifo_ptr_wr); -+ FM_DMP_V32(buf, n, p_mm, tx_fifo_ptr_rd); -+ FM_DMP_V32(buf, n, p_mm, tx_fifo_ptr_wr); -+ FM_DMP_V32(buf, n, p_mm, imask); -+ FM_DMP_V32(buf, n, p_mm, ievent); -+ -+ return n; -+} -+ -+static int memac_dump_regs(struct mac_device *h_mac, char *buf, int nn) -+{ -+ struct memac_regs *p_mm = (struct memac_regs *) h_mac->vaddr; -+ int i = 0, n = nn; -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_TITLE(buf, n, p_mm, "FM MAC - MEMAC -%d", h_mac->cell_index); -+ -+ FM_DMP_V32(buf, n, p_mm, command_config); -+ FM_DMP_V32(buf, n, p_mm, mac_addr0.mac_addr_l); -+ FM_DMP_V32(buf, n, p_mm, mac_addr0.mac_addr_u); -+ FM_DMP_V32(buf, n, p_mm, maxfrm); -+ FM_DMP_V32(buf, n, p_mm, hashtable_ctrl); -+ FM_DMP_V32(buf, n, p_mm, ievent); -+ FM_DMP_V32(buf, n, p_mm, tx_ipg_length); -+ FM_DMP_V32(buf, n, p_mm, imask); -+ -+ for (i = 0; i < 4; ++i) -+ FM_DMP_V32(buf, n, p_mm, pause_quanta[i]); -+ -+ for (i = 0; i < 4; ++i) -+ FM_DMP_V32(buf, n, p_mm, pause_thresh[i]); -+ -+ FM_DMP_V32(buf, n, p_mm, rx_pause_status); -+ -+ for (i = 0; i < MEMAC_NUM_OF_PADDRS; ++i) { -+ FM_DMP_V32(buf, n, p_mm, mac_addr[i].mac_addr_l); -+ FM_DMP_V32(buf, n, p_mm, mac_addr[i].mac_addr_u); -+ } -+ -+ FM_DMP_V32(buf, n, p_mm, lpwake_timer); -+ FM_DMP_V32(buf, n, p_mm, sleep_timer); -+ FM_DMP_V32(buf, n, p_mm, statn_config); -+ FM_DMP_V32(buf, n, p_mm, if_mode); -+ FM_DMP_V32(buf, n, p_mm, if_status); -+ FM_DMP_V32(buf, n, p_mm, hg_config); -+ FM_DMP_V32(buf, n, p_mm, hg_pause_quanta); -+ FM_DMP_V32(buf, n, p_mm, hg_pause_thresh); -+ FM_DMP_V32(buf, n, p_mm, hgrx_pause_status); -+ FM_DMP_V32(buf, n, p_mm, hg_fifos_status); -+ FM_DMP_V32(buf, n, p_mm, rhm); -+ FM_DMP_V32(buf, n, p_mm, thm); -+ -+ return n; -+} -+ -+static int memac_dump_regs_rx(struct mac_device *h_mac, char *buf, int nn) -+{ -+ struct memac_regs *p_mm = (struct memac_regs *) h_mac->vaddr; -+ int n = nn; -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_TITLE(buf, n, p_mm, "FM MAC - MEMAC -%d Rx stats", h_mac->cell_index); -+ -+ /* Rx Statistics Counter */ -+ FM_DMP_V32(buf, n, p_mm, reoct_l); -+ FM_DMP_V32(buf, n, p_mm, reoct_u); -+ FM_DMP_V32(buf, n, p_mm, roct_l); -+ FM_DMP_V32(buf, n, p_mm, roct_u); -+ FM_DMP_V32(buf, n, p_mm, raln_l); -+ FM_DMP_V32(buf, n, p_mm, raln_u); -+ FM_DMP_V32(buf, n, p_mm, rxpf_l); -+ FM_DMP_V32(buf, n, p_mm, rxpf_u); -+ FM_DMP_V32(buf, n, p_mm, rfrm_l); -+ FM_DMP_V32(buf, n, p_mm, rfrm_u); -+ FM_DMP_V32(buf, n, p_mm, rfcs_l); -+ FM_DMP_V32(buf, n, p_mm, rfcs_u); -+ FM_DMP_V32(buf, n, p_mm, rvlan_l); -+ FM_DMP_V32(buf, n, p_mm, rvlan_u); -+ FM_DMP_V32(buf, n, p_mm, rerr_l); -+ FM_DMP_V32(buf, n, p_mm, rerr_u); -+ FM_DMP_V32(buf, n, p_mm, ruca_l); -+ FM_DMP_V32(buf, n, p_mm, ruca_u); -+ FM_DMP_V32(buf, n, p_mm, rmca_l); -+ FM_DMP_V32(buf, n, p_mm, rmca_u); -+ FM_DMP_V32(buf, n, p_mm, rbca_l); -+ FM_DMP_V32(buf, n, p_mm, rbca_u); -+ FM_DMP_V32(buf, n, p_mm, rdrp_l); -+ FM_DMP_V32(buf, n, p_mm, rdrp_u); -+ FM_DMP_V32(buf, n, p_mm, rpkt_l); -+ FM_DMP_V32(buf, n, p_mm, rpkt_u); -+ FM_DMP_V32(buf, n, p_mm, rund_l); -+ FM_DMP_V32(buf, n, p_mm, rund_u); -+ FM_DMP_V32(buf, n, p_mm, r64_l); -+ FM_DMP_V32(buf, n, p_mm, r64_u); -+ FM_DMP_V32(buf, n, p_mm, r127_l); -+ FM_DMP_V32(buf, n, p_mm, r127_u); -+ FM_DMP_V32(buf, n, p_mm, r255_l); -+ FM_DMP_V32(buf, n, p_mm, r255_u); -+ FM_DMP_V32(buf, n, p_mm, r511_l); -+ FM_DMP_V32(buf, n, p_mm, r511_u); -+ FM_DMP_V32(buf, n, p_mm, r1023_l); -+ FM_DMP_V32(buf, n, p_mm, r1023_u); -+ FM_DMP_V32(buf, n, p_mm, r1518_l); -+ FM_DMP_V32(buf, n, p_mm, r1518_u); -+ FM_DMP_V32(buf, n, p_mm, r1519x_l); -+ FM_DMP_V32(buf, n, p_mm, r1519x_u); -+ FM_DMP_V32(buf, n, p_mm, rovr_l); -+ FM_DMP_V32(buf, n, p_mm, rovr_u); -+ FM_DMP_V32(buf, n, p_mm, rjbr_l); -+ FM_DMP_V32(buf, n, p_mm, rjbr_u); -+ FM_DMP_V32(buf, n, p_mm, rfrg_l); -+ FM_DMP_V32(buf, n, p_mm, rfrg_u); -+ FM_DMP_V32(buf, n, p_mm, rcnp_l); -+ FM_DMP_V32(buf, n, p_mm, rcnp_u); -+ FM_DMP_V32(buf, n, p_mm, rdrntp_l); -+ FM_DMP_V32(buf, n, p_mm, rdrntp_u); -+ -+ return n; -+} -+ -+static int memac_dump_regs_tx(struct mac_device *h_mac, char *buf, int nn) -+{ -+ struct memac_regs *p_mm = (struct memac_regs *) h_mac->vaddr; -+ int n = nn; -+ -+ FM_DMP_SUBTITLE(buf, n, "\n"); -+ FM_DMP_TITLE(buf, n, p_mm, "FM MAC - MEMAC -%d Tx stats", h_mac->cell_index); -+ -+ -+ /* Tx Statistics Counter */ -+ FM_DMP_V32(buf, n, p_mm, teoct_l); -+ FM_DMP_V32(buf, n, p_mm, teoct_u); -+ FM_DMP_V32(buf, n, p_mm, toct_l); -+ FM_DMP_V32(buf, n, p_mm, toct_u); -+ FM_DMP_V32(buf, n, p_mm, txpf_l); -+ FM_DMP_V32(buf, n, p_mm, txpf_u); -+ FM_DMP_V32(buf, n, p_mm, tfrm_l); -+ FM_DMP_V32(buf, n, p_mm, tfrm_u); -+ FM_DMP_V32(buf, n, p_mm, tfcs_l); -+ FM_DMP_V32(buf, n, p_mm, tfcs_u); -+ FM_DMP_V32(buf, n, p_mm, tvlan_l); -+ FM_DMP_V32(buf, n, p_mm, tvlan_u); -+ FM_DMP_V32(buf, n, p_mm, terr_l); -+ FM_DMP_V32(buf, n, p_mm, terr_u); -+ FM_DMP_V32(buf, n, p_mm, tuca_l); -+ FM_DMP_V32(buf, n, p_mm, tuca_u); -+ FM_DMP_V32(buf, n, p_mm, tmca_l); -+ FM_DMP_V32(buf, n, p_mm, tmca_u); -+ FM_DMP_V32(buf, n, p_mm, tbca_l); -+ FM_DMP_V32(buf, n, p_mm, tbca_u); -+ FM_DMP_V32(buf, n, p_mm, tpkt_l); -+ FM_DMP_V32(buf, n, p_mm, tpkt_u); -+ FM_DMP_V32(buf, n, p_mm, tund_l); -+ FM_DMP_V32(buf, n, p_mm, tund_u); -+ FM_DMP_V32(buf, n, p_mm, t64_l); -+ FM_DMP_V32(buf, n, p_mm, t64_u); -+ FM_DMP_V32(buf, n, p_mm, t127_l); -+ FM_DMP_V32(buf, n, p_mm, t127_u); -+ FM_DMP_V32(buf, n, p_mm, t255_l); -+ FM_DMP_V32(buf, n, p_mm, t255_u); -+ FM_DMP_V32(buf, n, p_mm, t511_l); -+ FM_DMP_V32(buf, n, p_mm, t511_u); -+ FM_DMP_V32(buf, n, p_mm, t1023_l); -+ FM_DMP_V32(buf, n, p_mm, t1023_u); -+ FM_DMP_V32(buf, n, p_mm, t1518_l); -+ FM_DMP_V32(buf, n, p_mm, t1518_u); -+ FM_DMP_V32(buf, n, p_mm, t1519x_l); -+ FM_DMP_V32(buf, n, p_mm, t1519x_u); -+ FM_DMP_V32(buf, n, p_mm, tcnp_l); -+ FM_DMP_V32(buf, n, p_mm, tcnp_u); -+ -+ return n; -+} -+ -+int fm_mac_dump_regs(struct mac_device *h_mac, char *buf, int nn) -+{ -+ int n = nn; -+ -+ n = h_mac->dump_mac_regs(h_mac, buf, n); -+ -+ return n; -+} -+EXPORT_SYMBOL(fm_mac_dump_regs); -+ -+int fm_mac_dump_rx_stats(struct mac_device *h_mac, char *buf, int nn) -+{ -+ int n = nn; -+ -+ if(h_mac->dump_mac_rx_stats) -+ n = h_mac->dump_mac_rx_stats(h_mac, buf, n); -+ -+ return n; -+} -+EXPORT_SYMBOL(fm_mac_dump_rx_stats); -+ -+int fm_mac_dump_tx_stats(struct mac_device *h_mac, char *buf, int nn) -+{ -+ int n = nn; -+ -+ if(h_mac->dump_mac_tx_stats) -+ n = h_mac->dump_mac_tx_stats(h_mac, buf, n); -+ -+ return n; -+} -+EXPORT_SYMBOL(fm_mac_dump_tx_stats); -+ -+static void __cold setup_dtsec(struct mac_device *mac_dev) -+{ -+ mac_dev->init_phy = dtsec_init_phy; -+ mac_dev->init = init; -+ mac_dev->start = start; -+ mac_dev->stop = stop; -+ mac_dev->set_promisc = fm_mac_set_promiscuous; -+ mac_dev->change_addr = fm_mac_modify_mac_addr; -+ mac_dev->set_multi = set_multi; -+ mac_dev->uninit = uninit; -+ mac_dev->ptp_enable = fm_mac_enable_1588_time_stamp; -+ mac_dev->ptp_disable = fm_mac_disable_1588_time_stamp; -+ mac_dev->get_mac_handle = get_mac_handle; -+ mac_dev->set_tx_pause = fm_mac_set_tx_pause_frames; -+ mac_dev->set_rx_pause = fm_mac_set_rx_pause_frames; -+ mac_dev->fm_rtc_enable = fm_rtc_enable; -+ mac_dev->fm_rtc_disable = fm_rtc_disable; -+ mac_dev->fm_rtc_get_cnt = fm_rtc_get_cnt; -+ mac_dev->fm_rtc_set_cnt = fm_rtc_set_cnt; -+ mac_dev->fm_rtc_get_drift = fm_rtc_get_drift; -+ mac_dev->fm_rtc_set_drift = fm_rtc_set_drift; -+ mac_dev->fm_rtc_set_alarm = fm_rtc_set_alarm; -+ mac_dev->fm_rtc_set_fiper = fm_rtc_set_fiper; -+ mac_dev->set_wol = fm_mac_set_wol; -+ mac_dev->dump_mac_regs = dtsec_dump_regs; -+} -+ -+static void __cold setup_xgmac(struct mac_device *mac_dev) -+{ -+ mac_dev->init_phy = xgmac_init_phy; -+ mac_dev->init = init; -+ mac_dev->start = start; -+ mac_dev->stop = stop; -+ mac_dev->set_promisc = fm_mac_set_promiscuous; -+ mac_dev->change_addr = fm_mac_modify_mac_addr; -+ mac_dev->set_multi = set_multi; -+ mac_dev->uninit = uninit; -+ mac_dev->get_mac_handle = get_mac_handle; -+ mac_dev->set_tx_pause = fm_mac_set_tx_pause_frames; -+ mac_dev->set_rx_pause = fm_mac_set_rx_pause_frames; -+ mac_dev->set_wol = fm_mac_set_wol; -+ mac_dev->dump_mac_regs = xgmac_dump_regs; -+} -+ -+static void __cold setup_memac(struct mac_device *mac_dev) -+{ -+ mac_dev->init_phy = memac_init_phy; -+ mac_dev->init = memac_init; -+ mac_dev->start = start; -+ mac_dev->stop = stop; -+ mac_dev->set_promisc = fm_mac_set_promiscuous; -+ mac_dev->change_addr = fm_mac_modify_mac_addr; -+ mac_dev->set_multi = set_multi; -+ mac_dev->uninit = uninit; -+ mac_dev->get_mac_handle = get_mac_handle; -+ mac_dev->set_tx_pause = fm_mac_set_tx_pause_frames; -+ mac_dev->set_rx_pause = fm_mac_set_rx_pause_frames; -+ mac_dev->fm_rtc_enable = fm_rtc_enable; -+ mac_dev->fm_rtc_disable = fm_rtc_disable; -+ mac_dev->fm_rtc_get_cnt = fm_rtc_get_cnt; -+ mac_dev->fm_rtc_set_cnt = fm_rtc_set_cnt; -+ mac_dev->fm_rtc_get_drift = fm_rtc_get_drift; -+ mac_dev->fm_rtc_set_drift = fm_rtc_set_drift; -+ mac_dev->fm_rtc_set_alarm = fm_rtc_set_alarm; -+ mac_dev->fm_rtc_set_fiper = fm_rtc_set_fiper; -+ mac_dev->set_wol = fm_mac_set_wol; -+ mac_dev->dump_mac_regs = memac_dump_regs; -+ mac_dev->dump_mac_rx_stats = memac_dump_regs_rx; -+ mac_dev->dump_mac_tx_stats = memac_dump_regs_tx; -+} -+ -+void (*const mac_setup[])(struct mac_device *mac_dev) = { -+ [DTSEC] = setup_dtsec, -+ [XGMAC] = setup_xgmac, -+ [MEMAC] = setup_memac -+}; ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac.c -@@ -0,0 +1,470 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifdef CONFIG_FSL_DPAA_ETH_DEBUG -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": %s:%hu:%s() " fmt, \ -+ KBUILD_BASENAME".c", __LINE__, __func__ -+#else -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": " fmt -+#endif -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "lnxwrp_fm_ext.h" -+ -+#include "mac.h" -+ -+#define DTSEC_SUPPORTED \ -+ (SUPPORTED_10baseT_Half \ -+ | SUPPORTED_10baseT_Full \ -+ | SUPPORTED_100baseT_Half \ -+ | SUPPORTED_100baseT_Full \ -+ | SUPPORTED_Autoneg \ -+ | SUPPORTED_Pause \ -+ | SUPPORTED_Asym_Pause \ -+ | SUPPORTED_MII) -+ -+static const char phy_str[][11] = { -+ [PHY_INTERFACE_MODE_MII] = "mii", -+ [PHY_INTERFACE_MODE_GMII] = "gmii", -+ [PHY_INTERFACE_MODE_SGMII] = "sgmii", -+ [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", -+ [PHY_INTERFACE_MODE_TBI] = "tbi", -+ [PHY_INTERFACE_MODE_RMII] = "rmii", -+ [PHY_INTERFACE_MODE_RGMII] = "rgmii", -+ [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", -+ [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", -+ [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", -+ [PHY_INTERFACE_MODE_RTBI] = "rtbi", -+ [PHY_INTERFACE_MODE_XGMII] = "xgmii", -+ [PHY_INTERFACE_MODE_QSGMII] = "sgmii-2500" -+}; -+ -+static phy_interface_t __pure __attribute__((nonnull)) str2phy(const char *str) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(phy_str); i++) -+ if (strcmp(str, phy_str[i]) == 0) -+ return (phy_interface_t)i; -+ -+ return PHY_INTERFACE_MODE_MII; -+} -+ -+static const uint16_t phy2speed[] = { -+ [PHY_INTERFACE_MODE_MII] = SPEED_100, -+ [PHY_INTERFACE_MODE_GMII] = SPEED_1000, -+ [PHY_INTERFACE_MODE_SGMII] = SPEED_1000, -+ [PHY_INTERFACE_MODE_QSGMII] = SPEED_1000, -+ [PHY_INTERFACE_MODE_TBI] = SPEED_1000, -+ [PHY_INTERFACE_MODE_RMII] = SPEED_100, -+ [PHY_INTERFACE_MODE_RGMII] = SPEED_1000, -+ [PHY_INTERFACE_MODE_RGMII_ID] = SPEED_1000, -+ [PHY_INTERFACE_MODE_RGMII_RXID] = SPEED_1000, -+ [PHY_INTERFACE_MODE_RGMII_TXID] = SPEED_1000, -+ [PHY_INTERFACE_MODE_RTBI] = SPEED_1000, -+ [PHY_INTERFACE_MODE_XGMII] = SPEED_10000, -+ [PHY_INTERFACE_MODE_QSGMII] = SPEED_2500 -+}; -+ -+static struct mac_device * __cold -+alloc_macdev(struct device *dev, size_t sizeof_priv, -+ void (*setup)(struct mac_device *mac_dev)) -+{ -+ struct mac_device *mac_dev; -+ -+ mac_dev = devm_kzalloc(dev, sizeof(*mac_dev) + sizeof_priv, GFP_KERNEL); -+ if (unlikely(mac_dev == NULL)) -+ mac_dev = ERR_PTR(-ENOMEM); -+ else { -+ mac_dev->dev = dev; -+ dev_set_drvdata(dev, mac_dev); -+ setup(mac_dev); -+ } -+ -+ return mac_dev; -+} -+ -+static int __cold free_macdev(struct mac_device *mac_dev) -+{ -+ dev_set_drvdata(mac_dev->dev, NULL); -+ -+ return mac_dev->uninit(mac_dev->get_mac_handle(mac_dev)); -+} -+ -+static const struct of_device_id mac_match[] = { -+ [DTSEC] = { -+ .compatible = "fsl,fman-1g-mac" -+ }, -+ [XGMAC] = { -+ .compatible = "fsl,fman-10g-mac" -+ }, -+ [MEMAC] = { -+ .compatible = "fsl,fman-memac" -+ }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, mac_match); -+ -+static int __cold mac_probe(struct platform_device *_of_dev) -+{ -+ int _errno, i; -+ struct device *dev; -+ struct device_node *mac_node, *dev_node; -+ struct mac_device *mac_dev; -+ struct platform_device *of_dev; -+ struct resource res; -+ const uint8_t *mac_addr; -+ const char *char_prop; -+ int nph; -+ u32 cell_index; -+ const struct of_device_id *match; -+ -+ dev = &_of_dev->dev; -+ mac_node = dev->of_node; -+ -+ match = of_match_device(mac_match, dev); -+ if (!match) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(mac_match) - 1 && match != mac_match + i; -+ i++) -+ ; -+ BUG_ON(i >= ARRAY_SIZE(mac_match) - 1); -+ -+ mac_dev = alloc_macdev(dev, mac_sizeof_priv[i], mac_setup[i]); -+ if (IS_ERR(mac_dev)) { -+ _errno = PTR_ERR(mac_dev); -+ dev_err(dev, "alloc_macdev() = %d\n", _errno); -+ goto _return; -+ } -+ -+ INIT_LIST_HEAD(&mac_dev->mc_addr_list); -+ -+ /* Get the FM node */ -+ dev_node = of_get_parent(mac_node); -+ if (unlikely(dev_node == NULL)) { -+ dev_err(dev, "of_get_parent(%s) failed\n", -+ mac_node->full_name); -+ _errno = -EINVAL; -+ goto _return_dev_set_drvdata; -+ } -+ -+ of_dev = of_find_device_by_node(dev_node); -+ if (unlikely(of_dev == NULL)) { -+ dev_err(dev, "of_find_device_by_node(%s) failed\n", -+ dev_node->full_name); -+ _errno = -EINVAL; -+ goto _return_of_node_put; -+ } -+ -+ mac_dev->fm_dev = fm_bind(&of_dev->dev); -+ if (unlikely(mac_dev->fm_dev == NULL)) { -+ dev_err(dev, "fm_bind(%s) failed\n", dev_node->full_name); -+ _errno = -ENODEV; -+ goto _return_of_node_put; -+ } -+ -+ mac_dev->fm = (void *)fm_get_handle(mac_dev->fm_dev); -+ of_node_put(dev_node); -+ -+ /* Get the address of the memory mapped registers */ -+ _errno = of_address_to_resource(mac_node, 0, &res); -+ if (unlikely(_errno < 0)) { -+ dev_err(dev, "of_address_to_resource(%s) = %d\n", -+ mac_node->full_name, _errno); -+ goto _return_dev_set_drvdata; -+ } -+ -+ mac_dev->res = __devm_request_region( -+ dev, -+ fm_get_mem_region(mac_dev->fm_dev), -+ res.start, res.end + 1 - res.start, "mac"); -+ if (unlikely(mac_dev->res == NULL)) { -+ dev_err(dev, "__devm_request_mem_region(mac) failed\n"); -+ _errno = -EBUSY; -+ goto _return_dev_set_drvdata; -+ } -+ -+ mac_dev->vaddr = devm_ioremap(dev, mac_dev->res->start, -+ mac_dev->res->end + 1 -+ - mac_dev->res->start); -+ if (unlikely(mac_dev->vaddr == NULL)) { -+ dev_err(dev, "devm_ioremap() failed\n"); -+ _errno = -EIO; -+ goto _return_dev_set_drvdata; -+ } -+ -+#define TBIPA_OFFSET 0x1c -+#define TBIPA_DEFAULT_ADDR 5 /* override if used as external PHY addr. */ -+ mac_dev->tbi_node = of_parse_phandle(mac_node, "tbi-handle", 0); -+ if (mac_dev->tbi_node) { -+ u32 tbiaddr = TBIPA_DEFAULT_ADDR; -+ const __be32 *tbi_reg; -+ void __iomem *addr; -+ -+ tbi_reg = of_get_property(mac_dev->tbi_node, "reg", NULL); -+ if (tbi_reg) -+ tbiaddr = be32_to_cpup(tbi_reg); -+ addr = mac_dev->vaddr + TBIPA_OFFSET; -+ /* TODO: out_be32 does not exist on ARM */ -+ out_be32(addr, tbiaddr); -+ } -+ -+ if (!of_device_is_available(mac_node)) { -+ devm_iounmap(dev, mac_dev->vaddr); -+ __devm_release_region(dev, fm_get_mem_region(mac_dev->fm_dev), -+ res.start, res.end + 1 - res.start); -+ fm_unbind(mac_dev->fm_dev); -+ devm_kfree(dev, mac_dev); -+ dev_set_drvdata(dev, NULL); -+ return -ENODEV; -+ } -+ -+ /* Get the cell-index */ -+ _errno = of_property_read_u32(mac_node, "cell-index", &cell_index); -+ if (unlikely(_errno)) { -+ dev_err(dev, "Cannot read cell-index of mac node %s from device tree\n", -+ mac_node->full_name); -+ goto _return_dev_set_drvdata; -+ } -+ mac_dev->cell_index = (uint8_t)cell_index; -+ -+ /* Get the MAC address */ -+ mac_addr = of_get_mac_address(mac_node); -+ if (unlikely(mac_addr == NULL)) { -+ dev_err(dev, "of_get_mac_address(%s) failed\n", -+ mac_node->full_name); -+ _errno = -EINVAL; -+ goto _return_dev_set_drvdata; -+ } -+ memcpy(mac_dev->addr, mac_addr, sizeof(mac_dev->addr)); -+ -+ /* Verify the number of port handles */ -+ nph = of_count_phandle_with_args(mac_node, "fsl,port-handles", NULL); -+ if (unlikely(nph < 0)) { -+ dev_err(dev, "Cannot read port handles of mac node %s from device tree\n", -+ mac_node->full_name); -+ _errno = nph; -+ goto _return_dev_set_drvdata; -+ } -+ -+ if (nph != ARRAY_SIZE(mac_dev->port_dev)) { -+ dev_err(dev, "Not supported number of port handles of mac node %s from device tree\n", -+ mac_node->full_name); -+ _errno = -EINVAL; -+ goto _return_dev_set_drvdata; -+ } -+ -+ for_each_port_device(i, mac_dev->port_dev) { -+ dev_node = of_parse_phandle(mac_node, "fsl,port-handles", i); -+ if (unlikely(dev_node == NULL)) { -+ dev_err(dev, "Cannot find port node referenced by mac node %s from device tree\n", -+ mac_node->full_name); -+ _errno = -EINVAL; -+ goto _return_of_node_put; -+ } -+ -+ of_dev = of_find_device_by_node(dev_node); -+ if (unlikely(of_dev == NULL)) { -+ dev_err(dev, "of_find_device_by_node(%s) failed\n", -+ dev_node->full_name); -+ _errno = -EINVAL; -+ goto _return_of_node_put; -+ } -+ -+ mac_dev->port_dev[i] = fm_port_bind(&of_dev->dev); -+ if (unlikely(mac_dev->port_dev[i] == NULL)) { -+ dev_err(dev, "dev_get_drvdata(%s) failed\n", -+ dev_node->full_name); -+ _errno = -EINVAL; -+ goto _return_of_node_put; -+ } -+ of_node_put(dev_node); -+ } -+ -+ /* Get the PHY connection type */ -+ _errno = of_property_read_string(mac_node, "phy-connection-type", -+ &char_prop); -+ if (unlikely(_errno)) { -+ dev_warn(dev, -+ "Cannot read PHY connection type of mac node %s from device tree. Defaulting to MII\n", -+ mac_node->full_name); -+ mac_dev->phy_if = PHY_INTERFACE_MODE_MII; -+ } else -+ mac_dev->phy_if = str2phy(char_prop); -+ -+ mac_dev->link = false; -+ mac_dev->half_duplex = false; -+ mac_dev->speed = phy2speed[mac_dev->phy_if]; -+ mac_dev->max_speed = mac_dev->speed; -+ mac_dev->if_support = DTSEC_SUPPORTED; -+ /* We don't support half-duplex in SGMII mode */ -+ if (strstr(char_prop, "sgmii") || strstr(char_prop, "qsgmii")) -+ mac_dev->if_support &= ~(SUPPORTED_10baseT_Half | -+ SUPPORTED_100baseT_Half); -+ -+ if (strstr(char_prop, "sgmii-2500")) -+ mac_dev->if_support &= ~(SUPPORTED_10baseT_Half | -+ SUPPORTED_100baseT_Half); -+ -+ /* Gigabit support (no half-duplex) */ -+ if (mac_dev->max_speed == 1000) -+ mac_dev->if_support |= SUPPORTED_1000baseT_Full; -+ -+ /* The 10G interface only supports one mode */ -+ if (strstr(char_prop, "xgmii")) -+ mac_dev->if_support = SUPPORTED_10000baseT_Full; -+ -+ /* Get the rest of the PHY information */ -+ mac_dev->phy_node = of_parse_phandle(mac_node, "phy-handle", 0); -+ if (mac_dev->phy_node == NULL) { -+ u32 phy_id; -+ -+ _errno = of_property_read_u32(mac_node, "fixed-link", &phy_id); -+ if (_errno) { -+ dev_err(dev, "No PHY (or fixed link) found\n"); -+ _errno = -EINVAL; -+ goto _return_dev_set_drvdata; -+ } -+ -+ sprintf(mac_dev->fixed_bus_id, PHY_ID_FMT, "fixed-0", -+ phy_id); -+ } -+ -+ _errno = mac_dev->init(mac_dev); -+ if (unlikely(_errno < 0)) { -+ dev_err(dev, "mac_dev->init() = %d\n", _errno); -+ goto _return_dev_set_drvdata; -+ } -+ -+ /* pause frame autonegotiation enabled*/ -+ mac_dev->autoneg_pause = true; -+ -+ /* by intializing the values to false, force FMD to enable PAUSE frames -+ * on RX and TX -+ */ -+ mac_dev->rx_pause_req = mac_dev->tx_pause_req = true; -+ mac_dev->rx_pause_active = mac_dev->tx_pause_active = false; -+ _errno = set_mac_active_pause(mac_dev, true, true); -+ if (unlikely(_errno < 0)) -+ dev_err(dev, "set_mac_active_pause() = %d\n", _errno); -+ -+ dev_info(dev, -+ "FMan MAC address: %02hx:%02hx:%02hx:%02hx:%02hx:%02hx\n", -+ mac_dev->addr[0], mac_dev->addr[1], mac_dev->addr[2], -+ mac_dev->addr[3], mac_dev->addr[4], mac_dev->addr[5]); -+ -+ goto _return; -+ -+_return_of_node_put: -+ of_node_put(dev_node); -+_return_dev_set_drvdata: -+ dev_set_drvdata(dev, NULL); -+_return: -+ return _errno; -+} -+ -+static int __cold mac_remove(struct platform_device *of_dev) -+{ -+ int i, _errno; -+ struct device *dev; -+ struct mac_device *mac_dev; -+ -+ dev = &of_dev->dev; -+ mac_dev = (struct mac_device *)dev_get_drvdata(dev); -+ -+ for_each_port_device(i, mac_dev->port_dev) -+ fm_port_unbind(mac_dev->port_dev[i]); -+ -+ fm_unbind(mac_dev->fm_dev); -+ -+ _errno = free_macdev(mac_dev); -+ -+ return _errno; -+} -+ -+static struct platform_driver mac_driver = { -+ .driver = { -+ .name = KBUILD_MODNAME, -+ .of_match_table = mac_match, -+ .owner = THIS_MODULE, -+ }, -+ .probe = mac_probe, -+ .remove = mac_remove -+}; -+ -+static int __init __cold mac_load(void) -+{ -+ int _errno; -+ -+ pr_debug(KBUILD_MODNAME ": -> %s:%s()\n", -+ KBUILD_BASENAME".c", __func__); -+ -+ pr_info(KBUILD_MODNAME ": %s\n", mac_driver_description); -+ -+ _errno = platform_driver_register(&mac_driver); -+ if (unlikely(_errno < 0)) { -+ pr_err(KBUILD_MODNAME ": %s:%hu:%s(): platform_driver_register() = %d\n", -+ KBUILD_BASENAME".c", __LINE__, __func__, _errno); -+ goto _return; -+ } -+ -+ goto _return; -+ -+_return: -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+ -+ return _errno; -+} -+module_init(mac_load); -+ -+static void __exit __cold mac_unload(void) -+{ -+ pr_debug(KBUILD_MODNAME ": -> %s:%s()\n", -+ KBUILD_BASENAME".c", __func__); -+ -+ platform_driver_unregister(&mac_driver); -+ -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+} -+module_exit(mac_unload); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac.h -@@ -0,0 +1,134 @@ -+/* Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __MAC_H -+#define __MAC_H -+ -+#include /* struct device, BUS_ID_SIZE */ -+#include /* ETH_ALEN */ -+#include /* phy_interface_t, struct phy_device */ -+#include -+ -+#include "lnxwrp_fsl_fman.h" /* struct port_device */ -+ -+enum {DTSEC, XGMAC, MEMAC}; -+ -+struct mac_device { -+ struct device *dev; -+ void *priv; -+ uint8_t cell_index; -+ struct resource *res; -+ void __iomem *vaddr; -+ uint8_t addr[ETH_ALEN]; -+ bool promisc; -+ -+ struct fm *fm_dev; -+ struct fm_port *port_dev[2]; -+ -+ phy_interface_t phy_if; -+ u32 if_support; -+ bool link; -+ bool half_duplex; -+ uint16_t speed; -+ uint16_t max_speed; -+ struct device_node *phy_node; -+ char fixed_bus_id[MII_BUS_ID_SIZE + 3]; -+ struct device_node *tbi_node; -+ struct phy_device *phy_dev; -+ void *fm; -+ /* List of multicast addresses */ -+ struct list_head mc_addr_list; -+ -+ bool autoneg_pause; -+ bool rx_pause_req; -+ bool tx_pause_req; -+ bool rx_pause_active; -+ bool tx_pause_active; -+ -+ struct fm_mac_dev *(*get_mac_handle)(struct mac_device *mac_dev); -+ int (*init_phy)(struct net_device *net_dev, struct mac_device *mac_dev); -+ int (*init)(struct mac_device *mac_dev); -+ int (*start)(struct mac_device *mac_dev); -+ int (*stop)(struct mac_device *mac_dev); -+ int (*set_promisc)(struct fm_mac_dev *fm_mac_dev, bool enable); -+ int (*change_addr)(struct fm_mac_dev *fm_mac_dev, uint8_t *addr); -+ int (*set_multi)(struct net_device *net_dev, -+ struct mac_device *mac_dev); -+ int (*uninit)(struct fm_mac_dev *fm_mac_dev); -+ int (*ptp_enable)(struct fm_mac_dev *fm_mac_dev); -+ int (*ptp_disable)(struct fm_mac_dev *fm_mac_dev); -+ int (*set_rx_pause)(struct fm_mac_dev *fm_mac_dev, bool en); -+ int (*set_tx_pause)(struct fm_mac_dev *fm_mac_dev, bool en); -+ int (*fm_rtc_enable)(struct fm *fm_dev); -+ int (*fm_rtc_disable)(struct fm *fm_dev); -+ int (*fm_rtc_get_cnt)(struct fm *fm_dev, uint64_t *ts); -+ int (*fm_rtc_set_cnt)(struct fm *fm_dev, uint64_t ts); -+ int (*fm_rtc_get_drift)(struct fm *fm_dev, uint32_t *drift); -+ int (*fm_rtc_set_drift)(struct fm *fm_dev, uint32_t drift); -+ int (*fm_rtc_set_alarm)(struct fm *fm_dev, uint32_t id, uint64_t time); -+ int (*fm_rtc_set_fiper)(struct fm *fm_dev, uint32_t id, -+ uint64_t fiper); -+#ifdef CONFIG_PTP_1588_CLOCK_DPAA -+ int (*fm_rtc_enable_interrupt)(struct fm *fm_dev, uint32_t events); -+ int (*fm_rtc_disable_interrupt)(struct fm *fm_dev, uint32_t events); -+#endif -+ int (*set_wol)(struct fm_port *port, struct fm_mac_dev *fm_mac_dev, -+ bool en); -+ int (*dump_mac_regs)(struct mac_device *h_mac, char *buf, int nn); -+ int (*dump_mac_rx_stats)(struct mac_device *h_mac, char *buf, int nn); -+ int (*dump_mac_tx_stats)(struct mac_device *h_mac, char *buf, int nn); -+}; -+ -+struct mac_address { -+ uint8_t addr[ETH_ALEN]; -+ struct list_head list; -+}; -+ -+#define get_fm_handle(net_dev) \ -+ (((struct dpa_priv_s *)netdev_priv(net_dev))->mac_dev->fm_dev) -+ -+#define for_each_port_device(i, port_dev) \ -+ for (i = 0; i < ARRAY_SIZE(port_dev); i++) -+ -+static inline __attribute((nonnull)) void *macdev_priv( -+ const struct mac_device *mac_dev) -+{ -+ return (void *)mac_dev + sizeof(*mac_dev); -+} -+ -+extern const char *mac_driver_description; -+extern const size_t mac_sizeof_priv[]; -+extern void (*const mac_setup[])(struct mac_device *mac_dev); -+ -+int set_mac_active_pause(struct mac_device *mac_dev, bool rx, bool tx); -+void get_pause_cfg(struct mac_device *mac_dev, bool *rx_pause, bool *tx_pause); -+ -+#endif /* __MAC_H */ ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/offline_port.c -@@ -0,0 +1,848 @@ -+/* Copyright 2011-2012 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* Offline Parsing / Host Command port driver for FSL QorIQ FMan. -+ * Validates device-tree configuration and sets up the offline ports. -+ */ -+ -+#ifdef CONFIG_FSL_DPAA_ETH_DEBUG -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": %s:%hu:%s() " fmt, \ -+ KBUILD_BASENAME".c", __LINE__, __func__ -+#else -+#define pr_fmt(fmt) \ -+ KBUILD_MODNAME ": " fmt -+#endif -+ -+ -+#include -+#include -+#include -+#include -+ -+#include "offline_port.h" -+#include "dpaa_eth.h" -+#include "dpaa_eth_common.h" -+ -+#define OH_MOD_DESCRIPTION "FSL FMan Offline Parsing port driver" -+/* Manip extra space and data alignment for fragmentation */ -+#define FRAG_MANIP_SPACE 128 -+#define FRAG_DATA_ALIGN 64 -+ -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("Bogdan Hamciuc "); -+MODULE_DESCRIPTION(OH_MOD_DESCRIPTION); -+ -+ -+static const struct of_device_id oh_port_match_table[] = { -+ { -+ .compatible = "fsl,dpa-oh" -+ }, -+ { -+ .compatible = "fsl,dpa-oh-shared" -+ }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, oh_port_match_table); -+ -+#ifdef CONFIG_PM -+ -+static int oh_suspend(struct device *dev) -+{ -+ struct dpa_oh_config_s *oh_config; -+ -+ oh_config = dev_get_drvdata(dev); -+ return fm_port_suspend(oh_config->oh_port); -+} -+ -+static int oh_resume(struct device *dev) -+{ -+ struct dpa_oh_config_s *oh_config; -+ -+ oh_config = dev_get_drvdata(dev); -+ return fm_port_resume(oh_config->oh_port); -+} -+ -+static const struct dev_pm_ops oh_pm_ops = { -+ .suspend = oh_suspend, -+ .resume = oh_resume, -+}; -+ -+#define OH_PM_OPS (&oh_pm_ops) -+ -+#else /* CONFIG_PM */ -+ -+#define OH_PM_OPS NULL -+ -+#endif /* CONFIG_PM */ -+ -+/* Creates Frame Queues */ -+static uint32_t oh_fq_create(struct qman_fq *fq, -+ uint32_t fq_id, uint16_t channel, -+ uint16_t wq_id) -+{ -+ struct qm_mcc_initfq fq_opts; -+ uint32_t create_flags, init_flags; -+ uint32_t ret = 0; -+ -+ if (fq == NULL) -+ return 1; -+ -+ /* Set flags for FQ create */ -+ create_flags = QMAN_FQ_FLAG_LOCKED | QMAN_FQ_FLAG_TO_DCPORTAL; -+ -+ /* Create frame queue */ -+ ret = qman_create_fq(fq_id, create_flags, fq); -+ if (ret != 0) -+ return 1; -+ -+ /* Set flags for FQ init */ -+ init_flags = QMAN_INITFQ_FLAG_SCHED; -+ -+ /* Set FQ init options. Specify destination WQ ID and channel */ -+ fq_opts.we_mask = QM_INITFQ_WE_DESTWQ; -+ fq_opts.fqd.dest.wq = wq_id; -+ fq_opts.fqd.dest.channel = channel; -+ -+ /* Initialize frame queue */ -+ ret = qman_init_fq(fq, init_flags, &fq_opts); -+ if (ret != 0) { -+ qman_destroy_fq(fq, 0); -+ return 1; -+ } -+ -+ return 0; -+} -+ -+static void dump_fq(struct device *dev, int fqid, uint16_t channel) -+{ -+ if (channel) { -+ /* display fqs with a valid (!= 0) destination channel */ -+ dev_info(dev, "FQ ID:%d Channel ID:%d\n", fqid, channel); -+ } -+} -+ -+static void dump_fq_duple(struct device *dev, struct qman_fq *fqs, -+ int fqs_count, uint16_t channel_id) -+{ -+ int i; -+ for (i = 0; i < fqs_count; i++) -+ dump_fq(dev, (fqs + i)->fqid, channel_id); -+} -+ -+static void dump_oh_config(struct device *dev, struct dpa_oh_config_s *conf) -+{ -+ struct list_head *fq_list; -+ struct fq_duple *fqd; -+ int i; -+ -+ dev_info(dev, "Default egress frame queue: %d\n", conf->default_fqid); -+ dev_info(dev, "Default error frame queue: %d\n", conf->error_fqid); -+ -+ /* TX queues (old initialization) */ -+ dev_info(dev, "Initialized queues:"); -+ for (i = 0; i < conf->egress_cnt; i++) -+ dump_fq_duple(dev, conf->egress_fqs, conf->egress_cnt, -+ conf->channel); -+ -+ /* initialized ingress queues */ -+ list_for_each(fq_list, &conf->fqs_ingress_list) { -+ fqd = list_entry(fq_list, struct fq_duple, fq_list); -+ dump_fq_duple(dev, fqd->fqs, fqd->fqs_count, fqd->channel_id); -+ } -+ -+ /* initialized egress queues */ -+ list_for_each(fq_list, &conf->fqs_egress_list) { -+ fqd = list_entry(fq_list, struct fq_duple, fq_list); -+ dump_fq_duple(dev, fqd->fqs, fqd->fqs_count, fqd->channel_id); -+ } -+} -+ -+/* Destroys Frame Queues */ -+static void oh_fq_destroy(struct qman_fq *fq) -+{ -+ int _errno = 0; -+ -+ _errno = qman_retire_fq(fq, NULL); -+ if (unlikely(_errno < 0)) -+ pr_err(KBUILD_MODNAME": %s:%hu:%s(): qman_retire_fq(%u)=%d\n", -+ KBUILD_BASENAME".c", __LINE__, __func__, -+ qman_fq_fqid(fq), _errno); -+ -+ _errno = qman_oos_fq(fq); -+ if (unlikely(_errno < 0)) { -+ pr_err(KBUILD_MODNAME": %s:%hu:%s(): qman_oos_fq(%u)=%d\n", -+ KBUILD_BASENAME".c", __LINE__, __func__, -+ qman_fq_fqid(fq), _errno); -+ } -+ -+ qman_destroy_fq(fq, 0); -+} -+ -+/* Allocation code for the OH port's PCD frame queues */ -+static int __cold oh_alloc_pcd_fqids(struct device *dev, -+ uint32_t num, -+ uint8_t alignment, -+ uint32_t *base_fqid) -+{ -+ dev_crit(dev, "callback not implemented!\n"); -+ BUG(); -+ -+ return 0; -+} -+ -+static int __cold oh_free_pcd_fqids(struct device *dev, uint32_t base_fqid) -+{ -+ dev_crit(dev, "callback not implemented!\n"); -+ BUG(); -+ -+ return 0; -+} -+ -+static void oh_set_buffer_layout(struct fm_port *port, -+ struct dpa_buffer_layout_s *layout) -+{ -+ struct fm_port_params params; -+ -+ layout->priv_data_size = DPA_TX_PRIV_DATA_SIZE; -+ layout->parse_results = true; -+ layout->hash_results = true; -+ layout->time_stamp = false; -+ -+ fm_port_get_buff_layout_ext_params(port, ¶ms); -+ layout->manip_extra_space = params.manip_extra_space; -+ layout->data_align = params.data_align; -+} -+ -+static int -+oh_port_probe(struct platform_device *_of_dev) -+{ -+ struct device *dpa_oh_dev; -+ struct device_node *dpa_oh_node; -+ int lenp, _errno = 0, fq_idx, duple_idx; -+ int n_size, i, j, ret, duples_count; -+ struct platform_device *oh_of_dev; -+ struct device_node *oh_node, *bpool_node = NULL, *root_node; -+ struct device *oh_dev; -+ struct dpa_oh_config_s *oh_config = NULL; -+ const __be32 *oh_all_queues; -+ const __be32 *channel_ids; -+ const __be32 *oh_tx_queues; -+ uint32_t queues_count; -+ uint32_t crt_fqid_base; -+ uint32_t crt_fq_count; -+ bool frag_enabled = false; -+ struct fm_port_params oh_port_tx_params; -+ struct fm_port_pcd_param oh_port_pcd_params; -+ struct dpa_buffer_layout_s buf_layout; -+ -+ /* True if the current partition owns the OH port. */ -+ bool init_oh_port; -+ -+ const struct of_device_id *match; -+ int crt_ext_pools_count; -+ u32 ext_pool_size; -+ u32 port_id; -+ u32 channel_id; -+ -+ int channel_ids_count; -+ int channel_idx; -+ struct fq_duple *fqd; -+ struct list_head *fq_list, *fq_list_tmp; -+ -+ const __be32 *bpool_cfg; -+ uint32_t bpid; -+ -+ memset(&oh_port_tx_params, 0, sizeof(oh_port_tx_params)); -+ dpa_oh_dev = &_of_dev->dev; -+ dpa_oh_node = dpa_oh_dev->of_node; -+ BUG_ON(dpa_oh_node == NULL); -+ -+ match = of_match_device(oh_port_match_table, dpa_oh_dev); -+ if (!match) -+ return -EINVAL; -+ -+ dev_dbg(dpa_oh_dev, "Probing OH port...\n"); -+ -+ /* Find the referenced OH node */ -+ oh_node = of_parse_phandle(dpa_oh_node, "fsl,fman-oh-port", 0); -+ if (oh_node == NULL) { -+ dev_err(dpa_oh_dev, -+ "Can't find OH node referenced from node %s\n", -+ dpa_oh_node->full_name); -+ return -EINVAL; -+ } -+ dev_info(dpa_oh_dev, "Found OH node handle compatible with %s\n", -+ match->compatible); -+ -+ _errno = of_property_read_u32(oh_node, "cell-index", &port_id); -+ if (_errno) { -+ dev_err(dpa_oh_dev, "No port id found in node %s\n", -+ dpa_oh_node->full_name); -+ goto return_kfree; -+ } -+ -+ _errno = of_property_read_u32(oh_node, "fsl,qman-channel-id", -+ &channel_id); -+ if (_errno) { -+ dev_err(dpa_oh_dev, "No channel id found in node %s\n", -+ dpa_oh_node->full_name); -+ goto return_kfree; -+ } -+ -+ oh_of_dev = of_find_device_by_node(oh_node); -+ BUG_ON(oh_of_dev == NULL); -+ oh_dev = &oh_of_dev->dev; -+ -+ /* The OH port must be initialized exactly once. -+ * The following scenarios are of interest: -+ * - the node is Linux-private (will always initialize it); -+ * - the node is shared between two Linux partitions -+ * (only one of them will initialize it); -+ * - the node is shared between a Linux and a LWE partition -+ * (Linux will initialize it) - "fsl,dpa-oh-shared" -+ */ -+ -+ /* Check if the current partition owns the OH port -+ * and ought to initialize it. It may be the case that we leave this -+ * to another (also Linux) partition. -+ */ -+ init_oh_port = strcmp(match->compatible, "fsl,dpa-oh-shared"); -+ -+ /* If we aren't the "owner" of the OH node, we're done here. */ -+ if (!init_oh_port) { -+ dev_dbg(dpa_oh_dev, -+ "Not owning the shared OH port %s, will not initialize it.\n", -+ oh_node->full_name); -+ of_node_put(oh_node); -+ return 0; -+ } -+ -+ /* Allocate OH dev private data */ -+ oh_config = devm_kzalloc(dpa_oh_dev, sizeof(*oh_config), GFP_KERNEL); -+ if (oh_config == NULL) { -+ dev_err(dpa_oh_dev, -+ "Can't allocate private data for OH node %s referenced from node %s!\n", -+ oh_node->full_name, dpa_oh_node->full_name); -+ _errno = -ENOMEM; -+ goto return_kfree; -+ } -+ -+ INIT_LIST_HEAD(&oh_config->fqs_ingress_list); -+ INIT_LIST_HEAD(&oh_config->fqs_egress_list); -+ -+ /* FQs that enter OH port */ -+ lenp = 0; -+ oh_all_queues = of_get_property(dpa_oh_node, -+ "fsl,qman-frame-queues-ingress", &lenp); -+ if (lenp % (2 * sizeof(*oh_all_queues))) { -+ dev_warn(dpa_oh_dev, -+ "Wrong ingress queues format for OH node %s referenced from node %s!\n", -+ oh_node->full_name, dpa_oh_node->full_name); -+ /* just ignore the last unpaired value */ -+ } -+ -+ duples_count = lenp / (2 * sizeof(*oh_all_queues)); -+ dev_err(dpa_oh_dev, "Allocating %d ingress frame queues duples\n", -+ duples_count); -+ for (duple_idx = 0; duple_idx < duples_count; duple_idx++) { -+ crt_fqid_base = be32_to_cpu(oh_all_queues[2 * duple_idx]); -+ crt_fq_count = be32_to_cpu(oh_all_queues[2 * duple_idx + 1]); -+ -+ fqd = devm_kzalloc(dpa_oh_dev, -+ sizeof(struct fq_duple), GFP_KERNEL); -+ if (!fqd) { -+ dev_err(dpa_oh_dev, "Can't allocate structures for ingress frame queues for OH node %s referenced from node %s!\n", -+ oh_node->full_name, -+ dpa_oh_node->full_name); -+ _errno = -ENOMEM; -+ goto return_kfree; -+ } -+ -+ fqd->fqs = devm_kzalloc(dpa_oh_dev, -+ crt_fq_count * sizeof(struct qman_fq), -+ GFP_KERNEL); -+ if (!fqd->fqs) { -+ dev_err(dpa_oh_dev, "Can't allocate structures for ingress frame queues for OH node %s referenced from node %s!\n", -+ oh_node->full_name, -+ dpa_oh_node->full_name); -+ _errno = -ENOMEM; -+ goto return_kfree; -+ } -+ -+ for (j = 0; j < crt_fq_count; j++) -+ (fqd->fqs + j)->fqid = crt_fqid_base + j; -+ fqd->fqs_count = crt_fq_count; -+ fqd->channel_id = (uint16_t)channel_id; -+ list_add(&fqd->fq_list, &oh_config->fqs_ingress_list); -+ } -+ -+ /* create the ingress queues */ -+ list_for_each(fq_list, &oh_config->fqs_ingress_list) { -+ fqd = list_entry(fq_list, struct fq_duple, fq_list); -+ -+ for (j = 0; j < fqd->fqs_count; j++) { -+ ret = oh_fq_create(fqd->fqs + j, -+ (fqd->fqs + j)->fqid, -+ fqd->channel_id, 3); -+ if (ret != 0) { -+ dev_err(dpa_oh_dev, "Unable to create ingress frame queue %d for OH node %s referenced from node %s!\n", -+ (fqd->fqs + j)->fqid, -+ oh_node->full_name, -+ dpa_oh_node->full_name); -+ _errno = -EINVAL; -+ goto return_kfree; -+ } -+ } -+ } -+ -+ /* FQs that exit OH port */ -+ lenp = 0; -+ oh_all_queues = of_get_property(dpa_oh_node, -+ "fsl,qman-frame-queues-egress", &lenp); -+ if (lenp % (2 * sizeof(*oh_all_queues))) { -+ dev_warn(dpa_oh_dev, -+ "Wrong egress queues format for OH node %s referenced from node %s!\n", -+ oh_node->full_name, dpa_oh_node->full_name); -+ /* just ignore the last unpaired value */ -+ } -+ -+ duples_count = lenp / (2 * sizeof(*oh_all_queues)); -+ dev_dbg(dpa_oh_dev, "Allocating %d egress frame queues duples\n", -+ duples_count); -+ for (duple_idx = 0; duple_idx < duples_count; duple_idx++) { -+ crt_fqid_base = be32_to_cpu(oh_all_queues[2 * duple_idx]); -+ crt_fq_count = be32_to_cpu(oh_all_queues[2 * duple_idx + 1]); -+ -+ fqd = devm_kzalloc(dpa_oh_dev, -+ sizeof(struct fq_duple), GFP_KERNEL); -+ if (!fqd) { -+ dev_err(dpa_oh_dev, "Can't allocate structures for egress frame queues for OH node %s referenced from node %s!\n", -+ oh_node->full_name, -+ dpa_oh_node->full_name); -+ _errno = -ENOMEM; -+ goto return_kfree; -+ } -+ -+ fqd->fqs = devm_kzalloc(dpa_oh_dev, -+ crt_fq_count * sizeof(struct qman_fq), -+ GFP_KERNEL); -+ if (!fqd->fqs) { -+ dev_err(dpa_oh_dev, -+ "Can't allocate structures for egress frame queues for OH node %s referenced from node %s!\n", -+ oh_node->full_name, -+ dpa_oh_node->full_name); -+ _errno = -ENOMEM; -+ goto return_kfree; -+ } -+ -+ for (j = 0; j < crt_fq_count; j++) -+ (fqd->fqs + j)->fqid = crt_fqid_base + j; -+ fqd->fqs_count = crt_fq_count; -+ /* channel ID is specified in another attribute */ -+ fqd->channel_id = 0; -+ list_add_tail(&fqd->fq_list, &oh_config->fqs_egress_list); -+ -+ /* allocate the queue */ -+ -+ } -+ -+ /* channel_ids for FQs that exit OH port */ -+ lenp = 0; -+ channel_ids = of_get_property(dpa_oh_node, -+ "fsl,qman-channel-ids-egress", &lenp); -+ -+ channel_ids_count = lenp / (sizeof(*channel_ids)); -+ if (channel_ids_count != duples_count) { -+ dev_warn(dpa_oh_dev, -+ "Not all egress queues have a channel id for OH node %s referenced from node %s!\n", -+ oh_node->full_name, dpa_oh_node->full_name); -+ /* just ignore the queues that do not have a Channel ID */ -+ } -+ -+ channel_idx = 0; -+ list_for_each(fq_list, &oh_config->fqs_egress_list) { -+ if (channel_idx + 1 > channel_ids_count) -+ break; -+ fqd = list_entry(fq_list, struct fq_duple, fq_list); -+ fqd->channel_id = -+ (uint16_t)be32_to_cpu(channel_ids[channel_idx++]); -+ } -+ -+ /* create egress queues */ -+ list_for_each(fq_list, &oh_config->fqs_egress_list) { -+ fqd = list_entry(fq_list, struct fq_duple, fq_list); -+ -+ if (fqd->channel_id == 0) { -+ /* missing channel id in dts */ -+ continue; -+ } -+ -+ for (j = 0; j < fqd->fqs_count; j++) { -+ ret = oh_fq_create(fqd->fqs + j, -+ (fqd->fqs + j)->fqid, -+ fqd->channel_id, 3); -+ if (ret != 0) { -+ dev_err(dpa_oh_dev, "Unable to create egress frame queue %d for OH node %s referenced from node %s!\n", -+ (fqd->fqs + j)->fqid, -+ oh_node->full_name, -+ dpa_oh_node->full_name); -+ _errno = -EINVAL; -+ goto return_kfree; -+ } -+ } -+ } -+ -+ /* Read FQ ids/nums for the DPA OH node */ -+ oh_all_queues = of_get_property(dpa_oh_node, -+ "fsl,qman-frame-queues-oh", &lenp); -+ if (oh_all_queues == NULL) { -+ dev_err(dpa_oh_dev, -+ "No frame queues have been defined for OH node %s referenced from node %s\n", -+ oh_node->full_name, dpa_oh_node->full_name); -+ _errno = -EINVAL; -+ goto return_kfree; -+ } -+ -+ /* Check that the OH error and default FQs are there */ -+ BUG_ON(lenp % (2 * sizeof(*oh_all_queues))); -+ queues_count = lenp / (2 * sizeof(*oh_all_queues)); -+ if (queues_count != 2) { -+ dev_err(dpa_oh_dev, -+ "Error and Default queues must be defined for OH node %s referenced from node %s\n", -+ oh_node->full_name, dpa_oh_node->full_name); -+ _errno = -EINVAL; -+ goto return_kfree; -+ } -+ -+ /* Read the FQIDs defined for this OH port */ -+ dev_dbg(dpa_oh_dev, "Reading %d queues...\n", queues_count); -+ fq_idx = 0; -+ -+ /* Error FQID - must be present */ -+ crt_fqid_base = be32_to_cpu(oh_all_queues[fq_idx++]); -+ crt_fq_count = be32_to_cpu(oh_all_queues[fq_idx++]); -+ if (crt_fq_count != 1) { -+ dev_err(dpa_oh_dev, -+ "Only 1 Error FQ allowed in OH node %s referenced from node %s (read: %d FQIDs).\n", -+ oh_node->full_name, dpa_oh_node->full_name, -+ crt_fq_count); -+ _errno = -EINVAL; -+ goto return_kfree; -+ } -+ oh_config->error_fqid = crt_fqid_base; -+ dev_dbg(dpa_oh_dev, "Read Error FQID 0x%x for OH port %s.\n", -+ oh_config->error_fqid, oh_node->full_name); -+ -+ /* Default FQID - must be present */ -+ crt_fqid_base = be32_to_cpu(oh_all_queues[fq_idx++]); -+ crt_fq_count = be32_to_cpu(oh_all_queues[fq_idx++]); -+ if (crt_fq_count != 1) { -+ dev_err(dpa_oh_dev, -+ "Only 1 Default FQ allowed in OH node %s referenced from %s (read: %d FQIDs).\n", -+ oh_node->full_name, dpa_oh_node->full_name, -+ crt_fq_count); -+ _errno = -EINVAL; -+ goto return_kfree; -+ } -+ oh_config->default_fqid = crt_fqid_base; -+ dev_dbg(dpa_oh_dev, "Read Default FQID 0x%x for OH port %s.\n", -+ oh_config->default_fqid, oh_node->full_name); -+ -+ /* TX FQID - presence is optional */ -+ oh_tx_queues = of_get_property(dpa_oh_node, "fsl,qman-frame-queues-tx", -+ &lenp); -+ if (oh_tx_queues == NULL) { -+ dev_dbg(dpa_oh_dev, -+ "No tx queues have been defined for OH node %s referenced from node %s\n", -+ oh_node->full_name, dpa_oh_node->full_name); -+ goto config_port; -+ } -+ -+ /* Check that queues-tx has only a base and a count defined */ -+ BUG_ON(lenp % (2 * sizeof(*oh_tx_queues))); -+ queues_count = lenp / (2 * sizeof(*oh_tx_queues)); -+ if (queues_count != 1) { -+ dev_err(dpa_oh_dev, -+ "TX queues must be defined in only one tuple for OH node %s referenced from node %s\n", -+ oh_node->full_name, dpa_oh_node->full_name); -+ _errno = -EINVAL; -+ goto return_kfree; -+ } -+ -+ fq_idx = 0; -+ crt_fqid_base = be32_to_cpu(oh_tx_queues[fq_idx++]); -+ crt_fq_count = be32_to_cpu(oh_tx_queues[fq_idx++]); -+ oh_config->egress_cnt = crt_fq_count; -+ -+ /* Allocate TX queues */ -+ dev_dbg(dpa_oh_dev, "Allocating %d queues for TX...\n", crt_fq_count); -+ oh_config->egress_fqs = devm_kzalloc(dpa_oh_dev, -+ crt_fq_count * sizeof(struct qman_fq), GFP_KERNEL); -+ if (oh_config->egress_fqs == NULL) { -+ dev_err(dpa_oh_dev, -+ "Can't allocate private data for TX queues for OH node %s referenced from node %s!\n", -+ oh_node->full_name, dpa_oh_node->full_name); -+ _errno = -ENOMEM; -+ goto return_kfree; -+ } -+ -+ /* Create TX queues */ -+ for (i = 0; i < crt_fq_count; i++) { -+ ret = oh_fq_create(oh_config->egress_fqs + i, -+ crt_fqid_base + i, (uint16_t)channel_id, 3); -+ if (ret != 0) { -+ dev_err(dpa_oh_dev, -+ "Unable to create TX frame queue %d for OH node %s referenced from node %s!\n", -+ crt_fqid_base + i, oh_node->full_name, -+ dpa_oh_node->full_name); -+ _errno = -EINVAL; -+ goto return_kfree; -+ } -+ } -+ -+config_port: -+ /* Get a handle to the fm_port so we can set -+ * its configuration params -+ */ -+ oh_config->oh_port = fm_port_bind(oh_dev); -+ if (oh_config->oh_port == NULL) { -+ dev_err(dpa_oh_dev, "NULL drvdata from fm port dev %s!\n", -+ oh_node->full_name); -+ _errno = -EINVAL; -+ goto return_kfree; -+ } -+ -+ oh_set_buffer_layout(oh_config->oh_port, &buf_layout); -+ -+ /* read the pool handlers */ -+ crt_ext_pools_count = of_count_phandle_with_args(dpa_oh_node, -+ "fsl,bman-buffer-pools", NULL); -+ if (crt_ext_pools_count <= 0) { -+ dev_info(dpa_oh_dev, -+ "OH port %s has no buffer pool. Fragmentation will not be enabled\n", -+ oh_node->full_name); -+ goto init_port; -+ } -+ -+ /* used for reading ext_pool_size*/ -+ root_node = of_find_node_by_path("/"); -+ if (root_node == NULL) { -+ dev_err(dpa_oh_dev, "of_find_node_by_path(/) failed\n"); -+ _errno = -EINVAL; -+ goto return_kfree; -+ } -+ -+ n_size = of_n_size_cells(root_node); -+ of_node_put(root_node); -+ -+ dev_dbg(dpa_oh_dev, "OH port number of pools = %d\n", -+ crt_ext_pools_count); -+ -+ oh_port_tx_params.num_pools = (uint8_t)crt_ext_pools_count; -+ -+ for (i = 0; i < crt_ext_pools_count; i++) { -+ bpool_node = of_parse_phandle(dpa_oh_node, -+ "fsl,bman-buffer-pools", i); -+ if (bpool_node == NULL) { -+ dev_err(dpa_oh_dev, "Invalid Buffer pool node\n"); -+ _errno = -EINVAL; -+ goto return_kfree; -+ } -+ -+ _errno = of_property_read_u32(bpool_node, "fsl,bpid", &bpid); -+ if (_errno) { -+ dev_err(dpa_oh_dev, "Invalid Buffer Pool ID\n"); -+ _errno = -EINVAL; -+ goto return_kfree; -+ } -+ -+ oh_port_tx_params.pool_param[i].id = (uint8_t)bpid; -+ dev_dbg(dpa_oh_dev, "OH port bpool id = %u\n", bpid); -+ -+ bpool_cfg = of_get_property(bpool_node, -+ "fsl,bpool-ethernet-cfg", &lenp); -+ if (bpool_cfg == NULL) { -+ dev_err(dpa_oh_dev, "Invalid Buffer pool config params\n"); -+ _errno = -EINVAL; -+ goto return_kfree; -+ } -+ -+ ext_pool_size = of_read_number(bpool_cfg + n_size, n_size); -+ oh_port_tx_params.pool_param[i].size = (uint16_t)ext_pool_size; -+ dev_dbg(dpa_oh_dev, "OH port bpool size = %u\n", -+ ext_pool_size); -+ of_node_put(bpool_node); -+ -+ } -+ -+ if (buf_layout.data_align != FRAG_DATA_ALIGN || -+ buf_layout.manip_extra_space != FRAG_MANIP_SPACE) -+ goto init_port; -+ -+ frag_enabled = true; -+ dev_info(dpa_oh_dev, "IP Fragmentation enabled for OH port %d", -+ port_id); -+ -+init_port: -+ of_node_put(oh_node); -+ /* Set Tx params */ -+ dpaa_eth_init_port(tx, oh_config->oh_port, oh_port_tx_params, -+ oh_config->error_fqid, oh_config->default_fqid, (&buf_layout), -+ frag_enabled); -+ /* Set PCD params */ -+ oh_port_pcd_params.cba = oh_alloc_pcd_fqids; -+ oh_port_pcd_params.cbf = oh_free_pcd_fqids; -+ oh_port_pcd_params.dev = dpa_oh_dev; -+ fm_port_pcd_bind(oh_config->oh_port, &oh_port_pcd_params); -+ -+ dev_set_drvdata(dpa_oh_dev, oh_config); -+ -+ /* Enable the OH port */ -+ _errno = fm_port_enable(oh_config->oh_port); -+ if (_errno) -+ goto return_kfree; -+ -+ dev_info(dpa_oh_dev, "OH port %s enabled.\n", oh_node->full_name); -+ -+ /* print of all referenced & created queues */ -+ dump_oh_config(dpa_oh_dev, oh_config); -+ -+ return 0; -+ -+return_kfree: -+ if (bpool_node) -+ of_node_put(bpool_node); -+ if (oh_node) -+ of_node_put(oh_node); -+ if (oh_config && oh_config->egress_fqs) -+ devm_kfree(dpa_oh_dev, oh_config->egress_fqs); -+ -+ list_for_each_safe(fq_list, fq_list_tmp, &oh_config->fqs_ingress_list) { -+ fqd = list_entry(fq_list, struct fq_duple, fq_list); -+ list_del(fq_list); -+ devm_kfree(dpa_oh_dev, fqd->fqs); -+ devm_kfree(dpa_oh_dev, fqd); -+ } -+ -+ list_for_each_safe(fq_list, fq_list_tmp, &oh_config->fqs_egress_list) { -+ fqd = list_entry(fq_list, struct fq_duple, fq_list); -+ list_del(fq_list); -+ devm_kfree(dpa_oh_dev, fqd->fqs); -+ devm_kfree(dpa_oh_dev, fqd); -+ } -+ -+ devm_kfree(dpa_oh_dev, oh_config); -+ return _errno; -+} -+ -+static int __cold oh_port_remove(struct platform_device *_of_dev) -+{ -+ int _errno = 0, i; -+ struct dpa_oh_config_s *oh_config; -+ -+ pr_info("Removing OH port...\n"); -+ -+ oh_config = dev_get_drvdata(&_of_dev->dev); -+ if (oh_config == NULL) { -+ pr_err(KBUILD_MODNAME -+ ": %s:%hu:%s(): No OH config in device private data!\n", -+ KBUILD_BASENAME".c", __LINE__, __func__); -+ _errno = -ENODEV; -+ goto return_error; -+ } -+ -+ if (oh_config->egress_fqs) -+ for (i = 0; i < oh_config->egress_cnt; i++) -+ oh_fq_destroy(oh_config->egress_fqs + i); -+ -+ if (oh_config->oh_port == NULL) { -+ pr_err(KBUILD_MODNAME -+ ": %s:%hu:%s(): No fm port in device private data!\n", -+ KBUILD_BASENAME".c", __LINE__, __func__); -+ _errno = -EINVAL; -+ goto free_egress_fqs; -+ } -+ -+ _errno = fm_port_disable(oh_config->oh_port); -+ -+free_egress_fqs: -+ if (oh_config->egress_fqs) -+ devm_kfree(&_of_dev->dev, oh_config->egress_fqs); -+ devm_kfree(&_of_dev->dev, oh_config); -+ dev_set_drvdata(&_of_dev->dev, NULL); -+ -+return_error: -+ return _errno; -+} -+ -+static struct platform_driver oh_port_driver = { -+ .driver = { -+ .name = KBUILD_MODNAME, -+ .of_match_table = oh_port_match_table, -+ .owner = THIS_MODULE, -+ .pm = OH_PM_OPS, -+ }, -+ .probe = oh_port_probe, -+ .remove = oh_port_remove -+}; -+ -+static int __init __cold oh_port_load(void) -+{ -+ int _errno; -+ -+ pr_info(OH_MOD_DESCRIPTION "\n"); -+ -+ _errno = platform_driver_register(&oh_port_driver); -+ if (_errno < 0) { -+ pr_err(KBUILD_MODNAME -+ ": %s:%hu:%s(): platform_driver_register() = %d\n", -+ KBUILD_BASENAME".c", __LINE__, __func__, _errno); -+ } -+ -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+ return _errno; -+} -+module_init(oh_port_load); -+ -+static void __exit __cold oh_port_unload(void) -+{ -+ pr_debug(KBUILD_MODNAME ": -> %s:%s()\n", -+ KBUILD_BASENAME".c", __func__); -+ -+ platform_driver_unregister(&oh_port_driver); -+ -+ pr_debug(KBUILD_MODNAME ": %s:%s() ->\n", -+ KBUILD_BASENAME".c", __func__); -+} -+module_exit(oh_port_unload); ---- /dev/null -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/offline_port.h -@@ -0,0 +1,59 @@ -+/* Copyright 2011 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __OFFLINE_PORT_H -+#define __OFFLINE_PORT_H -+ -+struct fm_port; -+struct qman_fq; -+ -+/* fqs are defined in duples (base_fq, fq_count) */ -+struct fq_duple { -+ struct qman_fq *fqs; -+ int fqs_count; -+ uint16_t channel_id; -+ struct list_head fq_list; -+}; -+ -+/* OH port configuration */ -+struct dpa_oh_config_s { -+ uint32_t error_fqid; -+ uint32_t default_fqid; -+ struct fm_port *oh_port; -+ uint32_t egress_cnt; -+ struct qman_fq *egress_fqs; -+ uint16_t channel; -+ -+ struct list_head fqs_ingress_list; -+ struct list_head fqs_egress_list; -+}; -+ -+#endif /* __OFFLINE_PORT_H */ diff --git a/target/linux/layerscape/patches-4.4/7017-fsl_qbman-add-qbman-driver.patch b/target/linux/layerscape/patches-4.4/7017-fsl_qbman-add-qbman-driver.patch deleted file mode 100644 index e7e5d311c8..0000000000 --- a/target/linux/layerscape/patches-4.4/7017-fsl_qbman-add-qbman-driver.patch +++ /dev/null @@ -1,24828 +0,0 @@ -From f6f8ed4784936724154832ff9e4c5afe8caa63e4 Mon Sep 17 00:00:00 2001 -From: Zhao Qiang -Date: Mon, 11 Jul 2016 14:39:18 +0800 -Subject: [PATCH 17/70] fsl_qbman: add qbman driver - -The QMan and BMan are infrastructure components of dpaa, which are used -by both software and hardware for queuing and memory allocation/deallocation. - -Signed-off-by: Roy Pledge Signed-off-by: -Camelia Groza Signed-off-by: Geoff Thorpe - Signed-off-by: Ahmed Mansour - Signed-off-by: Alex Porosanu - Signed-off-by: Pan Jiafei - Signed-off-by: Haiying Wang - -Signed-off-by: Xie Jianhua-B29408 -Signed-off-by: Zhao Qiang ---- - arch/arm/Kconfig | 5 + - arch/powerpc/Kconfig | 9 +- - drivers/misc/Kconfig | 17 + - drivers/staging/Kconfig | 2 + - drivers/staging/Makefile | 1 + - drivers/staging/fsl_qbman/Kconfig | 211 + - drivers/staging/fsl_qbman/Makefile | 28 + - drivers/staging/fsl_qbman/bman_config.c | 705 +++ - drivers/staging/fsl_qbman/bman_debugfs.c | 119 + - drivers/staging/fsl_qbman/bman_driver.c | 574 +++ - drivers/staging/fsl_qbman/bman_high.c | 1141 +++++ - drivers/staging/fsl_qbman/bman_low.h | 559 +++ - drivers/staging/fsl_qbman/bman_private.h | 166 + - drivers/staging/fsl_qbman/bman_test.c | 56 + - drivers/staging/fsl_qbman/bman_test.h | 44 + - drivers/staging/fsl_qbman/bman_test_high.c | 183 + - drivers/staging/fsl_qbman/bman_test_thresh.c | 196 + - drivers/staging/fsl_qbman/dpa_alloc.c | 706 +++ - drivers/staging/fsl_qbman/dpa_sys.h | 259 ++ - drivers/staging/fsl_qbman/dpa_sys_arm.h | 95 + - drivers/staging/fsl_qbman/dpa_sys_arm64.h | 102 + - drivers/staging/fsl_qbman/dpa_sys_ppc32.h | 70 + - drivers/staging/fsl_qbman/dpa_sys_ppc64.h | 79 + - drivers/staging/fsl_qbman/fsl_usdpaa.c | 1982 ++++++++ - drivers/staging/fsl_qbman/fsl_usdpaa_irq.c | 289 ++ - drivers/staging/fsl_qbman/qbman_driver.c | 88 + - drivers/staging/fsl_qbman/qman_config.c | 1199 +++++ - drivers/staging/fsl_qbman/qman_debugfs.c | 1594 +++++++ - drivers/staging/fsl_qbman/qman_driver.c | 980 ++++ - drivers/staging/fsl_qbman/qman_high.c | 5568 +++++++++++++++++++++++ - drivers/staging/fsl_qbman/qman_low.h | 1407 ++++++ - drivers/staging/fsl_qbman/qman_private.h | 398 ++ - drivers/staging/fsl_qbman/qman_test.c | 57 + - drivers/staging/fsl_qbman/qman_test.h | 45 + - drivers/staging/fsl_qbman/qman_test_high.c | 216 + - drivers/staging/fsl_qbman/qman_test_hotpotato.c | 499 ++ - drivers/staging/fsl_qbman/qman_utility.c | 129 + - include/linux/fsl_bman.h | 532 +++ - include/linux/fsl_qman.h | 3889 ++++++++++++++++ - include/linux/fsl_usdpaa.h | 372 ++ - 40 files changed, 24569 insertions(+), 2 deletions(-) - create mode 100644 drivers/staging/fsl_qbman/Kconfig - create mode 100644 drivers/staging/fsl_qbman/Makefile - create mode 100644 drivers/staging/fsl_qbman/bman_config.c - create mode 100644 drivers/staging/fsl_qbman/bman_debugfs.c - create mode 100644 drivers/staging/fsl_qbman/bman_driver.c - create mode 100644 drivers/staging/fsl_qbman/bman_high.c - create mode 100644 drivers/staging/fsl_qbman/bman_low.h - create mode 100644 drivers/staging/fsl_qbman/bman_private.h - create mode 100644 drivers/staging/fsl_qbman/bman_test.c - create mode 100644 drivers/staging/fsl_qbman/bman_test.h - create mode 100644 drivers/staging/fsl_qbman/bman_test_high.c - create mode 100644 drivers/staging/fsl_qbman/bman_test_thresh.c - create mode 100644 drivers/staging/fsl_qbman/dpa_alloc.c - create mode 100644 drivers/staging/fsl_qbman/dpa_sys.h - create mode 100644 drivers/staging/fsl_qbman/dpa_sys_arm.h - create mode 100644 drivers/staging/fsl_qbman/dpa_sys_arm64.h - create mode 100644 drivers/staging/fsl_qbman/dpa_sys_ppc32.h - create mode 100644 drivers/staging/fsl_qbman/dpa_sys_ppc64.h - create mode 100644 drivers/staging/fsl_qbman/fsl_usdpaa.c - create mode 100644 drivers/staging/fsl_qbman/fsl_usdpaa_irq.c - create mode 100644 drivers/staging/fsl_qbman/qbman_driver.c - create mode 100644 drivers/staging/fsl_qbman/qman_config.c - create mode 100644 drivers/staging/fsl_qbman/qman_debugfs.c - create mode 100644 drivers/staging/fsl_qbman/qman_driver.c - create mode 100644 drivers/staging/fsl_qbman/qman_high.c - create mode 100644 drivers/staging/fsl_qbman/qman_low.h - create mode 100644 drivers/staging/fsl_qbman/qman_private.h - create mode 100644 drivers/staging/fsl_qbman/qman_test.c - create mode 100644 drivers/staging/fsl_qbman/qman_test.h - create mode 100644 drivers/staging/fsl_qbman/qman_test_high.c - create mode 100644 drivers/staging/fsl_qbman/qman_test_hotpotato.c - create mode 100644 drivers/staging/fsl_qbman/qman_utility.c - create mode 100644 include/linux/fsl_bman.h - create mode 100644 include/linux/fsl_qman.h - create mode 100644 include/linux/fsl_usdpaa.h - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1250,6 +1250,11 @@ source "arch/arm/common/Kconfig" - - menu "Bus support" - -+config HAS_FSL_QBMAN -+ bool "Datapath Acceleration Queue and Buffer management" -+ help -+ Datapath Acceleration Queue and Buffer management -+ - config ISA - bool - help ---- a/arch/powerpc/Kconfig -+++ b/arch/powerpc/Kconfig -@@ -786,6 +786,11 @@ config FSL_GTM - help - Freescale General-purpose Timers support - -+config HAS_FSL_QBMAN -+ bool "Datapath Acceleration Queue and Buffer management" -+ help -+ Datapath Acceleration Queue and Buffer management -+ - # Yes MCA RS/6000s exist but Linux-PPC does not currently support any - config MCA - bool -@@ -918,14 +923,14 @@ config DYNAMIC_MEMSTART - select NONSTATIC_KERNEL - help - This option enables the kernel to be loaded at any page aligned -- physical address. The kernel creates a mapping from KERNELBASE to -+ physical address. The kernel creates a mapping from KERNELBASE to - the address where the kernel is loaded. The page size here implies - the TLB page size of the mapping for kernel on the particular platform. - Please refer to the init code for finding the TLB page size. - - DYNAMIC_MEMSTART is an easy way of implementing pseudo-RELOCATABLE - kernel image, where the only restriction is the page aligned kernel -- load address. When this option is enabled, the compile time physical -+ load address. When this option is enabled, the compile time physical - address CONFIG_PHYSICAL_START is ignored. - - This option is overridden by CONFIG_RELOCATABLE ---- a/drivers/misc/Kconfig -+++ b/drivers/misc/Kconfig -@@ -236,6 +236,23 @@ config SGI_XP - this feature will allow for direct communication between SSIs - based on a network adapter and DMA messaging. - -+config FSL_USDPAA -+ bool "Freescale USDPAA process driver" -+ depends on FSL_DPA -+ default y -+ help -+ This driver provides user-space access to kernel-managed -+ resource interfaces for USDPAA applications, on the assumption -+ that each process will open this device once. Specifically, this -+ device exposes functionality that would be awkward if exposed -+ via the portal devices - ie. this device exposes functionality -+ that is inherently process-wide rather than portal-specific. -+ This device is necessary for obtaining access to DMA memory and -+ for allocation of Qman and Bman resources. In short, if you wish -+ to use USDPAA applications, you need this. -+ -+ If unsure, say Y. -+ - config CS5535_MFGPT - tristate "CS5535/CS5536 Geode Multi-Function General Purpose Timer (MFGPT) support" - depends on MFD_CS5535 ---- a/drivers/staging/Kconfig -+++ b/drivers/staging/Kconfig -@@ -106,6 +106,8 @@ source "drivers/staging/fbtft/Kconfig" - - source "drivers/staging/fsl-mc/Kconfig" - -+source "drivers/staging/fsl_qbman/Kconfig" -+ - source "drivers/staging/wilc1000/Kconfig" - - source "drivers/staging/most/Kconfig" ---- a/drivers/staging/Makefile -+++ b/drivers/staging/Makefile -@@ -45,5 +45,6 @@ obj-$(CONFIG_UNISYSSPAR) += unisys/ - obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clocking-wizard/ - obj-$(CONFIG_FB_TFT) += fbtft/ - obj-$(CONFIG_FSL_MC_BUS) += fsl-mc/ -+obj-$(CONFIG_FSL_DPA) += fsl_qbman/ - obj-$(CONFIG_WILC1000) += wilc1000/ - obj-$(CONFIG_MOST) += most/ ---- /dev/null -+++ b/drivers/staging/fsl_qbman/Kconfig -@@ -0,0 +1,211 @@ -+config FSL_DPA -+ bool "Freescale Datapath Queue and Buffer management" -+ depends on HAS_FSL_QBMAN -+ default y -+ select FSL_QMAN_FQ_LOOKUP if PPC64 -+ select FSL_QMAN_FQ_LOOKUP if ARM64 -+ -+ -+menu "Freescale Datapath QMan/BMan options" -+ depends on FSL_DPA -+ -+config FSL_DPA_CHECKING -+ bool "additional driver checking" -+ default n -+ ---help--- -+ Compiles in additional checks to sanity-check the drivers and any -+ use of it by other code. Not recommended for performance. -+ -+config FSL_DPA_CAN_WAIT -+ bool -+ default y -+ -+config FSL_DPA_CAN_WAIT_SYNC -+ bool -+ default y -+ -+config FSL_DPA_PIRQ_FAST -+ bool -+ default y -+ -+config FSL_DPA_PIRQ_SLOW -+ bool -+ default y -+ -+config FSL_DPA_PORTAL_SHARE -+ bool -+ default y -+ -+config FSL_BMAN -+ bool "Freescale Buffer Manager (BMan) support" -+ default y -+ -+if FSL_BMAN -+ -+config FSL_BMAN_CONFIG -+ bool "BMan device management" -+ default y -+ ---help--- -+ If this linux image is running natively, you need this option. If this -+ linux image is running as a guest OS under the hypervisor, only one -+ guest OS ("the control plane") needs this option. -+ -+config FSL_BMAN_TEST -+ tristate "BMan self-tests" -+ default n -+ ---help--- -+ This option compiles self-test code for BMan. -+ -+config FSL_BMAN_TEST_HIGH -+ bool "BMan high-level self-test" -+ depends on FSL_BMAN_TEST -+ default y -+ ---help--- -+ This requires the presence of cpu-affine portals, and performs -+ high-level API testing with them (whichever portal(s) are affine to -+ the cpu(s) the test executes on). -+ -+config FSL_BMAN_TEST_THRESH -+ bool "BMan threshold test" -+ depends on FSL_BMAN_TEST -+ default y -+ ---help--- -+ Multi-threaded (SMP) test of BMan pool depletion. A pool is seeded -+ before multiple threads (one per cpu) create pool objects to track -+ depletion state changes. The pool is then drained to empty by a -+ "drainer" thread, and the other threads that they observe exactly -+ the depletion state changes that are expected. -+ -+config FSL_BMAN_DEBUGFS -+ tristate "BMan debugfs interface" -+ depends on DEBUG_FS -+ default y -+ ---help--- -+ This option compiles debugfs code for BMan. -+ -+endif # FSL_BMAN -+ -+config FSL_QMAN -+ bool "Freescale Queue Manager (QMan) support" -+ default y -+ -+if FSL_QMAN -+ -+config FSL_QMAN_POLL_LIMIT -+ int -+ default 32 -+ -+config FSL_QMAN_CONFIG -+ bool "QMan device management" -+ default y -+ ---help--- -+ If this linux image is running natively, you need this option. If this -+ linux image is running as a guest OS under the hypervisor, only one -+ guest OS ("the control plane") needs this option. -+ -+config FSL_QMAN_TEST -+ tristate "QMan self-tests" -+ default n -+ ---help--- -+ This option compiles self-test code for QMan. -+ -+config FSL_QMAN_TEST_STASH_POTATO -+ bool "QMan 'hot potato' data-stashing self-test" -+ depends on FSL_QMAN_TEST -+ default y -+ ---help--- -+ This performs a "hot potato" style test enqueuing/dequeuing a frame -+ across a series of FQs scheduled to different portals (and cpus), with -+ DQRR, data and context stashing always on. -+ -+config FSL_QMAN_TEST_HIGH -+ bool "QMan high-level self-test" -+ depends on FSL_QMAN_TEST -+ default y -+ ---help--- -+ This requires the presence of cpu-affine portals, and performs -+ high-level API testing with them (whichever portal(s) are affine to -+ the cpu(s) the test executes on). -+ -+config FSL_QMAN_DEBUGFS -+ tristate "QMan debugfs interface" -+ depends on DEBUG_FS -+ default y -+ ---help--- -+ This option compiles debugfs code for QMan. -+ -+# H/w settings that can be hard-coded for now. -+config FSL_QMAN_FQD_SZ -+ int "size of Frame Queue Descriptor region" -+ default 10 -+ ---help--- -+ This is the size of the FQD region defined as: PAGE_SIZE * (2^value) -+ ex: 10 => PAGE_SIZE * (2^10) -+ Note: Default device-trees now require minimum Kconfig setting of 10. -+ -+config FSL_QMAN_PFDR_SZ -+ int "size of the PFDR pool" -+ default 13 -+ ---help--- -+ This is the size of the PFDR pool defined as: PAGE_SIZE * (2^value) -+ ex: 13 => PAGE_SIZE * (2^13) -+ -+# Corenet initiator settings. Stash request queues are 4-deep to match cores' -+# ability to snart. Stash priority is 3, other priorities are 2. -+config FSL_QMAN_CI_SCHED_CFG_SRCCIV -+ int -+ depends on FSL_QMAN_CONFIG -+ default 4 -+config FSL_QMAN_CI_SCHED_CFG_SRQ_W -+ int -+ depends on FSL_QMAN_CONFIG -+ default 3 -+config FSL_QMAN_CI_SCHED_CFG_RW_W -+ int -+ depends on FSL_QMAN_CONFIG -+ default 2 -+config FSL_QMAN_CI_SCHED_CFG_BMAN_W -+ int -+ depends on FSL_QMAN_CONFIG -+ default 2 -+ -+# portal interrupt settings -+config FSL_QMAN_PIRQ_DQRR_ITHRESH -+ int -+ default 12 -+config FSL_QMAN_PIRQ_MR_ITHRESH -+ int -+ default 4 -+config FSL_QMAN_PIRQ_IPERIOD -+ int -+ default 100 -+ -+# 64 bit kernel support -+config FSL_QMAN_FQ_LOOKUP -+ bool -+ default n -+ -+config QMAN_CEETM_UPDATE_PERIOD -+ int "Token update period for shaping, in nanoseconds" -+ default 1000 -+ ---help--- -+ Traffic shaping works by performing token calculations (using -+ credits) on shaper instances periodically. This update period -+ sets the granularity for how often those token rate credit -+ updates are performed, and thus determines the accuracy and -+ range of traffic rates that can be configured by users. The -+ reference manual recommends a 1 microsecond period as providing -+ a good balance between granularity and range. -+ -+ Unless you know what you are doing, leave this value at its default. -+ -+config FSL_QMAN_INIT_TIMEOUT -+ int "timeout for qman init stage, in seconds" -+ default 10 -+ ---help--- -+ The timeout setting to quit the initialization loop for non-control -+ partition in case the control partition fails to boot-up. -+ -+endif # FSL_QMAN -+ -+endmenu ---- /dev/null -+++ b/drivers/staging/fsl_qbman/Makefile -@@ -0,0 +1,28 @@ -+subdir-ccflags-y := -Werror -+ -+# Common -+obj-$(CONFIG_FSL_DPA) += dpa_alloc.o -+obj-$(CONFIG_HAS_FSL_QBMAN) += qbman_driver.o -+ -+# Bman -+obj-$(CONFIG_FSL_BMAN) += bman_high.o -+obj-$(CONFIG_FSL_BMAN_CONFIG) += bman_config.o bman_driver.o -+obj-$(CONFIG_FSL_BMAN_TEST) += bman_tester.o -+obj-$(CONFIG_FSL_BMAN_DEBUGFS) += bman_debugfs_interface.o -+bman_tester-y = bman_test.o -+bman_tester-$(CONFIG_FSL_BMAN_TEST_HIGH) += bman_test_high.o -+bman_tester-$(CONFIG_FSL_BMAN_TEST_THRESH) += bman_test_thresh.o -+bman_debugfs_interface-y = bman_debugfs.o -+ -+# Qman -+obj-$(CONFIG_FSL_QMAN) += qman_high.o qman_utility.o -+obj-$(CONFIG_FSL_QMAN_CONFIG) += qman_config.o qman_driver.o -+obj-$(CONFIG_FSL_QMAN_TEST) += qman_tester.o -+qman_tester-y = qman_test.o -+qman_tester-$(CONFIG_FSL_QMAN_TEST_STASH_POTATO) += qman_test_hotpotato.o -+qman_tester-$(CONFIG_FSL_QMAN_TEST_HIGH) += qman_test_high.o -+obj-$(CONFIG_FSL_QMAN_DEBUGFS) += qman_debugfs_interface.o -+qman_debugfs_interface-y = qman_debugfs.o -+ -+# USDPAA -+obj-$(CONFIG_FSL_USDPAA) += fsl_usdpaa.o fsl_usdpaa_irq.o ---- /dev/null -+++ b/drivers/staging/fsl_qbman/bman_config.c -@@ -0,0 +1,705 @@ -+/* Copyright (c) 2009-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include "bman_private.h" -+#include -+ -+/* Last updated for v00.79 of the BG */ -+ -+struct bman; -+ -+/* Register offsets */ -+#define REG_POOL_SWDET(n) (0x0000 + ((n) * 0x04)) -+#define REG_POOL_HWDET(n) (0x0100 + ((n) * 0x04)) -+#define REG_POOL_SWDXT(n) (0x0200 + ((n) * 0x04)) -+#define REG_POOL_HWDXT(n) (0x0300 + ((n) * 0x04)) -+#define REG_POOL_CONTENT(n) (0x0600 + ((n) * 0x04)) -+#define REG_FBPR_FPC 0x0800 -+#define REG_STATE_IDLE 0x960 -+#define REG_STATE_STOP 0x964 -+#define REG_ECSR 0x0a00 -+#define REG_ECIR 0x0a04 -+#define REG_EADR 0x0a08 -+#define REG_EDATA(n) (0x0a10 + ((n) * 0x04)) -+#define REG_SBEC(n) (0x0a80 + ((n) * 0x04)) -+#define REG_IP_REV_1 0x0bf8 -+#define REG_IP_REV_2 0x0bfc -+#define REG_FBPR_BARE 0x0c00 -+#define REG_FBPR_BAR 0x0c04 -+#define REG_FBPR_AR 0x0c10 -+#define REG_SRCIDR 0x0d04 -+#define REG_LIODNR 0x0d08 -+#define REG_ERR_ISR 0x0e00 /* + "enum bm_isr_reg" */ -+ -+/* Used by all error interrupt registers except 'inhibit' */ -+#define BM_EIRQ_IVCI 0x00000010 /* Invalid Command Verb */ -+#define BM_EIRQ_FLWI 0x00000008 /* FBPR Low Watermark */ -+#define BM_EIRQ_MBEI 0x00000004 /* Multi-bit ECC Error */ -+#define BM_EIRQ_SBEI 0x00000002 /* Single-bit ECC Error */ -+#define BM_EIRQ_BSCN 0x00000001 /* pool State Change Notification */ -+ -+/* BMAN_ECIR valid error bit */ -+#define PORTAL_ECSR_ERR (BM_EIRQ_IVCI) -+ -+union bman_ecir { -+ u32 ecir_raw; -+ struct { -+ u32 __reserved1:4; -+ u32 portal_num:4; -+ u32 __reserved2:12; -+ u32 numb:4; -+ u32 __reserved3:2; -+ u32 pid:6; -+ } __packed info; -+}; -+ -+union bman_eadr { -+ u32 eadr_raw; -+ struct { -+ u32 __reserved1:5; -+ u32 memid:3; -+ u32 __reserved2:14; -+ u32 eadr:10; -+ } __packed info; -+}; -+ -+struct bman_hwerr_txt { -+ u32 mask; -+ const char *txt; -+}; -+ -+#define BMAN_HWE_TXT(a, b) { .mask = BM_EIRQ_##a, .txt = b } -+ -+static const struct bman_hwerr_txt bman_hwerr_txts[] = { -+ BMAN_HWE_TXT(IVCI, "Invalid Command Verb"), -+ BMAN_HWE_TXT(FLWI, "FBPR Low Watermark"), -+ BMAN_HWE_TXT(MBEI, "Multi-bit ECC Error"), -+ BMAN_HWE_TXT(SBEI, "Single-bit ECC Error"), -+ BMAN_HWE_TXT(BSCN, "Pool State Change Notification"), -+}; -+#define BMAN_HWE_COUNT (sizeof(bman_hwerr_txts)/sizeof(struct bman_hwerr_txt)) -+ -+struct bman_error_info_mdata { -+ u16 addr_mask; -+ u16 bits; -+ const char *txt; -+}; -+ -+#define BMAN_ERR_MDATA(a, b, c) { .addr_mask = a, .bits = b, .txt = c} -+static const struct bman_error_info_mdata error_mdata[] = { -+ BMAN_ERR_MDATA(0x03FF, 192, "Stockpile memory"), -+ BMAN_ERR_MDATA(0x00FF, 256, "SW portal ring memory port 1"), -+ BMAN_ERR_MDATA(0x00FF, 256, "SW portal ring memory port 2"), -+}; -+#define BMAN_ERR_MDATA_COUNT \ -+ (sizeof(error_mdata)/sizeof(struct bman_error_info_mdata)) -+ -+/* Add this in Kconfig */ -+#define BMAN_ERRS_TO_UNENABLE (BM_EIRQ_FLWI) -+ -+/** -+ * bm_err_isr__ - Manipulate global interrupt registers -+ * @v: for accessors that write values, this is the 32-bit value -+ * -+ * Manipulates BMAN_ERR_ISR, BMAN_ERR_IER, BMAN_ERR_ISDR, BMAN_ERR_IIR. All -+ * manipulations except bm_err_isr_[un]inhibit() use 32-bit masks composed of -+ * the BM_EIRQ_*** definitions. Note that "bm_err_isr_enable_write" means -+ * "write the enable register" rather than "enable the write register"! -+ */ -+#define bm_err_isr_status_read(bm) \ -+ __bm_err_isr_read(bm, bm_isr_status) -+#define bm_err_isr_status_clear(bm, m) \ -+ __bm_err_isr_write(bm, bm_isr_status, m) -+#define bm_err_isr_enable_read(bm) \ -+ __bm_err_isr_read(bm, bm_isr_enable) -+#define bm_err_isr_enable_write(bm, v) \ -+ __bm_err_isr_write(bm, bm_isr_enable, v) -+#define bm_err_isr_disable_read(bm) \ -+ __bm_err_isr_read(bm, bm_isr_disable) -+#define bm_err_isr_disable_write(bm, v) \ -+ __bm_err_isr_write(bm, bm_isr_disable, v) -+#define bm_err_isr_inhibit(bm) \ -+ __bm_err_isr_write(bm, bm_isr_inhibit, 1) -+#define bm_err_isr_uninhibit(bm) \ -+ __bm_err_isr_write(bm, bm_isr_inhibit, 0) -+ -+/* -+ * TODO: unimplemented registers -+ * -+ * BMAN_POOLk_SDCNT, BMAN_POOLk_HDCNT, BMAN_FULT, -+ * BMAN_VLDPL, BMAN_EECC, BMAN_SBET, BMAN_EINJ -+ */ -+ -+/* Encapsulate "struct bman *" as a cast of the register space address. */ -+ -+static struct bman *bm_create(void *regs) -+{ -+ return (struct bman *)regs; -+} -+ -+static inline u32 __bm_in(struct bman *bm, u32 offset) -+{ -+ return in_be32((void *)bm + offset); -+} -+static inline void __bm_out(struct bman *bm, u32 offset, u32 val) -+{ -+ out_be32((void *)bm + offset, val); -+} -+#define bm_in(reg) __bm_in(bm, REG_##reg) -+#define bm_out(reg, val) __bm_out(bm, REG_##reg, val) -+ -+static u32 __bm_err_isr_read(struct bman *bm, enum bm_isr_reg n) -+{ -+ return __bm_in(bm, REG_ERR_ISR + (n << 2)); -+} -+ -+static void __bm_err_isr_write(struct bman *bm, enum bm_isr_reg n, u32 val) -+{ -+ __bm_out(bm, REG_ERR_ISR + (n << 2), val); -+} -+ -+static void bm_get_version(struct bman *bm, u16 *id, u8 *major, u8 *minor) -+{ -+ u32 v = bm_in(IP_REV_1); -+ *id = (v >> 16); -+ *major = (v >> 8) & 0xff; -+ *minor = v & 0xff; -+} -+ -+static u32 __generate_thresh(u32 val, int roundup) -+{ -+ u32 e = 0; /* co-efficient, exponent */ -+ int oddbit = 0; -+ while (val > 0xff) { -+ oddbit = val & 1; -+ val >>= 1; -+ e++; -+ if (roundup && oddbit) -+ val++; -+ } -+ DPA_ASSERT(e < 0x10); -+ return val | (e << 8); -+} -+ -+static void bm_set_pool(struct bman *bm, u8 pool, u32 swdet, u32 swdxt, -+ u32 hwdet, u32 hwdxt) -+{ -+ DPA_ASSERT(pool < bman_pool_max); -+ bm_out(POOL_SWDET(pool), __generate_thresh(swdet, 0)); -+ bm_out(POOL_SWDXT(pool), __generate_thresh(swdxt, 1)); -+ bm_out(POOL_HWDET(pool), __generate_thresh(hwdet, 0)); -+ bm_out(POOL_HWDXT(pool), __generate_thresh(hwdxt, 1)); -+} -+ -+static void bm_set_memory(struct bman *bm, u64 ba, int prio, u32 size) -+{ -+ u32 exp = ilog2(size); -+ /* choke if size isn't within range */ -+ DPA_ASSERT((size >= 4096) && (size <= 1073741824) && -+ is_power_of_2(size)); -+ /* choke if '[e]ba' has lower-alignment than 'size' */ -+ DPA_ASSERT(!(ba & (size - 1))); -+ bm_out(FBPR_BARE, upper_32_bits(ba)); -+ bm_out(FBPR_BAR, lower_32_bits(ba)); -+ bm_out(FBPR_AR, (prio ? 0x40000000 : 0) | (exp - 1)); -+} -+ -+/*****************/ -+/* Config driver */ -+/*****************/ -+ -+/* TODO: Kconfig these? */ -+#define DEFAULT_FBPR_SZ (PAGE_SIZE << 12) -+ -+/* We support only one of these. */ -+static struct bman *bm; -+static struct device_node *bm_node; -+ -+/* And this state belongs to 'bm'. It is set during fsl_bman_init(), but used -+ * during bman_init_ccsr(). */ -+static dma_addr_t fbpr_a; -+static size_t fbpr_sz = DEFAULT_FBPR_SZ; -+ -+static int bman_fbpr(struct reserved_mem *rmem) -+{ -+ fbpr_a = rmem->base; -+ fbpr_sz = rmem->size; -+ -+ WARN_ON(!(fbpr_a && fbpr_sz)); -+ -+ return 0; -+} -+RESERVEDMEM_OF_DECLARE(bman_fbpr, "fsl,bman-fbpr", bman_fbpr); -+ -+static int __init fsl_bman_init(struct device_node *node) -+{ -+ struct resource res; -+ u32 __iomem *regs; -+ const char *s; -+ int ret, standby = 0; -+ u16 id; -+ u8 major, minor; -+ -+ ret = of_address_to_resource(node, 0, &res); -+ if (ret) { -+ pr_err("Can't get %s property 'reg'\n", -+ node->full_name); -+ return ret; -+ } -+ s = of_get_property(node, "fsl,hv-claimable", &ret); -+ if (s && !strcmp(s, "standby")) -+ standby = 1; -+ /* Global configuration */ -+ regs = ioremap(res.start, res.end - res.start + 1); -+ bm = bm_create(regs); -+ BUG_ON(!bm); -+ bm_node = node; -+ bm_get_version(bm, &id, &major, &minor); -+ pr_info("Bman ver:%04x,%02x,%02x\n", id, major, minor); -+ if ((major == 1) && (minor == 0)) { -+ bman_ip_rev = BMAN_REV10; -+ bman_pool_max = 64; -+ } else if ((major == 2) && (minor == 0)) { -+ bman_ip_rev = BMAN_REV20; -+ bman_pool_max = 8; -+ } else if ((major == 2) && (minor == 1)) { -+ bman_ip_rev = BMAN_REV21; -+ bman_pool_max = 64; -+ } else { -+ pr_warn("unknown Bman version, default to rev1.0\n"); -+ } -+ -+ if (standby) { -+ pr_info(" -> in standby mode\n"); -+ return 0; -+ } -+ return 0; -+} -+ -+int bman_have_ccsr(void) -+{ -+ return bm ? 1 : 0; -+} -+ -+int bm_pool_set(u32 bpid, const u32 *thresholds) -+{ -+ if (!bm) -+ return -ENODEV; -+ bm_set_pool(bm, bpid, thresholds[0], -+ thresholds[1], thresholds[2], -+ thresholds[3]); -+ return 0; -+} -+EXPORT_SYMBOL(bm_pool_set); -+ -+__init int bman_init_early(void) -+{ -+ struct device_node *dn; -+ int ret; -+ -+ for_each_compatible_node(dn, NULL, "fsl,bman") { -+ if (bm) -+ pr_err("%s: only one 'fsl,bman' allowed\n", -+ dn->full_name); -+ else { -+ if (!of_device_is_available(dn)) -+ continue; -+ -+ ret = fsl_bman_init(dn); -+ BUG_ON(ret); -+ } -+ } -+ return 0; -+} -+postcore_initcall_sync(bman_init_early); -+ -+ -+static void log_edata_bits(u32 bit_count) -+{ -+ u32 i, j, mask = 0xffffffff; -+ -+ pr_warn("Bman ErrInt, EDATA:\n"); -+ i = bit_count/32; -+ if (bit_count%32) { -+ i++; -+ mask = ~(mask << bit_count%32); -+ } -+ j = 16-i; -+ pr_warn(" 0x%08x\n", bm_in(EDATA(j)) & mask); -+ j++; -+ for (; j < 16; j++) -+ pr_warn(" 0x%08x\n", bm_in(EDATA(j))); -+} -+ -+static void log_additional_error_info(u32 isr_val, u32 ecsr_val) -+{ -+ union bman_ecir ecir_val; -+ union bman_eadr eadr_val; -+ -+ ecir_val.ecir_raw = bm_in(ECIR); -+ /* Is portal info valid */ -+ if (ecsr_val & PORTAL_ECSR_ERR) { -+ pr_warn("Bman ErrInt: SWP id %d, numb %d, pid %d\n", -+ ecir_val.info.portal_num, ecir_val.info.numb, -+ ecir_val.info.pid); -+ } -+ if (ecsr_val & (BM_EIRQ_SBEI|BM_EIRQ_MBEI)) { -+ eadr_val.eadr_raw = bm_in(EADR); -+ pr_warn("Bman ErrInt: EADR Memory: %s, 0x%x\n", -+ error_mdata[eadr_val.info.memid].txt, -+ error_mdata[eadr_val.info.memid].addr_mask -+ & eadr_val.info.eadr); -+ log_edata_bits(error_mdata[eadr_val.info.memid].bits); -+ } -+} -+ -+/* Bman interrupt handler */ -+static irqreturn_t bman_isr(int irq, void *ptr) -+{ -+ u32 isr_val, ier_val, ecsr_val, isr_mask, i; -+ -+ ier_val = bm_err_isr_enable_read(bm); -+ isr_val = bm_err_isr_status_read(bm); -+ ecsr_val = bm_in(ECSR); -+ isr_mask = isr_val & ier_val; -+ -+ if (!isr_mask) -+ return IRQ_NONE; -+ for (i = 0; i < BMAN_HWE_COUNT; i++) { -+ if (bman_hwerr_txts[i].mask & isr_mask) { -+ pr_warn("Bman ErrInt: %s\n", bman_hwerr_txts[i].txt); -+ if (bman_hwerr_txts[i].mask & ecsr_val) { -+ log_additional_error_info(isr_mask, ecsr_val); -+ /* Re-arm error capture registers */ -+ bm_out(ECSR, ecsr_val); -+ } -+ if (bman_hwerr_txts[i].mask & BMAN_ERRS_TO_UNENABLE) { -+ pr_devel("Bman un-enabling error 0x%x\n", -+ bman_hwerr_txts[i].mask); -+ ier_val &= ~bman_hwerr_txts[i].mask; -+ bm_err_isr_enable_write(bm, ier_val); -+ } -+ } -+ } -+ bm_err_isr_status_clear(bm, isr_val); -+ return IRQ_HANDLED; -+} -+ -+static int __bind_irq(void) -+{ -+ int ret, err_irq; -+ -+ err_irq = of_irq_to_resource(bm_node, 0, NULL); -+ if (err_irq == 0) { -+ pr_info("Can't get %s property '%s'\n", bm_node->full_name, -+ "interrupts"); -+ return -ENODEV; -+ } -+ ret = request_irq(err_irq, bman_isr, IRQF_SHARED, "bman-err", bm_node); -+ if (ret) { -+ pr_err("request_irq() failed %d for '%s'\n", ret, -+ bm_node->full_name); -+ return -ENODEV; -+ } -+ /* Disable Buffer Pool State Change */ -+ bm_err_isr_disable_write(bm, BM_EIRQ_BSCN); -+ /* Write-to-clear any stale bits, (eg. starvation being asserted prior -+ * to resource allocation during driver init). */ -+ bm_err_isr_status_clear(bm, 0xffffffff); -+ /* Enable Error Interrupts */ -+ bm_err_isr_enable_write(bm, 0xffffffff); -+ return 0; -+} -+ -+int bman_init_ccsr(struct device_node *node) -+{ -+ int ret; -+ if (!bman_have_ccsr()) -+ return 0; -+ if (node != bm_node) -+ return -EINVAL; -+ /* FBPR memory */ -+ bm_set_memory(bm, fbpr_a, 0, fbpr_sz); -+ pr_info("bman-fbpr addr 0x%llx size 0x%zx\n", -+ (unsigned long long)fbpr_a, fbpr_sz); -+ -+ ret = __bind_irq(); -+ if (ret) -+ return ret; -+ return 0; -+} -+ -+u32 bm_pool_free_buffers(u32 bpid) -+{ -+ return bm_in(POOL_CONTENT(bpid)); -+} -+ -+#ifdef CONFIG_SYSFS -+ -+#define DRV_NAME "fsl-bman" -+#define SBEC_MAX_ID 1 -+#define SBEC_MIN_ID 0 -+ -+static ssize_t show_fbpr_fpc(struct device *dev, -+ struct device_attribute *dev_attr, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%u\n", bm_in(FBPR_FPC)); -+}; -+ -+static ssize_t show_pool_count(struct device *dev, -+ struct device_attribute *dev_attr, char *buf) -+{ -+ u32 data; -+ int i; -+ -+ if (!sscanf(dev_attr->attr.name, "%d", &i) || (i >= bman_pool_max)) -+ return -EINVAL; -+ data = bm_in(POOL_CONTENT(i)); -+ return snprintf(buf, PAGE_SIZE, "%d\n", data); -+}; -+ -+static ssize_t show_err_isr(struct device *dev, -+ struct device_attribute *dev_attr, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "0x%08x\n", bm_in(ERR_ISR)); -+}; -+ -+static ssize_t show_sbec(struct device *dev, -+ struct device_attribute *dev_attr, char *buf) -+{ -+ int i; -+ -+ if (!sscanf(dev_attr->attr.name, "sbec_%d", &i)) -+ return -EINVAL; -+ if (i < SBEC_MIN_ID || i > SBEC_MAX_ID) -+ return -EINVAL; -+ return snprintf(buf, PAGE_SIZE, "%u\n", bm_in(SBEC(i))); -+}; -+ -+static DEVICE_ATTR(err_isr, S_IRUSR, show_err_isr, NULL); -+static DEVICE_ATTR(fbpr_fpc, S_IRUSR, show_fbpr_fpc, NULL); -+ -+/* Didn't use DEVICE_ATTR as 64 of this would be required. -+ * Initialize them when needed. */ -+static char *name_attrs_pool_count; /* "xx" + null-terminator */ -+static struct device_attribute *dev_attr_buffer_pool_count; -+ -+static DEVICE_ATTR(sbec_0, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_1, S_IRUSR, show_sbec, NULL); -+ -+static struct attribute *bman_dev_attributes[] = { -+ &dev_attr_fbpr_fpc.attr, -+ &dev_attr_err_isr.attr, -+ NULL -+}; -+ -+static struct attribute *bman_dev_ecr_attributes[] = { -+ &dev_attr_sbec_0.attr, -+ &dev_attr_sbec_1.attr, -+ NULL -+}; -+ -+static struct attribute **bman_dev_pool_count_attributes; -+ -+ -+/* root level */ -+static const struct attribute_group bman_dev_attr_grp = { -+ .name = NULL, -+ .attrs = bman_dev_attributes -+}; -+static const struct attribute_group bman_dev_ecr_grp = { -+ .name = "error_capture", -+ .attrs = bman_dev_ecr_attributes -+}; -+static struct attribute_group bman_dev_pool_countent_grp = { -+ .name = "pool_count", -+}; -+ -+static int of_fsl_bman_remove(struct platform_device *ofdev) -+{ -+ sysfs_remove_group(&ofdev->dev.kobj, &bman_dev_attr_grp); -+ return 0; -+}; -+ -+static int of_fsl_bman_probe(struct platform_device *ofdev) -+{ -+ int ret, i; -+ -+ ret = sysfs_create_group(&ofdev->dev.kobj, &bman_dev_attr_grp); -+ if (ret) -+ goto done; -+ ret = sysfs_create_group(&ofdev->dev.kobj, &bman_dev_ecr_grp); -+ if (ret) -+ goto del_group_0; -+ -+ name_attrs_pool_count = kmalloc(sizeof(char) * bman_pool_max * 3, -+ GFP_KERNEL); -+ if (!name_attrs_pool_count) { -+ pr_err("Can't alloc name_attrs_pool_count\n"); -+ goto del_group_1; -+ } -+ -+ dev_attr_buffer_pool_count = kmalloc(sizeof(struct device_attribute) * -+ bman_pool_max, GFP_KERNEL); -+ if (!dev_attr_buffer_pool_count) { -+ pr_err("Can't alloc dev_attr-buffer_pool_count\n"); -+ goto del_group_2; -+ } -+ -+ bman_dev_pool_count_attributes = kmalloc(sizeof(struct attribute *) * -+ (bman_pool_max + 1), GFP_KERNEL); -+ if (!bman_dev_pool_count_attributes) { -+ pr_err("can't alloc bman_dev_pool_count_attributes\n"); -+ goto del_group_3; -+ } -+ -+ for (i = 0; i < bman_pool_max; i++) { -+ ret = scnprintf((name_attrs_pool_count + i * 3), 3, "%d", i); -+ if (!ret) -+ goto del_group_4; -+ dev_attr_buffer_pool_count[i].attr.name = -+ (name_attrs_pool_count + i * 3); -+ dev_attr_buffer_pool_count[i].attr.mode = S_IRUSR; -+ dev_attr_buffer_pool_count[i].show = show_pool_count; -+ bman_dev_pool_count_attributes[i] = -+ &dev_attr_buffer_pool_count[i].attr; -+ sysfs_attr_init(bman_dev_pool_count_attributes[i]); -+ } -+ bman_dev_pool_count_attributes[bman_pool_max] = NULL; -+ -+ bman_dev_pool_countent_grp.attrs = bman_dev_pool_count_attributes; -+ -+ ret = sysfs_create_group(&ofdev->dev.kobj, &bman_dev_pool_countent_grp); -+ if (ret) -+ goto del_group_4; -+ -+ goto done; -+ -+del_group_4: -+ kfree(bman_dev_pool_count_attributes); -+del_group_3: -+ kfree(dev_attr_buffer_pool_count); -+del_group_2: -+ kfree(name_attrs_pool_count); -+del_group_1: -+ sysfs_remove_group(&ofdev->dev.kobj, &bman_dev_ecr_grp); -+del_group_0: -+ sysfs_remove_group(&ofdev->dev.kobj, &bman_dev_attr_grp); -+done: -+ if (ret) -+ dev_err(&ofdev->dev, -+ "Cannot create dev attributes ret=%d\n", ret); -+ return ret; -+}; -+ -+static struct of_device_id of_fsl_bman_ids[] = { -+ { -+ .compatible = "fsl,bman", -+ }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, of_fsl_bman_ids); -+ -+#ifdef CONFIG_SUSPEND -+static u32 saved_isdr; -+ -+static int bman_pm_suspend_noirq(struct device *dev) -+{ -+ uint32_t idle_state; -+ -+ suspend_unused_bportal(); -+ /* save isdr, disable all, clear isr */ -+ saved_isdr = bm_err_isr_disable_read(bm); -+ bm_err_isr_disable_write(bm, 0xffffffff); -+ bm_err_isr_status_clear(bm, 0xffffffff); -+ -+ if (bman_ip_rev < BMAN_REV21) { -+#ifdef CONFIG_PM_DEBUG -+ pr_info("Bman version doesn't have STATE_IDLE\n"); -+#endif -+ return 0; -+ } -+ idle_state = bm_in(STATE_IDLE); -+ if (!(idle_state & 0x1)) { -+ pr_err("Bman not idle 0x%x aborting\n", idle_state); -+ bm_err_isr_disable_write(bm, saved_isdr); -+ resume_unused_bportal(); -+ return -EBUSY; -+ } -+#ifdef CONFIG_PM_DEBUG -+ pr_info("Bman suspend code, IDLE_STAT = 0x%x\n", idle_state); -+#endif -+ return 0; -+} -+ -+static int bman_pm_resume_noirq(struct device *dev) -+{ -+ /* restore isdr */ -+ bm_err_isr_disable_write(bm, saved_isdr); -+ resume_unused_bportal(); -+ return 0; -+} -+#else -+#define bman_pm_suspend_noirq NULL -+#define bman_pm_resume_noirq NULL -+#endif -+ -+static const struct dev_pm_ops bman_pm_ops = { -+ .suspend_noirq = bman_pm_suspend_noirq, -+ .resume_noirq = bman_pm_resume_noirq, -+}; -+ -+static struct platform_driver of_fsl_bman_driver = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = DRV_NAME, -+ .of_match_table = of_fsl_bman_ids, -+ .pm = &bman_pm_ops, -+ }, -+ .probe = of_fsl_bman_probe, -+ .remove = of_fsl_bman_remove, -+}; -+ -+static int bman_ctrl_init(void) -+{ -+ return platform_driver_register(&of_fsl_bman_driver); -+} -+ -+static void bman_ctrl_exit(void) -+{ -+ platform_driver_unregister(&of_fsl_bman_driver); -+} -+ -+module_init(bman_ctrl_init); -+module_exit(bman_ctrl_exit); -+ -+#endif /* CONFIG_SYSFS */ ---- /dev/null -+++ b/drivers/staging/fsl_qbman/bman_debugfs.c -@@ -0,0 +1,119 @@ -+/* Copyright 2010-2011 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include -+#include -+#include -+#include -+#include -+ -+static struct dentry *dfs_root; /* debugfs root directory */ -+ -+/******************************************************************************* -+ * Query Buffer Pool State -+ ******************************************************************************/ -+static int query_bp_state_show(struct seq_file *file, void *offset) -+{ -+ int ret; -+ struct bm_pool_state state; -+ int i, j; -+ u32 mask; -+ -+ memset(&state, 0, sizeof(struct bm_pool_state)); -+ ret = bman_query_pools(&state); -+ if (ret) { -+ seq_printf(file, "Error %d\n", ret); -+ return 0; -+ } -+ seq_puts(file, "bp_id free_buffers_avail bp_depleted\n"); -+ for (i = 0; i < 2; i++) { -+ mask = 0x80000000; -+ for (j = 0; j < 32; j++) { -+ seq_printf(file, -+ " %-2u %-3s %-3s\n", -+ (i*32)+j, -+ (state.as.state.__state[i] & mask) ? "no" : "yes", -+ (state.ds.state.__state[i] & mask) ? "yes" : "no"); -+ mask >>= 1; -+ } -+ } -+ return 0; -+} -+ -+static int query_bp_state_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, query_bp_state_show, NULL); -+} -+ -+static const struct file_operations query_bp_state_fops = { -+ .owner = THIS_MODULE, -+ .open = query_bp_state_open, -+ .read = seq_read, -+ .release = single_release, -+}; -+ -+static int __init bman_debugfs_module_init(void) -+{ -+ int ret = 0; -+ struct dentry *d; -+ -+ dfs_root = debugfs_create_dir("bman", NULL); -+ -+ if (dfs_root == NULL) { -+ ret = -ENOMEM; -+ pr_err("Cannot create bman debugfs dir\n"); -+ goto _return; -+ } -+ d = debugfs_create_file("query_bp_state", -+ S_IRUGO, -+ dfs_root, -+ NULL, -+ &query_bp_state_fops); -+ if (d == NULL) { -+ ret = -ENOMEM; -+ pr_err("Cannot create query_bp_state\n"); -+ goto _return; -+ } -+ return 0; -+ -+_return: -+ debugfs_remove_recursive(dfs_root); -+ return ret; -+} -+ -+static void __exit bman_debugfs_module_exit(void) -+{ -+ debugfs_remove_recursive(dfs_root); -+} -+ -+ -+module_init(bman_debugfs_module_init); -+module_exit(bman_debugfs_module_exit); -+MODULE_LICENSE("Dual BSD/GPL"); ---- /dev/null -+++ b/drivers/staging/fsl_qbman/bman_driver.c -@@ -0,0 +1,574 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include "bman_low.h" -+#ifdef CONFIG_HOTPLUG_CPU -+#include -+#endif -+/* -+ * Global variables of the max portal/pool number this bman version supported -+ */ -+u16 bman_ip_rev; -+EXPORT_SYMBOL(bman_ip_rev); -+u16 bman_pool_max; -+EXPORT_SYMBOL(bman_pool_max); -+static u16 bman_portal_max; -+ -+/* After initialising cpus that own shared portal configs, we cache the -+ * resulting portals (ie. not just the configs) in this array. Then we -+ * initialise slave cpus that don't have their own portals, redirecting them to -+ * portals from this cache in a round-robin assignment. */ -+static struct bman_portal *shared_portals[NR_CPUS]; -+static int num_shared_portals; -+static int shared_portals_idx; -+static LIST_HEAD(unused_pcfgs); -+static DEFINE_SPINLOCK(unused_pcfgs_lock); -+static void *affine_bportals[NR_CPUS]; -+ -+static int __init fsl_bpool_init(struct device_node *node) -+{ -+ int ret; -+ u32 *thresh, *bpid = (u32 *)of_get_property(node, "fsl,bpid", &ret); -+ if (!bpid || (ret != 4)) { -+ pr_err("Can't get %s property 'fsl,bpid'\n", node->full_name); -+ return -ENODEV; -+ } -+ thresh = (u32 *)of_get_property(node, "fsl,bpool-thresholds", &ret); -+ if (thresh) { -+ if (ret != 16) { -+ pr_err("Invalid %s property '%s'\n", -+ node->full_name, "fsl,bpool-thresholds"); -+ return -ENODEV; -+ } -+ } -+ if (thresh) { -+#ifdef CONFIG_FSL_BMAN_CONFIG -+ ret = bm_pool_set(be32_to_cpu(*bpid), thresh); -+ if (ret) -+ pr_err("No CCSR node for %s property '%s'\n", -+ node->full_name, "fsl,bpool-thresholds"); -+ return ret; -+#else -+ pr_err("Ignoring %s property '%s', no CCSR support\n", -+ node->full_name, "fsl,bpool-thresholds"); -+#endif -+ } -+ return 0; -+} -+ -+static int __init fsl_bpid_range_init(struct device_node *node) -+{ -+ int ret; -+ u32 *range = (u32 *)of_get_property(node, "fsl,bpid-range", &ret); -+ if (!range) { -+ pr_err("No 'fsl,bpid-range' property in node %s\n", -+ node->full_name); -+ return -EINVAL; -+ } -+ if (ret != 8) { -+ pr_err("'fsl,bpid-range' is not a 2-cell range in node %s\n", -+ node->full_name); -+ return -EINVAL; -+ } -+ bman_seed_bpid_range(be32_to_cpu(range[0]), be32_to_cpu(range[1])); -+ pr_info("Bman: BPID allocator includes range %d:%d\n", -+ be32_to_cpu(range[0]), be32_to_cpu(range[1])); -+ return 0; -+} -+ -+static struct bm_portal_config * __init parse_pcfg(struct device_node *node) -+{ -+ struct bm_portal_config *pcfg; -+ const u32 *index; -+ int irq, ret; -+ resource_size_t len; -+ -+ pcfg = kmalloc(sizeof(*pcfg), GFP_KERNEL); -+ if (!pcfg) { -+ pr_err("can't allocate portal config"); -+ return NULL; -+ } -+ -+ if (of_device_is_compatible(node, "fsl,bman-portal-1.0") || -+ of_device_is_compatible(node, "fsl,bman-portal-1.0.0")) { -+ bman_ip_rev = BMAN_REV10; -+ bman_pool_max = 64; -+ bman_portal_max = 10; -+ } else if (of_device_is_compatible(node, "fsl,bman-portal-2.0") || -+ of_device_is_compatible(node, "fsl,bman-portal-2.0.8")) { -+ bman_ip_rev = BMAN_REV20; -+ bman_pool_max = 8; -+ bman_portal_max = 3; -+ } else if (of_device_is_compatible(node, "fsl,bman-portal-2.1.0")) { -+ bman_ip_rev = BMAN_REV21; -+ bman_pool_max = 64; -+ bman_portal_max = 50; -+ } else if (of_device_is_compatible(node, "fsl,bman-portal-2.1.1")) { -+ bman_ip_rev = BMAN_REV21; -+ bman_pool_max = 64; -+ bman_portal_max = 25; -+ } else if (of_device_is_compatible(node, "fsl,bman-portal-2.1.2")) { -+ bman_ip_rev = BMAN_REV21; -+ bman_pool_max = 64; -+ bman_portal_max = 18; -+ } else if (of_device_is_compatible(node, "fsl,bman-portal-2.1.3")) { -+ bman_ip_rev = BMAN_REV21; -+ bman_pool_max = 64; -+ bman_portal_max = 10; -+ } else { -+ pr_warn("unknown BMan version in portal node," -+ "default to rev1.0\n"); -+ bman_ip_rev = BMAN_REV10; -+ bman_pool_max = 64; -+ bman_portal_max = 10; -+ } -+ -+ ret = of_address_to_resource(node, DPA_PORTAL_CE, -+ &pcfg->addr_phys[DPA_PORTAL_CE]); -+ if (ret) { -+ pr_err("Can't get %s property 'reg::CE'\n", node->full_name); -+ goto err; -+ } -+ ret = of_address_to_resource(node, DPA_PORTAL_CI, -+ &pcfg->addr_phys[DPA_PORTAL_CI]); -+ if (ret) { -+ pr_err("Can't get %s property 'reg::CI'\n", node->full_name); -+ goto err; -+ } -+ -+ index = of_get_property(node, "cell-index", &ret); -+ if (!index || (ret != 4)) { -+ pr_err("Can't get %s property '%s'\n", node->full_name, -+ "cell-index"); -+ goto err; -+ } -+ if (be32_to_cpu(*index) >= bman_portal_max) { -+ pr_err("BMan portal cell index %d out of range, max %d\n", -+ be32_to_cpu(*index), bman_portal_max); -+ goto err; -+ } -+ -+ pcfg->public_cfg.cpu = -1; -+ -+ irq = irq_of_parse_and_map(node, 0); -+ if (irq == 0) { -+ pr_err("Can't get %s property 'interrupts'\n", node->full_name); -+ goto err; -+ } -+ pcfg->public_cfg.irq = irq; -+ pcfg->public_cfg.index = be32_to_cpu(*index); -+ bman_depletion_fill(&pcfg->public_cfg.mask); -+ -+ len = resource_size(&pcfg->addr_phys[DPA_PORTAL_CE]); -+ if (len != (unsigned long)len) -+ goto err; -+ -+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) -+ pcfg->addr_virt[DPA_PORTAL_CE] = ioremap_cache_ns( -+ pcfg->addr_phys[DPA_PORTAL_CE].start, -+ resource_size(&pcfg->addr_phys[DPA_PORTAL_CE])); -+ pcfg->addr_virt[DPA_PORTAL_CI] = ioremap( -+ pcfg->addr_phys[DPA_PORTAL_CI].start, -+ resource_size(&pcfg->addr_phys[DPA_PORTAL_CI])); -+ -+#else -+ pcfg->addr_virt[DPA_PORTAL_CE] = ioremap_prot( -+ pcfg->addr_phys[DPA_PORTAL_CE].start, -+ (unsigned long)len, -+ 0); -+ pcfg->addr_virt[DPA_PORTAL_CI] = ioremap_prot( -+ pcfg->addr_phys[DPA_PORTAL_CI].start, -+ resource_size(&pcfg->addr_phys[DPA_PORTAL_CI]), -+ _PAGE_GUARDED | _PAGE_NO_CACHE); -+#endif -+ /* disable bp depletion */ -+ __raw_writel(0x0, pcfg->addr_virt[DPA_PORTAL_CI] + BM_REG_SCN(0)); -+ __raw_writel(0x0, pcfg->addr_virt[DPA_PORTAL_CI] + BM_REG_SCN(1)); -+ return pcfg; -+err: -+ kfree(pcfg); -+ return NULL; -+} -+ -+static struct bm_portal_config *get_pcfg(struct list_head *list) -+{ -+ struct bm_portal_config *pcfg; -+ if (list_empty(list)) -+ return NULL; -+ pcfg = list_entry(list->prev, struct bm_portal_config, list); -+ list_del(&pcfg->list); -+ return pcfg; -+} -+ -+static struct bm_portal_config *get_pcfg_idx(struct list_head *list, -+ uint32_t idx) -+{ -+ struct bm_portal_config *pcfg; -+ if (list_empty(list)) -+ return NULL; -+ list_for_each_entry(pcfg, list, list) { -+ if (pcfg->public_cfg.index == idx) { -+ list_del(&pcfg->list); -+ return pcfg; -+ } -+ } -+ return NULL; -+} -+ -+struct bm_portal_config *bm_get_unused_portal(void) -+{ -+ return bm_get_unused_portal_idx(QBMAN_ANY_PORTAL_IDX); -+} -+ -+struct bm_portal_config *bm_get_unused_portal_idx(uint32_t idx) -+{ -+ struct bm_portal_config *ret; -+ spin_lock(&unused_pcfgs_lock); -+ if (idx == QBMAN_ANY_PORTAL_IDX) -+ ret = get_pcfg(&unused_pcfgs); -+ else -+ ret = get_pcfg_idx(&unused_pcfgs, idx); -+ spin_unlock(&unused_pcfgs_lock); -+ return ret; -+} -+ -+void bm_put_unused_portal(struct bm_portal_config *pcfg) -+{ -+ spin_lock(&unused_pcfgs_lock); -+ list_add(&pcfg->list, &unused_pcfgs); -+ spin_unlock(&unused_pcfgs_lock); -+} -+ -+static struct bman_portal *init_pcfg(struct bm_portal_config *pcfg) -+{ -+ struct bman_portal *p; -+ p = bman_create_affine_portal(pcfg); -+ if (p) { -+#ifdef CONFIG_FSL_DPA_PIRQ_SLOW -+ bman_p_irqsource_add(p, BM_PIRQ_RCRI | BM_PIRQ_BSCN); -+#endif -+ pr_info("Bman portal %sinitialised, cpu %d\n", -+ pcfg->public_cfg.is_shared ? "(shared) " : "", -+ pcfg->public_cfg.cpu); -+ affine_bportals[pcfg->public_cfg.cpu] = p; -+ } else -+ pr_crit("Bman portal failure on cpu %d\n", -+ pcfg->public_cfg.cpu); -+ return p; -+} -+ -+static void init_slave(int cpu) -+{ -+ struct bman_portal *p; -+ p = bman_create_affine_slave(shared_portals[shared_portals_idx++], cpu); -+ if (!p) -+ pr_err("Bman slave portal failure on cpu %d\n", cpu); -+ else -+ pr_info("Bman portal %sinitialised, cpu %d\n", "(slave) ", cpu); -+ if (shared_portals_idx >= num_shared_portals) -+ shared_portals_idx = 0; -+ affine_bportals[cpu] = p; -+} -+ -+/* Bootarg "bportals=[...]" has the same syntax as "qportals=", and so the -+ * parsing is in dpa_sys.h. The syntax is a comma-separated list of indexes -+ * and/or ranges of indexes, with each being optionally prefixed by "s" to -+ * explicitly mark it or them for sharing. -+ * Eg; -+ * bportals=s0,1-3,s4 -+ * means that cpus 1,2,3 get "unshared" portals, cpus 0 and 4 get "shared" -+ * portals, and any remaining cpus share the portals that are assigned to cpus 0 -+ * or 4, selected in a round-robin fashion. (In this example, cpu 5 would share -+ * cpu 0's portal, cpu 6 would share cpu4's portal, and cpu 7 would share cpu -+ * 0's portal.) */ -+static struct cpumask want_unshared __initdata; /* cpus requested without "s" */ -+static struct cpumask want_shared __initdata; /* cpus requested with "s" */ -+ -+static int __init parse_bportals(char *str) -+{ -+ return parse_portals_bootarg(str, &want_shared, &want_unshared, -+ "bportals"); -+} -+__setup("bportals=", parse_bportals); -+ -+static void bman_offline_cpu(unsigned int cpu) -+{ -+ struct bman_portal *p; -+ const struct bm_portal_config *pcfg; -+ p = (struct bman_portal *)affine_bportals[cpu]; -+ if (p) { -+ pcfg = bman_get_bm_portal_config(p); -+ if (pcfg) -+ irq_set_affinity(pcfg->public_cfg.irq, cpumask_of(0)); -+ } -+} -+ -+#ifdef CONFIG_HOTPLUG_CPU -+static void bman_online_cpu(unsigned int cpu) -+{ -+ struct bman_portal *p; -+ const struct bm_portal_config *pcfg; -+ p = (struct bman_portal *)affine_bportals[cpu]; -+ if (p) { -+ pcfg = bman_get_bm_portal_config(p); -+ if (pcfg) -+ irq_set_affinity(pcfg->public_cfg.irq, cpumask_of(cpu)); -+ } -+} -+ -+static int bman_hotplug_cpu_callback(struct notifier_block *nfb, -+ unsigned long action, void *hcpu) -+{ -+ unsigned int cpu = (unsigned long)hcpu; -+ -+ switch (action) { -+ case CPU_ONLINE: -+ case CPU_ONLINE_FROZEN: -+ bman_online_cpu(cpu); -+ break; -+ case CPU_DOWN_PREPARE: -+ case CPU_DOWN_PREPARE_FROZEN: -+ bman_offline_cpu(cpu); -+ default: -+ break; -+ } -+ return NOTIFY_OK; -+} -+ -+static struct notifier_block bman_hotplug_cpu_notifier = { -+ .notifier_call = bman_hotplug_cpu_callback, -+}; -+#endif /* CONFIG_HOTPLUG_CPU */ -+ -+/* Initialise the Bman driver. The meat of this function deals with portals. The -+ * following describes the flow of portal-handling, the code "steps" refer to -+ * this description; -+ * 1. Portal configs are parsed from the device-tree into 'unused_pcfgs', with -+ * ::cpu==-1. Regions and interrupts are mapped (but interrupts are not -+ * bound). -+ * 2. The "want_shared" and "want_unshared" lists (as filled by the -+ * "bportals=[...]" bootarg) are processed, allocating portals and assigning -+ * them to cpus, placing them in the relevant list and setting ::cpu as -+ * appropriate. If no "bportals" bootarg was present, the defaut is to try to -+ * assign portals to all online cpus at the time of driver initialisation. -+ * Any failure to allocate portals (when parsing the "want" lists or when -+ * using default behaviour) will be silently tolerated (the "fixup" logic in -+ * step 3 will determine what happens in this case). -+ * 3. Do fixups relative to cpu_online_mask(). If no portals are marked for -+ * sharing and sharing is required (because not all cpus have been assigned -+ * portals), then one portal will marked for sharing. Conversely if no -+ * sharing is required, any portals marked for sharing will not be shared. It -+ * may be that sharing occurs when it wasn't expected, if portal allocation -+ * failed to honour all the requested assignments (including the default -+ * assignments if no bootarg is present). -+ * 4. Unshared portals are initialised on their respective cpus. -+ * 5. Shared portals are initialised on their respective cpus. -+ * 6. Each remaining cpu is initialised to slave to one of the shared portals, -+ * which are selected in a round-robin fashion. -+ * Any portal configs left unused are available for USDPAA allocation. -+ */ -+__init int bman_init(void) -+{ -+ struct cpumask slave_cpus; -+ struct cpumask unshared_cpus = *cpu_none_mask; -+ struct cpumask shared_cpus = *cpu_none_mask; -+ LIST_HEAD(unshared_pcfgs); -+ LIST_HEAD(shared_pcfgs); -+ struct device_node *dn; -+ struct bm_portal_config *pcfg; -+ struct bman_portal *p; -+ int cpu, ret; -+ struct cpumask offline_cpus; -+ -+ /* Initialise the Bman (CCSR) device */ -+ for_each_compatible_node(dn, NULL, "fsl,bman") { -+ if (!bman_init_ccsr(dn)) -+ pr_info("Bman err interrupt handler present\n"); -+ else -+ pr_err("Bman CCSR setup failed\n"); -+ } -+ /* Initialise any declared buffer pools */ -+ for_each_compatible_node(dn, NULL, "fsl,bpool") { -+ ret = fsl_bpool_init(dn); -+ if (ret) -+ return ret; -+ } -+ /* Step 1. See comments at the beginning of the file. */ -+ for_each_compatible_node(dn, NULL, "fsl,bman-portal") { -+ if (!of_device_is_available(dn)) -+ continue; -+ pcfg = parse_pcfg(dn); -+ if (pcfg) -+ list_add_tail(&pcfg->list, &unused_pcfgs); -+ } -+ /* Step 2. */ -+ for_each_possible_cpu(cpu) { -+ if (cpumask_test_cpu(cpu, &want_shared)) { -+ pcfg = get_pcfg(&unused_pcfgs); -+ if (!pcfg) -+ break; -+ pcfg->public_cfg.cpu = cpu; -+ list_add_tail(&pcfg->list, &shared_pcfgs); -+ cpumask_set_cpu(cpu, &shared_cpus); -+ } -+ if (cpumask_test_cpu(cpu, &want_unshared)) { -+ if (cpumask_test_cpu(cpu, &shared_cpus)) -+ continue; -+ pcfg = get_pcfg(&unused_pcfgs); -+ if (!pcfg) -+ break; -+ pcfg->public_cfg.cpu = cpu; -+ list_add_tail(&pcfg->list, &unshared_pcfgs); -+ cpumask_set_cpu(cpu, &unshared_cpus); -+ } -+ } -+ if (list_empty(&shared_pcfgs) && list_empty(&unshared_pcfgs)) { -+ /* Default, give an unshared portal to each online cpu */ -+ for_each_online_cpu(cpu) { -+ pcfg = get_pcfg(&unused_pcfgs); -+ if (!pcfg) -+ break; -+ pcfg->public_cfg.cpu = cpu; -+ list_add_tail(&pcfg->list, &unshared_pcfgs); -+ cpumask_set_cpu(cpu, &unshared_cpus); -+ } -+ } -+ /* Step 3. */ -+ cpumask_andnot(&slave_cpus, cpu_possible_mask, &shared_cpus); -+ cpumask_andnot(&slave_cpus, &slave_cpus, &unshared_cpus); -+ if (cpumask_empty(&slave_cpus)) { -+ /* No sharing required */ -+ if (!list_empty(&shared_pcfgs)) { -+ /* Migrate "shared" to "unshared" */ -+ cpumask_or(&unshared_cpus, &unshared_cpus, -+ &shared_cpus); -+ cpumask_clear(&shared_cpus); -+ list_splice_tail(&shared_pcfgs, &unshared_pcfgs); -+ INIT_LIST_HEAD(&shared_pcfgs); -+ } -+ } else { -+ /* Sharing required */ -+ if (list_empty(&shared_pcfgs)) { -+ /* Migrate one "unshared" to "shared" */ -+ pcfg = get_pcfg(&unshared_pcfgs); -+ if (!pcfg) { -+ pr_crit("No BMan portals available!\n"); -+ return 0; -+ } -+ cpumask_clear_cpu(pcfg->public_cfg.cpu, &unshared_cpus); -+ cpumask_set_cpu(pcfg->public_cfg.cpu, &shared_cpus); -+ list_add_tail(&pcfg->list, &shared_pcfgs); -+ } -+ } -+ /* Step 4. */ -+ list_for_each_entry(pcfg, &unshared_pcfgs, list) { -+ pcfg->public_cfg.is_shared = 0; -+ p = init_pcfg(pcfg); -+ if (!p) { -+ pr_crit("Unable to initialize bman portal\n"); -+ return 0; -+ } -+ } -+ /* Step 5. */ -+ list_for_each_entry(pcfg, &shared_pcfgs, list) { -+ pcfg->public_cfg.is_shared = 1; -+ p = init_pcfg(pcfg); -+ if (p) -+ shared_portals[num_shared_portals++] = p; -+ } -+ /* Step 6. */ -+ if (!cpumask_empty(&slave_cpus)) -+ for_each_cpu(cpu, &slave_cpus) -+ init_slave(cpu); -+ pr_info("Bman portals initialised\n"); -+ cpumask_andnot(&offline_cpus, cpu_possible_mask, cpu_online_mask); -+ for_each_cpu(cpu, &offline_cpus) -+ bman_offline_cpu(cpu); -+#ifdef CONFIG_HOTPLUG_CPU -+ register_hotcpu_notifier(&bman_hotplug_cpu_notifier); -+#endif -+ return 0; -+} -+ -+__init int bman_resource_init(void) -+{ -+ struct device_node *dn; -+ int ret; -+ -+ /* Initialise BPID allocation ranges */ -+ for_each_compatible_node(dn, NULL, "fsl,bpid-range") { -+ ret = fsl_bpid_range_init(dn); -+ if (ret) -+ return ret; -+ } -+ return 0; -+} -+ -+#ifdef CONFIG_SUSPEND -+void suspend_unused_bportal(void) -+{ -+ struct bm_portal_config *pcfg; -+ -+ if (list_empty(&unused_pcfgs)) -+ return; -+ -+ list_for_each_entry(pcfg, &unused_pcfgs, list) { -+#ifdef CONFIG_PM_DEBUG -+ pr_info("Need to save bportal %d\n", pcfg->public_cfg.index); -+#endif -+ /* save isdr, disable all via isdr, clear isr */ -+ pcfg->saved_isdr = -+ __raw_readl(pcfg->addr_virt[DPA_PORTAL_CI] + 0xe08); -+ __raw_writel(0xffffffff, pcfg->addr_virt[DPA_PORTAL_CI] + -+ 0xe08); -+ __raw_writel(0xffffffff, pcfg->addr_virt[DPA_PORTAL_CI] + -+ 0xe00); -+ } -+ return; -+} -+ -+void resume_unused_bportal(void) -+{ -+ struct bm_portal_config *pcfg; -+ -+ if (list_empty(&unused_pcfgs)) -+ return; -+ -+ list_for_each_entry(pcfg, &unused_pcfgs, list) { -+#ifdef CONFIG_PM_DEBUG -+ pr_info("Need to resume bportal %d\n", pcfg->public_cfg.index); -+#endif -+ /* restore isdr */ -+ __raw_writel(pcfg->saved_isdr, -+ pcfg->addr_virt[DPA_PORTAL_CI] + 0xe08); -+ } -+ return; -+} -+#endif ---- /dev/null -+++ b/drivers/staging/fsl_qbman/bman_high.c -@@ -0,0 +1,1141 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "bman_low.h" -+ -+/* Compilation constants */ -+#define RCR_THRESH 2 /* reread h/w CI when running out of space */ -+#define IRQNAME "BMan portal %d" -+#define MAX_IRQNAME 16 /* big enough for "BMan portal %d" */ -+ -+struct bman_portal { -+ struct bm_portal p; -+ /* 2-element array. pools[0] is mask, pools[1] is snapshot. */ -+ struct bman_depletion *pools; -+ int thresh_set; -+ unsigned long irq_sources; -+ u32 slowpoll; /* only used when interrupts are off */ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ struct bman_pool *rcri_owned; /* only 1 release WAIT_SYNC at a time */ -+#endif -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ raw_spinlock_t sharing_lock; /* only used if is_shared */ -+ int is_shared; -+ struct bman_portal *sharing_redirect; -+#endif -+ /* When the cpu-affine portal is activated, this is non-NULL */ -+ const struct bm_portal_config *config; -+ /* This is needed for power management */ -+ struct platform_device *pdev; -+ /* 64-entry hash-table of pool objects that are tracking depletion -+ * entry/exit (ie. BMAN_POOL_FLAG_DEPLETION). This isn't fast-path, so -+ * we're not fussy about cache-misses and so forth - whereas the above -+ * members should all fit in one cacheline. -+ * BTW, with 64 entries in the hash table and 64 buffer pools to track, -+ * you'll never guess the hash-function ... */ -+ struct bman_pool *cb[64]; -+ char irqname[MAX_IRQNAME]; -+ /* Track if the portal was alloced by the driver */ -+ u8 alloced; -+ /* power management data */ -+ u32 save_isdr; -+}; -+ -+/* For an explanation of the locking, redirection, or affine-portal logic, -+ * please consult the Qman driver for details. This is the same, only simpler -+ * (no fiddly Qman-specific bits.) */ -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+#define PORTAL_IRQ_LOCK(p, irqflags) \ -+ do { \ -+ if ((p)->is_shared) \ -+ raw_spin_lock_irqsave(&(p)->sharing_lock, irqflags); \ -+ else \ -+ local_irq_save(irqflags); \ -+ } while (0) -+#define PORTAL_IRQ_UNLOCK(p, irqflags) \ -+ do { \ -+ if ((p)->is_shared) \ -+ raw_spin_unlock_irqrestore(&(p)->sharing_lock, \ -+ irqflags); \ -+ else \ -+ local_irq_restore(irqflags); \ -+ } while (0) -+#else -+#define PORTAL_IRQ_LOCK(p, irqflags) local_irq_save(irqflags) -+#define PORTAL_IRQ_UNLOCK(p, irqflags) local_irq_restore(irqflags) -+#endif -+ -+static cpumask_t affine_mask; -+static DEFINE_SPINLOCK(affine_mask_lock); -+static DEFINE_PER_CPU(struct bman_portal, bman_affine_portal); -+static inline struct bman_portal *get_raw_affine_portal(void) -+{ -+ return &get_cpu_var(bman_affine_portal); -+} -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+static inline struct bman_portal *get_affine_portal(void) -+{ -+ struct bman_portal *p = get_raw_affine_portal(); -+ if (p->sharing_redirect) -+ return p->sharing_redirect; -+ return p; -+} -+#else -+#define get_affine_portal() get_raw_affine_portal() -+#endif -+static inline void put_affine_portal(void) -+{ -+ put_cpu_var(bman_affine_portal); -+} -+static inline struct bman_portal *get_poll_portal(void) -+{ -+ return &get_cpu_var(bman_affine_portal); -+} -+#define put_poll_portal() -+ -+/* GOTCHA: this object type refers to a pool, it isn't *the* pool. There may be -+ * more than one such object per Bman buffer pool, eg. if different users of the -+ * pool are operating via different portals. */ -+struct bman_pool { -+ struct bman_pool_params params; -+ /* Used for hash-table admin when using depletion notifications. */ -+ struct bman_portal *portal; -+ struct bman_pool *next; -+ /* stockpile state - NULL unless BMAN_POOL_FLAG_STOCKPILE is set */ -+ struct bm_buffer *sp; -+ unsigned int sp_fill; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ atomic_t in_use; -+#endif -+}; -+ -+/* (De)Registration of depletion notification callbacks */ -+static void depletion_link(struct bman_portal *portal, struct bman_pool *pool) -+{ -+ __maybe_unused unsigned long irqflags; -+ pool->portal = portal; -+ PORTAL_IRQ_LOCK(portal, irqflags); -+ pool->next = portal->cb[pool->params.bpid]; -+ portal->cb[pool->params.bpid] = pool; -+ if (!pool->next) -+ /* First object for that bpid on this portal, enable the BSCN -+ * mask bit. */ -+ bm_isr_bscn_mask(&portal->p, pool->params.bpid, 1); -+ PORTAL_IRQ_UNLOCK(portal, irqflags); -+} -+static void depletion_unlink(struct bman_pool *pool) -+{ -+ struct bman_pool *it, *last = NULL; -+ struct bman_pool **base = &pool->portal->cb[pool->params.bpid]; -+ __maybe_unused unsigned long irqflags; -+ PORTAL_IRQ_LOCK(pool->portal, irqflags); -+ it = *base; /* <-- gotcha, don't do this prior to the irq_save */ -+ while (it != pool) { -+ last = it; -+ it = it->next; -+ } -+ if (!last) -+ *base = pool->next; -+ else -+ last->next = pool->next; -+ if (!last && !pool->next) { -+ /* Last object for that bpid on this portal, disable the BSCN -+ * mask bit. */ -+ bm_isr_bscn_mask(&pool->portal->p, pool->params.bpid, 0); -+ /* And "forget" that we last saw this pool as depleted */ -+ bman_depletion_unset(&pool->portal->pools[1], -+ pool->params.bpid); -+ } -+ PORTAL_IRQ_UNLOCK(pool->portal, irqflags); -+} -+ -+/* In the case that the application's core loop calls qman_poll() and -+ * bman_poll(), we ought to balance how often we incur the overheads of the -+ * slow-path poll. We'll use two decrementer sources. The idle decrementer -+ * constant is used when the last slow-poll detected no work to do, and the busy -+ * decrementer constant when the last slow-poll had work to do. */ -+#define SLOW_POLL_IDLE 1000 -+#define SLOW_POLL_BUSY 10 -+static u32 __poll_portal_slow(struct bman_portal *p, u32 is); -+ -+/* Portal interrupt handler */ -+static irqreturn_t portal_isr(__always_unused int irq, void *ptr) -+{ -+ struct bman_portal *p = ptr; -+ u32 clear = p->irq_sources; -+ u32 is = bm_isr_status_read(&p->p) & p->irq_sources; -+ clear |= __poll_portal_slow(p, is); -+ bm_isr_status_clear(&p->p, clear); -+ return IRQ_HANDLED; -+} -+ -+#ifdef CONFIG_SUSPEND -+static int _bman_portal_suspend_noirq(struct device *dev) -+{ -+ struct bman_portal *p = (struct bman_portal *)dev->platform_data; -+#ifdef CONFIG_PM_DEBUG -+ struct platform_device *pdev = to_platform_device(dev); -+#endif -+ p->save_isdr = bm_isr_disable_read(&p->p); -+ bm_isr_disable_write(&p->p, 0xffffffff); -+ bm_isr_status_clear(&p->p, 0xffffffff); -+#ifdef CONFIG_PM_DEBUG -+ pr_info("Suspend for %s\n", pdev->name); -+#endif -+ return 0; -+} -+ -+static int _bman_portal_resume_noirq(struct device *dev) -+{ -+ struct bman_portal *p = (struct bman_portal *)dev->platform_data; -+ -+ /* restore isdr */ -+ bm_isr_disable_write(&p->p, p->save_isdr); -+ return 0; -+} -+#else -+#define _bman_portal_suspend_noirq NULL -+#define _bman_portal_resume_noirq NULL -+#endif -+ -+struct dev_pm_domain bman_portal_device_pm_domain = { -+ .ops = { -+ USE_PLATFORM_PM_SLEEP_OPS -+ .suspend_noirq = _bman_portal_suspend_noirq, -+ .resume_noirq = _bman_portal_resume_noirq, -+ } -+}; -+ -+struct bman_portal *bman_create_portal( -+ struct bman_portal *portal, -+ const struct bm_portal_config *config) -+{ -+ struct bm_portal *__p; -+ const struct bman_depletion *pools = &config->public_cfg.mask; -+ int ret; -+ u8 bpid = 0; -+ char buf[16]; -+ -+ if (!portal) { -+ portal = kmalloc(sizeof(*portal), GFP_KERNEL); -+ if (!portal) -+ return portal; -+ portal->alloced = 1; -+ } else -+ portal->alloced = 0; -+ -+ __p = &portal->p; -+ -+ /* prep the low-level portal struct with the mapped addresses from the -+ * config, everything that follows depends on it and "config" is more -+ * for (de)reference... */ -+ __p->addr.addr_ce = config->addr_virt[DPA_PORTAL_CE]; -+ __p->addr.addr_ci = config->addr_virt[DPA_PORTAL_CI]; -+ if (bm_rcr_init(__p, bm_rcr_pvb, bm_rcr_cce)) { -+ pr_err("Bman RCR initialisation failed\n"); -+ goto fail_rcr; -+ } -+ if (bm_mc_init(__p)) { -+ pr_err("Bman MC initialisation failed\n"); -+ goto fail_mc; -+ } -+ if (bm_isr_init(__p)) { -+ pr_err("Bman ISR initialisation failed\n"); -+ goto fail_isr; -+ } -+ portal->pools = kmalloc(2 * sizeof(*pools), GFP_KERNEL); -+ if (!portal->pools) -+ goto fail_pools; -+ portal->pools[0] = *pools; -+ bman_depletion_init(portal->pools + 1); -+ while (bpid < bman_pool_max) { -+ /* Default to all BPIDs disabled, we enable as required at -+ * run-time. */ -+ bm_isr_bscn_mask(__p, bpid, 0); -+ bpid++; -+ } -+ portal->slowpoll = 0; -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ portal->rcri_owned = NULL; -+#endif -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ raw_spin_lock_init(&portal->sharing_lock); -+ portal->is_shared = config->public_cfg.is_shared; -+ portal->sharing_redirect = NULL; -+#endif -+ sprintf(buf, "bportal-%u", config->public_cfg.index); -+ portal->pdev = platform_device_alloc(buf, -1); -+ if (!portal->pdev) -+ goto fail_devalloc; -+ portal->pdev->dev.pm_domain = &bman_portal_device_pm_domain; -+ portal->pdev->dev.platform_data = portal; -+ ret = platform_device_add(portal->pdev); -+ if (ret) -+ goto fail_devadd; -+ memset(&portal->cb, 0, sizeof(portal->cb)); -+ /* Write-to-clear any stale interrupt status bits */ -+ bm_isr_disable_write(__p, 0xffffffff); -+ portal->irq_sources = 0; -+ bm_isr_enable_write(__p, portal->irq_sources); -+ bm_isr_status_clear(__p, 0xffffffff); -+ snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, config->public_cfg.cpu); -+ if (request_irq(config->public_cfg.irq, portal_isr, 0, portal->irqname, -+ portal)) { -+ pr_err("request_irq() failed\n"); -+ goto fail_irq; -+ } -+ if ((config->public_cfg.cpu != -1) && -+ irq_can_set_affinity(config->public_cfg.irq) && -+ irq_set_affinity(config->public_cfg.irq, -+ cpumask_of(config->public_cfg.cpu))) { -+ pr_err("irq_set_affinity() failed %s\n", portal->irqname); -+ goto fail_affinity; -+ } -+ -+ /* Need RCR to be empty before continuing */ -+ ret = bm_rcr_get_fill(__p); -+ if (ret) { -+ pr_err("Bman RCR unclean\n"); -+ goto fail_rcr_empty; -+ } -+ /* Success */ -+ portal->config = config; -+ -+ bm_isr_disable_write(__p, 0); -+ bm_isr_uninhibit(__p); -+ return portal; -+fail_rcr_empty: -+fail_affinity: -+ free_irq(config->public_cfg.irq, portal); -+fail_irq: -+ platform_device_del(portal->pdev); -+fail_devadd: -+ platform_device_put(portal->pdev); -+fail_devalloc: -+ kfree(portal->pools); -+fail_pools: -+ bm_isr_finish(__p); -+fail_isr: -+ bm_mc_finish(__p); -+fail_mc: -+ bm_rcr_finish(__p); -+fail_rcr: -+ if (portal->alloced) -+ kfree(portal); -+ return NULL; -+} -+ -+struct bman_portal *bman_create_affine_portal( -+ const struct bm_portal_config *config) -+{ -+ struct bman_portal *portal; -+ -+ portal = &per_cpu(bman_affine_portal, config->public_cfg.cpu); -+ portal = bman_create_portal(portal, config); -+ if (portal) { -+ spin_lock(&affine_mask_lock); -+ cpumask_set_cpu(config->public_cfg.cpu, &affine_mask); -+ spin_unlock(&affine_mask_lock); -+ } -+ return portal; -+} -+ -+ -+struct bman_portal *bman_create_affine_slave(struct bman_portal *redirect, -+ int cpu) -+{ -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ struct bman_portal *p; -+ p = &per_cpu(bman_affine_portal, cpu); -+ BUG_ON(p->config); -+ BUG_ON(p->is_shared); -+ BUG_ON(!redirect->config->public_cfg.is_shared); -+ p->irq_sources = 0; -+ p->sharing_redirect = redirect; -+ return p; -+#else -+ BUG(); -+ return NULL; -+#endif -+} -+ -+void bman_destroy_portal(struct bman_portal *bm) -+{ -+ const struct bm_portal_config *pcfg; -+ pcfg = bm->config; -+ bm_rcr_cce_update(&bm->p); -+ bm_rcr_cce_update(&bm->p); -+ -+ free_irq(pcfg->public_cfg.irq, bm); -+ -+ kfree(bm->pools); -+ bm_isr_finish(&bm->p); -+ bm_mc_finish(&bm->p); -+ bm_rcr_finish(&bm->p); -+ bm->config = NULL; -+ if (bm->alloced) -+ kfree(bm); -+} -+ -+const struct bm_portal_config *bman_destroy_affine_portal(void) -+{ -+ struct bman_portal *bm = get_raw_affine_portal(); -+ const struct bm_portal_config *pcfg; -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ if (bm->sharing_redirect) { -+ bm->sharing_redirect = NULL; -+ put_affine_portal(); -+ return NULL; -+ } -+ bm->is_shared = 0; -+#endif -+ pcfg = bm->config; -+ bman_destroy_portal(bm); -+ spin_lock(&affine_mask_lock); -+ cpumask_clear_cpu(pcfg->public_cfg.cpu, &affine_mask); -+ spin_unlock(&affine_mask_lock); -+ put_affine_portal(); -+ return pcfg; -+} -+ -+/* When release logic waits on available RCR space, we need a global waitqueue -+ * in the case of "affine" use (as the waits wake on different cpus which means -+ * different portals - so we can't wait on any per-portal waitqueue). */ -+static DECLARE_WAIT_QUEUE_HEAD(affine_queue); -+ -+static u32 __poll_portal_slow(struct bman_portal *p, u32 is) -+{ -+ struct bman_depletion tmp; -+ u32 ret = is; -+ -+ /* There is a gotcha to be aware of. If we do the query before clearing -+ * the status register, we may miss state changes that occur between the -+ * two. If we write to clear the status register before the query, the -+ * cache-enabled query command may overtake the status register write -+ * unless we use a heavyweight sync (which we don't want). Instead, we -+ * write-to-clear the status register then *read it back* before doing -+ * the query, hence the odd while loop with the 'is' accumulation. */ -+ if (is & BM_PIRQ_BSCN) { -+ struct bm_mc_result *mcr; -+ __maybe_unused unsigned long irqflags; -+ unsigned int i, j; -+ u32 __is; -+ bm_isr_status_clear(&p->p, BM_PIRQ_BSCN); -+ while ((__is = bm_isr_status_read(&p->p)) & BM_PIRQ_BSCN) { -+ is |= __is; -+ bm_isr_status_clear(&p->p, BM_PIRQ_BSCN); -+ } -+ is &= ~BM_PIRQ_BSCN; -+ PORTAL_IRQ_LOCK(p, irqflags); -+ bm_mc_start(&p->p); -+ bm_mc_commit(&p->p, BM_MCC_VERB_CMD_QUERY); -+ while (!(mcr = bm_mc_result(&p->p))) -+ cpu_relax(); -+ tmp = mcr->query.ds.state; -+ tmp.__state[0] = be32_to_cpu(tmp.__state[0]); -+ tmp.__state[1] = be32_to_cpu(tmp.__state[1]); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ for (i = 0; i < 2; i++) { -+ int idx = i * 32; -+ /* tmp is a mask of currently-depleted pools. -+ * pools[0] is mask of those we care about. -+ * pools[1] is our previous view (we only want to -+ * be told about changes). */ -+ tmp.__state[i] &= p->pools[0].__state[i]; -+ if (tmp.__state[i] == p->pools[1].__state[i]) -+ /* fast-path, nothing to see, move along */ -+ continue; -+ for (j = 0; j <= 31; j++, idx++) { -+ struct bman_pool *pool = p->cb[idx]; -+ int b4 = bman_depletion_get(&p->pools[1], idx); -+ int af = bman_depletion_get(&tmp, idx); -+ if (b4 == af) -+ continue; -+ while (pool) { -+ pool->params.cb(p, pool, -+ pool->params.cb_ctx, af); -+ pool = pool->next; -+ } -+ } -+ } -+ p->pools[1] = tmp; -+ } -+ -+ if (is & BM_PIRQ_RCRI) { -+ __maybe_unused unsigned long irqflags; -+ PORTAL_IRQ_LOCK(p, irqflags); -+ bm_rcr_cce_update(&p->p); -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ /* If waiting for sync, we only cancel the interrupt threshold -+ * when the ring utilisation hits zero. */ -+ if (p->rcri_owned) { -+ if (!bm_rcr_get_fill(&p->p)) { -+ p->rcri_owned = NULL; -+ bm_rcr_set_ithresh(&p->p, 0); -+ } -+ } else -+#endif -+ bm_rcr_set_ithresh(&p->p, 0); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ wake_up(&affine_queue); -+ bm_isr_status_clear(&p->p, BM_PIRQ_RCRI); -+ is &= ~BM_PIRQ_RCRI; -+ } -+ -+ /* There should be no status register bits left undefined */ -+ DPA_ASSERT(!is); -+ return ret; -+} -+ -+const struct bman_portal_config *bman_get_portal_config(void) -+{ -+ struct bman_portal *p = get_affine_portal(); -+ const struct bman_portal_config *ret = &p->config->public_cfg; -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(bman_get_portal_config); -+ -+u32 bman_irqsource_get(void) -+{ -+ struct bman_portal *p = get_raw_affine_portal(); -+ u32 ret = p->irq_sources & BM_PIRQ_VISIBLE; -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(bman_irqsource_get); -+ -+int bman_p_irqsource_add(struct bman_portal *p, __maybe_unused u32 bits) -+{ -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ if (p->sharing_redirect) -+ return -EINVAL; -+ else -+#endif -+ { -+ __maybe_unused unsigned long irqflags; -+ PORTAL_IRQ_LOCK(p, irqflags); -+ set_bits(bits & BM_PIRQ_VISIBLE, &p->irq_sources); -+ bm_isr_enable_write(&p->p, p->irq_sources); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ } -+ return 0; -+} -+EXPORT_SYMBOL(bman_p_irqsource_add); -+ -+int bman_irqsource_add(__maybe_unused u32 bits) -+{ -+ struct bman_portal *p = get_raw_affine_portal(); -+ int ret = 0; -+ ret = bman_p_irqsource_add(p, bits); -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(bman_irqsource_add); -+ -+int bman_irqsource_remove(u32 bits) -+{ -+ struct bman_portal *p = get_raw_affine_portal(); -+ __maybe_unused unsigned long irqflags; -+ u32 ier; -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ if (p->sharing_redirect) { -+ put_affine_portal(); -+ return -EINVAL; -+ } -+#endif -+ /* Our interrupt handler only processes+clears status register bits that -+ * are in p->irq_sources. As we're trimming that mask, if one of them -+ * were to assert in the status register just before we remove it from -+ * the enable register, there would be an interrupt-storm when we -+ * release the IRQ lock. So we wait for the enable register update to -+ * take effect in h/w (by reading it back) and then clear all other bits -+ * in the status register. Ie. we clear them from ISR once it's certain -+ * IER won't allow them to reassert. */ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ bits &= BM_PIRQ_VISIBLE; -+ clear_bits(bits, &p->irq_sources); -+ bm_isr_enable_write(&p->p, p->irq_sources); -+ ier = bm_isr_enable_read(&p->p); -+ /* Using "~ier" (rather than "bits" or "~p->irq_sources") creates a -+ * data-dependency, ie. to protect against re-ordering. */ -+ bm_isr_status_clear(&p->p, ~ier); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return 0; -+} -+EXPORT_SYMBOL(bman_irqsource_remove); -+ -+const cpumask_t *bman_affine_cpus(void) -+{ -+ return &affine_mask; -+} -+EXPORT_SYMBOL(bman_affine_cpus); -+ -+u32 bman_poll_slow(void) -+{ -+ struct bman_portal *p = get_poll_portal(); -+ u32 ret; -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ if (unlikely(p->sharing_redirect)) -+ ret = (u32)-1; -+ else -+#endif -+ { -+ u32 is = bm_isr_status_read(&p->p) & ~p->irq_sources; -+ ret = __poll_portal_slow(p, is); -+ bm_isr_status_clear(&p->p, ret); -+ } -+ put_poll_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(bman_poll_slow); -+ -+/* Legacy wrapper */ -+void bman_poll(void) -+{ -+ struct bman_portal *p = get_poll_portal(); -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ if (unlikely(p->sharing_redirect)) -+ goto done; -+#endif -+ if (!(p->slowpoll--)) { -+ u32 is = bm_isr_status_read(&p->p) & ~p->irq_sources; -+ u32 active = __poll_portal_slow(p, is); -+ if (active) -+ p->slowpoll = SLOW_POLL_BUSY; -+ else -+ p->slowpoll = SLOW_POLL_IDLE; -+ } -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+done: -+#endif -+ put_poll_portal(); -+} -+EXPORT_SYMBOL(bman_poll); -+ -+static const u32 zero_thresholds[4] = {0, 0, 0, 0}; -+ -+struct bman_pool *bman_new_pool(const struct bman_pool_params *params) -+{ -+ struct bman_pool *pool = NULL; -+ u32 bpid; -+ -+ if (params->flags & BMAN_POOL_FLAG_DYNAMIC_BPID) { -+ int ret = bman_alloc_bpid(&bpid); -+ if (ret) -+ return NULL; -+ } else { -+ if (params->bpid >= bman_pool_max) -+ return NULL; -+ bpid = params->bpid; -+ } -+#ifdef CONFIG_FSL_BMAN_CONFIG -+ if (params->flags & BMAN_POOL_FLAG_THRESH) { -+ int ret = bm_pool_set(bpid, params->thresholds); -+ if (ret) -+ goto err; -+ } -+#else -+ if (params->flags & BMAN_POOL_FLAG_THRESH) -+ goto err; -+#endif -+ pool = kmalloc(sizeof(*pool), GFP_KERNEL); -+ if (!pool) -+ goto err; -+ pool->sp = NULL; -+ pool->sp_fill = 0; -+ pool->params = *params; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ atomic_set(&pool->in_use, 1); -+#endif -+ if (params->flags & BMAN_POOL_FLAG_DYNAMIC_BPID) -+ pool->params.bpid = bpid; -+ if (params->flags & BMAN_POOL_FLAG_STOCKPILE) { -+ pool->sp = kmalloc(sizeof(struct bm_buffer) * BMAN_STOCKPILE_SZ, -+ GFP_KERNEL); -+ if (!pool->sp) -+ goto err; -+ } -+ if (pool->params.flags & BMAN_POOL_FLAG_DEPLETION) { -+ struct bman_portal *p = get_affine_portal(); -+ if (!p->pools || !bman_depletion_get(&p->pools[0], bpid)) { -+ pr_err("Depletion events disabled for bpid %d\n", bpid); -+ goto err; -+ } -+ depletion_link(p, pool); -+ put_affine_portal(); -+ } -+ return pool; -+err: -+#ifdef CONFIG_FSL_BMAN_CONFIG -+ if (params->flags & BMAN_POOL_FLAG_THRESH) -+ bm_pool_set(bpid, zero_thresholds); -+#endif -+ if (params->flags & BMAN_POOL_FLAG_DYNAMIC_BPID) -+ bman_release_bpid(bpid); -+ if (pool) { -+ kfree(pool->sp); -+ kfree(pool); -+ } -+ return NULL; -+} -+EXPORT_SYMBOL(bman_new_pool); -+ -+void bman_free_pool(struct bman_pool *pool) -+{ -+#ifdef CONFIG_FSL_BMAN_CONFIG -+ if (pool->params.flags & BMAN_POOL_FLAG_THRESH) -+ bm_pool_set(pool->params.bpid, zero_thresholds); -+#endif -+ if (pool->params.flags & BMAN_POOL_FLAG_DEPLETION) -+ depletion_unlink(pool); -+ if (pool->params.flags & BMAN_POOL_FLAG_STOCKPILE) { -+ if (pool->sp_fill) -+ pr_err("Stockpile not flushed, has %u in bpid %u.\n", -+ pool->sp_fill, pool->params.bpid); -+ kfree(pool->sp); -+ pool->sp = NULL; -+ pool->params.flags ^= BMAN_POOL_FLAG_STOCKPILE; -+ } -+ if (pool->params.flags & BMAN_POOL_FLAG_DYNAMIC_BPID) -+ bman_release_bpid(pool->params.bpid); -+ kfree(pool); -+} -+EXPORT_SYMBOL(bman_free_pool); -+ -+const struct bman_pool_params *bman_get_params(const struct bman_pool *pool) -+{ -+ return &pool->params; -+} -+EXPORT_SYMBOL(bman_get_params); -+ -+static noinline void update_rcr_ci(struct bman_portal *p, u8 avail) -+{ -+ if (avail) -+ bm_rcr_cce_prefetch(&p->p); -+ else -+ bm_rcr_cce_update(&p->p); -+} -+ -+int bman_rcr_is_empty(void) -+{ -+ __maybe_unused unsigned long irqflags; -+ struct bman_portal *p = get_affine_portal(); -+ u8 avail; -+ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ update_rcr_ci(p, 0); -+ avail = bm_rcr_get_fill(&p->p); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return avail == 0; -+} -+EXPORT_SYMBOL(bman_rcr_is_empty); -+ -+static inline struct bm_rcr_entry *try_rel_start(struct bman_portal **p, -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+ __maybe_unused struct bman_pool *pool, -+#endif -+ __maybe_unused unsigned long *irqflags, -+ __maybe_unused u32 flags) -+{ -+ struct bm_rcr_entry *r; -+ u8 avail; -+ -+ *p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(*p, (*irqflags)); -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ if (unlikely((flags & BMAN_RELEASE_FLAG_WAIT) && -+ (flags & BMAN_RELEASE_FLAG_WAIT_SYNC))) { -+ if ((*p)->rcri_owned) { -+ PORTAL_IRQ_UNLOCK(*p, (*irqflags)); -+ put_affine_portal(); -+ return NULL; -+ } -+ (*p)->rcri_owned = pool; -+ } -+#endif -+ avail = bm_rcr_get_avail(&(*p)->p); -+ if (avail < 2) -+ update_rcr_ci(*p, avail); -+ r = bm_rcr_start(&(*p)->p); -+ if (unlikely(!r)) { -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ if (unlikely((flags & BMAN_RELEASE_FLAG_WAIT) && -+ (flags & BMAN_RELEASE_FLAG_WAIT_SYNC))) -+ (*p)->rcri_owned = NULL; -+#endif -+ PORTAL_IRQ_UNLOCK(*p, (*irqflags)); -+ put_affine_portal(); -+ } -+ return r; -+} -+ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+static noinline struct bm_rcr_entry *__wait_rel_start(struct bman_portal **p, -+ struct bman_pool *pool, -+ __maybe_unused unsigned long *irqflags, -+ u32 flags) -+{ -+ struct bm_rcr_entry *rcr = try_rel_start(p, pool, irqflags, flags); -+ if (!rcr) -+ bm_rcr_set_ithresh(&(*p)->p, 1); -+ return rcr; -+} -+ -+static noinline struct bm_rcr_entry *wait_rel_start(struct bman_portal **p, -+ struct bman_pool *pool, -+ __maybe_unused unsigned long *irqflags, -+ u32 flags) -+{ -+ struct bm_rcr_entry *rcr; -+#ifndef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ pool = NULL; -+#endif -+ if (flags & BMAN_RELEASE_FLAG_WAIT_INT) -+ /* NB: return NULL if signal occurs before completion. Signal -+ * can occur during return. Caller must check for signal */ -+ wait_event_interruptible(affine_queue, -+ (rcr = __wait_rel_start(p, pool, irqflags, flags))); -+ else -+ wait_event(affine_queue, -+ (rcr = __wait_rel_start(p, pool, irqflags, flags))); -+ return rcr; -+} -+#endif -+ -+static inline int __bman_release(struct bman_pool *pool, -+ const struct bm_buffer *bufs, u8 num, u32 flags) -+{ -+ struct bman_portal *p; -+ struct bm_rcr_entry *r; -+ __maybe_unused unsigned long irqflags; -+ u32 i = num - 1; -+ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+ if (flags & BMAN_RELEASE_FLAG_WAIT) -+ r = wait_rel_start(&p, pool, &irqflags, flags); -+ else -+ r = try_rel_start(&p, pool, &irqflags, flags); -+#else -+ r = try_rel_start(&p, &irqflags, flags); -+#endif -+ if (!r) -+ return -EBUSY; -+ /* We can copy all but the first entry, as this can trigger badness -+ * with the valid-bit. Use the overlay to mask the verb byte. */ -+ r->bufs[0].opaque = -+ ((cpu_to_be64((bufs[0].opaque | -+ ((u64)pool->params.bpid<<48)) -+ & 0x00ffffffffffffff))); -+ if (i) { -+ for (i = 1; i < num; i++) -+ r->bufs[i].opaque = -+ cpu_to_be64(bufs[i].opaque); -+ } -+ -+ bm_rcr_pvb_commit(&p->p, BM_RCR_VERB_CMD_BPID_SINGLE | -+ (num & BM_RCR_VERB_BUFCOUNT_MASK)); -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ /* if we wish to sync we need to set the threshold after h/w sees the -+ * new ring entry. As we're mixing cache-enabled and cache-inhibited -+ * accesses, this requires a heavy-weight sync. */ -+ if (unlikely((flags & BMAN_RELEASE_FLAG_WAIT) && -+ (flags & BMAN_RELEASE_FLAG_WAIT_SYNC))) { -+ hwsync(); -+ bm_rcr_set_ithresh(&p->p, 1); -+ } -+#endif -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ if (unlikely((flags & BMAN_RELEASE_FLAG_WAIT) && -+ (flags & BMAN_RELEASE_FLAG_WAIT_SYNC))) { -+ if (flags & BMAN_RELEASE_FLAG_WAIT_INT) -+ /* NB: return success even if signal occurs before -+ * condition is true. pvb_commit guarantees success */ -+ wait_event_interruptible(affine_queue, -+ (p->rcri_owned != pool)); -+ else -+ wait_event(affine_queue, (p->rcri_owned != pool)); -+ } -+#endif -+ return 0; -+} -+ -+int bman_release(struct bman_pool *pool, const struct bm_buffer *bufs, u8 num, -+ u32 flags) -+{ -+ int ret; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ if (!num || (num > 8)) -+ return -EINVAL; -+ if (pool->params.flags & BMAN_POOL_FLAG_NO_RELEASE) -+ return -EINVAL; -+#endif -+ /* Without stockpile, this API is a pass-through to the h/w operation */ -+ if (!(pool->params.flags & BMAN_POOL_FLAG_STOCKPILE)) -+ return __bman_release(pool, bufs, num, flags); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ if (!atomic_dec_and_test(&pool->in_use)) { -+ pr_crit("Parallel attempts to enter bman_released() detected."); -+ panic("only one instance of bman_released/acquired allowed"); -+ } -+#endif -+ /* Two movements of buffers are possible, and can occur in either order. -+ * A: moving buffers from the caller to the stockpile. -+ * B: moving buffers from the stockpile to hardware. -+ * Order 1: if there is already enough space in the stockpile for A -+ * then we want to do A first, and only do B if we trigger the -+ * stockpile-high threshold. -+ * Order 2: if there is not enough space in the stockpile for A, then -+ * we want to do B first, then do A if B had succeeded. However in this -+ * case B is dependent on how many buffers the user needs to release, -+ * not the stockpile-high threshold. -+ * Due to the different handling of B between the two cases, putting A -+ * and B in a while() loop would require quite obscure logic, so handle -+ * the different sequences explicitly. */ -+ if ((pool->sp_fill + num) <= BMAN_STOCKPILE_SZ) { -+ /* Order 1: do A */ -+ copy_words(pool->sp + pool->sp_fill, bufs, -+ sizeof(struct bm_buffer) * num); -+ pool->sp_fill += num; -+ /* do B relative to STOCKPILE_HIGH */ -+ while (pool->sp_fill >= BMAN_STOCKPILE_HIGH) { -+ ret = __bman_release(pool, -+ pool->sp + (pool->sp_fill - 8), 8, -+ flags); -+ if (ret >= 0) -+ pool->sp_fill -= 8; -+ } -+ } else { -+ /* Order 2: do B relative to 'num' */ -+ do { -+ ret = __bman_release(pool, -+ pool->sp + (pool->sp_fill - 8), 8, -+ flags); -+ if (ret < 0) -+ /* failure */ -+ goto release_done; -+ pool->sp_fill -= 8; -+ } while ((pool->sp_fill + num) > BMAN_STOCKPILE_SZ); -+ /* do A */ -+ copy_words(pool->sp + pool->sp_fill, bufs, -+ sizeof(struct bm_buffer) * num); -+ pool->sp_fill += num; -+ } -+ /* success */ -+ ret = 0; -+release_done: -+#ifdef CONFIG_FSL_DPA_CHECKING -+ atomic_inc(&pool->in_use); -+#endif -+ return ret; -+} -+EXPORT_SYMBOL(bman_release); -+ -+static inline int __bman_acquire(struct bman_pool *pool, struct bm_buffer *bufs, -+ u8 num) -+{ -+ struct bman_portal *p = get_affine_portal(); -+ struct bm_mc_command *mcc; -+ struct bm_mc_result *mcr; -+ __maybe_unused unsigned long irqflags; -+ int ret, i; -+ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ mcc = bm_mc_start(&p->p); -+ mcc->acquire.bpid = pool->params.bpid; -+ bm_mc_commit(&p->p, BM_MCC_VERB_CMD_ACQUIRE | -+ (num & BM_MCC_VERB_ACQUIRE_BUFCOUNT)); -+ while (!(mcr = bm_mc_result(&p->p))) -+ cpu_relax(); -+ ret = mcr->verb & BM_MCR_VERB_ACQUIRE_BUFCOUNT; -+ if (bufs) { -+ for (i = 0; i < num; i++) -+ bufs[i].opaque = -+ be64_to_cpu(mcr->acquire.bufs[i].opaque); -+ } -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ if (ret != num) -+ ret = -ENOMEM; -+ return ret; -+} -+ -+int bman_acquire(struct bman_pool *pool, struct bm_buffer *bufs, u8 num, -+ u32 flags) -+{ -+ int ret; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ if (!num || (num > 8)) -+ return -EINVAL; -+ if (pool->params.flags & BMAN_POOL_FLAG_ONLY_RELEASE) -+ return -EINVAL; -+#endif -+ /* Without stockpile, this API is a pass-through to the h/w operation */ -+ if (!(pool->params.flags & BMAN_POOL_FLAG_STOCKPILE)) -+ return __bman_acquire(pool, bufs, num); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ if (!atomic_dec_and_test(&pool->in_use)) { -+ pr_crit("Parallel attempts to enter bman_acquire() detected."); -+ panic("only one instance of bman_released/acquired allowed"); -+ } -+#endif -+ /* Two movements of buffers are possible, and can occur in either order. -+ * A: moving buffers from stockpile to the caller. -+ * B: moving buffers from hardware to the stockpile. -+ * Order 1: if there are already enough buffers in the stockpile for A -+ * then we want to do A first, and only do B if we trigger the -+ * stockpile-low threshold. -+ * Order 2: if there are not enough buffers in the stockpile for A, -+ * then we want to do B first, then do A if B had succeeded. However in -+ * this case B is dependent on how many buffers the user needs, not the -+ * stockpile-low threshold. -+ * Due to the different handling of B between the two cases, putting A -+ * and B in a while() loop would require quite obscure logic, so handle -+ * the different sequences explicitly. */ -+ if (num <= pool->sp_fill) { -+ /* Order 1: do A */ -+ copy_words(bufs, pool->sp + (pool->sp_fill - num), -+ sizeof(struct bm_buffer) * num); -+ pool->sp_fill -= num; -+ /* do B relative to STOCKPILE_LOW */ -+ while (pool->sp_fill <= BMAN_STOCKPILE_LOW) { -+ ret = __bman_acquire(pool, pool->sp + pool->sp_fill, 8); -+ if (ret < 0) -+ ret = __bman_acquire(pool, -+ pool->sp + pool->sp_fill, 1); -+ if (ret < 0) -+ break; -+ pool->sp_fill += ret; -+ } -+ } else { -+ /* Order 2: do B relative to 'num' */ -+ do { -+ ret = __bman_acquire(pool, pool->sp + pool->sp_fill, 8); -+ if (ret < 0) -+ ret = __bman_acquire(pool, -+ pool->sp + pool->sp_fill, 1); -+ if (ret < 0) -+ /* failure */ -+ goto acquire_done; -+ pool->sp_fill += ret; -+ } while (pool->sp_fill < num); -+ /* do A */ -+ copy_words(bufs, pool->sp + (pool->sp_fill - num), -+ sizeof(struct bm_buffer) * num); -+ pool->sp_fill -= num; -+ } -+ /* success */ -+ ret = num; -+acquire_done: -+#ifdef CONFIG_FSL_DPA_CHECKING -+ atomic_inc(&pool->in_use); -+#endif -+ return ret; -+} -+EXPORT_SYMBOL(bman_acquire); -+ -+int bman_flush_stockpile(struct bman_pool *pool, u32 flags) -+{ -+ u8 num; -+ int ret; -+ -+ while (pool->sp_fill) { -+ num = ((pool->sp_fill > 8) ? 8 : pool->sp_fill); -+ ret = __bman_release(pool, pool->sp + (pool->sp_fill - num), -+ num, flags); -+ if (ret) -+ return ret; -+ pool->sp_fill -= num; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(bman_flush_stockpile); -+ -+int bman_query_pools(struct bm_pool_state *state) -+{ -+ struct bman_portal *p = get_affine_portal(); -+ struct bm_mc_result *mcr; -+ __maybe_unused unsigned long irqflags; -+ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ bm_mc_start(&p->p); -+ bm_mc_commit(&p->p, BM_MCC_VERB_CMD_QUERY); -+ while (!(mcr = bm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & BM_MCR_VERB_CMD_MASK) == BM_MCR_VERB_CMD_QUERY); -+ *state = mcr->query; -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return 0; -+} -+EXPORT_SYMBOL(bman_query_pools); -+ -+#ifdef CONFIG_FSL_BMAN_CONFIG -+u32 bman_query_free_buffers(struct bman_pool *pool) -+{ -+ return bm_pool_free_buffers(pool->params.bpid); -+} -+EXPORT_SYMBOL(bman_query_free_buffers); -+ -+int bman_update_pool_thresholds(struct bman_pool *pool, const u32 *thresholds) -+{ -+ u32 bpid; -+ -+ bpid = bman_get_params(pool)->bpid; -+ -+ return bm_pool_set(bpid, thresholds); -+} -+EXPORT_SYMBOL(bman_update_pool_thresholds); -+#endif -+ -+int bman_shutdown_pool(u32 bpid) -+{ -+ struct bman_portal *p = get_affine_portal(); -+ __maybe_unused unsigned long irqflags; -+ int ret; -+ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ ret = bm_shutdown_pool(&p->p, bpid); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(bman_shutdown_pool); -+ -+const struct bm_portal_config *bman_get_bm_portal_config( -+ struct bman_portal *portal) -+{ -+ return portal->sharing_redirect ? NULL : portal->config; -+} ---- /dev/null -+++ b/drivers/staging/fsl_qbman/bman_low.h -@@ -0,0 +1,559 @@ -+/* Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "bman_private.h" -+ -+/***************************/ -+/* Portal register assists */ -+/***************************/ -+ -+#if defined(CONFIG_PPC32) || defined(CONFIG_PPC64) -+ -+/* Cache-inhibited register offsets */ -+#define BM_REG_RCR_PI_CINH 0x0000 -+#define BM_REG_RCR_CI_CINH 0x0004 -+#define BM_REG_RCR_ITR 0x0008 -+#define BM_REG_CFG 0x0100 -+#define BM_REG_SCN(n) (0x0200 + ((n) << 2)) -+#define BM_REG_ISR 0x0e00 -+#define BM_REG_IIR 0x0e0c -+ -+/* Cache-enabled register offsets */ -+#define BM_CL_CR 0x0000 -+#define BM_CL_RR0 0x0100 -+#define BM_CL_RR1 0x0140 -+#define BM_CL_RCR 0x1000 -+#define BM_CL_RCR_PI_CENA 0x3000 -+#define BM_CL_RCR_CI_CENA 0x3100 -+ -+#endif -+ -+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) -+ -+/* Cache-inhibited register offsets */ -+#define BM_REG_RCR_PI_CINH 0x3000 -+#define BM_REG_RCR_CI_CINH 0x3100 -+#define BM_REG_RCR_ITR 0x3200 -+#define BM_REG_CFG 0x3300 -+#define BM_REG_SCN(n) (0x3400 + ((n) << 6)) -+#define BM_REG_ISR 0x3e00 -+#define BM_REG_IIR 0x3ec0 -+ -+/* Cache-enabled register offsets */ -+#define BM_CL_CR 0x0000 -+#define BM_CL_RR0 0x0100 -+#define BM_CL_RR1 0x0140 -+#define BM_CL_RCR 0x1000 -+#define BM_CL_RCR_PI_CENA 0x3000 -+#define BM_CL_RCR_CI_CENA 0x3100 -+ -+#endif -+ -+/* BTW, the drivers (and h/w programming model) already obtain the required -+ * synchronisation for portal accesses via lwsync(), hwsync(), and -+ * data-dependencies. Use of barrier()s or other order-preserving primitives -+ * simply degrade performance. Hence the use of the __raw_*() interfaces, which -+ * simply ensure that the compiler treats the portal registers as volatile (ie. -+ * non-coherent). */ -+ -+/* Cache-inhibited register access. */ -+#define __bm_in(bm, o) be32_to_cpu(__raw_readl((bm)->addr_ci + (o))) -+#define __bm_out(bm, o, val) __raw_writel(cpu_to_be32(val), \ -+ (bm)->addr_ci + (o)); -+#define bm_in(reg) __bm_in(&portal->addr, BM_REG_##reg) -+#define bm_out(reg, val) __bm_out(&portal->addr, BM_REG_##reg, val) -+ -+/* Cache-enabled (index) register access */ -+#define __bm_cl_touch_ro(bm, o) dcbt_ro((bm)->addr_ce + (o)) -+#define __bm_cl_touch_rw(bm, o) dcbt_rw((bm)->addr_ce + (o)) -+#define __bm_cl_in(bm, o) be32_to_cpu(__raw_readl((bm)->addr_ce + (o))) -+#define __bm_cl_out(bm, o, val) \ -+ do { \ -+ u32 *__tmpclout = (bm)->addr_ce + (o); \ -+ __raw_writel(cpu_to_be32(val), __tmpclout); \ -+ dcbf(__tmpclout); \ -+ } while (0) -+#define __bm_cl_invalidate(bm, o) dcbi((bm)->addr_ce + (o)) -+#define bm_cl_touch_ro(reg) __bm_cl_touch_ro(&portal->addr, BM_CL_##reg##_CENA) -+#define bm_cl_touch_rw(reg) __bm_cl_touch_rw(&portal->addr, BM_CL_##reg##_CENA) -+#define bm_cl_in(reg) __bm_cl_in(&portal->addr, BM_CL_##reg##_CENA) -+#define bm_cl_out(reg, val) __bm_cl_out(&portal->addr, BM_CL_##reg##_CENA, val) -+#define bm_cl_invalidate(reg)\ -+ __bm_cl_invalidate(&portal->addr, BM_CL_##reg##_CENA) -+ -+/* Cyclic helper for rings. FIXME: once we are able to do fine-grain perf -+ * analysis, look at using the "extra" bit in the ring index registers to avoid -+ * cyclic issues. */ -+static inline u8 bm_cyc_diff(u8 ringsize, u8 first, u8 last) -+{ -+ /* 'first' is included, 'last' is excluded */ -+ if (first <= last) -+ return last - first; -+ return ringsize + last - first; -+} -+ -+/* Portal modes. -+ * Enum types; -+ * pmode == production mode -+ * cmode == consumption mode, -+ * Enum values use 3 letter codes. First letter matches the portal mode, -+ * remaining two letters indicate; -+ * ci == cache-inhibited portal register -+ * ce == cache-enabled portal register -+ * vb == in-band valid-bit (cache-enabled) -+ */ -+enum bm_rcr_pmode { /* matches BCSP_CFG::RPM */ -+ bm_rcr_pci = 0, /* PI index, cache-inhibited */ -+ bm_rcr_pce = 1, /* PI index, cache-enabled */ -+ bm_rcr_pvb = 2 /* valid-bit */ -+}; -+enum bm_rcr_cmode { /* s/w-only */ -+ bm_rcr_cci, /* CI index, cache-inhibited */ -+ bm_rcr_cce /* CI index, cache-enabled */ -+}; -+ -+ -+/* ------------------------- */ -+/* --- Portal structures --- */ -+ -+#define BM_RCR_SIZE 8 -+ -+struct bm_rcr { -+ struct bm_rcr_entry *ring, *cursor; -+ u8 ci, available, ithresh, vbit; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ u32 busy; -+ enum bm_rcr_pmode pmode; -+ enum bm_rcr_cmode cmode; -+#endif -+}; -+ -+struct bm_mc { -+ struct bm_mc_command *cr; -+ struct bm_mc_result *rr; -+ u8 rridx, vbit; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ enum { -+ /* Can only be _mc_start()ed */ -+ mc_idle, -+ /* Can only be _mc_commit()ed or _mc_abort()ed */ -+ mc_user, -+ /* Can only be _mc_retry()ed */ -+ mc_hw -+ } state; -+#endif -+}; -+ -+struct bm_addr { -+ void __iomem *addr_ce; /* cache-enabled */ -+ void __iomem *addr_ci; /* cache-inhibited */ -+}; -+ -+struct bm_portal { -+ struct bm_addr addr; -+ struct bm_rcr rcr; -+ struct bm_mc mc; -+ struct bm_portal_config config; -+} ____cacheline_aligned; -+ -+ -+/* --------------- */ -+/* --- RCR API --- */ -+ -+/* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */ -+#define RCR_CARRYCLEAR(p) \ -+ (void *)((unsigned long)(p) & (~(unsigned long)(BM_RCR_SIZE << 6))) -+ -+/* Bit-wise logic to convert a ring pointer to a ring index */ -+static inline u8 RCR_PTR2IDX(struct bm_rcr_entry *e) -+{ -+ return ((uintptr_t)e >> 6) & (BM_RCR_SIZE - 1); -+} -+ -+/* Increment the 'cursor' ring pointer, taking 'vbit' into account */ -+static inline void RCR_INC(struct bm_rcr *rcr) -+{ -+ /* NB: this is odd-looking, but experiments show that it generates -+ * fast code with essentially no branching overheads. We increment to -+ * the next RCR pointer and handle overflow and 'vbit'. */ -+ struct bm_rcr_entry *partial = rcr->cursor + 1; -+ rcr->cursor = RCR_CARRYCLEAR(partial); -+ if (partial != rcr->cursor) -+ rcr->vbit ^= BM_RCR_VERB_VBIT; -+} -+ -+static inline int bm_rcr_init(struct bm_portal *portal, enum bm_rcr_pmode pmode, -+ __maybe_unused enum bm_rcr_cmode cmode) -+{ -+ /* This use of 'register', as well as all other occurrences, is because -+ * it has been observed to generate much faster code with gcc than is -+ * otherwise the case. */ -+ register struct bm_rcr *rcr = &portal->rcr; -+ u32 cfg; -+ u8 pi; -+ -+ rcr->ring = portal->addr.addr_ce + BM_CL_RCR; -+ rcr->ci = bm_in(RCR_CI_CINH) & (BM_RCR_SIZE - 1); -+ -+ pi = bm_in(RCR_PI_CINH) & (BM_RCR_SIZE - 1); -+ rcr->cursor = rcr->ring + pi; -+ rcr->vbit = (bm_in(RCR_PI_CINH) & BM_RCR_SIZE) ? BM_RCR_VERB_VBIT : 0; -+ rcr->available = BM_RCR_SIZE - 1 -+ - bm_cyc_diff(BM_RCR_SIZE, rcr->ci, pi); -+ rcr->ithresh = bm_in(RCR_ITR); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ rcr->busy = 0; -+ rcr->pmode = pmode; -+ rcr->cmode = cmode; -+#endif -+ cfg = (bm_in(CFG) & 0xffffffe0) | (pmode & 0x3); /* BCSP_CFG::RPM */ -+ bm_out(CFG, cfg); -+ return 0; -+} -+ -+static inline void bm_rcr_finish(struct bm_portal *portal) -+{ -+ register struct bm_rcr *rcr = &portal->rcr; -+ u8 pi = bm_in(RCR_PI_CINH) & (BM_RCR_SIZE - 1); -+ u8 ci = bm_in(RCR_CI_CINH) & (BM_RCR_SIZE - 1); -+ DPA_ASSERT(!rcr->busy); -+ if (pi != RCR_PTR2IDX(rcr->cursor)) -+ pr_crit("losing uncommited RCR entries\n"); -+ if (ci != rcr->ci) -+ pr_crit("missing existing RCR completions\n"); -+ if (rcr->ci != RCR_PTR2IDX(rcr->cursor)) -+ pr_crit("RCR destroyed unquiesced\n"); -+} -+ -+static inline struct bm_rcr_entry *bm_rcr_start(struct bm_portal *portal) -+{ -+ register struct bm_rcr *rcr = &portal->rcr; -+ DPA_ASSERT(!rcr->busy); -+ if (!rcr->available) -+ return NULL; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ rcr->busy = 1; -+#endif -+ dcbz_64(rcr->cursor); -+ return rcr->cursor; -+} -+ -+static inline void bm_rcr_abort(struct bm_portal *portal) -+{ -+ __maybe_unused register struct bm_rcr *rcr = &portal->rcr; -+ DPA_ASSERT(rcr->busy); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ rcr->busy = 0; -+#endif -+} -+ -+static inline struct bm_rcr_entry *bm_rcr_pend_and_next( -+ struct bm_portal *portal, u8 myverb) -+{ -+ register struct bm_rcr *rcr = &portal->rcr; -+ DPA_ASSERT(rcr->busy); -+ DPA_ASSERT(rcr->pmode != bm_rcr_pvb); -+ if (rcr->available == 1) -+ return NULL; -+ rcr->cursor->__dont_write_directly__verb = myverb | rcr->vbit; -+ dcbf_64(rcr->cursor); -+ RCR_INC(rcr); -+ rcr->available--; -+ dcbz_64(rcr->cursor); -+ return rcr->cursor; -+} -+ -+static inline void bm_rcr_pci_commit(struct bm_portal *portal, u8 myverb) -+{ -+ register struct bm_rcr *rcr = &portal->rcr; -+ DPA_ASSERT(rcr->busy); -+ DPA_ASSERT(rcr->pmode == bm_rcr_pci); -+ rcr->cursor->__dont_write_directly__verb = myverb | rcr->vbit; -+ RCR_INC(rcr); -+ rcr->available--; -+ hwsync(); -+ bm_out(RCR_PI_CINH, RCR_PTR2IDX(rcr->cursor)); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ rcr->busy = 0; -+#endif -+} -+ -+static inline void bm_rcr_pce_prefetch(struct bm_portal *portal) -+{ -+ __maybe_unused register struct bm_rcr *rcr = &portal->rcr; -+ DPA_ASSERT(rcr->pmode == bm_rcr_pce); -+ bm_cl_invalidate(RCR_PI); -+ bm_cl_touch_rw(RCR_PI); -+} -+ -+static inline void bm_rcr_pce_commit(struct bm_portal *portal, u8 myverb) -+{ -+ register struct bm_rcr *rcr = &portal->rcr; -+ DPA_ASSERT(rcr->busy); -+ DPA_ASSERT(rcr->pmode == bm_rcr_pce); -+ rcr->cursor->__dont_write_directly__verb = myverb | rcr->vbit; -+ RCR_INC(rcr); -+ rcr->available--; -+ lwsync(); -+ bm_cl_out(RCR_PI, RCR_PTR2IDX(rcr->cursor)); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ rcr->busy = 0; -+#endif -+} -+ -+static inline void bm_rcr_pvb_commit(struct bm_portal *portal, u8 myverb) -+{ -+ register struct bm_rcr *rcr = &portal->rcr; -+ struct bm_rcr_entry *rcursor; -+ DPA_ASSERT(rcr->busy); -+ DPA_ASSERT(rcr->pmode == bm_rcr_pvb); -+ lwsync(); -+ rcursor = rcr->cursor; -+ rcursor->__dont_write_directly__verb = myverb | rcr->vbit; -+ dcbf_64(rcursor); -+ RCR_INC(rcr); -+ rcr->available--; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ rcr->busy = 0; -+#endif -+} -+ -+static inline u8 bm_rcr_cci_update(struct bm_portal *portal) -+{ -+ register struct bm_rcr *rcr = &portal->rcr; -+ u8 diff, old_ci = rcr->ci; -+ DPA_ASSERT(rcr->cmode == bm_rcr_cci); -+ rcr->ci = bm_in(RCR_CI_CINH) & (BM_RCR_SIZE - 1); -+ diff = bm_cyc_diff(BM_RCR_SIZE, old_ci, rcr->ci); -+ rcr->available += diff; -+ return diff; -+} -+ -+static inline void bm_rcr_cce_prefetch(struct bm_portal *portal) -+{ -+ __maybe_unused register struct bm_rcr *rcr = &portal->rcr; -+ DPA_ASSERT(rcr->cmode == bm_rcr_cce); -+ bm_cl_touch_ro(RCR_CI); -+} -+ -+static inline u8 bm_rcr_cce_update(struct bm_portal *portal) -+{ -+ register struct bm_rcr *rcr = &portal->rcr; -+ u8 diff, old_ci = rcr->ci; -+ DPA_ASSERT(rcr->cmode == bm_rcr_cce); -+ rcr->ci = bm_cl_in(RCR_CI) & (BM_RCR_SIZE - 1); -+ bm_cl_invalidate(RCR_CI); -+ diff = bm_cyc_diff(BM_RCR_SIZE, old_ci, rcr->ci); -+ rcr->available += diff; -+ return diff; -+} -+ -+static inline u8 bm_rcr_get_ithresh(struct bm_portal *portal) -+{ -+ register struct bm_rcr *rcr = &portal->rcr; -+ return rcr->ithresh; -+} -+ -+static inline void bm_rcr_set_ithresh(struct bm_portal *portal, u8 ithresh) -+{ -+ register struct bm_rcr *rcr = &portal->rcr; -+ rcr->ithresh = ithresh; -+ bm_out(RCR_ITR, ithresh); -+} -+ -+static inline u8 bm_rcr_get_avail(struct bm_portal *portal) -+{ -+ register struct bm_rcr *rcr = &portal->rcr; -+ return rcr->available; -+} -+ -+static inline u8 bm_rcr_get_fill(struct bm_portal *portal) -+{ -+ register struct bm_rcr *rcr = &portal->rcr; -+ return BM_RCR_SIZE - 1 - rcr->available; -+} -+ -+ -+/* ------------------------------ */ -+/* --- Management command API --- */ -+ -+static inline int bm_mc_init(struct bm_portal *portal) -+{ -+ register struct bm_mc *mc = &portal->mc; -+ mc->cr = portal->addr.addr_ce + BM_CL_CR; -+ mc->rr = portal->addr.addr_ce + BM_CL_RR0; -+ mc->rridx = (__raw_readb(&mc->cr->__dont_write_directly__verb) & -+ BM_MCC_VERB_VBIT) ? 0 : 1; -+ mc->vbit = mc->rridx ? BM_MCC_VERB_VBIT : 0; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ mc->state = mc_idle; -+#endif -+ return 0; -+} -+ -+static inline void bm_mc_finish(struct bm_portal *portal) -+{ -+ __maybe_unused register struct bm_mc *mc = &portal->mc; -+ DPA_ASSERT(mc->state == mc_idle); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ if (mc->state != mc_idle) -+ pr_crit("Losing incomplete MC command\n"); -+#endif -+} -+ -+static inline struct bm_mc_command *bm_mc_start(struct bm_portal *portal) -+{ -+ register struct bm_mc *mc = &portal->mc; -+ DPA_ASSERT(mc->state == mc_idle); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ mc->state = mc_user; -+#endif -+ dcbz_64(mc->cr); -+ return mc->cr; -+} -+ -+static inline void bm_mc_abort(struct bm_portal *portal) -+{ -+ __maybe_unused register struct bm_mc *mc = &portal->mc; -+ DPA_ASSERT(mc->state == mc_user); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ mc->state = mc_idle; -+#endif -+} -+ -+static inline void bm_mc_commit(struct bm_portal *portal, u8 myverb) -+{ -+ register struct bm_mc *mc = &portal->mc; -+ struct bm_mc_result *rr = mc->rr + mc->rridx; -+ DPA_ASSERT(mc->state == mc_user); -+ lwsync(); -+ mc->cr->__dont_write_directly__verb = myverb | mc->vbit; -+ dcbf(mc->cr); -+ dcbit_ro(rr); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ mc->state = mc_hw; -+#endif -+} -+ -+static inline struct bm_mc_result *bm_mc_result(struct bm_portal *portal) -+{ -+ register struct bm_mc *mc = &portal->mc; -+ struct bm_mc_result *rr = mc->rr + mc->rridx; -+ DPA_ASSERT(mc->state == mc_hw); -+ /* The inactive response register's verb byte always returns zero until -+ * its command is submitted and completed. This includes the valid-bit, -+ * in case you were wondering... */ -+ if (!__raw_readb(&rr->verb)) { -+ dcbit_ro(rr); -+ return NULL; -+ } -+ mc->rridx ^= 1; -+ mc->vbit ^= BM_MCC_VERB_VBIT; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ mc->state = mc_idle; -+#endif -+ return rr; -+} -+ -+ -+/* ------------------------------------- */ -+/* --- Portal interrupt register API --- */ -+ -+static inline int bm_isr_init(__always_unused struct bm_portal *portal) -+{ -+ return 0; -+} -+ -+static inline void bm_isr_finish(__always_unused struct bm_portal *portal) -+{ -+} -+ -+#define SCN_REG(bpid) BM_REG_SCN((bpid) / 32) -+#define SCN_BIT(bpid) (0x80000000 >> (bpid & 31)) -+static inline void bm_isr_bscn_mask(struct bm_portal *portal, u8 bpid, -+ int enable) -+{ -+ u32 val; -+ DPA_ASSERT(bpid < bman_pool_max); -+ /* REG_SCN for bpid=0..31, REG_SCN+4 for bpid=32..63 */ -+ val = __bm_in(&portal->addr, SCN_REG(bpid)); -+ if (enable) -+ val |= SCN_BIT(bpid); -+ else -+ val &= ~SCN_BIT(bpid); -+ __bm_out(&portal->addr, SCN_REG(bpid), val); -+} -+ -+static inline u32 __bm_isr_read(struct bm_portal *portal, enum bm_isr_reg n) -+{ -+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) -+ return __bm_in(&portal->addr, BM_REG_ISR + (n << 6)); -+#else -+ return __bm_in(&portal->addr, BM_REG_ISR + (n << 2)); -+#endif -+} -+ -+static inline void __bm_isr_write(struct bm_portal *portal, enum bm_isr_reg n, -+ u32 val) -+{ -+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) -+ __bm_out(&portal->addr, BM_REG_ISR + (n << 6), val); -+#else -+ __bm_out(&portal->addr, BM_REG_ISR + (n << 2), val); -+#endif -+} -+ -+/* Buffer Pool Cleanup */ -+static inline int bm_shutdown_pool(struct bm_portal *p, u32 bpid) -+{ -+ struct bm_mc_command *bm_cmd; -+ struct bm_mc_result *bm_res; -+ -+ int aq_count = 0; -+ bool stop = false; -+ while (!stop) { -+ /* Acquire buffers until empty */ -+ bm_cmd = bm_mc_start(p); -+ bm_cmd->acquire.bpid = bpid; -+ bm_mc_commit(p, BM_MCC_VERB_CMD_ACQUIRE | 1); -+ while (!(bm_res = bm_mc_result(p))) -+ cpu_relax(); -+ if (!(bm_res->verb & BM_MCR_VERB_ACQUIRE_BUFCOUNT)) { -+ /* Pool is empty */ -+ /* TBD : Should we do a few extra iterations in -+ case some other some blocks keep buffers 'on deck', -+ which may also be problematic */ -+ stop = true; -+ } else -+ ++aq_count; -+ } -+ return 0; -+} ---- /dev/null -+++ b/drivers/staging/fsl_qbman/bman_private.h -@@ -0,0 +1,166 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "dpa_sys.h" -+#include -+ -+/* Revision info (for errata and feature handling) */ -+#define BMAN_REV10 0x0100 -+#define BMAN_REV20 0x0200 -+#define BMAN_REV21 0x0201 -+#define QBMAN_ANY_PORTAL_IDX 0xffffffff -+extern u16 bman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */ -+ -+/* -+ * Global variables of the max portal/pool number this bman version supported -+ */ -+extern u16 bman_pool_max; -+ -+/* used by CCSR and portal interrupt code */ -+enum bm_isr_reg { -+ bm_isr_status = 0, -+ bm_isr_enable = 1, -+ bm_isr_disable = 2, -+ bm_isr_inhibit = 3 -+}; -+ -+struct bm_portal_config { -+ /* Corenet portal addresses; -+ * [0]==cache-enabled, [1]==cache-inhibited. */ -+ __iomem void *addr_virt[2]; -+ struct resource addr_phys[2]; -+ /* Allow these to be joined in lists */ -+ struct list_head list; -+ /* User-visible portal configuration settings */ -+ struct bman_portal_config public_cfg; -+ /* power management saved data */ -+ u32 saved_isdr; -+}; -+ -+#ifdef CONFIG_FSL_BMAN_CONFIG -+/* Hooks from bman_driver.c to bman_config.c */ -+int bman_init_ccsr(struct device_node *node); -+#endif -+ -+/* Hooks from bman_driver.c in to bman_high.c */ -+struct bman_portal *bman_create_portal( -+ struct bman_portal *portal, -+ const struct bm_portal_config *config); -+struct bman_portal *bman_create_affine_portal( -+ const struct bm_portal_config *config); -+struct bman_portal *bman_create_affine_slave(struct bman_portal *redirect, -+ int cpu); -+void bman_destroy_portal(struct bman_portal *bm); -+ -+const struct bm_portal_config *bman_destroy_affine_portal(void); -+ -+/* Hooks from fsl_usdpaa.c to bman_driver.c */ -+struct bm_portal_config *bm_get_unused_portal(void); -+struct bm_portal_config *bm_get_unused_portal_idx(uint32_t idx); -+void bm_put_unused_portal(struct bm_portal_config *pcfg); -+void bm_set_liodns(struct bm_portal_config *pcfg); -+ -+/* Pool logic in the portal driver, during initialisation, needs to know if -+ * there's access to CCSR or not (if not, it'll cripple the pool allocator). */ -+#ifdef CONFIG_FSL_BMAN_CONFIG -+int bman_have_ccsr(void); -+#else -+#define bman_have_ccsr() 0 -+#endif -+ -+/* Stockpile build constants. The _LOW value: when bman_acquire() is called and -+ * the stockpile fill-level is <= _LOW, an acquire is attempted from h/w but it -+ * might fail (if the buffer pool is depleted). So this value provides some -+ * "stagger" in that the bman_acquire() function will only fail if lots of bufs -+ * are requested at once or if h/w has been tested a couple of times without -+ * luck. The _HIGH value: when bman_release() is called and the stockpile -+ * fill-level is >= _HIGH, a release is attempted to h/w but it might fail (if -+ * the release ring is full). So this value provides some "stagger" so that -+ * ring-access is retried a couple of times prior to the API returning a -+ * failure. The following *must* be true; -+ * BMAN_STOCKPILE_HIGH-BMAN_STOCKPILE_LOW > 8 -+ * (to avoid thrashing) -+ * BMAN_STOCKPILE_SZ >= 16 -+ * (as the release logic expects to either send 8 buffers to hw prior to -+ * adding the given buffers to the stockpile or add the buffers to the -+ * stockpile before sending 8 to hw, as the API must be an all-or-nothing -+ * success/fail.) -+ */ -+#define BMAN_STOCKPILE_SZ 16u /* number of bufs in per-pool cache */ -+#define BMAN_STOCKPILE_LOW 2u /* when fill is <= this, acquire from hw */ -+#define BMAN_STOCKPILE_HIGH 14u /* when fill is >= this, release to hw */ -+ -+/*************************************************/ -+/* BMan s/w corenet portal, low-level i/face */ -+/*************************************************/ -+ -+/* Used by all portal interrupt registers except 'inhibit' -+ * This mask contains all the "irqsource" bits visible to API users -+ */ -+#define BM_PIRQ_VISIBLE (BM_PIRQ_RCRI | BM_PIRQ_BSCN) -+ -+/* These are bm__(). So for example, bm_disable_write() means "write -+ * the disable register" rather than "disable the ability to write". */ -+#define bm_isr_status_read(bm) __bm_isr_read(bm, bm_isr_status) -+#define bm_isr_status_clear(bm, m) __bm_isr_write(bm, bm_isr_status, m) -+#define bm_isr_enable_read(bm) __bm_isr_read(bm, bm_isr_enable) -+#define bm_isr_enable_write(bm, v) __bm_isr_write(bm, bm_isr_enable, v) -+#define bm_isr_disable_read(bm) __bm_isr_read(bm, bm_isr_disable) -+#define bm_isr_disable_write(bm, v) __bm_isr_write(bm, bm_isr_disable, v) -+#define bm_isr_inhibit(bm) __bm_isr_write(bm, bm_isr_inhibit, 1) -+#define bm_isr_uninhibit(bm) __bm_isr_write(bm, bm_isr_inhibit, 0) -+ -+#ifdef CONFIG_FSL_BMAN_CONFIG -+/* Set depletion thresholds associated with a buffer pool. Requires that the -+ * operating system have access to Bman CCSR (ie. compiled in support and -+ * run-time access courtesy of the device-tree). */ -+int bm_pool_set(u32 bpid, const u32 *thresholds); -+#define BM_POOL_THRESH_SW_ENTER 0 -+#define BM_POOL_THRESH_SW_EXIT 1 -+#define BM_POOL_THRESH_HW_ENTER 2 -+#define BM_POOL_THRESH_HW_EXIT 3 -+ -+/* Read the free buffer count for a given buffer */ -+u32 bm_pool_free_buffers(u32 bpid); -+ -+__init int bman_init(void); -+__init int bman_resource_init(void); -+ -+const struct bm_portal_config *bman_get_bm_portal_config( -+ struct bman_portal *portal); -+ -+/* power management */ -+#ifdef CONFIG_SUSPEND -+void suspend_unused_bportal(void); -+void resume_unused_bportal(void); -+#endif -+ -+#endif /* CONFIG_FSL_BMAN_CONFIG */ ---- /dev/null -+++ b/drivers/staging/fsl_qbman/bman_test.c -@@ -0,0 +1,56 @@ -+/* Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "bman_test.h" -+ -+MODULE_AUTHOR("Geoff Thorpe"); -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("Bman testing"); -+ -+static int test_init(void) -+{ -+#ifdef CONFIG_FSL_BMAN_TEST_HIGH -+ int loop = 1; -+ while (loop--) -+ bman_test_high(); -+#endif -+#ifdef CONFIG_FSL_BMAN_TEST_THRESH -+ bman_test_thresh(); -+#endif -+ return 0; -+} -+ -+static void test_exit(void) -+{ -+} -+ -+module_init(test_init); -+module_exit(test_exit); ---- /dev/null -+++ b/drivers/staging/fsl_qbman/bman_test.h -@@ -0,0 +1,44 @@ -+/* Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+void bman_test_high(void); -+void bman_test_thresh(void); ---- /dev/null -+++ b/drivers/staging/fsl_qbman/bman_test_high.c -@@ -0,0 +1,183 @@ -+/* Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "bman_test.h" -+#include "bman_private.h" -+ -+/*************/ -+/* constants */ -+/*************/ -+ -+#define PORTAL_OPAQUE ((void *)0xf00dbeef) -+#define POOL_OPAQUE ((void *)0xdeadabba) -+#define NUM_BUFS 93 -+#define LOOPS 3 -+#define BMAN_TOKEN_MASK 0x00FFFFFFFFFFLLU -+ -+/***************/ -+/* global vars */ -+/***************/ -+ -+static struct bman_pool *pool; -+static int depleted; -+static struct bm_buffer bufs_in[NUM_BUFS] ____cacheline_aligned; -+static struct bm_buffer bufs_out[NUM_BUFS] ____cacheline_aligned; -+static int bufs_received; -+ -+/* Predeclare the callback so we can instantiate pool parameters */ -+static void depletion_cb(struct bman_portal *, struct bman_pool *, void *, int); -+ -+/**********************/ -+/* internal functions */ -+/**********************/ -+ -+static void bufs_init(void) -+{ -+ int i; -+ for (i = 0; i < NUM_BUFS; i++) -+ bm_buffer_set64(&bufs_in[i], 0xfedc01234567LLU * i); -+ bufs_received = 0; -+} -+ -+static inline int bufs_cmp(const struct bm_buffer *a, const struct bm_buffer *b) -+{ -+ if ((bman_ip_rev == BMAN_REV20) || (bman_ip_rev == BMAN_REV21)) { -+ -+ /* On SoCs with Bman revison 2.0, Bman only respects the 40 -+ * LS-bits of buffer addresses, masking off the upper 8-bits on -+ * release commands. The API provides for 48-bit addresses -+ * because some SoCs support all 48-bits. When generating -+ * garbage addresses for testing, we either need to zero the -+ * upper 8-bits when releasing to Bman (otherwise we'll be -+ * disappointed when the buffers we acquire back from Bman -+ * don't match), or we need to mask the upper 8-bits off when -+ * comparing. We do the latter. -+ */ -+ if ((bm_buffer_get64(a) & BMAN_TOKEN_MASK) -+ < (bm_buffer_get64(b) & BMAN_TOKEN_MASK)) -+ return -1; -+ if ((bm_buffer_get64(a) & BMAN_TOKEN_MASK) -+ > (bm_buffer_get64(b) & BMAN_TOKEN_MASK)) -+ return 1; -+ } else { -+ if (bm_buffer_get64(a) < bm_buffer_get64(b)) -+ return -1; -+ if (bm_buffer_get64(a) > bm_buffer_get64(b)) -+ return 1; -+ } -+ -+ return 0; -+} -+ -+static void bufs_confirm(void) -+{ -+ int i, j; -+ for (i = 0; i < NUM_BUFS; i++) { -+ int matches = 0; -+ for (j = 0; j < NUM_BUFS; j++) -+ if (!bufs_cmp(&bufs_in[i], &bufs_out[j])) -+ matches++; -+ BUG_ON(matches != 1); -+ } -+} -+ -+/********/ -+/* test */ -+/********/ -+ -+static void depletion_cb(struct bman_portal *__portal, struct bman_pool *__pool, -+ void *pool_ctx, int __depleted) -+{ -+ BUG_ON(__pool != pool); -+ BUG_ON(pool_ctx != POOL_OPAQUE); -+ depleted = __depleted; -+} -+ -+void bman_test_high(void) -+{ -+ struct bman_pool_params pparams = { -+ .flags = BMAN_POOL_FLAG_DEPLETION | BMAN_POOL_FLAG_DYNAMIC_BPID, -+ .cb = depletion_cb, -+ .cb_ctx = POOL_OPAQUE, -+ }; -+ int i, loops = LOOPS; -+ struct bm_buffer tmp_buf; -+ -+ bufs_init(); -+ -+ pr_info("BMAN: --- starting high-level test ---\n"); -+ -+ pool = bman_new_pool(&pparams); -+ BUG_ON(!pool); -+ -+ /*******************/ -+ /* Release buffers */ -+ /*******************/ -+do_loop: -+ i = 0; -+ while (i < NUM_BUFS) { -+ u32 flags = BMAN_RELEASE_FLAG_WAIT; -+ int num = 8; -+ if ((i + num) > NUM_BUFS) -+ num = NUM_BUFS - i; -+ if ((i + num) == NUM_BUFS) -+ flags |= BMAN_RELEASE_FLAG_WAIT_SYNC; -+ if (bman_release(pool, bufs_in + i, num, flags)) -+ panic("bman_release() failed\n"); -+ i += num; -+ } -+ -+ /*******************/ -+ /* Acquire buffers */ -+ /*******************/ -+ while (i > 0) { -+ int tmp, num = 8; -+ if (num > i) -+ num = i; -+ tmp = bman_acquire(pool, bufs_out + i - num, num, 0); -+ BUG_ON(tmp != num); -+ i -= num; -+ } -+ -+ i = bman_acquire(pool, &tmp_buf, 1, 0); -+ BUG_ON(i > 0); -+ -+ bufs_confirm(); -+ -+ if (--loops) -+ goto do_loop; -+ -+ /************/ -+ /* Clean up */ -+ /************/ -+ bman_free_pool(pool); -+ pr_info("BMAN: --- finished high-level test ---\n"); -+} ---- /dev/null -+++ b/drivers/staging/fsl_qbman/bman_test_thresh.c -@@ -0,0 +1,196 @@ -+/* Copyright 2010-2011 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "bman_test.h" -+ -+/* Test constants */ -+#define TEST_NUMBUFS 129728 -+#define TEST_EXIT 129536 -+#define TEST_ENTRY 129024 -+ -+struct affine_test_data { -+ struct task_struct *t; -+ int cpu; -+ int expect_affinity; -+ int drain; -+ int num_enter; -+ int num_exit; -+ struct list_head node; -+ struct completion wakethread; -+ struct completion wakeparent; -+}; -+ -+static void cb_depletion(struct bman_portal *portal, -+ struct bman_pool *pool, -+ void *opaque, -+ int depleted) -+{ -+ struct affine_test_data *data = opaque; -+ int c = smp_processor_id(); -+ pr_info("cb_depletion: bpid=%d, depleted=%d, cpu=%d, original=%d\n", -+ bman_get_params(pool)->bpid, !!depleted, c, data->cpu); -+ /* We should be executing on the CPU of the thread that owns the pool if -+ * and that CPU has an affine portal (ie. it isn't slaved). */ -+ BUG_ON((c != data->cpu) && data->expect_affinity); -+ BUG_ON((c == data->cpu) && !data->expect_affinity); -+ if (depleted) -+ data->num_enter++; -+ else -+ data->num_exit++; -+} -+ -+/* Params used to set up a pool, this also dynamically allocates a BPID */ -+static const struct bman_pool_params params_nocb = { -+ .flags = BMAN_POOL_FLAG_DYNAMIC_BPID | BMAN_POOL_FLAG_THRESH, -+ .thresholds = { TEST_ENTRY, TEST_EXIT, 0, 0 } -+}; -+ -+/* Params used to set up each cpu's pool with callbacks enabled */ -+static struct bman_pool_params params_cb = { -+ .bpid = 0, /* will be replaced to match pool_nocb */ -+ .flags = BMAN_POOL_FLAG_DEPLETION, -+ .cb = cb_depletion -+}; -+ -+static struct bman_pool *pool_nocb; -+static LIST_HEAD(threads); -+ -+static int affine_test(void *__data) -+{ -+ struct bman_pool *pool; -+ struct affine_test_data *data = __data; -+ struct bman_pool_params my_params = params_cb; -+ -+ pr_info("thread %d: starting\n", data->cpu); -+ /* create the pool */ -+ my_params.cb_ctx = data; -+ pool = bman_new_pool(&my_params); -+ BUG_ON(!pool); -+ complete(&data->wakeparent); -+ wait_for_completion(&data->wakethread); -+ init_completion(&data->wakethread); -+ -+ /* if we're the drainer, we get signalled for that */ -+ if (data->drain) { -+ struct bm_buffer buf; -+ int ret; -+ pr_info("thread %d: draining...\n", data->cpu); -+ do { -+ ret = bman_acquire(pool, &buf, 1, 0); -+ } while (ret > 0); -+ pr_info("thread %d: draining done.\n", data->cpu); -+ complete(&data->wakeparent); -+ wait_for_completion(&data->wakethread); -+ init_completion(&data->wakethread); -+ } -+ -+ /* cleanup */ -+ bman_free_pool(pool); -+ while (!kthread_should_stop()) -+ cpu_relax(); -+ pr_info("thread %d: exiting\n", data->cpu); -+ return 0; -+} -+ -+static struct affine_test_data *start_affine_test(int cpu, int drain) -+{ -+ struct affine_test_data *data = kmalloc(sizeof(*data), GFP_KERNEL); -+ -+ if (!data) -+ return NULL; -+ data->cpu = cpu; -+ data->expect_affinity = cpumask_test_cpu(cpu, bman_affine_cpus()); -+ data->drain = drain; -+ data->num_enter = 0; -+ data->num_exit = 0; -+ init_completion(&data->wakethread); -+ init_completion(&data->wakeparent); -+ list_add_tail(&data->node, &threads); -+ data->t = kthread_create(affine_test, data, "threshtest%d", cpu); -+ BUG_ON(IS_ERR(data->t)); -+ kthread_bind(data->t, cpu); -+ wake_up_process(data->t); -+ return data; -+} -+ -+void bman_test_thresh(void) -+{ -+ int loop = TEST_NUMBUFS; -+ int ret, num_cpus = 0; -+ struct affine_test_data *data, *drainer = NULL; -+ -+ pr_info("bman_test_thresh: start\n"); -+ -+ /* allocate a BPID and seed it */ -+ pool_nocb = bman_new_pool(¶ms_nocb); -+ BUG_ON(!pool_nocb); -+ while (loop--) { -+ struct bm_buffer buf; -+ bm_buffer_set64(&buf, 0x0badbeef + loop); -+ ret = bman_release(pool_nocb, &buf, 1, -+ BMAN_RELEASE_FLAG_WAIT); -+ BUG_ON(ret); -+ } -+ while (!bman_rcr_is_empty()) -+ cpu_relax(); -+ pr_info("bman_test_thresh: buffers are in\n"); -+ -+ /* create threads and wait for them to create pools */ -+ params_cb.bpid = bman_get_params(pool_nocb)->bpid; -+ for_each_cpu(loop, cpu_online_mask) { -+ data = start_affine_test(loop, drainer ? 0 : 1); -+ BUG_ON(!data); -+ if (!drainer) -+ drainer = data; -+ num_cpus++; -+ wait_for_completion(&data->wakeparent); -+ } -+ -+ /* signal the drainer to start draining */ -+ complete(&drainer->wakethread); -+ wait_for_completion(&drainer->wakeparent); -+ init_completion(&drainer->wakeparent); -+ -+ /* tear down */ -+ list_for_each_entry_safe(data, drainer, &threads, node) { -+ complete(&data->wakethread); -+ ret = kthread_stop(data->t); -+ BUG_ON(ret); -+ list_del(&data->node); -+ /* check that we get the expected callbacks (and no others) */ -+ BUG_ON(data->num_enter != 1); -+ BUG_ON(data->num_exit != 0); -+ kfree(data); -+ } -+ bman_free_pool(pool_nocb); -+ -+ pr_info("bman_test_thresh: done\n"); -+} ---- /dev/null -+++ b/drivers/staging/fsl_qbman/dpa_alloc.c -@@ -0,0 +1,706 @@ -+/* Copyright 2009-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "dpa_sys.h" -+#include -+#include -+ -+/* Qman and Bman APIs are front-ends to the common code; */ -+ -+static DECLARE_DPA_ALLOC(bpalloc); /* BPID allocator */ -+static DECLARE_DPA_ALLOC(fqalloc); /* FQID allocator */ -+static DECLARE_DPA_ALLOC(qpalloc); /* pool-channel allocator */ -+static DECLARE_DPA_ALLOC(cgralloc); /* CGR ID allocator */ -+static DECLARE_DPA_ALLOC(ceetm0_challoc); /* CEETM Channel ID allocator */ -+static DECLARE_DPA_ALLOC(ceetm0_lfqidalloc); /* CEETM LFQID allocator */ -+static DECLARE_DPA_ALLOC(ceetm1_challoc); /* CEETM Channel ID allocator */ -+static DECLARE_DPA_ALLOC(ceetm1_lfqidalloc); /* CEETM LFQID allocator */ -+ -+/* This is a sort-of-conditional dpa_alloc_free() routine. Eg. when releasing -+ * FQIDs (probably from user-space), it can filter out those that aren't in the -+ * OOS state (better to leak a h/w resource than to crash). This function -+ * returns the number of invalid IDs that were not released. */ -+static u32 release_id_range(struct dpa_alloc *alloc, u32 id, u32 count, -+ int (*is_valid)(u32 id)) -+{ -+ int valid_mode = 0; -+ u32 loop = id, total_invalid = 0; -+ while (loop < (id + count)) { -+ int isvalid = is_valid ? is_valid(loop) : 1; -+ if (!valid_mode) { -+ /* We're looking for a valid ID to terminate an invalid -+ * range */ -+ if (isvalid) { -+ /* We finished a range of invalid IDs, a valid -+ * range is now underway */ -+ valid_mode = 1; -+ count -= (loop - id); -+ id = loop; -+ } else -+ total_invalid++; -+ } else { -+ /* We're looking for an invalid ID to terminate a -+ * valid range */ -+ if (!isvalid) { -+ /* Release the range of valid IDs, an unvalid -+ * range is now underway */ -+ if (loop > id) -+ dpa_alloc_free(alloc, id, loop - id); -+ valid_mode = 0; -+ } -+ } -+ loop++; -+ } -+ /* Release any unterminated range of valid IDs */ -+ if (valid_mode && count) -+ dpa_alloc_free(alloc, id, count); -+ return total_invalid; -+} -+ -+/* BPID allocator front-end */ -+ -+int bman_alloc_bpid_range(u32 *result, u32 count, u32 align, int partial) -+{ -+ return dpa_alloc_new(&bpalloc, result, count, align, partial); -+} -+EXPORT_SYMBOL(bman_alloc_bpid_range); -+ -+static int bp_cleanup(u32 bpid) -+{ -+ return bman_shutdown_pool(bpid) == 0; -+} -+void bman_release_bpid_range(u32 bpid, u32 count) -+{ -+ u32 total_invalid = release_id_range(&bpalloc, bpid, count, bp_cleanup); -+ if (total_invalid) -+ pr_err("BPID range [%d..%d] (%d) had %d leaks\n", -+ bpid, bpid + count - 1, count, total_invalid); -+} -+EXPORT_SYMBOL(bman_release_bpid_range); -+ -+void bman_seed_bpid_range(u32 bpid, u32 count) -+{ -+ dpa_alloc_seed(&bpalloc, bpid, count); -+} -+EXPORT_SYMBOL(bman_seed_bpid_range); -+ -+int bman_reserve_bpid_range(u32 bpid, u32 count) -+{ -+ return dpa_alloc_reserve(&bpalloc, bpid, count); -+} -+EXPORT_SYMBOL(bman_reserve_bpid_range); -+ -+ -+/* FQID allocator front-end */ -+ -+int qman_alloc_fqid_range(u32 *result, u32 count, u32 align, int partial) -+{ -+ return dpa_alloc_new(&fqalloc, result, count, align, partial); -+} -+EXPORT_SYMBOL(qman_alloc_fqid_range); -+ -+static int fq_cleanup(u32 fqid) -+{ -+ return qman_shutdown_fq(fqid) == 0; -+} -+void qman_release_fqid_range(u32 fqid, u32 count) -+{ -+ u32 total_invalid = release_id_range(&fqalloc, fqid, count, fq_cleanup); -+ if (total_invalid) -+ pr_err("FQID range [%d..%d] (%d) had %d leaks\n", -+ fqid, fqid + count - 1, count, total_invalid); -+} -+EXPORT_SYMBOL(qman_release_fqid_range); -+ -+int qman_reserve_fqid_range(u32 fqid, u32 count) -+{ -+ return dpa_alloc_reserve(&fqalloc, fqid, count); -+} -+EXPORT_SYMBOL(qman_reserve_fqid_range); -+ -+void qman_seed_fqid_range(u32 fqid, u32 count) -+{ -+ dpa_alloc_seed(&fqalloc, fqid, count); -+} -+EXPORT_SYMBOL(qman_seed_fqid_range); -+ -+/* Pool-channel allocator front-end */ -+ -+int qman_alloc_pool_range(u32 *result, u32 count, u32 align, int partial) -+{ -+ return dpa_alloc_new(&qpalloc, result, count, align, partial); -+} -+EXPORT_SYMBOL(qman_alloc_pool_range); -+ -+static int qpool_cleanup(u32 qp) -+{ -+ /* We query all FQDs starting from -+ * FQID 1 until we get an "invalid FQID" error, looking for non-OOS FQDs -+ * whose destination channel is the pool-channel being released. -+ * When a non-OOS FQD is found we attempt to clean it up */ -+ struct qman_fq fq = { -+ .fqid = 1 -+ }; -+ int err; -+ do { -+ struct qm_mcr_queryfq_np np; -+ err = qman_query_fq_np(&fq, &np); -+ if (err) -+ /* FQID range exceeded, found no problems */ -+ return 1; -+ if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) { -+ struct qm_fqd fqd; -+ err = qman_query_fq(&fq, &fqd); -+ BUG_ON(err); -+ if (fqd.dest.channel == qp) { -+ /* The channel is the FQ's target, clean it */ -+ if (qman_shutdown_fq(fq.fqid) != 0) -+ /* Couldn't shut down the FQ -+ so the pool must be leaked */ -+ return 0; -+ } -+ } -+ /* Move to the next FQID */ -+ fq.fqid++; -+ } while (1); -+} -+void qman_release_pool_range(u32 qp, u32 count) -+{ -+ u32 total_invalid = release_id_range(&qpalloc, qp, -+ count, qpool_cleanup); -+ if (total_invalid) { -+ /* Pool channels are almost always used individually */ -+ if (count == 1) -+ pr_err("Pool channel 0x%x had %d leaks\n", -+ qp, total_invalid); -+ else -+ pr_err("Pool channels [%d..%d] (%d) had %d leaks\n", -+ qp, qp + count - 1, count, total_invalid); -+ } -+} -+EXPORT_SYMBOL(qman_release_pool_range); -+ -+ -+void qman_seed_pool_range(u32 poolid, u32 count) -+{ -+ dpa_alloc_seed(&qpalloc, poolid, count); -+ -+} -+EXPORT_SYMBOL(qman_seed_pool_range); -+ -+int qman_reserve_pool_range(u32 poolid, u32 count) -+{ -+ return dpa_alloc_reserve(&qpalloc, poolid, count); -+} -+EXPORT_SYMBOL(qman_reserve_pool_range); -+ -+ -+/* CGR ID allocator front-end */ -+ -+int qman_alloc_cgrid_range(u32 *result, u32 count, u32 align, int partial) -+{ -+ return dpa_alloc_new(&cgralloc, result, count, align, partial); -+} -+EXPORT_SYMBOL(qman_alloc_cgrid_range); -+ -+static int cqr_cleanup(u32 cgrid) -+{ -+ /* We query all FQDs starting from -+ * FQID 1 until we get an "invalid FQID" error, looking for non-OOS FQDs -+ * whose CGR is the CGR being released. -+ */ -+ struct qman_fq fq = { -+ .fqid = 1 -+ }; -+ int err; -+ do { -+ struct qm_mcr_queryfq_np np; -+ err = qman_query_fq_np(&fq, &np); -+ if (err) -+ /* FQID range exceeded, found no problems */ -+ return 1; -+ if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) { -+ struct qm_fqd fqd; -+ err = qman_query_fq(&fq, &fqd); -+ BUG_ON(err); -+ if ((fqd.fq_ctrl & QM_FQCTRL_CGE) && -+ (fqd.cgid == cgrid)) { -+ pr_err("CRGID 0x%x is being used by FQID 0x%x," -+ " CGR will be leaked\n", -+ cgrid, fq.fqid); -+ return 1; -+ } -+ } -+ /* Move to the next FQID */ -+ fq.fqid++; -+ } while (1); -+} -+ -+void qman_release_cgrid_range(u32 cgrid, u32 count) -+{ -+ u32 total_invalid = release_id_range(&cgralloc, cgrid, -+ count, cqr_cleanup); -+ if (total_invalid) -+ pr_err("CGRID range [%d..%d] (%d) had %d leaks\n", -+ cgrid, cgrid + count - 1, count, total_invalid); -+} -+EXPORT_SYMBOL(qman_release_cgrid_range); -+ -+void qman_seed_cgrid_range(u32 cgrid, u32 count) -+{ -+ dpa_alloc_seed(&cgralloc, cgrid, count); -+ -+} -+EXPORT_SYMBOL(qman_seed_cgrid_range); -+ -+/* CEETM CHANNEL ID allocator front-end */ -+int qman_alloc_ceetm0_channel_range(u32 *result, u32 count, u32 align, -+ int partial) -+{ -+ return dpa_alloc_new(&ceetm0_challoc, result, count, align, partial); -+} -+EXPORT_SYMBOL(qman_alloc_ceetm0_channel_range); -+ -+int qman_alloc_ceetm1_channel_range(u32 *result, u32 count, u32 align, -+ int partial) -+{ -+ return dpa_alloc_new(&ceetm1_challoc, result, count, align, partial); -+} -+EXPORT_SYMBOL(qman_alloc_ceetm1_channel_range); -+ -+void qman_release_ceetm0_channel_range(u32 channelid, u32 count) -+{ -+ u32 total_invalid; -+ -+ total_invalid = release_id_range(&ceetm0_challoc, channelid, count, -+ NULL); -+ if (total_invalid) -+ pr_err("CEETM channel range [%d..%d] (%d) had %d leaks\n", -+ channelid, channelid + count - 1, count, total_invalid); -+} -+EXPORT_SYMBOL(qman_release_ceetm0_channel_range); -+ -+void qman_seed_ceetm0_channel_range(u32 channelid, u32 count) -+{ -+ dpa_alloc_seed(&ceetm0_challoc, channelid, count); -+ -+} -+EXPORT_SYMBOL(qman_seed_ceetm0_channel_range); -+ -+void qman_release_ceetm1_channel_range(u32 channelid, u32 count) -+{ -+ u32 total_invalid; -+ total_invalid = release_id_range(&ceetm1_challoc, channelid, count, -+ NULL); -+ if (total_invalid) -+ pr_err("CEETM channel range [%d..%d] (%d) had %d leaks\n", -+ channelid, channelid + count - 1, count, total_invalid); -+} -+EXPORT_SYMBOL(qman_release_ceetm1_channel_range); -+ -+void qman_seed_ceetm1_channel_range(u32 channelid, u32 count) -+{ -+ dpa_alloc_seed(&ceetm1_challoc, channelid, count); -+ -+} -+EXPORT_SYMBOL(qman_seed_ceetm1_channel_range); -+ -+/* CEETM LFQID allocator front-end */ -+int qman_alloc_ceetm0_lfqid_range(u32 *result, u32 count, u32 align, -+ int partial) -+{ -+ return dpa_alloc_new(&ceetm0_lfqidalloc, result, count, align, partial); -+} -+EXPORT_SYMBOL(qman_alloc_ceetm0_lfqid_range); -+ -+int qman_alloc_ceetm1_lfqid_range(u32 *result, u32 count, u32 align, -+ int partial) -+{ -+ return dpa_alloc_new(&ceetm1_lfqidalloc, result, count, align, partial); -+} -+EXPORT_SYMBOL(qman_alloc_ceetm1_lfqid_range); -+ -+void qman_release_ceetm0_lfqid_range(u32 lfqid, u32 count) -+{ -+ u32 total_invalid; -+ -+ total_invalid = release_id_range(&ceetm0_lfqidalloc, lfqid, count, -+ NULL); -+ if (total_invalid) -+ pr_err("CEETM LFQID range [0x%x..0x%x] (%d) had %d leaks\n", -+ lfqid, lfqid + count - 1, count, total_invalid); -+} -+EXPORT_SYMBOL(qman_release_ceetm0_lfqid_range); -+ -+void qman_seed_ceetm0_lfqid_range(u32 lfqid, u32 count) -+{ -+ dpa_alloc_seed(&ceetm0_lfqidalloc, lfqid, count); -+ -+} -+EXPORT_SYMBOL(qman_seed_ceetm0_lfqid_range); -+ -+void qman_release_ceetm1_lfqid_range(u32 lfqid, u32 count) -+{ -+ u32 total_invalid; -+ -+ total_invalid = release_id_range(&ceetm1_lfqidalloc, lfqid, count, -+ NULL); -+ if (total_invalid) -+ pr_err("CEETM LFQID range [0x%x..0x%x] (%d) had %d leaks\n", -+ lfqid, lfqid + count - 1, count, total_invalid); -+} -+EXPORT_SYMBOL(qman_release_ceetm1_lfqid_range); -+ -+void qman_seed_ceetm1_lfqid_range(u32 lfqid, u32 count) -+{ -+ dpa_alloc_seed(&ceetm1_lfqidalloc, lfqid, count); -+ -+} -+EXPORT_SYMBOL(qman_seed_ceetm1_lfqid_range); -+ -+ -+/* Everything else is the common backend to all the allocators */ -+ -+/* The allocator is a (possibly-empty) list of these; */ -+struct alloc_node { -+ struct list_head list; -+ u32 base; -+ u32 num; -+ /* refcount and is_alloced are only set -+ when the node is in the used list */ -+ unsigned int refcount; -+ int is_alloced; -+}; -+ -+/* #define DPA_ALLOC_DEBUG */ -+ -+#ifdef DPA_ALLOC_DEBUG -+#define DPRINT pr_info -+static void DUMP(struct dpa_alloc *alloc) -+{ -+ int off = 0; -+ char buf[256]; -+ struct alloc_node *p; -+ pr_info("Free Nodes\n"); -+ list_for_each_entry(p, &alloc->free, list) { -+ if (off < 255) -+ off += snprintf(buf + off, 255-off, "{%d,%d}", -+ p->base, p->base + p->num - 1); -+ } -+ pr_info("%s\n", buf); -+ -+ off = 0; -+ pr_info("Used Nodes\n"); -+ list_for_each_entry(p, &alloc->used, list) { -+ if (off < 255) -+ off += snprintf(buf + off, 255-off, "{%d,%d}", -+ p->base, p->base + p->num - 1); -+ } -+ pr_info("%s\n", buf); -+ -+ -+ -+} -+#else -+#define DPRINT(x...) -+#define DUMP(a) -+#endif -+ -+int dpa_alloc_new(struct dpa_alloc *alloc, u32 *result, u32 count, u32 align, -+ int partial) -+{ -+ struct alloc_node *i = NULL, *next_best = NULL, *used_node = NULL; -+ u32 base, next_best_base = 0, num = 0, next_best_num = 0; -+ struct alloc_node *margin_left, *margin_right; -+ -+ *result = (u32)-1; -+ DPRINT("alloc_range(%d,%d,%d)\n", count, align, partial); -+ DUMP(alloc); -+ /* If 'align' is 0, it should behave as though it was 1 */ -+ if (!align) -+ align = 1; -+ margin_left = kmalloc(sizeof(*margin_left), GFP_KERNEL); -+ if (!margin_left) -+ goto err; -+ margin_right = kmalloc(sizeof(*margin_right), GFP_KERNEL); -+ if (!margin_right) { -+ kfree(margin_left); -+ goto err; -+ } -+ spin_lock_irq(&alloc->lock); -+ list_for_each_entry(i, &alloc->free, list) { -+ base = (i->base + align - 1) / align; -+ base *= align; -+ if ((base - i->base) >= i->num) -+ /* alignment is impossible, regardless of count */ -+ continue; -+ num = i->num - (base - i->base); -+ if (num >= count) { -+ /* this one will do nicely */ -+ num = count; -+ goto done; -+ } -+ if (num > next_best_num) { -+ next_best = i; -+ next_best_base = base; -+ next_best_num = num; -+ } -+ } -+ if (partial && next_best) { -+ i = next_best; -+ base = next_best_base; -+ num = next_best_num; -+ } else -+ i = NULL; -+done: -+ if (i) { -+ if (base != i->base) { -+ margin_left->base = i->base; -+ margin_left->num = base - i->base; -+ list_add_tail(&margin_left->list, &i->list); -+ } else -+ kfree(margin_left); -+ if ((base + num) < (i->base + i->num)) { -+ margin_right->base = base + num; -+ margin_right->num = (i->base + i->num) - -+ (base + num); -+ list_add(&margin_right->list, &i->list); -+ } else -+ kfree(margin_right); -+ list_del(&i->list); -+ kfree(i); -+ *result = base; -+ } else { -+ spin_unlock_irq(&alloc->lock); -+ kfree(margin_left); -+ kfree(margin_right); -+ } -+ -+err: -+ DPRINT("returning %d\n", i ? num : -ENOMEM); -+ DUMP(alloc); -+ if (!i) -+ return -ENOMEM; -+ -+ /* Add the allocation to the used list with a refcount of 1 */ -+ used_node = kmalloc(sizeof(*used_node), GFP_KERNEL); -+ if (!used_node) { -+ spin_unlock_irq(&alloc->lock); -+ return -ENOMEM; -+ } -+ used_node->base = *result; -+ used_node->num = num; -+ used_node->refcount = 1; -+ used_node->is_alloced = 1; -+ list_add_tail(&used_node->list, &alloc->used); -+ spin_unlock_irq(&alloc->lock); -+ return (int)num; -+} -+ -+/* Allocate the list node using GFP_ATOMIC, because we *really* want to avoid -+ * forcing error-handling on to users in the deallocation path. */ -+static void _dpa_alloc_free(struct dpa_alloc *alloc, u32 base_id, u32 count) -+{ -+ struct alloc_node *i, *node = kmalloc(sizeof(*node), GFP_ATOMIC); -+ BUG_ON(!node); -+ DPRINT("release_range(%d,%d)\n", base_id, count); -+ DUMP(alloc); -+ BUG_ON(!count); -+ spin_lock_irq(&alloc->lock); -+ -+ -+ node->base = base_id; -+ node->num = count; -+ list_for_each_entry(i, &alloc->free, list) { -+ if (i->base >= node->base) { -+ /* BUG_ON(any overlapping) */ -+ BUG_ON(i->base < (node->base + node->num)); -+ list_add_tail(&node->list, &i->list); -+ goto done; -+ } -+ } -+ list_add_tail(&node->list, &alloc->free); -+done: -+ /* Merge to the left */ -+ i = list_entry(node->list.prev, struct alloc_node, list); -+ if (node->list.prev != &alloc->free) { -+ BUG_ON((i->base + i->num) > node->base); -+ if ((i->base + i->num) == node->base) { -+ node->base = i->base; -+ node->num += i->num; -+ list_del(&i->list); -+ kfree(i); -+ } -+ } -+ /* Merge to the right */ -+ i = list_entry(node->list.next, struct alloc_node, list); -+ if (node->list.next != &alloc->free) { -+ BUG_ON((node->base + node->num) > i->base); -+ if ((node->base + node->num) == i->base) { -+ node->num += i->num; -+ list_del(&i->list); -+ kfree(i); -+ } -+ } -+ spin_unlock_irq(&alloc->lock); -+ DUMP(alloc); -+} -+ -+ -+void dpa_alloc_free(struct dpa_alloc *alloc, u32 base_id, u32 count) -+{ -+ struct alloc_node *i = NULL; -+ spin_lock_irq(&alloc->lock); -+ -+ /* First find the node in the used list and decrement its ref count */ -+ list_for_each_entry(i, &alloc->used, list) { -+ if (i->base == base_id && i->num == count) { -+ --i->refcount; -+ if (i->refcount == 0) { -+ list_del(&i->list); -+ spin_unlock_irq(&alloc->lock); -+ if (i->is_alloced) -+ _dpa_alloc_free(alloc, base_id, count); -+ kfree(i); -+ return; -+ } -+ spin_unlock_irq(&alloc->lock); -+ return; -+ } -+ } -+ /* Couldn't find the allocation */ -+ pr_err("Attempt to free ID 0x%x COUNT %d that wasn't alloc'd or reserved\n", -+ base_id, count); -+ spin_unlock_irq(&alloc->lock); -+} -+ -+void dpa_alloc_seed(struct dpa_alloc *alloc, u32 base_id, u32 count) -+{ -+ /* Same as free but no previous allocation checking is needed */ -+ _dpa_alloc_free(alloc, base_id, count); -+} -+ -+ -+int dpa_alloc_reserve(struct dpa_alloc *alloc, u32 base, u32 num) -+{ -+ struct alloc_node *i = NULL, *used_node; -+ -+ DPRINT("alloc_reserve(%d,%d)\n", base, num); -+ DUMP(alloc); -+ -+ spin_lock_irq(&alloc->lock); -+ -+ /* Check for the node in the used list. -+ If found, increase it's refcount */ -+ list_for_each_entry(i, &alloc->used, list) { -+ if ((i->base == base) && (i->num == num)) { -+ ++i->refcount; -+ spin_unlock_irq(&alloc->lock); -+ return 0; -+ } -+ if ((base >= i->base) && (base < (i->base + i->num))) { -+ /* This is an attempt to reserve a region that was -+ already reserved or alloced with a different -+ base or num */ -+ pr_err("Cannot reserve %d - %d, it overlaps with" -+ " existing reservation from %d - %d\n", -+ base, base + num - 1, i->base, -+ i->base + i->num - 1); -+ spin_unlock_irq(&alloc->lock); -+ return -1; -+ } -+ } -+ /* Check to make sure this ID isn't in the free list */ -+ list_for_each_entry(i, &alloc->free, list) { -+ if ((base >= i->base) && (base < (i->base + i->num))) { -+ /* yep, the reservation is within this node */ -+ pr_err("Cannot reserve %d - %d, it overlaps with" -+ " free range %d - %d and must be alloced\n", -+ base, base + num - 1, -+ i->base, i->base + i->num - 1); -+ spin_unlock_irq(&alloc->lock); -+ return -1; -+ } -+ } -+ /* Add the allocation to the used list with a refcount of 1 */ -+ used_node = kmalloc(sizeof(*used_node), GFP_KERNEL); -+ if (!used_node) { -+ spin_unlock_irq(&alloc->lock); -+ return -ENOMEM; -+ -+ } -+ used_node->base = base; -+ used_node->num = num; -+ used_node->refcount = 1; -+ used_node->is_alloced = 0; -+ list_add_tail(&used_node->list, &alloc->used); -+ spin_unlock_irq(&alloc->lock); -+ return 0; -+} -+ -+ -+int dpa_alloc_pop(struct dpa_alloc *alloc, u32 *result, u32 *count) -+{ -+ struct alloc_node *i = NULL; -+ DPRINT("alloc_pop()\n"); -+ DUMP(alloc); -+ spin_lock_irq(&alloc->lock); -+ if (!list_empty(&alloc->free)) { -+ i = list_entry(alloc->free.next, struct alloc_node, list); -+ list_del(&i->list); -+ } -+ spin_unlock_irq(&alloc->lock); -+ DPRINT("returning %d\n", i ? 0 : -ENOMEM); -+ DUMP(alloc); -+ if (!i) -+ return -ENOMEM; -+ *result = i->base; -+ *count = i->num; -+ kfree(i); -+ return 0; -+} -+ -+int dpa_alloc_check(struct dpa_alloc *list_head, u32 item) -+{ -+ struct alloc_node *i = NULL; -+ int res = 0; -+ DPRINT("alloc_check()\n"); -+ spin_lock_irq(&list_head->lock); -+ -+ list_for_each_entry(i, &list_head->free, list) { -+ if ((item >= i->base) && (item < (i->base + i->num))) { -+ res = 1; -+ break; -+ } -+ } -+ spin_unlock_irq(&list_head->lock); -+ return res; -+} ---- /dev/null -+++ b/drivers/staging/fsl_qbman/dpa_sys.h -@@ -0,0 +1,259 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef DPA_SYS_H -+#define DPA_SYS_H -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* When copying aligned words or shorts, try to avoid memcpy() */ -+#define CONFIG_TRY_BETTER_MEMCPY -+ -+/* For 2-element tables related to cache-inhibited and cache-enabled mappings */ -+#define DPA_PORTAL_CE 0 -+#define DPA_PORTAL_CI 1 -+ -+/***********************/ -+/* Misc inline assists */ -+/***********************/ -+ -+#if defined CONFIG_PPC32 -+#include "dpa_sys_ppc32.h" -+#elif defined CONFIG_PPC64 -+#include "dpa_sys_ppc64.h" -+#elif defined CONFIG_ARM -+#include "dpa_sys_arm.h" -+#elif defined CONFIG_ARM64 -+#include "dpa_sys_arm64.h" -+#endif -+ -+ -+#ifdef CONFIG_FSL_DPA_CHECKING -+#define DPA_ASSERT(x) \ -+ do { \ -+ if (!(x)) { \ -+ pr_crit("ASSERT: (%s:%d) %s\n", __FILE__, __LINE__, \ -+ __stringify_1(x)); \ -+ dump_stack(); \ -+ panic("assertion failure"); \ -+ } \ -+ } while (0) -+#else -+#define DPA_ASSERT(x) -+#endif -+ -+/* memcpy() stuff - when you know alignments in advance */ -+#ifdef CONFIG_TRY_BETTER_MEMCPY -+static inline void copy_words(void *dest, const void *src, size_t sz) -+{ -+ u32 *__dest = dest; -+ const u32 *__src = src; -+ size_t __sz = sz >> 2; -+ BUG_ON((unsigned long)dest & 0x3); -+ BUG_ON((unsigned long)src & 0x3); -+ BUG_ON(sz & 0x3); -+ while (__sz--) -+ *(__dest++) = *(__src++); -+} -+static inline void copy_shorts(void *dest, const void *src, size_t sz) -+{ -+ u16 *__dest = dest; -+ const u16 *__src = src; -+ size_t __sz = sz >> 1; -+ BUG_ON((unsigned long)dest & 0x1); -+ BUG_ON((unsigned long)src & 0x1); -+ BUG_ON(sz & 0x1); -+ while (__sz--) -+ *(__dest++) = *(__src++); -+} -+static inline void copy_bytes(void *dest, const void *src, size_t sz) -+{ -+ u8 *__dest = dest; -+ const u8 *__src = src; -+ while (sz--) -+ *(__dest++) = *(__src++); -+} -+#else -+#define copy_words memcpy -+#define copy_shorts memcpy -+#define copy_bytes memcpy -+#endif -+ -+/************/ -+/* RB-trees */ -+/************/ -+ -+/* We encapsulate RB-trees so that its easier to use non-linux forms in -+ * non-linux systems. This also encapsulates the extra plumbing that linux code -+ * usually provides when using RB-trees. This encapsulation assumes that the -+ * data type held by the tree is u32. */ -+ -+struct dpa_rbtree { -+ struct rb_root root; -+}; -+#define DPA_RBTREE { .root = RB_ROOT } -+ -+static inline void dpa_rbtree_init(struct dpa_rbtree *tree) -+{ -+ tree->root = RB_ROOT; -+} -+ -+#define IMPLEMENT_DPA_RBTREE(name, type, node_field, val_field) \ -+static inline int name##_push(struct dpa_rbtree *tree, type *obj) \ -+{ \ -+ struct rb_node *parent = NULL, **p = &tree->root.rb_node; \ -+ while (*p) { \ -+ u32 item; \ -+ parent = *p; \ -+ item = rb_entry(parent, type, node_field)->val_field; \ -+ if (obj->val_field < item) \ -+ p = &parent->rb_left; \ -+ else if (obj->val_field > item) \ -+ p = &parent->rb_right; \ -+ else \ -+ return -EBUSY; \ -+ } \ -+ rb_link_node(&obj->node_field, parent, p); \ -+ rb_insert_color(&obj->node_field, &tree->root); \ -+ return 0; \ -+} \ -+static inline void name##_del(struct dpa_rbtree *tree, type *obj) \ -+{ \ -+ rb_erase(&obj->node_field, &tree->root); \ -+} \ -+static inline type *name##_find(struct dpa_rbtree *tree, u32 val) \ -+{ \ -+ type *ret; \ -+ struct rb_node *p = tree->root.rb_node; \ -+ while (p) { \ -+ ret = rb_entry(p, type, node_field); \ -+ if (val < ret->val_field) \ -+ p = p->rb_left; \ -+ else if (val > ret->val_field) \ -+ p = p->rb_right; \ -+ else \ -+ return ret; \ -+ } \ -+ return NULL; \ -+} -+ -+/************/ -+/* Bootargs */ -+/************/ -+ -+/* Qman has "qportals=" and Bman has "bportals=", they use the same syntax -+ * though; a comma-separated list of items, each item being a cpu index and/or a -+ * range of cpu indices, and each item optionally be prefixed by "s" to indicate -+ * that the portal associated with that cpu should be shared. See bman_driver.c -+ * for more specifics. */ -+static int __parse_portals_cpu(const char **s, unsigned int *cpu) -+{ -+ *cpu = 0; -+ if (!isdigit(**s)) -+ return -EINVAL; -+ while (isdigit(**s)) -+ *cpu = *cpu * 10 + (*((*s)++) - '0'); -+ return 0; -+} -+static inline int parse_portals_bootarg(char *str, struct cpumask *want_shared, -+ struct cpumask *want_unshared, -+ const char *argname) -+{ -+ const char *s = str; -+ unsigned int shared, cpu1, cpu2, loop; -+ -+keep_going: -+ if (*s == 's') { -+ shared = 1; -+ s++; -+ } else -+ shared = 0; -+ if (__parse_portals_cpu(&s, &cpu1)) -+ goto err; -+ if (*s == '-') { -+ s++; -+ if (__parse_portals_cpu(&s, &cpu2)) -+ goto err; -+ if (cpu2 < cpu1) -+ goto err; -+ } else -+ cpu2 = cpu1; -+ for (loop = cpu1; loop <= cpu2; loop++) -+ cpumask_set_cpu(loop, shared ? want_shared : want_unshared); -+ if (*s == ',') { -+ s++; -+ goto keep_going; -+ } else if ((*s == '\0') || isspace(*s)) -+ return 0; -+err: -+ pr_crit("Malformed %s argument: %s, offset: %lu\n", argname, str, -+ (unsigned long)s - (unsigned long)str); -+ return -EINVAL; -+} -+ -+/* Hooks from fsl_usdpaa_irq.c to fsl_usdpaa.c */ -+int usdpaa_get_portal_config(struct file *filp, void *cinh, -+ enum usdpaa_portal_type ptype, unsigned int *irq, -+ void **iir_reg); -+ -+#endif /* DPA_SYS_H */ ---- /dev/null -+++ b/drivers/staging/fsl_qbman/dpa_sys_arm.h -@@ -0,0 +1,95 @@ -+/* Copyright 2016 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef DPA_SYS_ARM_H -+#define DPA_SYS_ARM_H -+ -+#include -+#include -+ -+/* Implementation of ARM specific routines */ -+ -+/* TODO: NB, we currently assume that hwsync() and lwsync() imply compiler -+ * barriers and that dcb*() won't fall victim to compiler or execution -+ * reordering with respect to other code/instructions that manipulate the same -+ * cacheline. */ -+#define hwsync() { asm volatile("dmb st" : : : "memory"); } -+#define lwsync() { asm volatile("dmb st" : : : "memory"); } -+#define dcbf(p) { asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r" (p) : "memory"); } -+#define dcbt_ro(p) { asm volatile("pld [%0, #64];": : "r" (p)); } -+#define dcbt_rw(p) { asm volatile("pldw [%0, #64];": : "r" (p)); } -+#define dcbi(p) { asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (p) : "memory"); } -+ -+#define dcbz_64(p) { memset(p, 0, sizeof(*p)); } -+ -+#define dcbf_64(p) \ -+ do { \ -+ dcbf((u32)p); \ -+ } while (0) -+/* Commonly used combo */ -+#define dcbit_ro(p) \ -+ do { \ -+ dcbi((u32)p); \ -+ dcbt_ro((u32)p); \ -+ } while (0) -+ -+static inline u64 mfatb(void) -+{ -+ return get_cycles(); -+} -+ -+static inline u32 in_be32(volatile void *addr) -+{ -+ return be32_to_cpu(*((volatile u32 *) addr)); -+} -+ -+static inline void out_be32(void *addr, u32 val) -+{ -+ *((u32 *) addr) = cpu_to_be32(val); -+} -+ -+ -+static inline void set_bits(unsigned long mask, volatile unsigned long *p) -+{ -+ *p |= mask; -+} -+static inline void clear_bits(unsigned long mask, volatile unsigned long *p) -+{ -+ *p &= ~mask; -+} -+ -+static inline void flush_dcache_range(unsigned long start, unsigned long stop) -+{ -+ __cpuc_flush_dcache_area((void *) start, stop - start); -+} -+ -+#define hard_smp_processor_id() raw_smp_processor_id() -+#endif ---- /dev/null -+++ b/drivers/staging/fsl_qbman/dpa_sys_arm64.h -@@ -0,0 +1,102 @@ -+/* Copyright 2014 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef DPA_SYS_ARM64_H -+#define DPA_SYS_ARM64_H -+ -+#include -+#include -+ -+/* Implementation of ARM 64 bit specific routines */ -+ -+/* TODO: NB, we currently assume that hwsync() and lwsync() imply compiler -+ * barriers and that dcb*() won't fall victim to compiler or execution -+ * reordering with respect to other code/instructions that manipulate the same -+ * cacheline. */ -+#define hwsync() { asm volatile("dmb st" : : : "memory"); } -+#define lwsync() { asm volatile("dmb st" : : : "memory"); } -+#define dcbf(p) { asm volatile("dc cvac, %0;" : : "r" (p) : "memory"); } -+#define dcbt_ro(p) { asm volatile("prfm pldl1keep, [%0, #64]" : : "r" (p)); } -+#define dcbt_rw(p) { asm volatile("prfm pldl1keep, [%0, #64]" : : "r" (p)); } -+#define dcbi(p) { asm volatile("dc ivac, %0" : : "r"(p) : "memory"); } -+#define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); } -+ -+#define dcbz_64(p) \ -+ do { \ -+ dcbz(p); \ -+ } while (0) -+ -+#define dcbf_64(p) \ -+ do { \ -+ dcbf(p); \ -+ } while (0) -+/* Commonly used combo */ -+#define dcbit_ro(p) \ -+ do { \ -+ dcbi(p); \ -+ dcbt_ro(p); \ -+ } while (0) -+ -+static inline u64 mfatb(void) -+{ -+ return get_cycles(); -+} -+ -+static inline u32 in_be32(volatile void *addr) -+{ -+ return be32_to_cpu(*((volatile u32 *) addr)); -+} -+ -+static inline void out_be32(void *addr, u32 val) -+{ -+ *((u32 *) addr) = cpu_to_be32(val); -+} -+ -+ -+static inline void set_bits(unsigned long mask, volatile unsigned long *p) -+{ -+ *p |= mask; -+} -+static inline void clear_bits(unsigned long mask, volatile unsigned long *p) -+{ -+ *p &= ~mask; -+} -+ -+static inline void flush_dcache_range(unsigned long start, unsigned long stop) -+{ -+ __flush_dcache_area((void *) start, stop - start); -+} -+ -+#define hard_smp_processor_id() raw_smp_processor_id() -+ -+ -+ -+#endif ---- /dev/null -+++ b/drivers/staging/fsl_qbman/dpa_sys_ppc32.h -@@ -0,0 +1,70 @@ -+/* Copyright 2014 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef DPA_SYS_PPC32_H -+#define DPA_SYS_PPC32_H -+ -+/* Implementation of PowerPC 32 bit specific routines */ -+ -+/* TODO: NB, we currently assume that hwsync() and lwsync() imply compiler -+ * barriers and that dcb*() won't fall victim to compiler or execution -+ * reordering with respect to other code/instructions that manipulate the same -+ * cacheline. */ -+#define hwsync() __asm__ __volatile__ ("sync" : : : "memory") -+#define lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : : "memory") -+#define dcbf(p) __asm__ __volatile__ ("dcbf 0,%0" : : "r" (p) : "memory") -+#define dcbt_ro(p) __asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)) -+#define dcbt_rw(p) __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (p)) -+#define dcbi(p) dcbf(p) -+ -+#define dcbzl(p) __asm__ __volatile__ ("dcbzl 0,%0" : : "r" (p)) -+#define dcbz_64(p) dcbzl(p) -+#define dcbf_64(p) dcbf(p) -+ -+/* Commonly used combo */ -+#define dcbit_ro(p) \ -+ do { \ -+ dcbi(p); \ -+ dcbt_ro(p); \ -+ } while (0) -+ -+static inline u64 mfatb(void) -+{ -+ u32 hi, lo, chk; -+ do { -+ hi = mfspr(SPRN_ATBU); -+ lo = mfspr(SPRN_ATBL); -+ chk = mfspr(SPRN_ATBU); -+ } while (unlikely(hi != chk)); -+ return ((u64)hi << 32) | (u64)lo; -+} -+ -+#endif ---- /dev/null -+++ b/drivers/staging/fsl_qbman/dpa_sys_ppc64.h -@@ -0,0 +1,79 @@ -+/* Copyright 2014 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef DPA_SYS_PPC64_H -+#define DPA_SYS_PPC64_H -+ -+/* Implementation of PowerPC 64 bit specific routines */ -+ -+/* TODO: NB, we currently assume that hwsync() and lwsync() imply compiler -+ * barriers and that dcb*() won't fall victim to compiler or execution -+ * reordering with respect to other code/instructions that manipulate the same -+ * cacheline. */ -+#define hwsync() __asm__ __volatile__ ("sync" : : : "memory") -+#define lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : : "memory") -+#define dcbf(p) __asm__ __volatile__ ("dcbf 0,%0" : : "r" (p) : "memory") -+#define dcbt_ro(p) __asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)) -+#define dcbt_rw(p) __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (p)) -+#define dcbi(p) dcbf(p) -+ -+#define dcbz(p) __asm__ __volatile__ ("dcbz 0,%0" : : "r" (p)) -+#define dcbz_64(p) \ -+ do { \ -+ dcbz((void*)p + 32); \ -+ dcbz(p); \ -+ } while (0) -+#define dcbf_64(p) \ -+ do { \ -+ dcbf((void*)p + 32); \ -+ dcbf(p); \ -+ } while (0) -+/* Commonly used combo */ -+#define dcbit_ro(p) \ -+ do { \ -+ dcbi(p); \ -+ dcbi((void*)p + 32); \ -+ dcbt_ro(p); \ -+ dcbt_ro((void*)p + 32); \ -+ } while (0) -+ -+static inline u64 mfatb(void) -+{ -+ u32 hi, lo, chk; -+ do { -+ hi = mfspr(SPRN_ATBU); -+ lo = mfspr(SPRN_ATBL); -+ chk = mfspr(SPRN_ATBU); -+ } while (unlikely(hi != chk)); -+ return ((u64)hi << 32) | (u64)lo; -+} -+ -+#endif ---- /dev/null -+++ b/drivers/staging/fsl_qbman/fsl_usdpaa.c -@@ -0,0 +1,1982 @@ -+/* Copyright (C) 2008-2012 Freescale Semiconductor, Inc. -+ * Authors: Andy Fleming -+ * Timur Tabi -+ * Geoff Thorpe -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ -+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#if !(defined(CONFIG_ARM) || defined(CONFIG_ARM64)) -+#include -+#endif -+ -+#include "dpa_sys.h" -+#include -+#include "bman_low.h" -+#include "qman_low.h" -+ -+/* Physical address range of the memory reservation, exported for mm/mem.c */ -+static u64 phys_start; -+static u64 phys_size; -+static u64 arg_phys_size; -+ -+/* PFN versions of the above */ -+static unsigned long pfn_start; -+static unsigned long pfn_size; -+ -+/* Memory reservations are manipulated under this spinlock (which is why 'refs' -+ * isn't atomic_t). */ -+static DEFINE_SPINLOCK(mem_lock); -+ -+/* The range of TLB1 indices */ -+static unsigned int first_tlb; -+static unsigned int num_tlb = 1; -+static unsigned int current_tlb; /* loops around for fault handling */ -+ -+/* Memory reservation is represented as a list of 'mem_fragment's, some of which -+ * may be mapped. Unmapped fragments are always merged where possible. */ -+static LIST_HEAD(mem_list); -+ -+struct mem_mapping; -+ -+/* Memory fragments are in 'mem_list'. */ -+struct mem_fragment { -+ u64 base; -+ u64 len; -+ unsigned long pfn_base; /* PFN version of 'base' */ -+ unsigned long pfn_len; /* PFN version of 'len' */ -+ unsigned int refs; /* zero if unmapped */ -+ u64 root_len; /* Size of the orignal fragment */ -+ unsigned long root_pfn; /* PFN of the orignal fragment */ -+ struct list_head list; -+ /* if mapped, flags+name captured at creation time */ -+ u32 flags; -+ char name[USDPAA_DMA_NAME_MAX]; -+ u64 map_len; -+ /* support multi-process locks per-memory-fragment. */ -+ int has_locking; -+ wait_queue_head_t wq; -+ struct mem_mapping *owner; -+}; -+ -+/* Mappings of memory fragments in 'struct ctx'. These are created from -+ * ioctl(USDPAA_IOCTL_DMA_MAP), though the actual mapping then happens via a -+ * mmap(). */ -+struct mem_mapping { -+ struct mem_fragment *root_frag; -+ u32 frag_count; -+ u64 total_size; -+ struct list_head list; -+ int refs; -+ void *virt_addr; -+}; -+ -+struct portal_mapping { -+ struct usdpaa_ioctl_portal_map user; -+ union { -+ struct qm_portal_config *qportal; -+ struct bm_portal_config *bportal; -+ }; -+ /* Declare space for the portals in case the process -+ exits unexpectedly and needs to be cleaned by the kernel */ -+ union { -+ struct qm_portal qman_portal_low; -+ struct bm_portal bman_portal_low; -+ }; -+ struct list_head list; -+ struct resource *phys; -+ struct iommu_domain *iommu_domain; -+}; -+ -+/* Track the DPAA resources the process is using */ -+struct active_resource { -+ struct list_head list; -+ u32 id; -+ u32 num; -+ unsigned int refcount; -+}; -+ -+/* Per-FD state (which should also be per-process but we don't enforce that) */ -+struct ctx { -+ /* Lock to protect the context */ -+ spinlock_t lock; -+ /* Allocated resources get put here for accounting */ -+ struct list_head resources[usdpaa_id_max]; -+ /* list of DMA maps */ -+ struct list_head maps; -+ /* list of portal maps */ -+ struct list_head portals; -+}; -+ -+/* Different resource classes */ -+static const struct alloc_backend { -+ enum usdpaa_id_type id_type; -+ int (*alloc)(u32 *, u32, u32, int); -+ void (*release)(u32 base, unsigned int count); -+ int (*reserve)(u32 base, unsigned int count); -+ const char *acronym; -+} alloc_backends[] = { -+ { -+ .id_type = usdpaa_id_fqid, -+ .alloc = qman_alloc_fqid_range, -+ .release = qman_release_fqid_range, -+ .reserve = qman_reserve_fqid_range, -+ .acronym = "FQID" -+ }, -+ { -+ .id_type = usdpaa_id_bpid, -+ .alloc = bman_alloc_bpid_range, -+ .release = bman_release_bpid_range, -+ .reserve = bman_reserve_bpid_range, -+ .acronym = "BPID" -+ }, -+ { -+ .id_type = usdpaa_id_qpool, -+ .alloc = qman_alloc_pool_range, -+ .release = qman_release_pool_range, -+ .reserve = qman_reserve_pool_range, -+ .acronym = "QPOOL" -+ }, -+ { -+ .id_type = usdpaa_id_cgrid, -+ .alloc = qman_alloc_cgrid_range, -+ .release = qman_release_cgrid_range, -+ .acronym = "CGRID" -+ }, -+ { -+ .id_type = usdpaa_id_ceetm0_lfqid, -+ .alloc = qman_alloc_ceetm0_lfqid_range, -+ .release = qman_release_ceetm0_lfqid_range, -+ .acronym = "CEETM0_LFQID" -+ }, -+ { -+ .id_type = usdpaa_id_ceetm0_channelid, -+ .alloc = qman_alloc_ceetm0_channel_range, -+ .release = qman_release_ceetm0_channel_range, -+ .acronym = "CEETM0_LFQID" -+ }, -+ { -+ .id_type = usdpaa_id_ceetm1_lfqid, -+ .alloc = qman_alloc_ceetm1_lfqid_range, -+ .release = qman_release_ceetm1_lfqid_range, -+ .acronym = "CEETM1_LFQID" -+ }, -+ { -+ .id_type = usdpaa_id_ceetm1_channelid, -+ .alloc = qman_alloc_ceetm1_channel_range, -+ .release = qman_release_ceetm1_channel_range, -+ .acronym = "CEETM1_LFQID" -+ }, -+ { -+ /* This terminates the array */ -+ .id_type = usdpaa_id_max -+ } -+}; -+ -+/* Determines the largest acceptable page size for a given size -+ The sizes are determined by what the TLB1 acceptable page sizes are */ -+static u32 largest_page_size(u32 size) -+{ -+ int shift = 30; /* Start at 1G size */ -+ if (size < 4096) -+ return 0; -+ do { -+ if (size >= (1<= 12); /* Up to 4k */ -+ return 0; -+} -+ -+/* Determine if value is power of 4 */ -+static inline bool is_power_of_4(u64 x) -+{ -+ if (x == 0 || ((x & (x - 1)) != 0)) -+ return false; -+ return !!(x & 0x5555555555555555ull); -+} -+ -+/* Helper for ioctl_dma_map() when we have a larger fragment than we need. This -+ * splits the fragment into 4 and returns the upper-most. (The caller can loop -+ * until it has a suitable fragment size.) */ -+static struct mem_fragment *split_frag(struct mem_fragment *frag) -+{ -+ struct mem_fragment *x[3]; -+ -+ x[0] = kmalloc(sizeof(struct mem_fragment), GFP_ATOMIC); -+ x[1] = kmalloc(sizeof(struct mem_fragment), GFP_ATOMIC); -+ x[2] = kmalloc(sizeof(struct mem_fragment), GFP_ATOMIC); -+ if (!x[0] || !x[1] || !x[2]) { -+ kfree(x[0]); -+ kfree(x[1]); -+ kfree(x[2]); -+ return NULL; -+ } -+ BUG_ON(frag->refs); -+ frag->len >>= 2; -+ frag->pfn_len >>= 2; -+ x[0]->base = frag->base + frag->len; -+ x[1]->base = x[0]->base + frag->len; -+ x[2]->base = x[1]->base + frag->len; -+ x[0]->len = x[1]->len = x[2]->len = frag->len; -+ x[0]->pfn_base = frag->pfn_base + frag->pfn_len; -+ x[1]->pfn_base = x[0]->pfn_base + frag->pfn_len; -+ x[2]->pfn_base = x[1]->pfn_base + frag->pfn_len; -+ x[0]->pfn_len = x[1]->pfn_len = x[2]->pfn_len = frag->pfn_len; -+ x[0]->refs = x[1]->refs = x[2]->refs = 0; -+ x[0]->root_len = x[1]->root_len = x[2]->root_len = frag->root_len; -+ x[0]->root_pfn = x[1]->root_pfn = x[2]->root_pfn = frag->root_pfn; -+ x[0]->name[0] = x[1]->name[0] = x[2]->name[0] = 0; -+ list_add_tail(&x[0]->list, &frag->list); -+ list_add_tail(&x[1]->list, &x[0]->list); -+ list_add_tail(&x[2]->list, &x[1]->list); -+ return x[2]; -+} -+ -+static __maybe_unused void dump_frags(void) -+{ -+ struct mem_fragment *frag; -+ int i = 0; -+ list_for_each_entry(frag, &mem_list, list) { -+ pr_info("FRAG %d: base 0x%llx pfn_base 0x%lx len 0x%llx root_len 0x%llx root_pfn 0x%lx refs %d name %s\n", -+ i, frag->base, frag->pfn_base, -+ frag->len, frag->root_len, frag->root_pfn, -+ frag->refs, frag->name); -+ ++i; -+ } -+} -+ -+/* Walk the list of fragments and adjoin neighbouring segments if possible */ -+static void compress_frags(void) -+{ -+ /* Walk the fragment list and combine fragments */ -+ struct mem_fragment *frag, *nxtfrag; -+ u64 len = 0; -+ -+ int i, numfrags; -+ -+ -+ frag = list_entry(mem_list.next, struct mem_fragment, list); -+ -+ while (&frag->list != &mem_list) { -+ /* Must combine consecutive fragemenst with -+ same root_pfn such that they are power of 4 */ -+ if (frag->refs != 0) { -+ frag = list_entry(frag->list.next, -+ struct mem_fragment, list); -+ continue; /* Not this window */ -+ } -+ len = frag->len; -+ numfrags = 0; -+ nxtfrag = list_entry(frag->list.next, -+ struct mem_fragment, list); -+ while (true) { -+ if (&nxtfrag->list == &mem_list) { -+ numfrags = 0; -+ break; /* End of list */ -+ } -+ if (nxtfrag->refs) { -+ numfrags = 0; -+ break; /* In use still */ -+ } -+ if (nxtfrag->root_pfn != frag->root_pfn) { -+ numfrags = 0; -+ break; /* Crosses root fragment boundary */ -+ } -+ len += nxtfrag->len; -+ numfrags++; -+ if (is_power_of_4(len)) { -+ /* These fragments can be combined */ -+ break; -+ } -+ nxtfrag = list_entry(nxtfrag->list.next, -+ struct mem_fragment, list); -+ } -+ if (numfrags == 0) { -+ frag = list_entry(frag->list.next, -+ struct mem_fragment, list); -+ continue; /* try the next window */ -+ } -+ for (i = 0; i < numfrags; i++) { -+ struct mem_fragment *todel = -+ list_entry(nxtfrag->list.prev, -+ struct mem_fragment, list); -+ nxtfrag->len += todel->len; -+ nxtfrag->pfn_len += todel->pfn_len; -+ list_del(&todel->list); -+ } -+ /* Re evaluate the list, things may merge now */ -+ frag = list_entry(mem_list.next, struct mem_fragment, list); -+ } -+} -+ -+/* Hook from arch/powerpc/mm/mem.c */ -+int usdpaa_test_fault(unsigned long pfn, u64 *phys_addr, u64 *size) -+{ -+ struct mem_fragment *frag; -+ int idx = -1; -+ if ((pfn < pfn_start) || (pfn >= (pfn_start + pfn_size))) -+ return -1; -+ /* It's in-range, we need to find the fragment */ -+ spin_lock(&mem_lock); -+ list_for_each_entry(frag, &mem_list, list) { -+ if ((pfn >= frag->pfn_base) && (pfn < (frag->pfn_base + -+ frag->pfn_len))) { -+ *phys_addr = frag->base; -+ *size = frag->len; -+ idx = current_tlb++; -+ if (current_tlb >= (first_tlb + num_tlb)) -+ current_tlb = first_tlb; -+ break; -+ } -+ } -+ spin_unlock(&mem_lock); -+ return idx; -+} -+ -+static int usdpaa_open(struct inode *inode, struct file *filp) -+{ -+ const struct alloc_backend *backend = &alloc_backends[0]; -+ struct ctx *ctx = kmalloc(sizeof(struct ctx), GFP_KERNEL); -+ if (!ctx) -+ return -ENOMEM; -+ filp->private_data = ctx; -+ -+ while (backend->id_type != usdpaa_id_max) { -+ INIT_LIST_HEAD(&ctx->resources[backend->id_type]); -+ backend++; -+ } -+ -+ INIT_LIST_HEAD(&ctx->maps); -+ INIT_LIST_HEAD(&ctx->portals); -+ spin_lock_init(&ctx->lock); -+ -+ //filp->f_mapping->backing_dev_info = &directly_mappable_cdev_bdi; -+ -+ return 0; -+} -+ -+#define DQRR_MAXFILL 15 -+ -+/* Reset a QMan portal to its default state */ -+static int init_qm_portal(struct qm_portal_config *config, -+ struct qm_portal *portal) -+{ -+ const struct qm_dqrr_entry *dqrr = NULL; -+ int i; -+ -+ portal->addr.addr_ce = config->addr_virt[DPA_PORTAL_CE]; -+ portal->addr.addr_ci = config->addr_virt[DPA_PORTAL_CI]; -+ -+ /* Make sure interrupts are inhibited */ -+ qm_out(IIR, 1); -+ -+ /* Initialize the DQRR. This will stop any dequeue -+ commands that are in progress */ -+ if (qm_dqrr_init(portal, config, qm_dqrr_dpush, qm_dqrr_pvb, -+ qm_dqrr_cdc, DQRR_MAXFILL)) { -+ pr_err("qm_dqrr_init() failed when trying to" -+ " recover portal, portal will be leaked\n"); -+ return 1; -+ } -+ -+ /* Discard any entries on the DQRR */ -+ /* If we consume the ring twice something is wrong */ -+ for (i = 0; i < DQRR_MAXFILL * 2; i++) { -+ qm_dqrr_pvb_update(portal); -+ dqrr = qm_dqrr_current(portal); -+ if (!dqrr) -+ break; -+ qm_dqrr_cdc_consume_1ptr(portal, dqrr, 0); -+ qm_dqrr_pvb_update(portal); -+ qm_dqrr_next(portal); -+ } -+ /* Initialize the EQCR */ -+ if (qm_eqcr_init(portal, qm_eqcr_pvb, -+ qm_eqcr_get_ci_stashing(portal), 1)) { -+ pr_err("Qman EQCR initialisation failed\n"); -+ return 1; -+ } -+ /* initialize the MR */ -+ if (qm_mr_init(portal, qm_mr_pvb, qm_mr_cci)) { -+ pr_err("Qman MR initialisation failed\n"); -+ return 1; -+ } -+ qm_mr_pvb_update(portal); -+ while (qm_mr_current(portal)) { -+ qm_mr_next(portal); -+ qm_mr_cci_consume_to_current(portal); -+ qm_mr_pvb_update(portal); -+ } -+ -+ if (qm_mc_init(portal)) { -+ pr_err("Qman MC initialisation failed\n"); -+ return 1; -+ } -+ return 0; -+} -+ -+static int init_bm_portal(struct bm_portal_config *config, -+ struct bm_portal *portal) -+{ -+ portal->addr.addr_ce = config->addr_virt[DPA_PORTAL_CE]; -+ portal->addr.addr_ci = config->addr_virt[DPA_PORTAL_CI]; -+ -+ if (bm_rcr_init(portal, bm_rcr_pvb, bm_rcr_cce)) { -+ pr_err("Bman RCR initialisation failed\n"); -+ return 1; -+ } -+ if (bm_mc_init(portal)) { -+ pr_err("Bman MC initialisation failed\n"); -+ return 1; -+ } -+ return 0; -+} -+ -+/* Function that will scan all FQ's in the system. For each FQ that is not -+ OOS it will call the check_channel helper to determine if the FQ should -+ be torn down. If the check_channel helper returns true the FQ will be -+ transitioned to the OOS state */ -+static int qm_check_and_destroy_fqs(struct qm_portal *portal, void *ctx, -+ bool (*check_channel)(void*, u32)) -+{ -+ u32 fq_id = 0; -+ while (1) { -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ u8 state; -+ u32 channel; -+ -+ /* Determine the channel for the FQID */ -+ mcc = qm_mc_start(portal); -+ mcc->queryfq.fqid = fq_id; -+ qm_mc_commit(portal, QM_MCC_VERB_QUERYFQ); -+ while (!(mcr = qm_mc_result(portal))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) -+ == QM_MCR_VERB_QUERYFQ); -+ if (mcr->result != QM_MCR_RESULT_OK) -+ break; /* End of valid FQIDs */ -+ -+ channel = mcr->queryfq.fqd.dest.channel; -+ /* Determine the state of the FQID */ -+ mcc = qm_mc_start(portal); -+ mcc->queryfq_np.fqid = fq_id; -+ qm_mc_commit(portal, QM_MCC_VERB_QUERYFQ_NP); -+ while (!(mcr = qm_mc_result(portal))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) -+ == QM_MCR_VERB_QUERYFQ_NP); -+ state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK; -+ if (state == QM_MCR_NP_STATE_OOS) -+ /* Already OOS, no need to do anymore checks */ -+ goto next; -+ -+ if (check_channel(ctx, channel)) -+ qm_shutdown_fq(&portal, 1, fq_id); -+ next: -+ ++fq_id; -+ } -+ return 0; -+} -+ -+static bool check_channel_device(void *_ctx, u32 channel) -+{ -+ struct ctx *ctx = _ctx; -+ struct portal_mapping *portal, *tmpportal; -+ struct active_resource *res; -+ -+ /* See if the FQ is destined for one of the portals we're cleaning up */ -+ list_for_each_entry_safe(portal, tmpportal, &ctx->portals, list) { -+ if (portal->user.type == usdpaa_portal_qman) { -+ if (portal->qportal->public_cfg.channel == channel) { -+ /* This FQs destination is a portal -+ we're cleaning, send a retire */ -+ return true; -+ } -+ } -+ } -+ -+ /* Check the pool channels that will be released as well */ -+ list_for_each_entry(res, &ctx->resources[usdpaa_id_qpool], list) { -+ if ((res->id >= channel) && -+ ((res->id + res->num - 1) <= channel)) -+ return true; -+ } -+ return false; -+} -+ -+static bool check_portal_channel(void *ctx, u32 channel) -+{ -+ u32 portal_channel = *(u32 *)ctx; -+ if (portal_channel == channel) { -+ /* This FQs destination is a portal -+ we're cleaning, send a retire */ -+ return true; -+ } -+ return false; -+} -+ -+ -+ -+ -+static int usdpaa_release(struct inode *inode, struct file *filp) -+{ -+ struct ctx *ctx = filp->private_data; -+ struct mem_mapping *map, *tmpmap; -+ struct portal_mapping *portal, *tmpportal; -+ const struct alloc_backend *backend = &alloc_backends[0]; -+ struct active_resource *res; -+ struct qm_portal *qm_cleanup_portal = NULL; -+ struct bm_portal *bm_cleanup_portal = NULL; -+ struct qm_portal_config *qm_alloced_portal = NULL; -+ struct bm_portal_config *bm_alloced_portal = NULL; -+ -+ struct qm_portal *portal_array[qman_portal_max]; -+ int portal_count = 0; -+ -+ /* Ensure the release operation cannot be migrated to another -+ CPU as CPU specific variables may be needed during cleanup */ -+#ifdef CONFIG_PREEMPT_RT_FULL -+ migrate_disable(); -+#endif -+ /* The following logic is used to recover resources that were not -+ correctly released by the process that is closing the FD. -+ Step 1: syncronize the HW with the qm_portal/bm_portal structures -+ in the kernel -+ */ -+ -+ list_for_each_entry_safe(portal, tmpportal, &ctx->portals, list) { -+ /* Try to recover any portals that weren't shut down */ -+ if (portal->user.type == usdpaa_portal_qman) { -+ portal_array[portal_count] = &portal->qman_portal_low; -+ ++portal_count; -+ init_qm_portal(portal->qportal, -+ &portal->qman_portal_low); -+ if (!qm_cleanup_portal) { -+ qm_cleanup_portal = &portal->qman_portal_low; -+ } else { -+ /* Clean FQs on the dedicated channel */ -+ u32 chan = portal->qportal->public_cfg.channel; -+ qm_check_and_destroy_fqs( -+ &portal->qman_portal_low, &chan, -+ check_portal_channel); -+ } -+ } else { -+ /* BMAN */ -+ init_bm_portal(portal->bportal, -+ &portal->bman_portal_low); -+ if (!bm_cleanup_portal) -+ bm_cleanup_portal = &portal->bman_portal_low; -+ } -+ } -+ /* If no portal was found, allocate one for cleanup */ -+ if (!qm_cleanup_portal) { -+ qm_alloced_portal = qm_get_unused_portal(); -+ if (!qm_alloced_portal) { -+ pr_crit("No QMan portal avalaible for cleanup\n"); -+#ifdef CONFIG_PREEMPT_RT_FULL -+ migrate_enable(); -+#endif -+ return -1; -+ } -+ qm_cleanup_portal = kmalloc(sizeof(struct qm_portal), -+ GFP_KERNEL); -+ if (!qm_cleanup_portal) { -+#ifdef CONFIG_PREEMPT_RT_FULL -+ migrate_enable(); -+#endif -+ return -ENOMEM; -+ } -+ init_qm_portal(qm_alloced_portal, qm_cleanup_portal); -+ portal_array[portal_count] = qm_cleanup_portal; -+ ++portal_count; -+ } -+ if (!bm_cleanup_portal) { -+ bm_alloced_portal = bm_get_unused_portal(); -+ if (!bm_alloced_portal) { -+ pr_crit("No BMan portal avalaible for cleanup\n"); -+#ifdef CONFIG_PREEMPT_RT_FULL -+ migrate_enable(); -+#endif -+ return -1; -+ } -+ bm_cleanup_portal = kmalloc(sizeof(struct bm_portal), -+ GFP_KERNEL); -+ if (!bm_cleanup_portal) { -+#ifdef CONFIG_PREEMPT_RT_FULL -+ migrate_enable(); -+#endif -+ return -ENOMEM; -+ } -+ init_bm_portal(bm_alloced_portal, bm_cleanup_portal); -+ } -+ -+ /* OOS the FQs associated with this process */ -+ qm_check_and_destroy_fqs(qm_cleanup_portal, ctx, check_channel_device); -+ -+ while (backend->id_type != usdpaa_id_max) { -+ int leaks = 0; -+ list_for_each_entry(res, &ctx->resources[backend->id_type], -+ list) { -+ if (backend->id_type == usdpaa_id_fqid) { -+ int i = 0; -+ for (; i < res->num; i++) { -+ /* Clean FQs with the cleanup portal */ -+ qm_shutdown_fq(portal_array, -+ portal_count, -+ res->id + i); -+ } -+ } -+ leaks += res->num; -+ backend->release(res->id, res->num); -+ } -+ if (leaks) -+ pr_crit("USDPAA process leaking %d %s%s\n", leaks, -+ backend->acronym, (leaks > 1) ? "s" : ""); -+ backend++; -+ } -+ /* Release any DMA regions */ -+ spin_lock(&mem_lock); -+ list_for_each_entry_safe(map, tmpmap, &ctx->maps, list) { -+ struct mem_fragment *current_frag = map->root_frag; -+ int i; -+ if (map->root_frag->has_locking && -+ (map->root_frag->owner == map)) { -+ map->root_frag->owner = NULL; -+ wake_up(&map->root_frag->wq); -+ } -+ /* Check each fragment and merge if the ref count is 0 */ -+ for (i = 0; i < map->frag_count; i++) { -+ --current_frag->refs; -+ current_frag = list_entry(current_frag->list.prev, -+ struct mem_fragment, list); -+ } -+ -+ compress_frags(); -+ list_del(&map->list); -+ kfree(map); -+ } -+ spin_unlock(&mem_lock); -+ -+ /* Return portals */ -+ list_for_each_entry_safe(portal, tmpportal, &ctx->portals, list) { -+ if (portal->user.type == usdpaa_portal_qman) { -+ /* Give the portal back to the allocator */ -+ init_qm_portal(portal->qportal, -+ &portal->qman_portal_low); -+ qm_put_unused_portal(portal->qportal); -+ } else { -+ init_bm_portal(portal->bportal, -+ &portal->bman_portal_low); -+ bm_put_unused_portal(portal->bportal); -+ } -+ list_del(&portal->list); -+ kfree(portal); -+ } -+ if (qm_alloced_portal) { -+ qm_put_unused_portal(qm_alloced_portal); -+ kfree(qm_cleanup_portal); -+ } -+ if (bm_alloced_portal) { -+ bm_put_unused_portal(bm_alloced_portal); -+ kfree(bm_cleanup_portal); -+ } -+ -+ kfree(ctx); -+#ifdef CONFIG_PREEMPT_RT_FULL -+ migrate_enable(); -+#endif -+ return 0; -+} -+ -+static int check_mmap_dma(struct ctx *ctx, struct vm_area_struct *vma, -+ int *match, unsigned long *pfn) -+{ -+ struct mem_mapping *map; -+ -+ list_for_each_entry(map, &ctx->maps, list) { -+ int i; -+ struct mem_fragment *frag = map->root_frag; -+ -+ for (i = 0; i < map->frag_count; i++) { -+ if (frag->pfn_base == vma->vm_pgoff) { -+ *match = 1; -+ *pfn = frag->pfn_base; -+ return 0; -+ } -+ frag = list_entry(frag->list.next, struct mem_fragment, -+ list); -+ } -+ } -+ *match = 0; -+ return 0; -+} -+ -+static int check_mmap_resource(struct resource *res, struct vm_area_struct *vma, -+ int *match, unsigned long *pfn) -+{ -+ *pfn = res->start >> PAGE_SHIFT; -+ if (*pfn == vma->vm_pgoff) { -+ *match = 1; -+ if ((vma->vm_end - vma->vm_start) != resource_size(res)) -+ return -EINVAL; -+ } else -+ *match = 0; -+ return 0; -+} -+ -+static int check_mmap_portal(struct ctx *ctx, struct vm_area_struct *vma, -+ int *match, unsigned long *pfn) -+{ -+ struct portal_mapping *portal; -+ int ret; -+ -+ list_for_each_entry(portal, &ctx->portals, list) { -+ ret = check_mmap_resource(&portal->phys[DPA_PORTAL_CE], vma, -+ match, pfn); -+ if (*match) { -+ vma->vm_page_prot = -+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) -+ pgprot_cached_ns(vma->vm_page_prot); -+#else -+ pgprot_cached_noncoherent(vma->vm_page_prot); -+#endif -+ return ret; -+ } -+ ret = check_mmap_resource(&portal->phys[DPA_PORTAL_CI], vma, -+ match, pfn); -+ if (*match) { -+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); -+ return ret; -+ } -+ } -+ *match = 0; -+ return 0; -+} -+ -+static int usdpaa_mmap(struct file *filp, struct vm_area_struct *vma) -+{ -+ struct ctx *ctx = filp->private_data; -+ unsigned long pfn = 0; -+ int match, ret; -+ -+ spin_lock(&mem_lock); -+ ret = check_mmap_dma(ctx, vma, &match, &pfn); -+ if (!match) -+ ret = check_mmap_portal(ctx, vma, &match, &pfn); -+ spin_unlock(&mem_lock); -+ if (!match) -+ return -EINVAL; -+ if (!ret) -+ ret = remap_pfn_range(vma, vma->vm_start, pfn, -+ vma->vm_end - vma->vm_start, -+ vma->vm_page_prot); -+ return ret; -+} -+ -+/* Return the nearest rounded-up address >= 'addr' that is 'sz'-aligned. 'sz' -+ * must be a power of 2, but both 'addr' and 'sz' can be expressions. */ -+#define USDPAA_MEM_ROUNDUP(addr, sz) \ -+ ({ \ -+ unsigned long foo_align = (sz) - 1; \ -+ ((addr) + foo_align) & ~foo_align; \ -+ }) -+/* Searching for a size-aligned virtual address range starting from 'addr' */ -+static unsigned long usdpaa_get_unmapped_area(struct file *file, -+ unsigned long addr, -+ unsigned long len, -+ unsigned long pgoff, -+ unsigned long flags) -+{ -+ struct vm_area_struct *vma; -+ -+ if (len % PAGE_SIZE) -+ return -EINVAL; -+ if (!len) -+ return -EINVAL; -+ -+ /* Need to align the address to the largest pagesize of the mapping -+ * because the MMU requires the virtual address to have the same -+ * alignment as the physical address */ -+ addr = USDPAA_MEM_ROUNDUP(addr, largest_page_size(len)); -+ vma = find_vma(current->mm, addr); -+ /* Keep searching until we reach the end of currently-used virtual -+ * address-space or we find a big enough gap. */ -+ while (vma) { -+ if ((addr + len) < vma->vm_start) -+ return addr; -+ -+ addr = USDPAA_MEM_ROUNDUP(vma->vm_end, largest_page_size(len)); -+ vma = vma->vm_next; -+ } -+ if ((TASK_SIZE - len) < addr) -+ return -ENOMEM; -+ return addr; -+} -+ -+static long ioctl_id_alloc(struct ctx *ctx, void __user *arg) -+{ -+ struct usdpaa_ioctl_id_alloc i; -+ const struct alloc_backend *backend; -+ struct active_resource *res; -+ int ret = copy_from_user(&i, arg, sizeof(i)); -+ if (ret) -+ return ret; -+ if ((i.id_type >= usdpaa_id_max) || !i.num) -+ return -EINVAL; -+ backend = &alloc_backends[i.id_type]; -+ /* Allocate the required resource type */ -+ ret = backend->alloc(&i.base, i.num, i.align, i.partial); -+ if (ret < 0) -+ return ret; -+ i.num = ret; -+ /* Copy the result to user-space */ -+ ret = copy_to_user(arg, &i, sizeof(i)); -+ if (ret) { -+ backend->release(i.base, i.num); -+ return ret; -+ } -+ /* Assign the allocated range to the FD accounting */ -+ res = kmalloc(sizeof(*res), GFP_KERNEL); -+ if (!res) { -+ backend->release(i.base, i.num); -+ return -ENOMEM; -+ } -+ spin_lock(&ctx->lock); -+ res->id = i.base; -+ res->num = i.num; -+ res->refcount = 1; -+ list_add(&res->list, &ctx->resources[i.id_type]); -+ spin_unlock(&ctx->lock); -+ return 0; -+} -+ -+static long ioctl_id_release(struct ctx *ctx, void __user *arg) -+{ -+ struct usdpaa_ioctl_id_release i; -+ const struct alloc_backend *backend; -+ struct active_resource *tmp, *pos; -+ -+ int ret = copy_from_user(&i, arg, sizeof(i)); -+ if (ret) -+ return ret; -+ if ((i.id_type >= usdpaa_id_max) || !i.num) -+ return -EINVAL; -+ backend = &alloc_backends[i.id_type]; -+ /* Pull the range out of the FD accounting - the range is valid iff this -+ * succeeds. */ -+ spin_lock(&ctx->lock); -+ list_for_each_entry_safe(pos, tmp, &ctx->resources[i.id_type], list) { -+ if (pos->id == i.base && pos->num == i.num) { -+ pos->refcount--; -+ if (pos->refcount) { -+ spin_unlock(&ctx->lock); -+ return 0; /* Still being used */ -+ } -+ list_del(&pos->list); -+ kfree(pos); -+ spin_unlock(&ctx->lock); -+ goto found; -+ } -+ } -+ /* Failed to find the resource */ -+ spin_unlock(&ctx->lock); -+ pr_err("Couldn't find resource type %d base 0x%x num %d\n", -+ i.id_type, i.base, i.num); -+ return -EINVAL; -+found: -+ /* Release the resource to the backend */ -+ backend->release(i.base, i.num); -+ return 0; -+} -+ -+static long ioctl_id_reserve(struct ctx *ctx, void __user *arg) -+{ -+ struct usdpaa_ioctl_id_reserve i; -+ const struct alloc_backend *backend; -+ struct active_resource *tmp, *pos; -+ -+ int ret = copy_from_user(&i, arg, sizeof(i)); -+ if (ret) -+ return ret; -+ if ((i.id_type >= usdpaa_id_max) || !i.num) -+ return -EINVAL; -+ backend = &alloc_backends[i.id_type]; -+ if (!backend->reserve) -+ return -EINVAL; -+ /* Pull the range out of the FD accounting - the range is valid iff this -+ * succeeds. */ -+ spin_lock(&ctx->lock); -+ list_for_each_entry_safe(pos, tmp, &ctx->resources[i.id_type], list) { -+ if (pos->id == i.base && pos->num == i.num) { -+ pos->refcount++; -+ spin_unlock(&ctx->lock); -+ return 0; -+ } -+ } -+ -+ /* Failed to find the resource */ -+ spin_unlock(&ctx->lock); -+ -+ /* Reserve the resource in the backend */ -+ ret = backend->reserve(i.base, i.num); -+ if (ret) -+ return ret; -+ /* Assign the reserved range to the FD accounting */ -+ pos = kmalloc(sizeof(*pos), GFP_KERNEL); -+ if (!pos) { -+ backend->release(i.base, i.num); -+ return -ENOMEM; -+ } -+ spin_lock(&ctx->lock); -+ pos->id = i.base; -+ pos->num = i.num; -+ pos->refcount = 1; -+ list_add(&pos->list, &ctx->resources[i.id_type]); -+ spin_unlock(&ctx->lock); -+ return 0; -+} -+ -+static long ioctl_dma_map(struct file *fp, struct ctx *ctx, -+ struct usdpaa_ioctl_dma_map *i) -+{ -+ struct mem_fragment *frag, *start_frag, *next_frag; -+ struct mem_mapping *map, *tmp; -+ int ret = 0; -+ u32 largest_page, so_far = 0; -+ int frag_count = 0; -+ unsigned long next_addr = PAGE_SIZE, populate; -+ -+ /* error checking to ensure values copied from user space are valid */ -+ if (i->len % PAGE_SIZE) -+ return -EINVAL; -+ -+ map = kmalloc(sizeof(*map), GFP_KERNEL); -+ if (!map) -+ return -ENOMEM; -+ -+ spin_lock(&mem_lock); -+ if (i->flags & USDPAA_DMA_FLAG_SHARE) { -+ list_for_each_entry(frag, &mem_list, list) { -+ if (frag->refs && (frag->flags & -+ USDPAA_DMA_FLAG_SHARE) && -+ !strncmp(i->name, frag->name, -+ USDPAA_DMA_NAME_MAX)) { -+ /* Matching entry */ -+ if ((i->flags & USDPAA_DMA_FLAG_CREATE) && -+ !(i->flags & USDPAA_DMA_FLAG_LAZY)) { -+ ret = -EBUSY; -+ goto out; -+ } -+ -+ /* Check to ensure size matches record */ -+ if (i->len != frag->map_len && i->len) { -+ pr_err("ioctl_dma_map() Size requested does not match %s and is none zero. This usage will be disallowed in future release\n", -+ frag->name); -+ } -+ -+ /* Check if this has already been mapped -+ to this process */ -+ list_for_each_entry(tmp, &ctx->maps, list) -+ if (tmp->root_frag == frag) { -+ /* Already mapped, just need to -+ inc ref count */ -+ tmp->refs++; -+ kfree(map); -+ i->did_create = 0; -+ i->len = tmp->total_size; -+ i->phys_addr = frag->base; -+ i->ptr = tmp->virt_addr; -+ spin_unlock(&mem_lock); -+ return 0; -+ } -+ /* Matching entry - just need to map */ -+ i->has_locking = frag->has_locking; -+ i->did_create = 0; -+ i->len = frag->map_len; -+ start_frag = frag; -+ goto do_map; -+ } -+ } -+ /* No matching entry */ -+ if (!(i->flags & USDPAA_DMA_FLAG_CREATE)) { -+ pr_err("ioctl_dma_map() No matching entry\n"); -+ ret = -ENOMEM; -+ goto out; -+ } -+ } -+ /* New fragment required, size must be provided. */ -+ if (!i->len) { -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ /* Find one of more contiguous fragments that satisfy the total length -+ trying to minimize the number of fragments -+ compute the largest page size that the allocation could use */ -+ largest_page = largest_page_size(i->len); -+ start_frag = NULL; -+ while (largest_page && -+ largest_page <= largest_page_size(phys_size) && -+ start_frag == NULL) { -+ /* Search the list for a frag of that size */ -+ list_for_each_entry(frag, &mem_list, list) { -+ if (!frag->refs && (frag->len == largest_page)) { -+ /* See if the next x fragments are free -+ and can accomidate the size */ -+ u32 found_size = largest_page; -+ next_frag = list_entry(frag->list.prev, -+ struct mem_fragment, -+ list); -+ /* If the fragement is too small check -+ if the neighbours cab support it */ -+ while (found_size < i->len) { -+ if (&mem_list == &next_frag->list) -+ break; /* End of list */ -+ if (next_frag->refs != 0 || -+ next_frag->len == 0) -+ break; /* not enough space */ -+ found_size += next_frag->len; -+ next_frag = list_entry( -+ next_frag->list.prev, -+ struct mem_fragment, -+ list); -+ } -+ if (found_size >= i->len) { -+ /* Success! there is enough contigous -+ free space */ -+ start_frag = frag; -+ break; -+ } -+ } -+ } /* next frag loop */ -+ /* Couldn't statisfy the request with this -+ largest page size, try a smaller one */ -+ largest_page <<= 2; -+ } -+ if (start_frag == NULL) { -+ /* Couldn't find proper amount of space */ -+ ret = -ENOMEM; -+ goto out; -+ } -+ i->did_create = 1; -+do_map: -+ /* Verify there is sufficient space to do the mapping */ -+ down_write(¤t->mm->mmap_sem); -+ next_addr = usdpaa_get_unmapped_area(fp, next_addr, i->len, 0, 0); -+ up_write(¤t->mm->mmap_sem); -+ -+ if (next_addr & ~PAGE_MASK) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ /* We may need to divide the final fragment to accomidate the mapping */ -+ next_frag = start_frag; -+ while (so_far != i->len) { -+ BUG_ON(next_frag->len == 0); -+ while ((next_frag->len + so_far) > i->len) { -+ /* Split frag until they match */ -+ split_frag(next_frag); -+ } -+ so_far += next_frag->len; -+ next_frag->refs++; -+ ++frag_count; -+ next_frag = list_entry(next_frag->list.prev, -+ struct mem_fragment, list); -+ } -+ if (i->did_create) { -+ size_t name_len = 0; -+ start_frag->flags = i->flags; -+ strncpy(start_frag->name, i->name, USDPAA_DMA_NAME_MAX); -+ name_len = strnlen(start_frag->name, USDPAA_DMA_NAME_MAX); -+ if (name_len >= USDPAA_DMA_NAME_MAX) { -+ ret = -EFAULT; -+ goto out; -+ } -+ start_frag->map_len = i->len; -+ start_frag->has_locking = i->has_locking; -+ init_waitqueue_head(&start_frag->wq); -+ start_frag->owner = NULL; -+ } -+ -+ /* Setup the map entry */ -+ map->root_frag = start_frag; -+ map->total_size = i->len; -+ map->frag_count = frag_count; -+ map->refs = 1; -+ list_add(&map->list, &ctx->maps); -+ i->phys_addr = start_frag->base; -+out: -+ spin_unlock(&mem_lock); -+ -+ if (!ret) { -+ unsigned long longret; -+ down_write(¤t->mm->mmap_sem); -+ longret = do_mmap_pgoff(fp, next_addr, map->total_size, -+ PROT_READ | -+ (i->flags & -+ USDPAA_DMA_FLAG_RDONLY ? 0 -+ : PROT_WRITE), -+ MAP_SHARED, -+ start_frag->pfn_base, -+ &populate); -+ up_write(¤t->mm->mmap_sem); -+ if (longret & ~PAGE_MASK) { -+ ret = (int)longret; -+ } else { -+ i->ptr = (void *)longret; -+ map->virt_addr = i->ptr; -+ } -+ } else -+ kfree(map); -+ return ret; -+} -+ -+static long ioctl_dma_unmap(struct ctx *ctx, void __user *arg) -+{ -+ struct mem_mapping *map; -+ struct vm_area_struct *vma; -+ int ret, i; -+ struct mem_fragment *current_frag; -+ size_t sz; -+ unsigned long base; -+ unsigned long vaddr; -+ -+ down_write(¤t->mm->mmap_sem); -+ vma = find_vma(current->mm, (unsigned long)arg); -+ if (!vma || (vma->vm_start > (unsigned long)arg)) { -+ up_write(¤t->mm->mmap_sem); -+ return -EFAULT; -+ } -+ spin_lock(&mem_lock); -+ list_for_each_entry(map, &ctx->maps, list) { -+ if (map->root_frag->pfn_base == vma->vm_pgoff) { -+ /* Drop the map lock if we hold it */ -+ if (map->root_frag->has_locking && -+ (map->root_frag->owner == map)) { -+ map->root_frag->owner = NULL; -+ wake_up(&map->root_frag->wq); -+ } -+ goto map_match; -+ } -+ } -+ /* Failed to find a matching mapping for this process */ -+ ret = -EFAULT; -+ spin_unlock(&mem_lock); -+ goto out; -+map_match: -+ map->refs--; -+ if (map->refs != 0) { -+ /* Another call the dma_map is referencing this */ -+ ret = 0; -+ spin_unlock(&mem_lock); -+ goto out; -+ } -+ -+ current_frag = map->root_frag; -+ vaddr = (unsigned long) map->virt_addr; -+ for (i = 0; i < map->frag_count; i++) { -+ DPA_ASSERT(current_frag->refs > 0); -+ --current_frag->refs; -+#if !(defined(CONFIG_ARM) || defined(CONFIG_ARM64)) -+ /* -+ * Make sure we invalidate the TLB entry for -+ * this fragment, otherwise a remap of a different -+ * page to this vaddr would give acces to an -+ * incorrect piece of memory -+ */ -+ cleartlbcam(vaddr, mfspr(SPRN_PID)); -+#endif -+ vaddr += current_frag->len; -+ current_frag = list_entry(current_frag->list.prev, -+ struct mem_fragment, list); -+ } -+ map->root_frag->name[0] = 0; -+ list_del(&map->list); -+ compress_frags(); -+ spin_unlock(&mem_lock); -+ -+ base = vma->vm_start; -+ sz = vma->vm_end - vma->vm_start; -+ do_munmap(current->mm, base, sz); -+ ret = 0; -+ out: -+ up_write(¤t->mm->mmap_sem); -+ return ret; -+} -+ -+static long ioctl_dma_stats(struct ctx *ctx, void __user *arg) -+{ -+ struct mem_fragment *frag; -+ struct usdpaa_ioctl_dma_used result; -+ -+ result.free_bytes = 0; -+ result.total_bytes = phys_size; -+ -+ list_for_each_entry(frag, &mem_list, list) { -+ if (frag->refs == 0) -+ result.free_bytes += frag->len; -+ } -+ -+ return copy_to_user(arg, &result, sizeof(result)); } -+ -+static int test_lock(struct mem_mapping *map) -+{ -+ int ret = 0; -+ spin_lock(&mem_lock); -+ if (!map->root_frag->owner) { -+ map->root_frag->owner = map; -+ ret = 1; -+ } -+ spin_unlock(&mem_lock); -+ return ret; -+} -+ -+static long ioctl_dma_lock(struct ctx *ctx, void __user *arg) -+{ -+ struct mem_mapping *map; -+ struct vm_area_struct *vma; -+ -+ down_read(¤t->mm->mmap_sem); -+ vma = find_vma(current->mm, (unsigned long)arg); -+ if (!vma || (vma->vm_start > (unsigned long)arg)) { -+ up_read(¤t->mm->mmap_sem); -+ return -EFAULT; -+ } -+ spin_lock(&mem_lock); -+ list_for_each_entry(map, &ctx->maps, list) { -+ if (map->root_frag->pfn_base == vma->vm_pgoff) -+ goto map_match; -+ } -+ map = NULL; -+map_match: -+ spin_unlock(&mem_lock); -+ up_read(¤t->mm->mmap_sem); -+ -+ if (!map) -+ return -EFAULT; -+ if (!map->root_frag->has_locking) -+ return -ENODEV; -+ return wait_event_interruptible(map->root_frag->wq, test_lock(map)); -+} -+ -+static long ioctl_dma_unlock(struct ctx *ctx, void __user *arg) -+{ -+ struct mem_mapping *map; -+ struct vm_area_struct *vma; -+ int ret; -+ -+ down_read(¤t->mm->mmap_sem); -+ vma = find_vma(current->mm, (unsigned long)arg); -+ if (!vma || (vma->vm_start > (unsigned long)arg)) -+ ret = -EFAULT; -+ else { -+ spin_lock(&mem_lock); -+ list_for_each_entry(map, &ctx->maps, list) { -+ if (map->root_frag->pfn_base == vma->vm_pgoff) { -+ if (!map->root_frag->has_locking) -+ ret = -ENODEV; -+ else if (map->root_frag->owner == map) { -+ map->root_frag->owner = NULL; -+ wake_up(&map->root_frag->wq); -+ ret = 0; -+ } else -+ ret = -EBUSY; -+ goto map_match; -+ } -+ } -+ ret = -EINVAL; -+map_match: -+ spin_unlock(&mem_lock); -+ } -+ up_read(¤t->mm->mmap_sem); -+ return ret; -+} -+ -+static int portal_mmap(struct file *fp, struct resource *res, void **ptr) -+{ -+ unsigned long longret = 0, populate; -+ resource_size_t len; -+ -+ down_write(¤t->mm->mmap_sem); -+ len = resource_size(res); -+ if (len != (unsigned long)len) -+ return -EINVAL; -+ longret = do_mmap_pgoff(fp, PAGE_SIZE, (unsigned long)len, -+ PROT_READ | PROT_WRITE, MAP_SHARED, -+ res->start >> PAGE_SHIFT, &populate); -+ up_write(¤t->mm->mmap_sem); -+ -+ if (longret & ~PAGE_MASK) -+ return (int)longret; -+ -+ *ptr = (void *) longret; -+ return 0; -+} -+ -+static void portal_munmap(struct resource *res, void *ptr) -+{ -+ down_write(¤t->mm->mmap_sem); -+ do_munmap(current->mm, (unsigned long)ptr, resource_size(res)); -+ up_write(¤t->mm->mmap_sem); -+} -+ -+static long ioctl_portal_map(struct file *fp, struct ctx *ctx, -+ struct usdpaa_ioctl_portal_map *arg) -+{ -+ struct portal_mapping *mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); -+ int ret; -+ -+ if (!mapping) -+ return -ENOMEM; -+ -+ mapping->user = *arg; -+ mapping->iommu_domain = NULL; -+ -+ if (mapping->user.type == usdpaa_portal_qman) { -+ mapping->qportal = -+ qm_get_unused_portal_idx(mapping->user.index); -+ if (!mapping->qportal) { -+ ret = -ENODEV; -+ goto err_get_portal; -+ } -+ mapping->phys = &mapping->qportal->addr_phys[0]; -+ mapping->user.channel = mapping->qportal->public_cfg.channel; -+ mapping->user.pools = mapping->qportal->public_cfg.pools; -+ mapping->user.index = mapping->qportal->public_cfg.index; -+ } else if (mapping->user.type == usdpaa_portal_bman) { -+ mapping->bportal = -+ bm_get_unused_portal_idx(mapping->user.index); -+ if (!mapping->bportal) { -+ ret = -ENODEV; -+ goto err_get_portal; -+ } -+ mapping->phys = &mapping->bportal->addr_phys[0]; -+ mapping->user.index = mapping->bportal->public_cfg.index; -+ } else { -+ ret = -EINVAL; -+ goto err_copy_from_user; -+ } -+ /* Need to put pcfg in ctx's list before the mmaps because the mmap -+ * handlers look it up. */ -+ spin_lock(&mem_lock); -+ list_add(&mapping->list, &ctx->portals); -+ spin_unlock(&mem_lock); -+ ret = portal_mmap(fp, &mapping->phys[DPA_PORTAL_CE], -+ &mapping->user.addr.cena); -+ if (ret) -+ goto err_mmap_cena; -+ ret = portal_mmap(fp, &mapping->phys[DPA_PORTAL_CI], -+ &mapping->user.addr.cinh); -+ if (ret) -+ goto err_mmap_cinh; -+ *arg = mapping->user; -+ return ret; -+ -+err_mmap_cinh: -+ portal_munmap(&mapping->phys[DPA_PORTAL_CE], mapping->user.addr.cena); -+err_mmap_cena: -+ if ((mapping->user.type == usdpaa_portal_qman) && mapping->qportal) -+ qm_put_unused_portal(mapping->qportal); -+ else if ((mapping->user.type == usdpaa_portal_bman) && mapping->bportal) -+ bm_put_unused_portal(mapping->bportal); -+ spin_lock(&mem_lock); -+ list_del(&mapping->list); -+ spin_unlock(&mem_lock); -+err_get_portal: -+err_copy_from_user: -+ kfree(mapping); -+ return ret; -+} -+ -+static long ioctl_portal_unmap(struct ctx *ctx, struct usdpaa_portal_map *i) -+{ -+ struct portal_mapping *mapping; -+ struct vm_area_struct *vma; -+ unsigned long pfn; -+ u32 channel; -+ -+ /* Get the PFN corresponding to one of the virt addresses */ -+ down_read(¤t->mm->mmap_sem); -+ vma = find_vma(current->mm, (unsigned long)i->cinh); -+ if (!vma || (vma->vm_start > (unsigned long)i->cinh)) { -+ up_read(¤t->mm->mmap_sem); -+ return -EFAULT; -+ } -+ pfn = vma->vm_pgoff; -+ up_read(¤t->mm->mmap_sem); -+ -+ /* Find the corresponding portal */ -+ spin_lock(&mem_lock); -+ list_for_each_entry(mapping, &ctx->portals, list) { -+ if (pfn == (mapping->phys[DPA_PORTAL_CI].start >> PAGE_SHIFT)) -+ goto found; -+ } -+ mapping = NULL; -+found: -+ if (mapping) -+ list_del(&mapping->list); -+ spin_unlock(&mem_lock); -+ if (!mapping) -+ return -ENODEV; -+ portal_munmap(&mapping->phys[DPA_PORTAL_CI], mapping->user.addr.cinh); -+ portal_munmap(&mapping->phys[DPA_PORTAL_CE], mapping->user.addr.cena); -+ if (mapping->user.type == usdpaa_portal_qman) { -+ init_qm_portal(mapping->qportal, -+ &mapping->qman_portal_low); -+ -+ /* Tear down any FQs this portal is referencing */ -+ channel = mapping->qportal->public_cfg.channel; -+ qm_check_and_destroy_fqs(&mapping->qman_portal_low, -+ &channel, -+ check_portal_channel); -+ qm_put_unused_portal(mapping->qportal); -+ } else if (mapping->user.type == usdpaa_portal_bman) { -+ init_bm_portal(mapping->bportal, -+ &mapping->bman_portal_low); -+ bm_put_unused_portal(mapping->bportal); -+ } -+ kfree(mapping); -+ return 0; -+} -+ -+static void portal_config_pamu(struct qm_portal_config *pcfg, uint8_t sdest, -+ uint32_t cpu, uint32_t cache, uint32_t window) -+{ -+#ifdef CONFIG_FSL_PAMU -+ int ret; -+ int window_count = 1; -+ struct iommu_domain_geometry geom_attr; -+ struct pamu_stash_attribute stash_attr; -+ -+ pcfg->iommu_domain = iommu_domain_alloc(&platform_bus_type); -+ if (!pcfg->iommu_domain) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_domain_alloc() failed", -+ __func__); -+ goto _no_iommu; -+ } -+ geom_attr.aperture_start = 0; -+ geom_attr.aperture_end = -+ ((dma_addr_t)1 << min(8 * sizeof(dma_addr_t), (size_t)36)) - 1; -+ geom_attr.force_aperture = true; -+ ret = iommu_domain_set_attr(pcfg->iommu_domain, DOMAIN_ATTR_GEOMETRY, -+ &geom_attr); -+ if (ret < 0) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_domain_set_attr() = %d", -+ __func__, ret); -+ goto _iommu_domain_free; -+ } -+ ret = iommu_domain_set_attr(pcfg->iommu_domain, DOMAIN_ATTR_WINDOWS, -+ &window_count); -+ if (ret < 0) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_domain_set_attr() = %d", -+ __func__, ret); -+ goto _iommu_domain_free; -+ } -+ stash_attr.cpu = cpu; -+ stash_attr.cache = cache; -+ /* set stash information for the window */ -+ stash_attr.window = 0; -+ -+ ret = iommu_domain_set_attr(pcfg->iommu_domain, -+ DOMAIN_ATTR_FSL_PAMU_STASH, -+ &stash_attr); -+ if (ret < 0) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_domain_set_attr() = %d", -+ __func__, ret); -+ goto _iommu_domain_free; -+ } -+ ret = iommu_domain_window_enable(pcfg->iommu_domain, 0, 0, 1ULL << 36, -+ IOMMU_READ | IOMMU_WRITE); -+ if (ret < 0) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_domain_window_enable() = %d", -+ __func__, ret); -+ goto _iommu_domain_free; -+ } -+ ret = iommu_attach_device(pcfg->iommu_domain, &pcfg->dev); -+ if (ret < 0) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_device_attach() = %d", -+ __func__, ret); -+ goto _iommu_domain_free; -+ } -+ ret = iommu_domain_set_attr(pcfg->iommu_domain, -+ DOMAIN_ATTR_FSL_PAMU_ENABLE, -+ &window_count); -+ if (ret < 0) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_domain_set_attr() = %d", -+ __func__, ret); -+ goto _iommu_detach_device; -+ } -+_no_iommu: -+#endif -+ -+#ifdef CONFIG_FSL_QMAN_CONFIG -+ if (qman_set_sdest(pcfg->public_cfg.channel, sdest)) -+#endif -+ pr_warn("Failed to set QMan portal's stash request queue\n"); -+ -+ return; -+ -+#ifdef CONFIG_FSL_PAMU -+_iommu_detach_device: -+ iommu_detach_device(pcfg->iommu_domain, NULL); -+_iommu_domain_free: -+ iommu_domain_free(pcfg->iommu_domain); -+#endif -+} -+ -+static long ioctl_allocate_raw_portal(struct file *fp, struct ctx *ctx, -+ struct usdpaa_ioctl_raw_portal *arg) -+{ -+ struct portal_mapping *mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); -+ int ret; -+ -+ if (!mapping) -+ return -ENOMEM; -+ -+ mapping->user.type = arg->type; -+ mapping->iommu_domain = NULL; -+ if (arg->type == usdpaa_portal_qman) { -+ mapping->qportal = qm_get_unused_portal_idx(arg->index); -+ if (!mapping->qportal) { -+ ret = -ENODEV; -+ goto err; -+ } -+ mapping->phys = &mapping->qportal->addr_phys[0]; -+ arg->index = mapping->qportal->public_cfg.index; -+ arg->cinh = mapping->qportal->addr_phys[DPA_PORTAL_CI].start; -+ arg->cena = mapping->qportal->addr_phys[DPA_PORTAL_CE].start; -+ if (arg->enable_stash) { -+ /* Setup the PAMU with the supplied parameters */ -+ portal_config_pamu(mapping->qportal, arg->sdest, -+ arg->cpu, arg->cache, arg->window); -+ } -+ } else if (mapping->user.type == usdpaa_portal_bman) { -+ mapping->bportal = -+ bm_get_unused_portal_idx(arg->index); -+ if (!mapping->bportal) { -+ ret = -ENODEV; -+ goto err; -+ } -+ mapping->phys = &mapping->bportal->addr_phys[0]; -+ arg->index = mapping->bportal->public_cfg.index; -+ arg->cinh = mapping->bportal->addr_phys[DPA_PORTAL_CI].start; -+ arg->cena = mapping->bportal->addr_phys[DPA_PORTAL_CE].start; -+ } else { -+ ret = -EINVAL; -+ goto err; -+ } -+ /* Need to put pcfg in ctx's list before the mmaps because the mmap -+ * handlers look it up. */ -+ spin_lock(&mem_lock); -+ list_add(&mapping->list, &ctx->portals); -+ spin_unlock(&mem_lock); -+ return 0; -+err: -+ kfree(mapping); -+ return ret; -+} -+ -+static long ioctl_free_raw_portal(struct file *fp, struct ctx *ctx, -+ struct usdpaa_ioctl_raw_portal *arg) -+{ -+ struct portal_mapping *mapping; -+ u32 channel; -+ -+ /* Find the corresponding portal */ -+ spin_lock(&mem_lock); -+ list_for_each_entry(mapping, &ctx->portals, list) { -+ if (mapping->phys[DPA_PORTAL_CI].start == arg->cinh) -+ goto found; -+ } -+ mapping = NULL; -+found: -+ if (mapping) -+ list_del(&mapping->list); -+ spin_unlock(&mem_lock); -+ if (!mapping) -+ return -ENODEV; -+ if (mapping->user.type == usdpaa_portal_qman) { -+ init_qm_portal(mapping->qportal, -+ &mapping->qman_portal_low); -+ -+ /* Tear down any FQs this portal is referencing */ -+ channel = mapping->qportal->public_cfg.channel; -+ qm_check_and_destroy_fqs(&mapping->qman_portal_low, -+ &channel, -+ check_portal_channel); -+ qm_put_unused_portal(mapping->qportal); -+ } else if (mapping->user.type == usdpaa_portal_bman) { -+ init_bm_portal(mapping->bportal, -+ &mapping->bman_portal_low); -+ bm_put_unused_portal(mapping->bportal); -+ } -+ kfree(mapping); -+ return 0; -+} -+ -+static long usdpaa_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) -+{ -+ struct ctx *ctx = fp->private_data; -+ void __user *a = (void __user *)arg; -+ switch (cmd) { -+ case USDPAA_IOCTL_ID_ALLOC: -+ return ioctl_id_alloc(ctx, a); -+ case USDPAA_IOCTL_ID_RELEASE: -+ return ioctl_id_release(ctx, a); -+ case USDPAA_IOCTL_ID_RESERVE: -+ return ioctl_id_reserve(ctx, a); -+ case USDPAA_IOCTL_DMA_MAP: -+ { -+ struct usdpaa_ioctl_dma_map input; -+ int ret; -+ if (copy_from_user(&input, a, sizeof(input))) -+ return -EFAULT; -+ ret = ioctl_dma_map(fp, ctx, &input); -+ if (copy_to_user(a, &input, sizeof(input))) -+ return -EFAULT; -+ return ret; -+ } -+ case USDPAA_IOCTL_DMA_UNMAP: -+ return ioctl_dma_unmap(ctx, a); -+ case USDPAA_IOCTL_DMA_LOCK: -+ return ioctl_dma_lock(ctx, a); -+ case USDPAA_IOCTL_DMA_UNLOCK: -+ return ioctl_dma_unlock(ctx, a); -+ case USDPAA_IOCTL_PORTAL_MAP: -+ { -+ struct usdpaa_ioctl_portal_map input; -+ int ret; -+ if (copy_from_user(&input, a, sizeof(input))) -+ return -EFAULT; -+ ret = ioctl_portal_map(fp, ctx, &input); -+ if (copy_to_user(a, &input, sizeof(input))) -+ return -EFAULT; -+ return ret; -+ } -+ case USDPAA_IOCTL_PORTAL_UNMAP: -+ { -+ struct usdpaa_portal_map input; -+ if (copy_from_user(&input, a, sizeof(input))) -+ return -EFAULT; -+ return ioctl_portal_unmap(ctx, &input); -+ } -+ case USDPAA_IOCTL_DMA_USED: -+ return ioctl_dma_stats(ctx, a); -+ case USDPAA_IOCTL_ALLOC_RAW_PORTAL: -+ { -+ struct usdpaa_ioctl_raw_portal input; -+ int ret; -+ if (copy_from_user(&input, a, sizeof(input))) -+ return -EFAULT; -+ ret = ioctl_allocate_raw_portal(fp, ctx, &input); -+ if (copy_to_user(a, &input, sizeof(input))) -+ return -EFAULT; -+ return ret; -+ } -+ case USDPAA_IOCTL_FREE_RAW_PORTAL: -+ { -+ struct usdpaa_ioctl_raw_portal input; -+ if (copy_from_user(&input, a, sizeof(input))) -+ return -EFAULT; -+ return ioctl_free_raw_portal(fp, ctx, &input); -+ } -+ } -+ return -EINVAL; -+} -+ -+static long usdpaa_ioctl_compat(struct file *fp, unsigned int cmd, -+ unsigned long arg) -+{ -+#ifdef CONFIG_COMPAT -+ struct ctx *ctx = fp->private_data; -+ void __user *a = (void __user *)arg; -+#endif -+ switch (cmd) { -+#ifdef CONFIG_COMPAT -+ case USDPAA_IOCTL_DMA_MAP_COMPAT: -+ { -+ int ret; -+ struct usdpaa_ioctl_dma_map_compat input; -+ struct usdpaa_ioctl_dma_map converted; -+ -+ if (copy_from_user(&input, a, sizeof(input))) -+ return -EFAULT; -+ -+ converted.ptr = compat_ptr(input.ptr); -+ converted.phys_addr = input.phys_addr; -+ converted.len = input.len; -+ converted.flags = input.flags; -+ strncpy(converted.name, input.name, USDPAA_DMA_NAME_MAX); -+ converted.has_locking = input.has_locking; -+ converted.did_create = input.did_create; -+ -+ ret = ioctl_dma_map(fp, ctx, &converted); -+ input.ptr = ptr_to_compat(converted.ptr); -+ input.phys_addr = converted.phys_addr; -+ input.len = converted.len; -+ input.flags = converted.flags; -+ strncpy(input.name, converted.name, USDPAA_DMA_NAME_MAX); -+ input.has_locking = converted.has_locking; -+ input.did_create = converted.did_create; -+ if (copy_to_user(a, &input, sizeof(input))) -+ return -EFAULT; -+ return ret; -+ } -+ case USDPAA_IOCTL_PORTAL_MAP_COMPAT: -+ { -+ int ret; -+ struct compat_usdpaa_ioctl_portal_map input; -+ struct usdpaa_ioctl_portal_map converted; -+ if (copy_from_user(&input, a, sizeof(input))) -+ return -EFAULT; -+ converted.type = input.type; -+ converted.index = input.index; -+ ret = ioctl_portal_map(fp, ctx, &converted); -+ input.addr.cinh = ptr_to_compat(converted.addr.cinh); -+ input.addr.cena = ptr_to_compat(converted.addr.cena); -+ input.channel = converted.channel; -+ input.pools = converted.pools; -+ input.index = converted.index; -+ if (copy_to_user(a, &input, sizeof(input))) -+ return -EFAULT; -+ return ret; -+ } -+ case USDPAA_IOCTL_PORTAL_UNMAP_COMPAT: -+ { -+ struct usdpaa_portal_map_compat input; -+ struct usdpaa_portal_map converted; -+ -+ if (copy_from_user(&input, a, sizeof(input))) -+ return -EFAULT; -+ converted.cinh = compat_ptr(input.cinh); -+ converted.cena = compat_ptr(input.cena); -+ return ioctl_portal_unmap(ctx, &converted); -+ } -+ case USDPAA_IOCTL_ALLOC_RAW_PORTAL_COMPAT: -+ { -+ int ret; -+ struct usdpaa_ioctl_raw_portal converted; -+ struct compat_ioctl_raw_portal input; -+ if (copy_from_user(&input, a, sizeof(input))) -+ return -EFAULT; -+ converted.type = input.type; -+ converted.index = input.index; -+ converted.enable_stash = input.enable_stash; -+ converted.cpu = input.cpu; -+ converted.cache = input.cache; -+ converted.window = input.window; -+ converted.sdest = input.sdest; -+ ret = ioctl_allocate_raw_portal(fp, ctx, &converted); -+ -+ input.cinh = converted.cinh; -+ input.cena = converted.cena; -+ input.index = converted.index; -+ -+ if (copy_to_user(a, &input, sizeof(input))) -+ return -EFAULT; -+ return ret; -+ } -+ case USDPAA_IOCTL_FREE_RAW_PORTAL_COMPAT: -+ { -+ struct usdpaa_ioctl_raw_portal converted; -+ struct compat_ioctl_raw_portal input; -+ if (copy_from_user(&input, a, sizeof(input))) -+ return -EFAULT; -+ converted.type = input.type; -+ converted.index = input.index; -+ converted.cinh = input.cinh; -+ converted.cena = input.cena; -+ return ioctl_free_raw_portal(fp, ctx, &converted); -+ } -+#endif -+ default: -+ return usdpaa_ioctl(fp, cmd, arg); -+ } -+ return -EINVAL; -+} -+ -+int usdpaa_get_portal_config(struct file *filp, void *cinh, -+ enum usdpaa_portal_type ptype, unsigned int *irq, -+ void **iir_reg) -+{ -+ /* Walk the list of portals for filp and return the config -+ for the portal that matches the hint */ -+ struct ctx *context; -+ struct portal_mapping *portal; -+ -+ /* First sanitize the filp */ -+ if (filp->f_op->open != usdpaa_open) -+ return -ENODEV; -+ context = filp->private_data; -+ spin_lock(&context->lock); -+ list_for_each_entry(portal, &context->portals, list) { -+ if (portal->user.type == ptype && -+ portal->user.addr.cinh == cinh) { -+ if (ptype == usdpaa_portal_qman) { -+ *irq = portal->qportal->public_cfg.irq; -+ *iir_reg = portal->qportal->addr_virt[1] + -+ QM_REG_IIR; -+ } else { -+ *irq = portal->bportal->public_cfg.irq; -+ *iir_reg = portal->bportal->addr_virt[1] + -+ BM_REG_IIR; -+ } -+ spin_unlock(&context->lock); -+ return 0; -+ } -+ } -+ spin_unlock(&context->lock); -+ return -EINVAL; -+} -+ -+static const struct file_operations usdpaa_fops = { -+ .open = usdpaa_open, -+ .release = usdpaa_release, -+ .mmap = usdpaa_mmap, -+ .get_unmapped_area = usdpaa_get_unmapped_area, -+ .unlocked_ioctl = usdpaa_ioctl, -+ .compat_ioctl = usdpaa_ioctl_compat -+}; -+ -+static struct miscdevice usdpaa_miscdev = { -+ .name = "fsl-usdpaa", -+ .fops = &usdpaa_fops, -+ .minor = MISC_DYNAMIC_MINOR, -+}; -+ -+/* Early-boot memory allocation. The boot-arg "usdpaa_mem=" is used to -+ * indicate how much memory (if any) to allocate during early boot. If the -+ * format "usdpaa_mem=," is used, then will be interpreted as the -+ * number of TLB1 entries to reserve (default is 1). If there are more mappings -+ * than there are TLB1 entries, fault-handling will occur. */ -+ -+static __init int usdpaa_mem(char *arg) -+{ -+ pr_warn("uspdaa_mem argument is depracated\n"); -+ arg_phys_size = memparse(arg, &arg); -+ num_tlb = 1; -+ if (*arg == ',') { -+ unsigned long ul; -+ int err = kstrtoul(arg + 1, 0, &ul); -+ if (err < 0) { -+ num_tlb = 1; -+ pr_warn("ERROR, usdpaa_mem arg is invalid\n"); -+ } else -+ num_tlb = (unsigned int)ul; -+ } -+ return 0; -+} -+early_param("usdpaa_mem", usdpaa_mem); -+ -+static int usdpaa_mem_init(struct reserved_mem *rmem) -+{ -+ phys_start = rmem->base; -+ phys_size = rmem->size; -+ -+ WARN_ON(!(phys_start && phys_size)); -+ -+ return 0; -+} -+RESERVEDMEM_OF_DECLARE(usdpaa_mem_init, "fsl,usdpaa-mem", usdpaa_mem_init); -+ -+__init int fsl_usdpaa_init_early(void) -+{ -+ if (!phys_size || !phys_start) { -+ pr_info("No USDPAA memory, no 'fsl,usdpaa-mem' in device-tree\n"); -+ return 0; -+ } -+ if (phys_size % PAGE_SIZE) { -+ pr_err("'fsl,usdpaa-mem' size must be a multiple of page size\n"); -+ phys_size = 0; -+ return 0; -+ } -+ if (arg_phys_size && phys_size != arg_phys_size) { -+ pr_err("'usdpaa_mem argument size (0x%llx) does not match device tree size (0x%llx)\n", -+ arg_phys_size, phys_size); -+ phys_size = 0; -+ return 0; -+ } -+ pfn_start = phys_start >> PAGE_SHIFT; -+ pfn_size = phys_size >> PAGE_SHIFT; -+#ifdef CONFIG_PPC -+ first_tlb = current_tlb = tlbcam_index; -+ tlbcam_index += num_tlb; -+#endif -+ pr_info("USDPAA region at %llx:%llx(%lx:%lx), %d TLB1 entries)\n", -+ phys_start, phys_size, pfn_start, pfn_size, num_tlb); -+ return 0; -+} -+subsys_initcall(fsl_usdpaa_init_early); -+ -+ -+static int __init usdpaa_init(void) -+{ -+ struct mem_fragment *frag; -+ int ret; -+ u64 tmp_size = phys_size; -+ u64 tmp_start = phys_start; -+ u64 tmp_pfn_size = pfn_size; -+ u64 tmp_pfn_start = pfn_start; -+ -+ pr_info("Freescale USDPAA process driver\n"); -+ if (!phys_start) { -+ pr_warn("fsl-usdpaa: no region found\n"); -+ return 0; -+ } -+ -+ while (tmp_size != 0) { -+ u32 frag_size = largest_page_size(tmp_size); -+ frag = kmalloc(sizeof(*frag), GFP_KERNEL); -+ if (!frag) { -+ pr_err("Failed to setup USDPAA memory accounting\n"); -+ return -ENOMEM; -+ } -+ frag->base = tmp_start; -+ frag->len = frag->root_len = frag_size; -+ frag->root_pfn = tmp_pfn_start; -+ frag->pfn_base = tmp_pfn_start; -+ frag->pfn_len = frag_size / PAGE_SIZE; -+ frag->refs = 0; -+ init_waitqueue_head(&frag->wq); -+ frag->owner = NULL; -+ list_add(&frag->list, &mem_list); -+ -+ /* Adjust for this frag */ -+ tmp_start += frag_size; -+ tmp_size -= frag_size; -+ tmp_pfn_start += frag_size / PAGE_SIZE; -+ tmp_pfn_size -= frag_size / PAGE_SIZE; -+ } -+ ret = misc_register(&usdpaa_miscdev); -+ if (ret) -+ pr_err("fsl-usdpaa: failed to register misc device\n"); -+ return ret; -+} -+ -+static void __exit usdpaa_exit(void) -+{ -+ misc_deregister(&usdpaa_miscdev); -+} -+ -+module_init(usdpaa_init); -+module_exit(usdpaa_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Freescale Semiconductor"); -+MODULE_DESCRIPTION("Freescale USDPAA process driver"); ---- /dev/null -+++ b/drivers/staging/fsl_qbman/fsl_usdpaa_irq.c -@@ -0,0 +1,289 @@ -+/* Copyright (c) 2013 Freescale Semiconductor, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* define a device that allows USPDAA processes to open a file -+ descriptor and specify which IRQ it wants to montior using an ioctl() -+ When an IRQ is received, the device becomes readable so that a process -+ can use read() or select() type calls to monitor for IRQs */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "qman_low.h" -+#include "bman_low.h" -+ -+struct usdpaa_irq_ctx { -+ int irq_set; /* Set to true once the irq is set via ioctl */ -+ unsigned int irq_num; -+ u32 last_irq_count; /* Last value returned from read */ -+ u32 irq_count; /* Number of irqs since last read */ -+ wait_queue_head_t wait_queue; /* Waiting processes */ -+ spinlock_t lock; -+ void *inhibit_addr; /* inhibit register address */ -+ struct file *usdpaa_filp; -+ char irq_name[128]; -+}; -+ -+static int usdpaa_irq_open(struct inode *inode, struct file *filp) -+{ -+ struct usdpaa_irq_ctx *ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); -+ if (!ctx) -+ return -ENOMEM; -+ ctx->irq_set = 0; -+ ctx->irq_count = 0; -+ ctx->last_irq_count = 0; -+ init_waitqueue_head(&ctx->wait_queue); -+ spin_lock_init(&ctx->lock); -+ filp->private_data = ctx; -+ return 0; -+} -+ -+static int usdpaa_irq_release(struct inode *inode, struct file *filp) -+{ -+ struct usdpaa_irq_ctx *ctx = filp->private_data; -+ if (ctx->irq_set) { -+ /* Inhibit the IRQ */ -+ out_be32(ctx->inhibit_addr, 0x1); -+ irq_set_affinity_hint(ctx->irq_num, NULL); -+ free_irq(ctx->irq_num, ctx); -+ ctx->irq_set = 0; -+ fput(ctx->usdpaa_filp); -+ } -+ kfree(filp->private_data); -+ return 0; -+} -+ -+static irqreturn_t usdpaa_irq_handler(int irq, void *_ctx) -+{ -+ unsigned long flags; -+ struct usdpaa_irq_ctx *ctx = _ctx; -+ spin_lock_irqsave(&ctx->lock, flags); -+ ++ctx->irq_count; -+ spin_unlock_irqrestore(&ctx->lock, flags); -+ wake_up_all(&ctx->wait_queue); -+ /* Set the inhibit register. This will be reenabled -+ once the USDPAA code handles the IRQ */ -+ out_be32(ctx->inhibit_addr, 0x1); -+ pr_info("Inhibit at %p count %d", ctx->inhibit_addr, ctx->irq_count); -+ return IRQ_HANDLED; -+} -+ -+static int map_irq(struct file *fp, struct usdpaa_ioctl_irq_map *irq_map) -+{ -+ struct usdpaa_irq_ctx *ctx = fp->private_data; -+ int ret; -+ -+ if (ctx->irq_set) { -+ pr_debug("Setting USDPAA IRQ when it was already set!\n"); -+ return -EBUSY; -+ } -+ -+ ctx->usdpaa_filp = fget(irq_map->fd); -+ if (!ctx->usdpaa_filp) { -+ pr_debug("USDPAA fget(%d) returned NULL\n", irq_map->fd); -+ return -EINVAL; -+ } -+ -+ ret = usdpaa_get_portal_config(ctx->usdpaa_filp, irq_map->portal_cinh, -+ irq_map->type, &ctx->irq_num, -+ &ctx->inhibit_addr); -+ if (ret) { -+ pr_debug("USDPAA IRQ couldn't identify portal\n"); -+ fput(ctx->usdpaa_filp); -+ return ret; -+ } -+ -+ ctx->irq_set = 1; -+ -+ snprintf(ctx->irq_name, sizeof(ctx->irq_name), -+ "usdpaa_irq %d", ctx->irq_num); -+ -+ ret = request_irq(ctx->irq_num, usdpaa_irq_handler, 0, -+ ctx->irq_name, ctx); -+ if (ret) { -+ pr_err("USDPAA request_irq(%d) failed, ret= %d\n", -+ ctx->irq_num, ret); -+ ctx->irq_set = 0; -+ fput(ctx->usdpaa_filp); -+ return ret; -+ } -+ ret = irq_set_affinity(ctx->irq_num, tsk_cpus_allowed(current)); -+ if (ret) -+ pr_err("USDPAA irq_set_affinity() failed, ret= %d\n", ret); -+ -+ ret = irq_set_affinity_hint(ctx->irq_num, tsk_cpus_allowed(current)); -+ if (ret) -+ pr_err("USDPAA irq_set_affinity_hint() failed, ret= %d\n", ret); -+ -+ return 0; -+} -+ -+static long usdpaa_irq_ioctl(struct file *fp, unsigned int cmd, -+ unsigned long arg) -+{ -+ int ret; -+ struct usdpaa_ioctl_irq_map irq_map; -+ -+ if (cmd != USDPAA_IOCTL_PORTAL_IRQ_MAP) { -+ pr_debug("USDPAA IRQ unknown command 0x%x\n", cmd); -+ return -EINVAL; -+ } -+ -+ ret = copy_from_user(&irq_map, (void __user *)arg, -+ sizeof(irq_map)); -+ if (ret) -+ return ret; -+ return map_irq(fp, &irq_map); -+} -+ -+static ssize_t usdpaa_irq_read(struct file *filp, char __user *buff, -+ size_t count, loff_t *offp) -+{ -+ struct usdpaa_irq_ctx *ctx = filp->private_data; -+ int ret; -+ -+ if (!ctx->irq_set) { -+ pr_debug("Reading USDPAA IRQ before it was set\n"); -+ return -EINVAL; -+ } -+ -+ if (count < sizeof(ctx->irq_count)) { -+ pr_debug("USDPAA IRQ Read too small\n"); -+ return -EINVAL; -+ } -+ if (ctx->irq_count == ctx->last_irq_count) { -+ if (filp->f_flags & O_NONBLOCK) -+ return -EAGAIN; -+ -+ ret = wait_event_interruptible(ctx->wait_queue, -+ ctx->irq_count != ctx->last_irq_count); -+ if (ret == -ERESTARTSYS) -+ return ret; -+ } -+ -+ ctx->last_irq_count = ctx->irq_count; -+ -+ if (copy_to_user(buff, &ctx->last_irq_count, -+ sizeof(ctx->last_irq_count))) -+ return -EFAULT; -+ return sizeof(ctx->irq_count); -+} -+ -+static unsigned int usdpaa_irq_poll(struct file *filp, poll_table *wait) -+{ -+ struct usdpaa_irq_ctx *ctx = filp->private_data; -+ unsigned int ret = 0; -+ unsigned long flags; -+ -+ if (!ctx->irq_set) -+ return POLLHUP; -+ -+ poll_wait(filp, &ctx->wait_queue, wait); -+ -+ spin_lock_irqsave(&ctx->lock, flags); -+ if (ctx->irq_count != ctx->last_irq_count) -+ ret |= POLLIN | POLLRDNORM; -+ spin_unlock_irqrestore(&ctx->lock, flags); -+ return ret; -+} -+ -+static long usdpaa_irq_ioctl_compat(struct file *fp, unsigned int cmd, -+ unsigned long arg) -+{ -+#ifdef CONFIG_COMPAT -+ void __user *a = (void __user *)arg; -+#endif -+ switch (cmd) { -+#ifdef CONFIG_COMPAT -+ case USDPAA_IOCTL_PORTAL_IRQ_MAP_COMPAT: -+ { -+ struct compat_ioctl_irq_map input; -+ struct usdpaa_ioctl_irq_map converted; -+ if (copy_from_user(&input, a, sizeof(input))) -+ return -EFAULT; -+ converted.type = input.type; -+ converted.fd = input.fd; -+ converted.portal_cinh = compat_ptr(input.portal_cinh); -+ return map_irq(fp, &converted); -+ } -+#endif -+ default: -+ return usdpaa_irq_ioctl(fp, cmd, arg); -+ } -+} -+ -+static const struct file_operations usdpaa_irq_fops = { -+ .open = usdpaa_irq_open, -+ .release = usdpaa_irq_release, -+ .unlocked_ioctl = usdpaa_irq_ioctl, -+ .compat_ioctl = usdpaa_irq_ioctl_compat, -+ .read = usdpaa_irq_read, -+ .poll = usdpaa_irq_poll -+}; -+ -+static struct miscdevice usdpaa_miscdev = { -+ .name = "fsl-usdpaa-irq", -+ .fops = &usdpaa_irq_fops, -+ .minor = MISC_DYNAMIC_MINOR, -+}; -+ -+static int __init usdpaa_irq_init(void) -+{ -+ int ret; -+ -+ pr_info("Freescale USDPAA process IRQ driver\n"); -+ ret = misc_register(&usdpaa_miscdev); -+ if (ret) -+ pr_err("fsl-usdpaa-irq: failed to register misc device\n"); -+ return ret; -+} -+ -+static void __exit usdpaa_irq_exit(void) -+{ -+ misc_deregister(&usdpaa_miscdev); -+} -+ -+module_init(usdpaa_irq_init); -+module_exit(usdpaa_irq_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Freescale Semiconductor"); -+MODULE_DESCRIPTION("Freescale USDPAA process IRQ driver"); ---- /dev/null -+++ b/drivers/staging/fsl_qbman/qbman_driver.c -@@ -0,0 +1,88 @@ -+/* Copyright 2013 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include "qman_private.h" -+#include "bman_private.h" -+__init void qman_init_early(void); -+__init void bman_init_early(void); -+ -+static __init int qbman_init(void) -+{ -+ struct device_node *dn; -+ u32 is_portal_available; -+ -+ bman_init(); -+ qman_init(); -+ -+ is_portal_available = 0; -+ for_each_compatible_node(dn, NULL, "fsl,qman-portal") { -+ if (!of_device_is_available(dn)) -+ continue; -+ else -+ is_portal_available = 1; -+ } -+ -+ if (!qman_have_ccsr() && is_portal_available) { -+ struct qman_fq fq = { -+ .fqid = 1 -+ }; -+ struct qm_mcr_queryfq_np np; -+ int err, retry = CONFIG_FSL_QMAN_INIT_TIMEOUT; -+ struct timespec nowts, diffts, startts = current_kernel_time(); -+ /* Loop while querying given fqid succeeds or time out */ -+ while (1) { -+ err = qman_query_fq_np(&fq, &np); -+ if (!err) { -+ /* success, control-plane has configured QMan */ -+ break; -+ } else if (err != -ERANGE) { -+ pr_err("QMan: I/O error, continuing anyway\n"); -+ break; -+ } -+ nowts = current_kernel_time(); -+ diffts = timespec_sub(nowts, startts); -+ if (diffts.tv_sec > 0) { -+ if (!retry--) { -+ pr_err("QMan: time out, control-plane" -+ " dead?\n"); -+ break; -+ } -+ pr_warn("QMan: polling for the control-plane" -+ " (%d)\n", retry); -+ } -+ } -+ } -+ bman_resource_init(); -+ qman_resource_init(); -+ return 0; -+} -+subsys_initcall(qbman_init); ---- /dev/null -+++ b/drivers/staging/fsl_qbman/qman_config.c -@@ -0,0 +1,1199 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include "qman_private.h" -+#include -+#include -+ -+/* Last updated for v00.800 of the BG */ -+ -+/* Register offsets */ -+#define REG_QCSP_LIO_CFG(n) (0x0000 + ((n) * 0x10)) -+#define REG_QCSP_IO_CFG(n) (0x0004 + ((n) * 0x10)) -+#define REG_QCSP_DD_CFG(n) (0x000c + ((n) * 0x10)) -+#define REG_DD_CFG 0x0200 -+#define REG_DCP_CFG(n) (0x0300 + ((n) * 0x10)) -+#define REG_DCP_DD_CFG(n) (0x0304 + ((n) * 0x10)) -+#define REG_DCP_DLM_AVG(n) (0x030c + ((n) * 0x10)) -+#define REG_PFDR_FPC 0x0400 -+#define REG_PFDR_FP_HEAD 0x0404 -+#define REG_PFDR_FP_TAIL 0x0408 -+#define REG_PFDR_FP_LWIT 0x0410 -+#define REG_PFDR_CFG 0x0414 -+#define REG_SFDR_CFG 0x0500 -+#define REG_SFDR_IN_USE 0x0504 -+#define REG_WQ_CS_CFG(n) (0x0600 + ((n) * 0x04)) -+#define REG_WQ_DEF_ENC_WQID 0x0630 -+#define REG_WQ_SC_DD_CFG(n) (0x640 + ((n) * 0x04)) -+#define REG_WQ_PC_DD_CFG(n) (0x680 + ((n) * 0x04)) -+#define REG_WQ_DC0_DD_CFG(n) (0x6c0 + ((n) * 0x04)) -+#define REG_WQ_DC1_DD_CFG(n) (0x700 + ((n) * 0x04)) -+#define REG_WQ_DCn_DD_CFG(n) (0x6c0 + ((n) * 0x40)) /* n=2,3 */ -+#define REG_CM_CFG 0x0800 -+#define REG_ECSR 0x0a00 -+#define REG_ECIR 0x0a04 -+#define REG_EADR 0x0a08 -+#define REG_ECIR2 0x0a0c -+#define REG_EDATA(n) (0x0a10 + ((n) * 0x04)) -+#define REG_SBEC(n) (0x0a80 + ((n) * 0x04)) -+#define REG_MCR 0x0b00 -+#define REG_MCP(n) (0x0b04 + ((n) * 0x04)) -+#define REG_MISC_CFG 0x0be0 -+#define REG_HID_CFG 0x0bf0 -+#define REG_IDLE_STAT 0x0bf4 -+#define REG_IP_REV_1 0x0bf8 -+#define REG_IP_REV_2 0x0bfc -+#define REG_FQD_BARE 0x0c00 -+#define REG_PFDR_BARE 0x0c20 -+#define REG_offset_BAR 0x0004 /* relative to REG_[FQD|PFDR]_BARE */ -+#define REG_offset_AR 0x0010 /* relative to REG_[FQD|PFDR]_BARE */ -+#define REG_QCSP_BARE 0x0c80 -+#define REG_QCSP_BAR 0x0c84 -+#define REG_CI_SCHED_CFG 0x0d00 -+#define REG_SRCIDR 0x0d04 -+#define REG_LIODNR 0x0d08 -+#define REG_CI_RLM_AVG 0x0d14 -+#define REG_ERR_ISR 0x0e00 /* + "enum qm_isr_reg" */ -+#define REG_REV3_QCSP_LIO_CFG(n) (0x1000 + ((n) * 0x10)) -+#define REG_REV3_QCSP_IO_CFG(n) (0x1004 + ((n) * 0x10)) -+#define REG_REV3_QCSP_DD_CFG(n) (0x100c + ((n) * 0x10)) -+#define REG_CEETM_CFG_IDX 0x900 -+#define REG_CEETM_CFG_PRES 0x904 -+#define REG_CEETM_XSFDR_IN_USE 0x908 -+ -+/* Assists for QMAN_MCR */ -+#define MCR_INIT_PFDR 0x01000000 -+#define MCR_get_rslt(v) (u8)((v) >> 24) -+#define MCR_rslt_idle(r) (!rslt || (rslt >= 0xf0)) -+#define MCR_rslt_ok(r) (rslt == 0xf0) -+#define MCR_rslt_eaccess(r) (rslt == 0xf8) -+#define MCR_rslt_inval(r) (rslt == 0xff) -+ -+struct qman; -+ -+/* Follows WQ_CS_CFG0-5 */ -+enum qm_wq_class { -+ qm_wq_portal = 0, -+ qm_wq_pool = 1, -+ qm_wq_fman0 = 2, -+ qm_wq_fman1 = 3, -+ qm_wq_caam = 4, -+ qm_wq_pme = 5, -+ qm_wq_first = qm_wq_portal, -+ qm_wq_last = qm_wq_pme -+}; -+ -+/* Follows FQD_[BARE|BAR|AR] and PFDR_[BARE|BAR|AR] */ -+enum qm_memory { -+ qm_memory_fqd, -+ qm_memory_pfdr -+}; -+ -+/* Used by all error interrupt registers except 'inhibit' */ -+#define QM_EIRQ_CIDE 0x20000000 /* Corenet Initiator Data Error */ -+#define QM_EIRQ_CTDE 0x10000000 /* Corenet Target Data Error */ -+#define QM_EIRQ_CITT 0x08000000 /* Corenet Invalid Target Transaction */ -+#define QM_EIRQ_PLWI 0x04000000 /* PFDR Low Watermark */ -+#define QM_EIRQ_MBEI 0x02000000 /* Multi-bit ECC Error */ -+#define QM_EIRQ_SBEI 0x01000000 /* Single-bit ECC Error */ -+#define QM_EIRQ_PEBI 0x00800000 /* PFDR Enqueues Blocked Interrupt */ -+#define QM_EIRQ_IFSI 0x00020000 /* Invalid FQ Flow Control State */ -+#define QM_EIRQ_ICVI 0x00010000 /* Invalid Command Verb */ -+#define QM_EIRQ_IDDI 0x00000800 /* Invalid Dequeue (Direct-connect) */ -+#define QM_EIRQ_IDFI 0x00000400 /* Invalid Dequeue FQ */ -+#define QM_EIRQ_IDSI 0x00000200 /* Invalid Dequeue Source */ -+#define QM_EIRQ_IDQI 0x00000100 /* Invalid Dequeue Queue */ -+#define QM_EIRQ_IECE 0x00000010 /* Invalid Enqueue Configuration */ -+#define QM_EIRQ_IEOI 0x00000008 /* Invalid Enqueue Overflow */ -+#define QM_EIRQ_IESI 0x00000004 /* Invalid Enqueue State */ -+#define QM_EIRQ_IECI 0x00000002 /* Invalid Enqueue Channel */ -+#define QM_EIRQ_IEQI 0x00000001 /* Invalid Enqueue Queue */ -+ -+/* QMAN_ECIR valid error bit */ -+#define PORTAL_ECSR_ERR (QM_EIRQ_IEQI | QM_EIRQ_IESI | QM_EIRQ_IEOI | \ -+ QM_EIRQ_IDQI | QM_EIRQ_IDSI | QM_EIRQ_IDFI | \ -+ QM_EIRQ_IDDI | QM_EIRQ_ICVI | QM_EIRQ_IFSI) -+#define FQID_ECSR_ERR (QM_EIRQ_IEQI | QM_EIRQ_IECI | QM_EIRQ_IESI | \ -+ QM_EIRQ_IEOI | QM_EIRQ_IDQI | QM_EIRQ_IDFI | \ -+ QM_EIRQ_IFSI) -+ -+union qman_ecir { -+ u32 ecir_raw; -+ struct { -+ u32 __reserved:2; -+ u32 portal_type:1; -+ u32 portal_num:5; -+ u32 fqid:24; -+ } __packed info; -+}; -+ -+union qman_ecir2 { -+ u32 ecir2_raw; -+ struct { -+ u32 portal_type:1; -+ u32 __reserved:21; -+ u32 portal_num:10; -+ } __packed info; -+}; -+ -+union qman_eadr { -+ u32 eadr_raw; -+ struct { -+ u32 __reserved1:4; -+ u32 memid:4; -+ u32 __reserved2:12; -+ u32 eadr:12; -+ } __packed info; -+ struct { -+ u32 __reserved1:3; -+ u32 memid:5; -+ u32 __reserved:8; -+ u32 eadr:16; -+ } __packed info_rev3; -+}; -+ -+struct qman_hwerr_txt { -+ u32 mask; -+ const char *txt; -+}; -+ -+#define QMAN_HWE_TXT(a, b) { .mask = QM_EIRQ_##a, .txt = b } -+ -+static const struct qman_hwerr_txt qman_hwerr_txts[] = { -+ QMAN_HWE_TXT(CIDE, "Corenet Initiator Data Error"), -+ QMAN_HWE_TXT(CTDE, "Corenet Target Data Error"), -+ QMAN_HWE_TXT(CITT, "Corenet Invalid Target Transaction"), -+ QMAN_HWE_TXT(PLWI, "PFDR Low Watermark"), -+ QMAN_HWE_TXT(MBEI, "Multi-bit ECC Error"), -+ QMAN_HWE_TXT(SBEI, "Single-bit ECC Error"), -+ QMAN_HWE_TXT(PEBI, "PFDR Enqueues Blocked Interrupt"), -+ QMAN_HWE_TXT(ICVI, "Invalid Command Verb"), -+ QMAN_HWE_TXT(IFSI, "Invalid Flow Control State"), -+ QMAN_HWE_TXT(IDDI, "Invalid Dequeue (Direct-connect)"), -+ QMAN_HWE_TXT(IDFI, "Invalid Dequeue FQ"), -+ QMAN_HWE_TXT(IDSI, "Invalid Dequeue Source"), -+ QMAN_HWE_TXT(IDQI, "Invalid Dequeue Queue"), -+ QMAN_HWE_TXT(IECE, "Invalid Enqueue Configuration"), -+ QMAN_HWE_TXT(IEOI, "Invalid Enqueue Overflow"), -+ QMAN_HWE_TXT(IESI, "Invalid Enqueue State"), -+ QMAN_HWE_TXT(IECI, "Invalid Enqueue Channel"), -+ QMAN_HWE_TXT(IEQI, "Invalid Enqueue Queue") -+}; -+#define QMAN_HWE_COUNT (sizeof(qman_hwerr_txts)/sizeof(struct qman_hwerr_txt)) -+ -+struct qman_error_info_mdata { -+ u16 addr_mask; -+ u16 bits; -+ const char *txt; -+}; -+ -+#define QMAN_ERR_MDATA(a, b, c) { .addr_mask = a, .bits = b, .txt = c} -+static const struct qman_error_info_mdata error_mdata[] = { -+ QMAN_ERR_MDATA(0x01FF, 24, "FQD cache tag memory 0"), -+ QMAN_ERR_MDATA(0x01FF, 24, "FQD cache tag memory 1"), -+ QMAN_ERR_MDATA(0x01FF, 24, "FQD cache tag memory 2"), -+ QMAN_ERR_MDATA(0x01FF, 24, "FQD cache tag memory 3"), -+ QMAN_ERR_MDATA(0x0FFF, 512, "FQD cache memory"), -+ QMAN_ERR_MDATA(0x07FF, 128, "SFDR memory"), -+ QMAN_ERR_MDATA(0x01FF, 72, "WQ context memory"), -+ QMAN_ERR_MDATA(0x00FF, 240, "CGR memory"), -+ QMAN_ERR_MDATA(0x00FF, 302, "Internal Order Restoration List memory"), -+ QMAN_ERR_MDATA(0x01FF, 256, "SW portal ring memory"), -+ QMAN_ERR_MDATA(0x07FF, 181, "CEETM class queue descriptor memory"), -+ QMAN_ERR_MDATA(0x0FFF, 140, "CEETM extended SFDR memory"), -+ QMAN_ERR_MDATA(0x0FFF, 25, "CEETM logical FQ mapping memory"), -+ QMAN_ERR_MDATA(0x0FFF, 96, "CEETM dequeue context memory"), -+ QMAN_ERR_MDATA(0x07FF, 396, "CEETM ccgr memory"), -+ QMAN_ERR_MDATA(0x00FF, 146, "CEETM CQ channel shaping memory"), -+ QMAN_ERR_MDATA(0x007F, 256, "CEETM CQ channel scheduling memory"), -+ QMAN_ERR_MDATA(0x01FF, 88, "CEETM dequeue statistics memory"), -+}; -+#define QMAN_ERR_MDATA_COUNT \ -+ (sizeof(error_mdata)/sizeof(struct qman_error_info_mdata)) -+ -+/* Add this in Kconfig */ -+#define QMAN_ERRS_TO_UNENABLE (QM_EIRQ_PLWI | QM_EIRQ_PEBI) -+ -+/** -+ * qm_err_isr__ - Manipulate global interrupt registers -+ * @v: for accessors that write values, this is the 32-bit value -+ * -+ * Manipulates QMAN_ERR_ISR, QMAN_ERR_IER, QMAN_ERR_ISDR, QMAN_ERR_IIR. All -+ * manipulations except qm_err_isr_[un]inhibit() use 32-bit masks composed of -+ * the QM_EIRQ_*** definitions. Note that "qm_err_isr_enable_write" means -+ * "write the enable register" rather than "enable the write register"! -+ */ -+#define qm_err_isr_status_read(qm) \ -+ __qm_err_isr_read(qm, qm_isr_status) -+#define qm_err_isr_status_clear(qm, m) \ -+ __qm_err_isr_write(qm, qm_isr_status, m) -+#define qm_err_isr_enable_read(qm) \ -+ __qm_err_isr_read(qm, qm_isr_enable) -+#define qm_err_isr_enable_write(qm, v) \ -+ __qm_err_isr_write(qm, qm_isr_enable, v) -+#define qm_err_isr_disable_read(qm) \ -+ __qm_err_isr_read(qm, qm_isr_disable) -+#define qm_err_isr_disable_write(qm, v) \ -+ __qm_err_isr_write(qm, qm_isr_disable, v) -+#define qm_err_isr_inhibit(qm) \ -+ __qm_err_isr_write(qm, qm_isr_inhibit, 1) -+#define qm_err_isr_uninhibit(qm) \ -+ __qm_err_isr_write(qm, qm_isr_inhibit, 0) -+ -+/* -+ * TODO: unimplemented registers -+ * -+ * Keeping a list here of Qman registers I have not yet covered; -+ * QCSP_DD_IHRSR, QCSP_DD_IHRFR, QCSP_DD_HASR, -+ * DCP_DD_IHRSR, DCP_DD_IHRFR, DCP_DD_HASR, CM_CFG, -+ * QMAN_EECC, QMAN_SBET, QMAN_EINJ, QMAN_SBEC0-12 -+ */ -+ -+/* Encapsulate "struct qman *" as a cast of the register space address. */ -+ -+static struct qman *qm_create(void *regs) -+{ -+ return (struct qman *)regs; -+} -+ -+static inline u32 __qm_in(struct qman *qm, u32 offset) -+{ -+ return in_be32((void *)qm + offset); -+} -+static inline void __qm_out(struct qman *qm, u32 offset, u32 val) -+{ -+ out_be32((void *)qm + offset, val); -+} -+#define qm_in(reg) __qm_in(qm, REG_##reg) -+#define qm_out(reg, val) __qm_out(qm, REG_##reg, val) -+ -+static u32 __qm_err_isr_read(struct qman *qm, enum qm_isr_reg n) -+{ -+ return __qm_in(qm, REG_ERR_ISR + (n << 2)); -+} -+ -+static void __qm_err_isr_write(struct qman *qm, enum qm_isr_reg n, u32 val) -+{ -+ __qm_out(qm, REG_ERR_ISR + (n << 2), val); -+} -+ -+static void qm_set_dc(struct qman *qm, enum qm_dc_portal portal, -+ int ed, u8 sernd) -+{ -+ DPA_ASSERT(!ed || (portal == qm_dc_portal_fman0) || -+ (portal == qm_dc_portal_fman1)); -+ if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) -+ qm_out(DCP_CFG(portal), (ed ? 0x1000 : 0) | (sernd & 0x3ff)); -+ else -+ qm_out(DCP_CFG(portal), (ed ? 0x100 : 0) | (sernd & 0x1f)); -+} -+ -+static void qm_set_wq_scheduling(struct qman *qm, enum qm_wq_class wq_class, -+ u8 cs_elev, u8 csw2, u8 csw3, u8 csw4, u8 csw5, -+ u8 csw6, u8 csw7) -+{ -+ qm_out(WQ_CS_CFG(wq_class), ((cs_elev & 0xff) << 24) | -+ ((csw2 & 0x7) << 20) | ((csw3 & 0x7) << 16) | -+ ((csw4 & 0x7) << 12) | ((csw5 & 0x7) << 8) | -+ ((csw6 & 0x7) << 4) | (csw7 & 0x7)); -+} -+ -+static void qm_set_hid(struct qman *qm) -+{ -+ qm_out(HID_CFG, 0); -+} -+ -+static void qm_set_corenet_initiator(struct qman *qm) -+{ -+ qm_out(CI_SCHED_CFG, -+ 0x80000000 | /* write srcciv enable */ -+ (CONFIG_FSL_QMAN_CI_SCHED_CFG_SRCCIV << 24) | -+ (CONFIG_FSL_QMAN_CI_SCHED_CFG_SRQ_W << 8) | -+ (CONFIG_FSL_QMAN_CI_SCHED_CFG_RW_W << 4) | -+ CONFIG_FSL_QMAN_CI_SCHED_CFG_BMAN_W); -+} -+ -+static void qm_get_version(struct qman *qm, u16 *id, u8 *major, u8 *minor, -+ u8 *cfg) -+{ -+ u32 v = qm_in(IP_REV_1); -+ u32 v2 = qm_in(IP_REV_2); -+ *id = (v >> 16); -+ *major = (v >> 8) & 0xff; -+ *minor = v & 0xff; -+ *cfg = v2 & 0xff; -+} -+ -+static void qm_set_memory(struct qman *qm, enum qm_memory memory, u64 ba, -+ int enable, int prio, int stash, u32 size) -+{ -+ u32 offset = (memory == qm_memory_fqd) ? REG_FQD_BARE : REG_PFDR_BARE; -+ u32 exp = ilog2(size); -+ /* choke if size isn't within range */ -+ DPA_ASSERT((size >= 4096) && (size <= 1073741824) && -+ is_power_of_2(size)); -+ /* choke if 'ba' has lower-alignment than 'size' */ -+ DPA_ASSERT(!(ba & (size - 1))); -+ __qm_out(qm, offset, upper_32_bits(ba)); -+ __qm_out(qm, offset + REG_offset_BAR, lower_32_bits(ba)); -+ __qm_out(qm, offset + REG_offset_AR, -+ (enable ? 0x80000000 : 0) | -+ (prio ? 0x40000000 : 0) | -+ (stash ? 0x20000000 : 0) | -+ (exp - 1)); -+} -+ -+static void qm_set_pfdr_threshold(struct qman *qm, u32 th, u8 k) -+{ -+ qm_out(PFDR_FP_LWIT, th & 0xffffff); -+ qm_out(PFDR_CFG, k); -+} -+ -+static void qm_set_sfdr_threshold(struct qman *qm, u16 th) -+{ -+ qm_out(SFDR_CFG, th & 0x3ff); -+} -+ -+static int qm_init_pfdr(struct qman *qm, u32 pfdr_start, u32 num) -+{ -+ u8 rslt = MCR_get_rslt(qm_in(MCR)); -+ -+ DPA_ASSERT(pfdr_start && !(pfdr_start & 7) && !(num & 7) && num); -+ /* Make sure the command interface is 'idle' */ -+ if (!MCR_rslt_idle(rslt)) -+ panic("QMAN_MCR isn't idle"); -+ -+ /* Write the MCR command params then the verb */ -+ qm_out(MCP(0), pfdr_start); -+ /* TODO: remove this - it's a workaround for a model bug that is -+ * corrected in more recent versions. We use the workaround until -+ * everyone has upgraded. */ -+ qm_out(MCP(1), (pfdr_start + num - 16)); -+ lwsync(); -+ qm_out(MCR, MCR_INIT_PFDR); -+ /* Poll for the result */ -+ do { -+ rslt = MCR_get_rslt(qm_in(MCR)); -+ } while (!MCR_rslt_idle(rslt)); -+ if (MCR_rslt_ok(rslt)) -+ return 0; -+ if (MCR_rslt_eaccess(rslt)) -+ return -EACCES; -+ if (MCR_rslt_inval(rslt)) -+ return -EINVAL; -+ pr_crit("Unexpected result from MCR_INIT_PFDR: %02x\n", rslt); -+ return -ENOSYS; -+} -+ -+/*****************/ -+/* Config driver */ -+/*****************/ -+ -+#define DEFAULT_FQD_SZ (PAGE_SIZE << CONFIG_FSL_QMAN_FQD_SZ) -+#define DEFAULT_PFDR_SZ (PAGE_SIZE << CONFIG_FSL_QMAN_PFDR_SZ) -+ -+/* We support only one of these */ -+static struct qman *qm; -+static struct device_node *qm_node; -+ -+/* And this state belongs to 'qm'. It is set during fsl_qman_init(), but used -+ * during qman_init_ccsr(). */ -+static dma_addr_t fqd_a, pfdr_a; -+static size_t fqd_sz = DEFAULT_FQD_SZ, pfdr_sz = DEFAULT_PFDR_SZ; -+ -+static int qman_fqd(struct reserved_mem *rmem) -+{ -+ fqd_a = rmem->base; -+ fqd_sz = rmem->size; -+ -+ WARN_ON(!(fqd_a && fqd_sz)); -+ -+ return 0; -+} -+RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd); -+ -+static int qman_pfdr(struct reserved_mem *rmem) -+{ -+ pfdr_a = rmem->base; -+ pfdr_sz = rmem->size; -+ -+ WARN_ON(!(pfdr_a && pfdr_sz)); -+ -+ return 0; -+} -+RESERVEDMEM_OF_DECLARE(qman_fbpr, "fsl,qman-pfdr", qman_pfdr); -+ -+size_t get_qman_fqd_size() -+{ -+ return fqd_sz; -+} -+ -+/* Parse the property to extract the memory location and size and -+ * memblock_reserve() it. If it isn't supplied, memblock_alloc() the default -+ * size. Also flush this memory range from data cache so that QMAN originated -+ * transactions for this memory region could be marked non-coherent. -+ */ -+static __init int parse_mem_property(struct device_node *node, const char *name, -+ dma_addr_t *addr, size_t *sz, int zero) -+{ -+ int ret; -+ -+ /* If using a "zero-pma", don't try to zero it, even if you asked */ -+ if (zero && of_find_property(node, "zero-pma", &ret)) { -+ pr_info(" it's a 'zero-pma', not zeroing from s/w\n"); -+ zero = 0; -+ } -+ -+ if (zero) { -+ /* map as cacheable, non-guarded */ -+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) -+ void __iomem *tmpp = ioremap_cache(*addr, *sz); -+#else -+ void __iomem *tmpp = ioremap(*addr, *sz); -+#endif -+ -+ if (!tmpp) -+ return -ENOMEM; -+ memset_io(tmpp, 0, *sz); -+ flush_dcache_range((unsigned long)tmpp, -+ (unsigned long)tmpp + *sz); -+ iounmap(tmpp); -+ } -+ -+ return 0; -+} -+ -+/* TODO: -+ * - there is obviously no handling of errors, -+ * - the calls to qm_set_memory() hard-code the priority and CPC-stashing for -+ * both memory resources to zero. -+ */ -+static int __init fsl_qman_init(struct device_node *node) -+{ -+ struct resource res; -+ resource_size_t len; -+ u32 __iomem *regs; -+ const char *s; -+ int ret, standby = 0; -+ u16 id; -+ u8 major, minor, cfg; -+ ret = of_address_to_resource(node, 0, &res); -+ if (ret) { -+ pr_err("Can't get %s property '%s'\n", node->full_name, "reg"); -+ return ret; -+ } -+ s = of_get_property(node, "fsl,hv-claimable", &ret); -+ if (s && !strcmp(s, "standby")) -+ standby = 1; -+ if (!standby) { -+ ret = parse_mem_property(node, "fsl,qman-fqd", -+ &fqd_a, &fqd_sz, 1); -+ pr_info("qman-fqd addr 0x%llx size 0x%zx\n", -+ (unsigned long long)fqd_a, fqd_sz); -+ BUG_ON(ret); -+ ret = parse_mem_property(node, "fsl,qman-pfdr", -+ &pfdr_a, &pfdr_sz, 0); -+ pr_info("qman-pfdr addr 0x%llx size 0x%zx\n", -+ (unsigned long long)pfdr_a, pfdr_sz); -+ BUG_ON(ret); -+ } -+ /* Global configuration */ -+ len = resource_size(&res); -+ if (len != (unsigned long)len) -+ return -EINVAL; -+ regs = ioremap(res.start, (unsigned long)len); -+ qm = qm_create(regs); -+ qm_node = node; -+ qm_get_version(qm, &id, &major, &minor, &cfg); -+ pr_info("Qman ver:%04x,%02x,%02x,%02x\n", id, major, minor, cfg); -+ if (!qman_ip_rev) { -+ if ((major == 1) && (minor == 0)) { -+ pr_err("QMAN rev1.0 on P4080 rev1 is not supported!\n"); -+ iounmap(regs); -+ return -ENODEV; -+ } else if ((major == 1) && (minor == 1)) -+ qman_ip_rev = QMAN_REV11; -+ else if ((major == 1) && (minor == 2)) -+ qman_ip_rev = QMAN_REV12; -+ else if ((major == 2) && (minor == 0)) -+ qman_ip_rev = QMAN_REV20; -+ else if ((major == 3) && (minor == 0)) -+ qman_ip_rev = QMAN_REV30; -+ else if ((major == 3) && (minor == 1)) -+ qman_ip_rev = QMAN_REV31; -+ else if ((major == 3) && (minor == 2)) -+ qman_ip_rev = QMAN_REV32; -+ else { -+ pr_warn("unknown Qman version, default to rev1.1\n"); -+ qman_ip_rev = QMAN_REV11; -+ } -+ qman_ip_cfg = cfg; -+ } -+ -+ if (standby) { -+ pr_info(" -> in standby mode\n"); -+ return 0; -+ } -+ return 0; -+} -+ -+int qman_have_ccsr(void) -+{ -+ return qm ? 1 : 0; -+} -+ -+__init int qman_init_early(void) -+{ -+ struct device_node *dn; -+ int ret; -+ -+ for_each_compatible_node(dn, NULL, "fsl,qman") { -+ if (qm) -+ pr_err("%s: only one 'fsl,qman' allowed\n", -+ dn->full_name); -+ else { -+ if (!of_device_is_available(dn)) -+ continue; -+ -+ ret = fsl_qman_init(dn); -+ BUG_ON(ret); -+ } -+ } -+ return 0; -+} -+postcore_initcall_sync(qman_init_early); -+ -+static void log_edata_bits(u32 bit_count) -+{ -+ u32 i, j, mask = 0xffffffff; -+ -+ pr_warn("Qman ErrInt, EDATA:\n"); -+ i = bit_count/32; -+ if (bit_count%32) { -+ i++; -+ mask = ~(mask << bit_count%32); -+ } -+ j = 16-i; -+ pr_warn(" 0x%08x\n", qm_in(EDATA(j)) & mask); -+ j++; -+ for (; j < 16; j++) -+ pr_warn(" 0x%08x\n", qm_in(EDATA(j))); -+} -+ -+static void log_additional_error_info(u32 isr_val, u32 ecsr_val) -+{ -+ union qman_ecir ecir_val; -+ union qman_eadr eadr_val; -+ -+ ecir_val.ecir_raw = qm_in(ECIR); -+ /* Is portal info valid */ -+ if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) { -+ union qman_ecir2 ecir2_val; -+ ecir2_val.ecir2_raw = qm_in(ECIR2); -+ if (ecsr_val & PORTAL_ECSR_ERR) { -+ pr_warn("Qman ErrInt: %s id %d\n", -+ (ecir2_val.info.portal_type) ? -+ "DCP" : "SWP", ecir2_val.info.portal_num); -+ } -+ if (ecsr_val & (FQID_ECSR_ERR | QM_EIRQ_IECE)) { -+ pr_warn("Qman ErrInt: ecir.fqid 0x%x\n", -+ ecir_val.info.fqid); -+ } -+ if (ecsr_val & (QM_EIRQ_SBEI|QM_EIRQ_MBEI)) { -+ eadr_val.eadr_raw = qm_in(EADR); -+ pr_warn("Qman ErrInt: EADR Memory: %s, 0x%x\n", -+ error_mdata[eadr_val.info_rev3.memid].txt, -+ error_mdata[eadr_val.info_rev3.memid].addr_mask -+ & eadr_val.info_rev3.eadr); -+ log_edata_bits( -+ error_mdata[eadr_val.info_rev3.memid].bits); -+ } -+ } else { -+ if (ecsr_val & PORTAL_ECSR_ERR) { -+ pr_warn("Qman ErrInt: %s id %d\n", -+ (ecir_val.info.portal_type) ? -+ "DCP" : "SWP", ecir_val.info.portal_num); -+ } -+ if (ecsr_val & FQID_ECSR_ERR) { -+ pr_warn("Qman ErrInt: ecir.fqid 0x%x\n", -+ ecir_val.info.fqid); -+ } -+ if (ecsr_val & (QM_EIRQ_SBEI|QM_EIRQ_MBEI)) { -+ eadr_val.eadr_raw = qm_in(EADR); -+ pr_warn("Qman ErrInt: EADR Memory: %s, 0x%x\n", -+ error_mdata[eadr_val.info.memid].txt, -+ error_mdata[eadr_val.info.memid].addr_mask -+ & eadr_val.info.eadr); -+ log_edata_bits(error_mdata[eadr_val.info.memid].bits); -+ } -+ } -+} -+ -+/* Qman interrupt handler */ -+static irqreturn_t qman_isr(int irq, void *ptr) -+{ -+ u32 isr_val, ier_val, ecsr_val, isr_mask, i; -+ -+ ier_val = qm_err_isr_enable_read(qm); -+ isr_val = qm_err_isr_status_read(qm); -+ ecsr_val = qm_in(ECSR); -+ isr_mask = isr_val & ier_val; -+ -+ if (!isr_mask) -+ return IRQ_NONE; -+ for (i = 0; i < QMAN_HWE_COUNT; i++) { -+ if (qman_hwerr_txts[i].mask & isr_mask) { -+ pr_warn("Qman ErrInt: %s\n", qman_hwerr_txts[i].txt); -+ if (qman_hwerr_txts[i].mask & ecsr_val) { -+ log_additional_error_info(isr_mask, ecsr_val); -+ /* Re-arm error capture registers */ -+ qm_out(ECSR, ecsr_val); -+ } -+ if (qman_hwerr_txts[i].mask & QMAN_ERRS_TO_UNENABLE) { -+ pr_devel("Qman un-enabling error 0x%x\n", -+ qman_hwerr_txts[i].mask); -+ ier_val &= ~qman_hwerr_txts[i].mask; -+ qm_err_isr_enable_write(qm, ier_val); -+ } -+ } -+ } -+ qm_err_isr_status_clear(qm, isr_val); -+ return IRQ_HANDLED; -+} -+ -+static int __bind_irq(void) -+{ -+ int ret, err_irq; -+ -+ err_irq = of_irq_to_resource(qm_node, 0, NULL); -+ if (err_irq == 0) { -+ pr_info("Can't get %s property '%s'\n", qm_node->full_name, -+ "interrupts"); -+ return -ENODEV; -+ } -+ ret = request_irq(err_irq, qman_isr, IRQF_SHARED, "qman-err", qm_node); -+ if (ret) { -+ pr_err("request_irq() failed %d for '%s'\n", ret, -+ qm_node->full_name); -+ return -ENODEV; -+ } -+ /* Write-to-clear any stale bits, (eg. starvation being asserted prior -+ * to resource allocation during driver init). */ -+ qm_err_isr_status_clear(qm, 0xffffffff); -+ /* Enable Error Interrupts */ -+ qm_err_isr_enable_write(qm, 0xffffffff); -+ return 0; -+} -+ -+int qman_init_ccsr(struct device_node *node) -+{ -+ int ret; -+ if (!qman_have_ccsr()) -+ return 0; -+ if (node != qm_node) -+ return -EINVAL; -+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) -+ /* TEMP for LS1043 : should be done in uboot */ -+ qm_out(QCSP_BARE, 0x5); -+ qm_out(QCSP_BAR, 0x0); -+#endif -+ /* FQD memory */ -+ qm_set_memory(qm, qm_memory_fqd, fqd_a, 1, 0, 0, fqd_sz); -+ /* PFDR memory */ -+ qm_set_memory(qm, qm_memory_pfdr, pfdr_a, 1, 0, 0, pfdr_sz); -+ qm_init_pfdr(qm, 8, pfdr_sz / 64 - 8); -+ /* thresholds */ -+ qm_set_pfdr_threshold(qm, 512, 64); -+ qm_set_sfdr_threshold(qm, 128); -+ /* clear stale PEBI bit from interrupt status register */ -+ qm_err_isr_status_clear(qm, QM_EIRQ_PEBI); -+ /* corenet initiator settings */ -+ qm_set_corenet_initiator(qm); -+ /* HID settings */ -+ qm_set_hid(qm); -+ /* Set scheduling weights to defaults */ -+ for (ret = qm_wq_first; ret <= qm_wq_last; ret++) -+ qm_set_wq_scheduling(qm, ret, 0, 0, 0, 0, 0, 0, 0); -+ /* We are not prepared to accept ERNs for hardware enqueues */ -+ qm_set_dc(qm, qm_dc_portal_fman0, 1, 0); -+ qm_set_dc(qm, qm_dc_portal_fman1, 1, 0); -+ /* Initialise Error Interrupt Handler */ -+ ret = __bind_irq(); -+ if (ret) -+ return ret; -+ return 0; -+} -+ -+#define LIO_CFG_LIODN_MASK 0x0fff0000 -+void qman_liodn_fixup(u16 channel) -+{ -+ static int done; -+ static u32 liodn_offset; -+ u32 before, after; -+ int idx = channel - QM_CHANNEL_SWPORTAL0; -+ -+ if (!qman_have_ccsr()) -+ return; -+ if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) -+ before = qm_in(REV3_QCSP_LIO_CFG(idx)); -+ else -+ before = qm_in(QCSP_LIO_CFG(idx)); -+ if (!done) { -+ liodn_offset = before & LIO_CFG_LIODN_MASK; -+ done = 1; -+ return; -+ } -+ after = (before & (~LIO_CFG_LIODN_MASK)) | liodn_offset; -+ if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) -+ qm_out(REV3_QCSP_LIO_CFG(idx), after); -+ else -+ qm_out(QCSP_LIO_CFG(idx), after); -+} -+ -+#define IO_CFG_SDEST_MASK 0x00ff0000 -+int qman_set_sdest(u16 channel, unsigned int cpu_idx) -+{ -+ int idx = channel - QM_CHANNEL_SWPORTAL0; -+ u32 before, after; -+ -+ if (!qman_have_ccsr()) -+ return -ENODEV; -+ if ((qman_ip_rev & 0xFF00) == QMAN_REV31) { -+ /* LS1043A - only one L2 cache */ -+ cpu_idx = 0; -+ } -+ -+ if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) { -+ before = qm_in(REV3_QCSP_IO_CFG(idx)); -+ /* Each pair of vcpu share the same SRQ(SDEST) */ -+ cpu_idx /= 2; -+ after = (before & (~IO_CFG_SDEST_MASK)) | (cpu_idx << 16); -+ qm_out(REV3_QCSP_IO_CFG(idx), after); -+ } else { -+ before = qm_in(QCSP_IO_CFG(idx)); -+ after = (before & (~IO_CFG_SDEST_MASK)) | (cpu_idx << 16); -+ qm_out(QCSP_IO_CFG(idx), after); -+ } -+ return 0; -+} -+ -+#define MISC_CFG_WPM_MASK 0x00000002 -+int qm_set_wpm(int wpm) -+{ -+ u32 before; -+ u32 after; -+ -+ if (!qman_have_ccsr()) -+ return -ENODEV; -+ -+ before = qm_in(MISC_CFG); -+ after = (before & (~MISC_CFG_WPM_MASK)) | (wpm << 1); -+ qm_out(MISC_CFG, after); -+ return 0; -+} -+ -+int qm_get_wpm(int *wpm) -+{ -+ u32 before; -+ -+ if (!qman_have_ccsr()) -+ return -ENODEV; -+ -+ before = qm_in(MISC_CFG); -+ *wpm = (before & MISC_CFG_WPM_MASK) >> 1; -+ return 0; -+} -+ -+/* CEETM_CFG_PRES register has PRES field which is calculated by: -+ * PRES = (2^22 / credit update reference period) * QMan clock period -+ * = (2^22 * 10^9)/ CONFIG_QMAN_CEETM_UPDATE_PERIOD) / qman_clk -+ */ -+ -+int qman_ceetm_set_prescaler(enum qm_dc_portal portal) -+{ -+ u64 temp; -+ u16 pres; -+ -+ if (!qman_have_ccsr()) -+ return -ENODEV; -+ -+ temp = 0x400000 * 100; -+ do_div(temp, CONFIG_QMAN_CEETM_UPDATE_PERIOD); -+ temp *= 10000000; -+ do_div(temp, qman_clk); -+ pres = (u16) temp; -+ qm_out(CEETM_CFG_IDX, portal); -+ qm_out(CEETM_CFG_PRES, pres); -+ return 0; -+} -+ -+int qman_ceetm_get_prescaler(u16 *pres) -+{ -+ if (!qman_have_ccsr()) -+ return -ENODEV; -+ *pres = (u16)qm_in(CEETM_CFG_PRES); -+ return 0; -+} -+ -+#define DCP_CFG_CEETME_MASK 0xFFFF0000 -+#define QM_SP_ENABLE_CEETM(n) (0x80000000 >> (n)) -+int qman_sp_enable_ceetm_mode(enum qm_dc_portal portal, u16 sub_portal) -+{ -+ u32 dcp_cfg; -+ -+ if (!qman_have_ccsr()) -+ return -ENODEV; -+ -+ dcp_cfg = qm_in(DCP_CFG(portal)); -+ dcp_cfg |= QM_SP_ENABLE_CEETM(sub_portal); -+ qm_out(DCP_CFG(portal), dcp_cfg); -+ return 0; -+} -+ -+int qman_sp_disable_ceetm_mode(enum qm_dc_portal portal, u16 sub_portal) -+{ -+ u32 dcp_cfg; -+ -+ if (!qman_have_ccsr()) -+ return -ENODEV; -+ dcp_cfg = qm_in(DCP_CFG(portal)); -+ dcp_cfg &= ~(QM_SP_ENABLE_CEETM(sub_portal)); -+ qm_out(DCP_CFG(portal), dcp_cfg); -+ return 0; -+} -+ -+int qman_ceetm_get_xsfdr(enum qm_dc_portal portal, unsigned int *num) -+{ -+ if (!qman_have_ccsr()) -+ return -ENODEV; -+ *num = qm_in(CEETM_XSFDR_IN_USE); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_get_xsfdr); -+ -+#ifdef CONFIG_SYSFS -+ -+#define DRV_NAME "fsl-qman" -+#define DCP_MAX_ID 3 -+#define DCP_MIN_ID 0 -+ -+static ssize_t show_pfdr_fpc(struct device *dev, -+ struct device_attribute *dev_attr, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%u\n", qm_in(PFDR_FPC)); -+}; -+ -+static ssize_t show_dlm_avg(struct device *dev, -+ struct device_attribute *dev_attr, char *buf) -+{ -+ u32 data; -+ int i; -+ -+ if (!sscanf(dev_attr->attr.name, "dcp%d_dlm_avg", &i)) -+ return -EINVAL; -+ if (i < DCP_MIN_ID || i > DCP_MAX_ID) -+ return -EINVAL; -+ data = qm_in(DCP_DLM_AVG(i)); -+ return snprintf(buf, PAGE_SIZE, "%d.%08d\n", data>>8, -+ (data & 0x000000ff)*390625); -+}; -+ -+static ssize_t set_dlm_avg(struct device *dev, -+ struct device_attribute *dev_attr, const char *buf, size_t count) -+{ -+ unsigned long val; -+ int i; -+ -+ if (!sscanf(dev_attr->attr.name, "dcp%d_dlm_avg", &i)) -+ return -EINVAL; -+ if (i < DCP_MIN_ID || i > DCP_MAX_ID) -+ return -EINVAL; -+ if (kstrtoul(buf, 0, &val)) { -+ dev_dbg(dev, "invalid input %s\n", buf); -+ return -EINVAL; -+ } -+ qm_out(DCP_DLM_AVG(i), val); -+ return count; -+}; -+ -+static ssize_t show_pfdr_cfg(struct device *dev, -+ struct device_attribute *dev_attr, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%u\n", qm_in(PFDR_CFG)); -+}; -+ -+static ssize_t set_pfdr_cfg(struct device *dev, -+ struct device_attribute *dev_attr, const char *buf, size_t count) -+{ -+ unsigned long val; -+ -+ if (kstrtoul(buf, 0, &val)) { -+ dev_dbg(dev, "invalid input %s\n", buf); -+ return -EINVAL; -+ } -+ qm_out(PFDR_CFG, val); -+ return count; -+}; -+ -+static ssize_t show_sfdr_in_use(struct device *dev, -+ struct device_attribute *dev_attr, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%u\n", qm_in(SFDR_IN_USE)); -+}; -+ -+static ssize_t show_idle_stat(struct device *dev, -+ struct device_attribute *dev_attr, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%u\n", qm_in(IDLE_STAT)); -+}; -+ -+static ssize_t show_ci_rlm_avg(struct device *dev, -+ struct device_attribute *dev_attr, char *buf) -+{ -+ u32 data = qm_in(CI_RLM_AVG); -+ return snprintf(buf, PAGE_SIZE, "%d.%08d\n", data>>8, -+ (data & 0x000000ff)*390625); -+}; -+ -+static ssize_t set_ci_rlm_avg(struct device *dev, -+ struct device_attribute *dev_attr, const char *buf, size_t count) -+{ -+ unsigned long val; -+ -+ if (kstrtoul(buf, 0, &val)) { -+ dev_dbg(dev, "invalid input %s\n", buf); -+ return -EINVAL; -+ } -+ qm_out(CI_RLM_AVG, val); -+ return count; -+}; -+ -+static ssize_t show_err_isr(struct device *dev, -+ struct device_attribute *dev_attr, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "0x%08x\n", qm_in(ERR_ISR)); -+}; -+ -+#define SBEC_MAX_ID 14 -+#define SBEC_MIN_ID 0 -+ -+static ssize_t show_sbec(struct device *dev, -+ struct device_attribute *dev_attr, char *buf) -+{ -+ int i; -+ -+ if (!sscanf(dev_attr->attr.name, "sbec_%d", &i)) -+ return -EINVAL; -+ if (i < SBEC_MIN_ID || i > SBEC_MAX_ID) -+ return -EINVAL; -+ return snprintf(buf, PAGE_SIZE, "%u\n", qm_in(SBEC(i))); -+}; -+ -+static DEVICE_ATTR(pfdr_fpc, S_IRUSR, show_pfdr_fpc, NULL); -+static DEVICE_ATTR(pfdr_cfg, S_IRUSR, show_pfdr_cfg, set_pfdr_cfg); -+static DEVICE_ATTR(idle_stat, S_IRUSR, show_idle_stat, NULL); -+static DEVICE_ATTR(ci_rlm_avg, (S_IRUSR|S_IWUSR), -+ show_ci_rlm_avg, set_ci_rlm_avg); -+static DEVICE_ATTR(err_isr, S_IRUSR, show_err_isr, NULL); -+static DEVICE_ATTR(sfdr_in_use, S_IRUSR, show_sfdr_in_use, NULL); -+ -+static DEVICE_ATTR(dcp0_dlm_avg, (S_IRUSR|S_IWUSR), show_dlm_avg, set_dlm_avg); -+static DEVICE_ATTR(dcp1_dlm_avg, (S_IRUSR|S_IWUSR), show_dlm_avg, set_dlm_avg); -+static DEVICE_ATTR(dcp2_dlm_avg, (S_IRUSR|S_IWUSR), show_dlm_avg, set_dlm_avg); -+static DEVICE_ATTR(dcp3_dlm_avg, (S_IRUSR|S_IWUSR), show_dlm_avg, set_dlm_avg); -+ -+static DEVICE_ATTR(sbec_0, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_1, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_2, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_3, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_4, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_5, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_6, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_7, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_8, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_9, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_10, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_11, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_12, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_13, S_IRUSR, show_sbec, NULL); -+static DEVICE_ATTR(sbec_14, S_IRUSR, show_sbec, NULL); -+ -+static struct attribute *qman_dev_attributes[] = { -+ &dev_attr_pfdr_fpc.attr, -+ &dev_attr_pfdr_cfg.attr, -+ &dev_attr_idle_stat.attr, -+ &dev_attr_ci_rlm_avg.attr, -+ &dev_attr_err_isr.attr, -+ &dev_attr_dcp0_dlm_avg.attr, -+ &dev_attr_dcp1_dlm_avg.attr, -+ &dev_attr_dcp2_dlm_avg.attr, -+ &dev_attr_dcp3_dlm_avg.attr, -+ /* sfdr_in_use will be added if necessary */ -+ NULL -+}; -+ -+static struct attribute *qman_dev_ecr_attributes[] = { -+ &dev_attr_sbec_0.attr, -+ &dev_attr_sbec_1.attr, -+ &dev_attr_sbec_2.attr, -+ &dev_attr_sbec_3.attr, -+ &dev_attr_sbec_4.attr, -+ &dev_attr_sbec_5.attr, -+ &dev_attr_sbec_6.attr, -+ &dev_attr_sbec_7.attr, -+ &dev_attr_sbec_8.attr, -+ &dev_attr_sbec_9.attr, -+ &dev_attr_sbec_10.attr, -+ &dev_attr_sbec_11.attr, -+ &dev_attr_sbec_12.attr, -+ &dev_attr_sbec_13.attr, -+ &dev_attr_sbec_14.attr, -+ NULL -+}; -+ -+/* root level */ -+static const struct attribute_group qman_dev_attr_grp = { -+ .name = NULL, -+ .attrs = qman_dev_attributes -+}; -+static const struct attribute_group qman_dev_ecr_grp = { -+ .name = "error_capture", -+ .attrs = qman_dev_ecr_attributes -+}; -+ -+static int of_fsl_qman_remove(struct platform_device *ofdev) -+{ -+ sysfs_remove_group(&ofdev->dev.kobj, &qman_dev_attr_grp); -+ return 0; -+}; -+ -+static int of_fsl_qman_probe(struct platform_device *ofdev) -+{ -+ int ret; -+ -+ ret = sysfs_create_group(&ofdev->dev.kobj, &qman_dev_attr_grp); -+ if (ret) -+ goto done; -+ ret = sysfs_add_file_to_group(&ofdev->dev.kobj, -+ &dev_attr_sfdr_in_use.attr, qman_dev_attr_grp.name); -+ if (ret) -+ goto del_group_0; -+ ret = sysfs_create_group(&ofdev->dev.kobj, &qman_dev_ecr_grp); -+ if (ret) -+ goto del_group_0; -+ -+ goto done; -+ -+del_group_0: -+ sysfs_remove_group(&ofdev->dev.kobj, &qman_dev_attr_grp); -+done: -+ if (ret) -+ dev_err(&ofdev->dev, -+ "Cannot create dev attributes ret=%d\n", ret); -+ return ret; -+}; -+ -+static struct of_device_id of_fsl_qman_ids[] = { -+ { -+ .compatible = "fsl,qman", -+ }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, of_fsl_qman_ids); -+ -+#ifdef CONFIG_SUSPEND -+ -+static u32 saved_isdr; -+static int qman_pm_suspend_noirq(struct device *dev) -+{ -+ uint32_t idle_state; -+ -+ suspend_unused_qportal(); -+ /* save isdr, disable all, clear isr */ -+ saved_isdr = qm_err_isr_disable_read(qm); -+ qm_err_isr_disable_write(qm, 0xffffffff); -+ qm_err_isr_status_clear(qm, 0xffffffff); -+ idle_state = qm_in(IDLE_STAT); -+ if (!(idle_state & 0x1)) { -+ pr_err("Qman not idle 0x%x aborting\n", idle_state); -+ qm_err_isr_disable_write(qm, saved_isdr); -+ resume_unused_qportal(); -+ return -EBUSY; -+ } -+#ifdef CONFIG_PM_DEBUG -+ pr_info("Qman suspend code, IDLE_STAT = 0x%x\n", idle_state); -+#endif -+ return 0; -+} -+ -+static int qman_pm_resume_noirq(struct device *dev) -+{ -+ /* restore isdr */ -+ qm_err_isr_disable_write(qm, saved_isdr); -+ resume_unused_qportal(); -+ return 0; -+} -+#else -+#define qman_pm_suspend_noirq NULL -+#define qman_pm_resume_noirq NULL -+#endif -+ -+static const struct dev_pm_ops qman_pm_ops = { -+ .suspend_noirq = qman_pm_suspend_noirq, -+ .resume_noirq = qman_pm_resume_noirq, -+}; -+ -+static struct platform_driver of_fsl_qman_driver = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = DRV_NAME, -+ .of_match_table = of_fsl_qman_ids, -+ .pm = &qman_pm_ops, -+ }, -+ .probe = of_fsl_qman_probe, -+ .remove = of_fsl_qman_remove, -+}; -+ -+static int qman_ctrl_init(void) -+{ -+ return platform_driver_register(&of_fsl_qman_driver); -+} -+ -+static void qman_ctrl_exit(void) -+{ -+ platform_driver_unregister(&of_fsl_qman_driver); -+} -+ -+module_init(qman_ctrl_init); -+module_exit(qman_ctrl_exit); -+ -+#endif /* CONFIG_SYSFS */ ---- /dev/null -+++ b/drivers/staging/fsl_qbman/qman_debugfs.c -@@ -0,0 +1,1594 @@ -+/* Copyright 2010-2011 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include "qman_private.h" -+ -+#define MAX_FQID (0x00ffffff) -+#define QM_FQD_BLOCK_SIZE 64 -+#define QM_FQD_AR (0xC10) -+ -+static u32 fqid_max; -+static u64 qman_ccsr_start; -+static u64 qman_ccsr_size; -+ -+static const char * const state_txt[] = { -+ "Out of Service", -+ "Retired", -+ "Tentatively Scheduled", -+ "Truly Scheduled", -+ "Parked", -+ "Active, Active Held or Held Suspended", -+ "Unknown State 6", -+ "Unknown State 7", -+ NULL, -+}; -+ -+static const u8 fqd_states[] = { -+ QM_MCR_NP_STATE_OOS, QM_MCR_NP_STATE_RETIRED, QM_MCR_NP_STATE_TEN_SCHED, -+ QM_MCR_NP_STATE_TRU_SCHED, QM_MCR_NP_STATE_PARKED, -+ QM_MCR_NP_STATE_ACTIVE}; -+ -+struct mask_to_text { -+ u16 mask; -+ const char *txt; -+}; -+ -+struct mask_filter_s { -+ u16 mask; -+ u8 filter; -+}; -+ -+static const struct mask_filter_s mask_filter[] = { -+ {QM_FQCTRL_PREFERINCACHE, 0}, -+ {QM_FQCTRL_PREFERINCACHE, 1}, -+ {QM_FQCTRL_HOLDACTIVE, 0}, -+ {QM_FQCTRL_HOLDACTIVE, 1}, -+ {QM_FQCTRL_AVOIDBLOCK, 0}, -+ {QM_FQCTRL_AVOIDBLOCK, 1}, -+ {QM_FQCTRL_FORCESFDR, 0}, -+ {QM_FQCTRL_FORCESFDR, 1}, -+ {QM_FQCTRL_CPCSTASH, 0}, -+ {QM_FQCTRL_CPCSTASH, 1}, -+ {QM_FQCTRL_CTXASTASHING, 0}, -+ {QM_FQCTRL_CTXASTASHING, 1}, -+ {QM_FQCTRL_ORP, 0}, -+ {QM_FQCTRL_ORP, 1}, -+ {QM_FQCTRL_TDE, 0}, -+ {QM_FQCTRL_TDE, 1}, -+ {QM_FQCTRL_CGE, 0}, -+ {QM_FQCTRL_CGE, 1} -+}; -+ -+static const struct mask_to_text fq_ctrl_text_list[] = { -+ { -+ .mask = QM_FQCTRL_PREFERINCACHE, -+ .txt = "Prefer in cache", -+ }, -+ { -+ .mask = QM_FQCTRL_HOLDACTIVE, -+ .txt = "Hold active in portal", -+ }, -+ { -+ .mask = QM_FQCTRL_AVOIDBLOCK, -+ .txt = "Avoid Blocking", -+ }, -+ { -+ .mask = QM_FQCTRL_FORCESFDR, -+ .txt = "High-priority SFDRs", -+ }, -+ { -+ .mask = QM_FQCTRL_CPCSTASH, -+ .txt = "CPC Stash Enable", -+ }, -+ { -+ .mask = QM_FQCTRL_CTXASTASHING, -+ .txt = "Context-A stashing", -+ }, -+ { -+ .mask = QM_FQCTRL_ORP, -+ .txt = "ORP Enable", -+ }, -+ { -+ .mask = QM_FQCTRL_TDE, -+ .txt = "Tail-Drop Enable", -+ }, -+ { -+ .mask = QM_FQCTRL_CGE, -+ .txt = "Congestion Group Enable", -+ }, -+ { -+ .mask = 0, -+ .txt = NULL, -+ } -+}; -+ -+static const char *get_fqd_ctrl_text(u16 mask) -+{ -+ int i = 0; -+ -+ while (fq_ctrl_text_list[i].txt != NULL) { -+ if (fq_ctrl_text_list[i].mask == mask) -+ return fq_ctrl_text_list[i].txt; -+ i++; -+ } -+ return NULL; -+} -+ -+static const struct mask_to_text stashing_text_list[] = { -+ { -+ .mask = QM_STASHING_EXCL_CTX, -+ .txt = "FQ Ctx Stash" -+ }, -+ { -+ .mask = QM_STASHING_EXCL_DATA, -+ .txt = "Frame Data Stash", -+ }, -+ { -+ .mask = QM_STASHING_EXCL_ANNOTATION, -+ .txt = "Frame Annotation Stash", -+ }, -+ { -+ .mask = 0, -+ .txt = NULL, -+ }, -+}; -+ -+static int user_input_convert(const char __user *user_buf, size_t count, -+ unsigned long *val) -+{ -+ char buf[12]; -+ -+ if (count > sizeof(buf) - 1) -+ return -EINVAL; -+ if (copy_from_user(buf, user_buf, count)) -+ return -EFAULT; -+ buf[count] = '\0'; -+ if (kstrtoul(buf, 0, val)) -+ return -EINVAL; -+ return 0; -+} -+ -+struct line_buffer_fq { -+ u32 buf[8]; -+ u32 buf_cnt; -+ int line_cnt; -+}; -+ -+static void add_to_line_buffer(struct line_buffer_fq *line_buf, u32 fqid, -+ struct seq_file *file) -+{ -+ line_buf->buf[line_buf->buf_cnt] = fqid; -+ line_buf->buf_cnt++; -+ if (line_buf->buf_cnt == 8) { -+ /* Buffer is full, flush it */ -+ if (line_buf->line_cnt != 0) -+ seq_puts(file, ",\n"); -+ seq_printf(file, "0x%06x,0x%06x,0x%06x,0x%06x,0x%06x," -+ "0x%06x,0x%06x,0x%06x", -+ line_buf->buf[0], line_buf->buf[1], line_buf->buf[2], -+ line_buf->buf[3], line_buf->buf[4], line_buf->buf[5], -+ line_buf->buf[6], line_buf->buf[7]); -+ line_buf->buf_cnt = 0; -+ line_buf->line_cnt++; -+ } -+} -+ -+static void flush_line_buffer(struct line_buffer_fq *line_buf, -+ struct seq_file *file) -+{ -+ if (line_buf->buf_cnt) { -+ int y = 0; -+ if (line_buf->line_cnt != 0) -+ seq_puts(file, ",\n"); -+ while (y != line_buf->buf_cnt) { -+ if (y+1 == line_buf->buf_cnt) -+ seq_printf(file, "0x%06x", line_buf->buf[y]); -+ else -+ seq_printf(file, "0x%06x,", line_buf->buf[y]); -+ y++; -+ } -+ line_buf->line_cnt++; -+ } -+ if (line_buf->line_cnt) -+ seq_putc(file, '\n'); -+} -+ -+static struct dentry *dfs_root; /* debugfs root directory */ -+ -+/******************************************************************************* -+ * Query Frame Queue Non Programmable Fields -+ ******************************************************************************/ -+struct query_fq_np_fields_data_s { -+ u32 fqid; -+}; -+static struct query_fq_np_fields_data_s query_fq_np_fields_data = { -+ .fqid = 1, -+}; -+ -+static int query_fq_np_fields_show(struct seq_file *file, void *offset) -+{ -+ int ret; -+ struct qm_mcr_queryfq_np np; -+ struct qman_fq fq; -+ -+ fq.fqid = query_fq_np_fields_data.fqid; -+ ret = qman_query_fq_np(&fq, &np); -+ if (ret) -+ return ret; -+ /* Print state */ -+ seq_printf(file, "Query FQ Non Programmable Fields Result fqid 0x%x\n", -+ fq.fqid); -+ seq_printf(file, " force eligible pending: %s\n", -+ (np.state & QM_MCR_NP_STATE_FE) ? "yes" : "no"); -+ seq_printf(file, " retirement pending: %s\n", -+ (np.state & QM_MCR_NP_STATE_R) ? "yes" : "no"); -+ seq_printf(file, " state: %s\n", -+ state_txt[np.state & QM_MCR_NP_STATE_MASK]); -+ seq_printf(file, " fq_link: 0x%x\n", np.fqd_link); -+ seq_printf(file, " odp_seq: %u\n", np.odp_seq); -+ seq_printf(file, " orp_nesn: %u\n", np.orp_nesn); -+ seq_printf(file, " orp_ea_hseq: %u\n", np.orp_ea_hseq); -+ seq_printf(file, " orp_ea_tseq: %u\n", np.orp_ea_tseq); -+ seq_printf(file, " orp_ea_hptr: 0x%x\n", np.orp_ea_hptr); -+ seq_printf(file, " orp_ea_tptr: 0x%x\n", np.orp_ea_tptr); -+ seq_printf(file, " pfdr_hptr: 0x%x\n", np.pfdr_hptr); -+ seq_printf(file, " pfdr_tptr: 0x%x\n", np.pfdr_tptr); -+ seq_printf(file, " is: ics_surp contains a %s\n", -+ (np.is) ? "deficit" : "surplus"); -+ seq_printf(file, " ics_surp: %u\n", np.ics_surp); -+ seq_printf(file, " byte_cnt: %u\n", np.byte_cnt); -+ seq_printf(file, " frm_cnt: %u\n", np.frm_cnt); -+ seq_printf(file, " ra1_sfdr: 0x%x\n", np.ra1_sfdr); -+ seq_printf(file, " ra2_sfdr: 0x%x\n", np.ra2_sfdr); -+ seq_printf(file, " od1_sfdr: 0x%x\n", np.od1_sfdr); -+ seq_printf(file, " od2_sfdr: 0x%x\n", np.od2_sfdr); -+ seq_printf(file, " od3_sfdr: 0x%x\n", np.od3_sfdr); -+ return 0; -+} -+ -+static int query_fq_np_fields_open(struct inode *inode, -+ struct file *file) -+{ -+ return single_open(file, query_fq_np_fields_show, NULL); -+} -+ -+static ssize_t query_fq_np_fields_write(struct file *f, -+ const char __user *buf, size_t count, loff_t *off) -+{ -+ int ret; -+ unsigned long val; -+ -+ ret = user_input_convert(buf, count, &val); -+ if (ret) -+ return ret; -+ if (val > MAX_FQID) -+ return -EINVAL; -+ query_fq_np_fields_data.fqid = (u32)val; -+ return count; -+} -+ -+static const struct file_operations query_fq_np_fields_fops = { -+ .owner = THIS_MODULE, -+ .open = query_fq_np_fields_open, -+ .read = seq_read, -+ .write = query_fq_np_fields_write, -+ .release = single_release, -+}; -+ -+/******************************************************************************* -+ * Frame Queue Programmable Fields -+ ******************************************************************************/ -+struct query_fq_fields_data_s { -+ u32 fqid; -+}; -+ -+static struct query_fq_fields_data_s query_fq_fields_data = { -+ .fqid = 1, -+}; -+ -+static int query_fq_fields_show(struct seq_file *file, void *offset) -+{ -+ int ret; -+ struct qm_fqd fqd; -+ struct qman_fq fq; -+ int i = 0; -+ -+ memset(&fqd, 0, sizeof(struct qm_fqd)); -+ fq.fqid = query_fq_fields_data.fqid; -+ ret = qman_query_fq(&fq, &fqd); -+ if (ret) -+ return ret; -+ seq_printf(file, "Query FQ Programmable Fields Result fqid 0x%x\n", -+ fq.fqid); -+ seq_printf(file, " orprws: %u\n", fqd.orprws); -+ seq_printf(file, " oa: %u\n", fqd.oa); -+ seq_printf(file, " olws: %u\n", fqd.olws); -+ -+ seq_printf(file, " cgid: %u\n", fqd.cgid); -+ -+ if ((fqd.fq_ctrl & QM_FQCTRL_MASK) == 0) -+ seq_puts(file, " fq_ctrl: None\n"); -+ else { -+ i = 0; -+ seq_puts(file, " fq_ctrl:\n"); -+ while (fq_ctrl_text_list[i].txt != NULL) { -+ if ((fqd.fq_ctrl & QM_FQCTRL_MASK) & -+ fq_ctrl_text_list[i].mask) -+ seq_printf(file, " %s\n", -+ fq_ctrl_text_list[i].txt); -+ i++; -+ } -+ } -+ seq_printf(file, " dest_channel: %u\n", fqd.dest.channel); -+ seq_printf(file, " dest_wq: %u\n", fqd.dest.wq); -+ seq_printf(file, " ics_cred: %u\n", fqd.ics_cred); -+ seq_printf(file, " td_mant: %u\n", fqd.td.mant); -+ seq_printf(file, " td_exp: %u\n", fqd.td.exp); -+ -+ seq_printf(file, " ctx_b: 0x%x\n", fqd.context_b); -+ -+ seq_printf(file, " ctx_a: 0x%llx\n", qm_fqd_stashing_get64(&fqd)); -+ /* Any stashing configured */ -+ if ((fqd.context_a.stashing.exclusive & 0x7) == 0) -+ seq_puts(file, " ctx_a_stash_exclusive: None\n"); -+ else { -+ seq_puts(file, " ctx_a_stash_exclusive:\n"); -+ i = 0; -+ while (stashing_text_list[i].txt != NULL) { -+ if ((fqd.fq_ctrl & 0x7) & stashing_text_list[i].mask) -+ seq_printf(file, " %s\n", -+ stashing_text_list[i].txt); -+ i++; -+ } -+ } -+ seq_printf(file, " ctx_a_stash_annotation_cl: %u\n", -+ fqd.context_a.stashing.annotation_cl); -+ seq_printf(file, " ctx_a_stash_data_cl: %u\n", -+ fqd.context_a.stashing.data_cl); -+ seq_printf(file, " ctx_a_stash_context_cl: %u\n", -+ fqd.context_a.stashing.context_cl); -+ return 0; -+} -+ -+static int query_fq_fields_open(struct inode *inode, -+ struct file *file) -+{ -+ return single_open(file, query_fq_fields_show, NULL); -+} -+ -+static ssize_t query_fq_fields_write(struct file *f, -+ const char __user *buf, size_t count, loff_t *off) -+{ -+ int ret; -+ unsigned long val; -+ -+ ret = user_input_convert(buf, count, &val); -+ if (ret) -+ return ret; -+ if (val > MAX_FQID) -+ return -EINVAL; -+ query_fq_fields_data.fqid = (u32)val; -+ return count; -+} -+ -+static const struct file_operations query_fq_fields_fops = { -+ .owner = THIS_MODULE, -+ .open = query_fq_fields_open, -+ .read = seq_read, -+ .write = query_fq_fields_write, -+ .release = single_release, -+}; -+ -+/******************************************************************************* -+ * Query WQ lengths -+ ******************************************************************************/ -+struct query_wq_lengths_data_s { -+ union { -+ u16 channel_wq; /* ignores wq (3 lsbits) */ -+ struct { -+ u16 id:13; /* qm_channel */ -+ u16 __reserved:3; -+ } __packed channel; -+ }; -+}; -+static struct query_wq_lengths_data_s query_wq_lengths_data; -+static int query_wq_lengths_show(struct seq_file *file, void *offset) -+{ -+ int ret; -+ struct qm_mcr_querywq wq; -+ int i; -+ -+ memset(&wq, 0, sizeof(struct qm_mcr_querywq)); -+ wq.channel.id = query_wq_lengths_data.channel.id; -+ ret = qman_query_wq(0, &wq); -+ if (ret) -+ return ret; -+ seq_printf(file, "Query Result For Channel: 0x%x\n", wq.channel.id); -+ for (i = 0; i < 8; i++) -+ /* mask out upper 4 bits since they are not part of length */ -+ seq_printf(file, " wq%d_len : %u\n", i, wq.wq_len[i] & 0x0fff); -+ return 0; -+} -+ -+static int query_wq_lengths_open(struct inode *inode, -+ struct file *file) -+{ -+ return single_open(file, query_wq_lengths_show, NULL); -+} -+ -+static ssize_t query_wq_lengths_write(struct file *f, -+ const char __user *buf, size_t count, loff_t *off) -+{ -+ int ret; -+ unsigned long val; -+ -+ ret = user_input_convert(buf, count, &val); -+ if (ret) -+ return ret; -+ if (val > 0xfff8) -+ return -EINVAL; -+ query_wq_lengths_data.channel.id = (u16)val; -+ return count; -+} -+ -+static const struct file_operations query_wq_lengths_fops = { -+ .owner = THIS_MODULE, -+ .open = query_wq_lengths_open, -+ .read = seq_read, -+ .write = query_wq_lengths_write, -+ .release = single_release, -+}; -+ -+/******************************************************************************* -+ * Query CGR -+ ******************************************************************************/ -+struct query_cgr_s { -+ u8 cgid; -+}; -+static struct query_cgr_s query_cgr_data; -+ -+static int query_cgr_show(struct seq_file *file, void *offset) -+{ -+ int ret; -+ struct qm_mcr_querycgr cgrd; -+ struct qman_cgr cgr; -+ int i, j; -+ u32 mask; -+ -+ memset(&cgr, 0, sizeof(cgr)); -+ memset(&cgrd, 0, sizeof(cgrd)); -+ cgr.cgrid = query_cgr_data.cgid; -+ ret = qman_query_cgr(&cgr, &cgrd); -+ if (ret) -+ return ret; -+ seq_printf(file, "Query CGR id 0x%x\n", cgr.cgrid); -+ seq_printf(file, " wr_parm_g MA: %u, Mn: %u, SA: %u, Sn: %u, Pn: %u\n", -+ cgrd.cgr.wr_parm_g.MA, cgrd.cgr.wr_parm_g.Mn, -+ cgrd.cgr.wr_parm_g.SA, cgrd.cgr.wr_parm_g.Sn, -+ cgrd.cgr.wr_parm_g.Pn); -+ -+ seq_printf(file, " wr_parm_y MA: %u, Mn: %u, SA: %u, Sn: %u, Pn: %u\n", -+ cgrd.cgr.wr_parm_y.MA, cgrd.cgr.wr_parm_y.Mn, -+ cgrd.cgr.wr_parm_y.SA, cgrd.cgr.wr_parm_y.Sn, -+ cgrd.cgr.wr_parm_y.Pn); -+ -+ seq_printf(file, " wr_parm_r MA: %u, Mn: %u, SA: %u, Sn: %u, Pn: %u\n", -+ cgrd.cgr.wr_parm_r.MA, cgrd.cgr.wr_parm_r.Mn, -+ cgrd.cgr.wr_parm_r.SA, cgrd.cgr.wr_parm_r.Sn, -+ cgrd.cgr.wr_parm_r.Pn); -+ -+ seq_printf(file, " wr_en_g: %u, wr_en_y: %u, we_en_r: %u\n", -+ cgrd.cgr.wr_en_g, cgrd.cgr.wr_en_y, cgrd.cgr.wr_en_r); -+ -+ seq_printf(file, " cscn_en: %u\n", cgrd.cgr.cscn_en); -+ if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) { -+ seq_puts(file, " cscn_targ_dcp:\n"); -+ mask = 0x80000000; -+ for (i = 0; i < 32; i++) { -+ if (cgrd.cgr.cscn_targ & mask) -+ seq_printf(file, " send CSCN to dcp %u\n", -+ (31 - i)); -+ mask >>= 1; -+ } -+ -+ seq_puts(file, " cscn_targ_swp:\n"); -+ for (i = 0; i < 4; i++) { -+ mask = 0x80000000; -+ for (j = 0; j < 32; j++) { -+ if (cgrd.cscn_targ_swp[i] & mask) -+ seq_printf(file, " send CSCN to swp" -+ " %u\n", (127 - (i * 32) - j)); -+ mask >>= 1; -+ } -+ } -+ } else { -+ seq_printf(file, " cscn_targ: %u\n", cgrd.cgr.cscn_targ); -+ } -+ seq_printf(file, " cstd_en: %u\n", cgrd.cgr.cstd_en); -+ seq_printf(file, " cs: %u\n", cgrd.cgr.cs); -+ -+ seq_printf(file, " cs_thresh_TA: %u, cs_thresh_Tn: %u\n", -+ cgrd.cgr.cs_thres.TA, cgrd.cgr.cs_thres.Tn); -+ -+ seq_printf(file, " mode: %s\n", -+ (cgrd.cgr.mode & QMAN_CGR_MODE_FRAME) ? -+ "frame count" : "byte count"); -+ seq_printf(file, " i_bcnt: %llu\n", qm_mcr_querycgr_i_get64(&cgrd)); -+ seq_printf(file, " a_bcnt: %llu\n", qm_mcr_querycgr_a_get64(&cgrd)); -+ -+ return 0; -+} -+ -+static int query_cgr_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, query_cgr_show, NULL); -+} -+ -+static ssize_t query_cgr_write(struct file *f, const char __user *buf, -+ size_t count, loff_t *off) -+{ -+ int ret; -+ unsigned long val; -+ -+ ret = user_input_convert(buf, count, &val); -+ if (ret) -+ return ret; -+ if (val > 0xff) -+ return -EINVAL; -+ query_cgr_data.cgid = (u8)val; -+ return count; -+} -+ -+static const struct file_operations query_cgr_fops = { -+ .owner = THIS_MODULE, -+ .open = query_cgr_open, -+ .read = seq_read, -+ .write = query_cgr_write, -+ .release = single_release, -+}; -+ -+/******************************************************************************* -+ * Test Write CGR -+ ******************************************************************************/ -+struct test_write_cgr_s { -+ u64 i_bcnt; -+ u8 cgid; -+}; -+static struct test_write_cgr_s test_write_cgr_data; -+ -+static int testwrite_cgr_show(struct seq_file *file, void *offset) -+{ -+ int ret; -+ struct qm_mcr_cgrtestwrite result; -+ struct qman_cgr cgr; -+ u64 i_bcnt; -+ -+ memset(&cgr, 0, sizeof(struct qman_cgr)); -+ memset(&result, 0, sizeof(struct qm_mcr_cgrtestwrite)); -+ cgr.cgrid = test_write_cgr_data.cgid; -+ i_bcnt = test_write_cgr_data.i_bcnt; -+ ret = qman_testwrite_cgr(&cgr, i_bcnt, &result); -+ if (ret) -+ return ret; -+ seq_printf(file, "CGR Test Write CGR id 0x%x\n", cgr.cgrid); -+ seq_printf(file, " wr_parm_g MA: %u, Mn: %u, SA: %u, Sn: %u, Pn: %u\n", -+ result.cgr.wr_parm_g.MA, result.cgr.wr_parm_g.Mn, -+ result.cgr.wr_parm_g.SA, result.cgr.wr_parm_g.Sn, -+ result.cgr.wr_parm_g.Pn); -+ seq_printf(file, " wr_parm_y MA: %u, Mn: %u, SA: %u, Sn: %u, Pn: %u\n", -+ result.cgr.wr_parm_y.MA, result.cgr.wr_parm_y.Mn, -+ result.cgr.wr_parm_y.SA, result.cgr.wr_parm_y.Sn, -+ result.cgr.wr_parm_y.Pn); -+ seq_printf(file, " wr_parm_r MA: %u, Mn: %u, SA: %u, Sn: %u, Pn: %u\n", -+ result.cgr.wr_parm_r.MA, result.cgr.wr_parm_r.Mn, -+ result.cgr.wr_parm_r.SA, result.cgr.wr_parm_r.Sn, -+ result.cgr.wr_parm_r.Pn); -+ seq_printf(file, " wr_en_g: %u, wr_en_y: %u, we_en_r: %u\n", -+ result.cgr.wr_en_g, result.cgr.wr_en_y, result.cgr.wr_en_r); -+ seq_printf(file, " cscn_en: %u\n", result.cgr.cscn_en); -+ seq_printf(file, " cscn_targ: %u\n", result.cgr.cscn_targ); -+ seq_printf(file, " cstd_en: %u\n", result.cgr.cstd_en); -+ seq_printf(file, " cs: %u\n", result.cgr.cs); -+ seq_printf(file, " cs_thresh_TA: %u, cs_thresh_Tn: %u\n", -+ result.cgr.cs_thres.TA, result.cgr.cs_thres.Tn); -+ -+ /* Add Mode for Si 2 */ -+ seq_printf(file, " mode: %s\n", -+ (result.cgr.mode & QMAN_CGR_MODE_FRAME) ? -+ "frame count" : "byte count"); -+ -+ seq_printf(file, " i_bcnt: %llu\n", -+ qm_mcr_cgrtestwrite_i_get64(&result)); -+ seq_printf(file, " a_bcnt: %llu\n", -+ qm_mcr_cgrtestwrite_a_get64(&result)); -+ seq_printf(file, " wr_prob_g: %u\n", result.wr_prob_g); -+ seq_printf(file, " wr_prob_y: %u\n", result.wr_prob_y); -+ seq_printf(file, " wr_prob_r: %u\n", result.wr_prob_r); -+ return 0; -+} -+ -+static int testwrite_cgr_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, testwrite_cgr_show, NULL); -+} -+ -+static const struct file_operations testwrite_cgr_fops = { -+ .owner = THIS_MODULE, -+ .open = testwrite_cgr_open, -+ .read = seq_read, -+ .release = single_release, -+}; -+ -+ -+static int testwrite_cgr_ibcnt_show(struct seq_file *file, void *offset) -+{ -+ seq_printf(file, "i_bcnt: %llu\n", test_write_cgr_data.i_bcnt); -+ return 0; -+} -+static int testwrite_cgr_ibcnt_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, testwrite_cgr_ibcnt_show, NULL); -+} -+ -+static ssize_t testwrite_cgr_ibcnt_write(struct file *f, const char __user *buf, -+ size_t count, loff_t *off) -+{ -+ int ret; -+ unsigned long val; -+ -+ ret = user_input_convert(buf, count, &val); -+ if (ret) -+ return ret; -+ test_write_cgr_data.i_bcnt = val; -+ return count; -+} -+ -+static const struct file_operations teswrite_cgr_ibcnt_fops = { -+ .owner = THIS_MODULE, -+ .open = testwrite_cgr_ibcnt_open, -+ .read = seq_read, -+ .write = testwrite_cgr_ibcnt_write, -+ .release = single_release, -+}; -+ -+static int testwrite_cgr_cgrid_show(struct seq_file *file, void *offset) -+{ -+ seq_printf(file, "cgrid: %u\n", (u32)test_write_cgr_data.cgid); -+ return 0; -+} -+static int testwrite_cgr_cgrid_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, testwrite_cgr_cgrid_show, NULL); -+} -+ -+static ssize_t testwrite_cgr_cgrid_write(struct file *f, const char __user *buf, -+ size_t count, loff_t *off) -+{ -+ int ret; -+ unsigned long val; -+ -+ ret = user_input_convert(buf, count, &val); -+ if (ret) -+ return ret; -+ if (val > 0xff) -+ return -EINVAL; -+ test_write_cgr_data.cgid = (u8)val; -+ return count; -+} -+ -+static const struct file_operations teswrite_cgr_cgrid_fops = { -+ .owner = THIS_MODULE, -+ .open = testwrite_cgr_cgrid_open, -+ .read = seq_read, -+ .write = testwrite_cgr_cgrid_write, -+ .release = single_release, -+}; -+ -+/******************************************************************************* -+ * Query Congestion State -+ ******************************************************************************/ -+static int query_congestion_show(struct seq_file *file, void *offset) -+{ -+ int ret; -+ struct qm_mcr_querycongestion cs; -+ int i, j, in_cong = 0; -+ u32 mask; -+ -+ memset(&cs, 0, sizeof(struct qm_mcr_querycongestion)); -+ ret = qman_query_congestion(&cs); -+ if (ret) -+ return ret; -+ seq_puts(file, "Query Congestion Result\n"); -+ for (i = 0; i < 8; i++) { -+ mask = 0x80000000; -+ for (j = 0; j < 32; j++) { -+ if (cs.state.__state[i] & mask) { -+ in_cong = 1; -+ seq_printf(file, " cg %u: %s\n", (i*32)+j, -+ "in congestion"); -+ } -+ mask >>= 1; -+ } -+ } -+ if (!in_cong) -+ seq_puts(file, " All congestion groups not congested.\n"); -+ return 0; -+} -+ -+static int query_congestion_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, query_congestion_show, NULL); -+} -+ -+static const struct file_operations query_congestion_fops = { -+ .owner = THIS_MODULE, -+ .open = query_congestion_open, -+ .read = seq_read, -+ .release = single_release, -+}; -+ -+/******************************************************************************* -+ * Query CCGR -+ ******************************************************************************/ -+struct query_ccgr_s { -+ u32 ccgid; -+}; -+static struct query_ccgr_s query_ccgr_data; -+ -+static int query_ccgr_show(struct seq_file *file, void *offset) -+{ -+ int ret; -+ struct qm_mcr_ceetm_ccgr_query ccgr_query; -+ struct qm_mcc_ceetm_ccgr_query query_opts; -+ int i, j; -+ u32 mask; -+ -+ memset(&ccgr_query, 0, sizeof(struct qm_mcr_ceetm_ccgr_query)); -+ memset(&query_opts, 0, sizeof(struct qm_mcc_ceetm_ccgr_query)); -+ -+ if ((qman_ip_rev & 0xFF00) < QMAN_REV30) -+ return -EINVAL; -+ -+ seq_printf(file, "Query CCGID %x\n", query_ccgr_data.ccgid); -+ query_opts.dcpid = ((query_ccgr_data.ccgid & 0xFF000000) >> 24); -+ query_opts.ccgrid = query_ccgr_data.ccgid & 0x000001FF; -+ ret = qman_ceetm_query_ccgr(&query_opts, &ccgr_query); -+ if (ret) -+ return ret; -+ seq_printf(file, "Query CCGR id %x in DCP %d\n", query_opts.ccgrid, -+ query_opts.dcpid); -+ seq_printf(file, " wr_parm_g MA: %u, Mn: %u, SA: %u, Sn: %u, Pn: %u\n", -+ ccgr_query.cm_query.wr_parm_g.MA, -+ ccgr_query.cm_query.wr_parm_g.Mn, -+ ccgr_query.cm_query.wr_parm_g.SA, -+ ccgr_query.cm_query.wr_parm_g.Sn, -+ ccgr_query.cm_query.wr_parm_g.Pn); -+ -+ seq_printf(file, " wr_parm_y MA: %u, Mn: %u, SA: %u, Sn: %u, Pn: %u\n", -+ ccgr_query.cm_query.wr_parm_y.MA, -+ ccgr_query.cm_query.wr_parm_y.Mn, -+ ccgr_query.cm_query.wr_parm_y.SA, -+ ccgr_query.cm_query.wr_parm_y.Sn, -+ ccgr_query.cm_query.wr_parm_y.Pn); -+ -+ seq_printf(file, " wr_parm_r MA: %u, Mn: %u, SA: %u, Sn: %u, Pn: %u\n", -+ ccgr_query.cm_query.wr_parm_r.MA, -+ ccgr_query.cm_query.wr_parm_r.Mn, -+ ccgr_query.cm_query.wr_parm_r.SA, -+ ccgr_query.cm_query.wr_parm_r.Sn, -+ ccgr_query.cm_query.wr_parm_r.Pn); -+ -+ seq_printf(file, " wr_en_g: %u, wr_en_y: %u, we_en_r: %u\n", -+ ccgr_query.cm_query.ctl_wr_en_g, -+ ccgr_query.cm_query.ctl_wr_en_y, -+ ccgr_query.cm_query.ctl_wr_en_r); -+ -+ seq_printf(file, " cscn_en: %u\n", ccgr_query.cm_query.ctl_cscn_en); -+ seq_puts(file, " cscn_targ_dcp:\n"); -+ mask = 0x80000000; -+ for (i = 0; i < 32; i++) { -+ if (ccgr_query.cm_query.cscn_targ_dcp & mask) -+ seq_printf(file, " send CSCN to dcp %u\n", (31 - i)); -+ mask >>= 1; -+ } -+ -+ seq_puts(file, " cscn_targ_swp:\n"); -+ for (i = 0; i < 4; i++) { -+ mask = 0x80000000; -+ for (j = 0; j < 32; j++) { -+ if (ccgr_query.cm_query.cscn_targ_swp[i] & mask) -+ seq_printf(file, " send CSCN to swp" -+ "%u\n", (127 - (i * 32) - j)); -+ mask >>= 1; -+ } -+ } -+ -+ seq_printf(file, " td_en: %u\n", ccgr_query.cm_query.ctl_td_en); -+ -+ seq_printf(file, " cs_thresh_in_TA: %u, cs_thresh_in_Tn: %u\n", -+ ccgr_query.cm_query.cs_thres.TA, -+ ccgr_query.cm_query.cs_thres.Tn); -+ -+ seq_printf(file, " cs_thresh_out_TA: %u, cs_thresh_out_Tn: %u\n", -+ ccgr_query.cm_query.cs_thres_x.TA, -+ ccgr_query.cm_query.cs_thres_x.Tn); -+ -+ seq_printf(file, " td_thresh_TA: %u, td_thresh_Tn: %u\n", -+ ccgr_query.cm_query.td_thres.TA, -+ ccgr_query.cm_query.td_thres.Tn); -+ -+ seq_printf(file, " mode: %s\n", -+ (ccgr_query.cm_query.ctl_mode & -+ QMAN_CGR_MODE_FRAME) ? -+ "frame count" : "byte count"); -+ seq_printf(file, " i_cnt: %llu\n", (u64)ccgr_query.cm_query.i_cnt); -+ seq_printf(file, " a_cnt: %llu\n", (u64)ccgr_query.cm_query.a_cnt); -+ -+ return 0; -+} -+ -+static int query_ccgr_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, query_ccgr_show, NULL); -+} -+ -+static ssize_t query_ccgr_write(struct file *f, const char __user *buf, -+ size_t count, loff_t *off) -+{ -+ int ret; -+ unsigned long val; -+ -+ ret = user_input_convert(buf, count, &val); -+ if (ret) -+ return ret; -+ query_ccgr_data.ccgid = val; -+ return count; -+} -+ -+static const struct file_operations query_ccgr_fops = { -+ .owner = THIS_MODULE, -+ .open = query_ccgr_open, -+ .read = seq_read, -+ .write = query_ccgr_write, -+ .release = single_release, -+}; -+/******************************************************************************* -+ * QMan register -+ ******************************************************************************/ -+struct qman_register_s { -+ u32 val; -+}; -+static struct qman_register_s qman_register_data; -+ -+static void init_ccsrmempeek(void) -+{ -+ struct device_node *dn; -+ const u32 *regaddr_p; -+ -+ dn = of_find_compatible_node(NULL, NULL, "fsl,qman"); -+ if (!dn) { -+ pr_info("No fsl,qman node\n"); -+ return; -+ } -+ regaddr_p = of_get_address(dn, 0, &qman_ccsr_size, NULL); -+ if (!regaddr_p) { -+ of_node_put(dn); -+ return; -+ } -+ qman_ccsr_start = of_translate_address(dn, regaddr_p); -+ of_node_put(dn); -+} -+/* This function provides access to QMan ccsr memory map */ -+static int qman_ccsrmempeek(u32 *val, u32 offset) -+{ -+ void __iomem *addr; -+ u64 phys_addr; -+ -+ if (!qman_ccsr_start) -+ return -EINVAL; -+ -+ if (offset > (qman_ccsr_size - sizeof(u32))) -+ return -EINVAL; -+ -+ phys_addr = qman_ccsr_start + offset; -+ addr = ioremap(phys_addr, sizeof(u32)); -+ if (!addr) { -+ pr_err("ccsrmempeek, ioremap failed\n"); -+ return -EINVAL; -+ } -+ *val = in_be32(addr); -+ iounmap(addr); -+ return 0; -+} -+ -+static int qman_ccsrmempeek_show(struct seq_file *file, void *offset) -+{ -+ u32 b; -+ -+ qman_ccsrmempeek(&b, qman_register_data.val); -+ seq_printf(file, "QMan register offset = 0x%x\n", -+ qman_register_data.val); -+ seq_printf(file, "value = 0x%08x\n", b); -+ -+ return 0; -+} -+ -+static int qman_ccsrmempeek_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, qman_ccsrmempeek_show, NULL); -+} -+ -+static ssize_t qman_ccsrmempeek_write(struct file *f, const char __user *buf, -+ size_t count, loff_t *off) -+{ -+ int ret; -+ unsigned long val; -+ -+ ret = user_input_convert(buf, count, &val); -+ if (ret) -+ return ret; -+ /* multiple of 4 */ -+ if (val > (qman_ccsr_size - sizeof(u32))) { -+ pr_info("Input 0x%lx > 0x%llx\n", -+ val, (qman_ccsr_size - sizeof(u32))); -+ return -EINVAL; -+ } -+ if (val & 0x3) { -+ pr_info("Input 0x%lx not multiple of 4\n", val); -+ return -EINVAL; -+ } -+ qman_register_data.val = val; -+ return count; -+} -+ -+static const struct file_operations qman_ccsrmempeek_fops = { -+ .owner = THIS_MODULE, -+ .open = qman_ccsrmempeek_open, -+ .read = seq_read, -+ .write = qman_ccsrmempeek_write, -+}; -+ -+/******************************************************************************* -+ * QMan state -+ ******************************************************************************/ -+static int qman_fqd_state_show(struct seq_file *file, void *offset) -+{ -+ struct qm_mcr_queryfq_np np; -+ struct qman_fq fq; -+ struct line_buffer_fq line_buf; -+ int ret, i; -+ u8 *state = file->private; -+ u32 qm_fq_state_cnt[ARRAY_SIZE(fqd_states)]; -+ -+ memset(qm_fq_state_cnt, 0, sizeof(qm_fq_state_cnt)); -+ memset(&line_buf, 0, sizeof(line_buf)); -+ -+ seq_printf(file, "List of fq ids in state: %s\n", state_txt[*state]); -+ -+ for (i = 1; i < fqid_max; i++) { -+ fq.fqid = i; -+ ret = qman_query_fq_np(&fq, &np); -+ if (ret) -+ return ret; -+ if (*state == (np.state & QM_MCR_NP_STATE_MASK)) -+ add_to_line_buffer(&line_buf, fq.fqid, file); -+ /* Keep a summary count of all states */ -+ if ((np.state & QM_MCR_NP_STATE_MASK) < ARRAY_SIZE(fqd_states)) -+ qm_fq_state_cnt[(np.state & QM_MCR_NP_STATE_MASK)]++; -+ } -+ flush_line_buffer(&line_buf, file); -+ -+ for (i = 0; i < ARRAY_SIZE(fqd_states); i++) { -+ seq_printf(file, "%s count = %u\n", state_txt[i], -+ qm_fq_state_cnt[i]); -+ } -+ return 0; -+} -+ -+static int qman_fqd_state_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, qman_fqd_state_show, inode->i_private); -+} -+ -+static const struct file_operations qman_fqd_state_fops = { -+ .owner = THIS_MODULE, -+ .open = qman_fqd_state_open, -+ .read = seq_read, -+}; -+ -+static int qman_fqd_ctrl_show(struct seq_file *file, void *offset) -+{ -+ struct qm_fqd fqd; -+ struct qman_fq fq; -+ u32 fq_en_cnt = 0, fq_di_cnt = 0; -+ int ret, i; -+ struct mask_filter_s *data = file->private; -+ const char *ctrl_txt = get_fqd_ctrl_text(data->mask); -+ struct line_buffer_fq line_buf; -+ -+ memset(&line_buf, 0, sizeof(line_buf)); -+ seq_printf(file, "List of fq ids with: %s :%s\n", -+ ctrl_txt, (data->filter) ? "enabled" : "disabled"); -+ for (i = 1; i < fqid_max; i++) { -+ fq.fqid = i; -+ memset(&fqd, 0, sizeof(struct qm_fqd)); -+ ret = qman_query_fq(&fq, &fqd); -+ if (ret) -+ return ret; -+ if (data->filter) { -+ if (fqd.fq_ctrl & data->mask) -+ add_to_line_buffer(&line_buf, fq.fqid, file); -+ } else { -+ if (!(fqd.fq_ctrl & data->mask)) -+ add_to_line_buffer(&line_buf, fq.fqid, file); -+ } -+ if (fqd.fq_ctrl & data->mask) -+ fq_en_cnt++; -+ else -+ fq_di_cnt++; -+ } -+ flush_line_buffer(&line_buf, file); -+ -+ seq_printf(file, "Total FQD with: %s : enabled = %u\n", -+ ctrl_txt, fq_en_cnt); -+ seq_printf(file, "Total FQD with: %s : disabled = %u\n", -+ ctrl_txt, fq_di_cnt); -+ return 0; -+} -+ -+/******************************************************************************* -+ * QMan ctrl CGE, TDE, ORP, CTX, CPC, SFDR, BLOCK, HOLD, CACHE -+ ******************************************************************************/ -+static int qman_fqd_ctrl_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, qman_fqd_ctrl_show, inode->i_private); -+} -+ -+static const struct file_operations qman_fqd_ctrl_fops = { -+ .owner = THIS_MODULE, -+ .open = qman_fqd_ctrl_open, -+ .read = seq_read, -+}; -+ -+/******************************************************************************* -+ * QMan ctrl summary -+ ******************************************************************************/ -+/******************************************************************************* -+ * QMan summary state -+ ******************************************************************************/ -+static int qman_fqd_non_prog_summary_show(struct seq_file *file, void *offset) -+{ -+ struct qm_mcr_queryfq_np np; -+ struct qman_fq fq; -+ int ret, i; -+ u32 qm_fq_state_cnt[ARRAY_SIZE(fqd_states)]; -+ -+ memset(qm_fq_state_cnt, 0, sizeof(qm_fq_state_cnt)); -+ -+ for (i = 1; i < fqid_max; i++) { -+ fq.fqid = i; -+ ret = qman_query_fq_np(&fq, &np); -+ if (ret) -+ return ret; -+ /* Keep a summary count of all states */ -+ if ((np.state & QM_MCR_NP_STATE_MASK) < ARRAY_SIZE(fqd_states)) -+ qm_fq_state_cnt[(np.state & QM_MCR_NP_STATE_MASK)]++; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(fqd_states); i++) { -+ seq_printf(file, "%s count = %u\n", state_txt[i], -+ qm_fq_state_cnt[i]); -+ } -+ return 0; -+} -+ -+static int qman_fqd_prog_summary_show(struct seq_file *file, void *offset) -+{ -+ struct qm_fqd fqd; -+ struct qman_fq fq; -+ int ret, i , j; -+ u32 qm_prog_cnt[ARRAY_SIZE(mask_filter)/2]; -+ -+ memset(qm_prog_cnt, 0, sizeof(qm_prog_cnt)); -+ -+ for (i = 1; i < fqid_max; i++) { -+ memset(&fqd, 0, sizeof(struct qm_fqd)); -+ fq.fqid = i; -+ ret = qman_query_fq(&fq, &fqd); -+ if (ret) -+ return ret; -+ /* Keep a summary count of all states */ -+ for (j = 0; j < ARRAY_SIZE(mask_filter); j += 2) -+ if ((fqd.fq_ctrl & QM_FQCTRL_MASK) & -+ mask_filter[j].mask) -+ qm_prog_cnt[j/2]++; -+ } -+ for (i = 0; i < ARRAY_SIZE(mask_filter) / 2; i++) { -+ seq_printf(file, "%s count = %u\n", -+ get_fqd_ctrl_text(mask_filter[i*2].mask), -+ qm_prog_cnt[i]); -+ } -+ return 0; -+} -+ -+static int qman_fqd_summary_show(struct seq_file *file, void *offset) -+{ -+ int ret; -+ -+ /* Display summary of non programmable fields */ -+ ret = qman_fqd_non_prog_summary_show(file, offset); -+ if (ret) -+ return ret; -+ seq_puts(file, "-----------------------------------------\n"); -+ /* Display programmable fields */ -+ ret = qman_fqd_prog_summary_show(file, offset); -+ if (ret) -+ return ret; -+ return 0; -+} -+ -+static int qman_fqd_summary_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, qman_fqd_summary_show, NULL); -+} -+ -+static const struct file_operations qman_fqd_summary_fops = { -+ .owner = THIS_MODULE, -+ .open = qman_fqd_summary_open, -+ .read = seq_read, -+}; -+ -+/******************************************************************************* -+ * QMan destination work queue -+ ******************************************************************************/ -+struct qman_dest_wq_s { -+ u16 wq_id; -+}; -+static struct qman_dest_wq_s qman_dest_wq_data = { -+ .wq_id = 0, -+}; -+ -+static int qman_fqd_dest_wq_show(struct seq_file *file, void *offset) -+{ -+ struct qm_fqd fqd; -+ struct qman_fq fq; -+ int ret, i; -+ u16 *wq, wq_id = qman_dest_wq_data.wq_id; -+ struct line_buffer_fq line_buf; -+ -+ memset(&line_buf, 0, sizeof(line_buf)); -+ /* use vmalloc : need to allocate large memory region and don't -+ * require the memory to be physically contiguous. */ -+ wq = vzalloc(sizeof(u16) * (0xFFFF+1)); -+ if (!wq) -+ return -ENOMEM; -+ -+ seq_printf(file, "List of fq ids with destination work queue id" -+ " = 0x%x\n", wq_id); -+ -+ for (i = 1; i < fqid_max; i++) { -+ fq.fqid = i; -+ memset(&fqd, 0, sizeof(struct qm_fqd)); -+ ret = qman_query_fq(&fq, &fqd); -+ if (ret) { -+ vfree(wq); -+ return ret; -+ } -+ if (wq_id == fqd.dest_wq) -+ add_to_line_buffer(&line_buf, fq.fqid, file); -+ wq[fqd.dest_wq]++; -+ } -+ flush_line_buffer(&line_buf, file); -+ -+ seq_puts(file, "Summary of all FQD destination work queue values\n"); -+ for (i = 0; i < 0xFFFF; i++) { -+ if (wq[i]) -+ seq_printf(file, "Channel: 0x%x WQ: 0x%x WQ_ID: 0x%x, " -+ "count = %u\n", i >> 3, i & 0x3, i, wq[i]); -+ } -+ vfree(wq); -+ return 0; -+} -+ -+static ssize_t qman_fqd_dest_wq_write(struct file *f, const char __user *buf, -+ size_t count, loff_t *off) -+{ -+ int ret; -+ unsigned long val; -+ -+ ret = user_input_convert(buf, count, &val); -+ if (ret) -+ return ret; -+ if (val > 0xFFFF) -+ return -EINVAL; -+ qman_dest_wq_data.wq_id = val; -+ return count; -+} -+ -+static int qman_fqd_dest_wq_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, qman_fqd_dest_wq_show, NULL); -+} -+ -+static const struct file_operations qman_fqd_dest_wq_fops = { -+ .owner = THIS_MODULE, -+ .open = qman_fqd_dest_wq_open, -+ .read = seq_read, -+ .write = qman_fqd_dest_wq_write, -+}; -+ -+/******************************************************************************* -+ * QMan Intra-Class Scheduling Credit -+ ******************************************************************************/ -+static int qman_fqd_cred_show(struct seq_file *file, void *offset) -+{ -+ struct qm_fqd fqd; -+ struct qman_fq fq; -+ int ret, i; -+ u32 fq_cnt = 0; -+ struct line_buffer_fq line_buf; -+ -+ memset(&line_buf, 0, sizeof(line_buf)); -+ seq_puts(file, "List of fq ids with Intra-Class Scheduling Credit > 0" -+ "\n"); -+ -+ for (i = 1; i < fqid_max; i++) { -+ fq.fqid = i; -+ memset(&fqd, 0, sizeof(struct qm_fqd)); -+ ret = qman_query_fq(&fq, &fqd); -+ if (ret) -+ return ret; -+ if (fqd.ics_cred > 0) { -+ add_to_line_buffer(&line_buf, fq.fqid, file); -+ fq_cnt++; -+ } -+ } -+ flush_line_buffer(&line_buf, file); -+ -+ seq_printf(file, "Total FQD with ics_cred > 0 = %d\n", fq_cnt); -+ return 0; -+} -+ -+static int qman_fqd_cred_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, qman_fqd_cred_show, NULL); -+} -+ -+static const struct file_operations qman_fqd_cred_fops = { -+ .owner = THIS_MODULE, -+ .open = qman_fqd_cred_open, -+ .read = seq_read, -+}; -+ -+/******************************************************************************* -+ * Class Queue Fields -+ ******************************************************************************/ -+struct query_cq_fields_data_s { -+ u32 cqid; -+}; -+ -+static struct query_cq_fields_data_s query_cq_fields_data = { -+ .cqid = 1, -+}; -+ -+static int query_cq_fields_show(struct seq_file *file, void *offset) -+{ -+ int ret; -+ struct qm_mcr_ceetm_cq_query query_result; -+ unsigned int cqid; -+ unsigned int portal; -+ -+ if ((qman_ip_rev & 0xFF00) < QMAN_REV30) -+ return -EINVAL; -+ -+ cqid = query_cq_fields_data.cqid & 0x00FFFFFF; -+ portal = query_cq_fields_data.cqid >> 24; -+ if (portal > qm_dc_portal_fman1) -+ return -EINVAL; -+ -+ ret = qman_ceetm_query_cq(cqid, portal, &query_result); -+ if (ret) -+ return ret; -+ seq_printf(file, "Query CQ Fields Result cqid 0x%x on DCP %d\n", -+ cqid, portal); -+ seq_printf(file, " ccgid: %u\n", query_result.ccgid); -+ seq_printf(file, " state: %u\n", query_result.state); -+ seq_printf(file, " pfdr_hptr: %u\n", query_result.pfdr_hptr); -+ seq_printf(file, " pfdr_tptr: %u\n", query_result.pfdr_tptr); -+ seq_printf(file, " od1_xsfdr: %u\n", query_result.od1_xsfdr); -+ seq_printf(file, " od2_xsfdr: %u\n", query_result.od2_xsfdr); -+ seq_printf(file, " od3_xsfdr: %u\n", query_result.od3_xsfdr); -+ seq_printf(file, " od4_xsfdr: %u\n", query_result.od4_xsfdr); -+ seq_printf(file, " od5_xsfdr: %u\n", query_result.od5_xsfdr); -+ seq_printf(file, " od6_xsfdr: %u\n", query_result.od6_xsfdr); -+ seq_printf(file, " ra1_xsfdr: %u\n", query_result.ra1_xsfdr); -+ seq_printf(file, " ra2_xsfdr: %u\n", query_result.ra2_xsfdr); -+ seq_printf(file, " frame_count: %u\n", query_result.frm_cnt); -+ -+ return 0; -+} -+ -+static int query_cq_fields_open(struct inode *inode, -+ struct file *file) -+{ -+ return single_open(file, query_cq_fields_show, NULL); -+} -+ -+static ssize_t query_cq_fields_write(struct file *f, -+ const char __user *buf, size_t count, loff_t *off) -+{ -+ int ret; -+ unsigned long val; -+ -+ ret = user_input_convert(buf, count, &val); -+ if (ret) -+ return ret; -+ query_cq_fields_data.cqid = (u32)val; -+ return count; -+} -+ -+static const struct file_operations query_cq_fields_fops = { -+ .owner = THIS_MODULE, -+ .open = query_cq_fields_open, -+ .read = seq_read, -+ .write = query_cq_fields_write, -+ .release = single_release, -+}; -+ -+/******************************************************************************* -+ * READ CEETM_XSFDR_IN_USE -+ ******************************************************************************/ -+struct query_ceetm_xsfdr_data_s { -+ enum qm_dc_portal dcp_portal; -+}; -+ -+static struct query_ceetm_xsfdr_data_s query_ceetm_xsfdr_data; -+ -+static int query_ceetm_xsfdr_show(struct seq_file *file, void *offset) -+{ -+ int ret; -+ unsigned int xsfdr_in_use; -+ enum qm_dc_portal portal; -+ -+ -+ if (qman_ip_rev < QMAN_REV31) -+ return -EINVAL; -+ -+ portal = query_ceetm_xsfdr_data.dcp_portal; -+ ret = qman_ceetm_get_xsfdr(portal, &xsfdr_in_use); -+ if (ret) { -+ seq_printf(file, "Read CEETM_XSFDR_IN_USE on DCP %d failed\n", -+ portal); -+ return ret; -+ } -+ -+ seq_printf(file, "DCP%d: CEETM_XSFDR_IN_USE number is %u\n", portal, -+ (xsfdr_in_use & 0x1FFF)); -+ return 0; -+} -+ -+static int query_ceetm_xsfdr_open(struct inode *inode, -+ struct file *file) -+{ -+ return single_open(file, query_ceetm_xsfdr_show, NULL); -+} -+ -+static ssize_t query_ceetm_xsfdr_write(struct file *f, -+ const char __user *buf, size_t count, loff_t *off) -+{ -+ int ret; -+ unsigned long val; -+ -+ ret = user_input_convert(buf, count, &val); -+ if (ret) -+ return ret; -+ if (val > qm_dc_portal_fman1) -+ return -EINVAL; -+ query_ceetm_xsfdr_data.dcp_portal = (u32)val; -+ return count; -+} -+ -+static const struct file_operations query_ceetm_xsfdr_fops = { -+ .owner = THIS_MODULE, -+ .open = query_ceetm_xsfdr_open, -+ .read = seq_read, -+ .write = query_ceetm_xsfdr_write, -+ .release = single_release, -+}; -+ -+/* helper macros used in qman_debugfs_module_init */ -+#define QMAN_DBGFS_ENTRY(name, mode, parent, data, fops) \ -+ do { \ -+ d = debugfs_create_file(name, \ -+ mode, parent, \ -+ data, \ -+ fops); \ -+ if (d == NULL) { \ -+ ret = -ENOMEM; \ -+ goto _return; \ -+ } \ -+ } while (0) -+ -+/* dfs_root as parent */ -+#define QMAN_DBGFS_ENTRY_ROOT(name, mode, data, fops) \ -+ QMAN_DBGFS_ENTRY(name, mode, dfs_root, data, fops) -+ -+/* fqd_root as parent */ -+#define QMAN_DBGFS_ENTRY_FQDROOT(name, mode, data, fops) \ -+ QMAN_DBGFS_ENTRY(name, mode, fqd_root, data, fops) -+ -+/* fqd state */ -+#define QMAN_DBGFS_ENTRY_FQDSTATE(name, index) \ -+ QMAN_DBGFS_ENTRY_FQDROOT(name, S_IRUGO, \ -+ (void *)&mask_filter[index], &qman_fqd_ctrl_fops) -+ -+static int __init qman_debugfs_module_init(void) -+{ -+ int ret = 0; -+ struct dentry *d, *fqd_root; -+ u32 reg; -+ -+ fqid_max = 0; -+ init_ccsrmempeek(); -+ if (qman_ccsr_start) { -+ if (!qman_ccsrmempeek(®, QM_FQD_AR)) { -+ /* extract the size of the FQD window */ -+ reg = reg & 0x3f; -+ /* calculate valid frame queue descriptor range */ -+ fqid_max = (1 << (reg + 1)) / QM_FQD_BLOCK_SIZE; -+ } -+ } -+ dfs_root = debugfs_create_dir("qman", NULL); -+ fqd_root = debugfs_create_dir("fqd", dfs_root); -+ if (dfs_root == NULL || fqd_root == NULL) { -+ ret = -ENOMEM; -+ pr_err("Cannot create qman/fqd debugfs dir\n"); -+ goto _return; -+ } -+ if (fqid_max) { -+ QMAN_DBGFS_ENTRY_ROOT("ccsrmempeek", S_IRUGO | S_IWUGO, -+ NULL, &qman_ccsrmempeek_fops); -+ } -+ QMAN_DBGFS_ENTRY_ROOT("query_fq_np_fields", S_IRUGO | S_IWUGO, -+ &query_fq_np_fields_data, &query_fq_np_fields_fops); -+ -+ QMAN_DBGFS_ENTRY_ROOT("query_fq_fields", S_IRUGO | S_IWUGO, -+ &query_fq_fields_data, &query_fq_fields_fops); -+ -+ QMAN_DBGFS_ENTRY_ROOT("query_wq_lengths", S_IRUGO | S_IWUGO, -+ &query_wq_lengths_data, &query_wq_lengths_fops); -+ -+ QMAN_DBGFS_ENTRY_ROOT("query_cgr", S_IRUGO | S_IWUGO, -+ &query_cgr_data, &query_cgr_fops); -+ -+ QMAN_DBGFS_ENTRY_ROOT("query_congestion", S_IRUGO, -+ NULL, &query_congestion_fops); -+ -+ QMAN_DBGFS_ENTRY_ROOT("testwrite_cgr", S_IRUGO, -+ NULL, &testwrite_cgr_fops); -+ -+ QMAN_DBGFS_ENTRY_ROOT("testwrite_cgr_cgrid", S_IRUGO | S_IWUGO, -+ NULL, &teswrite_cgr_cgrid_fops); -+ -+ QMAN_DBGFS_ENTRY_ROOT("testwrite_cgr_ibcnt", S_IRUGO | S_IWUGO, -+ NULL, &teswrite_cgr_ibcnt_fops); -+ -+ QMAN_DBGFS_ENTRY_ROOT("query_ceetm_ccgr", S_IRUGO | S_IWUGO, -+ &query_ccgr_data, &query_ccgr_fops); -+ /* Create files with fqd_root as parent */ -+ -+ QMAN_DBGFS_ENTRY_FQDROOT("stateoos", S_IRUGO, -+ (void *)&fqd_states[QM_MCR_NP_STATE_OOS], &qman_fqd_state_fops); -+ -+ QMAN_DBGFS_ENTRY_FQDROOT("state_retired", S_IRUGO, -+ (void *)&fqd_states[QM_MCR_NP_STATE_RETIRED], -+ &qman_fqd_state_fops); -+ -+ QMAN_DBGFS_ENTRY_FQDROOT("state_tentatively_sched", S_IRUGO, -+ (void *)&fqd_states[QM_MCR_NP_STATE_TEN_SCHED], -+ &qman_fqd_state_fops); -+ -+ QMAN_DBGFS_ENTRY_FQDROOT("state_truly_sched", S_IRUGO, -+ (void *)&fqd_states[QM_MCR_NP_STATE_TRU_SCHED], -+ &qman_fqd_state_fops); -+ -+ QMAN_DBGFS_ENTRY_FQDROOT("state_parked", S_IRUGO, -+ (void *)&fqd_states[QM_MCR_NP_STATE_PARKED], -+ &qman_fqd_state_fops); -+ -+ QMAN_DBGFS_ENTRY_FQDROOT("state_active", S_IRUGO, -+ (void *)&fqd_states[QM_MCR_NP_STATE_ACTIVE], -+ &qman_fqd_state_fops); -+ QMAN_DBGFS_ENTRY_ROOT("query_cq_fields", S_IRUGO | S_IWUGO, -+ &query_cq_fields_data, &query_cq_fields_fops); -+ QMAN_DBGFS_ENTRY_ROOT("query_ceetm_xsfdr_in_use", S_IRUGO | S_IWUGO, -+ &query_ceetm_xsfdr_data, &query_ceetm_xsfdr_fops); -+ -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("cge_enable", 17); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("cge_disable", 16); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("tde_enable", 15); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("tde_disable", 14); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("orp_enable", 13); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("orp_disable", 12); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("ctx_a_stashing_enable", 11); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("ctx_a_stashing_disable", 10); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("cpc_enable", 9); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("cpc_disable", 8); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("sfdr_enable", 7); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("sfdr_disable", 6); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("avoid_blocking_enable", 5); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("avoid_blocking_disable", 4); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("hold_active_enable", 3); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("hold_active_disable", 2); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("prefer_in_cache_enable", 1); -+ -+ QMAN_DBGFS_ENTRY_FQDSTATE("prefer_in_cache_disable", 0); -+ -+ QMAN_DBGFS_ENTRY_FQDROOT("summary", S_IRUGO, -+ NULL, &qman_fqd_summary_fops); -+ -+ QMAN_DBGFS_ENTRY_FQDROOT("wq", S_IRUGO | S_IWUGO, -+ NULL, &qman_fqd_dest_wq_fops); -+ -+ QMAN_DBGFS_ENTRY_FQDROOT("cred", S_IRUGO, -+ NULL, &qman_fqd_cred_fops); -+ -+ return 0; -+ -+_return: -+ debugfs_remove_recursive(dfs_root); -+ return ret; -+} -+ -+static void __exit qman_debugfs_module_exit(void) -+{ -+ debugfs_remove_recursive(dfs_root); -+} -+ -+module_init(qman_debugfs_module_init); -+module_exit(qman_debugfs_module_exit); -+MODULE_LICENSE("Dual BSD/GPL"); ---- /dev/null -+++ b/drivers/staging/fsl_qbman/qman_driver.c -@@ -0,0 +1,980 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "qman_private.h" -+ -+#include /* hard_smp_processor_id() if !CONFIG_SMP */ -+#ifdef CONFIG_HOTPLUG_CPU -+#include -+#endif -+ -+/* Global variable containing revision id (even on non-control plane systems -+ * where CCSR isn't available) */ -+u16 qman_ip_rev; -+EXPORT_SYMBOL(qman_ip_rev); -+u8 qman_ip_cfg; -+EXPORT_SYMBOL(qman_ip_cfg); -+u16 qm_channel_pool1 = QMAN_CHANNEL_POOL1; -+EXPORT_SYMBOL(qm_channel_pool1); -+u16 qm_channel_caam = QMAN_CHANNEL_CAAM; -+EXPORT_SYMBOL(qm_channel_caam); -+u16 qm_channel_pme = QMAN_CHANNEL_PME; -+EXPORT_SYMBOL(qm_channel_pme); -+u16 qm_channel_dce = QMAN_CHANNEL_DCE; -+EXPORT_SYMBOL(qm_channel_dce); -+u16 qman_portal_max; -+EXPORT_SYMBOL(qman_portal_max); -+ -+u32 qman_clk; -+struct qm_ceetm qman_ceetms[QMAN_CEETM_MAX]; -+/* the qman ceetm instances on the given SoC */ -+u8 num_ceetms; -+ -+/* For these variables, and the portal-initialisation logic, the -+ * comments in bman_driver.c apply here so won't be repeated. */ -+static struct qman_portal *shared_portals[NR_CPUS]; -+static int num_shared_portals; -+static int shared_portals_idx; -+static LIST_HEAD(unused_pcfgs); -+static DEFINE_SPINLOCK(unused_pcfgs_lock); -+ -+/* A SDQCR mask comprising all the available/visible pool channels */ -+static u32 pools_sdqcr; -+ -+#define STR_ERR_NOPROP "No '%s' property in node %s\n" -+#define STR_ERR_CELL "'%s' is not a %d-cell range in node %s\n" -+#define STR_FQID_RANGE "fsl,fqid-range" -+#define STR_POOL_CHAN_RANGE "fsl,pool-channel-range" -+#define STR_CGRID_RANGE "fsl,cgrid-range" -+ -+/* A "fsl,fqid-range" node; release the given range to the allocator */ -+static __init int fsl_fqid_range_init(struct device_node *node) -+{ -+ int ret; -+ const u32 *range = of_get_property(node, STR_FQID_RANGE, &ret); -+ if (!range) { -+ pr_err(STR_ERR_NOPROP, STR_FQID_RANGE, node->full_name); -+ return -EINVAL; -+ } -+ if (ret != 8) { -+ pr_err(STR_ERR_CELL, STR_FQID_RANGE, 2, node->full_name); -+ return -EINVAL; -+ } -+ qman_seed_fqid_range(be32_to_cpu(range[0]), be32_to_cpu(range[1])); -+ pr_info("Qman: FQID allocator includes range %d:%d\n", -+ be32_to_cpu(range[0]), be32_to_cpu(range[1])); -+ return 0; -+} -+ -+/* A "fsl,pool-channel-range" node; add to the SDQCR mask only */ -+static __init int fsl_pool_channel_range_sdqcr(struct device_node *node) -+{ -+ int ret; -+ const u32 *chanid = of_get_property(node, STR_POOL_CHAN_RANGE, &ret); -+ if (!chanid) { -+ pr_err(STR_ERR_NOPROP, STR_POOL_CHAN_RANGE, node->full_name); -+ return -EINVAL; -+ } -+ if (ret != 8) { -+ pr_err(STR_ERR_CELL, STR_POOL_CHAN_RANGE, 1, node->full_name); -+ return -EINVAL; -+ } -+ for (ret = 0; ret < be32_to_cpu(chanid[1]); ret++) -+ pools_sdqcr |= QM_SDQCR_CHANNELS_POOL_CONV(be32_to_cpu(chanid[0]) + ret); -+ return 0; -+} -+ -+/* A "fsl,pool-channel-range" node; release the given range to the allocator */ -+static __init int fsl_pool_channel_range_init(struct device_node *node) -+{ -+ int ret; -+ const u32 *chanid = of_get_property(node, STR_POOL_CHAN_RANGE, &ret); -+ if (!chanid) { -+ pr_err(STR_ERR_NOPROP, STR_POOL_CHAN_RANGE, node->full_name); -+ return -EINVAL; -+ } -+ if (ret != 8) { -+ pr_err(STR_ERR_CELL, STR_POOL_CHAN_RANGE, 1, node->full_name); -+ return -EINVAL; -+ } -+ qman_seed_pool_range(be32_to_cpu(chanid[0]), be32_to_cpu(chanid[1])); -+ pr_info("Qman: pool channel allocator includes range %d:%d\n", -+ be32_to_cpu(chanid[0]), be32_to_cpu(chanid[1])); -+ return 0; -+} -+ -+/* A "fsl,cgrid-range" node; release the given range to the allocator */ -+static __init int fsl_cgrid_range_init(struct device_node *node) -+{ -+ struct qman_cgr cgr; -+ int ret, errors = 0; -+ const u32 *range = of_get_property(node, STR_CGRID_RANGE, &ret); -+ if (!range) { -+ pr_err(STR_ERR_NOPROP, STR_CGRID_RANGE, node->full_name); -+ return -EINVAL; -+ } -+ if (ret != 8) { -+ pr_err(STR_ERR_CELL, STR_CGRID_RANGE, 2, node->full_name); -+ return -EINVAL; -+ } -+ qman_seed_cgrid_range(be32_to_cpu(range[0]), be32_to_cpu(range[1])); -+ pr_info("Qman: CGRID allocator includes range %d:%d\n", -+ be32_to_cpu(range[0]), be32_to_cpu(range[1])); -+ for (cgr.cgrid = 0; cgr.cgrid < __CGR_NUM; cgr.cgrid++) { -+ ret = qman_modify_cgr(&cgr, QMAN_CGR_FLAG_USE_INIT, NULL); -+ if (ret) -+ errors++; -+ } -+ if (errors) -+ pr_err("Warning: %d error%s while initialising CGRs %d:%d\n", -+ errors, (errors > 1) ? "s" : "", range[0], range[1]); -+ return 0; -+} -+ -+static __init int fsl_ceetm_init(struct device_node *node) -+{ -+ enum qm_dc_portal dcp_portal; -+ struct qm_ceetm_sp *sp; -+ struct qm_ceetm_lni *lni; -+ int ret, i; -+ const u32 *range; -+ -+ /* Find LFQID range */ -+ range = of_get_property(node, "fsl,ceetm-lfqid-range", &ret); -+ if (!range) { -+ pr_err("No fsl,ceetm-lfqid-range in node %s\n", -+ node->full_name); -+ return -EINVAL; -+ } -+ if (ret != 8) { -+ pr_err("fsl,ceetm-lfqid-range is not a 2-cell range in node" -+ " %s\n", node->full_name); -+ return -EINVAL; -+ } -+ -+ dcp_portal = (be32_to_cpu(range[0]) & 0x0F0000) >> 16; -+ if (dcp_portal > qm_dc_portal_fman1) { -+ pr_err("The DCP portal %d doesn't support CEETM\n", dcp_portal); -+ return -EINVAL; -+ } -+ -+ if (dcp_portal == qm_dc_portal_fman0) -+ qman_seed_ceetm0_lfqid_range(be32_to_cpu(range[0]), be32_to_cpu(range[1])); -+ if (dcp_portal == qm_dc_portal_fman1) -+ qman_seed_ceetm1_lfqid_range(be32_to_cpu(range[0]), be32_to_cpu(range[1])); -+ pr_debug("Qman: The lfqid allocator of CEETM %d includes range" -+ " 0x%x:0x%x\n", dcp_portal, be32_to_cpu(range[0]), be32_to_cpu(range[1])); -+ -+ qman_ceetms[dcp_portal].idx = dcp_portal; -+ INIT_LIST_HEAD(&qman_ceetms[dcp_portal].sub_portals); -+ INIT_LIST_HEAD(&qman_ceetms[dcp_portal].lnis); -+ -+ /* Find Sub-portal range */ -+ range = of_get_property(node, "fsl,ceetm-sp-range", &ret); -+ if (!range) { -+ pr_err("No fsl,ceetm-sp-range in node %s\n", node->full_name); -+ return -EINVAL; -+ } -+ if (ret != 8) { -+ pr_err("fsl,ceetm-sp-range is not a 2-cell range in node %s\n", -+ node->full_name); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < be32_to_cpu(range[1]); i++) { -+ sp = kzalloc(sizeof(*sp), GFP_KERNEL); -+ if (!sp) { -+ pr_err("Can't alloc memory for sub-portal %d\n", -+ range[0] + i); -+ return -ENOMEM; -+ } -+ sp->idx = be32_to_cpu(range[0]) + i; -+ sp->dcp_idx = dcp_portal; -+ sp->is_claimed = 0; -+ list_add_tail(&sp->node, &qman_ceetms[dcp_portal].sub_portals); -+ sp++; -+ } -+ pr_debug("Qman: Reserve sub-portal %d:%d for CEETM %d\n", -+ be32_to_cpu(range[0]), be32_to_cpu(range[1]), dcp_portal); -+ qman_ceetms[dcp_portal].sp_range[0] = be32_to_cpu(range[0]); -+ qman_ceetms[dcp_portal].sp_range[1] = be32_to_cpu(range[1]); -+ -+ /* Find LNI range */ -+ range = of_get_property(node, "fsl,ceetm-lni-range", &ret); -+ if (!range) { -+ pr_err("No fsl,ceetm-lni-range in node %s\n", node->full_name); -+ return -EINVAL; -+ } -+ if (ret != 8) { -+ pr_err("fsl,ceetm-lni-range is not a 2-cell range in node %s\n", -+ node->full_name); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < be32_to_cpu(range[1]); i++) { -+ lni = kzalloc(sizeof(*lni), GFP_KERNEL); -+ if (!lni) { -+ pr_err("Can't alloc memory for LNI %d\n", -+ range[0] + i); -+ return -ENOMEM; -+ } -+ lni->idx = be32_to_cpu(range[0]) + i; -+ lni->dcp_idx = dcp_portal; -+ lni->is_claimed = 0; -+ INIT_LIST_HEAD(&lni->channels); -+ list_add_tail(&lni->node, &qman_ceetms[dcp_portal].lnis); -+ lni++; -+ } -+ pr_debug("Qman: Reserve LNI %d:%d for CEETM %d\n", -+ be32_to_cpu(range[0]), be32_to_cpu(range[1]), dcp_portal); -+ qman_ceetms[dcp_portal].lni_range[0] = be32_to_cpu(range[0]); -+ qman_ceetms[dcp_portal].lni_range[1] = be32_to_cpu(range[1]); -+ -+ /* Find CEETM channel range */ -+ range = of_get_property(node, "fsl,ceetm-channel-range", &ret); -+ if (!range) { -+ pr_err("No fsl,ceetm-channel-range in node %s\n", -+ node->full_name); -+ return -EINVAL; -+ } -+ if (ret != 8) { -+ pr_err("fsl,ceetm-channel-range is not a 2-cell range in node" -+ "%s\n", node->full_name); -+ return -EINVAL; -+ } -+ -+ if (dcp_portal == qm_dc_portal_fman0) -+ qman_seed_ceetm0_channel_range(be32_to_cpu(range[0]), be32_to_cpu(range[1])); -+ if (dcp_portal == qm_dc_portal_fman1) -+ qman_seed_ceetm1_channel_range(be32_to_cpu(range[0]), be32_to_cpu(range[1])); -+ pr_debug("Qman: The channel allocator of CEETM %d includes" -+ " range %d:%d\n", dcp_portal, be32_to_cpu(range[0]), be32_to_cpu(range[1])); -+ -+ /* Set CEETM PRES register */ -+ ret = qman_ceetm_set_prescaler(dcp_portal); -+ if (ret) -+ return ret; -+ return 0; -+} -+ -+static void qman_get_ip_revision(struct device_node *dn) -+{ -+ u16 ip_rev = 0; -+ u8 ip_cfg = QMAN_REV_CFG_0; -+ for_each_compatible_node(dn, NULL, "fsl,qman-portal") { -+ if (!of_device_is_available(dn)) -+ continue; -+ if (of_device_is_compatible(dn, "fsl,qman-portal-1.0") || -+ of_device_is_compatible(dn, "fsl,qman-portal-1.0.0")) { -+ pr_err("QMAN rev1.0 on P4080 rev1 is not supported!\n"); -+ BUG_ON(1); -+ } else if (of_device_is_compatible(dn, "fsl,qman-portal-1.1") || -+ of_device_is_compatible(dn, "fsl,qman-portal-1.1.0")) { -+ ip_rev = QMAN_REV11; -+ qman_portal_max = 10; -+ } else if (of_device_is_compatible(dn, "fsl,qman-portal-1.2") || -+ of_device_is_compatible(dn, "fsl,qman-portal-1.2.0")) { -+ ip_rev = QMAN_REV12; -+ qman_portal_max = 10; -+ } else if (of_device_is_compatible(dn, "fsl,qman-portal-2.0") || -+ of_device_is_compatible(dn, "fsl,qman-portal-2.0.0")) { -+ ip_rev = QMAN_REV20; -+ qman_portal_max = 3; -+ } else if (of_device_is_compatible(dn, -+ "fsl,qman-portal-3.0.0")) { -+ ip_rev = QMAN_REV30; -+ qman_portal_max = 50; -+ } else if (of_device_is_compatible(dn, -+ "fsl,qman-portal-3.0.1")) { -+ ip_rev = QMAN_REV30; -+ qman_portal_max = 25; -+ ip_cfg = QMAN_REV_CFG_1; -+ } else if (of_device_is_compatible(dn, -+ "fsl,qman-portal-3.1.0")) { -+ ip_rev = QMAN_REV31; -+ qman_portal_max = 50; -+ } else if (of_device_is_compatible(dn, -+ "fsl,qman-portal-3.1.1")) { -+ ip_rev = QMAN_REV31; -+ qman_portal_max = 25; -+ ip_cfg = QMAN_REV_CFG_1; -+ } else if (of_device_is_compatible(dn, -+ "fsl,qman-portal-3.1.2")) { -+ ip_rev = QMAN_REV31; -+ qman_portal_max = 18; -+ ip_cfg = QMAN_REV_CFG_2; -+ } else if (of_device_is_compatible(dn, -+ "fsl,qman-portal-3.1.3")) { -+ ip_rev = QMAN_REV31; -+ qman_portal_max = 10; -+ ip_cfg = QMAN_REV_CFG_3; -+ } else if (of_device_is_compatible(dn, -+ "fsl,qman-portal-3.2.0")) { -+ ip_rev = QMAN_REV32; -+ qman_portal_max = 10; -+ ip_cfg = QMAN_REV_CFG_3; // TODO: Verify for ls1043 -+ } else { -+ pr_warn("unknown QMan version in portal node," -+ "default to rev1.1\n"); -+ ip_rev = QMAN_REV11; -+ qman_portal_max = 10; -+ } -+ -+ if (!qman_ip_rev) { -+ if (ip_rev) { -+ qman_ip_rev = ip_rev; -+ qman_ip_cfg = ip_cfg; -+ } else { -+ pr_warn("unknown Qman version," -+ " default to rev1.1\n"); -+ qman_ip_rev = QMAN_REV11; -+ qman_ip_cfg = QMAN_REV_CFG_0; -+ } -+ } else if (ip_rev && (qman_ip_rev != ip_rev)) -+ pr_warn("Revision=0x%04x, but portal '%s' has" -+ " 0x%04x\n", -+ qman_ip_rev, dn->full_name, ip_rev); -+ if (qman_ip_rev == ip_rev) -+ break; -+ } -+} -+ -+/* Parse a portal node, perform generic mapping duties and return the config. It -+ * is not known at this stage for what purpose (or even if) the portal will be -+ * used. */ -+static struct qm_portal_config * __init parse_pcfg(struct device_node *node) -+{ -+ struct qm_portal_config *pcfg; -+ const u32 *index_p, *channel_p; -+ u32 index, channel; -+ int irq, ret; -+ resource_size_t len; -+ -+ pcfg = kmalloc(sizeof(*pcfg), GFP_KERNEL); -+ if (!pcfg) { -+ pr_err("can't allocate portal config"); -+ return NULL; -+ } -+ -+ /* -+ * This is a *horrible hack*, but the IOMMU/PAMU driver needs a -+ * 'struct device' in order to get the PAMU stashing setup and the QMan -+ * portal [driver] won't function at all without ring stashing -+ * -+ * Making the QMan portal driver nice and proper is part of the -+ * upstreaming effort -+ */ -+ pcfg->dev.bus = &platform_bus_type; -+ pcfg->dev.of_node = node; -+#ifdef CONFIG_FSL_PAMU -+ pcfg->dev.archdata.iommu_domain = NULL; -+#endif -+ -+ ret = of_address_to_resource(node, DPA_PORTAL_CE, -+ &pcfg->addr_phys[DPA_PORTAL_CE]); -+ if (ret) { -+ pr_err("Can't get %s property '%s'\n", node->full_name, -+ "reg::CE"); -+ goto err; -+ } -+ ret = of_address_to_resource(node, DPA_PORTAL_CI, -+ &pcfg->addr_phys[DPA_PORTAL_CI]); -+ if (ret) { -+ pr_err("Can't get %s property '%s'\n", node->full_name, -+ "reg::CI"); -+ goto err; -+ } -+ index_p = of_get_property(node, "cell-index", &ret); -+ if (!index_p || (ret != 4)) { -+ pr_err("Can't get %s property '%s'\n", node->full_name, -+ "cell-index"); -+ goto err; -+ } -+ index = be32_to_cpu(*index_p); -+ if (index >= qman_portal_max) { -+ pr_err("QMan portal index %d is beyond max (%d)\n", -+ index, qman_portal_max); -+ goto err; -+ } -+ -+ channel_p = of_get_property(node, "fsl,qman-channel-id", &ret); -+ if (!channel_p || (ret != 4)) { -+ pr_err("Can't get %s property '%s'\n", node->full_name, -+ "fsl,qman-channel-id"); -+ goto err; -+ } -+ channel = be32_to_cpu(*channel_p); -+ if (channel != (index + QM_CHANNEL_SWPORTAL0)) -+ pr_err("Warning: node %s has mismatched %s and %s\n", -+ node->full_name, "cell-index", "fsl,qman-channel-id"); -+ pcfg->public_cfg.channel = channel; -+ pcfg->public_cfg.cpu = -1; -+ irq = irq_of_parse_and_map(node, 0); -+ if (irq == 0) { -+ pr_err("Can't get %s property '%s'\n", node->full_name, -+ "interrupts"); -+ goto err; -+ } -+ pcfg->public_cfg.irq = irq; -+ pcfg->public_cfg.index = index; -+#ifdef CONFIG_FSL_QMAN_CONFIG -+ /* We need the same LIODN offset for all portals */ -+ qman_liodn_fixup(pcfg->public_cfg.channel); -+#endif -+ -+ len = resource_size(&pcfg->addr_phys[DPA_PORTAL_CE]); -+ if (len != (unsigned long)len) -+ goto err; -+ -+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) -+ pcfg->addr_virt[DPA_PORTAL_CE] = ioremap_cache_ns( -+ pcfg->addr_phys[DPA_PORTAL_CE].start, -+ resource_size(&pcfg->addr_phys[DPA_PORTAL_CE])); -+ -+ pcfg->addr_virt[DPA_PORTAL_CI] = ioremap( -+ pcfg->addr_phys[DPA_PORTAL_CI].start, -+ resource_size(&pcfg->addr_phys[DPA_PORTAL_CI])); -+#else -+ pcfg->addr_virt[DPA_PORTAL_CE] = ioremap_prot( -+ pcfg->addr_phys[DPA_PORTAL_CE].start, -+ (unsigned long)len, -+ 0); -+ pcfg->addr_virt[DPA_PORTAL_CI] = ioremap_prot( -+ pcfg->addr_phys[DPA_PORTAL_CI].start, -+ resource_size(&pcfg->addr_phys[DPA_PORTAL_CI]), -+ _PAGE_GUARDED | _PAGE_NO_CACHE); -+#endif -+ return pcfg; -+err: -+ kfree(pcfg); -+ return NULL; -+} -+ -+static struct qm_portal_config *get_pcfg(struct list_head *list) -+{ -+ struct qm_portal_config *pcfg; -+ if (list_empty(list)) -+ return NULL; -+ pcfg = list_entry(list->prev, struct qm_portal_config, list); -+ list_del(&pcfg->list); -+ return pcfg; -+} -+ -+static struct qm_portal_config *get_pcfg_idx(struct list_head *list, u32 idx) -+{ -+ struct qm_portal_config *pcfg; -+ if (list_empty(list)) -+ return NULL; -+ list_for_each_entry(pcfg, list, list) { -+ if (pcfg->public_cfg.index == idx) { -+ list_del(&pcfg->list); -+ return pcfg; -+ } -+ } -+ return NULL; -+} -+ -+static void portal_set_cpu(struct qm_portal_config *pcfg, int cpu) -+{ -+#ifdef CONFIG_FSL_PAMU -+ int ret; -+ int window_count = 1; -+ struct iommu_domain_geometry geom_attr; -+ struct pamu_stash_attribute stash_attr; -+ -+ pcfg->iommu_domain = iommu_domain_alloc(&platform_bus_type); -+ if (!pcfg->iommu_domain) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_domain_alloc() failed", -+ __func__); -+ goto _no_iommu; -+ } -+ geom_attr.aperture_start = 0; -+ geom_attr.aperture_end = -+ ((dma_addr_t)1 << min(8 * sizeof(dma_addr_t), (size_t)36)) - 1; -+ geom_attr.force_aperture = true; -+ ret = iommu_domain_set_attr(pcfg->iommu_domain, DOMAIN_ATTR_GEOMETRY, -+ &geom_attr); -+ if (ret < 0) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_domain_set_attr() = %d", -+ __func__, ret); -+ goto _iommu_domain_free; -+ } -+ ret = iommu_domain_set_attr(pcfg->iommu_domain, DOMAIN_ATTR_WINDOWS, -+ &window_count); -+ if (ret < 0) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_domain_set_attr() = %d", -+ __func__, ret); -+ goto _iommu_domain_free; -+ } -+ stash_attr.cpu = cpu; -+ stash_attr.cache = PAMU_ATTR_CACHE_L1; -+ /* set stash information for the window */ -+ stash_attr.window = 0; -+ ret = iommu_domain_set_attr(pcfg->iommu_domain, -+ DOMAIN_ATTR_FSL_PAMU_STASH, -+ &stash_attr); -+ if (ret < 0) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_domain_set_attr() = %d", -+ __func__, ret); -+ goto _iommu_domain_free; -+ } -+ ret = iommu_domain_window_enable(pcfg->iommu_domain, 0, 0, 1ULL << 36, -+ IOMMU_READ | IOMMU_WRITE); -+ if (ret < 0) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_domain_window_enable() = %d", -+ __func__, ret); -+ goto _iommu_domain_free; -+ } -+ ret = iommu_attach_device(pcfg->iommu_domain, &pcfg->dev); -+ if (ret < 0) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_device_attach() = %d", -+ __func__, ret); -+ goto _iommu_domain_free; -+ } -+ ret = iommu_domain_set_attr(pcfg->iommu_domain, -+ DOMAIN_ATTR_FSL_PAMU_ENABLE, -+ &window_count); -+ if (ret < 0) { -+ pr_err(KBUILD_MODNAME ":%s(): iommu_domain_set_attr() = %d", -+ __func__, ret); -+ goto _iommu_detach_device; -+ } -+ -+_no_iommu: -+#endif -+#ifdef CONFIG_FSL_QMAN_CONFIG -+ if (qman_set_sdest(pcfg->public_cfg.channel, cpu)) -+#endif -+ pr_warn("Failed to set QMan portal's stash request queue\n"); -+ -+ return; -+ -+#ifdef CONFIG_FSL_PAMU -+_iommu_detach_device: -+ iommu_detach_device(pcfg->iommu_domain, NULL); -+_iommu_domain_free: -+ iommu_domain_free(pcfg->iommu_domain); -+#endif -+} -+ -+struct qm_portal_config *qm_get_unused_portal_idx(u32 idx) -+{ -+ struct qm_portal_config *ret; -+ spin_lock(&unused_pcfgs_lock); -+ if (idx == QBMAN_ANY_PORTAL_IDX) -+ ret = get_pcfg(&unused_pcfgs); -+ else -+ ret = get_pcfg_idx(&unused_pcfgs, idx); -+ spin_unlock(&unused_pcfgs_lock); -+ /* Bind stashing LIODNs to the CPU we are currently executing on, and -+ * set the portal to use the stashing request queue corresonding to the -+ * cpu as well. The user-space driver assumption is that the pthread has -+ * to already be affine to one cpu only before opening a portal. If that -+ * check is circumvented, the only risk is a performance degradation - -+ * stashing will go to whatever cpu they happened to be running on when -+ * opening the device file, and if that isn't the cpu they subsequently -+ * bind to and do their polling on, tough. */ -+ if (ret) -+ portal_set_cpu(ret, hard_smp_processor_id()); -+ return ret; -+} -+ -+struct qm_portal_config *qm_get_unused_portal(void) -+{ -+ return qm_get_unused_portal_idx(QBMAN_ANY_PORTAL_IDX); -+} -+ -+void qm_put_unused_portal(struct qm_portal_config *pcfg) -+{ -+ spin_lock(&unused_pcfgs_lock); -+ list_add(&pcfg->list, &unused_pcfgs); -+ spin_unlock(&unused_pcfgs_lock); -+} -+ -+static struct qman_portal *init_pcfg(struct qm_portal_config *pcfg) -+{ -+ struct qman_portal *p; -+ -+ pcfg->iommu_domain = NULL; -+ portal_set_cpu(pcfg, pcfg->public_cfg.cpu); -+ p = qman_create_affine_portal(pcfg, NULL); -+ if (p) { -+ u32 irq_sources = 0; -+ /* Determine what should be interrupt-vs-poll driven */ -+#ifdef CONFIG_FSL_DPA_PIRQ_SLOW -+ irq_sources |= QM_PIRQ_EQCI | QM_PIRQ_EQRI | QM_PIRQ_MRI | -+ QM_PIRQ_CSCI | QM_PIRQ_CCSCI; -+#endif -+#ifdef CONFIG_FSL_DPA_PIRQ_FAST -+ irq_sources |= QM_PIRQ_DQRI; -+#endif -+ qman_p_irqsource_add(p, irq_sources); -+ pr_info("Qman portal %sinitialised, cpu %d\n", -+ pcfg->public_cfg.is_shared ? "(shared) " : "", -+ pcfg->public_cfg.cpu); -+ } else -+ pr_crit("Qman portal failure on cpu %d\n", -+ pcfg->public_cfg.cpu); -+ return p; -+} -+ -+static void init_slave(int cpu) -+{ -+ struct qman_portal *p; -+ struct cpumask oldmask = *tsk_cpus_allowed(current); -+ set_cpus_allowed_ptr(current, get_cpu_mask(cpu)); -+ p = qman_create_affine_slave(shared_portals[shared_portals_idx++], cpu); -+ if (!p) -+ pr_err("Qman slave portal failure on cpu %d\n", cpu); -+ else -+ pr_info("Qman portal %sinitialised, cpu %d\n", "(slave) ", cpu); -+ set_cpus_allowed_ptr(current, &oldmask); -+ if (shared_portals_idx >= num_shared_portals) -+ shared_portals_idx = 0; -+} -+ -+static struct cpumask want_unshared __initdata; -+static struct cpumask want_shared __initdata; -+ -+static int __init parse_qportals(char *str) -+{ -+ return parse_portals_bootarg(str, &want_shared, &want_unshared, -+ "qportals"); -+} -+__setup("qportals=", parse_qportals); -+ -+static void qman_portal_update_sdest(const struct qm_portal_config *pcfg, -+ unsigned int cpu) -+{ -+#ifdef CONFIG_FSL_PAMU -+ struct pamu_stash_attribute stash_attr; -+ int ret; -+ -+ if (pcfg->iommu_domain) { -+ stash_attr.cpu = cpu; -+ stash_attr.cache = PAMU_ATTR_CACHE_L1; -+ /* set stash information for the window */ -+ stash_attr.window = 0; -+ ret = iommu_domain_set_attr(pcfg->iommu_domain, -+ DOMAIN_ATTR_FSL_PAMU_STASH, &stash_attr); -+ if (ret < 0) { -+ pr_err("Failed to update pamu stash setting\n"); -+ return; -+ } -+ } -+#endif -+#ifdef CONFIG_FSL_QMAN_CONFIG -+ if (qman_set_sdest(pcfg->public_cfg.channel, cpu)) -+ pr_warn("Failed to update portal's stash request queue\n"); -+#endif -+} -+ -+static void qman_offline_cpu(unsigned int cpu) -+{ -+ struct qman_portal *p; -+ const struct qm_portal_config *pcfg; -+ p = (struct qman_portal *)affine_portals[cpu]; -+ if (p) { -+ pcfg = qman_get_qm_portal_config(p); -+ if (pcfg) { -+ irq_set_affinity(pcfg->public_cfg.irq, cpumask_of(0)); -+ qman_portal_update_sdest(pcfg, 0); -+ } -+ } -+} -+ -+#ifdef CONFIG_HOTPLUG_CPU -+static void qman_online_cpu(unsigned int cpu) -+{ -+ struct qman_portal *p; -+ const struct qm_portal_config *pcfg; -+ p = (struct qman_portal *)affine_portals[cpu]; -+ if (p) { -+ pcfg = qman_get_qm_portal_config(p); -+ if (pcfg) { -+ irq_set_affinity(pcfg->public_cfg.irq, cpumask_of(cpu)); -+ qman_portal_update_sdest(pcfg, cpu); -+ } -+ } -+} -+ -+static int qman_hotplug_cpu_callback(struct notifier_block *nfb, -+ unsigned long action, void *hcpu) -+{ -+ unsigned int cpu = (unsigned long)hcpu; -+ -+ switch (action) { -+ case CPU_ONLINE: -+ case CPU_ONLINE_FROZEN: -+ qman_online_cpu(cpu); -+ break; -+ case CPU_DOWN_PREPARE: -+ case CPU_DOWN_PREPARE_FROZEN: -+ qman_offline_cpu(cpu); -+ default: -+ break; -+ } -+ return NOTIFY_OK; -+} -+ -+static struct notifier_block qman_hotplug_cpu_notifier = { -+ .notifier_call = qman_hotplug_cpu_callback, -+}; -+#endif /* CONFIG_HOTPLUG_CPU */ -+ -+__init int qman_init(void) -+{ -+ struct cpumask slave_cpus; -+ struct cpumask unshared_cpus = *cpu_none_mask; -+ struct cpumask shared_cpus = *cpu_none_mask; -+ LIST_HEAD(unshared_pcfgs); -+ LIST_HEAD(shared_pcfgs); -+ struct device_node *dn; -+ struct qm_portal_config *pcfg; -+ struct qman_portal *p; -+ int cpu, ret; -+ const u32 *clk; -+ struct cpumask offline_cpus; -+ -+ /* Initialise the Qman (CCSR) device */ -+ for_each_compatible_node(dn, NULL, "fsl,qman") { -+ if (!qman_init_ccsr(dn)) -+ pr_info("Qman err interrupt handler present\n"); -+ else -+ pr_err("Qman CCSR setup failed\n"); -+ -+ clk = of_get_property(dn, "clock-frequency", NULL); -+ if (!clk) -+ pr_warn("Can't find Qman clock frequency\n"); -+ else -+ qman_clk = be32_to_cpu(*clk); -+ } -+#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP -+ /* Setup lookup table for FQ demux */ -+ ret = qman_setup_fq_lookup_table(get_qman_fqd_size()/64); -+ if (ret) -+ return ret; -+#endif -+ -+ /* Get qman ip revision */ -+ qman_get_ip_revision(dn); -+ if ((qman_ip_rev & 0xff00) >= QMAN_REV30) { -+ qm_channel_pool1 = QMAN_CHANNEL_POOL1_REV3; -+ qm_channel_caam = QMAN_CHANNEL_CAAM_REV3; -+ qm_channel_pme = QMAN_CHANNEL_PME_REV3; -+ } -+ -+ if ((qman_ip_rev == QMAN_REV31) && (qman_ip_cfg == QMAN_REV_CFG_2)) -+ qm_channel_dce = QMAN_CHANNEL_DCE_QMANREV312; -+ -+ /* -+ * Parse the ceetm node to get how many ceetm instances are supported -+ * on the current silicon. num_ceetms must be confirmed before portals -+ * are intiailized. -+ */ -+ num_ceetms = 0; -+ for_each_compatible_node(dn, NULL, "fsl,qman-ceetm") -+ num_ceetms++; -+ -+ /* Parse pool channels into the SDQCR mask. (Must happen before portals -+ * are initialised.) */ -+ for_each_compatible_node(dn, NULL, "fsl,pool-channel-range") { -+ ret = fsl_pool_channel_range_sdqcr(dn); -+ if (ret) -+ return ret; -+ } -+ -+ memset(affine_portals, 0, sizeof(void *) * num_possible_cpus()); -+ /* Initialise portals. See bman_driver.c for comments */ -+ for_each_compatible_node(dn, NULL, "fsl,qman-portal") { -+ if (!of_device_is_available(dn)) -+ continue; -+ pcfg = parse_pcfg(dn); -+ if (pcfg) { -+ pcfg->public_cfg.pools = pools_sdqcr; -+ list_add_tail(&pcfg->list, &unused_pcfgs); -+ } -+ } -+ for_each_possible_cpu(cpu) { -+ if (cpumask_test_cpu(cpu, &want_shared)) { -+ pcfg = get_pcfg(&unused_pcfgs); -+ if (!pcfg) -+ break; -+ pcfg->public_cfg.cpu = cpu; -+ list_add_tail(&pcfg->list, &shared_pcfgs); -+ cpumask_set_cpu(cpu, &shared_cpus); -+ } -+ if (cpumask_test_cpu(cpu, &want_unshared)) { -+ if (cpumask_test_cpu(cpu, &shared_cpus)) -+ continue; -+ pcfg = get_pcfg(&unused_pcfgs); -+ if (!pcfg) -+ break; -+ pcfg->public_cfg.cpu = cpu; -+ list_add_tail(&pcfg->list, &unshared_pcfgs); -+ cpumask_set_cpu(cpu, &unshared_cpus); -+ } -+ } -+ if (list_empty(&shared_pcfgs) && list_empty(&unshared_pcfgs)) { -+ for_each_online_cpu(cpu) { -+ pcfg = get_pcfg(&unused_pcfgs); -+ if (!pcfg) -+ break; -+ pcfg->public_cfg.cpu = cpu; -+ list_add_tail(&pcfg->list, &unshared_pcfgs); -+ cpumask_set_cpu(cpu, &unshared_cpus); -+ } -+ } -+ cpumask_andnot(&slave_cpus, cpu_possible_mask, &shared_cpus); -+ cpumask_andnot(&slave_cpus, &slave_cpus, &unshared_cpus); -+ if (cpumask_empty(&slave_cpus)) { -+ if (!list_empty(&shared_pcfgs)) { -+ cpumask_or(&unshared_cpus, &unshared_cpus, -+ &shared_cpus); -+ cpumask_clear(&shared_cpus); -+ list_splice_tail(&shared_pcfgs, &unshared_pcfgs); -+ INIT_LIST_HEAD(&shared_pcfgs); -+ } -+ } else { -+ if (list_empty(&shared_pcfgs)) { -+ pcfg = get_pcfg(&unshared_pcfgs); -+ if (!pcfg) { -+ pr_crit("No QMan portals available!\n"); -+ return 0; -+ } -+ cpumask_clear_cpu(pcfg->public_cfg.cpu, &unshared_cpus); -+ cpumask_set_cpu(pcfg->public_cfg.cpu, &shared_cpus); -+ list_add_tail(&pcfg->list, &shared_pcfgs); -+ } -+ } -+ list_for_each_entry(pcfg, &unshared_pcfgs, list) { -+ pcfg->public_cfg.is_shared = 0; -+ p = init_pcfg(pcfg); -+ if (!p) { -+ pr_crit("Unable to configure portals\n"); -+ return 0; -+ } -+ } -+ list_for_each_entry(pcfg, &shared_pcfgs, list) { -+ pcfg->public_cfg.is_shared = 1; -+ p = init_pcfg(pcfg); -+ if (p) -+ shared_portals[num_shared_portals++] = p; -+ } -+ if (!cpumask_empty(&slave_cpus)) -+ for_each_cpu(cpu, &slave_cpus) -+ init_slave(cpu); -+ pr_info("Qman portals initialised\n"); -+ cpumask_andnot(&offline_cpus, cpu_possible_mask, cpu_online_mask); -+ for_each_cpu(cpu, &offline_cpus) -+ qman_offline_cpu(cpu); -+#ifdef CONFIG_HOTPLUG_CPU -+ register_hotcpu_notifier(&qman_hotplug_cpu_notifier); -+#endif -+ return 0; -+} -+ -+__init int qman_resource_init(void) -+{ -+ struct device_node *dn; -+ int ret; -+ -+ /* Initialise FQID allocation ranges */ -+ for_each_compatible_node(dn, NULL, "fsl,fqid-range") { -+ ret = fsl_fqid_range_init(dn); -+ if (ret) -+ return ret; -+ } -+ /* Initialise CGRID allocation ranges */ -+ for_each_compatible_node(dn, NULL, "fsl,cgrid-range") { -+ ret = fsl_cgrid_range_init(dn); -+ if (ret) -+ return ret; -+ } -+ /* Parse pool channels into the allocator. (Must happen after portals -+ * are initialised.) */ -+ for_each_compatible_node(dn, NULL, "fsl,pool-channel-range") { -+ ret = fsl_pool_channel_range_init(dn); -+ if (ret) -+ return ret; -+ } -+ -+ /* Parse CEETM */ -+ for_each_compatible_node(dn, NULL, "fsl,qman-ceetm") { -+ ret = fsl_ceetm_init(dn); -+ if (ret) -+ return ret; -+ } -+ return 0; -+} -+ -+#ifdef CONFIG_SUSPEND -+void suspend_unused_qportal(void) -+{ -+ struct qm_portal_config *pcfg; -+ -+ if (list_empty(&unused_pcfgs)) -+ return; -+ -+ list_for_each_entry(pcfg, &unused_pcfgs, list) { -+#ifdef CONFIG_PM_DEBUG -+ pr_info("Need to save qportal %d\n", pcfg->public_cfg.index); -+#endif -+ /* save isdr, disable all via isdr, clear isr */ -+ pcfg->saved_isdr = -+ __raw_readl(pcfg->addr_virt[DPA_PORTAL_CI] + 0xe08); -+ __raw_writel(0xffffffff, pcfg->addr_virt[DPA_PORTAL_CI] + -+ 0xe08); -+ __raw_writel(0xffffffff, pcfg->addr_virt[DPA_PORTAL_CI] + -+ 0xe00); -+ } -+ return; -+} -+ -+void resume_unused_qportal(void) -+{ -+ struct qm_portal_config *pcfg; -+ -+ if (list_empty(&unused_pcfgs)) -+ return; -+ -+ list_for_each_entry(pcfg, &unused_pcfgs, list) { -+#ifdef CONFIG_PM_DEBUG -+ pr_info("Need to resume qportal %d\n", pcfg->public_cfg.index); -+#endif -+ /* restore isdr */ -+ __raw_writel(pcfg->saved_isdr, -+ pcfg->addr_virt[DPA_PORTAL_CI] + 0xe08); -+ } -+ return; -+} -+#endif -+ ---- /dev/null -+++ b/drivers/staging/fsl_qbman/qman_high.c -@@ -0,0 +1,5568 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "qman_low.h" -+ -+/* Compilation constants */ -+#define DQRR_MAXFILL 15 -+#define EQCR_ITHRESH 4 /* if EQCR congests, interrupt threshold */ -+#define IRQNAME "QMan portal %d" -+#define MAX_IRQNAME 16 /* big enough for "QMan portal %d" */ -+ -+/* Divide 'n' by 'd', rounding down if 'r' is negative, rounding up if it's -+ * positive, and rounding to the closest value if it's zero. NB, this macro -+ * implicitly upgrades parameters to unsigned 64-bit, so feed it with types -+ * that are compatible with this. NB, these arguments should not be expressions -+ * unless it is safe for them to be evaluated multiple times. Eg. do not pass -+ * in "some_value++" as a parameter to the macro! */ -+#define ROUNDING(n, d, r) \ -+ (((r) < 0) ? div64_u64((n), (d)) : \ -+ (((r) > 0) ? div64_u64(((n) + (d) - 1), (d)) : \ -+ div64_u64(((n) + ((d) / 2)), (d)))) -+ -+/* Lock/unlock frame queues, subject to the "LOCKED" flag. This is about -+ * inter-processor locking only. Note, FQLOCK() is always called either under a -+ * local_irq_save() or from interrupt context - hence there's no need for irq -+ * protection (and indeed, attempting to nest irq-protection doesn't work, as -+ * the "irq en/disable" machinery isn't recursive...). */ -+#define FQLOCK(fq) \ -+ do { \ -+ struct qman_fq *__fq478 = (fq); \ -+ if (fq_isset(__fq478, QMAN_FQ_FLAG_LOCKED)) \ -+ spin_lock(&__fq478->fqlock); \ -+ } while (0) -+#define FQUNLOCK(fq) \ -+ do { \ -+ struct qman_fq *__fq478 = (fq); \ -+ if (fq_isset(__fq478, QMAN_FQ_FLAG_LOCKED)) \ -+ spin_unlock(&__fq478->fqlock); \ -+ } while (0) -+ -+static inline void fq_set(struct qman_fq *fq, u32 mask) -+{ -+ set_bits(mask, &fq->flags); -+} -+static inline void fq_clear(struct qman_fq *fq, u32 mask) -+{ -+ clear_bits(mask, &fq->flags); -+} -+static inline int fq_isset(struct qman_fq *fq, u32 mask) -+{ -+ return fq->flags & mask; -+} -+static inline int fq_isclear(struct qman_fq *fq, u32 mask) -+{ -+ return !(fq->flags & mask); -+} -+ -+struct qman_portal { -+ struct qm_portal p; -+ unsigned long bits; /* PORTAL_BITS_*** - dynamic, strictly internal */ -+ unsigned long irq_sources; -+ u32 use_eqcr_ci_stashing; -+ u32 slowpoll; /* only used when interrupts are off */ -+ struct qman_fq *vdqcr_owned; /* only 1 volatile dequeue at a time */ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ struct qman_fq *eqci_owned; /* only 1 enqueue WAIT_SYNC at a time */ -+#endif -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ raw_spinlock_t sharing_lock; /* only used if is_shared */ -+ int is_shared; -+ struct qman_portal *sharing_redirect; -+#endif -+ u32 sdqcr; -+ int dqrr_disable_ref; -+ /* A portal-specific handler for DCP ERNs. If this is NULL, the global -+ * handler is called instead. */ -+ qman_cb_dc_ern cb_dc_ern; -+ /* When the cpu-affine portal is activated, this is non-NULL */ -+ const struct qm_portal_config *config; -+ /* This is needed for providing a non-NULL device to dma_map_***() */ -+ struct platform_device *pdev; -+ struct dpa_rbtree retire_table; -+ char irqname[MAX_IRQNAME]; -+ /* 2-element array. cgrs[0] is mask, cgrs[1] is snapshot. */ -+ struct qman_cgrs *cgrs; -+ /* linked-list of CSCN handlers. */ -+ struct list_head cgr_cbs; -+ /* list lock */ -+ spinlock_t cgr_lock; -+ /* 2-element array. ccgrs[0] is mask, ccgrs[1] is snapshot. */ -+ struct qman_ccgrs *ccgrs[QMAN_CEETM_MAX]; -+ /* 256-element array, each is a linked-list of CCSCN handlers. */ -+ struct list_head ccgr_cbs[QMAN_CEETM_MAX]; -+ /* list lock */ -+ spinlock_t ccgr_lock; -+ /* track if memory was allocated by the driver */ -+ u8 alloced; -+ /* power management data */ -+ u32 save_isdr; -+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ -+ /* Keep a shadow copy of the DQRR on LE systems -+ as the SW needs to do byteswaps of read only -+ memory. Must be aligned to the size of the -+ ring to ensure easy index calcualtions based -+ on address */ -+ struct qm_dqrr_entry shadow_dqrr[QM_DQRR_SIZE] -+ __attribute__((aligned(512))); -+#endif -+}; -+ -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+#define PORTAL_IRQ_LOCK(p, irqflags) \ -+ do { \ -+ if ((p)->is_shared) \ -+ raw_spin_lock_irqsave(&(p)->sharing_lock, irqflags); \ -+ else \ -+ local_irq_save(irqflags); \ -+ } while (0) -+#define PORTAL_IRQ_UNLOCK(p, irqflags) \ -+ do { \ -+ if ((p)->is_shared) \ -+ raw_spin_unlock_irqrestore(&(p)->sharing_lock, \ -+ irqflags); \ -+ else \ -+ local_irq_restore(irqflags); \ -+ } while (0) -+#else -+#define PORTAL_IRQ_LOCK(p, irqflags) local_irq_save(irqflags) -+#define PORTAL_IRQ_UNLOCK(p, irqflags) local_irq_restore(irqflags) -+#endif -+ -+/* Global handler for DCP ERNs. Used when the portal receiving the message does -+ * not have a portal-specific handler. */ -+static qman_cb_dc_ern cb_dc_ern; -+ -+static cpumask_t affine_mask; -+static DEFINE_SPINLOCK(affine_mask_lock); -+static u16 affine_channels[NR_CPUS]; -+static DEFINE_PER_CPU(struct qman_portal, qman_affine_portal); -+void *affine_portals[NR_CPUS]; -+ -+/* "raw" gets the cpu-local struct whether it's a redirect or not. */ -+static inline struct qman_portal *get_raw_affine_portal(void) -+{ -+ return &get_cpu_var(qman_affine_portal); -+} -+/* For ops that can redirect, this obtains the portal to use */ -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+static inline struct qman_portal *get_affine_portal(void) -+{ -+ struct qman_portal *p = get_raw_affine_portal(); -+ if (p->sharing_redirect) -+ return p->sharing_redirect; -+ return p; -+} -+#else -+#define get_affine_portal() get_raw_affine_portal() -+#endif -+/* For every "get", there must be a "put" */ -+static inline void put_affine_portal(void) -+{ -+ put_cpu_var(qman_affine_portal); -+} -+/* Exception: poll functions assume the caller is cpu-affine and in no risk of -+ * re-entrance, which are the two reasons we usually use the get/put_cpu_var() -+ * semantic - ie. to disable pre-emption. Some use-cases expect the execution -+ * context to remain as non-atomic during poll-triggered callbacks as it was -+ * when the poll API was first called (eg. NAPI), so we go out of our way in -+ * this case to not disable pre-emption. */ -+static inline struct qman_portal *get_poll_portal(void) -+{ -+ return &get_cpu_var(qman_affine_portal); -+} -+#define put_poll_portal() -+ -+/* This gives a FQID->FQ lookup to cover the fact that we can't directly demux -+ * retirement notifications (the fact they are sometimes h/w-consumed means that -+ * contextB isn't always a s/w demux - and as we can't know which case it is -+ * when looking at the notification, we have to use the slow lookup for all of -+ * them). NB, it's possible to have multiple FQ objects refer to the same FQID -+ * (though at most one of them should be the consumer), so this table isn't for -+ * all FQs - FQs are added when retirement commands are issued, and removed when -+ * they complete, which also massively reduces the size of this table. */ -+IMPLEMENT_DPA_RBTREE(fqtree, struct qman_fq, node, fqid); -+ -+/* This is what everything can wait on, even if it migrates to a different cpu -+ * to the one whose affine portal it is waiting on. */ -+static DECLARE_WAIT_QUEUE_HEAD(affine_queue); -+ -+static inline int table_push_fq(struct qman_portal *p, struct qman_fq *fq) -+{ -+ int ret = fqtree_push(&p->retire_table, fq); -+ if (ret) -+ pr_err("ERROR: double FQ-retirement %d\n", fq->fqid); -+ return ret; -+} -+ -+static inline void table_del_fq(struct qman_portal *p, struct qman_fq *fq) -+{ -+ fqtree_del(&p->retire_table, fq); -+} -+ -+static inline struct qman_fq *table_find_fq(struct qman_portal *p, u32 fqid) -+{ -+ return fqtree_find(&p->retire_table, fqid); -+} -+ -+#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP -+static void **qman_fq_lookup_table; -+static size_t qman_fq_lookup_table_size; -+ -+int qman_setup_fq_lookup_table(size_t num_entries) -+{ -+ num_entries++; -+ /* Allocate 1 more entry since the first entry is not used */ -+ qman_fq_lookup_table = vzalloc((num_entries * sizeof(void *))); -+ if (!qman_fq_lookup_table) { -+ pr_err("QMan: Could not allocate fq lookup table\n"); -+ return -ENOMEM; -+ } -+ qman_fq_lookup_table_size = num_entries; -+ pr_info("QMan: Allocated lookup table at %p, entry count %lu\n", -+ qman_fq_lookup_table, -+ (unsigned long)qman_fq_lookup_table_size); -+ return 0; -+} -+ -+/* global structure that maintains fq object mapping */ -+static DEFINE_SPINLOCK(fq_hash_table_lock); -+ -+static int find_empty_fq_table_entry(u32 *entry, struct qman_fq *fq) -+{ -+ u32 i; -+ -+ spin_lock(&fq_hash_table_lock); -+ /* Can't use index zero because this has special meaning -+ * in context_b field. */ -+ for (i = 1; i < qman_fq_lookup_table_size; i++) { -+ if (qman_fq_lookup_table[i] == NULL) { -+ *entry = i; -+ qman_fq_lookup_table[i] = fq; -+ spin_unlock(&fq_hash_table_lock); -+ return 0; -+ } -+ } -+ spin_unlock(&fq_hash_table_lock); -+ return -ENOMEM; -+} -+ -+static void clear_fq_table_entry(u32 entry) -+{ -+ spin_lock(&fq_hash_table_lock); -+ BUG_ON(entry >= qman_fq_lookup_table_size); -+ qman_fq_lookup_table[entry] = NULL; -+ spin_unlock(&fq_hash_table_lock); -+} -+ -+static inline struct qman_fq *get_fq_table_entry(u32 entry) -+{ -+ BUG_ON(entry >= qman_fq_lookup_table_size); -+ return qman_fq_lookup_table[entry]; -+} -+#endif -+ -+static inline void cpu_to_hw_fqd(struct qm_fqd *fqd) -+{ -+ /* Byteswap the FQD to HW format */ -+ fqd->fq_ctrl = cpu_to_be16(fqd->fq_ctrl); -+ fqd->dest_wq = cpu_to_be16(fqd->dest_wq); -+ fqd->ics_cred = cpu_to_be16(fqd->ics_cred); -+ fqd->context_b = cpu_to_be32(fqd->context_b); -+ fqd->context_a.opaque = cpu_to_be64(fqd->context_a.opaque); -+} -+ -+static inline void hw_fqd_to_cpu(struct qm_fqd *fqd) -+{ -+ /* Byteswap the FQD to CPU format */ -+ fqd->fq_ctrl = be16_to_cpu(fqd->fq_ctrl); -+ fqd->dest_wq = be16_to_cpu(fqd->dest_wq); -+ fqd->ics_cred = be16_to_cpu(fqd->ics_cred); -+ fqd->context_b = be32_to_cpu(fqd->context_b); -+ fqd->context_a.opaque = be64_to_cpu(fqd->context_a.opaque); -+} -+ -+/* Swap a 40 bit address */ -+static inline u64 cpu_to_be40(u64 in) -+{ -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ return in; -+#else -+ u64 out = 0; -+ u8 *p = (u8 *) &out; -+ p[0] = in >> 32; -+ p[1] = in >> 24; -+ p[2] = in >> 16; -+ p[3] = in >> 8; -+ p[4] = in >> 0; -+ return out; -+#endif -+} -+static inline u64 be40_to_cpu(u64 in) -+{ -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ return in; -+#else -+ u64 out = 0; -+ u8 *pout = (u8 *) &out; -+ u8 *pin = (u8 *) ∈ -+ pout[0] = pin[4]; -+ pout[1] = pin[3]; -+ pout[2] = pin[2]; -+ pout[3] = pin[1]; -+ pout[4] = pin[0]; -+ return out; -+#endif -+} -+ -+/* Swap a 24 bit value */ -+static inline u32 cpu_to_be24(u32 in) -+{ -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ return in; -+#else -+ u32 out = 0; -+ u8 *p = (u8 *) &out; -+ p[0] = in >> 16; -+ p[1] = in >> 8; -+ p[2] = in >> 0; -+ return out; -+#endif -+} -+ -+static inline u32 be24_to_cpu(u32 in) -+{ -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ return in; -+#else -+ u32 out = 0; -+ u8 *pout = (u8 *) &out; -+ u8 *pin = (u8 *) ∈ -+ pout[0] = pin[2]; -+ pout[1] = pin[1]; -+ pout[2] = pin[0]; -+ return out; -+#endif -+} -+ -+static inline u64 be48_to_cpu(u64 in) -+{ -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ return in; -+#else -+ u64 out = 0; -+ u8 *pout = (u8 *) &out; -+ u8 *pin = (u8 *) ∈ -+ -+ pout[0] = pin[5]; -+ pout[1] = pin[4]; -+ pout[2] = pin[3]; -+ pout[3] = pin[2]; -+ pout[4] = pin[1]; -+ pout[5] = pin[0]; -+ return out; -+#endif -+} -+static inline void cpu_to_hw_fd(struct qm_fd *fd) -+{ -+ fd->addr = cpu_to_be40(fd->addr); -+ fd->status = cpu_to_be32(fd->status); -+ fd->opaque = cpu_to_be32(fd->opaque); -+} -+ -+static inline void hw_fd_to_cpu(struct qm_fd *fd) -+{ -+ fd->addr = be40_to_cpu(fd->addr); -+ fd->status = be32_to_cpu(fd->status); -+ fd->opaque = be32_to_cpu(fd->opaque); -+} -+ -+static inline void hw_cq_query_to_cpu(struct qm_mcr_ceetm_cq_query *cq_query) -+{ -+ cq_query->ccgid = be16_to_cpu(cq_query->ccgid); -+ cq_query->state = be16_to_cpu(cq_query->state); -+ cq_query->pfdr_hptr = be24_to_cpu(cq_query->pfdr_hptr); -+ cq_query->pfdr_tptr = be24_to_cpu(cq_query->pfdr_tptr); -+ cq_query->od1_xsfdr = be16_to_cpu(cq_query->od1_xsfdr); -+ cq_query->od2_xsfdr = be16_to_cpu(cq_query->od2_xsfdr); -+ cq_query->od3_xsfdr = be16_to_cpu(cq_query->od3_xsfdr); -+ cq_query->od4_xsfdr = be16_to_cpu(cq_query->od4_xsfdr); -+ cq_query->od5_xsfdr = be16_to_cpu(cq_query->od5_xsfdr); -+ cq_query->od6_xsfdr = be16_to_cpu(cq_query->od6_xsfdr); -+ cq_query->ra1_xsfdr = be16_to_cpu(cq_query->ra1_xsfdr); -+ cq_query->ra2_xsfdr = be16_to_cpu(cq_query->ra2_xsfdr); -+ cq_query->frm_cnt = be24_to_cpu(cq_query->frm_cnt); -+} -+ -+static inline void hw_ccgr_query_to_cpu(struct qm_mcr_ceetm_ccgr_query *ccgr_q) -+{ -+ int i; -+ -+ ccgr_q->cm_query.cscn_targ_dcp = -+ be16_to_cpu(ccgr_q->cm_query.cscn_targ_dcp); -+ ccgr_q->cm_query.i_cnt = be40_to_cpu(ccgr_q->cm_query.i_cnt); -+ ccgr_q->cm_query.a_cnt = be40_to_cpu(ccgr_q->cm_query.a_cnt); -+ for (i = 0; i < ARRAY_SIZE(ccgr_q->cm_query.cscn_targ_swp); i++) -+ ccgr_q->cm_query.cscn_targ_swp[i] = -+ be32_to_cpu(ccgr_q->cm_query.cscn_targ_swp[i]); -+} -+ -+/* In the case that slow- and fast-path handling are both done by qman_poll() -+ * (ie. because there is no interrupt handling), we ought to balance how often -+ * we do the fast-path poll versus the slow-path poll. We'll use two decrementer -+ * sources, so we call the fast poll 'n' times before calling the slow poll -+ * once. The idle decrementer constant is used when the last slow-poll detected -+ * no work to do, and the busy decrementer constant when the last slow-poll had -+ * work to do. */ -+#define SLOW_POLL_IDLE 1000 -+#define SLOW_POLL_BUSY 10 -+static u32 __poll_portal_slow(struct qman_portal *p, u32 is); -+static inline unsigned int __poll_portal_fast(struct qman_portal *p, -+ unsigned int poll_limit); -+ -+/* Portal interrupt handler */ -+static irqreturn_t portal_isr(__always_unused int irq, void *ptr) -+{ -+ struct qman_portal *p = ptr; -+ /* -+ * The CSCI/CCSCI source is cleared inside __poll_portal_slow(), because -+ * it could race against a Query Congestion State command also given -+ * as part of the handling of this interrupt source. We mustn't -+ * clear it a second time in this top-level function. -+ */ -+ u32 clear = QM_DQAVAIL_MASK | (p->irq_sources & -+ ~(QM_PIRQ_CSCI | QM_PIRQ_CCSCI)); -+ u32 is = qm_isr_status_read(&p->p) & p->irq_sources; -+ /* DQRR-handling if it's interrupt-driven */ -+ if (is & QM_PIRQ_DQRI) -+ __poll_portal_fast(p, CONFIG_FSL_QMAN_POLL_LIMIT); -+ /* Handling of anything else that's interrupt-driven */ -+ clear |= __poll_portal_slow(p, is); -+ qm_isr_status_clear(&p->p, clear); -+ return IRQ_HANDLED; -+} -+ -+/* This inner version is used privately by qman_create_affine_portal(), as well -+ * as by the exported qman_stop_dequeues(). */ -+static inline void qman_stop_dequeues_ex(struct qman_portal *p) -+{ -+ unsigned long irqflags __maybe_unused; -+ PORTAL_IRQ_LOCK(p, irqflags); -+ if (!(p->dqrr_disable_ref++)) -+ qm_dqrr_set_maxfill(&p->p, 0); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+} -+ -+static int drain_mr(struct qm_portal *p) -+{ -+ const struct qm_mr_entry *msg; -+loop: -+ msg = qm_mr_current(p); -+ if (!msg) { -+ /* if MR was full and h/w had other FQRNI entries to produce, we -+ * need to allow it time to produce those entries once the -+ * existing entries are consumed. A worst-case situation -+ * (fully-loaded system) means h/w sequencers may have to do 3-4 -+ * other things before servicing the portal's MR pump, each of -+ * which (if slow) may take ~50 qman cycles (which is ~200 -+ * processor cycles). So rounding up and then multiplying this -+ * worst-case estimate by a factor of 10, just to be -+ * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume -+ * one entry at a time, so h/w has an opportunity to produce new -+ * entries well before the ring has been fully consumed, so -+ * we're being *really* paranoid here. */ -+ u64 now, then = mfatb(); -+ do { -+ now = mfatb(); -+ } while ((then + 10000) > now); -+ msg = qm_mr_current(p); -+ if (!msg) -+ return 0; -+ } -+ qm_mr_next(p); -+ qm_mr_cci_consume(p, 1); -+ goto loop; -+} -+ -+#ifdef CONFIG_SUSPEND -+static int _qman_portal_suspend_noirq(struct device *dev) -+{ -+ struct qman_portal *p = (struct qman_portal *)dev->platform_data; -+#ifdef CONFIG_PM_DEBUG -+ struct platform_device *pdev = to_platform_device(dev); -+#endif -+ -+ p->save_isdr = qm_isr_disable_read(&p->p); -+ qm_isr_disable_write(&p->p, 0xffffffff); -+ qm_isr_status_clear(&p->p, 0xffffffff); -+#ifdef CONFIG_PM_DEBUG -+ pr_info("Suspend for %s\n", pdev->name); -+#endif -+ return 0; -+} -+ -+static int _qman_portal_resume_noirq(struct device *dev) -+{ -+ struct qman_portal *p = (struct qman_portal *)dev->platform_data; -+ -+ /* restore isdr */ -+ qm_isr_disable_write(&p->p, p->save_isdr); -+ return 0; -+} -+#else -+#define _qman_portal_suspend_noirq NULL -+#define _qman_portal_resume_noirq NULL -+#endif -+ -+struct dev_pm_domain qman_portal_device_pm_domain = { -+ .ops = { -+ USE_PLATFORM_PM_SLEEP_OPS -+ .suspend_noirq = _qman_portal_suspend_noirq, -+ .resume_noirq = _qman_portal_resume_noirq, -+ } -+}; -+ -+struct qman_portal *qman_create_portal( -+ struct qman_portal *portal, -+ const struct qm_portal_config *config, -+ const struct qman_cgrs *cgrs) -+{ -+ struct qm_portal *__p; -+ char buf[16]; -+ int ret; -+ u32 isdr; -+ -+ if (!portal) { -+ portal = kmalloc(sizeof(*portal), GFP_KERNEL); -+ if (!portal) -+ return portal; -+ portal->alloced = 1; -+ } else -+ portal->alloced = 0; -+ -+ __p = &portal->p; -+ -+#ifdef CONFIG_FSL_PAMU -+ /* PAMU is required for stashing */ -+ portal->use_eqcr_ci_stashing = ((qman_ip_rev >= QMAN_REV30) ? -+ 1 : 0); -+#else -+ portal->use_eqcr_ci_stashing = 0; -+#endif -+ -+ /* prep the low-level portal struct with the mapped addresses from the -+ * config, everything that follows depends on it and "config" is more -+ * for (de)reference... */ -+ __p->addr.addr_ce = config->addr_virt[DPA_PORTAL_CE]; -+ __p->addr.addr_ci = config->addr_virt[DPA_PORTAL_CI]; -+ /* -+ * If CI-stashing is used, the current defaults use a threshold of 3, -+ * and stash with high-than-DQRR priority. -+ */ -+ if (qm_eqcr_init(__p, qm_eqcr_pvb, -+ portal->use_eqcr_ci_stashing ? 3 : 0, 1)) { -+ pr_err("Qman EQCR initialisation failed\n"); -+ goto fail_eqcr; -+ } -+ if (qm_dqrr_init(__p, config, qm_dqrr_dpush, qm_dqrr_pvb, -+ qm_dqrr_cdc, DQRR_MAXFILL)) { -+ pr_err("Qman DQRR initialisation failed\n"); -+ goto fail_dqrr; -+ } -+ if (qm_mr_init(__p, qm_mr_pvb, qm_mr_cci)) { -+ pr_err("Qman MR initialisation failed\n"); -+ goto fail_mr; -+ } -+ if (qm_mc_init(__p)) { -+ pr_err("Qman MC initialisation failed\n"); -+ goto fail_mc; -+ } -+ if (qm_isr_init(__p)) { -+ pr_err("Qman ISR initialisation failed\n"); -+ goto fail_isr; -+ } -+ /* static interrupt-gating controls */ -+ qm_dqrr_set_ithresh(__p, CONFIG_FSL_QMAN_PIRQ_DQRR_ITHRESH); -+ qm_mr_set_ithresh(__p, CONFIG_FSL_QMAN_PIRQ_MR_ITHRESH); -+ qm_isr_set_iperiod(__p, CONFIG_FSL_QMAN_PIRQ_IPERIOD); -+ portal->cgrs = kmalloc(2 * sizeof(*cgrs), GFP_KERNEL); -+ if (!portal->cgrs) -+ goto fail_cgrs; -+ /* initial snapshot is no-depletion */ -+ qman_cgrs_init(&portal->cgrs[1]); -+ if (cgrs) -+ portal->cgrs[0] = *cgrs; -+ else -+ /* if the given mask is NULL, assume all CGRs can be seen */ -+ qman_cgrs_fill(&portal->cgrs[0]); -+ INIT_LIST_HEAD(&portal->cgr_cbs); -+ spin_lock_init(&portal->cgr_lock); -+ if (num_ceetms) { -+ for (ret = 0; ret < num_ceetms; ret++) { -+ portal->ccgrs[ret] = kmalloc(2 * -+ sizeof(struct qman_ccgrs), GFP_KERNEL); -+ if (!portal->ccgrs[ret]) -+ goto fail_ccgrs; -+ qman_ccgrs_init(&portal->ccgrs[ret][1]); -+ qman_ccgrs_fill(&portal->ccgrs[ret][0]); -+ INIT_LIST_HEAD(&portal->ccgr_cbs[ret]); -+ } -+ } -+ spin_lock_init(&portal->ccgr_lock); -+ portal->bits = 0; -+ portal->slowpoll = 0; -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ portal->eqci_owned = NULL; -+#endif -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ raw_spin_lock_init(&portal->sharing_lock); -+ portal->is_shared = config->public_cfg.is_shared; -+ portal->sharing_redirect = NULL; -+#endif -+ portal->sdqcr = QM_SDQCR_SOURCE_CHANNELS | QM_SDQCR_COUNT_UPTO3 | -+ QM_SDQCR_DEDICATED_PRECEDENCE | QM_SDQCR_TYPE_PRIO_QOS | -+ QM_SDQCR_TOKEN_SET(0xab) | QM_SDQCR_CHANNELS_DEDICATED; -+ portal->dqrr_disable_ref = 0; -+ portal->cb_dc_ern = NULL; -+ sprintf(buf, "qportal-%d", config->public_cfg.channel); -+ portal->pdev = platform_device_alloc(buf, -1); -+ if (!portal->pdev) { -+ pr_err("qman_portal - platform_device_alloc() failed\n"); -+ goto fail_devalloc; -+ } -+#ifdef CONFIG_ARM -+ portal->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(40); -+ portal->pdev->dev.dma_mask = &portal->pdev->dev.coherent_dma_mask; -+#else -+ if (dma_set_mask(&portal->pdev->dev, DMA_BIT_MASK(40))) { -+ pr_err("qman_portal - dma_set_mask() failed\n"); -+ goto fail_devadd; -+ } -+#endif -+ portal->pdev->dev.pm_domain = &qman_portal_device_pm_domain; -+ portal->pdev->dev.platform_data = portal; -+ ret = platform_device_add(portal->pdev); -+ if (ret) { -+ pr_err("qman_portal - platform_device_add() failed\n"); -+ goto fail_devadd; -+ } -+ dpa_rbtree_init(&portal->retire_table); -+ isdr = 0xffffffff; -+ qm_isr_disable_write(__p, isdr); -+ portal->irq_sources = 0; -+ qm_isr_enable_write(__p, portal->irq_sources); -+ qm_isr_status_clear(__p, 0xffffffff); -+ snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, config->public_cfg.cpu); -+ if (request_irq(config->public_cfg.irq, portal_isr, 0, portal->irqname, -+ portal)) { -+ pr_err("request_irq() failed\n"); -+ goto fail_irq; -+ } -+ if ((config->public_cfg.cpu != -1) && -+ irq_can_set_affinity(config->public_cfg.irq) && -+ irq_set_affinity(config->public_cfg.irq, -+ cpumask_of(config->public_cfg.cpu))) { -+ pr_err("irq_set_affinity() failed\n"); -+ goto fail_affinity; -+ } -+ -+ /* Need EQCR to be empty before continuing */ -+ isdr ^= QM_PIRQ_EQCI; -+ qm_isr_disable_write(__p, isdr); -+ ret = qm_eqcr_get_fill(__p); -+ if (ret) { -+ pr_err("Qman EQCR unclean\n"); -+ goto fail_eqcr_empty; -+ } -+ isdr ^= (QM_PIRQ_DQRI | QM_PIRQ_MRI); -+ qm_isr_disable_write(__p, isdr); -+ while (qm_dqrr_current(__p) != NULL) -+ qm_dqrr_cdc_consume_n(__p, 0xffff); -+ drain_mr(__p); -+ /* Success */ -+ portal->config = config; -+ qm_isr_disable_write(__p, 0); -+ qm_isr_uninhibit(__p); -+ /* Write a sane SDQCR */ -+ qm_dqrr_sdqcr_set(__p, portal->sdqcr); -+ return portal; -+fail_eqcr_empty: -+fail_affinity: -+ free_irq(config->public_cfg.irq, portal); -+fail_irq: -+ platform_device_del(portal->pdev); -+fail_devadd: -+ platform_device_put(portal->pdev); -+fail_devalloc: -+ if (num_ceetms) -+ for (ret = 0; ret < num_ceetms; ret++) -+ kfree(portal->ccgrs[ret]); -+fail_ccgrs: -+ kfree(portal->cgrs); -+fail_cgrs: -+ qm_isr_finish(__p); -+fail_isr: -+ qm_mc_finish(__p); -+fail_mc: -+ qm_mr_finish(__p); -+fail_mr: -+ qm_dqrr_finish(__p); -+fail_dqrr: -+ qm_eqcr_finish(__p); -+fail_eqcr: -+ if (portal->alloced) -+ kfree(portal); -+ return NULL; -+} -+ -+struct qman_portal *qman_create_affine_portal( -+ const struct qm_portal_config *config, -+ const struct qman_cgrs *cgrs) -+{ -+ struct qman_portal *res; -+ struct qman_portal *portal; -+ -+ portal = &per_cpu(qman_affine_portal, config->public_cfg.cpu); -+ res = qman_create_portal(portal, config, cgrs); -+ if (res) { -+ spin_lock(&affine_mask_lock); -+ cpumask_set_cpu(config->public_cfg.cpu, &affine_mask); -+ affine_channels[config->public_cfg.cpu] = -+ config->public_cfg.channel; -+ affine_portals[config->public_cfg.cpu] = portal; -+ spin_unlock(&affine_mask_lock); -+ } -+ return res; -+} -+ -+/* These checks are BUG_ON()s because the driver is already supposed to avoid -+ * these cases. */ -+struct qman_portal *qman_create_affine_slave(struct qman_portal *redirect, -+ int cpu) -+{ -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ struct qman_portal *p; -+ p = &per_cpu(qman_affine_portal, cpu); -+ /* Check that we don't already have our own portal */ -+ BUG_ON(p->config); -+ /* Check that we aren't already slaving to another portal */ -+ BUG_ON(p->is_shared); -+ /* Check that 'redirect' is prepared to have us */ -+ BUG_ON(!redirect->config->public_cfg.is_shared); -+ /* These are the only elements to initialise when redirecting */ -+ p->irq_sources = 0; -+ p->sharing_redirect = redirect; -+ affine_portals[cpu] = p; -+ return p; -+#else -+ BUG(); -+ return NULL; -+#endif -+} -+ -+void qman_destroy_portal(struct qman_portal *qm) -+{ -+ const struct qm_portal_config *pcfg; -+ int i; -+ -+ /* Stop dequeues on the portal */ -+ qm_dqrr_sdqcr_set(&qm->p, 0); -+ -+ /* NB we do this to "quiesce" EQCR. If we add enqueue-completions or -+ * something related to QM_PIRQ_EQCI, this may need fixing. -+ * Also, due to the prefetching model used for CI updates in the enqueue -+ * path, this update will only invalidate the CI cacheline *after* -+ * working on it, so we need to call this twice to ensure a full update -+ * irrespective of where the enqueue processing was at when the teardown -+ * began. */ -+ qm_eqcr_cce_update(&qm->p); -+ qm_eqcr_cce_update(&qm->p); -+ pcfg = qm->config; -+ -+ free_irq(pcfg->public_cfg.irq, qm); -+ -+ kfree(qm->cgrs); -+ if (num_ceetms) -+ for (i = 0; i < num_ceetms; i++) -+ kfree(qm->ccgrs[i]); -+ qm_isr_finish(&qm->p); -+ qm_mc_finish(&qm->p); -+ qm_mr_finish(&qm->p); -+ qm_dqrr_finish(&qm->p); -+ qm_eqcr_finish(&qm->p); -+ -+ platform_device_del(qm->pdev); -+ platform_device_put(qm->pdev); -+ -+ qm->config = NULL; -+ if (qm->alloced) -+ kfree(qm); -+} -+ -+const struct qm_portal_config *qman_destroy_affine_portal(void) -+{ -+ /* We don't want to redirect if we're a slave, use "raw" */ -+ struct qman_portal *qm = get_raw_affine_portal(); -+ const struct qm_portal_config *pcfg; -+ int cpu; -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ if (qm->sharing_redirect) { -+ qm->sharing_redirect = NULL; -+ put_affine_portal(); -+ return NULL; -+ } -+ qm->is_shared = 0; -+#endif -+ pcfg = qm->config; -+ cpu = pcfg->public_cfg.cpu; -+ -+ qman_destroy_portal(qm); -+ -+ spin_lock(&affine_mask_lock); -+ cpumask_clear_cpu(cpu, &affine_mask); -+ spin_unlock(&affine_mask_lock); -+ put_affine_portal(); -+ return pcfg; -+} -+ -+const struct qman_portal_config *qman_p_get_portal_config(struct qman_portal *p) -+{ -+ return &p->config->public_cfg; -+} -+EXPORT_SYMBOL(qman_p_get_portal_config); -+ -+const struct qman_portal_config *qman_get_portal_config(void) -+{ -+ struct qman_portal *p = get_affine_portal(); -+ const struct qman_portal_config *ret = qman_p_get_portal_config(p); -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(qman_get_portal_config); -+ -+/* Inline helper to reduce nesting in __poll_portal_slow() */ -+static inline void fq_state_change(struct qman_portal *p, struct qman_fq *fq, -+ const struct qm_mr_entry *msg, u8 verb) -+{ -+ FQLOCK(fq); -+ switch (verb) { -+ case QM_MR_VERB_FQRL: -+ DPA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_ORL)); -+ fq_clear(fq, QMAN_FQ_STATE_ORL); -+ table_del_fq(p, fq); -+ break; -+ case QM_MR_VERB_FQRN: -+ DPA_ASSERT((fq->state == qman_fq_state_parked) || -+ (fq->state == qman_fq_state_sched)); -+ DPA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_CHANGING)); -+ fq_clear(fq, QMAN_FQ_STATE_CHANGING); -+ if (msg->fq.fqs & QM_MR_FQS_NOTEMPTY) -+ fq_set(fq, QMAN_FQ_STATE_NE); -+ if (msg->fq.fqs & QM_MR_FQS_ORLPRESENT) -+ fq_set(fq, QMAN_FQ_STATE_ORL); -+ else -+ table_del_fq(p, fq); -+ fq->state = qman_fq_state_retired; -+ break; -+ case QM_MR_VERB_FQPN: -+ DPA_ASSERT(fq->state == qman_fq_state_sched); -+ DPA_ASSERT(fq_isclear(fq, QMAN_FQ_STATE_CHANGING)); -+ fq->state = qman_fq_state_parked; -+ } -+ FQUNLOCK(fq); -+} -+ -+static u32 __poll_portal_slow(struct qman_portal *p, u32 is) -+{ -+ const struct qm_mr_entry *msg; -+ -+ if (is & QM_PIRQ_CSCI) { -+ struct qman_cgrs rr, c; -+ struct qm_mc_result *mcr; -+ struct qman_cgr *cgr; -+ unsigned long irqflags __maybe_unused; -+ -+ spin_lock_irqsave(&p->cgr_lock, irqflags); -+ /* -+ * The CSCI bit must be cleared _before_ issuing the -+ * Query Congestion State command, to ensure that a long -+ * CGR State Change callback cannot miss an intervening -+ * state change. -+ */ -+ qm_isr_status_clear(&p->p, QM_PIRQ_CSCI); -+ qm_mc_start(&p->p); -+ qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ /* mask out the ones I'm not interested in */ -+ qman_cgrs_and(&rr, (const struct qman_cgrs *) -+ &mcr->querycongestion.state, &p->cgrs[0]); -+ /* check previous snapshot for delta, enter/exit congestion */ -+ qman_cgrs_xor(&c, &rr, &p->cgrs[1]); -+ /* update snapshot */ -+ qman_cgrs_cp(&p->cgrs[1], &rr); -+ /* Invoke callback */ -+ list_for_each_entry(cgr, &p->cgr_cbs, node) -+ if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid)) -+ cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid)); -+ spin_unlock_irqrestore(&p->cgr_lock, irqflags); -+ } -+ if (is & QM_PIRQ_CCSCI) { -+ struct qman_ccgrs rr, c, congestion_result; -+ struct qm_mc_result *mcr; -+ struct qm_mc_command *mcc; -+ struct qm_ceetm_ccg *ccg; -+ unsigned long irqflags __maybe_unused; -+ int i, j, k; -+ -+ spin_lock_irqsave(&p->ccgr_lock, irqflags); -+ /* -+ * The CCSCI bit must be cleared _before_ issuing the -+ * Query Congestion State command, to ensure that a long -+ * CCGR State Change callback cannot miss an intervening -+ * state change. -+ */ -+ qm_isr_status_clear(&p->p, QM_PIRQ_CCSCI); -+ -+ for (i = 0; i < num_ceetms; i++) { -+ for (j = 0; j < 2; j++) { -+ mcc = qm_mc_start(&p->p); -+ mcc->ccgr_query.ccgrid = cpu_to_be16( -+ CEETM_QUERY_CONGESTION_STATE | j); -+ mcc->ccgr_query.dcpid = i; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_CCGR_QUERY); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ for (k = 0; k < 8; k++) -+ mcr->ccgr_query.congestion_state.state. -+ __state[k] = be32_to_cpu( -+ mcr->ccgr_query. -+ congestion_state.state. -+ __state[k]); -+ congestion_result.q[j] = -+ mcr->ccgr_query.congestion_state.state; -+ } -+ /* mask out the ones I'm not interested in */ -+ qman_ccgrs_and(&rr, &congestion_result, -+ &p->ccgrs[i][0]); -+ /* -+ * check previous snapshot for delta, enter/exit -+ * congestion. -+ */ -+ qman_ccgrs_xor(&c, &rr, &p->ccgrs[i][1]); -+ /* update snapshot */ -+ qman_ccgrs_cp(&p->ccgrs[i][1], &rr); -+ /* Invoke callback */ -+ list_for_each_entry(ccg, &p->ccgr_cbs[i], cb_node) -+ if (ccg->cb && qman_ccgrs_get(&c, -+ (ccg->parent->idx << 4) | ccg->idx)) -+ ccg->cb(ccg, ccg->cb_ctx, -+ qman_ccgrs_get(&rr, -+ (ccg->parent->idx << 4) -+ | ccg->idx)); -+ } -+ spin_unlock_irqrestore(&p->ccgr_lock, irqflags); -+ } -+ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ if (is & QM_PIRQ_EQCI) { -+ unsigned long irqflags; -+ PORTAL_IRQ_LOCK(p, irqflags); -+ p->eqci_owned = NULL; -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ wake_up(&affine_queue); -+ } -+#endif -+ -+ if (is & QM_PIRQ_EQRI) { -+ unsigned long irqflags __maybe_unused; -+ PORTAL_IRQ_LOCK(p, irqflags); -+ qm_eqcr_cce_update(&p->p); -+ qm_eqcr_set_ithresh(&p->p, 0); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ wake_up(&affine_queue); -+ } -+ -+ if (is & QM_PIRQ_MRI) { -+ struct qman_fq *fq; -+ u8 verb, num = 0; -+mr_loop: -+ qm_mr_pvb_update(&p->p); -+ msg = qm_mr_current(&p->p); -+ if (!msg) -+ goto mr_done; -+ verb = msg->verb & QM_MR_VERB_TYPE_MASK; -+ /* The message is a software ERN iff the 0x20 bit is set */ -+ if (verb & 0x20) { -+ switch (verb) { -+ case QM_MR_VERB_FQRNI: -+ /* nada, we drop FQRNIs on the floor */ -+ break; -+ case QM_MR_VERB_FQRN: -+ case QM_MR_VERB_FQRL: -+ /* Lookup in the retirement table */ -+ fq = table_find_fq(p, be32_to_cpu(msg->fq.fqid)); -+ BUG_ON(!fq); -+ fq_state_change(p, fq, msg, verb); -+ if (fq->cb.fqs) -+ fq->cb.fqs(p, fq, msg); -+ break; -+ case QM_MR_VERB_FQPN: -+ /* Parked */ -+#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP -+ fq = get_fq_table_entry( -+ be32_to_cpu(msg->fq.contextB)); -+#else -+ fq = (void *)(uintptr_t) -+ be32_to_cpu(msg->fq.contextB); -+#endif -+ fq_state_change(p, fq, msg, verb); -+ if (fq->cb.fqs) -+ fq->cb.fqs(p, fq, msg); -+ break; -+ case QM_MR_VERB_DC_ERN: -+ /* DCP ERN */ -+ if (p->cb_dc_ern) -+ p->cb_dc_ern(p, msg); -+ else if (cb_dc_ern) -+ cb_dc_ern(p, msg); -+ else { -+ static int warn_once; -+ if (!warn_once) { -+ pr_crit("Leaking DCP ERNs!\n"); -+ warn_once = 1; -+ } -+ } -+ break; -+ default: -+ pr_crit("Invalid MR verb 0x%02x\n", verb); -+ } -+ } else { -+ /* Its a software ERN */ -+#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP -+ pr_info("ROY\n"); -+ fq = get_fq_table_entry(be32_to_cpu(msg->ern.tag)); -+#else -+ fq = (void *)(uintptr_t)be32_to_cpu(msg->ern.tag); -+#endif -+ fq->cb.ern(p, fq, msg); -+ } -+ num++; -+ qm_mr_next(&p->p); -+ goto mr_loop; -+mr_done: -+ qm_mr_cci_consume(&p->p, num); -+ } -+ /* -+ * QM_PIRQ_CSCI/CCSCI has already been cleared, as part of its specific -+ * processing. If that interrupt source has meanwhile been re-asserted, -+ * we mustn't clear it here (or in the top-level interrupt handler). -+ */ -+ return is & (QM_PIRQ_EQCI | QM_PIRQ_EQRI | QM_PIRQ_MRI); -+} -+ -+/* remove some slowish-path stuff from the "fast path" and make sure it isn't -+ * inlined. */ -+static noinline void clear_vdqcr(struct qman_portal *p, struct qman_fq *fq) -+{ -+ p->vdqcr_owned = NULL; -+ FQLOCK(fq); -+ fq_clear(fq, QMAN_FQ_STATE_VDQCR); -+ FQUNLOCK(fq); -+ wake_up(&affine_queue); -+} -+ -+/* Look: no locks, no irq_save()s, no preempt_disable()s! :-) The only states -+ * that would conflict with other things if they ran at the same time on the -+ * same cpu are; -+ * -+ * (i) setting/clearing vdqcr_owned, and -+ * (ii) clearing the NE (Not Empty) flag. -+ * -+ * Both are safe. Because; -+ * -+ * (i) this clearing can only occur after qman_volatile_dequeue() has set the -+ * vdqcr_owned field (which it does before setting VDQCR), and -+ * qman_volatile_dequeue() blocks interrupts and preemption while this is -+ * done so that we can't interfere. -+ * (ii) the NE flag is only cleared after qman_retire_fq() has set it, and as -+ * with (i) that API prevents us from interfering until it's safe. -+ * -+ * The good thing is that qman_volatile_dequeue() and qman_retire_fq() run far -+ * less frequently (ie. per-FQ) than __poll_portal_fast() does, so the nett -+ * advantage comes from this function not having to "lock" anything at all. -+ * -+ * Note also that the callbacks are invoked at points which are safe against the -+ * above potential conflicts, but that this function itself is not re-entrant -+ * (this is because the function tracks one end of each FIFO in the portal and -+ * we do *not* want to lock that). So the consequence is that it is safe for -+ * user callbacks to call into any Qman API *except* qman_poll() (as that's the -+ * sole API that could be invoking the callback through this function). -+ */ -+static inline unsigned int __poll_portal_fast(struct qman_portal *p, -+ unsigned int poll_limit) -+{ -+ const struct qm_dqrr_entry *dq; -+ struct qman_fq *fq; -+ enum qman_cb_dqrr_result res; -+ unsigned int limit = 0; -+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ -+ struct qm_dqrr_entry *shadow; -+#endif -+loop: -+ qm_dqrr_pvb_update(&p->p); -+ dq = qm_dqrr_current(&p->p); -+ if (!dq) -+ goto done; -+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ -+ /* If running on an LE system the fields of the -+ dequeue entry must be swapped. Because the -+ QMan HW will ignore writes the DQRR entry is -+ copied and the index stored within the copy */ -+ shadow = &p->shadow_dqrr[DQRR_PTR2IDX(dq)]; -+ *shadow = *dq; -+ dq = shadow; -+ shadow->fqid = be32_to_cpu(shadow->fqid); -+ shadow->contextB = be32_to_cpu(shadow->contextB); -+ shadow->seqnum = be16_to_cpu(shadow->seqnum); -+ hw_fd_to_cpu(&shadow->fd); -+#endif -+ if (dq->stat & QM_DQRR_STAT_UNSCHEDULED) { -+ /* VDQCR: don't trust contextB as the FQ may have been -+ * configured for h/w consumption and we're draining it -+ * post-retirement. */ -+ fq = p->vdqcr_owned; -+ /* We only set QMAN_FQ_STATE_NE when retiring, so we only need -+ * to check for clearing it when doing volatile dequeues. It's -+ * one less thing to check in the critical path (SDQCR). */ -+ if (dq->stat & QM_DQRR_STAT_FQ_EMPTY) -+ fq_clear(fq, QMAN_FQ_STATE_NE); -+ /* this is duplicated from the SDQCR code, but we have stuff to -+ * do before *and* after this callback, and we don't want -+ * multiple if()s in the critical path (SDQCR). */ -+ res = fq->cb.dqrr(p, fq, dq); -+ if (res == qman_cb_dqrr_stop) -+ goto done; -+ /* Check for VDQCR completion */ -+ if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED) -+ clear_vdqcr(p, fq); -+ } else { -+ /* SDQCR: contextB points to the FQ */ -+#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP -+ fq = get_fq_table_entry(dq->contextB); -+#else -+ fq = (void *)(uintptr_t)dq->contextB; -+#endif -+ /* Now let the callback do its stuff */ -+ res = fq->cb.dqrr(p, fq, dq); -+ -+ /* The callback can request that we exit without consuming this -+ * entry nor advancing; */ -+ if (res == qman_cb_dqrr_stop) -+ goto done; -+ } -+ /* Interpret 'dq' from a driver perspective. */ -+ /* Parking isn't possible unless HELDACTIVE was set. NB, -+ * FORCEELIGIBLE implies HELDACTIVE, so we only need to -+ * check for HELDACTIVE to cover both. */ -+ DPA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) || -+ (res != qman_cb_dqrr_park)); -+ /* Defer just means "skip it, I'll consume it myself later on" */ -+ if (res != qman_cb_dqrr_defer) -+ qm_dqrr_cdc_consume_1ptr(&p->p, dq, (res == qman_cb_dqrr_park)); -+ /* Move forward */ -+ qm_dqrr_next(&p->p); -+ /* Entry processed and consumed, increment our counter. The callback can -+ * request that we exit after consuming the entry, and we also exit if -+ * we reach our processing limit, so loop back only if neither of these -+ * conditions is met. */ -+ if ((++limit < poll_limit) && (res != qman_cb_dqrr_consume_stop)) -+ goto loop; -+done: -+ return limit; -+} -+ -+u32 qman_irqsource_get(void) -+{ -+ /* "irqsource" and "poll" APIs mustn't redirect when sharing, they -+ * should shut the user out if they are not the primary CPU hosting the -+ * portal. That's why we use the "raw" interface. */ -+ struct qman_portal *p = get_raw_affine_portal(); -+ u32 ret = p->irq_sources & QM_PIRQ_VISIBLE; -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(qman_irqsource_get); -+ -+int qman_p_irqsource_add(struct qman_portal *p, u32 bits __maybe_unused) -+{ -+ __maybe_unused unsigned long irqflags; -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ if (p->sharing_redirect) -+ return -EINVAL; -+ else -+#endif -+ { -+ PORTAL_IRQ_LOCK(p, irqflags); -+ set_bits(bits & QM_PIRQ_VISIBLE, &p->irq_sources); -+ qm_isr_enable_write(&p->p, p->irq_sources); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ } -+ return 0; -+} -+EXPORT_SYMBOL(qman_p_irqsource_add); -+ -+int qman_irqsource_add(u32 bits __maybe_unused) -+{ -+ struct qman_portal *p = get_raw_affine_portal(); -+ int ret; -+ ret = qman_p_irqsource_add(p, bits); -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(qman_irqsource_add); -+ -+int qman_p_irqsource_remove(struct qman_portal *p, u32 bits) -+{ -+ __maybe_unused unsigned long irqflags; -+ u32 ier; -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ if (p->sharing_redirect) { -+ put_affine_portal(); -+ return -EINVAL; -+ } -+#endif -+ /* Our interrupt handler only processes+clears status register bits that -+ * are in p->irq_sources. As we're trimming that mask, if one of them -+ * were to assert in the status register just before we remove it from -+ * the enable register, there would be an interrupt-storm when we -+ * release the IRQ lock. So we wait for the enable register update to -+ * take effect in h/w (by reading it back) and then clear all other bits -+ * in the status register. Ie. we clear them from ISR once it's certain -+ * IER won't allow them to reassert. */ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ bits &= QM_PIRQ_VISIBLE; -+ clear_bits(bits, &p->irq_sources); -+ qm_isr_enable_write(&p->p, p->irq_sources); -+ -+ ier = qm_isr_enable_read(&p->p); -+ /* Using "~ier" (rather than "bits" or "~p->irq_sources") creates a -+ * data-dependency, ie. to protect against re-ordering. */ -+ qm_isr_status_clear(&p->p, ~ier); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ return 0; -+} -+EXPORT_SYMBOL(qman_p_irqsource_remove); -+ -+int qman_irqsource_remove(u32 bits) -+{ -+ struct qman_portal *p = get_raw_affine_portal(); -+ int ret; -+ ret = qman_p_irqsource_remove(p, bits); -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(qman_irqsource_remove); -+ -+const cpumask_t *qman_affine_cpus(void) -+{ -+ return &affine_mask; -+} -+EXPORT_SYMBOL(qman_affine_cpus); -+ -+u16 qman_affine_channel(int cpu) -+{ -+ if (cpu < 0) { -+ struct qman_portal *portal = get_raw_affine_portal(); -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ BUG_ON(portal->sharing_redirect); -+#endif -+ cpu = portal->config->public_cfg.cpu; -+ put_affine_portal(); -+ } -+ BUG_ON(!cpumask_test_cpu(cpu, &affine_mask)); -+ return affine_channels[cpu]; -+} -+EXPORT_SYMBOL(qman_affine_channel); -+ -+void *qman_get_affine_portal(int cpu) -+{ -+ return affine_portals[cpu]; -+} -+EXPORT_SYMBOL(qman_get_affine_portal); -+ -+int qman_p_poll_dqrr(struct qman_portal *p, unsigned int limit) -+{ -+ int ret; -+ -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ if (unlikely(p->sharing_redirect)) -+ ret = -EINVAL; -+ else -+#endif -+ { -+ BUG_ON(p->irq_sources & QM_PIRQ_DQRI); -+ ret = __poll_portal_fast(p, limit); -+ } -+ return ret; -+} -+EXPORT_SYMBOL(qman_p_poll_dqrr); -+ -+int qman_poll_dqrr(unsigned int limit) -+{ -+ struct qman_portal *p = get_poll_portal(); -+ int ret; -+ ret = qman_p_poll_dqrr(p, limit); -+ put_poll_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(qman_poll_dqrr); -+ -+u32 qman_p_poll_slow(struct qman_portal *p) -+{ -+ u32 ret; -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ if (unlikely(p->sharing_redirect)) -+ ret = (u32)-1; -+ else -+#endif -+ { -+ u32 is = qm_isr_status_read(&p->p) & ~p->irq_sources; -+ ret = __poll_portal_slow(p, is); -+ qm_isr_status_clear(&p->p, ret); -+ } -+ return ret; -+} -+EXPORT_SYMBOL(qman_p_poll_slow); -+ -+u32 qman_poll_slow(void) -+{ -+ struct qman_portal *p = get_poll_portal(); -+ u32 ret; -+ ret = qman_p_poll_slow(p); -+ put_poll_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(qman_poll_slow); -+ -+/* Legacy wrapper */ -+void qman_p_poll(struct qman_portal *p) -+{ -+#ifdef CONFIG_FSL_DPA_PORTAL_SHARE -+ if (unlikely(p->sharing_redirect)) -+ return; -+#endif -+ if ((~p->irq_sources) & QM_PIRQ_SLOW) { -+ if (!(p->slowpoll--)) { -+ u32 is = qm_isr_status_read(&p->p) & ~p->irq_sources; -+ u32 active = __poll_portal_slow(p, is); -+ if (active) { -+ qm_isr_status_clear(&p->p, active); -+ p->slowpoll = SLOW_POLL_BUSY; -+ } else -+ p->slowpoll = SLOW_POLL_IDLE; -+ } -+ } -+ if ((~p->irq_sources) & QM_PIRQ_DQRI) -+ __poll_portal_fast(p, CONFIG_FSL_QMAN_POLL_LIMIT); -+} -+EXPORT_SYMBOL(qman_p_poll); -+ -+void qman_poll(void) -+{ -+ struct qman_portal *p = get_poll_portal(); -+ qman_p_poll(p); -+ put_poll_portal(); -+} -+EXPORT_SYMBOL(qman_poll); -+ -+void qman_p_stop_dequeues(struct qman_portal *p) -+{ -+ qman_stop_dequeues_ex(p); -+} -+EXPORT_SYMBOL(qman_p_stop_dequeues); -+ -+void qman_stop_dequeues(void) -+{ -+ struct qman_portal *p = get_affine_portal(); -+ qman_p_stop_dequeues(p); -+ put_affine_portal(); -+} -+EXPORT_SYMBOL(qman_stop_dequeues); -+ -+void qman_p_start_dequeues(struct qman_portal *p) -+{ -+ unsigned long irqflags __maybe_unused; -+ PORTAL_IRQ_LOCK(p, irqflags); -+ DPA_ASSERT(p->dqrr_disable_ref > 0); -+ if (!(--p->dqrr_disable_ref)) -+ qm_dqrr_set_maxfill(&p->p, DQRR_MAXFILL); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+} -+EXPORT_SYMBOL(qman_p_start_dequeues); -+ -+void qman_start_dequeues(void) -+{ -+ struct qman_portal *p = get_affine_portal(); -+ qman_p_start_dequeues(p); -+ put_affine_portal(); -+} -+EXPORT_SYMBOL(qman_start_dequeues); -+ -+void qman_p_static_dequeue_add(struct qman_portal *p, u32 pools) -+{ -+ unsigned long irqflags __maybe_unused; -+ PORTAL_IRQ_LOCK(p, irqflags); -+ pools &= p->config->public_cfg.pools; -+ p->sdqcr |= pools; -+ qm_dqrr_sdqcr_set(&p->p, p->sdqcr); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+} -+EXPORT_SYMBOL(qman_p_static_dequeue_add); -+ -+void qman_static_dequeue_add(u32 pools) -+{ -+ struct qman_portal *p = get_affine_portal(); -+ qman_p_static_dequeue_add(p, pools); -+ put_affine_portal(); -+} -+EXPORT_SYMBOL(qman_static_dequeue_add); -+ -+void qman_p_static_dequeue_del(struct qman_portal *p, u32 pools) -+{ -+ unsigned long irqflags __maybe_unused; -+ PORTAL_IRQ_LOCK(p, irqflags); -+ pools &= p->config->public_cfg.pools; -+ p->sdqcr &= ~pools; -+ qm_dqrr_sdqcr_set(&p->p, p->sdqcr); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+} -+EXPORT_SYMBOL(qman_p_static_dequeue_del); -+ -+void qman_static_dequeue_del(u32 pools) -+{ -+ struct qman_portal *p = get_affine_portal(); -+ qman_p_static_dequeue_del(p, pools); -+ put_affine_portal(); -+} -+EXPORT_SYMBOL(qman_static_dequeue_del); -+ -+u32 qman_p_static_dequeue_get(struct qman_portal *p) -+{ -+ return p->sdqcr; -+} -+EXPORT_SYMBOL(qman_p_static_dequeue_get); -+ -+u32 qman_static_dequeue_get(void) -+{ -+ struct qman_portal *p = get_affine_portal(); -+ u32 ret = qman_p_static_dequeue_get(p); -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(qman_static_dequeue_get); -+ -+void qman_p_dca(struct qman_portal *p, struct qm_dqrr_entry *dq, -+ int park_request) -+{ -+ qm_dqrr_cdc_consume_1ptr(&p->p, dq, park_request); -+} -+EXPORT_SYMBOL(qman_p_dca); -+ -+void qman_dca(struct qm_dqrr_entry *dq, int park_request) -+{ -+ struct qman_portal *p = get_affine_portal(); -+ qman_p_dca(p, dq, park_request); -+ put_affine_portal(); -+} -+EXPORT_SYMBOL(qman_dca); -+ -+/*******************/ -+/* Frame queue API */ -+/*******************/ -+ -+static const char *mcr_result_str(u8 result) -+{ -+ switch (result) { -+ case QM_MCR_RESULT_NULL: -+ return "QM_MCR_RESULT_NULL"; -+ case QM_MCR_RESULT_OK: -+ return "QM_MCR_RESULT_OK"; -+ case QM_MCR_RESULT_ERR_FQID: -+ return "QM_MCR_RESULT_ERR_FQID"; -+ case QM_MCR_RESULT_ERR_FQSTATE: -+ return "QM_MCR_RESULT_ERR_FQSTATE"; -+ case QM_MCR_RESULT_ERR_NOTEMPTY: -+ return "QM_MCR_RESULT_ERR_NOTEMPTY"; -+ case QM_MCR_RESULT_PENDING: -+ return "QM_MCR_RESULT_PENDING"; -+ case QM_MCR_RESULT_ERR_BADCOMMAND: -+ return "QM_MCR_RESULT_ERR_BADCOMMAND"; -+ } -+ return ""; -+} -+ -+int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq) -+{ -+ struct qm_fqd fqd; -+ struct qm_mcr_queryfq_np np; -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ -+ if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID) { -+ int ret = qman_alloc_fqid(&fqid); -+ if (ret) -+ return ret; -+ } -+ spin_lock_init(&fq->fqlock); -+ fq->fqid = fqid; -+ fq->flags = flags; -+ fq->state = qman_fq_state_oos; -+ fq->cgr_groupid = 0; -+#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP -+ if (unlikely(find_empty_fq_table_entry(&fq->key, fq))) -+ return -ENOMEM; -+#endif -+ if (!(flags & QMAN_FQ_FLAG_AS_IS) || (flags & QMAN_FQ_FLAG_NO_MODIFY)) -+ return 0; -+ /* Everything else is AS_IS support */ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ mcc = qm_mc_start(&p->p); -+ mcc->queryfq.fqid = cpu_to_be32(fqid); -+ qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYFQ); -+ if (mcr->result != QM_MCR_RESULT_OK) { -+ pr_err("QUERYFQ failed: %s\n", mcr_result_str(mcr->result)); -+ goto err; -+ } -+ fqd = mcr->queryfq.fqd; -+ hw_fqd_to_cpu(&fqd); -+ mcc = qm_mc_start(&p->p); -+ mcc->queryfq_np.fqid = cpu_to_be32(fqid); -+ qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYFQ_NP); -+ if (mcr->result != QM_MCR_RESULT_OK) { -+ pr_err("QUERYFQ_NP failed: %s\n", mcr_result_str(mcr->result)); -+ goto err; -+ } -+ np = mcr->queryfq_np; -+ /* Phew, have queryfq and queryfq_np results, stitch together -+ * the FQ object from those. */ -+ fq->cgr_groupid = fqd.cgid; -+ switch (np.state & QM_MCR_NP_STATE_MASK) { -+ case QM_MCR_NP_STATE_OOS: -+ break; -+ case QM_MCR_NP_STATE_RETIRED: -+ fq->state = qman_fq_state_retired; -+ if (np.frm_cnt) -+ fq_set(fq, QMAN_FQ_STATE_NE); -+ break; -+ case QM_MCR_NP_STATE_TEN_SCHED: -+ case QM_MCR_NP_STATE_TRU_SCHED: -+ case QM_MCR_NP_STATE_ACTIVE: -+ fq->state = qman_fq_state_sched; -+ if (np.state & QM_MCR_NP_STATE_R) -+ fq_set(fq, QMAN_FQ_STATE_CHANGING); -+ break; -+ case QM_MCR_NP_STATE_PARKED: -+ fq->state = qman_fq_state_parked; -+ break; -+ default: -+ DPA_ASSERT(NULL == "invalid FQ state"); -+ } -+ if (fqd.fq_ctrl & QM_FQCTRL_CGE) -+ fq->state |= QMAN_FQ_STATE_CGR_EN; -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return 0; -+err: -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID) -+ qman_release_fqid(fqid); -+ return -EIO; -+} -+EXPORT_SYMBOL(qman_create_fq); -+ -+void qman_destroy_fq(struct qman_fq *fq, u32 flags __maybe_unused) -+{ -+ -+ /* We don't need to lock the FQ as it is a pre-condition that the FQ be -+ * quiesced. Instead, run some checks. */ -+ switch (fq->state) { -+ case qman_fq_state_parked: -+ DPA_ASSERT(flags & QMAN_FQ_DESTROY_PARKED); -+ case qman_fq_state_oos: -+ if (fq_isset(fq, QMAN_FQ_FLAG_DYNAMIC_FQID)) -+ qman_release_fqid(fq->fqid); -+#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP -+ clear_fq_table_entry(fq->key); -+#endif -+ return; -+ default: -+ break; -+ } -+ DPA_ASSERT(NULL == "qman_free_fq() on unquiesced FQ!"); -+} -+EXPORT_SYMBOL(qman_destroy_fq); -+ -+u32 qman_fq_fqid(struct qman_fq *fq) -+{ -+ return fq->fqid; -+} -+EXPORT_SYMBOL(qman_fq_fqid); -+ -+void qman_fq_state(struct qman_fq *fq, enum qman_fq_state *state, u32 *flags) -+{ -+ if (state) -+ *state = fq->state; -+ if (flags) -+ *flags = fq->flags; -+} -+EXPORT_SYMBOL(qman_fq_state); -+ -+int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res, myverb = (flags & QMAN_INITFQ_FLAG_SCHED) ? -+ QM_MCC_VERB_INITFQ_SCHED : QM_MCC_VERB_INITFQ_PARKED; -+ -+ if ((fq->state != qman_fq_state_oos) && -+ (fq->state != qman_fq_state_parked)) -+ return -EINVAL; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))) -+ return -EINVAL; -+#endif -+ if (opts && (opts->we_mask & QM_INITFQ_WE_OAC)) { -+ /* And can't be set at the same time as TDTHRESH */ -+ if (opts->we_mask & QM_INITFQ_WE_TDTHRESH) -+ return -EINVAL; -+ } -+ /* Issue an INITFQ_[PARKED|SCHED] management command */ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ FQLOCK(fq); -+ if (unlikely((fq_isset(fq, QMAN_FQ_STATE_CHANGING)) || -+ ((fq->state != qman_fq_state_oos) && -+ (fq->state != qman_fq_state_parked)))) { -+ FQUNLOCK(fq); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return -EBUSY; -+ } -+ mcc = qm_mc_start(&p->p); -+ if (opts) -+ mcc->initfq = *opts; -+ mcc->initfq.fqid = cpu_to_be32(fq->fqid); -+ mcc->initfq.count = 0; -+ -+ /* If the FQ does *not* have the TO_DCPORTAL flag, contextB is set as a -+ * demux pointer. Otherwise, the caller-provided value is allowed to -+ * stand, don't overwrite it. */ -+ if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) { -+ dma_addr_t phys_fq; -+ mcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTB; -+#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP -+ mcc->initfq.fqd.context_b = fq->key; -+#else -+ mcc->initfq.fqd.context_b = (u32)(uintptr_t)fq; -+#endif -+ /* and the physical address - NB, if the user wasn't trying to -+ * set CONTEXTA, clear the stashing settings. */ -+ if (!(mcc->initfq.we_mask & QM_INITFQ_WE_CONTEXTA)) { -+ mcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTA; -+ memset(&mcc->initfq.fqd.context_a, 0, -+ sizeof(mcc->initfq.fqd.context_a)); -+ } else { -+ phys_fq = dma_map_single(&p->pdev->dev, fq, sizeof(*fq), -+ DMA_TO_DEVICE); -+ qm_fqd_stashing_set64(&mcc->initfq.fqd, phys_fq); -+ } -+ } -+ if (flags & QMAN_INITFQ_FLAG_LOCAL) { -+ mcc->initfq.fqd.dest.channel = p->config->public_cfg.channel; -+ if (!(mcc->initfq.we_mask & QM_INITFQ_WE_DESTWQ)) { -+ mcc->initfq.we_mask |= QM_INITFQ_WE_DESTWQ; -+ mcc->initfq.fqd.dest.wq = 4; -+ } -+ } -+ mcc->initfq.we_mask = cpu_to_be16(mcc->initfq.we_mask); -+ cpu_to_hw_fqd(&mcc->initfq.fqd); -+ qm_mc_commit(&p->p, myverb); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb); -+ res = mcr->result; -+ if (res != QM_MCR_RESULT_OK) { -+ FQUNLOCK(fq); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return -EIO; -+ } -+ if (opts) { -+ if (opts->we_mask & QM_INITFQ_WE_FQCTRL) { -+ if (opts->fqd.fq_ctrl & QM_FQCTRL_CGE) -+ fq_set(fq, QMAN_FQ_STATE_CGR_EN); -+ else -+ fq_clear(fq, QMAN_FQ_STATE_CGR_EN); -+ } -+ if (opts->we_mask & QM_INITFQ_WE_CGID) -+ fq->cgr_groupid = opts->fqd.cgid; -+ } -+ fq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ? -+ qman_fq_state_sched : qman_fq_state_parked; -+ FQUNLOCK(fq); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return 0; -+} -+EXPORT_SYMBOL(qman_init_fq); -+ -+int qman_schedule_fq(struct qman_fq *fq) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ int ret = 0; -+ u8 res; -+ -+ if (fq->state != qman_fq_state_parked) -+ return -EINVAL; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))) -+ return -EINVAL; -+#endif -+ /* Issue a ALTERFQ_SCHED management command */ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ FQLOCK(fq); -+ if (unlikely((fq_isset(fq, QMAN_FQ_STATE_CHANGING)) || -+ (fq->state != qman_fq_state_parked))) { -+ ret = -EBUSY; -+ goto out; -+ } -+ mcc = qm_mc_start(&p->p); -+ mcc->alterfq.fqid = cpu_to_be32(fq->fqid); -+ qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_SCHED); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_SCHED); -+ res = mcr->result; -+ if (res != QM_MCR_RESULT_OK) { -+ ret = -EIO; -+ goto out; -+ } -+ fq->state = qman_fq_state_sched; -+out: -+ FQUNLOCK(fq); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(qman_schedule_fq); -+ -+int qman_retire_fq(struct qman_fq *fq, u32 *flags) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ int rval; -+ u8 res; -+ -+ if ((fq->state != qman_fq_state_parked) && -+ (fq->state != qman_fq_state_sched)) -+ return -EINVAL; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))) -+ return -EINVAL; -+#endif -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ FQLOCK(fq); -+ if (unlikely((fq_isset(fq, QMAN_FQ_STATE_CHANGING)) || -+ (fq->state == qman_fq_state_retired) || -+ (fq->state == qman_fq_state_oos))) { -+ rval = -EBUSY; -+ goto out; -+ } -+ rval = table_push_fq(p, fq); -+ if (rval) -+ goto out; -+ mcc = qm_mc_start(&p->p); -+ mcc->alterfq.fqid = cpu_to_be32(fq->fqid); -+ qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_RETIRE); -+ res = mcr->result; -+ /* "Elegant" would be to treat OK/PENDING the same way; set CHANGING, -+ * and defer the flags until FQRNI or FQRN (respectively) show up. But -+ * "Friendly" is to process OK immediately, and not set CHANGING. We do -+ * friendly, otherwise the caller doesn't necessarily have a fully -+ * "retired" FQ on return even if the retirement was immediate. However -+ * this does mean some code duplication between here and -+ * fq_state_change(). */ -+ if (likely(res == QM_MCR_RESULT_OK)) { -+ rval = 0; -+ /* Process 'fq' right away, we'll ignore FQRNI */ -+ if (mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) -+ fq_set(fq, QMAN_FQ_STATE_NE); -+ if (mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT) -+ fq_set(fq, QMAN_FQ_STATE_ORL); -+ else -+ table_del_fq(p, fq); -+ if (flags) -+ *flags = fq->flags; -+ fq->state = qman_fq_state_retired; -+ if (fq->cb.fqs) { -+ /* Another issue with supporting "immediate" retirement -+ * is that we're forced to drop FQRNIs, because by the -+ * time they're seen it may already be "too late" (the -+ * fq may have been OOS'd and free()'d already). But if -+ * the upper layer wants a callback whether it's -+ * immediate or not, we have to fake a "MR" entry to -+ * look like an FQRNI... */ -+ struct qm_mr_entry msg; -+ msg.verb = QM_MR_VERB_FQRNI; -+ msg.fq.fqs = mcr->alterfq.fqs; -+ msg.fq.fqid = fq->fqid; -+#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP -+ msg.fq.contextB = fq->key; -+#else -+ msg.fq.contextB = (u32)(uintptr_t)fq; -+#endif -+ fq->cb.fqs(p, fq, &msg); -+ } -+ } else if (res == QM_MCR_RESULT_PENDING) { -+ rval = 1; -+ fq_set(fq, QMAN_FQ_STATE_CHANGING); -+ } else { -+ rval = -EIO; -+ table_del_fq(p, fq); -+ } -+out: -+ FQUNLOCK(fq); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return rval; -+} -+EXPORT_SYMBOL(qman_retire_fq); -+ -+int qman_oos_fq(struct qman_fq *fq) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ int ret = 0; -+ u8 res; -+ -+ if (fq->state != qman_fq_state_retired) -+ return -EINVAL; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))) -+ return -EINVAL; -+#endif -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ FQLOCK(fq); -+ if (unlikely((fq_isset(fq, QMAN_FQ_STATE_BLOCKOOS)) || -+ (fq->state != qman_fq_state_retired))) { -+ ret = -EBUSY; -+ goto out; -+ } -+ mcc = qm_mc_start(&p->p); -+ mcc->alterfq.fqid = cpu_to_be32(fq->fqid); -+ qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_OOS); -+ res = mcr->result; -+ if (res != QM_MCR_RESULT_OK) { -+ ret = -EIO; -+ goto out; -+ } -+ fq->state = qman_fq_state_oos; -+out: -+ FQUNLOCK(fq); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(qman_oos_fq); -+ -+int qman_fq_flow_control(struct qman_fq *fq, int xon) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ int ret = 0; -+ u8 res; -+ u8 myverb; -+ -+ if ((fq->state == qman_fq_state_oos) || -+ (fq->state == qman_fq_state_retired) || -+ (fq->state == qman_fq_state_parked)) -+ return -EINVAL; -+ -+#ifdef CONFIG_FSL_DPA_CHECKING -+ if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))) -+ return -EINVAL; -+#endif -+ /* Issue a ALTER_FQXON or ALTER_FQXOFF management command */ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ FQLOCK(fq); -+ if (unlikely((fq_isset(fq, QMAN_FQ_STATE_CHANGING)) || -+ (fq->state == qman_fq_state_parked) || -+ (fq->state == qman_fq_state_oos) || -+ (fq->state == qman_fq_state_retired))) { -+ ret = -EBUSY; -+ goto out; -+ } -+ mcc = qm_mc_start(&p->p); -+ mcc->alterfq.fqid = fq->fqid; -+ mcc->alterfq.count = 0; -+ myverb = xon ? QM_MCC_VERB_ALTER_FQXON : QM_MCC_VERB_ALTER_FQXOFF; -+ -+ qm_mc_commit(&p->p, myverb); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb); -+ -+ res = mcr->result; -+ if (res != QM_MCR_RESULT_OK) { -+ ret = -EIO; -+ goto out; -+ } -+out: -+ FQUNLOCK(fq); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(qman_fq_flow_control); -+ -+int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p = get_affine_portal(); -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ mcc = qm_mc_start(&p->p); -+ mcc->queryfq.fqid = cpu_to_be32(fq->fqid); -+ qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ); -+ res = mcr->result; -+ if (res == QM_MCR_RESULT_OK) -+ memcpy_fromio(fqd, &mcr->queryfq.fqd, sizeof(*fqd)); -+ hw_fqd_to_cpu(fqd); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ if (res != QM_MCR_RESULT_OK) -+ return -EIO; -+ return 0; -+} -+EXPORT_SYMBOL(qman_query_fq); -+ -+int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p = get_affine_portal(); -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ mcc = qm_mc_start(&p->p); -+ mcc->queryfq.fqid = cpu_to_be32(fq->fqid); -+ qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP); -+ res = mcr->result; -+ if (res == QM_MCR_RESULT_OK) { -+ memcpy_fromio(np, &mcr->queryfq_np, sizeof(*np)); -+ np->fqd_link = be24_to_cpu(np->fqd_link); -+ np->odp_seq = be16_to_cpu(np->odp_seq); -+ np->orp_nesn = be16_to_cpu(np->orp_nesn); -+ np->orp_ea_hseq = be16_to_cpu(np->orp_ea_hseq); -+ np->orp_ea_tseq = be16_to_cpu(np->orp_ea_tseq); -+ np->orp_ea_hptr = be24_to_cpu(np->orp_ea_hptr); -+ np->orp_ea_tptr = be24_to_cpu(np->orp_ea_tptr); -+ np->pfdr_hptr = be24_to_cpu(np->pfdr_hptr); -+ np->pfdr_tptr = be24_to_cpu(np->pfdr_tptr); -+ np->ics_surp = be16_to_cpu(np->ics_surp); -+ np->byte_cnt = be32_to_cpu(np->byte_cnt); -+ np->frm_cnt = be24_to_cpu(np->frm_cnt); -+ np->ra1_sfdr = be16_to_cpu(np->ra1_sfdr); -+ np->ra2_sfdr = be16_to_cpu(np->ra2_sfdr); -+ np->od1_sfdr = be16_to_cpu(np->od1_sfdr); -+ np->od2_sfdr = be16_to_cpu(np->od2_sfdr); -+ np->od3_sfdr = be16_to_cpu(np->od3_sfdr); -+ -+ -+ } -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ if (res == QM_MCR_RESULT_ERR_FQID) -+ return -ERANGE; -+ else if (res != QM_MCR_RESULT_OK) -+ return -EIO; -+ return 0; -+} -+EXPORT_SYMBOL(qman_query_fq_np); -+ -+int qman_query_wq(u8 query_dedicated, struct qm_mcr_querywq *wq) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p = get_affine_portal(); -+ unsigned long irqflags __maybe_unused; -+ u8 res, myverb; -+ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ myverb = (query_dedicated) ? QM_MCR_VERB_QUERYWQ_DEDICATED : -+ QM_MCR_VERB_QUERYWQ; -+ mcc = qm_mc_start(&p->p); -+ mcc->querywq.channel.id = cpu_to_be16(wq->channel.id); -+ qm_mc_commit(&p->p, myverb); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb); -+ res = mcr->result; -+ if (res == QM_MCR_RESULT_OK) { -+ int i, array_len; -+ wq->channel.id = be16_to_cpu(mcr->querywq.channel.id); -+ array_len = ARRAY_SIZE(mcr->querywq.wq_len); -+ for (i = 0; i < array_len; i++) -+ wq->wq_len[i] = be32_to_cpu(mcr->querywq.wq_len[i]); -+ } -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("QUERYWQ failed: %s\n", mcr_result_str(res)); -+ return -EIO; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(qman_query_wq); -+ -+int qman_testwrite_cgr(struct qman_cgr *cgr, u64 i_bcnt, -+ struct qm_mcr_cgrtestwrite *result) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p = get_affine_portal(); -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ mcc = qm_mc_start(&p->p); -+ mcc->cgrtestwrite.cgid = cgr->cgrid; -+ mcc->cgrtestwrite.i_bcnt_hi = (u8)(i_bcnt >> 32); -+ mcc->cgrtestwrite.i_bcnt_lo = (u32)i_bcnt; -+ qm_mc_commit(&p->p, QM_MCC_VERB_CGRTESTWRITE); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_CGRTESTWRITE); -+ res = mcr->result; -+ if (res == QM_MCR_RESULT_OK) -+ memcpy_fromio(result, &mcr->cgrtestwrite, sizeof(*result)); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CGR TEST WRITE failed: %s\n", mcr_result_str(res)); -+ return -EIO; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(qman_testwrite_cgr); -+ -+int qman_query_cgr(struct qman_cgr *cgr, struct qm_mcr_querycgr *cgrd) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p = get_affine_portal(); -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ int i; -+ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ mcc = qm_mc_start(&p->p); -+ mcc->querycgr.cgid = cgr->cgrid; -+ qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCGR); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYCGR); -+ res = mcr->result; -+ if (res == QM_MCR_RESULT_OK) -+ memcpy_fromio(cgrd, &mcr->querycgr, sizeof(*cgrd)); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("QUERY_CGR failed: %s\n", mcr_result_str(res)); -+ return -EIO; -+ } -+ cgrd->cgr.wr_parm_g.word = -+ be32_to_cpu(cgrd->cgr.wr_parm_g.word); -+ cgrd->cgr.wr_parm_y.word = -+ be32_to_cpu(cgrd->cgr.wr_parm_y.word); -+ cgrd->cgr.wr_parm_r.word = -+ be32_to_cpu(cgrd->cgr.wr_parm_r.word); -+ cgrd->cgr.cscn_targ = be32_to_cpu(cgrd->cgr.cscn_targ); -+ cgrd->cgr.__cs_thres = be16_to_cpu(cgrd->cgr.__cs_thres); -+ for (i = 0; i < ARRAY_SIZE(cgrd->cscn_targ_swp); i++) -+ be32_to_cpus(&cgrd->cscn_targ_swp[i]); -+ return 0; -+} -+EXPORT_SYMBOL(qman_query_cgr); -+ -+int qman_query_congestion(struct qm_mcr_querycongestion *congestion) -+{ -+ struct qm_mc_result *mcr; -+ struct qman_portal *p = get_affine_portal(); -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ int i; -+ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ qm_mc_start(&p->p); -+ qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == -+ QM_MCC_VERB_QUERYCONGESTION); -+ res = mcr->result; -+ if (res == QM_MCR_RESULT_OK) -+ memcpy_fromio(congestion, &mcr->querycongestion, -+ sizeof(*congestion)); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("QUERY_CONGESTION failed: %s\n", mcr_result_str(res)); -+ return -EIO; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(congestion->state.__state); i++) -+ be32_to_cpus(&congestion->state.__state[i]); -+ return 0; -+} -+EXPORT_SYMBOL(qman_query_congestion); -+ -+/* internal function used as a wait_event() expression */ -+static int set_p_vdqcr(struct qman_portal *p, struct qman_fq *fq, u32 vdqcr) -+{ -+ unsigned long irqflags __maybe_unused; -+ int ret = -EBUSY; -+ PORTAL_IRQ_LOCK(p, irqflags); -+ if (!p->vdqcr_owned) { -+ FQLOCK(fq); -+ if (fq_isset(fq, QMAN_FQ_STATE_VDQCR)) -+ goto escape; -+ fq_set(fq, QMAN_FQ_STATE_VDQCR); -+ FQUNLOCK(fq); -+ p->vdqcr_owned = fq; -+ ret = 0; -+ } -+escape: -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ if (!ret) -+ qm_dqrr_vdqcr_set(&p->p, vdqcr); -+ return ret; -+} -+ -+static int set_vdqcr(struct qman_portal **p, struct qman_fq *fq, u32 vdqcr) -+{ -+ int ret; -+ *p = get_affine_portal(); -+ ret = set_p_vdqcr(*p, fq, vdqcr); -+ put_affine_portal(); -+ return ret; -+} -+ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+static int wait_p_vdqcr_start(struct qman_portal *p, struct qman_fq *fq, -+ u32 vdqcr, u32 flags) -+{ -+ int ret = 0; -+ if (flags & QMAN_VOLATILE_FLAG_WAIT_INT) -+ ret = wait_event_interruptible(affine_queue, -+ !(ret = set_p_vdqcr(p, fq, vdqcr))); -+ else -+ wait_event(affine_queue, !(ret = set_p_vdqcr(p, fq, vdqcr))); -+ return ret; -+} -+ -+static int wait_vdqcr_start(struct qman_portal **p, struct qman_fq *fq, -+ u32 vdqcr, u32 flags) -+{ -+ int ret = 0; -+ if (flags & QMAN_VOLATILE_FLAG_WAIT_INT) -+ ret = wait_event_interruptible(affine_queue, -+ !(ret = set_vdqcr(p, fq, vdqcr))); -+ else -+ wait_event(affine_queue, !(ret = set_vdqcr(p, fq, vdqcr))); -+ return ret; -+} -+#endif -+ -+int qman_p_volatile_dequeue(struct qman_portal *p, struct qman_fq *fq, -+ u32 flags __maybe_unused, u32 vdqcr) -+{ -+ int ret; -+ -+ if ((fq->state != qman_fq_state_parked) && -+ (fq->state != qman_fq_state_retired)) -+ return -EINVAL; -+ if (vdqcr & QM_VDQCR_FQID_MASK) -+ return -EINVAL; -+ if (fq_isset(fq, QMAN_FQ_STATE_VDQCR)) -+ return -EBUSY; -+ vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid; -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+ if (flags & QMAN_VOLATILE_FLAG_WAIT) -+ ret = wait_p_vdqcr_start(p, fq, vdqcr, flags); -+ else -+#endif -+ ret = set_p_vdqcr(p, fq, vdqcr); -+ if (ret) -+ return ret; -+ /* VDQCR is set */ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+ if (flags & QMAN_VOLATILE_FLAG_FINISH) { -+ if (flags & QMAN_VOLATILE_FLAG_WAIT_INT) -+ /* NB: don't propagate any error - the caller wouldn't -+ * know whether the VDQCR was issued or not. A signal -+ * could arrive after returning anyway, so the caller -+ * can check signal_pending() if that's an issue. */ -+ wait_event_interruptible(affine_queue, -+ !fq_isset(fq, QMAN_FQ_STATE_VDQCR)); -+ else -+ wait_event(affine_queue, -+ !fq_isset(fq, QMAN_FQ_STATE_VDQCR)); -+ } -+#endif -+ return 0; -+} -+EXPORT_SYMBOL(qman_p_volatile_dequeue); -+ -+int qman_volatile_dequeue(struct qman_fq *fq, u32 flags __maybe_unused, -+ u32 vdqcr) -+{ -+ struct qman_portal *p; -+ int ret; -+ -+ if ((fq->state != qman_fq_state_parked) && -+ (fq->state != qman_fq_state_retired)) -+ return -EINVAL; -+ if (vdqcr & QM_VDQCR_FQID_MASK) -+ return -EINVAL; -+ if (fq_isset(fq, QMAN_FQ_STATE_VDQCR)) -+ return -EBUSY; -+ vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid; -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+ if (flags & QMAN_VOLATILE_FLAG_WAIT) -+ ret = wait_vdqcr_start(&p, fq, vdqcr, flags); -+ else -+#endif -+ ret = set_vdqcr(&p, fq, vdqcr); -+ if (ret) -+ return ret; -+ /* VDQCR is set */ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+ if (flags & QMAN_VOLATILE_FLAG_FINISH) { -+ if (flags & QMAN_VOLATILE_FLAG_WAIT_INT) -+ /* NB: don't propagate any error - the caller wouldn't -+ * know whether the VDQCR was issued or not. A signal -+ * could arrive after returning anyway, so the caller -+ * can check signal_pending() if that's an issue. */ -+ wait_event_interruptible(affine_queue, -+ !fq_isset(fq, QMAN_FQ_STATE_VDQCR)); -+ else -+ wait_event(affine_queue, -+ !fq_isset(fq, QMAN_FQ_STATE_VDQCR)); -+ } -+#endif -+ return 0; -+} -+EXPORT_SYMBOL(qman_volatile_dequeue); -+ -+static noinline void update_eqcr_ci(struct qman_portal *p, u8 avail) -+{ -+ if (avail) -+ qm_eqcr_cce_prefetch(&p->p); -+ else -+ qm_eqcr_cce_update(&p->p); -+} -+ -+int qman_eqcr_is_empty(void) -+{ -+ unsigned long irqflags __maybe_unused; -+ struct qman_portal *p = get_affine_portal(); -+ u8 avail; -+ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ update_eqcr_ci(p, 0); -+ avail = qm_eqcr_get_fill(&p->p); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return avail == 0; -+} -+EXPORT_SYMBOL(qman_eqcr_is_empty); -+ -+void qman_set_dc_ern(qman_cb_dc_ern handler, int affine) -+{ -+ if (affine) { -+ unsigned long irqflags __maybe_unused; -+ struct qman_portal *p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ p->cb_dc_ern = handler; -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ } else -+ cb_dc_ern = handler; -+} -+EXPORT_SYMBOL(qman_set_dc_ern); -+ -+static inline struct qm_eqcr_entry *try_p_eq_start(struct qman_portal *p, -+ unsigned long *irqflags __maybe_unused, -+ struct qman_fq *fq, -+ const struct qm_fd *fd, -+ u32 flags) -+{ -+ struct qm_eqcr_entry *eq; -+ u8 avail; -+ PORTAL_IRQ_LOCK(p, (*irqflags)); -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ if (unlikely((flags & QMAN_ENQUEUE_FLAG_WAIT) && -+ (flags & QMAN_ENQUEUE_FLAG_WAIT_SYNC))) { -+ if (p->eqci_owned) { -+ PORTAL_IRQ_UNLOCK(p, (*irqflags)); -+ return NULL; -+ } -+ p->eqci_owned = fq; -+ } -+#endif -+ if (p->use_eqcr_ci_stashing) { -+ /* -+ * The stashing case is easy, only update if we need to in -+ * order to try and liberate ring entries. -+ */ -+ eq = qm_eqcr_start_stash(&p->p); -+ } else { -+ /* -+ * The non-stashing case is harder, need to prefetch ahead of -+ * time. -+ */ -+ avail = qm_eqcr_get_avail(&p->p); -+ if (avail < 2) -+ update_eqcr_ci(p, avail); -+ eq = qm_eqcr_start_no_stash(&p->p); -+ } -+ -+ if (unlikely(!eq)) { -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ if (unlikely((flags & QMAN_ENQUEUE_FLAG_WAIT) && -+ (flags & QMAN_ENQUEUE_FLAG_WAIT_SYNC))) -+ p->eqci_owned = NULL; -+#endif -+ PORTAL_IRQ_UNLOCK(p, (*irqflags)); -+ return NULL; -+ } -+ if (flags & QMAN_ENQUEUE_FLAG_DCA) -+ eq->dca = QM_EQCR_DCA_ENABLE | -+ ((flags & QMAN_ENQUEUE_FLAG_DCA_PARK) ? -+ QM_EQCR_DCA_PARK : 0) | -+ ((flags >> 8) & QM_EQCR_DCA_IDXMASK); -+ eq->fqid = cpu_to_be32(fq->fqid); -+#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP -+ eq->tag = cpu_to_be32(fq->key); -+#else -+ eq->tag = cpu_to_be32((u32)(uintptr_t)fq); -+#endif -+ eq->fd = *fd; -+ cpu_to_hw_fd(&eq->fd); -+ return eq; -+} -+ -+static inline struct qm_eqcr_entry *try_eq_start(struct qman_portal **p, -+ unsigned long *irqflags __maybe_unused, -+ struct qman_fq *fq, -+ const struct qm_fd *fd, -+ u32 flags) -+{ -+ struct qm_eqcr_entry *eq; -+ *p = get_affine_portal(); -+ eq = try_p_eq_start(*p, irqflags, fq, fd, flags); -+ if (!eq) -+ put_affine_portal(); -+ return eq; -+} -+ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+static noinline struct qm_eqcr_entry *__wait_eq_start(struct qman_portal **p, -+ unsigned long *irqflags __maybe_unused, -+ struct qman_fq *fq, -+ const struct qm_fd *fd, -+ u32 flags) -+{ -+ struct qm_eqcr_entry *eq = try_eq_start(p, irqflags, fq, fd, flags); -+ if (!eq) -+ qm_eqcr_set_ithresh(&(*p)->p, EQCR_ITHRESH); -+ return eq; -+} -+static noinline struct qm_eqcr_entry *wait_eq_start(struct qman_portal **p, -+ unsigned long *irqflags __maybe_unused, -+ struct qman_fq *fq, -+ const struct qm_fd *fd, -+ u32 flags) -+{ -+ struct qm_eqcr_entry *eq; -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT_INT) -+ /* NB: return NULL if signal occurs before completion. Signal -+ * can occur during return. Caller must check for signal */ -+ wait_event_interruptible(affine_queue, -+ (eq = __wait_eq_start(p, irqflags, fq, fd, flags))); -+ else -+ wait_event(affine_queue, -+ (eq = __wait_eq_start(p, irqflags, fq, fd, flags))); -+ return eq; -+} -+static noinline struct qm_eqcr_entry *__wait_p_eq_start(struct qman_portal *p, -+ unsigned long *irqflags __maybe_unused, -+ struct qman_fq *fq, -+ const struct qm_fd *fd, -+ u32 flags) -+{ -+ struct qm_eqcr_entry *eq = try_p_eq_start(p, irqflags, fq, fd, flags); -+ if (!eq) -+ qm_eqcr_set_ithresh(&p->p, EQCR_ITHRESH); -+ return eq; -+} -+static noinline struct qm_eqcr_entry *wait_p_eq_start(struct qman_portal *p, -+ unsigned long *irqflags __maybe_unused, -+ struct qman_fq *fq, -+ const struct qm_fd *fd, -+ u32 flags) -+{ -+ struct qm_eqcr_entry *eq; -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT_INT) -+ /* NB: return NULL if signal occurs before completion. Signal -+ * can occur during return. Caller must check for signal */ -+ wait_event_interruptible(affine_queue, -+ (eq = __wait_p_eq_start(p, irqflags, fq, fd, flags))); -+ else -+ wait_event(affine_queue, -+ (eq = __wait_p_eq_start(p, irqflags, fq, fd, flags))); -+ return eq; -+} -+#endif -+ -+int qman_p_enqueue(struct qman_portal *p, struct qman_fq *fq, -+ const struct qm_fd *fd, u32 flags) -+{ -+ struct qm_eqcr_entry *eq; -+ unsigned long irqflags __maybe_unused; -+ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT) -+ eq = wait_p_eq_start(p, &irqflags, fq, fd, flags); -+ else -+#endif -+ eq = try_p_eq_start(p, &irqflags, fq, fd, flags); -+ if (!eq) -+ return -EBUSY; -+ /* Note: QM_EQCR_VERB_INTERRUPT == QMAN_ENQUEUE_FLAG_WAIT_SYNC */ -+ qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE | -+ (flags & (QM_EQCR_VERB_COLOUR_MASK | QM_EQCR_VERB_INTERRUPT))); -+ /* Factor the below out, it's used from qman_enqueue_orp() too */ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ if (unlikely((flags & QMAN_ENQUEUE_FLAG_WAIT) && -+ (flags & QMAN_ENQUEUE_FLAG_WAIT_SYNC))) { -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT_INT) -+ /* NB: return success even if signal occurs before -+ * condition is true. pvb_commit guarantees success */ -+ wait_event_interruptible(affine_queue, -+ (p->eqci_owned != fq)); -+ else -+ wait_event(affine_queue, (p->eqci_owned != fq)); -+ } -+#endif -+ return 0; -+} -+EXPORT_SYMBOL(qman_p_enqueue); -+ -+int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd, u32 flags) -+{ -+ struct qman_portal *p; -+ struct qm_eqcr_entry *eq; -+ unsigned long irqflags __maybe_unused; -+ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT) -+ eq = wait_eq_start(&p, &irqflags, fq, fd, flags); -+ else -+#endif -+ eq = try_eq_start(&p, &irqflags, fq, fd, flags); -+ if (!eq) -+ return -EBUSY; -+ /* Note: QM_EQCR_VERB_INTERRUPT == QMAN_ENQUEUE_FLAG_WAIT_SYNC */ -+ qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE | -+ (flags & (QM_EQCR_VERB_COLOUR_MASK | QM_EQCR_VERB_INTERRUPT))); -+ /* Factor the below out, it's used from qman_enqueue_orp() too */ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ if (unlikely((flags & QMAN_ENQUEUE_FLAG_WAIT) && -+ (flags & QMAN_ENQUEUE_FLAG_WAIT_SYNC))) { -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT_INT) -+ /* NB: return success even if signal occurs before -+ * condition is true. pvb_commit guarantees success */ -+ wait_event_interruptible(affine_queue, -+ (p->eqci_owned != fq)); -+ else -+ wait_event(affine_queue, (p->eqci_owned != fq)); -+ } -+#endif -+ return 0; -+} -+EXPORT_SYMBOL(qman_enqueue); -+ -+int qman_p_enqueue_orp(struct qman_portal *p, struct qman_fq *fq, -+ const struct qm_fd *fd, u32 flags, -+ struct qman_fq *orp, u16 orp_seqnum) -+{ -+ struct qm_eqcr_entry *eq; -+ unsigned long irqflags __maybe_unused; -+ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT) -+ eq = wait_p_eq_start(p, &irqflags, fq, fd, flags); -+ else -+#endif -+ eq = try_p_eq_start(p, &irqflags, fq, fd, flags); -+ if (!eq) -+ return -EBUSY; -+ /* Process ORP-specifics here */ -+ if (flags & QMAN_ENQUEUE_FLAG_NLIS) -+ orp_seqnum |= QM_EQCR_SEQNUM_NLIS; -+ else { -+ orp_seqnum &= ~QM_EQCR_SEQNUM_NLIS; -+ if (flags & QMAN_ENQUEUE_FLAG_NESN) -+ orp_seqnum |= QM_EQCR_SEQNUM_NESN; -+ else -+ /* No need to check 4 QMAN_ENQUEUE_FLAG_HOLE */ -+ orp_seqnum &= ~QM_EQCR_SEQNUM_NESN; -+ } -+ eq->seqnum = cpu_to_be16(orp_seqnum); -+ eq->orp = cpu_to_be32(orp->fqid); -+ /* Note: QM_EQCR_VERB_INTERRUPT == QMAN_ENQUEUE_FLAG_WAIT_SYNC */ -+ qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_ORP | -+ ((flags & (QMAN_ENQUEUE_FLAG_HOLE | QMAN_ENQUEUE_FLAG_NESN)) ? -+ 0 : QM_EQCR_VERB_CMD_ENQUEUE) | -+ (flags & (QM_EQCR_VERB_COLOUR_MASK | QM_EQCR_VERB_INTERRUPT))); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ if (unlikely((flags & QMAN_ENQUEUE_FLAG_WAIT) && -+ (flags & QMAN_ENQUEUE_FLAG_WAIT_SYNC))) { -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT_INT) -+ /* NB: return success even if signal occurs before -+ * condition is true. pvb_commit guarantees success */ -+ wait_event_interruptible(affine_queue, -+ (p->eqci_owned != fq)); -+ else -+ wait_event(affine_queue, (p->eqci_owned != fq)); -+ } -+#endif -+ return 0; -+} -+EXPORT_SYMBOL(qman_p_enqueue_orp); -+ -+int qman_enqueue_orp(struct qman_fq *fq, const struct qm_fd *fd, u32 flags, -+ struct qman_fq *orp, u16 orp_seqnum) -+{ -+ struct qman_portal *p; -+ struct qm_eqcr_entry *eq; -+ unsigned long irqflags __maybe_unused; -+ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT) -+ eq = wait_eq_start(&p, &irqflags, fq, fd, flags); -+ else -+#endif -+ eq = try_eq_start(&p, &irqflags, fq, fd, flags); -+ if (!eq) -+ return -EBUSY; -+ /* Process ORP-specifics here */ -+ if (flags & QMAN_ENQUEUE_FLAG_NLIS) -+ orp_seqnum |= QM_EQCR_SEQNUM_NLIS; -+ else { -+ orp_seqnum &= ~QM_EQCR_SEQNUM_NLIS; -+ if (flags & QMAN_ENQUEUE_FLAG_NESN) -+ orp_seqnum |= QM_EQCR_SEQNUM_NESN; -+ else -+ /* No need to check 4 QMAN_ENQUEUE_FLAG_HOLE */ -+ orp_seqnum &= ~QM_EQCR_SEQNUM_NESN; -+ } -+ eq->seqnum = cpu_to_be16(orp_seqnum); -+ eq->orp = cpu_to_be32(orp->fqid); -+ /* Note: QM_EQCR_VERB_INTERRUPT == QMAN_ENQUEUE_FLAG_WAIT_SYNC */ -+ qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_ORP | -+ ((flags & (QMAN_ENQUEUE_FLAG_HOLE | QMAN_ENQUEUE_FLAG_NESN)) ? -+ 0 : QM_EQCR_VERB_CMD_ENQUEUE) | -+ (flags & (QM_EQCR_VERB_COLOUR_MASK | QM_EQCR_VERB_INTERRUPT))); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ if (unlikely((flags & QMAN_ENQUEUE_FLAG_WAIT) && -+ (flags & QMAN_ENQUEUE_FLAG_WAIT_SYNC))) { -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT_INT) -+ /* NB: return success even if signal occurs before -+ * condition is true. pvb_commit guarantees success */ -+ wait_event_interruptible(affine_queue, -+ (p->eqci_owned != fq)); -+ else -+ wait_event(affine_queue, (p->eqci_owned != fq)); -+ } -+#endif -+ return 0; -+} -+EXPORT_SYMBOL(qman_enqueue_orp); -+ -+int qman_p_enqueue_precommit(struct qman_portal *p, struct qman_fq *fq, -+ const struct qm_fd *fd, u32 flags, -+ qman_cb_precommit cb, void *cb_arg) -+{ -+ struct qm_eqcr_entry *eq; -+ unsigned long irqflags __maybe_unused; -+ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT) -+ eq = wait_p_eq_start(p, &irqflags, fq, fd, flags); -+ else -+#endif -+ eq = try_p_eq_start(p, &irqflags, fq, fd, flags); -+ if (!eq) -+ return -EBUSY; -+ /* invoke user supplied callback function before writing commit verb */ -+ if (cb(cb_arg)) { -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ return -EINVAL; -+ } -+ /* Note: QM_EQCR_VERB_INTERRUPT == QMAN_ENQUEUE_FLAG_WAIT_SYNC */ -+ qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE | -+ (flags & (QM_EQCR_VERB_COLOUR_MASK | QM_EQCR_VERB_INTERRUPT))); -+ /* Factor the below out, it's used from qman_enqueue_orp() too */ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ if (unlikely((flags & QMAN_ENQUEUE_FLAG_WAIT) && -+ (flags & QMAN_ENQUEUE_FLAG_WAIT_SYNC))) { -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT_INT) -+ /* NB: return success even if signal occurs before -+ * condition is true. pvb_commit guarantees success */ -+ wait_event_interruptible(affine_queue, -+ (p->eqci_owned != fq)); -+ else -+ wait_event(affine_queue, (p->eqci_owned != fq)); -+ } -+#endif -+ return 0; -+} -+EXPORT_SYMBOL(qman_p_enqueue_precommit); -+ -+int qman_enqueue_precommit(struct qman_fq *fq, const struct qm_fd *fd, -+ u32 flags, qman_cb_precommit cb, void *cb_arg) -+{ -+ struct qman_portal *p; -+ struct qm_eqcr_entry *eq; -+ unsigned long irqflags __maybe_unused; -+ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT) -+ eq = wait_eq_start(&p, &irqflags, fq, fd, flags); -+ else -+#endif -+ eq = try_eq_start(&p, &irqflags, fq, fd, flags); -+ if (!eq) -+ return -EBUSY; -+ /* invoke user supplied callback function before writing commit verb */ -+ if (cb(cb_arg)) { -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return -EINVAL; -+ } -+ /* Note: QM_EQCR_VERB_INTERRUPT == QMAN_ENQUEUE_FLAG_WAIT_SYNC */ -+ qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE | -+ (flags & (QM_EQCR_VERB_COLOUR_MASK | QM_EQCR_VERB_INTERRUPT))); -+ /* Factor the below out, it's used from qman_enqueue_orp() too */ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+ if (unlikely((flags & QMAN_ENQUEUE_FLAG_WAIT) && -+ (flags & QMAN_ENQUEUE_FLAG_WAIT_SYNC))) { -+ if (flags & QMAN_ENQUEUE_FLAG_WAIT_INT) -+ /* NB: return success even if signal occurs before -+ * condition is true. pvb_commit guarantees success */ -+ wait_event_interruptible(affine_queue, -+ (p->eqci_owned != fq)); -+ else -+ wait_event(affine_queue, (p->eqci_owned != fq)); -+ } -+#endif -+ return 0; -+} -+EXPORT_SYMBOL(qman_enqueue_precommit); -+ -+int qman_modify_cgr(struct qman_cgr *cgr, u32 flags, -+ struct qm_mcc_initcgr *opts) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p = get_affine_portal(); -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ u8 verb = QM_MCC_VERB_MODIFYCGR; -+ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ mcc = qm_mc_start(&p->p); -+ if (opts) -+ mcc->initcgr = *opts; -+ mcc->initcgr.we_mask = cpu_to_be16(mcc->initcgr.we_mask); -+ mcc->initcgr.cgr.wr_parm_g.word = -+ cpu_to_be32(mcc->initcgr.cgr.wr_parm_g.word); -+ mcc->initcgr.cgr.wr_parm_y.word = -+ cpu_to_be32(mcc->initcgr.cgr.wr_parm_y.word); -+ mcc->initcgr.cgr.wr_parm_r.word = -+ cpu_to_be32(mcc->initcgr.cgr.wr_parm_r.word); -+ mcc->initcgr.cgr.cscn_targ = cpu_to_be32(mcc->initcgr.cgr.cscn_targ); -+ mcc->initcgr.cgr.__cs_thres = cpu_to_be16(mcc->initcgr.cgr.__cs_thres); -+ -+ mcc->initcgr.cgid = cgr->cgrid; -+ if (flags & QMAN_CGR_FLAG_USE_INIT) -+ verb = QM_MCC_VERB_INITCGR; -+ qm_mc_commit(&p->p, verb); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == verb); -+ res = mcr->result; -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return (res == QM_MCR_RESULT_OK) ? 0 : -EIO; -+} -+EXPORT_SYMBOL(qman_modify_cgr); -+ -+#define TARG_MASK(n) (0x80000000 >> (n->config->public_cfg.channel - \ -+ QM_CHANNEL_SWPORTAL0)) -+#define TARG_DCP_MASK(n) (0x80000000 >> (10 + n)) -+#define PORTAL_IDX(n) (n->config->public_cfg.channel - QM_CHANNEL_SWPORTAL0) -+ -+static u8 qman_cgr_cpus[__CGR_NUM]; -+ -+int qman_create_cgr(struct qman_cgr *cgr, u32 flags, -+ struct qm_mcc_initcgr *opts) -+{ -+ unsigned long irqflags __maybe_unused; -+ struct qm_mcr_querycgr cgr_state; -+ struct qm_mcc_initcgr local_opts; -+ int ret; -+ struct qman_portal *p; -+ -+ /* We have to check that the provided CGRID is within the limits of the -+ * data-structures, for obvious reasons. However we'll let h/w take -+ * care of determining whether it's within the limits of what exists on -+ * the SoC. */ -+ if (cgr->cgrid >= __CGR_NUM) -+ return -EINVAL; -+ -+ preempt_disable(); -+ p = get_affine_portal(); -+ qman_cgr_cpus[cgr->cgrid] = smp_processor_id(); -+ preempt_enable(); -+ -+ memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr)); -+ cgr->chan = p->config->public_cfg.channel; -+ spin_lock_irqsave(&p->cgr_lock, irqflags); -+ -+ /* if no opts specified, just add it to the list */ -+ if (!opts) -+ goto add_list; -+ -+ ret = qman_query_cgr(cgr, &cgr_state); -+ if (ret) -+ goto release_lock; -+ if (opts) -+ local_opts = *opts; -+ if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) -+ local_opts.cgr.cscn_targ_upd_ctrl = -+ QM_CGR_TARG_UDP_CTRL_WRITE_BIT | PORTAL_IDX(p); -+ else -+ /* Overwrite TARG */ -+ local_opts.cgr.cscn_targ = cgr_state.cgr.cscn_targ | -+ TARG_MASK(p); -+ local_opts.we_mask |= QM_CGR_WE_CSCN_TARG; -+ -+ /* send init if flags indicate so */ -+ if (opts && (flags & QMAN_CGR_FLAG_USE_INIT)) -+ ret = qman_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT, &local_opts); -+ else -+ ret = qman_modify_cgr(cgr, 0, &local_opts); -+ if (ret) -+ goto release_lock; -+add_list: -+ list_add(&cgr->node, &p->cgr_cbs); -+ -+ /* Determine if newly added object requires its callback to be called */ -+ ret = qman_query_cgr(cgr, &cgr_state); -+ if (ret) { -+ /* we can't go back, so proceed and return success, but screen -+ * and wail to the log file */ -+ pr_crit("CGR HW state partially modified\n"); -+ ret = 0; -+ goto release_lock; -+ } -+ if (cgr->cb && cgr_state.cgr.cscn_en && qman_cgrs_get(&p->cgrs[1], -+ cgr->cgrid)) -+ cgr->cb(p, cgr, 1); -+release_lock: -+ spin_unlock_irqrestore(&p->cgr_lock, irqflags); -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(qman_create_cgr); -+ -+int qman_create_cgr_to_dcp(struct qman_cgr *cgr, u32 flags, u16 dcp_portal, -+ struct qm_mcc_initcgr *opts) -+{ -+ unsigned long irqflags __maybe_unused; -+ struct qm_mcc_initcgr local_opts; -+ struct qm_mcr_querycgr cgr_state; -+ int ret; -+ -+ /* We have to check that the provided CGRID is within the limits of the -+ * data-structures, for obvious reasons. However we'll let h/w take -+ * care of determining whether it's within the limits of what exists on -+ * the SoC. -+ */ -+ if (cgr->cgrid >= __CGR_NUM) -+ return -EINVAL; -+ -+ ret = qman_query_cgr(cgr, &cgr_state); -+ if (ret) -+ return ret; -+ -+ memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr)); -+ if (opts) -+ local_opts = *opts; -+ -+ if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) -+ local_opts.cgr.cscn_targ_upd_ctrl = -+ QM_CGR_TARG_UDP_CTRL_WRITE_BIT | -+ QM_CGR_TARG_UDP_CTRL_DCP | dcp_portal; -+ else -+ local_opts.cgr.cscn_targ = cgr_state.cgr.cscn_targ | -+ TARG_DCP_MASK(dcp_portal); -+ local_opts.we_mask |= QM_CGR_WE_CSCN_TARG; -+ -+ /* send init if flags indicate so */ -+ if (opts && (flags & QMAN_CGR_FLAG_USE_INIT)) -+ ret = qman_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT, -+ &local_opts); -+ else -+ ret = qman_modify_cgr(cgr, 0, &local_opts); -+ -+ return ret; -+} -+EXPORT_SYMBOL(qman_create_cgr_to_dcp); -+ -+int qman_delete_cgr(struct qman_cgr *cgr) -+{ -+ unsigned long irqflags __maybe_unused; -+ struct qm_mcr_querycgr cgr_state; -+ struct qm_mcc_initcgr local_opts; -+ int ret = 0; -+ struct qman_cgr *i; -+ struct qman_portal *p = get_affine_portal(); -+ -+ if (cgr->chan != p->config->public_cfg.channel) { -+ pr_crit("Attempting to delete cgr from different portal " -+ "than it was create: create 0x%x, delete 0x%x\n", -+ cgr->chan, p->config->public_cfg.channel); -+ ret = -EINVAL; -+ goto put_portal; -+ } -+ memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr)); -+ spin_lock_irqsave(&p->cgr_lock, irqflags); -+ list_del(&cgr->node); -+ /* -+ * If there are no other CGR objects for this CGRID in the list, update -+ * CSCN_TARG accordingly -+ */ -+ list_for_each_entry(i, &p->cgr_cbs, node) -+ if ((i->cgrid == cgr->cgrid) && i->cb) -+ goto release_lock; -+ ret = qman_query_cgr(cgr, &cgr_state); -+ if (ret) { -+ /* add back to the list */ -+ list_add(&cgr->node, &p->cgr_cbs); -+ goto release_lock; -+ } -+ /* Overwrite TARG */ -+ local_opts.we_mask = QM_CGR_WE_CSCN_TARG; -+ if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) -+ local_opts.cgr.cscn_targ_upd_ctrl = PORTAL_IDX(p); -+ else -+ local_opts.cgr.cscn_targ = cgr_state.cgr.cscn_targ & -+ ~(TARG_MASK(p)); -+ ret = qman_modify_cgr(cgr, 0, &local_opts); -+ if (ret) -+ /* add back to the list */ -+ list_add(&cgr->node, &p->cgr_cbs); -+release_lock: -+ spin_unlock_irqrestore(&p->cgr_lock, irqflags); -+put_portal: -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(qman_delete_cgr); -+ -+struct cgr_comp { -+ struct qman_cgr *cgr; -+ struct completion completion; -+}; -+ -+static int qman_delete_cgr_thread(void *p) -+{ -+ struct cgr_comp *cgr_comp = (struct cgr_comp *)p; -+ int res; -+ -+ res = qman_delete_cgr((struct qman_cgr *)cgr_comp->cgr); -+ complete(&cgr_comp->completion); -+ -+ return res; -+} -+ -+void qman_delete_cgr_safe(struct qman_cgr *cgr) -+{ -+ struct task_struct *thread; -+ struct cgr_comp cgr_comp; -+ -+ preempt_disable(); -+ if (qman_cgr_cpus[cgr->cgrid] != smp_processor_id()) { -+ init_completion(&cgr_comp.completion); -+ cgr_comp.cgr = cgr; -+ thread = kthread_create(qman_delete_cgr_thread, &cgr_comp, -+ "cgr_del"); -+ -+ if (likely(!IS_ERR(thread))) { -+ kthread_bind(thread, qman_cgr_cpus[cgr->cgrid]); -+ wake_up_process(thread); -+ wait_for_completion(&cgr_comp.completion); -+ preempt_enable(); -+ return; -+ } -+ } -+ qman_delete_cgr(cgr); -+ preempt_enable(); -+} -+EXPORT_SYMBOL(qman_delete_cgr_safe); -+ -+int qm_get_clock(u64 *clock_hz) -+{ -+ if (!qman_clk) { -+ pr_warn("Qman clock speed is unknown\n"); -+ return -EINVAL; -+ } -+ *clock_hz = (u64)qman_clk; -+ return 0; -+} -+EXPORT_SYMBOL(qm_get_clock); -+ -+int qm_set_clock(u64 clock_hz) -+{ -+ if (qman_clk) -+ return -1; -+ qman_clk = (u32)clock_hz; -+ return 0; -+} -+EXPORT_SYMBOL(qm_set_clock); -+ -+/* CEETM management command */ -+static int qman_ceetm_configure_lfqmt(struct qm_mcc_ceetm_lfqmt_config *opts) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->lfqmt_config = *opts; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_LFQMT_CONFIG); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == -+ QM_CEETM_VERB_LFQMT_CONFIG); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ -+ res = mcr->result; -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: CONFIGURE LFQMT failed\n"); -+ return -EIO; -+ } -+ return 0; -+} -+ -+int qman_ceetm_query_lfqmt(int lfqid, -+ struct qm_mcr_ceetm_lfqmt_query *lfqmt_query) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->lfqmt_query.lfqid = lfqid; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_LFQMT_QUERY); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_CEETM_VERB_LFQMT_QUERY); -+ res = mcr->result; -+ if (res == QM_MCR_RESULT_OK) -+ *lfqmt_query = mcr->lfqmt_query; -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: QUERY LFQMT failed\n"); -+ return -EIO; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_query_lfqmt); -+ -+static int qman_ceetm_configure_cq(struct qm_mcc_ceetm_cq_config *opts) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->cq_config = *opts; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_CQ_CONFIG); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ res = mcr->result; -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_CEETM_VERB_CQ_CONFIG); -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: CONFIGURE CQ failed\n"); -+ return -EIO; -+ } -+ return 0; -+} -+ -+int qman_ceetm_query_cq(unsigned int cqid, unsigned int dcpid, -+ struct qm_mcr_ceetm_cq_query *cq_query) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->cq_query.cqid = cpu_to_be16(cqid); -+ mcc->cq_query.dcpid = dcpid; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_CQ_QUERY); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_CEETM_VERB_CQ_QUERY); -+ res = mcr->result; -+ if (res == QM_MCR_RESULT_OK) { -+ *cq_query = mcr->cq_query; -+ hw_cq_query_to_cpu(cq_query); -+ } -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: QUERY CQ failed\n"); -+ return -EIO; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_query_cq); -+ -+static int qman_ceetm_configure_dct(struct qm_mcc_ceetm_dct_config *opts) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->dct_config = *opts; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_DCT_CONFIG); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_CEETM_VERB_DCT_CONFIG); -+ res = mcr->result; -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: CONFIGURE DCT failed\n"); -+ return -EIO; -+ } -+ return 0; -+} -+ -+static int qman_ceetm_query_dct(struct qm_mcc_ceetm_dct_query *opts, -+ struct qm_mcr_ceetm_dct_query *dct_query) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p = get_affine_portal(); -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->dct_query = *opts; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_DCT_QUERY); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_CEETM_VERB_DCT_QUERY); -+ res = mcr->result; -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: QUERY DCT failed\n"); -+ return -EIO; -+ } -+ -+ *dct_query = mcr->dct_query; -+ return 0; -+} -+ -+static int qman_ceetm_configure_class_scheduler( -+ struct qm_mcc_ceetm_class_scheduler_config *opts) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->csch_config = *opts; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_CLASS_SCHEDULER_CONFIG); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == -+ QM_CEETM_VERB_CLASS_SCHEDULER_CONFIG); -+ res = mcr->result; -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: CONFIGURE CLASS SCHEDULER failed\n"); -+ return -EIO; -+ } -+ return 0; -+} -+ -+static int qman_ceetm_query_class_scheduler(struct qm_ceetm_channel *channel, -+ struct qm_mcr_ceetm_class_scheduler_query *query) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->csch_query.cqcid = channel->idx; -+ mcc->csch_query.dcpid = channel->dcp_idx; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_CLASS_SCHEDULER_QUERY); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == -+ QM_CEETM_VERB_CLASS_SCHEDULER_QUERY); -+ res = mcr->result; -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: QUERY CLASS SCHEDULER failed\n"); -+ return -EIO; -+ } -+ *query = mcr->csch_query; -+ return 0; -+} -+ -+static int qman_ceetm_configure_mapping_shaper_tcfc( -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config *opts) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->mst_config = *opts; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_MAPPING_SHAPER_TCFC_CONFIG); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == -+ QM_CEETM_VERB_MAPPING_SHAPER_TCFC_CONFIG); -+ res = mcr->result; -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: CONFIGURE CHANNEL MAPPING failed\n"); -+ return -EIO; -+ } -+ return 0; -+} -+ -+static int qman_ceetm_query_mapping_shaper_tcfc( -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query *opts, -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query *response) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->mst_query = *opts; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_MAPPING_SHAPER_TCFC_QUERY); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == -+ QM_CEETM_VERB_MAPPING_SHAPER_TCFC_QUERY); -+ res = mcr->result; -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: QUERY CHANNEL MAPPING failed\n"); -+ return -EIO; -+ } -+ -+ *response = mcr->mst_query; -+ return 0; -+} -+ -+static int qman_ceetm_configure_ccgr(struct qm_mcc_ceetm_ccgr_config *opts) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->ccgr_config = *opts; -+ -+ qm_mc_commit(&p->p, QM_CEETM_VERB_CCGR_CONFIG); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_CEETM_VERB_CCGR_CONFIG); -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ -+ res = mcr->result; -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: CONFIGURE CCGR failed\n"); -+ return -EIO; -+ } -+ return 0; -+} -+ -+int qman_ceetm_query_ccgr(struct qm_mcc_ceetm_ccgr_query *ccgr_query, -+ struct qm_mcr_ceetm_ccgr_query *response) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->ccgr_query.ccgrid = cpu_to_be16(ccgr_query->ccgrid); -+ mcc->ccgr_query.dcpid = ccgr_query->dcpid; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_CCGR_QUERY); -+ -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_CEETM_VERB_CCGR_QUERY); -+ res = mcr->result; -+ if (res == QM_MCR_RESULT_OK) { -+ *response = mcr->ccgr_query; -+ hw_ccgr_query_to_cpu(response); -+ } -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: QUERY CCGR failed\n"); -+ return -EIO; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_query_ccgr); -+ -+static int qman_ceetm_cq_peek_pop_xsfdrread(struct qm_ceetm_cq *cq, -+ u8 command_type, u16 xsfdr, -+ struct qm_mcr_ceetm_cq_peek_pop_xsfdrread *cq_ppxr) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ switch (command_type) { -+ case 0: -+ case 1: -+ mcc->cq_ppxr.cqid = (cq->parent->idx << 4) | cq->idx; -+ break; -+ case 2: -+ mcc->cq_ppxr.xsfdr = xsfdr; -+ break; -+ default: -+ break; -+ } -+ mcc->cq_ppxr.ct = command_type; -+ mcc->cq_ppxr.dcpid = cq->parent->dcp_idx; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_CQ_PEEK_POP_XFDRREAD); -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == -+ QM_CEETM_VERB_CQ_PEEK_POP_XFDRREAD); -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ -+ res = mcr->result; -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: CQ PEEK/POP/XSFDR READ failed\n"); -+ return -EIO; -+ } -+ *cq_ppxr = mcr->cq_ppxr; -+ return 0; -+} -+ -+static int qman_ceetm_query_statistics(u16 cid, -+ enum qm_dc_portal dcp_idx, -+ u16 command_type, -+ struct qm_mcr_ceetm_statistics_query *query_result) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->stats_query_write.cid = cid; -+ mcc->stats_query_write.dcpid = dcp_idx; -+ mcc->stats_query_write.ct = command_type; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_STATISTICS_QUERY_WRITE); -+ -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == -+ QM_CEETM_VERB_STATISTICS_QUERY_WRITE); -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ -+ res = mcr->result; -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: STATISTICS QUERY failed\n"); -+ return -EIO; -+ } -+ *query_result = mcr->stats_query; -+ return 0; -+} -+ -+int qman_ceetm_query_write_statistics(u16 cid, enum qm_dc_portal dcp_idx, -+ u16 command_type, u64 frame_count, -+ u64 byte_count) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ mcc->stats_query_write.cid = cid; -+ mcc->stats_query_write.dcpid = dcp_idx; -+ mcc->stats_query_write.ct = command_type; -+ mcc->stats_query_write.frm_cnt = frame_count; -+ mcc->stats_query_write.byte_cnt = byte_count; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_STATISTICS_QUERY_WRITE); -+ -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == -+ QM_CEETM_VERB_STATISTICS_QUERY_WRITE); -+ -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ -+ res = mcr->result; -+ if (res != QM_MCR_RESULT_OK) { -+ pr_err("CEETM: STATISTICS WRITE failed\n"); -+ return -EIO; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_query_write_statistics); -+ -+int qman_ceetm_bps2tokenrate(u64 bps, struct qm_ceetm_rate *token_rate, -+ int rounding) -+{ -+ u16 pres; -+ u64 temp; -+ u64 qman_freq; -+ int ret; -+ -+ /* Read PRES from CEET_CFG_PRES register */ -+ ret = qman_ceetm_get_prescaler(&pres); -+ if (ret) -+ return -EINVAL; -+ -+ ret = qm_get_clock(&qman_freq); -+ if (ret) -+ return -EINVAL; -+ -+ /* token-rate = bytes-per-second * update-reference-period -+ * -+ * Where token-rate is N/8192 for a integer N, and -+ * update-reference-period is (2^22)/(PRES*QHz), where PRES -+ * is the prescalar value and QHz is the QMan clock frequency. -+ * So: -+ * -+ * token-rate = (byte-per-second*2^22)/PRES*QHZ) -+ * -+ * Converting to bits-per-second gives; -+ * -+ * token-rate = (bps*2^19) / (PRES*QHZ) -+ * N = (bps*2^32) / (PRES*QHz) -+ * -+ * And to avoid 64-bit overflow if 'bps' is larger than 4Gbps -+ * (yet minimise rounding error if 'bps' is small), we reorganise -+ * the formula to use two 16-bit shifts rather than 1 32-bit shift. -+ * N = (((bps*2^16)/PRES)*2^16)/QHz -+ */ -+ temp = ROUNDING((bps << 16), pres, rounding); -+ temp = ROUNDING((temp << 16), qman_freq, rounding); -+ token_rate->whole = temp >> 13; -+ token_rate->fraction = temp & (((u64)1 << 13) - 1); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_bps2tokenrate); -+ -+int qman_ceetm_tokenrate2bps(const struct qm_ceetm_rate *token_rate, u64 *bps, -+ int rounding) -+{ -+ u16 pres; -+ u64 temp; -+ u64 qman_freq; -+ int ret; -+ -+ /* Read PRES from CEET_CFG_PRES register */ -+ ret = qman_ceetm_get_prescaler(&pres); -+ if (ret) -+ return -EINVAL; -+ -+ ret = qm_get_clock(&qman_freq); -+ if (ret) -+ return -EINVAL; -+ -+ /* bytes-per-second = token-rate / update-reference-period -+ * -+ * where "token-rate" is N/8192 for an integer N, and -+ * "update-reference-period" is (2^22)/(PRES*QHz), where PRES is -+ * the prescalar value and QHz is the QMan clock frequency. So; -+ * -+ * bytes-per-second = (N/8192) / (4194304/PRES*QHz) -+ * = N*PRES*QHz / (4194304*8192) -+ * = N*PRES*QHz / (2^35) -+ * -+ * Converting to bits-per-second gives; -+ * -+ * bps = N*PRES*QHZ / (2^32) -+ * -+ * Note, the numerator has a maximum width of 72 bits! So to -+ * avoid 64-bit overflow errors, we calculate PRES*QHZ (maximum -+ * width 48 bits) divided by 2^9 (reducing to maximum 39 bits), before -+ * multiplying by N (goes to maximum of 63 bits). -+ * -+ * temp = PRES*QHZ / (2^16) -+ * kbps = temp*N / (2^16) -+ */ -+ temp = ROUNDING(qman_freq * pres, (u64)1 << 16 , rounding); -+ temp *= ((token_rate->whole << 13) + token_rate->fraction); -+ *bps = ROUNDING(temp, (u64)(1) << 16, rounding); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_tokenrate2bps); -+ -+int qman_ceetm_sp_claim(struct qm_ceetm_sp **sp, enum qm_dc_portal dcp_idx, -+ unsigned int sp_idx) -+{ -+ struct qm_ceetm_sp *p; -+ -+ DPA_ASSERT((dcp_idx == qm_dc_portal_fman0) || -+ (dcp_idx == qm_dc_portal_fman1)); -+ -+ if ((sp_idx < qman_ceetms[dcp_idx].sp_range[0]) || -+ (sp_idx > (qman_ceetms[dcp_idx].sp_range[0] + -+ qman_ceetms[dcp_idx].sp_range[1]))) { -+ pr_err("Sub-portal index doesn't exist\n"); -+ return -EINVAL; -+ } -+ -+ list_for_each_entry(p, &qman_ceetms[dcp_idx].sub_portals, node) { -+ if ((p->idx == sp_idx) && (p->is_claimed == 0)) { -+ p->is_claimed = 1; -+ *sp = p; -+ return 0; -+ } -+ } -+ pr_err("The sub-portal#%d is not available!\n", sp_idx); -+ return -ENODEV; -+} -+EXPORT_SYMBOL(qman_ceetm_sp_claim); -+ -+int qman_ceetm_sp_release(struct qm_ceetm_sp *sp) -+{ -+ struct qm_ceetm_sp *p; -+ -+ if (sp->lni && sp->lni->is_claimed == 1) { -+ pr_err("The dependency of sub-portal has not been released!\n"); -+ return -EBUSY; -+ } -+ -+ list_for_each_entry(p, &qman_ceetms[sp->dcp_idx].sub_portals, node) { -+ if (p->idx == sp->idx) { -+ p->is_claimed = 0; -+ p->lni = NULL; -+ } -+ } -+ /* Disable CEETM mode of this sub-portal */ -+ qman_sp_disable_ceetm_mode(sp->dcp_idx, sp->idx); -+ -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_sp_release); -+ -+int qman_ceetm_lni_claim(struct qm_ceetm_lni **lni, enum qm_dc_portal dcp_idx, -+ unsigned int lni_idx) -+{ -+ struct qm_ceetm_lni *p; -+ -+ if ((lni_idx < qman_ceetms[dcp_idx].lni_range[0]) || -+ (lni_idx > (qman_ceetms[dcp_idx].lni_range[0] + -+ qman_ceetms[dcp_idx].lni_range[1]))) { -+ pr_err("The lni index is out of range\n"); -+ return -EINVAL; -+ } -+ -+ list_for_each_entry(p, &qman_ceetms[dcp_idx].lnis, node) { -+ if ((p->idx == lni_idx) && (p->is_claimed == 0)) { -+ *lni = p; -+ p->is_claimed = 1; -+ return 0; -+ } -+ } -+ -+ pr_err("The LNI#%d is not available!\n", lni_idx); -+ return -EINVAL; -+} -+EXPORT_SYMBOL(qman_ceetm_lni_claim); -+ -+int qman_ceetm_lni_release(struct qm_ceetm_lni *lni) -+{ -+ struct qm_ceetm_lni *p; -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ -+ if (!list_empty(&lni->channels)) { -+ pr_err("The LNI dependencies are not released!\n"); -+ return -EBUSY; -+ } -+ -+ list_for_each_entry(p, &qman_ceetms[lni->dcp_idx].lnis, node) { -+ if (p->idx == lni->idx) { -+ p->shaper_enable = 0; -+ p->shaper_couple = 0; -+ p->cr_token_rate.whole = 0; -+ p->cr_token_rate.fraction = 0; -+ p->er_token_rate.whole = 0; -+ p->er_token_rate.fraction = 0; -+ p->cr_token_bucket_limit = 0; -+ p->er_token_bucket_limit = 0; -+ p->is_claimed = 0; -+ } -+ } -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_LNI_SHAPER | lni->idx); -+ config_opts.dcpid = lni->dcp_idx; -+ memset(&config_opts.shaper_config, 0, -+ sizeof(config_opts.shaper_config)); -+ return qman_ceetm_configure_mapping_shaper_tcfc(&config_opts); -+} -+EXPORT_SYMBOL(qman_ceetm_lni_release); -+ -+int qman_ceetm_sp_set_lni(struct qm_ceetm_sp *sp, struct qm_ceetm_lni *lni) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_SP_MAPPING | sp->idx); -+ config_opts.dcpid = sp->dcp_idx; -+ config_opts.sp_mapping.map_lni_id = lni->idx; -+ sp->lni = lni; -+ -+ if (qman_ceetm_configure_mapping_shaper_tcfc(&config_opts)) -+ return -EINVAL; -+ -+ /* Enable CEETM mode for this sub-portal */ -+ return qman_sp_enable_ceetm_mode(sp->dcp_idx, sp->idx); -+} -+EXPORT_SYMBOL(qman_ceetm_sp_set_lni); -+ -+int qman_ceetm_sp_get_lni(struct qm_ceetm_sp *sp, unsigned int *lni_idx) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_SP_MAPPING | sp->idx); -+ query_opts.dcpid = sp->dcp_idx; -+ if (qman_ceetm_query_mapping_shaper_tcfc(&query_opts, &query_result)) { -+ pr_err("Can't get SP <-> LNI mapping\n"); -+ return -EINVAL; -+ } -+ *lni_idx = query_result.sp_mapping_query.map_lni_id; -+ sp->lni->idx = query_result.sp_mapping_query.map_lni_id; -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_sp_get_lni); -+ -+int qman_ceetm_lni_enable_shaper(struct qm_ceetm_lni *lni, int coupled, -+ int oal) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ -+ lni->shaper_enable = 1; -+ lni->shaper_couple = coupled; -+ lni->oal = oal; -+ -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_LNI_SHAPER | lni->idx); -+ config_opts.dcpid = lni->dcp_idx; -+ config_opts.shaper_config.cpl = coupled; -+ config_opts.shaper_config.oal = oal; -+ config_opts.shaper_config.crtcr = cpu_to_be24((lni->cr_token_rate.whole -+ << 13) | lni->cr_token_rate.fraction); -+ config_opts.shaper_config.ertcr = cpu_to_be24((lni->er_token_rate.whole -+ << 13) | lni->er_token_rate.fraction); -+ config_opts.shaper_config.crtbl = -+ cpu_to_be16(lni->cr_token_bucket_limit); -+ config_opts.shaper_config.ertbl = -+ cpu_to_be16(lni->er_token_bucket_limit); -+ config_opts.shaper_config.mps = 60; -+ -+ return qman_ceetm_configure_mapping_shaper_tcfc(&config_opts); -+} -+EXPORT_SYMBOL(qman_ceetm_lni_enable_shaper); -+ -+int qman_ceetm_lni_disable_shaper(struct qm_ceetm_lni *lni) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ -+ if (!lni->shaper_enable) { -+ pr_err("The shaper has been disabled\n"); -+ return -EINVAL; -+ } -+ -+ config_opts.cid = CEETM_COMMAND_LNI_SHAPER | lni->idx; -+ config_opts.dcpid = lni->dcp_idx; -+ config_opts.shaper_config.cpl = (lni->shaper_couple << 7) | lni->oal; -+ config_opts.shaper_config.crtbl = lni->cr_token_bucket_limit; -+ config_opts.shaper_config.ertbl = lni->er_token_bucket_limit; -+ /* Set CR/ER rate with all 1's to configure an infinite rate, thus -+ * disable the shaping. -+ */ -+ config_opts.shaper_config.crtcr = 0xFFFFFF; -+ config_opts.shaper_config.ertcr = 0xFFFFFF; -+ config_opts.shaper_config.mps = 60; -+ lni->shaper_enable = 0; -+ return qman_ceetm_configure_mapping_shaper_tcfc(&config_opts); -+} -+EXPORT_SYMBOL(qman_ceetm_lni_disable_shaper); -+ -+int qman_ceetm_lni_is_shaper_enabled(struct qm_ceetm_lni *lni) -+{ -+ return lni->shaper_enable; -+} -+EXPORT_SYMBOL(qman_ceetm_lni_is_shaper_enabled); -+ -+int qman_ceetm_lni_set_commit_rate(struct qm_ceetm_lni *lni, -+ const struct qm_ceetm_rate *token_rate, -+ u16 token_limit) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ int ret; -+ -+ lni->cr_token_rate.whole = token_rate->whole; -+ lni->cr_token_rate.fraction = token_rate->fraction; -+ lni->cr_token_bucket_limit = token_limit; -+ if (!lni->shaper_enable) -+ return 0; -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_LNI_SHAPER | lni->idx); -+ query_opts.dcpid = lni->dcp_idx; -+ ret = qman_ceetm_query_mapping_shaper_tcfc(&query_opts, -+ &query_result); -+ if (ret) { -+ pr_err("Fail to get current LNI shaper setting\n"); -+ return -EINVAL; -+ } -+ -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_LNI_SHAPER | lni->idx); -+ config_opts.dcpid = lni->dcp_idx; -+ config_opts.shaper_config.crtcr = cpu_to_be24((token_rate->whole << 13) -+ | (token_rate->fraction)); -+ config_opts.shaper_config.crtbl = cpu_to_be16(token_limit); -+ config_opts.shaper_config.cpl = query_result.shaper_query.cpl; -+ config_opts.shaper_config.oal = query_result.shaper_query.oal; -+ config_opts.shaper_config.ertcr = query_result.shaper_query.ertcr; -+ config_opts.shaper_config.ertbl = query_result.shaper_query.ertbl; -+ config_opts.shaper_config.mps = query_result.shaper_query.mps; -+ return qman_ceetm_configure_mapping_shaper_tcfc(&config_opts); -+} -+EXPORT_SYMBOL(qman_ceetm_lni_set_commit_rate); -+ -+int qman_ceetm_lni_set_commit_rate_bps(struct qm_ceetm_lni *lni, -+ u64 bps, -+ u16 token_limit) -+{ -+ struct qm_ceetm_rate token_rate; -+ int ret; -+ -+ ret = qman_ceetm_bps2tokenrate(bps, &token_rate, 0); -+ if (ret) { -+ pr_err("Can not convert bps to token rate\n"); -+ return -EINVAL; -+ } -+ -+ return qman_ceetm_lni_set_commit_rate(lni, &token_rate, token_limit); -+} -+EXPORT_SYMBOL(qman_ceetm_lni_set_commit_rate_bps); -+ -+int qman_ceetm_lni_get_commit_rate(struct qm_ceetm_lni *lni, -+ struct qm_ceetm_rate *token_rate, -+ u16 *token_limit) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ int ret; -+ -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_LNI_SHAPER | lni->idx); -+ query_opts.dcpid = lni->dcp_idx; -+ -+ ret = qman_ceetm_query_mapping_shaper_tcfc(&query_opts, &query_result); -+ if (ret) { -+ pr_err("The LNI CR rate or limit is not set\n"); -+ return -EINVAL; -+ } -+ token_rate->whole = be24_to_cpu(query_result.shaper_query.crtcr) >> 13; -+ token_rate->fraction = be24_to_cpu(query_result.shaper_query.crtcr) & -+ 0x1FFF; -+ *token_limit = be16_to_cpu(query_result.shaper_query.crtbl); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_lni_get_commit_rate); -+ -+int qman_ceetm_lni_get_commit_rate_bps(struct qm_ceetm_lni *lni, -+ u64 *bps, u16 *token_limit) -+{ -+ struct qm_ceetm_rate token_rate; -+ int ret; -+ -+ ret = qman_ceetm_lni_get_commit_rate(lni, &token_rate, token_limit); -+ if (ret) { -+ pr_err("The LNI CR rate or limit is not available\n"); -+ return -EINVAL; -+ } -+ -+ return qman_ceetm_tokenrate2bps(&token_rate, bps, 0); -+} -+EXPORT_SYMBOL(qman_ceetm_lni_get_commit_rate_bps); -+ -+int qman_ceetm_lni_set_excess_rate(struct qm_ceetm_lni *lni, -+ const struct qm_ceetm_rate *token_rate, -+ u16 token_limit) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ int ret; -+ -+ lni->er_token_rate.whole = token_rate->whole; -+ lni->er_token_rate.fraction = token_rate->fraction; -+ lni->er_token_bucket_limit = token_limit; -+ if (!lni->shaper_enable) -+ return 0; -+ -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_LNI_SHAPER | lni->idx); -+ query_opts.dcpid = lni->dcp_idx; -+ ret = qman_ceetm_query_mapping_shaper_tcfc(&query_opts, -+ &query_result); -+ if (ret) { -+ pr_err("Fail to get current LNI shaper setting\n"); -+ return -EINVAL; -+ } -+ -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_LNI_SHAPER | lni->idx); -+ config_opts.dcpid = lni->dcp_idx; -+ config_opts.shaper_config.ertcr = cpu_to_be24( -+ (token_rate->whole << 13) | (token_rate->fraction)); -+ config_opts.shaper_config.ertbl = cpu_to_be16(token_limit); -+ config_opts.shaper_config.cpl = query_result.shaper_query.cpl; -+ config_opts.shaper_config.oal = query_result.shaper_query.oal; -+ config_opts.shaper_config.crtcr = query_result.shaper_query.crtcr; -+ config_opts.shaper_config.crtbl = query_result.shaper_query.crtbl; -+ config_opts.shaper_config.mps = query_result.shaper_query.mps; -+ return qman_ceetm_configure_mapping_shaper_tcfc(&config_opts); -+} -+EXPORT_SYMBOL(qman_ceetm_lni_set_excess_rate); -+ -+int qman_ceetm_lni_set_excess_rate_bps(struct qm_ceetm_lni *lni, -+ u64 bps, -+ u16 token_limit) -+{ -+ struct qm_ceetm_rate token_rate; -+ int ret; -+ -+ ret = qman_ceetm_bps2tokenrate(bps, &token_rate, 0); -+ if (ret) { -+ pr_err("Can not convert bps to token rate\n"); -+ return -EINVAL; -+ } -+ return qman_ceetm_lni_set_excess_rate(lni, &token_rate, token_limit); -+} -+EXPORT_SYMBOL(qman_ceetm_lni_set_excess_rate_bps); -+ -+int qman_ceetm_lni_get_excess_rate(struct qm_ceetm_lni *lni, -+ struct qm_ceetm_rate *token_rate, -+ u16 *token_limit) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ int ret; -+ -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_LNI_SHAPER | lni->idx); -+ query_opts.dcpid = lni->dcp_idx; -+ ret = qman_ceetm_query_mapping_shaper_tcfc(&query_opts, &query_result); -+ if (ret) { -+ pr_err("The LNI ER rate or limit is not set\n"); -+ return -EINVAL; -+ } -+ token_rate->whole = be24_to_cpu(query_result.shaper_query.ertcr) >> 13; -+ token_rate->fraction = be24_to_cpu(query_result.shaper_query.ertcr) & -+ 0x1FFF; -+ *token_limit = be16_to_cpu(query_result.shaper_query.ertbl); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_lni_get_excess_rate); -+ -+int qman_ceetm_lni_get_excess_rate_bps(struct qm_ceetm_lni *lni, -+ u64 *bps, u16 *token_limit) -+{ -+ struct qm_ceetm_rate token_rate; -+ int ret; -+ -+ ret = qman_ceetm_lni_get_excess_rate(lni, &token_rate, token_limit); -+ if (ret) { -+ pr_err("The LNI ER rate or limit is not available\n"); -+ return -EINVAL; -+ } -+ -+ return qman_ceetm_tokenrate2bps(&token_rate, bps, 0); -+} -+EXPORT_SYMBOL(qman_ceetm_lni_get_excess_rate_bps); -+ -+#define QMAN_CEETM_LNITCFCC_CQ_LEVEL_SHIFT(n) ((15 - n) * 4) -+#define QMAN_CEETM_LNITCFCC_ENABLE 0x8 -+int qman_ceetm_lni_set_tcfcc(struct qm_ceetm_lni *lni, -+ unsigned int cq_level, -+ int traffic_class) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ u64 lnitcfcc; -+ -+ if ((cq_level > 15) | (traffic_class > 7)) { -+ pr_err("The CQ or traffic class id is out of range\n"); -+ return -EINVAL; -+ } -+ -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_TCFC | lni->idx); -+ query_opts.dcpid = lni->dcp_idx; -+ if (qman_ceetm_query_mapping_shaper_tcfc(&query_opts, &query_result)) { -+ pr_err("Fail to query tcfcc\n"); -+ return -EINVAL; -+ } -+ -+ lnitcfcc = be64_to_cpu(query_result.tcfc_query.lnitcfcc); -+ if (traffic_class == -1) { -+ /* disable tcfc for this CQ */ -+ lnitcfcc &= ~((u64)QMAN_CEETM_LNITCFCC_ENABLE << -+ QMAN_CEETM_LNITCFCC_CQ_LEVEL_SHIFT(cq_level)); -+ } else { -+ lnitcfcc &= ~((u64)0xF << -+ QMAN_CEETM_LNITCFCC_CQ_LEVEL_SHIFT(cq_level)); -+ lnitcfcc |= ((u64)(QMAN_CEETM_LNITCFCC_ENABLE | -+ traffic_class)) << -+ QMAN_CEETM_LNITCFCC_CQ_LEVEL_SHIFT(cq_level); -+ } -+ config_opts.tcfc_config.lnitcfcc = cpu_to_be64(lnitcfcc); -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_TCFC | lni->idx); -+ config_opts.dcpid = lni->dcp_idx; -+ return qman_ceetm_configure_mapping_shaper_tcfc(&config_opts); -+} -+EXPORT_SYMBOL(qman_ceetm_lni_set_tcfcc); -+ -+#define QMAN_CEETM_LNITCFCC_TC_MASK 0x7 -+int qman_ceetm_lni_get_tcfcc(struct qm_ceetm_lni *lni, unsigned int cq_level, -+ int *traffic_class) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ int ret; -+ u8 lnitcfcc; -+ -+ if (cq_level > 15) { -+ pr_err("the CQ level is out of range\n"); -+ return -EINVAL; -+ } -+ -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_TCFC | lni->idx); -+ query_opts.dcpid = lni->dcp_idx; -+ ret = qman_ceetm_query_mapping_shaper_tcfc(&query_opts, &query_result); -+ if (ret) -+ return ret; -+ lnitcfcc = (u8)be64_to_cpu((query_result.tcfc_query.lnitcfcc) >> -+ QMAN_CEETM_LNITCFCC_CQ_LEVEL_SHIFT(cq_level)); -+ if (lnitcfcc & QMAN_CEETM_LNITCFCC_ENABLE) -+ *traffic_class = lnitcfcc & QMAN_CEETM_LNITCFCC_TC_MASK; -+ else -+ *traffic_class = -1; -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_lni_get_tcfcc); -+ -+int qman_ceetm_channel_claim(struct qm_ceetm_channel **channel, -+ struct qm_ceetm_lni *lni) -+{ -+ struct qm_ceetm_channel *p; -+ u32 channel_idx; -+ int ret = 0; -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ -+ if (lni->dcp_idx == qm_dc_portal_fman0) { -+ ret = qman_alloc_ceetm0_channel(&channel_idx); -+ } else if (lni->dcp_idx == qm_dc_portal_fman1) { -+ ret = qman_alloc_ceetm1_channel(&channel_idx); -+ } else { -+ pr_err("dcp_idx %u does not correspond to a known fman in this driver\n", -+ lni->dcp_idx); -+ return -EINVAL; -+ } -+ -+ if (ret) { -+ pr_err("The is no channel available for LNI#%d\n", lni->idx); -+ return -ENODEV; -+ } -+ -+ p = kzalloc(sizeof(*p), GFP_KERNEL); -+ if (!p) -+ return -ENOMEM; -+ p->idx = channel_idx; -+ p->dcp_idx = lni->dcp_idx; -+ list_add_tail(&p->node, &lni->channels); -+ INIT_LIST_HEAD(&p->class_queues); -+ INIT_LIST_HEAD(&p->ccgs); -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_MAPPING | -+ channel_idx); -+ config_opts.dcpid = lni->dcp_idx; -+ config_opts.channel_mapping.map_lni_id = lni->idx; -+ config_opts.channel_mapping.map_shaped = 0; -+ if (qman_ceetm_configure_mapping_shaper_tcfc(&config_opts)) { -+ pr_err("Can't map channel#%d for LNI#%d\n", -+ channel_idx, lni->idx); -+ return -EINVAL; -+ } -+ *channel = p; -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_channel_claim); -+ -+int qman_ceetm_channel_release(struct qm_ceetm_channel *channel) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ if (!list_empty(&channel->class_queues)) { -+ pr_err("CEETM channel#%d has class queue unreleased!\n", -+ channel->idx); -+ return -EBUSY; -+ } -+ if (!list_empty(&channel->ccgs)) { -+ pr_err("CEETM channel#%d has ccg unreleased!\n", -+ channel->idx); -+ return -EBUSY; -+ } -+ -+ /* channel->dcp_idx corresponds to known fman validation */ -+ if ((channel->dcp_idx != qm_dc_portal_fman0) && -+ (channel->dcp_idx != qm_dc_portal_fman1)) { -+ pr_err("dcp_idx %u does not correspond to a known fman in this driver\n", -+ channel->dcp_idx); -+ return -EINVAL; -+ } -+ -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_SHAPER | -+ channel->idx); -+ config_opts.dcpid = channel->dcp_idx; -+ memset(&config_opts.shaper_config, 0, -+ sizeof(config_opts.shaper_config)); -+ if (qman_ceetm_configure_mapping_shaper_tcfc(&config_opts)) { -+ pr_err("Can't reset channel shapping parameters\n"); -+ return -EINVAL; -+ } -+ -+ if (channel->dcp_idx == qm_dc_portal_fman0) { -+ qman_release_ceetm0_channelid(channel->idx); -+ } else if (channel->dcp_idx == qm_dc_portal_fman1) { -+ qman_release_ceetm1_channelid(channel->idx); -+ } else { -+ pr_err("dcp_idx %u does not correspond to a known fman in this driver\n", -+ channel->dcp_idx); -+ return -EINVAL; -+ } -+ list_del(&channel->node); -+ kfree(channel); -+ -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_channel_release); -+ -+int qman_ceetm_channel_enable_shaper(struct qm_ceetm_channel *channel, -+ int coupled) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ -+ if (channel->shaper_enable == 1) { -+ pr_err("This channel shaper has been enabled!\n"); -+ return -EINVAL; -+ } -+ -+ channel->shaper_enable = 1; -+ channel->shaper_couple = coupled; -+ -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_MAPPING | -+ channel->idx); -+ query_opts.dcpid = (u8)channel->dcp_idx; -+ -+ if (qman_ceetm_query_mapping_shaper_tcfc(&query_opts, &query_result)) { -+ pr_err("Can't query channel mapping\n"); -+ return -EINVAL; -+ } -+ -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_MAPPING | -+ channel->idx); -+ config_opts.dcpid = channel->dcp_idx; -+ config_opts.channel_mapping.map_lni_id = -+ query_result.channel_mapping_query.map_lni_id; -+ config_opts.channel_mapping.map_shaped = 1; -+ if (qman_ceetm_configure_mapping_shaper_tcfc(&config_opts)) { -+ pr_err("Can't enable shaper for channel #%d\n", channel->idx); -+ return -EINVAL; -+ } -+ -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_SHAPER | -+ channel->idx); -+ config_opts.shaper_config.cpl = coupled; -+ config_opts.shaper_config.crtcr = cpu_to_be24((channel->cr_token_rate. -+ whole << 13) | -+ channel->cr_token_rate.fraction); -+ config_opts.shaper_config.ertcr = cpu_to_be24((channel->er_token_rate. -+ whole << 13) | -+ channel->er_token_rate.fraction); -+ config_opts.shaper_config.crtbl = -+ cpu_to_be16(channel->cr_token_bucket_limit); -+ config_opts.shaper_config.ertbl = -+ cpu_to_be16(channel->er_token_bucket_limit); -+ return qman_ceetm_configure_mapping_shaper_tcfc(&config_opts); -+} -+EXPORT_SYMBOL(qman_ceetm_channel_enable_shaper); -+ -+int qman_ceetm_channel_disable_shaper(struct qm_ceetm_channel *channel) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ -+ -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_MAPPING | -+ channel->idx); -+ query_opts.dcpid = channel->dcp_idx; -+ -+ if (qman_ceetm_query_mapping_shaper_tcfc(&query_opts, &query_result)) { -+ pr_err("Can't query channel mapping\n"); -+ return -EINVAL; -+ } -+ -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_MAPPING | -+ channel->idx); -+ config_opts.dcpid = channel->dcp_idx; -+ config_opts.channel_mapping.map_shaped = 0; -+ config_opts.channel_mapping.map_lni_id = -+ query_result.channel_mapping_query.map_lni_id; -+ -+ return qman_ceetm_configure_mapping_shaper_tcfc(&config_opts); -+} -+EXPORT_SYMBOL(qman_ceetm_channel_disable_shaper); -+ -+int qman_ceetm_channel_is_shaper_enabled(struct qm_ceetm_channel *channel) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ -+ query_opts.cid = CEETM_COMMAND_CHANNEL_MAPPING | channel->idx; -+ query_opts.dcpid = channel->dcp_idx; -+ -+ if (qman_ceetm_query_mapping_shaper_tcfc(&query_opts, &query_result)) { -+ pr_err("Can't query channel mapping\n"); -+ return -EINVAL; -+ } -+ -+ return query_result.channel_mapping_query.map_shaped; -+} -+EXPORT_SYMBOL(qman_ceetm_channel_is_shaper_enabled); -+ -+int qman_ceetm_channel_set_commit_rate(struct qm_ceetm_channel *channel, -+ const struct qm_ceetm_rate *token_rate, -+ u16 token_limit) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ int ret; -+ -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_SHAPER | -+ channel->idx); -+ query_opts.dcpid = channel->dcp_idx; -+ -+ ret = qman_ceetm_query_mapping_shaper_tcfc(&query_opts, &query_result); -+ if (ret) { -+ pr_err("Fail to get the current channel shaper setting\n"); -+ return -EINVAL; -+ } -+ -+ channel->cr_token_rate.whole = token_rate->whole; -+ channel->cr_token_rate.fraction = token_rate->fraction; -+ channel->cr_token_bucket_limit = token_limit; -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_SHAPER | -+ channel->idx); -+ config_opts.dcpid = channel->dcp_idx; -+ config_opts.shaper_config.crtcr = cpu_to_be24((token_rate->whole -+ << 13) | (token_rate->fraction)); -+ config_opts.shaper_config.crtbl = cpu_to_be16(token_limit); -+ config_opts.shaper_config.cpl = query_result.shaper_query.cpl; -+ config_opts.shaper_config.ertcr = query_result.shaper_query.ertcr; -+ config_opts.shaper_config.ertbl = query_result.shaper_query.ertbl; -+ return qman_ceetm_configure_mapping_shaper_tcfc(&config_opts); -+} -+EXPORT_SYMBOL(qman_ceetm_channel_set_commit_rate); -+ -+int qman_ceetm_channel_set_commit_rate_bps(struct qm_ceetm_channel *channel, -+ u64 bps, u16 token_limit) -+{ -+ struct qm_ceetm_rate token_rate; -+ int ret; -+ -+ ret = qman_ceetm_bps2tokenrate(bps, &token_rate, 0); -+ if (ret) { -+ pr_err("Can not convert bps to token rate\n"); -+ return -EINVAL; -+ } -+ return qman_ceetm_channel_set_commit_rate(channel, &token_rate, -+ token_limit); -+} -+EXPORT_SYMBOL(qman_ceetm_channel_set_commit_rate_bps); -+ -+int qman_ceetm_channel_get_commit_rate(struct qm_ceetm_channel *channel, -+ struct qm_ceetm_rate *token_rate, -+ u16 *token_limit) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ int ret; -+ -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_SHAPER | -+ channel->idx); -+ query_opts.dcpid = channel->dcp_idx; -+ -+ ret = qman_ceetm_query_mapping_shaper_tcfc(&query_opts, &query_result); -+ if (ret | !query_result.shaper_query.crtcr | -+ !query_result.shaper_query.crtbl) { -+ pr_err("The channel commit rate or limit is not set\n"); -+ return -EINVAL; -+ } -+ token_rate->whole = be24_to_cpu(query_result.shaper_query.crtcr) >> 13; -+ token_rate->fraction = be24_to_cpu(query_result.shaper_query.crtcr) & -+ 0x1FFF; -+ *token_limit = be16_to_cpu(query_result.shaper_query.crtbl); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_channel_get_commit_rate); -+ -+int qman_ceetm_channel_get_commit_rate_bps(struct qm_ceetm_channel *channel, -+ u64 *bps, u16 *token_limit) -+{ -+ struct qm_ceetm_rate token_rate; -+ int ret; -+ -+ ret = qman_ceetm_channel_get_commit_rate(channel, &token_rate, -+ token_limit); -+ if (ret) { -+ pr_err("The channel CR rate or limit is not available\n"); -+ return -EINVAL; -+ } -+ -+ return qman_ceetm_tokenrate2bps(&token_rate, bps, 0); -+} -+EXPORT_SYMBOL(qman_ceetm_channel_get_commit_rate_bps); -+ -+int qman_ceetm_channel_set_excess_rate(struct qm_ceetm_channel *channel, -+ const struct qm_ceetm_rate *token_rate, -+ u16 token_limit) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ int ret; -+ -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_SHAPER | -+ channel->idx); -+ query_opts.dcpid = channel->dcp_idx; -+ ret = qman_ceetm_query_mapping_shaper_tcfc(&query_opts, &query_result); -+ if (ret) { -+ pr_err("Fail to get the current channel shaper setting\n"); -+ return -EINVAL; -+ } -+ -+ channel->er_token_rate.whole = token_rate->whole; -+ channel->er_token_rate.fraction = token_rate->fraction; -+ channel->er_token_bucket_limit = token_limit; -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_SHAPER | -+ channel->idx); -+ config_opts.dcpid = channel->dcp_idx; -+ config_opts.shaper_config.ertcr = cpu_to_be24( -+ (token_rate->whole << 13) | (token_rate->fraction)); -+ config_opts.shaper_config.ertbl = cpu_to_be16(token_limit); -+ config_opts.shaper_config.cpl = query_result.shaper_query.cpl; -+ config_opts.shaper_config.crtcr = query_result.shaper_query.crtcr; -+ config_opts.shaper_config.crtbl = query_result.shaper_query.crtbl; -+ return qman_ceetm_configure_mapping_shaper_tcfc(&config_opts); -+} -+EXPORT_SYMBOL(qman_ceetm_channel_set_excess_rate); -+ -+int qman_ceetm_channel_set_excess_rate_bps(struct qm_ceetm_channel *channel, -+ u64 bps, u16 token_limit) -+{ -+ struct qm_ceetm_rate token_rate; -+ int ret; -+ -+ ret = qman_ceetm_bps2tokenrate(bps, &token_rate, 0); -+ if (ret) { -+ pr_err("Can not convert bps to token rate\n"); -+ return -EINVAL; -+ } -+ return qman_ceetm_channel_set_excess_rate(channel, &token_rate, -+ token_limit); -+} -+EXPORT_SYMBOL(qman_ceetm_channel_set_excess_rate_bps); -+ -+int qman_ceetm_channel_get_excess_rate(struct qm_ceetm_channel *channel, -+ struct qm_ceetm_rate *token_rate, -+ u16 *token_limit) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ int ret; -+ -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_SHAPER | -+ channel->idx); -+ query_opts.dcpid = channel->dcp_idx; -+ ret = qman_ceetm_query_mapping_shaper_tcfc(&query_opts, &query_result); -+ if (ret | !query_result.shaper_query.ertcr | -+ !query_result.shaper_query.ertbl) { -+ pr_err("The channel excess rate or limit is not set\n"); -+ return -EINVAL; -+ } -+ token_rate->whole = be24_to_cpu(query_result.shaper_query.ertcr) >> 13; -+ token_rate->fraction = be24_to_cpu(query_result.shaper_query.ertcr) & -+ 0x1FFF; -+ *token_limit = be16_to_cpu(query_result.shaper_query.ertbl); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_channel_get_excess_rate); -+ -+int qman_ceetm_channel_get_excess_rate_bps(struct qm_ceetm_channel *channel, -+ u64 *bps, u16 *token_limit) -+{ -+ struct qm_ceetm_rate token_rate; -+ int ret; -+ -+ ret = qman_ceetm_channel_get_excess_rate(channel, &token_rate, -+ token_limit); -+ if (ret) { -+ pr_err("The channel ER rate or limit is not available\n"); -+ return -EINVAL; -+ } -+ -+ return qman_ceetm_tokenrate2bps(&token_rate, bps, 0); -+} -+EXPORT_SYMBOL(qman_ceetm_channel_get_excess_rate_bps); -+ -+int qman_ceetm_channel_set_weight(struct qm_ceetm_channel *channel, -+ u16 token_limit) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config config_opts; -+ -+ if (channel->shaper_enable) { -+ pr_err("This channel is a shaped one\n"); -+ return -EINVAL; -+ } -+ -+ channel->cr_token_bucket_limit = token_limit; -+ config_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_SHAPER | -+ channel->idx); -+ config_opts.dcpid = channel->dcp_idx; -+ config_opts.shaper_config.crtbl = cpu_to_be16(token_limit); -+ return qman_ceetm_configure_mapping_shaper_tcfc(&config_opts); -+} -+EXPORT_SYMBOL(qman_ceetm_channel_set_weight); -+ -+int qman_ceetm_channel_get_weight(struct qm_ceetm_channel *channel, -+ u16 *token_limit) -+{ -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query query_opts; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query query_result; -+ int ret; -+ -+ query_opts.cid = cpu_to_be16(CEETM_COMMAND_CHANNEL_SHAPER | -+ channel->idx); -+ query_opts.dcpid = channel->dcp_idx; -+ ret = qman_ceetm_query_mapping_shaper_tcfc(&query_opts, &query_result); -+ if (ret | !query_result.shaper_query.crtbl) { -+ pr_err("This unshaped channel's uFQ wight is unavailable\n"); -+ return -EINVAL; -+ } -+ *token_limit = be16_to_cpu(query_result.shaper_query.crtbl); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_channel_get_weight); -+ -+int qman_ceetm_channel_set_group(struct qm_ceetm_channel *channel, int group_b, -+ unsigned int prio_a, unsigned int prio_b) -+{ -+ struct qm_mcc_ceetm_class_scheduler_config config_opts; -+ struct qm_mcr_ceetm_class_scheduler_query query_result; -+ int i; -+ -+ if (prio_a > 7) { -+ pr_err("The priority of group A is out of range\n"); -+ return -EINVAL; -+ } -+ if (group_b && (prio_b > 7)) { -+ pr_err("The priority of group B is out of range\n"); -+ return -EINVAL; -+ } -+ -+ if (qman_ceetm_query_class_scheduler(channel, &query_result)) { -+ pr_err("Can't query channel#%d's scheduler!\n", channel->idx); -+ return -EINVAL; -+ } -+ -+ config_opts.cqcid = cpu_to_be16(channel->idx); -+ config_opts.dcpid = channel->dcp_idx; -+ config_opts.gpc_combine_flag = !group_b; -+ config_opts.gpc_prio_a = prio_a; -+ config_opts.gpc_prio_b = prio_b; -+ -+ for (i = 0; i < 8; i++) -+ config_opts.w[i] = query_result.w[i]; -+ config_opts.crem = query_result.crem; -+ config_opts.erem = query_result.erem; -+ -+ return qman_ceetm_configure_class_scheduler(&config_opts); -+} -+EXPORT_SYMBOL(qman_ceetm_channel_set_group); -+ -+int qman_ceetm_channel_get_group(struct qm_ceetm_channel *channel, int *group_b, -+ unsigned int *prio_a, unsigned int *prio_b) -+{ -+ struct qm_mcr_ceetm_class_scheduler_query query_result; -+ -+ if (qman_ceetm_query_class_scheduler(channel, &query_result)) { -+ pr_err("Can't query channel#%d's scheduler!\n", channel->idx); -+ return -EINVAL; -+ } -+ *group_b = !query_result.gpc_combine_flag; -+ *prio_a = query_result.gpc_prio_a; -+ *prio_b = query_result.gpc_prio_b; -+ -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_channel_get_group); -+ -+#define GROUP_A_ELIGIBILITY_SET (1 << 8) -+#define GROUP_B_ELIGIBILITY_SET (1 << 9) -+#define CQ_ELIGIBILITY_SET(n) (1 << (7 - n)) -+int qman_ceetm_channel_set_group_cr_eligibility(struct qm_ceetm_channel -+ *channel, int group_b, int cre) -+{ -+ struct qm_mcc_ceetm_class_scheduler_config csch_config; -+ struct qm_mcr_ceetm_class_scheduler_query csch_query; -+ int i; -+ -+ if (qman_ceetm_query_class_scheduler(channel, &csch_query)) { -+ pr_err("Cannot get the channel %d scheduler setting.\n", -+ channel->idx); -+ return -EINVAL; -+ } -+ csch_config.cqcid = cpu_to_be16(channel->idx); -+ csch_config.dcpid = channel->dcp_idx; -+ csch_config.gpc_combine_flag = csch_query.gpc_combine_flag; -+ csch_config.gpc_prio_a = csch_query.gpc_prio_a; -+ csch_config.gpc_prio_b = csch_query.gpc_prio_b; -+ -+ for (i = 0; i < 8; i++) -+ csch_config.w[i] = csch_query.w[i]; -+ csch_config.erem = csch_query.erem; -+ if (group_b) -+ csch_config.crem = (be16_to_cpu(csch_query.crem) -+ & ~GROUP_B_ELIGIBILITY_SET) -+ | (cre ? GROUP_B_ELIGIBILITY_SET : 0); -+ else -+ csch_config.crem = (be16_to_cpu(csch_query.crem) -+ & ~GROUP_A_ELIGIBILITY_SET) -+ | (cre ? GROUP_A_ELIGIBILITY_SET : 0); -+ -+ csch_config.crem = cpu_to_be16(csch_config.crem); -+ -+ if (qman_ceetm_configure_class_scheduler(&csch_config)) { -+ pr_err("Cannot config channel %d's scheduler with " -+ "group_%c's cr eligibility\n", channel->idx, -+ group_b ? 'b' : 'a'); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_channel_set_group_cr_eligibility); -+ -+int qman_ceetm_channel_set_group_er_eligibility(struct qm_ceetm_channel -+ *channel, int group_b, int ere) -+{ -+ struct qm_mcc_ceetm_class_scheduler_config csch_config; -+ struct qm_mcr_ceetm_class_scheduler_query csch_query; -+ int i; -+ -+ if (qman_ceetm_query_class_scheduler(channel, &csch_query)) { -+ pr_err("Cannot get the channel %d scheduler setting.\n", -+ channel->idx); -+ return -EINVAL; -+ } -+ csch_config.cqcid = cpu_to_be16(channel->idx); -+ csch_config.dcpid = channel->dcp_idx; -+ csch_config.gpc_combine_flag = csch_query.gpc_combine_flag; -+ csch_config.gpc_prio_a = csch_query.gpc_prio_a; -+ csch_config.gpc_prio_b = csch_query.gpc_prio_b; -+ -+ for (i = 0; i < 8; i++) -+ csch_config.w[i] = csch_query.w[i]; -+ csch_config.crem = csch_query.crem; -+ if (group_b) -+ csch_config.erem = (be16_to_cpu(csch_query.erem) -+ & ~GROUP_B_ELIGIBILITY_SET) -+ | (ere ? GROUP_B_ELIGIBILITY_SET : 0); -+ else -+ csch_config.erem = (be16_to_cpu(csch_query.erem) -+ & ~GROUP_A_ELIGIBILITY_SET) -+ | (ere ? GROUP_A_ELIGIBILITY_SET : 0); -+ -+ csch_config.erem = cpu_to_be16(csch_config.erem); -+ -+ if (qman_ceetm_configure_class_scheduler(&csch_config)) { -+ pr_err("Cannot config channel %d's scheduler with " -+ "group_%c's er eligibility\n", channel->idx, -+ group_b ? 'b' : 'a'); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_channel_set_group_er_eligibility); -+ -+int qman_ceetm_channel_set_cq_cr_eligibility(struct qm_ceetm_channel *channel, -+ unsigned int idx, int cre) -+{ -+ struct qm_mcc_ceetm_class_scheduler_config csch_config; -+ struct qm_mcr_ceetm_class_scheduler_query csch_query; -+ int i; -+ -+ if (idx > 7) { -+ pr_err("CQ index is out of range\n"); -+ return -EINVAL; -+ } -+ if (qman_ceetm_query_class_scheduler(channel, &csch_query)) { -+ pr_err("Cannot get the channel %d scheduler setting.\n", -+ channel->idx); -+ return -EINVAL; -+ } -+ csch_config.cqcid = cpu_to_be16(channel->idx); -+ csch_config.dcpid = channel->dcp_idx; -+ csch_config.gpc_combine_flag = csch_query.gpc_combine_flag; -+ csch_config.gpc_prio_a = csch_query.gpc_prio_a; -+ csch_config.gpc_prio_b = csch_query.gpc_prio_b; -+ for (i = 0; i < 8; i++) -+ csch_config.w[i] = csch_query.w[i]; -+ csch_config.erem = csch_query.erem; -+ csch_config.crem = (be16_to_cpu(csch_query.crem) -+ & ~CQ_ELIGIBILITY_SET(idx)) | -+ (cre ? CQ_ELIGIBILITY_SET(idx) : 0); -+ csch_config.crem = cpu_to_be16(csch_config.crem); -+ if (qman_ceetm_configure_class_scheduler(&csch_config)) { -+ pr_err("Cannot config channel scheduler to set " -+ "cr eligibility mask for CQ#%d\n", idx); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_channel_set_cq_cr_eligibility); -+ -+int qman_ceetm_channel_set_cq_er_eligibility(struct qm_ceetm_channel *channel, -+ unsigned int idx, int ere) -+{ -+ struct qm_mcc_ceetm_class_scheduler_config csch_config; -+ struct qm_mcr_ceetm_class_scheduler_query csch_query; -+ int i; -+ -+ if (idx > 7) { -+ pr_err("CQ index is out of range\n"); -+ return -EINVAL; -+ } -+ if (qman_ceetm_query_class_scheduler(channel, &csch_query)) { -+ pr_err("Cannot get the channel %d scheduler setting.\n", -+ channel->idx); -+ return -EINVAL; -+ } -+ csch_config.cqcid = cpu_to_be16(channel->idx); -+ csch_config.dcpid = channel->dcp_idx; -+ csch_config.gpc_combine_flag = csch_query.gpc_combine_flag; -+ csch_config.gpc_prio_a = csch_query.gpc_prio_a; -+ csch_config.gpc_prio_b = csch_query.gpc_prio_b; -+ for (i = 0; i < 8; i++) -+ csch_config.w[i] = csch_query.w[i]; -+ csch_config.crem = csch_query.crem; -+ csch_config.erem = (be16_to_cpu(csch_query.erem) -+ & ~CQ_ELIGIBILITY_SET(idx)) | -+ (ere ? CQ_ELIGIBILITY_SET(idx) : 0); -+ csch_config.erem = cpu_to_be16(csch_config.erem); -+ if (qman_ceetm_configure_class_scheduler(&csch_config)) { -+ pr_err("Cannot config channel scheduler to set " -+ "er eligibility mask for CQ#%d\n", idx); -+ return -EINVAL; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_channel_set_cq_er_eligibility); -+ -+int qman_ceetm_cq_claim(struct qm_ceetm_cq **cq, -+ struct qm_ceetm_channel *channel, unsigned int idx, -+ struct qm_ceetm_ccg *ccg) -+{ -+ struct qm_ceetm_cq *p; -+ struct qm_mcc_ceetm_cq_config cq_config; -+ -+ if (idx > 7) { -+ pr_err("The independent class queue id is out of range\n"); -+ return -EINVAL; -+ } -+ -+ list_for_each_entry(p, &channel->class_queues, node) { -+ if (p->idx == idx) { -+ pr_err("The CQ#%d has been claimed!\n", idx); -+ return -EINVAL; -+ } -+ } -+ -+ p = kmalloc(sizeof(*p), GFP_KERNEL); -+ if (!p) { -+ pr_err("Can't allocate memory for CQ#%d!\n", idx); -+ return -ENOMEM; -+ } -+ -+ list_add_tail(&p->node, &channel->class_queues); -+ p->idx = idx; -+ p->is_claimed = 1; -+ p->parent = channel; -+ INIT_LIST_HEAD(&p->bound_lfqids); -+ -+ if (ccg) { -+ cq_config.cqid = cpu_to_be16((channel->idx << 4) | idx); -+ cq_config.dcpid = channel->dcp_idx; -+ cq_config.ccgid = cpu_to_be16(ccg->idx); -+ if (qman_ceetm_configure_cq(&cq_config)) { -+ pr_err("Can't configure the CQ#%d with CCGRID#%d\n", -+ idx, ccg->idx); -+ list_del(&p->node); -+ kfree(p); -+ return -EINVAL; -+ } -+ } -+ -+ *cq = p; -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_cq_claim); -+ -+int qman_ceetm_cq_claim_A(struct qm_ceetm_cq **cq, -+ struct qm_ceetm_channel *channel, unsigned int idx, -+ struct qm_ceetm_ccg *ccg) -+{ -+ struct qm_ceetm_cq *p; -+ struct qm_mcc_ceetm_cq_config cq_config; -+ -+ if ((idx < 8) || (idx > 15)) { -+ pr_err("This grouped class queue id is out of range\n"); -+ return -EINVAL; -+ } -+ -+ list_for_each_entry(p, &channel->class_queues, node) { -+ if (p->idx == idx) { -+ pr_err("The CQ#%d has been claimed!\n", idx); -+ return -EINVAL; -+ } -+ } -+ -+ p = kmalloc(sizeof(*p), GFP_KERNEL); -+ if (!p) { -+ pr_err("Can't allocate memory for CQ#%d!\n", idx); -+ return -ENOMEM; -+ } -+ -+ list_add_tail(&p->node, &channel->class_queues); -+ p->idx = idx; -+ p->is_claimed = 1; -+ p->parent = channel; -+ INIT_LIST_HEAD(&p->bound_lfqids); -+ -+ if (ccg) { -+ cq_config.cqid = cpu_to_be16((channel->idx << 4) | idx); -+ cq_config.dcpid = channel->dcp_idx; -+ cq_config.ccgid = cpu_to_be16(ccg->idx); -+ if (qman_ceetm_configure_cq(&cq_config)) { -+ pr_err("Can't configure the CQ#%d with CCGRID#%d\n", -+ idx, ccg->idx); -+ list_del(&p->node); -+ kfree(p); -+ return -EINVAL; -+ } -+ } -+ *cq = p; -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_cq_claim_A); -+ -+int qman_ceetm_cq_claim_B(struct qm_ceetm_cq **cq, -+ struct qm_ceetm_channel *channel, unsigned int idx, -+ struct qm_ceetm_ccg *ccg) -+{ -+ struct qm_ceetm_cq *p; -+ struct qm_mcc_ceetm_cq_config cq_config; -+ -+ if ((idx < 12) || (idx > 15)) { -+ pr_err("This grouped class queue id is out of range\n"); -+ return -EINVAL; -+ } -+ -+ list_for_each_entry(p, &channel->class_queues, node) { -+ if (p->idx == idx) { -+ pr_err("The CQ#%d has been claimed!\n", idx); -+ return -EINVAL; -+ } -+ } -+ -+ p = kmalloc(sizeof(*p), GFP_KERNEL); -+ if (!p) { -+ pr_err("Can't allocate memory for CQ#%d!\n", idx); -+ return -ENOMEM; -+ } -+ -+ list_add_tail(&p->node, &channel->class_queues); -+ p->idx = idx; -+ p->is_claimed = 1; -+ p->parent = channel; -+ INIT_LIST_HEAD(&p->bound_lfqids); -+ -+ if (ccg) { -+ cq_config.cqid = cpu_to_be16((channel->idx << 4) | idx); -+ cq_config.dcpid = channel->dcp_idx; -+ cq_config.ccgid = cpu_to_be16(ccg->idx); -+ if (qman_ceetm_configure_cq(&cq_config)) { -+ pr_err("Can't configure the CQ#%d with CCGRID#%d\n", -+ idx, ccg->idx); -+ list_del(&p->node); -+ kfree(p); -+ return -EINVAL; -+ } -+ } -+ *cq = p; -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_cq_claim_B); -+ -+int qman_ceetm_cq_release(struct qm_ceetm_cq *cq) -+{ -+ if (!list_empty(&cq->bound_lfqids)) { -+ pr_err("The CQ#%d has unreleased LFQID\n", cq->idx); -+ return -EBUSY; -+ } -+ list_del(&cq->node); -+ qman_ceetm_drain_cq(cq); -+ kfree(cq); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_cq_release); -+ -+int qman_ceetm_set_queue_weight(struct qm_ceetm_cq *cq, -+ struct qm_ceetm_weight_code *weight_code) -+{ -+ struct qm_mcc_ceetm_class_scheduler_config config_opts; -+ struct qm_mcr_ceetm_class_scheduler_query query_result; -+ int i; -+ -+ if (cq->idx < 8) { -+ pr_err("Can not set weight for ungrouped class queue\n"); -+ return -EINVAL; -+ } -+ -+ if (qman_ceetm_query_class_scheduler(cq->parent, &query_result)) { -+ pr_err("Can't query channel#%d's scheduler!\n", -+ cq->parent->idx); -+ return -EINVAL; -+ } -+ -+ config_opts.cqcid = cpu_to_be16(cq->parent->idx); -+ config_opts.dcpid = cq->parent->dcp_idx; -+ config_opts.crem = query_result.crem; -+ config_opts.erem = query_result.erem; -+ config_opts.gpc_combine_flag = query_result.gpc_combine_flag; -+ config_opts.gpc_prio_a = query_result.gpc_prio_a; -+ config_opts.gpc_prio_b = query_result.gpc_prio_b; -+ -+ for (i = 0; i < 8; i++) -+ config_opts.w[i] = query_result.w[i]; -+ config_opts.w[cq->idx - 8] = ((weight_code->y << 3) | -+ (weight_code->x & 0x7)); -+ return qman_ceetm_configure_class_scheduler(&config_opts); -+} -+EXPORT_SYMBOL(qman_ceetm_set_queue_weight); -+ -+int qman_ceetm_get_queue_weight(struct qm_ceetm_cq *cq, -+ struct qm_ceetm_weight_code *weight_code) -+{ -+ struct qm_mcr_ceetm_class_scheduler_query query_result; -+ -+ if (cq->idx < 8) { -+ pr_err("Can not get weight for ungrouped class queue\n"); -+ return -EINVAL; -+ } -+ -+ if (qman_ceetm_query_class_scheduler(cq->parent, -+ &query_result)) { -+ pr_err("Can't get the weight code for CQ#%d!\n", cq->idx); -+ return -EINVAL; -+ } -+ weight_code->y = query_result.w[cq->idx - 8] >> 3; -+ weight_code->x = query_result.w[cq->idx - 8] & 0x7; -+ -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_get_queue_weight); -+ -+/* The WBFS code is represent as {x,y}, the effect wieght can be calculated as: -+ * effective weight = 2^x / (1 - (y/64)) -+ * = 2^(x+6) / (64 - y) -+ */ -+static void reduce_fraction(u32 *n, u32 *d) -+{ -+ u32 factor = 2; -+ u32 lesser = (*n < *d) ? *n : *d; -+ /* If factor exceeds the square-root of the lesser of *n and *d, -+ * then there's no point continuing. Proof: if there was a factor -+ * bigger than the square root, that would imply there exists -+ * another factor smaller than the square-root with which it -+ * multiplies to give 'lesser' - but that's a contradiction -+ * because the other factor would have already been found and -+ * divided out. -+ */ -+ while ((factor * factor) <= lesser) { -+ /* If 'factor' is a factor of *n and *d, divide them both -+ * by 'factor' as many times as possible. -+ */ -+ while (!(*n % factor) && !(*d % factor)) { -+ *n /= factor; -+ *d /= factor; -+ lesser /= factor; -+ } -+ if (factor == 2) -+ factor = 3; -+ else -+ factor += 2; -+ } -+} -+ -+int qman_ceetm_wbfs2ratio(struct qm_ceetm_weight_code *weight_code, -+ u32 *numerator, -+ u32 *denominator) -+{ -+ *numerator = (u32) 1 << (weight_code->x + 6); -+ *denominator = 64 - weight_code->y; -+ reduce_fraction(numerator, denominator); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_wbfs2ratio); -+ -+/* For a given x, the weight is between 2^x (inclusive) and 2^(x+1) (exclusive). -+ * So find 'x' by range, and then estimate 'y' using: -+ * 64 - y = 2^(x + 6) / weight -+ * = 2^(x + 6) / (n/d) -+ * = d * 2^(x+6) / n -+ * y = 64 - (d * 2^(x+6) / n) -+ */ -+int qman_ceetm_ratio2wbfs(u32 numerator, -+ u32 denominator, -+ struct qm_ceetm_weight_code *weight_code, -+ int rounding) -+{ -+ unsigned int y, x = 0; -+ /* search incrementing 'x' until: -+ * weight < 2^(x+1) -+ * n/d < 2^(x+1) -+ * n < d * 2^(x+1) -+ */ -+ while ((x < 8) && (numerator >= (denominator << (x + 1)))) -+ x++; -+ if (x >= 8) -+ return -ERANGE; -+ /* because of the subtraction, use '-rounding' */ -+ y = 64 - ROUNDING(denominator << (x + 6), numerator, -rounding); -+ if (y >= 32) -+ return -ERANGE; -+ weight_code->x = x; -+ weight_code->y = y; -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_ratio2wbfs); -+ -+int qman_ceetm_set_queue_weight_in_ratio(struct qm_ceetm_cq *cq, u32 ratio) -+{ -+ struct qm_ceetm_weight_code weight_code; -+ -+ if (qman_ceetm_ratio2wbfs(ratio, 100, &weight_code, 0)) { -+ pr_err("Cannot get wbfs code for cq %x\n", cq->idx); -+ return -EINVAL; -+ } -+ return qman_ceetm_set_queue_weight(cq, &weight_code); -+} -+EXPORT_SYMBOL(qman_ceetm_set_queue_weight_in_ratio); -+ -+int qman_ceetm_get_queue_weight_in_ratio(struct qm_ceetm_cq *cq, u32 *ratio) -+{ -+ struct qm_ceetm_weight_code weight_code; -+ u32 n, d; -+ -+ if (qman_ceetm_get_queue_weight(cq, &weight_code)) { -+ pr_err("Cannot query the weight code for cq%x\n", cq->idx); -+ return -EINVAL; -+ } -+ -+ if (qman_ceetm_wbfs2ratio(&weight_code, &n, &d)) { -+ pr_err("Cannot get the ratio with wbfs code\n"); -+ return -EINVAL; -+ } -+ -+ *ratio = (n * (u32)100) / d; -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_get_queue_weight_in_ratio); -+ -+int qman_ceetm_cq_get_dequeue_statistics(struct qm_ceetm_cq *cq, u32 flags, -+ u64 *frame_count, u64 *byte_count) -+{ -+ struct qm_mcr_ceetm_statistics_query result; -+ u16 cid, command_type; -+ enum qm_dc_portal dcp_idx; -+ int ret; -+ -+ cid = cpu_to_be16((cq->parent->idx << 4) | cq->idx); -+ dcp_idx = cq->parent->dcp_idx; -+ if (flags == QMAN_CEETM_FLAG_CLEAR_STATISTICS_COUNTER) -+ command_type = CEETM_QUERY_DEQUEUE_CLEAR_STATISTICS; -+ else -+ command_type = CEETM_QUERY_DEQUEUE_STATISTICS; -+ -+ ret = qman_ceetm_query_statistics(cid, dcp_idx, command_type, &result); -+ if (ret) { -+ pr_err("Can't query the statistics of CQ#%d!\n", cq->idx); -+ return -EINVAL; -+ } -+ -+ *frame_count = be40_to_cpu(result.frm_cnt); -+ *byte_count = be48_to_cpu(result.byte_cnt); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_cq_get_dequeue_statistics); -+ -+int qman_ceetm_drain_cq(struct qm_ceetm_cq *cq) -+{ -+ struct qm_mcr_ceetm_cq_peek_pop_xsfdrread ppxr; -+ int ret; -+ -+ do { -+ ret = qman_ceetm_cq_peek_pop_xsfdrread(cq, 1, 0, &ppxr); -+ if (ret) { -+ pr_err("Failed to pop frame from CQ\n"); -+ return -EINVAL; -+ } -+ } while (!(ppxr.stat & 0x2)); -+ -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_drain_cq); -+ -+#define CEETM_LFQMT_LFQID_MSB 0xF00000 -+#define CEETM_LFQMT_LFQID_LSB 0x000FFF -+int qman_ceetm_lfq_claim(struct qm_ceetm_lfq **lfq, -+ struct qm_ceetm_cq *cq) -+{ -+ struct qm_ceetm_lfq *p; -+ u32 lfqid; -+ int ret = 0; -+ struct qm_mcc_ceetm_lfqmt_config lfqmt_config; -+ -+ if (cq->parent->dcp_idx == qm_dc_portal_fman0) { -+ ret = qman_alloc_ceetm0_lfqid(&lfqid); -+ } else if (cq->parent->dcp_idx == qm_dc_portal_fman1) { -+ ret = qman_alloc_ceetm1_lfqid(&lfqid); -+ } else { -+ pr_err("dcp_idx %u does not correspond to a known fman in this driver\n", -+ cq->parent->dcp_idx); -+ return -EINVAL; -+ } -+ -+ if (ret) { -+ pr_err("There is no lfqid avalaible for CQ#%d!\n", cq->idx); -+ return -ENODEV; -+ } -+ p = kmalloc(sizeof(*p), GFP_KERNEL); -+ if (!p) -+ return -ENOMEM; -+ p->idx = lfqid; -+ p->dctidx = (u16)(lfqid & CEETM_LFQMT_LFQID_LSB); -+ p->parent = cq->parent; -+ list_add_tail(&p->node, &cq->bound_lfqids); -+ -+ lfqmt_config.lfqid = cpu_to_be24(CEETM_LFQMT_LFQID_MSB | -+ (cq->parent->dcp_idx << 16) | -+ (lfqid & CEETM_LFQMT_LFQID_LSB)); -+ lfqmt_config.cqid = cpu_to_be16((cq->parent->idx << 4) | (cq->idx)); -+ lfqmt_config.dctidx = cpu_to_be16(p->dctidx); -+ if (qman_ceetm_configure_lfqmt(&lfqmt_config)) { -+ pr_err("Can't configure LFQMT for LFQID#%d @ CQ#%d\n", -+ lfqid, cq->idx); -+ list_del(&p->node); -+ kfree(p); -+ return -EINVAL; -+ } -+ *lfq = p; -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_lfq_claim); -+ -+int qman_ceetm_lfq_release(struct qm_ceetm_lfq *lfq) -+{ -+ if (lfq->parent->dcp_idx == qm_dc_portal_fman0) { -+ qman_release_ceetm0_lfqid(lfq->idx); -+ } else if (lfq->parent->dcp_idx == qm_dc_portal_fman1) { -+ qman_release_ceetm1_lfqid(lfq->idx); -+ } else { -+ pr_err("dcp_idx %u does not correspond to a known fman in this driver\n", -+ lfq->parent->dcp_idx); -+ return -EINVAL; -+ } -+ list_del(&lfq->node); -+ kfree(lfq); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_lfq_release); -+ -+int qman_ceetm_lfq_set_context(struct qm_ceetm_lfq *lfq, u64 context_a, -+ u32 context_b) -+{ -+ struct qm_mcc_ceetm_dct_config dct_config; -+ lfq->context_a = context_a; -+ lfq->context_b = context_b; -+ dct_config.dctidx = cpu_to_be16(lfq->dctidx); -+ dct_config.dcpid = lfq->parent->dcp_idx; -+ dct_config.context_b = cpu_to_be32(context_b); -+ dct_config.context_a = cpu_to_be64(context_a); -+ return qman_ceetm_configure_dct(&dct_config); -+} -+EXPORT_SYMBOL(qman_ceetm_lfq_set_context); -+ -+int qman_ceetm_lfq_get_context(struct qm_ceetm_lfq *lfq, u64 *context_a, -+ u32 *context_b) -+{ -+ struct qm_mcc_ceetm_dct_query dct_query; -+ struct qm_mcr_ceetm_dct_query query_result; -+ -+ dct_query.dctidx = cpu_to_be16(lfq->dctidx); -+ dct_query.dcpid = lfq->parent->dcp_idx; -+ if (qman_ceetm_query_dct(&dct_query, &query_result)) { -+ pr_err("Can't query LFQID#%d's context!\n", lfq->idx); -+ return -EINVAL; -+ } -+ *context_a = be64_to_cpu(query_result.context_a); -+ *context_b = be32_to_cpu(query_result.context_b); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_lfq_get_context); -+ -+int qman_ceetm_create_fq(struct qm_ceetm_lfq *lfq, struct qman_fq *fq) -+{ -+ spin_lock_init(&fq->fqlock); -+ fq->fqid = lfq->idx; -+ fq->flags = QMAN_FQ_FLAG_NO_MODIFY; -+ if (lfq->ern) -+ fq->cb.ern = lfq->ern; -+#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP -+ if (unlikely(find_empty_fq_table_entry(&fq->key, fq))) -+ return -ENOMEM; -+#endif -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_create_fq); -+ -+int qman_ceetm_ccg_claim(struct qm_ceetm_ccg **ccg, -+ struct qm_ceetm_channel *channel, -+ unsigned int idx, -+ void (*cscn)(struct qm_ceetm_ccg *, -+ void *cb_ctx, -+ int congested), -+ void *cb_ctx) -+{ -+ struct qm_ceetm_ccg *p; -+ -+ if (idx > 15) { -+ pr_err("The given ccg index is out of range\n"); -+ return -EINVAL; -+ } -+ -+ list_for_each_entry(p, &channel->ccgs, node) { -+ if (p->idx == idx) { -+ pr_err("The CCG#%d has been claimed\n", idx); -+ return -EINVAL; -+ } -+ } -+ -+ p = kmalloc(sizeof(*p), GFP_KERNEL); -+ if (!p) { -+ pr_err("Can't allocate memory for CCG#%d!\n", idx); -+ return -ENOMEM; -+ } -+ -+ list_add_tail(&p->node, &channel->ccgs); -+ -+ p->idx = idx; -+ p->parent = channel; -+ p->cb = cscn; -+ p->cb_ctx = cb_ctx; -+ INIT_LIST_HEAD(&p->cb_node); -+ -+ *ccg = p; -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_ccg_claim); -+ -+int qman_ceetm_ccg_release(struct qm_ceetm_ccg *ccg) -+{ -+ unsigned long irqflags __maybe_unused; -+ struct qm_mcc_ceetm_ccgr_config config_opts; -+ int ret = 0; -+ struct qman_portal *p = get_affine_portal(); -+ -+ memset(&config_opts, 0, sizeof(struct qm_mcc_ceetm_ccgr_config)); -+ spin_lock_irqsave(&p->ccgr_lock, irqflags); -+ if (!list_empty(&ccg->cb_node)) -+ list_del(&ccg->cb_node); -+ config_opts.ccgrid = cpu_to_be16(CEETM_CCGR_CM_CONFIGURE | -+ (ccg->parent->idx << 4) | ccg->idx); -+ config_opts.dcpid = ccg->parent->dcp_idx; -+ config_opts.we_mask = cpu_to_be16(QM_CCGR_WE_CSCN_TUPD); -+ config_opts.cm_config.cscn_tupd = cpu_to_be16(PORTAL_IDX(p)); -+ ret = qman_ceetm_configure_ccgr(&config_opts); -+ spin_unlock_irqrestore(&p->ccgr_lock, irqflags); -+ put_affine_portal(); -+ -+ list_del(&ccg->node); -+ kfree(ccg); -+ return ret; -+} -+EXPORT_SYMBOL(qman_ceetm_ccg_release); -+ -+int qman_ceetm_ccg_set(struct qm_ceetm_ccg *ccg, u16 we_mask, -+ const struct qm_ceetm_ccg_params *params) -+{ -+ struct qm_mcc_ceetm_ccgr_config config_opts; -+ unsigned long irqflags __maybe_unused; -+ int ret; -+ struct qman_portal *p; -+ -+ if (((ccg->parent->idx << 4) | ccg->idx) >= (2 * __CGR_NUM)) -+ return -EINVAL; -+ -+ p = get_affine_portal(); -+ -+ memset(&config_opts, 0, sizeof(struct qm_mcc_ceetm_ccgr_config)); -+ spin_lock_irqsave(&p->ccgr_lock, irqflags); -+ -+ config_opts.ccgrid = cpu_to_be16(CEETM_CCGR_CM_CONFIGURE | -+ (ccg->parent->idx << 4) | ccg->idx); -+ config_opts.dcpid = ccg->parent->dcp_idx; -+ config_opts.we_mask = we_mask; -+ if (we_mask & QM_CCGR_WE_CSCN_EN) { -+ config_opts.we_mask |= QM_CCGR_WE_CSCN_TUPD; -+ config_opts.cm_config.cscn_tupd = cpu_to_be16( -+ QM_CGR_TARG_UDP_CTRL_WRITE_BIT | PORTAL_IDX(p)); -+ } -+ config_opts.we_mask = cpu_to_be16(config_opts.we_mask); -+ config_opts.cm_config.ctl_wr_en_g = params->wr_en_g; -+ config_opts.cm_config.ctl_wr_en_y = params->wr_en_y; -+ config_opts.cm_config.ctl_wr_en_r = params->wr_en_r; -+ config_opts.cm_config.ctl_td_en = params->td_en; -+ config_opts.cm_config.ctl_td_mode = params->td_mode; -+ config_opts.cm_config.ctl_cscn_en = params->cscn_en; -+ config_opts.cm_config.ctl_mode = params->mode; -+ config_opts.cm_config.oal = params->oal; -+ config_opts.cm_config.cs_thres.hword = -+ cpu_to_be16(params->cs_thres_in.hword); -+ config_opts.cm_config.cs_thres_x.hword = -+ cpu_to_be16(params->cs_thres_out.hword); -+ config_opts.cm_config.td_thres.hword = -+ cpu_to_be16(params->td_thres.hword); -+ config_opts.cm_config.wr_parm_g.word = -+ cpu_to_be32(params->wr_parm_g.word); -+ config_opts.cm_config.wr_parm_y.word = -+ cpu_to_be32(params->wr_parm_y.word); -+ config_opts.cm_config.wr_parm_r.word = -+ cpu_to_be32(params->wr_parm_r.word); -+ ret = qman_ceetm_configure_ccgr(&config_opts); -+ if (ret) { -+ pr_err("Configure CCGR CM failed!\n"); -+ goto release_lock; -+ } -+ -+ if (we_mask & QM_CCGR_WE_CSCN_EN) -+ if (list_empty(&ccg->cb_node)) -+ list_add(&ccg->cb_node, -+ &p->ccgr_cbs[ccg->parent->dcp_idx]); -+release_lock: -+ spin_unlock_irqrestore(&p->ccgr_lock, irqflags); -+ put_affine_portal(); -+ return ret; -+} -+EXPORT_SYMBOL(qman_ceetm_ccg_set); -+ -+#define CEETM_CCGR_CTL_MASK 0x01 -+int qman_ceetm_ccg_get(struct qm_ceetm_ccg *ccg, -+ struct qm_ceetm_ccg_params *params) -+{ -+ struct qm_mcc_ceetm_ccgr_query query_opts; -+ struct qm_mcr_ceetm_ccgr_query query_result; -+ -+ query_opts.ccgrid = cpu_to_be16(CEETM_CCGR_CM_QUERY | -+ (ccg->parent->idx << 4) | ccg->idx); -+ query_opts.dcpid = ccg->parent->dcp_idx; -+ -+ if (qman_ceetm_query_ccgr(&query_opts, &query_result)) { -+ pr_err("Can't query CCGR#%d\n", ccg->idx); -+ return -EINVAL; -+ } -+ -+ params->wr_parm_r.word = -+ be32_to_cpu(query_result.cm_query.wr_parm_r.word); -+ params->wr_parm_y.word = -+ be32_to_cpu(query_result.cm_query.wr_parm_y.word); -+ params->wr_parm_g.word = -+ be32_to_cpu(query_result.cm_query.wr_parm_g.word); -+ params->td_thres.hword = -+ be16_to_cpu(query_result.cm_query.td_thres.hword); -+ params->cs_thres_out.hword = -+ be16_to_cpu(query_result.cm_query.cs_thres_x.hword); -+ params->cs_thres_in.hword = -+ be16_to_cpu(query_result.cm_query.cs_thres.hword); -+ params->oal = query_result.cm_query.oal; -+ params->wr_en_g = query_result.cm_query.ctl_wr_en_g; -+ params->wr_en_y = query_result.cm_query.ctl_wr_en_y; -+ params->wr_en_r = query_result.cm_query.ctl_wr_en_r; -+ params->td_en = query_result.cm_query.ctl_td_en; -+ params->td_mode = query_result.cm_query.ctl_td_mode; -+ params->cscn_en = query_result.cm_query.ctl_cscn_en; -+ params->mode = query_result.cm_query.ctl_mode; -+ -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_ccg_get); -+ -+int qman_ceetm_ccg_get_reject_statistics(struct qm_ceetm_ccg *ccg, u32 flags, -+ u64 *frame_count, u64 *byte_count) -+{ -+ struct qm_mcr_ceetm_statistics_query result; -+ u16 cid, command_type; -+ enum qm_dc_portal dcp_idx; -+ int ret; -+ -+ cid = cpu_to_be16((ccg->parent->idx << 4) | ccg->idx); -+ dcp_idx = ccg->parent->dcp_idx; -+ if (flags == QMAN_CEETM_FLAG_CLEAR_STATISTICS_COUNTER) -+ command_type = CEETM_QUERY_REJECT_CLEAR_STATISTICS; -+ else -+ command_type = CEETM_QUERY_REJECT_STATISTICS; -+ -+ ret = qman_ceetm_query_statistics(cid, dcp_idx, command_type, &result); -+ if (ret) { -+ pr_err("Can't query the statistics of CCG#%d!\n", ccg->idx); -+ return -EINVAL; -+ } -+ -+ *frame_count = be40_to_cpu(result.frm_cnt); -+ *byte_count = be48_to_cpu(result.byte_cnt); -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_ccg_get_reject_statistics); -+ -+int qman_ceetm_cscn_swp_get(struct qm_ceetm_ccg *ccg, -+ u16 swp_idx, -+ unsigned int *cscn_enabled) -+{ -+ struct qm_mcc_ceetm_ccgr_query query_opts; -+ struct qm_mcr_ceetm_ccgr_query query_result; -+ int i; -+ -+ DPA_ASSERT(swp_idx < 127); -+ query_opts.ccgrid = cpu_to_be16(CEETM_CCGR_CM_QUERY | -+ (ccg->parent->idx << 4) | ccg->idx); -+ query_opts.dcpid = ccg->parent->dcp_idx; -+ -+ if (qman_ceetm_query_ccgr(&query_opts, &query_result)) { -+ pr_err("Can't query CCGR#%d\n", ccg->idx); -+ return -EINVAL; -+ } -+ -+ i = swp_idx / 32; -+ i = 3 - i; -+ *cscn_enabled = be32_to_cpu(query_result.cm_query.cscn_targ_swp[i]) >> -+ (31 - swp_idx % 32); -+ -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_cscn_swp_get); -+ -+int qman_ceetm_cscn_dcp_set(struct qm_ceetm_ccg *ccg, -+ u16 dcp_idx, -+ u8 vcgid, -+ unsigned int cscn_enabled, -+ u16 we_mask, -+ const struct qm_ceetm_ccg_params *params) -+{ -+ struct qm_mcc_ceetm_ccgr_config config_opts; -+ int ret; -+ -+ config_opts.ccgrid = cpu_to_be16(CEETM_CCGR_CM_CONFIGURE | -+ (ccg->parent->idx << 4) | ccg->idx); -+ config_opts.dcpid = ccg->parent->dcp_idx; -+ config_opts.we_mask = cpu_to_be16(we_mask | QM_CCGR_WE_CSCN_TUPD | -+ QM_CCGR_WE_CDV); -+ config_opts.cm_config.cdv = vcgid; -+ config_opts.cm_config.cscn_tupd = cpu_to_be16((cscn_enabled << 15) | -+ QM_CGR_TARG_UDP_CTRL_DCP | dcp_idx); -+ config_opts.cm_config.ctl_wr_en_g = params->wr_en_g; -+ config_opts.cm_config.ctl_wr_en_y = params->wr_en_y; -+ config_opts.cm_config.ctl_wr_en_r = params->wr_en_r; -+ config_opts.cm_config.ctl_td_en = params->td_en; -+ config_opts.cm_config.ctl_td_mode = params->td_mode; -+ config_opts.cm_config.ctl_cscn_en = params->cscn_en; -+ config_opts.cm_config.ctl_mode = params->mode; -+ config_opts.cm_config.cs_thres.hword = -+ cpu_to_be16(params->cs_thres_in.hword); -+ config_opts.cm_config.cs_thres_x.hword = -+ cpu_to_be16(params->cs_thres_out.hword); -+ config_opts.cm_config.td_thres.hword = -+ cpu_to_be16(params->td_thres.hword); -+ config_opts.cm_config.wr_parm_g.word = -+ cpu_to_be32(params->wr_parm_g.word); -+ config_opts.cm_config.wr_parm_y.word = -+ cpu_to_be32(params->wr_parm_y.word); -+ config_opts.cm_config.wr_parm_r.word = -+ cpu_to_be32(params->wr_parm_r.word); -+ -+ ret = qman_ceetm_configure_ccgr(&config_opts); -+ if (ret) { -+ pr_err("Configure CSCN_TARG_DCP failed!\n"); -+ return -EINVAL; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_cscn_dcp_set); -+ -+int qman_ceetm_cscn_dcp_get(struct qm_ceetm_ccg *ccg, -+ u16 dcp_idx, -+ u8 *vcgid, -+ unsigned int *cscn_enabled) -+{ -+ struct qm_mcc_ceetm_ccgr_query query_opts; -+ struct qm_mcr_ceetm_ccgr_query query_result; -+ -+ query_opts.ccgrid = cpu_to_be16(CEETM_CCGR_CM_QUERY | -+ (ccg->parent->idx << 4) | ccg->idx); -+ query_opts.dcpid = ccg->parent->dcp_idx; -+ -+ if (qman_ceetm_query_ccgr(&query_opts, &query_result)) { -+ pr_err("Can't query CCGR#%d\n", ccg->idx); -+ return -EINVAL; -+ } -+ -+ *vcgid = query_result.cm_query.cdv; -+ *cscn_enabled = (be16_to_cpu(query_result.cm_query.cscn_targ_dcp >> -+ dcp_idx)) & 0x1; -+ return 0; -+} -+EXPORT_SYMBOL(qman_ceetm_cscn_dcp_get); -+ -+int qman_ceetm_querycongestion(struct __qm_mcr_querycongestion *ccg_state, -+ unsigned int dcp_idx) -+{ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ u8 res; -+ int i, j; -+ -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ -+ mcc = qm_mc_start(&p->p); -+ for (i = 0; i < 2; i++) { -+ mcc->ccgr_query.ccgrid = -+ cpu_to_be16(CEETM_QUERY_CONGESTION_STATE | i); -+ mcc->ccgr_query.dcpid = dcp_idx; -+ qm_mc_commit(&p->p, QM_CEETM_VERB_CCGR_QUERY); -+ -+ while (!(mcr = qm_mc_result(&p->p))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == -+ QM_CEETM_VERB_CCGR_QUERY); -+ res = mcr->result; -+ if (res == QM_MCR_RESULT_OK) { -+ for (j = 0; j < 8; j++) -+ mcr->ccgr_query.congestion_state.state. -+ __state[j] = -+ be32_to_cpu(mcr->ccgr_query. -+ congestion_state.state.__state[j]); -+ -+ *(ccg_state + i) = -+ mcr->ccgr_query.congestion_state.state; -+ } else { -+ pr_err("QUERY CEETM CONGESTION STATE failed\n"); -+ return -EIO; -+ } -+ } -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return 0; -+} -+ -+int qman_set_wpm(int wpm_enable) -+{ -+ return qm_set_wpm(wpm_enable); -+} -+EXPORT_SYMBOL(qman_set_wpm); -+ -+int qman_get_wpm(int *wpm_enable) -+{ -+ return qm_get_wpm(wpm_enable); -+} -+EXPORT_SYMBOL(qman_get_wpm); -+ -+int qman_shutdown_fq(u32 fqid) -+{ -+ struct qman_portal *p; -+ unsigned long irqflags __maybe_unused; -+ int ret; -+ struct qm_portal *low_p; -+ p = get_affine_portal(); -+ PORTAL_IRQ_LOCK(p, irqflags); -+ low_p = &p->p; -+ ret = qm_shutdown_fq(&low_p, 1, fqid); -+ PORTAL_IRQ_UNLOCK(p, irqflags); -+ put_affine_portal(); -+ return ret; -+} -+ -+const struct qm_portal_config *qman_get_qm_portal_config( -+ struct qman_portal *portal) -+{ -+ return portal->sharing_redirect ? NULL : portal->config; -+} ---- /dev/null -+++ b/drivers/staging/fsl_qbman/qman_low.h -@@ -0,0 +1,1407 @@ -+/* Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "qman_private.h" -+ -+/***************************/ -+/* Portal register assists */ -+/***************************/ -+ -+/* Cache-inhibited register offsets */ -+#if defined(CONFIG_PPC32) || defined(CONFIG_PPC64) -+ -+#define QM_REG_EQCR_PI_CINH 0x0000 -+#define QM_REG_EQCR_CI_CINH 0x0004 -+#define QM_REG_EQCR_ITR 0x0008 -+#define QM_REG_DQRR_PI_CINH 0x0040 -+#define QM_REG_DQRR_CI_CINH 0x0044 -+#define QM_REG_DQRR_ITR 0x0048 -+#define QM_REG_DQRR_DCAP 0x0050 -+#define QM_REG_DQRR_SDQCR 0x0054 -+#define QM_REG_DQRR_VDQCR 0x0058 -+#define QM_REG_DQRR_PDQCR 0x005c -+#define QM_REG_MR_PI_CINH 0x0080 -+#define QM_REG_MR_CI_CINH 0x0084 -+#define QM_REG_MR_ITR 0x0088 -+#define QM_REG_CFG 0x0100 -+#define QM_REG_ISR 0x0e00 -+#define QM_REG_IIR 0x0e0c -+#define QM_REG_ITPR 0x0e14 -+ -+/* Cache-enabled register offsets */ -+#define QM_CL_EQCR 0x0000 -+#define QM_CL_DQRR 0x1000 -+#define QM_CL_MR 0x2000 -+#define QM_CL_EQCR_PI_CENA 0x3000 -+#define QM_CL_EQCR_CI_CENA 0x3100 -+#define QM_CL_DQRR_PI_CENA 0x3200 -+#define QM_CL_DQRR_CI_CENA 0x3300 -+#define QM_CL_MR_PI_CENA 0x3400 -+#define QM_CL_MR_CI_CENA 0x3500 -+#define QM_CL_CR 0x3800 -+#define QM_CL_RR0 0x3900 -+#define QM_CL_RR1 0x3940 -+ -+#endif -+ -+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) -+ -+#define QM_REG_EQCR_PI_CINH 0x3000 -+#define QM_REG_EQCR_CI_CINH 0x3040 -+#define QM_REG_EQCR_ITR 0x3080 -+#define QM_REG_DQRR_PI_CINH 0x3100 -+#define QM_REG_DQRR_CI_CINH 0x3140 -+#define QM_REG_DQRR_ITR 0x3180 -+#define QM_REG_DQRR_DCAP 0x31C0 -+#define QM_REG_DQRR_SDQCR 0x3200 -+#define QM_REG_DQRR_VDQCR 0x3240 -+#define QM_REG_DQRR_PDQCR 0x3280 -+#define QM_REG_MR_PI_CINH 0x3300 -+#define QM_REG_MR_CI_CINH 0x3340 -+#define QM_REG_MR_ITR 0x3380 -+#define QM_REG_CFG 0x3500 -+#define QM_REG_ISR 0x3600 -+#define QM_REG_IIR 0x36C0 -+#define QM_REG_ITPR 0x3740 -+ -+/* Cache-enabled register offsets */ -+#define QM_CL_EQCR 0x0000 -+#define QM_CL_DQRR 0x1000 -+#define QM_CL_MR 0x2000 -+#define QM_CL_EQCR_PI_CENA 0x3000 -+#define QM_CL_EQCR_CI_CENA 0x3040 -+#define QM_CL_DQRR_PI_CENA 0x3100 -+#define QM_CL_DQRR_CI_CENA 0x3140 -+#define QM_CL_MR_PI_CENA 0x3300 -+#define QM_CL_MR_CI_CENA 0x3340 -+#define QM_CL_CR 0x3800 -+#define QM_CL_RR0 0x3900 -+#define QM_CL_RR1 0x3940 -+ -+#endif -+ -+ -+/* BTW, the drivers (and h/w programming model) already obtain the required -+ * synchronisation for portal accesses via lwsync(), hwsync(), and -+ * data-dependencies. Use of barrier()s or other order-preserving primitives -+ * simply degrade performance. Hence the use of the __raw_*() interfaces, which -+ * simply ensure that the compiler treats the portal registers as volatile (ie. -+ * non-coherent). */ -+ -+/* Cache-inhibited register access. */ -+#define __qm_in(qm, o) be32_to_cpu(__raw_readl((qm)->addr_ci + (o))) -+#define __qm_out(qm, o, val) __raw_writel((cpu_to_be32(val)), \ -+ (qm)->addr_ci + (o)); -+#define qm_in(reg) __qm_in(&portal->addr, QM_REG_##reg) -+#define qm_out(reg, val) __qm_out(&portal->addr, QM_REG_##reg, val) -+ -+/* Cache-enabled (index) register access */ -+#define __qm_cl_touch_ro(qm, o) dcbt_ro((qm)->addr_ce + (o)) -+#define __qm_cl_touch_rw(qm, o) dcbt_rw((qm)->addr_ce + (o)) -+#define __qm_cl_in(qm, o) be32_to_cpu(__raw_readl((qm)->addr_ce + (o))) -+#define __qm_cl_out(qm, o, val) \ -+ do { \ -+ u32 *__tmpclout = (qm)->addr_ce + (o); \ -+ __raw_writel(cpu_to_be32(val), __tmpclout); \ -+ dcbf(__tmpclout); \ -+ } while (0) -+#define __qm_cl_invalidate(qm, o) dcbi((qm)->addr_ce + (o)) -+#define qm_cl_touch_ro(reg) __qm_cl_touch_ro(&portal->addr, QM_CL_##reg##_CENA) -+#define qm_cl_touch_rw(reg) __qm_cl_touch_rw(&portal->addr, QM_CL_##reg##_CENA) -+#define qm_cl_in(reg) __qm_cl_in(&portal->addr, QM_CL_##reg##_CENA) -+#define qm_cl_out(reg, val) __qm_cl_out(&portal->addr, QM_CL_##reg##_CENA, val) -+#define qm_cl_invalidate(reg)\ -+ __qm_cl_invalidate(&portal->addr, QM_CL_##reg##_CENA) -+ -+/* Cache-enabled ring access */ -+#define qm_cl(base, idx) ((void *)base + ((idx) << 6)) -+ -+/* Cyclic helper for rings. FIXME: once we are able to do fine-grain perf -+ * analysis, look at using the "extra" bit in the ring index registers to avoid -+ * cyclic issues. */ -+static inline u8 qm_cyc_diff(u8 ringsize, u8 first, u8 last) -+{ -+ /* 'first' is included, 'last' is excluded */ -+ if (first <= last) -+ return last - first; -+ return ringsize + last - first; -+} -+ -+/* Portal modes. -+ * Enum types; -+ * pmode == production mode -+ * cmode == consumption mode, -+ * dmode == h/w dequeue mode. -+ * Enum values use 3 letter codes. First letter matches the portal mode, -+ * remaining two letters indicate; -+ * ci == cache-inhibited portal register -+ * ce == cache-enabled portal register -+ * vb == in-band valid-bit (cache-enabled) -+ * dc == DCA (Discrete Consumption Acknowledgement), DQRR-only -+ * As for "enum qm_dqrr_dmode", it should be self-explanatory. -+ */ -+enum qm_eqcr_pmode { /* matches QCSP_CFG::EPM */ -+ qm_eqcr_pci = 0, /* PI index, cache-inhibited */ -+ qm_eqcr_pce = 1, /* PI index, cache-enabled */ -+ qm_eqcr_pvb = 2 /* valid-bit */ -+}; -+enum qm_dqrr_dmode { /* matches QCSP_CFG::DP */ -+ qm_dqrr_dpush = 0, /* SDQCR + VDQCR */ -+ qm_dqrr_dpull = 1 /* PDQCR */ -+}; -+enum qm_dqrr_pmode { /* s/w-only */ -+ qm_dqrr_pci, /* reads DQRR_PI_CINH */ -+ qm_dqrr_pce, /* reads DQRR_PI_CENA */ -+ qm_dqrr_pvb /* reads valid-bit */ -+}; -+enum qm_dqrr_cmode { /* matches QCSP_CFG::DCM */ -+ qm_dqrr_cci = 0, /* CI index, cache-inhibited */ -+ qm_dqrr_cce = 1, /* CI index, cache-enabled */ -+ qm_dqrr_cdc = 2 /* Discrete Consumption Acknowledgement */ -+}; -+enum qm_mr_pmode { /* s/w-only */ -+ qm_mr_pci, /* reads MR_PI_CINH */ -+ qm_mr_pce, /* reads MR_PI_CENA */ -+ qm_mr_pvb /* reads valid-bit */ -+}; -+enum qm_mr_cmode { /* matches QCSP_CFG::MM */ -+ qm_mr_cci = 0, /* CI index, cache-inhibited */ -+ qm_mr_cce = 1 /* CI index, cache-enabled */ -+}; -+ -+ -+/* ------------------------- */ -+/* --- Portal structures --- */ -+ -+#define QM_EQCR_SIZE 8 -+#define QM_DQRR_SIZE 16 -+#define QM_MR_SIZE 8 -+ -+struct qm_eqcr { -+ struct qm_eqcr_entry *ring, *cursor; -+ u8 ci, available, ithresh, vbit; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ u32 busy; -+ enum qm_eqcr_pmode pmode; -+#endif -+}; -+ -+struct qm_dqrr { -+ const struct qm_dqrr_entry *ring, *cursor; -+ u8 pi, ci, fill, ithresh, vbit; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ enum qm_dqrr_dmode dmode; -+ enum qm_dqrr_pmode pmode; -+ enum qm_dqrr_cmode cmode; -+#endif -+}; -+ -+struct qm_mr { -+ const struct qm_mr_entry *ring, *cursor; -+ u8 pi, ci, fill, ithresh, vbit; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ enum qm_mr_pmode pmode; -+ enum qm_mr_cmode cmode; -+#endif -+}; -+ -+struct qm_mc { -+ struct qm_mc_command *cr; -+ struct qm_mc_result *rr; -+ u8 rridx, vbit; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ enum { -+ /* Can be _mc_start()ed */ -+ qman_mc_idle, -+ /* Can be _mc_commit()ed or _mc_abort()ed */ -+ qman_mc_user, -+ /* Can only be _mc_retry()ed */ -+ qman_mc_hw -+ } state; -+#endif -+}; -+ -+#define QM_PORTAL_ALIGNMENT ____cacheline_aligned -+ -+struct qm_addr { -+ void __iomem *addr_ce; /* cache-enabled */ -+ void __iomem *addr_ci; /* cache-inhibited */ -+}; -+ -+struct qm_portal { -+ /* In the non-CONFIG_FSL_DPA_CHECKING case, the following stuff up to -+ * and including 'mc' fits within a cacheline (yay!). The 'config' part -+ * is setup-only, so isn't a cause for a concern. In other words, don't -+ * rearrange this structure on a whim, there be dragons ... */ -+ struct qm_addr addr; -+ struct qm_eqcr eqcr; -+ struct qm_dqrr dqrr; -+ struct qm_mr mr; -+ struct qm_mc mc; -+} QM_PORTAL_ALIGNMENT; -+ -+ -+/* ---------------- */ -+/* --- EQCR API --- */ -+ -+/* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */ -+#define EQCR_CARRYCLEAR(p) \ -+ (void *)((unsigned long)(p) & (~(unsigned long)(QM_EQCR_SIZE << 6))) -+ -+/* Bit-wise logic to convert a ring pointer to a ring index */ -+static inline u8 EQCR_PTR2IDX(struct qm_eqcr_entry *e) -+{ -+ return ((uintptr_t)e >> 6) & (QM_EQCR_SIZE - 1); -+} -+ -+/* Increment the 'cursor' ring pointer, taking 'vbit' into account */ -+static inline void EQCR_INC(struct qm_eqcr *eqcr) -+{ -+ /* NB: this is odd-looking, but experiments show that it generates fast -+ * code with essentially no branching overheads. We increment to the -+ * next EQCR pointer and handle overflow and 'vbit'. */ -+ struct qm_eqcr_entry *partial = eqcr->cursor + 1; -+ eqcr->cursor = EQCR_CARRYCLEAR(partial); -+ if (partial != eqcr->cursor) -+ eqcr->vbit ^= QM_EQCR_VERB_VBIT; -+} -+ -+static inline int qm_eqcr_init(struct qm_portal *portal, -+ enum qm_eqcr_pmode pmode, -+ unsigned int eq_stash_thresh, -+ int eq_stash_prio) -+{ -+ /* This use of 'register', as well as all other occurrences, is because -+ * it has been observed to generate much faster code with gcc than is -+ * otherwise the case. */ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ u32 cfg; -+ u8 pi; -+ -+ eqcr->ring = portal->addr.addr_ce + QM_CL_EQCR; -+ eqcr->ci = qm_in(EQCR_CI_CINH) & (QM_EQCR_SIZE - 1); -+ qm_cl_invalidate(EQCR_CI); -+ pi = qm_in(EQCR_PI_CINH) & (QM_EQCR_SIZE - 1); -+ eqcr->cursor = eqcr->ring + pi; -+ eqcr->vbit = (qm_in(EQCR_PI_CINH) & QM_EQCR_SIZE) ? -+ QM_EQCR_VERB_VBIT : 0; -+ eqcr->available = QM_EQCR_SIZE - 1 - -+ qm_cyc_diff(QM_EQCR_SIZE, eqcr->ci, pi); -+ eqcr->ithresh = qm_in(EQCR_ITR); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ eqcr->busy = 0; -+ eqcr->pmode = pmode; -+#endif -+ cfg = (qm_in(CFG) & 0x00ffffff) | -+ (eq_stash_thresh << 28) | /* QCSP_CFG: EST */ -+ (eq_stash_prio << 26) | /* QCSP_CFG: EP */ -+ ((pmode & 0x3) << 24); /* QCSP_CFG::EPM */ -+ qm_out(CFG, cfg); -+ return 0; -+} -+ -+static inline unsigned int qm_eqcr_get_ci_stashing(struct qm_portal *portal) -+{ -+ return (qm_in(CFG) >> 28) & 0x7; -+} -+ -+static inline void qm_eqcr_finish(struct qm_portal *portal) -+{ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ u8 pi, ci; -+ u32 cfg; -+ -+ /* -+ * Disable EQCI stashing because the QMan only -+ * presents the value it previously stashed to -+ * maintain coherency. Setting the stash threshold -+ * to 1 then 0 ensures that QMan has resyncronized -+ * its internal copy so that the portal is clean -+ * when it is reinitialized in the future -+ */ -+ cfg = (qm_in(CFG) & 0x0fffffff) | -+ (1 << 28); /* QCSP_CFG: EST */ -+ qm_out(CFG, cfg); -+ cfg &= 0x0fffffff; /* stash threshold = 0 */ -+ qm_out(CFG, cfg); -+ -+ pi = qm_in(EQCR_PI_CINH) & (QM_EQCR_SIZE - 1); -+ ci = qm_in(EQCR_CI_CINH) & (QM_EQCR_SIZE - 1); -+ -+ /* Refresh EQCR CI cache value */ -+ qm_cl_invalidate(EQCR_CI); -+ eqcr->ci = qm_cl_in(EQCR_CI) & (QM_EQCR_SIZE - 1); -+ -+ DPA_ASSERT(!eqcr->busy); -+ if (pi != EQCR_PTR2IDX(eqcr->cursor)) -+ pr_crit("losing uncommited EQCR entries\n"); -+ if (ci != eqcr->ci) -+ pr_crit("missing existing EQCR completions\n"); -+ if (eqcr->ci != EQCR_PTR2IDX(eqcr->cursor)) -+ pr_crit("EQCR destroyed unquiesced\n"); -+} -+ -+static inline struct qm_eqcr_entry *qm_eqcr_start_no_stash(struct qm_portal -+ *portal) -+{ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ DPA_ASSERT(!eqcr->busy); -+ if (!eqcr->available) -+ return NULL; -+ -+ -+#ifdef CONFIG_FSL_DPA_CHECKING -+ eqcr->busy = 1; -+#endif -+ dcbz_64(eqcr->cursor); -+ return eqcr->cursor; -+} -+ -+static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal -+ *portal) -+{ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ u8 diff, old_ci; -+ -+ DPA_ASSERT(!eqcr->busy); -+ if (!eqcr->available) { -+ old_ci = eqcr->ci; -+ eqcr->ci = qm_cl_in(EQCR_CI) & (QM_EQCR_SIZE - 1); -+ diff = qm_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci); -+ eqcr->available += diff; -+ if (!diff) -+ return NULL; -+ } -+#ifdef CONFIG_FSL_DPA_CHECKING -+ eqcr->busy = 1; -+#endif -+ dcbz_64(eqcr->cursor); -+ return eqcr->cursor; -+} -+ -+static inline void qm_eqcr_abort(struct qm_portal *portal) -+{ -+ __maybe_unused register struct qm_eqcr *eqcr = &portal->eqcr; -+ DPA_ASSERT(eqcr->busy); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ eqcr->busy = 0; -+#endif -+} -+ -+static inline struct qm_eqcr_entry *qm_eqcr_pend_and_next( -+ struct qm_portal *portal, u8 myverb) -+{ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ DPA_ASSERT(eqcr->busy); -+ DPA_ASSERT(eqcr->pmode != qm_eqcr_pvb); -+ if (eqcr->available == 1) -+ return NULL; -+ eqcr->cursor->__dont_write_directly__verb = myverb | eqcr->vbit; -+ dcbf(eqcr->cursor); -+ EQCR_INC(eqcr); -+ eqcr->available--; -+ dcbz_64(eqcr->cursor); -+ return eqcr->cursor; -+} -+ -+#define EQCR_COMMIT_CHECKS(eqcr) \ -+do { \ -+ DPA_ASSERT(eqcr->busy); \ -+ DPA_ASSERT(eqcr->cursor->orp == (eqcr->cursor->orp & 0x00ffffff)); \ -+ DPA_ASSERT(eqcr->cursor->fqid == (eqcr->cursor->fqid & 0x00ffffff)); \ -+} while (0) -+ -+static inline void qm_eqcr_pci_commit(struct qm_portal *portal, u8 myverb) -+{ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ EQCR_COMMIT_CHECKS(eqcr); -+ DPA_ASSERT(eqcr->pmode == qm_eqcr_pci); -+ eqcr->cursor->__dont_write_directly__verb = myverb | eqcr->vbit; -+ EQCR_INC(eqcr); -+ eqcr->available--; -+ dcbf(eqcr->cursor); -+ hwsync(); -+ qm_out(EQCR_PI_CINH, EQCR_PTR2IDX(eqcr->cursor)); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ eqcr->busy = 0; -+#endif -+} -+ -+static inline void qm_eqcr_pce_prefetch(struct qm_portal *portal) -+{ -+ __maybe_unused register struct qm_eqcr *eqcr = &portal->eqcr; -+ DPA_ASSERT(eqcr->pmode == qm_eqcr_pce); -+ qm_cl_invalidate(EQCR_PI); -+ qm_cl_touch_rw(EQCR_PI); -+} -+ -+static inline void qm_eqcr_pce_commit(struct qm_portal *portal, u8 myverb) -+{ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ EQCR_COMMIT_CHECKS(eqcr); -+ DPA_ASSERT(eqcr->pmode == qm_eqcr_pce); -+ eqcr->cursor->__dont_write_directly__verb = myverb | eqcr->vbit; -+ EQCR_INC(eqcr); -+ eqcr->available--; -+ dcbf(eqcr->cursor); -+ lwsync(); -+ qm_cl_out(EQCR_PI, EQCR_PTR2IDX(eqcr->cursor)); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ eqcr->busy = 0; -+#endif -+} -+ -+static inline void qm_eqcr_pvb_commit(struct qm_portal *portal, u8 myverb) -+{ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ struct qm_eqcr_entry *eqcursor; -+ EQCR_COMMIT_CHECKS(eqcr); -+ DPA_ASSERT(eqcr->pmode == qm_eqcr_pvb); -+ lwsync(); -+ eqcursor = eqcr->cursor; -+ eqcursor->__dont_write_directly__verb = myverb | eqcr->vbit; -+ dcbf(eqcursor); -+ EQCR_INC(eqcr); -+ eqcr->available--; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ eqcr->busy = 0; -+#endif -+} -+ -+static inline u8 qm_eqcr_cci_update(struct qm_portal *portal) -+{ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ u8 diff, old_ci = eqcr->ci; -+ eqcr->ci = qm_in(EQCR_CI_CINH) & (QM_EQCR_SIZE - 1); -+ diff = qm_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci); -+ eqcr->available += diff; -+ return diff; -+} -+ -+static inline void qm_eqcr_cce_prefetch(struct qm_portal *portal) -+{ -+ __maybe_unused register struct qm_eqcr *eqcr = &portal->eqcr; -+ qm_cl_touch_ro(EQCR_CI); -+} -+ -+static inline u8 qm_eqcr_cce_update(struct qm_portal *portal) -+{ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ u8 diff, old_ci = eqcr->ci; -+ eqcr->ci = qm_cl_in(EQCR_CI) & (QM_EQCR_SIZE - 1); -+ qm_cl_invalidate(EQCR_CI); -+ diff = qm_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci); -+ eqcr->available += diff; -+ return diff; -+} -+ -+static inline u8 qm_eqcr_get_ithresh(struct qm_portal *portal) -+{ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ return eqcr->ithresh; -+} -+ -+static inline void qm_eqcr_set_ithresh(struct qm_portal *portal, u8 ithresh) -+{ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ eqcr->ithresh = ithresh; -+ qm_out(EQCR_ITR, ithresh); -+} -+ -+static inline u8 qm_eqcr_get_avail(struct qm_portal *portal) -+{ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ return eqcr->available; -+} -+ -+static inline u8 qm_eqcr_get_fill(struct qm_portal *portal) -+{ -+ register struct qm_eqcr *eqcr = &portal->eqcr; -+ return QM_EQCR_SIZE - 1 - eqcr->available; -+} -+ -+ -+/* ---------------- */ -+/* --- DQRR API --- */ -+ -+/* FIXME: many possible improvements; -+ * - look at changing the API to use pointer rather than index parameters now -+ * that 'cursor' is a pointer, -+ * - consider moving other parameters to pointer if it could help (ci) -+ */ -+ -+#define DQRR_CARRYCLEAR(p) \ -+ (void *)((unsigned long)(p) & (~(unsigned long)(QM_DQRR_SIZE << 6))) -+ -+static inline u8 DQRR_PTR2IDX(const struct qm_dqrr_entry *e) -+{ -+ return ((uintptr_t)e >> 6) & (QM_DQRR_SIZE - 1); -+} -+ -+static inline const struct qm_dqrr_entry *DQRR_INC( -+ const struct qm_dqrr_entry *e) -+{ -+ return DQRR_CARRYCLEAR(e + 1); -+} -+ -+static inline void qm_dqrr_set_maxfill(struct qm_portal *portal, u8 mf) -+{ -+ qm_out(CFG, (qm_in(CFG) & 0xff0fffff) | -+ ((mf & (QM_DQRR_SIZE - 1)) << 20)); -+} -+ -+static inline void qm_dqrr_cci_consume(struct qm_portal *portal, u8 num) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->cmode == qm_dqrr_cci); -+ dqrr->ci = (dqrr->ci + num) & (QM_DQRR_SIZE - 1); -+ qm_out(DQRR_CI_CINH, dqrr->ci); -+} -+ -+static inline void qm_dqrr_cce_consume(struct qm_portal *portal, u8 num) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->cmode == qm_dqrr_cce); -+ dqrr->ci = (dqrr->ci + num) & (QM_DQRR_SIZE - 1); -+ qm_cl_out(DQRR_CI, dqrr->ci); -+} -+ -+static inline void qm_dqrr_cdc_consume_n(struct qm_portal *portal, u16 bitmask) -+{ -+ __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->cmode == qm_dqrr_cdc); -+ qm_out(DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */ -+ ((u32)bitmask << 16)); /* DQRR_DCAP::DCAP_CI */ -+ dqrr->ci = qm_in(DQRR_CI_CINH) & (QM_DQRR_SIZE - 1); -+ dqrr->fill = qm_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi); -+} -+ -+static inline int qm_dqrr_init(struct qm_portal *portal, -+ const struct qm_portal_config *config, -+ enum qm_dqrr_dmode dmode, -+ __maybe_unused enum qm_dqrr_pmode pmode, -+ enum qm_dqrr_cmode cmode, u8 max_fill) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ u32 cfg; -+ -+ /* Make sure the DQRR will be idle when we enable */ -+ qm_out(DQRR_SDQCR, 0); -+ qm_out(DQRR_VDQCR, 0); -+ qm_out(DQRR_PDQCR, 0); -+ dqrr->ring = portal->addr.addr_ce + QM_CL_DQRR; -+ dqrr->pi = qm_in(DQRR_PI_CINH) & (QM_DQRR_SIZE - 1); -+ dqrr->ci = qm_in(DQRR_CI_CINH) & (QM_DQRR_SIZE - 1); -+ dqrr->cursor = dqrr->ring + dqrr->ci; -+ dqrr->fill = qm_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi); -+ dqrr->vbit = (qm_in(DQRR_PI_CINH) & QM_DQRR_SIZE) ? -+ QM_DQRR_VERB_VBIT : 0; -+ dqrr->ithresh = qm_in(DQRR_ITR); -+ -+ /* Free up pending DQRR entries if any as per current DCM */ -+ if (dqrr->fill) { -+ enum qm_dqrr_cmode dcm = (qm_in(CFG) >> 16) & 3; -+ -+#ifdef CONFIG_FSL_DPA_CHECKING -+ dqrr->cmode = dcm; -+#endif -+ switch (dcm) { -+ case qm_dqrr_cci: -+ qm_dqrr_cci_consume(portal, dqrr->fill); -+ break; -+ case qm_dqrr_cce: -+ qm_dqrr_cce_consume(portal, dqrr->fill); -+ break; -+ case qm_dqrr_cdc: -+ qm_dqrr_cdc_consume_n(portal, (QM_DQRR_SIZE - 1)); -+ break; -+ default: -+ DPA_ASSERT(0); -+ } -+ } -+ -+#ifdef CONFIG_FSL_DPA_CHECKING -+ dqrr->dmode = dmode; -+ dqrr->pmode = pmode; -+ dqrr->cmode = cmode; -+#endif -+ /* Invalidate every ring entry before beginning */ -+ for (cfg = 0; cfg < QM_DQRR_SIZE; cfg++) -+ dcbi(qm_cl(dqrr->ring, cfg)); -+ cfg = (qm_in(CFG) & 0xff000f00) | -+ ((max_fill & (QM_DQRR_SIZE - 1)) << 20) | /* DQRR_MF */ -+ ((dmode & 1) << 18) | /* DP */ -+ ((cmode & 3) << 16) | /* DCM */ -+ 0xa0 | /* RE+SE */ -+ (0 ? 0x40 : 0) | /* Ignore RP */ -+ (0 ? 0x10 : 0); /* Ignore SP */ -+ qm_out(CFG, cfg); -+ qm_dqrr_set_maxfill(portal, max_fill); -+ return 0; -+} -+ -+static inline void qm_dqrr_finish(struct qm_portal *portal) -+{ -+ __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ if ((dqrr->cmode != qm_dqrr_cdc) && -+ (dqrr->ci != DQRR_PTR2IDX(dqrr->cursor))) -+ pr_crit("Ignoring completed DQRR entries\n"); -+#endif -+} -+ -+static inline const struct qm_dqrr_entry *qm_dqrr_current( -+ struct qm_portal *portal) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ if (!dqrr->fill) -+ return NULL; -+ return dqrr->cursor; -+} -+ -+static inline u8 qm_dqrr_cursor(struct qm_portal *portal) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ return DQRR_PTR2IDX(dqrr->cursor); -+} -+ -+static inline u8 qm_dqrr_next(struct qm_portal *portal) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->fill); -+ dqrr->cursor = DQRR_INC(dqrr->cursor); -+ return --dqrr->fill; -+} -+ -+static inline u8 qm_dqrr_pci_update(struct qm_portal *portal) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ u8 diff, old_pi = dqrr->pi; -+ DPA_ASSERT(dqrr->pmode == qm_dqrr_pci); -+ dqrr->pi = qm_in(DQRR_PI_CINH) & (QM_DQRR_SIZE - 1); -+ diff = qm_cyc_diff(QM_DQRR_SIZE, old_pi, dqrr->pi); -+ dqrr->fill += diff; -+ return diff; -+} -+ -+static inline void qm_dqrr_pce_prefetch(struct qm_portal *portal) -+{ -+ __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->pmode == qm_dqrr_pce); -+ qm_cl_invalidate(DQRR_PI); -+ qm_cl_touch_ro(DQRR_PI); -+} -+ -+static inline u8 qm_dqrr_pce_update(struct qm_portal *portal) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ u8 diff, old_pi = dqrr->pi; -+ DPA_ASSERT(dqrr->pmode == qm_dqrr_pce); -+ dqrr->pi = qm_cl_in(DQRR_PI) & (QM_DQRR_SIZE - 1); -+ diff = qm_cyc_diff(QM_DQRR_SIZE, old_pi, dqrr->pi); -+ dqrr->fill += diff; -+ return diff; -+} -+ -+static inline void qm_dqrr_pvb_update(struct qm_portal *portal) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ const struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi); -+ DPA_ASSERT(dqrr->pmode == qm_dqrr_pvb); -+#ifndef CONFIG_FSL_PAMU -+ /* -+ * If PAMU is not available we need to invalidate the cache. -+ * When PAMU is available the cache is updated by stash -+ */ -+ dcbi(res); -+ dcbt_ro(res); -+#endif -+ -+ /* when accessing 'verb', use __raw_readb() to ensure that compiler -+ * inlining doesn't try to optimise out "excess reads". */ -+ if ((__raw_readb(&res->verb) & QM_DQRR_VERB_VBIT) == dqrr->vbit) { -+ dqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1); -+ if (!dqrr->pi) -+ dqrr->vbit ^= QM_DQRR_VERB_VBIT; -+ dqrr->fill++; -+ } -+} -+ -+ -+static inline void qm_dqrr_cci_consume_to_current(struct qm_portal *portal) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->cmode == qm_dqrr_cci); -+ dqrr->ci = DQRR_PTR2IDX(dqrr->cursor); -+ qm_out(DQRR_CI_CINH, dqrr->ci); -+} -+ -+static inline void qm_dqrr_cce_prefetch(struct qm_portal *portal) -+{ -+ __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->cmode == qm_dqrr_cce); -+ qm_cl_invalidate(DQRR_CI); -+ qm_cl_touch_rw(DQRR_CI); -+} -+ -+static inline void qm_dqrr_cce_consume_to_current(struct qm_portal *portal) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->cmode == qm_dqrr_cce); -+ dqrr->ci = DQRR_PTR2IDX(dqrr->cursor); -+ qm_cl_out(DQRR_CI, dqrr->ci); -+} -+ -+static inline void qm_dqrr_cdc_consume_1(struct qm_portal *portal, u8 idx, -+ int park) -+{ -+ __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->cmode == qm_dqrr_cdc); -+ DPA_ASSERT(idx < QM_DQRR_SIZE); -+ qm_out(DQRR_DCAP, (0 << 8) | /* S */ -+ ((park ? 1 : 0) << 6) | /* PK */ -+ idx); /* DCAP_CI */ -+} -+ -+static inline void qm_dqrr_cdc_consume_1ptr(struct qm_portal *portal, -+ const struct qm_dqrr_entry *dq, -+ int park) -+{ -+ __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr; -+ u8 idx = DQRR_PTR2IDX(dq); -+ DPA_ASSERT(dqrr->cmode == qm_dqrr_cdc); -+ DPA_ASSERT((dqrr->ring + idx) == dq); -+ DPA_ASSERT(idx < QM_DQRR_SIZE); -+ qm_out(DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */ -+ ((park ? 1 : 0) << 6) | /* DQRR_DCAP::PK */ -+ idx); /* DQRR_DCAP::DCAP_CI */ -+} -+ -+static inline u8 qm_dqrr_cdc_cci(struct qm_portal *portal) -+{ -+ __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->cmode == qm_dqrr_cdc); -+ return qm_in(DQRR_CI_CINH) & (QM_DQRR_SIZE - 1); -+} -+ -+static inline void qm_dqrr_cdc_cce_prefetch(struct qm_portal *portal) -+{ -+ __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->cmode == qm_dqrr_cdc); -+ qm_cl_invalidate(DQRR_CI); -+ qm_cl_touch_ro(DQRR_CI); -+} -+ -+static inline u8 qm_dqrr_cdc_cce(struct qm_portal *portal) -+{ -+ __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->cmode == qm_dqrr_cdc); -+ return qm_cl_in(DQRR_CI) & (QM_DQRR_SIZE - 1); -+} -+ -+static inline u8 qm_dqrr_get_ci(struct qm_portal *portal) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->cmode != qm_dqrr_cdc); -+ return dqrr->ci; -+} -+ -+static inline void qm_dqrr_park(struct qm_portal *portal, u8 idx) -+{ -+ __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->cmode != qm_dqrr_cdc); -+ qm_out(DQRR_DCAP, (0 << 8) | /* S */ -+ (1 << 6) | /* PK */ -+ (idx & (QM_DQRR_SIZE - 1))); /* DCAP_CI */ -+} -+ -+static inline void qm_dqrr_park_current(struct qm_portal *portal) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ DPA_ASSERT(dqrr->cmode != qm_dqrr_cdc); -+ qm_out(DQRR_DCAP, (0 << 8) | /* S */ -+ (1 << 6) | /* PK */ -+ DQRR_PTR2IDX(dqrr->cursor)); /* DCAP_CI */ -+} -+ -+static inline void qm_dqrr_sdqcr_set(struct qm_portal *portal, u32 sdqcr) -+{ -+ qm_out(DQRR_SDQCR, sdqcr); -+} -+ -+static inline u32 qm_dqrr_sdqcr_get(struct qm_portal *portal) -+{ -+ return qm_in(DQRR_SDQCR); -+} -+ -+static inline void qm_dqrr_vdqcr_set(struct qm_portal *portal, u32 vdqcr) -+{ -+ qm_out(DQRR_VDQCR, vdqcr); -+} -+ -+static inline u32 qm_dqrr_vdqcr_get(struct qm_portal *portal) -+{ -+ return qm_in(DQRR_VDQCR); -+} -+ -+static inline void qm_dqrr_pdqcr_set(struct qm_portal *portal, u32 pdqcr) -+{ -+ qm_out(DQRR_PDQCR, pdqcr); -+} -+ -+static inline u32 qm_dqrr_pdqcr_get(struct qm_portal *portal) -+{ -+ return qm_in(DQRR_PDQCR); -+} -+ -+static inline u8 qm_dqrr_get_ithresh(struct qm_portal *portal) -+{ -+ register struct qm_dqrr *dqrr = &portal->dqrr; -+ return dqrr->ithresh; -+} -+ -+static inline void qm_dqrr_set_ithresh(struct qm_portal *portal, u8 ithresh) -+{ -+ qm_out(DQRR_ITR, ithresh); -+} -+ -+static inline u8 qm_dqrr_get_maxfill(struct qm_portal *portal) -+{ -+ return (qm_in(CFG) & 0x00f00000) >> 20; -+} -+ -+ -+/* -------------- */ -+/* --- MR API --- */ -+ -+#define MR_CARRYCLEAR(p) \ -+ (void *)((unsigned long)(p) & (~(unsigned long)(QM_MR_SIZE << 6))) -+ -+static inline u8 MR_PTR2IDX(const struct qm_mr_entry *e) -+{ -+ return ((uintptr_t)e >> 6) & (QM_MR_SIZE - 1); -+} -+ -+static inline const struct qm_mr_entry *MR_INC(const struct qm_mr_entry *e) -+{ -+ return MR_CARRYCLEAR(e + 1); -+} -+ -+static inline int qm_mr_init(struct qm_portal *portal, enum qm_mr_pmode pmode, -+ enum qm_mr_cmode cmode) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ u32 cfg; -+ -+ mr->ring = portal->addr.addr_ce + QM_CL_MR; -+ mr->pi = qm_in(MR_PI_CINH) & (QM_MR_SIZE - 1); -+ mr->ci = qm_in(MR_CI_CINH) & (QM_MR_SIZE - 1); -+ mr->cursor = mr->ring + mr->ci; -+ mr->fill = qm_cyc_diff(QM_MR_SIZE, mr->ci, mr->pi); -+ mr->vbit = (qm_in(MR_PI_CINH) & QM_MR_SIZE) ? QM_MR_VERB_VBIT : 0; -+ mr->ithresh = qm_in(MR_ITR); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ mr->pmode = pmode; -+ mr->cmode = cmode; -+#endif -+ cfg = (qm_in(CFG) & 0xfffff0ff) | -+ ((cmode & 1) << 8); /* QCSP_CFG:MM */ -+ qm_out(CFG, cfg); -+ return 0; -+} -+ -+static inline void qm_mr_finish(struct qm_portal *portal) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ if (mr->ci != MR_PTR2IDX(mr->cursor)) -+ pr_crit("Ignoring completed MR entries\n"); -+} -+ -+static inline const struct qm_mr_entry *qm_mr_current(struct qm_portal *portal) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ if (!mr->fill) -+ return NULL; -+ return mr->cursor; -+} -+ -+static inline u8 qm_mr_cursor(struct qm_portal *portal) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ return MR_PTR2IDX(mr->cursor); -+} -+ -+static inline u8 qm_mr_next(struct qm_portal *portal) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ DPA_ASSERT(mr->fill); -+ mr->cursor = MR_INC(mr->cursor); -+ return --mr->fill; -+} -+ -+static inline u8 qm_mr_pci_update(struct qm_portal *portal) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ u8 diff, old_pi = mr->pi; -+ DPA_ASSERT(mr->pmode == qm_mr_pci); -+ mr->pi = qm_in(MR_PI_CINH); -+ diff = qm_cyc_diff(QM_MR_SIZE, old_pi, mr->pi); -+ mr->fill += diff; -+ return diff; -+} -+ -+static inline void qm_mr_pce_prefetch(struct qm_portal *portal) -+{ -+ __maybe_unused register struct qm_mr *mr = &portal->mr; -+ DPA_ASSERT(mr->pmode == qm_mr_pce); -+ qm_cl_invalidate(MR_PI); -+ qm_cl_touch_ro(MR_PI); -+} -+ -+static inline u8 qm_mr_pce_update(struct qm_portal *portal) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ u8 diff, old_pi = mr->pi; -+ DPA_ASSERT(mr->pmode == qm_mr_pce); -+ mr->pi = qm_cl_in(MR_PI) & (QM_MR_SIZE - 1); -+ diff = qm_cyc_diff(QM_MR_SIZE, old_pi, mr->pi); -+ mr->fill += diff; -+ return diff; -+} -+ -+static inline void qm_mr_pvb_update(struct qm_portal *portal) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ const struct qm_mr_entry *res = qm_cl(mr->ring, mr->pi); -+ DPA_ASSERT(mr->pmode == qm_mr_pvb); -+ /* when accessing 'verb', use __raw_readb() to ensure that compiler -+ * inlining doesn't try to optimise out "excess reads". */ -+ if ((__raw_readb(&res->verb) & QM_MR_VERB_VBIT) == mr->vbit) { -+ mr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1); -+ if (!mr->pi) -+ mr->vbit ^= QM_MR_VERB_VBIT; -+ mr->fill++; -+ res = MR_INC(res); -+ } -+ dcbit_ro(res); -+} -+ -+static inline void qm_mr_cci_consume(struct qm_portal *portal, u8 num) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ DPA_ASSERT(mr->cmode == qm_mr_cci); -+ mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1); -+ qm_out(MR_CI_CINH, mr->ci); -+} -+ -+static inline void qm_mr_cci_consume_to_current(struct qm_portal *portal) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ DPA_ASSERT(mr->cmode == qm_mr_cci); -+ mr->ci = MR_PTR2IDX(mr->cursor); -+ qm_out(MR_CI_CINH, mr->ci); -+} -+ -+static inline void qm_mr_cce_prefetch(struct qm_portal *portal) -+{ -+ __maybe_unused register struct qm_mr *mr = &portal->mr; -+ DPA_ASSERT(mr->cmode == qm_mr_cce); -+ qm_cl_invalidate(MR_CI); -+ qm_cl_touch_rw(MR_CI); -+} -+ -+static inline void qm_mr_cce_consume(struct qm_portal *portal, u8 num) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ DPA_ASSERT(mr->cmode == qm_mr_cce); -+ mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1); -+ qm_cl_out(MR_CI, mr->ci); -+} -+ -+static inline void qm_mr_cce_consume_to_current(struct qm_portal *portal) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ DPA_ASSERT(mr->cmode == qm_mr_cce); -+ mr->ci = MR_PTR2IDX(mr->cursor); -+ qm_cl_out(MR_CI, mr->ci); -+} -+ -+static inline u8 qm_mr_get_ci(struct qm_portal *portal) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ return mr->ci; -+} -+ -+static inline u8 qm_mr_get_ithresh(struct qm_portal *portal) -+{ -+ register struct qm_mr *mr = &portal->mr; -+ return mr->ithresh; -+} -+ -+static inline void qm_mr_set_ithresh(struct qm_portal *portal, u8 ithresh) -+{ -+ qm_out(MR_ITR, ithresh); -+} -+ -+ -+/* ------------------------------ */ -+/* --- Management command API --- */ -+ -+static inline int qm_mc_init(struct qm_portal *portal) -+{ -+ register struct qm_mc *mc = &portal->mc; -+ mc->cr = portal->addr.addr_ce + QM_CL_CR; -+ mc->rr = portal->addr.addr_ce + QM_CL_RR0; -+ mc->rridx = (__raw_readb(&mc->cr->__dont_write_directly__verb) & -+ QM_MCC_VERB_VBIT) ? 0 : 1; -+ mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ mc->state = qman_mc_idle; -+#endif -+ return 0; -+} -+ -+static inline void qm_mc_finish(struct qm_portal *portal) -+{ -+ __maybe_unused register struct qm_mc *mc = &portal->mc; -+ DPA_ASSERT(mc->state == qman_mc_idle); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ if (mc->state != qman_mc_idle) -+ pr_crit("Losing incomplete MC command\n"); -+#endif -+} -+ -+static inline struct qm_mc_command *qm_mc_start(struct qm_portal *portal) -+{ -+ register struct qm_mc *mc = &portal->mc; -+ DPA_ASSERT(mc->state == qman_mc_idle); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ mc->state = qman_mc_user; -+#endif -+ dcbz_64(mc->cr); -+ return mc->cr; -+} -+ -+static inline void qm_mc_abort(struct qm_portal *portal) -+{ -+ __maybe_unused register struct qm_mc *mc = &portal->mc; -+ DPA_ASSERT(mc->state == qman_mc_user); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ mc->state = qman_mc_idle; -+#endif -+} -+ -+static inline void qm_mc_commit(struct qm_portal *portal, u8 myverb) -+{ -+ register struct qm_mc *mc = &portal->mc; -+ struct qm_mc_result *rr = mc->rr + mc->rridx; -+ DPA_ASSERT(mc->state == qman_mc_user); -+ lwsync(); -+ mc->cr->__dont_write_directly__verb = myverb | mc->vbit; -+ dcbf(mc->cr); -+ dcbit_ro(rr); -+#ifdef CONFIG_FSL_DPA_CHECKING -+ mc->state = qman_mc_hw; -+#endif -+} -+ -+static inline struct qm_mc_result *qm_mc_result(struct qm_portal *portal) -+{ -+ register struct qm_mc *mc = &portal->mc; -+ struct qm_mc_result *rr = mc->rr + mc->rridx; -+ DPA_ASSERT(mc->state == qman_mc_hw); -+ /* The inactive response register's verb byte always returns zero until -+ * its command is submitted and completed. This includes the valid-bit, -+ * in case you were wondering... */ -+ if (!__raw_readb(&rr->verb)) { -+ dcbit_ro(rr); -+ return NULL; -+ } -+ mc->rridx ^= 1; -+ mc->vbit ^= QM_MCC_VERB_VBIT; -+#ifdef CONFIG_FSL_DPA_CHECKING -+ mc->state = qman_mc_idle; -+#endif -+ return rr; -+} -+ -+ -+/* ------------------------------------- */ -+/* --- Portal interrupt register API --- */ -+ -+static inline int qm_isr_init(__always_unused struct qm_portal *portal) -+{ -+ return 0; -+} -+ -+static inline void qm_isr_finish(__always_unused struct qm_portal *portal) -+{ -+} -+ -+static inline void qm_isr_set_iperiod(struct qm_portal *portal, u16 iperiod) -+{ -+ qm_out(ITPR, iperiod); -+} -+ -+static inline u32 __qm_isr_read(struct qm_portal *portal, enum qm_isr_reg n) -+{ -+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) -+ return __qm_in(&portal->addr, QM_REG_ISR + (n << 6)); -+#else -+ return __qm_in(&portal->addr, QM_REG_ISR + (n << 2)); -+#endif -+} -+ -+static inline void __qm_isr_write(struct qm_portal *portal, enum qm_isr_reg n, -+ u32 val) -+{ -+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) -+ __qm_out(&portal->addr, QM_REG_ISR + (n << 6), val); -+#else -+ __qm_out(&portal->addr, QM_REG_ISR + (n << 2), val); -+#endif -+} -+ -+/* Cleanup FQs */ -+static inline int qm_shutdown_fq(struct qm_portal **portal, int portal_count, -+ u32 fqid) -+{ -+ -+ struct qm_mc_command *mcc; -+ struct qm_mc_result *mcr; -+ u8 state; -+ int orl_empty, fq_empty, i, drain = 0; -+ u32 result; -+ u32 channel, wq; -+ u16 dest_wq; -+ -+ /* Determine the state of the FQID */ -+ mcc = qm_mc_start(portal[0]); -+ mcc->queryfq_np.fqid = cpu_to_be32(fqid); -+ qm_mc_commit(portal[0], QM_MCC_VERB_QUERYFQ_NP); -+ while (!(mcr = qm_mc_result(portal[0]))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP); -+ state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK; -+ if (state == QM_MCR_NP_STATE_OOS) -+ return 0; /* Already OOS, no need to do anymore checks */ -+ -+ /* Query which channel the FQ is using */ -+ mcc = qm_mc_start(portal[0]); -+ mcc->queryfq.fqid = cpu_to_be32(fqid); -+ qm_mc_commit(portal[0], QM_MCC_VERB_QUERYFQ); -+ while (!(mcr = qm_mc_result(portal[0]))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ); -+ -+ /* Need to store these since the MCR gets reused */ -+ dest_wq = be16_to_cpu(mcr->queryfq.fqd.dest_wq); -+ wq = dest_wq & 0x7; -+ channel = dest_wq>>3; -+ -+ switch (state) { -+ case QM_MCR_NP_STATE_TEN_SCHED: -+ case QM_MCR_NP_STATE_TRU_SCHED: -+ case QM_MCR_NP_STATE_ACTIVE: -+ case QM_MCR_NP_STATE_PARKED: -+ orl_empty = 0; -+ mcc = qm_mc_start(portal[0]); -+ mcc->alterfq.fqid = cpu_to_be32(fqid); -+ qm_mc_commit(portal[0], QM_MCC_VERB_ALTER_RETIRE); -+ while (!(mcr = qm_mc_result(portal[0]))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == -+ QM_MCR_VERB_ALTER_RETIRE); -+ result = mcr->result; /* Make a copy as we reuse MCR below */ -+ -+ if (result == QM_MCR_RESULT_PENDING) { -+ /* Need to wait for the FQRN in the message ring, which -+ will only occur once the FQ has been drained. In -+ order for the FQ to drain the portal needs to be set -+ to dequeue from the channel the FQ is scheduled on */ -+ const struct qm_mr_entry *msg; -+ const struct qm_dqrr_entry *dqrr = NULL; -+ int found_fqrn = 0; -+ u16 dequeue_wq = 0; -+ -+ /* Flag that we need to drain FQ */ -+ drain = 1; -+ -+ if (channel >= qm_channel_pool1 && -+ channel < (qm_channel_pool1 + 15)) { -+ /* Pool channel, enable the bit in the portal */ -+ dequeue_wq = (channel - -+ qm_channel_pool1 + 1)<<4 | wq; -+ } else if (channel < qm_channel_pool1) { -+ /* Dedicated channel */ -+ dequeue_wq = wq; -+ } else { -+ pr_info("Cannot recover FQ 0x%x, it is " -+ "scheduled on channel 0x%x", -+ fqid, channel); -+ return -EBUSY; -+ } -+ /* Set the sdqcr to drain this channel */ -+ if (channel < qm_channel_pool1) -+ for (i = 0; i < portal_count; i++) -+ qm_dqrr_sdqcr_set(portal[i], -+ QM_SDQCR_TYPE_ACTIVE | -+ QM_SDQCR_CHANNELS_DEDICATED); -+ else -+ for (i = 0; i < portal_count; i++) -+ qm_dqrr_sdqcr_set( -+ portal[i], -+ QM_SDQCR_TYPE_ACTIVE | -+ QM_SDQCR_CHANNELS_POOL_CONV -+ (channel)); -+ while (!found_fqrn) { -+ /* Keep draining DQRR while checking the MR*/ -+ for (i = 0; i < portal_count; i++) { -+ qm_dqrr_pvb_update(portal[i]); -+ dqrr = qm_dqrr_current(portal[i]); -+ while (dqrr) { -+ qm_dqrr_cdc_consume_1ptr( -+ portal[i], dqrr, 0); -+ qm_dqrr_pvb_update(portal[i]); -+ qm_dqrr_next(portal[i]); -+ dqrr = qm_dqrr_current( -+ portal[i]); -+ } -+ /* Process message ring too */ -+ qm_mr_pvb_update(portal[i]); -+ msg = qm_mr_current(portal[i]); -+ while (msg) { -+ if ((msg->verb & -+ QM_MR_VERB_TYPE_MASK) -+ == QM_MR_VERB_FQRN) -+ found_fqrn = 1; -+ qm_mr_next(portal[i]); -+ qm_mr_cci_consume_to_current( -+ portal[i]); -+ qm_mr_pvb_update(portal[i]); -+ msg = qm_mr_current(portal[i]); -+ } -+ cpu_relax(); -+ } -+ } -+ } -+ if (result != QM_MCR_RESULT_OK && -+ result != QM_MCR_RESULT_PENDING) { -+ /* error */ -+ pr_err("qman_retire_fq failed on FQ 0x%x, result=0x%x\n", -+ fqid, result); -+ return -1; -+ } -+ if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) { -+ /* ORL had no entries, no need to wait until the -+ ERNs come in */ -+ orl_empty = 1; -+ } -+ /* Retirement succeeded, check to see if FQ needs -+ to be drained */ -+ if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) { -+ /* FQ is Not Empty, drain using volatile DQ commands */ -+ fq_empty = 0; -+ do { -+ const struct qm_dqrr_entry *dqrr = NULL; -+ u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3); -+ qm_dqrr_vdqcr_set(portal[0], vdqcr); -+ -+ /* Wait for a dequeue to occur */ -+ while (dqrr == NULL) { -+ qm_dqrr_pvb_update(portal[0]); -+ dqrr = qm_dqrr_current(portal[0]); -+ if (!dqrr) -+ cpu_relax(); -+ } -+ /* Process the dequeues, making sure to -+ empty the ring completely */ -+ while (dqrr) { -+ if (be32_to_cpu(dqrr->fqid) == fqid && -+ dqrr->stat & QM_DQRR_STAT_FQ_EMPTY) -+ fq_empty = 1; -+ qm_dqrr_cdc_consume_1ptr(portal[0], -+ dqrr, 0); -+ qm_dqrr_pvb_update(portal[0]); -+ qm_dqrr_next(portal[0]); -+ dqrr = qm_dqrr_current(portal[0]); -+ } -+ } while (fq_empty == 0); -+ } -+ for (i = 0; i < portal_count; i++) -+ qm_dqrr_sdqcr_set(portal[i], 0); -+ -+ /* Wait for the ORL to have been completely drained */ -+ while (orl_empty == 0) { -+ const struct qm_mr_entry *msg; -+ qm_mr_pvb_update(portal[0]); -+ msg = qm_mr_current(portal[0]); -+ while (msg) { -+ if ((msg->verb & QM_MR_VERB_TYPE_MASK) == -+ QM_MR_VERB_FQRL) -+ orl_empty = 1; -+ qm_mr_next(portal[0]); -+ qm_mr_cci_consume_to_current(portal[0]); -+ qm_mr_pvb_update(portal[0]); -+ msg = qm_mr_current(portal[0]); -+ } -+ cpu_relax(); -+ } -+ mcc = qm_mc_start(portal[0]); -+ mcc->alterfq.fqid = cpu_to_be32(fqid); -+ qm_mc_commit(portal[0], QM_MCC_VERB_ALTER_OOS); -+ while (!(mcr = qm_mc_result(portal[0]))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == -+ QM_MCR_VERB_ALTER_OOS); -+ if (mcr->result != QM_MCR_RESULT_OK) { -+ pr_err("OOS after drain Failed on FQID 0x%x, result 0x%x\n", -+ fqid, mcr->result); -+ return -1; -+ } -+ return 0; -+ case QM_MCR_NP_STATE_RETIRED: -+ /* Send OOS Command */ -+ mcc = qm_mc_start(portal[0]); -+ mcc->alterfq.fqid = cpu_to_be32(fqid); -+ qm_mc_commit(portal[0], QM_MCC_VERB_ALTER_OOS); -+ while (!(mcr = qm_mc_result(portal[0]))) -+ cpu_relax(); -+ DPA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == -+ QM_MCR_VERB_ALTER_OOS); -+ if (mcr->result) { -+ pr_err("OOS Failed on FQID 0x%x\n", fqid); -+ return -1; -+ } -+ return 0; -+ } -+ return -1; -+} ---- /dev/null -+++ b/drivers/staging/fsl_qbman/qman_private.h -@@ -0,0 +1,398 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "dpa_sys.h" -+#include -+#include -+ -+#if defined(CONFIG_FSL_PAMU) -+#include -+#endif -+ -+#if !defined(CONFIG_FSL_QMAN_FQ_LOOKUP) && defined(CONFIG_PPC64) -+#error "_PPC64 requires _FSL_QMAN_FQ_LOOKUP" -+#endif -+ -+#define QBMAN_ANY_PORTAL_IDX 0xffffffff -+ /* ----------------- */ -+ /* Congestion Groups */ -+ /* ----------------- */ -+/* This wrapper represents a bit-array for the state of the 256 Qman congestion -+ * groups. Is also used as a *mask* for congestion groups, eg. so we ignore -+ * those that don't concern us. We harness the structure and accessor details -+ * already used in the management command to query congestion groups. */ -+struct qman_cgrs { -+ struct __qm_mcr_querycongestion q; -+}; -+static inline void qman_cgrs_init(struct qman_cgrs *c) -+{ -+ memset(c, 0, sizeof(*c)); -+} -+static inline void qman_cgrs_fill(struct qman_cgrs *c) -+{ -+ memset(c, 0xff, sizeof(*c)); -+} -+static inline int qman_cgrs_get(struct qman_cgrs *c, int num) -+{ -+ return QM_MCR_QUERYCONGESTION(&c->q, num); -+} -+static inline void qman_cgrs_set(struct qman_cgrs *c, int num) -+{ -+ c->q.__state[__CGR_WORD(num)] |= (0x80000000 >> __CGR_SHIFT(num)); -+} -+static inline void qman_cgrs_unset(struct qman_cgrs *c, int num) -+{ -+ c->q.__state[__CGR_WORD(num)] &= ~(0x80000000 >> __CGR_SHIFT(num)); -+} -+static inline int qman_cgrs_next(struct qman_cgrs *c, int num) -+{ -+ while ((++num < __CGR_NUM) && !qman_cgrs_get(c, num)) -+ ; -+ return num; -+} -+static inline void qman_cgrs_cp(struct qman_cgrs *dest, -+ const struct qman_cgrs *src) -+{ -+ *dest = *src; -+} -+static inline void qman_cgrs_and(struct qman_cgrs *dest, -+ const struct qman_cgrs *a, const struct qman_cgrs *b) -+{ -+ int ret; -+ u32 *_d = dest->q.__state; -+ const u32 *_a = a->q.__state; -+ const u32 *_b = b->q.__state; -+ for (ret = 0; ret < 8; ret++) -+ *(_d++) = *(_a++) & *(_b++); -+} -+static inline void qman_cgrs_xor(struct qman_cgrs *dest, -+ const struct qman_cgrs *a, const struct qman_cgrs *b) -+{ -+ int ret; -+ u32 *_d = dest->q.__state; -+ const u32 *_a = a->q.__state; -+ const u32 *_b = b->q.__state; -+ for (ret = 0; ret < 8; ret++) -+ *(_d++) = *(_a++) ^ *(_b++); -+} -+ -+ /* ----------------------- */ -+ /* CEETM Congestion Groups */ -+ /* ----------------------- */ -+/* This wrapper represents a bit-array for the state of the 512 Qman CEETM -+ * congestion groups. -+ */ -+struct qman_ccgrs { -+ struct __qm_mcr_querycongestion q[2]; -+}; -+static inline void qman_ccgrs_init(struct qman_ccgrs *c) -+{ -+ memset(c, 0, sizeof(*c)); -+} -+static inline void qman_ccgrs_fill(struct qman_ccgrs *c) -+{ -+ memset(c, 0xff, sizeof(*c)); -+} -+static inline int qman_ccgrs_get(struct qman_ccgrs *c, int num) -+{ -+ if (num < __CGR_NUM) -+ return QM_MCR_QUERYCONGESTION(&c->q[0], num); -+ else -+ return QM_MCR_QUERYCONGESTION(&c->q[1], (num - __CGR_NUM)); -+} -+static inline int qman_ccgrs_next(struct qman_ccgrs *c, int num) -+{ -+ while ((++num < __CGR_NUM) && !qman_ccgrs_get(c, num)) -+ ; -+ return num; -+} -+static inline void qman_ccgrs_cp(struct qman_ccgrs *dest, -+ const struct qman_ccgrs *src) -+{ -+ *dest = *src; -+} -+static inline void qman_ccgrs_and(struct qman_ccgrs *dest, -+ const struct qman_ccgrs *a, const struct qman_ccgrs *b) -+{ -+ int ret, i; -+ u32 *_d; -+ const u32 *_a, *_b; -+ for (i = 0; i < 2; i++) { -+ _d = dest->q[i].__state; -+ _a = a->q[i].__state; -+ _b = b->q[i].__state; -+ for (ret = 0; ret < 8; ret++) -+ *(_d++) = *(_a++) & *(_b++); -+ } -+} -+static inline void qman_ccgrs_xor(struct qman_ccgrs *dest, -+ const struct qman_ccgrs *a, const struct qman_ccgrs *b) -+{ -+ int ret, i; -+ u32 *_d; -+ const u32 *_a, *_b; -+ for (i = 0; i < 2; i++) { -+ _d = dest->q[i].__state; -+ _a = a->q[i].__state; -+ _b = b->q[i].__state; -+ for (ret = 0; ret < 8; ret++) -+ *(_d++) = *(_a++) ^ *(_b++); -+ } -+} -+ -+/* used by CCSR and portal interrupt code */ -+enum qm_isr_reg { -+ qm_isr_status = 0, -+ qm_isr_enable = 1, -+ qm_isr_disable = 2, -+ qm_isr_inhibit = 3 -+}; -+ -+struct qm_portal_config { -+ /* Corenet portal addresses; -+ * [0]==cache-enabled, [1]==cache-inhibited. */ -+ __iomem void *addr_virt[2]; -+ struct resource addr_phys[2]; -+ struct device dev; -+ struct iommu_domain *iommu_domain; -+ /* Allow these to be joined in lists */ -+ struct list_head list; -+ /* User-visible portal configuration settings */ -+ struct qman_portal_config public_cfg; -+ /* power management saved data */ -+ u32 saved_isdr; -+}; -+ -+/* Revision info (for errata and feature handling) */ -+#define QMAN_REV11 0x0101 -+#define QMAN_REV12 0x0102 -+#define QMAN_REV20 0x0200 -+#define QMAN_REV30 0x0300 -+#define QMAN_REV31 0x0301 -+#define QMAN_REV32 0x0302 -+ -+/* QMan REV_2 register contains the Cfg option */ -+#define QMAN_REV_CFG_0 0x0 -+#define QMAN_REV_CFG_1 0x1 -+#define QMAN_REV_CFG_2 0x2 -+#define QMAN_REV_CFG_3 0x3 -+ -+extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */ -+extern u8 qman_ip_cfg; -+extern u32 qman_clk; -+extern u16 qman_portal_max; -+ -+#ifdef CONFIG_FSL_QMAN_CONFIG -+/* Hooks from qman_driver.c to qman_config.c */ -+int qman_init_ccsr(struct device_node *node); -+void qman_liodn_fixup(u16 channel); -+int qman_set_sdest(u16 channel, unsigned int cpu_idx); -+size_t get_qman_fqd_size(void); -+#else -+static inline size_t get_qman_fqd_size(void) -+{ -+ return (PAGE_SIZE << CONFIG_FSL_QMAN_FQD_SZ); -+} -+#endif -+ -+int qm_set_wpm(int wpm); -+int qm_get_wpm(int *wpm); -+ -+/* Hooks from qman_driver.c in to qman_high.c */ -+struct qman_portal *qman_create_portal( -+ struct qman_portal *portal, -+ const struct qm_portal_config *config, -+ const struct qman_cgrs *cgrs); -+ -+struct qman_portal *qman_create_affine_portal( -+ const struct qm_portal_config *config, -+ const struct qman_cgrs *cgrs); -+struct qman_portal *qman_create_affine_slave(struct qman_portal *redirect, -+ int cpu); -+const struct qm_portal_config *qman_destroy_affine_portal(void); -+void qman_destroy_portal(struct qman_portal *qm); -+ -+/* Hooks from fsl_usdpaa.c to qman_driver.c */ -+struct qm_portal_config *qm_get_unused_portal(void); -+struct qm_portal_config *qm_get_unused_portal_idx(uint32_t idx); -+ -+void qm_put_unused_portal(struct qm_portal_config *pcfg); -+void qm_set_liodns(struct qm_portal_config *pcfg); -+ -+/* This CGR feature is supported by h/w and required by unit-tests and the -+ * debugfs hooks, so is implemented in the driver. However it allows an explicit -+ * corruption of h/w fields by s/w that are usually incorruptible (because the -+ * counters are usually maintained entirely within h/w). As such, we declare -+ * this API internally. */ -+int qman_testwrite_cgr(struct qman_cgr *cgr, u64 i_bcnt, -+ struct qm_mcr_cgrtestwrite *result); -+ -+#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP -+/* If the fq object pointer is greater than the size of context_b field, -+ * than a lookup table is required. */ -+int qman_setup_fq_lookup_table(size_t num_entries); -+#endif -+ -+ -+/*************************************************/ -+/* QMan s/w corenet portal, low-level i/face */ -+/*************************************************/ -+ -+/* Note: most functions are only used by the high-level interface, so are -+ * inlined from qman_low.h. The stuff below is for use by other parts of the -+ * driver. */ -+ -+/* For qm_dqrr_sdqcr_set(); Choose one SOURCE. Choose one COUNT. Choose one -+ * dequeue TYPE. Choose TOKEN (8-bit). -+ * If SOURCE == CHANNELS, -+ * Choose CHANNELS_DEDICATED and/or CHANNELS_POOL(n). -+ * You can choose DEDICATED_PRECEDENCE if the portal channel should have -+ * priority. -+ * If SOURCE == SPECIFICWQ, -+ * Either select the work-queue ID with SPECIFICWQ_WQ(), or select the -+ * channel (SPECIFICWQ_DEDICATED or SPECIFICWQ_POOL()) and specify the -+ * work-queue priority (0-7) with SPECIFICWQ_WQ() - either way, you get the -+ * same value. -+ */ -+#define QM_SDQCR_SOURCE_CHANNELS 0x0 -+#define QM_SDQCR_SOURCE_SPECIFICWQ 0x40000000 -+#define QM_SDQCR_COUNT_EXACT1 0x0 -+#define QM_SDQCR_COUNT_UPTO3 0x20000000 -+#define QM_SDQCR_DEDICATED_PRECEDENCE 0x10000000 -+#define QM_SDQCR_TYPE_MASK 0x03000000 -+#define QM_SDQCR_TYPE_NULL 0x0 -+#define QM_SDQCR_TYPE_PRIO_QOS 0x01000000 -+#define QM_SDQCR_TYPE_ACTIVE_QOS 0x02000000 -+#define QM_SDQCR_TYPE_ACTIVE 0x03000000 -+#define QM_SDQCR_TOKEN_MASK 0x00ff0000 -+#define QM_SDQCR_TOKEN_SET(v) (((v) & 0xff) << 16) -+#define QM_SDQCR_TOKEN_GET(v) (((v) >> 16) & 0xff) -+#define QM_SDQCR_CHANNELS_DEDICATED 0x00008000 -+#define QM_SDQCR_SPECIFICWQ_MASK 0x000000f7 -+#define QM_SDQCR_SPECIFICWQ_DEDICATED 0x00000000 -+#define QM_SDQCR_SPECIFICWQ_POOL(n) ((n) << 4) -+#define QM_SDQCR_SPECIFICWQ_WQ(n) (n) -+ -+/* For qm_dqrr_vdqcr_set(): use FQID(n) to fill in the frame queue ID */ -+#define QM_VDQCR_FQID_MASK 0x00ffffff -+#define QM_VDQCR_FQID(n) ((n) & QM_VDQCR_FQID_MASK) -+ -+/* For qm_dqrr_pdqcr_set(); Choose one MODE. Choose one COUNT. -+ * If MODE==SCHEDULED -+ * Choose SCHEDULED_CHANNELS or SCHEDULED_SPECIFICWQ. Choose one dequeue TYPE. -+ * If CHANNELS, -+ * Choose CHANNELS_DEDICATED and/or CHANNELS_POOL() channels. -+ * You can choose DEDICATED_PRECEDENCE if the portal channel should have -+ * priority. -+ * If SPECIFICWQ, -+ * Either select the work-queue ID with SPECIFICWQ_WQ(), or select the -+ * channel (SPECIFICWQ_DEDICATED or SPECIFICWQ_POOL()) and specify the -+ * work-queue priority (0-7) with SPECIFICWQ_WQ() - either way, you get the -+ * same value. -+ * If MODE==UNSCHEDULED -+ * Choose FQID(). -+ */ -+#define QM_PDQCR_MODE_SCHEDULED 0x0 -+#define QM_PDQCR_MODE_UNSCHEDULED 0x80000000 -+#define QM_PDQCR_SCHEDULED_CHANNELS 0x0 -+#define QM_PDQCR_SCHEDULED_SPECIFICWQ 0x40000000 -+#define QM_PDQCR_COUNT_EXACT1 0x0 -+#define QM_PDQCR_COUNT_UPTO3 0x20000000 -+#define QM_PDQCR_DEDICATED_PRECEDENCE 0x10000000 -+#define QM_PDQCR_TYPE_MASK 0x03000000 -+#define QM_PDQCR_TYPE_NULL 0x0 -+#define QM_PDQCR_TYPE_PRIO_QOS 0x01000000 -+#define QM_PDQCR_TYPE_ACTIVE_QOS 0x02000000 -+#define QM_PDQCR_TYPE_ACTIVE 0x03000000 -+#define QM_PDQCR_CHANNELS_DEDICATED 0x00008000 -+#define QM_PDQCR_CHANNELS_POOL(n) (0x00008000 >> (n)) -+#define QM_PDQCR_SPECIFICWQ_MASK 0x000000f7 -+#define QM_PDQCR_SPECIFICWQ_DEDICATED 0x00000000 -+#define QM_PDQCR_SPECIFICWQ_POOL(n) ((n) << 4) -+#define QM_PDQCR_SPECIFICWQ_WQ(n) (n) -+#define QM_PDQCR_FQID(n) ((n) & 0xffffff) -+ -+/* Used by all portal interrupt registers except 'inhibit' -+ * Channels with frame availability -+ */ -+#define QM_PIRQ_DQAVAIL 0x0000ffff -+ -+/* The DQAVAIL interrupt fields break down into these bits; */ -+#define QM_DQAVAIL_PORTAL 0x8000 /* Portal channel */ -+#define QM_DQAVAIL_POOL(n) (0x8000 >> (n)) /* Pool channel, n==[1..15] */ -+#define QM_DQAVAIL_MASK 0xffff -+/* This mask contains all the "irqsource" bits visible to API users */ -+#define QM_PIRQ_VISIBLE (QM_PIRQ_SLOW | QM_PIRQ_DQRI) -+ -+/* These are qm__(). So for example, qm_disable_write() means "write -+ * the disable register" rather than "disable the ability to write". */ -+#define qm_isr_status_read(qm) __qm_isr_read(qm, qm_isr_status) -+#define qm_isr_status_clear(qm, m) __qm_isr_write(qm, qm_isr_status, m) -+#define qm_isr_enable_read(qm) __qm_isr_read(qm, qm_isr_enable) -+#define qm_isr_enable_write(qm, v) __qm_isr_write(qm, qm_isr_enable, v) -+#define qm_isr_disable_read(qm) __qm_isr_read(qm, qm_isr_disable) -+#define qm_isr_disable_write(qm, v) __qm_isr_write(qm, qm_isr_disable, v) -+/* TODO: unfortunate name-clash here, reword? */ -+#define qm_isr_inhibit(qm) __qm_isr_write(qm, qm_isr_inhibit, 1) -+#define qm_isr_uninhibit(qm) __qm_isr_write(qm, qm_isr_inhibit, 0) -+ -+#ifdef CONFIG_FSL_QMAN_CONFIG -+int qman_have_ccsr(void); -+#else -+#define qman_have_ccsr 0 -+#endif -+ -+__init int qman_init(void); -+__init int qman_resource_init(void); -+ -+/* CEETM related */ -+#define QMAN_CEETM_MAX 2 -+extern u8 num_ceetms; -+extern struct qm_ceetm qman_ceetms[QMAN_CEETM_MAX]; -+int qman_sp_enable_ceetm_mode(enum qm_dc_portal portal, u16 sub_portal); -+int qman_sp_disable_ceetm_mode(enum qm_dc_portal portal, u16 sub_portal); -+int qman_ceetm_set_prescaler(enum qm_dc_portal portal); -+int qman_ceetm_get_prescaler(u16 *pres); -+int qman_ceetm_query_cq(unsigned int cqid, unsigned int dcpid, -+ struct qm_mcr_ceetm_cq_query *cq_query); -+int qman_ceetm_query_ccgr(struct qm_mcc_ceetm_ccgr_query *ccgr_query, -+ struct qm_mcr_ceetm_ccgr_query *response); -+int qman_ceetm_get_xsfdr(enum qm_dc_portal portal, unsigned int *num); -+ -+extern void *affine_portals[NR_CPUS]; -+const struct qm_portal_config *qman_get_qm_portal_config( -+ struct qman_portal *portal); -+ -+/* power management */ -+#ifdef CONFIG_SUSPEND -+void suspend_unused_qportal(void); -+void resume_unused_qportal(void); -+#endif ---- /dev/null -+++ b/drivers/staging/fsl_qbman/qman_test.c -@@ -0,0 +1,57 @@ -+/* Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "qman_test.h" -+ -+MODULE_AUTHOR("Geoff Thorpe"); -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("Qman testing"); -+ -+static int test_init(void) -+{ -+ int loop = 1; -+ while (loop--) { -+#ifdef CONFIG_FSL_QMAN_TEST_STASH_POTATO -+ qman_test_hotpotato(); -+#endif -+#ifdef CONFIG_FSL_QMAN_TEST_HIGH -+ qman_test_high(); -+#endif -+ } -+ return 0; -+} -+ -+static void test_exit(void) -+{ -+} -+ -+module_init(test_init); -+module_exit(test_exit); ---- /dev/null -+++ b/drivers/staging/fsl_qbman/qman_test.h -@@ -0,0 +1,45 @@ -+/* Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+void qman_test_hotpotato(void); -+void qman_test_high(void); -+ ---- /dev/null -+++ b/drivers/staging/fsl_qbman/qman_test_high.c -@@ -0,0 +1,216 @@ -+/* Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "qman_test.h" -+ -+/*************/ -+/* constants */ -+/*************/ -+ -+#define CGR_ID 27 -+#define POOL_ID 2 -+#define FQ_FLAGS QMAN_FQ_FLAG_DYNAMIC_FQID -+#define NUM_ENQUEUES 10 -+#define NUM_PARTIAL 4 -+#define PORTAL_SDQCR (QM_SDQCR_SOURCE_CHANNELS | \ -+ QM_SDQCR_TYPE_PRIO_QOS | \ -+ QM_SDQCR_TOKEN_SET(0x98) | \ -+ QM_SDQCR_CHANNELS_DEDICATED | \ -+ QM_SDQCR_CHANNELS_POOL(POOL_ID)) -+#define PORTAL_OPAQUE ((void *)0xf00dbeef) -+#define VDQCR_FLAGS (QMAN_VOLATILE_FLAG_WAIT | QMAN_VOLATILE_FLAG_FINISH) -+ -+/*************************************/ -+/* Predeclarations (eg. for fq_base) */ -+/*************************************/ -+ -+static enum qman_cb_dqrr_result cb_dqrr(struct qman_portal *, -+ struct qman_fq *, -+ const struct qm_dqrr_entry *); -+static void cb_ern(struct qman_portal *, struct qman_fq *, -+ const struct qm_mr_entry *); -+static void cb_fqs(struct qman_portal *, struct qman_fq *, -+ const struct qm_mr_entry *); -+ -+/***************/ -+/* global vars */ -+/***************/ -+ -+static struct qm_fd fd, fd_dq; -+static struct qman_fq fq_base = { -+ .cb.dqrr = cb_dqrr, -+ .cb.ern = cb_ern, -+ .cb.fqs = cb_fqs -+}; -+static DECLARE_WAIT_QUEUE_HEAD(waitqueue); -+static int retire_complete, sdqcr_complete; -+ -+/**********************/ -+/* internal functions */ -+/**********************/ -+ -+/* Helpers for initialising and "incrementing" a frame descriptor */ -+static void fd_init(struct qm_fd *__fd) -+{ -+ qm_fd_addr_set64(__fd, 0xabdeadbeefLLU); -+ __fd->format = qm_fd_contig_big; -+ __fd->length29 = 0x0000ffff; -+ __fd->cmd = 0xfeedf00d; -+} -+ -+static void fd_inc(struct qm_fd *__fd) -+{ -+ u64 t = qm_fd_addr_get64(__fd); -+ int z = t >> 40; -+ t <<= 1; -+ if (z) -+ t |= 1; -+ qm_fd_addr_set64(__fd, t); -+ __fd->length29--; -+ __fd->cmd++; -+} -+ -+/* The only part of the 'fd' we can't memcmp() is the ppid */ -+static int fd_cmp(const struct qm_fd *a, const struct qm_fd *b) -+{ -+ int r = (qm_fd_addr_get64(a) == qm_fd_addr_get64(b)) ? 0 : -1; -+ if (!r) -+ r = a->format - b->format; -+ if (!r) -+ r = a->opaque - b->opaque; -+ if (!r) -+ r = a->cmd - b->cmd; -+ return r; -+} -+ -+/********/ -+/* test */ -+/********/ -+ -+static void do_enqueues(struct qman_fq *fq) -+{ -+ unsigned int loop; -+ for (loop = 0; loop < NUM_ENQUEUES; loop++) { -+ if (qman_enqueue(fq, &fd, QMAN_ENQUEUE_FLAG_WAIT | -+ (((loop + 1) == NUM_ENQUEUES) ? -+ QMAN_ENQUEUE_FLAG_WAIT_SYNC : 0))) -+ panic("qman_enqueue() failed\n"); -+ fd_inc(&fd); -+ } -+} -+ -+void qman_test_high(void) -+{ -+ unsigned int flags; -+ int res; -+ struct qman_fq *fq = &fq_base; -+ -+ pr_info("qman_test_high starting\n"); -+ fd_init(&fd); -+ fd_init(&fd_dq); -+ -+ /* Initialise (parked) FQ */ -+ if (qman_create_fq(0, FQ_FLAGS, fq)) -+ panic("qman_create_fq() failed\n"); -+ if (qman_init_fq(fq, QMAN_INITFQ_FLAG_LOCAL, NULL)) -+ panic("qman_init_fq() failed\n"); -+ -+ /* Do enqueues + VDQCR, twice. (Parked FQ) */ -+ do_enqueues(fq); -+ pr_info("VDQCR (till-empty);\n"); -+ if (qman_volatile_dequeue(fq, VDQCR_FLAGS, -+ QM_VDQCR_NUMFRAMES_TILLEMPTY)) -+ panic("qman_volatile_dequeue() failed\n"); -+ do_enqueues(fq); -+ pr_info("VDQCR (%d of %d);\n", NUM_PARTIAL, NUM_ENQUEUES); -+ if (qman_volatile_dequeue(fq, VDQCR_FLAGS, -+ QM_VDQCR_NUMFRAMES_SET(NUM_PARTIAL))) -+ panic("qman_volatile_dequeue() failed\n"); -+ pr_info("VDQCR (%d of %d);\n", NUM_ENQUEUES - NUM_PARTIAL, -+ NUM_ENQUEUES); -+ if (qman_volatile_dequeue(fq, VDQCR_FLAGS, -+ QM_VDQCR_NUMFRAMES_SET(NUM_ENQUEUES - NUM_PARTIAL))) -+ panic("qman_volatile_dequeue() failed\n"); -+ -+ do_enqueues(fq); -+ pr_info("scheduled dequeue (till-empty)\n"); -+ if (qman_schedule_fq(fq)) -+ panic("qman_schedule_fq() failed\n"); -+ wait_event(waitqueue, sdqcr_complete); -+ -+ /* Retire and OOS the FQ */ -+ res = qman_retire_fq(fq, &flags); -+ if (res < 0) -+ panic("qman_retire_fq() failed\n"); -+ wait_event(waitqueue, retire_complete); -+ if (flags & QMAN_FQ_STATE_BLOCKOOS) -+ panic("leaking frames\n"); -+ if (qman_oos_fq(fq)) -+ panic("qman_oos_fq() failed\n"); -+ qman_destroy_fq(fq, 0); -+ pr_info("qman_test_high finished\n"); -+} -+ -+static enum qman_cb_dqrr_result cb_dqrr(struct qman_portal *p, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dq) -+{ -+ if (fd_cmp(&fd_dq, &dq->fd)) { -+ pr_err("BADNESS: dequeued frame doesn't match;\n"); -+ pr_err("Expected 0x%llx, got 0x%llx\n", -+ (unsigned long long)fd_dq.length29, -+ (unsigned long long)dq->fd.length29); -+ BUG(); -+ } -+ fd_inc(&fd_dq); -+ if (!(dq->stat & QM_DQRR_STAT_UNSCHEDULED) && !fd_cmp(&fd_dq, &fd)) { -+ sdqcr_complete = 1; -+ wake_up(&waitqueue); -+ } -+ return qman_cb_dqrr_consume; -+} -+ -+static void cb_ern(struct qman_portal *p, struct qman_fq *fq, -+ const struct qm_mr_entry *msg) -+{ -+ panic("cb_ern() unimplemented"); -+} -+ -+static void cb_fqs(struct qman_portal *p, struct qman_fq *fq, -+ const struct qm_mr_entry *msg) -+{ -+ u8 verb = (msg->verb & QM_MR_VERB_TYPE_MASK); -+ if ((verb != QM_MR_VERB_FQRN) && (verb != QM_MR_VERB_FQRNI)) -+ panic("unexpected FQS message"); -+ pr_info("Retirement message received\n"); -+ retire_complete = 1; -+ wake_up(&waitqueue); -+} ---- /dev/null -+++ b/drivers/staging/fsl_qbman/qman_test_hotpotato.c -@@ -0,0 +1,499 @@ -+/* Copyright 2009-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include "qman_test.h" -+ -+/* Algorithm: -+ * -+ * Each cpu will have HP_PER_CPU "handlers" set up, each of which incorporates -+ * an rx/tx pair of FQ objects (both of which are stashed on dequeue). The -+ * organisation of FQIDs is such that the HP_PER_CPU*NUM_CPUS handlers will -+ * shuttle a "hot potato" frame around them such that every forwarding action -+ * moves it from one cpu to another. (The use of more than one handler per cpu -+ * is to allow enough handlers/FQs to truly test the significance of caching - -+ * ie. when cache-expiries are occurring.) -+ * -+ * The "hot potato" frame content will be HP_NUM_WORDS*4 bytes in size, and the -+ * first and last words of the frame data will undergo a transformation step on -+ * each forwarding action. To achieve this, each handler will be assigned a -+ * 32-bit "mixer", that is produced using a 32-bit LFSR. When a frame is -+ * received by a handler, the mixer of the expected sender is XOR'd into all -+ * words of the entire frame, which is then validated against the original -+ * values. Then, before forwarding, the entire frame is XOR'd with the mixer of -+ * the current handler. Apart from validating that the frame is taking the -+ * expected path, this also provides some quasi-realistic overheads to each -+ * forwarding action - dereferencing *all* the frame data, computation, and -+ * conditional branching. There is a "special" handler designated to act as the -+ * instigator of the test by creating an enqueuing the "hot potato" frame, and -+ * to determine when the test has completed by counting HP_LOOPS iterations. -+ * -+ * Init phases: -+ * -+ * 1. prepare each cpu's 'hp_cpu' struct using on_each_cpu(,,1) and link them -+ * into 'hp_cpu_list'. Specifically, set processor_id, allocate HP_PER_CPU -+ * handlers and link-list them (but do no other handler setup). -+ * -+ * 2. scan over 'hp_cpu_list' HP_PER_CPU times, the first time sets each -+ * hp_cpu's 'iterator' to point to its first handler. With each loop, -+ * allocate rx/tx FQIDs and mixer values to the hp_cpu's iterator handler -+ * and advance the iterator for the next loop. This includes a final fixup, -+ * which connects the last handler to the first (and which is why phase 2 -+ * and 3 are separate). -+ * -+ * 3. scan over 'hp_cpu_list' HP_PER_CPU times, the first time sets each -+ * hp_cpu's 'iterator' to point to its first handler. With each loop, -+ * initialise FQ objects and advance the iterator for the next loop. -+ * Moreover, do this initialisation on the cpu it applies to so that Rx FQ -+ * initialisation targets the correct cpu. -+ */ -+ -+/* helper to run something on all cpus (can't use on_each_cpu(), as that invokes -+ * the fn from irq context, which is too restrictive). */ -+struct bstrap { -+ void (*fn)(void); -+ atomic_t started; -+}; -+static int bstrap_fn(void *__bstrap) -+{ -+ struct bstrap *bstrap = __bstrap; -+ atomic_inc(&bstrap->started); -+ bstrap->fn(); -+ while (!kthread_should_stop()) -+ msleep(1); -+ return 0; -+} -+static int on_all_cpus(void (*fn)(void)) -+{ -+ int cpu; -+ for_each_cpu(cpu, cpu_online_mask) { -+ struct bstrap bstrap = { -+ .fn = fn, -+ .started = ATOMIC_INIT(0) -+ }; -+ struct task_struct *k = kthread_create(bstrap_fn, &bstrap, -+ "hotpotato%d", cpu); -+ int ret; -+ if (IS_ERR(k)) -+ return -ENOMEM; -+ kthread_bind(k, cpu); -+ wake_up_process(k); -+ /* If we call kthread_stop() before the "wake up" has had an -+ * effect, then the thread may exit with -EINTR without ever -+ * running the function. So poll until it's started before -+ * requesting it to stop. */ -+ while (!atomic_read(&bstrap.started)) -+ msleep(10); -+ ret = kthread_stop(k); -+ if (ret) -+ return ret; -+ } -+ return 0; -+} -+ -+struct hp_handler { -+ -+ /* The following data is stashed when 'rx' is dequeued; */ -+ /* -------------- */ -+ /* The Rx FQ, dequeues of which will stash the entire hp_handler */ -+ struct qman_fq rx; -+ /* The Tx FQ we should forward to */ -+ struct qman_fq tx; -+ /* The value we XOR post-dequeue, prior to validating */ -+ u32 rx_mixer; -+ /* The value we XOR pre-enqueue, after validating */ -+ u32 tx_mixer; -+ /* what the hotpotato address should be on dequeue */ -+ dma_addr_t addr; -+ u32 *frame_ptr; -+ -+ /* The following data isn't (necessarily) stashed on dequeue; */ -+ /* -------------- */ -+ u32 fqid_rx, fqid_tx; -+ /* list node for linking us into 'hp_cpu' */ -+ struct list_head node; -+ /* Just to check ... */ -+ unsigned int processor_id; -+} ____cacheline_aligned; -+ -+struct hp_cpu { -+ /* identify the cpu we run on; */ -+ unsigned int processor_id; -+ /* root node for the per-cpu list of handlers */ -+ struct list_head handlers; -+ /* list node for linking us into 'hp_cpu_list' */ -+ struct list_head node; -+ /* when repeatedly scanning 'hp_list', each time linking the n'th -+ * handlers together, this is used as per-cpu iterator state */ -+ struct hp_handler *iterator; -+}; -+ -+/* Each cpu has one of these */ -+static DEFINE_PER_CPU(struct hp_cpu, hp_cpus); -+ -+/* links together the hp_cpu structs, in first-come first-serve order. */ -+static LIST_HEAD(hp_cpu_list); -+static spinlock_t hp_lock = __SPIN_LOCK_UNLOCKED(hp_lock); -+ -+static unsigned int hp_cpu_list_length; -+ -+/* the "special" handler, that starts and terminates the test. */ -+static struct hp_handler *special_handler; -+static int loop_counter; -+ -+/* handlers are allocated out of this, so they're properly aligned. */ -+static struct kmem_cache *hp_handler_slab; -+ -+/* this is the frame data */ -+static void *__frame_ptr; -+static u32 *frame_ptr; -+static dma_addr_t frame_dma; -+ -+/* the main function waits on this */ -+static DECLARE_WAIT_QUEUE_HEAD(queue); -+ -+#define HP_PER_CPU 2 -+#define HP_LOOPS 8 -+/* 80 bytes, like a small ethernet frame, and bleeds into a second cacheline */ -+#define HP_NUM_WORDS 80 -+/* First word of the LFSR-based frame data */ -+#define HP_FIRST_WORD 0xabbaf00d -+ -+static inline u32 do_lfsr(u32 prev) -+{ -+ return (prev >> 1) ^ (-(prev & 1u) & 0xd0000001u); -+} -+ -+static void allocate_frame_data(void) -+{ -+ u32 lfsr = HP_FIRST_WORD; -+ int loop; -+ struct platform_device *pdev = platform_device_alloc("foobar", -1); -+ if (!pdev) -+ panic("platform_device_alloc() failed"); -+ if (platform_device_add(pdev)) -+ panic("platform_device_add() failed"); -+ __frame_ptr = kmalloc(4 * HP_NUM_WORDS, GFP_KERNEL); -+ if (!__frame_ptr) -+ panic("kmalloc() failed"); -+ frame_ptr = (void *)(((unsigned long)__frame_ptr + 63) & -+ ~(unsigned long)63); -+ for (loop = 0; loop < HP_NUM_WORDS; loop++) { -+ frame_ptr[loop] = lfsr; -+ lfsr = do_lfsr(lfsr); -+ } -+ frame_dma = dma_map_single(&pdev->dev, frame_ptr, 4 * HP_NUM_WORDS, -+ DMA_BIDIRECTIONAL); -+ platform_device_del(pdev); -+ platform_device_put(pdev); -+} -+ -+static void deallocate_frame_data(void) -+{ -+ kfree(__frame_ptr); -+} -+ -+static inline void process_frame_data(struct hp_handler *handler, -+ const struct qm_fd *fd) -+{ -+ u32 *p = handler->frame_ptr; -+ u32 lfsr = HP_FIRST_WORD; -+ int loop; -+ if (qm_fd_addr_get64(fd) != handler->addr) -+ panic("bad frame address"); -+ for (loop = 0; loop < HP_NUM_WORDS; loop++, p++) { -+ *p ^= handler->rx_mixer; -+ if (*p != lfsr) -+ panic("corrupt frame data"); -+ *p ^= handler->tx_mixer; -+ lfsr = do_lfsr(lfsr); -+ } -+} -+ -+static enum qman_cb_dqrr_result normal_dqrr(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dqrr) -+{ -+ struct hp_handler *handler = (struct hp_handler *)fq; -+ -+ process_frame_data(handler, &dqrr->fd); -+ if (qman_enqueue(&handler->tx, &dqrr->fd, 0)) -+ panic("qman_enqueue() failed"); -+ return qman_cb_dqrr_consume; -+} -+ -+static enum qman_cb_dqrr_result special_dqrr(struct qman_portal *portal, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dqrr) -+{ -+ struct hp_handler *handler = (struct hp_handler *)fq; -+ -+ process_frame_data(handler, &dqrr->fd); -+ if (++loop_counter < HP_LOOPS) { -+ if (qman_enqueue(&handler->tx, &dqrr->fd, 0)) -+ panic("qman_enqueue() failed"); -+ } else { -+ pr_info("Received final (%dth) frame\n", loop_counter); -+ wake_up(&queue); -+ } -+ return qman_cb_dqrr_consume; -+} -+ -+static void create_per_cpu_handlers(void) -+{ -+ struct hp_handler *handler; -+ int loop; -+ struct hp_cpu *hp_cpu = &get_cpu_var(hp_cpus); -+ -+ hp_cpu->processor_id = smp_processor_id(); -+ spin_lock(&hp_lock); -+ list_add_tail(&hp_cpu->node, &hp_cpu_list); -+ hp_cpu_list_length++; -+ spin_unlock(&hp_lock); -+ INIT_LIST_HEAD(&hp_cpu->handlers); -+ for (loop = 0; loop < HP_PER_CPU; loop++) { -+ handler = kmem_cache_alloc(hp_handler_slab, GFP_KERNEL); -+ if (!handler) -+ panic("kmem_cache_alloc() failed"); -+ handler->processor_id = hp_cpu->processor_id; -+ handler->addr = frame_dma; -+ handler->frame_ptr = frame_ptr; -+ list_add_tail(&handler->node, &hp_cpu->handlers); -+ } -+ put_cpu_var(hp_cpus); -+} -+ -+static void destroy_per_cpu_handlers(void) -+{ -+ struct list_head *loop, *tmp; -+ struct hp_cpu *hp_cpu = &get_cpu_var(hp_cpus); -+ -+ spin_lock(&hp_lock); -+ list_del(&hp_cpu->node); -+ spin_unlock(&hp_lock); -+ list_for_each_safe(loop, tmp, &hp_cpu->handlers) { -+ u32 flags; -+ struct hp_handler *handler = list_entry(loop, struct hp_handler, -+ node); -+ if (qman_retire_fq(&handler->rx, &flags)) -+ panic("qman_retire_fq(rx) failed"); -+ BUG_ON(flags & QMAN_FQ_STATE_BLOCKOOS); -+ if (qman_oos_fq(&handler->rx)) -+ panic("qman_oos_fq(rx) failed"); -+ qman_destroy_fq(&handler->rx, 0); -+ qman_destroy_fq(&handler->tx, 0); -+ qman_release_fqid(handler->fqid_rx); -+ list_del(&handler->node); -+ kmem_cache_free(hp_handler_slab, handler); -+ } -+ put_cpu_var(hp_cpus); -+} -+ -+static inline u8 num_cachelines(u32 offset) -+{ -+ u8 res = (offset + (L1_CACHE_BYTES - 1)) -+ / (L1_CACHE_BYTES); -+ if (res > 3) -+ return 3; -+ return res; -+} -+#define STASH_DATA_CL \ -+ num_cachelines(HP_NUM_WORDS * 4) -+#define STASH_CTX_CL \ -+ num_cachelines(offsetof(struct hp_handler, fqid_rx)) -+ -+static void init_handler(void *__handler) -+{ -+ struct qm_mcc_initfq opts; -+ struct hp_handler *handler = __handler; -+ BUG_ON(handler->processor_id != smp_processor_id()); -+ /* Set up rx */ -+ memset(&handler->rx, 0, sizeof(handler->rx)); -+ if (handler == special_handler) -+ handler->rx.cb.dqrr = special_dqrr; -+ else -+ handler->rx.cb.dqrr = normal_dqrr; -+ if (qman_create_fq(handler->fqid_rx, 0, &handler->rx)) -+ panic("qman_create_fq(rx) failed"); -+ memset(&opts, 0, sizeof(opts)); -+ opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; -+ opts.fqd.fq_ctrl = QM_FQCTRL_CTXASTASHING; -+ opts.fqd.context_a.stashing.data_cl = STASH_DATA_CL; -+ opts.fqd.context_a.stashing.context_cl = STASH_CTX_CL; -+ if (qman_init_fq(&handler->rx, QMAN_INITFQ_FLAG_SCHED | -+ QMAN_INITFQ_FLAG_LOCAL, &opts)) -+ panic("qman_init_fq(rx) failed"); -+ /* Set up tx */ -+ memset(&handler->tx, 0, sizeof(handler->tx)); -+ if (qman_create_fq(handler->fqid_tx, QMAN_FQ_FLAG_NO_MODIFY, -+ &handler->tx)) -+ panic("qman_create_fq(tx) failed"); -+} -+ -+static void init_phase2(void) -+{ -+ int loop; -+ u32 fqid = 0; -+ u32 lfsr = 0xdeadbeef; -+ struct hp_cpu *hp_cpu; -+ struct hp_handler *handler; -+ -+ for (loop = 0; loop < HP_PER_CPU; loop++) { -+ list_for_each_entry(hp_cpu, &hp_cpu_list, node) { -+ int ret; -+ if (!loop) -+ hp_cpu->iterator = list_first_entry( -+ &hp_cpu->handlers, -+ struct hp_handler, node); -+ else -+ hp_cpu->iterator = list_entry( -+ hp_cpu->iterator->node.next, -+ struct hp_handler, node); -+ /* Rx FQID is the previous handler's Tx FQID */ -+ hp_cpu->iterator->fqid_rx = fqid; -+ /* Allocate new FQID for Tx */ -+ ret = qman_alloc_fqid(&fqid); -+ if (ret) -+ panic("qman_alloc_fqid() failed"); -+ hp_cpu->iterator->fqid_tx = fqid; -+ /* Rx mixer is the previous handler's Tx mixer */ -+ hp_cpu->iterator->rx_mixer = lfsr; -+ /* Get new mixer for Tx */ -+ lfsr = do_lfsr(lfsr); -+ hp_cpu->iterator->tx_mixer = lfsr; -+ } -+ } -+ /* Fix up the first handler (fqid_rx==0, rx_mixer=0xdeadbeef) */ -+ hp_cpu = list_first_entry(&hp_cpu_list, struct hp_cpu, node); -+ handler = list_first_entry(&hp_cpu->handlers, struct hp_handler, node); -+ BUG_ON((handler->fqid_rx != 0) || (handler->rx_mixer != 0xdeadbeef)); -+ handler->fqid_rx = fqid; -+ handler->rx_mixer = lfsr; -+ /* and tag it as our "special" handler */ -+ special_handler = handler; -+} -+ -+static void init_phase3(void) -+{ -+ int loop; -+ struct hp_cpu *hp_cpu; -+ -+ for (loop = 0; loop < HP_PER_CPU; loop++) { -+ list_for_each_entry(hp_cpu, &hp_cpu_list, node) { -+ if (!loop) -+ hp_cpu->iterator = list_first_entry( -+ &hp_cpu->handlers, -+ struct hp_handler, node); -+ else -+ hp_cpu->iterator = list_entry( -+ hp_cpu->iterator->node.next, -+ struct hp_handler, node); -+ preempt_disable(); -+ if (hp_cpu->processor_id == smp_processor_id()) -+ init_handler(hp_cpu->iterator); -+ else -+ smp_call_function_single(hp_cpu->processor_id, -+ init_handler, hp_cpu->iterator, 1); -+ preempt_enable(); -+ } -+ } -+} -+ -+static void send_first_frame(void *ignore) -+{ -+ u32 *p = special_handler->frame_ptr; -+ u32 lfsr = HP_FIRST_WORD; -+ int loop; -+ struct qm_fd fd; -+ -+ BUG_ON(special_handler->processor_id != smp_processor_id()); -+ memset(&fd, 0, sizeof(fd)); -+ qm_fd_addr_set64(&fd, special_handler->addr); -+ fd.format = qm_fd_contig_big; -+ fd.length29 = HP_NUM_WORDS * 4; -+ for (loop = 0; loop < HP_NUM_WORDS; loop++, p++) { -+ if (*p != lfsr) -+ panic("corrupt frame data"); -+ *p ^= special_handler->tx_mixer; -+ lfsr = do_lfsr(lfsr); -+ } -+ pr_info("Sending first frame\n"); -+ if (qman_enqueue(&special_handler->tx, &fd, 0)) -+ panic("qman_enqueue() failed"); -+} -+ -+void qman_test_hotpotato(void) -+{ -+ if (cpumask_weight(cpu_online_mask) < 2) { -+ pr_info("qman_test_hotpotato, skip - only 1 CPU\n"); -+ return; -+ } -+ -+ pr_info("qman_test_hotpotato starting\n"); -+ -+ hp_cpu_list_length = 0; -+ loop_counter = 0; -+ hp_handler_slab = kmem_cache_create("hp_handler_slab", -+ sizeof(struct hp_handler), L1_CACHE_BYTES, -+ SLAB_HWCACHE_ALIGN, NULL); -+ if (!hp_handler_slab) -+ panic("kmem_cache_create() failed"); -+ -+ allocate_frame_data(); -+ -+ /* Init phase 1 */ -+ pr_info("Creating %d handlers per cpu...\n", HP_PER_CPU); -+ if (on_all_cpus(create_per_cpu_handlers)) -+ panic("on_each_cpu() failed"); -+ pr_info("Number of cpus: %d, total of %d handlers\n", -+ hp_cpu_list_length, hp_cpu_list_length * HP_PER_CPU); -+ -+ init_phase2(); -+ -+ init_phase3(); -+ -+ preempt_disable(); -+ if (special_handler->processor_id == smp_processor_id()) -+ send_first_frame(NULL); -+ else -+ smp_call_function_single(special_handler->processor_id, -+ send_first_frame, NULL, 1); -+ preempt_enable(); -+ -+ wait_event(queue, loop_counter == HP_LOOPS); -+ deallocate_frame_data(); -+ if (on_all_cpus(destroy_per_cpu_handlers)) -+ panic("on_each_cpu() failed"); -+ kmem_cache_destroy(hp_handler_slab); -+ pr_info("qman_test_hotpotato finished\n"); -+} ---- /dev/null -+++ b/drivers/staging/fsl_qbman/qman_utility.c -@@ -0,0 +1,129 @@ -+/* Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "qman_private.h" -+ -+/* ----------------- */ -+/* --- FQID Pool --- */ -+ -+struct qman_fqid_pool { -+ /* Base and size of the FQID range */ -+ u32 fqid_base; -+ u32 total; -+ /* Number of FQIDs currently "allocated" */ -+ u32 used; -+ /* Allocation optimisation. When 'usedfqid_base = fqid_start; -+ pool->total = num; -+ pool->used = 0; -+ pool->next = 0; -+ pool->bits = kzalloc(QNUM_BYTES(num), GFP_KERNEL); -+ if (!pool->bits) { -+ kfree(pool); -+ return NULL; -+ } -+ /* If num is not an even multiple of QLONG_BITS (or even 8, for -+ * byte-oriented searching) then we fill the trailing bits with 1, to -+ * make them look allocated (permanently). */ -+ for (i = num + 1; i < QNUM_BITS(num); i++) -+ set_bit(i, pool->bits); -+ return pool; -+} -+EXPORT_SYMBOL(qman_fqid_pool_create); -+ -+int qman_fqid_pool_destroy(struct qman_fqid_pool *pool) -+{ -+ int ret = pool->used; -+ kfree(pool->bits); -+ kfree(pool); -+ return ret; -+} -+EXPORT_SYMBOL(qman_fqid_pool_destroy); -+ -+int qman_fqid_pool_alloc(struct qman_fqid_pool *pool, u32 *fqid) -+{ -+ int ret; -+ if (pool->used == pool->total) -+ return -ENOMEM; -+ *fqid = pool->fqid_base + pool->next; -+ ret = test_and_set_bit(pool->next, pool->bits); -+ BUG_ON(ret); -+ if (++pool->used == pool->total) -+ return 0; -+ pool->next = find_next_zero_bit(pool->bits, pool->total, pool->next); -+ if (pool->next >= pool->total) -+ pool->next = find_first_zero_bit(pool->bits, pool->total); -+ BUG_ON(pool->next >= pool->total); -+ return 0; -+} -+EXPORT_SYMBOL(qman_fqid_pool_alloc); -+ -+void qman_fqid_pool_free(struct qman_fqid_pool *pool, u32 fqid) -+{ -+ int ret; -+ -+ fqid -= pool->fqid_base; -+ ret = test_and_clear_bit(fqid, pool->bits); -+ BUG_ON(!ret); -+ if (pool->used-- == pool->total) -+ pool->next = fqid; -+} -+EXPORT_SYMBOL(qman_fqid_pool_free); -+ -+u32 qman_fqid_pool_used(struct qman_fqid_pool *pool) -+{ -+ return pool->used; -+} -+EXPORT_SYMBOL(qman_fqid_pool_used); ---- /dev/null -+++ b/include/linux/fsl_bman.h -@@ -0,0 +1,532 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef FSL_BMAN_H -+#define FSL_BMAN_H -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/* Last updated for v00.79 of the BG */ -+ -+/* Portal processing (interrupt) sources */ -+#define BM_PIRQ_RCRI 0x00000002 /* RCR Ring (below threshold) */ -+#define BM_PIRQ_BSCN 0x00000001 /* Buffer depletion State Change */ -+ -+/* This wrapper represents a bit-array for the depletion state of the 64 Bman -+ * buffer pools. */ -+struct bman_depletion { -+ u32 __state[2]; -+}; -+#define BMAN_DEPLETION_EMPTY { { 0x00000000, 0x00000000 } } -+#define BMAN_DEPLETION_FULL { { 0xffffffff, 0xffffffff } } -+#define __bmdep_word(x) ((x) >> 5) -+#define __bmdep_shift(x) ((x) & 0x1f) -+#define __bmdep_bit(x) (0x80000000 >> __bmdep_shift(x)) -+static inline void bman_depletion_init(struct bman_depletion *c) -+{ -+ c->__state[0] = c->__state[1] = 0; -+} -+static inline void bman_depletion_fill(struct bman_depletion *c) -+{ -+ c->__state[0] = c->__state[1] = ~0; -+} -+static inline int bman_depletion_get(const struct bman_depletion *c, u8 bpid) -+{ -+ return c->__state[__bmdep_word(bpid)] & __bmdep_bit(bpid); -+} -+static inline void bman_depletion_set(struct bman_depletion *c, u8 bpid) -+{ -+ c->__state[__bmdep_word(bpid)] |= __bmdep_bit(bpid); -+} -+static inline void bman_depletion_unset(struct bman_depletion *c, u8 bpid) -+{ -+ c->__state[__bmdep_word(bpid)] &= ~__bmdep_bit(bpid); -+} -+ -+/* ------------------------------------------------------- */ -+/* --- Bman data structures (and associated constants) --- */ -+ -+/* Represents s/w corenet portal mapped data structures */ -+struct bm_rcr_entry; /* RCR (Release Command Ring) entries */ -+struct bm_mc_command; /* MC (Management Command) command */ -+struct bm_mc_result; /* MC result */ -+ -+/* Code-reduction, define a wrapper for 48-bit buffers. In cases where a buffer -+ * pool id specific to this buffer is needed (BM_RCR_VERB_CMD_BPID_MULTI, -+ * BM_MCC_VERB_ACQUIRE), the 'bpid' field is used. */ -+struct bm_buffer { -+ union { -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 __reserved1; -+ u8 bpid; -+ u16 hi; /* High 16-bits of 48-bit address */ -+ u32 lo; /* Low 32-bits of 48-bit address */ -+#else -+ u32 lo; -+ u16 hi; -+ u8 bpid; -+ u8 __reserved; -+#endif -+ }; -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u64 __notaddress:16; -+ u64 addr:48; -+#else -+ u64 addr:48; -+ u64 __notaddress:16; -+#endif -+ }; -+ u64 opaque; -+ }; -+} __aligned(8); -+static inline u64 bm_buffer_get64(const struct bm_buffer *buf) -+{ -+ return buf->addr; -+} -+static inline dma_addr_t bm_buf_addr(const struct bm_buffer *buf) -+{ -+ return (dma_addr_t)buf->addr; -+} -+/* Macro, so we compile better if 'v' isn't always 64-bit */ -+#define bm_buffer_set64(buf, v) \ -+ do { \ -+ struct bm_buffer *__buf931 = (buf); \ -+ __buf931->hi = upper_32_bits(v); \ -+ __buf931->lo = lower_32_bits(v); \ -+ } while (0) -+ -+/* See 1.5.3.5.4: "Release Command" */ -+struct bm_rcr_entry { -+ union { -+ struct { -+ u8 __dont_write_directly__verb; -+ u8 bpid; /* used with BM_RCR_VERB_CMD_BPID_SINGLE */ -+ u8 __reserved1[62]; -+ }; -+ struct bm_buffer bufs[8]; -+ }; -+} __packed; -+#define BM_RCR_VERB_VBIT 0x80 -+#define BM_RCR_VERB_CMD_MASK 0x70 /* one of two values; */ -+#define BM_RCR_VERB_CMD_BPID_SINGLE 0x20 -+#define BM_RCR_VERB_CMD_BPID_MULTI 0x30 -+#define BM_RCR_VERB_BUFCOUNT_MASK 0x0f /* values 1..8 */ -+ -+/* See 1.5.3.1: "Acquire Command" */ -+/* See 1.5.3.2: "Query Command" */ -+struct bm_mcc_acquire { -+ u8 bpid; -+ u8 __reserved1[62]; -+} __packed; -+struct bm_mcc_query { -+ u8 __reserved2[63]; -+} __packed; -+struct bm_mc_command { -+ u8 __dont_write_directly__verb; -+ union { -+ struct bm_mcc_acquire acquire; -+ struct bm_mcc_query query; -+ }; -+} __packed; -+#define BM_MCC_VERB_VBIT 0x80 -+#define BM_MCC_VERB_CMD_MASK 0x70 /* where the verb contains; */ -+#define BM_MCC_VERB_CMD_ACQUIRE 0x10 -+#define BM_MCC_VERB_CMD_QUERY 0x40 -+#define BM_MCC_VERB_ACQUIRE_BUFCOUNT 0x0f /* values 1..8 go here */ -+ -+/* See 1.5.3.3: "Acquire Response" */ -+/* See 1.5.3.4: "Query Response" */ -+struct bm_pool_state { -+ u8 __reserved1[32]; -+ /* "availability state" and "depletion state" */ -+ struct { -+ u8 __reserved1[8]; -+ /* Access using bman_depletion_***() */ -+ struct bman_depletion state; -+ } as, ds; -+}; -+struct bm_mc_result { -+ union { -+ struct { -+ u8 verb; -+ u8 __reserved1[63]; -+ }; -+ union { -+ struct { -+ u8 __reserved1; -+ u8 bpid; -+ u8 __reserved2[62]; -+ }; -+ struct bm_buffer bufs[8]; -+ } acquire; -+ struct bm_pool_state query; -+ }; -+} __packed; -+#define BM_MCR_VERB_VBIT 0x80 -+#define BM_MCR_VERB_CMD_MASK BM_MCC_VERB_CMD_MASK -+#define BM_MCR_VERB_CMD_ACQUIRE BM_MCC_VERB_CMD_ACQUIRE -+#define BM_MCR_VERB_CMD_QUERY BM_MCC_VERB_CMD_QUERY -+#define BM_MCR_VERB_CMD_ERR_INVALID 0x60 -+#define BM_MCR_VERB_CMD_ERR_ECC 0x70 -+#define BM_MCR_VERB_ACQUIRE_BUFCOUNT BM_MCC_VERB_ACQUIRE_BUFCOUNT /* 0..8 */ -+/* Determine the "availability state" of pool 'p' from a query result 'r' */ -+#define BM_MCR_QUERY_AVAILABILITY(r, p) \ -+ bman_depletion_get(&r->query.as.state, p) -+/* Determine the "depletion state" of pool 'p' from a query result 'r' */ -+#define BM_MCR_QUERY_DEPLETION(r, p) \ -+ bman_depletion_get(&r->query.ds.state, p) -+ -+/*******************************************************************/ -+/* Managed (aka "shared" or "mux/demux") portal, high-level i/face */ -+/*******************************************************************/ -+ -+ /* Portal and Buffer Pools */ -+ /* ----------------------- */ -+/* Represents a managed portal */ -+struct bman_portal; -+ -+/* This object type represents Bman buffer pools. */ -+struct bman_pool; -+ -+struct bman_portal_config { -+ /* This is used for any "core-affine" portals, ie. default portals -+ * associated to the corresponding cpu. -1 implies that there is no core -+ * affinity configured. */ -+ int cpu; -+ /* portal interrupt line */ -+ int irq; -+ /* the unique index of this portal */ -+ u32 index; -+ /* Is this portal shared? (If so, it has coarser locking and demuxes -+ * processing on behalf of other CPUs.) */ -+ int is_shared; -+ /* These are the buffer pool IDs that may be used via this portal. */ -+ struct bman_depletion mask; -+}; -+ -+/* This callback type is used when handling pool depletion entry/exit. The -+ * 'cb_ctx' value is the opaque value associated with the pool object in -+ * bman_new_pool(). 'depleted' is non-zero on depletion-entry, and zero on -+ * depletion-exit. */ -+typedef void (*bman_cb_depletion)(struct bman_portal *bm, -+ struct bman_pool *pool, void *cb_ctx, int depleted); -+ -+/* This struct specifies parameters for a bman_pool object. */ -+struct bman_pool_params { -+ /* index of the buffer pool to encapsulate (0-63), ignored if -+ * BMAN_POOL_FLAG_DYNAMIC_BPID is set. */ -+ u32 bpid; -+ /* bit-mask of BMAN_POOL_FLAG_*** options */ -+ u32 flags; -+ /* depletion-entry/exit callback, if BMAN_POOL_FLAG_DEPLETION is set */ -+ bman_cb_depletion cb; -+ /* opaque user value passed as a parameter to 'cb' */ -+ void *cb_ctx; -+ /* depletion-entry/exit thresholds, if BMAN_POOL_FLAG_THRESH is set. NB: -+ * this is only allowed if BMAN_POOL_FLAG_DYNAMIC_BPID is used *and* -+ * when run in the control plane (which controls Bman CCSR). This array -+ * matches the definition of bm_pool_set(). */ -+ u32 thresholds[4]; -+}; -+ -+/* Flags to bman_new_pool() */ -+#define BMAN_POOL_FLAG_NO_RELEASE 0x00000001 /* can't release to pool */ -+#define BMAN_POOL_FLAG_ONLY_RELEASE 0x00000002 /* can only release to pool */ -+#define BMAN_POOL_FLAG_DEPLETION 0x00000004 /* track depletion entry/exit */ -+#define BMAN_POOL_FLAG_DYNAMIC_BPID 0x00000008 /* (de)allocate bpid */ -+#define BMAN_POOL_FLAG_THRESH 0x00000010 /* set depletion thresholds */ -+#define BMAN_POOL_FLAG_STOCKPILE 0x00000020 /* stockpile to reduce hw ops */ -+ -+/* Flags to bman_release() */ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+#define BMAN_RELEASE_FLAG_WAIT 0x00000001 /* wait if RCR is full */ -+#define BMAN_RELEASE_FLAG_WAIT_INT 0x00000002 /* if we wait, interruptible? */ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+#define BMAN_RELEASE_FLAG_WAIT_SYNC 0x00000004 /* if wait, until consumed? */ -+#endif -+#endif -+#define BMAN_RELEASE_FLAG_NOW 0x00000008 /* issue immediate release */ -+ -+/* Flags to bman_acquire() */ -+#define BMAN_ACQUIRE_FLAG_STOCKPILE 0x00000001 /* no hw op, stockpile only */ -+ -+ /* Portal Management */ -+ /* ----------------- */ -+/** -+ * bman_get_portal_config - get portal configuration settings -+ * -+ * This returns a read-only view of the current cpu's affine portal settings. -+ */ -+const struct bman_portal_config *bman_get_portal_config(void); -+ -+/** -+ * bman_irqsource_get - return the portal work that is interrupt-driven -+ * -+ * Returns a bitmask of BM_PIRQ_**I processing sources that are currently -+ * enabled for interrupt handling on the current cpu's affine portal. These -+ * sources will trigger the portal interrupt and the interrupt handler (or a -+ * tasklet/bottom-half it defers to) will perform the corresponding processing -+ * work. The bman_poll_***() functions will only process sources that are not in -+ * this bitmask. If the current CPU is sharing a portal hosted on another CPU, -+ * this always returns zero. -+ */ -+u32 bman_irqsource_get(void); -+ -+/** -+ * bman_irqsource_add - add processing sources to be interrupt-driven -+ * @bits: bitmask of BM_PIRQ_**I processing sources -+ * -+ * Adds processing sources that should be interrupt-driven (rather than -+ * processed via bman_poll_***() functions). Returns zero for success, or -+ * -EINVAL if the current CPU is sharing a portal hosted on another CPU. */ -+int bman_irqsource_add(u32 bits); -+ -+/** -+ * bman_irqsource_remove - remove processing sources from being interrupt-driven -+ * @bits: bitmask of BM_PIRQ_**I processing sources -+ * -+ * Removes processing sources from being interrupt-driven, so that they will -+ * instead be processed via bman_poll_***() functions. Returns zero for success, -+ * or -EINVAL if the current CPU is sharing a portal hosted on another CPU. */ -+int bman_irqsource_remove(u32 bits); -+ -+/** -+ * bman_affine_cpus - return a mask of cpus that have affine portals -+ */ -+const cpumask_t *bman_affine_cpus(void); -+ -+/** -+ * bman_poll_slow - process anything that isn't interrupt-driven. -+ * -+ * This function does any portal processing that isn't interrupt-driven. If the -+ * current CPU is sharing a portal hosted on another CPU, this function will -+ * return -EINVAL, otherwise the return value is a bitmask of BM_PIRQ_* sources -+ * indicating what interrupt sources were actually processed by the call. -+ * -+ * NB, unlike the legacy wrapper bman_poll(), this function will -+ * deterministically check for the presence of portal processing work and do it, -+ * which implies some latency even if there's nothing to do. The bman_poll() -+ * wrapper on the other hand (like the qman_poll() wrapper) attenuates this by -+ * checking for (and doing) portal processing infrequently. Ie. such that -+ * qman_poll() and bman_poll() can be called from core-processing loops. Use -+ * bman_poll_slow() when you yourself are deciding when to incur the overhead of -+ * processing. -+ */ -+u32 bman_poll_slow(void); -+ -+/** -+ * bman_poll - process anything that isn't interrupt-driven. -+ * -+ * Dispatcher logic on a cpu can use this to trigger any maintenance of the -+ * affine portal. This function does whatever processing is not triggered by -+ * interrupts. This is a legacy wrapper that can be used in core-processing -+ * loops but mitigates the performance overhead of portal processing by -+ * adaptively bypassing true portal processing most of the time. (Processing is -+ * done once every 10 calls if the previous processing revealed that work needed -+ * to be done, or once very 1000 calls if the previous processing revealed no -+ * work needed doing.) If you wish to control this yourself, call -+ * bman_poll_slow() instead, which always checks for portal processing work. -+ */ -+void bman_poll(void); -+ -+/** -+ * bman_rcr_is_empty - Determine if portal's RCR is empty -+ * -+ * For use in situations where a cpu-affine caller needs to determine when all -+ * releases for the local portal have been processed by Bman but can't use the -+ * BMAN_RELEASE_FLAG_WAIT_SYNC flag to do this from the final bman_release(). -+ * The function forces tracking of RCR consumption (which normally doesn't -+ * happen until release processing needs to find space to put new release -+ * commands), and returns zero if the ring still has unprocessed entries, -+ * non-zero if it is empty. -+ */ -+int bman_rcr_is_empty(void); -+ -+/** -+ * bman_alloc_bpid_range - Allocate a contiguous range of BPIDs -+ * @result: is set by the API to the base BPID of the allocated range -+ * @count: the number of BPIDs required -+ * @align: required alignment of the allocated range -+ * @partial: non-zero if the API can return fewer than @count BPIDs -+ * -+ * Returns the number of buffer pools allocated, or a negative error code. If -+ * @partial is non zero, the allocation request may return a smaller range of -+ * BPs than requested (though alignment will be as requested). If @partial is -+ * zero, the return value will either be 'count' or negative. -+ */ -+int bman_alloc_bpid_range(u32 *result, u32 count, u32 align, int partial); -+static inline int bman_alloc_bpid(u32 *result) -+{ -+ int ret = bman_alloc_bpid_range(result, 1, 0, 0); -+ return (ret > 0) ? 0 : ret; -+} -+ -+/** -+ * bman_release_bpid_range - Release the specified range of buffer pool IDs -+ * @bpid: the base BPID of the range to deallocate -+ * @count: the number of BPIDs in the range -+ * -+ * This function can also be used to seed the allocator with ranges of BPIDs -+ * that it can subsequently allocate from. -+ */ -+void bman_release_bpid_range(u32 bpid, unsigned int count); -+static inline void bman_release_bpid(u32 bpid) -+{ -+ bman_release_bpid_range(bpid, 1); -+} -+ -+int bman_reserve_bpid_range(u32 bpid, unsigned int count); -+static inline int bman_reserve_bpid(u32 bpid) -+{ -+ return bman_reserve_bpid_range(bpid, 1); -+} -+ -+void bman_seed_bpid_range(u32 bpid, unsigned int count); -+ -+ -+int bman_shutdown_pool(u32 bpid); -+ -+ /* Pool management */ -+ /* --------------- */ -+/** -+ * bman_new_pool - Allocates a Buffer Pool object -+ * @params: parameters specifying the buffer pool ID and behaviour -+ * -+ * Creates a pool object for the given @params. A portal and the depletion -+ * callback field of @params are only used if the BMAN_POOL_FLAG_DEPLETION flag -+ * is set. NB, the fields from @params are copied into the new pool object, so -+ * the structure provided by the caller can be released or reused after the -+ * function returns. -+ */ -+struct bman_pool *bman_new_pool(const struct bman_pool_params *params); -+ -+/** -+ * bman_free_pool - Deallocates a Buffer Pool object -+ * @pool: the pool object to release -+ * -+ */ -+void bman_free_pool(struct bman_pool *pool); -+ -+/** -+ * bman_get_params - Returns a pool object's parameters. -+ * @pool: the pool object -+ * -+ * The returned pointer refers to state within the pool object so must not be -+ * modified and can no longer be read once the pool object is destroyed. -+ */ -+const struct bman_pool_params *bman_get_params(const struct bman_pool *pool); -+ -+/** -+ * bman_release - Release buffer(s) to the buffer pool -+ * @pool: the buffer pool object to release to -+ * @bufs: an array of buffers to release -+ * @num: the number of buffers in @bufs (1-8) -+ * @flags: bit-mask of BMAN_RELEASE_FLAG_*** options -+ * -+ * Adds the given buffers to RCR entries. If the portal @p was created with the -+ * "COMPACT" flag, then it will be using a compaction algorithm to improve -+ * utilisation of RCR. As such, these buffers may join an existing ring entry -+ * and/or it may not be issued right away so as to allow future releases to join -+ * the same ring entry. Use the BMAN_RELEASE_FLAG_NOW flag to override this -+ * behaviour by committing the RCR entry (or entries) right away. If the RCR -+ * ring is full, the function will return -EBUSY unless BMAN_RELEASE_FLAG_WAIT -+ * is selected, in which case it will sleep waiting for space to become -+ * available in RCR. If the function receives a signal before such time (and -+ * BMAN_RELEASE_FLAG_WAIT_INT is set), the function returns -EINTR. Otherwise, -+ * it returns zero. -+ */ -+int bman_release(struct bman_pool *pool, const struct bm_buffer *bufs, u8 num, -+ u32 flags); -+ -+/** -+ * bman_acquire - Acquire buffer(s) from a buffer pool -+ * @pool: the buffer pool object to acquire from -+ * @bufs: array for storing the acquired buffers -+ * @num: the number of buffers desired (@bufs is at least this big) -+ * -+ * Issues an "Acquire" command via the portal's management command interface. -+ * The return value will be the number of buffers obtained from the pool, or a -+ * negative error code if a h/w error or pool starvation was encountered. In -+ * the latter case, the content of @bufs is undefined. -+ */ -+int bman_acquire(struct bman_pool *pool, struct bm_buffer *bufs, u8 num, -+ u32 flags); -+ -+/** -+ * bman_flush_stockpile - Flush stockpile buffer(s) to the buffer pool -+ * @pool: the buffer pool object the stockpile belongs -+ * @flags: bit-mask of BMAN_RELEASE_FLAG_*** options -+ * -+ * Adds stockpile buffers to RCR entries until the stockpile is empty. -+ * The return value will be a negative error code if a h/w error occurred. -+ * If BMAN_RELEASE_FLAG_NOW flag is passed and RCR ring is full, -+ * -EAGAIN will be returned. -+ */ -+int bman_flush_stockpile(struct bman_pool *pool, u32 flags); -+ -+/** -+ * bman_query_pools - Query all buffer pool states -+ * @state: storage for the queried availability and depletion states -+ */ -+int bman_query_pools(struct bm_pool_state *state); -+ -+#ifdef CONFIG_FSL_BMAN_CONFIG -+/** -+ * bman_query_free_buffers - Query how many free buffers are in buffer pool -+ * @pool: the buffer pool object to query -+ * -+ * Return the number of the free buffers -+ */ -+u32 bman_query_free_buffers(struct bman_pool *pool); -+ -+/** -+ * bman_update_pool_thresholds - Change the buffer pool's depletion thresholds -+ * @pool: the buffer pool object to which the thresholds will be set -+ * @thresholds: the new thresholds -+ */ -+int bman_update_pool_thresholds(struct bman_pool *pool, const u32 *thresholds); -+#endif -+ -+/** -+ * The below bman_p_***() variant might be called in a situation that the cpu -+ * which the portal affine to is not online yet. -+ * @bman_portal specifies which portal the API will use. -+*/ -+int bman_p_irqsource_add(struct bman_portal *p, __maybe_unused u32 bits); -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* FSL_BMAN_H */ ---- /dev/null -+++ b/include/linux/fsl_qman.h -@@ -0,0 +1,3889 @@ -+/* Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef FSL_QMAN_H -+#define FSL_QMAN_H -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/* Last updated for v00.800 of the BG */ -+ -+/* Hardware constants */ -+#define QM_CHANNEL_SWPORTAL0 0 -+#define QMAN_CHANNEL_POOL1 0x21 -+#define QMAN_CHANNEL_CAAM 0x80 -+#define QMAN_CHANNEL_PME 0xa0 -+#define QMAN_CHANNEL_POOL1_REV3 0x401 -+#define QMAN_CHANNEL_CAAM_REV3 0x840 -+#define QMAN_CHANNEL_PME_REV3 0x860 -+#define QMAN_CHANNEL_DCE 0x8a0 -+#define QMAN_CHANNEL_DCE_QMANREV312 0x880 -+extern u16 qm_channel_pool1; -+extern u16 qm_channel_caam; -+extern u16 qm_channel_pme; -+extern u16 qm_channel_dce; -+enum qm_dc_portal { -+ qm_dc_portal_fman0 = 0, -+ qm_dc_portal_fman1 = 1, -+ qm_dc_portal_caam = 2, -+ qm_dc_portal_pme = 3, -+ qm_dc_portal_rman = 4, -+ qm_dc_portal_dce = 5 -+}; -+ -+/* Portal processing (interrupt) sources */ -+#define QM_PIRQ_CCSCI 0x00200000 /* CEETM Congestion State Change */ -+#define QM_PIRQ_CSCI 0x00100000 /* Congestion State Change */ -+#define QM_PIRQ_EQCI 0x00080000 /* Enqueue Command Committed */ -+#define QM_PIRQ_EQRI 0x00040000 /* EQCR Ring (below threshold) */ -+#define QM_PIRQ_DQRI 0x00020000 /* DQRR Ring (non-empty) */ -+#define QM_PIRQ_MRI 0x00010000 /* MR Ring (non-empty) */ -+/* This mask contains all the interrupt sources that need handling except DQRI, -+ * ie. that if present should trigger slow-path processing. */ -+#define QM_PIRQ_SLOW (QM_PIRQ_CSCI | QM_PIRQ_EQCI | QM_PIRQ_EQRI | \ -+ QM_PIRQ_MRI | QM_PIRQ_CCSCI) -+ -+/* --- Clock speed --- */ -+/* A qman driver instance may or may not know the current qman clock speed. -+ * However, certain CEETM calculations may not be possible if this is not known. -+ * The 'set' function will only succeed (return zero) if the driver did not -+ * already know the clock speed. Likewise, the 'get' function will only succeed -+ * if the driver does know the clock speed (either because it knew when booting, -+ * or was told via 'set'). In cases where software is running on a driver -+ * instance that does not know the clock speed (eg. on a hypervised data-plane), -+ * and the user can obtain the current qman clock speed by other means (eg. from -+ * a message sent from the control-plane), then the 'set' function can be used -+ * to enable rate-calculations in a driver where it would otherwise not be -+ * possible. */ -+int qm_get_clock(u64 *clock_hz); -+int qm_set_clock(u64 clock_hz); -+ -+/* For qman_static_dequeue_*** APIs */ -+#define QM_SDQCR_CHANNELS_POOL_MASK 0x00007fff -+/* for n in [1,15] */ -+#define QM_SDQCR_CHANNELS_POOL(n) (0x00008000 >> (n)) -+/* for conversion from n of qm_channel */ -+static inline u32 QM_SDQCR_CHANNELS_POOL_CONV(u16 channel) -+{ -+ return QM_SDQCR_CHANNELS_POOL(channel + 1 - qm_channel_pool1); -+} -+ -+/* For qman_volatile_dequeue(); Choose one PRECEDENCE. EXACT is optional. Use -+ * NUMFRAMES(n) (6-bit) or NUMFRAMES_TILLEMPTY to fill in the frame-count. Use -+ * FQID(n) to fill in the frame queue ID. */ -+#define QM_VDQCR_PRECEDENCE_VDQCR 0x0 -+#define QM_VDQCR_PRECEDENCE_SDQCR 0x80000000 -+#define QM_VDQCR_EXACT 0x40000000 -+#define QM_VDQCR_NUMFRAMES_MASK 0x3f000000 -+#define QM_VDQCR_NUMFRAMES_SET(n) (((n) & 0x3f) << 24) -+#define QM_VDQCR_NUMFRAMES_GET(n) (((n) >> 24) & 0x3f) -+#define QM_VDQCR_NUMFRAMES_TILLEMPTY QM_VDQCR_NUMFRAMES_SET(0) -+ -+ -+/* ------------------------------------------------------- */ -+/* --- Qman data structures (and associated constants) --- */ -+ -+/* Represents s/w corenet portal mapped data structures */ -+struct qm_eqcr_entry; /* EQCR (EnQueue Command Ring) entries */ -+struct qm_dqrr_entry; /* DQRR (DeQueue Response Ring) entries */ -+struct qm_mr_entry; /* MR (Message Ring) entries */ -+struct qm_mc_command; /* MC (Management Command) command */ -+struct qm_mc_result; /* MC result */ -+ -+/* See David Lapp's "Frame formats" document, "dpateam", Jan 07, 2008 */ -+#define QM_FD_FORMAT_SG 0x4 -+#define QM_FD_FORMAT_LONG 0x2 -+#define QM_FD_FORMAT_COMPOUND 0x1 -+enum qm_fd_format { -+ /* 'contig' implies a contiguous buffer, whereas 'sg' implies a -+ * scatter-gather table. 'big' implies a 29-bit length with no offset -+ * field, otherwise length is 20-bit and offset is 9-bit. 'compound' -+ * implies a s/g-like table, where each entry itself represents a frame -+ * (contiguous or scatter-gather) and the 29-bit "length" is -+ * interpreted purely for congestion calculations, ie. a "congestion -+ * weight". */ -+ qm_fd_contig = 0, -+ qm_fd_contig_big = QM_FD_FORMAT_LONG, -+ qm_fd_sg = QM_FD_FORMAT_SG, -+ qm_fd_sg_big = QM_FD_FORMAT_SG | QM_FD_FORMAT_LONG, -+ qm_fd_compound = QM_FD_FORMAT_COMPOUND -+}; -+ -+/* Capitalised versions are un-typed but can be used in static expressions */ -+#define QM_FD_CONTIG 0 -+#define QM_FD_CONTIG_BIG QM_FD_FORMAT_LONG -+#define QM_FD_SG QM_FD_FORMAT_SG -+#define QM_FD_SG_BIG (QM_FD_FORMAT_SG | QM_FD_FORMAT_LONG) -+#define QM_FD_COMPOUND QM_FD_FORMAT_COMPOUND -+ -+/* See 1.5.1.1: "Frame Descriptor (FD)" */ -+struct qm_fd { -+ union { -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 dd:2; /* dynamic debug */ -+ u8 liodn_offset:6; -+ u8 bpid:8; /* Buffer Pool ID */ -+ u8 eliodn_offset:4; -+ u8 __reserved:4; -+ u8 addr_hi; /* high 8-bits of 40-bit address */ -+ u32 addr_lo; /* low 32-bits of 40-bit address */ -+#else -+ u8 liodn_offset:6; -+ u8 dd:2; /* dynamic debug */ -+ u8 bpid:8; /* Buffer Pool ID */ -+ u8 __reserved:4; -+ u8 eliodn_offset:4; -+ u8 addr_hi; /* high 8-bits of 40-bit address */ -+ u32 addr_lo; /* low 32-bits of 40-bit address */ -+#endif -+ }; -+ struct { -+ u64 __notaddress:24; -+ /* More efficient address accessor */ -+ u64 addr:40; -+ }; -+ u64 opaque_addr; -+ }; -+ /* The 'format' field indicates the interpretation of the remaining 29 -+ * bits of the 32-bit word. For packing reasons, it is duplicated in the -+ * other union elements. Note, union'd structs are difficult to use with -+ * static initialisation under gcc, in which case use the "opaque" form -+ * with one of the macros. */ -+ union { -+ /* For easier/faster copying of this part of the fd (eg. from a -+ * DQRR entry to an EQCR entry) copy 'opaque' */ -+ u32 opaque; -+ /* If 'format' is _contig or _sg, 20b length and 9b offset */ -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ enum qm_fd_format format:3; -+ u16 offset:9; -+ u32 length20:20; -+#else -+ u32 length20:20; -+ u16 offset:9; -+ enum qm_fd_format format:3; -+#endif -+ }; -+ /* If 'format' is _contig_big or _sg_big, 29b length */ -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ enum qm_fd_format _format1:3; -+ u32 length29:29; -+#else -+ u32 length29:29; -+ enum qm_fd_format _format1:3; -+#endif -+ }; -+ /* If 'format' is _compound, 29b "congestion weight" */ -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ enum qm_fd_format _format2:3; -+ u32 cong_weight:29; -+#else -+ u32 cong_weight:29; -+ enum qm_fd_format _format2:3; -+#endif -+ }; -+ }; -+ union { -+ u32 cmd; -+ u32 status; -+ }; -+} __aligned(8); -+#define QM_FD_DD_NULL 0x00 -+#define QM_FD_PID_MASK 0x3f -+static inline u64 qm_fd_addr_get64(const struct qm_fd *fd) -+{ -+ return fd->addr; -+} -+ -+static inline dma_addr_t qm_fd_addr(const struct qm_fd *fd) -+{ -+ return (dma_addr_t)fd->addr; -+} -+/* Macro, so we compile better if 'v' isn't always 64-bit */ -+#define qm_fd_addr_set64(fd, v) \ -+ do { \ -+ struct qm_fd *__fd931 = (fd); \ -+ __fd931->addr = v; \ -+ } while (0) -+ -+/* For static initialisation of FDs (which is complicated by the use of unions -+ * in "struct qm_fd"), use the following macros. Note that; -+ * - 'dd', 'pid' and 'bpid' are ignored because there's no static initialisation -+ * use-case), -+ * - use capitalised QM_FD_*** formats for static initialisation. -+ */ -+#define QM_FD_FMT_20(cmd, addr_hi, addr_lo, fmt, off, len) \ -+ { 0, 0, 0, 0, 0, addr_hi, addr_lo, \ -+ { (((fmt)&0x7) << 29) | (((off)&0x1ff) << 20) | ((len)&0xfffff) }, \ -+ { cmd } } -+#define QM_FD_FMT_29(cmd, addr_hi, addr_lo, fmt, len) \ -+ { 0, 0, 0, 0, 0, addr_hi, addr_lo, \ -+ { (((fmt)&0x7) << 29) | ((len)&0x1fffffff) }, \ -+ { cmd } } -+ -+/* See 2.2.1.3 Multi-Core Datapath Acceleration Architecture */ -+#define QM_SG_OFFSET_MASK 0x1FFF -+struct qm_sg_entry { -+ union { -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 __reserved1[3]; -+ u8 addr_hi; /* high 8-bits of 40-bit address */ -+ u32 addr_lo; /* low 32-bits of 40-bit address */ -+#else -+ u32 addr_lo; /* low 32-bits of 40-bit address */ -+ u8 addr_hi; /* high 8-bits of 40-bit address */ -+ u8 __reserved1[3]; -+#endif -+ }; -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u64 __notaddress:24; -+ u64 addr:40; -+#else -+ u64 addr:40; -+ u64 __notaddress:24; -+#endif -+ }; -+ u64 opaque; -+ }; -+ union { -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u32 extension:1; /* Extension bit */ -+ u32 final:1; /* Final bit */ -+ u32 length:30; -+#else -+ u32 length:30; -+ u32 final:1; /* Final bit */ -+ u32 extension:1; /* Extension bit */ -+#endif -+ }; -+ u32 sgt_efl; -+ }; -+ u8 __reserved2; -+ u8 bpid; -+ union { -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u16 __reserved3:3; -+ u16 offset:13; -+#else -+ u16 offset:13; -+ u16 __reserved3:3; -+#endif -+ }; -+ u16 opaque_offset; -+ }; -+} __packed; -+union qm_sg_efl { -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u32 extension:1; /* Extension bit */ -+ u32 final:1; /* Final bit */ -+ u32 length:30; -+#else -+ u32 length:30; -+ u32 final:1; /* Final bit */ -+ u32 extension:1; /* Extension bit */ -+#endif -+ }; -+ u32 efl; -+}; -+static inline u64 qm_sg_entry_get64(const struct qm_sg_entry *sg) -+{ -+ return be64_to_cpu(sg->opaque); -+} -+static inline dma_addr_t qm_sg_addr(const struct qm_sg_entry *sg) -+{ -+ return (dma_addr_t)be64_to_cpu(sg->opaque); -+} -+static inline u8 qm_sg_entry_get_ext(const struct qm_sg_entry *sg) -+{ -+ union qm_sg_efl u; -+ -+ u.efl = be32_to_cpu(sg->sgt_efl); -+ return u.extension; -+} -+static inline u8 qm_sg_entry_get_final(const struct qm_sg_entry *sg) -+{ -+ union qm_sg_efl u; -+ -+ u.efl = be32_to_cpu(sg->sgt_efl); -+ return u.final; -+} -+static inline u32 qm_sg_entry_get_len(const struct qm_sg_entry *sg) -+{ -+ union qm_sg_efl u; -+ -+ u.efl = be32_to_cpu(sg->sgt_efl); -+ return u.length; -+} -+static inline u8 qm_sg_entry_get_bpid(const struct qm_sg_entry *sg) -+{ -+ return sg->bpid; -+} -+static inline u16 qm_sg_entry_get_offset(const struct qm_sg_entry *sg) -+{ -+ u32 opaque_offset = be16_to_cpu(sg->opaque_offset); -+ -+ return opaque_offset & 0x1fff; -+} -+ -+/* Macro, so we compile better if 'v' isn't always 64-bit */ -+#define qm_sg_entry_set64(sg, v) \ -+ do { \ -+ struct qm_sg_entry *__sg931 = (sg); \ -+ __sg931->opaque = cpu_to_be64(v); \ -+ } while (0) -+#define qm_sg_entry_set_ext(sg, v) \ -+ do { \ -+ union qm_sg_efl __u932; \ -+ __u932.efl = be32_to_cpu((sg)->sgt_efl); \ -+ __u932.extension = v; \ -+ (sg)->sgt_efl = cpu_to_be32(__u932.efl); \ -+ } while (0) -+#define qm_sg_entry_set_final(sg, v) \ -+ do { \ -+ union qm_sg_efl __u933; \ -+ __u933.efl = be32_to_cpu((sg)->sgt_efl); \ -+ __u933.final = v; \ -+ (sg)->sgt_efl = cpu_to_be32(__u933.efl); \ -+ } while (0) -+#define qm_sg_entry_set_len(sg, v) \ -+ do { \ -+ union qm_sg_efl __u934; \ -+ __u934.efl = be32_to_cpu((sg)->sgt_efl); \ -+ __u934.length = v; \ -+ (sg)->sgt_efl = cpu_to_be32(__u934.efl); \ -+ } while (0) -+#define qm_sg_entry_set_bpid(sg, v) \ -+ do { \ -+ struct qm_sg_entry *__u935 = (sg); \ -+ __u935->bpid = v; \ -+ } while (0) -+#define qm_sg_entry_set_offset(sg, v) \ -+ do { \ -+ struct qm_sg_entry *__u936 = (sg); \ -+ __u936->opaque_offset = cpu_to_be16(v); \ -+ } while (0) -+ -+/* See 1.5.8.1: "Enqueue Command" */ -+struct qm_eqcr_entry { -+ u8 __dont_write_directly__verb; -+ u8 dca; -+ u16 seqnum; -+ u32 orp; /* 24-bit */ -+ u32 fqid; /* 24-bit */ -+ u32 tag; -+ struct qm_fd fd; -+ u8 __reserved3[32]; -+} __packed; -+#define QM_EQCR_VERB_VBIT 0x80 -+#define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */ -+#define QM_EQCR_VERB_CMD_ENQUEUE 0x01 -+#define QM_EQCR_VERB_COLOUR_MASK 0x18 /* 4 possible values; */ -+#define QM_EQCR_VERB_COLOUR_GREEN 0x00 -+#define QM_EQCR_VERB_COLOUR_YELLOW 0x08 -+#define QM_EQCR_VERB_COLOUR_RED 0x10 -+#define QM_EQCR_VERB_COLOUR_OVERRIDE 0x18 -+#define QM_EQCR_VERB_INTERRUPT 0x04 /* on command consumption */ -+#define QM_EQCR_VERB_ORP 0x02 /* enable order restoration */ -+#define QM_EQCR_DCA_ENABLE 0x80 -+#define QM_EQCR_DCA_PARK 0x40 -+#define QM_EQCR_DCA_IDXMASK 0x0f /* "DQRR::idx" goes here */ -+#define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */ -+#define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */ -+#define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */ -+#define QM_EQCR_FQID_NULL 0 /* eg. for an ORP seqnum hole */ -+ -+/* See 1.5.8.2: "Frame Dequeue Response" */ -+struct qm_dqrr_entry { -+ u8 verb; -+ u8 stat; -+ u16 seqnum; /* 15-bit */ -+ u8 tok; -+ u8 __reserved2[3]; -+ u32 fqid; /* 24-bit */ -+ u32 contextB; -+ struct qm_fd fd; -+ u8 __reserved4[32]; -+}; -+#define QM_DQRR_VERB_VBIT 0x80 -+#define QM_DQRR_VERB_MASK 0x7f /* where the verb contains; */ -+#define QM_DQRR_VERB_FRAME_DEQUEUE 0x60 /* "this format" */ -+#define QM_DQRR_STAT_FQ_EMPTY 0x80 /* FQ empty */ -+#define QM_DQRR_STAT_FQ_HELDACTIVE 0x40 /* FQ held active */ -+#define QM_DQRR_STAT_FQ_FORCEELIGIBLE 0x20 /* FQ was force-eligible'd */ -+#define QM_DQRR_STAT_FD_VALID 0x10 /* has a non-NULL FD */ -+#define QM_DQRR_STAT_UNSCHEDULED 0x02 /* Unscheduled dequeue */ -+#define QM_DQRR_STAT_DQCR_EXPIRED 0x01 /* VDQCR or PDQCR expired*/ -+ -+/* See 1.5.8.3: "ERN Message Response" */ -+/* See 1.5.8.4: "FQ State Change Notification" */ -+struct qm_mr_entry { -+ u8 verb; -+ union { -+ struct { -+ u8 dca; -+ u16 seqnum; -+ u8 rc; /* Rejection Code */ -+ u32 orp:24; -+ u32 fqid; /* 24-bit */ -+ u32 tag; -+ struct qm_fd fd; -+ } __packed ern; -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 colour:2; /* See QM_MR_DCERN_COLOUR_* */ -+ u8 __reserved1:3; -+ enum qm_dc_portal portal:3; -+#else -+ enum qm_dc_portal portal:3; -+ u8 __reserved1:3; -+ u8 colour:2; /* See QM_MR_DCERN_COLOUR_* */ -+#endif -+ u16 __reserved2; -+ u8 rc; /* Rejection Code */ -+ u32 __reserved3:24; -+ u32 fqid; /* 24-bit */ -+ u32 tag; -+ struct qm_fd fd; -+ } __packed dcern; -+ struct { -+ u8 fqs; /* Frame Queue Status */ -+ u8 __reserved1[6]; -+ u32 fqid; /* 24-bit */ -+ u32 contextB; -+ u8 __reserved2[16]; -+ } __packed fq; /* FQRN/FQRNI/FQRL/FQPN */ -+ }; -+ u8 __reserved2[32]; -+} __packed; -+#define QM_MR_VERB_VBIT 0x80 -+/* The "ern" VERB bits match QM_EQCR_VERB_*** so aren't reproduced here. ERNs -+ * originating from direct-connect portals ("dcern") use 0x20 as a verb which -+ * would be invalid as a s/w enqueue verb. A s/w ERN can be distinguished from -+ * the other MR types by noting if the 0x20 bit is unset. */ -+#define QM_MR_VERB_TYPE_MASK 0x27 -+#define QM_MR_VERB_DC_ERN 0x20 -+#define QM_MR_VERB_FQRN 0x21 -+#define QM_MR_VERB_FQRNI 0x22 -+#define QM_MR_VERB_FQRL 0x23 -+#define QM_MR_VERB_FQPN 0x24 -+#define QM_MR_RC_MASK 0xf0 /* contains one of; */ -+#define QM_MR_RC_CGR_TAILDROP 0x00 -+#define QM_MR_RC_WRED 0x10 -+#define QM_MR_RC_ERROR 0x20 -+#define QM_MR_RC_ORPWINDOW_EARLY 0x30 -+#define QM_MR_RC_ORPWINDOW_LATE 0x40 -+#define QM_MR_RC_FQ_TAILDROP 0x50 -+#define QM_MR_RC_ORPWINDOW_RETIRED 0x60 -+#define QM_MR_RC_ORP_ZERO 0x70 -+#define QM_MR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */ -+#define QM_MR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */ -+#define QM_MR_DCERN_COLOUR_GREEN 0x00 -+#define QM_MR_DCERN_COLOUR_YELLOW 0x01 -+#define QM_MR_DCERN_COLOUR_RED 0x02 -+#define QM_MR_DCERN_COLOUR_OVERRIDE 0x03 -+ -+/* An identical structure of FQD fields is present in the "Init FQ" command and -+ * the "Query FQ" result, it's suctioned out into the "struct qm_fqd" type. -+ * Within that, the 'stashing' and 'taildrop' pieces are also factored out, the -+ * latter has two inlines to assist with converting to/from the mant+exp -+ * representation. */ -+struct qm_fqd_stashing { -+ /* See QM_STASHING_EXCL_<...> */ -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 exclusive; -+ u8 __reserved1:2; -+ /* Numbers of cachelines */ -+ u8 annotation_cl:2; -+ u8 data_cl:2; -+ u8 context_cl:2; -+#else -+ u8 context_cl:2; -+ u8 data_cl:2; -+ u8 annotation_cl:2; -+ u8 __reserved1:2; -+ u8 exclusive; -+#endif -+} __packed; -+struct qm_fqd_taildrop { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u16 __reserved1:3; -+ u16 mant:8; -+ u16 exp:5; -+#else -+ u16 exp:5; -+ u16 mant:8; -+ u16 __reserved1:3; -+#endif -+} __packed; -+struct qm_fqd_oac { -+ /* See QM_OAC_<...> */ -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 oac:2; /* "Overhead Accounting Control" */ -+ u8 __reserved1:6; -+#else -+ u8 __reserved1:6; -+ u8 oac:2; /* "Overhead Accounting Control" */ -+#endif -+ /* Two's-complement value (-128 to +127) */ -+ signed char oal; /* "Overhead Accounting Length" */ -+} __packed; -+struct qm_fqd { -+ union { -+ u8 orpc; -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 __reserved1:2; -+ u8 orprws:3; -+ u8 oa:1; -+ u8 olws:2; -+#else -+ u8 olws:2; -+ u8 oa:1; -+ u8 orprws:3; -+ u8 __reserved1:2; -+#endif -+ } __packed; -+ }; -+ u8 cgid; -+ u16 fq_ctrl; /* See QM_FQCTRL_<...> */ -+ union { -+ u16 dest_wq; -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u16 channel:13; /* qm_channel */ -+ u16 wq:3; -+#else -+ u16 wq:3; -+ u16 channel:13; /* qm_channel */ -+#endif -+ } __packed dest; -+ }; -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u16 __reserved2:1; -+ u16 ics_cred:15; -+#else -+ u16 __reserved2:1; -+ u16 ics_cred:15; -+#endif -+ /* For "Initialize Frame Queue" commands, the write-enable mask -+ * determines whether 'td' or 'oac_init' is observed. For query -+ * commands, this field is always 'td', and 'oac_query' (below) reflects -+ * the Overhead ACcounting values. */ -+ union { -+ struct qm_fqd_taildrop td; -+ struct qm_fqd_oac oac_init; -+ }; -+ u32 context_b; -+ union { -+ /* Treat it as 64-bit opaque */ -+ u64 opaque; -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u32 hi; -+ u32 lo; -+#else -+ u32 lo; -+ u32 hi; -+#endif -+ }; -+ /* Treat it as s/w portal stashing config */ -+ /* See 1.5.6.7.1: "FQD Context_A field used for [...] */ -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ struct qm_fqd_stashing stashing; -+ /* 48-bit address of FQ context to -+ * stash, must be cacheline-aligned */ -+ u16 context_hi; -+ u32 context_lo; -+#else -+ u32 context_lo; -+ u16 context_hi; -+ struct qm_fqd_stashing stashing; -+#endif -+ } __packed; -+ } context_a; -+ struct qm_fqd_oac oac_query; -+} __packed; -+/* 64-bit converters for context_hi/lo */ -+static inline u64 qm_fqd_stashing_get64(const struct qm_fqd *fqd) -+{ -+ return ((u64)fqd->context_a.context_hi << 32) | -+ (u64)fqd->context_a.context_lo; -+} -+static inline dma_addr_t qm_fqd_stashing_addr(const struct qm_fqd *fqd) -+{ -+ return (dma_addr_t)qm_fqd_stashing_get64(fqd); -+} -+static inline u64 qm_fqd_context_a_get64(const struct qm_fqd *fqd) -+{ -+ return ((u64)fqd->context_a.hi << 32) | -+ (u64)fqd->context_a.lo; -+} -+/* Macro, so we compile better when 'v' isn't necessarily 64-bit */ -+#define qm_fqd_stashing_set64(fqd, v) \ -+ do { \ -+ struct qm_fqd *__fqd931 = (fqd); \ -+ __fqd931->context_a.context_hi = upper_32_bits(v); \ -+ __fqd931->context_a.context_lo = lower_32_bits(v); \ -+ } while (0) -+#define qm_fqd_context_a_set64(fqd, v) \ -+ do { \ -+ struct qm_fqd *__fqd931 = (fqd); \ -+ __fqd931->context_a.hi = upper_32_bits(v); \ -+ __fqd931->context_a.lo = lower_32_bits(v); \ -+ } while (0) -+/* convert a threshold value into mant+exp representation */ -+static inline int qm_fqd_taildrop_set(struct qm_fqd_taildrop *td, u32 val, -+ int roundup) -+{ -+ u32 e = 0; -+ int oddbit = 0; -+ if (val > 0xe0000000) -+ return -ERANGE; -+ while (val > 0xff) { -+ oddbit = val & 1; -+ val >>= 1; -+ e++; -+ if (roundup && oddbit) -+ val++; -+ } -+ td->exp = e; -+ td->mant = val; -+ return 0; -+} -+/* and the other direction */ -+static inline u32 qm_fqd_taildrop_get(const struct qm_fqd_taildrop *td) -+{ -+ return (u32)td->mant << td->exp; -+} -+ -+/* See 1.5.2.2: "Frame Queue Descriptor (FQD)" */ -+/* Frame Queue Descriptor (FQD) field 'fq_ctrl' uses these constants */ -+#define QM_FQCTRL_MASK 0x07ff /* 'fq_ctrl' flags; */ -+#define QM_FQCTRL_CGE 0x0400 /* Congestion Group Enable */ -+#define QM_FQCTRL_TDE 0x0200 /* Tail-Drop Enable */ -+#define QM_FQCTRL_ORP 0x0100 /* ORP Enable */ -+#define QM_FQCTRL_CTXASTASHING 0x0080 /* Context-A stashing */ -+#define QM_FQCTRL_CPCSTASH 0x0040 /* CPC Stash Enable */ -+#define QM_FQCTRL_FORCESFDR 0x0008 /* High-priority SFDRs */ -+#define QM_FQCTRL_AVOIDBLOCK 0x0004 /* Don't block active */ -+#define QM_FQCTRL_HOLDACTIVE 0x0002 /* Hold active in portal */ -+#define QM_FQCTRL_PREFERINCACHE 0x0001 /* Aggressively cache FQD */ -+#define QM_FQCTRL_LOCKINCACHE QM_FQCTRL_PREFERINCACHE /* older naming */ -+ -+/* See 1.5.6.7.1: "FQD Context_A field used for [...] */ -+/* Frame Queue Descriptor (FQD) field 'CONTEXT_A' uses these constants */ -+#define QM_STASHING_EXCL_ANNOTATION 0x04 -+#define QM_STASHING_EXCL_DATA 0x02 -+#define QM_STASHING_EXCL_CTX 0x01 -+ -+/* See 1.5.5.3: "Intra Class Scheduling" */ -+/* FQD field 'OAC' (Overhead ACcounting) uses these constants */ -+#define QM_OAC_ICS 0x2 /* Accounting for Intra-Class Scheduling */ -+#define QM_OAC_CG 0x1 /* Accounting for Congestion Groups */ -+ -+/* See 1.5.8.4: "FQ State Change Notification" */ -+/* This struct represents the 32-bit "WR_PARM_[GYR]" parameters in CGR fields -+ * and associated commands/responses. The WRED parameters are calculated from -+ * these fields as follows; -+ * MaxTH = MA * (2 ^ Mn) -+ * Slope = SA / (2 ^ Sn) -+ * MaxP = 4 * (Pn + 1) -+ */ -+struct qm_cgr_wr_parm { -+ union { -+ u32 word; -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u32 MA:8; -+ u32 Mn:5; -+ u32 SA:7; /* must be between 64-127 */ -+ u32 Sn:6; -+ u32 Pn:6; -+#else -+ u32 Pn:6; -+ u32 Sn:6; -+ u32 SA:7; /* must be between 64-127 */ -+ u32 Mn:5; -+ u32 MA:8; -+#endif -+ } __packed; -+ }; -+} __packed; -+/* This struct represents the 13-bit "CS_THRES" CGR field. In the corresponding -+ * management commands, this is padded to a 16-bit structure field, so that's -+ * how we represent it here. The congestion state threshold is calculated from -+ * these fields as follows; -+ * CS threshold = TA * (2 ^ Tn) -+ */ -+struct qm_cgr_cs_thres { -+ union { -+ u16 hword; -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u16 __reserved:3; -+ u16 TA:8; -+ u16 Tn:5; -+#else -+ u16 Tn:5; -+ u16 TA:8; -+ u16 __reserved:3; -+#endif -+ } __packed; -+ }; -+} __packed; -+/* This identical structure of CGR fields is present in the "Init/Modify CGR" -+ * commands and the "Query CGR" result. It's suctioned out here into its own -+ * struct. */ -+struct __qm_mc_cgr { -+ struct qm_cgr_wr_parm wr_parm_g; -+ struct qm_cgr_wr_parm wr_parm_y; -+ struct qm_cgr_wr_parm wr_parm_r; -+ u8 wr_en_g; /* boolean, use QM_CGR_EN */ -+ u8 wr_en_y; /* boolean, use QM_CGR_EN */ -+ u8 wr_en_r; /* boolean, use QM_CGR_EN */ -+ u8 cscn_en; /* boolean, use QM_CGR_EN */ -+ union { -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u16 cscn_targ_upd_ctrl; /* use QM_CSCN_TARG_UDP_ */ -+ u16 cscn_targ_dcp_low; /* CSCN_TARG_DCP low-16bits */ -+#else -+ u16 cscn_targ_dcp_low; /* CSCN_TARG_DCP low-16bits */ -+ u16 cscn_targ_upd_ctrl; /* use QM_CSCN_TARG_UDP_ */ -+#endif -+ }; -+ u32 cscn_targ; /* use QM_CGR_TARG_* */ -+ }; -+ u8 cstd_en; /* boolean, use QM_CGR_EN */ -+ u8 cs; /* boolean, only used in query response */ -+ union { -+ /* use qm_cgr_cs_thres_set64() */ -+ struct qm_cgr_cs_thres cs_thres; -+ u16 __cs_thres; -+ }; -+ u8 mode; /* QMAN_CGR_MODE_FRAME not supported in rev1.0 */ -+} __packed; -+#define QM_CGR_EN 0x01 /* For wr_en_*, cscn_en, cstd_en */ -+#define QM_CGR_TARG_UDP_CTRL_WRITE_BIT 0x8000 /* value written to portal bit*/ -+#define QM_CGR_TARG_UDP_CTRL_DCP 0x4000 /* 0: SWP, 1: DCP */ -+#define QM_CGR_TARG_PORTAL(n) (0x80000000 >> (n)) /* s/w portal, 0-9 */ -+#define QM_CGR_TARG_FMAN0 0x00200000 /* direct-connect portal: fman0 */ -+#define QM_CGR_TARG_FMAN1 0x00100000 /* : fman1 */ -+/* Convert CGR thresholds to/from "cs_thres" format */ -+static inline u64 qm_cgr_cs_thres_get64(const struct qm_cgr_cs_thres *th) -+{ -+ return (u64)th->TA << th->Tn; -+} -+static inline int qm_cgr_cs_thres_set64(struct qm_cgr_cs_thres *th, u64 val, -+ int roundup) -+{ -+ u32 e = 0; -+ int oddbit = 0; -+ while (val > 0xff) { -+ oddbit = val & 1; -+ val >>= 1; -+ e++; -+ if (roundup && oddbit) -+ val++; -+ } -+ th->Tn = e; -+ th->TA = val; -+ return 0; -+} -+ -+/* See 1.5.8.5.1: "Initialize FQ" */ -+/* See 1.5.8.5.2: "Query FQ" */ -+/* See 1.5.8.5.3: "Query FQ Non-Programmable Fields" */ -+/* See 1.5.8.5.4: "Alter FQ State Commands " */ -+/* See 1.5.8.6.1: "Initialize/Modify CGR" */ -+/* See 1.5.8.6.2: "CGR Test Write" */ -+/* See 1.5.8.6.3: "Query CGR" */ -+/* See 1.5.8.6.4: "Query Congestion Group State" */ -+struct qm_mcc_initfq { -+ u8 __reserved1; -+ u16 we_mask; /* Write Enable Mask */ -+ u32 fqid; /* 24-bit */ -+ u16 count; /* Initialises 'count+1' FQDs */ -+ struct qm_fqd fqd; /* the FQD fields go here */ -+ u8 __reserved3[30]; -+} __packed; -+struct qm_mcc_queryfq { -+ u8 __reserved1[3]; -+ u32 fqid; /* 24-bit */ -+ u8 __reserved2[56]; -+} __packed; -+struct qm_mcc_queryfq_np { -+ u8 __reserved1[3]; -+ u32 fqid; /* 24-bit */ -+ u8 __reserved2[56]; -+} __packed; -+struct qm_mcc_alterfq { -+ u8 __reserved1[3]; -+ u32 fqid; /* 24-bit */ -+ u8 __reserved2; -+ u8 count; /* number of consecutive FQID */ -+ u8 __reserved3[10]; -+ u32 context_b; /* frame queue context b */ -+ u8 __reserved4[40]; -+} __packed; -+struct qm_mcc_initcgr { -+ u8 __reserved1; -+ u16 we_mask; /* Write Enable Mask */ -+ struct __qm_mc_cgr cgr; /* CGR fields */ -+ u8 __reserved2[2]; -+ u8 cgid; -+ u8 __reserved4[32]; -+} __packed; -+struct qm_mcc_cgrtestwrite { -+ u8 __reserved1[2]; -+ u8 i_bcnt_hi:8;/* high 8-bits of 40-bit "Instant" */ -+ u32 i_bcnt_lo; /* low 32-bits of 40-bit */ -+ u8 __reserved2[23]; -+ u8 cgid; -+ u8 __reserved3[32]; -+} __packed; -+struct qm_mcc_querycgr { -+ u8 __reserved1[30]; -+ u8 cgid; -+ u8 __reserved2[32]; -+} __packed; -+struct qm_mcc_querycongestion { -+ u8 __reserved[63]; -+} __packed; -+struct qm_mcc_querywq { -+ u8 __reserved; -+ /* select channel if verb != QUERYWQ_DEDICATED */ -+ union { -+ u16 channel_wq; /* ignores wq (3 lsbits) */ -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u16 id:13; /* qm_channel */ -+ u16 __reserved1:3; -+#else -+ u16 __reserved1:3; -+ u16 id:13; /* qm_channel */ -+#endif -+ } __packed channel; -+ }; -+ u8 __reserved2[60]; -+} __packed; -+ -+struct qm_mcc_ceetm_lfqmt_config { -+ u8 __reserved1[4]; -+ u32 lfqid:24; -+ u8 __reserved2[2]; -+ u16 cqid; -+ u8 __reserved3[2]; -+ u16 dctidx; -+ u8 __reserved4[48]; -+} __packed; -+ -+struct qm_mcc_ceetm_lfqmt_query { -+ u8 __reserved1[4]; -+ u32 lfqid:24; -+ u8 __reserved2[56]; -+} __packed; -+ -+struct qm_mcc_ceetm_cq_config { -+ u8 __reserved1; -+ u16 cqid; -+ u8 dcpid; -+ u8 __reserved2; -+ u16 ccgid; -+ u8 __reserved3[56]; -+} __packed; -+ -+struct qm_mcc_ceetm_cq_query { -+ u8 __reserved1; -+ u16 cqid; -+ u8 dcpid; -+ u8 __reserved2[59]; -+} __packed; -+ -+struct qm_mcc_ceetm_dct_config { -+ u8 __reserved1; -+ u16 dctidx; -+ u8 dcpid; -+ u8 __reserved2[15]; -+ u32 context_b; -+ u64 context_a; -+ u8 __reserved3[32]; -+} __packed; -+ -+struct qm_mcc_ceetm_dct_query { -+ u8 __reserved1; -+ u16 dctidx; -+ u8 dcpid; -+ u8 __reserved2[59]; -+} __packed; -+ -+struct qm_mcc_ceetm_class_scheduler_config { -+ u8 __reserved1; -+ u16 cqcid; -+ u8 dcpid; -+ u8 __reserved2[6]; -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 gpc_reserved:1; -+ u8 gpc_combine_flag:1; -+ u8 gpc_prio_b:3; -+ u8 gpc_prio_a:3; -+#else -+ u8 gpc_prio_a:3; -+ u8 gpc_prio_b:3; -+ u8 gpc_combine_flag:1; -+ u8 gpc_reserved:1; -+#endif -+ u16 crem; -+ u16 erem; -+ u8 w[8]; -+ u8 __reserved3[40]; -+} __packed; -+ -+struct qm_mcc_ceetm_class_scheduler_query { -+ u8 __reserved1; -+ u16 cqcid; -+ u8 dcpid; -+ u8 __reserved2[59]; -+} __packed; -+ -+#define CEETM_COMMAND_CHANNEL_MAPPING (0 << 12) -+#define CEETM_COMMAND_SP_MAPPING (1 << 12) -+#define CEETM_COMMAND_CHANNEL_SHAPER (2 << 12) -+#define CEETM_COMMAND_LNI_SHAPER (3 << 12) -+#define CEETM_COMMAND_TCFC (4 << 12) -+ -+#define CEETM_CCGRID_MASK 0x01FF -+#define CEETM_CCGR_CM_CONFIGURE (0 << 14) -+#define CEETM_CCGR_DN_CONFIGURE (1 << 14) -+#define CEETM_CCGR_TEST_WRITE (2 << 14) -+#define CEETM_CCGR_CM_QUERY (0 << 14) -+#define CEETM_CCGR_DN_QUERY (1 << 14) -+#define CEETM_CCGR_DN_QUERY_FLUSH (2 << 14) -+#define CEETM_QUERY_CONGESTION_STATE (3 << 14) -+ -+struct qm_mcc_ceetm_mapping_shaper_tcfc_config { -+ u8 __reserved1; -+ u16 cid; -+ u8 dcpid; -+ union { -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 map_shaped:1; -+ u8 map_reserved:4; -+ u8 map_lni_id:3; -+#else -+ u8 map_lni_id:3; -+ u8 map_reserved:4; -+ u8 map_shaped:1; -+#endif -+ u8 __reserved2[58]; -+ } __packed channel_mapping; -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 map_reserved:5; -+ u8 map_lni_id:3; -+#else -+ u8 map_lni_id:3; -+ u8 map_reserved:5; -+#endif -+ u8 __reserved2[58]; -+ } __packed sp_mapping; -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 cpl:1; -+ u8 cpl_reserved:2; -+ u8 oal:5; -+#else -+ u8 oal:5; -+ u8 cpl_reserved:2; -+ u8 cpl:1; -+#endif -+ u32 crtcr:24; -+ u32 ertcr:24; -+ u16 crtbl; -+ u16 ertbl; -+ u8 mps; /* This will be hardcoded by driver with 60 */ -+ u8 __reserved2[47]; -+ } __packed shaper_config; -+ struct { -+ u8 __reserved2[11]; -+ u64 lnitcfcc; -+ u8 __reserved3[40]; -+ } __packed tcfc_config; -+ }; -+} __packed; -+ -+struct qm_mcc_ceetm_mapping_shaper_tcfc_query { -+ u8 __reserved1; -+ u16 cid; -+ u8 dcpid; -+ u8 __reserved2[59]; -+} __packed; -+ -+struct qm_mcc_ceetm_ccgr_config { -+ u8 __reserved1; -+ u16 ccgrid; -+ u8 dcpid; -+ u8 __reserved2; -+ u16 we_mask; -+ union { -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 ctl_reserved:1; -+ u8 ctl_wr_en_g:1; -+ u8 ctl_wr_en_y:1; -+ u8 ctl_wr_en_r:1; -+ u8 ctl_td_en:1; -+ u8 ctl_td_mode:1; -+ u8 ctl_cscn_en:1; -+ u8 ctl_mode:1; -+#else -+ u8 ctl_mode:1; -+ u8 ctl_cscn_en:1; -+ u8 ctl_td_mode:1; -+ u8 ctl_td_en:1; -+ u8 ctl_wr_en_r:1; -+ u8 ctl_wr_en_y:1; -+ u8 ctl_wr_en_g:1; -+ u8 ctl_reserved:1; -+#endif -+ u8 cdv; -+ u16 cscn_tupd; -+ u8 oal; -+ u8 __reserved3; -+ struct qm_cgr_cs_thres cs_thres; -+ struct qm_cgr_cs_thres cs_thres_x; -+ struct qm_cgr_cs_thres td_thres; -+ struct qm_cgr_wr_parm wr_parm_g; -+ struct qm_cgr_wr_parm wr_parm_y; -+ struct qm_cgr_wr_parm wr_parm_r; -+ } __packed cm_config; -+ struct { -+ u8 dnc; -+ u8 dn0; -+ u8 dn1; -+ u64 dnba:40; -+ u8 __reserved3[2]; -+ u16 dnth_0; -+ u8 __reserved4[2]; -+ u16 dnth_1; -+ u8 __reserved5[8]; -+ } __packed dn_config; -+ struct { -+ u8 __reserved3[3]; -+ u64 i_cnt:40; -+ u8 __reserved4[16]; -+ } __packed test_write; -+ }; -+ u8 __reserved5[32]; -+} __packed; -+ -+struct qm_mcc_ceetm_ccgr_query { -+ u8 __reserved1; -+ u16 ccgrid; -+ u8 dcpid; -+ u8 __reserved2[59]; -+} __packed; -+ -+struct qm_mcc_ceetm_cq_peek_pop_xsfdrread { -+ u8 __reserved1; -+ u16 cqid; -+ u8 dcpid; -+ u8 ct; -+ u16 xsfdr; -+ u8 __reserved2[56]; -+} __packed; -+ -+#define CEETM_QUERY_DEQUEUE_STATISTICS 0x00 -+#define CEETM_QUERY_DEQUEUE_CLEAR_STATISTICS 0x01 -+#define CEETM_WRITE_DEQUEUE_STATISTICS 0x02 -+#define CEETM_QUERY_REJECT_STATISTICS 0x03 -+#define CEETM_QUERY_REJECT_CLEAR_STATISTICS 0x04 -+#define CEETM_WRITE_REJECT_STATISTICS 0x05 -+struct qm_mcc_ceetm_statistics_query_write { -+ u8 __reserved1; -+ u16 cid; -+ u8 dcpid; -+ u8 ct; -+ u8 __reserved2[13]; -+ u64 frm_cnt:40; -+ u8 __reserved3[2]; -+ u64 byte_cnt:48; -+ u8 __reserved[32]; -+} __packed; -+ -+struct qm_mc_command { -+ u8 __dont_write_directly__verb; -+ union { -+ struct qm_mcc_initfq initfq; -+ struct qm_mcc_queryfq queryfq; -+ struct qm_mcc_queryfq_np queryfq_np; -+ struct qm_mcc_alterfq alterfq; -+ struct qm_mcc_initcgr initcgr; -+ struct qm_mcc_cgrtestwrite cgrtestwrite; -+ struct qm_mcc_querycgr querycgr; -+ struct qm_mcc_querycongestion querycongestion; -+ struct qm_mcc_querywq querywq; -+ struct qm_mcc_ceetm_lfqmt_config lfqmt_config; -+ struct qm_mcc_ceetm_lfqmt_query lfqmt_query; -+ struct qm_mcc_ceetm_cq_config cq_config; -+ struct qm_mcc_ceetm_cq_query cq_query; -+ struct qm_mcc_ceetm_dct_config dct_config; -+ struct qm_mcc_ceetm_dct_query dct_query; -+ struct qm_mcc_ceetm_class_scheduler_config csch_config; -+ struct qm_mcc_ceetm_class_scheduler_query csch_query; -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_config mst_config; -+ struct qm_mcc_ceetm_mapping_shaper_tcfc_query mst_query; -+ struct qm_mcc_ceetm_ccgr_config ccgr_config; -+ struct qm_mcc_ceetm_ccgr_query ccgr_query; -+ struct qm_mcc_ceetm_cq_peek_pop_xsfdrread cq_ppxr; -+ struct qm_mcc_ceetm_statistics_query_write stats_query_write; -+ }; -+} __packed; -+#define QM_MCC_VERB_VBIT 0x80 -+#define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */ -+#define QM_MCC_VERB_INITFQ_PARKED 0x40 -+#define QM_MCC_VERB_INITFQ_SCHED 0x41 -+#define QM_MCC_VERB_QUERYFQ 0x44 -+#define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */ -+#define QM_MCC_VERB_QUERYWQ 0x46 -+#define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47 -+#define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */ -+#define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */ -+#define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */ -+#define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */ -+#define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */ -+#define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */ -+#define QM_MCC_VERB_INITCGR 0x50 -+#define QM_MCC_VERB_MODIFYCGR 0x51 -+#define QM_MCC_VERB_CGRTESTWRITE 0x52 -+#define QM_MCC_VERB_QUERYCGR 0x58 -+#define QM_MCC_VERB_QUERYCONGESTION 0x59 -+/* INITFQ-specific flags */ -+#define QM_INITFQ_WE_MASK 0x01ff /* 'Write Enable' flags; */ -+#define QM_INITFQ_WE_OAC 0x0100 -+#define QM_INITFQ_WE_ORPC 0x0080 -+#define QM_INITFQ_WE_CGID 0x0040 -+#define QM_INITFQ_WE_FQCTRL 0x0020 -+#define QM_INITFQ_WE_DESTWQ 0x0010 -+#define QM_INITFQ_WE_ICSCRED 0x0008 -+#define QM_INITFQ_WE_TDTHRESH 0x0004 -+#define QM_INITFQ_WE_CONTEXTB 0x0002 -+#define QM_INITFQ_WE_CONTEXTA 0x0001 -+/* INITCGR/MODIFYCGR-specific flags */ -+#define QM_CGR_WE_MASK 0x07ff /* 'Write Enable Mask'; */ -+#define QM_CGR_WE_WR_PARM_G 0x0400 -+#define QM_CGR_WE_WR_PARM_Y 0x0200 -+#define QM_CGR_WE_WR_PARM_R 0x0100 -+#define QM_CGR_WE_WR_EN_G 0x0080 -+#define QM_CGR_WE_WR_EN_Y 0x0040 -+#define QM_CGR_WE_WR_EN_R 0x0020 -+#define QM_CGR_WE_CSCN_EN 0x0010 -+#define QM_CGR_WE_CSCN_TARG 0x0008 -+#define QM_CGR_WE_CSTD_EN 0x0004 -+#define QM_CGR_WE_CS_THRES 0x0002 -+#define QM_CGR_WE_MODE 0x0001 -+ -+/* See 1.5.9.7 CEETM Management Commands */ -+#define QM_CEETM_VERB_LFQMT_CONFIG 0x70 -+#define QM_CEETM_VERB_LFQMT_QUERY 0x71 -+#define QM_CEETM_VERB_CQ_CONFIG 0x72 -+#define QM_CEETM_VERB_CQ_QUERY 0x73 -+#define QM_CEETM_VERB_DCT_CONFIG 0x74 -+#define QM_CEETM_VERB_DCT_QUERY 0x75 -+#define QM_CEETM_VERB_CLASS_SCHEDULER_CONFIG 0x76 -+#define QM_CEETM_VERB_CLASS_SCHEDULER_QUERY 0x77 -+#define QM_CEETM_VERB_MAPPING_SHAPER_TCFC_CONFIG 0x78 -+#define QM_CEETM_VERB_MAPPING_SHAPER_TCFC_QUERY 0x79 -+#define QM_CEETM_VERB_CCGR_CONFIG 0x7A -+#define QM_CEETM_VERB_CCGR_QUERY 0x7B -+#define QM_CEETM_VERB_CQ_PEEK_POP_XFDRREAD 0x7C -+#define QM_CEETM_VERB_STATISTICS_QUERY_WRITE 0x7D -+ -+/* See 1.5.8.5.1: "Initialize FQ" */ -+/* See 1.5.8.5.2: "Query FQ" */ -+/* See 1.5.8.5.3: "Query FQ Non-Programmable Fields" */ -+/* See 1.5.8.5.4: "Alter FQ State Commands " */ -+/* See 1.5.8.6.1: "Initialize/Modify CGR" */ -+/* See 1.5.8.6.2: "CGR Test Write" */ -+/* See 1.5.8.6.3: "Query CGR" */ -+/* See 1.5.8.6.4: "Query Congestion Group State" */ -+struct qm_mcr_initfq { -+ u8 __reserved1[62]; -+} __packed; -+struct qm_mcr_queryfq { -+ u8 __reserved1[8]; -+ struct qm_fqd fqd; /* the FQD fields are here */ -+ u8 __reserved2[30]; -+} __packed; -+struct qm_mcr_queryfq_np { -+ u8 __reserved1; -+ u8 state; /* QM_MCR_NP_STATE_*** */ -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 __reserved2; -+ u32 fqd_link:24; -+ u16 __reserved3:2; -+ u16 odp_seq:14; -+ u16 __reserved4:2; -+ u16 orp_nesn:14; -+ u16 __reserved5:1; -+ u16 orp_ea_hseq:15; -+ u16 __reserved6:1; -+ u16 orp_ea_tseq:15; -+ u8 __reserved7; -+ u32 orp_ea_hptr:24; -+ u8 __reserved8; -+ u32 orp_ea_tptr:24; -+ u8 __reserved9; -+ u32 pfdr_hptr:24; -+ u8 __reserved10; -+ u32 pfdr_tptr:24; -+ u8 __reserved11[5]; -+ u8 __reserved12:7; -+ u8 is:1; -+ u16 ics_surp; -+ u32 byte_cnt; -+ u8 __reserved13; -+ u32 frm_cnt:24; -+ u32 __reserved14; -+ u16 ra1_sfdr; /* QM_MCR_NP_RA1_*** */ -+ u16 ra2_sfdr; /* QM_MCR_NP_RA2_*** */ -+ u16 __reserved15; -+ u16 od1_sfdr; /* QM_MCR_NP_OD1_*** */ -+ u16 od2_sfdr; /* QM_MCR_NP_OD2_*** */ -+ u16 od3_sfdr; /* QM_MCR_NP_OD3_*** */ -+#else -+ u8 __reserved2; -+ u32 fqd_link:24; -+ -+ u16 odp_seq:14; -+ u16 __reserved3:2; -+ -+ u16 orp_nesn:14; -+ u16 __reserved4:2; -+ -+ u16 orp_ea_hseq:15; -+ u16 __reserved5:1; -+ -+ u16 orp_ea_tseq:15; -+ u16 __reserved6:1; -+ -+ u8 __reserved7; -+ u32 orp_ea_hptr:24; -+ -+ u8 __reserved8; -+ u32 orp_ea_tptr:24; -+ -+ u8 __reserved9; -+ u32 pfdr_hptr:24; -+ -+ u8 __reserved10; -+ u32 pfdr_tptr:24; -+ -+ u8 __reserved11[5]; -+ u8 is:1; -+ u8 __reserved12:7; -+ u16 ics_surp; -+ u32 byte_cnt; -+ u8 __reserved13; -+ u32 frm_cnt:24; -+ u32 __reserved14; -+ u16 ra1_sfdr; /* QM_MCR_NP_RA1_*** */ -+ u16 ra2_sfdr; /* QM_MCR_NP_RA2_*** */ -+ u16 __reserved15; -+ u16 od1_sfdr; /* QM_MCR_NP_OD1_*** */ -+ u16 od2_sfdr; /* QM_MCR_NP_OD2_*** */ -+ u16 od3_sfdr; /* QM_MCR_NP_OD3_*** */ -+#endif -+} __packed; -+ -+ -+struct qm_mcr_alterfq { -+ u8 fqs; /* Frame Queue Status */ -+ u8 __reserved1[61]; -+} __packed; -+struct qm_mcr_initcgr { -+ u8 __reserved1[62]; -+} __packed; -+struct qm_mcr_cgrtestwrite { -+ u16 __reserved1; -+ struct __qm_mc_cgr cgr; /* CGR fields */ -+ u8 __reserved2[3]; -+ u32 __reserved3:24; -+ u32 i_bcnt_hi:8;/* high 8-bits of 40-bit "Instant" */ -+ u32 i_bcnt_lo; /* low 32-bits of 40-bit */ -+ u32 __reserved4:24; -+ u32 a_bcnt_hi:8;/* high 8-bits of 40-bit "Average" */ -+ u32 a_bcnt_lo; /* low 32-bits of 40-bit */ -+ u16 lgt; /* Last Group Tick */ -+ u16 wr_prob_g; -+ u16 wr_prob_y; -+ u16 wr_prob_r; -+ u8 __reserved5[8]; -+} __packed; -+struct qm_mcr_querycgr { -+ u16 __reserved1; -+ struct __qm_mc_cgr cgr; /* CGR fields */ -+ u8 __reserved2[3]; -+ union { -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u32 __reserved3:24; -+ u32 i_bcnt_hi:8;/* high 8-bits of 40-bit "Instant" */ -+ u32 i_bcnt_lo; /* low 32-bits of 40-bit */ -+#else -+ u32 i_bcnt_lo; /* low 32-bits of 40-bit */ -+ u32 i_bcnt_hi:8;/* high 8-bits of 40-bit "Instant" */ -+ u32 __reserved3:24; -+#endif -+ }; -+ u64 i_bcnt; -+ }; -+ union { -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u32 __reserved4:24; -+ u32 a_bcnt_hi:8;/* high 8-bits of 40-bit "Average" */ -+ u32 a_bcnt_lo; /* low 32-bits of 40-bit */ -+#else -+ u32 a_bcnt_lo; /* low 32-bits of 40-bit */ -+ u32 a_bcnt_hi:8;/* high 8-bits of 40-bit "Average" */ -+ u32 __reserved4:24; -+#endif -+ }; -+ u64 a_bcnt; -+ }; -+ union { -+ u32 cscn_targ_swp[4]; -+ u8 __reserved5[16]; -+ }; -+} __packed; -+static inline u64 qm_mcr_querycgr_i_get64(const struct qm_mcr_querycgr *q) -+{ -+ return be64_to_cpu(q->i_bcnt); -+} -+static inline u64 qm_mcr_querycgr_a_get64(const struct qm_mcr_querycgr *q) -+{ -+ return be64_to_cpu(q->a_bcnt); -+} -+static inline u64 qm_mcr_cgrtestwrite_i_get64( -+ const struct qm_mcr_cgrtestwrite *q) -+{ -+ return be64_to_cpu(((u64)q->i_bcnt_hi << 32) | (u64)q->i_bcnt_lo); -+} -+static inline u64 qm_mcr_cgrtestwrite_a_get64( -+ const struct qm_mcr_cgrtestwrite *q) -+{ -+ return be64_to_cpu(((u64)q->a_bcnt_hi << 32) | (u64)q->a_bcnt_lo); -+} -+/* Macro, so we compile better if 'v' isn't always 64-bit */ -+#define qm_mcr_querycgr_i_set64(q, v) \ -+ do { \ -+ struct qm_mcr_querycgr *__q931 = (fd); \ -+ __q931->i_bcnt_hi = upper_32_bits(v); \ -+ __q931->i_bcnt_lo = lower_32_bits(v); \ -+ } while (0) -+#define qm_mcr_querycgr_a_set64(q, v) \ -+ do { \ -+ struct qm_mcr_querycgr *__q931 = (fd); \ -+ __q931->a_bcnt_hi = upper_32_bits(v); \ -+ __q931->a_bcnt_lo = lower_32_bits(v); \ -+ } while (0) -+struct __qm_mcr_querycongestion { -+ u32 __state[8]; -+}; -+struct qm_mcr_querycongestion { -+ u8 __reserved[30]; -+ /* Access this struct using QM_MCR_QUERYCONGESTION() */ -+ struct __qm_mcr_querycongestion state; -+} __packed; -+struct qm_mcr_querywq { -+ union { -+ u16 channel_wq; /* ignores wq (3 lsbits) */ -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u16 id:13; /* qm_channel */ -+ u16 __reserved:3; -+#else -+ u16 __reserved:3; -+ u16 id:13; /* qm_channel */ -+#endif -+ } __packed channel; -+ }; -+ u8 __reserved[28]; -+ u32 wq_len[8]; -+} __packed; -+ -+/* QMAN CEETM Management Command Response */ -+struct qm_mcr_ceetm_lfqmt_config { -+ u8 __reserved1[62]; -+} __packed; -+struct qm_mcr_ceetm_lfqmt_query { -+ u8 __reserved1[8]; -+ u16 cqid; -+ u8 __reserved2[2]; -+ u16 dctidx; -+ u8 __reserved3[2]; -+ u16 ccgid; -+ u8 __reserved4[44]; -+} __packed; -+ -+struct qm_mcr_ceetm_cq_config { -+ u8 __reserved1[62]; -+} __packed; -+ -+struct qm_mcr_ceetm_cq_query { -+ u8 __reserved1[4]; -+ u16 ccgid; -+ u16 state; -+ u32 pfdr_hptr:24; -+ u32 pfdr_tptr:24; -+ u16 od1_xsfdr; -+ u16 od2_xsfdr; -+ u16 od3_xsfdr; -+ u16 od4_xsfdr; -+ u16 od5_xsfdr; -+ u16 od6_xsfdr; -+ u16 ra1_xsfdr; -+ u16 ra2_xsfdr; -+ u8 __reserved2; -+ u32 frm_cnt:24; -+ u8 __reserved333[28]; -+} __packed; -+ -+struct qm_mcr_ceetm_dct_config { -+ u8 __reserved1[62]; -+} __packed; -+ -+struct qm_mcr_ceetm_dct_query { -+ u8 __reserved1[18]; -+ u32 context_b; -+ u64 context_a; -+ u8 __reserved2[32]; -+} __packed; -+ -+struct qm_mcr_ceetm_class_scheduler_config { -+ u8 __reserved1[62]; -+} __packed; -+ -+struct qm_mcr_ceetm_class_scheduler_query { -+ u8 __reserved1[9]; -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 gpc_reserved:1; -+ u8 gpc_combine_flag:1; -+ u8 gpc_prio_b:3; -+ u8 gpc_prio_a:3; -+#else -+ u8 gpc_prio_a:3; -+ u8 gpc_prio_b:3; -+ u8 gpc_combine_flag:1; -+ u8 gpc_reserved:1; -+#endif -+ u16 crem; -+ u16 erem; -+ u8 w[8]; -+ u8 __reserved2[5]; -+ u32 wbfslist:24; -+ u32 d8; -+ u32 d9; -+ u32 d10; -+ u32 d11; -+ u32 d12; -+ u32 d13; -+ u32 d14; -+ u32 d15; -+} __packed; -+ -+struct qm_mcr_ceetm_mapping_shaper_tcfc_config { -+ u16 cid; -+ u8 __reserved2[60]; -+} __packed; -+ -+struct qm_mcr_ceetm_mapping_shaper_tcfc_query { -+ u16 cid; -+ u8 __reserved1; -+ union { -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 map_shaped:1; -+ u8 map_reserved:4; -+ u8 map_lni_id:3; -+#else -+ u8 map_lni_id:3; -+ u8 map_reserved:4; -+ u8 map_shaped:1; -+#endif -+ u8 __reserved2[58]; -+ } __packed channel_mapping_query; -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 map_reserved:5; -+ u8 map_lni_id:3; -+#else -+ u8 map_lni_id:3; -+ u8 map_reserved:5; -+#endif -+ u8 __reserved2[58]; -+ } __packed sp_mapping_query; -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 cpl:1; -+ u8 cpl_reserved:2; -+ u8 oal:5; -+#else -+ u8 oal:5; -+ u8 cpl_reserved:2; -+ u8 cpl:1; -+#endif -+ u32 crtcr:24; -+ u32 ertcr:24; -+ u16 crtbl; -+ u16 ertbl; -+ u8 mps; -+ u8 __reserved2[15]; -+ u32 crat; -+ u32 erat; -+ u8 __reserved3[24]; -+ } __packed shaper_query; -+ struct { -+ u8 __reserved1[11]; -+ u64 lnitcfcc; -+ u8 __reserved3[40]; -+ } __packed tcfc_query; -+ }; -+} __packed; -+ -+struct qm_mcr_ceetm_ccgr_config { -+ u8 __reserved1[46]; -+ union { -+ u8 __reserved2[8]; -+ struct { -+ u16 timestamp; -+ u16 wr_porb_g; -+ u16 wr_prob_y; -+ u16 wr_prob_r; -+ } __packed test_write; -+ }; -+ u8 __reserved3[8]; -+} __packed; -+ -+struct qm_mcr_ceetm_ccgr_query { -+ u8 __reserved1[6]; -+ union { -+ struct { -+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -+ u8 ctl_reserved:1; -+ u8 ctl_wr_en_g:1; -+ u8 ctl_wr_en_y:1; -+ u8 ctl_wr_en_r:1; -+ u8 ctl_td_en:1; -+ u8 ctl_td_mode:1; -+ u8 ctl_cscn_en:1; -+ u8 ctl_mode:1; -+#else -+ u8 ctl_mode:1; -+ u8 ctl_cscn_en:1; -+ u8 ctl_td_mode:1; -+ u8 ctl_td_en:1; -+ u8 ctl_wr_en_r:1; -+ u8 ctl_wr_en_y:1; -+ u8 ctl_wr_en_g:1; -+ u8 ctl_reserved:1; -+#endif -+ u8 cdv; -+ u8 __reserved2[2]; -+ u8 oal; -+ u8 __reserved3; -+ struct qm_cgr_cs_thres cs_thres; -+ struct qm_cgr_cs_thres cs_thres_x; -+ struct qm_cgr_cs_thres td_thres; -+ struct qm_cgr_wr_parm wr_parm_g; -+ struct qm_cgr_wr_parm wr_parm_y; -+ struct qm_cgr_wr_parm wr_parm_r; -+ u16 cscn_targ_dcp; -+ u8 dcp_lsn; -+ u64 i_cnt:40; -+ u8 __reserved4[3]; -+ u64 a_cnt:40; -+ u32 cscn_targ_swp[4]; -+ } __packed cm_query; -+ struct { -+ u8 dnc; -+ u8 dn0; -+ u8 dn1; -+ u64 dnba:40; -+ u8 __reserved2[2]; -+ u16 dnth_0; -+ u8 __reserved3[2]; -+ u16 dnth_1; -+ u8 __reserved4[10]; -+ u16 dnacc_0; -+ u8 __reserved5[2]; -+ u16 dnacc_1; -+ u8 __reserved6[24]; -+ } __packed dn_query; -+ struct { -+ u8 __reserved2[24]; -+ struct __qm_mcr_querycongestion state; -+ } __packed congestion_state; -+ -+ }; -+} __packed; -+ -+struct qm_mcr_ceetm_cq_peek_pop_xsfdrread { -+ u8 stat; -+ u8 __reserved1[11]; -+ u16 dctidx; -+ struct qm_fd fd; -+ u8 __reserved2[32]; -+} __packed; -+ -+struct qm_mcr_ceetm_statistics_query { -+ u8 __reserved1[17]; -+ u64 frm_cnt:40; -+ u8 __reserved2[2]; -+ u64 byte_cnt:48; -+ u8 __reserved3[32]; -+} __packed; -+ -+struct qm_mc_result { -+ u8 verb; -+ u8 result; -+ union { -+ struct qm_mcr_initfq initfq; -+ struct qm_mcr_queryfq queryfq; -+ struct qm_mcr_queryfq_np queryfq_np; -+ struct qm_mcr_alterfq alterfq; -+ struct qm_mcr_initcgr initcgr; -+ struct qm_mcr_cgrtestwrite cgrtestwrite; -+ struct qm_mcr_querycgr querycgr; -+ struct qm_mcr_querycongestion querycongestion; -+ struct qm_mcr_querywq querywq; -+ struct qm_mcr_ceetm_lfqmt_config lfqmt_config; -+ struct qm_mcr_ceetm_lfqmt_query lfqmt_query; -+ struct qm_mcr_ceetm_cq_config cq_config; -+ struct qm_mcr_ceetm_cq_query cq_query; -+ struct qm_mcr_ceetm_dct_config dct_config; -+ struct qm_mcr_ceetm_dct_query dct_query; -+ struct qm_mcr_ceetm_class_scheduler_config csch_config; -+ struct qm_mcr_ceetm_class_scheduler_query csch_query; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_config mst_config; -+ struct qm_mcr_ceetm_mapping_shaper_tcfc_query mst_query; -+ struct qm_mcr_ceetm_ccgr_config ccgr_config; -+ struct qm_mcr_ceetm_ccgr_query ccgr_query; -+ struct qm_mcr_ceetm_cq_peek_pop_xsfdrread cq_ppxr; -+ struct qm_mcr_ceetm_statistics_query stats_query; -+ }; -+} __packed; -+ -+#define QM_MCR_VERB_RRID 0x80 -+#define QM_MCR_VERB_MASK QM_MCC_VERB_MASK -+#define QM_MCR_VERB_INITFQ_PARKED QM_MCC_VERB_INITFQ_PARKED -+#define QM_MCR_VERB_INITFQ_SCHED QM_MCC_VERB_INITFQ_SCHED -+#define QM_MCR_VERB_QUERYFQ QM_MCC_VERB_QUERYFQ -+#define QM_MCR_VERB_QUERYFQ_NP QM_MCC_VERB_QUERYFQ_NP -+#define QM_MCR_VERB_QUERYWQ QM_MCC_VERB_QUERYWQ -+#define QM_MCR_VERB_QUERYWQ_DEDICATED QM_MCC_VERB_QUERYWQ_DEDICATED -+#define QM_MCR_VERB_ALTER_SCHED QM_MCC_VERB_ALTER_SCHED -+#define QM_MCR_VERB_ALTER_FE QM_MCC_VERB_ALTER_FE -+#define QM_MCR_VERB_ALTER_RETIRE QM_MCC_VERB_ALTER_RETIRE -+#define QM_MCR_VERB_ALTER_OOS QM_MCC_VERB_ALTER_OOS -+#define QM_MCR_RESULT_NULL 0x00 -+#define QM_MCR_RESULT_OK 0xf0 -+#define QM_MCR_RESULT_ERR_FQID 0xf1 -+#define QM_MCR_RESULT_ERR_FQSTATE 0xf2 -+#define QM_MCR_RESULT_ERR_NOTEMPTY 0xf3 /* OOS fails if FQ is !empty */ -+#define QM_MCR_RESULT_ERR_BADCHANNEL 0xf4 -+#define QM_MCR_RESULT_PENDING 0xf8 -+#define QM_MCR_RESULT_ERR_BADCOMMAND 0xff -+#define QM_MCR_NP_STATE_FE 0x10 -+#define QM_MCR_NP_STATE_R 0x08 -+#define QM_MCR_NP_STATE_MASK 0x07 /* Reads FQD::STATE; */ -+#define QM_MCR_NP_STATE_OOS 0x00 -+#define QM_MCR_NP_STATE_RETIRED 0x01 -+#define QM_MCR_NP_STATE_TEN_SCHED 0x02 -+#define QM_MCR_NP_STATE_TRU_SCHED 0x03 -+#define QM_MCR_NP_STATE_PARKED 0x04 -+#define QM_MCR_NP_STATE_ACTIVE 0x05 -+#define QM_MCR_NP_PTR_MASK 0x07ff /* for RA[12] & OD[123] */ -+#define QM_MCR_NP_RA1_NRA(v) (((v) >> 14) & 0x3) /* FQD::NRA */ -+#define QM_MCR_NP_RA2_IT(v) (((v) >> 14) & 0x1) /* FQD::IT */ -+#define QM_MCR_NP_OD1_NOD(v) (((v) >> 14) & 0x3) /* FQD::NOD */ -+#define QM_MCR_NP_OD3_NPC(v) (((v) >> 14) & 0x3) /* FQD::NPC */ -+#define QM_MCR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */ -+#define QM_MCR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */ -+/* This extracts the state for congestion group 'n' from a query response. -+ * Eg. -+ * u8 cgr = [...]; -+ * struct qm_mc_result *res = [...]; -+ * printf("congestion group %d congestion state: %d\n", cgr, -+ * QM_MCR_QUERYCONGESTION(&res->querycongestion.state, cgr)); -+ */ -+#define __CGR_WORD(num) (num >> 5) -+#define __CGR_SHIFT(num) (num & 0x1f) -+#define __CGR_NUM (sizeof(struct __qm_mcr_querycongestion) << 3) -+static inline int QM_MCR_QUERYCONGESTION(struct __qm_mcr_querycongestion *p, -+ u8 cgr) -+{ -+ return be32_to_cpu(p->__state[__CGR_WORD(cgr)]) & -+ (0x80000000 >> __CGR_SHIFT(cgr)); -+} -+ -+ -+/*********************/ -+/* Utility interface */ -+/*********************/ -+ -+/* Represents an allocator over a range of FQIDs. NB, accesses are not locked, -+ * spinlock them yourself if needed. */ -+struct qman_fqid_pool; -+ -+/* Create/destroy a FQID pool, num must be a multiple of 32. NB, _destroy() -+ * always succeeds, but returns non-zero if there were "leaked" FQID -+ * allocations. */ -+struct qman_fqid_pool *qman_fqid_pool_create(u32 fqid_start, u32 num); -+int qman_fqid_pool_destroy(struct qman_fqid_pool *pool); -+/* Alloc/free a FQID from the range. _alloc() returns zero for success. */ -+int qman_fqid_pool_alloc(struct qman_fqid_pool *pool, u32 *fqid); -+void qman_fqid_pool_free(struct qman_fqid_pool *pool, u32 fqid); -+u32 qman_fqid_pool_used(struct qman_fqid_pool *pool); -+ -+/*******************************************************************/ -+/* Managed (aka "shared" or "mux/demux") portal, high-level i/face */ -+/*******************************************************************/ -+ -+ /* Portal and Frame Queues */ -+ /* ----------------------- */ -+/* Represents a managed portal */ -+struct qman_portal; -+ -+/* This object type represents Qman frame queue descriptors (FQD), it is -+ * cacheline-aligned, and initialised by qman_create_fq(). The structure is -+ * defined further down. */ -+struct qman_fq; -+ -+/* This object type represents a Qman congestion group, it is defined further -+ * down. */ -+struct qman_cgr; -+ -+struct qman_portal_config { -+ /* If the caller enables DQRR stashing (and thus wishes to operate the -+ * portal from only one cpu), this is the logical CPU that the portal -+ * will stash to. Whether stashing is enabled or not, this setting is -+ * also used for any "core-affine" portals, ie. default portals -+ * associated to the corresponding cpu. -1 implies that there is no core -+ * affinity configured. */ -+ int cpu; -+ /* portal interrupt line */ -+ int irq; -+ /* the unique index of this portal */ -+ u32 index; -+ /* Is this portal shared? (If so, it has coarser locking and demuxes -+ * processing on behalf of other CPUs.) */ -+ int is_shared; -+ /* The portal's dedicated channel id, use this value for initialising -+ * frame queues to target this portal when scheduled. */ -+ u16 channel; -+ /* A mask of which pool channels this portal has dequeue access to -+ * (using QM_SDQCR_CHANNELS_POOL(n) for the bitmask) */ -+ u32 pools; -+}; -+ -+/* This enum, and the callback type that returns it, are used when handling -+ * dequeued frames via DQRR. Note that for "null" callbacks registered with the -+ * portal object (for handling dequeues that do not demux because contextB is -+ * NULL), the return value *MUST* be qman_cb_dqrr_consume. */ -+enum qman_cb_dqrr_result { -+ /* DQRR entry can be consumed */ -+ qman_cb_dqrr_consume, -+ /* Like _consume, but requests parking - FQ must be held-active */ -+ qman_cb_dqrr_park, -+ /* Does not consume, for DCA mode only. This allows out-of-order -+ * consumes by explicit calls to qman_dca() and/or the use of implicit -+ * DCA via EQCR entries. */ -+ qman_cb_dqrr_defer, -+ /* Stop processing without consuming this ring entry. Exits the current -+ * qman_poll_dqrr() or interrupt-handling, as appropriate. If within an -+ * interrupt handler, the callback would typically call -+ * qman_irqsource_remove(QM_PIRQ_DQRI) before returning this value, -+ * otherwise the interrupt will reassert immediately. */ -+ qman_cb_dqrr_stop, -+ /* Like qman_cb_dqrr_stop, but consumes the current entry. */ -+ qman_cb_dqrr_consume_stop -+}; -+typedef enum qman_cb_dqrr_result (*qman_cb_dqrr)(struct qman_portal *qm, -+ struct qman_fq *fq, -+ const struct qm_dqrr_entry *dqrr); -+ -+/* This callback type is used when handling ERNs, FQRNs and FQRLs via MR. They -+ * are always consumed after the callback returns. */ -+typedef void (*qman_cb_mr)(struct qman_portal *qm, struct qman_fq *fq, -+ const struct qm_mr_entry *msg); -+ -+/* This callback type is used when handling DCP ERNs */ -+typedef void (*qman_cb_dc_ern)(struct qman_portal *qm, -+ const struct qm_mr_entry *msg); -+ -+/* s/w-visible states. Ie. tentatively scheduled + truly scheduled + active + -+ * held-active + held-suspended are just "sched". Things like "retired" will not -+ * be assumed until it is complete (ie. QMAN_FQ_STATE_CHANGING is set until -+ * then, to indicate it's completing and to gate attempts to retry the retire -+ * command). Note, park commands do not set QMAN_FQ_STATE_CHANGING because it's -+ * technically impossible in the case of enqueue DCAs (which refer to DQRR ring -+ * index rather than the FQ that ring entry corresponds to), so repeated park -+ * commands are allowed (if you're silly enough to try) but won't change FQ -+ * state, and the resulting park notifications move FQs from "sched" to -+ * "parked". */ -+enum qman_fq_state { -+ qman_fq_state_oos, -+ qman_fq_state_parked, -+ qman_fq_state_sched, -+ qman_fq_state_retired -+}; -+ -+/* Frame queue objects (struct qman_fq) are stored within memory passed to -+ * qman_create_fq(), as this allows stashing of caller-provided demux callback -+ * pointers at no extra cost to stashing of (driver-internal) FQ state. If the -+ * caller wishes to add per-FQ state and have it benefit from dequeue-stashing, -+ * they should; -+ * -+ * (a) extend the qman_fq structure with their state; eg. -+ * -+ * // myfq is allocated and driver_fq callbacks filled in; -+ * struct my_fq { -+ * struct qman_fq base; -+ * int an_extra_field; -+ * [ ... add other fields to be associated with each FQ ...] -+ * } *myfq = some_my_fq_allocator(); -+ * struct qman_fq *fq = qman_create_fq(fqid, flags, &myfq->base); -+ * -+ * // in a dequeue callback, access extra fields from 'fq' via a cast; -+ * struct my_fq *myfq = (struct my_fq *)fq; -+ * do_something_with(myfq->an_extra_field); -+ * [...] -+ * -+ * (b) when and if configuring the FQ for context stashing, specify how ever -+ * many cachelines are required to stash 'struct my_fq', to accelerate not -+ * only the Qman driver but the callback as well. -+ */ -+ -+struct qman_fq_cb { -+ qman_cb_dqrr dqrr; /* for dequeued frames */ -+ qman_cb_mr ern; /* for s/w ERNs */ -+ qman_cb_mr fqs; /* frame-queue state changes*/ -+}; -+ -+struct qman_fq { -+ /* Caller of qman_create_fq() provides these demux callbacks */ -+ struct qman_fq_cb cb; -+ /* These are internal to the driver, don't touch. In particular, they -+ * may change, be removed, or extended (so you shouldn't rely on -+ * sizeof(qman_fq) being a constant). */ -+ spinlock_t fqlock; -+ u32 fqid; -+ volatile unsigned long flags; -+ enum qman_fq_state state; -+ int cgr_groupid; -+ struct rb_node node; -+#ifdef CONFIG_FSL_QMAN_FQ_LOOKUP -+ u32 key; -+#endif -+}; -+ -+/* This callback type is used when handling congestion group entry/exit. -+ * 'congested' is non-zero on congestion-entry, and zero on congestion-exit. */ -+typedef void (*qman_cb_cgr)(struct qman_portal *qm, -+ struct qman_cgr *cgr, int congested); -+ -+struct qman_cgr { -+ /* Set these prior to qman_create_cgr() */ -+ u32 cgrid; /* 0..255, but u32 to allow specials like -1, 256, etc.*/ -+ qman_cb_cgr cb; -+ /* These are private to the driver */ -+ u16 chan; /* portal channel this object is created on */ -+ struct list_head node; -+}; -+ -+/* Flags to qman_create_fq() */ -+#define QMAN_FQ_FLAG_NO_ENQUEUE 0x00000001 /* can't enqueue */ -+#define QMAN_FQ_FLAG_NO_MODIFY 0x00000002 /* can only enqueue */ -+#define QMAN_FQ_FLAG_TO_DCPORTAL 0x00000004 /* consumed by CAAM/PME/Fman */ -+#define QMAN_FQ_FLAG_LOCKED 0x00000008 /* multi-core locking */ -+#define QMAN_FQ_FLAG_AS_IS 0x00000010 /* query h/w state */ -+#define QMAN_FQ_FLAG_DYNAMIC_FQID 0x00000020 /* (de)allocate fqid */ -+ -+/* Flags to qman_destroy_fq() */ -+#define QMAN_FQ_DESTROY_PARKED 0x00000001 /* FQ can be parked or OOS */ -+ -+/* Flags from qman_fq_state() */ -+#define QMAN_FQ_STATE_CHANGING 0x80000000 /* 'state' is changing */ -+#define QMAN_FQ_STATE_NE 0x40000000 /* retired FQ isn't empty */ -+#define QMAN_FQ_STATE_ORL 0x20000000 /* retired FQ has ORL */ -+#define QMAN_FQ_STATE_BLOCKOOS 0xe0000000 /* if any are set, no OOS */ -+#define QMAN_FQ_STATE_CGR_EN 0x10000000 /* CGR enabled */ -+#define QMAN_FQ_STATE_VDQCR 0x08000000 /* being volatile dequeued */ -+ -+/* Flags to qman_init_fq() */ -+#define QMAN_INITFQ_FLAG_SCHED 0x00000001 /* schedule rather than park */ -+#define QMAN_INITFQ_FLAG_LOCAL 0x00000004 /* set dest portal */ -+ -+/* Flags to qman_volatile_dequeue() */ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+#define QMAN_VOLATILE_FLAG_WAIT 0x00000001 /* wait if VDQCR is in use */ -+#define QMAN_VOLATILE_FLAG_WAIT_INT 0x00000002 /* if wait, interruptible? */ -+#define QMAN_VOLATILE_FLAG_FINISH 0x00000004 /* wait till VDQCR completes */ -+#endif -+ -+/* Flags to qman_enqueue(). NB, the strange numbering is to align with hardware, -+ * bit-wise. (NB: the PME API is sensitive to these precise numberings too, so -+ * any change here should be audited in PME.) */ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT -+#define QMAN_ENQUEUE_FLAG_WAIT 0x00010000 /* wait if EQCR is full */ -+#define QMAN_ENQUEUE_FLAG_WAIT_INT 0x00020000 /* if wait, interruptible? */ -+#ifdef CONFIG_FSL_DPA_CAN_WAIT_SYNC -+#define QMAN_ENQUEUE_FLAG_WAIT_SYNC 0x00000004 /* if wait, until consumed? */ -+#endif -+#endif -+#define QMAN_ENQUEUE_FLAG_WATCH_CGR 0x00080000 /* watch congestion state */ -+#define QMAN_ENQUEUE_FLAG_DCA 0x00008000 /* perform enqueue-DCA */ -+#define QMAN_ENQUEUE_FLAG_DCA_PARK 0x00004000 /* If DCA, requests park */ -+#define QMAN_ENQUEUE_FLAG_DCA_PTR(p) /* If DCA, p is DQRR entry */ \ -+ (((u32)(p) << 2) & 0x00000f00) -+#define QMAN_ENQUEUE_FLAG_C_GREEN 0x00000000 /* choose one C_*** flag */ -+#define QMAN_ENQUEUE_FLAG_C_YELLOW 0x00000008 -+#define QMAN_ENQUEUE_FLAG_C_RED 0x00000010 -+#define QMAN_ENQUEUE_FLAG_C_OVERRIDE 0x00000018 -+/* For the ORP-specific qman_enqueue_orp() variant; -+ * - this flag indicates "Not Last In Sequence", ie. all but the final fragment -+ * of a frame. */ -+#define QMAN_ENQUEUE_FLAG_NLIS 0x01000000 -+/* - this flag performs no enqueue but fills in an ORP sequence number that -+ * would otherwise block it (eg. if a frame has been dropped). */ -+#define QMAN_ENQUEUE_FLAG_HOLE 0x02000000 -+/* - this flag performs no enqueue but advances NESN to the given sequence -+ * number. */ -+#define QMAN_ENQUEUE_FLAG_NESN 0x04000000 -+ -+/* Flags to qman_modify_cgr() */ -+#define QMAN_CGR_FLAG_USE_INIT 0x00000001 -+#define QMAN_CGR_MODE_FRAME 0x00000001 -+ -+ /* Portal Management */ -+ /* ----------------- */ -+/** -+ * qman_get_portal_config - get portal configuration settings -+ * -+ * This returns a read-only view of the current cpu's affine portal settings. -+ */ -+const struct qman_portal_config *qman_get_portal_config(void); -+ -+/** -+ * qman_irqsource_get - return the portal work that is interrupt-driven -+ * -+ * Returns a bitmask of QM_PIRQ_**I processing sources that are currently -+ * enabled for interrupt handling on the current cpu's affine portal. These -+ * sources will trigger the portal interrupt and the interrupt handler (or a -+ * tasklet/bottom-half it defers to) will perform the corresponding processing -+ * work. The qman_poll_***() functions will only process sources that are not in -+ * this bitmask. If the current CPU is sharing a portal hosted on another CPU, -+ * this always returns zero. -+ */ -+u32 qman_irqsource_get(void); -+ -+/** -+ * qman_irqsource_add - add processing sources to be interrupt-driven -+ * @bits: bitmask of QM_PIRQ_**I processing sources -+ * -+ * Adds processing sources that should be interrupt-driven (rather than -+ * processed via qman_poll_***() functions). Returns zero for success, or -+ * -EINVAL if the current CPU is sharing a portal hosted on another CPU. -+ */ -+int qman_irqsource_add(u32 bits); -+ -+/** -+ * qman_irqsource_remove - remove processing sources from being interrupt-driven -+ * @bits: bitmask of QM_PIRQ_**I processing sources -+ * -+ * Removes processing sources from being interrupt-driven, so that they will -+ * instead be processed via qman_poll_***() functions. Returns zero for success, -+ * or -EINVAL if the current CPU is sharing a portal hosted on another CPU. -+ */ -+int qman_irqsource_remove(u32 bits); -+ -+/** -+ * qman_affine_cpus - return a mask of cpus that have affine portals -+ */ -+const cpumask_t *qman_affine_cpus(void); -+ -+/** -+ * qman_affine_channel - return the channel ID of an portal -+ * @cpu: the cpu whose affine portal is the subject of the query -+ * -+ * If @cpu is -1, the affine portal for the current CPU will be used. It is a -+ * bug to call this function for any value of @cpu (other than -1) that is not a -+ * member of the mask returned from qman_affine_cpus(). -+ */ -+u16 qman_affine_channel(int cpu); -+ -+/** -+ * qman_get_affine_portal - return the portal pointer affine to cpu -+ * @cpu: the cpu whose affine portal is the subject of the query -+ * -+ */ -+void *qman_get_affine_portal(int cpu); -+ -+/** -+ * qman_poll_dqrr - process DQRR (fast-path) entries -+ * @limit: the maximum number of DQRR entries to process -+ * -+ * Use of this function requires that DQRR processing not be interrupt-driven. -+ * Ie. the value returned by qman_irqsource_get() should not include -+ * QM_PIRQ_DQRI. If the current CPU is sharing a portal hosted on another CPU, -+ * this function will return -EINVAL, otherwise the return value is >=0 and -+ * represents the number of DQRR entries processed. -+ */ -+int qman_poll_dqrr(unsigned int limit); -+ -+/** -+ * qman_poll_slow - process anything (except DQRR) that isn't interrupt-driven. -+ * -+ * This function does any portal processing that isn't interrupt-driven. If the -+ * current CPU is sharing a portal hosted on another CPU, this function will -+ * return (u32)-1, otherwise the return value is a bitmask of QM_PIRQ_* sources -+ * indicating what interrupt sources were actually processed by the call. -+ */ -+u32 qman_poll_slow(void); -+ -+/** -+ * qman_poll - legacy wrapper for qman_poll_dqrr() and qman_poll_slow() -+ * -+ * Dispatcher logic on a cpu can use this to trigger any maintenance of the -+ * affine portal. There are two classes of portal processing in question; -+ * fast-path (which involves demuxing dequeue ring (DQRR) entries and tracking -+ * enqueue ring (EQCR) consumption), and slow-path (which involves EQCR -+ * thresholds, congestion state changes, etc). This function does whatever -+ * processing is not triggered by interrupts. -+ * -+ * Note, if DQRR and some slow-path processing are poll-driven (rather than -+ * interrupt-driven) then this function uses a heuristic to determine how often -+ * to run slow-path processing - as slow-path processing introduces at least a -+ * minimum latency each time it is run, whereas fast-path (DQRR) processing is -+ * close to zero-cost if there is no work to be done. Applications can tune this -+ * behaviour themselves by using qman_poll_dqrr() and qman_poll_slow() directly -+ * rather than going via this wrapper. -+ */ -+void qman_poll(void); -+ -+/** -+ * qman_stop_dequeues - Stop h/w dequeuing to the s/w portal -+ * -+ * Disables DQRR processing of the portal. This is reference-counted, so -+ * qman_start_dequeues() must be called as many times as qman_stop_dequeues() to -+ * truly re-enable dequeuing. -+ */ -+void qman_stop_dequeues(void); -+ -+/** -+ * qman_start_dequeues - (Re)start h/w dequeuing to the s/w portal -+ * -+ * Enables DQRR processing of the portal. This is reference-counted, so -+ * qman_start_dequeues() must be called as many times as qman_stop_dequeues() to -+ * truly re-enable dequeuing. -+ */ -+void qman_start_dequeues(void); -+ -+/** -+ * qman_static_dequeue_add - Add pool channels to the portal SDQCR -+ * @pools: bit-mask of pool channels, using QM_SDQCR_CHANNELS_POOL(n) -+ * -+ * Adds a set of pool channels to the portal's static dequeue command register -+ * (SDQCR). The requested pools are limited to those the portal has dequeue -+ * access to. -+ */ -+void qman_static_dequeue_add(u32 pools); -+ -+/** -+ * qman_static_dequeue_del - Remove pool channels from the portal SDQCR -+ * @pools: bit-mask of pool channels, using QM_SDQCR_CHANNELS_POOL(n) -+ * -+ * Removes a set of pool channels from the portal's static dequeue command -+ * register (SDQCR). The requested pools are limited to those the portal has -+ * dequeue access to. -+ */ -+void qman_static_dequeue_del(u32 pools); -+ -+/** -+ * qman_static_dequeue_get - return the portal's current SDQCR -+ * -+ * Returns the portal's current static dequeue command register (SDQCR). The -+ * entire register is returned, so if only the currently-enabled pool channels -+ * are desired, mask the return value with QM_SDQCR_CHANNELS_POOL_MASK. -+ */ -+u32 qman_static_dequeue_get(void); -+ -+/** -+ * qman_dca - Perform a Discrete Consumption Acknowledgement -+ * @dq: the DQRR entry to be consumed -+ * @park_request: indicates whether the held-active @fq should be parked -+ * -+ * Only allowed in DCA-mode portals, for DQRR entries whose handler callback had -+ * previously returned 'qman_cb_dqrr_defer'. NB, as with the other APIs, this -+ * does not take a 'portal' argument but implies the core affine portal from the -+ * cpu that is currently executing the function. For reasons of locking, this -+ * function must be called from the same CPU as that which processed the DQRR -+ * entry in the first place. -+ */ -+void qman_dca(struct qm_dqrr_entry *dq, int park_request); -+ -+/** -+ * qman_eqcr_is_empty - Determine if portal's EQCR is empty -+ * -+ * For use in situations where a cpu-affine caller needs to determine when all -+ * enqueues for the local portal have been processed by Qman but can't use the -+ * QMAN_ENQUEUE_FLAG_WAIT_SYNC flag to do this from the final qman_enqueue(). -+ * The function forces tracking of EQCR consumption (which normally doesn't -+ * happen until enqueue processing needs to find space to put new enqueue -+ * commands), and returns zero if the ring still has unprocessed entries, -+ * non-zero if it is empty. -+ */ -+int qman_eqcr_is_empty(void); -+ -+/** -+ * qman_set_dc_ern - Set the handler for DCP enqueue rejection notifications -+ * @handler: callback for processing DCP ERNs -+ * @affine: whether this handler is specific to the locally affine portal -+ * -+ * If a hardware block's interface to Qman (ie. its direct-connect portal, or -+ * DCP) is configured not to receive enqueue rejections, then any enqueues -+ * through that DCP that are rejected will be sent to a given software portal. -+ * If @affine is non-zero, then this handler will only be used for DCP ERNs -+ * received on the portal affine to the current CPU. If multiple CPUs share a -+ * portal and they all call this function, they will be setting the handler for -+ * the same portal! If @affine is zero, then this handler will be global to all -+ * portals handled by this instance of the driver. Only those portals that do -+ * not have their own affine handler will use the global handler. -+ */ -+void qman_set_dc_ern(qman_cb_dc_ern handler, int affine); -+ -+ /* FQ management */ -+ /* ------------- */ -+/** -+ * qman_create_fq - Allocates a FQ -+ * @fqid: the index of the FQD to encapsulate, must be "Out of Service" -+ * @flags: bit-mask of QMAN_FQ_FLAG_*** options -+ * @fq: memory for storing the 'fq', with callbacks filled in -+ * -+ * Creates a frame queue object for the given @fqid, unless the -+ * QMAN_FQ_FLAG_DYNAMIC_FQID flag is set in @flags, in which case a FQID is -+ * dynamically allocated (or the function fails if none are available). Once -+ * created, the caller should not touch the memory at 'fq' except as extended to -+ * adjacent memory for user-defined fields (see the definition of "struct -+ * qman_fq" for more info). NO_MODIFY is only intended for enqueuing to -+ * pre-existing frame-queues that aren't to be otherwise interfered with, it -+ * prevents all other modifications to the frame queue. The TO_DCPORTAL flag -+ * causes the driver to honour any contextB modifications requested in the -+ * qm_init_fq() API, as this indicates the frame queue will be consumed by a -+ * direct-connect portal (PME, CAAM, or Fman). When frame queues are consumed by -+ * software portals, the contextB field is controlled by the driver and can't be -+ * modified by the caller. If the AS_IS flag is specified, management commands -+ * will be used on portal @p to query state for frame queue @fqid and construct -+ * a frame queue object based on that, rather than assuming/requiring that it be -+ * Out of Service. -+ */ -+int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq); -+ -+/** -+ * qman_destroy_fq - Deallocates a FQ -+ * @fq: the frame queue object to release -+ * @flags: bit-mask of QMAN_FQ_FREE_*** options -+ * -+ * The memory for this frame queue object ('fq' provided in qman_create_fq()) is -+ * not deallocated but the caller regains ownership, to do with as desired. The -+ * FQ must be in the 'out-of-service' state unless the QMAN_FQ_FREE_PARKED flag -+ * is specified, in which case it may also be in the 'parked' state. -+ */ -+void qman_destroy_fq(struct qman_fq *fq, u32 flags); -+ -+/** -+ * qman_fq_fqid - Queries the frame queue ID of a FQ object -+ * @fq: the frame queue object to query -+ */ -+u32 qman_fq_fqid(struct qman_fq *fq); -+ -+/** -+ * qman_fq_state - Queries the state of a FQ object -+ * @fq: the frame queue object to query -+ * @state: pointer to state enum to return the FQ scheduling state -+ * @flags: pointer to state flags to receive QMAN_FQ_STATE_*** bitmask -+ * -+ * Queries the state of the FQ object, without performing any h/w commands. -+ * This captures the state, as seen by the driver, at the time the function -+ * executes. -+ */ -+void qman_fq_state(struct qman_fq *fq, enum qman_fq_state *state, u32 *flags); -+ -+/** -+ * qman_init_fq - Initialises FQ fields, leaves the FQ "parked" or "scheduled" -+ * @fq: the frame queue object to modify, must be 'parked' or new. -+ * @flags: bit-mask of QMAN_INITFQ_FLAG_*** options -+ * @opts: the FQ-modification settings, as defined in the low-level API -+ * -+ * The @opts parameter comes from the low-level portal API. Select -+ * QMAN_INITFQ_FLAG_SCHED in @flags to cause the frame queue to be scheduled -+ * rather than parked. NB, @opts can be NULL. -+ * -+ * Note that some fields and options within @opts may be ignored or overwritten -+ * by the driver; -+ * 1. the 'count' and 'fqid' fields are always ignored (this operation only -+ * affects one frame queue: @fq). -+ * 2. the QM_INITFQ_WE_CONTEXTB option of the 'we_mask' field and the associated -+ * 'fqd' structure's 'context_b' field are sometimes overwritten; -+ * - if @fq was not created with QMAN_FQ_FLAG_TO_DCPORTAL, then context_b is -+ * initialised to a value used by the driver for demux. -+ * - if context_b is initialised for demux, so is context_a in case stashing -+ * is requested (see item 4). -+ * (So caller control of context_b is only possible for TO_DCPORTAL frame queue -+ * objects.) -+ * 3. if @flags contains QMAN_INITFQ_FLAG_LOCAL, the 'fqd' structure's -+ * 'dest::channel' field will be overwritten to match the portal used to issue -+ * the command. If the WE_DESTWQ write-enable bit had already been set by the -+ * caller, the channel workqueue will be left as-is, otherwise the write-enable -+ * bit is set and the workqueue is set to a default of 4. If the "LOCAL" flag -+ * isn't set, the destination channel/workqueue fields and the write-enable bit -+ * are left as-is. -+ * 4. if the driver overwrites context_a/b for demux, then if -+ * QM_INITFQ_WE_CONTEXTA is set, the driver will only overwrite -+ * context_a.address fields and will leave the stashing fields provided by the -+ * user alone, otherwise it will zero out the context_a.stashing fields. -+ */ -+int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts); -+ -+/** -+ * qman_schedule_fq - Schedules a FQ -+ * @fq: the frame queue object to schedule, must be 'parked' -+ * -+ * Schedules the frame queue, which must be Parked, which takes it to -+ * Tentatively-Scheduled or Truly-Scheduled depending on its fill-level. -+ */ -+int qman_schedule_fq(struct qman_fq *fq); -+ -+/** -+ * qman_retire_fq - Retires a FQ -+ * @fq: the frame queue object to retire -+ * @flags: FQ flags (as per qman_fq_state) if retirement completes immediately -+ * -+ * Retires the frame queue. This returns zero if it succeeds immediately, +1 if -+ * the retirement was started asynchronously, otherwise it returns negative for -+ * failure. When this function returns zero, @flags is set to indicate whether -+ * the retired FQ is empty and/or whether it has any ORL fragments (to show up -+ * as ERNs). Otherwise the corresponding flags will be known when a subsequent -+ * FQRN message shows up on the portal's message ring. -+ * -+ * NB, if the retirement is asynchronous (the FQ was in the Truly Scheduled or -+ * Active state), the completion will be via the message ring as a FQRN - but -+ * the corresponding callback may occur before this function returns!! Ie. the -+ * caller should be prepared to accept the callback as the function is called, -+ * not only once it has returned. -+ */ -+int qman_retire_fq(struct qman_fq *fq, u32 *flags); -+ -+/** -+ * qman_oos_fq - Puts a FQ "out of service" -+ * @fq: the frame queue object to be put out-of-service, must be 'retired' -+ * -+ * The frame queue must be retired and empty, and if any order restoration list -+ * was released as ERNs at the time of retirement, they must all be consumed. -+ */ -+int qman_oos_fq(struct qman_fq *fq); -+ -+/** -+ * qman_fq_flow_control - Set the XON/XOFF state of a FQ -+ * @fq: the frame queue object to be set to XON/XOFF state, must not be 'oos', -+ * or 'retired' or 'parked' state -+ * @xon: boolean to set fq in XON or XOFF state -+ * -+ * The frame should be in Tentatively Scheduled state or Truly Schedule sate, -+ * otherwise the IFSI interrupt will be asserted. -+ */ -+int qman_fq_flow_control(struct qman_fq *fq, int xon); -+ -+/** -+ * qman_query_fq - Queries FQD fields (via h/w query command) -+ * @fq: the frame queue object to be queried -+ * @fqd: storage for the queried FQD fields -+ */ -+int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd); -+ -+/** -+ * qman_query_fq_np - Queries non-programmable FQD fields -+ * @fq: the frame queue object to be queried -+ * @np: storage for the queried FQD fields -+ */ -+int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np); -+ -+/** -+ * qman_query_wq - Queries work queue lengths -+ * @query_dedicated: If non-zero, query length of WQs in the channel dedicated -+ * to this software portal. Otherwise, query length of WQs in a -+ * channel specified in wq. -+ * @wq: storage for the queried WQs lengths. Also specified the channel to -+ * to query if query_dedicated is zero. -+ */ -+int qman_query_wq(u8 query_dedicated, struct qm_mcr_querywq *wq); -+ -+/** -+ * qman_volatile_dequeue - Issue a volatile dequeue command -+ * @fq: the frame queue object to dequeue from -+ * @flags: a bit-mask of QMAN_VOLATILE_FLAG_*** options -+ * @vdqcr: bit mask of QM_VDQCR_*** options, as per qm_dqrr_vdqcr_set() -+ * -+ * Attempts to lock access to the portal's VDQCR volatile dequeue functionality. -+ * The function will block and sleep if QMAN_VOLATILE_FLAG_WAIT is specified and -+ * the VDQCR is already in use, otherwise returns non-zero for failure. If -+ * QMAN_VOLATILE_FLAG_FINISH is specified, the function will only return once -+ * the VDQCR command has finished executing (ie. once the callback for the last -+ * DQRR entry resulting from the VDQCR command has been called). If not using -+ * the FINISH flag, completion can be determined either by detecting the -+ * presence of the QM_DQRR_STAT_UNSCHEDULED and QM_DQRR_STAT_DQCR_EXPIRED bits -+ * in the "stat" field of the "struct qm_dqrr_entry" passed to the FQ's dequeue -+ * callback, or by waiting for the QMAN_FQ_STATE_VDQCR bit to disappear from the -+ * "flags" retrieved from qman_fq_state(). -+ */ -+int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr); -+ -+/** -+ * qman_enqueue - Enqueue a frame to a frame queue -+ * @fq: the frame queue object to enqueue to -+ * @fd: a descriptor of the frame to be enqueued -+ * @flags: bit-mask of QMAN_ENQUEUE_FLAG_*** options -+ * -+ * Fills an entry in the EQCR of portal @qm to enqueue the frame described by -+ * @fd. The descriptor details are copied from @fd to the EQCR entry, the 'pid' -+ * field is ignored. The return value is non-zero on error, such as ring full -+ * (and FLAG_WAIT not specified), congestion avoidance (FLAG_WATCH_CGR -+ * specified), etc. If the ring is full and FLAG_WAIT is specified, this -+ * function will block. If FLAG_INTERRUPT is set, the EQCI bit of the portal -+ * interrupt will assert when Qman consumes the EQCR entry (subject to "status -+ * disable", "enable", and "inhibit" registers). If FLAG_DCA is set, Qman will -+ * perform an implied "discrete consumption acknowledgement" on the dequeue -+ * ring's (DQRR) entry, at the ring index specified by the FLAG_DCA_IDX(x) -+ * macro. (As an alternative to issuing explicit DCA actions on DQRR entries, -+ * this implicit DCA can delay the release of a "held active" frame queue -+ * corresponding to a DQRR entry until Qman consumes the EQCR entry - providing -+ * order-preservation semantics in packet-forwarding scenarios.) If FLAG_DCA is -+ * set, then FLAG_DCA_PARK can also be set to imply that the DQRR consumption -+ * acknowledgement should "park request" the "held active" frame queue. Ie. -+ * when the portal eventually releases that frame queue, it will be left in the -+ * Parked state rather than Tentatively Scheduled or Truly Scheduled. If the -+ * portal is watching congestion groups, the QMAN_ENQUEUE_FLAG_WATCH_CGR flag -+ * is requested, and the FQ is a member of a congestion group, then this -+ * function returns -EAGAIN if the congestion group is currently congested. -+ * Note, this does not eliminate ERNs, as the async interface means we can be -+ * sending enqueue commands to an un-congested FQ that becomes congested before -+ * the enqueue commands are processed, but it does minimise needless thrashing -+ * of an already busy hardware resource by throttling many of the to-be-dropped -+ * enqueues "at the source". -+ */ -+int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd, u32 flags); -+ -+typedef int (*qman_cb_precommit) (void *arg); -+/** -+ * qman_enqueue_precommit - Enqueue a frame to a frame queue and call cb -+ * @fq: the frame queue object to enqueue to -+ * @fd: a descriptor of the frame to be enqueued -+ * @flags: bit-mask of QMAN_ENQUEUE_FLAG_*** options -+ * @cb: user supplied callback function to invoke before writing commit verb. -+ * @cb_arg: callback function argument -+ * -+ * This is similar to qman_enqueue except that it will invoke a user supplied -+ * callback function just before writng the commit verb. This is useful -+ * when the user want to do something *just before* enqueuing the request and -+ * the enqueue can't fail. -+ */ -+int qman_enqueue_precommit(struct qman_fq *fq, const struct qm_fd *fd, -+ u32 flags, qman_cb_precommit cb, void *cb_arg); -+ -+/** -+ * qman_enqueue_orp - Enqueue a frame to a frame queue using an ORP -+ * @fq: the frame queue object to enqueue to -+ * @fd: a descriptor of the frame to be enqueued -+ * @flags: bit-mask of QMAN_ENQUEUE_FLAG_*** options -+ * @orp: the frame queue object used as an order restoration point. -+ * @orp_seqnum: the sequence number of this frame in the order restoration path -+ * -+ * Similar to qman_enqueue(), but with the addition of an Order Restoration -+ * Point (@orp) and corresponding sequence number (@orp_seqnum) for this -+ * enqueue operation to employ order restoration. Each frame queue object acts -+ * as an Order Definition Point (ODP) by providing each frame dequeued from it -+ * with an incrementing sequence number, this value is generally ignored unless -+ * that sequence of dequeued frames will need order restoration later. Each -+ * frame queue object also encapsulates an Order Restoration Point (ORP), which -+ * is a re-assembly context for re-ordering frames relative to their sequence -+ * numbers as they are enqueued. The ORP does not have to be within the frame -+ * queue that receives the enqueued frame, in fact it is usually the frame -+ * queue from which the frames were originally dequeued. For the purposes of -+ * order restoration, multiple frames (or "fragments") can be enqueued for a -+ * single sequence number by setting the QMAN_ENQUEUE_FLAG_NLIS flag for all -+ * enqueues except the final fragment of a given sequence number. Ordering -+ * between sequence numbers is guaranteed, even if fragments of different -+ * sequence numbers are interlaced with one another. Fragments of the same -+ * sequence number will retain the order in which they are enqueued. If no -+ * enqueue is to performed, QMAN_ENQUEUE_FLAG_HOLE indicates that the given -+ * sequence number is to be "skipped" by the ORP logic (eg. if a frame has been -+ * dropped from a sequence), or QMAN_ENQUEUE_FLAG_NESN indicates that the given -+ * sequence number should become the ORP's "Next Expected Sequence Number". -+ * -+ * Side note: a frame queue object can be used purely as an ORP, without -+ * carrying any frames at all. Care should be taken not to deallocate a frame -+ * queue object that is being actively used as an ORP, as a future allocation -+ * of the frame queue object may start using the internal ORP before the -+ * previous use has finished. -+ */ -+int qman_enqueue_orp(struct qman_fq *fq, const struct qm_fd *fd, u32 flags, -+ struct qman_fq *orp, u16 orp_seqnum); -+ -+/** -+ * qman_alloc_fqid_range - Allocate a contiguous range of FQIDs -+ * @result: is set by the API to the base FQID of the allocated range -+ * @count: the number of FQIDs required -+ * @align: required alignment of the allocated range -+ * @partial: non-zero if the API can return fewer than @count FQIDs -+ * -+ * Returns the number of frame queues allocated, or a negative error code. If -+ * @partial is non zero, the allocation request may return a smaller range of -+ * FQs than requested (though alignment will be as requested). If @partial is -+ * zero, the return value will either be 'count' or negative. -+ */ -+int qman_alloc_fqid_range(u32 *result, u32 count, u32 align, int partial); -+static inline int qman_alloc_fqid(u32 *result) -+{ -+ int ret = qman_alloc_fqid_range(result, 1, 0, 0); -+ return (ret > 0) ? 0 : ret; -+} -+ -+/** -+ * qman_release_fqid_range - Release the specified range of frame queue IDs -+ * @fqid: the base FQID of the range to deallocate -+ * @count: the number of FQIDs in the range -+ * -+ * This function can also be used to seed the allocator with ranges of FQIDs -+ * that it can subsequently allocate from. -+ */ -+void qman_release_fqid_range(u32 fqid, unsigned int count); -+static inline void qman_release_fqid(u32 fqid) -+{ -+ qman_release_fqid_range(fqid, 1); -+} -+ -+void qman_seed_fqid_range(u32 fqid, unsigned int count); -+ -+ -+int qman_shutdown_fq(u32 fqid); -+ -+/** -+ * qman_reserve_fqid_range - Reserve the specified range of frame queue IDs -+ * @fqid: the base FQID of the range to deallocate -+ * @count: the number of FQIDs in the range -+ */ -+int qman_reserve_fqid_range(u32 fqid, unsigned int count); -+static inline int qman_reserve_fqid(u32 fqid) -+{ -+ return qman_reserve_fqid_range(fqid, 1); -+} -+ -+ /* Pool-channel management */ -+ /* ----------------------- */ -+/** -+ * qman_alloc_pool_range - Allocate a contiguous range of pool-channel IDs -+ * @result: is set by the API to the base pool-channel ID of the allocated range -+ * @count: the number of pool-channel IDs required -+ * @align: required alignment of the allocated range -+ * @partial: non-zero if the API can return fewer than @count -+ * -+ * Returns the number of pool-channel IDs allocated, or a negative error code. -+ * If @partial is non zero, the allocation request may return a smaller range of -+ * than requested (though alignment will be as requested). If @partial is zero, -+ * the return value will either be 'count' or negative. -+ */ -+int qman_alloc_pool_range(u32 *result, u32 count, u32 align, int partial); -+static inline int qman_alloc_pool(u32 *result) -+{ -+ int ret = qman_alloc_pool_range(result, 1, 0, 0); -+ return (ret > 0) ? 0 : ret; -+} -+ -+/** -+ * qman_release_pool_range - Release the specified range of pool-channel IDs -+ * @id: the base pool-channel ID of the range to deallocate -+ * @count: the number of pool-channel IDs in the range -+ */ -+void qman_release_pool_range(u32 id, unsigned int count); -+static inline void qman_release_pool(u32 id) -+{ -+ qman_release_pool_range(id, 1); -+} -+ -+/** -+ * qman_reserve_pool_range - Reserve the specified range of pool-channel IDs -+ * @id: the base pool-channel ID of the range to reserve -+ * @count: the number of pool-channel IDs in the range -+ */ -+int qman_reserve_pool_range(u32 id, unsigned int count); -+static inline int qman_reserve_pool(u32 id) -+{ -+ return qman_reserve_pool_range(id, 1); -+} -+ -+void qman_seed_pool_range(u32 id, unsigned int count); -+ -+ /* CGR management */ -+ /* -------------- */ -+/** -+ * qman_create_cgr - Register a congestion group object -+ * @cgr: the 'cgr' object, with fields filled in -+ * @flags: QMAN_CGR_FLAG_* values -+ * @opts: optional state of CGR settings -+ * -+ * Registers this object to receiving congestion entry/exit callbacks on the -+ * portal affine to the cpu portal on which this API is executed. If opts is -+ * NULL then only the callback (cgr->cb) function is registered. If @flags -+ * contains QMAN_CGR_FLAG_USE_INIT, then an init hw command (which will reset -+ * any unspecified parameters) will be used rather than a modify hw hardware -+ * (which only modifies the specified parameters). -+ */ -+int qman_create_cgr(struct qman_cgr *cgr, u32 flags, -+ struct qm_mcc_initcgr *opts); -+ -+/** -+ * qman_create_cgr_to_dcp - Register a congestion group object to DCP portal -+ * @cgr: the 'cgr' object, with fields filled in -+ * @flags: QMAN_CGR_FLAG_* values -+ * @dcp_portal: the DCP portal to which the cgr object is registered. -+ * @opts: optional state of CGR settings -+ * -+ */ -+int qman_create_cgr_to_dcp(struct qman_cgr *cgr, u32 flags, u16 dcp_portal, -+ struct qm_mcc_initcgr *opts); -+ -+/** -+ * qman_delete_cgr - Deregisters a congestion group object -+ * @cgr: the 'cgr' object to deregister -+ * -+ * "Unplugs" this CGR object from the portal affine to the cpu on which this API -+ * is executed. This must be excuted on the same affine portal on which it was -+ * created. -+ */ -+int qman_delete_cgr(struct qman_cgr *cgr); -+ -+/** -+ * qman_delete_cgr_safe - Deregisters a congestion group object from any CPU -+ * @cgr: the 'cgr' object to deregister -+ * -+ * This will select the proper CPU and run there qman_delete_cgr(). -+ */ -+void qman_delete_cgr_safe(struct qman_cgr *cgr); -+ -+/** -+ * qman_modify_cgr - Modify CGR fields -+ * @cgr: the 'cgr' object to modify -+ * @flags: QMAN_CGR_FLAG_* values -+ * @opts: the CGR-modification settings -+ * -+ * The @opts parameter comes from the low-level portal API, and can be NULL. -+ * Note that some fields and options within @opts may be ignored or overwritten -+ * by the driver, in particular the 'cgrid' field is ignored (this operation -+ * only affects the given CGR object). If @flags contains -+ * QMAN_CGR_FLAG_USE_INIT, then an init hw command (which will reset any -+ * unspecified parameters) will be used rather than a modify hw hardware (which -+ * only modifies the specified parameters). -+ */ -+int qman_modify_cgr(struct qman_cgr *cgr, u32 flags, -+ struct qm_mcc_initcgr *opts); -+ -+/** -+* qman_query_cgr - Queries CGR fields -+* @cgr: the 'cgr' object to query -+* @result: storage for the queried congestion group record -+*/ -+int qman_query_cgr(struct qman_cgr *cgr, struct qm_mcr_querycgr *result); -+ -+/** -+ * qman_query_congestion - Queries the state of all congestion groups -+ * @congestion: storage for the queried state of all congestion groups -+ */ -+int qman_query_congestion(struct qm_mcr_querycongestion *congestion); -+ -+/** -+ * qman_alloc_cgrid_range - Allocate a contiguous range of CGR IDs -+ * @result: is set by the API to the base CGR ID of the allocated range -+ * @count: the number of CGR IDs required -+ * @align: required alignment of the allocated range -+ * @partial: non-zero if the API can return fewer than @count -+ * -+ * Returns the number of CGR IDs allocated, or a negative error code. -+ * If @partial is non zero, the allocation request may return a smaller range of -+ * than requested (though alignment will be as requested). If @partial is zero, -+ * the return value will either be 'count' or negative. -+ */ -+int qman_alloc_cgrid_range(u32 *result, u32 count, u32 align, int partial); -+static inline int qman_alloc_cgrid(u32 *result) -+{ -+ int ret = qman_alloc_cgrid_range(result, 1, 0, 0); -+ return (ret > 0) ? 0 : ret; -+} -+ -+/** -+ * qman_release_cgrid_range - Release the specified range of CGR IDs -+ * @id: the base CGR ID of the range to deallocate -+ * @count: the number of CGR IDs in the range -+ */ -+void qman_release_cgrid_range(u32 id, unsigned int count); -+static inline void qman_release_cgrid(u32 id) -+{ -+ qman_release_cgrid_range(id, 1); -+} -+ -+/** -+ * qman_reserve_cgrid_range - Reserve the specified range of CGR ID -+ * @id: the base CGR ID of the range to reserve -+ * @count: the number of CGR IDs in the range -+ */ -+int qman_reserve_cgrid_range(u32 id, unsigned int count); -+static inline int qman_reserve_cgrid(u32 id) -+{ -+ return qman_reserve_cgrid_range(id, 1); -+} -+ -+void qman_seed_cgrid_range(u32 id, unsigned int count); -+ -+ -+ /* Helpers */ -+ /* ------- */ -+/** -+ * qman_poll_fq_for_init - Check if an FQ has been initialised from OOS -+ * @fqid: the FQID that will be initialised by other s/w -+ * -+ * In many situations, a FQID is provided for communication between s/w -+ * entities, and whilst the consumer is responsible for initialising and -+ * scheduling the FQ, the producer(s) generally create a wrapper FQ object using -+ * and only call qman_enqueue() (no FQ initialisation, scheduling, etc). Ie; -+ * qman_create_fq(..., QMAN_FQ_FLAG_NO_MODIFY, ...); -+ * However, data can not be enqueued to the FQ until it is initialised out of -+ * the OOS state - this function polls for that condition. It is particularly -+ * useful for users of IPC functions - each endpoint's Rx FQ is the other -+ * endpoint's Tx FQ, so each side can initialise and schedule their Rx FQ object -+ * and then use this API on the (NO_MODIFY) Tx FQ object in order to -+ * synchronise. The function returns zero for success, +1 if the FQ is still in -+ * the OOS state, or negative if there was an error. -+ */ -+static inline int qman_poll_fq_for_init(struct qman_fq *fq) -+{ -+ struct qm_mcr_queryfq_np np; -+ int err; -+ err = qman_query_fq_np(fq, &np); -+ if (err) -+ return err; -+ if ((np.state & QM_MCR_NP_STATE_MASK) == QM_MCR_NP_STATE_OOS) -+ return 1; -+ return 0; -+} -+ -+ /* -------------- */ -+ /* CEETM :: types */ -+ /* -------------- */ -+/** -+ * Token Rate Structure -+ * Shaping rates are based on a "credit" system and a pre-configured h/w -+ * internal timer. The following type represents a shaper "rate" parameter as a -+ * fractional number of "tokens". Here's how it works. This (fractional) number -+ * of tokens is added to the shaper's "credit" every time the h/w timer elapses -+ * (up to a limit which is set by another shaper parameter). Every time a frame -+ * is enqueued through a shaper, the shaper deducts as many tokens as there are -+ * bytes of data in the enqueued frame. A shaper will not allow itself to -+ * enqueue any frames if its token count is negative. As such; -+ * -+ * The rate at which data is enqueued is limited by the -+ * rate at which tokens are added. -+ * -+ * Therefore if the user knows the period between these h/w timer updates in -+ * seconds, they can calculate the maximum traffic rate of the shaper (in -+ * bytes-per-second) from the token rate. And vice versa, they can calculate -+ * the token rate to use in order to achieve a given traffic rate. -+ */ -+struct qm_ceetm_rate { -+ /* The token rate is; whole + (fraction/8192) */ -+ u32 whole:11; /* 0..2047 */ -+ u32 fraction:13; /* 0..8191 */ -+}; -+ -+struct qm_ceetm_weight_code { -+ /* The weight code is; 5 msbits + 3 lsbits */ -+ u8 y:5; -+ u8 x:3; -+}; -+ -+struct qm_ceetm { -+ unsigned int idx; -+ struct list_head sub_portals; -+ struct list_head lnis; -+ unsigned int sp_range[2]; -+ unsigned int lni_range[2]; -+}; -+ -+struct qm_ceetm_sp { -+ struct list_head node; -+ unsigned int idx; -+ unsigned int dcp_idx; -+ int is_claimed; -+ struct qm_ceetm_lni *lni; -+}; -+ -+/* Logical Network Interface */ -+struct qm_ceetm_lni { -+ struct list_head node; -+ unsigned int idx; -+ unsigned int dcp_idx; -+ int is_claimed; -+ struct qm_ceetm_sp *sp; -+ struct list_head channels; -+ int shaper_enable; -+ int shaper_couple; -+ int oal; -+ struct qm_ceetm_rate cr_token_rate; -+ struct qm_ceetm_rate er_token_rate; -+ u16 cr_token_bucket_limit; -+ u16 er_token_bucket_limit; -+}; -+ -+/* Class Queue Channel */ -+struct qm_ceetm_channel { -+ struct list_head node; -+ unsigned int idx; -+ unsigned int lni_idx; -+ unsigned int dcp_idx; -+ struct list_head class_queues; -+ struct list_head ccgs; -+ u8 shaper_enable; -+ u8 shaper_couple; -+ struct qm_ceetm_rate cr_token_rate; -+ struct qm_ceetm_rate er_token_rate; -+ u16 cr_token_bucket_limit; -+ u16 er_token_bucket_limit; -+}; -+ -+struct qm_ceetm_ccg; -+ -+/* This callback type is used when handling congestion entry/exit. The -+ * 'cb_ctx' value is the opaque value associated with ccg object. -+ * 'congested' is non-zero on congestion-entry, and zero on congestion-exit. -+ */ -+typedef void (*qman_cb_ccgr)(struct qm_ceetm_ccg *ccg, void *cb_ctx, -+ int congested); -+ -+/* Class Congestion Group */ -+struct qm_ceetm_ccg { -+ struct qm_ceetm_channel *parent; -+ struct list_head node; -+ struct list_head cb_node; -+ qman_cb_ccgr cb; -+ void *cb_ctx; -+ unsigned int idx; -+}; -+ -+/* Class Queue */ -+struct qm_ceetm_cq { -+ struct qm_ceetm_channel *parent; -+ struct qm_ceetm_ccg *ccg; -+ struct list_head node; -+ unsigned int idx; -+ int is_claimed; -+ struct list_head bound_lfqids; -+ struct list_head binding_node; -+}; -+ -+/* Logical Frame Queue */ -+struct qm_ceetm_lfq { -+ struct qm_ceetm_channel *parent; -+ struct list_head node; -+ unsigned int idx; -+ unsigned int dctidx; -+ u64 context_a; -+ u32 context_b; -+ qman_cb_mr ern; -+}; -+ -+/** -+ * qman_ceetm_bps2tokenrate - Given a desired rate 'bps' measured in bps -+ * (ie. bits-per-second), compute the 'token_rate' fraction that best -+ * approximates that rate. -+ * @bps: the desired shaper rate in bps. -+ * @token_rate: the output token rate computed with the given kbps. -+ * @rounding: dictates how to round if an exact conversion is not possible; if -+ * it is negative then 'token_rate' will round down to the highest value that -+ * does not exceed the desired rate, if it is positive then 'token_rate' will -+ * round up to the lowest value that is greater than or equal to the desired -+ * rate, and if it is zero then it will round to the nearest approximation, -+ * whether that be up or down. -+ * -+ * Return 0 for success, or -EINVAL if prescaler or qman clock is not available. -+ */ -+int qman_ceetm_bps2tokenrate(u64 bps, -+ struct qm_ceetm_rate *token_rate, -+ int rounding); -+ -+/** -+ * qman_ceetm_tokenrate2bps - Given a 'token_rate', compute the -+ * corresponding number of 'bps'. -+ * @token_rate: the input desired token_rate fraction. -+ * @bps: the output shaper rate in bps computed with the give token rate. -+ * @rounding: has the same semantics as the previous function. -+ * -+ * Return 0 for success, or -EINVAL if prescaler or qman clock is not available. -+ */ -+int qman_ceetm_tokenrate2bps(const struct qm_ceetm_rate *token_rate, -+ u64 *bps, -+ int rounding); -+ -+int qman_alloc_ceetm0_channel_range(u32 *result, u32 count, u32 align, -+ int partial); -+static inline int qman_alloc_ceetm0_channel(u32 *result) -+{ -+ int ret = qman_alloc_ceetm0_channel_range(result, 1, 0, 0); -+ return (ret > 0) ? 0 : ret; -+} -+void qman_release_ceetm0_channel_range(u32 channelid, u32 count); -+static inline void qman_release_ceetm0_channelid(u32 channelid) -+{ -+ qman_release_ceetm0_channel_range(channelid, 1); -+} -+ -+int qman_reserve_ceetm0_channel_range(u32 channelid, u32 count); -+static inline int qman_reserve_ceetm0_channelid(u32 channelid) -+{ -+ return qman_reserve_ceetm0_channel_range(channelid, 1); -+} -+ -+void qman_seed_ceetm0_channel_range(u32 channelid, u32 count); -+ -+ -+int qman_alloc_ceetm1_channel_range(u32 *result, u32 count, u32 align, -+ int partial); -+static inline int qman_alloc_ceetm1_channel(u32 *result) -+{ -+ int ret = qman_alloc_ceetm1_channel_range(result, 1, 0, 0); -+ return (ret > 0) ? 0 : ret; -+} -+void qman_release_ceetm1_channel_range(u32 channelid, u32 count); -+static inline void qman_release_ceetm1_channelid(u32 channelid) -+{ -+ qman_release_ceetm1_channel_range(channelid, 1); -+} -+int qman_reserve_ceetm1_channel_range(u32 channelid, u32 count); -+static inline int qman_reserve_ceetm1_channelid(u32 channelid) -+{ -+ return qman_reserve_ceetm1_channel_range(channelid, 1); -+} -+ -+void qman_seed_ceetm1_channel_range(u32 channelid, u32 count); -+ -+ -+int qman_alloc_ceetm0_lfqid_range(u32 *result, u32 count, u32 align, -+ int partial); -+static inline int qman_alloc_ceetm0_lfqid(u32 *result) -+{ -+ int ret = qman_alloc_ceetm0_lfqid_range(result, 1, 0, 0); -+ return (ret > 0) ? 0 : ret; -+} -+void qman_release_ceetm0_lfqid_range(u32 lfqid, u32 count); -+static inline void qman_release_ceetm0_lfqid(u32 lfqid) -+{ -+ qman_release_ceetm0_lfqid_range(lfqid, 1); -+} -+int qman_reserve_ceetm0_lfqid_range(u32 lfqid, u32 count); -+static inline int qman_reserve_ceetm0_lfqid(u32 lfqid) -+{ -+ return qman_reserve_ceetm0_lfqid_range(lfqid, 1); -+} -+ -+void qman_seed_ceetm0_lfqid_range(u32 lfqid, u32 count); -+ -+ -+int qman_alloc_ceetm1_lfqid_range(u32 *result, u32 count, u32 align, -+ int partial); -+static inline int qman_alloc_ceetm1_lfqid(u32 *result) -+{ -+ int ret = qman_alloc_ceetm1_lfqid_range(result, 1, 0, 0); -+ return (ret > 0) ? 0 : ret; -+} -+void qman_release_ceetm1_lfqid_range(u32 lfqid, u32 count); -+static inline void qman_release_ceetm1_lfqid(u32 lfqid) -+{ -+ qman_release_ceetm1_lfqid_range(lfqid, 1); -+} -+int qman_reserve_ceetm1_lfqid_range(u32 lfqid, u32 count); -+static inline int qman_reserve_ceetm1_lfqid(u32 lfqid) -+{ -+ return qman_reserve_ceetm1_lfqid_range(lfqid, 1); -+} -+ -+void qman_seed_ceetm1_lfqid_range(u32 lfqid, u32 count); -+ -+ -+ /* ----------------------------- */ -+ /* CEETM :: sub-portals */ -+ /* ----------------------------- */ -+ -+/** -+ * qman_ceetm_claim_sp - Claims the given sub-portal, provided it is available -+ * to us and configured for traffic-management. -+ * @sp: the returned sub-portal object, if successful. -+ * @dcp_id: specifies the desired Fman block (and thus the relevant CEETM -+ * instance), -+ * @sp_idx" is the desired sub-portal index from 0 to 15. -+ * -+ * Returns zero for success, or -ENODEV if the sub-portal is in use, or -EINVAL -+ * if the sp_idx is out of range. -+ * -+ * Note that if there are multiple driver domains (eg. a linux kernel versus -+ * user-space drivers in USDPAA, or multiple guests running under a hypervisor) -+ * then a sub-portal may be accessible by more than one instance of a qman -+ * driver and so it may be claimed multiple times. If this is the case, it is -+ * up to the system architect to prevent conflicting configuration actions -+ * coming from the different driver domains. The qman drivers do not have any -+ * behind-the-scenes coordination to prevent this from happening. -+ */ -+int qman_ceetm_sp_claim(struct qm_ceetm_sp **sp, -+ enum qm_dc_portal dcp_idx, -+ unsigned int sp_idx); -+ -+/** -+ * qman_ceetm_sp_release - Releases a previously claimed sub-portal. -+ * @sp: the sub-portal to be released. -+ * -+ * Returns 0 for success, or -EBUSY for failure if the dependencies are not -+ * released. -+ */ -+int qman_ceetm_sp_release(struct qm_ceetm_sp *sp); -+ -+ /* ----------------------------------- */ -+ /* CEETM :: logical network interfaces */ -+ /* ----------------------------------- */ -+ -+/** -+ * qman_ceetm_lni_claim - Claims an unclaimed LNI. -+ * @lni: the returned LNI object, if successful. -+ * @dcp_id: specifies the desired Fman block (and thus the relevant CEETM -+ * instance) -+ * @lni_idx: is the desired LNI index. -+ * -+ * Returns zero for success, or -EINVAL on failure, which will happen if the LNI -+ * is not available or has already been claimed (and not yet successfully -+ * released), or lni_dix is out of range. -+ * -+ * Note that there may be multiple driver domains (or instances) that need to -+ * transmit out the same LNI, so this claim is only guaranteeing exclusivity -+ * within the domain of the driver being called. See qman_ceetm_sp_claim() and -+ * qman_ceetm_sp_get_lni() for more information. -+ */ -+int qman_ceetm_lni_claim(struct qm_ceetm_lni **lni, -+ enum qm_dc_portal dcp_id, -+ unsigned int lni_idx); -+ -+/** -+ * qman_ceetm_lni_releaes - Releases a previously claimed LNI. -+ * @lni: the lni needs to be released. -+ * -+ * This will only succeed if all dependent objects have been released. -+ * Returns zero for success, or -EBUSY if the dependencies are not released. -+ */ -+int qman_ceetm_lni_release(struct qm_ceetm_lni *lni); -+ -+/** -+ * qman_ceetm_sp_set_lni -+ * qman_ceetm_sp_get_lni - Set/get the LNI that the sub-portal is currently -+ * mapped to. -+ * @sp: the given sub-portal. -+ * @lni(in "set"function): the LNI object which the sp will be mappaed to. -+ * @lni_idx(in "get" function): the LNI index which the sp is mapped to. -+ * -+ * Returns zero for success, or -EINVAL for the "set" function when this sp-lni -+ * mapping has been set, or configure mapping command returns error, and -+ * -EINVAL for "get" function when this sp-lni mapping is not set or the query -+ * mapping command returns error. -+ * -+ * This may be useful in situations where multiple driver domains have access -+ * to the same sub-portals in order to all be able to transmit out the same -+ * physical interface (perhaps they're on different IP addresses or VPNs, so -+ * Fman is splitting Rx traffic and here we need to converge Tx traffic). In -+ * that case, a control-plane is likely to use qman_ceetm_lni_claim() followed -+ * by qman_ceetm_sp_set_lni() to configure the sub-portal, and other domains -+ * are likely to use qman_ceetm_sp_get_lni() followed by qman_ceetm_lni_claim() -+ * in order to determine the LNI that the control-plane had assigned. This is -+ * why the "get" returns an index, whereas the "set" takes an (already claimed) -+ * LNI object. -+ */ -+int qman_ceetm_sp_set_lni(struct qm_ceetm_sp *sp, -+ struct qm_ceetm_lni *lni); -+int qman_ceetm_sp_get_lni(struct qm_ceetm_sp *sp, -+ unsigned int *lni_idx); -+ -+/** -+ * qman_ceetm_lni_enable_shaper -+ * qman_ceetm_lni_disable_shaper - Enables/disables shaping on the LNI. -+ * @lni: the given LNI. -+ * @coupled: indicates whether CR and ER are coupled. -+ * @oal: the overhead accounting length which is added to the actual length of -+ * each frame when performing shaper calculations. -+ * -+ * When the number of (unused) committed-rate tokens reach the committed-rate -+ * token limit, 'coupled' indicates whether surplus tokens should be added to -+ * the excess-rate token count (up to the excess-rate token limit). -+ * When LNI is claimed, the shaper is disabled by default. The enable function -+ * will turn on this shaper for this lni. -+ * Whenever a claimed LNI is first enabled for shaping, its committed and -+ * excess token rates and limits are zero, so will need to be changed to do -+ * anything useful. The shaper can subsequently be enabled/disabled without -+ * resetting the shaping parameters, but the shaping parameters will be reset -+ * when the LNI is released. -+ * -+ * Returns zero for success, or errno for "enable" function in the cases as: -+ * a) -EINVAL if the shaper is already enabled, -+ * b) -EIO if the configure shaper command returns error. -+ * For "disable" function, returns: -+ * a) -EINVAL if the shaper is has already disabled. -+ * b) -EIO if calling configure shaper command returns error. -+ */ -+int qman_ceetm_lni_enable_shaper(struct qm_ceetm_lni *lni, int coupled, -+ int oal); -+int qman_ceetm_lni_disable_shaper(struct qm_ceetm_lni *lni); -+ -+/** -+ * qman_ceetm_lni_is_shaper_enabled - Check LNI shaper status -+ * @lni: the give LNI -+ */ -+int qman_ceetm_lni_is_shaper_enabled(struct qm_ceetm_lni *lni); -+ -+/** -+ * qman_ceetm_lni_set_commit_rate -+ * qman_ceetm_lni_get_commit_rate -+ * qman_ceetm_lni_set_excess_rate -+ * qman_ceetm_lni_get_excess_rate - Set/get the shaper CR/ER token rate and -+ * token limit for the given LNI. -+ * @lni: the given LNI. -+ * @token_rate: the desired token rate for "set" fuction, or the token rate of -+ * the LNI queried by "get" function. -+ * @token_limit: the desired token bucket limit for "set" function, or the token -+ * limit of the given LNI queried by "get" function. -+ * -+ * Returns zero for success. The "set" function returns -EINVAL if the given -+ * LNI is unshapped or -EIO if the configure shaper command returns error. -+ * The "get" function returns -EINVAL if the token rate or the token limit is -+ * not set or the query command returns error. -+ */ -+int qman_ceetm_lni_set_commit_rate(struct qm_ceetm_lni *lni, -+ const struct qm_ceetm_rate *token_rate, -+ u16 token_limit); -+int qman_ceetm_lni_get_commit_rate(struct qm_ceetm_lni *lni, -+ struct qm_ceetm_rate *token_rate, -+ u16 *token_limit); -+int qman_ceetm_lni_set_excess_rate(struct qm_ceetm_lni *lni, -+ const struct qm_ceetm_rate *token_rate, -+ u16 token_limit); -+int qman_ceetm_lni_get_excess_rate(struct qm_ceetm_lni *lni, -+ struct qm_ceetm_rate *token_rate, -+ u16 *token_limit); -+/** -+ * qman_ceetm_lni_set_commit_rate_bps -+ * qman_ceetm_lni_get_commit_rate_bps -+ * qman_ceetm_lni_set_excess_rate_bps -+ * qman_ceetm_lni_get_excess_rate_bps - Set/get the shaper CR/ER rate -+ * and token limit for the given LNI. -+ * @lni: the given LNI. -+ * @bps: the desired shaping rate in bps for "set" fuction, or the shaping rate -+ * of the LNI queried by "get" function. -+ * @token_limit: the desired token bucket limit for "set" function, or the token -+ * limit of the given LNI queried by "get" function. -+ * -+ * Returns zero for success. The "set" function returns -EINVAL if the given -+ * LNI is unshapped or -EIO if the configure shaper command returns error. -+ * The "get" function returns -EINVAL if the token rate or the token limit is -+ * not set or the query command returns error. -+ */ -+int qman_ceetm_lni_set_commit_rate_bps(struct qm_ceetm_lni *lni, -+ u64 bps, -+ u16 token_limit); -+int qman_ceetm_lni_get_commit_rate_bps(struct qm_ceetm_lni *lni, -+ u64 *bps, u16 *token_limit); -+int qman_ceetm_lni_set_excess_rate_bps(struct qm_ceetm_lni *lni, -+ u64 bps, -+ u16 token_limit); -+int qman_ceetm_lni_get_excess_rate_bps(struct qm_ceetm_lni *lni, -+ u64 *bps, u16 *token_limit); -+ -+/** -+ * qman_ceetm_lni_set_tcfcc -+ * qman_ceetm_lni_get_tcfcc - Configure/query "Traffic Class Flow Control". -+ * @lni: the given LNI. -+ * @cq_level: is between 0 and 15, representing individual class queue levels -+ * (CQ0 to CQ7 for every channel) and grouped class queue levels (CQ8 to CQ15 -+ * for every channel). -+ * @traffic_class: is between 0 and 7 when associating a given class queue level -+ * to a traffic class, or -1 when disabling traffic class flow control for this -+ * class queue level. -+ * -+ * Return zero for success, or -EINVAL if the cq_level or traffic_class is out -+ * of range as indicated above, or -EIO if the configure/query tcfcc command -+ * returns error. -+ * -+ * Refer to the section of QMan CEETM traffic class flow control in the -+ * Reference Manual. -+ */ -+int qman_ceetm_lni_set_tcfcc(struct qm_ceetm_lni *lni, -+ unsigned int cq_level, -+ int traffic_class); -+int qman_ceetm_lni_get_tcfcc(struct qm_ceetm_lni *lni, -+ unsigned int cq_level, -+ int *traffic_class); -+ -+ /* ----------------------------- */ -+ /* CEETM :: class queue channels */ -+ /* ----------------------------- */ -+ -+/** -+ * qman_ceetm_channel_claim - Claims an unclaimed CQ channel that is mapped to -+ * the given LNI. -+ * @channel: the returned class queue channel object, if successful. -+ * @lni: the LNI that the channel belongs to. -+ * -+ * Channels are always initially "unshaped". -+ * -+ * Return zero for success, or -ENODEV if there is no channel available(all 32 -+ * channels are claimed) or -EINVAL if the channel mapping command returns -+ * error. -+ */ -+int qman_ceetm_channel_claim(struct qm_ceetm_channel **channel, -+ struct qm_ceetm_lni *lni); -+ -+/** -+ * qman_ceetm_channel_release - Releases a previously claimed CQ channel. -+ * @channel: the channel needs to be released. -+ * -+ * Returns zero for success, or -EBUSY if the dependencies are still in use. -+ * -+ * Note any shaping of the channel will be cleared to leave it in an unshaped -+ * state. -+ */ -+int qman_ceetm_channel_release(struct qm_ceetm_channel *channel); -+ -+/** -+ * qman_ceetm_channel_enable_shaper -+ * qman_ceetm_channel_disable_shaper - Enables/disables shaping on the channel. -+ * @channel: the given channel. -+ * @coupled: indicates whether surplus CR tokens should be added to the -+ * excess-rate token count (up to the excess-rate token limit) when the number -+ * of (unused) committed-rate tokens reach the committed_rate token limit. -+ * -+ * Whenever a claimed channel is first enabled for shaping, its committed and -+ * excess token rates and limits are zero, so will need to be changed to do -+ * anything useful. The shaper can subsequently be enabled/disabled without -+ * resetting the shaping parameters, but the shaping parameters will be reset -+ * when the channel is released. -+ * -+ * Return 0 for success, or -EINVAL for failure, in the case that the channel -+ * shaper has been enabled/disabled or the management command returns error. -+ */ -+int qman_ceetm_channel_enable_shaper(struct qm_ceetm_channel *channel, -+ int coupled); -+int qman_ceetm_channel_disable_shaper(struct qm_ceetm_channel *channel); -+ -+/** -+ * qman_ceetm_channel_is_shaper_enabled - Check channel shaper status. -+ * @channel: the give channel. -+ */ -+int qman_ceetm_channel_is_shaper_enabled(struct qm_ceetm_channel *channel); -+ -+/** -+ * qman_ceetm_channel_set_commit_rate -+ * qman_ceetm_channel_get_commit_rate -+ * qman_ceetm_channel_set_excess_rate -+ * qman_ceetm_channel_get_excess_rate - Set/get channel CR/ER shaper parameters. -+ * @channel: the given channel. -+ * @token_rate: the desired token rate for "set" function, or the queried token -+ * rate for "get" function. -+ * @token_limit: the desired token limit for "set" function, or the queried -+ * token limit for "get" function. -+ * -+ * Return zero for success. The "set" function returns -EINVAL if the channel -+ * is unshaped, or -EIO if the configure shapper command returns error. The -+ * "get" function returns -EINVAL if token rate of token limit is not set, or -+ * the query shaper command returns error. -+ */ -+int qman_ceetm_channel_set_commit_rate(struct qm_ceetm_channel *channel, -+ const struct qm_ceetm_rate *token_rate, -+ u16 token_limit); -+int qman_ceetm_channel_get_commit_rate(struct qm_ceetm_channel *channel, -+ struct qm_ceetm_rate *token_rate, -+ u16 *token_limit); -+int qman_ceetm_channel_set_excess_rate(struct qm_ceetm_channel *channel, -+ const struct qm_ceetm_rate *token_rate, -+ u16 token_limit); -+int qman_ceetm_channel_get_excess_rate(struct qm_ceetm_channel *channel, -+ struct qm_ceetm_rate *token_rate, -+ u16 *token_limit); -+/** -+ * qman_ceetm_channel_set_commit_rate_bps -+ * qman_ceetm_channel_get_commit_rate_bps -+ * qman_ceetm_channel_set_excess_rate_bps -+ * qman_ceetm_channel_get_excess_rate_bps - Set/get channel CR/ER shaper -+ * parameters. -+ * @channel: the given channel. -+ * @token_rate: the desired shaper rate in bps for "set" function, or the -+ * shaper rate in bps for "get" function. -+ * @token_limit: the desired token limit for "set" function, or the queried -+ * token limit for "get" function. -+ * -+ * Return zero for success. The "set" function returns -EINVAL if the channel -+ * is unshaped, or -EIO if the configure shapper command returns error. The -+ * "get" function returns -EINVAL if token rate of token limit is not set, or -+ * the query shaper command returns error. -+ */ -+int qman_ceetm_channel_set_commit_rate_bps(struct qm_ceetm_channel *channel, -+ u64 bps, u16 token_limit); -+int qman_ceetm_channel_get_commit_rate_bps(struct qm_ceetm_channel *channel, -+ u64 *bps, u16 *token_limit); -+int qman_ceetm_channel_set_excess_rate_bps(struct qm_ceetm_channel *channel, -+ u64 bps, u16 token_limit); -+int qman_ceetm_channel_get_excess_rate_bps(struct qm_ceetm_channel *channel, -+ u64 *bps, u16 *token_limit); -+ -+/** -+ * qman_ceetm_channel_set_weight -+ * qman_ceetm_channel_get_weight - Set/get the weight for unshaped channel -+ * @channel: the given channel. -+ * @token_limit: the desired token limit as the weight of the unshaped channel -+ * for "set" function, or the queried token limit for "get" function. -+ * -+ * The algorithm of unshaped fair queuing (uFQ) is used for unshaped channel. -+ * It allows the unshaped channels to be included in the CR time eligible list, -+ * and thus use the configured CR token limit value as their fair queuing -+ * weight. -+ * -+ * Return zero for success, or -EINVAL if the channel is a shaped channel or -+ * the management command returns error. -+ */ -+int qman_ceetm_channel_set_weight(struct qm_ceetm_channel *channel, -+ u16 token_limit); -+int qman_ceetm_channel_get_weight(struct qm_ceetm_channel *channel, -+ u16 *token_limit); -+ -+/** -+ * qman_ceetm_channel_set_group -+ * qman_ceetm_channel_get_group - Set/get the grouping of the class scheduler. -+ * @channel: the given channel. -+ * @group_b: indicates whether there is group B in this channel. -+ * @prio_a: the priority of group A. -+ * @prio_b: the priority of group B. -+ * -+ * There are 8 individual class queues (CQ0-CQ7), and 8 grouped class queues -+ * (CQ8-CQ15). If 'group_b' is zero, then all the grouped class queues are in -+ * group A, otherwise they are split into group A (CQ8-11) and group B -+ * (CQ12-C15). The individual class queues and the group(s) are in strict -+ * priority order relative to each other. Within the group(s), the scheduling -+ * is not strict priority order, but the result of scheduling within a group -+ * is in strict priority order relative to the other class queues in the -+ * channel. 'prio_a' and 'prio_b' control the priority order of the groups -+ * relative to the individual class queues, and take values from 0-7. Eg. if -+ * 'group_b' is non-zero, 'prio_a' is 2 and 'prio_b' is 6, then the strict -+ * priority order would be; -+ * CQ0, CQ1, CQ2, GROUPA, CQ3, CQ4, CQ5, CQ6, GROUPB, CQ7 -+ * -+ * Return 0 for success. For "set" function, returns -EINVAL if prio_a or -+ * prio_b are out of the range 0 - 7 (priority of group A or group B can not -+ * be 0, CQ0 is always the highest class queue in this channel.), or -EIO if -+ * the configure scheduler command returns error. For "get" function, return -+ * -EINVAL if the query scheduler command returns error. -+ */ -+int qman_ceetm_channel_set_group(struct qm_ceetm_channel *channel, -+ int group_b, -+ unsigned int prio_a, -+ unsigned int prio_b); -+int qman_ceetm_channel_get_group(struct qm_ceetm_channel *channel, -+ int *group_b, -+ unsigned int *prio_a, -+ unsigned int *prio_b); -+ -+/** -+ * qman_ceetm_channel_set_group_cr_eligibility -+ * qman_ceetm_channel_set_group_er_eligibility - Set channel group eligibility -+ * @channel: the given channel object -+ * @group_b: indicates whether there is group B in this channel. -+ * @cre: the commit rate eligibility, 1 for enable, 0 for disable. -+ * -+ * Return zero for success, or -EINVAL if eligibility setting fails. -+*/ -+int qman_ceetm_channel_set_group_cr_eligibility(struct qm_ceetm_channel -+ *channel, int group_b, int cre); -+int qman_ceetm_channel_set_group_er_eligibility(struct qm_ceetm_channel -+ *channel, int group_b, int ere); -+ -+/** -+ * qman_ceetm_channel_set_cq_cr_eligibility -+ * qman_ceetm_channel_set_cq_er_eligibility - Set channel cq eligibility -+ * @channel: the given channel object -+ * @idx: is from 0 to 7 (representing CQ0 to CQ7). -+ * @cre: the commit rate eligibility, 1 for enable, 0 for disable. -+ * -+ * Return zero for success, or -EINVAL if eligibility setting fails. -+*/ -+int qman_ceetm_channel_set_cq_cr_eligibility(struct qm_ceetm_channel *channel, -+ unsigned int idx, int cre); -+int qman_ceetm_channel_set_cq_er_eligibility(struct qm_ceetm_channel *channel, -+ unsigned int idx, int ere); -+ -+ /* --------------------- */ -+ /* CEETM :: class queues */ -+ /* --------------------- */ -+ -+/** -+ * qman_ceetm_cq_claim - Claims an individual class queue. -+ * @cq: the returned class queue object, if successful. -+ * @channel: the class queue channel. -+ * @idx: is from 0 to 7 (representing CQ0 to CQ7). -+ * @ccg: represents the class congestion group that this class queue should be -+ * subscribed to, or NULL if no congestion group membership is desired. -+ * -+ * Returns zero for success, or -EINVAL if @idx is out of range 0 - 7 or -+ * if this class queue has been claimed, or configure class queue command -+ * returns error, or returns -ENOMEM if allocating CQ memory fails. -+ */ -+int qman_ceetm_cq_claim(struct qm_ceetm_cq **cq, -+ struct qm_ceetm_channel *channel, -+ unsigned int idx, -+ struct qm_ceetm_ccg *ccg); -+ -+/** -+ * qman_ceetm_cq_claim_A - Claims a class queue group A. -+ * @cq: the returned class queue object, if successful. -+ * @channel: the class queue channel. -+ * @idx: is from 8 to 15 if only group A exits, otherwise, it is from 8 to 11. -+ * @ccg: represents the class congestion group that this class queue should be -+ * subscribed to, or NULL if no congestion group membership is desired. -+ * -+ * Return zero for success, or -EINVAL if @idx is out the range or if -+ * this class queue has been claimed or configure class queue command returns -+ * error, or returns -ENOMEM if allocating CQ memory fails. -+ */ -+int qman_ceetm_cq_claim_A(struct qm_ceetm_cq **cq, -+ struct qm_ceetm_channel *channel, -+ unsigned int idx, -+ struct qm_ceetm_ccg *ccg); -+ -+/** -+ * qman_ceetm_cq_claim_B - Claims a class queue group B. -+ * @cq: the returned class queue object, if successful. -+ * @channel: the class queue channel. -+ * @idx: is from 0 to 3 (CQ12 to CQ15). -+ * @ccg: represents the class congestion group that this class queue should be -+ * subscribed to, or NULL if no congestion group membership is desired. -+ * -+ * Return zero for success, or -EINVAL if @idx is out the range or if -+ * this class queue has been claimed or configure class queue command returns -+ * error, or returns -ENOMEM if allocating CQ memory fails. -+ */ -+int qman_ceetm_cq_claim_B(struct qm_ceetm_cq **cq, -+ struct qm_ceetm_channel *channel, -+ unsigned int idx, -+ struct qm_ceetm_ccg *ccg); -+ -+/** -+ * qman_ceetm_cq_release - Releases a previously claimed class queue. -+ * @cq: The class queue to be released. -+ * -+ * Return zero for success, or -EBUSY if the dependent objects (eg. logical -+ * FQIDs) have not been released. -+ */ -+int qman_ceetm_cq_release(struct qm_ceetm_cq *cq); -+ -+/** -+ * qman_ceetm_set_queue_weight -+ * qman_ceetm_get_queue_weight - Configure/query the weight of a grouped class -+ * queue. -+ * @cq: the given class queue. -+ * @weight_code: the desired weight code to set for the given class queue for -+ * "set" function or the queired weight code for "get" function. -+ * -+ * Grouped class queues have a default weight code of zero, which corresponds to -+ * a scheduler weighting of 1. This function can be used to modify a grouped -+ * class queue to another weight, (Use the helpers qman_ceetm_wbfs2ratio() -+ * and qman_ceetm_ratio2wbfs() to convert between these 'weight_code' values -+ * and the corresponding sharing weight.) -+ * -+ * Returns zero for success, or -EIO if the configure weight command returns -+ * error for "set" function, or -EINVAL if the query command returns -+ * error for "get" function. -+ * See section "CEETM Weighted Scheduling among Grouped Classes" in Reference -+ * Manual for weight and weight code. -+ */ -+int qman_ceetm_set_queue_weight(struct qm_ceetm_cq *cq, -+ struct qm_ceetm_weight_code *weight_code); -+int qman_ceetm_get_queue_weight(struct qm_ceetm_cq *cq, -+ struct qm_ceetm_weight_code *weight_code); -+ -+/** -+ * qman_ceetm_set_queue_weight_in_ratio -+ * qman_ceetm_get_queue_weight_in_ratio - Configure/query the weight of a -+ * grouped class queue. -+ * @cq: the given class queue. -+ * @ratio: the weight in ratio. It should be the real ratio number multiplied -+ * by 100 to get rid of fraction. -+ * -+ * Returns zero for success, or -EIO if the configure weight command returns -+ * error for "set" function, or -EINVAL if the query command returns -+ * error for "get" function. -+ */ -+int qman_ceetm_set_queue_weight_in_ratio(struct qm_ceetm_cq *cq, u32 ratio); -+int qman_ceetm_get_queue_weight_in_ratio(struct qm_ceetm_cq *cq, u32 *ratio); -+ -+/* Weights are encoded using a pseudo-exponential scheme. The weight codes 0, -+ * 32, 64, [...] correspond to weights of 1, 2, 4, [...]. The weights -+ * corresponding to intermediate weight codes are calculated using linear -+ * interpolation on the inverted values. Or put another way, the inverse weights -+ * for each 32nd weight code are 1, 1/2, 1/4, [...], and so the intervals -+ * between these are divided linearly into 32 intermediate values, the inverses -+ * of which form the remaining weight codes. -+ * -+ * The Weighted Bandwidth Fair Scheduling (WBFS) algorithm provides a form of -+ * scheduling within a group of class queues (group A or B). Weights are used to -+ * normalise the class queues to an underlying BFS algorithm where all class -+ * queues are assumed to require "equal bandwidth". So the weights referred to -+ * by the weight codes act as divisors on the size of frames being enqueued. Ie. -+ * one class queue in a group is assigned a weight of 2 whilst the other class -+ * queues in the group keep the default weight of 1, then the WBFS scheduler -+ * will effectively treat all frames enqueued on the weight-2 class queue as -+ * having half the number of bytes they really have. Ie. if all other things are -+ * equal, that class queue would get twice as much bytes-per-second bandwidth as -+ * the others. So weights should be chosen to provide bandwidth ratios between -+ * members of the same class queue group. These weights have no bearing on -+ * behaviour outside that group's WBFS mechanism though. -+ */ -+ -+/** -+ * qman_ceetm_wbfs2ratio - Given a weight code ('wbfs'), an accurate fractional -+ * representation of the corresponding weight is given (in order to not lose -+ * any precision). -+ * @weight_code: The given weight code in WBFS. -+ * @numerator: the numerator part of the weight computed by the weight code. -+ * @denominator: the denominator part of the weight computed by the weight code -+ * -+ * Returns zero for success or -EINVAL if the given weight code is illegal. -+ */ -+int qman_ceetm_wbfs2ratio(struct qm_ceetm_weight_code *weight_code, -+ u32 *numerator, -+ u32 *denominator); -+/** -+ * qman_ceetm_ratio2wbfs - Given a weight, find the nearest possible weight code -+ * If the user needs to know how close this is, convert the resulting weight -+ * code back to a weight and compare. -+ * @numerator: numerator part of the given weight. -+ * @denominator: denominator part of the given weight. -+ * @weight_code: the weight code computed from the given weight. -+ * -+ * Returns zero for success, or -ERANGE if "numerator/denominator" is outside -+ * the range of weights. -+ */ -+int qman_ceetm_ratio2wbfs(u32 numerator, -+ u32 denominator, -+ struct qm_ceetm_weight_code *weight_code, -+ int rounding); -+ -+#define QMAN_CEETM_FLAG_CLEAR_STATISTICS_COUNTER 0x1 -+/** -+ * qman_ceetm_cq_get_dequeue_statistics - Get the statistics provided by CEETM -+ * CQ counters. -+ * @cq: the given CQ object. -+ * @flags: indicates whether the statistics counter will be cleared after query. -+ * @frame_count: The number of the frames that have been counted since the -+ * counter was cleared last time. -+ * @byte_count: the number of bytes in all frames that have been counted. -+ * -+ * Return zero for success or -EINVAL if query statistics command returns error. -+ * -+ */ -+int qman_ceetm_cq_get_dequeue_statistics(struct qm_ceetm_cq *cq, u32 flags, -+ u64 *frame_count, u64 *byte_count); -+ -+/** -+ * qman_ceetm_drain_cq - drain the CQ till it is empty. -+ * @cq: the give CQ object. -+ * Return 0 for success or -EINVAL for unsuccessful command to empty CQ. -+ */ -+int qman_ceetm_drain_cq(struct qm_ceetm_cq *cq); -+ -+ /* ---------------------- */ -+ /* CEETM :: logical FQIDs */ -+ /* ---------------------- */ -+/** -+ * qman_ceetm_lfq_claim - Claims an unused logical FQID, associates it with -+ * the given class queue. -+ * @lfq: the returned lfq object, if successful. -+ * @cq: the class queue which needs to claim a LFQID. -+ * -+ * Return zero for success, or -ENODEV if no LFQID is available or -ENOMEM if -+ * allocating memory for lfq fails, or -EINVAL if configuring LFQMT fails. -+ */ -+int qman_ceetm_lfq_claim(struct qm_ceetm_lfq **lfq, -+ struct qm_ceetm_cq *cq); -+ -+/** -+ * qman_ceetm_lfq_release - Releases a previously claimed logical FQID. -+ * @lfq: the lfq to be released. -+ * -+ * Return zero for success. -+ */ -+int qman_ceetm_lfq_release(struct qm_ceetm_lfq *lfq); -+ -+/** -+ * qman_ceetm_lfq_set_context -+ * qman_ceetm_lfq_get_context - Set/get the context_a/context_b pair to the -+ * "dequeue context table" associated with the logical FQID. -+ * @lfq: the given logical FQ object. -+ * @context_a: contextA of the dequeue context. -+ * @context_b: contextB of the dequeue context. -+ * -+ * Returns zero for success, or -EINVAL if there is error to set/get the -+ * context pair. -+ */ -+int qman_ceetm_lfq_set_context(struct qm_ceetm_lfq *lfq, -+ u64 context_a, -+ u32 context_b); -+int qman_ceetm_lfq_get_context(struct qm_ceetm_lfq *lfq, -+ u64 *context_a, -+ u32 *context_b); -+ -+/** -+ * qman_ceetm_create_fq - Initialise a FQ object for the LFQ. -+ * @lfq: the given logic fq. -+ * @fq: the fq object created for the given logic fq. -+ * -+ * The FQ object can be used in qman_enqueue() and qman_enqueue_orp() APIs to -+ * target a logical FQID (and the class queue it is associated with). -+ * Note that this FQ object can only be used for enqueues, and -+ * in the case of qman_enqueue_orp() it can not be used as the 'orp' parameter, -+ * only as 'fq'. This FQ object can not (and shouldn't) be destroyed, it is only -+ * valid as long as the underlying 'lfq' remains claimed. It is the user's -+ * responsibility to ensure that the underlying 'lfq' is not released until any -+ * enqueues to this FQ object have completed. The only field the user needs to -+ * fill in is fq->cb.ern, as that enqueue rejection handler is the callback that -+ * could conceivably be called on this FQ object. This API can be called -+ * multiple times to create multiple FQ objects referring to the same logical -+ * FQID, and any enqueue rejections will respect the callback of the object that -+ * issued the enqueue (and will identify the object via the parameter passed to -+ * the callback too). There is no 'flags' parameter to this API as there is for -+ * qman_create_fq() - the created FQ object behaves as though qman_create_fq() -+ * had been called with the single flag QMAN_FQ_FLAG_NO_MODIFY. -+ * -+ * Returns 0 for success. -+ */ -+int qman_ceetm_create_fq(struct qm_ceetm_lfq *lfq, struct qman_fq *fq); -+ -+ /* -------------------------------- */ -+ /* CEETM :: class congestion groups */ -+ /* -------------------------------- */ -+ -+/** -+ * qman_ceetm_ccg_claim - Claims an unused CCG. -+ * @ccg: the returned CCG object, if successful. -+ * @channel: the given class queue channel -+ * @cscn: the callback function of this CCG. -+ * @cb_ctx: the corresponding context to be used used if state change -+ * notifications are later enabled for this CCG. -+ * -+ * The congestion group is local to the given class queue channel, so only -+ * class queues within the channel can be associated with that congestion group. -+ * The association of class queues to congestion groups occurs when the class -+ * queues are claimed, see qman_ceetm_cq_claim() and related functions. -+ * Congestion groups are in a "zero" state when initially claimed, and they are -+ * returned to that state when released. -+ * -+ * Return zero for success, or -EINVAL if no CCG in the channel is available. -+ */ -+int qman_ceetm_ccg_claim(struct qm_ceetm_ccg **ccg, -+ struct qm_ceetm_channel *channel, -+ unsigned int idx, -+ void (*cscn)(struct qm_ceetm_ccg *, -+ void *cb_ctx, -+ int congested), -+ void *cb_ctx); -+ -+/** -+ * qman_ceetm_ccg_release - Releases a previously claimed CCG. -+ * @ccg: the given ccg. -+ * -+ * Returns zero for success, or -EBUSY if the given ccg's dependent objects -+ * (class queues that are associated with the CCG) have not been released. -+ */ -+int qman_ceetm_ccg_release(struct qm_ceetm_ccg *ccg); -+ -+/* This struct is used to specify attributes for a CCG. The 'we_mask' field -+ * controls which CCG attributes are to be updated, and the remainder specify -+ * the values for those attributes. A CCG counts either frames or the bytes -+ * within those frames, but not both ('mode'). A CCG can optionally cause -+ * enqueues to be rejected, due to tail-drop or WRED, or both (they are -+ * independent options, 'td_en' and 'wr_en_g,wr_en_y,wr_en_r'). Tail-drop can be -+ * level-triggered due to a single threshold ('td_thres') or edge-triggered due -+ * to a "congestion state", but not both ('td_mode'). Congestion state has -+ * distinct entry and exit thresholds ('cs_thres_in' and 'cs_thres_out'), and -+ * notifications can be sent to software the CCG goes in to and out of this -+ * congested state ('cscn_en'). */ -+struct qm_ceetm_ccg_params { -+ /* Boolean fields together in a single bitfield struct */ -+ struct { -+ /* Whether to count bytes or frames. 1==frames */ -+ u8 mode:1; -+ /* En/disable tail-drop. 1==enable */ -+ u8 td_en:1; -+ /* Tail-drop on congestion-state or threshold. 1=threshold */ -+ u8 td_mode:1; -+ /* Generate congestion state change notifications. 1==enable */ -+ u8 cscn_en:1; -+ /* Enable WRED rejections (per colour). 1==enable */ -+ u8 wr_en_g:1; -+ u8 wr_en_y:1; -+ u8 wr_en_r:1; -+ } __packed; -+ /* Tail-drop threshold. See qm_cgr_thres_[gs]et64(). */ -+ struct qm_cgr_cs_thres td_thres; -+ /* Congestion state thresholds, for entry and exit. */ -+ struct qm_cgr_cs_thres cs_thres_in; -+ struct qm_cgr_cs_thres cs_thres_out; -+ /* Overhead accounting length. Per-packet "tax", from -128 to +127 */ -+ signed char oal; -+ /* Congestion state change notification for DCP portal, virtual CCGID*/ -+ /* WRED parameters. */ -+ struct qm_cgr_wr_parm wr_parm_g; -+ struct qm_cgr_wr_parm wr_parm_y; -+ struct qm_cgr_wr_parm wr_parm_r; -+}; -+/* Bits used in 'we_mask' to qman_ceetm_ccg_set(), controls which attributes of -+ * the CCGR are to be updated. */ -+#define QM_CCGR_WE_MODE 0x0001 /* mode (bytes/frames) */ -+#define QM_CCGR_WE_CS_THRES_IN 0x0002 /* congestion state entry threshold */ -+#define QM_CCGR_WE_TD_EN 0x0004 /* congestion state tail-drop enable */ -+#define QM_CCGR_WE_CSCN_TUPD 0x0008 /* CSCN target update */ -+#define QM_CCGR_WE_CSCN_EN 0x0010 /* congestion notification enable */ -+#define QM_CCGR_WE_WR_EN_R 0x0020 /* WRED enable - red */ -+#define QM_CCGR_WE_WR_EN_Y 0x0040 /* WRED enable - yellow */ -+#define QM_CCGR_WE_WR_EN_G 0x0080 /* WRED enable - green */ -+#define QM_CCGR_WE_WR_PARM_R 0x0100 /* WRED parameters - red */ -+#define QM_CCGR_WE_WR_PARM_Y 0x0200 /* WRED parameters - yellow */ -+#define QM_CCGR_WE_WR_PARM_G 0x0400 /* WRED parameters - green */ -+#define QM_CCGR_WE_OAL 0x0800 /* overhead accounting length */ -+#define QM_CCGR_WE_CS_THRES_OUT 0x1000 /* congestion state exit threshold */ -+#define QM_CCGR_WE_TD_THRES 0x2000 /* tail-drop threshold */ -+#define QM_CCGR_WE_TD_MODE 0x4000 /* tail-drop mode (state/threshold) */ -+#define QM_CCGR_WE_CDV 0x8000 /* cdv */ -+ -+/** -+ * qman_ceetm_ccg_set -+ * qman_ceetm_ccg_get - Configure/query a subset of CCG attributes. -+ * @ccg: the given CCG object. -+ * @we_mask: the write enable mask. -+ * @params: the parameters setting for this ccg -+ * -+ * Return 0 for success, or -EIO if configure ccg command returns error for -+ * "set" function, or -EINVAL if query ccg command returns error for "get" -+ * function. -+ */ -+int qman_ceetm_ccg_set(struct qm_ceetm_ccg *ccg, -+ u16 we_mask, -+ const struct qm_ceetm_ccg_params *params); -+int qman_ceetm_ccg_get(struct qm_ceetm_ccg *ccg, -+ struct qm_ceetm_ccg_params *params); -+ -+/** qman_ceetm_cscn_swp_set - Add or remove a software portal from the target -+ * mask. -+ * qman_ceetm_cscn_swp_get - Query whether a given software portal index is -+ * in the cscn target mask. -+ * @ccg: the give CCG object. -+ * @swp_idx: the index of the software portal. -+ * @cscn_enabled: 1: Set the swp to be cscn target. 0: remove the swp from -+ * the target mask. -+ * @we_mask: the write enable mask. -+ * @params: the parameters setting for this ccg -+ * -+ * Return 0 for success, or -EINVAL if command in set/get function fails. -+ */ -+int qman_ceetm_cscn_swp_set(struct qm_ceetm_ccg *ccg, -+ u16 swp_idx, -+ unsigned int cscn_enabled, -+ u16 we_mask, -+ const struct qm_ceetm_ccg_params *params); -+int qman_ceetm_cscn_swp_get(struct qm_ceetm_ccg *ccg, -+ u16 swp_idx, -+ unsigned int *cscn_enabled); -+ -+/** qman_ceetm_cscn_dcp_set - Add or remove a direct connect portal from the\ -+ * target mask. -+ * qman_ceetm_cscn_swp_get - Query whether a given direct connect portal index -+ * is in the cscn target mask. -+ * @ccg: the give CCG object. -+ * @dcp_idx: the index of the direct connect portal. -+ * @vcgid: congestion state change notification for dcp portal, virtual CGID. -+ * @cscn_enabled: 1: Set the dcp to be cscn target. 0: remove the dcp from -+ * the target mask. -+ * @we_mask: the write enable mask. -+ * @params: the parameters setting for this ccg -+ * -+ * Return 0 for success, or -EINVAL if command in set/get function fails. -+ */ -+int qman_ceetm_cscn_dcp_set(struct qm_ceetm_ccg *ccg, -+ u16 dcp_idx, -+ u8 vcgid, -+ unsigned int cscn_enabled, -+ u16 we_mask, -+ const struct qm_ceetm_ccg_params *params); -+int qman_ceetm_cscn_dcp_get(struct qm_ceetm_ccg *ccg, -+ u16 dcp_idx, -+ u8 *vcgid, -+ unsigned int *cscn_enabled); -+ -+/** -+ * qman_ceetm_ccg_get_reject_statistics - Get the statistics provided by -+ * CEETM CCG counters. -+ * @ccg: the given CCG object. -+ * @flags: indicates whether the statistics counter will be cleared after query. -+ * @frame_count: The number of the frames that have been counted since the -+ * counter was cleared last time. -+ * @byte_count: the number of bytes in all frames that have been counted. -+ * -+ * Return zero for success or -EINVAL if query statistics command returns error. -+ * -+ */ -+int qman_ceetm_ccg_get_reject_statistics(struct qm_ceetm_ccg *ccg, u32 flags, -+ u64 *frame_count, u64 *byte_count); -+ -+/** -+ * qman_ceetm_query_lfqmt - Query the logical frame queue mapping table -+ * @lfqid: Logical Frame Queue ID -+ * @lfqmt_query: Results of the query command -+ * -+ * Returns zero for success or -EIO if the query command returns error. -+ * -+ */ -+int qman_ceetm_query_lfqmt(int lfqid, -+ struct qm_mcr_ceetm_lfqmt_query *lfqmt_query); -+ -+/** -+ * qman_ceetm_query_write_statistics - Query (and optionally write) statistics -+ * @cid: Target ID (CQID or CCGRID) -+ * @dcp_idx: CEETM portal ID -+ * @command_type: One of the following: -+ * 0 = Query dequeue statistics. CID carries the CQID to be queried. -+ * 1 = Query and clear dequeue statistics. CID carries the CQID to be queried -+ * 2 = Write dequeue statistics. CID carries the CQID to be written. -+ * 3 = Query reject statistics. CID carries the CCGRID to be queried. -+ * 4 = Query and clear reject statistics. CID carries the CCGRID to be queried -+ * 5 = Write reject statistics. CID carries the CCGRID to be written -+ * @frame_count: Frame count value to be written if this is a write command -+ * @byte_count: Bytes count value to be written if this is a write command -+ * -+ * Returns zero for success or -EIO if the query command returns error. -+ */ -+int qman_ceetm_query_write_statistics(u16 cid, enum qm_dc_portal dcp_idx, -+ u16 command_type, u64 frame_count, -+ u64 byte_count); -+ -+/** -+ * qman_set_wpm - Set waterfall power management -+ * -+ * @wpm_enable: boolean, 1 = enable wpm, 0 = disable wpm. -+ * -+ * Return 0 for success, return -ENODEV if QMan misc_cfg register is not -+ * accessible. -+ */ -+int qman_set_wpm(int wpm_enable); -+ -+/** -+ * qman_get_swp - Query the waterfall power management setting -+ * -+ * @wpm_enable: boolean, 1 = enable wpm, 0 = disable wpm. -+ * -+ * Return 0 for success, return -ENODEV if QMan misc_cfg register is not -+ * accessible. -+ */ -+int qman_get_wpm(int *wpm_enable); -+ -+/* The below qman_p_***() variants might be called in a migration situation -+ * (e.g. cpu hotplug). They are used to continue accessing the portal that -+ * execution was affine to prior to migration. -+ * @qman_portal specifies which portal the APIs will use. -+*/ -+const struct qman_portal_config *qman_p_get_portal_config(struct qman_portal -+ *p); -+int qman_p_irqsource_add(struct qman_portal *p, u32 bits); -+int qman_p_irqsource_remove(struct qman_portal *p, u32 bits); -+int qman_p_poll_dqrr(struct qman_portal *p, unsigned int limit); -+u32 qman_p_poll_slow(struct qman_portal *p); -+void qman_p_poll(struct qman_portal *p); -+void qman_p_stop_dequeues(struct qman_portal *p); -+void qman_p_start_dequeues(struct qman_portal *p); -+void qman_p_static_dequeue_add(struct qman_portal *p, u32 pools); -+void qman_p_static_dequeue_del(struct qman_portal *p, u32 pools); -+u32 qman_p_static_dequeue_get(struct qman_portal *p); -+void qman_p_dca(struct qman_portal *p, struct qm_dqrr_entry *dq, -+ int park_request); -+int qman_p_volatile_dequeue(struct qman_portal *p, struct qman_fq *fq, -+ u32 flags __maybe_unused, u32 vdqcr); -+int qman_p_enqueue(struct qman_portal *p, struct qman_fq *fq, -+ const struct qm_fd *fd, u32 flags); -+int qman_p_enqueue_orp(struct qman_portal *p, struct qman_fq *fq, -+ const struct qm_fd *fd, u32 flags, -+ struct qman_fq *orp, u16 orp_seqnum); -+int qman_p_enqueue_precommit(struct qman_portal *p, struct qman_fq *fq, -+ const struct qm_fd *fd, u32 flags, -+ qman_cb_precommit cb, void *cb_arg); -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* FSL_QMAN_H */ ---- /dev/null -+++ b/include/linux/fsl_usdpaa.h -@@ -0,0 +1,372 @@ -+/* Copyright 2011-2012 Freescale Semiconductor, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ -+ -+#ifndef FSL_USDPAA_H -+#define FSL_USDPAA_H -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#include -+#include -+#include /* For "enum qm_channel" */ -+#include -+ -+#ifdef CONFIG_FSL_USDPAA -+ -+/******************************/ -+/* Allocation of resource IDs */ -+/******************************/ -+ -+/* This enum is used to distinguish between the type of underlying object being -+ * manipulated. */ -+enum usdpaa_id_type { -+ usdpaa_id_fqid, -+ usdpaa_id_bpid, -+ usdpaa_id_qpool, -+ usdpaa_id_cgrid, -+ usdpaa_id_ceetm0_lfqid, -+ usdpaa_id_ceetm0_channelid, -+ usdpaa_id_ceetm1_lfqid, -+ usdpaa_id_ceetm1_channelid, -+ usdpaa_id_max /* <-- not a valid type, represents the number of types */ -+}; -+#define USDPAA_IOCTL_MAGIC 'u' -+struct usdpaa_ioctl_id_alloc { -+ uint32_t base; /* Return value, the start of the allocated range */ -+ enum usdpaa_id_type id_type; /* what kind of resource(s) to allocate */ -+ uint32_t num; /* how many IDs to allocate (and return value) */ -+ uint32_t align; /* must be a power of 2, 0 is treated like 1 */ -+ int partial; /* whether to allow less than 'num' */ -+}; -+struct usdpaa_ioctl_id_release { -+ /* Input; */ -+ enum usdpaa_id_type id_type; -+ uint32_t base; -+ uint32_t num; -+}; -+struct usdpaa_ioctl_id_reserve { -+ enum usdpaa_id_type id_type; -+ uint32_t base; -+ uint32_t num; -+}; -+ -+ -+/* ioctl() commands */ -+#define USDPAA_IOCTL_ID_ALLOC \ -+ _IOWR(USDPAA_IOCTL_MAGIC, 0x01, struct usdpaa_ioctl_id_alloc) -+#define USDPAA_IOCTL_ID_RELEASE \ -+ _IOW(USDPAA_IOCTL_MAGIC, 0x02, struct usdpaa_ioctl_id_release) -+#define USDPAA_IOCTL_ID_RESERVE \ -+ _IOW(USDPAA_IOCTL_MAGIC, 0x0A, struct usdpaa_ioctl_id_reserve) -+ -+/**********************/ -+/* Mapping DMA memory */ -+/**********************/ -+ -+/* Maximum length for a map name, including NULL-terminator */ -+#define USDPAA_DMA_NAME_MAX 16 -+/* Flags for requesting DMA maps. Maps are private+unnamed or sharable+named. -+ * For a sharable and named map, specify _SHARED (whether creating one or -+ * binding to an existing one). If _SHARED is specified and _CREATE is not, then -+ * the mapping must already exist. If _SHARED and _CREATE are specified and the -+ * mapping doesn't already exist, it will be created. If _SHARED and _CREATE are -+ * specified and the mapping already exists, the mapping will fail unless _LAZY -+ * is specified. When mapping to a pre-existing sharable map, the length must be -+ * an exact match. Lengths must be a power-of-4 multiple of page size. -+ * -+ * Note that this does not actually map the memory to user-space, that is done -+ * by a subsequent mmap() using the page offset returned from this ioctl(). The -+ * ioctl() is what gives the process permission to do this, and a page-offset -+ * with which to do so. -+ */ -+#define USDPAA_DMA_FLAG_SHARE 0x01 -+#define USDPAA_DMA_FLAG_CREATE 0x02 -+#define USDPAA_DMA_FLAG_LAZY 0x04 -+#define USDPAA_DMA_FLAG_RDONLY 0x08 -+struct usdpaa_ioctl_dma_map { -+ /* Output parameters - virtual and physical addresses */ -+ void *ptr; -+ uint64_t phys_addr; -+ /* Input parameter, the length of the region to be created (or if -+ * mapping an existing region, this must match it). Must be a power-of-4 -+ * multiple of page size. */ -+ uint64_t len; -+ /* Input parameter, the USDPAA_DMA_FLAG_* settings. */ -+ uint32_t flags; -+ /* If _FLAG_SHARE is specified, the name of the region to be created (or -+ * of the existing mapping to use). */ -+ char name[USDPAA_DMA_NAME_MAX]; -+ /* If this ioctl() creates the mapping, this is an input parameter -+ * stating whether the region supports locking. If mapping an existing -+ * region, this is a return value indicating the same thing. */ -+ int has_locking; -+ /* In the case of a successful map with _CREATE and _LAZY, this return -+ * value indicates whether we created the mapped region or whether it -+ * already existed. */ -+ int did_create; -+}; -+ -+#ifdef CONFIG_COMPAT -+struct usdpaa_ioctl_dma_map_compat { -+ /* Output parameters - virtual and physical addresses */ -+ compat_uptr_t ptr; -+ uint64_t phys_addr; -+ /* Input parameter, the length of the region to be created (or if -+ * mapping an existing region, this must match it). Must be a power-of-4 -+ * multiple of page size. */ -+ uint64_t len; -+ /* Input parameter, the USDPAA_DMA_FLAG_* settings. */ -+ uint32_t flags; -+ /* If _FLAG_SHARE is specified, the name of the region to be created (or -+ * of the existing mapping to use). */ -+ char name[USDPAA_DMA_NAME_MAX]; -+ /* If this ioctl() creates the mapping, this is an input parameter -+ * stating whether the region supports locking. If mapping an existing -+ * region, this is a return value indicating the same thing. */ -+ int has_locking; -+ /* In the case of a successful map with _CREATE and _LAZY, this return -+ * value indicates whether we created the mapped region or whether it -+ * already existed. */ -+ int did_create; -+}; -+ -+#define USDPAA_IOCTL_DMA_MAP_COMPAT \ -+ _IOWR(USDPAA_IOCTL_MAGIC, 0x03, struct usdpaa_ioctl_dma_map_compat) -+#endif -+ -+ -+#define USDPAA_IOCTL_DMA_MAP \ -+ _IOWR(USDPAA_IOCTL_MAGIC, 0x03, struct usdpaa_ioctl_dma_map) -+/* munmap() does not remove the DMA map, just the user-space mapping to it. -+ * This ioctl will do both (though you can munmap() before calling the ioctl -+ * too). */ -+#define USDPAA_IOCTL_DMA_UNMAP \ -+ _IOW(USDPAA_IOCTL_MAGIC, 0x04, unsigned char) -+/* We implement a cross-process locking scheme per DMA map. Call this ioctl() -+ * with a mmap()'d address, and the process will (interruptible) sleep if the -+ * lock is already held by another process. Process destruction will -+ * automatically clean up any held locks. */ -+#define USDPAA_IOCTL_DMA_LOCK \ -+ _IOW(USDPAA_IOCTL_MAGIC, 0x05, unsigned char) -+#define USDPAA_IOCTL_DMA_UNLOCK \ -+ _IOW(USDPAA_IOCTL_MAGIC, 0x06, unsigned char) -+ -+/***************************************/ -+/* Mapping and using QMan/BMan portals */ -+/***************************************/ -+enum usdpaa_portal_type { -+ usdpaa_portal_qman, -+ usdpaa_portal_bman, -+}; -+ -+#define QBMAN_ANY_PORTAL_IDX 0xffffffff -+ -+struct usdpaa_ioctl_portal_map { -+ /* Input parameter, is a qman or bman portal required. */ -+ -+ enum usdpaa_portal_type type; -+ /* Specifes a specific portal index to map or QBMAN_ANY_PORTAL_IDX -+ for don't care. The portal index will be populated by the -+ driver when the ioctl() successfully completes */ -+ uint32_t index; -+ -+ /* Return value if the map succeeds, this gives the mapped -+ * cache-inhibited (cinh) and cache-enabled (cena) addresses. */ -+ struct usdpaa_portal_map { -+ void *cinh; -+ void *cena; -+ } addr; -+ /* Qman-specific return values */ -+ uint16_t channel; -+ uint32_t pools; -+}; -+ -+#ifdef CONFIG_COMPAT -+struct compat_usdpaa_ioctl_portal_map { -+ /* Input parameter, is a qman or bman portal required. */ -+ enum usdpaa_portal_type type; -+ /* Specifes a specific portal index to map or QBMAN_ANY_PORTAL_IDX -+ for don't care. The portal index will be populated by the -+ driver when the ioctl() successfully completes */ -+ uint32_t index; -+ /* Return value if the map succeeds, this gives the mapped -+ * cache-inhibited (cinh) and cache-enabled (cena) addresses. */ -+ struct usdpaa_portal_map_compat { -+ compat_uptr_t cinh; -+ compat_uptr_t cena; -+ } addr; -+ /* Qman-specific return values */ -+ uint16_t channel; -+ uint32_t pools; -+}; -+#define USDPAA_IOCTL_PORTAL_MAP_COMPAT \ -+ _IOWR(USDPAA_IOCTL_MAGIC, 0x07, struct compat_usdpaa_ioctl_portal_map) -+#define USDPAA_IOCTL_PORTAL_UNMAP_COMPAT \ -+ _IOW(USDPAA_IOCTL_MAGIC, 0x08, struct usdpaa_portal_map_compat) -+#endif -+ -+#define USDPAA_IOCTL_PORTAL_MAP \ -+ _IOWR(USDPAA_IOCTL_MAGIC, 0x07, struct usdpaa_ioctl_portal_map) -+#define USDPAA_IOCTL_PORTAL_UNMAP \ -+ _IOW(USDPAA_IOCTL_MAGIC, 0x08, struct usdpaa_portal_map) -+ -+struct usdpaa_ioctl_irq_map { -+ enum usdpaa_portal_type type; /* Type of portal to map */ -+ int fd; /* File descriptor that contains the portal */ -+ void *portal_cinh; /* Cache inhibited area to identify the portal */ -+}; -+ -+#define USDPAA_IOCTL_PORTAL_IRQ_MAP \ -+ _IOW(USDPAA_IOCTL_MAGIC, 0x09, struct usdpaa_ioctl_irq_map) -+ -+#ifdef CONFIG_COMPAT -+ -+struct compat_ioctl_irq_map { -+ enum usdpaa_portal_type type; /* Type of portal to map */ -+ compat_int_t fd; /* File descriptor that contains the portal */ -+ compat_uptr_t portal_cinh; /* Used identify the portal */}; -+ -+#define USDPAA_IOCTL_PORTAL_IRQ_MAP_COMPAT \ -+ _IOW(USDPAA_IOCTL_MAGIC, 0x09, struct compat_ioctl_irq_map) -+#endif -+ -+/* ioctl to query the amount of DMA memory used in the system */ -+struct usdpaa_ioctl_dma_used { -+ uint64_t free_bytes; -+ uint64_t total_bytes; -+}; -+#define USDPAA_IOCTL_DMA_USED \ -+ _IOR(USDPAA_IOCTL_MAGIC, 0x0B, struct usdpaa_ioctl_dma_used) -+ -+/* ioctl to allocate a raw portal */ -+struct usdpaa_ioctl_raw_portal { -+ /* inputs */ -+ enum usdpaa_portal_type type; /* Type of portal to allocate */ -+ -+ /* set to non zero to turn on stashing */ -+ uint8_t enable_stash; -+ /* Stashing attributes for the portal */ -+ uint32_t cpu; -+ uint32_t cache; -+ uint32_t window; -+ -+ /* Specifies the stash request queue this portal should use */ -+ uint8_t sdest; -+ -+ /* Specifes a specific portal index to map or QBMAN_ANY_PORTAL_IDX -+ * for don't care. The portal index will be populated by the -+ * driver when the ioctl() successfully completes */ -+ uint32_t index; -+ -+ /* outputs */ -+ uint64_t cinh; -+ uint64_t cena; -+}; -+ -+#define USDPAA_IOCTL_ALLOC_RAW_PORTAL \ -+ _IOWR(USDPAA_IOCTL_MAGIC, 0x0C, struct usdpaa_ioctl_raw_portal) -+ -+#define USDPAA_IOCTL_FREE_RAW_PORTAL \ -+ _IOR(USDPAA_IOCTL_MAGIC, 0x0D, struct usdpaa_ioctl_raw_portal) -+ -+#ifdef CONFIG_COMPAT -+ -+struct compat_ioctl_raw_portal { -+ /* inputs */ -+ enum usdpaa_portal_type type; /* Type of portal to allocate */ -+ -+ /* set to non zero to turn on stashing */ -+ uint8_t enable_stash; -+ /* Stashing attributes for the portal */ -+ uint32_t cpu; -+ uint32_t cache; -+ uint32_t window; -+ /* Specifies the stash request queue this portal should use */ -+ uint8_t sdest; -+ -+ /* Specifes a specific portal index to map or QBMAN_ANY_PORTAL_IDX -+ * for don't care. The portal index will be populated by the -+ * driver when the ioctl() successfully completes */ -+ uint32_t index; -+ -+ /* outputs */ -+ uint64_t cinh; -+ uint64_t cena; -+}; -+ -+#define USDPAA_IOCTL_ALLOC_RAW_PORTAL_COMPAT \ -+ _IOWR(USDPAA_IOCTL_MAGIC, 0x0C, struct compat_ioctl_raw_portal) -+ -+#define USDPAA_IOCTL_FREE_RAW_PORTAL_COMPAT \ -+ _IOR(USDPAA_IOCTL_MAGIC, 0x0D, struct compat_ioctl_raw_portal) -+ -+#endif -+ -+#ifdef __KERNEL__ -+ -+/* Early-boot hook */ -+int __init fsl_usdpaa_init_early(void); -+ -+/* Fault-handling in arch/powerpc/mm/mem.c gives USDPAA an opportunity to detect -+ * faults within its ranges via this hook. */ -+int usdpaa_test_fault(unsigned long pfn, u64 *phys_addr, u64 *size); -+ -+#endif /* __KERNEL__ */ -+ -+#endif /* CONFIG_FSL_USDPAA */ -+ -+#ifdef __KERNEL__ -+/* This interface is needed in a few places and though it's not specific to -+ * USDPAA as such, creating a new header for it doesn't make any sense. The -+ * qbman kernel driver implements this interface and uses it as the backend for -+ * both the FQID and BPID allocators. The fsl_usdpaa driver also uses this -+ * interface for tracking per-process allocations handed out to user-space. */ -+struct dpa_alloc { -+ struct list_head free; -+ spinlock_t lock; -+ struct list_head used; -+}; -+#define DECLARE_DPA_ALLOC(name) \ -+ struct dpa_alloc name = { \ -+ .free = { \ -+ .prev = &name.free, \ -+ .next = &name.free \ -+ }, \ -+ .lock = __SPIN_LOCK_UNLOCKED(name.lock), \ -+ .used = { \ -+ .prev = &name.used, \ -+ .next = &name.used \ -+ } \ -+ } -+static inline void dpa_alloc_init(struct dpa_alloc *alloc) -+{ -+ INIT_LIST_HEAD(&alloc->free); -+ INIT_LIST_HEAD(&alloc->used); -+ spin_lock_init(&alloc->lock); -+} -+int dpa_alloc_new(struct dpa_alloc *alloc, u32 *result, u32 count, u32 align, -+ int partial); -+void dpa_alloc_free(struct dpa_alloc *alloc, u32 base_id, u32 count); -+void dpa_alloc_seed(struct dpa_alloc *alloc, u32 fqid, u32 count); -+ -+/* Like 'new' but specifies the desired range, returns -ENOMEM if the entire -+ * desired range is not available, or 0 for success. */ -+int dpa_alloc_reserve(struct dpa_alloc *alloc, u32 base_id, u32 count); -+/* Pops and returns contiguous ranges from the allocator. Returns -ENOMEM when -+ * 'alloc' is empty. */ -+int dpa_alloc_pop(struct dpa_alloc *alloc, u32 *result, u32 *count); -+/* Returns 1 if the specified id is alloced, 0 otherwise */ -+int dpa_alloc_check(struct dpa_alloc *list, u32 id); -+#endif /* __KERNEL__ */ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* FSL_USDPAA_H */ diff --git a/target/linux/layerscape/patches-4.4/7018-devres-add-devm_alloc_percpu.patch b/target/linux/layerscape/patches-4.4/7018-devres-add-devm_alloc_percpu.patch deleted file mode 100644 index 835403e582..0000000000 --- a/target/linux/layerscape/patches-4.4/7018-devres-add-devm_alloc_percpu.patch +++ /dev/null @@ -1,138 +0,0 @@ -From f7792176d939e79b4f525114a95d0fd8266bef8e Mon Sep 17 00:00:00 2001 -From: Madalin Bucur -Date: Wed, 19 Nov 2014 13:06:54 +0200 -Subject: [PATCH 18/70] devres: add devm_alloc_percpu() - -Introduce managed counterparts for alloc_percpu() and free_percpu(). -Add devm_alloc_percpu() and devm_free_percpu() into the managed -interfaces list. - -Signed-off-by: Madalin Bucur - -Change-Id: I93546348e7b0e1974fda8b6c7a3b3710ce45b724 -Reviewed-on: http://git.am.freescale.net:8181/24140 -Reviewed-by: Madalin-Cristian Bucur -Tested-by: Madalin-Cristian Bucur - -Conflicts: - Documentation/driver-model/devres.txt - drivers/base/devres.c - -Conflicts: - drivers/base/devres.c ---- - Documentation/driver-model/devres.txt | 4 +++ - drivers/base/devres.c | 63 +++++++++++++++++++++++++++++++++ - include/linux/device.h | 19 ++++++++++ - 3 files changed, 86 insertions(+) - ---- a/Documentation/driver-model/devres.txt -+++ b/Documentation/driver-model/devres.txt -@@ -321,6 +321,10 @@ PHY - devm_usb_get_phy() - devm_usb_put_phy() - -+PER-CPU MEM -+ devm_alloc_percpu() -+ devm_free_percpu() -+ - PINCTRL - devm_pinctrl_get() - devm_pinctrl_put() ---- a/drivers/base/devres.c -+++ b/drivers/base/devres.c -@@ -985,3 +985,66 @@ void devm_free_pages(struct device *dev, - &devres)); - } - EXPORT_SYMBOL_GPL(devm_free_pages); -+ -+static void devm_percpu_release(struct device *dev, void *pdata) -+{ -+ void __percpu *p; -+ -+ p = *(void __percpu **)pdata; -+ free_percpu(p); -+} -+ -+static int devm_percpu_match(struct device *dev, void *data, void *p) -+{ -+ struct devres *devr = container_of(data, struct devres, data); -+ -+ return *(void **)devr->data == p; -+} -+ -+/** -+ * __devm_alloc_percpu - Resource-managed alloc_percpu -+ * @dev: Device to allocate per-cpu memory for -+ * @size: Size of per-cpu memory to allocate -+ * @align: Alignement of per-cpu memory to allocate -+ * -+ * Managed alloc_percpu. Per-cpu memory allocated with this function is -+ * automatically freed on driver detach. -+ * -+ * RETURNS: -+ * Pointer to allocated memory on success, NULL on failure. -+ */ -+void __percpu *__devm_alloc_percpu(struct device *dev, size_t size, -+ size_t align) -+{ -+ void *p; -+ void __percpu *pcpu; -+ -+ pcpu = __alloc_percpu(size, align); -+ if (!pcpu) -+ return NULL; -+ -+ p = devres_alloc(devm_percpu_release, sizeof(void *), GFP_KERNEL); -+ if (!p) -+ return NULL; -+ -+ *(void __percpu **)p = pcpu; -+ -+ devres_add(dev, p); -+ -+ return pcpu; -+} -+EXPORT_SYMBOL_GPL(__devm_alloc_percpu); -+ -+/** -+ * devm_free_percpu - Resource-managed free_percpu -+ * @dev: Device this memory belongs to -+ * @pdata: Per-cpu memory to free -+ * -+ * Free memory allocated with devm_alloc_percpu(). -+ */ -+void devm_free_percpu(struct device *dev, void __percpu *pdata) -+{ -+ WARN_ON(devres_destroy(dev, devm_percpu_release, devm_percpu_match, -+ (void *)pdata)); -+} -+EXPORT_SYMBOL_GPL(devm_free_percpu); ---- a/include/linux/device.h -+++ b/include/linux/device.h -@@ -683,6 +683,25 @@ void __iomem *devm_ioremap_resource(stru - int devm_add_action(struct device *dev, void (*action)(void *), void *data); - void devm_remove_action(struct device *dev, void (*action)(void *), void *data); - -+/** -+ * devm_alloc_percpu - Resource-managed alloc_percpu -+ * @dev: Device to allocate per-cpu memory for -+ * @type: Type to allocate per-cpu memory for -+ * -+ * Managed alloc_percpu. Per-cpu memory allocated with this function is -+ * automatically freed on driver detach. -+ * -+ * RETURNS: -+ * Pointer to allocated memory on success, NULL on failure. -+ */ -+#define devm_alloc_percpu(dev, type) \ -+ (typeof(type) __percpu *)__devm_alloc_percpu(dev, sizeof(type), \ -+ __alignof__(type)) -+ -+void __percpu *__devm_alloc_percpu(struct device *dev, size_t size, -+ size_t align); -+void devm_free_percpu(struct device *dev, void __percpu *pdata); -+ - struct device_dma_parameters { - /* - * a low level driver may set these to teach IOMMU code about diff --git a/target/linux/layerscape/patches-4.4/7019-net-readd-skb_recycle.patch b/target/linux/layerscape/patches-4.4/7019-net-readd-skb_recycle.patch deleted file mode 100644 index 062233f18b..0000000000 --- a/target/linux/layerscape/patches-4.4/7019-net-readd-skb_recycle.patch +++ /dev/null @@ -1,59 +0,0 @@ -From abc24ef7a69f54c3317beea98078831ba9bfa2cd Mon Sep 17 00:00:00 2001 -From: Madalin Bucur -Date: Tue, 5 Jan 2016 12:12:07 +0200 -Subject: [PATCH 19/70] net: readd skb_recycle() - -Adding back skb_recycle() as it's used by the DPAA Ethernet driver. -This was removed from the upstream kernel because it was lacking users. - -Signed-off-by: Madalin Bucur ---- - include/linux/skbuff.h | 1 + - net/core/skbuff.c | 26 ++++++++++++++++++++++++++ - 2 files changed, 27 insertions(+) - ---- a/include/linux/skbuff.h -+++ b/include/linux/skbuff.h -@@ -799,6 +799,7 @@ void kfree_skb(struct sk_buff *skb); - void kfree_skb_list(struct sk_buff *segs); - void skb_tx_error(struct sk_buff *skb); - void consume_skb(struct sk_buff *skb); -+void skb_recycle(struct sk_buff *skb); - void __kfree_skb(struct sk_buff *skb); - extern struct kmem_cache *skbuff_head_cache; - ---- a/net/core/skbuff.c -+++ b/net/core/skbuff.c -@@ -766,6 +766,32 @@ void consume_skb(struct sk_buff *skb) - } - EXPORT_SYMBOL(consume_skb); - -+/** -+ * skb_recycle - clean up an skb for reuse -+ * @skb: buffer -+ * -+ * Recycles the skb to be reused as a receive buffer. This -+ * function does any necessary reference count dropping, and -+ * cleans up the skbuff as if it just came from __alloc_skb(). -+ */ -+void skb_recycle(struct sk_buff *skb) -+{ -+ struct skb_shared_info *shinfo; -+ u8 head_frag = skb->head_frag; -+ -+ skb_release_head_state(skb); -+ -+ shinfo = skb_shinfo(skb); -+ memset(shinfo, 0, offsetof(struct skb_shared_info, dataref)); -+ atomic_set(&shinfo->dataref, 1); -+ -+ memset(skb, 0, offsetof(struct sk_buff, tail)); -+ skb->data = skb->head + NET_SKB_PAD; -+ skb->head_frag = head_frag; -+ skb_reset_tail_pointer(skb); -+} -+EXPORT_SYMBOL(skb_recycle); -+ - /* Make sure a field is enclosed inside headers_start/headers_end section */ - #define CHECK_SKB_FIELD(field) \ - BUILD_BUG_ON(offsetof(struct sk_buff, field) < \ diff --git a/target/linux/layerscape/patches-4.4/7020-net-add-custom-NETIF-flags.patch b/target/linux/layerscape/patches-4.4/7020-net-add-custom-NETIF-flags.patch deleted file mode 100644 index c89a58c37e..0000000000 --- a/target/linux/layerscape/patches-4.4/7020-net-add-custom-NETIF-flags.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 608986fc6b41633753701d5df9c1ab6a13856608 Mon Sep 17 00:00:00 2001 -From: Madalin Bucur -Date: Mon, 11 Jul 2016 14:14:15 +0800 -Subject: [PATCH 20/70] net: add custom NETIF flags - -commit 6a53650c0c4513429d91e6ad7253340f3d3b9da5 -[context adjustment] - -These flags are used by DPAA Ethernet to impose different behaviors -in the networking stack. - -Signed-off-by: Bogdan Hamciuc -Signed-off-by: Madalin Bucur -Integrated-by: Zhao Qiang ---- - include/linux/netdev_features.h | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/include/linux/netdev_features.h -+++ b/include/linux/netdev_features.h -@@ -66,6 +66,9 @@ enum { - NETIF_F_HW_VLAN_STAG_FILTER_BIT,/* Receive filtering on VLAN STAGs */ - NETIF_F_HW_L2FW_DOFFLOAD_BIT, /* Allow L2 Forwarding in Hardware */ - NETIF_F_BUSY_POLL_BIT, /* Busy poll */ -+ /* Freescale DPA support */ -+ NETIF_F_HW_QDISC_BIT, /* Supports hardware Qdisc */ -+ NETIF_F_HW_ACCEL_MQ_BIT, /* Hardware-accelerated multiqueue */ - - /* - * Add your fresh new feature above and remember to update -@@ -124,6 +127,9 @@ enum { - #define NETIF_F_HW_VLAN_STAG_TX __NETIF_F(HW_VLAN_STAG_TX) - #define NETIF_F_HW_L2FW_DOFFLOAD __NETIF_F(HW_L2FW_DOFFLOAD) - #define NETIF_F_BUSY_POLL __NETIF_F(BUSY_POLL) -+/* Freescale DPA support */ -+#define NETIF_F_HW_QDISC __NETIF_F(HW_QDISC) -+#define NETIF_F_HW_ACCEL_MQ __NETIF_F(HW_ACCEL_MQ) - - #define for_each_netdev_feature(mask_addr, bit) \ - for_each_set_bit(bit, (unsigned long *)mask_addr, NETDEV_FEATURE_COUNT) diff --git a/target/linux/layerscape/patches-4.4/7021-net-Make-the-netdev-watchdog-aware-of-hardware-multi.patch b/target/linux/layerscape/patches-4.4/7021-net-Make-the-netdev-watchdog-aware-of-hardware-multi.patch deleted file mode 100644 index 69bba053a7..0000000000 --- a/target/linux/layerscape/patches-4.4/7021-net-Make-the-netdev-watchdog-aware-of-hardware-multi.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 6aa1eca98ca44f515e10d8058d0ff6db3c8a3c11 Mon Sep 17 00:00:00 2001 -From: Bogdan Hamciuc -Date: Fri, 28 Sep 2012 17:04:33 +0300 -Subject: [PATCH 21/70] net: Make the netdev watchdog aware of hardware - multiqueue devices - -If the netdev declares the NETIF_F_HW_ACCEL_MQ (accelerated multiqueue) -capability, tell the watchdog to consider the per-netdev trans_start -field rather than any individual multiqueue's timestamp. That is -justified by the fact that queues only go in and out of congestion -in groups, not individually, as far as the net device is concerned. - -Change-Id: I07a6693bf1f0bb1e9396c5e232452223a511ecc1 -Signed-off-by: Bogdan Hamciuc -Reviewed-on: http://git.am.freescale.net:8181/1033 -Reviewed-by: Fleming Andrew-AFLEMING -Tested-by: Fleming Andrew-AFLEMING ---- - net/sched/sch_generic.c | 17 ++++++++++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - ---- a/net/sched/sch_generic.c -+++ b/net/sched/sch_generic.c -@@ -290,8 +290,23 @@ static void dev_watchdog(unsigned long a - txq = netdev_get_tx_queue(dev, i); - /* - * old device drivers set dev->trans_start -+ * -+ * (Actually, not only "old" devices, but also -+ * those which perform queue management in a -+ * separate hw accelerator. So even though the -+ * net device itself is single-queued, it makes -+ * sense (and is safe, too) to use kernel's -+ * multiqueue interface, specifically to avoid -+ * unnecessary device locking in SMP systems. -+ * In this case, we ought to consider not an -+ * individual txq's timestamp as a congestion -+ * indicator, but the "old" per-netdev field.) - */ -- trans_start = txq->trans_start ? : dev->trans_start; -+ if (dev->features & NETIF_F_HW_ACCEL_MQ) -+ trans_start = dev->trans_start; -+ else -+ trans_start = txq->trans_start ? : -+ dev->trans_start; - if (netif_xmit_stopped(txq) && - time_after(jiffies, (trans_start + - dev->watchdog_timeo))) { diff --git a/target/linux/layerscape/patches-4.4/7024-Add-APIs-to-setup-HugeTLB-mappings-for-USDPAA.patch b/target/linux/layerscape/patches-4.4/7024-Add-APIs-to-setup-HugeTLB-mappings-for-USDPAA.patch deleted file mode 100644 index f0247f0dea..0000000000 --- a/target/linux/layerscape/patches-4.4/7024-Add-APIs-to-setup-HugeTLB-mappings-for-USDPAA.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 2dcd28f7b4f5b92686da45f4ec46802026fb8573 Mon Sep 17 00:00:00 2001 -From: Roy Pledge -Date: Mon, 11 Jul 2016 14:34:59 +0800 -Subject: [PATCH 24/70] Add APIs to setup HugeTLB mappings for USDPAA - -commit 189653d40d5dc41b8bd4cfb61f766bd8a89b1e34 -[context adjustment] - -Signed-off-by: Zhao Qiang ---- - arch/powerpc/mm/fsl_booke_mmu.c | 14 +++++++++++++- - arch/powerpc/mm/mmu_decl.h | 6 ++++++ - 2 files changed, 19 insertions(+), 1 deletion(-) - ---- a/arch/powerpc/mm/fsl_booke_mmu.c -+++ b/arch/powerpc/mm/fsl_booke_mmu.c -@@ -105,7 +105,7 @@ unsigned long p_mapped_by_tlbcam(phys_ad - * an unsigned long (for example, 32-bit implementations cannot support a 4GB - * size). - */ --static void settlbcam(int index, unsigned long virt, phys_addr_t phys, -+void settlbcam(int index, unsigned long virt, phys_addr_t phys, - unsigned long size, unsigned long flags, unsigned int pid) - { - unsigned int tsize; -@@ -143,6 +143,18 @@ static void settlbcam(int index, unsigne - tlbcam_addrs[index].phys = phys; - } - -+void cleartlbcam(unsigned long virt, unsigned int pid) -+{ -+ int i = 0; -+ for (i = 0; i < NUM_TLBCAMS; i++) { -+ if (tlbcam_addrs[i].start == virt) { -+ TLBCAM[i].MAS1 = 0; -+ loadcam_entry(i); -+ return; -+ } -+ } -+} -+ - unsigned long calc_cam_sz(unsigned long ram, unsigned long virt, - phys_addr_t phys) - { ---- a/arch/powerpc/mm/mmu_decl.h -+++ b/arch/powerpc/mm/mmu_decl.h -@@ -91,6 +91,12 @@ extern void _tlbia(void); - - #endif /* CONFIG_PPC_MMU_NOHASH */ - -+void settlbcam(int index, unsigned long virt, phys_addr_t phys, -+ unsigned long size, unsigned long flags, unsigned int pid); -+ -+void cleartlbcam(unsigned long virt, unsigned int pid); -+ -+ - #ifdef CONFIG_PPC32 - - extern void mapin_ram(void); diff --git a/target/linux/layerscape/patches-4.4/7029-fmd-SGMII-PCS-needs-to-be-reprogrammed-after-sleep.patch b/target/linux/layerscape/patches-4.4/7029-fmd-SGMII-PCS-needs-to-be-reprogrammed-after-sleep.patch deleted file mode 100644 index 8c10e3d9f5..0000000000 --- a/target/linux/layerscape/patches-4.4/7029-fmd-SGMII-PCS-needs-to-be-reprogrammed-after-sleep.patch +++ /dev/null @@ -1,228 +0,0 @@ -From afcfdda960da9d9ad4c4d21c7dd0cc7791cf36c7 Mon Sep 17 00:00:00 2001 -From: Madalin Bucur -Date: Wed, 4 May 2016 19:24:53 +0300 -Subject: [PATCH 29/70] fmd: SGMII PCS needs to be reprogrammed after sleep - -Signed-off-by: Madalin Bucur ---- - drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.c | 6 ++ - .../freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c | 1 + - .../freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c | 12 ++++ - .../freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h | 1 + - .../freescale/sdk_fman/Peripherals/FM/MAC/memac.c | 58 +++++++++++--------- - .../freescale/sdk_fman/Peripherals/FM/MAC/tgec.c | 1 + - .../sdk_fman/inc/Peripherals/fm_mac_ext.h | 13 +++++ - .../sdk_fman/src/inc/wrapper/lnxwrp_fsl_fman.h | 2 + - .../freescale/sdk_fman/src/wrapper/lnxwrp_fm.c | 14 +++++ - 9 files changed, 83 insertions(+), 25 deletions(-) - ---- a/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.c -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.c -@@ -175,6 +175,12 @@ static int dpaa_resume(struct device *de - priv = netdev_priv(net_dev); - mac_dev = priv->mac_dev; - -+ err = fm_mac_resume(mac_dev->get_mac_handle(mac_dev)); -+ if (err) { -+ netdev_err(net_dev, "fm_mac_resume = %d\n", err); -+ goto resume_failed; -+ } -+ - err = fm_port_resume(mac_dev->port_dev[TX]); - if (err) { - netdev_err(net_dev, "fm_port_resume(TX) = %d\n", err); ---- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c -@@ -1371,6 +1371,7 @@ static void InitFmMacControllerDriver(t_ - - p_FmMacControllerDriver->f_FM_MAC_Enable = DtsecEnable; - p_FmMacControllerDriver->f_FM_MAC_Disable = DtsecDisable; -+ p_FmMacControllerDriver->f_FM_MAC_Resume = NULL; - - p_FmMacControllerDriver->f_FM_MAC_SetException = DtsecSetException; - ---- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c -@@ -299,6 +299,18 @@ t_Error FM_MAC_Disable (t_Handle h_FmMac - RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG); - } - -+t_Error FM_MAC_Resume (t_Handle h_FmMac) -+{ -+ t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac; -+ -+ SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE); -+ -+ if (p_FmMacControllerDriver->f_FM_MAC_Resume) -+ return p_FmMacControllerDriver->f_FM_MAC_Resume(h_FmMac); -+ -+ return E_OK; -+} -+ - /* ......................................................................... */ - - t_Error FM_MAC_Enable1588TimeStamp (t_Handle h_FmMac) ---- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h -@@ -91,6 +91,7 @@ typedef struct { - - t_Error (*f_FM_MAC_Enable) (t_Handle h_FmMac, e_CommMode mode); - t_Error (*f_FM_MAC_Disable) (t_Handle h_FmMac, e_CommMode mode); -+ t_Error (*f_FM_MAC_Resume) (t_Handle h_FmMac); - t_Error (*f_FM_MAC_Enable1588TimeStamp) (t_Handle h_FmMac); - t_Error (*f_FM_MAC_Disable1588TimeStamp) (t_Handle h_FmMac); - t_Error (*f_FM_MAC_Reset) (t_Handle h_FmMac, bool wait); ---- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c -@@ -812,6 +812,37 @@ static uint16_t MemacGetMaxFrameLength(t - return fman_memac_get_max_frame_len(p_Memac->p_MemMap); - } - -+static t_Error MemacInitInternalPhy(t_Handle h_Memac) -+{ -+ t_Memac *p_Memac = (t_Memac *)h_Memac; -+ uint8_t i, phyAddr; -+ -+ if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_SGMII) -+ { -+ /* Configure internal SGMII PHY */ -+ if (p_Memac->enetMode & ENET_IF_SGMII_BASEX) -+ SetupSgmiiInternalPhyBaseX(p_Memac, PHY_MDIO_ADDR); -+ else -+ SetupSgmiiInternalPhy(p_Memac, PHY_MDIO_ADDR); -+ } -+ else if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_QSGMII) -+ { -+ /* Configure 4 internal SGMII PHYs */ -+ for (i = 0; i < 4; i++) -+ { -+ /* QSGMII PHY address occupies 3 upper bits of 5-bit -+ phyAddress; the lower 2 bits are used to extend -+ register address space and access each one of 4 -+ ports inside QSGMII. */ -+ phyAddr = (uint8_t)((PHY_MDIO_ADDR << 2) | i); -+ if (p_Memac->enetMode & ENET_IF_SGMII_BASEX) -+ SetupSgmiiInternalPhyBaseX(p_Memac, phyAddr); -+ else -+ SetupSgmiiInternalPhy(p_Memac, phyAddr); -+ } -+ } -+ return E_OK; -+} - - /*****************************************************************************/ - /* mEMAC Init & Free API */ -@@ -825,7 +856,6 @@ static t_Error MemacInit(t_Handle h_Mema - struct memac_cfg *p_MemacDriverParam; - enum enet_interface enet_interface; - enum enet_speed enet_speed; -- uint8_t i, phyAddr; - t_EnetAddr ethAddr; - e_FmMacType portType; - t_Error err; -@@ -887,30 +917,7 @@ static t_Error MemacInit(t_Handle h_Mema - } - #endif /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 */ - -- if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_SGMII) -- { -- /* Configure internal SGMII PHY */ -- if (p_Memac->enetMode & ENET_IF_SGMII_BASEX) -- SetupSgmiiInternalPhyBaseX(p_Memac, PHY_MDIO_ADDR); -- else -- SetupSgmiiInternalPhy(p_Memac, PHY_MDIO_ADDR); -- } -- else if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_QSGMII) -- { -- /* Configure 4 internal SGMII PHYs */ -- for (i = 0; i < 4; i++) -- { -- /* QSGMII PHY address occupies 3 upper bits of 5-bit -- phyAddress; the lower 2 bits are used to extend -- register address space and access each one of 4 -- ports inside QSGMII. */ -- phyAddr = (uint8_t)((PHY_MDIO_ADDR << 2) | i); -- if (p_Memac->enetMode & ENET_IF_SGMII_BASEX) -- SetupSgmiiInternalPhyBaseX(p_Memac, phyAddr); -- else -- SetupSgmiiInternalPhy(p_Memac, phyAddr); -- } -- } -+ MemacInitInternalPhy(h_Memac); - - /* Max Frame Length */ - err = FmSetMacMaxFrame(p_Memac->fmMacControllerDriver.h_Fm, -@@ -1008,6 +1015,7 @@ static void InitFmMacControllerDriver(t_ - - p_FmMacControllerDriver->f_FM_MAC_Enable = MemacEnable; - p_FmMacControllerDriver->f_FM_MAC_Disable = MemacDisable; -+ p_FmMacControllerDriver->f_FM_MAC_Resume = MemacInitInternalPhy; - - p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames = MemacSetTxAutoPauseFrames; - p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames = MemacSetTxPauseFrames; ---- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.c -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.c -@@ -897,6 +897,7 @@ static void InitFmMacControllerDriver(t_ - - p_FmMacControllerDriver->f_FM_MAC_Enable = TgecEnable; - p_FmMacControllerDriver->f_FM_MAC_Disable = TgecDisable; -+ p_FmMacControllerDriver->f_FM_MAC_Resume = NULL; - - p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames = TgecTxMacPause; - p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames = TgecSetTxPauseFrames; ---- a/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_mac_ext.h -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_mac_ext.h -@@ -467,6 +467,19 @@ t_Error FM_MAC_Enable(t_Handle h_FmMac, - t_Error FM_MAC_Disable(t_Handle h_FmMac, e_CommMode mode); - - /**************************************************************************//** -+ @Function FM_MAC_Resume -+ -+ @Description Re-init the MAC after suspend -+ -+ @Param[in] h_FmMac A handle to a FM MAC Module. -+ -+ @Return E_OK on success; Error code otherwise. -+ -+ @Cautions Allowed only following FM_MAC_Init(). -+*//***************************************************************************/ -+t_Error FM_MAC_Resume(t_Handle h_FmMac); -+ -+/**************************************************************************//** - @Function FM_MAC_Enable1588TimeStamp - - @Description Enables the TSU operation. ---- a/drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/lnxwrp_fsl_fman.h -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/lnxwrp_fsl_fman.h -@@ -765,6 +765,8 @@ int fm_mac_enable(struct fm_mac_dev *fm_ - - int fm_mac_disable(struct fm_mac_dev *fm_mac_dev); - -+int fm_mac_resume(struct fm_mac_dev *fm_mac_dev); -+ - int fm_mac_set_promiscuous(struct fm_mac_dev *fm_mac_dev, - bool enable); - ---- a/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_fm.c -+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_fm.c -@@ -1733,6 +1733,20 @@ int fm_mac_disable(struct fm_mac_dev *fm - } - EXPORT_SYMBOL(fm_mac_disable); - -+int fm_mac_resume(struct fm_mac_dev *fm_mac_dev) -+{ -+ int _errno; -+ t_Error err; -+ -+ err = FM_MAC_Resume(fm_mac_dev); -+ _errno = -GET_ERROR_TYPE(err); -+ if (unlikely(_errno < 0)) -+ pr_err("FM_MAC_Resume() = 0x%08x\n", err); -+ -+ return _errno; -+} -+EXPORT_SYMBOL(fm_mac_resume); -+ - int fm_mac_set_promiscuous(struct fm_mac_dev *fm_mac_dev, - bool enable) - { diff --git a/target/linux/layerscape/patches-4.4/7030-fmd-use-kernel-api-for-64bit-division.patch b/target/linux/layerscape/patches-4.4/7030-fmd-use-kernel-api-for-64bit-division.patch deleted file mode 100644 index cd2283ca77..0000000000 --- a/target/linux/layerscape/patches-4.4/7030-fmd-use-kernel-api-for-64bit-division.patch +++ /dev/null @@ -1,178 +0,0 @@ -From c86be7b4f9ca4f4c8c916a9c350edbcd0e86a528 Mon Sep 17 00:00:00 2001 -From: Madalin Bucur -Date: Mon, 18 Apr 2016 16:41:59 +0300 -Subject: [PATCH 30/70] fmd: use kernel api for 64bit division - -Signed-off-by: Madalin Bucur ---- - .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c | 1 + - .../sdk_fman/Peripherals/FM/Pcd/fm_plcr.c | 5 +++-- - .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.c | 1 + - .../freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.c | 12 ++++++------ - .../freescale/sdk_fman/Peripherals/FM/fm.c | 5 +++-- - .../freescale/sdk_fman/Peripherals/FM/fman.c | 7 +++---- - .../net/ethernet/freescale/sdk_fman/inc/math_ext.h | 1 + - .../net/ethernet/freescale/sdk_fman/inc/ncsw_ext.h | 2 +- - 8 files changed, 19 insertions(+), 15 deletions(-) - ---- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c -@@ -36,6 +36,7 @@ - - @Description FM Coarse Classifier implementation - *//***************************************************************************/ -+#include - #include "std_ext.h" - #include "error_ext.h" - #include "string_ext.h" ---- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_plcr.c -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_plcr.c -@@ -36,6 +36,7 @@ - - @Description FM PCD POLICER... - *//***************************************************************************/ -+#include - #include "std_ext.h" - #include "error_ext.h" - #include "string_ext.h" -@@ -205,13 +206,13 @@ static void GetInfoRateReg(e_FmPcdPlcrRa - div = 1000000000; /* nano */ - div *= 10; /* 10 nano */ - } -- *p_Integer = (tmp< - #include "std_ext.h" - #include "error_ext.h" - #include "string_ext.h" ---- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.c -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.c -@@ -38,7 +38,7 @@ - - @Cautions None - *//***************************************************************************/ -- -+#include - #include "error_ext.h" - #include "debug_ext.h" - #include "string_ext.h" -@@ -470,11 +470,11 @@ t_Error FM_RTC_SetAlarm(t_Handle h_FmRtc - RETURN_ERROR(MAJOR, E_INVALID_SELECTION, - ("Alarm time must be equal or larger than RTC period - %d nanoseconds", - p_Rtc->clockPeriodNanoSec)); -- if (p_FmRtcAlarmParams->alarmTime % (uint64_t)p_Rtc->clockPeriodNanoSec) -+ tmpAlarm = p_FmRtcAlarmParams->alarmTime; -+ if (do_div(tmpAlarm, p_Rtc->clockPeriodNanoSec)) - RETURN_ERROR(MAJOR, E_INVALID_SELECTION, - ("Alarm time must be a multiple of RTC period - %d nanoseconds", - p_Rtc->clockPeriodNanoSec)); -- tmpAlarm = p_FmRtcAlarmParams->alarmTime/(uint64_t)p_Rtc->clockPeriodNanoSec; - - if (p_FmRtcAlarmParams->f_AlarmCallback) - { -@@ -508,11 +508,11 @@ t_Error FM_RTC_SetPeriodicPulse(t_Handle - RETURN_ERROR(MAJOR, E_INVALID_SELECTION, - ("Periodic pulse must be equal or larger than RTC period - %d nanoseconds", - p_Rtc->clockPeriodNanoSec)); -- if (p_FmRtcPeriodicPulseParams->periodicPulsePeriod % (uint64_t)p_Rtc->clockPeriodNanoSec) -+ tmpFiper = p_FmRtcPeriodicPulseParams->periodicPulsePeriod; -+ if (do_div(tmpFiper, p_Rtc->clockPeriodNanoSec)) - RETURN_ERROR(MAJOR, E_INVALID_SELECTION, - ("Periodic pulse must be a multiple of RTC period - %d nanoseconds", - p_Rtc->clockPeriodNanoSec)); -- tmpFiper = p_FmRtcPeriodicPulseParams->periodicPulsePeriod/(uint64_t)p_Rtc->clockPeriodNanoSec; - if (tmpFiper & 0xffffffff00000000LL) - RETURN_ERROR(MAJOR, E_INVALID_SELECTION, - ("Periodic pulse/RTC Period must be smaller than 4294967296", -@@ -628,7 +628,7 @@ t_Error FM_RTC_SetCurrentTime(t_Handle h - SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE); - SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE); - -- ts = ts/p_Rtc->clockPeriodNanoSec; -+ do_div(ts, p_Rtc->clockPeriodNanoSec); - fman_rtc_set_timer(p_Rtc->p_MemMap, (int64_t)ts); - - return E_OK; ---- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm.c -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm.c -@@ -43,6 +43,7 @@ - #include "sprint_ext.h" - #include "debug_ext.h" - #include "fm_muram_ext.h" -+#include - - #include "fm_common.h" - #include "fm_ipc.h" -@@ -5087,9 +5088,9 @@ t_Error FM_CtrlMonGetCounters(t_Handle h - effValue = (uint64_t) - ((uint64_t)GET_UINT32(p_MonRegs->tpc2h) << 32 | GET_UINT32(p_MonRegs->tpc2l)); - -- p_Mon->percentCnt[0] = (uint8_t)((clkCnt - utilValue) * 100 / clkCnt); -+ p_Mon->percentCnt[0] = (uint8_t)div64_u64((clkCnt - utilValue) * 100, clkCnt); - if (clkCnt != utilValue) -- p_Mon->percentCnt[1] = (uint8_t)(((clkCnt - utilValue) - effValue) * 100 / (clkCnt - utilValue)); -+ p_Mon->percentCnt[1] = (uint8_t)div64_u64(((clkCnt - utilValue) - effValue) * 100, clkCnt - utilValue); - else - p_Mon->percentCnt[1] = 0; - ---- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fman.c -+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fman.c -@@ -31,7 +31,7 @@ - */ - - -- -+#include - #include "fsl_fman.h" - #include "dpaa_integration_ext.h" - -@@ -186,10 +186,9 @@ void fman_enable_time_stamp(struct fman_ - * we do not div back, since we write this value as a fraction - * see spec */ - -- frac = (((uint64_t)ts_freq << 16) - ((uint64_t)intgr << 16) * fm_clk_freq) -- / fm_clk_freq; -+ frac = ((uint64_t)ts_freq << 16) - ((uint64_t)intgr << 16) * fm_clk_freq; - /* we check remainder of the division in order to round up if not int */ -- if (((ts_freq << 16) - (intgr << 16)*fm_clk_freq) % fm_clk_freq) -+ if (do_div(frac, fm_clk_freq)) - frac++; - - tmp = (intgr << FPM_TS_INT_SHIFT) | (uint16_t)frac; ---- a/drivers/net/ethernet/freescale/sdk_fman/inc/math_ext.h -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/math_ext.h -@@ -37,6 +37,7 @@ - - #if defined(NCSW_LINUX) && defined(__KERNEL__) - #include -+#include - - #elif defined(__MWERKS__) - #define LOW(x) ( sizeof(x)==8 ? *(1+(int32_t*)&x) : (*(int32_t*)&x)) ---- a/drivers/net/ethernet/freescale/sdk_fman/inc/ncsw_ext.h -+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/ncsw_ext.h -@@ -142,7 +142,7 @@ do - } while (0) - - /* Ceiling division - not the fastest way, but safer in terms of overflow */ --#define DIV_CEIL(x,y) (((x)/(y)) + ((((((x)/(y)))*(y)) == (x)) ? 0 : 1)) -+#define DIV_CEIL(x,y) (div64_u64((x),(y)) + (((div64_u64((x),(y))*(y)) == (x)) ? 0 : 1)) - - /* Round up a number to be a multiple of a second number */ - #define ROUND_UP(x,y) ((((x) + (y) - 1) / (y)) * (y)) diff --git a/target/linux/layerscape/patches-4.4/7031-fsl_qbman-Enable-DPAA1-QBMan-for-ARM64-platforms.patch b/target/linux/layerscape/patches-4.4/7031-fsl_qbman-Enable-DPAA1-QBMan-for-ARM64-platforms.patch deleted file mode 100644 index 24f79895da..0000000000 --- a/target/linux/layerscape/patches-4.4/7031-fsl_qbman-Enable-DPAA1-QBMan-for-ARM64-platforms.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d0a7d97bdfb7a755d55bb53725d71f81aab90fe7 Mon Sep 17 00:00:00 2001 -From: Roy Pledge -Date: Thu, 14 Apr 2016 10:21:02 +0800 -Subject: [PATCH 31/70] fsl_qbman: Enable DPAA1 QBMan for ARM64 platforms - -commit ddb0ae0f9d638efc70402d4fb570bca3a3178091 -[context adjustment] - -Enable the QBMan device for ARM64 platofrms. This is needed for -ARM based SoCs that have DPAA1 such as the LS1043A - -Signed-off-by: Roy Pledge -Integrated-by: Zhao Qiang ---- - arch/arm64/Kconfig | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/Kconfig -+++ b/arch/arm64/Kconfig -@@ -187,6 +187,11 @@ source "arch/arm64/Kconfig.platforms" - - menu "Bus support" - -+config HAS_FSL_QBMAN -+ bool "Datapath Acceleration Queue and Buffer management" -+ help -+ Datapath Acceleration Queue and Buffer management -+ - config PCI - bool "PCI support" - help diff --git a/target/linux/layerscape/patches-4.4/7064-dpaa_eth-repair-issue-introduced-with-2.5G-support.patch b/target/linux/layerscape/patches-4.4/7064-dpaa_eth-repair-issue-introduced-with-2.5G-support.patch deleted file mode 100644 index 929e2103b3..0000000000 --- a/target/linux/layerscape/patches-4.4/7064-dpaa_eth-repair-issue-introduced-with-2.5G-support.patch +++ /dev/null @@ -1,22 +0,0 @@ -From e555d24e5df9b2d5b8a613ff46af68fc3ff3a360 Mon Sep 17 00:00:00 2001 -From: Madalin Bucur -Date: Wed, 30 Mar 2016 16:12:33 +0300 -Subject: [PATCH 64/70] dpaa_eth: repair issue introduced with 2.5G support - -Signed-off-by: Madalin Bucur ---- - drivers/net/ethernet/freescale/sdk_dpaa/mac.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/net/ethernet/freescale/sdk_dpaa/mac.c -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac.c -@@ -346,7 +346,8 @@ static int __cold mac_probe(struct platf - SUPPORTED_100baseT_Half); - - /* Gigabit support (no half-duplex) */ -- if (mac_dev->max_speed == 1000) -+ if (mac_dev->max_speed == SPEED_1000 || -+ mac_dev->max_speed == SPEED_2500) - mac_dev->if_support |= SUPPORTED_1000baseT_Full; - - /* The 10G interface only supports one mode */ diff --git a/target/linux/layerscape/patches-4.4/7065-dpaa_eth-replace-sgmii-2500-with-qsgmii.patch b/target/linux/layerscape/patches-4.4/7065-dpaa_eth-replace-sgmii-2500-with-qsgmii.patch deleted file mode 100644 index ed44a1f270..0000000000 --- a/target/linux/layerscape/patches-4.4/7065-dpaa_eth-replace-sgmii-2500-with-qsgmii.patch +++ /dev/null @@ -1,39 +0,0 @@ -From a768af05b1ffe644f54303036e5c048952e0f721 Mon Sep 17 00:00:00 2001 -From: Madalin Bucur -Date: Mon, 4 Apr 2016 20:23:21 +0300 -Subject: [PATCH 65/70] dpaa_eth: replace sgmii-2500 with qsgmii - -Signed-off-by: Madalin Bucur ---- - drivers/net/ethernet/freescale/sdk_dpaa/mac.c | 6 ------ - 1 file changed, 6 deletions(-) - ---- a/drivers/net/ethernet/freescale/sdk_dpaa/mac.c -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac.c -@@ -74,7 +74,6 @@ static const char phy_str[][11] = { - [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", - [PHY_INTERFACE_MODE_RTBI] = "rtbi", - [PHY_INTERFACE_MODE_XGMII] = "xgmii", -- [PHY_INTERFACE_MODE_QSGMII] = "sgmii-2500" - }; - - static phy_interface_t __pure __attribute__((nonnull)) str2phy(const char *str) -@@ -101,7 +100,6 @@ static const uint16_t phy2speed[] = { - [PHY_INTERFACE_MODE_RGMII_TXID] = SPEED_1000, - [PHY_INTERFACE_MODE_RTBI] = SPEED_1000, - [PHY_INTERFACE_MODE_XGMII] = SPEED_10000, -- [PHY_INTERFACE_MODE_QSGMII] = SPEED_2500 - }; - - static struct mac_device * __cold -@@ -341,10 +339,6 @@ static int __cold mac_probe(struct platf - mac_dev->if_support &= ~(SUPPORTED_10baseT_Half | - SUPPORTED_100baseT_Half); - -- if (strstr(char_prop, "sgmii-2500")) -- mac_dev->if_support &= ~(SUPPORTED_10baseT_Half | -- SUPPORTED_100baseT_Half); -- - /* Gigabit support (no half-duplex) */ - if (mac_dev->max_speed == SPEED_1000 || - mac_dev->max_speed == SPEED_2500) diff --git a/target/linux/layerscape/patches-4.4/7066-fmd-add-2.5G-SGMII-mode-suport.patch b/target/linux/layerscape/patches-4.4/7066-fmd-add-2.5G-SGMII-mode-suport.patch deleted file mode 100644 index 4014ab4e2a..0000000000 --- a/target/linux/layerscape/patches-4.4/7066-fmd-add-2.5G-SGMII-mode-suport.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 95d12688fa875f7a00590aaf6de5f34d55531d68 Mon Sep 17 00:00:00 2001 -From: Madalin Bucur -Date: Thu, 14 Apr 2016 14:12:38 +0300 -Subject: [PATCH 66/70] fmd: add 2.5G SGMII mode suport - -Signed-off-by: Madalin Bucur ---- - drivers/net/ethernet/freescale/sdk_dpaa/mac.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/drivers/net/ethernet/freescale/sdk_dpaa/mac.c -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac.c -@@ -74,6 +74,7 @@ static const char phy_str[][11] = { - [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", - [PHY_INTERFACE_MODE_RTBI] = "rtbi", - [PHY_INTERFACE_MODE_XGMII] = "xgmii", -+ [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", - }; - - static phy_interface_t __pure __attribute__((nonnull)) str2phy(const char *str) -@@ -100,6 +101,7 @@ static const uint16_t phy2speed[] = { - [PHY_INTERFACE_MODE_RGMII_TXID] = SPEED_1000, - [PHY_INTERFACE_MODE_RTBI] = SPEED_1000, - [PHY_INTERFACE_MODE_XGMII] = SPEED_10000, -+ [PHY_INTERFACE_MODE_SGMII_2500] = SPEED_2500, - }; - - static struct mac_device * __cold -@@ -335,7 +337,8 @@ static int __cold mac_probe(struct platf - mac_dev->max_speed = mac_dev->speed; - mac_dev->if_support = DTSEC_SUPPORTED; - /* We don't support half-duplex in SGMII mode */ -- if (strstr(char_prop, "sgmii") || strstr(char_prop, "qsgmii")) -+ if (strstr(char_prop, "sgmii") || strstr(char_prop, "qsgmii") || -+ strstr(char_prop, "sgmii-2500")) - mac_dev->if_support &= ~(SUPPORTED_10baseT_Half | - SUPPORTED_100baseT_Half); - diff --git a/target/linux/layerscape/patches-4.4/7067-net-phy-add-SGMII-2500-PHY.patch b/target/linux/layerscape/patches-4.4/7067-net-phy-add-SGMII-2500-PHY.patch deleted file mode 100644 index 42e6b5cd98..0000000000 --- a/target/linux/layerscape/patches-4.4/7067-net-phy-add-SGMII-2500-PHY.patch +++ /dev/null @@ -1,20 +0,0 @@ -From 6e4322d938f01f58156b0a5929daa648ecad4754 Mon Sep 17 00:00:00 2001 -From: Madalin Bucur -Date: Thu, 14 Apr 2016 12:03:52 +0300 -Subject: [PATCH 67/70] net: phy: add SGMII 2500 PHY - -Signed-off-by: Madalin Bucur ---- - include/linux/phy.h | 1 + - 1 file changed, 1 insertion(+) - ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -77,6 +77,7 @@ typedef enum { - PHY_INTERFACE_MODE_XGMII, - PHY_INTERFACE_MODE_MOCA, - PHY_INTERFACE_MODE_QSGMII, -+ PHY_INTERFACE_MODE_SGMII_2500, - PHY_INTERFACE_MODE_MAX, - } phy_interface_t; - diff --git a/target/linux/layerscape/patches-4.4/7068-dpaa_ethernet-fix-link-state-detect-for-10G-interfac.patch b/target/linux/layerscape/patches-4.4/7068-dpaa_ethernet-fix-link-state-detect-for-10G-interfac.patch deleted file mode 100644 index 08dafdda0f..0000000000 --- a/target/linux/layerscape/patches-4.4/7068-dpaa_ethernet-fix-link-state-detect-for-10G-interfac.patch +++ /dev/null @@ -1,63 +0,0 @@ -From f77f25498902f84d53a64a6397db2fa4b0d0dd4b Mon Sep 17 00:00:00 2001 -From: Shaohui Xie -Date: Thu, 31 Mar 2016 10:53:06 +0800 -Subject: [PATCH 68/70] dpaa_ethernet: fix link state detect for 10G interface - -There are drivers to support 10G PHYs with copper interface, so we -change binding between MAC and 10G PHY to use phy_state_machine to -detect link state. - -Signed-off-by: Shaohui Xie ---- - drivers/net/ethernet/freescale/sdk_dpaa/mac-api.c | 20 ++++++++------------ - 1 file changed, 8 insertions(+), 12 deletions(-) - ---- a/drivers/net/ethernet/freescale/sdk_dpaa/mac-api.c -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac-api.c -@@ -279,20 +279,15 @@ static int __cold start(struct mac_devic - - _errno = fm_mac_enable(mac_dev->get_mac_handle(mac_dev)); - -- if (!_errno && phy_dev) { -- if (macdev2enetinterface(mac_dev) != e_ENET_MODE_XGMII_10000) -- phy_start(phy_dev); -- else if (phy_dev->drv->read_status) -- phy_dev->drv->read_status(phy_dev); -- } -+ if (!_errno && phy_dev) -+ phy_start(phy_dev); - - return _errno; - } - - static int __cold stop(struct mac_device *mac_dev) - { -- if (mac_dev->phy_dev && -- (macdev2enetinterface(mac_dev) != e_ENET_MODE_XGMII_10000)) -+ if (mac_dev->phy_dev) - phy_stop(mac_dev->phy_dev); - - return fm_mac_disable(mac_dev->get_mac_handle(mac_dev)); -@@ -477,8 +472,8 @@ static int xgmac_init_phy(struct net_dev - phy_dev = phy_attach(net_dev, mac_dev->fixed_bus_id, - mac_dev->phy_if); - else -- phy_dev = of_phy_attach(net_dev, mac_dev->phy_node, 0, -- mac_dev->phy_if); -+ phy_dev = of_phy_connect(net_dev, mac_dev->phy_node, -+ &adjust_link, 0, mac_dev->phy_if); - if (unlikely(phy_dev == NULL) || IS_ERR(phy_dev)) { - netdev_err(net_dev, "Could not attach to PHY %s\n", - mac_dev->phy_node ? -@@ -510,8 +505,9 @@ static int memac_init_phy(struct net_dev - mac_dev->phy_dev = NULL; - return 0; - } else -- phy_dev = of_phy_attach(net_dev, mac_dev->phy_node, 0, -- mac_dev->phy_if); -+ phy_dev = of_phy_connect(net_dev, mac_dev->phy_node, -+ &adjust_link, 0, -+ mac_dev->phy_if); - } else { - if (!mac_dev->phy_node) - phy_dev = phy_connect(net_dev, mac_dev->fixed_bus_id, diff --git a/target/linux/layerscape/patches-4.4/7072-LS1012-Add-PPFE-driver-in-Linux.patch b/target/linux/layerscape/patches-4.4/7072-LS1012-Add-PPFE-driver-in-Linux.patch deleted file mode 100644 index 21339e819e..0000000000 --- a/target/linux/layerscape/patches-4.4/7072-LS1012-Add-PPFE-driver-in-Linux.patch +++ /dev/null @@ -1,15167 +0,0 @@ -From 0157efe2fbe2fe56c34727d326cd74284c06cbd5 Mon Sep 17 00:00:00 2001 -From: Bhaskar Upadhaya -Date: Wed, 24 Aug 2016 10:51:21 +0800 -Subject: [PATCH 072/113] LS1012: Add PPFE driver in Linux - -commit 7584b690d4c8e4e435c2e6abcdb38d6595a0c302 -[context adjustment] -[don't apply fsl-ls1012a-rdb.dts and fsl-ls1012a.dtsi] -[Let PPFE driver can be selectd as a module] - -Signed-off-by: Bhaskar Upadhaya -Integrated-by: Zhao Qiang -Integrated-by: Yutang Jiang ---- - drivers/staging/Kconfig | 2 + - drivers/staging/Makefile | 1 + - drivers/staging/fsl_ppfe/Kconfig | 5 + - drivers/staging/fsl_ppfe/Makefile | 44 + - drivers/staging/fsl_ppfe/config.h | 8 + - drivers/staging/fsl_ppfe/control_link.lds | 32 + - drivers/staging/fsl_ppfe/include/pfe/cbus.h | 88 + - drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h | 55 + - .../staging/fsl_ppfe/include/pfe/cbus/class_csr.h | 242 ++ - drivers/staging/fsl_ppfe/include/pfe/cbus/emac.h | 243 ++ - .../staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h | 250 ++ - drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h | 78 + - drivers/staging/fsl_ppfe/include/pfe/cbus/gpt.h | 29 + - drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h | 96 + - .../staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h | 51 + - .../staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h | 128 + - .../staging/fsl_ppfe/include/pfe/cbus/util_csr.h | 61 + - drivers/staging/fsl_ppfe/include/pfe/class.h | 133 + - drivers/staging/fsl_ppfe/include/pfe/class/ccu.h | 28 + - drivers/staging/fsl_ppfe/include/pfe/class/efet.h | 44 + - .../staging/fsl_ppfe/include/pfe/class/mac_hash.h | 55 + - drivers/staging/fsl_ppfe/include/pfe/class/perg.h | 39 + - .../staging/fsl_ppfe/include/pfe/class/vlan_hash.h | 46 + - drivers/staging/fsl_ppfe/include/pfe/gpt.h | 44 + - drivers/staging/fsl_ppfe/include/pfe/pe.h | 626 +++++ - drivers/staging/fsl_ppfe/include/pfe/pfe.h | 444 +++ - drivers/staging/fsl_ppfe/include/pfe/tmu.h | 68 + - .../staging/fsl_ppfe/include/pfe/tmu/phy_queue.h | 56 + - drivers/staging/fsl_ppfe/include/pfe/tmu/sched.h | 72 + - drivers/staging/fsl_ppfe/include/pfe/tmu/shaper.h | 37 + - drivers/staging/fsl_ppfe/include/pfe/uart.h | 31 + - drivers/staging/fsl_ppfe/include/pfe/util.h | 49 + - drivers/staging/fsl_ppfe/include/pfe/util/eape.h | 57 + - drivers/staging/fsl_ppfe/include/pfe/util/efet.h | 119 + - drivers/staging/fsl_ppfe/include/pfe/util/inq.h | 28 + - drivers/staging/fsl_ppfe/pfe_ctrl.c | 363 +++ - drivers/staging/fsl_ppfe/pfe_ctrl.h | 111 + - drivers/staging/fsl_ppfe/pfe_ctrl_hal.c | 207 ++ - drivers/staging/fsl_ppfe/pfe_ctrl_hal.h | 129 + - drivers/staging/fsl_ppfe/pfe_debugfs.c | 109 + - drivers/staging/fsl_ppfe/pfe_debugfs.h | 8 + - drivers/staging/fsl_ppfe/pfe_eth.c | 2956 ++++++++++++++++++++ - drivers/staging/fsl_ppfe/pfe_eth.h | 384 +++ - drivers/staging/fsl_ppfe/pfe_firmware.c | 322 +++ - drivers/staging/fsl_ppfe/pfe_firmware.h | 41 + - drivers/staging/fsl_ppfe/pfe_hal.c | 2217 +++++++++++++++ - drivers/staging/fsl_ppfe/pfe_hif.c | 939 +++++++ - drivers/staging/fsl_ppfe/pfe_hif.h | 322 +++ - drivers/staging/fsl_ppfe/pfe_hif_lib.c | 658 +++++ - drivers/staging/fsl_ppfe/pfe_hif_lib.h | 219 ++ - drivers/staging/fsl_ppfe/pfe_hw.c | 188 ++ - drivers/staging/fsl_ppfe/pfe_hw.h | 32 + - drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c | 341 +++ - drivers/staging/fsl_ppfe/pfe_mod.c | 140 + - drivers/staging/fsl_ppfe/pfe_mod.h | 163 ++ - drivers/staging/fsl_ppfe/pfe_perfmon.c | 175 ++ - drivers/staging/fsl_ppfe/pfe_perfmon.h | 41 + - drivers/staging/fsl_ppfe/pfe_platform.c | 358 +++ - drivers/staging/fsl_ppfe/pfe_sysfs.c | 855 ++++++ - drivers/staging/fsl_ppfe/pfe_sysfs.h | 34 + - drivers/staging/fsl_ppfe/platform.h | 25 + - include/linux/skbuff.h | 11 + - net/core/skbuff.c | 84 + - 63 files changed, 14821 insertions(+) - create mode 100644 drivers/staging/fsl_ppfe/Kconfig - create mode 100644 drivers/staging/fsl_ppfe/Makefile - create mode 100644 drivers/staging/fsl_ppfe/config.h - create mode 100644 drivers/staging/fsl_ppfe/control_link.lds - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/emac.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/gpt.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/class.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/class/ccu.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/class/efet.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/class/mac_hash.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/class/perg.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/class/vlan_hash.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/gpt.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/pe.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/pfe.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/tmu.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/tmu/phy_queue.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/tmu/sched.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/tmu/shaper.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/uart.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/util.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/util/eape.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/util/efet.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/util/inq.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl_hal.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl_hal.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_hal.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_perfmon.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_perfmon.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_platform.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.h - create mode 100644 drivers/staging/fsl_ppfe/platform.h - ---- a/drivers/staging/Kconfig -+++ b/drivers/staging/Kconfig -@@ -112,4 +112,6 @@ source "drivers/staging/wilc1000/Kconfig - - source "drivers/staging/most/Kconfig" - -+source "drivers/staging/fsl_ppfe/Kconfig" -+ - endif # STAGING ---- a/drivers/staging/Makefile -+++ b/drivers/staging/Makefile -@@ -48,3 +48,4 @@ obj-$(CONFIG_FSL_MC_BUS) += fsl-mc/ - obj-$(CONFIG_FSL_DPA) += fsl_qbman/ - obj-$(CONFIG_WILC1000) += wilc1000/ - obj-$(CONFIG_MOST) += most/ -+obj-$(CONFIG_FSL_PPFE) += fsl_ppfe/ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/Kconfig -@@ -0,0 +1,5 @@ -+config FSL_PPFE -+ tristate "Freescale PPFE Driver" -+ default m -+ help -+ only compiled as module ! ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/Makefile -@@ -0,0 +1,44 @@ -+# -+# Copyright (C) 2007 Freescale Semiconductor, Inc. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 2 of the License, or -+# (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ -+ -+all: modules -+ -+modules clean: -+ make CROSS_COMPILE=$(CROSS_COMPILE) ARCH=$(ARCH) -C $(KERNELDIR) M=`pwd` $@ -+ -+EXTRA_CFLAGS += -I$(src)/include -I$(src) -DCOMCERTO_2000 -DCONFIG_PLATFORM_LS1012A -DGEMAC_MTIP -DCONFIG_UTIL_DISABLED -+ -+EXTRA_LDFLAGS += -T$(srctree)/$(src)/control_link.lds -+ -+#only compiled as module ! -+obj-$(CONFIG_FSL_PPFE) += pfe.o -+ -+pfe-y += pfe_mod.o \ -+ pfe_hw.o \ -+ pfe_firmware.o \ -+ pfe_ctrl.o \ -+ pfe_ctrl_hal.o \ -+ pfe_hif.o \ -+ pfe_hif_lib.o\ -+ pfe_eth.o \ -+ pfe_perfmon.o \ -+ pfe_sysfs.o \ -+ pfe_debugfs.o \ -+ pfe_ls1012a_platform.o \ -+ pfe_hal.o \ -+ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/config.h -@@ -0,0 +1,8 @@ -+#ifndef _CONFIG_H_ -+#define _CONFIG_H_ -+#define CFG_WIFI_OFFLOAD (1 << 1) -+#define CFG_ICC (1 << 11) -+#define CFG_RTP (1 << 14) -+#define CFG_ELLIPTIC (1 << 15) -+#define CFG_ALL (0 | CFG_WIFI_OFFLOAD | CFG_ICC | CFG_RTP | CFG_ELLIPTIC ) -+#endif /* _CONFIG_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/control_link.lds -@@ -0,0 +1,32 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+SECTIONS -+{ -+ .class_dmem_sh : SUBALIGN(8) { -+ __class_dmem_sh = .; -+ *(SORT(.class_dmem_sh_*)) -+ } -+ -+ .tmu_dmem_sh : SUBALIGN(8) { -+ __tmu_dmem_sh = .; -+ *(SORT(.tmu_dmem_sh_*)) -+ } -+ -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus.h -@@ -0,0 +1,88 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _CBUS_H_ -+#define _CBUS_H_ -+ -+#define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000) -+#define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000) -+#define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000) -+#define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000) -+#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000) -+#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000) -+#define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000) /* FIXME not documented */ -+#define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000) /* FIXME not documented */ -+#define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000) -+#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000) -+#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000) -+#define LMEM_SIZE 0x10000 -+#define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE) -+#define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000) -+#define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000) -+#if defined(CONFIG_PLATFORM_C2000) -+#define EMAC3_BASE_ADDR (CBUS_BASE_ADDR + 0x330000) -+#define EGPI3_BASE_ADDR (CBUS_BASE_ADDR + 0x340000) -+#endif -+#define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000) -+#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000) -+#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000) -+ -+#define IS_LMEM(addr, len) (((unsigned long)(addr) >= (unsigned long)LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= (unsigned long)LMEM_END)) -+ -+/** -+* \defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR -+* XXX_MEM_ACCESS_ADDR register bit definitions. -+* @{ -+*/ -+#define PE_MEM_ACCESS_WRITE (1<<31) /**< Internal Memory Write. */ -+#define PE_MEM_ACCESS_IMEM (1<<15) -+#define PE_MEM_ACCESS_DMEM (1<<16) -+#define PE_MEM_ACCESS_BYTE_ENABLE(offset,size) (((((1 << (size)) - 1) << (4 - (offset) - (size))) & 0xf) << 24) /**< Byte Enables of the Internal memory access. These are interpred in BE */ -+// @} -+#if defined(CONFIG_PLATFORM_LS1012A) -+#include "cbus/emac_mtip.h" -+#else -+#include "cbus/emac.h" -+#endif //CONFIG_PLATFORM_LS1012A -+#include "cbus/gpi.h" -+#include "cbus/bmu.h" -+#include "cbus/hif.h" -+#include "cbus/tmu_csr.h" -+#include "cbus/class_csr.h" -+#include "cbus/hif_nocpy.h" -+#include "cbus/util_csr.h" -+#include "cbus/gpt.h" -+ -+ -+/* PFE cores states */ -+#define CORE_DISABLE 0x00000000 -+#define CORE_ENABLE 0x00000001 -+#define CORE_SW_RESET 0x00000002 -+ -+/* LMEM defines */ -+#define LMEM_HDR_SIZE 0x0010 -+#define LMEM_BUF_SIZE_LN2 0x7 -+#define LMEM_BUF_SIZE (1 << LMEM_BUF_SIZE_LN2) -+ -+/* DDR defines */ -+#define DDR_HDR_SIZE 0x0100 -+#define DDR_BUF_SIZE_LN2 0xb -+#define DDR_BUF_SIZE (1 << DDR_BUF_SIZE_LN2) -+ -+ -+#endif /* _CBUS_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _BMU_H_ -+#define _BMU_H_ -+ -+#define BMU_VERSION 0x000 -+#define BMU_CTRL 0x004 -+#define BMU_UCAST_CONFIG 0x008 -+#define BMU_UCAST_BASE_ADDR 0x00c -+#define BMU_BUF_SIZE 0x010 -+#define BMU_BUF_CNT 0x014 -+#define BMU_THRES 0x018 -+#define BMU_INT_SRC 0x020 -+#define BMU_INT_ENABLE 0x024 -+#define BMU_ALLOC_CTRL 0x030 -+#define BMU_FREE_CTRL 0x034 -+#define BMU_FREE_ERR_ADDR 0x038 -+#define BMU_CURR_BUF_CNT 0x03c -+#define BMU_MCAST_CNT 0x040 -+#define BMU_MCAST_ALLOC_CTRL 0x044 -+#define BMU_REM_BUF_CNT 0x048 -+#define BMU_LOW_WATERMARK 0x050 -+#define BMU_HIGH_WATERMARK 0x054 -+#define BMU_INT_MEM_ACCESS 0x100 -+ -+typedef struct { -+ unsigned long baseaddr; -+ u32 count; -+ u32 size; -+} BMU_CFG; -+ -+ -+#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2 -+#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2 -+ -+#define BMU2_MCAST_ALLOC_CTRL BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL -+ -+#endif /* _BMU_H_ */ -+ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h -@@ -0,0 +1,242 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _CLASS_CSR_H_ -+#define _CLASS_CSR_H_ -+ -+/** @file class_csr.h. -+ * class_csr - block containing all the classifier control and status register. Mapped on CBUS and accessible from all PE's and ARM. -+ */ -+ -+ -+#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000) -+#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004) -+#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010) -+#define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014) /**< (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */ -+#define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f) /**< LMEM header size for the Classifier block.\ Data in the LMEM is written from this offset. */ -+#define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16) /**< DDR header size for the Classifier block.\ Data in the DDR is written from this offset. */ -+ -+#define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020) /**< DMEM address of first [15:0] and second [31:16] buffers on QB side. */ -+#define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024) /**< DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */ -+ -+#define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060) /**< DMEM address of first [15:0] and second [31:16] buffers on RO side. */ -+#define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064) /**< DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */ -+ -+/** @name Class PE memory access. Allows external PE's and HOST to read/write PMEM/DMEM memory ranges for each classifier PE. -+ */ -+//@{ -+#define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100) /**< {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]}, See \ref XXX_MEM_ACCESS_ADDR for details. */ -+#define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104) /**< Internal Memory Access Write Data [31:0] */ -+#define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108) /**< Internal Memory Access Read Data [31:0] */ -+//@} -+#define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114) -+#define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118) -+ -+#define CLASS_PHY1_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x11c) -+#define CLASS_PHY1_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x120) -+#define CLASS_PHY1_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x124) -+#define CLASS_PHY1_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x128) -+#define CLASS_PHY1_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x12c) -+#define CLASS_PHY1_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x130) -+#define CLASS_PHY1_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x134) -+#define CLASS_PHY1_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x138) -+#define CLASS_PHY1_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x13c) -+#define CLASS_PHY1_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x140) -+#define CLASS_PHY2_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x144) -+#define CLASS_PHY2_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x148) -+#define CLASS_PHY2_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x14c) -+#define CLASS_PHY2_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x150) -+#define CLASS_PHY2_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x154) -+#define CLASS_PHY2_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x158) -+#define CLASS_PHY2_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x15c) -+#define CLASS_PHY2_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x160) -+#define CLASS_PHY2_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x164) -+#define CLASS_PHY2_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x168) -+#define CLASS_PHY3_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x16c) -+#define CLASS_PHY3_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x170) -+#define CLASS_PHY3_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x174) -+#define CLASS_PHY3_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x178) -+#define CLASS_PHY3_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x17c) -+#define CLASS_PHY3_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x180) -+#define CLASS_PHY3_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x184) -+#define CLASS_PHY3_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x188) -+#define CLASS_PHY3_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x18c) -+#define CLASS_PHY3_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x190) -+#define CLASS_PHY1_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x194) -+#define CLASS_PHY1_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x198) -+#define CLASS_PHY1_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x19c) -+#define CLASS_PHY1_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a0) -+#define CLASS_PHY2_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a4) -+#define CLASS_PHY2_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a8) -+#define CLASS_PHY2_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1ac) -+#define CLASS_PHY2_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b0) -+#define CLASS_PHY3_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b4) -+#define CLASS_PHY3_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b8) -+#define CLASS_PHY3_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1bc) -+#define CLASS_PHY3_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c0) -+#define CLASS_PHY4_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c4) -+#define CLASS_PHY4_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c8) -+#define CLASS_PHY4_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1cc) -+#define CLASS_PHY4_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1d0) -+#define CLASS_PHY4_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d4) -+#define CLASS_PHY4_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d8) -+#define CLASS_PHY4_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1dc) -+#define CLASS_PHY4_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e0) -+#define CLASS_PHY4_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x1e4) -+#define CLASS_PHY4_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e8) -+#define CLASS_PHY4_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x1ec) -+#define CLASS_PHY4_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x1f0) -+#define CLASS_PHY4_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f4) -+#define CLASS_PHY4_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f8) -+ -+#define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200) -+#define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204) -+#define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208) -+#define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c) -+#define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210) -+#define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214) -+#define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218) -+#define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c) -+#define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220) -+#define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224) -+ -+#define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228) -+ -+#define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c) -+#define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230) -+ -+#define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234) /**< (route_entry_size[9:0], route_hash_size[23:16] (this is actually ln2(size))) */ -+#define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff) -+#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16) -+ -+#define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238) -+ -+#define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c) -+#define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240) -+#define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244) -+#define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248) -+#define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c) -+#define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250) -+#define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254) -+ -+#define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258) -+#define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000) //bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE -+ -+#define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c) -+ -+#define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260) -+#define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264) -+#define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268) -+#define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c) -+#define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270) -+#define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274) -+#define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278) -+#define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c) -+#define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280) -+#define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284) -+#define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288) -+#define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c) -+ -+#define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290) -+#define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294) -+ -+#define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298) -+#define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c) -+ -+#define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0) -+ -+#define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4) -+#define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8) -+#define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac) -+#define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0) -+#define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4) -+#define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8) -+ -+#define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc) -+ -+/* CLASS defines */ -+#define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */ -+#define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */ -+ -+#define CLASS_PBUF0_BASE_ADDR 0x000 /* Can be configured */ -+#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE) /* Can be configured */ -+#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE) /* Can be configured */ -+#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE) /* Can be configured */ -+ -+#define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET) -+#define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET) -+#define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET) -+#define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET) -+ -+#define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) | CLASS_PBUF0_BASE_ADDR) -+#define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) | CLASS_PBUF2_BASE_ADDR) -+ -+#define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16) | CLASS_PBUF0_HEADER_BASE_ADDR) -+#define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16) | CLASS_PBUF2_HEADER_BASE_ADDR) -+ -+#define CLASS_ROUTE_SIZE 128 -+#define CLASS_MAX_ROUTE_SIZE 256 -+#define CLASS_ROUTE_HASH_BITS 20 -+#define CLASS_ROUTE_HASH_MASK ((1 << CLASS_ROUTE_HASH_BITS) - 1) -+ -+#define CLASS_ROUTE0_BASE_ADDR 0x400 /* Can be configured */ -+#define CLASS_ROUTE1_BASE_ADDR (CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE) /* Can be configured */ -+#define CLASS_ROUTE2_BASE_ADDR (CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE) /* Can be configured */ -+#define CLASS_ROUTE3_BASE_ADDR (CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE) /* Can be configured */ -+ -+#define CLASS_SA_SIZE 128 -+#define CLASS_IPSEC_SA0_BASE_ADDR 0x600 -+#define CLASS_IPSEC_SA1_BASE_ADDR (CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE) /* not used */ -+#define CLASS_IPSEC_SA2_BASE_ADDR (CLASS_IPSEC_SA1_BASE_ADDR + CLASS_SA_SIZE) /* not used */ -+#define CLASS_IPSEC_SA3_BASE_ADDR (CLASS_IPSEC_SA2_BASE_ADDR + CLASS_SA_SIZE) /* not used */ -+ -+/* generic purpose free dmem buffer, last portion of 2K dmem pbuf */ -+#define CLASS_GP_DMEM_BUF_SIZE (2048 - (CLASS_PBUF_SIZE*4) - (CLASS_ROUTE_SIZE*4) - (CLASS_SA_SIZE)) -+#define CLASS_GP_DMEM_BUF ((void *)(CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE)) -+ -+ -+#define TWO_LEVEL_ROUTE (1 << 0) -+#define PHYNO_IN_HASH (1 << 1) -+#define HW_ROUTE_FETCH (1 << 3) -+#define HW_BRIDGE_FETCH (1 << 5) -+#define IP_ALIGNED (1 << 6) -+#define ARC_HIT_CHECK_EN (1 << 7) -+#define CLASS_TOE (1 << 11) -+#define HASH_NORMAL (0 << 12) -+#define HASH_CRC_PORT (1 << 12) -+#define HASH_CRC_IP (2 << 12) -+#define HASH_CRC_PORT_IP (3 << 12) -+#define QB2BUS_LE (1 << 15) -+ -+#define TCP_CHKSUM_DROP (1 << 0) -+#define UDP_CHKSUM_DROP (1 << 1) -+#define IPV4_CHKSUM_DROP (1 << 9) -+ -+/*CLASS_HIF_PARSE bits*/ -+#define HIF_PKT_CLASS_EN (1 << 0) -+#define HIF_PKT_OFFSET(ofst) ((ofst&0xF) << 1) -+ -+typedef struct { -+ u32 toe_mode; -+ unsigned long route_table_baseaddr; -+ u32 route_table_hash_bits; -+ u32 pe_sys_clk_ratio; -+ u32 resume; -+} CLASS_CFG; -+ -+#endif /* _CLASS_CSR_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/emac.h -@@ -0,0 +1,243 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _EMAC_H_ -+#define _EMAC_H_ -+ -+#define EMAC_NETWORK_CONTROL 0x000 -+#define EMAC_NETWORK_CONFIG 0x004 -+#define EMAC_NETWORK_STATUS 0x008 -+#define EMAC_DMA_CONFIG 0x010 -+ -+#define EMAC_PHY_MANAGEMENT 0x034 -+ -+#define EMAC_HASH_BOT 0x080 -+#define EMAC_HASH_TOP 0x084 -+ -+#define EMAC_SPEC1_ADD_BOT 0x088 -+#define EMAC_SPEC1_ADD_TOP 0x08c -+#define EMAC_SPEC2_ADD_BOT 0x090 -+#define EMAC_SPEC2_ADD_TOP 0x094 -+#define EMAC_SPEC3_ADD_BOT 0x098 -+#define EMAC_SPEC3_ADD_TOP 0x09c -+#define EMAC_SPEC4_ADD_BOT 0x0a0 -+#define EMAC_SPEC4_ADD_TOP 0x0a4 -+#define EMAC_WOL 0x0b8 -+ -+#define EMAC_STACKED_VLAN_REG 0x0c0 -+ -+#define EMAC_SPEC1_ADD_MASK_BOT 0x0c8 -+#define EMAC_SPEC1_ADD_MASK_TOP 0x0cc -+ -+#define EMAC_RMON_BASE_OFST 0x100 -+ -+#define EMAC_SPEC5_ADD_BOT 0x300 -+#define EMAC_SPEC5_ADD_TOP 0x304 -+#define EMAC_SPEC6_ADD_BOT 0x308 -+#define EMAC_SPEC6_ADD_TOP 0x30c -+#define EMAC_SPEC7_ADD_BOT 0x310 -+#define EMAC_SPEC7_ADD_TOP 0x314 -+#define EMAC_SPEC8_ADD_BOT 0x318 -+#define EMAC_SPEC8_ADD_TOP 0x31c -+#define EMAC_SPEC9_ADD_BOT 0x320 -+#define EMAC_SPEC9_ADD_TOP 0x324 -+#define EMAC_SPEC10_ADD_BOT 0x328 -+#define EMAC_SPEC10_ADD_TOP 0x32c -+#define EMAC_SPEC11_ADD_BOT 0x330 -+#define EMAC_SPEC11_ADD_TOP 0x334 -+#define EMAC_SPEC12_ADD_BOT 0x338 -+#define EMAC_SPEC12_ADD_TOP 0x33c -+#define EMAC_SPEC13_ADD_BOT 0x340 -+#define EMAC_SPEC13_ADD_TOP 0x344 -+#define EMAC_SPEC14_ADD_BOT 0x348 -+#define EMAC_SPEC14_ADD_TOP 0x34c -+#define EMAC_SPEC15_ADD_BOT 0x350 -+#define EMAC_SPEC15_ADD_TOP 0x354 -+#define EMAC_SPEC16_ADD_BOT 0x358 -+#define EMAC_SPEC16_ADD_TOP 0x35c -+#define EMAC_SPEC17_ADD_BOT 0x360 -+#define EMAC_SPEC17_ADD_TOP 0x364 -+#define EMAC_SPEC18_ADD_BOT 0x368 -+#define EMAC_SPEC18_ADD_TOP 0x36c -+#define EMAC_SPEC19_ADD_BOT 0x370 -+#define EMAC_SPEC19_ADD_TOP 0x374 -+#define EMAC_SPEC20_ADD_BOT 0x378 -+#define EMAC_SPEC20_ADD_TOP 0x37c -+#define EMAC_SPEC21_ADD_BOT 0x380 -+#define EMAC_SPEC21_ADD_TOP 0x384 -+#define EMAC_SPEC22_ADD_BOT 0x388 -+#define EMAC_SPEC22_ADD_TOP 0x38c -+#define EMAC_SPEC23_ADD_BOT 0x390 -+#define EMAC_SPEC23_ADD_TOP 0x394 -+#define EMAC_SPEC24_ADD_BOT 0x398 -+#define EMAC_SPEC24_ADD_TOP 0x39c -+#define EMAC_SPEC25_ADD_BOT 0x3a0 -+#define EMAC_SPEC25_ADD_TOP 0x3a4 -+#define EMAC_SPEC26_ADD_BOT 0x3a8 -+#define EMAC_SPEC26_ADD_TOP 0x3ac -+#define EMAC_SPEC27_ADD_BOT 0x3b0 -+#define EMAC_SPEC27_ADD_TOP 0x3b4 -+#define EMAC_SPEC28_ADD_BOT 0x3b8 -+#define EMAC_SPEC28_ADD_TOP 0x3bc -+#define EMAC_SPEC29_ADD_BOT 0x3c0 -+#define EMAC_SPEC29_ADD_TOP 0x3c4 -+#define EMAC_SPEC30_ADD_BOT 0x3c8 -+#define EMAC_SPEC30_ADD_TOP 0x3cc -+#define EMAC_SPEC31_ADD_BOT 0x3d0 -+#define EMAC_SPEC31_ADD_TOP 0x3d4 -+#define EMAC_SPEC32_ADD_BOT 0x3d8 -+#define EMAC_SPEC32_ADD_TOP 0x3dc -+ -+#define EMAC_SPEC_ADDR_MAX 32 -+ -+#define EMAC_CONTROL 0x7a0 -+ -+/* GEMAC definitions and settings */ -+ -+#define EMAC_PORT_0 0 -+#define EMAC_PORT_1 1 -+#define EMAC_PORT_2 2 -+ -+/* The possible operating speeds of the MAC, currently supporting 10, 100 and -+ * 1000Mb modes. -+ */ -+typedef enum {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS} MAC_SPEED; -+ -+#define GMII 1 -+#define MII 2 -+#define RMII 3 -+#define RGMII 4 -+#define SGMII 5 -+ -+#define DUP_HALF 0x00 -+#define DUP_FULL 0x01 -+ -+/* EMAC_NETWORK_CONTROL bits definition */ -+#define EMAC_LB_PHY (1 << 0) -+#define EMAC_LB_MAC (1 << 1) -+#define EMAC_RX_ENABLE (1 << 2) -+#define EMAC_TX_ENABLE (1 << 3) -+#define EMAC_MDIO_EN (1 << 4) /* Enable MDIO port */ -+ -+/* WoL (Wake on Lan bit definition) */ -+#define EMAC_WOL_MAGIC (1 << 16) -+#define EMAC_WOL_ARP (1 << 17) -+#define EMAC_WOL_SPEC_ADDR (1 << 18) -+#define EMAC_WOL_MULTI (1 << 19) -+ -+/* EMAC_NETWORK_CONFIG bits definition */ -+#define EMAC_SPEED_100 (1 << 0) -+#define EMAC_HALF_DUP (0 << 1) -+#define EMAC_FULL_DUP (1 << 1) -+#define EMAC_DUPLEX_MASK (1 << 1) -+#define EMAC_ENABLE_JUMBO_FRAME (1 << 3) -+#define EMAC_ENABLE_COPY_ALL (1 << 4) -+#define EMAC_NO_BROADCAST (1 << 5) -+#define EMAC_ENABLE_MULTICAST (1 << 6) -+#define EMAC_ENABLE_UNICAST (1 << 7) -+#define EMAC_ENABLE_1536_RX (1 << 8) -+#define EMAC_SPEED_1000 (1 << 10) -+#define EMAC_PCS_ENABLE (1 << 11) -+#define EMAC_ENABLE_PAUSE_RX (1 << 13) -+#define EMAC_REMOVE_FCS (1 << 17) -+#define EMAC_ENABLE_CHKSUM_RX (1 << 24) -+#define EMAC_MDC_DIV_MASK (0x7 << 18) /* PCLK divisor for MDC */ -+#define EMAC_DATA_BUS_WIDTH_SHIFT 21 -+#define EMAC_DATA_BUS_WIDTH_MASK (0x3 << EMAC_DATA_BUS_WIDTH_SHIFT) -+#define EMAC_DATA_BUS_WIDTH_32 (0x00 << EMAC_DATA_BUS_WIDTH_SHIFT) -+#define EMAC_DATA_BUS_WIDTH_64 (0x01 << EMAC_DATA_BUS_WIDTH_SHIFT) -+#define EMAC_DATA_BUS_WIDTH_128 (0x10 << EMAC_DATA_BUS_WIDTH_SHIFT) -+#define EMAC_ENABLE_FCS_RX (1 << 26) -+#define EMAC_SGMII_MODE_ENABLE (1 << 27) -+ -+#define EMAC_SPEED_MASK (EMAC_SPEED_100 | EMAC_SPEED_1000) -+ -+/* EMAC_STACKED_VLAN_REG bits definition */ -+#define EMAC_ENABLE_STACKED_VLAN (1 << 31) -+ -+/* EMAC_CONTROL bits definition */ -+#define EMAC_TWO_BYTES_IP_ALIGN (1 << 0) // two bytes IP alignement -+ -+/* EMAC_NET_STATUS bits definition */ -+#define EMAC_PHY_IDLE (1<<2) /* PHY management is idle */ -+#define EMAC_MDIO_IN (1<<1) /* Status of mdio_in pin */ -+#define EMAC_LINK_STATUS (1<<0) /* Status of link pin */ -+ -+/* EMAC_DMA_CONFIG Bit definitions */ -+#define EMAC_ENABLE_CHKSUM_TX (1<<11) -+ -+//RMII enable – bit 1 / RGMII enable – bit 2 -+#define EMAC_RMII_MODE_ENABLE ((1 << 1) | (0 << 2)) -+#define EMAC_RMII_MODE_DISABLE (0 << 1) -+#define EMAC_RGMII_MODE_ENABLE ((0 << 1) | (1 << 2)) -+#define EMAC_RGMII_MODE_DISABLE (0 << 2) -+#define EMAC_MII_MODE_ENABLE (EMAC_RMII_MODE_DISABLE | EMAC_RGMII_MODE_DISABLE) -+#define EMAC_GMII_MODE_ENABLE (EMAC_RMII_MODE_DISABLE | EMAC_RGMII_MODE_DISABLE) -+#define EMAC_MODE_MASK (0x3 << 1) -+ -+/* Default configuration */ -+#define EMAC0_DEFAULT_DUPLEX_MODE FULLDUPLEX -+#define EMAC0_DEFAULT_EMAC_MODE RGMII -+#define EMAC0_DEFAULT_EMAC_SPEED SPEED_1000M -+ -+#define EMAC1_DEFAULT_DUPLEX_MODE FULLDUPLEX -+#define EMAC1_DEFAULT_EMAC_MODE RGMII -+#define EMAC1_DEFAULT_EMAC_SPEED SPEED_1000M -+ -+#define EMAC2_DEFAULT_DUPLEX_MODE FULLDUPLEX -+#define EMAC2_DEFAULT_EMAC_MODE RGMII -+#define EMAC2_DEFAULT_EMAC_SPEED SPEED_1000M -+ -+/* EMAC Hash size */ -+#define EMAC_HASH_REG_BITS 64 -+ -+/* The Address organisation for the MAC device. All addresses are split into -+ * two 32-bit register fields. The first one (bottom) is the lower 32-bits of -+ * the address and the other field are the high order bits - this may be 16-bits -+ * in the case of MAC addresses, or 32-bits for the hash address. -+ * In terms of memory storage, the first item (bottom) is assumed to be at a -+ * lower address location than 'top'. i.e. top should be at address location of -+ * 'bottom' + 4 bytes. -+ */ -+typedef struct { -+ u32 bottom; /* Lower 32-bits of address. */ -+ u32 top; /* Upper 32-bits of address. */ -+} MAC_ADDR; -+ -+ -+/* The following is the organisation of the address filters section of the MAC -+ * registers. The Cadence MAC contains four possible specific address match -+ * addresses, if an incoming frame corresponds to any one of these four -+ * addresses then the frame will be copied to memory. -+ * It is not necessary for all four of the address match registers to be -+ * programmed, this is application dependant. -+ */ -+typedef struct { -+ MAC_ADDR one; /* Specific address register 1. */ -+ MAC_ADDR two; /* Specific address register 2. */ -+ MAC_ADDR three; /* Specific address register 3. */ -+ MAC_ADDR four; /* Specific address register 4. */ -+} SPEC_ADDR; -+ -+typedef struct { -+ u32 mode; -+ u32 speed; -+ u32 duplex; -+} GEMAC_CFG; -+ -+#endif /* _EMAC_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h -@@ -0,0 +1,250 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _EMAC_H_ -+#define _EMAC_H_ -+ -+#define EMAC_IEVENT_REG 0x004 -+#define EMAC_IMASK_REG 0x008 -+#define EMAC_R_DES_ACTIVE_REG 0x010 -+#define EMAC_X_DES_ACTIVE_REG 0x014 -+#define EMAC_ECNTRL_REG 0x024 -+#define EMAC_MII_DATA_REG 0x040 -+#define EMAC_MII_CTRL_REG 0x044 -+#define EMAC_MIB_CTRL_STS_REG 0x064 -+#define EMAC_RCNTRL_REG 0x084 -+#define EMAC_TCNTRL_REG 0x0C4 -+#define EMAC_PHY_ADDR_LOW 0x0E4 -+#define EMAC_PHY_ADDR_HIGH 0x0E8 -+#define EMAC_GAUR 0x120 -+#define EMAC_GALR 0x124 -+#define EMAC_TFWR_STR_FWD 0x144 -+#define EMAC_RX_SECTIOM_FULL 0x190 -+#define EMAC_TX_SECTION_EMPTY 0x1A0 -+#define EMAC_TRUNC_FL 0x1B0 -+ -+#define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */ -+#define RMON_T_PACKETS 0x204 /* RMON TX packet count */ -+#define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */ -+#define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */ -+#define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */ -+#define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */ -+#define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */ -+#define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */ -+#define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */ -+#define RMON_T_COL 0x224 /* RMON TX collision count */ -+#define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */ -+#define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */ -+#define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */ -+#define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */ -+#define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */ -+#define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */ -+#define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */ -+#define RMON_T_OCTETS 0x244 /* RMON TX octets */ -+#define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */ -+#define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */ -+#define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */ -+#define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */ -+#define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */ -+#define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */ -+#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */ -+#define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */ -+#define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */ -+#define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */ -+#define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */ -+#define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */ -+#define RMON_R_PACKETS 0x284 /* RMON RX packet count */ -+#define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */ -+#define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */ -+#define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */ -+#define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */ -+#define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */ -+#define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */ -+#define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */ -+#define RMON_R_RESVD_O 0x2a4 /* Reserved */ -+#define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */ -+#define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */ -+#define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */ -+#define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */ -+#define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */ -+#define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */ -+#define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */ -+#define RMON_R_OCTETS 0x2c4 /* RMON RX octets */ -+#define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */ -+#define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */ -+#define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */ -+#define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */ -+#define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */ -+#define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */ -+#define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */ -+ -+#define EMAC_SMAC_0_0 0x500 /*Supplemental MAC Address 0 (RW).*/ -+#define EMAC_SMAC_0_1 0x504 /*Supplemental MAC Address 0 (RW).*/ -+ -+/* GEMAC definitions and settings */ -+ -+#define EMAC_PORT_0 0 -+#define EMAC_PORT_1 1 -+ -+/* GEMAC Bit definitions */ -+#define EMAC_IEVENT_HBERR 0x80000000 -+#define EMAC_IEVENT_BABR 0x40000000 -+#define EMAC_IEVENT_BABT 0x20000000 -+#define EMAC_IEVENT_GRA 0x10000000 -+#define EMAC_IEVENT_TXF 0x08000000 -+#define EMAC_IEVENT_TXB 0x04000000 -+#define EMAC_IEVENT_RXF 0x02000000 -+#define EMAC_IEVENT_RXB 0x01000000 -+#define EMAC_IEVENT_MII 0x00800000 -+#define EMAC_IEVENT_EBERR 0x00400000 -+#define EMAC_IEVENT_LC 0x00200000 -+#define EMAC_IEVENT_RL 0x00100000 -+#define EMAC_IEVENT_UN 0x00080000 -+ -+#define EMAC_IMASK_HBERR 0x80000000 -+#define EMAC_IMASK_BABR 0x40000000 -+#define EMAC_IMASKT_BABT 0x20000000 -+#define EMAC_IMASK_GRA 0x10000000 -+#define EMAC_IMASKT_TXF 0x08000000 -+#define EMAC_IMASK_TXB 0x04000000 -+#define EMAC_IMASKT_RXF 0x02000000 -+#define EMAC_IMASK_RXB 0x01000000 -+#define EMAC_IMASK_MII 0x00800000 -+#define EMAC_IMASK_EBERR 0x00400000 -+#define EMAC_IMASK_LC 0x00200000 -+#define EMAC_IMASKT_RL 0x00100000 -+#define EMAC_IMASK_UN 0x00080000 -+ -+#define EMAC_RCNTRL_MAX_FL_SHIFT 16 -+#define EMAC_RCNTRL_LOOP 0x00000001 -+#define EMAC_RCNTRL_DRT 0x00000002 -+#define EMAC_RCNTRL_MII_MODE 0x00000004 -+#define EMAC_RCNTRL_PROM 0x00000008 -+#define EMAC_RCNTRL_BC_REJ 0x00000010 -+#define EMAC_RCNTRL_FCE 0x00000020 -+#define EMAC_RCNTRL_RGMII 0x00000040 -+#define EMAC_RCNTRL_SGMII 0x00000080 -+#define EMAC_RCNTRL_RMII 0x00000100 -+#define EMAC_RCNTRL_RMII_10T 0x00000200 -+#define EMAC_RCNTRL_CRC_FWD 0x00004000 -+ -+#define EMAC_TCNTRL_GTS 0x00000001 -+#define EMAC_TCNTRL_HBC 0x00000002 -+#define EMAC_TCNTRL_FDEN 0x00000004 -+#define EMAC_TCNTRL_TFC_PAUSE 0x00000008 -+#define EMAC_TCNTRL_RFC_PAUSE 0x00000010 -+ -+#define EMAC_ECNTRL_RESET 0x00000001 /* reset the EMAC */ -+#define EMAC_ECNTRL_ETHER_EN 0x00000002 /* enable the EMAC */ -+#define EMAC_ECNTRL_SPEED 0x00000020 -+#define EMAC_ECNTRL_DBSWAP 0x00000100 -+ -+#define EMAC_X_WMRK_STRFWD 0x00000100 -+ -+#define EMAC_X_DES_ACTIVE_TDAR 0x01000000 -+#define EMAC_R_DES_ACTIVE_RDAR 0x01000000 -+ -+ -+ -+/* The possible operating speeds of the MAC, currently supporting 10, 100 and -+ * 1000Mb modes. -+ */ -+typedef enum {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS} MAC_SPEED; -+ -+#define GMII 1 -+#define MII 2 -+#define RMII 3 -+#define RGMII 4 -+#define SGMII 5 -+ -+#define DUPLEX_HALF 0x00 -+#define DUPLEX_FULL 0x01 -+ -+ -+/* Default configuration */ -+#define EMAC0_DEFAULT_DUPLEX_MODE FULLDUPLEX -+#define EMAC0_DEFAULT_EMAC_MODE RGMII -+#define EMAC0_DEFAULT_EMAC_SPEED SPEED_1000M -+ -+#define EMAC1_DEFAULT_DUPLEX_MODE FULLDUPLEX -+#define EMAC1_DEFAULT_EMAC_MODE SGMII -+#define EMAC1_DEFAULT_EMAC_SPEED SPEED_1000M -+ -+/* MII-related definitios */ -+#define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ -+#define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ -+#define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ -+#define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ -+#define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ -+#define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */ -+#define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ -+ -+#define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ -+#define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */ -+#define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ -+#define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */ -+ -+#define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT) -+#define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_PA_SHIFT) -+#define EMAC_MII_DATA(v) (v & 0xffff) -+ -+#define EMAC_MII_SPEED_SHIFT 1 -+#define EMAC_HOLDTIME_SHIFT 8 -+#define EMAC_HOLDTIME_MASK 0x7 -+#define EMAC_HOLDTIME(v) ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT) -+ -+/* The Address organisation for the MAC device. All addresses are split into -+ * two 32-bit register fields. The first one (bottom) is the lower 32-bits of -+ * the address and the other field are the high order bits - this may be 16-bits -+ * in the case of MAC addresses, or 32-bits for the hash address. -+ * In terms of memory storage, the first item (bottom) is assumed to be at a -+ * lower address location than 'top'. i.e. top should be at address location of -+ * 'bottom' + 4 bytes. -+ */ -+typedef struct { -+ u32 bottom; /* Lower 32-bits of address. */ -+ u32 top; /* Upper 32-bits of address. */ -+} MAC_ADDR; -+ -+ -+/* The following is the organisation of the address filters section of the MAC -+ * registers. The Cadence MAC contains four possible specific address match -+ * addresses, if an incoming frame corresponds to any one of these four -+ * addresses then the frame will be copied to memory. -+ * It is not necessary for all four of the address match registers to be -+ * programmed, this is application dependant. -+ */ -+typedef struct { -+ MAC_ADDR one; /* Specific address register 1. */ -+ MAC_ADDR two; /* Specific address register 2. */ -+ MAC_ADDR three; /* Specific address register 3. */ -+ MAC_ADDR four; /* Specific address register 4. */ -+} SPEC_ADDR; -+ -+typedef struct { -+ u32 mode; -+ u32 speed; -+ u32 duplex; -+} GEMAC_CFG; -+ -+/* EMAC Hash size */ -+#define EMAC_HASH_REG_BITS 64 -+ -+#define EMAC_SPEC_ADDR_MAX 4 -+ -+#endif /* _EMAC_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h -@@ -0,0 +1,78 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _GPI_H_ -+#define _GPI_H_ -+ -+#define GPI_VERSION 0x00 -+#define GPI_CTRL 0x04 -+#define GPI_RX_CONFIG 0x08 -+#define GPI_HDR_SIZE 0x0c -+#define GPI_BUF_SIZE 0x10 -+#define GPI_LMEM_ALLOC_ADDR 0x14 -+#define GPI_LMEM_FREE_ADDR 0x18 -+#define GPI_DDR_ALLOC_ADDR 0x1c -+#define GPI_DDR_FREE_ADDR 0x20 -+#define GPI_CLASS_ADDR 0x24 -+#define GPI_DRX_FIFO 0x28 -+#define GPI_TRX_FIFO 0x2c -+#define GPI_INQ_PKTPTR 0x30 -+#define GPI_DDR_DATA_OFFSET 0x34 -+#define GPI_LMEM_DATA_OFFSET 0x38 -+#define GPI_TMLF_TX 0x4c -+#define GPI_DTX_ASEQ 0x50 -+#define GPI_FIFO_STATUS 0x54 -+#define GPI_FIFO_DEBUG 0x58 -+#define GPI_TX_PAUSE_TIME 0x5c -+#define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60 -+#define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64 -+#define GPI_TOE_CHKSUM_EN 0x68 -+#define GPI_OVERRUN_DROPCNT 0x6c -+ -+typedef struct { -+ u32 lmem_rtry_cnt; -+ u32 tmlf_txthres; -+ u32 aseq_len; -+} GPI_CFG; -+ -+ -+/* GPI commons defines */ -+#define GPI_LMEM_BUF_EN 0x1 -+#define GPI_DDR_BUF_EN 0x1 -+ -+/* EGPI 1 defines */ -+#define EGPI1_LMEM_RTRY_CNT 0x40 -+#define EGPI1_TMLF_TXTHRES 0xBC -+#define EGPI1_ASEQ_LEN 0x50 -+ -+/* EGPI 2 defines */ -+#define EGPI2_LMEM_RTRY_CNT 0x40 -+#define EGPI2_TMLF_TXTHRES 0xBC -+#define EGPI2_ASEQ_LEN 0x40 -+ -+/* EGPI 3 defines */ -+#define EGPI3_LMEM_RTRY_CNT 0x40 -+#define EGPI3_TMLF_TXTHRES 0xBC -+#define EGPI3_ASEQ_LEN 0x40 -+ -+/* HGPI defines */ -+#define HGPI_LMEM_RTRY_CNT 0x40 -+#define HGPI_TMLF_TXTHRES 0xBC -+#define HGPI_ASEQ_LEN 0x40 -+ -+#endif /* _GPI_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/gpt.h -@@ -0,0 +1,29 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _CBUS_GPT_H_ -+#define _CBUS_GPT_H_ -+ -+#define CBUS_GPT_VERSION (CBUS_GPT_BASE_ADDR + 0x00) -+#define CBUS_GPT_STATUS (CBUS_GPT_BASE_ADDR + 0x04) -+#define CBUS_GPT_CONFIG (CBUS_GPT_BASE_ADDR + 0x08) -+#define CBUS_GPT_COUNTER (CBUS_GPT_BASE_ADDR + 0x0c) -+#define CBUS_GPT_PERIOD (CBUS_GPT_BASE_ADDR + 0x10) -+#define CBUS_GPT_WIDTH (CBUS_GPT_BASE_ADDR + 0x14) -+ -+#endif /* _CBUS_GPT_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h -@@ -0,0 +1,96 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _HIF_H_ -+#define _HIF_H_ -+ -+/** @file hif.h. -+ * hif - PFE hif block control and status register. Mapped on CBUS and accessible from all PE's and ARM. -+ */ -+#define HIF_VERSION (HIF_BASE_ADDR + 0x00) -+#define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04) -+#define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08) -+#define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c) -+#define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10) -+#define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14) -+#define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20) -+#define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24) -+#define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30) -+#define HIF_INT_SRC (HIF_BASE_ADDR + 0x34) -+#define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38) -+#define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c) -+#define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40) -+#define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44) -+#define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48) -+#define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c) -+#define HIF_INT_COAL (HIF_BASE_ADDR + 0x50) -+ -+/*HIF_INT_SRC/ HIF_INT_ENABLE control bits */ -+#define HIF_INT (1 << 0) -+#define HIF_RXBD_INT (1 << 1) -+#define HIF_RXPKT_INT (1 << 2) -+#define HIF_TXBD_INT (1 << 3) -+#define HIF_TXPKT_INT (1 << 4) -+ -+/*HIF_TX_CTRL bits */ -+#define HIF_CTRL_DMA_EN (1<<0) -+#define HIF_CTRL_BDP_POLL_CTRL_EN (1<<1) -+#define HIF_CTRL_BDP_CH_START_WSTB (1<<2) -+ -+/*HIF_INT_ENABLE bits */ -+#define HIF_INT_EN (1 << 0) -+#define HIF_RXBD_INT_EN (1 << 1) -+#define HIF_RXPKT_INT_EN (1 << 2) -+#define HIF_TXBD_INT_EN (1 << 3) -+#define HIF_TXPKT_INT_EN (1 << 4) -+ -+/*HIF_POLL_CTRL bits*/ -+#define HIF_RX_POLL_CTRL_CYCLE 0x0400 -+#define HIF_TX_POLL_CTRL_CYCLE 0x0400 -+ -+/*HIF_INT_COAL bits*/ -+#define HIF_INT_COAL_ENABLE (1 << 31) -+ -+/*Buffer descriptor control bits */ -+#define BD_CTRL_BUFLEN_MASK 0x3fff -+#define BD_BUF_LEN(x) (x & BD_CTRL_BUFLEN_MASK) -+#define BD_CTRL_CBD_INT_EN (1 << 16) -+#define BD_CTRL_PKT_INT_EN (1 << 17) -+#define BD_CTRL_LIFM (1 << 18) -+#define BD_CTRL_LAST_BD (1 << 19) -+#define BD_CTRL_DIR (1 << 20) -+#define BD_CTRL_LMEM_CPY (1 << 21) /*Valid only for HIF_NOCPY*/ -+#define BD_CTRL_PKT_XFER (1 << 24) -+#define BD_CTRL_DESC_EN (1 << 31) -+#define BD_CTRL_PARSE_DISABLE (1 << 25) -+#define BD_CTRL_BRFETCH_DISABLE (1 << 26) -+#define BD_CTRL_RTFETCH_DISABLE (1 << 27) -+ -+/*Buffer descriptor status bits*/ -+#define BD_STATUS_CONN_ID(x) ((x) & 0xffff) -+#define BD_STATUS_DIR_PROC_ID (1 << 16) -+#define BD_STATUS_CONN_ID_EN (1 << 17)) -+#define BD_STATUS_PE2PROC_ID(x) (((x) & 7) << 18) -+#define BD_STATUS_LE_DATA (1 << 21) -+#define BD_STATUS_CHKSUM_EN (1 << 22) -+ -+/*HIF Buffer descriptor status bits */ -+#define DIR_PROC_ID (1 << 16) -+#define PROC_ID(id) ((id) << 18) -+ -+#endif /* _HIF_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h -@@ -0,0 +1,51 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _HIF_NOCPY_H_ -+#define _HIF_NOCPY_H_ -+ -+#define HIF_NOCPY_VERSION (HIF_NOCPY_BASE_ADDR + 0x00) -+#define HIF_NOCPY_TX_CTRL (HIF_NOCPY_BASE_ADDR + 0x04) -+#define HIF_NOCPY_TX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x08) -+#define HIF_NOCPY_TX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x0c) -+#define HIF_NOCPY_TX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x10) -+#define HIF_NOCPY_TX_STATUS (HIF_NOCPY_BASE_ADDR + 0x14) -+#define HIF_NOCPY_RX_CTRL (HIF_NOCPY_BASE_ADDR + 0x20) -+#define HIF_NOCPY_RX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x24) -+#define HIF_NOCPY_RX_STATUS (HIF_NOCPY_BASE_ADDR + 0x30) -+#define HIF_NOCPY_INT_SRC (HIF_NOCPY_BASE_ADDR + 0x34) -+#define HIF_NOCPY_INT_ENABLE (HIF_NOCPY_BASE_ADDR + 0x38) -+#define HIF_NOCPY_POLL_CTRL (HIF_NOCPY_BASE_ADDR + 0x3c) -+#define HIF_NOCPY_RX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x40) -+#define HIF_NOCPY_RX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x44) -+#define HIF_NOCPY_TX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x48) -+#define HIF_NOCPY_RX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x4c) -+#define HIF_NOCPY_RX_INQ0_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x50) -+#define HIF_NOCPY_RX_INQ1_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x54) -+#define HIF_NOCPY_TX_PORT_NO (HIF_NOCPY_BASE_ADDR + 0x60) -+#define HIF_NOCPY_LMEM_ALLOC_ADDR (HIF_NOCPY_BASE_ADDR + 0x64) -+#define HIF_NOCPY_CLASS_ADDR (HIF_NOCPY_BASE_ADDR + 0x68) -+#define HIF_NOCPY_TMU_PORT0_ADDR (HIF_NOCPY_BASE_ADDR + 0x70) -+#define HIF_NOCPY_TMU_PORT1_ADDR (HIF_NOCPY_BASE_ADDR + 0x74) -+#define HIF_NOCPY_TMU_PORT2_ADDR (HIF_NOCPY_BASE_ADDR + 0x7c) -+#define HIF_NOCPY_TMU_PORT3_ADDR (HIF_NOCPY_BASE_ADDR + 0x80) -+#define HIF_NOCPY_TMU_PORT4_ADDR (HIF_NOCPY_BASE_ADDR + 0x84) -+#define HIF_NOCPY_INT_COAL (HIF_NOCPY_BASE_ADDR + 0x90) -+ -+ -+#endif /* _HIF_NOCPY_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h -@@ -0,0 +1,128 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _TMU_CSR_H_ -+#define _TMU_CSR_H_ -+ -+#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000) -+#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004) -+#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008) -+#define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c) -+#define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010) -+#define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014) -+#define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018) -+#define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c) -+#define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020) -+#define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024) -+#define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028) -+#define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c) -+#define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030) -+#define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034) -+#define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038) -+#define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c) -+#define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040) -+#define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044) -+#define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048) -+#define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c) -+#define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050) -+#define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054) -+#define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058) -+#define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c) -+#define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060) -+#define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064) -+#define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068) -+#define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c) -+#define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070) -+#define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074) -+#define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078) -+#define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c) -+#define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080) -+#define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084) -+#define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088) -+#define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c) -+#define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090) -+#define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094) -+#define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098) -+#define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c) -+#define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0) -+#define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4) -+#define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8) -+#define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac) -+#define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0) -+#define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4) -+#define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY0 */ -+#define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc) -+#define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0) -+#define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4) -+#define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8) -+#define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc) -+#define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0) -+#define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4) -+#define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8) -+#define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc) -+#define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0) -+ -+#define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4) /**< [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory Write [27:24] Byte Enables of the Internal memory access [23:0] Address of the internal memory. This address is used to access both the PM and DM of all the PE's */ -+#define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8) /**< Internal Memory Access Write Data */ -+#define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec) /**< Internal Memory Access Read Data. The commands are blocked at the mem_access only */ -+ -+#define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0) /**< [31:0] PHY0 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */ -+#define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4) /**< [31:0] PHY1 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */ -+#define TMU_PHY2_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f8) /**< [31:0] PHY2 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */ -+#define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc) /**< [31:0] PHY3 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */ -+#define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100) -+#define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104) -+ -+#define TMU_BUS_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x108) -+#define TMU_BUS_ACCESS (TMU_CSR_BASE_ADDR + 0x10c) -+#define TMU_BUS_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x110) -+ -+#define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114) -+#define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118) -+#define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c) -+#define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134) /**< [31:0] PHY4 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */ -+#define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY1 */ -+#define TMU_TDQ2_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x13c) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY2 */ -+#define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY3 */ -+#define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144) -+#define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148) /**< [31:0] PHY5 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */ -+ -+#define SW_RESET (1 << 0) /**< Global software reset */ -+#define INQ_RESET (1 << 2) -+#define TEQ_RESET (1 << 3) -+#define TDQ_RESET (1 << 4) -+#define PE_RESET (1 << 5) -+#define MEM_INIT (1 << 6) -+#define MEM_INIT_DONE (1 << 7) -+#define LLM_INIT (1 << 8) -+#define LLM_INIT_DONE (1 << 9) -+#define ECC_MEM_INIT_DONE (1<<10) -+ -+typedef struct { -+ u32 pe_sys_clk_ratio; -+ unsigned long llm_base_addr; -+ u32 llm_queue_len; -+} TMU_CFG; -+ -+/* Not HW related for pfe_ctrl / pfe common defines */ -+#define DEFAULT_MAX_QDEPTH 80 -+#define DEFAULT_Q0_QDEPTH 511 //We keep one large queue for host tx qos -+#define DEFAULT_TMU3_QDEPTH 127 -+ -+ -+#endif /* _TMU_CSR_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h -@@ -0,0 +1,61 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _UTIL_CSR_H_ -+#define _UTIL_CSR_H_ -+ -+#define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000) -+#define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004) -+#define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010) -+ -+#define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014) -+ -+#define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020) -+#define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024) -+#define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060) -+#define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064) -+ -+#define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100) -+#define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104) -+#define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108) -+ -+#define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114) -+#define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118) -+ -+#define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200) -+#define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204) -+#define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208) -+#define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c) -+#define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210) -+#define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214) -+#define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218) -+#define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c) -+#define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220) -+#define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224) -+ -+#define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228) -+#define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c) -+#define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230) -+ -+#define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234) -+ -+typedef struct { -+ u32 pe_sys_clk_ratio; -+} UTIL_CFG; -+ -+#endif /* _UTIL_CSR_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/class.h -@@ -0,0 +1,133 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _CLASS_H_ -+#define _CLASS_H_ -+ -+#include "pe.h" -+ -+#define CLASS_DMEM_BASE_ADDR 0x00000000 -+#define CLASS_DMEM_SIZE 0x2000 -+#define CLASS_DMEM_END (CLASS_DMEM_BASE_ADDR + CLASS_DMEM_SIZE) -+#define CLASS_PMEM_BASE_ADDR 0x00010000 -+ -+#define CBUS_BASE_ADDR 0xc0000000 -+#define CLASS_APB_BASE_ADDR 0xc1000000 -+#define CLASS_AHB1_BASE_ADDR 0xc2000000 -+#define CLASS_AHB2_BASE_ADDR 0xc3000000 -+ -+#include "cbus.h" -+ -+#define GPT_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x00000) -+#define UART_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x10000) -+#define PERG_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x20000) -+#define EFET_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x40000) -+ -+#define MAC_HASH_BASE_ADDR (CLASS_AHB1_BASE_ADDR + 0x30000) -+#define VLAN_HASH_BASE_ADDR (CLASS_AHB1_BASE_ADDR + 0x50000) -+ -+#define PE_LMEM_BASE_ADDR (CLASS_AHB2_BASE_ADDR + 0x10000) -+#define PE_LMEM_SIZE 0x8000 -+#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE) -+#define CCU_BASE_ADDR (CLASS_AHB2_BASE_ADDR + 0x20000) -+ -+#define IS_DMEM(addr, len) (((unsigned long)(addr) >= CLASS_DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= CLASS_DMEM_END)) -+#define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PE_LMEM_END)) -+ -+ -+#include "gpt.h" -+#include "uart.h" -+#include "class/perg.h" -+#include "class/efet.h" -+#include "class/mac_hash.h" -+#include "class/vlan_hash.h" -+#include "class/ccu.h" -+ -+ -+#define CLASS_MAX_PBUFFERS 4 -+ -+#define PBUF_HWPARSE_OFFSET 0x10 /* Fixed by hardware */ -+ -+#define PAYLOAD_DMEM_MAX_SIZE (CLASS_PBUF_SIZE - CLASS_PBUF_HEADER_OFFSET - sizeof(class_rx_hdr_t)) -+ -+ -+#define MIN_PKT_SIZE 56 -+ -+#define PARSE_ETH_TYPE (1 << 0) -+#define PARSE_VLAN_TYPE (1 << 1) -+#define PARSE_PPPOE_TYPE (1 << 2) -+#define PARSE_ARP_TYPE (1 << 3) -+#define PARSE_MCAST_TYPE (1 << 4) -+#define PARSE_IP_TYPE (1 << 5) -+#define PARSE_IPV6_TYPE (1 << 6) -+#define PARSE_IPV4_TYPE (1 << 7) -+ -+#define PARSE_IPX_TYPE (1 << 9) -+ -+#define PARSE_UDP_FLOW (1 << 11) -+#define PARSE_TCP_FLOW (1 << 12) -+#define PARSE_ICMP_FLOW (1 << 13) -+#define PARSE_IGMP_FLOW (1 << 14) -+#define PARSE_FRAG_FLOW (1 << 15) -+ -+#define PARSE_HIF_PKT (1 << 23) -+#define PARSE_ARC_HIT (1 << 24) -+#define PARSE_PKT_OVERFLOW (1 << 25) -+ -+#define PARSE_PROTO_MISMATCH (1 << 28) -+#define PARSE_L3_MISMATCH (1 << 29) -+#define PARSE_L2_MISMATCH (1 << 30) -+#define PARSE_INCOMPLETE (1 << 31) -+ -+ -+typedef struct _hwparse_t { -+ u16 sid; -+ u16 connid; -+ u8 toevec; -+ u8 pLayer2Hdr; -+ u8 pLayer3Hdr; -+ u8 pLayer4Hdr; -+ u16 vlanid; -+ u16 ifParseFlags; -+ u32 parseFlags; -+ u16 srcport; -+ u16 dstport; -+ u32 proto:8; -+ u32 port:4; -+ u32 hash:20; -+ u64 rte_res_valid:1; -+ u64 vlan_res_valid:1; -+ u64 dst_res_valid:1; -+ u64 src_res_valid:1; -+ u64 vlan_lookup:20; -+ u64 dst_lookup:20; -+ u64 src_lookup:20; -+} hwparse_t; -+ -+ -+typedef struct { -+ u8 num_cpy; /* no of copies to send out from RO block, for each there must be a corresponding tx pre-header */ -+ u8 dma_len; /* len to be DMAed to DDR mem, including all tx pre-headers */ -+ u16 src_addr; /* class dmem source address, pointing to first tx pre-header */ -+ u32 dst_addr; /* DDR memory destination address of first tx pre-header, must be so packet data is continuous in DDR */ -+ u32 res1; /* reserved for software usage - queue number? */ -+ u16 res2; /* reserved for software usage */ -+ u16 tsv; /* time stamp val */ -+} class_tx_desc_t; -+ -+#endif /* _CLASS_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/class/ccu.h -@@ -0,0 +1,28 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _CCU_H_ -+#define _CCU_H_ -+ -+#define CCU_ADDR (CCU_BASE_ADDR + 0x00) -+#define CCU_CNT (CCU_BASE_ADDR + 0x04) -+#define CCU_STATUS (CCU_BASE_ADDR + 0x08) -+#define CCU_VAL (CCU_BASE_ADDR + 0x0c) -+ -+#endif /* _CCU_H_ */ -+ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/class/efet.h -@@ -0,0 +1,44 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _CLASS_EFET_H_ -+#define _CLASS_EFET_H_ -+ -+//#define CLASS_EFET_ASYNC 1 -+ -+#define CLASS_EFET_ENTRY_ADDR (EFET_BASE_ADDR + 0x00) -+#define CLASS_EFET_ENTRY_SIZE (EFET_BASE_ADDR + 0x04) -+#define CLASS_EFET_ENTRY_DMEM_ADDR (EFET_BASE_ADDR + 0x08) -+#define CLASS_EFET_ENTRY_STATUS (EFET_BASE_ADDR + 0x0c) -+#define CLASS_EFET_ENTRY_ENDIAN (EFET_BASE_ADDR + 0x10) -+ -+#define CBUS2DMEM 0 -+#define DMEM2CBUS 1 -+ -+#define EFET2BUS_LE (1 << 0) -+#define PE2BUS_LE (1 << 1) -+ -+#ifdef CLASS_EFET_ASYNC -+void class_efet_async(u32 cbus_addr, u32 dmem_addr, u32 len, u32 dir); -+#endif -+ -+void class_efet_sync(u32 cbus_addr, u32 dmem_addr, u32 len, u32 dir); -+ -+ -+#endif /* _CLASS_EFET_H_ */ -+ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/class/mac_hash.h -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _MAC_HASH_H_ -+#define _MAC_HASH_H_ -+ -+#define MAC_HASH_REQ1_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x000) -+#define MAC_HASH_REQ2_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x020) -+#define MAC_HASH_REQ3_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x040) -+#define MAC_HASH_REQ4_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x060) -+#define MAC_HASH_REQ5_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x080) -+#define MAC_HASH_REQ6_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x0a0) -+#define MAC_HASH_REQ7_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x0c0) -+#define MAC_HASH_REQ8_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x0e0) -+ -+#define MAC_HASH_REQ_CMD(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x000) -+#define MAC_HASH_REQ_MAC1_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x004) -+#define MAC_HASH_REQ_MAC2_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x008) -+#define MAC_HASH_REQ_MASK1_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x00c) -+#define MAC_HASH_REQ_MASK2_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x010) -+#define MAC_HASH_REQ_ENTRY(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x014) -+#define MAC_HASH_REQ_STATUS(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x018) -+#define MAC_HASH_REQ_ENTRY_MAYCH(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x01c) -+ -+ -+#define MAC_HASH_FREELIST_PTR_HEAD (MAC_HASH_BASE_ADDR + 0x100) -+#define MAC_HASH_FREELIST_PTR_TAIL (MAC_HASH_BASE_ADDR + 0x104) -+#define MAC_HASH_FREELIST_ENTRIES_ADDR (MAC_HASH_BASE_ADDR + 0x108) -+ -+ -+#define HASH_CMD_INIT 1 -+#define HASH_CMD_ADD 2 -+#define HASH_CMD_DELETE 3 -+#define HASH_CMD_UPDATE 4 -+#define HASH_CMD_SEARCH 5 -+#define HASH_CMD_MEM_READ 6 -+#define HASH_CMD_MEM_WRITE 7 -+ -+#endif /* _MAC_HASH_H_ */ -+ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/class/perg.h -@@ -0,0 +1,39 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _PERG_H_ -+#define _PERG_H_ -+ -+#define PERG_QB_BUF_STATUS (PERG_BASE_ADDR + 0x00) -+#define PERG_RO_BUF_STATUS (PERG_BASE_ADDR + 0x04) -+#define PERG_CLR_QB_BUF_STATUS (PERG_BASE_ADDR + 0x08) -+#define PERG_SET_RO_BUF_STATUS (PERG_BASE_ADDR + 0x0c) -+#define PERG_CLR_RO_ERR_PKT (PERG_BASE_ADDR + 0x10) -+#define PERG_CLR_BMU2_ERR_PKT (PERG_BASE_ADDR + 0x14) -+ -+#define PERG_ID (PERG_BASE_ADDR + 0x18) -+#define PERG_TIMER1 (PERG_BASE_ADDR + 0x1c) -+//FIXME #define PERG_TIMER2 (PERG_BASE_ADDR + 0x20) -+#define PERG_BMU1_CURRDEPTH (PERG_BASE_ADDR + 0x20) -+#define PERG_BMU2_CURRDEPTH (PERG_BASE_ADDR + 0x24) -+#define PERG_HOST_GP (PERG_BASE_ADDR + 0x2c) -+#define PERG_PE_GP (PERG_BASE_ADDR + 0x30) -+#define PERG_INT_ENABLE (PERG_BASE_ADDR + 0x34) -+#define PERG_INT_SRC (PERG_BASE_ADDR + 0x38) -+ -+#endif /* _PERG_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/class/vlan_hash.h -@@ -0,0 +1,46 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _VLAN_HASH_H_ -+#define _VLAN_HASH_H_ -+ -+#define VLAN_HASH_REQ1_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x000) -+#define VLAN_HASH_REQ2_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x020) -+#define VLAN_HASH_REQ3_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x040) -+#define VLAN_HASH_REQ4_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x060) -+#define VLAN_HASH_REQ5_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x080) -+#define VLAN_HASH_REQ6_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x0a0) -+#define VLAN_HASH_REQ7_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x0c0) -+#define VLAN_HASH_REQ8_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x0e0) -+ -+#define VLAN_HASH_REQ_CMD(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x000) -+#define VLAN_HASH_REQ_MAC1_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x004) -+#define VLAN_HASH_REQ_MAC2_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x008) -+#define VLAN_HASH_REQ_MASK1_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x00c) -+#define VLAN_HASH_REQ_MASK2_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x010) -+#define VLAN_HASH_REQ_ENTRY(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x014) -+#define VLAN_HASH_REQ_STATUS(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x018) -+#define VLAN_HASH_REQ_ENTRY_MAYCH(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x01c) -+ -+ -+#define VLAN_HASH_FREELIST_PTR_HEAD (VLAN_HASH_BASE_ADDR + 0x100) -+#define VLAN_HASH_FREELIST_PTR_TAIL (VLAN_HASH_BASE_ADDR + 0x104) -+#define VLAN_HASH_FREELIST_ENTRIES_ADDR (VLAN_HASH_BASE_ADDR + 0x108) -+ -+#endif /* _VLAN_HASH_H_ */ -+ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/gpt.h -@@ -0,0 +1,44 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _GPT_H_ -+#define _GPT_H_ -+ -+#define GPT_VERSION (GPT_BASE_ADDR + 0x00) -+#define GPT_STATUS (GPT_BASE_ADDR + 0x04) -+#define GPT_CONFIG (GPT_BASE_ADDR + 0x08) -+#define GPT_COUNTER (GPT_BASE_ADDR + 0x0c) -+#define GPT_PERIOD (GPT_BASE_ADDR + 0x10) -+#define GPT_WIDTH (GPT_BASE_ADDR + 0x14) -+ -+/*** These bits are defined for GPT_STATUS register */ -+#define GPT_STAT_IRQ (1<<0) -+#define GPT_STAT_OVERFLOW_ERR (1<<4) -+#define GPT_STAT_TMR_ENABLE (1<<8) -+#define GPT_STAT_TMR_DISABLE (1<<9) -+ -+/*** These bits are defined for GPT_CONFIG register */ -+#define GPT_CONFIG_PWM_MODE 0x1 -+#define GPT_CONFIG_WCAP_MODE 0x2 -+#define GPT_CONFIG_CAP_PULSE_OUT (1<<2) -+#define GPT_CONFIG_PERIOD_CNT (1<<3) -+#define GPT_CONFIG_INTR_ENABLE (1<<4) -+#define GPT_CONFIG_AUX_SEL (1<<5) -+ -+ -+#endif /* _GPT_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/pe.h -@@ -0,0 +1,626 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _PE_H_ -+#define _PE_H_ -+ -+#include "hal.h" -+ -+#if defined(COMCERTO_2000_CLASS) -+#include "pfe/class.h" -+#elif defined(COMCERTO_2000_TMU) -+#include "pfe/tmu.h" -+#elif defined(COMCERTO_2000_UTIL) -+#include "pfe/util.h" -+#endif -+ -+enum { -+ CLASS0_ID = 0, -+ CLASS1_ID, -+ CLASS2_ID, -+ CLASS3_ID, -+ CLASS4_ID, -+ CLASS5_ID, -+ TMU0_ID, -+ TMU1_ID, -+ TMU2_ID, -+ TMU3_ID, -+ UTIL_ID, -+ MAX_PE -+}; -+#define PE_ID_ANY MAX_PE -+ -+/* Hardware definition of physical ports */ -+/* CLASS rx header phy number */ -+enum CLASS_RX_PHY { -+ RX_PHY_0 = 0x0, -+ RX_PHY_1, -+ RX_PHY_2, -+ RX_PHY_HIF, -+ RX_PHY_HIF_NOCPY, -+ RX_PHY_CLASS = 1 << 14, /**< Control bit (in PHYNO field) used to inform CLASS PE that packet comes from Class. */ -+ RX_PHY_UTIL = 1 << 15 /**< Control bit (in PHYNO field) used to inform CLASS PE that packet comes from UtilPE. */ -+}; -+ -+#define RX_PHY_SW_INPUT_PORT_OFFSET 11 /**< Offset in PHYNO field where the original input port will be stored for packets coming directly from software (UtilPE or Class). */ -+ -+ -+/* CLASS/TMU tx header phy number */ -+enum TMU_TX_PHY { -+ TX_PHY_TMU0 = 0x0, -+ TX_PHY_TMU1, -+ TX_PHY_TMU2, -+ TX_PHY_TMU3 -+}; -+ -+ -+// NOTE: Any changes to the following drop counter definitions must also -+// be reflected in the pfe/pfe.h file and in pfe_ctrl/pfe_sysfs.c. -+ -+#if defined(COMCERTO_2000_CLASS) -+ -+#define CLASS_DROP_ICC 0 -+#define CLASS_DROP_HOST_PKT_ERROR 1 -+#define CLASS_DROP_RX_ERROR 2 -+#define CLASS_DROP_IPSEC_OUT 3 -+#define CLASS_DROP_IPSEC_IN 4 -+#define CLASS_DROP_EXPT_IPSEC 5 -+#define CLASS_DROP_REASSEMBLY 6 -+#define CLASS_DROP_FRAGMENTER 7 -+#define CLASS_DROP_NATT 8 -+#define CLASS_DROP_SOCKET 9 -+#define CLASS_DROP_MULTICAST 10 -+#define CLASS_DROP_NATPT 11 -+#define CLASS_DROP_TX_DISABLE 12 -+ -+#define CLASS_NUM_DROP_COUNTERS 13 -+ -+extern U32 drop_counter[CLASS_NUM_DROP_COUNTERS]; -+#define DROP_PACKET(pmtd, counter) free_packet(pmtd, CLASS_DROP_##counter) -+#define DROP_BUFFER(addr, counter) free_buffer(addr, CLASS_DROP_##counter) -+ -+#elif defined(COMCERTO_2000_UTIL) -+ -+#define UTIL_DROP_IPSEC_OUT 0 -+#define UTIL_DROP_IPSEC_IN 1 -+#define UTIL_DROP_IPSEC_RATE_LIMIT 2 -+#define UTIL_DROP_FRAGMENTER 3 -+#define UTIL_DROP_SOCKET 4 -+#define UTIL_DROP_TX_DISABLE 5 -+#define UTIL_DROP_RX_ERROR 6 -+#define UTIL_DROP_NO_MTD 7 -+ -+#define UTIL_NUM_DROP_COUNTERS 8 -+ -+extern U32 drop_counter[UTIL_NUM_DROP_COUNTERS]; -+#define DROP_PACKET(pmtd, counter) free_packet(pmtd, UTIL_DROP_##counter) -+#define DROP_BUFFER(addr, counter) free_buffer(addr, UTIL_DROP_##counter) -+ -+#endif -+ -+ -+ -+#define DDR_BASE_ADDR 0x00020000 -+#define DDR_END 0x86000000 /* This includes ACP and IRAM areas */ -+#define IRAM_BASE_ADDR 0x83000000 -+ -+#define IS_DDR(addr, len) (((unsigned long)(addr) >= DDR_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DDR_END)) -+/* action bits of act_phyno is defined as follows */ -+ -+#define ACT_SRC_MAC_REPLACE (1 << (4 + 0)) -+#define ACT_VLAN_ADD (1 << (4 + 1)) -+#define ACT_TCPCHKSUM_REPLACE (1 << (4 + 2)) -+#define ACT_VLAN_REPLACE (1 << (4 + 3)) -+#define ACT_DONT_FREE_BUFFER (1 << (4 + 5)) -+#define ACT_IPCHKSUM_REPLACE (1 << (4 + 6)) -+ -+typedef struct { -+ u8 start_data_off; /* packet data start offset, relative to start of this tx pre-header */ -+ u8 start_buf_off; /* this tx pre-header start offset, relative to start of DDR buffer */ -+ u16 pkt_length; /* total packet length */ -+ u8 act_phyno; /* action / phy number */ -+ u8 queueno; /* queueno */ -+ u16 unused; -+} class_tx_hdr_t; -+ -+typedef struct { -+ u8 start_data_off; /* packet data start offset, relative to start of this tx pre-header */ -+ u8 start_buf_off; /* this tx pre-header start offset, relative to start of DDR buffer */ -+ u16 pkt_length; /* total packet length */ -+ u8 act_phyno; /* action / phy number */ -+ u8 queueno; /* queueno */ -+ u16 src_mac_msb; /* indicates src_mac 47:32 */ -+ u32 src_mac_lsb; /* indicates src_mac 31:0 */ -+ u32 vlanid; /* vlanid */ -+} class_tx_hdr_mc_t; -+ -+typedef struct { -+ u32 next_ptr; /* ptr to the start of the first DDR buffer */ -+ u16 length; /* total packet length */ -+ u16 phyno; /* input physical port number */ -+ u32 status; /* gemac status bits bits[32:63]*/ -+ u32 status2; /* gemac status bits bits[0:31] */ -+} class_rx_hdr_t; -+/* class_rx_hdr status bits (status0 bits in hardware blocks) -+ * from hif_top/dma_dxr_dtx.v -+ * STATUS[9:0] is the encoding of bits in the LMEM buffer as seen by the QB block, -+ * NOT the encoding of bits as seen by the Class PEs in the DMEM rx header */ -+#define STATUS_PARSE_DISABLE (1 << 0) -+#define STATUS_BRFETCH_DISABLE (1 << 1) -+#define STATUS_RTFETCH_DISABLE (1 << 2) -+#define STATUS_DIR_PROC_ID (1 << 3) -+#define STATUS_CONN_ID_EN (1 << 4)) -+#define STATUS_PE2PROC_ID(x) (((x) & 7) << 5) -+#define STATUS_LE_DATA (1 << 8) -+#define STATUS_CHKSUM_EN (1 << 9) -+ -+/* from gpi/gpi_rmlf.v */ -+#define STATUS_CUMULATIVE_ERR (1 << 16) -+#define STATUS_LENGTH_ERR (1 << 17) -+#define STATUS_CRC_ERR (1 << 18) -+#define STATUS_TOO_SHORT_ERR (1 << 19) -+#define STATUS_TOO_LONG_ERR (1 << 20) -+#define STATUS_CODE_ERR (1 << 21) -+#define STATUS_MC_HASH_MATCH (1 << 22) -+#define STATUS_CUMULATIVE_ARC_HIT (1 << 23) -+#define STATUS_UNICAST_HASH_MATCH (1 << 24) -+#define STATUS_IP_CHECKSUM_CORRECT (1 << 25) -+#define STATUS_TCP_CHECKSUM_CORRECT (1 << 26) -+#define STATUS_UDP_CHECKSUM_CORRECT (1 << 27) -+#define STATUS_OVERFLOW_ERR (1 << 28) -+ -+#define UTIL_MAGIC_NUM 0xffd8ffe000104a46 -+#define UTIL_DDRC_WA -+ -+/* The following structure is filled by class-pe when the packet -+ * has to be sent to util-pe, by filling the required information */ -+typedef struct { -+ u32 mtd_flags : 16; -+ u32 packet_type : 8; -+ u32 input_port : 4; -+ u32 data_offset : 4; -+ u32 word[MTD_PRIV]; -+#ifdef UTIL_DDRC_WA -+ u64 magic_num; // magic_number to verify the data validity in utilpe -+#endif -+} __attribute__((aligned(8))) util_rx_hdr_t; // Size must be a multiple of 64-bit to allow copies using EFET. -+ -+#define UTIL_RX_IPS_IN_PKT EVENT_IPS_IN -+#define UTIL_RX_IPS_OUT_PKT EVENT_IPS_OUT -+#define UTIL_RX_RTP_PKT EVENT_RTP_RELAY -+#define UTIL_RX_RTP_QOS_PKT EVENT_RTP_QOS -+#define UTIL_RX_FRAG4_PKT EVENT_FRAG4 -+#define UTIL_RX_FRAG6_PKT EVENT_FRAG6 -+ -+/** Structure passed from UtilPE to Class, stored at the end of the LMEM buffer. Defined and used by software only. -+ * -+ */ -+ -+typedef struct -+{ -+ void *next; -+ u16 next_length; -+ u8 next_l3offset; -+ u8 next_l4offset; -+} frag_info; -+ -+typedef struct { -+ u8 packet_type : 6; -+ u8 padding : 2; -+ -+ u8 offset : 3; -+ u8 ddr_offset : 5; -+ -+ u16 mtd_flags; -+ union { -+ u16 half[6]; -+ u8 byte[12]; -+ -+ struct { -+ u16 sa_handle[2]; // SA_MAX_OP value should be used here instead of 2 -+ u8 proto; -+ S8 sa_op; -+ u8 l2hdr_len; -+ u8 adj_dmem; -+ } ipsec; -+ -+ struct { -+ u16 l4offset; -+ u16 socket_id; -+ BOOL update; -+ u8 reserved; -+ u32 payload_diff; -+ } relay; -+ -+ struct { -+ u16 l3offset; -+ u16 l4offset; -+ -+ frag_info frag; -+ } ipv6; -+ -+ struct { -+ u16 l3offset; -+ } ipv4; -+ -+ struct { -+ u32 ddr_addr; -+ u16 length; -+ u8 port; -+ u8 queue; -+ u8 action; -+ } tx; -+ }; -+} lmem_trailer_t; -+ -+/* The following values are defined for packet_type of lmem_trailer_t. -+ * These represent different types of packets sent from util to class -+ * for processing */ -+enum { -+ UTIL_TX_IPS_IN = 0, -+ UTIL_TX_IPV4_RTP_PKT, -+ UTIL_TX_IPV6_RTP_PKT, -+ UTIL_TX_IPV4_PKT, -+ UTIL_TX_IPV6_PKT, -+ UTIL_TX_EXPT_PKT, -+#ifdef CFG_PCAP -+ UTIL_TX_PKT, -+#endif -+ UTIL_TX_MAX_PKT -+}; -+ -+ -+#define UTIL_TX_TRAILER_SIZE sizeof(lmem_trailer_t) -+#define UTIL_TX_TRAILER(mtd) ((lmem_trailer_t *)ROUND_UP32((u32)(mtd)->rx_dmem_end)) -+ -+typedef struct { -+ u32 pkt_ptr; -+ u8 phyno; -+ u8 queueno; -+ u16 len; -+} tmu_tx_hdr_t; -+ -+struct hif_pkt_hdr { -+ u8 client_id; -+ u8 qNo; -+ u16 client_ctrl_le_lsw; -+ u16 client_ctrl_le_msw; -+}; -+ -+ -+#if defined(CFG_WIFI_OFFLOAD) -+#define MAX_WIFI_VAPS 3 -+#define PFE_WIFI_PKT_HEADROOM 96 /*PFE inserts this headroom for WiFi tx packets only in lro mode */ -+#else -+#define MAX_WIFI_VAPS 0 -+#endif -+ -+/* HIF header client id */ -+enum HIF_CLIENT_ID { -+ CLIENT_ID_GEM0 = 0, -+ CLIENT_ID_GEM1, -+ CLIENT_ID_GEM2, -+ CLIENT_ID_WIFI0, -+ CLIENT_ID_WIFI_LAST = MAX_WIFI_VAPS + CLIENT_ID_GEM2, -+ CLIENT_ID_PCAP, -+ CLIENT_ID_UNKNOWN = 0xff, -+}; -+ -+ -+#define IS_WIFI_CLIENT_ID(_clid) (((_clid) >= CLIENT_ID_WIFI0) && ((_clid) <= CLIENT_ID_WIFI_LAST)) -+ -+/* These match LE definition */ -+#define HIF_CTRL_TX_TSO_NOCPY __cpu_to_le32(1 << 8) -+#define HIF_CTRL_TX_IPSEC_OUT __cpu_to_le32(1 << 7) -+#define HIF_CTRL_TX_WIFI_OWNMAC __cpu_to_le32(1 << 6) -+#define HIF_CTRL_TX_TSO_END __cpu_to_le32(1 << 5) -+#define HIF_CTRL_TX_TSO6 __cpu_to_le32(1 << 4) -+#define HIF_CTRL_TX_TSO __cpu_to_le32(1 << 3) -+#define HIF_CTRL_TX_CHECKSUM __cpu_to_le32(1 << 2) -+#define HIF_CTRL_TX_CSUM_VALIDATE __cpu_to_le32(1 << 1) -+#define HIF_CTRL_TX_WIFI_TXOFLD __cpu_to_le32(1 << 0) -+ -+#define HIF_CTRL_RX_OFFSET_MASK __cpu_to_le32(0xf << 24) -+#define HIF_CTRL_RX_PE_ID_MASK __cpu_to_le32(0xf << 16) -+#define HIF_CTRL_RX_IPSEC_IN __cpu_to_le32(1 << 4) -+#define HIF_CTRL_RX_WIFI_EXPT __cpu_to_le32(1 << 3) -+#define HIF_CTRL_RX_CHECKSUMMED __cpu_to_le32(1 << 2) -+#define HIF_CTRL_RX_CONTINUED __cpu_to_le32(1 << 1) -+#define HIF_CTRL_RX_WIFI_HEADROOM __cpu_to_le32(1 << 0) -+ -+#ifdef CFG_LRO -+struct hif_lro_hdr { -+ u16 data_offset; -+ u16 mss; -+}; -+#endif -+ -+struct hif_ipsec_hdr { -+ u16 sa_handle[2]; -+}; -+ -+#define MAX_TSO_BUF_DESCS 5 -+struct hif_tso_buf_desc { -+ u32 addr; -+ u32 ctrl; -+#define TSO_CTRL_LAST_BUFFER (1 << 31) -+}; -+ -+struct hif_tso_hdr { -+ u16 ip_off; -+ u16 ip_id; -+ u16 ip_len; -+ u16 tcp_off; -+ u32 tcp_seq; -+}; -+ -+struct hif_tso_hdr_nocpy { -+ u16 ip_off; -+ u16 ip_id; -+ u16 ip_len; -+ u16 tcp_off; -+ u32 tcp_seq; -+ struct hif_tso_buf_desc bdesc[MAX_TSO_BUF_DESCS]; -+}; -+ -+struct hif_pcap_hdr { -+ u8 ifindex; -+ u8 unused; -+ u16 seqno; -+ u32 timestamp; -+}; -+ -+ -+struct pe_sync_mailbox -+{ -+ u32 stop; -+ u32 stopped; -+}; -+ -+struct pe_msg_mailbox -+{ -+ u32 dst; -+ u32 src; -+ u32 len; -+ u32 request; -+}; -+ -+ -+/** Basic busy loop delay function -+* -+* @param cycles Number of cycles to delay (actual cpu cycles should be close to 3 x cycles) -+* -+*/ -+static inline void delay(u32 cycles) -+{ -+ volatile int i; -+ -+ for (i = 0; i < cycles; i++); -+} -+ -+ -+/** Read PE id -+* -+* @return PE id (0 - 5 for CLASS-PE's, 6 - 9 for TMU-PE's, 10 for UTIL-PE) -+* -+*/ -+static inline u32 esi_get_mpid(void) -+{ -+ u32 mpid; -+ -+ asm ("rcsr %0, Configuration, MPID" : "=d" (mpid)); -+ -+ return mpid; -+} -+ -+ -+#define esi_get_csr(bank, csr) \ -+({ \ -+ u32 res; \ -+ asm ("rcsr %0, " #bank ", " #csr : "=d" (res)); \ -+ res; \ -+}) -+ -+#define esi_get_isa0() esi_get_csr(Configuration, ISA0) -+#define esi_get_isa1() esi_get_csr(Configuration, ISA1) -+#define esi_get_isa2() esi_get_csr(Configuration, ISA2) -+#define esi_get_isa3() esi_get_csr(Configuration, ISA3) -+#define esi_get_epc() esi_get_csr(Thread, EPC) -+#define esi_get_ecas() esi_get_csr(Thread, ECAS) -+#define esi_get_eid() esi_get_csr(Thread, EID) -+#define esi_get_ed() esi_get_csr(Thread, ED) -+ -+static inline void esi_pe_stop(U32 state) -+{ -+ PESTATUS_SETSTATE(state); -+ while (1) -+ { -+ asm("stop"); -+ } -+} -+ -+ -+/** Same 64bit alignment memory copy using efet. -+* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR. -+* Both the source and destination must have the same 64bit alignment, length should be more than four bytes -+* or dst/src must be 32bit aligned. Otherwise use efet_memcpy_any() -+* Uses efet synchronous interface to copy the data. -+* -+* @param dst Destination address to write to (must have the same 64bit alignment as src) -+* @param src Source address to read from (must have the same 64bit alignment as dst) -+* @param len Number of bytes to copy -+* -+*/ -+void efet_memcpy(void *dst, void *src, unsigned int len); -+ -+/** Same 64bit alignment memory copy using efet. -+* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR. -+* Both the source and destination must have the same 64bit alignment, there is no restriction on length. -+* For UTIL-PE revA0, this function will still fail to handle small/unaligned writes. -+* Uses efet synchronous interface to copy the data. -+* -+* @param dst Destination address to write to (must have the same 64bit alignment as src) -+* @param src Source address to read from (must have the same 64bit alignment as dst) -+* @param len Number of bytes to copy -+* -+*/ -+void efet_memcpy_any(void *dst, void *src, unsigned int len); -+ -+/** Same 64bit alignment memory copy using efet. -+* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR. -+* Both the source and destination must have the same 64bit alignment, length should be more than four bytes -+* or dst/src must be 32bit aligned. -+* Uses efet asynchronous interface to copy the data. -+* -+* @param dst Destination address to write to (must have the same 64bit alignment as src) -+* @param src Source address to read from (must have the same 64bit alignment as dst) -+* @param len Number of bytes to copy -+* -+*/ -+void efet_memcpy_nowait(void *dst, void *src, unsigned int len); -+ -+/** Unaligned memory copy using efet. -+* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR. -+* There is not restriction on source and destination, nor on length. -+* -+* @param dst Destination address to write to -+* @param src Source address to read from -+* @param len Number of bytes to copy -+* @param dmem_buf temp dmem buffer to use, must be 64bit aligned -+* @param dmem_len length of dmem buffer, must be 64bit aligned and at least 16 bytes -+* -+*/ -+void efet_memcpy_unaligned(void *dst, void *src, unsigned int len, void *dmem_buf, unsigned int dmem_len); -+ -+/** Aligned memory copy of 4 bytes to register address. -+* Register address must be 32 bit aligned. -+* -+* @param val value to be copied. -+* @param reg_addr Register address (must be 16bit aligned) -+* -+*/ -+void __efet_writel(u32 val, void *addr); -+ -+#ifdef REVA_WA -+#define efet_writel(val, addr) __efet_writel((u32)(val), (void *) (addr)) -+#else -+#define efet_writel(val, addr) writel((u32)(val), (void *) (addr)) -+#endif -+ -+ -+/** 32bit aligned memory copy. -+* Source and destination addresses must be 32bit aligned, there is no restriction on the length. -+* -+* @param dst Destination address (must be 32bit aligned) -+* @param src Source address (must be 32bit aligned) -+* @param len Number of bytes to copy -+* -+*/ -+void memcpy_aligned32(void *dst, void *src, unsigned int len); -+ -+/** Aligned memory copy. -+* Source and destination addresses must have the same alignment -+* relative to 32bit boundaries (but otherwsie may have any alignment), -+* there is no restriction on the length. -+* -+* @param dst Destination address -+* @param src Source address (must have same 32bit alignment as dst) -+* @param len Number of bytes to copy -+* -+*/ -+void memcpy_aligned(void *dst, void *src, unsigned int len); -+ -+/** Unaligned memory copy. -+* Implements unaligned memory copy. We first align the destination -+* to a 32bit boundary (using byte copies) then the src, and finally use a loop -+* of read, shift, write -+* -+* @param dst Destination address -+* @param src Source address (must have same 32bit alignment as dst) -+* @param len Number of bytes to copy -+* -+*/ -+void memcpy_unaligned(void *dst, void *src, unsigned int len); -+ -+/** Generic memory set. -+* Implements a generic memory set. Not very optimal (uses byte writes for the entire range) -+* -+* -+* @param dst Destination address -+* @param val Value to set memory to -+* @param len Number of bytes to set -+* -+*/ -+void memset(void *dst, u8 val, unsigned int len); -+ -+/** Generic memory copy. -+* Implements generic memory copy. If source and destination have the same -+* alignment memcpy_aligned() is used, otherwise memcpy_unaligned() -+* -+* @param dst Destination address -+* @param src Source address -+* @param len Number of bytes to copy -+* -+*/ -+void memcpy(void *dst, void *src, unsigned int len); -+ -+/** Generic memorymove. -+* Implements generic memorymove, where copies across overlapping -+* memory regions is supported. -+* Uses the dmem_buf passed as a parameter as a temporary buffer. -+* Includes two copies, forces one of the copies to be definitely aligned. -+* The "dmem_len" being passed should be atleast 3 bytes greater than "len" -+* The 3 bytes here are shift bytes used to ensure one aligned copy. -+* -+* @param dst Destination address -+* @param src Source address -+* @param len Number of bytes to copy -+* @param dmem_buf temp dmem buffer to use, must be 32bit aligned -+* @param dmem_len length of dmem buffer, must be 32bit aligned and at least 3 bytes greater -+* than @param len -+* -+*/ -+ -+void *memorymove(void * dst, void * src, unsigned int len, void *dmem_buf, unsigned int dmem_len); -+ -+/** Aligned memory copy in DDR memory. -+ * Implements aligned memory copy between two DDR buffers using efet_memcpy64 and DMEM -+ * Both the source and destination must have the same 64bit alignment, there is no restriction on length. -+ * If start or end are not 64bit aligned, data in destination buffer before start/after end will be corrupted. -+ * -+ * @param dst DDR Destination address -+ * @param src DDR Source address -+ * @param len Number of bytes to copy -+ * @param dmem_buf temp dmem buffer to use, must be 64bit aligned -+ * @param dmem_len length of dmem buffer, must be 64bit aligned and at least 16 bytes -+ */ -+void memcpy_ddr_to_ddr(void *dst, void *src, unsigned int len, void *dmem_buf, unsigned int dmem_len); -+ -+/** Unaligned memory copy in DDR memory. -+ * Implements generic memory copy between two DDR buffers using efet_memcpy and DMEM -+ * There is no restriction on the source, destination and length alignments. -+ * -+ * @param dst DDR Destination address -+ * @param src DDR Source address -+ * @param len Number of bytes to copy -+ * @param dmem_buf temp dmem buffer to use, must be 64bit aligned -+ * @param dmem_len length of dmem buffer, must be 64bit aligned and at least 16 bytes -+ */ -+void memcpy_ddr_to_ddr_unaligned(void *dst, void *src, unsigned int len, void *dmem_buf, unsigned int dmem_len); -+ -+#endif /* _PE_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/pfe.h -@@ -0,0 +1,444 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _PFE_H_ -+#define _PFE_H_ -+ -+#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) -+#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) /* Only valid for mem access register interface */ -+#define CLASS_DMEM_SIZE 0x00002000 -+#define CLASS_IMEM_SIZE 0x00008000 -+ -+#define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) -+#define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) /* Only valid for mem access register interface */ -+#define TMU_DMEM_SIZE 0x00000800 -+#define TMU_IMEM_SIZE 0x00002000 -+ -+#define UTIL_DMEM_BASE_ADDR 0x00000000 -+#define UTIL_DMEM_SIZE 0x00002000 -+ -+#define PE_LMEM_BASE_ADDR 0xc3010000 -+#define PE_LMEM_SIZE 0x8000 -+#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE) -+ -+#define DMEM_BASE_ADDR 0x00000000 -+#define DMEM_SIZE 0x2000 /**< TMU has less... */ -+#define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE) -+ -+#define PMEM_BASE_ADDR 0x00010000 -+#define PMEM_SIZE 0x8000 /**< TMU has less... */ -+#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE) -+ -+ -+/* These check memory ranges from PE point of view/memory map */ -+#define IS_DMEM(addr, len) (((unsigned long)(addr) >= DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DMEM_END)) -+#define IS_PMEM(addr, len) (((unsigned long)(addr) >= PMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PMEM_END)) -+#define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PE_LMEM_END)) -+ -+#define IS_PFE_LMEM(addr, len) (((unsigned long)(addr) >= CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && (((unsigned long)(addr) + (len)) <= CBUS_VIRT_TO_PFE(LMEM_END))) -+#define __IS_PHYS_DDR(addr, len) (((unsigned long)(addr) >= DDR_PHYS_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DDR_PHYS_END)) -+#define IS_PHYS_DDR(addr, len) __IS_PHYS_DDR(DDR_PFE_TO_PHYS(addr), len) -+ -+/* If using a run-time virtual address for the cbus base address use this code */ -+extern void *cbus_base_addr; -+extern void *ddr_base_addr; -+extern unsigned long ddr_phys_base_addr; -+extern unsigned int ddr_size; -+ -+#if defined(COMCERTO_2000_CONTROL) -+#include -+#if defined (CONFIG_PLATFORM_C2000) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) -+/*This is copied from arch/arm/include/asm/system_info.h */ -+extern unsigned int system_rev; -+#endif -+#endif -+#endif -+ -+#define CBUS_BASE_ADDR cbus_base_addr -+#define DDR_PHYS_BASE_ADDR ddr_phys_base_addr -+#define DDR_BASE_ADDR ddr_base_addr -+#define DDR_SIZE ddr_size -+ -+#define DDR_PHYS_END (DDR_PHYS_BASE_ADDR + DDR_SIZE) -+ -+#if defined(CONFIG_PLATFORM_C2000) -+#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /**< CBUS physical base address as seen by PE's. */ -+#define DDR_PHYS_TO_PFE(p) (p) -+#define DDR_PFE_TO_PHYS(p) (p) -+#define CBUS_PHYS_TO_PFE(p) (p) -+#else -+#define LS1012A_PFE_RESET_WA /*PFE doesn't have global reset and re-init should takecare few things to make PFE functional after reset */ -+#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /**< CBUS physical base address as seen by PE's. */ -+#define PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE 0xc0000000 /**< CBUS physical base address as seen by PE's. */ -+#define DDR_PHYS_TO_PFE(p) (((unsigned long int) (p)) & 0x7FFFFFFF) -+#define DDR_PFE_TO_PHYS(p) (((unsigned long int) (p)) | 0x80000000) -+#define CBUS_PHYS_TO_PFE(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE) /*Translates to PFE address map */ -+#endif -+ -+#define DDR_PHYS_TO_VIRT(p) (((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR) -+#define DDR_VIRT_TO_PHYS(v) (((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR) -+#define DDR_VIRT_TO_PFE(p) (DDR_PHYS_TO_PFE(DDR_VIRT_TO_PHYS(p))) -+ -+#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + PFE_CBUS_PHYS_BASE_ADDR) -+#define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR) -+ -+/* The below part of the code is used in QOS control driver from host */ -+#define TMU_APB_BASE_ADDR 0xc1000000 /** TMU base address seen by pe's */ -+ -+#define SHAPER0_BASE_ADDR (TMU_APB_BASE_ADDR + 0x020000) -+#define SHAPER1_BASE_ADDR (TMU_APB_BASE_ADDR + 0x030000) -+#define SHAPER2_BASE_ADDR (TMU_APB_BASE_ADDR + 0x040000) -+#define SHAPER3_BASE_ADDR (TMU_APB_BASE_ADDR + 0x050000) -+#define SHAPER4_BASE_ADDR (TMU_APB_BASE_ADDR + 0x060000) -+#define SHAPER5_BASE_ADDR (TMU_APB_BASE_ADDR + 0x070000) -+#define SHAPER6_BASE_ADDR (TMU_APB_BASE_ADDR + 0x080000) -+#define SHAPER7_BASE_ADDR (TMU_APB_BASE_ADDR + 0x090000) -+#define SHAPER8_BASE_ADDR (TMU_APB_BASE_ADDR + 0x0a0000) -+#define SHAPER9_BASE_ADDR (TMU_APB_BASE_ADDR + 0x0b0000) -+ -+#define SCHED0_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1c0000) -+#define SCHED1_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1d0000) -+#define SCHED2_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1e0000) -+#define SCHED3_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1f0000) -+#define SCHED4_BASE_ADDR (TMU_APB_BASE_ADDR + 0x200000) -+#define SCHED5_BASE_ADDR (TMU_APB_BASE_ADDR + 0x210000) -+#define SCHED6_BASE_ADDR (TMU_APB_BASE_ADDR + 0x220000) -+#define SCHED7_BASE_ADDR (TMU_APB_BASE_ADDR + 0x230000) -+ -+#define PHY_QUEUE_BASE_ADDR (TMU_APB_BASE_ADDR + 0x260000) -+#define QUEUE_RESULT0 (PHY_QUEUE_BASE_ADDR + 0x48) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY3), [6:0] winner input queue number */ -+#define QUEUE_RESULT1 (PHY_QUEUE_BASE_ADDR + 0x4c) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY4), [6:0] winner input queue number */ -+#define QUEUE_RESULT2 (PHY_QUEUE_BASE_ADDR + 0x50) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY5), [6:0] winner input queue number */ -+ -+#define QUEUE_RESULT0_REGOFFSET (QUEUE_RESULT0 - QUEUE_RESULT0) -+#define QUEUE_RESULT1_REGOFFSET (QUEUE_RESULT1 - QUEUE_RESULT0) -+#define QUEUE_RESULT2_REGOFFSET (QUEUE_RESULT2 - QUEUE_RESULT0) -+ -+ -+#include "cbus.h" -+ -+enum { -+ CLASS0_ID = 0, -+ CLASS1_ID, -+ CLASS2_ID, -+ CLASS3_ID, -+#if !defined(CONFIG_PLATFORM_PCI) -+ CLASS4_ID, -+ CLASS5_ID, -+#endif -+#if !defined(CONFIG_TMU_DUMMY) -+ TMU0_ID, -+ TMU1_ID, -+ TMU2_ID, -+ TMU3_ID, -+#else -+ TMU0_ID, -+#endif -+#if !defined(CONFIG_UTIL_DISABLED) -+ UTIL_ID, -+#endif -+ MAX_PE -+}; -+ -+enum { -+ CLASS_TYPE = 0, -+ TMU_TYPE, -+ UTIL_TYPE -+}; -+ -+#if !defined(CONFIG_PLATFORM_PCI) -+#define CLASS_MASK ((1 << CLASS0_ID) | (1 << CLASS1_ID) | (1 << CLASS2_ID) | (1 << CLASS3_ID) | (1 << CLASS4_ID) | (1 << CLASS5_ID)) -+#define CLASS_MAX_ID CLASS5_ID -+#else -+#define CLASS_MASK ((1 << CLASS0_ID) | (1 << CLASS1_ID) | (1 << CLASS2_ID) | (1 << CLASS3_ID)) -+#define CLASS_MAX_ID CLASS3_ID -+#endif -+ -+#if !defined(CONFIG_TMU_DUMMY) -+#if defined(CONFIG_PLATFORM_LS1012A) -+#define TMU_MASK ((1 << TMU0_ID) | (1 << TMU1_ID) | (1 << TMU3_ID)) -+#else -+#define TMU_MASK ((1 << TMU0_ID) | (1 << TMU1_ID) | (1 << TMU2_ID) | (1 << TMU3_ID)) -+#endif -+#define TMU_MAX_ID TMU3_ID -+#else -+#define TMU_MASK (1 << TMU0_ID) -+#define TMU_MAX_ID TMU0_ID -+#endif -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+#define UTIL_MASK (1 << UTIL_ID) -+#endif -+ -+typedef struct tPE_STATUS -+{ -+ u32 cpu_state; -+ u32 activity_counter; -+ u32 rx; -+ union { -+ u32 tx; -+ u32 tmu_qstatus; -+ }; -+ u32 drop; -+#if defined(CFG_PE_DEBUG) -+ u32 debug_indicator; -+ u32 debug[16]; -+#endif -+} __attribute__((aligned(16))) PE_STATUS; -+ -+ -+struct pe_sync_mailbox -+{ -+ u32 stop; -+ u32 stopped; -+}; -+ -+struct pe_msg_mailbox -+{ -+ u32 dst; -+ u32 src; -+ u32 len; -+ u32 request; -+}; -+ -+// Drop counter definitions -+ -+#define CLASS_NUM_DROP_COUNTERS 13 -+#define UTIL_NUM_DROP_COUNTERS 8 -+ -+ -+/** PE information. -+ * Structure containing PE's specific information. It is used to create -+ * generic C functions common to all PE's. -+ * Before using the library functions this structure needs to be initialized with the different registers virtual addresses -+ * (according to the ARM MMU mmaping). The default initialization supports a virtual == physical mapping. -+ * -+ */ -+struct pe_info -+{ -+ u32 dmem_base_addr; /**< PE's dmem base address */ -+ u32 pmem_base_addr; /**< PE's pmem base address */ -+ u32 pmem_size; /**< PE's pmem size */ -+ -+ void *mem_access_wdata; /**< PE's _MEM_ACCESS_WDATA register address */ -+ void *mem_access_addr; /**< PE's _MEM_ACCESS_ADDR register address */ -+ void *mem_access_rdata; /**< PE's _MEM_ACCESS_RDATA register address */ -+}; -+ -+ -+void pe_lmem_read(u32 *dst, u32 len, u32 offset); -+void pe_lmem_write(u32 *src, u32 len, u32 offset); -+ -+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len); -+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len); -+ -+u32 pe_pmem_read(int id, u32 addr, u8 size); -+ -+void pe_dmem_write(int id, u32 val, u32 addr, u8 size); -+u32 pe_dmem_read(int id, u32 addr, u8 size); -+void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len); -+void class_pe_lmem_memset(u32 dst, int val, unsigned int len); -+void class_bus_write(u32 val, u32 addr, u8 size); -+u32 class_bus_read(u32 addr, u8 size); -+ -+ -+#define class_bus_readl(addr) class_bus_read(addr, 4) -+#define class_bus_readw(addr) class_bus_read(addr, 2) -+#define class_bus_readb(addr) class_bus_read(addr, 1) -+ -+#define class_bus_writel(val, addr) class_bus_write(val, addr, 4) -+#define class_bus_writew(val, addr) class_bus_write(val, addr, 2) -+#define class_bus_writeb(val, addr) class_bus_write(val, addr, 1) -+ -+#define pe_dmem_readl(id, addr) pe_dmem_read(id, addr, 4) -+#define pe_dmem_readw(id, addr) pe_dmem_read(id, addr, 2) -+#define pe_dmem_readb(id, addr) pe_dmem_read(id, addr, 1) -+ -+#define pe_dmem_writel(id, val, addr) pe_dmem_write(id, val, addr, 4) -+#define pe_dmem_writew(id, val, addr) pe_dmem_write(id, val, addr, 2) -+#define pe_dmem_writeb(id, val, addr) pe_dmem_write(id, val, addr, 1) -+ -+//int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr); -+int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr, struct device *dev); -+ -+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base, unsigned int ddr_size); -+void bmu_init(void *base, BMU_CFG *cfg); -+void bmu_reset(void *base); -+void bmu_enable(void *base); -+void bmu_disable(void *base); -+void bmu_set_config(void *base, BMU_CFG *cfg); -+ -+/* An enumerated type for loopback values. This can be one of three values, no -+ * loopback -normal operation, local loopback with internal loopback module of -+ * MAC or PHY loopback which is through the external PHY. -+ */ -+#ifndef __MAC_LOOP_ENUM__ -+#define __MAC_LOOP_ENUM__ -+typedef enum {LB_NONE, LB_EXT, LB_LOCAL} MAC_LOOP; -+#endif -+ -+ -+void gemac_init(void *base, void *config); -+void gemac_disable_rx_checksum_offload(void *base); -+void gemac_enable_rx_checksum_offload(void *base); -+void gemac_set_mdc_div(void *base, int mdc_div); -+void gemac_set_speed(void *base, MAC_SPEED gem_speed); -+void gemac_set_duplex(void *base, int duplex); -+void gemac_set_mode(void *base, int mode); -+void gemac_enable(void *base); -+void gemac_tx_disable(void *base); -+void gemac_disable(void *base); -+void gemac_reset(void *base); -+void gemac_set_address(void *base, SPEC_ADDR *addr); -+SPEC_ADDR gemac_get_address(void *base); -+void gemac_set_loop( void *base, MAC_LOOP gem_loop ); -+void gemac_set_laddr1(void *base, MAC_ADDR *address); -+void gemac_set_laddr2(void *base, MAC_ADDR *address); -+void gemac_set_laddr3(void *base, MAC_ADDR *address); -+void gemac_set_laddr4(void *base, MAC_ADDR *address); -+void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index); -+void gemac_clear_laddr1(void *base); -+void gemac_clear_laddr2(void *base); -+void gemac_clear_laddr3(void *base); -+void gemac_clear_laddr4(void *base); -+void gemac_clear_laddrN(void *base, unsigned int entry_index); -+MAC_ADDR gemac_get_hash( void *base ); -+void gemac_set_hash( void *base, MAC_ADDR *hash ); -+MAC_ADDR gem_get_laddr1(void *base); -+MAC_ADDR gem_get_laddr2(void *base); -+MAC_ADDR gem_get_laddr3(void *base); -+MAC_ADDR gem_get_laddr4(void *base); -+MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index); -+void gemac_set_config(void *base, GEMAC_CFG *cfg); -+void gemac_allow_broadcast(void *base); -+void gemac_no_broadcast(void *base); -+void gemac_enable_unicast(void *base); -+void gemac_disable_unicast(void *base); -+void gemac_enable_multicast(void *base); -+void gemac_disable_multicast(void *base); -+void gemac_enable_fcs_rx(void *base); -+void gemac_disable_fcs_rx(void *base); -+void gemac_enable_1536_rx(void *base); -+void gemac_disable_1536_rx(void *base); -+void gemac_enable_rx_jmb(void *base); -+void gemac_disable_rx_jmb(void *base); -+void gemac_enable_stacked_vlan(void *base); -+void gemac_disable_stacked_vlan(void *base); -+void gemac_enable_pause_rx(void *base); -+void gemac_disable_pause_rx(void *base); -+void gemac_enable_copy_all(void *base); -+void gemac_disable_copy_all(void *base); -+void gemac_set_bus_width(void *base, int width); -+void gemac_set_wol(void *base, u32 wol_conf); -+ -+void gpi_init(void *base, GPI_CFG *cfg); -+void gpi_reset(void *base); -+void gpi_enable(void *base); -+void gpi_disable(void *base); -+void gpi_set_config(void *base, GPI_CFG *cfg); -+ -+void class_init(CLASS_CFG *cfg); -+void class_reset(void); -+void class_enable(void); -+void class_disable(void); -+void class_set_config(CLASS_CFG *cfg); -+ -+void tmu_reset(void); -+void tmu_init(TMU_CFG *cfg); -+void tmu_enable(u32 pe_mask); -+void tmu_disable(u32 pe_mask); -+u32 tmu_qstatus(u32 if_id); -+u32 tmu_pkts_processed(u32 if_id); -+ -+void util_init(UTIL_CFG *cfg); -+void util_reset(void); -+void util_enable(void); -+void util_disable(void); -+ -+void hif_nocpy_init(void); -+void hif_nocpy_tx_enable(void); -+void hif_nocpy_tx_disable(void); -+void hif_nocpy_rx_enable(void); -+void hif_nocpy_rx_disable(void); -+ -+void hif_init(void); -+void hif_tx_enable(void); -+void hif_tx_disable(void); -+void hif_rx_enable(void); -+void hif_rx_disable(void); -+ -+ -+/** Get Chip Revision level -+* -+*/ -+ -+static inline unsigned int CHIP_REVISION(void) -+{ -+#if defined (CONFIG_PLATFORM_C2000) -+#if 1 -+ return system_rev; -+ //return 0; -+#else -+ return (readl(COMCERTO_GPIO_DEVICE_ID_REG) >> 24) & 0xf; -+#endif -+ -+#else -+ /*For LS1012A return always 1 */ -+ return 1; -+#endif -+} -+ -+/** Start HIF rx DMA -+* -+*/ -+static inline void hif_rx_dma_start(void) -+{ -+ /*TODO not sure poll_cntrl_en is required or not */ -+ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_RX_CTRL); -+} -+ -+/** Start HIF tx DMA -+* -+*/ -+static inline void hif_tx_dma_start(void) -+{ -+ /*TODO not sure poll_cntrl_en is required or not */ -+ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL); -+} -+ -+/** Start HIF_NOCPY rx DMA -+* -+*/ -+static inline void hif_nocpy_rx_dma_start(void) -+{ -+ /*TODO not sure poll_cntrl_en is required or not */ -+ writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_NOCPY_RX_CTRL); -+} -+ -+/** Start HIF_NOCPY tx DMA -+* -+*/ -+static inline void hif_nocpy_tx_dma_start(void) -+{ -+ /*TODO not sure poll_cntrl_en is required or not */ -+ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_NOCPY_TX_CTRL); -+} -+ -+#endif /* _PFE_H_ */ -+ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/tmu.h -@@ -0,0 +1,68 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _TMU_H_ -+#define _TMU_H_ -+ -+#define TMU_DMEM_BASE_ADDR 0x00000000 -+#define TMU_PMEM_BASE_ADDR 0x00010000 -+ -+#define CBUS_BASE_ADDR 0xc0000000 -+#define TMU_APB_BASE_ADDR 0xc1000000 -+ -+#if defined (COMCERTO_2000_TMU) || defined (COMCERTO_2000_CONTROL) -+ -+#include "cbus.h" -+ -+#define GPT_BASE_ADDR (TMU_APB_BASE_ADDR + 0x00000) -+#define UART_BASE_ADDR (TMU_APB_BASE_ADDR + 0x10000) -+ -+#define SHAPER0_BASE_ADDR (TMU_APB_BASE_ADDR + 0x020000) -+#define SHAPER1_BASE_ADDR (TMU_APB_BASE_ADDR + 0x030000) -+#define SHAPER2_BASE_ADDR (TMU_APB_BASE_ADDR + 0x040000) -+#define SHAPER3_BASE_ADDR (TMU_APB_BASE_ADDR + 0x050000) -+#define SHAPER4_BASE_ADDR (TMU_APB_BASE_ADDR + 0x060000) -+#define SHAPER5_BASE_ADDR (TMU_APB_BASE_ADDR + 0x070000) -+#define SHAPER6_BASE_ADDR (TMU_APB_BASE_ADDR + 0x080000) -+#define SHAPER7_BASE_ADDR (TMU_APB_BASE_ADDR + 0x090000) -+#define SHAPER8_BASE_ADDR (TMU_APB_BASE_ADDR + 0x0a0000) -+#define SHAPER9_BASE_ADDR (TMU_APB_BASE_ADDR + 0x0b0000) -+ -+#define SCHED0_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1c0000) -+#define SCHED1_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1d0000) -+#define SCHED2_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1e0000) -+#define SCHED3_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1f0000) -+#define SCHED4_BASE_ADDR (TMU_APB_BASE_ADDR + 0x200000) -+#define SCHED5_BASE_ADDR (TMU_APB_BASE_ADDR + 0x210000) -+#define SCHED6_BASE_ADDR (TMU_APB_BASE_ADDR + 0x220000) -+#define SCHED7_BASE_ADDR (TMU_APB_BASE_ADDR + 0x230000) -+ -+#define SHAPER_STATUS (TMU_APB_BASE_ADDR + 0x270000) /**< [9:0] bitmask of shapers that have positive credit */ -+ -+#include "gpt.h" -+#include "uart.h" -+#include "tmu/shaper.h" -+#include "tmu/sched.h" -+ -+#endif -+ -+#define PHY_QUEUE_BASE_ADDR (TMU_APB_BASE_ADDR + 0x260000) -+ -+#include "tmu/phy_queue.h" -+ -+#endif /* _TMU_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/tmu/phy_queue.h -@@ -0,0 +1,56 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _PHY_QUEUE_H_ -+#define _PHY_QUEUE_H_ -+ -+#define PHY_QUEUE_SHAPER_STATUS (PHY_QUEUE_BASE_ADDR + 0x00) /**< [28:19] same as SHAPER_STATUS, [18:3] same as QUEUE_STATUS, [2:0] must be zero before a new packet may be dequeued */ -+#define QUEUE_STATUS (PHY_QUEUE_BASE_ADDR + 0x04) /**< [15:0] bit mask of input queues with pending packets */ -+ -+#define QUEUE0_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x08) -+#define QUEUE1_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x0c) -+#define QUEUE2_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x10) -+#define QUEUE3_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x14) -+#define QUEUE4_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x18) -+#define QUEUE5_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x1c) -+#define QUEUE6_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x20) -+#define QUEUE7_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x24) -+#define QUEUE8_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x28) -+#define QUEUE9_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x2c) -+#define QUEUE10_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x30) -+#define QUEUE11_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x34) -+#define QUEUE12_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x38) -+#define QUEUE13_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x3c) -+#define QUEUE14_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x40) -+#define QUEUE15_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x44) -+#define QUEUE_RESULT0 (PHY_QUEUE_BASE_ADDR + 0x48) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY3), [6:0] winner input queue number */ -+#define QUEUE_RESULT1 (PHY_QUEUE_BASE_ADDR + 0x4c) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY4), [6:0] winner input queue number */ -+#define QUEUE_RESULT2 (PHY_QUEUE_BASE_ADDR + 0x50) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY5), [6:0] winner input queue number */ -+#define TMU_PE_GP_REG (PHY_QUEUE_BASE_ADDR + 0x54) -+#define QUEUE_GBL_PKTLEN (PHY_QUEUE_BASE_ADDR + 0x5c) -+#define QUEUE_GBL_PKTLEN_MASK (PHY_QUEUE_BASE_ADDR + 0x60) -+ -+#define QUEUE_RESULT0_REGOFFSET (QUEUE_RESULT0 - QUEUE_RESULT0) -+#define QUEUE_RESULT1_REGOFFSET (QUEUE_RESULT1 - QUEUE_RESULT0) -+#define QUEUE_RESULT2_REGOFFSET (QUEUE_RESULT2 - QUEUE_RESULT0) -+ -+#define TEQ_HTD (1 << 22) -+#define TEQ_HWRED (1 << 21) -+ -+ -+#endif /* _PHY_QUEUE_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/tmu/sched.h -@@ -0,0 +1,72 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _SCHED_H_ -+#define _SCHED_H_ -+ -+/* Offsets from SCHEDx_BASE_ADDR */ -+#define SCHED_CTRL 0x00 -+#define SCHED_SLOT_TIME 0x04 -+#define SCHED_RES 0x08 -+#define SCHED_QUEUE_ALLOC0 0x0c -+#define SCHED_QUEUE_ALLOC1 0x10 -+#define SCHED_BW 0x14 -+#define SCHED_GUR_DEF_CTR 0x18 -+#define SCHED_AVL_CTR 0x1c -+#define SCHED_QU0_WGHT 0x20 -+#define SCHED_QU1_WGHT 0x24 -+#define SCHED_QU2_WGHT 0x28 -+#define SCHED_QU3_WGHT 0x2c -+#define SCHED_QU4_WGHT 0x30 -+#define SCHED_QU5_WGHT 0x34 -+#define SCHED_QU6_WGHT 0x38 -+#define SCHED_QU7_WGHT 0x3c -+#define SCHED_QUE0_DEFICIT_CNT 0x40 -+#define SCHED_QUE1_DEFICIT_CNT 0x44 -+#define SCHED_QUE2_DEFICIT_CNT 0x48 -+#define SCHED_QUE3_DEFICIT_CNT 0x4c -+#define SCHED_QUE4_DEFICIT_CNT 0x50 -+#define SCHED_QUE5_DEFICIT_CNT 0x54 -+#define SCHED_QUE6_DEFICIT_CNT 0x58 -+#define SCHED_QUE7_DEFICIT_CNT 0x5c -+#define SCHED_PKT_LEN 0x60 -+ -+#define SCHED_CTRL_ALGOTYPE(x) (((x) & 0xf) << 0) -+#define SCHED_CTRL_CALQUOTA(x) (((x) & 0x1) << 4) -+#define SCHED_CTRL_ACTIVE_Q(x) (((x) & 0xff) << 8) -+#define SCHED_CTRL_SHARE_BW(x) (((x) & 0xff) << 16) -+#define SCHED_CTRL_BARROW_BW(x) (((x) & 0xff) << 24) -+ -+#define SCHED_QUEUE_ALLOC(x, b) (((x) & 0x1f) << (b)) -+ -+#define SCHED_QUEUE_ALLOC0_QUEUEA(x) (((x) & 0x1f) << 0) -+#define SCHED_QUEUE_ALLOC0_QUEUEB(x) (((x) & 0x1f) << 8) -+#define SCHED_QUEUE_ALLOC0_QUEUEC(x) (((x) & 0x1f) << 16) -+#define SCHED_QUEUE_ALLOC0_QUEUED(x) (((x) & 0x1f) << 24) -+ -+#define SCHED_QUEUE_ALLOC0_RES0(x) (((x) & 0x7) << 5) -+#define SCHED_QUEUE_ALLOC0_RES1(x) (((x) & 0x7) << 13) -+#define SCHED_QUEUE_ALLOC0_RES2(x) (((x) & 0x7) << 21) -+#define SCHED_QUEUE_ALLOC0_RES3(x) (((x) & 0x7) << 29) -+ -+#define SCHED_QUEUE_ALLOC1_QUEUEA(x) (((x) & 0x1f) << 0) -+#define SCHED_QUEUE_ALLOC1_QUEUEB(x) (((x) & 0x1f) << 8) -+#define SCHED_QUEUE_ALLOC1_QUEUEC(x) (((x) & 0x1f) << 16) -+#define SCHED_QUEUE_ALLOC1_QUEUED(x) (((x) & 0x1f) << 24) -+ -+#endif /* _SCHED_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/tmu/shaper.h -@@ -0,0 +1,37 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _SHAPER_H_ -+#define _SHAPER_H_ -+ -+/* Offsets from SHAPPERx_BASE_ADDR */ -+#define SHAPER_CTRL 0x00 -+#define SHAPER_WEIGHT 0x04 -+#define SHAPER_PKT_LEN 0x08 -+ -+#define SHAPER_CTRL_ENABLE(x) (((x) & 0x1) << 0) -+#define SHAPER_CTRL_QNO(x) (((x) & 0x3f) << 1) -+#define SHAPER_CTRL_CLKDIV(x) (((x) & 0xffff) << 16) -+ -+#define SHAPER_WEIGHT_FRACWT(x) (((x) & 0xff) << 0) -+#define SHAPER_WEIGHT_INTWT(x) (((x) & 0x3) << 8) -+#define SHAPER_WEIGHT_MAXCREDIT(x) (((x) & 0x3fffff) << 10) -+ -+#define PORT_SHAPER_MASK (1 << 0) -+ -+#endif /* _SHAPER_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/uart.h -@@ -0,0 +1,31 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _UART_H_ -+#define _UART_H_ -+ -+#define UART_THR (UART_BASE_ADDR + 0x00) -+#define UART_IER (UART_BASE_ADDR + 0x04) -+#define UART_IIR (UART_BASE_ADDR + 0x08) -+#define UART_LCR (UART_BASE_ADDR + 0x0c) -+#define UART_MCR (UART_BASE_ADDR + 0x10) -+#define UART_LSR (UART_BASE_ADDR + 0x14) -+#define UART_MDR (UART_BASE_ADDR + 0x18) -+#define UART_SCRATCH (UART_BASE_ADDR + 0x1c) -+ -+#endif /* _UART_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/util.h -@@ -0,0 +1,49 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _UTIL_H_ -+#define _UTIL_H_ -+ -+#define UTIL_DMEM_BASE_ADDR 0x00000000 -+#define UTIL_DMEM_SIZE 0x00002000 -+#define UTIL_DMEM_END (UTIL_DMEM_BASE_ADDR + UTIL_DMEM_SIZE) -+ -+#define IS_DMEM(addr, len) (((unsigned long)(addr) >= UTIL_DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= UTIL_DMEM_END)) -+ -+#define CBUS_BASE_ADDR 0xc0000000 -+#define UTIL_APB_BASE_ADDR 0xc1000000 -+ -+#include "cbus.h" -+ -+#define GPT_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x00000) -+#define UART_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x10000) -+#define EAPE_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x20000) -+#define INQ_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x30000) -+#define EFET1_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x40000) -+#define EFET2_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x50000) -+#define EFET3_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x60000) -+ -+ -+#include "gpt.h" -+#include "uart.h" -+#include "util/eape.h" -+#include "util/inq.h" -+#include "util/efet.h" -+ -+ -+#endif /* _UTIL_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/util/eape.h -@@ -0,0 +1,57 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _EAPE_H_ -+#define _EAPE_H_ -+ -+#define EAPE_STATUS (EAPE_BASE_ADDR + 0x0) -+#define EAPE_INT_ENABLE (EAPE_BASE_ADDR + 0x4) -+#define EAPE_INT_SRC (EAPE_BASE_ADDR + 0x8) -+#define EAPE_HOST_INT_ENABLE (EAPE_BASE_ADDR + 0xc) -+ -+/** The following bits represents to enable interrupts from host and to host -+* from / to utilpe */ -+ -+#define IRQ_EN_EFET_TO_UTIL 0x1 -+#define IRQ_EN_QB_TO_UTIL 0x2 -+#define IRQ_EN_INQ_TO_UTIL 0x4 -+#define IRQ_EN_EAPE_TO_UTIL 0x8 -+#define IRQ_EN_GPT_TMR_TO_UTIL 0x10 -+#define IRQ_EN_UART_TO_UTIL 0x20 -+#define IRQ_EN_SYSLP_TO_UTIL 0x40 -+#define IRQ_EN_UPEGP_TO_UTIL 0x80 -+ -+/** Out interrupts */ -+ -+#define IRQ_EN_EFET_OUT 0x100 -+#define IRQ_EN_QB_OUT 0x200 -+#define IRQ_EN_INQ_OUT 0x400 -+#define IRQ_EN_EAPE_OUT 0x800 -+#define IRQ_EN_GPT_TMR_OUT 0x1000 -+#define IRQ_EN_UART_OUT 0x2000 -+#define IRQ_EN_SYSLP_OUT 0x4000 -+#define IRQ_EN_UPEGP_OUT 0x8000 -+ -+/** The following bits are enabled in the status register -+ * which are mapped to IPSEC status register bits */ -+#define EAPE_IN_STAT_AVAIL 0x1 -+#define EAPE_OUT_STAT_AVAIL 0x2 -+#define EAPE_IN_CMD_AVAIL 0x4 -+#define EAPE_OUT_CMD_AVAIL 0x8 -+ -+#endif /* _EAPE_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/util/efet.h -@@ -0,0 +1,119 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _UTIL_EFET_H_ -+#define _UTIL_EFET_H_ -+ -+#define EFET_ENTRY_ADDR 0x00 -+#define EFET_ENTRY_SIZE 0x04 -+#define EFET_ENTRY_DMEM_ADDR 0x08 -+#define EFET_ENTRY_STATUS 0x0c -+#define EFET_ENTRY_ENDIAN 0x10 -+ -+#define CBUS2DMEM 0 -+#define DMEM2CBUS 1 -+ -+#define EFET2BUS_LE (1 << 0) -+ -+#define EFET1 0 -+#define EFET2 1 -+#define EFET3 2 -+#define MAX_UTIL_EFET_LEN 128 -+ -+extern const unsigned long util_efet_baseaddr[3]; -+extern u32 util_efet_status; -+ -+/* The barrier call is an empirical work-around for an unknown bug: for some unknown reason, it solves -+ * a UtilPE crash observed with LRO and packet steering. Other solutions also worked (e.g. barrier, -+ * nop calls in other positions). However, no common pattern could be extracted from those solutions -+ * to narrow down the source of the crash. -+ */ -+ -+#define __UTIL_EFET(i, cbus_addr, dmem_addr,len,dir) do { \ -+ __writel((len & 0x3FF) | (dir << 16), util_efet_baseaddr[i] + EFET_ENTRY_SIZE); \ -+ __writel(dmem_addr, util_efet_baseaddr[i] + EFET_ENTRY_DMEM_ADDR);\ -+ __writel(cbus_addr, util_efet_baseaddr[i] + EFET_ENTRY_ADDR);\ -+ nop();\ -+ }while(0) -+ -+#define UTIL_EFET(i, cbus_addr, dmem_addr,len,dir) do { \ -+ __UTIL_EFET(i, cbus_addr, dmem_addr, len, dir); \ -+ util_efet_status |= (1 << i); \ -+ } while(0) -+ -+ -+/** Waits for the util efet to finish a transaction, blocking the caller -+* (without updating the status). -+* Can be called at any time. -+* -+* @param i Efet index -+* -+* -+*/ -+static inline void __util_efet_wait(int i) -+{ -+ while (!(readl(util_efet_baseaddr[i] + EFET_ENTRY_STATUS) & 0x1)) ; -+} -+ -+/** Waits for the util efet to finish a transaction, blocking the caller. -+* Can be called at any time. -+* -+* @param i Efet index -+* -+*/ -+static inline void util_efet_wait(int i) -+{ -+ __util_efet_wait(i); -+ -+ util_efet_status &= ~(1 << i); -+} -+ -+/** Asynchronous interface to util efet read/write functions. -+* It will wait for the efet to finish previous transaction, but does not wait for the current transaction to finish. -+* -+* @param i Efet index -+* @param cbus_addr Cbus address (must be 64bits aligned) -+* @param dmem_addr DMEM address (must be 64bits aligned) -+* @param len Number of bytes to copy (must be 64bits aligned size) -+* @param dir Direction of the transaction (0 - cbus to dmem, 1 - dmem to cbus) -+* -+*/ -+static inline void util_efet_async(int i, u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir) -+{ -+ if (util_efet_status & (1 << i)) -+ util_efet_wait(i); -+ -+ UTIL_EFET(i, cbus_addr, dmem_addr, len, dir); -+} -+ -+ -+static inline void util_efet_async0( u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir) -+{ -+ util_efet_async(0, cbus_addr, dmem_addr, len,dir); -+} -+ -+/* EFET 2 is aways used for SYNC operations */ -+static inline void util_efet_sync2(u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir) -+{ -+ __UTIL_EFET(2, cbus_addr, dmem_addr, len,dir); -+ __util_efet_wait(2); -+} -+ -+void util_efet_sync0(u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir); -+#endif /* _UTIL_EFET_H_ */ -+ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/util/inq.h -@@ -0,0 +1,28 @@ -+/* -+ * Copyright (c) 2011, 2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -+ * -+*/ -+#ifndef _INQ_H_ -+#define _INQ_H_ -+ -+#define INQ_HOST_GP (INQ_BASE_ADDR + 0x00) /* FIXME what are these for ? */ -+#define INQ_UPE_GP (INQ_BASE_ADDR + 0x04) /* FIXME what are these for ? */ -+ -+#define INQ_QB_PKTPTR (INQ_BASE_ADDR + 0x08) -+#define INQ_FIFO_CNT (INQ_BASE_ADDR + 0x0c) -+ -+#endif /* _INQ_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_ctrl.c -@@ -0,0 +1,363 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifdef __KERNEL__ -+#include -+#include -+#include -+#include -+#include -+#else -+#include "platform.h" -+#endif -+ -+#include "pfe_mod.h" -+#include "pfe_ctrl.h" -+ -+#include "pfe_ctrl_hal.h" -+ -+static struct pe_sync_mailbox CLASS_DMEM_SH2(sync_mailbox); -+static struct pe_sync_mailbox TMU_DMEM_SH2(sync_mailbox); -+ -+static struct pe_msg_mailbox CLASS_DMEM_SH2(msg_mailbox); -+static struct pe_msg_mailbox TMU_DMEM_SH2(msg_mailbox); -+ -+#if !defined(CONFIG_PLATFORM_LS1012A) -+static u32 CLASS_DMEM_SH2(resume); -+static u32 TMU_DMEM_SH2(resume); -+#endif -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+static struct pe_sync_mailbox UTIL_DMEM_SH2(sync_mailbox); -+static struct pe_msg_mailbox UTIL_DMEM_SH2(msg_mailbox); -+static u32 UTIL_DMEM_SH2(resume); -+#endif -+ -+static int pfe_ctrl_timer(void *data); -+ -+static int initialized = 0; -+ -+#define TIMEOUT_MS 1000 -+ -+int relax(unsigned long end) -+{ -+#ifdef __KERNEL__ -+ if (time_after(jiffies, end)) { -+ if (time_after(jiffies, end + (TIMEOUT_MS * HZ) / 1000)) { -+ return -1; -+ } -+ -+ if (need_resched()) -+ schedule(); -+ } -+#else -+ udelay(1); -+#endif -+ -+ return 0; -+} -+ -+#if !defined(CONFIG_PLATFORM_LS1012A) -+void pfe_ctrl_suspend(struct pfe_ctrl *ctrl) -+{ -+ int id; -+ -+ kthread_stop(ctrl->timer_thread); -+ -+ mutex_lock(&ctrl->mutex); -+ -+ initialized = 0; -+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) -+ pe_dmem_write(id, cpu_to_be32(0x1), (unsigned long)virt_to_class_dmem(&class_resume), 4); -+ -+ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) { -+#if defined(CONFIG_PLATFORM_LS1012A) -+ if(id == TMU2_ID) continue; -+#endif -+ pe_dmem_write(id, cpu_to_be32(0x1), (unsigned long)virt_to_class_dmem(&tmu_resume), 4); -+ } -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+ pe_dmem_write(UTIL_ID, cpu_to_be32(0x1), (unsigned long)virt_to_class_dmem(&util_resume), 4); -+#endif -+ -+ pe_sync_stop(&pfe->ctrl, 0xFF); -+ -+ mutex_unlock(&ctrl->mutex); -+} -+ -+void pfe_ctrl_resume(struct pfe_ctrl *ctrl) -+{ -+ mutex_lock(&ctrl->mutex); -+ initialized = 1; -+ pe_start(&pfe->ctrl, 0xFF); -+ mutex_unlock(&ctrl->mutex); -+ -+ ctrl->timer_thread = kthread_create(pfe_ctrl_timer, ctrl, "pfe_ctrl_timer"); -+ -+ wake_up_process(ctrl->timer_thread); -+} -+#endif -+ -+/** PE sync stop. -+* Stops packet processing for a list of PE's (specified using a bitmask). -+* The caller must hold ctrl->mutex. -+* -+* @param ctrl Control context -+* @param pe_mask Mask of PE id's to stop -+* -+*/ -+int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask) -+{ -+ struct pe_sync_mailbox *mbox; -+ int pe_stopped = 0; -+ unsigned long end = jiffies + 2; -+ int i; -+ -+#if defined(CONFIG_PLATFORM_LS1012A) -+ //TODO Util should be removed after IPSec is ported -+ pe_mask &= 0x2FF; //Exclude Util + TMU2 -+#endif -+ for (i = 0; i < MAX_PE; i++) -+ if (pe_mask & (1 << i)) { -+ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; -+ -+ pe_dmem_write(i, cpu_to_be32(0x1), (unsigned long)&mbox->stop, 4); -+ } -+ -+ while (pe_stopped != pe_mask) { -+ for (i = 0; i < MAX_PE; i++) -+ if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) { -+ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; -+ -+ if (pe_dmem_read(i, (unsigned long)&mbox->stopped, 4) & cpu_to_be32(0x1)) -+ pe_stopped |= (1 << i); -+ } -+ -+ if (relax(end) < 0) -+ goto err; -+ } -+ -+ return 0; -+ -+err: -+ printk(KERN_ERR "%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped); -+ -+ for (i = 0; i < MAX_PE; i++) -+ if (pe_mask & (1 << i)) { -+ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; -+ -+ pe_dmem_write(i, cpu_to_be32(0x0), (unsigned long)&mbox->stop, 4); -+ } -+ -+ return -EIO; -+} -+ -+/** PE start. -+* Starts packet processing for a list of PE's (specified using a bitmask). -+* The caller must hold ctrl->mutex. -+* -+* @param ctrl Control context -+* @param pe_mask Mask of PE id's to start -+* -+*/ -+void pe_start(struct pfe_ctrl *ctrl, int pe_mask) -+{ -+ struct pe_sync_mailbox *mbox; -+ int i; -+ -+#if defined(CONFIG_PLATFORM_LS1012A) -+ //TODO Util should be removed after IPSec is ported -+ pe_mask &= 0x2FF; //Exclude Util + TMU2 -+#endif -+ for (i = 0; i < MAX_PE; i++) -+ if (pe_mask & (1 << i)) { -+ -+ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; -+ -+ pe_dmem_write(i, cpu_to_be32(0x0), (unsigned long)&mbox->stop, 4); -+ } -+} -+ -+ -+/** Sends a control request to a given PE (to copy data to/from internal memory from/to DDR). -+* The caller must hold ctrl->mutex. -+* -+* @param ctrl Control context -+* @param id PE id -+* @param dst Physical destination address of data -+* @param src Physical source address of data -+* @param len Data length -+* -+*/ -+int pe_request(struct pfe_ctrl *ctrl, int id, unsigned short cmd_type, unsigned long dst, unsigned long src, int len) -+{ -+ struct pe_msg_mailbox mbox = { -+ .dst = cpu_to_be32(dst), -+ .src = cpu_to_be32(src), -+ .len = cpu_to_be32(len), -+ .request = cpu_to_be32((cmd_type << 16) | 0x1), -+ }; -+ struct pe_msg_mailbox *pmbox = (void *)ctrl->msg_mailbox_baseaddr[id]; -+ unsigned long end = jiffies + 2; -+ u32 rc; -+ -+ /* This works because .request is written last */ -+ pe_dmem_memcpy_to32(id, (unsigned long)pmbox, &mbox, sizeof(mbox)); -+ -+ while ((rc = pe_dmem_read(id, (unsigned long)&pmbox->request, 4)) & cpu_to_be32(0xffff)) { -+ if (relax(end) < 0) -+ goto err; -+ } -+ -+ rc = be32_to_cpu(rc); -+ -+ return rc >> 16; -+ -+err: -+ printk(KERN_ERR "%s: timeout, %x\n", __func__, be32_to_cpu(rc)); -+ pe_dmem_write(id, cpu_to_be32(0), (unsigned long)&pmbox->request, 4); -+ return -EIO; -+} -+ -+ -+/** Control code timer thread. -+* -+* A kernel thread is used so that the timer code can be run under the control path mutex. -+* The thread wakes up regularly and checks if any timer in the timer list as expired. -+* The timers are re-started automatically. -+* The code tries to keep the number of times a timer runs per unit time constant on average, -+* if the thread scheduling is delayed, it's possible for a particular timer to be scheduled in -+* quick succession to make up for the lost time. -+* -+* @param data Pointer to the control context structure -+* -+* @return 0 on sucess, a negative value on error -+* -+*/ -+static int pfe_ctrl_timer(void *data) -+{ -+ struct pfe_ctrl *ctrl = data; -+ TIMER_ENTRY *timer, *next; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ while (1) -+ { -+ schedule_timeout_uninterruptible(ctrl->timer_period); -+ -+ mutex_lock(&ctrl->mutex); -+ -+ list_for_each_entry_safe(timer, next, &ctrl->timer_list, list) -+ { -+ if (time_after(jiffies, timer->timeout)) -+ { -+ timer->timeout += timer->period; -+ -+ timer->handler(); -+ } -+ } -+ -+ mutex_unlock(&ctrl->mutex); -+ -+ if (kthread_should_stop()) -+ break; -+ } -+ -+ printk(KERN_INFO "%s exiting\n", __func__); -+ -+ return 0; -+} -+ -+ -+int pfe_ctrl_init(struct pfe *pfe) -+{ -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ int id; -+ int rc; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ mutex_init(&ctrl->mutex); -+ spin_lock_init(&ctrl->lock); -+ -+ ctrl->timer_period = HZ / TIMER_TICKS_PER_SEC; -+ -+ INIT_LIST_HEAD(&ctrl->timer_list); -+ -+ /*INIT_WORK(&ctrl->work, comcerto_fpp_workqueue);*/ -+ -+ INIT_LIST_HEAD(&ctrl->msg_list); -+ -+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { -+ ctrl->sync_mailbox_baseaddr[id] = virt_to_class_dmem(&class_sync_mailbox); -+ ctrl->msg_mailbox_baseaddr[id] = virt_to_class_dmem(&class_msg_mailbox); -+ } -+ -+ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) { -+#if defined(CONFIG_PLATFORM_LS1012A) -+ if(id == TMU2_ID) continue; -+#endif -+ ctrl->sync_mailbox_baseaddr[id] = virt_to_tmu_dmem(&tmu_sync_mailbox); -+ ctrl->msg_mailbox_baseaddr[id] = virt_to_tmu_dmem(&tmu_msg_mailbox); -+ } -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+ ctrl->sync_mailbox_baseaddr[UTIL_ID] = virt_to_util_dmem(&util_sync_mailbox); -+ ctrl->msg_mailbox_baseaddr[UTIL_ID] = virt_to_util_dmem(&util_msg_mailbox); -+#endif -+ -+ ctrl->hash_array_baseaddr = pfe->ddr_baseaddr + ROUTE_TABLE_BASEADDR; -+ ctrl->hash_array_phys_baseaddr = pfe->ddr_phys_baseaddr + ROUTE_TABLE_BASEADDR; -+ ctrl->ipsec_lmem_phys_baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR + IPSEC_LMEM_BASEADDR); -+ ctrl->ipsec_lmem_baseaddr = (LMEM_BASE_ADDR + IPSEC_LMEM_BASEADDR); -+ -+ ctrl->timer_thread = kthread_create(pfe_ctrl_timer, ctrl, "pfe_ctrl_timer"); -+ if (IS_ERR(ctrl->timer_thread)) -+ { -+ printk (KERN_ERR "%s: kthread_create() failed\n", __func__); -+ rc = PTR_ERR(ctrl->timer_thread); -+ goto err0; -+ } -+ -+ ctrl->dev = pfe->dev; -+ -+ wake_up_process(ctrl->timer_thread); -+ -+ printk(KERN_INFO "%s finished\n", __func__); -+ -+ initialized = 1; -+ -+ return 0; -+ -+err0: -+ return rc; -+} -+ -+ -+void pfe_ctrl_exit(struct pfe *pfe) -+{ -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ initialized = 0; -+ -+ kthread_stop(ctrl->timer_thread); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_ctrl.h -@@ -0,0 +1,111 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _PFE_CTRL_H_ -+#define _PFE_CTRL_H_ -+ -+#include -+ -+#include "pfe_mod.h" -+#include "pfe/pfe.h" -+ -+#define DMA_BUF_SIZE_128 0x80 /* enough for 1 conntracks */ -+#define DMA_BUF_SIZE_256 0x100 /* enough for 2 conntracks, 1 bridge entry or 1 multicast entry */ -+#define DMA_BUF_SIZE_512 0x200 /* 512bytes dma allocated buffers used by rtp relay feature */ -+#define DMA_BUF_MIN_ALIGNMENT 8 -+#define DMA_BUF_BOUNDARY (4 * 1024) /* bursts can not cross 4k boundary */ -+ -+#define CMD_TX_ENABLE 0x0501 -+#define CMD_TX_DISABLE 0x0502 -+ -+#define CMD_RX_LRO 0x0011 -+#define CMD_PKTCAP_ENABLE 0x0d01 -+#define CMD_QM_EXPT_RATE 0x020c -+ -+#define EXPT_TYPE_PCAP 0x3 -+ -+struct pfe_ctrl { -+ struct mutex mutex; -+ spinlock_t lock; -+ -+ void *dma_pool; -+ void *dma_pool_512; -+ void *dma_pool_128; -+ -+ struct device *dev; -+ -+ void *hash_array_baseaddr; /** Virtual base address of the conntrack hash array */ -+ unsigned long hash_array_phys_baseaddr; /** Physical base address of the conntrack hash array */ -+ -+ struct task_struct *timer_thread; -+ struct list_head timer_list; -+ unsigned long timer_period; -+ -+ int (*event_cb)(u16, u16, u16*); -+ -+ unsigned long sync_mailbox_baseaddr[MAX_PE]; /* Sync mailbox PFE internal address, initialized when parsing elf images */ -+ unsigned long msg_mailbox_baseaddr[MAX_PE]; /* Msg mailbox PFE internal address, initialized when parsing elf images */ -+ -+ unsigned long class_dmem_sh; -+ unsigned long class_pe_lmem_sh; -+ unsigned long tmu_dmem_sh; -+ unsigned long util_dmem_sh; -+ unsigned long util_ddr_sh; -+ struct clk *clk_axi; -+ unsigned int sys_clk; // AXI clock value, in KHz -+ void *ipsec_lmem_baseaddr; -+ unsigned long ipsec_lmem_phys_baseaddr; -+ -+ /* used for asynchronous message transfer to PFE */ -+ struct list_head msg_list; -+ struct work_struct work; -+}; -+ -+int pfe_ctrl_init(struct pfe *pfe); -+void pfe_ctrl_exit(struct pfe *pfe); -+ -+int pe_send_cmd(unsigned short cmd_type, unsigned short action, unsigned long param1, unsigned long param2); -+int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask); -+void pe_start(struct pfe_ctrl *ctrl, int pe_mask); -+int pe_request(struct pfe_ctrl *ctrl, int id,unsigned short cmd_type, unsigned long dst, unsigned long src, int len); -+int pe_read(struct pfe_ctrl *ctrl, int id, u32 *dst, unsigned long src, int len, int clear_flag); -+int tmu_pe_request(struct pfe_ctrl *ctrl, int id, unsigned int tmu_cmd_bitmask); -+ -+int pfe_ctrl_set_eth_state(int id, unsigned int state, unsigned char *mac_addr); -+int pfe_ctrl_set_lro(char enable); -+#ifdef CFG_PCAP -+int pfe_ctrl_set_pcap(char enable); -+int pfe_ctrl_set_pcap_ratelimit(u32 pkts_per_msec); -+#endif -+void pfe_ctrl_suspend(struct pfe_ctrl *ctrl); -+void pfe_ctrl_resume(struct pfe_ctrl *ctrl); -+int relax(unsigned long end); -+ -+/* used for asynchronous message transfer to PFE */ -+#define FPP_MAX_MSG_LENGTH 256 /* expressed in U8 -> 256 bytes*/ -+struct fpp_msg { -+ struct list_head list; -+ void (*callback)(unsigned long, int, u16, u16 *); -+ unsigned long data; -+ u16 fcode; -+ u16 length; -+ u16 *payload; -+}; -+ -+#endif /* _PFE_CTRL_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_ctrl_hal.c -@@ -0,0 +1,207 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+/* OS abstraction functions used by PFE control code */ -+ -+#include -+ -+#include "pfe_ctrl_hal.h" -+ -+#include "pfe_mod.h" -+ -+extern char *__class_dmem_sh; -+extern char *__tmu_dmem_sh; -+#if !defined(CONFIG_UTIL_DISABLED) -+extern char *__util_dmem_sh; -+extern char *__util_ddr_sh; -+#endif -+ -+HostMessage msg_buf; -+static int msg_buf_used = 0; -+unsigned long virt_to_class_dmem(void *p) -+{ -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ -+ if (p) -+ return (unsigned long)p - (unsigned long)&__class_dmem_sh + ctrl->class_dmem_sh; -+ else -+ return 0; -+} -+unsigned long virt_to_tmu_dmem(void *p) -+{ -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ -+ if (p) -+ return (unsigned long)p - (unsigned long)&__tmu_dmem_sh + ctrl->tmu_dmem_sh; -+ else -+ return 0; -+} -+ -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+unsigned long virt_to_util_dmem(void *p) -+{ -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ -+ if (p) -+ return (unsigned long)p - (unsigned long)&__util_dmem_sh + ctrl->util_dmem_sh; -+ else -+ return 0; -+} -+ -+/** Returns the DDR physical address of a Util PE shared DDR variable. -+ * -+ * @param p pointer (kernel space, virtual) to be converted to a physical address. -+ */ -+unsigned long virt_to_util_ddr(void *p) -+{ -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ -+ if (p) -+ return (unsigned long)p - (unsigned long)&__util_ddr_sh + ctrl->util_ddr_sh; -+ else -+ return 0; -+} -+/** Returns the virtual address of a Util PE shared DDR variable. -+ * -+ * @param p pointer (kernel space, virtual) to be converted to a pointer (usable in kernel space) -+ * pointing to the actual data. -+ */ -+ -+void * virt_to_util_virt(void *p) -+{ -+ if (p) -+ return DDR_PHYS_TO_VIRT(virt_to_util_ddr(p)); -+ else -+ return NULL; -+} -+#endif -+unsigned long virt_to_phys_iram(void *p) -+{ -+ if (p) -+ return (p - pfe->iram_baseaddr) + pfe->iram_phys_baseaddr; -+ else -+ return 0; -+} -+ -+unsigned long virt_to_phys_ipsec_lmem(void *p) -+{ -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ -+ if (p) -+ return (p - ctrl->ipsec_lmem_baseaddr) + ctrl->ipsec_lmem_phys_baseaddr; -+ else -+ return 0; -+} -+ -+unsigned long virt_to_phys_ipsec_axi(void *p) -+{ -+ if (p) -+ return (p - pfe->ipsec_baseaddr) + pfe->ipsec_phys_baseaddr; -+ else -+ return 0; -+} -+ -+ -+HostMessage *msg_alloc(void) -+{ -+ if (msg_buf_used) -+ { -+ printk(KERN_ERR "%s: failed\n", __func__); -+ return NULL; -+ } -+ -+ msg_buf_used = 1; -+ -+ return &msg_buf; -+} -+ -+void msg_free(HostMessage *msg) -+{ -+ if (!msg_buf_used) -+ printk(KERN_ERR "%s: freing already free msg buffer\n", __func__); -+ -+ msg_buf_used = 0; -+} -+ -+int msg_send(HostMessage *msg) -+{ -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ int rc = -1; -+ -+ if (!ctrl->event_cb) -+ goto out; -+ -+ if (ctrl->event_cb(msg->code, msg->length, msg->data) < 0) -+ goto out; -+ -+ rc = 0; -+ -+out: -+ msg_free(msg); -+ -+ return rc; -+} -+ -+ -+void timer_init(TIMER_ENTRY *timer, TIMER_HANDLER handler) -+{ -+ timer->handler = handler; -+ timer->running = 0; -+} -+ -+ -+void timer_add(TIMER_ENTRY *timer, u16 granularity) -+{ -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ -+ -+ timer->period = granularity; -+ timer->timeout = jiffies + timer->period; -+ -+ if (!timer->running) -+ { -+ list_add(&timer->list, &ctrl->timer_list); -+ timer->running = 1; -+ } -+} -+ -+ -+void timer_del(TIMER_ENTRY *timer) -+{ -+ -+ if (timer->running) -+ { -+ list_del(&timer->list); -+ timer->running = 0; -+ } -+} -+ -+ -+void *Heap_Alloc(int size) -+{ -+ /* FIXME we may want to use dma API's and use non cacheable memory */ -+ return pfe_kmalloc(size, GFP_KERNEL); -+} -+ -+ -+void Heap_Free(void *p) -+{ -+ pfe_kfree(p); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_ctrl_hal.h -@@ -0,0 +1,129 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _PFE_CTRL_HAL_H_ -+#define _PFE_CTRL_HAL_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "pfe_mod.h" -+ -+#define CLASS_DMEM_SH(var) __attribute__((section(".class_dmem_sh_" #var))) var -+#define CLASS_PE_LMEM_SH(var) __attribute__((section(".class_pe_lmem_sh_" #var))) var -+#define TMU_DMEM_SH(var) __attribute__((section(".tmu_dmem_sh_" #var))) var -+#define UTIL_DMEM_SH(var) __attribute__((section(".util_dmem_sh_" #var))) var -+#define UTIL_DDR_SH(var) __attribute__((section(".util_ddr_sh_" #var))) var -+ -+#define CLASS_DMEM_SH2(var) __attribute__((section(".class_dmem_sh_" #var))) class_##var -+#define CLASS_PE_LMEM_SH2(var) __attribute__((section(".class_pe_lmem_sh_" #var))) class_##var -+#define TMU_DMEM_SH2(var) __attribute__((section(".tmu_dmem_sh_" #var))) tmu_##var -+#define UTIL_DMEM_SH2(var) __attribute__((section(".util_dmem_sh_" #var))) util_##var -+ -+/** Translate the name of a shared variable to its PFE counterpart. -+ * Those macros may be used to determine the address of a shared variable, -+ * and will work even if the variable is accessed through a macro, as is the case -+ * with most fields of gFppGlobals. -+ */ -+#define CONCAT(str, var) str##var -+#define CLASS_VARNAME2(var) CONCAT(class_, var) -+#define UTIL_VARNAME2(var) CONCAT(util_, var) -+#define TMU_VARNAME2(var) CONCAT(tmu_, var) -+ -+typedef struct tHostMessage { -+ u16 length; -+ u16 code; -+ u16 data[128]; -+} HostMessage; -+ -+HostMessage *msg_alloc(void); -+void msg_free(HostMessage *msg); -+int msg_send(HostMessage *msg); -+ -+ -+unsigned long virt_to_class(void *p); -+unsigned long virt_to_class_dmem(void *p); -+unsigned long virt_to_class_pe_lmem(void *p); -+unsigned long virt_to_tmu_dmem(void *p); -+unsigned long virt_to_util_dmem(void *p); -+unsigned long virt_to_util_ddr(void *p); -+void * virt_to_util_virt(void *p); -+unsigned long virt_to_phys_iram(void *p); -+unsigned long virt_to_phys_ipsec_lmem(void *p); -+unsigned long virt_to_phys_ipsec_axi(void *p); -+ -+ -+#define TIMER_TICKS_PER_SEC 100 -+ -+#if TIMER_TICKS_PER_SEC > HZ -+#error TIMER_TICKS_PER_SEC is too high -+#endif -+ -+ -+typedef void (* TIMER_HANDLER)(void); -+ -+typedef struct { -+ struct list_head list; -+ unsigned long timeout; -+ unsigned long period; -+ TIMER_HANDLER handler; -+ char running; -+} TIMER_ENTRY; -+ -+ -+/** Initializes a timer structure. -+* Must be called once for each TIMER_ENTRY structure. -+* The caller must be holding the ctrl->mutex. -+* -+* @param timer pointer to the timer to be initialized -+* @param handler timer handler function pointer -+* -+*/ -+void timer_init(TIMER_ENTRY *timer, TIMER_HANDLER handler); -+ -+/** Adds a timer to the running timer list. -+* It's safe to call even if the timer was already running. In this case we just update the granularity. -+* The caller must be holding the ctrl->mutex. -+* -+* @param timer pointer to the timer to be added -+* @param granularity granularity of the timer (in timer tick units) -+* -+*/ -+void timer_add(TIMER_ENTRY *timer, u16 granularity); -+ -+/** Deletes a timer from the running timer list. -+* It's safe to call even if the timer is no longer running. -+* The caller must be holding the ctrl->mutex. -+* -+* @param timer pointer to the timer to be removed -+*/ -+void timer_del(TIMER_ENTRY *timer); -+ -+void *Heap_Alloc(int size); -+ -+#define Heap_Alloc_ARAM(s) Heap_Alloc(s) -+#define __Heap_Alloc(h, s) Heap_Alloc(s) -+void Heap_Free(void *p); -+ -+#endif /* _PFE_CTRL_HAL_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_debugfs.c -@@ -0,0 +1,109 @@ -+/* -+ * (C) Copyright 2013 -+ * Author : Freescale Technologes -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ * */ -+ -+#include -+#include -+#include -+ -+#include "pfe_mod.h" -+ -+static int dmem_show(struct seq_file *s, void *unused) -+{ -+ u32 dmem_addr, val; -+ int id = (long int)s->private; -+ int i; -+ -+ for (dmem_addr = 0; dmem_addr < CLASS_DMEM_SIZE; dmem_addr += 8 * 4) { -+ seq_printf(s, "%04x:", dmem_addr); -+ -+ for (i = 0; i < 8; i++) { -+ val = pe_dmem_read(id, dmem_addr + i * 4, 4); -+ seq_printf(s, " %02x %02x %02x %02x", val & 0xff, (val >> 8) & 0xff, (val >> 16) & 0xff, (val >> 24) & 0xff); -+ } -+ -+ seq_printf(s, "\n"); -+ } -+ -+ return 0; -+} -+ -+static int dmem_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, dmem_show, inode->i_private); -+} -+ -+static const struct file_operations dmem_fops = { -+ .open = dmem_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+int pfe_debugfs_init(struct pfe *pfe) -+{ -+ struct dentry *d; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ pfe->dentry = debugfs_create_dir("pfe", NULL); -+ if (IS_ERR_OR_NULL(pfe->dentry)) -+ goto err_dir; -+ -+ d = debugfs_create_file("pe0_dmem", S_IRUGO, pfe->dentry, (void *)0, &dmem_fops); -+ if (IS_ERR_OR_NULL(d)) -+ goto err_pe; -+ -+ d = debugfs_create_file("pe1_dmem", S_IRUGO, pfe->dentry, (void *)1, &dmem_fops); -+ if (IS_ERR_OR_NULL(d)) -+ goto err_pe; -+ -+ d = debugfs_create_file("pe2_dmem", S_IRUGO, pfe->dentry, (void *)2, &dmem_fops); -+ if (IS_ERR_OR_NULL(d)) -+ goto err_pe; -+ -+ d = debugfs_create_file("pe3_dmem", S_IRUGO, pfe->dentry, (void *)3, &dmem_fops); -+ if (IS_ERR_OR_NULL(d)) -+ goto err_pe; -+ -+ d = debugfs_create_file("pe4_dmem", S_IRUGO, pfe->dentry, (void *)4, &dmem_fops); -+ if (IS_ERR_OR_NULL(d)) -+ goto err_pe; -+ -+ d = debugfs_create_file("pe5_dmem", S_IRUGO, pfe->dentry, (void *)5, &dmem_fops); -+ if (IS_ERR_OR_NULL(d)) -+ goto err_pe; -+ -+ return 0; -+ -+err_pe: -+ debugfs_remove_recursive(pfe->dentry); -+ -+err_dir: -+ return -1; -+} -+ -+void pfe_debugfs_exit(struct pfe *pfe) -+{ -+ debugfs_remove_recursive(pfe->dentry); -+} -+ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_debugfs.h -@@ -0,0 +1,8 @@ -+#ifndef _PFE_DEBUGFS_H_ -+#define _PFE_DEBUGFS_H_ -+ -+int pfe_debugfs_init(struct pfe *pfe); -+void pfe_debugfs_exit(struct pfe *pfe); -+#endif /* _PFE_DEBUGFS_H_ */ -+ -+ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_eth.c -@@ -0,0 +1,2956 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+/** @pfe_eth.c. -+ * Ethernet driver for to handle exception path for PFE. -+ * - uses HIF functions to send/receive packets. -+ * - uses ctrl function to start/stop interfaces. -+ * - uses direct register accesses to control phy operation. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#if defined(CONFIG_NF_CONNTRACK_MARK) -+#include -+#endif -+ -+#include "pfe_mod.h" -+#include "pfe_eth.h" -+ -+const char comcerto_eth_driver_version[]="1.0"; -+static void *cbus_emac_base[3]; -+static void *cbus_gpi_base[3]; -+ -+/* Forward Declaration */ -+static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv); -+static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv, int force); -+static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int txQ_num, int from_tx, int n_desc); -+ -+#if defined(CONFIG_PLATFORM_C2000) -+static void pfe_eth_set_device_wakeup(struct pfe *pfe); -+ -+ -+ -+unsigned int gemac_regs[] = { -+ 0x0000, /* Network control */ -+ 0x0004, /* Network configuration */ -+ 0x0008, /* Network status */ -+ 0x0010, /* DMA configuration */ -+ 0x0014, /* Transmit status */ -+ 0x0020, /* Receive status */ -+ 0x0024, /* Interrupt status */ -+ 0x0030, /* Interrupt mask */ -+ 0x0038, /* Received pause quantum */ -+ 0x003c, /* Transmit pause quantum */ -+ 0x0080, /* Hash register bottom [31:0] */ -+ 0x0084, /* Hash register bottom [63:32] */ -+ 0x0088, /* Specific address 1 bottom [31:0] */ -+ 0x008c, /* Specific address 1 top [47:32] */ -+ 0x0090, /* Specific address 2 bottom [31:0] */ -+ 0x0094, /* Specific address 2 top [47:32] */ -+ 0x0098, /* Specific address 3 bottom [31:0] */ -+ 0x009c, /* Specific address 3 top [47:32] */ -+ 0x00a0, /* Specific address 4 bottom [31:0] */ -+ 0x00a4, /* Specific address 4 top [47:32] */ -+ 0x00a8, /* Type ID Match 1 */ -+ 0x00ac, /* Type ID Match 2 */ -+ 0x00b0, /* Type ID Match 3 */ -+ 0x00b4, /* Type ID Match 4 */ -+ 0x00b8, /* Wake Up ON LAN */ -+ 0x00bc, /* IPG stretch register */ -+ 0x00c0, /* Stacked VLAN Register */ -+ 0x00fc, /* Module ID */ -+ 0x07a0 /* EMAC Control register */ -+}; -+#else -+unsigned int gemac_regs[] = { -+ 0x0004, /*Interrupt event */ -+ 0x0008, /*Interrupt mask */ -+ 0x0024, /*Ethernet control */ -+ 0x0064, /*MIB Control/Status */ -+ 0x0084, /*Receive control/status */ -+ 0x00C4, /*Transmit control */ -+ 0x00E4, /*Physical address low */ -+ 0x00E8, /*Physical address high */ -+ 0x0144, /*Transmit FIFO Watermark and Store and Forward Control*/ -+ 0x0190, /* Receive FIFO Section Full Threshold */ -+ 0x01A0, /* Transmit FIFO Section Empty Threshold */ -+ 0x01B0, /* Frame Truncation Length */ -+}; -+#endif -+/********************************************************************/ -+/* SYSFS INTERFACE */ -+/********************************************************************/ -+ -+ -+ -+#ifdef PFE_ETH_NAPI_STATS -+/* -+ * pfe_eth_show_napi_stats -+ */ -+static ssize_t pfe_eth_show_napi_stats(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ ssize_t len = 0; -+ -+ len += sprintf(buf + len, "sched: %u\n", priv->napi_counters[NAPI_SCHED_COUNT]); -+ len += sprintf(buf + len, "poll: %u\n", priv->napi_counters[NAPI_POLL_COUNT]); -+ len += sprintf(buf + len, "packet: %u\n", priv->napi_counters[NAPI_PACKET_COUNT]); -+ len += sprintf(buf + len, "budget: %u\n", priv->napi_counters[NAPI_FULL_BUDGET_COUNT]); -+ len += sprintf(buf + len, "desc: %u\n", priv->napi_counters[NAPI_DESC_COUNT]); -+ -+ return len; -+} -+ -+/* -+ * pfe_eth_set_napi_stats -+ */ -+static ssize_t pfe_eth_set_napi_stats(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ -+ memset(priv->napi_counters, 0, sizeof(priv->napi_counters)); -+ -+ return count; -+} -+#endif -+#ifdef PFE_ETH_TX_STATS -+/** pfe_eth_show_tx_stats -+ * -+ */ -+static ssize_t pfe_eth_show_tx_stats(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ ssize_t len = 0; -+ int i; -+ -+ len += sprintf(buf + len, "TX queues stats:\n"); -+ -+ for (i = 0; i < emac_txq_cnt; i++) { -+ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->dev, i); -+ -+ len += sprintf(buf + len, "\n"); -+ __netif_tx_lock_bh(tx_queue); -+ -+ hif_tx_lock(&pfe->hif); -+ len += sprintf(buf + len, "Queue %2d : credits = %10d\n", i, hif_lib_tx_credit_avail(pfe, priv->id, i)); -+ len += sprintf(buf + len, " tx packets = %10d\n", pfe->tmu_credit.tx_packets[priv->id][i]); -+ hif_tx_unlock(&pfe->hif); -+ -+ /* Don't output additionnal stats if queue never used */ -+ if (!pfe->tmu_credit.tx_packets[priv->id][i]) -+ goto skip; -+ -+ len += sprintf(buf + len, " clean_fail = %10d\n", priv->clean_fail[i]); -+ len += sprintf(buf + len, " stop_queue = %10d\n", priv->stop_queue_total[i]); -+ len += sprintf(buf + len, " stop_queue_hif = %10d\n", priv->stop_queue_hif[i]); -+ len += sprintf(buf + len, " stop_queue_hif_client = %10d\n", priv->stop_queue_hif_client[i]); -+ len += sprintf(buf + len, " stop_queue_credit = %10d\n", priv->stop_queue_credit[i]); -+skip: -+ __netif_tx_unlock_bh(tx_queue); -+ } -+ return len; -+} -+ -+/** pfe_eth_set_tx_stats -+ * -+ */ -+static ssize_t pfe_eth_set_tx_stats(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ int i; -+ -+ for (i = 0; i < emac_txq_cnt; i++) { -+ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->dev, i); -+ -+ __netif_tx_lock_bh(tx_queue); -+ priv->clean_fail[i] = 0; -+ priv->stop_queue_total[i] = 0; -+ priv->stop_queue_hif[i] = 0; -+ priv->stop_queue_hif_client[i]= 0; -+ priv->stop_queue_credit[i] = 0; -+ __netif_tx_unlock_bh(tx_queue); -+ } -+ -+ return count; -+} -+#endif -+/** pfe_eth_show_txavail -+ * -+ */ -+static ssize_t pfe_eth_show_txavail(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ ssize_t len = 0; -+ int i; -+ -+ for (i = 0; i < emac_txq_cnt; i++) { -+ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->dev, i); -+ -+ __netif_tx_lock_bh(tx_queue); -+ -+ len += sprintf(buf + len, "%d", hif_lib_tx_avail(&priv->client, i)); -+ -+ __netif_tx_unlock_bh(tx_queue); -+ -+ if (i == (emac_txq_cnt - 1)) -+ len += sprintf(buf + len, "\n"); -+ else -+ len += sprintf(buf + len, " "); -+ } -+ -+ return len; -+} -+ -+ -+/** pfe_eth_show_default_priority -+ * -+ */ -+static ssize_t pfe_eth_show_default_priority(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ unsigned long flags; -+ int rc; -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ rc = sprintf(buf, "%d\n", priv->default_priority); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ -+ return rc; -+} -+ -+/** pfe_eth_set_default_priority -+ * -+ */ -+ -+static ssize_t pfe_eth_set_default_priority(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ priv->default_priority = simple_strtoul(buf, NULL, 0); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ -+ return count; -+} -+ -+static DEVICE_ATTR(txavail, 0444, pfe_eth_show_txavail, NULL); -+static DEVICE_ATTR(default_priority, 0644, pfe_eth_show_default_priority, pfe_eth_set_default_priority); -+ -+#ifdef PFE_ETH_NAPI_STATS -+static DEVICE_ATTR(napi_stats, 0644, pfe_eth_show_napi_stats, pfe_eth_set_napi_stats); -+#endif -+ -+#ifdef PFE_ETH_TX_STATS -+static DEVICE_ATTR(tx_stats, 0644, pfe_eth_show_tx_stats, pfe_eth_set_tx_stats); -+#endif -+ -+ -+/** pfe_eth_sysfs_init -+ * -+ */ -+static int pfe_eth_sysfs_init(struct net_device *dev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ int err; -+ -+ /* Initialize the default values */ -+ /* By default, packets without conntrack will use this default high priority queue */ -+ priv->default_priority = 15; -+ -+ /* Create our sysfs files */ -+ err = device_create_file(&dev->dev, &dev_attr_default_priority); -+ if (err) { -+ netdev_err(dev, "failed to create default_priority sysfs files\n"); -+ goto err_priority; -+ } -+ -+ err = device_create_file(&dev->dev, &dev_attr_txavail); -+ if (err) { -+ netdev_err(dev, "failed to create default_priority sysfs files\n"); -+ goto err_txavail; -+ } -+ -+#ifdef PFE_ETH_NAPI_STATS -+ err = device_create_file(&dev->dev, &dev_attr_napi_stats); -+ if (err) { -+ netdev_err(dev, "failed to create napi stats sysfs files\n"); -+ goto err_napi; -+ } -+#endif -+ -+#ifdef PFE_ETH_TX_STATS -+ err = device_create_file(&dev->dev, &dev_attr_tx_stats); -+ if (err) { -+ netdev_err(dev, "failed to create tx stats sysfs files\n"); -+ goto err_tx; -+ } -+#endif -+ -+ return 0; -+ -+#ifdef PFE_ETH_TX_STATS -+err_tx: -+#endif -+#ifdef PFE_ETH_NAPI_STATS -+ device_remove_file(&dev->dev, &dev_attr_napi_stats); -+ -+err_napi: -+#endif -+ device_remove_file(&dev->dev, &dev_attr_txavail); -+ -+err_txavail: -+ device_remove_file(&dev->dev, &dev_attr_default_priority); -+ -+err_priority: -+ return -1; -+} -+ -+/** pfe_eth_sysfs_exit -+ * -+ */ -+void pfe_eth_sysfs_exit(struct net_device *dev) -+{ -+#ifdef PFE_ETH_TX_STATS -+ device_remove_file(&dev->dev, &dev_attr_tx_stats); -+#endif -+ -+#ifdef PFE_ETH_NAPI_STATS -+ device_remove_file(&dev->dev, &dev_attr_napi_stats); -+#endif -+ device_remove_file(&dev->dev, &dev_attr_txavail); -+ device_remove_file(&dev->dev, &dev_attr_default_priority); -+} -+ -+/*************************************************************************/ -+/* ETHTOOL INTERCAE */ -+/*************************************************************************/ -+ -+#if defined(CONFIG_PLATFORM_C2000) -+static char stat_gstrings[][ETH_GSTRING_LEN] = { -+ "tx- octets", -+ "tx- packets", -+ "tx- broadcast", -+ "tx- multicast", -+ "tx- pause", -+ "tx- 64 bytes packets", -+ "tx- 64 - 127 bytes packets", -+ "tx- 128 - 255 bytes packets", -+ "tx- 256 - 511 bytes packets", -+ "tx- 512 - 1023 bytes packets", -+ "tx- 1024 - 1518 bytes packets", -+ "tx- > 1518 bytes packets", -+ "tx- underruns - errors", -+ "tx- single collision", -+ "tx- multi collision", -+ "tx- exces. collision - errors", -+ "tx- late collision - errors", -+ "tx- deferred", -+ "tx- carrier sense - errors", -+ "rx- octets", -+ "rx- packets", -+ "rx- broadcast", -+ "rx- multicast", -+ "rx- pause", -+ "rx- 64 bytes packets", -+ "rx- 64 - 127 bytes packets", -+ "rx- 128 - 255 bytes packets", -+ "rx- 256 - 511 bytes packets", -+ "rx- 512 - 1023 bytes packets", -+ "rx- 1024 - 1518 bytes packets", -+ "rx- > 1518 bytes packets", -+ "rx- undersize -errors", -+ "rx- oversize - errors ", -+ "rx- jabbers - errors", -+ "rx- fcs - errors", -+ "rx- length - errors", -+ "rx- symbol - errors", -+ "rx- align - errors", -+ "rx- ressource - errors", -+ "rx- overrun - errors", -+ "rx- IP cksum - errors", -+ "rx- TCP cksum - errors", -+ "rx- UDP cksum - errors" -+}; -+ -+ -+/** -+ * pfe_eth_gstrings - Fill in a buffer with the strings which correspond to -+ * the stats. -+ * -+ */ -+static void pfe_eth_gstrings(struct net_device *dev, u32 stringset, u8 * buf) -+{ -+ switch (stringset) { -+ case ETH_SS_STATS: -+ memcpy(buf, stat_gstrings, (EMAC_RMON_LEN - 2) * ETH_GSTRING_LEN); -+ break; -+ -+ default: -+ WARN_ON(1); -+ break; -+ } -+} -+ -+/** -+ * pfe_eth_fill_stats - Fill in an array of 64-bit statistics from -+ * various sources. This array will be appended -+ * to the end of the ethtool_stats* structure, and -+ * returned to user space -+ */ -+static void pfe_eth_fill_stats(struct net_device *dev, struct ethtool_stats *dummy, u64 * buf) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ int i; -+ for (i=0;iEMAC_baseaddr + EMAC_RMON_BASE_OFST + (i << 2)); -+ if ( ( i == EMAC_RMON_TXBYTES_POS ) || ( i == EMAC_RMON_RXBYTES_POS ) ){ -+ i++; -+ *buf |= (u64)readl(priv->EMAC_baseaddr + EMAC_RMON_BASE_OFST + (i << 2)) << 32; -+ } -+ } -+ -+} -+ -+/** -+ * pfe_eth_stats_count - Returns the number of stats (and their corresponding strings) -+ * -+ */ -+static int pfe_eth_stats_count(struct net_device *dev, int sset) -+{ -+ switch (sset) { -+ case ETH_SS_STATS: -+ return EMAC_RMON_LEN - 2; -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+#if defined(CONFIG_PLATFORM_C2000) -+/** -+ * pfe_eth_set_wol - Set the magic packet option, in WoL register. -+ * -+ */ -+static int pfe_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ -+ if (wol->wolopts & ~(WAKE_MAGIC | WAKE_ARP | WAKE_MCAST | WAKE_UCAST)) -+ return -EOPNOTSUPP; -+ -+ priv->wol = 0; -+ -+ if (wol->wolopts & WAKE_MAGIC) -+ priv->wol |= EMAC_WOL_MAGIC; -+ if (wol->wolopts & WAKE_ARP) -+ priv->wol |= EMAC_WOL_ARP; -+ if (wol->wolopts & WAKE_MCAST) -+ priv->wol |= EMAC_WOL_MULTI; -+ if (wol->wolopts & WAKE_UCAST) -+ priv->wol |= EMAC_WOL_SPEC_ADDR; -+ -+ pfe_eth_set_device_wakeup(priv->pfe); -+ -+ return 0; -+} -+ -+/** -+ * -+ * pfe_eth_get_wol - Get the WoL options. -+ * -+ */ -+static void pfe_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ -+ wol->supported = (WAKE_MAGIC | WAKE_ARP | WAKE_MCAST | WAKE_UCAST); -+ wol->wolopts = 0; -+ -+ if(priv->wol & EMAC_WOL_MAGIC) -+ wol->wolopts |= WAKE_MAGIC; -+ if(priv->wol & EMAC_WOL_ARP) -+ wol->wolopts |= WAKE_ARP; -+ if(priv->wol & EMAC_WOL_MULTI) -+ wol->wolopts |= WAKE_UCAST; -+ if(priv->wol & EMAC_WOL_SPEC_ADDR) -+ wol->wolopts |= WAKE_UCAST; -+ -+ memset(&wol->sopass, 0, sizeof(wol->sopass)); -+} -+#endif -+/** -+ * pfe_eth_gemac_reglen - Return the length of the register structure. -+ * -+ */ -+static int pfe_eth_gemac_reglen(struct net_device *dev) -+{ -+ return (sizeof (gemac_regs)/ sizeof(u32)) + (( MAX_UC_SPEC_ADDR_REG - 3 ) * 2); -+} -+ -+/** -+ * pfe_eth_gemac_get_regs - Return the gemac register structure. -+ * -+ */ -+static void pfe_eth_gemac_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf) -+{ -+ int i,j; -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ u32 *buf = (u32 *) regbuf; -+ -+ for (i = 0; i < sizeof (gemac_regs) / sizeof (u32); i++) -+ buf[i] = readl( priv->EMAC_baseaddr + gemac_regs[i] ); -+ -+ for (j = 0; j < (( MAX_UC_SPEC_ADDR_REG - 3 ) * 2); j++,i++) -+ buf[i] = readl( priv->EMAC_baseaddr + EMAC_SPEC5_ADD_BOT + (j<<2) ); -+ -+} -+ -+ -+#else //if defined(CONFIG_PLATFORM_C2000) -+/*MTIP GEMAC */ -+static const struct fec_stat { -+ char name[ETH_GSTRING_LEN]; -+ u16 offset; -+} fec_stats[] = { -+ /* RMON TX */ -+ { "tx_dropped", RMON_T_DROP }, -+ { "tx_packets", RMON_T_PACKETS }, -+ { "tx_broadcast", RMON_T_BC_PKT }, -+ { "tx_multicast", RMON_T_MC_PKT }, -+ { "tx_crc_errors", RMON_T_CRC_ALIGN }, -+ { "tx_undersize", RMON_T_UNDERSIZE }, -+ { "tx_oversize", RMON_T_OVERSIZE }, -+ { "tx_fragment", RMON_T_FRAG }, -+ { "tx_jabber", RMON_T_JAB }, -+ { "tx_collision", RMON_T_COL }, -+ { "tx_64byte", RMON_T_P64 }, -+ { "tx_65to127byte", RMON_T_P65TO127 }, -+ { "tx_128to255byte", RMON_T_P128TO255 }, -+ { "tx_256to511byte", RMON_T_P256TO511 }, -+ { "tx_512to1023byte", RMON_T_P512TO1023 }, -+ { "tx_1024to2047byte", RMON_T_P1024TO2047 }, -+ { "tx_GTE2048byte", RMON_T_P_GTE2048 }, -+ { "tx_octets", RMON_T_OCTETS }, -+ -+ /* IEEE TX */ -+ { "IEEE_tx_drop", IEEE_T_DROP }, -+ { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, -+ { "IEEE_tx_1col", IEEE_T_1COL }, -+ { "IEEE_tx_mcol", IEEE_T_MCOL }, -+ { "IEEE_tx_def", IEEE_T_DEF }, -+ { "IEEE_tx_lcol", IEEE_T_LCOL }, -+ { "IEEE_tx_excol", IEEE_T_EXCOL }, -+ { "IEEE_tx_macerr", IEEE_T_MACERR }, -+ { "IEEE_tx_cserr", IEEE_T_CSERR }, -+ { "IEEE_tx_sqe", IEEE_T_SQE }, -+ { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, -+ { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, -+ -+ /* RMON RX */ -+ { "rx_packets", RMON_R_PACKETS }, -+ { "rx_broadcast", RMON_R_BC_PKT }, -+ { "rx_multicast", RMON_R_MC_PKT }, -+ { "rx_crc_errors", RMON_R_CRC_ALIGN }, -+ { "rx_undersize", RMON_R_UNDERSIZE }, -+ { "rx_oversize", RMON_R_OVERSIZE }, -+ { "rx_fragment", RMON_R_FRAG }, -+ { "rx_jabber", RMON_R_JAB }, -+ { "rx_64byte", RMON_R_P64 }, -+ { "rx_65to127byte", RMON_R_P65TO127 }, -+ { "rx_128to255byte", RMON_R_P128TO255 }, -+ { "rx_256to511byte", RMON_R_P256TO511 }, -+ { "rx_512to1023byte", RMON_R_P512TO1023 }, -+ { "rx_1024to2047byte", RMON_R_P1024TO2047 }, -+ { "rx_GTE2048byte", RMON_R_P_GTE2048 }, -+ { "rx_octets", RMON_R_OCTETS }, -+ -+ /* IEEE RX */ -+ { "IEEE_rx_drop", IEEE_R_DROP }, -+ { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, -+ { "IEEE_rx_crc", IEEE_R_CRC }, -+ { "IEEE_rx_align", IEEE_R_ALIGN }, -+ { "IEEE_rx_macerr", IEEE_R_MACERR }, -+ { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, -+ { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, -+}; -+ -+static void pfe_eth_fill_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(fec_stats); i++) -+ data[i] = readl(priv->EMAC_baseaddr + fec_stats[i].offset); -+} -+ -+static void pfe_eth_gstrings(struct net_device *netdev, -+ u32 stringset, u8 *data) -+{ -+ int i; -+ switch (stringset) { -+ case ETH_SS_STATS: -+ for (i = 0; i < ARRAY_SIZE(fec_stats); i++) -+ memcpy(data + i * ETH_GSTRING_LEN, -+ fec_stats[i].name, ETH_GSTRING_LEN); -+ break; -+ } -+} -+ -+static int pfe_eth_stats_count(struct net_device *dev, int sset) -+{ -+ switch (sset) { -+ case ETH_SS_STATS: -+ return ARRAY_SIZE(fec_stats); -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+/** -+ * pfe_eth_gemac_reglen - Return the length of the register structure. -+ * -+ */ -+static int pfe_eth_gemac_reglen(struct net_device *dev) -+{ -+ printk("%s() \n", __func__); -+ return (sizeof (gemac_regs)/ sizeof(u32)) ; -+} -+ -+/** -+ * pfe_eth_gemac_get_regs - Return the gemac register structure. -+ * -+ */ -+static void pfe_eth_gemac_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf) -+{ -+ int i; -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ u32 *buf = (u32 *) regbuf; -+ -+ printk("%s() \n", __func__); -+ for (i = 0; i < sizeof (gemac_regs) / sizeof (u32); i++) -+ buf[i] = readl( priv->EMAC_baseaddr + gemac_regs[i] ); -+ -+} -+ -+ -+#endif -+ -+/** -+ * pfe_eth_get_drvinfo - Fills in the drvinfo structure with some basic info -+ * -+ */ -+static void pfe_eth_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) -+{ -+ strncpy(drvinfo->driver, DRV_NAME, COMCERTO_INFOSTR_LEN); -+ strncpy(drvinfo->version, comcerto_eth_driver_version, COMCERTO_INFOSTR_LEN); -+ strncpy(drvinfo->fw_version, "N/A", COMCERTO_INFOSTR_LEN); -+ strncpy(drvinfo->bus_info, "N/A", COMCERTO_INFOSTR_LEN); -+ drvinfo->testinfo_len = 0; -+ drvinfo->regdump_len = 0; -+ drvinfo->eedump_len = 0; -+} -+ -+/** -+ * pfe_eth_set_settings - Used to send commands to PHY. -+ * -+ */ -+ -+static int pfe_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ struct phy_device *phydev = priv->phydev; -+ -+ if (NULL == phydev) -+ return -ENODEV; -+ -+ return phy_ethtool_sset(phydev, cmd); -+} -+ -+ -+/** -+ * pfe_eth_getsettings - Return the current settings in the ethtool_cmd structure. -+ * -+ */ -+static int pfe_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ struct phy_device *phydev = priv->phydev; -+ -+ if (NULL == phydev) -+ return -ENODEV; -+ -+ return phy_ethtool_gset(phydev, cmd); -+} -+ -+ -+/** -+ * pfe_eth_get_msglevel - Gets the debug message mask. -+ * -+ */ -+static uint32_t pfe_eth_get_msglevel(struct net_device *dev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ -+ return priv->msg_enable; -+} -+ -+/** -+ * pfe_eth_set_msglevel - Sets the debug message mask. -+ * -+ */ -+static void pfe_eth_set_msglevel(struct net_device *dev, uint32_t data) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ -+ priv->msg_enable = data; -+} -+ -+#define HIF_RX_COAL_MAX_CLKS (~(1<<31)) -+#define HIF_RX_COAL_CLKS_PER_USEC (pfe->ctrl.sys_clk/1000) -+#define HIF_RX_COAL_MAX_USECS (HIF_RX_COAL_MAX_CLKS/HIF_RX_COAL_CLKS_PER_USEC) -+ -+/** -+ * pfe_eth_set_coalesce - Sets rx interrupt coalescing timer. -+ * -+ */ -+static int pfe_eth_set_coalesce(struct net_device *dev, -+ struct ethtool_coalesce *ec) -+{ -+ if (ec->rx_coalesce_usecs > HIF_RX_COAL_MAX_USECS) -+ return -EINVAL; -+ -+ if (!ec->rx_coalesce_usecs) { -+ writel(0, HIF_INT_COAL); -+ return 0; -+ } -+ -+ writel((ec->rx_coalesce_usecs * HIF_RX_COAL_CLKS_PER_USEC) | HIF_INT_COAL_ENABLE, HIF_INT_COAL); -+ -+ return 0; -+} -+ -+/** -+ * pfe_eth_get_coalesce - Gets rx interrupt coalescing timer value. -+ * -+ */ -+static int pfe_eth_get_coalesce(struct net_device *dev, -+ struct ethtool_coalesce *ec) -+{ -+ int reg_val = readl(HIF_INT_COAL); -+ -+ if (reg_val & HIF_INT_COAL_ENABLE) -+ ec->rx_coalesce_usecs = (reg_val & HIF_RX_COAL_MAX_CLKS) / HIF_RX_COAL_CLKS_PER_USEC; -+ else -+ ec->rx_coalesce_usecs = 0; -+ -+ return 0; -+} -+ -+#if defined(CONFIG_PLATFORM_C2000) -+/** -+ * pfe_eth_pause_rx_enabled - Tests if pause rx is enabled on GEM -+ * -+ */ -+static int pfe_eth_pause_rx_enabled(struct pfe_eth_priv_s *priv) -+{ -+ return (readl(priv->EMAC_baseaddr + EMAC_NETWORK_CONFIG) & EMAC_ENABLE_PAUSE_RX) != 0; -+} -+ -+/** -+ * pfe_eth_set_pauseparam - Sets pause parameters -+ * -+ */ -+static int pfe_eth_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ -+ if (epause->rx_pause) -+ { -+ gemac_enable_pause_rx(priv->EMAC_baseaddr); -+ if (priv->phydev) -+ priv->phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; -+ } -+ else -+ { -+ gemac_disable_pause_rx(priv->EMAC_baseaddr); -+ if (priv->phydev) -+ priv->phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); -+ } -+ -+ return 0; -+} -+ -+/** -+ * pfe_eth_get_pauseparam - Gets pause parameters -+ * -+ */ -+static void pfe_eth_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ -+ epause->autoneg = 0; -+ epause->tx_pause = 0; -+ epause->rx_pause = pfe_eth_pause_rx_enabled(priv); -+} -+ -+/** pfe_eth_get_hash -+ */ -+static int pfe_eth_get_hash(u8 * addr) -+{ -+ u8 temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8; -+ temp1 = addr[0] & 0x3F ; -+ temp2 = ((addr[0] & 0xC0) >> 6)| ((addr[1] & 0x0F) << 2); -+ temp3 = ((addr[1] & 0xF0) >> 4) | ((addr[2] & 0x03) << 4); -+ temp4 = (addr[2] & 0xFC) >> 2; -+ temp5 = addr[3] & 0x3F; -+ temp6 = ((addr[3] & 0xC0) >> 6) | ((addr[4] & 0x0F) << 2); -+ temp7 = ((addr[4] & 0xF0) >>4 ) | ((addr[5] & 0x03) << 4); -+ temp8 = ((addr[5] &0xFC) >> 2); -+ return (temp1 ^ temp2 ^ temp3 ^ temp4 ^ temp5 ^ temp6 ^ temp7 ^ temp8); -+} -+ -+#else -+ /*TODO Add pause frame support for LS1012A */ -+ -+/** pfe_eth_get_hash -+ */ -+#define HASH_BITS 6 /* #bits in hash */ -+#define CRC32_POLY 0xEDB88320 -+ -+static int pfe_eth_get_hash(u8 * addr) -+{ -+ unsigned int i, bit, data, crc, hash; -+ -+ /* calculate crc32 value of mac address */ -+ crc = 0xffffffff; -+ -+ for (i = 0; i < 6; i++) { -+ data = addr[i]; -+ for (bit = 0; bit < 8; bit++, data >>= 1) { -+ crc = (crc >> 1) ^ -+ (((crc ^ data) & 1) ? CRC32_POLY : 0); -+ } -+ } -+ -+ /* only upper 6 bits (HASH_BITS) are used -+ * which point to specific bit in he hash registers -+ */ -+ hash = (crc >> (32 - HASH_BITS)) & 0x3f; -+ -+ return hash; -+} -+ -+#endif -+ -+struct ethtool_ops pfe_ethtool_ops = { -+ .get_settings = pfe_eth_get_settings, -+ .set_settings = pfe_eth_set_settings, -+ .get_drvinfo = pfe_eth_get_drvinfo, -+ .get_regs_len = pfe_eth_gemac_reglen, -+ .get_regs = pfe_eth_gemac_get_regs, -+ .get_link = ethtool_op_get_link, -+#if defined(CONFIG_PLATFORM_C2000) -+ .get_wol = pfe_eth_get_wol, -+ .set_wol = pfe_eth_set_wol, -+ .set_pauseparam = pfe_eth_set_pauseparam, -+ .get_pauseparam = pfe_eth_get_pauseparam, -+#endif -+ .get_strings = pfe_eth_gstrings, -+ .get_sset_count = pfe_eth_stats_count, -+ .get_ethtool_stats = pfe_eth_fill_stats, -+ .get_msglevel = pfe_eth_get_msglevel, -+ .set_msglevel = pfe_eth_set_msglevel, -+ .set_coalesce = pfe_eth_set_coalesce, -+ .get_coalesce = pfe_eth_get_coalesce, -+}; -+ -+ -+ -+#if defined(CONFIG_PLATFORM_C2000) -+/** pfe_eth_mdio_reset -+ */ -+int pfe_eth_mdio_reset(struct mii_bus *bus) -+{ -+ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)bus->priv; -+ -+ netif_info(priv, hw, priv->dev, "%s\n", __func__); -+ -+#if !defined(CONFIG_PLATFORM_EMULATION) -+ mutex_lock(&bus->mdio_lock); -+ -+ /* Setup the MII Mgmt clock speed */ -+ if (priv->mii_bus) -+ gemac_set_mdc_div(priv->EMAC_baseaddr, priv->mdc_div); -+ -+ /* Reset the management interface */ -+ __raw_writel(__raw_readl(priv->EMAC_baseaddr + EMAC_NETWORK_CONTROL) | EMAC_MDIO_EN, -+ priv->EMAC_baseaddr + EMAC_NETWORK_CONTROL); -+ -+ /* Wait until the bus is free */ -+ while(!(__raw_readl(priv->EMAC_baseaddr + EMAC_NETWORK_STATUS) & EMAC_PHY_IDLE)); -+ -+ mutex_unlock(&bus->mdio_lock); -+#endif -+ -+ return 0; -+} -+ -+ -+/** pfe_eth_gemac_phy_timeout -+ * -+ */ -+static int pfe_eth_gemac_phy_timeout(struct pfe_eth_priv_s *priv, int timeout) -+{ -+ while(!(__raw_readl(priv->EMAC_baseaddr + EMAC_NETWORK_STATUS) & EMAC_PHY_IDLE)) { -+ -+ if (timeout-- <= 0) { -+ return -1; -+ } -+ -+ udelay(10); -+ } -+ -+ return 0; -+} -+ -+ -+/** pfe_eth_mdio_write -+ */ -+static int pfe_eth_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value) -+{ -+ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)bus->priv; -+ u32 write_data; -+ -+#if !defined(CONFIG_PLATFORM_EMULATION) -+ -+ netif_info(priv, hw, priv->dev, "%s: phy %d\n", __func__, mii_id); -+ -+// netif_info(priv, hw, priv->dev, "%s %d %d %x\n", bus->id, mii_id, regnum, value); -+ -+ write_data = 0x50020000; -+ write_data |= ((mii_id << 23) | (regnum << 18) | value); -+ __raw_writel(write_data, priv->EMAC_baseaddr + EMAC_PHY_MANAGEMENT); -+ -+ if (pfe_eth_gemac_phy_timeout(priv, EMAC_MDIO_TIMEOUT)){ -+ netdev_err(priv->dev, "%s: phy MDIO write timeout\n", __func__); -+ return -1; -+ } -+ -+#endif -+ -+ return 0; -+} -+ -+ -+/** pfe_eth_mdio_read -+ */ -+static int pfe_eth_mdio_read(struct mii_bus *bus, int mii_id, int regnum) -+{ -+ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)bus->priv; -+ u16 value = 0; -+ u32 write_data; -+ -+#if !defined(CONFIG_PLATFORM_EMULATION) -+ netif_info(priv, hw, priv->dev, "%s: phy %d\n", __func__, mii_id); -+ -+ write_data = 0x60020000; -+ write_data |= ((mii_id << 23) | (regnum << 18)); -+ -+ __raw_writel(write_data, priv->EMAC_baseaddr + EMAC_PHY_MANAGEMENT); -+ -+ if (pfe_eth_gemac_phy_timeout( priv, EMAC_MDIO_TIMEOUT)) { -+ netdev_err(priv->dev, "%s: phy MDIO read timeout\n", __func__); -+ return -1; -+ } -+ -+ value = __raw_readl(priv->EMAC_baseaddr + EMAC_PHY_MANAGEMENT) & 0xFFFF; -+#endif -+ -+// netif_info(priv, hw, priv->dev, "%s %d %d %x\n", bus->id, mii_id, regnum, value); -+ -+ return value; -+} -+ -+#else -+/** pfe_eth_mdio_reset -+ */ -+int pfe_eth_mdio_reset(struct mii_bus *bus) -+{ -+ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)bus->priv; -+ u32 phy_speed, pclk = 250000000; /*TODO this needs to be checked read from the correct source*/ -+ -+ netif_info(priv, hw, priv->dev, "%s\n", __func__); -+ -+ mutex_lock(&bus->mdio_lock); -+ -+ /* -+ * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) -+ * -+ * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while -+ * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. -+ */ -+ phy_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT); -+ phy_speed |= EMAC_HOLDTIME(0x5); -+ __raw_writel(phy_speed, priv->PHY_baseaddr + EMAC_MII_CTRL_REG); -+ -+ mutex_unlock(&bus->mdio_lock); -+ -+ return 0; -+} -+ -+/** pfe_eth_gemac_phy_timeout -+ * -+ */ -+static int pfe_eth_gemac_phy_timeout(struct pfe_eth_priv_s *priv, int timeout) -+{ -+ while(!(__raw_readl(priv->PHY_baseaddr + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) { -+ -+ if (timeout-- <= 0) { -+ return -1; -+ } -+ -+ udelay(10); -+ } -+ __raw_writel(EMAC_IEVENT_MII, priv->PHY_baseaddr + EMAC_IEVENT_REG); -+ -+ return 0; -+} -+ -+static int pfe_eth_mdio_mux(u8 muxval) -+{ -+ struct i2c_adapter *a; -+ struct i2c_msg msg; -+ unsigned char buf[2]; -+ int ret; -+ -+ a = i2c_get_adapter(0); -+ if (!a) -+ return -ENODEV; -+ -+ /* set bit 1 (the second bit) of chip at 0x09, register 0x13 */ -+ buf[0] = 0x54; //reg number -+ buf[1] = (muxval << 6)| 0x3; //data -+ msg.addr = 0x66; -+ msg.buf = buf; -+ msg.len = 2; -+ msg.flags = 0; -+ ret = i2c_transfer(a, &msg, 1); -+ i2c_put_adapter(a); -+ if (ret != 1) -+ return -ENODEV; -+ return 0; -+ -+ -+} -+ -+static int pfe_eth_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value) -+{ -+ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)bus->priv; -+ -+ /*FIXME Dirty hack to configure mux */ -+ if(priv->mdio_muxval) { -+ if(mii_id == 0x1) -+ pfe_eth_mdio_mux(0x1); -+ else -+ pfe_eth_mdio_mux(0x2); -+ } -+ -+ /* start a write op */ -+ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | -+ EMAC_MII_DATA_PA(mii_id) | EMAC_MII_DATA_RA(regnum) | -+ EMAC_MII_DATA_TA | EMAC_MII_DATA(value), -+ priv->PHY_baseaddr + EMAC_MII_DATA_REG); -+ -+ if (pfe_eth_gemac_phy_timeout(priv, EMAC_MDIO_TIMEOUT)){ -+ netdev_err(priv->dev, "%s: phy MDIO write timeout\n", __func__); -+ return -1; -+ } -+ netif_info(priv, hw, priv->dev, "%s: phy %x reg %x val %x\n", __func__, mii_id, regnum, value); -+ -+ return 0; -+ -+ -+} -+static int pfe_eth_mdio_read(struct mii_bus *bus, int mii_id, int regnum) -+{ -+ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)bus->priv; -+ u16 value = 0; -+ -+ /*FIXME Dirty hack to configure mux */ -+ if(priv->mdio_muxval){ -+ if(mii_id == 0x1) -+ pfe_eth_mdio_mux(0x1); -+ else -+ pfe_eth_mdio_mux(0x2); -+ } -+ -+ /* start a read op */ -+ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | -+ EMAC_MII_DATA_PA(mii_id) | EMAC_MII_DATA_RA(regnum) | -+ EMAC_MII_DATA_TA, priv->PHY_baseaddr + EMAC_MII_DATA_REG); -+ -+ if (pfe_eth_gemac_phy_timeout( priv, EMAC_MDIO_TIMEOUT)) { -+ netdev_err(priv->dev, "%s: phy MDIO read timeout\n", __func__); -+ return -1; -+ } -+ -+ value = EMAC_MII_DATA(__raw_readl(priv->PHY_baseaddr + EMAC_MII_DATA_REG)); -+ netif_info(priv, hw, priv->dev, "%s: phy %x reg %x val %x\n", __func__, mii_id, regnum, value); -+ return value; -+} -+#endif -+static int pfe_eth_mdio_init(struct pfe_eth_priv_s *priv, struct comcerto_mdio_platform_data *minfo) -+{ -+ struct mii_bus *bus; -+ int rc; -+ -+ netif_info(priv, drv, priv->dev, "%s\n", __func__); -+ printk( "%s\n", __func__); -+ -+#if !defined(CONFIG_PLATFORM_EMULATION) -+ bus = mdiobus_alloc(); -+ if (!bus) { -+ netdev_err(priv->dev, "mdiobus_alloc() failed\n"); -+ rc = -ENOMEM; -+ goto err0; -+ } -+ -+ bus->name = "Comcerto MDIO Bus"; -+ bus->read = &pfe_eth_mdio_read; -+ bus->write = &pfe_eth_mdio_write; -+ bus->reset = &pfe_eth_mdio_reset; -+ snprintf(bus->id, MII_BUS_ID_SIZE, "comcerto-%x", priv->id); -+ bus->priv = priv; -+ -+ bus->phy_mask = minfo->phy_mask; -+ priv->mdc_div = minfo->mdc_div; -+ -+ if (!priv->mdc_div) -+ priv->mdc_div = 64; -+ -+ bus->irq = minfo->irq; -+ -+ bus->parent = priv->pfe->dev; -+ -+ netif_info(priv, drv, priv->dev, "%s: mdc_div: %d, phy_mask: %x \n", __func__, priv->mdc_div, bus->phy_mask); -+ rc = mdiobus_register(bus); -+ if (rc) { -+ netdev_err(priv->dev, "mdiobus_register(%s) failed\n", bus->name); -+ goto err1; -+ } -+ -+ priv->mii_bus = bus; -+ pfe_eth_mdio_reset(bus); -+ -+ return 0; -+ -+err1: -+ mdiobus_free(bus); -+err0: -+ return rc; -+#else -+ return 0; -+#endif -+ -+} -+ -+/** pfe_eth_mdio_exit -+ */ -+static void pfe_eth_mdio_exit(struct mii_bus *bus) -+{ -+ if (!bus) -+ return; -+ -+ netif_info((struct pfe_eth_priv_s *)bus->priv, drv, ((struct pfe_eth_priv_s *)(bus->priv))->dev, "%s\n", __func__); -+ -+ mdiobus_unregister(bus); -+ mdiobus_free(bus); -+} -+ -+#if defined(CONFIG_PLATFORM_C2000) -+/** pfe_get_interface -+ */ -+static phy_interface_t pfe_get_interface(struct net_device *dev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ u32 mii_mode = priv->einfo->mii_config; -+ -+ netif_info(priv, drv, dev, "%s\n", __func__); -+ -+ if (priv->einfo->gemac_mode & (GEMAC_SW_CONF)) { -+ switch (mii_mode) { -+ case CONFIG_COMCERTO_USE_GMII: -+ return PHY_INTERFACE_MODE_GMII; -+ break; -+ case CONFIG_COMCERTO_USE_RGMII: -+ return PHY_INTERFACE_MODE_RGMII; -+ break; -+ case CONFIG_COMCERTO_USE_RMII: -+ return PHY_INTERFACE_MODE_RMII; -+ break; -+ case CONFIG_COMCERTO_USE_SGMII: -+ return PHY_INTERFACE_MODE_SGMII; -+ break; -+ -+ default : -+ case CONFIG_COMCERTO_USE_MII: -+ return PHY_INTERFACE_MODE_MII; -+ break; -+ -+ } -+ } else { -+ // Bootstrap config read from controller -+ BUG(); -+ return 0; -+ } -+} -+#endif -+ -+/** pfe_get_phydev_speed -+ */ -+static int pfe_get_phydev_speed(struct phy_device *phydev) -+{ -+ switch (phydev->speed) { -+ case 10: -+ return SPEED_10M; -+ case 100: -+ return SPEED_100M; -+ case 1000: -+ default: -+ return SPEED_1000M; -+ } -+ -+} -+ -+/** pfe_set_rgmii_speed -+ */ -+#define RGMIIPCR 0x434 -+/* RGMIIPCR bit definitions*/ -+#define SCFG_RGMIIPCR_EN_AUTO (0x00000008) -+#define SCFG_RGMIIPCR_SETSP_1000M (0x00000004) -+#define SCFG_RGMIIPCR_SETSP_100M (0x00000000) -+#define SCFG_RGMIIPCR_SETSP_10M (0x00000002) -+#define SCFG_RGMIIPCR_SETFD (0x00000001) -+ -+static void pfe_set_rgmii_speed(struct phy_device *phydev) -+{ -+ u32 rgmii_pcr; -+ -+ regmap_read(pfe->scfg, RGMIIPCR, &rgmii_pcr); -+ rgmii_pcr &= ~(SCFG_RGMIIPCR_SETSP_1000M|SCFG_RGMIIPCR_SETSP_10M); -+ -+ switch (phydev->speed) { -+ case 10: -+ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M; -+ break; -+ case 1000: -+ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M; -+ break; -+ case 100: -+ default: -+ /* Default is 100M */ -+ break; -+ } -+ regmap_write(pfe->scfg, RGMIIPCR, rgmii_pcr); -+ -+ -+} -+/** pfe_get_phydev_duplex -+ */ -+static int pfe_get_phydev_duplex(struct phy_device *phydev) -+{ -+ //return ( phydev->duplex == DUPLEX_HALF ) ? DUP_HALF:DUP_FULL ; -+ return DUPLEX_FULL; -+} -+ -+/** pfe_eth_adjust_link -+ */ -+static void pfe_eth_adjust_link(struct net_device *dev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ unsigned long flags; -+ struct phy_device *phydev = priv->phydev; -+ int new_state = 0; -+ -+ netif_info(priv, drv, dev, "%s\n", __func__); -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ if (phydev->link) { -+ /* Now we make sure that we can be in full duplex mode. -+ * If not, we operate in half-duplex mode. */ -+ if (phydev->duplex != priv->oldduplex) { -+ new_state = 1; -+ gemac_set_duplex(priv->EMAC_baseaddr, pfe_get_phydev_duplex(phydev)); -+ priv->oldduplex = phydev->duplex; -+ } -+ -+ if (phydev->speed != priv->oldspeed) { -+ new_state = 1; -+ gemac_set_speed(priv->EMAC_baseaddr, pfe_get_phydev_speed(phydev)); -+ if(priv->einfo->mii_config == PHY_INTERFACE_MODE_RGMII) -+ pfe_set_rgmii_speed(phydev); -+ priv->oldspeed = phydev->speed; -+ } -+ -+ if (!priv->oldlink) { -+ new_state = 1; -+ priv->oldlink = 1; -+ } -+ -+ } else if (priv->oldlink) { -+ new_state = 1; -+ priv->oldlink = 0; -+ priv->oldspeed = 0; -+ priv->oldduplex = -1; -+ } -+ -+ if (new_state && netif_msg_link(priv)) -+ phy_print_status(phydev); -+ -+ spin_unlock_irqrestore(&priv->lock, flags); -+} -+ -+ -+/** pfe_phy_exit -+ */ -+static void pfe_phy_exit(struct net_device *dev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ -+ netif_info(priv, drv, dev, "%s\n", __func__); -+ -+ phy_disconnect(priv->phydev); -+ priv->phydev = NULL; -+} -+ -+/** pfe_eth_stop -+ */ -+static void pfe_eth_stop( struct net_device *dev , int wake) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ -+ netif_info(priv, drv, dev, "%s\n", __func__); -+ -+ if (wake) -+ gemac_tx_disable(priv->EMAC_baseaddr); -+ else { -+ gemac_disable(priv->EMAC_baseaddr); -+ gpi_disable(priv->GPI_baseaddr); -+ -+ if (priv->phydev) -+ phy_stop(priv->phydev); -+ } -+} -+ -+/** pfe_eth_start -+ */ -+static int pfe_eth_start( struct pfe_eth_priv_s *priv ) -+{ -+ netif_info(priv, drv, priv->dev, "%s\n", __func__); -+ -+ if (priv->phydev) -+ phy_start(priv->phydev); -+ -+ gpi_enable(priv->GPI_baseaddr); -+ gemac_enable(priv->EMAC_baseaddr); -+ -+ return 0; -+} -+ -+/*Configure on chip serdes through mdio -+ * Is there any better way to do this? */ -+static void ls1012a_configure_serdes(struct net_device *dev) -+{ -+ struct pfe_eth_priv_s *priv = pfe->eth.eth_priv[0]; // FIXME This will not work for EMAC2 as SGMII -+ /*int value,sgmii_2500=0; */ -+ struct mii_bus *bus = priv->mii_bus; -+ -+ netif_info(priv, drv, dev, "%s\n", __func__); -+ /* PCS configuration done with corresponding GEMAC */ -+ -+ pfe_eth_mdio_read(bus, 0, 0); -+ pfe_eth_mdio_read(bus, 0, 1); -+#if 1 -+ /*These settings taken from validtion team */ -+ pfe_eth_mdio_write(bus, 0, 0x0, 0x8000); -+ pfe_eth_mdio_write(bus, 0, 0x14, 0xb); -+ pfe_eth_mdio_write(bus, 0, 0x4, 0x1a1); -+ pfe_eth_mdio_write(bus, 0, 0x12, 0x400); -+ pfe_eth_mdio_write(bus, 0, 0x13, 0x0); -+ pfe_eth_mdio_write(bus, 0, 0x0, 0x1140); -+ return; -+#else -+ /*Reset serdes */ -+ pfe_eth_mdio_write(bus, 0, 0x0, 0x8000); -+ -+ /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */ -+ value = PHY_SGMII_IF_MODE_SGMII; -+ if (!sgmii_2500) -+ value |= PHY_SGMII_IF_MODE_AN; -+ -+ pfe_eth_mdio_write(bus, 0, 0x14, value); -+ -+ /* Dev ability according to SGMII specification */ -+ value = PHY_SGMII_DEV_ABILITY_SGMII; -+ pfe_eth_mdio_write(bus, 0, 0x4, value); -+ -+ //These values taken from validation team -+ pfe_eth_mdio_write(bus, 0, 0x13, 0x0); -+ pfe_eth_mdio_write(bus, 0, 0x12, 0x400); -+ -+ /* Restart AN */ -+ value = PHY_SGMII_CR_DEF_VAL; -+ if (!sgmii_2500) -+ value |= PHY_SGMII_CR_RESET_AN; -+ pfe_eth_mdio_write(bus, 0, 0, value); -+ -+#endif -+} -+ -+/** pfe_phy_init -+ * -+ */ -+static int pfe_phy_init(struct net_device *dev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ struct phy_device *phydev; -+ char phy_id[MII_BUS_ID_SIZE + 3]; -+ char bus_id[MII_BUS_ID_SIZE]; -+ phy_interface_t interface; -+ -+ priv->oldlink = 0; -+ priv->oldspeed = 0; -+ priv->oldduplex = -1; -+ -+ snprintf(bus_id, MII_BUS_ID_SIZE, "comcerto-%d", 0); -+ snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, priv->einfo->phy_id); -+ -+ netif_info(priv, drv, dev, "%s: %s\n", __func__, phy_id); -+#if defined(CONFIG_PLATFORM_C2000) -+ interface = pfe_get_interface(dev); -+#else -+ interface = priv->einfo->mii_config; -+ if(interface == PHY_INTERFACE_MODE_SGMII) { -+ /*Configure SGMII PCS */ -+ if(pfe->scfg) { -+ /*Config MDIO from serdes */ -+ regmap_write(pfe->scfg, 0x484, 0x00000000); -+ } -+ ls1012a_configure_serdes(dev); -+ } -+ -+ if(pfe->scfg) { -+ /*Config MDIO from PAD */ -+ regmap_write(pfe->scfg, 0x484, 0x80000000); -+ } -+#endif -+ -+ -+ priv->oldlink = 0; -+ priv->oldspeed = 0; -+ priv->oldduplex = -1; -+ -+ printk("%s interface %x \n", __func__, interface); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0) -+ phydev = phy_connect(dev, phy_id, &pfe_eth_adjust_link, interface); -+#else -+ phydev = phy_connect(dev, phy_id, &pfe_eth_adjust_link, 0, interface); -+#endif -+ -+ if (IS_ERR(phydev)) { -+ netdev_err(dev, "phy_connect() failed\n"); -+ return PTR_ERR(phydev); -+ } -+ -+ priv->phydev = phydev; -+ phydev->irq = PHY_POLL; -+ -+#if defined(CONFIG_PLATFORM_C2000) -+ /* Pause frame support */ -+ phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; -+ if (pfe_eth_pause_rx_enabled(priv)) -+ phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; -+ else -+ phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); -+#else -+ /*TODO Add pause frame support for LS1012A */ -+#endif -+ -+ return 0; -+} -+ -+/** pfe_gemac_init -+ */ -+static int pfe_gemac_init(struct pfe_eth_priv_s *priv) -+{ -+ GEMAC_CFG cfg; -+ -+ netif_info(priv, ifup, priv->dev, "%s\n", __func__); -+ -+ /* software config */ -+ /* MII interface mode selection */ -+ switch (priv->einfo->mii_config) { -+ case CONFIG_COMCERTO_USE_GMII: -+ cfg.mode = GMII; -+ break; -+ -+ case CONFIG_COMCERTO_USE_MII: -+ cfg.mode = MII; -+ break; -+ -+ case CONFIG_COMCERTO_USE_RGMII: -+ cfg.mode = RGMII; -+ break; -+ -+ case CONFIG_COMCERTO_USE_RMII: -+ cfg.mode = RMII; -+ break; -+ -+ case CONFIG_COMCERTO_USE_SGMII: -+ cfg.mode = SGMII; -+ break; -+ -+ default: -+ cfg.mode = RGMII; -+ } -+ -+ /* Speed selection */ -+ switch (priv->einfo->gemac_mode & GEMAC_SW_SPEED_1G ) { -+ case GEMAC_SW_SPEED_1G: -+ cfg.speed = SPEED_1000M; -+ break; -+ -+ case GEMAC_SW_SPEED_100M: -+ cfg.speed = SPEED_100M; -+ break; -+ -+ case GEMAC_SW_SPEED_10M: -+ cfg.speed = SPEED_10M; -+ break; -+ -+ default: -+ cfg.speed = SPEED_1000M; -+ } -+ -+ /* Duplex selection */ -+ cfg.duplex = ( priv->einfo->gemac_mode & GEMAC_SW_FULL_DUPLEX ) ? DUPLEX_FULL : DUPLEX_HALF; -+ -+ gemac_set_config( priv->EMAC_baseaddr, &cfg); -+ gemac_allow_broadcast( priv->EMAC_baseaddr ); -+ gemac_disable_unicast( priv->EMAC_baseaddr ); -+ gemac_disable_multicast( priv->EMAC_baseaddr ); -+ gemac_disable_fcs_rx( priv->EMAC_baseaddr ); -+ gemac_enable_1536_rx( priv->EMAC_baseaddr ); -+ gemac_enable_rx_jmb( priv->EMAC_baseaddr ); -+ gemac_enable_stacked_vlan( priv->EMAC_baseaddr ); -+ gemac_enable_pause_rx( priv->EMAC_baseaddr ); -+ gemac_set_bus_width(priv->EMAC_baseaddr, 64); -+ /*TODO just for testing remove it later */ -+ gemac_enable_copy_all(priv->EMAC_baseaddr); -+ -+ /*GEM will perform checksum verifications*/ -+ if (priv->dev->features & NETIF_F_RXCSUM) -+ gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr); -+ else -+ gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr); -+ -+ return 0; -+} -+ -+/** pfe_eth_event_handler -+ */ -+static int pfe_eth_event_handler(void *data, int event, int qno) -+{ -+ struct pfe_eth_priv_s *priv = data; -+ -+ switch (event) { -+ case EVENT_RX_PKT_IND: -+ -+ if (qno == 0) { -+ if (napi_schedule_prep(&priv->high_napi)) { -+ netif_info(priv, intr, priv->dev, "%s: schedule high prio poll\n", __func__); -+ -+#ifdef PFE_ETH_NAPI_STATS -+ priv->napi_counters[NAPI_SCHED_COUNT]++; -+#endif -+ -+ __napi_schedule(&priv->high_napi); -+ } -+ } -+ else if (qno == 1) { -+ if (napi_schedule_prep(&priv->low_napi)) { -+ netif_info(priv, intr, priv->dev, "%s: schedule low prio poll\n", __func__); -+ -+#ifdef PFE_ETH_NAPI_STATS -+ priv->napi_counters[NAPI_SCHED_COUNT]++; -+#endif -+ __napi_schedule(&priv->low_napi); -+ } -+ } -+ else if (qno == 2) { -+ if (napi_schedule_prep(&priv->lro_napi)) { -+ netif_info(priv, intr, priv->dev, "%s: schedule lro prio poll\n", __func__); -+ -+#ifdef PFE_ETH_NAPI_STATS -+ priv->napi_counters[NAPI_SCHED_COUNT]++; -+#endif -+ __napi_schedule(&priv->lro_napi); -+ } -+ } -+ -+ break; -+ -+ case EVENT_TXDONE_IND: -+ case EVENT_HIGH_RX_WM: -+ default: -+ break; -+ } -+ -+ return 0; -+} -+ -+/** pfe_eth_open -+ */ -+static int pfe_eth_open(struct net_device *dev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ struct hif_client_s *client; -+ int rc; -+ -+ netif_info(priv, ifup, dev, "%s\n", __func__); -+ -+ /* Register client driver with HIF */ -+ client = &priv->client; -+ memset(client, 0, sizeof(*client)); -+ client->id = PFE_CL_GEM0 + priv->id; -+ client->tx_qn = emac_txq_cnt; -+ client->rx_qn = EMAC_RXQ_CNT; -+ client->priv = priv; -+ client->pfe = priv->pfe; -+ client->event_handler = pfe_eth_event_handler; -+ -+ /* FIXME : For now hif lib sets all tx and rx queues to same size */ -+ client->tx_qsize = EMAC_TXQ_DEPTH; -+ client->rx_qsize = EMAC_RXQ_DEPTH; -+ -+ if ((rc = hif_lib_client_register(client))) { -+ netdev_err(dev, "%s: hif_lib_client_register(%d) failed\n", __func__, client->id); -+ goto err0; -+ } -+ -+ netif_info(priv, drv, dev, "%s: registered client: %p\n", __func__, client); -+ -+#if defined(CONFIG_PLATFORM_C2000) -+ /* Enable gemac tx clock */ -+ clk_enable(priv->gemtx_clk); -+#endif -+ -+ pfe_gemac_init(priv); -+ -+ if (!is_valid_ether_addr(dev->dev_addr)) { -+ netdev_err(dev, "%s: invalid MAC address\n", __func__); -+ rc = -EADDRNOTAVAIL; -+ goto err1; -+ } -+ -+ gemac_set_laddrN( priv->EMAC_baseaddr, ( MAC_ADDR *)dev->dev_addr, 1 ); -+ -+ napi_enable(&priv->high_napi); -+ napi_enable(&priv->low_napi); -+ napi_enable(&priv->lro_napi); -+ -+ rc = pfe_eth_start(priv); -+ -+ netif_tx_wake_all_queues(dev); -+ -+ //pfe_ctrl_set_eth_state(priv->id, 1, dev->dev_addr); -+ -+ priv->tx_timer.expires = jiffies + ( COMCERTO_TX_RECOVERY_TIMEOUT_MS * HZ )/1000; -+ add_timer(&priv->tx_timer); -+ -+ return rc; -+ -+err1: -+ hif_lib_client_unregister(&priv->client); -+#if defined(CONFIG_PLATFORM_C2000) -+ clk_disable(priv->gemtx_clk); -+#endif -+ -+err0: -+ return rc; -+} -+/* -+ * pfe_eth_shutdown -+ */ -+int pfe_eth_shutdown( struct net_device *dev, int wake) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ int i, qstatus; -+ unsigned long next_poll = jiffies + 1, end = jiffies + (TX_POLL_TIMEOUT_MS * HZ) / 1000; -+ int tx_pkts, prv_tx_pkts; -+ -+ netif_info(priv, ifdown, dev, "%s\n", __func__); -+ -+ del_timer_sync(&priv->tx_timer); -+ -+ for(i = 0; i < emac_txq_cnt; i++) -+ hrtimer_cancel(&priv->fast_tx_timeout[i].timer); -+ -+ netif_tx_stop_all_queues(dev); -+ -+ do { -+ tx_pkts = 0; -+ pfe_eth_flush_tx(priv, 1); -+ -+ for (i = 0; i < emac_txq_cnt; i++) -+ tx_pkts += hif_lib_tx_pending(&priv->client, i); -+ -+ if (tx_pkts) { -+ /*Don't wait forever, break if we cross max timeout */ -+ if (time_after(jiffies, end)) { -+ printk(KERN_ERR "(%s)Tx is not complete after %dmsec\n", dev->name, TX_POLL_TIMEOUT_MS); -+ break; -+ } -+ -+ printk("%s : (%s) Waiting for tx packets to free. Pending tx pkts = %d.\n", __func__, dev->name, tx_pkts); -+ if (need_resched()) -+ schedule(); -+ } -+ -+ } while(tx_pkts); -+ -+ end = jiffies + (TX_POLL_TIMEOUT_MS * HZ) / 1000; -+ /*Disable transmit in PFE before disabling GEMAC */ -+ //pfe_ctrl_set_eth_state(priv->id, 0, NULL); -+ -+ prv_tx_pkts = tmu_pkts_processed(priv->id); -+ /*Wait till TMU transmits all pending packets -+ * poll tmu_qstatus and pkts processed by TMU for every 10ms -+ * Consider TMU is busy, If we see TMU qeueu pending or any packets processed by TMU -+ */ -+ while(1) { -+ -+ if (time_after(jiffies, next_poll)) { -+ -+ tx_pkts = tmu_pkts_processed(priv->id); -+ qstatus = tmu_qstatus(priv->id) & 0x7ffff; -+ -+ if(!qstatus && (tx_pkts == prv_tx_pkts)) { -+ break; -+ } -+ /*Don't wait forever, break if we cross max timeout(TX_POLL_TIMEOUT_MS) */ -+ if (time_after(jiffies, end)) { -+ printk(KERN_ERR "TMU%d is busy after %dmsec\n", priv->id, TX_POLL_TIMEOUT_MS); -+ break; -+ } -+ prv_tx_pkts = tx_pkts; -+ next_poll++; -+ } -+ if (need_resched()) -+ schedule(); -+ -+ -+ } -+ /* Wait for some more time to complete transmitting packet if any */ -+ next_poll = jiffies + 1; -+ while(1) { -+ if (time_after(jiffies, next_poll)) -+ break; -+ if (need_resched()) -+ schedule(); -+ } -+ -+ pfe_eth_stop(dev, wake); -+ -+ napi_disable(&priv->lro_napi); -+ napi_disable(&priv->low_napi); -+ napi_disable(&priv->high_napi); -+ -+#if defined(CONFIG_PLATFORM_C2000) -+ /* Disable gemac tx clock */ -+ clk_disable(priv->gemtx_clk); -+#endif -+ -+ hif_lib_client_unregister(&priv->client); -+ -+ return 0; -+} -+ -+/* pfe_eth_close -+ * -+ */ -+static int pfe_eth_close( struct net_device *dev ) -+{ -+ pfe_eth_shutdown(dev, 0); -+ -+ return 0; -+} -+ -+/* pfe_eth_suspend -+ * -+ * return value : 1 if netdevice is configured to wakeup system -+ * 0 otherwise -+ */ -+int pfe_eth_suspend(struct net_device *dev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ int retval = 0; -+ -+ if (priv->wol) { -+ gemac_set_wol(priv->EMAC_baseaddr, priv->wol); -+ retval = 1; -+ } -+ pfe_eth_shutdown(dev, priv->wol); -+ -+ return retval; -+} -+ -+/** pfe_eth_resume -+ * -+ */ -+int pfe_eth_resume(struct net_device *dev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ -+ if (priv->wol) -+ gemac_set_wol(priv->EMAC_baseaddr, 0); -+ -+ return pfe_eth_open(dev); -+} -+ -+#if defined(CONFIG_PLATFORM_C2000) -+/** pfe_eth_set_device_wakeup -+ * -+ * Called when a netdevice changes its wol status. -+ * Scans state of all interfaces and updae PFE device -+ * wakeable state -+ */ -+static void pfe_eth_set_device_wakeup(struct pfe *pfe) -+{ -+ int i; -+ int wake = 0; -+ -+ for(i = 0; i < NUM_GEMAC_SUPPORT; i++) -+ wake |= pfe->eth.eth_priv[i]->wol; -+ -+ device_set_wakeup_enable(pfe->dev, wake); -+ //TODO Find correct IRQ mapping. -+ //TODO interface with PMU -+ //int irq_set_irq_wake(unsigned int irq, unsigned int on) -+} -+#endif -+/** pfe_eth_get_queuenum -+ * -+ */ -+static int pfe_eth_get_queuenum( struct pfe_eth_priv_s *priv, struct sk_buff *skb ) -+{ -+ int queuenum = 0; -+ unsigned long flags; -+ -+ /* Get the Fast Path queue number */ -+ /* Use conntrack mark (if conntrack exists), then packet mark (if any), then fallback to default */ -+#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK) -+ if (skb->nfct) { -+ enum ip_conntrack_info cinfo; -+ struct nf_conn *ct; -+ ct = nf_ct_get(skb, &cinfo); -+ -+ if (ct) { -+ u_int32_t connmark; -+ connmark = ct->mark; -+ -+ if ((connmark & 0x80000000) && priv->id != 0) -+ connmark >>= 16; -+ -+ queuenum = connmark & EMAC_QUEUENUM_MASK; -+ } -+ } -+ else /* continued after #endif ... */ -+#endif -+ if (skb->mark) -+ queuenum = skb->mark & EMAC_QUEUENUM_MASK; -+ else { -+ spin_lock_irqsave(&priv->lock, flags); -+ queuenum = priv->default_priority & EMAC_QUEUENUM_MASK; -+ spin_unlock_irqrestore(&priv->lock, flags); -+ } -+ -+ return queuenum; -+} -+ -+ -+ -+/** pfe_eth_might_stop_tx -+ * -+ */ -+static int pfe_eth_might_stop_tx(struct pfe_eth_priv_s *priv, int queuenum, struct netdev_queue *tx_queue, unsigned int n_desc, unsigned int n_segs) -+{ -+ int tried = 0; -+ ktime_t kt; -+ -+try_again: -+ if (unlikely((__hif_tx_avail(&pfe->hif) < n_desc) -+ || (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) -+ || (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < n_segs))) { -+ -+ if (!tried) { -+ hif_tx_unlock(&pfe->hif); -+ pfe_eth_flush_txQ(priv, queuenum, 1, n_desc); -+ hif_lib_update_credit(&priv->client, queuenum); -+ tried = 1; -+ hif_tx_lock(&pfe->hif); -+ goto try_again; -+ } -+#ifdef PFE_ETH_TX_STATS -+ if (__hif_tx_avail(&pfe->hif) < n_desc) -+ priv->stop_queue_hif[queuenum]++; -+ else if (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) { -+ priv->stop_queue_hif_client[queuenum]++; -+ } -+ else if (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < n_segs) { -+ priv->stop_queue_credit[queuenum]++; -+ } -+ priv->stop_queue_total[queuenum]++; -+#endif -+ netif_tx_stop_queue(tx_queue); -+ -+ kt = ktime_set(0, COMCERTO_TX_FAST_RECOVERY_TIMEOUT_MS * NSEC_PER_MSEC); -+ hrtimer_start(&priv->fast_tx_timeout[queuenum].timer, kt, HRTIMER_MODE_REL); -+ return -1; -+ } -+ else { -+ return 0; -+ } -+} -+ -+#define SA_MAX_OP 2 -+/** pfe_hif_send_packet -+ * -+ * At this level if TX fails we drop the packet -+ */ -+static void pfe_hif_send_packet( struct sk_buff *skb, struct pfe_eth_priv_s *priv, int queuenum) -+{ -+ struct skb_shared_info *sh = skb_shinfo(skb); -+ unsigned int nr_frags; -+ u32 ctrl = 0; -+ -+ netif_info(priv, tx_queued, priv->dev, "%s\n", __func__); -+ -+ if (skb_is_gso(skb)) { -+ priv->stats.tx_dropped++; -+ return; -+ } -+ -+ if (skb->ip_summed == CHECKSUM_PARTIAL) { -+ if (skb->len > 1522) { -+ skb->ip_summed = 0; -+ ctrl = 0; -+ -+ if (pfe_compute_csum(skb)){ -+ kfree_skb(skb); -+ return; -+ } -+ } -+ else -+ ctrl = HIF_CTRL_TX_CHECKSUM; -+ } -+ -+ nr_frags = sh->nr_frags; -+ -+ if (nr_frags) { -+ skb_frag_t *f; -+ int i; -+ -+ __hif_lib_xmit_pkt(&priv->client, queuenum, skb->data, skb_headlen(skb), ctrl, HIF_FIRST_BUFFER, skb); -+ -+ for (i = 0; i < nr_frags - 1; i++) { -+ f = &sh->frags[i]; -+ __hif_lib_xmit_pkt(&priv->client, queuenum, skb_frag_address(f), skb_frag_size(f), 0x0, 0x0, skb); -+ } -+ -+ f = &sh->frags[i]; -+ -+ __hif_lib_xmit_pkt(&priv->client, queuenum, skb_frag_address(f), skb_frag_size(f), 0x0, HIF_LAST_BUFFER|HIF_DATA_VALID, skb); -+ -+ netif_info(priv, tx_queued, priv->dev, "%s: pkt sent successfully skb:%p nr_frags:%d len:%d\n", __func__, skb, nr_frags, skb->len); -+ } -+ else { -+ __hif_lib_xmit_pkt(&priv->client, queuenum, skb->data, skb->len, ctrl, HIF_FIRST_BUFFER | HIF_LAST_BUFFER | HIF_DATA_VALID, skb); -+ netif_info(priv, tx_queued, priv->dev, "%s: pkt sent successfully skb:%p len:%d\n", __func__, skb, skb->len); -+ } -+ hif_tx_dma_start(); -+ priv->stats.tx_packets++; -+ priv->stats.tx_bytes += skb->len; -+ hif_lib_tx_credit_use(pfe, priv->id, queuenum, 1); -+} -+ -+/** pfe_eth_flush_txQ -+ */ -+static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int txQ_num, int from_tx, int n_desc) -+{ -+ struct sk_buff *skb; -+ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->dev, txQ_num); -+ int count = max(TX_FREE_MAX_COUNT, n_desc); -+ unsigned int flags; -+ -+ netif_info(priv, tx_done, priv->dev, "%s\n", __func__); -+ -+ if (!from_tx) -+ __netif_tx_lock_bh(tx_queue); -+ -+ /* Clean HIF and client queue */ -+ while (count && (skb = hif_lib_tx_get_next_complete(&priv->client, txQ_num, &flags, count))) { -+ -+ /* FIXME : Invalid data can be skipped in hif_lib itself */ -+ if (flags & HIF_DATA_VALID) { -+ dev_kfree_skb_any(skb); -+ -+ } -+ // When called from the timer, flush all descriptors -+ if (from_tx) -+ count--; -+ } -+ -+ if (!from_tx) -+ __netif_tx_unlock_bh(tx_queue); -+} -+ -+/** pfe_eth_flush_tx -+ */ -+static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv, int force) -+{ -+ int ii; -+ -+ netif_info(priv, tx_done, priv->dev, "%s\n", __func__); -+ -+ for (ii = 0; ii < emac_txq_cnt; ii++) { -+ if (force || (time_after(jiffies, priv->client.tx_q[ii].jiffies_last_packet + (COMCERTO_TX_RECOVERY_TIMEOUT_MS * HZ)/1000))) { -+ pfe_eth_flush_txQ(priv, ii, 0, 0); //We will release everything we can based on from_tx param, so the count param can be set to any value -+ hif_lib_update_credit(&priv->client, ii); -+ } -+ } -+} -+ -+void pfe_tx_get_req_desc(struct sk_buff *skb, unsigned int *n_desc, unsigned int *n_segs) -+{ -+ struct skb_shared_info *sh = skb_shinfo(skb); -+ -+ // Scattered data -+ if (sh->nr_frags) { -+ *n_desc = sh->nr_frags + 1; -+ *n_segs = 1; -+ } -+ // Regular case -+ else { -+ *n_desc = 1; -+ *n_segs = 1; -+ } -+ return; -+} -+ -+/** pfe_eth_send_packet -+ */ -+static int pfe_eth_send_packet(struct sk_buff *skb, struct net_device *dev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ int txQ_num = skb_get_queue_mapping(skb); -+ int n_desc, n_segs, count; -+ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->dev, txQ_num); -+ -+ netif_info(priv, tx_queued, dev, "%s\n", __func__); -+ -+ if ((!skb_is_gso(skb)) && (skb_headroom(skb) < (PFE_PKT_HEADER_SZ + sizeof(unsigned long)))) { -+ -+ netif_warn(priv, tx_err, priv->dev, "%s: copying skb\n", __func__); -+ -+ if (pskb_expand_head(skb, (PFE_PKT_HEADER_SZ + sizeof(unsigned long)), 0, GFP_ATOMIC)) { -+ /* No need to re-transmit, no way to recover*/ -+ kfree_skb(skb); -+ priv->stats.tx_dropped++; -+ return NETDEV_TX_OK; -+ } -+ } -+ -+ pfe_tx_get_req_desc(skb, &n_desc, &n_segs); -+ -+ hif_tx_lock(&pfe->hif); -+ if(unlikely(pfe_eth_might_stop_tx(priv, txQ_num, tx_queue, n_desc, n_segs))) { -+#ifdef PFE_ETH_TX_STATS -+ if(priv->was_stopped[txQ_num]) { -+ priv->clean_fail[txQ_num]++; -+ priv->was_stopped[txQ_num] = 0; -+ } -+#endif -+ hif_tx_unlock(&pfe->hif); -+ return NETDEV_TX_BUSY; -+ } -+ -+ pfe_hif_send_packet(skb, priv, txQ_num); -+ -+ hif_tx_unlock(&pfe->hif); -+ -+ dev->trans_start = jiffies; -+ -+ // Recycle buffers if a socket's send buffer becomes half full or if the HIF client queue starts filling up -+ if (((count = (hif_lib_tx_pending(&priv->client, txQ_num) - HIF_CL_TX_FLUSH_MARK)) > 0) -+ || (skb->sk && ((sk_wmem_alloc_get(skb->sk) << 1) > skb->sk->sk_sndbuf))) -+ pfe_eth_flush_txQ(priv, txQ_num, 1, count); -+ -+#ifdef PFE_ETH_TX_STATS -+ priv->was_stopped[txQ_num] = 0; -+#endif -+ -+ return NETDEV_TX_OK; -+} -+ -+/** pfe_eth_select_queue -+ * -+ */ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0) -+static u16 pfe_eth_select_queue( struct net_device *dev, struct sk_buff *skb, -+ void *accel_priv, select_queue_fallback_t fallback) -+#else -+static u16 pfe_eth_select_queue( struct net_device *dev, struct sk_buff *skb ) -+#endif -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ -+ return pfe_eth_get_queuenum(priv, skb); -+} -+ -+ -+/** pfe_eth_get_stats -+ */ -+static struct net_device_stats *pfe_eth_get_stats(struct net_device *dev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ -+ netif_info(priv, drv, dev, "%s\n", __func__); -+ -+ return &priv->stats; -+} -+ -+ -+/** pfe_eth_change_mtu -+ */ -+static int pfe_eth_change_mtu(struct net_device *dev, int new_mtu) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ int oldsize = dev->mtu ; -+ int frame_size = new_mtu + ETH_HLEN +4; -+ -+ netif_info(priv, drv, dev, "%s\n", __func__); -+ -+ if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { -+ netif_err(priv, drv, dev, "Invalid MTU setting\n"); -+ return -EINVAL; -+ } -+ -+ if ((new_mtu > 1500) && (dev->features & NETIF_F_TSO)) -+ { -+ priv->usr_features = dev->features; -+ if (dev->features & NETIF_F_TSO) -+ { -+ netdev_err(dev, "MTU cannot be set to more than 1500 while TSO is enabled. disabling TSO.\n"); -+ dev->features &= ~(NETIF_F_TSO); -+ } -+ } -+ else if ((dev->mtu > 1500) && (new_mtu <= 1500)) -+ { -+ if (priv->usr_features & NETIF_F_TSO) -+ { -+ priv->usr_features &= ~(NETIF_F_TSO); -+ dev->features |= NETIF_F_TSO; -+ netdev_err(dev, "MTU is <= 1500, Enabling TSO feature.\n"); -+ } -+ } -+ -+ /* Only stop and start the controller if it isn't already -+ * stopped, and we changed something */ -+ if ((oldsize != new_mtu) && (dev->flags & IFF_UP)){ -+ netdev_err(dev, "Can not change MTU - fast_path must be disabled and ifconfig down must be issued first\n"); -+ -+ return -EINVAL; -+ } -+ -+ dev->mtu = new_mtu; -+ -+ return 0; -+} -+ -+/** pfe_eth_set_mac_address -+ */ -+static int pfe_eth_set_mac_address(struct net_device *dev, void *addr) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ struct sockaddr *sa = addr; -+ -+ netif_info(priv, drv, dev, "%s\n", __func__); -+ -+ if (!is_valid_ether_addr(sa->sa_data)) -+ return -EADDRNOTAVAIL; -+ -+ memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); -+ -+ gemac_set_laddrN(priv->EMAC_baseaddr, (MAC_ADDR *)dev->dev_addr, 1); -+ -+ return 0; -+ -+} -+ -+/** pfe_eth_enet_addr_byte_mac -+ */ -+int pfe_eth_enet_addr_byte_mac(u8 * enet_byte_addr, MAC_ADDR *enet_addr) -+{ -+ if ((enet_byte_addr == NULL) || (enet_addr == NULL)) -+ { -+ return -1; -+ } -+ else -+ { -+ enet_addr->bottom = enet_byte_addr[0] | -+ (enet_byte_addr[1] << 8) | -+ (enet_byte_addr[2] << 16) | -+ (enet_byte_addr[3] << 24); -+ enet_addr->top = enet_byte_addr[4] | -+ (enet_byte_addr[5] << 8); -+ return 0; -+ } -+} -+ -+ -+ -+/** pfe_eth_set_multi -+ */ -+static void pfe_eth_set_multi(struct net_device *dev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ MAC_ADDR hash_addr; /* hash register structure */ -+ MAC_ADDR spec_addr; /* specific mac address register structure */ -+ int result; /* index into hash register to set.. */ -+ int uc_count = 0; -+ struct netdev_hw_addr *ha; -+ -+ if (dev->flags & IFF_PROMISC) { -+ netif_info(priv, drv, dev, "entering promiscuous mode\n"); -+ -+ priv->promisc = 1; -+ gemac_enable_copy_all(priv->EMAC_baseaddr); -+ } else { -+ priv->promisc = 0; -+ gemac_disable_copy_all(priv->EMAC_baseaddr); -+ } -+ -+ /* Enable broadcast frame reception if required. */ -+ if (dev->flags & IFF_BROADCAST) { -+ gemac_allow_broadcast(priv->EMAC_baseaddr); -+ } else { -+ netif_info(priv, drv, dev, "disabling broadcast frame reception\n"); -+ -+ gemac_no_broadcast(priv->EMAC_baseaddr); -+ } -+ -+ if (dev->flags & IFF_ALLMULTI) { -+ /* Set the hash to rx all multicast frames */ -+ hash_addr.bottom = 0xFFFFFFFF; -+ hash_addr.top = 0xFFFFFFFF; -+ gemac_set_hash(priv->EMAC_baseaddr, &hash_addr); -+ gemac_enable_multicast(priv->EMAC_baseaddr); -+ netdev_for_each_uc_addr(ha, dev) { -+ if(uc_count >= MAX_UC_SPEC_ADDR_REG) break; -+ pfe_eth_enet_addr_byte_mac(ha->addr, &spec_addr); -+ gemac_set_laddrN(priv->EMAC_baseaddr, &spec_addr, uc_count + 2); -+ uc_count++; -+ } -+ } else if ((netdev_mc_count(dev) > 0) || (netdev_uc_count(dev))) { -+ u8 *addr; -+ -+ hash_addr.bottom = 0; -+ hash_addr.top = 0; -+ -+ netdev_for_each_mc_addr(ha, dev) { -+ addr = ha->addr; -+ -+ netif_info(priv, drv, dev, "adding multicast address %X:%X:%X:%X:%X:%X to gem filter\n", -+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); -+ -+ result = pfe_eth_get_hash(addr); -+ -+ if (result >= EMAC_HASH_REG_BITS) { -+ break; -+ } else { -+ if (result < 32) { -+ hash_addr.bottom |= (1 << result); -+ } else { -+ hash_addr.top |= (1 << (result - 32)); -+ } -+ } -+ -+ } -+ -+ uc_count = -1; -+ netdev_for_each_uc_addr(ha, dev) { -+ addr = ha->addr; -+ -+ if(++uc_count < MAX_UC_SPEC_ADDR_REG) -+ { -+ netdev_info(dev, "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem filter\n", -+ addr[0], addr[1], addr[2], -+ addr[3], addr[4], addr[5]); -+ -+ pfe_eth_enet_addr_byte_mac(addr, &spec_addr); -+ gemac_set_laddrN(priv->EMAC_baseaddr, &spec_addr, uc_count + 2); -+ } -+ else -+ { -+ netif_info(priv, drv, dev, "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem hash\n", -+ addr[0], addr[1], addr[2], -+ addr[3], addr[4], addr[5]); -+ -+ result = pfe_eth_get_hash(addr); -+ if (result >= EMAC_HASH_REG_BITS) { -+ break; -+ } else { -+ if (result < 32) -+ hash_addr.bottom |= (1 << result); -+ else -+ hash_addr.top |= (1 << (result - 32)); -+ } -+ -+ -+ } -+ } -+ -+ gemac_set_hash(priv->EMAC_baseaddr, &hash_addr); -+ if(netdev_mc_count(dev)) -+ gemac_enable_multicast(priv->EMAC_baseaddr); -+ else -+ gemac_disable_multicast(priv->EMAC_baseaddr); -+ } -+ -+ if(netdev_uc_count(dev) >= MAX_UC_SPEC_ADDR_REG) -+ gemac_enable_unicast(priv->EMAC_baseaddr); -+ else -+ { -+ /* Check if there are any specific address HW registers that need -+ * to be flushed -+ * */ -+ for(uc_count = netdev_uc_count(dev); uc_count < MAX_UC_SPEC_ADDR_REG; uc_count++) -+ gemac_clear_laddrN(priv->EMAC_baseaddr, uc_count + 2); -+ -+ gemac_disable_unicast(priv->EMAC_baseaddr); -+ } -+ -+ if (dev->flags & IFF_LOOPBACK) { -+ gemac_set_loop(priv->EMAC_baseaddr, LB_LOCAL); -+ } -+ -+ return; -+} -+ -+/** pfe_eth_set_features -+ */ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) -+static int pfe_eth_set_features(struct net_device *dev, netdev_features_t features) -+#else -+static int pfe_eth_set_features(struct net_device *dev, u32 features) -+#endif -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ int rc = 0; -+ -+ if (features & NETIF_F_RXCSUM) -+ gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr); -+ else -+ gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr); -+ return rc; -+} -+ -+/** pfe_eth_fix_features -+ */ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) -+static netdev_features_t pfe_eth_fix_features(struct net_device *dev, netdev_features_t features) -+#else -+static unsigned int pfe_eth_fix_features(struct net_device *dev,u32 features) -+#endif -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(dev); -+ -+ if (dev->mtu > 1500) -+ { -+ if (features & (NETIF_F_TSO)) -+ { -+ priv->usr_features |= NETIF_F_TSO; -+ features &= ~(NETIF_F_TSO); -+ netdev_err(dev, "TSO cannot be enabled when the MTU is larger than 1500. Please set the MTU to 1500 or lower first.\n"); -+ } -+ } -+ -+ return features; -+} -+ -+/** pfe_eth_tx_timeout -+ */ -+void pfe_eth_tx_timeout(unsigned long data ) -+{ -+ struct pfe_eth_priv_s *priv = (struct pfe_eth_priv_s *)data; -+ -+ netif_info(priv, timer, priv->dev, "%s\n", __func__); -+ -+ pfe_eth_flush_tx(priv, 0); -+ -+ priv->tx_timer.expires = jiffies + ( COMCERTO_TX_RECOVERY_TIMEOUT_MS * HZ )/1000; -+ add_timer(&priv->tx_timer); -+} -+ -+/** pfe_eth_fast_tx_timeout -+ */ -+static enum hrtimer_restart pfe_eth_fast_tx_timeout(struct hrtimer *timer) -+{ -+ struct pfe_eth_fast_timer *fast_tx_timeout = container_of(timer, struct pfe_eth_fast_timer, timer); -+ struct pfe_eth_priv_s *priv = container_of(fast_tx_timeout->base, struct pfe_eth_priv_s, fast_tx_timeout); -+ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->dev, fast_tx_timeout->queuenum); -+ -+ if(netif_tx_queue_stopped(tx_queue)) { -+#ifdef PFE_ETH_TX_STATS -+ priv->was_stopped[fast_tx_timeout->queuenum] = 1; -+#endif -+ netif_tx_wake_queue(tx_queue); -+ } -+ -+ return HRTIMER_NORESTART; -+} -+ -+/** pfe_eth_fast_tx_timeout_init -+ */ -+static void pfe_eth_fast_tx_timeout_init(struct pfe_eth_priv_s *priv) -+{ -+ int i; -+ for (i = 0; i < emac_txq_cnt; i++) { -+ priv->fast_tx_timeout[i].queuenum = i; -+ hrtimer_init(&priv->fast_tx_timeout[i].timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); -+ priv->fast_tx_timeout[i].timer.function = pfe_eth_fast_tx_timeout; -+ priv->fast_tx_timeout[i].base = priv->fast_tx_timeout; -+ } -+} -+ -+static struct sk_buff *pfe_eth_rx_skb(struct net_device *dev, struct pfe_eth_priv_s *priv, unsigned int qno) -+{ -+ void *buf_addr; -+ unsigned int rx_ctrl; -+ unsigned int desc_ctrl = 0; -+ struct hif_ipsec_hdr *ipsec_hdr = NULL; -+ struct sk_buff *skb; -+ struct sk_buff *skb_frag, *skb_frag_last = NULL; -+ int length = 0, offset; -+ -+ skb = priv->skb_inflight[qno]; -+ -+ if (skb && (skb_frag_last = skb_shinfo(skb)->frag_list)) { -+ while (skb_frag_last->next) -+ skb_frag_last = skb_frag_last->next; -+ } -+ -+ while (!(desc_ctrl & CL_DESC_LAST)) { -+ -+ buf_addr = hif_lib_receive_pkt(&priv->client, qno, &length, &offset, &rx_ctrl, &desc_ctrl, (void **)&ipsec_hdr); -+ if (!buf_addr) -+ goto incomplete; -+ -+#ifdef PFE_ETH_NAPI_STATS -+ priv->napi_counters[NAPI_DESC_COUNT]++; -+#endif -+ -+ /* First frag */ -+ if (desc_ctrl & CL_DESC_FIRST) { -+#if defined(CONFIG_PLATFORM_EMULATION) || defined(CONFIG_PLATFORM_PCI) -+ skb = dev_alloc_skb(PFE_BUF_SIZE); -+ if (unlikely(!skb)) { -+ goto pkt_drop; -+ } -+ -+ skb_copy_to_linear_data(skb, buf_addr, length + offset); -+ kfree(buf_addr); -+#else -+#if defined(CONFIG_COMCERTO_ZONE_DMA_NCNB) -+ skb = alloc_skb(length + offset + 32, GFP_ATOMIC); -+#else -+ skb = alloc_skb_header(PFE_BUF_SIZE, buf_addr, GFP_ATOMIC); -+#endif -+ if (unlikely(!skb)) { -+ goto pkt_drop; -+ } -+#endif -+ skb_reserve(skb, offset); -+#if defined(CONFIG_COMCERTO_ZONE_DMA_NCNB) -+ __memcpy(skb->data, buf_addr + offset, length); -+ if (ipsec_hdr) { -+ sah_local = *(unsigned int *)&ipsec_hdr->sa_handle[0]; -+ } -+ kfree(buf_addr); -+#endif -+ skb_put(skb, length); -+ skb->dev = dev; -+ -+ if ((dev->features & NETIF_F_RXCSUM) && (rx_ctrl & HIF_CTRL_RX_CHECKSUMMED)) -+ skb->ip_summed = CHECKSUM_UNNECESSARY; -+ else -+ skb_checksum_none_assert(skb); -+ -+ } else { -+ -+ /* Next frags */ -+ if (unlikely(!skb)) { -+ printk(KERN_ERR "%s: NULL skb_inflight\n", __func__); -+ goto pkt_drop; -+ } -+ -+#if defined(CONFIG_COMCERTO_ZONE_DMA_NCNB) -+ skb_frag = alloc_skb(length + offset + 32, GFP_ATOMIC); -+#else -+ skb_frag = alloc_skb_header(PFE_BUF_SIZE, buf_addr, GFP_ATOMIC); -+#endif -+ if (unlikely(!skb_frag)) { -+ kfree(buf_addr); -+ goto pkt_drop; -+ } -+ -+ skb_reserve(skb_frag, offset); -+#if defined(CONFIG_COMCERTO_ZONE_DMA_NCNB) -+ __memcpy(skb_frag->data, buf_addr + offset, length); -+ kfree(buf_addr); -+#endif -+ skb_put(skb_frag, length); -+ -+ skb_frag->dev = dev; -+ -+ if (skb_shinfo(skb)->frag_list) -+ skb_frag_last->next = skb_frag; -+ else -+ skb_shinfo(skb)->frag_list = skb_frag; -+ -+ skb->truesize += skb_frag->truesize; -+ skb->data_len += length; -+ skb->len += length; -+ skb_frag_last = skb_frag; -+ } -+ } -+ -+ priv->skb_inflight[qno] = NULL; -+ return skb; -+ -+incomplete: -+ priv->skb_inflight[qno] = skb; -+ return NULL; -+ -+pkt_drop: -+ priv->skb_inflight[qno] = NULL; -+ -+ if (skb) { -+ kfree_skb(skb); -+ } else { -+ kfree(buf_addr); -+ } -+ -+ priv->stats.rx_errors++; -+ -+ return NULL; -+} -+ -+ -+/** pfe_eth_poll -+ */ -+static int pfe_eth_poll(struct pfe_eth_priv_s *priv, struct napi_struct *napi, unsigned int qno, int budget) -+{ -+ struct net_device *dev = priv->dev; -+ struct sk_buff *skb; -+ int work_done = 0; -+ unsigned int len; -+ -+ netif_info(priv, intr, priv->dev, "%s\n", __func__); -+ -+#ifdef PFE_ETH_NAPI_STATS -+ priv->napi_counters[NAPI_POLL_COUNT]++; -+#endif -+ -+ do { -+ skb = pfe_eth_rx_skb(dev, priv, qno); -+ -+ if (!skb) -+ break; -+ -+ len = skb->len; -+ -+ /* Packet will be processed */ -+ skb->protocol = eth_type_trans(skb, dev); -+ -+ netif_receive_skb(skb); -+ -+ priv->stats.rx_packets++; -+ priv->stats.rx_bytes += len; -+ -+ dev->last_rx = jiffies; -+ -+ work_done++; -+ -+#ifdef PFE_ETH_NAPI_STATS -+ priv->napi_counters[NAPI_PACKET_COUNT]++; -+#endif -+ -+ } while (work_done < budget); -+ -+ /* If no Rx receive nor cleanup work was done, exit polling mode. -+ * No more netif_running(dev) check is required here , as this is checked in -+ * net/core/dev.c ( 2.6.33.5 kernel specific). -+ */ -+ if (work_done < budget) { -+ napi_complete(napi); -+ -+ hif_lib_event_handler_start(&priv->client, EVENT_RX_PKT_IND, qno); -+ } -+#ifdef PFE_ETH_NAPI_STATS -+ else -+ priv->napi_counters[NAPI_FULL_BUDGET_COUNT]++; -+#endif -+ -+ return work_done; -+} -+ -+/** pfe_eth_lro_poll -+ */ -+static int pfe_eth_lro_poll(struct napi_struct *napi, int budget) -+{ -+ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, lro_napi); -+ -+ netif_info(priv, intr, priv->dev, "%s\n", __func__); -+ -+ return pfe_eth_poll(priv, napi, 2, budget); -+} -+ -+ -+/** pfe_eth_low_poll -+ */ -+static int pfe_eth_low_poll(struct napi_struct *napi, int budget) -+{ -+ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, low_napi); -+ -+ netif_info(priv, intr, priv->dev, "%s\n", __func__); -+ -+ return pfe_eth_poll(priv, napi, 1, budget); -+} -+ -+/** pfe_eth_high_poll -+ */ -+static int pfe_eth_high_poll(struct napi_struct *napi, int budget ) -+{ -+ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, high_napi); -+ -+ netif_info(priv, intr, priv->dev, "%s\n", __func__); -+ -+ return pfe_eth_poll(priv, napi, 0, budget); -+} -+ -+static const struct net_device_ops pfe_netdev_ops = { -+ .ndo_open = pfe_eth_open, -+ .ndo_stop = pfe_eth_close, -+ .ndo_start_xmit = pfe_eth_send_packet, -+ .ndo_select_queue = pfe_eth_select_queue, -+ .ndo_get_stats = pfe_eth_get_stats, -+ .ndo_change_mtu = pfe_eth_change_mtu, -+ .ndo_set_mac_address = pfe_eth_set_mac_address, -+ .ndo_set_rx_mode = pfe_eth_set_multi, -+ .ndo_set_features = pfe_eth_set_features, -+ .ndo_fix_features = pfe_eth_fix_features, -+ .ndo_validate_addr = eth_validate_addr, -+}; -+ -+ -+/** pfe_eth_init_one -+ */ -+ -+static int pfe_eth_init_one( struct pfe *pfe, int id ) -+{ -+ struct net_device *dev = NULL; -+ struct pfe_eth_priv_s *priv = NULL; -+ struct comcerto_eth_platform_data *einfo; -+ struct comcerto_mdio_platform_data *minfo; -+ struct comcerto_pfe_platform_data *pfe_info; -+ int err; -+ -+ /* Extract pltform data */ -+#if defined(CONFIG_PLATFORM_EMULATION) || defined(CONFIG_PLATFORM_PCI) -+ pfe_info = (struct comcerto_pfe_platform_data *) &comcerto_pfe_pdata; -+#else -+ pfe_info = (struct comcerto_pfe_platform_data *) pfe->dev->platform_data; -+#endif -+ if (!pfe_info) { -+ printk(KERN_ERR "%s: pfe missing additional platform data\n", __func__); -+ err = -ENODEV; -+ goto err0; -+ } -+ -+ einfo = (struct comcerto_eth_platform_data *) pfe_info->comcerto_eth_pdata; -+ -+ /* einfo never be NULL, but no harm in having this check */ -+ if (!einfo) { -+ printk(KERN_ERR "%s: pfe missing additional gemacs platform data\n", __func__); -+ err = -ENODEV; -+ goto err0; -+ } -+ -+ minfo = (struct comcerto_mdio_platform_data *) pfe_info->comcerto_mdio_pdata; -+ -+ /* einfo never be NULL, but no harm in having this check */ -+ if (!minfo) { -+ printk(KERN_ERR "%s: pfe missing additional mdios platform data\n", __func__); -+ err = -ENODEV; -+ goto err0; -+ } -+ -+ /* -+ * FIXME: Need to check some flag in "einfo" to know whether -+ * GEMAC is enabled Or not. -+ */ -+ -+ /* Create an ethernet device instance */ -+ dev = alloc_etherdev_mq(sizeof (*priv), emac_txq_cnt); -+ -+ if (!dev) { -+ printk(KERN_ERR "%s: gemac %d device allocation failed\n", __func__, einfo[id].gem_id); -+ err = -ENOMEM; -+ goto err0; -+ } -+ -+ priv = netdev_priv(dev); -+ priv->dev = dev; -+ priv->id = einfo[id].gem_id; -+ priv->pfe = pfe; -+ -+#if defined(CONFIG_PLATFORM_C2000) -+ /* get gemac tx clock */ -+ priv->gemtx_clk = clk_get(NULL, "gemtx"); -+ -+ if (IS_ERR(priv->gemtx_clk)) { -+ printk(KERN_ERR "%s: Unable to get the clock for gemac %d\n", __func__, priv->id); -+ err = -ENODEV; -+ goto err1; -+ } -+#endif -+ -+ pfe->eth.eth_priv[id] = priv; -+ -+ /* Set the info in the priv to the current info */ -+ priv->einfo = &einfo[id]; -+ priv->EMAC_baseaddr = cbus_emac_base[id]; -+ priv->PHY_baseaddr = cbus_emac_base[0]; -+ priv->mdio_muxval = einfo[id].mdio_muxval; -+ priv->GPI_baseaddr = cbus_gpi_base[id]; -+ -+ /* FIXME : For now TMU queue numbers hardcoded, later should be taken from pfe.h */ -+#define HIF_GEMAC_TMUQ_BASE 6 -+ priv->low_tmuQ = HIF_GEMAC_TMUQ_BASE + (id * 2); -+ priv->high_tmuQ = priv->low_tmuQ + 1; -+ -+ spin_lock_init(&priv->lock); -+ priv->tx_timer.data = (unsigned long)priv; -+ priv->tx_timer.function = pfe_eth_tx_timeout; -+ priv->tx_timer.expires = jiffies + ( COMCERTO_TX_RECOVERY_TIMEOUT_MS * HZ )/1000; -+ init_timer(&priv->tx_timer); -+ -+ pfe_eth_fast_tx_timeout_init(priv); -+ -+ /* Copy the station address into the dev structure, */ -+ memcpy(dev->dev_addr, einfo[id].mac_addr, ETH_ALEN); -+ -+ /* Initialize mdio */ -+ if (minfo[id].enabled) { -+ if ((err = pfe_eth_mdio_init(priv, &minfo[id]))) { -+ netdev_err(dev, "%s: pfe_eth_mdio_init() failed\n", __func__); -+ goto err2; -+ } -+ } -+ -+ dev->mtu = 1500; -+ -+ /* supported features */ -+ dev->hw_features = NETIF_F_SG; -+ /* Enable after checksum offload is validated -+ dev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | -+ NETIF_F_SG; */ -+ -+ /* enabled by default */ -+ dev->features = dev->hw_features; -+ -+ priv->usr_features = dev->features; -+ -+ dev->netdev_ops = &pfe_netdev_ops; -+ -+ dev->ethtool_ops = &pfe_ethtool_ops; -+ -+ /* Enable basic messages by default */ -+ priv->msg_enable = NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK | NETIF_MSG_PROBE; -+ -+ netif_napi_add(dev, &priv->low_napi, pfe_eth_low_poll, HIF_RX_POLL_WEIGHT - 16); -+ netif_napi_add(dev, &priv->high_napi, pfe_eth_high_poll, HIF_RX_POLL_WEIGHT - 16); -+ netif_napi_add(dev, &priv->lro_napi, pfe_eth_lro_poll, HIF_RX_POLL_WEIGHT - 16); -+ -+ err = register_netdev(dev); -+ -+ if (err) { -+ netdev_err(dev, "register_netdev() failed\n"); -+ goto err3; -+ } -+ -+ if (!(priv->einfo->phy_flags & GEMAC_NO_PHY)) { -+ err = pfe_phy_init(dev); -+ if (err) { -+ netdev_err(dev, "%s: pfe_phy_init() failed\n", __func__); -+ goto err4; -+ } -+ } -+ -+ -+ /* Create all the sysfs files */ -+ if(pfe_eth_sysfs_init(dev)) -+ goto err4; -+ -+ netif_info(priv, probe, dev, "%s: created interface, baseaddr: %p\n", __func__, priv->EMAC_baseaddr); -+ -+ return 0; -+err4: -+ unregister_netdev(dev); -+err3: -+ pfe_eth_mdio_exit(priv->mii_bus); -+err2: -+#if defined(CONFIG_PLATFORM_C2000) -+ clk_put(priv->gemtx_clk); -+err1: -+#endif -+ free_netdev(priv->dev); -+ -+err0: -+ return err; -+} -+ -+/** pfe_eth_init -+ */ -+int pfe_eth_init(struct pfe *pfe) -+{ -+ int ii = 0; -+ int err; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ cbus_emac_base[0] = EMAC1_BASE_ADDR; -+ cbus_emac_base[1] = EMAC2_BASE_ADDR; -+ -+ cbus_gpi_base[0] = EGPI1_BASE_ADDR; -+ cbus_gpi_base[1] = EGPI2_BASE_ADDR; -+ -+#if !defined(CONFIG_PLATFORM_LS1012A) -+ cbus_emac_base[2] = EMAC3_BASE_ADDR; -+ cbus_gpi_base[2] = EGPI3_BASE_ADDR; -+#endif -+ -+ for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) { -+ if ((err = pfe_eth_init_one(pfe, ii))) -+ goto err0; -+ } -+ -+ return 0; -+ -+err0: -+ while(ii--){ -+ pfe_eth_exit_one( pfe->eth.eth_priv[ii] ); -+ } -+ -+ /* Register three network devices in the kernel */ -+ return err; -+} -+ -+/** pfe_eth_exit_one -+ */ -+static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv) -+{ -+ netif_info(priv, probe, priv->dev, "%s\n", __func__); -+ -+ pfe_eth_sysfs_exit(priv->dev); -+ -+#if defined(CONFIG_PLATFORM_C2000) -+ clk_put(priv->gemtx_clk); -+#endif -+ -+ unregister_netdev(priv->dev); -+ -+ pfe_eth_mdio_exit(priv->mii_bus); -+ -+ if (!(priv->einfo->phy_flags & GEMAC_NO_PHY)) -+ pfe_phy_exit(priv->dev); -+ -+ free_netdev(priv->dev); -+} -+ -+/** pfe_eth_exit -+ */ -+void pfe_eth_exit(struct pfe *pfe) -+{ -+ int ii; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ for(ii = 0; ii < NUM_GEMAC_SUPPORT; ii++ ) { -+ /* -+ * FIXME: Need to check some flag in "einfo" to know whether -+ * GEMAC is enabled Or not. -+ */ -+ -+ pfe_eth_exit_one(pfe->eth.eth_priv[ii]); -+ } -+} -+ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_eth.h -@@ -0,0 +1,384 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _PFE_ETH_H_ -+#define _PFE_ETH_H_ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define PFE_ETH_NAPI_STATS -+#define PFE_ETH_TX_STATS -+ -+#define PFE_ETH_FRAGS_MAX (65536/HIF_RX_PKT_MIN_SIZE) -+#define LRO_LEN_COUNT_MAX 32 -+#define LRO_NB_COUNT_MAX 32 -+ -+#if defined(CONFIG_PLATFORM_PCI) || defined(CONFIG_PLATFORM_EMULATION) || defined(CONFIG_PLATFORM_LS1012A) -+ -+#define CONFIG_COMCERTO_GEMAC 1 -+ -+#define CONFIG_COMCERTO_USE_MII 1 -+#define CONFIG_COMCERTO_USE_RMII 2 -+#define CONFIG_COMCERTO_USE_GMII 4 -+#define CONFIG_COMCERTO_USE_RGMII 8 -+#define CONFIG_COMCERTO_USE_SGMII 16 -+ -+#define GEMAC_SW_CONF (1 << 8) | (1 << 11) // GEMAC configured by SW -+#define GEMAC_PHY_CONF 0 // GEMAC configured by phy lines (not for MII/GMII) -+#define GEMAC_SW_FULL_DUPLEX (1 << 9) -+#define GEMAC_SW_SPEED_10M (0 << 12) -+#define GEMAC_SW_SPEED_100M (1 << 12) -+#define GEMAC_SW_SPEED_1G (2 << 12) -+ -+#define GEMAC_NO_PHY (1 << 0) // set if no phy connected to MAC (ex ethernet switch). In this case use MAC fixed configuration -+#define GEMAC_PHY_RGMII_ADD_DELAY (1 << 1) -+ -+/* gemac to interface name assignment */ -+#define GEMAC0_ITF_NAME "eth5" -+#define GEMAC1_ITF_NAME "eth6" -+#define GEMAC2_ITF_NAME "eth7" -+ -+#define GEMAC0_MAC { 0x00, 0xED, 0xCD, 0xEF, 0xAA, 0xCC } -+#define GEMAC1_MAC { 0x00, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E } -+ -+struct comcerto_eth_platform_data { -+ /* device specific information */ -+ u32 device_flags; -+ char name[16]; -+ -+ -+ /* board specific information */ -+ u32 mii_config; -+ u32 gemac_mode; -+ u32 phy_flags; -+ u32 gem_id; -+ u32 bus_id; -+ u32 phy_id; -+ u32 mdio_muxval; -+ u8 mac_addr[ETH_ALEN]; -+}; -+ -+struct comcerto_mdio_platform_data { -+ int enabled; -+ int irq[32]; -+ u32 phy_mask; -+ int mdc_div; -+}; -+ -+struct comcerto_pfe_platform_data -+{ -+ struct comcerto_eth_platform_data comcerto_eth_pdata[3]; -+ struct comcerto_mdio_platform_data comcerto_mdio_pdata[3]; -+}; -+#if !defined(CONFIG_PLATFORM_LS1012A) -+static struct comcerto_pfe_platform_data comcerto_pfe_pdata = { -+ .comcerto_eth_pdata[0] = { -+ .name = GEMAC0_ITF_NAME, -+ .device_flags = CONFIG_COMCERTO_GEMAC, -+ .mii_config = CONFIG_COMCERTO_USE_MII, -+ .gemac_mode = GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_100M, -+#if defined(CONFIG_PLATFORM_EMULATION) || defined(CONFIG_PLATFORM_PCI) -+ .phy_flags = GEMAC_NO_PHY, -+#else -+ .phy_flags = GEMAC_PHY_RGMII_ADD_DELAY, -+#endif -+ .bus_id = 0, -+ .phy_id = 0, -+ .gem_id = 0, -+ .mac_addr = (u8[])GEMAC0_MAC, -+ }, -+ -+ .comcerto_eth_pdata[1] = { -+ .name = GEMAC1_ITF_NAME, -+ .device_flags = CONFIG_COMCERTO_GEMAC, -+ .mii_config = CONFIG_COMCERTO_USE_RGMII, -+ .gemac_mode = GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G, -+ .phy_flags = GEMAC_NO_PHY, -+ .gem_id = 1, -+ .mac_addr = (u8[])GEMAC1_MAC, -+ }, -+ -+ .comcerto_eth_pdata[2] = { -+ .name = GEMAC2_ITF_NAME, -+ }, -+ -+ .comcerto_mdio_pdata[0] = { -+ .enabled = 1, -+ .phy_mask = 0xFFFFFFFE, -+ .mdc_div = 96, -+ .irq = { -+ [0] = PHY_POLL, -+ }, -+ }, -+}; -+#endif -+#endif -+ -+#if defined(CONFIG_PLATFORM_LS1012A) -+#define NUM_GEMAC_SUPPORT 2 -+#define DRV_NAME "ls1012a-geth" -+#else -+#define NUM_GEMAC_SUPPORT 3 -+#define DRV_NAME "c2000-geth" -+#endif -+#define COMCERTO_INFOSTR_LEN 32 -+#define COMCERTO_TX_RECOVERY_TIMEOUT_MS 500 -+#define COMCERTO_TX_FAST_RECOVERY_TIMEOUT_MS 3 -+#define TX_POLL_TIMEOUT_MS 1000 -+ -+#define EMAC_TXQ_CNT 16 -+#define EMAC_TXQ_DEPTH (HIF_TX_DESC_NT) -+ -+#define JUMBO_FRAME_SIZE 10258 -+/** -+ * Client Tx queue threshold, for txQ flush condition. -+ * It must be smaller than the queue size (in case we ever change it in the future). -+ */ -+#define HIF_CL_TX_FLUSH_MARK 32 -+ -+/** -+ * Max number of TX resources (HIF descriptors or skbs) that will be released -+ * in a single go during batch recycling. -+ * Should be lower than the flush mark so the SW can provide the HW with a -+ * continuous stream of packets instead of bursts. -+ */ -+#define TX_FREE_MAX_COUNT 16 -+#define EMAC_RXQ_CNT 3 -+#define EMAC_RXQ_DEPTH HIF_RX_DESC_NT /* make sure clients can receive a full burst of packets */ -+#define EMAC_RMON_TXBYTES_POS 0x00 -+#define EMAC_RMON_RXBYTES_POS 0x14 -+ -+#define EMAC_QUEUENUM_MASK (emac_txq_cnt - 1) -+#define EMAC_MDIO_TIMEOUT 1000 -+#define MAX_UC_SPEC_ADDR_REG 31 -+ -+ -+/* The set of statistics registers implemented in the Cadence MAC. -+ * The statistics registers implemented are a subset of all the statistics -+ * available, but contains all the compulsory ones. -+ * For full descriptions on the registers, refer to the Cadence MAC programmers -+ * guide or the IEEE 802.3 specifications. -+ */ -+struct gemac_stats{ -+ u32 octets_tx_bot; /* Lower 32-bits for number of octets tx'd */ -+ u32 octets_tx_top; /* Upper 16-bits for number of octets tx'd */ -+ u32 frames_tx; /* Number of frames transmitted OK */ -+ u32 broadcast_tx; /* Number of broadcast frames transmitted */ -+ u32 multicast_tx; /* Number of multicast frames transmitted */ -+ u32 pause_tx; /* Number of pause frames transmitted. */ -+ u32 frame64_tx; /* Number of 64byte frames transmitted */ -+ u32 frame65_127_tx; /* Number of 65-127 byte frames transmitted */ -+ u32 frame128_255_tx; /* Number of 128-255 byte frames transmitted */ -+ u32 frame256_511_tx; /* Number of 256-511 byte frames transmitted */ -+ u32 frame512_1023_tx; /* Number of 512-1023 byte frames transmitted */ -+ u32 frame1024_1518_tx; /* Number of 1024-1518 byte frames transmitted*/ -+ u32 frame1519_tx; /* Number of frames greater than 1518 bytes tx*/ -+ u32 tx_urun; /* Transmit underrun errors due to DMA */ -+ u32 single_col; /* Number of single collision frames */ -+ u32 multi_col; /* Number of multi collision frames */ -+ u32 excess_col; /* Number of excessive collision frames. */ -+ u32 late_col; /* Collisions occuring after slot time */ -+ u32 def_tx; /* Frames deferred due to crs */ -+ u32 crs_errors; /* Errors caused by crs not being asserted. */ -+ u32 octets_rx_bot; /* Lower 32-bits for number of octets rx'd */ -+ u32 octets_rx_top; /* Upper 16-bits for number of octets rx'd */ -+ u32 frames_rx; /* Number of frames received OK */ -+ u32 broadcast_rx; /* Number of broadcast frames received */ -+ u32 multicast_rx; /* Number of multicast frames received */ -+ u32 pause_rx; /* Number of pause frames received. */ -+ u32 frame64_rx; /* Number of 64byte frames received */ -+ u32 frame65_127_rx; /* Number of 65-127 byte frames received */ -+ u32 frame128_255_rx; /* Number of 128-255 byte frames received */ -+ u32 frame256_511_rx; /* Number of 256-511 byte frames received */ -+ u32 frame512_1023_rx; /* Number of 512-1023 byte frames received */ -+ u32 frame1024_1518_rx; /* Number of 1024-1518 byte frames received*/ -+ u32 frame1519_rx; /* Number of frames greater than 1518 bytes rx*/ -+ u32 usize_frames; /* Frames received less than min of 64 bytes */ -+ u32 excess_length; /* Number of excessive length frames rx */ -+ u32 jabbers; /* Excessive length + crc or align errors. */ -+ u32 fcs_errors; /* Number of frames received with crc errors */ -+ u32 length_check_errors;/* Number of frames with incorrect length */ -+ u32 rx_symbol_errors; /* Number of times rx_er asserted during rx */ -+ u32 align_errors; /* Frames received without integer no. bytes */ -+ u32 rx_res_errors; /* Number of times buffers ran out during rx */ -+ u32 rx_orun; /* Receive overrun errors due to DMA */ -+ u32 ip_cksum; /* IP header checksum errors */ -+ u32 tcp_cksum; /* TCP checksum errors */ -+ u32 udp_cksum; /* UDP checksum errors */ -+}; -+ -+#define EMAC_REG_SPACE sizeof(struct gemac_reg) -+#define EMAC_RMON_LEN (sizeof(struct gemac_stats)/sizeof(u32)) -+ -+ -+struct pfe_eth_fast_timer { -+ int queuenum; -+ struct hrtimer timer; -+ void * base; -+}; -+ -+typedef struct pfe_eth_priv_s -+{ -+ struct pfe *pfe; -+ struct hif_client_s client; -+ struct napi_struct lro_napi; -+ struct napi_struct low_napi; -+ struct napi_struct high_napi; -+ int low_tmuQ; -+ int high_tmuQ; -+ struct net_device_stats stats; -+ struct net_device *dev; -+ int id; -+ int promisc; -+ unsigned int msg_enable; -+ unsigned int usr_features; -+ -+ spinlock_t lock; -+ unsigned int event_status; -+ int irq; -+ void* EMAC_baseaddr; -+ void* PHY_baseaddr; /* This points to the EMAC base from where we access PHY */ -+ void* GPI_baseaddr; -+ int mdio_muxval; -+ /* PHY stuff */ -+ struct phy_device *phydev; -+ int oldspeed; -+ int oldduplex; -+ int oldlink; -+ /* mdio info */ -+ int mdc_div; -+ struct mii_bus *mii_bus; -+ struct clk *gemtx_clk; -+ int wol; -+ -+ int default_priority; -+ struct timer_list tx_timer; -+ struct pfe_eth_fast_timer fast_tx_timeout[EMAC_TXQ_CNT]; -+ -+ struct comcerto_eth_platform_data *einfo; -+ struct sk_buff *skb_inflight[EMAC_RXQ_CNT + 6]; -+ -+#ifdef PFE_ETH_LRO_STATS -+ unsigned int lro_len_counters[LRO_LEN_COUNT_MAX]; -+ unsigned int lro_nb_counters[LRO_NB_COUNT_MAX]; //TODO change to exact max number when RX scatter done -+#endif -+ -+ -+#ifdef PFE_ETH_TX_STATS -+ unsigned int stop_queue_total[EMAC_TXQ_CNT]; -+ unsigned int stop_queue_hif[EMAC_TXQ_CNT]; -+ unsigned int stop_queue_hif_client[EMAC_TXQ_CNT]; -+ unsigned int stop_queue_credit[EMAC_TXQ_CNT]; -+ unsigned int clean_fail[EMAC_TXQ_CNT]; -+ unsigned int was_stopped[EMAC_TXQ_CNT]; -+#endif -+ -+#ifdef PFE_ETH_NAPI_STATS -+ unsigned int napi_counters[NAPI_MAX_COUNT]; -+#endif -+ unsigned int frags_inflight[EMAC_RXQ_CNT + 6]; -+ -+}pfe_eth_priv_t; -+ -+struct pfe_eth { -+ struct pfe_eth_priv_s *eth_priv[3]; -+}; -+ -+int pfe_eth_init(struct pfe *pfe); -+void pfe_eth_exit(struct pfe *pfe); -+int pfe_eth_suspend(struct net_device *dev); -+int pfe_eth_resume(struct net_device *dev); -+int pfe_eth_mdio_reset(struct mii_bus *bus); -+ -+/** pfe_compute_csum -+ * -+ */ -+static int inline pfe_compute_csum(struct sk_buff *skb) -+{ -+ struct skb_shared_info *sh; -+ unsigned int nr_frags; -+ skb_frag_t *f; -+ u32 csum = 0; -+ int i; -+ int len; -+ -+ /* Make sure that no intermediate buffers/fragments are odd byte aligned */ -+ if (skb_is_nonlinear(skb)) { -+ int linearize = 0; -+ -+ sh = skb_shinfo(skb); -+ nr_frags = sh->nr_frags; -+ len = skb_headlen(skb) - skb_transport_offset(skb); -+ -+ if (len & 0x1) { -+ linearize = 1; -+ //printk("#1 Odd length %d\n", len); -+ } -+ else { -+ for (i = 0; i < nr_frags - 1; i++) { -+ f = &sh->frags[i]; -+ len = skb_frag_size(f); -+ -+ if (len & 0x1) { -+ linearize = 1; -+ //printk("#2 %d Odd length %d\n", i, len); -+ break; -+ } -+ } -+ } -+ -+ if (linearize) -+ if (skb_linearize(skb)) -+ return -1; -+ } -+ -+ /* Compute checksum */ -+ if (!skb_is_nonlinear(skb)) { -+ *(u16*)(skb_transport_header(skb) + skb->csum_offset) = csum_fold(csum_partial(skb_transport_header(skb), skb->len - skb_transport_offset(skb), 0)); -+ } -+ else { -+ sh = skb_shinfo(skb); -+ nr_frags = sh->nr_frags; -+ -+ if (nr_frags) { -+ csum = csum_partial(skb_transport_header(skb), skb_headlen(skb) - skb_transport_offset(skb), 0); -+ -+ for (i = 0; i < nr_frags - 1; i++) { -+ f = &sh->frags[i]; -+ csum = csum_partial(skb_frag_address(f), skb_frag_size(f), csum); -+ } -+ -+ f = &sh->frags[i]; -+ *(u16*)(skb_transport_header(skb) + skb->csum_offset) = csum_fold(csum_partial(skb_frag_address(f), skb_frag_size(f), csum)); -+ } -+ } -+ -+ return 0; -+} -+ -+ -+ -+#endif /* _PFE_ETH_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_firmware.c -@@ -0,0 +1,322 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+/** @file -+ * Contains all the functions to handle parsing and loading of PE firmware files. -+ */ -+#include -+ -+#include "pfe_mod.h" -+#include "pfe_firmware.h" -+#include "pfe/pfe.h" -+ -+static Elf32_Shdr * get_elf_section_header(const struct firmware *fw, const char *section) -+{ -+ Elf32_Ehdr *elf_hdr = (Elf32_Ehdr *)fw->data; -+ Elf32_Shdr *shdr, *shdr_shstr; -+ Elf32_Off e_shoff = be32_to_cpu(elf_hdr->e_shoff); -+ Elf32_Half e_shentsize = be16_to_cpu(elf_hdr->e_shentsize); -+ Elf32_Half e_shnum = be16_to_cpu(elf_hdr->e_shnum); -+ Elf32_Half e_shstrndx = be16_to_cpu(elf_hdr->e_shstrndx); -+ Elf32_Off shstr_offset; -+ Elf32_Word sh_name; -+ const char *name; -+ int i; -+ -+ /* Section header strings */ -+ shdr_shstr = (Elf32_Shdr *)(fw->data + e_shoff + e_shstrndx * e_shentsize); -+ shstr_offset = be32_to_cpu(shdr_shstr->sh_offset); -+ -+ for (i = 0; i < e_shnum; i++) { -+ shdr = (Elf32_Shdr *)(fw->data + e_shoff + i * e_shentsize); -+ -+ sh_name = be32_to_cpu(shdr->sh_name); -+ -+ name = (const char *)(fw->data + shstr_offset + sh_name); -+ -+ if (!strcmp(name, section)) -+ return shdr; -+ } -+ -+ printk(KERN_ERR "%s: didn't find section %s\n", __func__, section); -+ -+ return NULL; -+} -+ -+static unsigned long get_elf_section(const struct firmware *fw, const char *section) -+{ -+ Elf32_Shdr *shdr = get_elf_section_header(fw, section); -+ -+ if (shdr) -+ return be32_to_cpu(shdr->sh_addr); -+ else -+ return -1; -+} -+ -+#if defined(CFG_DIAGS) -+static int pfe_get_diags_info(const struct firmware *fw, struct pfe_diags_info *diags_info) -+{ -+ Elf32_Shdr *shdr; -+ unsigned long offset, size; -+ -+ shdr = get_elf_section_header(fw, ".pfe_diags_str"); -+ if (shdr) -+ { -+ offset = be32_to_cpu(shdr->sh_offset); -+ size = be32_to_cpu(shdr->sh_size); -+ diags_info->diags_str_base = be32_to_cpu(shdr->sh_addr); -+ diags_info->diags_str_size = size; -+ diags_info->diags_str_array = pfe_kmalloc(size, GFP_KERNEL); -+ memcpy(diags_info->diags_str_array, fw->data+offset, size); -+ -+ return 0; -+ } else -+ { -+ return -1; -+ } -+} -+#endif -+ -+static void pfe_check_version_info(const struct firmware *fw) -+{ -+ static char *version = NULL; -+ -+ Elf32_Shdr *shdr = get_elf_section_header(fw, ".version"); -+ -+ if (shdr) -+ { -+ if(!version) -+ { -+ /* this is the first fw we load, use its version string as reference (whatever it is) */ -+ version = (char *)(fw->data + be32_to_cpu(shdr->sh_offset)); -+ -+ printk(KERN_INFO "PFE binary version: %s\n", version); -+ } -+ else -+ { -+ /* already have loaded at least one firmware, check sequence can start now */ -+ if(strcmp(version, (char *)(fw->data + be32_to_cpu(shdr->sh_offset)))) -+ { -+ printk(KERN_INFO "WARNING: PFE firmware binaries from incompatible version\n"); -+ } -+ } -+ } -+ else -+ { -+ /* version cannot be verified, a potential issue that should be reported */ -+ printk(KERN_INFO "WARNING: PFE firmware binaries from incompatible version\n"); -+ } -+} -+ -+/** PFE elf firmware loader. -+* Loads an elf firmware image into a list of PE's (specified using a bitmask) -+* -+* @param pe_mask Mask of PE id's to load firmware to -+* @param fw Pointer to the firmware image -+* -+* @return 0 on sucess, a negative value on error -+* -+*/ -+int pfe_load_elf(int pe_mask, const struct firmware *fw, struct pfe *pfe) -+{ -+ Elf32_Ehdr *elf_hdr = (Elf32_Ehdr *)fw->data; -+ Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum); -+ Elf32_Shdr *shdr = (Elf32_Shdr *) (fw->data + be32_to_cpu(elf_hdr->e_shoff)); -+ int id, section; -+ int rc; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ /* Some sanity checks */ -+ if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG)) -+ { -+ printk(KERN_ERR "%s: incorrect elf magic number\n", __func__); -+ return -EINVAL; -+ } -+ -+ if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32) -+ { -+ printk(KERN_ERR "%s: incorrect elf class(%x)\n", __func__, elf_hdr->e_ident[EI_CLASS]); -+ return -EINVAL; -+ } -+ -+ if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB) -+ { -+ printk(KERN_ERR "%s: incorrect elf data(%x)\n", __func__, elf_hdr->e_ident[EI_DATA]); -+ return -EINVAL; -+ } -+ -+ if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC) -+ { -+ printk(KERN_ERR "%s: incorrect elf file type(%x)\n", __func__, be16_to_cpu(elf_hdr->e_type)); -+ return -EINVAL; -+ } -+ -+ for (section = 0; section < sections; section++, shdr++) -+ { -+ if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR))) -+ continue; -+ -+ for (id = 0; id < MAX_PE; id++) -+ if (pe_mask & (1 << id)) -+ { -+ rc = pe_load_elf_section(id, fw->data, shdr, pfe->dev); -+ if (rc < 0) -+ goto err; -+ } -+ } -+ -+ pfe_check_version_info(fw); -+ -+ return 0; -+ -+err: -+ return rc; -+} -+ -+ -+/** PFE firmware initialization. -+* Loads different firmware files from filesystem. -+* Initializes PE IMEM/DMEM and UTIL-PE DDR -+* Initializes control path symbol addresses (by looking them up in the elf firmware files -+* Takes PE's out of reset -+* -+* @return 0 on sucess, a negative value on error -+* -+*/ -+int pfe_firmware_init(struct pfe *pfe) -+{ -+ const struct firmware *class_fw, *tmu_fw; -+ int rc = 0; -+#if !defined(CONFIG_UTIL_DISABLED) -+ const char* util_fw_name; -+ const struct firmware *util_fw; -+#endif -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ if (request_firmware(&class_fw, CLASS_FIRMWARE_FILENAME, pfe->dev)) { -+ printk(KERN_ERR "%s: request firmware %s failed\n", __func__, CLASS_FIRMWARE_FILENAME); -+ rc = -ETIMEDOUT; -+ goto err0; -+ } -+ -+ if (request_firmware(&tmu_fw, TMU_FIRMWARE_FILENAME, pfe->dev)) { -+ printk(KERN_ERR "%s: request firmware %s failed\n", __func__, TMU_FIRMWARE_FILENAME); -+ rc = -ETIMEDOUT; -+ goto err1; -+ } -+#if !defined(CONFIG_UTIL_DISABLED) -+#if defined(CONFIG_PLATFORM_C2000) -+ util_fw_name = (system_rev == 0) ? UTIL_REVA0_FIRMWARE_FILENAME : UTIL_FIRMWARE_FILENAME; -+#else -+ util_fw_name = UTIL_FIRMWARE_FILENAME; -+#endif -+ -+ if (request_firmware(&util_fw, util_fw_name, pfe->dev)) { -+ printk(KERN_ERR "%s: request firmware %s failed\n", __func__, util_fw_name); -+ rc = -ETIMEDOUT; -+ goto err2; -+ } -+#endif -+ rc = pfe_load_elf(CLASS_MASK, class_fw, pfe); -+ if (rc < 0) { -+ printk(KERN_ERR "%s: class firmware load failed\n", __func__); -+ goto err3; -+ } -+ -+ pfe->ctrl.class_dmem_sh = get_elf_section(class_fw, ".dmem_sh"); -+ pfe->ctrl.class_pe_lmem_sh = get_elf_section(class_fw, ".pe_lmem_sh"); -+ -+#if defined(CFG_DIAGS) -+ rc = pfe_get_diags_info(class_fw, &pfe->diags.class_diags_info); -+ if (rc < 0) { -+ printk (KERN_WARNING "PFE diags won't be available for class PEs\n"); -+ rc = 0; -+ } -+#endif -+ -+ printk(KERN_INFO "%s: class firmware loaded %#lx %#lx\n", __func__, pfe->ctrl.class_dmem_sh, pfe->ctrl.class_pe_lmem_sh); -+ -+ rc = pfe_load_elf(TMU_MASK, tmu_fw, pfe); -+ if (rc < 0) { -+ printk(KERN_ERR "%s: tmu firmware load failed\n", __func__); -+ goto err3; -+ } -+ -+ pfe->ctrl.tmu_dmem_sh = get_elf_section(tmu_fw, ".dmem_sh"); -+ -+ printk(KERN_INFO "%s: tmu firmware loaded %#lx\n", __func__, pfe->ctrl.tmu_dmem_sh); -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+ rc = pfe_load_elf(UTIL_MASK, util_fw, pfe); -+ if (rc < 0) { -+ printk(KERN_ERR "%s: util firmware load failed\n", __func__); -+ goto err3; -+ } -+ -+ pfe->ctrl.util_dmem_sh = get_elf_section(util_fw, ".dmem_sh"); -+ pfe->ctrl.util_ddr_sh = get_elf_section(util_fw, ".ddr_sh"); -+ -+#if defined(CFG_DIAGS) -+ rc = pfe_get_diags_info(util_fw, &pfe->diags.util_diags_info); -+ if (rc < 0) { -+ printk(KERN_WARNING "PFE diags won't be available for util PE\n"); -+ rc = 0; -+ } -+#endif -+ -+ printk(KERN_INFO "%s: util firmware loaded %#lx\n", __func__, pfe->ctrl.util_dmem_sh); -+ -+ util_enable(); -+#endif -+ -+ tmu_enable(0xf); -+ class_enable(); -+ -+err3: -+#if !defined(CONFIG_UTIL_DISABLED) -+ release_firmware(util_fw); -+ -+err2: -+#endif -+ release_firmware(tmu_fw); -+ -+err1: -+ release_firmware(class_fw); -+ -+err0: -+ return rc; -+} -+ -+/** PFE firmware cleanup -+* Puts PE's in reset -+* -+* -+*/ -+void pfe_firmware_exit(struct pfe *pfe) -+{ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ class_disable(); -+ tmu_disable(0xf); -+#if !defined(CONFIG_UTIL_DISABLED) -+ util_disable(); -+#endif -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_firmware.h -@@ -0,0 +1,41 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _PFE_FIRMWARE_H_ -+#define _PFE_FIRMWARE_H_ -+ -+#if defined(CONFIG_PLATFORM_C2000) -+#define CLASS_FIRMWARE_FILENAME "class_c2000.elf" -+#define TMU_FIRMWARE_FILENAME "tmu_c2000.elf" -+#define UTIL_FIRMWARE_FILENAME "util_c2000.elf" -+#define UTIL_REVA0_FIRMWARE_FILENAME "util_c2000_revA0.elf" -+#else -+#define CLASS_FIRMWARE_FILENAME "ppfe_class_ls1012a.elf" -+#define TMU_FIRMWARE_FILENAME "ppfe_tmu_ls1012a.elf" -+#endif -+ -+#define PFE_FW_CHECK_PASS 0 -+#define PFE_FW_CHECK_FAIL 1 -+#define NUM_PFE_FW 3 -+ -+int pfe_firmware_init(struct pfe *pfe); -+void pfe_firmware_exit(struct pfe *pfe); -+ -+#endif /* _PFE_FIRMWARE_H_ */ -+ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hal.c -@@ -0,0 +1,2217 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+ -+#include "pfe_ctrl_hal.h" -+#include "pfe/pfe.h" -+ -+void *cbus_base_addr; -+void *ddr_base_addr; -+unsigned long ddr_phys_base_addr; -+unsigned int ddr_size; -+ -+static struct pe_info pe[MAX_PE]; -+ -+/** Initializes the PFE library. -+* Must be called before using any of the library functions. -+* -+* @param[in] cbus_base CBUS virtual base address (as mapped in the host CPU address space) -+* @param[in] ddr_base PFE DDR range virtual base address (as mapped in the host CPU address space) -+* @param[in] ddr_phys_base PFE DDR range physical base address (as mapped in platform) -+* @param[in] size PFE DDR range size (as defined by the host software) -+*/ -+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base, unsigned int size) -+{ -+ cbus_base_addr = cbus_base; -+ ddr_base_addr = ddr_base; -+ ddr_phys_base_addr = ddr_phys_base; -+ ddr_size = size; -+ -+ pe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0); -+ pe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0); -+ pe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE; -+ pe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; -+ pe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; -+ pe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; -+ -+ pe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1); -+ pe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1); -+ pe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE; -+ pe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; -+ pe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; -+ pe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; -+ -+ pe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2); -+ pe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2); -+ pe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE; -+ pe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; -+ pe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; -+ pe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; -+ -+ pe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3); -+ pe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3); -+ pe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE; -+ pe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; -+ pe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; -+ pe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; -+ -+#if !defined(CONFIG_PLATFORM_PCI) -+ pe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4); -+ pe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4); -+ pe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE; -+ pe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; -+ pe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; -+ pe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; -+ -+ pe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5); -+ pe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5); -+ pe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE; -+ pe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; -+ pe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; -+ pe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; -+#endif -+ pe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0); -+ pe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0); -+ pe[TMU0_ID].pmem_size = TMU_IMEM_SIZE; -+ pe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; -+ pe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; -+ pe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; -+ -+#if !defined(CONFIG_TMU_DUMMY) -+ pe[TMU1_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(1); -+ pe[TMU1_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(1); -+ pe[TMU1_ID].pmem_size = TMU_IMEM_SIZE; -+ pe[TMU1_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; -+ pe[TMU1_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; -+ pe[TMU1_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; -+ -+#if !defined(CONFIG_PLATFORM_LS1012A) -+ pe[TMU2_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(2); -+ pe[TMU2_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(2); -+ pe[TMU2_ID].pmem_size = TMU_IMEM_SIZE; -+ pe[TMU2_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; -+ pe[TMU2_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; -+ pe[TMU2_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; -+#endif -+ -+ pe[TMU3_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(3); -+ pe[TMU3_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(3); -+ pe[TMU3_ID].pmem_size = TMU_IMEM_SIZE; -+ pe[TMU3_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; -+ pe[TMU3_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; -+ pe[TMU3_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; -+#endif -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+ pe[UTIL_ID].dmem_base_addr = UTIL_DMEM_BASE_ADDR; -+ pe[UTIL_ID].mem_access_wdata = UTIL_MEM_ACCESS_WDATA; -+ pe[UTIL_ID].mem_access_addr = UTIL_MEM_ACCESS_ADDR; -+ pe[UTIL_ID].mem_access_rdata = UTIL_MEM_ACCESS_RDATA; -+#endif -+} -+ -+ -+/** Writes a buffer to PE internal memory from the host -+ * through indirect access registers. -+ * -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID) -+ * @param[in] src Buffer source address -+ * @param[in] mem_access_addr DMEM destination address (must be 32bit aligned) -+ * @param[in] len Number of bytes to copy -+ */ -+void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned int len) -+{ -+ u32 offset = 0, val, addr; -+ unsigned int len32 = len >> 2; -+ int i; -+ -+ addr = mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, 4); -+ -+ for (i = 0; i < len32; i++, offset += 4, src += 4) { -+ val = *(u32 *)src; -+ writel(cpu_to_be32(val), pe[id].mem_access_wdata); -+ writel(addr + offset, pe[id].mem_access_addr); -+ } -+ -+ if ((len = (len & 0x3))) { -+ val = 0; -+ -+ addr = (mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset; -+ -+ for (i = 0; i < len; i++, src++) -+ val |= (*(u8 *)src) << (8 * i); -+ -+ writel(cpu_to_be32(val), pe[id].mem_access_wdata); -+ writel(addr, pe[id].mem_access_addr); -+ } -+} -+ -+/** Writes a buffer to PE internal data memory (DMEM) from the host -+ * through indirect access registers. -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID) -+ * @param[in] src Buffer source address -+ * @param[in] dst DMEM destination address (must be 32bit aligned) -+ * @param[in] len Number of bytes to copy -+ */ -+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len) -+{ -+ pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | PE_MEM_ACCESS_DMEM, src, len); -+} -+ -+ -+/** Writes a buffer to PE internal program memory (PMEM) from the host -+ * through indirect access registers. -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID) -+ * @param[in] src Buffer source address -+ * @param[in] dst PMEM destination address (must be 32bit aligned) -+ * @param[in] len Number of bytes to copy -+ */ -+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len) -+{ -+ pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_IMEM, src, len); -+} -+ -+ -+/** Reads PE internal program memory (IMEM) from the host -+ * through indirect access registers. -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID) -+ * @param[in] addr PMEM read address (must be aligned on size) -+ * @param[in] size Number of bytes to read (maximum 4, must not cross 32bit boundaries) -+ * @return the data read (in PE endianess, i.e BE). -+ */ -+u32 pe_pmem_read(int id, u32 addr, u8 size) -+{ -+ u32 offset = addr & 0x3; -+ u32 mask = 0xffffffff >> ((4 - size) << 3); -+ u32 val; -+ -+ addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size); -+ -+ writel(addr, pe[id].mem_access_addr); -+ val = be32_to_cpu(readl(pe[id].mem_access_rdata)); -+ -+ return (val >> (offset << 3)) & mask; -+} -+ -+ -+/** Writes PE internal data memory (DMEM) from the host -+ * through indirect access registers. -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID) -+ * @param[in] addr DMEM write address (must be aligned on size) -+ * @param[in] val Value to write (in PE endianess, i.e BE) -+ * @param[in] size Number of bytes to write (maximum 4, must not cross 32bit boundaries) -+ */ -+void pe_dmem_write(int id, u32 val, u32 addr, u8 size) -+{ -+ u32 offset = addr & 0x3; -+ -+ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size); -+ -+ /* Indirect access interface is byte swapping data being written */ -+ writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata); -+ writel(addr, pe[id].mem_access_addr); -+} -+ -+ -+/** Reads PE internal data memory (DMEM) from the host -+ * through indirect access registers. -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID) -+ * @param[in] addr DMEM read address (must be aligned on size) -+ * @param[in] size Number of bytes to read (maximum 4, must not cross 32bit boundaries) -+ * @return the data read (in PE endianess, i.e BE). -+ */ -+u32 pe_dmem_read(int id, u32 addr, u8 size) -+{ -+ u32 offset = addr & 0x3; -+ u32 mask = 0xffffffff >> ((4 - size) << 3); -+ u32 val; -+ -+ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size); -+ -+ writel(addr, pe[id].mem_access_addr); -+ -+ /* Indirect access interface is byte swapping data being read */ -+ val = be32_to_cpu(readl(pe[id].mem_access_rdata)); -+ -+ return (val >> (offset << 3)) & mask; -+} -+ -+ -+/** This function is used to write to CLASS internal bus peripherals (ccu, pe-lem) from the host -+* through indirect access registers. -+* @param[in] val value to write -+* @param[in] addr Address to write to (must be aligned on size) -+* @param[in] size Number of bytes to write (1, 2 or 4) -+* -+*/ -+void class_bus_write(u32 val, u32 addr, u8 size) -+{ -+ u32 offset = addr & 0x3; -+ -+ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE); -+ -+ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE | (size << 24); -+ -+ writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA); -+ writel(addr, CLASS_BUS_ACCESS_ADDR); -+} -+ -+ -+/** Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host -+* through indirect access registers. -+* @param[in] addr Address to read from (must be aligned on size) -+* @param[in] size Number of bytes to read (1, 2 or 4) -+* @return the read data -+* -+*/ -+u32 class_bus_read(u32 addr, u8 size) -+{ -+ u32 offset = addr & 0x3; -+ u32 mask = 0xffffffff >> ((4 - size) << 3); -+ u32 val; -+ -+ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE); -+ -+ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24); -+ -+ writel(addr, CLASS_BUS_ACCESS_ADDR); -+ val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA)); -+ -+ return (val >> (offset << 3)) & mask; -+} -+ -+ -+/** Writes data to the cluster memory (PE_LMEM) -+* @param[in] dst PE LMEM destination address (must be 32bit aligned) -+* @param[in] src Buffer source address -+* @param[in] len Number of bytes to copy -+*/ -+void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len) -+{ -+ u32 len32 = len >> 2; -+ int i; -+ -+ for (i = 0; i < len32; i++, src += 4, dst += 4) -+ class_bus_write(*(u32 *)src, dst, 4); -+ -+ if (len & 0x2) -+ { -+ class_bus_write(*(u16 *)src, dst, 2); -+ src += 2; -+ dst += 2; -+ } -+ -+ if (len & 0x1) -+ { -+ class_bus_write(*(u8 *)src, dst, 1); -+ src++; -+ dst++; -+ } -+} -+ -+/** Writes value to the cluster memory (PE_LMEM) -+* @param[in] dst PE LMEM destination address (must be 32bit aligned) -+* @param[in] val Value to write -+* @param[in] len Number of bytes to write -+*/ -+void class_pe_lmem_memset(u32 dst, int val, unsigned int len) -+{ -+ u32 len32 = len >> 2; -+ int i; -+ -+ val = val | (val << 8) | (val << 16) | (val << 24); -+ -+ for (i = 0; i < len32; i++, dst += 4) -+ class_bus_write(val, dst, 4); -+ -+ if (len & 0x2) -+ { -+ class_bus_write(val, dst, 2); -+ dst += 2; -+ } -+ -+ if (len & 0x1) -+ { -+ class_bus_write(val, dst, 1); -+ dst++; -+ } -+} -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+ -+/** Writes UTIL program memory (DDR) from the host. -+ * -+ * @param[in] addr Address to write (virtual, must be aligned on size) -+ * @param[in] val Value to write (in PE endianess, i.e BE) -+ * @param[in] size Number of bytes to write (2 or 4) -+ */ -+static void util_pmem_write(u32 val, void *addr, u8 size) -+{ -+ void *addr64 = (void *)((unsigned long)addr & ~0x7); -+ unsigned long off = 8 - ((unsigned long)addr & 0x7) - size; -+ -+ //IMEM should be loaded as a 64bit swapped value in a 64bit aligned location -+ if (size == 4) -+ writel(be32_to_cpu(val), addr64 + off); -+ else -+ writew(be16_to_cpu((u16)val), addr64 + off); -+} -+ -+ -+/** Writes a buffer to UTIL program memory (DDR) from the host. -+ * -+ * @param[in] dst Address to write (virtual, must be at least 16bit aligned) -+ * @param[in] src Buffer to write (in PE endianess, i.e BE, must have same alignment as dst) -+ * @param[in] len Number of bytes to write (must be at least 16bit aligned) -+ */ -+static void util_pmem_memcpy(void *dst, const void *src, unsigned int len) -+{ -+ unsigned int len32; -+ int i; -+ -+ if ((unsigned long)src & 0x2) { -+ util_pmem_write(*(u16 *)src, dst, 2); -+ src += 2; -+ dst += 2; -+ len -= 2; -+ } -+ -+ len32 = len >> 2; -+ -+ for (i = 0; i < len32; i++, dst += 4, src += 4) -+ util_pmem_write(*(u32 *)src, dst, 4); -+ -+ if (len & 0x2) -+ util_pmem_write(*(u16 *)src, dst, len & 0x2); -+} -+#endif -+ -+/** Loads an elf section into pmem -+ * Code needs to be at least 16bit aligned and only PROGBITS sections are supported -+ * -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID) -+ * @param[in] data pointer to the elf firmware -+ * @param[in] shdr pointer to the elf section header -+ * -+ */ -+static int pe_load_pmem_section(int id, const void *data, Elf32_Shdr *shdr) -+{ -+ u32 offset = be32_to_cpu(shdr->sh_offset); -+ u32 addr = be32_to_cpu(shdr->sh_addr); -+ u32 size = be32_to_cpu(shdr->sh_size); -+ u32 type = be32_to_cpu(shdr->sh_type); -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+ if (id == UTIL_ID) -+ { -+ printk(KERN_ERR "%s: unsuported pmem section for UTIL\n", __func__); -+ return -EINVAL; -+ } -+#endif -+ -+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) -+ { -+ printk(KERN_ERR "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n", -+ __func__, addr, (unsigned long) data + offset); -+ -+ return -EINVAL; -+ } -+ -+ if (addr & 0x1) -+ { -+ printk(KERN_ERR "%s: load address(%x) is not 16bit aligned\n", __func__, addr); -+ return -EINVAL; -+ } -+ -+ if (size & 0x1) -+ { -+ printk(KERN_ERR "%s: load size(%x) is not 16bit aligned\n", __func__, size); -+ return -EINVAL; -+ } -+ -+ switch (type) -+ { -+ case SHT_PROGBITS: -+ pe_pmem_memcpy_to32(id, addr, data + offset, size); -+ -+ break; -+ -+ default: -+ printk(KERN_ERR "%s: unsuported section type(%x)\n", __func__, type); -+ return -EINVAL; -+ break; -+ } -+ -+ return 0; -+} -+ -+ -+/** Loads an elf section into dmem -+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0 -+ * -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID) -+ * @param[in] data pointer to the elf firmware -+ * @param[in] shdr pointer to the elf section header -+ * -+ */ -+static int pe_load_dmem_section(int id, const void *data, Elf32_Shdr *shdr) -+{ -+ u32 offset = be32_to_cpu(shdr->sh_offset); -+ u32 addr = be32_to_cpu(shdr->sh_addr); -+ u32 size = be32_to_cpu(shdr->sh_size); -+ u32 type = be32_to_cpu(shdr->sh_type); -+ u32 size32 = size >> 2; -+ int i; -+ -+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) -+ { -+ printk(KERN_ERR "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n", -+ __func__, addr, (unsigned long)data + offset); -+ -+ return -EINVAL; -+ } -+ -+ if (addr & 0x3) -+ { -+ printk(KERN_ERR "%s: load address(%x) is not 32bit aligned\n", __func__, addr); -+ return -EINVAL; -+ } -+ -+ switch (type) -+ { -+ case SHT_PROGBITS: -+ pe_dmem_memcpy_to32(id, addr, data + offset, size); -+ break; -+ -+ case SHT_NOBITS: -+ for (i = 0; i < size32; i++, addr += 4) -+ pe_dmem_write(id, 0, addr, 4); -+ -+ if (size & 0x3) -+ pe_dmem_write(id, 0, addr, size & 0x3); -+ -+ break; -+ -+ default: -+ printk(KERN_ERR "%s: unsuported section type(%x)\n", __func__, type); -+ return -EINVAL; -+ break; -+ } -+ -+ return 0; -+} -+ -+ -+/** Loads an elf section into DDR -+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0 -+ * -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID) -+ * @param[in] data pointer to the elf firmware -+ * @param[in] shdr pointer to the elf section header -+ * -+ */ -+static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr, struct device *dev) -+{ -+ u32 offset = be32_to_cpu(shdr->sh_offset); -+ u32 addr = be32_to_cpu(shdr->sh_addr); -+ u32 size = be32_to_cpu(shdr->sh_size); -+ u32 type = be32_to_cpu(shdr->sh_type); -+ u32 flags = be32_to_cpu(shdr->sh_flags); -+ -+ switch (type) -+ { -+ case SHT_PROGBITS: -+ if (flags & SHF_EXECINSTR) -+ { -+ if (id <= CLASS_MAX_ID) -+ { -+ /* DO the loading only once in DDR */ -+ if (id == CLASS0_ID) -+ { -+ printk(KERN_ERR "%s: load address(%x) and elf file address(%lx) rcvd\n", __func__, addr, (unsigned long)data + offset); -+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) -+ { -+ printk(KERN_ERR "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n", -+ __func__, addr, (unsigned long)data + offset); -+ -+ return -EINVAL; -+ } -+ -+ if (addr & 0x1) -+ { -+ printk(KERN_ERR "%s: load address(%x) is not 16bit aligned\n", __func__, addr); -+ return -EINVAL; -+ } -+ -+ if (size & 0x1) -+ { -+ printk(KERN_ERR "%s: load length(%x) is not 16bit aligned\n", __func__, size); -+ return -EINVAL; -+ } -+ memcpy(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), data + offset, size); -+ } -+ } -+#if !defined(CONFIG_UTIL_DISABLED) -+ else if (id == UTIL_ID) -+ { -+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) -+ { -+ printk(KERN_ERR "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n", -+ __func__, addr, (unsigned long)data + offset); -+ -+ return -EINVAL; -+ } -+ -+ if (addr & 0x1) -+ { -+ printk(KERN_ERR "%s: load address(%x) is not 16bit aligned\n", __func__, addr); -+ return -EINVAL; -+ } -+ -+ if (size & 0x1) -+ { -+ printk(KERN_ERR "%s: load length(%x) is not 16bit aligned\n", __func__, size); -+ return -EINVAL; -+ } -+ -+ util_pmem_memcpy(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), data + offset, size); -+ } -+#endif -+ else -+ { -+ printk(KERN_ERR "%s: unsuported ddr section type(%x) for PE(%d)\n", __func__, type, id); -+ return -EINVAL; -+ } -+ -+ } -+ else -+ { -+ memcpy(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), data + offset, size); -+ } -+ -+ break; -+ -+ case SHT_NOBITS: -+ memset(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), 0, size); -+ -+ break; -+ -+ default: -+ printk(KERN_ERR "%s: unsuported section type(%x)\n", __func__, type); -+ return -EINVAL; -+ break; -+ } -+ -+ return 0; -+} -+ -+ -+/** Loads an elf section into pe lmem -+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0 -+ * -+ * @param[in] id PE identification (CLASS0_ID,..., CLASS5_ID) -+ * @param[in] data pointer to the elf firmware -+ * @param[in] shdr pointer to the elf section header -+ * -+ */ -+static int pe_load_pe_lmem_section(int id, const void *data, Elf32_Shdr *shdr) -+{ -+ u32 offset = be32_to_cpu(shdr->sh_offset); -+ u32 addr = be32_to_cpu(shdr->sh_addr); -+ u32 size = be32_to_cpu(shdr->sh_size); -+ u32 type = be32_to_cpu(shdr->sh_type); -+ -+ if (id > CLASS_MAX_ID) -+ { -+ printk(KERN_ERR "%s: unsuported pe-lmem section type(%x) for PE(%d)\n", __func__, type, id); -+ return -EINVAL; -+ } -+ -+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) -+ { -+ printk(KERN_ERR "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n", -+ __func__, addr, (unsigned long)data + offset); -+ -+ return -EINVAL; -+ } -+ -+ if (addr & 0x3) -+ { -+ printk(KERN_ERR "%s: load address(%x) is not 32bit aligned\n", __func__, addr); -+ return -EINVAL; -+ } -+ -+ switch (type) -+ { -+ case SHT_PROGBITS: -+ class_pe_lmem_memcpy_to32(addr, data + offset, size); -+ break; -+ -+ case SHT_NOBITS: -+ class_pe_lmem_memset(addr, 0, size); -+ break; -+ -+ default: -+ printk(KERN_ERR "%s: unsuported section type(%x)\n", __func__, type); -+ return -EINVAL; -+ break; -+ } -+ -+ return 0; -+} -+ -+ -+/** Loads an elf section into a PE -+ * For now only supports loading a section to dmem (all PE's), pmem (class and tmu PE's), -+ * DDDR (util PE code) -+ * -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID) -+ * @param[in] data pointer to the elf firmware -+ * @param[in] shdr pointer to the elf section header -+ * -+ */ -+int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr, struct device *dev) -+{ -+ u32 addr = be32_to_cpu(shdr->sh_addr); -+ u32 size = be32_to_cpu(shdr->sh_size); -+ -+ if (IS_DMEM(addr, size)) -+ return pe_load_dmem_section(id, data, shdr); -+ else if (IS_PMEM(addr, size)) -+ return pe_load_pmem_section(id, data, shdr); -+ else if (IS_PFE_LMEM(addr, size)) -+ return 0; /* FIXME */ -+ else if (IS_PHYS_DDR(addr, size)) -+ return pe_load_ddr_section(id, data, shdr, dev); -+ else if (IS_PE_LMEM(addr, size)) -+ return pe_load_pe_lmem_section(id, data, shdr); -+ else { -+ printk(KERN_ERR "%s: unsuported memory range(%x)\n", __func__, addr); -+// return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+ -+/**************************** BMU ***************************/ -+ -+/** Initializes a BMU block. -+* @param[in] base BMU block base address -+* @param[in] cfg BMU configuration -+*/ -+void bmu_init(void *base, BMU_CFG *cfg) -+{ -+ bmu_disable(base); -+ -+ bmu_set_config(base, cfg); -+ -+ bmu_reset(base); -+} -+ -+/** Resets a BMU block. -+* @param[in] base BMU block base address -+*/ -+void bmu_reset(void *base) -+{ -+ writel(CORE_SW_RESET, base + BMU_CTRL); -+ -+ /* Wait for self clear */ -+ while (readl(base + BMU_CTRL) & CORE_SW_RESET) ; -+} -+ -+/** Enabled a BMU block. -+* @param[in] base BMU block base address -+*/ -+void bmu_enable(void *base) -+{ -+ writel (CORE_ENABLE, base + BMU_CTRL); -+} -+ -+/** Disables a BMU block. -+* @param[in] base BMU block base address -+*/ -+void bmu_disable(void *base) -+{ -+ writel (CORE_DISABLE, base + BMU_CTRL); -+} -+ -+/** Sets the configuration of a BMU block. -+* @param[in] base BMU block base address -+* @param[in] cfg BMU configuration -+*/ -+void bmu_set_config(void *base, BMU_CFG *cfg) -+{ -+ writel (cfg->baseaddr, base + BMU_UCAST_BASE_ADDR); -+ writel (cfg->count & 0xffff, base + BMU_UCAST_CONFIG); -+ writel (cfg->size & 0xffff, base + BMU_BUF_SIZE); -+// writel (BMU1_THRES_CNT, base + BMU_THRES); -+ -+ /* Interrupts are never used */ -+// writel (0x0, base + BMU_INT_SRC); -+ writel (0x0, base + BMU_INT_ENABLE); -+} -+#if defined(CONFIG_PLATFORM_C2000) -+/**************************** GEMAC ***************************/ -+ -+/** Enable Rx Checksum Engine. With this enabled, Frame with bad IP, -+ * TCP or UDP checksums are discarded -+ * -+ * @param[in] base GEMAC base address. -+ */ -+void gemac_enable_rx_checksum_offload(void *base) -+{ -+ writel(readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_CHKSUM_RX, base + EMAC_NETWORK_CONFIG); -+ writel(readl(CLASS_L4_CHKSUM_ADDR) | IPV4_CHKSUM_DROP, CLASS_L4_CHKSUM_ADDR); -+} -+ -+/** Disable Rx Checksum Engine. -+ * -+ * @param[in] base GEMAC base address. -+ */ -+void gemac_disable_rx_checksum_offload(void *base) -+{ -+ writel(readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_CHKSUM_RX, base + EMAC_NETWORK_CONFIG); -+ writel(readl(CLASS_L4_CHKSUM_ADDR) & ~IPV4_CHKSUM_DROP, CLASS_L4_CHKSUM_ADDR); -+} -+ -+/** Setup the MII Mgmt clock speed. -+ * @param[in] base GEMAC base address (GEMAC0, GEMAC1, GEMAC2) -+ * @param[in] mdc_div MII clock dividor -+ */ -+void gemac_set_mdc_div(void *base, int mdc_div) -+{ -+ u32 val = readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_MDC_DIV_MASK; -+ u32 div; -+ -+ switch (mdc_div) { -+ case 8: -+ div = 0; -+ break; -+ -+ case 16: -+ div = 1; -+ break; -+ -+ case 32: -+ div = 2; -+ break; -+ -+ case 48: -+ div = 3; -+ break; -+ -+ default: -+ case 64: -+ div = 4; -+ break; -+ -+ case 96: -+ div = 5; -+ break; -+ -+ case 128: -+ div = 6; -+ break; -+ -+ case 224: -+ div = 7; -+ break; -+ } -+ -+ val |= div << 18; -+ -+ writel(val, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC set speed. -+* @param[in] base GEMAC base address -+* @param[in] speed GEMAC speed (10, 100 or 1000 Mbps) -+*/ -+void gemac_set_speed(void *base, MAC_SPEED gem_speed) -+{ -+ u32 val = readl(base + EMAC_NETWORK_CONFIG); -+ -+ val = val & ~EMAC_SPEED_MASK; -+ -+ switch (gem_speed) -+ { -+ case SPEED_10M: -+ val &= (~EMAC_PCS_ENABLE); -+ break; -+ -+ case SPEED_100M: -+ val = val | EMAC_SPEED_100; -+ val &= (~EMAC_PCS_ENABLE); -+ break; -+ -+ case SPEED_1000M: -+ val = val | EMAC_SPEED_1000; -+ val &= (~EMAC_PCS_ENABLE); -+ break; -+ -+ case SPEED_1000M_PCS: -+ val = val | EMAC_SPEED_1000; -+ val |= EMAC_PCS_ENABLE; -+ break; -+ -+ default: -+ val = val | EMAC_SPEED_100; -+ val &= (~EMAC_PCS_ENABLE); -+ break; -+ } -+ -+ writel (val, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC set duplex. -+* @param[in] base GEMAC base address -+* @param[in] duplex GEMAC duplex mode (Full, Half) -+*/ -+void gemac_set_duplex(void *base, int duplex) -+{ -+ u32 val = readl(base + EMAC_NETWORK_CONFIG); -+ -+ if (duplex == DUPLEX_HALF) -+ val = (val & ~EMAC_DUPLEX_MASK) | EMAC_HALF_DUP; -+ else -+ val = (val & ~EMAC_DUPLEX_MASK) | EMAC_FULL_DUP; -+ -+ writel (val, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC set mode. -+* @param[in] base GEMAC base address -+* @param[in] mode GEMAC operation mode (MII, RMII, RGMII, SGMII) -+*/ -+ -+#if defined(CONFIG_IP_ALIGNED) -+#define IP_ALIGNED_BITVAL EMAC_TWO_BYTES_IP_ALIGN -+#else -+#define IP_ALIGNED_BITVAL 0 -+#endif -+ -+void gemac_set_mode(void *base, int mode) -+{ -+ switch (mode) -+ { -+ case GMII: -+ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_GMII_MODE_ENABLE | IP_ALIGNED_BITVAL, base + EMAC_CONTROL); -+ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG); -+ break; -+ -+ case RGMII: -+ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_RGMII_MODE_ENABLE | IP_ALIGNED_BITVAL, base + EMAC_CONTROL); -+ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG); -+ break; -+ -+ case RMII: -+ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_RMII_MODE_ENABLE | IP_ALIGNED_BITVAL, base + EMAC_CONTROL); -+ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG); -+ break; -+ -+ case MII: -+ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_MII_MODE_ENABLE | IP_ALIGNED_BITVAL, base + EMAC_CONTROL); -+ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG); -+ break; -+ -+ case SGMII: -+ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | (EMAC_RMII_MODE_DISABLE | EMAC_RGMII_MODE_DISABLE) | IP_ALIGNED_BITVAL, base + EMAC_CONTROL); -+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_SGMII_MODE_ENABLE, base + EMAC_NETWORK_CONFIG); -+ break; -+ -+ default: -+ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_MII_MODE_ENABLE | IP_ALIGNED_BITVAL, base + EMAC_CONTROL); -+ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG); -+ break; -+ } -+} -+/** GEMAC Enable MDIO: Activate the Management interface. This is required to program the PHY -+ * @param[in] base GEMAC base address -+ */ -+void gemac_enable_mdio(void *base) -+{ -+ u32 data; -+ -+ data = readl(base + EMAC_NETWORK_CONTROL); -+ data |= EMAC_MDIO_EN; -+ writel(data, base + EMAC_NETWORK_CONTROL); -+} -+ -+/** GEMAC Disable MDIO: Disable the Management interface. -+ * @param[in] base GEMAC base address -+ */ -+void gemac_disable_mdio(void *base) -+{ -+ u32 data; -+ -+ data = readl(base + EMAC_NETWORK_CONTROL); -+ data &= ~EMAC_MDIO_EN; -+ writel(data, base + EMAC_NETWORK_CONTROL); -+} -+ -+ -+/** GEMAC reset function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_reset(void *base) -+{ -+} -+ -+/** GEMAC enable function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONTROL) | EMAC_TX_ENABLE | EMAC_RX_ENABLE, base + EMAC_NETWORK_CONTROL); -+} -+ -+/** GEMAC disable function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_disable(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONTROL) & ~(EMAC_TX_ENABLE | EMAC_RX_ENABLE), base + EMAC_NETWORK_CONTROL); -+} -+ -+/** GEMAC TX disable function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_tx_disable(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONTROL) & ~(EMAC_TX_ENABLE), base + EMAC_NETWORK_CONTROL); -+} -+ -+/** GEMAC set mac address configuration. -+* @param[in] base GEMAC base address -+* @param[in] addr MAC address to be configured -+*/ -+void gemac_set_address(void *base, SPEC_ADDR *addr) -+{ -+ writel(addr->one.bottom, base + EMAC_SPEC1_ADD_BOT); -+ writel(addr->one.top, base + EMAC_SPEC1_ADD_TOP); -+ writel(addr->two.bottom, base + EMAC_SPEC2_ADD_BOT); -+ writel(addr->two.top, base + EMAC_SPEC2_ADD_TOP); -+ writel(addr->three.bottom, base + EMAC_SPEC3_ADD_BOT); -+ writel(addr->three.top, base + EMAC_SPEC3_ADD_TOP); -+ writel(addr->four.bottom, base + EMAC_SPEC4_ADD_BOT); -+ writel(addr->four.top, base + EMAC_SPEC4_ADD_TOP); -+} -+ -+/** GEMAC get mac address configuration. -+* @param[in] base GEMAC base address -+* -+* @return MAC addresses configured -+*/ -+SPEC_ADDR gemac_get_address(void *base) -+{ -+ SPEC_ADDR addr; -+ -+ addr.one.bottom = readl(base + EMAC_SPEC1_ADD_BOT); -+ addr.one.top = readl(base + EMAC_SPEC1_ADD_TOP); -+ addr.two.bottom = readl(base + EMAC_SPEC2_ADD_BOT); -+ addr.two.top = readl(base + EMAC_SPEC2_ADD_TOP); -+ addr.three.bottom = readl(base + EMAC_SPEC3_ADD_BOT); -+ addr.three.top = readl(base + EMAC_SPEC3_ADD_TOP); -+ addr.four.bottom = readl(base + EMAC_SPEC4_ADD_BOT); -+ addr.four.top = readl(base + EMAC_SPEC4_ADD_TOP); -+ -+ return addr; -+} -+ -+/** Sets the hash register of the MAC. -+ * This register is used for matching unicast and multicast frames. -+ * -+ * @param[in] base GEMAC base address. -+ * @param[in] hash 64-bit hash to be configured. -+ */ -+void gemac_set_hash( void *base, MAC_ADDR *hash ) -+{ -+ writel(hash->bottom, base + EMAC_HASH_BOT); -+ writel(hash->top, base + EMAC_HASH_TOP); -+} -+ -+/** Get the current value hash register of the MAC. -+ * This register is used for matching unicast and multicast frames. -+ * -+ * @param[in] base GEMAC base address -+ -+ * @returns 64-bit hash. -+ */ -+MAC_ADDR gemac_get_hash( void *base ) -+{ -+ MAC_ADDR hash; -+ -+ hash.bottom = readl(base + EMAC_HASH_BOT); -+ hash.top = readl(base + EMAC_HASH_TOP); -+ -+ return hash; -+} -+ -+/** GEMAC set specific local addresses of the MAC. -+* Rather than setting up all four specific addresses, this function sets them up individually. -+* -+* @param[in] base GEMAC base address -+* @param[in] addr MAC address to be configured -+*/ -+void gemac_set_laddr1(void *base, MAC_ADDR *address) -+{ -+ writel(address->bottom, base + EMAC_SPEC1_ADD_BOT); -+ writel(address->top, base + EMAC_SPEC1_ADD_TOP); -+} -+ -+ -+void gemac_set_laddr2(void *base, MAC_ADDR *address) -+{ -+ writel(address->bottom, base + EMAC_SPEC2_ADD_BOT); -+ writel(address->top, base + EMAC_SPEC2_ADD_TOP); -+} -+ -+ -+void gemac_set_laddr3(void *base, MAC_ADDR *address) -+{ -+ writel(address->bottom, base + EMAC_SPEC3_ADD_BOT); -+ writel(address->top, base + EMAC_SPEC3_ADD_TOP); -+} -+ -+ -+void gemac_set_laddr4(void *base, MAC_ADDR *address) -+{ -+ writel(address->bottom, base + EMAC_SPEC4_ADD_BOT); -+ writel(address->top, base + EMAC_SPEC4_ADD_TOP); -+} -+ -+void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index) -+{ -+ if( (entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX) ) -+ return; -+ -+ entry_index = entry_index - 1; -+ -+ if (entry_index < 4) -+ { -+ writel(address->bottom, base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT); -+ writel(address->top, base + (entry_index * 8) + EMAC_SPEC1_ADD_TOP); -+ } -+ else -+ { -+ writel(address->bottom, base + ((entry_index - 4) * 8) + EMAC_SPEC5_ADD_BOT); -+ writel(address->top, base + ((entry_index - 4) * 8) + EMAC_SPEC5_ADD_TOP); -+ } -+} -+ -+/** Get specific local addresses of the MAC. -+* This allows returning of a single specific address stored in the MAC. -+* @param[in] base GEMAC base address -+* -+* @return Specific MAC address 1 -+* -+*/ -+MAC_ADDR gem_get_laddr1(void *base) -+{ -+ MAC_ADDR addr; -+ addr.bottom = readl(base + EMAC_SPEC1_ADD_BOT); -+ addr.top = readl(base + EMAC_SPEC1_ADD_TOP); -+ return addr; -+} -+ -+ -+MAC_ADDR gem_get_laddr2(void *base) -+{ -+ MAC_ADDR addr; -+ addr.bottom = readl(base + EMAC_SPEC2_ADD_BOT); -+ addr.top = readl(base + EMAC_SPEC2_ADD_TOP); -+ return addr; -+} -+ -+ -+MAC_ADDR gem_get_laddr3(void *base) -+{ -+ MAC_ADDR addr; -+ addr.bottom = readl(base + EMAC_SPEC3_ADD_BOT); -+ addr.top = readl(base + EMAC_SPEC3_ADD_TOP); -+ return addr; -+} -+ -+ -+MAC_ADDR gem_get_laddr4(void *base) -+{ -+ MAC_ADDR addr; -+ addr.bottom = readl(base + EMAC_SPEC4_ADD_BOT); -+ addr.top = readl(base + EMAC_SPEC4_ADD_TOP); -+ return addr; -+} -+ -+MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index) -+{ -+ MAC_ADDR addr = {0xffffffff, 0xffffffff}; -+ -+ if( (entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX) ) -+ return addr; -+ -+ entry_index = entry_index - 1; -+ -+ if (entry_index < 4) -+ { -+ addr.bottom = readl(base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT); -+ addr.top = readl(base + (entry_index * 8) + EMAC_SPEC1_ADD_TOP); -+ } -+ else -+ { -+ addr.bottom = readl(base + ((entry_index - 4) * 8) + EMAC_SPEC5_ADD_BOT); -+ addr.top = readl(base + ((entry_index - 4) * 8) + EMAC_SPEC5_ADD_TOP); -+ } -+ -+ return addr; -+} -+ -+/** Clear specific local addresses of the MAC. -+ * @param[in] base GEMAC base address -+ */ -+ -+void gemac_clear_laddr1(void *base) -+{ -+ writel(0, base + EMAC_SPEC1_ADD_BOT); -+} -+ -+void gemac_clear_laddr2(void *base) -+{ -+ writel(0, base + EMAC_SPEC2_ADD_BOT); -+} -+ -+void gemac_clear_laddr3(void *base) -+{ -+ writel(0, base + EMAC_SPEC3_ADD_BOT); -+} -+ -+void gemac_clear_laddr4(void *base) -+{ -+ writel(0, base + EMAC_SPEC4_ADD_BOT); -+} -+ -+void gemac_clear_laddrN(void *base, unsigned int entry_index) -+{ -+ if( (entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX) ) -+ return; -+ -+ entry_index = entry_index - 1; -+ -+ if ( entry_index < 4 ) -+ writel(0, base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT); -+ else -+ writel(0, base + ((entry_index - 4) * 8) + EMAC_SPEC5_ADD_BOT); -+} -+ -+/** Set the loopback mode of the MAC. This can be either no loopback for normal -+ * operation, local loopback through MAC internal loopback module or PHY -+ * loopback for external loopback through a PHY. This asserts the external loop -+ * pin. -+ * -+ * @param[in] base GEMAC base address. -+ * @param[in] gem_loop Loopback mode to be enabled. LB_LOCAL - MAC Loopback, -+ * LB_EXT - PHY Loopback. -+ */ -+void gemac_set_loop( void *base, MAC_LOOP gem_loop ) -+{ -+ switch (gem_loop) { -+ case LB_LOCAL: -+ writel(readl(base + EMAC_NETWORK_CONTROL) & (~EMAC_LB_PHY), -+ base + EMAC_NETWORK_CONTROL); -+ writel(readl(base + EMAC_NETWORK_CONTROL) | (EMAC_LB_MAC), -+ base + EMAC_NETWORK_CONTROL); -+ break; -+ case LB_EXT: -+ writel(readl(base + EMAC_NETWORK_CONTROL) & (~EMAC_LB_MAC), -+ base + EMAC_NETWORK_CONTROL); -+ writel(readl(base + EMAC_NETWORK_CONTROL) | (EMAC_LB_PHY), -+ base + EMAC_NETWORK_CONTROL); -+ break; -+ default: -+ writel(readl(base + EMAC_NETWORK_CONTROL) & (~(EMAC_LB_MAC | EMAC_LB_PHY)), -+ base + EMAC_NETWORK_CONTROL); -+ } -+} -+ -+/** GEMAC allow frames -+ * @param[in] base GEMAC base address -+ */ -+void gemac_enable_copy_all(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_COPY_ALL, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC do not allow frames -+ * @param[in] base GEMAC base address -+*/ -+void gemac_disable_copy_all(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_COPY_ALL, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC allow broadcast function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_allow_broadcast(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_NO_BROADCAST, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC no broadcast function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_no_broadcast(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_NO_BROADCAST, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC enable unicast function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_unicast(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_UNICAST, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC disable unicast function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_disable_unicast(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_UNICAST, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC enable multicast function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_multicast(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_MULTICAST, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC disable multicast function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_disable_multicast(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_MULTICAST, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC enable fcs rx function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_fcs_rx(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_FCS_RX, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC disable fcs rx function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_disable_fcs_rx(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_FCS_RX, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC enable 1536 rx function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_1536_rx(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_1536_RX, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC disable 1536 rx function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_disable_1536_rx(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_1536_RX, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC enable jumbo function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_rx_jmb(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_JUMBO_FRAME, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC disable jumbo function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_disable_rx_jmb(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_JUMBO_FRAME, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC enable stacked vlan function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_stacked_vlan(void *base) -+{ -+ writel (readl(base + EMAC_STACKED_VLAN_REG) | EMAC_ENABLE_STACKED_VLAN, base + EMAC_STACKED_VLAN_REG); -+} -+ -+/** GEMAC enable stacked vlan function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_disable_stacked_vlan(void *base) -+{ -+ writel (readl(base + EMAC_STACKED_VLAN_REG) & ~EMAC_ENABLE_STACKED_VLAN, base + EMAC_STACKED_VLAN_REG); -+} -+ -+/** GEMAC enable pause rx function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_pause_rx(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_PAUSE_RX, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC disable pause rx function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_disable_pause_rx(void *base) -+{ -+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_PAUSE_RX, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** GEMAC wol configuration -+* @param[in] base GEMAC base address -+* @param[in] wol_conf WoL register configuration -+*/ -+void gemac_set_wol(void *base, u32 wol_conf) -+{ -+ writel(wol_conf, base + EMAC_WOL); -+} -+ -+/** Sets Gemac bus width to 64bit -+ * @param[in] base GEMAC base address -+ * @param[in] width gemac bus width to be set possible values are 32/64/128 -+ * */ -+void gemac_set_bus_width(void *base, int width) -+{ -+ u32 val = readl(base + EMAC_NETWORK_CONFIG); -+ switch(width) -+ { -+ case 32: -+ val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_32; -+ case 128: -+ val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_128; -+ case 64: -+ default: -+ val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_64; -+ -+ } -+ writel (val, base + EMAC_NETWORK_CONFIG); -+} -+ -+/** Sets Gemac configuration. -+* @param[in] base GEMAC base address -+* @param[in] cfg GEMAC configuration -+*/ -+void gemac_set_config(void *base, GEMAC_CFG *cfg) -+{ -+ gemac_set_mode(base, cfg->mode); -+ -+ gemac_set_speed(base, cfg->speed); -+ -+ gemac_set_duplex(base,cfg->duplex); -+} -+#elif defined(CONFIG_PLATFORM_LS1012A) -+/**************************** MTIP GEMAC ***************************/ -+ -+/** Enable Rx Checksum Engine. With this enabled, Frame with bad IP, -+ * TCP or UDP checksums are discarded -+ * -+ * @param[in] base GEMAC base address. -+ */ -+void gemac_enable_rx_checksum_offload(void *base) -+{ -+ /*Do not find configuration to do this */ -+} -+ -+/** Disable Rx Checksum Engine. -+ * -+ * @param[in] base GEMAC base address. -+ */ -+void gemac_disable_rx_checksum_offload(void *base) -+{ -+ /*Do not find configuration to do this */ -+} -+ -+/** GEMAC set speed. -+* @param[in] base GEMAC base address -+* @param[in] speed GEMAC speed (10, 100 or 1000 Mbps) -+*/ -+void gemac_set_speed(void *base, MAC_SPEED gem_speed) -+{ -+ u32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED; -+ u32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T; -+ -+ switch (gem_speed) -+ { -+ case SPEED_10M: -+ rcr |= EMAC_RCNTRL_RMII_10T; -+ break; -+ -+ -+ case SPEED_1000M: -+ ecr |= EMAC_ECNTRL_SPEED; -+ break; -+ -+ case SPEED_100M: -+ default: -+ /*It is in 100M mode */ -+ break; -+ } -+ writel(ecr, (base + EMAC_ECNTRL_REG)); -+ writel(rcr, (base + EMAC_RCNTRL_REG)); -+} -+ -+/** GEMAC set duplex. -+* @param[in] base GEMAC base address -+* @param[in] duplex GEMAC duplex mode (Full, Half) -+*/ -+void gemac_set_duplex(void *base, int duplex) -+{ -+ -+ if (duplex == DUPLEX_HALF) { -+ printk("%s() TODO\n", __func__); -+ writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base + EMAC_TCNTRL_REG); -+ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base + EMAC_RCNTRL_REG)); -+ }else{ -+ writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base + EMAC_TCNTRL_REG); -+ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base + EMAC_RCNTRL_REG)); -+ } -+} -+ -+/** GEMAC set mode. -+* @param[in] base GEMAC base address -+* @param[in] mode GEMAC operation mode (MII, RMII, RGMII, SGMII) -+*/ -+void gemac_set_mode(void *base, int mode) -+{ -+ u32 val = readl(base + EMAC_RCNTRL_REG); -+ -+ /*Remove loopbank*/ -+ val &= ~EMAC_RCNTRL_LOOP; -+ -+ /*Enable flow control and MII mode*/ -+ val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE); -+ -+ writel(val, base + EMAC_RCNTRL_REG); -+} -+ -+/** GEMAC enable function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable(void *base) -+{ -+ writel(readl(base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, base + EMAC_ECNTRL_REG); -+} -+ -+/** GEMAC disable function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_disable(void *base) -+{ -+ writel(readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, base + EMAC_ECNTRL_REG); -+} -+ -+/** GEMAC TX disable function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_tx_disable(void *base) -+{ -+ writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base + EMAC_TCNTRL_REG); -+} -+ -+/** Sets the hash register of the MAC. -+ * This register is used for matching unicast and multicast frames. -+ * -+ * @param[in] base GEMAC base address. -+ * @param[in] hash 64-bit hash to be configured. -+ */ -+void gemac_set_hash( void *base, MAC_ADDR *hash ) -+{ -+ writel(hash->bottom, base + EMAC_GALR); -+ writel(hash->top, base + EMAC_GAUR); -+} -+ -+void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index) -+{ -+ if( (entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX) ) -+ return; -+ -+ entry_index = entry_index - 1; -+ if (entry_index < 1) { -+ writel(htonl(address->bottom), base + EMAC_PHY_ADDR_LOW); -+ writel((htonl(address->top) | 0x8808), base + EMAC_PHY_ADDR_HIGH); -+ } -+ else -+ { -+ /* TODO for other entry_index */ -+ /*printk("%s for entry_index %d \n",__func__, entry_index); */ -+ writel(htonl(address->bottom), base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0); -+ writel((htonl(address->top) | 0x8808), base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1); -+ } -+ -+} -+ -+void gemac_clear_laddrN(void *base, unsigned int entry_index) -+{ -+ if( (entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX) ) -+ return; -+ -+ entry_index = entry_index - 1; -+ if (entry_index < 1) { -+ writel(0, base + EMAC_PHY_ADDR_LOW); -+ writel(0, base + EMAC_PHY_ADDR_HIGH); -+ } -+ else -+ { -+ writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0); -+ writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1); -+ } -+ -+ -+} -+ -+/** Set the loopback mode of the MAC. This can be either no loopback for normal -+ * operation, local loopback through MAC internal loopback module or PHY -+ * loopback for external loopback through a PHY. This asserts the external loop -+ * pin. -+ * -+ * @param[in] base GEMAC base address. -+ * @param[in] gem_loop Loopback mode to be enabled. LB_LOCAL - MAC Loopback, -+ * LB_EXT - PHY Loopback. -+ */ -+void gemac_set_loop( void *base, MAC_LOOP gem_loop ) -+{ -+ printk("%s()\n", __func__); -+ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base + EMAC_RCNTRL_REG)); -+} -+ -+ -+/** GEMAC allow frames -+ * @param[in] base GEMAC base address -+ */ -+void gemac_enable_copy_all(void *base) -+{ -+ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base + EMAC_RCNTRL_REG)); -+} -+ -+/** GEMAC do not allow frames -+ * @param[in] base GEMAC base address -+*/ -+void gemac_disable_copy_all(void *base) -+{ -+ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base + EMAC_RCNTRL_REG)); -+} -+ -+/** GEMAC allow broadcast function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_allow_broadcast(void *base) -+{ -+ writel (readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_BC_REJ, base + EMAC_RCNTRL_REG); -+} -+ -+/** GEMAC no broadcast function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_no_broadcast(void *base) -+{ -+ writel (readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base + EMAC_RCNTRL_REG); -+} -+ -+/** GEMAC enable unicast function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_unicast(void *base) -+{ -+ return; -+} -+ -+/** GEMAC disable unicast function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_disable_unicast(void *base) -+{ -+ return; -+} -+ -+/** GEMAC enable multicast function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_multicast(void *base) -+{ -+ return; -+} -+ -+/** GEMAC disable multicast function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_disable_multicast(void *base) -+{ -+ /* TODO how to disable multicast? */ -+ return; -+} -+ -+/** GEMAC enable fcs rx function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_fcs_rx(void *base) -+{ -+ /*Do not find configuration to do this */ -+} -+ -+/** GEMAC disable fcs rx function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_disable_fcs_rx(void *base) -+{ -+ /*Do not find configuration to do this */ -+} -+ -+ -+/** GEMAC enable 1536 rx function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_1536_rx(void *base) -+{ -+ /* Set 1536 as Maximum frame length */ -+ writel (readl(base + EMAC_RCNTRL_REG) | (1536 << 16), base + EMAC_RCNTRL_REG); -+} -+ -+/** GEMAC enable jumbo function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_rx_jmb(void *base) -+{ -+ /*TODO what is the jumbo size supported by MTIP */ -+ writel (readl(base + EMAC_RCNTRL_REG) | (JUMBO_FRAME_SIZE << 16), base + EMAC_RCNTRL_REG); -+} -+ -+/** GEMAC enable stacked vlan function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_stacked_vlan(void *base) -+{ -+ /* MTIP doesn't support stacked vlan */ -+ return; -+} -+ -+/** GEMAC enable pause rx function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_enable_pause_rx(void *base) -+{ -+ writel (readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_FCE, base + EMAC_RCNTRL_REG); -+} -+ -+/** GEMAC disable pause rx function. -+* @param[in] base GEMAC base address -+*/ -+void gemac_disable_pause_rx(void *base) -+{ -+ writel (readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_FCE, base + EMAC_RCNTRL_REG); -+} -+ -+/** GEMAC wol configuration -+* @param[in] base GEMAC base address -+* @param[in] wol_conf WoL register configuration -+*/ -+void gemac_set_wol(void *base, u32 wol_conf) -+{ -+ printk("%s() TODO\n", __func__); -+} -+ -+/** Sets Gemac bus width to 64bit -+ * @param[in] base GEMAC base address -+ * @param[in] width gemac bus width to be set possible values are 32/64/128 -+ * */ -+void gemac_set_bus_width(void *base, int width) -+{ -+} -+ -+/** Sets Gemac configuration. -+* @param[in] base GEMAC base address -+* @param[in] cfg GEMAC configuration -+*/ -+void gemac_set_config(void *base, GEMAC_CFG *cfg) -+{ -+ -+ /*GEMAC config taken from VLSI */ -+ writel(0x00000004, base + EMAC_TFWR_STR_FWD); -+ writel(0x00000005, base + EMAC_RX_SECTIOM_FULL); -+ writel(0x00003fff, base + EMAC_TRUNC_FL); -+ writel(0x00000030, base + EMAC_TX_SECTION_EMPTY); -+ writel(0x00000000, base + EMAC_MIB_CTRL_STS_REG); -+ -+ gemac_set_mode(base, cfg->mode); -+ -+ gemac_set_speed(base, cfg->speed); -+ -+ gemac_set_duplex(base,cfg->duplex); -+} -+ -+ -+#endif //CONFIG_PLATFORM_LS1012A) -+ -+ -+ -+/**************************** GPI ***************************/ -+ -+/** Initializes a GPI block. -+* @param[in] base GPI base address -+* @param[in] cfg GPI configuration -+*/ -+void gpi_init(void *base, GPI_CFG *cfg) -+{ -+ gpi_reset(base); -+ -+ gpi_disable(base); -+ -+ gpi_set_config(base, cfg); -+} -+ -+/** Resets a GPI block. -+* @param[in] base GPI base address -+*/ -+void gpi_reset(void *base) -+{ -+ writel (CORE_SW_RESET, base + GPI_CTRL); -+} -+ -+/** Enables a GPI block. -+* @param[in] base GPI base address -+*/ -+void gpi_enable(void *base) -+{ -+ writel (CORE_ENABLE, base + GPI_CTRL); -+} -+ -+/** Disables a GPI block. -+* @param[in] base GPI base address -+*/ -+void gpi_disable(void *base) -+{ -+ writel (CORE_DISABLE, base + GPI_CTRL); -+} -+ -+ -+/** Sets the configuration of a GPI block. -+* @param[in] base GPI base address -+* @param[in] cfg GPI configuration -+*/ -+void gpi_set_config(void *base, GPI_CFG *cfg) -+{ -+ writel (CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base + GPI_LMEM_ALLOC_ADDR); -+ writel (CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base + GPI_LMEM_FREE_ADDR); -+ writel (CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base + GPI_DDR_ALLOC_ADDR); -+ writel (CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base + GPI_DDR_FREE_ADDR); -+ writel (CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR); -+ writel (DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET); -+ writel (LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET); -+ writel (0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET); -+ writel (0, base + GPI_DDR_SEC_BUF_DATA_OFFSET); -+ writel ((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE); -+ writel ((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE); -+ -+ writel (((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) | GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG); -+ writel (cfg->tmlf_txthres, base + GPI_TMLF_TX); -+ writel (cfg->aseq_len, base + GPI_DTX_ASEQ); -+ writel (1, base + GPI_TOE_CHKSUM_EN); -+} -+ -+/**************************** CLASSIFIER ***************************/ -+ -+/** Initializes CLASSIFIER block. -+* @param[in] cfg CLASSIFIER configuration -+*/ -+void class_init(CLASS_CFG *cfg) -+{ -+ class_reset(); -+ -+ class_disable(); -+ -+ class_set_config(cfg); -+} -+ -+/** Resets CLASSIFIER block. -+* -+*/ -+void class_reset(void) -+{ -+ writel(CORE_SW_RESET, CLASS_TX_CTRL); -+} -+ -+/** Enables all CLASS-PE's cores. -+* -+*/ -+void class_enable(void) -+{ -+ writel(CORE_ENABLE, CLASS_TX_CTRL); -+} -+ -+/** Disables all CLASS-PE's cores. -+* -+*/ -+void class_disable(void) -+{ -+ writel(CORE_DISABLE, CLASS_TX_CTRL); -+} -+ -+/** Sets the configuration of the CLASSIFIER block. -+* @param[in] cfg CLASSIFIER configuration -+*/ -+void class_set_config(CLASS_CFG *cfg) -+{ -+ u32 val; -+ -+ /* Initialize route table */ -+ if (!cfg->resume) -+ memset(DDR_PHYS_TO_VIRT(cfg->route_table_baseaddr), 0, (1 << cfg->route_table_hash_bits) * CLASS_ROUTE_SIZE); -+ -+#if !defined(LS1012A_PFE_RESET_WA) -+ writel(cfg->pe_sys_clk_ratio, CLASS_PE_SYS_CLK_RATIO); -+#endif -+ -+ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, CLASS_HDR_SIZE); -+ writel(LMEM_BUF_SIZE, CLASS_LMEM_BUF_SIZE); -+ writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) | CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits), CLASS_ROUTE_HASH_ENTRY_SIZE); -+ writel(HIF_PKT_CLASS_EN| HIF_PKT_OFFSET(sizeof(struct hif_hdr)), CLASS_HIF_PARSE); -+ -+ val = HASH_CRC_PORT_IP | QB2BUS_LE; -+ -+#if defined(CONFIG_IP_ALIGNED) -+ val |= IP_ALIGNED; -+#endif -+ -+ /* Class PE packet steering will only work if TOE mode, bridge fetch or -+ * route fetch are enabled (see class/qb_fet.v). Route fetch would trigger -+ * additional memory copies (likely from DDR because of hash table size, which -+ * cannot be reduced because PE software still relies on hash value computed -+ * in HW), so when not in TOE mode we simply enable HW bridge fetch even -+ * though we don't use it. -+ */ -+ if (cfg->toe_mode) -+ val |= CLASS_TOE; -+ else -+ val |= HW_BRIDGE_FETCH; -+ -+ writel(val, CLASS_ROUTE_MULTI); -+ -+ writel(DDR_PHYS_TO_PFE(cfg->route_table_baseaddr), CLASS_ROUTE_TABLE_BASE); -+ writel(CLASS_PE0_RO_DM_ADDR0_VAL, CLASS_PE0_RO_DM_ADDR0); -+ writel(CLASS_PE0_RO_DM_ADDR1_VAL, CLASS_PE0_RO_DM_ADDR1); -+ writel(CLASS_PE0_QB_DM_ADDR0_VAL, CLASS_PE0_QB_DM_ADDR0); -+ writel(CLASS_PE0_QB_DM_ADDR1_VAL, CLASS_PE0_QB_DM_ADDR1); -+ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), CLASS_TM_INQ_ADDR); -+ -+ writel(23, CLASS_AFULL_THRES); -+ writel(23, CLASS_TSQ_FIFO_THRES); -+ -+ writel(24, CLASS_MAX_BUF_CNT); -+ writel(24, CLASS_TSQ_MAX_CNT); -+} -+ -+/**************************** TMU ***************************/ -+ -+void tmu_reset(void) -+{ -+ writel(SW_RESET, TMU_CTRL); -+} -+ -+/** Initializes TMU block. -+* @param[in] cfg TMU configuration -+*/ -+void tmu_init(TMU_CFG *cfg) -+{ -+ int q, phyno; -+ -+ tmu_disable(0xF); -+ mdelay(10); -+ -+#if !defined(LS1012A_PFE_RESET_WA) -+ /* keep in soft reset */ -+ writel(SW_RESET, TMU_CTRL); -+#endif -+ writel(0x3, TMU_SYS_GENERIC_CONTROL); -+ writel(750, TMU_INQ_WATERMARK); -+ writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY0_INQ_ADDR); -+ writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY1_INQ_ADDR); -+#if !defined(CONFIG_PLATFORM_LS1012A) -+ writel(CBUS_VIRT_TO_PFE(EGPI3_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY2_INQ_ADDR); -+#endif -+ writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY3_INQ_ADDR); -+ writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR); -+ writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR); -+ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), TMU_BMU_INQ_ADDR); -+ -+ writel(0x3FF, TMU_TDQ0_SCH_CTRL); // enabling all 10 schedulers [9:0] of each TDQ -+ writel(0x3FF, TMU_TDQ1_SCH_CTRL); -+#if !defined(CONFIG_PLATFORM_LS1012A) -+ writel(0x3FF, TMU_TDQ2_SCH_CTRL); -+#endif -+ writel(0x3FF, TMU_TDQ3_SCH_CTRL); -+ -+#if !defined(LS1012A_PFE_RESET_WA) -+ writel(cfg->pe_sys_clk_ratio, TMU_PE_SYS_CLK_RATIO); -+#endif -+ -+#if !defined(LS1012A_PFE_RESET_WA) -+ writel(DDR_PHYS_TO_PFE(cfg->llm_base_addr), TMU_LLM_BASE_ADDR); // Extra packet pointers will be stored from this address onwards -+ -+ writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN); -+ writel(5, TMU_TDQ_IIFG_CFG); -+ writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE); -+ -+ writel(0x0, TMU_CTRL); -+ -+ /* MEM init */ -+ printk(KERN_INFO "%s: mem init\n", __func__); -+ writel(MEM_INIT, TMU_CTRL); -+ -+ while(!(readl(TMU_CTRL) & MEM_INIT_DONE)) ; -+ -+ /* LLM init */ -+ printk(KERN_INFO "%s: lmem init\n", __func__); -+ writel(LLM_INIT, TMU_CTRL); -+ -+ while(!(readl(TMU_CTRL) & LLM_INIT_DONE)) ; -+#endif -+ // set up each queue for tail drop -+ for (phyno = 0; phyno < 4; phyno++) -+ { -+#if defined(CONFIG_PLATFORM_LS1012A) -+ if(phyno == 2) continue; -+#endif -+ for (q = 0; q < 16; q++) -+ { -+ u32 qdepth; -+ writel((phyno << 8) | q, TMU_TEQ_CTRL); -+ writel(1 << 22, TMU_TEQ_QCFG); //Enable tail drop -+ -+ if (phyno == 3) -+ qdepth = DEFAULT_TMU3_QDEPTH; -+ else -+ qdepth = (q == 0) ? DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH; -+ -+ // LOG: 68855 -+ // The following is a workaround for the reordered packet and BMU2 buffer leakage issue. -+ if (CHIP_REVISION() == 0) -+ qdepth = 31; -+ -+ writel(qdepth << 18, TMU_TEQ_HW_PROB_CFG2); -+ writel(qdepth >> 14, TMU_TEQ_HW_PROB_CFG3); -+ } -+ } -+ -+#ifdef CFG_LRO -+ /* Set TMU-3 queue 5 (LRO) in no-drop mode */ -+ writel((3 << 8) | TMU_QUEUE_LRO, TMU_TEQ_CTRL); -+ writel(0, TMU_TEQ_QCFG); -+#endif -+ -+ writel(0x05, TMU_TEQ_DISABLE_DROPCHK); -+ -+ writel(0x0, TMU_CTRL); -+} -+ -+/** Enables TMU-PE cores. -+* @param[in] pe_mask TMU PE mask -+*/ -+void tmu_enable(u32 pe_mask) -+{ -+ writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL); -+} -+ -+/** Disables TMU cores. -+* @param[in] pe_mask TMU PE mask -+*/ -+void tmu_disable(u32 pe_mask) -+{ -+ writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL); -+} -+/** This will return the tmu queue status -+ * @param[in] if_id gem interface id or TMU index -+ * @return returns the bit mask of busy queues, zero means all queues are empty -+ */ -+u32 tmu_qstatus(u32 if_id) -+{ -+ return cpu_to_be32(pe_dmem_read(TMU0_ID+if_id, PESTATUS_ADDR_TMU + offsetof(PE_STATUS, tmu_qstatus), 4)); -+} -+ -+u32 tmu_pkts_processed(u32 if_id) -+{ -+ return cpu_to_be32(pe_dmem_read(TMU0_ID+if_id, PESTATUS_ADDR_TMU + offsetof(PE_STATUS, rx), 4)); -+} -+/**************************** UTIL ***************************/ -+ -+/** Resets UTIL block. -+*/ -+void util_reset(void) -+{ -+ writel(CORE_SW_RESET, UTIL_TX_CTRL); -+} -+ -+/** Initializes UTIL block. -+* @param[in] cfg UTIL configuration -+*/ -+void util_init(UTIL_CFG *cfg) -+{ -+ writel(cfg->pe_sys_clk_ratio, UTIL_PE_SYS_CLK_RATIO); -+} -+ -+/** Enables UTIL-PE core. -+* -+*/ -+void util_enable(void) -+{ -+ writel(CORE_ENABLE, UTIL_TX_CTRL); -+} -+ -+/** Disables UTIL-PE core. -+* -+*/ -+void util_disable(void) -+{ -+ writel(CORE_DISABLE, UTIL_TX_CTRL); -+} -+ -+/**************************** HIF ***************************/ -+ -+/** Initializes HIF no copy block. -+* -+*/ -+void hif_nocpy_init(void) -+{ -+ writel(4, HIF_NOCPY_TX_PORT_NO); -+ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), HIF_NOCPY_LMEM_ALLOC_ADDR); -+ writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), HIF_NOCPY_CLASS_ADDR); -+ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), HIF_NOCPY_TMU_PORT0_ADDR); -+ writel(HIF_RX_POLL_CTRL_CYCLE<<16|HIF_TX_POLL_CTRL_CYCLE, HIF_NOCPY_POLL_CTRL); -+} -+ -+/** Enable hif_nocpy tx DMA and interrupt -+* -+*/ -+void hif_nocpy_tx_enable(void) -+{ -+ /*TODO not sure poll_cntrl_en is required or not */ -+ writel( HIF_CTRL_DMA_EN, HIF_NOCPY_TX_CTRL); -+ //writel((readl(HIF_NOCPY_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN), HIF_NOCPY_INT_ENABLE); -+} -+ -+/** Disable hif_nocpy tx DMA and interrupt -+* -+*/ -+void hif_nocpy_tx_disable(void) -+{ -+ u32 hif_int; -+ -+ writel(0, HIF_NOCPY_TX_CTRL); -+ -+ hif_int = readl(HIF_NOCPY_INT_ENABLE); -+ hif_int &= HIF_TXPKT_INT_EN; -+ writel(hif_int, HIF_NOCPY_INT_ENABLE); -+} -+ -+/** Enable hif rx DMA and interrupt -+* -+*/ -+void hif_nocpy_rx_enable(void) -+{ -+ hif_nocpy_rx_dma_start(); -+ writel((readl(HIF_NOCPY_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN), HIF_NOCPY_INT_ENABLE); -+} -+ -+/** Disable hif_nocpy rx DMA and interrupt -+* -+*/ -+void hif_nocpy_rx_disable(void) -+{ -+ u32 hif_int; -+ -+ writel(0, HIF_NOCPY_RX_CTRL); -+ -+ hif_int = readl(HIF_NOCPY_INT_ENABLE); -+ hif_int &= HIF_RXPKT_INT_EN; -+ writel(hif_int, HIF_NOCPY_INT_ENABLE); -+ -+} -+/** Initializes HIF copy block. -+* -+*/ -+void hif_init(void) -+{ -+ /*Initialize HIF registers*/ -+ writel((HIF_RX_POLL_CTRL_CYCLE << 16) | HIF_TX_POLL_CTRL_CYCLE, HIF_POLL_CTRL); -+} -+ -+/** Enable hif tx DMA and interrupt -+* -+*/ -+void hif_tx_enable(void) -+{ -+ /*TODO not sure poll_cntrl_en is required or not */ -+ writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL); -+ writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN), HIF_INT_ENABLE); -+} -+ -+/** Disable hif tx DMA and interrupt -+* -+*/ -+void hif_tx_disable(void) -+{ -+ u32 hif_int; -+ -+ writel(0, HIF_TX_CTRL); -+ -+ hif_int = readl(HIF_INT_ENABLE); -+ hif_int &= HIF_TXPKT_INT_EN; -+ writel(hif_int, HIF_INT_ENABLE); -+} -+ -+/** Enable hif rx DMA and interrupt -+* -+*/ -+void hif_rx_enable(void) -+{ -+ hif_rx_dma_start(); -+ writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN), HIF_INT_ENABLE); -+} -+ -+/** Disable hif rx DMA and interrupt -+* -+*/ -+void hif_rx_disable(void) -+{ -+ u32 hif_int; -+ -+ writel(0, HIF_RX_CTRL); -+ -+ hif_int = readl(HIF_INT_ENABLE); -+ hif_int &= HIF_RXPKT_INT_EN; -+ writel(hif_int, HIF_INT_ENABLE); -+ -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hif.c -@@ -0,0 +1,939 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifdef __KERNEL__ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#else -+#include "platform.h" -+#endif -+ -+ -+#include "pfe_mod.h" -+#if 0 -+#define DMA_MAP_SINGLE(dev, vaddr, size, direction) dma_map_single(dev, vaddr, size, direction) -+#define DMA_UNMAP_SINGLE(dev, vaddr, size, direction) dma_unmap_single(dev, vaddr, size, direction) -+void ct_flush(void *addr, u32 size) -+{ -+ dma_map_single(pfe->dev, addr, size, DMA_TO_DEVICE); -+} -+#else -+#define DMA_UNMAP_SINGLE(dev, vaddr, size, direction) -+#define DMA_MAP_SINGLE(dev, vaddr, size, direction) virt_to_phys(vaddr) -+#define ct_flush(addr, sz) -+#endif -+ -+#define HIF_INT_MASK (HIF_INT | HIF_RXPKT_INT) -+ -+#define inc_cl_idx(idxname) idxname = (idxname+1) & (queue->size-1) -+#define inc_hif_rxidx(idxname) idxname = (idxname+1) & (hif->RxRingSize-1) -+#define inc_hif_txidx(idxname) idxname = (idxname+1) & (hif->TxRingSize-1) -+ -+unsigned char napi_first_batch = 0; -+ -+static int pfe_hif_alloc_descr(struct pfe_hif *hif) -+{ -+#if !defined(CONFIG_PLATFORM_PCI) -+ void *addr; -+ dma_addr_t dma_addr; -+ int err = 0; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ addr = dma_alloc_coherent(pfe->dev, -+ HIF_RX_DESC_NT * sizeof(struct hif_desc) + HIF_TX_DESC_NT * sizeof(struct hif_desc), -+ &dma_addr, GFP_KERNEL); -+ -+ if (!addr) { -+ printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n", __func__); -+ err = -ENOMEM; -+ goto err0; -+ } -+ -+ hif->descr_baseaddr_p = dma_addr; -+ hif->descr_baseaddr_v = addr; -+#else -+ hif->descr_baseaddr_p = pfe->ddr_phys_baseaddr + HIF_DESC_BASEADDR; -+ hif->descr_baseaddr_v = pfe->ddr_baseaddr + HIF_DESC_BASEADDR; -+#endif -+ hif->RxRingSize = HIF_RX_DESC_NT; -+ hif->TxRingSize = HIF_TX_DESC_NT; -+ -+ return 0; -+ -+err0: -+ return err; -+} -+ -+static void pfe_hif_free_descr(struct pfe_hif *hif) -+{ -+ printk(KERN_INFO "%s\n", __func__); -+#if !defined(CONFIG_PLATFORM_PCI) -+ dma_free_coherent(pfe->dev, -+ hif->RxRingSize * sizeof(struct hif_desc) + hif->TxRingSize * sizeof(struct hif_desc), -+ hif->descr_baseaddr_v, hif->descr_baseaddr_p); -+#endif -+} -+void pfe_hif_desc_dump(struct pfe_hif *hif) -+{ -+ struct hif_desc *desc; -+ unsigned long desc_p; -+ int ii=0; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ desc = hif->RxBase; -+ desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v + hif->descr_baseaddr_p); -+ -+ printk("HIF Rx desc base %p physical %x\n", desc, (u32)desc_p); -+ for (ii = 0; ii < hif->RxRingSize; ii++) { -+ printk(KERN_INFO "status: %08x, ctrl: %08x, data: %08x, next: %x\n", -+ desc->status, desc->ctrl, desc->data, desc->next); -+ desc++; -+ } -+ -+ desc = hif->TxBase; -+ desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v + hif->descr_baseaddr_p); -+ -+ printk("HIF Tx desc base %p physical %x\n", desc, (u32)desc_p); -+ for (ii = 0; ii < hif->TxRingSize; ii++) { -+ printk(KERN_INFO "status: %08x, ctrl: %08x, data: %08x, next: %x\n", -+ desc->status, desc->ctrl, desc->data, desc->next); -+ desc++; -+ } -+ -+} -+ -+/* pfe_hif_release_buffers -+ * -+ */ -+static void pfe_hif_release_buffers(struct pfe_hif *hif) -+{ -+ struct hif_desc *desc; -+ int i = 0; -+ -+ hif->RxBase = hif->descr_baseaddr_v; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ /*Free Rx buffers */ -+#if !defined(CONFIG_PLATFORM_PCI) -+ desc = hif->RxBase; -+ for (i = 0; i < hif->RxRingSize; i++) { -+ if (desc->data) { -+ if ((i < hif->shm->rx_buf_pool_cnt) && (hif->shm->rx_buf_pool[i] == NULL)) { -+ //dma_unmap_single(hif->dev, desc->data, hif->rx_buf_len[i], DMA_FROM_DEVICE); -+ DMA_UNMAP_SINGLE(hif->dev, desc->data, hif->rx_buf_len[i], DMA_FROM_DEVICE); -+ hif->shm->rx_buf_pool[i] = hif->rx_buf_addr[i]; -+ } -+ else { -+ /*TODO This should not happen*/ -+ printk(KERN_ERR "%s: buffer pool already full\n", __func__); -+ } -+ } -+ -+ desc->data = 0; -+ desc->status = 0; -+ desc->ctrl = 0; -+ desc++; -+ } -+#endif -+} -+ -+ -+/* -+ * pfe_hif_init_buffers -+ * This function initializes the HIF Rx/Tx ring descriptors and -+ * initialize Rx queue with buffers. -+ */ -+static int pfe_hif_init_buffers(struct pfe_hif *hif) -+{ -+ struct hif_desc *desc, *first_desc_p; -+ u32 data; -+ int i = 0; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ /* Check enough Rx buffers available in the shared memory */ -+ if (hif->shm->rx_buf_pool_cnt < hif->RxRingSize) -+ return -ENOMEM; -+ -+ hif->RxBase = hif->descr_baseaddr_v; -+ memset(hif->RxBase, 0, hif->RxRingSize * sizeof(struct hif_desc)); -+ -+ /*Initialize Rx descriptors */ -+ desc = hif->RxBase; -+ first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p; -+ -+ for (i = 0; i < hif->RxRingSize; i++) { -+ /* Initialize Rx buffers from the shared memory */ -+ -+#if defined(CONFIG_PLATFORM_PCI) -+ data = pfe->ddr_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR + i * DDR_BUF_SIZE; -+#else -+ data = (u32)DMA_MAP_SINGLE(hif->dev, hif->shm->rx_buf_pool[i], pfe_pkt_size, DMA_FROM_DEVICE); -+ hif->rx_buf_addr[i] = hif->shm->rx_buf_pool[i]; -+ hif->rx_buf_len[i] = pfe_pkt_size; -+ // printk("#%d %p %p %d\n", i, data, hif->rx_buf_addr[i], hif->rx_buf_len[i]); -+ hif->shm->rx_buf_pool[i] = NULL; -+#endif -+ if (likely(dma_mapping_error(hif->dev, data) == 0)) { -+ desc->data = DDR_PHYS_TO_PFE(data); -+ } else { -+ printk(KERN_ERR "%s : low on mem\n", __func__); -+ -+ goto err; -+ } -+ -+ desc->status = 0; -+ wmb(); -+ desc->ctrl = BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM | BD_CTRL_DIR | -+ BD_CTRL_DESC_EN | BD_BUF_LEN(pfe_pkt_size); -+ /* Chain descriptors */ -+ desc->next = (u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1); -+ desc++; -+ } -+ -+ /* Overwrite last descriptor to chain it to first one*/ -+ desc--; -+ desc->next = (u32)DDR_PHYS_TO_PFE(first_desc_p); -+ -+ hif->RxtocleanIndex = 0; -+ -+ /*Initialize Rx buffer descriptor ring base address */ -+ writel(DDR_PHYS_TO_PFE(hif->descr_baseaddr_p), HIF_RX_BDP_ADDR); -+ -+ hif->TxBase = hif->RxBase + hif->RxRingSize; -+ first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p + hif->RxRingSize; -+ memset(hif->TxBase, 0, hif->TxRingSize * sizeof(struct hif_desc)); -+ -+ /*Initialize tx descriptors */ -+ desc = hif->TxBase; -+ -+ for (i = 0; i < hif->TxRingSize; i++) { -+ /* Chain descriptors */ -+ desc->next = (u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1); -+#if defined(CONFIG_PLATFORM_PCI) -+ desc->data = pfe->ddr_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR + i * DDR_BUF_SIZE; -+#endif -+ desc->ctrl = 0; -+ desc++; -+ } -+ -+ /* Overwrite last descriptor to chain it to first one */ -+ desc--; -+ desc->next = (u32)DDR_PHYS_TO_PFE(first_desc_p); -+ hif->TxAvail = hif->TxRingSize; -+ hif->Txtosend = 0; -+ hif->Txtoclean = 0; -+ hif->Txtoflush = 0; -+ -+ /*Initialize Tx buffer descriptor ring base address */ -+ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), HIF_TX_BDP_ADDR); -+ -+ return 0; -+ -+err: -+ pfe_hif_release_buffers(hif); -+ return -ENOMEM; -+} -+ -+/* pfe_hif_client_register -+ * -+ * This function used to register a client driver with the HIF driver. -+ * -+ * Return value: -+ * 0 - on Successful registration -+ */ -+static int pfe_hif_client_register(struct pfe_hif *hif, u32 client_id, struct hif_client_shm *client_shm) -+{ -+ struct hif_client *client = &hif->client[client_id]; -+ u32 i, cnt; -+ struct rx_queue_desc *rx_qbase; -+ struct tx_queue_desc *tx_qbase; -+ struct hif_rx_queue *rx_queue; -+ struct hif_tx_queue *tx_queue; -+ int err = 0; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ spin_lock_bh(&hif->tx_lock); -+ -+ if (test_bit(client_id, &hif->shm->gClient_status[0])) { -+ printk(KERN_ERR "%s: client %d already registered\n", __func__, client_id); -+ err = -1; -+ goto unlock; -+ } -+ -+ memset(client, 0, sizeof(struct hif_client)); -+ -+ /*Initialize client Rx queues baseaddr, size */ -+ -+ cnt = CLIENT_CTRL_RX_Q_CNT(client_shm->ctrl); -+ /*Check if client is requesting for more queues than supported */ -+ if (cnt > HIF_CLIENT_QUEUES_MAX) -+ cnt = HIF_CLIENT_QUEUES_MAX; -+ -+ client->rx_qn = cnt; -+ rx_qbase = (struct rx_queue_desc *)client_shm->rx_qbase; -+ for (i = 0; i < cnt; i++) -+ { -+ rx_queue = &client->rx_q[i]; -+ rx_queue->base = rx_qbase + i * client_shm->rx_qsize; -+ rx_queue->size = client_shm->rx_qsize; -+ rx_queue->write_idx = 0; -+ } -+ -+ /*Initialize client Tx queues baseaddr, size */ -+ cnt = CLIENT_CTRL_TX_Q_CNT(client_shm->ctrl); -+ -+ /*Check if client is requesting for more queues than supported */ -+ if (cnt > HIF_CLIENT_QUEUES_MAX) -+ cnt = HIF_CLIENT_QUEUES_MAX; -+ -+ client->tx_qn = cnt; -+ tx_qbase = (struct tx_queue_desc *)client_shm->tx_qbase; -+ for (i = 0; i < cnt; i++) -+ { -+ tx_queue = &client->tx_q[i]; -+ tx_queue->base = tx_qbase + i * client_shm->tx_qsize; -+ tx_queue->size = client_shm->tx_qsize; -+ tx_queue->ack_idx = 0; -+ } -+ -+ set_bit(client_id, &hif->shm->gClient_status[0]); -+ -+unlock: -+ spin_unlock_bh(&hif->tx_lock); -+ -+ return err; -+} -+ -+ -+/* pfe_hif_client_unregister -+ * -+ * This function used to unregister a client from the HIF driver. -+ * -+ */ -+static void pfe_hif_client_unregister(struct pfe_hif *hif, u32 client_id) -+{ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ /* Mark client as no longer available (which prevents further packet receive for this client) */ -+ spin_lock_bh(&hif->tx_lock); -+ -+ if (!test_bit(client_id, &hif->shm->gClient_status[0])) { -+ printk(KERN_ERR "%s: client %d not registered\n", __func__, client_id); -+ -+ spin_unlock_bh(&hif->tx_lock); -+ return; -+ } -+ -+ clear_bit(client_id, &hif->shm->gClient_status[0]); -+ -+ spin_unlock_bh(&hif->tx_lock); -+} -+ -+/* client_put_rxpacket- -+ * This functions puts the Rx pkt in the given client Rx queue. -+ * It actually swap the Rx pkt in the client Rx descriptor buffer -+ * and returns the free buffer from it. -+ * -+ * If the funtion returns NULL means client Rx queue is full and -+ * packet couldn't send to client queue. -+ */ -+static void *client_put_rxpacket(struct hif_rx_queue *queue, void *pkt, u32 len, u32 flags, u32 client_ctrl, u32 *rem_len) -+{ -+ void *free_pkt = NULL; -+ struct rx_queue_desc *desc = queue->base + queue->write_idx; -+ -+ if (desc->ctrl & CL_DESC_OWN) { -+#if defined(CONFIG_PLATFORM_PCI) -+ memcpy(desc->data, pkt, len); -+ free_pkt = PFE_HOST_TO_PCI(pkt); -+ smp_wmb(); -+ desc->ctrl = CL_DESC_BUF_LEN(len) | flags; -+ inc_cl_idx(queue->write_idx); -+#else -+ //TODO: move allocations after Rx loop to improve instruction cache locality -+ if (page_mode) { -+ int rem_page_size = PAGE_SIZE - PRESENT_OFST_IN_PAGE(pkt); -+ int cur_pkt_size = ROUND_MIN_RX_SIZE(len + pfe_pkt_headroom); -+ *rem_len = (rem_page_size - cur_pkt_size); -+ //printk("%p rem_len %d cur_len %d buf_len %d\n", pkt, rem_page_size, cur_pkt_size, *rem_len); -+ if (*rem_len) -+ { -+ free_pkt = pkt + cur_pkt_size; -+ get_page(virt_to_page(free_pkt)); -+ } else { -+ free_pkt = (void *)__get_free_page(GFP_ATOMIC | GFP_DMA_PFE); -+ *rem_len = pfe_pkt_size; -+ } -+ } else { -+ free_pkt = kmalloc(PFE_BUF_SIZE, GFP_ATOMIC | GFP_DMA_PFE); -+ *rem_len = PFE_BUF_SIZE - pfe_pkt_headroom; -+ } -+ -+ if (free_pkt) { -+ desc->data = pkt; -+ desc->client_ctrl = client_ctrl; -+ smp_wmb(); -+ desc->ctrl = CL_DESC_BUF_LEN(len) | flags; -+ inc_cl_idx(queue->write_idx); -+ free_pkt += pfe_pkt_headroom; -+ } -+#endif -+ } -+ -+ return free_pkt; -+} -+ -+ -+/* pfe_hif_rx_process- -+ * This function does pfe hif rx queue processing. -+ * Dequeue packet from Rx queue and send it to corresponding client queue -+ */ -+static int pfe_hif_rx_process(struct pfe_hif *hif, int budget) -+{ -+ struct hif_desc *desc; -+ struct hif_hdr *pkt_hdr; -+ struct __hif_hdr hif_hdr; -+ void *free_buf; -+ int rtc, len, rx_processed = 0; -+ struct __hif_desc local_desc; -+ int flags; -+ unsigned int desc_p; -+ unsigned int buf_size = 0; -+ -+ spin_lock_bh(&hif->lock); -+ -+ rtc = hif->RxtocleanIndex; -+ -+ while (rx_processed < budget) -+ { -+ /*TODO may need to implement rx process budget */ -+ desc = hif->RxBase + rtc; -+ -+ __memcpy12(&local_desc, desc); -+ -+ /* ACK pending Rx interrupt */ -+ if (local_desc.ctrl & BD_CTRL_DESC_EN) { -+ writel(HIF_INT_MASK, HIF_INT_SRC); -+ -+ if(rx_processed == 0) -+ { -+ if(napi_first_batch == 1) -+ { -+ desc_p = hif->descr_baseaddr_p + ((unsigned long int)(desc) - (unsigned long int)hif->descr_baseaddr_v); -+#if defined(CONFIG_PLATFORM_C2000) -+ outer_inv_range(desc_p, (desc_p + 16)); -+#endif -+ napi_first_batch = 0; -+ } -+ } -+ -+ __memcpy12(&local_desc, desc); -+ -+ if (local_desc.ctrl & BD_CTRL_DESC_EN) -+ break; -+ } -+ -+ napi_first_batch = 0; -+ -+#ifdef HIF_NAPI_STATS -+ hif->napi_counters[NAPI_DESC_COUNT]++; -+#endif -+ len = BD_BUF_LEN(local_desc.ctrl); -+#if defined(CONFIG_PLATFORM_PCI) -+ pkt_hdr = &hif_hdr; -+ memcpy(pkt_hdr, (void *)PFE_PCI_TO_HOST(local_desc.data), sizeof(struct hif_hdr)); -+#else -+ //dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data), hif->rx_buf_len[rtc], DMA_FROM_DEVICE); -+ DMA_UNMAP_SINGLE(hif->dev, DDR_PFE_TO_PHYS(local_desc.data), hif->rx_buf_len[rtc], DMA_FROM_DEVICE); -+ -+ pkt_hdr = (struct hif_hdr *)hif->rx_buf_addr[rtc]; -+ -+ /* Track last HIF header received */ -+ if (!hif->started) { -+ hif->started = 1; -+ -+ __memcpy8(&hif_hdr, pkt_hdr); -+ -+ hif->qno = hif_hdr.hdr.qNo; -+ hif->client_id = hif_hdr.hdr.client_id; -+ hif->client_ctrl = (hif_hdr.hdr.client_ctrl1 << 16) | hif_hdr.hdr.client_ctrl; -+ flags = CL_DESC_FIRST; -+ -+// printk(KERN_INFO "start of packet: id %d, q %d, len %d, flags %x %x\n", hif->client_id, hif->qno, len, local_desc.ctrl, hif->client_ctrl); -+ } -+ else { -+// printk(KERN_INFO "continuation: id %d, q %d, len %d, flags %x\n", hif->client_id, hif->qno, len, local_desc.ctrl); -+ flags = 0; -+ } -+ -+ if (local_desc.ctrl & BD_CTRL_LIFM) -+ flags |= CL_DESC_LAST; -+#endif -+ /* Check for valid client id and still registered */ -+ if ((hif->client_id >= HIF_CLIENTS_MAX) || !(test_bit(hif->client_id, &hif->shm->gClient_status[0]))) { -+ if (printk_ratelimit()) -+ printk(KERN_ERR "%s: packet with invalid client id %d qNo %d\n", __func__, hif->client_id, hif->qno); -+ -+#if defined(CONFIG_PLATFORM_PCI) -+ free_buf = local_desc.data; -+#else -+ free_buf = pkt_hdr; -+#endif -+ goto pkt_drop; -+ } -+ -+ /* Check to valid queue number */ -+ if (hif->client[hif->client_id].rx_qn <= hif->qno) { -+ printk(KERN_INFO "%s: packet with invalid queue: %d\n", __func__, hif->qno); -+ hif->qno = 0; -+ } -+ -+#if defined(CONFIG_PLATFORM_PCI) -+ free_buf = client_put_rxpacket(&hif->client[hif->client_id].rx_q[hif->qno], -+ (void *)PFE_PCI_TO_HOST(desc->data), len, flags, hif->client_ctrl, &buf_zize); -+#else -+ free_buf = client_put_rxpacket(&hif->client[hif->client_id].rx_q[hif->qno], -+ (void *)pkt_hdr, len, flags, hif->client_ctrl, &buf_size); -+#endif -+ -+ hif_lib_indicate_client(hif->client_id, EVENT_RX_PKT_IND, hif->qno); -+ -+ if (unlikely(!free_buf)) { -+#ifdef HIF_NAPI_STATS -+ hif->napi_counters[NAPI_CLIENT_FULL_COUNT]++; -+#endif -+ /* If we want to keep in polling mode to retry later, we need to tell napi that we consumed -+ the full budget or we will hit a livelock scenario. The core code keeps this napi instance -+ at the head of the list and none of the other instances get to run */ -+ rx_processed = budget; -+ -+ if (flags & CL_DESC_FIRST) -+ hif->started = 0; -+ -+ break; -+ } -+ -+ pkt_drop: -+#if defined(CONFIG_PLATFORM_PCI) -+ desc->data = (u32)free_buf; -+#else -+ /*Fill free buffer in the descriptor */ -+ hif->rx_buf_addr[rtc] = free_buf; -+ hif->rx_buf_len[rtc] = min(pfe_pkt_size, buf_size); -+ desc->data = DDR_PHYS_TO_PFE((u32)DMA_MAP_SINGLE(hif->dev, free_buf, hif->rx_buf_len[rtc], DMA_FROM_DEVICE)); -+ //printk("#%p %p %d\n", desc->data, hif->rx_buf_addr[rtc], hif->rx_buf_len[rtc]); -+#endif -+ wmb(); -+ desc->ctrl = BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM | BD_CTRL_DIR | -+ BD_CTRL_DESC_EN | BD_BUF_LEN(hif->rx_buf_len[rtc]); -+ -+ inc_hif_rxidx(rtc); -+ -+ if (local_desc.ctrl & BD_CTRL_LIFM) { -+ if (!(hif->client_ctrl & HIF_CTRL_RX_CONTINUED)) { -+ rx_processed++; -+ -+#ifdef HIF_NAPI_STATS -+ hif->napi_counters[NAPI_PACKET_COUNT]++; -+#endif -+ } -+ hif->started = 0; -+ } -+ } -+ -+ hif->RxtocleanIndex = rtc; -+ spin_unlock_bh(&hif->lock); -+ -+ /* we made some progress, re-start rx dma in case it stopped */ -+ hif_rx_dma_start(); -+ -+ return rx_processed; -+} -+ -+ -+/* client_ack_txpacket- -+ * This function ack the Tx packet in the give client Tx queue by resetting -+ * ownership bit in the descriptor. -+ */ -+static int client_ack_txpacket(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no) -+{ -+ struct hif_tx_queue *queue = &hif->client[client_id].tx_q[q_no]; -+ struct tx_queue_desc *desc = queue->base + queue->ack_idx; -+ -+ if (desc->ctrl & CL_DESC_OWN) { -+ /*TODO Do we need to match the pkt address also? */ -+ desc->ctrl &= ~CL_DESC_OWN; -+ inc_cl_idx(queue->ack_idx); -+ -+ return 0; -+ } -+ else { -+ /*This should not happen */ -+ printk(KERN_ERR "%s: %d %d %d %d %d %p %d\n", __func__, hif->Txtosend, hif->Txtoclean, hif->TxAvail, client_id, q_no, queue, queue->ack_idx); -+ BUG(); -+ return 1; -+ } -+} -+ -+void __hif_tx_done_process(struct pfe_hif *hif, int count) -+{ -+ struct hif_desc *desc; -+ struct hif_desc_sw *desc_sw; -+ int ttc, tx_avl; -+ -+ ttc = hif->Txtoclean; -+ tx_avl = hif->TxAvail; -+ -+ while ((tx_avl < hif->TxRingSize) && count--) { -+ desc = hif->TxBase + ttc; -+ -+ if (desc->ctrl & BD_CTRL_DESC_EN) -+ break; -+ -+ desc_sw = &hif->tx_sw_queue[ttc]; -+ -+ if (desc_sw->data) { -+#if !defined(CONFIG_PLATFORM_PCI) -+ //dmap_unmap_single(hif->dev, desc_sw->data, desc_sw->len, DMA_TO_DEVICE); -+ DMA_UNMAP_SINGLE(hif->dev, desc_sw->data, desc_sw->len, DMA_TO_DEVICE); -+#endif -+ } -+ client_ack_txpacket(hif, desc_sw->client_id, desc_sw->q_no); -+ -+ inc_hif_txidx(ttc); -+ tx_avl++; -+ } -+ -+ hif->Txtoclean = ttc; -+ hif->TxAvail = tx_avl; -+} -+ -+ -+/* __hif_xmit_pkt - -+ * This function puts one packet in the HIF Tx queue -+ */ -+void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no, void *data, u32 len, unsigned int flags) -+{ -+ struct hif_desc *desc; -+ struct hif_desc_sw *desc_sw; -+ -+#if defined(CONFIG_PLATFORM_EMULATION) -+ { -+ struct hif_queue *queue = &hif->client[client_id].rx_q[0]; -+ struct queue_desc *qdesc = queue->base + queue->write_idx; -+ void *buf; -+ -+ printk("%s: packet loop backed client_id:%d qno:%d data : %p len:%d\n", __func__, client_id, q_no, data, len); -+#if 1 -+ if (qdesc->ctrl & CL_DESC_OWN) { -+ buf = (void *)qdesc->data; -+ memcpy(buf, data, len); -+ wmb(); -+ qdesc->ctrl = CL_DESC_BUF_LEN(len); -+ inc_cl_idx(queue->write_idx); -+ printk("%s: packet loop backed..\n", __func__); -+ hif_lib_indicate_client(client_id, EVENT_RX_PKT_IND, q_no); -+ client_ack_txpacket(&hif->client[client_id].tx_q[q_no]); -+ } -+#endif -+ } -+ -+#else -+ desc = hif->TxBase + hif->Txtosend; -+ desc_sw = &hif->tx_sw_queue[hif->Txtosend]; -+ -+ desc_sw->len = len; -+ desc_sw->client_id = client_id; -+ desc_sw->q_no = q_no; -+ desc_sw->flags = flags; -+ -+#if !defined(CONFIG_PLATFORM_PCI) -+ if (flags & HIF_DONT_DMA_MAP) { -+ desc_sw->data = 0; -+ desc->data = (u32)DDR_PHYS_TO_PFE(data); -+ } else { -+ desc_sw->data = DMA_MAP_SINGLE(hif->dev, data, len, DMA_TO_DEVICE); -+ desc->data = (u32)DDR_PHYS_TO_PFE(desc_sw->data); -+ } -+#else -+#define ALIGN32(x) ((x) & ~0x3) -+ memcpy(PFE_PCI_TO_HOST(desc->data), data, ALIGN32(len+0x3)); -+#endif -+ -+ inc_hif_txidx(hif->Txtosend); -+ hif->TxAvail--; -+ -+ /* For TSO we skip actual TX until the last descriptor */ -+ /* This reduce the number of required wmb() */ -+ if ((flags & HIF_TSO) && (!((flags & HIF_DATA_VALID) && (flags & HIF_LAST_BUFFER)))) -+ goto skip_tx; -+ -+ wmb(); -+ -+ do { -+ desc_sw = &hif->tx_sw_queue[hif->Txtoflush]; -+ desc = hif->TxBase + hif->Txtoflush; -+ -+ if (desc_sw->flags & HIF_LAST_BUFFER) { -+ if ((desc_sw->client_id < PFE_CL_VWD0) || (desc_sw->client_id > (PFE_CL_VWD0 + MAX_VAP_SUPPORT))) -+ desc->ctrl = BD_CTRL_LIFM | BD_CTRL_BRFETCH_DISABLE | -+ BD_CTRL_RTFETCH_DISABLE | BD_CTRL_PARSE_DISABLE | -+ BD_CTRL_DESC_EN | BD_BUF_LEN(desc_sw->len); -+ else { -+ -+ desc->ctrl = BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_BUF_LEN(desc_sw->len); -+ } -+ } -+ else -+ desc->ctrl = BD_CTRL_DESC_EN | BD_BUF_LEN(desc_sw->len); -+ -+ inc_hif_txidx(hif->Txtoflush); -+ } -+ while (hif->Txtoflush != hif->Txtosend); -+ -+skip_tx: -+ return; -+ -+#endif -+} -+ -+ -+int hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no, void *data, unsigned int len) -+{ -+ int rc = 0; -+ -+ spin_lock_bh(&hif->tx_lock); -+ -+ if (!hif->TxAvail) -+ rc = 1; -+ else { -+ __hif_xmit_pkt(hif, client_id, q_no, data, len, HIF_FIRST_BUFFER | HIF_LAST_BUFFER); -+ hif_tx_dma_start(); -+ } -+ if (hif->TxAvail < (hif->TxRingSize >> 1)) -+ __hif_tx_done_process(hif, TX_FREE_MAX_COUNT); -+ -+ spin_unlock_bh(&hif->tx_lock); -+ -+ return rc; -+} -+ -+/* hif_isr- -+ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block -+ */ -+static irqreturn_t hif_isr(int irq, void *dev_id) -+{ -+ struct pfe_hif *hif = (struct pfe_hif *) dev_id; -+ int int_status; -+ -+ /*Read hif interrupt source register */ -+ int_status = readl_relaxed(HIF_INT_SRC); -+ -+ if ((int_status & HIF_INT) == 0) -+ return(IRQ_NONE); -+ -+ int_status &= ~(HIF_INT); -+ -+ if (int_status & HIF_RXPKT_INT) { -+ int_status &= ~(HIF_RXPKT_INT); -+ -+ /* Disable interrupts */ -+ writel_relaxed(0, HIF_INT_ENABLE); -+ -+ napi_first_batch = 1; -+ -+ if (napi_schedule_prep(&hif->napi)) -+ { -+#ifdef HIF_NAPI_STATS -+ hif->napi_counters[NAPI_SCHED_COUNT]++; -+#endif -+ __napi_schedule(&hif->napi); -+ } -+ } -+ -+ if (int_status) { -+ printk(KERN_INFO "%s : Invalid interrupt : %d\n", __func__, int_status); -+ writel(int_status, HIF_INT_SRC); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+ -+void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int data2) -+{ -+ unsigned int client_id = data1; -+ -+ if (client_id >= HIF_CLIENTS_MAX) -+ { -+ printk(KERN_ERR "%s: client id %d out of bounds\n", __func__, client_id); -+ return; -+ } -+ -+ switch (req) { -+ case REQUEST_CL_REGISTER: -+ /* Request for register a client */ -+ printk(KERN_INFO "%s: register client_id %d\n", __func__, client_id); -+ pfe_hif_client_register(hif, client_id, (struct hif_client_shm *)&hif->shm->client[client_id]); -+ break; -+ -+ case REQUEST_CL_UNREGISTER: -+ printk(KERN_INFO "%s: unregister client_id %d\n", __func__, client_id); -+ -+ /* Request for unregister a client */ -+ pfe_hif_client_unregister(hif, client_id); -+ -+ break; -+ -+ default: -+ printk(KERN_ERR "%s: unsupported request %d\n", __func__, req); -+ break; -+ } -+ -+ /*TODO check for TMU queue resume request */ -+ -+ /*Process client Tx queues -+ * Currently we don't have checking for tx pending*/ -+} -+ -+/** pfe_hif_rx_poll -+ * This function is NAPI poll function to process HIF Rx queue. -+ */ -+static int pfe_hif_rx_poll(struct napi_struct *napi, int budget) -+{ -+ struct pfe_hif *hif = container_of(napi, struct pfe_hif, napi); -+ int work_done; -+ -+#ifdef HIF_NAPI_STATS -+ hif->napi_counters[NAPI_POLL_COUNT]++; -+#endif -+ -+ work_done = pfe_hif_rx_process(hif, budget); -+ -+ if (work_done < budget) -+ { -+ napi_complete(napi); -+ writel_relaxed(HIF_INT_MASK, HIF_INT_ENABLE); -+ } -+#ifdef HIF_NAPI_STATS -+ else -+ hif->napi_counters[NAPI_FULL_BUDGET_COUNT]++; -+#endif -+ -+ return work_done; -+} -+ -+/* pfe_hif_init -+ * This function initializes the baseaddresses and irq, etc. -+ */ -+int pfe_hif_init(struct pfe *pfe) -+{ -+ struct pfe_hif *hif = &pfe->hif; -+ int err; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ hif->dev = pfe->dev; -+ hif->irq = pfe->hif_irq; -+ -+ if ((err = pfe_hif_alloc_descr(hif))) { -+ goto err0; -+ } -+ -+ if (pfe_hif_init_buffers(hif)) { -+ printk(KERN_ERR "%s: Could not initialize buffer descriptors\n", __func__); -+ err = -ENOMEM; -+ goto err1; -+ } -+ -+ /* Initilize NAPI for Rx processing */ -+ init_dummy_netdev(&hif->dummy_dev); -+ netif_napi_add(&hif->dummy_dev, &hif->napi, pfe_hif_rx_poll, HIF_RX_POLL_WEIGHT); -+ napi_enable(&hif->napi); -+ -+ spin_lock_init(&hif->tx_lock); -+ spin_lock_init(&hif->lock); -+ -+ hif_init(); -+ hif_rx_enable(); -+ hif_tx_enable(); -+ -+ /* Disable tx done interrupt */ -+ writel(HIF_INT_MASK, HIF_INT_ENABLE); -+ -+ gpi_enable(HGPI_BASE_ADDR); -+ -+#ifdef __KERNEL__ -+ err = request_irq(hif->irq, hif_isr, 0, "pfe_hif", hif); -+ if (err) { -+ printk(KERN_ERR "%s: failed to get the hif IRQ = %d\n", __func__, hif->irq); -+ goto err1; -+ } -+#else -+ /*TODO register interrupts */ -+#endif -+ -+ return 0; -+err1: -+ pfe_hif_free_descr(hif); -+err0: -+ return err; -+} -+ -+/* pfe_hif_exit- -+ */ -+void pfe_hif_exit(struct pfe *pfe) -+{ -+ struct pfe_hif *hif = &pfe->hif; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ spin_lock_bh(&hif->lock); -+ hif->shm->gClient_status[0] = 0; -+ hif->shm->gClient_status[1] = 0; /* Make sure all clients are disabled */ -+ -+ spin_unlock_bh(&hif->lock); -+ -+ /*Disable Rx/Tx */ -+ gpi_disable(HGPI_BASE_ADDR); -+ hif_rx_disable(); -+ hif_tx_disable(); -+ -+ napi_disable(&hif->napi); -+ netif_napi_del(&hif->napi); -+ -+#ifdef __KERNEL__ -+ free_irq(hif->irq, hif); -+#endif -+ pfe_hif_release_buffers(hif); -+ pfe_hif_free_descr(hif); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hif.h -@@ -0,0 +1,322 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _PFE_HIF_H_ -+#define _PFE_HIF_H_ -+ -+#include -+ -+#define HIF_NAPI_STATS -+ -+#define HIF_CLIENT_QUEUES_MAX 16 -+#define HIF_RX_POLL_WEIGHT 64 -+ -+#define HIF_RX_PKT_MIN_SIZE 0x800 /* 2KB */ -+#define HIF_RX_PKT_MIN_SIZE_MASK ~(HIF_RX_PKT_MIN_SIZE - 1) -+#define ROUND_MIN_RX_SIZE(_sz) ((_sz + (HIF_RX_PKT_MIN_SIZE - 1)) & HIF_RX_PKT_MIN_SIZE_MASK) -+#define PRESENT_OFST_IN_PAGE(_buf) (((unsigned long int)_buf & (PAGE_SIZE - 1)) & HIF_RX_PKT_MIN_SIZE_MASK) -+ -+enum { -+ NAPI_SCHED_COUNT = 0, -+ NAPI_POLL_COUNT, -+ NAPI_PACKET_COUNT, -+ NAPI_DESC_COUNT, -+ NAPI_FULL_BUDGET_COUNT, -+ NAPI_CLIENT_FULL_COUNT, -+ NAPI_MAX_COUNT -+}; -+ -+ -+/* XXX HIF_TX_DESC_NT value should be always greter than 4, -+ * Otherwise HIF_TX_POLL_MARK will become zero. -+ */ -+#if defined(CONFIG_PLATFORM_PCI) -+#define HIF_RX_DESC_NT 4 -+#define HIF_TX_DESC_NT 4 -+#else -+#if defined(CONFIG_COMCERTO_64K_PAGES) -+#define HIF_RX_DESC_NT 64 -+#else -+#define HIF_RX_DESC_NT 256 -+#endif -+#define HIF_TX_DESC_NT 2048 -+#endif -+ -+#define HIF_FIRST_BUFFER (1 << 0) -+#define HIF_LAST_BUFFER (1 << 1) -+#define HIF_DONT_DMA_MAP (1 << 2) //TODO merge it with TSO -+#define HIF_DATA_VALID (1 << 3) -+#define HIF_TSO (1 << 4) -+ -+#define MAX_VAP_SUPPORT 3 -+#define MAX_WIFI_VAPS MAX_VAP_SUPPORT -+ -+enum { -+ PFE_CL_GEM0 = 0, -+ PFE_CL_GEM1, -+ PFE_CL_GEM2, -+ PFE_CL_VWD0, -+ PFE_CL_VWD_LAST = PFE_CL_VWD0 + MAX_VAP_SUPPORT, -+ PFE_CL_PCAP0, -+ HIF_CLIENTS_MAX -+}; -+ -+/*structure to store client queue info */ -+struct hif_rx_queue { -+ struct rx_queue_desc *base; -+ u32 size; -+ u32 write_idx; -+}; -+ -+struct hif_tx_queue { -+ struct tx_queue_desc *base; -+ u32 size; -+ u32 ack_idx; -+}; -+ -+/*Structure to store the client info */ -+struct hif_client { -+ int rx_qn; -+ struct hif_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX]; -+ int tx_qn; -+ struct hif_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX]; -+}; -+ -+/*HIF hardware buffer descriptor */ -+struct hif_desc { -+ volatile u32 ctrl; -+ volatile u32 status; -+ volatile u32 data; -+ volatile u32 next; -+}; -+ -+struct __hif_desc { -+ u32 ctrl; -+ u32 status; -+ u32 data; -+}; -+ -+struct hif_desc_sw { -+ dma_addr_t data; -+ u16 len; -+ u8 client_id; -+ u8 q_no; -+ u16 flags; -+}; -+ -+struct hif_hdr { -+ u8 client_id; -+ u8 qNo; -+ u16 client_ctrl; -+ u16 client_ctrl1; -+}; -+ -+struct __hif_hdr { -+ union { -+ struct hif_hdr hdr; -+ u32 word[2]; -+ }; -+}; -+ -+struct hif_lro_hdr { -+ u16 data_offset; -+ u16 mss; -+}; -+ -+struct hif_ipsec_hdr { -+ u16 sa_handle[2]; -+}__attribute__((packed)); -+ -+#define MAX_TSO_BUF_DESCS 5 -+struct hif_tso_buf_desc { -+ u32 addr; -+ u32 ctrl; -+#define TSO_CTRL_LAST_BUFFER (1 << 31) -+}; -+ -+struct hif_tso_hdr { -+ struct hif_hdr pkt_hdr; -+ u16 ip_off; -+ u16 ip_id; -+ u16 ip_len; -+ u16 tcp_off; -+ u32 tcp_seq; -+} __attribute__((packed)); -+ -+struct hif_tso_hdr_nocpy { -+ struct hif_tso_hdr tso_hdr; -+ struct hif_tso_buf_desc bdesc[MAX_TSO_BUF_DESCS]; -+} __attribute__((packed)); -+ -+struct hif_pcap_hdr { -+ u8 ifindex; -+ u8 unused; -+ u16 seqno; -+ u32 timestamp; -+}__attribute__((packed)); -+ -+/* HIF_CTRL_TX... defines */ -+#define HIF_CTRL_TX_TSO_NOCPY (1 << 8) -+#define HIF_CTRL_TX_IPSEC_OUT (1 << 7) -+#define HIF_CTRL_TX_OWN_MAC (1 << 6) -+#define HIF_CTRL_TX_TSO_END (1 << 5) -+#define HIF_CTRL_TX_TSO6 (1 << 4) -+#define HIF_CTRL_TX_TSO (1 << 3) -+#define HIF_CTRL_TX_CHECKSUM (1 << 2) -+#define HIF_CTRL_TX_CSUM_VALIDATE (1 << 1) -+#define HIF_CTRL_TX_WIFI (1 << 0) -+ -+/* HIF_CTRL_RX... defines */ -+#define HIF_CTRL_RX_OFFSET_OFST (24) -+#define HIF_CTRL_RX_PE_ID_OFST (16) -+#define HIF_CTRL_RX_IPSEC_IN (1 << 4) -+#define HIF_CTRL_RX_WIFI_EXPT (1 << 3) -+#define HIF_CTRL_RX_CHECKSUMMED (1 << 2) -+#define HIF_CTRL_RX_CONTINUED (1 << 1) -+#define HIF_CTRL_RX_WIFI_HEADROOM (1 << 0) -+ -+#define HIF_CTRL_VAPID_OFST (8) -+ -+struct pfe_hif { -+ /* To store registered clients in hif layer */ -+ struct hif_client client[HIF_CLIENTS_MAX]; -+ struct hif_shm *shm; -+ int irq; -+ -+ void *descr_baseaddr_v; -+ unsigned long descr_baseaddr_p; -+ -+ struct hif_desc *RxBase; -+ u32 RxRingSize; -+ u32 RxtocleanIndex; -+ void *rx_buf_addr[HIF_RX_DESC_NT]; -+ int rx_buf_len[HIF_RX_DESC_NT]; -+ unsigned int qno; -+ unsigned int client_id; -+ unsigned int client_ctrl; -+ unsigned int started; -+ -+ struct hif_desc *TxBase; -+ u32 TxRingSize; -+ u32 Txtosend; -+ u32 Txtoclean; -+ u32 TxAvail; -+ u32 Txtoflush; -+ struct hif_desc_sw tx_sw_queue[HIF_TX_DESC_NT]; -+ struct hif_tso_hdr_nocpy *tso_hdr_v; -+ dma_addr_t tso_hdr_p; -+ -+ spinlock_t tx_lock; -+ spinlock_t lock; -+ struct net_device dummy_dev; -+ struct napi_struct napi; -+ struct device *dev; -+ -+#ifdef CONFIG_HOTPLUG_CPU -+ struct notifier_block cpu_notify; -+#endif -+ -+#ifdef HIF_NAPI_STATS -+ unsigned int napi_counters[NAPI_MAX_COUNT]; -+#endif -+}; -+ -+void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no, void *data, u32 len, unsigned int flags); -+int hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no, void *data, unsigned int len); -+void __hif_tx_done_process(struct pfe_hif *hif, int count); -+void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int data2); -+int pfe_hif_init(struct pfe *pfe); -+void pfe_hif_exit(struct pfe *pfe); -+ -+static inline void hif_tx_done_process(struct pfe_hif *hif, int count) -+{ -+ spin_lock_bh(&hif->tx_lock); -+ __hif_tx_done_process(hif, count); -+ spin_unlock_bh(&hif->tx_lock); -+} -+ -+static inline void hif_tx_lock(struct pfe_hif *hif) -+{ -+ spin_lock_bh(&hif->tx_lock); -+} -+ -+static inline void hif_tx_unlock(struct pfe_hif *hif) -+{ -+ spin_unlock_bh(&hif->tx_lock); -+} -+ -+static inline int __hif_tx_avail(struct pfe_hif *hif) -+{ -+ return hif->TxAvail; -+} -+ -+#if defined(CONFIG_PLATFORM_C2000) -+static inline void __memcpy8(void *dst, void *src) -+{ -+ asm volatile ( "ldm %1, {r9, r10}\n\t" -+ "stm %0, {r9, r10}\n\t" -+ : -+ : "r" (dst), "r" (src) -+ : "r9", "r10", "memory" -+ ); -+} -+ -+static inline void __memcpy12(void *dst, void *src) -+{ -+ asm volatile ( "ldm %1, {r8, r9, r10}\n\t" -+ "stm %0, {r8, r9, r10}\n\t" -+ : -+ : "r" (dst), "r" (src) -+ : "r8", "r9", "r10", "memory" -+ ); -+} -+ -+static inline void __memcpy16(void *dst, void *src) -+{ -+ asm volatile ( "ldm %1, {r7, r8, r9, r10}\n\t" -+ "stm %0, {r7, r8, r9, r10}\n\t" -+ : -+ : "r"(dst), "r"(src) -+ : "r7", "r8", "r9", "r10", "memory" -+ ); -+} -+ -+#define HIF_MEMCPY_BURSTSIZE 32 /*__memcpy copy 32byte in a burst*/ -+static inline void __memcpy(void *dst, void *src, unsigned int len) -+{ -+ void *end = src + len; -+ -+ dst = (void *)((unsigned long)dst & ~0x3); -+ src = (void *)((unsigned long)src & ~0x3); -+ -+ while (src < end) { -+ asm volatile ( "ldm %1!, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" -+ "stm %0!, {r3, r4, r5, r6, r7, r8, r9, r10}\n\t" -+ : "+r"(dst), "+r"(src) -+ : -+ : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "memory" -+ ); -+ } -+} -+#else -+#define __memcpy8(dst, src) memcpy(dst, src, 8) -+#define __memcpy12(dst, src) memcpy(dst, src, 12) -+#define __memcpy(dst, src, len) memcpy(dst, src, len) -+#endif -+#endif /* _PFE_HIF_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.c -@@ -0,0 +1,658 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) -+//#include -+#endif -+ -+#include "pfe_mod.h" -+#include "pfe_hif.h" -+#include "pfe_hif_lib.h" -+#include "pfe_ctrl_hal.h" -+ -+ -+unsigned int lro_mode = 0; -+unsigned int page_mode = 0; -+unsigned int tx_qos = 0; -+unsigned int pfe_pkt_size; -+unsigned int pfe_pkt_headroom; -+unsigned int emac_txq_cnt; -+ -+/** @pfe_hal_lib.c. -+ * Common functions used by HIF client drivers -+ */ -+ -+/*HIF shared memory Global variable */ -+struct hif_shm ghif_shm; -+ -+/* TMU tx transmitted packets counter, 1 per TMU */ -+unsigned int TMU_DMEM_SH(tx_trans)[EMAC_TXQ_CNT]; -+ -+/* Cleanup the HIF shared memory, release HIF rx_buffer_pool. -+ * This function should be called after pfe_hif_exit -+ * -+ * @param[in] hif_shm Shared memory address location in DDR -+ */ -+static void pfe_hif_shm_clean(struct hif_shm *hif_shm) -+{ -+ int i; -+ void *pkt; -+ -+ for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) { -+ pkt = hif_shm->rx_buf_pool[i]; -+ if (pkt) { -+ hif_shm->rx_buf_pool[i] = NULL; -+ pkt -= pfe_pkt_headroom; -+ -+ if (page_mode) { -+ put_page(virt_to_page(pkt)); -+ } else -+ kfree(pkt); -+ } -+ } -+} -+ -+/* Initialize shared memory used between HIF driver and clients, -+ * allocate rx_buffer_pool required for HIF Rx descriptors. -+ * This function should be called before initializing HIF driver. -+ * -+ * @param[in] hif_shm Shared memory address location in DDR -+ * @rerurn 0 - on succes, <0 on fail to initialize -+ */ -+static int pfe_hif_shm_init(struct hif_shm *hif_shm) -+{ -+ int i; -+ void *pkt; -+ -+ memset(hif_shm, 0, sizeof(struct hif_shm)); -+ hif_shm->rx_buf_pool_cnt = HIF_RX_DESC_NT; -+ -+ for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) { -+ if (page_mode) { -+ pkt = (void *)__get_free_page(GFP_KERNEL | GFP_DMA_PFE); -+ } else -+ pkt = kmalloc(PFE_BUF_SIZE, GFP_KERNEL | GFP_DMA_PFE); -+ -+ if (pkt) -+ hif_shm->rx_buf_pool[i] = pkt + pfe_pkt_headroom; -+ else -+ goto err0; -+ } -+ -+ return 0; -+ -+err0: -+ printk(KERN_ERR "%s Low memory\n", __func__); -+ pfe_hif_shm_clean(hif_shm); -+ return -ENOMEM; -+} -+ -+/*This function sends indication to HIF driver -+ * -+ * @param[in] hif hif context -+ **/ -+static void hif_lib_indicate_hif(struct pfe_hif *hif, int req, int data1, int data2) -+{ -+ //TODO : If we separate HIF and HIF LIB, then send req and data through shared memory. -+ -+ hif_process_client_req(hif, req, data1, data2); -+} -+ -+void hif_lib_indicate_client(int client_id, int event_type, int qno) -+{ -+ struct hif_client_s *client = pfe->hif_client[client_id]; -+ -+ /* -+ * TODO : Right now, all events are queue number based. So we are masking events per queue -+ * basis. Later if we add any events those do not depend on queue number, then we may -+ * may need may need to add masking per event. -+ */ -+ if (!client || (event_type >= HIF_EVENT_MAX) || (qno >= HIF_CLIENT_QUEUES_MAX) ) -+ return; -+ -+ if (!test_and_set_bit(qno, &client->queue_mask[event_type])) { -+ client->event_handler(client->priv, event_type, qno); -+ } -+ -+} -+ -+ -+/*This function releases Rx queue descriptors memory and pre-filled buffers -+ * -+ * @param[in] client hif_client context -+ */ -+static void hif_lib_client_release_rx_buffers(struct hif_client_s *client) -+{ -+ struct rx_queue_desc *desc; -+ int qno, ii; -+ void *buf; -+ -+ for (qno = 0; qno < client->rx_qn; qno++) { -+ desc = client->rx_q[qno].base; -+ -+ for (ii = 0; ii < client->rx_q[qno].size; ii++) { -+ buf = (void *)desc->data; -+ if (buf) { -+ buf -= pfe_pkt_headroom; -+ -+ if (page_mode) -+ free_page((unsigned long)buf); -+ else -+ kfree(buf); -+ -+ desc->ctrl = 0; -+ } -+ -+ desc++; -+ } -+ } -+ -+ kfree(client->rx_qbase); -+} -+ -+ -+/*This function allocates memory for the rxq descriptors and pre-fill rx queues -+ * with buffers. -+ * @param[in] client client context -+ * @param[in] q_size size of the rxQ, all queues are of same size -+ */ -+static int hif_lib_client_init_rx_buffers(struct hif_client_s *client, int q_size) -+{ -+ struct rx_queue_desc *desc; -+ struct hif_client_rx_queue *queue; -+ int ii, qno; -+ -+ /*Allocate memory for the client queues */ -+ client->rx_qbase = kzalloc(client->rx_qn * q_size * sizeof(struct rx_queue_desc), GFP_KERNEL); -+ if (!client->rx_qbase){ -+ goto err; -+ } -+ -+ for (qno = 0; qno < client->rx_qn; qno++) { -+ queue = &client->rx_q[qno]; -+ -+ queue->base = client->rx_qbase + qno * q_size * sizeof(struct rx_queue_desc); -+ queue->size = q_size; -+ queue->read_idx = 0; -+ queue->write_idx = 0; -+ -+ dbg_print_info("rx queue: %d, base: %p, size: %d \n", qno, queue->base, queue->size); -+ } -+ -+ for (qno = 0; qno < client->rx_qn; qno++) { -+ queue = &client->rx_q[qno]; -+ desc = queue->base; -+ -+ for (ii = 0; ii < queue->size; ii++) { -+ desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | CL_DESC_OWN; -+ desc++; -+ } -+ } -+ -+ return 0; -+ -+err: -+ return 1; -+} -+ -+#define inc_cl_idx(idxname) idxname = (idxname+1) & (queue->size-1) -+ -+static void hif_lib_client_cleanup_tx_queue(struct hif_client_tx_queue *queue) -+{ -+ dbg_print_info( "%s\n", __func__); -+ -+ /* Check if there are any pending packets. Client must flush the tx queues -+ before unregistering, by calling by calling hif_lib_tx_get_next_complete() */ -+ /* Hif no longer calls since we are no longer registered */ -+ -+ if (queue->tx_pending) -+ printk(KERN_ERR "%s: pending transmit packets\n", __func__); -+} -+ -+static void hif_lib_client_release_tx_buffers(struct hif_client_s *client) -+{ -+ int qno; -+ -+ dbg_print_info("%s\n", __func__); -+ -+ for (qno = 0; qno < client->tx_qn; qno++) { -+ hif_lib_client_cleanup_tx_queue(&client->tx_q[qno]); -+ } -+ -+ kfree(client->tx_qbase); -+} -+ -+static int hif_lib_client_init_tx_buffers(struct hif_client_s *client, int q_size) -+{ -+ struct hif_client_tx_queue *queue; -+ int qno; -+ -+ client->tx_qbase = kzalloc(client->tx_qn * q_size * sizeof(struct tx_queue_desc), GFP_KERNEL); -+ if (!client->tx_qbase) { -+ return 1; -+ } -+ -+ for (qno = 0; qno < client->tx_qn; qno++) { -+ queue = &client->tx_q[qno]; -+ -+ queue->base = client->tx_qbase + qno * q_size * sizeof(struct tx_queue_desc); -+ queue->size = q_size; -+ queue->read_idx = 0; -+ queue->write_idx = 0; -+ queue->tx_pending = 0; -+ queue->nocpy_flag = 0; -+ queue->prev_tmu_tx_pkts = 0; -+ queue->done_tmu_tx_pkts = 0; -+ -+ dbg_print_info("tx queue: %d, base: %p, size: %d \n", qno, queue->base, queue->size); -+ } -+ -+ return 0; -+} -+ -+static int hif_lib_event_dummy( void *priv, int event_type, int qno) -+{ -+ return 0; -+} -+ -+int hif_lib_client_register(struct hif_client_s *client) -+{ -+ struct hif_shm *hif_shm; -+ struct hif_client_shm *client_shm; -+ int err, i; -+// int loop_cnt = 0; -+ -+ dbg_print_info("%s\n", __func__); -+ -+ /*Allocate memory before spin_lock*/ -+ if (hif_lib_client_init_rx_buffers(client, client->rx_qsize)) { -+ err = -ENOMEM; -+ goto err_rx; -+ } -+ -+ if (hif_lib_client_init_tx_buffers(client, client->tx_qsize)) { -+ err = -ENOMEM; -+ goto err_tx; -+ } -+ -+ spin_lock_bh(&pfe->hif.lock); -+ if (!(client->pfe) || (client->id >= HIF_CLIENTS_MAX) || (pfe->hif_client[client->id])) { -+ err = -EINVAL; -+ goto err; -+ } -+ -+ hif_shm = client->pfe->hif.shm; -+ -+ if (!client->event_handler) -+ client->event_handler = hif_lib_event_dummy; -+ -+ /*Initialize client specific shared memory */ -+ client_shm = (struct hif_client_shm *)&hif_shm->client[client->id]; -+ client_shm->rx_qbase = (unsigned long int)client->rx_qbase; -+ client_shm->rx_qsize = client->rx_qsize; -+ client_shm->tx_qbase = (unsigned long int)client->tx_qbase; -+ client_shm->tx_qsize = client->tx_qsize; -+ client_shm->ctrl = (client->tx_qn << CLIENT_CTRL_TX_Q_CNT_OFST) | (client->rx_qn << CLIENT_CTRL_RX_Q_CNT_OFST); -+// spin_lock_init(&client->rx_lock); -+ -+ for (i = 0; i < HIF_EVENT_MAX; i++) { -+ client->queue_mask[i] = 0; /* By default all events are unmasked */ -+ } -+ -+ /*Indicate to HIF driver*/ -+ hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_REGISTER, client->id, 0); -+ -+ dbg_print_info("%s: client: %p, client_id: %d, tx_qsize: %d, rx_qsize: %d\n", -+ __func__, client, client->id, client->tx_qsize, client->rx_qsize); -+ -+ client->cpu_id = -1; -+ -+ pfe->hif_client[client->id] = client; -+ spin_unlock_bh(&pfe->hif.lock); -+ -+ return 0; -+ -+err: -+ spin_unlock_bh(&pfe->hif.lock); -+ hif_lib_client_release_tx_buffers(client); -+ -+err_tx: -+ hif_lib_client_release_rx_buffers(client); -+ -+err_rx: -+ return err; -+} -+ -+int hif_lib_client_unregister(struct hif_client_s *client) -+{ -+ struct pfe *pfe = client->pfe; -+ u32 client_id = client->id; -+ -+ printk(KERN_INFO "%s : client: %p, client_id: %d, txQ_depth: %d, rxQ_depth: %d\n", -+ __func__, client, client->id, client->tx_qsize, client->rx_qsize); -+ -+ -+ spin_lock_bh(&pfe->hif.lock); -+ hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_UNREGISTER, client->id, 0); -+ -+ hif_lib_client_release_tx_buffers(client); -+ hif_lib_client_release_rx_buffers(client); -+ pfe->hif_client[client_id] = NULL; -+ spin_unlock_bh(&pfe->hif.lock); -+ -+ return 0; -+} -+ -+int hif_lib_event_handler_start(struct hif_client_s *client, int event, int qno) -+{ -+ struct hif_client_rx_queue *queue = &client->rx_q[qno]; -+ struct rx_queue_desc *desc = queue->base + queue->read_idx; -+ -+ if ((event >= HIF_EVENT_MAX) || ( qno >= HIF_CLIENT_QUEUES_MAX)) { -+ dbg_print_info("%s: Unsupported event : %d queue number : %d\n", __func__, event, qno); -+ return -1; -+ } -+ -+ test_and_clear_bit(qno, &client->queue_mask[event]); -+ -+ switch (event) { -+ case EVENT_RX_PKT_IND: -+ if (!(desc->ctrl & CL_DESC_OWN)) -+ hif_lib_indicate_client(client->id, EVENT_RX_PKT_IND, qno); -+ break; -+ -+ case EVENT_HIGH_RX_WM: -+ case EVENT_TXDONE_IND: -+ default: -+ break; -+ } -+ -+ return 0; -+} -+ -+ -+/*This function gets one packet from the specified client queue -+ * It also refill the rx buffer */ -+void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int *ofst, unsigned int *rx_ctrl, unsigned int *desc_ctrl, void **priv_data) -+{ -+ struct hif_client_rx_queue *queue = &client->rx_q[qno]; -+ struct rx_queue_desc *desc; -+ void *pkt = NULL; -+ -+ //printk(KERN_INFO "%s\n", __func__); -+#if defined(CONFIG_PLATFORM_EMULATION) -+ printk(KERN_INFO "%s:qno:%d cid:%d desc:%p rdidx:%d \n", -+ __func__, qno, client->id, desc, -+ queue->read_idx); -+#endif -+ -+ /* Following lock is to protect rx queue access from, hif_lib_event_handler_start. -+ * In general below lock is not required, because hif_lib_xmit_pkt and -+ * hif_lib_event_handler_start are called from napi poll and which is not -+ * re-entrant. But if some client use in different way this lock is required. -+ */ -+ //spin_lock_irqsave(&client->rx_lock, flags); -+ desc = queue->base + queue->read_idx; -+ if (!(desc->ctrl & CL_DESC_OWN)) { -+ pkt = desc->data - pfe_pkt_headroom; -+ -+ *rx_ctrl = desc->client_ctrl; -+ *desc_ctrl = desc->ctrl; -+ -+ if (desc->ctrl & CL_DESC_FIRST) { -+ u16 size = *rx_ctrl >> HIF_CTRL_RX_OFFSET_OFST; -+ -+ if (size) { -+ *len = CL_DESC_BUF_LEN(desc->ctrl) - PFE_PKT_HEADER_SZ - size; -+ *ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ + size; -+ *priv_data = desc->data + PFE_PKT_HEADER_SZ; -+ } else { -+ *len = CL_DESC_BUF_LEN(desc->ctrl) - PFE_PKT_HEADER_SZ; -+ *ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ; -+ *priv_data = NULL; -+ } -+ -+ } else { -+ *len = CL_DESC_BUF_LEN(desc->ctrl); -+ *ofst = pfe_pkt_headroom; -+ } -+ -+ desc->data = NULL; // Needed so we don't free a buffer/page twice on module_exit -+ smp_wmb(); -+ -+ desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | CL_DESC_OWN; -+ inc_cl_idx(queue->read_idx); -+ } -+ -+ //spin_unlock_irqrestore(&client->rx_lock, flags); -+ return pkt; -+} -+ -+static inline void hif_hdr_write(struct hif_hdr *pkt_hdr, unsigned int client_id, unsigned int qno, u32 client_ctrl) -+{ -+ /* Optimize the write since the destinaton may be non-cacheable */ -+ if (!((unsigned long)pkt_hdr & 0x3)) { -+ ((u32 *)pkt_hdr)[0] = (client_ctrl << 16) | (qno << 8) | client_id; -+ } else { -+ ((u16 *)pkt_hdr)[0] = (qno << 8) | (client_id & 0xFF); -+ ((u16 *)pkt_hdr)[1] = (client_ctrl & 0xFFFF); -+ } -+} -+ -+/*This function puts the given packet in the specific client queue */ -+void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data, unsigned int len, u32 client_ctrl, unsigned int flags, void *client_data) -+{ -+ struct hif_client_tx_queue *queue = &client->tx_q[qno]; -+ struct tx_queue_desc *desc = queue->base + queue->write_idx; -+ -+ //printk(KERN_INFO "%s\n",__func__); -+ -+ /* First buffer */ -+ if (flags & HIF_FIRST_BUFFER) -+ { -+ data -= sizeof(struct hif_hdr); -+ len += sizeof(struct hif_hdr); -+ -+ hif_hdr_write(data, client->id, qno, client_ctrl); -+ } -+ -+ desc->data = client_data; -+ desc->ctrl = CL_DESC_OWN | CL_DESC_FLAGS(flags); -+ -+ __hif_xmit_pkt(&pfe->hif, client->id, qno, data, len, flags); -+ -+ inc_cl_idx(queue->write_idx); -+ queue->tx_pending++; -+ queue->jiffies_last_packet = jiffies; -+ -+} -+ -+/*This function puts the given packet in the specific client queue */ -+int hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data, unsigned int len, u32 client_ctrl, void *client_data) -+{ -+ struct hif_client_tx_queue *queue = &client->tx_q[qno]; -+ struct tx_queue_desc *desc = queue->base + queue->write_idx; -+ -+ //printk(KERN_INFO "%s\n",__func__); -+ -+ if (queue->tx_pending < queue->size) { -+ /*Construct pkt header */ -+ -+ data -= sizeof(struct hif_hdr); -+ len += sizeof(struct hif_hdr); -+ -+ hif_hdr_write(data, client->id, qno, client_ctrl); -+ -+ desc->data = client_data; -+ desc->ctrl = CL_DESC_OWN | CL_DESC_FLAGS(HIF_FIRST_BUFFER | HIF_LAST_BUFFER | HIF_DATA_VALID); -+ -+ if (hif_xmit_pkt(&pfe->hif, client->id, qno, data, len)) -+ return 1; -+ -+ inc_cl_idx(queue->write_idx); -+ queue->tx_pending++; -+ queue->jiffies_last_packet = jiffies; -+ -+ return 0; -+ } -+ -+ dbg_print_info("%s Tx client %d qno %d is full\n",__func__, client->id, qno); -+ return 1; -+} -+ -+void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno, unsigned int *flags, int count) -+{ -+ struct hif_client_tx_queue *queue = &client->tx_q[qno]; -+ struct tx_queue_desc *desc = queue->base + queue->read_idx; -+ -+ dbg_print_info("%s: qno : %d rd_indx: %d pending:%d\n",__func__, qno, queue->read_idx, queue->tx_pending); -+ -+ if (!queue->tx_pending ) -+ return NULL; -+ -+ if (queue->nocpy_flag && !queue->done_tmu_tx_pkts) { -+ u32 tmu_tx_pkts = be32_to_cpu(pe_dmem_read(TMU0_ID + client->id, virt_to_tmu_dmem(&tx_trans[qno]), 4)); -+ -+ if (queue->prev_tmu_tx_pkts > tmu_tx_pkts) -+ queue->done_tmu_tx_pkts = UINT_MAX - queue->prev_tmu_tx_pkts + tmu_tx_pkts; -+ else -+ queue->done_tmu_tx_pkts = tmu_tx_pkts - queue->prev_tmu_tx_pkts; -+ -+ queue->prev_tmu_tx_pkts = tmu_tx_pkts; -+ -+ if (!queue->done_tmu_tx_pkts) { -+ return NULL; -+ } -+ } -+ -+ if (desc->ctrl & CL_DESC_OWN) { -+ hif_tx_done_process(&pfe->hif, count); -+ -+ //Check again, if packets done in tx queue. -+ if (desc->ctrl & CL_DESC_OWN) -+ return NULL; -+ } -+ -+ inc_cl_idx(queue->read_idx); -+ queue->tx_pending--; -+ -+ *flags = CL_DESC_GET_FLAGS(desc->ctrl); -+ -+ if (queue->done_tmu_tx_pkts && (*flags & HIF_LAST_BUFFER)) -+ queue->done_tmu_tx_pkts--; -+ -+ -+ return desc->data; -+} -+ -+//FIXME: TMU queues length mapping needs to be declared in shared PFE/PFE_CTRL header -+static void hif_lib_tmu_credit_init(struct pfe *pfe) -+{ -+ int i, q; -+ -+ for (i = 0; i < NUM_GEMAC_SUPPORT; i++) -+ for (q = 0; q < emac_txq_cnt; q++) { -+ pfe->tmu_credit.tx_credit_max[i][q] = (q == 0) ? DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH; -+ pfe->tmu_credit.tx_credit[i][q] = pfe->tmu_credit.tx_credit_max[i][q]; -+ } -+} -+/** __hif_lib_update_credit -+ * -+ * @param[in] client hif client context -+ * @param[in] queue queue number in match with TMU -+ */ -+void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue) -+{ -+ unsigned int tmu_tx_packets, tmp; -+ -+ if (tx_qos) { -+ tmu_tx_packets = be32_to_cpu(pe_dmem_read(TMU0_ID + client->id, virt_to_tmu_dmem(&tx_trans[queue]), 4)); -+ -+ // tx_packets counter overflowed -+ if (tmu_tx_packets > pfe->tmu_credit.tx_packets[client->id][queue]) { -+ tmp = UINT_MAX - tmu_tx_packets + pfe->tmu_credit.tx_packets[client->id][queue]; -+ pfe->tmu_credit.tx_credit[client->id][queue] = pfe->tmu_credit.tx_credit_max[client->id][queue] - tmp; -+ } -+ // TMU tx <= pfe_eth tx, normal case or both OF since last time -+ else -+ pfe->tmu_credit.tx_credit[client->id][queue] = pfe->tmu_credit.tx_credit_max[client->id][queue] - (pfe->tmu_credit.tx_packets[client->id][queue] - tmu_tx_packets); -+ } -+} -+ -+/** hif_lib_update_credit -+ * -+ * @param[in] client hif client context -+ * @param[in] queue queue number in match with TMU -+ */ -+void hif_lib_update_credit(struct hif_client_s *client, unsigned int queue) -+{ -+ spin_lock_bh(&pfe->hif.tx_lock); -+ __hif_lib_update_credit(client, queue); -+ spin_unlock_bh(&pfe->hif.tx_lock); -+} -+ -+int pfe_hif_lib_init(struct pfe *pfe) -+{ -+ int rc; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ if (lro_mode) { -+ page_mode = 1; -+ pfe_pkt_size = min(PAGE_SIZE, MAX_PFE_PKT_SIZE); -+ pfe_pkt_headroom = 0; -+ } else { -+ page_mode = 0; -+ pfe_pkt_size = PFE_PKT_SIZE; -+ pfe_pkt_headroom = PFE_PKT_HEADROOM; -+ } -+ -+ if (tx_qos) -+ emac_txq_cnt = EMAC_TXQ_CNT / 2; -+ else -+ emac_txq_cnt = EMAC_TXQ_CNT; -+ -+ hif_lib_tmu_credit_init(pfe); -+ pfe->hif.shm = &ghif_shm; -+ rc = pfe_hif_shm_init(pfe->hif.shm); -+ -+ return rc; -+} -+ -+ -+void pfe_hif_lib_exit(struct pfe *pfe) -+{ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ pfe_hif_shm_clean(pfe->hif.shm); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.h -@@ -0,0 +1,219 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _PFE_HIF_LIB_H_ -+#define _PFE_HIF_LIB_H_ -+ -+#include "pfe_hif.h" -+ -+#ifdef HIF_LIB_DEBUG -+#define dbg_print_info( fmt, args...) \ -+ printk(KERN_INFO fmt, ##args) -+#else -+#define dbg_print_info( fmt, args...) -+#endif -+ -+#define HIF_CL_REQ_TIMEOUT 10 -+ -+#if defined(CONFIG_COMCERTO_ZONE_DMA_NCNB) -+#define GFP_DMA_PFE (GFP_DMA_NCNB | __GFP_NOWARN) -+#else -+#define GFP_DMA_PFE 0 -+#endif -+ -+enum { -+ REQUEST_CL_REGISTER = 0, -+ REQUEST_CL_UNREGISTER, -+ HIF_REQUEST_MAX -+}; -+ -+enum { -+ EVENT_HIGH_RX_WM = 0, /* Event to indicate that client rx queue is reached water mark level */ -+ EVENT_RX_PKT_IND, /* Event to indicate that, packet recieved for client */ -+ EVENT_TXDONE_IND, /* Event to indicate that, packet tx done for client */ -+ HIF_EVENT_MAX -+}; -+ -+/*structure to store client queue info */ -+ -+/*structure to store client queue info */ -+struct hif_client_rx_queue { -+ struct rx_queue_desc *base; -+ u32 size; -+ u32 read_idx; -+ u32 write_idx; -+}; -+ -+struct hif_client_tx_queue { -+ struct tx_queue_desc *base; -+ u32 size; -+ u32 read_idx; -+ u32 write_idx; -+ u32 tx_pending; -+ unsigned long jiffies_last_packet; -+ u32 nocpy_flag; -+ u32 prev_tmu_tx_pkts; -+ u32 done_tmu_tx_pkts; -+ u32 cur_tso_hdr_p; -+ int tso_buf_cnt; -+}; -+ -+struct hif_client_s -+{ -+ int id; -+ int tx_qn; -+ int rx_qn; -+ void *rx_qbase; -+ void *tx_qbase; -+ /* FIXME tx/rx_qsize fields can be removed after per queue depth is supported*/ -+ int tx_qsize; -+ int rx_qsize; -+ int cpu_id; -+ -+// spinlock_t rx_lock; -+ struct hif_client_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX]; -+ struct hif_client_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX]; -+ int (*event_handler)(void *priv, int event, int data); -+ unsigned long queue_mask[HIF_EVENT_MAX]; -+ struct pfe *pfe; -+ void *priv; -+}; -+ -+ -+/* Client specific shared memory -+ * It contains number of Rx/Tx queues, base addresses and queue sizes */ -+struct hif_client_shm { -+ u32 ctrl; /*0-7: number of Rx queues, 8-15: number of tx queues */ -+ unsigned long rx_qbase; /*Rx queue base address */ -+ u32 rx_qsize; /*each Rx queue size, all Rx queues are of same size */ -+ unsigned long tx_qbase; /* Tx queue base address */ -+ u32 tx_qsize; /*each Tx queue size, all Tx queues are of same size */ -+}; -+ -+/*Client shared memory ctrl bit description */ -+#define CLIENT_CTRL_RX_Q_CNT_OFST 0 -+#define CLIENT_CTRL_TX_Q_CNT_OFST 8 -+#define CLIENT_CTRL_RX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_RX_Q_CNT_OFST) & 0xFF) -+#define CLIENT_CTRL_TX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_TX_Q_CNT_OFST) & 0xFF) -+ -+ -+ -+/*Shared memory used to communicate between HIF driver and host/client drivers -+ * Before starting the hif driver rx_buf_pool ans rx_buf_pool_cnt should be -+ * initialized with host buffers and buffers count in the pool. -+ * rx_buf_pool_cnt should be >= HIF_RX_DESC_NT. -+ * -+ */ -+struct hif_shm { -+ u32 rx_buf_pool_cnt; /*Number of rx buffers available*/ -+ void *rx_buf_pool[HIF_RX_DESC_NT];/*Rx buffers required to initialize HIF rx descriptors */ -+ unsigned long gClient_status[2]; /*Global client status bit mask */ -+ u32 hif_qfull; /*TODO Client-id that caused for the TMU3 queue stop */ -+ u32 hif_qresume; /*TODO */ -+ struct hif_client_shm client[HIF_CLIENTS_MAX]; /* Client specific shared memory */ -+}; -+ -+ -+#define CL_DESC_OWN (1 << 31) /* This sets owner ship to HIF driver */ -+#define CL_DESC_LAST (1 << 30) /* This indicates last packet for multi buffers handling */ -+#define CL_DESC_FIRST (1 << 29) /* This indicates first packet for multi buffers handling */ -+#define CL_DESC_BUF_LEN(x) ((x) & 0xFFFF) -+#define CL_DESC_FLAGS(x) (((x) & 0xF) << 16) -+#define CL_DESC_GET_FLAGS(x) (((x) >> 16) & 0xF) -+ -+struct rx_queue_desc { -+ void *data; -+ u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/ -+ u32 client_ctrl; -+}; -+ -+struct tx_queue_desc { -+ void *data; -+ u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/ -+}; -+ -+/* HIF Rx is not working properly for 2-byte aligned buffers and -+ * ip_header should be 4byte aligned for better iperformance. -+ * "ip_header = 64 + 6(hif_header) + 14 (MAC Header)" will be 4byte aligned. -+ */ -+#define PFE_PKT_HEADER_SZ sizeof(struct hif_hdr) -+#define PFE_BUF_SIZE 2048 /* must be big enough for headroom, pkt size and skb shared info */ -+#define PFE_PKT_HEADROOM 128 -+#define SKB_SHARED_INFO_SIZE 256 /* At least sizeof(struct skb_shared_info) bytes */ -+ -+//#define PFE_PKT_SIZE 1544 /* maximum ethernet packet size */ -+#define PFE_PKT_SIZE (PFE_BUF_SIZE - PFE_PKT_HEADROOM - SKB_SHARED_INFO_SIZE) /* maximum ethernet packet size after reassembly offload*/ -+#define MAX_L2_HDR_SIZE 14 /* Not correct for VLAN/PPPoE */ -+#define MAX_L3_HDR_SIZE 20 /* Not correct for IPv6 */ -+#define MAX_L4_HDR_SIZE 60 /* TCP with maximum options */ -+#define MAX_HDR_SIZE (MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE + MAX_L4_HDR_SIZE) -+#define MAX_WIFI_HDR_SIZE (MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE + 6) -+#define MAX_PFE_PKT_SIZE 16380UL /* Used in page mode to clamp packet size to the maximum supported by the hif hw interface (<16KiB) */ -+ -+extern unsigned int pfe_pkt_size; -+extern unsigned int pfe_pkt_headroom; -+extern unsigned int page_mode; -+extern unsigned int lro_mode; -+extern unsigned int tx_qos; -+extern unsigned int emac_txq_cnt; -+ -+int pfe_hif_lib_init(struct pfe *pfe); -+void pfe_hif_lib_exit(struct pfe *pfe); -+int hif_lib_client_register(struct hif_client_s *client); -+int hif_lib_client_unregister(struct hif_client_s *client); -+void __hif_lib_xmit_tso_hdr(struct hif_client_s *client, unsigned int qno, u32 client_ctrl, unsigned int ip_off, unsigned int ip_id, unsigned int ip_len, unsigned int tcp_off, unsigned int tcp_seq); -+void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data, unsigned int len, u32 client_ctrl, unsigned int flags, void *client_data); -+int hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data, unsigned int len, u32 client_ctrl, void *client_data); -+void hif_lib_indicate_client(int cl_id, int event, int data); -+int hif_lib_event_handler_start( struct hif_client_s *client, int event, int data ); -+int hif_lib_tmu_queue_start( struct hif_client_s *client, int qno ); -+int hif_lib_tmu_queue_stop( struct hif_client_s *client, int qno ); -+void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno, unsigned int *flags, int count); -+void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int *ofst, unsigned int *rx_ctrl, unsigned int *desc_ctrl, void **priv_data); -+void hif_lib_update_credit(struct hif_client_s *client, unsigned int qno); -+void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue); -+void hif_lib_set_rx_cpu_affinity(struct hif_client_s *client, int cpu_id); -+void hif_lib_set_tx_queue_nocpy(struct hif_client_s *client, int qno, int enable); -+static inline int hif_lib_tx_avail(struct hif_client_s *client, unsigned int qno) -+{ -+ struct hif_client_tx_queue *queue = &client->tx_q[qno]; -+ -+ return (queue->size - queue->tx_pending); -+} -+ -+static inline int hif_lib_get_tx_wrIndex(struct hif_client_s *client, unsigned int qno) -+{ -+ struct hif_client_tx_queue *queue = &client->tx_q[qno]; -+ -+ return queue->write_idx; -+} -+ -+ -+static inline int hif_lib_tx_pending(struct hif_client_s *client, unsigned int qno) -+{ -+ struct hif_client_tx_queue *queue = &client->tx_q[qno]; -+ -+ return queue->tx_pending; -+} -+ -+#define hif_lib_tx_credit_avail(pfe, id, qno) pfe->tmu_credit.tx_credit[id][qno] -+#define hif_lib_tx_credit_max(pfe, id, qno) pfe->tmu_credit.tx_credit_max[id][qno] -+#define hif_lib_tx_credit_use(pfe, id, qno, credit) do {if (tx_qos) {pfe->tmu_credit.tx_credit[id][qno]-= credit; pfe->tmu_credit.tx_packets[id][qno]+=credit;}} while (0) -+ -+#endif /* _PFE_HIF_LIB_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hw.c -@@ -0,0 +1,188 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include "pfe_mod.h" -+#include "pfe_hw.h" -+ -+/* Functions to handle most of pfe hw register initialization */ -+ -+int pfe_hw_init(struct pfe *pfe, int resume) -+{ -+ CLASS_CFG class_cfg = { -+ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO, -+ .route_table_baseaddr = pfe->ddr_phys_baseaddr + ROUTE_TABLE_BASEADDR, -+ .route_table_hash_bits = ROUTE_TABLE_HASH_BITS, -+ }; -+ -+ TMU_CFG tmu_cfg = { -+ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO, -+ .llm_base_addr = pfe->ddr_phys_baseaddr + TMU_LLM_BASEADDR, -+ .llm_queue_len = TMU_LLM_QUEUE_LEN, -+ }; -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+ UTIL_CFG util_cfg = { -+ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO, -+ }; -+#endif -+ -+ BMU_CFG bmu1_cfg = { -+ .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR + BMU1_LMEM_BASEADDR), -+ .count = BMU1_BUF_COUNT, -+ .size = BMU1_BUF_SIZE, -+ }; -+ -+ BMU_CFG bmu2_cfg = { -+ .baseaddr = DDR_PHYS_TO_PFE(pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR), -+ .count = BMU2_BUF_COUNT, -+ .size = BMU2_BUF_SIZE, -+ }; -+ -+ GPI_CFG egpi1_cfg = { -+ .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT, -+ .tmlf_txthres = EGPI1_TMLF_TXTHRES, -+ .aseq_len = EGPI1_ASEQ_LEN, -+ }; -+ -+ GPI_CFG egpi2_cfg = { -+ .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT, -+ .tmlf_txthres = EGPI2_TMLF_TXTHRES, -+ .aseq_len = EGPI2_ASEQ_LEN, -+ }; -+ -+#if defined(CONFIG_PLATFORM_C2000) -+ GPI_CFG egpi3_cfg = { -+ .lmem_rtry_cnt = EGPI3_LMEM_RTRY_CNT, -+ .tmlf_txthres = EGPI3_TMLF_TXTHRES, -+ .aseq_len = EGPI3_ASEQ_LEN, -+ }; -+#endif -+ -+ GPI_CFG hgpi_cfg = { -+ .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT, -+ .tmlf_txthres = HGPI_TMLF_TXTHRES, -+ .aseq_len = HGPI_ASEQ_LEN, -+ }; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+#if defined(CONFIG_PLATFORM_LS1012A) && !defined(LS1012A_PFE_RESET_WA) -+ /* LS1012A needs this to make PE work correctly */ -+ writel(0x3, CLASS_PE_SYS_CLK_RATIO); -+ writel(0x3, TMU_PE_SYS_CLK_RATIO); -+ writel(0x3, UTIL_PE_SYS_CLK_RATIO); -+ udelay(10); -+#endif -+ -+ printk(KERN_INFO "CLASS version: %x\n", readl(CLASS_VERSION)); -+ printk(KERN_INFO "TMU version: %x\n", readl(TMU_VERSION)); -+ -+ printk(KERN_INFO "BMU1 version: %x\n", readl(BMU1_BASE_ADDR + BMU_VERSION)); -+ printk(KERN_INFO "BMU2 version: %x\n", readl(BMU2_BASE_ADDR + BMU_VERSION)); -+#if defined(CONFIG_PLATFORM_C2000) -+ printk(KERN_INFO "EMAC1 network cfg: %x\n", readl(EMAC1_BASE_ADDR + EMAC_NETWORK_CONFIG)); -+ printk(KERN_INFO "EMAC2 network cfg: %x\n", readl(EMAC2_BASE_ADDR + EMAC_NETWORK_CONFIG)); -+#if !defined(CONFIG_PLATFORM_PCI) -+ printk(KERN_INFO "EMAC3 network cfg: %x\n", readl(EMAC3_BASE_ADDR + EMAC_NETWORK_CONFIG)); -+#endif -+#else -+ //TODO print MTIP config -+#endif -+ -+ printk(KERN_INFO "EGPI1 version: %x\n", readl(EGPI1_BASE_ADDR + GPI_VERSION)); -+ printk(KERN_INFO "EGPI2 version: %x\n", readl(EGPI2_BASE_ADDR + GPI_VERSION)); -+#if !defined(CONFIG_PLATFORM_PCI) && !defined(CONFIG_PLATFORM_LS1012A) -+ printk(KERN_INFO "EGPI3 version: %x\n", readl(EGPI3_BASE_ADDR + GPI_VERSION)); -+#endif -+ printk(KERN_INFO "HGPI version: %x\n", readl(HGPI_BASE_ADDR + GPI_VERSION)); -+ -+#if !defined(CONFIG_PLATFORM_PCI) -+ printk(KERN_INFO "GPT version: %x\n", readl(CBUS_GPT_VERSION)); -+#endif -+ -+ printk(KERN_INFO "HIF version: %x\n", readl(HIF_VERSION)); -+ printk(KERN_INFO "HIF NOPCY version: %x\n", readl(HIF_NOCPY_VERSION)); -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+ printk(KERN_INFO "UTIL version: %x\n", readl(UTIL_VERSION)); -+#endif -+ while(!(readl(TMU_CTRL) & ECC_MEM_INIT_DONE)) ; -+ -+ hif_rx_disable(); -+ hif_tx_disable(); -+ -+ bmu_init(BMU1_BASE_ADDR, &bmu1_cfg); -+ -+ printk(KERN_INFO "bmu_init(1) done\n"); -+ -+ bmu_init(BMU2_BASE_ADDR, &bmu2_cfg); -+ -+ printk(KERN_INFO "bmu_init(2) done\n"); -+ -+ class_cfg.resume = resume ? 1 : 0; -+ -+ class_init(&class_cfg); -+ -+ printk(KERN_INFO "class_init() done\n"); -+ -+ tmu_init(&tmu_cfg); -+ -+ printk(KERN_INFO "tmu_init() done\n"); -+#if !defined(CONFIG_UTIL_DISABLED) -+ util_init(&util_cfg); -+ -+ printk(KERN_INFO "util_init() done\n"); -+#endif -+ gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg); -+ -+ printk(KERN_INFO "gpi_init(1) done\n"); -+ -+ gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg); -+ -+ printk(KERN_INFO "gpi_init(2) done\n"); -+#if !defined(CONFIG_PLATFORM_PCI) && !defined(CONFIG_PLATFORM_LS1012A) -+ gpi_init(EGPI3_BASE_ADDR, &egpi3_cfg); -+ -+ printk(KERN_INFO "gpi_init(3) done\n"); -+#endif -+ gpi_init(HGPI_BASE_ADDR, &hgpi_cfg); -+ -+ printk(KERN_INFO "gpi_init(hif) done\n"); -+ -+ bmu_enable(BMU1_BASE_ADDR); -+ -+ printk(KERN_INFO "bmu_enable(1) done\n"); -+ -+ bmu_enable(BMU2_BASE_ADDR); -+ -+ printk(KERN_INFO "bmu_enable(2) done\n"); -+ -+ return 0; -+} -+ -+void pfe_hw_exit(struct pfe *pfe) -+{ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ bmu_disable(BMU1_BASE_ADDR); -+ bmu_reset(BMU1_BASE_ADDR); -+ -+ bmu_disable(BMU2_BASE_ADDR); -+ bmu_reset(BMU2_BASE_ADDR); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hw.h -@@ -0,0 +1,32 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _PFE_HW_H_ -+#define _PFE_HW_H_ -+ -+#if !defined(CONFIG_PLATFORM_PCI) -+#define PE_SYS_CLK_RATIO 1 /* SYS/AXI = 250MHz, HFE = 500MHz */ -+#else -+#define PE_SYS_CLK_RATIO 0 /* SYS = 40MHz, HFE = 40MHz */ -+#endif -+ -+int pfe_hw_init(struct pfe *pfe, int resume); -+void pfe_hw_exit(struct pfe *pfe); -+ -+#endif /* _PFE_HW_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c -@@ -0,0 +1,341 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+ -+#include "pfe_mod.h" -+ -+struct comcerto_pfe_platform_data pfe_platform_data; -+ -+ -+ -+static int pfe_get_gemac_if_proprties(struct device_node *parent, int port, int if_cnt, -+ struct comcerto_pfe_platform_data *pdata) -+{ -+ struct device_node *gem = NULL, *phy = NULL; -+ int size; -+ int ii = 0, phy_id = 0; -+ const u32 *addr; -+ const void *mac_addr; -+ -+ for (ii = 0; ii < if_cnt; ii++) { -+ gem = of_get_next_child(parent, gem); -+ if (!gem) -+ goto err; -+ addr = of_get_property(gem, "reg", &size); -+ if (addr && (be32_to_cpup(addr) == port)) -+ break; -+ } -+ -+ if (ii >= if_cnt) { -+ printk(KERN_ERR "%s:%d Failed to find interface = %d\n", __func__, __LINE__, if_cnt); -+ goto err; -+ } -+ -+ pdata->comcerto_eth_pdata[port].gem_id = port; -+ -+ mac_addr = of_get_mac_address(gem); -+ -+ if (mac_addr) { -+ memcpy(pdata->comcerto_eth_pdata[port].mac_addr, mac_addr, ETH_ALEN); -+ } -+ -+ if ((pdata->comcerto_eth_pdata[port].mii_config = of_get_phy_mode(gem)) < 0) -+ printk(KERN_ERR "%s:%d Incorrect Phy mode....\n", __func__, __LINE__); -+ -+ -+ addr = of_get_property(gem, "fsl,gemac-bus-id", &size); -+ if (!addr) -+ printk(KERN_ERR "%s:%d Invalid gemac-bus-id....\n", __func__, __LINE__); -+ else -+ pdata->comcerto_eth_pdata[port].bus_id = be32_to_cpup(addr); -+ -+ addr = of_get_property(gem, "fsl,gemac-phy-id", &size); -+ if (!addr) -+ printk(KERN_ERR "%s:%d Invalid gemac-phy-id....\n", __func__, __LINE__); -+ else -+ phy_id = pdata->comcerto_eth_pdata[port].phy_id = be32_to_cpup(addr); -+ -+ addr = of_get_property(gem, "fsl,mdio-mux-val", &size); -+ if (!addr) -+ printk(KERN_ERR "%s: Invalid mdio-mux-val....\n", __func__); -+ else -+ phy_id = pdata->comcerto_eth_pdata[port].mdio_muxval= be32_to_cpup(addr); -+ -+ -+ addr = of_get_property(gem, "fsl,pfe-phy-if-flags", &size); -+ if (!addr) -+ printk(KERN_ERR "%s:%d Invalid pfe-phy-if-flags....\n", __func__, __LINE__); -+ else -+ pdata->comcerto_eth_pdata[port].phy_flags = be32_to_cpup(addr); -+ -+ addr = of_get_property(gem, "fsl,pfe-gemac-mode", &size); -+ if (!addr) -+ printk(KERN_ERR "%s:%d Invalid pfe-gemac-mode....\n", __func__, __LINE__); -+ else -+ pdata->comcerto_eth_pdata[port].gemac_mode = be32_to_cpup(addr); -+ -+ -+ /* If PHY is enabled, read mdio properties */ -+ if (pdata->comcerto_eth_pdata[port].phy_flags & GEMAC_NO_PHY) -+ goto done; -+ -+ phy = of_get_next_child(gem, NULL); -+ -+ addr = of_get_property(phy, "reg", &size); -+ -+ if (!addr) -+ printk(KERN_ERR "%s:%d Invalid phy enable flag....\n", __func__, __LINE__); -+ else -+ pdata->comcerto_mdio_pdata[port].enabled = be32_to_cpup(addr); -+ -+ addr = of_get_property (phy, "fsl,mdio-phy-mask", &size); -+ if (!addr) -+ printk(KERN_ERR "%s:%d Unable to read mdio-phy-mask....\n", __func__, __LINE__); -+ else -+ pdata->comcerto_mdio_pdata[port].phy_mask= be32_to_cpup(addr); -+ pdata->comcerto_mdio_pdata[port].irq[0] = PHY_POLL; -+ -+done: -+ -+ return 0; -+ -+err: -+ return -1; -+} -+/** -+ * pfe_platform_probe - -+ * -+ * -+ */ -+static int pfe_platform_probe(struct platform_device *pdev) -+{ -+ struct resource res; -+ int ii, rc, interface_count = 0, size = 0; -+ const u32 *prop; -+ struct device_node *np; -+ -+ np = pdev->dev.of_node; -+ -+ if (!np) { -+ printk(KERN_ERR "Invalid device node\n"); -+ return -EINVAL; -+ } -+ -+ pfe = kzalloc(sizeof(struct pfe), GFP_KERNEL); -+ if (!pfe) { -+ rc = -ENOMEM; -+ goto err_alloc; -+ } -+ -+ platform_set_drvdata(pdev, pfe); -+ -+ dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); -+ -+ if (of_address_to_resource(np, 2, &res)) -+ { -+ rc = -ENOMEM; -+ printk(KERN_ERR "failed to get ddr resource\n"); -+ goto err_ddr; -+ } -+ -+ -+ pfe->ddr_phys_baseaddr = res.start; -+ pfe->ddr_size = resource_size(&res); -+ -+ //pfe->ddr_baseaddr = ioremap(res.start, resource_size(&res)); -+ pfe->ddr_baseaddr = phys_to_virt(res.start); -+ if (!pfe->ddr_baseaddr) { -+ printk(KERN_ERR "ioremap() ddr failed\n"); -+ rc = -ENOMEM; -+ goto err_ddr; -+ } -+ -+ /*printk("%s:%d : DDR Res : Phy addr:len = %x:%x Mapped addr : %x\n", __func__, __LINE__, -+ pfe->ddr_phys_baseaddr, pfe->ddr_size, pfe->ddr_baseaddr);*/ -+ -+ pfe->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,"fsl,pfe-scfg"); -+ if (IS_ERR(pfe->scfg)) { -+ dev_err(&pdev->dev, "No syscfg phandle specified\n"); -+ return PTR_ERR(pfe->scfg); -+ } -+ /*printk("%s scfg %p\n",__func__,pfe->scfg);*/ -+ -+ -+#if 1 -+ if (!(pfe->cbus_baseaddr = of_iomap(np, 1))) -+ { -+ rc = -ENOMEM; -+ printk(KERN_ERR "failed to get axi resource\n"); -+ goto err_axi; -+ } -+ -+ /*printk("%s:%d : AXI Mapped addr : %lx\n", __func__, __LINE__, pfe->cbus_baseaddr); -+ printk("%s:%d : AXI Mapped addr : phys %lx\n", __func__, __LINE__, virt_to_phys(pfe->cbus_baseaddr));*/ -+#else -+ -+ if (of_address_to_resource(np, 1, &res)) -+ { -+ rc = -ENOMEM; -+ printk(KERN_ERR "failed to get AXI resource\n"); -+ goto err_iram; -+ } -+ pfe->cbus_baseaddr = ioremap(res.start, resource_size(&res)); -+ if (!pfe->cbus_baseaddr) { -+ printk(KERN_INFO "ioremap() AXI failed %lx %x\n", res.start, resource_size(&res)); -+ rc = -ENOMEM; -+ goto err_iram; -+ } -+ printk("%s:%d : AXI Mapped addr : %x PHY addr = %x\n", __func__, __LINE__, pfe->cbus_baseaddr, res.start); -+#endif -+ -+ pfe->hif_irq = platform_get_irq(pdev, 0); -+ if (pfe->hif_irq < 0) { -+ printk(KERN_ERR "platform_get_irq_byname(hif) failed\n"); -+ rc = pfe->hif_irq; -+ goto err_hif_irq; -+ } -+ /*printk("hif_irq: %d \n", pfe->hif_irq);*/ -+ -+ /* Read interface count */ -+ prop = of_get_property(np, "fsl,pfe-num-interfaces", &size); -+ if (!prop) { -+ printk(KERN_ERR "Failed to read number of interfaces\n"); -+ rc = -ENXIO; -+ goto err_prop; -+ } -+ -+ interface_count = be32_to_cpup(prop); -+ /*printk(KERN_INFO "%s:%d Number of interfaces : %d\n", __func__, __LINE__, interface_count);*/ -+ if (interface_count <= 0) { -+ printk(KERN_ERR "No ethernet interface count : %d\n", interface_count); -+ rc = -ENXIO; -+ goto err_prop; -+ } -+ -+ for (ii = 0; ii < interface_count; ii++) { -+ pfe_get_gemac_if_proprties(np, ii, interface_count, &pfe_platform_data); -+ } -+ -+ -+ pfe->dev = &pdev->dev; -+ -+ pfe->dev->platform_data = &pfe_platform_data; -+ -+ //FIXME get the correct clock from dts -+ pfe->ctrl.sys_clk = 250000; // save sys_clk value as KHz -+ -+ rc = pfe_probe(pfe); -+ if (rc < 0) -+ goto err_probe; -+ -+ return 0; -+ -+err_probe: -+err_prop: -+ /*TODO complet the code */ -+err_hif_irq: -+ iounmap(pfe->cbus_baseaddr); -+ -+err_axi: -+ iounmap(pfe->ddr_baseaddr); -+ -+err_ddr: -+ platform_set_drvdata(pdev, NULL); -+ -+ kfree(pfe); -+ -+err_alloc: -+ return rc; -+} -+ -+ -+/** -+ * pfe_platform_remove - -+ * -+ * -+ */ -+static int pfe_platform_remove(struct platform_device *pdev) -+{ -+ struct pfe *pfe = platform_get_drvdata(pdev); -+ int rc; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ rc = pfe_remove(pfe); -+ -+ iounmap(pfe->cbus_baseaddr); -+ iounmap(pfe->ddr_baseaddr); -+ -+ platform_set_drvdata(pdev, NULL); -+ -+ kfree(pfe); -+ -+ return rc; -+} -+ -+static struct of_device_id pfe_match[] = { -+ { -+ .compatible = "fsl,pfe", -+ }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, pfe_match); -+ -+static struct platform_driver pfe_platform_driver = { -+ .probe = pfe_platform_probe, -+ .remove = pfe_platform_remove, -+ .driver = { -+ .name = "pfe", -+ .of_match_table = pfe_match, -+ }, -+}; -+ -+#if 0 -+static int __init pfe_module_init(void) -+{ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ return platform_driver_register(&pfe_platform_driver); -+} -+ -+ -+static void __exit pfe_module_exit(void) -+{ -+ platform_driver_unregister(&pfe_platform_driver); -+ -+ printk(KERN_INFO "%s\n", __func__); -+} -+module_init(pfe_module_init); -+module_exit(pfe_module_exit); -+#endif -+ -+module_platform_driver(pfe_platform_driver); -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("PFE Ethernet driver"); -+MODULE_AUTHOR("NXP DNCPE"); ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_mod.c -@@ -0,0 +1,140 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#include "pfe_mod.h" -+ -+struct pfe *pfe; -+ -+/** -+ * pfe_probe - -+ * -+ * -+ */ -+int pfe_probe(struct pfe *pfe) -+{ -+ int rc; -+ -+ -+ if (DDR_MAX_SIZE > pfe->ddr_size) { -+ printk(KERN_ERR "%s: required DDR memory (%x) above platform ddr memory (%x)\n", __func__, DDR_MAX_SIZE, pfe->ddr_size); -+ rc = -ENOMEM; -+ goto err_hw; -+ } -+ -+ if (((int) (pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR) & (8*SZ_1M - 1)) != 0) { -+ printk(KERN_ERR "%s: BMU2 base address (0x%x) must be aligned on 8MB boundary\n", __func__, (int) pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR); -+ rc = -ENOMEM; -+ goto err_hw; -+ } -+ -+ -+ printk(KERN_INFO "cbus_baseaddr: %lx, ddr_baseaddr: %lx, ddr_phys_baseaddr: %lx, ddr_size: %x\n", -+ (unsigned long)pfe->cbus_baseaddr, (unsigned long)pfe->ddr_baseaddr, -+ pfe->ddr_phys_baseaddr, pfe->ddr_size); -+ -+ pfe_lib_init(pfe->cbus_baseaddr, pfe->ddr_baseaddr, pfe->ddr_phys_baseaddr, pfe->ddr_size); -+ -+ rc = pfe_hw_init(pfe, 0); -+ if (rc < 0) -+ goto err_hw; -+ -+ rc = pfe_hif_lib_init(pfe); -+ if (rc < 0) -+ goto err_hif_lib; -+ -+ rc = pfe_hif_init(pfe); -+ if (rc < 0) -+ goto err_hif; -+ -+ rc = pfe_firmware_init(pfe); -+ if (rc < 0) -+ goto err_firmware; -+ -+ rc = pfe_ctrl_init(pfe); -+ if (rc < 0) -+ goto err_ctrl; -+ -+ rc = pfe_eth_init(pfe); -+ if (rc < 0) -+ goto err_eth; -+ -+ rc = pfe_sysfs_init(pfe); -+ if(rc < 0) -+ goto err_sysfs; -+ -+ rc = pfe_debugfs_init(pfe); -+ if (rc < 0) -+ goto err_debugfs; -+ -+ return 0; -+ -+err_debugfs: -+ pfe_sysfs_exit(pfe); -+ -+err_sysfs: -+ pfe_eth_exit(pfe); -+ -+err_eth: -+ pfe_ctrl_exit(pfe); -+ -+err_ctrl: -+ pfe_firmware_exit(pfe); -+ -+err_firmware: -+ pfe_hif_exit(pfe); -+ -+err_hif: -+ pfe_hif_lib_exit(pfe); -+ -+err_hif_lib: -+ pfe_hw_exit(pfe); -+ -+err_hw: -+ return rc; -+} -+ -+ -+/** -+ * pfe_remove - -+ * -+ * -+ */ -+int pfe_remove(struct pfe *pfe) -+{ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ pfe_debugfs_exit(pfe); -+ -+ pfe_sysfs_exit(pfe); -+ -+ pfe_eth_exit(pfe); -+ -+ pfe_ctrl_exit(pfe); -+ -+ pfe_firmware_exit(pfe); -+ -+ pfe_hif_exit(pfe); -+ -+ pfe_hif_lib_exit(pfe); -+ -+ pfe_hw_exit(pfe); -+ -+ return 0; -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_mod.h -@@ -0,0 +1,163 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _PFE_MOD_H_ -+#define _PFE_MOD_H_ -+ -+#include -+#include -+ -+struct pfe; -+ -+#include "config.h" -+#include "pfe_hw.h" -+#include "pfe_firmware.h" -+#include "pfe_ctrl.h" -+#include "pfe_hif.h" -+#include "pfe_hif_lib.h" -+#include "pfe_eth.h" -+#include "pfe_sysfs.h" -+#include "pfe_perfmon.h" -+#include "pfe_debugfs.h" -+ -+struct pfe_tmu_credit { -+ /* Number of allowed TX packet in-flight, matches TMU queue size */ -+ unsigned int tx_credit[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT]; -+ unsigned int tx_credit_max[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT]; -+ unsigned int tx_packets[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT]; -+}; -+ -+struct pfe { -+ struct regmap *scfg; -+ unsigned long ddr_phys_baseaddr; -+ void *ddr_baseaddr; -+ unsigned int ddr_size; -+ void *cbus_baseaddr; -+ void *apb_baseaddr; -+ unsigned long iram_phys_baseaddr; -+ void *iram_baseaddr; -+ unsigned long ipsec_phys_baseaddr; -+ void *ipsec_baseaddr; -+ int hif_irq; -+ int hif_client_irq; -+ struct device *dev; -+ struct dentry *dentry; -+ struct pfe_ctrl ctrl; -+ struct pfe_hif hif; -+ struct pfe_eth eth; -+ struct hif_client_s *hif_client[HIF_CLIENTS_MAX]; -+#if defined(CFG_DIAGS) -+ struct pfe_diags diags; -+#endif -+ struct pfe_tmu_credit tmu_credit; -+ struct pfe_cpumon cpumon; -+ struct pfe_memmon memmon; -+ int wake; -+ struct clk * hfe_clock; -+}; -+ -+extern struct pfe *pfe; -+ -+int pfe_probe(struct pfe *pfe); -+int pfe_remove(struct pfe *pfe); -+ -+#ifndef SZ_1K -+#define SZ_1K 1024 -+#endif -+ -+#ifndef SZ_1M -+#define SZ_1M (1024 * 1024) -+#endif -+ -+/* DDR Mapping */ -+#if !defined(CONFIG_PLATFORM_PCI) -+#define ROUTE_TABLE_BASEADDR 0 -+#define ROUTE_TABLE_HASH_BITS 15 /**< 32K entries */ -+#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE) -+#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE) -+#define BMU2_BUF_COUNT (4096 - 256) /**< This is to get a total DDR size of 12MiB */ -+#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT) -+#define UTIL_CODE_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE) -+#define UTIL_CODE_SIZE (128 * SZ_1K) -+#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE) -+#define UTIL_DDR_DATA_SIZE (64 * SZ_1K) -+#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE) -+#define CLASS_DDR_DATA_SIZE (32 * SZ_1K) -+#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE) -+#define TMU_DDR_DATA_SIZE (32 * SZ_1K) -+#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE) -+#define TMU_LLM_QUEUE_LEN (8 * 512) /**< Must be power of two and at least 16 * 8 = 128 bytes */ -+#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */ -+ -+#define DDR_MAX_SIZE (TMU_LLM_BASEADDR + TMU_LLM_SIZE) -+ -+#else -+ -+#define UTIL_CODE_BASEADDR 0 -+#if defined(CONFIG_UTIL_DISABLED) -+#define UTIL_CODE_SIZE (0 * SZ_1K) -+#else -+#define UTIL_CODE_SIZE (8 * SZ_1K) -+#endif -+#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE) -+#define UTIL_DDR_DATA_SIZE (0 * SZ_1K) -+#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE) -+#define CLASS_DDR_DATA_SIZE (0 * SZ_1K) -+#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE) -+#define TMU_DDR_DATA_SIZE (0 * SZ_1K) -+#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE) -+#define ROUTE_TABLE_HASH_BITS 5 /**< 32 entries */ -+#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE) -+#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE) -+#define BMU2_BUF_COUNT 16 -+#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT) -+#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE) -+#define TMU_LLM_QUEUE_LEN (16 * 8) /**< Must be power of two and at least 16 * 8 = 128 bytes */ -+#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */ -+#define HIF_DESC_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE) -+#define HIF_RX_DESC_SIZE (16*HIF_RX_DESC_NT) -+#define HIF_TX_DESC_SIZE (16*HIF_TX_DESC_NT) -+#define HIF_DESC_SIZE (HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE) -+#define HIF_RX_PKT_DDR_BASEADDR (HIF_DESC_BASEADDR + HIF_DESC_SIZE) -+#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE) -+#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE) -+#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE) -+#define ROUTE_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE) -+#define ROUTE_SIZE (2 * CLASS_ROUTE_SIZE) -+ -+#define DDR_MAX_SIZE (ROUTE_BASEADDR + ROUTE_SIZE) -+ -+#define PFE_HOST_TO_PCI(addr) (((u32)addr)- ((u32)DDR_BASE_ADDR)) -+#define PFE_PCI_TO_HOST(addr) (((u32)addr)+ ((u32)DDR_BASE_ADDR)) -+#endif -+ -+/* IRAM Mapping */ -+#define IPSEC_IRAM_BASEADDR 0 -+#define IPSEC_IRAM_SIZE 0x2000 -+ -+/* LMEM Mapping */ -+#define BMU1_LMEM_BASEADDR 0 -+#define BMU1_BUF_COUNT 256 -+#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT) -+#define IPSEC_LMEM_BASEADDR (BMU1_LMEM_BASEADDR + BMU1_LMEM_SIZE) -+#define IPSEC_LMEM_SIZE (30 * 1024) -+ -+ -+ -+#endif /* _PFE_MOD_H */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_perfmon.c -@@ -0,0 +1,175 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+/* PFE performance monitoring functions */ -+ -+#include "pfe_ctrl_hal.h" -+#include "pfe_perfmon.h" -+ -+static TIMER_ENTRY cpumon_timer; -+ -+u32 CLASS_DMEM_SH2(cpu_ticks[2]); -+u32 TMU_DMEM_SH2(cpu_ticks[2]); -+#if !defined(CONFIG_UTIL_DISABLED) -+u32 UTIL_DMEM_SH2(cpu_ticks[2]); -+#endif -+ -+#define compute_active_pct(total_ticks, active_ticks) ((active_ticks * 100 + (total_ticks >> 1)) / total_ticks) -+ -+static void cpumon_timer_handler(void) -+{ -+ int id; -+ u32 dmem_addr; -+ u32 ticks[2]; -+ u32 total, active; -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ struct pfe_cpumon *cpumon = &pfe->cpumon; -+ -+ // Process class PE's -+ total = active = 0; -+ dmem_addr = virt_to_class_dmem(&class_cpu_ticks[0]); -+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) -+ { -+ cpumon->cpu_usage_pct[id] = 0; -+ if (pe_sync_stop(ctrl, (1 << id)) < 0) -+ continue; -+ ticks[0] = be32_to_cpu(pe_dmem_read(id, dmem_addr, 4)); -+ ticks[1] = be32_to_cpu(pe_dmem_read(id, dmem_addr + 4, 4)); -+ pe_dmem_write(id, 0, dmem_addr, 4); -+ pe_dmem_write(id, 0, dmem_addr + 4, 4); -+ pe_start(ctrl, (1 << id)); -+ ticks[0] >>= 8; // divide both values by 256, so multiply by 100 won't overflow -+ ticks[1] >>= 8; -+ total += ticks[0]; -+ active += ticks[1]; -+ if (ticks[0] != 0) -+ cpumon->cpu_usage_pct[id] = compute_active_pct(ticks[0], ticks[1]); -+ } -+ if (total != 0) -+ cpumon->class_usage_pct = compute_active_pct(total, active); -+ else -+ cpumon->class_usage_pct = 0; -+ -+ // Process TMU PE's -+ total = active = 0; -+ dmem_addr = virt_to_tmu_dmem(&tmu_cpu_ticks[0]); -+ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) -+ { -+#if defined(CONFIG_PLATFORM_LS1012A) -+ if(id == TMU2_ID) continue; -+#endif -+ cpumon->cpu_usage_pct[id] = 0; -+ if (pe_sync_stop(ctrl, (1 << id)) < 0) -+ continue; -+ ticks[0] = be32_to_cpu(pe_dmem_read(id, dmem_addr, 4)); -+ ticks[1] = be32_to_cpu(pe_dmem_read(id, dmem_addr + 4, 4)); -+ pe_dmem_write(id, 0, dmem_addr, 4); -+ pe_dmem_write(id, 0, dmem_addr + 4, 4); -+ pe_start(ctrl, (1 << id)); -+ ticks[0] >>= 8; // divide both values by 256, so multiply by 100 won't overflow -+ ticks[1] >>= 8; -+ if (ticks[0] != 0) -+ cpumon->cpu_usage_pct[id] = compute_active_pct(ticks[0], ticks[1]); -+ } -+#if !defined(CONFIG_UTIL_DISABLED) -+ // Process Util PE -+ dmem_addr = virt_to_util_dmem(&util_cpu_ticks[0]); -+ cpumon->cpu_usage_pct[UTIL_ID] = 0; -+ if (pe_sync_stop(ctrl, (1 << UTIL_ID)) < 0) -+ return; -+ ticks[0] = be32_to_cpu(pe_dmem_read(UTIL_ID, dmem_addr, 4)); -+ ticks[1] = be32_to_cpu(pe_dmem_read(UTIL_ID, dmem_addr + 4, 4)); -+ pe_dmem_write(UTIL_ID, 0, dmem_addr, 4); -+ pe_dmem_write(UTIL_ID, 0, dmem_addr + 4, 4); -+ pe_start(ctrl, (1 << UTIL_ID)); -+ ticks[0] >>= 8; // divide both values by 256, so multiply by 100 won't overflow -+ ticks[1] >>= 8; -+ if (ticks[0] != 0) -+ cpumon->cpu_usage_pct[UTIL_ID] = compute_active_pct(ticks[0], ticks[1]); -+#endif -+} -+ -+static int pfe_cpumon_init(struct pfe *pfe) -+{ -+ timer_init(&cpumon_timer, cpumon_timer_handler); -+ timer_add(&cpumon_timer, CT_CPUMON_INTERVAL); -+ return 0; -+} -+ -+static void pfe_cpumon_exit(struct pfe *pfe) -+{ -+ timer_del(&cpumon_timer); -+} -+ -+ -+/*********************************************************************************/ -+ -+// Memory monitor functions -+ -+void * pfe_kmalloc(size_t size, int flags) -+{ -+ struct pfe_memmon *memmon = &pfe->memmon; -+ void *ptr; -+ ptr = kmalloc(size, flags); -+ if (ptr) -+ memmon->kernel_memory_allocated += ksize(ptr); -+ return ptr; -+} -+ -+void * pfe_kzalloc(size_t size, int flags) -+{ -+ struct pfe_memmon *memmon = &pfe->memmon; -+ void *ptr; -+ ptr = kzalloc(size, flags); -+ if (ptr) -+ memmon->kernel_memory_allocated += ksize(ptr); -+ return ptr; -+} -+ -+void pfe_kfree(void *ptr) -+{ -+ struct pfe_memmon *memmon = &pfe->memmon; -+ memmon->kernel_memory_allocated -= ksize(ptr); -+ kfree(ptr); -+} -+ -+static int pfe_memmon_init(struct pfe *pfe) -+{ -+ return 0; -+} -+ -+static void pfe_memmon_exit(struct pfe *pfe) -+{ -+} -+ -+/*********************************************************************************/ -+ -+ -+int pfe_perfmon_init(struct pfe *pfe) -+{ -+ pfe_cpumon_init(pfe); -+ pfe_memmon_init(pfe); -+ return 0; -+} -+ -+void pfe_perfmon_exit(struct pfe *pfe) -+{ -+ pfe_cpumon_exit(pfe); -+ pfe_memmon_exit(pfe); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_perfmon.h -@@ -0,0 +1,41 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _PFE_PERFMON_H_ -+#define _PFE_PERFMON_H_ -+ -+#define CT_CPUMON_INTERVAL (1 * TIMER_TICKS_PER_SEC) -+ -+struct pfe_cpumon { -+ u32 cpu_usage_pct[MAX_PE]; -+ u32 class_usage_pct; -+}; -+ -+struct pfe_memmon { -+ u32 kernel_memory_allocated; -+}; -+ -+void * pfe_kmalloc(size_t size, int flags); -+void * pfe_kzalloc(size_t size, int flags); -+void pfe_kfree(void *ptr); -+ -+int pfe_perfmon_init(struct pfe *pfe); -+void pfe_perfmon_exit(struct pfe *pfe); -+ -+#endif /* _PFE_PERFMON_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_platform.c -@@ -0,0 +1,358 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "pfe_mod.h" -+ -+/** -+ * pfe_platform_probe - -+ * -+ * -+ */ -+static int pfe_platform_probe(struct platform_device *pdev) -+{ -+ struct resource *r; -+ int rc; -+ struct clk *clk_axi; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ pfe = kzalloc(sizeof(struct pfe), GFP_KERNEL); -+ if (!pfe) { -+ rc = -ENOMEM; -+ goto err_alloc; -+ } -+ -+ platform_set_drvdata(pdev, pfe); -+ -+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ddr"); -+ if (!r) { -+ printk(KERN_INFO "platform_get_resource_byname(ddr) failed\n"); -+ rc = -ENXIO; -+ goto err_ddr; -+ } -+ -+ pfe->ddr_phys_baseaddr = r->start; -+ pfe->ddr_size = resource_size(r); -+ -+ pfe->ddr_baseaddr = ioremap(r->start, resource_size(r)); -+ if (!pfe->ddr_baseaddr) { -+ printk(KERN_INFO "ioremap() ddr failed\n"); -+ rc = -ENOMEM; -+ goto err_ddr; -+ } -+ -+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "axi"); -+ if (!r) { -+ printk(KERN_INFO "platform_get_resource_byname(axi) failed\n"); -+ rc = -ENXIO; -+ goto err_axi; -+ } -+ -+ pfe->cbus_baseaddr = ioremap(r->start, resource_size(r)); -+ if (!pfe->cbus_baseaddr) { -+ printk(KERN_INFO "ioremap() axi failed\n"); -+ rc = -ENOMEM; -+ goto err_axi; -+ } -+ -+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb"); -+ if (!r) { -+ printk(KERN_INFO "platform_get_resource_byname(apb) failed\n"); -+ rc = -ENXIO; -+ goto err_apb; -+ } -+ -+ pfe->apb_baseaddr = ioremap(r->start, resource_size(r)); -+ if (!pfe->apb_baseaddr) { -+ printk(KERN_INFO "ioremap() apb failed\n"); -+ rc = -ENOMEM; -+ goto err_apb; -+ } -+ -+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iram"); -+ if (!r) { -+ printk(KERN_INFO "platform_get_resource_byname(iram) failed\n"); -+ rc = -ENXIO; -+ goto err_iram; -+ } -+ -+ pfe->iram_phys_baseaddr = r->start; -+ pfe->iram_baseaddr = ioremap(r->start, resource_size(r)); -+ if (!pfe->iram_baseaddr) { -+ printk(KERN_INFO "ioremap() iram failed\n"); -+ rc = -ENOMEM; -+ goto err_iram; -+ } -+ -+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ipsec"); -+ if (!r) { -+ printk(KERN_INFO "platform_get_resource_byname(ipsec) failed\n"); -+ rc = -ENXIO; -+ goto err_ipsec; -+ } -+ -+ pfe->ipsec_phys_baseaddr = r->start; -+ /* Just map only initial 1MB , as its enough to access espah engine -+ */ -+ //pfe->ipsec_baseaddr = ioremap(r->start, resource_size(r)); -+ pfe->ipsec_baseaddr = ioremap(r->start, 1*1024*1024); -+ if (!pfe->ipsec_baseaddr) { -+ printk(KERN_INFO "ioremap() ipsec failed\n"); -+ rc = -ENOMEM; -+ goto err_ipsec; -+ } -+ -+ printk(KERN_INFO "ipsec: baseaddr :%x --- %x\n", (u32)pfe->ipsec_phys_baseaddr, (u32)pfe->ipsec_baseaddr); -+ -+ pfe->hif_irq = platform_get_irq_byname(pdev, "hif"); -+ if (pfe->hif_irq < 0) { -+ printk(KERN_INFO "platform_get_irq_byname(hif) failed\n"); -+ rc = pfe->hif_irq; -+ goto err_hif_irq; -+ } -+ -+#if 0 -+ pfe->hif_client_irq = platform_get_irq_byname(pdev, "hif_client"); -+ if (pfe->hif_client_irq < 0) { -+ printk(KERN_INFO "platform_get_irq_byname(hif_client) failed\n"); -+ rc = pfe->hif_client_irq; -+ goto err_hif_irq; -+ } -+#endif -+ -+ pfe->dev = &pdev->dev; -+ -+ -+ /* Get the system clock */ -+ clk_axi = clk_get(NULL,"axi"); -+ if (IS_ERR(clk_axi)) { -+ printk(KERN_INFO "clk_get call failed\n"); -+ rc = -ENXIO; -+ goto err_clk; -+ } -+ -+ /* HFE core clock */ -+ pfe->hfe_clock = clk_get(NULL, "hfe_core"); -+ if (IS_ERR(pfe->hfe_clock)) { -+ printk(KERN_INFO "clk_get call failed\n"); -+ rc = -ENXIO; -+ goto err_hfe_clock; -+ } -+ -+ clk_disable(pfe->hfe_clock); -+ c2000_block_reset(COMPONENT_PFE_SYS, 1); -+ mdelay(1); -+ c2000_block_reset(COMPONENT_PFE_SYS, 0); -+ clk_enable(pfe->hfe_clock); -+ -+ pfe->ctrl.clk_axi = clk_axi; -+ pfe->ctrl.sys_clk = clk_get_rate(clk_axi) / 1000; // save sys_clk value as KHz -+ -+ rc = pfe_probe(pfe); -+ if (rc < 0) -+ goto err_probe; -+ -+ return 0; -+ -+err_probe: -+ clk_put(pfe->hfe_clock); -+err_hfe_clock: -+ clk_put(clk_axi); -+err_clk: -+err_hif_irq: -+ iounmap(pfe->ipsec_baseaddr); -+err_ipsec: -+ iounmap(pfe->iram_baseaddr); -+err_iram: -+ iounmap(pfe->apb_baseaddr); -+ -+err_apb: -+ iounmap(pfe->cbus_baseaddr); -+ -+err_axi: -+ iounmap(pfe->ddr_baseaddr); -+ -+err_ddr: -+ platform_set_drvdata(pdev, NULL); -+ -+ kfree(pfe); -+ -+err_alloc: -+ return rc; -+} -+ -+ -+/** -+ * pfe_platform_remove - -+ * -+ * -+ */ -+static int pfe_platform_remove(struct platform_device *pdev) -+{ -+ struct pfe *pfe = platform_get_drvdata(pdev); -+ int rc; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ rc = pfe_remove(pfe); -+ -+ c2000_block_reset(COMPONENT_PFE_SYS, 1); -+ clk_disable(pfe->hfe_clock); -+ clk_put(pfe->hfe_clock); -+ clk_put(pfe->ctrl.clk_axi); -+ iounmap(pfe->ipsec_baseaddr); -+ iounmap(pfe->iram_baseaddr); -+ iounmap(pfe->apb_baseaddr); -+ iounmap(pfe->cbus_baseaddr); -+ iounmap(pfe->ddr_baseaddr); -+ -+ platform_set_drvdata(pdev, NULL); -+ -+ kfree(pfe); -+ -+ return rc; -+} -+ -+#ifdef CONFIG_PM -+ -+#ifdef CONFIG_PM_SLEEP -+static int pfe_platform_suspend(struct device *dev) -+{ -+ struct pfe *pfe = platform_get_drvdata(to_platform_device(dev)); -+ struct net_device *netdev; -+ int i; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ pfe->wake = 0; -+ -+ for (i = 0; i < (NUM_GEMAC_SUPPORT - 1); i++ ) { -+ netdev = pfe->eth.eth_priv[i]->dev; -+ -+ netif_device_detach(netdev); -+ -+ if (netif_running(netdev)) -+ if(pfe_eth_suspend(netdev)) -+ pfe->wake =1; -+ } -+ -+ /* Shutdown PFE only if we're not waking up the system */ -+ if (!pfe->wake) { -+ pfe_ctrl_suspend(&pfe->ctrl); -+ pfe_hif_exit(pfe); -+ pfe_hif_lib_exit(pfe); -+ -+ class_disable(); -+ tmu_disable(0xf); -+#if !defined(CONFIG_UTIL_DISABLED) -+ util_disable(); -+#endif -+ pfe_hw_exit(pfe); -+ c2000_block_reset(COMPONENT_PFE_SYS, 1); -+ clk_disable(pfe->hfe_clock); -+ } -+ -+ return 0; -+} -+ -+static int pfe_platform_resume(struct device *dev) -+{ -+ struct pfe *pfe = platform_get_drvdata(to_platform_device(dev)); -+ struct net_device *netdev; -+ int i; -+ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ if (!pfe->wake) { -+ /* Sequence follows VLSI recommendation (bug 71927) */ -+ c2000_block_reset(COMPONENT_PFE_SYS, 1); -+ mdelay(1); -+ c2000_block_reset(COMPONENT_PFE_SYS, 0); -+ clk_enable(pfe->hfe_clock); -+ -+ pfe_hw_init(pfe, 1); -+ pfe_hif_lib_init(pfe); -+ pfe_hif_init(pfe); -+#if !defined(CONFIG_UTIL_DISABLED) -+ util_enable(); -+#endif -+ tmu_enable(0xf); -+ class_enable(); -+ pfe_ctrl_resume(&pfe->ctrl); -+ } -+ -+ for(i = 0; i < (NUM_GEMAC_SUPPORT - 1); i++) { -+ netdev = pfe->eth.eth_priv[i]->dev; -+ -+ if (pfe->eth.eth_priv[i]->mii_bus) -+ pfe_eth_mdio_reset(pfe->eth.eth_priv[i]->mii_bus); -+ -+ if (netif_running(netdev)) -+ pfe_eth_resume(netdev); -+ -+ netif_device_attach(netdev); -+ } -+ return 0; -+} -+#else -+#define pfe_platform_suspend NULL -+#define pfe_platform_resume NULL -+#endif -+ -+static const struct dev_pm_ops pfe_platform_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(pfe_platform_suspend, pfe_platform_resume) -+}; -+ -+#endif -+ -+static struct platform_driver pfe_platform_driver = { -+ .probe = pfe_platform_probe, -+ .remove = pfe_platform_remove, -+ .driver = { -+ .name = "pfe", -+#ifdef CONFIG_PM -+ .pm = &pfe_platform_pm_ops, -+#endif -+ }, -+}; -+ -+ -+static int __init pfe_module_init(void) -+{ -+ printk(KERN_INFO "%s\n", __func__); -+ -+ return platform_driver_register(&pfe_platform_driver); -+} -+ -+ -+static void __exit pfe_module_exit(void) -+{ -+ platform_driver_unregister(&pfe_platform_driver); -+ -+ printk(KERN_INFO "%s\n", __func__); -+} -+ -+MODULE_LICENSE("GPL"); -+module_init(pfe_module_init); -+module_exit(pfe_module_exit); ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_sysfs.c -@@ -0,0 +1,855 @@ -+/* -+ * (C) Copyright 2011 -+ * Author : Freescale Semiconductor, Inc. -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ * */ -+ -+#include -+#include -+ -+#include "pfe_mod.h" -+#include "pfe_ctrl_hal.h" -+ -+#define PE_EXCEPTION_DUMP_ADDRESS 0x1fa8 -+#define NUM_QUEUES 16 -+ -+static char register_name[20][5] = { -+ "EPC", "ECAS", "EID", "ED", -+ "r0", "r1", "r2", "r3", -+ "r4", "r5", "r6", "r7", -+ "r8", "r9", "r10", "r11", -+ "r12", "r13", "r14", "r15", -+}; -+ -+static char exception_name[14][20] = { -+ "Reset", -+ "HardwareFailure", -+ "NMI", -+ "InstBreakpoint", -+ "DataBreakpoint", -+ "Unsupported", -+ "PrivilegeViolation", -+ "InstBusError", -+ "DataBusError", -+ "AlignmentError", -+ "ArithmeticError", -+ "SystemCall", -+ "MemoryManagement", -+ "Interrupt", -+}; -+ -+static unsigned long class_do_clear = 0; -+static unsigned long tmu_do_clear = 0; -+#if !defined(CONFIG_UTIL_DISABLED) -+static unsigned long util_do_clear = 0; -+#endif -+ -+u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset); -+ -+static ssize_t display_pe_status(char *buf, int id, u32 dmem_addr, unsigned long do_clear) -+{ -+ ssize_t len = 0; -+ u32 val; -+ char statebuf[5]; -+ struct pfe_cpumon *cpumon = &pfe->cpumon; -+ u32 debug_indicator; -+ u32 debug[20]; -+ -+ *(u32 *)statebuf = pe_dmem_read(id, dmem_addr, 4); -+ dmem_addr += 4; -+ -+ statebuf[4] = '\0'; -+ len += sprintf(buf + len, "state=%4s ", statebuf); -+ -+ val = pe_dmem_read(id, dmem_addr, 4); -+ dmem_addr += 4; -+ len += sprintf(buf + len, "ctr=%08x ", cpu_to_be32(val)); -+ -+ val = pe_dmem_read(id, dmem_addr, 4); -+ if (do_clear && val) -+ pe_dmem_write(id, 0, dmem_addr, 4); -+ dmem_addr += 4; -+ len += sprintf(buf + len, "rx=%u ", cpu_to_be32(val)); -+ -+ val = pe_dmem_read(id, dmem_addr, 4); -+ if (do_clear && val) -+ pe_dmem_write(id, 0, dmem_addr, 4); -+ dmem_addr += 4; -+ if (id >= TMU0_ID && id <= TMU_MAX_ID) -+ len += sprintf(buf + len, "qstatus=%x", cpu_to_be32(val)); -+ else -+ len += sprintf(buf + len, "tx=%u", cpu_to_be32(val)); -+ -+ val = pe_dmem_read(id, dmem_addr, 4); -+ if (do_clear && val) -+ pe_dmem_write(id, 0, dmem_addr, 4); -+ dmem_addr += 4; -+ if (val) -+ len += sprintf(buf + len, " drop=%u", cpu_to_be32(val)); -+ -+ len += sprintf(buf + len, " load=%d%%", cpumon->cpu_usage_pct[id]); -+ -+ len += sprintf(buf + len, "\n"); -+ -+ debug_indicator = pe_dmem_read(id, dmem_addr, 4); -+ dmem_addr += 4; -+ if (!strncmp((char *)&debug_indicator, "DBUG", 4)) -+ { -+ int j, last = 0; -+ for (j = 0; j < 16; j++) -+ { -+ debug[j] = pe_dmem_read(id, dmem_addr, 4); -+ if (debug[j]) -+ { -+ if (do_clear) -+ pe_dmem_write(id, 0, dmem_addr, 4); -+ last = j + 1; -+ } -+ dmem_addr += 4; -+ } -+ for (j = 0; j < last; j++) -+ { -+ len += sprintf(buf + len, "%08x%s", cpu_to_be32(debug[j]), -+ (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " "); -+ } -+ } -+ -+ if (!strncmp(statebuf, "DEAD", 4)) -+ { -+ u32 i, dump = PE_EXCEPTION_DUMP_ADDRESS; -+ -+ len += sprintf(buf + len, "Exception details:\n"); -+ for (i = 0; i < 20; i++) { -+ debug[i] = pe_dmem_read(id, dump, 4); -+ dump +=4; -+ if (i == 2) -+ len += sprintf(buf + len, "%4s = %08x (=%s) ", register_name[i], cpu_to_be32(debug[i]), exception_name[min((u32) cpu_to_be32(debug[i]), (u32)13)]); -+ else -+ len += sprintf(buf + len, "%4s = %08x%s", register_name[i], cpu_to_be32(debug[i]), -+ (i & 0x3) == 0x3 || i == 19 ? "\n" : " "); -+ } -+ } -+ -+ return len; -+} -+ -+static ssize_t class_phy_stats(char *buf, int phy) -+{ -+ ssize_t len = 0; -+ int off1 = phy * 0x28; -+ int off2 = phy * 0x10; -+ -+ if (phy == 3) -+ off1 = CLASS_PHY4_RX_PKTS - CLASS_PHY1_RX_PKTS; -+ -+ len += sprintf(buf + len, "phy: %d\n", phy); -+ len += sprintf(buf + len, " rx: %10u, tx: %10u, intf: %10u, ipv4: %10u, ipv6: %10u\n", -+ readl(CLASS_PHY1_RX_PKTS + off1), readl(CLASS_PHY1_TX_PKTS + off1), -+ readl(CLASS_PHY1_INTF_MATCH_PKTS + off1), readl(CLASS_PHY1_V4_PKTS + off1), -+ readl(CLASS_PHY1_V6_PKTS + off1)); -+ -+ len += sprintf(buf + len, " icmp: %10u, igmp: %10u, tcp: %10u, udp: %10u\n", -+ readl(CLASS_PHY1_ICMP_PKTS + off2), readl(CLASS_PHY1_IGMP_PKTS + off2), -+ readl(CLASS_PHY1_TCP_PKTS + off2), readl(CLASS_PHY1_UDP_PKTS + off2)); -+ -+ len += sprintf(buf + len, " err\n"); -+ len += sprintf(buf + len, " lp: %10u, intf: %10u, l3: %10u, chcksum: %10u, ttl: %10u\n", -+ readl(CLASS_PHY1_LP_FAIL_PKTS + off1), readl(CLASS_PHY1_INTF_FAIL_PKTS + off1), -+ readl(CLASS_PHY1_L3_FAIL_PKTS + off1), readl(CLASS_PHY1_CHKSUM_ERR_PKTS + off1), -+ readl(CLASS_PHY1_TTL_ERR_PKTS + off1)); -+ -+ return len; -+} -+ -+/** qm_read_drop_stat -+ * This function is used to read the drop statistics from the TMU -+ * hw drop counter. Since the hw counter is always cleared afer -+ * reading, this function maintains the previous drop count, and -+ * adds the new value to it. That value can be retrieved by -+ * passing a pointer to it with the total_drops arg. -+ * -+ * @param tmu TMU number (0 - 3) -+ * @param queue queue number (0 - 15) -+ * @param total_drops pointer to location to store total drops (or NULL) -+ * @param do_reset if TRUE, clear total drops after updating -+ * -+ */ -+ -+u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset) -+{ -+ static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES]; -+ u32 val; -+ writel((tmu << 8) | queue, TMU_TEQ_CTRL); -+ writel((tmu << 8) | queue, TMU_LLM_CTRL); -+ val = readl(TMU_TEQ_DROP_STAT); -+ qtotal[tmu][queue] += val; -+ if (total_drops) -+ *total_drops = qtotal[tmu][queue]; -+ if (do_reset) -+ qtotal[tmu][queue] = 0; -+ return val; -+} -+ -+static ssize_t tmu_queue_stats(char *buf, int tmu, int queue) -+{ -+ ssize_t len = 0; -+ u32 drops; -+ -+ len += sprintf(buf + len, "%d-%02d, ", tmu, queue); -+ -+ drops = qm_read_drop_stat(tmu, queue, NULL, 0); -+ -+ /* Select queue */ -+ writel((tmu << 8) | queue, TMU_TEQ_CTRL); -+ writel((tmu << 8) | queue, TMU_LLM_CTRL); -+ -+ len += sprintf(buf + len, "(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n", -+ drops, readl(TMU_TEQ_TRANS_STAT), -+ readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR), -+ readl(TMU_LLM_QUE_DROPCNT)); -+ -+ return len; -+} -+ -+ -+static ssize_t tmu_queues(char *buf, int tmu) -+{ -+ ssize_t len = 0; -+ int queue; -+ -+ for (queue = 0; queue < 16; queue++) -+ len += tmu_queue_stats(buf + len, tmu, queue); -+ -+ return len; -+} -+ -+static ssize_t tmu_ctx(char *buf, int tmu) -+{ -+ ssize_t len = 0; -+ int i; -+ u32 val, tmu_context_addr = TMU_CONTEXT_ADDR; -+ -+ len += sprintf(buf+len, " TMU %d \n", TMU0_ID+tmu); -+ for (i = 1; i <= 160 ; i++, tmu_context_addr += 4) -+ { -+ val = pe_dmem_read(TMU0_ID+tmu, tmu_context_addr , 4); -+ if (i == 5) -+ len += sprintf(buf+len, "\nShapers: Each shaper structure is 8 bytes and there are 10 shapers\n"); -+ -+ if (i == 25) -+ len += sprintf(buf+len, "\nScheduler: Each scheduler structure is 48 bytes and there are 8 schedulers\n"); -+ if (i == 121) -+ len += sprintf(buf+len, "\nQueue: Each queue structure is 2 bytes and there are 16 queues\n"); -+ -+ if (i == 129) -+ len += sprintf(buf+len, "\nqlenmasks array for 16 queues\n"); -+ if (i == 145) -+ len += sprintf(buf+len, "\nqresultmap array for 16 queues\n"); -+ if (i%8 == 0) -+ len += sprintf(buf+len, "%08x \n", cpu_to_be32(val)); -+ else -+ len += sprintf(buf+len, "%08x ", cpu_to_be32(val)); -+ } -+ -+ len += sprintf(buf+len, "\n"); -+ -+ return len; -+} -+ -+static ssize_t block_version(char *buf, void *addr) -+{ -+ ssize_t len = 0; -+ u32 val; -+ -+ val = readl(addr); -+ len += sprintf(buf + len, "revision: %x, version: %x, id: %x\n", (val >> 24) & 0xff, (val >> 16) & 0xff, val & 0xffff); -+ -+ return len; -+} -+ -+static ssize_t bmu(char *buf, int id, void *base) -+{ -+ ssize_t len = 0; -+ -+ len += sprintf(buf + len, "bmu: %d\n ", id); -+ -+ len += block_version(buf + len, base + BMU_VERSION); -+ -+ len += sprintf(buf + len, " buf size: %x\n", (1 << readl(base + BMU_BUF_SIZE))); -+ len += sprintf(buf + len, " buf count: %x\n", readl(base + BMU_BUF_CNT)); -+ len += sprintf(buf + len, " buf rem: %x\n", readl(base + BMU_REM_BUF_CNT)); -+ len += sprintf(buf + len, " buf curr: %x\n", readl(base + BMU_CURR_BUF_CNT)); -+ len += sprintf(buf + len, " free err: %x\n", readl(base + BMU_FREE_ERR_ADDR)); -+ -+ return len; -+} -+ -+static ssize_t gpi(char *buf, int id, void *base) -+{ -+ ssize_t len = 0; -+ u32 val; -+ -+ len += sprintf(buf + len, "gpi%d:\n ", id); -+ len += block_version(buf + len, base + GPI_VERSION); -+ -+ len += sprintf(buf + len, " tx under stick: %x\n", readl(base + GPI_FIFO_STATUS)); -+ val = readl(base + GPI_FIFO_DEBUG); -+ len += sprintf(buf + len, " tx pkts: %x\n", (val >> 23) & 0x3f); -+ len += sprintf(buf + len, " rx pkts: %x\n", (val >> 18) & 0x3f); -+ len += sprintf(buf + len, " tx bytes: %x\n", (val >> 9) & 0x1ff); -+ len += sprintf(buf + len, " rx bytes: %x\n", (val >> 0) & 0x1ff); -+ len += sprintf(buf + len, " overrun: %x\n", readl(base + GPI_OVERRUN_DROPCNT)); -+ -+ return len; -+} -+ -+static ssize_t pfe_set_class(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -+{ -+ class_do_clear = simple_strtoul(buf, NULL, 0); -+ return count; -+} -+ -+static ssize_t pfe_show_class(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ int id; -+ u32 val; -+ struct pfe_cpumon *cpumon = &pfe->cpumon; -+ -+ len += block_version(buf + len, CLASS_VERSION); -+ -+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) -+ { -+ len += sprintf(buf + len, "%d: ", id - CLASS0_ID); -+ -+ val = readl(CLASS_PE0_DEBUG + id * 4); -+ len += sprintf(buf + len, "pc=1%04x ", val & 0xffff); -+ -+ len += display_pe_status(buf + len, id, PESTATUS_ADDR_CLASS, class_do_clear); -+ } -+ len += sprintf(buf + len, "aggregate load=%d%%\n\n", cpumon->class_usage_pct); -+ -+ len += sprintf(buf + len, "pe status: 0x%x\n", readl(CLASS_PE_STATUS)); -+ len += sprintf(buf + len, "max buf cnt: 0x%x afull thres: 0x%x\n", readl(CLASS_MAX_BUF_CNT), readl(CLASS_AFULL_THRES)); -+ len += sprintf(buf + len, "tsq max cnt: 0x%x tsq fifo thres: 0x%x\n", readl(CLASS_TSQ_MAX_CNT), readl(CLASS_TSQ_FIFO_THRES)); -+ len += sprintf(buf + len, "state: 0x%x\n", readl(CLASS_STATE)); -+ -+ len += class_phy_stats(buf + len, 0); -+ len += class_phy_stats(buf + len, 1); -+ len += class_phy_stats(buf + len, 2); -+ len += class_phy_stats(buf + len, 3); -+ -+ return len; -+} -+ -+static ssize_t pfe_set_tmu(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -+{ -+ tmu_do_clear = simple_strtoul(buf, NULL, 0); -+ return count; -+} -+ -+static ssize_t pfe_show_tmu(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ int id; -+ u32 val; -+ -+ len += block_version(buf + len, TMU_VERSION); -+ -+ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) -+ { -+#if defined(CONFIG_PLATFORM_LS1012A) -+ if(id == TMU2_ID) continue; -+#endif -+ len += sprintf(buf + len, "%d: ", id - TMU0_ID); -+ -+ len += display_pe_status(buf + len, id, PESTATUS_ADDR_TMU, tmu_do_clear); -+ } -+ -+ len += sprintf(buf + len, "pe status: %x\n", readl(TMU_PE_STATUS)); -+ len += sprintf(buf + len, "inq fifo cnt: %x\n", readl(TMU_PHY_INQ_FIFO_CNT)); -+ val = readl(TMU_INQ_STAT); -+ len += sprintf(buf + len, "inq wr ptr: %x\n", val & 0x3ff); -+ len += sprintf(buf + len, "inq rd ptr: %x\n", val >> 10); -+ -+ -+ return len; -+} -+ -+ -+static unsigned long drops_do_clear = 0; -+static u32 CLASS_DMEM_SH2(drop_counter)[CLASS_NUM_DROP_COUNTERS]; -+#if !defined(CONFIG_UTIL_DISABLED) -+static u32 UTIL_DMEM_SH2(drop_counter)[UTIL_NUM_DROP_COUNTERS]; -+#endif -+ -+char *class_drop_description[CLASS_NUM_DROP_COUNTERS] = { -+ "ICC", -+ "Host Pkt Error", -+ "Rx Error", -+ "IPsec Outbound", -+ "IPsec Inbound", -+ "EXPT IPsec Error", -+ "Reassembly", -+ "Fragmenter", -+ "NAT-T", -+ "Socket", -+ "Multicast", -+ "NAT-PT", -+ "Tx Disabled", -+}; -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+char *util_drop_description[UTIL_NUM_DROP_COUNTERS] = { -+ "IPsec Outbound", -+ "IPsec Inbound", -+ "IPsec Rate Limiter", -+ "Fragmenter", -+ "Socket", -+ "Tx Disabled", -+ "Rx Error", -+}; -+#endif -+ -+static ssize_t pfe_set_drops(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -+{ -+ drops_do_clear = simple_strtoul(buf, NULL, 0); -+ return count; -+} -+ -+static u32 tmu_drops[4][16]; -+static ssize_t pfe_show_drops(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ int id, dropnum; -+ int tmu, queue; -+ u32 val; -+ u32 dmem_addr; -+ int num_class_drops = 0, num_tmu_drops = 0, num_util_drops = 0; -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ -+ memset(class_drop_counter, 0, sizeof(class_drop_counter)); -+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) -+ { -+ if (drops_do_clear) -+ pe_sync_stop(ctrl, (1 << id)); -+ for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS; dropnum++) -+ { -+ dmem_addr = virt_to_class_dmem(&class_drop_counter[dropnum]); -+ val = be32_to_cpu(pe_dmem_read(id, dmem_addr, 4)); -+ class_drop_counter[dropnum] += val; -+ num_class_drops += val; -+ if (drops_do_clear) -+ pe_dmem_write(id, 0, dmem_addr, 4); -+ } -+ if (drops_do_clear) -+ pe_start(ctrl, (1 << id)); -+ } -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+ if (drops_do_clear) -+ pe_sync_stop(ctrl, (1 << UTIL_ID)); -+ for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) -+ { -+ dmem_addr = virt_to_util_dmem(&util_drop_counter[dropnum]); -+ val = be32_to_cpu(pe_dmem_read(UTIL_ID, dmem_addr, 4)); -+ util_drop_counter[dropnum] = val; -+ num_util_drops += val; -+ if (drops_do_clear) -+ pe_dmem_write(UTIL_ID, 0, dmem_addr, 4); -+ } -+ if (drops_do_clear) -+ pe_start(ctrl, (1 << UTIL_ID)); -+#endif -+ for (tmu = 0; tmu < 4; tmu++) -+ { -+ for (queue = 0; queue < 16; queue++) -+ { -+ qm_read_drop_stat(tmu, queue, &tmu_drops[tmu][queue], drops_do_clear); -+ num_tmu_drops += tmu_drops[tmu][queue]; -+ } -+ } -+ -+ if (num_class_drops == 0 && num_util_drops == 0 && num_tmu_drops == 0) -+ len += sprintf(buf + len, "No PE drops\n\n"); -+ -+ if (num_class_drops > 0) -+ { -+ len += sprintf(buf + len, "Class PE drops --\n"); -+ for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS; dropnum++) -+ { -+ if (class_drop_counter[dropnum] > 0) -+ len += sprintf(buf + len, " %s: %d\n", class_drop_description[dropnum], class_drop_counter[dropnum]); -+ } -+ len += sprintf(buf + len, "\n"); -+ } -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+ if (num_util_drops > 0) -+ { -+ len += sprintf(buf + len, "Util PE drops --\n"); -+ for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) -+ { -+ if (util_drop_counter[dropnum] > 0) -+ len += sprintf(buf + len, " %s: %d\n", util_drop_description[dropnum], util_drop_counter[dropnum]); -+ } -+ len += sprintf(buf + len, "\n"); -+ } -+#endif -+ if (num_tmu_drops > 0) -+ { -+ len += sprintf(buf + len, "TMU drops --\n"); -+ for (tmu = 0; tmu < 4; tmu++) -+ { -+ for (queue = 0; queue < 16; queue++) -+ { -+ if (tmu_drops[tmu][queue] > 0) -+ len += sprintf(buf + len, " TMU%d-Q%d: %d\n", tmu, queue, tmu_drops[tmu][queue]); -+ } -+ } -+ len += sprintf(buf + len, "\n"); -+ } -+ -+ return len; -+} -+ -+static ssize_t pfe_show_tmu0_queues(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ return tmu_queues(buf, 0); -+} -+ -+static ssize_t pfe_show_tmu1_queues(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ return tmu_queues(buf, 1); -+} -+ -+static ssize_t pfe_show_tmu2_queues(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ return tmu_queues(buf, 2); -+} -+ -+static ssize_t pfe_show_tmu3_queues(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ return tmu_queues(buf, 3); -+} -+ -+static ssize_t pfe_show_tmu0_ctx(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ return tmu_ctx(buf, 0); -+} -+static ssize_t pfe_show_tmu1_ctx(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ return tmu_ctx(buf, 1); -+} -+static ssize_t pfe_show_tmu2_ctx(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ return tmu_ctx(buf, 2); -+} -+ -+static ssize_t pfe_show_tmu3_ctx(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ return tmu_ctx(buf, 3); -+} -+ -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+static ssize_t pfe_set_util(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -+{ -+ util_do_clear = simple_strtoul(buf, NULL, 0); -+ return count; -+} -+ -+static ssize_t pfe_show_util(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ -+ -+ len += block_version(buf + len, UTIL_VERSION); -+ -+ pe_sync_stop(ctrl, (1 << UTIL_ID)); -+ len += display_pe_status(buf + len, UTIL_ID, PESTATUS_ADDR_UTIL, util_do_clear); -+ pe_start(ctrl, (1 << UTIL_ID)); -+ -+ len += sprintf(buf + len, "pe status: %x\n", readl(UTIL_PE_STATUS)); -+ len += sprintf(buf + len, "max buf cnt: %x\n", readl(UTIL_MAX_BUF_CNT)); -+ len += sprintf(buf + len, "tsq max cnt: %x\n", readl(UTIL_TSQ_MAX_CNT)); -+ -+ return len; -+} -+#endif -+ -+static ssize_t pfe_show_bmu(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ -+ len += bmu(buf + len, 1, BMU1_BASE_ADDR); -+ len += bmu(buf + len, 2, BMU2_BASE_ADDR); -+ -+ return len; -+} -+ -+static ssize_t pfe_show_hif(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ -+ len += sprintf(buf + len, "hif:\n "); -+ len += block_version(buf + len, HIF_VERSION); -+ -+ len += sprintf(buf + len, " tx curr bd: %x\n", readl(HIF_TX_CURR_BD_ADDR)); -+ len += sprintf(buf + len, " tx status: %x\n", readl(HIF_TX_STATUS)); -+ len += sprintf(buf + len, " tx dma status: %x\n", readl(HIF_TX_DMA_STATUS)); -+ -+ len += sprintf(buf + len, " rx curr bd: %x\n", readl(HIF_RX_CURR_BD_ADDR)); -+ len += sprintf(buf + len, " rx status: %x\n", readl(HIF_RX_STATUS)); -+ len += sprintf(buf + len, " rx dma status: %x\n", readl(HIF_RX_DMA_STATUS)); -+ -+ len += sprintf(buf + len, "hif nocopy:\n "); -+ len += block_version(buf + len, HIF_NOCPY_VERSION); -+ -+ len += sprintf(buf + len, " tx curr bd: %x\n", readl(HIF_NOCPY_TX_CURR_BD_ADDR)); -+ len += sprintf(buf + len, " tx status: %x\n", readl(HIF_NOCPY_TX_STATUS)); -+ len += sprintf(buf + len, " tx dma status: %x\n", readl(HIF_NOCPY_TX_DMA_STATUS)); -+ -+ len += sprintf(buf + len, " rx curr bd: %x\n", readl(HIF_NOCPY_RX_CURR_BD_ADDR)); -+ len += sprintf(buf + len, " rx status: %x\n", readl(HIF_NOCPY_RX_STATUS)); -+ len += sprintf(buf + len, " rx dma status: %x\n", readl(HIF_NOCPY_RX_DMA_STATUS)); -+ -+ return len; -+} -+ -+ -+static ssize_t pfe_show_gpi(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ -+ len += gpi(buf + len, 0, EGPI1_BASE_ADDR); -+ len += gpi(buf + len, 1, EGPI2_BASE_ADDR); -+#if !defined(CONFIG_PLATFORM_LS1012A) -+ len += gpi(buf + len, 2, EGPI3_BASE_ADDR); -+#endif -+ len += gpi(buf + len, 3, HGPI_BASE_ADDR); -+ -+ return len; -+} -+ -+static ssize_t pfe_show_pfemem(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ struct pfe_memmon *memmon = &pfe->memmon; -+ -+ len += sprintf(buf + len, "Kernel Memory: %d Bytes (%d KB)\n", memmon->kernel_memory_allocated, (memmon->kernel_memory_allocated + 1023) / 1024); -+ -+ return len; -+} -+ -+#ifdef HIF_NAPI_STATS -+static ssize_t pfe_show_hif_napi_stats(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct pfe *pfe = platform_get_drvdata(pdev); -+ ssize_t len = 0; -+ -+ len += sprintf(buf + len, "sched: %u\n", pfe->hif.napi_counters[NAPI_SCHED_COUNT]); -+ len += sprintf(buf + len, "poll: %u\n", pfe->hif.napi_counters[NAPI_POLL_COUNT]); -+ len += sprintf(buf + len, "packet: %u\n", pfe->hif.napi_counters[NAPI_PACKET_COUNT]); -+ len += sprintf(buf + len, "budget: %u\n", pfe->hif.napi_counters[NAPI_FULL_BUDGET_COUNT]); -+ len += sprintf(buf + len, "desc: %u\n", pfe->hif.napi_counters[NAPI_DESC_COUNT]); -+ len += sprintf(buf + len, "full: %u\n", pfe->hif.napi_counters[NAPI_CLIENT_FULL_COUNT]); -+ -+ return len; -+} -+ -+static ssize_t pfe_set_hif_napi_stats(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct pfe *pfe = platform_get_drvdata(pdev); -+ -+ memset(pfe->hif.napi_counters, 0, sizeof(pfe->hif.napi_counters)); -+ -+ return count; -+} -+ -+static DEVICE_ATTR(hif_napi_stats, 0644, pfe_show_hif_napi_stats, pfe_set_hif_napi_stats); -+#endif -+ -+ -+static DEVICE_ATTR(class, 0644, pfe_show_class, pfe_set_class); -+static DEVICE_ATTR(tmu, 0644, pfe_show_tmu, pfe_set_tmu); -+#if !defined(CONFIG_UTIL_DISABLED) -+static DEVICE_ATTR(util, 0644, pfe_show_util, pfe_set_util); -+#endif -+static DEVICE_ATTR(bmu, 0444, pfe_show_bmu, NULL); -+static DEVICE_ATTR(hif, 0444, pfe_show_hif, NULL); -+static DEVICE_ATTR(gpi, 0444, pfe_show_gpi, NULL); -+static DEVICE_ATTR(drops, 0644, pfe_show_drops, pfe_set_drops); -+static DEVICE_ATTR(tmu0_queues, 0444, pfe_show_tmu0_queues, NULL); -+static DEVICE_ATTR(tmu1_queues, 0444, pfe_show_tmu1_queues, NULL); -+static DEVICE_ATTR(tmu2_queues, 0444, pfe_show_tmu2_queues, NULL); -+static DEVICE_ATTR(tmu3_queues, 0444, pfe_show_tmu3_queues, NULL); -+static DEVICE_ATTR(tmu0_ctx, 0444, pfe_show_tmu0_ctx, NULL); -+static DEVICE_ATTR(tmu1_ctx, 0444, pfe_show_tmu1_ctx, NULL); -+static DEVICE_ATTR(tmu2_ctx, 0444, pfe_show_tmu2_ctx, NULL); -+static DEVICE_ATTR(tmu3_ctx, 0444, pfe_show_tmu3_ctx, NULL); -+static DEVICE_ATTR(pfemem, 0444, pfe_show_pfemem, NULL); -+ -+ -+int pfe_sysfs_init(struct pfe *pfe) -+{ -+ if (device_create_file(pfe->dev, &dev_attr_class)) -+ goto err_class; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu)) -+ goto err_tmu; -+ -+#if !defined(CONFIG_UTIL_DISABLED) -+ if (device_create_file(pfe->dev, &dev_attr_util)) -+ goto err_util; -+#endif -+ -+ if (device_create_file(pfe->dev, &dev_attr_bmu)) -+ goto err_bmu; -+ -+ if (device_create_file(pfe->dev, &dev_attr_hif)) -+ goto err_hif; -+ -+ if (device_create_file(pfe->dev, &dev_attr_gpi)) -+ goto err_gpi; -+ -+ if (device_create_file(pfe->dev, &dev_attr_drops)) -+ goto err_drops; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu0_queues)) -+ goto err_tmu0_queues; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu1_queues)) -+ goto err_tmu1_queues; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu2_queues)) -+ goto err_tmu2_queues; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu3_queues)) -+ goto err_tmu3_queues; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu0_ctx)) -+ goto err_tmu0_ctx; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu1_ctx)) -+ goto err_tmu1_ctx; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu2_ctx)) -+ goto err_tmu2_ctx; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu3_ctx)) -+ goto err_tmu3_ctx; -+ -+ if (device_create_file(pfe->dev, &dev_attr_pfemem)) -+ goto err_pfemem; -+ -+#ifdef HIF_NAPI_STATS -+ if (device_create_file(pfe->dev, &dev_attr_hif_napi_stats)) -+ goto err_hif_napi_stats; -+#endif -+ -+ return 0; -+ -+#ifdef HIF_NAPI_STATS -+err_hif_napi_stats: -+ device_remove_file(pfe->dev, &dev_attr_pfemem); -+#endif -+ -+err_pfemem: -+ device_remove_file(pfe->dev, &dev_attr_tmu3_ctx); -+ -+err_tmu3_ctx: -+ device_remove_file(pfe->dev, &dev_attr_tmu2_ctx); -+ -+err_tmu2_ctx: -+ device_remove_file(pfe->dev, &dev_attr_tmu1_ctx); -+ -+err_tmu1_ctx: -+ device_remove_file(pfe->dev, &dev_attr_tmu0_ctx); -+ -+err_tmu0_ctx: -+ device_remove_file(pfe->dev, &dev_attr_tmu3_queues); -+ -+err_tmu3_queues: -+ device_remove_file(pfe->dev, &dev_attr_tmu2_queues); -+ -+err_tmu2_queues: -+ device_remove_file(pfe->dev, &dev_attr_tmu1_queues); -+ -+err_tmu1_queues: -+ device_remove_file(pfe->dev, &dev_attr_tmu0_queues); -+ -+err_tmu0_queues: -+ device_remove_file(pfe->dev, &dev_attr_drops); -+ -+err_drops: -+ device_remove_file(pfe->dev, &dev_attr_gpi); -+ -+err_gpi: -+ device_remove_file(pfe->dev, &dev_attr_hif); -+ -+err_hif: -+ device_remove_file(pfe->dev, &dev_attr_bmu); -+ -+err_bmu: -+#if !defined(CONFIG_UTIL_DISABLED) -+ device_remove_file(pfe->dev, &dev_attr_util); -+ -+err_util: -+#endif -+ device_remove_file(pfe->dev, &dev_attr_tmu); -+ -+err_tmu: -+ device_remove_file(pfe->dev, &dev_attr_class); -+ -+err_class: -+ return -1; -+} -+ -+ -+void pfe_sysfs_exit(struct pfe *pfe) -+{ -+#ifdef HIF_NAPI_STATS -+ device_remove_file(pfe->dev, &dev_attr_hif_napi_stats); -+#endif -+ -+ device_remove_file(pfe->dev, &dev_attr_pfemem); -+ device_remove_file(pfe->dev, &dev_attr_tmu3_ctx); -+ device_remove_file(pfe->dev, &dev_attr_tmu2_ctx); -+ device_remove_file(pfe->dev, &dev_attr_tmu1_ctx); -+ device_remove_file(pfe->dev, &dev_attr_tmu0_ctx); -+ device_remove_file(pfe->dev, &dev_attr_tmu3_queues); -+ device_remove_file(pfe->dev, &dev_attr_tmu2_queues); -+ device_remove_file(pfe->dev, &dev_attr_tmu1_queues); -+ device_remove_file(pfe->dev, &dev_attr_tmu0_queues); -+ device_remove_file(pfe->dev, &dev_attr_drops); -+ device_remove_file(pfe->dev, &dev_attr_gpi); -+ device_remove_file(pfe->dev, &dev_attr_hif); -+ device_remove_file(pfe->dev, &dev_attr_bmu); -+#if !defined(CONFIG_UTIL_DISABLED) -+ device_remove_file(pfe->dev, &dev_attr_util); -+#endif -+ device_remove_file(pfe->dev, &dev_attr_tmu); -+ device_remove_file(pfe->dev, &dev_attr_class); -+} -+ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_sysfs.h -@@ -0,0 +1,34 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _PFE_SYSFS_H_ -+#define _PFE_SYSFS_H_ -+ -+#include -+ -+#define PESTATUS_ADDR_CLASS 0x800 -+#define PESTATUS_ADDR_TMU 0x80 -+#define PESTATUS_ADDR_UTIL 0x0 -+ -+#define TMU_CONTEXT_ADDR 0x3c8 -+#define IPSEC_CNTRS_ADDR 0x840 -+ -+int pfe_sysfs_init(struct pfe *pfe); -+void pfe_sysfs_exit(struct pfe *pfe); -+#endif /* _PFE_SYSFS_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/platform.h -@@ -0,0 +1,25 @@ -+/* -+ * -+ * Copyright (C) 2007 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _PLATFORM_H_ -+#define _PLATFORM_H_ -+ -+#define virt_to_phys(virt) ((unsigned long)virt) -+ -+#endif /* _PLATFORM_H_ */ ---- a/include/linux/skbuff.h -+++ b/include/linux/skbuff.h -@@ -858,6 +858,17 @@ static inline struct sk_buff *alloc_skb_ - return __alloc_skb(size, priority, SKB_ALLOC_FCLONE, NUMA_NO_NODE); - } - -+extern struct sk_buff *__alloc_skb_header(unsigned int size, void *data, -+ gfp_t gfp_mask, -+ int fclone, -+ int node); -+static inline struct sk_buff *alloc_skb_header(unsigned int size, -+ u8 *data, -+ gfp_t priority) -+{ -+ return __alloc_skb_header(size, data, priority, 0, -1); -+} -+ - struct sk_buff *__alloc_skb_head(gfp_t priority, int node); - static inline struct sk_buff *alloc_skb_head(gfp_t priority) - { ---- a/net/core/skbuff.c -+++ b/net/core/skbuff.c -@@ -283,6 +283,90 @@ nodata: - EXPORT_SYMBOL(__alloc_skb); - - /** -+ * __alloc_skb_header - allocate a network buffer -+ * @size: size to allocate -+ * @gfp_mask: allocation mask -+ * @fclone: allocate from fclone cache instead of head cache -+ * and allocate a cloned (child) skb -+ * -+ * Allocate a new &sk_buff. The returned buffer has no headroom and a -+ * tail room of size bytes. The object has a reference count of one. -+ * The return is the buffer. On a failure the return is %NULL. -+ * -+ * Buffers may only be allocated from interrupts using a @gfp_mask of -+ * %GFP_ATOMIC. -+ */ -+struct sk_buff *__alloc_skb_header(unsigned int size, void *data, -+ gfp_t gfp_mask, int fclone, int node) -+{ -+ struct kmem_cache *cache; -+ struct skb_shared_info *shinfo; -+ struct sk_buff *skb; -+ -+ cache = fclone ? skbuff_fclone_cache : skbuff_head_cache; -+ -+ if (size <= SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) { -+ skb = NULL; -+ goto out; -+ } -+ -+ /* Get the HEAD */ -+ skb = kmem_cache_alloc_node(cache, gfp_mask & ~__GFP_DMA, node); -+ if (!skb) -+ goto out; -+ prefetchw(skb); -+ -+ /* kmalloc might give us more room than requested. -+ * Put skb_shared_info exactly at the end of allocated zone, -+ * to allow max possible filling before reallocation. -+ */ -+ size = SKB_WITH_OVERHEAD(ksize(data)); -+ prefetchw(data + size); -+ -+ /* Only clear those fields we need to clear, not those that we will -+ * actually initialise below. Hence, don't put any more fields after -+ * the tail pointer in struct sk_buff! -+ */ -+ memset(skb, 0, offsetof(struct sk_buff, tail)); -+ /* Account for allocated memory : skb + skb->head */ -+ skb->truesize = SKB_TRUESIZE(size); -+ atomic_set(&skb->users, 1); -+ skb->head = data; -+ skb->data = data; -+ skb_reset_tail_pointer(skb); -+ skb->end = skb->tail + size; -+#ifdef NET_SKBUFF_DATA_USES_OFFSET -+ skb->mac_header = ~0U; -+#endif -+ -+#if defined(CONFIG_COMCERTO_CUSTOM_SKB_LAYOUT) -+ skb->mspd_data = NULL; -+ skb->mspd_len = 0; -+#endif -+ -+ /* make sure we initialize shinfo sequentially */ -+ shinfo = skb_shinfo(skb); -+ memset(shinfo, 0, offsetof(struct skb_shared_info, dataref)); -+ atomic_set(&shinfo->dataref, 1); -+ kmemcheck_annotate_variable(shinfo->destructor_arg); -+ -+ if (fclone) { -+ struct sk_buff *child = skb + 1; -+ atomic_t *fclone_ref = (atomic_t *)(child + 1); -+ -+ kmemcheck_annotate_bitfield(child, flags1); -+ kmemcheck_annotate_bitfield(child, flags2); -+ skb->fclone = SKB_FCLONE_ORIG; -+ atomic_set(fclone_ref, 1); -+ -+ child->fclone = SKB_FCLONE_UNAVAILABLE; -+ } -+out: -+ return skb; -+} -+EXPORT_SYMBOL(__alloc_skb_header); -+ -+/** - * __build_skb - build a network buffer - * @data: data buffer provided by caller - * @frag_size: size of data, or 0 if head was kmalloced diff --git a/target/linux/layerscape/patches-4.4/7126-net-phy-add-driver-for-aquantia-AQR106-107-phy.patch b/target/linux/layerscape/patches-4.4/7126-net-phy-add-driver-for-aquantia-AQR106-107-phy.patch deleted file mode 100644 index 474982c2cc..0000000000 --- a/target/linux/layerscape/patches-4.4/7126-net-phy-add-driver-for-aquantia-AQR106-107-phy.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 637a6e183edf302111b28461c0c98b9634b30437 Mon Sep 17 00:00:00 2001 -From: Mingkai Hu -Date: Fri, 1 Apr 2016 17:11:10 +0800 -Subject: [PATCH 126/141] net: phy: add driver for aquantia AQR106/107 phy - -Signed-off-by: Mingkai Hu ---- - drivers/net/phy/aquantia.c | 30 ++++++++++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - ---- a/drivers/net/phy/aquantia.c -+++ b/drivers/net/phy/aquantia.c -@@ -21,6 +21,8 @@ - #define PHY_ID_AQ1202 0x03a1b445 - #define PHY_ID_AQ2104 0x03a1b460 - #define PHY_ID_AQR105 0x03a1b4a2 -+#define PHY_ID_AQR106 0x03a1b4d0 -+#define PHY_ID_AQR107 0x03a1b4e0 - #define PHY_ID_AQR405 0x03a1b4b0 - - #define PHY_AQUANTIA_FEATURES (SUPPORTED_10000baseT_Full | \ -@@ -157,6 +159,32 @@ static struct phy_driver aquantia_driver - .driver = { .owner = THIS_MODULE,}, - }, - { -+ .phy_id = PHY_ID_AQR106, -+ .phy_id_mask = 0xfffffff0, -+ .name = "Aquantia AQR106", -+ .features = PHY_AQUANTIA_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+ .aneg_done = aquantia_aneg_done, -+ .config_aneg = aquantia_config_aneg, -+ .config_intr = aquantia_config_intr, -+ .ack_interrupt = aquantia_ack_interrupt, -+ .read_status = aquantia_read_status, -+ .driver = { .owner = THIS_MODULE,}, -+}, -+{ -+ .phy_id = PHY_ID_AQR107, -+ .phy_id_mask = 0xfffffff0, -+ .name = "Aquantia AQR107", -+ .features = PHY_AQUANTIA_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, -+ .aneg_done = aquantia_aneg_done, -+ .config_aneg = aquantia_config_aneg, -+ .config_intr = aquantia_config_intr, -+ .ack_interrupt = aquantia_ack_interrupt, -+ .read_status = aquantia_read_status, -+ .driver = { .owner = THIS_MODULE,}, -+}, -+{ - .phy_id = PHY_ID_AQR405, - .phy_id_mask = 0xfffffff0, - .name = "Aquantia AQR405", -@@ -177,6 +205,8 @@ static struct mdio_device_id __maybe_unu - { PHY_ID_AQ1202, 0xfffffff0 }, - { PHY_ID_AQ2104, 0xfffffff0 }, - { PHY_ID_AQR105, 0xfffffff0 }, -+ { PHY_ID_AQR106, 0xfffffff0 }, -+ { PHY_ID_AQR107, 0xfffffff0 }, - { PHY_ID_AQR405, 0xfffffff0 }, - { } - }; diff --git a/target/linux/layerscape/patches-4.4/7144-dpaa-call-arch_setup_dma_ops-before-using-dma_ops.patch b/target/linux/layerscape/patches-4.4/7144-dpaa-call-arch_setup_dma_ops-before-using-dma_ops.patch deleted file mode 100644 index ef8cf01b47..0000000000 --- a/target/linux/layerscape/patches-4.4/7144-dpaa-call-arch_setup_dma_ops-before-using-dma_ops.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 0ac69de37277aec31d18a8c7b9d9a3a65b629526 Mon Sep 17 00:00:00 2001 -From: Yangbo Lu -Date: Wed, 12 Oct 2016 16:30:57 +0800 -Subject: [PATCH 144/226] dpaa: call arch_setup_dma_ops before using dma_ops - -A previous patch caused dpaa call trace. This patch provides -a temporary workaround for this until this is fixed by upstream. - -Fixes: 1dccb598df54 ("arm64: simplify dma_get_ops") -Signed-off-by: Yangbo Lu ---- - .../ethernet/freescale/sdk_dpaa/dpaa_eth_common.c | 12 ++++++------ - drivers/staging/fsl_qbman/qman_high.c | 1 + - 2 files changed, 7 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_common.c -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_common.c -@@ -754,6 +754,12 @@ dpa_bp_alloc(struct dpa_bp *dpa_bp) - goto pdev_register_failed; - } - -+#ifdef CONFIG_FMAN_ARM -+ /* force coherency */ -+ pdev->dev.archdata.dma_coherent = true; -+ arch_setup_dma_ops(&pdev->dev, 0, 0, NULL, true); -+#endif -+ - err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(40)); - if (err) - goto pdev_mask_failed; -@@ -765,12 +771,6 @@ dpa_bp_alloc(struct dpa_bp *dpa_bp) - goto pdev_mask_failed; - } - --#ifdef CONFIG_FMAN_ARM -- /* force coherency */ -- pdev->dev.archdata.dma_coherent = true; -- arch_setup_dma_ops(&pdev->dev, 0, 0, NULL, true); --#endif -- - dpa_bp->dev = &pdev->dev; - - if (dpa_bp->seed_cb) { ---- a/drivers/staging/fsl_qbman/qman_high.c -+++ b/drivers/staging/fsl_qbman/qman_high.c -@@ -662,6 +662,7 @@ struct qman_portal *qman_create_portal( - portal->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(40); - portal->pdev->dev.dma_mask = &portal->pdev->dev.coherent_dma_mask; - #else -+ arch_setup_dma_ops(&portal->pdev->dev, 0, 0, NULL, false); - if (dma_set_mask(&portal->pdev->dev, DMA_BIT_MASK(40))) { - pr_err("qman_portal - dma_set_mask() failed\n"); - goto fail_devadd; diff --git a/target/linux/layerscape/patches-4.4/7145-staging-fsl-mc-Added-generic-MSI-support-for-FSL-MC-.patch b/target/linux/layerscape/patches-4.4/7145-staging-fsl-mc-Added-generic-MSI-support-for-FSL-MC-.patch deleted file mode 100644 index 1f3a9f0506..0000000000 --- a/target/linux/layerscape/patches-4.4/7145-staging-fsl-mc-Added-generic-MSI-support-for-FSL-MC-.patch +++ /dev/null @@ -1,400 +0,0 @@ -From 8ebb892cd56d14e72580ab36c3b5eb2d4603a7fe Mon Sep 17 00:00:00 2001 -From: "J. German Rivera" -Date: Wed, 6 Jan 2016 16:03:21 -0600 -Subject: [PATCH 145/226] staging: fsl-mc: Added generic MSI support for - FSL-MC devices - -Created an MSI domain for the fsl-mc bus-- including functions -to create a domain, find a domain, alloc/free domain irqs, and -bus specific overrides for domain and irq_chip ops. - -Signed-off-by: J. German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/Kconfig | 1 + - drivers/staging/fsl-mc/bus/Makefile | 1 + - drivers/staging/fsl-mc/bus/mc-msi.c | 276 +++++++++++++++++++++++++++ - drivers/staging/fsl-mc/include/dprc.h | 2 +- - drivers/staging/fsl-mc/include/mc-private.h | 17 ++ - drivers/staging/fsl-mc/include/mc.h | 17 ++ - 6 files changed, 313 insertions(+), 1 deletion(-) - create mode 100644 drivers/staging/fsl-mc/bus/mc-msi.c - ---- a/drivers/staging/fsl-mc/bus/Kconfig -+++ b/drivers/staging/fsl-mc/bus/Kconfig -@@ -9,6 +9,7 @@ - config FSL_MC_BUS - tristate "Freescale Management Complex (MC) bus driver" - depends on OF && ARM64 -+ select GENERIC_MSI_IRQ_DOMAIN - help - Driver to enable the bus infrastructure for the Freescale - QorIQ Management Complex (fsl-mc). The fsl-mc is a hardware ---- a/drivers/staging/fsl-mc/bus/Makefile -+++ b/drivers/staging/fsl-mc/bus/Makefile -@@ -13,5 +13,6 @@ mc-bus-driver-objs := mc-bus.o \ - dpmng.o \ - dprc-driver.o \ - mc-allocator.o \ -+ mc-msi.o \ - dpmcp.o \ - dpbp.o ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/mc-msi.c -@@ -0,0 +1,276 @@ -+/* -+ * Freescale Management Complex (MC) bus driver MSI support -+ * -+ * Copyright (C) 2015 Freescale Semiconductor, Inc. -+ * Author: German Rivera -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include "../include/mc-private.h" -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "../include/mc-sys.h" -+#include "dprc-cmd.h" -+ -+static void fsl_mc_msi_set_desc(msi_alloc_info_t *arg, -+ struct msi_desc *desc) -+{ -+ arg->desc = desc; -+ arg->hwirq = (irq_hw_number_t)desc->fsl_mc.msi_index; -+} -+ -+static void fsl_mc_msi_update_dom_ops(struct msi_domain_info *info) -+{ -+ struct msi_domain_ops *ops = info->ops; -+ -+ if (WARN_ON(!ops)) -+ return; -+ -+ /* -+ * set_desc should not be set by the caller -+ */ -+ if (WARN_ON(ops->set_desc)) -+ return; -+ -+ ops->set_desc = fsl_mc_msi_set_desc; -+} -+ -+static void __fsl_mc_msi_write_msg(struct fsl_mc_device *mc_bus_dev, -+ struct fsl_mc_device_irq *mc_dev_irq) -+{ -+ int error; -+ struct fsl_mc_device *owner_mc_dev = mc_dev_irq->mc_dev; -+ struct msi_desc *msi_desc = mc_dev_irq->msi_desc; -+ struct dprc_irq_cfg irq_cfg; -+ -+ /* -+ * msi_desc->msg.address is 0x0 when this function is invoked in -+ * the free_irq() code path. In this case, for the MC, we don't -+ * really need to "unprogram" the MSI, so we just return. -+ */ -+ if (msi_desc->msg.address_lo == 0x0 && msi_desc->msg.address_hi == 0x0) -+ return; -+ -+ if (WARN_ON(!owner_mc_dev)) -+ return; -+ -+ irq_cfg.paddr = ((u64)msi_desc->msg.address_hi << 32) | -+ msi_desc->msg.address_lo; -+ irq_cfg.val = msi_desc->msg.data; -+ irq_cfg.user_irq_id = msi_desc->irq; -+ -+ if (owner_mc_dev == mc_bus_dev) { -+ /* -+ * IRQ is for the mc_bus_dev's DPRC itself -+ */ -+ error = dprc_set_irq(mc_bus_dev->mc_io, -+ MC_CMD_FLAG_INTR_DIS | MC_CMD_FLAG_PRI, -+ mc_bus_dev->mc_handle, -+ mc_dev_irq->dev_irq_index, -+ &irq_cfg); -+ if (error < 0) { -+ dev_err(&owner_mc_dev->dev, -+ "dprc_set_irq() failed: %d\n", error); -+ } -+ } else { -+ /* -+ * IRQ is for for a child device of mc_bus_dev -+ */ -+ error = dprc_set_obj_irq(mc_bus_dev->mc_io, -+ MC_CMD_FLAG_INTR_DIS | MC_CMD_FLAG_PRI, -+ mc_bus_dev->mc_handle, -+ owner_mc_dev->obj_desc.type, -+ owner_mc_dev->obj_desc.id, -+ mc_dev_irq->dev_irq_index, -+ &irq_cfg); -+ if (error < 0) { -+ dev_err(&owner_mc_dev->dev, -+ "dprc_obj_set_irq() failed: %d\n", error); -+ } -+ } -+} -+ -+/* -+ * NOTE: This function is invoked with interrupts disabled -+ */ -+static void fsl_mc_msi_write_msg(struct irq_data *irq_data, -+ struct msi_msg *msg) -+{ -+ struct msi_desc *msi_desc = irq_data_get_msi_desc(irq_data); -+ struct fsl_mc_device *mc_bus_dev = to_fsl_mc_device(msi_desc->dev); -+ struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); -+ struct fsl_mc_device_irq *mc_dev_irq = -+ &mc_bus->irq_resources[msi_desc->fsl_mc.msi_index]; -+ -+ WARN_ON(mc_dev_irq->msi_desc != msi_desc); -+ msi_desc->msg = *msg; -+ -+ /* -+ * Program the MSI (paddr, value) pair in the device: -+ */ -+ __fsl_mc_msi_write_msg(mc_bus_dev, mc_dev_irq); -+} -+ -+static void fsl_mc_msi_update_chip_ops(struct msi_domain_info *info) -+{ -+ struct irq_chip *chip = info->chip; -+ -+ if (WARN_ON((!chip))) -+ return; -+ -+ /* -+ * irq_write_msi_msg should not be set by the caller -+ */ -+ if (WARN_ON(chip->irq_write_msi_msg)) -+ return; -+ -+ chip->irq_write_msi_msg = fsl_mc_msi_write_msg; -+} -+ -+/** -+ * fsl_mc_msi_create_irq_domain - Create a fsl-mc MSI interrupt domain -+ * @np: Optional device-tree node of the interrupt controller -+ * @info: MSI domain info -+ * @parent: Parent irq domain -+ * -+ * Updates the domain and chip ops and creates a fsl-mc MSI -+ * interrupt domain. -+ * -+ * Returns: -+ * A domain pointer or NULL in case of failure. -+ */ -+struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode, -+ struct msi_domain_info *info, -+ struct irq_domain *parent) -+{ -+ struct irq_domain *domain; -+ -+ if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) -+ fsl_mc_msi_update_dom_ops(info); -+ if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) -+ fsl_mc_msi_update_chip_ops(info); -+ -+ domain = msi_create_irq_domain(fwnode, info, parent); -+ if (domain) -+ domain->bus_token = DOMAIN_BUS_FSL_MC_MSI; -+ -+ return domain; -+} -+ -+int fsl_mc_find_msi_domain(struct device *mc_platform_dev, -+ struct irq_domain **mc_msi_domain) -+{ -+ struct irq_domain *msi_domain; -+ struct device_node *mc_of_node = mc_platform_dev->of_node; -+ -+ msi_domain = of_msi_get_domain(mc_platform_dev, mc_of_node, -+ DOMAIN_BUS_FSL_MC_MSI); -+ if (!msi_domain) { -+ pr_err("Unable to find fsl-mc MSI domain for %s\n", -+ mc_of_node->full_name); -+ -+ return -ENOENT; -+ } -+ -+ *mc_msi_domain = msi_domain; -+ return 0; -+} -+ -+static void fsl_mc_msi_free_descs(struct device *dev) -+{ -+ struct msi_desc *desc, *tmp; -+ -+ list_for_each_entry_safe(desc, tmp, dev_to_msi_list(dev), list) { -+ list_del(&desc->list); -+ free_msi_entry(desc); -+ } -+} -+ -+static int fsl_mc_msi_alloc_descs(struct device *dev, unsigned int irq_count) -+ -+{ -+ unsigned int i; -+ int error; -+ struct msi_desc *msi_desc; -+ -+ for (i = 0; i < irq_count; i++) { -+ msi_desc = alloc_msi_entry(dev); -+ if (!msi_desc) { -+ dev_err(dev, "Failed to allocate msi entry\n"); -+ error = -ENOMEM; -+ goto cleanup_msi_descs; -+ } -+ -+ msi_desc->fsl_mc.msi_index = i; -+ msi_desc->nvec_used = 1; -+ INIT_LIST_HEAD(&msi_desc->list); -+ list_add_tail(&msi_desc->list, dev_to_msi_list(dev)); -+ } -+ -+ return 0; -+ -+cleanup_msi_descs: -+ fsl_mc_msi_free_descs(dev); -+ return error; -+} -+ -+int fsl_mc_msi_domain_alloc_irqs(struct device *dev, -+ unsigned int irq_count) -+{ -+ struct irq_domain *msi_domain; -+ int error; -+ -+ if (WARN_ON(!list_empty(dev_to_msi_list(dev)))) -+ return -EINVAL; -+ -+ error = fsl_mc_msi_alloc_descs(dev, irq_count); -+ if (error < 0) -+ return error; -+ -+ msi_domain = dev_get_msi_domain(dev); -+ if (WARN_ON(!msi_domain)) { -+ error = -EINVAL; -+ goto cleanup_msi_descs; -+ } -+ -+ /* -+ * NOTE: Calling this function will trigger the invocation of the -+ * its_fsl_mc_msi_prepare() callback -+ */ -+ error = msi_domain_alloc_irqs(msi_domain, dev, irq_count); -+ -+ if (error) { -+ dev_err(dev, "Failed to allocate IRQs\n"); -+ goto cleanup_msi_descs; -+ } -+ -+ return 0; -+ -+cleanup_msi_descs: -+ fsl_mc_msi_free_descs(dev); -+ return error; -+} -+ -+void fsl_mc_msi_domain_free_irqs(struct device *dev) -+{ -+ struct irq_domain *msi_domain; -+ -+ msi_domain = dev_get_msi_domain(dev); -+ if (WARN_ON(!msi_domain)) -+ return; -+ -+ msi_domain_free_irqs(msi_domain, dev); -+ -+ if (WARN_ON(list_empty(dev_to_msi_list(dev)))) -+ return; -+ -+ fsl_mc_msi_free_descs(dev); -+} ---- a/drivers/staging/fsl-mc/include/dprc.h -+++ b/drivers/staging/fsl-mc/include/dprc.h -@@ -176,7 +176,7 @@ int dprc_reset_container(struct fsl_mc_i - * @user_irq_id: A user defined number associated with this IRQ - */ - struct dprc_irq_cfg { -- u64 paddr; -+ phys_addr_t paddr; - u32 val; - int user_irq_id; - }; ---- a/drivers/staging/fsl-mc/include/mc-private.h -+++ b/drivers/staging/fsl-mc/include/mc-private.h -@@ -26,6 +26,9 @@ - strcmp(_obj_type, "dpmcp") == 0 || \ - strcmp(_obj_type, "dpcon") == 0) - -+struct irq_domain; -+struct msi_domain_info; -+ - /** - * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device - * @root_mc_bus_dev: MC object device representing the root DPRC -@@ -79,11 +82,13 @@ struct fsl_mc_resource_pool { - * @resource_pools: array of resource pools (one pool per resource type) - * for this MC bus. These resources represent allocatable entities - * from the physical DPRC. -+ * @irq_resources: Pointer to array of IRQ objects for the IRQ pool - * @scan_mutex: Serializes bus scanning - */ - struct fsl_mc_bus { - struct fsl_mc_device mc_dev; - struct fsl_mc_resource_pool resource_pools[FSL_MC_NUM_POOL_TYPES]; -+ struct fsl_mc_device_irq *irq_resources; - struct mutex scan_mutex; /* serializes bus scanning */ - }; - -@@ -116,4 +121,16 @@ int __must_check fsl_mc_resource_allocat - - void fsl_mc_resource_free(struct fsl_mc_resource *resource); - -+struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode, -+ struct msi_domain_info *info, -+ struct irq_domain *parent); -+ -+int fsl_mc_find_msi_domain(struct device *mc_platform_dev, -+ struct irq_domain **mc_msi_domain); -+ -+int fsl_mc_msi_domain_alloc_irqs(struct device *dev, -+ unsigned int irq_count); -+ -+void fsl_mc_msi_domain_free_irqs(struct device *dev); -+ - #endif /* _FSL_MC_PRIVATE_H_ */ ---- a/drivers/staging/fsl-mc/include/mc.h -+++ b/drivers/staging/fsl-mc/include/mc.h -@@ -104,6 +104,23 @@ struct fsl_mc_resource { - }; - - /** -+ * struct fsl_mc_device_irq - MC object device message-based interrupt -+ * @msi_desc: pointer to MSI descriptor allocated by fsl_mc_msi_alloc_descs() -+ * @mc_dev: MC object device that owns this interrupt -+ * @dev_irq_index: device-relative IRQ index -+ * @resource: MC generic resource associated with the interrupt -+ */ -+struct fsl_mc_device_irq { -+ struct msi_desc *msi_desc; -+ struct fsl_mc_device *mc_dev; -+ u8 dev_irq_index; -+ struct fsl_mc_resource resource; -+}; -+ -+#define to_fsl_mc_irq(_mc_resource) \ -+ container_of(_mc_resource, struct fsl_mc_device_irq, resource) -+ -+/** - * Bit masks for a MC object device (struct fsl_mc_device) flags - */ - #define FSL_MC_IS_DPRC 0x0001 diff --git a/target/linux/layerscape/patches-4.4/7146-staging-fsl-mc-Added-GICv3-ITS-support-for-FSL-MC-MS.patch b/target/linux/layerscape/patches-4.4/7146-staging-fsl-mc-Added-GICv3-ITS-support-for-FSL-MC-MS.patch deleted file mode 100644 index 5b254d70d2..0000000000 --- a/target/linux/layerscape/patches-4.4/7146-staging-fsl-mc-Added-GICv3-ITS-support-for-FSL-MC-MS.patch +++ /dev/null @@ -1,167 +0,0 @@ -From 85cb8ae26b6c69f0a118f32b7b7cd4f22d782da3 Mon Sep 17 00:00:00 2001 -From: "J. German Rivera" -Date: Wed, 6 Jan 2016 16:03:22 -0600 -Subject: [PATCH 146/226] staging: fsl-mc: Added GICv3-ITS support for FSL-MC - MSIs - -Added platform-specific MSI support layer for FSL-MC devices. - -Signed-off-by: J. German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/Makefile | 1 + - .../staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c | 127 ++++++++++++++++++++ - drivers/staging/fsl-mc/include/mc-private.h | 4 + - 3 files changed, 132 insertions(+) - create mode 100644 drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c - ---- a/drivers/staging/fsl-mc/bus/Makefile -+++ b/drivers/staging/fsl-mc/bus/Makefile -@@ -14,5 +14,6 @@ mc-bus-driver-objs := mc-bus.o \ - dprc-driver.o \ - mc-allocator.o \ - mc-msi.o \ -+ irq-gic-v3-its-fsl-mc-msi.o \ - dpmcp.o \ - dpbp.o ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c -@@ -0,0 +1,127 @@ -+/* -+ * Freescale Management Complex (MC) bus driver MSI support -+ * -+ * Copyright (C) 2015 Freescale Semiconductor, Inc. -+ * Author: German Rivera -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include "../include/mc-private.h" -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "../include/mc-sys.h" -+#include "dprc-cmd.h" -+ -+static struct irq_chip its_msi_irq_chip = { -+ .name = "fsl-mc-bus-msi", -+ .irq_mask = irq_chip_mask_parent, -+ .irq_unmask = irq_chip_unmask_parent, -+ .irq_eoi = irq_chip_eoi_parent, -+ .irq_set_affinity = msi_domain_set_affinity -+}; -+ -+static int its_fsl_mc_msi_prepare(struct irq_domain *msi_domain, -+ struct device *dev, -+ int nvec, msi_alloc_info_t *info) -+{ -+ struct fsl_mc_device *mc_bus_dev; -+ struct msi_domain_info *msi_info; -+ -+ if (WARN_ON(dev->bus != &fsl_mc_bus_type)) -+ return -EINVAL; -+ -+ mc_bus_dev = to_fsl_mc_device(dev); -+ if (WARN_ON(!(mc_bus_dev->flags & FSL_MC_IS_DPRC))) -+ return -EINVAL; -+ -+ /* -+ * Set the device Id to be passed to the GIC-ITS: -+ * -+ * NOTE: This device id corresponds to the IOMMU stream ID -+ * associated with the DPRC object (ICID). -+ */ -+ info->scratchpad[0].ul = mc_bus_dev->icid; -+ msi_info = msi_get_domain_info(msi_domain->parent); -+ return msi_info->ops->msi_prepare(msi_domain->parent, dev, nvec, info); -+} -+ -+static struct msi_domain_ops its_fsl_mc_msi_ops = { -+ .msi_prepare = its_fsl_mc_msi_prepare, -+}; -+ -+static struct msi_domain_info its_fsl_mc_msi_domain_info = { -+ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), -+ .ops = &its_fsl_mc_msi_ops, -+ .chip = &its_msi_irq_chip, -+}; -+ -+static const struct of_device_id its_device_id[] = { -+ { .compatible = "arm,gic-v3-its", }, -+ {}, -+}; -+ -+int __init its_fsl_mc_msi_init(void) -+{ -+ struct device_node *np; -+ struct irq_domain *parent; -+ struct irq_domain *mc_msi_domain; -+ -+ for (np = of_find_matching_node(NULL, its_device_id); np; -+ np = of_find_matching_node(np, its_device_id)) { -+ if (!of_property_read_bool(np, "msi-controller")) -+ continue; -+ -+ parent = irq_find_matching_host(np, DOMAIN_BUS_NEXUS); -+ if (!parent || !msi_get_domain_info(parent)) { -+ pr_err("%s: unable to locate ITS domain\n", -+ np->full_name); -+ continue; -+ } -+ -+ mc_msi_domain = fsl_mc_msi_create_irq_domain( -+ of_node_to_fwnode(np), -+ &its_fsl_mc_msi_domain_info, -+ parent); -+ if (!mc_msi_domain) { -+ pr_err("%s: unable to create fsl-mc domain\n", -+ np->full_name); -+ continue; -+ } -+ -+ WARN_ON(mc_msi_domain-> -+ host_data != &its_fsl_mc_msi_domain_info); -+ -+ pr_info("fsl-mc MSI: %s domain created\n", np->full_name); -+ } -+ -+ return 0; -+} -+ -+void its_fsl_mc_msi_cleanup(void) -+{ -+ struct device_node *np; -+ -+ for (np = of_find_matching_node(NULL, its_device_id); np; -+ np = of_find_matching_node(np, its_device_id)) { -+ struct irq_domain *mc_msi_domain = irq_find_matching_host( -+ np, -+ DOMAIN_BUS_FSL_MC_MSI); -+ -+ if (!of_property_read_bool(np, "msi-controller")) -+ continue; -+ -+ mc_msi_domain = irq_find_matching_host(np, -+ DOMAIN_BUS_FSL_MC_MSI); -+ if (mc_msi_domain && -+ mc_msi_domain->host_data == &its_fsl_mc_msi_domain_info) -+ irq_domain_remove(mc_msi_domain); -+ } -+} ---- a/drivers/staging/fsl-mc/include/mc-private.h -+++ b/drivers/staging/fsl-mc/include/mc-private.h -@@ -133,4 +133,8 @@ int fsl_mc_msi_domain_alloc_irqs(struct - - void fsl_mc_msi_domain_free_irqs(struct device *dev); - -+int __init its_fsl_mc_msi_init(void); -+ -+void its_fsl_mc_msi_cleanup(void); -+ - #endif /* _FSL_MC_PRIVATE_H_ */ diff --git a/target/linux/layerscape/patches-4.4/7147-staging-fsl-mc-Extended-MC-bus-allocator-to-include-.patch b/target/linux/layerscape/patches-4.4/7147-staging-fsl-mc-Extended-MC-bus-allocator-to-include-.patch deleted file mode 100644 index c02c892b21..0000000000 --- a/target/linux/layerscape/patches-4.4/7147-staging-fsl-mc-Extended-MC-bus-allocator-to-include-.patch +++ /dev/null @@ -1,326 +0,0 @@ -From 23b09c6b4162a8264b600f35d7048256a7afc0cd Mon Sep 17 00:00:00 2001 -From: "J. German Rivera" -Date: Wed, 6 Jan 2016 16:03:23 -0600 -Subject: [PATCH 147/226] staging: fsl-mc: Extended MC bus allocator to - include IRQs - -All the IRQs for DPAA2 objects in the same DPRC must use -the ICID of that DPRC, as their device Id in the GIC-ITS. -Thus, all these IRQs must share the same ITT table in the GIC. -As a result, a pool of IRQs with the same device Id must be -preallocated per DPRC (fsl-mc bus instance). So, the fsl-mc -bus object allocator is extended to also provide services -to allocate IRQs to DPAA2 devices, from their parent fsl-mc bus -IRQ pool. - -Signed-off-by: J. German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-allocator.c | 199 +++++++++++++++++++++++++++ - drivers/staging/fsl-mc/include/mc-private.h | 15 ++ - drivers/staging/fsl-mc/include/mc.h | 9 ++ - 3 files changed, 223 insertions(+) - ---- a/drivers/staging/fsl-mc/bus/mc-allocator.c -+++ b/drivers/staging/fsl-mc/bus/mc-allocator.c -@@ -15,6 +15,7 @@ - #include "../include/dpcon-cmd.h" - #include "dpmcp-cmd.h" - #include "dpmcp.h" -+#include - - /** - * fsl_mc_resource_pool_add_device - add allocatable device to a resource -@@ -160,6 +161,7 @@ static const char *const fsl_mc_pool_typ - [FSL_MC_POOL_DPMCP] = "dpmcp", - [FSL_MC_POOL_DPBP] = "dpbp", - [FSL_MC_POOL_DPCON] = "dpcon", -+ [FSL_MC_POOL_IRQ] = "irq", - }; - - static int __must_check object_type_to_pool_type(const char *object_type, -@@ -465,6 +467,203 @@ void fsl_mc_object_free(struct fsl_mc_de - } - EXPORT_SYMBOL_GPL(fsl_mc_object_free); - -+/* -+ * Initialize the interrupt pool associated with a MC bus. -+ * It allocates a block of IRQs from the GIC-ITS -+ */ -+int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus, -+ unsigned int irq_count) -+{ -+ unsigned int i; -+ struct msi_desc *msi_desc; -+ struct fsl_mc_device_irq *irq_resources; -+ struct fsl_mc_device_irq *mc_dev_irq; -+ int error; -+ struct fsl_mc_device *mc_bus_dev = &mc_bus->mc_dev; -+ struct fsl_mc_resource_pool *res_pool = -+ &mc_bus->resource_pools[FSL_MC_POOL_IRQ]; -+ -+ if (WARN_ON(irq_count == 0 || -+ irq_count > FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS)) -+ return -EINVAL; -+ -+ error = fsl_mc_msi_domain_alloc_irqs(&mc_bus_dev->dev, irq_count); -+ if (error < 0) -+ return error; -+ -+ irq_resources = devm_kzalloc(&mc_bus_dev->dev, -+ sizeof(*irq_resources) * irq_count, -+ GFP_KERNEL); -+ if (!irq_resources) { -+ error = -ENOMEM; -+ goto cleanup_msi_irqs; -+ } -+ -+ for (i = 0; i < irq_count; i++) { -+ mc_dev_irq = &irq_resources[i]; -+ -+ /* -+ * NOTE: This mc_dev_irq's MSI addr/value pair will be set -+ * by the fsl_mc_msi_write_msg() callback -+ */ -+ mc_dev_irq->resource.type = res_pool->type; -+ mc_dev_irq->resource.data = mc_dev_irq; -+ mc_dev_irq->resource.parent_pool = res_pool; -+ INIT_LIST_HEAD(&mc_dev_irq->resource.node); -+ list_add_tail(&mc_dev_irq->resource.node, &res_pool->free_list); -+ } -+ -+ for_each_msi_entry(msi_desc, &mc_bus_dev->dev) { -+ mc_dev_irq = &irq_resources[msi_desc->fsl_mc.msi_index]; -+ mc_dev_irq->msi_desc = msi_desc; -+ mc_dev_irq->resource.id = msi_desc->irq; -+ } -+ -+ res_pool->max_count = irq_count; -+ res_pool->free_count = irq_count; -+ mc_bus->irq_resources = irq_resources; -+ return 0; -+ -+cleanup_msi_irqs: -+ fsl_mc_msi_domain_free_irqs(&mc_bus_dev->dev); -+ return error; -+} -+EXPORT_SYMBOL_GPL(fsl_mc_populate_irq_pool); -+ -+/** -+ * Teardown the interrupt pool associated with an MC bus. -+ * It frees the IRQs that were allocated to the pool, back to the GIC-ITS. -+ */ -+void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus) -+{ -+ struct fsl_mc_device *mc_bus_dev = &mc_bus->mc_dev; -+ struct fsl_mc_resource_pool *res_pool = -+ &mc_bus->resource_pools[FSL_MC_POOL_IRQ]; -+ -+ if (WARN_ON(!mc_bus->irq_resources)) -+ return; -+ -+ if (WARN_ON(res_pool->max_count == 0)) -+ return; -+ -+ if (WARN_ON(res_pool->free_count != res_pool->max_count)) -+ return; -+ -+ INIT_LIST_HEAD(&res_pool->free_list); -+ res_pool->max_count = 0; -+ res_pool->free_count = 0; -+ mc_bus->irq_resources = NULL; -+ fsl_mc_msi_domain_free_irqs(&mc_bus_dev->dev); -+} -+EXPORT_SYMBOL_GPL(fsl_mc_cleanup_irq_pool); -+ -+/** -+ * It allocates the IRQs required by a given MC object device. The -+ * IRQs are allocated from the interrupt pool associated with the -+ * MC bus that contains the device, if the device is not a DPRC device. -+ * Otherwise, the IRQs are allocated from the interrupt pool associated -+ * with the MC bus that represents the DPRC device itself. -+ */ -+int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev) -+{ -+ int i; -+ int irq_count; -+ int res_allocated_count = 0; -+ int error = -EINVAL; -+ struct fsl_mc_device_irq **irqs = NULL; -+ struct fsl_mc_bus *mc_bus; -+ struct fsl_mc_resource_pool *res_pool; -+ -+ if (WARN_ON(mc_dev->irqs)) -+ return -EINVAL; -+ -+ irq_count = mc_dev->obj_desc.irq_count; -+ if (WARN_ON(irq_count == 0)) -+ return -EINVAL; -+ -+ if (strcmp(mc_dev->obj_desc.type, "dprc") == 0) -+ mc_bus = to_fsl_mc_bus(mc_dev); -+ else -+ mc_bus = to_fsl_mc_bus(to_fsl_mc_device(mc_dev->dev.parent)); -+ -+ if (WARN_ON(!mc_bus->irq_resources)) -+ return -EINVAL; -+ -+ res_pool = &mc_bus->resource_pools[FSL_MC_POOL_IRQ]; -+ if (res_pool->free_count < irq_count) { -+ dev_err(&mc_dev->dev, -+ "Not able to allocate %u irqs for device\n", irq_count); -+ return -ENOSPC; -+ } -+ -+ irqs = devm_kzalloc(&mc_dev->dev, irq_count * sizeof(irqs[0]), -+ GFP_KERNEL); -+ if (!irqs) -+ return -ENOMEM; -+ -+ for (i = 0; i < irq_count; i++) { -+ struct fsl_mc_resource *resource; -+ -+ error = fsl_mc_resource_allocate(mc_bus, FSL_MC_POOL_IRQ, -+ &resource); -+ if (error < 0) -+ goto error_resource_alloc; -+ -+ irqs[i] = to_fsl_mc_irq(resource); -+ res_allocated_count++; -+ -+ WARN_ON(irqs[i]->mc_dev); -+ irqs[i]->mc_dev = mc_dev; -+ irqs[i]->dev_irq_index = i; -+ } -+ -+ mc_dev->irqs = irqs; -+ return 0; -+ -+error_resource_alloc: -+ for (i = 0; i < res_allocated_count; i++) { -+ irqs[i]->mc_dev = NULL; -+ fsl_mc_resource_free(&irqs[i]->resource); -+ } -+ -+ return error; -+} -+EXPORT_SYMBOL_GPL(fsl_mc_allocate_irqs); -+ -+/* -+ * It frees the IRQs that were allocated for a MC object device, by -+ * returning them to the corresponding interrupt pool. -+ */ -+void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev) -+{ -+ int i; -+ int irq_count; -+ struct fsl_mc_bus *mc_bus; -+ struct fsl_mc_device_irq **irqs = mc_dev->irqs; -+ -+ if (WARN_ON(!irqs)) -+ return; -+ -+ irq_count = mc_dev->obj_desc.irq_count; -+ -+ if (strcmp(mc_dev->obj_desc.type, "dprc") == 0) -+ mc_bus = to_fsl_mc_bus(mc_dev); -+ else -+ mc_bus = to_fsl_mc_bus(to_fsl_mc_device(mc_dev->dev.parent)); -+ -+ if (WARN_ON(!mc_bus->irq_resources)) -+ return; -+ -+ for (i = 0; i < irq_count; i++) { -+ WARN_ON(!irqs[i]->mc_dev); -+ irqs[i]->mc_dev = NULL; -+ fsl_mc_resource_free(&irqs[i]->resource); -+ } -+ -+ mc_dev->irqs = NULL; -+} -+EXPORT_SYMBOL_GPL(fsl_mc_free_irqs); -+ - /** - * fsl_mc_allocator_probe - callback invoked when an allocatable device is - * being added to the system ---- a/drivers/staging/fsl-mc/include/mc-private.h -+++ b/drivers/staging/fsl-mc/include/mc-private.h -@@ -30,6 +30,16 @@ struct irq_domain; - struct msi_domain_info; - - /** -+ * Maximum number of total IRQs that can be pre-allocated for an MC bus' -+ * IRQ pool -+ */ -+#define FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS 256 -+ -+struct device_node; -+struct irq_domain; -+struct msi_domain_info; -+ -+/** - * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device - * @root_mc_bus_dev: MC object device representing the root DPRC - * @num_translation_ranges: number of entries in addr_translation_ranges -@@ -137,4 +147,9 @@ int __init its_fsl_mc_msi_init(void); - - void its_fsl_mc_msi_cleanup(void); - -+int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus, -+ unsigned int irq_count); -+ -+void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus); -+ - #endif /* _FSL_MC_PRIVATE_H_ */ ---- a/drivers/staging/fsl-mc/include/mc.h -+++ b/drivers/staging/fsl-mc/include/mc.h -@@ -14,12 +14,14 @@ - #include - #include - #include -+#include - #include "../include/dprc.h" - - #define FSL_MC_VENDOR_FREESCALE 0x1957 - - struct fsl_mc_device; - struct fsl_mc_io; -+struct fsl_mc_bus; - - /** - * struct fsl_mc_driver - MC object device driver object -@@ -75,6 +77,7 @@ enum fsl_mc_pool_type { - FSL_MC_POOL_DPMCP = 0x0, /* corresponds to "dpmcp" in the MC */ - FSL_MC_POOL_DPBP, /* corresponds to "dpbp" in the MC */ - FSL_MC_POOL_DPCON, /* corresponds to "dpcon" in the MC */ -+ FSL_MC_POOL_IRQ, - - /* - * NOTE: New resource pool types must be added before this entry -@@ -141,6 +144,7 @@ struct fsl_mc_device_irq { - * NULL if none. - * @obj_desc: MC description of the DPAA device - * @regions: pointer to array of MMIO region entries -+ * @irqs: pointer to array of pointers to interrupts allocated to this device - * @resource: generic resource associated with this MC object device, if any. - * - * Generic device object for MC object devices that are "attached" to a -@@ -172,6 +176,7 @@ struct fsl_mc_device { - struct fsl_mc_io *mc_io; - struct dprc_obj_desc obj_desc; - struct resource *regions; -+ struct fsl_mc_device_irq **irqs; - struct fsl_mc_resource *resource; - }; - -@@ -215,6 +220,10 @@ int __must_check fsl_mc_object_allocate( - - void fsl_mc_object_free(struct fsl_mc_device *mc_adev); - -+int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev); -+ -+void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev); -+ - extern struct bus_type fsl_mc_bus_type; - - #endif /* _FSL_MC_H_ */ diff --git a/target/linux/layerscape/patches-4.4/7148-staging-fsl-mc-Changed-DPRC-built-in-portal-s-mc_io-.patch b/target/linux/layerscape/patches-4.4/7148-staging-fsl-mc-Changed-DPRC-built-in-portal-s-mc_io-.patch deleted file mode 100644 index 17dcb75897..0000000000 --- a/target/linux/layerscape/patches-4.4/7148-staging-fsl-mc-Changed-DPRC-built-in-portal-s-mc_io-.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 0f2a65dea2024b7898e3c0b42e0a7864d6538567 Mon Sep 17 00:00:00 2001 -From: "J. German Rivera" -Date: Wed, 6 Jan 2016 16:03:24 -0600 -Subject: [PATCH 148/226] staging: fsl-mc: Changed DPRC built-in portal's - mc_io to be atomic - -The DPRC built-in portal's mc_io is used to send commands to the MC -to program MSIs for MC objects. This is done by the -fsl_mc_msi_write_msg() callback, which is invoked by the generic MSI -layer with interrupts disabled. As a result, the mc_io used in -fsl_mc_msi_write_msg needs to be an atomic mc_io. - -Signed-off-by: J. German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 4 +++- - drivers/staging/fsl-mc/bus/mc-bus.c | 3 ++- - 2 files changed, 5 insertions(+), 2 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -396,7 +396,9 @@ static int dprc_probe(struct fsl_mc_devi - error = fsl_create_mc_io(&mc_dev->dev, - mc_dev->regions[0].start, - region_size, -- NULL, 0, &mc_dev->mc_io); -+ NULL, -+ FSL_MC_IO_ATOMIC_CONTEXT_PORTAL, -+ &mc_dev->mc_io); - if (error < 0) - return error; - } ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -702,7 +702,8 @@ static int fsl_mc_bus_probe(struct platf - mc_portal_phys_addr = res.start; - mc_portal_size = resource_size(&res); - error = fsl_create_mc_io(&pdev->dev, mc_portal_phys_addr, -- mc_portal_size, NULL, 0, &mc_io); -+ mc_portal_size, NULL, -+ FSL_MC_IO_ATOMIC_CONTEXT_PORTAL, &mc_io); - if (error < 0) - return error; - diff --git a/target/linux/layerscape/patches-4.4/7149-staging-fsl-mc-Populate-the-IRQ-pool-for-an-MC-bus-i.patch b/target/linux/layerscape/patches-4.4/7149-staging-fsl-mc-Populate-the-IRQ-pool-for-an-MC-bus-i.patch deleted file mode 100644 index e72d5a7ef7..0000000000 --- a/target/linux/layerscape/patches-4.4/7149-staging-fsl-mc-Populate-the-IRQ-pool-for-an-MC-bus-i.patch +++ /dev/null @@ -1,109 +0,0 @@ -From 78ab7589777526022757e9c95b9d5864786eb4e5 Mon Sep 17 00:00:00 2001 -From: "J. German Rivera" -Date: Wed, 6 Jan 2016 16:03:25 -0600 -Subject: [PATCH 149/226] staging: fsl-mc: Populate the IRQ pool for an MC bus - instance - -Scan the corresponding DPRC container to get total count -of IRQs needed by all its child DPAA2 objects. Then, -preallocate a set of MSI IRQs with the DPRC's ICID -(GIT-ITS device Id) to populate the the DPRC's IRQ pool. -Each child DPAA2 object in the DPRC and the DPRC object itself -will allocate their necessary MSI IRQs from the DPRC's IRQ pool, -in their driver probe function. - -Signed-off-by: J. German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 24 ++++++++++++++++++++++-- - drivers/staging/fsl-mc/include/mc-private.h | 3 ++- - 2 files changed, 24 insertions(+), 3 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -241,6 +241,7 @@ static void dprc_cleanup_all_resource_po - * dprc_scan_objects - Discover objects in a DPRC - * - * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object -+ * @total_irq_count: total number of IRQs needed by objects in the DPRC. - * - * Detects objects added and removed from a DPRC and synchronizes the - * state of the Linux bus driver, MC by adding and removing -@@ -254,11 +255,13 @@ static void dprc_cleanup_all_resource_po - * populated before they can get allocation requests from probe callbacks - * of the device drivers for the non-allocatable devices. - */ --int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev) -+int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, -+ unsigned int *total_irq_count) - { - int num_child_objects; - int dprc_get_obj_failures; - int error; -+ unsigned int irq_count = mc_bus_dev->obj_desc.irq_count; - struct dprc_obj_desc *child_obj_desc_array = NULL; - - error = dprc_get_obj_count(mc_bus_dev->mc_io, -@@ -307,6 +310,7 @@ int dprc_scan_objects(struct fsl_mc_devi - continue; - } - -+ irq_count += obj_desc->irq_count; - dev_dbg(&mc_bus_dev->dev, - "Discovered object: type %s, id %d\n", - obj_desc->type, obj_desc->id); -@@ -319,6 +323,7 @@ int dprc_scan_objects(struct fsl_mc_devi - } - } - -+ *total_irq_count = irq_count; - dprc_remove_devices(mc_bus_dev, child_obj_desc_array, - num_child_objects); - -@@ -344,6 +349,7 @@ EXPORT_SYMBOL_GPL(dprc_scan_objects); - int dprc_scan_container(struct fsl_mc_device *mc_bus_dev) - { - int error; -+ unsigned int irq_count; - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); - - dprc_init_all_resource_pools(mc_bus_dev); -@@ -352,11 +358,25 @@ int dprc_scan_container(struct fsl_mc_de - * Discover objects in the DPRC: - */ - mutex_lock(&mc_bus->scan_mutex); -- error = dprc_scan_objects(mc_bus_dev); -+ error = dprc_scan_objects(mc_bus_dev, &irq_count); - mutex_unlock(&mc_bus->scan_mutex); - if (error < 0) - goto error; - -+ if (dev_get_msi_domain(&mc_bus_dev->dev) && !mc_bus->irq_resources) { -+ if (irq_count > FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS) { -+ dev_warn(&mc_bus_dev->dev, -+ "IRQs needed (%u) exceed IRQs preallocated (%u)\n", -+ irq_count, FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS); -+ } -+ -+ error = fsl_mc_populate_irq_pool( -+ mc_bus, -+ FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS); -+ if (error < 0) -+ goto error; -+ } -+ - return 0; - error: - dprc_cleanup_all_resource_pools(mc_bus_dev); ---- a/drivers/staging/fsl-mc/include/mc-private.h -+++ b/drivers/staging/fsl-mc/include/mc-private.h -@@ -114,7 +114,8 @@ void fsl_mc_device_remove(struct fsl_mc_ - - int dprc_scan_container(struct fsl_mc_device *mc_bus_dev); - --int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev); -+int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, -+ unsigned int *total_irq_count); - - int __init dprc_driver_init(void); - diff --git a/target/linux/layerscape/patches-4.4/7150-staging-fsl-mc-set-MSI-domain-for-DPRC-objects.patch b/target/linux/layerscape/patches-4.4/7150-staging-fsl-mc-set-MSI-domain-for-DPRC-objects.patch deleted file mode 100644 index 0c69783ad9..0000000000 --- a/target/linux/layerscape/patches-4.4/7150-staging-fsl-mc-set-MSI-domain-for-DPRC-objects.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 15bfab2641c61fb50a876860e8909ab84d2b8701 Mon Sep 17 00:00:00 2001 -From: "J. German Rivera" -Date: Wed, 6 Jan 2016 16:03:26 -0600 -Subject: [PATCH 150/226] staging: fsl-mc: set MSI domain for DPRC objects - -THE MSI domain associated with a root DPRC object is -obtained form the device tree. Child DPRCs inherit -the parent DPRC MSI domain. - -Signed-off-by: J. German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 39 ++++++++++++++++++++++++++++++ - 1 file changed, 39 insertions(+) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -13,6 +13,7 @@ - #include "../include/mc-sys.h" - #include - #include -+#include - #include "dprc-cmd.h" - - struct dprc_child_objs { -@@ -398,11 +399,16 @@ static int dprc_probe(struct fsl_mc_devi - { - int error; - size_t region_size; -+ struct device *parent_dev = mc_dev->dev.parent; - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); -+ bool msi_domain_set = false; - - if (WARN_ON(strcmp(mc_dev->obj_desc.type, "dprc") != 0)) - return -EINVAL; - -+ if (WARN_ON(dev_get_msi_domain(&mc_dev->dev))) -+ return -EINVAL; -+ - if (!mc_dev->mc_io) { - /* - * This is a child DPRC: -@@ -421,6 +427,30 @@ static int dprc_probe(struct fsl_mc_devi - &mc_dev->mc_io); - if (error < 0) - return error; -+ /* -+ * Inherit parent MSI domain: -+ */ -+ dev_set_msi_domain(&mc_dev->dev, -+ dev_get_msi_domain(parent_dev)); -+ msi_domain_set = true; -+ } else { -+ /* -+ * This is a root DPRC -+ */ -+ struct irq_domain *mc_msi_domain; -+ -+ if (WARN_ON(parent_dev->bus == &fsl_mc_bus_type)) -+ return -EINVAL; -+ -+ error = fsl_mc_find_msi_domain(parent_dev, -+ &mc_msi_domain); -+ if (error < 0) { -+ dev_warn(&mc_dev->dev, -+ "WARNING: MC bus without interrupt support\n"); -+ } else { -+ dev_set_msi_domain(&mc_dev->dev, mc_msi_domain); -+ msi_domain_set = true; -+ } - } - - error = dprc_open(mc_dev->mc_io, 0, mc_dev->obj_desc.id, -@@ -446,6 +476,9 @@ error_cleanup_open: - (void)dprc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); - - error_cleanup_mc_io: -+ if (msi_domain_set) -+ dev_set_msi_domain(&mc_dev->dev, NULL); -+ - fsl_destroy_mc_io(mc_dev->mc_io); - return error; - } -@@ -463,6 +496,7 @@ error_cleanup_mc_io: - static int dprc_remove(struct fsl_mc_device *mc_dev) - { - int error; -+ struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); - - if (WARN_ON(strcmp(mc_dev->obj_desc.type, "dprc") != 0)) - return -EINVAL; -@@ -475,6 +509,11 @@ static int dprc_remove(struct fsl_mc_dev - if (error < 0) - dev_err(&mc_dev->dev, "dprc_close() failed: %d\n", error); - -+ if (dev_get_msi_domain(&mc_dev->dev)) { -+ fsl_mc_cleanup_irq_pool(mc_bus); -+ dev_set_msi_domain(&mc_dev->dev, NULL); -+ } -+ - dev_info(&mc_dev->dev, "DPRC device unbound from driver"); - return 0; - } diff --git a/target/linux/layerscape/patches-4.4/7151-staging-fsl-mc-Fixed-bug-in-dprc_probe-error-path.patch b/target/linux/layerscape/patches-4.4/7151-staging-fsl-mc-Fixed-bug-in-dprc_probe-error-path.patch deleted file mode 100644 index 3324048a06..0000000000 --- a/target/linux/layerscape/patches-4.4/7151-staging-fsl-mc-Fixed-bug-in-dprc_probe-error-path.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 22aa842ae501ea8724afd45fcb0d7b17a67cb950 Mon Sep 17 00:00:00 2001 -From: "J. German Rivera" -Date: Wed, 6 Jan 2016 16:03:27 -0600 -Subject: [PATCH 151/226] staging: fsl-mc: Fixed bug in dprc_probe() error - path - -Destroy mc_io in error path in dprc_probe() only if the mc_io was -created in this function. - -Signed-off-by: J. German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 17 ++++++++++++++--- - 1 file changed, 14 insertions(+), 3 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -401,6 +401,7 @@ static int dprc_probe(struct fsl_mc_devi - size_t region_size; - struct device *parent_dev = mc_dev->dev.parent; - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); -+ bool mc_io_created = false; - bool msi_domain_set = false; - - if (WARN_ON(strcmp(mc_dev->obj_desc.type, "dprc") != 0)) -@@ -413,6 +414,9 @@ static int dprc_probe(struct fsl_mc_devi - /* - * This is a child DPRC: - */ -+ if (WARN_ON(parent_dev->bus != &fsl_mc_bus_type)) -+ return -EINVAL; -+ - if (WARN_ON(mc_dev->obj_desc.region_count == 0)) - return -EINVAL; - -@@ -427,6 +431,9 @@ static int dprc_probe(struct fsl_mc_devi - &mc_dev->mc_io); - if (error < 0) - return error; -+ -+ mc_io_created = true; -+ - /* - * Inherit parent MSI domain: - */ -@@ -457,7 +464,7 @@ static int dprc_probe(struct fsl_mc_devi - &mc_dev->mc_handle); - if (error < 0) { - dev_err(&mc_dev->dev, "dprc_open() failed: %d\n", error); -- goto error_cleanup_mc_io; -+ goto error_cleanup_msi_domain; - } - - mutex_init(&mc_bus->scan_mutex); -@@ -475,11 +482,15 @@ static int dprc_probe(struct fsl_mc_devi - error_cleanup_open: - (void)dprc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); - --error_cleanup_mc_io: -+error_cleanup_msi_domain: - if (msi_domain_set) - dev_set_msi_domain(&mc_dev->dev, NULL); - -- fsl_destroy_mc_io(mc_dev->mc_io); -+ if (mc_io_created) { -+ fsl_destroy_mc_io(mc_dev->mc_io); -+ mc_dev->mc_io = NULL; -+ } -+ - return error; - } - diff --git a/target/linux/layerscape/patches-4.4/7152-staging-fsl-mc-Added-DPRC-interrupt-handler.patch b/target/linux/layerscape/patches-4.4/7152-staging-fsl-mc-Added-DPRC-interrupt-handler.patch deleted file mode 100644 index 61b7ee71e1..0000000000 --- a/target/linux/layerscape/patches-4.4/7152-staging-fsl-mc-Added-DPRC-interrupt-handler.patch +++ /dev/null @@ -1,301 +0,0 @@ -From aa83997b14c31b34d9af24cb42726b55fa630464 Mon Sep 17 00:00:00 2001 -From: "J. German Rivera" -Date: Wed, 6 Jan 2016 16:03:28 -0600 -Subject: [PATCH 152/226] staging: fsl-mc: Added DPRC interrupt handler - -The interrupt handler for DPRC IRQs is added. DPRC IRQs are -generated for hot plug events related to DPAA2 objects in a given -DPRC. These events include, creating/destroying DPAA2 objects in -the DPRC, changing the "plugged" state of DPAA2 objects and moving -objects between DPRCs. - -Signed-off-by: J. German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 247 ++++++++++++++++++++++++++++++ - 1 file changed, 247 insertions(+) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include "dprc-cmd.h" - - struct dprc_child_objs { -@@ -386,6 +387,230 @@ error: - EXPORT_SYMBOL_GPL(dprc_scan_container); - - /** -+ * dprc_irq0_handler - Regular ISR for DPRC interrupt 0 -+ * -+ * @irq: IRQ number of the interrupt being handled -+ * @arg: Pointer to device structure -+ */ -+static irqreturn_t dprc_irq0_handler(int irq_num, void *arg) -+{ -+ return IRQ_WAKE_THREAD; -+} -+ -+/** -+ * dprc_irq0_handler_thread - Handler thread function for DPRC interrupt 0 -+ * -+ * @irq: IRQ number of the interrupt being handled -+ * @arg: Pointer to device structure -+ */ -+static irqreturn_t dprc_irq0_handler_thread(int irq_num, void *arg) -+{ -+ int error; -+ u32 status; -+ struct device *dev = (struct device *)arg; -+ struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); -+ struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); -+ struct fsl_mc_io *mc_io = mc_dev->mc_io; -+ struct msi_desc *msi_desc = mc_dev->irqs[0]->msi_desc; -+ -+ dev_dbg(dev, "DPRC IRQ %d triggered on CPU %u\n", -+ irq_num, smp_processor_id()); -+ -+ if (WARN_ON(!(mc_dev->flags & FSL_MC_IS_DPRC))) -+ return IRQ_HANDLED; -+ -+ mutex_lock(&mc_bus->scan_mutex); -+ if (WARN_ON(!msi_desc || msi_desc->irq != (u32)irq_num)) -+ goto out; -+ -+ error = dprc_get_irq_status(mc_io, 0, mc_dev->mc_handle, 0, -+ &status); -+ if (error < 0) { -+ dev_err(dev, -+ "dprc_get_irq_status() failed: %d\n", error); -+ goto out; -+ } -+ -+ error = dprc_clear_irq_status(mc_io, 0, mc_dev->mc_handle, 0, -+ status); -+ if (error < 0) { -+ dev_err(dev, -+ "dprc_clear_irq_status() failed: %d\n", error); -+ goto out; -+ } -+ -+ if (status & (DPRC_IRQ_EVENT_OBJ_ADDED | -+ DPRC_IRQ_EVENT_OBJ_REMOVED | -+ DPRC_IRQ_EVENT_CONTAINER_DESTROYED | -+ DPRC_IRQ_EVENT_OBJ_DESTROYED | -+ DPRC_IRQ_EVENT_OBJ_CREATED)) { -+ unsigned int irq_count; -+ -+ error = dprc_scan_objects(mc_dev, &irq_count); -+ if (error < 0) { -+ /* -+ * If the error is -ENXIO, we ignore it, as it indicates -+ * that the object scan was aborted, as we detected that -+ * an object was removed from the DPRC in the MC, while -+ * we were scanning the DPRC. -+ */ -+ if (error != -ENXIO) { -+ dev_err(dev, "dprc_scan_objects() failed: %d\n", -+ error); -+ } -+ -+ goto out; -+ } -+ -+ if (irq_count > FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS) { -+ dev_warn(dev, -+ "IRQs needed (%u) exceed IRQs preallocated (%u)\n", -+ irq_count, FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS); -+ } -+ } -+ -+out: -+ mutex_unlock(&mc_bus->scan_mutex); -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Disable and clear interrupt for a given DPRC object -+ */ -+static int disable_dprc_irq(struct fsl_mc_device *mc_dev) -+{ -+ int error; -+ struct fsl_mc_io *mc_io = mc_dev->mc_io; -+ -+ WARN_ON(mc_dev->obj_desc.irq_count != 1); -+ -+ /* -+ * Disable generation of interrupt, while we configure it: -+ */ -+ error = dprc_set_irq_enable(mc_io, 0, mc_dev->mc_handle, 0, 0); -+ if (error < 0) { -+ dev_err(&mc_dev->dev, -+ "Disabling DPRC IRQ failed: dprc_set_irq_enable() failed: %d\n", -+ error); -+ return error; -+ } -+ -+ /* -+ * Disable all interrupt causes for the interrupt: -+ */ -+ error = dprc_set_irq_mask(mc_io, 0, mc_dev->mc_handle, 0, 0x0); -+ if (error < 0) { -+ dev_err(&mc_dev->dev, -+ "Disabling DPRC IRQ failed: dprc_set_irq_mask() failed: %d\n", -+ error); -+ return error; -+ } -+ -+ /* -+ * Clear any leftover interrupts: -+ */ -+ error = dprc_clear_irq_status(mc_io, 0, mc_dev->mc_handle, 0, ~0x0U); -+ if (error < 0) { -+ dev_err(&mc_dev->dev, -+ "Disabling DPRC IRQ failed: dprc_clear_irq_status() failed: %d\n", -+ error); -+ return error; -+ } -+ -+ return 0; -+} -+ -+static int register_dprc_irq_handler(struct fsl_mc_device *mc_dev) -+{ -+ int error; -+ struct fsl_mc_device_irq *irq = mc_dev->irqs[0]; -+ -+ WARN_ON(mc_dev->obj_desc.irq_count != 1); -+ -+ /* -+ * NOTE: devm_request_threaded_irq() invokes the device-specific -+ * function that programs the MSI physically in the device -+ */ -+ error = devm_request_threaded_irq(&mc_dev->dev, -+ irq->msi_desc->irq, -+ dprc_irq0_handler, -+ dprc_irq0_handler_thread, -+ IRQF_NO_SUSPEND | IRQF_ONESHOT, -+ "FSL MC DPRC irq0", -+ &mc_dev->dev); -+ if (error < 0) { -+ dev_err(&mc_dev->dev, -+ "devm_request_threaded_irq() failed: %d\n", -+ error); -+ return error; -+ } -+ -+ return 0; -+} -+ -+static int enable_dprc_irq(struct fsl_mc_device *mc_dev) -+{ -+ int error; -+ -+ /* -+ * Enable all interrupt causes for the interrupt: -+ */ -+ error = dprc_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle, 0, -+ ~0x0u); -+ if (error < 0) { -+ dev_err(&mc_dev->dev, -+ "Enabling DPRC IRQ failed: dprc_set_irq_mask() failed: %d\n", -+ error); -+ -+ return error; -+ } -+ -+ /* -+ * Enable generation of the interrupt: -+ */ -+ error = dprc_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle, 0, 1); -+ if (error < 0) { -+ dev_err(&mc_dev->dev, -+ "Enabling DPRC IRQ failed: dprc_set_irq_enable() failed: %d\n", -+ error); -+ -+ return error; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Setup interrupt for a given DPRC device -+ */ -+static int dprc_setup_irq(struct fsl_mc_device *mc_dev) -+{ -+ int error; -+ -+ error = fsl_mc_allocate_irqs(mc_dev); -+ if (error < 0) -+ return error; -+ -+ error = disable_dprc_irq(mc_dev); -+ if (error < 0) -+ goto error_free_irqs; -+ -+ error = register_dprc_irq_handler(mc_dev); -+ if (error < 0) -+ goto error_free_irqs; -+ -+ error = enable_dprc_irq(mc_dev); -+ if (error < 0) -+ goto error_free_irqs; -+ -+ return 0; -+ -+error_free_irqs: -+ fsl_mc_free_irqs(mc_dev); -+ return error; -+} -+ -+/** - * dprc_probe - callback invoked when a DPRC is being bound to this driver - * - * @mc_dev: Pointer to fsl-mc device representing a DPRC -@@ -476,6 +701,13 @@ static int dprc_probe(struct fsl_mc_devi - if (error < 0) - goto error_cleanup_open; - -+ /* -+ * Configure interrupt for the DPRC object associated with this MC bus: -+ */ -+ error = dprc_setup_irq(mc_dev); -+ if (error < 0) -+ goto error_cleanup_open; -+ - dev_info(&mc_dev->dev, "DPRC device bound to driver"); - return 0; - -@@ -494,6 +726,15 @@ error_cleanup_msi_domain: - return error; - } - -+/* -+ * Tear down interrupt for a given DPRC object -+ */ -+static void dprc_teardown_irq(struct fsl_mc_device *mc_dev) -+{ -+ (void)disable_dprc_irq(mc_dev); -+ fsl_mc_free_irqs(mc_dev); -+} -+ - /** - * dprc_remove - callback invoked when a DPRC is being unbound from this driver - * -@@ -514,6 +755,12 @@ static int dprc_remove(struct fsl_mc_dev - if (WARN_ON(!mc_dev->mc_io)) - return -EINVAL; - -+ if (WARN_ON(!mc_bus->irq_resources)) -+ return -EINVAL; -+ -+ if (dev_get_msi_domain(&mc_dev->dev)) -+ dprc_teardown_irq(mc_dev); -+ - device_for_each_child(&mc_dev->dev, NULL, __fsl_mc_device_remove); - dprc_cleanup_all_resource_pools(mc_dev); - error = dprc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); diff --git a/target/linux/layerscape/patches-4.4/7153-staging-fsl-mc-Added-MSI-support-to-the-MC-bus-drive.patch b/target/linux/layerscape/patches-4.4/7153-staging-fsl-mc-Added-MSI-support-to-the-MC-bus-drive.patch deleted file mode 100644 index cbc6c5e650..0000000000 --- a/target/linux/layerscape/patches-4.4/7153-staging-fsl-mc-Added-MSI-support-to-the-MC-bus-drive.patch +++ /dev/null @@ -1,59 +0,0 @@ -From f588a135d9260f2e7fe29b0bb0b5294fc9c99f6c Mon Sep 17 00:00:00 2001 -From: "J. German Rivera" -Date: Wed, 6 Jan 2016 16:03:29 -0600 -Subject: [PATCH 153/226] staging: fsl-mc: Added MSI support to the MC bus - driver - -Initialize/Cleanup ITS-MSI support for the MC bus driver at driver -init/exit time. Associate an MSI domain with each DPAA2 child device. - -Signed-off-by: J. German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -16,6 +16,8 @@ - #include - #include - #include -+#include -+#include - #include "../include/dpmng.h" - #include "../include/mc-sys.h" - #include "dprc-cmd.h" -@@ -472,6 +474,8 @@ int fsl_mc_device_add(struct dprc_obj_de - mc_dev->icid = parent_mc_dev->icid; - mc_dev->dma_mask = FSL_MC_DEFAULT_DMA_MASK; - mc_dev->dev.dma_mask = &mc_dev->dma_mask; -+ dev_set_msi_domain(&mc_dev->dev, -+ dev_get_msi_domain(&parent_mc_dev->dev)); - } - - /* -@@ -833,8 +837,15 @@ static int __init fsl_mc_bus_driver_init - if (error < 0) - goto error_cleanup_dprc_driver; - -+ error = its_fsl_mc_msi_init(); -+ if (error < 0) -+ goto error_cleanup_mc_allocator; -+ - return 0; - -+error_cleanup_mc_allocator: -+ fsl_mc_allocator_driver_exit(); -+ - error_cleanup_dprc_driver: - dprc_driver_exit(); - -@@ -856,6 +867,7 @@ static void __exit fsl_mc_bus_driver_exi - if (WARN_ON(!mc_dev_cache)) - return; - -+ its_fsl_mc_msi_cleanup(); - fsl_mc_allocator_driver_exit(); - dprc_driver_exit(); - platform_driver_unregister(&fsl_mc_bus_driver); diff --git a/target/linux/layerscape/patches-4.4/7154-staging-fsl-mc-Remove-unneeded-parentheses.patch b/target/linux/layerscape/patches-4.4/7154-staging-fsl-mc-Remove-unneeded-parentheses.patch deleted file mode 100644 index 64af81c19e..0000000000 --- a/target/linux/layerscape/patches-4.4/7154-staging-fsl-mc-Remove-unneeded-parentheses.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 6ce3c078c4eac406b38de689c8e366d7345a51ba Mon Sep 17 00:00:00 2001 -From: Janani Ravichandran -Date: Thu, 11 Feb 2016 18:00:25 -0500 -Subject: [PATCH 154/226] staging: fsl-mc: Remove unneeded parentheses - -Remove unneeded parentheses on the right hand side of assignment -statements. -Semantic patch: - -@@ -expression a, b, c; -@@ - -( - a = (b == c) -| - a = -- ( - b -- ) -) - -Signed-off-by: Janani Ravichandran -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -129,7 +129,7 @@ static void check_plugged_state_change(s - { - int error; - u32 plugged_flag_at_mc = -- (obj_desc->state & DPRC_OBJ_STATE_PLUGGED); -+ obj_desc->state & DPRC_OBJ_STATE_PLUGGED; - - if (plugged_flag_at_mc != - (mc_dev->obj_desc.state & DPRC_OBJ_STATE_PLUGGED)) { diff --git a/target/linux/layerscape/patches-4.4/7155-staging-fsl-mc-Do-not-allow-building-as-a-module.patch b/target/linux/layerscape/patches-4.4/7155-staging-fsl-mc-Do-not-allow-building-as-a-module.patch deleted file mode 100644 index 1ae62537fc..0000000000 --- a/target/linux/layerscape/patches-4.4/7155-staging-fsl-mc-Do-not-allow-building-as-a-module.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 322ff2fe86ec4dead2d2bceb20b624c72bdd1405 Mon Sep 17 00:00:00 2001 -From: Thierry Reding -Date: Mon, 15 Feb 2016 14:22:22 +0100 -Subject: [PATCH 155/226] staging: fsl-mc: Do not allow building as a module - -This driver uses functionality (MSI IRQ domain) whose symbols aren't -exported, and hence the modular build fails. While arguably there might -be reasons to make these symbols available to modules, that change would -be fairly involved and the set of exported functions should be carefully -auditioned. Fix the build failure for now by marking the driver boolean. - -Cc: J. German Rivera -Cc: Greg Kroah-Hartman -Signed-off-by: Thierry Reding -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/staging/fsl-mc/bus/Kconfig -+++ b/drivers/staging/fsl-mc/bus/Kconfig -@@ -7,7 +7,7 @@ - # - - config FSL_MC_BUS -- tristate "Freescale Management Complex (MC) bus driver" -+ bool "Freescale Management Complex (MC) bus driver" - depends on OF && ARM64 - select GENERIC_MSI_IRQ_DOMAIN - help diff --git a/target/linux/layerscape/patches-4.4/7156-staging-fsl-mc-Avoid-section-mismatch.patch b/target/linux/layerscape/patches-4.4/7156-staging-fsl-mc-Avoid-section-mismatch.patch deleted file mode 100644 index 60fecd9b08..0000000000 --- a/target/linux/layerscape/patches-4.4/7156-staging-fsl-mc-Avoid-section-mismatch.patch +++ /dev/null @@ -1,43 +0,0 @@ -From b2e5cfb43faf26517d191de65121f1a40166340f Mon Sep 17 00:00:00 2001 -From: Thierry Reding -Date: Mon, 15 Feb 2016 14:22:23 +0100 -Subject: [PATCH 156/226] staging: fsl-mc: Avoid section mismatch - -The fsl_mc_allocator_driver_exit() function is marked __exit, but is -called by the error handling code in fsl_mc_allocator_driver_init(). -This results in a section mismatch, which in turn could lead to -executing random code. - -Remove the __exit annotation to fix this. - -Cc: J. German Rivera -Cc: Greg Kroah-Hartman -Signed-off-by: Thierry Reding -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-allocator.c | 2 +- - drivers/staging/fsl-mc/include/mc-private.h | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/mc-allocator.c -+++ b/drivers/staging/fsl-mc/bus/mc-allocator.c -@@ -756,7 +756,7 @@ int __init fsl_mc_allocator_driver_init( - return fsl_mc_driver_register(&fsl_mc_allocator_driver); - } - --void __exit fsl_mc_allocator_driver_exit(void) -+void fsl_mc_allocator_driver_exit(void) - { - fsl_mc_driver_unregister(&fsl_mc_allocator_driver); - } ---- a/drivers/staging/fsl-mc/include/mc-private.h -+++ b/drivers/staging/fsl-mc/include/mc-private.h -@@ -123,7 +123,7 @@ void dprc_driver_exit(void); - - int __init fsl_mc_allocator_driver_init(void); - --void __exit fsl_mc_allocator_driver_exit(void); -+void fsl_mc_allocator_driver_exit(void); - - int __must_check fsl_mc_resource_allocate(struct fsl_mc_bus *mc_bus, - enum fsl_mc_pool_type pool_type, diff --git a/target/linux/layerscape/patches-4.4/7157-staging-fsl-mc-Remove-unneeded-else-following-a-retu.patch b/target/linux/layerscape/patches-4.4/7157-staging-fsl-mc-Remove-unneeded-else-following-a-retu.patch deleted file mode 100644 index ee0d1f62bc..0000000000 --- a/target/linux/layerscape/patches-4.4/7157-staging-fsl-mc-Remove-unneeded-else-following-a-retu.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 5f82c6ff69f3a4bb635e619a893292bea711421e Mon Sep 17 00:00:00 2001 -From: Janani Ravichandran -Date: Thu, 18 Feb 2016 17:22:50 -0500 -Subject: [PATCH 157/226] staging: fsl-mc: Remove unneeded else following a - return - -Remove unnecessary else when there is a return statement in the -corresponding if block. Coccinelle patch used: - -@rule1@ -expression e1; -@@ - - if (e1) { ... return ...; } -- else{ - ... -- } - -@rule2@ -expression e2; -statement s1; -@@ - - if(e2) { ... return ...; } -- else - s1 - -Signed-off-by: Janani Ravichandran -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -248,8 +248,7 @@ static bool fsl_mc_is_root_dprc(struct d - fsl_mc_get_root_dprc(dev, &root_dprc_dev); - if (!root_dprc_dev) - return false; -- else -- return dev == root_dprc_dev; -+ return dev == root_dprc_dev; - } - - static int get_dprc_icid(struct fsl_mc_io *mc_io, diff --git a/target/linux/layerscape/patches-4.4/7158-staging-fsl-mc-Drop-unneeded-void-pointer-cast.patch b/target/linux/layerscape/patches-4.4/7158-staging-fsl-mc-Drop-unneeded-void-pointer-cast.patch deleted file mode 100644 index 51e8792985..0000000000 --- a/target/linux/layerscape/patches-4.4/7158-staging-fsl-mc-Drop-unneeded-void-pointer-cast.patch +++ /dev/null @@ -1,43 +0,0 @@ -From d9605741556a15dceed105afd7369d644aa46207 Mon Sep 17 00:00:00 2001 -From: Janani Ravichandran -Date: Thu, 25 Feb 2016 14:46:11 -0500 -Subject: [PATCH 158/226] staging: fsl-mc: Drop unneeded void pointer cast - -Void pointers need not be cast to other pointer types. -Semantic patch used: - -@r@ -expression x; -void *e; -type T; -identifier f; -@@ - -( - *((T *)e) -| - ((T *)x) [...] -| - ((T *)x)->f -| -- (T *) - e -) - -Signed-off-by: Janani Ravichandran -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -407,7 +407,7 @@ static irqreturn_t dprc_irq0_handler_thr - { - int error; - u32 status; -- struct device *dev = (struct device *)arg; -+ struct device *dev = arg; - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); - struct fsl_mc_io *mc_io = mc_dev->mc_io; diff --git a/target/linux/layerscape/patches-4.4/7159-staging-fsl-mc-bus-Eliminate-double-function-call.patch b/target/linux/layerscape/patches-4.4/7159-staging-fsl-mc-bus-Eliminate-double-function-call.patch deleted file mode 100644 index 74ac4fd28f..0000000000 --- a/target/linux/layerscape/patches-4.4/7159-staging-fsl-mc-bus-Eliminate-double-function-call.patch +++ /dev/null @@ -1,73 +0,0 @@ -From ecd7b5d9616e50f48a400749f17db19fd8a43f25 Mon Sep 17 00:00:00 2001 -From: Bhaktipriya Shridhar -Date: Sun, 28 Feb 2016 23:58:05 +0530 -Subject: [PATCH 159/226] staging: fsl-mc: bus: Eliminate double function call - -A call to irq_find_matching_host was already made and the result -has been stored in mc_msi_domain. mc_msi_domain is again reassigned -using the same function call which is redundant. - -irq_find_matching_host returns/locates a domain for a given fwnode. -The domain is identified using device node and bus_token(if several -domains have same device node but different purposes they can be -distinguished using bus-specific token). -http://www.bricktou.com/include/linux/irqdomain_irq_find_matching_host_en.html - -Also, of_property_read_bool finds and reads a boolean from a property -device node from which the property value is to be read. It doesn't -alter the device node. -http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/083698.html - -Since, both the function calls have the same device node and bus_token, -the return values shall be the same. Hence, the second call has been -removed. - -This was done using Coccinelle: - -@r@ -idexpression *x; -identifier f; -position p1,p2; -@@ - -x@p1 = f(...) -... when != x -( -x@p2 = f(...) -) - -@script:python@ -p1 << r.p1; -p2 << r.p2; -@@ - -if (p1[0].line == p2[0].line): - cocci.include_match(False) - -@@ -idexpression *x; -identifier f; -position r.p1,r.p2; -@@ - -*x@p1 = f(...) -... -*x@p2 = f(...) - -Signed-off-by: Bhaktipriya Shridhar -Signed-off-by: Greg Kroah-Hartman ---- - .../staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c -+++ b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c -@@ -118,8 +118,6 @@ void its_fsl_mc_msi_cleanup(void) - if (!of_property_read_bool(np, "msi-controller")) - continue; - -- mc_msi_domain = irq_find_matching_host(np, -- DOMAIN_BUS_FSL_MC_MSI); - if (mc_msi_domain && - mc_msi_domain->host_data == &its_fsl_mc_msi_domain_info) - irq_domain_remove(mc_msi_domain); diff --git a/target/linux/layerscape/patches-4.4/7160-Staging-fsl-mc-Replace-pr_debug-with-dev_dbg.patch b/target/linux/layerscape/patches-4.4/7160-Staging-fsl-mc-Replace-pr_debug-with-dev_dbg.patch deleted file mode 100644 index 2d9c947263..0000000000 --- a/target/linux/layerscape/patches-4.4/7160-Staging-fsl-mc-Replace-pr_debug-with-dev_dbg.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 8727f71717b449a4c74a5a599374c05822d525f7 Mon Sep 17 00:00:00 2001 -From: Bhumika Goyal -Date: Fri, 4 Mar 2016 19:14:52 +0530 -Subject: [PATCH 160/226] Staging: fsl-mc: Replace pr_debug with dev_dbg - -This patch replaces pr_debug calls with dev_dbg when the device structure -is available as dev_* prints identifying information about the struct -device. -Done using coccinelle: - -@r exists@ -identifier f, s; -identifier x; -position p; -@@ -f(...,struct s *x,...) { -<+... -when != x == NULL -\(pr_err@p\|pr_debug@p\|pr_info\)(...); -...+> -} - -@r2@ -identifier fld2; -identifier r.s; -@@ - -struct s { - ... - struct device *fld2; - ... -}; - -@@ -identifier r.x,r2.fld2; -position r.p; -@@ - -( --pr_err@p -+dev_err - ( -+ &x->fld2, -...) -| -- pr_debug@p -+ dev_dbg - ( -+ &x->fld2, -...) -| -- pr_info@p -+ dev_info - ( -+ &x->fld2, -...) -) - -Signed-off-by: Bhumika Goyal -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-sys.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/mc-sys.c -+++ b/drivers/staging/fsl-mc/bus/mc-sys.c -@@ -328,7 +328,8 @@ static int mc_polling_wait_preemptible(s - MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS); - - if (time_after_eq(jiffies, jiffies_until_timeout)) { -- pr_debug("MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n", -+ dev_dbg(&mc_io->dev, -+ "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n", - mc_io->portal_phys_addr, - (unsigned int) - MC_CMD_HDR_READ_TOKEN(cmd->header), -@@ -369,7 +370,8 @@ static int mc_polling_wait_atomic(struct - udelay(MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS); - timeout_usecs -= MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS; - if (timeout_usecs == 0) { -- pr_debug("MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n", -+ dev_dbg(&mc_io->dev, -+ "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n", - mc_io->portal_phys_addr, - (unsigned int) - MC_CMD_HDR_READ_TOKEN(cmd->header), -@@ -424,7 +426,8 @@ int mc_send_command(struct fsl_mc_io *mc - goto common_exit; - - if (status != MC_CMD_STATUS_OK) { -- pr_debug("MC command failed: portal: %#llx, obj handle: %#x, command: %#x, status: %s (%#x)\n", -+ dev_dbg(&mc_io->dev, -+ "MC command failed: portal: %#llx, obj handle: %#x, command: %#x, status: %s (%#x)\n", - mc_io->portal_phys_addr, - (unsigned int)MC_CMD_HDR_READ_TOKEN(cmd->header), - (unsigned int)MC_CMD_HDR_READ_CMDID(cmd->header), diff --git a/target/linux/layerscape/patches-4.4/7161-Staging-fsl-mc-Replace-pr_err-with-dev_err.patch b/target/linux/layerscape/patches-4.4/7161-Staging-fsl-mc-Replace-pr_err-with-dev_err.patch deleted file mode 100644 index 3da41c16c3..0000000000 --- a/target/linux/layerscape/patches-4.4/7161-Staging-fsl-mc-Replace-pr_err-with-dev_err.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 79b4625a6ab72251e00aa94ee22a6bfe32dbeeda Mon Sep 17 00:00:00 2001 -From: Bhumika Goyal -Date: Fri, 4 Mar 2016 19:15:55 +0530 -Subject: [PATCH 161/226] Staging: fsl-mc: Replace pr_err with dev_err - -This patch replaces pr_err calls with dev_err when the device structure -is available as dev_* prints identifying information about the struct device. -Done using coccinelle: - -@r exists@ -identifier f, s; -identifier x; -position p; -@@ -f(...,struct s *x,...) { -<+... -when != x == NULL -\(pr_err@p\|pr_debug@p\|pr_info\)(...); -...+> -} - -@r2@ -identifier fld2; -identifier r.s; -@@ - -struct s { - ... - struct device *fld2; - ... -}; - -@@ -identifier r.x,r2.fld2; -position r.p; -@@ - -( --pr_err@p -+dev_err - ( -+ &x->fld2, -...) -| -- pr_debug@p -+ dev_dbg - ( -+ &x->fld2, -...) -| -- pr_info@p -+ dev_info - ( -+ &x->fld2, -...) -) - -Signed-off-by: Bhumika Goyal -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -260,14 +260,15 @@ static int get_dprc_icid(struct fsl_mc_i - - error = dprc_open(mc_io, 0, container_id, &dprc_handle); - if (error < 0) { -- pr_err("dprc_open() failed: %d\n", error); -+ dev_err(&mc_io->dev, "dprc_open() failed: %d\n", error); - return error; - } - - memset(&attr, 0, sizeof(attr)); - error = dprc_get_attributes(mc_io, 0, dprc_handle, &attr); - if (error < 0) { -- pr_err("dprc_get_attributes() failed: %d\n", error); -+ dev_err(&mc_io->dev, "dprc_get_attributes() failed: %d\n", -+ error); - goto common_cleanup; - } - diff --git a/target/linux/layerscape/patches-4.4/7162-staging-fsl-mc-fix-incorrect-type-passed-to-dev_dbg-.patch b/target/linux/layerscape/patches-4.4/7162-staging-fsl-mc-fix-incorrect-type-passed-to-dev_dbg-.patch deleted file mode 100644 index 4a326020df..0000000000 --- a/target/linux/layerscape/patches-4.4/7162-staging-fsl-mc-fix-incorrect-type-passed-to-dev_dbg-.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 83e0f572a74bceeb3736b19b929c91d12d1d6d80 Mon Sep 17 00:00:00 2001 -From: Cihangir Akturk -Date: Mon, 14 Mar 2016 18:14:06 +0200 -Subject: [PATCH 162/226] staging: fsl-mc: fix incorrect type passed to - dev_dbg macros - -dev_dbg macros expect const struct device ** as its second -argument but here the argument we are passing is of type -struct device ** this patch fixes this error. - -Fixes: de71daf5c839 ("Staging: fsl-mc: Replace pr_debug with dev_dbg") -Cc: Bhumika Goyal -Reported-by: Guenter Roeck -Signed-off-by: Cihangir Akturk -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-sys.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/mc-sys.c -+++ b/drivers/staging/fsl-mc/bus/mc-sys.c -@@ -328,7 +328,7 @@ static int mc_polling_wait_preemptible(s - MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS); - - if (time_after_eq(jiffies, jiffies_until_timeout)) { -- dev_dbg(&mc_io->dev, -+ dev_dbg(mc_io->dev, - "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n", - mc_io->portal_phys_addr, - (unsigned int) -@@ -370,7 +370,7 @@ static int mc_polling_wait_atomic(struct - udelay(MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS); - timeout_usecs -= MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS; - if (timeout_usecs == 0) { -- dev_dbg(&mc_io->dev, -+ dev_dbg(mc_io->dev, - "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n", - mc_io->portal_phys_addr, - (unsigned int) -@@ -426,7 +426,7 @@ int mc_send_command(struct fsl_mc_io *mc - goto common_exit; - - if (status != MC_CMD_STATUS_OK) { -- dev_dbg(&mc_io->dev, -+ dev_dbg(mc_io->dev, - "MC command failed: portal: %#llx, obj handle: %#x, command: %#x, status: %s (%#x)\n", - mc_io->portal_phys_addr, - (unsigned int)MC_CMD_HDR_READ_TOKEN(cmd->header), diff --git a/target/linux/layerscape/patches-4.4/7163-staging-fsl-mc-fix-incorrect-type-passed-to-dev_err-.patch b/target/linux/layerscape/patches-4.4/7163-staging-fsl-mc-fix-incorrect-type-passed-to-dev_err-.patch deleted file mode 100644 index 024e10f297..0000000000 --- a/target/linux/layerscape/patches-4.4/7163-staging-fsl-mc-fix-incorrect-type-passed-to-dev_err-.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 79929c151efbc047a8a82f9cafcb9238465caa86 Mon Sep 17 00:00:00 2001 -From: Cihangir Akturk -Date: Mon, 14 Mar 2016 18:14:07 +0200 -Subject: [PATCH 163/226] staging: fsl-mc: fix incorrect type passed to - dev_err macros - -dev_err macros expect const struct device ** as its second -argument, but here the argument we are passing is of typ -struct device **. This patch fixes this error. - -Fixes: 454b0ec8bf99 ("Staging: fsl-mc: Replace pr_err with dev_err") -Cc: Bhumika Goyal -Reported-by: Guenter Roeck -Signed-off-by: Cihangir Akturk -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -260,14 +260,14 @@ static int get_dprc_icid(struct fsl_mc_i - - error = dprc_open(mc_io, 0, container_id, &dprc_handle); - if (error < 0) { -- dev_err(&mc_io->dev, "dprc_open() failed: %d\n", error); -+ dev_err(mc_io->dev, "dprc_open() failed: %d\n", error); - return error; - } - - memset(&attr, 0, sizeof(attr)); - error = dprc_get_attributes(mc_io, 0, dprc_handle, &attr); - if (error < 0) { -- dev_err(&mc_io->dev, "dprc_get_attributes() failed: %d\n", -+ dev_err(mc_io->dev, "dprc_get_attributes() failed: %d\n", - error); - goto common_cleanup; - } diff --git a/target/linux/layerscape/patches-4.4/7164-staging-fsl-mc-get-rid-of-mutex_locked-variables.patch b/target/linux/layerscape/patches-4.4/7164-staging-fsl-mc-get-rid-of-mutex_locked-variables.patch deleted file mode 100644 index d16485f4cd..0000000000 --- a/target/linux/layerscape/patches-4.4/7164-staging-fsl-mc-get-rid-of-mutex_locked-variables.patch +++ /dev/null @@ -1,207 +0,0 @@ -From d36a6b361a3a181559daebcf32e11ab18431a854 Mon Sep 17 00:00:00 2001 -From: Cihangir Akturk -Date: Sat, 9 Apr 2016 21:45:18 +0300 -Subject: [PATCH 164/226] staging: fsl-mc: get rid of mutex_locked variables - -Remove mutex_locked variables which are used to determine whether mutex is -locked, instead add another label to unlock mutex on premature exits due to -an error. - -This patch also addresses the folowing warnings reported by coccinelle: - -drivers/staging/fsl-mc/bus/mc-allocator.c:237:1-7: preceding lock on line 204 -drivers/staging/fsl-mc/bus/mc-allocator.c:89:1-7: preceding lock on line 57 -drivers/staging/fsl-mc/bus/mc-allocator.c:157:1-7: preceding lock on line 124 - -Signed-off-by: Cihangir Akturk -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-allocator.c | 61 ++++++++++++----------------- - 1 file changed, 24 insertions(+), 37 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/mc-allocator.c -+++ b/drivers/staging/fsl-mc/bus/mc-allocator.c -@@ -39,7 +39,6 @@ static int __must_check fsl_mc_resource_ - struct fsl_mc_resource *resource; - struct fsl_mc_device *mc_bus_dev = &mc_bus->mc_dev; - int error = -EINVAL; -- bool mutex_locked = false; - - if (WARN_ON(pool_type < 0 || pool_type >= FSL_MC_NUM_POOL_TYPES)) - goto out; -@@ -55,13 +54,12 @@ static int __must_check fsl_mc_resource_ - goto out; - - mutex_lock(&res_pool->mutex); -- mutex_locked = true; - - if (WARN_ON(res_pool->max_count < 0)) -- goto out; -+ goto out_unlock; - if (WARN_ON(res_pool->free_count < 0 || - res_pool->free_count > res_pool->max_count)) -- goto out; -+ goto out_unlock; - - resource = devm_kzalloc(&mc_bus_dev->dev, sizeof(*resource), - GFP_KERNEL); -@@ -69,7 +67,7 @@ static int __must_check fsl_mc_resource_ - error = -ENOMEM; - dev_err(&mc_bus_dev->dev, - "Failed to allocate memory for fsl_mc_resource\n"); -- goto out; -+ goto out_unlock; - } - - resource->type = pool_type; -@@ -82,10 +80,9 @@ static int __must_check fsl_mc_resource_ - res_pool->free_count++; - res_pool->max_count++; - error = 0; -+out_unlock: -+ mutex_unlock(&res_pool->mutex); - out: -- if (mutex_locked) -- mutex_unlock(&res_pool->mutex); -- - return error; - } - -@@ -106,7 +103,6 @@ static int __must_check fsl_mc_resource_ - struct fsl_mc_resource_pool *res_pool; - struct fsl_mc_resource *resource; - int error = -EINVAL; -- bool mutex_locked = false; - - if (WARN_ON(!FSL_MC_IS_ALLOCATABLE(mc_dev->obj_desc.type))) - goto out; -@@ -122,13 +118,12 @@ static int __must_check fsl_mc_resource_ - goto out; - - mutex_lock(&res_pool->mutex); -- mutex_locked = true; - - if (WARN_ON(res_pool->max_count <= 0)) -- goto out; -+ goto out_unlock; - if (WARN_ON(res_pool->free_count <= 0 || - res_pool->free_count > res_pool->max_count)) -- goto out; -+ goto out_unlock; - - /* - * If the device is currently allocated, its resource is not -@@ -139,7 +134,7 @@ static int __must_check fsl_mc_resource_ - dev_err(&mc_bus_dev->dev, - "Device %s cannot be removed from resource pool\n", - dev_name(&mc_dev->dev)); -- goto out; -+ goto out_unlock; - } - - list_del(&resource->node); -@@ -150,10 +145,9 @@ static int __must_check fsl_mc_resource_ - devm_kfree(&mc_bus_dev->dev, resource); - mc_dev->resource = NULL; - error = 0; -+out_unlock: -+ mutex_unlock(&res_pool->mutex); - out: -- if (mutex_locked) -- mutex_unlock(&res_pool->mutex); -- - return error; - } - -@@ -188,21 +182,19 @@ int __must_check fsl_mc_resource_allocat - struct fsl_mc_resource *resource; - struct fsl_mc_device *mc_bus_dev = &mc_bus->mc_dev; - int error = -EINVAL; -- bool mutex_locked = false; - - BUILD_BUG_ON(ARRAY_SIZE(fsl_mc_pool_type_strings) != - FSL_MC_NUM_POOL_TYPES); - - *new_resource = NULL; - if (WARN_ON(pool_type < 0 || pool_type >= FSL_MC_NUM_POOL_TYPES)) -- goto error; -+ goto out; - - res_pool = &mc_bus->resource_pools[pool_type]; - if (WARN_ON(res_pool->mc_bus != mc_bus)) -- goto error; -+ goto out; - - mutex_lock(&res_pool->mutex); -- mutex_locked = true; - resource = list_first_entry_or_null(&res_pool->free_list, - struct fsl_mc_resource, node); - -@@ -212,28 +204,26 @@ int __must_check fsl_mc_resource_allocat - dev_err(&mc_bus_dev->dev, - "No more resources of type %s left\n", - fsl_mc_pool_type_strings[pool_type]); -- goto error; -+ goto out_unlock; - } - - if (WARN_ON(resource->type != pool_type)) -- goto error; -+ goto out_unlock; - if (WARN_ON(resource->parent_pool != res_pool)) -- goto error; -+ goto out_unlock; - if (WARN_ON(res_pool->free_count <= 0 || - res_pool->free_count > res_pool->max_count)) -- goto error; -+ goto out_unlock; - - list_del(&resource->node); - INIT_LIST_HEAD(&resource->node); - - res_pool->free_count--; -+ error = 0; -+out_unlock: - mutex_unlock(&res_pool->mutex); - *new_resource = resource; -- return 0; --error: -- if (mutex_locked) -- mutex_unlock(&res_pool->mutex); -- -+out: - return error; - } - EXPORT_SYMBOL_GPL(fsl_mc_resource_allocate); -@@ -241,26 +231,23 @@ EXPORT_SYMBOL_GPL(fsl_mc_resource_alloca - void fsl_mc_resource_free(struct fsl_mc_resource *resource) - { - struct fsl_mc_resource_pool *res_pool; -- bool mutex_locked = false; - - res_pool = resource->parent_pool; - if (WARN_ON(resource->type != res_pool->type)) -- goto out; -+ return; - - mutex_lock(&res_pool->mutex); -- mutex_locked = true; - if (WARN_ON(res_pool->free_count < 0 || - res_pool->free_count >= res_pool->max_count)) -- goto out; -+ goto out_unlock; - - if (WARN_ON(!list_empty(&resource->node))) -- goto out; -+ goto out_unlock; - - list_add_tail(&resource->node, &res_pool->free_list); - res_pool->free_count++; --out: -- if (mutex_locked) -- mutex_unlock(&res_pool->mutex); -+out_unlock: -+ mutex_unlock(&res_pool->mutex); - } - EXPORT_SYMBOL_GPL(fsl_mc_resource_free); - diff --git a/target/linux/layerscape/patches-4.4/7165-staging-fsl-mc-TODO-updates.patch b/target/linux/layerscape/patches-4.4/7165-staging-fsl-mc-TODO-updates.patch deleted file mode 100644 index 858c6e21e8..0000000000 --- a/target/linux/layerscape/patches-4.4/7165-staging-fsl-mc-TODO-updates.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 7b3bffea6d36f396faf1814088f03a6b8efe1ccb Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Mon, 11 Apr 2016 11:48:37 -0500 -Subject: [PATCH 165/226] staging: fsl-mc: TODO updates - -remove 3 of the remaining TODO items: - - -multiple root fsl-mc buses-- done in patch series starting with - commit 14f928054a05 ("staging: fsl-mc: abstract test for existence - of fsl-mc bus") - - -interrupt support-- done in patch series starting with - commit 9b1b282ccd81 ("irqdomain: Added domain bus token - DOMAIN_BUS_FSL_MC_MSI") - - -MC command serialization-- done in commit 63f2be5c3b358 ("staging: - fsl-mc: Added serialization to mc_send_command()") - -Signed-off-by: Stuart Yoder -Acked-by: German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/TODO | 13 ------------- - 1 file changed, 13 deletions(-) - ---- a/drivers/staging/fsl-mc/TODO -+++ b/drivers/staging/fsl-mc/TODO -@@ -1,21 +1,8 @@ --* Decide if multiple root fsl-mc buses will be supported per Linux instance, -- and if so add support for this. -- - * Add at least one device driver for a DPAA2 object (child device of the - fsl-mc bus). Most likely candidate for this is adding DPAA2 Ethernet - driver support, which depends on drivers for several objects: DPNI, - DPIO, DPMAC. Other pre-requisites include: - -- * interrupt support. for meaningful driver support we need -- interrupts, and thus need message interrupt support by the bus -- driver. -- -Note: this has dependencies on generic MSI support work -- in process upstream, see [1] and [2]. -- -- * Management Complex (MC) command serialization. locking mechanisms -- are needed by drivers to serialize commands sent to the MC, including -- from atomic context. -- - * MC firmware uprev. The MC firmware upon which the fsl-mc - bus driver and DPAA2 object drivers are based is continuing - to evolve, so minor updates are needed to keep in sync with binary diff --git a/target/linux/layerscape/patches-4.4/7166-staging-fsl-mc-DPAA2-overview-readme-update.patch b/target/linux/layerscape/patches-4.4/7166-staging-fsl-mc-DPAA2-overview-readme-update.patch deleted file mode 100644 index f63574d649..0000000000 --- a/target/linux/layerscape/patches-4.4/7166-staging-fsl-mc-DPAA2-overview-readme-update.patch +++ /dev/null @@ -1,279 +0,0 @@ -From 720bf9c9a6fdff63ecc4b382a5092c0020fb7b42 Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Mon, 11 Apr 2016 11:48:42 -0500 -Subject: [PATCH 166/226] staging: fsl-mc: DPAA2 overview readme update - -incorporated feedback from review comments, other misc cleanup/tweaks - -Signed-off-by: Stuart Yoder -Acked-by: German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/README.txt | 138 +++++++++++++++++++++---------------- - 1 file changed, 80 insertions(+), 58 deletions(-) - ---- a/drivers/staging/fsl-mc/README.txt -+++ b/drivers/staging/fsl-mc/README.txt -@@ -11,11 +11,11 @@ Contents summary - -Overview of DPAA2 objects - -DPAA2 Linux driver architecture overview - -bus driver -- -dprc driver -+ -DPRC driver - -allocator -- -dpio driver -+ -DPIO driver - -Ethernet -- -mac -+ -MAC - - DPAA2 Overview - -------------- -@@ -37,6 +37,9 @@ interfaces, an L2 switch, or accelerator - The MC provides memory-mapped I/O command interfaces (MC portals) - which DPAA2 software drivers use to operate on DPAA2 objects: - -+The diagram below shows an overview of the DPAA2 resource management -+architecture: -+ - +--------------------------------------+ - | OS | - | DPAA2 drivers | -@@ -77,13 +80,13 @@ DPIO objects. - - Overview of DPAA2 Objects - ------------------------- --The section provides a brief overview of some key objects --in the DPAA2 hardware. A simple scenario is described illustrating --the objects involved in creating a network interfaces. -+The section provides a brief overview of some key DPAA2 objects. -+A simple scenario is described illustrating the objects involved -+in creating a network interfaces. - - -DPRC (Datapath Resource Container) - -- A DPRC is an container object that holds all the other -+ A DPRC is a container object that holds all the other - types of DPAA2 objects. In the example diagram below there - are 8 objects of 5 types (DPMCP, DPIO, DPBP, DPNI, and DPMAC) - in the container. -@@ -101,23 +104,23 @@ the objects involved in creating a netwo - | | - +---------------------------------------------------------+ - -- From the point of view of an OS, a DPRC is bus-like. Like -- a plug-and-play bus, such as PCI, DPRC commands can be used to -- enumerate the contents of the DPRC, discover the hardware -- objects present (including mappable regions and interrupts). -+ From the point of view of an OS, a DPRC behaves similar to a plug and -+ play bus, like PCI. DPRC commands can be used to enumerate the contents -+ of the DPRC, discover the hardware objects present (including mappable -+ regions and interrupts). - -- dprc.1 (bus) -+ DPRC.1 (bus) - | - +--+--------+-------+-------+-------+ - | | | | | -- dpmcp.1 dpio.1 dpbp.1 dpni.1 dpmac.1 -- dpmcp.2 dpio.2 -- dpmcp.3 -+ DPMCP.1 DPIO.1 DPBP.1 DPNI.1 DPMAC.1 -+ DPMCP.2 DPIO.2 -+ DPMCP.3 - - Hardware objects can be created and destroyed dynamically, providing - the ability to hot plug/unplug objects in and out of the DPRC. - -- A DPRC has a mappable mmio region (an MC portal) that can be used -+ A DPRC has a mappable MMIO region (an MC portal) that can be used - to send MC commands. It has an interrupt for status events (like - hotplug). - -@@ -137,10 +140,11 @@ the objects involved in creating a netwo - A typical Ethernet NIC is monolithic-- the NIC device contains TX/RX - queuing mechanisms, configuration mechanisms, buffer management, - physical ports, and interrupts. DPAA2 uses a more granular approach -- utilizing multiple hardware objects. Each object has specialized -- functions, and are used together by software to provide Ethernet network -- interface functionality. This approach provides efficient use of finite -- hardware resources, flexibility, and performance advantages. -+ utilizing multiple hardware objects. Each object provides specialized -+ functions. Groups of these objects are used by software to provide -+ Ethernet network interface functionality. This approach provides -+ efficient use of finite hardware resources, flexibility, and -+ performance advantages. - - The diagram below shows the objects needed for a simple - network interface configuration on a system with 2 CPUs. -@@ -168,46 +172,52 @@ the objects involved in creating a netwo - - Below the objects are described. For each object a brief description - is provided along with a summary of the kinds of operations the object -- supports and a summary of key resources of the object (mmio regions -- and irqs). -+ supports and a summary of key resources of the object (MMIO regions -+ and IRQs). - - -DPMAC (Datapath Ethernet MAC): represents an Ethernet MAC, a - hardware device that connects to an Ethernet PHY and allows - physical transmission and reception of Ethernet frames. -- -mmio regions: none -- -irqs: dpni link change -+ -MMIO regions: none -+ -IRQs: DPNI link change - -commands: set link up/down, link config, get stats, -- irq config, enable, reset -+ IRQ config, enable, reset - - -DPNI (Datapath Network Interface): contains TX/RX queues, -- network interface configuration, and rx buffer pool configuration -- mechanisms. -- -mmio regions: none -- -irqs: link state -+ network interface configuration, and RX buffer pool configuration -+ mechanisms. The TX/RX queues are in memory and are identified by -+ queue number. -+ -MMIO regions: none -+ -IRQs: link state - -commands: port config, offload config, queue config, -- parse/classify config, irq config, enable, reset -+ parse/classify config, IRQ config, enable, reset - - -DPIO (Datapath I/O): provides interfaces to enqueue and dequeue -- packets and do hardware buffer pool management operations. For -- optimum performance there is typically DPIO per CPU. This allows -- each CPU to perform simultaneous enqueue/dequeue operations. -- -mmio regions: queue operations, buffer mgmt -- -irqs: data availability, congestion notification, buffer -+ packets and do hardware buffer pool management operations. The DPAA2 -+ architecture separates the mechanism to access queues (the DPIO object) -+ from the queues themselves. The DPIO provides an MMIO interface to -+ enqueue/dequeue packets. To enqueue something a descriptor is written -+ to the DPIO MMIO region, which includes the target queue number. -+ There will typically be one DPIO assigned to each CPU. This allows all -+ CPUs to simultaneously perform enqueue/dequeued operations. DPIOs are -+ expected to be shared by different DPAA2 drivers. -+ -MMIO regions: queue operations, buffer management -+ -IRQs: data availability, congestion notification, buffer - pool depletion -- -commands: irq config, enable, reset -+ -commands: IRQ config, enable, reset - - -DPBP (Datapath Buffer Pool): represents a hardware buffer - pool. -- -mmio regions: none -- -irqs: none -+ -MMIO regions: none -+ -IRQs: none - -commands: enable, reset - - -DPMCP (Datapath MC Portal): provides an MC command portal. - Used by drivers to send commands to the MC to manage - objects. -- -mmio regions: MC command portal -- -irqs: command completion -- -commands: irq config, enable, reset -+ -MMIO regions: MC command portal -+ -IRQs: command completion -+ -commands: IRQ config, enable, reset - - Object Connections - ------------------ -@@ -268,22 +278,22 @@ of each driver follows. - | Stack | - +------------+ +------------+ - | Allocator |. . . . . . . | Ethernet | -- |(dpmcp,dpbp)| | (dpni) | -+ |(DPMCP,DPBP)| | (DPNI) | - +-.----------+ +---+---+----+ - . . ^ | - . . | | dequeue> - +-------------+ . | | - | DPRC driver | . +---+---V----+ +---------+ -- | (dprc) | . . . . . .| DPIO driver| | MAC | -- +----------+--+ | (dpio) | | (dpmac) | -+ | (DPRC) | . . . . . .| DPIO driver| | MAC | -+ +----------+--+ | (DPIO) | | (DPMAC) | - | +------+-----+ +-----+---+ - | | | - | | | - +----+--------------+ | +--+---+ -- | mc-bus driver | | | PHY | -+ | MC-bus driver | | | PHY | - | | | |driver| -- | /fsl-mc@80c000000 | | +--+---+ -+ | /soc/fsl-mc | | +--+---+ - +-------------------+ | | - | | - ================================ HARDWARE =========|=================|====== -@@ -298,25 +308,27 @@ of each driver follows. - - A brief description of each driver is provided below. - -- mc-bus driver -+ MC-bus driver - ------------- -- The mc-bus driver is a platform driver and is probed from an -- "/fsl-mc@xxxx" node in the device tree passed in by boot firmware. -- It is responsible for bootstrapping the DPAA2 kernel infrastructure. -+ The MC-bus driver is a platform driver and is probed from a -+ node in the device tree (compatible "fsl,qoriq-mc") passed in by boot -+ firmware. It is responsible for bootstrapping the DPAA2 kernel -+ infrastructure. - Key functions include: - -registering a new bus type named "fsl-mc" with the kernel, - and implementing bus call-backs (e.g. match/uevent/dev_groups) -- -implemeting APIs for DPAA2 driver registration and for device -+ -implementing APIs for DPAA2 driver registration and for device - add/remove -- -creates an MSI irq domain -- -do a device add of the 'root' DPRC device, which is needed -- to bootstrap things -+ -creates an MSI IRQ domain -+ -doing a 'device add' to expose the 'root' DPRC, in turn triggering -+ a bind of the root DPRC to the DPRC driver - - DPRC driver - ----------- -- The dprc-driver is bound DPRC objects and does runtime management -+ The DPRC driver is bound to DPRC objects and does runtime management - of a bus instance. It performs the initial bus scan of the DPRC -- and handles interrupts for container events such as hot plug. -+ and handles interrupts for container events such as hot plug by -+ re-scanning the DPRC. - - Allocator - ---------- -@@ -334,14 +346,20 @@ A brief description of each driver is pr - DPIO driver - ----------- - The DPIO driver is bound to DPIO objects and provides services that allow -- other drivers such as the Ethernet driver to receive and transmit data. -+ other drivers such as the Ethernet driver to enqueue and dequeue data for -+ their respective objects. - Key services include: - -data availability notifications - -hardware queuing operations (enqueue and dequeue of data) - -hardware buffer pool management - -+ To transmit a packet the Ethernet driver puts data on a queue and -+ invokes a DPIO API. For receive, the Ethernet driver registers -+ a data availability notification callback. To dequeue a packet -+ a DPIO API is used. -+ - There is typically one DPIO object per physical CPU for optimum -- performance, allowing each CPU to simultaneously enqueue -+ performance, allowing different CPUs to simultaneously enqueue - and dequeue data. - - The DPIO driver operates on behalf of all DPAA2 drivers -@@ -362,3 +380,7 @@ A brief description of each driver is pr - by the appropriate PHY driver via an mdio bus. The MAC driver - plays a role of being a proxy between the PHY driver and the - MC. It does this proxy via the MC commands to a DPMAC object. -+ If the PHY driver signals a link change, the MAC driver notifies -+ the MC via a DPMAC command. If a network interface is brought -+ up or down, the MC notifies the DPMAC driver via an interrupt and -+ the driver can take appropriate action. diff --git a/target/linux/layerscape/patches-4.4/7167-staging-fsl-mc-update-dpmcp-binary-interface-to-v3.0.patch b/target/linux/layerscape/patches-4.4/7167-staging-fsl-mc-update-dpmcp-binary-interface-to-v3.0.patch deleted file mode 100644 index b759606140..0000000000 --- a/target/linux/layerscape/patches-4.4/7167-staging-fsl-mc-update-dpmcp-binary-interface-to-v3.0.patch +++ /dev/null @@ -1,123 +0,0 @@ -From fa245614c92ffbdaec6a56552032432b5343b1dc Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Mon, 11 Apr 2016 11:48:48 -0500 -Subject: [PATCH 167/226] staging: fsl-mc: update dpmcp binary interface to - v3.0 - -Signed-off-by: Stuart Yoder -Acked-by: German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dpmcp-cmd.h | 5 ++--- - drivers/staging/fsl-mc/bus/dpmcp.c | 35 ++------------------------------ - drivers/staging/fsl-mc/bus/dpmcp.h | 10 ++------- - 3 files changed, 6 insertions(+), 44 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dpmcp-cmd.h -+++ b/drivers/staging/fsl-mc/bus/dpmcp-cmd.h -@@ -33,8 +33,8 @@ - #define _FSL_DPMCP_CMD_H - - /* DPMCP Version */ --#define DPMCP_VER_MAJOR 2 --#define DPMCP_VER_MINOR 1 -+#define DPMCP_VER_MAJOR 3 -+#define DPMCP_VER_MINOR 0 - - /* Command IDs */ - #define DPMCP_CMDID_CLOSE 0x800 -@@ -52,6 +52,5 @@ - #define DPMCP_CMDID_SET_IRQ_MASK 0x014 - #define DPMCP_CMDID_GET_IRQ_MASK 0x015 - #define DPMCP_CMDID_GET_IRQ_STATUS 0x016 --#define DPMCP_CMDID_CLEAR_IRQ_STATUS 0x017 - - #endif /* _FSL_DPMCP_CMD_H */ ---- a/drivers/staging/fsl-mc/bus/dpmcp.c -+++ b/drivers/staging/fsl-mc/bus/dpmcp.c -@@ -213,7 +213,7 @@ int dpmcp_set_irq(struct fsl_mc_io *mc_i - cmd.params[0] |= mc_enc(0, 8, irq_index); - cmd.params[0] |= mc_enc(32, 32, irq_cfg->val); - cmd.params[1] |= mc_enc(0, 64, irq_cfg->paddr); -- cmd.params[2] |= mc_enc(0, 32, irq_cfg->user_irq_id); -+ cmd.params[2] |= mc_enc(0, 32, irq_cfg->irq_num); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -@@ -254,7 +254,7 @@ int dpmcp_get_irq(struct fsl_mc_io *mc_i - /* retrieve response parameters */ - irq_cfg->val = (u32)mc_dec(cmd.params[0], 0, 32); - irq_cfg->paddr = (u64)mc_dec(cmd.params[1], 0, 64); -- irq_cfg->user_irq_id = (int)mc_dec(cmd.params[2], 0, 32); -+ irq_cfg->irq_num = (int)mc_dec(cmd.params[2], 0, 32); - *type = (int)mc_dec(cmd.params[2], 32, 32); - return 0; - } -@@ -435,37 +435,6 @@ int dpmcp_get_irq_status(struct fsl_mc_i - } - - /** -- * dpmcp_clear_irq_status() - Clear a pending interrupt's status -- * -- * @mc_io: Pointer to MC portal's I/O object -- * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -- * @token: Token of DPMCP object -- * @irq_index: The interrupt index to configure -- * @status: Bits to clear (W1C) - one bit per cause: -- * 0 = don't change -- * 1 = clear status bit -- * -- * Return: '0' on Success; Error code otherwise. -- */ --int dpmcp_clear_irq_status(struct fsl_mc_io *mc_io, -- u32 cmd_flags, -- u16 token, -- u8 irq_index, -- u32 status) --{ -- struct mc_command cmd = { 0 }; -- -- /* prepare command */ -- cmd.header = mc_encode_cmd_header(DPMCP_CMDID_CLEAR_IRQ_STATUS, -- cmd_flags, token); -- cmd.params[0] |= mc_enc(0, 32, status); -- cmd.params[0] |= mc_enc(32, 8, irq_index); -- -- /* send command to mc*/ -- return mc_send_command(mc_io, &cmd); --} -- --/** - * dpmcp_get_attributes - Retrieve DPMCP attributes. - * - * @mc_io: Pointer to MC portal's I/O object ---- a/drivers/staging/fsl-mc/bus/dpmcp.h -+++ b/drivers/staging/fsl-mc/bus/dpmcp.h -@@ -82,12 +82,12 @@ int dpmcp_reset(struct fsl_mc_io *mc_io, - * struct dpmcp_irq_cfg - IRQ configuration - * @paddr: Address that must be written to signal a message-based interrupt - * @val: Value to write into irq_addr address -- * @user_irq_id: A user defined number associated with this IRQ -+ * @irq_num: A user defined number associated with this IRQ - */ - struct dpmcp_irq_cfg { - uint64_t paddr; - uint32_t val; -- int user_irq_id; -+ int irq_num; - }; - - int dpmcp_set_irq(struct fsl_mc_io *mc_io, -@@ -133,12 +133,6 @@ int dpmcp_get_irq_status(struct fsl_mc_i - uint8_t irq_index, - uint32_t *status); - --int dpmcp_clear_irq_status(struct fsl_mc_io *mc_io, -- uint32_t cmd_flags, -- uint16_t token, -- uint8_t irq_index, -- uint32_t status); -- - /** - * struct dpmcp_attr - Structure representing DPMCP attributes - * @id: DPMCP object ID diff --git a/target/linux/layerscape/patches-4.4/7168-staging-fsl-mc-update-dpbp-binary-interface-to-v2.2.patch b/target/linux/layerscape/patches-4.4/7168-staging-fsl-mc-update-dpbp-binary-interface-to-v2.2.patch deleted file mode 100644 index 474baf42be..0000000000 --- a/target/linux/layerscape/patches-4.4/7168-staging-fsl-mc-update-dpbp-binary-interface-to-v2.2.patch +++ /dev/null @@ -1,208 +0,0 @@ -From de0fa9842d52e4e80576d378f32aa9ca76a4270b Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Mon, 11 Apr 2016 11:48:54 -0500 -Subject: [PATCH 168/226] staging: fsl-mc: update dpbp binary interface to - v2.2 - -Signed-off-by: Stuart Yoder -Acked-by: German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dpbp.c | 77 ++++++++++++++++++++++++++++- - drivers/staging/fsl-mc/include/dpbp-cmd.h | 4 +- - drivers/staging/fsl-mc/include/dpbp.h | 51 ++++++++++++++++++- - 3 files changed, 127 insertions(+), 5 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dpbp.c -+++ b/drivers/staging/fsl-mc/bus/dpbp.c -@@ -293,7 +293,7 @@ int dpbp_set_irq(struct fsl_mc_io *mc_io - cmd.params[0] |= mc_enc(0, 8, irq_index); - cmd.params[0] |= mc_enc(32, 32, irq_cfg->val); - cmd.params[1] |= mc_enc(0, 64, irq_cfg->addr); -- cmd.params[2] |= mc_enc(0, 32, irq_cfg->user_irq_id); -+ cmd.params[2] |= mc_enc(0, 32, irq_cfg->irq_num); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -@@ -334,7 +334,7 @@ int dpbp_get_irq(struct fsl_mc_io *mc_io - /* retrieve response parameters */ - irq_cfg->val = (u32)mc_dec(cmd.params[0], 0, 32); - irq_cfg->addr = (u64)mc_dec(cmd.params[1], 0, 64); -- irq_cfg->user_irq_id = (int)mc_dec(cmd.params[2], 0, 32); -+ irq_cfg->irq_num = (int)mc_dec(cmd.params[2], 0, 32); - *type = (int)mc_dec(cmd.params[2], 32, 32); - return 0; - } -@@ -502,6 +502,7 @@ int dpbp_get_irq_status(struct fsl_mc_io - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_STATUS, - cmd_flags, token); -+ cmd.params[0] |= mc_enc(0, 32, *status); - cmd.params[0] |= mc_enc(32, 8, irq_index); - - /* send command to mc*/ -@@ -580,3 +581,75 @@ int dpbp_get_attributes(struct fsl_mc_io - return 0; - } - EXPORT_SYMBOL(dpbp_get_attributes); -+ -+/** -+ * dpbp_set_notifications() - Set notifications towards software -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPBP object -+ * @cfg: notifications configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpbp_set_notifications(struct fsl_mc_io *mc_io, -+ u32 cmd_flags, -+ u16 token, -+ struct dpbp_notification_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_NOTIFICATIONS, -+ cmd_flags, -+ token); -+ -+ cmd.params[0] |= mc_enc(0, 32, cfg->depletion_entry); -+ cmd.params[0] |= mc_enc(32, 32, cfg->depletion_exit); -+ cmd.params[1] |= mc_enc(0, 32, cfg->surplus_entry); -+ cmd.params[1] |= mc_enc(32, 32, cfg->surplus_exit); -+ cmd.params[2] |= mc_enc(0, 16, cfg->options); -+ cmd.params[3] |= mc_enc(0, 64, cfg->message_ctx); -+ cmd.params[4] |= mc_enc(0, 64, cfg->message_iova); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+/** -+ * dpbp_get_notifications() - Get the notifications configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPBP object -+ * @cfg: notifications configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpbp_get_notifications(struct fsl_mc_io *mc_io, -+ u32 cmd_flags, -+ u16 token, -+ struct dpbp_notification_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_NOTIFICATIONS, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ cfg->depletion_entry = (u32)mc_dec(cmd.params[0], 0, 32); -+ cfg->depletion_exit = (u32)mc_dec(cmd.params[0], 32, 32); -+ cfg->surplus_entry = (u32)mc_dec(cmd.params[1], 0, 32); -+ cfg->surplus_exit = (u32)mc_dec(cmd.params[1], 32, 32); -+ cfg->options = (u16)mc_dec(cmd.params[2], 0, 16); -+ cfg->message_ctx = (u64)mc_dec(cmd.params[3], 0, 64); -+ cfg->message_iova = (u64)mc_dec(cmd.params[4], 0, 64); -+ -+ return 0; -+} ---- a/drivers/staging/fsl-mc/include/dpbp-cmd.h -+++ b/drivers/staging/fsl-mc/include/dpbp-cmd.h -@@ -34,7 +34,7 @@ - - /* DPBP Version */ - #define DPBP_VER_MAJOR 2 --#define DPBP_VER_MINOR 1 -+#define DPBP_VER_MINOR 2 - - /* Command IDs */ - #define DPBP_CMDID_CLOSE 0x800 -@@ -57,4 +57,6 @@ - #define DPBP_CMDID_GET_IRQ_STATUS 0x016 - #define DPBP_CMDID_CLEAR_IRQ_STATUS 0x017 - -+#define DPBP_CMDID_SET_NOTIFICATIONS 0x01b0 -+#define DPBP_CMDID_GET_NOTIFICATIONS 0x01b1 - #endif /* _FSL_DPBP_CMD_H */ ---- a/drivers/staging/fsl-mc/include/dpbp.h -+++ b/drivers/staging/fsl-mc/include/dpbp.h -@@ -85,12 +85,12 @@ int dpbp_reset(struct fsl_mc_io *mc_io, - * struct dpbp_irq_cfg - IRQ configuration - * @addr: Address that must be written to signal a message-based interrupt - * @val: Value to write into irq_addr address -- * @user_irq_id: A user defined number associated with this IRQ -+ * @irq_num: A user defined number associated with this IRQ - */ - struct dpbp_irq_cfg { - u64 addr; - u32 val; -- int user_irq_id; -+ int irq_num; - }; - - int dpbp_set_irq(struct fsl_mc_io *mc_io, -@@ -168,6 +168,53 @@ int dpbp_get_attributes(struct fsl_mc_io - u16 token, - struct dpbp_attr *attr); - -+/** -+ * DPBP notifications options -+ */ -+ -+/** -+ * BPSCN write will attempt to allocate into a cache (coherent write) -+ */ -+#define DPBP_NOTIF_OPT_COHERENT_WRITE 0x00000001 -+ -+/** -+ * struct dpbp_notification_cfg - Structure representing DPBP notifications -+ * towards software -+ * @depletion_entry: below this threshold the pool is "depleted"; -+ * set it to '0' to disable it -+ * @depletion_exit: greater than or equal to this threshold the pool exit its -+ * "depleted" state -+ * @surplus_entry: above this threshold the pool is in "surplus" state; -+ * set it to '0' to disable it -+ * @surplus_exit: less than or equal to this threshold the pool exit its -+ * "surplus" state -+ * @message_iova: MUST be given if either 'depletion_entry' or 'surplus_entry' -+ * is not '0' (enable); I/O virtual address (must be in DMA-able memory), -+ * must be 16B aligned. -+ * @message_ctx: The context that will be part of the BPSCN message and will -+ * be written to 'message_iova' -+ * @options: Mask of available options; use 'DPBP_NOTIF_OPT_' values -+ */ -+struct dpbp_notification_cfg { -+ u32 depletion_entry; -+ u32 depletion_exit; -+ u32 surplus_entry; -+ u32 surplus_exit; -+ u64 message_iova; -+ u64 message_ctx; -+ u16 options; -+}; -+ -+int dpbp_set_notifications(struct fsl_mc_io *mc_io, -+ u32 cmd_flags, -+ u16 token, -+ struct dpbp_notification_cfg *cfg); -+ -+int dpbp_get_notifications(struct fsl_mc_io *mc_io, -+ u32 cmd_flags, -+ u16 token, -+ struct dpbp_notification_cfg *cfg); -+ - /** @} */ - - #endif /* __FSL_DPBP_H */ diff --git a/target/linux/layerscape/patches-4.4/7169-staging-fsl-mc-update-dprc-binary-interface-to-v5.1.patch b/target/linux/layerscape/patches-4.4/7169-staging-fsl-mc-update-dprc-binary-interface-to-v5.1.patch deleted file mode 100644 index 4db299803d..0000000000 --- a/target/linux/layerscape/patches-4.4/7169-staging-fsl-mc-update-dprc-binary-interface-to-v5.1.patch +++ /dev/null @@ -1,206 +0,0 @@ -From 45dce4cd82ddc618ade56747620a2a29f7d9a99d Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Mon, 11 Apr 2016 11:48:59 -0500 -Subject: [PATCH 169/226] staging: fsl-mc: update dprc binary interface to - v5.1 - -The meaning of the "status" parameter in dprc_get_irq_status -has changed, and this patch updates the flib and caller -of the API. - -Signed-off-by: Stuart Yoder -Acked-by: German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-cmd.h | 4 ++-- - drivers/staging/fsl-mc/bus/dprc-driver.c | 1 + - drivers/staging/fsl-mc/bus/dprc.c | 26 +++++++++++++------------- - drivers/staging/fsl-mc/bus/mc-msi.c | 2 +- - drivers/staging/fsl-mc/include/dprc.h | 19 ++++++++++++------- - 5 files changed, 29 insertions(+), 23 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dprc-cmd.h -+++ b/drivers/staging/fsl-mc/bus/dprc-cmd.h -@@ -41,8 +41,8 @@ - #define _FSL_DPRC_CMD_H - - /* DPRC Version */ --#define DPRC_VER_MAJOR 4 --#define DPRC_VER_MINOR 0 -+#define DPRC_VER_MAJOR 5 -+#define DPRC_VER_MINOR 1 - - /* Command IDs */ - #define DPRC_CMDID_CLOSE 0x800 ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -423,6 +423,7 @@ static irqreturn_t dprc_irq0_handler_thr - if (WARN_ON(!msi_desc || msi_desc->irq != (u32)irq_num)) - goto out; - -+ status = 0; - error = dprc_get_irq_status(mc_io, 0, mc_dev->mc_handle, 0, - &status); - if (error < 0) { ---- a/drivers/staging/fsl-mc/bus/dprc.c -+++ b/drivers/staging/fsl-mc/bus/dprc.c -@@ -265,7 +265,7 @@ int dprc_get_irq(struct fsl_mc_io *mc_io - /* retrieve response parameters */ - irq_cfg->val = mc_dec(cmd.params[0], 0, 32); - irq_cfg->paddr = mc_dec(cmd.params[1], 0, 64); -- irq_cfg->user_irq_id = mc_dec(cmd.params[2], 0, 32); -+ irq_cfg->irq_num = mc_dec(cmd.params[2], 0, 32); - *type = mc_dec(cmd.params[2], 32, 32); - - return 0; -@@ -296,7 +296,7 @@ int dprc_set_irq(struct fsl_mc_io *mc_io - cmd.params[0] |= mc_enc(32, 8, irq_index); - cmd.params[0] |= mc_enc(0, 32, irq_cfg->val); - cmd.params[1] |= mc_enc(0, 64, irq_cfg->paddr); -- cmd.params[2] |= mc_enc(0, 32, irq_cfg->user_irq_id); -+ cmd.params[2] |= mc_enc(0, 32, irq_cfg->irq_num); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -@@ -466,6 +466,7 @@ int dprc_get_irq_status(struct fsl_mc_io - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ_STATUS, - cmd_flags, token); -+ cmd.params[0] |= mc_enc(0, 32, *status); - cmd.params[0] |= mc_enc(32, 8, irq_index); - - /* send command to mc*/ -@@ -948,6 +949,7 @@ int dprc_get_obj(struct fsl_mc_io *mc_io - obj_desc->state = mc_dec(cmd.params[1], 32, 32); - obj_desc->ver_major = mc_dec(cmd.params[2], 0, 16); - obj_desc->ver_minor = mc_dec(cmd.params[2], 16, 16); -+ obj_desc->flags = mc_dec(cmd.params[2], 32, 16); - obj_desc->type[0] = mc_dec(cmd.params[3], 0, 8); - obj_desc->type[1] = mc_dec(cmd.params[3], 8, 8); - obj_desc->type[2] = mc_dec(cmd.params[3], 16, 8); -@@ -1042,6 +1044,7 @@ int dprc_get_obj_desc(struct fsl_mc_io * - obj_desc->state = (u32)mc_dec(cmd.params[1], 32, 32); - obj_desc->ver_major = (u16)mc_dec(cmd.params[2], 0, 16); - obj_desc->ver_minor = (u16)mc_dec(cmd.params[2], 16, 16); -+ obj_desc->flags = mc_dec(cmd.params[2], 32, 16); - obj_desc->type[0] = (char)mc_dec(cmd.params[3], 0, 8); - obj_desc->type[1] = (char)mc_dec(cmd.params[3], 8, 8); - obj_desc->type[2] = (char)mc_dec(cmd.params[3], 16, 8); -@@ -1108,7 +1111,7 @@ int dprc_set_obj_irq(struct fsl_mc_io *m - cmd.params[0] |= mc_enc(32, 8, irq_index); - cmd.params[0] |= mc_enc(0, 32, irq_cfg->val); - cmd.params[1] |= mc_enc(0, 64, irq_cfg->paddr); -- cmd.params[2] |= mc_enc(0, 32, irq_cfg->user_irq_id); -+ cmd.params[2] |= mc_enc(0, 32, irq_cfg->irq_num); - cmd.params[2] |= mc_enc(32, 32, obj_id); - cmd.params[3] |= mc_enc(0, 8, obj_type[0]); - cmd.params[3] |= mc_enc(8, 8, obj_type[1]); -@@ -1189,7 +1192,7 @@ int dprc_get_obj_irq(struct fsl_mc_io *m - /* retrieve response parameters */ - irq_cfg->val = (u32)mc_dec(cmd.params[0], 0, 32); - irq_cfg->paddr = (u64)mc_dec(cmd.params[1], 0, 64); -- irq_cfg->user_irq_id = (int)mc_dec(cmd.params[2], 0, 32); -+ irq_cfg->irq_num = (int)mc_dec(cmd.params[2], 0, 32); - *type = (int)mc_dec(cmd.params[2], 32, 32); - - return 0; -@@ -1437,14 +1440,8 @@ EXPORT_SYMBOL(dprc_set_obj_label); - * @endpoint1: Endpoint 1 configuration parameters - * @endpoint2: Endpoint 2 configuration parameters - * @cfg: Connection configuration. The connection configuration is ignored for -- * connections made to DPMAC objects, where rate is set according to -- * MAC configuration. -- * The committed rate is the guaranteed rate for the connection. -- * The maximum rate is an upper limit allowed for the connection; it is -- * expected to be equal or higher than the committed rate. -- * When committed and maximum rates are both zero, the connection is set -- * to "best effort" mode, having lower priority compared to connections -- * with committed or maximum rates. -+ * connections made to DPMAC objects, where rate is retrieved from the -+ * MAC configuration. - * - * Return: '0' on Success; Error code otherwise. - */ -@@ -1555,7 +1552,10 @@ int dprc_disconnect(struct fsl_mc_io *mc - * @token: Token of DPRC object - * @endpoint1: Endpoint 1 configuration parameters - * @endpoint2: Returned endpoint 2 configuration parameters --* @state: Returned link state: 1 - link is up, 0 - link is down -+* @state: Returned link state: -+* 1 - link is up; -+* 0 - link is down; -+* -1 - no connection (endpoint2 information is irrelevant) - * - * Return: '0' on Success; -ENAVAIL if connection does not exist. - */ ---- a/drivers/staging/fsl-mc/bus/mc-msi.c -+++ b/drivers/staging/fsl-mc/bus/mc-msi.c -@@ -65,7 +65,7 @@ static void __fsl_mc_msi_write_msg(struc - irq_cfg.paddr = ((u64)msi_desc->msg.address_hi << 32) | - msi_desc->msg.address_lo; - irq_cfg.val = msi_desc->msg.data; -- irq_cfg.user_irq_id = msi_desc->irq; -+ irq_cfg.irq_num = msi_desc->irq; - - if (owner_mc_dev == mc_bus_dev) { - /* ---- a/drivers/staging/fsl-mc/include/dprc.h -+++ b/drivers/staging/fsl-mc/include/dprc.h -@@ -94,11 +94,6 @@ int dprc_close(struct fsl_mc_io *mc_io, - */ - #define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED 0x00000008 - --/* IOMMU bypass - indicates whether objects of this container are permitted -- * to bypass the IOMMU. -- */ --#define DPRC_CFG_OPT_IOMMU_BYPASS 0x00000010 -- - /* AIOP - Indicates that container belongs to AIOP. */ - #define DPRC_CFG_OPT_AIOP 0x00000020 - -@@ -173,12 +168,12 @@ int dprc_reset_container(struct fsl_mc_i - * struct dprc_irq_cfg - IRQ configuration - * @paddr: Address that must be written to signal a message-based interrupt - * @val: Value to write into irq_addr address -- * @user_irq_id: A user defined number associated with this IRQ -+ * @irq_num: A user defined number associated with this IRQ - */ - struct dprc_irq_cfg { - phys_addr_t paddr; - u32 val; -- int user_irq_id; -+ int irq_num; - }; - - int dprc_set_irq(struct fsl_mc_io *mc_io, -@@ -353,6 +348,14 @@ int dprc_get_obj_count(struct fsl_mc_io - #define DPRC_OBJ_STATE_PLUGGED 0x00000002 - - /** -+ * Shareability flag - Object flag indicating no memory shareability. -+ * the object generates memory accesses that are non coherent with other -+ * masters; -+ * user is responsible for proper memory handling through IOMMU configuration. -+ */ -+#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001 -+ -+/** - * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj() - * @type: Type of object: NULL terminated string - * @id: ID of logical object resource -@@ -363,6 +366,7 @@ int dprc_get_obj_count(struct fsl_mc_io - * @region_count: Number of mappable regions supported by the object - * @state: Object state: combination of DPRC_OBJ_STATE_ states - * @label: Object label -+ * @flags: Object's flags - */ - struct dprc_obj_desc { - char type[16]; -@@ -374,6 +378,7 @@ struct dprc_obj_desc { - u8 region_count; - u32 state; - char label[16]; -+ u16 flags; - }; - - int dprc_get_obj(struct fsl_mc_io *mc_io, diff --git a/target/linux/layerscape/patches-4.4/7170-staging-fsl-mc-don-t-use-object-versions-to-make-bin.patch b/target/linux/layerscape/patches-4.4/7170-staging-fsl-mc-don-t-use-object-versions-to-make-bin.patch deleted file mode 100644 index 2224d457e8..0000000000 --- a/target/linux/layerscape/patches-4.4/7170-staging-fsl-mc-don-t-use-object-versions-to-make-bin.patch +++ /dev/null @@ -1,136 +0,0 @@ -From 9382e1723e4de9832407f7e65bd4812b31e5a51d Mon Sep 17 00:00:00 2001 -From: Itai Katz -Date: Mon, 11 Apr 2016 11:55:40 -0500 -Subject: [PATCH 170/226] staging: fsl-mc: don't use object versions to make - binding decisions - -Up until now if the object version expected by a driver (in the API header -file) did not match the actual object version in the MC hardware the bus -driver refused to bind the object to the driver or printed out WARN_ON -dumps. - -This patch removes those checks, and the responsibility of object version -checking should now be done in the object drivers themselves. If the actual -version discovered is not supported, the driver's probe function should fail. -Drivers should use version checks to support new features and provide -backwards compatibility if at all possible. - -This patch also removes the checks that caused bus driver probing to fail -if the overall MC version discovered did not match the firmware version -from the API header...this was too strict. The overall MC version is -informational like a release number, and continues to be printed in the -boot log. - -Signed-off-by: Itai Katz -(Stuart: reworded commit log) -Signed-off-by: Stuart Yoder -Acked-by: German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 4 +-- - drivers/staging/fsl-mc/bus/mc-allocator.c | 6 ----- - drivers/staging/fsl-mc/bus/mc-bus.c | 38 +---------------------------- - 3 files changed, 2 insertions(+), 46 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -780,9 +780,7 @@ static int dprc_remove(struct fsl_mc_dev - static const struct fsl_mc_device_match_id match_id_table[] = { - { - .vendor = FSL_MC_VENDOR_FREESCALE, -- .obj_type = "dprc", -- .ver_major = DPRC_VER_MAJOR, -- .ver_minor = DPRC_VER_MINOR}, -+ .obj_type = "dprc"}, - {.vendor = 0x0}, - }; - ---- a/drivers/staging/fsl-mc/bus/mc-allocator.c -+++ b/drivers/staging/fsl-mc/bus/mc-allocator.c -@@ -709,20 +709,14 @@ static const struct fsl_mc_device_match_ - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dpbp", -- .ver_major = DPBP_VER_MAJOR, -- .ver_minor = DPBP_VER_MINOR - }, - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dpmcp", -- .ver_major = DPMCP_VER_MAJOR, -- .ver_minor = DPMCP_VER_MINOR - }, - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dpcon", -- .ver_major = DPCON_VER_MAJOR, -- .ver_minor = DPCON_VER_MINOR - }, - {.vendor = 0x0}, - }; ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -40,8 +40,6 @@ static int fsl_mc_bus_match(struct devic - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(drv); - bool found = false; -- bool major_version_mismatch = false; -- bool minor_version_mismatch = false; - - if (WARN_ON(!fsl_mc_bus_exists())) - goto out; -@@ -64,32 +62,12 @@ static int fsl_mc_bus_match(struct devic - for (id = mc_drv->match_id_table; id->vendor != 0x0; id++) { - if (id->vendor == mc_dev->obj_desc.vendor && - strcmp(id->obj_type, mc_dev->obj_desc.type) == 0) { -- if (id->ver_major == mc_dev->obj_desc.ver_major) { -- found = true; -- if (id->ver_minor != mc_dev->obj_desc.ver_minor) -- minor_version_mismatch = true; -- } else { -- major_version_mismatch = true; -- } -+ found = true; - - break; - } - } - -- if (major_version_mismatch) { -- dev_warn(dev, -- "Major version mismatch: driver version %u.%u, MC object version %u.%u\n", -- id->ver_major, id->ver_minor, -- mc_dev->obj_desc.ver_major, -- mc_dev->obj_desc.ver_minor); -- } else if (minor_version_mismatch) { -- dev_warn(dev, -- "Minor version mismatch: driver version %u.%u, MC object version %u.%u\n", -- id->ver_major, id->ver_minor, -- mc_dev->obj_desc.ver_major, -- mc_dev->obj_desc.ver_minor); -- } -- - out: - dev_dbg(dev, "%smatched\n", found ? "" : "not "); - return found; -@@ -722,20 +700,6 @@ static int fsl_mc_bus_probe(struct platf - "Freescale Management Complex Firmware version: %u.%u.%u\n", - mc_version.major, mc_version.minor, mc_version.revision); - -- if (mc_version.major < MC_VER_MAJOR) { -- dev_err(&pdev->dev, -- "ERROR: MC firmware version not supported by driver (driver version: %u.%u)\n", -- MC_VER_MAJOR, MC_VER_MINOR); -- error = -ENOTSUPP; -- goto error_cleanup_mc_io; -- } -- -- if (mc_version.major > MC_VER_MAJOR) { -- dev_warn(&pdev->dev, -- "WARNING: driver may not support newer MC firmware features (driver version: %u.%u)\n", -- MC_VER_MAJOR, MC_VER_MINOR); -- } -- - error = get_mc_addr_translation_ranges(&pdev->dev, - &mc->translation_ranges, - &mc->num_translation_ranges); diff --git a/target/linux/layerscape/patches-4.4/7171-staging-fsl-mc-set-up-coherent-dma-ops-for-added-dev.patch b/target/linux/layerscape/patches-4.4/7171-staging-fsl-mc-set-up-coherent-dma-ops-for-added-dev.patch deleted file mode 100644 index d6de805e6a..0000000000 --- a/target/linux/layerscape/patches-4.4/7171-staging-fsl-mc-set-up-coherent-dma-ops-for-added-dev.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 3657147d6fea1977c07373325626bf50fe15bcfc Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Mon, 11 Apr 2016 11:49:13 -0500 -Subject: [PATCH 171/226] staging: fsl-mc: set up coherent dma ops for added - devices - -Unless discovered devices have the no shareability flag set, -set up coherent dma ops for them. - -Signed-off-by: Stuart Yoder -Acked-by: German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -469,6 +469,10 @@ int fsl_mc_device_add(struct dprc_obj_de - goto error_cleanup_dev; - } - -+ /* Objects are coherent, unless 'no shareability' flag set. */ -+ if (!(obj_desc->flags & DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY)) -+ arch_setup_dma_ops(&mc_dev->dev, 0, 0, NULL, true); -+ - /* - * The device-specific probe callback will get invoked by device_add() - */ diff --git a/target/linux/layerscape/patches-4.4/7172-staging-fsl-mc-set-cacheable-flag-for-added-devices-.patch b/target/linux/layerscape/patches-4.4/7172-staging-fsl-mc-set-cacheable-flag-for-added-devices-.patch deleted file mode 100644 index 7de34d19ea..0000000000 --- a/target/linux/layerscape/patches-4.4/7172-staging-fsl-mc-set-cacheable-flag-for-added-devices-.patch +++ /dev/null @@ -1,30 +0,0 @@ -From f7011c18a26d40a07b837a79d0efdad795ad7250 Mon Sep 17 00:00:00 2001 -From: Itai Katz -Date: Mon, 11 Apr 2016 11:55:48 -0500 -Subject: [PATCH 172/226] staging: fsl-mc: set cacheable flag for added - devices if applicable - -Some DPAA2 devices have mmio regions that should be mapped as -cacheable by drivers. Set IORESOURCE_CACHEABLE in the region's -flags if applicable. - -Signed-off-by: Itai Katz -[Stuart: update subject and commit message] -Signed-off-by: Stuart Yoder -Acked-by: German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -354,6 +354,8 @@ static int fsl_mc_device_get_mmio_region - regions[i].end = regions[i].start + region_desc.size - 1; - regions[i].name = "fsl-mc object MMIO region"; - regions[i].flags = IORESOURCE_IO; -+ if (region_desc.flags & DPRC_REGION_CACHEABLE) -+ regions[i].flags |= IORESOURCE_CACHEABLE; - } - - mc_dev->regions = regions; diff --git a/target/linux/layerscape/patches-4.4/7173-staging-fsl-mc-get-version-of-root-dprc-from-MC-hard.patch b/target/linux/layerscape/patches-4.4/7173-staging-fsl-mc-get-version-of-root-dprc-from-MC-hard.patch deleted file mode 100644 index ade5b33c42..0000000000 --- a/target/linux/layerscape/patches-4.4/7173-staging-fsl-mc-get-version-of-root-dprc-from-MC-hard.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 2df13a365ecda7e3321cf9d4e1a9ebd63e58c28b Mon Sep 17 00:00:00 2001 -From: Itai Katz -Date: Mon, 11 Apr 2016 11:55:55 -0500 -Subject: [PATCH 173/226] staging: fsl-mc: get version of root dprc from MC - hardware - -The root dprc is discovered as a platform device in the device tree. The -version of that dprc was previously set using hardcoded values from the API -header in the kernel). This patch removes the use of the hardcoded version -numbers and instead reads the actual dprc version from the hardware. - -Signed-off-by: Itai Katz -(Stuart: resolved merge conflict, updated commit subject/log) -Signed-off-by: Stuart Yoder -Acked-by: German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 45 ++++++++++++++++++++++++++++------- - 1 file changed, 37 insertions(+), 8 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -229,11 +229,10 @@ static bool fsl_mc_is_root_dprc(struct d - return dev == root_dprc_dev; - } - --static int get_dprc_icid(struct fsl_mc_io *mc_io, -- int container_id, u16 *icid) -+static int get_dprc_attr(struct fsl_mc_io *mc_io, -+ int container_id, struct dprc_attributes *attr) - { - u16 dprc_handle; -- struct dprc_attributes attr; - int error; - - error = dprc_open(mc_io, 0, container_id, &dprc_handle); -@@ -242,15 +241,14 @@ static int get_dprc_icid(struct fsl_mc_i - return error; - } - -- memset(&attr, 0, sizeof(attr)); -- error = dprc_get_attributes(mc_io, 0, dprc_handle, &attr); -+ memset(attr, 0, sizeof(struct dprc_attributes)); -+ error = dprc_get_attributes(mc_io, 0, dprc_handle, attr); - if (error < 0) { - dev_err(mc_io->dev, "dprc_get_attributes() failed: %d\n", - error); - goto common_cleanup; - } - -- *icid = attr.icid; - error = 0; - - common_cleanup: -@@ -258,6 +256,34 @@ common_cleanup: - return error; - } - -+static int get_dprc_icid(struct fsl_mc_io *mc_io, -+ int container_id, u16 *icid) -+{ -+ struct dprc_attributes attr; -+ int error; -+ -+ error = get_dprc_attr(mc_io, container_id, &attr); -+ if (error == 0) -+ *icid = attr.icid; -+ -+ return error; -+} -+ -+static int get_dprc_version(struct fsl_mc_io *mc_io, -+ int container_id, u16 *major, u16 *minor) -+{ -+ struct dprc_attributes attr; -+ int error; -+ -+ error = get_dprc_attr(mc_io, container_id, &attr); -+ if (error == 0) { -+ *major = attr.version.major; -+ *minor = attr.version.minor; -+ } -+ -+ return error; -+} -+ - static int translate_mc_addr(struct fsl_mc_device *mc_dev, - enum dprc_region_type mc_region_type, - u64 mc_offset, phys_addr_t *phys_addr) -@@ -719,11 +745,14 @@ static int fsl_mc_bus_probe(struct platf - goto error_cleanup_mc_io; - } - -+ error = get_dprc_version(mc_io, container_id, -+ &obj_desc.ver_major, &obj_desc.ver_minor); -+ if (error < 0) -+ goto error_cleanup_mc_io; -+ - obj_desc.vendor = FSL_MC_VENDOR_FREESCALE; - strcpy(obj_desc.type, "dprc"); - obj_desc.id = container_id; -- obj_desc.ver_major = DPRC_VER_MAJOR; -- obj_desc.ver_minor = DPRC_VER_MINOR; - obj_desc.irq_count = 1; - obj_desc.region_count = 0; - diff --git a/target/linux/layerscape/patches-4.4/7174-staging-fsl-mc-add-dprc-version-check.patch b/target/linux/layerscape/patches-4.4/7174-staging-fsl-mc-add-dprc-version-check.patch deleted file mode 100644 index a5ec35c667..0000000000 --- a/target/linux/layerscape/patches-4.4/7174-staging-fsl-mc-add-dprc-version-check.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 653898b483e5448084b15214a8c20959b418dbe7 Mon Sep 17 00:00:00 2001 -From: Itai Katz -Date: Mon, 11 Apr 2016 11:56:05 -0500 -Subject: [PATCH 174/226] staging: fsl-mc: add dprc version check - -The dprc driver supports dprc version 5.0 and above. -This patch adds the code to check the version. - -Signed-off-by: Itai Katz -(Stuart: resolved merge conflicts, split dpseci quirk into separate patch) -Signed-off-by: Stuart Yoder -Acked-by: German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-cmd.h | 6 +++--- - drivers/staging/fsl-mc/bus/dprc-driver.c | 19 +++++++++++++++++++ - drivers/staging/fsl-mc/bus/mc-bus.c | 1 + - drivers/staging/fsl-mc/include/mc-private.h | 2 ++ - 4 files changed, 25 insertions(+), 3 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dprc-cmd.h -+++ b/drivers/staging/fsl-mc/bus/dprc-cmd.h -@@ -40,9 +40,9 @@ - #ifndef _FSL_DPRC_CMD_H - #define _FSL_DPRC_CMD_H - --/* DPRC Version */ --#define DPRC_VER_MAJOR 5 --#define DPRC_VER_MINOR 1 -+/* Minimal supported DPRC Version */ -+#define DPRC_MIN_VER_MAJOR 5 -+#define DPRC_MIN_VER_MINOR 0 - - /* Command IDs */ - #define DPRC_CMDID_CLOSE 0x800 ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -693,6 +693,25 @@ static int dprc_probe(struct fsl_mc_devi - goto error_cleanup_msi_domain; - } - -+ error = dprc_get_attributes(mc_dev->mc_io, 0, mc_dev->mc_handle, -+ &mc_bus->dprc_attr); -+ if (error < 0) { -+ dev_err(&mc_dev->dev, "dprc_get_attributes() failed: %d\n", -+ error); -+ goto error_cleanup_open; -+ } -+ -+ if (mc_bus->dprc_attr.version.major < DPRC_MIN_VER_MAJOR || -+ (mc_bus->dprc_attr.version.major == DPRC_MIN_VER_MAJOR && -+ mc_bus->dprc_attr.version.minor < DPRC_MIN_VER_MINOR)) { -+ dev_err(&mc_dev->dev, -+ "ERROR: DPRC version %d.%d not supported\n", -+ mc_bus->dprc_attr.version.major, -+ mc_bus->dprc_attr.version.minor); -+ error = -ENOTSUPP; -+ goto error_cleanup_open; -+ } -+ - mutex_init(&mc_bus->scan_mutex); - - /* ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -745,6 +745,7 @@ static int fsl_mc_bus_probe(struct platf - goto error_cleanup_mc_io; - } - -+ memset(&obj_desc, 0, sizeof(struct dprc_obj_desc)); - error = get_dprc_version(mc_io, container_id, - &obj_desc.ver_major, &obj_desc.ver_minor); - if (error < 0) ---- a/drivers/staging/fsl-mc/include/mc-private.h -+++ b/drivers/staging/fsl-mc/include/mc-private.h -@@ -94,12 +94,14 @@ struct fsl_mc_resource_pool { - * from the physical DPRC. - * @irq_resources: Pointer to array of IRQ objects for the IRQ pool - * @scan_mutex: Serializes bus scanning -+ * @dprc_attr: DPRC attributes - */ - struct fsl_mc_bus { - struct fsl_mc_device mc_dev; - struct fsl_mc_resource_pool resource_pools[FSL_MC_NUM_POOL_TYPES]; - struct fsl_mc_device_irq *irq_resources; - struct mutex scan_mutex; /* serializes bus scanning */ -+ struct dprc_attributes dprc_attr; - }; - - #define to_fsl_mc_bus(_mc_dev) \ diff --git a/target/linux/layerscape/patches-4.4/7175-staging-fsl-mc-add-quirk-handling-for-dpseci-objects.patch b/target/linux/layerscape/patches-4.4/7175-staging-fsl-mc-add-quirk-handling-for-dpseci-objects.patch deleted file mode 100644 index 36c6f89fc6..0000000000 --- a/target/linux/layerscape/patches-4.4/7175-staging-fsl-mc-add-quirk-handling-for-dpseci-objects.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 5366dc8896ca7cf028db73643860821b189a1dfd Mon Sep 17 00:00:00 2001 -From: Horia Geanta -Date: Mon, 11 Apr 2016 11:50:26 -0500 -Subject: [PATCH 175/226] staging: fsl-mc: add quirk handling for dpseci - objects < 4.0 - -dpseci objects < 4.0 are not coherent-- in spite of the fact -that the MC reports them to be coherent in certain versions. -Add a special case to set the no shareability flag for dpseci -objects < 4.0. - -Signed-off-by: Horia Geanta -(Stuart: reworded commit message, updated comment in patch) -Signed-off-by: Stuart Yoder -Acked-by: German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -312,6 +312,15 @@ int dprc_scan_objects(struct fsl_mc_devi - continue; - } - -+ /* -+ * add a quirk for all versions of dpsec < 4.0...none -+ * are coherent regardless of what the MC reports. -+ */ -+ if ((strcmp(obj_desc->type, "dpseci") == 0) && -+ (obj_desc->ver_major < 4)) -+ obj_desc->flags |= -+ DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY; -+ - irq_count += obj_desc->irq_count; - dev_dbg(&mc_bus_dev->dev, - "Discovered object: type %s, id %d\n", diff --git a/target/linux/layerscape/patches-4.4/7176-staging-fsl-mc-add-dpmcp-version-check.patch b/target/linux/layerscape/patches-4.4/7176-staging-fsl-mc-add-dpmcp-version-check.patch deleted file mode 100644 index 148a724c03..0000000000 --- a/target/linux/layerscape/patches-4.4/7176-staging-fsl-mc-add-dpmcp-version-check.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 035789ffb3b89b9764d7cc79d209a5795c18fa93 Mon Sep 17 00:00:00 2001 -From: Itai Katz -Date: Mon, 11 Apr 2016 11:56:11 -0500 -Subject: [PATCH 176/226] staging: fsl-mc: add dpmcp version check - -The dpmcp driver supports dpmcp version 3.0 and above. -This patch adds the code to check the version. - -Signed-off-by: Itai Katz -Signed-off-by: Stuart Yoder -Acked-by: German Rivera - - drivers/staging/fsl-mc/bus/dpmcp-cmd.h | 6 +++--- - drivers/staging/fsl-mc/bus/mc-allocator.c | 11 +++++++++++ - 2 files changed, 14 insertions(+), 3 deletions(-) -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dpmcp-cmd.h | 6 +++--- - drivers/staging/fsl-mc/bus/mc-allocator.c | 11 +++++++++++ - 2 files changed, 14 insertions(+), 3 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dpmcp-cmd.h -+++ b/drivers/staging/fsl-mc/bus/dpmcp-cmd.h -@@ -32,9 +32,9 @@ - #ifndef _FSL_DPMCP_CMD_H - #define _FSL_DPMCP_CMD_H - --/* DPMCP Version */ --#define DPMCP_VER_MAJOR 3 --#define DPMCP_VER_MINOR 0 -+/* Minimal supported DPMCP Version */ -+#define DPMCP_MIN_VER_MAJOR 3 -+#define DPMCP_MIN_VER_MINOR 0 - - /* Command IDs */ - #define DPMCP_CMDID_CLOSE 0x800 ---- a/drivers/staging/fsl-mc/bus/mc-allocator.c -+++ b/drivers/staging/fsl-mc/bus/mc-allocator.c -@@ -297,6 +297,17 @@ int __must_check fsl_mc_portal_allocate( - if (WARN_ON(!dpmcp_dev)) - goto error_cleanup_resource; - -+ if (dpmcp_dev->obj_desc.ver_major < DPMCP_MIN_VER_MAJOR || -+ (dpmcp_dev->obj_desc.ver_major == DPMCP_MIN_VER_MAJOR && -+ dpmcp_dev->obj_desc.ver_minor < DPMCP_MIN_VER_MINOR)) { -+ dev_err(&dpmcp_dev->dev, -+ "ERROR: Version %d.%d of DPMCP not supported.\n", -+ dpmcp_dev->obj_desc.ver_major, -+ dpmcp_dev->obj_desc.ver_minor); -+ error = -ENOTSUPP; -+ goto error_cleanup_resource; -+ } -+ - if (WARN_ON(dpmcp_dev->obj_desc.region_count == 0)) - goto error_cleanup_resource; - diff --git a/target/linux/layerscape/patches-4.4/7177-staging-fsl-mc-return-EINVAL-for-all-fsl_mc_portal_a.patch b/target/linux/layerscape/patches-4.4/7177-staging-fsl-mc-return-EINVAL-for-all-fsl_mc_portal_a.patch deleted file mode 100644 index 3a5a3f5646..0000000000 --- a/target/linux/layerscape/patches-4.4/7177-staging-fsl-mc-return-EINVAL-for-all-fsl_mc_portal_a.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 324147c1a6806301d9441a8d83c7c5ac880140cd Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Horia=20Geant=C4=83?= -Date: Mon, 11 Apr 2016 11:56:16 -0500 -Subject: [PATCH 177/226] staging: fsl-mc: return -EINVAL for all - fsl_mc_portal_allocate() failures -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There are some error paths that allow for a NULL new_mc_io and err = 0 -return code. Return -EINVAL instead. - -Signed-off-by: Horia Geantă -Signed-off-by: Stuart Yoder -Acked-by: German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-allocator.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/staging/fsl-mc/bus/mc-allocator.c -+++ b/drivers/staging/fsl-mc/bus/mc-allocator.c -@@ -293,6 +293,7 @@ int __must_check fsl_mc_portal_allocate( - if (error < 0) - return error; - -+ error = -EINVAL; - dpmcp_dev = resource->data; - if (WARN_ON(!dpmcp_dev)) - goto error_cleanup_resource; diff --git a/target/linux/layerscape/patches-4.4/7178-staging-fsl-mc-bus-Drop-warning.patch b/target/linux/layerscape/patches-4.4/7178-staging-fsl-mc-bus-Drop-warning.patch deleted file mode 100644 index dae0a5701e..0000000000 --- a/target/linux/layerscape/patches-4.4/7178-staging-fsl-mc-bus-Drop-warning.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 9821898bbfa5a21254baafe19b3cc97516fc6019 Mon Sep 17 00:00:00 2001 -From: Matthias Brugger -Date: Thu, 14 Apr 2016 23:24:26 +0200 -Subject: [PATCH 178/226] staging: fsl-mc: bus: Drop warning - -When updating the irq_chip and msi_domain_ops, the code checkes for -already present functions. -When more then one ITS controller are present in the system, -irq_chip and msi_domain_ops got already set and a warning is invoked. - -This patch deletes the warning, as the funtions are just already set to -the needed callbacks. - -Signed-off-by: Matthias Brugger -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-msi.c | 12 ++++-------- - 1 file changed, 4 insertions(+), 8 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/mc-msi.c -+++ b/drivers/staging/fsl-mc/bus/mc-msi.c -@@ -37,10 +37,8 @@ static void fsl_mc_msi_update_dom_ops(st - /* - * set_desc should not be set by the caller - */ -- if (WARN_ON(ops->set_desc)) -- return; -- -- ops->set_desc = fsl_mc_msi_set_desc; -+ if (ops->set_desc == NULL) -+ ops->set_desc = fsl_mc_msi_set_desc; - } - - static void __fsl_mc_msi_write_msg(struct fsl_mc_device *mc_bus_dev, -@@ -129,10 +127,8 @@ static void fsl_mc_msi_update_chip_ops(s - /* - * irq_write_msi_msg should not be set by the caller - */ -- if (WARN_ON(chip->irq_write_msi_msg)) -- return; -- -- chip->irq_write_msi_msg = fsl_mc_msi_write_msg; -+ if (chip->irq_write_msi_msg == NULL) -+ chip->irq_write_msi_msg = fsl_mc_msi_write_msg; - } - - /** diff --git a/target/linux/layerscape/patches-4.4/7179-staging-fsl-mc-add-support-for-the-modalias-sysfs-at.patch b/target/linux/layerscape/patches-4.4/7179-staging-fsl-mc-add-support-for-the-modalias-sysfs-at.patch deleted file mode 100644 index 030c195f76..0000000000 --- a/target/linux/layerscape/patches-4.4/7179-staging-fsl-mc-add-support-for-the-modalias-sysfs-at.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 227c693741ce1fbf0ad146c87f03369334941f2e Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Wed, 22 Jun 2016 16:40:42 -0500 -Subject: [PATCH 179/226] staging: fsl-mc: add support for the modalias sysfs - attribute - -In order to support uevent based module loading implement modalias support -for the fsl-mc bus driver. Aliases are based on vendor and object/device -id and are of the form "fsl-mc:vNdN". - -Signed-off-by: Stuart Yoder -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -82,10 +82,35 @@ static int fsl_mc_bus_uevent(struct devi - return 0; - } - -+static ssize_t modalias_show(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); -+ -+ return sprintf(buf, "fsl-mc:v%08Xd%s\n", mc_dev->obj_desc.vendor, -+ mc_dev->obj_desc.type); -+} -+static DEVICE_ATTR_RO(modalias); -+ -+static struct attribute *fsl_mc_dev_attrs[] = { -+ &dev_attr_modalias.attr, -+ NULL, -+}; -+ -+static const struct attribute_group fsl_mc_dev_group = { -+ .attrs = fsl_mc_dev_attrs, -+}; -+ -+static const struct attribute_group *fsl_mc_dev_groups[] = { -+ &fsl_mc_dev_group, -+ NULL, -+}; -+ - struct bus_type fsl_mc_bus_type = { - .name = "fsl-mc", - .match = fsl_mc_bus_match, - .uevent = fsl_mc_bus_uevent, -+ .dev_groups = fsl_mc_dev_groups, - }; - EXPORT_SYMBOL_GPL(fsl_mc_bus_type); - diff --git a/target/linux/layerscape/patches-4.4/7180-staging-fsl-mc-implement-uevent-callback-and-set-the.patch b/target/linux/layerscape/patches-4.4/7180-staging-fsl-mc-implement-uevent-callback-and-set-the.patch deleted file mode 100644 index 266219b8a8..0000000000 --- a/target/linux/layerscape/patches-4.4/7180-staging-fsl-mc-implement-uevent-callback-and-set-the.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 721966c3990bc4596c6270afc1ea68c756b72f0d Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Wed, 22 Jun 2016 16:40:43 -0500 -Subject: [PATCH 180/226] staging: fsl-mc: implement uevent callback and set - the modalias - -Replace placeholder code in the uevent callback to properly -set the MODALIAS env variable. - -Signed-off-by: Stuart Yoder -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -78,7 +78,13 @@ out: - */ - static int fsl_mc_bus_uevent(struct device *dev, struct kobj_uevent_env *env) - { -- pr_debug("%s invoked\n", __func__); -+ struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); -+ -+ if (add_uevent_var(env, "MODALIAS=fsl-mc:v%08Xd%s", -+ mc_dev->obj_desc.vendor, -+ mc_dev->obj_desc.type)) -+ return -ENOMEM; -+ - return 0; - } - diff --git a/target/linux/layerscape/patches-4.4/7181-staging-fsl-mc-clean-up-the-device-id-struct.patch b/target/linux/layerscape/patches-4.4/7181-staging-fsl-mc-clean-up-the-device-id-struct.patch deleted file mode 100644 index e5c58debd4..0000000000 --- a/target/linux/layerscape/patches-4.4/7181-staging-fsl-mc-clean-up-the-device-id-struct.patch +++ /dev/null @@ -1,85 +0,0 @@ -From c7b1e04ae4f47323800ca2b3d3430ecf1d9ed7df Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Wed, 22 Jun 2016 16:40:44 -0500 -Subject: [PATCH 181/226] staging: fsl-mc: clean up the device id struct - --rename the struct used for fsl-mc device ids to be more - consistent with other busses --remove the now obsolete and unused version fields - -Signed-off-by: Stuart Yoder -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 2 +- - drivers/staging/fsl-mc/bus/mc-allocator.c | 2 +- - drivers/staging/fsl-mc/bus/mc-bus.c | 2 +- - drivers/staging/fsl-mc/include/mc.h | 10 +++------- - 4 files changed, 6 insertions(+), 10 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -805,7 +805,7 @@ static int dprc_remove(struct fsl_mc_dev - return 0; - } - --static const struct fsl_mc_device_match_id match_id_table[] = { -+static const struct fsl_mc_device_id match_id_table[] = { - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dprc"}, ---- a/drivers/staging/fsl-mc/bus/mc-allocator.c -+++ b/drivers/staging/fsl-mc/bus/mc-allocator.c -@@ -717,7 +717,7 @@ static int fsl_mc_allocator_remove(struc - return 0; - } - --static const struct fsl_mc_device_match_id match_id_table[] = { -+static const struct fsl_mc_device_id match_id_table[] = { - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dpbp", ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -36,7 +36,7 @@ static bool fsl_mc_is_root_dprc(struct d - */ - static int fsl_mc_bus_match(struct device *dev, struct device_driver *drv) - { -- const struct fsl_mc_device_match_id *id; -+ const struct fsl_mc_device_id *id; - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(drv); - bool found = false; ---- a/drivers/staging/fsl-mc/include/mc.h -+++ b/drivers/staging/fsl-mc/include/mc.h -@@ -39,7 +39,7 @@ struct fsl_mc_bus; - */ - struct fsl_mc_driver { - struct device_driver driver; -- const struct fsl_mc_device_match_id *match_id_table; -+ const struct fsl_mc_device_id *match_id_table; - int (*probe)(struct fsl_mc_device *dev); - int (*remove)(struct fsl_mc_device *dev); - void (*shutdown)(struct fsl_mc_device *dev); -@@ -51,20 +51,16 @@ struct fsl_mc_driver { - container_of(_drv, struct fsl_mc_driver, driver) - - /** -- * struct fsl_mc_device_match_id - MC object device Id entry for driver matching -+ * struct fsl_mc_device_id - MC object device Id entry for driver matching - * @vendor: vendor ID - * @obj_type: MC object type -- * @ver_major: MC object version major number -- * @ver_minor: MC object version minor number - * - * Type of entries in the "device Id" table for MC object devices supported by - * a MC object device driver. The last entry of the table has vendor set to 0x0 - */ --struct fsl_mc_device_match_id { -+struct fsl_mc_device_id { - u16 vendor; - const char obj_type[16]; -- u32 ver_major; -- u32 ver_minor; - }; - - /** diff --git a/target/linux/layerscape/patches-4.4/7182-staging-fsl-mc-add-support-for-device-table-matching.patch b/target/linux/layerscape/patches-4.4/7182-staging-fsl-mc-add-support-for-device-table-matching.patch deleted file mode 100644 index 5ebb4591aa..0000000000 --- a/target/linux/layerscape/patches-4.4/7182-staging-fsl-mc-add-support-for-device-table-matching.patch +++ /dev/null @@ -1,98 +0,0 @@ -From bd83c4253992d263cb83108e26b4687058f11deb Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Wed, 22 Jun 2016 16:40:45 -0500 -Subject: [PATCH 182/226] staging: fsl-mc: add support for device table - matching - -Move the definition of fsl_mc_device_id to its proper location in -mod_devicetable.h, and add fsl-mc bus support to devicetable-offsets.c -and file2alias.c to enable device table matching. With this patch udev -based module loading of fsl-mc drivers is supported. - -Signed-off-by: Stuart Yoder -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/include/mc.h | 13 ------------- - include/linux/mod_devicetable.h | 16 ++++++++++++++++ - scripts/mod/devicetable-offsets.c | 4 ++++ - scripts/mod/file2alias.c | 12 ++++++++++++ - 4 files changed, 32 insertions(+), 13 deletions(-) - ---- a/drivers/staging/fsl-mc/include/mc.h -+++ b/drivers/staging/fsl-mc/include/mc.h -@@ -51,19 +51,6 @@ struct fsl_mc_driver { - container_of(_drv, struct fsl_mc_driver, driver) - - /** -- * struct fsl_mc_device_id - MC object device Id entry for driver matching -- * @vendor: vendor ID -- * @obj_type: MC object type -- * -- * Type of entries in the "device Id" table for MC object devices supported by -- * a MC object device driver. The last entry of the table has vendor set to 0x0 -- */ --struct fsl_mc_device_id { -- u16 vendor; -- const char obj_type[16]; --}; -- --/** - * enum fsl_mc_pool_type - Types of allocatable MC bus resources - * - * Entries in these enum are used as indices in the array of resource ---- a/include/linux/mod_devicetable.h -+++ b/include/linux/mod_devicetable.h -@@ -657,4 +657,20 @@ struct ulpi_device_id { - kernel_ulong_t driver_data; - }; - -+/** -+ * struct fsl_mc_device_id - MC object device identifier -+ * @vendor: vendor ID -+ * @obj_type: MC object type -+ * @ver_major: MC object version major number -+ * @ver_minor: MC object version minor number -+ * -+ * Type of entries in the "device Id" table for MC object devices supported by -+ * a MC object device driver. The last entry of the table has vendor set to 0x0 -+ */ -+struct fsl_mc_device_id { -+ __u16 vendor; -+ const char obj_type[16]; -+}; -+ -+ - #endif /* LINUX_MOD_DEVICETABLE_H */ ---- a/scripts/mod/devicetable-offsets.c -+++ b/scripts/mod/devicetable-offsets.c -@@ -202,5 +202,9 @@ int main(void) - DEVID_FIELD(hda_device_id, rev_id); - DEVID_FIELD(hda_device_id, api_version); - -+ DEVID(fsl_mc_device_id); -+ DEVID_FIELD(fsl_mc_device_id, vendor); -+ DEVID_FIELD(fsl_mc_device_id, obj_type); -+ - return 0; - } ---- a/scripts/mod/file2alias.c -+++ b/scripts/mod/file2alias.c -@@ -1271,6 +1271,18 @@ static int do_hda_entry(const char *file - } - ADD_TO_DEVTABLE("hdaudio", hda_device_id, do_hda_entry); - -+/* Looks like: fsl-mc:vNdN */ -+static int do_fsl_mc_entry(const char *filename, void *symval, -+ char *alias) -+{ -+ DEF_FIELD(symval, fsl_mc_device_id, vendor); -+ DEF_FIELD_ADDR(symval, fsl_mc_device_id, obj_type); -+ -+ sprintf(alias, "fsl-mc:v%08Xd%s", vendor, *obj_type); -+ return 1; -+} -+ADD_TO_DEVTABLE("fslmc", fsl_mc_device_id, do_fsl_mc_entry); -+ - /* Does namelen bytes of name exactly match the symbol? */ - static bool sym_is(const char *name, unsigned namelen, const char *symbol) - { diff --git a/target/linux/layerscape/patches-4.4/7183-staging-fsl-mc-export-mc_get_version.patch b/target/linux/layerscape/patches-4.4/7183-staging-fsl-mc-export-mc_get_version.patch deleted file mode 100644 index 330a1a885d..0000000000 --- a/target/linux/layerscape/patches-4.4/7183-staging-fsl-mc-export-mc_get_version.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 4087dc71f82a71c25f9d051773094f4ae3f4238d Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Wed, 22 Jun 2016 16:40:46 -0500 -Subject: [PATCH 183/226] staging: fsl-mc: export mc_get_version - -some drivers (built as modules) rely on mc_get_version() - -Signed-off-by: Stuart Yoder -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dpmng.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/staging/fsl-mc/bus/dpmng.c -+++ b/drivers/staging/fsl-mc/bus/dpmng.c -@@ -67,6 +67,7 @@ int mc_get_version(struct fsl_mc_io *mc_ - - return 0; - } -+EXPORT_SYMBOL(mc_get_version); - - /** - * dpmng_get_container_id() - Get container ID associated with a given portal. diff --git a/target/linux/layerscape/patches-4.4/7184-staging-fsl-mc-make-fsl_mc_is_root_dprc-global.patch b/target/linux/layerscape/patches-4.4/7184-staging-fsl-mc-make-fsl_mc_is_root_dprc-global.patch deleted file mode 100644 index 92b9c59a0c..0000000000 --- a/target/linux/layerscape/patches-4.4/7184-staging-fsl-mc-make-fsl_mc_is_root_dprc-global.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 82981b28f3a8a7f4ac61d8dc87a0abaeebfbe6dc Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Wed, 22 Jun 2016 16:40:47 -0500 -Subject: [PATCH 184/226] staging: fsl-mc: make fsl_mc_is_root_dprc() global - -make fsl_mc_is_root_dprc() global so that the dprc driver -can use it - -Signed-off-by: Stuart Yoder -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 28 +++++++++++++--------------- - drivers/staging/fsl-mc/include/mc.h | 2 ++ - 2 files changed, 15 insertions(+), 15 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -24,8 +24,6 @@ - - static struct kmem_cache *mc_dev_cache; - --static bool fsl_mc_is_root_dprc(struct device *dev); -- - /** - * fsl_mc_bus_match - device to driver matching callback - * @dev: the MC object device structure to match against -@@ -247,19 +245,6 @@ static void fsl_mc_get_root_dprc(struct - } - } - --/** -- * fsl_mc_is_root_dprc - function to check if a given device is a root dprc -- */ --static bool fsl_mc_is_root_dprc(struct device *dev) --{ -- struct device *root_dprc_dev; -- -- fsl_mc_get_root_dprc(dev, &root_dprc_dev); -- if (!root_dprc_dev) -- return false; -- return dev == root_dprc_dev; --} -- - static int get_dprc_attr(struct fsl_mc_io *mc_io, - int container_id, struct dprc_attributes *attr) - { -@@ -424,6 +409,19 @@ error_cleanup_regions: - } - - /** -+ * fsl_mc_is_root_dprc - function to check if a given device is a root dprc -+ */ -+bool fsl_mc_is_root_dprc(struct device *dev) -+{ -+ struct device *root_dprc_dev; -+ -+ fsl_mc_get_root_dprc(dev, &root_dprc_dev); -+ if (!root_dprc_dev) -+ return false; -+ return dev == root_dprc_dev; -+} -+ -+/** - * Add a newly discovered MC object device to be visible in Linux - */ - int fsl_mc_device_add(struct dprc_obj_desc *obj_desc, ---- a/drivers/staging/fsl-mc/include/mc.h -+++ b/drivers/staging/fsl-mc/include/mc.h -@@ -207,6 +207,8 @@ int __must_check fsl_mc_allocate_irqs(st - - void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev); - -+bool fsl_mc_is_root_dprc(struct device *dev); -+ - extern struct bus_type fsl_mc_bus_type; - - #endif /* _FSL_MC_H_ */ diff --git a/target/linux/layerscape/patches-4.4/7185-staging-fsl-mc-fix-asymmetry-in-destroy-of-mc_io.patch b/target/linux/layerscape/patches-4.4/7185-staging-fsl-mc-fix-asymmetry-in-destroy-of-mc_io.patch deleted file mode 100644 index b148c76068..0000000000 --- a/target/linux/layerscape/patches-4.4/7185-staging-fsl-mc-fix-asymmetry-in-destroy-of-mc_io.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 4e55a4c296d3a93c95320cdac0b8e72f3cfefb98 Mon Sep 17 00:00:00 2001 -From: Bharat Bhushan -Date: Wed, 22 Jun 2016 16:40:48 -0500 -Subject: [PATCH 185/226] staging: fsl-mc: fix asymmetry in destroy of mc_io - -An mc_io represents a mapped MC portal. Previously, an mc_io was -created for the root dprc in fsl_mc_bus_probe() and for child dprcs -in dprc_probe(). But the free of that data structure happened in the -general bus remove callback. This asymmetry resulted in some bugs due -to unwanted destroys of mc_io object in some scenarios (e.g. vfio). - -Fix this bug by making things symmetric-- mc_io created in -fsl_mc_bus_probe() is freed in fsl_mc_bus_remove(). The mc_io created -in dprc_probe() is freed in dprc_remove(). - -Signed-off-by: Bharat Bhushan -[Stuart: added check for root dprc and reworded commit message] -Signed-off-by: Stuart Yoder -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 5 +++++ - drivers/staging/fsl-mc/bus/mc-bus.c | 8 ++++---- - 2 files changed, 9 insertions(+), 4 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -801,6 +801,11 @@ static int dprc_remove(struct fsl_mc_dev - dev_set_msi_domain(&mc_dev->dev, NULL); - } - -+ if (!fsl_mc_is_root_dprc(&mc_dev->dev)) { -+ fsl_destroy_mc_io(mc_dev->mc_io); -+ mc_dev->mc_io = NULL; -+ } -+ - dev_info(&mc_dev->dev, "DPRC device unbound from driver"); - return 0; - } ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -579,10 +579,6 @@ void fsl_mc_device_remove(struct fsl_mc_ - - if (strcmp(mc_dev->obj_desc.type, "dprc") == 0) { - mc_bus = to_fsl_mc_bus(mc_dev); -- if (mc_dev->mc_io) { -- fsl_destroy_mc_io(mc_dev->mc_io); -- mc_dev->mc_io = NULL; -- } - - if (fsl_mc_is_root_dprc(&mc_dev->dev)) { - if (atomic_read(&root_dprc_count) > 0) -@@ -810,6 +806,10 @@ static int fsl_mc_bus_remove(struct plat - return -EINVAL; - - fsl_mc_device_remove(mc->root_mc_bus_dev); -+ -+ fsl_destroy_mc_io(mc->root_mc_bus_dev->mc_io); -+ mc->root_mc_bus_dev->mc_io = NULL; -+ - dev_info(&pdev->dev, "Root MC bus device removed"); - return 0; - } diff --git a/target/linux/layerscape/patches-4.4/7186-staging-fsl-mc-dprc-add-missing-irq-free.patch b/target/linux/layerscape/patches-4.4/7186-staging-fsl-mc-dprc-add-missing-irq-free.patch deleted file mode 100644 index 0a485ec3e1..0000000000 --- a/target/linux/layerscape/patches-4.4/7186-staging-fsl-mc-dprc-add-missing-irq-free.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 159abffaa5e2acf910b5e4cdca81a7b6d2dd958f Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Wed, 22 Jun 2016 16:40:49 -0500 -Subject: [PATCH 186/226] staging: fsl-mc: dprc: add missing irq free - -add missing free of the Linux irq when tearing down interrupts - -Signed-off-by: Stuart Yoder -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -760,7 +760,12 @@ error_cleanup_msi_domain: - */ - static void dprc_teardown_irq(struct fsl_mc_device *mc_dev) - { -+ struct fsl_mc_device_irq *irq = mc_dev->irqs[0]; -+ - (void)disable_dprc_irq(mc_dev); -+ -+ devm_free_irq(&mc_dev->dev, irq->msi_desc->irq, &mc_dev->dev); -+ - fsl_mc_free_irqs(mc_dev); - } - diff --git a/target/linux/layerscape/patches-4.4/7187-staging-fsl-mc-dprc-fix-ordering-problem-freeing-res.patch b/target/linux/layerscape/patches-4.4/7187-staging-fsl-mc-dprc-fix-ordering-problem-freeing-res.patch deleted file mode 100644 index c03e8d9b1f..0000000000 --- a/target/linux/layerscape/patches-4.4/7187-staging-fsl-mc-dprc-fix-ordering-problem-freeing-res.patch +++ /dev/null @@ -1,41 +0,0 @@ -From b104ed7497745e2e6da214b37ef22edaf38098c7 Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Wed, 22 Jun 2016 16:40:50 -0500 -Subject: [PATCH 187/226] staging: fsl-mc: dprc: fix ordering problem freeing - resources in remove of dprc - -When unbinding a dprc from the dprc driver the cleanup of -the resource pools must happen after irq pool cleanup -is done. - -Signed-off-by: Stuart Yoder -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 10 ++++++---- - 1 file changed, 6 insertions(+), 4 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -796,16 +796,18 @@ static int dprc_remove(struct fsl_mc_dev - dprc_teardown_irq(mc_dev); - - device_for_each_child(&mc_dev->dev, NULL, __fsl_mc_device_remove); -- dprc_cleanup_all_resource_pools(mc_dev); -- error = dprc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); -- if (error < 0) -- dev_err(&mc_dev->dev, "dprc_close() failed: %d\n", error); - - if (dev_get_msi_domain(&mc_dev->dev)) { - fsl_mc_cleanup_irq_pool(mc_bus); - dev_set_msi_domain(&mc_dev->dev, NULL); - } - -+ dprc_cleanup_all_resource_pools(mc_dev); -+ -+ error = dprc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); -+ if (error < 0) -+ dev_err(&mc_dev->dev, "dprc_close() failed: %d\n", error); -+ - if (!fsl_mc_is_root_dprc(&mc_dev->dev)) { - fsl_destroy_mc_io(mc_dev->mc_io); - mc_dev->mc_io = NULL; diff --git a/target/linux/layerscape/patches-4.4/7188-staging-fsl-mc-properly-set-hwirq-in-msi-set_desc.patch b/target/linux/layerscape/patches-4.4/7188-staging-fsl-mc-properly-set-hwirq-in-msi-set_desc.patch deleted file mode 100644 index 34aadad782..0000000000 --- a/target/linux/layerscape/patches-4.4/7188-staging-fsl-mc-properly-set-hwirq-in-msi-set_desc.patch +++ /dev/null @@ -1,48 +0,0 @@ -From f5f9462cb947922817225b69240740e637de0149 Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Wed, 22 Jun 2016 16:40:51 -0500 -Subject: [PATCH 188/226] staging: fsl-mc: properly set hwirq in msi set_desc - -For an MSI domain the hwirq is an arbitrary but unique -id to identify an interrupt. Previously the hwirq was set to -the MSI index of the interrupt, but that only works if there is -one DPRC. Additional DPRCs require an expanded namespace. Use -both the ICID (which is unique per DPRC) and the MSI index to -compose a hwirq value. - -Signed-off-by: Stuart Yoder -Signed-off-by: Greg Kroah-Hartman ---- - drivers/staging/fsl-mc/bus/mc-msi.c | 17 ++++++++++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - ---- a/drivers/staging/fsl-mc/bus/mc-msi.c -+++ b/drivers/staging/fsl-mc/bus/mc-msi.c -@@ -20,11 +20,26 @@ - #include "../include/mc-sys.h" - #include "dprc-cmd.h" - -+/* -+ * Generate a unique ID identifying the interrupt (only used within the MSI -+ * irqdomain. Combine the icid with the interrupt index. -+ */ -+static irq_hw_number_t fsl_mc_domain_calc_hwirq(struct fsl_mc_device *dev, -+ struct msi_desc *desc) -+{ -+ /* -+ * Make the base hwirq value for ICID*10000 so it is readable -+ * as a decimal value in /proc/interrupts. -+ */ -+ return (irq_hw_number_t)(desc->fsl_mc.msi_index + (dev->icid * 10000)); -+} -+ - static void fsl_mc_msi_set_desc(msi_alloc_info_t *arg, - struct msi_desc *desc) - { - arg->desc = desc; -- arg->hwirq = (irq_hw_number_t)desc->fsl_mc.msi_index; -+ arg->hwirq = fsl_mc_domain_calc_hwirq(to_fsl_mc_device(desc->dev), -+ desc); - } - - static void fsl_mc_msi_update_dom_ops(struct msi_domain_info *info) diff --git a/target/linux/layerscape/patches-4.4/7189-staging-fsl-mc-update-dpcon-binary-interface-to-v2.2.patch b/target/linux/layerscape/patches-4.4/7189-staging-fsl-mc-update-dpcon-binary-interface-to-v2.2.patch deleted file mode 100644 index 5f60ea7d87..0000000000 --- a/target/linux/layerscape/patches-4.4/7189-staging-fsl-mc-update-dpcon-binary-interface-to-v2.2.patch +++ /dev/null @@ -1,964 +0,0 @@ -From 95c8565453e068db2664b5ee9cb0b7eced9a8d24 Mon Sep 17 00:00:00 2001 -From: Ioana Radulescu -Date: Fri, 3 Jul 2015 19:02:45 +0300 -Subject: [PATCH 189/226] staging: fsl-mc: update dpcon binary interface to - v2.2 - --this includes adding the command building/parsing - wrapper functions - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-mc/bus/Makefile | 3 +- - drivers/staging/fsl-mc/bus/dpcon.c | 407 ++++++++++++++++++++++++++++ - drivers/staging/fsl-mc/include/dpcon-cmd.h | 102 ++++++- - drivers/staging/fsl-mc/include/dpcon.h | 407 ++++++++++++++++++++++++++++ - 4 files changed, 917 insertions(+), 2 deletions(-) - create mode 100644 drivers/staging/fsl-mc/bus/dpcon.c - create mode 100644 drivers/staging/fsl-mc/include/dpcon.h - ---- a/drivers/staging/fsl-mc/bus/Makefile -+++ b/drivers/staging/fsl-mc/bus/Makefile -@@ -16,4 +16,5 @@ mc-bus-driver-objs := mc-bus.o \ - mc-msi.o \ - irq-gic-v3-its-fsl-mc-msi.o \ - dpmcp.o \ -- dpbp.o -+ dpbp.o \ -+ dpcon.o ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpcon.c -@@ -0,0 +1,407 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include "../include/mc-sys.h" -+#include "../include/mc-cmd.h" -+#include "../include/dpcon.h" -+#include "../include/dpcon-cmd.h" -+ -+int dpcon_open(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ int dpcon_id, -+ uint16_t *token) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_OPEN, -+ cmd_flags, -+ 0); -+ DPCON_CMD_OPEN(cmd, dpcon_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header); -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpcon_open); -+ -+int dpcon_close(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_CLOSE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+EXPORT_SYMBOL(dpcon_close); -+ -+int dpcon_create(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ const struct dpcon_cfg *cfg, -+ uint16_t *token) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_CREATE, -+ cmd_flags, -+ 0); -+ DPCON_CMD_CREATE(cmd, cfg); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header); -+ -+ return 0; -+} -+ -+int dpcon_destroy(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_DESTROY, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpcon_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_ENABLE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+EXPORT_SYMBOL(dpcon_enable); -+ -+int dpcon_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_DISABLE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+EXPORT_SYMBOL(dpcon_disable); -+ -+int dpcon_is_enabled(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_IS_ENABLED, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPCON_RSP_IS_ENABLED(cmd, *en); -+ -+ return 0; -+} -+ -+int dpcon_reset(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_RESET, -+ cmd_flags, token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpcon_set_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ struct dpcon_irq_cfg *irq_cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_IRQ, -+ cmd_flags, -+ token); -+ DPCON_CMD_SET_IRQ(cmd, irq_index, irq_cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpcon_get_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ int *type, -+ struct dpcon_irq_cfg *irq_cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_IRQ, -+ cmd_flags, -+ token); -+ DPCON_CMD_GET_IRQ(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPCON_RSP_GET_IRQ(cmd, *type, irq_cfg); -+ -+ return 0; -+} -+ -+int dpcon_set_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ DPCON_CMD_SET_IRQ_ENABLE(cmd, irq_index, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpcon_get_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ DPCON_CMD_GET_IRQ_ENABLE(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPCON_RSP_GET_IRQ_ENABLE(cmd, *en); -+ -+ return 0; -+} -+ -+int dpcon_set_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t mask) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_IRQ_MASK, -+ cmd_flags, -+ token); -+ DPCON_CMD_SET_IRQ_MASK(cmd, irq_index, mask); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpcon_get_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *mask) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_IRQ_MASK, -+ cmd_flags, -+ token); -+ DPCON_CMD_GET_IRQ_MASK(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPCON_RSP_GET_IRQ_MASK(cmd, *mask); -+ -+ return 0; -+} -+ -+int dpcon_get_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *status) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_IRQ_STATUS, -+ cmd_flags, -+ token); -+ DPCON_CMD_GET_IRQ_STATUS(cmd, irq_index, *status); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPCON_RSP_GET_IRQ_STATUS(cmd, *status); -+ -+ return 0; -+} -+ -+int dpcon_clear_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t status) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_CLEAR_IRQ_STATUS, -+ cmd_flags, -+ token); -+ DPCON_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpcon_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpcon_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_ATTR, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPCON_RSP_GET_ATTR(cmd, attr); -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpcon_get_attributes); -+ -+int dpcon_set_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpcon_notification_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_NOTIFICATION, -+ cmd_flags, -+ token); -+ DPCON_CMD_SET_NOTIFICATION(cmd, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+EXPORT_SYMBOL(dpcon_set_notification); -+ ---- a/drivers/staging/fsl-mc/include/dpcon-cmd.h -+++ b/drivers/staging/fsl-mc/include/dpcon-cmd.h -@@ -34,7 +34,7 @@ - - /* DPCON Version */ - #define DPCON_VER_MAJOR 2 --#define DPCON_VER_MINOR 1 -+#define DPCON_VER_MINOR 2 - - /* Command IDs */ - #define DPCON_CMDID_CLOSE 0x800 -@@ -59,4 +59,104 @@ - - #define DPCON_CMDID_SET_NOTIFICATION 0x100 - -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_CMD_OPEN(cmd, dpcon_id) \ -+ MC_CMD_OP(cmd, 0, 0, 32, int, dpcon_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_CMD_CREATE(cmd, cfg) \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_priorities) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_RSP_IS_ENABLED(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\ -+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\ -+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_CMD_GET_IRQ(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_RSP_GET_IRQ(cmd, type, irq_cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val);\ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\ -+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \ -+ MC_RSP_OP(cmd, 2, 32, 32, int, type);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_CMD_GET_IRQ_ENABLE(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_RSP_GET_IRQ_ENABLE(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_CMD_GET_IRQ_MASK(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_RSP_GET_IRQ_MASK(cmd, mask) \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_RSP_GET_IRQ_STATUS(cmd, status) \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_RSP_GET_ATTR(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ -+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qbman_ch_id);\ -+ MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->num_priorities);\ -+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\ -+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPCON_CMD_SET_NOTIFICATION(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dpio_id);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->priority);\ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx);\ -+} while (0) -+ - #endif /* _FSL_DPCON_CMD_H */ ---- /dev/null -+++ b/drivers/staging/fsl-mc/include/dpcon.h -@@ -0,0 +1,407 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef __FSL_DPCON_H -+#define __FSL_DPCON_H -+ -+/* Data Path Concentrator API -+ * Contains initialization APIs and runtime control APIs for DPCON -+ */ -+ -+struct fsl_mc_io; -+ -+/** General DPCON macros */ -+ -+/** -+ * Use it to disable notifications; see dpcon_set_notification() -+ */ -+#define DPCON_INVALID_DPIO_ID (int)(-1) -+ -+/** -+ * dpcon_open() - Open a control session for the specified object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @dpcon_id: DPCON unique ID -+ * @token: Returned token; use in subsequent API calls -+ * -+ * This function can be used to open a control session for an -+ * already created object; an object may have been declared in -+ * the DPL or by calling the dpcon_create() function. -+ * This function returns a unique authentication token, -+ * associated with the specific object ID and the specific MC -+ * portal; this token must be used in all subsequent commands for -+ * this specific object. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_open(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ int dpcon_id, -+ uint16_t *token); -+ -+/** -+ * dpcon_close() - Close the control session of the object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * -+ * After this function is called, no further operations are -+ * allowed on the object without opening a new control session. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_close(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * struct dpcon_cfg - Structure representing DPCON configuration -+ * @num_priorities: Number of priorities for the DPCON channel (1-8) -+ */ -+struct dpcon_cfg { -+ uint8_t num_priorities; -+}; -+ -+/** -+ * dpcon_create() - Create the DPCON object. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @cfg: Configuration structure -+ * @token: Returned token; use in subsequent API calls -+ * -+ * Create the DPCON object, allocate required resources and -+ * perform required initialization. -+ * -+ * The object can be created either by declaring it in the -+ * DPL file, or by calling this function. -+ * -+ * This function returns a unique authentication token, -+ * associated with the specific object ID and the specific MC -+ * portal; this token must be used in all subsequent calls to -+ * this specific object. For objects that are created using the -+ * DPL file, call dpcon_open() function to get an authentication -+ * token first. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_create(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ const struct dpcon_cfg *cfg, -+ uint16_t *token); -+ -+/** -+ * dpcon_destroy() - Destroy the DPCON object and release all its resources. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpcon_destroy(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpcon_enable() - Enable the DPCON -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * -+ * Return: '0' on Success; Error code otherwise -+ */ -+int dpcon_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpcon_disable() - Disable the DPCON -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * -+ * Return: '0' on Success; Error code otherwise -+ */ -+int dpcon_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpcon_is_enabled() - Check if the DPCON is enabled. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * @en: Returns '1' if object is enabled; '0' otherwise -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_is_enabled(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en); -+ -+/** -+ * dpcon_reset() - Reset the DPCON, returns the object to initial state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_reset(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * struct dpcon_irq_cfg - IRQ configuration -+ * @addr: Address that must be written to signal a message-based interrupt -+ * @val: Value to write into irq_addr address -+ * @irq_num: A user defined number associated with this IRQ -+ */ -+struct dpcon_irq_cfg { -+ uint64_t addr; -+ uint32_t val; -+ int irq_num; -+}; -+ -+/** -+ * dpcon_set_irq() - Set IRQ information for the DPCON to trigger an interrupt. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * @irq_index: Identifies the interrupt index to configure -+ * @irq_cfg: IRQ configuration -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_set_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ struct dpcon_irq_cfg *irq_cfg); -+ -+/** -+ * dpcon_get_irq() - Get IRQ information from the DPCON. -+ * -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * @irq_index: The interrupt index to configure -+ * @type: Interrupt type: 0 represents message interrupt -+ * type (both irq_addr and irq_val are valid) -+ * @irq_cfg: IRQ attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_get_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ int *type, -+ struct dpcon_irq_cfg *irq_cfg); -+ -+/** -+ * dpcon_set_irq_enable() - Set overall interrupt state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * @irq_index: The interrupt index to configure -+ * @en: Interrupt state - enable = 1, disable = 0 -+ * -+ * Allows GPP software to control when interrupts are generated. -+ * Each interrupt can have up to 32 causes. The enable/disable control's the -+ * overall interrupt state. if the interrupt is disabled no causes will cause -+ * an interrupt. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_set_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t en); -+ -+/** -+ * dpcon_get_irq_enable() - Get overall interrupt state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * @irq_index: The interrupt index to configure -+ * @en: Returned interrupt state - enable = 1, disable = 0 -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_get_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t *en); -+ -+/** -+ * dpcon_set_irq_mask() - Set interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * @irq_index: The interrupt index to configure -+ * @mask: Event mask to trigger interrupt; -+ * each bit: -+ * 0 = ignore event -+ * 1 = consider event for asserting IRQ -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_set_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t mask); -+ -+/** -+ * dpcon_get_irq_mask() - Get interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * @irq_index: The interrupt index to configure -+ * @mask: Returned event mask to trigger interrupt -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_get_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *mask); -+ -+/** -+ * dpcon_get_irq_status() - Get the current status of any pending interrupts. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * @irq_index: The interrupt index to configure -+ * @status: interrupts status - one bit per cause: -+ * 0 = no interrupt pending -+ * 1 = interrupt pending -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_get_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *status); -+ -+/** -+ * dpcon_clear_irq_status() - Clear a pending interrupt's status -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * @irq_index: The interrupt index to configure -+ * @status: bits to clear (W1C) - one bit per cause: -+ * 0 = don't change -+ * 1 = clear status bit -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_clear_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t status); -+ -+/** -+ * struct dpcon_attr - Structure representing DPCON attributes -+ * @id: DPCON object ID -+ * @version: DPCON version -+ * @qbman_ch_id: Channel ID to be used by dequeue operation -+ * @num_priorities: Number of priorities for the DPCON channel (1-8) -+ */ -+struct dpcon_attr { -+ int id; -+ /** -+ * struct version - DPCON version -+ * @major: DPCON major version -+ * @minor: DPCON minor version -+ */ -+ struct { -+ uint16_t major; -+ uint16_t minor; -+ } version; -+ uint16_t qbman_ch_id; -+ uint8_t num_priorities; -+}; -+ -+/** -+ * dpcon_get_attributes() - Retrieve DPCON attributes. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * @attr: Object's attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpcon_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpcon_attr *attr); -+ -+/** -+ * struct dpcon_notification_cfg - Structure representing notification parameters -+ * @dpio_id: DPIO object ID; must be configured with a notification channel; -+ * to disable notifications set it to 'DPCON_INVALID_DPIO_ID'; -+ * @priority: Priority selection within the DPIO channel; valid values -+ * are 0-7, depending on the number of priorities in that channel -+ * @user_ctx: User context value provided with each CDAN message -+ */ -+struct dpcon_notification_cfg { -+ int dpio_id; -+ uint8_t priority; -+ uint64_t user_ctx; -+}; -+ -+/** -+ * dpcon_set_notification() - Set DPCON notification destination -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCON object -+ * @cfg: Notification parameters -+ * -+ * Return: '0' on Success; Error code otherwise -+ */ -+int dpcon_set_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpcon_notification_cfg *cfg); -+ -+#endif /* __FSL_DPCON_H */ diff --git a/target/linux/layerscape/patches-4.4/7190-staging-fsl-mc-root-dprc-rescan-attribute-to-sync-ke.patch b/target/linux/layerscape/patches-4.4/7190-staging-fsl-mc-root-dprc-rescan-attribute-to-sync-ke.patch deleted file mode 100644 index a38907b0bd..0000000000 --- a/target/linux/layerscape/patches-4.4/7190-staging-fsl-mc-root-dprc-rescan-attribute-to-sync-ke.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 75b607ff8725eac74f3375b3370f7d121d1827a3 Mon Sep 17 00:00:00 2001 -From: Lijun Pan -Date: Mon, 8 Feb 2016 17:40:14 -0600 -Subject: [PATCH 190/226] staging: fsl-mc: root dprc rescan attribute to sync - kernel with MC - -Introduce the rescan attribute as a device attribute to -synchronize the fsl-mc bus objects and the MC firmware. - -To rescan the root dprc only, e.g. -echo 1 > /sys/bus/fsl-mc/devices/dprc.1/rescan - -Signed-off-by: Lijun Pan -[Stuart: resolved merge conflict] -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 29 +++++++++++++++++++++++++++++ - 1 file changed, 29 insertions(+) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -96,8 +96,37 @@ static ssize_t modalias_show(struct devi - } - static DEVICE_ATTR_RO(modalias); - -+static ssize_t rescan_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ unsigned long val; -+ unsigned int irq_count; -+ struct fsl_mc_device *root_mc_dev; -+ struct fsl_mc_bus *root_mc_bus; -+ -+ if (!fsl_mc_is_root_dprc(dev)) -+ return -EINVAL; -+ -+ root_mc_dev = to_fsl_mc_device(dev); -+ root_mc_bus = to_fsl_mc_bus(root_mc_dev); -+ -+ if (kstrtoul(buf, 0, &val) < 0) -+ return -EINVAL; -+ -+ if (val) { -+ mutex_lock(&root_mc_bus->scan_mutex); -+ dprc_scan_objects(root_mc_dev, &irq_count); -+ mutex_unlock(&root_mc_bus->scan_mutex); -+ } -+ -+ return count; -+} -+static DEVICE_ATTR_WO(rescan); -+ - static struct attribute *fsl_mc_dev_attrs[] = { - &dev_attr_modalias.attr, -+ &dev_attr_rescan.attr, - NULL, - }; - diff --git a/target/linux/layerscape/patches-4.4/7191-staging-fsl-mc-bus-rescan-attribute-to-sync-kernel-w.patch b/target/linux/layerscape/patches-4.4/7191-staging-fsl-mc-bus-rescan-attribute-to-sync-kernel-w.patch deleted file mode 100644 index d89815d812..0000000000 --- a/target/linux/layerscape/patches-4.4/7191-staging-fsl-mc-bus-rescan-attribute-to-sync-kernel-w.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 417d71b1e291725c01893bf1553478924d05952f Mon Sep 17 00:00:00 2001 -From: Lijun Pan -Date: Mon, 8 Feb 2016 17:40:16 -0600 -Subject: [PATCH 191/226] staging: fsl-mc: bus rescan attribute to sync kernel - with MC - -Introduce the rescan attribute as a bus attribute to -synchronize the fsl-mc bus objects and the MC firmware. - -To rescan the fsl-mc bus, e.g., -echo 1 > /sys/bus/fsl-mc/rescan - -Signed-off-by: Lijun Pan ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 47 +++++++++++++++++++++++++++++++++++ - 1 file changed, 47 insertions(+) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -139,11 +139,58 @@ static const struct attribute_group *fsl - NULL, - }; - -+static int scan_fsl_mc_bus(struct device *dev, void *data) -+{ -+ unsigned int irq_count; -+ struct fsl_mc_device *root_mc_dev; -+ struct fsl_mc_bus *root_mc_bus; -+ -+ if (fsl_mc_is_root_dprc(dev)) { -+ root_mc_dev = to_fsl_mc_device(dev); -+ root_mc_bus = to_fsl_mc_bus(root_mc_dev); -+ mutex_lock(&root_mc_bus->scan_mutex); -+ dprc_scan_objects(root_mc_dev, &irq_count); -+ mutex_unlock(&root_mc_bus->scan_mutex); -+ } -+ -+ return 0; -+} -+ -+static ssize_t bus_rescan_store(struct bus_type *bus, -+ const char *buf, size_t count) -+{ -+ unsigned long val; -+ -+ if (kstrtoul(buf, 0, &val) < 0) -+ return -EINVAL; -+ -+ if (val) -+ bus_for_each_dev(bus, NULL, NULL, scan_fsl_mc_bus); -+ -+ return count; -+} -+static BUS_ATTR(rescan, (S_IWUSR | S_IWGRP), NULL, bus_rescan_store); -+ -+static struct attribute *fsl_mc_bus_attrs[] = { -+ &bus_attr_rescan.attr, -+ NULL, -+}; -+ -+static const struct attribute_group fsl_mc_bus_group = { -+ .attrs = fsl_mc_bus_attrs, -+}; -+ -+static const struct attribute_group *fsl_mc_bus_groups[] = { -+ &fsl_mc_bus_group, -+ NULL, -+}; -+ - struct bus_type fsl_mc_bus_type = { - .name = "fsl-mc", - .match = fsl_mc_bus_match, - .uevent = fsl_mc_bus_uevent, - .dev_groups = fsl_mc_dev_groups, -+ .bus_groups = fsl_mc_bus_groups, - }; - EXPORT_SYMBOL_GPL(fsl_mc_bus_type); - diff --git a/target/linux/layerscape/patches-4.4/7192-staging-fsl-mc-Propagate-driver_override-for-a-child.patch b/target/linux/layerscape/patches-4.4/7192-staging-fsl-mc-Propagate-driver_override-for-a-child.patch deleted file mode 100644 index 20b952e5f3..0000000000 --- a/target/linux/layerscape/patches-4.4/7192-staging-fsl-mc-Propagate-driver_override-for-a-child.patch +++ /dev/null @@ -1,193 +0,0 @@ -From 2b9110586a96afc0d0e246835da176c48ae7c973 Mon Sep 17 00:00:00 2001 -From: "J. German Rivera" -Date: Fri, 13 Mar 2015 15:03:32 -0500 -Subject: [PATCH 192/226] staging: fsl-mc: Propagate driver_override for a - child DPRC's children - -When a child DPRC is bound to the vfio_fsl_mc driver via driver_override, -its own children should not be bound to corresponding host kernel -drivers, but instead should be bound to the vfio_fsl_mc driver as -well. - -Currently, when a child container is scanned by the vfio_fsl_mc driver, -child devices found are automatically bound to corresponding host kernel -drivers (e.g., DPMCP and DPBP objects are bound to the fsl_mc_allocator -driver, DPNI objects are bound to the ldpaa_eth driver, etc), Then, -the user has to manually unbind these child devices from their drivers, -set the driver_override sysfs attribute to vfio_fsl_mc driver, for each -of them and rebind them. - -Signed-off-by: J. German Rivera -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 14 ++++++++++---- - drivers/staging/fsl-mc/bus/mc-bus.c | 20 +++++++++++++++++--- - drivers/staging/fsl-mc/include/mc-private.h | 2 ++ - drivers/staging/fsl-mc/include/mc.h | 2 ++ - 4 files changed, 31 insertions(+), 7 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -152,6 +152,8 @@ static void check_plugged_state_change(s - * dprc_add_new_devices - Adds devices to the logical bus for a DPRC - * - * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object -+ * @driver_override: driver override to apply to new objects found in the DPRC, -+ * or NULL, if none. - * @obj_desc_array: array of device descriptors for child devices currently - * present in the physical DPRC. - * @num_child_objects_in_mc: number of entries in obj_desc_array -@@ -161,6 +163,7 @@ static void check_plugged_state_change(s - * in the physical DPRC. - */ - static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev, -+ const char *driver_override, - struct dprc_obj_desc *obj_desc_array, - int num_child_objects_in_mc) - { -@@ -184,7 +187,7 @@ static void dprc_add_new_devices(struct - } - - error = fsl_mc_device_add(obj_desc, NULL, &mc_bus_dev->dev, -- &child_dev); -+ driver_override, &child_dev); - if (error < 0) - continue; - } -@@ -243,6 +246,8 @@ static void dprc_cleanup_all_resource_po - * dprc_scan_objects - Discover objects in a DPRC - * - * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object -+ * @driver_override: driver override to apply to new objects found in the DPRC, -+ * or NULL, if none. - * @total_irq_count: total number of IRQs needed by objects in the DPRC. - * - * Detects objects added and removed from a DPRC and synchronizes the -@@ -258,6 +263,7 @@ static void dprc_cleanup_all_resource_po - * of the device drivers for the non-allocatable devices. - */ - int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, -+ const char *driver_override, - unsigned int *total_irq_count) - { - int num_child_objects; -@@ -338,7 +344,7 @@ int dprc_scan_objects(struct fsl_mc_devi - dprc_remove_devices(mc_bus_dev, child_obj_desc_array, - num_child_objects); - -- dprc_add_new_devices(mc_bus_dev, child_obj_desc_array, -+ dprc_add_new_devices(mc_bus_dev, driver_override, child_obj_desc_array, - num_child_objects); - - if (child_obj_desc_array) -@@ -369,7 +375,7 @@ int dprc_scan_container(struct fsl_mc_de - * Discover objects in the DPRC: - */ - mutex_lock(&mc_bus->scan_mutex); -- error = dprc_scan_objects(mc_bus_dev, &irq_count); -+ error = dprc_scan_objects(mc_bus_dev, NULL, &irq_count); - mutex_unlock(&mc_bus->scan_mutex); - if (error < 0) - goto error; -@@ -456,7 +462,7 @@ static irqreturn_t dprc_irq0_handler_thr - DPRC_IRQ_EVENT_OBJ_CREATED)) { - unsigned int irq_count; - -- error = dprc_scan_objects(mc_dev, &irq_count); -+ error = dprc_scan_objects(mc_dev, NULL, &irq_count); - if (error < 0) { - /* - * If the error is -ENXIO, we ignore it, as it indicates ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -116,7 +116,7 @@ static ssize_t rescan_store(struct devic - - if (val) { - mutex_lock(&root_mc_bus->scan_mutex); -- dprc_scan_objects(root_mc_dev, &irq_count); -+ dprc_scan_objects(root_mc_dev, NULL, &irq_count); - mutex_unlock(&root_mc_bus->scan_mutex); - } - -@@ -149,7 +149,7 @@ static int scan_fsl_mc_bus(struct device - root_mc_dev = to_fsl_mc_device(dev); - root_mc_bus = to_fsl_mc_bus(root_mc_dev); - mutex_lock(&root_mc_bus->scan_mutex); -- dprc_scan_objects(root_mc_dev, &irq_count); -+ dprc_scan_objects(root_mc_dev, NULL, &irq_count); - mutex_unlock(&root_mc_bus->scan_mutex); - } - -@@ -503,6 +503,7 @@ bool fsl_mc_is_root_dprc(struct device * - int fsl_mc_device_add(struct dprc_obj_desc *obj_desc, - struct fsl_mc_io *mc_io, - struct device *parent_dev, -+ const char *driver_override, - struct fsl_mc_device **new_mc_dev) - { - int error; -@@ -535,6 +536,18 @@ int fsl_mc_device_add(struct dprc_obj_de - - mc_dev->obj_desc = *obj_desc; - mc_dev->mc_io = mc_io; -+ if (driver_override) { -+ /* -+ * We trust driver_override, so we don't need to use -+ * kstrndup() here -+ */ -+ mc_dev->driver_override = kstrdup(driver_override, GFP_KERNEL); -+ if (!mc_dev->driver_override) { -+ error = -ENOMEM; -+ goto error_cleanup_dev; -+ } -+ } -+ - device_initialize(&mc_dev->dev); - mc_dev->dev.parent = parent_dev; - mc_dev->dev.bus = &fsl_mc_bus_type; -@@ -858,7 +871,8 @@ static int fsl_mc_bus_probe(struct platf - obj_desc.irq_count = 1; - obj_desc.region_count = 0; - -- error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, &mc_bus_dev); -+ error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, NULL, -+ &mc_bus_dev); - if (error < 0) - goto error_cleanup_mc_io; - ---- a/drivers/staging/fsl-mc/include/mc-private.h -+++ b/drivers/staging/fsl-mc/include/mc-private.h -@@ -110,6 +110,7 @@ struct fsl_mc_bus { - int __must_check fsl_mc_device_add(struct dprc_obj_desc *obj_desc, - struct fsl_mc_io *mc_io, - struct device *parent_dev, -+ const char *driver_override, - struct fsl_mc_device **new_mc_dev); - - void fsl_mc_device_remove(struct fsl_mc_device *mc_dev); -@@ -117,6 +118,7 @@ void fsl_mc_device_remove(struct fsl_mc_ - int dprc_scan_container(struct fsl_mc_device *mc_bus_dev); - - int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, -+ const char *driver_override, - unsigned int *total_irq_count); - - int __init dprc_driver_init(void); ---- a/drivers/staging/fsl-mc/include/mc.h -+++ b/drivers/staging/fsl-mc/include/mc.h -@@ -129,6 +129,7 @@ struct fsl_mc_device_irq { - * @regions: pointer to array of MMIO region entries - * @irqs: pointer to array of pointers to interrupts allocated to this device - * @resource: generic resource associated with this MC object device, if any. -+ * @driver_override: Driver name to force a match - * - * Generic device object for MC object devices that are "attached" to a - * MC bus. -@@ -161,6 +162,7 @@ struct fsl_mc_device { - struct resource *regions; - struct fsl_mc_device_irq **irqs; - struct fsl_mc_resource *resource; -+ const char *driver_override; - }; - - #define to_fsl_mc_device(_dev) \ diff --git a/target/linux/layerscape/patches-4.4/7193-staging-fsl-mc-add-device-binding-path-driver_overri.patch b/target/linux/layerscape/patches-4.4/7193-staging-fsl-mc-add-device-binding-path-driver_overri.patch deleted file mode 100644 index 60d294a1da..0000000000 --- a/target/linux/layerscape/patches-4.4/7193-staging-fsl-mc-add-device-binding-path-driver_overri.patch +++ /dev/null @@ -1,111 +0,0 @@ -From 0bda83c15b2ecfc45fac0656df15d4f4fa65afa9 Mon Sep 17 00:00:00 2001 -From: Bharat Bhushan -Date: Wed, 18 Mar 2015 17:32:59 -0500 -Subject: [PATCH 193/226] staging: fsl-mc: add device binding path - 'driver_override' - -This patch is required for vfio-fsl-mc meta driver to successfully bind -layerscape container devices for device passthrough. This patch adds -a mechanism to allow a layerscape device to specify a driver rather than -a layerscape driver provide a device match. - -This patch is based on following proposed patches for PCI and platform devices -- https://lkml.org/lkml/2014/4/8/571 :- For Platform devices -- http://lists-archives.com/linux-kernel/28030441-pci-introduce-new-device-binding-path-using-pci_dev-driver_override.html :- For PCI devices - -Example to allow a device (dprc.1) to specifically bind -with driver (vfio-fsl-mc):- -- echo vfio-fsl-mc > /sys/bus/fsl-mc/devices/dprc.1/driver_override -- echo dprc.1 > /sys/bus/fsl-mc/drivers/fsl_mc_dprc/unbind -- echo dprc.1 > /sys/bus/fsl-mc/drivers/vfio-fsl-mc/bind - -Signed-off-by: J. German Rivera -(Stuart: resolved merge conflicts) -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 53 +++++++++++++++++++++++++++++++++++ - 1 file changed, 53 insertions(+) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -42,6 +42,12 @@ static int fsl_mc_bus_match(struct devic - if (WARN_ON(!fsl_mc_bus_exists())) - goto out; - -+ /* When driver_override is set, only bind to the matching driver */ -+ if (mc_dev->driver_override) { -+ found = !strcmp(mc_dev->driver_override, mc_drv->driver.name); -+ goto out; -+ } -+ - if (!mc_drv->match_id_table) - goto out; - -@@ -96,6 +102,50 @@ static ssize_t modalias_show(struct devi - } - static DEVICE_ATTR_RO(modalias); - -+static ssize_t driver_override_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); -+ const char *driver_override, *old = mc_dev->driver_override; -+ char *cp; -+ -+ if (WARN_ON(dev->bus != &fsl_mc_bus_type)) -+ return -EINVAL; -+ -+ if (count > PATH_MAX) -+ return -EINVAL; -+ -+ driver_override = kstrndup(buf, count, GFP_KERNEL); -+ if (!driver_override) -+ return -ENOMEM; -+ -+ cp = strchr(driver_override, '\n'); -+ if (cp) -+ *cp = '\0'; -+ -+ if (strlen(driver_override)) { -+ mc_dev->driver_override = driver_override; -+ } else { -+ kfree(driver_override); -+ mc_dev->driver_override = NULL; -+ } -+ -+ kfree(old); -+ -+ return count; -+} -+ -+static ssize_t driver_override_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); -+ -+ return sprintf(buf, "%s\n", mc_dev->driver_override); -+} -+ -+static DEVICE_ATTR_RW(driver_override); -+ - static ssize_t rescan_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -@@ -127,6 +177,7 @@ static DEVICE_ATTR_WO(rescan); - static struct attribute *fsl_mc_dev_attrs[] = { - &dev_attr_modalias.attr, - &dev_attr_rescan.attr, -+ &dev_attr_driver_override.attr, - NULL, - }; - -@@ -677,6 +728,8 @@ void fsl_mc_device_remove(struct fsl_mc_ - } - } - -+ kfree(mc_dev->driver_override); -+ mc_dev->driver_override = NULL; - if (mc_bus) - devm_kfree(mc_dev->dev.parent, mc_bus); - else diff --git a/target/linux/layerscape/patches-4.4/7194-staging-fsl-mc-export-irq-cleanup-for-vfio-to-use.patch b/target/linux/layerscape/patches-4.4/7194-staging-fsl-mc-export-irq-cleanup-for-vfio-to-use.patch deleted file mode 100644 index 0b926850c8..0000000000 --- a/target/linux/layerscape/patches-4.4/7194-staging-fsl-mc-export-irq-cleanup-for-vfio-to-use.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 552d628c887d970b9a97d8db2629adc4820fb8e3 Mon Sep 17 00:00:00 2001 -From: Bharat Bhushan -Date: Thu, 16 Jul 2015 14:44:24 +0530 -Subject: [PATCH 194/226] staging: fsl-mc: export irq cleanup for vfio to use - -VFIO driver needs these basic functions for -setting up itt/its of dprc's bound to it. - -Signed-off-by: Bharat Bhushan -(Stuart: resolved merge conflict, commit log cleanup) -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-mc/bus/dprc-driver.c | 4 ++-- - drivers/staging/fsl-mc/include/mc-private.h | 4 ++++ - 2 files changed, 6 insertions(+), 2 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dprc-driver.c -+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c -@@ -193,7 +193,7 @@ static void dprc_add_new_devices(struct - } - } - --static void dprc_init_all_resource_pools(struct fsl_mc_device *mc_bus_dev) -+void dprc_init_all_resource_pools(struct fsl_mc_device *mc_bus_dev) - { - int pool_type; - struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); -@@ -234,7 +234,7 @@ static void dprc_cleanup_resource_pool(s - WARN_ON(free_count != res_pool->free_count); - } - --static void dprc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev) -+void dprc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev) - { - int pool_type; - ---- a/drivers/staging/fsl-mc/include/mc-private.h -+++ b/drivers/staging/fsl-mc/include/mc-private.h -@@ -157,4 +157,8 @@ int fsl_mc_populate_irq_pool(struct fsl_ - - void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus); - -+void dprc_init_all_resource_pools(struct fsl_mc_device *mc_bus_dev); -+ -+void dprc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev); -+ - #endif /* _FSL_MC_PRIVATE_H_ */ diff --git a/target/linux/layerscape/patches-4.4/7195-increment-MC_CMD_COMPLETION_TIMEOUT_MS.patch b/target/linux/layerscape/patches-4.4/7195-increment-MC_CMD_COMPLETION_TIMEOUT_MS.patch deleted file mode 100644 index 438234b148..0000000000 --- a/target/linux/layerscape/patches-4.4/7195-increment-MC_CMD_COMPLETION_TIMEOUT_MS.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 71d19cd1107fa435d056e08e7d7ef7d8f714cf35 Mon Sep 17 00:00:00 2001 -From: Lijun Pan -Date: Fri, 31 Jul 2015 15:07:32 -0500 -Subject: [PATCH 195/226] increment MC_CMD_COMPLETION_TIMEOUT_MS - -5000ms is barely enough for dpsw/dpdmux creation. -If MC firmware could run faster, we would decrement the value later on. - -Signed-off-by: Lijun Pan -(Stuart: resolved merge conflict) -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-mc/bus/mc-sys.c | 38 +++++++++++++++-------------------- - 1 file changed, 16 insertions(+), 22 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/mc-sys.c -+++ b/drivers/staging/fsl-mc/bus/mc-sys.c -@@ -43,8 +43,10 @@ - - /** - * Timeout in milliseconds to wait for the completion of an MC command -+ * 5000 ms is barely enough for dpsw/dpdmux creation -+ * TODO: if MC firmware could response faster, we should decrease this value - */ --#define MC_CMD_COMPLETION_TIMEOUT_MS 500 -+#define MC_CMD_COMPLETION_TIMEOUT_MS 5000 - - /* - * usleep_range() min and max values used to throttle down polling -@@ -327,17 +329,8 @@ static int mc_polling_wait_preemptible(s - usleep_range(MC_CMD_COMPLETION_POLLING_MIN_SLEEP_USECS, - MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS); - -- if (time_after_eq(jiffies, jiffies_until_timeout)) { -- dev_dbg(mc_io->dev, -- "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n", -- mc_io->portal_phys_addr, -- (unsigned int) -- MC_CMD_HDR_READ_TOKEN(cmd->header), -- (unsigned int) -- MC_CMD_HDR_READ_CMDID(cmd->header)); -- -+ if (time_after_eq(jiffies, jiffies_until_timeout)) - return -ETIMEDOUT; -- } - } - - *mc_status = status; -@@ -369,17 +362,8 @@ static int mc_polling_wait_atomic(struct - - udelay(MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS); - timeout_usecs -= MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS; -- if (timeout_usecs == 0) { -- dev_dbg(mc_io->dev, -- "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n", -- mc_io->portal_phys_addr, -- (unsigned int) -- MC_CMD_HDR_READ_TOKEN(cmd->header), -- (unsigned int) -- MC_CMD_HDR_READ_CMDID(cmd->header)); -- -+ if (timeout_usecs == 0) - return -ETIMEDOUT; -- } - } - - *mc_status = status; -@@ -422,9 +406,19 @@ int mc_send_command(struct fsl_mc_io *mc - else - error = mc_polling_wait_atomic(mc_io, cmd, &status); - -- if (error < 0) -+ if (error < 0) { -+ if (error == -ETIMEDOUT) { -+ pr_debug("MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n", -+ mc_io->portal_phys_addr, -+ (unsigned int) -+ MC_CMD_HDR_READ_TOKEN(cmd->header), -+ (unsigned int) -+ MC_CMD_HDR_READ_CMDID(cmd->header)); -+ } - goto common_exit; - -+ } -+ - if (status != MC_CMD_STATUS_OK) { - dev_dbg(mc_io->dev, - "MC command failed: portal: %#llx, obj handle: %#x, command: %#x, status: %s (%#x)\n", diff --git a/target/linux/layerscape/patches-4.4/7196-staging-fsl-mc-make-fsl_mc_get_root_dprc-public.patch b/target/linux/layerscape/patches-4.4/7196-staging-fsl-mc-make-fsl_mc_get_root_dprc-public.patch deleted file mode 100644 index d465f90c33..0000000000 --- a/target/linux/layerscape/patches-4.4/7196-staging-fsl-mc-make-fsl_mc_get_root_dprc-public.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 12b1317fb3ab5b56efd833fa3b22965adf1d2c96 Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Fri, 15 Apr 2016 17:07:16 -0500 -Subject: [PATCH 196/226] staging: fsl-mc: make fsl_mc_get_root_dprc public - -this is needed by other components (e.g. vfio) to find -the root dprc - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-mc/bus/mc-bus.c | 3 ++- - drivers/staging/fsl-mc/include/mc.h | 3 +++ - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/staging/fsl-mc/bus/mc-bus.c -+++ b/drivers/staging/fsl-mc/bus/mc-bus.c -@@ -358,7 +358,7 @@ EXPORT_SYMBOL_GPL(fsl_mc_bus_exists); - /** - * fsl_mc_get_root_dprc - function to traverse to the root dprc - */ --static void fsl_mc_get_root_dprc(struct device *dev, -+void fsl_mc_get_root_dprc(struct device *dev, - struct device **root_dprc_dev) - { - if (WARN_ON(!dev)) { -@@ -371,6 +371,7 @@ static void fsl_mc_get_root_dprc(struct - *root_dprc_dev = (*root_dprc_dev)->parent; - } - } -+EXPORT_SYMBOL_GPL(fsl_mc_get_root_dprc); - - static int get_dprc_attr(struct fsl_mc_io *mc_io, - int container_id, struct dprc_attributes *attr) ---- a/drivers/staging/fsl-mc/include/mc.h -+++ b/drivers/staging/fsl-mc/include/mc.h -@@ -191,6 +191,9 @@ void fsl_mc_driver_unregister(struct fsl - - bool fsl_mc_bus_exists(void); - -+void fsl_mc_get_root_dprc(struct device *dev, -+ struct device **root_dprc_dev); -+ - int __must_check fsl_mc_portal_allocate(struct fsl_mc_device *mc_dev, - u16 mc_io_flags, - struct fsl_mc_io **new_mc_io); diff --git a/target/linux/layerscape/patches-4.4/7197-staging-fsl-mc-Management-Complex-restool-driver.patch b/target/linux/layerscape/patches-4.4/7197-staging-fsl-mc-Management-Complex-restool-driver.patch deleted file mode 100644 index 2a5e5df2be..0000000000 --- a/target/linux/layerscape/patches-4.4/7197-staging-fsl-mc-Management-Complex-restool-driver.patch +++ /dev/null @@ -1,489 +0,0 @@ -From fb4881d149742e4c5595aca8bf86c99d2ea155ad Mon Sep 17 00:00:00 2001 -From: Lijun Pan -Date: Mon, 8 Feb 2016 17:40:18 -0600 -Subject: [PATCH 197/226] staging: fsl-mc: Management Complex restool driver - -The kernel support for the restool (a user space resource management -tool) is a driver for the /dev/dprc.N device file. -Its purpose is to provide an ioctl interface, -which the restool uses to interact with the MC bus driver -and with the MC firmware. -We allocate a dpmcp at driver initialization, -and keep that dpmcp until driver exit. -We use that dpmcp by default. -If that dpmcp is in use, we create another portal at run time -and destroy the newly created portal after use. -The ioctl RESTOOL_SEND_MC_COMMAND sends user space command to fsl-mc -bus and utilizes the fsl-mc bus to communicate with MC firmware. -The ioctl RESTOOL_DPRC_SYNC request the mc-bus launch -objects scan under root dprc. -In order to support multiple root dprc, we utilize the bus notify -mechanism to scan fsl_mc_bus_type for the newly added root dprc. -After discovering the root dprc, it creates a miscdevice -/dev/dprc.N to associate with this root dprc. - -Signed-off-by: Lijun Pan -[Stuart: minor fix to resolve compile error] -Signed-off-by: Stuart Yoder ---- - Documentation/ioctl/ioctl-number.txt | 1 + - drivers/staging/fsl-mc/bus/Kconfig | 7 +- - drivers/staging/fsl-mc/bus/Makefile | 3 + - drivers/staging/fsl-mc/bus/mc-ioctl.h | 22 ++ - drivers/staging/fsl-mc/bus/mc-restool.c | 392 +++++++++++++++++++++++++++++++ - 5 files changed, 424 insertions(+), 1 deletion(-) - create mode 100644 drivers/staging/fsl-mc/bus/mc-ioctl.h - create mode 100644 drivers/staging/fsl-mc/bus/mc-restool.c - ---- a/Documentation/ioctl/ioctl-number.txt -+++ b/Documentation/ioctl/ioctl-number.txt -@@ -170,6 +170,7 @@ Code Seq#(hex) Include File Comments - 'R' 00-1F linux/random.h conflict! - 'R' 01 linux/rfkill.h conflict! - 'R' C0-DF net/bluetooth/rfcomm.h -+'R' E0-EF drivers/staging/fsl-mc/bus/mc-ioctl.h - 'S' all linux/cdrom.h conflict! - 'S' 80-81 scsi/scsi_ioctl.h conflict! - 'S' 82-FF scsi/scsi.h conflict! ---- a/drivers/staging/fsl-mc/bus/Kconfig -+++ b/drivers/staging/fsl-mc/bus/Kconfig -@@ -22,4 +22,9 @@ config FSL_MC_BUS - Only enable this option when building the kernel for - Freescale QorQIQ LS2xxxx SoCs. - -- -+config FSL_MC_RESTOOL -+ tristate "Freescale Management Complex (MC) restool driver" -+ depends on FSL_MC_BUS -+ help -+ Driver that provides kernel support for the Freescale Management -+ Complex resource manager user-space tool. ---- a/drivers/staging/fsl-mc/bus/Makefile -+++ b/drivers/staging/fsl-mc/bus/Makefile -@@ -18,3 +18,6 @@ mc-bus-driver-objs := mc-bus.o \ - dpmcp.o \ - dpbp.o \ - dpcon.o -+ -+# MC restool kernel support -+obj-$(CONFIG_FSL_MC_RESTOOL) += mc-restool.o ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/mc-ioctl.h -@@ -0,0 +1,22 @@ -+/* -+ * Freescale Management Complex (MC) ioclt interface -+ * -+ * Copyright (C) 2014 Freescale Semiconductor, Inc. -+ * Author: Lijun Pan -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+#ifndef _FSL_MC_IOCTL_H_ -+#define _FSL_MC_IOCTL_H_ -+ -+#include -+#include "../include/mc-sys.h" -+ -+#define RESTOOL_IOCTL_TYPE 'R' -+ -+#define RESTOOL_SEND_MC_COMMAND \ -+ _IOWR(RESTOOL_IOCTL_TYPE, 0xE0, struct mc_command) -+ -+#endif /* _FSL_MC_IOCTL_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/mc-restool.c -@@ -0,0 +1,392 @@ -+/* -+ * Freescale Management Complex (MC) restool driver -+ * -+ * Copyright (C) 2014 Freescale Semiconductor, Inc. -+ * Author: Lijun Pan -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include "../include/mc-private.h" -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "mc-ioctl.h" -+#include "../include/mc-sys.h" -+#include "../include/mc-cmd.h" -+#include "../include/dpmng.h" -+ -+/** -+ * Maximum number of DPRCs that can be opened at the same time -+ */ -+#define MAX_DPRC_HANDLES 64 -+ -+/** -+ * restool_misc - information associated with the newly added miscdevice -+ * @misc: newly created miscdevice associated with root dprc -+ * @miscdevt: device id of this miscdevice -+ * @list: a linked list node representing this miscdevcie -+ * @static_mc_io: pointer to the static MC I/O object used by the restool -+ * @dynamic_instance_count: number of dynamically created instances -+ * @static_instance_in_use: static instance is in use or not -+ * @mutex: mutex lock to serialze the open/release operations -+ * @dev: root dprc associated with this miscdevice -+ */ -+struct restool_misc { -+ struct miscdevice misc; -+ dev_t miscdevt; -+ struct list_head list; -+ struct fsl_mc_io *static_mc_io; -+ u32 dynamic_instance_count; -+ bool static_instance_in_use; -+ struct mutex mutex; /* serialze the open/release operations */ -+ struct device *dev; -+}; -+ -+/* -+ * initialize a global list to link all -+ * the miscdevice nodes (struct restool_misc) -+ */ -+static LIST_HEAD(misc_list); -+static DEFINE_MUTEX(misc_list_mutex); -+ -+static int fsl_mc_restool_dev_open(struct inode *inode, struct file *filep) -+{ -+ struct fsl_mc_device *root_mc_dev; -+ int error; -+ struct fsl_mc_io *dynamic_mc_io = NULL; -+ struct restool_misc *restool_misc = NULL; -+ struct restool_misc *restool_misc_cursor; -+ -+ mutex_lock(&misc_list_mutex); -+ -+ list_for_each_entry(restool_misc_cursor, &misc_list, list) { -+ if (restool_misc_cursor->miscdevt == inode->i_rdev) { -+ restool_misc = restool_misc_cursor; -+ break; -+ } -+ } -+ -+ mutex_unlock(&misc_list_mutex); -+ -+ if (!restool_misc) -+ return -EINVAL; -+ -+ if (WARN_ON(!restool_misc->dev)) -+ return -EINVAL; -+ -+ mutex_lock(&restool_misc->mutex); -+ -+ if (!restool_misc->static_instance_in_use) { -+ restool_misc->static_instance_in_use = true; -+ filep->private_data = restool_misc->static_mc_io; -+ } else { -+ dynamic_mc_io = kzalloc(sizeof(*dynamic_mc_io), GFP_KERNEL); -+ if (!dynamic_mc_io) { -+ error = -ENOMEM; -+ goto err_unlock; -+ } -+ -+ root_mc_dev = to_fsl_mc_device(restool_misc->dev); -+ error = fsl_mc_portal_allocate(root_mc_dev, 0, &dynamic_mc_io); -+ if (error < 0) { -+ pr_err("Not able to allocate MC portal\n"); -+ goto free_dynamic_mc_io; -+ } -+ ++restool_misc->dynamic_instance_count; -+ filep->private_data = dynamic_mc_io; -+ } -+ -+ mutex_unlock(&restool_misc->mutex); -+ -+ return 0; -+ -+free_dynamic_mc_io: -+ kfree(dynamic_mc_io); -+err_unlock: -+ mutex_unlock(&restool_misc->mutex); -+ -+ return error; -+} -+ -+static int fsl_mc_restool_dev_release(struct inode *inode, struct file *filep) -+{ -+ struct fsl_mc_io *local_mc_io = filep->private_data; -+ struct restool_misc *restool_misc = NULL; -+ struct restool_misc *restool_misc_cursor; -+ -+ if (WARN_ON(!filep->private_data)) -+ return -EINVAL; -+ -+ mutex_lock(&misc_list_mutex); -+ -+ list_for_each_entry(restool_misc_cursor, &misc_list, list) { -+ if (restool_misc_cursor->miscdevt == inode->i_rdev) { -+ restool_misc = restool_misc_cursor; -+ break; -+ } -+ } -+ -+ mutex_unlock(&misc_list_mutex); -+ -+ if (!restool_misc) -+ return -EINVAL; -+ -+ mutex_lock(&restool_misc->mutex); -+ -+ if (WARN_ON(restool_misc->dynamic_instance_count == 0 && -+ !restool_misc->static_instance_in_use)) { -+ mutex_unlock(&restool_misc->mutex); -+ return -EINVAL; -+ } -+ -+ /* Globally clean up opened/untracked handles */ -+ fsl_mc_portal_reset(local_mc_io); -+ -+ /* -+ * must check -+ * whether local_mc_io is dynamic or static instance -+ * Otherwise it will free up the reserved portal by accident -+ * or even not free up the dynamic allocated portal -+ * if 2 or more instances running concurrently -+ */ -+ if (local_mc_io == restool_misc->static_mc_io) { -+ restool_misc->static_instance_in_use = false; -+ } else { -+ fsl_mc_portal_free(local_mc_io); -+ kfree(filep->private_data); -+ --restool_misc->dynamic_instance_count; -+ } -+ -+ filep->private_data = NULL; -+ mutex_unlock(&restool_misc->mutex); -+ -+ return 0; -+} -+ -+static int restool_send_mc_command(unsigned long arg, -+ struct fsl_mc_io *local_mc_io) -+{ -+ int error; -+ struct mc_command mc_cmd; -+ -+ if (copy_from_user(&mc_cmd, (void __user *)arg, sizeof(mc_cmd))) -+ return -EFAULT; -+ -+ /* -+ * Send MC command to the MC: -+ */ -+ error = mc_send_command(local_mc_io, &mc_cmd); -+ if (error < 0) -+ return error; -+ -+ if (copy_to_user((void __user *)arg, &mc_cmd, sizeof(mc_cmd))) -+ return -EFAULT; -+ -+ return 0; -+} -+ -+static long -+fsl_mc_restool_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ int error; -+ -+ switch (cmd) { -+ case RESTOOL_SEND_MC_COMMAND: -+ error = restool_send_mc_command(arg, file->private_data); -+ break; -+ default: -+ pr_err("%s: unexpected ioctl call number\n", __func__); -+ error = -EINVAL; -+ } -+ -+ return error; -+} -+ -+static const struct file_operations fsl_mc_restool_dev_fops = { -+ .owner = THIS_MODULE, -+ .open = fsl_mc_restool_dev_open, -+ .release = fsl_mc_restool_dev_release, -+ .unlocked_ioctl = fsl_mc_restool_dev_ioctl, -+}; -+ -+static int restool_add_device_file(struct device *dev) -+{ -+ u32 name1 = 0; -+ char name2[20] = {0}; -+ int error; -+ struct fsl_mc_device *root_mc_dev; -+ struct restool_misc *restool_misc; -+ -+ if (dev->bus == &platform_bus_type && dev->driver_data) { -+ if (sscanf(dev_name(dev), "%x.%s", &name1, name2) != 2) -+ return -EINVAL; -+ -+ if (strcmp(name2, "fsl-mc") == 0) -+ pr_debug("platform's root dprc name is: %s\n", -+ dev_name(&(((struct fsl_mc *) -+ (dev->driver_data))->root_mc_bus_dev->dev))); -+ } -+ -+ if (!fsl_mc_is_root_dprc(dev)) -+ return 0; -+ -+ restool_misc = kzalloc(sizeof(*restool_misc), GFP_KERNEL); -+ if (!restool_misc) -+ return -ENOMEM; -+ -+ restool_misc->dev = dev; -+ root_mc_dev = to_fsl_mc_device(dev); -+ error = fsl_mc_portal_allocate(root_mc_dev, 0, -+ &restool_misc->static_mc_io); -+ if (error < 0) { -+ pr_err("Not able to allocate MC portal\n"); -+ goto free_restool_misc; -+ } -+ -+ restool_misc->misc.minor = MISC_DYNAMIC_MINOR; -+ restool_misc->misc.name = dev_name(dev); -+ restool_misc->misc.fops = &fsl_mc_restool_dev_fops; -+ -+ error = misc_register(&restool_misc->misc); -+ if (error < 0) { -+ pr_err("misc_register() failed: %d\n", error); -+ goto free_portal; -+ } -+ -+ restool_misc->miscdevt = restool_misc->misc.this_device->devt; -+ mutex_init(&restool_misc->mutex); -+ mutex_lock(&misc_list_mutex); -+ list_add(&restool_misc->list, &misc_list); -+ mutex_unlock(&misc_list_mutex); -+ -+ pr_info("/dev/%s driver registered\n", dev_name(dev)); -+ -+ return 0; -+ -+free_portal: -+ fsl_mc_portal_free(restool_misc->static_mc_io); -+free_restool_misc: -+ kfree(restool_misc); -+ -+ return error; -+} -+ -+static int restool_bus_notifier(struct notifier_block *nb, -+ unsigned long action, void *data) -+{ -+ int error; -+ struct device *dev = data; -+ -+ switch (action) { -+ case BUS_NOTIFY_ADD_DEVICE: -+ error = restool_add_device_file(dev); -+ if (error) -+ return error; -+ break; -+ case BUS_NOTIFY_DEL_DEVICE: -+ case BUS_NOTIFY_REMOVED_DEVICE: -+ case BUS_NOTIFY_BIND_DRIVER: -+ case BUS_NOTIFY_BOUND_DRIVER: -+ case BUS_NOTIFY_UNBIND_DRIVER: -+ case BUS_NOTIFY_UNBOUND_DRIVER: -+ break; -+ default: -+ pr_err("%s: unrecognized device action from %s\n", __func__, -+ dev_name(dev)); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int add_to_restool(struct device *dev, void *data) -+{ -+ return restool_add_device_file(dev); -+} -+ -+static int __init fsl_mc_restool_driver_init(void) -+{ -+ int error; -+ struct notifier_block *nb; -+ -+ nb = kzalloc(sizeof(*nb), GFP_KERNEL); -+ if (!nb) -+ return -ENOMEM; -+ -+ nb->notifier_call = restool_bus_notifier; -+ error = bus_register_notifier(&fsl_mc_bus_type, nb); -+ if (error) -+ goto free_nb; -+ -+ /* -+ * This driver runs after fsl-mc bus driver runs. -+ * Hence, many of the root dprcs are already attached to fsl-mc bus -+ * In order to make sure we find all the root dprcs, -+ * we need to scan the fsl_mc_bus_type. -+ */ -+ error = bus_for_each_dev(&fsl_mc_bus_type, NULL, NULL, add_to_restool); -+ if (error) { -+ bus_unregister_notifier(&fsl_mc_bus_type, nb); -+ kfree(nb); -+ pr_err("restool driver registration failure\n"); -+ return error; -+ } -+ -+ return 0; -+ -+free_nb: -+ kfree(nb); -+ return error; -+} -+ -+module_init(fsl_mc_restool_driver_init); -+ -+static void __exit fsl_mc_restool_driver_exit(void) -+{ -+ struct restool_misc *restool_misc; -+ struct restool_misc *restool_misc_tmp; -+ char name1[20] = {0}; -+ u32 name2 = 0; -+ -+ list_for_each_entry_safe(restool_misc, restool_misc_tmp, -+ &misc_list, list) { -+ if (sscanf(restool_misc->misc.name, "%4s.%u", name1, &name2) -+ != 2) -+ continue; -+ -+ pr_debug("name1=%s,name2=%u\n", name1, name2); -+ pr_debug("misc-device: %s\n", restool_misc->misc.name); -+ if (strcmp(name1, "dprc") != 0) -+ continue; -+ -+ if (WARN_ON(!restool_misc->static_mc_io)) -+ return; -+ -+ if (WARN_ON(restool_misc->dynamic_instance_count != 0)) -+ return; -+ -+ if (WARN_ON(restool_misc->static_instance_in_use)) -+ return; -+ -+ misc_deregister(&restool_misc->misc); -+ pr_info("/dev/%s driver unregistered\n", -+ restool_misc->misc.name); -+ fsl_mc_portal_free(restool_misc->static_mc_io); -+ list_del(&restool_misc->list); -+ kfree(restool_misc); -+ } -+} -+ -+module_exit(fsl_mc_restool_driver_exit); -+ -+MODULE_AUTHOR("Freescale Semiconductor Inc."); -+MODULE_DESCRIPTION("Freescale's MC restool driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/layerscape/patches-4.4/7198-staging-fsl-mc-dpio-services-driver.patch b/target/linux/layerscape/patches-4.4/7198-staging-fsl-mc-dpio-services-driver.patch deleted file mode 100644 index 7613d0a631..0000000000 --- a/target/linux/layerscape/patches-4.4/7198-staging-fsl-mc-dpio-services-driver.patch +++ /dev/null @@ -1,8943 +0,0 @@ -From 331b26080961f0289c3a8a8e5e65f6524b23be19 Mon Sep 17 00:00:00 2001 -From: Jeffrey Ladouceur -Date: Tue, 7 Apr 2015 23:24:55 -0400 -Subject: [PATCH 198/226] staging: fsl-mc: dpio services driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This is a commit of a squash of the cummulative dpio services patches -in the sdk 2.0 kernel as of 3/7/2016. - -staging: fsl-mc: dpio: initial implementation of dpio services - -* Port from kernel 3.16 to 3.19 -* upgrade to match MC fw 7.0.0 -* return -EPROBE_DEFER if fsl_mc_portal_allocate() fails. -* enable DPIO interrupt support -* implement service FQDAN handling -* DPIO service selects DPIO objects using crude algorithms for now, we - will look to make this smarter later on. -* Locks all DPIO ops that aren't innately lockless. Smarter selection - logic may allow locking to be relaxed eventually. -* Portable QBMan driver source (and low-level MC flib code for DPIO) is - included and encapsulated within the DPIO driver. - -Signed-off-by: Geoff Thorpe -Signed-off-by: Haiying Wang -Signed-off-by: Roy Pledge -Signed-off-by: Bogdan Hamciuc -Signed-off-by: Ioana Radulescu -Signed-off-by: Cristian Sovaiala -Signed-off-by: J. German Rivera -Signed-off-by: Jeffrey Ladouceur -[Stuart: resolved merge conflicts] -Signed-off-by: Stuart Yoder - -dpio: Use locks when querying fq state - -merged from patch in 3.19-bringup branch. - -Signed-off-by: Ioana Radulescu -Signed-off-by: Jeffrey Ladouceur -Change-Id: Ia4d09f8a0cf4d8a4a2aa1cb39be789c34425286d -Reviewed-on: http://git.am.freescale.net:8181/34707 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Haiying Wang -Reviewed-by: Stuart Yoder - -qbman: Fix potential race in VDQCR handling - -Remove atomic_read() check of the VDQCR busy marker. These checks were racy -as the flag could be incorrectly cleared if checked while another thread was -starting a pull command. The check is unneeded since we can determine the -owner of the outstanding pull command through other means. - -Signed-off-by: Roy Pledge -Change-Id: Icc64577c0a4ce6dadef208975e980adfc6796c86 -Reviewed-on: http://git.am.freescale.net:8181/34705 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Haiying Wang -Reviewed-by: Roy Pledge -Reviewed-by: Stuart Yoder - -dpio: Fix IRQ handler and remove useless spinlock - -The IRQ handler for a threaded IRQ requires two parts: initally the handler -should check status and inhibit the IRQ then the threaded portion should -process and reenable. - -Also remove a spinlock that was redundant with the QMan driver and a debug -check that could trigger under a race condition - -Signed-off-by: Roy Pledge -Signed-off-by: Jeffrey Ladouceur -Change-Id: I64926583af0be954228de94ae354fa005c8ec88a -Reviewed-on: http://git.am.freescale.net:8181/34706 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Haiying Wang -Reviewed-by: Roy Pledge -Reviewed-by: Stuart Yoder - -staging: fsl-mc: dpio: Implement polling if IRQ not available - -Temporarly add a polling mode to DPIO in the case that the IRQ -registration fails - -Signed-off-by: Roy Pledge -Change-Id: Iebbd488fd14dd9878ef846e40f3ebcbcd0eb1e80 -Reviewed-on: http://git.am.freescale.net:8181/34775 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Jeffrey Ladouceur -Reviewed-by: Stuart Yoder - -fsl-mc-dpio: Fix to make this work without interrupt - -Some additional fixes to make dpio driver work in poll mode. -This is needed for direct assignment to KVM Guest. - -Signed-off-by: Bharat Bhushan -Change-Id: Icf66b8c0c7f7e1610118f78396534c067f594934 -Reviewed-on: http://git.am.freescale.net:8181/35333 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Roy Pledge -Reviewed-by: Stuart Yoder - -fsl-mc-dpio: Make QBMan token tracking internal - -Previousy the QBMan portal code required the caller to properly set and -check for a token value used by the driver to detect when the QMan -hardware had completed a dequeue. This patch simplifes the driver -interface by internally dealing with token values. The driver will now -set the token value to 0 once it has dequeued a frame while a token -value of 1 indicates the HW has completed the dequeue but SW has not -consumed the frame yet. - -Signed-off-by: Roy Pledge -Change-Id: If94d9728b0faa0fd79b47108f5cb05a425b89c18 -Reviewed-on: http://git.am.freescale.net:8181/35433 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Haiying Wang -Reviewed-by: Stuart Yoder - -fsl-mc-dpio: Distribute DPIO IRQs among cores - -Configure the DPIO IRQ affinities across all available cores - -Signed-off-by: Roy Pledge -Change-Id: Ib45968a070460b7e9410bfe6067b20ecd3524c54 -Reviewed-on: http://git.am.freescale.net:8181/35540 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Haiying Wang -Reviewed-by: Bogdan Hamciuc -Reviewed-by: Stuart Yoder - -dpio/qbman: add flush after finishing cena write - -Signed-off-by: Haiying Wang -Change-Id: I19537f101f7f5b443d60c0ad0e5d96c1dc302223 -Reviewed-on: http://git.am.freescale.net:8181/35854 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Roy Pledge -Reviewed-by: Stuart Yoder - -dpio/qbman: rename qbman_dq_entry to qbman_result - -Currently qbman_dq_entry is used for both dq result in dqrr -and memory, and notifications in dqrr and memory. It doesn't -make sense to have dq_entry in name for those notifications -which have nothing to do with dq. So we rename this as -qbman_result which is meaningful for both cases. - -Signed-off-by: Haiying Wang -Change-Id: I62b3e729c571a1195e8802a9fab3fca97a14eae4 -Reviewed-on: http://git.am.freescale.net:8181/35535 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Roy Pledge -Reviewed-by: Stuart Yoder - -dpio/qbman: add APIs to parse BPSCN and CGCU - -BPSCN and CGCU are notifications which can only be written to memory. -We need to consider the host endianness while parsing these notification. -Also modify the check of FQRN/CSCN_MEM with the same consideration. - -Signed-off-by: Haiying Wang -Change-Id: I572e0aa126107aed40e1ce326d5df7956882a939 -Reviewed-on: http://git.am.freescale.net:8181/35536 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Roy Pledge -Reviewed-by: Stuart Yoder - -dpio/qbman: remove EXPORT_SYMBOL for qbman APIs - -because they are only used by dpio. - -Signed-off-by: Haiying Wang -Change-Id: I12e7b81c2d32f3c7b3df9fd73b742b1b675f4b8b -Reviewed-on: http://git.am.freescale.net:8181/35537 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Roy Pledge -Reviewed-by: Stuart Yoder - -dpio/qbman: add invalidate and prefetch support - -for cachable memory access. -Also remove the redundant memory barriers. - -Signed-off-by: Haiying Wang -Change-Id: I452a768278d1c5ef37e5741e9b011d725cb57b30 -Reviewed-on: http://git.am.freescale.net:8181/35873 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Roy Pledge -Reviewed-by: Stuart Yoder - -dpio-driver: Fix qman-portal interrupt masking in poll mode - -DPIO driver should mask qman-portal interrupt reporting When -working in poll mode. has_irq flag is used for same, but -interrupt maksing was happening before it was decided that -system will work in poll mode of interrupt mode. - -This patch fixes the issue and not irq masking/enabling is -happening after irq/poll mode is decided. - -Signed-off-by: Bharat Bhushan -Change-Id: I44de07b6142e80b3daea45e7d51a2d2799b2ed8d -Reviewed-on: http://git.am.freescale.net:8181/37100 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Roy Pledge -Reviewed-by: Stuart Yoder -(cherry picked from commit 3579244250dcb287a0fe58bcc3b3780076d040a2) - -dpio: Add a function to query buffer pool depth - -Add a debug function thay allows users to query the number -of buffers in a specific buffer pool - -Signed-off-by: Roy Pledge -Change-Id: Ie9a5f2e86d6a04ae61868bcc807121780c53cf6c -Reviewed-on: http://git.am.freescale.net:8181/36069 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder -(cherry picked from commit 3c749d860592f62f6b219232580ca35fd1075337) - -dpio: Use normal cachable non-shareable memory for qbman cena - -QBMan SWP CENA portal memory requires the memory to be cacheable, -and non-shareable. - -Signed-off-by: Haiying Wang -Change-Id: I1c01cffe9ff2503fea2396d7cc761508f6e1ca85 -Reviewed-on: http://git.am.freescale.net:8181/35487 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder -(cherry picked from commit 2a7e1ede7e155d9219006999893912e0b029ce4c) - -fsl-dpio: Process frames in IRQ context - -Stop using threaded IRQs and move back to hardirq top-halves. -This is the first patch of a small series adapting the DPIO and Ethernet -code to these changes. - -Signed-off-by: Roy Pledge -Tested-by: Ioana Radulescu -Tested-by: Bogdan Hamciuc -Tested-by: Review Code-CDREVIEW -Reviewed-by: Bogdan Hamciuc -Reviewed-by: Stuart Yoder -[Stuart: split out dpaa-eth part separately] -Signed-off-by: Stuart Yoder - -fsl-dpio: Fast DPIO object selection - -The DPIO service code had a couple of problems with performance impact: - - The DPIO service object was protected by a global lock, within - functions called from the fast datapath on multiple CPUs. - - The DPIO service code would iterate unnecessarily through its linked - list, while most of the time it looks for CPU-bound objects. - -Add a fast-access array pointing to the same dpaa_io objects as the DPIO -service's linked list, used in non-preemptible contexts. -Avoid list access/reordering if a specific CPU was requested. This -greatly limits contention on the global service lock. -Make explicit calls for per-CPU DPIO service objects if the current -context permits (which is the case on most of the Ethernet fastpath). - -These changes incidentally fix a functional problem, too: according to -the specification of struct dpaa_io_notification_ctx, registration should -fail if the specification of 'desired_cpu' cannot be observed. Instead, -dpaa_io_service_register() would keep searching for non-affine DPIO -objects, even when that was not requested. - -Signed-off-by: Bogdan Hamciuc -Change-Id: I2dd78bc56179f97d3fd78052a653456e5f89ed82 -Reviewed-on: http://git.am.freescale.net:8181/37689 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Roy Pledge -Reviewed-by: Stuart Yoder - -DPIO: Implement a missing lock in DPIO - -Implement missing DPIO service notification deregistration lock - -Signed-off-by: Roy Pledge -Change-Id: Ida9a4d00cc3a66bc215c260a8df2b197366736f7 -Reviewed-on: http://git.am.freescale.net:8181/38497 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Haiying Wang -Reviewed-by: Stuart Yoder - -staging: fsl-mc: migrated dpio flibs for MC fw 8.0.0 - -Signed-off-by: Stuart Yoder - -fsl_qbman: Ensure SDQCR is only enabled if a channel is selected - -QMan HW considers an SDQCR command that does not indicate any -channels to dequeue from to be an error. This change ensures that -a NULL command is set in the case no channels are selected for dequeue - -Signed-off-by: Roy Pledge -Change-Id: I8861304881885db00df4a29d760848990d706c70 -Reviewed-on: http://git.am.freescale.net:8181/38498 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Haiying Wang -Reviewed-by: Stuart Yoder - -flib: dpio: Fix compiler warning. - -Gcc takes the credit here. -To be merged with other fixes on this branch. - -Signed-off-by: Bogdan Hamciuc -Change-Id: If81f35ab3e8061aae1e03b72ab16a4c1dc390c3a -Reviewed-on: http://git.am.freescale.net:8181/39148 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -staging: fsl-mc: dpio: remove programing of MSIs in dpio driver - -this is now handled in the bus driver - -Signed-off-by: Stuart Yoder - -fsl_qbman: Enable CDAN generation - -Enable CDAN notificiation registration in both QBMan and DPIO - -Signed-off-by: Roy Pledge - -fsl_dpio: Implement API to dequeue from a channel - -Implement an API that allows users to dequeue from a channel - -Signed-off-by: Roy Pledge - -fsl-dpio: Change dequeue command type - -For now CDANs don't work with priority precedence. - -Signed-off-by: Ioana Radulescu - -fsl-dpio: Export FQD context getter function - -Signed-off-by: Ioana Radulescu - -fsl_dpio: Fix DPIO polling thread logic - -Fix the logic for the DPIO polling logic and ensure the thread -is not parked - -Signed-off-by: Roy Pledge -[Stuart: fixed typo in comment] -Signed-off-by: Stuart Yoder - -fsl-dpio,qbman: Export functions - -A few of the functions used by the Ethernet driver were not exported -yet. Needed in order to compile Eth driver as a module. - -Signed-off-by: Ioana Radulescu -Signed-off-by: Stuart Yoder - -fsl_qbman: Use proper accessors when reading QBMan portals - -Use accessors that properly byteswap when accessing QBMan portals - -Signed-off-by: Roy Pledge - -fsl_qbman: Fix encoding of 64 byte values - -The QBMan driver encodes commands in 32 bit host endianess then -coverts to little endian before sending to HW. This means 64 -byte values need to be encoded so that the values will be -correctly swapped when the commands are written to HW. - -Signed-off-by: Roy Pledge - -dpaa_fd: Add functions for SG entries endianness conversions - -Scatter gather entries are little endian at the hardware level. -Add functions for converting the SG entry structure to cpu -endianness to avoid incorrect behaviour on BE kernels. - -Signed-off-by: Ioana Radulescu - -fsl_dpaa: update header files with kernel-doc format - -Signed-off-by: Haiying Wang - -qbman: update header fiels to follow kernel-doc format - -Plus rename orp_id as opr_id based on the BG. - -Signed-off-by: Haiying Wang - -fsl/dpio: rename ldpaa to dpaa2 - -Signed-off-by: Haiying Wang -(Stuart: removed eth part out into separate patch) -Signed-off-by: Stuart Yoder - -qbman_test: update qbman_test - -- Update to sync with latest change in qbman driver. -- Add bpscn test case - -Signed-off-by: Haiying Wang - -fsl-dpio: add FLE (Frame List Entry) for FMT=dpaa_fd_list support - -Signed-off-by: Horia Geantă - -fsl-dpio: add accessors for FD[FRC] - -Signed-off-by: Horia Geantă - -fsl-dpio: add accessors for FD[FLC] - -Signed-off-by: Horia Geantă -(Stuart: corrected typo in subject) -Signed-off-by: Stuart Yoder - -fsl/dpio: dpaa2_fd: Add the comments for newly added APIs. - -Signed-off-by: Haiying Wang -[Stuart: added fsl/dpio prefix on commit subject] -Signed-off-by: Stuart Yoder - -fsl-dpio: rename dpaa_* structure to dpaa2_* - -Signed-off-by: Haiying Wang -(Stuart: split eth and caam parts out into separate patches) -Signed-off-by: Stuart Yoder - -fsl-dpio: update the header file with more description in comments - -plus fix some typos. - -Signed-off-by: Haiying Wang -Signed-off-by: Roy Pledge - -fsl-dpio: fix Klocwork issues. - -Signed-off-by: Haiying Wang - -fsl_dpio: Fix kernel doc issues and add an overview - -Signed-off-by: Roy Pledge - -fsl-dpio,qbman: Prefer affine portal to acquire/release buffers - -The FQ enqueue/dequeue DPIO code attempts to select an affine QBMan -portal in order to minimize contention (under the assumption that most -of the calling code runs in affine contexts). Doing the same now for -buffer acquire/release. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpio: prefer affine QBMan portal in dpaa2_io_service_enqueue_fq - -Commit 7b057d9bc3d31 ("fsl-dpio: Fast DPIO object selection") -took care of dpaa2_io_service_enqueue_qd, missing -dpaa2_io_service_enqueue_fq. - -Cc: Bogdan Hamciuc -Signed-off-by: Horia Geantă - -fsl/dpio: update the dpio flib files from mc9.0.0 release - -Signed-off-by: Haiying Wang - -fsl/dpio: pass qman_version from dpio attributes to swp desc - -Signed-off-by: Haiying Wang - -fsl/dpio/qbman: Use qman version to determin dqrr size - -Signed-off-by: Haiying Wang - -fsl-dpio: Fix dequeue type enum values - -enum qbman_pull_type_e did not follow the volatile dequeue command -specification, for which VERB=b'00 is a valid value (but of no -interest to us). - -Signed-off-by: Bogdan Hamciuc -Signed-off-by: Roy Pledge - -fsl-dpio: Volatile dequeue with priority precedence - -Use priority precedence to do volatile dequeue from channels, rather -than active FQ precedence. - -Signed-off-by: Bogdan Hamciuc -Signed-off-by: Roy Pledge - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-mc/bus/Kconfig | 16 + - drivers/staging/fsl-mc/bus/Makefile | 3 + - drivers/staging/fsl-mc/bus/dpio/Makefile | 9 + - drivers/staging/fsl-mc/bus/dpio/dpio-drv.c | 405 +++++++ - drivers/staging/fsl-mc/bus/dpio/dpio-drv.h | 33 + - drivers/staging/fsl-mc/bus/dpio/dpio.c | 468 ++++++++ - drivers/staging/fsl-mc/bus/dpio/dpio_service.c | 801 +++++++++++++ - drivers/staging/fsl-mc/bus/dpio/fsl_dpio.h | 460 ++++++++ - drivers/staging/fsl-mc/bus/dpio/fsl_dpio_cmd.h | 184 +++ - drivers/staging/fsl-mc/bus/dpio/fsl_qbman_base.h | 123 ++ - drivers/staging/fsl-mc/bus/dpio/fsl_qbman_portal.h | 753 ++++++++++++ - drivers/staging/fsl-mc/bus/dpio/qbman_debug.c | 846 ++++++++++++++ - drivers/staging/fsl-mc/bus/dpio/qbman_debug.h | 136 +++ - drivers/staging/fsl-mc/bus/dpio/qbman_portal.c | 1212 ++++++++++++++++++++ - drivers/staging/fsl-mc/bus/dpio/qbman_portal.h | 261 +++++ - drivers/staging/fsl-mc/bus/dpio/qbman_private.h | 173 +++ - drivers/staging/fsl-mc/bus/dpio/qbman_sys.h | 307 +++++ - drivers/staging/fsl-mc/bus/dpio/qbman_sys_decl.h | 86 ++ - drivers/staging/fsl-mc/bus/dpio/qbman_test.c | 664 +++++++++++ - drivers/staging/fsl-mc/include/fsl_dpaa2_fd.h | 774 +++++++++++++ - drivers/staging/fsl-mc/include/fsl_dpaa2_io.h | 619 ++++++++++ - 21 files changed, 8333 insertions(+) - create mode 100644 drivers/staging/fsl-mc/bus/dpio/Makefile - create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-drv.c - create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-drv.h - create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio.c - create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio_service.c - create mode 100644 drivers/staging/fsl-mc/bus/dpio/fsl_dpio.h - create mode 100644 drivers/staging/fsl-mc/bus/dpio/fsl_dpio_cmd.h - create mode 100644 drivers/staging/fsl-mc/bus/dpio/fsl_qbman_base.h - create mode 100644 drivers/staging/fsl-mc/bus/dpio/fsl_qbman_portal.h - create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_debug.c - create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_debug.h - create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_portal.c - create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_portal.h - create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_private.h - create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_sys.h - create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_sys_decl.h - create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_test.c - create mode 100644 drivers/staging/fsl-mc/include/fsl_dpaa2_fd.h - create mode 100644 drivers/staging/fsl-mc/include/fsl_dpaa2_io.h - ---- a/drivers/staging/fsl-mc/bus/Kconfig -+++ b/drivers/staging/fsl-mc/bus/Kconfig -@@ -28,3 +28,19 @@ config FSL_MC_RESTOOL - help - Driver that provides kernel support for the Freescale Management - Complex resource manager user-space tool. -+ -+config FSL_MC_DPIO -+ tristate "Freescale Data Path I/O (DPIO) driver" -+ depends on FSL_MC_BUS -+ help -+ Driver for Freescale Data Path I/O (DPIO) devices. -+ A DPIO device provides queue and buffer management facilities -+ for software to interact with other Data Path devices. This -+ driver does not expose the DPIO device individually, but -+ groups them under a service layer API. -+ -+config FSL_QBMAN_DEBUG -+ tristate "Freescale QBMAN Debug APIs" -+ depends on FSL_MC_DPIO -+ help -+ QBMan debug assistant APIs. ---- a/drivers/staging/fsl-mc/bus/Makefile -+++ b/drivers/staging/fsl-mc/bus/Makefile -@@ -21,3 +21,6 @@ mc-bus-driver-objs := mc-bus.o \ - - # MC restool kernel support - obj-$(CONFIG_FSL_MC_RESTOOL) += mc-restool.o -+ -+# MC DPIO driver -+obj-$(CONFIG_FSL_MC_DPIO) += dpio/ ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/Makefile -@@ -0,0 +1,9 @@ -+# -+# Freescale DPIO driver -+# -+ -+obj-$(CONFIG_FSL_MC_BUS) += fsl-dpio-drv.o -+ -+fsl-dpio-drv-objs := dpio-drv.o dpio_service.o dpio.o qbman_portal.o -+ -+obj-$(CONFIG_FSL_QBMAN_DEBUG) += qbman_debug.o ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/dpio-drv.c -@@ -0,0 +1,405 @@ -+/* Copyright 2014 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../../include/mc.h" -+#include "../../include/fsl_dpaa2_io.h" -+ -+#include "fsl_qbman_portal.h" -+#include "fsl_dpio.h" -+#include "fsl_dpio_cmd.h" -+ -+#include "dpio-drv.h" -+ -+#define DPIO_DESCRIPTION "DPIO Driver" -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("Freescale Semiconductor, Inc"); -+MODULE_DESCRIPTION(DPIO_DESCRIPTION); -+ -+#define MAX_DPIO_IRQ_NAME 16 /* Big enough for "FSL DPIO %d" */ -+ -+struct dpio_priv { -+ struct dpaa2_io *io; -+ char irq_name[MAX_DPIO_IRQ_NAME]; -+ struct task_struct *thread; -+}; -+ -+static int dpio_thread(void *data) -+{ -+ struct dpaa2_io *io = data; -+ -+ while (!kthread_should_stop()) { -+ int err = dpaa2_io_poll(io); -+ -+ if (err) { -+ pr_err("dpaa2_io_poll() failed\n"); -+ return err; -+ } -+ msleep(50); -+ } -+ return 0; -+} -+ -+static irqreturn_t dpio_irq_handler(int irq_num, void *arg) -+{ -+ struct device *dev = (struct device *)arg; -+ struct dpio_priv *priv = dev_get_drvdata(dev); -+ -+ return dpaa2_io_irq(priv->io); -+} -+ -+static void unregister_dpio_irq_handlers(struct fsl_mc_device *ls_dev) -+{ -+ int i; -+ struct fsl_mc_device_irq *irq; -+ int irq_count = ls_dev->obj_desc.irq_count; -+ -+ for (i = 0; i < irq_count; i++) { -+ irq = ls_dev->irqs[i]; -+ devm_free_irq(&ls_dev->dev, irq->msi_desc->irq, &ls_dev->dev); -+ } -+} -+ -+static int register_dpio_irq_handlers(struct fsl_mc_device *ls_dev, int cpu) -+{ -+ struct dpio_priv *priv; -+ unsigned int i; -+ int error; -+ struct fsl_mc_device_irq *irq; -+ unsigned int num_irq_handlers_registered = 0; -+ int irq_count = ls_dev->obj_desc.irq_count; -+ cpumask_t mask; -+ -+ priv = dev_get_drvdata(&ls_dev->dev); -+ -+ if (WARN_ON(irq_count != 1)) -+ return -EINVAL; -+ -+ for (i = 0; i < irq_count; i++) { -+ irq = ls_dev->irqs[i]; -+ error = devm_request_irq(&ls_dev->dev, -+ irq->msi_desc->irq, -+ dpio_irq_handler, -+ 0, -+ priv->irq_name, -+ &ls_dev->dev); -+ if (error < 0) { -+ dev_err(&ls_dev->dev, -+ "devm_request_irq() failed: %d\n", -+ error); -+ goto error_unregister_irq_handlers; -+ } -+ -+ /* Set the IRQ affinity */ -+ cpumask_clear(&mask); -+ cpumask_set_cpu(cpu, &mask); -+ if (irq_set_affinity(irq->msi_desc->irq, &mask)) -+ pr_err("irq_set_affinity failed irq %d cpu %d\n", -+ irq->msi_desc->irq, cpu); -+ -+ num_irq_handlers_registered++; -+ } -+ -+ return 0; -+ -+error_unregister_irq_handlers: -+ for (i = 0; i < num_irq_handlers_registered; i++) { -+ irq = ls_dev->irqs[i]; -+ devm_free_irq(&ls_dev->dev, irq->msi_desc->irq, -+ &ls_dev->dev); -+ } -+ -+ return error; -+} -+ -+static int __cold -+dpaa2_dpio_probe(struct fsl_mc_device *ls_dev) -+{ -+ struct dpio_attr dpio_attrs; -+ struct dpaa2_io_desc desc; -+ struct dpio_priv *priv; -+ int err = -ENOMEM; -+ struct device *dev = &ls_dev->dev; -+ struct dpaa2_io *defservice; -+ bool irq_allocated = false; -+ static int next_cpu; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ goto err_priv_alloc; -+ -+ dev_set_drvdata(dev, priv); -+ -+ err = fsl_mc_portal_allocate(ls_dev, 0, &ls_dev->mc_io); -+ if (err) { -+ dev_err(dev, "MC portal allocation failed\n"); -+ err = -EPROBE_DEFER; -+ goto err_mcportal; -+ } -+ -+ err = dpio_open(ls_dev->mc_io, 0, ls_dev->obj_desc.id, -+ &ls_dev->mc_handle); -+ if (err) { -+ dev_err(dev, "dpio_open() failed\n"); -+ goto err_open; -+ } -+ -+ err = dpio_get_attributes(ls_dev->mc_io, 0, ls_dev->mc_handle, -+ &dpio_attrs); -+ if (err) { -+ dev_err(dev, "dpio_get_attributes() failed %d\n", err); -+ goto err_get_attr; -+ } -+ err = dpio_enable(ls_dev->mc_io, 0, ls_dev->mc_handle); -+ if (err) { -+ dev_err(dev, "dpio_enable() failed %d\n", err); -+ goto err_get_attr; -+ } -+ pr_info("ce_paddr=0x%llx, ci_paddr=0x%llx, portalid=%d, prios=%d\n", -+ ls_dev->regions[0].start, -+ ls_dev->regions[1].start, -+ dpio_attrs.qbman_portal_id, -+ dpio_attrs.num_priorities); -+ -+ pr_info("ce_size=0x%llx, ci_size=0x%llx\n", -+ resource_size(&ls_dev->regions[0]), -+ resource_size(&ls_dev->regions[1])); -+ -+ desc.qman_version = dpio_attrs.qbman_version; -+ /* Build DPIO driver object out of raw MC object */ -+ desc.receives_notifications = dpio_attrs.num_priorities ? 1 : 0; -+ desc.has_irq = 1; -+ desc.will_poll = 1; -+ desc.has_8prio = dpio_attrs.num_priorities == 8 ? 1 : 0; -+ desc.cpu = next_cpu; -+ desc.stash_affinity = 1; /* TODO: Figure out how to determine -+ this setting - will we ever have non-affine -+ portals where we stash to a platform cache? */ -+ next_cpu = (next_cpu + 1) % num_active_cpus(); -+ desc.dpio_id = ls_dev->obj_desc.id; -+ desc.regs_cena = ioremap_cache_ns(ls_dev->regions[0].start, -+ resource_size(&ls_dev->regions[0])); -+ desc.regs_cinh = ioremap(ls_dev->regions[1].start, -+ resource_size(&ls_dev->regions[1])); -+ -+ err = fsl_mc_allocate_irqs(ls_dev); -+ if (err) { -+ dev_err(dev, "DPIO fsl_mc_allocate_irqs failed\n"); -+ desc.has_irq = 0; -+ } else { -+ irq_allocated = true; -+ -+ snprintf(priv->irq_name, MAX_DPIO_IRQ_NAME, "FSL DPIO %d", -+ desc.dpio_id); -+ -+ err = register_dpio_irq_handlers(ls_dev, desc.cpu); -+ if (err) -+ desc.has_irq = 0; -+ } -+ -+ priv->io = dpaa2_io_create(&desc); -+ if (!priv->io) { -+ dev_err(dev, "DPIO setup failed\n"); -+ goto err_dpaa2_io_create; -+ } -+ -+ /* If no irq then go to poll mode */ -+ if (desc.has_irq == 0) { -+ dev_info(dev, "Using polling mode for DPIO %d\n", -+ desc.dpio_id); -+ /* goto err_register_dpio_irq; */ -+ /* TEMP: Start polling if IRQ could not -+ be registered. This will go away once -+ KVM support for MSI is present */ -+ if (irq_allocated == true) -+ fsl_mc_free_irqs(ls_dev); -+ -+ if (desc.stash_affinity) -+ priv->thread = kthread_create_on_cpu(dpio_thread, -+ priv->io, -+ desc.cpu, -+ "dpio_aff%u"); -+ else -+ priv->thread = -+ kthread_create(dpio_thread, -+ priv->io, -+ "dpio_non%u", -+ dpio_attrs.qbman_portal_id); -+ if (IS_ERR(priv->thread)) { -+ dev_err(dev, "DPIO thread failure\n"); -+ err = PTR_ERR(priv->thread); -+ goto err_dpaa_thread; -+ } -+ kthread_unpark(priv->thread); -+ wake_up_process(priv->thread); -+ } -+ -+ defservice = dpaa2_io_default_service(); -+ err = dpaa2_io_service_add(defservice, priv->io); -+ dpaa2_io_down(defservice); -+ if (err) { -+ dev_err(dev, "DPIO add-to-service failed\n"); -+ goto err_dpaa2_io_add; -+ } -+ -+ dev_info(dev, "dpio: probed object %d\n", ls_dev->obj_desc.id); -+ dev_info(dev, " receives_notifications = %d\n", -+ desc.receives_notifications); -+ dev_info(dev, " has_irq = %d\n", desc.has_irq); -+ dpio_close(ls_dev->mc_io, 0, ls_dev->mc_handle); -+ fsl_mc_portal_free(ls_dev->mc_io); -+ return 0; -+ -+err_dpaa2_io_add: -+ unregister_dpio_irq_handlers(ls_dev); -+/* TEMP: To be restored once polling is removed -+ err_register_dpio_irq: -+ fsl_mc_free_irqs(ls_dev); -+*/ -+err_dpaa_thread: -+err_dpaa2_io_create: -+ dpio_disable(ls_dev->mc_io, 0, ls_dev->mc_handle); -+err_get_attr: -+ dpio_close(ls_dev->mc_io, 0, ls_dev->mc_handle); -+err_open: -+ fsl_mc_portal_free(ls_dev->mc_io); -+err_mcportal: -+ dev_set_drvdata(dev, NULL); -+ devm_kfree(dev, priv); -+err_priv_alloc: -+ return err; -+} -+ -+/* -+ * Tear down interrupts for a given DPIO object -+ */ -+static void dpio_teardown_irqs(struct fsl_mc_device *ls_dev) -+{ -+ /* (void)disable_dpio_irqs(ls_dev); */ -+ unregister_dpio_irq_handlers(ls_dev); -+ fsl_mc_free_irqs(ls_dev); -+} -+ -+static int __cold -+dpaa2_dpio_remove(struct fsl_mc_device *ls_dev) -+{ -+ struct device *dev; -+ struct dpio_priv *priv; -+ int err; -+ -+ dev = &ls_dev->dev; -+ priv = dev_get_drvdata(dev); -+ -+ /* there is no implementation yet for pulling a DPIO object out of a -+ * running service (and they're currently always running). -+ */ -+ dev_crit(dev, "DPIO unplugging is broken, the service holds onto it\n"); -+ -+ if (priv->thread) -+ kthread_stop(priv->thread); -+ else -+ dpio_teardown_irqs(ls_dev); -+ -+ err = fsl_mc_portal_allocate(ls_dev, 0, &ls_dev->mc_io); -+ if (err) { -+ dev_err(dev, "MC portal allocation failed\n"); -+ goto err_mcportal; -+ } -+ -+ err = dpio_open(ls_dev->mc_io, 0, ls_dev->obj_desc.id, -+ &ls_dev->mc_handle); -+ if (err) { -+ dev_err(dev, "dpio_open() failed\n"); -+ goto err_open; -+ } -+ -+ dev_set_drvdata(dev, NULL); -+ dpaa2_io_down(priv->io); -+ -+ err = 0; -+ -+ dpio_disable(ls_dev->mc_io, 0, ls_dev->mc_handle); -+ dpio_close(ls_dev->mc_io, 0, ls_dev->mc_handle); -+err_open: -+ fsl_mc_portal_free(ls_dev->mc_io); -+err_mcportal: -+ return err; -+} -+ -+static const struct fsl_mc_device_match_id dpaa2_dpio_match_id_table[] = { -+ { -+ .vendor = FSL_MC_VENDOR_FREESCALE, -+ .obj_type = "dpio", -+ .ver_major = DPIO_VER_MAJOR, -+ .ver_minor = DPIO_VER_MINOR -+ }, -+ { .vendor = 0x0 } -+}; -+ -+static struct fsl_mc_driver dpaa2_dpio_driver = { -+ .driver = { -+ .name = KBUILD_MODNAME, -+ .owner = THIS_MODULE, -+ }, -+ .probe = dpaa2_dpio_probe, -+ .remove = dpaa2_dpio_remove, -+ .match_id_table = dpaa2_dpio_match_id_table -+}; -+ -+static int dpio_driver_init(void) -+{ -+ int err; -+ -+ err = dpaa2_io_service_driver_init(); -+ if (!err) { -+ err = fsl_mc_driver_register(&dpaa2_dpio_driver); -+ if (err) -+ dpaa2_io_service_driver_exit(); -+ } -+ return err; -+} -+static void dpio_driver_exit(void) -+{ -+ fsl_mc_driver_unregister(&dpaa2_dpio_driver); -+ dpaa2_io_service_driver_exit(); -+} -+module_init(dpio_driver_init); -+module_exit(dpio_driver_exit); ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/dpio-drv.h -@@ -0,0 +1,33 @@ -+/* Copyright 2014 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+int dpaa2_io_service_driver_init(void); -+void dpaa2_io_service_driver_exit(void); ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/dpio.c -@@ -0,0 +1,468 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include "../../include/mc-sys.h" -+#include "../../include/mc-cmd.h" -+#include "fsl_dpio.h" -+#include "fsl_dpio_cmd.h" -+ -+int dpio_open(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ int dpio_id, -+ uint16_t *token) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN, -+ cmd_flags, -+ 0); -+ DPIO_CMD_OPEN(cmd, dpio_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header); -+ -+ return 0; -+} -+ -+int dpio_close(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLOSE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpio_create(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ const struct dpio_cfg *cfg, -+ uint16_t *token) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_CREATE, -+ cmd_flags, -+ 0); -+ DPIO_CMD_CREATE(cmd, cfg); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header); -+ -+ return 0; -+} -+ -+int dpio_destroy(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_DESTROY, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpio_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_ENABLE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpio_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_DISABLE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpio_is_enabled(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_IS_ENABLED, cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPIO_RSP_IS_ENABLED(cmd, *en); -+ -+ return 0; -+} -+ -+int dpio_reset(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_RESET, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpio_set_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ struct dpio_irq_cfg *irq_cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_SET_IRQ, -+ cmd_flags, -+ token); -+ DPIO_CMD_SET_IRQ(cmd, irq_index, irq_cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpio_get_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ int *type, -+ struct dpio_irq_cfg *irq_cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_IRQ, -+ cmd_flags, -+ token); -+ DPIO_CMD_GET_IRQ(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPIO_RSP_GET_IRQ(cmd, *type, irq_cfg); -+ -+ return 0; -+} -+ -+int dpio_set_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_SET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ DPIO_CMD_SET_IRQ_ENABLE(cmd, irq_index, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpio_get_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ DPIO_CMD_GET_IRQ_ENABLE(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPIO_RSP_GET_IRQ_ENABLE(cmd, *en); -+ -+ return 0; -+} -+ -+int dpio_set_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t mask) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_SET_IRQ_MASK, -+ cmd_flags, -+ token); -+ DPIO_CMD_SET_IRQ_MASK(cmd, irq_index, mask); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpio_get_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *mask) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_IRQ_MASK, -+ cmd_flags, -+ token); -+ DPIO_CMD_GET_IRQ_MASK(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPIO_RSP_GET_IRQ_MASK(cmd, *mask); -+ -+ return 0; -+} -+ -+int dpio_get_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *status) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_IRQ_STATUS, -+ cmd_flags, -+ token); -+ DPIO_CMD_GET_IRQ_STATUS(cmd, irq_index, *status); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPIO_RSP_GET_IRQ_STATUS(cmd, *status); -+ -+ return 0; -+} -+ -+int dpio_clear_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t status) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLEAR_IRQ_STATUS, -+ cmd_flags, -+ token); -+ DPIO_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpio_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpio_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_ATTR, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPIO_RSP_GET_ATTR(cmd, attr); -+ -+ return 0; -+} -+ -+int dpio_set_stashing_destination(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t sdest) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_SET_STASHING_DEST, -+ cmd_flags, -+ token); -+ DPIO_CMD_SET_STASHING_DEST(cmd, sdest); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpio_get_stashing_destination(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t *sdest) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_STASHING_DEST, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPIO_RSP_GET_STASHING_DEST(cmd, *sdest); -+ -+ return 0; -+} -+ -+int dpio_add_static_dequeue_channel(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int dpcon_id, -+ uint8_t *channel_index) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_ADD_STATIC_DEQUEUE_CHANNEL, -+ cmd_flags, -+ token); -+ DPIO_CMD_ADD_STATIC_DEQUEUE_CHANNEL(cmd, dpcon_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPIO_RSP_ADD_STATIC_DEQUEUE_CHANNEL(cmd, *channel_index); -+ -+ return 0; -+} -+ -+int dpio_remove_static_dequeue_channel(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int dpcon_id) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header( -+ DPIO_CMDID_REMOVE_STATIC_DEQUEUE_CHANNEL, -+ cmd_flags, -+ token); -+ DPIO_CMD_REMOVE_STATIC_DEQUEUE_CHANNEL(cmd, dpcon_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/dpio_service.c -@@ -0,0 +1,801 @@ -+/* Copyright 2014 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include -+#include "fsl_qbman_portal.h" -+#include "../../include/mc.h" -+#include "../../include/fsl_dpaa2_io.h" -+#include "fsl_dpio.h" -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dpio-drv.h" -+#include "qbman_debug.h" -+ -+#define UNIMPLEMENTED() pr_err("FOO: %s unimplemented!\n", __func__) -+ -+#define MAGIC_SERVICE 0xabcd9876 -+#define MAGIC_OBJECT 0x1234fedc -+ -+struct dpaa2_io { -+ /* If MAGIC_SERVICE, this is a group of objects, use the 'service' part -+ * of the union. If MAGIC_OBJECT, use the 'object' part of the union. If -+ * it's neither, something got corrupted. This is mainly to satisfy -+ * dpaa2_io_from_registration(), which dereferences a caller- -+ * instantiated struct and so warrants a bug-checking step - hence the -+ * magic rather than a boolean. -+ */ -+ unsigned int magic; -+ atomic_t refs; -+ union { -+ struct dpaa2_io_service { -+ spinlock_t lock; -+ struct list_head list; -+ /* for targeted dpaa2_io selection */ -+ struct dpaa2_io *objects_by_cpu[NR_CPUS]; -+ cpumask_t cpus_notifications; -+ cpumask_t cpus_stashing; -+ int has_nonaffine; -+ /* slight hack. record the special case of the -+ * "default service", because that's the case where we -+ * need to avoid a kfree() ... */ -+ int is_defservice; -+ } service; -+ struct dpaa2_io_object { -+ struct dpaa2_io_desc dpio_desc; -+ struct qbman_swp_desc swp_desc; -+ struct qbman_swp *swp; -+ /* If the object is part of a service, this is it (and -+ * 'node' is linked into the service's list) */ -+ struct dpaa2_io *service; -+ struct list_head node; -+ /* Interrupt mask, as used with -+ * qbman_swp_interrupt_[gs]et_vanish(). This isn't -+ * locked, because the higher layer is driving all -+ * "ingress" processing. */ -+ uint32_t irq_mask; -+ /* As part of simplifying assumptions, we provide an -+ * irq-safe lock for each type of DPIO operation that -+ * isn't innately lockless. The selection algorithms -+ * (which are simplified) require this, whereas -+ * eventually adherence to cpu-affinity will presumably -+ * relax the locking requirements. */ -+ spinlock_t lock_mgmt_cmd; -+ spinlock_t lock_notifications; -+ struct list_head notifications; -+ } object; -+ }; -+}; -+ -+struct dpaa2_io_store { -+ unsigned int max; -+ dma_addr_t paddr; -+ struct dpaa2_dq *vaddr; -+ void *alloced_addr; /* the actual return from kmalloc as it may -+ be adjusted for alignment purposes */ -+ unsigned int idx; /* position of the next-to-be-returned entry */ -+ struct qbman_swp *swp; /* portal used to issue VDQCR */ -+ struct device *dev; /* device used for DMA mapping */ -+}; -+ -+static struct dpaa2_io def_serv; -+ -+/**********************/ -+/* Internal functions */ -+/**********************/ -+ -+static void service_init(struct dpaa2_io *d, int is_defservice) -+{ -+ struct dpaa2_io_service *s = &d->service; -+ -+ d->magic = MAGIC_SERVICE; -+ atomic_set(&d->refs, 1); -+ spin_lock_init(&s->lock); -+ INIT_LIST_HEAD(&s->list); -+ cpumask_clear(&s->cpus_notifications); -+ cpumask_clear(&s->cpus_stashing); -+ s->has_nonaffine = 0; -+ s->is_defservice = is_defservice; -+} -+ -+/* Selection algorithms, stupid ones at that. These are to handle the case where -+ * the given dpaa2_io is a service, by choosing the non-service dpaa2_io within -+ * it to use. -+ */ -+static struct dpaa2_io *_service_select_by_cpu_slow(struct dpaa2_io_service *ss, -+ int cpu) -+{ -+ struct dpaa2_io *o; -+ unsigned long irqflags; -+ -+ spin_lock_irqsave(&ss->lock, irqflags); -+ /* TODO: this is about the dumbest and slowest selection algorithm you -+ * could imagine. (We're looking for something working first, and -+ * something efficient second...) -+ */ -+ list_for_each_entry(o, &ss->list, object.node) -+ if (o->object.dpio_desc.cpu == cpu) -+ goto found; -+ -+ /* No joy. Try the first nonaffine portal (bleurgh) */ -+ if (ss->has_nonaffine) -+ list_for_each_entry(o, &ss->list, object.node) -+ if (!o->object.dpio_desc.stash_affinity) -+ goto found; -+ -+ /* No joy. Try the first object. Told you it was horrible. */ -+ if (!list_empty(&ss->list)) -+ o = list_entry(ss->list.next, struct dpaa2_io, object.node); -+ else -+ o = NULL; -+ -+found: -+ spin_unlock_irqrestore(&ss->lock, irqflags); -+ return o; -+} -+ -+static struct dpaa2_io *service_select_by_cpu(struct dpaa2_io *d, int cpu) -+{ -+ struct dpaa2_io_service *ss; -+ unsigned long irqflags; -+ -+ if (!d) -+ d = &def_serv; -+ else if (d->magic == MAGIC_OBJECT) -+ return d; -+ BUG_ON(d->magic != MAGIC_SERVICE); -+ -+ ss = &d->service; -+ -+ /* If cpu==-1, choose the current cpu, with no guarantees about -+ * potentially being migrated away. -+ */ -+ if (unlikely(cpu < 0)) { -+ spin_lock_irqsave(&ss->lock, irqflags); -+ cpu = smp_processor_id(); -+ spin_unlock_irqrestore(&ss->lock, irqflags); -+ -+ return _service_select_by_cpu_slow(ss, cpu); -+ } -+ -+ /* If a specific cpu was requested, pick it up immediately */ -+ return ss->objects_by_cpu[cpu]; -+} -+ -+static inline struct dpaa2_io *service_select_any(struct dpaa2_io *d) -+{ -+ struct dpaa2_io_service *ss; -+ struct dpaa2_io *o; -+ unsigned long irqflags; -+ -+ if (!d) -+ d = &def_serv; -+ else if (d->magic == MAGIC_OBJECT) -+ return d; -+ BUG_ON(d->magic != MAGIC_SERVICE); -+ -+ /* -+ * Lock the service, looking for the first DPIO object in the list, -+ * ignore everything else about that DPIO, and choose it to do the -+ * operation! As a post-selection step, move the DPIO to the end of -+ * the list. It should improve load-balancing a little, although it -+ * might also incur a performance hit, given that the lock is *global* -+ * and this may be called on the fast-path... -+ */ -+ ss = &d->service; -+ spin_lock_irqsave(&ss->lock, irqflags); -+ if (!list_empty(&ss->list)) { -+ o = list_entry(ss->list.next, struct dpaa2_io, object.node); -+ list_del(&o->object.node); -+ list_add_tail(&o->object.node, &ss->list); -+ } else -+ o = NULL; -+ spin_unlock_irqrestore(&ss->lock, irqflags); -+ return o; -+} -+ -+/* If the context is not preemptible, select the service affine to the -+ * current cpu. Otherwise, "select any". -+ */ -+static inline struct dpaa2_io *_service_select(struct dpaa2_io *d) -+{ -+ struct dpaa2_io *temp = d; -+ -+ if (likely(!preemptible())) { -+ d = service_select_by_cpu(d, smp_processor_id()); -+ if (likely(d)) -+ return d; -+ } -+ return service_select_any(temp); -+} -+ -+/**********************/ -+/* Exported functions */ -+/**********************/ -+ -+struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc) -+{ -+ struct dpaa2_io *ret = kmalloc(sizeof(*ret), GFP_KERNEL); -+ struct dpaa2_io_object *o = &ret->object; -+ -+ if (!ret) -+ return NULL; -+ ret->magic = MAGIC_OBJECT; -+ atomic_set(&ret->refs, 1); -+ o->dpio_desc = *desc; -+ o->swp_desc.cena_bar = o->dpio_desc.regs_cena; -+ o->swp_desc.cinh_bar = o->dpio_desc.regs_cinh; -+ o->swp_desc.qman_version = o->dpio_desc.qman_version; -+ o->swp = qbman_swp_init(&o->swp_desc); -+ o->service = NULL; -+ if (!o->swp) { -+ kfree(ret); -+ return NULL; -+ } -+ INIT_LIST_HEAD(&o->node); -+ spin_lock_init(&o->lock_mgmt_cmd); -+ spin_lock_init(&o->lock_notifications); -+ INIT_LIST_HEAD(&o->notifications); -+ if (!o->dpio_desc.has_irq) -+ qbman_swp_interrupt_set_vanish(o->swp, 0xffffffff); -+ else { -+ /* For now only enable DQRR interrupts */ -+ qbman_swp_interrupt_set_trigger(o->swp, -+ QBMAN_SWP_INTERRUPT_DQRI); -+ } -+ qbman_swp_interrupt_clear_status(o->swp, 0xffffffff); -+ if (o->dpio_desc.receives_notifications) -+ qbman_swp_push_set(o->swp, 0, 1); -+ return ret; -+} -+EXPORT_SYMBOL(dpaa2_io_create); -+ -+struct dpaa2_io *dpaa2_io_create_service(void) -+{ -+ struct dpaa2_io *ret = kmalloc(sizeof(*ret), GFP_KERNEL); -+ -+ if (ret) -+ service_init(ret, 0); -+ return ret; -+} -+EXPORT_SYMBOL(dpaa2_io_create_service); -+ -+struct dpaa2_io *dpaa2_io_default_service(void) -+{ -+ atomic_inc(&def_serv.refs); -+ return &def_serv; -+} -+EXPORT_SYMBOL(dpaa2_io_default_service); -+ -+void dpaa2_io_down(struct dpaa2_io *d) -+{ -+ if (!atomic_dec_and_test(&d->refs)) -+ return; -+ if (d->magic == MAGIC_SERVICE) { -+ BUG_ON(!list_empty(&d->service.list)); -+ if (d->service.is_defservice) -+ /* avoid the kfree()! */ -+ return; -+ } else { -+ BUG_ON(d->magic != MAGIC_OBJECT); -+ BUG_ON(d->object.service); -+ BUG_ON(!list_empty(&d->object.notifications)); -+ } -+ kfree(d); -+} -+EXPORT_SYMBOL(dpaa2_io_down); -+ -+int dpaa2_io_service_add(struct dpaa2_io *s, struct dpaa2_io *o) -+{ -+ struct dpaa2_io_service *ss = &s->service; -+ struct dpaa2_io_object *oo = &o->object; -+ int res = -EINVAL; -+ -+ if ((s->magic != MAGIC_SERVICE) || (o->magic != MAGIC_OBJECT)) -+ return res; -+ atomic_inc(&o->refs); -+ atomic_inc(&s->refs); -+ spin_lock(&ss->lock); -+ /* 'obj' must not already be associated with a service */ -+ if (!oo->service) { -+ oo->service = s; -+ list_add(&oo->node, &ss->list); -+ if (oo->dpio_desc.receives_notifications) { -+ cpumask_set_cpu(oo->dpio_desc.cpu, -+ &ss->cpus_notifications); -+ /* Update the fast-access array */ -+ ss->objects_by_cpu[oo->dpio_desc.cpu] = -+ container_of(oo, struct dpaa2_io, object); -+ } -+ if (oo->dpio_desc.stash_affinity) -+ cpumask_set_cpu(oo->dpio_desc.cpu, -+ &ss->cpus_stashing); -+ if (!oo->dpio_desc.stash_affinity) -+ ss->has_nonaffine = 1; -+ /* success */ -+ res = 0; -+ } -+ spin_unlock(&ss->lock); -+ if (res) { -+ dpaa2_io_down(s); -+ dpaa2_io_down(o); -+ } -+ return res; -+} -+EXPORT_SYMBOL(dpaa2_io_service_add); -+ -+int dpaa2_io_get_descriptor(struct dpaa2_io *obj, struct dpaa2_io_desc *desc) -+{ -+ if (obj->magic == MAGIC_SERVICE) -+ return -EINVAL; -+ BUG_ON(obj->magic != MAGIC_OBJECT); -+ *desc = obj->object.dpio_desc; -+ return 0; -+} -+EXPORT_SYMBOL(dpaa2_io_get_descriptor); -+ -+#define DPAA_POLL_MAX 32 -+ -+int dpaa2_io_poll(struct dpaa2_io *obj) -+{ -+ const struct dpaa2_dq *dq; -+ struct qbman_swp *swp; -+ int max = 0; -+ -+ if (obj->magic != MAGIC_OBJECT) -+ return -EINVAL; -+ swp = obj->object.swp; -+ dq = qbman_swp_dqrr_next(swp); -+ while (dq) { -+ if (qbman_result_is_SCN(dq)) { -+ struct dpaa2_io_notification_ctx *ctx; -+ uint64_t q64; -+ -+ q64 = qbman_result_SCN_ctx(dq); -+ ctx = (void *)q64; -+ ctx->cb(ctx); -+ } else -+ pr_crit("Unrecognised/ignored DQRR entry\n"); -+ qbman_swp_dqrr_consume(swp, dq); -+ ++max; -+ if (max > DPAA_POLL_MAX) -+ return 0; -+ dq = qbman_swp_dqrr_next(swp); -+ } -+ return 0; -+} -+EXPORT_SYMBOL(dpaa2_io_poll); -+ -+int dpaa2_io_irq(struct dpaa2_io *obj) -+{ -+ struct qbman_swp *swp; -+ uint32_t status; -+ -+ if (obj->magic != MAGIC_OBJECT) -+ return -EINVAL; -+ swp = obj->object.swp; -+ status = qbman_swp_interrupt_read_status(swp); -+ if (!status) -+ return IRQ_NONE; -+ dpaa2_io_poll(obj); -+ qbman_swp_interrupt_clear_status(swp, status); -+ qbman_swp_interrupt_set_inhibit(swp, 0); -+ return IRQ_HANDLED; -+} -+EXPORT_SYMBOL(dpaa2_io_irq); -+ -+int dpaa2_io_pause_poll(struct dpaa2_io *obj) -+{ -+ UNIMPLEMENTED(); -+ return -EINVAL; -+} -+EXPORT_SYMBOL(dpaa2_io_pause_poll); -+ -+int dpaa2_io_resume_poll(struct dpaa2_io *obj) -+{ -+ UNIMPLEMENTED(); -+ return -EINVAL; -+} -+EXPORT_SYMBOL(dpaa2_io_resume_poll); -+ -+void dpaa2_io_service_notifications(struct dpaa2_io *s, cpumask_t *mask) -+{ -+ struct dpaa2_io_service *ss = &s->service; -+ -+ BUG_ON(s->magic != MAGIC_SERVICE); -+ cpumask_copy(mask, &ss->cpus_notifications); -+} -+EXPORT_SYMBOL(dpaa2_io_service_notifications); -+ -+void dpaa2_io_service_stashing(struct dpaa2_io *s, cpumask_t *mask) -+{ -+ struct dpaa2_io_service *ss = &s->service; -+ -+ BUG_ON(s->magic != MAGIC_SERVICE); -+ cpumask_copy(mask, &ss->cpus_stashing); -+} -+EXPORT_SYMBOL(dpaa2_io_service_stashing); -+ -+int dpaa2_io_service_has_nonaffine(struct dpaa2_io *s) -+{ -+ struct dpaa2_io_service *ss = &s->service; -+ -+ BUG_ON(s->magic != MAGIC_SERVICE); -+ return ss->has_nonaffine; -+} -+EXPORT_SYMBOL(dpaa2_io_service_has_nonaffine); -+ -+int dpaa2_io_service_register(struct dpaa2_io *d, -+ struct dpaa2_io_notification_ctx *ctx) -+{ -+ unsigned long irqflags; -+ -+ d = service_select_by_cpu(d, ctx->desired_cpu); -+ if (!d) -+ return -ENODEV; -+ ctx->dpio_id = d->object.dpio_desc.dpio_id; -+ ctx->qman64 = (uint64_t)ctx; -+ ctx->dpio_private = d; -+ spin_lock_irqsave(&d->object.lock_notifications, irqflags); -+ list_add(&ctx->node, &d->object.notifications); -+ spin_unlock_irqrestore(&d->object.lock_notifications, irqflags); -+ if (ctx->is_cdan) -+ /* Enable the generation of CDAN notifications */ -+ qbman_swp_CDAN_set_context_enable(d->object.swp, -+ (uint16_t)ctx->id, -+ ctx->qman64); -+ return 0; -+} -+EXPORT_SYMBOL(dpaa2_io_service_register); -+ -+int dpaa2_io_service_deregister(struct dpaa2_io *service, -+ struct dpaa2_io_notification_ctx *ctx) -+{ -+ struct dpaa2_io *d = ctx->dpio_private; -+ unsigned long irqflags; -+ -+ if (!service) -+ service = &def_serv; -+ BUG_ON((service != d) && (service != d->object.service)); -+ if (ctx->is_cdan) -+ qbman_swp_CDAN_disable(d->object.swp, -+ (uint16_t)ctx->id); -+ spin_lock_irqsave(&d->object.lock_notifications, irqflags); -+ list_del(&ctx->node); -+ spin_unlock_irqrestore(&d->object.lock_notifications, irqflags); -+ return 0; -+} -+EXPORT_SYMBOL(dpaa2_io_service_deregister); -+ -+int dpaa2_io_service_rearm(struct dpaa2_io *d, -+ struct dpaa2_io_notification_ctx *ctx) -+{ -+ unsigned long irqflags; -+ int err; -+ -+ d = _service_select(d); -+ if (!d) -+ return -ENODEV; -+ spin_lock_irqsave(&d->object.lock_mgmt_cmd, irqflags); -+ if (ctx->is_cdan) -+ err = qbman_swp_CDAN_enable(d->object.swp, (uint16_t)ctx->id); -+ else -+ err = qbman_swp_fq_schedule(d->object.swp, ctx->id); -+ spin_unlock_irqrestore(&d->object.lock_mgmt_cmd, irqflags); -+ return err; -+} -+EXPORT_SYMBOL(dpaa2_io_service_rearm); -+ -+int dpaa2_io_from_registration(struct dpaa2_io_notification_ctx *ctx, -+ struct dpaa2_io **io) -+{ -+ struct dpaa2_io_notification_ctx *tmp; -+ struct dpaa2_io *d = ctx->dpio_private; -+ unsigned long irqflags; -+ int ret = 0; -+ -+ BUG_ON(d->magic != MAGIC_OBJECT); -+ /* Iterate the notifications associated with 'd' looking for a match. If -+ * not, we've been passed an unregistered ctx! */ -+ spin_lock_irqsave(&d->object.lock_notifications, irqflags); -+ list_for_each_entry(tmp, &d->object.notifications, node) -+ if (tmp == ctx) -+ goto found; -+ ret = -EINVAL; -+found: -+ spin_unlock_irqrestore(&d->object.lock_notifications, irqflags); -+ if (!ret) { -+ atomic_inc(&d->refs); -+ *io = d; -+ } -+ return ret; -+} -+EXPORT_SYMBOL(dpaa2_io_from_registration); -+ -+int dpaa2_io_service_get_persistent(struct dpaa2_io *service, int cpu, -+ struct dpaa2_io **ret) -+{ -+ if (cpu == -1) -+ *ret = service_select_any(service); -+ else -+ *ret = service_select_by_cpu(service, cpu); -+ if (*ret) { -+ atomic_inc(&(*ret)->refs); -+ return 0; -+ } -+ return -ENODEV; -+} -+EXPORT_SYMBOL(dpaa2_io_service_get_persistent); -+ -+int dpaa2_io_service_pull_fq(struct dpaa2_io *d, uint32_t fqid, -+ struct dpaa2_io_store *s) -+{ -+ struct qbman_pull_desc pd; -+ int err; -+ -+ qbman_pull_desc_clear(&pd); -+ qbman_pull_desc_set_storage(&pd, s->vaddr, s->paddr, 1); -+ qbman_pull_desc_set_numframes(&pd, (uint8_t)s->max); -+ qbman_pull_desc_set_fq(&pd, fqid); -+ d = _service_select(d); -+ if (!d) -+ return -ENODEV; -+ s->swp = d->object.swp; -+ err = qbman_swp_pull(d->object.swp, &pd); -+ if (err) -+ s->swp = NULL; -+ return err; -+} -+EXPORT_SYMBOL(dpaa2_io_service_pull_fq); -+ -+int dpaa2_io_service_pull_channel(struct dpaa2_io *d, uint32_t channelid, -+ struct dpaa2_io_store *s) -+{ -+ struct qbman_pull_desc pd; -+ int err; -+ -+ qbman_pull_desc_clear(&pd); -+ qbman_pull_desc_set_storage(&pd, s->vaddr, s->paddr, 1); -+ qbman_pull_desc_set_numframes(&pd, (uint8_t)s->max); -+ qbman_pull_desc_set_channel(&pd, channelid, qbman_pull_type_prio); -+ d = _service_select(d); -+ if (!d) -+ return -ENODEV; -+ s->swp = d->object.swp; -+ err = qbman_swp_pull(d->object.swp, &pd); -+ if (err) -+ s->swp = NULL; -+ return err; -+} -+EXPORT_SYMBOL(dpaa2_io_service_pull_channel); -+ -+int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d, -+ uint32_t fqid, -+ const struct dpaa2_fd *fd) -+{ -+ struct qbman_eq_desc ed; -+ -+ d = _service_select(d); -+ if (!d) -+ return -ENODEV; -+ qbman_eq_desc_clear(&ed); -+ qbman_eq_desc_set_no_orp(&ed, 0); -+ qbman_eq_desc_set_fq(&ed, fqid); -+ return qbman_swp_enqueue(d->object.swp, &ed, -+ (const struct qbman_fd *)fd); -+} -+EXPORT_SYMBOL(dpaa2_io_service_enqueue_fq); -+ -+int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d, -+ uint32_t qdid, uint8_t prio, uint16_t qdbin, -+ const struct dpaa2_fd *fd) -+{ -+ struct qbman_eq_desc ed; -+ -+ d = _service_select(d); -+ if (!d) -+ return -ENODEV; -+ qbman_eq_desc_clear(&ed); -+ qbman_eq_desc_set_no_orp(&ed, 0); -+ qbman_eq_desc_set_qd(&ed, qdid, qdbin, prio); -+ return qbman_swp_enqueue(d->object.swp, &ed, -+ (const struct qbman_fd *)fd); -+} -+EXPORT_SYMBOL(dpaa2_io_service_enqueue_qd); -+ -+int dpaa2_io_service_release(struct dpaa2_io *d, -+ uint32_t bpid, -+ const uint64_t *buffers, -+ unsigned int num_buffers) -+{ -+ struct qbman_release_desc rd; -+ -+ d = _service_select(d); -+ if (!d) -+ return -ENODEV; -+ qbman_release_desc_clear(&rd); -+ qbman_release_desc_set_bpid(&rd, bpid); -+ return qbman_swp_release(d->object.swp, &rd, buffers, num_buffers); -+} -+EXPORT_SYMBOL(dpaa2_io_service_release); -+ -+int dpaa2_io_service_acquire(struct dpaa2_io *d, -+ uint32_t bpid, -+ uint64_t *buffers, -+ unsigned int num_buffers) -+{ -+ unsigned long irqflags; -+ int err; -+ -+ d = _service_select(d); -+ if (!d) -+ return -ENODEV; -+ spin_lock_irqsave(&d->object.lock_mgmt_cmd, irqflags); -+ err = qbman_swp_acquire(d->object.swp, bpid, buffers, num_buffers); -+ spin_unlock_irqrestore(&d->object.lock_mgmt_cmd, irqflags); -+ return err; -+} -+EXPORT_SYMBOL(dpaa2_io_service_acquire); -+ -+struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames, -+ struct device *dev) -+{ -+ struct dpaa2_io_store *ret = kmalloc(sizeof(*ret), GFP_KERNEL); -+ size_t size; -+ -+ BUG_ON(!max_frames || (max_frames > 16)); -+ if (!ret) -+ return NULL; -+ ret->max = max_frames; -+ size = max_frames * sizeof(struct dpaa2_dq) + 64; -+ ret->alloced_addr = kmalloc(size, GFP_KERNEL); -+ if (!ret->alloced_addr) { -+ kfree(ret); -+ return NULL; -+ } -+ ret->vaddr = PTR_ALIGN(ret->alloced_addr, 64); -+ ret->paddr = dma_map_single(dev, ret->vaddr, -+ sizeof(struct dpaa2_dq) * max_frames, -+ DMA_FROM_DEVICE); -+ if (dma_mapping_error(dev, ret->paddr)) { -+ kfree(ret->alloced_addr); -+ kfree(ret); -+ return NULL; -+ } -+ ret->idx = 0; -+ ret->dev = dev; -+ return ret; -+} -+EXPORT_SYMBOL(dpaa2_io_store_create); -+ -+void dpaa2_io_store_destroy(struct dpaa2_io_store *s) -+{ -+ dma_unmap_single(s->dev, s->paddr, sizeof(struct dpaa2_dq) * s->max, -+ DMA_FROM_DEVICE); -+ kfree(s->alloced_addr); -+ kfree(s); -+} -+EXPORT_SYMBOL(dpaa2_io_store_destroy); -+ -+struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last) -+{ -+ int match; -+ struct dpaa2_dq *ret = &s->vaddr[s->idx]; -+ -+ match = qbman_result_has_new_result(s->swp, ret); -+ if (!match) { -+ *is_last = 0; -+ return NULL; -+ } -+ BUG_ON(!qbman_result_is_DQ(ret)); -+ s->idx++; -+ if (dpaa2_dq_is_pull_complete(ret)) { -+ *is_last = 1; -+ s->idx = 0; -+ /* If we get an empty dequeue result to terminate a zero-results -+ * vdqcr, return NULL to the caller rather than expecting him to -+ * check non-NULL results every time. */ -+ if (!(dpaa2_dq_flags(ret) & DPAA2_DQ_STAT_VALIDFRAME)) -+ ret = NULL; -+ } else -+ *is_last = 0; -+ return ret; -+} -+EXPORT_SYMBOL(dpaa2_io_store_next); -+ -+#ifdef CONFIG_FSL_QBMAN_DEBUG -+int dpaa2_io_query_fq_count(struct dpaa2_io *d, uint32_t fqid, -+ uint32_t *fcnt, uint32_t *bcnt) -+{ -+ struct qbman_attr state; -+ struct qbman_swp *swp; -+ unsigned long irqflags; -+ int ret; -+ -+ d = service_select_any(d); -+ if (!d) -+ return -ENODEV; -+ -+ swp = d->object.swp; -+ spin_lock_irqsave(&d->object.lock_mgmt_cmd, irqflags); -+ ret = qbman_fq_query_state(swp, fqid, &state); -+ spin_unlock_irqrestore(&d->object.lock_mgmt_cmd, irqflags); -+ if (ret) -+ return ret; -+ *fcnt = qbman_fq_state_frame_count(&state); -+ *bcnt = qbman_fq_state_byte_count(&state); -+ -+ return 0; -+} -+EXPORT_SYMBOL(dpaa2_io_query_fq_count); -+ -+int dpaa2_io_query_bp_count(struct dpaa2_io *d, uint32_t bpid, -+ uint32_t *num) -+{ -+ struct qbman_attr state; -+ struct qbman_swp *swp; -+ unsigned long irqflags; -+ int ret; -+ -+ d = service_select_any(d); -+ if (!d) -+ return -ENODEV; -+ -+ swp = d->object.swp; -+ spin_lock_irqsave(&d->object.lock_mgmt_cmd, irqflags); -+ ret = qbman_bp_query(swp, bpid, &state); -+ spin_unlock_irqrestore(&d->object.lock_mgmt_cmd, irqflags); -+ if (ret) -+ return ret; -+ *num = qbman_bp_info_num_free_bufs(&state); -+ return 0; -+} -+EXPORT_SYMBOL(dpaa2_io_query_bp_count); -+ -+#endif -+ -+/* module init/exit hooks called from dpio-drv.c. These are declared in -+ * dpio-drv.h. -+ */ -+int dpaa2_io_service_driver_init(void) -+{ -+ service_init(&def_serv, 1); -+ return 0; -+} -+ -+void dpaa2_io_service_driver_exit(void) -+{ -+ if (atomic_read(&def_serv.refs) != 1) -+ pr_err("default DPIO service leaves dangling DPIO objects!\n"); -+} ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/fsl_dpio.h -@@ -0,0 +1,460 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef __FSL_DPIO_H -+#define __FSL_DPIO_H -+ -+/* Data Path I/O Portal API -+ * Contains initialization APIs and runtime control APIs for DPIO -+ */ -+ -+struct fsl_mc_io; -+ -+/** -+ * dpio_open() - Open a control session for the specified object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @dpio_id: DPIO unique ID -+ * @token: Returned token; use in subsequent API calls -+ * -+ * This function can be used to open a control session for an -+ * already created object; an object may have been declared in -+ * the DPL or by calling the dpio_create() function. -+ * This function returns a unique authentication token, -+ * associated with the specific object ID and the specific MC -+ * portal; this token must be used in all subsequent commands for -+ * this specific object. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_open(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ int dpio_id, -+ uint16_t *token); -+ -+/** -+ * dpio_close() - Close the control session of the object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_close(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * enum dpio_channel_mode - DPIO notification channel mode -+ * @DPIO_NO_CHANNEL: No support for notification channel -+ * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a -+ * dedicated channel in the DPIO; user should point the queue's -+ * destination in the relevant interface to this DPIO -+ */ -+enum dpio_channel_mode { -+ DPIO_NO_CHANNEL = 0, -+ DPIO_LOCAL_CHANNEL = 1, -+}; -+ -+/** -+ * struct dpio_cfg - Structure representing DPIO configuration -+ * @channel_mode: Notification channel mode -+ * @num_priorities: Number of priorities for the notification channel (1-8); -+ * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' -+ */ -+struct dpio_cfg { -+ enum dpio_channel_mode channel_mode; -+ uint8_t num_priorities; -+}; -+ -+/** -+ * dpio_create() - Create the DPIO object. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @cfg: Configuration structure -+ * @token: Returned token; use in subsequent API calls -+ * -+ * Create the DPIO object, allocate required resources and -+ * perform required initialization. -+ * -+ * The object can be created either by declaring it in the -+ * DPL file, or by calling this function. -+ * -+ * This function returns a unique authentication token, -+ * associated with the specific object ID and the specific MC -+ * portal; this token must be used in all subsequent calls to -+ * this specific object. For objects that are created using the -+ * DPL file, call dpio_open() function to get an authentication -+ * token first. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_create(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ const struct dpio_cfg *cfg, -+ uint16_t *token); -+ -+/** -+ * dpio_destroy() - Destroy the DPIO object and release all its resources. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * -+ * Return: '0' on Success; Error code otherwise -+ */ -+int dpio_destroy(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpio_enable() - Enable the DPIO, allow I/O portal operations. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * -+ * Return: '0' on Success; Error code otherwise -+ */ -+int dpio_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpio_disable() - Disable the DPIO, stop any I/O portal operation. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * -+ * Return: '0' on Success; Error code otherwise -+ */ -+int dpio_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpio_is_enabled() - Check if the DPIO is enabled. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @en: Returns '1' if object is enabled; '0' otherwise -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_is_enabled(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en); -+ -+/** -+ * dpio_reset() - Reset the DPIO, returns the object to initial state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_reset(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpio_set_stashing_destination() - Set the stashing destination. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @sdest: stashing destination value -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_set_stashing_destination(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t sdest); -+ -+/** -+ * dpio_get_stashing_destination() - Get the stashing destination.. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @sdest: Returns the stashing destination value -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_get_stashing_destination(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t *sdest); -+ -+/** -+ * dpio_add_static_dequeue_channel() - Add a static dequeue channel. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @dpcon_id: DPCON object ID -+ * @channel_index: Returned channel index to be used in qbman API -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_add_static_dequeue_channel(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int dpcon_id, -+ uint8_t *channel_index); -+ -+/** -+ * dpio_remove_static_dequeue_channel() - Remove a static dequeue channel. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @dpcon_id: DPCON object ID -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_remove_static_dequeue_channel(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int dpcon_id); -+ -+/** -+ * DPIO IRQ Index and Events -+ */ -+ -+/** -+ * Irq software-portal index -+ */ -+#define DPIO_IRQ_SWP_INDEX 0 -+ -+/** -+ * struct dpio_irq_cfg - IRQ configuration -+ * @addr: Address that must be written to signal a message-based interrupt -+ * @val: Value to write into irq_addr address -+ * @irq_num: A user defined number associated with this IRQ -+ */ -+struct dpio_irq_cfg { -+ uint64_t addr; -+ uint32_t val; -+ int irq_num; -+}; -+ -+/** -+ * dpio_set_irq() - Set IRQ information for the DPIO to trigger an interrupt. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @irq_index: Identifies the interrupt index to configure -+ * @irq_cfg: IRQ configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_set_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ struct dpio_irq_cfg *irq_cfg); -+ -+/** -+ * dpio_get_irq() - Get IRQ information from the DPIO. -+ * -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @irq_index: The interrupt index to configure -+ * @type: Interrupt type: 0 represents message interrupt -+ * type (both irq_addr and irq_val are valid) -+ * @irq_cfg: IRQ attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_get_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ int *type, -+ struct dpio_irq_cfg *irq_cfg); -+ -+/** -+ * dpio_set_irq_enable() - Set overall interrupt state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @irq_index: The interrupt index to configure -+ * @en: Interrupt state - enable = 1, disable = 0 -+ * -+ * Allows GPP software to control when interrupts are generated. -+ * Each interrupt can have up to 32 causes. The enable/disable control's the -+ * overall interrupt state. if the interrupt is disabled no causes will cause -+ * an interrupt. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_set_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t en); -+ -+/** -+ * dpio_get_irq_enable() - Get overall interrupt state -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @irq_index: The interrupt index to configure -+ * @en: Returned interrupt state - enable = 1, disable = 0 -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_get_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t *en); -+ -+/** -+ * dpio_set_irq_mask() - Set interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @irq_index: The interrupt index to configure -+ * @mask: event mask to trigger interrupt; -+ * each bit: -+ * 0 = ignore event -+ * 1 = consider event for asserting IRQ -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_set_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t mask); -+ -+/** -+ * dpio_get_irq_mask() - Get interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @irq_index: The interrupt index to configure -+ * @mask: Returned event mask to trigger interrupt -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_get_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *mask); -+ -+/** -+ * dpio_get_irq_status() - Get the current status of any pending interrupts. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @irq_index: The interrupt index to configure -+ * @status: Returned interrupts status - one bit per cause: -+ * 0 = no interrupt pending -+ * 1 = interrupt pending -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_get_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *status); -+ -+/** -+ * dpio_clear_irq_status() - Clear a pending interrupt's status -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @irq_index: The interrupt index to configure -+ * @status: bits to clear (W1C) - one bit per cause: -+ * 0 = don't change -+ * 1 = clear status bit -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpio_clear_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t status); -+ -+/** -+ * struct dpio_attr - Structure representing DPIO attributes -+ * @id: DPIO object ID -+ * @version: DPIO version -+ * @qbman_portal_ce_offset: offset of the software portal cache-enabled area -+ * @qbman_portal_ci_offset: offset of the software portal cache-inhibited area -+ * @qbman_portal_id: Software portal ID -+ * @channel_mode: Notification channel mode -+ * @num_priorities: Number of priorities for the notification channel (1-8); -+ * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' -+ * @qbman_version: QBMAN version -+ */ -+struct dpio_attr { -+ int id; -+ /** -+ * struct version - DPIO version -+ * @major: DPIO major version -+ * @minor: DPIO minor version -+ */ -+ struct { -+ uint16_t major; -+ uint16_t minor; -+ } version; -+ uint64_t qbman_portal_ce_offset; -+ uint64_t qbman_portal_ci_offset; -+ uint16_t qbman_portal_id; -+ enum dpio_channel_mode channel_mode; -+ uint8_t num_priorities; -+ uint32_t qbman_version; -+}; -+ -+/** -+ * dpio_get_attributes() - Retrieve DPIO attributes -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPIO object -+ * @attr: Returned object's attributes -+ * -+ * Return: '0' on Success; Error code otherwise -+ */ -+int dpio_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpio_attr *attr); -+#endif /* __FSL_DPIO_H */ ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/fsl_dpio_cmd.h -@@ -0,0 +1,184 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef _FSL_DPIO_CMD_H -+#define _FSL_DPIO_CMD_H -+ -+/* DPIO Version */ -+#define DPIO_VER_MAJOR 3 -+#define DPIO_VER_MINOR 2 -+ -+/* Command IDs */ -+#define DPIO_CMDID_CLOSE 0x800 -+#define DPIO_CMDID_OPEN 0x803 -+#define DPIO_CMDID_CREATE 0x903 -+#define DPIO_CMDID_DESTROY 0x900 -+ -+#define DPIO_CMDID_ENABLE 0x002 -+#define DPIO_CMDID_DISABLE 0x003 -+#define DPIO_CMDID_GET_ATTR 0x004 -+#define DPIO_CMDID_RESET 0x005 -+#define DPIO_CMDID_IS_ENABLED 0x006 -+ -+#define DPIO_CMDID_SET_IRQ 0x010 -+#define DPIO_CMDID_GET_IRQ 0x011 -+#define DPIO_CMDID_SET_IRQ_ENABLE 0x012 -+#define DPIO_CMDID_GET_IRQ_ENABLE 0x013 -+#define DPIO_CMDID_SET_IRQ_MASK 0x014 -+#define DPIO_CMDID_GET_IRQ_MASK 0x015 -+#define DPIO_CMDID_GET_IRQ_STATUS 0x016 -+#define DPIO_CMDID_CLEAR_IRQ_STATUS 0x017 -+ -+#define DPIO_CMDID_SET_STASHING_DEST 0x120 -+#define DPIO_CMDID_GET_STASHING_DEST 0x121 -+#define DPIO_CMDID_ADD_STATIC_DEQUEUE_CHANNEL 0x122 -+#define DPIO_CMDID_REMOVE_STATIC_DEQUEUE_CHANNEL 0x123 -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_CMD_OPEN(cmd, dpio_id) \ -+ MC_CMD_OP(cmd, 0, 0, 32, int, dpio_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_CMD_CREATE(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 16, 2, enum dpio_channel_mode, \ -+ cfg->channel_mode);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->num_priorities);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_RSP_IS_ENABLED(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\ -+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\ -+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_CMD_GET_IRQ(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_RSP_GET_IRQ(cmd, type, irq_cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \ -+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \ -+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_CMD_GET_IRQ_ENABLE(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_RSP_GET_IRQ_ENABLE(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_CMD_GET_IRQ_MASK(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_RSP_GET_IRQ_MASK(cmd, mask) \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_RSP_GET_IRQ_STATUS(cmd, status) \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_RSP_GET_ATTR(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ -+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qbman_portal_id);\ -+ MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->num_priorities);\ -+ MC_RSP_OP(cmd, 0, 56, 4, enum dpio_channel_mode, attr->channel_mode);\ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->qbman_portal_ce_offset);\ -+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, attr->qbman_portal_ci_offset);\ -+ MC_RSP_OP(cmd, 3, 0, 16, uint16_t, attr->version.major);\ -+ MC_RSP_OP(cmd, 3, 16, 16, uint16_t, attr->version.minor);\ -+ MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_CMD_SET_STASHING_DEST(cmd, sdest) \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, sdest) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_RSP_GET_STASHING_DEST(cmd, sdest) \ -+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, sdest) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_CMD_ADD_STATIC_DEQUEUE_CHANNEL(cmd, dpcon_id) \ -+ MC_CMD_OP(cmd, 0, 0, 32, int, dpcon_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_RSP_ADD_STATIC_DEQUEUE_CHANNEL(cmd, channel_index) \ -+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, channel_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPIO_CMD_REMOVE_STATIC_DEQUEUE_CHANNEL(cmd, dpcon_id) \ -+ MC_CMD_OP(cmd, 0, 0, 32, int, dpcon_id) -+#endif /* _FSL_DPIO_CMD_H */ ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/fsl_qbman_base.h -@@ -0,0 +1,123 @@ -+/* Copyright (C) 2014 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef _FSL_QBMAN_BASE_H -+#define _FSL_QBMAN_BASE_H -+ -+/** -+ * struct qbman_block_desc - qbman block descriptor structure -+ * -+ * Descriptor for a QBMan instance on the SoC. On partitions/targets that do not -+ * control this QBMan instance, these values may simply be place-holders. The -+ * idea is simply that we be able to distinguish between them, eg. so that SWP -+ * descriptors can identify which QBMan instance they belong to. -+ */ -+struct qbman_block_desc { -+ void *ccsr_reg_bar; /* CCSR register map */ -+ int irq_rerr; /* Recoverable error interrupt line */ -+ int irq_nrerr; /* Non-recoverable error interrupt line */ -+}; -+ -+/** -+ * struct qbman_swp_desc - qbman software portal descriptor structure -+ * -+ * Descriptor for a QBMan software portal, expressed in terms that make sense to -+ * the user context. Ie. on MC, this information is likely to be true-physical, -+ * and instantiated statically at compile-time. On GPP, this information is -+ * likely to be obtained via "discovery" over a partition's "layerscape bus" -+ * (ie. in response to a MC portal command), and would take into account any -+ * virtualisation of the GPP user's address space and/or interrupt numbering. -+ */ -+struct qbman_swp_desc { -+ const struct qbman_block_desc *block; /* The QBMan instance */ -+ void *cena_bar; /* Cache-enabled portal register map */ -+ void *cinh_bar; /* Cache-inhibited portal register map */ -+ uint32_t qman_version; -+}; -+ -+/* Driver object for managing a QBMan portal */ -+struct qbman_swp; -+ -+/** -+ * struct qbman_fd - basci structure for qbman frame descriptor -+ * -+ * Place-holder for FDs, we represent it via the simplest form that we need for -+ * now. Different overlays may be needed to support different options, etc. (It -+ * is impractical to define One True Struct, because the resulting encoding -+ * routines (lots of read-modify-writes) would be worst-case performance whether -+ * or not circumstances required them.) -+ * -+ * Note, as with all data-structures exchanged between software and hardware (be -+ * they located in the portal register map or DMA'd to and from main-memory), -+ * the driver ensures that the caller of the driver API sees the data-structures -+ * in host-endianness. "struct qbman_fd" is no exception. The 32-bit words -+ * contained within this structure are represented in host-endianness, even if -+ * hardware always treats them as little-endian. As such, if any of these fields -+ * are interpreted in a binary (rather than numerical) fashion by hardware -+ * blocks (eg. accelerators), then the user should be careful. We illustrate -+ * with an example; -+ * -+ * Suppose the desired behaviour of an accelerator is controlled by the "frc" -+ * field of the FDs that are sent to it. Suppose also that the behaviour desired -+ * by the user corresponds to an "frc" value which is expressed as the literal -+ * sequence of bytes 0xfe, 0xed, 0xab, and 0xba. So "frc" should be the 32-bit -+ * value in which 0xfe is the first byte and 0xba is the last byte, and as -+ * hardware is little-endian, this amounts to a 32-bit "value" of 0xbaabedfe. If -+ * the software is little-endian also, this can simply be achieved by setting -+ * frc=0xbaabedfe. On the other hand, if software is big-endian, it should set -+ * frc=0xfeedabba! The best away of avoiding trouble with this sort of thing is -+ * to treat the 32-bit words as numerical values, in which the offset of a field -+ * from the beginning of the first byte (as required or generated by hardware) -+ * is numerically encoded by a left-shift (ie. by raising the field to a -+ * corresponding power of 2). Ie. in the current example, software could set -+ * "frc" in the following way, and it would work correctly on both little-endian -+ * and big-endian operation; -+ * fd.frc = (0xfe << 0) | (0xed << 8) | (0xab << 16) | (0xba << 24); -+ */ -+struct qbman_fd { -+ union { -+ uint32_t words[8]; -+ struct qbman_fd_simple { -+ uint32_t addr_lo; -+ uint32_t addr_hi; -+ uint32_t len; -+ /* offset in the MS 16 bits, BPID in the LS 16 bits */ -+ uint32_t bpid_offset; -+ uint32_t frc; /* frame context */ -+ /* "err", "va", "cbmt", "asal", [...] */ -+ uint32_t ctrl; -+ /* flow context */ -+ uint32_t flc_lo; -+ uint32_t flc_hi; -+ } simple; -+ }; -+}; -+ -+#endif /* !_FSL_QBMAN_BASE_H */ ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/fsl_qbman_portal.h -@@ -0,0 +1,753 @@ -+/* Copyright (C) 2014 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef _FSL_QBMAN_PORTAL_H -+#define _FSL_QBMAN_PORTAL_H -+ -+#include "fsl_qbman_base.h" -+ -+/** -+ * qbman_swp_init() - Create a functional object representing the given -+ * QBMan portal descriptor. -+ * @d: the given qbman swp descriptor -+ * -+ * Return qbman_swp portal object for success, NULL if the object cannot -+ * be created. -+ */ -+struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d); -+/** -+ * qbman_swp_finish() - Create and destroy a functional object representing -+ * the given QBMan portal descriptor. -+ * @p: the qbman_swp object to be destroyed. -+ * -+ */ -+void qbman_swp_finish(struct qbman_swp *p); -+ -+/** -+ * qbman_swp_get_desc() - Get the descriptor of the given portal object. -+ * @p: the given portal object. -+ * -+ * Return the descriptor for this portal. -+ */ -+const struct qbman_swp_desc *qbman_swp_get_desc(struct qbman_swp *p); -+ -+ /**************/ -+ /* Interrupts */ -+ /**************/ -+ -+/* See the QBMan driver API documentation for details on the interrupt -+ * mechanisms. */ -+#define QBMAN_SWP_INTERRUPT_EQRI ((uint32_t)0x00000001) -+#define QBMAN_SWP_INTERRUPT_EQDI ((uint32_t)0x00000002) -+#define QBMAN_SWP_INTERRUPT_DQRI ((uint32_t)0x00000004) -+#define QBMAN_SWP_INTERRUPT_RCRI ((uint32_t)0x00000008) -+#define QBMAN_SWP_INTERRUPT_RCDI ((uint32_t)0x00000010) -+#define QBMAN_SWP_INTERRUPT_VDCI ((uint32_t)0x00000020) -+ -+/** -+ * qbman_swp_interrupt_get_vanish() -+ * qbman_swp_interrupt_set_vanish() - Get/Set the data in software portal -+ * interrupt status disable register. -+ * @p: the given software portal object. -+ * @mask: The mask to set in SWP_IDSR register. -+ * -+ * Return the settings in SWP_ISDR register for Get function. -+ */ -+uint32_t qbman_swp_interrupt_get_vanish(struct qbman_swp *p); -+void qbman_swp_interrupt_set_vanish(struct qbman_swp *p, uint32_t mask); -+ -+/** -+ * qbman_swp_interrupt_read_status() -+ * qbman_swp_interrupt_clear_status() - Get/Set the data in software portal -+ * interrupt status register. -+ * @p: the given software portal object. -+ * @mask: The mask to set in SWP_ISR register. -+ * -+ * Return the settings in SWP_ISR register for Get function. -+ * -+ */ -+uint32_t qbman_swp_interrupt_read_status(struct qbman_swp *p); -+void qbman_swp_interrupt_clear_status(struct qbman_swp *p, uint32_t mask); -+ -+/** -+ * qbman_swp_interrupt_get_trigger() -+ * qbman_swp_interrupt_set_trigger() - Get/Set the data in software portal -+ * interrupt enable register. -+ * @p: the given software portal object. -+ * @mask: The mask to set in SWP_IER register. -+ * -+ * Return the settings in SWP_IER register for Get function. -+ */ -+uint32_t qbman_swp_interrupt_get_trigger(struct qbman_swp *p); -+void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, uint32_t mask); -+ -+/** -+ * qbman_swp_interrupt_get_inhibit() -+ * qbman_swp_interrupt_set_inhibit() - Set/Set the data in software portal -+ * interrupt inhibit register. -+ * @p: the given software portal object. -+ * @mask: The mask to set in SWP_IIR register. -+ * -+ * Return the settings in SWP_IIR register for Get function. -+ */ -+int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p); -+void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit); -+ -+ /************/ -+ /* Dequeues */ -+ /************/ -+ -+/* See the QBMan driver API documentation for details on the enqueue -+ * mechanisms. NB: the use of a 'dpaa2_' prefix for this type is because it is -+ * primarily used by the "DPIO" layer that sits above (and hides) the QBMan -+ * driver. The structure is defined in the DPIO interface, but to avoid circular -+ * dependencies we just pre/re-declare it here opaquely. */ -+struct dpaa2_dq; -+ -+/* ------------------- */ -+/* Push-mode dequeuing */ -+/* ------------------- */ -+ -+/** -+ * qbman_swp_push_get() - Get the push dequeue setup. -+ * @p: the software portal object. -+ * @channel_idx: the channel index to query. -+ * @enabled: returned boolean to show whether the push dequeue is enabled for -+ * the given channel. -+ */ -+void qbman_swp_push_get(struct qbman_swp *, uint8_t channel_idx, int *enabled); -+/** -+ * qbman_swp_push_set() - Enable or disable push dequeue. -+ * @p: the software portal object. -+ * @channel_idx: the channel index.. -+ * @enable: enable or disable push dequeue. -+ * -+ * The user of a portal can enable and disable push-mode dequeuing of up to 16 -+ * channels independently. It does not specify this toggling by channel IDs, but -+ * rather by specifying the index (from 0 to 15) that has been mapped to the -+ * desired channel. -+ */ -+void qbman_swp_push_set(struct qbman_swp *, uint8_t channel_idx, int enable); -+ -+/* ------------------- */ -+/* Pull-mode dequeuing */ -+/* ------------------- */ -+ -+/** -+ * struct qbman_pull_desc - the structure for pull dequeue descriptor -+ */ -+struct qbman_pull_desc { -+ uint32_t dont_manipulate_directly[6]; -+}; -+ -+enum qbman_pull_type_e { -+ /* dequeue with priority precedence, respect intra-class scheduling */ -+ qbman_pull_type_prio = 1, -+ /* dequeue with active FQ precedence, respect ICS */ -+ qbman_pull_type_active, -+ /* dequeue with active FQ precedence, no ICS */ -+ qbman_pull_type_active_noics -+}; -+ -+/** -+ * qbman_pull_desc_clear() - Clear the contents of a descriptor to -+ * default/starting state. -+ * @d: the pull dequeue descriptor to be cleared. -+ */ -+void qbman_pull_desc_clear(struct qbman_pull_desc *d); -+ -+/** -+ * qbman_pull_desc_set_storage()- Set the pull dequeue storage -+ * @d: the pull dequeue descriptor to be set. -+ * @storage: the pointer of the memory to store the dequeue result. -+ * @storage_phys: the physical address of the storage memory. -+ * @stash: to indicate whether write allocate is enabled. -+ * -+ * If not called, or if called with 'storage' as NULL, the result pull dequeues -+ * will produce results to DQRR. If 'storage' is non-NULL, then results are -+ * produced to the given memory location (using the physical/DMA address which -+ * the caller provides in 'storage_phys'), and 'stash' controls whether or not -+ * those writes to main-memory express a cache-warming attribute. -+ */ -+void qbman_pull_desc_set_storage(struct qbman_pull_desc *d, -+ struct dpaa2_dq *storage, -+ dma_addr_t storage_phys, -+ int stash); -+/** -+ * qbman_pull_desc_set_numframes() - Set the number of frames to be dequeued. -+ * @d: the pull dequeue descriptor to be set. -+ * @numframes: number of frames to be set, must be between 1 and 16, inclusive. -+ */ -+void qbman_pull_desc_set_numframes(struct qbman_pull_desc *, uint8_t numframes); -+ -+/** -+ * qbman_pull_desc_set_fq() - Set fqid from which the dequeue command dequeues. -+ * @fqid: the frame queue index of the given FQ. -+ * -+ * qbman_pull_desc_set_wq() - Set wqid from which the dequeue command dequeues. -+ * @wqid: composed of channel id and wqid within the channel. -+ * @dct: the dequeue command type. -+ * -+ * qbman_pull_desc_set_channel() - Set channelid from which the dequeue command -+ * dequeues. -+ * @chid: the channel id to be dequeued. -+ * @dct: the dequeue command type. -+ * -+ * Exactly one of the following descriptor "actions" should be set. (Calling any -+ * one of these will replace the effect of any prior call to one of these.) -+ * - pull dequeue from the given frame queue (FQ) -+ * - pull dequeue from any FQ in the given work queue (WQ) -+ * - pull dequeue from any FQ in any WQ in the given channel -+ */ -+void qbman_pull_desc_set_fq(struct qbman_pull_desc *, uint32_t fqid); -+void qbman_pull_desc_set_wq(struct qbman_pull_desc *, uint32_t wqid, -+ enum qbman_pull_type_e dct); -+void qbman_pull_desc_set_channel(struct qbman_pull_desc *, uint32_t chid, -+ enum qbman_pull_type_e dct); -+ -+/** -+ * qbman_swp_pull() - Issue the pull dequeue command -+ * @s: the software portal object. -+ * @d: the software portal descriptor which has been configured with -+ * the set of qbman_pull_desc_set_*() calls. -+ * -+ * Return 0 for success, and -EBUSY if the software portal is not ready -+ * to do pull dequeue. -+ */ -+int qbman_swp_pull(struct qbman_swp *, struct qbman_pull_desc *d); -+ -+/* -------------------------------- */ -+/* Polling DQRR for dequeue results */ -+/* -------------------------------- */ -+ -+/** -+ * qbman_swp_dqrr_next() - Get an valid DQRR entry. -+ * @s: the software portal object. -+ * -+ * Return NULL if there are no unconsumed DQRR entries. Return a DQRR entry -+ * only once, so repeated calls can return a sequence of DQRR entries, without -+ * requiring they be consumed immediately or in any particular order. -+ */ -+const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s); -+ -+/** -+ * qbman_swp_dqrr_consume() - Consume DQRR entries previously returned from -+ * qbman_swp_dqrr_next(). -+ * @s: the software portal object. -+ * @dq: the DQRR entry to be consumed. -+ */ -+void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq); -+ -+/* ------------------------------------------------- */ -+/* Polling user-provided storage for dequeue results */ -+/* ------------------------------------------------- */ -+/** -+ * qbman_result_has_new_result() - Check and get the dequeue response from the -+ * dq storage memory set in pull dequeue command -+ * @s: the software portal object. -+ * @dq: the dequeue result read from the memory. -+ * -+ * Only used for user-provided storage of dequeue results, not DQRR. For -+ * efficiency purposes, the driver will perform any required endianness -+ * conversion to ensure that the user's dequeue result storage is in host-endian -+ * format (whether or not that is the same as the little-endian format that -+ * hardware DMA'd to the user's storage). As such, once the user has called -+ * qbman_result_has_new_result() and been returned a valid dequeue result, -+ * they should not call it again on the same memory location (except of course -+ * if another dequeue command has been executed to produce a new result to that -+ * location). -+ * -+ * Return 1 for getting a valid dequeue result, or 0 for not getting a valid -+ * dequeue result. -+ */ -+int qbman_result_has_new_result(struct qbman_swp *, -+ const struct dpaa2_dq *); -+ -+/* -------------------------------------------------------- */ -+/* Parsing dequeue entries (DQRR and user-provided storage) */ -+/* -------------------------------------------------------- */ -+ -+/** -+ * qbman_result_is_DQ() - check the dequeue result is a dequeue response or not -+ * @dq: the dequeue result to be checked. -+ * -+ * DQRR entries may contain non-dequeue results, ie. notifications -+ */ -+int qbman_result_is_DQ(const struct dpaa2_dq *); -+ -+/** -+ * qbman_result_is_SCN() - Check the dequeue result is notification or not -+ * @dq: the dequeue result to be checked. -+ * -+ * All the non-dequeue results (FQDAN/CDAN/CSCN/...) are "state change -+ * notifications" of one type or another. Some APIs apply to all of them, of the -+ * form qbman_result_SCN_***(). -+ */ -+static inline int qbman_result_is_SCN(const struct dpaa2_dq *dq) -+{ -+ return !qbman_result_is_DQ(dq); -+} -+ -+/** -+ * Recognise different notification types, only required if the user allows for -+ * these to occur, and cares about them when they do. -+ */ -+int qbman_result_is_FQDAN(const struct dpaa2_dq *); -+ /* FQ Data Availability */ -+int qbman_result_is_CDAN(const struct dpaa2_dq *); -+ /* Channel Data Availability */ -+int qbman_result_is_CSCN(const struct dpaa2_dq *); -+ /* Congestion State Change */ -+int qbman_result_is_BPSCN(const struct dpaa2_dq *); -+ /* Buffer Pool State Change */ -+int qbman_result_is_CGCU(const struct dpaa2_dq *); -+ /* Congestion Group Count Update */ -+/* Frame queue state change notifications; (FQDAN in theory counts too as it -+ * leaves a FQ parked, but it is primarily a data availability notification) */ -+int qbman_result_is_FQRN(const struct dpaa2_dq *); /* Retirement */ -+int qbman_result_is_FQRNI(const struct dpaa2_dq *); -+ /* Retirement Immediate */ -+int qbman_result_is_FQPN(const struct dpaa2_dq *); /* Park */ -+ -+/* NB: for parsing dequeue results (when "is_DQ" is TRUE), use the higher-layer -+ * dpaa2_dq_*() functions. */ -+ -+/* State-change notifications (FQDAN/CDAN/CSCN/...). */ -+/** -+ * qbman_result_SCN_state() - Get the state field in State-change notification -+ */ -+uint8_t qbman_result_SCN_state(const struct dpaa2_dq *); -+/** -+ * qbman_result_SCN_rid() - Get the resource id in State-change notification -+ */ -+uint32_t qbman_result_SCN_rid(const struct dpaa2_dq *); -+/** -+ * qbman_result_SCN_ctx() - Get the context data in State-change notification -+ */ -+uint64_t qbman_result_SCN_ctx(const struct dpaa2_dq *); -+/** -+ * qbman_result_SCN_state_in_mem() - Get the state field in State-change -+ * notification which is written to memory instead of DQRR. -+ */ -+uint8_t qbman_result_SCN_state_in_mem(const struct dpaa2_dq *); -+/** -+ * qbman_result_SCN_rid_in_mem() - Get the resource id in State-change -+ * notification which is written to memory instead of DQRR. -+ */ -+uint32_t qbman_result_SCN_rid_in_mem(const struct dpaa2_dq *); -+ -+/* Type-specific "resource IDs". Mainly for illustration purposes, though it -+ * also gives the appropriate type widths. */ -+#define qbman_result_FQDAN_fqid(dq) qbman_result_SCN_rid(dq) -+#define qbman_result_FQRN_fqid(dq) qbman_result_SCN_rid(dq) -+#define qbman_result_FQRNI_fqid(dq) qbman_result_SCN_rid(dq) -+#define qbman_result_FQPN_fqid(dq) qbman_result_SCN_rid(dq) -+#define qbman_result_CDAN_cid(dq) ((uint16_t)qbman_result_SCN_rid(dq)) -+#define qbman_result_CSCN_cgid(dq) ((uint16_t)qbman_result_SCN_rid(dq)) -+ -+/** -+ * qbman_result_bpscn_bpid() - Get the bpid from BPSCN -+ * -+ * Return the buffer pool id. -+ */ -+uint16_t qbman_result_bpscn_bpid(const struct dpaa2_dq *); -+/** -+ * qbman_result_bpscn_has_free_bufs() - Check whether there are free -+ * buffers in the pool from BPSCN. -+ * -+ * Return the number of free buffers. -+ */ -+int qbman_result_bpscn_has_free_bufs(const struct dpaa2_dq *); -+/** -+ * qbman_result_bpscn_is_depleted() - Check BPSCN to see whether the -+ * buffer pool is depleted. -+ * -+ * Return the status of buffer pool depletion. -+ */ -+int qbman_result_bpscn_is_depleted(const struct dpaa2_dq *); -+/** -+ * qbman_result_bpscn_is_surplus() - Check BPSCN to see whether the buffer -+ * pool is surplus or not. -+ * -+ * Return the status of buffer pool surplus. -+ */ -+int qbman_result_bpscn_is_surplus(const struct dpaa2_dq *); -+/** -+ * qbman_result_bpscn_ctx() - Get the BPSCN CTX from BPSCN message -+ * -+ * Return the BPSCN context. -+ */ -+uint64_t qbman_result_bpscn_ctx(const struct dpaa2_dq *); -+ -+/* Parsing CGCU */ -+/** -+ * qbman_result_cgcu_cgid() - Check CGCU resouce id, i.e. cgid -+ * -+ * Return the CGCU resource id. -+ */ -+uint16_t qbman_result_cgcu_cgid(const struct dpaa2_dq *); -+/** -+ * qbman_result_cgcu_icnt() - Get the I_CNT from CGCU -+ * -+ * Return instantaneous count in the CGCU notification. -+ */ -+uint64_t qbman_result_cgcu_icnt(const struct dpaa2_dq *); -+ -+ /************/ -+ /* Enqueues */ -+ /************/ -+/** -+ * struct qbman_eq_desc - structure of enqueue descriptor -+ */ -+struct qbman_eq_desc { -+ uint32_t dont_manipulate_directly[8]; -+}; -+ -+/** -+ * struct qbman_eq_response - structure of enqueue response -+ */ -+struct qbman_eq_response { -+ uint32_t dont_manipulate_directly[16]; -+}; -+ -+/** -+ * qbman_eq_desc_clear() - Clear the contents of a descriptor to -+ * default/starting state. -+ */ -+void qbman_eq_desc_clear(struct qbman_eq_desc *); -+ -+/* Exactly one of the following descriptor "actions" should be set. (Calling -+ * any one of these will replace the effect of any prior call to one of these.) -+ * - enqueue without order-restoration -+ * - enqueue with order-restoration -+ * - fill a hole in the order-restoration sequence, without any enqueue -+ * - advance NESN (Next Expected Sequence Number), without any enqueue -+ * 'respond_success' indicates whether an enqueue response should be DMA'd -+ * after success (otherwise a response is DMA'd only after failure). -+ * 'incomplete' indicates that other fragments of the same 'seqnum' are yet to -+ * be enqueued. -+ */ -+/** -+ * qbman_eq_desc_set_no_orp() - Set enqueue descriptor without orp -+ * @d: the enqueue descriptor. -+ * @response_success: 1 = enqueue with response always; 0 = enqueue with -+ * rejections returned on a FQ. -+ */ -+void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success); -+ -+/** -+ * qbman_eq_desc_set_orp() - Set order-resotration in the enqueue descriptor -+ * @d: the enqueue descriptor. -+ * @response_success: 1 = enqueue with response always; 0 = enqueue with -+ * rejections returned on a FQ. -+ * @opr_id: the order point record id. -+ * @seqnum: the order restoration sequence number. -+ * @incomplete: indiates whether this is the last fragments using the same -+ * sequeue number. -+ */ -+void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success, -+ uint32_t opr_id, uint32_t seqnum, int incomplete); -+ -+/** -+ * qbman_eq_desc_set_orp_hole() - fill a hole in the order-restoration sequence -+ * without any enqueue -+ * @d: the enqueue descriptor. -+ * @opr_id: the order point record id. -+ * @seqnum: the order restoration sequence number. -+ */ -+void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, uint32_t opr_id, -+ uint32_t seqnum); -+ -+/** -+ * qbman_eq_desc_set_orp_nesn() - advance NESN (Next Expected Sequence Number) -+ * without any enqueue -+ * @d: the enqueue descriptor. -+ * @opr_id: the order point record id. -+ * @seqnum: the order restoration sequence number. -+ */ -+void qbman_eq_desc_set_orp_nesn(struct qbman_eq_desc *d, uint32_t opr_id, -+ uint32_t seqnum); -+ -+/** -+ * qbman_eq_desc_set_response() - Set the enqueue response info. -+ * @d: the enqueue descriptor -+ * @storage_phys: the physical address of the enqueue response in memory. -+ * @stash: indicate that the write allocation enabled or not. -+ * -+ * In the case where an enqueue response is DMA'd, this determines where that -+ * response should go. (The physical/DMA address is given for hardware's -+ * benefit, but software should interpret it as a "struct qbman_eq_response" -+ * data structure.) 'stash' controls whether or not the write to main-memory -+ * expresses a cache-warming attribute. -+ */ -+void qbman_eq_desc_set_response(struct qbman_eq_desc *d, -+ dma_addr_t storage_phys, -+ int stash); -+/** -+ * qbman_eq_desc_set_token() - Set token for the enqueue command -+ * @d: the enqueue descriptor -+ * @token: the token to be set. -+ * -+ * token is the value that shows up in an enqueue response that can be used to -+ * detect when the results have been published. The easiest technique is to zero -+ * result "storage" before issuing an enqueue, and use any non-zero 'token' -+ * value. -+ */ -+void qbman_eq_desc_set_token(struct qbman_eq_desc *d, uint8_t token); -+ -+/** -+ * qbman_eq_desc_set_fq() -+ * qbman_eq_desc_set_qd() - Set eithe FQ or Queuing Destination for the enqueue -+ * command. -+ * @d: the enqueue descriptor -+ * @fqid: the id of the frame queue to be enqueued. -+ * @qdid: the id of the queuing destination to be enqueued. -+ * @qd_bin: the queuing destination bin -+ * @qd_prio: the queuing destination priority. -+ * -+ * Exactly one of the following descriptor "targets" should be set. (Calling any -+ * one of these will replace the effect of any prior call to one of these.) -+ * - enqueue to a frame queue -+ * - enqueue to a queuing destination -+ * Note, that none of these will have any affect if the "action" type has been -+ * set to "orp_hole" or "orp_nesn". -+ */ -+void qbman_eq_desc_set_fq(struct qbman_eq_desc *, uint32_t fqid); -+void qbman_eq_desc_set_qd(struct qbman_eq_desc *, uint32_t qdid, -+ uint32_t qd_bin, uint32_t qd_prio); -+ -+/** -+ * qbman_eq_desc_set_eqdi() - enable/disable EQDI interrupt -+ * @d: the enqueue descriptor -+ * @enable: boolean to enable/disable EQDI -+ * -+ * Determines whether or not the portal's EQDI interrupt source should be -+ * asserted after the enqueue command is completed. -+ */ -+void qbman_eq_desc_set_eqdi(struct qbman_eq_desc *, int enable); -+ -+/** -+ * qbman_eq_desc_set_dca() - Set DCA mode in the enqueue command. -+ * @d: the enqueue descriptor. -+ * @enable: enabled/disable DCA mode. -+ * @dqrr_idx: DCAP_CI, the DCAP consumer index. -+ * @park: determine the whether park the FQ or not -+ * -+ * Determines whether or not a portal DQRR entry should be consumed once the -+ * enqueue command is completed. (And if so, and the DQRR entry corresponds -+ * to a held-active (order-preserving) FQ, whether the FQ should be parked -+ * instead of being rescheduled.) -+ */ -+void qbman_eq_desc_set_dca(struct qbman_eq_desc *, int enable, -+ uint32_t dqrr_idx, int park); -+ -+/** -+ * qbman_swp_enqueue() - Issue an enqueue command. -+ * @s: the software portal used for enqueue. -+ * @d: the enqueue descriptor. -+ * @fd: the frame descriptor to be enqueued. -+ * -+ * Please note that 'fd' should only be NULL if the "action" of the -+ * descriptor is "orp_hole" or "orp_nesn". -+ * -+ * Return 0 for successful enqueue, -EBUSY if the EQCR is not ready. -+ */ -+int qbman_swp_enqueue(struct qbman_swp *, const struct qbman_eq_desc *, -+ const struct qbman_fd *fd); -+ -+/** -+ * qbman_swp_enqueue_thresh() - Set the threshold for EQRI interrupt. -+ * -+ * An EQRI interrupt can be generated when the fill-level of EQCR falls below -+ * the 'thresh' value set here. Setting thresh==0 (the default) disables. -+ */ -+int qbman_swp_enqueue_thresh(struct qbman_swp *, unsigned int thresh); -+ -+ /*******************/ -+ /* Buffer releases */ -+ /*******************/ -+/** -+ * struct qbman_release_desc - The structure for buffer release descriptor -+ */ -+struct qbman_release_desc { -+ uint32_t dont_manipulate_directly[1]; -+}; -+ -+/** -+ * qbman_release_desc_clear() - Clear the contents of a descriptor to -+ * default/starting state. -+ */ -+void qbman_release_desc_clear(struct qbman_release_desc *); -+ -+/** -+ * qbman_release_desc_set_bpid() - Set the ID of the buffer pool to release to -+ */ -+void qbman_release_desc_set_bpid(struct qbman_release_desc *, uint32_t bpid); -+ -+/** -+ * qbman_release_desc_set_rcdi() - Determines whether or not the portal's RCDI -+ * interrupt source should be asserted after the release command is completed. -+ */ -+void qbman_release_desc_set_rcdi(struct qbman_release_desc *, int enable); -+ -+/** -+ * qbman_swp_release() - Issue a buffer release command. -+ * @s: the software portal object. -+ * @d: the release descriptor. -+ * @buffers: a pointer pointing to the buffer address to be released. -+ * @num_buffers: number of buffers to be released, must be less than 8. -+ * -+ * Return 0 for success, -EBUSY if the release command ring is not ready. -+ */ -+int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d, -+ const uint64_t *buffers, unsigned int num_buffers); -+ -+ /*******************/ -+ /* Buffer acquires */ -+ /*******************/ -+ -+/** -+ * qbman_swp_acquire() - Issue a buffer acquire command. -+ * @s: the software portal object. -+ * @bpid: the buffer pool index. -+ * @buffers: a pointer pointing to the acquired buffer address|es. -+ * @num_buffers: number of buffers to be acquired, must be less than 8. -+ * -+ * Return 0 for success, or negative error code if the acquire command -+ * fails. -+ */ -+int qbman_swp_acquire(struct qbman_swp *, uint32_t bpid, uint64_t *buffers, -+ unsigned int num_buffers); -+ -+ /*****************/ -+ /* FQ management */ -+ /*****************/ -+ -+/** -+ * qbman_swp_fq_schedule() - Move the fq to the scheduled state. -+ * @s: the software portal object. -+ * @fqid: the index of frame queue to be scheduled. -+ * -+ * There are a couple of different ways that a FQ can end up parked state, -+ * This schedules it. -+ * -+ * Return 0 for success, or negative error code for failure. -+ */ -+int qbman_swp_fq_schedule(struct qbman_swp *s, uint32_t fqid); -+ -+/** -+ * qbman_swp_fq_force() - Force the FQ to fully scheduled state. -+ * @s: the software portal object. -+ * @fqid: the index of frame queue to be forced. -+ * -+ * Force eligible will force a tentatively-scheduled FQ to be fully-scheduled -+ * and thus be available for selection by any channel-dequeuing behaviour (push -+ * or pull). If the FQ is subsequently "dequeued" from the channel and is still -+ * empty at the time this happens, the resulting dq_entry will have no FD. -+ * (qbman_result_DQ_fd() will return NULL.) -+ * -+ * Return 0 for success, or negative error code for failure. -+ */ -+int qbman_swp_fq_force(struct qbman_swp *s, uint32_t fqid); -+ -+/** -+ * qbman_swp_fq_xon() -+ * qbman_swp_fq_xoff() - XON/XOFF the frame queue. -+ * @s: the software portal object. -+ * @fqid: the index of frame queue. -+ * -+ * These functions change the FQ flow-control stuff between XON/XOFF. (The -+ * default is XON.) This setting doesn't affect enqueues to the FQ, just -+ * dequeues. XOFF FQs will remain in the tenatively-scheduled state, even when -+ * non-empty, meaning they won't be selected for scheduled dequeuing. If a FQ is -+ * changed to XOFF after it had already become truly-scheduled to a channel, and -+ * a pull dequeue of that channel occurs that selects that FQ for dequeuing, -+ * then the resulting dq_entry will have no FD. (qbman_result_DQ_fd() will -+ * return NULL.) -+ * -+ * Return 0 for success, or negative error code for failure. -+ */ -+int qbman_swp_fq_xon(struct qbman_swp *s, uint32_t fqid); -+int qbman_swp_fq_xoff(struct qbman_swp *s, uint32_t fqid); -+ -+ /**********************/ -+ /* Channel management */ -+ /**********************/ -+ -+/* If the user has been allocated a channel object that is going to generate -+ * CDANs to another channel, then these functions will be necessary. -+ * CDAN-enabled channels only generate a single CDAN notification, after which -+ * it they need to be reenabled before they'll generate another. (The idea is -+ * that pull dequeuing will occur in reaction to the CDAN, followed by a -+ * reenable step.) Each function generates a distinct command to hardware, so a -+ * combination function is provided if the user wishes to modify the "context" -+ * (which shows up in each CDAN message) each time they reenable, as a single -+ * command to hardware. */ -+/** -+ * qbman_swp_CDAN_set_context() - Set CDAN context -+ * @s: the software portal object. -+ * @channelid: the channel index. -+ * @ctx: the context to be set in CDAN. -+ * -+ * Return 0 for success, or negative error code for failure. -+ */ -+int qbman_swp_CDAN_set_context(struct qbman_swp *, uint16_t channelid, -+ uint64_t ctx); -+ -+/** -+ * qbman_swp_CDAN_enable() - Enable CDAN for the channel. -+ * @s: the software portal object. -+ * @channelid: the index of the channel to generate CDAN. -+ * -+ * Return 0 for success, or negative error code for failure. -+ */ -+int qbman_swp_CDAN_enable(struct qbman_swp *, uint16_t channelid); -+ -+/** -+ * qbman_swp_CDAN_disable() - disable CDAN for the channel. -+ * @s: the software portal object. -+ * @channelid: the index of the channel to generate CDAN. -+ * -+ * Return 0 for success, or negative error code for failure. -+ */ -+int qbman_swp_CDAN_disable(struct qbman_swp *, uint16_t channelid); -+ -+/** -+ * qbman_swp_CDAN_set_context_enable() - Set CDAN contest and enable CDAN -+ * @s: the software portal object. -+ * @channelid: the index of the channel to generate CDAN. -+ * @ctx: the context set in CDAN. -+ * -+ * Return 0 for success, or negative error code for failure. -+ */ -+int qbman_swp_CDAN_set_context_enable(struct qbman_swp *, uint16_t channelid, -+ uint64_t ctx); -+ -+#endif /* !_FSL_QBMAN_PORTAL_H */ ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/qbman_debug.c -@@ -0,0 +1,846 @@ -+/* Copyright (C) 2015 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "qbman_portal.h" -+#include "qbman_debug.h" -+#include "fsl_qbman_portal.h" -+ -+/* QBMan portal management command code */ -+#define QBMAN_BP_QUERY 0x32 -+#define QBMAN_FQ_QUERY 0x44 -+#define QBMAN_FQ_QUERY_NP 0x45 -+#define QBMAN_CGR_QUERY 0x51 -+#define QBMAN_WRED_QUERY 0x54 -+#define QBMAN_CGR_STAT_QUERY 0x55 -+#define QBMAN_CGR_STAT_QUERY_CLR 0x56 -+ -+enum qbman_attr_usage_e { -+ qbman_attr_usage_fq, -+ qbman_attr_usage_bpool, -+ qbman_attr_usage_cgr, -+}; -+ -+struct int_qbman_attr { -+ uint32_t words[32]; -+ enum qbman_attr_usage_e usage; -+}; -+ -+#define attr_type_set(a, e) \ -+{ \ -+ struct qbman_attr *__attr = a; \ -+ enum qbman_attr_usage_e __usage = e; \ -+ ((struct int_qbman_attr *)__attr)->usage = __usage; \ -+} -+ -+#define ATTR32(d) (&(d)->dont_manipulate_directly[0]) -+#define ATTR32_1(d) (&(d)->dont_manipulate_directly[16]) -+ -+static struct qb_attr_code code_bp_bpid = QB_CODE(0, 16, 16); -+static struct qb_attr_code code_bp_bdi = QB_CODE(1, 16, 1); -+static struct qb_attr_code code_bp_va = QB_CODE(1, 17, 1); -+static struct qb_attr_code code_bp_wae = QB_CODE(1, 18, 1); -+static struct qb_attr_code code_bp_swdet = QB_CODE(4, 0, 16); -+static struct qb_attr_code code_bp_swdxt = QB_CODE(4, 16, 16); -+static struct qb_attr_code code_bp_hwdet = QB_CODE(5, 0, 16); -+static struct qb_attr_code code_bp_hwdxt = QB_CODE(5, 16, 16); -+static struct qb_attr_code code_bp_swset = QB_CODE(6, 0, 16); -+static struct qb_attr_code code_bp_swsxt = QB_CODE(6, 16, 16); -+static struct qb_attr_code code_bp_vbpid = QB_CODE(7, 0, 14); -+static struct qb_attr_code code_bp_icid = QB_CODE(7, 16, 15); -+static struct qb_attr_code code_bp_pl = QB_CODE(7, 31, 1); -+static struct qb_attr_code code_bp_bpscn_addr_lo = QB_CODE(8, 0, 32); -+static struct qb_attr_code code_bp_bpscn_addr_hi = QB_CODE(9, 0, 32); -+static struct qb_attr_code code_bp_bpscn_ctx_lo = QB_CODE(10, 0, 32); -+static struct qb_attr_code code_bp_bpscn_ctx_hi = QB_CODE(11, 0, 32); -+static struct qb_attr_code code_bp_hw_targ = QB_CODE(12, 0, 16); -+static struct qb_attr_code code_bp_state = QB_CODE(1, 24, 3); -+static struct qb_attr_code code_bp_fill = QB_CODE(2, 0, 32); -+static struct qb_attr_code code_bp_hdptr = QB_CODE(3, 0, 32); -+static struct qb_attr_code code_bp_sdcnt = QB_CODE(13, 0, 8); -+static struct qb_attr_code code_bp_hdcnt = QB_CODE(13, 1, 8); -+static struct qb_attr_code code_bp_sscnt = QB_CODE(13, 2, 8); -+ -+void qbman_bp_attr_clear(struct qbman_attr *a) -+{ -+ memset(a, 0, sizeof(*a)); -+ attr_type_set(a, qbman_attr_usage_bpool); -+} -+ -+int qbman_bp_query(struct qbman_swp *s, uint32_t bpid, -+ struct qbman_attr *a) -+{ -+ uint32_t *p; -+ uint32_t verb, rslt; -+ uint32_t *attr = ATTR32(a); -+ -+ qbman_bp_attr_clear(a); -+ -+ /* Start the management command */ -+ p = qbman_swp_mc_start(s); -+ if (!p) -+ return -EBUSY; -+ -+ /* Encode the caller-provided attributes */ -+ qb_attr_code_encode(&code_bp_bpid, p, bpid); -+ -+ /* Complete the management command */ -+ p = qbman_swp_mc_complete(s, p, p[0] | QBMAN_BP_QUERY); -+ -+ /* Decode the outcome */ -+ verb = qb_attr_code_decode(&code_generic_verb, p); -+ rslt = qb_attr_code_decode(&code_generic_rslt, p); -+ BUG_ON(verb != QBMAN_BP_QUERY); -+ -+ /* Determine success or failure */ -+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) { -+ pr_err("Query of BPID 0x%x failed, code=0x%02x\n", bpid, rslt); -+ return -EIO; -+ } -+ -+ /* For the query, word[0] of the result contains only the -+ * verb/rslt fields, so skip word[0]. -+ */ -+ word_copy(&attr[1], &p[1], 15); -+ return 0; -+} -+ -+void qbman_bp_attr_get_bdi(struct qbman_attr *a, int *bdi, int *va, int *wae) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ *bdi = !!qb_attr_code_decode(&code_bp_bdi, p); -+ *va = !!qb_attr_code_decode(&code_bp_va, p); -+ *wae = !!qb_attr_code_decode(&code_bp_wae, p); -+} -+ -+static uint32_t qbman_bp_thresh_to_value(uint32_t val) -+{ -+ return (val & 0xff) << ((val & 0xf00) >> 8); -+} -+ -+void qbman_bp_attr_get_swdet(struct qbman_attr *a, uint32_t *swdet) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ *swdet = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swdet, -+ p)); -+} -+void qbman_bp_attr_get_swdxt(struct qbman_attr *a, uint32_t *swdxt) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ *swdxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swdxt, -+ p)); -+} -+void qbman_bp_attr_get_hwdet(struct qbman_attr *a, uint32_t *hwdet) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ *hwdet = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_hwdet, -+ p)); -+} -+void qbman_bp_attr_get_hwdxt(struct qbman_attr *a, uint32_t *hwdxt) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ *hwdxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_hwdxt, -+ p)); -+} -+ -+void qbman_bp_attr_get_swset(struct qbman_attr *a, uint32_t *swset) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ *swset = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swset, -+ p)); -+} -+ -+void qbman_bp_attr_get_swsxt(struct qbman_attr *a, uint32_t *swsxt) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ *swsxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swsxt, -+ p)); -+} -+ -+void qbman_bp_attr_get_vbpid(struct qbman_attr *a, uint32_t *vbpid) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ *vbpid = qb_attr_code_decode(&code_bp_vbpid, p); -+} -+ -+void qbman_bp_attr_get_icid(struct qbman_attr *a, uint32_t *icid, int *pl) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ *icid = qb_attr_code_decode(&code_bp_icid, p); -+ *pl = !!qb_attr_code_decode(&code_bp_pl, p); -+} -+ -+void qbman_bp_attr_get_bpscn_addr(struct qbman_attr *a, uint64_t *bpscn_addr) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ *bpscn_addr = ((uint64_t)qb_attr_code_decode(&code_bp_bpscn_addr_hi, -+ p) << 32) | -+ (uint64_t)qb_attr_code_decode(&code_bp_bpscn_addr_lo, -+ p); -+} -+ -+void qbman_bp_attr_get_bpscn_ctx(struct qbman_attr *a, uint64_t *bpscn_ctx) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ *bpscn_ctx = ((uint64_t)qb_attr_code_decode(&code_bp_bpscn_ctx_hi, p) -+ << 32) | -+ (uint64_t)qb_attr_code_decode(&code_bp_bpscn_ctx_lo, -+ p); -+} -+ -+void qbman_bp_attr_get_hw_targ(struct qbman_attr *a, uint32_t *hw_targ) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ *hw_targ = qb_attr_code_decode(&code_bp_hw_targ, p); -+} -+ -+int qbman_bp_info_has_free_bufs(struct qbman_attr *a) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ return !(int)(qb_attr_code_decode(&code_bp_state, p) & 0x1); -+} -+ -+int qbman_bp_info_is_depleted(struct qbman_attr *a) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ return (int)(qb_attr_code_decode(&code_bp_state, p) & 0x2); -+} -+ -+int qbman_bp_info_is_surplus(struct qbman_attr *a) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ return (int)(qb_attr_code_decode(&code_bp_state, p) & 0x4); -+} -+ -+uint32_t qbman_bp_info_num_free_bufs(struct qbman_attr *a) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ return qb_attr_code_decode(&code_bp_fill, p); -+} -+ -+uint32_t qbman_bp_info_hdptr(struct qbman_attr *a) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ return qb_attr_code_decode(&code_bp_hdptr, p); -+} -+ -+uint32_t qbman_bp_info_sdcnt(struct qbman_attr *a) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ return qb_attr_code_decode(&code_bp_sdcnt, p); -+} -+ -+uint32_t qbman_bp_info_hdcnt(struct qbman_attr *a) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ return qb_attr_code_decode(&code_bp_hdcnt, p); -+} -+ -+uint32_t qbman_bp_info_sscnt(struct qbman_attr *a) -+{ -+ uint32_t *p = ATTR32(a); -+ -+ return qb_attr_code_decode(&code_bp_sscnt, p); -+} -+ -+static struct qb_attr_code code_fq_fqid = QB_CODE(1, 0, 24); -+static struct qb_attr_code code_fq_cgrid = QB_CODE(2, 16, 16); -+static struct qb_attr_code code_fq_destwq = QB_CODE(3, 0, 15); -+static struct qb_attr_code code_fq_fqctrl = QB_CODE(3, 24, 8); -+static struct qb_attr_code code_fq_icscred = QB_CODE(4, 0, 15); -+static struct qb_attr_code code_fq_tdthresh = QB_CODE(4, 16, 13); -+static struct qb_attr_code code_fq_oa_len = QB_CODE(5, 0, 12); -+static struct qb_attr_code code_fq_oa_ics = QB_CODE(5, 14, 1); -+static struct qb_attr_code code_fq_oa_cgr = QB_CODE(5, 15, 1); -+static struct qb_attr_code code_fq_mctl_bdi = QB_CODE(5, 24, 1); -+static struct qb_attr_code code_fq_mctl_ff = QB_CODE(5, 25, 1); -+static struct qb_attr_code code_fq_mctl_va = QB_CODE(5, 26, 1); -+static struct qb_attr_code code_fq_mctl_ps = QB_CODE(5, 27, 1); -+static struct qb_attr_code code_fq_ctx_lower32 = QB_CODE(6, 0, 32); -+static struct qb_attr_code code_fq_ctx_upper32 = QB_CODE(7, 0, 32); -+static struct qb_attr_code code_fq_icid = QB_CODE(8, 0, 15); -+static struct qb_attr_code code_fq_pl = QB_CODE(8, 15, 1); -+static struct qb_attr_code code_fq_vfqid = QB_CODE(9, 0, 24); -+static struct qb_attr_code code_fq_erfqid = QB_CODE(10, 0, 24); -+ -+void qbman_fq_attr_clear(struct qbman_attr *a) -+{ -+ memset(a, 0, sizeof(*a)); -+ attr_type_set(a, qbman_attr_usage_fq); -+} -+ -+/* FQ query function for programmable fields */ -+int qbman_fq_query(struct qbman_swp *s, uint32_t fqid, struct qbman_attr *desc) -+{ -+ uint32_t *p; -+ uint32_t verb, rslt; -+ uint32_t *d = ATTR32(desc); -+ -+ qbman_fq_attr_clear(desc); -+ -+ p = qbman_swp_mc_start(s); -+ if (!p) -+ return -EBUSY; -+ qb_attr_code_encode(&code_fq_fqid, p, fqid); -+ p = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY); -+ -+ /* Decode the outcome */ -+ verb = qb_attr_code_decode(&code_generic_verb, p); -+ rslt = qb_attr_code_decode(&code_generic_rslt, p); -+ BUG_ON(verb != QBMAN_FQ_QUERY); -+ -+ /* Determine success or failure */ -+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) { -+ pr_err("Query of FQID 0x%x failed, code=0x%02x\n", -+ fqid, rslt); -+ return -EIO; -+ } -+ /* For the configure, word[0] of the command contains only the WE-mask. -+ * For the query, word[0] of the result contains only the verb/rslt -+ * fields. Skip word[0] in the latter case. */ -+ word_copy(&d[1], &p[1], 15); -+ return 0; -+} -+ -+void qbman_fq_attr_get_fqctrl(struct qbman_attr *d, uint32_t *fqctrl) -+{ -+ uint32_t *p = ATTR32(d); -+ -+ *fqctrl = qb_attr_code_decode(&code_fq_fqctrl, p); -+} -+ -+void qbman_fq_attr_get_cgrid(struct qbman_attr *d, uint32_t *cgrid) -+{ -+ uint32_t *p = ATTR32(d); -+ -+ *cgrid = qb_attr_code_decode(&code_fq_cgrid, p); -+} -+ -+void qbman_fq_attr_get_destwq(struct qbman_attr *d, uint32_t *destwq) -+{ -+ uint32_t *p = ATTR32(d); -+ -+ *destwq = qb_attr_code_decode(&code_fq_destwq, p); -+} -+ -+void qbman_fq_attr_get_icscred(struct qbman_attr *d, uint32_t *icscred) -+{ -+ uint32_t *p = ATTR32(d); -+ -+ *icscred = qb_attr_code_decode(&code_fq_icscred, p); -+} -+ -+static struct qb_attr_code code_tdthresh_exp = QB_CODE(0, 0, 5); -+static struct qb_attr_code code_tdthresh_mant = QB_CODE(0, 5, 8); -+static uint32_t qbman_thresh_to_value(uint32_t val) -+{ -+ uint32_t m, e; -+ -+ m = qb_attr_code_decode(&code_tdthresh_mant, &val); -+ e = qb_attr_code_decode(&code_tdthresh_exp, &val); -+ return m << e; -+} -+ -+void qbman_fq_attr_get_tdthresh(struct qbman_attr *d, uint32_t *tdthresh) -+{ -+ uint32_t *p = ATTR32(d); -+ -+ *tdthresh = qbman_thresh_to_value(qb_attr_code_decode(&code_fq_tdthresh, -+ p)); -+} -+ -+void qbman_fq_attr_get_oa(struct qbman_attr *d, -+ int *oa_ics, int *oa_cgr, int32_t *oa_len) -+{ -+ uint32_t *p = ATTR32(d); -+ -+ *oa_ics = !!qb_attr_code_decode(&code_fq_oa_ics, p); -+ *oa_cgr = !!qb_attr_code_decode(&code_fq_oa_cgr, p); -+ *oa_len = qb_attr_code_makesigned(&code_fq_oa_len, -+ qb_attr_code_decode(&code_fq_oa_len, p)); -+} -+ -+void qbman_fq_attr_get_mctl(struct qbman_attr *d, -+ int *bdi, int *ff, int *va, int *ps) -+{ -+ uint32_t *p = ATTR32(d); -+ -+ *bdi = !!qb_attr_code_decode(&code_fq_mctl_bdi, p); -+ *ff = !!qb_attr_code_decode(&code_fq_mctl_ff, p); -+ *va = !!qb_attr_code_decode(&code_fq_mctl_va, p); -+ *ps = !!qb_attr_code_decode(&code_fq_mctl_ps, p); -+} -+ -+void qbman_fq_attr_get_ctx(struct qbman_attr *d, uint32_t *hi, uint32_t *lo) -+{ -+ uint32_t *p = ATTR32(d); -+ -+ *hi = qb_attr_code_decode(&code_fq_ctx_upper32, p); -+ *lo = qb_attr_code_decode(&code_fq_ctx_lower32, p); -+} -+ -+void qbman_fq_attr_get_icid(struct qbman_attr *d, uint32_t *icid, int *pl) -+{ -+ uint32_t *p = ATTR32(d); -+ -+ *icid = qb_attr_code_decode(&code_fq_icid, p); -+ *pl = !!qb_attr_code_decode(&code_fq_pl, p); -+} -+ -+void qbman_fq_attr_get_vfqid(struct qbman_attr *d, uint32_t *vfqid) -+{ -+ uint32_t *p = ATTR32(d); -+ -+ *vfqid = qb_attr_code_decode(&code_fq_vfqid, p); -+} -+ -+void qbman_fq_attr_get_erfqid(struct qbman_attr *d, uint32_t *erfqid) -+{ -+ uint32_t *p = ATTR32(d); -+ -+ *erfqid = qb_attr_code_decode(&code_fq_erfqid, p); -+} -+ -+/* Query FQ Non-Programmalbe Fields */ -+static struct qb_attr_code code_fq_np_state = QB_CODE(0, 16, 3); -+static struct qb_attr_code code_fq_np_fe = QB_CODE(0, 19, 1); -+static struct qb_attr_code code_fq_np_x = QB_CODE(0, 20, 1); -+static struct qb_attr_code code_fq_np_r = QB_CODE(0, 21, 1); -+static struct qb_attr_code code_fq_np_oe = QB_CODE(0, 22, 1); -+static struct qb_attr_code code_fq_np_frm_cnt = QB_CODE(6, 0, 24); -+static struct qb_attr_code code_fq_np_byte_cnt = QB_CODE(7, 0, 32); -+ -+int qbman_fq_query_state(struct qbman_swp *s, uint32_t fqid, -+ struct qbman_attr *state) -+{ -+ uint32_t *p; -+ uint32_t verb, rslt; -+ uint32_t *d = ATTR32(state); -+ -+ qbman_fq_attr_clear(state); -+ -+ p = qbman_swp_mc_start(s); -+ if (!p) -+ return -EBUSY; -+ qb_attr_code_encode(&code_fq_fqid, p, fqid); -+ p = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY_NP); -+ -+ /* Decode the outcome */ -+ verb = qb_attr_code_decode(&code_generic_verb, p); -+ rslt = qb_attr_code_decode(&code_generic_rslt, p); -+ BUG_ON(verb != QBMAN_FQ_QUERY_NP); -+ -+ /* Determine success or failure */ -+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) { -+ pr_err("Query NP fields of FQID 0x%x failed, code=0x%02x\n", -+ fqid, rslt); -+ return -EIO; -+ } -+ word_copy(&d[0], &p[0], 16); -+ return 0; -+} -+ -+uint32_t qbman_fq_state_schedstate(const struct qbman_attr *state) -+{ -+ const uint32_t *p = ATTR32(state); -+ -+ return qb_attr_code_decode(&code_fq_np_state, p); -+} -+ -+int qbman_fq_state_force_eligible(const struct qbman_attr *state) -+{ -+ const uint32_t *p = ATTR32(state); -+ -+ return !!qb_attr_code_decode(&code_fq_np_fe, p); -+} -+ -+int qbman_fq_state_xoff(const struct qbman_attr *state) -+{ -+ const uint32_t *p = ATTR32(state); -+ -+ return !!qb_attr_code_decode(&code_fq_np_x, p); -+} -+ -+int qbman_fq_state_retirement_pending(const struct qbman_attr *state) -+{ -+ const uint32_t *p = ATTR32(state); -+ -+ return !!qb_attr_code_decode(&code_fq_np_r, p); -+} -+ -+int qbman_fq_state_overflow_error(const struct qbman_attr *state) -+{ -+ const uint32_t *p = ATTR32(state); -+ -+ return !!qb_attr_code_decode(&code_fq_np_oe, p); -+} -+ -+uint32_t qbman_fq_state_frame_count(const struct qbman_attr *state) -+{ -+ const uint32_t *p = ATTR32(state); -+ -+ return qb_attr_code_decode(&code_fq_np_frm_cnt, p); -+} -+ -+uint32_t qbman_fq_state_byte_count(const struct qbman_attr *state) -+{ -+ const uint32_t *p = ATTR32(state); -+ -+ return qb_attr_code_decode(&code_fq_np_byte_cnt, p); -+} -+ -+/* Query CGR */ -+static struct qb_attr_code code_cgr_cgid = QB_CODE(0, 16, 16); -+static struct qb_attr_code code_cgr_cscn_wq_en_enter = QB_CODE(2, 0, 1); -+static struct qb_attr_code code_cgr_cscn_wq_en_exit = QB_CODE(2, 1, 1); -+static struct qb_attr_code code_cgr_cscn_wq_icd = QB_CODE(2, 2, 1); -+static struct qb_attr_code code_cgr_mode = QB_CODE(3, 16, 2); -+static struct qb_attr_code code_cgr_rej_cnt_mode = QB_CODE(3, 18, 1); -+static struct qb_attr_code code_cgr_cscn_bdi = QB_CODE(3, 19, 1); -+static struct qb_attr_code code_cgr_cscn_wr_en_enter = QB_CODE(3, 24, 1); -+static struct qb_attr_code code_cgr_cscn_wr_en_exit = QB_CODE(3, 25, 1); -+static struct qb_attr_code code_cgr_cg_wr_ae = QB_CODE(3, 26, 1); -+static struct qb_attr_code code_cgr_cscn_dcp_en = QB_CODE(3, 27, 1); -+static struct qb_attr_code code_cgr_cg_wr_va = QB_CODE(3, 28, 1); -+static struct qb_attr_code code_cgr_i_cnt_wr_en = QB_CODE(4, 0, 1); -+static struct qb_attr_code code_cgr_i_cnt_wr_bnd = QB_CODE(4, 1, 5); -+static struct qb_attr_code code_cgr_td_en = QB_CODE(4, 8, 1); -+static struct qb_attr_code code_cgr_cs_thres = QB_CODE(4, 16, 13); -+static struct qb_attr_code code_cgr_cs_thres_x = QB_CODE(5, 0, 13); -+static struct qb_attr_code code_cgr_td_thres = QB_CODE(5, 16, 13); -+static struct qb_attr_code code_cgr_cscn_tdcp = QB_CODE(6, 0, 16); -+static struct qb_attr_code code_cgr_cscn_wqid = QB_CODE(6, 16, 16); -+static struct qb_attr_code code_cgr_cscn_vcgid = QB_CODE(7, 0, 16); -+static struct qb_attr_code code_cgr_cg_icid = QB_CODE(7, 16, 15); -+static struct qb_attr_code code_cgr_cg_pl = QB_CODE(7, 31, 1); -+static struct qb_attr_code code_cgr_cg_wr_addr_lo = QB_CODE(8, 0, 32); -+static struct qb_attr_code code_cgr_cg_wr_addr_hi = QB_CODE(9, 0, 32); -+static struct qb_attr_code code_cgr_cscn_ctx_lo = QB_CODE(10, 0, 32); -+static struct qb_attr_code code_cgr_cscn_ctx_hi = QB_CODE(11, 0, 32); -+ -+void qbman_cgr_attr_clear(struct qbman_attr *a) -+{ -+ memset(a, 0, sizeof(*a)); -+ attr_type_set(a, qbman_attr_usage_cgr); -+} -+ -+int qbman_cgr_query(struct qbman_swp *s, uint32_t cgid, struct qbman_attr *attr) -+{ -+ uint32_t *p; -+ uint32_t verb, rslt; -+ uint32_t *d[2]; -+ int i; -+ uint32_t query_verb; -+ -+ d[0] = ATTR32(attr); -+ d[1] = ATTR32_1(attr); -+ -+ qbman_cgr_attr_clear(attr); -+ -+ for (i = 0; i < 2; i++) { -+ p = qbman_swp_mc_start(s); -+ if (!p) -+ return -EBUSY; -+ query_verb = i ? QBMAN_WRED_QUERY : QBMAN_CGR_QUERY; -+ -+ qb_attr_code_encode(&code_cgr_cgid, p, cgid); -+ p = qbman_swp_mc_complete(s, p, p[0] | query_verb); -+ -+ /* Decode the outcome */ -+ verb = qb_attr_code_decode(&code_generic_verb, p); -+ rslt = qb_attr_code_decode(&code_generic_rslt, p); -+ BUG_ON(verb != query_verb); -+ -+ /* Determine success or failure */ -+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) { -+ pr_err("Query CGID 0x%x failed,", cgid); -+ pr_err(" verb=0x%02x, code=0x%02x\n", verb, rslt); -+ return -EIO; -+ } -+ /* For the configure, word[0] of the command contains only the -+ * verb/cgid. For the query, word[0] of the result contains -+ * only the verb/rslt fields. Skip word[0] in the latter case. -+ */ -+ word_copy(&d[i][1], &p[1], 15); -+ } -+ return 0; -+} -+ -+void qbman_cgr_attr_get_ctl1(struct qbman_attr *d, int *cscn_wq_en_enter, -+ int *cscn_wq_en_exit, int *cscn_wq_icd) -+ { -+ uint32_t *p = ATTR32(d); -+ *cscn_wq_en_enter = !!qb_attr_code_decode(&code_cgr_cscn_wq_en_enter, -+ p); -+ *cscn_wq_en_exit = !!qb_attr_code_decode(&code_cgr_cscn_wq_en_exit, p); -+ *cscn_wq_icd = !!qb_attr_code_decode(&code_cgr_cscn_wq_icd, p); -+} -+ -+void qbman_cgr_attr_get_mode(struct qbman_attr *d, uint32_t *mode, -+ int *rej_cnt_mode, int *cscn_bdi) -+{ -+ uint32_t *p = ATTR32(d); -+ *mode = qb_attr_code_decode(&code_cgr_mode, p); -+ *rej_cnt_mode = !!qb_attr_code_decode(&code_cgr_rej_cnt_mode, p); -+ *cscn_bdi = !!qb_attr_code_decode(&code_cgr_cscn_bdi, p); -+} -+ -+void qbman_cgr_attr_get_ctl2(struct qbman_attr *d, int *cscn_wr_en_enter, -+ int *cscn_wr_en_exit, int *cg_wr_ae, -+ int *cscn_dcp_en, int *cg_wr_va) -+{ -+ uint32_t *p = ATTR32(d); -+ *cscn_wr_en_enter = !!qb_attr_code_decode(&code_cgr_cscn_wr_en_enter, -+ p); -+ *cscn_wr_en_exit = !!qb_attr_code_decode(&code_cgr_cscn_wr_en_exit, p); -+ *cg_wr_ae = !!qb_attr_code_decode(&code_cgr_cg_wr_ae, p); -+ *cscn_dcp_en = !!qb_attr_code_decode(&code_cgr_cscn_dcp_en, p); -+ *cg_wr_va = !!qb_attr_code_decode(&code_cgr_cg_wr_va, p); -+} -+ -+void qbman_cgr_attr_get_iwc(struct qbman_attr *d, int *i_cnt_wr_en, -+ uint32_t *i_cnt_wr_bnd) -+{ -+ uint32_t *p = ATTR32(d); -+ *i_cnt_wr_en = !!qb_attr_code_decode(&code_cgr_i_cnt_wr_en, p); -+ *i_cnt_wr_bnd = qb_attr_code_decode(&code_cgr_i_cnt_wr_bnd, p); -+} -+ -+void qbman_cgr_attr_get_tdc(struct qbman_attr *d, int *td_en) -+{ -+ uint32_t *p = ATTR32(d); -+ *td_en = !!qb_attr_code_decode(&code_cgr_td_en, p); -+} -+ -+void qbman_cgr_attr_get_cs_thres(struct qbman_attr *d, uint32_t *cs_thres) -+{ -+ uint32_t *p = ATTR32(d); -+ *cs_thres = qbman_thresh_to_value(qb_attr_code_decode( -+ &code_cgr_cs_thres, p)); -+} -+ -+void qbman_cgr_attr_get_cs_thres_x(struct qbman_attr *d, -+ uint32_t *cs_thres_x) -+{ -+ uint32_t *p = ATTR32(d); -+ *cs_thres_x = qbman_thresh_to_value(qb_attr_code_decode( -+ &code_cgr_cs_thres_x, p)); -+} -+ -+void qbman_cgr_attr_get_td_thres(struct qbman_attr *d, uint32_t *td_thres) -+{ -+ uint32_t *p = ATTR32(d); -+ *td_thres = qbman_thresh_to_value(qb_attr_code_decode( -+ &code_cgr_td_thres, p)); -+} -+ -+void qbman_cgr_attr_get_cscn_tdcp(struct qbman_attr *d, uint32_t *cscn_tdcp) -+{ -+ uint32_t *p = ATTR32(d); -+ *cscn_tdcp = qb_attr_code_decode(&code_cgr_cscn_tdcp, p); -+} -+ -+void qbman_cgr_attr_get_cscn_wqid(struct qbman_attr *d, uint32_t *cscn_wqid) -+{ -+ uint32_t *p = ATTR32(d); -+ *cscn_wqid = qb_attr_code_decode(&code_cgr_cscn_wqid, p); -+} -+ -+void qbman_cgr_attr_get_cscn_vcgid(struct qbman_attr *d, -+ uint32_t *cscn_vcgid) -+{ -+ uint32_t *p = ATTR32(d); -+ *cscn_vcgid = qb_attr_code_decode(&code_cgr_cscn_vcgid, p); -+} -+ -+void qbman_cgr_attr_get_cg_icid(struct qbman_attr *d, uint32_t *icid, -+ int *pl) -+{ -+ uint32_t *p = ATTR32(d); -+ *icid = qb_attr_code_decode(&code_cgr_cg_icid, p); -+ *pl = !!qb_attr_code_decode(&code_cgr_cg_pl, p); -+} -+ -+void qbman_cgr_attr_get_cg_wr_addr(struct qbman_attr *d, -+ uint64_t *cg_wr_addr) -+{ -+ uint32_t *p = ATTR32(d); -+ *cg_wr_addr = ((uint64_t)qb_attr_code_decode(&code_cgr_cg_wr_addr_hi, -+ p) << 32) | -+ (uint64_t)qb_attr_code_decode(&code_cgr_cg_wr_addr_lo, -+ p); -+} -+ -+void qbman_cgr_attr_get_cscn_ctx(struct qbman_attr *d, uint64_t *cscn_ctx) -+{ -+ uint32_t *p = ATTR32(d); -+ *cscn_ctx = ((uint64_t)qb_attr_code_decode(&code_cgr_cscn_ctx_hi, p) -+ << 32) | -+ (uint64_t)qb_attr_code_decode(&code_cgr_cscn_ctx_lo, p); -+} -+ -+#define WRED_EDP_WORD(n) (18 + n/4) -+#define WRED_EDP_OFFSET(n) (8 * (n % 4)) -+#define WRED_PARM_DP_WORD(n) (n + 20) -+#define WRED_WE_EDP(n) (16 + n * 2) -+#define WRED_WE_PARM_DP(n) (17 + n * 2) -+void qbman_cgr_attr_wred_get_edp(struct qbman_attr *d, uint32_t idx, -+ int *edp) -+{ -+ uint32_t *p = ATTR32(d); -+ struct qb_attr_code code_wred_edp = QB_CODE(WRED_EDP_WORD(idx), -+ WRED_EDP_OFFSET(idx), 8); -+ *edp = (int)qb_attr_code_decode(&code_wred_edp, p); -+} -+ -+void qbman_cgr_attr_wred_dp_decompose(uint32_t dp, uint64_t *minth, -+ uint64_t *maxth, uint8_t *maxp) -+{ -+ uint8_t ma, mn, step_i, step_s, pn; -+ -+ ma = (uint8_t)(dp >> 24); -+ mn = (uint8_t)(dp >> 19) & 0x1f; -+ step_i = (uint8_t)(dp >> 11); -+ step_s = (uint8_t)(dp >> 6) & 0x1f; -+ pn = (uint8_t)dp & 0x3f; -+ -+ *maxp = ((pn<<2) * 100)/256; -+ -+ if (mn == 0) -+ *maxth = ma; -+ else -+ *maxth = ((ma+256) * (1<<(mn-1))); -+ -+ if (step_s == 0) -+ *minth = *maxth - step_i; -+ else -+ *minth = *maxth - (256 + step_i) * (1<<(step_s - 1)); -+} -+ -+void qbman_cgr_attr_wred_get_parm_dp(struct qbman_attr *d, uint32_t idx, -+ uint32_t *dp) -+{ -+ uint32_t *p = ATTR32(d); -+ struct qb_attr_code code_wred_parm_dp = QB_CODE(WRED_PARM_DP_WORD(idx), -+ 0, 8); -+ *dp = qb_attr_code_decode(&code_wred_parm_dp, p); -+} -+ -+/* Query CGR/CCGR/CQ statistics */ -+static struct qb_attr_code code_cgr_stat_ct = QB_CODE(4, 0, 32); -+static struct qb_attr_code code_cgr_stat_frame_cnt_lo = QB_CODE(4, 0, 32); -+static struct qb_attr_code code_cgr_stat_frame_cnt_hi = QB_CODE(5, 0, 8); -+static struct qb_attr_code code_cgr_stat_byte_cnt_lo = QB_CODE(6, 0, 32); -+static struct qb_attr_code code_cgr_stat_byte_cnt_hi = QB_CODE(7, 0, 16); -+static int qbman_cgr_statistics_query(struct qbman_swp *s, uint32_t cgid, -+ int clear, uint32_t command_type, -+ uint64_t *frame_cnt, uint64_t *byte_cnt) -+{ -+ uint32_t *p; -+ uint32_t verb, rslt; -+ uint32_t query_verb; -+ uint32_t hi, lo; -+ -+ p = qbman_swp_mc_start(s); -+ if (!p) -+ return -EBUSY; -+ -+ qb_attr_code_encode(&code_cgr_cgid, p, cgid); -+ if (command_type < 2) -+ qb_attr_code_encode(&code_cgr_stat_ct, p, command_type); -+ query_verb = clear ? -+ QBMAN_CGR_STAT_QUERY_CLR : QBMAN_CGR_STAT_QUERY; -+ p = qbman_swp_mc_complete(s, p, p[0] | query_verb); -+ -+ /* Decode the outcome */ -+ verb = qb_attr_code_decode(&code_generic_verb, p); -+ rslt = qb_attr_code_decode(&code_generic_rslt, p); -+ BUG_ON(verb != query_verb); -+ -+ /* Determine success or failure */ -+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) { -+ pr_err("Query statistics of CGID 0x%x failed,", cgid); -+ pr_err(" verb=0x%02x code=0x%02x\n", verb, rslt); -+ return -EIO; -+ } -+ -+ if (*frame_cnt) { -+ hi = qb_attr_code_decode(&code_cgr_stat_frame_cnt_hi, p); -+ lo = qb_attr_code_decode(&code_cgr_stat_frame_cnt_lo, p); -+ *frame_cnt = ((uint64_t)hi << 32) | (uint64_t)lo; -+ } -+ if (*byte_cnt) { -+ hi = qb_attr_code_decode(&code_cgr_stat_byte_cnt_hi, p); -+ lo = qb_attr_code_decode(&code_cgr_stat_byte_cnt_lo, p); -+ *byte_cnt = ((uint64_t)hi << 32) | (uint64_t)lo; -+ } -+ -+ return 0; -+} -+ -+int qbman_cgr_reject_statistics(struct qbman_swp *s, uint32_t cgid, int clear, -+ uint64_t *frame_cnt, uint64_t *byte_cnt) -+{ -+ return qbman_cgr_statistics_query(s, cgid, clear, 0xff, -+ frame_cnt, byte_cnt); -+} -+ -+int qbman_ccgr_reject_statistics(struct qbman_swp *s, uint32_t cgid, int clear, -+ uint64_t *frame_cnt, uint64_t *byte_cnt) -+{ -+ return qbman_cgr_statistics_query(s, cgid, clear, 1, -+ frame_cnt, byte_cnt); -+} -+ -+int qbman_cq_dequeue_statistics(struct qbman_swp *s, uint32_t cgid, int clear, -+ uint64_t *frame_cnt, uint64_t *byte_cnt) -+{ -+ return qbman_cgr_statistics_query(s, cgid, clear, 0, -+ frame_cnt, byte_cnt); -+} ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/qbman_debug.h -@@ -0,0 +1,136 @@ -+/* Copyright (C) 2015 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+struct qbman_attr { -+ uint32_t dont_manipulate_directly[40]; -+}; -+ -+/* Buffer pool query commands */ -+int qbman_bp_query(struct qbman_swp *s, uint32_t bpid, -+ struct qbman_attr *a); -+void qbman_bp_attr_get_bdi(struct qbman_attr *a, int *bdi, int *va, int *wae); -+void qbman_bp_attr_get_swdet(struct qbman_attr *a, uint32_t *swdet); -+void qbman_bp_attr_get_swdxt(struct qbman_attr *a, uint32_t *swdxt); -+void qbman_bp_attr_get_hwdet(struct qbman_attr *a, uint32_t *hwdet); -+void qbman_bp_attr_get_hwdxt(struct qbman_attr *a, uint32_t *hwdxt); -+void qbman_bp_attr_get_swset(struct qbman_attr *a, uint32_t *swset); -+void qbman_bp_attr_get_swsxt(struct qbman_attr *a, uint32_t *swsxt); -+void qbman_bp_attr_get_vbpid(struct qbman_attr *a, uint32_t *vbpid); -+void qbman_bp_attr_get_icid(struct qbman_attr *a, uint32_t *icid, int *pl); -+void qbman_bp_attr_get_bpscn_addr(struct qbman_attr *a, uint64_t *bpscn_addr); -+void qbman_bp_attr_get_bpscn_ctx(struct qbman_attr *a, uint64_t *bpscn_ctx); -+void qbman_bp_attr_get_hw_targ(struct qbman_attr *a, uint32_t *hw_targ); -+int qbman_bp_info_has_free_bufs(struct qbman_attr *a); -+int qbman_bp_info_is_depleted(struct qbman_attr *a); -+int qbman_bp_info_is_surplus(struct qbman_attr *a); -+uint32_t qbman_bp_info_num_free_bufs(struct qbman_attr *a); -+uint32_t qbman_bp_info_hdptr(struct qbman_attr *a); -+uint32_t qbman_bp_info_sdcnt(struct qbman_attr *a); -+uint32_t qbman_bp_info_hdcnt(struct qbman_attr *a); -+uint32_t qbman_bp_info_sscnt(struct qbman_attr *a); -+ -+/* FQ query function for programmable fields */ -+int qbman_fq_query(struct qbman_swp *s, uint32_t fqid, -+ struct qbman_attr *desc); -+void qbman_fq_attr_get_fqctrl(struct qbman_attr *d, uint32_t *fqctrl); -+void qbman_fq_attr_get_cgrid(struct qbman_attr *d, uint32_t *cgrid); -+void qbman_fq_attr_get_destwq(struct qbman_attr *d, uint32_t *destwq); -+void qbman_fq_attr_get_icscred(struct qbman_attr *d, uint32_t *icscred); -+void qbman_fq_attr_get_tdthresh(struct qbman_attr *d, uint32_t *tdthresh); -+void qbman_fq_attr_get_oa(struct qbman_attr *d, -+ int *oa_ics, int *oa_cgr, int32_t *oa_len); -+void qbman_fq_attr_get_mctl(struct qbman_attr *d, -+ int *bdi, int *ff, int *va, int *ps); -+void qbman_fq_attr_get_ctx(struct qbman_attr *d, uint32_t *hi, uint32_t *lo); -+void qbman_fq_attr_get_icid(struct qbman_attr *d, uint32_t *icid, int *pl); -+void qbman_fq_attr_get_vfqid(struct qbman_attr *d, uint32_t *vfqid); -+void qbman_fq_attr_get_erfqid(struct qbman_attr *d, uint32_t *erfqid); -+ -+/* FQ query command for non-programmable fields*/ -+enum qbman_fq_schedstate_e { -+ qbman_fq_schedstate_oos = 0, -+ qbman_fq_schedstate_retired, -+ qbman_fq_schedstate_tentatively_scheduled, -+ qbman_fq_schedstate_truly_scheduled, -+ qbman_fq_schedstate_parked, -+ qbman_fq_schedstate_held_active, -+}; -+ -+int qbman_fq_query_state(struct qbman_swp *s, uint32_t fqid, -+ struct qbman_attr *state); -+uint32_t qbman_fq_state_schedstate(const struct qbman_attr *state); -+int qbman_fq_state_force_eligible(const struct qbman_attr *state); -+int qbman_fq_state_xoff(const struct qbman_attr *state); -+int qbman_fq_state_retirement_pending(const struct qbman_attr *state); -+int qbman_fq_state_overflow_error(const struct qbman_attr *state); -+uint32_t qbman_fq_state_frame_count(const struct qbman_attr *state); -+uint32_t qbman_fq_state_byte_count(const struct qbman_attr *state); -+ -+/* CGR query */ -+int qbman_cgr_query(struct qbman_swp *s, uint32_t cgid, -+ struct qbman_attr *attr); -+void qbman_cgr_attr_get_ctl1(struct qbman_attr *d, int *cscn_wq_en_enter, -+ int *cscn_wq_en_exit, int *cscn_wq_icd); -+void qbman_cgr_attr_get_mode(struct qbman_attr *d, uint32_t *mode, -+ int *rej_cnt_mode, int *cscn_bdi); -+void qbman_cgr_attr_get_ctl2(struct qbman_attr *d, int *cscn_wr_en_enter, -+ int *cscn_wr_en_exit, int *cg_wr_ae, -+ int *cscn_dcp_en, int *cg_wr_va); -+void qbman_cgr_attr_get_iwc(struct qbman_attr *d, int *i_cnt_wr_en, -+ uint32_t *i_cnt_wr_bnd); -+void qbman_cgr_attr_get_tdc(struct qbman_attr *d, int *td_en); -+void qbman_cgr_attr_get_cs_thres(struct qbman_attr *d, uint32_t *cs_thres); -+void qbman_cgr_attr_get_cs_thres_x(struct qbman_attr *d, -+ uint32_t *cs_thres_x); -+void qbman_cgr_attr_get_td_thres(struct qbman_attr *d, uint32_t *td_thres); -+void qbman_cgr_attr_get_cscn_tdcp(struct qbman_attr *d, uint32_t *cscn_tdcp); -+void qbman_cgr_attr_get_cscn_wqid(struct qbman_attr *d, uint32_t *cscn_wqid); -+void qbman_cgr_attr_get_cscn_vcgid(struct qbman_attr *d, -+ uint32_t *cscn_vcgid); -+void qbman_cgr_attr_get_cg_icid(struct qbman_attr *d, uint32_t *icid, -+ int *pl); -+void qbman_cgr_attr_get_cg_wr_addr(struct qbman_attr *d, -+ uint64_t *cg_wr_addr); -+void qbman_cgr_attr_get_cscn_ctx(struct qbman_attr *d, uint64_t *cscn_ctx); -+void qbman_cgr_attr_wred_get_edp(struct qbman_attr *d, uint32_t idx, -+ int *edp); -+void qbman_cgr_attr_wred_dp_decompose(uint32_t dp, uint64_t *minth, -+ uint64_t *maxth, uint8_t *maxp); -+void qbman_cgr_attr_wred_get_parm_dp(struct qbman_attr *d, uint32_t idx, -+ uint32_t *dp); -+ -+/* CGR/CCGR/CQ statistics query */ -+int qbman_cgr_reject_statistics(struct qbman_swp *s, uint32_t cgid, int clear, -+ uint64_t *frame_cnt, uint64_t *byte_cnt); -+int qbman_ccgr_reject_statistics(struct qbman_swp *s, uint32_t cgid, int clear, -+ uint64_t *frame_cnt, uint64_t *byte_cnt); -+int qbman_cq_dequeue_statistics(struct qbman_swp *s, uint32_t cgid, int clear, -+ uint64_t *frame_cnt, uint64_t *byte_cnt); ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/qbman_portal.c -@@ -0,0 +1,1212 @@ -+/* Copyright (C) 2014 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "qbman_portal.h" -+ -+/* QBMan portal management command codes */ -+#define QBMAN_MC_ACQUIRE 0x30 -+#define QBMAN_WQCHAN_CONFIGURE 0x46 -+ -+/* CINH register offsets */ -+#define QBMAN_CINH_SWP_EQAR 0x8c0 -+#define QBMAN_CINH_SWP_DQPI 0xa00 -+#define QBMAN_CINH_SWP_DCAP 0xac0 -+#define QBMAN_CINH_SWP_SDQCR 0xb00 -+#define QBMAN_CINH_SWP_RAR 0xcc0 -+#define QBMAN_CINH_SWP_ISR 0xe00 -+#define QBMAN_CINH_SWP_IER 0xe40 -+#define QBMAN_CINH_SWP_ISDR 0xe80 -+#define QBMAN_CINH_SWP_IIR 0xec0 -+ -+/* CENA register offsets */ -+#define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((uint32_t)(n) << 6)) -+#define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((uint32_t)(n) << 6)) -+#define QBMAN_CENA_SWP_RCR(n) (0x400 + ((uint32_t)(n) << 6)) -+#define QBMAN_CENA_SWP_CR 0x600 -+#define QBMAN_CENA_SWP_RR(vb) (0x700 + ((uint32_t)(vb) >> 1)) -+#define QBMAN_CENA_SWP_VDQCR 0x780 -+ -+/* Reverse mapping of QBMAN_CENA_SWP_DQRR() */ -+#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0x1ff) >> 6) -+ -+/* QBMan FQ management command codes */ -+#define QBMAN_FQ_SCHEDULE 0x48 -+#define QBMAN_FQ_FORCE 0x49 -+#define QBMAN_FQ_XON 0x4d -+#define QBMAN_FQ_XOFF 0x4e -+ -+/*******************************/ -+/* Pre-defined attribute codes */ -+/*******************************/ -+ -+struct qb_attr_code code_generic_verb = QB_CODE(0, 0, 7); -+struct qb_attr_code code_generic_rslt = QB_CODE(0, 8, 8); -+ -+/*************************/ -+/* SDQCR attribute codes */ -+/*************************/ -+ -+/* we put these here because at least some of them are required by -+ * qbman_swp_init() */ -+struct qb_attr_code code_sdqcr_dct = QB_CODE(0, 24, 2); -+struct qb_attr_code code_sdqcr_fc = QB_CODE(0, 29, 1); -+struct qb_attr_code code_sdqcr_tok = QB_CODE(0, 16, 8); -+#define CODE_SDQCR_DQSRC(n) QB_CODE(0, n, 1) -+enum qbman_sdqcr_dct { -+ qbman_sdqcr_dct_null = 0, -+ qbman_sdqcr_dct_prio_ics, -+ qbman_sdqcr_dct_active_ics, -+ qbman_sdqcr_dct_active -+}; -+enum qbman_sdqcr_fc { -+ qbman_sdqcr_fc_one = 0, -+ qbman_sdqcr_fc_up_to_3 = 1 -+}; -+struct qb_attr_code code_sdqcr_dqsrc = QB_CODE(0, 0, 16); -+ -+/*********************************/ -+/* Portal constructor/destructor */ -+/*********************************/ -+ -+/* Software portals should always be in the power-on state when we initialise, -+ * due to the CCSR-based portal reset functionality that MC has. -+ * -+ * Erk! Turns out that QMan versions prior to 4.1 do not correctly reset DQRR -+ * valid-bits, so we need to support a workaround where we don't trust -+ * valid-bits when detecting new entries until any stale ring entries have been -+ * overwritten at least once. The idea is that we read PI for the first few -+ * entries, then switch to valid-bit after that. The trick is to clear the -+ * bug-work-around boolean once the PI wraps around the ring for the first time. -+ * -+ * Note: this still carries a slight additional cost once the decrementer hits -+ * zero, so ideally the workaround should only be compiled in if the compiled -+ * image needs to support affected chips. We use WORKAROUND_DQRR_RESET_BUG for -+ * this. -+ */ -+struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) -+{ -+ int ret; -+ struct qbman_swp *p = kmalloc(sizeof(*p), GFP_KERNEL); -+ -+ if (!p) -+ return NULL; -+ p->desc = d; -+#ifdef QBMAN_CHECKING -+ p->mc.check = swp_mc_can_start; -+#endif -+ p->mc.valid_bit = QB_VALID_BIT; -+ p->sdq = 0; -+ qb_attr_code_encode(&code_sdqcr_dct, &p->sdq, qbman_sdqcr_dct_prio_ics); -+ qb_attr_code_encode(&code_sdqcr_fc, &p->sdq, qbman_sdqcr_fc_up_to_3); -+ qb_attr_code_encode(&code_sdqcr_tok, &p->sdq, 0xbb); -+ atomic_set(&p->vdq.busy, 1); -+ p->vdq.valid_bit = QB_VALID_BIT; -+ p->dqrr.next_idx = 0; -+ p->dqrr.valid_bit = QB_VALID_BIT; -+ /* TODO: should also read PI/CI type registers and check that they're on -+ * PoR values. If we're asked to initialise portals that aren't in reset -+ * state, bad things will follow. */ -+#ifdef WORKAROUND_DQRR_RESET_BUG -+ p->dqrr.reset_bug = 1; -+#endif -+ if ((p->desc->qman_version & 0xFFFF0000) < QMAN_REV_4100) -+ p->dqrr.dqrr_size = 4; -+ else -+ p->dqrr.dqrr_size = 8; -+ ret = qbman_swp_sys_init(&p->sys, d, p->dqrr.dqrr_size); -+ if (ret) { -+ kfree(p); -+ pr_err("qbman_swp_sys_init() failed %d\n", ret); -+ return NULL; -+ } -+ /* SDQCR needs to be initialized to 0 when no channels are -+ being dequeued from or else the QMan HW will indicate an -+ error. The values that were calculated above will be -+ applied when dequeues from a specific channel are enabled */ -+ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_SDQCR, 0); -+ return p; -+} -+ -+void qbman_swp_finish(struct qbman_swp *p) -+{ -+#ifdef QBMAN_CHECKING -+ BUG_ON(p->mc.check != swp_mc_can_start); -+#endif -+ qbman_swp_sys_finish(&p->sys); -+ kfree(p); -+} -+ -+const struct qbman_swp_desc *qbman_swp_get_desc(struct qbman_swp *p) -+{ -+ return p->desc; -+} -+ -+/**************/ -+/* Interrupts */ -+/**************/ -+ -+uint32_t qbman_swp_interrupt_get_vanish(struct qbman_swp *p) -+{ -+ return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ISDR); -+} -+ -+void qbman_swp_interrupt_set_vanish(struct qbman_swp *p, uint32_t mask) -+{ -+ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ISDR, mask); -+} -+ -+uint32_t qbman_swp_interrupt_read_status(struct qbman_swp *p) -+{ -+ return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ISR); -+} -+ -+void qbman_swp_interrupt_clear_status(struct qbman_swp *p, uint32_t mask) -+{ -+ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ISR, mask); -+} -+ -+uint32_t qbman_swp_interrupt_get_trigger(struct qbman_swp *p) -+{ -+ return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_IER); -+} -+ -+void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, uint32_t mask) -+{ -+ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_IER, mask); -+} -+ -+int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p) -+{ -+ return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_IIR); -+} -+ -+void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit) -+{ -+ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_IIR, inhibit ? 0xffffffff : 0); -+} -+ -+/***********************/ -+/* Management commands */ -+/***********************/ -+ -+/* -+ * Internal code common to all types of management commands. -+ */ -+ -+void *qbman_swp_mc_start(struct qbman_swp *p) -+{ -+ void *ret; -+#ifdef QBMAN_CHECKING -+ BUG_ON(p->mc.check != swp_mc_can_start); -+#endif -+ ret = qbman_cena_write_start(&p->sys, QBMAN_CENA_SWP_CR); -+#ifdef QBMAN_CHECKING -+ if (!ret) -+ p->mc.check = swp_mc_can_submit; -+#endif -+ return ret; -+} -+ -+void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint32_t cmd_verb) -+{ -+ uint32_t *v = cmd; -+#ifdef QBMAN_CHECKING -+ BUG_ON(!p->mc.check != swp_mc_can_submit); -+#endif -+ /* TBD: "|=" is going to hurt performance. Need to move as many fields -+ * out of word zero, and for those that remain, the "OR" needs to occur -+ * at the caller side. This debug check helps to catch cases where the -+ * caller wants to OR but has forgotten to do so. */ -+ BUG_ON((*v & cmd_verb) != *v); -+ *v = cmd_verb | p->mc.valid_bit; -+ qbman_cena_write_complete(&p->sys, QBMAN_CENA_SWP_CR, cmd); -+#ifdef QBMAN_CHECKING -+ p->mc.check = swp_mc_can_poll; -+#endif -+} -+ -+void *qbman_swp_mc_result(struct qbman_swp *p) -+{ -+ uint32_t *ret, verb; -+#ifdef QBMAN_CHECKING -+ BUG_ON(p->mc.check != swp_mc_can_poll); -+#endif -+ qbman_cena_invalidate_prefetch(&p->sys, -+ QBMAN_CENA_SWP_RR(p->mc.valid_bit)); -+ ret = qbman_cena_read(&p->sys, QBMAN_CENA_SWP_RR(p->mc.valid_bit)); -+ /* Remove the valid-bit - command completed iff the rest is non-zero */ -+ verb = ret[0] & ~QB_VALID_BIT; -+ if (!verb) -+ return NULL; -+#ifdef QBMAN_CHECKING -+ p->mc.check = swp_mc_can_start; -+#endif -+ p->mc.valid_bit ^= QB_VALID_BIT; -+ return ret; -+} -+ -+/***********/ -+/* Enqueue */ -+/***********/ -+ -+/* These should be const, eventually */ -+static struct qb_attr_code code_eq_cmd = QB_CODE(0, 0, 2); -+static struct qb_attr_code code_eq_eqdi = QB_CODE(0, 3, 1); -+static struct qb_attr_code code_eq_dca_en = QB_CODE(0, 15, 1); -+static struct qb_attr_code code_eq_dca_pk = QB_CODE(0, 14, 1); -+static struct qb_attr_code code_eq_dca_idx = QB_CODE(0, 8, 2); -+static struct qb_attr_code code_eq_orp_en = QB_CODE(0, 2, 1); -+static struct qb_attr_code code_eq_orp_is_nesn = QB_CODE(0, 31, 1); -+static struct qb_attr_code code_eq_orp_nlis = QB_CODE(0, 30, 1); -+static struct qb_attr_code code_eq_orp_seqnum = QB_CODE(0, 16, 14); -+static struct qb_attr_code code_eq_opr_id = QB_CODE(1, 0, 16); -+static struct qb_attr_code code_eq_tgt_id = QB_CODE(2, 0, 24); -+/* static struct qb_attr_code code_eq_tag = QB_CODE(3, 0, 32); */ -+static struct qb_attr_code code_eq_qd_en = QB_CODE(0, 4, 1); -+static struct qb_attr_code code_eq_qd_bin = QB_CODE(4, 0, 16); -+static struct qb_attr_code code_eq_qd_pri = QB_CODE(4, 16, 4); -+static struct qb_attr_code code_eq_rsp_stash = QB_CODE(5, 16, 1); -+static struct qb_attr_code code_eq_rsp_id = QB_CODE(5, 24, 8); -+static struct qb_attr_code code_eq_rsp_lo = QB_CODE(6, 0, 32); -+ -+enum qbman_eq_cmd_e { -+ /* No enqueue, primarily for plugging ORP gaps for dropped frames */ -+ qbman_eq_cmd_empty, -+ /* DMA an enqueue response once complete */ -+ qbman_eq_cmd_respond, -+ /* DMA an enqueue response only if the enqueue fails */ -+ qbman_eq_cmd_respond_reject -+}; -+ -+void qbman_eq_desc_clear(struct qbman_eq_desc *d) -+{ -+ memset(d, 0, sizeof(*d)); -+} -+ -+void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_eq_orp_en, cl, 0); -+ qb_attr_code_encode(&code_eq_cmd, cl, -+ respond_success ? qbman_eq_cmd_respond : -+ qbman_eq_cmd_respond_reject); -+} -+ -+void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success, -+ uint32_t opr_id, uint32_t seqnum, int incomplete) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_eq_orp_en, cl, 1); -+ qb_attr_code_encode(&code_eq_cmd, cl, -+ respond_success ? qbman_eq_cmd_respond : -+ qbman_eq_cmd_respond_reject); -+ qb_attr_code_encode(&code_eq_opr_id, cl, opr_id); -+ qb_attr_code_encode(&code_eq_orp_seqnum, cl, seqnum); -+ qb_attr_code_encode(&code_eq_orp_nlis, cl, !!incomplete); -+} -+ -+void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, uint32_t opr_id, -+ uint32_t seqnum) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_eq_orp_en, cl, 1); -+ qb_attr_code_encode(&code_eq_cmd, cl, qbman_eq_cmd_empty); -+ qb_attr_code_encode(&code_eq_opr_id, cl, opr_id); -+ qb_attr_code_encode(&code_eq_orp_seqnum, cl, seqnum); -+ qb_attr_code_encode(&code_eq_orp_nlis, cl, 0); -+ qb_attr_code_encode(&code_eq_orp_is_nesn, cl, 0); -+} -+ -+void qbman_eq_desc_set_orp_nesn(struct qbman_eq_desc *d, uint32_t opr_id, -+ uint32_t seqnum) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_eq_orp_en, cl, 1); -+ qb_attr_code_encode(&code_eq_cmd, cl, qbman_eq_cmd_empty); -+ qb_attr_code_encode(&code_eq_opr_id, cl, opr_id); -+ qb_attr_code_encode(&code_eq_orp_seqnum, cl, seqnum); -+ qb_attr_code_encode(&code_eq_orp_nlis, cl, 0); -+ qb_attr_code_encode(&code_eq_orp_is_nesn, cl, 1); -+} -+ -+void qbman_eq_desc_set_response(struct qbman_eq_desc *d, -+ dma_addr_t storage_phys, -+ int stash) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode_64(&code_eq_rsp_lo, (uint64_t *)cl, storage_phys); -+ qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash); -+} -+ -+void qbman_eq_desc_set_token(struct qbman_eq_desc *d, uint8_t token) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_eq_rsp_id, cl, (uint32_t)token); -+} -+ -+void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, uint32_t fqid) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_eq_qd_en, cl, 0); -+ qb_attr_code_encode(&code_eq_tgt_id, cl, fqid); -+} -+ -+void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid, -+ uint32_t qd_bin, uint32_t qd_prio) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_eq_qd_en, cl, 1); -+ qb_attr_code_encode(&code_eq_tgt_id, cl, qdid); -+ qb_attr_code_encode(&code_eq_qd_bin, cl, qd_bin); -+ qb_attr_code_encode(&code_eq_qd_pri, cl, qd_prio); -+} -+ -+void qbman_eq_desc_set_eqdi(struct qbman_eq_desc *d, int enable) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_eq_eqdi, cl, !!enable); -+} -+ -+void qbman_eq_desc_set_dca(struct qbman_eq_desc *d, int enable, -+ uint32_t dqrr_idx, int park) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_eq_dca_en, cl, !!enable); -+ if (enable) { -+ qb_attr_code_encode(&code_eq_dca_pk, cl, !!park); -+ qb_attr_code_encode(&code_eq_dca_idx, cl, dqrr_idx); -+ } -+} -+ -+#define EQAR_IDX(eqar) ((eqar) & 0x7) -+#define EQAR_VB(eqar) ((eqar) & 0x80) -+#define EQAR_SUCCESS(eqar) ((eqar) & 0x100) -+ -+int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d, -+ const struct qbman_fd *fd) -+{ -+ uint32_t *p; -+ const uint32_t *cl = qb_cl(d); -+ uint32_t eqar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_EQAR); -+ -+ pr_debug("EQAR=%08x\n", eqar); -+ if (!EQAR_SUCCESS(eqar)) -+ return -EBUSY; -+ p = qbman_cena_write_start(&s->sys, -+ QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar))); -+ word_copy(&p[1], &cl[1], 7); -+ word_copy(&p[8], fd, sizeof(*fd) >> 2); -+ /* Set the verb byte, have to substitute in the valid-bit */ -+ p[0] = cl[0] | EQAR_VB(eqar); -+ qbman_cena_write_complete(&s->sys, -+ QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)), -+ p); -+ return 0; -+} -+ -+/*************************/ -+/* Static (push) dequeue */ -+/*************************/ -+ -+void qbman_swp_push_get(struct qbman_swp *s, uint8_t channel_idx, int *enabled) -+{ -+ struct qb_attr_code code = CODE_SDQCR_DQSRC(channel_idx); -+ -+ BUG_ON(channel_idx > 15); -+ *enabled = (int)qb_attr_code_decode(&code, &s->sdq); -+} -+ -+void qbman_swp_push_set(struct qbman_swp *s, uint8_t channel_idx, int enable) -+{ -+ uint16_t dqsrc; -+ struct qb_attr_code code = CODE_SDQCR_DQSRC(channel_idx); -+ -+ BUG_ON(channel_idx > 15); -+ qb_attr_code_encode(&code, &s->sdq, !!enable); -+ /* Read make the complete src map. If no channels are enabled -+ the SDQCR must be 0 or else QMan will assert errors */ -+ dqsrc = (uint16_t)qb_attr_code_decode(&code_sdqcr_dqsrc, &s->sdq); -+ if (dqsrc != 0) -+ qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_SDQCR, s->sdq); -+ else -+ qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_SDQCR, 0); -+} -+ -+/***************************/ -+/* Volatile (pull) dequeue */ -+/***************************/ -+ -+/* These should be const, eventually */ -+static struct qb_attr_code code_pull_dct = QB_CODE(0, 0, 2); -+static struct qb_attr_code code_pull_dt = QB_CODE(0, 2, 2); -+static struct qb_attr_code code_pull_rls = QB_CODE(0, 4, 1); -+static struct qb_attr_code code_pull_stash = QB_CODE(0, 5, 1); -+static struct qb_attr_code code_pull_numframes = QB_CODE(0, 8, 4); -+static struct qb_attr_code code_pull_token = QB_CODE(0, 16, 8); -+static struct qb_attr_code code_pull_dqsource = QB_CODE(1, 0, 24); -+static struct qb_attr_code code_pull_rsp_lo = QB_CODE(2, 0, 32); -+ -+enum qb_pull_dt_e { -+ qb_pull_dt_channel, -+ qb_pull_dt_workqueue, -+ qb_pull_dt_framequeue -+}; -+ -+void qbman_pull_desc_clear(struct qbman_pull_desc *d) -+{ -+ memset(d, 0, sizeof(*d)); -+} -+ -+void qbman_pull_desc_set_storage(struct qbman_pull_desc *d, -+ struct dpaa2_dq *storage, -+ dma_addr_t storage_phys, -+ int stash) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ /* Squiggle the pointer 'storage' into the extra 2 words of the -+ * descriptor (which aren't copied to the hw command) */ -+ *(void **)&cl[4] = storage; -+ if (!storage) { -+ qb_attr_code_encode(&code_pull_rls, cl, 0); -+ return; -+ } -+ qb_attr_code_encode(&code_pull_rls, cl, 1); -+ qb_attr_code_encode(&code_pull_stash, cl, !!stash); -+ qb_attr_code_encode_64(&code_pull_rsp_lo, (uint64_t *)cl, storage_phys); -+} -+ -+void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, uint8_t numframes) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ BUG_ON(!numframes || (numframes > 16)); -+ qb_attr_code_encode(&code_pull_numframes, cl, -+ (uint32_t)(numframes - 1)); -+} -+ -+void qbman_pull_desc_set_token(struct qbman_pull_desc *d, uint8_t token) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_pull_token, cl, token); -+} -+ -+void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, uint32_t fqid) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_pull_dct, cl, 1); -+ qb_attr_code_encode(&code_pull_dt, cl, qb_pull_dt_framequeue); -+ qb_attr_code_encode(&code_pull_dqsource, cl, fqid); -+} -+ -+void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, uint32_t wqid, -+ enum qbman_pull_type_e dct) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_pull_dct, cl, dct); -+ qb_attr_code_encode(&code_pull_dt, cl, qb_pull_dt_workqueue); -+ qb_attr_code_encode(&code_pull_dqsource, cl, wqid); -+} -+ -+void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, uint32_t chid, -+ enum qbman_pull_type_e dct) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_pull_dct, cl, dct); -+ qb_attr_code_encode(&code_pull_dt, cl, qb_pull_dt_channel); -+ qb_attr_code_encode(&code_pull_dqsource, cl, chid); -+} -+ -+int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d) -+{ -+ uint32_t *p; -+ uint32_t *cl = qb_cl(d); -+ -+ if (!atomic_dec_and_test(&s->vdq.busy)) { -+ atomic_inc(&s->vdq.busy); -+ return -EBUSY; -+ } -+ s->vdq.storage = *(void **)&cl[4]; -+ qb_attr_code_encode(&code_pull_token, cl, 1); -+ p = qbman_cena_write_start(&s->sys, QBMAN_CENA_SWP_VDQCR); -+ word_copy(&p[1], &cl[1], 3); -+ /* Set the verb byte, have to substitute in the valid-bit */ -+ p[0] = cl[0] | s->vdq.valid_bit; -+ s->vdq.valid_bit ^= QB_VALID_BIT; -+ qbman_cena_write_complete(&s->sys, QBMAN_CENA_SWP_VDQCR, p); -+ return 0; -+} -+ -+/****************/ -+/* Polling DQRR */ -+/****************/ -+ -+static struct qb_attr_code code_dqrr_verb = QB_CODE(0, 0, 8); -+static struct qb_attr_code code_dqrr_response = QB_CODE(0, 0, 7); -+static struct qb_attr_code code_dqrr_stat = QB_CODE(0, 8, 8); -+static struct qb_attr_code code_dqrr_seqnum = QB_CODE(0, 16, 14); -+static struct qb_attr_code code_dqrr_odpid = QB_CODE(1, 0, 16); -+/* static struct qb_attr_code code_dqrr_tok = QB_CODE(1, 24, 8); */ -+static struct qb_attr_code code_dqrr_fqid = QB_CODE(2, 0, 24); -+static struct qb_attr_code code_dqrr_byte_count = QB_CODE(4, 0, 32); -+static struct qb_attr_code code_dqrr_frame_count = QB_CODE(5, 0, 24); -+static struct qb_attr_code code_dqrr_ctx_lo = QB_CODE(6, 0, 32); -+ -+#define QBMAN_RESULT_DQ 0x60 -+#define QBMAN_RESULT_FQRN 0x21 -+#define QBMAN_RESULT_FQRNI 0x22 -+#define QBMAN_RESULT_FQPN 0x24 -+#define QBMAN_RESULT_FQDAN 0x25 -+#define QBMAN_RESULT_CDAN 0x26 -+#define QBMAN_RESULT_CSCN_MEM 0x27 -+#define QBMAN_RESULT_CGCU 0x28 -+#define QBMAN_RESULT_BPSCN 0x29 -+#define QBMAN_RESULT_CSCN_WQ 0x2a -+ -+static struct qb_attr_code code_dqpi_pi = QB_CODE(0, 0, 4); -+ -+/* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry -+ * only once, so repeated calls can return a sequence of DQRR entries, without -+ * requiring they be consumed immediately or in any particular order. */ -+const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s) -+{ -+ uint32_t verb; -+ uint32_t response_verb; -+ uint32_t flags; -+ const struct dpaa2_dq *dq; -+ const uint32_t *p; -+ -+ /* Before using valid-bit to detect if something is there, we have to -+ * handle the case of the DQRR reset bug... */ -+#ifdef WORKAROUND_DQRR_RESET_BUG -+ if (unlikely(s->dqrr.reset_bug)) { -+ /* We pick up new entries by cache-inhibited producer index, -+ * which means that a non-coherent mapping would require us to -+ * invalidate and read *only* once that PI has indicated that -+ * there's an entry here. The first trip around the DQRR ring -+ * will be much less efficient than all subsequent trips around -+ * it... -+ */ -+ uint32_t dqpi = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_DQPI); -+ uint32_t pi = qb_attr_code_decode(&code_dqpi_pi, &dqpi); -+ /* there are new entries iff pi != next_idx */ -+ if (pi == s->dqrr.next_idx) -+ return NULL; -+ /* if next_idx is/was the last ring index, and 'pi' is -+ * different, we can disable the workaround as all the ring -+ * entries have now been DMA'd to so valid-bit checking is -+ * repaired. Note: this logic needs to be based on next_idx -+ * (which increments one at a time), rather than on pi (which -+ * can burst and wrap-around between our snapshots of it). -+ */ -+ if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1)) { -+ pr_debug("DEBUG: next_idx=%d, pi=%d, clear reset bug\n", -+ s->dqrr.next_idx, pi); -+ s->dqrr.reset_bug = 0; -+ } -+ qbman_cena_invalidate_prefetch(&s->sys, -+ QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); -+ } -+#endif -+ -+ dq = qbman_cena_read(&s->sys, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); -+ p = qb_cl(dq); -+ verb = qb_attr_code_decode(&code_dqrr_verb, p); -+ -+ /* If the valid-bit isn't of the expected polarity, nothing there. Note, -+ * in the DQRR reset bug workaround, we shouldn't need to skip these -+ * check, because we've already determined that a new entry is available -+ * and we've invalidated the cacheline before reading it, so the -+ * valid-bit behaviour is repaired and should tell us what we already -+ * knew from reading PI. -+ */ -+ if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) { -+ qbman_cena_invalidate_prefetch(&s->sys, -+ QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); -+ return NULL; -+ } -+ /* There's something there. Move "next_idx" attention to the next ring -+ * entry (and prefetch it) before returning what we found. */ -+ s->dqrr.next_idx++; -+ s->dqrr.next_idx &= s->dqrr.dqrr_size - 1; /* Wrap around */ -+ /* TODO: it's possible to do all this without conditionals, optimise it -+ * later. */ -+ if (!s->dqrr.next_idx) -+ s->dqrr.valid_bit ^= QB_VALID_BIT; -+ -+ /* If this is the final response to a volatile dequeue command -+ indicate that the vdq is no longer busy */ -+ flags = dpaa2_dq_flags(dq); -+ response_verb = qb_attr_code_decode(&code_dqrr_response, &verb); -+ if ((response_verb == QBMAN_RESULT_DQ) && -+ (flags & DPAA2_DQ_STAT_VOLATILE) && -+ (flags & DPAA2_DQ_STAT_EXPIRED)) -+ atomic_inc(&s->vdq.busy); -+ -+ qbman_cena_invalidate_prefetch(&s->sys, -+ QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); -+ return dq; -+} -+ -+/* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */ -+void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq) -+{ -+ qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq)); -+} -+ -+/*********************************/ -+/* Polling user-provided storage */ -+/*********************************/ -+ -+int qbman_result_has_new_result(struct qbman_swp *s, -+ const struct dpaa2_dq *dq) -+{ -+ /* To avoid converting the little-endian DQ entry to host-endian prior -+ * to us knowing whether there is a valid entry or not (and run the -+ * risk of corrupting the incoming hardware LE write), we detect in -+ * hardware endianness rather than host. This means we need a different -+ * "code" depending on whether we are BE or LE in software, which is -+ * where DQRR_TOK_OFFSET comes in... */ -+ static struct qb_attr_code code_dqrr_tok_detect = -+ QB_CODE(0, DQRR_TOK_OFFSET, 8); -+ /* The user trying to poll for a result treats "dq" as const. It is -+ * however the same address that was provided to us non-const in the -+ * first place, for directing hardware DMA to. So we can cast away the -+ * const because it is mutable from our perspective. */ -+ uint32_t *p = qb_cl((struct dpaa2_dq *)dq); -+ uint32_t token; -+ -+ token = qb_attr_code_decode(&code_dqrr_tok_detect, &p[1]); -+ if (token != 1) -+ return 0; -+ qb_attr_code_encode(&code_dqrr_tok_detect, &p[1], 0); -+ -+ /* Only now do we convert from hardware to host endianness. Also, as we -+ * are returning success, the user has promised not to call us again, so -+ * there's no risk of us converting the endianness twice... */ -+ make_le32_n(p, 16); -+ -+ /* VDQCR "no longer busy" hook - not quite the same as DQRR, because the -+ * fact "VDQCR" shows busy doesn't mean that the result we're looking at -+ * is from the same command. Eg. we may be looking at our 10th dequeue -+ * result from our first VDQCR command, yet the second dequeue command -+ * could have been kicked off already, after seeing the 1st result. Ie. -+ * the result we're looking at is not necessarily proof that we can -+ * reset "busy". We instead base the decision on whether the current -+ * result is sitting at the first 'storage' location of the busy -+ * command. */ -+ if (s->vdq.storage == dq) { -+ s->vdq.storage = NULL; -+ atomic_inc(&s->vdq.busy); -+ } -+ return 1; -+} -+ -+/********************************/ -+/* Categorising qbman_result */ -+/********************************/ -+ -+static struct qb_attr_code code_result_in_mem = -+ QB_CODE(0, QBMAN_RESULT_VERB_OFFSET_IN_MEM, 7); -+ -+static inline int __qbman_result_is_x(const struct dpaa2_dq *dq, uint32_t x) -+{ -+ const uint32_t *p = qb_cl(dq); -+ uint32_t response_verb = qb_attr_code_decode(&code_dqrr_response, p); -+ -+ return response_verb == x; -+} -+ -+static inline int __qbman_result_is_x_in_mem(const struct dpaa2_dq *dq, -+ uint32_t x) -+{ -+ const uint32_t *p = qb_cl(dq); -+ uint32_t response_verb = qb_attr_code_decode(&code_result_in_mem, p); -+ -+ return (response_verb == x); -+} -+ -+int qbman_result_is_DQ(const struct dpaa2_dq *dq) -+{ -+ return __qbman_result_is_x(dq, QBMAN_RESULT_DQ); -+} -+ -+int qbman_result_is_FQDAN(const struct dpaa2_dq *dq) -+{ -+ return __qbman_result_is_x(dq, QBMAN_RESULT_FQDAN); -+} -+ -+int qbman_result_is_CDAN(const struct dpaa2_dq *dq) -+{ -+ return __qbman_result_is_x(dq, QBMAN_RESULT_CDAN); -+} -+ -+int qbman_result_is_CSCN(const struct dpaa2_dq *dq) -+{ -+ return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_CSCN_MEM) || -+ __qbman_result_is_x(dq, QBMAN_RESULT_CSCN_WQ); -+} -+ -+int qbman_result_is_BPSCN(const struct dpaa2_dq *dq) -+{ -+ return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_BPSCN); -+} -+ -+int qbman_result_is_CGCU(const struct dpaa2_dq *dq) -+{ -+ return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_CGCU); -+} -+ -+int qbman_result_is_FQRN(const struct dpaa2_dq *dq) -+{ -+ return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_FQRN); -+} -+ -+int qbman_result_is_FQRNI(const struct dpaa2_dq *dq) -+{ -+ return __qbman_result_is_x_in_mem(dq, QBMAN_RESULT_FQRNI); -+} -+ -+int qbman_result_is_FQPN(const struct dpaa2_dq *dq) -+{ -+ return __qbman_result_is_x(dq, QBMAN_RESULT_FQPN); -+} -+ -+/*********************************/ -+/* Parsing frame dequeue results */ -+/*********************************/ -+ -+/* These APIs assume qbman_result_is_DQ() is TRUE */ -+ -+uint32_t dpaa2_dq_flags(const struct dpaa2_dq *dq) -+{ -+ const uint32_t *p = qb_cl(dq); -+ -+ return qb_attr_code_decode(&code_dqrr_stat, p); -+} -+ -+uint16_t dpaa2_dq_seqnum(const struct dpaa2_dq *dq) -+{ -+ const uint32_t *p = qb_cl(dq); -+ -+ return (uint16_t)qb_attr_code_decode(&code_dqrr_seqnum, p); -+} -+ -+uint16_t dpaa2_dq_odpid(const struct dpaa2_dq *dq) -+{ -+ const uint32_t *p = qb_cl(dq); -+ -+ return (uint16_t)qb_attr_code_decode(&code_dqrr_odpid, p); -+} -+ -+uint32_t dpaa2_dq_fqid(const struct dpaa2_dq *dq) -+{ -+ const uint32_t *p = qb_cl(dq); -+ -+ return qb_attr_code_decode(&code_dqrr_fqid, p); -+} -+ -+uint32_t dpaa2_dq_byte_count(const struct dpaa2_dq *dq) -+{ -+ const uint32_t *p = qb_cl(dq); -+ -+ return qb_attr_code_decode(&code_dqrr_byte_count, p); -+} -+ -+uint32_t dpaa2_dq_frame_count(const struct dpaa2_dq *dq) -+{ -+ const uint32_t *p = qb_cl(dq); -+ -+ return qb_attr_code_decode(&code_dqrr_frame_count, p); -+} -+ -+uint64_t dpaa2_dq_fqd_ctx(const struct dpaa2_dq *dq) -+{ -+ const uint64_t *p = (uint64_t *)qb_cl(dq); -+ -+ return qb_attr_code_decode_64(&code_dqrr_ctx_lo, p); -+} -+EXPORT_SYMBOL(dpaa2_dq_fqd_ctx); -+ -+const struct dpaa2_fd *dpaa2_dq_fd(const struct dpaa2_dq *dq) -+{ -+ const uint32_t *p = qb_cl(dq); -+ -+ return (const struct dpaa2_fd *)&p[8]; -+} -+EXPORT_SYMBOL(dpaa2_dq_fd); -+ -+/**************************************/ -+/* Parsing state-change notifications */ -+/**************************************/ -+ -+static struct qb_attr_code code_scn_state = QB_CODE(0, 16, 8); -+static struct qb_attr_code code_scn_rid = QB_CODE(1, 0, 24); -+static struct qb_attr_code code_scn_state_in_mem = -+ QB_CODE(0, SCN_STATE_OFFSET_IN_MEM, 8); -+static struct qb_attr_code code_scn_rid_in_mem = -+ QB_CODE(1, SCN_RID_OFFSET_IN_MEM, 24); -+static struct qb_attr_code code_scn_ctx_lo = QB_CODE(2, 0, 32); -+ -+uint8_t qbman_result_SCN_state(const struct dpaa2_dq *scn) -+{ -+ const uint32_t *p = qb_cl(scn); -+ -+ return (uint8_t)qb_attr_code_decode(&code_scn_state, p); -+} -+ -+uint32_t qbman_result_SCN_rid(const struct dpaa2_dq *scn) -+{ -+ const uint32_t *p = qb_cl(scn); -+ -+ return qb_attr_code_decode(&code_scn_rid, p); -+} -+ -+uint64_t qbman_result_SCN_ctx(const struct dpaa2_dq *scn) -+{ -+ const uint64_t *p = (uint64_t *)qb_cl(scn); -+ -+ return qb_attr_code_decode_64(&code_scn_ctx_lo, p); -+} -+ -+uint8_t qbman_result_SCN_state_in_mem(const struct dpaa2_dq *scn) -+{ -+ const uint32_t *p = qb_cl(scn); -+ -+ return (uint8_t)qb_attr_code_decode(&code_scn_state_in_mem, p); -+} -+ -+uint32_t qbman_result_SCN_rid_in_mem(const struct dpaa2_dq *scn) -+{ -+ const uint32_t *p = qb_cl(scn); -+ uint32_t result_rid; -+ -+ result_rid = qb_attr_code_decode(&code_scn_rid_in_mem, p); -+ return make_le24(result_rid); -+} -+ -+/*****************/ -+/* Parsing BPSCN */ -+/*****************/ -+uint16_t qbman_result_bpscn_bpid(const struct dpaa2_dq *scn) -+{ -+ return (uint16_t)qbman_result_SCN_rid_in_mem(scn) & 0x3FFF; -+} -+ -+int qbman_result_bpscn_has_free_bufs(const struct dpaa2_dq *scn) -+{ -+ return !(int)(qbman_result_SCN_state_in_mem(scn) & 0x1); -+} -+ -+int qbman_result_bpscn_is_depleted(const struct dpaa2_dq *scn) -+{ -+ return (int)(qbman_result_SCN_state_in_mem(scn) & 0x2); -+} -+ -+int qbman_result_bpscn_is_surplus(const struct dpaa2_dq *scn) -+{ -+ return (int)(qbman_result_SCN_state_in_mem(scn) & 0x4); -+} -+ -+uint64_t qbman_result_bpscn_ctx(const struct dpaa2_dq *scn) -+{ -+ return qbman_result_SCN_ctx(scn); -+} -+ -+/*****************/ -+/* Parsing CGCU */ -+/*****************/ -+uint16_t qbman_result_cgcu_cgid(const struct dpaa2_dq *scn) -+{ -+ return (uint16_t)qbman_result_SCN_rid_in_mem(scn) & 0xFFFF; -+} -+ -+uint64_t qbman_result_cgcu_icnt(const struct dpaa2_dq *scn) -+{ -+ return qbman_result_SCN_ctx(scn) & 0xFFFFFFFFFF; -+} -+ -+/******************/ -+/* Buffer release */ -+/******************/ -+ -+/* These should be const, eventually */ -+/* static struct qb_attr_code code_release_num = QB_CODE(0, 0, 3); */ -+static struct qb_attr_code code_release_set_me = QB_CODE(0, 5, 1); -+static struct qb_attr_code code_release_rcdi = QB_CODE(0, 6, 1); -+static struct qb_attr_code code_release_bpid = QB_CODE(0, 16, 16); -+ -+void qbman_release_desc_clear(struct qbman_release_desc *d) -+{ -+ uint32_t *cl; -+ -+ memset(d, 0, sizeof(*d)); -+ cl = qb_cl(d); -+ qb_attr_code_encode(&code_release_set_me, cl, 1); -+} -+ -+void qbman_release_desc_set_bpid(struct qbman_release_desc *d, uint32_t bpid) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_release_bpid, cl, bpid); -+} -+ -+void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable) -+{ -+ uint32_t *cl = qb_cl(d); -+ -+ qb_attr_code_encode(&code_release_rcdi, cl, !!enable); -+} -+ -+#define RAR_IDX(rar) ((rar) & 0x7) -+#define RAR_VB(rar) ((rar) & 0x80) -+#define RAR_SUCCESS(rar) ((rar) & 0x100) -+ -+int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d, -+ const uint64_t *buffers, unsigned int num_buffers) -+{ -+ uint32_t *p; -+ const uint32_t *cl = qb_cl(d); -+ uint32_t rar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_RAR); -+ -+ pr_debug("RAR=%08x\n", rar); -+ if (!RAR_SUCCESS(rar)) -+ return -EBUSY; -+ BUG_ON(!num_buffers || (num_buffers > 7)); -+ /* Start the release command */ -+ p = qbman_cena_write_start(&s->sys, -+ QBMAN_CENA_SWP_RCR(RAR_IDX(rar))); -+ /* Copy the caller's buffer pointers to the command */ -+ u64_to_le32_copy(&p[2], buffers, num_buffers); -+ /* Set the verb byte, have to substitute in the valid-bit and the number -+ * of buffers. */ -+ p[0] = cl[0] | RAR_VB(rar) | num_buffers; -+ qbman_cena_write_complete(&s->sys, -+ QBMAN_CENA_SWP_RCR(RAR_IDX(rar)), -+ p); -+ return 0; -+} -+ -+/*******************/ -+/* Buffer acquires */ -+/*******************/ -+ -+/* These should be const, eventually */ -+static struct qb_attr_code code_acquire_bpid = QB_CODE(0, 16, 16); -+static struct qb_attr_code code_acquire_num = QB_CODE(1, 0, 3); -+static struct qb_attr_code code_acquire_r_num = QB_CODE(1, 0, 3); -+ -+int qbman_swp_acquire(struct qbman_swp *s, uint32_t bpid, uint64_t *buffers, -+ unsigned int num_buffers) -+{ -+ uint32_t *p; -+ uint32_t verb, rslt, num; -+ -+ BUG_ON(!num_buffers || (num_buffers > 7)); -+ -+ /* Start the management command */ -+ p = qbman_swp_mc_start(s); -+ -+ if (!p) -+ return -EBUSY; -+ -+ /* Encode the caller-provided attributes */ -+ qb_attr_code_encode(&code_acquire_bpid, p, bpid); -+ qb_attr_code_encode(&code_acquire_num, p, num_buffers); -+ -+ /* Complete the management command */ -+ p = qbman_swp_mc_complete(s, p, p[0] | QBMAN_MC_ACQUIRE); -+ -+ /* Decode the outcome */ -+ verb = qb_attr_code_decode(&code_generic_verb, p); -+ rslt = qb_attr_code_decode(&code_generic_rslt, p); -+ num = qb_attr_code_decode(&code_acquire_r_num, p); -+ BUG_ON(verb != QBMAN_MC_ACQUIRE); -+ -+ /* Determine success or failure */ -+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) { -+ pr_err("Acquire buffers from BPID 0x%x failed, code=0x%02x\n", -+ bpid, rslt); -+ return -EIO; -+ } -+ BUG_ON(num > num_buffers); -+ /* Copy the acquired buffers to the caller's array */ -+ u64_from_le32_copy(buffers, &p[2], num); -+ return (int)num; -+} -+ -+/*****************/ -+/* FQ management */ -+/*****************/ -+ -+static struct qb_attr_code code_fqalt_fqid = QB_CODE(1, 0, 32); -+ -+static int qbman_swp_alt_fq_state(struct qbman_swp *s, uint32_t fqid, -+ uint8_t alt_fq_verb) -+{ -+ uint32_t *p; -+ uint32_t verb, rslt; -+ -+ /* Start the management command */ -+ p = qbman_swp_mc_start(s); -+ if (!p) -+ return -EBUSY; -+ -+ qb_attr_code_encode(&code_fqalt_fqid, p, fqid); -+ /* Complete the management command */ -+ p = qbman_swp_mc_complete(s, p, p[0] | alt_fq_verb); -+ -+ /* Decode the outcome */ -+ verb = qb_attr_code_decode(&code_generic_verb, p); -+ rslt = qb_attr_code_decode(&code_generic_rslt, p); -+ BUG_ON(verb != alt_fq_verb); -+ -+ /* Determine success or failure */ -+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) { -+ pr_err("ALT FQID %d failed: verb = 0x%08x, code = 0x%02x\n", -+ fqid, alt_fq_verb, rslt); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+int qbman_swp_fq_schedule(struct qbman_swp *s, uint32_t fqid) -+{ -+ return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_SCHEDULE); -+} -+ -+int qbman_swp_fq_force(struct qbman_swp *s, uint32_t fqid) -+{ -+ return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_FORCE); -+} -+ -+int qbman_swp_fq_xon(struct qbman_swp *s, uint32_t fqid) -+{ -+ return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XON); -+} -+ -+int qbman_swp_fq_xoff(struct qbman_swp *s, uint32_t fqid) -+{ -+ return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XOFF); -+} -+ -+/**********************/ -+/* Channel management */ -+/**********************/ -+ -+static struct qb_attr_code code_cdan_cid = QB_CODE(0, 16, 12); -+static struct qb_attr_code code_cdan_we = QB_CODE(1, 0, 8); -+static struct qb_attr_code code_cdan_en = QB_CODE(1, 8, 1); -+static struct qb_attr_code code_cdan_ctx_lo = QB_CODE(2, 0, 32); -+ -+/* Hide "ICD" for now as we don't use it, don't set it, and don't test it, so it -+ * would be irresponsible to expose it. */ -+#define CODE_CDAN_WE_EN 0x1 -+#define CODE_CDAN_WE_CTX 0x4 -+ -+static int qbman_swp_CDAN_set(struct qbman_swp *s, uint16_t channelid, -+ uint8_t we_mask, uint8_t cdan_en, -+ uint64_t ctx) -+{ -+ uint32_t *p; -+ uint32_t verb, rslt; -+ -+ /* Start the management command */ -+ p = qbman_swp_mc_start(s); -+ if (!p) -+ return -EBUSY; -+ -+ /* Encode the caller-provided attributes */ -+ qb_attr_code_encode(&code_cdan_cid, p, channelid); -+ qb_attr_code_encode(&code_cdan_we, p, we_mask); -+ qb_attr_code_encode(&code_cdan_en, p, cdan_en); -+ qb_attr_code_encode_64(&code_cdan_ctx_lo, (uint64_t *)p, ctx); -+ /* Complete the management command */ -+ p = qbman_swp_mc_complete(s, p, p[0] | QBMAN_WQCHAN_CONFIGURE); -+ -+ /* Decode the outcome */ -+ verb = qb_attr_code_decode(&code_generic_verb, p); -+ rslt = qb_attr_code_decode(&code_generic_rslt, p); -+ BUG_ON(verb != QBMAN_WQCHAN_CONFIGURE); -+ -+ /* Determine success or failure */ -+ if (unlikely(rslt != QBMAN_MC_RSLT_OK)) { -+ pr_err("CDAN cQID %d failed: code = 0x%02x\n", -+ channelid, rslt); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+int qbman_swp_CDAN_set_context(struct qbman_swp *s, uint16_t channelid, -+ uint64_t ctx) -+{ -+ return qbman_swp_CDAN_set(s, channelid, -+ CODE_CDAN_WE_CTX, -+ 0, ctx); -+} -+ -+int qbman_swp_CDAN_enable(struct qbman_swp *s, uint16_t channelid) -+{ -+ return qbman_swp_CDAN_set(s, channelid, -+ CODE_CDAN_WE_EN, -+ 1, 0); -+} -+int qbman_swp_CDAN_disable(struct qbman_swp *s, uint16_t channelid) -+{ -+ return qbman_swp_CDAN_set(s, channelid, -+ CODE_CDAN_WE_EN, -+ 0, 0); -+} -+int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s, uint16_t channelid, -+ uint64_t ctx) -+{ -+ return qbman_swp_CDAN_set(s, channelid, -+ CODE_CDAN_WE_EN | CODE_CDAN_WE_CTX, -+ 1, ctx); -+} ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/qbman_portal.h -@@ -0,0 +1,261 @@ -+/* Copyright (C) 2014 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "qbman_private.h" -+#include "fsl_qbman_portal.h" -+#include "../../include/fsl_dpaa2_fd.h" -+ -+/* All QBMan command and result structures use this "valid bit" encoding */ -+#define QB_VALID_BIT ((uint32_t)0x80) -+ -+/* Management command result codes */ -+#define QBMAN_MC_RSLT_OK 0xf0 -+ -+/* TBD: as of QBMan 4.1, DQRR will be 8 rather than 4! */ -+#define QBMAN_DQRR_SIZE 4 -+ -+/* DQRR valid-bit reset bug. See qbman_portal.c::qbman_swp_init(). */ -+#define WORKAROUND_DQRR_RESET_BUG -+ -+/* --------------------- */ -+/* portal data structure */ -+/* --------------------- */ -+ -+struct qbman_swp { -+ const struct qbman_swp_desc *desc; -+ /* The qbman_sys (ie. arch/OS-specific) support code can put anything it -+ * needs in here. */ -+ struct qbman_swp_sys sys; -+ /* Management commands */ -+ struct { -+#ifdef QBMAN_CHECKING -+ enum swp_mc_check { -+ swp_mc_can_start, /* call __qbman_swp_mc_start() */ -+ swp_mc_can_submit, /* call __qbman_swp_mc_submit() */ -+ swp_mc_can_poll, /* call __qbman_swp_mc_result() */ -+ } check; -+#endif -+ uint32_t valid_bit; /* 0x00 or 0x80 */ -+ } mc; -+ /* Push dequeues */ -+ uint32_t sdq; -+ /* Volatile dequeues */ -+ struct { -+ /* VDQCR supports a "1 deep pipeline", meaning that if you know -+ * the last-submitted command is already executing in the -+ * hardware (as evidenced by at least 1 valid dequeue result), -+ * you can write another dequeue command to the register, the -+ * hardware will start executing it as soon as the -+ * already-executing command terminates. (This minimises latency -+ * and stalls.) With that in mind, this "busy" variable refers -+ * to whether or not a command can be submitted, not whether or -+ * not a previously-submitted command is still executing. In -+ * other words, once proof is seen that the previously-submitted -+ * command is executing, "vdq" is no longer "busy". -+ */ -+ atomic_t busy; -+ uint32_t valid_bit; /* 0x00 or 0x80 */ -+ /* We need to determine when vdq is no longer busy. This depends -+ * on whether the "busy" (last-submitted) dequeue command is -+ * targeting DQRR or main-memory, and detected is based on the -+ * presence of the dequeue command's "token" showing up in -+ * dequeue entries in DQRR or main-memory (respectively). */ -+ struct dpaa2_dq *storage; /* NULL if DQRR */ -+ } vdq; -+ /* DQRR */ -+ struct { -+ uint32_t next_idx; -+ uint32_t valid_bit; -+ uint8_t dqrr_size; -+#ifdef WORKAROUND_DQRR_RESET_BUG -+ int reset_bug; -+#endif -+ } dqrr; -+}; -+ -+/* -------------------------- */ -+/* portal management commands */ -+/* -------------------------- */ -+ -+/* Different management commands all use this common base layer of code to issue -+ * commands and poll for results. The first function returns a pointer to where -+ * the caller should fill in their MC command (though they should ignore the -+ * verb byte), the second function commits merges in the caller-supplied command -+ * verb (which should not include the valid-bit) and submits the command to -+ * hardware, and the third function checks for a completed response (returns -+ * non-NULL if only if the response is complete). */ -+void *qbman_swp_mc_start(struct qbman_swp *p); -+void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint32_t cmd_verb); -+void *qbman_swp_mc_result(struct qbman_swp *p); -+ -+/* Wraps up submit + poll-for-result */ -+static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd, -+ uint32_t cmd_verb) -+{ -+ int loopvar; -+ -+ qbman_swp_mc_submit(swp, cmd, cmd_verb); -+ DBG_POLL_START(loopvar); -+ do { -+ DBG_POLL_CHECK(loopvar); -+ cmd = qbman_swp_mc_result(swp); -+ } while (!cmd); -+ return cmd; -+} -+ -+/* ------------ */ -+/* qb_attr_code */ -+/* ------------ */ -+ -+/* This struct locates a sub-field within a QBMan portal (CENA) cacheline which -+ * is either serving as a configuration command or a query result. The -+ * representation is inherently little-endian, as the indexing of the words is -+ * itself little-endian in nature and layerscape is little endian for anything -+ * that crosses a word boundary too (64-bit fields are the obvious examples). -+ */ -+struct qb_attr_code { -+ unsigned int word; /* which uint32_t[] array member encodes the field */ -+ unsigned int lsoffset; /* encoding offset from ls-bit */ -+ unsigned int width; /* encoding width. (bool must be 1.) */ -+}; -+ -+/* Some pre-defined codes */ -+extern struct qb_attr_code code_generic_verb; -+extern struct qb_attr_code code_generic_rslt; -+ -+/* Macros to define codes */ -+#define QB_CODE(a, b, c) { a, b, c} -+#define QB_CODE_NULL \ -+ QB_CODE((unsigned int)-1, (unsigned int)-1, (unsigned int)-1) -+ -+/* Rotate a code "ms", meaning that it moves from less-significant bytes to -+ * more-significant, from less-significant words to more-significant, etc. The -+ * "ls" version does the inverse, from more-significant towards -+ * less-significant. -+ */ -+static inline void qb_attr_code_rotate_ms(struct qb_attr_code *code, -+ unsigned int bits) -+{ -+ code->lsoffset += bits; -+ while (code->lsoffset > 31) { -+ code->word++; -+ code->lsoffset -= 32; -+ } -+} -+static inline void qb_attr_code_rotate_ls(struct qb_attr_code *code, -+ unsigned int bits) -+{ -+ /* Don't be fooled, this trick should work because the types are -+ * unsigned. So the case that interests the while loop (the rotate has -+ * gone too far and the word count needs to compensate for it), is -+ * manifested when lsoffset is negative. But that equates to a really -+ * large unsigned value, starting with lots of "F"s. As such, we can -+ * continue adding 32 back to it until it wraps back round above zero, -+ * to a value of 31 or less... -+ */ -+ code->lsoffset -= bits; -+ while (code->lsoffset > 31) { -+ code->word--; -+ code->lsoffset += 32; -+ } -+} -+/* Implement a loop of code rotations until 'expr' evaluates to FALSE (0). */ -+#define qb_attr_code_for_ms(code, bits, expr) \ -+ for (; expr; qb_attr_code_rotate_ms(code, bits)) -+#define qb_attr_code_for_ls(code, bits, expr) \ -+ for (; expr; qb_attr_code_rotate_ls(code, bits)) -+ -+/* decode a field from a cacheline */ -+static inline uint32_t qb_attr_code_decode(const struct qb_attr_code *code, -+ const uint32_t *cacheline) -+{ -+ return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]); -+} -+static inline uint64_t qb_attr_code_decode_64(const struct qb_attr_code *code, -+ const uint64_t *cacheline) -+{ -+ uint64_t res; -+ u64_from_le32_copy(&res, &cacheline[code->word/2], 1); -+ return res; -+} -+ -+/* encode a field to a cacheline */ -+static inline void qb_attr_code_encode(const struct qb_attr_code *code, -+ uint32_t *cacheline, uint32_t val) -+{ -+ cacheline[code->word] = -+ r32_uint32_t(code->lsoffset, code->width, cacheline[code->word]) -+ | e32_uint32_t(code->lsoffset, code->width, val); -+} -+static inline void qb_attr_code_encode_64(const struct qb_attr_code *code, -+ uint64_t *cacheline, uint64_t val) -+{ -+ u64_to_le32_copy(&cacheline[code->word/2], &val, 1); -+} -+ -+/* Small-width signed values (two's-complement) will decode into medium-width -+ * positives. (Eg. for an 8-bit signed field, which stores values from -128 to -+ * +127, a setting of -7 would appear to decode to the 32-bit unsigned value -+ * 249. Likewise -120 would decode as 136.) This function allows the caller to -+ * "re-sign" such fields to 32-bit signed. (Eg. -7, which was 249 with an 8-bit -+ * encoding, will become 0xfffffff9 if you cast the return value to uint32_t). -+ */ -+static inline int32_t qb_attr_code_makesigned(const struct qb_attr_code *code, -+ uint32_t val) -+{ -+ BUG_ON(val >= (1 << code->width)); -+ /* If the high bit was set, it was encoding a negative */ -+ if (val >= (1 << (code->width - 1))) -+ return (int32_t)0 - (int32_t)(((uint32_t)1 << code->width) - -+ val); -+ /* Otherwise, it was encoding a positive */ -+ return (int32_t)val; -+} -+ -+/* ---------------------- */ -+/* Descriptors/cachelines */ -+/* ---------------------- */ -+ -+/* To avoid needless dynamic allocation, the driver API often gives the caller -+ * a "descriptor" type that the caller can instantiate however they like. -+ * Ultimately though, it is just a cacheline of binary storage (or something -+ * smaller when it is known that the descriptor doesn't need all 64 bytes) for -+ * holding pre-formatted pieces of hardware commands. The performance-critical -+ * code can then copy these descriptors directly into hardware command -+ * registers more efficiently than trying to construct/format commands -+ * on-the-fly. The API user sees the descriptor as an array of 32-bit words in -+ * order for the compiler to know its size, but the internal details are not -+ * exposed. The following macro is used within the driver for converting *any* -+ * descriptor pointer to a usable array pointer. The use of a macro (instead of -+ * an inline) is necessary to work with different descriptor types and to work -+ * correctly with const and non-const inputs (and similarly-qualified outputs). -+ */ -+#define qb_cl(d) (&(d)->dont_manipulate_directly[0]) ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/qbman_private.h -@@ -0,0 +1,173 @@ -+/* Copyright (C) 2014 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+*/ -+ -+/* Perform extra checking */ -+#define QBMAN_CHECKING -+ -+/* To maximise the amount of logic that is common between the Linux driver and -+ * other targets (such as the embedded MC firmware), we pivot here between the -+ * inclusion of two platform-specific headers. -+ * -+ * The first, qbman_sys_decl.h, includes any and all required system headers as -+ * well as providing any definitions for the purposes of compatibility. The -+ * second, qbman_sys.h, is where platform-specific routines go. -+ * -+ * The point of the split is that the platform-independent code (including this -+ * header) may depend on platform-specific declarations, yet other -+ * platform-specific routines may depend on platform-independent definitions. -+ */ -+ -+#include "qbman_sys_decl.h" -+ -+#define QMAN_REV_4000 0x04000000 -+#define QMAN_REV_4100 0x04010000 -+#define QMAN_REV_4101 0x04010001 -+ -+/* When things go wrong, it is a convenient trick to insert a few FOO() -+ * statements in the code to trace progress. TODO: remove this once we are -+ * hacking the code less actively. -+ */ -+#define FOO() fsl_os_print("FOO: %s:%d\n", __FILE__, __LINE__) -+ -+/* Any time there is a register interface which we poll on, this provides a -+ * "break after x iterations" scheme for it. It's handy for debugging, eg. -+ * where you don't want millions of lines of log output from a polling loop -+ * that won't, because such things tend to drown out the earlier log output -+ * that might explain what caused the problem. (NB: put ";" after each macro!) -+ * TODO: we should probably remove this once we're done sanitising the -+ * simulator... -+ */ -+#define DBG_POLL_START(loopvar) (loopvar = 10) -+#define DBG_POLL_CHECK(loopvar) \ -+ do {if (!(loopvar--)) BUG_ON(1); } while (0) -+ -+/* For CCSR or portal-CINH registers that contain fields at arbitrary offsets -+ * and widths, these macro-generated encode/decode/isolate/remove inlines can -+ * be used. -+ * -+ * Eg. to "d"ecode a 14-bit field out of a register (into a "uint16_t" type), -+ * where the field is located 3 bits "up" from the least-significant bit of the -+ * register (ie. the field location within the 32-bit register corresponds to a -+ * mask of 0x0001fff8), you would do; -+ * uint16_t field = d32_uint16_t(3, 14, reg_value); -+ * -+ * Or to "e"ncode a 1-bit boolean value (input type is "int", zero is FALSE, -+ * non-zero is TRUE, so must convert all non-zero inputs to 1, hence the "!!" -+ * operator) into a register at bit location 0x00080000 (19 bits "in" from the -+ * LS bit), do; -+ * reg_value |= e32_int(19, 1, !!field); -+ * -+ * If you wish to read-modify-write a register, such that you leave the 14-bit -+ * field as-is but have all other fields set to zero, then "i"solate the 14-bit -+ * value using; -+ * reg_value = i32_uint16_t(3, 14, reg_value); -+ * -+ * Alternatively, you could "r"emove the 1-bit boolean field (setting it to -+ * zero) but leaving all other fields as-is; -+ * reg_val = r32_int(19, 1, reg_value); -+ * -+ */ -+#define MAKE_MASK32(width) (width == 32 ? 0xffffffff : \ -+ (uint32_t)((1 << width) - 1)) -+#define DECLARE_CODEC32(t) \ -+static inline uint32_t e32_##t(uint32_t lsoffset, uint32_t width, t val) \ -+{ \ -+ BUG_ON(width > (sizeof(t) * 8)); \ -+ return ((uint32_t)val & MAKE_MASK32(width)) << lsoffset; \ -+} \ -+static inline t d32_##t(uint32_t lsoffset, uint32_t width, uint32_t val) \ -+{ \ -+ BUG_ON(width > (sizeof(t) * 8)); \ -+ return (t)((val >> lsoffset) & MAKE_MASK32(width)); \ -+} \ -+static inline uint32_t i32_##t(uint32_t lsoffset, uint32_t width, \ -+ uint32_t val) \ -+{ \ -+ BUG_ON(width > (sizeof(t) * 8)); \ -+ return e32_##t(lsoffset, width, d32_##t(lsoffset, width, val)); \ -+} \ -+static inline uint32_t r32_##t(uint32_t lsoffset, uint32_t width, \ -+ uint32_t val) \ -+{ \ -+ BUG_ON(width > (sizeof(t) * 8)); \ -+ return ~(MAKE_MASK32(width) << lsoffset) & val; \ -+} -+DECLARE_CODEC32(uint32_t) -+DECLARE_CODEC32(uint16_t) -+DECLARE_CODEC32(uint8_t) -+DECLARE_CODEC32(int) -+ -+ /*********************/ -+ /* Debugging assists */ -+ /*********************/ -+ -+static inline void __hexdump(unsigned long start, unsigned long end, -+ unsigned long p, size_t sz, const unsigned char *c) -+{ -+ while (start < end) { -+ unsigned int pos = 0; -+ char buf[64]; -+ int nl = 0; -+ -+ pos += sprintf(buf + pos, "%08lx: ", start); -+ do { -+ if ((start < p) || (start >= (p + sz))) -+ pos += sprintf(buf + pos, ".."); -+ else -+ pos += sprintf(buf + pos, "%02x", *(c++)); -+ if (!(++start & 15)) { -+ buf[pos++] = '\n'; -+ nl = 1; -+ } else { -+ nl = 0; -+ if (!(start & 1)) -+ buf[pos++] = ' '; -+ if (!(start & 3)) -+ buf[pos++] = ' '; -+ } -+ } while (start & 15); -+ if (!nl) -+ buf[pos++] = '\n'; -+ buf[pos] = '\0'; -+ pr_info("%s", buf); -+ } -+} -+static inline void hexdump(const void *ptr, size_t sz) -+{ -+ unsigned long p = (unsigned long)ptr; -+ unsigned long start = p & ~(unsigned long)15; -+ unsigned long end = (p + sz + 15) & ~(unsigned long)15; -+ const unsigned char *c = ptr; -+ -+ __hexdump(start, end, p, sz, c); -+} -+ -+#include "qbman_sys.h" ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/qbman_sys.h -@@ -0,0 +1,307 @@ -+/* Copyright (C) 2014 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+/* qbman_sys_decl.h and qbman_sys.h are the two platform-specific files in the -+ * driver. They are only included via qbman_private.h, which is itself a -+ * platform-independent file and is included by all the other driver source. -+ * -+ * qbman_sys_decl.h is included prior to all other declarations and logic, and -+ * it exists to provide compatibility with any linux interfaces our -+ * single-source driver code is dependent on (eg. kmalloc). Ie. this file -+ * provides linux compatibility. -+ * -+ * This qbman_sys.h header, on the other hand, is included *after* any common -+ * and platform-neutral declarations and logic in qbman_private.h, and exists to -+ * implement any platform-specific logic of the qbman driver itself. Ie. it is -+ * *not* to provide linux compatibility. -+ */ -+ -+/* Trace the 3 different classes of read/write access to QBMan. #undef as -+ * required. */ -+#undef QBMAN_CCSR_TRACE -+#undef QBMAN_CINH_TRACE -+#undef QBMAN_CENA_TRACE -+ -+static inline void word_copy(void *d, const void *s, unsigned int cnt) -+{ -+ uint32_t *dd = d; -+ const uint32_t *ss = s; -+ -+ while (cnt--) -+ *(dd++) = *(ss++); -+} -+ -+/* Currently, the CENA support code expects each 32-bit word to be written in -+ * host order, and these are converted to hardware (little-endian) order on -+ * command submission. However, 64-bit quantities are must be written (and read) -+ * as two 32-bit words with the least-significant word first, irrespective of -+ * host endianness. */ -+static inline void u64_to_le32_copy(void *d, const uint64_t *s, -+ unsigned int cnt) -+{ -+ uint32_t *dd = d; -+ const uint32_t *ss = (const uint32_t *)s; -+ -+ while (cnt--) { -+ /* TBD: the toolchain was choking on the use of 64-bit types up -+ * until recently so this works entirely with 32-bit variables. -+ * When 64-bit types become usable again, investigate better -+ * ways of doing this. */ -+#if defined(__BIG_ENDIAN) -+ *(dd++) = ss[1]; -+ *(dd++) = ss[0]; -+ ss += 2; -+#else -+ *(dd++) = *(ss++); -+ *(dd++) = *(ss++); -+#endif -+ } -+} -+static inline void u64_from_le32_copy(uint64_t *d, const void *s, -+ unsigned int cnt) -+{ -+ const uint32_t *ss = s; -+ uint32_t *dd = (uint32_t *)d; -+ -+ while (cnt--) { -+#if defined(__BIG_ENDIAN) -+ dd[1] = *(ss++); -+ dd[0] = *(ss++); -+ dd += 2; -+#else -+ *(dd++) = *(ss++); -+ *(dd++) = *(ss++); -+#endif -+ } -+} -+ -+/* Convert a host-native 32bit value into little endian */ -+#if defined(__BIG_ENDIAN) -+static inline uint32_t make_le32(uint32_t val) -+{ -+ return ((val & 0xff) << 24) | ((val & 0xff00) << 8) | -+ ((val & 0xff0000) >> 8) | ((val & 0xff000000) >> 24); -+} -+static inline uint32_t make_le24(uint32_t val) -+{ -+ return (((val & 0xff) << 16) | (val & 0xff00) | -+ ((val & 0xff0000) >> 16)); -+} -+#else -+#define make_le32(val) (val) -+#define make_le24(val) (val) -+#endif -+static inline void make_le32_n(uint32_t *val, unsigned int num) -+{ -+ while (num--) { -+ *val = make_le32(*val); -+ val++; -+ } -+} -+ -+ /******************/ -+ /* Portal access */ -+ /******************/ -+struct qbman_swp_sys { -+ /* On GPP, the sys support for qbman_swp is here. The CENA region isi -+ * not an mmap() of the real portal registers, but an allocated -+ * place-holder, because the actual writes/reads to/from the portal are -+ * marshalled from these allocated areas using QBMan's "MC access -+ * registers". CINH accesses are atomic so there's no need for a -+ * place-holder. */ -+ void *cena; -+ void __iomem *addr_cena; -+ void __iomem *addr_cinh; -+}; -+ -+/* P_OFFSET is (ACCESS_CMD,0,12) - offset within the portal -+ * C is (ACCESS_CMD,12,1) - is inhibited? (0==CENA, 1==CINH) -+ * SWP_IDX is (ACCESS_CMD,16,10) - Software portal index -+ * P is (ACCESS_CMD,28,1) - (0==special portal, 1==any portal) -+ * T is (ACCESS_CMD,29,1) - Command type (0==READ, 1==WRITE) -+ * E is (ACCESS_CMD,31,1) - Command execute (1 to issue, poll for 0==complete) -+ */ -+ -+static inline void qbman_cinh_write(struct qbman_swp_sys *s, uint32_t offset, -+ uint32_t val) -+{ -+ -+ writel_relaxed(val, s->addr_cinh + offset); -+#ifdef QBMAN_CINH_TRACE -+ pr_info("qbman_cinh_write(%p:0x%03x) 0x%08x\n", -+ s->addr_cinh, offset, val); -+#endif -+} -+ -+static inline uint32_t qbman_cinh_read(struct qbman_swp_sys *s, uint32_t offset) -+{ -+ uint32_t reg = readl_relaxed(s->addr_cinh + offset); -+ -+#ifdef QBMAN_CINH_TRACE -+ pr_info("qbman_cinh_read(%p:0x%03x) 0x%08x\n", -+ s->addr_cinh, offset, reg); -+#endif -+ return reg; -+} -+ -+static inline void *qbman_cena_write_start(struct qbman_swp_sys *s, -+ uint32_t offset) -+{ -+ void *shadow = s->cena + offset; -+ -+#ifdef QBMAN_CENA_TRACE -+ pr_info("qbman_cena_write_start(%p:0x%03x) %p\n", -+ s->addr_cena, offset, shadow); -+#endif -+ BUG_ON(offset & 63); -+ dcbz(shadow); -+ return shadow; -+} -+ -+static inline void qbman_cena_write_complete(struct qbman_swp_sys *s, -+ uint32_t offset, void *cmd) -+{ -+ const uint32_t *shadow = cmd; -+ int loop; -+ -+#ifdef QBMAN_CENA_TRACE -+ pr_info("qbman_cena_write_complete(%p:0x%03x) %p\n", -+ s->addr_cena, offset, shadow); -+ hexdump(cmd, 64); -+#endif -+ for (loop = 15; loop >= 1; loop--) -+ writel_relaxed(shadow[loop], s->addr_cena + -+ offset + loop * 4); -+ lwsync(); -+ writel_relaxed(shadow[0], s->addr_cena + offset); -+ dcbf(s->addr_cena + offset); -+} -+ -+static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset) -+{ -+ uint32_t *shadow = s->cena + offset; -+ unsigned int loop; -+ -+#ifdef QBMAN_CENA_TRACE -+ pr_info("qbman_cena_read(%p:0x%03x) %p\n", -+ s->addr_cena, offset, shadow); -+#endif -+ -+ for (loop = 0; loop < 16; loop++) -+ shadow[loop] = readl_relaxed(s->addr_cena + offset -+ + loop * 4); -+#ifdef QBMAN_CENA_TRACE -+ hexdump(shadow, 64); -+#endif -+ return shadow; -+} -+ -+static inline void qbman_cena_invalidate_prefetch(struct qbman_swp_sys *s, -+ uint32_t offset) -+{ -+ dcivac(s->addr_cena + offset); -+ prefetch_for_load(s->addr_cena + offset); -+} -+ -+ /******************/ -+ /* Portal support */ -+ /******************/ -+ -+/* The SWP_CFG portal register is special, in that it is used by the -+ * platform-specific code rather than the platform-independent code in -+ * qbman_portal.c. So use of it is declared locally here. */ -+#define QBMAN_CINH_SWP_CFG 0xd00 -+ -+/* For MC portal use, we always configure with -+ * DQRR_MF is (SWP_CFG,20,3) - DQRR max fill (<- 0x4) -+ * EST is (SWP_CFG,16,3) - EQCR_CI stashing threshold (<- 0x0) -+ * RPM is (SWP_CFG,12,2) - RCR production notification mode (<- 0x3) -+ * DCM is (SWP_CFG,10,2) - DQRR consumption notification mode (<- 0x2) -+ * EPM is (SWP_CFG,8,2) - EQCR production notification mode (<- 0x3) -+ * SD is (SWP_CFG,5,1) - memory stashing drop enable (<- FALSE) -+ * SP is (SWP_CFG,4,1) - memory stashing priority (<- TRUE) -+ * SE is (SWP_CFG,3,1) - memory stashing enable (<- 0x0) -+ * DP is (SWP_CFG,2,1) - dequeue stashing priority (<- TRUE) -+ * DE is (SWP_CFG,1,1) - dequeue stashing enable (<- 0x0) -+ * EP is (SWP_CFG,0,1) - EQCR_CI stashing priority (<- FALSE) -+ */ -+static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn, -+ uint8_t est, uint8_t rpm, uint8_t dcm, -+ uint8_t epm, int sd, int sp, int se, -+ int dp, int de, int ep) -+{ -+ uint32_t reg; -+ -+ reg = e32_uint8_t(20, (uint32_t)(3 + (max_fill >> 3)), max_fill) | -+ e32_uint8_t(16, 3, est) | e32_uint8_t(12, 2, rpm) | -+ e32_uint8_t(10, 2, dcm) | e32_uint8_t(8, 2, epm) | -+ e32_int(5, 1, sd) | e32_int(4, 1, sp) | e32_int(3, 1, se) | -+ e32_int(2, 1, dp) | e32_int(1, 1, de) | e32_int(0, 1, ep) | -+ e32_uint8_t(14, 1, wn); -+ return reg; -+} -+ -+static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, -+ const struct qbman_swp_desc *d, -+ uint8_t dqrr_size) -+{ -+ uint32_t reg; -+ -+ s->addr_cena = d->cena_bar; -+ s->addr_cinh = d->cinh_bar; -+ s->cena = (void *)get_zeroed_page(GFP_KERNEL); -+ if (!s->cena) { -+ pr_err("Could not allocate page for cena shadow\n"); -+ return -1; -+ } -+ -+#ifdef QBMAN_CHECKING -+ /* We should never be asked to initialise for a portal that isn't in -+ * the power-on state. (Ie. don't forget to reset portals when they are -+ * decommissioned!) -+ */ -+ reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG); -+ BUG_ON(reg); -+#endif -+ reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0); -+ qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg); -+ reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG); -+ if (!reg) { -+ pr_err("The portal is not enabled!\n"); -+ kfree(s->cena); -+ return -1; -+ } -+ return 0; -+} -+ -+static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s) -+{ -+ free_page((unsigned long)s->cena); -+} ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/qbman_sys_decl.h -@@ -0,0 +1,86 @@ -+/* Copyright (C) 2014 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "fsl_qbman_base.h" -+ -+/* The platform-independent code shouldn't need endianness, except for -+ * weird/fast-path cases like qbman_result_has_token(), which needs to -+ * perform a passive and endianness-specific test on a read-only data structure -+ * very quickly. It's an exception, and this symbol is used for that case. */ -+#if defined(__BIG_ENDIAN) -+#define DQRR_TOK_OFFSET 0 -+#define QBMAN_RESULT_VERB_OFFSET_IN_MEM 24 -+#define SCN_STATE_OFFSET_IN_MEM 8 -+#define SCN_RID_OFFSET_IN_MEM 8 -+#else -+#define DQRR_TOK_OFFSET 24 -+#define QBMAN_RESULT_VERB_OFFSET_IN_MEM 0 -+#define SCN_STATE_OFFSET_IN_MEM 16 -+#define SCN_RID_OFFSET_IN_MEM 0 -+#endif -+ -+/* Similarly-named functions */ -+#define upper32(a) upper_32_bits(a) -+#define lower32(a) lower_32_bits(a) -+ -+ /****************/ -+ /* arch assists */ -+ /****************/ -+ -+#define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); } -+#define lwsync() { asm volatile("dmb st" : : : "memory"); } -+#define dcbf(p) { asm volatile("dc cvac, %0;" : : "r" (p) : "memory"); } -+#define dcivac(p) { asm volatile("dc ivac, %0" : : "r"(p) : "memory"); } -+static inline void prefetch_for_load(void *p) -+{ -+ asm volatile("prfm pldl1keep, [%0, #64]" : : "r" (p)); -+} -+static inline void prefetch_for_store(void *p) -+{ -+ asm volatile("prfm pstl1keep, [%0, #64]" : : "r" (p)); -+} ---- /dev/null -+++ b/drivers/staging/fsl-mc/bus/dpio/qbman_test.c -@@ -0,0 +1,664 @@ -+/* Copyright (C) 2014 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+ -+#include "qbman_private.h" -+#include "fsl_qbman_portal.h" -+#include "qbman_debug.h" -+#include "../../include/fsl_dpaa2_fd.h" -+ -+#define QBMAN_SWP_CENA_BASE 0x818000000 -+#define QBMAN_SWP_CINH_BASE 0x81c000000 -+ -+#define QBMAN_PORTAL_IDX 2 -+#define QBMAN_TEST_FQID 19 -+#define QBMAN_TEST_BPID 23 -+#define QBMAN_USE_QD -+#ifdef QBMAN_USE_QD -+#define QBMAN_TEST_QDID 1 -+#endif -+#define QBMAN_TEST_LFQID 0xf00010 -+ -+#define NUM_EQ_FRAME 10 -+#define NUM_DQ_FRAME 10 -+#define NUM_DQ_IN_DQRR 5 -+#define NUM_DQ_IN_MEM (NUM_DQ_FRAME - NUM_DQ_IN_DQRR) -+ -+static struct qbman_swp *swp; -+static struct qbman_eq_desc eqdesc; -+static struct qbman_pull_desc pulldesc; -+static struct qbman_release_desc releasedesc; -+static struct qbman_eq_response eq_storage[1]; -+static struct dpaa2_dq dq_storage[NUM_DQ_IN_MEM] __aligned(64); -+static dma_addr_t eq_storage_phys; -+static dma_addr_t dq_storage_phys; -+ -+/* FQ ctx attribute values for the test code. */ -+#define FQCTX_HI 0xabbaf00d -+#define FQCTX_LO 0x98765432 -+#define FQ_VFQID 0x123456 -+ -+/* Sample frame descriptor */ -+static struct qbman_fd_simple fd = { -+ .addr_lo = 0xbabaf33d, -+ .addr_hi = 0x01234567, -+ .len = 0x7777, -+ .frc = 0xdeadbeef, -+ .flc_lo = 0xcafecafe, -+ .flc_hi = 0xbeadabba -+}; -+ -+static void fd_inc(struct qbman_fd_simple *_fd) -+{ -+ _fd->addr_lo += _fd->len; -+ _fd->flc_lo += 0x100; -+ _fd->frc += 0x10; -+} -+ -+static int fd_cmp(struct qbman_fd *fda, struct qbman_fd *fdb) -+{ -+ int i; -+ -+ for (i = 0; i < 8; i++) -+ if (fda->words[i] - fdb->words[i]) -+ return 1; -+ return 0; -+} -+ -+struct qbman_fd fd_eq[NUM_EQ_FRAME]; -+struct qbman_fd fd_dq[NUM_DQ_FRAME]; -+ -+/* "Buffers" to be released (and storage for buffers to be acquired) */ -+static uint64_t rbufs[320]; -+static uint64_t abufs[320]; -+ -+static void do_enqueue(struct qbman_swp *swp) -+{ -+ int i, j, ret; -+ -+#ifdef QBMAN_USE_QD -+ pr_info("*****QBMan_test: Enqueue %d frames to QD %d\n", -+ NUM_EQ_FRAME, QBMAN_TEST_QDID); -+#else -+ pr_info("*****QBMan_test: Enqueue %d frames to FQ %d\n", -+ NUM_EQ_FRAME, QBMAN_TEST_FQID); -+#endif -+ for (i = 0; i < NUM_EQ_FRAME; i++) { -+ /*********************************/ -+ /* Prepare a enqueue descriptor */ -+ /*********************************/ -+ memset(eq_storage, 0, sizeof(eq_storage)); -+ eq_storage_phys = virt_to_phys(eq_storage); -+ qbman_eq_desc_clear(&eqdesc); -+ qbman_eq_desc_set_no_orp(&eqdesc, 0); -+ qbman_eq_desc_set_response(&eqdesc, eq_storage_phys, 0); -+ qbman_eq_desc_set_token(&eqdesc, 0x99); -+#ifdef QBMAN_USE_QD -+ /**********************************/ -+ /* Prepare a Queueing Destination */ -+ /**********************************/ -+ qbman_eq_desc_set_qd(&eqdesc, QBMAN_TEST_QDID, 0, 3); -+#else -+ qbman_eq_desc_set_fq(&eqdesc, QBMAN_TEST_FQID); -+#endif -+ -+ /******************/ -+ /* Try an enqueue */ -+ /******************/ -+ ret = qbman_swp_enqueue(swp, &eqdesc, -+ (const struct qbman_fd *)&fd); -+ BUG_ON(ret); -+ for (j = 0; j < 8; j++) -+ fd_eq[i].words[j] = *((uint32_t *)&fd + j); -+ fd_inc(&fd); -+ } -+} -+ -+static void do_push_dequeue(struct qbman_swp *swp) -+{ -+ int i, j; -+ const struct dpaa2_dq *dq_storage1; -+ const struct qbman_fd *__fd; -+ int loopvar; -+ -+ pr_info("*****QBMan_test: Start push dequeue\n"); -+ for (i = 0; i < NUM_DQ_FRAME; i++) { -+ DBG_POLL_START(loopvar); -+ do { -+ DBG_POLL_CHECK(loopvar); -+ dq_storage1 = qbman_swp_dqrr_next(swp); -+ } while (!dq_storage1); -+ if (dq_storage1) { -+ __fd = (const struct qbman_fd *) -+ dpaa2_dq_fd(dq_storage1); -+ for (j = 0; j < 8; j++) -+ fd_dq[i].words[j] = __fd->words[j]; -+ if (fd_cmp(&fd_eq[i], &fd_dq[i])) { -+ pr_info("enqueue FD is\n"); -+ hexdump(&fd_eq[i], 32); -+ pr_info("dequeue FD is\n"); -+ hexdump(&fd_dq[i], 32); -+ } -+ qbman_swp_dqrr_consume(swp, dq_storage1); -+ } else { -+ pr_info("The push dequeue fails\n"); -+ } -+ } -+} -+ -+static void do_pull_dequeue(struct qbman_swp *swp) -+{ -+ int i, j, ret; -+ const struct dpaa2_dq *dq_storage1; -+ const struct qbman_fd *__fd; -+ int loopvar; -+ -+ pr_info("*****QBMan_test: Dequeue %d frames with dq entry in DQRR\n", -+ NUM_DQ_IN_DQRR); -+ for (i = 0; i < NUM_DQ_IN_DQRR; i++) { -+ qbman_pull_desc_clear(&pulldesc); -+ qbman_pull_desc_set_storage(&pulldesc, NULL, 0, 0); -+ qbman_pull_desc_set_numframes(&pulldesc, 1); -+ qbman_pull_desc_set_fq(&pulldesc, QBMAN_TEST_FQID); -+ -+ ret = qbman_swp_pull(swp, &pulldesc); -+ BUG_ON(ret); -+ DBG_POLL_START(loopvar); -+ do { -+ DBG_POLL_CHECK(loopvar); -+ dq_storage1 = qbman_swp_dqrr_next(swp); -+ } while (!dq_storage1); -+ -+ if (dq_storage1) { -+ __fd = (const struct qbman_fd *) -+ dpaa2_dq_fd(dq_storage1); -+ for (j = 0; j < 8; j++) -+ fd_dq[i].words[j] = __fd->words[j]; -+ if (fd_cmp(&fd_eq[i], &fd_dq[i])) { -+ pr_info("enqueue FD is\n"); -+ hexdump(&fd_eq[i], 32); -+ pr_info("dequeue FD is\n"); -+ hexdump(&fd_dq[i], 32); -+ } -+ qbman_swp_dqrr_consume(swp, dq_storage1); -+ } else { -+ pr_info("Dequeue with dq entry in DQRR fails\n"); -+ } -+ } -+ -+ pr_info("*****QBMan_test: Dequeue %d frames with dq entry in memory\n", -+ NUM_DQ_IN_MEM); -+ for (i = 0; i < NUM_DQ_IN_MEM; i++) { -+ dq_storage_phys = virt_to_phys(&dq_storage[i]); -+ qbman_pull_desc_clear(&pulldesc); -+ qbman_pull_desc_set_storage(&pulldesc, &dq_storage[i], -+ dq_storage_phys, 1); -+ qbman_pull_desc_set_numframes(&pulldesc, 1); -+ qbman_pull_desc_set_fq(&pulldesc, QBMAN_TEST_FQID); -+ ret = qbman_swp_pull(swp, &pulldesc); -+ BUG_ON(ret); -+ -+ DBG_POLL_START(loopvar); -+ do { -+ DBG_POLL_CHECK(loopvar); -+ ret = qbman_result_has_new_result(swp, -+ &dq_storage[i]); -+ } while (!ret); -+ -+ if (ret) { -+ for (j = 0; j < 8; j++) -+ fd_dq[i + NUM_DQ_IN_DQRR].words[j] = -+ dq_storage[i].dont_manipulate_directly[j + 8]; -+ j = i + NUM_DQ_IN_DQRR; -+ if (fd_cmp(&fd_eq[j], &fd_dq[j])) { -+ pr_info("enqueue FD is\n"); -+ hexdump(&fd_eq[i + NUM_DQ_IN_DQRR], 32); -+ pr_info("dequeue FD is\n"); -+ hexdump(&fd_dq[i + NUM_DQ_IN_DQRR], 32); -+ hexdump(&dq_storage[i], 64); -+ } -+ } else { -+ pr_info("Dequeue with dq entry in memory fails\n"); -+ } -+ } -+} -+ -+static void release_buffer(struct qbman_swp *swp, unsigned int num) -+{ -+ int ret; -+ unsigned int i, j; -+ -+ qbman_release_desc_clear(&releasedesc); -+ qbman_release_desc_set_bpid(&releasedesc, QBMAN_TEST_BPID); -+ pr_info("*****QBMan_test: Release %d buffers to BP %d\n", -+ num, QBMAN_TEST_BPID); -+ for (i = 0; i < (num / 7 + 1); i++) { -+ j = ((num - i * 7) > 7) ? 7 : (num - i * 7); -+ ret = qbman_swp_release(swp, &releasedesc, &rbufs[i * 7], j); -+ BUG_ON(ret); -+ } -+} -+ -+static void acquire_buffer(struct qbman_swp *swp, unsigned int num) -+{ -+ int ret; -+ unsigned int i, j; -+ -+ pr_info("*****QBMan_test: Acquire %d buffers from BP %d\n", -+ num, QBMAN_TEST_BPID); -+ -+ for (i = 0; i < (num / 7 + 1); i++) { -+ j = ((num - i * 7) > 7) ? 7 : (num - i * 7); -+ ret = qbman_swp_acquire(swp, QBMAN_TEST_BPID, &abufs[i * 7], j); -+ BUG_ON(ret != j); -+ } -+} -+ -+static void buffer_pool_test(struct qbman_swp *swp) -+{ -+ struct qbman_attr info; -+ struct dpaa2_dq *bpscn_message; -+ dma_addr_t bpscn_phys; -+ uint64_t bpscn_ctx; -+ uint64_t ctx = 0xbbccddaadeadbeefull; -+ int i, ret; -+ uint32_t hw_targ; -+ -+ pr_info("*****QBMan_test: test buffer pool management\n"); -+ ret = qbman_bp_query(swp, QBMAN_TEST_BPID, &info); -+ qbman_bp_attr_get_bpscn_addr(&info, &bpscn_phys); -+ pr_info("The bpscn is %llx, info_phys is %llx\n", bpscn_phys, -+ virt_to_phys(&info)); -+ bpscn_message = phys_to_virt(bpscn_phys); -+ -+ for (i = 0; i < 320; i++) -+ rbufs[i] = 0xf00dabba01234567ull + i * 0x40; -+ -+ release_buffer(swp, 320); -+ -+ pr_info("QBMan_test: query the buffer pool\n"); -+ qbman_bp_query(swp, QBMAN_TEST_BPID, &info); -+ hexdump(&info, 64); -+ qbman_bp_attr_get_hw_targ(&info, &hw_targ); -+ pr_info("hw_targ is %d\n", hw_targ); -+ -+ /* Acquire buffers to trigger BPSCN */ -+ acquire_buffer(swp, 300); -+ /* BPSCN should be written to the memory */ -+ qbman_bp_query(swp, QBMAN_TEST_BPID, &info); -+ hexdump(&info, 64); -+ hexdump(bpscn_message, 64); -+ BUG_ON(!qbman_result_is_BPSCN(bpscn_message)); -+ /* There should be free buffers in the pool */ -+ BUG_ON(!(qbman_result_bpscn_has_free_bufs(bpscn_message))); -+ /* Buffer pool is depleted */ -+ BUG_ON(!qbman_result_bpscn_is_depleted(bpscn_message)); -+ /* The ctx should match */ -+ bpscn_ctx = qbman_result_bpscn_ctx(bpscn_message); -+ pr_info("BPSCN test: ctx %llx, bpscn_ctx %llx\n", ctx, bpscn_ctx); -+ BUG_ON(ctx != bpscn_ctx); -+ memset(bpscn_message, 0, sizeof(struct dpaa2_dq)); -+ -+ /* Re-seed the buffer pool to trigger BPSCN */ -+ release_buffer(swp, 240); -+ /* BPSCN should be written to the memory */ -+ BUG_ON(!qbman_result_is_BPSCN(bpscn_message)); -+ /* There should be free buffers in the pool */ -+ BUG_ON(!(qbman_result_bpscn_has_free_bufs(bpscn_message))); -+ /* Buffer pool is not depleted */ -+ BUG_ON(qbman_result_bpscn_is_depleted(bpscn_message)); -+ memset(bpscn_message, 0, sizeof(struct dpaa2_dq)); -+ -+ acquire_buffer(swp, 260); -+ /* BPSCN should be written to the memory */ -+ BUG_ON(!qbman_result_is_BPSCN(bpscn_message)); -+ /* There should be free buffers in the pool while BPSCN generated */ -+ BUG_ON(!(qbman_result_bpscn_has_free_bufs(bpscn_message))); -+ /* Buffer pool is depletion */ -+ BUG_ON(!qbman_result_bpscn_is_depleted(bpscn_message)); -+} -+ -+static void ceetm_test(struct qbman_swp *swp) -+{ -+ int i, j, ret; -+ -+ qbman_eq_desc_clear(&eqdesc); -+ qbman_eq_desc_set_no_orp(&eqdesc, 0); -+ qbman_eq_desc_set_fq(&eqdesc, QBMAN_TEST_LFQID); -+ pr_info("*****QBMan_test: Enqueue to LFQID %x\n", -+ QBMAN_TEST_LFQID); -+ for (i = 0; i < NUM_EQ_FRAME; i++) { -+ ret = qbman_swp_enqueue(swp, &eqdesc, -+ (const struct qbman_fd *)&fd); -+ BUG_ON(ret); -+ for (j = 0; j < 8; j++) -+ fd_eq[i].words[j] = *((uint32_t *)&fd + j); -+ fd_inc(&fd); -+ } -+} -+ -+int qbman_test(void) -+{ -+ struct qbman_swp_desc pd; -+ uint32_t reg; -+ -+ pd.cena_bar = ioremap_cache_ns(QBMAN_SWP_CENA_BASE + -+ QBMAN_PORTAL_IDX * 0x10000, 0x10000); -+ pd.cinh_bar = ioremap(QBMAN_SWP_CINH_BASE + -+ QBMAN_PORTAL_IDX * 0x10000, 0x10000); -+ -+ /* Detect whether the mc image is the test image with GPP setup */ -+ reg = readl_relaxed(pd.cena_bar + 0x4); -+ if (reg != 0xdeadbeef) { -+ pr_err("The MC image doesn't have GPP test setup, stop!\n"); -+ iounmap(pd.cena_bar); -+ iounmap(pd.cinh_bar); -+ return -1; -+ } -+ -+ pr_info("*****QBMan_test: Init QBMan SWP %d\n", QBMAN_PORTAL_IDX); -+ swp = qbman_swp_init(&pd); -+ if (!swp) { -+ iounmap(pd.cena_bar); -+ iounmap(pd.cinh_bar); -+ return -1; -+ } -+ -+ /*******************/ -+ /* Enqueue frames */ -+ /*******************/ -+ do_enqueue(swp); -+ -+ /*******************/ -+ /* Do pull dequeue */ -+ /*******************/ -+ do_pull_dequeue(swp); -+ -+ /*******************/ -+ /* Enqueue frames */ -+ /*******************/ -+ qbman_swp_push_set(swp, 0, 1); -+ qbman_swp_fq_schedule(swp, QBMAN_TEST_FQID); -+ do_enqueue(swp); -+ -+ /*******************/ -+ /* Do push dequeue */ -+ /*******************/ -+ do_push_dequeue(swp); -+ -+ /**************************/ -+ /* Test buffer pool funcs */ -+ /**************************/ -+ buffer_pool_test(swp); -+ -+ /******************/ -+ /* CEETM test */ -+ /******************/ -+ ceetm_test(swp); -+ -+ qbman_swp_finish(swp); -+ pr_info("*****QBMan_test: Kernel test Passed\n"); -+ return 0; -+} -+ -+/* user-space test-case, definitions: -+ * -+ * 1 portal only, using portal index 3. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define QBMAN_TEST_US_SWP 3 /* portal index for user space */ -+ -+#define QBMAN_TEST_MAGIC 'q' -+struct qbman_test_swp_ioctl { -+ unsigned long portal1_cinh; -+ unsigned long portal1_cena; -+}; -+struct qbman_test_dma_ioctl { -+ unsigned long ptr; -+ uint64_t phys_addr; -+}; -+ -+struct qbman_test_priv { -+ int has_swp_map; -+ int has_dma_map; -+ unsigned long pgoff; -+}; -+ -+#define QBMAN_TEST_SWP_MAP \ -+ _IOR(QBMAN_TEST_MAGIC, 0x01, struct qbman_test_swp_ioctl) -+#define QBMAN_TEST_SWP_UNMAP \ -+ _IOR(QBMAN_TEST_MAGIC, 0x02, struct qbman_test_swp_ioctl) -+#define QBMAN_TEST_DMA_MAP \ -+ _IOR(QBMAN_TEST_MAGIC, 0x03, struct qbman_test_dma_ioctl) -+#define QBMAN_TEST_DMA_UNMAP \ -+ _IOR(QBMAN_TEST_MAGIC, 0x04, struct qbman_test_dma_ioctl) -+ -+#define TEST_PORTAL1_CENA_PGOFF ((QBMAN_SWP_CENA_BASE + QBMAN_TEST_US_SWP * \ -+ 0x10000) >> PAGE_SHIFT) -+#define TEST_PORTAL1_CINH_PGOFF ((QBMAN_SWP_CINH_BASE + QBMAN_TEST_US_SWP * \ -+ 0x10000) >> PAGE_SHIFT) -+ -+static int qbman_test_open(struct inode *inode, struct file *filp) -+{ -+ struct qbman_test_priv *priv; -+ -+ priv = kmalloc(sizeof(struct qbman_test_priv), GFP_KERNEL); -+ if (!priv) -+ return -EIO; -+ filp->private_data = priv; -+ priv->has_swp_map = 0; -+ priv->has_dma_map = 0; -+ priv->pgoff = 0; -+ return 0; -+} -+ -+static int qbman_test_mmap(struct file *filp, struct vm_area_struct *vma) -+{ -+ int ret; -+ struct qbman_test_priv *priv = filp->private_data; -+ -+ BUG_ON(!priv); -+ -+ if (vma->vm_pgoff == TEST_PORTAL1_CINH_PGOFF) -+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); -+ else if (vma->vm_pgoff == TEST_PORTAL1_CENA_PGOFF) -+ vma->vm_page_prot = pgprot_cached_ns(vma->vm_page_prot); -+ else if (vma->vm_pgoff == priv->pgoff) -+ vma->vm_page_prot = pgprot_cached(vma->vm_page_prot); -+ else { -+ pr_err("Damn, unrecognised pg_off!!\n"); -+ return -EINVAL; -+ } -+ ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, -+ vma->vm_end - vma->vm_start, -+ vma->vm_page_prot); -+ return ret; -+} -+ -+static long qbman_test_ioctl(struct file *fp, unsigned int cmd, -+ unsigned long arg) -+{ -+ void __user *a = (void __user *)arg; -+ unsigned long longret, populate; -+ int ret = 0; -+ struct qbman_test_priv *priv = fp->private_data; -+ -+ BUG_ON(!priv); -+ -+ switch (cmd) { -+ case QBMAN_TEST_SWP_MAP: -+ { -+ struct qbman_test_swp_ioctl params; -+ -+ if (priv->has_swp_map) -+ return -EINVAL; -+ down_write(¤t->mm->mmap_sem); -+ /* Map portal1 CINH */ -+ longret = do_mmap_pgoff(fp, PAGE_SIZE, 0x10000, -+ PROT_READ | PROT_WRITE, MAP_SHARED, -+ TEST_PORTAL1_CINH_PGOFF, &populate); -+ if (longret & ~PAGE_MASK) { -+ ret = (int)longret; -+ goto out; -+ } -+ params.portal1_cinh = longret; -+ /* Map portal1 CENA */ -+ longret = do_mmap_pgoff(fp, PAGE_SIZE, 0x10000, -+ PROT_READ | PROT_WRITE, MAP_SHARED, -+ TEST_PORTAL1_CENA_PGOFF, &populate); -+ if (longret & ~PAGE_MASK) { -+ ret = (int)longret; -+ goto out; -+ } -+ params.portal1_cena = longret; -+ priv->has_swp_map = 1; -+out: -+ up_write(¤t->mm->mmap_sem); -+ if (!ret && copy_to_user(a, ¶ms, sizeof(params))) -+ return -EFAULT; -+ return ret; -+ } -+ case QBMAN_TEST_SWP_UNMAP: -+ { -+ struct qbman_test_swp_ioctl params; -+ -+ if (!priv->has_swp_map) -+ return -EINVAL; -+ -+ if (copy_from_user(¶ms, a, sizeof(params))) -+ return -EFAULT; -+ down_write(¤t->mm->mmap_sem); -+ do_munmap(current->mm, params.portal1_cena, 0x10000); -+ do_munmap(current->mm, params.portal1_cinh, 0x10000); -+ up_write(¤t->mm->mmap_sem); -+ priv->has_swp_map = 0; -+ return 0; -+ } -+ case QBMAN_TEST_DMA_MAP: -+ { -+ struct qbman_test_dma_ioctl params; -+ void *vaddr; -+ -+ if (priv->has_dma_map) -+ return -EINVAL; -+ vaddr = (void *)get_zeroed_page(GFP_KERNEL); -+ params.phys_addr = virt_to_phys(vaddr); -+ priv->pgoff = (unsigned long)params.phys_addr >> PAGE_SHIFT; -+ down_write(¤t->mm->mmap_sem); -+ longret = do_mmap_pgoff(fp, PAGE_SIZE, PAGE_SIZE, -+ PROT_READ | PROT_WRITE, MAP_SHARED, -+ priv->pgoff, &populate); -+ if (longret & ~PAGE_MASK) { -+ ret = (int)longret; -+ return ret; -+ } -+ params.ptr = longret; -+ priv->has_dma_map = 1; -+ up_write(¤t->mm->mmap_sem); -+ if (copy_to_user(a, ¶ms, sizeof(params))) -+ return -EFAULT; -+ return 0; -+ } -+ case QBMAN_TEST_DMA_UNMAP: -+ { -+ struct qbman_test_dma_ioctl params; -+ -+ if (!priv->has_dma_map) -+ return -EINVAL; -+ if (copy_from_user(¶ms, a, sizeof(params))) -+ return -EFAULT; -+ down_write(¤t->mm->mmap_sem); -+ do_munmap(current->mm, params.ptr, PAGE_SIZE); -+ up_write(¤t->mm->mmap_sem); -+ free_page((unsigned long)phys_to_virt(params.phys_addr)); -+ priv->has_dma_map = 0; -+ return 0; -+ } -+ default: -+ pr_err("Bad ioctl cmd!\n"); -+ } -+ return -EINVAL; -+} -+ -+static const struct file_operations qbman_fops = { -+ .open = qbman_test_open, -+ .mmap = qbman_test_mmap, -+ .unlocked_ioctl = qbman_test_ioctl -+}; -+ -+static struct miscdevice qbman_miscdev = { -+ .name = "qbman-test", -+ .fops = &qbman_fops, -+ .minor = MISC_DYNAMIC_MINOR, -+}; -+ -+static int qbman_miscdev_init; -+ -+static int test_init(void) -+{ -+ int ret = qbman_test(); -+ -+ if (!ret) { -+ /* MC image supports the test cases, so instantiate the -+ * character devic that the user-space test case will use to do -+ * its memory mappings. */ -+ ret = misc_register(&qbman_miscdev); -+ if (ret) { -+ pr_err("qbman-test: failed to register misc device\n"); -+ return ret; -+ } -+ pr_info("qbman-test: misc device registered!\n"); -+ qbman_miscdev_init = 1; -+ } -+ return 0; -+} -+ -+static void test_exit(void) -+{ -+ if (qbman_miscdev_init) { -+ misc_deregister(&qbman_miscdev); -+ qbman_miscdev_init = 0; -+ } -+} -+ -+module_init(test_init); -+module_exit(test_exit); ---- /dev/null -+++ b/drivers/staging/fsl-mc/include/fsl_dpaa2_fd.h -@@ -0,0 +1,774 @@ -+/* Copyright 2014 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef __FSL_DPAA2_FD_H -+#define __FSL_DPAA2_FD_H -+ -+/** -+ * DOC: DPAA2 FD - Frame Descriptor APIs for DPAA2 -+ * -+ * Frame Descriptors (FDs) are used to describe frame data in the DPAA2. -+ * Frames can be enqueued and dequeued to Frame Queues which are consumed -+ * by the various DPAA accelerators (WRIOP, SEC, PME, DCE) -+ * -+ * There are three types of frames: Single, Scatter Gather and Frame Lists. -+ * -+ * The set of APIs in this file must be used to create, manipulate and -+ * query Frame Descriptor. -+ * -+ */ -+ -+/** -+ * struct dpaa2_fd - Place-holder for FDs. -+ * @words: for easier/faster copying the whole FD structure. -+ * @addr_lo: the lower 32 bits of the address in FD. -+ * @addr_hi: the upper 32 bits of the address in FD. -+ * @len: the length field in FD. -+ * @bpid_offset: represent the bpid and offset fields in FD -+ * @frc: frame context -+ * @ctrl: the 32bit control bits including dd, sc,... va, err. -+ * @flc_lo: the lower 32bit of flow context. -+ * @flc_hi: the upper 32bits of flow context. -+ * -+ * This structure represents the basic Frame Descriptor used in the system. -+ * We represent it via the simplest form that we need for now. Different -+ * overlays may be needed to support different options, etc. (It is impractical -+ * to define One True Struct, because the resulting encoding routines (lots of -+ * read-modify-writes) would be worst-case performance whether or not -+ * circumstances required them.) -+ */ -+struct dpaa2_fd { -+ union { -+ u32 words[8]; -+ struct dpaa2_fd_simple { -+ u32 addr_lo; -+ u32 addr_hi; -+ u32 len; -+ /* offset in the MS 16 bits, BPID in the LS 16 bits */ -+ u32 bpid_offset; -+ u32 frc; /* frame context */ -+ /* "err", "va", "cbmt", "asal", [...] */ -+ u32 ctrl; -+ /* flow context */ -+ u32 flc_lo; -+ u32 flc_hi; -+ } simple; -+ }; -+}; -+ -+enum dpaa2_fd_format { -+ dpaa2_fd_single = 0, -+ dpaa2_fd_list, -+ dpaa2_fd_sg -+}; -+ -+/* Accessors for SG entry fields -+ * -+ * These setters and getters assume little endian format. For converting -+ * between LE and cpu endianness, the specific conversion functions must be -+ * called before the SGE contents are accessed by the core (on Rx), -+ * respectively before the SG table is sent to hardware (on Tx) -+ */ -+ -+/** -+ * dpaa2_fd_get_addr() - get the addr field of frame descriptor -+ * @fd: the given frame descriptor. -+ * -+ * Return the address in the frame descriptor. -+ */ -+static inline dma_addr_t dpaa2_fd_get_addr(const struct dpaa2_fd *fd) -+{ -+ return (dma_addr_t)((((uint64_t)fd->simple.addr_hi) << 32) -+ + fd->simple.addr_lo); -+} -+ -+/** -+ * dpaa2_fd_set_addr() - Set the addr field of frame descriptor -+ * @fd: the given frame descriptor. -+ * @addr: the address needs to be set in frame descriptor. -+ */ -+static inline void dpaa2_fd_set_addr(struct dpaa2_fd *fd, dma_addr_t addr) -+{ -+ fd->simple.addr_hi = upper_32_bits(addr); -+ fd->simple.addr_lo = lower_32_bits(addr); -+} -+ -+/** -+ * dpaa2_fd_get_frc() - Get the frame context in the frame descriptor -+ * @fd: the given frame descriptor. -+ * -+ * Return the frame context field in the frame descriptor. -+ */ -+static inline u32 dpaa2_fd_get_frc(const struct dpaa2_fd *fd) -+{ -+ return fd->simple.frc; -+} -+ -+/** -+ * dpaa2_fd_set_frc() - Set the frame context in the frame descriptor -+ * @fd: the given frame descriptor. -+ * @frc: the frame context needs to be set in frame descriptor. -+ */ -+static inline void dpaa2_fd_set_frc(struct dpaa2_fd *fd, u32 frc) -+{ -+ fd->simple.frc = frc; -+} -+ -+/** -+ * dpaa2_fd_get_flc() - Get the flow context in the frame descriptor -+ * @fd: the given frame descriptor. -+ * -+ * Return the flow context in the frame descriptor. -+ */ -+static inline dma_addr_t dpaa2_fd_get_flc(const struct dpaa2_fd *fd) -+{ -+ return (dma_addr_t)((((uint64_t)fd->simple.flc_hi) << 32) + -+ fd->simple.flc_lo); -+} -+ -+/** -+ * dpaa2_fd_set_flc() - Set the flow context field of frame descriptor -+ * @fd: the given frame descriptor. -+ * @flc_addr: the flow context needs to be set in frame descriptor. -+ */ -+static inline void dpaa2_fd_set_flc(struct dpaa2_fd *fd, dma_addr_t flc_addr) -+{ -+ fd->simple.flc_hi = upper_32_bits(flc_addr); -+ fd->simple.flc_lo = lower_32_bits(flc_addr); -+} -+ -+/** -+ * dpaa2_fd_get_len() - Get the length in the frame descriptor -+ * @fd: the given frame descriptor. -+ * -+ * Return the length field in the frame descriptor. -+ */ -+static inline u32 dpaa2_fd_get_len(const struct dpaa2_fd *fd) -+{ -+ return fd->simple.len; -+} -+ -+/** -+ * dpaa2_fd_set_len() - Set the length field of frame descriptor -+ * @fd: the given frame descriptor. -+ * @len: the length needs to be set in frame descriptor. -+ */ -+static inline void dpaa2_fd_set_len(struct dpaa2_fd *fd, u32 len) -+{ -+ fd->simple.len = len; -+} -+ -+/** -+ * dpaa2_fd_get_offset() - Get the offset field in the frame descriptor -+ * @fd: the given frame descriptor. -+ * -+ * Return the offset. -+ */ -+static inline uint16_t dpaa2_fd_get_offset(const struct dpaa2_fd *fd) -+{ -+ return (uint16_t)(fd->simple.bpid_offset >> 16) & 0x0FFF; -+} -+ -+/** -+ * dpaa2_fd_set_offset() - Set the offset field of frame descriptor -+ * -+ * @fd: the given frame descriptor. -+ * @offset: the offset needs to be set in frame descriptor. -+ */ -+static inline void dpaa2_fd_set_offset(struct dpaa2_fd *fd, uint16_t offset) -+{ -+ fd->simple.bpid_offset &= 0xF000FFFF; -+ fd->simple.bpid_offset |= (u32)offset << 16; -+} -+ -+/** -+ * dpaa2_fd_get_format() - Get the format field in the frame descriptor -+ * @fd: the given frame descriptor. -+ * -+ * Return the format. -+ */ -+static inline enum dpaa2_fd_format dpaa2_fd_get_format( -+ const struct dpaa2_fd *fd) -+{ -+ return (enum dpaa2_fd_format)((fd->simple.bpid_offset >> 28) & 0x3); -+} -+ -+/** -+ * dpaa2_fd_set_format() - Set the format field of frame descriptor -+ * -+ * @fd: the given frame descriptor. -+ * @format: the format needs to be set in frame descriptor. -+ */ -+static inline void dpaa2_fd_set_format(struct dpaa2_fd *fd, -+ enum dpaa2_fd_format format) -+{ -+ fd->simple.bpid_offset &= 0xCFFFFFFF; -+ fd->simple.bpid_offset |= (u32)format << 28; -+} -+ -+/** -+ * dpaa2_fd_get_bpid() - Get the bpid field in the frame descriptor -+ * @fd: the given frame descriptor. -+ * -+ * Return the bpid. -+ */ -+static inline uint16_t dpaa2_fd_get_bpid(const struct dpaa2_fd *fd) -+{ -+ return (uint16_t)(fd->simple.bpid_offset & 0xFFFF); -+} -+ -+/** -+ * dpaa2_fd_set_bpid() - Set the bpid field of frame descriptor -+ * -+ * @fd: the given frame descriptor. -+ * @bpid: the bpid needs to be set in frame descriptor. -+ */ -+static inline void dpaa2_fd_set_bpid(struct dpaa2_fd *fd, uint16_t bpid) -+{ -+ fd->simple.bpid_offset &= 0xFFFF0000; -+ fd->simple.bpid_offset |= (u32)bpid; -+} -+ -+/** -+ * struct dpaa2_sg_entry - the scatter-gathering structure -+ * @addr_lo: the lower 32bit of address -+ * @addr_hi: the upper 32bit of address -+ * @len: the length in this sg entry. -+ * @bpid_offset: offset in the MS 16 bits, BPID in the LS 16 bits. -+ */ -+struct dpaa2_sg_entry { -+ u32 addr_lo; -+ u32 addr_hi; -+ u32 len; -+ u32 bpid_offset; -+}; -+ -+enum dpaa2_sg_format { -+ dpaa2_sg_single = 0, -+ dpaa2_sg_frame_data, -+ dpaa2_sg_sgt_ext -+}; -+ -+/** -+ * dpaa2_sg_get_addr() - Get the address from SG entry -+ * @sg: the given scatter-gathering object. -+ * -+ * Return the address. -+ */ -+static inline dma_addr_t dpaa2_sg_get_addr(const struct dpaa2_sg_entry *sg) -+{ -+ return (dma_addr_t)((((u64)sg->addr_hi) << 32) + sg->addr_lo); -+} -+ -+/** -+ * dpaa2_sg_set_addr() - Set the address in SG entry -+ * @sg: the given scatter-gathering object. -+ * @addr: the address to be set. -+ */ -+static inline void dpaa2_sg_set_addr(struct dpaa2_sg_entry *sg, dma_addr_t addr) -+{ -+ sg->addr_hi = upper_32_bits(addr); -+ sg->addr_lo = lower_32_bits(addr); -+} -+ -+ -+static inline bool dpaa2_sg_short_len(const struct dpaa2_sg_entry *sg) -+{ -+ return (sg->bpid_offset >> 30) & 0x1; -+} -+ -+/** -+ * dpaa2_sg_get_len() - Get the length in SG entry -+ * @sg: the given scatter-gathering object. -+ * -+ * Return the length. -+ */ -+static inline u32 dpaa2_sg_get_len(const struct dpaa2_sg_entry *sg) -+{ -+ if (dpaa2_sg_short_len(sg)) -+ return sg->len & 0x1FFFF; -+ return sg->len; -+} -+ -+/** -+ * dpaa2_sg_set_len() - Set the length in SG entry -+ * @sg: the given scatter-gathering object. -+ * @len: the length to be set. -+ */ -+static inline void dpaa2_sg_set_len(struct dpaa2_sg_entry *sg, u32 len) -+{ -+ sg->len = len; -+} -+ -+/** -+ * dpaa2_sg_get_offset() - Get the offset in SG entry -+ * @sg: the given scatter-gathering object. -+ * -+ * Return the offset. -+ */ -+static inline u16 dpaa2_sg_get_offset(const struct dpaa2_sg_entry *sg) -+{ -+ return (u16)(sg->bpid_offset >> 16) & 0x0FFF; -+} -+ -+/** -+ * dpaa2_sg_set_offset() - Set the offset in SG entry -+ * @sg: the given scatter-gathering object. -+ * @offset: the offset to be set. -+ */ -+static inline void dpaa2_sg_set_offset(struct dpaa2_sg_entry *sg, -+ u16 offset) -+{ -+ sg->bpid_offset &= 0xF000FFFF; -+ sg->bpid_offset |= (u32)offset << 16; -+} -+ -+/** -+ * dpaa2_sg_get_format() - Get the SG format in SG entry -+ * @sg: the given scatter-gathering object. -+ * -+ * Return the format. -+ */ -+static inline enum dpaa2_sg_format -+ dpaa2_sg_get_format(const struct dpaa2_sg_entry *sg) -+{ -+ return (enum dpaa2_sg_format)((sg->bpid_offset >> 28) & 0x3); -+} -+ -+/** -+ * dpaa2_sg_set_format() - Set the SG format in SG entry -+ * @sg: the given scatter-gathering object. -+ * @format: the format to be set. -+ */ -+static inline void dpaa2_sg_set_format(struct dpaa2_sg_entry *sg, -+ enum dpaa2_sg_format format) -+{ -+ sg->bpid_offset &= 0xCFFFFFFF; -+ sg->bpid_offset |= (u32)format << 28; -+} -+ -+/** -+ * dpaa2_sg_get_bpid() - Get the buffer pool id in SG entry -+ * @sg: the given scatter-gathering object. -+ * -+ * Return the bpid. -+ */ -+static inline u16 dpaa2_sg_get_bpid(const struct dpaa2_sg_entry *sg) -+{ -+ return (u16)(sg->bpid_offset & 0x3FFF); -+} -+ -+/** -+ * dpaa2_sg_set_bpid() - Set the buffer pool id in SG entry -+ * @sg: the given scatter-gathering object. -+ * @bpid: the bpid to be set. -+ */ -+static inline void dpaa2_sg_set_bpid(struct dpaa2_sg_entry *sg, u16 bpid) -+{ -+ sg->bpid_offset &= 0xFFFFC000; -+ sg->bpid_offset |= (u32)bpid; -+} -+ -+/** -+ * dpaa2_sg_is_final() - Check final bit in SG entry -+ * @sg: the given scatter-gathering object. -+ * -+ * Return bool. -+ */ -+static inline bool dpaa2_sg_is_final(const struct dpaa2_sg_entry *sg) -+{ -+ return !!(sg->bpid_offset >> 31); -+} -+ -+/** -+ * dpaa2_sg_set_final() - Set the final bit in SG entry -+ * @sg: the given scatter-gathering object. -+ * @final: the final boolean to be set. -+ */ -+static inline void dpaa2_sg_set_final(struct dpaa2_sg_entry *sg, bool final) -+{ -+ sg->bpid_offset &= 0x7FFFFFFF; -+ sg->bpid_offset |= (u32)final << 31; -+} -+ -+/* Endianness conversion helper functions -+ * The accelerator drivers which construct / read scatter gather entries -+ * need to call these in order to account for endianness mismatches between -+ * hardware and cpu -+ */ -+#ifdef __BIG_ENDIAN -+/** -+ * dpaa2_sg_cpu_to_le() - convert scatter gather entry from native cpu -+ * format little endian format. -+ * @sg: the given scatter gather entry. -+ */ -+static inline void dpaa2_sg_cpu_to_le(struct dpaa2_sg_entry *sg) -+{ -+ uint32_t *p = (uint32_t *)sg; -+ int i; -+ -+ for (i = 0; i < sizeof(*sg) / sizeof(u32); i++) -+ cpu_to_le32s(p++); -+} -+ -+/** -+ * dpaa2_sg_le_to_cpu() - convert scatter gather entry from little endian -+ * format to native cpu format. -+ * @sg: the given scatter gather entry. -+ */ -+static inline void dpaa2_sg_le_to_cpu(struct dpaa2_sg_entry *sg) -+{ -+ uint32_t *p = (uint32_t *)sg; -+ int i; -+ -+ for (i = 0; i < sizeof(*sg) / sizeof(u32); i++) -+ le32_to_cpus(p++); -+} -+#else -+#define dpaa2_sg_cpu_to_le(sg) -+#define dpaa2_sg_le_to_cpu(sg) -+#endif /* __BIG_ENDIAN */ -+ -+ -+/** -+ * struct dpaa2_fl_entry - structure for frame list entry. -+ * @addr_lo: the lower 32bit of address -+ * @addr_hi: the upper 32bit of address -+ * @len: the length in this sg entry. -+ * @bpid_offset: offset in the MS 16 bits, BPID in the LS 16 bits. -+ * @frc: frame context -+ * @ctrl: the 32bit control bits including dd, sc,... va, err. -+ * @flc_lo: the lower 32bit of flow context. -+ * @flc_hi: the upper 32bits of flow context. -+ * -+ * Frame List Entry (FLE) -+ * Identical to dpaa2_fd.simple layout, but some bits are different -+ */ -+struct dpaa2_fl_entry { -+ u32 addr_lo; -+ u32 addr_hi; -+ u32 len; -+ u32 bpid_offset; -+ u32 frc; -+ u32 ctrl; -+ u32 flc_lo; -+ u32 flc_hi; -+}; -+ -+enum dpaa2_fl_format { -+ dpaa2_fl_single = 0, -+ dpaa2_fl_res, -+ dpaa2_fl_sg -+}; -+ -+/** -+ * dpaa2_fl_get_addr() - Get address in the frame list entry -+ * @fle: the given frame list entry. -+ * -+ * Return address for the get function. -+ */ -+static inline dma_addr_t dpaa2_fl_get_addr(const struct dpaa2_fl_entry *fle) -+{ -+ return (dma_addr_t)((((uint64_t)fle->addr_hi) << 32) + fle->addr_lo); -+} -+ -+/** -+ * dpaa2_fl_set_addr() - Set the address in the frame list entry -+ * @fle: the given frame list entry. -+ * @addr: the address needs to be set. -+ * -+ */ -+static inline void dpaa2_fl_set_addr(struct dpaa2_fl_entry *fle, -+ dma_addr_t addr) -+{ -+ fle->addr_hi = upper_32_bits(addr); -+ fle->addr_lo = lower_32_bits(addr); -+} -+ -+/** -+ * dpaa2_fl_get_flc() - Get the flow context in the frame list entry -+ * @fle: the given frame list entry. -+ * -+ * Return flow context for the get function. -+ */ -+static inline dma_addr_t dpaa2_fl_get_flc(const struct dpaa2_fl_entry *fle) -+{ -+ return (dma_addr_t)((((uint64_t)fle->flc_hi) << 32) + fle->flc_lo); -+} -+ -+/** -+ * dpaa2_fl_set_flc() - Set the flow context in the frame list entry -+ * @fle: the given frame list entry. -+ * @flc_addr: the flow context address needs to be set. -+ * -+ */ -+static inline void dpaa2_fl_set_flc(struct dpaa2_fl_entry *fle, -+ dma_addr_t flc_addr) -+{ -+ fle->flc_hi = upper_32_bits(flc_addr); -+ fle->flc_lo = lower_32_bits(flc_addr); -+} -+ -+/** -+ * dpaa2_fl_get_len() - Get the length in the frame list entry -+ * @fle: the given frame list entry. -+ * -+ * Return length for the get function. -+ */ -+static inline u32 dpaa2_fl_get_len(const struct dpaa2_fl_entry *fle) -+{ -+ return fle->len; -+} -+ -+/** -+ * dpaa2_fl_set_len() - Set the length in the frame list entry -+ * @fle: the given frame list entry. -+ * @len: the length needs to be set. -+ * -+ */ -+static inline void dpaa2_fl_set_len(struct dpaa2_fl_entry *fle, u32 len) -+{ -+ fle->len = len; -+} -+ -+/** -+ * dpaa2_fl_get_offset() - Get/Set the offset in the frame list entry -+ * @fle: the given frame list entry. -+ * -+ * Return offset for the get function. -+ */ -+static inline uint16_t dpaa2_fl_get_offset(const struct dpaa2_fl_entry *fle) -+{ -+ return (uint16_t)(fle->bpid_offset >> 16) & 0x0FFF; -+} -+ -+/** -+ * dpaa2_fl_set_offset() - Set the offset in the frame list entry -+ * @fle: the given frame list entry. -+ * @offset: the offset needs to be set. -+ * -+ */ -+static inline void dpaa2_fl_set_offset(struct dpaa2_fl_entry *fle, -+ uint16_t offset) -+{ -+ fle->bpid_offset &= 0xF000FFFF; -+ fle->bpid_offset |= (u32)(offset & 0x0FFF) << 16; -+} -+ -+/** -+ * dpaa2_fl_get_format() - Get the format in the frame list entry -+ * @fle: the given frame list entry. -+ * -+ * Return frame list format for the get function. -+ */ -+static inline enum dpaa2_fl_format dpaa2_fl_get_format( -+ const struct dpaa2_fl_entry *fle) -+{ -+ return (enum dpaa2_fl_format)((fle->bpid_offset >> 28) & 0x3); -+} -+ -+/** -+ * dpaa2_fl_set_format() - Set the format in the frame list entry -+ * @fle: the given frame list entry. -+ * @format: the frame list format needs to be set. -+ * -+ */ -+static inline void dpaa2_fl_set_format(struct dpaa2_fl_entry *fle, -+ enum dpaa2_fl_format format) -+{ -+ fle->bpid_offset &= 0xCFFFFFFF; -+ fle->bpid_offset |= (u32)(format & 0x3) << 28; -+} -+ -+/** -+ * dpaa2_fl_get_bpid() - Get the buffer pool id in the frame list entry -+ * @fle: the given frame list entry. -+ * -+ * Return bpid for the get function. -+ */ -+static inline uint16_t dpaa2_fl_get_bpid(const struct dpaa2_fl_entry *fle) -+{ -+ return (uint16_t)(fle->bpid_offset & 0x3FFF); -+} -+ -+/** -+ * dpaa2_fl_set_bpid() - Set the buffer pool id in the frame list entry -+ * @fle: the given frame list entry. -+ * @bpid: the buffer pool id needs to be set. -+ * -+ */ -+static inline void dpaa2_fl_set_bpid(struct dpaa2_fl_entry *fle, uint16_t bpid) -+{ -+ fle->bpid_offset &= 0xFFFFC000; -+ fle->bpid_offset |= (u32)bpid; -+} -+ -+/** dpaa2_fl_is_final() - check the final bit is set or not in the frame list. -+ * @fle: the given frame list entry. -+ * -+ * Return final bit settting. -+ */ -+static inline bool dpaa2_fl_is_final(const struct dpaa2_fl_entry *fle) -+{ -+ return !!(fle->bpid_offset >> 31); -+} -+ -+/** -+ * dpaa2_fl_set_final() - Set the final bit in the frame list entry -+ * @fle: the given frame list entry. -+ * @final: the final bit needs to be set. -+ * -+ */ -+static inline void dpaa2_fl_set_final(struct dpaa2_fl_entry *fle, bool final) -+{ -+ fle->bpid_offset &= 0x7FFFFFFF; -+ fle->bpid_offset |= (u32)final << 31; -+} -+ -+/** -+ * struct dpaa2_dq - the qman result structure -+ * @dont_manipulate_directly: the 16 32bit data to represent the whole -+ * possible qman dequeue result. -+ * -+ * When frames are dequeued, the FDs show up inside "dequeue" result structures -+ * (if at all, not all dequeue results contain valid FDs). This structure type -+ * is intentionally defined without internal detail, and the only reason it -+ * isn't declared opaquely (without size) is to allow the user to provide -+ * suitably-sized (and aligned) memory for these entries. -+ */ -+struct dpaa2_dq { -+ uint32_t dont_manipulate_directly[16]; -+}; -+ -+/* Parsing frame dequeue results */ -+/* FQ empty */ -+#define DPAA2_DQ_STAT_FQEMPTY 0x80 -+/* FQ held active */ -+#define DPAA2_DQ_STAT_HELDACTIVE 0x40 -+/* FQ force eligible */ -+#define DPAA2_DQ_STAT_FORCEELIGIBLE 0x20 -+/* Valid frame */ -+#define DPAA2_DQ_STAT_VALIDFRAME 0x10 -+/* FQ ODP enable */ -+#define DPAA2_DQ_STAT_ODPVALID 0x04 -+/* Volatile dequeue */ -+#define DPAA2_DQ_STAT_VOLATILE 0x02 -+/* volatile dequeue command is expired */ -+#define DPAA2_DQ_STAT_EXPIRED 0x01 -+ -+/** -+ * dpaa2_dq_flags() - Get the stat field of dequeue response -+ * @dq: the dequeue result. -+ */ -+uint32_t dpaa2_dq_flags(const struct dpaa2_dq *dq); -+ -+/** -+ * dpaa2_dq_is_pull() - Check whether the dq response is from a pull -+ * command. -+ * @dq: the dequeue result. -+ * -+ * Return 1 for volatile(pull) dequeue, 0 for static dequeue. -+ */ -+static inline int dpaa2_dq_is_pull(const struct dpaa2_dq *dq) -+{ -+ return (int)(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_VOLATILE); -+} -+ -+/** -+ * dpaa2_dq_is_pull_complete() - Check whether the pull command is completed. -+ * @dq: the dequeue result. -+ * -+ * Return boolean. -+ */ -+static inline int dpaa2_dq_is_pull_complete( -+ const struct dpaa2_dq *dq) -+{ -+ return (int)(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_EXPIRED); -+} -+ -+/** -+ * dpaa2_dq_seqnum() - Get the seqnum field in dequeue response -+ * seqnum is valid only if VALIDFRAME flag is TRUE -+ * @dq: the dequeue result. -+ * -+ * Return seqnum. -+ */ -+uint16_t dpaa2_dq_seqnum(const struct dpaa2_dq *dq); -+ -+/** -+ * dpaa2_dq_odpid() - Get the seqnum field in dequeue response -+ * odpid is valid only if ODPVAILD flag is TRUE. -+ * @dq: the dequeue result. -+ * -+ * Return odpid. -+ */ -+uint16_t dpaa2_dq_odpid(const struct dpaa2_dq *dq); -+ -+/** -+ * dpaa2_dq_fqid() - Get the fqid in dequeue response -+ * @dq: the dequeue result. -+ * -+ * Return fqid. -+ */ -+uint32_t dpaa2_dq_fqid(const struct dpaa2_dq *dq); -+ -+/** -+ * dpaa2_dq_byte_count() - Get the byte count in dequeue response -+ * @dq: the dequeue result. -+ * -+ * Return the byte count remaining in the FQ. -+ */ -+uint32_t dpaa2_dq_byte_count(const struct dpaa2_dq *dq); -+ -+/** -+ * dpaa2_dq_frame_count() - Get the frame count in dequeue response -+ * @dq: the dequeue result. -+ * -+ * Return the frame count remaining in the FQ. -+ */ -+uint32_t dpaa2_dq_frame_count(const struct dpaa2_dq *dq); -+ -+/** -+ * dpaa2_dq_fd_ctx() - Get the frame queue context in dequeue response -+ * @dq: the dequeue result. -+ * -+ * Return the frame queue context. -+ */ -+uint64_t dpaa2_dq_fqd_ctx(const struct dpaa2_dq *dq); -+ -+/** -+ * dpaa2_dq_fd() - Get the frame descriptor in dequeue response -+ * @dq: the dequeue result. -+ * -+ * Return the frame descriptor. -+ */ -+const struct dpaa2_fd *dpaa2_dq_fd(const struct dpaa2_dq *dq); -+ -+#endif /* __FSL_DPAA2_FD_H */ ---- /dev/null -+++ b/drivers/staging/fsl-mc/include/fsl_dpaa2_io.h -@@ -0,0 +1,619 @@ -+/* Copyright 2014 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef __FSL_DPAA2_IO_H -+#define __FSL_DPAA2_IO_H -+ -+#include "fsl_dpaa2_fd.h" -+ -+struct dpaa2_io; -+struct dpaa2_io_store; -+ -+/** -+ * DOC: DPIO Service Management -+ * -+ * The DPIO service provides APIs for users to interact with the datapath -+ * by enqueueing and dequeing frame descriptors. -+ * -+ * The following set of APIs can be used to enqueue and dequeue frames -+ * as well as producing notification callbacks when data is available -+ * for dequeue. -+ */ -+ -+/** -+ * struct dpaa2_io_desc - The DPIO descriptor. -+ * @receives_notifications: Use notificaton mode. -+ * @has_irq: use irq-based proessing. -+ * @will_poll: use poll processing. -+ * @has_8prio: set for channel with 8 priority WQs. -+ * @cpu: the cpu index that at least interrupt handlers will execute on. -+ * @stash_affinity: the stash affinity for this portal favour 'cpu' -+ * @regs_cena: the cache enabled regs. -+ * @regs_cinh: the cache inhibited regs. -+ * @dpio_id: The dpio index. -+ * @qman_version: the qman version -+ * -+ * Describe the attributes and features of the DPIO object. -+ */ -+struct dpaa2_io_desc { -+ /* non-zero iff the DPIO has a channel */ -+ int receives_notifications; -+ /* non-zero if the DPIO portal interrupt is handled. If so, the -+ * caller/OS handles the interrupt and calls dpaa2_io_service_irq(). */ -+ int has_irq; -+ /* non-zero if the caller/OS is prepared to called the -+ * dpaa2_io_service_poll() routine as part of its run-to-completion (or -+ * scheduling) loop. If so, the DPIO service may dynamically switch some -+ * of its processing between polling-based and irq-based. It is illegal -+ * combination to have (!has_irq && !will_poll). */ -+ int will_poll; -+ /* ignored unless 'receives_notifications'. Non-zero iff the channel has -+ * 8 priority WQs, otherwise the channel has 2. */ -+ int has_8prio; -+ /* the cpu index that at least interrupt handlers will execute on. And -+ * if 'stash_affinity' is non-zero, the cache targeted by stash -+ * transactions is affine to this cpu. */ -+ int cpu; -+ /* non-zero if stash transactions for this portal favour 'cpu' over -+ * other CPUs. (Eg. zero if there's no stashing, or stashing is to -+ * shared cache.) */ -+ int stash_affinity; -+ /* Caller-provided flags, determined by bus-scanning and/or creation of -+ * DPIO objects via MC commands. */ -+ void *regs_cena; -+ void *regs_cinh; -+ int dpio_id; -+ uint32_t qman_version; -+}; -+ -+/** -+ * dpaa2_io_create() - create a dpaa2_io object. -+ * @desc: the dpaa2_io descriptor -+ * -+ * Activates a "struct dpaa2_io" corresponding to the given config of an actual -+ * DPIO object. This handle can be used on it's own (like a one-portal "DPIO -+ * service") or later be added to a service-type "struct dpaa2_io" object. Note, -+ * the information required on 'cfg' is copied so the caller is free to do as -+ * they wish with the input parameter upon return. -+ * -+ * Return a valid dpaa2_io object for success, or NULL for failure. -+ */ -+struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc); -+ -+/** -+ * dpaa2_io_create_service() - Create an (initially empty) DPIO service. -+ * -+ * Return a valid dpaa2_io object for success, or NULL for failure. -+ */ -+struct dpaa2_io *dpaa2_io_create_service(void); -+ -+/** -+ * dpaa2_io_default_service() - Use the driver's own global (and initially -+ * empty) DPIO service. -+ * -+ * This increments the reference count, so don't forget to use dpaa2_io_down() -+ * for each time this function is called. -+ * -+ * Return a valid dpaa2_io object for success, or NULL for failure. -+ */ -+struct dpaa2_io *dpaa2_io_default_service(void); -+ -+/** -+ * dpaa2_io_down() - release the dpaa2_io object. -+ * @d: the dpaa2_io object to be released. -+ * -+ * The "struct dpaa2_io" type can represent an individual DPIO object (as -+ * described by "struct dpaa2_io_desc") or an instance of a "DPIO service", -+ * which can be used to group/encapsulate multiple DPIO objects. In all cases, -+ * each handle obtained should be released using this function. -+ */ -+void dpaa2_io_down(struct dpaa2_io *d); -+ -+/** -+ * dpaa2_io_service_add() - Add the given DPIO object to the given DPIO service. -+ * @service: the given DPIO service. -+ * @obj: the given DPIO object. -+ * -+ * 'service' must have been created by dpaa2_io_create_service() and 'obj' -+ * must have been created by dpaa2_io_create(). This increments the reference -+ * count on the object that 'obj' refers to, so the user could call -+ * dpaa2_io_down(obj) after this and the object will persist within the service -+ * (and will be destroyed when the service is destroyed). -+ * -+ * Return 0 for success, or -EINVAL for failure. -+ */ -+int dpaa2_io_service_add(struct dpaa2_io *service, struct dpaa2_io *obj); -+ -+/** -+ * dpaa2_io_get_descriptor() - Get the DPIO descriptor of the given DPIO object. -+ * @obj: the given DPIO object. -+ * @desc: the returned DPIO descriptor. -+ * -+ * This function will return failure if the given dpaa2_io struct represents a -+ * service rather than an individual DPIO object, otherwise it returns zero and -+ * the given 'cfg' structure is filled in. -+ * -+ * Return 0 for success, or -EINVAL for failure. -+ */ -+int dpaa2_io_get_descriptor(struct dpaa2_io *obj, struct dpaa2_io_desc *desc); -+ -+/** -+ * dpaa2_io_poll() - Process any notifications and h/w-initiated events that -+ * are polling-driven. -+ * @obj: the given DPIO object. -+ * -+ * Obligatory for DPIO objects that have dpaa2_io_desc::will_poll non-zero. -+ * -+ * Return 0 for success, or -EINVAL for failure. -+ */ -+int dpaa2_io_poll(struct dpaa2_io *obj); -+ -+/** -+ * dpaa2_io_irq() - Process any notifications and h/w-initiated events that are -+ * irq-driven. -+ * @obj: the given DPIO object. -+ * -+ * Obligatory for DPIO objects that have dpaa2_io_desc::has_irq non-zero. -+ * -+ * Return IRQ_HANDLED for success, or -EINVAL for failure. -+ */ -+int dpaa2_io_irq(struct dpaa2_io *obj); -+ -+/** -+ * dpaa2_io_pause_poll() - Used to stop polling. -+ * @obj: the given DPIO object. -+ * -+ * If a polling application is going to stop polling for a period of time and -+ * supports interrupt processing, it can call this function to convert all -+ * processing to IRQ. (Eg. when sleeping.) -+ * -+ * Return -EINVAL. -+ */ -+int dpaa2_io_pause_poll(struct dpaa2_io *obj); -+ -+/** -+ * dpaa2_io_resume_poll() - Resume polling -+ * @obj: the given DPIO object. -+ * -+ * Return -EINVAL. -+ */ -+int dpaa2_io_resume_poll(struct dpaa2_io *obj); -+ -+/** -+ * dpaa2_io_service_notifications() - Get a mask of cpus that the DPIO service -+ * can receive notifications on. -+ * @s: the given DPIO object. -+ * @mask: the mask of cpus. -+ * -+ * Note that this is a run-time snapshot. If things like cpu-hotplug are -+ * supported in the target system, then an attempt to register notifications -+ * for a cpu that appears present in the given mask might fail if that cpu has -+ * gone offline in the mean time. -+ */ -+void dpaa2_io_service_notifications(struct dpaa2_io *s, cpumask_t *mask); -+ -+/** -+ * dpaa2_io_service_stashing - Get a mask of cpus that the DPIO service has stash -+ * affinity to. -+ * @s: the given DPIO object. -+ * @mask: the mask of cpus. -+ */ -+void dpaa2_io_service_stashing(struct dpaa2_io *s, cpumask_t *mask); -+ -+/** -+ * dpaa2_io_service_nonaffine() - Check the DPIO service's cpu affinity -+ * for stashing. -+ * @s: the given DPIO object. -+ * -+ * Return a boolean, whether or not the DPIO service has resources that have no -+ * particular cpu affinity for stashing. (Useful to know if you wish to operate -+ * on CPUs that the service has no affinity to, you would choose to use -+ * resources that are neutral, rather than affine to a different CPU.) Unlike -+ * other service-specific APIs, this one doesn't return an error if it is passed -+ * a non-service object. So don't do it. -+ */ -+int dpaa2_io_service_has_nonaffine(struct dpaa2_io *s); -+ -+/*************************/ -+/* Notification handling */ -+/*************************/ -+ -+/** -+ * struct dpaa2_io_notification_ctx - The DPIO notification context structure. -+ * @cb: the callback to be invoked when the notification arrives. -+ * @is_cdan: Zero/FALSE for FQDAN, non-zero/TRUE for CDAN. -+ * @id: FQID or channel ID, needed for rearm. -+ * @desired_cpu: the cpu on which the notifications will show up. -+ * @actual_cpu: the cpu the notification actually shows up. -+ * @migration_cb: callback function used for migration. -+ * @dpio_id: the dpio index. -+ * @qman64: the 64-bit context value shows up in the FQDAN/CDAN. -+ * @node: the list node. -+ * @dpio_private: the dpio object internal to dpio_service. -+ * -+ * When a FQDAN/CDAN registration is made (eg. by DPNI/DPCON/DPAI code), a -+ * context of the following type is used. The caller can embed it within a -+ * larger structure in order to add state that is tracked along with the -+ * notification (this may be useful when callbacks are invoked that pass this -+ * notification context as a parameter). -+ */ -+struct dpaa2_io_notification_ctx { -+ void (*cb)(struct dpaa2_io_notification_ctx *); -+ int is_cdan; -+ uint32_t id; -+ /* This specifies which cpu the user wants notifications to show up on -+ * (ie. to execute 'cb'). If notification-handling on that cpu is not -+ * available at the time of notification registration, the registration -+ * will fail. */ -+ int desired_cpu; -+ /* If the target platform supports cpu-hotplug or other features -+ * (related to power-management, one would expect) that can migrate IRQ -+ * handling of a given DPIO object, then this value will potentially be -+ * different to 'desired_cpu' at run-time. */ -+ int actual_cpu; -+ /* And if migration does occur and this callback is non-NULL, it will -+ * be invoked prior to any futher notification callbacks executing on -+ * 'newcpu'. Note that 'oldcpu' is what 'actual_cpu' was prior to the -+ * migration, and 'newcpu' is what it is now. Both could conceivably be -+ * different to 'desired_cpu'. */ -+ void (*migration_cb)(struct dpaa2_io_notification_ctx *, -+ int oldcpu, int newcpu); -+ /* These are returned from dpaa2_io_service_register(). -+ * 'dpio_id' is the dpaa2_io_desc::dpio_id value of the DPIO object that -+ * has been selected by the service for receiving the notifications. The -+ * caller can use this value in the MC command that attaches the FQ (or -+ * channel) of their DPNI (or DPCON, respectively) to this DPIO for -+ * notification-generation. -+ * 'qman64' is the 64-bit context value that needs to be sent in the -+ * same MC command in order to be programmed into the FQ or channel - -+ * this is the 64-bit value that shows up in the FQDAN/CDAN messages to -+ * the DPIO object, and the DPIO service specifies this value back to -+ * the caller so that the notifications that show up will be -+ * comprensible/demux-able to the DPIO service. */ -+ int dpio_id; -+ uint64_t qman64; -+ /* These fields are internal to the DPIO service once the context is -+ * registered. TBD: may require more internal state fields. */ -+ struct list_head node; -+ void *dpio_private; -+}; -+ -+/** -+ * dpaa2_io_service_register() - Prepare for servicing of FQDAN or CDAN -+ * notifications on the given DPIO service. -+ * @service: the given DPIO service. -+ * @ctx: the notification context. -+ * -+ * The MC command to attach the caller's DPNI/DPCON/DPAI device to a -+ * DPIO object is performed after this function is called. In that way, (a) the -+ * DPIO service is "ready" to handle a notification arrival (which might happen -+ * before the "attach" command to MC has returned control of execution back to -+ * the caller), and (b) the DPIO service can provide back to the caller the -+ * 'dpio_id' and 'qman64' parameters that it should pass along in the MC command -+ * in order for the DPNI/DPCON/DPAI resources to be configured to produce the -+ * right notification fields to the DPIO service. -+ * -+ * Return 0 for success, or -ENODEV for failure. -+ */ -+int dpaa2_io_service_register(struct dpaa2_io *service, -+ struct dpaa2_io_notification_ctx *ctx); -+ -+/** -+ * dpaa2_io_service_deregister - The opposite of 'register'. -+ * @service: the given DPIO service. -+ * @ctx: the notification context. -+ * -+ * Note that 'register' should be called *before* -+ * making the MC call to attach the notification-producing device to the -+ * notification-handling DPIO service, the 'unregister' function should be -+ * called *after* making the MC call to detach the notification-producing -+ * device. -+ * -+ * Return 0 for success. -+ */ -+int dpaa2_io_service_deregister(struct dpaa2_io *service, -+ struct dpaa2_io_notification_ctx *ctx); -+ -+/** -+ * dpaa2_io_service_rearm() - Rearm the notification for the given DPIO service. -+ * @service: the given DPIO service. -+ * @ctx: the notification context. -+ * -+ * Once a FQDAN/CDAN has been produced, the corresponding FQ/channel is -+ * considered "disarmed". Ie. the user can issue pull dequeue operations on that -+ * traffic source for as long as it likes. Eventually it may wish to "rearm" -+ * that source to allow it to produce another FQDAN/CDAN, that's what this -+ * function achieves. -+ * -+ * Return 0 for success, or -ENODEV if no service available, -EBUSY/-EIO for not -+ * being able to implement the rearm the notifiaton due to setting CDAN or -+ * scheduling fq. -+ */ -+int dpaa2_io_service_rearm(struct dpaa2_io *service, -+ struct dpaa2_io_notification_ctx *ctx); -+ -+/** -+ * dpaa2_io_from_registration() - Get the DPIO object from the given notification -+ * context. -+ * @ctx: the given notifiation context. -+ * @ret: the returned DPIO object. -+ * -+ * Like 'dpaa2_io_service_get_persistent()' (see below), except that the -+ * returned handle is not selected based on a 'cpu' argument, but is the same -+ * DPIO object that the given notification context is registered against. The -+ * returned handle carries a reference count, so a corresponding dpaa2_io_down() -+ * would be required when the reference is no longer needed. -+ * -+ * Return 0 for success, or -EINVAL for failure. -+ */ -+int dpaa2_io_from_registration(struct dpaa2_io_notification_ctx *ctx, -+ struct dpaa2_io **ret); -+ -+/**********************************/ -+/* General usage of DPIO services */ -+/**********************************/ -+ -+/** -+ * dpaa2_io_service_get_persistent() - Get the DPIO resource from the given -+ * notification context and cpu. -+ * @service: the DPIO service. -+ * @cpu: the cpu that the DPIO resource has stashing affinity to. -+ * @ret: the returned DPIO resource. -+ * -+ * The various DPIO interfaces can accept a "struct dpaa2_io" handle that refers -+ * to an individual DPIO object or to a whole service. In the latter case, an -+ * internal choice is made for each operation. This function supports the former -+ * case, by selecting an individual DPIO object *from* the service in order for -+ * it to be used multiple times to provide "persistence". The returned handle -+ * also carries a reference count, so a corresponding dpaa2_io_down() would be -+ * required when the reference is no longer needed. Note, a parameter of -1 for -+ * 'cpu' will select a DPIO resource that has no particular stashing affinity to -+ * any cpu (eg. one that stashes to platform cache). -+ * -+ * Return 0 for success, or -ENODEV for failure. -+ */ -+int dpaa2_io_service_get_persistent(struct dpaa2_io *service, int cpu, -+ struct dpaa2_io **ret); -+ -+/*****************/ -+/* Pull dequeues */ -+/*****************/ -+ -+/** -+ * dpaa2_io_service_pull_fq() - pull dequeue functions from a fq. -+ * @d: the given DPIO service. -+ * @fqid: the given frame queue id. -+ * @s: the dpaa2_io_store object for the result. -+ * -+ * To support DCA/order-preservation, it will be necessary to support an -+ * alternative form, because they must ultimately dequeue to DQRR rather than a -+ * user-supplied dpaa2_io_store. Furthermore, those dequeue results will -+ * "complete" using a caller-provided callback (from DQRR processing) rather -+ * than the caller explicitly looking at their dpaa2_io_store for results. Eg. -+ * the alternative form will likely take a callback parameter rather than a -+ * store parameter. Ignoring it for now to keep the picture clearer. -+ * -+ * Return 0 for success, or error code for failure. -+ */ -+int dpaa2_io_service_pull_fq(struct dpaa2_io *d, uint32_t fqid, -+ struct dpaa2_io_store *s); -+ -+/** -+ * dpaa2_io_service_pull_channel() - pull dequeue functions from a channel. -+ * @d: the given DPIO service. -+ * @channelid: the given channel id. -+ * @s: the dpaa2_io_store object for the result. -+ * -+ * To support DCA/order-preservation, it will be necessary to support an -+ * alternative form, because they must ultimately dequeue to DQRR rather than a -+ * user-supplied dpaa2_io_store. Furthermore, those dequeue results will -+ * "complete" using a caller-provided callback (from DQRR processing) rather -+ * than the caller explicitly looking at their dpaa2_io_store for results. Eg. -+ * the alternative form will likely take a callback parameter rather than a -+ * store parameter. Ignoring it for now to keep the picture clearer. -+ * -+ * Return 0 for success, or error code for failure. -+ */ -+int dpaa2_io_service_pull_channel(struct dpaa2_io *d, uint32_t channelid, -+ struct dpaa2_io_store *s); -+ -+/************/ -+/* Enqueues */ -+/************/ -+ -+/** -+ * dpaa2_io_service_enqueue_fq() - Enqueue a frame to a frame queue. -+ * @d: the given DPIO service. -+ * @fqid: the given frame queue id. -+ * @fd: the frame descriptor which is enqueued. -+ * -+ * This definition bypasses some features that are not expected to be priority-1 -+ * features, and may not be needed at all via current assumptions (QBMan's -+ * feature set is wider than the MC object model is intendeding to support, -+ * initially at least). Plus, keeping them out (for now) keeps the API view -+ * simpler. Missing features are; -+ * - enqueue confirmation (results DMA'd back to the user) -+ * - ORP -+ * - DCA/order-preservation (see note in "pull dequeues") -+ * - enqueue consumption interrupts -+ * -+ * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready, -+ * or -ENODEV if there is no dpio service. -+ */ -+int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d, -+ uint32_t fqid, -+ const struct dpaa2_fd *fd); -+ -+/** -+ * dpaa2_io_service_enqueue_qd() - Enqueue a frame to a QD. -+ * @d: the given DPIO service. -+ * @qdid: the given queuing destination id. -+ * @prio: the given queuing priority. -+ * @qdbin: the given queuing destination bin. -+ * @fd: the frame descriptor which is enqueued. -+ * -+ * This definition bypasses some features that are not expected to be priority-1 -+ * features, and may not be needed at all via current assumptions (QBMan's -+ * feature set is wider than the MC object model is intendeding to support, -+ * initially at least). Plus, keeping them out (for now) keeps the API view -+ * simpler. Missing features are; -+ * - enqueue confirmation (results DMA'd back to the user) -+ * - ORP -+ * - DCA/order-preservation (see note in "pull dequeues") -+ * - enqueue consumption interrupts -+ * -+ * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready, -+ * or -ENODEV if there is no dpio service. -+ */ -+int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d, -+ uint32_t qdid, uint8_t prio, uint16_t qdbin, -+ const struct dpaa2_fd *fd); -+ -+/*******************/ -+/* Buffer handling */ -+/*******************/ -+ -+/** -+ * dpaa2_io_service_release() - Release buffers to a buffer pool. -+ * @d: the given DPIO object. -+ * @bpid: the buffer pool id. -+ * @buffers: the buffers to be released. -+ * @num_buffers: the number of the buffers to be released. -+ * -+ * Return 0 for success, and negative error code for failure. -+ */ -+int dpaa2_io_service_release(struct dpaa2_io *d, -+ uint32_t bpid, -+ const uint64_t *buffers, -+ unsigned int num_buffers); -+ -+/** -+ * dpaa2_io_service_acquire() - Acquire buffers from a buffer pool. -+ * @d: the given DPIO object. -+ * @bpid: the buffer pool id. -+ * @buffers: the buffer addresses for acquired buffers. -+ * @num_buffers: the expected number of the buffers to acquire. -+ * -+ * Return a negative error code if the command failed, otherwise it returns -+ * the number of buffers acquired, which may be less than the number requested. -+ * Eg. if the buffer pool is empty, this will return zero. -+ */ -+int dpaa2_io_service_acquire(struct dpaa2_io *d, -+ uint32_t bpid, -+ uint64_t *buffers, -+ unsigned int num_buffers); -+ -+/***************/ -+/* DPIO stores */ -+/***************/ -+ -+/* These are reusable memory blocks for retrieving dequeue results into, and to -+ * assist with parsing those results once they show up. They also hide the -+ * details of how to use "tokens" to make detection of DMA results possible (ie. -+ * comparing memory before the DMA and after it) while minimising the needless -+ * clearing/rewriting of those memory locations between uses. -+ */ -+ -+/** -+ * dpaa2_io_store_create() - Create the dma memory storage for dequeue -+ * result. -+ * @max_frames: the maximum number of dequeued result for frames, must be <= 16. -+ * @dev: the device to allow mapping/unmapping the DMAable region. -+ * -+ * Constructor - max_frames must be <= 16. The user provides the -+ * device struct to allow mapping/unmapping of the DMAable region. Area for -+ * storage will be allocated during create. The size of this storage is -+ * "max_frames*sizeof(struct dpaa2_dq)". The 'dpaa2_io_store' returned is a -+ * wrapper structure allocated within the DPIO code, which owns and manages -+ * allocated store. -+ * -+ * Return dpaa2_io_store struct for successfuly created storage memory, or NULL -+ * if not getting the stroage for dequeue result in create API. -+ */ -+struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames, -+ struct device *dev); -+ -+/** -+ * dpaa2_io_store_destroy() - Destroy the dma memory storage for dequeue -+ * result. -+ * @s: the storage memory to be destroyed. -+ * -+ * Frees to specified storage memory. -+ */ -+void dpaa2_io_store_destroy(struct dpaa2_io_store *s); -+ -+/** -+ * dpaa2_io_store_next() - Determine when the next dequeue result is available. -+ * @s: the dpaa2_io_store object. -+ * @is_last: indicate whether this is the last frame in the pull command. -+ * -+ * Once dpaa2_io_store has been passed to a function that performs dequeues to -+ * it, like dpaa2_ni_rx(), this function can be used to determine when the next -+ * frame result is available. Once this function returns non-NULL, a subsequent -+ * call to it will try to find the *next* dequeue result. -+ * -+ * Note that if a pull-dequeue has a null result because the target FQ/channel -+ * was empty, then this function will return NULL rather than expect the caller -+ * to always check for this on his own side. As such, "is_last" can be used to -+ * differentiate between "end-of-empty-dequeue" and "still-waiting". -+ * -+ * Return dequeue result for a valid dequeue result, or NULL for empty dequeue. -+ */ -+struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last); -+ -+#ifdef CONFIG_FSL_QBMAN_DEBUG -+/** -+ * dpaa2_io_query_fq_count() - Get the frame and byte count for a given fq. -+ * @d: the given DPIO object. -+ * @fqid: the id of frame queue to be queried. -+ * @fcnt: the queried frame count. -+ * @bcnt: the queried byte count. -+ * -+ * Knowing the FQ count at run-time can be useful in debugging situations. -+ * The instantaneous frame- and byte-count are hereby returned. -+ * -+ * Return 0 for a successful query, and negative error code if query fails. -+ */ -+int dpaa2_io_query_fq_count(struct dpaa2_io *d, uint32_t fqid, -+ uint32_t *fcnt, uint32_t *bcnt); -+ -+/** -+ * dpaa2_io_query_bp_count() - Query the number of buffers currenty in a -+ * buffer pool. -+ * @d: the given DPIO object. -+ * @bpid: the index of buffer pool to be queried. -+ * @num: the queried number of buffers in the buffer pool. -+ * -+ * Return 0 for a sucessful query, and negative error code if query fails. -+ */ -+int dpaa2_io_query_bp_count(struct dpaa2_io *d, uint32_t bpid, -+ uint32_t *num); -+#endif -+#endif /* __FSL_DPAA2_IO_H */ diff --git a/target/linux/layerscape/patches-4.4/7199-dpaa2-dpio-Cosmetic-cleanup.patch b/target/linux/layerscape/patches-4.4/7199-dpaa2-dpio-Cosmetic-cleanup.patch deleted file mode 100644 index dd5eb7e1b0..0000000000 --- a/target/linux/layerscape/patches-4.4/7199-dpaa2-dpio-Cosmetic-cleanup.patch +++ /dev/null @@ -1,35 +0,0 @@ -From a4150e8ec8da3add3933dd026c7154dcca2ee2e7 Mon Sep 17 00:00:00 2001 -From: Mihai Caraman -Date: Tue, 5 Apr 2016 14:47:57 +0000 -Subject: [PATCH 199/226] dpaa2-dpio: Cosmetic cleanup - -Replace obsolete terms. - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-mc/bus/dpio/fsl_qbman_base.h | 2 +- - drivers/staging/fsl-mc/bus/dpio/qbman_portal.h | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dpio/fsl_qbman_base.h -+++ b/drivers/staging/fsl-mc/bus/dpio/fsl_qbman_base.h -@@ -51,7 +51,7 @@ struct qbman_block_desc { - * Descriptor for a QBMan software portal, expressed in terms that make sense to - * the user context. Ie. on MC, this information is likely to be true-physical, - * and instantiated statically at compile-time. On GPP, this information is -- * likely to be obtained via "discovery" over a partition's "layerscape bus" -+ * likely to be obtained via "discovery" over a partition's "MC bus" - * (ie. in response to a MC portal command), and would take into account any - * virtualisation of the GPP user's address space and/or interrupt numbering. - */ ---- a/drivers/staging/fsl-mc/bus/dpio/qbman_portal.h -+++ b/drivers/staging/fsl-mc/bus/dpio/qbman_portal.h -@@ -138,7 +138,7 @@ static inline void *qbman_swp_mc_complet - /* This struct locates a sub-field within a QBMan portal (CENA) cacheline which - * is either serving as a configuration command or a query result. The - * representation is inherently little-endian, as the indexing of the words is -- * itself little-endian in nature and layerscape is little endian for anything -+ * itself little-endian in nature and DPAA2 is little endian for anything - * that crosses a word boundary too (64-bit fields are the obvious examples). - */ - struct qb_attr_code { diff --git a/target/linux/layerscape/patches-4.4/7200-staging-fsl-mc-dpio-driver-match-id-cleanup.patch b/target/linux/layerscape/patches-4.4/7200-staging-fsl-mc-dpio-driver-match-id-cleanup.patch deleted file mode 100644 index 91ff06a381..0000000000 --- a/target/linux/layerscape/patches-4.4/7200-staging-fsl-mc-dpio-driver-match-id-cleanup.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 3cc23880ecb98efe2d868254201ac58f945d9e1d Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Wed, 15 Jun 2016 14:05:08 -0500 -Subject: [PATCH 200/226] staging: fsl-mc: dpio driver match id cleanup - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-mc/bus/dpio/dpio-drv.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/staging/fsl-mc/bus/dpio/dpio-drv.c -+++ b/drivers/staging/fsl-mc/bus/dpio/dpio-drv.c -@@ -364,12 +364,10 @@ err_mcportal: - return err; - } - --static const struct fsl_mc_device_match_id dpaa2_dpio_match_id_table[] = { -+static const struct fsl_mc_device_id dpaa2_dpio_match_id_table[] = { - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dpio", -- .ver_major = DPIO_VER_MAJOR, -- .ver_minor = DPIO_VER_MINOR - }, - { .vendor = 0x0 } - }; diff --git a/target/linux/layerscape/patches-4.4/7201-staging-dpaa2-eth-initial-commit-of-dpaa2-eth-driver.patch b/target/linux/layerscape/patches-4.4/7201-staging-dpaa2-eth-initial-commit-of-dpaa2-eth-driver.patch deleted file mode 100644 index cbec144516..0000000000 --- a/target/linux/layerscape/patches-4.4/7201-staging-dpaa2-eth-initial-commit-of-dpaa2-eth-driver.patch +++ /dev/null @@ -1,12268 +0,0 @@ -From e588172442093fe22374dc1bfc88a7da751d6b30 Mon Sep 17 00:00:00 2001 -From: Bogdan Hamciuc -Date: Tue, 15 Sep 2015 10:14:16 -0500 -Subject: [PATCH 201/226] staging: dpaa2-eth: initial commit of dpaa2-eth - driver - -commit 3106ece5d96784b63a4eabb26661baaefedd164f -[context adjustment] - -This is a commit of a squash of the cumulative dpaa2-eth patches -in the sdk 2.0 kernel as of 3/7/2016. - -flib,dpaa2-eth: flib header update (Rebasing onto kernel 3.19, MC 0.6) - -this patch was moved from 4.0 branch - -Signed-off-by: Bogdan Hamciuc -[Stuart: split into multiple patches] -Signed-off-by: Stuart Yoder -Integrated-by: Jilong Guo - -flib,dpaa2-eth: updated Eth (was: Rebasing onto kernel 3.19, MC 0.6) - -updated Ethernet driver from 4.0 branch - -Signed-off-by: Bogdan Hamciuc -[Stuart: cherry-picked patch from 4.0 and split it up] -Signed-off-by: Stuart Yoder - -Conflicts: - - drivers/staging/Makefile - -Signed-off-by: Stuart Yoder - -dpaa2-eth: Adjust 'options' size - -The 'options' field of various MC configuration structures has changed -from u64 to u32 as of MC firmware version 7.0. - -Signed-off-by: Bogdan Hamciuc -Change-Id: I9ba0c19fc22f745e6be6cc40862afa18fa3ac3db -Reviewed-on: http://git.am.freescale.net:8181/35579 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Selectively disable preemption - -Temporary workaround for a MC Bus API quirk which only allows us to -specify exclusively, either a spinlock-protected MC Portal, or a -mutex-protected one, but then tries to match the runtime context in -order to enforce their usage. - -Te Be Reverted. - -Signed-off-by: Bogdan Hamciuc -Change-Id: Ida2ec1fdbdebfd2e427f96ddad7582880146fda9 -Reviewed-on: http://git.am.freescale.net:8181/35580 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Fix ethtool bug - -We were writing beyond the end of the allocated data area for ethtool -statistics. - -Signed-off-by: Ioana Radulescu -Change-Id: I6b77498a78dad06970508ebbed7144be73854f7f -Reviewed-on: http://git.am.freescale.net:8181/35583 -Reviewed-by: Bogdan Hamciuc -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Retry read if store unexpectedly empty - -After we place a volatile dequeue command, we might get to inquire the -store before the DMA has actually completed. In such cases, we must -retry, lest we'll have the store overwritten by the next legitimate -volatile dequeue. - -Signed-off-by: Bogdan Hamciuc -Change-Id: I314fbb8b4d9f589715e42d35fc6677d726b8f5ba -Reviewed-on: http://git.am.freescale.net:8181/35584 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -flib: Fix "missing braces around initializer" warning - -Gcc does not support (yet?) the ={0} initializer in the case of an array -of structs. Fixing the Flib in order to make the warning go away. - -Signed-off-by: Bogdan Hamciuc -Change-Id: I8782ecb714c032cfeeecf4c8323cf9dbb702b10f -Reviewed-on: http://git.am.freescale.net:8181/35586 -Reviewed-by: Stuart Yoder -Tested-by: Stuart Yoder - -Revert "dpaa2-eth: Selectively disable preemption" - -This reverts commit e1455823c33b8dd48b5d2d50a7e8a11d3934cc0d. - -dpaa2-eth: Fix memory leak - -A buffer kmalloc'ed at probe time was not freed after it was no -longer needed. - -Signed-off-by: Ioana Radulescu -Change-Id: Iba197209e9203ed306449729c6dcd23ec95f094d -Reviewed-on: http://git.am.freescale.net:8181/35756 -Reviewed-by: Bogdan Hamciuc -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Remove unused field in ldpaa_eth_priv structure - -Signed-off-by: Ioana Radulescu -Change-Id: I124c3e4589b6420b1ea5cc05a03a51ea938b2bea -Reviewed-on: http://git.am.freescale.net:8181/35757 -Reviewed-by: Bogdan Hamciuc -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Fix "NOHZ: local_softirq_pending" warning - -Explicitly run softirqs after we enable NAPI. This in particular gets us -rid of the "NOHZ: local_softirq_pending" warnings, but it also solves a -couple of other problems, among which fluctuating performance and high -ping latencies. - -Notes: - - This will prevent us from timely processing notifications and -other "non-frame events" coming into the software portal. So far, -though, we only expect Dequeue Available Notifications, so this patch -is good enough for now. - - A degradation in console responsiveness is expected, especially in -cases where the bottom-half runs on the same CPU as the console. - -Signed-off-by: Bogdan Hamciuc -Signed-off-by: Ioana Radulescu -Change-Id: Ia6f11da433024e80ee59e821c9eabfa5068df5e5 -Reviewed-on: http://git.am.freescale.net:8181/35830 -Reviewed-by: Alexandru Marginean -Reviewed-by: Stuart Yoder -Tested-by: Stuart Yoder - -dpaa2-eth: Add polling mode for link state changes - -Add the Kconfigurable option of using a thread for polling on -the link state instead of relying on interrupts from the MC. - -Signed-off-by: Ioana Radulescu -Change-Id: If2fe66fc5c0fbee2568d7afa15d43ea33f92e8e2 -Reviewed-on: http://git.am.freescale.net:8181/35967 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Bogdan Hamciuc -Reviewed-by: Stuart Yoder - -dpaa2-eth: Update copyright years. - -Signed-off-by: Bogdan Hamciuc -Change-Id: I7e00eecfc5569027c908124726edaf06be357c02 -Reviewed-on: http://git.am.freescale.net:8181/37666 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Ruxandra Ioana Radulescu -Reviewed-by: Stuart Yoder - -dpaa2-eth: Drain bpools when netdev is down - -In a data path layout with potentially a dozen interfaces, not all of -them may be up at the same time, yet they may consume a fair amount of -buffer space. -Drain the buffer pool upon ifdown and re-seed it at ifup. - -Signed-off-by: Bogdan Hamciuc -Change-Id: I24a379b643c8b5161a33b966c3314cf91024ed4a -Reviewed-on: http://git.am.freescale.net:8181/37667 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Ruxandra Ioana Radulescu -Reviewed-by: Stuart Yoder - -dpaa2-eth: Interrupts cleanup - -Add the code for cleaning up interrupts on driver removal. -This was lost during transition from kernel 3.16 to 3.19. - -Also, there's no need to call devm_free_irq() if probe fails -as the kernel will release all driver resources. - -Signed-off-by: Ioana Radulescu -Change-Id: Ifd404bbf399d5ba62e2896371076719c1d6b4214 -Reviewed-on: http://git.am.freescale.net:8181/36199 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Bogdan Hamciuc -Reviewed-by: Bharat Bhushan -Reviewed-by: Stuart Yoder -Reviewed-on: http://git.am.freescale.net:8181/37690 - -dpaa2-eth: Ethtool support for hashing - -Only one set of header fields is supported for all protocols, the driver -silently replaces previous configuration regardless of user selected -protocol. -Following fields are supported: - L2DA - VLAN tag - L3 proto - IP SA - IP DA - L4 bytes 0 & 1 [TCP/UDP src port] - L4 bytes 2 & 3 [TCP/UDP dst port] - -Signed-off-by: Alex Marginean - -Change-Id: I97c9dac1b842fe6bc7115e40c08c42f67dee8c9c -Reviewed-on: http://git.am.freescale.net:8181/37260 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Bogdan Hamciuc -Reviewed-by: Stuart Yoder - -dpaa2-eth: Fix maximum number of FQs - -The maximum number of Rx/Tx conf FQs associated to a DPNI was not -updated when the implementation changed. It just happened to work -by accident. - -Signed-off-by: Ioana Radulescu -Reviewed-by: Bogdan Hamciuc -Change-Id: I03e30e0121a40d0d15fcdc4bee1fb98caa17c0ef -Reviewed-on: http://git.am.freescale.net:8181/37668 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Fix Rx buffer address alignment - -We need to align the start address of the Rx buffers to -LDPAA_ETH_BUF_ALIGN bytes. We were using SMP_CACHE_BYTES instead. -It happened to work because both defines have the value of 64, -but this may change at some point. - -Signed-off-by: Ioana Radulescu -Reviewed-by: Bogdan Hamciuc -Change-Id: I08a0f3f18f82c5581c491bd395e3ad066b25bcf5 -Reviewed-on: http://git.am.freescale.net:8181/37669 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Add buffer count to ethtool statistics - -Print the number of buffers available in the pool for a certain DPNI -along with the rest of the ethtool -S stats. - -Signed-off-by: Ioana Radulescu -Reviewed-by: Bogdan Hamciuc -Change-Id: Ia1f5cf341c8414ae2058a73f6bc81490ef134592 -Reviewed-on: http://git.am.freescale.net:8181/37671 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Add Rx error queue - -Add a Kconfigurable option that allows Rx error frames to be -enqueued on an error FQ. By default error frames are discarded, -but for debug purposes we may want to process them at driver -level. - -Note: Checkpatch issues a false positive about complex macros that -should be parenthesized. - -Signed-off-by: Ioana Radulescu -Reviewed-by: Bogdan Hamciuc -Change-Id: I7d19d00b5d5445514ebd112c886ce8ccdbb1f0da -Reviewed-on: http://git.am.freescale.net:8181/37672 -Reviewed-by: Stuart Yoder -Tested-by: Stuart Yoder - -staging: fsl-dpaa2: FLib headers cleanup - -Going with the flow of moving fsl-dpaa2 headers into the drivers' -location rather than keeping them all in one place. - -Signed-off-by: Bogdan Hamciuc -Change-Id: Ia2870cd019a4934c7835d38752a46b2a0045f30e -Reviewed-on: http://git.am.freescale.net:8181/37674 -Reviewed-by: Ruxandra Ioana Radulescu -Reviewed-by: Stuart Yoder -Tested-by: Stuart Yoder - -dpaa2-eth: Klocwork fixes - -Fix several issues reported by Klocwork. - -Signed-off-by: Ioana Radulescu -Reviewed-by: Bogdan Hamciuc -Change-Id: I1e23365765f3b0ff9b6474d8207df7c1f2433ccd -Reviewed-on: http://git.am.freescale.net:8181/37675 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Probe devices with no hash support - -Don't fail at probe if the DPNI doesn't have the hash distribution -option enabled. Instead, initialize a single Rx frame queue and -use it for all incoming traffic. - -Rx flow hashing configuration through ethtool will not work -in this case. - -Signed-off-by: Ioana Radulescu -Reviewed-by: Bogdan Hamciuc -Change-Id: Iaf17e05b15946e6901c39a21b5344b89e9f1d797 -Reviewed-on: http://git.am.freescale.net:8181/37676 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Process frames in IRQ context - -Stop using threaded IRQs and move back to hardirq top-halves. -This is the first patch of a small series adapting the DPIO and Ethernet -code to these changes. - -Signed-off-by: Roy Pledge -Tested-by: Ioana Radulescu -Tested-by: Bogdan Hamciuc -Reviewed-by: Bogdan Hamciuc -Reviewed-by: Stuart Yoder -[Stuart: split dpio and eth into separate patches, updated subject] -Signed-off-by: Stuart Yoder - -dpaa2-eth: Fix bug in NAPI poll - -We incorrectly rearmed FQDAN notifications at the end of a NAPI cycle, -regardless of whether the NAPI budget was consumed or not. We only need -to rearm notifications if the NAPI cycle cleaned less frames than its -budget, otherwise a new NAPI poll will be scheduled anyway. - -Signed-off-by: Ioana Radulescu -Reviewed-by: Bogdan Hamciuc -Change-Id: Ib55497bdbd769047420b3150668f2e2aef3c93f6 -Reviewed-on: http://git.am.freescale.net:8181/38317 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Use dma_map_sg on Tx - -Use the simpler dma_map_sg() along with the scatterlist API if the -egress frame is scatter-gather, at the cost of keeping some extra -information in the frame's software annotation area. - -Signed-off-by: Bogdan Hamciuc -Change-Id: If293aeabbd58d031f21456704357d4ff7e53c559 -Reviewed-on: http://git.am.freescale.net:8181/37681 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Reduce retries if Tx portal busy - -Too many retries due to Tx portal contention led to a significant cycle -waste and reduction in performance. -Reducing the number of enqueue retries and dropping frame if eventually -unsuccessful. - -Signed-off-by: Bogdan Hamciuc -Change-Id: Ib111ec61cd4294a7632348c25fa3d7f4002be0c0 -Reviewed-on: http://git.am.freescale.net:8181/37682 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Add sysfs support for TxConf affinity change - -This adds support in sysfs for affining Tx Confirmation queues to GPPs, -via the affine DPIO objects. - -The user can specify a cpu list in /sys/class/net/ni/txconf_affinity -to which the Ethernet driver will affine the TxConf FQs, in round-robin -fashion. This is naturally a bit coarse, because there is no "official" -mapping of the transmitting CPUs to Tx Confirmation queues. - -Signed-off-by: Bogdan Hamciuc -Change-Id: I4b3da632e202ceeb22986c842d746aafe2a87a81 -Reviewed-on: http://git.am.freescale.net:8181/37684 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Implement ndo_select_queue - -Use a very simple selection function for the egress FQ. The purpose -behind this is to more evenly distribute Tx Confirmation traffic, -especially in the case of multiple egress flows, when bundling it all on -CPU 0 would make that CPU a bottleneck. - -Signed-off-by: Bogdan Hamciuc -Change-Id: Ibfe8aad7ad5c719cc95d7817d7de6d2094f0f7ed -Reviewed-on: http://git.am.freescale.net:8181/37685 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Reduce TxConf NAPI weight back to 64 - -It turns out that not only the kernel frowned upon the old budget of 256, -but the measured values were well below that anyway. - -Signed-off-by: Bogdan Hamciuc -Change-Id: I62ddd3ea1dbfd8b51e2bcb2286e0d5eb10ac7f27 -Reviewed-on: http://git.am.freescale.net:8181/37688 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Try refilling the buffer pool less often - -We used to check if the buffer pool needs refilling at each Rx -frame. Instead, do that check (and the actual buffer release if -needed) only after a pull dequeue. - -Signed-off-by: Ioana Radulescu -Change-Id: Id52fab83873c40a711b8cadfcf909eb7e2e210f3 -Reviewed-on: http://git.am.freescale.net:8181/38318 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Bogdan Hamciuc -Reviewed-by: Stuart Yoder - -dpaa2-eth: Stay in NAPI if exact budget is met - -An off-by-one bug would cause premature exiting from the NAPI cycle. -Performance degradation is particularly severe in IPFWD cases. - -Signed-off-by: Ioana Radulescu -Tested-by: Bogdan Hamciuc -Change-Id: I9de2580c7ff8e46cbca9613890b03737add35e26 -Reviewed-on: http://git.am.freescale.net:8181/37908 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Bogdan Hamciuc -Reviewed-by: Stuart Yoder - -dpaa2-eth: Minor changes to FQ stats - -Signed-off-by: Ioana Radulescu -Change-Id: I0ced0e7b2eee28599cdea79094336c0d44f0d32b -Reviewed-on: http://git.am.freescale.net:8181/38319 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Bogdan Hamciuc -Reviewed-by: Stuart Yoder - -dpaa2-eth: Support fewer DPIOs than CPUs - -The previous DPIO functions would transparently choose a (perhaps -non-affine) CPU if the required CPU was not available. Now that their API -contract is enforced, we must make an explicit request for *any* DPIO if -the request for an *affine* DPIO has failed. - -Signed-off-by: Bogdan Hamciuc -Change-Id: Ib08047ffa33518993b1ffa4671d0d4f36d6793d0 -Reviewed-on: http://git.am.freescale.net:8181/38320 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Roy Pledge -Reviewed-by: Stuart Yoder - -dpaa2-eth: cosmetic changes in hashing code - -Signed-off-by: Alex Marginean -Change-Id: I79e21a69a6fb68cdbdb8d853c059661f8988dbf9 -Reviewed-on: http://git.am.freescale.net:8181/37258 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Prefetch data before initial access - -Signed-off-by: Ioana Radulescu -Change-Id: Ie8f0163651aea7e3e197a408f89ca98d296d4b8b -Reviewed-on: http://git.am.freescale.net:8181/38753 -Reviewed-by: Bogdan Hamciuc -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Use netif_receive_skb - -netif_rx() is a leftover since our pre-NAPI codebase. - -Signed-off-by: Ioana Radulescu -Change-Id: I02ff0a059862964df1bf81b247853193994c2dfe -Reviewed-on: http://git.am.freescale.net:8181/38754 -Reviewed-by: Bogdan Hamciuc -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Use napi_alloc_frag() on Rx. - -A bit better-suited than netdev_alloc_frag(). - -Signed-off-by: Ioana Radulescu -Change-Id: I8863a783502db963e5dc968f049534c36ad484e2 -Reviewed-on: http://git.am.freescale.net:8181/38755 -Reviewed-by: Bogdan Hamciuc -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Silence skb_realloc_headroom() warning - -pktgen tests tend to be too noisy because pktgen does not observe the -net device's needed_headroom specification and we used to be pretty loud -about that. We'll print the warning message just once. - -Signed-off-by: Bogdan Hamciuc -Change-Id: I3c12eba29c79aa9c487307d367f6d9f4dbe447a3 -Reviewed-on: http://git.am.freescale.net:8181/38756 -Reviewed-by: Ruxandra Ioana Radulescu -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Print message upon device unplugging - -Give a console notification when a DPNI is unplugged. This is useful for -automated tests to know the operation (which is not instantaneous) has -finished. - -Signed-off-by: Bogdan Hamciuc -Change-Id: If33033201fcee7671ad91c2b56badf3fb56a9e3e -Reviewed-on: http://git.am.freescale.net:8181/38757 -Reviewed-by: Ruxandra Ioana Radulescu -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Add debugfs support - -Add debugfs entries for showing detailed per-CPU and per-FQ -counters for each network interface. Also add a knob for -resetting these stats. -The agregated interface statistics were already available through -ethtool -S. - -Signed-off-by: Ioana Radulescu -Reviewed-by: Bogdan Hamciuc -Change-Id: I55f5bfe07a15b0d1bf0c6175d8829654163a4318 -Reviewed-on: http://git.am.freescale.net:8181/38758 -Reviewed-by: Stuart Yoder -Tested-by: Stuart Yoder - -dpaa2-eth: limited support for flow steering - -Steering is supported on a sub-set of fields, including DMAC, IP SRC -and DST, L4 ports. -Steering and hashing configurations depend on each other, that makes -the whole thing tricky to configure. Currently FS can be configured -using only the fields selected for hashing and all the hashing fields -must be included in the match key - masking doesn't work yet. - -Signed-off-by: Alex Marginean -Change-Id: I9fa3199f7818a9a5f9d69d3483ffd839056cc468 -Reviewed-on: http://git.am.freescale.net:8181/38759 -Reviewed-by: Bogdan Hamciuc -Tested-by: Review Code-CDREVIEW -Reviewed-by: Ruxandra Ioana Radulescu -Reviewed-by: Stuart Yoder - -dpaa2-eth: Rename files into the dpaa2 nomenclature - -Signed-off-by: Bogdan Hamciuc -Change-Id: I1c3d62e2f19a59d4b65727234fd7df2dfd8683d9 -Reviewed-on: http://git.am.freescale.net:8181/38965 -Reviewed-by: Alexandru Marginean -Reviewed-by: Ruxandra Ioana Radulescu -Reviewed-by: Stuart Yoder -Tested-by: Stuart Yoder - -staging: dpaa2-eth: migrated remaining flibs for MC fw 8.0.0 - -Signed-off-by: J. German Rivera -[Stuart: split eth part into separate patch, updated subject] -Signed-off-by: Stuart Yoder - -dpaa2-eth: Clear 'backup_pool' attribute - -New MC-0.7 firmware allows specifying an alternate buffer pool, but we -are momentarily not using that feature. - -Signed-off-by: Bogdan Hamciuc -Change-Id: I0a6e6626512b7bbddfef732c71f1400b67f3e619 -Reviewed-on: http://git.am.freescale.net:8181/39149 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -dpaa2-eth: Do programing of MSIs in devm_request_threaded_irq() - -With the new dprc_set_obj_irq() we can now program MSIS in the device -in the callback invoked from devm_request_threaded_irq(). -Since this callback is invoked with interrupts disabled, we need to -use an atomic portal, instead of the root DPRC's built-in portal -which is non-atomic. - -Signed-off-by: Itai Katz -Signed-off-by: J. German Rivera -[Stuart: split original patch into multiple patches] -Signed-off-by: Stuart Yoder - -dpaa2-eth: Do not map beyond skb tail - -On Tx do dma_map only until skb->tail, rather than skb->end. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Declare NETIF_F_LLTX as a capability - -We are effectively doing lock-less Tx. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Avoid bitcopy of 'backpointers' struct - -Make 'struct ldpaa_eth_swa bps' a pointer and void copying it on both Tx -and TxConf. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Use CDANs instead of FQDANs - -Use Channel Dequeue Available Notifications (CDANs) instead of -Frame Queue notifications. We allocate a QMan channel (or DPCON -object) for each available cpu and assign to it the Rx and Tx conf -queues associated with that cpu. - -We usually want to have affine DPIOs and DPCONs (one for each core). -If this is not possible due to insufficient resources, we distribute -all ingress traffic on the cores with affine DPIOs. - -NAPI instances are now one per channel instead of one per FQ, as the -interrupt source changes. Statistics counters change accordingly. - -Note that after this commit is applied, one needs to provide sufficient -DPCON objects (either through DPL on restool) in order for the Ethernet -interfaces to work. - -Signed-off-by: Ioana Radulescu -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Cleanup debugfs statistics - -Several minor changes to statistics reporting: -* Fix print alignment of statistics counters -* Fix a naming ambiguity in the cpu_stats debugfs ops -* Add Rx/Tx error counters; these were already used, but not -reported in the per-CPU stats - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Add tx shaping configuration in sysfs - -Egress traffic can be shaped via a per-DPNI SysFS entry: - echo M N > /sys/class/net/ni/tx_shaping -where: - M is the maximum throughput, expressed in Mbps. - N is the maximum burst size, expressed in bytes, at most 64000. - -To remove shaping, use M=0, N=0. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Fix "Tx busy" counter - -Under heavy egress load, when a large number of the transmitted packets -cannot be sent because of high portal contention, the "Tx busy" counter -was not properly incremented. - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Fix memory cleanup in case of Tx congestion - -The error path of ldpaa_eth_tx() was not properly freeing the SGT buffer -if the enqueue had failed because of congestion. DMA unmapping was -missing, too. - -Factor the code originally inside the TxConf callback out into a -separate function that would be called on both TxConf and Tx paths. - -Signed-off-by: Bogdan Hamciuc -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Use napi_gro_receive() - -Call napi_gro_receive(), effectively enabling GRO. -NOTE: We could further optimize this by looking ahead in the parse results -received from hardware and only using GRO when the L3+L4 combination is -appropriate. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Fix compilation of Rx Error FQ code - -Conditionally-compiled code slipped between cracks when FLibs were -updated. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: Add Kconfig dependency on DEBUG_FS - -The driver's debugfs support depends on the generic CONFIG_DEBUG_FS. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Fix interface down/up bug - -If a networking interface was brought down while still receiving -ingress traffic, the delay between DPNI disable and NAPI disable -was not enough to ensure all in-flight frames got processed. -Instead, some frames were left pending in the Rx queues. If the -net device was then removed (i.e. restool unbind/unplug), the -call to dpni_reset() silently failed and the kernel crashed on -device replugging. - -Fix this by increasing the FQ drain time. Also, at ifconfig up -we enable NAPI before starting the DPNI, to make sure we don't -miss any early CDANs. - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Iterate only through initialized channels - -The number of DPIO objects available to a DPNI may be fewer than the -number of online cores. A typical example would be a DPNI with a -distribution size smaller than 8. Since we only initialize as many -channels (DPCONs) as there are DPIOs, iterating through all online cpus -would produce a nasty oops when retrieving ethtool stats. - -Signed-off-by: Bogdan Hamciuc - -net: pktgen: Observe needed_headroom of the device - -Allocate enough space so as not to force the outgoing net device to do -skb_realloc_headroom(). - -Signed-off-by: Bogdan Hamciuc -Signed-off-by: David S. Miller - -dpaa2-eth: Trace buffer pool seeding - -Add ftrace support for buffer pool seeding. Individual buffers are -described by virtual and dma addresses and sizes, as well as by bpid. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Explicitly set carrier off at ifconfig up - -If we don't, netif_carrier_ok() will still return true even if the link -state is marked as LINKWATCH_PENDING, which in a dpni-2-dpni case may -last indefinitely long. This will cause "ifconfig up" followed by "ip -link show" to report LOWER_UP when the peer DPNI is still down (and in -fact before we've even received any link notification at all). - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Fix FQ type in stats print - -Fix a bug where the type of the Rx error queue was printed -incorrectly in the debugfs statistics - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Don't build debugfs support as a separate module - -Instead have module init and exit functions declared explicitly for -the Ethernet driver and initialize/destroy the debugfs directory there. - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Remove debugfs #ifdefs from dpaa2-eth.c - -Instead of conditionally compiling the calls to debugfs init -functions in dpaa2-eth.c, define no-op stubs for these functions -in case the debugfs Kconfig option is not enabled. This makes -the code more readable. - -Signed-off-by: Ioana Radulescu -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Use napi_complete_done() - -Replace napi_complete() with napi_complete_done(). - -Together with setting /sys/class/net/ethX/gro_flush_timeout, this -allows us to take better advantage of GRO coalescing and improves -throughput and cpu load in TCP termination tests. - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Fix error path in probe - -NAPI delete was called at the wrong place when exiting probe -function on an error path - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Allocate channels based on queue count - -Limit the number of channels allocated per DPNI to the maximum -between the number of Rx queues per traffic class (distribution size) -and Tx confirmation queues (number of tx flows). -If this happens to be larger than the number of available cores, only -allocate one channel for each core and distribute the frame queues on -the cores/channels in a round robin fashion. - -Signed-off-by: Ioana Radulescu -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Use DPNI setting for number of Tx flows - -Instead of creating one Tx flow for each online cpu, use the DPNI -attributes for deciding how many senders we have. - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Renounce sentinel in enum dpni_counter - -Bring back the Flib header dpni.h to its initial content by removing the -sentinel value in enum dpni_counter. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Fix Rx queue count - -We were missing a roundup to the next power of 2 in order to be in sync -with the MC implementation. -Actually, moved that logic in a separate function which we'll remove -once the MC API is updated. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Unmap the S/G table outside ldpaa_eth_free_rx_fd - -The Scatter-Gather table is already unmapped outside ldpaa_eth_free_rx_fd -so no need to try to unmap it once more. - -Signed-off-by: Cristian Sovaiala - -dpaa2-eth: Use napi_schedule_irqoff() - -At the time we schedule NAPI, the Dequeue Available Notifications (which -are the de facto triggers of NAPI processing) are already disabled. - -Signed-off-by: Ioana Radulescu -Signed-off-by: Bogdan Hamciuc - -net: Fix ethernet Kconfig - -Re-add missing 'source' directive. This exists on the integration -branch, but was mistakenly removed by an earlier dpaa2-eth rebase. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Manually update link state at ifup - -The DPMAC may have handled the link state notification before the DPNI -is up. A new PHY state transision may not subsequently occur, so the -DPNI must initiate a read of the DPMAC state. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Stop carrier upon ifdown - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Fix print messages in link state handling code - -Avoid an "(uninitialized)" message during DPNI probe by replacing -netdev_info() with its corresponding dev_info(). -Purge some related comments and add some netdev messages to assist -link state debugging. -Remove an excessively defensive assertion. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Do not allow ethtool settings change while the NI is up - -Due to a MC limitation, link state changes while the DPNI is enabled -will fail. For now, we'll just prevent the call from going down to the MC -if we know it will fail. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Reduce ethtool messages verbosity - -Transform a couple of netdev_info() calls into netdev_dbg(). - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Only unmask IRQs that we actually handle - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Produce fewer boot log messages - -No longer print one line for each all-zero hwaddr that was replaced with -a random MAC address; just inform the user once that this has occurred. -And reduce redundancy of some printouts in the bootlog. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Fix big endian issue - -We were not doing any endianness conversions on the scatter gather -table entries, which caused problems on big endian kernels. - -For frame descriptors the QMan driver takes care of this transparently, -but in the case of SG entries we need to do it ourselves. - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Force atomic context for lazy bpool seeding - -We use the same ldpaa_bp_add_7() function for initial buffer pool -seeding (from .ndo_open) and for hotpath pool replenishing. The function -is using napi_alloc_frag() as an optimization for the Rx datapath, but -that turns out to require atomic execution because of a this_cpu_ptr() -call down its stack. -This patch temporarily disables preemption around the initial seeding of -the Rx buffer pool. - -Signed-off-by: Bogdan Hamciuc - -dpaa-eth: Integrate Flib version 0.7.1.2 - -Although API-compatible with 0.7.1.1, there are some ABI changes -that warrant a new integration. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: No longer adjust max_dist_per_tc - -The MC firmware until version 0.7.1.1/8.0.2 requires that -max_dist_per_tc have the value expected by the hardware, which would be -different from what the user expects. MC firmware 0.7.1.2/8.0.5 fixes -that, so we remove our transparent conversion. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Enforce 256-byte Rx alignment - -Hardware erratum enforced by MC requires that Rx buffer lengths and -addresses be 265-byte aligned. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Rename Tx buf alignment macro - -The existing "BUF_ALIGN" macro remained confined to Tx usage, after -separate alignment was introduced for Rx. Renaming accordingly. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Fix hashing distribution size - -Commit be3fb62623e4338e60fb60019f134b6055cbc127 -Author: Bogdan Hamciuc -Date: Fri Oct 23 18:26:44 2015 +0300 - - dpaa2-eth: No longer adjust max_dist_per_tc - -missed one usage of the ldpaa_queue_count() function, making -distribution size inadvertenly lower. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Remove ndo_select_queue - -Our implementation of ndo_select_queue would lead to questions regarding -our support for qdiscs. Until we find an optimal way to select the txq -without breaking future qdisc integration, just remove the -ndo_select_queue callback entirely and leave the stack figure out the -flow. -This incurs a ~2-3% penalty on some performance tests. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Select TxConf FQ based on processor id - -Use smp_processor_id instead of skb queue mapping to determine the tx -flow id and implicitly the confirmation queue. - -Signed-off-by: Bogdan Hamciuc - -dpaa2-eth: Reduce number of buffers in bpool - -Reduce the maximum number of buffers in each buffer pool associated -with a DPNI. This in turn reduces the number of memory allocations -performed in a single batch when buffers fall below a certain -threshold. - -Provides a significant performance boost (~5-10% increase) on both -termination and forwarding scenarios, while also reducing the driver -memory footprint. - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Replace "ldpaa" with "dpaa2" - -Replace all instances of "ldpaa"/"LDPAA" in the Ethernet driver -(names of functions, structures, macros, etc), with "dpaa2"/"DPAA2", -except for DPIO API function calls. - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: rename ldpaa to dpaa2 - -Signed-off-by: Haiying Wang -(Stuart: this patch was split out from the origin global rename patch) -Signed-off-by: Stuart Yoder - -dpaa2-eth: Rename dpaa_io_query_fq_count to dpaa2_io_query_fq_count - -Signed-off-by: Cristian Sovaiala - -fsl-dpio: rename dpaa_* structure to dpaa2_* - -Signed-off-by: Haiying Wang - -dpaa2-eth, dpni, fsl-mc: Updates for MC0.8.0 - -Several changes need to be performed in sync for supporting -the newest MC version: -* Update mc-cmd.h -* Update the dpni binary interface to v6.0 -* Update the DPAA2 Eth driver to account for several API changes - -Signed-off-by: Ioana Radulescu - -staging: fsl-dpaa2: ethernet: add support for hardware timestamping - -Signed-off-by: Yangbo Lu - -fsl-dpaa2: eth: Do not set bpid in egress fd - -We don't do FD recycling on egress, BPID is therefore not necessary. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: eth: Amend buffer refill comment - -A change request has been pending for placing an upper bound to the -buffer replenish logic on Rx. However, short of practical alternatives, -resort to amending the relevant comment and rely on ksoftirqd to -guarantee interactivity. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: eth: Configure a taildrop threshold for each Rx frame queue. - -The selected value allows for Rx jumbo (10K) frames processing -while at the same time helps balance the system in the case of -IP forwarding. - -Also compute the number of buffers in the pool based on the TD -threshold to avoid starving some of the ingress queues in small -frames, high throughput scenarios. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Check objects' FLIB version - -Make sure we support the DPNI, DPCON and DPBP version, otherwise -abort probing early on and provide an error message. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Remove likely/unlikely from cold paths - -Signed-off-by: Cristian Sovaiala -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: eth: Remove __cold attribute - -Signed-off-by: Cristian Sovaiala - -fsl-dpaa2: eth: Replace netdev_XXX with dev_XXX before register_netdevice() - -Signed-off-by: Cristian Sovaiala -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: eth: Fix coccinelle issue - -drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c:687:1-36: WARNING: -Assignment of bool to 0/1 - -Signed-off-by: Cristian Sovaiala - -fsl-dpaa2: eth: Fix minor spelling issue - -Signed-off-by: Cristian Sovaiala - -fsl-dpaa2: eth: Add a couple of 'unlikely' on hot path - -Signed-off-by: Cristian Sovaiala -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: eth: Fix a bunch of minor issues found by static analysis tools - -As found by Klocworks and Checkpatch: - - Unused variables - - Integer type replacements - - Unchecked memory allocations - - Whitespace, alignment and newlining - -Signed-off-by: Cristian Sovaiala -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: eth: Remove "inline" keyword from static functions - -Signed-off-by: Cristian Sovaiala - -fsl-dpaa2: eth: Remove BUG/BUG_ONs - -Signed-off-by: Cristian Sovaiala -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: eth: Use NAPI_POLL_WEIGHT - -No need to define our own macro as long as we're using the -default value of 64. - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Move dpaa2_eth_swa structure to header file - -It was the only structure defined inside dpaa2-eth.c - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Replace uintX_t with uX - -Signed-off-by: Ioana Radulescu -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: eth: Minor fixes & cosmetics - -- Make driver log level an int, because this is what - netif_msg_init expects. -- Remove driver description macro as it was used only once, - immediately after being defined -- Remove include comment - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Move bcast address setup to dpaa2_eth_netdev_init - -It seems to fit better there than directly in probe. - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Fix DMA mapping bug - -During hashing/flow steering configuration via ethtool, we were -doing a DMA unmap from the wrong address. Fix the issue by using -the DMA address that was initially mapped. - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Associate buffer counting to queues instead of cpu - -Move the buffer counters from being percpu variables to being -associated with QMan channels. This is more natural as we need -to dimension the buffer pool count based on distribution size -rather than number of online cores. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Provide driver and fw version to ethtool - -Read fw version from the MC and interpret DPNI FLib major.minor as the -driver's version. Report these in 'ethool -i'. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: eth: Remove dependency on GCOV_KERNEL - -Signed-off-by: Cristian Sovaiala - -fsl-dpaa2: eth: Remove FIXME/TODO comments from the code - -Some of the concerns had already been addressed, a couple are being -fixed in place. -Left a few TODOs related to the flow-steering code, which needs to be -revisited before upstreaming anyway. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Remove forward declarations - -Instead move the functions such that they are defined prior to -being used. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Remove dead code in IRQ handler - -If any of those conditions were met, it is unlikely we'd ever be there -in the first place. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: eth: Remove dpaa2_dpbp_drain() - -Its sole caller was __dpaa2_dpbp_free(), so move its content and get rid -of one function call. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: eth: Remove duplicate define - -We somehow ended up with two defines for the maximum number -of tx queues. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Move header comment to .c file - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: eth: Make DPCON allocation failure produce a benign message - -Number of DPCONs may be smaller than the number of CPUs in a number of -valid scenarios. One such scenario is when the DPNI's distribution width -is smaller than the number of cores and we just don't want to -over-allocate DPCONs. -Make the DPCON allocation failure less menacing by changing the logged -message. - -While at it, remove a unused parameter in function prototype. - -Signed-off-by: Bogdan Hamciuc - -dpaa2 eth: irq update - -Signed-off-by: Stuart Yoder - -Conflicts: - drivers/staging/Kconfig - drivers/staging/Makefile ---- - MAINTAINERS | 15 + - drivers/staging/Kconfig | 2 + - drivers/staging/Makefile | 1 + - drivers/staging/fsl-dpaa2/Kconfig | 11 + - drivers/staging/fsl-dpaa2/Makefile | 5 + - drivers/staging/fsl-dpaa2/ethernet/Kconfig | 42 + - drivers/staging/fsl-dpaa2/ethernet/Makefile | 21 + - .../staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.c | 319 +++ - .../staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.h | 61 + - .../staging/fsl-dpaa2/ethernet/dpaa2-eth-trace.h | 185 ++ - drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c | 2793 ++++++++++++++++++++ - drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h | 366 +++ - drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c | 882 +++++++ - drivers/staging/fsl-dpaa2/ethernet/dpkg.h | 175 ++ - drivers/staging/fsl-dpaa2/ethernet/dpni-cmd.h | 1058 ++++++++ - drivers/staging/fsl-dpaa2/ethernet/dpni.c | 1907 +++++++++++++ - drivers/staging/fsl-dpaa2/ethernet/dpni.h | 2581 ++++++++++++++++++ - drivers/staging/fsl-mc/include/mc-cmd.h | 5 +- - drivers/staging/fsl-mc/include/net.h | 481 ++++ - net/core/pktgen.c | 1 + - 20 files changed, 10910 insertions(+), 1 deletion(-) - create mode 100644 drivers/staging/fsl-dpaa2/Kconfig - create mode 100644 drivers/staging/fsl-dpaa2/Makefile - create mode 100644 drivers/staging/fsl-dpaa2/ethernet/Kconfig - create mode 100644 drivers/staging/fsl-dpaa2/ethernet/Makefile - create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.c - create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.h - create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-trace.h - create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c - create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h - create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c - create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpkg.h - create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpni-cmd.h - create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpni.c - create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpni.h - create mode 100644 drivers/staging/fsl-mc/include/net.h - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -4539,6 +4539,21 @@ L: linux-kernel@vger.kernel.org - S: Maintained - F: drivers/staging/fsl-mc/ - -+FREESCALE DPAA2 ETH DRIVER -+M: Ioana Radulescu -+M: Bogdan Hamciuc -+M: Cristian Sovaiala -+L: linux-kernel@vger.kernel.org -+S: Maintained -+F: drivers/staging/fsl-dpaa2/ethernet/ -+ -+FREESCALE QORIQ MANAGEMENT COMPLEX RESTOOL DRIVER -+M: Lijun Pan -+L: linux-kernel@vger.kernel.org -+S: Maintained -+F: drivers/staging/fsl-mc/bus/mc-ioctl.h -+F: drivers/staging/fsl-mc/bus/mc-restool.c -+ - FREEVXFS FILESYSTEM - M: Christoph Hellwig - W: ftp://ftp.openlinux.org/pub/people/hch/vxfs ---- a/drivers/staging/Kconfig -+++ b/drivers/staging/Kconfig -@@ -114,4 +114,6 @@ source "drivers/staging/most/Kconfig" - - source "drivers/staging/fsl_ppfe/Kconfig" - -+source "drivers/staging/fsl-dpaa2/Kconfig" -+ - endif # STAGING ---- a/drivers/staging/Makefile -+++ b/drivers/staging/Makefile -@@ -49,3 +49,4 @@ obj-$(CONFIG_FSL_DPA) += fsl_q - obj-$(CONFIG_WILC1000) += wilc1000/ - obj-$(CONFIG_MOST) += most/ - obj-$(CONFIG_FSL_PPFE) += fsl_ppfe/ -+obj-$(CONFIG_FSL_DPAA2) += fsl-dpaa2/ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/Kconfig -@@ -0,0 +1,11 @@ -+# -+# Freescale device configuration -+# -+ -+config FSL_DPAA2 -+ bool "Freescale DPAA2 devices" -+ depends on FSL_MC_BUS -+ ---help--- -+ Build drivers for Freescale DataPath Acceleration Architecture (DPAA2) family of SoCs. -+# TODO move DPIO driver in-here? -+source "drivers/staging/fsl-dpaa2/ethernet/Kconfig" ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/Makefile -@@ -0,0 +1,5 @@ -+# -+# Makefile for the Freescale network device drivers. -+# -+ -+obj-$(CONFIG_FSL_DPAA2_ETH) += ethernet/ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethernet/Kconfig -@@ -0,0 +1,42 @@ -+# -+# Freescale DPAA Ethernet driver configuration -+# -+# Copyright (C) 2014-2015 Freescale Semiconductor, Inc. -+# -+# This file is released under the GPLv2 -+# -+ -+menuconfig FSL_DPAA2_ETH -+ tristate "Freescale DPAA2 Ethernet" -+ depends on FSL_DPAA2 && FSL_MC_BUS && FSL_MC_DPIO -+ select FSL_DPAA2_MAC -+ default y -+ ---help--- -+ Freescale Data Path Acceleration Architecture Ethernet -+ driver, using the Freescale MC bus driver. -+ -+if FSL_DPAA2_ETH -+config FSL_DPAA2_ETH_LINK_POLL -+ bool "Use polling mode for link state" -+ default n -+ ---help--- -+ Poll for detecting link state changes instead of using -+ interrupts. -+ -+config FSL_DPAA2_ETH_USE_ERR_QUEUE -+ bool "Enable Rx error queue" -+ default n -+ ---help--- -+ Allow Rx error frames to be enqueued on an error queue -+ and processed by the driver (by default they are dropped -+ in hardware). -+ This may impact performance, recommended for debugging -+ purposes only. -+ -+config FSL_DPAA2_ETH_DEBUGFS -+ depends on DEBUG_FS && FSL_QBMAN_DEBUG -+ bool "Enable debugfs support" -+ default n -+ ---help--- -+ Enable advanced statistics through debugfs interface. -+endif ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethernet/Makefile -@@ -0,0 +1,21 @@ -+# -+# Makefile for the Freescale DPAA Ethernet controllers -+# -+# Copyright (C) 2014-2015 Freescale Semiconductor, Inc. -+# -+# This file is released under the GPLv2 -+# -+ -+ccflags-y += -DVERSION=\"\" -+ -+obj-$(CONFIG_FSL_DPAA2_ETH) += fsl-dpaa2-eth.o -+ -+fsl-dpaa2-eth-objs := dpaa2-eth.o dpaa2-ethtool.o dpni.o -+fsl-dpaa2-eth-${CONFIG_FSL_DPAA2_ETH_DEBUGFS} += dpaa2-eth-debugfs.o -+ -+#Needed by the tracing framework -+CFLAGS_dpaa2-eth.o := -I$(src) -+ -+ifeq ($(CONFIG_FSL_DPAA2_ETH_GCOV),y) -+ GCOV_PROFILE := y -+endif ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.c -@@ -0,0 +1,319 @@ -+ -+/* Copyright 2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include -+#include -+#include "dpaa2-eth.h" -+#include "dpaa2-eth-debugfs.h" -+ -+#define DPAA2_ETH_DBG_ROOT "dpaa2-eth" -+ -+ -+static struct dentry *dpaa2_dbg_root; -+ -+static int dpaa2_dbg_cpu_show(struct seq_file *file, void *offset) -+{ -+ struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private; -+ struct rtnl_link_stats64 *stats; -+ struct dpaa2_eth_stats *extras; -+ int i; -+ -+ seq_printf(file, "Per-CPU stats for %s\n", priv->net_dev->name); -+ seq_printf(file, "%s%16s%16s%16s%16s%16s%16s%16s%16s\n", -+ "CPU", "Rx", "Rx Err", "Rx SG", "Tx", "Tx Err", "Tx conf", -+ "Tx SG", "Enq busy"); -+ -+ for_each_online_cpu(i) { -+ stats = per_cpu_ptr(priv->percpu_stats, i); -+ extras = per_cpu_ptr(priv->percpu_extras, i); -+ seq_printf(file, "%3d%16llu%16llu%16llu%16llu%16llu%16llu%16llu%16llu\n", -+ i, -+ stats->rx_packets, -+ stats->rx_errors, -+ extras->rx_sg_frames, -+ stats->tx_packets, -+ stats->tx_errors, -+ extras->tx_conf_frames, -+ extras->tx_sg_frames, -+ extras->tx_portal_busy); -+ } -+ -+ return 0; -+} -+ -+static int dpaa2_dbg_cpu_open(struct inode *inode, struct file *file) -+{ -+ int err; -+ struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)inode->i_private; -+ -+ err = single_open(file, dpaa2_dbg_cpu_show, priv); -+ if (err < 0) -+ netdev_err(priv->net_dev, "single_open() failed\n"); -+ -+ return err; -+} -+ -+static const struct file_operations dpaa2_dbg_cpu_ops = { -+ .open = dpaa2_dbg_cpu_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static char *fq_type_to_str(struct dpaa2_eth_fq *fq) -+{ -+ switch (fq->type) { -+ case DPAA2_RX_FQ: -+ return "Rx"; -+ case DPAA2_TX_CONF_FQ: -+ return "Tx conf"; -+ case DPAA2_RX_ERR_FQ: -+ return "Rx err"; -+ default: -+ return "N/A"; -+ } -+} -+ -+static int dpaa2_dbg_fqs_show(struct seq_file *file, void *offset) -+{ -+ struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private; -+ struct dpaa2_eth_fq *fq; -+ u32 fcnt, bcnt; -+ int i, err; -+ -+ seq_printf(file, "FQ stats for %s:\n", priv->net_dev->name); -+ seq_printf(file, "%s%16s%16s%16s%16s\n", -+ "VFQID", "CPU", "Type", "Frames", "Pending frames"); -+ -+ for (i = 0; i < priv->num_fqs; i++) { -+ fq = &priv->fq[i]; -+ err = dpaa2_io_query_fq_count(NULL, fq->fqid, &fcnt, &bcnt); -+ if (err) -+ fcnt = 0; -+ -+ seq_printf(file, "%5d%16d%16s%16llu%16u\n", -+ fq->fqid, -+ fq->target_cpu, -+ fq_type_to_str(fq), -+ fq->stats.frames, -+ fcnt); -+ } -+ -+ return 0; -+} -+ -+static int dpaa2_dbg_fqs_open(struct inode *inode, struct file *file) -+{ -+ int err; -+ struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)inode->i_private; -+ -+ err = single_open(file, dpaa2_dbg_fqs_show, priv); -+ if (err < 0) -+ netdev_err(priv->net_dev, "single_open() failed\n"); -+ -+ return err; -+} -+ -+static const struct file_operations dpaa2_dbg_fq_ops = { -+ .open = dpaa2_dbg_fqs_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static int dpaa2_dbg_ch_show(struct seq_file *file, void *offset) -+{ -+ struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private; -+ struct dpaa2_eth_channel *ch; -+ int i; -+ -+ seq_printf(file, "Channel stats for %s:\n", priv->net_dev->name); -+ seq_printf(file, "%s%16s%16s%16s%16s%16s\n", -+ "CHID", "CPU", "Deq busy", "Frames", "CDANs", -+ "Avg frm/CDAN"); -+ -+ for (i = 0; i < priv->num_channels; i++) { -+ ch = priv->channel[i]; -+ seq_printf(file, "%4d%16d%16llu%16llu%16llu%16llu\n", -+ ch->ch_id, -+ ch->nctx.desired_cpu, -+ ch->stats.dequeue_portal_busy, -+ ch->stats.frames, -+ ch->stats.cdan, -+ ch->stats.frames / ch->stats.cdan); -+ } -+ -+ return 0; -+} -+ -+static int dpaa2_dbg_ch_open(struct inode *inode, struct file *file) -+{ -+ int err; -+ struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)inode->i_private; -+ -+ err = single_open(file, dpaa2_dbg_ch_show, priv); -+ if (err < 0) -+ netdev_err(priv->net_dev, "single_open() failed\n"); -+ -+ return err; -+} -+ -+static const struct file_operations dpaa2_dbg_ch_ops = { -+ .open = dpaa2_dbg_ch_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static ssize_t dpaa2_dbg_reset_write(struct file *file, const char __user *buf, -+ size_t count, loff_t *offset) -+{ -+ struct dpaa2_eth_priv *priv = file->private_data; -+ struct rtnl_link_stats64 *percpu_stats; -+ struct dpaa2_eth_stats *percpu_extras; -+ struct dpaa2_eth_fq *fq; -+ struct dpaa2_eth_channel *ch; -+ int i; -+ -+ for_each_online_cpu(i) { -+ percpu_stats = per_cpu_ptr(priv->percpu_stats, i); -+ memset(percpu_stats, 0, sizeof(*percpu_stats)); -+ -+ percpu_extras = per_cpu_ptr(priv->percpu_extras, i); -+ memset(percpu_extras, 0, sizeof(*percpu_extras)); -+ } -+ -+ for (i = 0; i < priv->num_fqs; i++) { -+ fq = &priv->fq[i]; -+ memset(&fq->stats, 0, sizeof(fq->stats)); -+ } -+ -+ for_each_cpu(i, &priv->dpio_cpumask) { -+ ch = priv->channel[i]; -+ memset(&ch->stats, 0, sizeof(ch->stats)); -+ } -+ -+ return count; -+} -+ -+static const struct file_operations dpaa2_dbg_reset_ops = { -+ .open = simple_open, -+ .write = dpaa2_dbg_reset_write, -+}; -+ -+void dpaa2_dbg_add(struct dpaa2_eth_priv *priv) -+{ -+ if (!dpaa2_dbg_root) -+ return; -+ -+ /* Create a directory for the interface */ -+ priv->dbg.dir = debugfs_create_dir(priv->net_dev->name, -+ dpaa2_dbg_root); -+ if (!priv->dbg.dir) { -+ netdev_err(priv->net_dev, "debugfs_create_dir() failed\n"); -+ return; -+ } -+ -+ /* per-cpu stats file */ -+ priv->dbg.cpu_stats = debugfs_create_file("cpu_stats", S_IRUGO, -+ priv->dbg.dir, priv, -+ &dpaa2_dbg_cpu_ops); -+ if (!priv->dbg.cpu_stats) { -+ netdev_err(priv->net_dev, "debugfs_create_file() failed\n"); -+ goto err_cpu_stats; -+ } -+ -+ /* per-fq stats file */ -+ priv->dbg.fq_stats = debugfs_create_file("fq_stats", S_IRUGO, -+ priv->dbg.dir, priv, -+ &dpaa2_dbg_fq_ops); -+ if (!priv->dbg.fq_stats) { -+ netdev_err(priv->net_dev, "debugfs_create_file() failed\n"); -+ goto err_fq_stats; -+ } -+ -+ /* per-fq stats file */ -+ priv->dbg.ch_stats = debugfs_create_file("ch_stats", S_IRUGO, -+ priv->dbg.dir, priv, -+ &dpaa2_dbg_ch_ops); -+ if (!priv->dbg.fq_stats) { -+ netdev_err(priv->net_dev, "debugfs_create_file() failed\n"); -+ goto err_ch_stats; -+ } -+ -+ /* reset stats */ -+ priv->dbg.reset_stats = debugfs_create_file("reset_stats", S_IWUSR, -+ priv->dbg.dir, priv, -+ &dpaa2_dbg_reset_ops); -+ if (!priv->dbg.reset_stats) { -+ netdev_err(priv->net_dev, "debugfs_create_file() failed\n"); -+ goto err_reset_stats; -+ } -+ -+ return; -+ -+err_reset_stats: -+ debugfs_remove(priv->dbg.ch_stats); -+err_ch_stats: -+ debugfs_remove(priv->dbg.fq_stats); -+err_fq_stats: -+ debugfs_remove(priv->dbg.cpu_stats); -+err_cpu_stats: -+ debugfs_remove(priv->dbg.dir); -+} -+ -+void dpaa2_dbg_remove(struct dpaa2_eth_priv *priv) -+{ -+ debugfs_remove(priv->dbg.reset_stats); -+ debugfs_remove(priv->dbg.fq_stats); -+ debugfs_remove(priv->dbg.ch_stats); -+ debugfs_remove(priv->dbg.cpu_stats); -+ debugfs_remove(priv->dbg.dir); -+} -+ -+void dpaa2_eth_dbg_init(void) -+{ -+ dpaa2_dbg_root = debugfs_create_dir(DPAA2_ETH_DBG_ROOT, NULL); -+ if (!dpaa2_dbg_root) { -+ pr_err("DPAA2-ETH: debugfs create failed\n"); -+ return; -+ } -+ -+ pr_info("DPAA2-ETH: debugfs created\n"); -+} -+ -+void __exit dpaa2_eth_dbg_exit(void) -+{ -+ debugfs_remove(dpaa2_dbg_root); -+} -+ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.h -@@ -0,0 +1,61 @@ -+/* Copyright 2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef DPAA2_ETH_DEBUGFS_H -+#define DPAA2_ETH_DEBUGFS_H -+ -+#include -+#include "dpaa2-eth.h" -+ -+extern struct dpaa2_eth_priv *priv; -+ -+struct dpaa2_debugfs { -+ struct dentry *dir; -+ struct dentry *fq_stats; -+ struct dentry *ch_stats; -+ struct dentry *cpu_stats; -+ struct dentry *reset_stats; -+}; -+ -+#ifdef CONFIG_FSL_DPAA2_ETH_DEBUGFS -+void dpaa2_eth_dbg_init(void); -+void dpaa2_eth_dbg_exit(void); -+void dpaa2_dbg_add(struct dpaa2_eth_priv *priv); -+void dpaa2_dbg_remove(struct dpaa2_eth_priv *priv); -+#else -+static inline void dpaa2_eth_dbg_init(void) {} -+static inline void dpaa2_eth_dbg_exit(void) {} -+static inline void dpaa2_dbg_add(struct dpaa2_eth_priv *priv) {} -+static inline void dpaa2_dbg_remove(struct dpaa2_eth_priv *priv) {} -+#endif /* CONFIG_FSL_DPAA2_ETH_DEBUGFS */ -+ -+#endif /* DPAA2_ETH_DEBUGFS_H */ -+ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-trace.h -@@ -0,0 +1,185 @@ -+/* Copyright 2014-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#undef TRACE_SYSTEM -+#define TRACE_SYSTEM dpaa2_eth -+ -+#if !defined(_DPAA2_ETH_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) -+#define _DPAA2_ETH_TRACE_H -+ -+#include -+#include -+#include "dpaa2-eth.h" -+#include -+ -+#define TR_FMT "[%s] fd: addr=0x%llx, len=%u, off=%u" -+/* trace_printk format for raw buffer event class */ -+#define TR_BUF_FMT "[%s] vaddr=%p size=%zu dma_addr=%pad map_size=%zu bpid=%d" -+ -+/* This is used to declare a class of events. -+ * individual events of this type will be defined below. -+ */ -+ -+/* Store details about a frame descriptor */ -+DECLARE_EVENT_CLASS(dpaa2_eth_fd, -+ /* Trace function prototype */ -+ TP_PROTO(struct net_device *netdev, -+ const struct dpaa2_fd *fd), -+ -+ /* Repeat argument list here */ -+ TP_ARGS(netdev, fd), -+ -+ /* A structure containing the relevant information we want -+ * to record. Declare name and type for each normal element, -+ * name, type and size for arrays. Use __string for variable -+ * length strings. -+ */ -+ TP_STRUCT__entry( -+ __field(u64, fd_addr) -+ __field(u32, fd_len) -+ __field(u16, fd_offset) -+ __string(name, netdev->name) -+ ), -+ -+ /* The function that assigns values to the above declared -+ * fields -+ */ -+ TP_fast_assign( -+ __entry->fd_addr = dpaa2_fd_get_addr(fd); -+ __entry->fd_len = dpaa2_fd_get_len(fd); -+ __entry->fd_offset = dpaa2_fd_get_offset(fd); -+ __assign_str(name, netdev->name); -+ ), -+ -+ /* This is what gets printed when the trace event is -+ * triggered. -+ */ -+ TP_printk(TR_FMT, -+ __get_str(name), -+ __entry->fd_addr, -+ __entry->fd_len, -+ __entry->fd_offset) -+); -+ -+/* Now declare events of the above type. Format is: -+ * DEFINE_EVENT(class, name, proto, args), with proto and args same as for class -+ */ -+ -+/* Tx (egress) fd */ -+DEFINE_EVENT(dpaa2_eth_fd, dpaa2_tx_fd, -+ TP_PROTO(struct net_device *netdev, -+ const struct dpaa2_fd *fd), -+ -+ TP_ARGS(netdev, fd) -+); -+ -+/* Rx fd */ -+DEFINE_EVENT(dpaa2_eth_fd, dpaa2_rx_fd, -+ TP_PROTO(struct net_device *netdev, -+ const struct dpaa2_fd *fd), -+ -+ TP_ARGS(netdev, fd) -+); -+ -+/* Tx confirmation fd */ -+DEFINE_EVENT(dpaa2_eth_fd, dpaa2_tx_conf_fd, -+ TP_PROTO(struct net_device *netdev, -+ const struct dpaa2_fd *fd), -+ -+ TP_ARGS(netdev, fd) -+); -+ -+/* Log data about raw buffers. Useful for tracing DPBP content. */ -+TRACE_EVENT(dpaa2_eth_buf_seed, -+ /* Trace function prototype */ -+ TP_PROTO(struct net_device *netdev, -+ /* virtual address and size */ -+ void *vaddr, -+ size_t size, -+ /* dma map address and size */ -+ dma_addr_t dma_addr, -+ size_t map_size, -+ /* buffer pool id, if relevant */ -+ u16 bpid), -+ -+ /* Repeat argument list here */ -+ TP_ARGS(netdev, vaddr, size, dma_addr, map_size, bpid), -+ -+ /* A structure containing the relevant information we want -+ * to record. Declare name and type for each normal element, -+ * name, type and size for arrays. Use __string for variable -+ * length strings. -+ */ -+ TP_STRUCT__entry( -+ __field(void *, vaddr) -+ __field(size_t, size) -+ __field(dma_addr_t, dma_addr) -+ __field(size_t, map_size) -+ __field(u16, bpid) -+ __string(name, netdev->name) -+ ), -+ -+ /* The function that assigns values to the above declared -+ * fields -+ */ -+ TP_fast_assign( -+ __entry->vaddr = vaddr; -+ __entry->size = size; -+ __entry->dma_addr = dma_addr; -+ __entry->map_size = map_size; -+ __entry->bpid = bpid; -+ __assign_str(name, netdev->name); -+ ), -+ -+ /* This is what gets printed when the trace event is -+ * triggered. -+ */ -+ TP_printk(TR_BUF_FMT, -+ __get_str(name), -+ __entry->vaddr, -+ __entry->size, -+ &__entry->dma_addr, -+ __entry->map_size, -+ __entry->bpid) -+); -+ -+/* If only one event of a certain type needs to be declared, use TRACE_EVENT(). -+ * The syntax is the same as for DECLARE_EVENT_CLASS(). -+ */ -+ -+#endif /* _DPAA2_ETH_TRACE_H */ -+ -+/* This must be outside ifdef _DPAA2_ETH_TRACE_H */ -+#undef TRACE_INCLUDE_PATH -+#define TRACE_INCLUDE_PATH . -+#undef TRACE_INCLUDE_FILE -+#define TRACE_INCLUDE_FILE dpaa2-eth-trace -+#include ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c -@@ -0,0 +1,2793 @@ -+/* Copyright 2014-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../../fsl-mc/include/mc.h" -+#include "../../fsl-mc/include/mc-sys.h" -+#include "dpaa2-eth.h" -+ -+/* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files -+ * using trace events only need to #include -+ */ -+#define CREATE_TRACE_POINTS -+#include "dpaa2-eth-trace.h" -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("Freescale Semiconductor, Inc"); -+MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver"); -+ -+static int debug = -1; -+module_param(debug, int, S_IRUGO); -+MODULE_PARM_DESC(debug, "Module/Driver verbosity level"); -+ -+/* Oldest DPAA2 objects version we are compatible with */ -+#define DPAA2_SUPPORTED_DPNI_VERSION 6 -+#define DPAA2_SUPPORTED_DPBP_VERSION 2 -+#define DPAA2_SUPPORTED_DPCON_VERSION 2 -+ -+/* Iterate through the cpumask in a round-robin fashion. */ -+#define cpumask_rr(cpu, maskptr) \ -+do { \ -+ (cpu) = cpumask_next((cpu), (maskptr)); \ -+ if ((cpu) >= nr_cpu_ids) \ -+ (cpu) = cpumask_first((maskptr)); \ -+} while (0) -+ -+static void dpaa2_eth_rx_csum(struct dpaa2_eth_priv *priv, -+ u32 fd_status, -+ struct sk_buff *skb) -+{ -+ skb_checksum_none_assert(skb); -+ -+ /* HW checksum validation is disabled, nothing to do here */ -+ if (!(priv->net_dev->features & NETIF_F_RXCSUM)) -+ return; -+ -+ /* Read checksum validation bits */ -+ if (!((fd_status & DPAA2_ETH_FAS_L3CV) && -+ (fd_status & DPAA2_ETH_FAS_L4CV))) -+ return; -+ -+ /* Inform the stack there's no need to compute L3/L4 csum anymore */ -+ skb->ip_summed = CHECKSUM_UNNECESSARY; -+} -+ -+/* Free a received FD. -+ * Not to be used for Tx conf FDs or on any other paths. -+ */ -+static void dpaa2_eth_free_rx_fd(struct dpaa2_eth_priv *priv, -+ const struct dpaa2_fd *fd, -+ void *vaddr) -+{ -+ struct device *dev = priv->net_dev->dev.parent; -+ dma_addr_t addr = dpaa2_fd_get_addr(fd); -+ u8 fd_format = dpaa2_fd_get_format(fd); -+ -+ if (fd_format == dpaa2_fd_sg) { -+ struct dpaa2_sg_entry *sgt = vaddr + dpaa2_fd_get_offset(fd); -+ void *sg_vaddr; -+ int i; -+ -+ for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) { -+ dpaa2_sg_le_to_cpu(&sgt[i]); -+ -+ addr = dpaa2_sg_get_addr(&sgt[i]); -+ dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUFFER_SIZE, -+ DMA_FROM_DEVICE); -+ -+ sg_vaddr = phys_to_virt(addr); -+ put_page(virt_to_head_page(sg_vaddr)); -+ -+ if (dpaa2_sg_is_final(&sgt[i])) -+ break; -+ } -+ } -+ -+ put_page(virt_to_head_page(vaddr)); -+} -+ -+/* Build a linear skb based on a single-buffer frame descriptor */ -+static struct sk_buff *dpaa2_eth_build_linear_skb(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_channel *ch, -+ const struct dpaa2_fd *fd, -+ void *fd_vaddr) -+{ -+ struct sk_buff *skb = NULL; -+ u16 fd_offset = dpaa2_fd_get_offset(fd); -+ u32 fd_length = dpaa2_fd_get_len(fd); -+ -+ skb = build_skb(fd_vaddr, DPAA2_ETH_RX_BUFFER_SIZE + -+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); -+ if (unlikely(!skb)) { -+ netdev_err(priv->net_dev, "build_skb() failed\n"); -+ return NULL; -+ } -+ -+ skb_reserve(skb, fd_offset); -+ skb_put(skb, fd_length); -+ -+ ch->buf_count--; -+ -+ return skb; -+} -+ -+/* Build a non linear (fragmented) skb based on a S/G table */ -+static struct sk_buff *dpaa2_eth_build_frag_skb(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_channel *ch, -+ struct dpaa2_sg_entry *sgt) -+{ -+ struct sk_buff *skb = NULL; -+ struct device *dev = priv->net_dev->dev.parent; -+ void *sg_vaddr; -+ dma_addr_t sg_addr; -+ u16 sg_offset; -+ u32 sg_length; -+ struct page *page, *head_page; -+ int page_offset; -+ int i; -+ -+ for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) { -+ struct dpaa2_sg_entry *sge = &sgt[i]; -+ -+ dpaa2_sg_le_to_cpu(sge); -+ -+ /* We don't support anything else yet! */ -+ if (unlikely(dpaa2_sg_get_format(sge) != dpaa2_sg_single)) { -+ dev_warn_once(dev, "Unsupported S/G entry format: %d\n", -+ dpaa2_sg_get_format(sge)); -+ return NULL; -+ } -+ -+ /* Get the address, offset and length from the S/G entry */ -+ sg_addr = dpaa2_sg_get_addr(sge); -+ dma_unmap_single(dev, sg_addr, DPAA2_ETH_RX_BUFFER_SIZE, -+ DMA_FROM_DEVICE); -+ if (unlikely(dma_mapping_error(dev, sg_addr))) { -+ netdev_err(priv->net_dev, "DMA unmap failed\n"); -+ return NULL; -+ } -+ sg_vaddr = phys_to_virt(sg_addr); -+ sg_length = dpaa2_sg_get_len(sge); -+ -+ if (i == 0) { -+ /* We build the skb around the first data buffer */ -+ skb = build_skb(sg_vaddr, DPAA2_ETH_RX_BUFFER_SIZE + -+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); -+ if (unlikely(!skb)) { -+ netdev_err(priv->net_dev, "build_skb failed\n"); -+ return NULL; -+ } -+ sg_offset = dpaa2_sg_get_offset(sge); -+ skb_reserve(skb, sg_offset); -+ skb_put(skb, sg_length); -+ } else { -+ /* Subsequent data in SGEntries are stored at -+ * offset 0 in their buffers, we don't need to -+ * compute sg_offset. -+ */ -+ WARN_ONCE(dpaa2_sg_get_offset(sge) != 0, -+ "Non-zero offset in SGE[%d]!\n", i); -+ -+ /* Rest of the data buffers are stored as skb frags */ -+ page = virt_to_page(sg_vaddr); -+ head_page = virt_to_head_page(sg_vaddr); -+ -+ /* Offset in page (which may be compound) */ -+ page_offset = ((unsigned long)sg_vaddr & -+ (PAGE_SIZE - 1)) + -+ (page_address(page) - page_address(head_page)); -+ -+ skb_add_rx_frag(skb, i - 1, head_page, page_offset, -+ sg_length, DPAA2_ETH_RX_BUFFER_SIZE); -+ } -+ -+ if (dpaa2_sg_is_final(sge)) -+ break; -+ } -+ -+ /* Count all data buffers + sgt buffer */ -+ ch->buf_count -= i + 2; -+ -+ return skb; -+} -+ -+static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_channel *ch, -+ const struct dpaa2_fd *fd, -+ struct napi_struct *napi) -+{ -+ dma_addr_t addr = dpaa2_fd_get_addr(fd); -+ u8 fd_format = dpaa2_fd_get_format(fd); -+ void *vaddr; -+ struct sk_buff *skb; -+ struct rtnl_link_stats64 *percpu_stats; -+ struct dpaa2_eth_stats *percpu_extras; -+ struct device *dev = priv->net_dev->dev.parent; -+ struct dpaa2_fas *fas; -+ u32 status = 0; -+ -+ /* Tracing point */ -+ trace_dpaa2_rx_fd(priv->net_dev, fd); -+ -+ dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUFFER_SIZE, DMA_FROM_DEVICE); -+ vaddr = phys_to_virt(addr); -+ -+ prefetch(vaddr + priv->buf_layout.private_data_size); -+ prefetch(vaddr + dpaa2_fd_get_offset(fd)); -+ -+ percpu_stats = this_cpu_ptr(priv->percpu_stats); -+ percpu_extras = this_cpu_ptr(priv->percpu_extras); -+ -+ if (fd_format == dpaa2_fd_single) { -+ skb = dpaa2_eth_build_linear_skb(priv, ch, fd, vaddr); -+ } else if (fd_format == dpaa2_fd_sg) { -+ struct dpaa2_sg_entry *sgt = -+ vaddr + dpaa2_fd_get_offset(fd); -+ skb = dpaa2_eth_build_frag_skb(priv, ch, sgt); -+ put_page(virt_to_head_page(vaddr)); -+ percpu_extras->rx_sg_frames++; -+ percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd); -+ } else { -+ /* We don't support any other format */ -+ netdev_err(priv->net_dev, "Received invalid frame format\n"); -+ goto err_frame_format; -+ } -+ -+ if (unlikely(!skb)) { -+ dev_err_once(dev, "error building skb\n"); -+ goto err_build_skb; -+ } -+ -+ prefetch(skb->data); -+ -+ if (priv->ts_rx_en) { -+ struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); -+ u64 *ns = (u64 *) (vaddr + -+ priv->buf_layout.private_data_size + -+ sizeof(struct dpaa2_fas)); -+ -+ *ns = DPAA2_PTP_NOMINAL_FREQ_PERIOD_NS * (*ns); -+ memset(shhwtstamps, 0, sizeof(*shhwtstamps)); -+ shhwtstamps->hwtstamp = ns_to_ktime(*ns); -+ } -+ -+ /* Check if we need to validate the L4 csum */ -+ if (likely(fd->simple.frc & DPAA2_FD_FRC_FASV)) { -+ fas = (struct dpaa2_fas *) -+ (vaddr + priv->buf_layout.private_data_size); -+ status = le32_to_cpu(fas->status); -+ dpaa2_eth_rx_csum(priv, status, skb); -+ } -+ -+ skb->protocol = eth_type_trans(skb, priv->net_dev); -+ -+ percpu_stats->rx_packets++; -+ percpu_stats->rx_bytes += skb->len; -+ -+ if (priv->net_dev->features & NETIF_F_GRO) -+ napi_gro_receive(napi, skb); -+ else -+ netif_receive_skb(skb); -+ -+ return; -+err_frame_format: -+err_build_skb: -+ dpaa2_eth_free_rx_fd(priv, fd, vaddr); -+ percpu_stats->rx_dropped++; -+} -+ -+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE -+static void dpaa2_eth_rx_err(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_channel *ch, -+ const struct dpaa2_fd *fd, -+ struct napi_struct *napi __always_unused) -+{ -+ struct device *dev = priv->net_dev->dev.parent; -+ dma_addr_t addr = dpaa2_fd_get_addr(fd); -+ void *vaddr; -+ struct rtnl_link_stats64 *percpu_stats; -+ struct dpaa2_fas *fas; -+ u32 status = 0; -+ -+ dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUFFER_SIZE, DMA_FROM_DEVICE); -+ vaddr = phys_to_virt(addr); -+ -+ if (fd->simple.frc & DPAA2_FD_FRC_FASV) { -+ fas = (struct dpaa2_fas *) -+ (vaddr + priv->buf_layout.private_data_size); -+ status = le32_to_cpu(fas->status); -+ -+ /* All frames received on this queue should have at least -+ * one of the Rx error bits set */ -+ WARN_ON_ONCE((status & DPAA2_ETH_RX_ERR_MASK) == 0); -+ netdev_dbg(priv->net_dev, "Rx frame error: 0x%08x\n", -+ status & DPAA2_ETH_RX_ERR_MASK); -+ } -+ dpaa2_eth_free_rx_fd(priv, fd, vaddr); -+ -+ percpu_stats = this_cpu_ptr(priv->percpu_stats); -+ percpu_stats->rx_errors++; -+} -+#endif -+ -+/* Consume all frames pull-dequeued into the store. This is the simplest way to -+ * make sure we don't accidentally issue another volatile dequeue which would -+ * overwrite (leak) frames already in the store. -+ * -+ * Observance of NAPI budget is not our concern, leaving that to the caller. -+ */ -+static int dpaa2_eth_store_consume(struct dpaa2_eth_channel *ch) -+{ -+ struct dpaa2_eth_priv *priv = ch->priv; -+ struct dpaa2_eth_fq *fq; -+ struct dpaa2_dq *dq; -+ const struct dpaa2_fd *fd; -+ int cleaned = 0; -+ int is_last; -+ -+ do { -+ dq = dpaa2_io_store_next(ch->store, &is_last); -+ if (unlikely(!dq)) { -+ if (unlikely(!is_last)) { -+ netdev_dbg(priv->net_dev, -+ "Channel %d reqturned no valid frames\n", -+ ch->ch_id); -+ /* MUST retry until we get some sort of -+ * valid response token (be it "empty dequeue" -+ * or a valid frame). -+ */ -+ continue; -+ } -+ break; -+ } -+ -+ /* Obtain FD and process it */ -+ fd = dpaa2_dq_fd(dq); -+ fq = (struct dpaa2_eth_fq *)dpaa2_dq_fqd_ctx(dq); -+ fq->stats.frames++; -+ -+ fq->consume(priv, ch, fd, &ch->napi); -+ cleaned++; -+ } while (!is_last); -+ -+ return cleaned; -+} -+ -+static int dpaa2_eth_build_sg_fd(struct dpaa2_eth_priv *priv, -+ struct sk_buff *skb, -+ struct dpaa2_fd *fd) -+{ -+ struct device *dev = priv->net_dev->dev.parent; -+ void *sgt_buf = NULL; -+ dma_addr_t addr; -+ int nr_frags = skb_shinfo(skb)->nr_frags; -+ struct dpaa2_sg_entry *sgt; -+ int i, j, err; -+ int sgt_buf_size; -+ struct scatterlist *scl, *crt_scl; -+ int num_sg; -+ int num_dma_bufs; -+ struct dpaa2_eth_swa *bps; -+ -+ /* Create and map scatterlist. -+ * We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have -+ * to go beyond nr_frags+1. -+ * Note: We don't support chained scatterlists -+ */ -+ WARN_ON(PAGE_SIZE / sizeof(struct scatterlist) < nr_frags + 1); -+ scl = kcalloc(nr_frags + 1, sizeof(struct scatterlist), GFP_ATOMIC); -+ if (unlikely(!scl)) -+ return -ENOMEM; -+ -+ sg_init_table(scl, nr_frags + 1); -+ num_sg = skb_to_sgvec(skb, scl, 0, skb->len); -+ num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_TO_DEVICE); -+ if (unlikely(!num_dma_bufs)) { -+ netdev_err(priv->net_dev, "dma_map_sg() error\n"); -+ err = -ENOMEM; -+ goto dma_map_sg_failed; -+ } -+ -+ /* Prepare the HW SGT structure */ -+ sgt_buf_size = priv->tx_data_offset + -+ sizeof(struct dpaa2_sg_entry) * (1 + num_dma_bufs); -+ sgt_buf = kzalloc(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN, GFP_ATOMIC); -+ if (unlikely(!sgt_buf)) { -+ netdev_err(priv->net_dev, "failed to allocate SGT buffer\n"); -+ err = -ENOMEM; -+ goto sgt_buf_alloc_failed; -+ } -+ sgt_buf = PTR_ALIGN(sgt_buf, DPAA2_ETH_TX_BUF_ALIGN); -+ -+ /* PTA from egress side is passed as is to the confirmation side so -+ * we need to clear some fields here in order to find consistent values -+ * on TX confirmation. We are clearing FAS (Frame Annotation Status) -+ * field here. -+ */ -+ memset(sgt_buf + priv->buf_layout.private_data_size, 0, 8); -+ -+ sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset); -+ -+ /* Fill in the HW SGT structure. -+ * -+ * sgt_buf is zeroed out, so the following fields are implicit -+ * in all sgt entries: -+ * - offset is 0 -+ * - format is 'dpaa2_sg_single' -+ */ -+ for_each_sg(scl, crt_scl, num_dma_bufs, i) { -+ dpaa2_sg_set_addr(&sgt[i], sg_dma_address(crt_scl)); -+ dpaa2_sg_set_len(&sgt[i], sg_dma_len(crt_scl)); -+ } -+ dpaa2_sg_set_final(&sgt[i - 1], true); -+ -+ /* Store the skb backpointer in the SGT buffer. -+ * Fit the scatterlist and the number of buffers alongside the -+ * skb backpointer in the SWA. We'll need all of them on Tx Conf. -+ */ -+ bps = (struct dpaa2_eth_swa *)sgt_buf; -+ bps->skb = skb; -+ bps->scl = scl; -+ bps->num_sg = num_sg; -+ bps->num_dma_bufs = num_dma_bufs; -+ -+ for (j = 0; j < i; j++) -+ dpaa2_sg_cpu_to_le(&sgt[j]); -+ -+ /* Separately map the SGT buffer */ -+ addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_TO_DEVICE); -+ if (unlikely(dma_mapping_error(dev, addr))) { -+ netdev_err(priv->net_dev, "dma_map_single() failed\n"); -+ err = -ENOMEM; -+ goto dma_map_single_failed; -+ } -+ dpaa2_fd_set_offset(fd, priv->tx_data_offset); -+ dpaa2_fd_set_format(fd, dpaa2_fd_sg); -+ dpaa2_fd_set_addr(fd, addr); -+ dpaa2_fd_set_len(fd, skb->len); -+ -+ fd->simple.ctrl = DPAA2_FD_CTRL_ASAL | DPAA2_FD_CTRL_PTA | -+ DPAA2_FD_CTRL_PTV1; -+ -+ return 0; -+ -+dma_map_single_failed: -+ kfree(sgt_buf); -+sgt_buf_alloc_failed: -+ dma_unmap_sg(dev, scl, num_sg, DMA_TO_DEVICE); -+dma_map_sg_failed: -+ kfree(scl); -+ return err; -+} -+ -+static int dpaa2_eth_build_single_fd(struct dpaa2_eth_priv *priv, -+ struct sk_buff *skb, -+ struct dpaa2_fd *fd) -+{ -+ struct device *dev = priv->net_dev->dev.parent; -+ u8 *buffer_start; -+ struct sk_buff **skbh; -+ dma_addr_t addr; -+ -+ buffer_start = PTR_ALIGN(skb->data - priv->tx_data_offset - -+ DPAA2_ETH_TX_BUF_ALIGN, -+ DPAA2_ETH_TX_BUF_ALIGN); -+ -+ /* PTA from egress side is passed as is to the confirmation side so -+ * we need to clear some fields here in order to find consistent values -+ * on TX confirmation. We are clearing FAS (Frame Annotation Status) -+ * field here. -+ */ -+ memset(buffer_start + priv->buf_layout.private_data_size, 0, 8); -+ -+ /* Store a backpointer to the skb at the beginning of the buffer -+ * (in the private data area) such that we can release it -+ * on Tx confirm -+ */ -+ skbh = (struct sk_buff **)buffer_start; -+ *skbh = skb; -+ -+ addr = dma_map_single(dev, -+ buffer_start, -+ skb_tail_pointer(skb) - buffer_start, -+ DMA_TO_DEVICE); -+ if (unlikely(dma_mapping_error(dev, addr))) { -+ dev_err(dev, "dma_map_single() failed\n"); -+ return -EINVAL; -+ } -+ -+ dpaa2_fd_set_addr(fd, addr); -+ dpaa2_fd_set_offset(fd, (u16)(skb->data - buffer_start)); -+ dpaa2_fd_set_len(fd, skb->len); -+ dpaa2_fd_set_format(fd, dpaa2_fd_single); -+ -+ fd->simple.ctrl = DPAA2_FD_CTRL_ASAL | DPAA2_FD_CTRL_PTA | -+ DPAA2_FD_CTRL_PTV1; -+ -+ return 0; -+} -+ -+/* DMA-unmap and free FD and possibly SGT buffer allocated on Tx. The skb -+ * back-pointed to is also freed. -+ * This can be called either from dpaa2_eth_tx_conf() or on the error path of -+ * dpaa2_eth_tx(). -+ * Optionally, return the frame annotation status word (FAS), which needs -+ * to be checked if we're on the confirmation path. -+ */ -+static void dpaa2_eth_free_fd(const struct dpaa2_eth_priv *priv, -+ const struct dpaa2_fd *fd, -+ u32 *status) -+{ -+ struct device *dev = priv->net_dev->dev.parent; -+ dma_addr_t fd_addr; -+ struct sk_buff **skbh, *skb; -+ unsigned char *buffer_start; -+ int unmap_size; -+ struct scatterlist *scl; -+ int num_sg, num_dma_bufs; -+ struct dpaa2_eth_swa *bps; -+ bool fd_single; -+ struct dpaa2_fas *fas; -+ -+ fd_addr = dpaa2_fd_get_addr(fd); -+ skbh = phys_to_virt(fd_addr); -+ fd_single = (dpaa2_fd_get_format(fd) == dpaa2_fd_single); -+ -+ if (fd_single) { -+ skb = *skbh; -+ buffer_start = (unsigned char *)skbh; -+ /* Accessing the skb buffer is safe before dma unmap, because -+ * we didn't map the actual skb shell. -+ */ -+ dma_unmap_single(dev, fd_addr, -+ skb_tail_pointer(skb) - buffer_start, -+ DMA_TO_DEVICE); -+ } else { -+ bps = (struct dpaa2_eth_swa *)skbh; -+ skb = bps->skb; -+ scl = bps->scl; -+ num_sg = bps->num_sg; -+ num_dma_bufs = bps->num_dma_bufs; -+ -+ /* Unmap the scatterlist */ -+ dma_unmap_sg(dev, scl, num_sg, DMA_TO_DEVICE); -+ kfree(scl); -+ -+ /* Unmap the SGT buffer */ -+ unmap_size = priv->tx_data_offset + -+ sizeof(struct dpaa2_sg_entry) * (1 + num_dma_bufs); -+ dma_unmap_single(dev, fd_addr, unmap_size, DMA_TO_DEVICE); -+ } -+ -+ if (priv->ts_tx_en && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { -+ struct skb_shared_hwtstamps shhwtstamps; -+ u64 *ns; -+ -+ memset(&shhwtstamps, 0, sizeof(shhwtstamps)); -+ -+ ns = (u64 *)((void *)skbh + -+ priv->buf_layout.private_data_size + -+ sizeof(struct dpaa2_fas)); -+ *ns = DPAA2_PTP_NOMINAL_FREQ_PERIOD_NS * (*ns); -+ shhwtstamps.hwtstamp = ns_to_ktime(*ns); -+ skb_tstamp_tx(skb, &shhwtstamps); -+ } -+ -+ /* Check the status from the Frame Annotation after we unmap the first -+ * buffer but before we free it. -+ */ -+ if (status && (fd->simple.frc & DPAA2_FD_FRC_FASV)) { -+ fas = (struct dpaa2_fas *) -+ ((void *)skbh + priv->buf_layout.private_data_size); -+ *status = le32_to_cpu(fas->status); -+ } -+ -+ /* Free SGT buffer kmalloc'ed on tx */ -+ if (!fd_single) -+ kfree(skbh); -+ -+ /* Move on with skb release */ -+ dev_kfree_skb(skb); -+} -+ -+static int dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ struct dpaa2_fd fd; -+ struct rtnl_link_stats64 *percpu_stats; -+ struct dpaa2_eth_stats *percpu_extras; -+ int err, i; -+ /* TxConf FQ selection primarily based on cpu affinity; this is -+ * non-migratable context, so it's safe to call smp_processor_id(). -+ */ -+ u16 queue_mapping = smp_processor_id() % priv->dpni_attrs.max_senders; -+ -+ percpu_stats = this_cpu_ptr(priv->percpu_stats); -+ percpu_extras = this_cpu_ptr(priv->percpu_extras); -+ -+ /* Setup the FD fields */ -+ memset(&fd, 0, sizeof(fd)); -+ -+ if (unlikely(skb_headroom(skb) < DPAA2_ETH_NEEDED_HEADROOM(priv))) { -+ struct sk_buff *ns; -+ -+ dev_info_once(net_dev->dev.parent, -+ "skb headroom too small, must realloc.\n"); -+ ns = skb_realloc_headroom(skb, DPAA2_ETH_NEEDED_HEADROOM(priv)); -+ if (unlikely(!ns)) { -+ percpu_stats->tx_dropped++; -+ goto err_alloc_headroom; -+ } -+ dev_kfree_skb(skb); -+ skb = ns; -+ } -+ -+ /* We'll be holding a back-reference to the skb until Tx Confirmation; -+ * we don't want that overwritten by a concurrent Tx with a cloned skb. -+ */ -+ skb = skb_unshare(skb, GFP_ATOMIC); -+ if (unlikely(!skb)) { -+ netdev_err(net_dev, "Out of memory for skb_unshare()"); -+ /* skb_unshare() has already freed the skb */ -+ percpu_stats->tx_dropped++; -+ return NETDEV_TX_OK; -+ } -+ -+ if (skb_is_nonlinear(skb)) { -+ err = dpaa2_eth_build_sg_fd(priv, skb, &fd); -+ percpu_extras->tx_sg_frames++; -+ percpu_extras->tx_sg_bytes += skb->len; -+ } else { -+ err = dpaa2_eth_build_single_fd(priv, skb, &fd); -+ } -+ -+ if (unlikely(err)) { -+ percpu_stats->tx_dropped++; -+ goto err_build_fd; -+ } -+ -+ /* Tracing point */ -+ trace_dpaa2_tx_fd(net_dev, &fd); -+ -+ for (i = 0; i < (DPAA2_ETH_MAX_TX_QUEUES << 1); i++) { -+ err = dpaa2_io_service_enqueue_qd(NULL, priv->tx_qdid, 0, -+ priv->fq[queue_mapping].flowid, -+ &fd); -+ if (err != -EBUSY) -+ break; -+ } -+ percpu_extras->tx_portal_busy += i; -+ if (unlikely(err < 0)) { -+ netdev_dbg(net_dev, "error enqueueing Tx frame\n"); -+ percpu_stats->tx_errors++; -+ /* Clean up everything, including freeing the skb */ -+ dpaa2_eth_free_fd(priv, &fd, NULL); -+ } else { -+ percpu_stats->tx_packets++; -+ percpu_stats->tx_bytes += skb->len; -+ } -+ -+ return NETDEV_TX_OK; -+ -+err_build_fd: -+err_alloc_headroom: -+ dev_kfree_skb(skb); -+ -+ return NETDEV_TX_OK; -+} -+ -+static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_channel *ch, -+ const struct dpaa2_fd *fd, -+ struct napi_struct *napi __always_unused) -+{ -+ struct rtnl_link_stats64 *percpu_stats; -+ struct dpaa2_eth_stats *percpu_extras; -+ u32 status = 0; -+ -+ /* Tracing point */ -+ trace_dpaa2_tx_conf_fd(priv->net_dev, fd); -+ -+ percpu_extras = this_cpu_ptr(priv->percpu_extras); -+ percpu_extras->tx_conf_frames++; -+ percpu_extras->tx_conf_bytes += dpaa2_fd_get_len(fd); -+ -+ dpaa2_eth_free_fd(priv, fd, &status); -+ -+ if (unlikely(status & DPAA2_ETH_TXCONF_ERR_MASK)) { -+ netdev_err(priv->net_dev, "TxConf frame error(s): 0x%08x\n", -+ status & DPAA2_ETH_TXCONF_ERR_MASK); -+ percpu_stats = this_cpu_ptr(priv->percpu_stats); -+ /* Tx-conf logically pertains to the egress path. */ -+ percpu_stats->tx_errors++; -+ } -+} -+ -+static int dpaa2_eth_set_rx_csum(struct dpaa2_eth_priv *priv, bool enable) -+{ -+ int err; -+ -+ err = dpni_set_l3_chksum_validation(priv->mc_io, 0, priv->mc_token, -+ enable); -+ if (err) { -+ netdev_err(priv->net_dev, -+ "dpni_set_l3_chksum_validation() failed\n"); -+ return err; -+ } -+ -+ err = dpni_set_l4_chksum_validation(priv->mc_io, 0, priv->mc_token, -+ enable); -+ if (err) { -+ netdev_err(priv->net_dev, -+ "dpni_set_l4_chksum_validation failed\n"); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int dpaa2_eth_set_tx_csum(struct dpaa2_eth_priv *priv, bool enable) -+{ -+ struct dpaa2_eth_fq *fq; -+ struct dpni_tx_flow_cfg tx_flow_cfg; -+ int err; -+ int i; -+ -+ memset(&tx_flow_cfg, 0, sizeof(tx_flow_cfg)); -+ tx_flow_cfg.options = DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN | -+ DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN; -+ tx_flow_cfg.l3_chksum_gen = enable; -+ tx_flow_cfg.l4_chksum_gen = enable; -+ -+ for (i = 0; i < priv->num_fqs; i++) { -+ fq = &priv->fq[i]; -+ if (fq->type != DPAA2_TX_CONF_FQ) -+ continue; -+ -+ /* The Tx flowid is kept in the corresponding TxConf FQ. */ -+ err = dpni_set_tx_flow(priv->mc_io, 0, priv->mc_token, -+ &fq->flowid, &tx_flow_cfg); -+ if (err) { -+ netdev_err(priv->net_dev, "dpni_set_tx_flow failed\n"); -+ return err; -+ } -+ } -+ -+ return 0; -+} -+ -+static int dpaa2_bp_add_7(struct dpaa2_eth_priv *priv, u16 bpid) -+{ -+ struct device *dev = priv->net_dev->dev.parent; -+ u64 buf_array[7]; -+ void *buf; -+ dma_addr_t addr; -+ int i; -+ -+ for (i = 0; i < 7; i++) { -+ /* Allocate buffer visible to WRIOP + skb shared info + -+ * alignment padding -+ */ -+ buf = napi_alloc_frag(DPAA2_ETH_BUF_RAW_SIZE); -+ if (unlikely(!buf)) { -+ dev_err(dev, "buffer allocation failed\n"); -+ goto err_alloc; -+ } -+ buf = PTR_ALIGN(buf, DPAA2_ETH_RX_BUF_ALIGN); -+ -+ addr = dma_map_single(dev, buf, DPAA2_ETH_RX_BUFFER_SIZE, -+ DMA_FROM_DEVICE); -+ if (unlikely(dma_mapping_error(dev, addr))) { -+ dev_err(dev, "dma_map_single() failed\n"); -+ goto err_map; -+ } -+ buf_array[i] = addr; -+ -+ /* tracing point */ -+ trace_dpaa2_eth_buf_seed(priv->net_dev, -+ buf, DPAA2_ETH_BUF_RAW_SIZE, -+ addr, DPAA2_ETH_RX_BUFFER_SIZE, -+ bpid); -+ } -+ -+release_bufs: -+ /* In case the portal is busy, retry until successful. -+ * The buffer release function would only fail if the QBMan portal -+ * was busy, which implies portal contention (i.e. more CPUs than -+ * portals, i.e. GPPs w/o affine DPIOs). For all practical purposes, -+ * there is little we can realistically do, short of giving up - -+ * in which case we'd risk depleting the buffer pool and never again -+ * receiving the Rx interrupt which would kick-start the refill logic. -+ * So just keep retrying, at the risk of being moved to ksoftirqd. -+ */ -+ while (dpaa2_io_service_release(NULL, bpid, buf_array, i)) -+ cpu_relax(); -+ return i; -+ -+err_map: -+ put_page(virt_to_head_page(buf)); -+err_alloc: -+ if (i) -+ goto release_bufs; -+ -+ return 0; -+} -+ -+static int dpaa2_dpbp_seed(struct dpaa2_eth_priv *priv, u16 bpid) -+{ -+ int i, j; -+ int new_count; -+ -+ /* This is the lazy seeding of Rx buffer pools. -+ * dpaa2_bp_add_7() is also used on the Rx hotpath and calls -+ * napi_alloc_frag(). The trouble with that is that it in turn ends up -+ * calling this_cpu_ptr(), which mandates execution in atomic context. -+ * Rather than splitting up the code, do a one-off preempt disable. -+ */ -+ preempt_disable(); -+ for (j = 0; j < priv->num_channels; j++) { -+ for (i = 0; i < DPAA2_ETH_NUM_BUFS; i += 7) { -+ new_count = dpaa2_bp_add_7(priv, bpid); -+ priv->channel[j]->buf_count += new_count; -+ -+ if (new_count < 7) { -+ preempt_enable(); -+ goto out_of_memory; -+ } -+ } -+ } -+ preempt_enable(); -+ -+ return 0; -+ -+out_of_memory: -+ return -ENOMEM; -+} -+ -+/** -+ * Drain the specified number of buffers from the DPNI's private buffer pool. -+ * @count must not exceeed 7 -+ */ -+static void dpaa2_dpbp_drain_cnt(struct dpaa2_eth_priv *priv, int count) -+{ -+ struct device *dev = priv->net_dev->dev.parent; -+ u64 buf_array[7]; -+ void *vaddr; -+ int ret, i; -+ -+ do { -+ ret = dpaa2_io_service_acquire(NULL, priv->dpbp_attrs.bpid, -+ buf_array, count); -+ if (ret < 0) { -+ pr_err("dpaa2_io_service_acquire() failed\n"); -+ return; -+ } -+ for (i = 0; i < ret; i++) { -+ /* Same logic as on regular Rx path */ -+ dma_unmap_single(dev, buf_array[i], -+ DPAA2_ETH_RX_BUFFER_SIZE, -+ DMA_FROM_DEVICE); -+ vaddr = phys_to_virt(buf_array[i]); -+ put_page(virt_to_head_page(vaddr)); -+ } -+ } while (ret); -+} -+ -+static void __dpaa2_dpbp_free(struct dpaa2_eth_priv *priv) -+{ -+ int i; -+ -+ dpaa2_dpbp_drain_cnt(priv, 7); -+ dpaa2_dpbp_drain_cnt(priv, 1); -+ -+ for (i = 0; i < priv->num_channels; i++) -+ priv->channel[i]->buf_count = 0; -+} -+ -+/* Function is called from softirq context only, so we don't need to guard -+ * the access to percpu count -+ */ -+static int dpaa2_dpbp_refill(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_channel *ch, -+ u16 bpid) -+{ -+ int new_count; -+ int err = 0; -+ -+ if (unlikely(ch->buf_count < DPAA2_ETH_REFILL_THRESH)) { -+ do { -+ new_count = dpaa2_bp_add_7(priv, bpid); -+ if (unlikely(!new_count)) { -+ /* Out of memory; abort for now, we'll -+ * try later on -+ */ -+ break; -+ } -+ ch->buf_count += new_count; -+ } while (ch->buf_count < DPAA2_ETH_NUM_BUFS); -+ -+ if (unlikely(ch->buf_count < DPAA2_ETH_NUM_BUFS)) -+ err = -ENOMEM; -+ } -+ -+ return err; -+} -+ -+static int __dpaa2_eth_pull_channel(struct dpaa2_eth_channel *ch) -+{ -+ int err; -+ int dequeues = -1; -+ struct dpaa2_eth_priv *priv = ch->priv; -+ -+ /* Retry while portal is busy */ -+ do { -+ err = dpaa2_io_service_pull_channel(NULL, ch->ch_id, ch->store); -+ dequeues++; -+ } while (err == -EBUSY); -+ if (unlikely(err)) -+ netdev_err(priv->net_dev, "dpaa2_io_service_pull err %d", err); -+ -+ ch->stats.dequeue_portal_busy += dequeues; -+ return err; -+} -+ -+static int dpaa2_eth_poll(struct napi_struct *napi, int budget) -+{ -+ struct dpaa2_eth_channel *ch; -+ int cleaned = 0, store_cleaned; -+ struct dpaa2_eth_priv *priv; -+ int err; -+ -+ ch = container_of(napi, struct dpaa2_eth_channel, napi); -+ priv = ch->priv; -+ -+ __dpaa2_eth_pull_channel(ch); -+ -+ do { -+ /* Refill pool if appropriate */ -+ dpaa2_dpbp_refill(priv, ch, priv->dpbp_attrs.bpid); -+ -+ store_cleaned = dpaa2_eth_store_consume(ch); -+ cleaned += store_cleaned; -+ -+ if (store_cleaned == 0 || -+ cleaned > budget - DPAA2_ETH_STORE_SIZE) -+ break; -+ -+ /* Try to dequeue some more */ -+ err = __dpaa2_eth_pull_channel(ch); -+ if (unlikely(err)) -+ break; -+ } while (1); -+ -+ if (cleaned < budget) { -+ napi_complete_done(napi, cleaned); -+ err = dpaa2_io_service_rearm(NULL, &ch->nctx); -+ if (unlikely(err)) -+ netdev_err(priv->net_dev, -+ "Notif rearm failed for channel %d\n", -+ ch->ch_id); -+ } -+ -+ ch->stats.frames += cleaned; -+ -+ return cleaned; -+} -+ -+static void dpaa2_eth_napi_enable(struct dpaa2_eth_priv *priv) -+{ -+ struct dpaa2_eth_channel *ch; -+ int i; -+ -+ for (i = 0; i < priv->num_channels; i++) { -+ ch = priv->channel[i]; -+ napi_enable(&ch->napi); -+ } -+} -+ -+static void dpaa2_eth_napi_disable(struct dpaa2_eth_priv *priv) -+{ -+ struct dpaa2_eth_channel *ch; -+ int i; -+ -+ for (i = 0; i < priv->num_channels; i++) { -+ ch = priv->channel[i]; -+ napi_disable(&ch->napi); -+ } -+} -+ -+static int dpaa2_link_state_update(struct dpaa2_eth_priv *priv) -+{ -+ struct dpni_link_state state; -+ int err; -+ -+ err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state); -+ if (unlikely(err)) { -+ netdev_err(priv->net_dev, -+ "dpni_get_link_state() failed\n"); -+ return err; -+ } -+ -+ /* Chech link state; speed / duplex changes are not treated yet */ -+ if (priv->link_state.up == state.up) -+ return 0; -+ -+ priv->link_state = state; -+ if (state.up) { -+ netif_carrier_on(priv->net_dev); -+ netif_tx_start_all_queues(priv->net_dev); -+ } else { -+ netif_tx_stop_all_queues(priv->net_dev); -+ netif_carrier_off(priv->net_dev); -+ } -+ -+ netdev_info(priv->net_dev, "Link Event: state %s", -+ state.up ? "up" : "down"); -+ -+ return 0; -+} -+ -+static int dpaa2_eth_open(struct net_device *net_dev) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ int err; -+ -+ err = dpaa2_dpbp_seed(priv, priv->dpbp_attrs.bpid); -+ if (err) { -+ /* Not much to do; the buffer pool, though not filled up, -+ * may still contain some buffers which would enable us -+ * to limp on. -+ */ -+ netdev_err(net_dev, "Buffer seeding failed for DPBP %d (bpid=%d)\n", -+ priv->dpbp_dev->obj_desc.id, priv->dpbp_attrs.bpid); -+ } -+ -+ /* We'll only start the txqs when the link is actually ready; make sure -+ * we don't race against the link up notification, which may come -+ * immediately after dpni_enable(); -+ */ -+ netif_tx_stop_all_queues(net_dev); -+ dpaa2_eth_napi_enable(priv); -+ /* Also, explicitly set carrier off, otherwise netif_carrier_ok() will -+ * return true and cause 'ip link show' to report the LOWER_UP flag, -+ * even though the link notification wasn't even received. -+ */ -+ netif_carrier_off(net_dev); -+ -+ err = dpni_enable(priv->mc_io, 0, priv->mc_token); -+ if (err < 0) { -+ dev_err(net_dev->dev.parent, "dpni_enable() failed\n"); -+ goto enable_err; -+ } -+ -+ /* If the DPMAC object has already processed the link up interrupt, -+ * we have to learn the link state ourselves. -+ */ -+ err = dpaa2_link_state_update(priv); -+ if (err < 0) { -+ dev_err(net_dev->dev.parent, "Can't update link state\n"); -+ goto link_state_err; -+ } -+ -+ return 0; -+ -+link_state_err: -+enable_err: -+ dpaa2_eth_napi_disable(priv); -+ __dpaa2_dpbp_free(priv); -+ return err; -+} -+ -+static int dpaa2_eth_stop(struct net_device *net_dev) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ -+ /* Stop Tx and Rx traffic */ -+ netif_tx_stop_all_queues(net_dev); -+ netif_carrier_off(net_dev); -+ dpni_disable(priv->mc_io, 0, priv->mc_token); -+ -+ msleep(500); -+ -+ dpaa2_eth_napi_disable(priv); -+ msleep(100); -+ -+ __dpaa2_dpbp_free(priv); -+ -+ return 0; -+} -+ -+static int dpaa2_eth_init(struct net_device *net_dev) -+{ -+ u64 supported = 0; -+ u64 not_supported = 0; -+ const struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ u32 options = priv->dpni_attrs.options; -+ -+ /* Capabilities listing */ -+ supported |= IFF_LIVE_ADDR_CHANGE | IFF_PROMISC | IFF_ALLMULTI; -+ -+ if (options & DPNI_OPT_UNICAST_FILTER) -+ supported |= IFF_UNICAST_FLT; -+ else -+ not_supported |= IFF_UNICAST_FLT; -+ -+ if (options & DPNI_OPT_MULTICAST_FILTER) -+ supported |= IFF_MULTICAST; -+ else -+ not_supported |= IFF_MULTICAST; -+ -+ net_dev->priv_flags |= supported; -+ net_dev->priv_flags &= ~not_supported; -+ -+ /* Features */ -+ net_dev->features = NETIF_F_RXCSUM | -+ NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | -+ NETIF_F_SG | NETIF_F_HIGHDMA | -+ NETIF_F_LLTX; -+ net_dev->hw_features = net_dev->features; -+ -+ return 0; -+} -+ -+static int dpaa2_eth_set_addr(struct net_device *net_dev, void *addr) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ struct device *dev = net_dev->dev.parent; -+ int err; -+ -+ err = eth_mac_addr(net_dev, addr); -+ if (err < 0) { -+ dev_err(dev, "eth_mac_addr() failed with error %d\n", err); -+ return err; -+ } -+ -+ err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token, -+ net_dev->dev_addr); -+ if (err) { -+ dev_err(dev, "dpni_set_primary_mac_addr() failed (%d)\n", err); -+ return err; -+ } -+ -+ return 0; -+} -+ -+/** Fill in counters maintained by the GPP driver. These may be different from -+ * the hardware counters obtained by ethtool. -+ */ -+static struct rtnl_link_stats64 -+*dpaa2_eth_get_stats(struct net_device *net_dev, -+ struct rtnl_link_stats64 *stats) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ struct rtnl_link_stats64 *percpu_stats; -+ u64 *cpustats; -+ u64 *netstats = (u64 *)stats; -+ int i, j; -+ int num = sizeof(struct rtnl_link_stats64) / sizeof(u64); -+ -+ for_each_possible_cpu(i) { -+ percpu_stats = per_cpu_ptr(priv->percpu_stats, i); -+ cpustats = (u64 *)percpu_stats; -+ for (j = 0; j < num; j++) -+ netstats[j] += cpustats[j]; -+ } -+ -+ return stats; -+} -+ -+static int dpaa2_eth_change_mtu(struct net_device *net_dev, int mtu) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ int err; -+ -+ if (mtu < 68 || mtu > DPAA2_ETH_MAX_MTU) { -+ netdev_err(net_dev, "Invalid MTU %d. Valid range is: 68..%d\n", -+ mtu, DPAA2_ETH_MAX_MTU); -+ return -EINVAL; -+ } -+ -+ /* Set the maximum Rx frame length to match the transmit side; -+ * account for L2 headers when computing the MFL -+ */ -+ err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token, -+ (u16)DPAA2_ETH_L2_MAX_FRM(mtu)); -+ if (err) { -+ netdev_err(net_dev, "dpni_set_mfl() failed\n"); -+ return err; -+ } -+ -+ net_dev->mtu = mtu; -+ return 0; -+} -+ -+/* Convenience macro to make code littered with error checking more readable */ -+#define DPAA2_ETH_WARN_IF_ERR(err, netdevp, format, ...) \ -+do { \ -+ if (err) \ -+ netdev_warn(netdevp, format, ##__VA_ARGS__); \ -+} while (0) -+ -+/* Copy mac unicast addresses from @net_dev to @priv. -+ * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable. -+ */ -+static void _dpaa2_eth_hw_add_uc_addr(const struct net_device *net_dev, -+ struct dpaa2_eth_priv *priv) -+{ -+ struct netdev_hw_addr *ha; -+ int err; -+ -+ netdev_for_each_uc_addr(ha, net_dev) { -+ err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, -+ ha->addr); -+ DPAA2_ETH_WARN_IF_ERR(err, priv->net_dev, -+ "Could not add ucast MAC %pM to the filtering table (err %d)\n", -+ ha->addr, err); -+ } -+} -+ -+/* Copy mac multicast addresses from @net_dev to @priv -+ * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable. -+ */ -+static void _dpaa2_eth_hw_add_mc_addr(const struct net_device *net_dev, -+ struct dpaa2_eth_priv *priv) -+{ -+ struct netdev_hw_addr *ha; -+ int err; -+ -+ netdev_for_each_mc_addr(ha, net_dev) { -+ err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, -+ ha->addr); -+ DPAA2_ETH_WARN_IF_ERR(err, priv->net_dev, -+ "Could not add mcast MAC %pM to the filtering table (err %d)\n", -+ ha->addr, err); -+ } -+} -+ -+static void dpaa2_eth_set_rx_mode(struct net_device *net_dev) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ int uc_count = netdev_uc_count(net_dev); -+ int mc_count = netdev_mc_count(net_dev); -+ u8 max_uc = priv->dpni_attrs.max_unicast_filters; -+ u8 max_mc = priv->dpni_attrs.max_multicast_filters; -+ u32 options = priv->dpni_attrs.options; -+ u16 mc_token = priv->mc_token; -+ struct fsl_mc_io *mc_io = priv->mc_io; -+ int err; -+ -+ /* Basic sanity checks; these probably indicate a misconfiguration */ -+ if (!(options & DPNI_OPT_UNICAST_FILTER) && max_uc != 0) -+ netdev_info(net_dev, -+ "max_unicast_filters=%d, you must have DPNI_OPT_UNICAST_FILTER in the DPL\n", -+ max_uc); -+ if (!(options & DPNI_OPT_MULTICAST_FILTER) && max_mc != 0) -+ netdev_info(net_dev, -+ "max_multicast_filters=%d, you must have DPNI_OPT_MULTICAST_FILTER in the DPL\n", -+ max_mc); -+ -+ /* Force promiscuous if the uc or mc counts exceed our capabilities. */ -+ if (uc_count > max_uc) { -+ netdev_info(net_dev, -+ "Unicast addr count reached %d, max allowed is %d; forcing promisc\n", -+ uc_count, max_uc); -+ goto force_promisc; -+ } -+ if (mc_count > max_mc) { -+ netdev_info(net_dev, -+ "Multicast addr count reached %d, max allowed is %d; forcing promisc\n", -+ mc_count, max_mc); -+ goto force_mc_promisc; -+ } -+ -+ /* Adjust promisc settings due to flag combinations */ -+ if (net_dev->flags & IFF_PROMISC) { -+ goto force_promisc; -+ } else if (net_dev->flags & IFF_ALLMULTI) { -+ /* First, rebuild unicast filtering table. This should be done -+ * in promisc mode, in order to avoid frame loss while we -+ * progressively add entries to the table. -+ * We don't know whether we had been in promisc already, and -+ * making an MC call to find it is expensive; so set uc promisc -+ * nonetheless. -+ */ -+ err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1); -+ DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't set uc promisc\n"); -+ -+ /* Actual uc table reconstruction. */ -+ err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 0); -+ DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't clear uc filters\n"); -+ _dpaa2_eth_hw_add_uc_addr(net_dev, priv); -+ -+ /* Finally, clear uc promisc and set mc promisc as requested. */ -+ err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0); -+ DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't clear uc promisc\n"); -+ goto force_mc_promisc; -+ } -+ -+ /* Neither unicast, nor multicast promisc will be on... eventually. -+ * For now, rebuild mac filtering tables while forcing both of them on. -+ */ -+ err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1); -+ DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't set uc promisc (%d)\n", err); -+ err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1); -+ DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't set mc promisc (%d)\n", err); -+ -+ /* Actual mac filtering tables reconstruction */ -+ err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 1); -+ DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't clear mac filters\n"); -+ _dpaa2_eth_hw_add_mc_addr(net_dev, priv); -+ _dpaa2_eth_hw_add_uc_addr(net_dev, priv); -+ -+ /* Now we can clear both ucast and mcast promisc, without risking -+ * to drop legitimate frames anymore. -+ */ -+ err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0); -+ DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't clear ucast promisc\n"); -+ err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 0); -+ DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't clear mcast promisc\n"); -+ -+ return; -+ -+force_promisc: -+ err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1); -+ DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't set ucast promisc\n"); -+force_mc_promisc: -+ err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1); -+ DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't set mcast promisc\n"); -+} -+ -+static int dpaa2_eth_set_features(struct net_device *net_dev, -+ netdev_features_t features) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ netdev_features_t changed = features ^ net_dev->features; -+ int err; -+ -+ if (changed & NETIF_F_RXCSUM) { -+ bool enable = !!(features & NETIF_F_RXCSUM); -+ -+ err = dpaa2_eth_set_rx_csum(priv, enable); -+ if (err) -+ return err; -+ } -+ -+ if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) { -+ bool enable = !!(features & -+ (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); -+ err = dpaa2_eth_set_tx_csum(priv, enable); -+ if (err) -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int dpaa2_eth_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(dev); -+ struct hwtstamp_config config; -+ -+ if (copy_from_user(&config, rq->ifr_data, sizeof(config))) -+ return -EFAULT; -+ -+ switch (config.tx_type) { -+ case HWTSTAMP_TX_OFF: -+ priv->ts_tx_en = false; -+ break; -+ case HWTSTAMP_TX_ON: -+ priv->ts_tx_en = true; -+ break; -+ default: -+ return -ERANGE; -+ } -+ -+ if (config.rx_filter == HWTSTAMP_FILTER_NONE) -+ priv->ts_rx_en = false; -+ else { -+ priv->ts_rx_en = true; -+ /* TS is set for all frame types, not only those requested */ -+ config.rx_filter = HWTSTAMP_FILTER_ALL; -+ } -+ -+ return copy_to_user(rq->ifr_data, &config, sizeof(config)) ? -+ -EFAULT : 0; -+} -+ -+static int dpaa2_eth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -+{ -+ if (cmd == SIOCSHWTSTAMP) -+ return dpaa2_eth_ts_ioctl(dev, rq, cmd); -+ else -+ return -EINVAL; -+} -+ -+static const struct net_device_ops dpaa2_eth_ops = { -+ .ndo_open = dpaa2_eth_open, -+ .ndo_start_xmit = dpaa2_eth_tx, -+ .ndo_stop = dpaa2_eth_stop, -+ .ndo_init = dpaa2_eth_init, -+ .ndo_set_mac_address = dpaa2_eth_set_addr, -+ .ndo_get_stats64 = dpaa2_eth_get_stats, -+ .ndo_change_mtu = dpaa2_eth_change_mtu, -+ .ndo_set_rx_mode = dpaa2_eth_set_rx_mode, -+ .ndo_set_features = dpaa2_eth_set_features, -+ .ndo_do_ioctl = dpaa2_eth_ioctl, -+}; -+ -+static void dpaa2_eth_cdan_cb(struct dpaa2_io_notification_ctx *ctx) -+{ -+ struct dpaa2_eth_channel *ch; -+ -+ ch = container_of(ctx, struct dpaa2_eth_channel, nctx); -+ -+ /* Update NAPI statistics */ -+ ch->stats.cdan++; -+ -+ napi_schedule_irqoff(&ch->napi); -+} -+ -+static void dpaa2_eth_setup_fqs(struct dpaa2_eth_priv *priv) -+{ -+ int i; -+ -+ /* We have one TxConf FQ per Tx flow */ -+ for (i = 0; i < priv->dpni_attrs.max_senders; i++) { -+ priv->fq[priv->num_fqs].netdev_priv = priv; -+ priv->fq[priv->num_fqs].type = DPAA2_TX_CONF_FQ; -+ priv->fq[priv->num_fqs].consume = dpaa2_eth_tx_conf; -+ priv->fq[priv->num_fqs++].flowid = DPNI_NEW_FLOW_ID; -+ } -+ -+ /* The number of Rx queues (Rx distribution width) may be different from -+ * the number of cores. -+ * We only support one traffic class for now. -+ */ -+ for (i = 0; i < dpaa2_queue_count(priv); i++) { -+ priv->fq[priv->num_fqs].netdev_priv = priv; -+ priv->fq[priv->num_fqs].type = DPAA2_RX_FQ; -+ priv->fq[priv->num_fqs].consume = dpaa2_eth_rx; -+ priv->fq[priv->num_fqs++].flowid = (u16)i; -+ } -+ -+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE -+ /* We have exactly one Rx error queue per DPNI */ -+ priv->fq[priv->num_fqs].netdev_priv = priv; -+ priv->fq[priv->num_fqs].type = DPAA2_RX_ERR_FQ; -+ priv->fq[priv->num_fqs++].consume = dpaa2_eth_rx_err; -+#endif -+} -+ -+static int check_obj_version(struct fsl_mc_device *ls_dev, u16 mc_version) -+{ -+ char *name = ls_dev->obj_desc.type; -+ struct device *dev = &ls_dev->dev; -+ u16 supported_version, flib_version; -+ -+ if (strcmp(name, "dpni") == 0) { -+ flib_version = DPNI_VER_MAJOR; -+ supported_version = DPAA2_SUPPORTED_DPNI_VERSION; -+ } else if (strcmp(name, "dpbp") == 0) { -+ flib_version = DPBP_VER_MAJOR; -+ supported_version = DPAA2_SUPPORTED_DPBP_VERSION; -+ } else if (strcmp(name, "dpcon") == 0) { -+ flib_version = DPCON_VER_MAJOR; -+ supported_version = DPAA2_SUPPORTED_DPCON_VERSION; -+ } else { -+ dev_err(dev, "invalid object type (%s)\n", name); -+ return -EINVAL; -+ } -+ -+ /* Check that the FLIB-defined version matches the one reported by MC */ -+ if (mc_version != flib_version) { -+ dev_err(dev, -+ "%s FLIB version mismatch: MC reports %d, we have %d\n", -+ name, mc_version, flib_version); -+ return -EINVAL; -+ } -+ -+ /* ... and that we actually support it */ -+ if (mc_version < supported_version) { -+ dev_err(dev, "Unsupported %s FLIB version (%d)\n", -+ name, mc_version); -+ return -EINVAL; -+ } -+ dev_dbg(dev, "Using %s FLIB version %d\n", name, mc_version); -+ -+ return 0; -+} -+ -+static struct fsl_mc_device *dpaa2_dpcon_setup(struct dpaa2_eth_priv *priv) -+{ -+ struct fsl_mc_device *dpcon; -+ struct device *dev = priv->net_dev->dev.parent; -+ struct dpcon_attr attrs; -+ int err; -+ -+ err = fsl_mc_object_allocate(to_fsl_mc_device(dev), -+ FSL_MC_POOL_DPCON, &dpcon); -+ if (err) { -+ dev_info(dev, "Not enough DPCONs, will go on as-is\n"); -+ return NULL; -+ } -+ -+ err = dpcon_open(priv->mc_io, 0, dpcon->obj_desc.id, &dpcon->mc_handle); -+ if (err) { -+ dev_err(dev, "dpcon_open() failed\n"); -+ goto err_open; -+ } -+ -+ err = dpcon_get_attributes(priv->mc_io, 0, dpcon->mc_handle, &attrs); -+ if (err) { -+ dev_err(dev, "dpcon_get_attributes() failed\n"); -+ goto err_get_attr; -+ } -+ -+ err = check_obj_version(dpcon, attrs.version.major); -+ if (err) -+ goto err_dpcon_ver; -+ -+ err = dpcon_enable(priv->mc_io, 0, dpcon->mc_handle); -+ if (err) { -+ dev_err(dev, "dpcon_enable() failed\n"); -+ goto err_enable; -+ } -+ -+ return dpcon; -+ -+err_enable: -+err_dpcon_ver: -+err_get_attr: -+ dpcon_close(priv->mc_io, 0, dpcon->mc_handle); -+err_open: -+ fsl_mc_object_free(dpcon); -+ -+ return NULL; -+} -+ -+static void dpaa2_dpcon_free(struct dpaa2_eth_priv *priv, -+ struct fsl_mc_device *dpcon) -+{ -+ dpcon_disable(priv->mc_io, 0, dpcon->mc_handle); -+ dpcon_close(priv->mc_io, 0, dpcon->mc_handle); -+ fsl_mc_object_free(dpcon); -+} -+ -+static struct dpaa2_eth_channel * -+dpaa2_alloc_channel(struct dpaa2_eth_priv *priv) -+{ -+ struct dpaa2_eth_channel *channel; -+ struct dpcon_attr attr; -+ struct device *dev = priv->net_dev->dev.parent; -+ int err; -+ -+ channel = kzalloc(sizeof(*channel), GFP_ATOMIC); -+ if (!channel) { -+ dev_err(dev, "Memory allocation failed\n"); -+ return NULL; -+ } -+ -+ channel->dpcon = dpaa2_dpcon_setup(priv); -+ if (!channel->dpcon) -+ goto err_setup; -+ -+ err = dpcon_get_attributes(priv->mc_io, 0, channel->dpcon->mc_handle, -+ &attr); -+ if (err) { -+ dev_err(dev, "dpcon_get_attributes() failed\n"); -+ goto err_get_attr; -+ } -+ -+ channel->dpcon_id = attr.id; -+ channel->ch_id = attr.qbman_ch_id; -+ channel->priv = priv; -+ -+ return channel; -+ -+err_get_attr: -+ dpaa2_dpcon_free(priv, channel->dpcon); -+err_setup: -+ kfree(channel); -+ return NULL; -+} -+ -+static void dpaa2_free_channel(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_channel *channel) -+{ -+ dpaa2_dpcon_free(priv, channel->dpcon); -+ kfree(channel); -+} -+ -+static int dpaa2_dpio_setup(struct dpaa2_eth_priv *priv) -+{ -+ struct dpaa2_io_notification_ctx *nctx; -+ struct dpaa2_eth_channel *channel; -+ struct dpcon_notification_cfg dpcon_notif_cfg; -+ struct device *dev = priv->net_dev->dev.parent; -+ int i, err; -+ -+ /* Don't allocate more channels than strictly necessary and assign -+ * them to cores starting from the first one available in -+ * cpu_online_mask. -+ * If the number of channels is lower than the number of cores, -+ * there will be no rx/tx conf processing on the last cores in the mask. -+ */ -+ cpumask_clear(&priv->dpio_cpumask); -+ for_each_online_cpu(i) { -+ /* Try to allocate a channel */ -+ channel = dpaa2_alloc_channel(priv); -+ if (!channel) -+ goto err_alloc_ch; -+ -+ priv->channel[priv->num_channels] = channel; -+ -+ nctx = &channel->nctx; -+ nctx->is_cdan = 1; -+ nctx->cb = dpaa2_eth_cdan_cb; -+ nctx->id = channel->ch_id; -+ nctx->desired_cpu = i; -+ -+ /* Register the new context */ -+ err = dpaa2_io_service_register(NULL, nctx); -+ if (err) { -+ dev_info(dev, "No affine DPIO for core %d\n", i); -+ /* This core doesn't have an affine DPIO, but there's -+ * a chance another one does, so keep trying -+ */ -+ dpaa2_free_channel(priv, channel); -+ continue; -+ } -+ -+ /* Register DPCON notification with MC */ -+ dpcon_notif_cfg.dpio_id = nctx->dpio_id; -+ dpcon_notif_cfg.priority = 0; -+ dpcon_notif_cfg.user_ctx = nctx->qman64; -+ err = dpcon_set_notification(priv->mc_io, 0, -+ channel->dpcon->mc_handle, -+ &dpcon_notif_cfg); -+ if (err) { -+ dev_err(dev, "dpcon_set_notification failed()\n"); -+ goto err_set_cdan; -+ } -+ -+ /* If we managed to allocate a channel and also found an affine -+ * DPIO for this core, add it to the final mask -+ */ -+ cpumask_set_cpu(i, &priv->dpio_cpumask); -+ priv->num_channels++; -+ -+ if (priv->num_channels == dpaa2_max_channels(priv)) -+ break; -+ } -+ -+ /* Tx confirmation queues can only be serviced by cpus -+ * with an affine DPIO/channel -+ */ -+ cpumask_copy(&priv->txconf_cpumask, &priv->dpio_cpumask); -+ -+ return 0; -+ -+err_set_cdan: -+ dpaa2_io_service_deregister(NULL, nctx); -+ dpaa2_free_channel(priv, channel); -+err_alloc_ch: -+ if (cpumask_empty(&priv->dpio_cpumask)) { -+ dev_err(dev, "No cpu with an affine DPIO/DPCON\n"); -+ return -ENODEV; -+ } -+ cpumask_copy(&priv->txconf_cpumask, &priv->dpio_cpumask); -+ -+ return 0; -+} -+ -+static void dpaa2_dpio_free(struct dpaa2_eth_priv *priv) -+{ -+ int i; -+ struct dpaa2_eth_channel *ch; -+ -+ /* deregister CDAN notifications and free channels */ -+ for (i = 0; i < priv->num_channels; i++) { -+ ch = priv->channel[i]; -+ dpaa2_io_service_deregister(NULL, &ch->nctx); -+ dpaa2_free_channel(priv, ch); -+ } -+} -+ -+static struct dpaa2_eth_channel * -+dpaa2_get_channel_by_cpu(struct dpaa2_eth_priv *priv, int cpu) -+{ -+ struct device *dev = priv->net_dev->dev.parent; -+ int i; -+ -+ for (i = 0; i < priv->num_channels; i++) -+ if (priv->channel[i]->nctx.desired_cpu == cpu) -+ return priv->channel[i]; -+ -+ /* We should never get here. Issue a warning and return -+ * the first channel, because it's still better than nothing -+ */ -+ dev_warn(dev, "No affine channel found for cpu %d\n", cpu); -+ -+ return priv->channel[0]; -+} -+ -+static void dpaa2_set_fq_affinity(struct dpaa2_eth_priv *priv) -+{ -+ struct device *dev = priv->net_dev->dev.parent; -+ struct dpaa2_eth_fq *fq; -+ int rx_cpu, txconf_cpu; -+ int i; -+ -+ /* For each FQ, pick one channel/CPU to deliver frames to. -+ * This may well change at runtime, either through irqbalance or -+ * through direct user intervention. -+ */ -+ rx_cpu = cpumask_first(&priv->dpio_cpumask); -+ txconf_cpu = cpumask_first(&priv->txconf_cpumask); -+ -+ for (i = 0; i < priv->num_fqs; i++) { -+ fq = &priv->fq[i]; -+ switch (fq->type) { -+ case DPAA2_RX_FQ: -+ case DPAA2_RX_ERR_FQ: -+ fq->target_cpu = rx_cpu; -+ cpumask_rr(rx_cpu, &priv->dpio_cpumask); -+ break; -+ case DPAA2_TX_CONF_FQ: -+ fq->target_cpu = txconf_cpu; -+ cpumask_rr(txconf_cpu, &priv->txconf_cpumask); -+ break; -+ default: -+ dev_err(dev, "Unknown FQ type: %d\n", fq->type); -+ } -+ fq->channel = dpaa2_get_channel_by_cpu(priv, fq->target_cpu); -+ } -+} -+ -+static int dpaa2_dpbp_setup(struct dpaa2_eth_priv *priv) -+{ -+ int err; -+ struct fsl_mc_device *dpbp_dev; -+ struct device *dev = priv->net_dev->dev.parent; -+ -+ err = fsl_mc_object_allocate(to_fsl_mc_device(dev), FSL_MC_POOL_DPBP, -+ &dpbp_dev); -+ if (err) { -+ dev_err(dev, "DPBP device allocation failed\n"); -+ return err; -+ } -+ -+ priv->dpbp_dev = dpbp_dev; -+ -+ err = dpbp_open(priv->mc_io, 0, priv->dpbp_dev->obj_desc.id, -+ &dpbp_dev->mc_handle); -+ if (err) { -+ dev_err(dev, "dpbp_open() failed\n"); -+ goto err_open; -+ } -+ -+ err = dpbp_enable(priv->mc_io, 0, dpbp_dev->mc_handle); -+ if (err) { -+ dev_err(dev, "dpbp_enable() failed\n"); -+ goto err_enable; -+ } -+ -+ err = dpbp_get_attributes(priv->mc_io, 0, dpbp_dev->mc_handle, -+ &priv->dpbp_attrs); -+ if (err) { -+ dev_err(dev, "dpbp_get_attributes() failed\n"); -+ goto err_get_attr; -+ } -+ -+ err = check_obj_version(dpbp_dev, priv->dpbp_attrs.version.major); -+ if (err) -+ goto err_dpbp_ver; -+ -+ return 0; -+ -+err_dpbp_ver: -+err_get_attr: -+ dpbp_disable(priv->mc_io, 0, dpbp_dev->mc_handle); -+err_enable: -+ dpbp_close(priv->mc_io, 0, dpbp_dev->mc_handle); -+err_open: -+ fsl_mc_object_free(dpbp_dev); -+ -+ return err; -+} -+ -+static void dpaa2_dpbp_free(struct dpaa2_eth_priv *priv) -+{ -+ __dpaa2_dpbp_free(priv); -+ dpbp_disable(priv->mc_io, 0, priv->dpbp_dev->mc_handle); -+ dpbp_close(priv->mc_io, 0, priv->dpbp_dev->mc_handle); -+ fsl_mc_object_free(priv->dpbp_dev); -+} -+ -+static int dpaa2_dpni_setup(struct fsl_mc_device *ls_dev) -+{ -+ struct device *dev = &ls_dev->dev; -+ struct dpaa2_eth_priv *priv; -+ struct net_device *net_dev; -+ void *dma_mem; -+ int err; -+ -+ net_dev = dev_get_drvdata(dev); -+ priv = netdev_priv(net_dev); -+ -+ priv->dpni_id = ls_dev->obj_desc.id; -+ -+ /* and get a handle for the DPNI this interface is associate with */ -+ err = dpni_open(priv->mc_io, 0, priv->dpni_id, &priv->mc_token); -+ if (err) { -+ dev_err(dev, "dpni_open() failed\n"); -+ goto err_open; -+ } -+ -+ ls_dev->mc_io = priv->mc_io; -+ ls_dev->mc_handle = priv->mc_token; -+ -+ dma_mem = kzalloc(DPAA2_EXT_CFG_SIZE, GFP_DMA | GFP_KERNEL); -+ if (!dma_mem) -+ goto err_alloc; -+ -+ priv->dpni_attrs.ext_cfg_iova = dma_map_single(dev, dma_mem, -+ DPAA2_EXT_CFG_SIZE, -+ DMA_FROM_DEVICE); -+ if (dma_mapping_error(dev, priv->dpni_attrs.ext_cfg_iova)) { -+ dev_err(dev, "dma mapping for dpni_ext_cfg failed\n"); -+ goto err_dma_map; -+ } -+ -+ err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token, -+ &priv->dpni_attrs); -+ if (err) { -+ dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err); -+ dma_unmap_single(dev, priv->dpni_attrs.ext_cfg_iova, -+ DPAA2_EXT_CFG_SIZE, DMA_FROM_DEVICE); -+ goto err_get_attr; -+ } -+ -+ err = check_obj_version(ls_dev, priv->dpni_attrs.version.major); -+ if (err) -+ goto err_dpni_ver; -+ -+ dma_unmap_single(dev, priv->dpni_attrs.ext_cfg_iova, -+ DPAA2_EXT_CFG_SIZE, DMA_FROM_DEVICE); -+ -+ memset(&priv->dpni_ext_cfg, 0, sizeof(priv->dpni_ext_cfg)); -+ err = dpni_extract_extended_cfg(&priv->dpni_ext_cfg, dma_mem); -+ if (err) { -+ dev_err(dev, "dpni_extract_extended_cfg() failed\n"); -+ goto err_extract; -+ } -+ -+ /* Configure our buffers' layout */ -+ priv->buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT | -+ DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | -+ DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE | -+ DPNI_BUF_LAYOUT_OPT_DATA_ALIGN; -+ priv->buf_layout.pass_parser_result = true; -+ priv->buf_layout.pass_frame_status = true; -+ priv->buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE; -+ /* HW erratum mandates data alignment in multiples of 256 */ -+ priv->buf_layout.data_align = DPAA2_ETH_RX_BUF_ALIGN; -+ /* ...rx, ... */ -+ err = dpni_set_rx_buffer_layout(priv->mc_io, 0, priv->mc_token, -+ &priv->buf_layout); -+ if (err) { -+ dev_err(dev, "dpni_set_rx_buffer_layout() failed"); -+ goto err_buf_layout; -+ } -+ /* ... tx, ... */ -+ /* remove Rx-only options */ -+ priv->buf_layout.options &= ~(DPNI_BUF_LAYOUT_OPT_DATA_ALIGN | -+ DPNI_BUF_LAYOUT_OPT_PARSER_RESULT); -+ err = dpni_set_tx_buffer_layout(priv->mc_io, 0, priv->mc_token, -+ &priv->buf_layout); -+ if (err) { -+ dev_err(dev, "dpni_set_tx_buffer_layout() failed"); -+ goto err_buf_layout; -+ } -+ /* ... tx-confirm. */ -+ priv->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE; -+ priv->buf_layout.options |= DPNI_BUF_LAYOUT_OPT_TIMESTAMP; -+ priv->buf_layout.pass_timestamp = 1; -+ err = dpni_set_tx_conf_buffer_layout(priv->mc_io, 0, priv->mc_token, -+ &priv->buf_layout); -+ if (err) { -+ dev_err(dev, "dpni_set_tx_conf_buffer_layout() failed"); -+ goto err_buf_layout; -+ } -+ /* Now that we've set our tx buffer layout, retrieve the minimum -+ * required tx data offset. -+ */ -+ err = dpni_get_tx_data_offset(priv->mc_io, 0, priv->mc_token, -+ &priv->tx_data_offset); -+ if (err) { -+ dev_err(dev, "dpni_get_tx_data_offset() failed\n"); -+ goto err_data_offset; -+ } -+ -+ /* Warn in case TX data offset is not multiple of 64 bytes. */ -+ WARN_ON(priv->tx_data_offset % 64); -+ -+ /* Accommodate SWA space. */ -+ priv->tx_data_offset += DPAA2_ETH_SWA_SIZE; -+ -+ /* allocate classification rule space */ -+ priv->cls_rule = kzalloc(sizeof(*priv->cls_rule) * -+ DPAA2_CLASSIFIER_ENTRY_COUNT, GFP_KERNEL); -+ if (!priv->cls_rule) -+ goto err_cls_rule; -+ -+ kfree(dma_mem); -+ -+ return 0; -+ -+err_cls_rule: -+err_data_offset: -+err_buf_layout: -+err_extract: -+err_dpni_ver: -+err_get_attr: -+err_dma_map: -+ kfree(dma_mem); -+err_alloc: -+ dpni_close(priv->mc_io, 0, priv->mc_token); -+err_open: -+ return err; -+} -+ -+static void dpaa2_dpni_free(struct dpaa2_eth_priv *priv) -+{ -+ int err; -+ -+ err = dpni_reset(priv->mc_io, 0, priv->mc_token); -+ if (err) -+ netdev_warn(priv->net_dev, "dpni_reset() failed (err %d)\n", -+ err); -+ -+ dpni_close(priv->mc_io, 0, priv->mc_token); -+} -+ -+static int dpaa2_rx_flow_setup(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_fq *fq) -+{ -+ struct device *dev = priv->net_dev->dev.parent; -+ struct dpni_queue_attr rx_queue_attr; -+ struct dpni_queue_cfg queue_cfg; -+ int err; -+ -+ memset(&queue_cfg, 0, sizeof(queue_cfg)); -+ queue_cfg.options = DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST | -+ DPNI_QUEUE_OPT_TAILDROP_THRESHOLD; -+ queue_cfg.dest_cfg.dest_type = DPNI_DEST_DPCON; -+ queue_cfg.dest_cfg.priority = 1; -+ queue_cfg.user_ctx = (u64)fq; -+ queue_cfg.dest_cfg.dest_id = fq->channel->dpcon_id; -+ queue_cfg.tail_drop_threshold = DPAA2_ETH_TAILDROP_THRESH; -+ err = dpni_set_rx_flow(priv->mc_io, 0, priv->mc_token, 0, fq->flowid, -+ &queue_cfg); -+ if (err) { -+ dev_err(dev, "dpni_set_rx_flow() failed\n"); -+ return err; -+ } -+ -+ /* Get the actual FQID that was assigned by MC */ -+ err = dpni_get_rx_flow(priv->mc_io, 0, priv->mc_token, 0, fq->flowid, -+ &rx_queue_attr); -+ if (err) { -+ dev_err(dev, "dpni_get_rx_flow() failed\n"); -+ return err; -+ } -+ fq->fqid = rx_queue_attr.fqid; -+ -+ return 0; -+} -+ -+static int dpaa2_tx_flow_setup(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_fq *fq) -+{ -+ struct device *dev = priv->net_dev->dev.parent; -+ struct dpni_tx_flow_cfg tx_flow_cfg; -+ struct dpni_tx_conf_cfg tx_conf_cfg; -+ struct dpni_tx_conf_attr tx_conf_attr; -+ int err; -+ -+ memset(&tx_flow_cfg, 0, sizeof(tx_flow_cfg)); -+ tx_flow_cfg.options = DPNI_TX_FLOW_OPT_TX_CONF_ERROR; -+ tx_flow_cfg.use_common_tx_conf_queue = 0; -+ err = dpni_set_tx_flow(priv->mc_io, 0, priv->mc_token, -+ &fq->flowid, &tx_flow_cfg); -+ if (err) { -+ dev_err(dev, "dpni_set_tx_flow() failed\n"); -+ return err; -+ } -+ -+ tx_conf_cfg.errors_only = 0; -+ tx_conf_cfg.queue_cfg.options = DPNI_QUEUE_OPT_USER_CTX | -+ DPNI_QUEUE_OPT_DEST; -+ tx_conf_cfg.queue_cfg.user_ctx = (u64)fq; -+ tx_conf_cfg.queue_cfg.dest_cfg.dest_type = DPNI_DEST_DPCON; -+ tx_conf_cfg.queue_cfg.dest_cfg.dest_id = fq->channel->dpcon_id; -+ tx_conf_cfg.queue_cfg.dest_cfg.priority = 0; -+ -+ err = dpni_set_tx_conf(priv->mc_io, 0, priv->mc_token, fq->flowid, -+ &tx_conf_cfg); -+ if (err) { -+ dev_err(dev, "dpni_set_tx_conf() failed\n"); -+ return err; -+ } -+ -+ err = dpni_get_tx_conf(priv->mc_io, 0, priv->mc_token, fq->flowid, -+ &tx_conf_attr); -+ if (err) { -+ dev_err(dev, "dpni_get_tx_conf() failed\n"); -+ return err; -+ } -+ -+ fq->fqid = tx_conf_attr.queue_attr.fqid; -+ -+ return 0; -+} -+ -+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE -+static int dpaa2_rx_err_setup(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_fq *fq) -+{ -+ struct dpni_queue_attr queue_attr; -+ struct dpni_queue_cfg queue_cfg; -+ int err; -+ -+ /* Configure the Rx error queue to generate CDANs, -+ * just like the Rx queues */ -+ queue_cfg.options = DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST; -+ queue_cfg.dest_cfg.dest_type = DPNI_DEST_DPCON; -+ queue_cfg.dest_cfg.priority = 1; -+ queue_cfg.user_ctx = (u64)fq; -+ queue_cfg.dest_cfg.dest_id = fq->channel->dpcon_id; -+ err = dpni_set_rx_err_queue(priv->mc_io, 0, priv->mc_token, &queue_cfg); -+ if (err) { -+ netdev_err(priv->net_dev, "dpni_set_rx_err_queue() failed\n"); -+ return err; -+ } -+ -+ /* Get the FQID */ -+ err = dpni_get_rx_err_queue(priv->mc_io, 0, priv->mc_token, &queue_attr); -+ if (err) { -+ netdev_err(priv->net_dev, "dpni_get_rx_err_queue() failed\n"); -+ return err; -+ } -+ fq->fqid = queue_attr.fqid; -+ -+ return 0; -+} -+#endif -+ -+static int dpaa2_dpni_bind(struct dpaa2_eth_priv *priv) -+{ -+ struct net_device *net_dev = priv->net_dev; -+ struct device *dev = net_dev->dev.parent; -+ struct dpni_pools_cfg pools_params; -+ struct dpni_error_cfg err_cfg; -+ int err = 0; -+ int i; -+ -+ pools_params.num_dpbp = 1; -+ pools_params.pools[0].dpbp_id = priv->dpbp_dev->obj_desc.id; -+ pools_params.pools[0].backup_pool = 0; -+ pools_params.pools[0].buffer_size = DPAA2_ETH_RX_BUFFER_SIZE; -+ err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params); -+ if (err) { -+ dev_err(dev, "dpni_set_pools() failed\n"); -+ return err; -+ } -+ -+ dpaa2_cls_check(net_dev); -+ -+ /* have the interface implicitly distribute traffic based on supported -+ * header fields -+ */ -+ if (dpaa2_eth_hash_enabled(priv)) { -+ err = dpaa2_set_hash(net_dev, DPAA2_RXH_SUPPORTED); -+ if (err) -+ return err; -+ } -+ -+ /* Configure handling of error frames */ -+ err_cfg.errors = DPAA2_ETH_RX_ERR_MASK; -+ err_cfg.set_frame_annotation = 1; -+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE -+ err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE; -+#else -+ err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD; -+#endif -+ err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token, -+ &err_cfg); -+ if (err) { -+ dev_err(dev, "dpni_set_errors_behavior failed\n"); -+ return err; -+ } -+ -+ /* Configure Rx and Tx conf queues to generate CDANs */ -+ for (i = 0; i < priv->num_fqs; i++) { -+ switch (priv->fq[i].type) { -+ case DPAA2_RX_FQ: -+ err = dpaa2_rx_flow_setup(priv, &priv->fq[i]); -+ break; -+ case DPAA2_TX_CONF_FQ: -+ err = dpaa2_tx_flow_setup(priv, &priv->fq[i]); -+ break; -+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE -+ case DPAA2_RX_ERR_FQ: -+ err = dpaa2_rx_err_setup(priv, &priv->fq[i]); -+ break; -+#endif -+ default: -+ dev_err(dev, "Invalid FQ type %d\n", priv->fq[i].type); -+ return -EINVAL; -+ } -+ if (err) -+ return err; -+ } -+ -+ err = dpni_get_qdid(priv->mc_io, 0, priv->mc_token, &priv->tx_qdid); -+ if (err) { -+ dev_err(dev, "dpni_get_qdid() failed\n"); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int dpaa2_eth_alloc_rings(struct dpaa2_eth_priv *priv) -+{ -+ struct net_device *net_dev = priv->net_dev; -+ struct device *dev = net_dev->dev.parent; -+ int i; -+ -+ for (i = 0; i < priv->num_channels; i++) { -+ priv->channel[i]->store = -+ dpaa2_io_store_create(DPAA2_ETH_STORE_SIZE, dev); -+ if (!priv->channel[i]->store) { -+ netdev_err(net_dev, "dpaa2_io_store_create() failed\n"); -+ goto err_ring; -+ } -+ } -+ -+ return 0; -+ -+err_ring: -+ for (i = 0; i < priv->num_channels; i++) { -+ if (!priv->channel[i]->store) -+ break; -+ dpaa2_io_store_destroy(priv->channel[i]->store); -+ } -+ -+ return -ENOMEM; -+} -+ -+static void dpaa2_eth_free_rings(struct dpaa2_eth_priv *priv) -+{ -+ int i; -+ -+ for (i = 0; i < priv->num_channels; i++) -+ dpaa2_io_store_destroy(priv->channel[i]->store); -+} -+ -+static int dpaa2_eth_netdev_init(struct net_device *net_dev) -+{ -+ int err; -+ struct device *dev = net_dev->dev.parent; -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ u8 mac_addr[ETH_ALEN]; -+ u8 bcast_addr[ETH_ALEN]; -+ -+ net_dev->netdev_ops = &dpaa2_eth_ops; -+ -+ /* If the DPL contains all-0 mac_addr, set a random hardware address */ -+ err = dpni_get_primary_mac_addr(priv->mc_io, 0, priv->mc_token, -+ mac_addr); -+ if (err) { -+ dev_err(dev, "dpni_get_primary_mac_addr() failed (%d)", err); -+ return err; -+ } -+ if (is_zero_ether_addr(mac_addr)) { -+ /* Fills in net_dev->dev_addr, as required by -+ * register_netdevice() -+ */ -+ eth_hw_addr_random(net_dev); -+ /* Make the user aware, without cluttering the boot log */ -+ pr_info_once(KBUILD_MODNAME " device(s) have all-zero hwaddr, replaced with random"); -+ err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token, -+ net_dev->dev_addr); -+ if (err) { -+ dev_err(dev, "dpni_set_primary_mac_addr(): %d\n", err); -+ return err; -+ } -+ /* Override NET_ADDR_RANDOM set by eth_hw_addr_random(); for all -+ * practical purposes, this will be our "permanent" mac address, -+ * at least until the next reboot. This move will also permit -+ * register_netdevice() to properly fill up net_dev->perm_addr. -+ */ -+ net_dev->addr_assign_type = NET_ADDR_PERM; -+ } else { -+ /* NET_ADDR_PERM is default, all we have to do is -+ * fill in the device addr. -+ */ -+ memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len); -+ } -+ -+ /* Explicitly add the broadcast address to the MAC filtering table; -+ * the MC won't do that for us. -+ */ -+ eth_broadcast_addr(bcast_addr); -+ err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, bcast_addr); -+ if (err) { -+ dev_warn(dev, "dpni_add_mac_addr() failed (%d)\n", err); -+ /* Won't return an error; at least, we'd have egress traffic */ -+ } -+ -+ /* Reserve enough space to align buffer as per hardware requirement; -+ * NOTE: priv->tx_data_offset MUST be initialized at this point. -+ */ -+ net_dev->needed_headroom = DPAA2_ETH_NEEDED_HEADROOM(priv); -+ -+ /* Our .ndo_init will be called herein */ -+ err = register_netdev(net_dev); -+ if (err < 0) { -+ dev_err(dev, "register_netdev() = %d\n", err); -+ return err; -+ } -+ -+ return 0; -+} -+ -+#ifdef CONFIG_FSL_DPAA2_ETH_LINK_POLL -+static int dpaa2_poll_link_state(void *arg) -+{ -+ struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)arg; -+ int err; -+ -+ while (!kthread_should_stop()) { -+ err = dpaa2_link_state_update(priv); -+ if (unlikely(err)) -+ return err; -+ -+ msleep(DPAA2_ETH_LINK_STATE_REFRESH); -+ } -+ -+ return 0; -+} -+#else -+static irqreturn_t dpni_irq0_handler(int irq_num, void *arg) -+{ -+ return IRQ_WAKE_THREAD; -+} -+ -+static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg) -+{ -+ u8 irq_index = DPNI_IRQ_INDEX; -+ u32 status, clear = 0; -+ struct device *dev = (struct device *)arg; -+ struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev); -+ struct net_device *net_dev = dev_get_drvdata(dev); -+ int err; -+ -+ netdev_dbg(net_dev, "IRQ %d received\n", irq_num); -+ err = dpni_get_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle, -+ irq_index, &status); -+ if (unlikely(err)) { -+ netdev_err(net_dev, "Can't get irq status (err %d)", err); -+ clear = 0xffffffff; -+ goto out; -+ } -+ -+ if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { -+ clear |= DPNI_IRQ_EVENT_LINK_CHANGED; -+ dpaa2_link_state_update(netdev_priv(net_dev)); -+ } -+ -+out: -+ dpni_clear_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle, -+ irq_index, clear); -+ return IRQ_HANDLED; -+} -+ -+static int dpaa2_eth_setup_irqs(struct fsl_mc_device *ls_dev) -+{ -+ int err = 0; -+ struct fsl_mc_device_irq *irq; -+ int irq_count = ls_dev->obj_desc.irq_count; -+ u8 irq_index = DPNI_IRQ_INDEX; -+ u32 mask = DPNI_IRQ_EVENT_LINK_CHANGED; -+ -+ /* The only interrupt supported now is the link state notification. */ -+ if (WARN_ON(irq_count != 1)) -+ return -EINVAL; -+ -+ irq = ls_dev->irqs[0]; -+ err = devm_request_threaded_irq(&ls_dev->dev, irq->msi_desc->irq, -+ dpni_irq0_handler, -+ dpni_irq0_handler_thread, -+ IRQF_NO_SUSPEND | IRQF_ONESHOT, -+ dev_name(&ls_dev->dev), &ls_dev->dev); -+ if (err < 0) { -+ dev_err(&ls_dev->dev, "devm_request_threaded_irq(): %d", err); -+ return err; -+ } -+ -+ err = dpni_set_irq_mask(ls_dev->mc_io, 0, ls_dev->mc_handle, -+ irq_index, mask); -+ if (err < 0) { -+ dev_err(&ls_dev->dev, "dpni_set_irq_mask(): %d", err); -+ return err; -+ } -+ -+ err = dpni_set_irq_enable(ls_dev->mc_io, 0, ls_dev->mc_handle, -+ irq_index, 1); -+ if (err < 0) { -+ dev_err(&ls_dev->dev, "dpni_set_irq_enable(): %d", err); -+ return err; -+ } -+ -+ return 0; -+} -+#endif -+ -+static void dpaa2_eth_napi_add(struct dpaa2_eth_priv *priv) -+{ -+ int i; -+ struct dpaa2_eth_channel *ch; -+ -+ for (i = 0; i < priv->num_channels; i++) { -+ ch = priv->channel[i]; -+ /* NAPI weight *MUST* be a multiple of DPAA2_ETH_STORE_SIZE */ -+ netif_napi_add(priv->net_dev, &ch->napi, dpaa2_eth_poll, -+ NAPI_POLL_WEIGHT); -+ } -+} -+ -+static void dpaa2_eth_napi_del(struct dpaa2_eth_priv *priv) -+{ -+ int i; -+ struct dpaa2_eth_channel *ch; -+ -+ for (i = 0; i < priv->num_channels; i++) { -+ ch = priv->channel[i]; -+ netif_napi_del(&ch->napi); -+ } -+} -+ -+/* SysFS support */ -+ -+static ssize_t dpaa2_eth_show_tx_shaping(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(to_net_dev(dev)); -+ /* No MC API for getting the shaping config. We're stateful. */ -+ struct dpni_tx_shaping_cfg *scfg = &priv->shaping_cfg; -+ -+ return sprintf(buf, "%u %hu\n", scfg->rate_limit, scfg->max_burst_size); -+} -+ -+static ssize_t dpaa2_eth_write_tx_shaping(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, -+ size_t count) -+{ -+ int err, items; -+ struct dpaa2_eth_priv *priv = netdev_priv(to_net_dev(dev)); -+ struct dpni_tx_shaping_cfg scfg; -+ -+ items = sscanf(buf, "%u %hu", &scfg.rate_limit, &scfg.max_burst_size); -+ if (items != 2) { -+ pr_err("Expected format: \"rate_limit(Mbps) max_burst_size(bytes)\"\n"); -+ return -EINVAL; -+ } -+ /* Size restriction as per MC API documentation */ -+ if (scfg.max_burst_size > 64000) { -+ pr_err("max_burst_size must be <= 64000, thanks.\n"); -+ return -EINVAL; -+ } -+ -+ err = dpni_set_tx_shaping(priv->mc_io, 0, priv->mc_token, &scfg); -+ if (err) { -+ dev_err(dev, "dpni_set_tx_shaping() failed\n"); -+ return -EPERM; -+ } -+ /* If successful, save the current configuration for future inquiries */ -+ priv->shaping_cfg = scfg; -+ -+ return count; -+} -+ -+static ssize_t dpaa2_eth_show_txconf_cpumask(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(to_net_dev(dev)); -+ -+ return cpumap_print_to_pagebuf(1, buf, &priv->txconf_cpumask); -+} -+ -+static ssize_t dpaa2_eth_write_txconf_cpumask(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, -+ size_t count) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(to_net_dev(dev)); -+ struct dpaa2_eth_fq *fq; -+ bool running = netif_running(priv->net_dev); -+ int i, err; -+ -+ err = cpulist_parse(buf, &priv->txconf_cpumask); -+ if (err) -+ return err; -+ -+ /* Only accept CPUs that have an affine DPIO */ -+ if (!cpumask_subset(&priv->txconf_cpumask, &priv->dpio_cpumask)) { -+ netdev_info(priv->net_dev, -+ "cpumask must be a subset of 0x%lx\n", -+ *cpumask_bits(&priv->dpio_cpumask)); -+ cpumask_and(&priv->txconf_cpumask, &priv->dpio_cpumask, -+ &priv->txconf_cpumask); -+ } -+ -+ /* Rewiring the TxConf FQs requires interface shutdown. -+ */ -+ if (running) { -+ err = dpaa2_eth_stop(priv->net_dev); -+ if (err) -+ return -ENODEV; -+ } -+ -+ /* Set the new TxConf FQ affinities */ -+ dpaa2_set_fq_affinity(priv); -+ -+#ifdef CONFIG_FSL_DPAA2_ETH_LINK_POLL -+ /* dpaa2_eth_open() below will *stop* the Tx queues until an explicit -+ * link up notification is received. Give the polling thread enough time -+ * to detect the link state change, or else we'll end up with the -+ * transmission side forever shut down. -+ */ -+ msleep(2 * DPAA2_ETH_LINK_STATE_REFRESH); -+#endif -+ -+ for (i = 0; i < priv->num_fqs; i++) { -+ fq = &priv->fq[i]; -+ if (fq->type != DPAA2_TX_CONF_FQ) -+ continue; -+ dpaa2_tx_flow_setup(priv, fq); -+ } -+ -+ if (running) { -+ err = dpaa2_eth_open(priv->net_dev); -+ if (err) -+ return -ENODEV; -+ } -+ -+ return count; -+} -+ -+static struct device_attribute dpaa2_eth_attrs[] = { -+ __ATTR(txconf_cpumask, -+ S_IRUSR | S_IWUSR, -+ dpaa2_eth_show_txconf_cpumask, -+ dpaa2_eth_write_txconf_cpumask), -+ -+ __ATTR(tx_shaping, -+ S_IRUSR | S_IWUSR, -+ dpaa2_eth_show_tx_shaping, -+ dpaa2_eth_write_tx_shaping), -+}; -+ -+void dpaa2_eth_sysfs_init(struct device *dev) -+{ -+ int i, err; -+ -+ for (i = 0; i < ARRAY_SIZE(dpaa2_eth_attrs); i++) { -+ err = device_create_file(dev, &dpaa2_eth_attrs[i]); -+ if (err) { -+ dev_err(dev, "ERROR creating sysfs file\n"); -+ goto undo; -+ } -+ } -+ return; -+ -+undo: -+ while (i > 0) -+ device_remove_file(dev, &dpaa2_eth_attrs[--i]); -+} -+ -+void dpaa2_eth_sysfs_remove(struct device *dev) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(dpaa2_eth_attrs); i++) -+ device_remove_file(dev, &dpaa2_eth_attrs[i]); -+} -+ -+static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev) -+{ -+ struct device *dev; -+ struct net_device *net_dev = NULL; -+ struct dpaa2_eth_priv *priv = NULL; -+ int err = 0; -+ -+ dev = &dpni_dev->dev; -+ -+ /* Net device */ -+ net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA2_ETH_MAX_TX_QUEUES); -+ if (!net_dev) { -+ dev_err(dev, "alloc_etherdev_mq() failed\n"); -+ return -ENOMEM; -+ } -+ -+ SET_NETDEV_DEV(net_dev, dev); -+ dev_set_drvdata(dev, net_dev); -+ -+ priv = netdev_priv(net_dev); -+ priv->net_dev = net_dev; -+ priv->msg_enable = netif_msg_init(debug, -1); -+ -+ /* Obtain a MC portal */ -+ err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL, -+ &priv->mc_io); -+ if (err) { -+ dev_err(dev, "MC portal allocation failed\n"); -+ goto err_portal_alloc; -+ } -+ -+#ifndef CONFIG_FSL_DPAA2_ETH_LINK_POLL -+ err = fsl_mc_allocate_irqs(dpni_dev); -+ if (err) { -+ dev_err(dev, "MC irqs allocation failed\n"); -+ goto err_irqs_alloc; -+ } -+#endif -+ -+ /* DPNI initialization */ -+ err = dpaa2_dpni_setup(dpni_dev); -+ if (err < 0) -+ goto err_dpni_setup; -+ -+ /* DPIO */ -+ err = dpaa2_dpio_setup(priv); -+ if (err) -+ goto err_dpio_setup; -+ -+ /* FQs */ -+ dpaa2_eth_setup_fqs(priv); -+ dpaa2_set_fq_affinity(priv); -+ -+ /* DPBP */ -+ err = dpaa2_dpbp_setup(priv); -+ if (err) -+ goto err_dpbp_setup; -+ -+ /* DPNI binding to DPIO and DPBPs */ -+ err = dpaa2_dpni_bind(priv); -+ if (err) -+ goto err_bind; -+ -+ dpaa2_eth_napi_add(priv); -+ -+ /* Percpu statistics */ -+ priv->percpu_stats = alloc_percpu(*priv->percpu_stats); -+ if (!priv->percpu_stats) { -+ dev_err(dev, "alloc_percpu(percpu_stats) failed\n"); -+ err = -ENOMEM; -+ goto err_alloc_percpu_stats; -+ } -+ priv->percpu_extras = alloc_percpu(*priv->percpu_extras); -+ if (!priv->percpu_extras) { -+ dev_err(dev, "alloc_percpu(percpu_extras) failed\n"); -+ err = -ENOMEM; -+ goto err_alloc_percpu_extras; -+ } -+ -+ snprintf(net_dev->name, IFNAMSIZ, "ni%d", dpni_dev->obj_desc.id); -+ if (!dev_valid_name(net_dev->name)) { -+ dev_warn(&net_dev->dev, -+ "netdevice name \"%s\" cannot be used, reverting to default..\n", -+ net_dev->name); -+ dev_alloc_name(net_dev, "eth%d"); -+ dev_warn(&net_dev->dev, "using name \"%s\"\n", net_dev->name); -+ } -+ -+ err = dpaa2_eth_netdev_init(net_dev); -+ if (err) -+ goto err_netdev_init; -+ -+ /* Configure checksum offload based on current interface flags */ -+ err = dpaa2_eth_set_rx_csum(priv, -+ !!(net_dev->features & NETIF_F_RXCSUM)); -+ if (err) -+ goto err_csum; -+ -+ err = dpaa2_eth_set_tx_csum(priv, -+ !!(net_dev->features & -+ (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))); -+ if (err) -+ goto err_csum; -+ -+ err = dpaa2_eth_alloc_rings(priv); -+ if (err) -+ goto err_alloc_rings; -+ -+ net_dev->ethtool_ops = &dpaa2_ethtool_ops; -+ -+#ifdef CONFIG_FSL_DPAA2_ETH_LINK_POLL -+ priv->poll_thread = kthread_run(dpaa2_poll_link_state, priv, -+ "%s_poll_link", net_dev->name); -+#else -+ err = dpaa2_eth_setup_irqs(dpni_dev); -+ if (err) { -+ netdev_err(net_dev, "ERROR %d setting up interrupts", err); -+ goto err_setup_irqs; -+ } -+#endif -+ -+ dpaa2_eth_sysfs_init(&net_dev->dev); -+ dpaa2_dbg_add(priv); -+ -+ dev_info(dev, "Probed interface %s\n", net_dev->name); -+ return 0; -+ -+#ifndef CONFIG_FSL_DPAA2_ETH_LINK_POLL -+err_setup_irqs: -+#endif -+ dpaa2_eth_free_rings(priv); -+err_alloc_rings: -+err_csum: -+ unregister_netdev(net_dev); -+err_netdev_init: -+ free_percpu(priv->percpu_extras); -+err_alloc_percpu_extras: -+ free_percpu(priv->percpu_stats); -+err_alloc_percpu_stats: -+ dpaa2_eth_napi_del(priv); -+err_bind: -+ dpaa2_dpbp_free(priv); -+err_dpbp_setup: -+ dpaa2_dpio_free(priv); -+err_dpio_setup: -+ kfree(priv->cls_rule); -+ dpni_close(priv->mc_io, 0, priv->mc_token); -+err_dpni_setup: -+#ifndef CONFIG_FSL_DPAA2_ETH_LINK_POLL -+ fsl_mc_free_irqs(dpni_dev); -+err_irqs_alloc: -+#endif -+ fsl_mc_portal_free(priv->mc_io); -+err_portal_alloc: -+ dev_set_drvdata(dev, NULL); -+ free_netdev(net_dev); -+ -+ return err; -+} -+ -+static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev) -+{ -+ struct device *dev; -+ struct net_device *net_dev; -+ struct dpaa2_eth_priv *priv; -+ -+ dev = &ls_dev->dev; -+ net_dev = dev_get_drvdata(dev); -+ priv = netdev_priv(net_dev); -+ -+ dpaa2_dbg_remove(priv); -+ dpaa2_eth_sysfs_remove(&net_dev->dev); -+ -+ unregister_netdev(net_dev); -+ dev_info(net_dev->dev.parent, "Removed interface %s\n", net_dev->name); -+ -+ dpaa2_dpio_free(priv); -+ dpaa2_eth_free_rings(priv); -+ dpaa2_eth_napi_del(priv); -+ dpaa2_dpbp_free(priv); -+ dpaa2_dpni_free(priv); -+ -+ fsl_mc_portal_free(priv->mc_io); -+ -+ free_percpu(priv->percpu_stats); -+ free_percpu(priv->percpu_extras); -+ -+#ifdef CONFIG_FSL_DPAA2_ETH_LINK_POLL -+ kthread_stop(priv->poll_thread); -+#else -+ fsl_mc_free_irqs(ls_dev); -+#endif -+ -+ kfree(priv->cls_rule); -+ -+ dev_set_drvdata(dev, NULL); -+ free_netdev(net_dev); -+ -+ return 0; -+} -+ -+static const struct fsl_mc_device_match_id dpaa2_eth_match_id_table[] = { -+ { -+ .vendor = FSL_MC_VENDOR_FREESCALE, -+ .obj_type = "dpni", -+ .ver_major = DPNI_VER_MAJOR, -+ .ver_minor = DPNI_VER_MINOR -+ }, -+ { .vendor = 0x0 } -+}; -+ -+static struct fsl_mc_driver dpaa2_eth_driver = { -+ .driver = { -+ .name = KBUILD_MODNAME, -+ .owner = THIS_MODULE, -+ }, -+ .probe = dpaa2_eth_probe, -+ .remove = dpaa2_eth_remove, -+ .match_id_table = dpaa2_eth_match_id_table -+}; -+ -+static int __init dpaa2_eth_driver_init(void) -+{ -+ int err; -+ -+ dpaa2_eth_dbg_init(); -+ -+ err = fsl_mc_driver_register(&dpaa2_eth_driver); -+ if (err) { -+ dpaa2_eth_dbg_exit(); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static void __exit dpaa2_eth_driver_exit(void) -+{ -+ fsl_mc_driver_unregister(&dpaa2_eth_driver); -+ dpaa2_eth_dbg_exit(); -+} -+ -+module_init(dpaa2_eth_driver_init); -+module_exit(dpaa2_eth_driver_exit); ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h -@@ -0,0 +1,366 @@ -+/* Copyright 2014-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef __DPAA2_ETH_H -+#define __DPAA2_ETH_H -+ -+#include -+#include -+#include "../../fsl-mc/include/fsl_dpaa2_io.h" -+#include "../../fsl-mc/include/fsl_dpaa2_fd.h" -+#include "../../fsl-mc/include/dpbp.h" -+#include "../../fsl-mc/include/dpbp-cmd.h" -+#include "../../fsl-mc/include/dpcon.h" -+#include "../../fsl-mc/include/dpcon-cmd.h" -+#include "../../fsl-mc/include/dpmng.h" -+#include "dpni.h" -+#include "dpni-cmd.h" -+ -+#include "dpaa2-eth-trace.h" -+#include "dpaa2-eth-debugfs.h" -+ -+#define DPAA2_ETH_STORE_SIZE 16 -+ -+/* Maximum receive frame size is 64K */ -+#define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUFFER_SIZE) -+ -+/* Maximum acceptable MTU value. It is in direct relation with the MC-enforced -+ * Max Frame Length (currently 10k). -+ */ -+#define DPAA2_ETH_MFL (10 * 1024) -+#define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN) -+/* Convert L3 MTU to L2 MFL */ -+#define DPAA2_ETH_L2_MAX_FRM(mtu) (mtu + VLAN_ETH_HLEN) -+ -+/* Set the taildrop threshold (in bytes) to allow the enqueue of several jumbo -+ * frames in the Rx queues (length of the current frame is not -+ * taken into account when making the taildrop decision) -+ */ -+#define DPAA2_ETH_TAILDROP_THRESH (64 * 1024) -+ -+/* Buffer quota per queue. Must be large enough such that for minimum sized -+ * frames taildrop kicks in before the bpool gets depleted, so we compute -+ * how many 64B frames fit inside the taildrop threshold and add a margin -+ * to accommodate the buffer refill delay. -+ */ -+#define DPAA2_ETH_MAX_FRAMES_PER_QUEUE (DPAA2_ETH_TAILDROP_THRESH / 64) -+#define DPAA2_ETH_NUM_BUFS (DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256) -+#define DPAA2_ETH_REFILL_THRESH DPAA2_ETH_MAX_FRAMES_PER_QUEUE -+ -+/* Hardware requires alignment for ingress/egress buffer addresses -+ * and ingress buffer lengths. -+ */ -+#define DPAA2_ETH_RX_BUFFER_SIZE 2048 -+#define DPAA2_ETH_TX_BUF_ALIGN 64 -+#define DPAA2_ETH_RX_BUF_ALIGN 256 -+#define DPAA2_ETH_NEEDED_HEADROOM(p_priv) \ -+ ((p_priv)->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN) -+ -+#define DPAA2_ETH_BUF_RAW_SIZE \ -+ (DPAA2_ETH_RX_BUFFER_SIZE + \ -+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + \ -+ DPAA2_ETH_RX_BUF_ALIGN) -+ -+/* PTP nominal frequency 1MHz */ -+#define DPAA2_PTP_NOMINAL_FREQ_PERIOD_NS 1000 -+ -+/* We are accommodating a skb backpointer and some S/G info -+ * in the frame's software annotation. The hardware -+ * options are either 0 or 64, so we choose the latter. -+ */ -+#define DPAA2_ETH_SWA_SIZE 64 -+ -+/* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */ -+struct dpaa2_eth_swa { -+ struct sk_buff *skb; -+ struct scatterlist *scl; -+ int num_sg; -+ int num_dma_bufs; -+}; -+ -+/* Annotation valid bits in FD FRC */ -+#define DPAA2_FD_FRC_FASV 0x8000 -+#define DPAA2_FD_FRC_FAEADV 0x4000 -+#define DPAA2_FD_FRC_FAPRV 0x2000 -+#define DPAA2_FD_FRC_FAIADV 0x1000 -+#define DPAA2_FD_FRC_FASWOV 0x0800 -+#define DPAA2_FD_FRC_FAICFDV 0x0400 -+ -+/* Annotation bits in FD CTRL */ -+#define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128 */ -+#define DPAA2_FD_CTRL_PTA 0x00800000 -+#define DPAA2_FD_CTRL_PTV1 0x00400000 -+ -+/* Frame annotation status */ -+struct dpaa2_fas { -+ u8 reserved; -+ u8 ppid; -+ __le16 ifpid; -+ __le32 status; -+} __packed; -+ -+/* Debug frame, otherwise supposed to be discarded */ -+#define DPAA2_ETH_FAS_DISC 0x80000000 -+/* MACSEC frame */ -+#define DPAA2_ETH_FAS_MS 0x40000000 -+#define DPAA2_ETH_FAS_PTP 0x08000000 -+/* Ethernet multicast frame */ -+#define DPAA2_ETH_FAS_MC 0x04000000 -+/* Ethernet broadcast frame */ -+#define DPAA2_ETH_FAS_BC 0x02000000 -+#define DPAA2_ETH_FAS_KSE 0x00040000 -+#define DPAA2_ETH_FAS_EOFHE 0x00020000 -+#define DPAA2_ETH_FAS_MNLE 0x00010000 -+#define DPAA2_ETH_FAS_TIDE 0x00008000 -+#define DPAA2_ETH_FAS_PIEE 0x00004000 -+/* Frame length error */ -+#define DPAA2_ETH_FAS_FLE 0x00002000 -+/* Frame physical error; our favourite pastime */ -+#define DPAA2_ETH_FAS_FPE 0x00001000 -+#define DPAA2_ETH_FAS_PTE 0x00000080 -+#define DPAA2_ETH_FAS_ISP 0x00000040 -+#define DPAA2_ETH_FAS_PHE 0x00000020 -+#define DPAA2_ETH_FAS_BLE 0x00000010 -+/* L3 csum validation performed */ -+#define DPAA2_ETH_FAS_L3CV 0x00000008 -+/* L3 csum error */ -+#define DPAA2_ETH_FAS_L3CE 0x00000004 -+/* L4 csum validation performed */ -+#define DPAA2_ETH_FAS_L4CV 0x00000002 -+/* L4 csum error */ -+#define DPAA2_ETH_FAS_L4CE 0x00000001 -+/* These bits always signal errors */ -+#define DPAA2_ETH_RX_ERR_MASK (DPAA2_ETH_FAS_KSE | \ -+ DPAA2_ETH_FAS_EOFHE | \ -+ DPAA2_ETH_FAS_MNLE | \ -+ DPAA2_ETH_FAS_TIDE | \ -+ DPAA2_ETH_FAS_PIEE | \ -+ DPAA2_ETH_FAS_FLE | \ -+ DPAA2_ETH_FAS_FPE | \ -+ DPAA2_ETH_FAS_PTE | \ -+ DPAA2_ETH_FAS_ISP | \ -+ DPAA2_ETH_FAS_PHE | \ -+ DPAA2_ETH_FAS_BLE | \ -+ DPAA2_ETH_FAS_L3CE | \ -+ DPAA2_ETH_FAS_L4CE) -+/* Unsupported features in the ingress */ -+#define DPAA2_ETH_RX_UNSUPP_MASK DPAA2_ETH_FAS_MS -+/* Tx errors */ -+#define DPAA2_ETH_TXCONF_ERR_MASK (DPAA2_ETH_FAS_KSE | \ -+ DPAA2_ETH_FAS_EOFHE | \ -+ DPAA2_ETH_FAS_MNLE | \ -+ DPAA2_ETH_FAS_TIDE) -+ -+/* Time in milliseconds between link state updates */ -+#define DPAA2_ETH_LINK_STATE_REFRESH 1000 -+ -+/* Driver statistics, other than those in struct rtnl_link_stats64. -+ * These are usually collected per-CPU and aggregated by ethtool. -+ */ -+struct dpaa2_eth_stats { -+ __u64 tx_conf_frames; -+ __u64 tx_conf_bytes; -+ __u64 tx_sg_frames; -+ __u64 tx_sg_bytes; -+ __u64 rx_sg_frames; -+ __u64 rx_sg_bytes; -+ /* Enqueues retried due to portal busy */ -+ __u64 tx_portal_busy; -+}; -+ -+/* Per-FQ statistics */ -+struct dpaa2_eth_fq_stats { -+ /* Number of frames received on this queue */ -+ __u64 frames; -+}; -+ -+/* Per-channel statistics */ -+struct dpaa2_eth_ch_stats { -+ /* Volatile dequeues retried due to portal busy */ -+ __u64 dequeue_portal_busy; -+ /* Number of CDANs; useful to estimate avg NAPI len */ -+ __u64 cdan; -+ /* Number of frames received on queues from this channel */ -+ __u64 frames; -+}; -+ -+/* Maximum number of Rx queues associated with a DPNI */ -+#define DPAA2_ETH_MAX_RX_QUEUES 16 -+#define DPAA2_ETH_MAX_TX_QUEUES NR_CPUS -+#define DPAA2_ETH_MAX_RX_ERR_QUEUES 1 -+#define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \ -+ DPAA2_ETH_MAX_TX_QUEUES + \ -+ DPAA2_ETH_MAX_RX_ERR_QUEUES) -+ -+#define DPAA2_ETH_MAX_DPCONS NR_CPUS -+ -+enum dpaa2_eth_fq_type { -+ DPAA2_RX_FQ = 0, -+ DPAA2_TX_CONF_FQ, -+ DPAA2_RX_ERR_FQ -+}; -+ -+struct dpaa2_eth_priv; -+ -+struct dpaa2_eth_fq { -+ u32 fqid; -+ u16 flowid; -+ int target_cpu; -+ struct dpaa2_eth_channel *channel; -+ enum dpaa2_eth_fq_type type; -+ -+ void (*consume)(struct dpaa2_eth_priv *, -+ struct dpaa2_eth_channel *, -+ const struct dpaa2_fd *, -+ struct napi_struct *); -+ struct dpaa2_eth_priv *netdev_priv; /* backpointer */ -+ struct dpaa2_eth_fq_stats stats; -+}; -+ -+struct dpaa2_eth_channel { -+ struct dpaa2_io_notification_ctx nctx; -+ struct fsl_mc_device *dpcon; -+ int dpcon_id; -+ int ch_id; -+ int dpio_id; -+ struct napi_struct napi; -+ struct dpaa2_io_store *store; -+ struct dpaa2_eth_priv *priv; -+ int buf_count; -+ struct dpaa2_eth_ch_stats stats; -+}; -+ -+struct dpaa2_cls_rule { -+ struct ethtool_rx_flow_spec fs; -+ bool in_use; -+}; -+ -+struct dpaa2_eth_priv { -+ struct net_device *net_dev; -+ -+ u8 num_fqs; -+ /* First queue is tx conf, the rest are rx */ -+ struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES]; -+ -+ u8 num_channels; -+ struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS]; -+ -+ int dpni_id; -+ struct dpni_attr dpni_attrs; -+ struct dpni_extended_cfg dpni_ext_cfg; -+ /* Insofar as the MC is concerned, we're using one layout on all 3 types -+ * of buffers (Rx, Tx, Tx-Conf). -+ */ -+ struct dpni_buffer_layout buf_layout; -+ u16 tx_data_offset; -+ -+ struct fsl_mc_device *dpbp_dev; -+ struct dpbp_attr dpbp_attrs; -+ -+ u16 tx_qdid; -+ struct fsl_mc_io *mc_io; -+ /* SysFS-controlled affinity mask for TxConf FQs */ -+ struct cpumask txconf_cpumask; -+ /* Cores which have an affine DPIO/DPCON. -+ * This is the cpu set on which Rx frames are processed; -+ * Tx confirmation frames are processed on a subset of this, -+ * depending on user settings. -+ */ -+ struct cpumask dpio_cpumask; -+ -+ /* Standard statistics */ -+ struct rtnl_link_stats64 __percpu *percpu_stats; -+ /* Extra stats, in addition to the ones known by the kernel */ -+ struct dpaa2_eth_stats __percpu *percpu_extras; -+ u32 msg_enable; /* net_device message level */ -+ -+ u16 mc_token; -+ -+ struct dpni_link_state link_state; -+ struct task_struct *poll_thread; -+ -+ /* enabled ethtool hashing bits */ -+ u64 rx_hash_fields; -+ -+#ifdef CONFIG_FSL_DPAA2_ETH_DEBUGFS -+ struct dpaa2_debugfs dbg; -+#endif -+ -+ /* array of classification rules */ -+ struct dpaa2_cls_rule *cls_rule; -+ -+ struct dpni_tx_shaping_cfg shaping_cfg; -+ -+ bool ts_tx_en; /* Tx timestamping enabled */ -+ bool ts_rx_en; /* Rx timestamping enabled */ -+}; -+ -+/* default Rx hash options, set during probing */ -+#define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \ -+ | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \ -+ | RXH_L4_B_2_3) -+ -+#define dpaa2_eth_hash_enabled(priv) \ -+ ((priv)->dpni_attrs.options & DPNI_OPT_DIST_HASH) -+ -+#define dpaa2_eth_fs_enabled(priv) \ -+ ((priv)->dpni_attrs.options & DPNI_OPT_DIST_FS) -+ -+#define DPAA2_CLASSIFIER_ENTRY_COUNT 16 -+ -+/* Required by struct dpni_attr::ext_cfg_iova */ -+#define DPAA2_EXT_CFG_SIZE 256 -+ -+extern const struct ethtool_ops dpaa2_ethtool_ops; -+ -+int dpaa2_set_hash(struct net_device *net_dev, u64 flags); -+ -+static int dpaa2_queue_count(struct dpaa2_eth_priv *priv) -+{ -+ if (!dpaa2_eth_hash_enabled(priv)) -+ return 1; -+ -+ return priv->dpni_ext_cfg.tc_cfg[0].max_dist; -+} -+ -+static inline int dpaa2_max_channels(struct dpaa2_eth_priv *priv) -+{ -+ /* Ideally, we want a number of channels large enough -+ * to accommodate both the Rx distribution size -+ * and the max number of Tx confirmation queues -+ */ -+ return max_t(int, dpaa2_queue_count(priv), -+ priv->dpni_attrs.max_senders); -+} -+ -+void dpaa2_cls_check(struct net_device *); -+ -+#endif /* __DPAA2_H */ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c -@@ -0,0 +1,882 @@ -+/* Copyright 2014-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "dpni.h" /* DPNI_LINK_OPT_* */ -+#include "dpaa2-eth.h" -+ -+/* size of DMA memory used to pass configuration to classifier, in bytes */ -+#define DPAA2_CLASSIFIER_DMA_SIZE 256 -+ -+/* To be kept in sync with 'enum dpni_counter' */ -+char dpaa2_ethtool_stats[][ETH_GSTRING_LEN] = { -+ "rx frames", -+ "rx bytes", -+ "rx frames dropped", -+ "rx err frames", -+ "rx mcast frames", -+ "rx mcast bytes", -+ "rx bcast frames", -+ "rx bcast bytes", -+ "tx frames", -+ "tx bytes", -+ "tx err frames", -+}; -+ -+#define DPAA2_ETH_NUM_STATS ARRAY_SIZE(dpaa2_ethtool_stats) -+ -+/* To be kept in sync with 'struct dpaa2_eth_stats' */ -+char dpaa2_ethtool_extras[][ETH_GSTRING_LEN] = { -+ /* per-cpu stats */ -+ -+ "tx conf frames", -+ "tx conf bytes", -+ "tx sg frames", -+ "tx sg bytes", -+ "rx sg frames", -+ "rx sg bytes", -+ /* how many times we had to retry the enqueue command */ -+ "tx portal busy", -+ -+ /* Channel stats */ -+ -+ /* How many times we had to retry the volatile dequeue command */ -+ "portal busy", -+ /* Number of notifications received */ -+ "cdan", -+#ifdef CONFIG_FSL_QBMAN_DEBUG -+ /* FQ stats */ -+ "rx pending frames", -+ "rx pending bytes", -+ "tx conf pending frames", -+ "tx conf pending bytes", -+ "buffer count" -+#endif -+}; -+ -+#define DPAA2_ETH_NUM_EXTRA_STATS ARRAY_SIZE(dpaa2_ethtool_extras) -+ -+static void dpaa2_get_drvinfo(struct net_device *net_dev, -+ struct ethtool_drvinfo *drvinfo) -+{ -+ struct mc_version mc_ver; -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ char fw_version[ETHTOOL_FWVERS_LEN]; -+ char version[32]; -+ int err; -+ -+ err = mc_get_version(priv->mc_io, 0, &mc_ver); -+ if (err) { -+ strlcpy(drvinfo->fw_version, "Error retrieving MC version", -+ sizeof(drvinfo->fw_version)); -+ } else { -+ scnprintf(fw_version, sizeof(fw_version), "%d.%d.%d", -+ mc_ver.major, mc_ver.minor, mc_ver.revision); -+ strlcpy(drvinfo->fw_version, fw_version, -+ sizeof(drvinfo->fw_version)); -+ } -+ -+ scnprintf(version, sizeof(version), "%d.%d", DPNI_VER_MAJOR, -+ DPNI_VER_MINOR); -+ strlcpy(drvinfo->version, version, sizeof(drvinfo->version)); -+ -+ strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver)); -+ strlcpy(drvinfo->bus_info, dev_name(net_dev->dev.parent->parent), -+ sizeof(drvinfo->bus_info)); -+} -+ -+static u32 dpaa2_get_msglevel(struct net_device *net_dev) -+{ -+ return ((struct dpaa2_eth_priv *)netdev_priv(net_dev))->msg_enable; -+} -+ -+static void dpaa2_set_msglevel(struct net_device *net_dev, -+ u32 msg_enable) -+{ -+ ((struct dpaa2_eth_priv *)netdev_priv(net_dev))->msg_enable = -+ msg_enable; -+} -+ -+static int dpaa2_get_settings(struct net_device *net_dev, -+ struct ethtool_cmd *cmd) -+{ -+ struct dpni_link_state state = {0}; -+ int err = 0; -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ -+ err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state); -+ if (err) { -+ netdev_err(net_dev, "ERROR %d getting link state", err); -+ goto out; -+ } -+ -+ /* At the moment, we have no way of interrogating the DPMAC -+ * from the DPNI side - and for that matter there may exist -+ * no DPMAC at all. So for now we just don't report anything -+ * beyond the DPNI attributes. -+ */ -+ if (state.options & DPNI_LINK_OPT_AUTONEG) -+ cmd->autoneg = AUTONEG_ENABLE; -+ if (!(state.options & DPNI_LINK_OPT_HALF_DUPLEX)) -+ cmd->duplex = DUPLEX_FULL; -+ ethtool_cmd_speed_set(cmd, state.rate); -+ -+out: -+ return err; -+} -+ -+static int dpaa2_set_settings(struct net_device *net_dev, -+ struct ethtool_cmd *cmd) -+{ -+ struct dpni_link_cfg cfg = {0}; -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ int err = 0; -+ -+ netdev_dbg(net_dev, "Setting link parameters..."); -+ -+ /* Due to a temporary firmware limitation, the DPNI must be down -+ * in order to be able to change link settings. Taking steps to let -+ * the user know that. -+ */ -+ if (netif_running(net_dev)) { -+ netdev_info(net_dev, "Sorry, interface must be brought down first.\n"); -+ return -EACCES; -+ } -+ -+ cfg.rate = ethtool_cmd_speed(cmd); -+ if (cmd->autoneg == AUTONEG_ENABLE) -+ cfg.options |= DPNI_LINK_OPT_AUTONEG; -+ else -+ cfg.options &= ~DPNI_LINK_OPT_AUTONEG; -+ if (cmd->duplex == DUPLEX_HALF) -+ cfg.options |= DPNI_LINK_OPT_HALF_DUPLEX; -+ else -+ cfg.options &= ~DPNI_LINK_OPT_HALF_DUPLEX; -+ -+ err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &cfg); -+ if (err) -+ /* ethtool will be loud enough if we return an error; no point -+ * in putting our own error message on the console by default -+ */ -+ netdev_dbg(net_dev, "ERROR %d setting link cfg", err); -+ -+ return err; -+} -+ -+static void dpaa2_get_strings(struct net_device *netdev, u32 stringset, -+ u8 *data) -+{ -+ u8 *p = data; -+ int i; -+ -+ switch (stringset) { -+ case ETH_SS_STATS: -+ for (i = 0; i < DPAA2_ETH_NUM_STATS; i++) { -+ strlcpy(p, dpaa2_ethtool_stats[i], ETH_GSTRING_LEN); -+ p += ETH_GSTRING_LEN; -+ } -+ for (i = 0; i < DPAA2_ETH_NUM_EXTRA_STATS; i++) { -+ strlcpy(p, dpaa2_ethtool_extras[i], ETH_GSTRING_LEN); -+ p += ETH_GSTRING_LEN; -+ } -+ break; -+ } -+} -+ -+static int dpaa2_get_sset_count(struct net_device *net_dev, int sset) -+{ -+ switch (sset) { -+ case ETH_SS_STATS: /* ethtool_get_stats(), ethtool_get_drvinfo() */ -+ return DPAA2_ETH_NUM_STATS + DPAA2_ETH_NUM_EXTRA_STATS; -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+/** Fill in hardware counters, as returned by the MC firmware. -+ */ -+static void dpaa2_get_ethtool_stats(struct net_device *net_dev, -+ struct ethtool_stats *stats, -+ u64 *data) -+{ -+ int i; /* Current index in the data array */ -+ int j, k, err; -+ -+#ifdef CONFIG_FSL_QBMAN_DEBUG -+ u32 fcnt, bcnt; -+ u32 fcnt_rx_total = 0, fcnt_tx_total = 0; -+ u32 bcnt_rx_total = 0, bcnt_tx_total = 0; -+ u32 buf_cnt; -+#endif -+ u64 cdan = 0; -+ u64 portal_busy = 0; -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ struct dpaa2_eth_stats *extras; -+ struct dpaa2_eth_ch_stats *ch_stats; -+ -+ memset(data, 0, -+ sizeof(u64) * (DPAA2_ETH_NUM_STATS + DPAA2_ETH_NUM_EXTRA_STATS)); -+ -+ /* Print standard counters, from DPNI statistics */ -+ for (i = 0; i < DPAA2_ETH_NUM_STATS; i++) { -+ err = dpni_get_counter(priv->mc_io, 0, priv->mc_token, i, -+ data + i); -+ if (err != 0) -+ netdev_warn(net_dev, "Err %d getting DPNI counter %d", -+ err, i); -+ } -+ -+ /* Print per-cpu extra stats */ -+ for_each_online_cpu(k) { -+ extras = per_cpu_ptr(priv->percpu_extras, k); -+ for (j = 0; j < sizeof(*extras) / sizeof(__u64); j++) -+ *((__u64 *)data + i + j) += *((__u64 *)extras + j); -+ } -+ i += j; -+ -+ /* We may be using fewer DPIOs than actual CPUs */ -+ for_each_cpu(j, &priv->dpio_cpumask) { -+ ch_stats = &priv->channel[j]->stats; -+ cdan += ch_stats->cdan; -+ portal_busy += ch_stats->dequeue_portal_busy; -+ } -+ -+ *(data + i++) = portal_busy; -+ *(data + i++) = cdan; -+ -+#ifdef CONFIG_FSL_QBMAN_DEBUG -+ for (j = 0; j < priv->num_fqs; j++) { -+ /* Print FQ instantaneous counts */ -+ err = dpaa2_io_query_fq_count(NULL, priv->fq[j].fqid, -+ &fcnt, &bcnt); -+ if (err) { -+ netdev_warn(net_dev, "FQ query error %d", err); -+ return; -+ } -+ -+ if (priv->fq[j].type == DPAA2_TX_CONF_FQ) { -+ fcnt_tx_total += fcnt; -+ bcnt_tx_total += bcnt; -+ } else { -+ fcnt_rx_total += fcnt; -+ bcnt_rx_total += bcnt; -+ } -+ } -+ *(data + i++) = fcnt_rx_total; -+ *(data + i++) = bcnt_rx_total; -+ *(data + i++) = fcnt_tx_total; -+ *(data + i++) = bcnt_tx_total; -+ -+ err = dpaa2_io_query_bp_count(NULL, priv->dpbp_attrs.bpid, &buf_cnt); -+ if (err) { -+ netdev_warn(net_dev, "Buffer count query error %d\n", err); -+ return; -+ } -+ *(data + i++) = buf_cnt; -+#endif -+} -+ -+static const struct dpaa2_hash_fields { -+ u64 rxnfc_field; -+ enum net_prot cls_prot; -+ int cls_field; -+ int size; -+} dpaa2_hash_fields[] = { -+ { -+ /* L2 header */ -+ .rxnfc_field = RXH_L2DA, -+ .cls_prot = NET_PROT_ETH, -+ .cls_field = NH_FLD_ETH_DA, -+ .size = 6, -+ }, { -+ /* VLAN header */ -+ .rxnfc_field = RXH_VLAN, -+ .cls_prot = NET_PROT_VLAN, -+ .cls_field = NH_FLD_VLAN_TCI, -+ .size = 2, -+ }, { -+ /* IP header */ -+ .rxnfc_field = RXH_IP_SRC, -+ .cls_prot = NET_PROT_IP, -+ .cls_field = NH_FLD_IP_SRC, -+ .size = 4, -+ }, { -+ .rxnfc_field = RXH_IP_DST, -+ .cls_prot = NET_PROT_IP, -+ .cls_field = NH_FLD_IP_DST, -+ .size = 4, -+ }, { -+ .rxnfc_field = RXH_L3_PROTO, -+ .cls_prot = NET_PROT_IP, -+ .cls_field = NH_FLD_IP_PROTO, -+ .size = 1, -+ }, { -+ /* Using UDP ports, this is functionally equivalent to raw -+ * byte pairs from L4 header. -+ */ -+ .rxnfc_field = RXH_L4_B_0_1, -+ .cls_prot = NET_PROT_UDP, -+ .cls_field = NH_FLD_UDP_PORT_SRC, -+ .size = 2, -+ }, { -+ .rxnfc_field = RXH_L4_B_2_3, -+ .cls_prot = NET_PROT_UDP, -+ .cls_field = NH_FLD_UDP_PORT_DST, -+ .size = 2, -+ }, -+}; -+ -+static int dpaa2_cls_is_enabled(struct net_device *net_dev, u64 flag) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ -+ return !!(priv->rx_hash_fields & flag); -+} -+ -+static int dpaa2_cls_key_off(struct net_device *net_dev, u64 flag) -+{ -+ int i, off = 0; -+ -+ for (i = 0; i < ARRAY_SIZE(dpaa2_hash_fields); i++) { -+ if (dpaa2_hash_fields[i].rxnfc_field & flag) -+ return off; -+ if (dpaa2_cls_is_enabled(net_dev, -+ dpaa2_hash_fields[i].rxnfc_field)) -+ off += dpaa2_hash_fields[i].size; -+ } -+ -+ return -1; -+} -+ -+static u8 dpaa2_cls_key_size(struct net_device *net_dev) -+{ -+ u8 i, size = 0; -+ -+ for (i = 0; i < ARRAY_SIZE(dpaa2_hash_fields); i++) { -+ if (!dpaa2_cls_is_enabled(net_dev, -+ dpaa2_hash_fields[i].rxnfc_field)) -+ continue; -+ size += dpaa2_hash_fields[i].size; -+ } -+ -+ return size; -+} -+ -+static u8 dpaa2_cls_max_key_size(struct net_device *net_dev) -+{ -+ u8 i, size = 0; -+ -+ for (i = 0; i < ARRAY_SIZE(dpaa2_hash_fields); i++) -+ size += dpaa2_hash_fields[i].size; -+ -+ return size; -+} -+ -+void dpaa2_cls_check(struct net_device *net_dev) -+{ -+ u8 key_size = dpaa2_cls_max_key_size(net_dev); -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ -+ if (priv->dpni_attrs.options & DPNI_OPT_DIST_FS && -+ priv->dpni_attrs.max_dist_key_size < key_size) { -+ dev_err(&net_dev->dev, -+ "max_dist_key_size = %d, expected %d. Steering is disabled\n", -+ priv->dpni_attrs.max_dist_key_size, -+ key_size); -+ priv->dpni_attrs.options &= ~DPNI_OPT_DIST_FS; -+ } -+} -+ -+/* Set RX hash options -+ * flags is a combination of RXH_ bits -+ */ -+int dpaa2_set_hash(struct net_device *net_dev, u64 flags) -+{ -+ struct device *dev = net_dev->dev.parent; -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ struct dpkg_profile_cfg cls_cfg; -+ struct dpni_rx_tc_dist_cfg dist_cfg; -+ u8 *dma_mem; -+ u64 enabled_flags = 0; -+ int i; -+ int err = 0; -+ -+ if (!dpaa2_eth_hash_enabled(priv)) { -+ dev_err(dev, "Hashing support is not enabled\n"); -+ return -EOPNOTSUPP; -+ } -+ -+ if (flags & ~DPAA2_RXH_SUPPORTED) { -+ /* RXH_DISCARD is not supported */ -+ dev_err(dev, "unsupported option selected, supported options are: mvtsdfn\n"); -+ return -EOPNOTSUPP; -+ } -+ -+ memset(&cls_cfg, 0, sizeof(cls_cfg)); -+ -+ for (i = 0; i < ARRAY_SIZE(dpaa2_hash_fields); i++) { -+ struct dpkg_extract *key = -+ &cls_cfg.extracts[cls_cfg.num_extracts]; -+ -+ if (!(flags & dpaa2_hash_fields[i].rxnfc_field)) -+ continue; -+ -+ if (cls_cfg.num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS) { -+ dev_err(dev, "error adding key extraction rule, too many rules?\n"); -+ return -E2BIG; -+ } -+ -+ key->type = DPKG_EXTRACT_FROM_HDR; -+ key->extract.from_hdr.prot = -+ dpaa2_hash_fields[i].cls_prot; -+ key->extract.from_hdr.type = DPKG_FULL_FIELD; -+ key->extract.from_hdr.field = -+ dpaa2_hash_fields[i].cls_field; -+ cls_cfg.num_extracts++; -+ -+ enabled_flags |= dpaa2_hash_fields[i].rxnfc_field; -+ } -+ -+ dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_DMA | GFP_KERNEL); -+ if (!dma_mem) -+ return -ENOMEM; -+ -+ err = dpni_prepare_key_cfg(&cls_cfg, dma_mem); -+ if (err) { -+ dev_err(dev, "dpni_prepare_key_cfg error %d", err); -+ return err; -+ } -+ -+ memset(&dist_cfg, 0, sizeof(dist_cfg)); -+ -+ /* Prepare for setting the rx dist */ -+ dist_cfg.key_cfg_iova = dma_map_single(net_dev->dev.parent, dma_mem, -+ DPAA2_CLASSIFIER_DMA_SIZE, -+ DMA_TO_DEVICE); -+ if (dma_mapping_error(net_dev->dev.parent, dist_cfg.key_cfg_iova)) { -+ dev_err(dev, "DMA mapping failed\n"); -+ kfree(dma_mem); -+ return -ENOMEM; -+ } -+ -+ dist_cfg.dist_size = dpaa2_queue_count(priv); -+ if (dpaa2_eth_fs_enabled(priv)) { -+ dist_cfg.dist_mode = DPNI_DIST_MODE_FS; -+ dist_cfg.fs_cfg.miss_action = DPNI_FS_MISS_HASH; -+ } else { -+ dist_cfg.dist_mode = DPNI_DIST_MODE_HASH; -+ } -+ -+ err = dpni_set_rx_tc_dist(priv->mc_io, 0, priv->mc_token, 0, &dist_cfg); -+ dma_unmap_single(net_dev->dev.parent, dist_cfg.key_cfg_iova, -+ DPAA2_CLASSIFIER_DMA_SIZE, DMA_TO_DEVICE); -+ kfree(dma_mem); -+ if (err) { -+ dev_err(dev, "dpni_set_rx_tc_dist() error %d\n", err); -+ return err; -+ } -+ -+ priv->rx_hash_fields = enabled_flags; -+ -+ return 0; -+} -+ -+static int dpaa2_cls_prep_rule(struct net_device *net_dev, -+ struct ethtool_rx_flow_spec *fs, -+ void *key) -+{ -+ struct ethtool_tcpip4_spec *l4ip4_h, *l4ip4_m; -+ struct ethhdr *eth_h, *eth_m; -+ struct ethtool_flow_ext *ext_h, *ext_m; -+ const u8 key_size = dpaa2_cls_key_size(net_dev); -+ void *msk = key + key_size; -+ -+ memset(key, 0, key_size * 2); -+ -+ /* This code is a major mess, it has to be cleaned up after the -+ * classification mask issue is fixed and key format will be made static -+ */ -+ -+ switch (fs->flow_type & 0xff) { -+ case TCP_V4_FLOW: -+ l4ip4_h = &fs->h_u.tcp_ip4_spec; -+ l4ip4_m = &fs->m_u.tcp_ip4_spec; -+ /* TODO: ethertype to match IPv4 and protocol to match TCP */ -+ goto l4ip4; -+ -+ case UDP_V4_FLOW: -+ l4ip4_h = &fs->h_u.udp_ip4_spec; -+ l4ip4_m = &fs->m_u.udp_ip4_spec; -+ goto l4ip4; -+ -+ case SCTP_V4_FLOW: -+ l4ip4_h = &fs->h_u.sctp_ip4_spec; -+ l4ip4_m = &fs->m_u.sctp_ip4_spec; -+ -+l4ip4: -+ if (l4ip4_m->tos) { -+ netdev_err(net_dev, -+ "ToS is not supported for IPv4 L4\n"); -+ return -EOPNOTSUPP; -+ } -+ if (l4ip4_m->ip4src && -+ !dpaa2_cls_is_enabled(net_dev, RXH_IP_SRC)) { -+ netdev_err(net_dev, "IP SRC not supported!\n"); -+ return -EOPNOTSUPP; -+ } -+ if (l4ip4_m->ip4dst && -+ !dpaa2_cls_is_enabled(net_dev, RXH_IP_DST)) { -+ netdev_err(net_dev, "IP DST not supported!\n"); -+ return -EOPNOTSUPP; -+ } -+ if (l4ip4_m->psrc && -+ !dpaa2_cls_is_enabled(net_dev, RXH_L4_B_0_1)) { -+ netdev_err(net_dev, "PSRC not supported, ignored\n"); -+ return -EOPNOTSUPP; -+ } -+ if (l4ip4_m->pdst && -+ !dpaa2_cls_is_enabled(net_dev, RXH_L4_B_2_3)) { -+ netdev_err(net_dev, "PDST not supported, ignored\n"); -+ return -EOPNOTSUPP; -+ } -+ -+ if (dpaa2_cls_is_enabled(net_dev, RXH_IP_SRC)) { -+ *(u32 *)(key + dpaa2_cls_key_off(net_dev, RXH_IP_SRC)) -+ = l4ip4_h->ip4src; -+ *(u32 *)(msk + dpaa2_cls_key_off(net_dev, RXH_IP_SRC)) -+ = l4ip4_m->ip4src; -+ } -+ if (dpaa2_cls_is_enabled(net_dev, RXH_IP_DST)) { -+ *(u32 *)(key + dpaa2_cls_key_off(net_dev, RXH_IP_DST)) -+ = l4ip4_h->ip4dst; -+ *(u32 *)(msk + dpaa2_cls_key_off(net_dev, RXH_IP_DST)) -+ = l4ip4_m->ip4dst; -+ } -+ -+ if (dpaa2_cls_is_enabled(net_dev, RXH_L4_B_0_1)) { -+ *(u32 *)(key + dpaa2_cls_key_off(net_dev, RXH_L4_B_0_1)) -+ = l4ip4_h->psrc; -+ *(u32 *)(msk + dpaa2_cls_key_off(net_dev, RXH_L4_B_0_1)) -+ = l4ip4_m->psrc; -+ } -+ -+ if (dpaa2_cls_is_enabled(net_dev, RXH_L4_B_2_3)) { -+ *(u32 *)(key + dpaa2_cls_key_off(net_dev, RXH_L4_B_2_3)) -+ = l4ip4_h->pdst; -+ *(u32 *)(msk + dpaa2_cls_key_off(net_dev, RXH_L4_B_2_3)) -+ = l4ip4_m->pdst; -+ } -+ break; -+ -+ case ETHER_FLOW: -+ eth_h = &fs->h_u.ether_spec; -+ eth_m = &fs->m_u.ether_spec; -+ -+ if (eth_m->h_proto) { -+ netdev_err(net_dev, "Ethertype is not supported!\n"); -+ return -EOPNOTSUPP; -+ } -+ -+ if (!is_zero_ether_addr(eth_m->h_source)) { -+ netdev_err(net_dev, "ETH SRC is not supported!\n"); -+ return -EOPNOTSUPP; -+ } -+ -+ if (dpaa2_cls_is_enabled(net_dev, RXH_L2DA)) { -+ ether_addr_copy(key -+ + dpaa2_cls_key_off(net_dev, RXH_L2DA), -+ eth_h->h_dest); -+ ether_addr_copy(msk -+ + dpaa2_cls_key_off(net_dev, RXH_L2DA), -+ eth_m->h_dest); -+ } else { -+ if (!is_zero_ether_addr(eth_m->h_dest)) { -+ netdev_err(net_dev, -+ "ETH DST is not supported!\n"); -+ return -EOPNOTSUPP; -+ } -+ } -+ break; -+ -+ default: -+ /* TODO: IP user flow, AH, ESP */ -+ return -EOPNOTSUPP; -+ } -+ -+ if (fs->flow_type & FLOW_EXT) { -+ /* TODO: ETH data, VLAN ethertype, VLAN TCI .. */ -+ return -EOPNOTSUPP; -+ } -+ -+ if (fs->flow_type & FLOW_MAC_EXT) { -+ ext_h = &fs->h_ext; -+ ext_m = &fs->m_ext; -+ -+ if (dpaa2_cls_is_enabled(net_dev, RXH_L2DA)) { -+ ether_addr_copy(key -+ + dpaa2_cls_key_off(net_dev, RXH_L2DA), -+ ext_h->h_dest); -+ ether_addr_copy(msk -+ + dpaa2_cls_key_off(net_dev, RXH_L2DA), -+ ext_m->h_dest); -+ } else { -+ if (!is_zero_ether_addr(ext_m->h_dest)) { -+ netdev_err(net_dev, -+ "ETH DST is not supported!\n"); -+ return -EOPNOTSUPP; -+ } -+ } -+ } -+ return 0; -+} -+ -+static int dpaa2_do_cls(struct net_device *net_dev, -+ struct ethtool_rx_flow_spec *fs, -+ bool add) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ const int rule_cnt = DPAA2_CLASSIFIER_ENTRY_COUNT; -+ struct dpni_rule_cfg rule_cfg; -+ void *dma_mem; -+ int err = 0; -+ -+ if (!dpaa2_eth_fs_enabled(priv)) { -+ netdev_err(net_dev, "dev does not support steering!\n"); -+ /* dev doesn't support steering */ -+ return -EOPNOTSUPP; -+ } -+ -+ if ((fs->ring_cookie != RX_CLS_FLOW_DISC && -+ fs->ring_cookie >= dpaa2_queue_count(priv)) || -+ fs->location >= rule_cnt) -+ return -EINVAL; -+ -+ memset(&rule_cfg, 0, sizeof(rule_cfg)); -+ rule_cfg.key_size = dpaa2_cls_key_size(net_dev); -+ -+ /* allocate twice the key size, for the actual key and for mask */ -+ dma_mem = kzalloc(rule_cfg.key_size * 2, GFP_DMA | GFP_KERNEL); -+ if (!dma_mem) -+ return -ENOMEM; -+ -+ err = dpaa2_cls_prep_rule(net_dev, fs, dma_mem); -+ if (err) -+ goto err_free_mem; -+ -+ rule_cfg.key_iova = dma_map_single(net_dev->dev.parent, dma_mem, -+ rule_cfg.key_size * 2, -+ DMA_TO_DEVICE); -+ -+ rule_cfg.mask_iova = rule_cfg.key_iova + rule_cfg.key_size; -+ -+ if (!(priv->dpni_attrs.options & DPNI_OPT_FS_MASK_SUPPORT)) { -+ int i; -+ u8 *mask = dma_mem + rule_cfg.key_size; -+ -+ /* check that nothing is masked out, otherwise it won't work */ -+ for (i = 0; i < rule_cfg.key_size; i++) { -+ if (mask[i] == 0xff) -+ continue; -+ netdev_err(net_dev, "dev does not support masking!\n"); -+ err = -EOPNOTSUPP; -+ goto err_free_mem; -+ } -+ rule_cfg.mask_iova = 0; -+ } -+ -+ /* No way to control rule order in firmware */ -+ if (add) -+ err = dpni_add_fs_entry(priv->mc_io, 0, priv->mc_token, 0, -+ &rule_cfg, (u16)fs->ring_cookie); -+ else -+ err = dpni_remove_fs_entry(priv->mc_io, 0, priv->mc_token, 0, -+ &rule_cfg); -+ -+ dma_unmap_single(net_dev->dev.parent, rule_cfg.key_iova, -+ rule_cfg.key_size * 2, DMA_TO_DEVICE); -+ if (err) { -+ netdev_err(net_dev, "dpaa2_add_cls() error %d\n", err); -+ goto err_free_mem; -+ } -+ -+ priv->cls_rule[fs->location].fs = *fs; -+ priv->cls_rule[fs->location].in_use = true; -+ -+err_free_mem: -+ kfree(dma_mem); -+ -+ return err; -+} -+ -+static int dpaa2_add_cls(struct net_device *net_dev, -+ struct ethtool_rx_flow_spec *fs) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ int err; -+ -+ err = dpaa2_do_cls(net_dev, fs, true); -+ if (err) -+ return err; -+ -+ priv->cls_rule[fs->location].in_use = true; -+ priv->cls_rule[fs->location].fs = *fs; -+ -+ return 0; -+} -+ -+static int dpaa2_del_cls(struct net_device *net_dev, int location) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ int err; -+ -+ err = dpaa2_do_cls(net_dev, &priv->cls_rule[location].fs, false); -+ if (err) -+ return err; -+ -+ priv->cls_rule[location].in_use = false; -+ -+ return 0; -+} -+ -+static void dpaa2_clear_cls(struct net_device *net_dev) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ int i, err; -+ -+ for (i = 0; i < DPAA2_CLASSIFIER_ENTRY_COUNT; i++) { -+ if (!priv->cls_rule[i].in_use) -+ continue; -+ -+ err = dpaa2_del_cls(net_dev, i); -+ if (err) -+ netdev_warn(net_dev, -+ "err trying to delete classification entry %d\n", -+ i); -+ } -+} -+ -+static int dpaa2_set_rxnfc(struct net_device *net_dev, -+ struct ethtool_rxnfc *rxnfc) -+{ -+ int err = 0; -+ -+ switch (rxnfc->cmd) { -+ case ETHTOOL_SRXFH: -+ /* first off clear ALL classification rules, chaging key -+ * composition will break them anyway -+ */ -+ dpaa2_clear_cls(net_dev); -+ /* we purposely ignore cmd->flow_type for now, because the -+ * classifier only supports a single set of fields for all -+ * protocols -+ */ -+ err = dpaa2_set_hash(net_dev, rxnfc->data); -+ break; -+ case ETHTOOL_SRXCLSRLINS: -+ err = dpaa2_add_cls(net_dev, &rxnfc->fs); -+ break; -+ -+ case ETHTOOL_SRXCLSRLDEL: -+ err = dpaa2_del_cls(net_dev, rxnfc->fs.location); -+ break; -+ -+ default: -+ err = -EOPNOTSUPP; -+ } -+ -+ return err; -+} -+ -+static int dpaa2_get_rxnfc(struct net_device *net_dev, -+ struct ethtool_rxnfc *rxnfc, u32 *rule_locs) -+{ -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ const int rule_cnt = DPAA2_CLASSIFIER_ENTRY_COUNT; -+ int i, j; -+ -+ switch (rxnfc->cmd) { -+ case ETHTOOL_GRXFH: -+ /* we purposely ignore cmd->flow_type for now, because the -+ * classifier only supports a single set of fields for all -+ * protocols -+ */ -+ rxnfc->data = priv->rx_hash_fields; -+ break; -+ -+ case ETHTOOL_GRXRINGS: -+ rxnfc->data = dpaa2_queue_count(priv); -+ break; -+ -+ case ETHTOOL_GRXCLSRLCNT: -+ for (i = 0, rxnfc->rule_cnt = 0; i < rule_cnt; i++) -+ if (priv->cls_rule[i].in_use) -+ rxnfc->rule_cnt++; -+ rxnfc->data = rule_cnt; -+ break; -+ -+ case ETHTOOL_GRXCLSRULE: -+ if (!priv->cls_rule[rxnfc->fs.location].in_use) -+ return -EINVAL; -+ -+ rxnfc->fs = priv->cls_rule[rxnfc->fs.location].fs; -+ break; -+ -+ case ETHTOOL_GRXCLSRLALL: -+ for (i = 0, j = 0; i < rule_cnt; i++) { -+ if (!priv->cls_rule[i].in_use) -+ continue; -+ if (j == rxnfc->rule_cnt) -+ return -EMSGSIZE; -+ rule_locs[j++] = i; -+ } -+ rxnfc->rule_cnt = j; -+ rxnfc->data = rule_cnt; -+ break; -+ -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ return 0; -+} -+ -+const struct ethtool_ops dpaa2_ethtool_ops = { -+ .get_drvinfo = dpaa2_get_drvinfo, -+ .get_msglevel = dpaa2_get_msglevel, -+ .set_msglevel = dpaa2_set_msglevel, -+ .get_link = ethtool_op_get_link, -+ .get_settings = dpaa2_get_settings, -+ .set_settings = dpaa2_set_settings, -+ .get_sset_count = dpaa2_get_sset_count, -+ .get_ethtool_stats = dpaa2_get_ethtool_stats, -+ .get_strings = dpaa2_get_strings, -+ .get_rxnfc = dpaa2_get_rxnfc, -+ .set_rxnfc = dpaa2_set_rxnfc, -+}; ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpkg.h -@@ -0,0 +1,175 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef __FSL_DPKG_H_ -+#define __FSL_DPKG_H_ -+ -+#include -+#include "../../fsl-mc/include/net.h" -+ -+/* Data Path Key Generator API -+ * Contains initialization APIs and runtime APIs for the Key Generator -+ */ -+ -+/** Key Generator properties */ -+ -+/** -+ * Number of masks per key extraction -+ */ -+#define DPKG_NUM_OF_MASKS 4 -+/** -+ * Number of extractions per key profile -+ */ -+#define DPKG_MAX_NUM_OF_EXTRACTS 10 -+ -+/** -+ * enum dpkg_extract_from_hdr_type - Selecting extraction by header types -+ * @DPKG_FROM_HDR: Extract selected bytes from header, by offset -+ * @DPKG_FROM_FIELD: Extract selected bytes from header, by offset from field -+ * @DPKG_FULL_FIELD: Extract a full field -+ */ -+enum dpkg_extract_from_hdr_type { -+ DPKG_FROM_HDR = 0, -+ DPKG_FROM_FIELD = 1, -+ DPKG_FULL_FIELD = 2 -+}; -+ -+/** -+ * enum dpkg_extract_type - Enumeration for selecting extraction type -+ * @DPKG_EXTRACT_FROM_HDR: Extract from the header -+ * @DPKG_EXTRACT_FROM_DATA: Extract from data not in specific header -+ * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result; -+ * e.g. can be used to extract header existence; -+ * please refer to 'Parse Result definition' section in the parser BG -+ */ -+enum dpkg_extract_type { -+ DPKG_EXTRACT_FROM_HDR = 0, -+ DPKG_EXTRACT_FROM_DATA = 1, -+ DPKG_EXTRACT_FROM_PARSE = 3 -+}; -+ -+/** -+ * struct dpkg_mask - A structure for defining a single extraction mask -+ * @mask: Byte mask for the extracted content -+ * @offset: Offset within the extracted content -+ */ -+struct dpkg_mask { -+ uint8_t mask; -+ uint8_t offset; -+}; -+ -+/** -+ * struct dpkg_extract - A structure for defining a single extraction -+ * @type: Determines how the union below is interpreted: -+ * DPKG_EXTRACT_FROM_HDR: selects 'from_hdr'; -+ * DPKG_EXTRACT_FROM_DATA: selects 'from_data'; -+ * DPKG_EXTRACT_FROM_PARSE: selects 'from_parse' -+ * @extract: Selects extraction method -+ * @num_of_byte_masks: Defines the number of valid entries in the array below; -+ * This is also the number of bytes to be used as masks -+ * @masks: Masks parameters -+ */ -+struct dpkg_extract { -+ enum dpkg_extract_type type; -+ /** -+ * union extract - Selects extraction method -+ * @from_hdr - Used when 'type = DPKG_EXTRACT_FROM_HDR' -+ * @from_data - Used when 'type = DPKG_EXTRACT_FROM_DATA' -+ * @from_parse - Used when 'type = DPKG_EXTRACT_FROM_PARSE' -+ */ -+ union { -+ /** -+ * struct from_hdr - Used when 'type = DPKG_EXTRACT_FROM_HDR' -+ * @prot: Any of the supported headers -+ * @type: Defines the type of header extraction: -+ * DPKG_FROM_HDR: use size & offset below; -+ * DPKG_FROM_FIELD: use field, size and offset below; -+ * DPKG_FULL_FIELD: use field below -+ * @field: One of the supported fields (NH_FLD_) -+ * -+ * @size: Size in bytes -+ * @offset: Byte offset -+ * @hdr_index: Clear for cases not listed below; -+ * Used for protocols that may have more than a single -+ * header, 0 indicates an outer header; -+ * Supported protocols (possible values): -+ * NET_PROT_VLAN (0, HDR_INDEX_LAST); -+ * NET_PROT_MPLS (0, 1, HDR_INDEX_LAST); -+ * NET_PROT_IP(0, HDR_INDEX_LAST); -+ * NET_PROT_IPv4(0, HDR_INDEX_LAST); -+ * NET_PROT_IPv6(0, HDR_INDEX_LAST); -+ */ -+ -+ struct { -+ enum net_prot prot; -+ enum dpkg_extract_from_hdr_type type; -+ uint32_t field; -+ uint8_t size; -+ uint8_t offset; -+ uint8_t hdr_index; -+ } from_hdr; -+ /** -+ * struct from_data - Used when 'type = DPKG_EXTRACT_FROM_DATA' -+ * @size: Size in bytes -+ * @offset: Byte offset -+ */ -+ struct { -+ uint8_t size; -+ uint8_t offset; -+ } from_data; -+ -+ /** -+ * struct from_parse - Used when 'type = DPKG_EXTRACT_FROM_PARSE' -+ * @size: Size in bytes -+ * @offset: Byte offset -+ */ -+ struct { -+ uint8_t size; -+ uint8_t offset; -+ } from_parse; -+ } extract; -+ -+ uint8_t num_of_byte_masks; -+ struct dpkg_mask masks[DPKG_NUM_OF_MASKS]; -+}; -+ -+/** -+ * struct dpkg_profile_cfg - A structure for defining a full Key Generation -+ * profile (rule) -+ * @num_extracts: Defines the number of valid entries in the array below -+ * @extracts: Array of required extractions -+ */ -+struct dpkg_profile_cfg { -+ uint8_t num_extracts; -+ struct dpkg_extract extracts[DPKG_MAX_NUM_OF_EXTRACTS]; -+}; -+ -+#endif /* __FSL_DPKG_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpni-cmd.h -@@ -0,0 +1,1058 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef _FSL_DPNI_CMD_H -+#define _FSL_DPNI_CMD_H -+ -+/* DPNI Version */ -+#define DPNI_VER_MAJOR 6 -+#define DPNI_VER_MINOR 0 -+ -+/* Command IDs */ -+#define DPNI_CMDID_OPEN 0x801 -+#define DPNI_CMDID_CLOSE 0x800 -+#define DPNI_CMDID_CREATE 0x901 -+#define DPNI_CMDID_DESTROY 0x900 -+ -+#define DPNI_CMDID_ENABLE 0x002 -+#define DPNI_CMDID_DISABLE 0x003 -+#define DPNI_CMDID_GET_ATTR 0x004 -+#define DPNI_CMDID_RESET 0x005 -+#define DPNI_CMDID_IS_ENABLED 0x006 -+ -+#define DPNI_CMDID_SET_IRQ 0x010 -+#define DPNI_CMDID_GET_IRQ 0x011 -+#define DPNI_CMDID_SET_IRQ_ENABLE 0x012 -+#define DPNI_CMDID_GET_IRQ_ENABLE 0x013 -+#define DPNI_CMDID_SET_IRQ_MASK 0x014 -+#define DPNI_CMDID_GET_IRQ_MASK 0x015 -+#define DPNI_CMDID_GET_IRQ_STATUS 0x016 -+#define DPNI_CMDID_CLEAR_IRQ_STATUS 0x017 -+ -+#define DPNI_CMDID_SET_POOLS 0x200 -+#define DPNI_CMDID_GET_RX_BUFFER_LAYOUT 0x201 -+#define DPNI_CMDID_SET_RX_BUFFER_LAYOUT 0x202 -+#define DPNI_CMDID_GET_TX_BUFFER_LAYOUT 0x203 -+#define DPNI_CMDID_SET_TX_BUFFER_LAYOUT 0x204 -+#define DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT 0x205 -+#define DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT 0x206 -+#define DPNI_CMDID_SET_L3_CHKSUM_VALIDATION 0x207 -+#define DPNI_CMDID_GET_L3_CHKSUM_VALIDATION 0x208 -+#define DPNI_CMDID_SET_L4_CHKSUM_VALIDATION 0x209 -+#define DPNI_CMDID_GET_L4_CHKSUM_VALIDATION 0x20A -+#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B -+#define DPNI_CMDID_SET_TX_CONF_REVOKE 0x20C -+ -+#define DPNI_CMDID_GET_QDID 0x210 -+#define DPNI_CMDID_GET_SP_INFO 0x211 -+#define DPNI_CMDID_GET_TX_DATA_OFFSET 0x212 -+#define DPNI_CMDID_GET_COUNTER 0x213 -+#define DPNI_CMDID_SET_COUNTER 0x214 -+#define DPNI_CMDID_GET_LINK_STATE 0x215 -+#define DPNI_CMDID_SET_MAX_FRAME_LENGTH 0x216 -+#define DPNI_CMDID_GET_MAX_FRAME_LENGTH 0x217 -+#define DPNI_CMDID_SET_MTU 0x218 -+#define DPNI_CMDID_GET_MTU 0x219 -+#define DPNI_CMDID_SET_LINK_CFG 0x21A -+#define DPNI_CMDID_SET_TX_SHAPING 0x21B -+ -+#define DPNI_CMDID_SET_MCAST_PROMISC 0x220 -+#define DPNI_CMDID_GET_MCAST_PROMISC 0x221 -+#define DPNI_CMDID_SET_UNICAST_PROMISC 0x222 -+#define DPNI_CMDID_GET_UNICAST_PROMISC 0x223 -+#define DPNI_CMDID_SET_PRIM_MAC 0x224 -+#define DPNI_CMDID_GET_PRIM_MAC 0x225 -+#define DPNI_CMDID_ADD_MAC_ADDR 0x226 -+#define DPNI_CMDID_REMOVE_MAC_ADDR 0x227 -+#define DPNI_CMDID_CLR_MAC_FILTERS 0x228 -+ -+#define DPNI_CMDID_SET_VLAN_FILTERS 0x230 -+#define DPNI_CMDID_ADD_VLAN_ID 0x231 -+#define DPNI_CMDID_REMOVE_VLAN_ID 0x232 -+#define DPNI_CMDID_CLR_VLAN_FILTERS 0x233 -+ -+#define DPNI_CMDID_SET_RX_TC_DIST 0x235 -+#define DPNI_CMDID_SET_TX_FLOW 0x236 -+#define DPNI_CMDID_GET_TX_FLOW 0x237 -+#define DPNI_CMDID_SET_RX_FLOW 0x238 -+#define DPNI_CMDID_GET_RX_FLOW 0x239 -+#define DPNI_CMDID_SET_RX_ERR_QUEUE 0x23A -+#define DPNI_CMDID_GET_RX_ERR_QUEUE 0x23B -+ -+#define DPNI_CMDID_SET_RX_TC_POLICING 0x23E -+#define DPNI_CMDID_SET_RX_TC_EARLY_DROP 0x23F -+ -+#define DPNI_CMDID_SET_QOS_TBL 0x240 -+#define DPNI_CMDID_ADD_QOS_ENT 0x241 -+#define DPNI_CMDID_REMOVE_QOS_ENT 0x242 -+#define DPNI_CMDID_CLR_QOS_TBL 0x243 -+#define DPNI_CMDID_ADD_FS_ENT 0x244 -+#define DPNI_CMDID_REMOVE_FS_ENT 0x245 -+#define DPNI_CMDID_CLR_FS_ENT 0x246 -+#define DPNI_CMDID_SET_VLAN_INSERTION 0x247 -+#define DPNI_CMDID_SET_VLAN_REMOVAL 0x248 -+#define DPNI_CMDID_SET_IPR 0x249 -+#define DPNI_CMDID_SET_IPF 0x24A -+ -+#define DPNI_CMDID_SET_TX_SELECTION 0x250 -+#define DPNI_CMDID_GET_RX_TC_POLICING 0x251 -+#define DPNI_CMDID_GET_RX_TC_EARLY_DROP 0x252 -+#define DPNI_CMDID_SET_RX_TC_CONGESTION_NOTIFICATION 0x253 -+#define DPNI_CMDID_GET_RX_TC_CONGESTION_NOTIFICATION 0x254 -+#define DPNI_CMDID_SET_TX_TC_CONGESTION_NOTIFICATION 0x255 -+#define DPNI_CMDID_GET_TX_TC_CONGESTION_NOTIFICATION 0x256 -+#define DPNI_CMDID_SET_TX_CONF 0x257 -+#define DPNI_CMDID_GET_TX_CONF 0x258 -+#define DPNI_CMDID_SET_TX_CONF_CONGESTION_NOTIFICATION 0x259 -+#define DPNI_CMDID_GET_TX_CONF_CONGESTION_NOTIFICATION 0x25A -+#define DPNI_CMDID_SET_TX_TC_EARLY_DROP 0x25B -+#define DPNI_CMDID_GET_TX_TC_EARLY_DROP 0x25C -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_OPEN(cmd, dpni_id) \ -+ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id) -+ -+#define DPNI_PREP_EXTENDED_CFG(ext, cfg) \ -+do { \ -+ MC_PREP_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \ -+ MC_PREP_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \ -+ MC_PREP_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \ -+ MC_PREP_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \ -+ MC_PREP_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \ -+ MC_PREP_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \ -+ MC_PREP_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \ -+ MC_PREP_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \ -+ MC_PREP_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \ -+ MC_PREP_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \ -+ MC_PREP_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \ -+ MC_PREP_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \ -+ MC_PREP_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \ -+ MC_PREP_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \ -+ MC_PREP_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \ -+ MC_PREP_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \ -+ MC_PREP_OP(ext, 4, 0, 16, uint16_t, \ -+ cfg->ipr_cfg.max_open_frames_ipv4); \ -+ MC_PREP_OP(ext, 4, 16, 16, uint16_t, \ -+ cfg->ipr_cfg.max_open_frames_ipv6); \ -+ MC_PREP_OP(ext, 4, 32, 16, uint16_t, \ -+ cfg->ipr_cfg.max_reass_frm_size); \ -+ MC_PREP_OP(ext, 5, 0, 16, uint16_t, \ -+ cfg->ipr_cfg.min_frag_size_ipv4); \ -+ MC_PREP_OP(ext, 5, 16, 16, uint16_t, \ -+ cfg->ipr_cfg.min_frag_size_ipv6); \ -+} while (0) -+ -+#define DPNI_EXT_EXTENDED_CFG(ext, cfg) \ -+do { \ -+ MC_EXT_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \ -+ MC_EXT_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \ -+ MC_EXT_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \ -+ MC_EXT_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \ -+ MC_EXT_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \ -+ MC_EXT_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \ -+ MC_EXT_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \ -+ MC_EXT_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \ -+ MC_EXT_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \ -+ MC_EXT_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \ -+ MC_EXT_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \ -+ MC_EXT_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \ -+ MC_EXT_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \ -+ MC_EXT_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \ -+ MC_EXT_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \ -+ MC_EXT_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \ -+ MC_EXT_OP(ext, 4, 0, 16, uint16_t, \ -+ cfg->ipr_cfg.max_open_frames_ipv4); \ -+ MC_EXT_OP(ext, 4, 16, 16, uint16_t, \ -+ cfg->ipr_cfg.max_open_frames_ipv6); \ -+ MC_EXT_OP(ext, 4, 32, 16, uint16_t, \ -+ cfg->ipr_cfg.max_reass_frm_size); \ -+ MC_EXT_OP(ext, 5, 0, 16, uint16_t, \ -+ cfg->ipr_cfg.min_frag_size_ipv4); \ -+ MC_EXT_OP(ext, 5, 16, 16, uint16_t, \ -+ cfg->ipr_cfg.min_frag_size_ipv6); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_CREATE(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->adv.max_tcs); \ -+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->adv.max_senders); \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]); \ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]); \ -+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]); \ -+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]); \ -+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]); \ -+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->adv.options); \ -+ MC_CMD_OP(cmd, 2, 0, 8, uint8_t, cfg->adv.max_unicast_filters); \ -+ MC_CMD_OP(cmd, 2, 8, 8, uint8_t, cfg->adv.max_multicast_filters); \ -+ MC_CMD_OP(cmd, 2, 16, 8, uint8_t, cfg->adv.max_vlan_filters); \ -+ MC_CMD_OP(cmd, 2, 24, 8, uint8_t, cfg->adv.max_qos_entries); \ -+ MC_CMD_OP(cmd, 2, 32, 8, uint8_t, cfg->adv.max_qos_key_size); \ -+ MC_CMD_OP(cmd, 2, 48, 8, uint8_t, cfg->adv.max_dist_key_size); \ -+ MC_CMD_OP(cmd, 2, 56, 8, enum net_prot, cfg->adv.start_hdr); \ -+ MC_CMD_OP(cmd, 4, 48, 8, uint8_t, cfg->adv.max_policers); \ -+ MC_CMD_OP(cmd, 4, 56, 8, uint8_t, cfg->adv.max_congestion_ctrl); \ -+ MC_CMD_OP(cmd, 5, 0, 64, uint64_t, cfg->adv.ext_cfg_iova); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_POOLS(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \ -+ MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \ -+ MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\ -+ MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \ -+ MC_CMD_OP(cmd, 4, 48, 16, uint16_t, cfg->pools[1].buffer_size);\ -+ MC_CMD_OP(cmd, 1, 32, 32, int, cfg->pools[2].dpbp_id); \ -+ MC_CMD_OP(cmd, 5, 0, 16, uint16_t, cfg->pools[2].buffer_size);\ -+ MC_CMD_OP(cmd, 2, 0, 32, int, cfg->pools[3].dpbp_id); \ -+ MC_CMD_OP(cmd, 5, 16, 16, uint16_t, cfg->pools[3].buffer_size);\ -+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->pools[4].dpbp_id); \ -+ MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->pools[4].buffer_size);\ -+ MC_CMD_OP(cmd, 3, 0, 32, int, cfg->pools[5].dpbp_id); \ -+ MC_CMD_OP(cmd, 5, 48, 16, uint16_t, cfg->pools[5].buffer_size);\ -+ MC_CMD_OP(cmd, 3, 32, 32, int, cfg->pools[6].dpbp_id); \ -+ MC_CMD_OP(cmd, 6, 0, 16, uint16_t, cfg->pools[6].buffer_size);\ -+ MC_CMD_OP(cmd, 4, 0, 32, int, cfg->pools[7].dpbp_id); \ -+ MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_IS_ENABLED(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \ -+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_GET_IRQ(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_IRQ(cmd, type, irq_cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \ -+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \ -+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_GET_IRQ_ENABLE(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_IRQ_ENABLE(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_GET_IRQ_MASK(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_IRQ_MASK(cmd, mask) \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_IRQ_STATUS(cmd, status) \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_GET_ATTR(cmd, attr) \ -+ MC_CMD_OP(cmd, 6, 0, 64, uint64_t, attr->ext_cfg_iova) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_ATTR(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ -+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->max_tcs); \ -+ MC_RSP_OP(cmd, 0, 40, 8, uint8_t, attr->max_senders); \ -+ MC_RSP_OP(cmd, 0, 48, 8, enum net_prot, attr->start_hdr); \ -+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options); \ -+ MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->max_unicast_filters); \ -+ MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->max_multicast_filters);\ -+ MC_RSP_OP(cmd, 2, 16, 8, uint8_t, attr->max_vlan_filters); \ -+ MC_RSP_OP(cmd, 2, 24, 8, uint8_t, attr->max_qos_entries); \ -+ MC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->max_qos_key_size); \ -+ MC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->max_dist_key_size); \ -+ MC_RSP_OP(cmd, 4, 48, 8, uint8_t, attr->max_policers); \ -+ MC_RSP_OP(cmd, 4, 56, 8, uint8_t, attr->max_congestion_ctrl); \ -+ MC_RSP_OP(cmd, 5, 32, 16, uint16_t, attr->version.major);\ -+ MC_RSP_OP(cmd, 5, 48, 16, uint16_t, attr->version.minor);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->errors); \ -+ MC_CMD_OP(cmd, 0, 32, 4, enum dpni_error_action, cfg->error_action); \ -+ MC_CMD_OP(cmd, 0, 36, 1, int, cfg->set_frame_annotation); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ -+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ -+ MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ -+ MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ -+ MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ -+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ -+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_RX_BUFFER_LAYOUT(cmd, layout) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ -+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \ -+ MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ -+ MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ -+ MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ -+ MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ -+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_TX_BUFFER_LAYOUT(cmd, layout) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ -+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ -+ MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ -+ MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ -+ MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ -+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ -+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_TX_BUFFER_LAYOUT(cmd, layout) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ -+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \ -+ MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ -+ MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ -+ MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ -+ MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ -+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_TX_CONF_BUFFER_LAYOUT(cmd, layout) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ -+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ -+ MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ -+ MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ -+ MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ -+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ -+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_TX_CONF_BUFFER_LAYOUT(cmd, layout) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ -+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \ -+ MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ -+ MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ -+ MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ -+ MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ -+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_L3_CHKSUM_VALIDATION(cmd, en) \ -+ MC_CMD_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_L3_CHKSUM_VALIDATION(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_L4_CHKSUM_VALIDATION(cmd, en) \ -+ MC_CMD_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_L4_CHKSUM_VALIDATION(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_QDID(cmd, qdid) \ -+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, qdid) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_SP_INFO(cmd, sp_info) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, sp_info->spids[0]); \ -+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, sp_info->spids[1]); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_TX_DATA_OFFSET(cmd, data_offset) \ -+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, data_offset) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_GET_COUNTER(cmd, counter) \ -+ MC_CMD_OP(cmd, 0, 0, 16, enum dpni_counter, counter) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_COUNTER(cmd, value) \ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, value) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_COUNTER(cmd, counter, value) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, enum dpni_counter, counter); \ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, value); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_LINK_CFG(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate);\ -+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_LINK_STATE(cmd, state) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 32, 1, int, state->up);\ -+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, state->rate);\ -+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_TX_SHAPING(cmd, tx_shaper) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, tx_shaper->max_burst_size);\ -+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, tx_shaper->rate_limit);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_MAX_FRAME_LENGTH(cmd, max_frame_length) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, max_frame_length) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_MAX_FRAME_LENGTH(cmd, max_frame_length) \ -+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, max_frame_length) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_MTU(cmd, mtu) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, mtu) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_MTU(cmd, mtu) \ -+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, mtu) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_MULTICAST_PROMISC(cmd, en) \ -+ MC_CMD_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_MULTICAST_PROMISC(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_UNICAST_PROMISC(cmd, en) \ -+ MC_CMD_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_UNICAST_PROMISC(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ -+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ -+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ -+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ -+ MC_RSP_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ -+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ -+ MC_RSP_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ -+ MC_RSP_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ -+ MC_RSP_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ -+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ -+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ -+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ -+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ -+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ -+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_CLEAR_MAC_FILTERS(cmd, unicast, multicast) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 1, int, unicast); \ -+ MC_CMD_OP(cmd, 0, 1, 1, int, multicast); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_VLAN_FILTERS(cmd, en) \ -+ MC_CMD_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_ADD_VLAN_ID(cmd, vlan_id) \ -+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, vlan_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_REMOVE_VLAN_ID(cmd, vlan_id) \ -+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, vlan_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_TX_SELECTION(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->tc_sched[0].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 0, 16, 4, enum dpni_tx_schedule_mode, \ -+ cfg->tc_sched[0].mode); \ -+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->tc_sched[1].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 0, 48, 4, enum dpni_tx_schedule_mode, \ -+ cfg->tc_sched[1].mode); \ -+ MC_CMD_OP(cmd, 1, 0, 16, uint16_t, cfg->tc_sched[2].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 1, 16, 4, enum dpni_tx_schedule_mode, \ -+ cfg->tc_sched[2].mode); \ -+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, cfg->tc_sched[3].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 1, 48, 4, enum dpni_tx_schedule_mode, \ -+ cfg->tc_sched[3].mode); \ -+ MC_CMD_OP(cmd, 2, 0, 16, uint16_t, cfg->tc_sched[4].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 2, 16, 4, enum dpni_tx_schedule_mode, \ -+ cfg->tc_sched[4].mode); \ -+ MC_CMD_OP(cmd, 2, 32, 16, uint16_t, cfg->tc_sched[5].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 2, 48, 4, enum dpni_tx_schedule_mode, \ -+ cfg->tc_sched[5].mode); \ -+ MC_CMD_OP(cmd, 3, 0, 16, uint16_t, cfg->tc_sched[6].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 3, 16, 4, enum dpni_tx_schedule_mode, \ -+ cfg->tc_sched[6].mode); \ -+ MC_CMD_OP(cmd, 3, 32, 16, uint16_t, cfg->tc_sched[7].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 3, 48, 4, enum dpni_tx_schedule_mode, \ -+ cfg->tc_sched[7].mode); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_RX_TC_DIST(cmd, tc_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->dist_size); \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 0, 24, 4, enum dpni_dist_mode, cfg->dist_mode); \ -+ MC_CMD_OP(cmd, 0, 28, 4, enum dpni_fs_miss_action, \ -+ cfg->fs_cfg.miss_action); \ -+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, cfg->fs_cfg.default_flow_id); \ -+ MC_CMD_OP(cmd, 6, 0, 64, uint64_t, cfg->key_cfg_iova); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_TX_FLOW(cmd, flow_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 43, 1, int, cfg->l3_chksum_gen);\ -+ MC_CMD_OP(cmd, 0, 44, 1, int, cfg->l4_chksum_gen);\ -+ MC_CMD_OP(cmd, 0, 45, 1, int, cfg->use_common_tx_conf_queue);\ -+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id);\ -+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_SET_TX_FLOW(cmd, flow_id) \ -+ MC_RSP_OP(cmd, 0, 48, 16, uint16_t, flow_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_GET_TX_FLOW(cmd, flow_id) \ -+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_TX_FLOW(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 43, 1, int, attr->l3_chksum_gen);\ -+ MC_RSP_OP(cmd, 0, 44, 1, int, attr->l4_chksum_gen);\ -+ MC_RSP_OP(cmd, 0, 45, 1, int, attr->use_common_tx_conf_queue);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_RX_FLOW(cmd, tc_id, flow_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority);\ -+ MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, cfg->dest_cfg.dest_type);\ -+ MC_CMD_OP(cmd, 0, 42, 1, int, cfg->order_preservation_en);\ -+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \ -+ MC_CMD_OP(cmd, 2, 16, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \ -+ MC_CMD_OP(cmd, 3, 0, 4, enum dpni_flc_type, cfg->flc_cfg.flc_type); \ -+ MC_CMD_OP(cmd, 3, 4, 4, enum dpni_stash_size, \ -+ cfg->flc_cfg.frame_data_size);\ -+ MC_CMD_OP(cmd, 3, 8, 4, enum dpni_stash_size, \ -+ cfg->flc_cfg.flow_context_size);\ -+ MC_CMD_OP(cmd, 3, 32, 32, uint32_t, cfg->flc_cfg.options);\ -+ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->flc_cfg.flow_context);\ -+ MC_CMD_OP(cmd, 5, 0, 32, uint32_t, cfg->tail_drop_threshold); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_GET_RX_FLOW(cmd, tc_id, flow_id) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_RX_FLOW(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id); \ -+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\ -+ MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, attr->dest_cfg.dest_type); \ -+ MC_RSP_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx); \ -+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->tail_drop_threshold); \ -+ MC_RSP_OP(cmd, 2, 32, 32, uint32_t, attr->fqid); \ -+ MC_RSP_OP(cmd, 3, 0, 4, enum dpni_flc_type, attr->flc_cfg.flc_type); \ -+ MC_RSP_OP(cmd, 3, 4, 4, enum dpni_stash_size, \ -+ attr->flc_cfg.frame_data_size);\ -+ MC_RSP_OP(cmd, 3, 8, 4, enum dpni_stash_size, \ -+ attr->flc_cfg.flow_context_size);\ -+ MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->flc_cfg.options);\ -+ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, attr->flc_cfg.flow_context);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_RX_ERR_QUEUE(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority);\ -+ MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, cfg->dest_cfg.dest_type);\ -+ MC_CMD_OP(cmd, 0, 42, 1, int, cfg->order_preservation_en);\ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \ -+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options); \ -+ MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->tail_drop_threshold); \ -+ MC_CMD_OP(cmd, 3, 0, 4, enum dpni_flc_type, cfg->flc_cfg.flc_type); \ -+ MC_CMD_OP(cmd, 3, 4, 4, enum dpni_stash_size, \ -+ cfg->flc_cfg.frame_data_size);\ -+ MC_CMD_OP(cmd, 3, 8, 4, enum dpni_stash_size, \ -+ cfg->flc_cfg.flow_context_size);\ -+ MC_CMD_OP(cmd, 3, 32, 32, uint32_t, cfg->flc_cfg.options);\ -+ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->flc_cfg.flow_context);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_RX_ERR_QUEUE(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id); \ -+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\ -+ MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, attr->dest_cfg.dest_type);\ -+ MC_RSP_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx); \ -+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->tail_drop_threshold); \ -+ MC_RSP_OP(cmd, 2, 32, 32, uint32_t, attr->fqid); \ -+ MC_RSP_OP(cmd, 3, 0, 4, enum dpni_flc_type, attr->flc_cfg.flc_type); \ -+ MC_RSP_OP(cmd, 3, 4, 4, enum dpni_stash_size, \ -+ attr->flc_cfg.frame_data_size);\ -+ MC_RSP_OP(cmd, 3, 8, 4, enum dpni_stash_size, \ -+ attr->flc_cfg.flow_context_size);\ -+ MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->flc_cfg.options);\ -+ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, attr->flc_cfg.flow_context);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_TX_CONF_REVOKE(cmd, revoke) \ -+ MC_CMD_OP(cmd, 0, 0, 1, int, revoke) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_QOS_TABLE(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->default_tc); \ -+ MC_CMD_OP(cmd, 0, 40, 1, int, cfg->discard_on_miss); \ -+ MC_CMD_OP(cmd, 6, 0, 64, uint64_t, cfg->key_cfg_iova); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_ADD_QOS_ENTRY(cmd, cfg, tc_id) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->key_size); \ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->key_iova); \ -+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->mask_iova); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_REMOVE_QOS_ENTRY(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->key_size); \ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->key_iova); \ -+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->mask_iova); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_ADD_FS_ENTRY(cmd, tc_id, cfg, flow_id) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->key_size); \ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->key_iova); \ -+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->mask_iova); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_REMOVE_FS_ENTRY(cmd, tc_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->key_size); \ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->key_iova); \ -+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->mask_iova); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_CLEAR_FS_ENTRIES(cmd, tc_id) \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_VLAN_INSERTION(cmd, en) \ -+ MC_CMD_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_VLAN_REMOVAL(cmd, en) \ -+ MC_CMD_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_IPR(cmd, en) \ -+ MC_CMD_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_IPF(cmd, en) \ -+ MC_CMD_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_RX_TC_POLICING(cmd, tc_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 4, enum dpni_policer_mode, cfg->mode); \ -+ MC_CMD_OP(cmd, 0, 4, 4, enum dpni_policer_color, cfg->default_color); \ -+ MC_CMD_OP(cmd, 0, 8, 4, enum dpni_policer_unit, cfg->units); \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, cfg->options); \ -+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->cir); \ -+ MC_CMD_OP(cmd, 1, 32, 32, uint32_t, cfg->cbs); \ -+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->eir); \ -+ MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->ebs);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_GET_RX_TC_POLICING(cmd, tc_id) \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_RSP_GET_RX_TC_POLICING(cmd, cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 4, enum dpni_policer_mode, cfg->mode); \ -+ MC_RSP_OP(cmd, 0, 4, 4, enum dpni_policer_color, cfg->default_color); \ -+ MC_RSP_OP(cmd, 0, 8, 4, enum dpni_policer_unit, cfg->units); \ -+ MC_RSP_OP(cmd, 0, 32, 32, uint32_t, cfg->options); \ -+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->cir); \ -+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, cfg->cbs); \ -+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, cfg->eir); \ -+ MC_RSP_OP(cmd, 2, 32, 32, uint32_t, cfg->ebs);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_PREP_EARLY_DROP(ext, cfg) \ -+do { \ -+ MC_PREP_OP(ext, 0, 0, 2, enum dpni_early_drop_mode, cfg->mode); \ -+ MC_PREP_OP(ext, 0, 2, 2, \ -+ enum dpni_congestion_unit, cfg->units); \ -+ MC_PREP_OP(ext, 0, 32, 32, uint32_t, cfg->tail_drop_threshold); \ -+ MC_PREP_OP(ext, 1, 0, 8, uint8_t, cfg->green.drop_probability); \ -+ MC_PREP_OP(ext, 2, 0, 64, uint64_t, cfg->green.max_threshold); \ -+ MC_PREP_OP(ext, 3, 0, 64, uint64_t, cfg->green.min_threshold); \ -+ MC_PREP_OP(ext, 5, 0, 8, uint8_t, cfg->yellow.drop_probability);\ -+ MC_PREP_OP(ext, 6, 0, 64, uint64_t, cfg->yellow.max_threshold); \ -+ MC_PREP_OP(ext, 7, 0, 64, uint64_t, cfg->yellow.min_threshold); \ -+ MC_PREP_OP(ext, 9, 0, 8, uint8_t, cfg->red.drop_probability); \ -+ MC_PREP_OP(ext, 10, 0, 64, uint64_t, cfg->red.max_threshold); \ -+ MC_PREP_OP(ext, 11, 0, 64, uint64_t, cfg->red.min_threshold); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_EXT_EARLY_DROP(ext, cfg) \ -+do { \ -+ MC_EXT_OP(ext, 0, 0, 2, enum dpni_early_drop_mode, cfg->mode); \ -+ MC_EXT_OP(ext, 0, 2, 2, \ -+ enum dpni_congestion_unit, cfg->units); \ -+ MC_EXT_OP(ext, 0, 32, 32, uint32_t, cfg->tail_drop_threshold); \ -+ MC_EXT_OP(ext, 1, 0, 8, uint8_t, cfg->green.drop_probability); \ -+ MC_EXT_OP(ext, 2, 0, 64, uint64_t, cfg->green.max_threshold); \ -+ MC_EXT_OP(ext, 3, 0, 64, uint64_t, cfg->green.min_threshold); \ -+ MC_EXT_OP(ext, 5, 0, 8, uint8_t, cfg->yellow.drop_probability);\ -+ MC_EXT_OP(ext, 6, 0, 64, uint64_t, cfg->yellow.max_threshold); \ -+ MC_EXT_OP(ext, 7, 0, 64, uint64_t, cfg->yellow.min_threshold); \ -+ MC_EXT_OP(ext, 9, 0, 8, uint8_t, cfg->red.drop_probability); \ -+ MC_EXT_OP(ext, 10, 0, 64, uint64_t, cfg->red.max_threshold); \ -+ MC_EXT_OP(ext, 11, 0, 64, uint64_t, cfg->red.min_threshold); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_RX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, early_drop_iova); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_GET_RX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, early_drop_iova); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_SET_TX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, early_drop_iova); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPNI_CMD_GET_TX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, early_drop_iova); \ -+} while (0) -+ -+#define DPNI_CMD_SET_RX_TC_CONGESTION_NOTIFICATION(cmd, tc_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 2, enum dpni_congestion_unit, cfg->units); \ -+ MC_CMD_OP(cmd, 0, 4, 4, enum dpni_dest, cfg->dest_cfg.dest_type); \ -+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->dest_cfg.priority); \ -+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->threshold_entry); \ -+ MC_CMD_OP(cmd, 1, 32, 32, uint32_t, cfg->threshold_exit); \ -+ MC_CMD_OP(cmd, 2, 0, 16, uint16_t, cfg->options); \ -+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->dest_cfg.dest_id); \ -+ MC_CMD_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx); \ -+ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova); \ -+} while (0) -+ -+#define DPNI_CMD_GET_RX_TC_CONGESTION_NOTIFICATION(cmd, tc_id) \ -+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id) -+ -+#define DPNI_RSP_GET_RX_TC_CONGESTION_NOTIFICATION(cmd, cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 2, enum dpni_congestion_unit, cfg->units); \ -+ MC_RSP_OP(cmd, 0, 4, 4, enum dpni_dest, cfg->dest_cfg.dest_type); \ -+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, cfg->dest_cfg.priority); \ -+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->threshold_entry); \ -+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, cfg->threshold_exit); \ -+ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, cfg->options); \ -+ MC_RSP_OP(cmd, 2, 32, 32, int, cfg->dest_cfg.dest_id); \ -+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx); \ -+ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova); \ -+} while (0) -+ -+#define DPNI_CMD_SET_TX_TC_CONGESTION_NOTIFICATION(cmd, tc_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 2, enum dpni_congestion_unit, cfg->units); \ -+ MC_CMD_OP(cmd, 0, 4, 4, enum dpni_dest, cfg->dest_cfg.dest_type); \ -+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->dest_cfg.priority); \ -+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->threshold_entry); \ -+ MC_CMD_OP(cmd, 1, 32, 32, uint32_t, cfg->threshold_exit); \ -+ MC_CMD_OP(cmd, 2, 0, 16, uint16_t, cfg->options); \ -+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->dest_cfg.dest_id); \ -+ MC_CMD_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx); \ -+ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova); \ -+} while (0) -+ -+#define DPNI_CMD_GET_TX_TC_CONGESTION_NOTIFICATION(cmd, tc_id) \ -+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id) -+ -+#define DPNI_RSP_GET_TX_TC_CONGESTION_NOTIFICATION(cmd, cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 2, enum dpni_congestion_unit, cfg->units); \ -+ MC_RSP_OP(cmd, 0, 4, 4, enum dpni_dest, cfg->dest_cfg.dest_type); \ -+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, cfg->dest_cfg.priority); \ -+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->threshold_entry); \ -+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, cfg->threshold_exit); \ -+ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, cfg->options); \ -+ MC_RSP_OP(cmd, 2, 32, 32, int, cfg->dest_cfg.dest_id); \ -+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx); \ -+ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova); \ -+} while (0) -+ -+#define DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->queue_cfg.dest_cfg.priority); \ -+ MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \ -+ cfg->queue_cfg.dest_cfg.dest_type); \ -+ MC_CMD_OP(cmd, 0, 42, 1, int, cfg->errors_only); \ -+ MC_CMD_OP(cmd, 0, 46, 1, int, cfg->queue_cfg.order_preservation_en); \ -+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->queue_cfg.user_ctx); \ -+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->queue_cfg.options); \ -+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->queue_cfg.dest_cfg.dest_id); \ -+ MC_CMD_OP(cmd, 3, 0, 32, uint32_t, \ -+ cfg->queue_cfg.tail_drop_threshold); \ -+ MC_CMD_OP(cmd, 4, 0, 4, enum dpni_flc_type, \ -+ cfg->queue_cfg.flc_cfg.flc_type); \ -+ MC_CMD_OP(cmd, 4, 4, 4, enum dpni_stash_size, \ -+ cfg->queue_cfg.flc_cfg.frame_data_size); \ -+ MC_CMD_OP(cmd, 4, 8, 4, enum dpni_stash_size, \ -+ cfg->queue_cfg.flc_cfg.flow_context_size); \ -+ MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->queue_cfg.flc_cfg.options); \ -+ MC_CMD_OP(cmd, 5, 0, 64, uint64_t, \ -+ cfg->queue_cfg.flc_cfg.flow_context); \ -+} while (0) -+ -+#define DPNI_CMD_GET_TX_CONF(cmd, flow_id) \ -+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id) -+ -+#define DPNI_RSP_GET_TX_CONF(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \ -+ attr->queue_attr.dest_cfg.priority); \ -+ MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \ -+ attr->queue_attr.dest_cfg.dest_type); \ -+ MC_RSP_OP(cmd, 0, 42, 1, int, attr->errors_only); \ -+ MC_RSP_OP(cmd, 0, 46, 1, int, \ -+ attr->queue_attr.order_preservation_en); \ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->queue_attr.user_ctx); \ -+ MC_RSP_OP(cmd, 2, 32, 32, int, attr->queue_attr.dest_cfg.dest_id); \ -+ MC_RSP_OP(cmd, 3, 0, 32, uint32_t, \ -+ attr->queue_attr.tail_drop_threshold); \ -+ MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->queue_attr.fqid); \ -+ MC_RSP_OP(cmd, 4, 0, 4, enum dpni_flc_type, \ -+ attr->queue_attr.flc_cfg.flc_type); \ -+ MC_RSP_OP(cmd, 4, 4, 4, enum dpni_stash_size, \ -+ attr->queue_attr.flc_cfg.frame_data_size); \ -+ MC_RSP_OP(cmd, 4, 8, 4, enum dpni_stash_size, \ -+ attr->queue_attr.flc_cfg.flow_context_size); \ -+ MC_RSP_OP(cmd, 4, 32, 32, uint32_t, attr->queue_attr.flc_cfg.options); \ -+ MC_RSP_OP(cmd, 5, 0, 64, uint64_t, \ -+ attr->queue_attr.flc_cfg.flow_context); \ -+} while (0) -+ -+#define DPNI_CMD_SET_TX_CONF_CONGESTION_NOTIFICATION(cmd, flow_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 2, enum dpni_congestion_unit, cfg->units); \ -+ MC_CMD_OP(cmd, 0, 4, 4, enum dpni_dest, cfg->dest_cfg.dest_type); \ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->dest_cfg.priority); \ -+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ -+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->threshold_entry); \ -+ MC_CMD_OP(cmd, 1, 32, 32, uint32_t, cfg->threshold_exit); \ -+ MC_CMD_OP(cmd, 2, 0, 16, uint16_t, cfg->options); \ -+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->dest_cfg.dest_id); \ -+ MC_CMD_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx); \ -+ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova); \ -+} while (0) -+ -+#define DPNI_CMD_GET_TX_CONF_CONGESTION_NOTIFICATION(cmd, flow_id) \ -+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id) -+ -+#define DPNI_RSP_GET_TX_CONF_CONGESTION_NOTIFICATION(cmd, cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 2, enum dpni_congestion_unit, cfg->units); \ -+ MC_RSP_OP(cmd, 0, 4, 4, enum dpni_dest, cfg->dest_cfg.dest_type); \ -+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, cfg->dest_cfg.priority); \ -+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->threshold_entry); \ -+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, cfg->threshold_exit); \ -+ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, cfg->options); \ -+ MC_RSP_OP(cmd, 2, 32, 32, int, cfg->dest_cfg.dest_id); \ -+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, cfg->message_ctx); \ -+ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, cfg->message_iova); \ -+} while (0) -+ -+#endif /* _FSL_DPNI_CMD_H */ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpni.c -@@ -0,0 +1,1907 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include "../../fsl-mc/include/mc-sys.h" -+#include "../../fsl-mc/include/mc-cmd.h" -+#include "dpni.h" -+#include "dpni-cmd.h" -+ -+int dpni_prepare_key_cfg(const struct dpkg_profile_cfg *cfg, -+ uint8_t *key_cfg_buf) -+{ -+ int i, j; -+ int offset = 0; -+ int param = 1; -+ uint64_t *params = (uint64_t *)key_cfg_buf; -+ -+ if (!key_cfg_buf || !cfg) -+ return -EINVAL; -+ -+ params[0] |= mc_enc(0, 8, cfg->num_extracts); -+ params[0] = cpu_to_le64(params[0]); -+ -+ if (cfg->num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS) -+ return -EINVAL; -+ -+ for (i = 0; i < cfg->num_extracts; i++) { -+ switch (cfg->extracts[i].type) { -+ case DPKG_EXTRACT_FROM_HDR: -+ params[param] |= mc_enc(0, 8, -+ cfg->extracts[i].extract.from_hdr.prot); -+ params[param] |= mc_enc(8, 4, -+ cfg->extracts[i].extract.from_hdr.type); -+ params[param] |= mc_enc(16, 8, -+ cfg->extracts[i].extract.from_hdr.size); -+ params[param] |= mc_enc(24, 8, -+ cfg->extracts[i].extract. -+ from_hdr.offset); -+ params[param] |= mc_enc(32, 32, -+ cfg->extracts[i].extract. -+ from_hdr.field); -+ params[param] = cpu_to_le64(params[param]); -+ param++; -+ params[param] |= mc_enc(0, 8, -+ cfg->extracts[i].extract. -+ from_hdr.hdr_index); -+ break; -+ case DPKG_EXTRACT_FROM_DATA: -+ params[param] |= mc_enc(16, 8, -+ cfg->extracts[i].extract. -+ from_data.size); -+ params[param] |= mc_enc(24, 8, -+ cfg->extracts[i].extract. -+ from_data.offset); -+ params[param] = cpu_to_le64(params[param]); -+ param++; -+ break; -+ case DPKG_EXTRACT_FROM_PARSE: -+ params[param] |= mc_enc(16, 8, -+ cfg->extracts[i].extract. -+ from_parse.size); -+ params[param] |= mc_enc(24, 8, -+ cfg->extracts[i].extract. -+ from_parse.offset); -+ params[param] = cpu_to_le64(params[param]); -+ param++; -+ break; -+ default: -+ return -EINVAL; -+ } -+ params[param] |= mc_enc( -+ 24, 8, cfg->extracts[i].num_of_byte_masks); -+ params[param] |= mc_enc(32, 4, cfg->extracts[i].type); -+ params[param] = cpu_to_le64(params[param]); -+ param++; -+ for (offset = 0, j = 0; -+ j < DPKG_NUM_OF_MASKS; -+ offset += 16, j++) { -+ params[param] |= mc_enc( -+ (offset), 8, cfg->extracts[i].masks[j].mask); -+ params[param] |= mc_enc( -+ (offset + 8), 8, -+ cfg->extracts[i].masks[j].offset); -+ } -+ params[param] = cpu_to_le64(params[param]); -+ param++; -+ } -+ return 0; -+} -+ -+int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg, -+ uint8_t *ext_cfg_buf) -+{ -+ uint64_t *ext_params = (uint64_t *)ext_cfg_buf; -+ -+ DPNI_PREP_EXTENDED_CFG(ext_params, cfg); -+ -+ return 0; -+} -+ -+int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg, -+ const uint8_t *ext_cfg_buf) -+{ -+ uint64_t *ext_params = (uint64_t *)ext_cfg_buf; -+ -+ DPNI_EXT_EXTENDED_CFG(ext_params, cfg); -+ -+ return 0; -+} -+ -+int dpni_open(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ int dpni_id, -+ uint16_t *token) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_OPEN, -+ cmd_flags, -+ 0); -+ DPNI_CMD_OPEN(cmd, dpni_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header); -+ -+ return 0; -+} -+ -+int dpni_close(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLOSE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_create(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ const struct dpni_cfg *cfg, -+ uint16_t *token) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CREATE, -+ cmd_flags, -+ 0); -+ DPNI_CMD_CREATE(cmd, cfg); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header); -+ -+ return 0; -+} -+ -+int dpni_destroy(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_DESTROY, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_pools(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_pools_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_POOLS, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_POOLS(cmd, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ENABLE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_DISABLE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_is_enabled(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_IS_ENABLED, cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_IS_ENABLED(cmd, *en); -+ -+ return 0; -+} -+ -+int dpni_reset(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ struct dpni_irq_cfg *irq_cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IRQ, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_IRQ(cmd, irq_index, irq_cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ int *type, -+ struct dpni_irq_cfg *irq_cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_IRQ(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_IRQ(cmd, *type, irq_cfg); -+ -+ return 0; -+} -+ -+int dpni_set_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_IRQ_ENABLE(cmd, irq_index, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_IRQ_ENABLE(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_IRQ_ENABLE(cmd, *en); -+ -+ return 0; -+} -+ -+int dpni_set_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t mask) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IRQ_MASK, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_IRQ_MASK(cmd, irq_index, mask); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *mask) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_MASK, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_IRQ_MASK(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_IRQ_MASK(cmd, *mask); -+ -+ return 0; -+} -+ -+int dpni_get_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *status) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_STATUS, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_IRQ_STATUS(cmd, irq_index, *status); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_IRQ_STATUS(cmd, *status); -+ -+ return 0; -+} -+ -+int dpni_clear_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t status) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLEAR_IRQ_STATUS, -+ cmd_flags, -+ token); -+ DPNI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_ATTR(cmd, attr); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_ATTR(cmd, attr); -+ -+ return 0; -+} -+ -+int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_error_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_ERRORS_BEHAVIOR, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_buffer_layout *layout) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_BUFFER_LAYOUT, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout); -+ -+ return 0; -+} -+ -+int dpni_set_rx_buffer_layout(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_buffer_layout *layout) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_BUFFER_LAYOUT, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_RX_BUFFER_LAYOUT(cmd, layout); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_tx_buffer_layout(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_buffer_layout *layout) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_BUFFER_LAYOUT, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_TX_BUFFER_LAYOUT(cmd, layout); -+ -+ return 0; -+} -+ -+int dpni_set_tx_buffer_layout(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_buffer_layout *layout) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_BUFFER_LAYOUT, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_TX_BUFFER_LAYOUT(cmd, layout); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_tx_conf_buffer_layout(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_buffer_layout *layout) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_TX_CONF_BUFFER_LAYOUT(cmd, layout); -+ -+ return 0; -+} -+ -+int dpni_set_tx_conf_buffer_layout(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_buffer_layout *layout) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_TX_CONF_BUFFER_LAYOUT(cmd, layout); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_l3_chksum_validation(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_L3_CHKSUM_VALIDATION, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_L3_CHKSUM_VALIDATION(cmd, *en); -+ -+ return 0; -+} -+ -+int dpni_set_l3_chksum_validation(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_L3_CHKSUM_VALIDATION, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_L3_CHKSUM_VALIDATION(cmd, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_l4_chksum_validation(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_L4_CHKSUM_VALIDATION, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_L4_CHKSUM_VALIDATION(cmd, *en); -+ -+ return 0; -+} -+ -+int dpni_set_l4_chksum_validation(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_L4_CHKSUM_VALIDATION, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_L4_CHKSUM_VALIDATION(cmd, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_qdid(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *qdid) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QDID, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_QDID(cmd, *qdid); -+ -+ return 0; -+} -+ -+int dpni_get_sp_info(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_sp_info *sp_info) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_SP_INFO, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_SP_INFO(cmd, sp_info); -+ -+ return 0; -+} -+ -+int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *data_offset) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_DATA_OFFSET, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_TX_DATA_OFFSET(cmd, *data_offset); -+ -+ return 0; -+} -+ -+int dpni_get_counter(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ enum dpni_counter counter, -+ uint64_t *value) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_COUNTER, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_COUNTER(cmd, counter); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_COUNTER(cmd, *value); -+ -+ return 0; -+} -+ -+int dpni_set_counter(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ enum dpni_counter counter, -+ uint64_t value) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_COUNTER, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_COUNTER(cmd, counter, value); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_link_cfg(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_link_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_LINK_CFG, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_LINK_CFG(cmd, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_link_state(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_link_state *state) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_LINK_STATE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_LINK_STATE(cmd, state); -+ -+ return 0; -+} -+ -+int dpni_set_tx_shaping(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_tx_shaping_cfg *tx_shaper) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_SHAPING, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_TX_SHAPING(cmd, tx_shaper); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_max_frame_length(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t max_frame_length) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_MAX_FRAME_LENGTH, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_MAX_FRAME_LENGTH(cmd, max_frame_length); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_max_frame_length(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *max_frame_length) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_MAX_FRAME_LENGTH, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_MAX_FRAME_LENGTH(cmd, *max_frame_length); -+ -+ return 0; -+} -+ -+int dpni_set_mtu(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t mtu) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_MTU, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_MTU(cmd, mtu); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_mtu(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *mtu) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_MTU, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_MTU(cmd, *mtu); -+ -+ return 0; -+} -+ -+int dpni_set_multicast_promisc(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_MCAST_PROMISC, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_MULTICAST_PROMISC(cmd, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_multicast_promisc(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_MCAST_PROMISC, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_MULTICAST_PROMISC(cmd, *en); -+ -+ return 0; -+} -+ -+int dpni_set_unicast_promisc(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_UNICAST_PROMISC, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_UNICAST_PROMISC(cmd, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_unicast_promisc(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_UNICAST_PROMISC, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_UNICAST_PROMISC(cmd, *en); -+ -+ return 0; -+} -+ -+int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const uint8_t mac_addr[6]) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_PRIM_MAC, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t mac_addr[6]) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_PRIM_MAC, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr); -+ -+ return 0; -+} -+ -+int dpni_add_mac_addr(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const uint8_t mac_addr[6]) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_MAC_ADDR, -+ cmd_flags, -+ token); -+ DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_remove_mac_addr(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const uint8_t mac_addr[6]) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_MAC_ADDR, -+ cmd_flags, -+ token); -+ DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_clear_mac_filters(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int unicast, -+ int multicast) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLR_MAC_FILTERS, -+ cmd_flags, -+ token); -+ DPNI_CMD_CLEAR_MAC_FILTERS(cmd, unicast, multicast); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_vlan_filters(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_VLAN_FILTERS, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_VLAN_FILTERS(cmd, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_add_vlan_id(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_VLAN_ID, -+ cmd_flags, -+ token); -+ DPNI_CMD_ADD_VLAN_ID(cmd, vlan_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_remove_vlan_id(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_VLAN_ID, -+ cmd_flags, -+ token); -+ DPNI_CMD_REMOVE_VLAN_ID(cmd, vlan_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_clear_vlan_filters(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLR_VLAN_FILTERS, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_tx_selection(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_tx_selection_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_SELECTION, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_TX_SELECTION(cmd, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_rx_tc_dist(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ const struct dpni_rx_tc_dist_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_TC_DIST, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_RX_TC_DIST(cmd, tc_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_tx_flow(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *flow_id, -+ const struct dpni_tx_flow_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_FLOW, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_TX_FLOW(cmd, *flow_id, cfg); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_SET_TX_FLOW(cmd, *flow_id); -+ -+ return 0; -+} -+ -+int dpni_get_tx_flow(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t flow_id, -+ struct dpni_tx_flow_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_FLOW, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_TX_FLOW(cmd, flow_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_TX_FLOW(cmd, attr); -+ -+ return 0; -+} -+ -+int dpni_set_rx_flow(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ uint16_t flow_id, -+ const struct dpni_queue_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_FLOW, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_RX_FLOW(cmd, tc_id, flow_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_rx_flow(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ uint16_t flow_id, -+ struct dpni_queue_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_FLOW, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_RX_FLOW(cmd, tc_id, flow_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_RX_FLOW(cmd, attr); -+ -+ return 0; -+} -+ -+int dpni_set_rx_err_queue(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_queue_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_ERR_QUEUE, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_RX_ERR_QUEUE(cmd, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_rx_err_queue(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_queue_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_ERR_QUEUE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPNI_RSP_GET_RX_ERR_QUEUE(cmd, attr); -+ -+ return 0; -+} -+ -+int dpni_set_tx_conf_revoke(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int revoke) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONF_REVOKE, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_TX_CONF_REVOKE(cmd, revoke); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_qos_table(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_qos_tbl_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_QOS_TBL, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_QOS_TABLE(cmd, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_add_qos_entry(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_rule_cfg *cfg, -+ uint8_t tc_id) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_QOS_ENT, -+ cmd_flags, -+ token); -+ DPNI_CMD_ADD_QOS_ENTRY(cmd, cfg, tc_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_remove_qos_entry(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_rule_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_QOS_ENT, -+ cmd_flags, -+ token); -+ DPNI_CMD_REMOVE_QOS_ENTRY(cmd, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_clear_qos_table(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLR_QOS_TBL, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_add_fs_entry(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ const struct dpni_rule_cfg *cfg, -+ uint16_t flow_id) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_FS_ENT, -+ cmd_flags, -+ token); -+ DPNI_CMD_ADD_FS_ENTRY(cmd, tc_id, cfg, flow_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_remove_fs_entry(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ const struct dpni_rule_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_FS_ENT, -+ cmd_flags, -+ token); -+ DPNI_CMD_REMOVE_FS_ENTRY(cmd, tc_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_clear_fs_entries(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLR_FS_ENT, -+ cmd_flags, -+ token); -+ DPNI_CMD_CLEAR_FS_ENTRIES(cmd, tc_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_vlan_insertion(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_VLAN_INSERTION, -+ cmd_flags, token); -+ DPNI_CMD_SET_VLAN_INSERTION(cmd, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_vlan_removal(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_VLAN_REMOVAL, -+ cmd_flags, token); -+ DPNI_CMD_SET_VLAN_REMOVAL(cmd, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_ipr(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IPR, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_IPR(cmd, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_ipf(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IPF, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_IPF(cmd, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_rx_tc_policing(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ const struct dpni_rx_tc_policing_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_TC_POLICING, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_RX_TC_POLICING(cmd, tc_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_rx_tc_policing(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ struct dpni_rx_tc_policing_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_TC_POLICING, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_RX_TC_POLICING(cmd, tc_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ DPNI_RSP_GET_RX_TC_POLICING(cmd, cfg); -+ -+ return 0; -+} -+ -+void dpni_prepare_early_drop(const struct dpni_early_drop_cfg *cfg, -+ uint8_t *early_drop_buf) -+{ -+ uint64_t *ext_params = (uint64_t *)early_drop_buf; -+ -+ DPNI_PREP_EARLY_DROP(ext_params, cfg); -+} -+ -+void dpni_extract_early_drop(struct dpni_early_drop_cfg *cfg, -+ const uint8_t *early_drop_buf) -+{ -+ uint64_t *ext_params = (uint64_t *)early_drop_buf; -+ -+ DPNI_EXT_EARLY_DROP(ext_params, cfg); -+} -+ -+int dpni_set_rx_tc_early_drop(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ uint64_t early_drop_iova) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_TC_EARLY_DROP, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_RX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_rx_tc_early_drop(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ uint64_t early_drop_iova) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_RX_TC_EARLY_DROP, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_RX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_tx_tc_early_drop(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ uint64_t early_drop_iova) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_TC_EARLY_DROP, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_TX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_tx_tc_early_drop(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ uint64_t early_drop_iova) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_TC_EARLY_DROP, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_TX_TC_EARLY_DROP(cmd, tc_id, early_drop_iova); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_set_rx_tc_congestion_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ const struct dpni_congestion_notification_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header( -+ DPNI_CMDID_SET_RX_TC_CONGESTION_NOTIFICATION, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_RX_TC_CONGESTION_NOTIFICATION(cmd, tc_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_rx_tc_congestion_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ struct dpni_congestion_notification_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header( -+ DPNI_CMDID_GET_RX_TC_CONGESTION_NOTIFICATION, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_RX_TC_CONGESTION_NOTIFICATION(cmd, tc_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ DPNI_RSP_GET_RX_TC_CONGESTION_NOTIFICATION(cmd, cfg); -+ -+ return 0; -+} -+ -+int dpni_set_tx_tc_congestion_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ const struct dpni_congestion_notification_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header( -+ DPNI_CMDID_SET_TX_TC_CONGESTION_NOTIFICATION, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_TX_TC_CONGESTION_NOTIFICATION(cmd, tc_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_tx_tc_congestion_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ struct dpni_congestion_notification_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header( -+ DPNI_CMDID_GET_TX_TC_CONGESTION_NOTIFICATION, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_TX_TC_CONGESTION_NOTIFICATION(cmd, tc_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ DPNI_RSP_GET_TX_TC_CONGESTION_NOTIFICATION(cmd, cfg); -+ -+ return 0; -+} -+ -+int dpni_set_tx_conf(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t flow_id, -+ const struct dpni_tx_conf_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONF, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_tx_conf(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t flow_id, -+ struct dpni_tx_conf_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_CONF, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_TX_CONF(cmd, flow_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ DPNI_RSP_GET_TX_CONF(cmd, attr); -+ -+ return 0; -+} -+ -+int dpni_set_tx_conf_congestion_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t flow_id, -+ const struct dpni_congestion_notification_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header( -+ DPNI_CMDID_SET_TX_CONF_CONGESTION_NOTIFICATION, -+ cmd_flags, -+ token); -+ DPNI_CMD_SET_TX_CONF_CONGESTION_NOTIFICATION(cmd, flow_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpni_get_tx_conf_congestion_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t flow_id, -+ struct dpni_congestion_notification_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header( -+ DPNI_CMDID_GET_TX_CONF_CONGESTION_NOTIFICATION, -+ cmd_flags, -+ token); -+ DPNI_CMD_GET_TX_CONF_CONGESTION_NOTIFICATION(cmd, flow_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ DPNI_RSP_GET_TX_CONF_CONGESTION_NOTIFICATION(cmd, cfg); -+ -+ return 0; -+} ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpni.h -@@ -0,0 +1,2581 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef __FSL_DPNI_H -+#define __FSL_DPNI_H -+ -+#include "dpkg.h" -+ -+struct fsl_mc_io; -+ -+/** -+ * Data Path Network Interface API -+ * Contains initialization APIs and runtime control APIs for DPNI -+ */ -+ -+/** General DPNI macros */ -+ -+/** -+ * Maximum number of traffic classes -+ */ -+#define DPNI_MAX_TC 8 -+/** -+ * Maximum number of buffer pools per DPNI -+ */ -+#define DPNI_MAX_DPBP 8 -+/** -+ * Maximum number of storage-profiles per DPNI -+ */ -+#define DPNI_MAX_SP 2 -+ -+/** -+ * All traffic classes considered; see dpni_set_rx_flow() -+ */ -+#define DPNI_ALL_TCS (uint8_t)(-1) -+/** -+ * All flows within traffic class considered; see dpni_set_rx_flow() -+ */ -+#define DPNI_ALL_TC_FLOWS (uint16_t)(-1) -+/** -+ * Generate new flow ID; see dpni_set_tx_flow() -+ */ -+#define DPNI_NEW_FLOW_ID (uint16_t)(-1) -+/* use for common tx-conf queue; see dpni_set_tx_conf_() */ -+#define DPNI_COMMON_TX_CONF (uint16_t)(-1) -+ -+/** -+ * dpni_open() - Open a control session for the specified object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @dpni_id: DPNI unique ID -+ * @token: Returned token; use in subsequent API calls -+ * -+ * This function can be used to open a control session for an -+ * already created object; an object may have been declared in -+ * the DPL or by calling the dpni_create() function. -+ * This function returns a unique authentication token, -+ * associated with the specific object ID and the specific MC -+ * portal; this token must be used in all subsequent commands for -+ * this specific object. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_open(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ int dpni_id, -+ uint16_t *token); -+ -+/** -+ * dpni_close() - Close the control session of the object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * -+ * After this function is called, no further operations are -+ * allowed on the object without opening a new control session. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_close(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/* DPNI configuration options */ -+ -+/** -+ * Allow different distribution key profiles for different traffic classes; -+ * if not set, a single key profile is assumed -+ */ -+#define DPNI_OPT_ALLOW_DIST_KEY_PER_TC 0x00000001 -+ -+/** -+ * Disable all non-error transmit confirmation; error frames are reported -+ * back to a common Tx error queue -+ */ -+#define DPNI_OPT_TX_CONF_DISABLED 0x00000002 -+ -+/** -+ * Disable per-sender private Tx confirmation/error queue -+ */ -+#define DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED 0x00000004 -+ -+/** -+ * Support distribution based on hashed key; -+ * allows statistical distribution over receive queues in a traffic class -+ */ -+#define DPNI_OPT_DIST_HASH 0x00000010 -+ -+/** -+ * DEPRECATED - if this flag is selected and and all new 'max_fs_entries' are -+ * '0' then backward compatibility is preserved; -+ * Support distribution based on flow steering; -+ * allows explicit control of distribution over receive queues in a traffic -+ * class -+ */ -+#define DPNI_OPT_DIST_FS 0x00000020 -+ -+/** -+ * Unicast filtering support -+ */ -+#define DPNI_OPT_UNICAST_FILTER 0x00000080 -+/** -+ * Multicast filtering support -+ */ -+#define DPNI_OPT_MULTICAST_FILTER 0x00000100 -+/** -+ * VLAN filtering support -+ */ -+#define DPNI_OPT_VLAN_FILTER 0x00000200 -+/** -+ * Support IP reassembly on received packets -+ */ -+#define DPNI_OPT_IPR 0x00000800 -+/** -+ * Support IP fragmentation on transmitted packets -+ */ -+#define DPNI_OPT_IPF 0x00001000 -+/** -+ * VLAN manipulation support -+ */ -+#define DPNI_OPT_VLAN_MANIPULATION 0x00010000 -+/** -+ * Support masking of QoS lookup keys -+ */ -+#define DPNI_OPT_QOS_MASK_SUPPORT 0x00020000 -+/** -+ * Support masking of Flow Steering lookup keys -+ */ -+#define DPNI_OPT_FS_MASK_SUPPORT 0x00040000 -+ -+/** -+ * struct dpni_extended_cfg - Structure representing extended DPNI configuration -+ * @tc_cfg: TCs configuration -+ * @ipr_cfg: IP reassembly configuration -+ */ -+struct dpni_extended_cfg { -+ /** -+ * struct tc_cfg - TC configuration -+ * @max_dist: Maximum distribution size for Rx traffic class; -+ * supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96, -+ * 112,128,192,224,256,384,448,512,768,896,1024; -+ * value '0' will be treated as '1'. -+ * other unsupported values will be round down to the nearest -+ * supported value. -+ * @max_fs_entries: Maximum FS entries for Rx traffic class; -+ * '0' means no support for this TC; -+ */ -+ struct { -+ uint16_t max_dist; -+ uint16_t max_fs_entries; -+ } tc_cfg[DPNI_MAX_TC]; -+ /** -+ * struct ipr_cfg - Structure representing IP reassembly configuration -+ * @max_reass_frm_size: Maximum size of the reassembled frame -+ * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments -+ * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments -+ * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly -+ * process -+ * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly -+ * process -+ */ -+ struct { -+ uint16_t max_reass_frm_size; -+ uint16_t min_frag_size_ipv4; -+ uint16_t min_frag_size_ipv6; -+ uint16_t max_open_frames_ipv4; -+ uint16_t max_open_frames_ipv6; -+ } ipr_cfg; -+}; -+ -+/** -+ * dpni_prepare_extended_cfg() - function prepare extended parameters -+ * @cfg: extended structure -+ * @ext_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA -+ * -+ * This function has to be called before dpni_create() -+ */ -+int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg, -+ uint8_t *ext_cfg_buf); -+ -+/** -+ * struct dpni_cfg - Structure representing DPNI configuration -+ * @mac_addr: Primary MAC address -+ * @adv: Advanced parameters; default is all zeros; -+ * use this structure to change default settings -+ */ -+struct dpni_cfg { -+ uint8_t mac_addr[6]; -+ /** -+ * struct adv - Advanced parameters -+ * @options: Mask of available options; use 'DPNI_OPT_' values -+ * @start_hdr: Selects the packet starting header for parsing; -+ * 'NET_PROT_NONE' is treated as default: 'NET_PROT_ETH' -+ * @max_senders: Maximum number of different senders; used as the number -+ * of dedicated Tx flows; Non-power-of-2 values are rounded -+ * up to the next power-of-2 value as hardware demands it; -+ * '0' will be treated as '1' -+ * @max_tcs: Maximum number of traffic classes (for both Tx and Rx); -+ * '0' will e treated as '1' -+ * @max_unicast_filters: Maximum number of unicast filters; -+ * '0' is treated as '16' -+ * @max_multicast_filters: Maximum number of multicast filters; -+ * '0' is treated as '64' -+ * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in -+ * the QoS table; '0' is treated as '64' -+ * @max_qos_key_size: Maximum key size for the QoS look-up; -+ * '0' is treated as '24' which is enough for IPv4 -+ * 5-tuple -+ * @max_dist_key_size: Maximum key size for the distribution; -+ * '0' is treated as '24' which is enough for IPv4 5-tuple -+ * @max_policers: Maximum number of policers; -+ * should be between '0' and max_tcs -+ * @max_congestion_ctrl: Maximum number of congestion control groups -+ * (CGs); covers early drop and congestion notification -+ * requirements; -+ * should be between '0' and ('max_tcs' + 'max_senders') -+ * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory -+ * filled with the extended configuration by calling -+ * dpni_prepare_extended_cfg() -+ */ -+ struct { -+ uint32_t options; -+ enum net_prot start_hdr; -+ uint8_t max_senders; -+ uint8_t max_tcs; -+ uint8_t max_unicast_filters; -+ uint8_t max_multicast_filters; -+ uint8_t max_vlan_filters; -+ uint8_t max_qos_entries; -+ uint8_t max_qos_key_size; -+ uint8_t max_dist_key_size; -+ uint8_t max_policers; -+ uint8_t max_congestion_ctrl; -+ uint64_t ext_cfg_iova; -+ } adv; -+}; -+ -+/** -+ * dpni_create() - Create the DPNI object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @cfg: Configuration structure -+ * @token: Returned token; use in subsequent API calls -+ * -+ * Create the DPNI object, allocate required resources and -+ * perform required initialization. -+ * -+ * The object can be created either by declaring it in the -+ * DPL file, or by calling this function. -+ * -+ * This function returns a unique authentication token, -+ * associated with the specific object ID and the specific MC -+ * portal; this token must be used in all subsequent calls to -+ * this specific object. For objects that are created using the -+ * DPL file, call dpni_open() function to get an authentication -+ * token first. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_create(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ const struct dpni_cfg *cfg, -+ uint16_t *token); -+ -+/** -+ * dpni_destroy() - Destroy the DPNI object and release all its resources. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_destroy(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * struct dpni_pools_cfg - Structure representing buffer pools configuration -+ * @num_dpbp: Number of DPBPs -+ * @pools: Array of buffer pools parameters; The number of valid entries -+ * must match 'num_dpbp' value -+ */ -+struct dpni_pools_cfg { -+ uint8_t num_dpbp; -+ /** -+ * struct pools - Buffer pools parameters -+ * @dpbp_id: DPBP object ID -+ * @buffer_size: Buffer size -+ * @backup_pool: Backup pool -+ */ -+ struct { -+ int dpbp_id; -+ uint16_t buffer_size; -+ int backup_pool; -+ } pools[DPNI_MAX_DPBP]; -+}; -+ -+/** -+ * dpni_set_pools() - Set buffer pools configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @cfg: Buffer pools configuration -+ * -+ * mandatory for DPNI operation -+ * warning:Allowed only when DPNI is disabled -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_pools(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_pools_cfg *cfg); -+ -+/** -+ * dpni_enable() - Enable the DPNI, allow sending and receiving frames. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpni_disable() - Disable the DPNI, stop sending and receiving frames. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpni_is_enabled() - Check if the DPNI is enabled. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Returns '1' if object is enabled; '0' otherwise -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_is_enabled(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en); -+ -+/** -+ * dpni_reset() - Reset the DPNI, returns the object to initial state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_reset(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * DPNI IRQ Index and Events -+ */ -+ -+/** -+ * IRQ index -+ */ -+#define DPNI_IRQ_INDEX 0 -+/** -+ * IRQ event - indicates a change in link state -+ */ -+#define DPNI_IRQ_EVENT_LINK_CHANGED 0x00000001 -+ -+/** -+ * struct dpni_irq_cfg - IRQ configuration -+ * @addr: Address that must be written to signal a message-based interrupt -+ * @val: Value to write into irq_addr address -+ * @irq_num: A user defined number associated with this IRQ -+ */ -+struct dpni_irq_cfg { -+ uint64_t addr; -+ uint32_t val; -+ int irq_num; -+}; -+ -+/** -+ * dpni_set_irq() - Set IRQ information for the DPNI to trigger an interrupt. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @irq_index: Identifies the interrupt index to configure -+ * @irq_cfg: IRQ configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ struct dpni_irq_cfg *irq_cfg); -+ -+/** -+ * dpni_get_irq() - Get IRQ information from the DPNI. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @irq_index: The interrupt index to configure -+ * @type: Interrupt type: 0 represents message interrupt -+ * type (both irq_addr and irq_val are valid) -+ * @irq_cfg: IRQ attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ int *type, -+ struct dpni_irq_cfg *irq_cfg); -+ -+/** -+ * dpni_set_irq_enable() - Set overall interrupt state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @irq_index: The interrupt index to configure -+ * @en: Interrupt state: - enable = 1, disable = 0 -+ * -+ * Allows GPP software to control when interrupts are generated. -+ * Each interrupt can have up to 32 causes. The enable/disable control's the -+ * overall interrupt state. if the interrupt is disabled no causes will cause -+ * an interrupt. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t en); -+ -+/** -+ * dpni_get_irq_enable() - Get overall interrupt state -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @irq_index: The interrupt index to configure -+ * @en: Returned interrupt state - enable = 1, disable = 0 -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t *en); -+ -+/** -+ * dpni_set_irq_mask() - Set interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @irq_index: The interrupt index to configure -+ * @mask: event mask to trigger interrupt; -+ * each bit: -+ * 0 = ignore event -+ * 1 = consider event for asserting IRQ -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t mask); -+ -+/** -+ * dpni_get_irq_mask() - Get interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @irq_index: The interrupt index to configure -+ * @mask: Returned event mask to trigger interrupt -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *mask); -+ -+/** -+ * dpni_get_irq_status() - Get the current status of any pending interrupts. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @irq_index: The interrupt index to configure -+ * @status: Returned interrupts status - one bit per cause: -+ * 0 = no interrupt pending -+ * 1 = interrupt pending -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *status); -+ -+/** -+ * dpni_clear_irq_status() - Clear a pending interrupt's status -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @irq_index: The interrupt index to configure -+ * @status: bits to clear (W1C) - one bit per cause: -+ * 0 = don't change -+ * 1 = clear status bit -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_clear_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t status); -+ -+/** -+ * struct dpni_attr - Structure representing DPNI attributes -+ * @id: DPNI object ID -+ * @version: DPNI version -+ * @start_hdr: Indicates the packet starting header for parsing -+ * @options: Mask of available options; reflects the value as was given in -+ * object's creation -+ * @max_senders: Maximum number of different senders; used as the number -+ * of dedicated Tx flows; -+ * @max_tcs: Maximum number of traffic classes (for both Tx and Rx) -+ * @max_unicast_filters: Maximum number of unicast filters -+ * @max_multicast_filters: Maximum number of multicast filters -+ * @max_vlan_filters: Maximum number of VLAN filters -+ * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in QoS table -+ * @max_qos_key_size: Maximum key size for the QoS look-up -+ * @max_dist_key_size: Maximum key size for the distribution look-up -+ * @max_policers: Maximum number of policers; -+ * @max_congestion_ctrl: Maximum number of congestion control groups (CGs); -+ * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory; -+ * call dpni_extract_extended_cfg() to extract the extended configuration -+ */ -+struct dpni_attr { -+ int id; -+ /** -+ * struct version - DPNI version -+ * @major: DPNI major version -+ * @minor: DPNI minor version -+ */ -+ struct { -+ uint16_t major; -+ uint16_t minor; -+ } version; -+ enum net_prot start_hdr; -+ uint32_t options; -+ uint8_t max_senders; -+ uint8_t max_tcs; -+ uint8_t max_unicast_filters; -+ uint8_t max_multicast_filters; -+ uint8_t max_vlan_filters; -+ uint8_t max_qos_entries; -+ uint8_t max_qos_key_size; -+ uint8_t max_dist_key_size; -+ uint8_t max_policers; -+ uint8_t max_congestion_ctrl; -+ uint64_t ext_cfg_iova; -+}; -+ -+/** -+ * dpni_get_attributes() - Retrieve DPNI attributes. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @attr: Object's attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_attr *attr); -+ -+/** -+ * dpni_extract_extended_cfg() - extract the extended parameters -+ * @cfg: extended structure -+ * @ext_cfg_buf: 256 bytes of DMA-able memory -+ * -+ * This function has to be called after dpni_get_attributes() -+ */ -+int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg, -+ const uint8_t *ext_cfg_buf); -+ -+/** -+ * DPNI errors -+ */ -+ -+/** -+ * Extract out of frame header error -+ */ -+#define DPNI_ERROR_EOFHE 0x00020000 -+/** -+ * Frame length error -+ */ -+#define DPNI_ERROR_FLE 0x00002000 -+/** -+ * Frame physical error -+ */ -+#define DPNI_ERROR_FPE 0x00001000 -+/** -+ * Parsing header error -+ */ -+#define DPNI_ERROR_PHE 0x00000020 -+/** -+ * Parser L3 checksum error -+ */ -+#define DPNI_ERROR_L3CE 0x00000004 -+/** -+ * Parser L3 checksum error -+ */ -+#define DPNI_ERROR_L4CE 0x00000001 -+ -+/** -+ * enum dpni_error_action - Defines DPNI behavior for errors -+ * @DPNI_ERROR_ACTION_DISCARD: Discard the frame -+ * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow -+ * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue -+ */ -+enum dpni_error_action { -+ DPNI_ERROR_ACTION_DISCARD = 0, -+ DPNI_ERROR_ACTION_CONTINUE = 1, -+ DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2 -+}; -+ -+/** -+ * struct dpni_error_cfg - Structure representing DPNI errors treatment -+ * @errors: Errors mask; use 'DPNI_ERROR__ -+ * @error_action: The desired action for the errors mask -+ * @set_frame_annotation: Set to '1' to mark the errors in frame annotation -+ * status (FAS); relevant only for the non-discard action -+ */ -+struct dpni_error_cfg { -+ uint32_t errors; -+ enum dpni_error_action error_action; -+ int set_frame_annotation; -+}; -+ -+/** -+ * dpni_set_errors_behavior() - Set errors behavior -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @cfg: Errors configuration -+ * -+ * this function may be called numerous times with different -+ * error masks -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_error_cfg *cfg); -+ -+/** -+ * DPNI buffer layout modification options -+ */ -+ -+/** -+ * Select to modify the time-stamp setting -+ */ -+#define DPNI_BUF_LAYOUT_OPT_TIMESTAMP 0x00000001 -+/** -+ * Select to modify the parser-result setting; not applicable for Tx -+ */ -+#define DPNI_BUF_LAYOUT_OPT_PARSER_RESULT 0x00000002 -+/** -+ * Select to modify the frame-status setting -+ */ -+#define DPNI_BUF_LAYOUT_OPT_FRAME_STATUS 0x00000004 -+/** -+ * Select to modify the private-data-size setting -+ */ -+#define DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE 0x00000008 -+/** -+ * Select to modify the data-alignment setting -+ */ -+#define DPNI_BUF_LAYOUT_OPT_DATA_ALIGN 0x00000010 -+/** -+ * Select to modify the data-head-room setting -+ */ -+#define DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM 0x00000020 -+/** -+ * Select to modify the data-tail-room setting -+ */ -+#define DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM 0x00000040 -+ -+/** -+ * struct dpni_buffer_layout - Structure representing DPNI buffer layout -+ * @options: Flags representing the suggested modifications to the buffer -+ * layout; Use any combination of 'DPNI_BUF_LAYOUT_OPT_' flags -+ * @pass_timestamp: Pass timestamp value -+ * @pass_parser_result: Pass parser results -+ * @pass_frame_status: Pass frame status -+ * @private_data_size: Size kept for private data (in bytes) -+ * @data_align: Data alignment -+ * @data_head_room: Data head room -+ * @data_tail_room: Data tail room -+ */ -+struct dpni_buffer_layout { -+ uint32_t options; -+ int pass_timestamp; -+ int pass_parser_result; -+ int pass_frame_status; -+ uint16_t private_data_size; -+ uint16_t data_align; -+ uint16_t data_head_room; -+ uint16_t data_tail_room; -+}; -+ -+/** -+ * dpni_get_rx_buffer_layout() - Retrieve Rx buffer layout attributes. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @layout: Returns buffer layout attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_buffer_layout *layout); -+ -+/** -+ * dpni_set_rx_buffer_layout() - Set Rx buffer layout configuration. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @layout: Buffer layout configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ * -+ * @warning Allowed only when DPNI is disabled -+ */ -+int dpni_set_rx_buffer_layout(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_buffer_layout *layout); -+ -+/** -+ * dpni_get_tx_buffer_layout() - Retrieve Tx buffer layout attributes. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @layout: Returns buffer layout attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_tx_buffer_layout(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_buffer_layout *layout); -+ -+/** -+ * dpni_set_tx_buffer_layout() - Set Tx buffer layout configuration. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @layout: Buffer layout configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ * -+ * @warning Allowed only when DPNI is disabled -+ */ -+int dpni_set_tx_buffer_layout(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_buffer_layout *layout); -+ -+/** -+ * dpni_get_tx_conf_buffer_layout() - Retrieve Tx confirmation buffer layout -+ * attributes. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @layout: Returns buffer layout attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_tx_conf_buffer_layout(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_buffer_layout *layout); -+ -+/** -+ * dpni_set_tx_conf_buffer_layout() - Set Tx confirmation buffer layout -+ * configuration. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @layout: Buffer layout configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ * -+ * @warning Allowed only when DPNI is disabled -+ */ -+int dpni_set_tx_conf_buffer_layout(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_buffer_layout *layout); -+ -+/** -+ * dpni_set_l3_chksum_validation() - Enable/disable L3 checksum validation -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Set to '1' to enable; '0' to disable -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_l3_chksum_validation(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en); -+ -+/** -+ * dpni_get_l3_chksum_validation() - Get L3 checksum validation mode -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Returns '1' if enabled; '0' otherwise -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_l3_chksum_validation(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en); -+ -+/** -+ * dpni_set_l4_chksum_validation() - Enable/disable L4 checksum validation -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Set to '1' to enable; '0' to disable -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_l4_chksum_validation(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en); -+ -+/** -+ * dpni_get_l4_chksum_validation() - Get L4 checksum validation mode -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Returns '1' if enabled; '0' otherwise -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_l4_chksum_validation(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en); -+ -+/** -+ * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used -+ * for enqueue operations -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @qdid: Returned virtual QDID value that should be used as an argument -+ * in all enqueue operations -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_qdid(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *qdid); -+ -+/** -+ * struct dpni_sp_info - Structure representing DPNI storage-profile information -+ * (relevant only for DPNI owned by AIOP) -+ * @spids: array of storage-profiles -+ */ -+struct dpni_sp_info { -+ uint16_t spids[DPNI_MAX_SP]; -+}; -+ -+/** -+ * dpni_get_spids() - Get the AIOP storage profile IDs associated with the DPNI -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @sp_info: Returned AIOP storage-profile information -+ * -+ * Return: '0' on Success; Error code otherwise. -+ * -+ * @warning Only relevant for DPNI that belongs to AIOP container. -+ */ -+int dpni_get_sp_info(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_sp_info *sp_info); -+ -+/** -+ * dpni_get_tx_data_offset() - Get the Tx data offset (from start of buffer) -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @data_offset: Tx data offset (from start of buffer) -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *data_offset); -+ -+/** -+ * enum dpni_counter - DPNI counter types -+ * @DPNI_CNT_ING_FRAME: Counts ingress frames -+ * @DPNI_CNT_ING_BYTE: Counts ingress bytes -+ * @DPNI_CNT_ING_FRAME_DROP: Counts ingress frames dropped due to explicit -+ * 'drop' setting -+ * @DPNI_CNT_ING_FRAME_DISCARD: Counts ingress frames discarded due to errors -+ * @DPNI_CNT_ING_MCAST_FRAME: Counts ingress multicast frames -+ * @DPNI_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes -+ * @DPNI_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames -+ * @DPNI_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes -+ * @DPNI_CNT_EGR_FRAME: Counts egress frames -+ * @DPNI_CNT_EGR_BYTE: Counts egress bytes -+ * @DPNI_CNT_EGR_FRAME_DISCARD: Counts egress frames discarded due to errors -+ */ -+enum dpni_counter { -+ DPNI_CNT_ING_FRAME = 0x0, -+ DPNI_CNT_ING_BYTE = 0x1, -+ DPNI_CNT_ING_FRAME_DROP = 0x2, -+ DPNI_CNT_ING_FRAME_DISCARD = 0x3, -+ DPNI_CNT_ING_MCAST_FRAME = 0x4, -+ DPNI_CNT_ING_MCAST_BYTE = 0x5, -+ DPNI_CNT_ING_BCAST_FRAME = 0x6, -+ DPNI_CNT_ING_BCAST_BYTES = 0x7, -+ DPNI_CNT_EGR_FRAME = 0x8, -+ DPNI_CNT_EGR_BYTE = 0x9, -+ DPNI_CNT_EGR_FRAME_DISCARD = 0xa -+}; -+ -+/** -+ * dpni_get_counter() - Read a specific DPNI counter -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @counter: The requested counter -+ * @value: Returned counter's current value -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_counter(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ enum dpni_counter counter, -+ uint64_t *value); -+ -+/** -+ * dpni_set_counter() - Set (or clear) a specific DPNI counter -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @counter: The requested counter -+ * @value: New counter value; typically pass '0' for resetting -+ * the counter. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_counter(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ enum dpni_counter counter, -+ uint64_t value); -+ -+/** -+ * Enable auto-negotiation -+ */ -+#define DPNI_LINK_OPT_AUTONEG 0x0000000000000001ULL -+/** -+ * Enable half-duplex mode -+ */ -+#define DPNI_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL -+/** -+ * Enable pause frames -+ */ -+#define DPNI_LINK_OPT_PAUSE 0x0000000000000004ULL -+/** -+ * Enable a-symmetric pause frames -+ */ -+#define DPNI_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL -+ -+/** -+ * struct - Structure representing DPNI link configuration -+ * @rate: Rate -+ * @options: Mask of available options; use 'DPNI_LINK_OPT_' values -+ */ -+struct dpni_link_cfg { -+ uint32_t rate; -+ uint64_t options; -+}; -+ -+/** -+ * dpni_set_link_cfg() - set the link configuration. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @cfg: Link configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_link_cfg(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_link_cfg *cfg); -+ -+/** -+ * struct dpni_link_state - Structure representing DPNI link state -+ * @rate: Rate -+ * @options: Mask of available options; use 'DPNI_LINK_OPT_' values -+ * @up: Link state; '0' for down, '1' for up -+ */ -+struct dpni_link_state { -+ uint32_t rate; -+ uint64_t options; -+ int up; -+}; -+ -+/** -+ * dpni_get_link_state() - Return the link state (either up or down) -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @state: Returned link state; -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_link_state(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_link_state *state); -+ -+/** -+ * struct dpni_tx_shaping - Structure representing DPNI tx shaping configuration -+ * @rate_limit: rate in Mbps -+ * @max_burst_size: burst size in bytes (up to 64KB) -+ */ -+struct dpni_tx_shaping_cfg { -+ uint32_t rate_limit; -+ uint16_t max_burst_size; -+}; -+ -+/** -+ * dpni_set_tx_shaping() - Set the transmit shaping -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tx_shaper: tx shaping configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_tx_shaping(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_tx_shaping_cfg *tx_shaper); -+ -+/** -+ * dpni_set_max_frame_length() - Set the maximum received frame length. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @max_frame_length: Maximum received frame length (in -+ * bytes); frame is discarded if its -+ * length exceeds this value -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_max_frame_length(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t max_frame_length); -+ -+/** -+ * dpni_get_max_frame_length() - Get the maximum received frame length. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @max_frame_length: Maximum received frame length (in -+ * bytes); frame is discarded if its -+ * length exceeds this value -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_max_frame_length(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *max_frame_length); -+ -+/** -+ * dpni_set_mtu() - Set the MTU for the interface. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @mtu: MTU length (in bytes) -+ * -+ * MTU determines the maximum fragment size for performing IP -+ * fragmentation on egress packets. -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_mtu(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t mtu); -+ -+/** -+ * dpni_get_mtu() - Get the MTU. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @mtu: Returned MTU length (in bytes) -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_mtu(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *mtu); -+ -+/** -+ * dpni_set_multicast_promisc() - Enable/disable multicast promiscuous mode -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Set to '1' to enable; '0' to disable -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_multicast_promisc(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en); -+ -+/** -+ * dpni_get_multicast_promisc() - Get multicast promiscuous mode -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Returns '1' if enabled; '0' otherwise -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_multicast_promisc(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en); -+ -+/** -+ * dpni_set_unicast_promisc() - Enable/disable unicast promiscuous mode -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Set to '1' to enable; '0' to disable -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_unicast_promisc(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en); -+ -+/** -+ * dpni_get_unicast_promisc() - Get unicast promiscuous mode -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Returns '1' if enabled; '0' otherwise -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_unicast_promisc(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en); -+ -+/** -+ * dpni_set_primary_mac_addr() - Set the primary MAC address -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @mac_addr: MAC address to set as primary address -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const uint8_t mac_addr[6]); -+ -+/** -+ * dpni_get_primary_mac_addr() - Get the primary MAC address -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @mac_addr: Returned MAC address -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t mac_addr[6]); -+ -+/** -+ * dpni_add_mac_addr() - Add MAC address filter -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @mac_addr: MAC address to add -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_add_mac_addr(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const uint8_t mac_addr[6]); -+ -+/** -+ * dpni_remove_mac_addr() - Remove MAC address filter -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @mac_addr: MAC address to remove -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_remove_mac_addr(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const uint8_t mac_addr[6]); -+ -+/** -+ * dpni_clear_mac_filters() - Clear all unicast and/or multicast MAC filters -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @unicast: Set to '1' to clear unicast addresses -+ * @multicast: Set to '1' to clear multicast addresses -+ * -+ * The primary MAC address is not cleared by this operation. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_clear_mac_filters(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int unicast, -+ int multicast); -+ -+/** -+ * dpni_set_vlan_filters() - Enable/disable VLAN filtering mode -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Set to '1' to enable; '0' to disable -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_vlan_filters(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en); -+ -+/** -+ * dpni_add_vlan_id() - Add VLAN ID filter -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @vlan_id: VLAN ID to add -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_add_vlan_id(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id); -+ -+/** -+ * dpni_remove_vlan_id() - Remove VLAN ID filter -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @vlan_id: VLAN ID to remove -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_remove_vlan_id(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id); -+ -+/** -+ * dpni_clear_vlan_filters() - Clear all VLAN filters -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_clear_vlan_filters(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * enum dpni_tx_schedule_mode - DPNI Tx scheduling mode -+ * @DPNI_TX_SCHED_STRICT_PRIORITY: strict priority -+ * @DPNI_TX_SCHED_WEIGHTED: weighted based scheduling -+ */ -+enum dpni_tx_schedule_mode { -+ DPNI_TX_SCHED_STRICT_PRIORITY, -+ DPNI_TX_SCHED_WEIGHTED, -+}; -+ -+/** -+ * struct dpni_tx_schedule_cfg - Structure representing Tx -+ * scheduling configuration -+ * @mode: scheduling mode -+ * @delta_bandwidth: Bandwidth represented in weights from 100 to 10000; -+ * not applicable for 'strict-priority' mode; -+ */ -+struct dpni_tx_schedule_cfg { -+ enum dpni_tx_schedule_mode mode; -+ uint16_t delta_bandwidth; -+}; -+ -+/** -+ * struct dpni_tx_selection_cfg - Structure representing transmission -+ * selection configuration -+ * @tc_sched: an array of traffic-classes -+ */ -+struct dpni_tx_selection_cfg { -+ struct dpni_tx_schedule_cfg tc_sched[DPNI_MAX_TC]; -+}; -+ -+/** -+ * dpni_set_tx_selection() - Set transmission selection configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @cfg: transmission selection configuration -+ * -+ * warning: Allowed only when DPNI is disabled -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_tx_selection(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_tx_selection_cfg *cfg); -+ -+/** -+ * enum dpni_dist_mode - DPNI distribution mode -+ * @DPNI_DIST_MODE_NONE: No distribution -+ * @DPNI_DIST_MODE_HASH: Use hash distribution; only relevant if -+ * the 'DPNI_OPT_DIST_HASH' option was set at DPNI creation -+ * @DPNI_DIST_MODE_FS: Use explicit flow steering; only relevant if -+ * the 'DPNI_OPT_DIST_FS' option was set at DPNI creation -+ */ -+enum dpni_dist_mode { -+ DPNI_DIST_MODE_NONE = 0, -+ DPNI_DIST_MODE_HASH = 1, -+ DPNI_DIST_MODE_FS = 2 -+}; -+ -+/** -+ * enum dpni_fs_miss_action - DPNI Flow Steering miss action -+ * @DPNI_FS_MISS_DROP: In case of no-match, drop the frame -+ * @DPNI_FS_MISS_EXPLICIT_FLOWID: In case of no-match, use explicit flow-id -+ * @DPNI_FS_MISS_HASH: In case of no-match, distribute using hash -+ */ -+enum dpni_fs_miss_action { -+ DPNI_FS_MISS_DROP = 0, -+ DPNI_FS_MISS_EXPLICIT_FLOWID = 1, -+ DPNI_FS_MISS_HASH = 2 -+}; -+ -+/** -+ * struct dpni_fs_tbl_cfg - Flow Steering table configuration -+ * @miss_action: Miss action selection -+ * @default_flow_id: Used when 'miss_action = DPNI_FS_MISS_EXPLICIT_FLOWID' -+ */ -+struct dpni_fs_tbl_cfg { -+ enum dpni_fs_miss_action miss_action; -+ uint16_t default_flow_id; -+}; -+ -+/** -+ * dpni_prepare_key_cfg() - function prepare extract parameters -+ * @cfg: defining a full Key Generation profile (rule) -+ * @key_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA -+ * -+ * This function has to be called before the following functions: -+ * - dpni_set_rx_tc_dist() -+ * - dpni_set_qos_table() -+ */ -+int dpni_prepare_key_cfg(const struct dpkg_profile_cfg *cfg, -+ uint8_t *key_cfg_buf); -+ -+/** -+ * struct dpni_rx_tc_dist_cfg - Rx traffic class distribution configuration -+ * @dist_size: Set the distribution size; -+ * supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96, -+ * 112,128,192,224,256,384,448,512,768,896,1024 -+ * @dist_mode: Distribution mode -+ * @key_cfg_iova: I/O virtual address of 256 bytes DMA-able memory filled with -+ * the extractions to be used for the distribution key by calling -+ * dpni_prepare_key_cfg() relevant only when -+ * 'dist_mode != DPNI_DIST_MODE_NONE', otherwise it can be '0' -+ * @fs_cfg: Flow Steering table configuration; only relevant if -+ * 'dist_mode = DPNI_DIST_MODE_FS' -+ */ -+struct dpni_rx_tc_dist_cfg { -+ uint16_t dist_size; -+ enum dpni_dist_mode dist_mode; -+ uint64_t key_cfg_iova; -+ struct dpni_fs_tbl_cfg fs_cfg; -+}; -+ -+/** -+ * dpni_set_rx_tc_dist() - Set Rx traffic class distribution configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @cfg: Traffic class distribution configuration -+ * -+ * warning: if 'dist_mode != DPNI_DIST_MODE_NONE', call dpni_prepare_key_cfg() -+ * first to prepare the key_cfg_iova parameter -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_set_rx_tc_dist(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ const struct dpni_rx_tc_dist_cfg *cfg); -+ -+/** -+ * Set to select color aware mode (otherwise - color blind) -+ */ -+#define DPNI_POLICER_OPT_COLOR_AWARE 0x00000001 -+/** -+ * Set to discard frame with RED color -+ */ -+#define DPNI_POLICER_OPT_DISCARD_RED 0x00000002 -+ -+/** -+ * enum dpni_policer_mode - selecting the policer mode -+ * @DPNI_POLICER_MODE_NONE: Policer is disabled -+ * @DPNI_POLICER_MODE_PASS_THROUGH: Policer pass through -+ * @DPNI_POLICER_MODE_RFC_2698: Policer algorithm RFC 2698 -+ * @DPNI_POLICER_MODE_RFC_4115: Policer algorithm RFC 4115 -+ */ -+enum dpni_policer_mode { -+ DPNI_POLICER_MODE_NONE = 0, -+ DPNI_POLICER_MODE_PASS_THROUGH, -+ DPNI_POLICER_MODE_RFC_2698, -+ DPNI_POLICER_MODE_RFC_4115 -+}; -+ -+/** -+ * enum dpni_policer_unit - DPNI policer units -+ * @DPNI_POLICER_UNIT_BYTES: bytes units -+ * @DPNI_POLICER_UNIT_FRAMES: frames units -+ */ -+enum dpni_policer_unit { -+ DPNI_POLICER_UNIT_BYTES = 0, -+ DPNI_POLICER_UNIT_FRAMES -+}; -+ -+/** -+ * enum dpni_policer_color - selecting the policer color -+ * @DPNI_POLICER_COLOR_GREEN: Green color -+ * @DPNI_POLICER_COLOR_YELLOW: Yellow color -+ * @DPNI_POLICER_COLOR_RED: Red color -+ */ -+enum dpni_policer_color { -+ DPNI_POLICER_COLOR_GREEN = 0, -+ DPNI_POLICER_COLOR_YELLOW, -+ DPNI_POLICER_COLOR_RED -+}; -+ -+/** -+ * struct dpni_rx_tc_policing_cfg - Policer configuration -+ * @options: Mask of available options; use 'DPNI_POLICER_OPT_' values -+ * @mode: policer mode -+ * @default_color: For pass-through mode the policer re-colors with this -+ * color any incoming packets. For Color aware non-pass-through mode: -+ * policer re-colors with this color all packets with FD[DROPP]>2. -+ * @units: Bytes or Packets -+ * @cir: Committed information rate (CIR) in Kbps or packets/second -+ * @cbs: Committed burst size (CBS) in bytes or packets -+ * @eir: Peak information rate (PIR, rfc2698) in Kbps or packets/second -+ * Excess information rate (EIR, rfc4115) in Kbps or packets/second -+ * @ebs: Peak burst size (PBS, rfc2698) in bytes or packets -+ * Excess burst size (EBS, rfc4115) in bytes or packets -+ */ -+struct dpni_rx_tc_policing_cfg { -+ uint32_t options; -+ enum dpni_policer_mode mode; -+ enum dpni_policer_unit units; -+ enum dpni_policer_color default_color; -+ uint32_t cir; -+ uint32_t cbs; -+ uint32_t eir; -+ uint32_t ebs; -+}; -+ -+/** -+ * dpni_set_rx_tc_policing() - Set Rx traffic class policing configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @cfg: Traffic class policing configuration -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_set_rx_tc_policing(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ const struct dpni_rx_tc_policing_cfg *cfg); -+ -+/** -+ * dpni_get_rx_tc_policing() - Get Rx traffic class policing configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @cfg: Traffic class policing configuration -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_get_rx_tc_policing(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ struct dpni_rx_tc_policing_cfg *cfg); -+ -+/** -+ * enum dpni_congestion_unit - DPNI congestion units -+ * @DPNI_CONGESTION_UNIT_BYTES: bytes units -+ * @DPNI_CONGESTION_UNIT_FRAMES: frames units -+ */ -+enum dpni_congestion_unit { -+ DPNI_CONGESTION_UNIT_BYTES = 0, -+ DPNI_CONGESTION_UNIT_FRAMES -+}; -+ -+/** -+ * enum dpni_early_drop_mode - DPNI early drop mode -+ * @DPNI_EARLY_DROP_MODE_NONE: early drop is disabled -+ * @DPNI_EARLY_DROP_MODE_TAIL: early drop in taildrop mode -+ * @DPNI_EARLY_DROP_MODE_WRED: early drop in WRED mode -+ */ -+enum dpni_early_drop_mode { -+ DPNI_EARLY_DROP_MODE_NONE = 0, -+ DPNI_EARLY_DROP_MODE_TAIL, -+ DPNI_EARLY_DROP_MODE_WRED -+}; -+ -+/** -+ * struct dpni_wred_cfg - WRED configuration -+ * @max_threshold: maximum threshold that packets may be discarded. Above this -+ * threshold all packets are discarded; must be less than 2^39; -+ * approximated to be expressed as (x+256)*2^(y-1) due to HW -+ * implementation. -+ * @min_threshold: minimum threshold that packets may be discarded at -+ * @drop_probability: probability that a packet will be discarded (1-100, -+ * associated with the max_threshold). -+ */ -+struct dpni_wred_cfg { -+ uint64_t max_threshold; -+ uint64_t min_threshold; -+ uint8_t drop_probability; -+}; -+ -+/** -+ * struct dpni_early_drop_cfg - early-drop configuration -+ * @mode: drop mode -+ * @units: units type -+ * @green: WRED - 'green' configuration -+ * @yellow: WRED - 'yellow' configuration -+ * @red: WRED - 'red' configuration -+ * @tail_drop_threshold: tail drop threshold -+ */ -+struct dpni_early_drop_cfg { -+ enum dpni_early_drop_mode mode; -+ enum dpni_congestion_unit units; -+ -+ struct dpni_wred_cfg green; -+ struct dpni_wred_cfg yellow; -+ struct dpni_wred_cfg red; -+ -+ uint32_t tail_drop_threshold; -+}; -+ -+/** -+ * dpni_prepare_early_drop() - prepare an early drop. -+ * @cfg: Early-drop configuration -+ * @early_drop_buf: Zeroed 256 bytes of memory before mapping it to DMA -+ * -+ * This function has to be called before dpni_set_rx_tc_early_drop or -+ * dpni_set_tx_tc_early_drop -+ * -+ */ -+void dpni_prepare_early_drop(const struct dpni_early_drop_cfg *cfg, -+ uint8_t *early_drop_buf); -+ -+/** -+ * dpni_extract_early_drop() - extract the early drop configuration. -+ * @cfg: Early-drop configuration -+ * @early_drop_buf: Zeroed 256 bytes of memory before mapping it to DMA -+ * -+ * This function has to be called after dpni_get_rx_tc_early_drop or -+ * dpni_get_tx_tc_early_drop -+ * -+ */ -+void dpni_extract_early_drop(struct dpni_early_drop_cfg *cfg, -+ const uint8_t *early_drop_buf); -+ -+/** -+ * dpni_set_rx_tc_early_drop() - Set Rx traffic class early-drop configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @early_drop_iova: I/O virtual address of 256 bytes DMA-able memory filled -+ * with the early-drop configuration by calling dpni_prepare_early_drop() -+ * -+ * warning: Before calling this function, call dpni_prepare_early_drop() to -+ * prepare the early_drop_iova parameter -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_set_rx_tc_early_drop(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ uint64_t early_drop_iova); -+ -+/** -+ * dpni_get_rx_tc_early_drop() - Get Rx traffic class early-drop configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @early_drop_iova: I/O virtual address of 256 bytes DMA-able memory -+ * -+ * warning: After calling this function, call dpni_extract_early_drop() to -+ * get the early drop configuration -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_get_rx_tc_early_drop(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ uint64_t early_drop_iova); -+ -+/** -+ * dpni_set_tx_tc_early_drop() - Set Tx traffic class early-drop configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @early_drop_iova: I/O virtual address of 256 bytes DMA-able memory filled -+ * with the early-drop configuration by calling dpni_prepare_early_drop() -+ * -+ * warning: Before calling this function, call dpni_prepare_early_drop() to -+ * prepare the early_drop_iova parameter -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_set_tx_tc_early_drop(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ uint64_t early_drop_iova); -+ -+/** -+ * dpni_get_tx_tc_early_drop() - Get Tx traffic class early-drop configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @early_drop_iova: I/O virtual address of 256 bytes DMA-able memory -+ * -+ * warning: After calling this function, call dpni_extract_early_drop() to -+ * get the early drop configuration -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_get_tx_tc_early_drop(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ uint64_t early_drop_iova); -+ -+/** -+ * enum dpni_dest - DPNI destination types -+ * @DPNI_DEST_NONE: Unassigned destination; The queue is set in parked mode and -+ * does not generate FQDAN notifications; user is expected to -+ * dequeue from the queue based on polling or other user-defined -+ * method -+ * @DPNI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN -+ * notifications to the specified DPIO; user is expected to dequeue -+ * from the queue only after notification is received -+ * @DPNI_DEST_DPCON: The queue is set in schedule mode and does not generate -+ * FQDAN notifications, but is connected to the specified DPCON -+ * object; user is expected to dequeue from the DPCON channel -+ */ -+enum dpni_dest { -+ DPNI_DEST_NONE = 0, -+ DPNI_DEST_DPIO = 1, -+ DPNI_DEST_DPCON = 2 -+}; -+ -+/** -+ * struct dpni_dest_cfg - Structure representing DPNI destination parameters -+ * @dest_type: Destination type -+ * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type -+ * @priority: Priority selection within the DPIO or DPCON channel; valid values -+ * are 0-1 or 0-7, depending on the number of priorities in that -+ * channel; not relevant for 'DPNI_DEST_NONE' option -+ */ -+struct dpni_dest_cfg { -+ enum dpni_dest dest_type; -+ int dest_id; -+ uint8_t priority; -+}; -+ -+/* DPNI congestion options */ -+ -+/** -+ * CSCN message is written to message_iova once entering a -+ * congestion state (see 'threshold_entry') -+ */ -+#define DPNI_CONG_OPT_WRITE_MEM_ON_ENTER 0x00000001 -+/** -+ * CSCN message is written to message_iova once exiting a -+ * congestion state (see 'threshold_exit') -+ */ -+#define DPNI_CONG_OPT_WRITE_MEM_ON_EXIT 0x00000002 -+/** -+ * CSCN write will attempt to allocate into a cache (coherent write); -+ * valid only if 'DPNI_CONG_OPT_WRITE_MEM_' is selected -+ */ -+#define DPNI_CONG_OPT_COHERENT_WRITE 0x00000004 -+/** -+ * if 'dest_cfg.dest_type != DPNI_DEST_NONE' CSCN message is sent to -+ * DPIO/DPCON's WQ channel once entering a congestion state -+ * (see 'threshold_entry') -+ */ -+#define DPNI_CONG_OPT_NOTIFY_DEST_ON_ENTER 0x00000008 -+/** -+ * if 'dest_cfg.dest_type != DPNI_DEST_NONE' CSCN message is sent to -+ * DPIO/DPCON's WQ channel once exiting a congestion state -+ * (see 'threshold_exit') -+ */ -+#define DPNI_CONG_OPT_NOTIFY_DEST_ON_EXIT 0x00000010 -+/** -+ * if 'dest_cfg.dest_type != DPNI_DEST_NONE' when the CSCN is written to the -+ * sw-portal's DQRR, the DQRI interrupt is asserted immediately (if enabled) -+ */ -+#define DPNI_CONG_OPT_INTR_COALESCING_DISABLED 0x00000020 -+ -+/** -+ * struct dpni_congestion_notification_cfg - congestion notification -+ * configuration -+ * @units: units type -+ * @threshold_entry: above this threshold we enter a congestion state. -+ * set it to '0' to disable it -+ * @threshold_exit: below this threshold we exit the congestion state. -+ * @message_ctx: The context that will be part of the CSCN message -+ * @message_iova: I/O virtual address (must be in DMA-able memory), -+ * must be 16B aligned; valid only if 'DPNI_CONG_OPT_WRITE_MEM_' is -+ * contained in 'options' -+ * @dest_cfg: CSCN can be send to either DPIO or DPCON WQ channel -+ * @options: Mask of available options; use 'DPNI_CONG_OPT_' values -+ */ -+ -+struct dpni_congestion_notification_cfg { -+ enum dpni_congestion_unit units; -+ uint32_t threshold_entry; -+ uint32_t threshold_exit; -+ uint64_t message_ctx; -+ uint64_t message_iova; -+ struct dpni_dest_cfg dest_cfg; -+ uint16_t options; -+}; -+ -+/** -+ * dpni_set_rx_tc_congestion_notification() - Set Rx traffic class congestion -+ * notification configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @cfg: congestion notification configuration -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_set_rx_tc_congestion_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ const struct dpni_congestion_notification_cfg *cfg); -+ -+/** -+ * dpni_get_rx_tc_congestion_notification() - Get Rx traffic class congestion -+ * notification configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @cfg: congestion notification configuration -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_get_rx_tc_congestion_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ struct dpni_congestion_notification_cfg *cfg); -+ -+/** -+ * dpni_set_tx_tc_congestion_notification() - Set Tx traffic class congestion -+ * notification configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @cfg: congestion notification configuration -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_set_tx_tc_congestion_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ const struct dpni_congestion_notification_cfg *cfg); -+ -+/** -+ * dpni_get_tx_tc_congestion_notification() - Get Tx traffic class congestion -+ * notification configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @cfg: congestion notification configuration -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_get_tx_tc_congestion_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ struct dpni_congestion_notification_cfg *cfg); -+ -+/** -+ * enum dpni_flc_type - DPNI FLC types -+ * @DPNI_FLC_USER_DEFINED: select the FLC to be used for user defined value -+ * @DPNI_FLC_STASH: select the FLC to be used for stash control -+ */ -+enum dpni_flc_type { -+ DPNI_FLC_USER_DEFINED = 0, -+ DPNI_FLC_STASH = 1, -+}; -+ -+/** -+ * enum dpni_stash_size - DPNI FLC stashing size -+ * @DPNI_STASH_SIZE_0B: no stash -+ * @DPNI_STASH_SIZE_64B: stashes 64 bytes -+ * @DPNI_STASH_SIZE_128B: stashes 128 bytes -+ * @DPNI_STASH_SIZE_192B: stashes 192 bytes -+ */ -+enum dpni_stash_size { -+ DPNI_STASH_SIZE_0B = 0, -+ DPNI_STASH_SIZE_64B = 1, -+ DPNI_STASH_SIZE_128B = 2, -+ DPNI_STASH_SIZE_192B = 3, -+}; -+ -+/* DPNI FLC stash options */ -+ -+/** -+ * stashes the whole annotation area (up to 192 bytes) -+ */ -+#define DPNI_FLC_STASH_FRAME_ANNOTATION 0x00000001 -+ -+/** -+ * struct dpni_flc_cfg - Structure representing DPNI FLC configuration -+ * @flc_type: FLC type -+ * @options: Mask of available options; -+ * use 'DPNI_FLC_STASH_' values -+ * @frame_data_size: Size of frame data to be stashed -+ * @flow_context_size: Size of flow context to be stashed -+ * @flow_context: 1. In case flc_type is 'DPNI_FLC_USER_DEFINED': -+ * this value will be provided in the frame descriptor -+ * (FD[FLC]) -+ * 2. In case flc_type is 'DPNI_FLC_STASH': -+ * this value will be I/O virtual address of the -+ * flow-context; -+ * Must be cacheline-aligned and DMA-able memory -+ */ -+struct dpni_flc_cfg { -+ enum dpni_flc_type flc_type; -+ uint32_t options; -+ enum dpni_stash_size frame_data_size; -+ enum dpni_stash_size flow_context_size; -+ uint64_t flow_context; -+}; -+ -+/** -+ * DPNI queue modification options -+ */ -+ -+/** -+ * Select to modify the user's context associated with the queue -+ */ -+#define DPNI_QUEUE_OPT_USER_CTX 0x00000001 -+/** -+ * Select to modify the queue's destination -+ */ -+#define DPNI_QUEUE_OPT_DEST 0x00000002 -+/** Select to modify the flow-context parameters; -+ * not applicable for Tx-conf/Err queues as the FD comes from the user -+ */ -+#define DPNI_QUEUE_OPT_FLC 0x00000004 -+/** -+ * Select to modify the queue's order preservation -+ */ -+#define DPNI_QUEUE_OPT_ORDER_PRESERVATION 0x00000008 -+/* Select to modify the queue's tail-drop threshold */ -+#define DPNI_QUEUE_OPT_TAILDROP_THRESHOLD 0x00000010 -+ -+/** -+ * struct dpni_queue_cfg - Structure representing queue configuration -+ * @options: Flags representing the suggested modifications to the queue; -+ * Use any combination of 'DPNI_QUEUE_OPT_' flags -+ * @user_ctx: User context value provided in the frame descriptor of each -+ * dequeued frame; valid only if 'DPNI_QUEUE_OPT_USER_CTX' -+ * is contained in 'options' -+ * @dest_cfg: Queue destination parameters; -+ * valid only if 'DPNI_QUEUE_OPT_DEST' is contained in 'options' -+ * @flc_cfg: Flow context configuration; in case the TC's distribution -+ * is either NONE or HASH the FLC's settings of flow#0 are used. -+ * in the case of FS (flow-steering) the flow's FLC settings -+ * are used. -+ * valid only if 'DPNI_QUEUE_OPT_FLC' is contained in 'options' -+ * @order_preservation_en: enable/disable order preservation; -+ * valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained -+ * in 'options' -+ * @tail_drop_threshold: set the queue's tail drop threshold in bytes; -+ * '0' value disable the threshold; maximum value is 0xE000000; -+ * valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is contained -+ * in 'options' -+ */ -+struct dpni_queue_cfg { -+ uint32_t options; -+ uint64_t user_ctx; -+ struct dpni_dest_cfg dest_cfg; -+ struct dpni_flc_cfg flc_cfg; -+ int order_preservation_en; -+ uint32_t tail_drop_threshold; -+}; -+ -+/** -+ * struct dpni_queue_attr - Structure representing queue attributes -+ * @user_ctx: User context value provided in the frame descriptor of each -+ * dequeued frame -+ * @dest_cfg: Queue destination configuration -+ * @flc_cfg: Flow context configuration -+ * @order_preservation_en: enable/disable order preservation -+ * @tail_drop_threshold: queue's tail drop threshold in bytes; -+ * @fqid: Virtual fqid value to be used for dequeue operations -+ */ -+struct dpni_queue_attr { -+ uint64_t user_ctx; -+ struct dpni_dest_cfg dest_cfg; -+ struct dpni_flc_cfg flc_cfg; -+ int order_preservation_en; -+ uint32_t tail_drop_threshold; -+ -+ uint32_t fqid; -+}; -+ -+/** -+ * DPNI Tx flow modification options -+ */ -+ -+/** -+ * Select to modify the settings for dedicate Tx confirmation/error -+ */ -+#define DPNI_TX_FLOW_OPT_TX_CONF_ERROR 0x00000001 -+/** -+ * Select to modify the L3 checksum generation setting -+ */ -+#define DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN 0x00000010 -+/** -+ * Select to modify the L4 checksum generation setting -+ */ -+#define DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN 0x00000020 -+ -+/** -+ * struct dpni_tx_flow_cfg - Structure representing Tx flow configuration -+ * @options: Flags representing the suggested modifications to the Tx flow; -+ * Use any combination 'DPNI_TX_FLOW_OPT_' flags -+ * @use_common_tx_conf_queue: Set to '1' to use the common (default) Tx -+ * confirmation and error queue; Set to '0' to use the private -+ * Tx confirmation and error queue; valid only if -+ * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' wasn't set at DPNI creation -+ * and 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in 'options' -+ * @l3_chksum_gen: Set to '1' to enable L3 checksum generation; '0' to disable; -+ * valid only if 'DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN' is contained in 'options' -+ * @l4_chksum_gen: Set to '1' to enable L4 checksum generation; '0' to disable; -+ * valid only if 'DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN' is contained in 'options' -+ */ -+struct dpni_tx_flow_cfg { -+ uint32_t options; -+ int use_common_tx_conf_queue; -+ int l3_chksum_gen; -+ int l4_chksum_gen; -+}; -+ -+/** -+ * dpni_set_tx_flow() - Set Tx flow configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @flow_id: Provides (or returns) the sender's flow ID; -+ * for each new sender set (*flow_id) to 'DPNI_NEW_FLOW_ID' to generate -+ * a new flow_id; this ID should be used as the QDBIN argument -+ * in enqueue operations -+ * @cfg: Tx flow configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_tx_flow(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *flow_id, -+ const struct dpni_tx_flow_cfg *cfg); -+ -+/** -+ * struct dpni_tx_flow_attr - Structure representing Tx flow attributes -+ * @use_common_tx_conf_queue: '1' if using common (default) Tx confirmation and -+ * error queue; '0' if using private Tx confirmation and error queue -+ * @l3_chksum_gen: '1' if L3 checksum generation is enabled; '0' if disabled -+ * @l4_chksum_gen: '1' if L4 checksum generation is enabled; '0' if disabled -+ */ -+struct dpni_tx_flow_attr { -+ int use_common_tx_conf_queue; -+ int l3_chksum_gen; -+ int l4_chksum_gen; -+}; -+ -+/** -+ * dpni_get_tx_flow() - Get Tx flow attributes -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @flow_id: The sender's flow ID, as returned by the -+ * dpni_set_tx_flow() function -+ * @attr: Returned Tx flow attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_tx_flow(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t flow_id, -+ struct dpni_tx_flow_attr *attr); -+ -+/** -+ * struct dpni_tx_conf_cfg - Structure representing Tx conf configuration -+ * @errors_only: Set to '1' to report back only error frames; -+ * Set to '0' to confirm transmission/error for all transmitted frames; -+ * @queue_cfg: Queue configuration -+ */ -+struct dpni_tx_conf_cfg { -+ int errors_only; -+ struct dpni_queue_cfg queue_cfg; -+}; -+ -+/** -+ * dpni_set_tx_conf() - Set Tx confirmation and error queue configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @flow_id: The sender's flow ID, as returned by the -+ * dpni_set_tx_flow() function; -+ * use 'DPNI_COMMON_TX_CONF' for common tx-conf -+ * @cfg: Queue configuration -+ * -+ * If either 'DPNI_OPT_TX_CONF_DISABLED' or -+ * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation, -+ * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF'; -+ * i.e. only serve the common tx-conf-err queue; -+ * if 'DPNI_OPT_TX_CONF_DISABLED' was selected, only error frames are reported -+ * back - successfully transmitted frames are not confirmed. Otherwise, all -+ * transmitted frames are sent for confirmation. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_tx_conf(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t flow_id, -+ const struct dpni_tx_conf_cfg *cfg); -+ -+/** -+ * struct dpni_tx_conf_attr - Structure representing Tx conf attributes -+ * @errors_only: '1' if only error frames are reported back; '0' if all -+ * transmitted frames are confirmed -+ * @queue_attr: Queue attributes -+ */ -+struct dpni_tx_conf_attr { -+ int errors_only; -+ struct dpni_queue_attr queue_attr; -+}; -+ -+/** -+ * dpni_get_tx_conf() - Get Tx confirmation and error queue attributes -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @flow_id: The sender's flow ID, as returned by the -+ * dpni_set_tx_flow() function; -+ * use 'DPNI_COMMON_TX_CONF' for common tx-conf -+ * @attr: Returned tx-conf attributes -+ * -+ * If either 'DPNI_OPT_TX_CONF_DISABLED' or -+ * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation, -+ * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF'; -+ * i.e. only serve the common tx-conf-err queue; -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_tx_conf(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t flow_id, -+ struct dpni_tx_conf_attr *attr); -+ -+/** -+ * dpni_set_tx_conf_congestion_notification() - Set Tx conf congestion -+ * notification configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @flow_id: The sender's flow ID, as returned by the -+ * dpni_set_tx_flow() function; -+ * use 'DPNI_COMMON_TX_CONF' for common tx-conf -+ * @cfg: congestion notification configuration -+ * -+ * If either 'DPNI_OPT_TX_CONF_DISABLED' or -+ * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation, -+ * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF'; -+ * i.e. only serve the common tx-conf-err queue; -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_set_tx_conf_congestion_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t flow_id, -+ const struct dpni_congestion_notification_cfg *cfg); -+ -+/** -+ * dpni_get_tx_conf_congestion_notification() - Get Tx conf congestion -+ * notification configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @flow_id: The sender's flow ID, as returned by the -+ * dpni_set_tx_flow() function; -+ * use 'DPNI_COMMON_TX_CONF' for common tx-conf -+ * @cfg: congestion notification -+ * -+ * If either 'DPNI_OPT_TX_CONF_DISABLED' or -+ * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation, -+ * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF'; -+ * i.e. only serve the common tx-conf-err queue; -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpni_get_tx_conf_congestion_notification(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t flow_id, -+ struct dpni_congestion_notification_cfg *cfg); -+ -+/** -+ * dpni_set_tx_conf_revoke() - Tx confirmation revocation -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @revoke: revoke or not -+ * -+ * This function is useful only when 'DPNI_OPT_TX_CONF_DISABLED' is not -+ * selected at DPNI creation. -+ * Calling this function with 'revoke' set to '1' disables all transmit -+ * confirmation (including the private confirmation queues), regardless of -+ * previous settings; Note that in this case, Tx error frames are still -+ * enqueued to the general transmit errors queue. -+ * Calling this function with 'revoke' set to '0' restores the previous -+ * settings for both general and private transmit confirmation. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_tx_conf_revoke(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int revoke); -+ -+/** -+ * dpni_set_rx_flow() - Set Rx flow configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7); -+ * use 'DPNI_ALL_TCS' to set all TCs and all flows -+ * @flow_id: Rx flow id within the traffic class; use -+ * 'DPNI_ALL_TC_FLOWS' to set all flows within -+ * this tc_id; ignored if tc_id is set to -+ * 'DPNI_ALL_TCS'; -+ * @cfg: Rx flow configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_rx_flow(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ uint16_t flow_id, -+ const struct dpni_queue_cfg *cfg); -+ -+/** -+ * dpni_get_rx_flow() - Get Rx flow attributes -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @flow_id: Rx flow id within the traffic class -+ * @attr: Returned Rx flow attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_rx_flow(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ uint16_t flow_id, -+ struct dpni_queue_attr *attr); -+ -+/** -+ * dpni_set_rx_err_queue() - Set Rx error queue configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @cfg: Queue configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_rx_err_queue(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_queue_cfg *cfg); -+ -+/** -+ * dpni_get_rx_err_queue() - Get Rx error queue attributes -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @attr: Returned Queue attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_get_rx_err_queue(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpni_queue_attr *attr); -+ -+/** -+ * struct dpni_qos_tbl_cfg - Structure representing QOS table configuration -+ * @key_cfg_iova: I/O virtual address of 256 bytes DMA-able memory filled with -+ * key extractions to be used as the QoS criteria by calling -+ * dpni_prepare_key_cfg() -+ * @discard_on_miss: Set to '1' to discard frames in case of no match (miss); -+ * '0' to use the 'default_tc' in such cases -+ * @default_tc: Used in case of no-match and 'discard_on_miss'= 0 -+ */ -+struct dpni_qos_tbl_cfg { -+ uint64_t key_cfg_iova; -+ int discard_on_miss; -+ uint8_t default_tc; -+}; -+ -+/** -+ * dpni_set_qos_table() - Set QoS mapping table -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @cfg: QoS table configuration -+ * -+ * This function and all QoS-related functions require that -+ *'max_tcs > 1' was set at DPNI creation. -+ * -+ * warning: Before calling this function, call dpni_prepare_key_cfg() to -+ * prepare the key_cfg_iova parameter -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_qos_table(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_qos_tbl_cfg *cfg); -+ -+/** -+ * struct dpni_rule_cfg - Rule configuration for table lookup -+ * @key_iova: I/O virtual address of the key (must be in DMA-able memory) -+ * @mask_iova: I/O virtual address of the mask (must be in DMA-able memory) -+ * @key_size: key and mask size (in bytes) -+ */ -+struct dpni_rule_cfg { -+ uint64_t key_iova; -+ uint64_t mask_iova; -+ uint8_t key_size; -+}; -+ -+/** -+ * dpni_add_qos_entry() - Add QoS mapping entry (to select a traffic class) -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @cfg: QoS rule to add -+ * @tc_id: Traffic class selection (0-7) -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_add_qos_entry(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_rule_cfg *cfg, -+ uint8_t tc_id); -+ -+/** -+ * dpni_remove_qos_entry() - Remove QoS mapping entry -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @cfg: QoS rule to remove -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_remove_qos_entry(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpni_rule_cfg *cfg); -+ -+/** -+ * dpni_clear_qos_table() - Clear all QoS mapping entries -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * -+ * Following this function call, all frames are directed to -+ * the default traffic class (0) -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_clear_qos_table(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpni_add_fs_entry() - Add Flow Steering entry for a specific traffic class -+ * (to select a flow ID) -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @cfg: Flow steering rule to add -+ * @flow_id: Flow id selection (must be smaller than the -+ * distribution size of the traffic class) -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_add_fs_entry(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ const struct dpni_rule_cfg *cfg, -+ uint16_t flow_id); -+ -+/** -+ * dpni_remove_fs_entry() - Remove Flow Steering entry from a specific -+ * traffic class -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * @cfg: Flow steering rule to remove -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_remove_fs_entry(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id, -+ const struct dpni_rule_cfg *cfg); -+ -+/** -+ * dpni_clear_fs_entries() - Clear all Flow Steering entries of a specific -+ * traffic class -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @tc_id: Traffic class selection (0-7) -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_clear_fs_entries(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t tc_id); -+ -+/** -+ * dpni_set_vlan_insertion() - Enable/disable VLAN insertion for egress frames -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Set to '1' to enable; '0' to disable -+ * -+ * Requires that the 'DPNI_OPT_VLAN_MANIPULATION' option is set -+ * at DPNI creation. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_vlan_insertion(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en); -+ -+/** -+ * dpni_set_vlan_removal() - Enable/disable VLAN removal for ingress frames -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Set to '1' to enable; '0' to disable -+ * -+ * Requires that the 'DPNI_OPT_VLAN_MANIPULATION' option is set -+ * at DPNI creation. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_vlan_removal(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en); -+ -+/** -+ * dpni_set_ipr() - Enable/disable IP reassembly of ingress frames -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Set to '1' to enable; '0' to disable -+ * -+ * Requires that the 'DPNI_OPT_IPR' option is set at DPNI creation. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_ipr(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en); -+ -+/** -+ * dpni_set_ipf() - Enable/disable IP fragmentation of egress frames -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPNI object -+ * @en: Set to '1' to enable; '0' to disable -+ * -+ * Requires that the 'DPNI_OPT_IPF' option is set at DPNI -+ * creation. Fragmentation is performed according to MTU value -+ * set by dpni_set_mtu() function -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpni_set_ipf(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int en); -+ -+#endif /* __FSL_DPNI_H */ ---- a/drivers/staging/fsl-mc/include/mc-cmd.h -+++ b/drivers/staging/fsl-mc/include/mc-cmd.h -@@ -103,8 +103,11 @@ enum mc_cmd_status { - #define MC_CMD_HDR_READ_FLAGS(_hdr) \ - ((u32)mc_dec((_hdr), MC_CMD_HDR_FLAGS_O, MC_CMD_HDR_FLAGS_S)) - -+#define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \ -+ ((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg))) -+ - #define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ -- ((_ext)[_param] |= mc_enc((_offset), (_width), _arg)) -+ (_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width))) - - #define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ - ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg)) ---- /dev/null -+++ b/drivers/staging/fsl-mc/include/net.h -@@ -0,0 +1,481 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef __FSL_NET_H -+#define __FSL_NET_H -+ -+#define LAST_HDR_INDEX 0xFFFFFFFF -+ -+/*****************************************************************************/ -+/* Protocol fields */ -+/*****************************************************************************/ -+ -+/************************* Ethernet fields *********************************/ -+#define NH_FLD_ETH_DA (1) -+#define NH_FLD_ETH_SA (NH_FLD_ETH_DA << 1) -+#define NH_FLD_ETH_LENGTH (NH_FLD_ETH_DA << 2) -+#define NH_FLD_ETH_TYPE (NH_FLD_ETH_DA << 3) -+#define NH_FLD_ETH_FINAL_CKSUM (NH_FLD_ETH_DA << 4) -+#define NH_FLD_ETH_PADDING (NH_FLD_ETH_DA << 5) -+#define NH_FLD_ETH_ALL_FIELDS ((NH_FLD_ETH_DA << 6) - 1) -+ -+#define NH_FLD_ETH_ADDR_SIZE 6 -+ -+/*************************** VLAN fields ***********************************/ -+#define NH_FLD_VLAN_VPRI (1) -+#define NH_FLD_VLAN_CFI (NH_FLD_VLAN_VPRI << 1) -+#define NH_FLD_VLAN_VID (NH_FLD_VLAN_VPRI << 2) -+#define NH_FLD_VLAN_LENGTH (NH_FLD_VLAN_VPRI << 3) -+#define NH_FLD_VLAN_TYPE (NH_FLD_VLAN_VPRI << 4) -+#define NH_FLD_VLAN_ALL_FIELDS ((NH_FLD_VLAN_VPRI << 5) - 1) -+ -+#define NH_FLD_VLAN_TCI (NH_FLD_VLAN_VPRI | \ -+ NH_FLD_VLAN_CFI | \ -+ NH_FLD_VLAN_VID) -+ -+/************************ IP (generic) fields ******************************/ -+#define NH_FLD_IP_VER (1) -+#define NH_FLD_IP_DSCP (NH_FLD_IP_VER << 2) -+#define NH_FLD_IP_ECN (NH_FLD_IP_VER << 3) -+#define NH_FLD_IP_PROTO (NH_FLD_IP_VER << 4) -+#define NH_FLD_IP_SRC (NH_FLD_IP_VER << 5) -+#define NH_FLD_IP_DST (NH_FLD_IP_VER << 6) -+#define NH_FLD_IP_TOS_TC (NH_FLD_IP_VER << 7) -+#define NH_FLD_IP_ID (NH_FLD_IP_VER << 8) -+#define NH_FLD_IP_ALL_FIELDS ((NH_FLD_IP_VER << 9) - 1) -+ -+#define NH_FLD_IP_PROTO_SIZE 1 -+ -+/***************************** IPV4 fields *********************************/ -+#define NH_FLD_IPV4_VER (1) -+#define NH_FLD_IPV4_HDR_LEN (NH_FLD_IPV4_VER << 1) -+#define NH_FLD_IPV4_TOS (NH_FLD_IPV4_VER << 2) -+#define NH_FLD_IPV4_TOTAL_LEN (NH_FLD_IPV4_VER << 3) -+#define NH_FLD_IPV4_ID (NH_FLD_IPV4_VER << 4) -+#define NH_FLD_IPV4_FLAG_D (NH_FLD_IPV4_VER << 5) -+#define NH_FLD_IPV4_FLAG_M (NH_FLD_IPV4_VER << 6) -+#define NH_FLD_IPV4_OFFSET (NH_FLD_IPV4_VER << 7) -+#define NH_FLD_IPV4_TTL (NH_FLD_IPV4_VER << 8) -+#define NH_FLD_IPV4_PROTO (NH_FLD_IPV4_VER << 9) -+#define NH_FLD_IPV4_CKSUM (NH_FLD_IPV4_VER << 10) -+#define NH_FLD_IPV4_SRC_IP (NH_FLD_IPV4_VER << 11) -+#define NH_FLD_IPV4_DST_IP (NH_FLD_IPV4_VER << 12) -+#define NH_FLD_IPV4_OPTS (NH_FLD_IPV4_VER << 13) -+#define NH_FLD_IPV4_OPTS_COUNT (NH_FLD_IPV4_VER << 14) -+#define NH_FLD_IPV4_ALL_FIELDS ((NH_FLD_IPV4_VER << 15) - 1) -+ -+#define NH_FLD_IPV4_ADDR_SIZE 4 -+#define NH_FLD_IPV4_PROTO_SIZE 1 -+ -+/***************************** IPV6 fields *********************************/ -+#define NH_FLD_IPV6_VER (1) -+#define NH_FLD_IPV6_TC (NH_FLD_IPV6_VER << 1) -+#define NH_FLD_IPV6_SRC_IP (NH_FLD_IPV6_VER << 2) -+#define NH_FLD_IPV6_DST_IP (NH_FLD_IPV6_VER << 3) -+#define NH_FLD_IPV6_NEXT_HDR (NH_FLD_IPV6_VER << 4) -+#define NH_FLD_IPV6_FL (NH_FLD_IPV6_VER << 5) -+#define NH_FLD_IPV6_HOP_LIMIT (NH_FLD_IPV6_VER << 6) -+#define NH_FLD_IPV6_ID (NH_FLD_IPV6_VER << 7) -+#define NH_FLD_IPV6_ALL_FIELDS ((NH_FLD_IPV6_VER << 8) - 1) -+ -+#define NH_FLD_IPV6_ADDR_SIZE 16 -+#define NH_FLD_IPV6_NEXT_HDR_SIZE 1 -+ -+/***************************** ICMP fields *********************************/ -+#define NH_FLD_ICMP_TYPE (1) -+#define NH_FLD_ICMP_CODE (NH_FLD_ICMP_TYPE << 1) -+#define NH_FLD_ICMP_CKSUM (NH_FLD_ICMP_TYPE << 2) -+#define NH_FLD_ICMP_ID (NH_FLD_ICMP_TYPE << 3) -+#define NH_FLD_ICMP_SQ_NUM (NH_FLD_ICMP_TYPE << 4) -+#define NH_FLD_ICMP_ALL_FIELDS ((NH_FLD_ICMP_TYPE << 5) - 1) -+ -+#define NH_FLD_ICMP_CODE_SIZE 1 -+#define NH_FLD_ICMP_TYPE_SIZE 1 -+ -+/***************************** IGMP fields *********************************/ -+#define NH_FLD_IGMP_VERSION (1) -+#define NH_FLD_IGMP_TYPE (NH_FLD_IGMP_VERSION << 1) -+#define NH_FLD_IGMP_CKSUM (NH_FLD_IGMP_VERSION << 2) -+#define NH_FLD_IGMP_DATA (NH_FLD_IGMP_VERSION << 3) -+#define NH_FLD_IGMP_ALL_FIELDS ((NH_FLD_IGMP_VERSION << 4) - 1) -+ -+/***************************** TCP fields **********************************/ -+#define NH_FLD_TCP_PORT_SRC (1) -+#define NH_FLD_TCP_PORT_DST (NH_FLD_TCP_PORT_SRC << 1) -+#define NH_FLD_TCP_SEQ (NH_FLD_TCP_PORT_SRC << 2) -+#define NH_FLD_TCP_ACK (NH_FLD_TCP_PORT_SRC << 3) -+#define NH_FLD_TCP_OFFSET (NH_FLD_TCP_PORT_SRC << 4) -+#define NH_FLD_TCP_FLAGS (NH_FLD_TCP_PORT_SRC << 5) -+#define NH_FLD_TCP_WINDOW (NH_FLD_TCP_PORT_SRC << 6) -+#define NH_FLD_TCP_CKSUM (NH_FLD_TCP_PORT_SRC << 7) -+#define NH_FLD_TCP_URGPTR (NH_FLD_TCP_PORT_SRC << 8) -+#define NH_FLD_TCP_OPTS (NH_FLD_TCP_PORT_SRC << 9) -+#define NH_FLD_TCP_OPTS_COUNT (NH_FLD_TCP_PORT_SRC << 10) -+#define NH_FLD_TCP_ALL_FIELDS ((NH_FLD_TCP_PORT_SRC << 11) - 1) -+ -+#define NH_FLD_TCP_PORT_SIZE 2 -+ -+/***************************** UDP fields **********************************/ -+#define NH_FLD_UDP_PORT_SRC (1) -+#define NH_FLD_UDP_PORT_DST (NH_FLD_UDP_PORT_SRC << 1) -+#define NH_FLD_UDP_LEN (NH_FLD_UDP_PORT_SRC << 2) -+#define NH_FLD_UDP_CKSUM (NH_FLD_UDP_PORT_SRC << 3) -+#define NH_FLD_UDP_ALL_FIELDS ((NH_FLD_UDP_PORT_SRC << 4) - 1) -+ -+#define NH_FLD_UDP_PORT_SIZE 2 -+ -+/*************************** UDP-lite fields *******************************/ -+#define NH_FLD_UDP_LITE_PORT_SRC (1) -+#define NH_FLD_UDP_LITE_PORT_DST (NH_FLD_UDP_LITE_PORT_SRC << 1) -+#define NH_FLD_UDP_LITE_ALL_FIELDS \ -+ ((NH_FLD_UDP_LITE_PORT_SRC << 2) - 1) -+ -+#define NH_FLD_UDP_LITE_PORT_SIZE 2 -+ -+/*************************** UDP-encap-ESP fields **************************/ -+#define NH_FLD_UDP_ENC_ESP_PORT_SRC (1) -+#define NH_FLD_UDP_ENC_ESP_PORT_DST (NH_FLD_UDP_ENC_ESP_PORT_SRC << 1) -+#define NH_FLD_UDP_ENC_ESP_LEN (NH_FLD_UDP_ENC_ESP_PORT_SRC << 2) -+#define NH_FLD_UDP_ENC_ESP_CKSUM (NH_FLD_UDP_ENC_ESP_PORT_SRC << 3) -+#define NH_FLD_UDP_ENC_ESP_SPI (NH_FLD_UDP_ENC_ESP_PORT_SRC << 4) -+#define NH_FLD_UDP_ENC_ESP_SEQUENCE_NUM (NH_FLD_UDP_ENC_ESP_PORT_SRC << 5) -+#define NH_FLD_UDP_ENC_ESP_ALL_FIELDS \ -+ ((NH_FLD_UDP_ENC_ESP_PORT_SRC << 6) - 1) -+ -+#define NH_FLD_UDP_ENC_ESP_PORT_SIZE 2 -+#define NH_FLD_UDP_ENC_ESP_SPI_SIZE 4 -+ -+/***************************** SCTP fields *********************************/ -+#define NH_FLD_SCTP_PORT_SRC (1) -+#define NH_FLD_SCTP_PORT_DST (NH_FLD_SCTP_PORT_SRC << 1) -+#define NH_FLD_SCTP_VER_TAG (NH_FLD_SCTP_PORT_SRC << 2) -+#define NH_FLD_SCTP_CKSUM (NH_FLD_SCTP_PORT_SRC << 3) -+#define NH_FLD_SCTP_ALL_FIELDS ((NH_FLD_SCTP_PORT_SRC << 4) - 1) -+ -+#define NH_FLD_SCTP_PORT_SIZE 2 -+ -+/***************************** DCCP fields *********************************/ -+#define NH_FLD_DCCP_PORT_SRC (1) -+#define NH_FLD_DCCP_PORT_DST (NH_FLD_DCCP_PORT_SRC << 1) -+#define NH_FLD_DCCP_ALL_FIELDS ((NH_FLD_DCCP_PORT_SRC << 2) - 1) -+ -+#define NH_FLD_DCCP_PORT_SIZE 2 -+ -+/***************************** IPHC fields *********************************/ -+#define NH_FLD_IPHC_CID (1) -+#define NH_FLD_IPHC_CID_TYPE (NH_FLD_IPHC_CID << 1) -+#define NH_FLD_IPHC_HCINDEX (NH_FLD_IPHC_CID << 2) -+#define NH_FLD_IPHC_GEN (NH_FLD_IPHC_CID << 3) -+#define NH_FLD_IPHC_D_BIT (NH_FLD_IPHC_CID << 4) -+#define NH_FLD_IPHC_ALL_FIELDS ((NH_FLD_IPHC_CID << 5) - 1) -+ -+/***************************** SCTP fields *********************************/ -+#define NH_FLD_SCTP_CHUNK_DATA_TYPE (1) -+#define NH_FLD_SCTP_CHUNK_DATA_FLAGS (NH_FLD_SCTP_CHUNK_DATA_TYPE << 1) -+#define NH_FLD_SCTP_CHUNK_DATA_LENGTH (NH_FLD_SCTP_CHUNK_DATA_TYPE << 2) -+#define NH_FLD_SCTP_CHUNK_DATA_TSN (NH_FLD_SCTP_CHUNK_DATA_TYPE << 3) -+#define NH_FLD_SCTP_CHUNK_DATA_STREAM_ID (NH_FLD_SCTP_CHUNK_DATA_TYPE << 4) -+#define NH_FLD_SCTP_CHUNK_DATA_STREAM_SQN (NH_FLD_SCTP_CHUNK_DATA_TYPE << 5) -+#define NH_FLD_SCTP_CHUNK_DATA_PAYLOAD_PID (NH_FLD_SCTP_CHUNK_DATA_TYPE << 6) -+#define NH_FLD_SCTP_CHUNK_DATA_UNORDERED (NH_FLD_SCTP_CHUNK_DATA_TYPE << 7) -+#define NH_FLD_SCTP_CHUNK_DATA_BEGGINING (NH_FLD_SCTP_CHUNK_DATA_TYPE << 8) -+#define NH_FLD_SCTP_CHUNK_DATA_END (NH_FLD_SCTP_CHUNK_DATA_TYPE << 9) -+#define NH_FLD_SCTP_CHUNK_DATA_ALL_FIELDS \ -+ ((NH_FLD_SCTP_CHUNK_DATA_TYPE << 10) - 1) -+ -+/*************************** L2TPV2 fields *********************************/ -+#define NH_FLD_L2TPV2_TYPE_BIT (1) -+#define NH_FLD_L2TPV2_LENGTH_BIT (NH_FLD_L2TPV2_TYPE_BIT << 1) -+#define NH_FLD_L2TPV2_SEQUENCE_BIT (NH_FLD_L2TPV2_TYPE_BIT << 2) -+#define NH_FLD_L2TPV2_OFFSET_BIT (NH_FLD_L2TPV2_TYPE_BIT << 3) -+#define NH_FLD_L2TPV2_PRIORITY_BIT (NH_FLD_L2TPV2_TYPE_BIT << 4) -+#define NH_FLD_L2TPV2_VERSION (NH_FLD_L2TPV2_TYPE_BIT << 5) -+#define NH_FLD_L2TPV2_LEN (NH_FLD_L2TPV2_TYPE_BIT << 6) -+#define NH_FLD_L2TPV2_TUNNEL_ID (NH_FLD_L2TPV2_TYPE_BIT << 7) -+#define NH_FLD_L2TPV2_SESSION_ID (NH_FLD_L2TPV2_TYPE_BIT << 8) -+#define NH_FLD_L2TPV2_NS (NH_FLD_L2TPV2_TYPE_BIT << 9) -+#define NH_FLD_L2TPV2_NR (NH_FLD_L2TPV2_TYPE_BIT << 10) -+#define NH_FLD_L2TPV2_OFFSET_SIZE (NH_FLD_L2TPV2_TYPE_BIT << 11) -+#define NH_FLD_L2TPV2_FIRST_BYTE (NH_FLD_L2TPV2_TYPE_BIT << 12) -+#define NH_FLD_L2TPV2_ALL_FIELDS \ -+ ((NH_FLD_L2TPV2_TYPE_BIT << 13) - 1) -+ -+/*************************** L2TPV3 fields *********************************/ -+#define NH_FLD_L2TPV3_CTRL_TYPE_BIT (1) -+#define NH_FLD_L2TPV3_CTRL_LENGTH_BIT (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 1) -+#define NH_FLD_L2TPV3_CTRL_SEQUENCE_BIT (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 2) -+#define NH_FLD_L2TPV3_CTRL_VERSION (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 3) -+#define NH_FLD_L2TPV3_CTRL_LENGTH (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 4) -+#define NH_FLD_L2TPV3_CTRL_CONTROL (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 5) -+#define NH_FLD_L2TPV3_CTRL_SENT (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 6) -+#define NH_FLD_L2TPV3_CTRL_RECV (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 7) -+#define NH_FLD_L2TPV3_CTRL_FIRST_BYTE (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 8) -+#define NH_FLD_L2TPV3_CTRL_ALL_FIELDS \ -+ ((NH_FLD_L2TPV3_CTRL_TYPE_BIT << 9) - 1) -+ -+#define NH_FLD_L2TPV3_SESS_TYPE_BIT (1) -+#define NH_FLD_L2TPV3_SESS_VERSION (NH_FLD_L2TPV3_SESS_TYPE_BIT << 1) -+#define NH_FLD_L2TPV3_SESS_ID (NH_FLD_L2TPV3_SESS_TYPE_BIT << 2) -+#define NH_FLD_L2TPV3_SESS_COOKIE (NH_FLD_L2TPV3_SESS_TYPE_BIT << 3) -+#define NH_FLD_L2TPV3_SESS_ALL_FIELDS \ -+ ((NH_FLD_L2TPV3_SESS_TYPE_BIT << 4) - 1) -+ -+/**************************** PPP fields ***********************************/ -+#define NH_FLD_PPP_PID (1) -+#define NH_FLD_PPP_COMPRESSED (NH_FLD_PPP_PID << 1) -+#define NH_FLD_PPP_ALL_FIELDS ((NH_FLD_PPP_PID << 2) - 1) -+ -+/************************** PPPoE fields ***********************************/ -+#define NH_FLD_PPPOE_VER (1) -+#define NH_FLD_PPPOE_TYPE (NH_FLD_PPPOE_VER << 1) -+#define NH_FLD_PPPOE_CODE (NH_FLD_PPPOE_VER << 2) -+#define NH_FLD_PPPOE_SID (NH_FLD_PPPOE_VER << 3) -+#define NH_FLD_PPPOE_LEN (NH_FLD_PPPOE_VER << 4) -+#define NH_FLD_PPPOE_SESSION (NH_FLD_PPPOE_VER << 5) -+#define NH_FLD_PPPOE_PID (NH_FLD_PPPOE_VER << 6) -+#define NH_FLD_PPPOE_ALL_FIELDS ((NH_FLD_PPPOE_VER << 7) - 1) -+ -+/************************* PPP-Mux fields **********************************/ -+#define NH_FLD_PPPMUX_PID (1) -+#define NH_FLD_PPPMUX_CKSUM (NH_FLD_PPPMUX_PID << 1) -+#define NH_FLD_PPPMUX_COMPRESSED (NH_FLD_PPPMUX_PID << 2) -+#define NH_FLD_PPPMUX_ALL_FIELDS ((NH_FLD_PPPMUX_PID << 3) - 1) -+ -+/*********************** PPP-Mux sub-frame fields **************************/ -+#define NH_FLD_PPPMUX_SUBFRM_PFF (1) -+#define NH_FLD_PPPMUX_SUBFRM_LXT (NH_FLD_PPPMUX_SUBFRM_PFF << 1) -+#define NH_FLD_PPPMUX_SUBFRM_LEN (NH_FLD_PPPMUX_SUBFRM_PFF << 2) -+#define NH_FLD_PPPMUX_SUBFRM_PID (NH_FLD_PPPMUX_SUBFRM_PFF << 3) -+#define NH_FLD_PPPMUX_SUBFRM_USE_PID (NH_FLD_PPPMUX_SUBFRM_PFF << 4) -+#define NH_FLD_PPPMUX_SUBFRM_ALL_FIELDS \ -+ ((NH_FLD_PPPMUX_SUBFRM_PFF << 5) - 1) -+ -+/*************************** LLC fields ************************************/ -+#define NH_FLD_LLC_DSAP (1) -+#define NH_FLD_LLC_SSAP (NH_FLD_LLC_DSAP << 1) -+#define NH_FLD_LLC_CTRL (NH_FLD_LLC_DSAP << 2) -+#define NH_FLD_LLC_ALL_FIELDS ((NH_FLD_LLC_DSAP << 3) - 1) -+ -+/*************************** NLPID fields **********************************/ -+#define NH_FLD_NLPID_NLPID (1) -+#define NH_FLD_NLPID_ALL_FIELDS ((NH_FLD_NLPID_NLPID << 1) - 1) -+ -+/*************************** SNAP fields ***********************************/ -+#define NH_FLD_SNAP_OUI (1) -+#define NH_FLD_SNAP_PID (NH_FLD_SNAP_OUI << 1) -+#define NH_FLD_SNAP_ALL_FIELDS ((NH_FLD_SNAP_OUI << 2) - 1) -+ -+/*************************** LLC SNAP fields *******************************/ -+#define NH_FLD_LLC_SNAP_TYPE (1) -+#define NH_FLD_LLC_SNAP_ALL_FIELDS ((NH_FLD_LLC_SNAP_TYPE << 1) - 1) -+ -+#define NH_FLD_ARP_HTYPE (1) -+#define NH_FLD_ARP_PTYPE (NH_FLD_ARP_HTYPE << 1) -+#define NH_FLD_ARP_HLEN (NH_FLD_ARP_HTYPE << 2) -+#define NH_FLD_ARP_PLEN (NH_FLD_ARP_HTYPE << 3) -+#define NH_FLD_ARP_OPER (NH_FLD_ARP_HTYPE << 4) -+#define NH_FLD_ARP_SHA (NH_FLD_ARP_HTYPE << 5) -+#define NH_FLD_ARP_SPA (NH_FLD_ARP_HTYPE << 6) -+#define NH_FLD_ARP_THA (NH_FLD_ARP_HTYPE << 7) -+#define NH_FLD_ARP_TPA (NH_FLD_ARP_HTYPE << 8) -+#define NH_FLD_ARP_ALL_FIELDS ((NH_FLD_ARP_HTYPE << 9) - 1) -+ -+/*************************** RFC2684 fields ********************************/ -+#define NH_FLD_RFC2684_LLC (1) -+#define NH_FLD_RFC2684_NLPID (NH_FLD_RFC2684_LLC << 1) -+#define NH_FLD_RFC2684_OUI (NH_FLD_RFC2684_LLC << 2) -+#define NH_FLD_RFC2684_PID (NH_FLD_RFC2684_LLC << 3) -+#define NH_FLD_RFC2684_VPN_OUI (NH_FLD_RFC2684_LLC << 4) -+#define NH_FLD_RFC2684_VPN_IDX (NH_FLD_RFC2684_LLC << 5) -+#define NH_FLD_RFC2684_ALL_FIELDS ((NH_FLD_RFC2684_LLC << 6) - 1) -+ -+/*************************** User defined fields ***************************/ -+#define NH_FLD_USER_DEFINED_SRCPORT (1) -+#define NH_FLD_USER_DEFINED_PCDID (NH_FLD_USER_DEFINED_SRCPORT << 1) -+#define NH_FLD_USER_DEFINED_ALL_FIELDS \ -+ ((NH_FLD_USER_DEFINED_SRCPORT << 2) - 1) -+ -+/*************************** Payload fields ********************************/ -+#define NH_FLD_PAYLOAD_BUFFER (1) -+#define NH_FLD_PAYLOAD_SIZE (NH_FLD_PAYLOAD_BUFFER << 1) -+#define NH_FLD_MAX_FRM_SIZE (NH_FLD_PAYLOAD_BUFFER << 2) -+#define NH_FLD_MIN_FRM_SIZE (NH_FLD_PAYLOAD_BUFFER << 3) -+#define NH_FLD_PAYLOAD_TYPE (NH_FLD_PAYLOAD_BUFFER << 4) -+#define NH_FLD_FRAME_SIZE (NH_FLD_PAYLOAD_BUFFER << 5) -+#define NH_FLD_PAYLOAD_ALL_FIELDS ((NH_FLD_PAYLOAD_BUFFER << 6) - 1) -+ -+/*************************** GRE fields ************************************/ -+#define NH_FLD_GRE_TYPE (1) -+#define NH_FLD_GRE_ALL_FIELDS ((NH_FLD_GRE_TYPE << 1) - 1) -+ -+/*************************** MINENCAP fields *******************************/ -+#define NH_FLD_MINENCAP_SRC_IP (1) -+#define NH_FLD_MINENCAP_DST_IP (NH_FLD_MINENCAP_SRC_IP << 1) -+#define NH_FLD_MINENCAP_TYPE (NH_FLD_MINENCAP_SRC_IP << 2) -+#define NH_FLD_MINENCAP_ALL_FIELDS \ -+ ((NH_FLD_MINENCAP_SRC_IP << 3) - 1) -+ -+/*************************** IPSEC AH fields *******************************/ -+#define NH_FLD_IPSEC_AH_SPI (1) -+#define NH_FLD_IPSEC_AH_NH (NH_FLD_IPSEC_AH_SPI << 1) -+#define NH_FLD_IPSEC_AH_ALL_FIELDS ((NH_FLD_IPSEC_AH_SPI << 2) - 1) -+ -+/*************************** IPSEC ESP fields ******************************/ -+#define NH_FLD_IPSEC_ESP_SPI (1) -+#define NH_FLD_IPSEC_ESP_SEQUENCE_NUM (NH_FLD_IPSEC_ESP_SPI << 1) -+#define NH_FLD_IPSEC_ESP_ALL_FIELDS ((NH_FLD_IPSEC_ESP_SPI << 2) - 1) -+ -+#define NH_FLD_IPSEC_ESP_SPI_SIZE 4 -+ -+/*************************** MPLS fields ***********************************/ -+#define NH_FLD_MPLS_LABEL_STACK (1) -+#define NH_FLD_MPLS_LABEL_STACK_ALL_FIELDS \ -+ ((NH_FLD_MPLS_LABEL_STACK << 1) - 1) -+ -+/*************************** MACSEC fields *********************************/ -+#define NH_FLD_MACSEC_SECTAG (1) -+#define NH_FLD_MACSEC_ALL_FIELDS ((NH_FLD_MACSEC_SECTAG << 1) - 1) -+ -+/*************************** GTP fields ************************************/ -+#define NH_FLD_GTP_TEID (1) -+ -+ -+/* Protocol options */ -+ -+/* Ethernet options */ -+#define NH_OPT_ETH_BROADCAST 1 -+#define NH_OPT_ETH_MULTICAST 2 -+#define NH_OPT_ETH_UNICAST 3 -+#define NH_OPT_ETH_BPDU 4 -+ -+#define NH_ETH_IS_MULTICAST_ADDR(addr) (addr[0] & 0x01) -+/* also applicable for broadcast */ -+ -+/* VLAN options */ -+#define NH_OPT_VLAN_CFI 1 -+ -+/* IPV4 options */ -+#define NH_OPT_IPV4_UNICAST 1 -+#define NH_OPT_IPV4_MULTICAST 2 -+#define NH_OPT_IPV4_BROADCAST 3 -+#define NH_OPT_IPV4_OPTION 4 -+#define NH_OPT_IPV4_FRAG 5 -+#define NH_OPT_IPV4_INITIAL_FRAG 6 -+ -+/* IPV6 options */ -+#define NH_OPT_IPV6_UNICAST 1 -+#define NH_OPT_IPV6_MULTICAST 2 -+#define NH_OPT_IPV6_OPTION 3 -+#define NH_OPT_IPV6_FRAG 4 -+#define NH_OPT_IPV6_INITIAL_FRAG 5 -+ -+/* General IP options (may be used for any version) */ -+#define NH_OPT_IP_FRAG 1 -+#define NH_OPT_IP_INITIAL_FRAG 2 -+#define NH_OPT_IP_OPTION 3 -+ -+/* Minenc. options */ -+#define NH_OPT_MINENCAP_SRC_ADDR_PRESENT 1 -+ -+/* GRE. options */ -+#define NH_OPT_GRE_ROUTING_PRESENT 1 -+ -+/* TCP options */ -+#define NH_OPT_TCP_OPTIONS 1 -+#define NH_OPT_TCP_CONTROL_HIGH_BITS 2 -+#define NH_OPT_TCP_CONTROL_LOW_BITS 3 -+ -+/* CAPWAP options */ -+#define NH_OPT_CAPWAP_DTLS 1 -+ -+enum net_prot { -+ NET_PROT_NONE = 0, -+ NET_PROT_PAYLOAD, -+ NET_PROT_ETH, -+ NET_PROT_VLAN, -+ NET_PROT_IPV4, -+ NET_PROT_IPV6, -+ NET_PROT_IP, -+ NET_PROT_TCP, -+ NET_PROT_UDP, -+ NET_PROT_UDP_LITE, -+ NET_PROT_IPHC, -+ NET_PROT_SCTP, -+ NET_PROT_SCTP_CHUNK_DATA, -+ NET_PROT_PPPOE, -+ NET_PROT_PPP, -+ NET_PROT_PPPMUX, -+ NET_PROT_PPPMUX_SUBFRM, -+ NET_PROT_L2TPV2, -+ NET_PROT_L2TPV3_CTRL, -+ NET_PROT_L2TPV3_SESS, -+ NET_PROT_LLC, -+ NET_PROT_LLC_SNAP, -+ NET_PROT_NLPID, -+ NET_PROT_SNAP, -+ NET_PROT_MPLS, -+ NET_PROT_IPSEC_AH, -+ NET_PROT_IPSEC_ESP, -+ NET_PROT_UDP_ENC_ESP, /* RFC 3948 */ -+ NET_PROT_MACSEC, -+ NET_PROT_GRE, -+ NET_PROT_MINENCAP, -+ NET_PROT_DCCP, -+ NET_PROT_ICMP, -+ NET_PROT_IGMP, -+ NET_PROT_ARP, -+ NET_PROT_CAPWAP_DATA, -+ NET_PROT_CAPWAP_CTRL, -+ NET_PROT_RFC2684, -+ NET_PROT_ICMPV6, -+ NET_PROT_FCOE, -+ NET_PROT_FIP, -+ NET_PROT_ISCSI, -+ NET_PROT_GTP, -+ NET_PROT_USER_DEFINED_L2, -+ NET_PROT_USER_DEFINED_L3, -+ NET_PROT_USER_DEFINED_L4, -+ NET_PROT_USER_DEFINED_L5, -+ NET_PROT_USER_DEFINED_SHIM1, -+ NET_PROT_USER_DEFINED_SHIM2, -+ -+ NET_PROT_DUMMY_LAST -+}; -+ -+/*! IEEE8021.Q */ -+#define NH_IEEE8021Q_ETYPE 0x8100 -+#define NH_IEEE8021Q_HDR(etype, pcp, dei, vlan_id) \ -+ ((((uint32_t)(etype & 0xFFFF)) << 16) | \ -+ (((uint32_t)(pcp & 0x07)) << 13) | \ -+ (((uint32_t)(dei & 0x01)) << 12) | \ -+ (((uint32_t)(vlan_id & 0xFFF)))) -+ -+#endif /* __FSL_NET_H */ ---- a/net/core/pktgen.c -+++ b/net/core/pktgen.c -@@ -2790,6 +2790,7 @@ static struct sk_buff *pktgen_alloc_skb( - } else { - skb = __netdev_alloc_skb(dev, size, GFP_NOWAIT); - } -+ skb_reserve(skb, LL_RESERVED_SPACE(dev)); - - /* the caller pre-fetches from skb->data and reserves for the mac hdr */ - if (likely(skb)) diff --git a/target/linux/layerscape/patches-4.4/7202-staging-fsl-dpaa2-eth-code-cleanup-for-upstreaming.patch b/target/linux/layerscape/patches-4.4/7202-staging-fsl-dpaa2-eth-code-cleanup-for-upstreaming.patch deleted file mode 100644 index d331b6600c..0000000000 --- a/target/linux/layerscape/patches-4.4/7202-staging-fsl-dpaa2-eth-code-cleanup-for-upstreaming.patch +++ /dev/null @@ -1,3257 +0,0 @@ -From 2a6f0dd5425cf43b8c09a8203e6ee64ba2b3868d Mon Sep 17 00:00:00 2001 -From: Bogdan Hamciuc -Date: Tue, 12 Jan 2016 08:58:40 +0200 -Subject: [PATCH 202/226] staging: fsl-dpaa2: eth: code cleanup for - upstreaming - --this is a squash of cleanup commits (see QLINUX-5338), all commit logs - are below - -Signed-off-by: Stuart Yoder - ---------------------------------------------------------------------- - -fsl-dpaa2: eth: Drain queues upon ifconfig down - -MC firmware assists in draining the Tx FQs; the Eth driver flushes the -Rx and TxConfirm queues then empties the buffer pool. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: eth: Don't use magic numbers - -Add a define to avoid mentioning directly the maximum number -of buffers released/acquired through a single QBMan command. - -Signed-off-by: Ioana Radulescu - -dpaa2-eth: Remove cpumask_rr macro - -It's only used in one place and not very intuitive - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Rename a variable - -The old name was a leftover and non-intuitive. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Rearrange code - -Rearrange the conditional statements in several functions -to avoid excessive indenting, with no change in functionality. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Remove incorrect check - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Fix bug on error path - -We were not doing a DMA unmap on the error path of dpaa2_dpni_setup. -Reorganize the code a bit to avoid this. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Error messages cleanup - -This commit cleans up and improves uniformity of messages on -error paths throughout the Ethernet driver: - -* don't use WARN/WARN_ON/WARN_ONCE for warning messages, as -we don't need a stack dump -* give up using the DPAA2_ETH_WARN_IF_ERR custom macro -* ensure dev_err and netdev_err are each used where needed and -not randomly -* remove error messages on memory allocation failures; the kernel -is quite capable of dumping a detailed message when that happens -* remove error messages on the fast path; we don't want to flood -the console and we already increment counters in most error cases -* ratelimit error messages where appropriate - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Fix name of ethtool counters - -Rename counters in ethtool -S from "portal busy" to "dequeue portal -busy" and from "tx portal busy" to "enqueue portal busy", so it's -less confusing for the user. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Retry DAN rearm if portal busy - -There's a chance the data available notification rearming will -fail if the QBMan portal is busy. Keep retrying until portal -becomes available again, like we do for buffer release and -pull dequeue operations. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Add cpu_relax() to portal busy loops - -For several DPIO operations, we may need to repeatedly try -until the QBMan portal is no longer busy. Add a cpu_relax() to -those loops, like we were already doing when seeding buffers. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Add a counter for channel pull errors - -We no longer print an error message in this case, so add an error -counter so we can at least know something went wrong. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Function renames - -Attempt to provide more uniformity for the DPAA2 Ethernet -driver function naming conventions: -* major functions (ndo_ops, driver ops, ethtool, etc) all have -the "dpaa2_eth" prefix -* non-static functions also start with "dpaa2_eth" -* static helper functions don't get any prefix in order to avoid -very long names -* some functions get more intuitive and/or explicit names -* don't use names starting with an underscore - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Structure and macro renames - -Some more renaming: -* defines of error/status bits in the frame annotation status -word get a "DPAA2_FAS" prefix instead of "DPAA2_ETH_FAS", as they're -not really specific to the ethernet driver. We may consider moving -these defines to a separate header file in the future -* DPAA2_ETH_RX_BUFFER_SIZE is renamed to DPAA2_ETH_RX_BUF_SIZE -to better match the naming style of other defines -* structure "dpaa2_eth_stats" becomes "dpaa2_eth_drv_stats" to -make it clear these are driver specific statistics - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Cosmetics - -Various coding style fixes and other minor cosmetics, -with no functional impact. Also remove a couple of unused -defines and a structure field. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Move function call - -Move call to set_fq_affinity() from probe to setup_fqs(), as it -logically belongs there. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Comments cleanup - -Add relevant comments where needed, remove obsolete or -useless ones. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Remove link poll Kconfig option - -Always try to use interrupts, but if they are not available -fall back to polling the link state. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: Remove message level - -We were defining netif message level, but we weren't using -it when printing error/info messages, so remove for now. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: eth: fix compile error on 4.5 uprev - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-dpaa2/ethernet/Kconfig | 6 - - .../staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.c | 6 +- - drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c | 992 ++++++++++---------- - drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h | 133 +-- - drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c | 226 ++--- - 5 files changed, 693 insertions(+), 670 deletions(-) - ---- a/drivers/staging/fsl-dpaa2/ethernet/Kconfig -+++ b/drivers/staging/fsl-dpaa2/ethernet/Kconfig -@@ -16,12 +16,6 @@ menuconfig FSL_DPAA2_ETH - driver, using the Freescale MC bus driver. - - if FSL_DPAA2_ETH --config FSL_DPAA2_ETH_LINK_POLL -- bool "Use polling mode for link state" -- default n -- ---help--- -- Poll for detecting link state changes instead of using -- interrupts. - - config FSL_DPAA2_ETH_USE_ERR_QUEUE - bool "Enable Rx error queue" ---- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.c -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.c -@@ -30,7 +30,6 @@ - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -- - #include - #include - #include "dpaa2-eth.h" -@@ -38,14 +37,13 @@ - - #define DPAA2_ETH_DBG_ROOT "dpaa2-eth" - -- - static struct dentry *dpaa2_dbg_root; - - static int dpaa2_dbg_cpu_show(struct seq_file *file, void *offset) - { - struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private; - struct rtnl_link_stats64 *stats; -- struct dpaa2_eth_stats *extras; -+ struct dpaa2_eth_drv_stats *extras; - int i; - - seq_printf(file, "Per-CPU stats for %s\n", priv->net_dev->name); -@@ -200,7 +198,7 @@ static ssize_t dpaa2_dbg_reset_write(str - { - struct dpaa2_eth_priv *priv = file->private_data; - struct rtnl_link_stats64 *percpu_stats; -- struct dpaa2_eth_stats *percpu_extras; -+ struct dpaa2_eth_drv_stats *percpu_extras; - struct dpaa2_eth_fq *fq; - struct dpaa2_eth_channel *ch; - int i; ---- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c -@@ -53,26 +53,14 @@ MODULE_LICENSE("Dual BSD/GPL"); - MODULE_AUTHOR("Freescale Semiconductor, Inc"); - MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver"); - --static int debug = -1; --module_param(debug, int, S_IRUGO); --MODULE_PARM_DESC(debug, "Module/Driver verbosity level"); -- - /* Oldest DPAA2 objects version we are compatible with */ - #define DPAA2_SUPPORTED_DPNI_VERSION 6 - #define DPAA2_SUPPORTED_DPBP_VERSION 2 - #define DPAA2_SUPPORTED_DPCON_VERSION 2 - --/* Iterate through the cpumask in a round-robin fashion. */ --#define cpumask_rr(cpu, maskptr) \ --do { \ -- (cpu) = cpumask_next((cpu), (maskptr)); \ -- if ((cpu) >= nr_cpu_ids) \ -- (cpu) = cpumask_first((maskptr)); \ --} while (0) -- --static void dpaa2_eth_rx_csum(struct dpaa2_eth_priv *priv, -- u32 fd_status, -- struct sk_buff *skb) -+static void validate_rx_csum(struct dpaa2_eth_priv *priv, -+ u32 fd_status, -+ struct sk_buff *skb) - { - skb_checksum_none_assert(skb); - -@@ -81,8 +69,8 @@ static void dpaa2_eth_rx_csum(struct dpa - return; - - /* Read checksum validation bits */ -- if (!((fd_status & DPAA2_ETH_FAS_L3CV) && -- (fd_status & DPAA2_ETH_FAS_L4CV))) -+ if (!((fd_status & DPAA2_FAS_L3CV) && -+ (fd_status & DPAA2_FAS_L4CV))) - return; - - /* Inform the stack there's no need to compute L3/L4 csum anymore */ -@@ -92,53 +80,55 @@ static void dpaa2_eth_rx_csum(struct dpa - /* Free a received FD. - * Not to be used for Tx conf FDs or on any other paths. - */ --static void dpaa2_eth_free_rx_fd(struct dpaa2_eth_priv *priv, -- const struct dpaa2_fd *fd, -- void *vaddr) -+static void free_rx_fd(struct dpaa2_eth_priv *priv, -+ const struct dpaa2_fd *fd, -+ void *vaddr) - { - struct device *dev = priv->net_dev->dev.parent; - dma_addr_t addr = dpaa2_fd_get_addr(fd); - u8 fd_format = dpaa2_fd_get_format(fd); -+ struct dpaa2_sg_entry *sgt; -+ void *sg_vaddr; -+ int i; - -- if (fd_format == dpaa2_fd_sg) { -- struct dpaa2_sg_entry *sgt = vaddr + dpaa2_fd_get_offset(fd); -- void *sg_vaddr; -- int i; -+ /* If single buffer frame, just free the data buffer */ -+ if (fd_format == dpaa2_fd_single) -+ goto free_buf; - -- for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) { -- dpaa2_sg_le_to_cpu(&sgt[i]); -+ /* For S/G frames, we first need to free all SG entries */ -+ sgt = vaddr + dpaa2_fd_get_offset(fd); -+ for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) { -+ dpaa2_sg_le_to_cpu(&sgt[i]); - -- addr = dpaa2_sg_get_addr(&sgt[i]); -- dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUFFER_SIZE, -- DMA_FROM_DEVICE); -+ addr = dpaa2_sg_get_addr(&sgt[i]); -+ dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE, -+ DMA_FROM_DEVICE); - -- sg_vaddr = phys_to_virt(addr); -- put_page(virt_to_head_page(sg_vaddr)); -+ sg_vaddr = phys_to_virt(addr); -+ put_page(virt_to_head_page(sg_vaddr)); - -- if (dpaa2_sg_is_final(&sgt[i])) -- break; -- } -+ if (dpaa2_sg_is_final(&sgt[i])) -+ break; - } - -+free_buf: - put_page(virt_to_head_page(vaddr)); - } - - /* Build a linear skb based on a single-buffer frame descriptor */ --static struct sk_buff *dpaa2_eth_build_linear_skb(struct dpaa2_eth_priv *priv, -- struct dpaa2_eth_channel *ch, -- const struct dpaa2_fd *fd, -- void *fd_vaddr) -+static struct sk_buff *build_linear_skb(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_channel *ch, -+ const struct dpaa2_fd *fd, -+ void *fd_vaddr) - { - struct sk_buff *skb = NULL; - u16 fd_offset = dpaa2_fd_get_offset(fd); - u32 fd_length = dpaa2_fd_get_len(fd); - -- skb = build_skb(fd_vaddr, DPAA2_ETH_RX_BUFFER_SIZE + -+ skb = build_skb(fd_vaddr, DPAA2_ETH_RX_BUF_SIZE + - SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); -- if (unlikely(!skb)) { -- netdev_err(priv->net_dev, "build_skb() failed\n"); -+ if (unlikely(!skb)) - return NULL; -- } - - skb_reserve(skb, fd_offset); - skb_put(skb, fd_length); -@@ -149,9 +139,9 @@ static struct sk_buff *dpaa2_eth_build_l - } - - /* Build a non linear (fragmented) skb based on a S/G table */ --static struct sk_buff *dpaa2_eth_build_frag_skb(struct dpaa2_eth_priv *priv, -- struct dpaa2_eth_channel *ch, -- struct dpaa2_sg_entry *sgt) -+static struct sk_buff *build_frag_skb(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_channel *ch, -+ struct dpaa2_sg_entry *sgt) - { - struct sk_buff *skb = NULL; - struct device *dev = priv->net_dev->dev.parent; -@@ -168,66 +158,57 @@ static struct sk_buff *dpaa2_eth_build_f - - dpaa2_sg_le_to_cpu(sge); - -- /* We don't support anything else yet! */ -- if (unlikely(dpaa2_sg_get_format(sge) != dpaa2_sg_single)) { -- dev_warn_once(dev, "Unsupported S/G entry format: %d\n", -- dpaa2_sg_get_format(sge)); -- return NULL; -- } -+ /* NOTE: We only support SG entries in dpaa2_sg_single format, -+ * but this is the only format we may receive from HW anyway -+ */ - -- /* Get the address, offset and length from the S/G entry */ -+ /* Get the address and length from the S/G entry */ - sg_addr = dpaa2_sg_get_addr(sge); -- dma_unmap_single(dev, sg_addr, DPAA2_ETH_RX_BUFFER_SIZE, -+ dma_unmap_single(dev, sg_addr, DPAA2_ETH_RX_BUF_SIZE, - DMA_FROM_DEVICE); -- if (unlikely(dma_mapping_error(dev, sg_addr))) { -- netdev_err(priv->net_dev, "DMA unmap failed\n"); -- return NULL; -- } -+ - sg_vaddr = phys_to_virt(sg_addr); - sg_length = dpaa2_sg_get_len(sge); - - if (i == 0) { - /* We build the skb around the first data buffer */ -- skb = build_skb(sg_vaddr, DPAA2_ETH_RX_BUFFER_SIZE + -+ skb = build_skb(sg_vaddr, DPAA2_ETH_RX_BUF_SIZE + - SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); -- if (unlikely(!skb)) { -- netdev_err(priv->net_dev, "build_skb failed\n"); -+ if (unlikely(!skb)) - return NULL; -- } -+ - sg_offset = dpaa2_sg_get_offset(sge); - skb_reserve(skb, sg_offset); - skb_put(skb, sg_length); - } else { -- /* Subsequent data in SGEntries are stored at -- * offset 0 in their buffers, we don't need to -- * compute sg_offset. -- */ -- WARN_ONCE(dpaa2_sg_get_offset(sge) != 0, -- "Non-zero offset in SGE[%d]!\n", i); -- - /* Rest of the data buffers are stored as skb frags */ - page = virt_to_page(sg_vaddr); - head_page = virt_to_head_page(sg_vaddr); - -- /* Offset in page (which may be compound) */ -+ /* Offset in page (which may be compound). -+ * Data in subsequent SG entries is stored from the -+ * beginning of the buffer, so we don't need to add the -+ * sg_offset. -+ */ - page_offset = ((unsigned long)sg_vaddr & - (PAGE_SIZE - 1)) + - (page_address(page) - page_address(head_page)); - - skb_add_rx_frag(skb, i - 1, head_page, page_offset, -- sg_length, DPAA2_ETH_RX_BUFFER_SIZE); -+ sg_length, DPAA2_ETH_RX_BUF_SIZE); - } - - if (dpaa2_sg_is_final(sge)) - break; - } - -- /* Count all data buffers + sgt buffer */ -+ /* Count all data buffers + SG table buffer */ - ch->buf_count -= i + 2; - - return skb; - } - -+/* Main Rx frame processing routine */ - static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv, - struct dpaa2_eth_channel *ch, - const struct dpaa2_fd *fd, -@@ -238,7 +219,7 @@ static void dpaa2_eth_rx(struct dpaa2_et - void *vaddr; - struct sk_buff *skb; - struct rtnl_link_stats64 *percpu_stats; -- struct dpaa2_eth_stats *percpu_extras; -+ struct dpaa2_eth_drv_stats *percpu_extras; - struct device *dev = priv->net_dev->dev.parent; - struct dpaa2_fas *fas; - u32 status = 0; -@@ -246,7 +227,7 @@ static void dpaa2_eth_rx(struct dpaa2_et - /* Tracing point */ - trace_dpaa2_rx_fd(priv->net_dev, fd); - -- dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUFFER_SIZE, DMA_FROM_DEVICE); -+ dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE, DMA_FROM_DEVICE); - vaddr = phys_to_virt(addr); - - prefetch(vaddr + priv->buf_layout.private_data_size); -@@ -256,32 +237,30 @@ static void dpaa2_eth_rx(struct dpaa2_et - percpu_extras = this_cpu_ptr(priv->percpu_extras); - - if (fd_format == dpaa2_fd_single) { -- skb = dpaa2_eth_build_linear_skb(priv, ch, fd, vaddr); -+ skb = build_linear_skb(priv, ch, fd, vaddr); - } else if (fd_format == dpaa2_fd_sg) { - struct dpaa2_sg_entry *sgt = - vaddr + dpaa2_fd_get_offset(fd); -- skb = dpaa2_eth_build_frag_skb(priv, ch, sgt); -+ skb = build_frag_skb(priv, ch, sgt); - put_page(virt_to_head_page(vaddr)); - percpu_extras->rx_sg_frames++; - percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd); - } else { - /* We don't support any other format */ -- netdev_err(priv->net_dev, "Received invalid frame format\n"); - goto err_frame_format; - } - -- if (unlikely(!skb)) { -- dev_err_once(dev, "error building skb\n"); -+ if (unlikely(!skb)) - goto err_build_skb; -- } - - prefetch(skb->data); - -+ /* Get the timestamp value */ - if (priv->ts_rx_en) { - struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); -- u64 *ns = (u64 *) (vaddr + -- priv->buf_layout.private_data_size + -- sizeof(struct dpaa2_fas)); -+ u64 *ns = (u64 *)(vaddr + -+ priv->buf_layout.private_data_size + -+ sizeof(struct dpaa2_fas)); - - *ns = DPAA2_PTP_NOMINAL_FREQ_PERIOD_NS * (*ns); - memset(shhwtstamps, 0, sizeof(*shhwtstamps)); -@@ -293,7 +272,7 @@ static void dpaa2_eth_rx(struct dpaa2_et - fas = (struct dpaa2_fas *) - (vaddr + priv->buf_layout.private_data_size); - status = le32_to_cpu(fas->status); -- dpaa2_eth_rx_csum(priv, status, skb); -+ validate_rx_csum(priv, status, skb); - } - - skb->protocol = eth_type_trans(skb, priv->net_dev); -@@ -309,11 +288,14 @@ static void dpaa2_eth_rx(struct dpaa2_et - return; - err_frame_format: - err_build_skb: -- dpaa2_eth_free_rx_fd(priv, fd, vaddr); -+ free_rx_fd(priv, fd, vaddr); - percpu_stats->rx_dropped++; - } - - #ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE -+/* Processing of Rx frames received on the error FQ -+ * We check and print the error bits and then free the frame -+ */ - static void dpaa2_eth_rx_err(struct dpaa2_eth_priv *priv, - struct dpaa2_eth_channel *ch, - const struct dpaa2_fd *fd, -@@ -326,21 +308,18 @@ static void dpaa2_eth_rx_err(struct dpaa - struct dpaa2_fas *fas; - u32 status = 0; - -- dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUFFER_SIZE, DMA_FROM_DEVICE); -+ dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE, DMA_FROM_DEVICE); - vaddr = phys_to_virt(addr); - - if (fd->simple.frc & DPAA2_FD_FRC_FASV) { - fas = (struct dpaa2_fas *) - (vaddr + priv->buf_layout.private_data_size); - status = le32_to_cpu(fas->status); -- -- /* All frames received on this queue should have at least -- * one of the Rx error bits set */ -- WARN_ON_ONCE((status & DPAA2_ETH_RX_ERR_MASK) == 0); -- netdev_dbg(priv->net_dev, "Rx frame error: 0x%08x\n", -- status & DPAA2_ETH_RX_ERR_MASK); -+ if (net_ratelimit()) -+ netdev_warn(priv->net_dev, "Rx frame error: 0x%08x\n", -+ status & DPAA2_ETH_RX_ERR_MASK); - } -- dpaa2_eth_free_rx_fd(priv, fd, vaddr); -+ free_rx_fd(priv, fd, vaddr); - - percpu_stats = this_cpu_ptr(priv->percpu_stats); - percpu_stats->rx_errors++; -@@ -353,7 +332,7 @@ static void dpaa2_eth_rx_err(struct dpaa - * - * Observance of NAPI budget is not our concern, leaving that to the caller. - */ --static int dpaa2_eth_store_consume(struct dpaa2_eth_channel *ch) -+static int consume_frames(struct dpaa2_eth_channel *ch) - { - struct dpaa2_eth_priv *priv = ch->priv; - struct dpaa2_eth_fq *fq; -@@ -365,20 +344,14 @@ static int dpaa2_eth_store_consume(struc - do { - dq = dpaa2_io_store_next(ch->store, &is_last); - if (unlikely(!dq)) { -- if (unlikely(!is_last)) { -- netdev_dbg(priv->net_dev, -- "Channel %d reqturned no valid frames\n", -- ch->ch_id); -- /* MUST retry until we get some sort of -- * valid response token (be it "empty dequeue" -- * or a valid frame). -- */ -- continue; -- } -- break; -+ /* If we're here, we *must* have placed a -+ * volatile dequeue comnmand, so keep reading through -+ * the store until we get some sort of valid response -+ * token (either a valid frame or an "empty dequeue") -+ */ -+ continue; - } - -- /* Obtain FD and process it */ - fd = dpaa2_dq_fd(dq); - fq = (struct dpaa2_eth_fq *)dpaa2_dq_fqd_ctx(dq); - fq->stats.frames++; -@@ -390,9 +363,10 @@ static int dpaa2_eth_store_consume(struc - return cleaned; - } - --static int dpaa2_eth_build_sg_fd(struct dpaa2_eth_priv *priv, -- struct sk_buff *skb, -- struct dpaa2_fd *fd) -+/* Create a frame descriptor based on a fragmented skb */ -+static int build_sg_fd(struct dpaa2_eth_priv *priv, -+ struct sk_buff *skb, -+ struct dpaa2_fd *fd) - { - struct device *dev = priv->net_dev->dev.parent; - void *sgt_buf = NULL; -@@ -404,14 +378,16 @@ static int dpaa2_eth_build_sg_fd(struct - struct scatterlist *scl, *crt_scl; - int num_sg; - int num_dma_bufs; -- struct dpaa2_eth_swa *bps; -+ struct dpaa2_eth_swa *swa; - - /* Create and map scatterlist. - * We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have - * to go beyond nr_frags+1. - * Note: We don't support chained scatterlists - */ -- WARN_ON(PAGE_SIZE / sizeof(struct scatterlist) < nr_frags + 1); -+ if (unlikely(PAGE_SIZE / sizeof(struct scatterlist) < nr_frags + 1)) -+ return -EINVAL; -+ - scl = kcalloc(nr_frags + 1, sizeof(struct scatterlist), GFP_ATOMIC); - if (unlikely(!scl)) - return -ENOMEM; -@@ -420,7 +396,6 @@ static int dpaa2_eth_build_sg_fd(struct - num_sg = skb_to_sgvec(skb, scl, 0, skb->len); - num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_TO_DEVICE); - if (unlikely(!num_dma_bufs)) { -- netdev_err(priv->net_dev, "dma_map_sg() error\n"); - err = -ENOMEM; - goto dma_map_sg_failed; - } -@@ -430,7 +405,6 @@ static int dpaa2_eth_build_sg_fd(struct - sizeof(struct dpaa2_sg_entry) * (1 + num_dma_bufs); - sgt_buf = kzalloc(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN, GFP_ATOMIC); - if (unlikely(!sgt_buf)) { -- netdev_err(priv->net_dev, "failed to allocate SGT buffer\n"); - err = -ENOMEM; - goto sgt_buf_alloc_failed; - } -@@ -462,19 +436,19 @@ static int dpaa2_eth_build_sg_fd(struct - * Fit the scatterlist and the number of buffers alongside the - * skb backpointer in the SWA. We'll need all of them on Tx Conf. - */ -- bps = (struct dpaa2_eth_swa *)sgt_buf; -- bps->skb = skb; -- bps->scl = scl; -- bps->num_sg = num_sg; -- bps->num_dma_bufs = num_dma_bufs; -+ swa = (struct dpaa2_eth_swa *)sgt_buf; -+ swa->skb = skb; -+ swa->scl = scl; -+ swa->num_sg = num_sg; -+ swa->num_dma_bufs = num_dma_bufs; - -+ /* Hardware expects the SG table to be in little endian format */ - for (j = 0; j < i; j++) - dpaa2_sg_cpu_to_le(&sgt[j]); - - /* Separately map the SGT buffer */ - addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_TO_DEVICE); - if (unlikely(dma_mapping_error(dev, addr))) { -- netdev_err(priv->net_dev, "dma_map_single() failed\n"); - err = -ENOMEM; - goto dma_map_single_failed; - } -@@ -484,7 +458,7 @@ static int dpaa2_eth_build_sg_fd(struct - dpaa2_fd_set_len(fd, skb->len); - - fd->simple.ctrl = DPAA2_FD_CTRL_ASAL | DPAA2_FD_CTRL_PTA | -- DPAA2_FD_CTRL_PTV1; -+ DPAA2_FD_CTRL_PTV1; - - return 0; - -@@ -497,9 +471,10 @@ dma_map_sg_failed: - return err; - } - --static int dpaa2_eth_build_single_fd(struct dpaa2_eth_priv *priv, -- struct sk_buff *skb, -- struct dpaa2_fd *fd) -+/* Create a frame descriptor based on a linear skb */ -+static int build_single_fd(struct dpaa2_eth_priv *priv, -+ struct sk_buff *skb, -+ struct dpaa2_fd *fd) - { - struct device *dev = priv->net_dev->dev.parent; - u8 *buffer_start; -@@ -524,14 +499,11 @@ static int dpaa2_eth_build_single_fd(str - skbh = (struct sk_buff **)buffer_start; - *skbh = skb; - -- addr = dma_map_single(dev, -- buffer_start, -+ addr = dma_map_single(dev, buffer_start, - skb_tail_pointer(skb) - buffer_start, - DMA_TO_DEVICE); -- if (unlikely(dma_mapping_error(dev, addr))) { -- dev_err(dev, "dma_map_single() failed\n"); -- return -EINVAL; -- } -+ if (unlikely(dma_mapping_error(dev, addr))) -+ return -ENOMEM; - - dpaa2_fd_set_addr(fd, addr); - dpaa2_fd_set_offset(fd, (u16)(skb->data - buffer_start)); -@@ -539,21 +511,23 @@ static int dpaa2_eth_build_single_fd(str - dpaa2_fd_set_format(fd, dpaa2_fd_single); - - fd->simple.ctrl = DPAA2_FD_CTRL_ASAL | DPAA2_FD_CTRL_PTA | -- DPAA2_FD_CTRL_PTV1; -+ DPAA2_FD_CTRL_PTV1; - - return 0; - } - --/* DMA-unmap and free FD and possibly SGT buffer allocated on Tx. The skb -+/* FD freeing routine on the Tx path -+ * -+ * DMA-unmap and free FD and possibly SGT buffer allocated on Tx. The skb - * back-pointed to is also freed. - * This can be called either from dpaa2_eth_tx_conf() or on the error path of - * dpaa2_eth_tx(). - * Optionally, return the frame annotation status word (FAS), which needs - * to be checked if we're on the confirmation path. - */ --static void dpaa2_eth_free_fd(const struct dpaa2_eth_priv *priv, -- const struct dpaa2_fd *fd, -- u32 *status) -+static void free_tx_fd(const struct dpaa2_eth_priv *priv, -+ const struct dpaa2_fd *fd, -+ u32 *status) - { - struct device *dev = priv->net_dev->dev.parent; - dma_addr_t fd_addr; -@@ -562,7 +536,7 @@ static void dpaa2_eth_free_fd(const stru - int unmap_size; - struct scatterlist *scl; - int num_sg, num_dma_bufs; -- struct dpaa2_eth_swa *bps; -+ struct dpaa2_eth_swa *swa; - bool fd_single; - struct dpaa2_fas *fas; - -@@ -580,11 +554,11 @@ static void dpaa2_eth_free_fd(const stru - skb_tail_pointer(skb) - buffer_start, - DMA_TO_DEVICE); - } else { -- bps = (struct dpaa2_eth_swa *)skbh; -- skb = bps->skb; -- scl = bps->scl; -- num_sg = bps->num_sg; -- num_dma_bufs = bps->num_dma_bufs; -+ swa = (struct dpaa2_eth_swa *)skbh; -+ skb = swa->skb; -+ scl = swa->scl; -+ num_sg = swa->num_sg; -+ num_dma_bufs = swa->num_dma_bufs; - - /* Unmap the scatterlist */ - dma_unmap_sg(dev, scl, num_sg, DMA_TO_DEVICE); -@@ -596,6 +570,7 @@ static void dpaa2_eth_free_fd(const stru - dma_unmap_single(dev, fd_addr, unmap_size, DMA_TO_DEVICE); - } - -+ /* Get the timestamp value */ - if (priv->ts_tx_en && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { - struct skb_shared_hwtstamps shhwtstamps; - u64 *ns; -@@ -610,8 +585,9 @@ static void dpaa2_eth_free_fd(const stru - skb_tstamp_tx(skb, &shhwtstamps); - } - -- /* Check the status from the Frame Annotation after we unmap the first -- * buffer but before we free it. -+ /* Read the status from the Frame Annotation after we unmap the first -+ * buffer but before we free it. The caller function is responsible -+ * for checking the status value. - */ - if (status && (fd->simple.frc & DPAA2_FD_FRC_FASV)) { - fas = (struct dpaa2_fas *) -@@ -632,24 +608,16 @@ static int dpaa2_eth_tx(struct sk_buff * - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); - struct dpaa2_fd fd; - struct rtnl_link_stats64 *percpu_stats; -- struct dpaa2_eth_stats *percpu_extras; -+ struct dpaa2_eth_drv_stats *percpu_extras; -+ u16 queue_mapping, flow_id; - int err, i; -- /* TxConf FQ selection primarily based on cpu affinity; this is -- * non-migratable context, so it's safe to call smp_processor_id(). -- */ -- u16 queue_mapping = smp_processor_id() % priv->dpni_attrs.max_senders; - - percpu_stats = this_cpu_ptr(priv->percpu_stats); - percpu_extras = this_cpu_ptr(priv->percpu_extras); - -- /* Setup the FD fields */ -- memset(&fd, 0, sizeof(fd)); -- - if (unlikely(skb_headroom(skb) < DPAA2_ETH_NEEDED_HEADROOM(priv))) { - struct sk_buff *ns; - -- dev_info_once(net_dev->dev.parent, -- "skb headroom too small, must realloc.\n"); - ns = skb_realloc_headroom(skb, DPAA2_ETH_NEEDED_HEADROOM(priv)); - if (unlikely(!ns)) { - percpu_stats->tx_dropped++; -@@ -664,18 +632,20 @@ static int dpaa2_eth_tx(struct sk_buff * - */ - skb = skb_unshare(skb, GFP_ATOMIC); - if (unlikely(!skb)) { -- netdev_err(net_dev, "Out of memory for skb_unshare()"); - /* skb_unshare() has already freed the skb */ - percpu_stats->tx_dropped++; - return NETDEV_TX_OK; - } - -+ /* Setup the FD fields */ -+ memset(&fd, 0, sizeof(fd)); -+ - if (skb_is_nonlinear(skb)) { -- err = dpaa2_eth_build_sg_fd(priv, skb, &fd); -+ err = build_sg_fd(priv, skb, &fd); - percpu_extras->tx_sg_frames++; - percpu_extras->tx_sg_bytes += skb->len; - } else { -- err = dpaa2_eth_build_single_fd(priv, skb, &fd); -+ err = build_single_fd(priv, skb, &fd); - } - - if (unlikely(err)) { -@@ -686,19 +656,22 @@ static int dpaa2_eth_tx(struct sk_buff * - /* Tracing point */ - trace_dpaa2_tx_fd(net_dev, &fd); - -+ /* TxConf FQ selection primarily based on cpu affinity; this is -+ * non-migratable context, so it's safe to call smp_processor_id(). -+ */ -+ queue_mapping = smp_processor_id() % priv->dpni_attrs.max_senders; -+ flow_id = priv->fq[queue_mapping].flowid; - for (i = 0; i < (DPAA2_ETH_MAX_TX_QUEUES << 1); i++) { - err = dpaa2_io_service_enqueue_qd(NULL, priv->tx_qdid, 0, -- priv->fq[queue_mapping].flowid, -- &fd); -+ flow_id, &fd); - if (err != -EBUSY) - break; - } - percpu_extras->tx_portal_busy += i; - if (unlikely(err < 0)) { -- netdev_dbg(net_dev, "error enqueueing Tx frame\n"); - percpu_stats->tx_errors++; - /* Clean up everything, including freeing the skb */ -- dpaa2_eth_free_fd(priv, &fd, NULL); -+ free_tx_fd(priv, &fd, NULL); - } else { - percpu_stats->tx_packets++; - percpu_stats->tx_bytes += skb->len; -@@ -713,13 +686,14 @@ err_alloc_headroom: - return NETDEV_TX_OK; - } - -+/* Tx confirmation frame processing routine */ - static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv, - struct dpaa2_eth_channel *ch, - const struct dpaa2_fd *fd, - struct napi_struct *napi __always_unused) - { - struct rtnl_link_stats64 *percpu_stats; -- struct dpaa2_eth_stats *percpu_extras; -+ struct dpaa2_eth_drv_stats *percpu_extras; - u32 status = 0; - - /* Tracing point */ -@@ -729,18 +703,16 @@ static void dpaa2_eth_tx_conf(struct dpa - percpu_extras->tx_conf_frames++; - percpu_extras->tx_conf_bytes += dpaa2_fd_get_len(fd); - -- dpaa2_eth_free_fd(priv, fd, &status); -+ free_tx_fd(priv, fd, &status); - - if (unlikely(status & DPAA2_ETH_TXCONF_ERR_MASK)) { -- netdev_err(priv->net_dev, "TxConf frame error(s): 0x%08x\n", -- status & DPAA2_ETH_TXCONF_ERR_MASK); - percpu_stats = this_cpu_ptr(priv->percpu_stats); - /* Tx-conf logically pertains to the egress path. */ - percpu_stats->tx_errors++; - } - } - --static int dpaa2_eth_set_rx_csum(struct dpaa2_eth_priv *priv, bool enable) -+static int set_rx_csum(struct dpaa2_eth_priv *priv, bool enable) - { - int err; - -@@ -763,7 +735,7 @@ static int dpaa2_eth_set_rx_csum(struct - return 0; - } - --static int dpaa2_eth_set_tx_csum(struct dpaa2_eth_priv *priv, bool enable) -+static int set_tx_csum(struct dpaa2_eth_priv *priv, bool enable) - { - struct dpaa2_eth_fq *fq; - struct dpni_tx_flow_cfg tx_flow_cfg; -@@ -793,37 +765,38 @@ static int dpaa2_eth_set_tx_csum(struct - return 0; - } - --static int dpaa2_bp_add_7(struct dpaa2_eth_priv *priv, u16 bpid) -+/* Perform a single release command to add buffers -+ * to the specified buffer pool -+ */ -+static int add_bufs(struct dpaa2_eth_priv *priv, u16 bpid) - { - struct device *dev = priv->net_dev->dev.parent; -- u64 buf_array[7]; -+ u64 buf_array[DPAA2_ETH_BUFS_PER_CMD]; - void *buf; - dma_addr_t addr; - int i; - -- for (i = 0; i < 7; i++) { -+ for (i = 0; i < DPAA2_ETH_BUFS_PER_CMD; i++) { - /* Allocate buffer visible to WRIOP + skb shared info + - * alignment padding - */ - buf = napi_alloc_frag(DPAA2_ETH_BUF_RAW_SIZE); -- if (unlikely(!buf)) { -- dev_err(dev, "buffer allocation failed\n"); -+ if (unlikely(!buf)) - goto err_alloc; -- } -+ - buf = PTR_ALIGN(buf, DPAA2_ETH_RX_BUF_ALIGN); - -- addr = dma_map_single(dev, buf, DPAA2_ETH_RX_BUFFER_SIZE, -+ addr = dma_map_single(dev, buf, DPAA2_ETH_RX_BUF_SIZE, - DMA_FROM_DEVICE); -- if (unlikely(dma_mapping_error(dev, addr))) { -- dev_err(dev, "dma_map_single() failed\n"); -+ if (unlikely(dma_mapping_error(dev, addr))) - goto err_map; -- } -+ - buf_array[i] = addr; - - /* tracing point */ - trace_dpaa2_eth_buf_seed(priv->net_dev, - buf, DPAA2_ETH_BUF_RAW_SIZE, -- addr, DPAA2_ETH_RX_BUFFER_SIZE, -+ addr, DPAA2_ETH_RX_BUF_SIZE, - bpid); - } - -@@ -850,59 +823,57 @@ err_alloc: - return 0; - } - --static int dpaa2_dpbp_seed(struct dpaa2_eth_priv *priv, u16 bpid) -+static int seed_pool(struct dpaa2_eth_priv *priv, u16 bpid) - { - int i, j; - int new_count; - - /* This is the lazy seeding of Rx buffer pools. -- * dpaa2_bp_add_7() is also used on the Rx hotpath and calls -+ * dpaa2_add_bufs() is also used on the Rx hotpath and calls - * napi_alloc_frag(). The trouble with that is that it in turn ends up - * calling this_cpu_ptr(), which mandates execution in atomic context. - * Rather than splitting up the code, do a one-off preempt disable. - */ - preempt_disable(); - for (j = 0; j < priv->num_channels; j++) { -- for (i = 0; i < DPAA2_ETH_NUM_BUFS; i += 7) { -- new_count = dpaa2_bp_add_7(priv, bpid); -+ for (i = 0; i < DPAA2_ETH_NUM_BUFS; -+ i += DPAA2_ETH_BUFS_PER_CMD) { -+ new_count = add_bufs(priv, bpid); - priv->channel[j]->buf_count += new_count; - -- if (new_count < 7) { -+ if (new_count < DPAA2_ETH_BUFS_PER_CMD) { - preempt_enable(); -- goto out_of_memory; -+ return -ENOMEM; - } - } - } - preempt_enable(); - - return 0; -- --out_of_memory: -- return -ENOMEM; - } - - /** - * Drain the specified number of buffers from the DPNI's private buffer pool. -- * @count must not exceeed 7 -+ * @count must not exceeed DPAA2_ETH_BUFS_PER_CMD - */ --static void dpaa2_dpbp_drain_cnt(struct dpaa2_eth_priv *priv, int count) -+static void drain_bufs(struct dpaa2_eth_priv *priv, int count) - { - struct device *dev = priv->net_dev->dev.parent; -- u64 buf_array[7]; -+ u64 buf_array[DPAA2_ETH_BUFS_PER_CMD]; - void *vaddr; - int ret, i; - - do { - ret = dpaa2_io_service_acquire(NULL, priv->dpbp_attrs.bpid, -- buf_array, count); -+ buf_array, count); - if (ret < 0) { -- pr_err("dpaa2_io_service_acquire() failed\n"); -+ netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n"); - return; - } - for (i = 0; i < ret; i++) { - /* Same logic as on regular Rx path */ - dma_unmap_single(dev, buf_array[i], -- DPAA2_ETH_RX_BUFFER_SIZE, -+ DPAA2_ETH_RX_BUF_SIZE, - DMA_FROM_DEVICE); - vaddr = phys_to_virt(buf_array[i]); - put_page(virt_to_head_page(vaddr)); -@@ -910,12 +881,12 @@ static void dpaa2_dpbp_drain_cnt(struct - } while (ret); - } - --static void __dpaa2_dpbp_free(struct dpaa2_eth_priv *priv) -+static void drain_pool(struct dpaa2_eth_priv *priv) - { - int i; - -- dpaa2_dpbp_drain_cnt(priv, 7); -- dpaa2_dpbp_drain_cnt(priv, 1); -+ drain_bufs(priv, DPAA2_ETH_BUFS_PER_CMD); -+ drain_bufs(priv, 1); - - for (i = 0; i < priv->num_channels; i++) - priv->channel[i]->buf_count = 0; -@@ -924,50 +895,55 @@ static void __dpaa2_dpbp_free(struct dpa - /* Function is called from softirq context only, so we don't need to guard - * the access to percpu count - */ --static int dpaa2_dpbp_refill(struct dpaa2_eth_priv *priv, -- struct dpaa2_eth_channel *ch, -- u16 bpid) -+static int refill_pool(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_channel *ch, -+ u16 bpid) - { - int new_count; -- int err = 0; - -- if (unlikely(ch->buf_count < DPAA2_ETH_REFILL_THRESH)) { -- do { -- new_count = dpaa2_bp_add_7(priv, bpid); -- if (unlikely(!new_count)) { -- /* Out of memory; abort for now, we'll -- * try later on -- */ -- break; -- } -- ch->buf_count += new_count; -- } while (ch->buf_count < DPAA2_ETH_NUM_BUFS); -+ if (likely(ch->buf_count >= DPAA2_ETH_REFILL_THRESH)) -+ return 0; - -- if (unlikely(ch->buf_count < DPAA2_ETH_NUM_BUFS)) -- err = -ENOMEM; -- } -+ do { -+ new_count = add_bufs(priv, bpid); -+ if (unlikely(!new_count)) { -+ /* Out of memory; abort for now, we'll try later on */ -+ break; -+ } -+ ch->buf_count += new_count; -+ } while (ch->buf_count < DPAA2_ETH_NUM_BUFS); - -- return err; -+ if (unlikely(ch->buf_count < DPAA2_ETH_NUM_BUFS)) -+ return -ENOMEM; -+ -+ return 0; - } - --static int __dpaa2_eth_pull_channel(struct dpaa2_eth_channel *ch) -+static int pull_channel(struct dpaa2_eth_channel *ch) - { - int err; - int dequeues = -1; -- struct dpaa2_eth_priv *priv = ch->priv; - - /* Retry while portal is busy */ - do { - err = dpaa2_io_service_pull_channel(NULL, ch->ch_id, ch->store); - dequeues++; -+ cpu_relax(); - } while (err == -EBUSY); -- if (unlikely(err)) -- netdev_err(priv->net_dev, "dpaa2_io_service_pull err %d", err); - - ch->stats.dequeue_portal_busy += dequeues; -+ if (unlikely(err)) -+ ch->stats.pull_err++; -+ - return err; - } - -+/* NAPI poll routine -+ * -+ * Frames are dequeued from the QMan channel associated with this NAPI context. -+ * Rx, Tx confirmation and (if configured) Rx error frames all count -+ * towards the NAPI budget. -+ */ - static int dpaa2_eth_poll(struct napi_struct *napi, int budget) - { - struct dpaa2_eth_channel *ch; -@@ -978,32 +954,32 @@ static int dpaa2_eth_poll(struct napi_st - ch = container_of(napi, struct dpaa2_eth_channel, napi); - priv = ch->priv; - -- __dpaa2_eth_pull_channel(ch); -+ while (cleaned < budget) { -+ err = pull_channel(ch); -+ if (unlikely(err)) -+ break; - -- do { - /* Refill pool if appropriate */ -- dpaa2_dpbp_refill(priv, ch, priv->dpbp_attrs.bpid); -+ refill_pool(priv, ch, priv->dpbp_attrs.bpid); - -- store_cleaned = dpaa2_eth_store_consume(ch); -+ store_cleaned = consume_frames(ch); - cleaned += store_cleaned; - -+ /* If we have enough budget left for a full store, -+ * try a new pull dequeue, otherwise we're done here -+ */ - if (store_cleaned == 0 || - cleaned > budget - DPAA2_ETH_STORE_SIZE) - break; -- -- /* Try to dequeue some more */ -- err = __dpaa2_eth_pull_channel(ch); -- if (unlikely(err)) -- break; -- } while (1); -+ } - - if (cleaned < budget) { - napi_complete_done(napi, cleaned); -- err = dpaa2_io_service_rearm(NULL, &ch->nctx); -- if (unlikely(err)) -- netdev_err(priv->net_dev, -- "Notif rearm failed for channel %d\n", -- ch->ch_id); -+ /* Re-enable data available notifications */ -+ do { -+ err = dpaa2_io_service_rearm(NULL, &ch->nctx); -+ cpu_relax(); -+ } while (err == -EBUSY); - } - - ch->stats.frames += cleaned; -@@ -1011,7 +987,7 @@ static int dpaa2_eth_poll(struct napi_st - return cleaned; - } - --static void dpaa2_eth_napi_enable(struct dpaa2_eth_priv *priv) -+static void enable_ch_napi(struct dpaa2_eth_priv *priv) - { - struct dpaa2_eth_channel *ch; - int i; -@@ -1022,7 +998,7 @@ static void dpaa2_eth_napi_enable(struct - } - } - --static void dpaa2_eth_napi_disable(struct dpaa2_eth_priv *priv) -+static void disable_ch_napi(struct dpaa2_eth_priv *priv) - { - struct dpaa2_eth_channel *ch; - int i; -@@ -1033,7 +1009,7 @@ static void dpaa2_eth_napi_disable(struc - } - } - --static int dpaa2_link_state_update(struct dpaa2_eth_priv *priv) -+static int link_state_update(struct dpaa2_eth_priv *priv) - { - struct dpni_link_state state; - int err; -@@ -1069,7 +1045,7 @@ static int dpaa2_eth_open(struct net_dev - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); - int err; - -- err = dpaa2_dpbp_seed(priv, priv->dpbp_attrs.bpid); -+ err = seed_pool(priv, priv->dpbp_attrs.bpid); - if (err) { - /* Not much to do; the buffer pool, though not filled up, - * may still contain some buffers which would enable us -@@ -1084,7 +1060,7 @@ static int dpaa2_eth_open(struct net_dev - * immediately after dpni_enable(); - */ - netif_tx_stop_all_queues(net_dev); -- dpaa2_eth_napi_enable(priv); -+ enable_ch_napi(priv); - /* Also, explicitly set carrier off, otherwise netif_carrier_ok() will - * return true and cause 'ip link show' to report the LOWER_UP flag, - * even though the link notification wasn't even received. -@@ -1093,16 +1069,16 @@ static int dpaa2_eth_open(struct net_dev - - err = dpni_enable(priv->mc_io, 0, priv->mc_token); - if (err < 0) { -- dev_err(net_dev->dev.parent, "dpni_enable() failed\n"); -+ netdev_err(net_dev, "dpni_enable() failed\n"); - goto enable_err; - } - - /* If the DPMAC object has already processed the link up interrupt, - * we have to learn the link state ourselves. - */ -- err = dpaa2_link_state_update(priv); -+ err = link_state_update(priv); - if (err < 0) { -- dev_err(net_dev->dev.parent, "Can't update link state\n"); -+ netdev_err(net_dev, "Can't update link state\n"); - goto link_state_err; - } - -@@ -1110,26 +1086,84 @@ static int dpaa2_eth_open(struct net_dev - - link_state_err: - enable_err: -- dpaa2_eth_napi_disable(priv); -- __dpaa2_dpbp_free(priv); -+ disable_ch_napi(priv); -+ drain_pool(priv); - return err; - } - -+/* The DPIO store must be empty when we call this, -+ * at the end of every NAPI cycle. -+ */ -+static u32 drain_channel(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_channel *ch) -+{ -+ u32 drained = 0, total = 0; -+ -+ do { -+ pull_channel(ch); -+ drained = consume_frames(ch); -+ total += drained; -+ } while (drained); -+ -+ return total; -+} -+ -+static u32 drain_ingress_frames(struct dpaa2_eth_priv *priv) -+{ -+ struct dpaa2_eth_channel *ch; -+ int i; -+ u32 drained = 0; -+ -+ for (i = 0; i < priv->num_channels; i++) { -+ ch = priv->channel[i]; -+ drained += drain_channel(priv, ch); -+ } -+ -+ return drained; -+} -+ - static int dpaa2_eth_stop(struct net_device *net_dev) - { - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ int dpni_enabled; -+ int retries = 10; -+ u32 drained; - -- /* Stop Tx and Rx traffic */ - netif_tx_stop_all_queues(net_dev); - netif_carrier_off(net_dev); -- dpni_disable(priv->mc_io, 0, priv->mc_token); - -- msleep(500); -+ /* Loop while dpni_disable() attempts to drain the egress FQs -+ * and confirm them back to us. -+ */ -+ do { -+ dpni_disable(priv->mc_io, 0, priv->mc_token); -+ dpni_is_enabled(priv->mc_io, 0, priv->mc_token, &dpni_enabled); -+ if (dpni_enabled) -+ /* Allow the MC some slack */ -+ msleep(100); -+ } while (dpni_enabled && --retries); -+ if (!retries) { -+ netdev_warn(net_dev, "Retry count exceeded disabling DPNI\n"); -+ /* Must go on and disable NAPI nonetheless, so we don't crash at -+ * the next "ifconfig up" -+ */ -+ } - -- dpaa2_eth_napi_disable(priv); -- msleep(100); -+ /* Wait for NAPI to complete on every core and disable it. -+ * In particular, this will also prevent NAPI from being rescheduled if -+ * a new CDAN is serviced, effectively discarding the CDAN. We therefore -+ * don't even need to disarm the channels, except perhaps for the case -+ * of a huge coalescing value. -+ */ -+ disable_ch_napi(priv); -+ -+ /* Manually drain the Rx and TxConf queues */ -+ drained = drain_ingress_frames(priv); -+ if (drained) -+ netdev_dbg(net_dev, "Drained %d frames.\n", drained); - -- __dpaa2_dpbp_free(priv); -+ /* Empty the buffer pool */ -+ drain_pool(priv); - - return 0; - } -@@ -1138,7 +1172,7 @@ static int dpaa2_eth_init(struct net_dev - { - u64 supported = 0; - u64 not_supported = 0; -- const struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -+ struct dpaa2_eth_priv *priv = netdev_priv(net_dev); - u32 options = priv->dpni_attrs.options; - - /* Capabilities listing */ -@@ -1230,7 +1264,7 @@ static int dpaa2_eth_change_mtu(struct n - err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token, - (u16)DPAA2_ETH_L2_MAX_FRM(mtu)); - if (err) { -- netdev_err(net_dev, "dpni_set_mfl() failed\n"); -+ netdev_err(net_dev, "dpni_set_max_frame_length() failed\n"); - return err; - } - -@@ -1238,18 +1272,11 @@ static int dpaa2_eth_change_mtu(struct n - return 0; - } - --/* Convenience macro to make code littered with error checking more readable */ --#define DPAA2_ETH_WARN_IF_ERR(err, netdevp, format, ...) \ --do { \ -- if (err) \ -- netdev_warn(netdevp, format, ##__VA_ARGS__); \ --} while (0) -- - /* Copy mac unicast addresses from @net_dev to @priv. - * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable. - */ --static void _dpaa2_eth_hw_add_uc_addr(const struct net_device *net_dev, -- struct dpaa2_eth_priv *priv) -+static void add_uc_hw_addr(const struct net_device *net_dev, -+ struct dpaa2_eth_priv *priv) - { - struct netdev_hw_addr *ha; - int err; -@@ -1257,17 +1284,18 @@ static void _dpaa2_eth_hw_add_uc_addr(co - netdev_for_each_uc_addr(ha, net_dev) { - err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, - ha->addr); -- DPAA2_ETH_WARN_IF_ERR(err, priv->net_dev, -- "Could not add ucast MAC %pM to the filtering table (err %d)\n", -- ha->addr, err); -+ if (err) -+ netdev_warn(priv->net_dev, -+ "Could not add ucast MAC %pM to the filtering table (err %d)\n", -+ ha->addr, err); - } - } - - /* Copy mac multicast addresses from @net_dev to @priv - * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable. - */ --static void _dpaa2_eth_hw_add_mc_addr(const struct net_device *net_dev, -- struct dpaa2_eth_priv *priv) -+static void add_mc_hw_addr(const struct net_device *net_dev, -+ struct dpaa2_eth_priv *priv) - { - struct netdev_hw_addr *ha; - int err; -@@ -1275,9 +1303,10 @@ static void _dpaa2_eth_hw_add_mc_addr(co - netdev_for_each_mc_addr(ha, net_dev) { - err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, - ha->addr); -- DPAA2_ETH_WARN_IF_ERR(err, priv->net_dev, -- "Could not add mcast MAC %pM to the filtering table (err %d)\n", -- ha->addr, err); -+ if (err) -+ netdev_warn(priv->net_dev, -+ "Could not add mcast MAC %pM to the filtering table (err %d)\n", -+ ha->addr, err); - } - } - -@@ -1296,11 +1325,11 @@ static void dpaa2_eth_set_rx_mode(struct - /* Basic sanity checks; these probably indicate a misconfiguration */ - if (!(options & DPNI_OPT_UNICAST_FILTER) && max_uc != 0) - netdev_info(net_dev, -- "max_unicast_filters=%d, you must have DPNI_OPT_UNICAST_FILTER in the DPL\n", -+ "max_unicast_filters=%d, DPNI_OPT_UNICAST_FILTER option must be enabled\n", - max_uc); - if (!(options & DPNI_OPT_MULTICAST_FILTER) && max_mc != 0) - netdev_info(net_dev, -- "max_multicast_filters=%d, you must have DPNI_OPT_MULTICAST_FILTER in the DPL\n", -+ "max_multicast_filters=%d, DPNI_OPT_MULTICAST_FILTER option must be enabled\n", - max_mc); - - /* Force promiscuous if the uc or mc counts exceed our capabilities. */ -@@ -1318,9 +1347,9 @@ static void dpaa2_eth_set_rx_mode(struct - } - - /* Adjust promisc settings due to flag combinations */ -- if (net_dev->flags & IFF_PROMISC) { -+ if (net_dev->flags & IFF_PROMISC) - goto force_promisc; -- } else if (net_dev->flags & IFF_ALLMULTI) { -+ if (net_dev->flags & IFF_ALLMULTI) { - /* First, rebuild unicast filtering table. This should be done - * in promisc mode, in order to avoid frame loss while we - * progressively add entries to the table. -@@ -1329,16 +1358,19 @@ static void dpaa2_eth_set_rx_mode(struct - * nonetheless. - */ - err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1); -- DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't set uc promisc\n"); -+ if (err) -+ netdev_warn(net_dev, "Can't set uc promisc\n"); - - /* Actual uc table reconstruction. */ - err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 0); -- DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't clear uc filters\n"); -- _dpaa2_eth_hw_add_uc_addr(net_dev, priv); -+ if (err) -+ netdev_warn(net_dev, "Can't clear uc filters\n"); -+ add_uc_hw_addr(net_dev, priv); - - /* Finally, clear uc promisc and set mc promisc as requested. */ - err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0); -- DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't clear uc promisc\n"); -+ if (err) -+ netdev_warn(net_dev, "Can't clear uc promisc\n"); - goto force_mc_promisc; - } - -@@ -1346,32 +1378,39 @@ static void dpaa2_eth_set_rx_mode(struct - * For now, rebuild mac filtering tables while forcing both of them on. - */ - err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1); -- DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't set uc promisc (%d)\n", err); -+ if (err) -+ netdev_warn(net_dev, "Can't set uc promisc (%d)\n", err); - err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1); -- DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't set mc promisc (%d)\n", err); -+ if (err) -+ netdev_warn(net_dev, "Can't set mc promisc (%d)\n", err); - - /* Actual mac filtering tables reconstruction */ - err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 1); -- DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't clear mac filters\n"); -- _dpaa2_eth_hw_add_mc_addr(net_dev, priv); -- _dpaa2_eth_hw_add_uc_addr(net_dev, priv); -+ if (err) -+ netdev_warn(net_dev, "Can't clear mac filters\n"); -+ add_mc_hw_addr(net_dev, priv); -+ add_uc_hw_addr(net_dev, priv); - - /* Now we can clear both ucast and mcast promisc, without risking - * to drop legitimate frames anymore. - */ - err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0); -- DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't clear ucast promisc\n"); -+ if (err) -+ netdev_warn(net_dev, "Can't clear ucast promisc\n"); - err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 0); -- DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't clear mcast promisc\n"); -+ if (err) -+ netdev_warn(net_dev, "Can't clear mcast promisc\n"); - - return; - - force_promisc: - err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1); -- DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't set ucast promisc\n"); -+ if (err) -+ netdev_warn(net_dev, "Can't set ucast promisc\n"); - force_mc_promisc: - err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1); -- DPAA2_ETH_WARN_IF_ERR(err, net_dev, "Can't set mcast promisc\n"); -+ if (err) -+ netdev_warn(net_dev, "Can't set mcast promisc\n"); - } - - static int dpaa2_eth_set_features(struct net_device *net_dev, -@@ -1379,20 +1418,19 @@ static int dpaa2_eth_set_features(struct - { - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); - netdev_features_t changed = features ^ net_dev->features; -+ bool enable; - int err; - - if (changed & NETIF_F_RXCSUM) { -- bool enable = !!(features & NETIF_F_RXCSUM); -- -- err = dpaa2_eth_set_rx_csum(priv, enable); -+ enable = !!(features & NETIF_F_RXCSUM); -+ err = set_rx_csum(priv, enable); - if (err) - return err; - } - - if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) { -- bool enable = !!(features & -- (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); -- err = dpaa2_eth_set_tx_csum(priv, enable); -+ enable = !!(features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); -+ err = set_tx_csum(priv, enable); - if (err) - return err; - } -@@ -1419,9 +1457,9 @@ static int dpaa2_eth_ts_ioctl(struct net - return -ERANGE; - } - -- if (config.rx_filter == HWTSTAMP_FILTER_NONE) -+ if (config.rx_filter == HWTSTAMP_FILTER_NONE) { - priv->ts_rx_en = false; -- else { -+ } else { - priv->ts_rx_en = true; - /* TS is set for all frame types, not only those requested */ - config.rx_filter = HWTSTAMP_FILTER_ALL; -@@ -1435,8 +1473,8 @@ static int dpaa2_eth_ioctl(struct net_de - { - if (cmd == SIOCSHWTSTAMP) - return dpaa2_eth_ts_ioctl(dev, rq, cmd); -- else -- return -EINVAL; -+ -+ return -EINVAL; - } - - static const struct net_device_ops dpaa2_eth_ops = { -@@ -1452,7 +1490,7 @@ static const struct net_device_ops dpaa2 - .ndo_do_ioctl = dpaa2_eth_ioctl, - }; - --static void dpaa2_eth_cdan_cb(struct dpaa2_io_notification_ctx *ctx) -+static void cdan_cb(struct dpaa2_io_notification_ctx *ctx) - { - struct dpaa2_eth_channel *ch; - -@@ -1464,37 +1502,9 @@ static void dpaa2_eth_cdan_cb(struct dpa - napi_schedule_irqoff(&ch->napi); - } - --static void dpaa2_eth_setup_fqs(struct dpaa2_eth_priv *priv) --{ -- int i; -- -- /* We have one TxConf FQ per Tx flow */ -- for (i = 0; i < priv->dpni_attrs.max_senders; i++) { -- priv->fq[priv->num_fqs].netdev_priv = priv; -- priv->fq[priv->num_fqs].type = DPAA2_TX_CONF_FQ; -- priv->fq[priv->num_fqs].consume = dpaa2_eth_tx_conf; -- priv->fq[priv->num_fqs++].flowid = DPNI_NEW_FLOW_ID; -- } -- -- /* The number of Rx queues (Rx distribution width) may be different from -- * the number of cores. -- * We only support one traffic class for now. -- */ -- for (i = 0; i < dpaa2_queue_count(priv); i++) { -- priv->fq[priv->num_fqs].netdev_priv = priv; -- priv->fq[priv->num_fqs].type = DPAA2_RX_FQ; -- priv->fq[priv->num_fqs].consume = dpaa2_eth_rx; -- priv->fq[priv->num_fqs++].flowid = (u16)i; -- } -- --#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE -- /* We have exactly one Rx error queue per DPNI */ -- priv->fq[priv->num_fqs].netdev_priv = priv; -- priv->fq[priv->num_fqs].type = DPAA2_RX_ERR_FQ; -- priv->fq[priv->num_fqs++].consume = dpaa2_eth_rx_err; --#endif --} -- -+/* Verify that the FLIB API version of various MC objects is supported -+ * by our driver -+ */ - static int check_obj_version(struct fsl_mc_device *ls_dev, u16 mc_version) - { - char *name = ls_dev->obj_desc.type; -@@ -1517,8 +1527,7 @@ static int check_obj_version(struct fsl_ - - /* Check that the FLIB-defined version matches the one reported by MC */ - if (mc_version != flib_version) { -- dev_err(dev, -- "%s FLIB version mismatch: MC reports %d, we have %d\n", -+ dev_err(dev, "%s FLIB version mismatch: MC reports %d, we have %d\n", - name, mc_version, flib_version); - return -EINVAL; - } -@@ -1534,7 +1543,8 @@ static int check_obj_version(struct fsl_ - return 0; - } - --static struct fsl_mc_device *dpaa2_dpcon_setup(struct dpaa2_eth_priv *priv) -+/* Allocate and configure a DPCON object */ -+static struct fsl_mc_device *setup_dpcon(struct dpaa2_eth_priv *priv) - { - struct fsl_mc_device *dpcon; - struct device *dev = priv->net_dev->dev.parent; -@@ -1582,8 +1592,8 @@ err_open: - return NULL; - } - --static void dpaa2_dpcon_free(struct dpaa2_eth_priv *priv, -- struct fsl_mc_device *dpcon) -+static void free_dpcon(struct dpaa2_eth_priv *priv, -+ struct fsl_mc_device *dpcon) - { - dpcon_disable(priv->mc_io, 0, dpcon->mc_handle); - dpcon_close(priv->mc_io, 0, dpcon->mc_handle); -@@ -1591,7 +1601,7 @@ static void dpaa2_dpcon_free(struct dpaa - } - - static struct dpaa2_eth_channel * --dpaa2_alloc_channel(struct dpaa2_eth_priv *priv) -+alloc_channel(struct dpaa2_eth_priv *priv) - { - struct dpaa2_eth_channel *channel; - struct dpcon_attr attr; -@@ -1599,12 +1609,10 @@ dpaa2_alloc_channel(struct dpaa2_eth_pri - int err; - - channel = kzalloc(sizeof(*channel), GFP_ATOMIC); -- if (!channel) { -- dev_err(dev, "Memory allocation failed\n"); -+ if (!channel) - return NULL; -- } - -- channel->dpcon = dpaa2_dpcon_setup(priv); -+ channel->dpcon = setup_dpcon(priv); - if (!channel->dpcon) - goto err_setup; - -@@ -1622,20 +1630,23 @@ dpaa2_alloc_channel(struct dpaa2_eth_pri - return channel; - - err_get_attr: -- dpaa2_dpcon_free(priv, channel->dpcon); -+ free_dpcon(priv, channel->dpcon); - err_setup: - kfree(channel); - return NULL; - } - --static void dpaa2_free_channel(struct dpaa2_eth_priv *priv, -- struct dpaa2_eth_channel *channel) -+static void free_channel(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_channel *channel) - { -- dpaa2_dpcon_free(priv, channel->dpcon); -+ free_dpcon(priv, channel->dpcon); - kfree(channel); - } - --static int dpaa2_dpio_setup(struct dpaa2_eth_priv *priv) -+/* DPIO setup: allocate and configure QBMan channels, setup core affinity -+ * and register data availability notifications -+ */ -+static int setup_dpio(struct dpaa2_eth_priv *priv) - { - struct dpaa2_io_notification_ctx *nctx; - struct dpaa2_eth_channel *channel; -@@ -1652,7 +1663,7 @@ static int dpaa2_dpio_setup(struct dpaa2 - cpumask_clear(&priv->dpio_cpumask); - for_each_online_cpu(i) { - /* Try to allocate a channel */ -- channel = dpaa2_alloc_channel(priv); -+ channel = alloc_channel(priv); - if (!channel) - goto err_alloc_ch; - -@@ -1660,7 +1671,7 @@ static int dpaa2_dpio_setup(struct dpaa2 - - nctx = &channel->nctx; - nctx->is_cdan = 1; -- nctx->cb = dpaa2_eth_cdan_cb; -+ nctx->cb = cdan_cb; - nctx->id = channel->ch_id; - nctx->desired_cpu = i; - -@@ -1671,7 +1682,7 @@ static int dpaa2_dpio_setup(struct dpaa2 - /* This core doesn't have an affine DPIO, but there's - * a chance another one does, so keep trying - */ -- dpaa2_free_channel(priv, channel); -+ free_channel(priv, channel); - continue; - } - -@@ -1693,7 +1704,7 @@ static int dpaa2_dpio_setup(struct dpaa2 - cpumask_set_cpu(i, &priv->dpio_cpumask); - priv->num_channels++; - -- if (priv->num_channels == dpaa2_max_channels(priv)) -+ if (priv->num_channels == dpaa2_eth_max_channels(priv)) - break; - } - -@@ -1706,7 +1717,7 @@ static int dpaa2_dpio_setup(struct dpaa2 - - err_set_cdan: - dpaa2_io_service_deregister(NULL, nctx); -- dpaa2_free_channel(priv, channel); -+ free_channel(priv, channel); - err_alloc_ch: - if (cpumask_empty(&priv->dpio_cpumask)) { - dev_err(dev, "No cpu with an affine DPIO/DPCON\n"); -@@ -1717,7 +1728,7 @@ err_alloc_ch: - return 0; - } - --static void dpaa2_dpio_free(struct dpaa2_eth_priv *priv) -+static void free_dpio(struct dpaa2_eth_priv *priv) - { - int i; - struct dpaa2_eth_channel *ch; -@@ -1726,12 +1737,12 @@ static void dpaa2_dpio_free(struct dpaa2 - for (i = 0; i < priv->num_channels; i++) { - ch = priv->channel[i]; - dpaa2_io_service_deregister(NULL, &ch->nctx); -- dpaa2_free_channel(priv, ch); -+ free_channel(priv, ch); - } - } - --static struct dpaa2_eth_channel * --dpaa2_get_channel_by_cpu(struct dpaa2_eth_priv *priv, int cpu) -+static struct dpaa2_eth_channel *get_affine_channel(struct dpaa2_eth_priv *priv, -+ int cpu) - { - struct device *dev = priv->net_dev->dev.parent; - int i; -@@ -1748,11 +1759,11 @@ dpaa2_get_channel_by_cpu(struct dpaa2_et - return priv->channel[0]; - } - --static void dpaa2_set_fq_affinity(struct dpaa2_eth_priv *priv) -+static void set_fq_affinity(struct dpaa2_eth_priv *priv) - { - struct device *dev = priv->net_dev->dev.parent; - struct dpaa2_eth_fq *fq; -- int rx_cpu, txconf_cpu; -+ int rx_cpu, txc_cpu; - int i; - - /* For each FQ, pick one channel/CPU to deliver frames to. -@@ -1760,7 +1771,7 @@ static void dpaa2_set_fq_affinity(struct - * through direct user intervention. - */ - rx_cpu = cpumask_first(&priv->dpio_cpumask); -- txconf_cpu = cpumask_first(&priv->txconf_cpumask); -+ txc_cpu = cpumask_first(&priv->txconf_cpumask); - - for (i = 0; i < priv->num_fqs; i++) { - fq = &priv->fq[i]; -@@ -1768,20 +1779,56 @@ static void dpaa2_set_fq_affinity(struct - case DPAA2_RX_FQ: - case DPAA2_RX_ERR_FQ: - fq->target_cpu = rx_cpu; -- cpumask_rr(rx_cpu, &priv->dpio_cpumask); -+ rx_cpu = cpumask_next(rx_cpu, &priv->dpio_cpumask); -+ if (rx_cpu >= nr_cpu_ids) -+ rx_cpu = cpumask_first(&priv->dpio_cpumask); - break; - case DPAA2_TX_CONF_FQ: -- fq->target_cpu = txconf_cpu; -- cpumask_rr(txconf_cpu, &priv->txconf_cpumask); -+ fq->target_cpu = txc_cpu; -+ txc_cpu = cpumask_next(txc_cpu, &priv->txconf_cpumask); -+ if (txc_cpu >= nr_cpu_ids) -+ txc_cpu = cpumask_first(&priv->txconf_cpumask); - break; - default: - dev_err(dev, "Unknown FQ type: %d\n", fq->type); - } -- fq->channel = dpaa2_get_channel_by_cpu(priv, fq->target_cpu); -+ fq->channel = get_affine_channel(priv, fq->target_cpu); -+ } -+} -+ -+static void setup_fqs(struct dpaa2_eth_priv *priv) -+{ -+ int i; -+ -+ /* We have one TxConf FQ per Tx flow */ -+ for (i = 0; i < priv->dpni_attrs.max_senders; i++) { -+ priv->fq[priv->num_fqs].type = DPAA2_TX_CONF_FQ; -+ priv->fq[priv->num_fqs].consume = dpaa2_eth_tx_conf; -+ priv->fq[priv->num_fqs++].flowid = DPNI_NEW_FLOW_ID; -+ } -+ -+ /* The number of Rx queues (Rx distribution width) may be different from -+ * the number of cores. -+ * We only support one traffic class for now. -+ */ -+ for (i = 0; i < dpaa2_eth_queue_count(priv); i++) { -+ priv->fq[priv->num_fqs].type = DPAA2_RX_FQ; -+ priv->fq[priv->num_fqs].consume = dpaa2_eth_rx; -+ priv->fq[priv->num_fqs++].flowid = (u16)i; - } -+ -+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE -+ /* We have exactly one Rx error queue per DPNI */ -+ priv->fq[priv->num_fqs].type = DPAA2_RX_ERR_FQ; -+ priv->fq[priv->num_fqs++].consume = dpaa2_eth_rx_err; -+#endif -+ -+ /* For each FQ, decide on which core to process incoming frames */ -+ set_fq_affinity(priv); - } - --static int dpaa2_dpbp_setup(struct dpaa2_eth_priv *priv) -+/* Allocate and configure one buffer pool for each interface */ -+static int setup_dpbp(struct dpaa2_eth_priv *priv) - { - int err; - struct fsl_mc_device *dpbp_dev; -@@ -1833,15 +1880,16 @@ err_open: - return err; - } - --static void dpaa2_dpbp_free(struct dpaa2_eth_priv *priv) -+static void free_dpbp(struct dpaa2_eth_priv *priv) - { -- __dpaa2_dpbp_free(priv); -+ drain_pool(priv); - dpbp_disable(priv->mc_io, 0, priv->dpbp_dev->mc_handle); - dpbp_close(priv->mc_io, 0, priv->dpbp_dev->mc_handle); - fsl_mc_object_free(priv->dpbp_dev); - } - --static int dpaa2_dpni_setup(struct fsl_mc_device *ls_dev) -+/* Configure the DPNI object this interface is associated with */ -+static int setup_dpni(struct fsl_mc_device *ls_dev) - { - struct device *dev = &ls_dev->dev; - struct dpaa2_eth_priv *priv; -@@ -1854,7 +1902,7 @@ static int dpaa2_dpni_setup(struct fsl_m - - priv->dpni_id = ls_dev->obj_desc.id; - -- /* and get a handle for the DPNI this interface is associate with */ -+ /* get a handle for the DPNI object */ - err = dpni_open(priv->mc_io, 0, priv->dpni_id, &priv->mc_token); - if (err) { - dev_err(dev, "dpni_open() failed\n"); -@@ -1864,7 +1912,10 @@ static int dpaa2_dpni_setup(struct fsl_m - ls_dev->mc_io = priv->mc_io; - ls_dev->mc_handle = priv->mc_token; - -- dma_mem = kzalloc(DPAA2_EXT_CFG_SIZE, GFP_DMA | GFP_KERNEL); -+ /* Map a memory region which will be used by MC to pass us an -+ * attribute structure -+ */ -+ dma_mem = kzalloc(DPAA2_EXT_CFG_SIZE, GFP_DMA | GFP_KERNEL); - if (!dma_mem) - goto err_alloc; - -@@ -1878,10 +1929,15 @@ static int dpaa2_dpni_setup(struct fsl_m - - err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token, - &priv->dpni_attrs); -+ -+ /* We'll check the return code after unmapping, as we need to -+ * do this anyway -+ */ -+ dma_unmap_single(dev, priv->dpni_attrs.ext_cfg_iova, -+ DPAA2_EXT_CFG_SIZE, DMA_FROM_DEVICE); -+ - if (err) { - dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err); -- dma_unmap_single(dev, priv->dpni_attrs.ext_cfg_iova, -- DPAA2_EXT_CFG_SIZE, DMA_FROM_DEVICE); - goto err_get_attr; - } - -@@ -1889,9 +1945,6 @@ static int dpaa2_dpni_setup(struct fsl_m - if (err) - goto err_dpni_ver; - -- dma_unmap_single(dev, priv->dpni_attrs.ext_cfg_iova, -- DPAA2_EXT_CFG_SIZE, DMA_FROM_DEVICE); -- - memset(&priv->dpni_ext_cfg, 0, sizeof(priv->dpni_ext_cfg)); - err = dpni_extract_extended_cfg(&priv->dpni_ext_cfg, dma_mem); - if (err) { -@@ -1909,15 +1962,15 @@ static int dpaa2_dpni_setup(struct fsl_m - priv->buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE; - /* HW erratum mandates data alignment in multiples of 256 */ - priv->buf_layout.data_align = DPAA2_ETH_RX_BUF_ALIGN; -- /* ...rx, ... */ -+ -+ /* rx buffer */ - err = dpni_set_rx_buffer_layout(priv->mc_io, 0, priv->mc_token, - &priv->buf_layout); - if (err) { - dev_err(dev, "dpni_set_rx_buffer_layout() failed"); - goto err_buf_layout; - } -- /* ... tx, ... */ -- /* remove Rx-only options */ -+ /* tx buffer: remove Rx-only options */ - priv->buf_layout.options &= ~(DPNI_BUF_LAYOUT_OPT_DATA_ALIGN | - DPNI_BUF_LAYOUT_OPT_PARSER_RESULT); - err = dpni_set_tx_buffer_layout(priv->mc_io, 0, priv->mc_token, -@@ -1926,7 +1979,7 @@ static int dpaa2_dpni_setup(struct fsl_m - dev_err(dev, "dpni_set_tx_buffer_layout() failed"); - goto err_buf_layout; - } -- /* ... tx-confirm. */ -+ /* tx-confirm: same options as tx */ - priv->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE; - priv->buf_layout.options |= DPNI_BUF_LAYOUT_OPT_TIMESTAMP; - priv->buf_layout.pass_timestamp = 1; -@@ -1946,8 +1999,9 @@ static int dpaa2_dpni_setup(struct fsl_m - goto err_data_offset; - } - -- /* Warn in case TX data offset is not multiple of 64 bytes. */ -- WARN_ON(priv->tx_data_offset % 64); -+ if ((priv->tx_data_offset % 64) != 0) -+ dev_warn(dev, "Tx data offset (%d) not a multiple of 64B", -+ priv->tx_data_offset); - - /* Accommodate SWA space. */ - priv->tx_data_offset += DPAA2_ETH_SWA_SIZE; -@@ -1976,7 +2030,7 @@ err_open: - return err; - } - --static void dpaa2_dpni_free(struct dpaa2_eth_priv *priv) -+static void free_dpni(struct dpaa2_eth_priv *priv) - { - int err; - -@@ -1988,8 +2042,8 @@ static void dpaa2_dpni_free(struct dpaa2 - dpni_close(priv->mc_io, 0, priv->mc_token); - } - --static int dpaa2_rx_flow_setup(struct dpaa2_eth_priv *priv, -- struct dpaa2_eth_fq *fq) -+static int setup_rx_flow(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_fq *fq) - { - struct device *dev = priv->net_dev->dev.parent; - struct dpni_queue_attr rx_queue_attr; -@@ -2023,8 +2077,8 @@ static int dpaa2_rx_flow_setup(struct dp - return 0; - } - --static int dpaa2_tx_flow_setup(struct dpaa2_eth_priv *priv, -- struct dpaa2_eth_fq *fq) -+static int setup_tx_flow(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_fq *fq) - { - struct device *dev = priv->net_dev->dev.parent; - struct dpni_tx_flow_cfg tx_flow_cfg; -@@ -2070,15 +2124,16 @@ static int dpaa2_tx_flow_setup(struct dp - } - - #ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE --static int dpaa2_rx_err_setup(struct dpaa2_eth_priv *priv, -- struct dpaa2_eth_fq *fq) -+static int setup_rx_err_flow(struct dpaa2_eth_priv *priv, -+ struct dpaa2_eth_fq *fq) - { - struct dpni_queue_attr queue_attr; - struct dpni_queue_cfg queue_cfg; - int err; - - /* Configure the Rx error queue to generate CDANs, -- * just like the Rx queues */ -+ * just like the Rx queues -+ */ - queue_cfg.options = DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST; - queue_cfg.dest_cfg.dest_type = DPNI_DEST_DPCON; - queue_cfg.dest_cfg.priority = 1; -@@ -2091,7 +2146,8 @@ static int dpaa2_rx_err_setup(struct dpa - } - - /* Get the FQID */ -- err = dpni_get_rx_err_queue(priv->mc_io, 0, priv->mc_token, &queue_attr); -+ err = dpni_get_rx_err_queue(priv->mc_io, 0, priv->mc_token, -+ &queue_attr); - if (err) { - netdev_err(priv->net_dev, "dpni_get_rx_err_queue() failed\n"); - return err; -@@ -2102,7 +2158,10 @@ static int dpaa2_rx_err_setup(struct dpa - } - #endif - --static int dpaa2_dpni_bind(struct dpaa2_eth_priv *priv) -+/* Bind the DPNI to its needed objects and resources: buffer pool, DPIOs, -+ * frame queues and channels -+ */ -+static int bind_dpni(struct dpaa2_eth_priv *priv) - { - struct net_device *net_dev = priv->net_dev; - struct device *dev = net_dev->dev.parent; -@@ -2114,20 +2173,20 @@ static int dpaa2_dpni_bind(struct dpaa2_ - pools_params.num_dpbp = 1; - pools_params.pools[0].dpbp_id = priv->dpbp_dev->obj_desc.id; - pools_params.pools[0].backup_pool = 0; -- pools_params.pools[0].buffer_size = DPAA2_ETH_RX_BUFFER_SIZE; -+ pools_params.pools[0].buffer_size = DPAA2_ETH_RX_BUF_SIZE; - err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params); - if (err) { - dev_err(dev, "dpni_set_pools() failed\n"); - return err; - } - -- dpaa2_cls_check(net_dev); -+ check_fs_support(net_dev); - - /* have the interface implicitly distribute traffic based on supported - * header fields - */ - if (dpaa2_eth_hash_enabled(priv)) { -- err = dpaa2_set_hash(net_dev, DPAA2_RXH_SUPPORTED); -+ err = dpaa2_eth_set_hash(net_dev, DPAA2_RXH_SUPPORTED); - if (err) - return err; - } -@@ -2151,14 +2210,14 @@ static int dpaa2_dpni_bind(struct dpaa2_ - for (i = 0; i < priv->num_fqs; i++) { - switch (priv->fq[i].type) { - case DPAA2_RX_FQ: -- err = dpaa2_rx_flow_setup(priv, &priv->fq[i]); -+ err = setup_rx_flow(priv, &priv->fq[i]); - break; - case DPAA2_TX_CONF_FQ: -- err = dpaa2_tx_flow_setup(priv, &priv->fq[i]); -+ err = setup_tx_flow(priv, &priv->fq[i]); - break; - #ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE - case DPAA2_RX_ERR_FQ: -- err = dpaa2_rx_err_setup(priv, &priv->fq[i]); -+ err = setup_rx_err_flow(priv, &priv->fq[i]); - break; - #endif - default: -@@ -2178,7 +2237,8 @@ static int dpaa2_dpni_bind(struct dpaa2_ - return 0; - } - --static int dpaa2_eth_alloc_rings(struct dpaa2_eth_priv *priv) -+/* Allocate rings for storing incoming frame descriptors */ -+static int alloc_rings(struct dpaa2_eth_priv *priv) - { - struct net_device *net_dev = priv->net_dev; - struct device *dev = net_dev->dev.parent; -@@ -2205,7 +2265,7 @@ err_ring: - return -ENOMEM; - } - --static void dpaa2_eth_free_rings(struct dpaa2_eth_priv *priv) -+static void free_rings(struct dpaa2_eth_priv *priv) - { - int i; - -@@ -2213,7 +2273,7 @@ static void dpaa2_eth_free_rings(struct - dpaa2_io_store_destroy(priv->channel[i]->store); - } - --static int dpaa2_eth_netdev_init(struct net_device *net_dev) -+static int netdev_init(struct net_device *net_dev) - { - int err; - struct device *dev = net_dev->dev.parent; -@@ -2223,7 +2283,9 @@ static int dpaa2_eth_netdev_init(struct - - net_dev->netdev_ops = &dpaa2_eth_ops; - -- /* If the DPL contains all-0 mac_addr, set a random hardware address */ -+ /* If the DPNI attributes contain an all-0 mac_addr, -+ * set a random hardware address -+ */ - err = dpni_get_primary_mac_addr(priv->mc_io, 0, priv->mc_token, - mac_addr); - if (err) { -@@ -2281,14 +2343,13 @@ static int dpaa2_eth_netdev_init(struct - return 0; - } - --#ifdef CONFIG_FSL_DPAA2_ETH_LINK_POLL --static int dpaa2_poll_link_state(void *arg) -+static int poll_link_state(void *arg) - { - struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)arg; - int err; - - while (!kthread_should_stop()) { -- err = dpaa2_link_state_update(priv); -+ err = link_state_update(priv); - if (unlikely(err)) - return err; - -@@ -2297,7 +2358,7 @@ static int dpaa2_poll_link_state(void *a - - return 0; - } --#else -+ - static irqreturn_t dpni_irq0_handler(int irq_num, void *arg) - { - return IRQ_WAKE_THREAD; -@@ -2312,7 +2373,6 @@ static irqreturn_t dpni_irq0_handler_thr - struct net_device *net_dev = dev_get_drvdata(dev); - int err; - -- netdev_dbg(net_dev, "IRQ %d received\n", irq_num); - err = dpni_get_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle, - irq_index, &status); - if (unlikely(err)) { -@@ -2323,7 +2383,7 @@ static irqreturn_t dpni_irq0_handler_thr - - if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { - clear |= DPNI_IRQ_EVENT_LINK_CHANGED; -- dpaa2_link_state_update(netdev_priv(net_dev)); -+ link_state_update(netdev_priv(net_dev)); - } - - out: -@@ -2332,17 +2392,18 @@ out: - return IRQ_HANDLED; - } - --static int dpaa2_eth_setup_irqs(struct fsl_mc_device *ls_dev) -+static int setup_irqs(struct fsl_mc_device *ls_dev) - { - int err = 0; - struct fsl_mc_device_irq *irq; -- int irq_count = ls_dev->obj_desc.irq_count; - u8 irq_index = DPNI_IRQ_INDEX; - u32 mask = DPNI_IRQ_EVENT_LINK_CHANGED; - -- /* The only interrupt supported now is the link state notification. */ -- if (WARN_ON(irq_count != 1)) -- return -EINVAL; -+ err = fsl_mc_allocate_irqs(ls_dev); -+ if (err) { -+ dev_err(&ls_dev->dev, "MC irqs allocation failed\n"); -+ return err; -+ } - - irq = ls_dev->irqs[0]; - err = devm_request_threaded_irq(&ls_dev->dev, irq->msi_desc->irq, -@@ -2352,28 +2413,34 @@ static int dpaa2_eth_setup_irqs(struct f - dev_name(&ls_dev->dev), &ls_dev->dev); - if (err < 0) { - dev_err(&ls_dev->dev, "devm_request_threaded_irq(): %d", err); -- return err; -+ goto free_mc_irq; - } - - err = dpni_set_irq_mask(ls_dev->mc_io, 0, ls_dev->mc_handle, - irq_index, mask); - if (err < 0) { - dev_err(&ls_dev->dev, "dpni_set_irq_mask(): %d", err); -- return err; -+ goto free_irq; - } - - err = dpni_set_irq_enable(ls_dev->mc_io, 0, ls_dev->mc_handle, - irq_index, 1); - if (err < 0) { - dev_err(&ls_dev->dev, "dpni_set_irq_enable(): %d", err); -- return err; -+ goto free_irq; - } - - return 0; -+ -+free_irq: -+ devm_free_irq(&ls_dev->dev, irq->msi_desc->irq, &ls_dev->dev); -+free_mc_irq: -+ fsl_mc_free_irqs(ls_dev); -+ -+ return err; - } --#endif - --static void dpaa2_eth_napi_add(struct dpaa2_eth_priv *priv) -+static void add_ch_napi(struct dpaa2_eth_priv *priv) - { - int i; - struct dpaa2_eth_channel *ch; -@@ -2386,7 +2453,7 @@ static void dpaa2_eth_napi_add(struct dp - } - } - --static void dpaa2_eth_napi_del(struct dpaa2_eth_priv *priv) -+static void del_ch_napi(struct dpaa2_eth_priv *priv) - { - int i; - struct dpaa2_eth_channel *ch; -@@ -2398,7 +2465,6 @@ static void dpaa2_eth_napi_del(struct dp - } - - /* SysFS support */ -- - static ssize_t dpaa2_eth_show_tx_shaping(struct device *dev, - struct device_attribute *attr, - char *buf) -@@ -2482,22 +2548,21 @@ static ssize_t dpaa2_eth_write_txconf_cp - } - - /* Set the new TxConf FQ affinities */ -- dpaa2_set_fq_affinity(priv); -+ set_fq_affinity(priv); - --#ifdef CONFIG_FSL_DPAA2_ETH_LINK_POLL - /* dpaa2_eth_open() below will *stop* the Tx queues until an explicit - * link up notification is received. Give the polling thread enough time - * to detect the link state change, or else we'll end up with the - * transmission side forever shut down. - */ -- msleep(2 * DPAA2_ETH_LINK_STATE_REFRESH); --#endif -+ if (priv->do_link_poll) -+ msleep(2 * DPAA2_ETH_LINK_STATE_REFRESH); - - for (i = 0; i < priv->num_fqs; i++) { - fq = &priv->fq[i]; - if (fq->type != DPAA2_TX_CONF_FQ) - continue; -- dpaa2_tx_flow_setup(priv, fq); -+ setup_tx_flow(priv, fq); - } - - if (running) { -@@ -2568,7 +2633,6 @@ static int dpaa2_eth_probe(struct fsl_mc - - priv = netdev_priv(net_dev); - priv->net_dev = net_dev; -- priv->msg_enable = netif_msg_init(debug, -1); - - /* Obtain a MC portal */ - err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL, -@@ -2578,39 +2642,27 @@ static int dpaa2_eth_probe(struct fsl_mc - goto err_portal_alloc; - } - --#ifndef CONFIG_FSL_DPAA2_ETH_LINK_POLL -- err = fsl_mc_allocate_irqs(dpni_dev); -- if (err) { -- dev_err(dev, "MC irqs allocation failed\n"); -- goto err_irqs_alloc; -- } --#endif -- -- /* DPNI initialization */ -- err = dpaa2_dpni_setup(dpni_dev); -- if (err < 0) -+ /* MC objects initialization and configuration */ -+ err = setup_dpni(dpni_dev); -+ if (err) - goto err_dpni_setup; - -- /* DPIO */ -- err = dpaa2_dpio_setup(priv); -+ err = setup_dpio(priv); - if (err) - goto err_dpio_setup; - -- /* FQs */ -- dpaa2_eth_setup_fqs(priv); -- dpaa2_set_fq_affinity(priv); -+ setup_fqs(priv); - -- /* DPBP */ -- err = dpaa2_dpbp_setup(priv); -+ err = setup_dpbp(priv); - if (err) - goto err_dpbp_setup; - -- /* DPNI binding to DPIO and DPBPs */ -- err = dpaa2_dpni_bind(priv); -+ err = bind_dpni(priv); - if (err) - goto err_bind; - -- dpaa2_eth_napi_add(priv); -+ /* Add a NAPI context for each channel */ -+ add_ch_napi(priv); - - /* Percpu statistics */ - priv->percpu_stats = alloc_percpu(*priv->percpu_stats); -@@ -2635,38 +2687,37 @@ static int dpaa2_eth_probe(struct fsl_mc - dev_warn(&net_dev->dev, "using name \"%s\"\n", net_dev->name); - } - -- err = dpaa2_eth_netdev_init(net_dev); -+ err = netdev_init(net_dev); - if (err) - goto err_netdev_init; - - /* Configure checksum offload based on current interface flags */ -- err = dpaa2_eth_set_rx_csum(priv, -- !!(net_dev->features & NETIF_F_RXCSUM)); -+ err = set_rx_csum(priv, !!(net_dev->features & NETIF_F_RXCSUM)); - if (err) - goto err_csum; - -- err = dpaa2_eth_set_tx_csum(priv, -- !!(net_dev->features & -- (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))); -+ err = set_tx_csum(priv, !!(net_dev->features & -+ (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))); - if (err) - goto err_csum; - -- err = dpaa2_eth_alloc_rings(priv); -+ err = alloc_rings(priv); - if (err) - goto err_alloc_rings; - - net_dev->ethtool_ops = &dpaa2_ethtool_ops; - --#ifdef CONFIG_FSL_DPAA2_ETH_LINK_POLL -- priv->poll_thread = kthread_run(dpaa2_poll_link_state, priv, -- "%s_poll_link", net_dev->name); --#else -- err = dpaa2_eth_setup_irqs(dpni_dev); -+ err = setup_irqs(dpni_dev); - if (err) { -- netdev_err(net_dev, "ERROR %d setting up interrupts", err); -- goto err_setup_irqs; -+ netdev_warn(net_dev, "Failed to set link interrupt, fall back to polling\n"); -+ priv->poll_thread = kthread_run(poll_link_state, priv, -+ "%s_poll_link", net_dev->name); -+ if (IS_ERR(priv->poll_thread)) { -+ netdev_err(net_dev, "Error starting polling thread\n"); -+ goto err_poll_thread; -+ } -+ priv->do_link_poll = true; - } --#endif - - dpaa2_eth_sysfs_init(&net_dev->dev); - dpaa2_dbg_add(priv); -@@ -2674,10 +2725,8 @@ static int dpaa2_eth_probe(struct fsl_mc - dev_info(dev, "Probed interface %s\n", net_dev->name); - return 0; - --#ifndef CONFIG_FSL_DPAA2_ETH_LINK_POLL --err_setup_irqs: --#endif -- dpaa2_eth_free_rings(priv); -+err_poll_thread: -+ free_rings(priv); - err_alloc_rings: - err_csum: - unregister_netdev(net_dev); -@@ -2686,19 +2735,15 @@ err_netdev_init: - err_alloc_percpu_extras: - free_percpu(priv->percpu_stats); - err_alloc_percpu_stats: -- dpaa2_eth_napi_del(priv); -+ del_ch_napi(priv); - err_bind: -- dpaa2_dpbp_free(priv); -+ free_dpbp(priv); - err_dpbp_setup: -- dpaa2_dpio_free(priv); -+ free_dpio(priv); - err_dpio_setup: - kfree(priv->cls_rule); - dpni_close(priv->mc_io, 0, priv->mc_token); - err_dpni_setup: --#ifndef CONFIG_FSL_DPAA2_ETH_LINK_POLL -- fsl_mc_free_irqs(dpni_dev); --err_irqs_alloc: --#endif - fsl_mc_portal_free(priv->mc_io); - err_portal_alloc: - dev_set_drvdata(dev, NULL); -@@ -2723,22 +2768,21 @@ static int dpaa2_eth_remove(struct fsl_m - unregister_netdev(net_dev); - dev_info(net_dev->dev.parent, "Removed interface %s\n", net_dev->name); - -- dpaa2_dpio_free(priv); -- dpaa2_eth_free_rings(priv); -- dpaa2_eth_napi_del(priv); -- dpaa2_dpbp_free(priv); -- dpaa2_dpni_free(priv); -+ free_dpio(priv); -+ free_rings(priv); -+ del_ch_napi(priv); -+ free_dpbp(priv); -+ free_dpni(priv); - - fsl_mc_portal_free(priv->mc_io); - - free_percpu(priv->percpu_stats); - free_percpu(priv->percpu_extras); - --#ifdef CONFIG_FSL_DPAA2_ETH_LINK_POLL -- kthread_stop(priv->poll_thread); --#else -- fsl_mc_free_irqs(ls_dev); --#endif -+ if (priv->do_link_poll) -+ kthread_stop(priv->poll_thread); -+ else -+ fsl_mc_free_irqs(ls_dev); - - kfree(priv->cls_rule); - ---- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h -@@ -49,8 +49,10 @@ - - #define DPAA2_ETH_STORE_SIZE 16 - --/* Maximum receive frame size is 64K */ --#define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUFFER_SIZE) -+/* Maximum number of scatter-gather entries in an ingress frame, -+ * considering the maximum receive frame size is 64K -+ */ -+#define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE) - - /* Maximum acceptable MTU value. It is in direct relation with the MC-enforced - * Max Frame Length (currently 10k). -@@ -75,17 +77,26 @@ - #define DPAA2_ETH_NUM_BUFS (DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256) - #define DPAA2_ETH_REFILL_THRESH DPAA2_ETH_MAX_FRAMES_PER_QUEUE - -+/* Maximum number of buffers that can be acquired/released through a single -+ * QBMan command -+ */ -+#define DPAA2_ETH_BUFS_PER_CMD 7 -+ - /* Hardware requires alignment for ingress/egress buffer addresses - * and ingress buffer lengths. - */ --#define DPAA2_ETH_RX_BUFFER_SIZE 2048 -+#define DPAA2_ETH_RX_BUF_SIZE 2048 - #define DPAA2_ETH_TX_BUF_ALIGN 64 - #define DPAA2_ETH_RX_BUF_ALIGN 256 - #define DPAA2_ETH_NEEDED_HEADROOM(p_priv) \ - ((p_priv)->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN) - -+/* Hardware only sees DPAA2_ETH_RX_BUF_SIZE, but we need to allocate ingress -+ * buffers large enough to allow building an skb around them and also account -+ * for alignment restrictions -+ */ - #define DPAA2_ETH_BUF_RAW_SIZE \ -- (DPAA2_ETH_RX_BUFFER_SIZE + \ -+ (DPAA2_ETH_RX_BUF_SIZE + \ - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + \ - DPAA2_ETH_RX_BUF_ALIGN) - -@@ -127,57 +138,56 @@ struct dpaa2_fas { - __le32 status; - } __packed; - -+/* Error and status bits in the frame annotation status word */ - /* Debug frame, otherwise supposed to be discarded */ --#define DPAA2_ETH_FAS_DISC 0x80000000 -+#define DPAA2_FAS_DISC 0x80000000 - /* MACSEC frame */ --#define DPAA2_ETH_FAS_MS 0x40000000 --#define DPAA2_ETH_FAS_PTP 0x08000000 -+#define DPAA2_FAS_MS 0x40000000 -+#define DPAA2_FAS_PTP 0x08000000 - /* Ethernet multicast frame */ --#define DPAA2_ETH_FAS_MC 0x04000000 -+#define DPAA2_FAS_MC 0x04000000 - /* Ethernet broadcast frame */ --#define DPAA2_ETH_FAS_BC 0x02000000 --#define DPAA2_ETH_FAS_KSE 0x00040000 --#define DPAA2_ETH_FAS_EOFHE 0x00020000 --#define DPAA2_ETH_FAS_MNLE 0x00010000 --#define DPAA2_ETH_FAS_TIDE 0x00008000 --#define DPAA2_ETH_FAS_PIEE 0x00004000 -+#define DPAA2_FAS_BC 0x02000000 -+#define DPAA2_FAS_KSE 0x00040000 -+#define DPAA2_FAS_EOFHE 0x00020000 -+#define DPAA2_FAS_MNLE 0x00010000 -+#define DPAA2_FAS_TIDE 0x00008000 -+#define DPAA2_FAS_PIEE 0x00004000 - /* Frame length error */ --#define DPAA2_ETH_FAS_FLE 0x00002000 --/* Frame physical error; our favourite pastime */ --#define DPAA2_ETH_FAS_FPE 0x00001000 --#define DPAA2_ETH_FAS_PTE 0x00000080 --#define DPAA2_ETH_FAS_ISP 0x00000040 --#define DPAA2_ETH_FAS_PHE 0x00000020 --#define DPAA2_ETH_FAS_BLE 0x00000010 -+#define DPAA2_FAS_FLE 0x00002000 -+/* Frame physical error */ -+#define DPAA2_FAS_FPE 0x00001000 -+#define DPAA2_FAS_PTE 0x00000080 -+#define DPAA2_FAS_ISP 0x00000040 -+#define DPAA2_FAS_PHE 0x00000020 -+#define DPAA2_FAS_BLE 0x00000010 - /* L3 csum validation performed */ --#define DPAA2_ETH_FAS_L3CV 0x00000008 -+#define DPAA2_FAS_L3CV 0x00000008 - /* L3 csum error */ --#define DPAA2_ETH_FAS_L3CE 0x00000004 -+#define DPAA2_FAS_L3CE 0x00000004 - /* L4 csum validation performed */ --#define DPAA2_ETH_FAS_L4CV 0x00000002 -+#define DPAA2_FAS_L4CV 0x00000002 - /* L4 csum error */ --#define DPAA2_ETH_FAS_L4CE 0x00000001 --/* These bits always signal errors */ --#define DPAA2_ETH_RX_ERR_MASK (DPAA2_ETH_FAS_KSE | \ -- DPAA2_ETH_FAS_EOFHE | \ -- DPAA2_ETH_FAS_MNLE | \ -- DPAA2_ETH_FAS_TIDE | \ -- DPAA2_ETH_FAS_PIEE | \ -- DPAA2_ETH_FAS_FLE | \ -- DPAA2_ETH_FAS_FPE | \ -- DPAA2_ETH_FAS_PTE | \ -- DPAA2_ETH_FAS_ISP | \ -- DPAA2_ETH_FAS_PHE | \ -- DPAA2_ETH_FAS_BLE | \ -- DPAA2_ETH_FAS_L3CE | \ -- DPAA2_ETH_FAS_L4CE) --/* Unsupported features in the ingress */ --#define DPAA2_ETH_RX_UNSUPP_MASK DPAA2_ETH_FAS_MS -+#define DPAA2_FAS_L4CE 0x00000001 -+/* Possible errors on the ingress path */ -+#define DPAA2_ETH_RX_ERR_MASK (DPAA2_FAS_KSE | \ -+ DPAA2_FAS_EOFHE | \ -+ DPAA2_FAS_MNLE | \ -+ DPAA2_FAS_TIDE | \ -+ DPAA2_FAS_PIEE | \ -+ DPAA2_FAS_FLE | \ -+ DPAA2_FAS_FPE | \ -+ DPAA2_FAS_PTE | \ -+ DPAA2_FAS_ISP | \ -+ DPAA2_FAS_PHE | \ -+ DPAA2_FAS_BLE | \ -+ DPAA2_FAS_L3CE | \ -+ DPAA2_FAS_L4CE) - /* Tx errors */ --#define DPAA2_ETH_TXCONF_ERR_MASK (DPAA2_ETH_FAS_KSE | \ -- DPAA2_ETH_FAS_EOFHE | \ -- DPAA2_ETH_FAS_MNLE | \ -- DPAA2_ETH_FAS_TIDE) -+#define DPAA2_ETH_TXCONF_ERR_MASK (DPAA2_FAS_KSE | \ -+ DPAA2_FAS_EOFHE | \ -+ DPAA2_FAS_MNLE | \ -+ DPAA2_FAS_TIDE) - - /* Time in milliseconds between link state updates */ - #define DPAA2_ETH_LINK_STATE_REFRESH 1000 -@@ -185,7 +195,7 @@ struct dpaa2_fas { - /* Driver statistics, other than those in struct rtnl_link_stats64. - * These are usually collected per-CPU and aggregated by ethtool. - */ --struct dpaa2_eth_stats { -+struct dpaa2_eth_drv_stats { - __u64 tx_conf_frames; - __u64 tx_conf_bytes; - __u64 tx_sg_frames; -@@ -210,15 +220,17 @@ struct dpaa2_eth_ch_stats { - __u64 cdan; - /* Number of frames received on queues from this channel */ - __u64 frames; -+ /* Pull errors */ -+ __u64 pull_err; - }; - --/* Maximum number of Rx queues associated with a DPNI */ -+/* Maximum number of queues associated with a DPNI */ - #define DPAA2_ETH_MAX_RX_QUEUES 16 - #define DPAA2_ETH_MAX_TX_QUEUES NR_CPUS - #define DPAA2_ETH_MAX_RX_ERR_QUEUES 1 --#define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \ -- DPAA2_ETH_MAX_TX_QUEUES + \ -- DPAA2_ETH_MAX_RX_ERR_QUEUES) -+#define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \ -+ DPAA2_ETH_MAX_TX_QUEUES + \ -+ DPAA2_ETH_MAX_RX_ERR_QUEUES) - - #define DPAA2_ETH_MAX_DPCONS NR_CPUS - -@@ -241,7 +253,6 @@ struct dpaa2_eth_fq { - struct dpaa2_eth_channel *, - const struct dpaa2_fd *, - struct napi_struct *); -- struct dpaa2_eth_priv *netdev_priv; /* backpointer */ - struct dpaa2_eth_fq_stats stats; - }; - -@@ -258,16 +269,16 @@ struct dpaa2_eth_channel { - struct dpaa2_eth_ch_stats stats; - }; - --struct dpaa2_cls_rule { -+struct dpaa2_eth_cls_rule { - struct ethtool_rx_flow_spec fs; - bool in_use; - }; - -+/* Driver private data */ - struct dpaa2_eth_priv { - struct net_device *net_dev; - - u8 num_fqs; -- /* First queue is tx conf, the rest are rx */ - struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES]; - - u8 num_channels; -@@ -299,12 +310,12 @@ struct dpaa2_eth_priv { - /* Standard statistics */ - struct rtnl_link_stats64 __percpu *percpu_stats; - /* Extra stats, in addition to the ones known by the kernel */ -- struct dpaa2_eth_stats __percpu *percpu_extras; -- u32 msg_enable; /* net_device message level */ -+ struct dpaa2_eth_drv_stats __percpu *percpu_extras; - - u16 mc_token; - - struct dpni_link_state link_state; -+ bool do_link_poll; - struct task_struct *poll_thread; - - /* enabled ethtool hashing bits */ -@@ -315,7 +326,7 @@ struct dpaa2_eth_priv { - #endif - - /* array of classification rules */ -- struct dpaa2_cls_rule *cls_rule; -+ struct dpaa2_eth_cls_rule *cls_rule; - - struct dpni_tx_shaping_cfg shaping_cfg; - -@@ -341,9 +352,9 @@ struct dpaa2_eth_priv { - - extern const struct ethtool_ops dpaa2_ethtool_ops; - --int dpaa2_set_hash(struct net_device *net_dev, u64 flags); -+int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags); - --static int dpaa2_queue_count(struct dpaa2_eth_priv *priv) -+static int dpaa2_eth_queue_count(struct dpaa2_eth_priv *priv) - { - if (!dpaa2_eth_hash_enabled(priv)) - return 1; -@@ -351,16 +362,16 @@ static int dpaa2_queue_count(struct dpaa - return priv->dpni_ext_cfg.tc_cfg[0].max_dist; - } - --static inline int dpaa2_max_channels(struct dpaa2_eth_priv *priv) -+static inline int dpaa2_eth_max_channels(struct dpaa2_eth_priv *priv) - { - /* Ideally, we want a number of channels large enough - * to accommodate both the Rx distribution size - * and the max number of Tx confirmation queues - */ -- return max_t(int, dpaa2_queue_count(priv), -+ return max_t(int, dpaa2_eth_queue_count(priv), - priv->dpni_attrs.max_senders); - } - --void dpaa2_cls_check(struct net_device *); -+void check_fs_support(struct net_device *); - - #endif /* __DPAA2_H */ ---- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c -@@ -52,7 +52,7 @@ char dpaa2_ethtool_stats[][ETH_GSTRING_L - - #define DPAA2_ETH_NUM_STATS ARRAY_SIZE(dpaa2_ethtool_stats) - --/* To be kept in sync with 'struct dpaa2_eth_stats' */ -+/* To be kept in sync with 'struct dpaa2_eth_drv_stats' */ - char dpaa2_ethtool_extras[][ETH_GSTRING_LEN] = { - /* per-cpu stats */ - -@@ -63,12 +63,12 @@ char dpaa2_ethtool_extras[][ETH_GSTRING_ - "rx sg frames", - "rx sg bytes", - /* how many times we had to retry the enqueue command */ -- "tx portal busy", -+ "enqueue portal busy", - - /* Channel stats */ -- - /* How many times we had to retry the volatile dequeue command */ -- "portal busy", -+ "dequeue portal busy", -+ "channel pull errors", - /* Number of notifications received */ - "cdan", - #ifdef CONFIG_FSL_QBMAN_DEBUG -@@ -83,8 +83,8 @@ char dpaa2_ethtool_extras[][ETH_GSTRING_ - - #define DPAA2_ETH_NUM_EXTRA_STATS ARRAY_SIZE(dpaa2_ethtool_extras) - --static void dpaa2_get_drvinfo(struct net_device *net_dev, -- struct ethtool_drvinfo *drvinfo) -+static void dpaa2_eth_get_drvinfo(struct net_device *net_dev, -+ struct ethtool_drvinfo *drvinfo) - { - struct mc_version mc_ver; - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -@@ -112,20 +112,8 @@ static void dpaa2_get_drvinfo(struct net - sizeof(drvinfo->bus_info)); - } - --static u32 dpaa2_get_msglevel(struct net_device *net_dev) --{ -- return ((struct dpaa2_eth_priv *)netdev_priv(net_dev))->msg_enable; --} -- --static void dpaa2_set_msglevel(struct net_device *net_dev, -- u32 msg_enable) --{ -- ((struct dpaa2_eth_priv *)netdev_priv(net_dev))->msg_enable = -- msg_enable; --} -- --static int dpaa2_get_settings(struct net_device *net_dev, -- struct ethtool_cmd *cmd) -+static int dpaa2_eth_get_settings(struct net_device *net_dev, -+ struct ethtool_cmd *cmd) - { - struct dpni_link_state state = {0}; - int err = 0; -@@ -152,8 +140,8 @@ out: - return err; - } - --static int dpaa2_set_settings(struct net_device *net_dev, -- struct ethtool_cmd *cmd) -+static int dpaa2_eth_set_settings(struct net_device *net_dev, -+ struct ethtool_cmd *cmd) - { - struct dpni_link_cfg cfg = {0}; - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -@@ -190,8 +178,8 @@ static int dpaa2_set_settings(struct net - return err; - } - --static void dpaa2_get_strings(struct net_device *netdev, u32 stringset, -- u8 *data) -+static void dpaa2_eth_get_strings(struct net_device *netdev, u32 stringset, -+ u8 *data) - { - u8 *p = data; - int i; -@@ -210,7 +198,7 @@ static void dpaa2_get_strings(struct net - } - } - --static int dpaa2_get_sset_count(struct net_device *net_dev, int sset) -+static int dpaa2_eth_get_sset_count(struct net_device *net_dev, int sset) - { - switch (sset) { - case ETH_SS_STATS: /* ethtool_get_stats(), ethtool_get_drvinfo() */ -@@ -222,9 +210,9 @@ static int dpaa2_get_sset_count(struct n - - /** Fill in hardware counters, as returned by the MC firmware. - */ --static void dpaa2_get_ethtool_stats(struct net_device *net_dev, -- struct ethtool_stats *stats, -- u64 *data) -+static void dpaa2_eth_get_ethtool_stats(struct net_device *net_dev, -+ struct ethtool_stats *stats, -+ u64 *data) - { - int i; /* Current index in the data array */ - int j, k, err; -@@ -236,9 +224,9 @@ static void dpaa2_get_ethtool_stats(stru - u32 buf_cnt; - #endif - u64 cdan = 0; -- u64 portal_busy = 0; -+ u64 portal_busy = 0, pull_err = 0; - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -- struct dpaa2_eth_stats *extras; -+ struct dpaa2_eth_drv_stats *extras; - struct dpaa2_eth_ch_stats *ch_stats; - - memset(data, 0, -@@ -266,16 +254,18 @@ static void dpaa2_get_ethtool_stats(stru - ch_stats = &priv->channel[j]->stats; - cdan += ch_stats->cdan; - portal_busy += ch_stats->dequeue_portal_busy; -+ pull_err += ch_stats->pull_err; - } - - *(data + i++) = portal_busy; -+ *(data + i++) = pull_err; - *(data + i++) = cdan; - - #ifdef CONFIG_FSL_QBMAN_DEBUG - for (j = 0; j < priv->num_fqs; j++) { - /* Print FQ instantaneous counts */ - err = dpaa2_io_query_fq_count(NULL, priv->fq[j].fqid, -- &fcnt, &bcnt); -+ &fcnt, &bcnt); - if (err) { - netdev_warn(net_dev, "FQ query error %d", err); - return; -@@ -303,12 +293,12 @@ static void dpaa2_get_ethtool_stats(stru - #endif - } - --static const struct dpaa2_hash_fields { -+static const struct dpaa2_eth_hash_fields { - u64 rxnfc_field; - enum net_prot cls_prot; - int cls_field; - int size; --} dpaa2_hash_fields[] = { -+} hash_fields[] = { - { - /* L2 header */ - .rxnfc_field = RXH_L2DA, -@@ -353,55 +343,53 @@ static const struct dpaa2_hash_fields { - }, - }; - --static int dpaa2_cls_is_enabled(struct net_device *net_dev, u64 flag) -+static int cls_is_enabled(struct net_device *net_dev, u64 flag) - { - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); - - return !!(priv->rx_hash_fields & flag); - } - --static int dpaa2_cls_key_off(struct net_device *net_dev, u64 flag) -+static int cls_key_off(struct net_device *net_dev, u64 flag) - { - int i, off = 0; - -- for (i = 0; i < ARRAY_SIZE(dpaa2_hash_fields); i++) { -- if (dpaa2_hash_fields[i].rxnfc_field & flag) -+ for (i = 0; i < ARRAY_SIZE(hash_fields); i++) { -+ if (hash_fields[i].rxnfc_field & flag) - return off; -- if (dpaa2_cls_is_enabled(net_dev, -- dpaa2_hash_fields[i].rxnfc_field)) -- off += dpaa2_hash_fields[i].size; -+ if (cls_is_enabled(net_dev, hash_fields[i].rxnfc_field)) -+ off += hash_fields[i].size; - } - - return -1; - } - --static u8 dpaa2_cls_key_size(struct net_device *net_dev) -+static u8 cls_key_size(struct net_device *net_dev) - { - u8 i, size = 0; - -- for (i = 0; i < ARRAY_SIZE(dpaa2_hash_fields); i++) { -- if (!dpaa2_cls_is_enabled(net_dev, -- dpaa2_hash_fields[i].rxnfc_field)) -+ for (i = 0; i < ARRAY_SIZE(hash_fields); i++) { -+ if (!cls_is_enabled(net_dev, hash_fields[i].rxnfc_field)) - continue; -- size += dpaa2_hash_fields[i].size; -+ size += hash_fields[i].size; - } - - return size; - } - --static u8 dpaa2_cls_max_key_size(struct net_device *net_dev) -+static u8 cls_max_key_size(struct net_device *net_dev) - { - u8 i, size = 0; - -- for (i = 0; i < ARRAY_SIZE(dpaa2_hash_fields); i++) -- size += dpaa2_hash_fields[i].size; -+ for (i = 0; i < ARRAY_SIZE(hash_fields); i++) -+ size += hash_fields[i].size; - - return size; - } - --void dpaa2_cls_check(struct net_device *net_dev) -+void check_fs_support(struct net_device *net_dev) - { -- u8 key_size = dpaa2_cls_max_key_size(net_dev); -+ u8 key_size = cls_max_key_size(net_dev); - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); - - if (priv->dpni_attrs.options & DPNI_OPT_DIST_FS && -@@ -417,7 +405,7 @@ void dpaa2_cls_check(struct net_device * - /* Set RX hash options - * flags is a combination of RXH_ bits - */ --int dpaa2_set_hash(struct net_device *net_dev, u64 flags) -+int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags) - { - struct device *dev = net_dev->dev.parent; - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); -@@ -441,11 +429,11 @@ int dpaa2_set_hash(struct net_device *ne - - memset(&cls_cfg, 0, sizeof(cls_cfg)); - -- for (i = 0; i < ARRAY_SIZE(dpaa2_hash_fields); i++) { -+ for (i = 0; i < ARRAY_SIZE(hash_fields); i++) { - struct dpkg_extract *key = - &cls_cfg.extracts[cls_cfg.num_extracts]; - -- if (!(flags & dpaa2_hash_fields[i].rxnfc_field)) -+ if (!(flags & hash_fields[i].rxnfc_field)) - continue; - - if (cls_cfg.num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS) { -@@ -454,14 +442,12 @@ int dpaa2_set_hash(struct net_device *ne - } - - key->type = DPKG_EXTRACT_FROM_HDR; -- key->extract.from_hdr.prot = -- dpaa2_hash_fields[i].cls_prot; -+ key->extract.from_hdr.prot = hash_fields[i].cls_prot; - key->extract.from_hdr.type = DPKG_FULL_FIELD; -- key->extract.from_hdr.field = -- dpaa2_hash_fields[i].cls_field; -+ key->extract.from_hdr.field = hash_fields[i].cls_field; - cls_cfg.num_extracts++; - -- enabled_flags |= dpaa2_hash_fields[i].rxnfc_field; -+ enabled_flags |= hash_fields[i].rxnfc_field; - } - - dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_DMA | GFP_KERNEL); -@@ -486,7 +472,7 @@ int dpaa2_set_hash(struct net_device *ne - return -ENOMEM; - } - -- dist_cfg.dist_size = dpaa2_queue_count(priv); -+ dist_cfg.dist_size = dpaa2_eth_queue_count(priv); - if (dpaa2_eth_fs_enabled(priv)) { - dist_cfg.dist_mode = DPNI_DIST_MODE_FS; - dist_cfg.fs_cfg.miss_action = DPNI_FS_MISS_HASH; -@@ -508,14 +494,14 @@ int dpaa2_set_hash(struct net_device *ne - return 0; - } - --static int dpaa2_cls_prep_rule(struct net_device *net_dev, -- struct ethtool_rx_flow_spec *fs, -- void *key) -+static int prep_cls_rule(struct net_device *net_dev, -+ struct ethtool_rx_flow_spec *fs, -+ void *key) - { - struct ethtool_tcpip4_spec *l4ip4_h, *l4ip4_m; - struct ethhdr *eth_h, *eth_m; - struct ethtool_flow_ext *ext_h, *ext_m; -- const u8 key_size = dpaa2_cls_key_size(net_dev); -+ const u8 key_size = cls_key_size(net_dev); - void *msk = key + key_size; - - memset(key, 0, key_size * 2); -@@ -546,51 +532,47 @@ l4ip4: - "ToS is not supported for IPv4 L4\n"); - return -EOPNOTSUPP; - } -- if (l4ip4_m->ip4src && -- !dpaa2_cls_is_enabled(net_dev, RXH_IP_SRC)) { -+ if (l4ip4_m->ip4src && !cls_is_enabled(net_dev, RXH_IP_SRC)) { - netdev_err(net_dev, "IP SRC not supported!\n"); - return -EOPNOTSUPP; - } -- if (l4ip4_m->ip4dst && -- !dpaa2_cls_is_enabled(net_dev, RXH_IP_DST)) { -+ if (l4ip4_m->ip4dst && !cls_is_enabled(net_dev, RXH_IP_DST)) { - netdev_err(net_dev, "IP DST not supported!\n"); - return -EOPNOTSUPP; - } -- if (l4ip4_m->psrc && -- !dpaa2_cls_is_enabled(net_dev, RXH_L4_B_0_1)) { -+ if (l4ip4_m->psrc && !cls_is_enabled(net_dev, RXH_L4_B_0_1)) { - netdev_err(net_dev, "PSRC not supported, ignored\n"); - return -EOPNOTSUPP; - } -- if (l4ip4_m->pdst && -- !dpaa2_cls_is_enabled(net_dev, RXH_L4_B_2_3)) { -+ if (l4ip4_m->pdst && !cls_is_enabled(net_dev, RXH_L4_B_2_3)) { - netdev_err(net_dev, "PDST not supported, ignored\n"); - return -EOPNOTSUPP; - } - -- if (dpaa2_cls_is_enabled(net_dev, RXH_IP_SRC)) { -- *(u32 *)(key + dpaa2_cls_key_off(net_dev, RXH_IP_SRC)) -+ if (cls_is_enabled(net_dev, RXH_IP_SRC)) { -+ *(u32 *)(key + cls_key_off(net_dev, RXH_IP_SRC)) - = l4ip4_h->ip4src; -- *(u32 *)(msk + dpaa2_cls_key_off(net_dev, RXH_IP_SRC)) -+ *(u32 *)(msk + cls_key_off(net_dev, RXH_IP_SRC)) - = l4ip4_m->ip4src; - } -- if (dpaa2_cls_is_enabled(net_dev, RXH_IP_DST)) { -- *(u32 *)(key + dpaa2_cls_key_off(net_dev, RXH_IP_DST)) -+ if (cls_is_enabled(net_dev, RXH_IP_DST)) { -+ *(u32 *)(key + cls_key_off(net_dev, RXH_IP_DST)) - = l4ip4_h->ip4dst; -- *(u32 *)(msk + dpaa2_cls_key_off(net_dev, RXH_IP_DST)) -+ *(u32 *)(msk + cls_key_off(net_dev, RXH_IP_DST)) - = l4ip4_m->ip4dst; - } - -- if (dpaa2_cls_is_enabled(net_dev, RXH_L4_B_0_1)) { -- *(u32 *)(key + dpaa2_cls_key_off(net_dev, RXH_L4_B_0_1)) -+ if (cls_is_enabled(net_dev, RXH_L4_B_0_1)) { -+ *(u32 *)(key + cls_key_off(net_dev, RXH_L4_B_0_1)) - = l4ip4_h->psrc; -- *(u32 *)(msk + dpaa2_cls_key_off(net_dev, RXH_L4_B_0_1)) -+ *(u32 *)(msk + cls_key_off(net_dev, RXH_L4_B_0_1)) - = l4ip4_m->psrc; - } - -- if (dpaa2_cls_is_enabled(net_dev, RXH_L4_B_2_3)) { -- *(u32 *)(key + dpaa2_cls_key_off(net_dev, RXH_L4_B_2_3)) -+ if (cls_is_enabled(net_dev, RXH_L4_B_2_3)) { -+ *(u32 *)(key + cls_key_off(net_dev, RXH_L4_B_2_3)) - = l4ip4_h->pdst; -- *(u32 *)(msk + dpaa2_cls_key_off(net_dev, RXH_L4_B_2_3)) -+ *(u32 *)(msk + cls_key_off(net_dev, RXH_L4_B_2_3)) - = l4ip4_m->pdst; - } - break; -@@ -609,12 +591,10 @@ l4ip4: - return -EOPNOTSUPP; - } - -- if (dpaa2_cls_is_enabled(net_dev, RXH_L2DA)) { -- ether_addr_copy(key -- + dpaa2_cls_key_off(net_dev, RXH_L2DA), -+ if (cls_is_enabled(net_dev, RXH_L2DA)) { -+ ether_addr_copy(key + cls_key_off(net_dev, RXH_L2DA), - eth_h->h_dest); -- ether_addr_copy(msk -- + dpaa2_cls_key_off(net_dev, RXH_L2DA), -+ ether_addr_copy(msk + cls_key_off(net_dev, RXH_L2DA), - eth_m->h_dest); - } else { - if (!is_zero_ether_addr(eth_m->h_dest)) { -@@ -639,12 +619,10 @@ l4ip4: - ext_h = &fs->h_ext; - ext_m = &fs->m_ext; - -- if (dpaa2_cls_is_enabled(net_dev, RXH_L2DA)) { -- ether_addr_copy(key -- + dpaa2_cls_key_off(net_dev, RXH_L2DA), -+ if (cls_is_enabled(net_dev, RXH_L2DA)) { -+ ether_addr_copy(key + cls_key_off(net_dev, RXH_L2DA), - ext_h->h_dest); -- ether_addr_copy(msk -- + dpaa2_cls_key_off(net_dev, RXH_L2DA), -+ ether_addr_copy(msk + cls_key_off(net_dev, RXH_L2DA), - ext_m->h_dest); - } else { - if (!is_zero_ether_addr(ext_m->h_dest)) { -@@ -657,9 +635,9 @@ l4ip4: - return 0; - } - --static int dpaa2_do_cls(struct net_device *net_dev, -- struct ethtool_rx_flow_spec *fs, -- bool add) -+static int do_cls(struct net_device *net_dev, -+ struct ethtool_rx_flow_spec *fs, -+ bool add) - { - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); - const int rule_cnt = DPAA2_CLASSIFIER_ENTRY_COUNT; -@@ -674,19 +652,19 @@ static int dpaa2_do_cls(struct net_devic - } - - if ((fs->ring_cookie != RX_CLS_FLOW_DISC && -- fs->ring_cookie >= dpaa2_queue_count(priv)) || -+ fs->ring_cookie >= dpaa2_eth_queue_count(priv)) || - fs->location >= rule_cnt) - return -EINVAL; - - memset(&rule_cfg, 0, sizeof(rule_cfg)); -- rule_cfg.key_size = dpaa2_cls_key_size(net_dev); -+ rule_cfg.key_size = cls_key_size(net_dev); - - /* allocate twice the key size, for the actual key and for mask */ - dma_mem = kzalloc(rule_cfg.key_size * 2, GFP_DMA | GFP_KERNEL); - if (!dma_mem) - return -ENOMEM; - -- err = dpaa2_cls_prep_rule(net_dev, fs, dma_mem); -+ err = prep_cls_rule(net_dev, fs, dma_mem); - if (err) - goto err_free_mem; - -@@ -735,13 +713,13 @@ err_free_mem: - return err; - } - --static int dpaa2_add_cls(struct net_device *net_dev, -- struct ethtool_rx_flow_spec *fs) -+static int add_cls(struct net_device *net_dev, -+ struct ethtool_rx_flow_spec *fs) - { - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); - int err; - -- err = dpaa2_do_cls(net_dev, fs, true); -+ err = do_cls(net_dev, fs, true); - if (err) - return err; - -@@ -751,12 +729,12 @@ static int dpaa2_add_cls(struct net_devi - return 0; - } - --static int dpaa2_del_cls(struct net_device *net_dev, int location) -+static int del_cls(struct net_device *net_dev, int location) - { - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); - int err; - -- err = dpaa2_do_cls(net_dev, &priv->cls_rule[location].fs, false); -+ err = do_cls(net_dev, &priv->cls_rule[location].fs, false); - if (err) - return err; - -@@ -765,7 +743,7 @@ static int dpaa2_del_cls(struct net_devi - return 0; - } - --static void dpaa2_clear_cls(struct net_device *net_dev) -+static void clear_cls(struct net_device *net_dev) - { - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); - int i, err; -@@ -774,7 +752,7 @@ static void dpaa2_clear_cls(struct net_d - if (!priv->cls_rule[i].in_use) - continue; - -- err = dpaa2_del_cls(net_dev, i); -+ err = del_cls(net_dev, i); - if (err) - netdev_warn(net_dev, - "err trying to delete classification entry %d\n", -@@ -782,8 +760,8 @@ static void dpaa2_clear_cls(struct net_d - } - } - --static int dpaa2_set_rxnfc(struct net_device *net_dev, -- struct ethtool_rxnfc *rxnfc) -+static int dpaa2_eth_set_rxnfc(struct net_device *net_dev, -+ struct ethtool_rxnfc *rxnfc) - { - int err = 0; - -@@ -792,19 +770,19 @@ static int dpaa2_set_rxnfc(struct net_de - /* first off clear ALL classification rules, chaging key - * composition will break them anyway - */ -- dpaa2_clear_cls(net_dev); -+ clear_cls(net_dev); - /* we purposely ignore cmd->flow_type for now, because the - * classifier only supports a single set of fields for all - * protocols - */ -- err = dpaa2_set_hash(net_dev, rxnfc->data); -+ err = dpaa2_eth_set_hash(net_dev, rxnfc->data); - break; - case ETHTOOL_SRXCLSRLINS: -- err = dpaa2_add_cls(net_dev, &rxnfc->fs); -+ err = add_cls(net_dev, &rxnfc->fs); - break; - - case ETHTOOL_SRXCLSRLDEL: -- err = dpaa2_del_cls(net_dev, rxnfc->fs.location); -+ err = del_cls(net_dev, rxnfc->fs.location); - break; - - default: -@@ -814,8 +792,8 @@ static int dpaa2_set_rxnfc(struct net_de - return err; - } - --static int dpaa2_get_rxnfc(struct net_device *net_dev, -- struct ethtool_rxnfc *rxnfc, u32 *rule_locs) -+static int dpaa2_eth_get_rxnfc(struct net_device *net_dev, -+ struct ethtool_rxnfc *rxnfc, u32 *rule_locs) - { - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); - const int rule_cnt = DPAA2_CLASSIFIER_ENTRY_COUNT; -@@ -831,7 +809,7 @@ static int dpaa2_get_rxnfc(struct net_de - break; - - case ETHTOOL_GRXRINGS: -- rxnfc->data = dpaa2_queue_count(priv); -+ rxnfc->data = dpaa2_eth_queue_count(priv); - break; - - case ETHTOOL_GRXCLSRLCNT: -@@ -868,15 +846,13 @@ static int dpaa2_get_rxnfc(struct net_de - } - - const struct ethtool_ops dpaa2_ethtool_ops = { -- .get_drvinfo = dpaa2_get_drvinfo, -- .get_msglevel = dpaa2_get_msglevel, -- .set_msglevel = dpaa2_set_msglevel, -+ .get_drvinfo = dpaa2_eth_get_drvinfo, - .get_link = ethtool_op_get_link, -- .get_settings = dpaa2_get_settings, -- .set_settings = dpaa2_set_settings, -- .get_sset_count = dpaa2_get_sset_count, -- .get_ethtool_stats = dpaa2_get_ethtool_stats, -- .get_strings = dpaa2_get_strings, -- .get_rxnfc = dpaa2_get_rxnfc, -- .set_rxnfc = dpaa2_set_rxnfc, -+ .get_settings = dpaa2_eth_get_settings, -+ .set_settings = dpaa2_eth_set_settings, -+ .get_sset_count = dpaa2_eth_get_sset_count, -+ .get_ethtool_stats = dpaa2_eth_get_ethtool_stats, -+ .get_strings = dpaa2_eth_get_strings, -+ .get_rxnfc = dpaa2_eth_get_rxnfc, -+ .set_rxnfc = dpaa2_eth_set_rxnfc, - }; diff --git a/target/linux/layerscape/patches-4.4/7203-fsl-dpaa2-eth-Update-description-of-DPNI-counters.patch b/target/linux/layerscape/patches-4.4/7203-fsl-dpaa2-eth-Update-description-of-DPNI-counters.patch deleted file mode 100644 index 41d1c04e20..0000000000 --- a/target/linux/layerscape/patches-4.4/7203-fsl-dpaa2-eth-Update-description-of-DPNI-counters.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 727de4692d731655dea96702aa099f4f4d3a5203 Mon Sep 17 00:00:00 2001 -From: Bogdan Hamciuc -Date: Mon, 21 Mar 2016 16:10:01 +0200 -Subject: [PATCH 203/226] fsl-dpaa2: eth: Update description of DPNI counters - -Update description of DPNI counters presented with "ethtool -S". - -Signed-off-by: Bogdan Hamciuc -(cherry picked from commit f68aab60355d00af13fdff2ded7bf38809beacd3) ---- - drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - ---- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c -@@ -39,15 +39,18 @@ - char dpaa2_ethtool_stats[][ETH_GSTRING_LEN] = { - "rx frames", - "rx bytes", -- "rx frames dropped", -- "rx err frames", -+ /* rx frames filtered/policed */ -+ "rx filtered frames", -+ /* rx frames dropped with errors */ -+ "rx discarded frames", - "rx mcast frames", - "rx mcast bytes", - "rx bcast frames", - "rx bcast bytes", - "tx frames", - "tx bytes", -- "tx err frames", -+ /* tx frames dropped with errors */ -+ "tx discarded frames", - }; - - #define DPAA2_ETH_NUM_STATS ARRAY_SIZE(dpaa2_ethtool_stats) diff --git a/target/linux/layerscape/patches-4.4/7204-fsl-dpaa2-eth-dpni-Clear-compiler-warnings.patch b/target/linux/layerscape/patches-4.4/7204-fsl-dpaa2-eth-dpni-Clear-compiler-warnings.patch deleted file mode 100644 index ff74d13003..0000000000 --- a/target/linux/layerscape/patches-4.4/7204-fsl-dpaa2-eth-dpni-Clear-compiler-warnings.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 9a38e2ce3b46a2bdc90b4ad190a26f9418909450 Mon Sep 17 00:00:00 2001 -From: Bogdan Hamciuc -Date: Tue, 29 Mar 2016 13:23:50 +0300 -Subject: [PATCH 204/226] fsl-dpaa2: eth: dpni: Clear compiler warnings -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Clear two warnings given by -Wcast-qual: -warning: cast discards ‘__attribute__((const))’ qualifier from pointer -target type - -Signed-off-by: Bogdan Hamciuc -(cherry picked from commit 96d14f291c2750e8b09268cecb84bfe7f013294d) ---- - drivers/staging/fsl-dpaa2/ethernet/dpni.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/staging/fsl-dpaa2/ethernet/dpni.c -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpni.c -@@ -128,7 +128,7 @@ int dpni_prepare_extended_cfg(const stru - int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg, - const uint8_t *ext_cfg_buf) - { -- uint64_t *ext_params = (uint64_t *)ext_cfg_buf; -+ const uint64_t *ext_params = (const uint64_t *)ext_cfg_buf; - - DPNI_EXT_EXTENDED_CFG(ext_params, cfg); - -@@ -1651,7 +1651,7 @@ void dpni_prepare_early_drop(const struc - void dpni_extract_early_drop(struct dpni_early_drop_cfg *cfg, - const uint8_t *early_drop_buf) - { -- uint64_t *ext_params = (uint64_t *)early_drop_buf; -+ const uint64_t *ext_params = (const uint64_t *)early_drop_buf; - - DPNI_EXT_EARLY_DROP(ext_params, cfg); - } diff --git a/target/linux/layerscape/patches-4.4/7205-fsl-dpaa2-eth-sanitize-supported-private-flags.patch b/target/linux/layerscape/patches-4.4/7205-fsl-dpaa2-eth-sanitize-supported-private-flags.patch deleted file mode 100644 index 0f96213a13..0000000000 --- a/target/linux/layerscape/patches-4.4/7205-fsl-dpaa2-eth-sanitize-supported-private-flags.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 51106cb1fd14dfbf62c2760921463376f56ac732 Mon Sep 17 00:00:00 2001 -From: Bogdan Purcareata -Date: Tue, 21 Jun 2016 18:40:47 +0000 -Subject: [PATCH 205/226] fsl-dpaa2: eth: sanitize supported private flags - -On linux-v4.6 with CONFIG_MACVLAN=y, when bringing up a ni interface, the -network stack crashes due to a segfault. This is related to the -macvlan_device_event notifier, which registers itself to all the network -interface in the system. - -The notifier reads the netdev private flags and incorrectly qualifies -the interface as a macvlan port, since both the IFF_MACVLAN_PORT and -IFF_PROMISC flags have the same offset. Code spelunking reveals that -IFF_PROMISC is only used as an interface flag, not a private interface -flag. - -A similar situation happens with IFF_ALLMULTI, which overlaps with -IFF_BRIDGE_PORT. No info on the consequences of this, since I haven't -tested bridge scenarios. The interface can still be set in allmulti -mode using userspace tools (e.g. ifconfig). - -IFF_MULTICAST overlaps with IFF_UNICAST_FLT, therefore the current code -has no effect as it is. The closest multicast activation based on device -capabilities has been seen in the case of the Aeroflex Gaisler Ethernet -MAC (aeroflex/greth.c) - here, the runtime (not private) flag is set on -device probe. On a side node, ether_setup enables IFF_MULTICAST by default. - -Remove IFF_PROMISC, IFF_ALLMULTI and IFF_MULTICAST from device capabilities -init. - -Signed-off-by: Bogdan Purcareata ---- - drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - ---- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c -@@ -1176,18 +1176,13 @@ static int dpaa2_eth_init(struct net_dev - u32 options = priv->dpni_attrs.options; - - /* Capabilities listing */ -- supported |= IFF_LIVE_ADDR_CHANGE | IFF_PROMISC | IFF_ALLMULTI; -+ supported |= IFF_LIVE_ADDR_CHANGE; - - if (options & DPNI_OPT_UNICAST_FILTER) - supported |= IFF_UNICAST_FLT; - else - not_supported |= IFF_UNICAST_FLT; - -- if (options & DPNI_OPT_MULTICAST_FILTER) -- supported |= IFF_MULTICAST; -- else -- not_supported |= IFF_MULTICAST; -- - net_dev->priv_flags |= supported; - net_dev->priv_flags &= ~not_supported; - diff --git a/target/linux/layerscape/patches-4.4/7206-fsl-dpaa2-eth-match-id-cleanup.patch b/target/linux/layerscape/patches-4.4/7206-fsl-dpaa2-eth-match-id-cleanup.patch deleted file mode 100644 index bdb0f58958..0000000000 --- a/target/linux/layerscape/patches-4.4/7206-fsl-dpaa2-eth-match-id-cleanup.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 7e536d0c2f870b39480268c20af6fc3d21abe611 Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Wed, 15 Jun 2016 14:03:43 -0500 -Subject: [PATCH 206/226] fsl-dpaa2: eth: match id cleanup - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c -@@ -2787,12 +2787,10 @@ static int dpaa2_eth_remove(struct fsl_m - return 0; - } - --static const struct fsl_mc_device_match_id dpaa2_eth_match_id_table[] = { -+static const struct fsl_mc_device_id dpaa2_eth_match_id_table[] = { - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dpni", -- .ver_major = DPNI_VER_MAJOR, -- .ver_minor = DPNI_VER_MINOR - }, - { .vendor = 0x0 } - }; diff --git a/target/linux/layerscape/patches-4.4/7207-fsl-dpaa2-eth-add-device-table-to-driver.patch b/target/linux/layerscape/patches-4.4/7207-fsl-dpaa2-eth-add-device-table-to-driver.patch deleted file mode 100644 index b7885cf01a..0000000000 --- a/target/linux/layerscape/patches-4.4/7207-fsl-dpaa2-eth-add-device-table-to-driver.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 8557c8a3823b341607e16048d8318a1958eab3a9 Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Thu, 12 May 2016 17:52:28 -0500 -Subject: [PATCH 207/226] fsl-dpaa2: eth: add device table to driver - -this is needed to have the driver loaded as a module - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c -+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c -@@ -2794,6 +2794,7 @@ static const struct fsl_mc_device_id dpa - }, - { .vendor = 0x0 } - }; -+MODULE_DEVICE_TABLE(fslmc, dpaa2_eth_match_id_table); - - static struct fsl_mc_driver dpaa2_eth_driver = { - .driver = { diff --git a/target/linux/layerscape/patches-4.4/7208-staging-fsl-dpaa2-mac-Added-MAC-PHY-interface-driver.patch b/target/linux/layerscape/patches-4.4/7208-staging-fsl-dpaa2-mac-Added-MAC-PHY-interface-driver.patch deleted file mode 100644 index 42a23a598c..0000000000 --- a/target/linux/layerscape/patches-4.4/7208-staging-fsl-dpaa2-mac-Added-MAC-PHY-interface-driver.patch +++ /dev/null @@ -1,2347 +0,0 @@ -From ecaf55d2907835cd0580903e134cdf08416ff694 Mon Sep 17 00:00:00 2001 -From: Bogdan Hamciuc -Date: Tue, 15 Sep 2015 10:27:19 -0500 -Subject: [PATCH 208/226] staging: fsl-dpaa2: mac: Added MAC / PHY interface - driver - -This is a commit of the cummulative, squashed dpmac patches. -All the commit logs are preserved below. - -Signed-off-by: Stuart Yoder - --------------------------------------------------------------- - -flib,dpmac: add dpmac files (Rebasing onto kernel 3.19, MC 0.6) - -patches moved from 4.0 kernel - -Signed-off-by: Bogdan Hamciuc -[Stuart: cherry-picked patch and split it up] -Signed-off-by: Stuart Yoder - -staging: fsl-dpaa2: mac: Added MAC / PHY interface driver. - -This driver works as a proxy between phylib including phy drivers and -the MC firmware. It receives updates on link state changes from PHY -lib and forwards them to MC and receives interrupt from MC whenever -a request is made to change the link state. - -Signed-off-by: Alex Marginean -Change-Id: I8097ea69ea8effded3bddd43b9d326bbb59ba6c8 -Reviewed-on: http://git.am.freescale.net:8181/35113 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -fsl-dpaa2: mac: Change IRQ flags - -Signed-off-by: Bogdan Hamciuc -Change-Id: Ia86570858f9cf7f673089cd7c2078662d56b2f01 -Reviewed-on: http://git.am.freescale.net:8181/35581 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -fsl-dpaa2: mac: Check for actual link state change - -Do not invoke the MC firmware if the link state hasn't changed. - -Signed-off-by: Alex Marginean -Change-Id: Iba59d8b52c72334efa28f6126e50ec821c802852 -Reviewed-on: http://git.am.freescale.net:8181/35582 -Reviewed-by: Bogdan Hamciuc -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -fsl-dpaa2: mac: Fix "dpmac netdevs" probing - -Fixup code under DPAA2_MAC_NETDEVS to probe again. In particular, remove -the temporary addition of "fixed.c" in the mac/ folder. - -Signed-off-by: Bogdan Hamciuc -Change-Id: Iea6768f3c5cd9b2de2c8421c03ecebf155b9792b -Reviewed-on: http://git.am.freescale.net:8181/37673 -Reviewed-by: Ruxandra Ioana Radulescu -Reviewed-by: Stuart Yoder -Tested-by: Stuart Yoder - -flib: Remove duplicate header files - -These files are included by the DPAA2 mac driver files. - -Signed-off-by: Razvan Stefanescu -Change-Id: Ieff56e3c34393ef65a5ac1123aaf00bacefa050c -Reviewed-on: http://git.am.freescale.net:8181/37257 -Reviewed-by: Alexandru Marginean -Reviewed-by: Stuart Yoder -Tested-by: Stuart Yoder - -fsl-dpaa2: mac: Add dependency on CONFIG_FIXED_PHY - -The DPAA2 DPMAC driver currently relies on fixed links, so it will fail -to probe in unusual ways if CONFIG_FIXED_PHY is not enabled. - -Signed-off-by: Bogdan Hamciuc -Change-Id: Ibc53226a215ed85a2ba22c55b18595fb939e7418 -Reviewed-on: http://git.am.freescale.net:8181/37687 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Stuart Yoder - -fsl-dpaa2: mac: Fix macro - -Remove macro ending backslash. - -Signed-off-by: Razvan Stefanescu -Change-Id: Ib0c4a41eee8fbe4aa7c991fc7fdb87771d3bf594 -Reviewed-on: http://git.am.freescale.net:8181/37254 -Tested-by: Review Code-CDREVIEW -Reviewed-by: Alexandru Marginean -Reviewed-by: Stuart Yoder - -fsl-dpaa2: mac: migrated remaining flibs for MC fw 8.0.0 - -Signed-off-by: J. German Rivera -[Stuart: split mac part out of original patch, updated subject] -Signed-off-by: Stuart Yoder - -staging: fsl-dpaa2: mac: Port to MC-0.7 Flibs - -Change-Id: Ief731e245bdc207f1bf8e7ff4dfdabb445d6010e -Signed-off-by: Bogdan Hamciuc -Reviewed-on: http://git.am.freescale.net:8181/39151 -Reviewed-by: Stuart Yoder -Tested-by: Stuart Yoder - -staging: fsl-dpaa2: mac: Do programing of MSIs in devm_request_threaded_irq() - -With the new dprc_set_obj_irq() we can now program MSIS in the device -in the callback invoked from devm_request_threaded_irq(). -Since this callback is invoked with interrupts disabled, we need to -use an atomic portal, instead of the root DPRC's built-in portal -which is non-atomic. - -Signed-off-by: Itai Katz -Signed-off-by: J. German Rivera -[Stuart: split original patch up by component] -Signed-off-by: Stuart Yoder - -fsl-dpaa2: mac: Fix driver probing - -The DPMAC probing function was broken in many ways. This patch adds -the following fixes: - - Look up PHY nodes based on the phy-handle property of the respective - DPMAC node; - - Defer DPMAC device probing until the MDIO MUX driver probes first (we - depend on that for configuring the PHYs on PCIe riser cards on - LS2085A QDS boards. - - Add Kconfig dependencies on XGMAC_MDIO and MDIO_BUS_MUX_MMIOREG. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Fix interrupt handling - -The DPMAC has two interrupt events muxed on a single interrupt line. -Both the PHY and the DPNI can initiate a link event. - -When the link event is initiated by the PHY (possibly as the effect of an -earlier link change request initiated by a DPNI), we must make sure -dpmac_set_link_state() is explicitly called in order for the event to be -propagated (back) to the DPNI. - -Finally, DPMAC interrupt mask has to be explicitly specified before calling -dpmac_set_irq_enabled(). - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Fix print in case device is not initialized - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Fix error paths at probe - -Merge error condition checks. Add error codes to the early exit paths. -Fix swapped goto labels. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Remove unused function prototype - -fixed_phy_register_2() was a leftover since we had to backport fixed PHY -implementation on kernel v3.10. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2/mac: Update dpmac binary interface to v3.2 - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: mac: Update Flib to MC 0.8.1 - -In practice, this adds a counter for "good" egress frames. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Add counter for "good" egress frames - -Now available with the 0.8.1 Flibs. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Update dpmac_set_link_state() error checking - -As of 0.8.1 Flibs, dpmac_set_link_state() no longer returns what we'd -consider spurious errors. This allows for cleaner error checking on -DPMAC-side. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Remove __cold attribute - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Check DPMAC FLIB version - -Make sure we support the DPMAC version, otherwise abort probing -early on and provide an error message. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: mac: Replace uintX_t with uX - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Fix crash on error path - -If the fixed-phy cannot be correctly registered, unregister_netdev() -receives a non-NULL, yet invalid phydev. Force the phydev reference to -NULL to avoid a crash on the probe routine's error path. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Remove TODOs comments from the code - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Fix ppx_eth_iface_mode order - -ppx_eth_iface_mode must be kept in sync with enum dpmac_eth_if, but some -array values weren't in the right order. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Remove forward declarations of functions - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Remove ppx_{err,warn,info} macros - -Replace with their straighforward equivalents, their contexts being -non-ambiguous. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Use non-atomic MC portal - -The DPMAC driver does not make MC calls from atomic contexts, so it is -safe to request non-atomic MC portals. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: Replace "ppx" prefix with "dpaa2_mac" - -Use a similar naming convention as for the Ethernet driver, -replacing "ppx" with "dpaa2_mac" as prefix for functions and -structures. - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: mac: Remove unnecessary blank line - -Signed-off-by: Ioana Radulescu - -fsl-dpaa2: mac: Do not handle link change confirmation interrupt - -The need for that interrupt is more about debugging. - -Signed-off-by: Bogdan Hamciuc - -fsl-dpaa2: mac: resolve compile issues on uprev to 4.5 - --interrupt info in mc struct changed upstream --fixed_phy_register() had new argument - -Signed-off-by: Stuart Yoder ---- - MAINTAINERS | 6 + - drivers/staging/fsl-dpaa2/Kconfig | 1 + - drivers/staging/fsl-dpaa2/Makefile | 1 + - drivers/staging/fsl-dpaa2/mac/Kconfig | 24 + - drivers/staging/fsl-dpaa2/mac/Makefile | 10 + - drivers/staging/fsl-dpaa2/mac/dpmac-cmd.h | 195 ++++++++ - drivers/staging/fsl-dpaa2/mac/dpmac.c | 422 ++++++++++++++++ - drivers/staging/fsl-dpaa2/mac/dpmac.h | 593 ++++++++++++++++++++++ - drivers/staging/fsl-dpaa2/mac/mac.c | 767 +++++++++++++++++++++++++++++ - 9 files changed, 2019 insertions(+) - create mode 100644 drivers/staging/fsl-dpaa2/mac/Kconfig - create mode 100644 drivers/staging/fsl-dpaa2/mac/Makefile - create mode 100644 drivers/staging/fsl-dpaa2/mac/dpmac-cmd.h - create mode 100644 drivers/staging/fsl-dpaa2/mac/dpmac.c - create mode 100644 drivers/staging/fsl-dpaa2/mac/dpmac.h - create mode 100644 drivers/staging/fsl-dpaa2/mac/mac.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -4554,6 +4554,12 @@ S: Maintained - F: drivers/staging/fsl-mc/bus/mc-ioctl.h - F: drivers/staging/fsl-mc/bus/mc-restool.c - -+FREESCALE DPAA2 MAC/PHY INTERFACE DRIVER -+M: Alex Marginean -+L: linux-kernel@vger.kernel.org -+S: Maintained -+F: drivers/staging/fsl-dpaa2/mac/ -+ - FREEVXFS FILESYSTEM - M: Christoph Hellwig - W: ftp://ftp.openlinux.org/pub/people/hch/vxfs ---- a/drivers/staging/fsl-dpaa2/Kconfig -+++ b/drivers/staging/fsl-dpaa2/Kconfig -@@ -9,3 +9,4 @@ config FSL_DPAA2 - Build drivers for Freescale DataPath Acceleration Architecture (DPAA2) family of SoCs. - # TODO move DPIO driver in-here? - source "drivers/staging/fsl-dpaa2/ethernet/Kconfig" -+source "drivers/staging/fsl-dpaa2/mac/Kconfig" ---- a/drivers/staging/fsl-dpaa2/Makefile -+++ b/drivers/staging/fsl-dpaa2/Makefile -@@ -3,3 +3,4 @@ - # - - obj-$(CONFIG_FSL_DPAA2_ETH) += ethernet/ -+obj-$(CONFIG_FSL_DPAA2_MAC) += mac/ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/mac/Kconfig -@@ -0,0 +1,24 @@ -+config FSL_DPAA2_MAC -+ tristate "DPAA2 MAC / PHY interface" -+ depends on FSL_MC_BUS && FSL_DPAA2 -+ select MDIO_BUS_MUX_MMIOREG -+ select FSL_XGMAC_MDIO -+ select FIXED_PHY -+ ---help--- -+ Prototype driver for DPAA2 MAC / PHY interface object. -+ This driver works as a proxy between phylib including phy drivers and -+ the MC firmware. It receives updates on link state changes from PHY -+ lib and forwards them to MC and receives interrupt from MC whenever -+ a request is made to change the link state. -+ -+ -+config FSL_DPAA2_MAC_NETDEVS -+ bool "Expose net interfaces for PHYs" -+ default n -+ depends on FSL_DPAA2_MAC -+ ---help--- -+ Exposes macX net interfaces which allow direct control over MACs and -+ PHYs. -+ . -+ Leave disabled if unsure. -+ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/mac/Makefile -@@ -0,0 +1,10 @@ -+ -+obj-$(CONFIG_FSL_DPAA2_MAC) += dpaa2-mac.o -+ -+dpaa2-mac-objs := mac.o dpmac.o -+ -+all: -+ make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules -+ -+clean: -+ make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/mac/dpmac-cmd.h -@@ -0,0 +1,195 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef _FSL_DPMAC_CMD_H -+#define _FSL_DPMAC_CMD_H -+ -+/* DPMAC Version */ -+#define DPMAC_VER_MAJOR 3 -+#define DPMAC_VER_MINOR 2 -+ -+/* Command IDs */ -+#define DPMAC_CMDID_CLOSE 0x800 -+#define DPMAC_CMDID_OPEN 0x80c -+#define DPMAC_CMDID_CREATE 0x90c -+#define DPMAC_CMDID_DESTROY 0x900 -+ -+#define DPMAC_CMDID_GET_ATTR 0x004 -+#define DPMAC_CMDID_RESET 0x005 -+ -+#define DPMAC_CMDID_SET_IRQ 0x010 -+#define DPMAC_CMDID_GET_IRQ 0x011 -+#define DPMAC_CMDID_SET_IRQ_ENABLE 0x012 -+#define DPMAC_CMDID_GET_IRQ_ENABLE 0x013 -+#define DPMAC_CMDID_SET_IRQ_MASK 0x014 -+#define DPMAC_CMDID_GET_IRQ_MASK 0x015 -+#define DPMAC_CMDID_GET_IRQ_STATUS 0x016 -+#define DPMAC_CMDID_CLEAR_IRQ_STATUS 0x017 -+ -+#define DPMAC_CMDID_MDIO_READ 0x0c0 -+#define DPMAC_CMDID_MDIO_WRITE 0x0c1 -+#define DPMAC_CMDID_GET_LINK_CFG 0x0c2 -+#define DPMAC_CMDID_SET_LINK_STATE 0x0c3 -+#define DPMAC_CMDID_GET_COUNTER 0x0c4 -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_CREATE(cmd, cfg) \ -+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->mac_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_OPEN(cmd, dpmac_id) \ -+ MC_CMD_OP(cmd, 0, 0, 32, int, dpmac_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\ -+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \ -+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_GET_IRQ(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_RSP_GET_IRQ(cmd, type, irq_cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \ -+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \ -+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_GET_IRQ_ENABLE(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_RSP_GET_IRQ_ENABLE(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_GET_IRQ_MASK(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_RSP_GET_IRQ_MASK(cmd, mask) \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_RSP_GET_IRQ_STATUS(cmd, status) \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_RSP_GET_ATTRIBUTES(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->phy_id);\ -+ MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ -+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\ -+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\ -+ MC_RSP_OP(cmd, 1, 32, 8, enum dpmac_link_type, attr->link_type);\ -+ MC_RSP_OP(cmd, 1, 40, 8, enum dpmac_eth_if, attr->eth_if);\ -+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_MDIO_READ(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ -+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_RSP_MDIO_READ(cmd, data) \ -+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, data) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ -+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->data); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ -+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ -+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ -+ MC_CMD_OP(cmd, 2, 0, 1, int, cfg->up); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_CMD_GET_COUNTER(cmd, type) \ -+ MC_CMD_OP(cmd, 0, 0, 8, enum dpmac_counter, type) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPMAC_RSP_GET_COUNTER(cmd, counter) \ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter) -+ -+#endif /* _FSL_DPMAC_CMD_H */ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/mac/dpmac.c -@@ -0,0 +1,422 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include "../../fsl-mc/include/mc-sys.h" -+#include "../../fsl-mc/include/mc-cmd.h" -+#include "dpmac.h" -+#include "dpmac-cmd.h" -+ -+int dpmac_open(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ int dpmac_id, -+ uint16_t *token) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN, -+ cmd_flags, -+ 0); -+ DPMAC_CMD_OPEN(cmd, dpmac_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header); -+ -+ return err; -+} -+ -+int dpmac_close(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpmac_create(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ const struct dpmac_cfg *cfg, -+ uint16_t *token) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE, -+ cmd_flags, -+ 0); -+ DPMAC_CMD_CREATE(cmd, cfg); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header); -+ -+ return 0; -+} -+ -+int dpmac_destroy(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_DESTROY, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpmac_set_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ struct dpmac_irq_cfg *irq_cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_IRQ, -+ cmd_flags, -+ token); -+ DPMAC_CMD_SET_IRQ(cmd, irq_index, irq_cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpmac_get_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ int *type, -+ struct dpmac_irq_cfg *irq_cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ, -+ cmd_flags, -+ token); -+ DPMAC_CMD_GET_IRQ(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPMAC_RSP_GET_IRQ(cmd, *type, irq_cfg); -+ -+ return 0; -+} -+ -+int dpmac_set_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ DPMAC_CMD_SET_IRQ_ENABLE(cmd, irq_index, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpmac_get_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ DPMAC_CMD_GET_IRQ_ENABLE(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPMAC_RSP_GET_IRQ_ENABLE(cmd, *en); -+ -+ return 0; -+} -+ -+int dpmac_set_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t mask) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_IRQ_MASK, -+ cmd_flags, -+ token); -+ DPMAC_CMD_SET_IRQ_MASK(cmd, irq_index, mask); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpmac_get_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *mask) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ_MASK, -+ cmd_flags, -+ token); -+ DPMAC_CMD_GET_IRQ_MASK(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPMAC_RSP_GET_IRQ_MASK(cmd, *mask); -+ -+ return 0; -+} -+ -+int dpmac_get_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *status) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ_STATUS, -+ cmd_flags, -+ token); -+ DPMAC_CMD_GET_IRQ_STATUS(cmd, irq_index, *status); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPMAC_RSP_GET_IRQ_STATUS(cmd, *status); -+ -+ return 0; -+} -+ -+int dpmac_clear_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t status) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLEAR_IRQ_STATUS, -+ cmd_flags, -+ token); -+ DPMAC_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpmac_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpmac_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_ATTR, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPMAC_RSP_GET_ATTRIBUTES(cmd, attr); -+ -+ return 0; -+} -+ -+int dpmac_mdio_read(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpmac_mdio_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_READ, -+ cmd_flags, -+ token); -+ DPMAC_CMD_MDIO_READ(cmd, cfg); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPMAC_RSP_MDIO_READ(cmd, cfg->data); -+ -+ return 0; -+} -+ -+int dpmac_mdio_write(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpmac_mdio_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_WRITE, -+ cmd_flags, -+ token); -+ DPMAC_CMD_MDIO_WRITE(cmd, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpmac_get_link_cfg(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpmac_link_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err = 0; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_LINK_CFG, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ DPMAC_RSP_GET_LINK_CFG(cmd, cfg); -+ -+ return 0; -+} -+ -+int dpmac_set_link_state(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpmac_link_state *link_state) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE, -+ cmd_flags, -+ token); -+ DPMAC_CMD_SET_LINK_STATE(cmd, link_state); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpmac_get_counter(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ enum dpmac_counter type, -+ uint64_t *counter) -+{ -+ struct mc_command cmd = { 0 }; -+ int err = 0; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_COUNTER, -+ cmd_flags, -+ token); -+ DPMAC_CMD_GET_COUNTER(cmd, type); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ DPMAC_RSP_GET_COUNTER(cmd, *counter); -+ -+ return 0; -+} ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/mac/dpmac.h -@@ -0,0 +1,593 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef __FSL_DPMAC_H -+#define __FSL_DPMAC_H -+ -+/* Data Path MAC API -+ * Contains initialization APIs and runtime control APIs for DPMAC -+ */ -+ -+struct fsl_mc_io; -+ -+/** -+ * dpmac_open() - Open a control session for the specified object. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @dpmac_id: DPMAC unique ID -+ * @token: Returned token; use in subsequent API calls -+ * -+ * This function can be used to open a control session for an -+ * already created object; an object may have been declared in -+ * the DPL or by calling the dpmac_create function. -+ * This function returns a unique authentication token, -+ * associated with the specific object ID and the specific MC -+ * portal; this token must be used in all subsequent commands for -+ * this specific object -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_open(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ int dpmac_id, -+ uint16_t *token); -+ -+/** -+ * dpmac_close() - Close the control session of the object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * -+ * After this function is called, no further operations are -+ * allowed on the object without opening a new control session. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_close(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * enum dpmac_link_type - DPMAC link type -+ * @DPMAC_LINK_TYPE_NONE: No link -+ * @DPMAC_LINK_TYPE_FIXED: Link is fixed type -+ * @DPMAC_LINK_TYPE_PHY: Link by PHY ID -+ * @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type -+ */ -+enum dpmac_link_type { -+ DPMAC_LINK_TYPE_NONE, -+ DPMAC_LINK_TYPE_FIXED, -+ DPMAC_LINK_TYPE_PHY, -+ DPMAC_LINK_TYPE_BACKPLANE -+}; -+ -+/** -+ * enum dpmac_eth_if - DPMAC Ethrnet interface -+ * @DPMAC_ETH_IF_MII: MII interface -+ * @DPMAC_ETH_IF_RMII: RMII interface -+ * @DPMAC_ETH_IF_SMII: SMII interface -+ * @DPMAC_ETH_IF_GMII: GMII interface -+ * @DPMAC_ETH_IF_RGMII: RGMII interface -+ * @DPMAC_ETH_IF_SGMII: SGMII interface -+ * @DPMAC_ETH_IF_QSGMII: QSGMII interface -+ * @DPMAC_ETH_IF_XAUI: XAUI interface -+ * @DPMAC_ETH_IF_XFI: XFI interface -+ */ -+enum dpmac_eth_if { -+ DPMAC_ETH_IF_MII, -+ DPMAC_ETH_IF_RMII, -+ DPMAC_ETH_IF_SMII, -+ DPMAC_ETH_IF_GMII, -+ DPMAC_ETH_IF_RGMII, -+ DPMAC_ETH_IF_SGMII, -+ DPMAC_ETH_IF_QSGMII, -+ DPMAC_ETH_IF_XAUI, -+ DPMAC_ETH_IF_XFI -+}; -+ -+/** -+ * struct dpmac_cfg - Structure representing DPMAC configuration -+ * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP, -+ * the MAC IDs are continuous. -+ * For example: 2 WRIOPs, 16 MACs in each: -+ * MAC IDs for the 1st WRIOP: 1-16, -+ * MAC IDs for the 2nd WRIOP: 17-32. -+ */ -+struct dpmac_cfg { -+ int mac_id; -+}; -+ -+/** -+ * dpmac_create() - Create the DPMAC object. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @cfg: Configuration structure -+ * @token: Returned token; use in subsequent API calls -+ * -+ * Create the DPMAC object, allocate required resources and -+ * perform required initialization. -+ * -+ * The object can be created either by declaring it in the -+ * DPL file, or by calling this function. -+ * This function returns a unique authentication token, -+ * associated with the specific object ID and the specific MC -+ * portal; this token must be used in all subsequent calls to -+ * this specific object. For objects that are created using the -+ * DPL file, call dpmac_open function to get an authentication -+ * token first. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_create(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ const struct dpmac_cfg *cfg, -+ uint16_t *token); -+ -+/** -+ * dpmac_destroy() - Destroy the DPMAC object and release all its resources. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpmac_destroy(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * DPMAC IRQ Index and Events -+ */ -+ -+/** -+ * IRQ index -+ */ -+#define DPMAC_IRQ_INDEX 0 -+/** -+ * IRQ event - indicates a change in link state -+ */ -+#define DPMAC_IRQ_EVENT_LINK_CFG_REQ 0x00000001 -+/** -+ * IRQ event - Indicates that the link state changed -+ */ -+#define DPMAC_IRQ_EVENT_LINK_CHANGED 0x00000002 -+ -+/** -+ * struct dpmac_irq_cfg - IRQ configuration -+ * @addr: Address that must be written to signal a message-based interrupt -+ * @val: Value to write into irq_addr address -+ * @irq_num: A user defined number associated with this IRQ -+ */ -+struct dpmac_irq_cfg { -+ uint64_t addr; -+ uint32_t val; -+ int irq_num; -+}; -+ -+/** -+ * dpmac_set_irq() - Set IRQ information for the DPMAC to trigger an interrupt. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @irq_index: Identifies the interrupt index to configure -+ * @irq_cfg: IRQ configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_set_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ struct dpmac_irq_cfg *irq_cfg); -+ -+/** -+ * dpmac_get_irq() - Get IRQ information from the DPMAC. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @irq_index: The interrupt index to configure -+ * @type: Interrupt type: 0 represents message interrupt -+ * type (both irq_addr and irq_val are valid) -+ * @irq_cfg: IRQ attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_get_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ int *type, -+ struct dpmac_irq_cfg *irq_cfg); -+ -+/** -+ * dpmac_set_irq_enable() - Set overall interrupt state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @irq_index: The interrupt index to configure -+ * @en: Interrupt state - enable = 1, disable = 0 -+ * -+ * Allows GPP software to control when interrupts are generated. -+ * Each interrupt can have up to 32 causes. The enable/disable control's the -+ * overall interrupt state. if the interrupt is disabled no causes will cause -+ * an interrupt. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_set_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t en); -+ -+/** -+ * dpmac_get_irq_enable() - Get overall interrupt state -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @irq_index: The interrupt index to configure -+ * @en: Returned interrupt state - enable = 1, disable = 0 -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_get_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t *en); -+ -+/** -+ * dpmac_set_irq_mask() - Set interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @irq_index: The interrupt index to configure -+ * @mask: Event mask to trigger interrupt; -+ * each bit: -+ * 0 = ignore event -+ * 1 = consider event for asserting IRQ -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_set_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t mask); -+ -+/** -+ * dpmac_get_irq_mask() - Get interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @irq_index: The interrupt index to configure -+ * @mask: Returned event mask to trigger interrupt -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_get_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *mask); -+ -+/** -+ * dpmac_get_irq_status() - Get the current status of any pending interrupts. -+ * -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @irq_index: The interrupt index to configure -+ * @status: Returned interrupts status - one bit per cause: -+ * 0 = no interrupt pending -+ * 1 = interrupt pending -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_get_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *status); -+ -+/** -+ * dpmac_clear_irq_status() - Clear a pending interrupt's status -+ * -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @irq_index: The interrupt index to configure -+ * @status: Bits to clear (W1C) - one bit per cause: -+ * 0 = don't change -+ * 1 = clear status bit -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_clear_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t status); -+ -+/** -+ * struct dpmac_attr - Structure representing DPMAC attributes -+ * @id: DPMAC object ID -+ * @phy_id: PHY ID -+ * @link_type: link type -+ * @eth_if: Ethernet interface -+ * @max_rate: Maximum supported rate - in Mbps -+ * @version: DPMAC version -+ */ -+struct dpmac_attr { -+ int id; -+ int phy_id; -+ enum dpmac_link_type link_type; -+ enum dpmac_eth_if eth_if; -+ uint32_t max_rate; -+ /** -+ * struct version - Structure representing DPMAC version -+ * @major: DPMAC major version -+ * @minor: DPMAC minor version -+ */ -+ struct { -+ uint16_t major; -+ uint16_t minor; -+ } version; -+}; -+ -+/** -+ * dpmac_get_attributes - Retrieve DPMAC attributes. -+ * -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @attr: Returned object's attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpmac_attr *attr); -+ -+/** -+ * struct dpmac_mdio_cfg - DPMAC MDIO read/write parameters -+ * @phy_addr: MDIO device address -+ * @reg: Address of the register within the Clause 45 PHY device from which data -+ * is to be read -+ * @data: Data read/write from/to MDIO -+ */ -+struct dpmac_mdio_cfg { -+ uint8_t phy_addr; -+ uint8_t reg; -+ uint16_t data; -+}; -+ -+/** -+ * dpmac_mdio_read() - Perform MDIO read transaction -+ * @mc_io: Pointer to opaque I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @cfg: Structure with MDIO transaction parameters -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_mdio_read(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpmac_mdio_cfg *cfg); -+ -+/** -+ * dpmac_mdio_write() - Perform MDIO write transaction -+ * @mc_io: Pointer to opaque I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @cfg: Structure with MDIO transaction parameters -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_mdio_write(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpmac_mdio_cfg *cfg); -+ -+/** -+ * DPMAC link configuration/state options -+ */ -+ -+/** -+ * Enable auto-negotiation -+ */ -+#define DPMAC_LINK_OPT_AUTONEG 0x0000000000000001ULL -+/** -+ * Enable half-duplex mode -+ */ -+#define DPMAC_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL -+/** -+ * Enable pause frames -+ */ -+#define DPMAC_LINK_OPT_PAUSE 0x0000000000000004ULL -+/** -+ * Enable a-symmetric pause frames -+ */ -+#define DPMAC_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL -+ -+/** -+ * struct dpmac_link_cfg - Structure representing DPMAC link configuration -+ * @rate: Link's rate - in Mbps -+ * @options: Enable/Disable DPMAC link cfg features (bitmap) -+ */ -+struct dpmac_link_cfg { -+ uint32_t rate; -+ uint64_t options; -+}; -+ -+/** -+ * dpmac_get_link_cfg() - Get Ethernet link configuration -+ * @mc_io: Pointer to opaque I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @cfg: Returned structure with the link configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_get_link_cfg(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpmac_link_cfg *cfg); -+ -+/** -+ * struct dpmac_link_state - DPMAC link configuration request -+ * @rate: Rate in Mbps -+ * @options: Enable/Disable DPMAC link cfg features (bitmap) -+ * @up: Link state -+ */ -+struct dpmac_link_state { -+ uint32_t rate; -+ uint64_t options; -+ int up; -+}; -+ -+/** -+ * dpmac_set_link_state() - Set the Ethernet link status -+ * @mc_io: Pointer to opaque I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @link_state: Link state configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpmac_set_link_state(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpmac_link_state *link_state); -+ -+/** -+ * enum dpmac_counter - DPMAC counter types -+ * @DPMAC_CNT_ING_FRAME_64: counts 64-bytes frames, good or bad. -+ * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-bytes frames, good or bad. -+ * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-bytes frames, good or bad. -+ * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-bytes frames, good or bad. -+ * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-bytes frames, good or bad. -+ * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-bytes frames, good or bad. -+ * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-bytes frames and larger -+ * (up to max frame length specified), -+ * good or bad. -+ * @DPMAC_CNT_ING_FRAG: counts frames which are shorter than 64 bytes received -+ * with a wrong CRC -+ * @DPMAC_CNT_ING_JABBER: counts frames longer than the maximum frame length -+ * specified, with a bad frame check sequence. -+ * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped frames due to internal errors. -+ * Occurs when a receive FIFO overflows. -+ * Includes also frames truncated as a result of -+ * the receive FIFO overflow. -+ * @DPMAC_CNT_ING_ALIGN_ERR: counts frames with an alignment error -+ * (optional used for wrong SFD). -+ * @DPMAC_CNT_EGR_UNDERSIZED: counts frames transmitted that was less than 64 -+ * bytes long with a good CRC. -+ * @DPMAC_CNT_ING_OVERSIZED: counts frames longer than the maximum frame length -+ * specified, with a good frame check sequence. -+ * @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frames (regular and PFC) -+ * @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frames transmitted -+ * (regular and PFC). -+ * @DPMAC_CNT_ING_BYTE: counts bytes received except preamble for all valid -+ * frames and valid pause frames. -+ * @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frames. -+ * @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frames. -+ * @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad frames received. -+ * @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frames. -+ * @DPMAC_CNT_ING_ERR_FRAME: counts frames received with an error -+ * (except for undersized/fragment frame). -+ * @DPMAC_CNT_EGR_BYTE: counts bytes transmitted except preamble for all valid -+ * frames and valid pause frames transmitted. -+ * @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frames. -+ * @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frames. -+ * @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frames. -+ * @DPMAC_CNT_EGR_ERR_FRAME: counts frames transmitted with an error. -+ * @DPMAC_CNT_ING_GOOD_FRAME: counts frames received without error, including -+ * pause frames. -+ * @DPMAC_CNT_ENG_GOOD_FRAME: counts frames transmitted without error, including -+ * pause frames. -+ */ -+enum dpmac_counter { -+ DPMAC_CNT_ING_FRAME_64, -+ DPMAC_CNT_ING_FRAME_127, -+ DPMAC_CNT_ING_FRAME_255, -+ DPMAC_CNT_ING_FRAME_511, -+ DPMAC_CNT_ING_FRAME_1023, -+ DPMAC_CNT_ING_FRAME_1518, -+ DPMAC_CNT_ING_FRAME_1519_MAX, -+ DPMAC_CNT_ING_FRAG, -+ DPMAC_CNT_ING_JABBER, -+ DPMAC_CNT_ING_FRAME_DISCARD, -+ DPMAC_CNT_ING_ALIGN_ERR, -+ DPMAC_CNT_EGR_UNDERSIZED, -+ DPMAC_CNT_ING_OVERSIZED, -+ DPMAC_CNT_ING_VALID_PAUSE_FRAME, -+ DPMAC_CNT_EGR_VALID_PAUSE_FRAME, -+ DPMAC_CNT_ING_BYTE, -+ DPMAC_CNT_ING_MCAST_FRAME, -+ DPMAC_CNT_ING_BCAST_FRAME, -+ DPMAC_CNT_ING_ALL_FRAME, -+ DPMAC_CNT_ING_UCAST_FRAME, -+ DPMAC_CNT_ING_ERR_FRAME, -+ DPMAC_CNT_EGR_BYTE, -+ DPMAC_CNT_EGR_MCAST_FRAME, -+ DPMAC_CNT_EGR_BCAST_FRAME, -+ DPMAC_CNT_EGR_UCAST_FRAME, -+ DPMAC_CNT_EGR_ERR_FRAME, -+ DPMAC_CNT_ING_GOOD_FRAME, -+ DPMAC_CNT_ENG_GOOD_FRAME -+}; -+ -+/** -+ * dpmac_get_counter() - Read a specific DPMAC counter -+ * @mc_io: Pointer to opaque I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPMAC object -+ * @type: The requested counter -+ * @counter: Returned counter value -+ * -+ * Return: The requested counter; '0' otherwise. -+ */ -+int dpmac_get_counter(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ enum dpmac_counter type, -+ uint64_t *counter); -+ -+#endif /* __FSL_DPMAC_H */ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/mac/mac.c -@@ -0,0 +1,767 @@ -+/* Copyright 2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../../fsl-mc/include/mc.h" -+#include "../../fsl-mc/include/mc-sys.h" -+ -+#include "dpmac.h" -+#include "dpmac-cmd.h" -+ -+#define DPAA2_SUPPORTED_DPMAC_VERSION 3 -+ -+struct dpaa2_mac_priv { -+ struct net_device *netdev; -+ struct fsl_mc_device *mc_dev; -+ struct dpmac_attr attr; -+ struct dpmac_link_state old_state; -+}; -+ -+/* TODO: fix the 10G modes, mapping can't be right: -+ * XGMII is paralel -+ * XAUI is serial, using 8b/10b encoding -+ * XFI is also serial but using 64b/66b encoding -+ * they can't all map to XGMII... -+ * -+ * This must be kept in sync with enum dpmac_eth_if. -+ */ -+static phy_interface_t dpaa2_mac_iface_mode[] = { -+ /* DPMAC_ETH_IF_MII */ -+ PHY_INTERFACE_MODE_MII, -+ /* DPMAC_ETH_IF_RMII */ -+ PHY_INTERFACE_MODE_RMII, -+ /* DPMAC_ETH_IF_SMII */ -+ PHY_INTERFACE_MODE_SMII, -+ /* DPMAC_ETH_IF_GMII */ -+ PHY_INTERFACE_MODE_GMII, -+ /* DPMAC_ETH_IF_RGMII */ -+ PHY_INTERFACE_MODE_RGMII, -+ /* DPMAC_ETH_IF_SGMII */ -+ PHY_INTERFACE_MODE_SGMII, -+ /* DPMAC_ETH_IF_QSGMII */ -+ PHY_INTERFACE_MODE_QSGMII, -+ /* DPMAC_ETH_IF_XAUI */ -+ PHY_INTERFACE_MODE_XGMII, -+ /* DPMAC_ETH_IF_XFI */ -+ PHY_INTERFACE_MODE_XGMII, -+}; -+ -+static void dpaa2_mac_link_changed(struct net_device *netdev) -+{ -+ struct phy_device *phydev; -+ struct dpmac_link_state state = { 0 }; -+ struct dpaa2_mac_priv *priv = netdev_priv(netdev); -+ int err; -+ -+ /* the PHY just notified us of link state change */ -+ phydev = netdev->phydev; -+ -+ state.up = !!phydev->link; -+ if (phydev->link) { -+ state.rate = phydev->speed; -+ -+ if (!phydev->duplex) -+ state.options |= DPMAC_LINK_OPT_HALF_DUPLEX; -+ if (phydev->autoneg) -+ state.options |= DPMAC_LINK_OPT_AUTONEG; -+ -+ netif_carrier_on(netdev); -+ } else { -+ netif_carrier_off(netdev); -+ } -+ -+ if (priv->old_state.up != state.up || -+ priv->old_state.rate != state.rate || -+ priv->old_state.options != state.options) { -+ priv->old_state = state; -+ phy_print_status(phydev); -+ } -+ -+ /* We must call into the MC firmware at all times, because we don't know -+ * when and whether a potential DPNI may have read the link state. -+ */ -+ err = dpmac_set_link_state(priv->mc_dev->mc_io, 0, -+ priv->mc_dev->mc_handle, &state); -+ if (unlikely(err)) -+ dev_err(&priv->mc_dev->dev, "dpmac_set_link_state: %d\n", err); -+} -+ -+/* IRQ bits that we handle */ -+static const u32 dpmac_irq_mask = DPMAC_IRQ_EVENT_LINK_CFG_REQ; -+ -+#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS -+static netdev_tx_t dpaa2_mac_drop_frame(struct sk_buff *skb, -+ struct net_device *dev) -+{ -+ /* we don't support I/O for now, drop the frame */ -+ dev_kfree_skb_any(skb); -+ return NETDEV_TX_OK; -+} -+ -+static int dpaa2_mac_open(struct net_device *netdev) -+{ -+ /* start PHY state machine */ -+ phy_start(netdev->phydev); -+ -+ return 0; -+} -+ -+static int dpaa2_mac_stop(struct net_device *netdev) -+{ -+ if (!netdev->phydev) -+ goto done; -+ -+ /* stop PHY state machine */ -+ phy_stop(netdev->phydev); -+ -+ /* signal link down to firmware */ -+ netdev->phydev->link = 0; -+ dpaa2_mac_link_changed(netdev); -+ -+done: -+ return 0; -+} -+ -+static int dpaa2_mac_get_settings(struct net_device *netdev, -+ struct ethtool_cmd *cmd) -+{ -+ return phy_ethtool_gset(netdev->phydev, cmd); -+} -+ -+static int dpaa2_mac_set_settings(struct net_device *netdev, -+ struct ethtool_cmd *cmd) -+{ -+ return phy_ethtool_sset(netdev->phydev, cmd); -+} -+ -+static struct rtnl_link_stats64 -+*dpaa2_mac_get_stats(struct net_device *netdev, -+ struct rtnl_link_stats64 *storage) -+{ -+ struct dpaa2_mac_priv *priv = netdev_priv(netdev); -+ u64 tmp; -+ int err; -+ -+ err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle, -+ DPMAC_CNT_EGR_MCAST_FRAME, -+ &storage->tx_packets); -+ if (err) -+ goto error; -+ err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle, -+ DPMAC_CNT_EGR_BCAST_FRAME, &tmp); -+ if (err) -+ goto error; -+ storage->tx_packets += tmp; -+ err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle, -+ DPMAC_CNT_EGR_UCAST_FRAME, &tmp); -+ if (err) -+ goto error; -+ storage->tx_packets += tmp; -+ -+ err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle, -+ DPMAC_CNT_EGR_UNDERSIZED, &storage->tx_dropped); -+ if (err) -+ goto error; -+ err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle, -+ DPMAC_CNT_EGR_BYTE, &storage->tx_bytes); -+ if (err) -+ goto error; -+ err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle, -+ DPMAC_CNT_EGR_ERR_FRAME, &storage->tx_errors); -+ if (err) -+ goto error; -+ -+ err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle, -+ DPMAC_CNT_ING_ALL_FRAME, &storage->rx_packets); -+ if (err) -+ goto error; -+ err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle, -+ DPMAC_CNT_ING_MCAST_FRAME, &storage->multicast); -+ if (err) -+ goto error; -+ err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle, -+ DPMAC_CNT_ING_FRAME_DISCARD, -+ &storage->rx_dropped); -+ if (err) -+ goto error; -+ err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle, -+ DPMAC_CNT_ING_ALIGN_ERR, &storage->rx_errors); -+ if (err) -+ goto error; -+ err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle, -+ DPMAC_CNT_ING_OVERSIZED, &tmp); -+ if (err) -+ goto error; -+ storage->rx_errors += tmp; -+ err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle, -+ DPMAC_CNT_ING_BYTE, &storage->rx_bytes); -+ if (err) -+ goto error; -+ -+ return storage; -+ -+error: -+ netdev_err(netdev, "dpmac_get_counter err %d\n", err); -+ return storage; -+} -+ -+static struct { -+ enum dpmac_counter id; -+ char name[ETH_GSTRING_LEN]; -+} dpaa2_mac_counters[] = { -+ {DPMAC_CNT_ING_ALL_FRAME, "rx all frames"}, -+ {DPMAC_CNT_ING_GOOD_FRAME, "rx frames ok"}, -+ {DPMAC_CNT_ING_ERR_FRAME, "rx frame errors"}, -+ {DPMAC_CNT_ING_FRAME_DISCARD, "rx frame discards"}, -+ {DPMAC_CNT_ING_UCAST_FRAME, "rx u-cast"}, -+ {DPMAC_CNT_ING_BCAST_FRAME, "rx b-cast"}, -+ {DPMAC_CNT_ING_MCAST_FRAME, "rx m-cast"}, -+ {DPMAC_CNT_ING_FRAME_64, "rx 64 bytes"}, -+ {DPMAC_CNT_ING_FRAME_127, "rx 65-127 bytes"}, -+ {DPMAC_CNT_ING_FRAME_255, "rx 128-255 bytes"}, -+ {DPMAC_CNT_ING_FRAME_511, "rx 256-511 bytes"}, -+ {DPMAC_CNT_ING_FRAME_1023, "rx 512-1023 bytes"}, -+ {DPMAC_CNT_ING_FRAME_1518, "rx 1024-1518 bytes"}, -+ {DPMAC_CNT_ING_FRAME_1519_MAX, "rx 1519-max bytes"}, -+ {DPMAC_CNT_ING_FRAG, "rx frags"}, -+ {DPMAC_CNT_ING_JABBER, "rx jabber"}, -+ {DPMAC_CNT_ING_ALIGN_ERR, "rx align errors"}, -+ {DPMAC_CNT_ING_OVERSIZED, "rx oversized"}, -+ {DPMAC_CNT_ING_VALID_PAUSE_FRAME, "rx pause"}, -+ {DPMAC_CNT_ING_BYTE, "rx bytes"}, -+ {DPMAC_CNT_ENG_GOOD_FRAME, "tx frames ok"}, -+ {DPMAC_CNT_EGR_UCAST_FRAME, "tx u-cast"}, -+ {DPMAC_CNT_EGR_MCAST_FRAME, "tx m-cast"}, -+ {DPMAC_CNT_EGR_BCAST_FRAME, "tx b-cast"}, -+ {DPMAC_CNT_EGR_ERR_FRAME, "tx frame errors"}, -+ {DPMAC_CNT_EGR_UNDERSIZED, "tx undersized"}, -+ {DPMAC_CNT_EGR_VALID_PAUSE_FRAME, "tx b-pause"}, -+ {DPMAC_CNT_EGR_BYTE, "tx bytes"}, -+ -+}; -+ -+static void dpaa2_mac_get_strings(struct net_device *netdev, -+ u32 stringset, u8 *data) -+{ -+ int i; -+ -+ switch (stringset) { -+ case ETH_SS_STATS: -+ for (i = 0; i < ARRAY_SIZE(dpaa2_mac_counters); i++) -+ memcpy(data + i * ETH_GSTRING_LEN, -+ dpaa2_mac_counters[i].name, -+ ETH_GSTRING_LEN); -+ break; -+ } -+} -+ -+static void dpaa2_mac_get_ethtool_stats(struct net_device *netdev, -+ struct ethtool_stats *stats, -+ u64 *data) -+{ -+ struct dpaa2_mac_priv *priv = netdev_priv(netdev); -+ int i; -+ int err; -+ -+ for (i = 0; i < ARRAY_SIZE(dpaa2_mac_counters); i++) { -+ err = dpmac_get_counter(priv->mc_dev->mc_io, -+ 0, -+ priv->mc_dev->mc_handle, -+ dpaa2_mac_counters[i].id, &data[i]); -+ if (err) -+ netdev_err(netdev, "dpmac_get_counter[%s] err %d\n", -+ dpaa2_mac_counters[i].name, err); -+ } -+} -+ -+static int dpaa2_mac_get_sset_count(struct net_device *dev, int sset) -+{ -+ switch (sset) { -+ case ETH_SS_STATS: -+ return ARRAY_SIZE(dpaa2_mac_counters); -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+static const struct net_device_ops dpaa2_mac_ndo_ops = { -+ .ndo_start_xmit = &dpaa2_mac_drop_frame, -+ .ndo_open = &dpaa2_mac_open, -+ .ndo_stop = &dpaa2_mac_stop, -+ .ndo_get_stats64 = &dpaa2_mac_get_stats, -+}; -+ -+static const struct ethtool_ops dpaa2_mac_ethtool_ops = { -+ .get_settings = &dpaa2_mac_get_settings, -+ .set_settings = &dpaa2_mac_set_settings, -+ .get_strings = &dpaa2_mac_get_strings, -+ .get_ethtool_stats = &dpaa2_mac_get_ethtool_stats, -+ .get_sset_count = &dpaa2_mac_get_sset_count, -+}; -+#endif /* CONFIG_FSL_DPAA2_MAC_NETDEVS */ -+ -+static int configure_link(struct dpaa2_mac_priv *priv, -+ struct dpmac_link_cfg *cfg) -+{ -+ struct phy_device *phydev = priv->netdev->phydev; -+ -+ if (!phydev) { -+ dev_warn(priv->netdev->dev.parent, -+ "asked to change PHY settings but PHY ref is NULL, ignoring\n"); -+ return 0; -+ } -+ -+ phydev->speed = cfg->rate; -+ phydev->duplex = !!(cfg->options & DPMAC_LINK_OPT_HALF_DUPLEX); -+ -+ if (cfg->options & DPMAC_LINK_OPT_AUTONEG) { -+ phydev->autoneg = 1; -+ phydev->advertising |= ADVERTISED_Autoneg; -+ } else { -+ phydev->autoneg = 0; -+ phydev->advertising &= ~ADVERTISED_Autoneg; -+ } -+ -+ phy_start_aneg(phydev); -+ -+ return 0; -+} -+ -+static irqreturn_t dpaa2_mac_irq_handler(int irq_num, void *arg) -+{ -+ struct device *dev = (struct device *)arg; -+ struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); -+ struct dpaa2_mac_priv *priv = dev_get_drvdata(dev); -+ struct dpmac_link_cfg link_cfg; -+ u8 irq_index = DPMAC_IRQ_INDEX; -+ u32 status, clear = 0; -+ int err; -+ -+ if (mc_dev->irqs[0]->msi_desc->irq != irq_num) { -+ dev_err(dev, "received unexpected interrupt %d!\n", irq_num); -+ goto err; -+ } -+ -+ err = dpmac_get_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle, -+ irq_index, &status); -+ if (err) { -+ dev_err(dev, "dpmac_get_irq_status err %d\n", err); -+ clear = ~0x0u; -+ goto out; -+ } -+ -+ /* DPNI-initiated link configuration; 'ifconfig up' also calls this */ -+ if (status & DPMAC_IRQ_EVENT_LINK_CFG_REQ) { -+ dev_dbg(dev, "DPMAC IRQ %d - LINK_CFG_REQ\n", irq_num); -+ clear |= DPMAC_IRQ_EVENT_LINK_CFG_REQ; -+ -+ err = dpmac_get_link_cfg(mc_dev->mc_io, 0, mc_dev->mc_handle, -+ &link_cfg); -+ if (err) { -+ dev_err(dev, "dpmac_get_link_cfg err %d\n", err); -+ goto out; -+ } -+ -+ err = configure_link(priv, &link_cfg); -+ if (err) { -+ dev_err(dev, "cannot configure link\n"); -+ goto out; -+ } -+ } -+ -+out: -+ err = dpmac_clear_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle, -+ irq_index, clear); -+ if (err < 0) -+ dev_err(&mc_dev->dev, "dpmac_clear_irq_status() err %d\n", err); -+ -+ return IRQ_HANDLED; -+ -+err: -+ dev_warn(dev, "DPMAC IRQ %d was not handled!\n", irq_num); -+ return IRQ_NONE; -+} -+ -+static int setup_irqs(struct fsl_mc_device *mc_dev) -+{ -+ int err; -+ -+ err = fsl_mc_allocate_irqs(mc_dev); -+ if (err) { -+ dev_err(&mc_dev->dev, "fsl_mc_allocate_irqs err %d\n", err); -+ return err; -+ } -+ -+ err = dpmac_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle, -+ DPMAC_IRQ_INDEX, dpmac_irq_mask); -+ if (err < 0) { -+ dev_err(&mc_dev->dev, "dpmac_set_irq_mask err %d\n", err); -+ goto free_irq; -+ } -+ err = dpmac_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle, -+ DPMAC_IRQ_INDEX, 0); -+ if (err) { -+ dev_err(&mc_dev->dev, "dpmac_set_irq_enable err %d\n", err); -+ goto free_irq; -+ } -+ -+ err = devm_request_threaded_irq(&mc_dev->dev, -+ mc_dev->irqs[0]->msi_desc->irq, -+ NULL, &dpaa2_mac_irq_handler, -+ IRQF_NO_SUSPEND | IRQF_ONESHOT, -+ dev_name(&mc_dev->dev), &mc_dev->dev); -+ if (err) { -+ dev_err(&mc_dev->dev, "devm_request_threaded_irq err %d\n", -+ err); -+ goto free_irq; -+ } -+ -+ err = dpmac_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle, -+ DPMAC_IRQ_INDEX, dpmac_irq_mask); -+ if (err < 0) { -+ dev_err(&mc_dev->dev, "dpmac_set_irq_mask err %d\n", err); -+ goto free_irq; -+ } -+ err = dpmac_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle, -+ DPMAC_IRQ_INDEX, 1); -+ if (err) { -+ dev_err(&mc_dev->dev, "dpmac_set_irq_enable err %d\n", err); -+ goto unregister_irq; -+ } -+ -+ return 0; -+ -+unregister_irq: -+ devm_free_irq(&mc_dev->dev, mc_dev->irqs[0]->msi_desc->irq, &mc_dev->dev); -+free_irq: -+ fsl_mc_free_irqs(mc_dev); -+ -+ return err; -+} -+ -+static void teardown_irqs(struct fsl_mc_device *mc_dev) -+{ -+ int err; -+ -+ err = dpmac_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle, -+ DPMAC_IRQ_INDEX, dpmac_irq_mask); -+ if (err < 0) -+ dev_err(&mc_dev->dev, "dpmac_set_irq_mask err %d\n", err); -+ -+ err = dpmac_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle, -+ DPMAC_IRQ_INDEX, 0); -+ if (err < 0) -+ dev_err(&mc_dev->dev, "dpmac_set_irq_enable err %d\n", err); -+ -+ devm_free_irq(&mc_dev->dev, mc_dev->irqs[0]->msi_desc->irq, &mc_dev->dev); -+ fsl_mc_free_irqs(mc_dev); -+} -+ -+static struct device_node *lookup_node(struct device *dev, int dpmac_id) -+{ -+ struct device_node *dpmacs, *dpmac = NULL; -+ struct device_node *mc_node = dev->of_node; -+ const void *id; -+ int lenp; -+ int dpmac_id_be32 = cpu_to_be32(dpmac_id); -+ -+ dpmacs = of_find_node_by_name(mc_node, "dpmacs"); -+ if (!dpmacs) { -+ dev_err(dev, "No dpmacs subnode in device-tree\n"); -+ return NULL; -+ } -+ -+ while ((dpmac = of_get_next_child(dpmacs, dpmac))) { -+ id = of_get_property(dpmac, "reg", &lenp); -+ if (!id || lenp != sizeof(int)) { -+ dev_warn(dev, "Unsuitable reg property in dpmac node\n"); -+ continue; -+ } -+ if (*(int *)id == dpmac_id_be32) -+ return dpmac; -+ } -+ -+ return NULL; -+} -+ -+static int check_dpmac_version(struct dpaa2_mac_priv *priv) -+{ -+ struct device *dev = &priv->mc_dev->dev; -+ int mc_version = priv->attr.version.major; -+ -+ /* Check that the FLIB-defined version matches the one reported by MC */ -+ if (mc_version != DPMAC_VER_MAJOR) { -+ dev_err(dev, "DPMAC FLIB version mismatch: MC says %d, we have %d\n", -+ mc_version, DPMAC_VER_MAJOR); -+ return -EINVAL; -+ } -+ -+ /* ... and that we actually support it */ -+ if (mc_version < DPAA2_SUPPORTED_DPMAC_VERSION) { -+ dev_err(dev, "Unsupported DPMAC FLIB version (%d)\n", -+ mc_version); -+ return -EINVAL; -+ } -+ -+ dev_dbg(dev, "Using DPMAC FLIB version %d\n", mc_version); -+ -+ return 0; -+} -+ -+static int dpaa2_mac_probe(struct fsl_mc_device *mc_dev) -+{ -+ struct device *dev; -+ struct dpaa2_mac_priv *priv = NULL; -+ struct device_node *phy_node, *dpmac_node; -+ struct net_device *netdev; -+ phy_interface_t if_mode; -+ int err = 0; -+ -+ /* just being completely paranoid */ -+ if (!mc_dev) -+ return -EFAULT; -+ dev = &mc_dev->dev; -+ -+ /* prepare a net_dev structure to make the phy lib API happy */ -+ netdev = alloc_etherdev(sizeof(*priv)); -+ if (!netdev) { -+ dev_err(dev, "alloc_etherdev error\n"); -+ err = -ENOMEM; -+ goto err_exit; -+ } -+ priv = netdev_priv(netdev); -+ priv->mc_dev = mc_dev; -+ priv->netdev = netdev; -+ -+ SET_NETDEV_DEV(netdev, dev); -+ snprintf(netdev->name, IFNAMSIZ, "mac%d", mc_dev->obj_desc.id); -+ -+ dev_set_drvdata(dev, priv); -+ -+ err = fsl_mc_portal_allocate(mc_dev, 0, &mc_dev->mc_io); -+ if (err || !mc_dev->mc_io) { -+ dev_err(dev, "fsl_mc_portal_allocate error: %d\n", err); -+ err = -ENODEV; -+ goto err_free_netdev; -+ } -+ -+ err = dpmac_open(mc_dev->mc_io, 0, mc_dev->obj_desc.id, -+ &mc_dev->mc_handle); -+ if (err || !mc_dev->mc_handle) { -+ dev_err(dev, "dpmac_open error: %d\n", err); -+ err = -ENODEV; -+ goto err_free_mcp; -+ } -+ -+ err = dpmac_get_attributes(mc_dev->mc_io, 0, -+ mc_dev->mc_handle, &priv->attr); -+ if (err) { -+ dev_err(dev, "dpmac_get_attributes err %d\n", err); -+ err = -EINVAL; -+ goto err_close; -+ } -+ -+ err = check_dpmac_version(priv); -+ if (err) -+ goto err_close; -+ -+ /* Look up the DPMAC node in the device-tree. */ -+ dpmac_node = lookup_node(dev, priv->attr.id); -+ if (!dpmac_node) { -+ dev_err(dev, "No dpmac@%d subnode found.\n", priv->attr.id); -+ err = -ENODEV; -+ goto err_close; -+ } -+ -+ err = setup_irqs(mc_dev); -+ if (err) { -+ err = -EFAULT; -+ goto err_close; -+ } -+ -+#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS -+ /* OPTIONAL, register netdev just to make it visible to the user */ -+ netdev->netdev_ops = &dpaa2_mac_ndo_ops; -+ netdev->ethtool_ops = &dpaa2_mac_ethtool_ops; -+ -+ /* phy starts up enabled so netdev should be up too */ -+ netdev->flags |= IFF_UP; -+ -+ err = register_netdev(priv->netdev); -+ if (err < 0) { -+ dev_err(dev, "register_netdev error %d\n", err); -+ err = -ENODEV; -+ goto err_free_irq; -+ } -+#endif /* CONFIG_FSL_DPAA2_MAC_NETDEVS */ -+ -+ /* probe the PHY as a fixed-link if the link type declared in DPC -+ * explicitly mandates this -+ */ -+ if (priv->attr.link_type == DPMAC_LINK_TYPE_FIXED) -+ goto probe_fixed_link; -+ -+ if (priv->attr.eth_if < ARRAY_SIZE(dpaa2_mac_iface_mode)) { -+ if_mode = dpaa2_mac_iface_mode[priv->attr.eth_if]; -+ dev_dbg(dev, "\tusing if mode %s for eth_if %d\n", -+ phy_modes(if_mode), priv->attr.eth_if); -+ } else { -+ dev_warn(dev, "Unexpected interface mode %d, will probe as fixed link\n", -+ priv->attr.eth_if); -+ goto probe_fixed_link; -+ } -+ -+ /* try to connect to the PHY */ -+ phy_node = of_parse_phandle(dpmac_node, "phy-handle", 0); -+ if (!phy_node) { -+ if (!phy_node) { -+ dev_err(dev, "dpmac node has no phy-handle property\n"); -+ err = -ENODEV; -+ goto err_no_phy; -+ } -+ } -+ netdev->phydev = of_phy_connect(netdev, phy_node, -+ &dpaa2_mac_link_changed, 0, if_mode); -+ if (!netdev->phydev) { -+ /* No need for dev_err(); the kernel's loud enough as it is. */ -+ dev_dbg(dev, "Can't of_phy_connect() now.\n"); -+ /* We might be waiting for the MDIO MUX to probe, so defer -+ * our own probing. -+ */ -+ err = -EPROBE_DEFER; -+ goto err_defer; -+ } -+ dev_info(dev, "Connected to %s PHY.\n", phy_modes(if_mode)); -+ -+probe_fixed_link: -+ if (!netdev->phydev) { -+ struct fixed_phy_status status = { -+ .link = 1, -+ /* fixed-phys don't support 10Gbps speed for now */ -+ .speed = 1000, -+ .duplex = 1, -+ }; -+ -+ /* try to register a fixed link phy */ -+ netdev->phydev = fixed_phy_register(PHY_POLL, &status, -1, NULL); -+ if (!netdev->phydev || IS_ERR(netdev->phydev)) { -+ dev_err(dev, "error trying to register fixed PHY\n"); -+ /* So we don't crash unregister_netdev() later on */ -+ netdev->phydev = NULL; -+ err = -EFAULT; -+ goto err_no_phy; -+ } -+ dev_info(dev, "Registered fixed PHY.\n"); -+ } -+ -+ /* start PHY state machine */ -+#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS -+ dpaa2_mac_open(netdev); -+#else /* CONFIG_FSL_DPAA2_MAC_NETDEVS */ -+ phy_start(netdev->phydev); -+#endif /* CONFIG_FSL_DPAA2_MAC_NETDEVS */ -+ return 0; -+ -+err_defer: -+err_no_phy: -+#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS -+ unregister_netdev(netdev); -+err_free_irq: -+#endif -+ teardown_irqs(mc_dev); -+err_close: -+ dpmac_close(mc_dev->mc_io, 0, mc_dev->mc_handle); -+err_free_mcp: -+ fsl_mc_portal_free(mc_dev->mc_io); -+err_free_netdev: -+ free_netdev(netdev); -+err_exit: -+ return err; -+} -+ -+static int dpaa2_mac_remove(struct fsl_mc_device *mc_dev) -+{ -+ struct device *dev = &mc_dev->dev; -+ struct dpaa2_mac_priv *priv = dev_get_drvdata(dev); -+ -+ unregister_netdev(priv->netdev); -+ teardown_irqs(priv->mc_dev); -+ dpmac_close(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle); -+ fsl_mc_portal_free(priv->mc_dev->mc_io); -+ free_netdev(priv->netdev); -+ -+ dev_set_drvdata(dev, NULL); -+ kfree(priv); -+ -+ return 0; -+} -+ -+static const struct fsl_mc_device_match_id dpaa2_mac_match_id_table[] = { -+ { -+ .vendor = FSL_MC_VENDOR_FREESCALE, -+ .obj_type = "dpmac", -+ .ver_major = DPMAC_VER_MAJOR, -+ .ver_minor = DPMAC_VER_MINOR, -+ }, -+ {} -+}; -+ -+static struct fsl_mc_driver dpaa2_mac_drv = { -+ .driver = { -+ .name = KBUILD_MODNAME, -+ .owner = THIS_MODULE, -+ }, -+ .probe = dpaa2_mac_probe, -+ .remove = dpaa2_mac_remove, -+ .match_id_table = dpaa2_mac_match_id_table, -+}; -+ -+module_fsl_mc_driver(dpaa2_mac_drv); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("DPAA2 PHY proxy interface driver"); diff --git a/target/linux/layerscape/patches-4.4/7209-staging-fsl-dpaa2-mac-Interrupt-code-cleanup.patch b/target/linux/layerscape/patches-4.4/7209-staging-fsl-dpaa2-mac-Interrupt-code-cleanup.patch deleted file mode 100644 index 9ed721f7fa..0000000000 --- a/target/linux/layerscape/patches-4.4/7209-staging-fsl-dpaa2-mac-Interrupt-code-cleanup.patch +++ /dev/null @@ -1,182 +0,0 @@ -From bb42890533f9592e8d30654b4e0b19c3cf7caaec Mon Sep 17 00:00:00 2001 -From: Ioana Radulescu -Date: Fri, 1 Apr 2016 18:38:18 +0300 -Subject: [PATCH 209/226] staging: fsl-dpaa2/mac: Interrupt code cleanup - -Cleanup and a couple of minor fixes for the interrupt -handling code: -* Removed a few unnecessary checks, unify format for others -* Don't print error/debug messages in interrupt handler -* No need to explicitly disable DPMAC interrupts before -configuring them -* Use unlikely in interrupt handler routine error checks -* if status register is zero or we're unable to read its value, -return IRQ_NONE instead of IRQ_HANDLED -* always clear the entire status register, not just the bit(s) -that were treated - -Signed-off-by: Ioana Radulescu -(cherry picked from commit 4b46eec16c56e4f453ca1558af9aceaf6ffe831a) -(Stuart:resolved merge conflict) -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-dpaa2/mac/mac.c | 77 ++++++++--------------------------- - 1 file changed, 16 insertions(+), 61 deletions(-) - ---- a/drivers/staging/fsl-dpaa2/mac/mac.c -+++ b/drivers/staging/fsl-dpaa2/mac/mac.c -@@ -132,7 +132,7 @@ static void dpaa2_mac_link_changed(struc - } - - /* IRQ bits that we handle */ --static const u32 dpmac_irq_mask = DPMAC_IRQ_EVENT_LINK_CFG_REQ; -+static const u32 dpmac_irq_mask = DPMAC_IRQ_EVENT_LINK_CFG_REQ; - - #ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS - static netdev_tx_t dpaa2_mac_drop_frame(struct sk_buff *skb, -@@ -345,16 +345,13 @@ static const struct ethtool_ops dpaa2_ma - }; - #endif /* CONFIG_FSL_DPAA2_MAC_NETDEVS */ - --static int configure_link(struct dpaa2_mac_priv *priv, -- struct dpmac_link_cfg *cfg) -+static void configure_link(struct dpaa2_mac_priv *priv, -+ struct dpmac_link_cfg *cfg) - { - struct phy_device *phydev = priv->netdev->phydev; - -- if (!phydev) { -- dev_warn(priv->netdev->dev.parent, -- "asked to change PHY settings but PHY ref is NULL, ignoring\n"); -- return 0; -- } -+ if (unlikely(!phydev)) -+ return; - - phydev->speed = cfg->rate; - phydev->duplex = !!(cfg->options & DPMAC_LINK_OPT_HALF_DUPLEX); -@@ -368,8 +365,6 @@ static int configure_link(struct dpaa2_m - } - - phy_start_aneg(phydev); -- -- return 0; - } - - static irqreturn_t dpaa2_mac_irq_handler(int irq_num, void *arg) -@@ -378,53 +373,29 @@ static irqreturn_t dpaa2_mac_irq_handler - struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - struct dpaa2_mac_priv *priv = dev_get_drvdata(dev); - struct dpmac_link_cfg link_cfg; -- u8 irq_index = DPMAC_IRQ_INDEX; -- u32 status, clear = 0; -+ u32 status; - int err; - -- if (mc_dev->irqs[0]->msi_desc->irq != irq_num) { -- dev_err(dev, "received unexpected interrupt %d!\n", irq_num); -- goto err; -- } -- - err = dpmac_get_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle, -- irq_index, &status); -- if (err) { -- dev_err(dev, "dpmac_get_irq_status err %d\n", err); -- clear = ~0x0u; -- goto out; -- } -+ DPMAC_IRQ_INDEX, &status); -+ if (unlikely(err || !status)) -+ return IRQ_NONE; - - /* DPNI-initiated link configuration; 'ifconfig up' also calls this */ - if (status & DPMAC_IRQ_EVENT_LINK_CFG_REQ) { -- dev_dbg(dev, "DPMAC IRQ %d - LINK_CFG_REQ\n", irq_num); -- clear |= DPMAC_IRQ_EVENT_LINK_CFG_REQ; -- - err = dpmac_get_link_cfg(mc_dev->mc_io, 0, mc_dev->mc_handle, - &link_cfg); -- if (err) { -- dev_err(dev, "dpmac_get_link_cfg err %d\n", err); -+ if (unlikely(err)) - goto out; -- } - -- err = configure_link(priv, &link_cfg); -- if (err) { -- dev_err(dev, "cannot configure link\n"); -- goto out; -- } -+ configure_link(priv, &link_cfg); - } - - out: -- err = dpmac_clear_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle, -- irq_index, clear); -- if (err < 0) -- dev_err(&mc_dev->dev, "dpmac_clear_irq_status() err %d\n", err); -+ dpmac_clear_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle, -+ DPMAC_IRQ_INDEX, status); - - return IRQ_HANDLED; -- --err: -- dev_warn(dev, "DPMAC IRQ %d was not handled!\n", irq_num); -- return IRQ_NONE; - } - - static int setup_irqs(struct fsl_mc_device *mc_dev) -@@ -437,19 +408,6 @@ static int setup_irqs(struct fsl_mc_devi - return err; - } - -- err = dpmac_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle, -- DPMAC_IRQ_INDEX, dpmac_irq_mask); -- if (err < 0) { -- dev_err(&mc_dev->dev, "dpmac_set_irq_mask err %d\n", err); -- goto free_irq; -- } -- err = dpmac_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle, -- DPMAC_IRQ_INDEX, 0); -- if (err) { -- dev_err(&mc_dev->dev, "dpmac_set_irq_enable err %d\n", err); -- goto free_irq; -- } -- - err = devm_request_threaded_irq(&mc_dev->dev, - mc_dev->irqs[0]->msi_desc->irq, - NULL, &dpaa2_mac_irq_handler, -@@ -463,7 +421,7 @@ static int setup_irqs(struct fsl_mc_devi - - err = dpmac_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle, - DPMAC_IRQ_INDEX, dpmac_irq_mask); -- if (err < 0) { -+ if (err) { - dev_err(&mc_dev->dev, "dpmac_set_irq_mask err %d\n", err); - goto free_irq; - } -@@ -490,12 +448,12 @@ static void teardown_irqs(struct fsl_mc_ - - err = dpmac_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle, - DPMAC_IRQ_INDEX, dpmac_irq_mask); -- if (err < 0) -+ if (err) - dev_err(&mc_dev->dev, "dpmac_set_irq_mask err %d\n", err); - - err = dpmac_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle, - DPMAC_IRQ_INDEX, 0); -- if (err < 0) -+ if (err) - dev_err(&mc_dev->dev, "dpmac_set_irq_enable err %d\n", err); - - devm_free_irq(&mc_dev->dev, mc_dev->irqs[0]->msi_desc->irq, &mc_dev->dev); -@@ -562,9 +520,6 @@ static int dpaa2_mac_probe(struct fsl_mc - phy_interface_t if_mode; - int err = 0; - -- /* just being completely paranoid */ -- if (!mc_dev) -- return -EFAULT; - dev = &mc_dev->dev; - - /* prepare a net_dev structure to make the phy lib API happy */ diff --git a/target/linux/layerscape/patches-4.4/7210-staging-fsl-dpaa2-mac-Fix-unregister_netdev-issue.patch b/target/linux/layerscape/patches-4.4/7210-staging-fsl-dpaa2-mac-Fix-unregister_netdev-issue.patch deleted file mode 100644 index ea582835c8..0000000000 --- a/target/linux/layerscape/patches-4.4/7210-staging-fsl-dpaa2-mac-Fix-unregister_netdev-issue.patch +++ /dev/null @@ -1,42 +0,0 @@ -From e74b6010eca026625ba4e39c80620320ca777deb Mon Sep 17 00:00:00 2001 -From: Ioana Radulescu -Date: Tue, 5 Apr 2016 13:35:14 +0300 -Subject: [PATCH 210/226] staging: fsl-dpaa2/mac: Fix unregister_netdev issue - -We only register the netdevice associated with a mac object if -ONFIG_FSL_DPAA2_MAC_NETDEV is set, but we always unregister it -during device remove(). Fix this by ifdef-ing the unregister -operation. - -Also ifdef the change in netdevice name as it only makes sense -under this option. - -Signed-off-by: Ioana Radulescu -(cherry picked from commit dd6a5313e194168d46fef495a6e3bc5207801473) ---- - drivers/staging/fsl-dpaa2/mac/mac.c | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/staging/fsl-dpaa2/mac/mac.c -+++ b/drivers/staging/fsl-dpaa2/mac/mac.c -@@ -534,7 +534,10 @@ static int dpaa2_mac_probe(struct fsl_mc - priv->netdev = netdev; - - SET_NETDEV_DEV(netdev, dev); -+ -+#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS - snprintf(netdev->name, IFNAMSIZ, "mac%d", mc_dev->obj_desc.id); -+#endif - - dev_set_drvdata(dev, priv); - -@@ -684,7 +687,9 @@ static int dpaa2_mac_remove(struct fsl_m - struct device *dev = &mc_dev->dev; - struct dpaa2_mac_priv *priv = dev_get_drvdata(dev); - -+#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS - unregister_netdev(priv->netdev); -+#endif - teardown_irqs(priv->mc_dev); - dpmac_close(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle); - fsl_mc_portal_free(priv->mc_dev->mc_io); diff --git a/target/linux/layerscape/patches-4.4/7211-staging-fsl-dpaa2-mac-Don-t-call-devm_free_irq.patch b/target/linux/layerscape/patches-4.4/7211-staging-fsl-dpaa2-mac-Don-t-call-devm_free_irq.patch deleted file mode 100644 index 46ecaea1e1..0000000000 --- a/target/linux/layerscape/patches-4.4/7211-staging-fsl-dpaa2-mac-Don-t-call-devm_free_irq.patch +++ /dev/null @@ -1,42 +0,0 @@ -From b4d01330c66cbab3563c58f66f73f55726c09aec Mon Sep 17 00:00:00 2001 -From: Ioana Radulescu -Date: Tue, 5 Apr 2016 17:54:14 +0300 -Subject: [PATCH 211/226] staging: fsl-dpaa2/mac: Don't call devm_free_irq - -MAC interrupts are registered with devm_request_threaded_irq(), so -there's no need to explicitly unregister them in case of a probe -error or at device remove, as the kernel will take care of that for us. - -Signed-off-by: Ioana Radulescu -(cherry picked from commit 58e0fd23ade4b13e0a3c7e5f201802013e12df1c) -(Stuart: resolved merge conflict) -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-dpaa2/mac/mac.c | 5 +---- - 1 file changed, 1 insertion(+), 4 deletions(-) - ---- a/drivers/staging/fsl-dpaa2/mac/mac.c -+++ b/drivers/staging/fsl-dpaa2/mac/mac.c -@@ -429,13 +429,11 @@ static int setup_irqs(struct fsl_mc_devi - DPMAC_IRQ_INDEX, 1); - if (err) { - dev_err(&mc_dev->dev, "dpmac_set_irq_enable err %d\n", err); -- goto unregister_irq; -+ goto free_irq; - } - - return 0; - --unregister_irq: -- devm_free_irq(&mc_dev->dev, mc_dev->irqs[0]->msi_desc->irq, &mc_dev->dev); - free_irq: - fsl_mc_free_irqs(mc_dev); - -@@ -456,7 +454,6 @@ static void teardown_irqs(struct fsl_mc_ - if (err) - dev_err(&mc_dev->dev, "dpmac_set_irq_enable err %d\n", err); - -- devm_free_irq(&mc_dev->dev, mc_dev->irqs[0]->msi_desc->irq, &mc_dev->dev); - fsl_mc_free_irqs(mc_dev); - } - diff --git a/target/linux/layerscape/patches-4.4/7212-staging-fsl-dpaa2-mac-Use-of_property_read_32.patch b/target/linux/layerscape/patches-4.4/7212-staging-fsl-dpaa2-mac-Use-of_property_read_32.patch deleted file mode 100644 index 8ab6de9bf0..0000000000 --- a/target/linux/layerscape/patches-4.4/7212-staging-fsl-dpaa2-mac-Use-of_property_read_32.patch +++ /dev/null @@ -1,43 +0,0 @@ -From e554a03fe11719db373be3c54ce8f230a98dd5e4 Mon Sep 17 00:00:00 2001 -From: Ioana Radulescu -Date: Wed, 6 Apr 2016 15:05:47 +0300 -Subject: [PATCH 212/226] staging: fsl-dpaa2/mac: Use of_property_read_32() - -Simplify reading of the dpmac id from device tree. - -Signed-off-by: Ioana Radulescu -(cherry picked from commit b0562bda063f95923bcd8b78dea84a6e0587d3da) ---- - drivers/staging/fsl-dpaa2/mac/mac.c | 13 +++++-------- - 1 file changed, 5 insertions(+), 8 deletions(-) - ---- a/drivers/staging/fsl-dpaa2/mac/mac.c -+++ b/drivers/staging/fsl-dpaa2/mac/mac.c -@@ -461,9 +461,8 @@ static struct device_node *lookup_node(s - { - struct device_node *dpmacs, *dpmac = NULL; - struct device_node *mc_node = dev->of_node; -- const void *id; -- int lenp; -- int dpmac_id_be32 = cpu_to_be32(dpmac_id); -+ u32 id; -+ int err; - - dpmacs = of_find_node_by_name(mc_node, "dpmacs"); - if (!dpmacs) { -@@ -472,12 +471,10 @@ static struct device_node *lookup_node(s - } - - while ((dpmac = of_get_next_child(dpmacs, dpmac))) { -- id = of_get_property(dpmac, "reg", &lenp); -- if (!id || lenp != sizeof(int)) { -- dev_warn(dev, "Unsuitable reg property in dpmac node\n"); -+ err = of_property_read_u32(dpmac, "reg", &id); -+ if (err) - continue; -- } -- if (*(int *)id == dpmac_id_be32) -+ if (id == dpmac_id) - return dpmac; - } - diff --git a/target/linux/layerscape/patches-4.4/7213-staging-fsl-dpaa2-mac-Remove-version-checks.patch b/target/linux/layerscape/patches-4.4/7213-staging-fsl-dpaa2-mac-Remove-version-checks.patch deleted file mode 100644 index 2c7bb88cc0..0000000000 --- a/target/linux/layerscape/patches-4.4/7213-staging-fsl-dpaa2-mac-Remove-version-checks.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 3e4dc755337ca86d29c9f21f5225a77595aee032 Mon Sep 17 00:00:00 2001 -From: Ioana Radulescu -Date: Wed, 6 Apr 2016 12:12:06 +0300 -Subject: [PATCH 213/226] staging: fsl-dpaa2/mac: Remove version checks - -We intend to ensure backward compatibility with all MC versions -going forward, so we don't require an exact version match anymore -between MAC driver, DPMAC API version and DPMAC object version in -MC firmware. - -Signed-off-by: Ioana Radulescu -(cherry picked from commit eafc210ef421fb0dca67b67bf1a2fe98cd060c31) ---- - drivers/staging/fsl-dpaa2/mac/mac.c | 29 ++--------------------------- - 1 file changed, 2 insertions(+), 27 deletions(-) - ---- a/drivers/staging/fsl-dpaa2/mac/mac.c -+++ b/drivers/staging/fsl-dpaa2/mac/mac.c -@@ -481,30 +481,6 @@ static struct device_node *lookup_node(s - return NULL; - } - --static int check_dpmac_version(struct dpaa2_mac_priv *priv) --{ -- struct device *dev = &priv->mc_dev->dev; -- int mc_version = priv->attr.version.major; -- -- /* Check that the FLIB-defined version matches the one reported by MC */ -- if (mc_version != DPMAC_VER_MAJOR) { -- dev_err(dev, "DPMAC FLIB version mismatch: MC says %d, we have %d\n", -- mc_version, DPMAC_VER_MAJOR); -- return -EINVAL; -- } -- -- /* ... and that we actually support it */ -- if (mc_version < DPAA2_SUPPORTED_DPMAC_VERSION) { -- dev_err(dev, "Unsupported DPMAC FLIB version (%d)\n", -- mc_version); -- return -EINVAL; -- } -- -- dev_dbg(dev, "Using DPMAC FLIB version %d\n", mc_version); -- -- return 0; --} -- - static int dpaa2_mac_probe(struct fsl_mc_device *mc_dev) - { - struct device *dev; -@@ -558,9 +534,8 @@ static int dpaa2_mac_probe(struct fsl_mc - goto err_close; - } - -- err = check_dpmac_version(priv); -- if (err) -- goto err_close; -+ dev_info_once(dev, "Using DPMAC API %d.%d\n", -+ priv->attr.version.major, priv->attr.version.minor); - - /* Look up the DPMAC node in the device-tree. */ - dpmac_node = lookup_node(dev, priv->attr.id); diff --git a/target/linux/layerscape/patches-4.4/7214-staging-fsl-dpaa2-mac-match-id-cleanup.patch b/target/linux/layerscape/patches-4.4/7214-staging-fsl-dpaa2-mac-match-id-cleanup.patch deleted file mode 100644 index 850d0e630c..0000000000 --- a/target/linux/layerscape/patches-4.4/7214-staging-fsl-dpaa2-mac-match-id-cleanup.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 137f5f17bad655024d18123b1be696ad6b9ec729 Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Wed, 15 Jun 2016 14:04:32 -0500 -Subject: [PATCH 214/226] staging: fsl-dpaa2/mac: match id cleanup - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-dpaa2/mac/mac.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/staging/fsl-dpaa2/mac/mac.c -+++ b/drivers/staging/fsl-dpaa2/mac/mac.c -@@ -670,12 +670,10 @@ static int dpaa2_mac_remove(struct fsl_m - return 0; - } - --static const struct fsl_mc_device_match_id dpaa2_mac_match_id_table[] = { -+static const struct fsl_mc_device_id dpaa2_mac_match_id_table[] = { - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dpmac", -- .ver_major = DPMAC_VER_MAJOR, -- .ver_minor = DPMAC_VER_MINOR, - }, - {} - }; diff --git a/target/linux/layerscape/patches-4.4/7215-dpaa2-evb-Added-Edge-Virtual-Bridge-driver.patch b/target/linux/layerscape/patches-4.4/7215-dpaa2-evb-Added-Edge-Virtual-Bridge-driver.patch deleted file mode 100644 index 344c2aec31..0000000000 --- a/target/linux/layerscape/patches-4.4/7215-dpaa2-evb-Added-Edge-Virtual-Bridge-driver.patch +++ /dev/null @@ -1,2918 +0,0 @@ -From 54bcaca10728c1a1c8adfa48124ea79cce4ef929 Mon Sep 17 00:00:00 2001 -From: Razvan Stefanescu -Date: Tue, 22 Sep 2015 08:43:08 +0300 -Subject: [PATCH 215/226] dpaa2-evb: Added Edge Virtual Bridge driver - -This is a commit of the cummulative, squashed dpaa2-evb patches. -All the commit logs are preserved below. - -Signed-off-by: Stuart Yoder - ----------------------------------------------------------------- - -dpaa2-evb: Added Edge Virtual Bridge driver - -This contains the following patches migrated from linux-v4.0: -staging: fsl-dpaa2: evb: Added Edge Virtual Bridge driver -staging: fsl-dpaa2: evb: Added ethtool port counters -staging: fsl-dpaa2: evb: Include by default in configuration -staging: fsl-dpaa2: evb: Rebasing onto kernel 4.0 -staging: fsl-dpaa2: evb: Port to MC-0.7 FLibs -dpaa2-evb: Set carrier state on port open -dpaa2-evb: Add support for link state update -dpaa2-evb: Update flib to MC 8.0.1 -staging: fsl-mc: migrated remaining flibs for MC fw 8.0.0 (split) - -Inital patches have been signed-off by: -Alex Marginean -J. German Rivera -Bogdan Hamciuc -Razvan Stefanescu - -And reviewed by: -Stuart Yoder - -Porting to linux-v4.1 requires changes related to iflink usage and -ndo_bridge_getlink() parameters list. - -Signed-off-by: Razvan Stefanescu - -dpaa2-evb: Port to linux-v4.1 - -Update iflink usage. -Update evb_getlink() parameter list to match ndo_bridge_getlink(). - -Signed-off-by: Razvan Stefanescu - -dpaa2-evb: Add VLAN_8021Q dependency - -EVB traffic steering methods related to VLAN require VLAN support in kernel. - -Signed-off-by: Razvan Stefanescu - -dpaa2-evb: Update dpdmux binary interface to 5.0 - -This corresponds to MC release 0.8.0. - -Signed-off-by: Razvan Stefanescu - -dpaa2-evb: Add support to set max frame length. - -All the packets bigger than max_frame_length will be dropped. - -Signed-off-by: Mihaela Panescu - -dpaa2-evb: resolve compile issues on uprev to 4.5 - --irq_number field no longer exists in fsl-mc interrupt - struct --netdev_master_upper_dev_link() has 2 new parameters, which - are set to NULL for now - -Signed-off-by: Stuart Yoder ---- - MAINTAINERS | 6 + - drivers/staging/fsl-dpaa2/Kconfig | 1 + - drivers/staging/fsl-dpaa2/Makefile | 1 + - drivers/staging/fsl-dpaa2/evb/Kconfig | 8 + - drivers/staging/fsl-dpaa2/evb/Makefile | 10 + - drivers/staging/fsl-dpaa2/evb/dpdmux-cmd.h | 256 ++++++ - drivers/staging/fsl-dpaa2/evb/dpdmux.c | 567 +++++++++++++ - drivers/staging/fsl-dpaa2/evb/dpdmux.h | 724 +++++++++++++++++ - drivers/staging/fsl-dpaa2/evb/evb.c | 1216 ++++++++++++++++++++++++++++ - 9 files changed, 2789 insertions(+) - create mode 100644 drivers/staging/fsl-dpaa2/evb/Kconfig - create mode 100644 drivers/staging/fsl-dpaa2/evb/Makefile - create mode 100644 drivers/staging/fsl-dpaa2/evb/dpdmux-cmd.h - create mode 100644 drivers/staging/fsl-dpaa2/evb/dpdmux.c - create mode 100644 drivers/staging/fsl-dpaa2/evb/dpdmux.h - create mode 100644 drivers/staging/fsl-dpaa2/evb/evb.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -4560,6 +4560,12 @@ L: linux-kernel@vger.kernel.org - S: Maintained - F: drivers/staging/fsl-dpaa2/mac/ - -++FREESCALE DPAA2 EDGE VIRTUAL BRIDGE DRIVER -+M: Alex Marginean -+L: linux-kernel@vger.kernel.org -+S: Maintained -+F: drivers/staging/fsl-dpaa2/evb/ -+ - FREEVXFS FILESYSTEM - M: Christoph Hellwig - W: ftp://ftp.openlinux.org/pub/people/hch/vxfs ---- a/drivers/staging/fsl-dpaa2/Kconfig -+++ b/drivers/staging/fsl-dpaa2/Kconfig -@@ -10,3 +10,4 @@ config FSL_DPAA2 - # TODO move DPIO driver in-here? - source "drivers/staging/fsl-dpaa2/ethernet/Kconfig" - source "drivers/staging/fsl-dpaa2/mac/Kconfig" -+source "drivers/staging/fsl-dpaa2/evb/Kconfig" ---- a/drivers/staging/fsl-dpaa2/Makefile -+++ b/drivers/staging/fsl-dpaa2/Makefile -@@ -4,3 +4,4 @@ - - obj-$(CONFIG_FSL_DPAA2_ETH) += ethernet/ - obj-$(CONFIG_FSL_DPAA2_MAC) += mac/ -+obj-$(CONFIG_FSL_DPAA2_EVB) += evb/ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/evb/Kconfig -@@ -0,0 +1,8 @@ -+config FSL_DPAA2_EVB -+ tristate "DPAA2 Edge Virtual Bridge" -+ depends on FSL_MC_BUS && FSL_DPAA2 && FSL_DPAA2_ETH -+ select FSL_DPAA2_MAC -+ select VLAN_8021Q -+ default y -+ ---help--- -+ Prototype driver for DPAA2 Edge Virtual Bridge. ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/evb/Makefile -@@ -0,0 +1,10 @@ -+ -+obj-$(CONFIG_FSL_DPAA2_EVB) += dpaa2-evb.o -+ -+dpaa2-evb-objs := evb.o dpdmux.o -+ -+all: -+ make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules -+ -+clean: -+ make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/evb/dpdmux-cmd.h -@@ -0,0 +1,256 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef _FSL_DPDMUX_CMD_H -+#define _FSL_DPDMUX_CMD_H -+ -+/* DPDMUX Version */ -+#define DPDMUX_VER_MAJOR 5 -+#define DPDMUX_VER_MINOR 0 -+ -+/* Command IDs */ -+#define DPDMUX_CMDID_CLOSE 0x800 -+#define DPDMUX_CMDID_OPEN 0x806 -+#define DPDMUX_CMDID_CREATE 0x906 -+#define DPDMUX_CMDID_DESTROY 0x900 -+ -+#define DPDMUX_CMDID_ENABLE 0x002 -+#define DPDMUX_CMDID_DISABLE 0x003 -+#define DPDMUX_CMDID_GET_ATTR 0x004 -+#define DPDMUX_CMDID_RESET 0x005 -+#define DPDMUX_CMDID_IS_ENABLED 0x006 -+ -+#define DPDMUX_CMDID_SET_IRQ 0x010 -+#define DPDMUX_CMDID_GET_IRQ 0x011 -+#define DPDMUX_CMDID_SET_IRQ_ENABLE 0x012 -+#define DPDMUX_CMDID_GET_IRQ_ENABLE 0x013 -+#define DPDMUX_CMDID_SET_IRQ_MASK 0x014 -+#define DPDMUX_CMDID_GET_IRQ_MASK 0x015 -+#define DPDMUX_CMDID_GET_IRQ_STATUS 0x016 -+#define DPDMUX_CMDID_CLEAR_IRQ_STATUS 0x017 -+ -+#define DPDMUX_CMDID_UL_SET_MAX_FRAME_LENGTH 0x0a1 -+ -+#define DPDMUX_CMDID_UL_RESET_COUNTERS 0x0a3 -+ -+#define DPDMUX_CMDID_IF_SET_ACCEPTED_FRAMES 0x0a7 -+#define DPDMUX_CMDID_IF_GET_ATTR 0x0a8 -+ -+#define DPDMUX_CMDID_IF_ADD_L2_RULE 0x0b0 -+#define DPDMUX_CMDID_IF_REMOVE_L2_RULE 0x0b1 -+#define DPDMUX_CMDID_IF_GET_COUNTER 0x0b2 -+#define DPDMUX_CMDID_IF_SET_LINK_CFG 0x0b3 -+#define DPDMUX_CMDID_IF_GET_LINK_STATE 0x0b4 -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_OPEN(cmd, dpdmux_id) \ -+ MC_CMD_OP(cmd, 0, 0, 32, int, dpdmux_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_CREATE(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, enum dpdmux_method, cfg->method);\ -+ MC_CMD_OP(cmd, 0, 8, 8, enum dpdmux_manip, cfg->manip);\ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs);\ -+ MC_CMD_OP(cmd, 1, 0, 16, uint16_t, cfg->adv.max_dmat_entries);\ -+ MC_CMD_OP(cmd, 1, 16, 16, uint16_t, cfg->adv.max_mc_groups);\ -+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, cfg->adv.max_vlan_ids);\ -+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->adv.options);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_RSP_IS_ENABLED(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\ -+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\ -+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_GET_IRQ(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_RSP_GET_IRQ(cmd, type, irq_cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr); \ -+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \ -+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_SET_IRQ_ENABLE(cmd, irq_index, en) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, en);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_GET_IRQ_ENABLE(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_RSP_GET_IRQ_ENABLE(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_GET_IRQ_MASK(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_RSP_GET_IRQ_MASK(cmd, mask) \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_RSP_GET_IRQ_STATUS(cmd, status) \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status) \ -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \ -+} while (0) -+ -+#define DPDMUX_RSP_GET_ATTR(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 8, enum dpdmux_method, attr->method);\ -+ MC_RSP_OP(cmd, 0, 8, 8, enum dpdmux_manip, attr->manip);\ -+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->num_ifs);\ -+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->mem_size);\ -+ MC_RSP_OP(cmd, 2, 0, 32, int, attr->id);\ -+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, attr->options);\ -+ MC_RSP_OP(cmd, 4, 0, 16, uint16_t, attr->version.major);\ -+ MC_RSP_OP(cmd, 4, 16, 16, uint16_t, attr->version.minor);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_UL_SET_MAX_FRAME_LENGTH(cmd, max_frame_length) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, max_frame_length) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_IF_SET_ACCEPTED_FRAMES(cmd, if_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 4, enum dpdmux_accepted_frames_type, cfg->type);\ -+ MC_CMD_OP(cmd, 0, 20, 4, enum dpdmux_unaccepted_frames_action, \ -+ cfg->unaccept_act);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_IF_GET_ATTR(cmd, if_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_RSP_IF_GET_ATTR(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 56, 4, enum dpdmux_accepted_frames_type, \ -+ attr->accept_frame_type);\ -+ MC_RSP_OP(cmd, 0, 24, 1, int, attr->enabled);\ -+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->rate);\ -+} while (0) -+ -+#define DPDMUX_CMD_IF_REMOVE_L2_RULE(cmd, if_id, l2_rule) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, l2_rule->mac_addr[5]);\ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, l2_rule->mac_addr[4]);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, l2_rule->mac_addr[3]);\ -+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, l2_rule->mac_addr[2]);\ -+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, l2_rule->mac_addr[1]);\ -+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, l2_rule->mac_addr[0]);\ -+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, l2_rule->vlan_id);\ -+} while (0) -+ -+#define DPDMUX_CMD_IF_ADD_L2_RULE(cmd, if_id, l2_rule) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, l2_rule->mac_addr[5]);\ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, l2_rule->mac_addr[4]);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, l2_rule->mac_addr[3]);\ -+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, l2_rule->mac_addr[2]);\ -+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, l2_rule->mac_addr[1]);\ -+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, l2_rule->mac_addr[0]);\ -+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, l2_rule->vlan_id);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_IF_GET_COUNTER(cmd, if_id, counter_type) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 8, enum dpdmux_counter_type, counter_type);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_RSP_IF_GET_COUNTER(cmd, counter) \ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_IF_SET_LINK_CFG(cmd, if_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate);\ -+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_CMD_IF_GET_LINK_STATE(cmd, if_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPDMUX_RSP_IF_GET_LINK_STATE(cmd, state) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 32, 1, int, state->up);\ -+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, state->rate);\ -+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\ -+} while (0) -+ -+#endif /* _FSL_DPDMUX_CMD_H */ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/evb/dpdmux.c -@@ -0,0 +1,567 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include "../../fsl-mc/include/mc-sys.h" -+#include "../../fsl-mc/include/mc-cmd.h" -+#include "dpdmux.h" -+#include "dpdmux-cmd.h" -+ -+int dpdmux_open(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ int dpdmux_id, -+ uint16_t *token) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_OPEN, -+ cmd_flags, -+ 0); -+ DPDMUX_CMD_OPEN(cmd, dpdmux_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header); -+ -+ return 0; -+} -+ -+int dpdmux_close(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_CLOSE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_create(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ const struct dpdmux_cfg *cfg, -+ uint16_t *token) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_CREATE, -+ cmd_flags, -+ 0); -+ DPDMUX_CMD_CREATE(cmd, cfg); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header); -+ -+ return 0; -+} -+ -+int dpdmux_destroy(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_DESTROY, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_ENABLE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_DISABLE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_is_enabled(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IS_ENABLED, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPDMUX_RSP_IS_ENABLED(cmd, *en); -+ -+ return 0; -+} -+ -+int dpdmux_reset(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_RESET, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_set_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ struct dpdmux_irq_cfg *irq_cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_IRQ, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_SET_IRQ(cmd, irq_index, irq_cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_get_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ int *type, -+ struct dpdmux_irq_cfg *irq_cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_GET_IRQ(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPDMUX_RSP_GET_IRQ(cmd, *type, irq_cfg); -+ -+ return 0; -+} -+ -+int dpdmux_set_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_SET_IRQ_ENABLE(cmd, irq_index, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_get_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_GET_IRQ_ENABLE(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPDMUX_RSP_GET_IRQ_ENABLE(cmd, *en); -+ -+ return 0; -+} -+ -+int dpdmux_set_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t mask) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_IRQ_MASK, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_SET_IRQ_MASK(cmd, irq_index, mask); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_get_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *mask) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ_MASK, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_GET_IRQ_MASK(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPDMUX_RSP_GET_IRQ_MASK(cmd, *mask); -+ -+ return 0; -+} -+ -+int dpdmux_get_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *status) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ_STATUS, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_GET_IRQ_STATUS(cmd, irq_index, *status); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPDMUX_RSP_GET_IRQ_STATUS(cmd, *status); -+ -+ return 0; -+} -+ -+int dpdmux_clear_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t status) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_CLEAR_IRQ_STATUS, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpdmux_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_ATTR, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPDMUX_RSP_GET_ATTR(cmd, attr); -+ -+ return 0; -+} -+ -+int dpdmux_ul_set_max_frame_length(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t max_frame_length) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_UL_SET_MAX_FRAME_LENGTH, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_UL_SET_MAX_FRAME_LENGTH(cmd, max_frame_length); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_ul_reset_counters(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_UL_RESET_COUNTERS, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_if_set_accepted_frames(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpdmux_accepted_frames *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_SET_ACCEPTED_FRAMES, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_IF_SET_ACCEPTED_FRAMES(cmd, if_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_if_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpdmux_if_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_GET_ATTR, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_IF_GET_ATTR(cmd, if_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPDMUX_RSP_IF_GET_ATTR(cmd, attr); -+ -+ return 0; -+} -+ -+int dpdmux_if_remove_l2_rule(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpdmux_l2_rule *rule) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_REMOVE_L2_RULE, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_IF_REMOVE_L2_RULE(cmd, if_id, rule); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_if_add_l2_rule(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpdmux_l2_rule *rule) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_ADD_L2_RULE, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_IF_ADD_L2_RULE(cmd, if_id, rule); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_if_get_counter(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ enum dpdmux_counter_type counter_type, -+ uint64_t *counter) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_GET_COUNTER, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_IF_GET_COUNTER(cmd, if_id, counter_type); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPDMUX_RSP_IF_GET_COUNTER(cmd, *counter); -+ -+ return 0; -+} -+ -+int dpdmux_if_set_link_cfg(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpdmux_link_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_SET_LINK_CFG, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_IF_SET_LINK_CFG(cmd, if_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpdmux_if_get_link_state(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpdmux_link_state *state) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_GET_LINK_STATE, -+ cmd_flags, -+ token); -+ DPDMUX_CMD_IF_GET_LINK_STATE(cmd, if_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPDMUX_RSP_IF_GET_LINK_STATE(cmd, state); -+ -+ return 0; -+} ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/evb/dpdmux.h -@@ -0,0 +1,724 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef __FSL_DPDMUX_H -+#define __FSL_DPDMUX_H -+ -+#include "../../fsl-mc/include/net.h" -+ -+struct fsl_mc_io; -+ -+/* Data Path Demux API -+ * Contains API for handling DPDMUX topology and functionality -+ */ -+ -+/** -+ * dpdmux_open() - Open a control session for the specified object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @dpdmux_id: DPDMUX unique ID -+ * @token: Returned token; use in subsequent API calls -+ * -+ * This function can be used to open a control session for an -+ * already created object; an object may have been declared in -+ * the DPL or by calling the dpdmux_create() function. -+ * This function returns a unique authentication token, -+ * associated with the specific object ID and the specific MC -+ * portal; this token must be used in all subsequent commands for -+ * this specific object. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_open(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ int dpdmux_id, -+ uint16_t *token); -+ -+/** -+ * dpdmux_close() - Close the control session of the object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * -+ * After this function is called, no further operations are -+ * allowed on the object without opening a new control session. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_close(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * DPDMUX general options -+ */ -+ -+/** -+ * Enable bridging between internal interfaces -+ */ -+#define DPDMUX_OPT_BRIDGE_EN 0x0000000000000002ULL -+ -+#define DPDMUX_IRQ_INDEX_IF 0x0000 -+#define DPDMUX_IRQ_INDEX 0x0001 -+ -+/** -+ * IRQ event - Indicates that the link state changed -+ */ -+#define DPDMUX_IRQ_EVENT_LINK_CHANGED 0x0001 -+ -+/** -+ * enum dpdmux_manip - DPDMUX manipulation operations -+ * @DPDMUX_MANIP_NONE: No manipulation on frames -+ * @DPDMUX_MANIP_ADD_REMOVE_S_VLAN: Add S-VLAN on egress, remove it on ingress -+ */ -+enum dpdmux_manip { -+ DPDMUX_MANIP_NONE = 0x0, -+ DPDMUX_MANIP_ADD_REMOVE_S_VLAN = 0x1 -+}; -+ -+/** -+ * enum dpdmux_method - DPDMUX method options -+ * @DPDMUX_METHOD_NONE: no DPDMUX method -+ * @DPDMUX_METHOD_C_VLAN_MAC: DPDMUX based on C-VLAN and MAC address -+ * @DPDMUX_METHOD_MAC: DPDMUX based on MAC address -+ * @DPDMUX_METHOD_C_VLAN: DPDMUX based on C-VLAN -+ * @DPDMUX_METHOD_S_VLAN: DPDMUX based on S-VLAN -+ */ -+enum dpdmux_method { -+ DPDMUX_METHOD_NONE = 0x0, -+ DPDMUX_METHOD_C_VLAN_MAC = 0x1, -+ DPDMUX_METHOD_MAC = 0x2, -+ DPDMUX_METHOD_C_VLAN = 0x3, -+ DPDMUX_METHOD_S_VLAN = 0x4 -+}; -+ -+/** -+ * struct dpdmux_cfg - DPDMUX configuration parameters -+ * @method: Defines the operation method for the DPDMUX address table -+ * @manip: Required manipulation operation -+ * @num_ifs: Number of interfaces (excluding the uplink interface) -+ * @adv: Advanced parameters; default is all zeros; -+ * use this structure to change default settings -+ */ -+struct dpdmux_cfg { -+ enum dpdmux_method method; -+ enum dpdmux_manip manip; -+ uint16_t num_ifs; -+ /** -+ * struct adv - Advanced parameters -+ * @options: DPDMUX options - combination of 'DPDMUX_OPT_' flags -+ * @max_dmat_entries: Maximum entries in DPDMUX address table -+ * 0 - indicates default: 64 entries per interface. -+ * @max_mc_groups: Number of multicast groups in DPDMUX table -+ * 0 - indicates default: 32 multicast groups -+ * @max_vlan_ids: max vlan ids allowed in the system - -+ * relevant only case of working in mac+vlan method. -+ * 0 - indicates default 16 vlan ids. -+ */ -+ struct { -+ uint64_t options; -+ uint16_t max_dmat_entries; -+ uint16_t max_mc_groups; -+ uint16_t max_vlan_ids; -+ } adv; -+}; -+ -+/** -+ * dpdmux_create() - Create the DPDMUX object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @cfg: Configuration structure -+ * @token: Returned token; use in subsequent API calls -+ * -+ * Create the DPDMUX object, allocate required resources and -+ * perform required initialization. -+ * -+ * The object can be created either by declaring it in the -+ * DPL file, or by calling this function. -+ * -+ * This function returns a unique authentication token, -+ * associated with the specific object ID and the specific MC -+ * portal; this token must be used in all subsequent calls to -+ * this specific object. For objects that are created using the -+ * DPL file, call dpdmux_open() function to get an authentication -+ * token first. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_create(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ const struct dpdmux_cfg *cfg, -+ uint16_t *token); -+ -+/** -+ * dpdmux_destroy() - Destroy the DPDMUX object and release all its resources. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpdmux_destroy(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpdmux_enable() - Enable DPDMUX functionality -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpdmux_disable() - Disable DPDMUX functionality -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpdmux_is_enabled() - Check if the DPDMUX is enabled. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @en: Returns '1' if object is enabled; '0' otherwise -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_is_enabled(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en); -+ -+/** -+ * dpdmux_reset() - Reset the DPDMUX, returns the object to initial state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_reset(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * struct dpdmux_irq_cfg - IRQ configuration -+ * @addr: Address that must be written to signal a message-based interrupt -+ * @val: Value to write into irq_addr address -+ * @irq_num: A user defined number associated with this IRQ -+ */ -+struct dpdmux_irq_cfg { -+ uint64_t addr; -+ uint32_t val; -+ int irq_num; -+}; -+ -+/** -+ * dpdmux_set_irq() - Set IRQ information for the DPDMUX to trigger an interrupt. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @irq_index: Identifies the interrupt index to configure -+ * @irq_cfg: IRQ configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_set_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ struct dpdmux_irq_cfg *irq_cfg); -+ -+/** -+ * dpdmux_get_irq() - Get IRQ information from the DPDMUX. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @irq_index: The interrupt index to configure -+ * @type: Interrupt type: 0 represents message interrupt -+ * type (both irq_addr and irq_val are valid) -+ * @irq_cfg: IRQ attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_get_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ int *type, -+ struct dpdmux_irq_cfg *irq_cfg); -+ -+/** -+ * dpdmux_set_irq_enable() - Set overall interrupt state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @irq_index: The interrupt index to configure -+ * @en: Interrupt state - enable = 1, disable = 0 -+ * -+ * Allows GPP software to control when interrupts are generated. -+ * Each interrupt can have up to 32 causes. The enable/disable control's the -+ * overall interrupt state. if the interrupt is disabled no causes will cause -+ * an interrupt. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_set_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t en); -+ -+/** -+ * dpdmux_get_irq_enable() - Get overall interrupt state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @irq_index: The interrupt index to configure -+ * @en: Returned interrupt state - enable = 1, disable = 0 -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_get_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t *en); -+ -+/** -+ * dpdmux_set_irq_mask() - Set interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @irq_index: The interrupt index to configure -+ * @mask: event mask to trigger interrupt; -+ * each bit: -+ * 0 = ignore event -+ * 1 = consider event for asserting IRQ -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_set_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t mask); -+ -+/** -+ * dpdmux_get_irq_mask() - Get interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @irq_index: The interrupt index to configure -+ * @mask: Returned event mask to trigger interrupt -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_get_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *mask); -+ -+/** -+ * dpdmux_get_irq_status() - Get the current status of any pending interrupts. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @irq_index: The interrupt index to configure -+ * @status: Returned interrupts status - one bit per cause: -+ * 0 = no interrupt pending -+ * 1 = interrupt pending -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_get_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *status); -+ -+/** -+ * dpdmux_clear_irq_status() - Clear a pending interrupt's status -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @irq_index: The interrupt index to configure -+ * @status: bits to clear (W1C) - one bit per cause: -+ * 0 = don't change -+ * 1 = clear status bit -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_clear_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t status); -+ -+/** -+ * struct dpdmux_attr - Structure representing DPDMUX attributes -+ * @id: DPDMUX object ID -+ * @version: DPDMUX version -+ * @options: Configuration options (bitmap) -+ * @method: DPDMUX address table method -+ * @manip: DPDMUX manipulation type -+ * @num_ifs: Number of interfaces (excluding the uplink interface) -+ * @mem_size: DPDMUX frame storage memory size -+ */ -+struct dpdmux_attr { -+ int id; -+ /** -+ * struct version - DPDMUX version -+ * @major: DPDMUX major version -+ * @minor: DPDMUX minor version -+ */ -+ struct { -+ uint16_t major; -+ uint16_t minor; -+ } version; -+ uint64_t options; -+ enum dpdmux_method method; -+ enum dpdmux_manip manip; -+ uint16_t num_ifs; -+ uint16_t mem_size; -+}; -+ -+/** -+ * dpdmux_get_attributes() - Retrieve DPDMUX attributes -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @attr: Returned object's attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpdmux_attr *attr); -+ -+/** -+ * dpdmux_ul_set_max_frame_length() - Set the maximum frame length in DPDMUX -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @max_frame_length: The required maximum frame length -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_ul_set_max_frame_length(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t max_frame_length); -+ -+/** -+ * enum dpdmux_counter_type - Counter types -+ * @DPDMUX_CNT_ING_FRAME: Counts ingress frames -+ * @DPDMUX_CNT_ING_BYTE: Counts ingress bytes -+ * @DPDMUX_CNT_ING_FLTR_FRAME: Counts filtered ingress frames -+ * @DPDMUX_CNT_ING_FRAME_DISCARD: Counts discarded ingress frames -+ * @DPDMUX_CNT_ING_MCAST_FRAME: Counts ingress multicast frames -+ * @DPDMUX_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes -+ * @DPDMUX_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames -+ * @DPDMUX_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes -+ * @DPDMUX_CNT_EGR_FRAME: Counts egress frames -+ * @DPDMUX_CNT_EGR_BYTE: Counts egress bytes -+ * @DPDMUX_CNT_EGR_FRAME_DISCARD: Counts discarded egress frames -+ */ -+enum dpdmux_counter_type { -+ DPDMUX_CNT_ING_FRAME = 0x0, -+ DPDMUX_CNT_ING_BYTE = 0x1, -+ DPDMUX_CNT_ING_FLTR_FRAME = 0x2, -+ DPDMUX_CNT_ING_FRAME_DISCARD = 0x3, -+ DPDMUX_CNT_ING_MCAST_FRAME = 0x4, -+ DPDMUX_CNT_ING_MCAST_BYTE = 0x5, -+ DPDMUX_CNT_ING_BCAST_FRAME = 0x6, -+ DPDMUX_CNT_ING_BCAST_BYTES = 0x7, -+ DPDMUX_CNT_EGR_FRAME = 0x8, -+ DPDMUX_CNT_EGR_BYTE = 0x9, -+ DPDMUX_CNT_EGR_FRAME_DISCARD = 0xa -+}; -+ -+/** -+ * enum dpdmux_accepted_frames_type - DPDMUX frame types -+ * @DPDMUX_ADMIT_ALL: The device accepts VLAN tagged, untagged and -+ * priority-tagged frames -+ * @DPDMUX_ADMIT_ONLY_VLAN_TAGGED: The device discards untagged frames or -+ * priority-tagged frames that are received on this -+ * interface -+ * @DPDMUX_ADMIT_ONLY_UNTAGGED: Untagged frames or priority-tagged frames -+ * received on this interface are accepted -+ */ -+enum dpdmux_accepted_frames_type { -+ DPDMUX_ADMIT_ALL = 0, -+ DPDMUX_ADMIT_ONLY_VLAN_TAGGED = 1, -+ DPDMUX_ADMIT_ONLY_UNTAGGED = 2 -+}; -+ -+/** -+ * enum dpdmux_action - DPDMUX action for un-accepted frames -+ * @DPDMUX_ACTION_DROP: Drop un-accepted frames -+ * @DPDMUX_ACTION_REDIRECT_TO_CTRL: Redirect un-accepted frames to the -+ * control interface -+ */ -+enum dpdmux_action { -+ DPDMUX_ACTION_DROP = 0, -+ DPDMUX_ACTION_REDIRECT_TO_CTRL = 1 -+}; -+ -+/** -+ * struct dpdmux_accepted_frames - Frame types configuration -+ * @type: Defines ingress accepted frames -+ * @unaccept_act: Defines action on frames not accepted -+ */ -+struct dpdmux_accepted_frames { -+ enum dpdmux_accepted_frames_type type; -+ enum dpdmux_action unaccept_act; -+}; -+ -+/** -+ * dpdmux_if_set_accepted_frames() - Set the accepted frame types -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @if_id: Interface ID (0 for uplink, or 1-num_ifs); -+ * @cfg: Frame types configuration -+ * -+ * if 'DPDMUX_ADMIT_ONLY_VLAN_TAGGED' is set - untagged frames or -+ * priority-tagged frames are discarded. -+ * if 'DPDMUX_ADMIT_ONLY_UNTAGGED' is set - untagged frames or -+ * priority-tagged frames are accepted. -+ * if 'DPDMUX_ADMIT_ALL' is set (default mode) - all VLAN tagged, -+ * untagged and priority-tagged frame are accepted; -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_if_set_accepted_frames(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpdmux_accepted_frames *cfg); -+ -+/** -+ * struct dpdmux_if_attr - Structure representing frame types configuration -+ * @rate: Configured interface rate (in bits per second) -+ * @enabled: Indicates if interface is enabled -+ * @accept_frame_type: Indicates type of accepted frames for the interface -+ */ -+struct dpdmux_if_attr { -+ uint32_t rate; -+ int enabled; -+ enum dpdmux_accepted_frames_type accept_frame_type; -+}; -+ -+/** -+ * dpdmux_if_get_attributes() - Obtain DPDMUX interface attributes -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @if_id: Interface ID (0 for uplink, or 1-num_ifs); -+ * @attr: Interface attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_if_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpdmux_if_attr *attr); -+ -+/** -+ * struct dpdmux_l2_rule - Structure representing L2 rule -+ * @mac_addr: MAC address -+ * @vlan_id: VLAN ID -+ */ -+struct dpdmux_l2_rule { -+ uint8_t mac_addr[6]; -+ uint16_t vlan_id; -+}; -+ -+/** -+ * dpdmux_if_remove_l2_rule() - Remove L2 rule from DPDMUX table -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @if_id: Destination interface ID -+ * @rule: L2 rule -+ * -+ * Function removes a L2 rule from DPDMUX table -+ * or adds an interface to an existing multicast address -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_if_remove_l2_rule(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpdmux_l2_rule *rule); -+ -+/** -+ * dpdmux_if_add_l2_rule() - Add L2 rule into DPDMUX table -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPDMUX object -+ * @if_id: Destination interface ID -+ * @rule: L2 rule -+ * -+ * Function adds a L2 rule into DPDMUX table -+ * or adds an interface to an existing multicast address -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_if_add_l2_rule(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpdmux_l2_rule *rule); -+ -+/** -+* dpdmux_if_get_counter() - Functions obtains specific counter of an interface -+* @mc_io: Pointer to MC portal's I/O object -+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+* @token: Token of DPDMUX object -+* @if_id: Interface Id -+* @counter_type: counter type -+* @counter: Returned specific counter information -+* -+* Return: '0' on Success; Error code otherwise. -+*/ -+int dpdmux_if_get_counter(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ enum dpdmux_counter_type counter_type, -+ uint64_t *counter); -+ -+/** -+* dpdmux_ul_reset_counters() - Function resets the uplink counter -+* @mc_io: Pointer to MC portal's I/O object -+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+* @token: Token of DPDMUX object -+* -+* Return: '0' on Success; Error code otherwise. -+*/ -+int dpdmux_ul_reset_counters(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * Enable auto-negotiation -+ */ -+#define DPDMUX_LINK_OPT_AUTONEG 0x0000000000000001ULL -+/** -+ * Enable half-duplex mode -+ */ -+#define DPDMUX_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL -+/** -+ * Enable pause frames -+ */ -+#define DPDMUX_LINK_OPT_PAUSE 0x0000000000000004ULL -+/** -+ * Enable a-symmetric pause frames -+ */ -+#define DPDMUX_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL -+ -+/** -+ * struct dpdmux_link_cfg - Structure representing DPDMUX link configuration -+ * @rate: Rate -+ * @options: Mask of available options; use 'DPDMUX_LINK_OPT_' values -+ */ -+struct dpdmux_link_cfg { -+ uint32_t rate; -+ uint64_t options; -+}; -+ -+/** -+ * dpdmux_if_set_link_cfg() - set the link configuration. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: interface id -+ * @cfg: Link configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpdmux_if_set_link_cfg(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpdmux_link_cfg *cfg); -+/** -+ * struct dpdmux_link_state - Structure representing DPDMUX link state -+ * @rate: Rate -+ * @options: Mask of available options; use 'DPDMUX_LINK_OPT_' values -+ * @up: 0 - down, 1 - up -+ */ -+struct dpdmux_link_state { -+ uint32_t rate; -+ uint64_t options; -+ int up; -+}; -+ -+/** -+ * dpdmux_if_get_link_state - Return the link state -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: interface id -+ * @state: link state -+ * -+ * @returns '0' on Success; Error code otherwise. -+ */ -+int dpdmux_if_get_link_state(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpdmux_link_state *state); -+ -+#endif /* __FSL_DPDMUX_H */ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/evb/evb.c -@@ -0,0 +1,1216 @@ -+/* Copyright 2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "../../fsl-mc/include/mc.h" -+ -+#include "dpdmux.h" -+#include "dpdmux-cmd.h" -+ -+/* IRQ index */ -+#define DPDMUX_MAX_IRQ_NUM 2 -+ -+/* MAX FRAME LENGTH (currently 10k) */ -+#define EVB_MAX_FRAME_LENGTH (10 * 1024) -+/* MIN FRAME LENGTH (64 bytes + 4 bytes CRC) */ -+#define EVB_MIN_FRAME_LENGTH 68 -+ -+struct evb_port_priv { -+ struct net_device *netdev; -+ struct list_head list; -+ u16 port_index; -+ struct evb_priv *evb_priv; -+ u8 vlans[VLAN_VID_MASK+1]; -+}; -+ -+struct evb_priv { -+ /* keep first */ -+ struct evb_port_priv uplink; -+ -+ struct fsl_mc_io *mc_io; -+ struct list_head port_list; -+ struct dpdmux_attr attr; -+ uint16_t mux_handle; -+ int dev_id; -+}; -+ -+static int _evb_port_carrier_state_sync(struct net_device *netdev) -+{ -+ struct evb_port_priv *port_priv = netdev_priv(netdev); -+ struct dpdmux_link_state state; -+ int err; -+ -+ err = dpdmux_if_get_link_state(port_priv->evb_priv->mc_io, 0, -+ port_priv->evb_priv->mux_handle, -+ port_priv->port_index, &state); -+ if (unlikely(err)) { -+ netdev_err(netdev, "dpdmux_if_get_link_state() err %d\n", err); -+ return err; -+ } -+ -+ WARN_ONCE(state.up > 1, "Garbage read into link_state"); -+ -+ if (state.up) -+ netif_carrier_on(port_priv->netdev); -+ else -+ netif_carrier_off(port_priv->netdev); -+ -+ return 0; -+} -+ -+static int evb_port_open(struct net_device *netdev) -+{ -+ int err; -+ -+ /* FIXME: enable port when support added */ -+ -+ err = _evb_port_carrier_state_sync(netdev); -+ if (err) { -+ netdev_err(netdev, "ethsw_port_carrier_state_sync err %d\n", -+ err); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static netdev_tx_t evb_dropframe(struct sk_buff *skb, struct net_device *dev) -+{ -+ /* we don't support I/O for now, drop the frame */ -+ dev_kfree_skb_any(skb); -+ return NETDEV_TX_OK; -+} -+ -+static int evb_links_state_update(struct evb_priv *priv) -+{ -+ struct evb_port_priv *port_priv; -+ struct list_head *pos; -+ int err; -+ -+ list_for_each(pos, &priv->port_list) { -+ port_priv = list_entry(pos, struct evb_port_priv, list); -+ -+ err = _evb_port_carrier_state_sync(port_priv->netdev); -+ if (err) -+ netdev_err(port_priv->netdev, -+ "_evb_port_carrier_state_sync err %d\n", -+ err); -+ } -+ -+ return 0; -+} -+ -+static irqreturn_t evb_irq0_handler(int irq_num, void *arg) -+{ -+ return IRQ_WAKE_THREAD; -+} -+ -+static irqreturn_t _evb_irq0_handler_thread(int irq_num, void *arg) -+{ -+ struct device *dev = (struct device *)arg; -+ struct fsl_mc_device *evb_dev = to_fsl_mc_device(dev); -+ struct net_device *netdev = dev_get_drvdata(dev); -+ struct evb_priv *priv = netdev_priv(netdev); -+ struct fsl_mc_io *io = priv->mc_io; -+ uint16_t token = priv->mux_handle; -+ int irq_index = DPDMUX_IRQ_INDEX_IF; -+ uint32_t status = 0, clear = 0; -+ int err; -+ -+ /* Sanity check */ -+ if (WARN_ON(!evb_dev || !evb_dev->irqs || !evb_dev->irqs[irq_index])) -+ goto out; -+ if (WARN_ON(evb_dev->irqs[irq_index]->msi_desc->irq != irq_num)) -+ goto out; -+ -+ err = dpdmux_get_irq_status(io, 0, token, irq_index, &status); -+ if (unlikely(err)) { -+ netdev_err(netdev, "Can't get irq status (err %d)", err); -+ clear = 0xffffffff; -+ goto out; -+ } -+ -+ /* FIXME clear irq status */ -+ -+ if (status & DPDMUX_IRQ_EVENT_LINK_CHANGED) { -+ clear |= DPDMUX_IRQ_EVENT_LINK_CHANGED; -+ -+ err = evb_links_state_update(priv); -+ if (unlikely(err)) -+ goto out; -+ } -+out: -+ err = dpdmux_clear_irq_status(io, 0, token, irq_index, clear); -+ if (unlikely(err)) -+ netdev_err(netdev, "Can't clear irq status (err %d)", err); -+ return IRQ_HANDLED; -+} -+ -+static int evb_setup_irqs(struct fsl_mc_device *evb_dev) -+{ -+ struct device *dev = &evb_dev->dev; -+ struct net_device *netdev = dev_get_drvdata(dev); -+ struct evb_priv *priv = netdev_priv(netdev); -+ int err = 0; -+ struct fsl_mc_device_irq *irq; -+ const int irq_index = DPDMUX_IRQ_INDEX_IF; -+ uint32_t mask = ~0x0u; /* FIXME: unmask handled irqs */ -+ -+ err = fsl_mc_allocate_irqs(evb_dev); -+ if (unlikely(err)) { -+ dev_err(dev, "MC irqs allocation failed\n"); -+ return err; -+ } -+ -+ if (WARN_ON(evb_dev->obj_desc.irq_count != DPDMUX_MAX_IRQ_NUM)) { -+ err = -EINVAL; -+ goto free_irq; -+ } -+ -+ err = dpdmux_set_irq_enable(priv->mc_io, 0, priv->mux_handle, -+ irq_index, 0); -+ if (unlikely(err)) { -+ dev_err(dev, "dpdmux_set_irq_enable err %d\n", err); -+ goto free_irq; -+ } -+ -+ irq = evb_dev->irqs[irq_index]; -+ -+ err = devm_request_threaded_irq(dev, irq->msi_desc->irq, -+ evb_irq0_handler, -+ _evb_irq0_handler_thread, -+ IRQF_NO_SUSPEND | IRQF_ONESHOT, -+ dev_name(dev), dev); -+ if (unlikely(err)) { -+ dev_err(dev, "devm_request_threaded_irq(): %d", err); -+ goto free_irq; -+ } -+ -+ err = dpdmux_set_irq_mask(priv->mc_io, 0, priv->mux_handle, -+ irq_index, mask); -+ if (unlikely(err)) { -+ dev_err(dev, "dpdmux_set_irq_mask(): %d", err); -+ goto free_devm_irq; -+ } -+ -+ err = dpdmux_set_irq_enable(priv->mc_io, 0, priv->mux_handle, -+ irq_index, 1); -+ if (unlikely(err)) { -+ dev_err(dev, "dpdmux_set_irq_enable(): %d", err); -+ goto free_devm_irq; -+ } -+ -+ return 0; -+ -+free_devm_irq: -+ devm_free_irq(dev, irq->msi_desc->irq, dev); -+free_irq: -+ fsl_mc_free_irqs(evb_dev); -+ return err; -+} -+ -+static void evb_teardown_irqs(struct fsl_mc_device *evb_dev) -+{ -+ struct device *dev = &evb_dev->dev; -+ struct net_device *netdev = dev_get_drvdata(dev); -+ struct evb_priv *priv = netdev_priv(netdev); -+ -+ dpdmux_set_irq_enable(priv->mc_io, 0, priv->mux_handle, -+ DPDMUX_IRQ_INDEX_IF, 0); -+ -+ devm_free_irq(dev, -+ evb_dev->irqs[DPDMUX_IRQ_INDEX_IF]->msi_desc->irq, -+ dev); -+ fsl_mc_free_irqs(evb_dev); -+} -+ -+static int evb_port_add_rule(struct net_device *netdev, -+ const unsigned char *addr, u16 vid) -+{ -+ struct evb_port_priv *port_priv = netdev_priv(netdev); -+ struct dpdmux_l2_rule rule = { .vlan_id = vid }; -+ int err; -+ -+ if (addr) -+ ether_addr_copy(rule.mac_addr, addr); -+ -+ err = dpdmux_if_add_l2_rule(port_priv->evb_priv->mc_io, -+ 0, -+ port_priv->evb_priv->mux_handle, -+ port_priv->port_index, &rule); -+ if (unlikely(err)) -+ netdev_err(netdev, "dpdmux_if_add_l2_rule err %d\n", err); -+ return err; -+} -+ -+static int evb_port_del_rule(struct net_device *netdev, -+ const unsigned char *addr, u16 vid) -+{ -+ struct evb_port_priv *port_priv = netdev_priv(netdev); -+ struct dpdmux_l2_rule rule = { .vlan_id = vid }; -+ int err; -+ -+ if (addr) -+ ether_addr_copy(rule.mac_addr, addr); -+ -+ err = dpdmux_if_remove_l2_rule(port_priv->evb_priv->mc_io, -+ 0, -+ port_priv->evb_priv->mux_handle, -+ port_priv->port_index, &rule); -+ if (unlikely(err)) -+ netdev_err(netdev, "dpdmux_if_remove_l2_rule err %d\n", err); -+ return err; -+} -+ -+static bool _lookup_address(struct net_device *netdev, -+ const unsigned char *addr) -+{ -+ struct netdev_hw_addr *ha; -+ struct netdev_hw_addr_list *list = (is_unicast_ether_addr(addr)) ? -+ &netdev->uc : &netdev->mc; -+ -+ netif_addr_lock_bh(netdev); -+ list_for_each_entry(ha, &list->list, list) { -+ if (ether_addr_equal(ha->addr, addr)) { -+ netif_addr_unlock_bh(netdev); -+ return true; -+ } -+ } -+ netif_addr_unlock_bh(netdev); -+ return false; -+} -+ -+static inline int evb_port_fdb_prep(struct nlattr *tb[], -+ struct net_device *netdev, -+ const unsigned char *addr, u16 *vid, -+ bool del) -+{ -+ struct evb_port_priv *port_priv = netdev_priv(netdev); -+ struct evb_priv *evb_priv = port_priv->evb_priv; -+ -+ *vid = 0; -+ -+ if (evb_priv->attr.method != DPDMUX_METHOD_MAC && -+ evb_priv->attr.method != DPDMUX_METHOD_C_VLAN_MAC) { -+ netdev_err(netdev, -+ "EVB mode does not support MAC classification\n"); -+ return -EOPNOTSUPP; -+ } -+ -+ /* check if the address is configured on this port */ -+ if (_lookup_address(netdev, addr)) { -+ if (!del) -+ return -EEXIST; -+ } else { -+ if (del) -+ return -ENOENT; -+ } -+ -+ if (tb[NDA_VLAN] && evb_priv->attr.method == DPDMUX_METHOD_C_VLAN_MAC) { -+ if (nla_len(tb[NDA_VLAN]) != sizeof(unsigned short)) { -+ netdev_err(netdev, "invalid vlan size %d\n", -+ nla_len(tb[NDA_VLAN])); -+ return -EINVAL; -+ } -+ -+ *vid = nla_get_u16(tb[NDA_VLAN]); -+ -+ if (!*vid || *vid >= VLAN_VID_MASK) { -+ netdev_err(netdev, "invalid vid value 0x%04x\n", *vid); -+ return -EINVAL; -+ } -+ } else if (evb_priv->attr.method == DPDMUX_METHOD_C_VLAN_MAC) { -+ netdev_err(netdev, -+ "EVB mode requires explicit VLAN configuration\n"); -+ return -EINVAL; -+ } else if (tb[NDA_VLAN]) { -+ netdev_warn(netdev, "VLAN not supported, argument ignored\n"); -+ } -+ -+ return 0; -+} -+ -+static int evb_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], -+ struct net_device *netdev, -+ const unsigned char *addr, u16 vid, u16 flags) -+{ -+ u16 _vid; -+ int err; -+ -+ /* TODO: add replace support when added to iproute bridge */ -+ if (!(flags & NLM_F_REQUEST)) { -+ netdev_err(netdev, -+ "evb_port_fdb_add unexpected flags value %08x\n", -+ flags); -+ return -EINVAL; -+ } -+ -+ err = evb_port_fdb_prep(tb, netdev, addr, &_vid, 0); -+ if (unlikely(err)) -+ return err; -+ -+ -+ err = evb_port_add_rule(netdev, addr, _vid); -+ if (unlikely(err)) -+ return err; -+ -+ if (is_unicast_ether_addr(addr)) { -+ err = dev_uc_add(netdev, addr); -+ if (unlikely(err)) { -+ netdev_err(netdev, "dev_uc_add err %d\n", err); -+ return err; -+ } -+ } else { -+ err = dev_mc_add(netdev, addr); -+ if (unlikely(err)) { -+ netdev_err(netdev, "dev_mc_add err %d\n", err); -+ return err; -+ } -+ } -+ -+ return 0; -+} -+ -+static int evb_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], -+ struct net_device *netdev, -+ const unsigned char *addr, u16 vid) -+{ -+ u16 _vid; -+ int err; -+ -+ err = evb_port_fdb_prep(tb, netdev, addr, &_vid, 1); -+ if (unlikely(err)) -+ return err; -+ -+ err = evb_port_del_rule(netdev, addr, _vid); -+ if (unlikely(err)) -+ return err; -+ -+ if (is_unicast_ether_addr(addr)) { -+ err = dev_uc_del(netdev, addr); -+ if (unlikely(err)) { -+ netdev_err(netdev, "dev_uc_del err %d\n", err); -+ return err; -+ } -+ } else { -+ err = dev_mc_del(netdev, addr); -+ if (unlikely(err)) { -+ netdev_err(netdev, "dev_mc_del err %d\n", err); -+ return err; -+ } -+ } -+ -+ return 0; -+} -+ -+static int evb_change_mtu(struct net_device *netdev, -+ int mtu) -+{ -+ struct evb_port_priv *port_priv = netdev_priv(netdev); -+ struct evb_priv *evb_priv = port_priv->evb_priv; -+ struct list_head *pos; -+ int err = 0; -+ -+ /* This operation is not permitted on downlinks */ -+ if (port_priv->port_index > 0) -+ return -EPERM; -+ -+ if (mtu < EVB_MIN_FRAME_LENGTH || mtu > EVB_MAX_FRAME_LENGTH) { -+ netdev_err(netdev, "Invalid MTU %d. Valid range is: %d..%d\n", -+ mtu, EVB_MIN_FRAME_LENGTH, EVB_MAX_FRAME_LENGTH); -+ return -EINVAL; -+ } -+ -+ err = dpdmux_ul_set_max_frame_length(evb_priv->mc_io, -+ 0, -+ evb_priv->mux_handle, -+ (uint16_t)mtu); -+ -+ if (unlikely(err)) { -+ netdev_err(netdev, "dpdmux_ul_set_max_frame_length err %d\n", -+ err); -+ return err; -+ } -+ -+ /* Update the max frame length for downlinks */ -+ list_for_each(pos, &evb_priv->port_list) { -+ port_priv = list_entry(pos, struct evb_port_priv, list); -+ port_priv->netdev->mtu = mtu; -+ } -+ -+ netdev->mtu = mtu; -+ return 0; -+} -+ -+static const struct nla_policy ifla_br_policy[IFLA_MAX+1] = { -+ [IFLA_BRIDGE_FLAGS] = { .type = NLA_U16 }, -+ [IFLA_BRIDGE_MODE] = { .type = NLA_U16 }, -+ [IFLA_BRIDGE_VLAN_INFO] = { .type = NLA_BINARY, -+ .len = sizeof(struct bridge_vlan_info), }, -+}; -+ -+static int evb_setlink_af_spec(struct net_device *netdev, -+ struct nlattr **tb) -+{ -+ struct bridge_vlan_info *vinfo; -+ struct evb_port_priv *port_priv = netdev_priv(netdev); -+ int err = 0; -+ -+ if (!tb[IFLA_BRIDGE_VLAN_INFO]) { -+ netdev_err(netdev, "no VLAN INFO in nlmsg\n"); -+ return -EOPNOTSUPP; -+ } -+ -+ vinfo = nla_data(tb[IFLA_BRIDGE_VLAN_INFO]); -+ -+ if (!vinfo->vid || vinfo->vid > VLAN_VID_MASK) -+ return -EINVAL; -+ -+ err = evb_port_add_rule(netdev, NULL, vinfo->vid); -+ if (unlikely(err)) -+ return err; -+ -+ port_priv->vlans[vinfo->vid] = 1; -+ -+ return 0; -+} -+ -+static int evb_setlink(struct net_device *netdev, -+ struct nlmsghdr *nlh, -+ u16 flags) -+{ -+ struct evb_port_priv *port_priv = netdev_priv(netdev); -+ struct evb_priv *evb_priv = port_priv->evb_priv; -+ struct nlattr *attr; -+ struct nlattr *tb[(IFLA_BRIDGE_MAX > IFLA_BRPORT_MAX) ? -+ IFLA_BRIDGE_MAX : IFLA_BRPORT_MAX+1]; -+ int err = 0; -+ -+ if (evb_priv->attr.method != DPDMUX_METHOD_C_VLAN && -+ evb_priv->attr.method != DPDMUX_METHOD_S_VLAN) { -+ netdev_err(netdev, -+ "EVB mode does not support VLAN only classification\n"); -+ return -EOPNOTSUPP; -+ } -+ -+ attr = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); -+ if (attr) { -+ err = nla_parse_nested(tb, IFLA_BRIDGE_MAX, attr, -+ ifla_br_policy); -+ if (unlikely(err)) { -+ netdev_err(netdev, -+ "nla_parse_nested for br_policy err %d\n", -+ err); -+ return err; -+ } -+ -+ err = evb_setlink_af_spec(netdev, tb); -+ return err; -+ } -+ -+ netdev_err(netdev, "nlmsg_find_attr found no AF_SPEC\n"); -+ return -EOPNOTSUPP; -+} -+ -+static int __nla_put_netdev(struct sk_buff *skb, struct net_device *netdev) -+{ -+ struct evb_port_priv *port_priv = netdev_priv(netdev); -+ struct evb_priv *evb_priv = port_priv->evb_priv; -+ u8 operstate = netif_running(netdev) ? -+ netdev->operstate : IF_OPER_DOWN; -+ int iflink; -+ int err; -+ -+ err = nla_put_string(skb, IFLA_IFNAME, netdev->name); -+ if (unlikely(err)) -+ goto nla_put_err; -+ err = nla_put_u32(skb, IFLA_MASTER, evb_priv->uplink.netdev->ifindex); -+ if (unlikely(err)) -+ goto nla_put_err; -+ err = nla_put_u32(skb, IFLA_MTU, netdev->mtu); -+ if (unlikely(err)) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_OPERSTATE, operstate); -+ if (unlikely(err)) -+ goto nla_put_err; -+ if (netdev->addr_len) { -+ err = nla_put(skb, IFLA_ADDRESS, netdev->addr_len, -+ netdev->dev_addr); -+ if (unlikely(err)) -+ goto nla_put_err; -+ } -+ -+ iflink = dev_get_iflink(netdev); -+ if (netdev->ifindex != iflink) { -+ err = nla_put_u32(skb, IFLA_LINK, iflink); -+ if (unlikely(err)) -+ goto nla_put_err; -+ } -+ -+ return 0; -+ -+nla_put_err: -+ netdev_err(netdev, "nla_put_ err %d\n", err); -+ return err; -+} -+ -+static int __nla_put_port(struct sk_buff *skb, struct net_device *netdev) -+{ -+ struct nlattr *nest; -+ int err; -+ -+ nest = nla_nest_start(skb, IFLA_PROTINFO | NLA_F_NESTED); -+ if (!nest) { -+ netdev_err(netdev, "nla_nest_start failed\n"); -+ return -ENOMEM; -+ } -+ -+ err = nla_put_u8(skb, IFLA_BRPORT_STATE, BR_STATE_FORWARDING); -+ if (unlikely(err)) -+ goto nla_put_err; -+ err = nla_put_u16(skb, IFLA_BRPORT_PRIORITY, 0); -+ if (unlikely(err)) -+ goto nla_put_err; -+ err = nla_put_u32(skb, IFLA_BRPORT_COST, 0); -+ if (unlikely(err)) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_BRPORT_MODE, 0); -+ if (unlikely(err)) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_BRPORT_GUARD, 0); -+ if (unlikely(err)) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_BRPORT_PROTECT, 0); -+ if (unlikely(err)) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_BRPORT_FAST_LEAVE, 0); -+ if (unlikely(err)) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_BRPORT_LEARNING, 0); -+ if (unlikely(err)) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_BRPORT_UNICAST_FLOOD, 1); -+ if (unlikely(err)) -+ goto nla_put_err; -+ nla_nest_end(skb, nest); -+ -+ return 0; -+ -+nla_put_err: -+ netdev_err(netdev, "nla_put_ err %d\n", err); -+ nla_nest_cancel(skb, nest); -+ return err; -+} -+ -+static int __nla_put_vlan(struct sk_buff *skb, struct net_device *netdev) -+{ -+ struct evb_port_priv *port_priv = netdev_priv(netdev); -+ struct nlattr *nest; -+ struct bridge_vlan_info vinfo; -+ const u8 *vlans = port_priv->vlans; -+ u16 i; -+ int err; -+ -+ nest = nla_nest_start(skb, IFLA_AF_SPEC); -+ if (!nest) { -+ netdev_err(netdev, "nla_nest_start failed"); -+ return -ENOMEM; -+ } -+ -+ for (i = 0; i < VLAN_VID_MASK+1; i++) { -+ if (!vlans[i]) -+ continue; -+ -+ vinfo.flags = 0; -+ vinfo.vid = i; -+ -+ err = nla_put(skb, IFLA_BRIDGE_VLAN_INFO, -+ sizeof(vinfo), &vinfo); -+ if (unlikely(err)) -+ goto nla_put_err; -+ } -+ -+ nla_nest_end(skb, nest); -+ -+ return 0; -+ -+nla_put_err: -+ netdev_err(netdev, "nla_put_ err %d\n", err); -+ nla_nest_cancel(skb, nest); -+ return err; -+} -+ -+static int evb_getlink(struct sk_buff *skb, u32 pid, u32 seq, -+ struct net_device *netdev, u32 filter_mask, int nlflags) -+{ -+ struct evb_port_priv *port_priv = netdev_priv(netdev); -+ struct evb_priv *evb_priv = port_priv->evb_priv; -+ struct ifinfomsg *hdr; -+ struct nlmsghdr *nlh; -+ int err; -+ -+ if (evb_priv->attr.method != DPDMUX_METHOD_C_VLAN && -+ evb_priv->attr.method != DPDMUX_METHOD_S_VLAN) { -+ return 0; -+ } -+ -+ nlh = nlmsg_put(skb, pid, seq, RTM_NEWLINK, sizeof(*hdr), NLM_F_MULTI); -+ if (!nlh) -+ return -EMSGSIZE; -+ -+ hdr = nlmsg_data(nlh); -+ memset(hdr, 0, sizeof(*hdr)); -+ hdr->ifi_family = AF_BRIDGE; -+ hdr->ifi_type = netdev->type; -+ hdr->ifi_index = netdev->ifindex; -+ hdr->ifi_flags = dev_get_flags(netdev); -+ -+ err = __nla_put_netdev(skb, netdev); -+ if (unlikely(err)) -+ goto nla_put_err; -+ -+ err = __nla_put_port(skb, netdev); -+ if (unlikely(err)) -+ goto nla_put_err; -+ -+ /* Check if the VID information is requested */ -+ if (filter_mask & RTEXT_FILTER_BRVLAN) { -+ err = __nla_put_vlan(skb, netdev); -+ if (unlikely(err)) -+ goto nla_put_err; -+ } -+ -+ nlmsg_end(skb, nlh); -+ return skb->len; -+ -+nla_put_err: -+ nlmsg_cancel(skb, nlh); -+ return -EMSGSIZE; -+} -+ -+static int evb_dellink(struct net_device *netdev, -+ struct nlmsghdr *nlh, -+ u16 flags) -+{ -+ struct nlattr *tb[IFLA_BRIDGE_MAX+1]; -+ struct nlattr *spec; -+ struct bridge_vlan_info *vinfo; -+ struct evb_port_priv *port_priv = netdev_priv(netdev); -+ int err = 0; -+ -+ spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); -+ if (!spec) -+ return 0; -+ -+ err = nla_parse_nested(tb, IFLA_BRIDGE_MAX, spec, ifla_br_policy); -+ if (unlikely(err)) -+ return err; -+ -+ if (!tb[IFLA_BRIDGE_VLAN_INFO]) -+ return -EOPNOTSUPP; -+ -+ vinfo = nla_data(tb[IFLA_BRIDGE_VLAN_INFO]); -+ -+ if (!vinfo->vid || vinfo->vid > VLAN_VID_MASK) -+ return -EINVAL; -+ -+ err = evb_port_del_rule(netdev, NULL, vinfo->vid); -+ if (unlikely(err)) { -+ netdev_err(netdev, "evb_port_del_rule err %d\n", err); -+ return err; -+ } -+ port_priv->vlans[vinfo->vid] = 0; -+ -+ return 0; -+} -+ -+static struct rtnl_link_stats64 * -+evb_port_get_stats(struct net_device *netdev, -+ struct rtnl_link_stats64 *storage) -+{ -+ struct evb_port_priv *port_priv = netdev_priv(netdev); -+ u64 tmp; -+ int err; -+ -+ err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io, -+ 0, -+ port_priv->evb_priv->mux_handle, -+ port_priv->port_index, -+ DPDMUX_CNT_ING_FRAME, &storage->rx_packets); -+ if (unlikely(err)) -+ goto error; -+ -+ err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io, -+ 0, -+ port_priv->evb_priv->mux_handle, -+ port_priv->port_index, -+ DPDMUX_CNT_ING_BYTE, &storage->rx_bytes); -+ if (unlikely(err)) -+ goto error; -+ -+ err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io, -+ 0, -+ port_priv->evb_priv->mux_handle, -+ port_priv->port_index, -+ DPDMUX_CNT_ING_FLTR_FRAME, &tmp); -+ if (unlikely(err)) -+ goto error; -+ -+ err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io, -+ 0, -+ port_priv->evb_priv->mux_handle, -+ port_priv->port_index, -+ DPDMUX_CNT_ING_FRAME_DISCARD, -+ &storage->rx_dropped); -+ if (unlikely(err)) { -+ storage->rx_dropped = tmp; -+ goto error; -+ } -+ storage->rx_dropped += tmp; -+ -+ err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io, -+ 0, -+ port_priv->evb_priv->mux_handle, -+ port_priv->port_index, -+ DPDMUX_CNT_ING_MCAST_FRAME, -+ &storage->multicast); -+ if (unlikely(err)) -+ goto error; -+ -+ err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io, -+ 0, -+ port_priv->evb_priv->mux_handle, -+ port_priv->port_index, -+ DPDMUX_CNT_EGR_FRAME, &storage->tx_packets); -+ if (unlikely(err)) -+ goto error; -+ -+ err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io, -+ 0, -+ port_priv->evb_priv->mux_handle, -+ port_priv->port_index, -+ DPDMUX_CNT_EGR_BYTE, &storage->tx_bytes); -+ if (unlikely(err)) -+ goto error; -+ -+ err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io, -+ 0, -+ port_priv->evb_priv->mux_handle, -+ port_priv->port_index, -+ DPDMUX_CNT_EGR_FRAME_DISCARD, -+ &storage->tx_dropped); -+ if (unlikely(err)) -+ goto error; -+ -+ return storage; -+ -+error: -+ netdev_err(netdev, "dpdmux_if_get_counter err %d\n", err); -+ return storage; -+} -+ -+static const struct net_device_ops evb_port_ops = { -+ .ndo_open = &evb_port_open, -+ -+ .ndo_start_xmit = &evb_dropframe, -+ -+ .ndo_fdb_add = &evb_port_fdb_add, -+ .ndo_fdb_del = &evb_port_fdb_del, -+ -+ .ndo_get_stats64 = &evb_port_get_stats, -+ .ndo_change_mtu = &evb_change_mtu, -+}; -+ -+static struct { -+ enum dpdmux_counter_type id; -+ char name[ETH_GSTRING_LEN]; -+} evb_ethtool_counters[] = { -+ {DPDMUX_CNT_ING_FRAME, "rx frames"}, -+ {DPDMUX_CNT_ING_BYTE, "rx bytes"}, -+ {DPDMUX_CNT_ING_FLTR_FRAME, "rx filtered frames"}, -+ {DPDMUX_CNT_ING_FRAME_DISCARD, "rx discarded frames"}, -+ {DPDMUX_CNT_ING_BCAST_FRAME, "rx b-cast frames"}, -+ {DPDMUX_CNT_ING_BCAST_BYTES, "rx b-cast bytes"}, -+ {DPDMUX_CNT_ING_MCAST_FRAME, "rx m-cast frames"}, -+ {DPDMUX_CNT_ING_MCAST_BYTE, "rx m-cast bytes"}, -+ {DPDMUX_CNT_EGR_FRAME, "tx frames"}, -+ {DPDMUX_CNT_EGR_BYTE, "tx bytes"}, -+ {DPDMUX_CNT_EGR_FRAME_DISCARD, "tx discarded frames"}, -+}; -+ -+static int evb_ethtool_get_sset_count(struct net_device *dev, int sset) -+{ -+ switch (sset) { -+ case ETH_SS_STATS: -+ return ARRAY_SIZE(evb_ethtool_counters); -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+static void evb_ethtool_get_strings(struct net_device *netdev, -+ u32 stringset, u8 *data) -+{ -+ int i; -+ -+ switch (stringset) { -+ case ETH_SS_STATS: -+ for (i = 0; i < ARRAY_SIZE(evb_ethtool_counters); i++) -+ memcpy(data + i * ETH_GSTRING_LEN, -+ evb_ethtool_counters[i].name, ETH_GSTRING_LEN); -+ break; -+ } -+} -+ -+static void evb_ethtool_get_stats(struct net_device *netdev, -+ struct ethtool_stats *stats, -+ u64 *data) -+{ -+ struct evb_port_priv *port_priv = netdev_priv(netdev); -+ int i; -+ int err; -+ -+ for (i = 0; i < ARRAY_SIZE(evb_ethtool_counters); i++) { -+ err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io, -+ 0, -+ port_priv->evb_priv->mux_handle, -+ port_priv->port_index, -+ evb_ethtool_counters[i].id, -+ &data[i]); -+ if (err) -+ netdev_err(netdev, "dpdmux_if_get_counter[%s] err %d\n", -+ evb_ethtool_counters[i].name, err); -+ } -+} -+ -+static const struct ethtool_ops evb_port_ethtool_ops = { -+ .get_strings = &evb_ethtool_get_strings, -+ .get_ethtool_stats = &evb_ethtool_get_stats, -+ .get_sset_count = &evb_ethtool_get_sset_count, -+}; -+ -+static int evb_open(struct net_device *netdev) -+{ -+ struct evb_priv *priv = netdev_priv(netdev); -+ int err = 0; -+ -+ err = dpdmux_enable(priv->mc_io, 0, priv->mux_handle); -+ if (unlikely(err)) -+ netdev_err(netdev, "dpdmux_enable err %d\n", err); -+ -+ return err; -+} -+ -+static int evb_close(struct net_device *netdev) -+{ -+ struct evb_priv *priv = netdev_priv(netdev); -+ int err = 0; -+ -+ err = dpdmux_disable(priv->mc_io, 0, priv->mux_handle); -+ if (unlikely(err)) -+ netdev_err(netdev, "dpdmux_disable err %d\n", err); -+ -+ return err; -+} -+ -+static const struct net_device_ops evb_ops = { -+ .ndo_start_xmit = &evb_dropframe, -+ .ndo_open = &evb_open, -+ .ndo_stop = &evb_close, -+ -+ .ndo_bridge_setlink = &evb_setlink, -+ .ndo_bridge_getlink = &evb_getlink, -+ .ndo_bridge_dellink = &evb_dellink, -+ -+ .ndo_get_stats64 = &evb_port_get_stats, -+ .ndo_change_mtu = &evb_change_mtu, -+}; -+ -+static int evb_takedown(struct fsl_mc_device *evb_dev) -+{ -+ struct device *dev = &evb_dev->dev; -+ struct net_device *netdev = dev_get_drvdata(dev); -+ struct evb_priv *priv = netdev_priv(netdev); -+ int err; -+ -+ err = dpdmux_close(priv->mc_io, 0, priv->mux_handle); -+ if (unlikely(err)) -+ dev_warn(dev, "dpdmux_close err %d\n", err); -+ -+ return 0; -+} -+ -+static int evb_init(struct fsl_mc_device *evb_dev) -+{ -+ struct device *dev = &evb_dev->dev; -+ struct net_device *netdev = dev_get_drvdata(dev); -+ struct evb_priv *priv = netdev_priv(netdev); -+ int err = 0; -+ -+ priv->dev_id = evb_dev->obj_desc.id; -+ -+ err = dpdmux_open(priv->mc_io, 0, priv->dev_id, &priv->mux_handle); -+ if (unlikely(err)) { -+ dev_err(dev, "dpdmux_open err %d\n", err); -+ goto err_exit; -+ } -+ if (!priv->mux_handle) { -+ dev_err(dev, "dpdmux_open returned null handle but no error\n"); -+ err = -EFAULT; -+ goto err_exit; -+ } -+ -+ err = dpdmux_get_attributes(priv->mc_io, 0, priv->mux_handle, -+ &priv->attr); -+ if (unlikely(err)) { -+ dev_err(dev, "dpdmux_get_attributes err %d\n", err); -+ goto err_close; -+ } -+ -+ err = dpdmux_reset(priv->mc_io, 0, priv->mux_handle); -+ if (unlikely(err)) { -+ dev_err(dev, "dpdmux_reset err %d\n", err); -+ goto err_close; -+ } -+ -+ return 0; -+ -+err_close: -+ dpdmux_close(priv->mc_io, 0, priv->mux_handle); -+err_exit: -+ return err; -+} -+ -+static int evb_remove(struct fsl_mc_device *evb_dev) -+{ -+ struct device *dev = &evb_dev->dev; -+ struct net_device *netdev = dev_get_drvdata(dev); -+ struct evb_priv *priv = netdev_priv(netdev); -+ struct evb_port_priv *port_priv; -+ struct list_head *pos; -+ -+ list_for_each(pos, &priv->port_list) { -+ port_priv = list_entry(pos, struct evb_port_priv, list); -+ -+ rtnl_lock(); -+ netdev_upper_dev_unlink(port_priv->netdev, netdev); -+ rtnl_unlock(); -+ -+ unregister_netdev(port_priv->netdev); -+ free_netdev(port_priv->netdev); -+ } -+ -+ evb_teardown_irqs(evb_dev); -+ -+ unregister_netdev(netdev); -+ -+ evb_takedown(evb_dev); -+ fsl_mc_portal_free(priv->mc_io); -+ -+ dev_set_drvdata(dev, NULL); -+ free_netdev(netdev); -+ -+ return 0; -+} -+ -+static int evb_probe(struct fsl_mc_device *evb_dev) -+{ -+ struct device *dev; -+ struct evb_priv *priv = NULL; -+ struct net_device *netdev = NULL; -+ char port_name[IFNAMSIZ]; -+ int i; -+ int err = 0; -+ -+ dev = &evb_dev->dev; -+ -+ /* register switch device, it's for management only - no I/O */ -+ netdev = alloc_etherdev(sizeof(*priv)); -+ if (!netdev) { -+ dev_err(dev, "alloc_etherdev error\n"); -+ return -ENOMEM; -+ } -+ netdev->netdev_ops = &evb_ops; -+ -+ dev_set_drvdata(dev, netdev); -+ -+ priv = netdev_priv(netdev); -+ -+ err = fsl_mc_portal_allocate(evb_dev, 0, &priv->mc_io); -+ if (unlikely(err)) { -+ dev_err(dev, "fsl_mc_portal_allocate err %d\n", err); -+ goto err_free_netdev; -+ } -+ if (!priv->mc_io) { -+ dev_err(dev, "fsl_mc_portal_allocate returned null handle but no error\n"); -+ err = -EFAULT; -+ goto err_free_netdev; -+ } -+ -+ err = evb_init(evb_dev); -+ if (unlikely(err)) { -+ dev_err(dev, "evb init err %d\n", err); -+ goto err_free_cmdport; -+ } -+ -+ INIT_LIST_HEAD(&priv->port_list); -+ netdev->flags |= IFF_PROMISC | IFF_MASTER; -+ -+ dev_alloc_name(netdev, "evb%d"); -+ -+ /* register switch ports */ -+ snprintf(port_name, IFNAMSIZ, "%sp%%d", netdev->name); -+ -+ /* only register downlinks? */ -+ for (i = 0; i < priv->attr.num_ifs + 1; i++) { -+ struct net_device *port_netdev; -+ struct evb_port_priv *port_priv; -+ -+ if (i) { -+ port_netdev = -+ alloc_etherdev(sizeof(struct evb_port_priv)); -+ if (!port_netdev) { -+ dev_err(dev, "alloc_etherdev error\n"); -+ goto err_takedown; -+ } -+ -+ port_priv = netdev_priv(port_netdev); -+ -+ port_netdev->flags |= IFF_PROMISC | IFF_SLAVE; -+ -+ dev_alloc_name(port_netdev, port_name); -+ } else { -+ port_netdev = netdev; -+ port_priv = &priv->uplink; -+ } -+ -+ port_priv->netdev = port_netdev; -+ port_priv->evb_priv = priv; -+ port_priv->port_index = i; -+ -+ SET_NETDEV_DEV(port_netdev, dev); -+ -+ if (i) { -+ port_netdev->netdev_ops = &evb_port_ops; -+ -+ err = register_netdev(port_netdev); -+ if (err < 0) { -+ dev_err(dev, "register_netdev err %d\n", err); -+ free_netdev(port_netdev); -+ goto err_takedown; -+ } -+ -+ rtnl_lock(); -+ err = netdev_master_upper_dev_link(port_netdev, netdev, NULL, NULL); -+ if (unlikely(err)) { -+ dev_err(dev, "netdev_master_upper_dev_link err %d\n", -+ err); -+ unregister_netdev(port_netdev); -+ free_netdev(port_netdev); -+ rtnl_unlock(); -+ goto err_takedown; -+ } -+ rtmsg_ifinfo(RTM_NEWLINK, port_netdev, -+ IFF_SLAVE, GFP_KERNEL); -+ rtnl_unlock(); -+ -+ list_add(&(port_priv->list), &(priv->port_list)); -+ } else { -+ err = register_netdev(netdev); -+ -+ if (err < 0) { -+ dev_err(dev, "register_netdev error %d\n", err); -+ goto err_takedown; -+ } -+ } -+ -+ port_netdev->ethtool_ops = &evb_port_ethtool_ops; -+ -+ /* ports are up from init */ -+ rtnl_lock(); -+ err = dev_open(port_netdev); -+ rtnl_unlock(); -+ if (unlikely(err)) -+ dev_warn(dev, "dev_open err %d\n", err); -+ } -+ -+ /* setup irqs */ -+ err = evb_setup_irqs(evb_dev); -+ if (unlikely(err)) { -+ dev_warn(dev, "evb_setup_irqs err %d\n", err); -+ goto err_takedown; -+ } -+ -+ dev_info(dev, "probed evb device with %d ports\n", -+ priv->attr.num_ifs); -+ return 0; -+ -+err_takedown: -+ evb_remove(evb_dev); -+err_free_cmdport: -+ fsl_mc_portal_free(priv->mc_io); -+err_free_netdev: -+ return err; -+} -+ -+static const struct fsl_mc_device_match_id evb_match_id_table[] = { -+ { -+ .vendor = FSL_MC_VENDOR_FREESCALE, -+ .obj_type = "dpdmux", -+ .ver_major = DPDMUX_VER_MAJOR, -+ .ver_minor = DPDMUX_VER_MINOR, -+ }, -+ {} -+}; -+ -+static struct fsl_mc_driver evb_drv = { -+ .driver = { -+ .name = KBUILD_MODNAME, -+ .owner = THIS_MODULE, -+ }, -+ .probe = evb_probe, -+ .remove = evb_remove, -+ .match_id_table = evb_match_id_table, -+}; -+ -+module_fsl_mc_driver(evb_drv); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Layerscape DPAA Edge Virtual Bridge driver (prototype)"); diff --git a/target/linux/layerscape/patches-4.4/7216-dpaa2-evb-Fix-interrupt-handling.patch b/target/linux/layerscape/patches-4.4/7216-dpaa2-evb-Fix-interrupt-handling.patch deleted file mode 100644 index d3d976af98..0000000000 --- a/target/linux/layerscape/patches-4.4/7216-dpaa2-evb-Fix-interrupt-handling.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 4efb592d8a931669df5df04bedcae8cbc85c3700 Mon Sep 17 00:00:00 2001 -From: Razvan Stefanescu -Date: Wed, 17 Feb 2016 16:31:01 +0200 -Subject: [PATCH 216/226] dpaa2-evb: Fix interrupt handling - -Mask only the events handled by the driver - DPDMUX_IRQ_EVENT_LINK_CHANGED. - -Use clear-on-read mechanism for the interrupt status and avoid calling -dpdmux_clear_irq_status(). Status contains the events handled (only link -state change for the moment) and masks the first 16-bits, as they are used -to store the interface ID that generated the event. - -Signed-off-by: Razvan Stefanescu ---- - drivers/staging/fsl-dpaa2/evb/evb.c | 20 ++++++++++---------- - 1 file changed, 10 insertions(+), 10 deletions(-) - ---- a/drivers/staging/fsl-dpaa2/evb/evb.c -+++ b/drivers/staging/fsl-dpaa2/evb/evb.c -@@ -151,7 +151,9 @@ static irqreturn_t _evb_irq0_handler_thr - struct fsl_mc_io *io = priv->mc_io; - uint16_t token = priv->mux_handle; - int irq_index = DPDMUX_IRQ_INDEX_IF; -- uint32_t status = 0, clear = 0; -+ -+ /* Mask the events and the if_id reserved bits to be cleared on read */ -+ uint32_t status = DPDMUX_IRQ_EVENT_LINK_CHANGED | 0xFFFF0000; - int err; - - /* Sanity check */ -@@ -163,23 +165,21 @@ static irqreturn_t _evb_irq0_handler_thr - err = dpdmux_get_irq_status(io, 0, token, irq_index, &status); - if (unlikely(err)) { - netdev_err(netdev, "Can't get irq status (err %d)", err); -- clear = 0xffffffff; -+ err = dpdmux_clear_irq_status(io, 0, token, irq_index, -+ 0xFFFFFFFF); -+ if (unlikely(err)) -+ netdev_err(netdev, "Can't clear irq status (err %d)", -+ err); - goto out; - } - -- /* FIXME clear irq status */ -- - if (status & DPDMUX_IRQ_EVENT_LINK_CHANGED) { -- clear |= DPDMUX_IRQ_EVENT_LINK_CHANGED; -- - err = evb_links_state_update(priv); - if (unlikely(err)) - goto out; - } -+ - out: -- err = dpdmux_clear_irq_status(io, 0, token, irq_index, clear); -- if (unlikely(err)) -- netdev_err(netdev, "Can't clear irq status (err %d)", err); - return IRQ_HANDLED; - } - -@@ -191,7 +191,7 @@ static int evb_setup_irqs(struct fsl_mc_ - int err = 0; - struct fsl_mc_device_irq *irq; - const int irq_index = DPDMUX_IRQ_INDEX_IF; -- uint32_t mask = ~0x0u; /* FIXME: unmask handled irqs */ -+ uint32_t mask = DPDMUX_IRQ_EVENT_LINK_CHANGED; - - err = fsl_mc_allocate_irqs(evb_dev); - if (unlikely(err)) { diff --git a/target/linux/layerscape/patches-4.4/7217-dpaa2-evb-Add-object-version-check.patch b/target/linux/layerscape/patches-4.4/7217-dpaa2-evb-Add-object-version-check.patch deleted file mode 100644 index 13d61cfb5f..0000000000 --- a/target/linux/layerscape/patches-4.4/7217-dpaa2-evb-Add-object-version-check.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 213c59501bbd6da8c56e95f90f8a8c6af2682002 Mon Sep 17 00:00:00 2001 -From: Razvan Stefanescu -Date: Thu, 18 Feb 2016 10:54:40 +0200 -Subject: [PATCH 217/226] dpaa2-evb: Add object version check - -Abort probing if DPDMUX object version is smaller than required. - -Signed-off-by: Razvan Stefanescu ---- - drivers/staging/fsl-dpaa2/evb/evb.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/drivers/staging/fsl-dpaa2/evb/evb.c -+++ b/drivers/staging/fsl-dpaa2/evb/evb.c -@@ -44,6 +44,10 @@ - #include "dpdmux.h" - #include "dpdmux-cmd.h" - -+/* Minimal supported DPDMUX version */ -+#define DPDMUX_MIN_VER_MAJOR 5 -+#define DPDMUX_MIN_VER_MINOR 0 -+ - /* IRQ index */ - #define DPDMUX_MAX_IRQ_NUM 2 - -@@ -1004,6 +1008,17 @@ static int evb_init(struct fsl_mc_device - goto err_close; - } - -+ /* Minimum supported DPDMUX version check */ -+ if (priv->attr.version.major < DPDMUX_MIN_VER_MAJOR || -+ (priv->attr.version.major == DPDMUX_MIN_VER_MAJOR && -+ priv->attr.version.minor < DPDMUX_MIN_VER_MINOR)) { -+ dev_err(dev, "DPDMUX version %d.%d not supported. Use %d.%d or greater.\n", -+ priv->attr.version.major, priv->attr.version.minor, -+ DPDMUX_MIN_VER_MAJOR, DPDMUX_MIN_VER_MAJOR); -+ err = -ENOTSUPP; -+ goto err_close; -+ } -+ - err = dpdmux_reset(priv->mc_io, 0, priv->mux_handle); - if (unlikely(err)) { - dev_err(dev, "dpdmux_reset err %d\n", err); diff --git a/target/linux/layerscape/patches-4.4/7218-dpaa2-evb-Cosmetic-cleanup.patch b/target/linux/layerscape/patches-4.4/7218-dpaa2-evb-Cosmetic-cleanup.patch deleted file mode 100644 index 54f77ab65c..0000000000 --- a/target/linux/layerscape/patches-4.4/7218-dpaa2-evb-Cosmetic-cleanup.patch +++ /dev/null @@ -1,20 +0,0 @@ -From 54d026dafa1f7d17758615736123917cc4f3f203 Mon Sep 17 00:00:00 2001 -From: Mihai Caraman -Date: Tue, 5 Apr 2016 14:12:10 +0000 -Subject: [PATCH 218/226] dpaa2-evb: Cosmetic cleanup - -Replace obsolete terms. - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-dpaa2/evb/evb.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/staging/fsl-dpaa2/evb/evb.c -+++ b/drivers/staging/fsl-dpaa2/evb/evb.c -@@ -1228,4 +1228,4 @@ static struct fsl_mc_driver evb_drv = { - module_fsl_mc_driver(evb_drv); - - MODULE_LICENSE("GPL"); --MODULE_DESCRIPTION("Layerscape DPAA Edge Virtual Bridge driver (prototype)"); -+MODULE_DESCRIPTION("DPAA2 Edge Virtual Bridge driver (prototype)"); diff --git a/target/linux/layerscape/patches-4.4/7219-dpaa2-evb-match-id-cleanup.patch b/target/linux/layerscape/patches-4.4/7219-dpaa2-evb-match-id-cleanup.patch deleted file mode 100644 index be1ab1baf0..0000000000 --- a/target/linux/layerscape/patches-4.4/7219-dpaa2-evb-match-id-cleanup.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 744bd6494a51443c2a7d32ed76e94e4fc5bd2404 Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Thu, 14 Jul 2016 17:32:23 -0500 -Subject: [PATCH 219/226] dpaa2-evb: match id cleanup - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-dpaa2/evb/evb.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/staging/fsl-dpaa2/evb/evb.c -+++ b/drivers/staging/fsl-dpaa2/evb/evb.c -@@ -1205,12 +1205,10 @@ err_free_netdev: - return err; - } - --static const struct fsl_mc_device_match_id evb_match_id_table[] = { -+static const struct fsl_mc_device_id evb_match_id_table[] = { - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dpdmux", -- .ver_major = DPDMUX_VER_MAJOR, -- .ver_minor = DPDMUX_VER_MINOR, - }, - {} - }; diff --git a/target/linux/layerscape/patches-4.4/7220-dpaa2-ethsw-Ethernet-Switch-driver.patch b/target/linux/layerscape/patches-4.4/7220-dpaa2-ethsw-Ethernet-Switch-driver.patch deleted file mode 100644 index 067eb59a23..0000000000 --- a/target/linux/layerscape/patches-4.4/7220-dpaa2-ethsw-Ethernet-Switch-driver.patch +++ /dev/null @@ -1,6605 +0,0 @@ -From 8df017d70c54ceafc99b7904785603c678a2e5c1 Mon Sep 17 00:00:00 2001 -From: Razvan Stefanescu -Date: Tue, 22 Sep 2015 11:36:34 +0300 -Subject: [PATCH 220/226] dpaa2-ethsw: Ethernet Switch driver - -This is a commit of the cummulative, squashed dpaa2-l2switch patches. -All the commit logs are preserved below. - -Signed-off-by: Stuart Yoder - ---------------------------------------------------------------------- - -dpaa2-ethsw: Ethernet Switch driver - -Initial support for DPAA2 L2 switch. The switch and all ports are -presented as network interfaces in linux (swX and swXpY). I/O -functionality is not available on these interfaces, they are exclusively -for management. - -Configuration is done using bridge tool. Supported commands are: -- fdb operations with unicast/multicast addresses -- vlan configuration -- setting STP state of ports -- flooding, learning control - -Offers support for retrieving port statistics via ethtool (or similar -applications). - -This patch contains the following patches squashed together: -staging: fsl-dpaa2: ethsw: ethernet switch driver -dpaa2-ethsw: Include by default in configuration -staging: fsl-dpaa2: ethsw: Rebasing onto kernel 4.0 -staging: fsl-mc: migrated remaining flibs for MC fw 8.0.0 -dpaa2-ethsw: Prefix driver name with dpaa2- -dpaa2-ethsw: Set carrier state on probe -dpaa2-ethsw: Add support for link state update - -These patches were initally submitted by: -Alex Marginean -J. German Rivera -Razvan Stefanescu - -and reviewed by Stuart Yoder - -Ported to linux-v4.1 by updating iflink usage and ndo_bridge_getlink() -parameters list update. - -Signed-off-by: Razvan Stefanescu -[Stuart: resolved minor merge conflicts] -Signed-off-by: Stuart Yoder - -dpaa2-ethsw: Update dpsw binary interface to 7.0 - -This corresponds to MC release 0.8.0. - -Signed-off-by: Razvan Stefanescu - -dpaa2-ethsw: Add object version check - -Abort probing if DPSW object version is smaller than required. - -Signed-off-by: Razvan Stefanescu - -dpaa2-ethsw: Fix interrupt handling - -Mask only the events handled by the driver - DPSW_IRQ_EVENT_LINK_CHANGED. - -Use clear-on-read mechanism for the interrupt status and avoid calling -dpsw_clear_irq_status(). Status contains the events handled (only link -state change for the moment) and masks the first 16-bits, as they are used -to store the interface ID that generated the event. - -Signed-off-by: Razvan Stefanescu - -dpaa2-ethsw: resolve compile issues on uprev to 4.5 - --irq_number field no longer exists in fsl-mc interrupt - struct --netdev_master_upper_dev_link() has 2 new parameters, which - are set to NULL for now - -Signed-off-by: Stuart Yoder ---- - MAINTAINERS | 6 + - drivers/staging/fsl-dpaa2/Kconfig | 1 + - drivers/staging/fsl-dpaa2/Makefile | 1 + - drivers/staging/fsl-dpaa2/ethsw/Kconfig | 7 + - drivers/staging/fsl-dpaa2/ethsw/Makefile | 10 + - drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h | 916 ++++++++++++ - drivers/staging/fsl-dpaa2/ethsw/dpsw.c | 1639 +++++++++++++++++++++ - drivers/staging/fsl-dpaa2/ethsw/dpsw.h | 2164 ++++++++++++++++++++++++++++ - drivers/staging/fsl-dpaa2/ethsw/switch.c | 1711 ++++++++++++++++++++++ - drivers/staging/fsl-mc/include/net.h | 1 - - 10 files changed, 6455 insertions(+), 1 deletion(-) - create mode 100644 drivers/staging/fsl-dpaa2/ethsw/Kconfig - create mode 100644 drivers/staging/fsl-dpaa2/ethsw/Makefile - create mode 100644 drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h - create mode 100644 drivers/staging/fsl-dpaa2/ethsw/dpsw.c - create mode 100644 drivers/staging/fsl-dpaa2/ethsw/dpsw.h - create mode 100644 drivers/staging/fsl-dpaa2/ethsw/switch.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -4554,6 +4554,12 @@ S: Maintained - F: drivers/staging/fsl-mc/bus/mc-ioctl.h - F: drivers/staging/fsl-mc/bus/mc-restool.c - -+FREESCALE DPAA2 ETHERNET SWITCH DRIVER -+M: Alex Marginean -+L: linux-kernel@vger.kernel.org -+S: Maintained -+F: drivers/staging/fsl-dpaa2/ethsw/ -+ - FREESCALE DPAA2 MAC/PHY INTERFACE DRIVER - M: Alex Marginean - L: linux-kernel@vger.kernel.org ---- a/drivers/staging/fsl-dpaa2/Kconfig -+++ b/drivers/staging/fsl-dpaa2/Kconfig -@@ -11,3 +11,4 @@ config FSL_DPAA2 - source "drivers/staging/fsl-dpaa2/ethernet/Kconfig" - source "drivers/staging/fsl-dpaa2/mac/Kconfig" - source "drivers/staging/fsl-dpaa2/evb/Kconfig" -+source "drivers/staging/fsl-dpaa2/ethsw/Kconfig" ---- a/drivers/staging/fsl-dpaa2/Makefile -+++ b/drivers/staging/fsl-dpaa2/Makefile -@@ -5,3 +5,4 @@ - obj-$(CONFIG_FSL_DPAA2_ETH) += ethernet/ - obj-$(CONFIG_FSL_DPAA2_MAC) += mac/ - obj-$(CONFIG_FSL_DPAA2_EVB) += evb/ -+obj-$(CONFIG_FSL_DPAA2_ETHSW) += ethsw/ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethsw/Kconfig -@@ -0,0 +1,7 @@ -+config FSL_DPAA2_ETHSW -+ tristate "DPAA2 Ethernet Switch" -+ depends on FSL_MC_BUS && FSL_DPAA2 && FSL_DPAA2_ETH -+ select FSL_DPAA2_MAC -+ default y -+ ---help--- -+ Prototype driver for DPAA2 Ethernet Switch. ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethsw/Makefile -@@ -0,0 +1,10 @@ -+ -+obj-$(CONFIG_FSL_DPAA2_ETHSW) += dpaa2-ethsw.o -+ -+dpaa2-ethsw-objs := switch.o dpsw.o -+ -+all: -+ make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules -+ -+clean: -+ make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h -@@ -0,0 +1,916 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef __FSL_DPSW_CMD_H -+#define __FSL_DPSW_CMD_H -+ -+/* DPSW Version */ -+#define DPSW_VER_MAJOR 7 -+#define DPSW_VER_MINOR 0 -+ -+/* Command IDs */ -+#define DPSW_CMDID_CLOSE 0x800 -+#define DPSW_CMDID_OPEN 0x802 -+#define DPSW_CMDID_CREATE 0x902 -+#define DPSW_CMDID_DESTROY 0x900 -+ -+#define DPSW_CMDID_ENABLE 0x002 -+#define DPSW_CMDID_DISABLE 0x003 -+#define DPSW_CMDID_GET_ATTR 0x004 -+#define DPSW_CMDID_RESET 0x005 -+#define DPSW_CMDID_IS_ENABLED 0x006 -+ -+#define DPSW_CMDID_SET_IRQ 0x010 -+#define DPSW_CMDID_GET_IRQ 0x011 -+#define DPSW_CMDID_SET_IRQ_ENABLE 0x012 -+#define DPSW_CMDID_GET_IRQ_ENABLE 0x013 -+#define DPSW_CMDID_SET_IRQ_MASK 0x014 -+#define DPSW_CMDID_GET_IRQ_MASK 0x015 -+#define DPSW_CMDID_GET_IRQ_STATUS 0x016 -+#define DPSW_CMDID_CLEAR_IRQ_STATUS 0x017 -+ -+#define DPSW_CMDID_SET_REFLECTION_IF 0x022 -+ -+#define DPSW_CMDID_ADD_CUSTOM_TPID 0x024 -+ -+#define DPSW_CMDID_REMOVE_CUSTOM_TPID 0x026 -+ -+#define DPSW_CMDID_IF_SET_TCI 0x030 -+#define DPSW_CMDID_IF_SET_STP 0x031 -+#define DPSW_CMDID_IF_SET_ACCEPTED_FRAMES 0x032 -+#define DPSW_CMDID_SET_IF_ACCEPT_ALL_VLAN 0x033 -+#define DPSW_CMDID_IF_GET_COUNTER 0x034 -+#define DPSW_CMDID_IF_SET_COUNTER 0x035 -+#define DPSW_CMDID_IF_SET_TX_SELECTION 0x036 -+#define DPSW_CMDID_IF_ADD_REFLECTION 0x037 -+#define DPSW_CMDID_IF_REMOVE_REFLECTION 0x038 -+#define DPSW_CMDID_IF_SET_FLOODING_METERING 0x039 -+#define DPSW_CMDID_IF_SET_METERING 0x03A -+#define DPSW_CMDID_IF_SET_EARLY_DROP 0x03B -+ -+#define DPSW_CMDID_IF_ENABLE 0x03D -+#define DPSW_CMDID_IF_DISABLE 0x03E -+ -+#define DPSW_CMDID_IF_GET_ATTR 0x042 -+ -+#define DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH 0x044 -+#define DPSW_CMDID_IF_GET_MAX_FRAME_LENGTH 0x045 -+#define DPSW_CMDID_IF_GET_LINK_STATE 0x046 -+#define DPSW_CMDID_IF_SET_FLOODING 0x047 -+#define DPSW_CMDID_IF_SET_BROADCAST 0x048 -+#define DPSW_CMDID_IF_SET_MULTICAST 0x049 -+#define DPSW_CMDID_IF_GET_TCI 0x04A -+ -+#define DPSW_CMDID_IF_SET_LINK_CFG 0x04C -+ -+#define DPSW_CMDID_VLAN_ADD 0x060 -+#define DPSW_CMDID_VLAN_ADD_IF 0x061 -+#define DPSW_CMDID_VLAN_ADD_IF_UNTAGGED 0x062 -+#define DPSW_CMDID_VLAN_ADD_IF_FLOODING 0x063 -+#define DPSW_CMDID_VLAN_REMOVE_IF 0x064 -+#define DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED 0x065 -+#define DPSW_CMDID_VLAN_REMOVE_IF_FLOODING 0x066 -+#define DPSW_CMDID_VLAN_REMOVE 0x067 -+#define DPSW_CMDID_VLAN_GET_IF 0x068 -+#define DPSW_CMDID_VLAN_GET_IF_FLOODING 0x069 -+#define DPSW_CMDID_VLAN_GET_IF_UNTAGGED 0x06A -+#define DPSW_CMDID_VLAN_GET_ATTRIBUTES 0x06B -+ -+#define DPSW_CMDID_FDB_GET_MULTICAST 0x080 -+#define DPSW_CMDID_FDB_GET_UNICAST 0x081 -+#define DPSW_CMDID_FDB_ADD 0x082 -+#define DPSW_CMDID_FDB_REMOVE 0x083 -+#define DPSW_CMDID_FDB_ADD_UNICAST 0x084 -+#define DPSW_CMDID_FDB_REMOVE_UNICAST 0x085 -+#define DPSW_CMDID_FDB_ADD_MULTICAST 0x086 -+#define DPSW_CMDID_FDB_REMOVE_MULTICAST 0x087 -+#define DPSW_CMDID_FDB_SET_LEARNING_MODE 0x088 -+#define DPSW_CMDID_FDB_GET_ATTR 0x089 -+ -+#define DPSW_CMDID_ACL_ADD 0x090 -+#define DPSW_CMDID_ACL_REMOVE 0x091 -+#define DPSW_CMDID_ACL_ADD_ENTRY 0x092 -+#define DPSW_CMDID_ACL_REMOVE_ENTRY 0x093 -+#define DPSW_CMDID_ACL_ADD_IF 0x094 -+#define DPSW_CMDID_ACL_REMOVE_IF 0x095 -+#define DPSW_CMDID_ACL_GET_ATTR 0x096 -+ -+#define DPSW_CMDID_CTRL_IF_GET_ATTR 0x0A0 -+#define DPSW_CMDID_CTRL_IF_SET_POOLS 0x0A1 -+#define DPSW_CMDID_CTRL_IF_ENABLE 0x0A2 -+#define DPSW_CMDID_CTRL_IF_DISABLE 0x0A3 -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_OPEN(cmd, dpsw_id) \ -+ MC_CMD_OP(cmd, 0, 0, 32, int, dpsw_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_CREATE(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->num_ifs);\ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->adv.max_fdbs);\ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->adv.max_meters_per_if);\ -+ MC_CMD_OP(cmd, 0, 32, 4, enum dpsw_component_type, \ -+ cfg->adv.component_type);\ -+ MC_CMD_OP(cmd, 1, 0, 16, uint16_t, cfg->adv.max_vlans);\ -+ MC_CMD_OP(cmd, 1, 16, 16, uint16_t, cfg->adv.max_fdb_entries);\ -+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, cfg->adv.fdb_aging_time);\ -+ MC_CMD_OP(cmd, 1, 48, 16, uint16_t, cfg->adv.max_fdb_mc_groups);\ -+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->adv.options);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_IS_ENABLED(cmd, en) \ -+ MC_RSP_OP(cmd, 0, 0, 1, int, en) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\ -+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\ -+ MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_GET_IRQ(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_GET_IRQ(cmd, type, irq_cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\ -+ MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \ -+ MC_RSP_OP(cmd, 2, 32, 32, int, type); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_SET_IRQ_ENABLE(cmd, irq_index, enable_state) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, enable_state); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_GET_IRQ_ENABLE(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_GET_IRQ_ENABLE(cmd, enable_state) \ -+ MC_RSP_OP(cmd, 0, 0, 8, uint8_t, enable_state) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_GET_IRQ_MASK(cmd, irq_index) \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_GET_IRQ_MASK(cmd, mask) \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_GET_IRQ_STATUS(cmd, status) \ -+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_GET_ATTR(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, attr->num_ifs);\ -+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, attr->max_fdbs);\ -+ MC_RSP_OP(cmd, 0, 24, 8, uint8_t, attr->num_fdbs);\ -+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->max_vlans);\ -+ MC_RSP_OP(cmd, 0, 48, 16, uint16_t, attr->num_vlans);\ -+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\ -+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\ -+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, attr->max_fdb_entries);\ -+ MC_RSP_OP(cmd, 1, 48, 16, uint16_t, attr->fdb_aging_time);\ -+ MC_RSP_OP(cmd, 2, 0, 32, int, attr->id);\ -+ MC_RSP_OP(cmd, 2, 32, 16, uint16_t, attr->mem_size);\ -+ MC_RSP_OP(cmd, 2, 48, 16, uint16_t, attr->max_fdb_mc_groups);\ -+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, attr->options);\ -+ MC_RSP_OP(cmd, 4, 0, 8, uint8_t, attr->max_meters_per_if);\ -+ MC_RSP_OP(cmd, 4, 8, 4, enum dpsw_component_type, \ -+ attr->component_type);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_SET_REFLECTION_IF(cmd, if_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_FLOODING(cmd, if_id, en) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 1, int, en);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_BROADCAST(cmd, if_id, en) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 1, int, en);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_MULTICAST(cmd, if_id, en) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 1, int, en);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_TCI(cmd, if_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 12, uint16_t, cfg->vlan_id);\ -+ MC_CMD_OP(cmd, 0, 28, 1, uint8_t, cfg->dei);\ -+ MC_CMD_OP(cmd, 0, 29, 3, uint8_t, cfg->pcp);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_GET_TCI(cmd, if_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_IF_GET_TCI(cmd, cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, cfg->vlan_id);\ -+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, cfg->dei);\ -+ MC_RSP_OP(cmd, 0, 40, 8, uint8_t, cfg->pcp);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_STP(cmd, if_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->vlan_id);\ -+ MC_CMD_OP(cmd, 0, 32, 4, enum dpsw_stp_state, cfg->state);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_ACCEPTED_FRAMES(cmd, if_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 4, enum dpsw_accepted_frames, cfg->type);\ -+ MC_CMD_OP(cmd, 0, 20, 4, enum dpsw_action, cfg->unaccept_act);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_ACCEPT_ALL_VLAN(cmd, if_id, accept_all) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 1, int, accept_all);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_GET_COUNTER(cmd, if_id, type) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 5, enum dpsw_counter, type);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_IF_GET_COUNTER(cmd, counter) \ -+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_COUNTER(cmd, if_id, type, counter) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 5, enum dpsw_counter, type);\ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, counter);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_TX_SELECTION(cmd, if_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 3, enum dpsw_priority_selector, \ -+ cfg->priority_selector);\ -+ MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->tc_id[0]);\ -+ MC_CMD_OP(cmd, 1, 8, 8, uint8_t, cfg->tc_id[1]);\ -+ MC_CMD_OP(cmd, 1, 16, 8, uint8_t, cfg->tc_id[2]);\ -+ MC_CMD_OP(cmd, 1, 24, 8, uint8_t, cfg->tc_id[3]);\ -+ MC_CMD_OP(cmd, 1, 32, 8, uint8_t, cfg->tc_id[4]);\ -+ MC_CMD_OP(cmd, 1, 40, 8, uint8_t, cfg->tc_id[5]);\ -+ MC_CMD_OP(cmd, 1, 48, 8, uint8_t, cfg->tc_id[6]);\ -+ MC_CMD_OP(cmd, 1, 56, 8, uint8_t, cfg->tc_id[7]);\ -+ MC_CMD_OP(cmd, 2, 0, 16, uint16_t, cfg->tc_sched[0].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 2, 16, 4, enum dpsw_schedule_mode, \ -+ cfg->tc_sched[0].mode);\ -+ MC_CMD_OP(cmd, 2, 32, 16, uint16_t, cfg->tc_sched[1].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 2, 48, 4, enum dpsw_schedule_mode, \ -+ cfg->tc_sched[1].mode);\ -+ MC_CMD_OP(cmd, 3, 0, 16, uint16_t, cfg->tc_sched[2].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 3, 16, 4, enum dpsw_schedule_mode, \ -+ cfg->tc_sched[2].mode);\ -+ MC_CMD_OP(cmd, 3, 32, 16, uint16_t, cfg->tc_sched[3].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 3, 48, 4, enum dpsw_schedule_mode, \ -+ cfg->tc_sched[3].mode);\ -+ MC_CMD_OP(cmd, 4, 0, 16, uint16_t, cfg->tc_sched[4].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 4, 16, 4, enum dpsw_schedule_mode, \ -+ cfg->tc_sched[4].mode);\ -+ MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->tc_sched[5].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 4, 48, 4, enum dpsw_schedule_mode, \ -+ cfg->tc_sched[5].mode);\ -+ MC_CMD_OP(cmd, 5, 0, 16, uint16_t, cfg->tc_sched[6].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 5, 16, 4, enum dpsw_schedule_mode, \ -+ cfg->tc_sched[6].mode);\ -+ MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->tc_sched[7].delta_bandwidth);\ -+ MC_CMD_OP(cmd, 5, 48, 4, enum dpsw_schedule_mode, \ -+ cfg->tc_sched[7].mode);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_ADD_REFLECTION(cmd, if_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->vlan_id);\ -+ MC_CMD_OP(cmd, 0, 32, 2, enum dpsw_reflection_filter, cfg->filter);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_REMOVE_REFLECTION(cmd, if_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->vlan_id);\ -+ MC_CMD_OP(cmd, 0, 32, 2, enum dpsw_reflection_filter, cfg->filter);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_FLOODING_METERING(cmd, if_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 24, 4, enum dpsw_metering_mode, cfg->mode);\ -+ MC_CMD_OP(cmd, 0, 28, 4, enum dpsw_metering_unit, cfg->units);\ -+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, cfg->cir);\ -+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->eir);\ -+ MC_CMD_OP(cmd, 1, 32, 32, uint32_t, cfg->cbs);\ -+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->ebs);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_METERING(cmd, if_id, tc_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id);\ -+ MC_CMD_OP(cmd, 0, 24, 4, enum dpsw_metering_mode, cfg->mode);\ -+ MC_CMD_OP(cmd, 0, 28, 4, enum dpsw_metering_unit, cfg->units);\ -+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, cfg->cir);\ -+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->eir);\ -+ MC_CMD_OP(cmd, 1, 32, 32, uint32_t, cfg->cbs);\ -+ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->ebs);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_PREP_EARLY_DROP(ext, cfg) \ -+do { \ -+ MC_PREP_OP(ext, 0, 0, 2, enum dpsw_early_drop_mode, cfg->drop_mode); \ -+ MC_PREP_OP(ext, 0, 2, 2, \ -+ enum dpsw_early_drop_unit, cfg->units); \ -+ MC_PREP_OP(ext, 0, 32, 32, uint32_t, cfg->tail_drop_threshold); \ -+ MC_PREP_OP(ext, 1, 0, 8, uint8_t, cfg->green.drop_probability); \ -+ MC_PREP_OP(ext, 2, 0, 64, uint64_t, cfg->green.max_threshold); \ -+ MC_PREP_OP(ext, 3, 0, 64, uint64_t, cfg->green.min_threshold); \ -+ MC_PREP_OP(ext, 5, 0, 8, uint8_t, cfg->yellow.drop_probability);\ -+ MC_PREP_OP(ext, 6, 0, 64, uint64_t, cfg->yellow.max_threshold); \ -+ MC_PREP_OP(ext, 7, 0, 64, uint64_t, cfg->yellow.min_threshold); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_EXT_EARLY_DROP(ext, cfg) \ -+do { \ -+ MC_EXT_OP(ext, 0, 0, 2, enum dpsw_early_drop_mode, cfg->drop_mode); \ -+ MC_EXT_OP(ext, 0, 2, 2, \ -+ enum dpsw_early_drop_unit, cfg->units); \ -+ MC_EXT_OP(ext, 0, 32, 32, uint32_t, cfg->tail_drop_threshold); \ -+ MC_EXT_OP(ext, 1, 0, 8, uint8_t, cfg->green.drop_probability); \ -+ MC_EXT_OP(ext, 2, 0, 64, uint64_t, cfg->green.max_threshold); \ -+ MC_EXT_OP(ext, 3, 0, 64, uint64_t, cfg->green.min_threshold); \ -+ MC_EXT_OP(ext, 5, 0, 8, uint8_t, cfg->yellow.drop_probability);\ -+ MC_EXT_OP(ext, 6, 0, 64, uint64_t, cfg->yellow.max_threshold); \ -+ MC_EXT_OP(ext, 7, 0, 64, uint64_t, cfg->yellow.min_threshold); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_EARLY_DROP(cmd, if_id, tc_id, early_drop_iova) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc_id); \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, if_id); \ -+ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, early_drop_iova); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_ADD_CUSTOM_TPID(cmd, cfg) \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->tpid) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_REMOVE_CUSTOM_TPID(cmd, cfg) \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->tpid) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_ENABLE(cmd, if_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_DISABLE(cmd, if_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_GET_ATTR(cmd, if_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_IF_GET_ATTR(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 0, 4, enum dpsw_accepted_frames, \ -+ attr->admit_untagged);\ -+ MC_RSP_OP(cmd, 0, 5, 1, int, attr->enabled);\ -+ MC_RSP_OP(cmd, 0, 6, 1, int, attr->accept_all_vlan);\ -+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, attr->num_tcs);\ -+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qdid);\ -+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options);\ -+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->rate);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_MAX_FRAME_LENGTH(cmd, if_id, frame_length) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, frame_length);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_GET_MAX_FRAME_LENGTH(cmd, if_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_IF_GET_MAX_FRAME_LENGTH(cmd, frame_length) \ -+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, frame_length) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_SET_LINK_CFG(cmd, if_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id);\ -+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate);\ -+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_IF_GET_LINK_STATE(cmd, if_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, if_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_IF_GET_LINK_STATE(cmd, state) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 32, 1, int, state->up);\ -+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, state->rate);\ -+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_VLAN_ADD(cmd, vlan_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->fdb_id);\ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_VLAN_ADD_IF(cmd, vlan_id) \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_VLAN_ADD_IF_UNTAGGED(cmd, vlan_id) \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_VLAN_ADD_IF_FLOODING(cmd, vlan_id) \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id) -+ -+#define DPSW_CMD_VLAN_REMOVE_IF(cmd, vlan_id) \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_VLAN_REMOVE_IF_UNTAGGED(cmd, vlan_id) \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_VLAN_REMOVE_IF_FLOODING(cmd, vlan_id) \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_VLAN_REMOVE(cmd, vlan_id) \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, vlan_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_VLAN_GET_ATTR(cmd, vlan_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, vlan_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_VLAN_GET_ATTR(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->fdb_id); \ -+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->num_ifs); \ -+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, attr->num_untagged_ifs); \ -+ MC_RSP_OP(cmd, 1, 48, 16, uint16_t, attr->num_flooding_ifs); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_VLAN_GET_IF(cmd, vlan_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, vlan_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_VLAN_GET_IF(cmd, cfg) \ -+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_VLAN_GET_IF_FLOODING(cmd, vlan_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, vlan_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_VLAN_GET_IF_FLOODING(cmd, cfg) \ -+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_VLAN_GET_IF_UNTAGGED(cmd, vlan_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, vlan_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_VLAN_GET_IF_UNTAGGED(cmd, cfg) \ -+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs) -+ -+/* param, offset, width, type, arg_name */ -+#define DPSW_CMD_FDB_ADD(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->fdb_aging_time);\ -+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, cfg->num_fdb_entries);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_FDB_ADD(cmd, fdb_id) \ -+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, fdb_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_FDB_REMOVE(cmd, fdb_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_FDB_ADD_UNICAST(cmd, fdb_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]);\ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]);\ -+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]);\ -+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]);\ -+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]);\ -+ MC_CMD_OP(cmd, 1, 0, 8, uint16_t, cfg->if_egress);\ -+ MC_CMD_OP(cmd, 1, 16, 4, enum dpsw_fdb_entry_type, cfg->type);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_FDB_GET_UNICAST(cmd, fdb_id) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]);\ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]);\ -+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]);\ -+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]);\ -+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_FDB_GET_UNICAST(cmd, cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, cfg->if_egress);\ -+ MC_RSP_OP(cmd, 1, 16, 4, enum dpsw_fdb_entry_type, cfg->type);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_FDB_REMOVE_UNICAST(cmd, fdb_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]);\ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]);\ -+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]);\ -+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]);\ -+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]);\ -+ MC_CMD_OP(cmd, 1, 0, 16, uint16_t, cfg->if_egress);\ -+ MC_CMD_OP(cmd, 1, 16, 4, enum dpsw_fdb_entry_type, cfg->type);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_FDB_ADD_MULTICAST(cmd, fdb_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs);\ -+ MC_CMD_OP(cmd, 0, 32, 4, enum dpsw_fdb_entry_type, cfg->type);\ -+ MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->mac_addr[5]);\ -+ MC_CMD_OP(cmd, 1, 8, 8, uint8_t, cfg->mac_addr[4]);\ -+ MC_CMD_OP(cmd, 1, 16, 8, uint8_t, cfg->mac_addr[3]);\ -+ MC_CMD_OP(cmd, 1, 24, 8, uint8_t, cfg->mac_addr[2]);\ -+ MC_CMD_OP(cmd, 1, 32, 8, uint8_t, cfg->mac_addr[1]);\ -+ MC_CMD_OP(cmd, 1, 40, 8, uint8_t, cfg->mac_addr[0]);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_FDB_GET_MULTICAST(cmd, fdb_id) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\ -+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]);\ -+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]);\ -+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]);\ -+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]);\ -+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]);\ -+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_FDB_GET_MULTICAST(cmd, cfg) \ -+do { \ -+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, cfg->num_ifs);\ -+ MC_RSP_OP(cmd, 1, 16, 4, enum dpsw_fdb_entry_type, cfg->type);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_FDB_REMOVE_MULTICAST(cmd, fdb_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs);\ -+ MC_CMD_OP(cmd, 0, 32, 4, enum dpsw_fdb_entry_type, cfg->type);\ -+ MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->mac_addr[5]);\ -+ MC_CMD_OP(cmd, 1, 8, 8, uint8_t, cfg->mac_addr[4]);\ -+ MC_CMD_OP(cmd, 1, 16, 8, uint8_t, cfg->mac_addr[3]);\ -+ MC_CMD_OP(cmd, 1, 24, 8, uint8_t, cfg->mac_addr[2]);\ -+ MC_CMD_OP(cmd, 1, 32, 8, uint8_t, cfg->mac_addr[1]);\ -+ MC_CMD_OP(cmd, 1, 40, 8, uint8_t, cfg->mac_addr[0]);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_FDB_SET_LEARNING_MODE(cmd, fdb_id, mode) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id);\ -+ MC_CMD_OP(cmd, 0, 16, 4, enum dpsw_fdb_learning_mode, mode);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_FDB_GET_ATTR(cmd, fdb_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, fdb_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_FDB_GET_ATTR(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->max_fdb_entries);\ -+ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->fdb_aging_time);\ -+ MC_RSP_OP(cmd, 0, 48, 16, uint16_t, attr->num_fdb_mc_groups);\ -+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->max_fdb_mc_groups);\ -+ MC_RSP_OP(cmd, 1, 16, 4, enum dpsw_fdb_learning_mode, \ -+ attr->learning_mode);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_ACL_ADD(cmd, cfg) \ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->max_entries) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_ACL_ADD(cmd, acl_id) \ -+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, acl_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_ACL_REMOVE(cmd, acl_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, acl_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_PREP_ACL_ENTRY(ext, key) \ -+do { \ -+ MC_PREP_OP(ext, 0, 0, 8, uint8_t, key->match.l2_dest_mac[5]);\ -+ MC_PREP_OP(ext, 0, 8, 8, uint8_t, key->match.l2_dest_mac[4]);\ -+ MC_PREP_OP(ext, 0, 16, 8, uint8_t, key->match.l2_dest_mac[3]);\ -+ MC_PREP_OP(ext, 0, 24, 8, uint8_t, key->match.l2_dest_mac[2]);\ -+ MC_PREP_OP(ext, 0, 32, 8, uint8_t, key->match.l2_dest_mac[1]);\ -+ MC_PREP_OP(ext, 0, 40, 8, uint8_t, key->match.l2_dest_mac[0]);\ -+ MC_PREP_OP(ext, 0, 48, 16, uint16_t, key->match.l2_tpid);\ -+ MC_PREP_OP(ext, 1, 0, 8, uint8_t, key->match.l2_source_mac[5]);\ -+ MC_PREP_OP(ext, 1, 8, 8, uint8_t, key->match.l2_source_mac[4]);\ -+ MC_PREP_OP(ext, 1, 16, 8, uint8_t, key->match.l2_source_mac[3]);\ -+ MC_PREP_OP(ext, 1, 24, 8, uint8_t, key->match.l2_source_mac[2]);\ -+ MC_PREP_OP(ext, 1, 32, 8, uint8_t, key->match.l2_source_mac[1]);\ -+ MC_PREP_OP(ext, 1, 40, 8, uint8_t, key->match.l2_source_mac[0]);\ -+ MC_PREP_OP(ext, 1, 48, 16, uint16_t, key->match.l2_vlan_id);\ -+ MC_PREP_OP(ext, 2, 0, 32, uint32_t, key->match.l3_dest_ip);\ -+ MC_PREP_OP(ext, 2, 32, 32, uint32_t, key->match.l3_source_ip);\ -+ MC_PREP_OP(ext, 3, 0, 16, uint16_t, key->match.l4_dest_port);\ -+ MC_PREP_OP(ext, 3, 16, 16, uint16_t, key->match.l4_source_port);\ -+ MC_PREP_OP(ext, 3, 32, 16, uint16_t, key->match.l2_ether_type);\ -+ MC_PREP_OP(ext, 3, 48, 8, uint8_t, key->match.l2_pcp_dei);\ -+ MC_PREP_OP(ext, 3, 56, 8, uint8_t, key->match.l3_dscp);\ -+ MC_PREP_OP(ext, 4, 0, 8, uint8_t, key->mask.l2_dest_mac[5]);\ -+ MC_PREP_OP(ext, 4, 8, 8, uint8_t, key->mask.l2_dest_mac[4]);\ -+ MC_PREP_OP(ext, 4, 16, 8, uint8_t, key->mask.l2_dest_mac[3]);\ -+ MC_PREP_OP(ext, 4, 24, 8, uint8_t, key->mask.l2_dest_mac[2]);\ -+ MC_PREP_OP(ext, 4, 32, 8, uint8_t, key->mask.l2_dest_mac[1]);\ -+ MC_PREP_OP(ext, 4, 40, 8, uint8_t, key->mask.l2_dest_mac[0]);\ -+ MC_PREP_OP(ext, 4, 48, 16, uint16_t, key->mask.l2_tpid);\ -+ MC_PREP_OP(ext, 5, 0, 8, uint8_t, key->mask.l2_source_mac[5]);\ -+ MC_PREP_OP(ext, 5, 8, 8, uint8_t, key->mask.l2_source_mac[4]);\ -+ MC_PREP_OP(ext, 5, 16, 8, uint8_t, key->mask.l2_source_mac[3]);\ -+ MC_PREP_OP(ext, 5, 24, 8, uint8_t, key->mask.l2_source_mac[2]);\ -+ MC_PREP_OP(ext, 5, 32, 8, uint8_t, key->mask.l2_source_mac[1]);\ -+ MC_PREP_OP(ext, 5, 40, 8, uint8_t, key->mask.l2_source_mac[0]);\ -+ MC_PREP_OP(ext, 5, 48, 16, uint16_t, key->mask.l2_vlan_id);\ -+ MC_PREP_OP(ext, 6, 0, 32, uint32_t, key->mask.l3_dest_ip);\ -+ MC_PREP_OP(ext, 6, 32, 32, uint32_t, key->mask.l3_source_ip);\ -+ MC_PREP_OP(ext, 7, 0, 16, uint16_t, key->mask.l4_dest_port);\ -+ MC_PREP_OP(ext, 7, 16, 16, uint16_t, key->mask.l4_source_port);\ -+ MC_PREP_OP(ext, 7, 32, 16, uint16_t, key->mask.l2_ether_type);\ -+ MC_PREP_OP(ext, 7, 48, 8, uint8_t, key->mask.l2_pcp_dei);\ -+ MC_PREP_OP(ext, 7, 56, 8, uint8_t, key->mask.l3_dscp);\ -+ MC_PREP_OP(ext, 8, 0, 8, uint8_t, key->match.l3_protocol);\ -+ MC_PREP_OP(ext, 8, 8, 8, uint8_t, key->mask.l3_protocol);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_EXT_ACL_ENTRY(ext, key) \ -+do { \ -+ MC_EXT_OP(ext, 0, 0, 8, uint8_t, key->match.l2_dest_mac[5]);\ -+ MC_EXT_OP(ext, 0, 8, 8, uint8_t, key->match.l2_dest_mac[4]);\ -+ MC_EXT_OP(ext, 0, 16, 8, uint8_t, key->match.l2_dest_mac[3]);\ -+ MC_EXT_OP(ext, 0, 24, 8, uint8_t, key->match.l2_dest_mac[2]);\ -+ MC_EXT_OP(ext, 0, 32, 8, uint8_t, key->match.l2_dest_mac[1]);\ -+ MC_EXT_OP(ext, 0, 40, 8, uint8_t, key->match.l2_dest_mac[0]);\ -+ MC_EXT_OP(ext, 0, 48, 16, uint16_t, key->match.l2_tpid);\ -+ MC_EXT_OP(ext, 1, 0, 8, uint8_t, key->match.l2_source_mac[5]);\ -+ MC_EXT_OP(ext, 1, 8, 8, uint8_t, key->match.l2_source_mac[4]);\ -+ MC_EXT_OP(ext, 1, 16, 8, uint8_t, key->match.l2_source_mac[3]);\ -+ MC_EXT_OP(ext, 1, 24, 8, uint8_t, key->match.l2_source_mac[2]);\ -+ MC_EXT_OP(ext, 1, 32, 8, uint8_t, key->match.l2_source_mac[1]);\ -+ MC_EXT_OP(ext, 1, 40, 8, uint8_t, key->match.l2_source_mac[0]);\ -+ MC_EXT_OP(ext, 1, 48, 16, uint16_t, key->match.l2_vlan_id);\ -+ MC_EXT_OP(ext, 2, 0, 32, uint32_t, key->match.l3_dest_ip);\ -+ MC_EXT_OP(ext, 2, 32, 32, uint32_t, key->match.l3_source_ip);\ -+ MC_EXT_OP(ext, 3, 0, 16, uint16_t, key->match.l4_dest_port);\ -+ MC_EXT_OP(ext, 3, 16, 16, uint16_t, key->match.l4_source_port);\ -+ MC_EXT_OP(ext, 3, 32, 16, uint16_t, key->match.l2_ether_type);\ -+ MC_EXT_OP(ext, 3, 48, 8, uint8_t, key->match.l2_pcp_dei);\ -+ MC_EXT_OP(ext, 3, 56, 8, uint8_t, key->match.l3_dscp);\ -+ MC_EXT_OP(ext, 4, 0, 8, uint8_t, key->mask.l2_dest_mac[5]);\ -+ MC_EXT_OP(ext, 4, 8, 8, uint8_t, key->mask.l2_dest_mac[4]);\ -+ MC_EXT_OP(ext, 4, 16, 8, uint8_t, key->mask.l2_dest_mac[3]);\ -+ MC_EXT_OP(ext, 4, 24, 8, uint8_t, key->mask.l2_dest_mac[2]);\ -+ MC_EXT_OP(ext, 4, 32, 8, uint8_t, key->mask.l2_dest_mac[1]);\ -+ MC_EXT_OP(ext, 4, 40, 8, uint8_t, key->mask.l2_dest_mac[0]);\ -+ MC_EXT_OP(ext, 4, 48, 16, uint16_t, key->mask.l2_tpid);\ -+ MC_EXT_OP(ext, 5, 0, 8, uint8_t, key->mask.l2_source_mac[5]);\ -+ MC_EXT_OP(ext, 5, 8, 8, uint8_t, key->mask.l2_source_mac[4]);\ -+ MC_EXT_OP(ext, 5, 16, 8, uint8_t, key->mask.l2_source_mac[3]);\ -+ MC_EXT_OP(ext, 5, 24, 8, uint8_t, key->mask.l2_source_mac[2]);\ -+ MC_EXT_OP(ext, 5, 32, 8, uint8_t, key->mask.l2_source_mac[1]);\ -+ MC_EXT_OP(ext, 5, 40, 8, uint8_t, key->mask.l2_source_mac[0]);\ -+ MC_EXT_OP(ext, 5, 48, 16, uint16_t, key->mask.l2_vlan_id);\ -+ MC_EXT_OP(ext, 6, 0, 32, uint32_t, key->mask.l3_dest_ip);\ -+ MC_EXT_OP(ext, 6, 32, 32, uint32_t, key->mask.l3_source_ip);\ -+ MC_EXT_OP(ext, 7, 0, 16, uint16_t, key->mask.l4_dest_port);\ -+ MC_EXT_OP(ext, 7, 16, 16, uint16_t, key->mask.l4_source_port);\ -+ MC_EXT_OP(ext, 7, 32, 16, uint16_t, key->mask.l2_ether_type);\ -+ MC_EXT_OP(ext, 7, 48, 8, uint8_t, key->mask.l2_pcp_dei);\ -+ MC_EXT_OP(ext, 7, 56, 8, uint8_t, key->mask.l3_dscp);\ -+ MC_EXT_OP(ext, 8, 0, 8, uint8_t, key->match.l3_protocol);\ -+ MC_EXT_OP(ext, 8, 8, 8, uint8_t, key->mask.l3_protocol);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_ACL_ADD_ENTRY(cmd, acl_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, acl_id);\ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->result.if_id);\ -+ MC_CMD_OP(cmd, 0, 32, 32, int, cfg->precedence);\ -+ MC_CMD_OP(cmd, 1, 0, 4, enum dpsw_acl_action, cfg->result.action);\ -+ MC_CMD_OP(cmd, 6, 0, 64, uint64_t, cfg->key_iova); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_ACL_REMOVE_ENTRY(cmd, acl_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, acl_id);\ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->result.if_id);\ -+ MC_CMD_OP(cmd, 0, 32, 32, int, cfg->precedence);\ -+ MC_CMD_OP(cmd, 1, 0, 4, enum dpsw_acl_action, cfg->result.action);\ -+ MC_CMD_OP(cmd, 6, 0, 64, uint64_t, cfg->key_iova); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_ACL_ADD_IF(cmd, acl_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, acl_id);\ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_ACL_REMOVE_IF(cmd, acl_id, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, acl_id);\ -+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->num_ifs); \ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_ACL_GET_ATTR(cmd, acl_id) \ -+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, acl_id) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_ACL_GET_ATTR(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->max_entries);\ -+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->num_entries);\ -+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, attr->num_ifs);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_RSP_CTRL_IF_GET_ATTR(cmd, attr) \ -+do { \ -+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->rx_fqid);\ -+ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, attr->rx_err_fqid);\ -+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->tx_err_conf_fqid);\ -+} while (0) -+ -+/* cmd, param, offset, width, type, arg_name */ -+#define DPSW_CMD_CTRL_IF_SET_POOLS(cmd, cfg) \ -+do { \ -+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \ -+ MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \ -+ MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \ -+ MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\ -+ MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \ -+ MC_CMD_OP(cmd, 4, 48, 16, uint16_t, cfg->pools[1].buffer_size);\ -+ MC_CMD_OP(cmd, 1, 32, 32, int, cfg->pools[2].dpbp_id); \ -+ MC_CMD_OP(cmd, 5, 0, 16, uint16_t, cfg->pools[2].buffer_size);\ -+ MC_CMD_OP(cmd, 2, 0, 32, int, cfg->pools[3].dpbp_id); \ -+ MC_CMD_OP(cmd, 5, 16, 16, uint16_t, cfg->pools[3].buffer_size);\ -+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->pools[4].dpbp_id); \ -+ MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->pools[4].buffer_size);\ -+ MC_CMD_OP(cmd, 3, 0, 32, int, cfg->pools[5].dpbp_id); \ -+ MC_CMD_OP(cmd, 5, 48, 16, uint16_t, cfg->pools[5].buffer_size);\ -+ MC_CMD_OP(cmd, 3, 32, 32, int, cfg->pools[6].dpbp_id); \ -+ MC_CMD_OP(cmd, 6, 0, 16, uint16_t, cfg->pools[6].buffer_size);\ -+ MC_CMD_OP(cmd, 4, 0, 32, int, cfg->pools[7].dpbp_id); \ -+ MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\ -+} while (0) -+ -+#endif /* __FSL_DPSW_CMD_H */ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethsw/dpsw.c -@@ -0,0 +1,1639 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include "../../fsl-mc/include/mc-sys.h" -+#include "../../fsl-mc/include/mc-cmd.h" -+#include "dpsw.h" -+#include "dpsw-cmd.h" -+ -+/* internal functions */ -+static void build_if_id_bitmap(const uint16_t *if_id, -+ const uint16_t num_ifs, -+ struct mc_command *cmd, -+ int start_param) -+{ -+ int i; -+ -+ for (i = 0; (i < num_ifs) && (i < DPSW_MAX_IF); i++) -+ cmd->params[start_param + (if_id[i] / 64)] |= mc_enc( -+ (if_id[i] % 64), 1, 1); -+} -+ -+static int read_if_id_bitmap(uint16_t *if_id, -+ uint16_t *num_ifs, -+ struct mc_command *cmd, -+ int start_param) -+{ -+ int bitmap[DPSW_MAX_IF] = { 0 }; -+ int i, j = 0; -+ int count = 0; -+ -+ for (i = 0; i < DPSW_MAX_IF; i++) { -+ bitmap[i] = (int)mc_dec(cmd->params[start_param + i / 64], -+ i % 64, 1); -+ count += bitmap[i]; -+ } -+ -+ *num_ifs = (uint16_t)count; -+ -+ for (i = 0; (i < DPSW_MAX_IF) && (j < count); i++) { -+ if (bitmap[i]) { -+ if_id[j] = (uint16_t)i; -+ j++; -+ } -+ } -+ -+ return 0; -+} -+ -+/* DPSW APIs */ -+int dpsw_open(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ int dpsw_id, -+ uint16_t *token) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_OPEN, -+ cmd_flags, -+ 0); -+ DPSW_CMD_OPEN(cmd, dpsw_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header); -+ -+ return 0; -+} -+ -+int dpsw_close(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CLOSE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_create(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ const struct dpsw_cfg *cfg, -+ uint16_t *token) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CREATE, -+ cmd_flags, -+ 0); -+ DPSW_CMD_CREATE(cmd, cfg); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header); -+ -+ return 0; -+} -+ -+int dpsw_destroy(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_DESTROY, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ENABLE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_DISABLE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_is_enabled(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IS_ENABLED, cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_IS_ENABLED(cmd, *en); -+ -+ return 0; -+} -+ -+int dpsw_reset(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_RESET, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_set_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ struct dpsw_irq_cfg *irq_cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_IRQ, -+ cmd_flags, -+ token); -+ DPSW_CMD_SET_IRQ(cmd, irq_index, irq_cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_get_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ int *type, -+ struct dpsw_irq_cfg *irq_cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_IRQ, -+ cmd_flags, -+ token); -+ DPSW_CMD_GET_IRQ(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_GET_IRQ(cmd, *type, irq_cfg); -+ -+ return 0; -+} -+ -+int dpsw_set_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ DPSW_CMD_SET_IRQ_ENABLE(cmd, irq_index, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_get_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t *en) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_IRQ_ENABLE, -+ cmd_flags, -+ token); -+ DPSW_CMD_GET_IRQ_ENABLE(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_GET_IRQ_ENABLE(cmd, *en); -+ -+ return 0; -+} -+ -+int dpsw_set_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t mask) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_IRQ_MASK, -+ cmd_flags, -+ token); -+ DPSW_CMD_SET_IRQ_MASK(cmd, irq_index, mask); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_get_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *mask) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_IRQ_MASK, -+ cmd_flags, -+ token); -+ DPSW_CMD_GET_IRQ_MASK(cmd, irq_index); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_GET_IRQ_MASK(cmd, *mask); -+ -+ return 0; -+} -+ -+int dpsw_get_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *status) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_IRQ_STATUS, -+ cmd_flags, -+ token); -+ DPSW_CMD_GET_IRQ_STATUS(cmd, irq_index, *status); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_GET_IRQ_STATUS(cmd, *status); -+ -+ return 0; -+} -+ -+int dpsw_clear_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t status) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CLEAR_IRQ_STATUS, -+ cmd_flags, -+ token); -+ DPSW_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpsw_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_ATTR, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_GET_ATTR(cmd, attr); -+ -+ return 0; -+} -+ -+int dpsw_set_reflection_if(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_REFLECTION_IF, -+ cmd_flags, -+ token); -+ DPSW_CMD_SET_REFLECTION_IF(cmd, if_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_set_link_cfg(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpsw_link_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_LINK_CFG, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_LINK_CFG(cmd, if_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_get_link_state(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpsw_link_state *state) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_LINK_STATE, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_GET_LINK_STATE(cmd, if_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_IF_GET_LINK_STATE(cmd, state); -+ -+ return 0; -+} -+ -+int dpsw_if_set_flooding(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ int en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_FLOODING, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_FLOODING(cmd, if_id, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_set_broadcast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ int en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_BROADCAST, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_FLOODING(cmd, if_id, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_set_multicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ int en) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_MULTICAST, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_FLOODING(cmd, if_id, en); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_set_tci(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_tci_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_TCI, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_TCI(cmd, if_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_get_tci(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpsw_tci_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err = 0; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_TCI, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_GET_TCI(cmd, if_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_IF_GET_TCI(cmd, cfg); -+ -+ return 0; -+} -+ -+int dpsw_if_set_stp(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_stp_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_STP, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_STP(cmd, if_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_set_accepted_frames(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_accepted_frames_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_ACCEPTED_FRAMES, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_ACCEPTED_FRAMES(cmd, if_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_set_accept_all_vlan(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ int accept_all) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_IF_ACCEPT_ALL_VLAN, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_ACCEPT_ALL_VLAN(cmd, if_id, accept_all); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_get_counter(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ enum dpsw_counter type, -+ uint64_t *counter) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_COUNTER, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_GET_COUNTER(cmd, if_id, type); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_IF_GET_COUNTER(cmd, *counter); -+ -+ return 0; -+} -+ -+int dpsw_if_set_counter(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ enum dpsw_counter type, -+ uint64_t counter) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_COUNTER, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_COUNTER(cmd, if_id, type, counter); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_set_tx_selection(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_tx_selection_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_TX_SELECTION, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_TX_SELECTION(cmd, if_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_add_reflection(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_reflection_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_ADD_REFLECTION, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_ADD_REFLECTION(cmd, if_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_remove_reflection(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_reflection_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_REMOVE_REFLECTION, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_REMOVE_REFLECTION(cmd, if_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_set_flooding_metering(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_metering_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_FLOODING_METERING, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_FLOODING_METERING(cmd, if_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_set_metering(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ uint8_t tc_id, -+ const struct dpsw_metering_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_METERING, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_METERING(cmd, if_id, tc_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+void dpsw_prepare_early_drop(const struct dpsw_early_drop_cfg *cfg, -+ uint8_t *early_drop_buf) -+{ -+ uint64_t *ext_params = (uint64_t *)early_drop_buf; -+ -+ DPSW_PREP_EARLY_DROP(ext_params, cfg); -+} -+ -+int dpsw_if_set_early_drop(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ uint8_t tc_id, -+ uint64_t early_drop_iova) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_EARLY_DROP, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_EARLY_DROP(cmd, if_id, tc_id, early_drop_iova); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_add_custom_tpid(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpsw_custom_tpid_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ADD_CUSTOM_TPID, -+ cmd_flags, -+ token); -+ DPSW_CMD_ADD_CUSTOM_TPID(cmd, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_remove_custom_tpid(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpsw_custom_tpid_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_REMOVE_CUSTOM_TPID, -+ cmd_flags, -+ token); -+ DPSW_CMD_REMOVE_CUSTOM_TPID(cmd, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_ENABLE, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_ENABLE(cmd, if_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_DISABLE, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_DISABLE(cmd, if_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpsw_if_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_ATTR, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_GET_ATTR(cmd, if_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_IF_GET_ATTR(cmd, attr); -+ -+ return 0; -+} -+ -+int dpsw_if_set_max_frame_length(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ uint16_t frame_length) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_SET_MAX_FRAME_LENGTH(cmd, if_id, frame_length); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_if_get_max_frame_length(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ uint16_t *frame_length) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_MAX_FRAME_LENGTH, -+ cmd_flags, -+ token); -+ DPSW_CMD_IF_GET_MAX_FRAME_LENGTH(cmd, if_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ DPSW_RSP_IF_GET_MAX_FRAME_LENGTH(cmd, *frame_length); -+ -+ return 0; -+} -+ -+int dpsw_vlan_add(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD, -+ cmd_flags, -+ token); -+ DPSW_CMD_VLAN_ADD(cmd, vlan_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_vlan_add_if(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_if_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1); -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD_IF, -+ cmd_flags, -+ token); -+ DPSW_CMD_VLAN_ADD_IF(cmd, vlan_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_vlan_add_if_untagged(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_if_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1); -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD_IF_UNTAGGED, -+ cmd_flags, -+ token); -+ DPSW_CMD_VLAN_ADD_IF_UNTAGGED(cmd, vlan_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_vlan_add_if_flooding(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_if_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1); -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD_IF_FLOODING, -+ cmd_flags, -+ token); -+ DPSW_CMD_VLAN_ADD_IF_FLOODING(cmd, vlan_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_vlan_remove_if(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_if_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1); -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE_IF, -+ cmd_flags, -+ token); -+ DPSW_CMD_VLAN_REMOVE_IF(cmd, vlan_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_vlan_remove_if_untagged(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_if_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1); -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED, -+ cmd_flags, -+ token); -+ DPSW_CMD_VLAN_REMOVE_IF_UNTAGGED(cmd, vlan_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_vlan_remove_if_flooding(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_if_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1); -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE_IF_FLOODING, -+ cmd_flags, -+ token); -+ DPSW_CMD_VLAN_REMOVE_IF_FLOODING(cmd, vlan_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_vlan_remove(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE, -+ cmd_flags, -+ token); -+ DPSW_CMD_VLAN_REMOVE(cmd, vlan_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_vlan_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ struct dpsw_vlan_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_GET_ATTRIBUTES, -+ cmd_flags, -+ token); -+ DPSW_CMD_VLAN_GET_ATTR(cmd, vlan_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_VLAN_GET_ATTR(cmd, attr); -+ -+ return 0; -+} -+ -+int dpsw_vlan_get_if(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ struct dpsw_vlan_if_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_GET_IF, -+ cmd_flags, -+ token); -+ DPSW_CMD_VLAN_GET_IF(cmd, vlan_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_VLAN_GET_IF(cmd, cfg); -+ read_if_id_bitmap(cfg->if_id, &cfg->num_ifs, &cmd, 1); -+ -+ return 0; -+} -+ -+int dpsw_vlan_get_if_flooding(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ struct dpsw_vlan_if_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_GET_IF_FLOODING, -+ cmd_flags, -+ token); -+ DPSW_CMD_VLAN_GET_IF_FLOODING(cmd, vlan_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_VLAN_GET_IF_FLOODING(cmd, cfg); -+ read_if_id_bitmap(cfg->if_id, &cfg->num_ifs, &cmd, 1); -+ -+ return 0; -+} -+ -+int dpsw_vlan_get_if_untagged(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ struct dpsw_vlan_if_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_GET_IF_UNTAGGED, -+ cmd_flags, -+ token); -+ DPSW_CMD_VLAN_GET_IF_UNTAGGED(cmd, vlan_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_VLAN_GET_IF(cmd, cfg); -+ read_if_id_bitmap(cfg->if_id, &cfg->num_ifs, &cmd, 1); -+ -+ return 0; -+} -+ -+int dpsw_fdb_add(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *fdb_id, -+ const struct dpsw_fdb_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_ADD, -+ cmd_flags, -+ token); -+ DPSW_CMD_FDB_ADD(cmd, cfg); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_FDB_ADD(cmd, *fdb_id); -+ -+ return 0; -+} -+ -+int dpsw_fdb_remove(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_REMOVE, -+ cmd_flags, -+ token); -+ DPSW_CMD_FDB_REMOVE(cmd, fdb_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_fdb_add_unicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ const struct dpsw_fdb_unicast_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_ADD_UNICAST, -+ cmd_flags, -+ token); -+ DPSW_CMD_FDB_ADD_UNICAST(cmd, fdb_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_fdb_get_unicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ struct dpsw_fdb_unicast_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_GET_UNICAST, -+ cmd_flags, -+ token); -+ DPSW_CMD_FDB_GET_UNICAST(cmd, fdb_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_FDB_GET_UNICAST(cmd, cfg); -+ -+ return 0; -+} -+ -+int dpsw_fdb_remove_unicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ const struct dpsw_fdb_unicast_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_REMOVE_UNICAST, -+ cmd_flags, -+ token); -+ DPSW_CMD_FDB_REMOVE_UNICAST(cmd, fdb_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_fdb_add_multicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ const struct dpsw_fdb_multicast_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 2); -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_ADD_MULTICAST, -+ cmd_flags, -+ token); -+ DPSW_CMD_FDB_ADD_MULTICAST(cmd, fdb_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_fdb_get_multicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ struct dpsw_fdb_multicast_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_GET_MULTICAST, -+ cmd_flags, -+ token); -+ DPSW_CMD_FDB_GET_MULTICAST(cmd, fdb_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_FDB_GET_MULTICAST(cmd, cfg); -+ read_if_id_bitmap(cfg->if_id, &cfg->num_ifs, &cmd, 2); -+ -+ return 0; -+} -+ -+int dpsw_fdb_remove_multicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ const struct dpsw_fdb_multicast_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 2); -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_REMOVE_MULTICAST, -+ cmd_flags, -+ token); -+ DPSW_CMD_FDB_REMOVE_MULTICAST(cmd, fdb_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_fdb_set_learning_mode(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ enum dpsw_fdb_learning_mode mode) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_SET_LEARNING_MODE, -+ cmd_flags, -+ token); -+ DPSW_CMD_FDB_SET_LEARNING_MODE(cmd, fdb_id, mode); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_fdb_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ struct dpsw_fdb_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_GET_ATTR, -+ cmd_flags, -+ token); -+ DPSW_CMD_FDB_GET_ATTR(cmd, fdb_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_FDB_GET_ATTR(cmd, attr); -+ -+ return 0; -+} -+ -+int dpsw_acl_add(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *acl_id, -+ const struct dpsw_acl_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_ADD, -+ cmd_flags, -+ token); -+ DPSW_CMD_ACL_ADD(cmd, cfg); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_ACL_ADD(cmd, *acl_id); -+ -+ return 0; -+} -+ -+int dpsw_acl_remove(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t acl_id) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_REMOVE, -+ cmd_flags, -+ token); -+ DPSW_CMD_ACL_REMOVE(cmd, acl_id); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+void dpsw_acl_prepare_entry_cfg(const struct dpsw_acl_key *key, -+ uint8_t *entry_cfg_buf) -+{ -+ uint64_t *ext_params = (uint64_t *)entry_cfg_buf; -+ -+ DPSW_PREP_ACL_ENTRY(ext_params, key); -+} -+ -+int dpsw_acl_add_entry(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t acl_id, -+ const struct dpsw_acl_entry_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_ADD_ENTRY, -+ cmd_flags, -+ token); -+ DPSW_CMD_ACL_ADD_ENTRY(cmd, acl_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_acl_remove_entry(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t acl_id, -+ const struct dpsw_acl_entry_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_REMOVE_ENTRY, -+ cmd_flags, -+ token); -+ DPSW_CMD_ACL_REMOVE_ENTRY(cmd, acl_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_acl_add_if(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t acl_id, -+ const struct dpsw_acl_if_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1); -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_ADD_IF, -+ cmd_flags, -+ token); -+ DPSW_CMD_ACL_ADD_IF(cmd, acl_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_acl_remove_if(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t acl_id, -+ const struct dpsw_acl_if_cfg *cfg) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ build_if_id_bitmap(cfg->if_id, cfg->num_ifs, &cmd, 1); -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_REMOVE_IF, -+ cmd_flags, -+ token); -+ DPSW_CMD_ACL_REMOVE_IF(cmd, acl_id, cfg); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_acl_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t acl_id, -+ struct dpsw_acl_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_ACL_GET_ATTR, -+ cmd_flags, -+ token); -+ DPSW_CMD_ACL_GET_ATTR(cmd, acl_id); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_ACL_GET_ATTR(cmd, attr); -+ -+ return 0; -+} -+ -+int dpsw_ctrl_if_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpsw_ctrl_if_attr *attr) -+{ -+ struct mc_command cmd = { 0 }; -+ int err; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CTRL_IF_GET_ATTR, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ err = mc_send_command(mc_io, &cmd); -+ if (err) -+ return err; -+ -+ /* retrieve response parameters */ -+ DPSW_RSP_CTRL_IF_GET_ATTR(cmd, attr); -+ -+ return 0; -+} -+ -+int dpsw_ctrl_if_set_pools(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpsw_ctrl_if_pools_cfg *pools) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CTRL_IF_SET_POOLS, -+ cmd_flags, -+ token); -+ DPSW_CMD_CTRL_IF_SET_POOLS(cmd, pools); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+int dpsw_ctrl_if_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CTRL_IF_ENABLE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} -+ -+/** -+* @brief Function disables control interface -+* @mc_io: Pointer to MC portal's I/O object -+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+* @token: Token of DPSW object -+* -+* Return: '0' on Success; Error code otherwise. -+*/ -+int dpsw_ctrl_if_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token) -+{ -+ struct mc_command cmd = { 0 }; -+ -+ /* prepare command */ -+ cmd.header = mc_encode_cmd_header(DPSW_CMDID_CTRL_IF_DISABLE, -+ cmd_flags, -+ token); -+ -+ /* send command to mc*/ -+ return mc_send_command(mc_io, &cmd); -+} ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethsw/dpsw.h -@@ -0,0 +1,2164 @@ -+/* Copyright 2013-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of the above-listed copyright holders nor the -+ * names of any contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+#ifndef __FSL_DPSW_H -+#define __FSL_DPSW_H -+ -+#include "../../fsl-mc/include/net.h" -+ -+/* Data Path L2-Switch API -+ * Contains API for handling DPSW topology and functionality -+ */ -+ -+struct fsl_mc_io; -+ -+/** -+ * DPSW general definitions -+ */ -+ -+/** -+ * Maximum number of traffic class priorities -+ */ -+#define DPSW_MAX_PRIORITIES 8 -+/** -+ * Maximum number of interfaces -+ */ -+#define DPSW_MAX_IF 64 -+ -+/** -+ * dpsw_open() - Open a control session for the specified object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @dpsw_id: DPSW unique ID -+ * @token: Returned token; use in subsequent API calls -+ * -+ * This function can be used to open a control session for an -+ * already created object; an object may have been declared in -+ * the DPL or by calling the dpsw_create() function. -+ * This function returns a unique authentication token, -+ * associated with the specific object ID and the specific MC -+ * portal; this token must be used in all subsequent commands for -+ * this specific object -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_open(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ int dpsw_id, -+ uint16_t *token); -+ -+/** -+ * dpsw_close() - Close the control session of the object -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * -+ * After this function is called, no further operations are -+ * allowed on the object without opening a new control session. -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_close(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * DPSW options -+ */ -+ -+/** -+ * Disable flooding -+ */ -+#define DPSW_OPT_FLOODING_DIS 0x0000000000000001ULL -+/** -+ * Disable Multicast -+ */ -+#define DPSW_OPT_MULTICAST_DIS 0x0000000000000004ULL -+/** -+ * Support control interface -+ */ -+#define DPSW_OPT_CTRL_IF_DIS 0x0000000000000010ULL -+/** -+ * Disable flooding metering -+ */ -+#define DPSW_OPT_FLOODING_METERING_DIS 0x0000000000000020ULL -+/** -+ * Enable metering -+ */ -+#define DPSW_OPT_METERING_EN 0x0000000000000040ULL -+ -+/** -+ * enum dpsw_component_type - component type of a bridge -+ * @DPSW_COMPONENT_TYPE_C_VLAN: A C-VLAN component of an -+ * enterprise VLAN bridge or of a Provider Bridge used -+ * to process C-tagged frames -+ * @DPSW_COMPONENT_TYPE_S_VLAN: An S-VLAN component of a -+ * Provider Bridge -+ * -+ */ -+enum dpsw_component_type { -+ DPSW_COMPONENT_TYPE_C_VLAN = 0, -+ DPSW_COMPONENT_TYPE_S_VLAN -+}; -+ -+/** -+ * struct dpsw_cfg - DPSW configuration -+ * @num_ifs: Number of external and internal interfaces -+ * @adv: Advanced parameters; default is all zeros; -+ * use this structure to change default settings -+ */ -+struct dpsw_cfg { -+ uint16_t num_ifs; -+ /** -+ * struct adv - Advanced parameters -+ * @options: Enable/Disable DPSW features (bitmap) -+ * @max_vlans: Maximum Number of VLAN's; 0 - indicates default 16 -+ * @max_meters_per_if: Number of meters per interface -+ * @max_fdbs: Maximum Number of FDB's; 0 - indicates default 16 -+ * @max_fdb_entries: Number of FDB entries for default FDB table; -+ * 0 - indicates default 1024 entries. -+ * @fdb_aging_time: Default FDB aging time for default FDB table; -+ * 0 - indicates default 300 seconds -+ * @max_fdb_mc_groups: Number of multicast groups in each FDB table; -+ * 0 - indicates default 32 -+ * @component_type: Indicates the component type of this bridge -+ */ -+ struct { -+ uint64_t options; -+ uint16_t max_vlans; -+ uint8_t max_meters_per_if; -+ uint8_t max_fdbs; -+ uint16_t max_fdb_entries; -+ uint16_t fdb_aging_time; -+ uint16_t max_fdb_mc_groups; -+ enum dpsw_component_type component_type; -+ } adv; -+}; -+ -+/** -+ * dpsw_create() - Create the DPSW object. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @cfg: Configuration structure -+ * @token: Returned token; use in subsequent API calls -+ * -+ * Create the DPSW object, allocate required resources and -+ * perform required initialization. -+ * -+ * The object can be created either by declaring it in the -+ * DPL file, or by calling this function. -+ * -+ * This function returns a unique authentication token, -+ * associated with the specific object ID and the specific MC -+ * portal; this token must be used in all subsequent calls to -+ * this specific object. For objects that are created using the -+ * DPL file, call dpsw_open() function to get an authentication -+ * token first -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_create(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ const struct dpsw_cfg *cfg, -+ uint16_t *token); -+ -+/** -+ * dpsw_destroy() - Destroy the DPSW object and release all its resources. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpsw_destroy(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpsw_enable() - Enable DPSW functionality -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpsw_disable() - Disable DPSW functionality -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * dpsw_is_enabled() - Check if the DPSW is enabled -+ * -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @en: Returns '1' if object is enabled; '0' otherwise -+ * -+ * Return: '0' on Success; Error code otherwise -+ */ -+int dpsw_is_enabled(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ int *en); -+ -+/** -+ * dpsw_reset() - Reset the DPSW, returns the object to initial state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_reset(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+ * DPSW IRQ Index and Events -+ */ -+ -+#define DPSW_IRQ_INDEX_IF 0x0000 -+#define DPSW_IRQ_INDEX_L2SW 0x0001 -+ -+/** -+ * IRQ event - Indicates that the link state changed -+ */ -+#define DPSW_IRQ_EVENT_LINK_CHANGED 0x0001 -+ -+/** -+ * struct dpsw_irq_cfg - IRQ configuration -+ * @addr: Address that must be written to signal a message-based interrupt -+ * @val: Value to write into irq_addr address -+ * @irq_num: A user defined number associated with this IRQ -+ */ -+struct dpsw_irq_cfg { -+ uint64_t addr; -+ uint32_t val; -+ int irq_num; -+}; -+ -+/** -+ * dpsw_set_irq() - Set IRQ information for the DPSW to trigger an interrupt. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @irq_index: Identifies the interrupt index to configure -+ * @irq_cfg: IRQ configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_set_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ struct dpsw_irq_cfg *irq_cfg); -+ -+/** -+ * dpsw_get_irq() - Get IRQ information from the DPSW -+ * -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @irq_index: The interrupt index to configure -+ * @type: Interrupt type: 0 represents message interrupt -+ * type (both irq_addr and irq_val are valid) -+ * @irq_cfg: IRQ attributes -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_get_irq(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ int *type, -+ struct dpsw_irq_cfg *irq_cfg); -+ -+/** -+ * dpsw_set_irq_enable() - Set overall interrupt state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCI object -+ * @irq_index: The interrupt index to configure -+ * @en: Interrupt state - enable = 1, disable = 0 -+ * -+ * Allows GPP software to control when interrupts are generated. -+ * Each interrupt can have up to 32 causes. The enable/disable control's the -+ * overall interrupt state. if the interrupt is disabled no causes will cause -+ * an interrupt -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_set_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t en); -+ -+/** -+ * dpsw_get_irq_enable() - Get overall interrupt state -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @irq_index: The interrupt index to configure -+ * @en: Returned Interrupt state - enable = 1, disable = 0 -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_get_irq_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint8_t *en); -+ -+/** -+ * dpsw_set_irq_mask() - Set interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCI object -+ * @irq_index: The interrupt index to configure -+ * @mask: event mask to trigger interrupt; -+ * each bit: -+ * 0 = ignore event -+ * 1 = consider event for asserting IRQ -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_set_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t mask); -+ -+/** -+ * dpsw_get_irq_mask() - Get interrupt mask. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @irq_index: The interrupt index to configure -+ * @mask: Returned event mask to trigger interrupt -+ * -+ * Every interrupt can have up to 32 causes and the interrupt model supports -+ * masking/unmasking each cause independently -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_get_irq_mask(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *mask); -+ -+/** -+ * dpsw_get_irq_status() - Get the current status of any pending interrupts -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @irq_index: The interrupt index to configure -+ * @status: Returned interrupts status - one bit per cause: -+ * 0 = no interrupt pending -+ * 1 = interrupt pending -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_get_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t *status); -+ -+/** -+ * dpsw_clear_irq_status() - Clear a pending interrupt's status -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPCI object -+ * @irq_index: The interrupt index to configure -+ * @status: bits to clear (W1C) - one bit per cause: -+ * 0 = don't change -+ * 1 = clear status bit -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_clear_irq_status(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint8_t irq_index, -+ uint32_t status); -+/** -+ * struct dpsw_attr - Structure representing DPSW attributes -+ * @id: DPSW object ID -+ * @version: DPSW version -+ * @options: Enable/Disable DPSW features -+ * @max_vlans: Maximum Number of VLANs -+ * @max_meters_per_if: Number of meters per interface -+ * @max_fdbs: Maximum Number of FDBs -+ * @max_fdb_entries: Number of FDB entries for default FDB table; -+ * 0 - indicates default 1024 entries. -+ * @fdb_aging_time: Default FDB aging time for default FDB table; -+ * 0 - indicates default 300 seconds -+ * @max_fdb_mc_groups: Number of multicast groups in each FDB table; -+ * 0 - indicates default 32 -+ * @mem_size: DPSW frame storage memory size -+ * @num_ifs: Number of interfaces -+ * @num_vlans: Current number of VLANs -+ * @num_fdbs: Current number of FDBs -+ * @component_type: Component type of this bridge -+ */ -+struct dpsw_attr { -+ int id; -+ /** -+ * struct version - DPSW version -+ * @major: DPSW major version -+ * @minor: DPSW minor version -+ */ -+ struct { -+ uint16_t major; -+ uint16_t minor; -+ } version; -+ uint64_t options; -+ uint16_t max_vlans; -+ uint8_t max_meters_per_if; -+ uint8_t max_fdbs; -+ uint16_t max_fdb_entries; -+ uint16_t fdb_aging_time; -+ uint16_t max_fdb_mc_groups; -+ uint16_t num_ifs; -+ uint16_t mem_size; -+ uint16_t num_vlans; -+ uint8_t num_fdbs; -+ enum dpsw_component_type component_type; -+}; -+ -+/** -+ * dpsw_get_attributes() - Retrieve DPSW attributes -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @attr: Returned DPSW attributes -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpsw_attr *attr); -+ -+/** -+ * dpsw_set_reflection_if() - Set target interface for reflected interfaces. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Id -+ * -+ * Only one reflection receive interface is allowed per switch -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_set_reflection_if(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id); -+ -+/** -+ * enum dpsw_action - Action selection for special/control frames -+ * @DPSW_ACTION_DROP: Drop frame -+ * @DPSW_ACTION_REDIRECT: Redirect frame to control port -+ */ -+enum dpsw_action { -+ DPSW_ACTION_DROP = 0, -+ DPSW_ACTION_REDIRECT = 1 -+}; -+ -+/** -+ * Enable auto-negotiation -+ */ -+#define DPSW_LINK_OPT_AUTONEG 0x0000000000000001ULL -+/** -+ * Enable half-duplex mode -+ */ -+#define DPSW_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL -+/** -+ * Enable pause frames -+ */ -+#define DPSW_LINK_OPT_PAUSE 0x0000000000000004ULL -+/** -+ * Enable a-symmetric pause frames -+ */ -+#define DPSW_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL -+ -+/** -+ * struct dpsw_link_cfg - Structure representing DPSW link configuration -+ * @rate: Rate -+ * @options: Mask of available options; use 'DPSW_LINK_OPT_' values -+ */ -+struct dpsw_link_cfg { -+ uint32_t rate; -+ uint64_t options; -+}; -+ -+/** -+ * dpsw_if_set_link_cfg() - set the link configuration. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: interface id -+ * @cfg: Link configuration -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_set_link_cfg(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpsw_link_cfg *cfg); -+/** -+ * struct dpsw_link_state - Structure representing DPSW link state -+ * @rate: Rate -+ * @options: Mask of available options; use 'DPSW_LINK_OPT_' values -+ * @up: 0 - covers two cases: down and disconnected, 1 - up -+ */ -+struct dpsw_link_state { -+ uint32_t rate; -+ uint64_t options; -+ int up; -+}; -+ -+/** -+ * dpsw_if_get_link_state - Return the link state -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: interface id -+ * @state: link state 1 - linkup, 0 - link down or disconnected -+ * -+ * @returns '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_get_link_state(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpsw_link_state *state); -+ -+/** -+ * dpsw_if_set_flooding() - Enable Disable flooding for particular interface -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @en: 1 - enable, 0 - disable -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_set_flooding(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ int en); -+ -+/** -+ * dpsw_if_set_broadcast() - Enable/disable broadcast for particular interface -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @en: 1 - enable, 0 - disable -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_set_broadcast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ int en); -+ -+/** -+ * dpsw_if_set_multicast() - Enable/disable multicast for particular interface -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @en: 1 - enable, 0 - disable -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_set_multicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ int en); -+ -+/** -+ * struct dpsw_tci_cfg - Tag Contorl Information (TCI) configuration -+ * @pcp: Priority Code Point (PCP): a 3-bit field which refers -+ * to the IEEE 802.1p priority -+ * @dei: Drop Eligible Indicator (DEI): a 1-bit field. May be used -+ * separately or in conjunction with PCP to indicate frames -+ * eligible to be dropped in the presence of congestion -+ * @vlan_id: VLAN Identifier (VID): a 12-bit field specifying the VLAN -+ * to which the frame belongs. The hexadecimal values -+ * of 0x000 and 0xFFF are reserved; -+ * all other values may be used as VLAN identifiers, -+ * allowing up to 4,094 VLANs -+ */ -+struct dpsw_tci_cfg { -+ uint8_t pcp; -+ uint8_t dei; -+ uint16_t vlan_id; -+}; -+ -+/** -+ * dpsw_if_set_tci() - Set default VLAN Tag Control Information (TCI) -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @cfg: Tag Control Information Configuration -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_set_tci(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_tci_cfg *cfg); -+ -+/** -+ * dpsw_if_get_tci() - Get default VLAN Tag Control Information (TCI) -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @cfg: Tag Control Information Configuration -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_get_tci(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpsw_tci_cfg *cfg); -+ -+/** -+ * enum dpsw_stp_state - Spanning Tree Protocol (STP) states -+ * @DPSW_STP_STATE_BLOCKING: Blocking state -+ * @DPSW_STP_STATE_LISTENING: Listening state -+ * @DPSW_STP_STATE_LEARNING: Learning state -+ * @DPSW_STP_STATE_FORWARDING: Forwarding state -+ * -+ */ -+enum dpsw_stp_state { -+ DPSW_STP_STATE_BLOCKING = 0, -+ DPSW_STP_STATE_LISTENING = 1, -+ DPSW_STP_STATE_LEARNING = 2, -+ DPSW_STP_STATE_FORWARDING = 3 -+}; -+ -+/** -+ * struct dpsw_stp_cfg - Spanning Tree Protocol (STP) Configuration -+ * @vlan_id: VLAN ID STP state -+ * @state: STP state -+ */ -+struct dpsw_stp_cfg { -+ uint16_t vlan_id; -+ enum dpsw_stp_state state; -+}; -+ -+/** -+ * dpsw_if_set_stp() - Function sets Spanning Tree Protocol (STP) state. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @cfg: STP State configuration parameters -+ * -+ * The following STP states are supported - -+ * blocking, listening, learning, forwarding and disabled. -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_set_stp(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_stp_cfg *cfg); -+ -+/** -+ * enum dpsw_accepted_frames - Types of frames to accept -+ * @DPSW_ADMIT_ALL: The device accepts VLAN tagged, untagged and -+ * priority tagged frames -+ * @DPSW_ADMIT_ONLY_VLAN_TAGGED: The device discards untagged frames or -+ * Priority-Tagged frames received on this interface. -+ * -+ */ -+enum dpsw_accepted_frames { -+ DPSW_ADMIT_ALL = 1, -+ DPSW_ADMIT_ONLY_VLAN_TAGGED = 3 -+}; -+ -+/** -+ * struct dpsw_accepted_frames_cfg - Types of frames to accept configuration -+ * @type: Defines ingress accepted frames -+ * @unaccept_act: When a frame is not accepted, it may be discarded or -+ * redirected to control interface depending on this mode -+ */ -+struct dpsw_accepted_frames_cfg { -+ enum dpsw_accepted_frames type; -+ enum dpsw_action unaccept_act; -+}; -+ -+/** -+ * dpsw_if_set_accepted_frames() -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @cfg: Frame types configuration -+ * -+ * When is admit_only_vlan_tagged- the device will discard untagged -+ * frames or Priority-Tagged frames received on this interface. -+ * When admit_only_untagged- untagged frames or Priority-Tagged -+ * frames received on this interface will be accepted and assigned -+ * to a VID based on the PVID and VID Set for this interface. -+ * When admit_all - the device will accept VLAN tagged, untagged -+ * and priority tagged frames. -+ * The default is admit_all -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_set_accepted_frames(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_accepted_frames_cfg *cfg); -+ -+/** -+ * dpsw_if_set_accept_all_vlan() -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @accept_all: Accept or drop frames having different VLAN -+ * -+ * When this is accept (FALSE), the device will discard incoming -+ * frames for VLANs that do not include this interface in its -+ * Member set. When accept (TRUE), the interface will accept all incoming frames -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_set_accept_all_vlan(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ int accept_all); -+ -+/** -+ * enum dpsw_counter - Counters types -+ * @DPSW_CNT_ING_FRAME: Counts ingress frames -+ * @DPSW_CNT_ING_BYTE: Counts ingress bytes -+ * @DPSW_CNT_ING_FLTR_FRAME: Counts filtered ingress frames -+ * @DPSW_CNT_ING_FRAME_DISCARD: Counts discarded ingress frame -+ * @DPSW_CNT_ING_MCAST_FRAME: Counts ingress multicast frames -+ * @DPSW_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes -+ * @DPSW_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames -+ * @DPSW_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes -+ * @DPSW_CNT_EGR_FRAME: Counts egress frames -+ * @DPSW_CNT_EGR_BYTE: Counts eEgress bytes -+ * @DPSW_CNT_EGR_FRAME_DISCARD: Counts discarded egress frames -+ * @DPSW_CNT_EGR_STP_FRAME_DISCARD: Counts egress STP discarded frames -+ */ -+enum dpsw_counter { -+ DPSW_CNT_ING_FRAME = 0x0, -+ DPSW_CNT_ING_BYTE = 0x1, -+ DPSW_CNT_ING_FLTR_FRAME = 0x2, -+ DPSW_CNT_ING_FRAME_DISCARD = 0x3, -+ DPSW_CNT_ING_MCAST_FRAME = 0x4, -+ DPSW_CNT_ING_MCAST_BYTE = 0x5, -+ DPSW_CNT_ING_BCAST_FRAME = 0x6, -+ DPSW_CNT_ING_BCAST_BYTES = 0x7, -+ DPSW_CNT_EGR_FRAME = 0x8, -+ DPSW_CNT_EGR_BYTE = 0x9, -+ DPSW_CNT_EGR_FRAME_DISCARD = 0xa, -+ DPSW_CNT_EGR_STP_FRAME_DISCARD = 0xb -+}; -+ -+/** -+ * dpsw_if_get_counter() - Get specific counter of particular interface -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @type: Counter type -+ * @counter: return value -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_get_counter(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ enum dpsw_counter type, -+ uint64_t *counter); -+ -+/** -+ * dpsw_if_set_counter() - Set specific counter of particular interface -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @type: Counter type -+ * @counter: New counter value -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_set_counter(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ enum dpsw_counter type, -+ uint64_t counter); -+ -+/** -+ * Maximum number of TC -+ */ -+#define DPSW_MAX_TC 8 -+ -+/** -+ * enum dpsw_priority_selector - User priority -+ * @DPSW_UP_PCP: Priority Code Point (PCP): a 3-bit field which -+ * refers to the IEEE 802.1p priority. -+ * @DPSW_UP_DSCP: Differentiated services Code Point (DSCP): 6 bit -+ * field from IP header -+ * -+ */ -+enum dpsw_priority_selector { -+ DPSW_UP_PCP = 0, -+ DPSW_UP_DSCP = 1 -+}; -+ -+/** -+ * enum dpsw_schedule_mode - Traffic classes scheduling -+ * @DPSW_SCHED_STRICT_PRIORITY: schedule strict priority -+ * @DPSW_SCHED_WEIGHTED: schedule based on token bucket created algorithm -+ */ -+enum dpsw_schedule_mode { -+ DPSW_SCHED_STRICT_PRIORITY, -+ DPSW_SCHED_WEIGHTED -+}; -+ -+/** -+ * struct dpsw_tx_schedule_cfg - traffic class configuration -+ * @mode: Strict or weight-based scheduling -+ * @delta_bandwidth: weighted Bandwidth in range from 100 to 10000 -+ */ -+struct dpsw_tx_schedule_cfg { -+ enum dpsw_schedule_mode mode; -+ uint16_t delta_bandwidth; -+}; -+ -+/** -+ * struct dpsw_tx_selection_cfg - Mapping user priority into traffic -+ * class configuration -+ * @priority_selector: Source for user priority regeneration -+ * @tc_id: The Regenerated User priority that the incoming -+ * User Priority is mapped to for this interface -+ * @tc_sched: Traffic classes configuration -+ */ -+struct dpsw_tx_selection_cfg { -+ enum dpsw_priority_selector priority_selector; -+ uint8_t tc_id[DPSW_MAX_PRIORITIES]; -+ struct dpsw_tx_schedule_cfg tc_sched[DPSW_MAX_TC]; -+}; -+ -+/** -+ * dpsw_if_set_tx_selection() - Function is used for mapping variety -+ * of frame fields -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @cfg: Traffic class mapping configuration -+ * -+ * Function is used for mapping variety of frame fields (DSCP, PCP) -+ * to Traffic Class. Traffic class is a number -+ * in the range from 0 to 7 -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_set_tx_selection(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_tx_selection_cfg *cfg); -+ -+/** -+ * enum dpsw_reflection_filter - Filter type for frames to reflect -+ * @DPSW_REFLECTION_FILTER_INGRESS_ALL: Reflect all frames -+ * @DPSW_REFLECTION_FILTER_INGRESS_VLAN: Reflect only frames belong to -+ * particular VLAN defined by vid parameter -+ * -+ */ -+enum dpsw_reflection_filter { -+ DPSW_REFLECTION_FILTER_INGRESS_ALL = 0, -+ DPSW_REFLECTION_FILTER_INGRESS_VLAN = 1 -+}; -+ -+/** -+ * struct dpsw_reflection_cfg - Structure representing reflection information -+ * @filter: Filter type for frames to reflect -+ * @vlan_id: Vlan Id to reflect; valid only when filter type is -+ * DPSW_INGRESS_VLAN -+ */ -+struct dpsw_reflection_cfg { -+ enum dpsw_reflection_filter filter; -+ uint16_t vlan_id; -+}; -+ -+/** -+ * dpsw_if_add_reflection() - Identify interface to be reflected or mirrored -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @cfg: Reflection configuration -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_add_reflection(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_reflection_cfg *cfg); -+ -+/** -+ * dpsw_if_remove_reflection() - Remove interface to be reflected or mirrored -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @cfg: Reflection configuration -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_remove_reflection(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_reflection_cfg *cfg); -+ -+/** -+ * enum dpsw_metering_mode - Metering modes -+ * @DPSW_METERING_MODE_NONE: metering disabled -+ * @DPSW_METERING_MODE_RFC2698: RFC 2698 -+ * @DPSW_METERING_MODE_RFC4115: RFC 4115 -+ */ -+enum dpsw_metering_mode { -+ DPSW_METERING_MODE_NONE = 0, -+ DPSW_METERING_MODE_RFC2698, -+ DPSW_METERING_MODE_RFC4115 -+}; -+ -+/** -+ * enum dpsw_metering_unit - Metering count -+ * @DPSW_METERING_UNIT_BYTES: count bytes -+ * @DPSW_METERING_UNIT_FRAMES: count frames -+ */ -+enum dpsw_metering_unit { -+ DPSW_METERING_UNIT_BYTES = 0, -+ DPSW_METERING_UNIT_FRAMES -+}; -+ -+/** -+ * struct dpsw_metering_cfg - Metering configuration -+ * @mode: metering modes -+ * @units: Bytes or frame units -+ * @cir: Committed information rate (CIR) in Kbits/s -+ * @eir: Peak information rate (PIR) Kbit/s rfc2698 -+ * Excess information rate (EIR) Kbit/s rfc4115 -+ * @cbs: Committed burst size (CBS) in bytes -+ * @ebs: Peak burst size (PBS) in bytes for rfc2698 -+ * Excess bust size (EBS) in bytes rfc4115 -+ * -+ */ -+struct dpsw_metering_cfg { -+ enum dpsw_metering_mode mode; -+ enum dpsw_metering_unit units; -+ uint32_t cir; -+ uint32_t eir; -+ uint32_t cbs; -+ uint32_t ebs; -+}; -+ -+/** -+ * dpsw_if_set_flooding_metering() - Set flooding metering -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @cfg: Metering parameters -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_set_flooding_metering(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ const struct dpsw_metering_cfg *cfg); -+ -+/** -+ * dpsw_if_set_metering() - Set interface metering for flooding -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @tc_id: Traffic class ID -+ * @cfg: Metering parameters -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_set_metering(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ uint8_t tc_id, -+ const struct dpsw_metering_cfg *cfg); -+ -+/** -+ * enum dpsw_early_drop_unit - DPSW early drop unit -+ * @DPSW_EARLY_DROP_UNIT_BYTE: count bytes -+ * @DPSW_EARLY_DROP_UNIT_FRAMES: count frames -+ */ -+enum dpsw_early_drop_unit { -+ DPSW_EARLY_DROP_UNIT_BYTE = 0, -+ DPSW_EARLY_DROP_UNIT_FRAMES -+}; -+ -+/** -+ * enum dpsw_early_drop_mode - DPSW early drop mode -+ * @DPSW_EARLY_DROP_MODE_NONE: early drop is disabled -+ * @DPSW_EARLY_DROP_MODE_TAIL: early drop in taildrop mode -+ * @DPSW_EARLY_DROP_MODE_WRED: early drop in WRED mode -+ */ -+enum dpsw_early_drop_mode { -+ DPSW_EARLY_DROP_MODE_NONE = 0, -+ DPSW_EARLY_DROP_MODE_TAIL, -+ DPSW_EARLY_DROP_MODE_WRED -+}; -+ -+/** -+ * struct dpsw_wred_cfg - WRED configuration -+ * @max_threshold: maximum threshold that packets may be discarded. Above this -+ * threshold all packets are discarded; must be less than 2^39; -+ * approximated to be expressed as (x+256)*2^(y-1) due to HW -+ * implementation. -+ * @min_threshold: minimum threshold that packets may be discarded at -+ * @drop_probability: probability that a packet will be discarded (1-100, -+ * associated with the maximum threshold) -+ */ -+struct dpsw_wred_cfg { -+ uint64_t min_threshold; -+ uint64_t max_threshold; -+ uint8_t drop_probability; -+}; -+ -+/** -+ * struct dpsw_early_drop_cfg - early-drop configuration -+ * @drop_mode: drop mode -+ * @units: count units -+ * @yellow: WRED - 'yellow' configuration -+ * @green: WRED - 'green' configuration -+ * @tail_drop_threshold: tail drop threshold -+ */ -+struct dpsw_early_drop_cfg { -+ enum dpsw_early_drop_mode drop_mode; -+ enum dpsw_early_drop_unit units; -+ struct dpsw_wred_cfg yellow; -+ struct dpsw_wred_cfg green; -+ uint32_t tail_drop_threshold; -+}; -+ -+/** -+ * dpsw_prepare_early_drop() - Prepare an early drop for setting in to interface -+ * @cfg: Early-drop configuration -+ * @early_drop_buf: Zeroed 256 bytes of memory before mapping it to DMA -+ * -+ * This function has to be called before dpsw_if_tc_set_early_drop -+ * -+ */ -+void dpsw_prepare_early_drop(const struct dpsw_early_drop_cfg *cfg, -+ uint8_t *early_drop_buf); -+ -+/** -+ * dpsw_if_set_early_drop() - Set interface traffic class early-drop -+ * configuration -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @tc_id: Traffic class selection (0-7) -+ * @early_drop_iova: I/O virtual address of 64 bytes; -+ * Must be cacheline-aligned and DMA-able memory -+ * -+ * warning: Before calling this function, call dpsw_prepare_if_tc_early_drop() -+ * to prepare the early_drop_iova parameter -+ * -+ * Return: '0' on Success; error code otherwise. -+ */ -+int dpsw_if_set_early_drop(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ uint8_t tc_id, -+ uint64_t early_drop_iova); -+ -+/** -+ * struct dpsw_custom_tpid_cfg - Structure representing tag Protocol identifier -+ * @tpid: An additional tag protocol identifier -+ */ -+struct dpsw_custom_tpid_cfg { -+ uint16_t tpid; -+}; -+ -+/** -+ * dpsw_add_custom_tpid() - API Configures a distinct Ethernet type value -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @cfg: Tag Protocol identifier -+ * -+ * API Configures a distinct Ethernet type value (or TPID value) -+ * to indicate a VLAN tag in addition to the common -+ * TPID values 0x8100 and 0x88A8. -+ * Two additional TPID's are supported -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_add_custom_tpid(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpsw_custom_tpid_cfg *cfg); -+ -+/** -+ * dpsw_remove_custom_tpid - API removes a distinct Ethernet type value -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @cfg: Tag Protocol identifier -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_remove_custom_tpid(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpsw_custom_tpid_cfg *cfg); -+ -+/** -+ * dpsw_if_enable() - Enable Interface -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id); -+ -+/** -+ * dpsw_if_disable() - Disable Interface -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id); -+ -+/** -+ * struct dpsw_if_attr - Structure representing DPSW interface attributes -+ * @num_tcs: Number of traffic classes -+ * @rate: Transmit rate in bits per second -+ * @options: Interface configuration options (bitmap) -+ * @enabled: Indicates if interface is enabled -+ * @accept_all_vlan: The device discards/accepts incoming frames -+ * for VLANs that do not include this interface -+ * @admit_untagged: When set to 'DPSW_ADMIT_ONLY_VLAN_TAGGED', the device -+ * discards untagged frames or priority-tagged frames received on -+ * this interface; -+ * When set to 'DPSW_ADMIT_ALL', untagged frames or priority- -+ * tagged frames received on this interface are accepted -+ * @qdid: control frames transmit qdid -+ */ -+struct dpsw_if_attr { -+ uint8_t num_tcs; -+ uint32_t rate; -+ uint32_t options; -+ int enabled; -+ int accept_all_vlan; -+ enum dpsw_accepted_frames admit_untagged; -+ uint16_t qdid; -+}; -+ -+/** -+ * dpsw_if_get_attributes() - Function obtains attributes of interface -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @attr: Returned interface attributes -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ struct dpsw_if_attr *attr); -+ -+/** -+ * dpsw_if_set_max_frame_length() - Set Maximum Receive frame length. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @frame_length: Maximum Frame Length -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_set_max_frame_length(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ uint16_t frame_length); -+ -+/** -+ * dpsw_if_get_max_frame_length() - Get Maximum Receive frame length. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @if_id: Interface Identifier -+ * @frame_length: Returned maximum Frame Length -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_if_get_max_frame_length(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t if_id, -+ uint16_t *frame_length); -+ -+/** -+ * struct dpsw_vlan_cfg - VLAN Configuration -+ * @fdb_id: Forwarding Data Base -+ */ -+struct dpsw_vlan_cfg { -+ uint16_t fdb_id; -+}; -+ -+/** -+ * dpsw_vlan_add() - Adding new VLAN to DPSW. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @vlan_id: VLAN Identifier -+ * @cfg: VLAN configuration -+ * -+ * Only VLAN ID and FDB ID are required parameters here. -+ * 12 bit VLAN ID is defined in IEEE802.1Q. -+ * Adding a duplicate VLAN ID is not allowed. -+ * FDB ID can be shared across multiple VLANs. Shared learning -+ * is obtained by calling dpsw_vlan_add for multiple VLAN IDs -+ * with same fdb_id -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_vlan_add(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_cfg *cfg); -+ -+/** -+ * struct dpsw_vlan_if_cfg - Set of VLAN Interfaces -+ * @num_ifs: The number of interfaces that are assigned to the egress -+ * list for this VLAN -+ * @if_id: The set of interfaces that are -+ * assigned to the egress list for this VLAN -+ */ -+struct dpsw_vlan_if_cfg { -+ uint16_t num_ifs; -+ uint16_t if_id[DPSW_MAX_IF]; -+}; -+ -+/** -+ * dpsw_vlan_add_if() - Adding a set of interfaces to an existing VLAN. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @vlan_id: VLAN Identifier -+ * @cfg: Set of interfaces to add -+ * -+ * It adds only interfaces not belonging to this VLAN yet, -+ * otherwise an error is generated and an entire command is -+ * ignored. This function can be called numerous times always -+ * providing required interfaces delta. -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_vlan_add_if(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_if_cfg *cfg); -+ -+/** -+ * dpsw_vlan_add_if_untagged() - Defining a set of interfaces that should be -+ * transmitted as untagged. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @vlan_id: VLAN Identifier -+ * @cfg: set of interfaces that should be transmitted as untagged -+ * -+ * These interfaces should already belong to this VLAN. -+ * By default all interfaces are transmitted as tagged. -+ * Providing un-existing interface or untagged interface that is -+ * configured untagged already generates an error and the entire -+ * command is ignored. -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_vlan_add_if_untagged(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_if_cfg *cfg); -+ -+/** -+ * dpsw_vlan_add_if_flooding() - Define a set of interfaces that should be -+ * included in flooding when frame with unknown destination -+ * unicast MAC arrived. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @vlan_id: VLAN Identifier -+ * @cfg: Set of interfaces that should be used for flooding -+ * -+ * These interfaces should belong to this VLAN. By default all -+ * interfaces are included into flooding list. Providing -+ * un-existing interface or an interface that already in the -+ * flooding list generates an error and the entire command is -+ * ignored. -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_vlan_add_if_flooding(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_if_cfg *cfg); -+ -+/** -+ * dpsw_vlan_remove_if() - Remove interfaces from an existing VLAN. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @vlan_id: VLAN Identifier -+ * @cfg: Set of interfaces that should be removed -+ * -+ * Interfaces must belong to this VLAN, otherwise an error -+ * is returned and an the command is ignored -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_vlan_remove_if(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_if_cfg *cfg); -+ -+/** -+ * dpsw_vlan_remove_if_untagged() - Define a set of interfaces that should be -+ * converted from transmitted as untagged to transmit as tagged. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @vlan_id: VLAN Identifier -+ * @cfg: set of interfaces that should be removed -+ * -+ * Interfaces provided by API have to belong to this VLAN and -+ * configured untagged, otherwise an error is returned and the -+ * command is ignored -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_vlan_remove_if_untagged(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_if_cfg *cfg); -+ -+/** -+ * dpsw_vlan_remove_if_flooding() - Define a set of interfaces that should be -+ * removed from the flooding list. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @vlan_id: VLAN Identifier -+ * @cfg: set of interfaces used for flooding -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_vlan_remove_if_flooding(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ const struct dpsw_vlan_if_cfg *cfg); -+ -+/** -+ * dpsw_vlan_remove() - Remove an entire VLAN -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @vlan_id: VLAN Identifier -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_vlan_remove(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id); -+ -+/** -+ * struct dpsw_vlan_attr - VLAN attributes -+ * @fdb_id: Associated FDB ID -+ * @num_ifs: Number of interfaces -+ * @num_untagged_ifs: Number of untagged interfaces -+ * @num_flooding_ifs: Number of flooding interfaces -+ */ -+struct dpsw_vlan_attr { -+ uint16_t fdb_id; -+ uint16_t num_ifs; -+ uint16_t num_untagged_ifs; -+ uint16_t num_flooding_ifs; -+}; -+ -+/** -+ * dpsw_vlan_get_attributes() - Get VLAN attributes -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @vlan_id: VLAN Identifier -+ * @attr: Returned DPSW attributes -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_vlan_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ struct dpsw_vlan_attr *attr); -+ -+/** -+ * dpsw_vlan_get_if() - Get interfaces belong to this VLAN -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @vlan_id: VLAN Identifier -+ * @cfg: Returned set of interfaces belong to this VLAN -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_vlan_get_if(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ struct dpsw_vlan_if_cfg *cfg); -+ -+/** -+ * dpsw_vlan_get_if_flooding() - Get interfaces used in flooding for this VLAN -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @vlan_id: VLAN Identifier -+ * @cfg: Returned set of flooding interfaces -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_vlan_get_if_flooding(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ struct dpsw_vlan_if_cfg *cfg); -+ -+/** -+ * dpsw_vlan_get_if_untagged() - Get interfaces that should be transmitted as -+ * untagged -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @vlan_id: VLAN Identifier -+ * @cfg: Returned set of untagged interfaces -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_vlan_get_if_untagged(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t vlan_id, -+ struct dpsw_vlan_if_cfg *cfg); -+ -+/** -+ * struct dpsw_fdb_cfg - FDB Configuration -+ * @num_fdb_entries: Number of FDB entries -+ * @fdb_aging_time: Aging time in seconds -+ */ -+struct dpsw_fdb_cfg { -+ uint16_t num_fdb_entries; -+ uint16_t fdb_aging_time; -+}; -+ -+/** -+ * dpsw_fdb_add() - Add FDB to switch and Returns handle to FDB table for -+ * the reference -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @fdb_id: Returned Forwarding Database Identifier -+ * @cfg: FDB Configuration -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_fdb_add(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *fdb_id, -+ const struct dpsw_fdb_cfg *cfg); -+ -+/** -+ * dpsw_fdb_remove() - Remove FDB from switch -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @fdb_id: Forwarding Database Identifier -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_fdb_remove(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id); -+ -+/** -+ * enum dpsw_fdb_entry_type - FDB Entry type - Static/Dynamic -+ * @DPSW_FDB_ENTRY_STATIC: Static entry -+ * @DPSW_FDB_ENTRY_DINAMIC: Dynamic entry -+ */ -+enum dpsw_fdb_entry_type { -+ DPSW_FDB_ENTRY_STATIC = 0, -+ DPSW_FDB_ENTRY_DINAMIC = 1 -+}; -+ -+/** -+ * struct dpsw_fdb_unicast_cfg - Unicast entry configuration -+ * @type: Select static or dynamic entry -+ * @mac_addr: MAC address -+ * @if_egress: Egress interface ID -+ */ -+struct dpsw_fdb_unicast_cfg { -+ enum dpsw_fdb_entry_type type; -+ uint8_t mac_addr[6]; -+ uint16_t if_egress; -+}; -+ -+/** -+ * dpsw_fdb_add_unicast() - Function adds an unicast entry into MAC lookup table -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @fdb_id: Forwarding Database Identifier -+ * @cfg: Unicast entry configuration -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_fdb_add_unicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ const struct dpsw_fdb_unicast_cfg *cfg); -+ -+/** -+ * dpsw_fdb_get_unicast() - Get unicast entry from MAC lookup table by -+ * unicast Ethernet address -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @fdb_id: Forwarding Database Identifier -+ * @cfg: Returned unicast entry configuration -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_fdb_get_unicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ struct dpsw_fdb_unicast_cfg *cfg); -+ -+/** -+ * dpsw_fdb_remove_unicast() - removes an entry from MAC lookup table -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @fdb_id: Forwarding Database Identifier -+ * @cfg: Unicast entry configuration -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_fdb_remove_unicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ const struct dpsw_fdb_unicast_cfg *cfg); -+ -+/** -+ * struct dpsw_fdb_multicast_cfg - Multi-cast entry configuration -+ * @type: Select static or dynamic entry -+ * @mac_addr: MAC address -+ * @num_ifs: Number of external and internal interfaces -+ * @if_id: Egress interface IDs -+ */ -+struct dpsw_fdb_multicast_cfg { -+ enum dpsw_fdb_entry_type type; -+ uint8_t mac_addr[6]; -+ uint16_t num_ifs; -+ uint16_t if_id[DPSW_MAX_IF]; -+}; -+ -+/** -+ * dpsw_fdb_add_multicast() - Add a set of egress interfaces to multi-cast group -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @fdb_id: Forwarding Database Identifier -+ * @cfg: Multicast entry configuration -+ * -+ * If group doesn't exist, it will be created. -+ * It adds only interfaces not belonging to this multicast group -+ * yet, otherwise error will be generated and the command is -+ * ignored. -+ * This function may be called numerous times always providing -+ * required interfaces delta. -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_fdb_add_multicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ const struct dpsw_fdb_multicast_cfg *cfg); -+ -+/** -+ * dpsw_fdb_get_multicast() - Reading multi-cast group by multi-cast Ethernet -+ * address. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @fdb_id: Forwarding Database Identifier -+ * @cfg: Returned multicast entry configuration -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_fdb_get_multicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ struct dpsw_fdb_multicast_cfg *cfg); -+ -+/** -+ * dpsw_fdb_remove_multicast() - Removing interfaces from an existing multicast -+ * group. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @fdb_id: Forwarding Database Identifier -+ * @cfg: Multicast entry configuration -+ * -+ * Interfaces provided by this API have to exist in the group, -+ * otherwise an error will be returned and an entire command -+ * ignored. If there is no interface left in the group, -+ * an entire group is deleted -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_fdb_remove_multicast(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ const struct dpsw_fdb_multicast_cfg *cfg); -+ -+/** -+ * enum dpsw_fdb_learning_mode - Auto-learning modes -+ * @DPSW_FDB_LEARNING_MODE_DIS: Disable Auto-learning -+ * @DPSW_FDB_LEARNING_MODE_HW: Enable HW auto-Learning -+ * @DPSW_FDB_LEARNING_MODE_NON_SECURE: Enable None secure learning by CPU -+ * @DPSW_FDB_LEARNING_MODE_SECURE: Enable secure learning by CPU -+ * -+ * NONE - SECURE LEARNING -+ * SMAC found DMAC found CTLU Action -+ * v v Forward frame to -+ * 1. DMAC destination -+ * - v Forward frame to -+ * 1. DMAC destination -+ * 2. Control interface -+ * v - Forward frame to -+ * 1. Flooding list of interfaces -+ * - - Forward frame to -+ * 1. Flooding list of interfaces -+ * 2. Control interface -+ * SECURE LEARING -+ * SMAC found DMAC found CTLU Action -+ * v v Forward frame to -+ * 1. DMAC destination -+ * - v Forward frame to -+ * 1. Control interface -+ * v - Forward frame to -+ * 1. Flooding list of interfaces -+ * - - Forward frame to -+ * 1. Control interface -+ */ -+enum dpsw_fdb_learning_mode { -+ DPSW_FDB_LEARNING_MODE_DIS = 0, -+ DPSW_FDB_LEARNING_MODE_HW = 1, -+ DPSW_FDB_LEARNING_MODE_NON_SECURE = 2, -+ DPSW_FDB_LEARNING_MODE_SECURE = 3 -+}; -+ -+/** -+ * dpsw_fdb_set_learning_mode() - Define FDB learning mode -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @fdb_id: Forwarding Database Identifier -+ * @mode: learning mode -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_fdb_set_learning_mode(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ enum dpsw_fdb_learning_mode mode); -+ -+/** -+ * struct dpsw_fdb_attr - FDB Attributes -+ * @max_fdb_entries: Number of FDB entries -+ * @fdb_aging_time: Aging time in seconds -+ * @learning_mode: Learning mode -+ * @num_fdb_mc_groups: Current number of multicast groups -+ * @max_fdb_mc_groups: Maximum number of multicast groups -+ */ -+struct dpsw_fdb_attr { -+ uint16_t max_fdb_entries; -+ uint16_t fdb_aging_time; -+ enum dpsw_fdb_learning_mode learning_mode; -+ uint16_t num_fdb_mc_groups; -+ uint16_t max_fdb_mc_groups; -+}; -+ -+/** -+ * dpsw_fdb_get_attributes() - Get FDB attributes -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @fdb_id: Forwarding Database Identifier -+ * @attr: Returned FDB attributes -+ * -+ * Return: Completion status. '0' on Success; Error code otherwise. -+ */ -+int dpsw_fdb_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t fdb_id, -+ struct dpsw_fdb_attr *attr); -+ -+/** -+ * struct dpsw_acl_cfg - ACL Configuration -+ * @max_entries: Number of FDB entries -+ */ -+struct dpsw_acl_cfg { -+ uint16_t max_entries; -+}; -+ -+/** -+ * struct dpsw_acl_fields - ACL fields. -+ * @l2_dest_mac: Destination MAC address: BPDU, Multicast, Broadcast, Unicast, -+ * slow protocols, MVRP, STP -+ * @l2_source_mac: Source MAC address -+ * @l2_tpid: Layer 2 (Ethernet) protocol type, used to identify the following -+ * protocols: MPLS, PTP, PFC, ARP, Jumbo frames, LLDP, IEEE802.1ae, -+ * Q-in-Q, IPv4, IPv6, PPPoE -+ * @l2_pcp_dei: indicate which protocol is encapsulated in the payload -+ * @l2_vlan_id: layer 2 VLAN ID -+ * @l2_ether_type: layer 2 Ethernet type -+ * @l3_dscp: Layer 3 differentiated services code point -+ * @l3_protocol: Tells the Network layer at the destination host, to which -+ * Protocol this packet belongs to. The following protocol are -+ * supported: ICMP, IGMP, IPv4 (encapsulation), TCP, IPv6 -+ * (encapsulation), GRE, PTP -+ * @l3_source_ip: Source IPv4 IP -+ * @l3_dest_ip: Destination IPv4 IP -+ * @l4_source_port: Source TCP/UDP Port -+ * @l4_dest_port: Destination TCP/UDP Port -+ */ -+struct dpsw_acl_fields { -+ uint8_t l2_dest_mac[6]; -+ uint8_t l2_source_mac[6]; -+ uint16_t l2_tpid; -+ uint8_t l2_pcp_dei; -+ uint16_t l2_vlan_id; -+ uint16_t l2_ether_type; -+ uint8_t l3_dscp; -+ uint8_t l3_protocol; -+ uint32_t l3_source_ip; -+ uint32_t l3_dest_ip; -+ uint16_t l4_source_port; -+ uint16_t l4_dest_port; -+}; -+ -+/** -+ * struct dpsw_acl_key - ACL key -+ * @match: Match fields -+ * @mask: Mask: b'1 - valid, b'0 don't care -+ */ -+struct dpsw_acl_key { -+ struct dpsw_acl_fields match; -+ struct dpsw_acl_fields mask; -+}; -+ -+/** -+ * enum dpsw_acl_action -+ * @DPSW_ACL_ACTION_DROP: Drop frame -+ * @DPSW_ACL_ACTION_REDIRECT: Redirect to certain port -+ * @DPSW_ACL_ACTION_ACCEPT: Accept frame -+ * @DPSW_ACL_ACTION_REDIRECT_TO_CTRL_IF: Redirect to control interface -+ */ -+enum dpsw_acl_action { -+ DPSW_ACL_ACTION_DROP, -+ DPSW_ACL_ACTION_REDIRECT, -+ DPSW_ACL_ACTION_ACCEPT, -+ DPSW_ACL_ACTION_REDIRECT_TO_CTRL_IF -+}; -+ -+/** -+ * struct dpsw_acl_result - ACL action -+ * @action: Action should be taken when ACL entry hit -+ * @if_id: Interface IDs to redirect frame. Valid only if redirect selected for -+ * action -+ */ -+struct dpsw_acl_result { -+ enum dpsw_acl_action action; -+ uint16_t if_id; -+}; -+ -+/** -+ * struct dpsw_acl_entry_cfg - ACL entry -+ * @key_iova: I/O virtual address of DMA-able memory filled with key after call -+ * to dpsw_acl_prepare_entry_cfg() -+ * @result: Required action when entry hit occurs -+ * @precedence: Precedence inside ACL 0 is lowest; This priority can not change -+ * during the lifetime of a Policy. It is user responsibility to -+ * space the priorities according to consequent rule additions. -+ */ -+struct dpsw_acl_entry_cfg { -+ uint64_t key_iova; -+ struct dpsw_acl_result result; -+ int precedence; -+}; -+ -+/** -+ * dpsw_acl_add() - Adds ACL to L2 switch. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @acl_id: Returned ACL ID, for the future reference -+ * @cfg: ACL configuration -+ * -+ * Create Access Control List. Multiple ACLs can be created and -+ * co-exist in L2 switch -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_acl_add(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t *acl_id, -+ const struct dpsw_acl_cfg *cfg); -+ -+/** -+ * dpsw_acl_remove() - Removes ACL from L2 switch. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @acl_id: ACL ID -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_acl_remove(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t acl_id); -+ -+/** -+ * dpsw_acl_prepare_entry_cfg() - Set an entry to ACL. -+ * @key: key -+ * @entry_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA -+ * -+ * This function has to be called before adding or removing acl_entry -+ * -+ */ -+void dpsw_acl_prepare_entry_cfg(const struct dpsw_acl_key *key, -+ uint8_t *entry_cfg_buf); -+ -+/** -+ * dpsw_acl_add_entry() - Adds an entry to ACL. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @acl_id: ACL ID -+ * @cfg: entry configuration -+ * -+ * warning: This function has to be called after dpsw_acl_set_entry_cfg() -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_acl_add_entry(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t acl_id, -+ const struct dpsw_acl_entry_cfg *cfg); -+ -+/** -+ * dpsw_acl_remove_entry() - Removes an entry from ACL. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @acl_id: ACL ID -+ * @cfg: entry configuration -+ * -+ * warning: This function has to be called after dpsw_acl_set_entry_cfg() -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_acl_remove_entry(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t acl_id, -+ const struct dpsw_acl_entry_cfg *cfg); -+ -+/** -+ * struct dpsw_acl_if_cfg - List of interfaces to Associate with ACL -+ * @num_ifs: Number of interfaces -+ * @if_id: List of interfaces -+ */ -+struct dpsw_acl_if_cfg { -+ uint16_t num_ifs; -+ uint16_t if_id[DPSW_MAX_IF]; -+}; -+ -+/** -+ * dpsw_acl_add_if() - Associate interface/interfaces with ACL. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @acl_id: ACL ID -+ * @cfg: interfaces list -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_acl_add_if(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t acl_id, -+ const struct dpsw_acl_if_cfg *cfg); -+ -+/** -+ * dpsw_acl_remove_if() - De-associate interface/interfaces from ACL. -+ * @mc_io: Pointer to MC portal's I/O object -+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+ * @token: Token of DPSW object -+ * @acl_id: ACL ID -+ * @cfg: interfaces list -+ * -+ * Return: '0' on Success; Error code otherwise. -+ */ -+int dpsw_acl_remove_if(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t acl_id, -+ const struct dpsw_acl_if_cfg *cfg); -+ -+/** -+ * struct dpsw_acl_attr - ACL Attributes -+ * @max_entries: Max number of ACL entries -+ * @num_entries: Number of used ACL entries -+ * @num_ifs: Number of interfaces associated with ACL -+ */ -+struct dpsw_acl_attr { -+ uint16_t max_entries; -+ uint16_t num_entries; -+ uint16_t num_ifs; -+}; -+ -+/** -+* dpsw_acl_get_attributes() - Get specific counter of particular interface -+* @mc_io: Pointer to MC portal's I/O object -+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+* @token: Token of DPSW object -+* @acl_id: ACL Identifier -+* @attr: Returned ACL attributes -+* -+* Return: '0' on Success; Error code otherwise. -+*/ -+int dpsw_acl_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ uint16_t acl_id, -+ struct dpsw_acl_attr *attr); -+/** -+* struct dpsw_ctrl_if_attr - Control interface attributes -+* @rx_fqid: Receive FQID -+* @rx_err_fqid: Receive error FQID -+* @tx_err_conf_fqid: Transmit error and confirmation FQID -+*/ -+struct dpsw_ctrl_if_attr { -+ uint32_t rx_fqid; -+ uint32_t rx_err_fqid; -+ uint32_t tx_err_conf_fqid; -+}; -+ -+/** -+* dpsw_ctrl_if_get_attributes() - Obtain control interface attributes -+* @mc_io: Pointer to MC portal's I/O object -+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+* @token: Token of DPSW object -+* @attr: Returned control interface attributes -+* -+* Return: '0' on Success; Error code otherwise. -+*/ -+int dpsw_ctrl_if_get_attributes(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ struct dpsw_ctrl_if_attr *attr); -+ -+/** -+ * Maximum number of DPBP -+ */ -+#define DPSW_MAX_DPBP 8 -+ -+/** -+ * struct dpsw_ctrl_if_pools_cfg - Control interface buffer pools configuration -+ * @num_dpbp: Number of DPBPs -+ * @pools: Array of buffer pools parameters; The number of valid entries -+ * must match 'num_dpbp' value -+ */ -+struct dpsw_ctrl_if_pools_cfg { -+ uint8_t num_dpbp; -+ /** -+ * struct pools - Buffer pools parameters -+ * @dpbp_id: DPBP object ID -+ * @buffer_size: Buffer size -+ * @backup_pool: Backup pool -+ */ -+ struct { -+ int dpbp_id; -+ uint16_t buffer_size; -+ int backup_pool; -+ } pools[DPSW_MAX_DPBP]; -+}; -+ -+/** -+* dpsw_ctrl_if_set_pools() - Set control interface buffer pools -+* @mc_io: Pointer to MC portal's I/O object -+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+* @token: Token of DPSW object -+* @cfg: buffer pools configuration -+* -+* Return: '0' on Success; Error code otherwise. -+*/ -+int dpsw_ctrl_if_set_pools(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token, -+ const struct dpsw_ctrl_if_pools_cfg *cfg); -+ -+/** -+* dpsw_ctrl_if_enable() - Enable control interface -+* @mc_io: Pointer to MC portal's I/O object -+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+* @token: Token of DPSW object -+* -+* Return: '0' on Success; Error code otherwise. -+*/ -+int dpsw_ctrl_if_enable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+/** -+* dpsw_ctrl_if_disable() - Function disables control interface -+* @mc_io: Pointer to MC portal's I/O object -+* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -+* @token: Token of DPSW object -+* -+* Return: '0' on Success; Error code otherwise. -+*/ -+int dpsw_ctrl_if_disable(struct fsl_mc_io *mc_io, -+ uint32_t cmd_flags, -+ uint16_t token); -+ -+#endif /* __FSL_DPSW_H */ ---- /dev/null -+++ b/drivers/staging/fsl-dpaa2/ethsw/switch.c -@@ -0,0 +1,1711 @@ -+/* Copyright 2014-2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "../../fsl-mc/include/mc.h" -+#include "dpsw.h" -+#include "dpsw-cmd.h" -+ -+/* Minimal supported DPSE version */ -+#define DPSW_MIN_VER_MAJOR 7 -+#define DPSW_MIN_VER_MINOR 0 -+ -+/* IRQ index */ -+#define DPSW_MAX_IRQ_NUM 2 -+ -+#define ETHSW_VLAN_MEMBER 1 -+#define ETHSW_VLAN_UNTAGGED 2 -+#define ETHSW_VLAN_PVID 4 -+#define ETHSW_VLAN_GLOBAL 8 -+ -+struct ethsw_port_priv { -+ struct net_device *netdev; -+ struct list_head list; -+ u16 port_index; -+ struct ethsw_dev_priv *ethsw_priv; -+ u8 stp_state; -+ -+ char vlans[VLAN_VID_MASK+1]; -+ -+}; -+ -+struct ethsw_dev_priv { -+ struct net_device *netdev; -+ struct fsl_mc_io *mc_io; -+ uint16_t dpsw_handle; -+ struct dpsw_attr sw_attr; -+ int dev_id; -+ /*TODO: redundant, we can use the slave dev list */ -+ struct list_head port_list; -+ -+ bool flood; -+ bool learning; -+ -+ char vlans[VLAN_VID_MASK+1]; -+}; -+ -+static int ethsw_port_stop(struct net_device *netdev); -+static int ethsw_port_open(struct net_device *netdev); -+ -+static inline void __get_priv(struct net_device *netdev, -+ struct ethsw_dev_priv **priv, -+ struct ethsw_port_priv **port_priv) -+{ -+ struct ethsw_dev_priv *_priv = NULL; -+ struct ethsw_port_priv *_port_priv = NULL; -+ -+ if (netdev->flags & IFF_MASTER) { -+ _priv = netdev_priv(netdev); -+ } else { -+ _port_priv = netdev_priv(netdev); -+ _priv = _port_priv->ethsw_priv; -+ } -+ -+ if (priv) -+ *priv = _priv; -+ if (port_priv) -+ *port_priv = _port_priv; -+} -+ -+/* -------------------------------------------------------------------------- */ -+/* ethsw netdevice ops */ -+ -+static netdev_tx_t ethsw_dropframe(struct sk_buff *skb, struct net_device *dev) -+{ -+ /* we don't support I/O for now, drop the frame */ -+ dev_kfree_skb_any(skb); -+ return NETDEV_TX_OK; -+} -+ -+static int ethsw_open(struct net_device *netdev) -+{ -+ struct ethsw_dev_priv *priv = netdev_priv(netdev); -+ struct list_head *pos; -+ struct ethsw_port_priv *port_priv = NULL; -+ int err; -+ -+ err = dpsw_enable(priv->mc_io, 0, priv->dpsw_handle); -+ if (err) { -+ netdev_err(netdev, "dpsw_enable err %d\n", err); -+ return err; -+ } -+ -+ list_for_each(pos, &priv->port_list) { -+ port_priv = list_entry(pos, struct ethsw_port_priv, list); -+ err = dev_open(port_priv->netdev); -+ if (err) -+ netdev_err(port_priv->netdev, "dev_open err %d\n", err); -+ } -+ -+ return 0; -+} -+ -+static int ethsw_stop(struct net_device *netdev) -+{ -+ struct ethsw_dev_priv *priv = netdev_priv(netdev); -+ struct list_head *pos; -+ struct ethsw_port_priv *port_priv = NULL; -+ int err; -+ -+ err = dpsw_disable(priv->mc_io, 0, priv->dpsw_handle); -+ if (err) { -+ netdev_err(netdev, "dpsw_disable err %d\n", err); -+ return err; -+ } -+ -+ list_for_each(pos, &priv->port_list) { -+ port_priv = list_entry(pos, struct ethsw_port_priv, list); -+ err = dev_close(port_priv->netdev); -+ if (err) -+ netdev_err(port_priv->netdev, -+ "dev_close err %d\n", err); -+ } -+ -+ return 0; -+} -+ -+static int ethsw_add_vlan(struct net_device *netdev, u16 vid) -+{ -+ struct ethsw_dev_priv *priv = netdev_priv(netdev); -+ int err; -+ -+ struct dpsw_vlan_cfg vcfg = { -+ /* TODO: add support for VLAN private FDBs */ -+ .fdb_id = 0, -+ }; -+ if (priv->vlans[vid]) { -+ netdev_err(netdev, "VLAN already configured\n"); -+ return -EEXIST; -+ } -+ -+ err = dpsw_vlan_add(priv->mc_io, 0, priv->dpsw_handle, vid, &vcfg); -+ if (err) { -+ netdev_err(netdev, "dpsw_vlan_add err %d\n", err); -+ return err; -+ } -+ priv->vlans[vid] = ETHSW_VLAN_MEMBER; -+ -+ return 0; -+} -+ -+static int ethsw_port_add_vlan(struct net_device *netdev, u16 vid, u16 flags) -+{ -+ struct ethsw_port_priv *port_priv = netdev_priv(netdev); -+ struct ethsw_dev_priv *priv = port_priv->ethsw_priv; -+ int err; -+ -+ struct dpsw_vlan_if_cfg vcfg = { -+ .num_ifs = 1, -+ .if_id[0] = port_priv->port_index, -+ }; -+ -+ if (port_priv->vlans[vid]) { -+ netdev_err(netdev, "VLAN already configured\n"); -+ return -EEXIST; -+ } -+ -+ if (flags & BRIDGE_VLAN_INFO_PVID && netif_oper_up(netdev)) { -+ netdev_err(netdev, "interface must be down to change PVID!\n"); -+ return -EBUSY; -+ } -+ -+ err = dpsw_vlan_add_if(priv->mc_io, 0, priv->dpsw_handle, vid, &vcfg); -+ if (err) { -+ netdev_err(netdev, "dpsw_vlan_add_if err %d\n", err); -+ return err; -+ } -+ port_priv->vlans[vid] = ETHSW_VLAN_MEMBER; -+ -+ if (flags & BRIDGE_VLAN_INFO_UNTAGGED) { -+ err = dpsw_vlan_add_if_untagged(priv->mc_io, 0, -+ priv->dpsw_handle, vid, &vcfg); -+ if (err) { -+ netdev_err(netdev, "dpsw_vlan_add_if_untagged err %d\n", -+ err); -+ return err; -+ } -+ port_priv->vlans[vid] |= ETHSW_VLAN_UNTAGGED; -+ } -+ -+ if (flags & BRIDGE_VLAN_INFO_PVID) { -+ struct dpsw_tci_cfg tci_cfg = { -+ /* TODO: at least add better defaults if these cannot -+ * be configured -+ */ -+ .pcp = 0, -+ .dei = 0, -+ .vlan_id = vid, -+ }; -+ -+ err = dpsw_if_set_tci(priv->mc_io, 0, priv->dpsw_handle, -+ port_priv->port_index, &tci_cfg); -+ if (err) { -+ netdev_err(netdev, "dpsw_if_set_tci err %d\n", err); -+ return err; -+ } -+ port_priv->vlans[vid] |= ETHSW_VLAN_PVID; -+ } -+ -+ return 0; -+} -+ -+static const struct nla_policy ifla_br_policy[IFLA_MAX+1] = { -+ [IFLA_BRIDGE_FLAGS] = { .type = NLA_U16 }, -+ [IFLA_BRIDGE_MODE] = { .type = NLA_U16 }, -+ [IFLA_BRIDGE_VLAN_INFO] = { .type = NLA_BINARY, -+ .len = sizeof(struct bridge_vlan_info), }, -+}; -+ -+static int ethsw_setlink_af_spec(struct net_device *netdev, -+ struct nlattr **tb) -+{ -+ struct bridge_vlan_info *vinfo; -+ struct ethsw_dev_priv *priv = NULL; -+ struct ethsw_port_priv *port_priv = NULL; -+ int err = 0; -+ -+ if (!tb[IFLA_BRIDGE_VLAN_INFO]) { -+ netdev_err(netdev, "no VLAN INFO in nlmsg\n"); -+ return -EOPNOTSUPP; -+ } -+ -+ vinfo = nla_data(tb[IFLA_BRIDGE_VLAN_INFO]); -+ -+ if (!vinfo->vid || vinfo->vid > VLAN_VID_MASK) -+ return -EINVAL; -+ -+ __get_priv(netdev, &priv, &port_priv); -+ -+ if (!port_priv || !priv->vlans[vinfo->vid]) { -+ /* command targets switch device or this is a new VLAN */ -+ err = ethsw_add_vlan(priv->netdev, vinfo->vid); -+ if (err) -+ return err; -+ -+ /* command targets switch device; mark it*/ -+ if (!port_priv) -+ priv->vlans[vinfo->vid] |= ETHSW_VLAN_GLOBAL; -+ } -+ -+ if (port_priv) { -+ /* command targets switch port */ -+ err = ethsw_port_add_vlan(netdev, vinfo->vid, vinfo->flags); -+ if (err) -+ return err; -+ } -+ -+ return 0; -+} -+ -+static const struct nla_policy ifla_brport_policy[IFLA_BRPORT_MAX + 1] = { -+ [IFLA_BRPORT_STATE] = { .type = NLA_U8 }, -+ [IFLA_BRPORT_COST] = { .type = NLA_U32 }, -+ [IFLA_BRPORT_PRIORITY] = { .type = NLA_U16 }, -+ [IFLA_BRPORT_MODE] = { .type = NLA_U8 }, -+ [IFLA_BRPORT_GUARD] = { .type = NLA_U8 }, -+ [IFLA_BRPORT_PROTECT] = { .type = NLA_U8 }, -+ [IFLA_BRPORT_LEARNING] = { .type = NLA_U8 }, -+ [IFLA_BRPORT_UNICAST_FLOOD] = { .type = NLA_U8 }, -+}; -+ -+static int ethsw_set_learning(struct net_device *netdev, u8 flag) -+{ -+ struct ethsw_dev_priv *priv = netdev_priv(netdev); -+ enum dpsw_fdb_learning_mode learn_mode; -+ int err; -+ -+ if (flag) -+ learn_mode = DPSW_FDB_LEARNING_MODE_HW; -+ else -+ learn_mode = DPSW_FDB_LEARNING_MODE_DIS; -+ -+ err = dpsw_fdb_set_learning_mode(priv->mc_io, 0, priv->dpsw_handle, -+ 0, learn_mode); -+ if (err) { -+ netdev_err(netdev, "dpsw_fdb_set_learning_mode err %d\n", err); -+ return err; -+ } -+ priv->learning = !!flag; -+ -+ return 0; -+} -+ -+static int ethsw_port_set_flood(struct net_device *netdev, u8 flag) -+{ -+ struct ethsw_port_priv *port_priv = netdev_priv(netdev); -+ struct ethsw_dev_priv *priv = port_priv->ethsw_priv; -+ int err; -+ -+ err = dpsw_if_set_flooding(priv->mc_io, 0, priv->dpsw_handle, -+ port_priv->port_index, (int)flag); -+ if (err) { -+ netdev_err(netdev, "dpsw_fdb_set_learning_mode err %d\n", err); -+ return err; -+ } -+ priv->flood = !!flag; -+ -+ return 0; -+} -+ -+static int ethsw_port_set_state(struct net_device *netdev, u8 state) -+{ -+ struct ethsw_port_priv *port_priv = netdev_priv(netdev); -+ struct ethsw_dev_priv *priv = port_priv->ethsw_priv; -+ u8 old_state = port_priv->stp_state; -+ int err; -+ -+ struct dpsw_stp_cfg stp_cfg = { -+ .vlan_id = 1, -+ .state = state, -+ }; -+ /* TODO: check port state, interface may be down */ -+ -+ if (state > BR_STATE_BLOCKING) -+ return -EINVAL; -+ -+ if (state == port_priv->stp_state) -+ return 0; -+ -+ if (state == BR_STATE_DISABLED) { -+ port_priv->stp_state = state; -+ -+ err = ethsw_port_stop(netdev); -+ if (err) -+ goto error; -+ } else { -+ err = dpsw_if_set_stp(priv->mc_io, 0, priv->dpsw_handle, -+ port_priv->port_index, &stp_cfg); -+ if (err) { -+ netdev_err(netdev, "dpsw_if_set_stp err %d\n", err); -+ return err; -+ } -+ -+ port_priv->stp_state = state; -+ -+ if (old_state == BR_STATE_DISABLED) { -+ err = ethsw_port_open(netdev); -+ if (err) -+ goto error; -+ } -+ } -+ -+ return 0; -+error: -+ port_priv->stp_state = old_state; -+ return err; -+} -+ -+static int ethsw_setlink_protinfo(struct net_device *netdev, -+ struct nlattr **tb) -+{ -+ struct ethsw_dev_priv *priv; -+ struct ethsw_port_priv *port_priv = NULL; -+ int err = 0; -+ -+ __get_priv(netdev, &priv, &port_priv); -+ -+ if (tb[IFLA_BRPORT_LEARNING]) { -+ u8 flag = nla_get_u8(tb[IFLA_BRPORT_LEARNING]); -+ -+ if (port_priv) -+ netdev_warn(netdev, -+ "learning set on whole switch dev\n"); -+ -+ err = ethsw_set_learning(priv->netdev, flag); -+ if (err) -+ return err; -+ -+ } else if (tb[IFLA_BRPORT_UNICAST_FLOOD] && port_priv) { -+ u8 flag = nla_get_u8(tb[IFLA_BRPORT_UNICAST_FLOOD]); -+ -+ err = ethsw_port_set_flood(port_priv->netdev, flag); -+ if (err) -+ return err; -+ -+ } else if (tb[IFLA_BRPORT_STATE] && port_priv) { -+ u8 state = nla_get_u8(tb[IFLA_BRPORT_STATE]); -+ -+ err = ethsw_port_set_state(port_priv->netdev, state); -+ if (err) -+ return err; -+ -+ } else { -+ return -EOPNOTSUPP; -+ } -+ -+ return 0; -+} -+ -+static int ethsw_setlink(struct net_device *netdev, -+ struct nlmsghdr *nlh, -+ u16 flags) -+{ -+ struct nlattr *attr; -+ struct nlattr *tb[(IFLA_BRIDGE_MAX > IFLA_BRPORT_MAX) ? -+ IFLA_BRIDGE_MAX : IFLA_BRPORT_MAX+1]; -+ int err = 0; -+ -+ attr = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); -+ if (attr) { -+ err = nla_parse_nested(tb, IFLA_BRIDGE_MAX, attr, -+ ifla_br_policy); -+ if (err) { -+ netdev_err(netdev, -+ "nla_parse_nested for br_policy err %d\n", -+ err); -+ return err; -+ } -+ -+ err = ethsw_setlink_af_spec(netdev, tb); -+ return err; -+ } -+ -+ attr = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_PROTINFO); -+ if (attr) { -+ err = nla_parse_nested(tb, IFLA_BRPORT_MAX, attr, -+ ifla_brport_policy); -+ if (err) { -+ netdev_err(netdev, -+ "nla_parse_nested for brport_policy err %d\n", -+ err); -+ return err; -+ } -+ -+ err = ethsw_setlink_protinfo(netdev, tb); -+ return err; -+ } -+ -+ netdev_err(netdev, "nlmsg_find_attr found no AF_SPEC/PROTINFO\n"); -+ return -EOPNOTSUPP; -+} -+ -+static int __nla_put_netdev(struct sk_buff *skb, struct net_device *netdev, -+ struct ethsw_dev_priv *priv) -+{ -+ u8 operstate = netif_running(netdev) ? netdev->operstate : IF_OPER_DOWN; -+ int iflink; -+ int err; -+ -+ err = nla_put_string(skb, IFLA_IFNAME, netdev->name); -+ if (err) -+ goto nla_put_err; -+ err = nla_put_u32(skb, IFLA_MASTER, priv->netdev->ifindex); -+ if (err) -+ goto nla_put_err; -+ err = nla_put_u32(skb, IFLA_MTU, netdev->mtu); -+ if (err) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_OPERSTATE, operstate); -+ if (err) -+ goto nla_put_err; -+ if (netdev->addr_len) { -+ err = nla_put(skb, IFLA_ADDRESS, netdev->addr_len, -+ netdev->dev_addr); -+ if (err) -+ goto nla_put_err; -+ } -+ -+ iflink = dev_get_iflink(netdev); -+ if (netdev->ifindex != iflink) { -+ err = nla_put_u32(skb, IFLA_LINK, iflink); -+ if (err) -+ goto nla_put_err; -+ } -+ -+ return 0; -+ -+nla_put_err: -+ netdev_err(netdev, "nla_put_ err %d\n", err); -+ return err; -+} -+ -+static int __nla_put_port(struct sk_buff *skb, struct net_device *netdev, -+ struct ethsw_port_priv *port_priv) -+{ -+ struct nlattr *nest; -+ int err; -+ -+ u8 stp_state = port_priv->stp_state; -+ -+ if (port_priv->stp_state == DPSW_STP_STATE_BLOCKING) -+ stp_state = BR_STATE_BLOCKING; -+ -+ nest = nla_nest_start(skb, IFLA_PROTINFO | NLA_F_NESTED); -+ if (!nest) { -+ netdev_err(netdev, "nla_nest_start failed\n"); -+ return -ENOMEM; -+ } -+ -+ err = nla_put_u8(skb, IFLA_BRPORT_STATE, stp_state); -+ if (err) -+ goto nla_put_err; -+ err = nla_put_u16(skb, IFLA_BRPORT_PRIORITY, 0); -+ if (err) -+ goto nla_put_err; -+ err = nla_put_u32(skb, IFLA_BRPORT_COST, 0); -+ if (err) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_BRPORT_MODE, 0); -+ if (err) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_BRPORT_GUARD, 0); -+ if (err) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_BRPORT_PROTECT, 0); -+ if (err) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_BRPORT_FAST_LEAVE, 0); -+ if (err) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_BRPORT_LEARNING, -+ port_priv->ethsw_priv->learning); -+ if (err) -+ goto nla_put_err; -+ err = nla_put_u8(skb, IFLA_BRPORT_UNICAST_FLOOD, -+ port_priv->ethsw_priv->flood); -+ if (err) -+ goto nla_put_err; -+ nla_nest_end(skb, nest); -+ -+ return 0; -+ -+nla_put_err: -+ netdev_err(netdev, "nla_put_ err %d\n", err); -+ nla_nest_cancel(skb, nest); -+ return err; -+} -+ -+static int __nla_put_vlan(struct sk_buff *skb, struct net_device *netdev, -+ struct ethsw_dev_priv *priv, -+ struct ethsw_port_priv *port_priv) -+{ -+ struct nlattr *nest; -+ struct bridge_vlan_info vinfo; -+ const char *vlans; -+ u16 i; -+ int err; -+ -+ nest = nla_nest_start(skb, IFLA_AF_SPEC); -+ if (!nest) { -+ netdev_err(netdev, "nla_nest_start failed"); -+ return -ENOMEM; -+ } -+ -+ if (port_priv) -+ vlans = port_priv->vlans; -+ else -+ vlans = priv->vlans; -+ -+ for (i = 0; i < VLAN_VID_MASK+1; i++) { -+ vinfo.flags = 0; -+ vinfo.vid = i; -+ -+ if (vlans[i] & ETHSW_VLAN_UNTAGGED) -+ vinfo.flags |= BRIDGE_VLAN_INFO_UNTAGGED; -+ -+ if (vlans[i] & ETHSW_VLAN_PVID) -+ vinfo.flags |= BRIDGE_VLAN_INFO_PVID; -+ -+ if (vlans[i] & ETHSW_VLAN_MEMBER) { -+ err = nla_put(skb, IFLA_BRIDGE_VLAN_INFO, -+ sizeof(vinfo), &vinfo); -+ if (err) -+ goto nla_put_err; -+ } -+ } -+ -+ nla_nest_end(skb, nest); -+ -+ return 0; -+nla_put_err: -+ netdev_err(netdev, "nla_put_ err %d\n", err); -+ nla_nest_cancel(skb, nest); -+ return err; -+} -+ -+static int ethsw_getlink(struct sk_buff *skb, u32 pid, u32 seq, -+ struct net_device *netdev, u32 filter_mask, -+ int nlflags) -+{ -+ struct ethsw_dev_priv *priv; -+ struct ethsw_port_priv *port_priv = NULL; -+ struct ifinfomsg *hdr; -+ struct nlmsghdr *nlh; -+ int err; -+ -+ __get_priv(netdev, &priv, &port_priv); -+ -+ nlh = nlmsg_put(skb, pid, seq, RTM_NEWLINK, sizeof(*hdr), NLM_F_MULTI); -+ if (!nlh) -+ return -EMSGSIZE; -+ -+ hdr = nlmsg_data(nlh); -+ memset(hdr, 0, sizeof(*hdr)); -+ hdr->ifi_family = AF_BRIDGE; -+ hdr->ifi_type = netdev->type; -+ hdr->ifi_index = netdev->ifindex; -+ hdr->ifi_flags = dev_get_flags(netdev); -+ -+ err = __nla_put_netdev(skb, netdev, priv); -+ if (err) -+ goto nla_put_err; -+ -+ if (port_priv) { -+ err = __nla_put_port(skb, netdev, port_priv); -+ if (err) -+ goto nla_put_err; -+ } -+ -+ /* Check if the VID information is requested */ -+ if (filter_mask & RTEXT_FILTER_BRVLAN) { -+ err = __nla_put_vlan(skb, netdev, priv, port_priv); -+ if (err) -+ goto nla_put_err; -+ } -+ -+ nlmsg_end(skb, nlh); -+ return skb->len; -+ -+nla_put_err: -+ nlmsg_cancel(skb, nlh); -+ return -EMSGSIZE; -+} -+ -+static int ethsw_dellink_switch(struct ethsw_dev_priv *priv, u16 vid) -+{ -+ struct list_head *pos; -+ struct ethsw_port_priv *ppriv_local = NULL; -+ int err = 0; -+ -+ if (!priv->vlans[vid]) -+ return -ENOENT; -+ -+ err = dpsw_vlan_remove(priv->mc_io, 0, priv->dpsw_handle, vid); -+ if (err) { -+ netdev_err(priv->netdev, "dpsw_vlan_remove err %d\n", err); -+ return err; -+ } -+ priv->vlans[vid] = 0; -+ -+ list_for_each(pos, &priv->port_list) { -+ ppriv_local = list_entry(pos, struct ethsw_port_priv, -+ list); -+ ppriv_local->vlans[vid] = 0; -+ } -+ -+ return 0; -+} -+ -+static int ethsw_dellink_port(struct ethsw_dev_priv *priv, -+ struct ethsw_port_priv *port_priv, -+ u16 vid) -+{ -+ struct list_head *pos; -+ struct ethsw_port_priv *ppriv_local = NULL; -+ struct dpsw_vlan_if_cfg vcfg = { -+ .num_ifs = 1, -+ .if_id[0] = port_priv->port_index, -+ }; -+ unsigned int count = 0; -+ int err = 0; -+ -+ if (!port_priv->vlans[vid]) -+ return -ENOENT; -+ -+ /* VLAN will be deleted from switch if global flag is not set -+ * and is configured on only one port -+ */ -+ if (!(priv->vlans[vid] & ETHSW_VLAN_GLOBAL)) { -+ list_for_each(pos, &priv->port_list) { -+ ppriv_local = list_entry(pos, struct ethsw_port_priv, -+ list); -+ if (ppriv_local->vlans[vid] & ETHSW_VLAN_MEMBER) -+ count++; -+ } -+ -+ if (count == 1) -+ return ethsw_dellink_switch(priv, vid); -+ } -+ -+ err = dpsw_vlan_remove_if(priv->mc_io, 0, priv->dpsw_handle, -+ vid, &vcfg); -+ if (err) { -+ netdev_err(priv->netdev, "dpsw_vlan_remove_if err %d\n", err); -+ return err; -+ } -+ port_priv->vlans[vid] = 0; -+ return 0; -+} -+ -+static int ethsw_dellink(struct net_device *netdev, -+ struct nlmsghdr *nlh, -+ u16 flags) -+{ -+ struct nlattr *tb[IFLA_BRIDGE_MAX+1]; -+ struct nlattr *spec; -+ struct bridge_vlan_info *vinfo; -+ struct ethsw_dev_priv *priv; -+ struct ethsw_port_priv *port_priv = NULL; -+ int err = 0; -+ -+ spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); -+ if (!spec) -+ return 0; -+ -+ err = nla_parse_nested(tb, IFLA_BRIDGE_MAX, spec, ifla_br_policy); -+ if (err) -+ return err; -+ -+ if (!tb[IFLA_BRIDGE_VLAN_INFO]) -+ return -EOPNOTSUPP; -+ -+ vinfo = nla_data(tb[IFLA_BRIDGE_VLAN_INFO]); -+ -+ if (!vinfo->vid || vinfo->vid > VLAN_VID_MASK) -+ return -EINVAL; -+ -+ __get_priv(netdev, &priv, &port_priv); -+ -+ /* decide if command targets switch device or port */ -+ if (!port_priv) -+ err = ethsw_dellink_switch(priv, vinfo->vid); -+ else -+ err = ethsw_dellink_port(priv, port_priv, vinfo->vid); -+ -+ return err; -+} -+ -+static const struct net_device_ops ethsw_ops = { -+ .ndo_open = ðsw_open, -+ .ndo_stop = ðsw_stop, -+ -+ .ndo_bridge_setlink = ðsw_setlink, -+ .ndo_bridge_getlink = ðsw_getlink, -+ .ndo_bridge_dellink = ðsw_dellink, -+ -+ .ndo_start_xmit = ðsw_dropframe, -+}; -+ -+/*--------------------------------------------------------------------------- */ -+/* switch port netdevice ops */ -+ -+static int _ethsw_port_carrier_state_sync(struct net_device *netdev) -+{ -+ struct ethsw_port_priv *port_priv = netdev_priv(netdev); -+ struct dpsw_link_state state; -+ int err; -+ -+ err = dpsw_if_get_link_state(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ port_priv->port_index, &state); -+ if (unlikely(err)) { -+ netdev_err(netdev, "dpsw_if_get_link_state() err %d\n", err); -+ return err; -+ } -+ -+ WARN_ONCE(state.up > 1, "Garbage read into link_state"); -+ -+ if (state.up) -+ netif_carrier_on(port_priv->netdev); -+ else -+ netif_carrier_off(port_priv->netdev); -+ -+ return 0; -+} -+ -+static int ethsw_port_open(struct net_device *netdev) -+{ -+ struct ethsw_port_priv *port_priv = netdev_priv(netdev); -+ int err; -+ -+ if (!netif_oper_up(netdev) || -+ port_priv->stp_state == BR_STATE_DISABLED) -+ return 0; -+ -+ err = dpsw_if_enable(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ port_priv->port_index); -+ if (err) { -+ netdev_err(netdev, "dpsw_if_enable err %d\n", err); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int ethsw_port_stop(struct net_device *netdev) -+{ -+ struct ethsw_port_priv *port_priv = netdev_priv(netdev); -+ int err; -+ -+ err = dpsw_if_disable(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ port_priv->port_index); -+ if (err) { -+ netdev_err(netdev, "dpsw_if_disable err %d\n", err); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int ethsw_port_fdb_add_uc(struct net_device *netdev, -+ const unsigned char *addr) -+{ -+ struct ethsw_port_priv *port_priv = netdev_priv(netdev); -+ struct dpsw_fdb_unicast_cfg entry = {0}; -+ int err; -+ -+ entry.if_egress = port_priv->port_index; -+ entry.type = DPSW_FDB_ENTRY_STATIC; -+ ether_addr_copy(entry.mac_addr, addr); -+ -+ err = dpsw_fdb_add_unicast(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ 0, &entry); -+ if (err) -+ netdev_err(netdev, "dpsw_fdb_add_unicast err %d\n", err); -+ return err; -+} -+ -+static int ethsw_port_fdb_del_uc(struct net_device *netdev, -+ const unsigned char *addr) -+{ -+ struct ethsw_port_priv *port_priv = netdev_priv(netdev); -+ struct dpsw_fdb_unicast_cfg entry = {0}; -+ int err; -+ -+ entry.if_egress = port_priv->port_index; -+ entry.type = DPSW_FDB_ENTRY_STATIC; -+ ether_addr_copy(entry.mac_addr, addr); -+ -+ err = dpsw_fdb_remove_unicast(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ 0, &entry); -+ if (err) -+ netdev_err(netdev, "dpsw_fdb_remove_unicast err %d\n", err); -+ return err; -+} -+ -+static int ethsw_port_fdb_add_mc(struct net_device *netdev, -+ const unsigned char *addr) -+{ -+ struct ethsw_port_priv *port_priv = netdev_priv(netdev); -+ struct dpsw_fdb_multicast_cfg entry = {0}; -+ int err; -+ -+ ether_addr_copy(entry.mac_addr, addr); -+ entry.type = DPSW_FDB_ENTRY_STATIC; -+ entry.num_ifs = 1; -+ entry.if_id[0] = port_priv->port_index; -+ -+ err = dpsw_fdb_add_multicast(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ 0, &entry); -+ if (err) -+ netdev_err(netdev, "dpsw_fdb_add_multicast err %d\n", err); -+ return err; -+} -+ -+static int ethsw_port_fdb_del_mc(struct net_device *netdev, -+ const unsigned char *addr) -+{ -+ struct ethsw_port_priv *port_priv = netdev_priv(netdev); -+ struct dpsw_fdb_multicast_cfg entry = {0}; -+ int err; -+ -+ ether_addr_copy(entry.mac_addr, addr); -+ entry.type = DPSW_FDB_ENTRY_STATIC; -+ entry.num_ifs = 1; -+ entry.if_id[0] = port_priv->port_index; -+ -+ err = dpsw_fdb_remove_multicast(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ 0, &entry); -+ if (err) -+ netdev_err(netdev, "dpsw_fdb_remove_multicast err %d\n", err); -+ return err; -+} -+ -+static int _lookup_address(struct net_device *netdev, int is_uc, -+ const unsigned char *addr) -+{ -+ struct netdev_hw_addr *ha; -+ struct netdev_hw_addr_list *list = (is_uc) ? &netdev->uc : &netdev->mc; -+ -+ netif_addr_lock_bh(netdev); -+ list_for_each_entry(ha, &list->list, list) { -+ if (ether_addr_equal(ha->addr, addr)) { -+ netif_addr_unlock_bh(netdev); -+ return 1; -+ } -+ } -+ netif_addr_unlock_bh(netdev); -+ return 0; -+} -+ -+static int ethsw_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], -+ struct net_device *netdev, -+ const unsigned char *addr, u16 vid, -+ u16 flags) -+{ -+ struct list_head *pos; -+ struct ethsw_port_priv *port_priv = netdev_priv(netdev); -+ struct ethsw_dev_priv *priv = port_priv->ethsw_priv; -+ int err; -+ -+ /* TODO: add replace support when added to iproute bridge */ -+ if (!(flags & NLM_F_REQUEST)) { -+ netdev_err(netdev, -+ "ethsw_port_fdb_add unexpected flags value %08x\n", -+ flags); -+ return -EINVAL; -+ } -+ -+ if (is_unicast_ether_addr(addr)) { -+ /* if entry cannot be replaced, return error if exists */ -+ if (flags & NLM_F_EXCL || flags & NLM_F_APPEND) { -+ list_for_each(pos, &priv->port_list) { -+ port_priv = list_entry(pos, -+ struct ethsw_port_priv, -+ list); -+ if (_lookup_address(port_priv->netdev, -+ 1, addr)) -+ return -EEXIST; -+ } -+ } -+ -+ err = ethsw_port_fdb_add_uc(netdev, addr); -+ if (err) { -+ netdev_err(netdev, "ethsw_port_fdb_add_uc err %d\n", -+ err); -+ return err; -+ } -+ -+ /* we might have replaced an existing entry for a different -+ * switch port, make sure the address doesn't linger in any -+ * port address list -+ */ -+ list_for_each(pos, &priv->port_list) { -+ port_priv = list_entry(pos, struct ethsw_port_priv, -+ list); -+ dev_uc_del(port_priv->netdev, addr); -+ } -+ -+ err = dev_uc_add(netdev, addr); -+ if (err) { -+ netdev_err(netdev, "dev_uc_add err %d\n", err); -+ return err; -+ } -+ } else { -+ struct dpsw_fdb_multicast_cfg entry = { -+ .type = DPSW_FDB_ENTRY_STATIC, -+ .num_ifs = 0, -+ }; -+ -+ /* check if address is already set on this port */ -+ if (_lookup_address(netdev, 0, addr)) -+ return -EEXIST; -+ -+ /* check if the address exists on other port */ -+ ether_addr_copy(entry.mac_addr, addr); -+ err = dpsw_fdb_get_multicast(priv->mc_io, 0, priv->dpsw_handle, -+ 0, &entry); -+ if (!err) { -+ /* entry exists, can we replace it? */ -+ if (flags & NLM_F_EXCL) -+ return -EEXIST; -+ } else if (err != -ENAVAIL) { -+ netdev_err(netdev, "dpsw_fdb_get_unicast err %d\n", -+ err); -+ return err; -+ } -+ -+ err = ethsw_port_fdb_add_mc(netdev, addr); -+ if (err) { -+ netdev_err(netdev, "ethsw_port_fdb_add_mc err %d\n", -+ err); -+ return err; -+ } -+ -+ err = dev_mc_add(netdev, addr); -+ if (err) { -+ netdev_err(netdev, "dev_mc_add err %d\n", err); -+ return err; -+ } -+ } -+ -+ return 0; -+} -+ -+static int ethsw_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], -+ struct net_device *netdev, -+ const unsigned char *addr, u16 vid) -+{ -+ int err; -+ -+ if (is_unicast_ether_addr(addr)) { -+ err = ethsw_port_fdb_del_uc(netdev, addr); -+ if (err) { -+ netdev_err(netdev, "ethsw_port_fdb_del_uc err %d\n", -+ err); -+ return err; -+ } -+ -+ /* also delete if configured on port */ -+ err = dev_uc_del(netdev, addr); -+ if (err && err != -ENOENT) { -+ netdev_err(netdev, "dev_uc_del err %d\n", err); -+ return err; -+ } -+ } else { -+ if (!_lookup_address(netdev, 0, addr)) -+ return -ENOENT; -+ -+ err = dev_mc_del(netdev, addr); -+ if (err) { -+ netdev_err(netdev, "dev_mc_del err %d\n", err); -+ return err; -+ } -+ -+ err = ethsw_port_fdb_del_mc(netdev, addr); -+ if (err) { -+ netdev_err(netdev, "ethsw_port_fdb_del_mc err %d\n", -+ err); -+ return err; -+ } -+ } -+ -+ return 0; -+} -+ -+static struct rtnl_link_stats64 * -+ethsw_port_get_stats(struct net_device *netdev, -+ struct rtnl_link_stats64 *storage) -+{ -+ struct ethsw_port_priv *port_priv = netdev_priv(netdev); -+ u64 tmp; -+ int err; -+ -+ err = dpsw_if_get_counter(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ port_priv->port_index, -+ DPSW_CNT_ING_FRAME, &storage->rx_packets); -+ if (err) -+ goto error; -+ -+ err = dpsw_if_get_counter(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ port_priv->port_index, -+ DPSW_CNT_EGR_FRAME, &storage->tx_packets); -+ if (err) -+ goto error; -+ -+ err = dpsw_if_get_counter(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ port_priv->port_index, -+ DPSW_CNT_ING_BYTE, &storage->rx_bytes); -+ if (err) -+ goto error; -+ -+ err = dpsw_if_get_counter(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ port_priv->port_index, -+ DPSW_CNT_EGR_BYTE, &storage->tx_bytes); -+ if (err) -+ goto error; -+ -+ err = dpsw_if_get_counter(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ port_priv->port_index, -+ DPSW_CNT_ING_FRAME_DISCARD, -+ &storage->rx_dropped); -+ if (err) -+ goto error; -+ -+ err = dpsw_if_get_counter(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ port_priv->port_index, -+ DPSW_CNT_ING_FLTR_FRAME, -+ &tmp); -+ if (err) -+ goto error; -+ storage->rx_dropped += tmp; -+ -+ err = dpsw_if_get_counter(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ port_priv->port_index, -+ DPSW_CNT_EGR_FRAME_DISCARD, -+ &storage->tx_dropped); -+ if (err) -+ goto error; -+ -+ return storage; -+ -+error: -+ netdev_err(netdev, "dpsw_if_get_counter err %d\n", err); -+ return storage; -+} -+ -+static const struct net_device_ops ethsw_port_ops = { -+ .ndo_open = ðsw_port_open, -+ .ndo_stop = ðsw_port_stop, -+ -+ .ndo_fdb_add = ðsw_port_fdb_add, -+ .ndo_fdb_del = ðsw_port_fdb_del, -+ .ndo_fdb_dump = &ndo_dflt_fdb_dump, -+ -+ .ndo_get_stats64 = ðsw_port_get_stats, -+ -+ .ndo_start_xmit = ðsw_dropframe, -+}; -+ -+static struct { -+ enum dpsw_counter id; -+ char name[ETH_GSTRING_LEN]; -+} ethsw_ethtool_counters[] = { -+ {DPSW_CNT_ING_FRAME, "rx frames"}, -+ {DPSW_CNT_ING_BYTE, "rx bytes"}, -+ {DPSW_CNT_ING_FLTR_FRAME, "rx filtered frames"}, -+ {DPSW_CNT_ING_FRAME_DISCARD, "rx discarded frames"}, -+ {DPSW_CNT_ING_BCAST_FRAME, "rx b-cast frames"}, -+ {DPSW_CNT_ING_BCAST_BYTES, "rx b-cast bytes"}, -+ {DPSW_CNT_ING_MCAST_FRAME, "rx m-cast frames"}, -+ {DPSW_CNT_ING_MCAST_BYTE, "rx m-cast bytes"}, -+ {DPSW_CNT_EGR_FRAME, "tx frames"}, -+ {DPSW_CNT_EGR_BYTE, "tx bytes"}, -+ {DPSW_CNT_EGR_FRAME_DISCARD, "tx discarded frames"}, -+ -+}; -+ -+static int ethsw_ethtool_get_sset_count(struct net_device *dev, int sset) -+{ -+ switch (sset) { -+ case ETH_SS_STATS: -+ return ARRAY_SIZE(ethsw_ethtool_counters); -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+static void ethsw_ethtool_get_strings(struct net_device *netdev, -+ u32 stringset, u8 *data) -+{ -+ int i; -+ -+ switch (stringset) { -+ case ETH_SS_STATS: -+ for (i = 0; i < ARRAY_SIZE(ethsw_ethtool_counters); i++) -+ memcpy(data + i * ETH_GSTRING_LEN, -+ ethsw_ethtool_counters[i].name, ETH_GSTRING_LEN); -+ break; -+ } -+} -+ -+static void ethsw_ethtool_get_stats(struct net_device *netdev, -+ struct ethtool_stats *stats, -+ u64 *data) -+{ -+ struct ethsw_port_priv *port_priv = netdev_priv(netdev); -+ int i; -+ int err; -+ -+ for (i = 0; i < ARRAY_SIZE(ethsw_ethtool_counters); i++) { -+ err = dpsw_if_get_counter(port_priv->ethsw_priv->mc_io, 0, -+ port_priv->ethsw_priv->dpsw_handle, -+ port_priv->port_index, -+ ethsw_ethtool_counters[i].id, -+ &data[i]); -+ if (err) -+ netdev_err(netdev, "dpsw_if_get_counter[%s] err %d\n", -+ ethsw_ethtool_counters[i].name, err); -+ } -+} -+ -+static const struct ethtool_ops ethsw_port_ethtool_ops = { -+ .get_strings = ðsw_ethtool_get_strings, -+ .get_ethtool_stats = ðsw_ethtool_get_stats, -+ .get_sset_count = ðsw_ethtool_get_sset_count, -+}; -+ -+/* -------------------------------------------------------------------------- */ -+/* ethsw driver functions */ -+ -+static int ethsw_links_state_update(struct ethsw_dev_priv *priv) -+{ -+ struct list_head *pos; -+ struct ethsw_port_priv *port_priv; -+ int err; -+ -+ list_for_each(pos, &priv->port_list) { -+ port_priv = list_entry(pos, struct ethsw_port_priv, -+ list); -+ -+ err = _ethsw_port_carrier_state_sync(port_priv->netdev); -+ if (err) -+ netdev_err(port_priv->netdev, -+ "_ethsw_port_carrier_state_sync err %d\n", -+ err); -+ } -+ -+ return 0; -+} -+ -+static irqreturn_t ethsw_irq0_handler(int irq_num, void *arg) -+{ -+ return IRQ_WAKE_THREAD; -+} -+ -+static irqreturn_t _ethsw_irq0_handler_thread(int irq_num, void *arg) -+{ -+ struct device *dev = (struct device *)arg; -+ struct fsl_mc_device *sw_dev = to_fsl_mc_device(dev); -+ struct net_device *netdev = dev_get_drvdata(dev); -+ struct ethsw_dev_priv *priv = netdev_priv(netdev); -+ -+ struct fsl_mc_io *io = priv->mc_io; -+ uint16_t token = priv->dpsw_handle; -+ int irq_index = DPSW_IRQ_INDEX_IF; -+ -+ /* Mask the events and the if_id reserved bits to be cleared on read */ -+ uint32_t status = DPSW_IRQ_EVENT_LINK_CHANGED | 0xFFFF0000; -+ int err; -+ -+ /* Sanity check */ -+ if (WARN_ON(!sw_dev || !sw_dev->irqs || !sw_dev->irqs[irq_index])) -+ goto out; -+ if (WARN_ON(sw_dev->irqs[irq_index]->msi_desc->irq != irq_num)) -+ goto out; -+ -+ err = dpsw_get_irq_status(io, 0, token, irq_index, &status); -+ if (unlikely(err)) { -+ netdev_err(netdev, "Can't get irq status (err %d)", err); -+ -+ err = dpsw_clear_irq_status(io, 0, token, irq_index, -+ 0xFFFFFFFF); -+ if (unlikely(err)) -+ netdev_err(netdev, "Can't clear irq status (err %d)", -+ err); -+ goto out; -+ } -+ -+ if (status & DPSW_IRQ_EVENT_LINK_CHANGED) { -+ err = ethsw_links_state_update(priv); -+ if (unlikely(err)) -+ goto out; -+ } -+ -+out: -+ return IRQ_HANDLED; -+} -+ -+static int ethsw_setup_irqs(struct fsl_mc_device *sw_dev) -+{ -+ struct device *dev = &sw_dev->dev; -+ struct net_device *netdev = dev_get_drvdata(dev); -+ struct ethsw_dev_priv *priv = netdev_priv(netdev); -+ int err = 0; -+ struct fsl_mc_device_irq *irq; -+ const int irq_index = DPSW_IRQ_INDEX_IF; -+ uint32_t mask = DPSW_IRQ_EVENT_LINK_CHANGED; -+ -+ err = fsl_mc_allocate_irqs(sw_dev); -+ if (unlikely(err)) { -+ dev_err(dev, "MC irqs allocation failed\n"); -+ return err; -+ } -+ -+ if (WARN_ON(sw_dev->obj_desc.irq_count != DPSW_MAX_IRQ_NUM)) { -+ err = -EINVAL; -+ goto free_irq; -+ } -+ -+ err = dpsw_set_irq_enable(priv->mc_io, 0, priv->dpsw_handle, -+ irq_index, 0); -+ if (unlikely(err)) { -+ dev_err(dev, "dpsw_set_irq_enable err %d\n", err); -+ goto free_irq; -+ } -+ -+ irq = sw_dev->irqs[irq_index]; -+ -+ err = devm_request_threaded_irq(dev, irq->msi_desc->irq, -+ ethsw_irq0_handler, -+ _ethsw_irq0_handler_thread, -+ IRQF_NO_SUSPEND | IRQF_ONESHOT, -+ dev_name(dev), dev); -+ if (unlikely(err)) { -+ dev_err(dev, "devm_request_threaded_irq(): %d", err); -+ goto free_irq; -+ } -+ -+ err = dpsw_set_irq_mask(priv->mc_io, 0, priv->dpsw_handle, -+ irq_index, mask); -+ if (unlikely(err)) { -+ dev_err(dev, "dpsw_set_irq_mask(): %d", err); -+ goto free_devm_irq; -+ } -+ -+ err = dpsw_set_irq_enable(priv->mc_io, 0, priv->dpsw_handle, -+ irq_index, 1); -+ if (unlikely(err)) { -+ dev_err(dev, "dpsw_set_irq_enable(): %d", err); -+ goto free_devm_irq; -+ } -+ -+ return 0; -+ -+free_devm_irq: -+ devm_free_irq(dev, irq->msi_desc->irq, dev); -+free_irq: -+ fsl_mc_free_irqs(sw_dev); -+ return err; -+} -+ -+static void ethsw_teardown_irqs(struct fsl_mc_device *sw_dev) -+{ -+ struct device *dev = &sw_dev->dev; -+ struct net_device *netdev = dev_get_drvdata(dev); -+ struct ethsw_dev_priv *priv = netdev_priv(netdev); -+ -+ dpsw_set_irq_enable(priv->mc_io, 0, priv->dpsw_handle, -+ DPSW_IRQ_INDEX_IF, 0); -+ devm_free_irq(dev, -+ sw_dev->irqs[DPSW_IRQ_INDEX_IF]->msi_desc->irq, -+ dev); -+ fsl_mc_free_irqs(sw_dev); -+} -+ -+static int __cold -+ethsw_init(struct fsl_mc_device *sw_dev) -+{ -+ struct device *dev = &sw_dev->dev; -+ struct ethsw_dev_priv *priv; -+ struct net_device *netdev; -+ int err = 0; -+ u16 i; -+ const struct dpsw_stp_cfg stp_cfg = { -+ .vlan_id = 1, -+ .state = DPSW_STP_STATE_FORWARDING, -+ }; -+ -+ netdev = dev_get_drvdata(dev); -+ priv = netdev_priv(netdev); -+ -+ priv->dev_id = sw_dev->obj_desc.id; -+ -+ err = dpsw_open(priv->mc_io, 0, priv->dev_id, &priv->dpsw_handle); -+ if (err) { -+ dev_err(dev, "dpsw_open err %d\n", err); -+ goto err_exit; -+ } -+ if (!priv->dpsw_handle) { -+ dev_err(dev, "dpsw_open returned null handle but no error\n"); -+ err = -EFAULT; -+ goto err_exit; -+ } -+ -+ err = dpsw_get_attributes(priv->mc_io, 0, priv->dpsw_handle, -+ &priv->sw_attr); -+ if (err) { -+ dev_err(dev, "dpsw_get_attributes err %d\n", err); -+ goto err_close; -+ } -+ -+ /* Minimum supported DPSW version check */ -+ if (priv->sw_attr.version.major < DPSW_MIN_VER_MAJOR || -+ (priv->sw_attr.version.major == DPSW_MIN_VER_MAJOR && -+ priv->sw_attr.version.minor < DPSW_MIN_VER_MINOR)) { -+ dev_err(dev, "DPSW version %d:%d not supported. Use %d.%d or greater.\n", -+ priv->sw_attr.version.major, -+ priv->sw_attr.version.minor, -+ DPSW_MIN_VER_MAJOR, DPSW_MIN_VER_MINOR); -+ err = -ENOTSUPP; -+ goto err_close; -+ } -+ -+ err = dpsw_reset(priv->mc_io, 0, priv->dpsw_handle); -+ if (err) { -+ dev_err(dev, "dpsw_reset err %d\n", err); -+ goto err_close; -+ } -+ -+ err = dpsw_fdb_set_learning_mode(priv->mc_io, 0, priv->dpsw_handle, 0, -+ DPSW_FDB_LEARNING_MODE_HW); -+ if (err) { -+ dev_err(dev, "dpsw_fdb_set_learning_mode err %d\n", err); -+ goto err_close; -+ } -+ -+ for (i = 0; i < priv->sw_attr.num_ifs; i++) { -+ err = dpsw_if_set_stp(priv->mc_io, 0, priv->dpsw_handle, i, -+ &stp_cfg); -+ if (err) { -+ dev_err(dev, "dpsw_if_set_stp err %d for port %d\n", -+ err, i); -+ goto err_close; -+ } -+ -+ err = dpsw_if_set_broadcast(priv->mc_io, 0, -+ priv->dpsw_handle, i, 1); -+ if (err) { -+ dev_err(dev, -+ "dpsw_if_set_broadcast err %d for port %d\n", -+ err, i); -+ goto err_close; -+ } -+ } -+ -+ return 0; -+ -+err_close: -+ dpsw_close(priv->mc_io, 0, priv->dpsw_handle); -+err_exit: -+ return err; -+} -+ -+static int __cold -+ethsw_takedown(struct fsl_mc_device *sw_dev) -+{ -+ struct device *dev = &sw_dev->dev; -+ struct net_device *netdev; -+ struct ethsw_dev_priv *priv; -+ int err; -+ -+ netdev = dev_get_drvdata(dev); -+ priv = netdev_priv(netdev); -+ -+ err = dpsw_close(priv->mc_io, 0, priv->dpsw_handle); -+ if (err) -+ dev_warn(dev, "dpsw_close err %d\n", err); -+ -+ return 0; -+} -+ -+static int __cold -+ethsw_remove(struct fsl_mc_device *sw_dev) -+{ -+ struct device *dev; -+ struct net_device *netdev; -+ struct ethsw_dev_priv *priv; -+ struct ethsw_port_priv *port_priv; -+ struct list_head *pos; -+ -+ dev = &sw_dev->dev; -+ netdev = dev_get_drvdata(dev); -+ priv = netdev_priv(netdev); -+ -+ list_for_each(pos, &priv->port_list) { -+ port_priv = list_entry(pos, struct ethsw_port_priv, list); -+ -+ rtnl_lock(); -+ netdev_upper_dev_unlink(port_priv->netdev, netdev); -+ rtnl_unlock(); -+ -+ unregister_netdev(port_priv->netdev); -+ free_netdev(port_priv->netdev); -+ } -+ -+ ethsw_teardown_irqs(sw_dev); -+ -+ unregister_netdev(netdev); -+ -+ ethsw_takedown(sw_dev); -+ fsl_mc_portal_free(priv->mc_io); -+ -+ dev_set_drvdata(dev, NULL); -+ free_netdev(netdev); -+ -+ return 0; -+} -+ -+static int __cold -+ethsw_probe(struct fsl_mc_device *sw_dev) -+{ -+ struct device *dev; -+ struct net_device *netdev = NULL; -+ struct ethsw_dev_priv *priv = NULL; -+ int err = 0; -+ u16 i; -+ const char def_mcast[ETH_ALEN] = { -+ 0x01, 0x00, 0x5e, 0x00, 0x00, 0x01, -+ }; -+ char port_name[IFNAMSIZ]; -+ -+ dev = &sw_dev->dev; -+ -+ /* register switch device, it's for management only - no I/O */ -+ netdev = alloc_etherdev(sizeof(*priv)); -+ if (!netdev) { -+ dev_err(dev, "alloc_etherdev error\n"); -+ return -ENOMEM; -+ } -+ netdev->netdev_ops = ðsw_ops; -+ -+ SET_NETDEV_DEV(netdev, dev); -+ dev_set_drvdata(dev, netdev); -+ -+ priv = netdev_priv(netdev); -+ priv->netdev = netdev; -+ -+ err = fsl_mc_portal_allocate(sw_dev, 0, &priv->mc_io); -+ if (err) { -+ dev_err(dev, "fsl_mc_portal_allocate err %d\n", err); -+ goto err_free_netdev; -+ } -+ if (!priv->mc_io) { -+ dev_err(dev, "fsl_mc_portal_allocate returned null handle but no error\n"); -+ err = -EFAULT; -+ goto err_free_netdev; -+ } -+ -+ err = ethsw_init(sw_dev); -+ if (err) { -+ dev_err(dev, "switch init err %d\n", err); -+ goto err_free_cmdport; -+ } -+ -+ netdev->flags = netdev->flags | IFF_PROMISC | IFF_MASTER; -+ -+ /* TODO: should we hold rtnl_lock here? We can't register_netdev under -+ * lock -+ */ -+ dev_alloc_name(netdev, "sw%d"); -+ err = register_netdev(netdev); -+ if (err < 0) { -+ dev_err(dev, "register_netdev error %d\n", err); -+ goto err_takedown; -+ } -+ if (err) -+ dev_info(dev, "register_netdev res %d\n", err); -+ -+ /* VLAN 1 is implicitly configured on the switch */ -+ priv->vlans[1] = ETHSW_VLAN_MEMBER; -+ /* Flooding, learning are implicitly enabled */ -+ priv->learning = true; -+ priv->flood = true; -+ -+ /* register switch ports */ -+ snprintf(port_name, IFNAMSIZ, "%sp%%d", netdev->name); -+ -+ INIT_LIST_HEAD(&priv->port_list); -+ for (i = 0; i < priv->sw_attr.num_ifs; i++) { -+ struct net_device *port_netdev; -+ struct ethsw_port_priv *port_priv; -+ -+ port_netdev = alloc_etherdev(sizeof(struct ethsw_port_priv)); -+ if (!port_netdev) { -+ dev_err(dev, "alloc_etherdev error\n"); -+ goto err_takedown; -+ } -+ -+ port_priv = netdev_priv(port_netdev); -+ port_priv->netdev = port_netdev; -+ port_priv->ethsw_priv = priv; -+ -+ port_priv->port_index = i; -+ port_priv->stp_state = BR_STATE_FORWARDING; -+ /* VLAN 1 is configured by default on all switch ports */ -+ port_priv->vlans[1] = ETHSW_VLAN_MEMBER | ETHSW_VLAN_UNTAGGED | -+ ETHSW_VLAN_PVID; -+ -+ SET_NETDEV_DEV(port_netdev, dev); -+ port_netdev->netdev_ops = ðsw_port_ops; -+ port_netdev->ethtool_ops = ðsw_port_ethtool_ops; -+ -+ port_netdev->flags = port_netdev->flags | -+ IFF_PROMISC | IFF_SLAVE; -+ -+ dev_alloc_name(port_netdev, port_name); -+ err = register_netdev(port_netdev); -+ if (err < 0) { -+ dev_err(dev, "register_netdev error %d\n", err); -+ free_netdev(port_netdev); -+ goto err_takedown; -+ } -+ -+ rtnl_lock(); -+ -+ err = netdev_master_upper_dev_link(port_netdev, netdev, NULL, NULL); -+ if (err) { -+ dev_err(dev, "netdev_master_upper_dev_link error %d\n", -+ err); -+ unregister_netdev(port_netdev); -+ free_netdev(port_netdev); -+ rtnl_unlock(); -+ goto err_takedown; -+ } -+ -+ rtmsg_ifinfo(RTM_NEWLINK, port_netdev, IFF_SLAVE, GFP_KERNEL); -+ -+ rtnl_unlock(); -+ -+ list_add(&port_priv->list, &priv->port_list); -+ -+ /* TODO: implmenet set_rm_mode instead of this */ -+ err = ethsw_port_fdb_add_mc(port_netdev, def_mcast); -+ if (err) -+ dev_warn(&netdev->dev, -+ "ethsw_port_fdb_add_mc err %d\n", err); -+ -+ -+ /* sync carrier state */ -+ err = _ethsw_port_carrier_state_sync(port_netdev); -+ if (err) -+ netdev_err(netdev, -+ "_ethsw_port_carrier_state_sync err %d\n", -+ err); -+ } -+ -+ /* the switch starts up enabled */ -+ rtnl_lock(); -+ err = dev_open(netdev); -+ rtnl_unlock(); -+ if (err) -+ dev_warn(dev, "dev_open err %d\n", err); -+ -+ /* setup irqs */ -+ err = ethsw_setup_irqs(sw_dev); -+ if (unlikely(err)) { -+ dev_warn(dev, "ethsw_setup_irqs err %d\n", err); -+ goto err_takedown; -+ } -+ -+ dev_info(&netdev->dev, -+ "probed %d port switch\n", priv->sw_attr.num_ifs); -+ return 0; -+ -+err_takedown: -+ ethsw_remove(sw_dev); -+err_free_cmdport: -+ fsl_mc_portal_free(priv->mc_io); -+err_free_netdev: -+ dev_set_drvdata(dev, NULL); -+ free_netdev(netdev); -+ -+ return err; -+} -+ -+static const struct fsl_mc_device_match_id ethsw_match_id_table[] = { -+ { -+ .vendor = FSL_MC_VENDOR_FREESCALE, -+ .obj_type = "dpsw", -+ .ver_major = DPSW_VER_MAJOR, -+ .ver_minor = DPSW_VER_MINOR, -+ }, -+ {} -+}; -+ -+static struct fsl_mc_driver eth_sw_drv = { -+ .driver = { -+ .name = KBUILD_MODNAME, -+ .owner = THIS_MODULE, -+ }, -+ .probe = ethsw_probe, -+ .remove = ethsw_remove, -+ .match_id_table = ethsw_match_id_table, -+}; -+ -+module_fsl_mc_driver(eth_sw_drv); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("DPAA2 Ethernet Switch Driver (prototype)"); ---- a/drivers/staging/fsl-mc/include/net.h -+++ b/drivers/staging/fsl-mc/include/net.h -@@ -367,7 +367,6 @@ - /*************************** GTP fields ************************************/ - #define NH_FLD_GTP_TEID (1) - -- - /* Protocol options */ - - /* Ethernet options */ diff --git a/target/linux/layerscape/patches-4.4/7221-dpaa2-ethsw-match-id-cleanup.patch b/target/linux/layerscape/patches-4.4/7221-dpaa2-ethsw-match-id-cleanup.patch deleted file mode 100644 index eac1340266..0000000000 --- a/target/linux/layerscape/patches-4.4/7221-dpaa2-ethsw-match-id-cleanup.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 535826c8b725f752e5da17ea576d6d96e7d53f13 Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Fri, 15 Jul 2016 13:13:41 -0500 -Subject: [PATCH 221/226] dpaa2-ethsw: match id cleanup - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-dpaa2/ethsw/switch.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/staging/fsl-dpaa2/ethsw/switch.c -+++ b/drivers/staging/fsl-dpaa2/ethsw/switch.c -@@ -1685,12 +1685,10 @@ err_free_netdev: - return err; - } - --static const struct fsl_mc_device_match_id ethsw_match_id_table[] = { -+static const struct fsl_mc_device_id ethsw_match_id_table[] = { - { - .vendor = FSL_MC_VENDOR_FREESCALE, - .obj_type = "dpsw", -- .ver_major = DPSW_VER_MAJOR, -- .ver_minor = DPSW_VER_MINOR, - }, - {} - }; diff --git a/target/linux/layerscape/patches-4.4/7222-dpaa2-ethsw-fix-compile-error-on-backport-to-4.4.patch b/target/linux/layerscape/patches-4.4/7222-dpaa2-ethsw-fix-compile-error-on-backport-to-4.4.patch deleted file mode 100644 index 16499218af..0000000000 --- a/target/linux/layerscape/patches-4.4/7222-dpaa2-ethsw-fix-compile-error-on-backport-to-4.4.patch +++ /dev/null @@ -1,21 +0,0 @@ -From c51ed10a001d3fd5b80b7bb92f2d5182f1d9fa5a Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Thu, 25 Aug 2016 16:10:12 -0500 -Subject: [PATCH 222/226] dpaa2-ethsw: fix compile error on backport to 4.4 - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-dpaa2/ethsw/switch.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/staging/fsl-dpaa2/ethsw/switch.c -+++ b/drivers/staging/fsl-dpaa2/ethsw/switch.c -@@ -1625,7 +1625,7 @@ ethsw_probe(struct fsl_mc_device *sw_dev - - rtnl_lock(); - -- err = netdev_master_upper_dev_link(port_netdev, netdev, NULL, NULL); -+ err = netdev_master_upper_dev_link(port_netdev, netdev); - if (err) { - dev_err(dev, "netdev_master_upper_dev_link error %d\n", - err); diff --git a/target/linux/layerscape/patches-4.4/7223-irqdomain-Added-domain-bus-token-DOMAIN_BUS_FSL_MC_M.patch b/target/linux/layerscape/patches-4.4/7223-irqdomain-Added-domain-bus-token-DOMAIN_BUS_FSL_MC_M.patch deleted file mode 100644 index 1d719e0887..0000000000 --- a/target/linux/layerscape/patches-4.4/7223-irqdomain-Added-domain-bus-token-DOMAIN_BUS_FSL_MC_M.patch +++ /dev/null @@ -1,26 +0,0 @@ -From b565bd9a6011819ff66bd4fa0a50f7e54dff2753 Mon Sep 17 00:00:00 2001 -From: "J. German Rivera" -Date: Wed, 6 Jan 2016 16:03:19 -0600 -Subject: [PATCH 223/226] irqdomain: Added domain bus token - DOMAIN_BUS_FSL_MC_MSI - -Since an FSL-MC bus is a new bus type that is neither PCI nor -PLATFORM, we need a new domain bus token to disambiguate the -IRQ domain for FSL-MC MSIs. - -Signed-off-by: J. German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - include/linux/irqdomain.h | 1 + - 1 file changed, 1 insertion(+) - ---- a/include/linux/irqdomain.h -+++ b/include/linux/irqdomain.h -@@ -73,6 +73,7 @@ enum irq_domain_bus_token { - DOMAIN_BUS_PCI_MSI, - DOMAIN_BUS_PLATFORM_MSI, - DOMAIN_BUS_NEXUS, -+ DOMAIN_BUS_FSL_MC_MSI, - }; - - /** diff --git a/target/linux/layerscape/patches-4.4/7224-fsl-mc-msi-Added-FSL-MC-specific-member-to-the-msi_d.patch b/target/linux/layerscape/patches-4.4/7224-fsl-mc-msi-Added-FSL-MC-specific-member-to-the-msi_d.patch deleted file mode 100644 index 8dd11f4160..0000000000 --- a/target/linux/layerscape/patches-4.4/7224-fsl-mc-msi-Added-FSL-MC-specific-member-to-the-msi_d.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 359c7977e003781024154da61e55181b92b12bdf Mon Sep 17 00:00:00 2001 -From: "J. German Rivera" -Date: Wed, 6 Jan 2016 16:03:20 -0600 -Subject: [PATCH 224/226] fsl-mc: msi: Added FSL-MC-specific member to the - msi_desc's union - -FSL-MC is a bus type different from PCI and platform, so it needs -its own member in the msi_desc's union. - -Signed-off-by: J. German Rivera -Signed-off-by: Greg Kroah-Hartman ---- - include/linux/msi.h | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/include/linux/msi.h -+++ b/include/linux/msi.h -@@ -33,6 +33,14 @@ struct platform_msi_desc { - }; - - /** -+ * fsl_mc_msi_desc - FSL-MC device specific msi descriptor data -+ * @msi_index: The index of the MSI descriptor -+ */ -+struct fsl_mc_msi_desc { -+ u16 msi_index; -+}; -+ -+/** - * struct msi_desc - Descriptor structure for MSI based interrupts - * @list: List head for management - * @irq: The base interrupt number -@@ -87,6 +95,7 @@ struct msi_desc { - * tree wide cleanup. - */ - struct platform_msi_desc platform; -+ struct fsl_mc_msi_desc fsl_mc; - }; - }; - diff --git a/target/linux/layerscape/patches-4.4/7225-dpaa2-evb-fix-4.4-backport-compile-error.patch b/target/linux/layerscape/patches-4.4/7225-dpaa2-evb-fix-4.4-backport-compile-error.patch deleted file mode 100644 index 2815d46e36..0000000000 --- a/target/linux/layerscape/patches-4.4/7225-dpaa2-evb-fix-4.4-backport-compile-error.patch +++ /dev/null @@ -1,21 +0,0 @@ -From dbdf9b1fe83f88090d88bce980885df4fac46162 Mon Sep 17 00:00:00 2001 -From: Stuart Yoder -Date: Thu, 25 Aug 2016 11:17:52 -0500 -Subject: [PATCH 225/226] dpaa2-evb: fix 4.4 backport compile error - -Signed-off-by: Stuart Yoder ---- - drivers/staging/fsl-dpaa2/evb/evb.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/staging/fsl-dpaa2/evb/evb.c -+++ b/drivers/staging/fsl-dpaa2/evb/evb.c -@@ -1153,7 +1153,7 @@ static int evb_probe(struct fsl_mc_devic - } - - rtnl_lock(); -- err = netdev_master_upper_dev_link(port_netdev, netdev, NULL, NULL); -+ err = netdev_master_upper_dev_link(port_netdev, netdev); - if (unlikely(err)) { - dev_err(dev, "netdev_master_upper_dev_link err %d\n", - err); diff --git a/target/linux/layerscape/patches-4.4/7226-dpaa_eth-fix-adjust_link-for-10G-2.5G.patch b/target/linux/layerscape/patches-4.4/7226-dpaa_eth-fix-adjust_link-for-10G-2.5G.patch deleted file mode 100644 index f5a2ed73cc..0000000000 --- a/target/linux/layerscape/patches-4.4/7226-dpaa_eth-fix-adjust_link-for-10G-2.5G.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 09a3bd3bb7e59703bfa5fa580436b4a85b15cfb0 Mon Sep 17 00:00:00 2001 -From: Shaohui Xie -Date: Fri, 22 Apr 2016 11:26:14 +0800 -Subject: [PATCH] dpaa_eth: fix adjust_link for 10G & 2.5G - -We don't support adjust link for 10G & 2.5G. - -Signed-off-by: Shaohui Xie ---- - drivers/net/ethernet/freescale/sdk_dpaa/mac-api.c | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - ---- a/drivers/net/ethernet/freescale/sdk_dpaa/mac-api.c -+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac-api.c -@@ -409,6 +409,10 @@ void get_pause_cfg(struct mac_device *ma - } - EXPORT_SYMBOL(get_pause_cfg); - -+static void adjust_link_void(struct net_device *net_dev) -+{ -+} -+ - static void adjust_link(struct net_device *net_dev) - { - struct dpa_priv_s *priv = netdev_priv(net_dev); -@@ -473,7 +477,7 @@ static int xgmac_init_phy(struct net_dev - mac_dev->phy_if); - else - phy_dev = of_phy_connect(net_dev, mac_dev->phy_node, -- &adjust_link, 0, mac_dev->phy_if); -+ &adjust_link_void, 0, mac_dev->phy_if); - if (unlikely(phy_dev == NULL) || IS_ERR(phy_dev)) { - netdev_err(net_dev, "Could not attach to PHY %s\n", - mac_dev->phy_node ? -@@ -506,7 +510,7 @@ static int memac_init_phy(struct net_dev - return 0; - } else - phy_dev = of_phy_connect(net_dev, mac_dev->phy_node, -- &adjust_link, 0, -+ &adjust_link_void, 0, - mac_dev->phy_if); - } else { - if (!mac_dev->phy_node) diff --git a/target/linux/layerscape/patches-4.4/8026-cpufreq-qoriq-Don-t-look-at-clock-implementation-det.patch b/target/linux/layerscape/patches-4.4/8026-cpufreq-qoriq-Don-t-look-at-clock-implementation-det.patch deleted file mode 100644 index e8cb061a54..0000000000 --- a/target/linux/layerscape/patches-4.4/8026-cpufreq-qoriq-Don-t-look-at-clock-implementation-det.patch +++ /dev/null @@ -1,274 +0,0 @@ -From 8f3768a7c649526f821a6a4cd32cc44a8e7fa317 Mon Sep 17 00:00:00 2001 -From: Scott Wood -Date: Fri, 15 Jan 2016 07:34:33 +0000 -Subject: [PATCH 26/70] cpufreq: qoriq: Don't look at clock implementation - details - -Get the CPU clock's potential parent clocks from the clock interface -itself, rather than manually parsing the clocks property to find a -phandle, looking at the clock-names property of that, and assuming that -those are valid parent clocks for the cpu clock. - -This is necessary now that the clocks are generated based on the clock -driver's knowledge of the chip rather than a fragile device-tree -description of the mux options. - -We can now rely on the clock driver to ensure that the mux only exposes -options that are valid. The cpufreq driver was currently being overly -conservative in some cases -- for example, the "min_cpufreq = -get_bus_freq()" restriction only applies to chips with erratum -A-004510, and whether the freq_mask used on p5020 is needed depends on -the actual frequencies of the PLLs (FWIW, p5040 has a similar -limitation but its .freq_mask was zero) -- and the frequency mask -mechanism made assumptions about particular parent clock indices that -are no longer valid. - -Signed-off-by: Scott Wood -Acked-by: Viresh Kumar ---- - drivers/cpufreq/qoriq-cpufreq.c | 138 ++++++++++++--------------------------- - 1 file changed, 41 insertions(+), 97 deletions(-) - ---- a/drivers/cpufreq/qoriq-cpufreq.c -+++ b/drivers/cpufreq/qoriq-cpufreq.c -@@ -11,6 +11,7 @@ - #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - - #include -+#include - #include - #include - #include -@@ -35,53 +36,20 @@ struct cpu_data { - struct cpufreq_frequency_table *table; - }; - -+/* -+ * Don't use cpufreq on this SoC -- used when the SoC would have otherwise -+ * matched a more generic compatible. -+ */ -+#define SOC_BLACKLIST 1 -+ - /** - * struct soc_data - SoC specific data -- * @freq_mask: mask the disallowed frequencies -- * @flag: unique flags -+ * @flags: SOC_xxx - */ - struct soc_data { -- u32 freq_mask[4]; -- u32 flag; --}; -- --#define FREQ_MASK 1 --/* see hardware specification for the allowed frqeuencies */ --static const struct soc_data sdata[] = { -- { /* used by p2041 and p3041 */ -- .freq_mask = {0x8, 0x8, 0x2, 0x2}, -- .flag = FREQ_MASK, -- }, -- { /* used by p5020 */ -- .freq_mask = {0x8, 0x2}, -- .flag = FREQ_MASK, -- }, -- { /* used by p4080, p5040 */ -- .freq_mask = {0}, -- .flag = 0, -- }, -+ u32 flags; - }; - --/* -- * the minimum allowed core frequency, in Hz -- * for chassis v1.0, >= platform frequency -- * for chassis v2.0, >= platform frequency / 2 -- */ --static u32 min_cpufreq; --static const u32 *fmask; -- --#if defined(CONFIG_ARM) --static int get_cpu_physical_id(int cpu) --{ -- return topology_core_id(cpu); --} --#else --static int get_cpu_physical_id(int cpu) --{ -- return get_hard_smp_processor_id(cpu); --} --#endif -- - static u32 get_bus_freq(void) - { - struct device_node *soc; -@@ -99,9 +67,10 @@ static u32 get_bus_freq(void) - return sysfreq; - } - --static struct device_node *cpu_to_clk_node(int cpu) -+static struct clk *cpu_to_clk(int cpu) - { -- struct device_node *np, *clk_np; -+ struct device_node *np; -+ struct clk *clk; - - if (!cpu_present(cpu)) - return NULL; -@@ -110,37 +79,28 @@ static struct device_node *cpu_to_clk_no - if (!np) - return NULL; - -- clk_np = of_parse_phandle(np, "clocks", 0); -- if (!clk_np) -- return NULL; -- -+ clk = of_clk_get(np, 0); - of_node_put(np); -- -- return clk_np; -+ return clk; - } - - /* traverse cpu nodes to get cpu mask of sharing clock wire */ - static void set_affected_cpus(struct cpufreq_policy *policy) - { -- struct device_node *np, *clk_np; - struct cpumask *dstp = policy->cpus; -+ struct clk *clk; - int i; - -- np = cpu_to_clk_node(policy->cpu); -- if (!np) -- return; -- - for_each_present_cpu(i) { -- clk_np = cpu_to_clk_node(i); -- if (!clk_np) -+ clk = cpu_to_clk(i); -+ if (IS_ERR(clk)) { -+ pr_err("%s: no clock for cpu %d\n", __func__, i); - continue; -+ } - -- if (clk_np == np) -+ if (clk_is_match(policy->clk, clk)) - cpumask_set_cpu(i, dstp); -- -- of_node_put(clk_np); - } -- of_node_put(np); - } - - /* reduce the duplicated frequencies in frequency table */ -@@ -198,7 +158,7 @@ static int qoriq_cpufreq_cpu_init(struct - { - struct device_node *np, *pnode; - int i, count, ret; -- u32 freq, mask; -+ u32 freq; - struct clk *clk; - struct cpufreq_frequency_table *table; - struct cpu_data *data; -@@ -219,17 +179,12 @@ static int qoriq_cpufreq_cpu_init(struct - goto err_nomem2; - } - -- pnode = of_parse_phandle(np, "clocks", 0); -- if (!pnode) { -- pr_err("%s: could not get clock information\n", __func__); -- goto err_nomem2; -- } -+ count = clk_get_num_parents(policy->clk); - -- count = of_property_count_strings(pnode, "clock-names"); - data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL); - if (!data->pclk) { - pr_err("%s: no memory\n", __func__); -- goto err_node; -+ goto err_nomem2; - } - - table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL); -@@ -238,23 +193,11 @@ static int qoriq_cpufreq_cpu_init(struct - goto err_pclk; - } - -- if (fmask) -- mask = fmask[get_cpu_physical_id(cpu)]; -- else -- mask = 0x0; -- - for (i = 0; i < count; i++) { -- clk = of_clk_get(pnode, i); -+ clk = clk_get_parent_by_index(policy->clk, i); - data->pclk[i] = clk; - freq = clk_get_rate(clk); -- /* -- * the clock is valid if its frequency is not masked -- * and large than minimum allowed frequency. -- */ -- if (freq < min_cpufreq || (mask & (1 << i))) -- table[i].frequency = CPUFREQ_ENTRY_INVALID; -- else -- table[i].frequency = freq / 1000; -+ table[i].frequency = freq / 1000; - table[i].driver_data = i; - } - freq_table_redup(table, count); -@@ -288,10 +231,7 @@ err_nomem1: - kfree(table); - err_pclk: - kfree(data->pclk); --err_node: -- of_node_put(pnode); - err_nomem2: -- policy->driver_data = NULL; - kfree(data); - err_np: - of_node_put(np); -@@ -332,12 +272,20 @@ static struct cpufreq_driver qoriq_cpufr - .attr = cpufreq_generic_attr, - }; - -+static const struct soc_data blacklist = { -+ .flags = SOC_BLACKLIST, -+}; -+ - static const struct of_device_id node_matches[] __initconst = { -- { .compatible = "fsl,p2041-clockgen", .data = &sdata[0], }, -- { .compatible = "fsl,p3041-clockgen", .data = &sdata[0], }, -- { .compatible = "fsl,p5020-clockgen", .data = &sdata[1], }, -- { .compatible = "fsl,p4080-clockgen", .data = &sdata[2], }, -- { .compatible = "fsl,p5040-clockgen", .data = &sdata[2], }, -+ /* e6500 cannot use cpufreq due to erratum A-008083 */ -+ { .compatible = "fsl,b4420-clockgen", &blacklist }, -+ { .compatible = "fsl,b4860-clockgen", &blacklist }, -+ { .compatible = "fsl,t2080-clockgen", &blacklist }, -+ { .compatible = "fsl,t4240-clockgen", &blacklist }, -+ -+ { .compatible = "fsl,ls1021a-clockgen", }, -+ { .compatible = "fsl,p4080-clockgen", }, -+ { .compatible = "fsl,qoriq-clockgen-1.0", }, - { .compatible = "fsl,qoriq-clockgen-2.0", }, - {} - }; -@@ -355,16 +303,12 @@ static int __init qoriq_cpufreq_init(voi - - match = of_match_node(node_matches, np); - data = match->data; -- if (data) { -- if (data->flag) -- fmask = data->freq_mask; -- min_cpufreq = get_bus_freq(); -- } else { -- min_cpufreq = get_bus_freq() / 2; -- } - - of_node_put(np); - -+ if (data && data->flags & SOC_BLACKLIST) -+ return -ENODEV; -+ - ret = cpufreq_register_driver(&qoriq_cpufreq_driver); - if (!ret) - pr_info("Freescale QorIQ CPU frequency scaling driver\n"); diff --git a/target/linux/layerscape/patches-4.4/8036-ls2085a-Add-support-for-reset.patch b/target/linux/layerscape/patches-4.4/8036-ls2085a-Add-support-for-reset.patch deleted file mode 100644 index 62420191b7..0000000000 --- a/target/linux/layerscape/patches-4.4/8036-ls2085a-Add-support-for-reset.patch +++ /dev/null @@ -1,135 +0,0 @@ -From 4b9227ba510562a51e87487905895aea97e17e77 Mon Sep 17 00:00:00 2001 -From: pankaj chauhan -Date: Tue, 3 Feb 2015 13:08:52 +0530 -Subject: [PATCH 36/70] ls2085a: Add support for reset - -Add support for layerscape reset driver. -Reset is implemented by raising RESET_REQ_B. - -Signed-off-by: pankaj chauhan -Signed-off-by: Stuart Yoder -(cherry picked from commit f248be3aea58ca32b7d77413d742996249b293e9) ---- - drivers/power/reset/Kconfig | 7 ++- - drivers/power/reset/Makefile | 1 + - drivers/power/reset/ls-reboot.c | 93 +++++++++++++++++++++++++++++++++++++++ - 3 files changed, 100 insertions(+), 1 deletion(-) - create mode 100644 drivers/power/reset/ls-reboot.c - ---- a/drivers/power/reset/Kconfig -+++ b/drivers/power/reset/Kconfig -@@ -173,5 +173,10 @@ config POWER_RESET_ZX - help - Reboot support for ZTE SoCs. - --endif -+config POWER_RESET_LAYERSCAPE -+ bool "Freescale LayerScape reset driver" -+ depends on ARCH_FSL_LS2085A -+ help -+ Reboot support for the Freescale LayerScape SoCs. - -+endif ---- a/drivers/power/reset/Makefile -+++ b/drivers/power/reset/Makefile -@@ -20,3 +20,4 @@ obj-$(CONFIG_POWER_RESET_SYSCON) += sysc - obj-$(CONFIG_POWER_RESET_SYSCON_POWEROFF) += syscon-poweroff.o - obj-$(CONFIG_POWER_RESET_RMOBILE) += rmobile-reset.o - obj-$(CONFIG_POWER_RESET_ZX) += zx-reboot.o -+obj-$(CONFIG_POWER_RESET_LAYERSCAPE) += ls-reboot.o ---- /dev/null -+++ b/drivers/power/reset/ls-reboot.c -@@ -0,0 +1,93 @@ -+/* -+ * Freescale LayerScape reboot driver -+ * -+ * Copyright (c) 2015, Freescale Semiconductor. -+ * Author: Pankaj Chauhan -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct ls_reboot_priv { -+ struct device *dev; -+ u32 *rstcr; -+}; -+ -+static struct ls_reboot_priv *ls_reboot_priv; -+ -+static void ls_reboot(enum reboot_mode reboot_mode, const char *cmd) -+{ -+ struct ls_reboot_priv *priv = ls_reboot_priv; -+ u32 val; -+ unsigned long timeout; -+ -+ if (ls_reboot_priv) { -+ val = readl(priv->rstcr); -+ val |= 0x02; -+ writel(val, priv->rstcr); -+ } -+ -+ timeout = jiffies + HZ; -+ while (time_before(jiffies, timeout)) -+ cpu_relax(); -+ -+} -+ -+static int ls_reboot_probe(struct platform_device *pdev) -+{ -+ ls_reboot_priv = devm_kzalloc(&pdev->dev, -+ sizeof(*ls_reboot_priv), GFP_KERNEL); -+ if (!ls_reboot_priv) { -+ dev_err(&pdev->dev, "out of memory for context\n"); -+ return -ENODEV; -+ } -+ -+ ls_reboot_priv->rstcr = of_iomap(pdev->dev.of_node, 0); -+ if (!ls_reboot_priv->rstcr) { -+ devm_kfree(&pdev->dev, ls_reboot_priv); -+ dev_err(&pdev->dev, "can not map resource\n"); -+ return -ENODEV; -+ } -+ -+ ls_reboot_priv->dev = &pdev->dev; -+ -+ arm_pm_restart = ls_reboot; -+ -+ return 0; -+} -+ -+static struct of_device_id ls_reboot_of_match[] = { -+ { .compatible = "fsl,ls-reset" }, -+ {} -+}; -+ -+static struct platform_driver ls_reboot_driver = { -+ .probe = ls_reboot_probe, -+ .driver = { -+ .name = "ls-reset", -+ .of_match_table = ls_reboot_of_match, -+ }, -+}; -+ -+static int __init ls_reboot_init(void) -+{ -+ return platform_driver_register(&ls_reboot_driver); -+} -+device_initcall(ls_reboot_init); diff --git a/target/linux/layerscape/patches-4.4/8037-ls1043a-Add-support-for-reset.patch b/target/linux/layerscape/patches-4.4/8037-ls1043a-Add-support-for-reset.patch deleted file mode 100644 index bd2d90e9bc..0000000000 --- a/target/linux/layerscape/patches-4.4/8037-ls1043a-Add-support-for-reset.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 5d7f8473e3472c16703bf5692d0b13f47d08c70a Mon Sep 17 00:00:00 2001 -From: Shaohui Xie -Date: Fri, 22 Jan 2016 12:01:28 +0800 -Subject: [PATCH 37/70] ls1043a: Add support for reset - -The reset in ls1043a is similar to ls2085a, but accessed in big endian, -so we modify the existing driver to handle endianness, if driver probes -property 'big-endian' in DTS, driver works in big endian mode, -otherwise, driver works in little endian by default. - -Signed-off-by: Shaohui Xie ---- - drivers/power/reset/ls-reboot.c | 18 +++++++++++++++--- - 1 file changed, 15 insertions(+), 3 deletions(-) - ---- a/drivers/power/reset/ls-reboot.c -+++ b/drivers/power/reset/ls-reboot.c -@@ -28,6 +28,7 @@ - struct ls_reboot_priv { - struct device *dev; - u32 *rstcr; -+ bool is_big_endian; - }; - - static struct ls_reboot_priv *ls_reboot_priv; -@@ -39,9 +40,15 @@ static void ls_reboot(enum reboot_mode r - unsigned long timeout; - - if (ls_reboot_priv) { -- val = readl(priv->rstcr); -- val |= 0x02; -- writel(val, priv->rstcr); -+ if (priv->is_big_endian) { -+ val = ioread32be(priv->rstcr); -+ val |= 0x02; -+ iowrite32be(val, priv->rstcr); -+ } else { -+ val = readl(priv->rstcr); -+ val |= 0x02; -+ writel(val, priv->rstcr); -+ } - } - - timeout = jiffies + HZ; -@@ -66,6 +73,11 @@ static int ls_reboot_probe(struct platfo - return -ENODEV; - } - -+ if (of_get_property(pdev->dev.of_node, "big-endian", NULL)) -+ ls_reboot_priv->is_big_endian = true; -+ else -+ ls_reboot_priv->is_big_endian = false; -+ - ls_reboot_priv->dev = &pdev->dev; - - arm_pm_restart = ls_reboot; diff --git a/target/linux/layerscape/patches-4.4/8038-reset-driver-Kconfig-Change-define-to-ARCH_LAYERSCAP.patch b/target/linux/layerscape/patches-4.4/8038-reset-driver-Kconfig-Change-define-to-ARCH_LAYERSCAP.patch deleted file mode 100644 index 793b3700d1..0000000000 --- a/target/linux/layerscape/patches-4.4/8038-reset-driver-Kconfig-Change-define-to-ARCH_LAYERSCAP.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 6569dc5ba472db76aefe65ef552c3f448348fbec Mon Sep 17 00:00:00 2001 -From: Rai Harninder-B01044 -Date: Wed, 28 Oct 2015 13:24:44 +0530 -Subject: [PATCH 38/70] reset driver: Kconfig: Change define to - ARCH_LAYERSCAPE - -Signed-off-by: Rai Harninder-B01044 ---- - drivers/power/reset/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/power/reset/Kconfig -+++ b/drivers/power/reset/Kconfig -@@ -175,7 +175,7 @@ config POWER_RESET_ZX - - config POWER_RESET_LAYERSCAPE - bool "Freescale LayerScape reset driver" -- depends on ARCH_FSL_LS2085A -+ depends on ARCH_LAYERSCAPE - help - Reboot support for the Freescale LayerScape SoCs. - diff --git a/target/linux/layerscape/patches-4.4/8042-drivers-gpio-Port-gpio-driver-to-support-layerscape-.patch b/target/linux/layerscape/patches-4.4/8042-drivers-gpio-Port-gpio-driver-to-support-layerscape-.patch deleted file mode 100644 index c857dbe771..0000000000 --- a/target/linux/layerscape/patches-4.4/8042-drivers-gpio-Port-gpio-driver-to-support-layerscape-.patch +++ /dev/null @@ -1,289 +0,0 @@ -From c2d0a12b5cfa61e43494483f5d1ee466b4998830 Mon Sep 17 00:00:00 2001 -From: Liu Gang -Date: Thu, 14 Jan 2016 19:48:09 +0800 -Subject: [PATCH 42/70] drivers/gpio: Port gpio driver to support layerscape - platform - -Layerscape has the same ip block/controller as -GPIO on powerpc platform(MPC8XXX). - -So use portable i/o accessors, as in_be32/out_be32 -accessors are Power architecture specific whereas -ioread32/iowrite32 and ioread32be/iowrite32be are -available in other architectures. - -Layerscape GPIO controller's registers may be big -or little endian, so the code needs to get the -endian property from DTB, then make additional -functions to fit right register read/write -operations. - -Currently the code can support ls2080a GPIO with -little endian registers. And it can also work well -on other layerscape platform with big endian GPIO -registers. - -Signed-off-by: Liu Gang ---- - drivers/gpio/Kconfig | 7 ++-- - drivers/gpio/gpio-mpc8xxx.c | 87 +++++++++++++++++++++++++++++++------------ - 2 files changed, 68 insertions(+), 26 deletions(-) - ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -282,12 +282,13 @@ config GPIO_MPC5200 - depends on PPC_MPC52xx - - config GPIO_MPC8XXX -- bool "MPC512x/MPC8xxx GPIO support" -+ bool "MPC512x/MPC8xxx/QorIQ GPIO support" - depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \ -- FSL_SOC_BOOKE || PPC_86xx -+ FSL_SOC_BOOKE || PPC_86xx || ARCH_LAYERSCAPE || ARM || \ -+ COMPILE_TEST - help - Say Y here if you're going to use hardware that connects to the -- MPC512x/831x/834x/837x/8572/8610 GPIOs. -+ MPC512x/831x/834x/837x/8572/8610/QorIQ GPIOs. - - config GPIO_MVEBU - def_bool y ---- a/drivers/gpio/gpio-mpc8xxx.c -+++ b/drivers/gpio/gpio-mpc8xxx.c -@@ -1,5 +1,5 @@ - /* -- * GPIOs on MPC512x/8349/8572/8610 and compatible -+ * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible - * - * Copyright (C) 2008 Peter Korsgaard - * -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - #define MPC8XXX_GPIO_PINS 32 - -@@ -44,6 +45,27 @@ struct mpc8xxx_gpio_chip { - const void *of_dev_id_data; - }; - -+static bool gpio_little_endian; -+static inline u32 gpio_in32(void __iomem *addr) -+{ -+ u32 val; -+ -+ if (gpio_little_endian) -+ val = ioread32(addr); -+ else -+ val = ioread32be(addr); -+ -+ return val; -+} -+ -+static inline void gpio_out32(u32 val, void __iomem *addr) -+{ -+ if (gpio_little_endian) -+ iowrite32(val, addr); -+ else -+ iowrite32be(val, addr); -+} -+ - static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) - { - return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); -@@ -59,9 +81,17 @@ static void mpc8xxx_gpio_save_regs(struc - { - struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); - -- mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT); -+ mpc8xxx_gc->data = gpio_in32(mm->regs + GPIO_DAT); - } - -+/* Generic set and clear bits accessor ports */ -+#define bgpio_setbits32(_addr, _v) \ -+ gpio_out32(gpio_in32(_addr) | (_v), (_addr)) -+#define bgpio_clrbits32(_addr, _v) \ -+ gpio_out32(gpio_in32(_addr) & ~(_v), (_addr)) -+#define bgpio_clrsetbits32(addr, clear, set) \ -+ gpio_out32((gpio_in32(addr) & ~(clear)) | (set), (addr)) -+ - /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs - * defined as output cannot be determined by reading GPDAT register, - * so we use shadow data register instead. The status of input pins -@@ -74,9 +104,9 @@ static int mpc8572_gpio_get(struct gpio_ - struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); - u32 out_mask, out_shadow; - -- out_mask = in_be32(mm->regs + GPIO_DIR); -+ out_mask = gpio_in32(mm->regs + GPIO_DIR); - -- val = in_be32(mm->regs + GPIO_DAT) & ~out_mask; -+ val = gpio_in32(mm->regs + GPIO_DAT) & ~out_mask; - out_shadow = mpc8xxx_gc->data & out_mask; - - return (val | out_shadow) & mpc8xxx_gpio2mask(gpio); -@@ -86,7 +116,7 @@ static int mpc8xxx_gpio_get(struct gpio_ - { - struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); - -- return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); -+ return gpio_in32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); - } - - static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) -@@ -102,7 +132,7 @@ static void mpc8xxx_gpio_set(struct gpio - else - mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio); - -- out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); -+ gpio_out32(mpc8xxx_gc->data, mm->regs + GPIO_DAT); - - raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); - } -@@ -128,7 +158,7 @@ static void mpc8xxx_gpio_set_multiple(st - } - } - -- out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); -+ gpio_out32(mpc8xxx_gc->data, mm->regs + GPIO_DAT); - - raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); - } -@@ -141,7 +171,7 @@ static int mpc8xxx_gpio_dir_in(struct gp - - raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - -- clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); -+ bgpio_clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); - - raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); - -@@ -158,7 +188,7 @@ static int mpc8xxx_gpio_dir_out(struct g - - raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - -- setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); -+ bgpio_setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); - - raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); - -@@ -201,7 +231,8 @@ static void mpc8xxx_gpio_irq_cascade(str - struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; - unsigned int mask; - -- mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); -+ mask = gpio_in32(mm->regs + GPIO_IER) -+ & gpio_in32(mm->regs + GPIO_IMR); - if (mask) - generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, - 32 - ffs(mask))); -@@ -217,7 +248,8 @@ static void mpc8xxx_irq_unmask(struct ir - - raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - -- setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); -+ bgpio_setbits32(mm->regs + GPIO_IMR, -+ mpc8xxx_gpio2mask(irqd_to_hwirq(d))); - - raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); - } -@@ -230,7 +262,8 @@ static void mpc8xxx_irq_mask(struct irq_ - - raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - -- clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); -+ bgpio_clrbits32(mm->regs + GPIO_IMR, -+ mpc8xxx_gpio2mask(irqd_to_hwirq(d))); - - raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); - } -@@ -240,7 +273,7 @@ static void mpc8xxx_irq_ack(struct irq_d - struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); - struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; - -- out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); -+ gpio_out32(mpc8xxx_gpio2mask(irqd_to_hwirq(d)), mm->regs + GPIO_IER); - } - - static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) -@@ -252,15 +285,15 @@ static int mpc8xxx_irq_set_type(struct i - switch (flow_type) { - case IRQ_TYPE_EDGE_FALLING: - raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); -- setbits32(mm->regs + GPIO_ICR, -- mpc8xxx_gpio2mask(irqd_to_hwirq(d))); -+ bgpio_setbits32(mm->regs + GPIO_ICR, -+ mpc8xxx_gpio2mask(irqd_to_hwirq(d))); - raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); - break; - - case IRQ_TYPE_EDGE_BOTH: - raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); -- clrbits32(mm->regs + GPIO_ICR, -- mpc8xxx_gpio2mask(irqd_to_hwirq(d))); -+ bgpio_clrbits32(mm->regs + GPIO_ICR, -+ mpc8xxx_gpio2mask(irqd_to_hwirq(d))); - raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); - break; - -@@ -292,20 +325,20 @@ static int mpc512x_irq_set_type(struct i - case IRQ_TYPE_EDGE_FALLING: - case IRQ_TYPE_LEVEL_LOW: - raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); -- clrsetbits_be32(reg, 3 << shift, 2 << shift); -+ bgpio_clrsetbits32(reg, 3 << shift, 2 << shift); - raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); - break; - - case IRQ_TYPE_EDGE_RISING: - case IRQ_TYPE_LEVEL_HIGH: - raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); -- clrsetbits_be32(reg, 3 << shift, 1 << shift); -+ bgpio_clrsetbits32(reg, 3 << shift, 1 << shift); - raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); - break; - - case IRQ_TYPE_EDGE_BOTH: - raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); -- clrbits32(reg, 3 << shift); -+ bgpio_clrbits32(reg, 3 << shift); - raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); - break; - -@@ -398,6 +431,14 @@ static int mpc8xxx_probe(struct platform - mm_gc = &mpc8xxx_gc->mm_gc; - gc = &mm_gc->gc; - -+ if (of_property_read_bool(np, "little-endian")) { -+ gpio_little_endian = true; -+ dev_dbg(&pdev->dev, "GPIO REGISTERS are LITTLE endian\n"); -+ } else { -+ gpio_little_endian = false; -+ dev_dbg(&pdev->dev, "GPIO REGISTERS are BIG endian\n"); -+ } -+ - mm_gc->save_regs = mpc8xxx_gpio_save_regs; - gc->ngpio = MPC8XXX_GPIO_PINS; - gc->direction_input = mpc8xxx_gpio_dir_in; -@@ -422,7 +463,7 @@ static int mpc8xxx_probe(struct platform - return ret; - - mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0); -- if (mpc8xxx_gc->irqn == NO_IRQ) -+ if (mpc8xxx_gc->irqn == 0) - return 0; - - mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, -@@ -435,8 +476,8 @@ static int mpc8xxx_probe(struct platform - mpc8xxx_gc->of_dev_id_data = id->data; - - /* ack and mask all irqs */ -- out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); -- out_be32(mm_gc->regs + GPIO_IMR, 0); -+ gpio_out32(0xffffffff, mm_gc->regs + GPIO_IER); -+ gpio_out32(0, mm_gc->regs + GPIO_IMR); - - irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, - mpc8xxx_gpio_irq_cascade, mpc8xxx_gc); diff --git a/target/linux/layerscape/patches-4.4/8048-mmc-sdhci-of-esdhc-add-remove-some-quirks-according-.patch b/target/linux/layerscape/patches-4.4/8048-mmc-sdhci-of-esdhc-add-remove-some-quirks-according-.patch deleted file mode 100644 index 09afa5e2ac..0000000000 --- a/target/linux/layerscape/patches-4.4/8048-mmc-sdhci-of-esdhc-add-remove-some-quirks-according-.patch +++ /dev/null @@ -1,60 +0,0 @@ -From dfc4661c2499aeb0a43b8a13b55213d1c190f640 Mon Sep 17 00:00:00 2001 -From: yangbo lu -Date: Tue, 19 Apr 2016 09:47:15 +0800 -Subject: [PATCH 48/70] mmc: sdhci-of-esdhc: add/remove some quirks according - to vendor version - -commit 6c42cb309fee2e126beed6b96a986dc7d85a033d -[context adjustment] - -A previous patch had removed esdhc_of_platform_init() by mistake. -static void esdhc_of_platform_init(struct sdhci_host *host) -{ - u32 vvn; - - vvn = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS); - vvn = (vvn & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT; - if (vvn == VENDOR_V_22) - host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; - - if (vvn > VENDOR_V_22) - host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; -} - -This patch is used to fix it by add/remove some quirks according to -verdor version in probe. - -Signed-off-by: Yangbo Lu -Fixes: f4932cfd22f1 ("mmc: sdhci-of-esdhc: support both BE and LE host controller") -Signed-off-by: Ulf Hansson -Integrated-by: Zhao Qiang ---- - drivers/mmc/host/sdhci-of-esdhc.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/mmc/host/sdhci-of-esdhc.c -+++ b/drivers/mmc/host/sdhci-of-esdhc.c -@@ -584,6 +584,8 @@ static int sdhci_esdhc_probe(struct plat - { - struct sdhci_host *host; - struct device_node *np; -+ struct sdhci_pltfm_host *pltfm_host; -+ struct sdhci_esdhc *esdhc; - int ret; - - np = pdev->dev.of_node; -@@ -611,6 +613,14 @@ static int sdhci_esdhc_probe(struct plat - if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) - host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; - -+ pltfm_host = sdhci_priv(host); -+ esdhc = pltfm_host->priv; -+ if (esdhc->vendor_ver == VENDOR_V_22) -+ host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; -+ -+ if (esdhc->vendor_ver > VENDOR_V_22) -+ host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; -+ - if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { - /* - * Freescale messed up with P2020 as it has a non-standard diff --git a/target/linux/layerscape/patches-4.4/8049-PCI-layerscape-Add-fsl-ls2085a-pcie-compatible-ID.patch b/target/linux/layerscape/patches-4.4/8049-PCI-layerscape-Add-fsl-ls2085a-pcie-compatible-ID.patch deleted file mode 100644 index 678da2fc17..0000000000 --- a/target/linux/layerscape/patches-4.4/8049-PCI-layerscape-Add-fsl-ls2085a-pcie-compatible-ID.patch +++ /dev/null @@ -1,25 +0,0 @@ -From f2d357f86d79141969e29ec1dc1669da5120e022 Mon Sep 17 00:00:00 2001 -From: Yang Shi -Date: Wed, 27 Jan 2016 09:32:05 -0800 -Subject: [PATCH 49/70] PCI: layerscape: Add "fsl,ls2085a-pcie" compatible ID - -The Layerscape PCI host driver must recognize ls2085a compatible when using -firmware with ls2085a compatible property, otherwise the PCI bus won't be -detected even though ls2085a compatible is included by the dts. - -Signed-off-by: Yang Shi -Signed-off-by: Bjorn Helgaas ---- - drivers/pci/host/pci-layerscape.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/pci/host/pci-layerscape.c -+++ b/drivers/pci/host/pci-layerscape.c -@@ -203,6 +203,7 @@ static const struct of_device_id ls_pcie - { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, - { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, - { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, -+ { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata }, - { }, - }; - MODULE_DEVICE_TABLE(of, ls_pcie_of_match); diff --git a/target/linux/layerscape/patches-4.4/8050-PCI-layerscape-Fix-MSG-TLP-drop-setting.patch b/target/linux/layerscape/patches-4.4/8050-PCI-layerscape-Fix-MSG-TLP-drop-setting.patch deleted file mode 100644 index 1aa23ab074..0000000000 --- a/target/linux/layerscape/patches-4.4/8050-PCI-layerscape-Fix-MSG-TLP-drop-setting.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 61959c53020fff0584d88e28d6dae9806184f1a8 Mon Sep 17 00:00:00 2001 -From: Minghuan Lian -Date: Mon, 29 Feb 2016 17:24:15 -0600 -Subject: [PATCH 50/70] PCI: layerscape: Fix MSG TLP drop setting - -Some kinds of Layerscape PCIe controllers will forward the received message -TLPs to system application address space, which could corrupt system memory -or lead to a system hang. Enable MSG_DROP to fix this issue. - -Signed-off-by: Minghuan Lian -Signed-off-by: Bjorn Helgaas ---- - drivers/pci/host/pci-layerscape.c | 21 +++++++++++++-------- - 1 file changed, 13 insertions(+), 8 deletions(-) - ---- a/drivers/pci/host/pci-layerscape.c -+++ b/drivers/pci/host/pci-layerscape.c -@@ -77,6 +77,16 @@ static void ls_pcie_fix_class(struct ls_ - iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE); - } - -+/* Drop MSG TLP except for Vendor MSG */ -+static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) -+{ -+ u32 val; -+ -+ val = ioread32(pcie->dbi + PCIE_STRFMR1); -+ val &= 0xDFFFFFFF; -+ iowrite32(val, pcie->dbi + PCIE_STRFMR1); -+} -+ - static int ls1021_pcie_link_up(struct pcie_port *pp) - { - u32 state; -@@ -97,7 +107,7 @@ static int ls1021_pcie_link_up(struct pc - static void ls1021_pcie_host_init(struct pcie_port *pp) - { - struct ls_pcie *pcie = to_ls_pcie(pp); -- u32 val, index[2]; -+ u32 index[2]; - - pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node, - "fsl,pcie-scfg"); -@@ -116,13 +126,7 @@ static void ls1021_pcie_host_init(struct - - dw_pcie_setup_rc(pp); - -- /* -- * LS1021A Workaround for internal TKT228622 -- * to fix the INTx hang issue -- */ -- val = ioread32(pcie->dbi + PCIE_STRFMR1); -- val &= 0xffff; -- iowrite32(val, pcie->dbi + PCIE_STRFMR1); -+ ls_pcie_drop_msg_tlp(pcie); - } - - static int ls_pcie_link_up(struct pcie_port *pp) -@@ -147,6 +151,7 @@ static void ls_pcie_host_init(struct pci - iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN); - ls_pcie_fix_class(pcie); - ls_pcie_clear_multifunction(pcie); -+ ls_pcie_drop_msg_tlp(pcie); - iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN); - } - diff --git a/target/linux/layerscape/patches-4.4/8060-irqchip-Add-Layerscape-SCFG-MSI-controller-support.patch b/target/linux/layerscape/patches-4.4/8060-irqchip-Add-Layerscape-SCFG-MSI-controller-support.patch deleted file mode 100644 index bfbce21bf6..0000000000 --- a/target/linux/layerscape/patches-4.4/8060-irqchip-Add-Layerscape-SCFG-MSI-controller-support.patch +++ /dev/null @@ -1,285 +0,0 @@ -From 83ec4322b33e8d7908a3df0343246882e4e6b83a Mon Sep 17 00:00:00 2001 -From: Minghuan Lian -Date: Wed, 23 Mar 2016 19:08:20 +0800 -Subject: [PATCH 60/70] irqchip: Add Layerscape SCFG MSI controller support - -upstream b8f3ebe630a4f1b4ff9340103d3b565ad5d78d43 commit -[context adjustment] - -Some kind of Freescale Layerscape SoC provides a MSI -implementation which uses two SCFG registers MSIIR and -MSIR to support 32 MSI interrupts for each PCIe controller. -The patch is to support it. - -Signed-off-by: Minghuan Lian -Tested-by: Alexander Stein -Acked-by: Marc Zyngier -Signed-off-by: Marc Zyngier ---- - drivers/irqchip/Kconfig | 5 + - drivers/irqchip/Makefile | 1 + - drivers/irqchip/irq-ls-scfg-msi.c | 240 +++++++++++++++++++++++++++++++++++++ - 3 files changed, 246 insertions(+) - create mode 100644 drivers/irqchip/irq-ls-scfg-msi.c - ---- a/drivers/irqchip/Kconfig -+++ b/drivers/irqchip/Kconfig -@@ -193,3 +193,8 @@ config IRQ_MXS - def_bool y if MACH_ASM9260 || ARCH_MXS - select IRQ_DOMAIN - select STMP_DEVICE -+ -+config LS_SCFG_MSI -+ def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE -+ depends on PCI && PCI_MSI -+ select PCI_MSI_IRQ_DOMAIN ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC) += irq-r - obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o - obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o - obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o -+obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o ---- /dev/null -+++ b/drivers/irqchip/irq-ls-scfg-msi.c -@@ -0,0 +1,240 @@ -+/* -+ * Freescale SCFG MSI(-X) support -+ * -+ * Copyright (C) 2016 Freescale Semiconductor. -+ * -+ * Author: Minghuan Lian -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MSI_MAX_IRQS 32 -+#define MSI_IBS_SHIFT 3 -+#define MSIR 4 -+ -+struct ls_scfg_msi { -+ spinlock_t lock; -+ struct platform_device *pdev; -+ struct irq_domain *parent; -+ struct irq_domain *msi_domain; -+ void __iomem *regs; -+ phys_addr_t msiir_addr; -+ int irq; -+ DECLARE_BITMAP(used, MSI_MAX_IRQS); -+}; -+ -+static struct irq_chip ls_scfg_msi_irq_chip = { -+ .name = "MSI", -+ .irq_mask = pci_msi_mask_irq, -+ .irq_unmask = pci_msi_unmask_irq, -+}; -+ -+static struct msi_domain_info ls_scfg_msi_domain_info = { -+ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | -+ MSI_FLAG_USE_DEF_CHIP_OPS | -+ MSI_FLAG_PCI_MSIX), -+ .chip = &ls_scfg_msi_irq_chip, -+}; -+ -+static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg) -+{ -+ struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data); -+ -+ msg->address_hi = upper_32_bits(msi_data->msiir_addr); -+ msg->address_lo = lower_32_bits(msi_data->msiir_addr); -+ msg->data = data->hwirq << MSI_IBS_SHIFT; -+} -+ -+static int ls_scfg_msi_set_affinity(struct irq_data *irq_data, -+ const struct cpumask *mask, bool force) -+{ -+ return -EINVAL; -+} -+ -+static struct irq_chip ls_scfg_msi_parent_chip = { -+ .name = "SCFG", -+ .irq_compose_msi_msg = ls_scfg_msi_compose_msg, -+ .irq_set_affinity = ls_scfg_msi_set_affinity, -+}; -+ -+static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain, -+ unsigned int virq, -+ unsigned int nr_irqs, -+ void *args) -+{ -+ struct ls_scfg_msi *msi_data = domain->host_data; -+ int pos, err = 0; -+ -+ WARN_ON(nr_irqs != 1); -+ -+ spin_lock(&msi_data->lock); -+ pos = find_first_zero_bit(msi_data->used, MSI_MAX_IRQS); -+ if (pos < MSI_MAX_IRQS) -+ __set_bit(pos, msi_data->used); -+ else -+ err = -ENOSPC; -+ spin_unlock(&msi_data->lock); -+ -+ if (err) -+ return err; -+ -+ irq_domain_set_info(domain, virq, pos, -+ &ls_scfg_msi_parent_chip, msi_data, -+ handle_simple_irq, NULL, NULL); -+ -+ return 0; -+} -+ -+static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain, -+ unsigned int virq, unsigned int nr_irqs) -+{ -+ struct irq_data *d = irq_domain_get_irq_data(domain, virq); -+ struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(d); -+ int pos; -+ -+ pos = d->hwirq; -+ if (pos < 0 || pos >= MSI_MAX_IRQS) { -+ pr_err("failed to teardown msi. Invalid hwirq %d\n", pos); -+ return; -+ } -+ -+ spin_lock(&msi_data->lock); -+ __clear_bit(pos, msi_data->used); -+ spin_unlock(&msi_data->lock); -+} -+ -+static const struct irq_domain_ops ls_scfg_msi_domain_ops = { -+ .alloc = ls_scfg_msi_domain_irq_alloc, -+ .free = ls_scfg_msi_domain_irq_free, -+}; -+ -+static void ls_scfg_msi_irq_handler(struct irq_desc *desc) -+{ -+ struct ls_scfg_msi *msi_data = irq_desc_get_handler_data(desc); -+ unsigned long val; -+ int pos, virq; -+ -+ chained_irq_enter(irq_desc_get_chip(desc), desc); -+ -+ val = ioread32be(msi_data->regs + MSIR); -+ for_each_set_bit(pos, &val, MSI_MAX_IRQS) { -+ virq = irq_find_mapping(msi_data->parent, (31 - pos)); -+ if (virq) -+ generic_handle_irq(virq); -+ } -+ -+ chained_irq_exit(irq_desc_get_chip(desc), desc); -+} -+ -+static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data) -+{ -+ /* Initialize MSI domain parent */ -+ msi_data->parent = irq_domain_add_linear(NULL, -+ MSI_MAX_IRQS, -+ &ls_scfg_msi_domain_ops, -+ msi_data); -+ if (!msi_data->parent) { -+ dev_err(&msi_data->pdev->dev, "failed to create IRQ domain\n"); -+ return -ENOMEM; -+ } -+ -+ msi_data->msi_domain = pci_msi_create_irq_domain( -+ of_node_to_fwnode(msi_data->pdev->dev.of_node), -+ &ls_scfg_msi_domain_info, -+ msi_data->parent); -+ if (!msi_data->msi_domain) { -+ dev_err(&msi_data->pdev->dev, "failed to create MSI domain\n"); -+ irq_domain_remove(msi_data->parent); -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+static int ls_scfg_msi_probe(struct platform_device *pdev) -+{ -+ struct ls_scfg_msi *msi_data; -+ struct resource *res; -+ int ret; -+ -+ msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL); -+ if (!msi_data) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ msi_data->regs = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(msi_data->regs)) { -+ dev_err(&pdev->dev, "failed to initialize 'regs'\n"); -+ return PTR_ERR(msi_data->regs); -+ } -+ msi_data->msiir_addr = res->start; -+ -+ msi_data->irq = platform_get_irq(pdev, 0); -+ if (msi_data->irq <= 0) { -+ dev_err(&pdev->dev, "failed to get MSI irq\n"); -+ return -ENODEV; -+ } -+ -+ msi_data->pdev = pdev; -+ spin_lock_init(&msi_data->lock); -+ -+ ret = ls_scfg_msi_domains_init(msi_data); -+ if (ret) -+ return ret; -+ -+ irq_set_chained_handler_and_data(msi_data->irq, -+ ls_scfg_msi_irq_handler, -+ msi_data); -+ -+ platform_set_drvdata(pdev, msi_data); -+ -+ return 0; -+} -+ -+static int ls_scfg_msi_remove(struct platform_device *pdev) -+{ -+ struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev); -+ -+ irq_set_chained_handler_and_data(msi_data->irq, NULL, NULL); -+ -+ irq_domain_remove(msi_data->msi_domain); -+ irq_domain_remove(msi_data->parent); -+ -+ platform_set_drvdata(pdev, NULL); -+ -+ return 0; -+} -+ -+static const struct of_device_id ls_scfg_msi_id[] = { -+ { .compatible = "fsl,1s1021a-msi", }, -+ { .compatible = "fsl,1s1043a-msi", }, -+ {}, -+}; -+ -+static struct platform_driver ls_scfg_msi_driver = { -+ .driver = { -+ .name = "ls-scfg-msi", -+ .of_match_table = ls_scfg_msi_id, -+ }, -+ .probe = ls_scfg_msi_probe, -+ .remove = ls_scfg_msi_remove, -+}; -+ -+module_platform_driver(ls_scfg_msi_driver); -+ -+MODULE_AUTHOR("Minghuan Lian "); -+MODULE_DESCRIPTION("Freescale Layerscape SCFG MSI controller driver"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/layerscape/patches-4.4/8061-arm64-layerscape-Enable-PCIe-for-Layerscape.patch b/target/linux/layerscape/patches-4.4/8061-arm64-layerscape-Enable-PCIe-for-Layerscape.patch deleted file mode 100644 index 49a07beb5d..0000000000 --- a/target/linux/layerscape/patches-4.4/8061-arm64-layerscape-Enable-PCIe-for-Layerscape.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 99b0e55881b217e9de4efd4d812dd3bd4f8c9380 Mon Sep 17 00:00:00 2001 -From: Mingkai Hu -Date: Thu, 19 Nov 2015 12:49:50 +0800 -Subject: [PATCH 61/70] arm64/layerscape: Enable PCIe for Layerscape - -Signed-off-by: Mingkai Hu -Integrated-by: Jiang Yutang ---- - arch/arm64/Kconfig.platforms | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/Kconfig.platforms -+++ b/arch/arm64/Kconfig.platforms -@@ -31,6 +31,8 @@ config ARCH_EXYNOS7 - - config ARCH_LAYERSCAPE - bool "ARMv8 based Freescale Layerscape SoC family" -+ select PCI_LAYERSCAPE if PCI -+ select LS_SCFG_MSI if PCI_MSI - help - This enables support for the Freescale Layerscape SoC family. - diff --git a/target/linux/layerscape/patches-4.4/8062-armv8-aarch32-enable-pci_domains-for-armv8-32bit.patch b/target/linux/layerscape/patches-4.4/8062-armv8-aarch32-enable-pci_domains-for-armv8-32bit.patch deleted file mode 100644 index 3c80e9c296..0000000000 --- a/target/linux/layerscape/patches-4.4/8062-armv8-aarch32-enable-pci_domains-for-armv8-32bit.patch +++ /dev/null @@ -1,20 +0,0 @@ -From 53ff2bc222c446dfb6ffa9b708a23e7b8b82abb3 Mon Sep 17 00:00:00 2001 -From: Pan Jiafei -Date: Fri, 3 Jun 2016 06:45:57 +0000 -Subject: [PATCH 62/70] armv8: aarch32: enable pci_domains for armv8-32bit - -Signed-off-by: Pan Jiafei ---- - arch/arm/mach-imx/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/mach-imx/Kconfig -+++ b/arch/arm/mach-imx/Kconfig -@@ -617,6 +617,7 @@ config ARCH_LAYERSCAPE - select ARM_GIC - select HAVE_ARM_ARCH_TIMER - select PCI_LAYERSCAPE if PCI -+ select PCI_DOMAINS if PCI - select LS1_MSI if PCI_MSI - - help diff --git a/target/linux/layerscape/patches-4.4/8073-ls1012a-added-clock-configuration.patch b/target/linux/layerscape/patches-4.4/8073-ls1012a-added-clock-configuration.patch deleted file mode 100644 index bee2824da7..0000000000 --- a/target/linux/layerscape/patches-4.4/8073-ls1012a-added-clock-configuration.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 9112596c3c7b7b8b1eded3323765fa711dc58e74 Mon Sep 17 00:00:00 2001 -From: Tang Yuantian -Date: Thu, 25 Aug 2016 10:38:28 +0800 -Subject: [PATCH 073/113] ls1012a: added clock configuration - -commit c9c11181191938b77bfd61e5094a63955cf711fd -[context adjustment] -[don't apply fsl-ls1012a.dtsi] - -Currently ls1012a used the clock configuration of ls1043a's. -But there is a little different between them. This patch added -ls1012a its own clock configuration. - -Signed-off-by: Tang Yuantian -Integrated-by: Zhao Qiang ---- - drivers/clk/clk-qoriq.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/drivers/clk/clk-qoriq.c -+++ b/drivers/clk/clk-qoriq.c -@@ -195,6 +195,14 @@ static const struct clockgen_muxinfo t10 - } - }; - -+static const struct clockgen_muxinfo ls1012a_cmux = { -+ { -+ [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, -+ {}, -+ [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, -+ } -+}; -+ - static const struct clockgen_muxinfo t1040_cmux = { - { - [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, -@@ -475,6 +483,16 @@ static const struct clockgen_chipinfo ch - .pll_mask = 0x03, - }, - { -+ .compat = "fsl,ls1012a-clockgen", -+ .cmux_groups = { -+ &ls1012a_cmux -+ }, -+ .cmux_to_group = { -+ 0, -1 -+ }, -+ .pll_mask = 0x03, -+ }, -+ { - .compat = "fsl,ls1043a-clockgen", - .init_periph = t2080_init_periph, - .cmux_groups = { -@@ -1275,6 +1293,7 @@ CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qo - CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init); - CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); - CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); -+CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init); - - /* Legacy nodes */ - CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init); diff --git a/target/linux/layerscape/patches-4.4/8114-drivers-PCIE-enable-for-Linux.patch b/target/linux/layerscape/patches-4.4/8114-drivers-PCIE-enable-for-Linux.patch deleted file mode 100644 index 61c85a1f3e..0000000000 --- a/target/linux/layerscape/patches-4.4/8114-drivers-PCIE-enable-for-Linux.patch +++ /dev/null @@ -1,49 +0,0 @@ -From cfe7a6abd3d7e9ffeed8230847bbe2f680757305 Mon Sep 17 00:00:00 2001 -From: Pratiyush Mohan Srivastava -Date: Sun, 24 Apr 2016 23:43:19 +0530 -Subject: [PATCH 114/123] drivers: PCIE enable for Linux - -[This patch from sdk release, just context adjustment] -Add support for PCIE for LS1012A in kernel - -Signed-off-by: Pratiyush Mohan Srivastava -Signed-off-by: Prabhakar Kushwaha -Integrated-by: Jiang Yutang ---- - drivers/irqchip/irq-ls-scfg-msi.c | 1 + - drivers/pci/host/pci-layerscape.c | 7 +++++++ - 2 files changed, 8 insertions(+) - ---- a/drivers/irqchip/irq-ls-scfg-msi.c -+++ b/drivers/irqchip/irq-ls-scfg-msi.c -@@ -219,6 +219,7 @@ static int ls_scfg_msi_remove(struct pla - } - - static const struct of_device_id ls_scfg_msi_id[] = { -+ { .compatible = "fsl,ls1012a-msi", }, - { .compatible = "fsl,1s1021a-msi", }, - { .compatible = "fsl,1s1043a-msi", }, - {}, ---- a/drivers/pci/host/pci-layerscape.c -+++ b/drivers/pci/host/pci-layerscape.c -@@ -192,6 +192,12 @@ static struct ls_pcie_drvdata ls1021_drv - .ops = &ls1021_pcie_host_ops, - }; - -+static struct ls_pcie_drvdata ls1012_drvdata = { -+ .lut_offset = 0xC0000, -+ .ltssm_shift = 24, -+ .ops = &ls_pcie_host_ops, -+}; -+ - static struct ls_pcie_drvdata ls1043_drvdata = { - .lut_offset = 0x10000, - .ltssm_shift = 24, -@@ -205,6 +211,7 @@ static struct ls_pcie_drvdata ls2080_drv - }; - - static const struct of_device_id ls_pcie_of_match[] = { -+ { .compatible = "fsl,ls1012a-pcie", .data = &ls1012_drvdata }, - { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, - { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, - { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, diff --git a/target/linux/layerscape/patches-4.4/8115-PCI-layerscape-call-dw_pcie_setup_rc-in-host-initial.patch b/target/linux/layerscape/patches-4.4/8115-PCI-layerscape-call-dw_pcie_setup_rc-in-host-initial.patch deleted file mode 100644 index cf67e59472..0000000000 --- a/target/linux/layerscape/patches-4.4/8115-PCI-layerscape-call-dw_pcie_setup_rc-in-host-initial.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 5d661761fd2354e4f976c83143a1bf7c1ecad766 Mon Sep 17 00:00:00 2001 -From: Yangbo Lu -Date: Tue, 20 Sep 2016 16:07:10 +0800 -Subject: [PATCH 115/115] PCI: layerscape: call dw_pcie_setup_rc() in host - initialization - -A previous patch moved some Root Complex programming from -dw_pcie_host_init() to dw_pcie_setup_rc() where it belongs, -while the pci-layerscape driver didn't call dw_pcie_setup_rc() -anywhere after that. This patch is to add dw_pcie_setup_rc() -calling in layerscape host initialization to fix ls1012a pci -issue caused by that patch. - -Fixes: c49b76f3c613("PCI: designware: Move Root Complex setup - code to dw_pcie_setup_rc()") -Signed-off-by: Yangbo Lu ---- - drivers/pci/host/pci-layerscape.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/pci/host/pci-layerscape.c -+++ b/drivers/pci/host/pci-layerscape.c -@@ -148,6 +148,7 @@ static void ls_pcie_host_init(struct pci - { - struct ls_pcie *pcie = to_ls_pcie(pp); - -+ dw_pcie_setup_rc(pp); - iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN); - ls_pcie_fix_class(pcie); - ls_pcie_clear_multifunction(pcie); diff --git a/target/linux/layerscape/patches-4.4/8125-rtc-pcf2127-add-pcf2129-device-id.patch b/target/linux/layerscape/patches-4.4/8125-rtc-pcf2127-add-pcf2129-device-id.patch deleted file mode 100644 index 6ece59771a..0000000000 --- a/target/linux/layerscape/patches-4.4/8125-rtc-pcf2127-add-pcf2129-device-id.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 228d15f0c525d1d62540539ebb8d311feddb79f5 Mon Sep 17 00:00:00 2001 -From: Akinobu Mita -Date: Mon, 26 Sep 2016 11:26:11 +0800 -Subject: [PATCH 125/141] rtc: pcf2127: add pcf2129 device id - -commit e8bf83a7f9454ed1026f100139ebd10eace0e280 -[context adjustment] - -There are only a few differences between PCF2127 and PCF2129 (PCF2127 -has 512 bytes of general purpose SRAM and count-down timer). - -The rtc-pcf2127 driver currently doesn't use the PCF2127 specific -functionality and Kconfig help text already says this driver supports -PCF2127/29, so we can simply add pcf2129 to device id list. - -Signed-off-by: Akinobu Mita -Signed-off-by: Alexandre Belloni -Signed-off-by: Shaohui Xie -Integrated-by: Zhao Qiang ---- - drivers/rtc/rtc-pcf2127.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - ---- a/drivers/rtc/rtc-pcf2127.c -+++ b/drivers/rtc/rtc-pcf2127.c -@@ -1,12 +1,12 @@ - /* -- * An I2C driver for the NXP PCF2127 RTC -+ * An I2C and SPI driver for the NXP PCF2127/29 RTC - * Copyright 2013 Til-Technologies - * - * Author: Renaud Cerrato - * - * based on the other drivers in this same directory. - * -- * http://www.nxp.com/documents/data_sheet/PCF2127AT.pdf -+ * Datasheet: http://cache.nxp.com/documents/data_sheet/PCF2127.pdf - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as -@@ -216,6 +216,7 @@ static int pcf2127_probe(struct i2c_clie - - static const struct i2c_device_id pcf2127_id[] = { - { "pcf2127", 0 }, -+ { "pcf2129", 0 }, - { } - }; - MODULE_DEVICE_TABLE(i2c, pcf2127_id); -@@ -223,6 +224,7 @@ MODULE_DEVICE_TABLE(i2c, pcf2127_id); - #ifdef CONFIG_OF - static const struct of_device_id pcf2127_of_match[] = { - { .compatible = "nxp,pcf2127" }, -+ { .compatible = "nxp,pcf2129" }, - {} - }; - MODULE_DEVICE_TABLE(of, pcf2127_of_match); -@@ -240,5 +242,5 @@ static struct i2c_driver pcf2127_driver - module_i2c_driver(pcf2127_driver); - - MODULE_AUTHOR("Renaud Cerrato "); --MODULE_DESCRIPTION("NXP PCF2127 RTC driver"); -+MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver"); - MODULE_LICENSE("GPL v2"); diff --git a/target/linux/layerscape/patches-4.4/8127-ls1046a-msi-Add-LS1046A-MSI-support.patch b/target/linux/layerscape/patches-4.4/8127-ls1046a-msi-Add-LS1046A-MSI-support.patch deleted file mode 100644 index a3850c706f..0000000000 --- a/target/linux/layerscape/patches-4.4/8127-ls1046a-msi-Add-LS1046A-MSI-support.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 51ab89c787184d47dbff37c3c69ea2c82cc4749c Mon Sep 17 00:00:00 2001 -From: Mingkai Hu -Date: Mon, 26 Sep 2016 12:13:56 +0800 -Subject: [PATCH 127/141] ls1046a/msi: Add LS1046A MSI support - -commit 2b5a00d46a8f8762b9f78b727eab6fc0e12f3fd7 -[context adjustment] - -Signed-off-by: Mingkai Hu -Integated-by: Zhao Qiang -Integated-by: Yutang Jiang ---- - drivers/irqchip/irq-ls-scfg-msi.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/irqchip/irq-ls-scfg-msi.c -+++ b/drivers/irqchip/irq-ls-scfg-msi.c -@@ -222,6 +222,7 @@ static const struct of_device_id ls_scfg - { .compatible = "fsl,ls1012a-msi", }, - { .compatible = "fsl,1s1021a-msi", }, - { .compatible = "fsl,1s1043a-msi", }, -+ { .compatible = "fsl,ls1046a-msi", }, - {}, - }; - diff --git a/target/linux/layerscape/patches-4.4/8128-pci-layerscape-add-LS1046A-support.patch b/target/linux/layerscape/patches-4.4/8128-pci-layerscape-add-LS1046A-support.patch deleted file mode 100644 index 0a9f296553..0000000000 --- a/target/linux/layerscape/patches-4.4/8128-pci-layerscape-add-LS1046A-support.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 5a95e58e58da417ca8a8f4ae11347ad9a66803cd Mon Sep 17 00:00:00 2001 -From: Mingkai Hu -Date: Mon, 26 Sep 2016 12:17:36 +0800 -Subject: [PATCH 128/141] pci/layerscape: add LS1046A support - -commit a52797fe443a79c53d0b63c505c99f65264de8b7 -[context adjustment] - -Signed-off-by: Mingkai Hu -Integrated-by: Zhao Qiang -Integrated-by: Yutang Jiang ---- - drivers/pci/host/pci-layerscape.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/pci/host/pci-layerscape.c -+++ b/drivers/pci/host/pci-layerscape.c -@@ -205,6 +205,12 @@ static struct ls_pcie_drvdata ls1043_drv - .ops = &ls_pcie_host_ops, - }; - -+static struct ls_pcie_drvdata ls1046_drvdata = { -+ .lut_offset = 0x10000, -+ .ltssm_shift = 24, -+ .ops = &ls_pcie_host_ops, -+}; -+ - static struct ls_pcie_drvdata ls2080_drvdata = { - .lut_offset = 0x80000, - .ltssm_shift = 0, -@@ -215,6 +221,7 @@ static const struct of_device_id ls_pcie - { .compatible = "fsl,ls1012a-pcie", .data = &ls1012_drvdata }, - { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, - { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, -+ { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata }, - { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, - { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata }, - { }, diff --git a/target/linux/layerscape/patches-4.4/8129-clk-qoriq-add-ls1046a-support.patch b/target/linux/layerscape/patches-4.4/8129-clk-qoriq-add-ls1046a-support.patch deleted file mode 100644 index ed2f565c31..0000000000 --- a/target/linux/layerscape/patches-4.4/8129-clk-qoriq-add-ls1046a-support.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 4fe33d4f4dc608fc5013390db58df06723282d01 Mon Sep 17 00:00:00 2001 -From: Mingkai Hu -Date: Thu, 2 Jun 2016 11:15:58 +0800 -Subject: [PATCH 129/141] clk: qoriq: add ls1046a support - -Signed-off-by: Mingkai Hu -Integated-by: Yutang Jiang ---- - drivers/clk/clk-qoriq.c | 41 +++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 41 insertions(+) - ---- a/drivers/clk/clk-qoriq.c -+++ b/drivers/clk/clk-qoriq.c -@@ -275,6 +275,31 @@ static const struct clockgen_muxinfo ls1 - }, - }; - -+static const struct clockgen_muxinfo ls1046a_hwa1 = { -+ { -+ {}, -+ {}, -+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, -+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, -+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, -+ { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, -+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, -+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, -+ }, -+}; -+ -+static const struct clockgen_muxinfo ls1046a_hwa2 = { -+ { -+ {}, -+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, -+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, -+ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, -+ {}, -+ {}, -+ { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, -+ }, -+}; -+ - static const struct clockgen_muxinfo t1023_hwa1 = { - { - {}, -@@ -508,6 +533,21 @@ static const struct clockgen_chipinfo ch - .flags = CG_PLL_8BIT, - }, - { -+ .compat = "fsl,ls1046a-clockgen", -+ .init_periph = t2080_init_periph, -+ .cmux_groups = { -+ &t1040_cmux -+ }, -+ .hwaccel = { -+ &ls1046a_hwa1, &ls1046a_hwa2 -+ }, -+ .cmux_to_group = { -+ 0, -1 -+ }, -+ .pll_mask = 0x07, -+ .flags = CG_PLL_8BIT, -+ }, -+ { - .compat = "fsl,ls2080a-clockgen", - .cmux_groups = { - &clockgen2_cmux_cga12, &clockgen2_cmux_cgb -@@ -1292,6 +1332,7 @@ CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qo - CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); - CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init); - CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); -+CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init); - CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); - CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init); - diff --git a/target/linux/layerscape/patches-4.4/8130-ls1046a-sata-Add-LS1046A-sata-support.patch b/target/linux/layerscape/patches-4.4/8130-ls1046a-sata-Add-LS1046A-sata-support.patch deleted file mode 100644 index ea384e6bd9..0000000000 --- a/target/linux/layerscape/patches-4.4/8130-ls1046a-sata-Add-LS1046A-sata-support.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 5cd461cd17c3e27e5501e499d5d865b60ee58257 Mon Sep 17 00:00:00 2001 -From: Gong Qianyu -Date: Mon, 26 Sep 2016 12:29:24 +0800 -Subject: [PATCH 130/141] ls1046a/sata: Add LS1046A sata support - -Signed-off-by: Gong Qianyu -Integrated-by: Zhao Qiang -Integated-by: Yutang Jiang ---- - drivers/ata/ahci_qoriq.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/ata/ahci_qoriq.c -+++ b/drivers/ata/ahci_qoriq.c -@@ -40,11 +40,16 @@ - #define AHCI_PORT_PHY_5_CFG 0x192c96a4 - #define AHCI_PORT_TRANS_CFG 0x08000025 - -+/* for ls1046a */ -+#define LS1046A_PORT_PHY2 0x28184d1f -+#define LS1046A_PORT_PHY3 0x0e081509 -+ - #define SATA_ECC_DISABLE 0x00020000 - - enum ahci_qoriq_type { - AHCI_LS1021A, - AHCI_LS1043A, -+ AHCI_LS1046A, - AHCI_LS2080A, - }; - -@@ -57,6 +62,7 @@ struct ahci_qoriq_priv { - static const struct of_device_id ahci_qoriq_of_match[] = { - { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A}, - { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A}, -+ { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A}, - { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A}, - {}, - }; -@@ -158,6 +164,13 @@ static int ahci_qoriq_phy_init(struct ah - writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); - break; - -+ case AHCI_LS1046A: -+ writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); -+ writel(LS1046A_PORT_PHY2, reg_base + PORT_PHY2); -+ writel(LS1046A_PORT_PHY3, reg_base + PORT_PHY3); -+ writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); -+ break; -+ - case AHCI_LS1043A: - case AHCI_LS2080A: - writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); diff --git a/target/linux/layerscape/patches-4.4/8134-pci-layerscape-add-LUT-DBG-reigster-offset-member.patch b/target/linux/layerscape/patches-4.4/8134-pci-layerscape-add-LUT-DBG-reigster-offset-member.patch deleted file mode 100644 index c3256e9839..0000000000 --- a/target/linux/layerscape/patches-4.4/8134-pci-layerscape-add-LUT-DBG-reigster-offset-member.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 57d147c02fdcbae5e61ba322d51c5734f9511fd7 Mon Sep 17 00:00:00 2001 -From: Mingkai Hu -Date: Mon, 26 Sep 2016 14:19:32 +0800 -Subject: [PATCH 134/141] pci/layerscape: add LUT DBG reigster offset member - -commit 59ab37d6f46356a5b9755fcec74b23616dfdd62f -[doesn't apply pm part] - -Different chip have different LUT debug register offset, -so add a member to avoid macro redifinition. - -Signed-off-by: Mingkai Hu -Integrated-by: Zhao Qiang -Integrated-by: Yutang Jiang ---- - drivers/pci/host/pci-layerscape.c | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - ---- a/drivers/pci/host/pci-layerscape.c -+++ b/drivers/pci/host/pci-layerscape.c -@@ -41,6 +41,7 @@ - struct ls_pcie_drvdata { - u32 lut_offset; - u32 ltssm_shift; -+ u32 lut_dbg; - struct pcie_host_ops *ops; - }; - -@@ -134,7 +135,7 @@ static int ls_pcie_link_up(struct pcie_p - struct ls_pcie *pcie = to_ls_pcie(pp); - u32 state; - -- state = (ioread32(pcie->lut + PCIE_LUT_DBG) >> -+ state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> - pcie->drvdata->ltssm_shift) & - LTSSM_STATE_MASK; - -@@ -196,24 +197,28 @@ static struct ls_pcie_drvdata ls1021_drv - static struct ls_pcie_drvdata ls1012_drvdata = { - .lut_offset = 0xC0000, - .ltssm_shift = 24, -+ .lut_dbg = 0x7fc, - .ops = &ls_pcie_host_ops, - }; - - static struct ls_pcie_drvdata ls1043_drvdata = { - .lut_offset = 0x10000, - .ltssm_shift = 24, -+ .lut_dbg = 0x7fc, - .ops = &ls_pcie_host_ops, - }; - - static struct ls_pcie_drvdata ls1046_drvdata = { -- .lut_offset = 0x10000, -+ .lut_offset = 0x80000, - .ltssm_shift = 24, -+ .lut_dbg = 0x407fc, - .ops = &ls_pcie_host_ops, - }; - - static struct ls_pcie_drvdata ls2080_drvdata = { - .lut_offset = 0x80000, - .ltssm_shift = 0, -+ .lut_dbg = 0x7fc, - .ops = &ls_pcie_host_ops, - }; - diff --git a/target/linux/layerscape/patches-4.4/8136-drivers-mmc-Add-compatible-string-for-LS1088A.patch b/target/linux/layerscape/patches-4.4/8136-drivers-mmc-Add-compatible-string-for-LS1088A.patch deleted file mode 100644 index cf0cecf786..0000000000 --- a/target/linux/layerscape/patches-4.4/8136-drivers-mmc-Add-compatible-string-for-LS1088A.patch +++ /dev/null @@ -1,24 +0,0 @@ -From f6f7c6ecdecfb75412a17205d9ac4905f6bc2851 Mon Sep 17 00:00:00 2001 -From: Rai Harninder -Date: Thu, 18 Feb 2016 16:35:35 +0530 -Subject: [PATCH 136/141] drivers/mmc: Add compatible string for LS1088A - -Signed-off-by: Rai Harninder -Signed-off-by: Pratiyush Mohan Srivastava -Signed-off-by: Raghav Dogra ---- - drivers/mmc/host/sdhci-pltfm.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/mmc/host/sdhci-pltfm.c -+++ b/drivers/mmc/host/sdhci-pltfm.c -@@ -93,6 +93,9 @@ void sdhci_get_of_property(struct platfo - if (of_device_is_compatible(np, "fsl,p2020-rev1-esdhc")) - host->quirks |= SDHCI_QUIRK_BROKEN_DMA; - -+ if (of_device_is_compatible(np, "fsl,ls1088a-esdhc")) -+ host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; -+ - if (of_device_is_compatible(np, "fsl,p2020-esdhc") || - of_device_is_compatible(np, "fsl,p1010-esdhc") || - of_device_is_compatible(np, "fsl,t4240-esdhc") || diff --git a/target/linux/layerscape/patches-4.4/8137-armv8-ls1088a-Add-PCIe-compatible.patch b/target/linux/layerscape/patches-4.4/8137-armv8-ls1088a-Add-PCIe-compatible.patch deleted file mode 100644 index d6137a8af6..0000000000 --- a/target/linux/layerscape/patches-4.4/8137-armv8-ls1088a-Add-PCIe-compatible.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 1aeb63c52ade1219032161fcdb923aa4c62b3796 Mon Sep 17 00:00:00 2001 -From: Prabhakar Kushwaha -Date: Sun, 9 Oct 2016 14:52:49 +0800 -Subject: [PATCH 137/141] armv8: ls1088a: Add PCIe compatible - -commit: 1a089a382b187c80390f022d1e3f3749b2adcc64 -[don't apply dtsi] - -Signed-off-by: Prabhakar Kushwaha -Integrated-by: Zhao Qiang ---- - drivers/pci/host/pci-layerscape.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/pci/host/pci-layerscape.c -+++ b/drivers/pci/host/pci-layerscape.c -@@ -215,6 +215,13 @@ static struct ls_pcie_drvdata ls1046_drv - .ops = &ls_pcie_host_ops, - }; - -+static struct ls_pcie_drvdata ls1088_drvdata = { -+ .lut_offset = 0x80000, -+ .ltssm_shift = 0, -+ .lut_dbg = 0x407fc, -+ .ops = &ls_pcie_host_ops, -+}; -+ - static struct ls_pcie_drvdata ls2080_drvdata = { - .lut_offset = 0x80000, - .ltssm_shift = 0, -@@ -227,6 +234,7 @@ static const struct of_device_id ls_pcie - { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, - { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, - { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata }, -+ { .compatible = "fsl,ls1088a-pcie", .data = &ls1088_drvdata }, - { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, - { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata }, - { }, diff --git a/target/linux/layerscape/patches-4.4/8138-pci-layerscape-add-MSI-interrupt-support.patch b/target/linux/layerscape/patches-4.4/8138-pci-layerscape-add-MSI-interrupt-support.patch deleted file mode 100644 index cbfa86c1e2..0000000000 --- a/target/linux/layerscape/patches-4.4/8138-pci-layerscape-add-MSI-interrupt-support.patch +++ /dev/null @@ -1,259 +0,0 @@ -From b0e74277164b17bb0d207ffe16056e13e558f6ba Mon Sep 17 00:00:00 2001 -From: Zhao Qiang -Date: Tue, 11 Oct 2016 16:25:07 +0800 -Subject: [PATCH 138/141] pci-layerscape: add MSI interrupt support - -Signed-off-by: Zhao Qiang ---- - drivers/iommu/amd_iommu.c | 5 +++-- - drivers/iommu/arm-smmu.c | 21 ++++++++++++++++++ - drivers/iommu/iommu.c | 8 +++---- - drivers/pci/host/pci-layerscape.c | 43 +++++++++++++++++++++++++++++++++++++ - drivers/pci/host/pci-layerscape.h | 17 +++++++++++++++ - drivers/pci/quirks.c | 19 +++++++++------- - drivers/pci/search.c | 5 ++--- - include/linux/pci.h | 6 +++--- - 8 files changed, 104 insertions(+), 20 deletions(-) - create mode 100644 drivers/pci/host/pci-layerscape.h - ---- a/drivers/iommu/amd_iommu.c -+++ b/drivers/iommu/amd_iommu.c -@@ -222,8 +222,9 @@ static u16 get_alias(struct device *dev) - */ - if (pci_alias == devid && - PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { -- pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; -- pdev->dma_alias_devfn = ivrs_alias & 0xff; -+ pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID; -+ pdev->dma_alias_devid = PCI_DEVID(pdev->bus->number, -+ ivrs_alias & 0xff); - pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", - PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), - dev_name(dev)); ---- a/drivers/iommu/arm-smmu.c -+++ b/drivers/iommu/arm-smmu.c -@@ -45,6 +45,10 @@ - - #include - -+#ifdef CONFIG_PCI_LAYERSCAPE -+#include <../drivers/pci/host/pci-layerscape.h> -+#endif -+ - #include "io-pgtable.h" - - /* Maximum number of stream IDs assigned to a single device */ -@@ -1352,6 +1356,23 @@ static int arm_smmu_init_platform_device - static int arm_smmu_add_device(struct device *dev) - { - struct iommu_group *group; -+#ifdef CONFIG_PCI_LAYERSCAPE -+ u16 sid; -+ u32 streamid; -+ struct pci_dev *pdev; -+ if (dev_is_pci(dev)) { -+ pdev = to_pci_dev(dev); -+ -+ pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid); -+ streamid = set_pcie_streamid_translation(pdev, sid); -+ if (~streamid == 0) { -+ return -ENODEV; -+ } -+ -+ pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID; -+ pdev->dma_alias_devid = streamid; -+ } -+#endif - - group = iommu_group_get_for_dev(dev); - if (IS_ERR(group)) ---- a/drivers/iommu/iommu.c -+++ b/drivers/iommu/iommu.c -@@ -697,10 +697,10 @@ static struct iommu_group *get_pci_alias - continue; - - /* We alias them or they alias us */ -- if (((pdev->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVFN) && -- pdev->dma_alias_devfn == tmp->devfn) || -- ((tmp->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVFN) && -- tmp->dma_alias_devfn == pdev->devfn)) { -+ if (((pdev->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVID) && -+ (pdev->dma_alias_devid & 0xff) == tmp->devfn) || -+ ((tmp->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVID) && -+ (tmp->dma_alias_devid & 0xff) == pdev->devfn)) { - - group = get_pci_alias_group(tmp, devfns); - if (group) { ---- a/drivers/pci/host/pci-layerscape.c -+++ b/drivers/pci/host/pci-layerscape.c -@@ -37,6 +37,11 @@ - - /* PEX LUT registers */ - #define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */ -+#define PCIE_LUT_UDR(n) (0x800 + (n) * 8) -+#define PCIE_LUT_LDR(n) (0x804 + (n) * 8) -+#define PCIE_LUT_MASK_ALL 0xffff -+#define PCIE_LUT_DR_NUM 32 -+#define PCIE_LUT_ENABLE (1 << 31) - - struct ls_pcie_drvdata { - u32 lut_offset; -@@ -52,10 +57,30 @@ struct ls_pcie { - struct pcie_port pp; - const struct ls_pcie_drvdata *drvdata; - int index; -+ const u32 *avail_streamids; -+ int streamid_index; - }; - - #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp) - -+u32 set_pcie_streamid_translation(struct pci_dev *pdev, u32 devid) -+{ -+ u32 index, streamid; -+ struct pcie_port *pp = pdev->bus->sysdata; -+ struct ls_pcie *pcie = to_ls_pcie(pp); -+ -+ if (!pcie->avail_streamids || !pcie->streamid_index) -+ return ~(u32)0; -+ -+ index = --pcie->streamid_index; -+ /* mask is set as all zeroes, want to match all bits */ -+ iowrite32((devid << 16), pcie->lut + PCIE_LUT_UDR(index)); -+ streamid = be32_to_cpup(&pcie->avail_streamids[index]); -+ iowrite32(streamid | PCIE_LUT_ENABLE, pcie->lut + PCIE_LUT_LDR(index)); -+ -+ return streamid; -+} -+ - static bool ls_pcie_is_bridge(struct ls_pcie *pcie) - { - u32 header_type; -@@ -284,10 +309,28 @@ static int __init ls_pcie_probe(struct p - - pcie->drvdata = match->data; - pcie->lut = pcie->dbi + pcie->drvdata->lut_offset; -+ /* Disable LDR zero */ -+ iowrite32(0, pcie->lut + PCIE_LUT_LDR(0)); - - if (!ls_pcie_is_bridge(pcie)) - return -ENODEV; - -+ if (of_device_is_compatible(pdev->dev.of_node, "fsl,ls2085a-pcie") || -+ of_device_is_compatible(pdev->dev.of_node, "fsl,ls2080a-pcie") || -+ of_device_is_compatible(pdev->dev.of_node, "fsl,ls1088a-pcie")) { -+ int len; -+ const u32 *prop; -+ struct device_node *np; -+ -+ np = pdev->dev.of_node; -+ prop = (u32 *)of_get_property(np, "available-stream-ids", &len); -+ if (prop) { -+ pcie->avail_streamids = prop; -+ pcie->streamid_index = len/sizeof(u32); -+ } else -+ dev_err(&pdev->dev, "PCIe endpoint partitioning not possible\n"); -+ } -+ - ret = ls_add_pcie_port(&pcie->pp, pdev); - if (ret < 0) - return ret; ---- /dev/null -+++ b/drivers/pci/host/pci-layerscape.h -@@ -0,0 +1,17 @@ -+/* -+ * Copyright (C) 2015 Freescale Semiconductor. -+ * -+ * Author: Varun Sethi -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#ifndef _PCI_LAYERSCAPE_H -+#define _PCI_LAYERSCAPE_H -+ -+/* function for setting up stream id to device id translation */ -+u32 set_pcie_streamid_translation(struct pci_dev *pdev, u32 devid); -+ -+#endif /* _PCI_LAYERSCAPE_H */ ---- a/drivers/pci/quirks.c -+++ b/drivers/pci/quirks.c -@@ -3589,8 +3589,9 @@ int pci_dev_specific_reset(struct pci_de - static void quirk_dma_func0_alias(struct pci_dev *dev) - { - if (PCI_FUNC(dev->devfn) != 0) { -- dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0); -- dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; -+ dev->dma_alias_devid = PCI_DEVID(dev->bus->number, -+ PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); -+ dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID; - } - } - -@@ -3605,8 +3606,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_R - static void quirk_dma_func1_alias(struct pci_dev *dev) - { - if (PCI_FUNC(dev->devfn) != 1) { -- dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1); -- dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; -+ dev->dma_alias_devid = PCI_DEVID(dev->bus->number, -+ PCI_DEVFN(PCI_SLOT(dev->devfn), 1)); -+ dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID; - } - } - -@@ -3670,11 +3672,12 @@ static void quirk_fixed_dma_alias(struct - - id = pci_match_id(fixed_dma_alias_tbl, dev); - if (id) { -- dev->dma_alias_devfn = id->driver_data; -- dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; -+ dev->dma_alias_devid = PCI_DEVID(dev->bus->number, -+ id->driver_data); -+ dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID; - dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n", -- PCI_SLOT(dev->dma_alias_devfn), -- PCI_FUNC(dev->dma_alias_devfn)); -+ PCI_SLOT(dev->dma_alias_devid), -+ PCI_FUNC(dev->dma_alias_devid)); - } - } - ---- a/drivers/pci/search.c -+++ b/drivers/pci/search.c -@@ -40,9 +40,8 @@ int pci_for_each_dma_alias(struct pci_de - * If the device is broken and uses an alias requester ID for - * DMA, iterate over that too. - */ -- if (unlikely(pdev->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVFN)) { -- ret = fn(pdev, PCI_DEVID(pdev->bus->number, -- pdev->dma_alias_devfn), data); -+ if (unlikely(pdev->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVID)) { -+ ret = fn(pdev, pdev->dma_alias_devid, data); - if (ret) - return ret; - } ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -172,8 +172,8 @@ enum pci_dev_flags { - PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), - /* Flag for quirk use to store if quirk-specific ACS is enabled */ - PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), -- /* Flag to indicate the device uses dma_alias_devfn */ -- PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4), -+ /* Flag to indicate the device uses dma_alias_devid */ -+ PCI_DEV_FLAGS_DMA_ALIAS_DEVID = (__force pci_dev_flags_t) (1 << 4), - /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ - PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), - /* Do not use bus resets for device */ -@@ -279,7 +279,7 @@ struct pci_dev { - u8 rom_base_reg; /* which config register controls the ROM */ - u8 pin; /* which interrupt pin this device uses */ - u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ -- u8 dma_alias_devfn;/* devfn of DMA alias, if any */ -+ u32 dma_alias_devid;/* devid of DMA alias */ - - struct pci_driver *driver; /* which driver has allocated this device */ - u64 dma_mask; /* Mask of the bits of bus address this diff --git a/target/linux/layerscape/patches-4.4/8142-drivers-mmc-Add-compatible-string-for-LS1046A.patch b/target/linux/layerscape/patches-4.4/8142-drivers-mmc-Add-compatible-string-for-LS1046A.patch deleted file mode 100644 index 34add83db4..0000000000 --- a/target/linux/layerscape/patches-4.4/8142-drivers-mmc-Add-compatible-string-for-LS1046A.patch +++ /dev/null @@ -1,20 +0,0 @@ -From 81c67bb120106c4fbd9b7191ab057b48e13e3e5e Mon Sep 17 00:00:00 2001 -From: Yutang Jiang -Date: Tue, 8 Nov 2016 01:27:50 +0800 -Subject: [PATCH 142/142] drivers/mmc: Add compatible string for LS1046A - -Signed-off-by: Yutang Jiang ---- - drivers/mmc/host/sdhci-of-esdhc.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/mmc/host/sdhci-of-esdhc.c -+++ b/drivers/mmc/host/sdhci-of-esdhc.c -@@ -607,6 +607,7 @@ static int sdhci_esdhc_probe(struct plat - of_device_is_compatible(np, "fsl,p4080-esdhc") || - of_device_is_compatible(np, "fsl,p1020-esdhc") || - of_device_is_compatible(np, "fsl,t1040-esdhc") || -+ of_device_is_compatible(np, "fsl,ls1046a-esdhc") || - of_device_is_compatible(np, "fsl,ls1021a-esdhc")) - host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; - diff --git a/target/linux/layerscape/patches-4.4/8229-drivers-clk-qoriq-Add-ls2088a-key-to-chipinfo-table.patch b/target/linux/layerscape/patches-4.4/8229-drivers-clk-qoriq-Add-ls2088a-key-to-chipinfo-table.patch deleted file mode 100644 index efc6467b09..0000000000 --- a/target/linux/layerscape/patches-4.4/8229-drivers-clk-qoriq-Add-ls2088a-key-to-chipinfo-table.patch +++ /dev/null @@ -1,30 +0,0 @@ -From cb8a47d43caa2b07a62d81ee0b65c0d16560c276 Mon Sep 17 00:00:00 2001 -From: Abhimanyu Saini -Date: Fri, 3 Jun 2016 13:15:28 +0530 -Subject: [PATCH 229/238] drivers: clk: qoriq: Add ls2088a key to chipinfo - table - ---- - drivers/clk/clk-qoriq.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/drivers/clk/clk-qoriq.c -+++ b/drivers/clk/clk-qoriq.c -@@ -559,6 +559,17 @@ static const struct clockgen_chipinfo ch - .flags = CG_VER3 | CG_LITTLE_ENDIAN, - }, - { -+ .compat = "fsl,ls2088a-clockgen", -+ .cmux_groups = { -+ &clockgen2_cmux_cga12, &clockgen2_cmux_cgb -+ }, -+ .cmux_to_group = { -+ 0, 0, 1, 1, -1 -+ }, -+ .pll_mask = 0x37, -+ .flags = CG_VER3 | CG_LITTLE_ENDIAN, -+ }, -+ { - .compat = "fsl,p2041-clockgen", - .guts_compat = "fsl,qoriq-device-config-1.0", - .init_periph = p2041_init_periph, diff --git a/target/linux/layerscape/patches-4.4/8230-layerscape-pci-fix-linkup-issue.patch b/target/linux/layerscape/patches-4.4/8230-layerscape-pci-fix-linkup-issue.patch deleted file mode 100644 index f28776cba1..0000000000 --- a/target/linux/layerscape/patches-4.4/8230-layerscape-pci-fix-linkup-issue.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 1b23a4e0f03063f823ea38065c1106f62a56b408 Mon Sep 17 00:00:00 2001 -From: Mingkai Hu -Date: Mon, 7 Nov 2016 15:03:51 +0800 -Subject: [PATCH 230/238] layerscape/pci: fix linkup issue - -commit e6612d785198abbb39142e2acb63f9bff26ab718 -[context adjustment] - -Signed-off-by: Mingkai Hu -Integrated-by: Zhao Qiang ---- - drivers/pci/host/pci-layerscape.c | 13 +++++++++---- - 1 file changed, 9 insertions(+), 4 deletions(-) - ---- a/drivers/pci/host/pci-layerscape.c -+++ b/drivers/pci/host/pci-layerscape.c -@@ -158,11 +158,16 @@ static void ls1021_pcie_host_init(struct - static int ls_pcie_link_up(struct pcie_port *pp) - { - struct ls_pcie *pcie = to_ls_pcie(pp); -- u32 state; -+ u32 state, offset; - -- state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> -- pcie->drvdata->ltssm_shift) & -- LTSSM_STATE_MASK; -+ if (of_get_property(pp->dev->of_node, "fsl,lut_diff", NULL)) -+ offset = 0x407fc; -+ else -+ offset = PCIE_LUT_DBG; -+ -+ state = (ioread32(pcie->lut + offset) >> -+ pcie->drvdata->ltssm_shift) & -+ LTSSM_STATE_MASK; - - if (state < LTSSM_PCIE_L0) - return 0; diff --git a/target/linux/layerscape/patches-4.4/8231-driver-clk-qoriq-Add-ls2088a-clk-support.patch b/target/linux/layerscape/patches-4.4/8231-driver-clk-qoriq-Add-ls2088a-clk-support.patch deleted file mode 100644 index 6c95cd0250..0000000000 --- a/target/linux/layerscape/patches-4.4/8231-driver-clk-qoriq-Add-ls2088a-clk-support.patch +++ /dev/null @@ -1,20 +0,0 @@ -From c62b4977614e133acc95c61237bcc8fe30581d13 Mon Sep 17 00:00:00 2001 -From: "ying.zhang" -Date: Thu, 22 Dec 2016 23:29:39 +0800 -Subject: [PATCH 231/238] driver: clk: qoriq: Add ls2088a clk support - -Signed-off-by: Zhao Qiang wq ---- - drivers/clk/clk-qoriq.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/clk/clk-qoriq.c -+++ b/drivers/clk/clk-qoriq.c -@@ -1346,6 +1346,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, " - CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init); - CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); - CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init); -+CLK_OF_DECLARE(qoriq_clockgen_ls2088a, "fsl,ls2088a-clockgen", clockgen_init); - - /* Legacy nodes */ - CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init); diff --git a/target/linux/layerscape/patches-4.4/8233-i2c-pca954x-Add-option-to-skip-disabling-PCA954x-Mux.patch b/target/linux/layerscape/patches-4.4/8233-i2c-pca954x-Add-option-to-skip-disabling-PCA954x-Mux.patch deleted file mode 100644 index 3cb39764fd..0000000000 --- a/target/linux/layerscape/patches-4.4/8233-i2c-pca954x-Add-option-to-skip-disabling-PCA954x-Mux.patch +++ /dev/null @@ -1,105 +0,0 @@ -From a4be9046c3a3fc39a06089553df8cc19a2abd814 Mon Sep 17 00:00:00 2001 -From: Priyanka Jain -Date: Tue, 3 Nov 2015 11:25:24 +0530 -Subject: [PATCH 233/238] i2c: pca954x: Add option to skip disabling PCA954x - Mux device - -On some Layerscape boards like LS2085ARDB/LS2080ARDB, -input pull-up resistors on PCA954x Mux device are -missing on board. So, if mux are disabled after powered-on, -input lines will float leading to incorrect functionality. - -Hence, PCA954x Mux device should never be turned-off after -power-on. - -Add option to skip disabling PCA954x Mux device -if device tree contians "i2c-mux-never-disable" property -for pca954x device node. - -Signed-off-by: Priyanka Jain ---- - drivers/i2c/muxes/i2c-mux-pca954x.c | 38 +++++++++++++++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - ---- a/drivers/i2c/muxes/i2c-mux-pca954x.c -+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c -@@ -63,6 +63,7 @@ struct pca954x { - struct i2c_adapter *virt_adaps[PCA954X_MAX_NCHANS]; - - u8 last_chan; /* last register value */ -+ u8 disable_mux; /* do not disable mux if val not 0 */ - }; - - struct chip_desc { -@@ -174,6 +175,13 @@ static int pca954x_deselect_mux(struct i - { - struct pca954x *data = i2c_get_clientdata(client); - -+#ifdef CONFIG_ARCH_LAYERSCAPE -+ if (data->disable_mux != 0) -+ data->last_chan = chips[data->type].nchans; -+ else -+ data->last_chan = 0; -+ return pca954x_reg_write(adap, client, data->disable_mux); -+#endif - /* Deselect active channel */ - data->last_chan = 0; - return pca954x_reg_write(adap, client, data->last_chan); -@@ -201,6 +209,23 @@ static int pca954x_probe(struct i2c_clie - if (!data) - return -ENOMEM; - -+#ifdef CONFIG_ARCH_LAYERSCAPE -+ /* The point here is that you must not disable a mux if there -+ * are no pullups on the input or you mess up the I2C. This -+ * needs to be put into the DTS really as the kernel cannot -+ * know this otherwise. -+ */ -+ data->type = id->driver_data; -+ data->disable_mux = of_node && -+ of_property_read_bool(of_node, "i2c-mux-never-disable") && -+ chips[data->type].muxtype == pca954x_ismux ? -+ chips[data->type].enable : 0; -+ /* force the first selection */ -+ if (data->disable_mux != 0) -+ data->last_chan = chips[data->type].nchans; -+ else -+ data->last_chan = 0; -+#endif - i2c_set_clientdata(client, data); - - /* Get the mux out of reset if a reset GPIO is specified. */ -@@ -212,13 +237,19 @@ static int pca954x_probe(struct i2c_clie - * that the mux is in fact present. This also - * initializes the mux to disconnected state. - */ -+#ifdef CONFIG_ARCH_LAYERSCAPE -+ if (i2c_smbus_write_byte(client, data->disable_mux) < 0) { -+#else - if (i2c_smbus_write_byte(client, 0) < 0) { -+#endif - dev_warn(&client->dev, "probe failed\n"); - return -ENODEV; - } - -+#ifndef CONFIG_ARCH_LAYERSCAPE - data->type = id->driver_data; - data->last_chan = 0; /* force the first selection */ -+#endif - - idle_disconnect_dt = of_node && - of_property_read_bool(of_node, "i2c-mux-idle-disconnect"); -@@ -289,6 +320,13 @@ static int pca954x_resume(struct device - struct i2c_client *client = to_i2c_client(dev); - struct pca954x *data = i2c_get_clientdata(client); - -+#ifdef CONFIG_ARCH_LAYERSCAPE -+ if (data->disable_mux != 0) -+ data->last_chan = chips[data->type].nchans; -+ else -+ data->last_chan = 0; -+ return i2c_smbus_write_byte(client, data->disable_mux); -+#endif - data->last_chan = 0; - return i2c_smbus_write_byte(client, 0); - } diff --git a/target/linux/layerscape/patches-4.4/8235-pci-layerscape-fix-pci-lut-offset-issue.patch b/target/linux/layerscape/patches-4.4/8235-pci-layerscape-fix-pci-lut-offset-issue.patch deleted file mode 100644 index def79412d7..0000000000 --- a/target/linux/layerscape/patches-4.4/8235-pci-layerscape-fix-pci-lut-offset-issue.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 2f3ea65dc8909cbf4116bd74b3dea8d25749508f Mon Sep 17 00:00:00 2001 -From: Zhao Qiang -Date: Wed, 23 Nov 2016 11:29:45 +0800 -Subject: [PATCH 235/238] pci/layerscape: fix pci lut offset issue - -Signed-off-by: Zhao Qiang ---- - drivers/pci/host/pci-layerscape.c | 13 ++++--------- - 1 file changed, 4 insertions(+), 9 deletions(-) - ---- a/drivers/pci/host/pci-layerscape.c -+++ b/drivers/pci/host/pci-layerscape.c -@@ -158,16 +158,11 @@ static void ls1021_pcie_host_init(struct - static int ls_pcie_link_up(struct pcie_port *pp) - { - struct ls_pcie *pcie = to_ls_pcie(pp); -- u32 state, offset; -+ u32 state; - -- if (of_get_property(pp->dev->of_node, "fsl,lut_diff", NULL)) -- offset = 0x407fc; -- else -- offset = PCIE_LUT_DBG; -- -- state = (ioread32(pcie->lut + offset) >> -- pcie->drvdata->ltssm_shift) & -- LTSSM_STATE_MASK; -+ state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> -+ pcie->drvdata->ltssm_shift) & -+ LTSSM_STATE_MASK; - - if (state < LTSSM_PCIE_L0) - return 0; diff --git a/target/linux/layerscape/patches-4.4/8236-clk-add-API-of-clks.patch b/target/linux/layerscape/patches-4.4/8236-clk-add-API-of-clks.patch deleted file mode 100644 index ce8b518303..0000000000 --- a/target/linux/layerscape/patches-4.4/8236-clk-add-API-of-clks.patch +++ /dev/null @@ -1,75 +0,0 @@ -From df2373ca941741f3f66750241a048ad4e2ff2c91 Mon Sep 17 00:00:00 2001 -From: Zhao Qiang -Date: Thu, 24 Nov 2016 11:47:45 +0800 -Subject: [PATCH 236/238] clk: add API of clks - -Signed-off-by: Zhao Qiang ---- - drivers/clk/clk.c | 19 +++++++++++++++++++ - include/linux/clk-provider.h | 1 + - include/linux/clk.h | 9 +++++++++ - 3 files changed, 29 insertions(+) - ---- a/drivers/clk/clk.c -+++ b/drivers/clk/clk.c -@@ -359,6 +359,19 @@ static struct clk_core *clk_core_get_par - return core->parents[index]; - } - -+struct clk *clk_get_parent_by_index(struct clk *clk, u8 index) -+{ -+ struct clk_core *parent; -+ -+ if (!clk) -+ return NULL; -+ -+ parent = clk_core_get_parent_by_index(clk->core, index); -+ -+ return !parent ? NULL : parent->hw->clk; -+} -+EXPORT_SYMBOL_GPL(clk_get_parent_by_index); -+ - struct clk_hw * - clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index) - { -@@ -2033,6 +2046,12 @@ static const struct file_operations clk_ - .release = single_release, - }; - -+unsigned int clk_get_num_parents(struct clk *clk) -+{ -+ return !clk ? 0 : clk->core->num_parents; -+} -+EXPORT_SYMBOL_GPL(clk_get_num_parents); -+ - static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level) - { - if (!c) ---- a/include/linux/clk-provider.h -+++ b/include/linux/clk-provider.h -@@ -656,6 +656,7 @@ unsigned int clk_hw_get_num_parents(cons - struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); - struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, - unsigned int index); -+struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); - unsigned int __clk_get_enable_count(struct clk *clk); - unsigned long clk_hw_get_rate(const struct clk_hw *hw); - unsigned long __clk_get_flags(struct clk *clk); ---- a/include/linux/clk.h -+++ b/include/linux/clk.h -@@ -392,6 +392,15 @@ int clk_set_parent(struct clk *clk, stru - struct clk *clk_get_parent(struct clk *clk); - - /** -+ * clk_get_num_parents - get number of possible parents -+ * @clk: clock source -+ * -+ * Returns the number of possible parents of this clock, -+ * which can then be enumerated using clk_get_parent_by_index(). -+ */ -+unsigned int clk_get_num_parents(struct clk *clk); -+ -+/** - * clk_get_sys - get a clock based upon the device name - * @dev_id: device name - * @con_id: connection ID diff --git a/target/linux/layerscape/patches-4.4/8237-pcie-ls208x-use-unified-compatible-fsl-ls2080a-pcie-.patch b/target/linux/layerscape/patches-4.4/8237-pcie-ls208x-use-unified-compatible-fsl-ls2080a-pcie-.patch deleted file mode 100644 index 6162e2b257..0000000000 --- a/target/linux/layerscape/patches-4.4/8237-pcie-ls208x-use-unified-compatible-fsl-ls2080a-pcie-.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 562f1311b529d81662ed41786b8d240db2e2ff51 Mon Sep 17 00:00:00 2001 -From: Shengzhou Liu -Date: Tue, 6 Dec 2016 15:30:39 +0800 -Subject: [PATCH 237/238] pcie/ls208x: use unified compatible - "fsl,ls2080a-pcie" for ls208x - -To avoid unnecessary reduplication, let's use unified compatible -"fsl,ls2080a-pcie" for ls2080a, ls2085a, ls2088a. - -This patch fixes issue of pcie not working on ls2088a. - -Signed-off-by: Shengzhou Liu ---- - arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 12 ++++-------- - drivers/pci/host/pci-layerscape.c | 13 ++++++++----- - 2 files changed, 12 insertions(+), 13 deletions(-) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi -@@ -513,8 +513,7 @@ - }; - - pcie1: pcie@3400000 { -- compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie", -- "fsl,ls2085a-pcie", "snps,dw-pcie"; -+ compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; -@@ -539,8 +538,7 @@ - }; - - pcie2: pcie@3500000 { -- compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie", -- "fsl,ls2085a-pcie", "snps,dw-pcie"; -+ compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; -@@ -565,8 +563,7 @@ - }; - - pcie3: pcie@3600000 { -- compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie", -- "fsl,ls2085a-pcie", "snps,dw-pcie"; -+ compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; -@@ -591,8 +588,7 @@ - }; - - pcie4: pcie@3700000 { -- compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie", -- "fsl,ls2085a-pcie", "snps,dw-pcie"; -+ compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; ---- a/drivers/pci/host/pci-layerscape.c -+++ b/drivers/pci/host/pci-layerscape.c -@@ -158,9 +158,14 @@ static void ls1021_pcie_host_init(struct - static int ls_pcie_link_up(struct pcie_port *pp) - { - struct ls_pcie *pcie = to_ls_pcie(pp); -- u32 state; -+ u32 state, offset; - -- state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> -+ if (of_get_property(pp->dev->of_node, "fsl,lut_diff", NULL)) -+ offset = 0x407fc; -+ else -+ offset = pcie->drvdata->lut_dbg; -+ -+ state = (ioread32(pcie->lut + offset) >> - pcie->drvdata->ltssm_shift) & - LTSSM_STATE_MASK; - -@@ -261,7 +266,6 @@ static const struct of_device_id ls_pcie - { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata }, - { .compatible = "fsl,ls1088a-pcie", .data = &ls1088_drvdata }, - { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, -- { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata }, - { }, - }; - MODULE_DEVICE_TABLE(of, ls_pcie_of_match); -@@ -315,8 +319,7 @@ static int __init ls_pcie_probe(struct p - if (!ls_pcie_is_bridge(pcie)) - return -ENODEV; - -- if (of_device_is_compatible(pdev->dev.of_node, "fsl,ls2085a-pcie") || -- of_device_is_compatible(pdev->dev.of_node, "fsl,ls2080a-pcie") || -+ if (of_device_is_compatible(pdev->dev.of_node, "fsl,ls2080a-pcie") || - of_device_is_compatible(pdev->dev.of_node, "fsl,ls1088a-pcie")) { - int len; - const u32 *prop; diff --git a/target/linux/layerscape/patches-4.4/8238-irqchip-ls-scfg-msi-fix-typo-of-MSI-compatible-strin.patch b/target/linux/layerscape/patches-4.4/8238-irqchip-ls-scfg-msi-fix-typo-of-MSI-compatible-strin.patch deleted file mode 100644 index 8f2c3831a3..0000000000 --- a/target/linux/layerscape/patches-4.4/8238-irqchip-ls-scfg-msi-fix-typo-of-MSI-compatible-strin.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 5cb8ea9dfcea4092fd3710cce3980a44433dc58f Mon Sep 17 00:00:00 2001 -From: Minghuan Lian -Date: Tue, 17 Jan 2017 17:32:35 +0800 -Subject: [PATCH 04/13] irqchip/ls-scfg-msi: fix typo of MSI compatible strings - -Cherry-pick patchwork patch with context adjustment. - -The patch is to fix typo of the Layerscape SCFG MSI dts compatible -strings. "1" is replaced by "l". - -Signed-off-by: Minghuan Lian -Acked-by: Rob Herring -Signed-off-by: Yangbo Lu ---- - .../devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt | 6 +++--- - drivers/irqchip/irq-ls-scfg-msi.c | 6 ++++-- - 2 files changed, 7 insertions(+), 5 deletions(-) - ---- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt -+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt -@@ -4,8 +4,8 @@ Required properties: - - - compatible: should be "fsl,-msi" to identify - Layerscape PCIe MSI controller block such as: -- "fsl,1s1021a-msi" -- "fsl,1s1043a-msi" -+ "fsl,ls1021a-msi" -+ "fsl,ls1043a-msi" - - msi-controller: indicates that this is a PCIe MSI controller node - - reg: physical base address of the controller and length of memory mapped. - - interrupts: an interrupt to the parent interrupt controller. -@@ -23,7 +23,7 @@ MSI controller node - Examples: - - msi1: msi-controller@1571000 { -- compatible = "fsl,1s1043a-msi"; -+ compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1571000 0x0 0x8>, - msi-controller; - interrupts = <0 116 0x4>; ---- a/drivers/irqchip/irq-ls-scfg-msi.c -+++ b/drivers/irqchip/irq-ls-scfg-msi.c -@@ -220,8 +220,10 @@ static int ls_scfg_msi_remove(struct pla - - static const struct of_device_id ls_scfg_msi_id[] = { - { .compatible = "fsl,ls1012a-msi", }, -- { .compatible = "fsl,1s1021a-msi", }, -- { .compatible = "fsl,1s1043a-msi", }, -+ { .compatible = "fsl,1s1021a-msi", }, /* a typo */ -+ { .compatible = "fsl,1s1043a-msi", }, /* a typo */ -+ { .compatible = "fsl,ls1021a-msi", }, -+ { .compatible = "fsl,ls1043a-msi", }, - { .compatible = "fsl,ls1046a-msi", }, - {}, - }; diff --git a/target/linux/layerscape/patches-4.4/8239-irqchip-ls-scfg-msi-add-LS1046a-MSI-support.patch b/target/linux/layerscape/patches-4.4/8239-irqchip-ls-scfg-msi-add-LS1046a-MSI-support.patch deleted file mode 100644 index bea806bf10..0000000000 --- a/target/linux/layerscape/patches-4.4/8239-irqchip-ls-scfg-msi-add-LS1046a-MSI-support.patch +++ /dev/null @@ -1,293 +0,0 @@ -From 20fd0e76257005cb46a2ce1a30018a45d96199bf Mon Sep 17 00:00:00 2001 -From: Minghuan Lian -Date: Tue, 17 Jan 2017 17:32:41 +0800 -Subject: [PATCH 10/13] irqchip/ls-scfg-msi: add LS1046a MSI support - -Cherry-pick patchwork patch with context adjustment. - -LS1046a includes 4 MSIRs, each MSIR is assigned a dedicate GIC -SPI interrupt and provides 32 MSI interrupts. Compared to previous -MSI, LS1046a's IBS(interrupt bit select) shift is changed to 2 and -total MSI interrupt number is changed to 128. - -The patch adds structure 'ls_scfg_msir' to describe MSIR setting and -'ibs_shift' to store the different value between the SoCs. - -Signed-off-by: Minghuan Lian -Signed-off-by: Yangbo Lu ---- - drivers/irqchip/irq-ls-scfg-msi.c | 168 +++++++++++++++++++++++++++++--------- - 1 file changed, 131 insertions(+), 37 deletions(-) - ---- a/drivers/irqchip/irq-ls-scfg-msi.c -+++ b/drivers/irqchip/irq-ls-scfg-msi.c -@@ -17,13 +17,24 @@ - #include - #include - #include -+#include - #include - #include - #include - --#define MSI_MAX_IRQS 32 --#define MSI_IBS_SHIFT 3 --#define MSIR 4 -+#define MSI_IRQS_PER_MSIR 32 -+#define MSI_MSIR_OFFSET 4 -+ -+struct ls_scfg_msi_cfg { -+ u32 ibs_shift; /* Shift of interrupt bit select */ -+}; -+ -+struct ls_scfg_msir { -+ struct ls_scfg_msi *msi_data; -+ unsigned int index; -+ unsigned int gic_irq; -+ void __iomem *reg; -+}; - - struct ls_scfg_msi { - spinlock_t lock; -@@ -32,8 +43,11 @@ struct ls_scfg_msi { - struct irq_domain *msi_domain; - void __iomem *regs; - phys_addr_t msiir_addr; -- int irq; -- DECLARE_BITMAP(used, MSI_MAX_IRQS); -+ struct ls_scfg_msi_cfg *cfg; -+ u32 msir_num; -+ struct ls_scfg_msir *msir; -+ u32 irqs_num; -+ unsigned long *used; - }; - - static struct irq_chip ls_scfg_msi_irq_chip = { -@@ -55,7 +69,7 @@ static void ls_scfg_msi_compose_msg(stru - - msg->address_hi = upper_32_bits(msi_data->msiir_addr); - msg->address_lo = lower_32_bits(msi_data->msiir_addr); -- msg->data = data->hwirq << MSI_IBS_SHIFT; -+ msg->data = data->hwirq; - } - - static int ls_scfg_msi_set_affinity(struct irq_data *irq_data, -@@ -81,8 +95,8 @@ static int ls_scfg_msi_domain_irq_alloc( - WARN_ON(nr_irqs != 1); - - spin_lock(&msi_data->lock); -- pos = find_first_zero_bit(msi_data->used, MSI_MAX_IRQS); -- if (pos < MSI_MAX_IRQS) -+ pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num); -+ if (pos < msi_data->irqs_num) - __set_bit(pos, msi_data->used); - else - err = -ENOSPC; -@@ -106,7 +120,7 @@ static void ls_scfg_msi_domain_irq_free( - int pos; - - pos = d->hwirq; -- if (pos < 0 || pos >= MSI_MAX_IRQS) { -+ if (pos < 0 || pos >= msi_data->irqs_num) { - pr_err("failed to teardown msi. Invalid hwirq %d\n", pos); - return; - } -@@ -123,15 +137,17 @@ static const struct irq_domain_ops ls_sc - - static void ls_scfg_msi_irq_handler(struct irq_desc *desc) - { -- struct ls_scfg_msi *msi_data = irq_desc_get_handler_data(desc); -+ struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc); -+ struct ls_scfg_msi *msi_data = msir->msi_data; - unsigned long val; -- int pos, virq; -+ int pos, virq, hwirq; - - chained_irq_enter(irq_desc_get_chip(desc), desc); - -- val = ioread32be(msi_data->regs + MSIR); -- for_each_set_bit(pos, &val, MSI_MAX_IRQS) { -- virq = irq_find_mapping(msi_data->parent, (31 - pos)); -+ val = ioread32be(msir->reg); -+ for_each_set_bit(pos, &val, MSI_IRQS_PER_MSIR) { -+ hwirq = ((31 - pos) << msi_data->cfg->ibs_shift) | msir->index; -+ virq = irq_find_mapping(msi_data->parent, hwirq); - if (virq) - generic_handle_irq(virq); - } -@@ -143,7 +159,7 @@ static int ls_scfg_msi_domains_init(stru - { - /* Initialize MSI domain parent */ - msi_data->parent = irq_domain_add_linear(NULL, -- MSI_MAX_IRQS, -+ msi_data->irqs_num, - &ls_scfg_msi_domain_ops, - msi_data); - if (!msi_data->parent) { -@@ -164,16 +180,88 @@ static int ls_scfg_msi_domains_init(stru - return 0; - } - -+static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index) -+{ -+ struct ls_scfg_msir *msir; -+ int virq, i, hwirq; -+ -+ virq = platform_get_irq(msi_data->pdev, index); -+ if (virq <= 0) -+ return -ENODEV; -+ -+ msir = &msi_data->msir[index]; -+ msir->index = index; -+ msir->msi_data = msi_data; -+ msir->gic_irq = virq; -+ msir->reg = msi_data->regs + MSI_MSIR_OFFSET + 4 * index; -+ -+ irq_set_chained_handler_and_data(msir->gic_irq, -+ ls_scfg_msi_irq_handler, -+ msir); -+ -+ /* Release the hwirqs corresponding to this MSIR */ -+ for (i = 0; i < MSI_IRQS_PER_MSIR; i++) { -+ hwirq = i << msi_data->cfg->ibs_shift | msir->index; -+ bitmap_clear(msi_data->used, hwirq, 1); -+ } -+ -+ return 0; -+} -+ -+static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir) -+{ -+ struct ls_scfg_msi *msi_data = msir->msi_data; -+ int i, hwirq; -+ -+ if (msir->gic_irq > 0) -+ irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL); -+ -+ for (i = 0; i < MSI_IRQS_PER_MSIR; i++) { -+ hwirq = i << msi_data->cfg->ibs_shift | msir->index; -+ bitmap_set(msi_data->used, hwirq, 1); -+ } -+ -+ return 0; -+} -+ -+static struct ls_scfg_msi_cfg ls1021_msi_cfg = { -+ .ibs_shift = 3, -+}; -+ -+static struct ls_scfg_msi_cfg ls1046_msi_cfg = { -+ .ibs_shift = 2, -+}; -+ -+static const struct of_device_id ls_scfg_msi_id[] = { -+ /* The following two misspelled compatibles are obsolete */ -+ { .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg}, -+ { .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg}, -+ -+ { .compatible = "fsl,ls1012a-msi", .data = &ls1021_msi_cfg }, -+ { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg }, -+ { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg }, -+ { .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ls_scfg_msi_id); -+ - static int ls_scfg_msi_probe(struct platform_device *pdev) - { -+ const struct of_device_id *match; - struct ls_scfg_msi *msi_data; - struct resource *res; -- int ret; -+ int i, ret; -+ -+ match = of_match_device(ls_scfg_msi_id, &pdev->dev); -+ if (!match) -+ return -ENODEV; - - msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL); - if (!msi_data) - return -ENOMEM; - -+ msi_data->cfg = (struct ls_scfg_msi_cfg *) match->data; -+ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - msi_data->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(msi_data->regs)) { -@@ -182,23 +270,37 @@ static int ls_scfg_msi_probe(struct plat - } - msi_data->msiir_addr = res->start; - -- msi_data->irq = platform_get_irq(pdev, 0); -- if (msi_data->irq <= 0) { -- dev_err(&pdev->dev, "failed to get MSI irq\n"); -- return -ENODEV; -- } -- - msi_data->pdev = pdev; - spin_lock_init(&msi_data->lock); - -+ msi_data->irqs_num = MSI_IRQS_PER_MSIR * -+ (1 << msi_data->cfg->ibs_shift); -+ msi_data->used = devm_kcalloc(&pdev->dev, -+ BITS_TO_LONGS(msi_data->irqs_num), -+ sizeof(*msi_data->used), -+ GFP_KERNEL); -+ if (!msi_data->used) -+ return -ENOMEM; -+ /* -+ * Reserve all the hwirqs -+ * The available hwirqs will be released in ls1_msi_setup_hwirq() -+ */ -+ bitmap_set(msi_data->used, 0, msi_data->irqs_num); -+ -+ msi_data->msir_num = of_irq_count(pdev->dev.of_node); -+ msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num, -+ sizeof(*msi_data->msir), -+ GFP_KERNEL); -+ if (!msi_data->msir) -+ return -ENOMEM; -+ -+ for (i = 0; i < msi_data->msir_num; i++) -+ ls_scfg_msi_setup_hwirq(msi_data, i); -+ - ret = ls_scfg_msi_domains_init(msi_data); - if (ret) - return ret; - -- irq_set_chained_handler_and_data(msi_data->irq, -- ls_scfg_msi_irq_handler, -- msi_data); -- - platform_set_drvdata(pdev, msi_data); - - return 0; -@@ -207,8 +309,10 @@ static int ls_scfg_msi_probe(struct plat - static int ls_scfg_msi_remove(struct platform_device *pdev) - { - struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev); -+ int i; - -- irq_set_chained_handler_and_data(msi_data->irq, NULL, NULL); -+ for (i = 0; i < msi_data->msir_num; i++) -+ ls_scfg_msi_teardown_hwirq(&msi_data->msir[i]); - - irq_domain_remove(msi_data->msi_domain); - irq_domain_remove(msi_data->parent); -@@ -218,16 +322,6 @@ static int ls_scfg_msi_remove(struct pla - return 0; - } - --static const struct of_device_id ls_scfg_msi_id[] = { -- { .compatible = "fsl,ls1012a-msi", }, -- { .compatible = "fsl,1s1021a-msi", }, /* a typo */ -- { .compatible = "fsl,1s1043a-msi", }, /* a typo */ -- { .compatible = "fsl,ls1021a-msi", }, -- { .compatible = "fsl,ls1043a-msi", }, -- { .compatible = "fsl,ls1046a-msi", }, -- {}, --}; -- - static struct platform_driver ls_scfg_msi_driver = { - .driver = { - .name = "ls-scfg-msi", diff --git a/target/linux/layerscape/patches-4.4/8240-irqchip-ls-scfg-msi-add-LS1043a-v1.1-MSI-support.patch b/target/linux/layerscape/patches-4.4/8240-irqchip-ls-scfg-msi-add-LS1043a-v1.1-MSI-support.patch deleted file mode 100644 index d1266a23ae..0000000000 --- a/target/linux/layerscape/patches-4.4/8240-irqchip-ls-scfg-msi-add-LS1043a-v1.1-MSI-support.patch +++ /dev/null @@ -1,134 +0,0 @@ -From ab9d5c5c767c17bf9526f84beb5667f2a50e1a4d Mon Sep 17 00:00:00 2001 -From: Minghuan Lian -Date: Tue, 17 Jan 2017 17:32:42 +0800 -Subject: [PATCH] irqchip/ls-scfg-msi: add LS1043a v1.1 MSI support - -Cherry-pick patchwork patch with context adjustment. - -A MSI controller of LS1043a v1.0 only includes one MSIR and -is assigned one GIC interrupt. In order to support affinity, -LS1043a v1.1 MSI is assigned 4 MSIRs and 4 GIC interrupts. -But the MSIR has the different offset and only supports 8 MSIs. -The bits between variable bit_start and bit_end in structure -ls_scfg_msir are used to show 8 MSI interrupts. msir_irqs and -msir_base are added to describe the difference of MSI between -LS1043a v1.1 and other SoCs. - -Signed-off-by: Minghuan Lian -Acked-by: Rob Herring -Signed-off-by: Yangbo Lu ---- - drivers/irqchip/irq-ls-scfg-msi.c | 45 +++++++++++++++++++++++++++++++++------ - 1 file changed, 39 insertions(+), 6 deletions(-) - ---- a/drivers/irqchip/irq-ls-scfg-msi.c -+++ b/drivers/irqchip/irq-ls-scfg-msi.c -@@ -25,14 +25,21 @@ - #define MSI_IRQS_PER_MSIR 32 - #define MSI_MSIR_OFFSET 4 - -+#define MSI_LS1043V1_1_IRQS_PER_MSIR 8 -+#define MSI_LS1043V1_1_MSIR_OFFSET 0x10 -+ - struct ls_scfg_msi_cfg { - u32 ibs_shift; /* Shift of interrupt bit select */ -+ u32 msir_irqs; /* The irq number per MSIR */ -+ u32 msir_base; /* The base address of MSIR */ - }; - - struct ls_scfg_msir { - struct ls_scfg_msi *msi_data; - unsigned int index; - unsigned int gic_irq; -+ unsigned int bit_start; -+ unsigned int bit_end; - void __iomem *reg; - }; - -@@ -140,13 +147,18 @@ static void ls_scfg_msi_irq_handler(stru - struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc); - struct ls_scfg_msi *msi_data = msir->msi_data; - unsigned long val; -- int pos, virq, hwirq; -+ int pos, size, virq, hwirq; - - chained_irq_enter(irq_desc_get_chip(desc), desc); - - val = ioread32be(msir->reg); -- for_each_set_bit(pos, &val, MSI_IRQS_PER_MSIR) { -- hwirq = ((31 - pos) << msi_data->cfg->ibs_shift) | msir->index; -+ -+ pos = msir->bit_start; -+ size = msir->bit_end + 1; -+ -+ for_each_set_bit_from(pos, &val, size) { -+ hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) | -+ msir->index; - virq = irq_find_mapping(msi_data->parent, hwirq); - if (virq) - generic_handle_irq(virq); -@@ -193,14 +205,24 @@ static int ls_scfg_msi_setup_hwirq(struc - msir->index = index; - msir->msi_data = msi_data; - msir->gic_irq = virq; -- msir->reg = msi_data->regs + MSI_MSIR_OFFSET + 4 * index; -+ msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index; -+ -+ if (msi_data->cfg->msir_irqs == MSI_LS1043V1_1_IRQS_PER_MSIR) { -+ msir->bit_start = 32 - ((msir->index + 1) * -+ MSI_LS1043V1_1_IRQS_PER_MSIR); -+ msir->bit_end = msir->bit_start + -+ MSI_LS1043V1_1_IRQS_PER_MSIR - 1; -+ } else { -+ msir->bit_start = 0; -+ msir->bit_end = msi_data->cfg->msir_irqs - 1; -+ } - - irq_set_chained_handler_and_data(msir->gic_irq, - ls_scfg_msi_irq_handler, - msir); - - /* Release the hwirqs corresponding to this MSIR */ -- for (i = 0; i < MSI_IRQS_PER_MSIR; i++) { -+ for (i = 0; i < msi_data->cfg->msir_irqs; i++) { - hwirq = i << msi_data->cfg->ibs_shift | msir->index; - bitmap_clear(msi_data->used, hwirq, 1); - } -@@ -216,7 +238,7 @@ static int ls_scfg_msi_teardown_hwirq(st - if (msir->gic_irq > 0) - irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL); - -- for (i = 0; i < MSI_IRQS_PER_MSIR; i++) { -+ for (i = 0; i < msi_data->cfg->msir_irqs; i++) { - hwirq = i << msi_data->cfg->ibs_shift | msir->index; - bitmap_set(msi_data->used, hwirq, 1); - } -@@ -226,10 +248,20 @@ static int ls_scfg_msi_teardown_hwirq(st - - static struct ls_scfg_msi_cfg ls1021_msi_cfg = { - .ibs_shift = 3, -+ .msir_irqs = MSI_IRQS_PER_MSIR, -+ .msir_base = MSI_MSIR_OFFSET, - }; - - static struct ls_scfg_msi_cfg ls1046_msi_cfg = { - .ibs_shift = 2, -+ .msir_irqs = MSI_IRQS_PER_MSIR, -+ .msir_base = MSI_MSIR_OFFSET, -+}; -+ -+static struct ls_scfg_msi_cfg ls1043_v1_1_msi_cfg = { -+ .ibs_shift = 2, -+ .msir_irqs = MSI_LS1043V1_1_IRQS_PER_MSIR, -+ .msir_base = MSI_LS1043V1_1_MSIR_OFFSET, - }; - - static const struct of_device_id ls_scfg_msi_id[] = { -@@ -240,6 +272,7 @@ static const struct of_device_id ls_scfg - { .compatible = "fsl,ls1012a-msi", .data = &ls1021_msi_cfg }, - { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg }, - { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg }, -+ { .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg }, - { .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg }, - {}, - }; diff --git a/target/linux/layerscape/patches-4.4/8241-irqchip-ls-scfg-msi-add-MSI-affinity-support.patch b/target/linux/layerscape/patches-4.4/8241-irqchip-ls-scfg-msi-add-MSI-affinity-support.patch deleted file mode 100644 index b3b3795b6c..0000000000 --- a/target/linux/layerscape/patches-4.4/8241-irqchip-ls-scfg-msi-add-MSI-affinity-support.patch +++ /dev/null @@ -1,152 +0,0 @@ -From a761ae710d6395af0d8d17a0b4b8f93a816ead46 Mon Sep 17 00:00:00 2001 -From: Minghuan Lian -Date: Tue, 17 Jan 2017 17:32:43 +0800 -Subject: [PATCH 12/13] irqchip/ls-scfg-msi: add MSI affinity support - -Cherry-pick patchwork patch. - -For LS1046a and LS1043a v1.1, the MSI controller has 4 MSIRs and 4 GIC -SPI interrupts which can be associated with different Core. -So we can support affinity to improve the performance. -The MSI message data is a byte for Layerscape MSI. - 7 6 5 4 3 2 1 0 -| - | IBS | SRS | -SRS bit0-1 is to select a MSIR which is associated with a CPU. -IBS bit2-6 of ls1046, bit2-4 of ls1043a v1.1 is to select bit of the -MSIR. With affinity, only bits of MSIR0(srs=0 cpu0) are available. -All other bits of the MSIR1-3(cpu1-3) are reserved. The MSI hwirq -always equals bit index of the MSIR0. When changing affinity, MSI -message data will be appended corresponding SRS then MSI will be -moved to the corresponding core. -But in affinity mode, there is only 8 MSI interrupts for a controller -of LS1043a v1.1. It cannot meet the requirement of the some PCIe -devices such as 4 ports Ethernet card. In contrast, without affinity, -all MSIRs can be used for core 0, the MSI interrupts can up to 32. -So the parameter is added to control affinity mode. -"lsmsi=no-affinity" will disable affinity and increase MSI -interrupt number. - -Signed-off-by: Minghuan Lian -Signed-off-by: Yangbo Lu ---- - drivers/irqchip/irq-ls-scfg-msi.c | 68 ++++++++++++++++++++++++++++++++++++--- - 1 file changed, 63 insertions(+), 5 deletions(-) - ---- a/drivers/irqchip/irq-ls-scfg-msi.c -+++ b/drivers/irqchip/irq-ls-scfg-msi.c -@@ -40,6 +40,7 @@ struct ls_scfg_msir { - unsigned int gic_irq; - unsigned int bit_start; - unsigned int bit_end; -+ unsigned int srs; /* Shared interrupt register select */ - void __iomem *reg; - }; - -@@ -70,6 +71,19 @@ static struct msi_domain_info ls_scfg_ms - .chip = &ls_scfg_msi_irq_chip, - }; - -+static int msi_affinity_flag = 1; -+ -+static int __init early_parse_ls_scfg_msi(char *p) -+{ -+ if (p && strncmp(p, "no-affinity", 11) == 0) -+ msi_affinity_flag = 0; -+ else -+ msi_affinity_flag = 1; -+ -+ return 0; -+} -+early_param("lsmsi", early_parse_ls_scfg_msi); -+ - static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg) - { - struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data); -@@ -77,12 +91,36 @@ static void ls_scfg_msi_compose_msg(stru - msg->address_hi = upper_32_bits(msi_data->msiir_addr); - msg->address_lo = lower_32_bits(msi_data->msiir_addr); - msg->data = data->hwirq; -+ -+ if (msi_affinity_flag) -+ msg->data |= cpumask_first(data->common->affinity); - } - - static int ls_scfg_msi_set_affinity(struct irq_data *irq_data, - const struct cpumask *mask, bool force) - { -- return -EINVAL; -+ struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data); -+ u32 cpu; -+ -+ if (!msi_affinity_flag) -+ return -EINVAL; -+ -+ if (!force) -+ cpu = cpumask_any_and(mask, cpu_online_mask); -+ else -+ cpu = cpumask_first(mask); -+ -+ if (cpu >= msi_data->msir_num) -+ return -EINVAL; -+ -+ if (msi_data->msir[cpu].gic_irq <= 0) { -+ pr_warn("cannot bind the irq to cpu%d\n", cpu); -+ return -EINVAL; -+ } -+ -+ cpumask_copy(irq_data->common->affinity, mask); -+ -+ return IRQ_SET_MASK_OK; - } - - static struct irq_chip ls_scfg_msi_parent_chip = { -@@ -158,7 +196,7 @@ static void ls_scfg_msi_irq_handler(stru - - for_each_set_bit_from(pos, &val, size) { - hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) | -- msir->index; -+ msir->srs; - virq = irq_find_mapping(msi_data->parent, hwirq); - if (virq) - generic_handle_irq(virq); -@@ -221,10 +259,19 @@ static int ls_scfg_msi_setup_hwirq(struc - ls_scfg_msi_irq_handler, - msir); - -+ if (msi_affinity_flag) { -+ /* Associate MSIR interrupt to the cpu */ -+ irq_set_affinity(msir->gic_irq, get_cpu_mask(index)); -+ msir->srs = 0; /* This value is determined by the CPU */ -+ } else -+ msir->srs = index; -+ - /* Release the hwirqs corresponding to this MSIR */ -- for (i = 0; i < msi_data->cfg->msir_irqs; i++) { -- hwirq = i << msi_data->cfg->ibs_shift | msir->index; -- bitmap_clear(msi_data->used, hwirq, 1); -+ if (!msi_affinity_flag || msir->index == 0) { -+ for (i = 0; i < msi_data->cfg->msir_irqs; i++) { -+ hwirq = i << msi_data->cfg->ibs_shift | msir->index; -+ bitmap_clear(msi_data->used, hwirq, 1); -+ } - } - - return 0; -@@ -321,6 +368,17 @@ static int ls_scfg_msi_probe(struct plat - bitmap_set(msi_data->used, 0, msi_data->irqs_num); - - msi_data->msir_num = of_irq_count(pdev->dev.of_node); -+ -+ if (msi_affinity_flag) { -+ u32 cpu_num; -+ -+ cpu_num = num_possible_cpus(); -+ if (msi_data->msir_num >= cpu_num) -+ msi_data->msir_num = cpu_num; -+ else -+ msi_affinity_flag = 0; -+ } -+ - msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num, - sizeof(*msi_data->msir), - GFP_KERNEL); diff --git a/target/linux/layerscape/patches-4.4/9069-Revert-arm64-simplify-dma_get_ops.patch b/target/linux/layerscape/patches-4.4/9069-Revert-arm64-simplify-dma_get_ops.patch deleted file mode 100644 index e2c356a7d0..0000000000 --- a/target/linux/layerscape/patches-4.4/9069-Revert-arm64-simplify-dma_get_ops.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 4885eb650b27f5639c8c72b8d4daa37f533b0b4d Mon Sep 17 00:00:00 2001 -From: Yutang Jiang -Date: Fri, 22 Jul 2016 01:03:29 +0800 -Subject: [PATCH 69/70] Revert "arm64: simplify dma_get_ops" - -This reverts commit 1dccb598df549d892b6450c261da54cdd7af44b4. ---- - arch/arm64/include/asm/dma-mapping.h | 13 ++++++++++--- - arch/arm64/mm/dma-mapping.c | 16 ++++++++++++---- - 2 files changed, 22 insertions(+), 7 deletions(-) - ---- a/arch/arm64/include/asm/dma-mapping.h -+++ b/arch/arm64/include/asm/dma-mapping.h -@@ -18,6 +18,7 @@ - - #ifdef __KERNEL__ - -+#include - #include - #include - -@@ -25,16 +26,22 @@ - #include - - #define DMA_ERROR_CODE (~(dma_addr_t)0) -+extern struct dma_map_ops *dma_ops; - extern struct dma_map_ops dummy_dma_ops; - - static inline struct dma_map_ops *__generic_dma_ops(struct device *dev) - { -- if (dev && dev->archdata.dma_ops) -+ if (unlikely(!dev)) -+ return dma_ops; -+ else if (dev->archdata.dma_ops) - return dev->archdata.dma_ops; -+ else if (acpi_disabled) -+ return dma_ops; - - /* -- * We expect no ISA devices, and all other DMA masters are expected to -- * have someone call arch_setup_dma_ops at device creation time. -+ * When ACPI is enabled, if arch_set_dma_ops is not called, -+ * we will disable device DMA capability by setting it -+ * to dummy_dma_ops. - */ - return &dummy_dma_ops; - } ---- a/arch/arm64/mm/dma-mapping.c -+++ b/arch/arm64/mm/dma-mapping.c -@@ -18,7 +18,6 @@ - */ - - #include --#include - #include - #include - #include -@@ -29,6 +28,9 @@ - - #include - -+struct dma_map_ops *dma_ops; -+EXPORT_SYMBOL(dma_ops); -+ - static pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot, - bool coherent) - { -@@ -513,7 +515,13 @@ EXPORT_SYMBOL(dummy_dma_ops); - - static int __init arm64_dma_init(void) - { -- return atomic_pool_init(); -+ int ret; -+ -+ dma_ops = &swiotlb_dma_ops; -+ -+ ret = atomic_pool_init(); -+ -+ return ret; - } - arch_initcall(arm64_dma_init); - -@@ -987,8 +995,8 @@ static void __iommu_setup_dma_ops(struct - void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, - struct iommu_ops *iommu, bool coherent) - { -- if (!dev->archdata.dma_ops) -- dev->archdata.dma_ops = &swiotlb_dma_ops; -+ if (!acpi_disabled && !dev->archdata.dma_ops) -+ dev->archdata.dma_ops = dma_ops; - - dev->archdata.dma_coherent = coherent; - __iommu_setup_dma_ops(dev, dma_base, size, iommu); diff --git a/target/linux/layerscape/patches-4.4/9070-Revert-arm64-use-fixmap-region-for-permanent-FDT-map.patch b/target/linux/layerscape/patches-4.4/9070-Revert-arm64-use-fixmap-region-for-permanent-FDT-map.patch deleted file mode 100644 index c247db474a..0000000000 --- a/target/linux/layerscape/patches-4.4/9070-Revert-arm64-use-fixmap-region-for-permanent-FDT-map.patch +++ /dev/null @@ -1,304 +0,0 @@ -From 6f7a129e59721f6d97a0f06f7078d06f19ade69e Mon Sep 17 00:00:00 2001 -From: Yutang Jiang -Date: Thu, 21 Jul 2016 19:37:42 +0800 -Subject: [PATCH 70/70] Revert "arm64: use fixmap region for permanent FDT - mapping" - -Signed-off-by: Yutang Jiang ---- - Documentation/arm64/booting.txt | 10 +++---- - arch/arm64/include/asm/boot.h | 14 ---------- - arch/arm64/include/asm/fixmap.h | 15 ----------- - arch/arm64/include/asm/mmu.h | 1 - - arch/arm64/kernel/head.S | 39 ++++++++++++++++++++++++++- - arch/arm64/kernel/setup.c | 29 +++++++++++++------- - arch/arm64/mm/init.c | 1 + - arch/arm64/mm/mmu.c | 57 --------------------------------------- - 8 files changed, 62 insertions(+), 104 deletions(-) - delete mode 100644 arch/arm64/include/asm/boot.h - ---- a/Documentation/arm64/booting.txt -+++ b/Documentation/arm64/booting.txt -@@ -45,13 +45,11 @@ sees fit.) - - Requirement: MANDATORY - --The device tree blob (dtb) must be placed on an 8-byte boundary and must --not exceed 2 megabytes in size. Since the dtb will be mapped cacheable --using blocks of up to 2 megabytes in size, it must not be placed within --any 2M region which must be mapped with any specific attributes. -+The device tree blob (dtb) must be placed on an 8-byte boundary within -+the first 512 megabytes from the start of the kernel image and must not -+cross a 2-megabyte boundary. This is to allow the kernel to map the -+blob using a single section mapping in the initial page tables. - --NOTE: versions prior to v4.2 also require that the DTB be placed within --the 512 MB region starting at text_offset bytes below the kernel Image. - - 3. Decompress the kernel image - ------------------------------ ---- a/arch/arm64/include/asm/boot.h -+++ /dev/null -@@ -1,14 +0,0 @@ -- --#ifndef __ASM_BOOT_H --#define __ASM_BOOT_H -- --#include -- --/* -- * arm64 requires the DTB to be 8 byte aligned and -- * not exceed 2MB in size. -- */ --#define MIN_FDT_ALIGN 8 --#define MAX_FDT_SIZE SZ_2M -- --#endif ---- a/arch/arm64/include/asm/fixmap.h -+++ b/arch/arm64/include/asm/fixmap.h -@@ -18,7 +18,6 @@ - #ifndef __ASSEMBLY__ - #include - #include --#include - #include - - /* -@@ -34,20 +33,6 @@ - */ - enum fixed_addresses { - FIX_HOLE, -- -- /* -- * Reserve a virtual window for the FDT that is 2 MB larger than the -- * maximum supported size, and put it at the top of the fixmap region. -- * The additional space ensures that any FDT that does not exceed -- * MAX_FDT_SIZE can be mapped regardless of whether it crosses any -- * 2 MB alignment boundaries. -- * -- * Keep this at the top so it remains 2 MB aligned. -- */ --#define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M) -- FIX_FDT_END, -- FIX_FDT = FIX_FDT_END + FIX_FDT_SIZE / PAGE_SIZE - 1, -- - FIX_EARLYCON_MEM_BASE, - FIX_TEXT_POKE0, - __end_of_permanent_fixed_addresses, ---- a/arch/arm64/include/asm/mmu.h -+++ b/arch/arm64/include/asm/mmu.h -@@ -34,6 +34,5 @@ extern void init_mem_pgprot(void); - extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys, - unsigned long virt, phys_addr_t size, - pgprot_t prot); --extern void *fixmap_remap_fdt(phys_addr_t dt_phys); - - #endif ---- a/arch/arm64/kernel/head.S -+++ b/arch/arm64/kernel/head.S -@@ -212,6 +212,8 @@ ENTRY(stext) - bl el2_setup // Drop to EL1, w20=cpu_boot_mode - adrp x24, __PHYS_OFFSET - bl set_cpu_boot_mode_flag -+ -+ bl __vet_fdt - bl __create_page_tables // x25=TTBR0, x26=TTBR1 - /* - * The following calls CPU setup code, see arch/arm64/mm/proc.S for -@@ -243,6 +245,24 @@ preserve_boot_args: - ENDPROC(preserve_boot_args) - - /* -+ * Determine validity of the x21 FDT pointer. -+ * The dtb must be 8-byte aligned and live in the first 512M of memory. -+ */ -+__vet_fdt: -+ tst x21, #0x7 -+ b.ne 1f -+ cmp x21, x24 -+ b.lt 1f -+ mov x0, #(1 << 29) -+ add x0, x0, x24 -+ cmp x21, x0 -+ b.ge 1f -+ ret -+1: -+ mov x21, #0 -+ ret -+ENDPROC(__vet_fdt) -+/* - * Macro to create a table entry to the next page. - * - * tbl: page table address -@@ -306,7 +326,8 @@ ENDPROC(preserve_boot_args) - * required to get the kernel running. The following sections are required: - * - identity mapping to enable the MMU (low address, TTBR0) - * - first few MB of the kernel linear mapping to jump to once the MMU has -- * been enabled -+ * been enabled, including the FDT blob (TTBR1) -+ * - pgd entry for fixed mappings (TTBR1) - */ - __create_page_tables: - adrp x25, idmap_pg_dir -@@ -396,6 +417,22 @@ __create_page_tables: - create_block_map x0, x7, x3, x5, x6 - - /* -+ * Map the FDT blob (maximum 2MB; must be within 512MB of -+ * PHYS_OFFSET). -+ */ -+ mov x3, x21 // FDT phys address -+ and x3, x3, #~((1 << 21) - 1) // 2MB aligned -+ mov x6, #PAGE_OFFSET -+ sub x5, x3, x24 // subtract PHYS_OFFSET -+ tst x5, #~((1 << 29) - 1) // within 512MB? -+ csel x21, xzr, x21, ne // zero the FDT pointer -+ b.ne 1f -+ add x5, x5, x6 // __va(FDT blob) -+ add x6, x5, #1 << 21 // 2MB for the FDT blob -+ sub x6, x6, #1 // inclusive range -+ create_block_map x0, x7, x3, x5, x6 -+1: -+ /* - * Since the page tables have been populated with non-cacheable - * accesses (MMU disabled), invalidate the idmap and swapper page - * tables again to remove any speculatively loaded cache lines. ---- a/arch/arm64/kernel/setup.c -+++ b/arch/arm64/kernel/setup.c -@@ -87,6 +87,18 @@ static struct resource mem_res[] = { - #define kernel_code mem_res[0] - #define kernel_data mem_res[1] - -+void __init early_print(const char *str, ...) -+{ -+ char buf[256]; -+ va_list ap; -+ -+ va_start(ap, str); -+ vsnprintf(buf, sizeof(buf), str, ap); -+ va_end(ap); -+ -+ printk("%s", buf); -+} -+ - /* - * The recorded values of x0 .. x3 upon kernel entry. - */ -@@ -180,14 +192,12 @@ static void __init smp_build_mpidr_hash( - - static void __init setup_machine_fdt(phys_addr_t dt_phys) - { -- void *dt_virt = fixmap_remap_fdt(dt_phys); -- -- if (!dt_virt || !early_init_dt_scan(dt_virt)) { -- pr_crit("\n" -- "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n" -- "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n" -- "\nPlease check your bootloader.", -- &dt_phys, dt_virt); -+ if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) { -+ early_print("\n" -+ "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n" -+ "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n" -+ "\nPlease check your bootloader.\n", -+ dt_phys, phys_to_virt(dt_phys)); - - while (true) - cpu_relax(); -@@ -294,6 +304,7 @@ void __init setup_arch(char **cmdline_p) - pr_info("Boot CPU: AArch64 Processor [%08x]\n", read_cpuid_id()); - - sprintf(init_utsname()->machine, ELF_PLATFORM); -+ setup_machine_fdt(__fdt_pointer); - init_mm.start_code = (unsigned long) _text; - init_mm.end_code = (unsigned long) _etext; - init_mm.end_data = (unsigned long) _edata; -@@ -304,8 +315,6 @@ void __init setup_arch(char **cmdline_p) - early_fixmap_init(); - early_ioremap_init(); - -- setup_machine_fdt(__fdt_pointer); -- - parse_early_param(); - - /* ---- a/arch/arm64/mm/init.c -+++ b/arch/arm64/mm/init.c -@@ -171,6 +171,7 @@ void __init arm64_memblock_init(void) - memblock_reserve(__virt_to_phys(initrd_start), initrd_end - initrd_start); - #endif - -+ early_init_fdt_reserve_self(); - early_init_fdt_scan_reserved_mem(); - - /* 4GB maximum for 32-bit only capable devices */ ---- a/arch/arm64/mm/mmu.c -+++ b/arch/arm64/mm/mmu.c -@@ -21,7 +21,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -641,59 +640,3 @@ void __set_fixmap(enum fixed_addresses i - flush_tlb_kernel_range(addr, addr+PAGE_SIZE); - } - } -- --void *__init fixmap_remap_fdt(phys_addr_t dt_phys) --{ -- const u64 dt_virt_base = __fix_to_virt(FIX_FDT); -- pgprot_t prot = PAGE_KERNEL_RO; -- int size, offset; -- void *dt_virt; -- -- /* -- * Check whether the physical FDT address is set and meets the minimum -- * alignment requirement. Since we are relying on MIN_FDT_ALIGN to be -- * at least 8 bytes so that we can always access the magic and size -- * fields of the FDT header after mapping the first chunk, double check -- * here if that is indeed the case. -- */ -- BUILD_BUG_ON(MIN_FDT_ALIGN < 8); -- if (!dt_phys || dt_phys % MIN_FDT_ALIGN) -- return NULL; -- -- /* -- * Make sure that the FDT region can be mapped without the need to -- * allocate additional translation table pages, so that it is safe -- * to call create_mapping() this early. -- * -- * On 64k pages, the FDT will be mapped using PTEs, so we need to -- * be in the same PMD as the rest of the fixmap. -- * On 4k pages, we'll use section mappings for the FDT so we only -- * have to be in the same PUD. -- */ -- BUILD_BUG_ON(dt_virt_base % SZ_2M); -- -- BUILD_BUG_ON(__fix_to_virt(FIX_FDT_END) >> SWAPPER_TABLE_SHIFT != -- __fix_to_virt(FIX_BTMAP_BEGIN) >> SWAPPER_TABLE_SHIFT); -- -- offset = dt_phys % SWAPPER_BLOCK_SIZE; -- dt_virt = (void *)dt_virt_base + offset; -- -- /* map the first chunk so we can read the size from the header */ -- create_mapping(round_down(dt_phys, SWAPPER_BLOCK_SIZE), dt_virt_base, -- SWAPPER_BLOCK_SIZE, prot); -- -- if (fdt_magic(dt_virt) != FDT_MAGIC) -- return NULL; -- -- size = fdt_totalsize(dt_virt); -- if (size > MAX_FDT_SIZE) -- return NULL; -- -- if (offset + size > SWAPPER_BLOCK_SIZE) -- create_mapping(round_down(dt_phys, SWAPPER_BLOCK_SIZE), dt_virt_base, -- round_up(offset + size, SWAPPER_BLOCK_SIZE), prot); -- -- memblock_reserve(dt_phys, size); -- -- return dt_virt; --}