From: Markus Stockhausen Date: Fri, 13 Feb 2026 08:26:20 +0000 (+0100) Subject: realtek: convert mach includes to rtl-otto X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=2b4cdb6941965df1b6f8abd68348b71117b09262;p=openwrt%2Fopenwrt.git realtek: convert mach includes to rtl-otto Right now the global includes are all named rtl838x. This suggests that they are only for one of the four SoC types (RTL838x aka Maple) required. As we are talking about the Otto platform rename that accordingly. All the drivers have already adapted that some time ago. Signed-off-by: Markus Stockhausen Link: https://github.com/openwrt/openwrt/pull/22005 Signed-off-by: Robert Marko --- diff --git a/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl-otto/ioremap.h b/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl-otto/ioremap.h new file mode 100644 index 0000000000..c49a095792 --- /dev/null +++ b/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl-otto/ioremap.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef RTL838X_IOREMAP_H_ +#define RTL838X_IOREMAP_H_ + +static inline int is_rtl838x_internal_registers(phys_addr_t offset) +{ + /* IO-Block */ + if (offset >= 0xb8000000 && offset < 0xb9000000) + return 1; + /* Switch block */ + if (offset >= 0xbb000000 && offset < 0xbc000000) + return 1; + return 0; +} + +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, + unsigned long flags) +{ + if (is_rtl838x_internal_registers(offset)) + return (void __iomem *)offset; + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return is_rtl838x_internal_registers((unsigned long)addr); +} + +#endif diff --git a/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl-otto/mach-rtl-otto.h b/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl-otto/mach-rtl-otto.h new file mode 100644 index 0000000000..8639661a94 --- /dev/null +++ b/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl-otto/mach-rtl-otto.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * Copyright (C) 2020 B. Koblitz + */ +#ifndef _MACH_RTL838X_H_ +#define _MACH_RTL838X_H_ + +#include +#include + +/* + * Register access macros + */ + +#define RTL838X_SW_BASE ((volatile void *) 0xBB000000) + +#define sw_r32(reg) readl(RTL838X_SW_BASE + reg) +#define sw_w32(val, reg) writel(val, RTL838X_SW_BASE + reg) +#define sw_w32_mask(clear, set, reg) sw_w32((sw_r32(reg) & ~(clear)) | (set), reg) + +#define RTL838X_MODEL_NAME_INFO (0x00D4) +#define RTL838X_CHIP_INFO (0x00D8) +#define RTL839X_MODEL_NAME_INFO (0x0FF0) +#define RTL839X_CHIP_INFO (0x0FF4) +#define RTL93XX_MODEL_NAME_INFO (0x0004) +#define RTL93XX_CHIP_INFO (0x0008) + +#define RTL838X_INT_RW_CTRL (0x0058) +#define RTL838X_EXT_VERSION (0x00D0) + +/* Definition of family IDs */ +#define RTL8380_FAMILY_ID (0x8380) +#define RTL8390_FAMILY_ID (0x8390) +#define RTL9300_FAMILY_ID (0x9300) +#define RTL9310_FAMILY_ID (0x9310) + +/* Basic SoC Features */ +#define RTL838X_CPU_PORT 28 +#define RTL839X_CPU_PORT 52 +#define RTL930X_CPU_PORT 28 +#define RTL931X_CPU_PORT 56 + +struct rtl83xx_soc_info { + unsigned char *name; + unsigned int id; + unsigned int family; + unsigned int revision; + unsigned int cpu; + bool testchip; + int cpu_port; + int memory_size; +}; + +#endif /* _MACH_RTL838X_H_ */ diff --git a/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl838x/ioremap.h b/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl838x/ioremap.h deleted file mode 100644 index c49a095792..0000000000 --- a/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl838x/ioremap.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef RTL838X_IOREMAP_H_ -#define RTL838X_IOREMAP_H_ - -static inline int is_rtl838x_internal_registers(phys_addr_t offset) -{ - /* IO-Block */ - if (offset >= 0xb8000000 && offset < 0xb9000000) - return 1; - /* Switch block */ - if (offset >= 0xbb000000 && offset < 0xbc000000) - return 1; - return 0; -} - -static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, - unsigned long flags) -{ - if (is_rtl838x_internal_registers(offset)) - return (void __iomem *)offset; - return NULL; -} - -static inline int plat_iounmap(const volatile void __iomem *addr) -{ - return is_rtl838x_internal_registers((unsigned long)addr); -} - -#endif diff --git a/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h b/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h deleted file mode 100644 index 8639661a94..0000000000 --- a/target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) - * Copyright (C) 2020 B. Koblitz - */ -#ifndef _MACH_RTL838X_H_ -#define _MACH_RTL838X_H_ - -#include -#include - -/* - * Register access macros - */ - -#define RTL838X_SW_BASE ((volatile void *) 0xBB000000) - -#define sw_r32(reg) readl(RTL838X_SW_BASE + reg) -#define sw_w32(val, reg) writel(val, RTL838X_SW_BASE + reg) -#define sw_w32_mask(clear, set, reg) sw_w32((sw_r32(reg) & ~(clear)) | (set), reg) - -#define RTL838X_MODEL_NAME_INFO (0x00D4) -#define RTL838X_CHIP_INFO (0x00D8) -#define RTL839X_MODEL_NAME_INFO (0x0FF0) -#define RTL839X_CHIP_INFO (0x0FF4) -#define RTL93XX_MODEL_NAME_INFO (0x0004) -#define RTL93XX_CHIP_INFO (0x0008) - -#define RTL838X_INT_RW_CTRL (0x0058) -#define RTL838X_EXT_VERSION (0x00D0) - -/* Definition of family IDs */ -#define RTL8380_FAMILY_ID (0x8380) -#define RTL8390_FAMILY_ID (0x8390) -#define RTL9300_FAMILY_ID (0x9300) -#define RTL9310_FAMILY_ID (0x9310) - -/* Basic SoC Features */ -#define RTL838X_CPU_PORT 28 -#define RTL839X_CPU_PORT 52 -#define RTL930X_CPU_PORT 28 -#define RTL931X_CPU_PORT 56 - -struct rtl83xx_soc_info { - unsigned char *name; - unsigned int id; - unsigned int family; - unsigned int revision; - unsigned int cpu; - bool testchip; - int cpu_port; - int memory_size; -}; - -#endif /* _MACH_RTL838X_H_ */ diff --git a/target/linux/realtek/files-6.12/arch/mips/rtl-otto/Makefile b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/Makefile new file mode 100644 index 0000000000..a9d1666d46 --- /dev/null +++ b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the rtl838x specific parts of the kernel +# + +obj-y := setup.o prom.o diff --git a/target/linux/realtek/files-6.12/arch/mips/rtl-otto/Platform b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/Platform new file mode 100644 index 0000000000..0b98b3927b --- /dev/null +++ b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/Platform @@ -0,0 +1,5 @@ +# +# Realtek RTL838x SoCs +# +cflags-$(CONFIG_MACH_REALTEK_RTL) += -I$(srctree)/arch/mips/include/asm/mach-rtl-otto/ +load-$(CONFIG_MACH_REALTEK_RTL) += 0xffffffff80100000 diff --git a/target/linux/realtek/files-6.12/arch/mips/rtl-otto/prom.c b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/prom.c new file mode 100644 index 0000000000..22b8030e4e --- /dev/null +++ b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/prom.c @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * prom.c + * Early initialization code for the Realtek RTL838X SoC + * + * based on the original BSP by + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * Copyright (C) 2020 B. Koblitz + * + */ + +#include +#include +#include +#include +#include + +#include + +#define RTL_SOC_BASE ((volatile void *) 0xB8000000) + +#define RTL83XX_DRAM_CONFIG 0x1004 + +#define RTL9300_SRAMSAR0 0x4000 +#define RTL9300_SRAMSAR1 0x4010 +#define RTL9300_SRAMSAR2 0x4020 +#define RTL9300_SRAMSAR3 0x4030 +#define RTL9300_UMSAR0 0x1300 +#define RTL9300_UMSAR1 0x1310 +#define RTL9300_UMSAR2 0x1320 +#define RTL9300_UMSAR3 0x1330 +#define RTL9300_O0DOR2 0x4220 +#define RTL9300_O0DMAR2 0x4224 + +#define RTL931X_DRAM_CONFIG 0x14304c + +#define soc_r32(reg) readl(RTL_SOC_BASE + reg) +#define soc_w32(val, reg) writel(val, RTL_SOC_BASE + reg) + +struct rtl83xx_soc_info soc_info; +const void *fdt; + +static char rtl_soc_name[16]; +static char rtl_system_type[48]; + +#ifdef CONFIG_MIPS_MT_SMP + +extern const struct plat_smp_ops vsmp_smp_ops; +static struct plat_smp_ops rtl_smp_ops; + +static void rtlsmp_init_secondary(void) +{ + /* + * Enable all CPU interrupts, as everything is managed by the external controller. + * TODO: Standard vsmp_init_secondary() has special treatment for Malta if external + * GIC is available. Maybe we need this too. + */ + if (mips_gic_present()) + pr_warn("%s: GIC present. Maybe interrupt enabling required.\n", __func__); + else + set_c0_status(ST0_IM); +} + +static void rtlsmp_finish(void) +{ + /* These devices are low on resources. There might be the chance that CEVT_R4K is + * not enabled in kernel build. Nevertheless the timer and interrupt 7 might be + * active by default after startup of secondary VPEs. With no registered handler + * that leads to continuous unhandeled interrupts. Disable it but keep the counter + * running so it can still be used as an entropy source. + */ + if (!IS_ENABLED(CONFIG_CEVT_R4K)) { + write_c0_status(read_c0_status() & ~CAUSEF_IP7); + write_c0_compare(read_c0_count() - 1); + } + + local_irq_enable(); +} + +static int rtlsmp_register(void) +{ + if (!cpu_has_mipsmt) + return 1; + + rtl_smp_ops = vsmp_smp_ops; + rtl_smp_ops.init_secondary = rtlsmp_init_secondary; + rtl_smp_ops.smp_finish = rtlsmp_finish; + register_smp_ops(&rtl_smp_ops); + + return 0; +} + +#else /* !CONFIG_MIPS_MT_SMP */ + +#define rtlsmp_register() (1) + +#endif + +static void __init apply_early_quirks(void) +{ + /* Open up write protected registers. Never mess with this elsewhere */ + if (soc_info.family == RTL8380_FAMILY_ID) + sw_w32(0x3, RTL838X_INT_RW_CTRL); +} + +void __init device_tree_init(void) +{ + if (!fdt_check_header(&__appended_dtb)) { + fdt = &__appended_dtb; + pr_info("Using appended Device Tree.\n"); + } + initial_boot_params = (void *)fdt; + unflatten_and_copy_device_tree(); + + /* delay cpc & smp probing to allow devicetree access */ + mips_cpc_probe(); + + if (!register_cps_smp_ops()) + return; + + if (!rtlsmp_register()) + return; + + register_up_smp_ops(); +} + +const char *get_system_type(void) +{ + return rtl_system_type; +} + +static void __init rtl838x_read_details(u32 model) +{ + u32 chip_info, ext_version, tmp; + + sw_w32(0xa << 28, RTL838X_CHIP_INFO); + + chip_info = sw_r32(RTL838X_CHIP_INFO); + soc_info.cpu = chip_info & 0xffff; + + ext_version = sw_r32(RTL838X_EXT_VERSION); + tmp = ext_version & 0x1f; + + if (tmp == 2) { + soc_info.revision = 1; + } else { + tmp = (chip_info >> 16) & 0x1f; + if (soc_info.cpu == 0x0477) { + soc_info.revision = tmp; + soc_info.testchip = true; + } else { + soc_info.revision = tmp - 1; + } + } +} + +static void __init rtl839x_read_details(u32 model) +{ + u32 chip_info; + + sw_w32(0xa << 28, RTL839X_CHIP_INFO); + + chip_info = sw_r32(RTL839X_CHIP_INFO); + soc_info.cpu = chip_info & 0xffff; + + soc_info.revision = (model >> 1) & 0x1f; + + if (!(model & 0x3e)) + soc_info.testchip = true; +} + +static void __init rtl93xx_read_details(u32 model) +{ + u32 chip_info; + + sw_w32(0xa << 16, RTL93XX_CHIP_INFO); + + chip_info = sw_r32(RTL93XX_CHIP_INFO); + soc_info.cpu = chip_info & 0xffff; + + soc_info.revision = model & 0xf; + + if (model & 0x30) + soc_info.testchip = true; +} + +static u32 __init read_model(void) +{ + u32 model, id; + + model = sw_r32(RTL838X_MODEL_NAME_INFO); + id = model >> 16 & 0xffff; + if ((id >= 0x8380 && id <= 0x8382) || id == 0x8330 || id == 0x8332) { + soc_info.id = id; + soc_info.family = RTL8380_FAMILY_ID; + soc_info.cpu_port = RTL838X_CPU_PORT; + apply_early_quirks(); + rtl838x_read_details(model); + return model; + } + + model = sw_r32(RTL839X_MODEL_NAME_INFO); + id = model >> 16 & 0xffff; + if ((id >= 0x8391 && id <= 0x8396) || (id >= 0x8351 && id <= 0x8353)) { + soc_info.id = id; + soc_info.family = RTL8390_FAMILY_ID; + soc_info.cpu_port = RTL839X_CPU_PORT; + apply_early_quirks(); + rtl839x_read_details(model); + return model; + } + + model = sw_r32(RTL93XX_MODEL_NAME_INFO); + id = model >> 16 & 0xffff; + if (id >= 0x9301 && id <= 0x9303) { + soc_info.id = id; + soc_info.family = RTL9300_FAMILY_ID; + soc_info.cpu_port = RTL930X_CPU_PORT; + apply_early_quirks(); + rtl93xx_read_details(model); + return model; + } else if (id >= 0x9311 && id <= 0x9313) { + soc_info.id = id; + soc_info.family = RTL9310_FAMILY_ID; + soc_info.cpu_port = RTL931X_CPU_PORT; + apply_early_quirks(); + rtl93xx_read_details(model); + return model; + } + + return 0; +} + +static void __init parse_model(u32 model) +{ + int val; + char suffix = 0; + + val = (model >> 11) & 0x1f; + if (val > 0 && val <= 26) + suffix = 'A' + (val - 1); + + snprintf(rtl_soc_name, sizeof(rtl_soc_name), "RTL%04X%c", + soc_info.id, suffix); + + soc_info.name = rtl_soc_name; +} + +static void __init set_system_type(void) +{ + char revision = '?'; + char *es = ""; + + if (soc_info.revision >= 0 && soc_info.revision < 26) + revision = 'A' + soc_info.revision; + + if (soc_info.testchip) + es = " ES"; + + snprintf(rtl_system_type, sizeof(rtl_system_type), + "Realtek %s%s rev %c (%04X)", + soc_info.name, es, revision, soc_info.cpu); +} + +static void get_system_memory(void) +{ + unsigned int dcr, bits; + + if (soc_info.family == RTL9310_FAMILY_ID) { + dcr = soc_r32(RTL931X_DRAM_CONFIG); + bits = (dcr >> 12) + ((dcr >> 6) & 0x3f) + (dcr & 0x3f); + } else { + dcr = soc_r32(RTL83XX_DRAM_CONFIG); + bits = ((dcr >> 28) & 0x3) + ((dcr >> 24) & 0x3) + + ((dcr >> 20) & 0xf) + ((dcr >> 16) & 0xf) + 20; + } + + soc_info.memory_size = 1 << bits; +} + +static void prepare_highmem(void) +{ + if ((soc_info.family != RTL9300_FAMILY_ID) || + (soc_info.memory_size <= 256 * 1024 * 1024) || + !IS_ENABLED(CONFIG_HIGHMEM)) + return; + + /* + * To use highmem on RTL930x, SRAM must be deactivated and the highmem mapping + * registers must be setup properly. The hardcoded 0x70000000 might be strange + * but at least it conforms somehow to the RTL931x devices. + * + * - RTL930x: highmem start 0x20000000 + offset 0x70000000 = 0x90000000 + * - RTL931x: highmem start 0x90000000 + no offset at all = 0x90000000 + */ + + pr_info("highmem kernel on RTL930x with > 256 MB RAM, adapt SoC memory mapping\n"); + + soc_w32(0, RTL9300_UMSAR0); + soc_w32(0, RTL9300_UMSAR1); + soc_w32(0, RTL9300_UMSAR2); + soc_w32(0, RTL9300_UMSAR3); + soc_w32(0, RTL9300_SRAMSAR0); + soc_w32(0, RTL9300_SRAMSAR1); + soc_w32(0, RTL9300_SRAMSAR2); + soc_w32(0, RTL9300_SRAMSAR3); + __sync(); + + soc_w32(0x70000000, RTL9300_O0DOR2); + soc_w32(0x7fffffff, RTL9300_O0DMAR2); + __sync(); +} + +void __init prom_init(void) +{ + u32 model = read_model(); + + parse_model(model); + set_system_type(); + get_system_memory(); + + pr_info("%s SoC with %d MB\n", get_system_type(), soc_info.memory_size >> 20); + + prepare_highmem(); + + /* + * fw_arg2 is be the pointer to the environment. Some devices (e.g. HP JG924A) hand + * over other than expected kernel boot arguments. Something like 0xfffdffff looks + * suspicous. Do extra cleanup for fw_init_cmdline() to avoid a hang during boot. + */ + if (fw_arg2 >= CKSEG2) + fw_arg2 = 0; + + fw_init_cmdline(); +} diff --git a/target/linux/realtek/files-6.12/arch/mips/rtl-otto/setup.c b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/setup.c new file mode 100644 index 0000000000..ee0b488cfd --- /dev/null +++ b/target/linux/realtek/files-6.12/arch/mips/rtl-otto/setup.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Setup for the Realtek RTL838X SoC: + * Memory, Timer and Serial + * + * Copyright (C) 2020 B. Koblitz + * based on the original BSP by + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "mach-rtl-otto.h" + +extern struct rtl83xx_soc_info soc_info; + +void __init plat_mem_setup(void) +{ + void *dtb; + + set_io_port_base(KSEG1); + + dtb = get_fdt(); + if (!dtb) + panic("no dtb found"); + + /* + * Load the devicetree. This causes the chosen node to be + * parsed resulting in our memory appearing + */ + __dt_setup_arch(dtb); +} + +static void plat_time_init_fallback(void) +{ + struct device_node *np; + u32 freq = 500000000; + + np = of_find_node_by_name(NULL, "cpus"); + if (!np) { + pr_err("Missing 'cpus' DT node, using default frequency."); + } else { + if (of_property_read_u32(np, "frequency", &freq) < 0) + pr_err("No 'frequency' property in DT, using default."); + else + pr_info("CPU frequency from device tree: %dMHz", freq / 1000000); + of_node_put(np); + } + mips_hpt_frequency = freq / 2; +} + +void __init plat_time_init(void) +{ +/* + * Initialization routine resembles generic MIPS plat_time_init() with + * lazy error handling. The final fallback is only needed until we have + * converted all device trees to new clock syntax. + */ + struct device_node *np; + struct clk *clk; + + of_clk_init(NULL); + + mips_hpt_frequency = 0; + np = of_get_cpu_node(0, NULL); + if (!np) { + pr_err("Failed to get CPU node\n"); + } else { + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); + } else { + mips_hpt_frequency = clk_get_rate(clk) / 2; + clk_put(clk); + } + } + + if (!mips_hpt_frequency) + plat_time_init_fallback(); + + timer_probe(); +} + +void __init arch_init_irq(void) +{ + irqchip_init(); +} diff --git a/target/linux/realtek/files-6.12/arch/mips/rtl838x/Makefile b/target/linux/realtek/files-6.12/arch/mips/rtl838x/Makefile deleted file mode 100644 index a9d1666d46..0000000000 --- a/target/linux/realtek/files-6.12/arch/mips/rtl838x/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the rtl838x specific parts of the kernel -# - -obj-y := setup.o prom.o diff --git a/target/linux/realtek/files-6.12/arch/mips/rtl838x/Platform b/target/linux/realtek/files-6.12/arch/mips/rtl838x/Platform deleted file mode 100644 index e824dee7b7..0000000000 --- a/target/linux/realtek/files-6.12/arch/mips/rtl838x/Platform +++ /dev/null @@ -1,5 +0,0 @@ -# -# Realtek RTL838x SoCs -# -cflags-$(CONFIG_MACH_REALTEK_RTL) += -I$(srctree)/arch/mips/include/asm/mach-rtl838x/ -load-$(CONFIG_MACH_REALTEK_RTL) += 0xffffffff80100000 diff --git a/target/linux/realtek/files-6.12/arch/mips/rtl838x/prom.c b/target/linux/realtek/files-6.12/arch/mips/rtl838x/prom.c deleted file mode 100644 index 9258bd5675..0000000000 --- a/target/linux/realtek/files-6.12/arch/mips/rtl838x/prom.c +++ /dev/null @@ -1,335 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * prom.c - * Early initialization code for the Realtek RTL838X SoC - * - * based on the original BSP by - * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) - * Copyright (C) 2020 B. Koblitz - * - */ - -#include -#include -#include -#include -#include - -#include - -#define RTL_SOC_BASE ((volatile void *) 0xB8000000) - -#define RTL83XX_DRAM_CONFIG 0x1004 - -#define RTL9300_SRAMSAR0 0x4000 -#define RTL9300_SRAMSAR1 0x4010 -#define RTL9300_SRAMSAR2 0x4020 -#define RTL9300_SRAMSAR3 0x4030 -#define RTL9300_UMSAR0 0x1300 -#define RTL9300_UMSAR1 0x1310 -#define RTL9300_UMSAR2 0x1320 -#define RTL9300_UMSAR3 0x1330 -#define RTL9300_O0DOR2 0x4220 -#define RTL9300_O0DMAR2 0x4224 - -#define RTL931X_DRAM_CONFIG 0x14304c - -#define soc_r32(reg) readl(RTL_SOC_BASE + reg) -#define soc_w32(val, reg) writel(val, RTL_SOC_BASE + reg) - -struct rtl83xx_soc_info soc_info; -const void *fdt; - -static char rtl_soc_name[16]; -static char rtl_system_type[48]; - -#ifdef CONFIG_MIPS_MT_SMP - -extern const struct plat_smp_ops vsmp_smp_ops; -static struct plat_smp_ops rtl_smp_ops; - -static void rtlsmp_init_secondary(void) -{ - /* - * Enable all CPU interrupts, as everything is managed by the external controller. - * TODO: Standard vsmp_init_secondary() has special treatment for Malta if external - * GIC is available. Maybe we need this too. - */ - if (mips_gic_present()) - pr_warn("%s: GIC present. Maybe interrupt enabling required.\n", __func__); - else - set_c0_status(ST0_IM); -} - -static void rtlsmp_finish(void) -{ - /* These devices are low on resources. There might be the chance that CEVT_R4K is - * not enabled in kernel build. Nevertheless the timer and interrupt 7 might be - * active by default after startup of secondary VPEs. With no registered handler - * that leads to continuous unhandeled interrupts. Disable it but keep the counter - * running so it can still be used as an entropy source. - */ - if (!IS_ENABLED(CONFIG_CEVT_R4K)) { - write_c0_status(read_c0_status() & ~CAUSEF_IP7); - write_c0_compare(read_c0_count() - 1); - } - - local_irq_enable(); -} - -static int rtlsmp_register(void) -{ - if (!cpu_has_mipsmt) - return 1; - - rtl_smp_ops = vsmp_smp_ops; - rtl_smp_ops.init_secondary = rtlsmp_init_secondary; - rtl_smp_ops.smp_finish = rtlsmp_finish; - register_smp_ops(&rtl_smp_ops); - - return 0; -} - -#else /* !CONFIG_MIPS_MT_SMP */ - -#define rtlsmp_register() (1) - -#endif - -static void __init apply_early_quirks(void) -{ - /* Open up write protected registers. Never mess with this elsewhere */ - if (soc_info.family == RTL8380_FAMILY_ID) - sw_w32(0x3, RTL838X_INT_RW_CTRL); -} - -void __init device_tree_init(void) -{ - if (!fdt_check_header(&__appended_dtb)) { - fdt = &__appended_dtb; - pr_info("Using appended Device Tree.\n"); - } - initial_boot_params = (void *)fdt; - unflatten_and_copy_device_tree(); - - /* delay cpc & smp probing to allow devicetree access */ - mips_cpc_probe(); - - if (!register_cps_smp_ops()) - return; - - if (!rtlsmp_register()) - return; - - register_up_smp_ops(); -} - -const char *get_system_type(void) -{ - return rtl_system_type; -} - -static void __init rtl838x_read_details(u32 model) -{ - u32 chip_info, ext_version, tmp; - - sw_w32(0xa << 28, RTL838X_CHIP_INFO); - - chip_info = sw_r32(RTL838X_CHIP_INFO); - soc_info.cpu = chip_info & 0xffff; - - ext_version = sw_r32(RTL838X_EXT_VERSION); - tmp = ext_version & 0x1f; - - if (tmp == 2) { - soc_info.revision = 1; - } else { - tmp = (chip_info >> 16) & 0x1f; - if (soc_info.cpu == 0x0477) { - soc_info.revision = tmp; - soc_info.testchip = true; - } else { - soc_info.revision = tmp - 1; - } - } -} - -static void __init rtl839x_read_details(u32 model) -{ - u32 chip_info; - - sw_w32(0xa << 28, RTL839X_CHIP_INFO); - - chip_info = sw_r32(RTL839X_CHIP_INFO); - soc_info.cpu = chip_info & 0xffff; - - soc_info.revision = (model >> 1) & 0x1f; - - if (!(model & 0x3e)) - soc_info.testchip = true; -} - -static void __init rtl93xx_read_details(u32 model) -{ - u32 chip_info; - - sw_w32(0xa << 16, RTL93XX_CHIP_INFO); - - chip_info = sw_r32(RTL93XX_CHIP_INFO); - soc_info.cpu = chip_info & 0xffff; - - soc_info.revision = model & 0xf; - - if (model & 0x30) - soc_info.testchip = true; -} - -static u32 __init read_model(void) -{ - u32 model, id; - - model = sw_r32(RTL838X_MODEL_NAME_INFO); - id = model >> 16 & 0xffff; - if ((id >= 0x8380 && id <= 0x8382) || id == 0x8330 || id == 0x8332) { - soc_info.id = id; - soc_info.family = RTL8380_FAMILY_ID; - soc_info.cpu_port = RTL838X_CPU_PORT; - apply_early_quirks(); - rtl838x_read_details(model); - return model; - } - - model = sw_r32(RTL839X_MODEL_NAME_INFO); - id = model >> 16 & 0xffff; - if ((id >= 0x8391 && id <= 0x8396) || (id >= 0x8351 && id <= 0x8353)) { - soc_info.id = id; - soc_info.family = RTL8390_FAMILY_ID; - soc_info.cpu_port = RTL839X_CPU_PORT; - apply_early_quirks(); - rtl839x_read_details(model); - return model; - } - - model = sw_r32(RTL93XX_MODEL_NAME_INFO); - id = model >> 16 & 0xffff; - if (id >= 0x9301 && id <= 0x9303) { - soc_info.id = id; - soc_info.family = RTL9300_FAMILY_ID; - soc_info.cpu_port = RTL930X_CPU_PORT; - apply_early_quirks(); - rtl93xx_read_details(model); - return model; - } else if (id >= 0x9311 && id <= 0x9313) { - soc_info.id = id; - soc_info.family = RTL9310_FAMILY_ID; - soc_info.cpu_port = RTL931X_CPU_PORT; - apply_early_quirks(); - rtl93xx_read_details(model); - return model; - } - - return 0; -} - -static void __init parse_model(u32 model) -{ - int val; - char suffix = 0; - - val = (model >> 11) & 0x1f; - if (val > 0 && val <= 26) - suffix = 'A' + (val - 1); - - snprintf(rtl_soc_name, sizeof(rtl_soc_name), "RTL%04X%c", - soc_info.id, suffix); - - soc_info.name = rtl_soc_name; -} - -static void __init set_system_type(void) -{ - char revision = '?'; - char *es = ""; - - if (soc_info.revision >= 0 && soc_info.revision < 26) - revision = 'A' + soc_info.revision; - - if (soc_info.testchip) - es = " ES"; - - snprintf(rtl_system_type, sizeof(rtl_system_type), - "Realtek %s%s rev %c (%04X)", - soc_info.name, es, revision, soc_info.cpu); -} - -static void get_system_memory(void) -{ - unsigned int dcr, bits; - - if (soc_info.family == RTL9310_FAMILY_ID) { - dcr = soc_r32(RTL931X_DRAM_CONFIG); - bits = (dcr >> 12) + ((dcr >> 6) & 0x3f) + (dcr & 0x3f); - } else { - dcr = soc_r32(RTL83XX_DRAM_CONFIG); - bits = ((dcr >> 28) & 0x3) + ((dcr >> 24) & 0x3) + - ((dcr >> 20) & 0xf) + ((dcr >> 16) & 0xf) + 20; - } - - soc_info.memory_size = 1 << bits; -} - -static void prepare_highmem(void) -{ - if ((soc_info.family != RTL9300_FAMILY_ID) || - (soc_info.memory_size <= 256 * 1024 * 1024) || - !IS_ENABLED(CONFIG_HIGHMEM)) - return; - - /* - * To use highmem on RTL930x, SRAM must be deactivated and the highmem mapping - * registers must be setup properly. The hardcoded 0x70000000 might be strange - * but at least it conforms somehow to the RTL931x devices. - * - * - RTL930x: highmem start 0x20000000 + offset 0x70000000 = 0x90000000 - * - RTL931x: highmem start 0x90000000 + no offset at all = 0x90000000 - */ - - pr_info("highmem kernel on RTL930x with > 256 MB RAM, adapt SoC memory mapping\n"); - - soc_w32(0, RTL9300_UMSAR0); - soc_w32(0, RTL9300_UMSAR1); - soc_w32(0, RTL9300_UMSAR2); - soc_w32(0, RTL9300_UMSAR3); - soc_w32(0, RTL9300_SRAMSAR0); - soc_w32(0, RTL9300_SRAMSAR1); - soc_w32(0, RTL9300_SRAMSAR2); - soc_w32(0, RTL9300_SRAMSAR3); - __sync(); - - soc_w32(0x70000000, RTL9300_O0DOR2); - soc_w32(0x7fffffff, RTL9300_O0DMAR2); - __sync(); -} - -void __init prom_init(void) -{ - u32 model = read_model(); - - parse_model(model); - set_system_type(); - get_system_memory(); - - pr_info("%s SoC with %d MB\n", get_system_type(), soc_info.memory_size >> 20); - - prepare_highmem(); - - /* - * fw_arg2 is be the pointer to the environment. Some devices (e.g. HP JG924A) hand - * over other than expected kernel boot arguments. Something like 0xfffdffff looks - * suspicous. Do extra cleanup for fw_init_cmdline() to avoid a hang during boot. - */ - if (fw_arg2 >= CKSEG2) - fw_arg2 = 0; - - fw_init_cmdline(); -} diff --git a/target/linux/realtek/files-6.12/arch/mips/rtl838x/setup.c b/target/linux/realtek/files-6.12/arch/mips/rtl838x/setup.c deleted file mode 100644 index 73d689058e..0000000000 --- a/target/linux/realtek/files-6.12/arch/mips/rtl838x/setup.c +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Setup for the Realtek RTL838X SoC: - * Memory, Timer and Serial - * - * Copyright (C) 2020 B. Koblitz - * based on the original BSP by - * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "mach-rtl83xx.h" - -extern struct rtl83xx_soc_info soc_info; - -void __init plat_mem_setup(void) -{ - void *dtb; - - set_io_port_base(KSEG1); - - dtb = get_fdt(); - if (!dtb) - panic("no dtb found"); - - /* - * Load the devicetree. This causes the chosen node to be - * parsed resulting in our memory appearing - */ - __dt_setup_arch(dtb); -} - -static void plat_time_init_fallback(void) -{ - struct device_node *np; - u32 freq = 500000000; - - np = of_find_node_by_name(NULL, "cpus"); - if (!np) { - pr_err("Missing 'cpus' DT node, using default frequency."); - } else { - if (of_property_read_u32(np, "frequency", &freq) < 0) - pr_err("No 'frequency' property in DT, using default."); - else - pr_info("CPU frequency from device tree: %dMHz", freq / 1000000); - of_node_put(np); - } - mips_hpt_frequency = freq / 2; -} - -void __init plat_time_init(void) -{ -/* - * Initialization routine resembles generic MIPS plat_time_init() with - * lazy error handling. The final fallback is only needed until we have - * converted all device trees to new clock syntax. - */ - struct device_node *np; - struct clk *clk; - - of_clk_init(NULL); - - mips_hpt_frequency = 0; - np = of_get_cpu_node(0, NULL); - if (!np) { - pr_err("Failed to get CPU node\n"); - } else { - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); - } else { - mips_hpt_frequency = clk_get_rate(clk) / 2; - clk_put(clk); - } - } - - if (!mips_hpt_frequency) - plat_time_init_fallback(); - - timer_probe(); -} - -void __init arch_init_irq(void) -{ - irqchip_init(); -} diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c index a4598e205f..8a69ef35b2 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include "rtl83xx.h" diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/debugfs.c index 4216899798..6e0c251501 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/debugfs.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/debugfs.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include "rtl83xx.h" diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c index 06334c812a..8b72c00d66 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #include "rtl83xx.h" diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/qos.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/qos.c index 33e0331b0c..b620cc6350 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/qos.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/qos.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include "rtl83xx.h" diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c index 87d7579f8f..75f7fccb91 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -#include +#include #include #include #include diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h index a3da09f579..6750fe94df 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h @@ -3,7 +3,7 @@ #ifndef _RTL838X_H #define _RTL838X_H -#include +#include #include /* Register definition */ diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c index a7e84931d7..13944f136c 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -#include +#include #include #include "rtl83xx.h" diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c index 83e38facd5..b079e63c70 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -#include +#include #include #include diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c index 992dc7794f..dbf51adfd2 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -#include +#include #include #include "rtl83xx.h" diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/tc.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/tc.c index 016f59fbd0..4a9b6b8c9f 100644 --- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/tc.c +++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/tc.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include "rtl83xx.h" #include "rtl838x.h" diff --git a/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c index 4aa44fdc55..7a557afb64 100644 --- a/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c @@ -20,7 +20,7 @@ #include #include -#include +#include #include "rtl838x_eth.h" int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data); diff --git a/target/linux/realtek/patches-6.12/300-mips-add-rtl838x-platform.patch b/target/linux/realtek/patches-6.12/300-mips-add-rtl838x-platform.patch index b15decaa93..c0ebb3184f 100644 --- a/target/linux/realtek/patches-6.12/300-mips-add-rtl838x-platform.patch +++ b/target/linux/realtek/patches-6.12/300-mips-add-rtl838x-platform.patch @@ -15,7 +15,7 @@ Submitted-by: Birger Koblitz platform-$(CONFIG_PIC32MZDA) += pic32/ platform-$(CONFIG_RALINK) += ralink/ platform-$(CONFIG_MIKROTIK_RB532) += rb532/ -+platform-$(CONFIG_MACH_REALTEK_RTL) += rtl838x/ ++platform-$(CONFIG_MACH_REALTEK_RTL) += rtl-otto/ platform-$(CONFIG_SGI_IP22) += sgi-ip22/ platform-$(CONFIG_SGI_IP27) += sgi-ip27/ platform-$(CONFIG_SGI_IP28) += sgi-ip22/