From: Romain Perier Date: Sun, 23 Aug 2015 09:32:37 +0000 (+0200) Subject: clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188 X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=3bba75a2ec32bd5fa7024a4de3b8cf9ee113a76a;p=openwrt%2Fstaging%2Fblogic.git clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188 Now that the rockchip clock subsystem does clock gating with GPIO banks, these are no longer enabled once during probe and no longer stay enabled for eternity. When all these clocks are disabled, the parent clock pclk_peri might be disabled too, as no other child claims it. So, we need to add pclk_peri to the critical clocks. Signed-off-by: Romain Perier Tested-by: Michael Niewoehner Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index fa2f36b2abe7..abb47608713b 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -717,6 +717,7 @@ static const char *const rk3188_critical_clocks[] __initconst = { "aclk_peri", "hclk_peri", "pclk_cpu", + "pclk_peri", }; static void __init rk3188_common_clk_init(struct device_node *np)