From: Ralf Baechle <ralf@linux-mips.org>
Date: Fri, 19 Jun 2009 14:01:44 +0000 (+0100)
Subject: MIPS: Hibernation: Remove SMP TLB and cacheflushing code.
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=44eeab67416711db9b84610ef18c99a60415dff8;p=openwrt%2Fstaging%2Fblogic.git

MIPS: Hibernation: Remove SMP TLB and cacheflushing code.

We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled.  A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled.  A local
flush is not needed either because we didn't change any mappings.  So
just delete the code.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S
index 486bd3fd01a1..4b8174b382d7 100644
--- a/arch/mips/power/hibernate.S
+++ b/arch/mips/power/hibernate.S
@@ -43,15 +43,6 @@ LEAF(swsusp_arch_resume)
 	bne t1, t3, 1b
 	PTR_L t0, PBE_NEXT(t0)
 	bnez t0, 0b
-	/* flush caches to make sure context is in memory */
-	PTR_L t0, __flush_cache_all
-	jalr t0
-	/* flush tlb entries */
-#ifdef CONFIG_SMP
-	jal	flush_tlb_all
-#else
-	jal	local_flush_tlb_all
-#endif
 	PTR_LA t0, saved_regs
 	PTR_L ra, PT_R31(t0)
 	PTR_L sp, PT_R29(t0)