From: Krzysztof Kozlowski <krzk@kernel.org>
Date: Tue, 26 Dec 2017 13:07:18 +0000 (+0100)
Subject: drm/exynos/decon: Move headers from global to local place
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=4f52e55081fb81d6348ecca1f5e2cd45480ca559;p=openwrt%2Fstaging%2Fblogic.git

drm/exynos/decon: Move headers from global to local place

The DECON headers contain only defines for registers.  There are no
other drivers using them so this should be put locally to the Exynos DRM
driver.  Keeping headers local helps managing the code.

Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
---

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 1d509a815d68..1c330f2a7a5d 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -21,13 +21,12 @@
 #include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 
-#include <video/exynos5433_decon.h>
-
 #include "exynos_drm_drv.h"
 #include "exynos_drm_crtc.h"
 #include "exynos_drm_fb.h"
 #include "exynos_drm_plane.h"
 #include "exynos_drm_iommu.h"
+#include "regs-decon5433.h"
 
 #define DSD_CFG_MUX 0x1004
 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
index 615efcf7782a..3931d5e33fe0 100644
--- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
@@ -25,13 +25,13 @@
 
 #include <video/of_display_timing.h>
 #include <video/of_videomode.h>
-#include <video/exynos7_decon.h>
 
 #include "exynos_drm_crtc.h"
 #include "exynos_drm_plane.h"
 #include "exynos_drm_drv.h"
 #include "exynos_drm_fb.h"
 #include "exynos_drm_iommu.h"
+#include "regs-decon7.h"
 
 /*
  * DECON stands for Display and Enhancement controller.
diff --git a/drivers/gpu/drm/exynos/regs-decon5433.h b/drivers/gpu/drm/exynos/regs-decon5433.h
new file mode 100644
index 000000000000..78957c9626f5
--- /dev/null
+++ b/drivers/gpu/drm/exynos/regs-decon5433.h
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics Co.Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundationr
+ */
+
+#ifndef EXYNOS_REGS_DECON_H
+#define EXYNOS_REGS_DECON_H
+
+/* Exynos543X DECON */
+#define DECON_VIDCON0			0x0000
+#define DECON_VIDOUTCON0		0x0010
+#define DECON_WINCONx(n)		(0x0020 + ((n) * 4))
+#define DECON_VIDOSDxH(n)		(0x0080 + ((n) * 4))
+#define DECON_SHADOWCON			0x00A0
+#define DECON_VIDOSDxA(n)		(0x00B0 + ((n) * 0x20))
+#define DECON_VIDOSDxB(n)		(0x00B4 + ((n) * 0x20))
+#define DECON_VIDOSDxC(n)		(0x00B8 + ((n) * 0x20))
+#define DECON_VIDOSDxD(n)		(0x00BC + ((n) * 0x20))
+#define DECON_VIDOSDxE(n)		(0x00C0 + ((n) * 0x20))
+#define DECON_VIDW0xADD0B0(n)		(0x0150 + ((n) * 0x10))
+#define DECON_VIDW0xADD0B1(n)		(0x0154 + ((n) * 0x10))
+#define DECON_VIDW0xADD0B2(n)		(0x0158 + ((n) * 0x10))
+#define DECON_VIDW0xADD1B0(n)		(0x01A0 + ((n) * 0x10))
+#define DECON_VIDW0xADD1B1(n)		(0x01A4 + ((n) * 0x10))
+#define DECON_VIDW0xADD1B2(n)		(0x01A8 + ((n) * 0x10))
+#define DECON_VIDW0xADD2(n)		(0x0200 + ((n) * 4))
+#define DECON_LOCALxSIZE(n)		(0x0214 + ((n) * 4))
+#define DECON_VIDINTCON0		0x0220
+#define DECON_VIDINTCON1		0x0224
+#define DECON_WxKEYCON0(n)		(0x0230 + ((n - 1) * 8))
+#define DECON_WxKEYCON1(n)		(0x0234 + ((n - 1) * 8))
+#define DECON_WxKEYALPHA(n)		(0x0250 + ((n - 1) * 4))
+#define DECON_WINxMAP(n)		(0x0270 + ((n) * 4))
+#define DECON_QOSLUT07_00		0x02C0
+#define DECON_QOSLUT15_08		0x02C4
+#define DECON_QOSCTRL			0x02C8
+#define DECON_BLENDERQx(n)		(0x0300 + ((n - 1) * 4))
+#define DECON_BLENDCON			0x0310
+#define DECON_OPE_VIDW0xADD0(n)		(0x0400 + ((n) * 4))
+#define DECON_OPE_VIDW0xADD1(n)		(0x0414 + ((n) * 4))
+#define DECON_FRAMEFIFO_REG7		0x051C
+#define DECON_FRAMEFIFO_REG8		0x0520
+#define DECON_FRAMEFIFO_STATUS		0x0524
+#define DECON_CMU			0x1404
+#define DECON_UPDATE			0x1410
+#define DECON_CRFMID			0x1414
+#define DECON_UPDATE_SCHEME		0x1438
+#define DECON_VIDCON1			0x2000
+#define DECON_VIDCON2			0x2004
+#define DECON_VIDCON3			0x2008
+#define DECON_VIDCON4			0x200C
+#define DECON_VIDTCON2			0x2028
+#define DECON_FRAME_SIZE		0x2038
+#define DECON_LINECNT_OP_THRESHOLD	0x203C
+#define DECON_TRIGCON			0x2040
+#define DECON_TRIGSKIP			0x2050
+#define DECON_CRCRDATA			0x20B0
+#define DECON_CRCCTRL			0x20B4
+
+/* Exynos5430 DECON */
+#define DECON_VIDTCON0			0x2020
+#define DECON_VIDTCON1			0x2024
+
+/* Exynos5433 DECON */
+#define DECON_VIDTCON00			0x2010
+#define DECON_VIDTCON01			0x2014
+#define DECON_VIDTCON10			0x2018
+#define DECON_VIDTCON11			0x201C
+
+/* Exynos543X DECON Internal */
+#define DECON_W013DSTREOCON		0x0320
+#define DECON_W233DSTREOCON		0x0324
+#define DECON_FRAMEFIFO_REG0		0x0500
+#define DECON_ENHANCER_CTRL		0x2100
+
+/* Exynos543X DECON TV */
+#define DECON_VCLKCON0			0x0014
+#define DECON_VIDINTCON2		0x0228
+#define DECON_VIDINTCON3		0x022C
+
+/* VIDCON0 */
+#define VIDCON0_SWRESET			(1 << 28)
+#define VIDCON0_CLKVALUP		(1 << 14)
+#define VIDCON0_VLCKFREE		(1 << 5)
+#define VIDCON0_STOP_STATUS		(1 << 2)
+#define VIDCON0_ENVID			(1 << 1)
+#define VIDCON0_ENVID_F			(1 << 0)
+
+/* VIDOUTCON0 */
+#define VIDOUT_INTERLACE_FIELD_F	(1 << 29)
+#define VIDOUT_INTERLACE_EN_F		(1 << 28)
+#define VIDOUT_LCD_ON			(1 << 24)
+#define VIDOUT_IF_F_MASK		(0x3 << 20)
+#define VIDOUT_RGB_IF			(0x0 << 20)
+#define VIDOUT_COMMAND_IF		(0x2 << 20)
+
+/* WINCONx */
+#define WINCONx_HAWSWP_F		(1 << 16)
+#define WINCONx_WSWP_F			(1 << 15)
+#define WINCONx_BURSTLEN_MASK		(0x3 << 10)
+#define WINCONx_BURSTLEN_16WORD		(0x0 << 10)
+#define WINCONx_BURSTLEN_8WORD		(0x1 << 10)
+#define WINCONx_BURSTLEN_4WORD		(0x2 << 10)
+#define WINCONx_BLD_PIX_F		(1 << 6)
+#define WINCONx_BPPMODE_MASK		(0xf << 2)
+#define WINCONx_BPPMODE_16BPP_565	(0x5 << 2)
+#define WINCONx_BPPMODE_16BPP_A1555	(0x6 << 2)
+#define WINCONx_BPPMODE_16BPP_I1555	(0x7 << 2)
+#define WINCONx_BPPMODE_24BPP_888	(0xb << 2)
+#define WINCONx_BPPMODE_24BPP_A1887	(0xc << 2)
+#define WINCONx_BPPMODE_25BPP_A1888	(0xd << 2)
+#define WINCONx_BPPMODE_32BPP_A8888	(0xd << 2)
+#define WINCONx_BPPMODE_16BPP_A4444	(0xe << 2)
+#define WINCONx_ALPHA_SEL_F		(1 << 1)
+#define WINCONx_ENWIN_F			(1 << 0)
+
+/* SHADOWCON */
+#define SHADOWCON_PROTECT_MASK		GENMASK(14, 10)
+#define SHADOWCON_Wx_PROTECT(n)		(1 << (10 + (n)))
+
+/* VIDOSDxD */
+#define VIDOSD_Wx_ALPHA_R_F(n)		(((n) & 0xff) << 16)
+#define VIDOSD_Wx_ALPHA_G_F(n)		(((n) & 0xff) << 8)
+#define VIDOSD_Wx_ALPHA_B_F(n)		(((n) & 0xff) << 0)
+
+/* VIDINTCON0 */
+#define VIDINTCON0_FRAMEDONE		(1 << 17)
+#define VIDINTCON0_FRAMESEL_BP		(0 << 15)
+#define VIDINTCON0_FRAMESEL_VS		(1 << 15)
+#define VIDINTCON0_FRAMESEL_AC		(2 << 15)
+#define VIDINTCON0_FRAMESEL_FP		(3 << 15)
+#define VIDINTCON0_INTFRMEN		(1 << 12)
+#define VIDINTCON0_INTEN		(1 << 0)
+
+/* VIDINTCON1 */
+#define VIDINTCON1_INTFRMDONEPEND	(1 << 2)
+#define VIDINTCON1_INTFRMPEND		(1 << 1)
+#define VIDINTCON1_INTFIFOPEND		(1 << 0)
+
+/* DECON_CMU */
+#define CMU_CLKGAGE_MODE_SFR_F		(1 << 1)
+#define CMU_CLKGAGE_MODE_MEM_F		(1 << 0)
+
+/* DECON_UPDATE */
+#define STANDALONE_UPDATE_F		(1 << 0)
+
+/* DECON_VIDCON1 */
+#define VIDCON1_LINECNT_MASK		(0x0fff << 16)
+#define VIDCON1_I80_ACTIVE		(1 << 15)
+#define VIDCON1_VSTATUS_MASK		(0x3 << 13)
+#define VIDCON1_VSTATUS_VS		(0 << 13)
+#define VIDCON1_VSTATUS_BP		(1 << 13)
+#define VIDCON1_VSTATUS_AC		(2 << 13)
+#define VIDCON1_VSTATUS_FP		(3 << 13)
+#define VIDCON1_VCLK_MASK		(0x3 << 9)
+#define VIDCON1_VCLK_RUN_VDEN_DISABLE	(0x3 << 9)
+#define VIDCON1_VCLK_HOLD		(0x0 << 9)
+#define VIDCON1_VCLK_RUN		(0x1 << 9)
+
+
+/* DECON_VIDTCON00 */
+#define VIDTCON00_VBPD_F(x)		(((x) & 0xfff) << 16)
+#define VIDTCON00_VFPD_F(x)		((x) & 0xfff)
+
+/* DECON_VIDTCON01 */
+#define VIDTCON01_VSPW_F(x)		(((x) & 0xfff) << 16)
+
+/* DECON_VIDTCON10 */
+#define VIDTCON10_HBPD_F(x)		(((x) & 0xfff) << 16)
+#define VIDTCON10_HFPD_F(x)		((x) & 0xfff)
+
+/* DECON_VIDTCON11 */
+#define VIDTCON11_HSPW_F(x)		(((x) & 0xfff) << 16)
+
+/* DECON_VIDTCON2 */
+#define VIDTCON2_LINEVAL(x)		(((x) & 0xfff) << 16)
+#define VIDTCON2_HOZVAL(x)		((x) & 0xfff)
+
+/* TRIGCON */
+#define TRIGCON_TRIGEN_PER_F		(1 << 31)
+#define TRIGCON_TRIGEN_F		(1 << 30)
+#define TRIGCON_TE_AUTO_MASK		(1 << 29)
+#define TRIGCON_WB_SWTRIGCMD		(1 << 28)
+#define TRIGCON_SWTRIGCMD_W4BUF		(1 << 26)
+#define TRIGCON_TRIGMODE_W4BUF		(1 << 25)
+#define TRIGCON_SWTRIGCMD_W3BUF		(1 << 21)
+#define TRIGCON_TRIGMODE_W3BUF		(1 << 20)
+#define TRIGCON_SWTRIGCMD_W2BUF		(1 << 16)
+#define TRIGCON_TRIGMODE_W2BUF		(1 << 15)
+#define TRIGCON_SWTRIGCMD_W1BUF		(1 << 11)
+#define TRIGCON_TRIGMODE_W1BUF		(1 << 10)
+#define TRIGCON_SWTRIGCMD_W0BUF		(1 << 6)
+#define TRIGCON_TRIGMODE_W0BUF		(1 << 5)
+#define TRIGCON_HWTRIGMASK		(1 << 4)
+#define TRIGCON_HWTRIGEN		(1 << 3)
+#define TRIGCON_HWTRIG_INV		(1 << 2)
+#define TRIGCON_SWTRIGCMD		(1 << 1)
+#define TRIGCON_SWTRIGEN		(1 << 0)
+
+/* DECON_CRCCTRL */
+#define CRCCTRL_CRCCLKEN		(0x1 << 2)
+#define CRCCTRL_CRCSTART_F		(0x1 << 1)
+#define CRCCTRL_CRCEN			(0x1 << 0)
+#define CRCCTRL_MASK			(0x7)
+
+#endif /* EXYNOS_REGS_DECON_H */
diff --git a/drivers/gpu/drm/exynos/regs-decon7.h b/drivers/gpu/drm/exynos/regs-decon7.h
new file mode 100644
index 000000000000..339ea1007ff5
--- /dev/null
+++ b/drivers/gpu/drm/exynos/regs-decon7.h
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Ajay Kumar <ajaykumar.rs@samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/* VIDCON0 */
+#define VIDCON0					0x00
+
+#define VIDCON0_SWRESET				(1 << 28)
+#define VIDCON0_DECON_STOP_STATUS		(1 << 2)
+#define VIDCON0_ENVID				(1 << 1)
+#define VIDCON0_ENVID_F				(1 << 0)
+
+/* VIDOUTCON0 */
+#define VIDOUTCON0				0x4
+
+#define VIDOUTCON0_DUAL_MASK			(0x3 << 24)
+#define VIDOUTCON0_DUAL_ON			(0x3 << 24)
+#define VIDOUTCON0_DISP_IF_1_ON			(0x2 << 24)
+#define VIDOUTCON0_DISP_IF_0_ON			(0x1 << 24)
+#define VIDOUTCON0_DUAL_OFF			(0x0 << 24)
+#define VIDOUTCON0_IF_SHIFT			23
+#define VIDOUTCON0_IF_MASK			(0x1 << 23)
+#define VIDOUTCON0_RGBIF			(0x0 << 23)
+#define VIDOUTCON0_I80IF			(0x1 << 23)
+
+/* VIDCON3 */
+#define VIDCON3					0x8
+
+/* VIDCON4 */
+#define VIDCON4					0xC
+#define VIDCON4_FIFOCNT_START_EN		(1 << 0)
+
+/* VCLKCON0 */
+#define VCLKCON0				0x10
+#define VCLKCON0_CLKVALUP			(1 << 8)
+#define VCLKCON0_VCLKFREE			(1 << 0)
+
+/* VCLKCON */
+#define VCLKCON1				0x14
+#define VCLKCON1_CLKVAL_NUM_VCLK(val)		(((val) & 0xff) << 0)
+#define VCLKCON2				0x18
+
+/* SHADOWCON */
+#define SHADOWCON				0x30
+
+#define SHADOWCON_WINx_PROTECT(_win)		(1 << (10 + (_win)))
+
+/* WINCONx */
+#define WINCON(_win)				(0x50 + ((_win) * 4))
+
+#define WINCONx_BUFSTATUS			(0x3 << 30)
+#define WINCONx_BUFSEL_MASK			(0x3 << 28)
+#define WINCONx_BUFSEL_SHIFT			28
+#define WINCONx_TRIPLE_BUF_MODE			(0x1 << 18)
+#define WINCONx_DOUBLE_BUF_MODE			(0x0 << 18)
+#define WINCONx_BURSTLEN_16WORD			(0x0 << 11)
+#define WINCONx_BURSTLEN_8WORD			(0x1 << 11)
+#define WINCONx_BURSTLEN_MASK			(0x1 << 11)
+#define WINCONx_BURSTLEN_SHIFT			11
+#define WINCONx_BLD_PLANE			(0 << 8)
+#define WINCONx_BLD_PIX				(1 << 8)
+#define WINCONx_ALPHA_MUL			(1 << 7)
+
+#define WINCONx_BPPMODE_MASK			(0xf << 2)
+#define WINCONx_BPPMODE_SHIFT			2
+#define WINCONx_BPPMODE_16BPP_565		(0x8 << 2)
+#define WINCONx_BPPMODE_24BPP_BGRx		(0x7 << 2)
+#define WINCONx_BPPMODE_24BPP_RGBx		(0x6 << 2)
+#define WINCONx_BPPMODE_24BPP_xBGR		(0x5 << 2)
+#define WINCONx_BPPMODE_24BPP_xRGB		(0x4 << 2)
+#define WINCONx_BPPMODE_32BPP_BGRA		(0x3 << 2)
+#define WINCONx_BPPMODE_32BPP_RGBA		(0x2 << 2)
+#define WINCONx_BPPMODE_32BPP_ABGR		(0x1 << 2)
+#define WINCONx_BPPMODE_32BPP_ARGB		(0x0 << 2)
+#define WINCONx_ALPHA_SEL			(1 << 1)
+#define WINCONx_ENWIN				(1 << 0)
+
+#define WINCON1_ALPHA_MUL_F			(1 << 7)
+#define WINCON2_ALPHA_MUL_F			(1 << 7)
+#define WINCON3_ALPHA_MUL_F			(1 << 7)
+#define WINCON4_ALPHA_MUL_F			(1 << 7)
+
+/*  VIDOSDxH: The height for the OSD image(READ ONLY)*/
+#define VIDOSD_H(_x)				(0x80 + ((_x) * 4))
+
+/* Frame buffer start addresses: VIDWxxADD0n */
+#define VIDW_BUF_START(_win)			(0x80 + ((_win) * 0x10))
+#define VIDW_BUF_START1(_win)			(0x84 + ((_win) * 0x10))
+#define VIDW_BUF_START2(_win)			(0x88 + ((_win) * 0x10))
+
+#define VIDW_WHOLE_X(_win)			(0x0130 + ((_win) * 8))
+#define VIDW_WHOLE_Y(_win)			(0x0134 + ((_win) * 8))
+#define VIDW_OFFSET_X(_win)			(0x0170 + ((_win) * 8))
+#define VIDW_OFFSET_Y(_win)			(0x0174 + ((_win) * 8))
+#define VIDW_BLKOFFSET(_win)			(0x01B0 + ((_win) * 4))
+#define VIDW_BLKSIZE(win)			(0x0200 + ((_win) * 4))
+
+/* Interrupt controls register */
+#define VIDINTCON2				0x228
+
+#define VIDINTCON1_INTEXTRA1_EN			(1 << 1)
+#define VIDINTCON1_INTEXTRA0_EN			(1 << 0)
+
+/* Interrupt controls and status register */
+#define VIDINTCON3				0x22C
+
+#define VIDINTCON1_INTEXTRA1_PEND		(1 << 1)
+#define VIDINTCON1_INTEXTRA0_PEND		(1 << 0)
+
+/* VIDOSDxA ~ VIDOSDxE */
+#define VIDOSD_BASE				0x230
+
+#define OSD_STRIDE				0x20
+
+#define VIDOSD_A(_win)				(VIDOSD_BASE + \
+						((_win) * OSD_STRIDE) + 0x00)
+#define VIDOSD_B(_win)				(VIDOSD_BASE + \
+						((_win) * OSD_STRIDE) + 0x04)
+#define VIDOSD_C(_win)				(VIDOSD_BASE + \
+						((_win) * OSD_STRIDE) + 0x08)
+#define VIDOSD_D(_win)				(VIDOSD_BASE + \
+						((_win) * OSD_STRIDE) + 0x0C)
+#define VIDOSD_E(_win)				(VIDOSD_BASE + \
+						((_win) * OSD_STRIDE) + 0x10)
+
+#define VIDOSDxA_TOPLEFT_X_MASK			(0x1fff << 13)
+#define VIDOSDxA_TOPLEFT_X_SHIFT		13
+#define VIDOSDxA_TOPLEFT_X_LIMIT		0x1fff
+#define VIDOSDxA_TOPLEFT_X(_x)			(((_x) & 0x1fff) << 13)
+
+#define VIDOSDxA_TOPLEFT_Y_MASK			(0x1fff << 0)
+#define VIDOSDxA_TOPLEFT_Y_SHIFT		0
+#define VIDOSDxA_TOPLEFT_Y_LIMIT		0x1fff
+#define VIDOSDxA_TOPLEFT_Y(_x)			(((_x) & 0x1fff) << 0)
+
+#define VIDOSDxB_BOTRIGHT_X_MASK		(0x1fff << 13)
+#define VIDOSDxB_BOTRIGHT_X_SHIFT		13
+#define VIDOSDxB_BOTRIGHT_X_LIMIT		0x1fff
+#define VIDOSDxB_BOTRIGHT_X(_x)			(((_x) & 0x1fff) << 13)
+
+#define VIDOSDxB_BOTRIGHT_Y_MASK		(0x1fff << 0)
+#define VIDOSDxB_BOTRIGHT_Y_SHIFT		0
+#define VIDOSDxB_BOTRIGHT_Y_LIMIT		0x1fff
+#define VIDOSDxB_BOTRIGHT_Y(_x)			(((_x) & 0x1fff) << 0)
+
+#define VIDOSDxC_ALPHA0_R_F(_x)			(((_x) & 0xFF) << 16)
+#define VIDOSDxC_ALPHA0_G_F(_x)			(((_x) & 0xFF) << 8)
+#define VIDOSDxC_ALPHA0_B_F(_x)			(((_x) & 0xFF) << 0)
+
+#define VIDOSDxD_ALPHA1_R_F(_x)			(((_x) & 0xFF) << 16)
+#define VIDOSDxD_ALPHA1_G_F(_x)			(((_x) & 0xFF) << 8)
+#define VIDOSDxD_ALPHA1_B_F(_x)			(((_x) & 0xFF) >> 0)
+
+/* Window MAP (Color map) */
+#define WINxMAP(_win)				(0x340 + ((_win) * 4))
+
+#define WINxMAP_MAP				(1 << 24)
+#define WINxMAP_MAP_COLOUR_MASK			(0xffffff << 0)
+#define WINxMAP_MAP_COLOUR_SHIFT		0
+#define WINxMAP_MAP_COLOUR_LIMIT		0xffffff
+#define WINxMAP_MAP_COLOUR(_x)			((_x) << 0)
+
+/* Window colour-key control registers */
+#define WKEYCON					0x370
+
+#define WKEYCON0				0x00
+#define WKEYCON1				0x04
+#define WxKEYCON0_KEYBL_EN			(1 << 26)
+#define WxKEYCON0_KEYEN_F			(1 << 25)
+#define WxKEYCON0_DIRCON			(1 << 24)
+#define WxKEYCON0_COMPKEY_MASK			(0xffffff << 0)
+#define WxKEYCON0_COMPKEY_SHIFT			0
+#define WxKEYCON0_COMPKEY_LIMIT			0xffffff
+#define WxKEYCON0_COMPKEY(_x)			((_x) << 0)
+#define WxKEYCON1_COLVAL_MASK			(0xffffff << 0)
+#define WxKEYCON1_COLVAL_SHIFT			0
+#define WxKEYCON1_COLVAL_LIMIT			0xffffff
+#define WxKEYCON1_COLVAL(_x)			((_x) << 0)
+
+/* color key control register for hardware window 1 ~ 4. */
+#define WKEYCON0_BASE(x)		((WKEYCON + WKEYCON0) + ((x - 1) * 8))
+/* color key value register for hardware window 1 ~ 4. */
+#define WKEYCON1_BASE(x)		((WKEYCON + WKEYCON1) + ((x - 1) * 8))
+
+/* Window KEY Alpha value */
+#define WxKEYALPHA(_win)			(0x3A0 + (((_win) - 1) * 0x4))
+
+#define Wx_KEYALPHA_R_F_SHIFT			16
+#define Wx_KEYALPHA_G_F_SHIFT			8
+#define Wx_KEYALPHA_B_F_SHIFT			0
+
+/* Blending equation */
+#define BLENDE(_win)				(0x03C0 + ((_win) * 4))
+#define BLENDE_COEF_ZERO			0x0
+#define BLENDE_COEF_ONE				0x1
+#define BLENDE_COEF_ALPHA_A			0x2
+#define BLENDE_COEF_ONE_MINUS_ALPHA_A		0x3
+#define BLENDE_COEF_ALPHA_B			0x4
+#define BLENDE_COEF_ONE_MINUS_ALPHA_B		0x5
+#define BLENDE_COEF_ALPHA0			0x6
+#define BLENDE_COEF_A				0xA
+#define BLENDE_COEF_ONE_MINUS_A			0xB
+#define BLENDE_COEF_B				0xC
+#define BLENDE_COEF_ONE_MINUS_B			0xD
+#define BLENDE_Q_FUNC(_v)			((_v) << 18)
+#define BLENDE_P_FUNC(_v)			((_v) << 12)
+#define BLENDE_B_FUNC(_v)			((_v) << 6)
+#define BLENDE_A_FUNC(_v)			((_v) << 0)
+
+/* Blending equation control */
+#define BLENDCON				0x3D8
+#define BLENDCON_NEW_MASK			(1 << 0)
+#define BLENDCON_NEW_8BIT_ALPHA_VALUE		(1 << 0)
+#define BLENDCON_NEW_4BIT_ALPHA_VALUE		(0 << 0)
+
+/* Interrupt control register */
+#define VIDINTCON0				0x500
+
+#define VIDINTCON0_WAKEUP_MASK			(0x3f << 26)
+#define VIDINTCON0_INTEXTRAEN			(1 << 21)
+
+#define VIDINTCON0_FRAMESEL0_SHIFT		15
+#define VIDINTCON0_FRAMESEL0_MASK		(0x3 << 15)
+#define VIDINTCON0_FRAMESEL0_BACKPORCH		(0x0 << 15)
+#define VIDINTCON0_FRAMESEL0_VSYNC		(0x1 << 15)
+#define VIDINTCON0_FRAMESEL0_ACTIVE		(0x2 << 15)
+#define VIDINTCON0_FRAMESEL0_FRONTPORCH		(0x3 << 15)
+
+#define VIDINTCON0_INT_FRAME			(1 << 11)
+
+#define VIDINTCON0_FIFOLEVEL_MASK		(0x7 << 3)
+#define VIDINTCON0_FIFOLEVEL_SHIFT		3
+#define VIDINTCON0_FIFOLEVEL_EMPTY		(0x0 << 3)
+#define VIDINTCON0_FIFOLEVEL_TO25PC		(0x1 << 3)
+#define VIDINTCON0_FIFOLEVEL_TO50PC		(0x2 << 3)
+#define VIDINTCON0_FIFOLEVEL_FULL		(0x4 << 3)
+
+#define VIDINTCON0_FIFOSEL_MAIN_EN		(1 << 1)
+#define VIDINTCON0_INT_FIFO			(1 << 1)
+
+#define VIDINTCON0_INT_ENABLE			(1 << 0)
+
+/* Interrupt controls and status register */
+#define VIDINTCON1				0x504
+
+#define VIDINTCON1_INT_EXTRA			(1 << 3)
+#define VIDINTCON1_INT_I80			(1 << 2)
+#define VIDINTCON1_INT_FRAME			(1 << 1)
+#define VIDINTCON1_INT_FIFO			(1 << 0)
+
+/* VIDCON1 */
+#define VIDCON1(_x)				(0x0600 + ((_x) * 0x50))
+#define VIDCON1_LINECNT_GET(_v)			(((_v) >> 17) & 0x1fff)
+#define VIDCON1_VCLK_MASK			(0x3 << 9)
+#define VIDCON1_VCLK_HOLD			(0x0 << 9)
+#define VIDCON1_VCLK_RUN			(0x1 << 9)
+#define VIDCON1_VCLK_RUN_VDEN_DISABLE		(0x3 << 9)
+#define VIDCON1_RGB_ORDER_O_MASK		(0x7 << 4)
+#define VIDCON1_RGB_ORDER_O_RGB			(0x0 << 4)
+#define VIDCON1_RGB_ORDER_O_GBR			(0x1 << 4)
+#define VIDCON1_RGB_ORDER_O_BRG			(0x2 << 4)
+#define VIDCON1_RGB_ORDER_O_BGR			(0x4 << 4)
+#define VIDCON1_RGB_ORDER_O_RBG			(0x5 << 4)
+#define VIDCON1_RGB_ORDER_O_GRB			(0x6 << 4)
+
+/* VIDTCON0 */
+#define VIDTCON0				0x610
+
+#define VIDTCON0_VBPD_MASK			(0xffff << 16)
+#define VIDTCON0_VBPD_SHIFT			16
+#define VIDTCON0_VBPD_LIMIT			0xffff
+#define VIDTCON0_VBPD(_x)			((_x) << 16)
+
+#define VIDTCON0_VFPD_MASK			(0xffff << 0)
+#define VIDTCON0_VFPD_SHIFT			0
+#define VIDTCON0_VFPD_LIMIT			0xffff
+#define VIDTCON0_VFPD(_x)			((_x) << 0)
+
+/* VIDTCON1 */
+#define VIDTCON1				0x614
+
+#define VIDTCON1_VSPW_MASK			(0xffff << 16)
+#define VIDTCON1_VSPW_SHIFT			16
+#define VIDTCON1_VSPW_LIMIT			0xffff
+#define VIDTCON1_VSPW(_x)			((_x) << 16)
+
+/* VIDTCON2 */
+#define VIDTCON2				0x618
+
+#define VIDTCON2_HBPD_MASK			(0xffff << 16)
+#define VIDTCON2_HBPD_SHIFT			16
+#define VIDTCON2_HBPD_LIMIT			0xffff
+#define VIDTCON2_HBPD(_x)			((_x) << 16)
+
+#define VIDTCON2_HFPD_MASK			(0xffff << 0)
+#define VIDTCON2_HFPD_SHIFT			0
+#define VIDTCON2_HFPD_LIMIT			0xffff
+#define VIDTCON2_HFPD(_x)			((_x) << 0)
+
+/* VIDTCON3 */
+#define VIDTCON3				0x61C
+
+#define VIDTCON3_HSPW_MASK			(0xffff << 16)
+#define VIDTCON3_HSPW_SHIFT			16
+#define VIDTCON3_HSPW_LIMIT			0xffff
+#define VIDTCON3_HSPW(_x)			((_x) << 16)
+
+/* VIDTCON4 */
+#define VIDTCON4				0x620
+
+#define VIDTCON4_LINEVAL_MASK			(0xfff << 16)
+#define VIDTCON4_LINEVAL_SHIFT			16
+#define VIDTCON4_LINEVAL_LIMIT			0xfff
+#define VIDTCON4_LINEVAL(_x)			(((_x) & 0xfff) << 16)
+
+#define VIDTCON4_HOZVAL_MASK			(0xfff << 0)
+#define VIDTCON4_HOZVAL_SHIFT			0
+#define VIDTCON4_HOZVAL_LIMIT			0xfff
+#define VIDTCON4_HOZVAL(_x)			(((_x) & 0xfff) << 0)
+
+/* LINECNT OP THRSHOLD*/
+#define LINECNT_OP_THRESHOLD			0x630
+
+/* CRCCTRL */
+#define CRCCTRL					0x6C8
+#define CRCCTRL_CRCCLKEN			(0x1 << 2)
+#define CRCCTRL_CRCSTART_F			(0x1 << 1)
+#define CRCCTRL_CRCEN				(0x1 << 0)
+
+/* DECON_CMU */
+#define DECON_CMU				0x704
+
+#define DECON_CMU_ALL_CLKGATE_ENABLE		0x3
+#define DECON_CMU_SE_CLKGATE_ENABLE		(0x1 << 2)
+#define DECON_CMU_SFR_CLKGATE_ENABLE		(0x1 << 1)
+#define DECON_CMU_MEM_CLKGATE_ENABLE		(0x1 << 0)
+
+/* DECON_UPDATE */
+#define DECON_UPDATE				0x710
+
+#define DECON_UPDATE_SLAVE_SYNC			(1 << 4)
+#define DECON_UPDATE_STANDALONE_F		(1 << 0)
diff --git a/include/video/exynos5433_decon.h b/include/video/exynos5433_decon.h
deleted file mode 100644
index 78957c9626f5..000000000000
--- a/include/video/exynos5433_decon.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * Copyright (C) 2014 Samsung Electronics Co.Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundationr
- */
-
-#ifndef EXYNOS_REGS_DECON_H
-#define EXYNOS_REGS_DECON_H
-
-/* Exynos543X DECON */
-#define DECON_VIDCON0			0x0000
-#define DECON_VIDOUTCON0		0x0010
-#define DECON_WINCONx(n)		(0x0020 + ((n) * 4))
-#define DECON_VIDOSDxH(n)		(0x0080 + ((n) * 4))
-#define DECON_SHADOWCON			0x00A0
-#define DECON_VIDOSDxA(n)		(0x00B0 + ((n) * 0x20))
-#define DECON_VIDOSDxB(n)		(0x00B4 + ((n) * 0x20))
-#define DECON_VIDOSDxC(n)		(0x00B8 + ((n) * 0x20))
-#define DECON_VIDOSDxD(n)		(0x00BC + ((n) * 0x20))
-#define DECON_VIDOSDxE(n)		(0x00C0 + ((n) * 0x20))
-#define DECON_VIDW0xADD0B0(n)		(0x0150 + ((n) * 0x10))
-#define DECON_VIDW0xADD0B1(n)		(0x0154 + ((n) * 0x10))
-#define DECON_VIDW0xADD0B2(n)		(0x0158 + ((n) * 0x10))
-#define DECON_VIDW0xADD1B0(n)		(0x01A0 + ((n) * 0x10))
-#define DECON_VIDW0xADD1B1(n)		(0x01A4 + ((n) * 0x10))
-#define DECON_VIDW0xADD1B2(n)		(0x01A8 + ((n) * 0x10))
-#define DECON_VIDW0xADD2(n)		(0x0200 + ((n) * 4))
-#define DECON_LOCALxSIZE(n)		(0x0214 + ((n) * 4))
-#define DECON_VIDINTCON0		0x0220
-#define DECON_VIDINTCON1		0x0224
-#define DECON_WxKEYCON0(n)		(0x0230 + ((n - 1) * 8))
-#define DECON_WxKEYCON1(n)		(0x0234 + ((n - 1) * 8))
-#define DECON_WxKEYALPHA(n)		(0x0250 + ((n - 1) * 4))
-#define DECON_WINxMAP(n)		(0x0270 + ((n) * 4))
-#define DECON_QOSLUT07_00		0x02C0
-#define DECON_QOSLUT15_08		0x02C4
-#define DECON_QOSCTRL			0x02C8
-#define DECON_BLENDERQx(n)		(0x0300 + ((n - 1) * 4))
-#define DECON_BLENDCON			0x0310
-#define DECON_OPE_VIDW0xADD0(n)		(0x0400 + ((n) * 4))
-#define DECON_OPE_VIDW0xADD1(n)		(0x0414 + ((n) * 4))
-#define DECON_FRAMEFIFO_REG7		0x051C
-#define DECON_FRAMEFIFO_REG8		0x0520
-#define DECON_FRAMEFIFO_STATUS		0x0524
-#define DECON_CMU			0x1404
-#define DECON_UPDATE			0x1410
-#define DECON_CRFMID			0x1414
-#define DECON_UPDATE_SCHEME		0x1438
-#define DECON_VIDCON1			0x2000
-#define DECON_VIDCON2			0x2004
-#define DECON_VIDCON3			0x2008
-#define DECON_VIDCON4			0x200C
-#define DECON_VIDTCON2			0x2028
-#define DECON_FRAME_SIZE		0x2038
-#define DECON_LINECNT_OP_THRESHOLD	0x203C
-#define DECON_TRIGCON			0x2040
-#define DECON_TRIGSKIP			0x2050
-#define DECON_CRCRDATA			0x20B0
-#define DECON_CRCCTRL			0x20B4
-
-/* Exynos5430 DECON */
-#define DECON_VIDTCON0			0x2020
-#define DECON_VIDTCON1			0x2024
-
-/* Exynos5433 DECON */
-#define DECON_VIDTCON00			0x2010
-#define DECON_VIDTCON01			0x2014
-#define DECON_VIDTCON10			0x2018
-#define DECON_VIDTCON11			0x201C
-
-/* Exynos543X DECON Internal */
-#define DECON_W013DSTREOCON		0x0320
-#define DECON_W233DSTREOCON		0x0324
-#define DECON_FRAMEFIFO_REG0		0x0500
-#define DECON_ENHANCER_CTRL		0x2100
-
-/* Exynos543X DECON TV */
-#define DECON_VCLKCON0			0x0014
-#define DECON_VIDINTCON2		0x0228
-#define DECON_VIDINTCON3		0x022C
-
-/* VIDCON0 */
-#define VIDCON0_SWRESET			(1 << 28)
-#define VIDCON0_CLKVALUP		(1 << 14)
-#define VIDCON0_VLCKFREE		(1 << 5)
-#define VIDCON0_STOP_STATUS		(1 << 2)
-#define VIDCON0_ENVID			(1 << 1)
-#define VIDCON0_ENVID_F			(1 << 0)
-
-/* VIDOUTCON0 */
-#define VIDOUT_INTERLACE_FIELD_F	(1 << 29)
-#define VIDOUT_INTERLACE_EN_F		(1 << 28)
-#define VIDOUT_LCD_ON			(1 << 24)
-#define VIDOUT_IF_F_MASK		(0x3 << 20)
-#define VIDOUT_RGB_IF			(0x0 << 20)
-#define VIDOUT_COMMAND_IF		(0x2 << 20)
-
-/* WINCONx */
-#define WINCONx_HAWSWP_F		(1 << 16)
-#define WINCONx_WSWP_F			(1 << 15)
-#define WINCONx_BURSTLEN_MASK		(0x3 << 10)
-#define WINCONx_BURSTLEN_16WORD		(0x0 << 10)
-#define WINCONx_BURSTLEN_8WORD		(0x1 << 10)
-#define WINCONx_BURSTLEN_4WORD		(0x2 << 10)
-#define WINCONx_BLD_PIX_F		(1 << 6)
-#define WINCONx_BPPMODE_MASK		(0xf << 2)
-#define WINCONx_BPPMODE_16BPP_565	(0x5 << 2)
-#define WINCONx_BPPMODE_16BPP_A1555	(0x6 << 2)
-#define WINCONx_BPPMODE_16BPP_I1555	(0x7 << 2)
-#define WINCONx_BPPMODE_24BPP_888	(0xb << 2)
-#define WINCONx_BPPMODE_24BPP_A1887	(0xc << 2)
-#define WINCONx_BPPMODE_25BPP_A1888	(0xd << 2)
-#define WINCONx_BPPMODE_32BPP_A8888	(0xd << 2)
-#define WINCONx_BPPMODE_16BPP_A4444	(0xe << 2)
-#define WINCONx_ALPHA_SEL_F		(1 << 1)
-#define WINCONx_ENWIN_F			(1 << 0)
-
-/* SHADOWCON */
-#define SHADOWCON_PROTECT_MASK		GENMASK(14, 10)
-#define SHADOWCON_Wx_PROTECT(n)		(1 << (10 + (n)))
-
-/* VIDOSDxD */
-#define VIDOSD_Wx_ALPHA_R_F(n)		(((n) & 0xff) << 16)
-#define VIDOSD_Wx_ALPHA_G_F(n)		(((n) & 0xff) << 8)
-#define VIDOSD_Wx_ALPHA_B_F(n)		(((n) & 0xff) << 0)
-
-/* VIDINTCON0 */
-#define VIDINTCON0_FRAMEDONE		(1 << 17)
-#define VIDINTCON0_FRAMESEL_BP		(0 << 15)
-#define VIDINTCON0_FRAMESEL_VS		(1 << 15)
-#define VIDINTCON0_FRAMESEL_AC		(2 << 15)
-#define VIDINTCON0_FRAMESEL_FP		(3 << 15)
-#define VIDINTCON0_INTFRMEN		(1 << 12)
-#define VIDINTCON0_INTEN		(1 << 0)
-
-/* VIDINTCON1 */
-#define VIDINTCON1_INTFRMDONEPEND	(1 << 2)
-#define VIDINTCON1_INTFRMPEND		(1 << 1)
-#define VIDINTCON1_INTFIFOPEND		(1 << 0)
-
-/* DECON_CMU */
-#define CMU_CLKGAGE_MODE_SFR_F		(1 << 1)
-#define CMU_CLKGAGE_MODE_MEM_F		(1 << 0)
-
-/* DECON_UPDATE */
-#define STANDALONE_UPDATE_F		(1 << 0)
-
-/* DECON_VIDCON1 */
-#define VIDCON1_LINECNT_MASK		(0x0fff << 16)
-#define VIDCON1_I80_ACTIVE		(1 << 15)
-#define VIDCON1_VSTATUS_MASK		(0x3 << 13)
-#define VIDCON1_VSTATUS_VS		(0 << 13)
-#define VIDCON1_VSTATUS_BP		(1 << 13)
-#define VIDCON1_VSTATUS_AC		(2 << 13)
-#define VIDCON1_VSTATUS_FP		(3 << 13)
-#define VIDCON1_VCLK_MASK		(0x3 << 9)
-#define VIDCON1_VCLK_RUN_VDEN_DISABLE	(0x3 << 9)
-#define VIDCON1_VCLK_HOLD		(0x0 << 9)
-#define VIDCON1_VCLK_RUN		(0x1 << 9)
-
-
-/* DECON_VIDTCON00 */
-#define VIDTCON00_VBPD_F(x)		(((x) & 0xfff) << 16)
-#define VIDTCON00_VFPD_F(x)		((x) & 0xfff)
-
-/* DECON_VIDTCON01 */
-#define VIDTCON01_VSPW_F(x)		(((x) & 0xfff) << 16)
-
-/* DECON_VIDTCON10 */
-#define VIDTCON10_HBPD_F(x)		(((x) & 0xfff) << 16)
-#define VIDTCON10_HFPD_F(x)		((x) & 0xfff)
-
-/* DECON_VIDTCON11 */
-#define VIDTCON11_HSPW_F(x)		(((x) & 0xfff) << 16)
-
-/* DECON_VIDTCON2 */
-#define VIDTCON2_LINEVAL(x)		(((x) & 0xfff) << 16)
-#define VIDTCON2_HOZVAL(x)		((x) & 0xfff)
-
-/* TRIGCON */
-#define TRIGCON_TRIGEN_PER_F		(1 << 31)
-#define TRIGCON_TRIGEN_F		(1 << 30)
-#define TRIGCON_TE_AUTO_MASK		(1 << 29)
-#define TRIGCON_WB_SWTRIGCMD		(1 << 28)
-#define TRIGCON_SWTRIGCMD_W4BUF		(1 << 26)
-#define TRIGCON_TRIGMODE_W4BUF		(1 << 25)
-#define TRIGCON_SWTRIGCMD_W3BUF		(1 << 21)
-#define TRIGCON_TRIGMODE_W3BUF		(1 << 20)
-#define TRIGCON_SWTRIGCMD_W2BUF		(1 << 16)
-#define TRIGCON_TRIGMODE_W2BUF		(1 << 15)
-#define TRIGCON_SWTRIGCMD_W1BUF		(1 << 11)
-#define TRIGCON_TRIGMODE_W1BUF		(1 << 10)
-#define TRIGCON_SWTRIGCMD_W0BUF		(1 << 6)
-#define TRIGCON_TRIGMODE_W0BUF		(1 << 5)
-#define TRIGCON_HWTRIGMASK		(1 << 4)
-#define TRIGCON_HWTRIGEN		(1 << 3)
-#define TRIGCON_HWTRIG_INV		(1 << 2)
-#define TRIGCON_SWTRIGCMD		(1 << 1)
-#define TRIGCON_SWTRIGEN		(1 << 0)
-
-/* DECON_CRCCTRL */
-#define CRCCTRL_CRCCLKEN		(0x1 << 2)
-#define CRCCTRL_CRCSTART_F		(0x1 << 1)
-#define CRCCTRL_CRCEN			(0x1 << 0)
-#define CRCCTRL_MASK			(0x7)
-
-#endif /* EXYNOS_REGS_DECON_H */
diff --git a/include/video/exynos7_decon.h b/include/video/exynos7_decon.h
deleted file mode 100644
index a62b11b613f6..000000000000
--- a/include/video/exynos7_decon.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/* include/video/exynos7_decon.h
- *
- * Copyright (c) 2014 Samsung Electronics Co., Ltd.
- * Author: Ajay Kumar <ajaykumar.rs@samsung.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-/* VIDCON0 */
-#define VIDCON0					0x00
-
-#define VIDCON0_SWRESET				(1 << 28)
-#define VIDCON0_DECON_STOP_STATUS		(1 << 2)
-#define VIDCON0_ENVID				(1 << 1)
-#define VIDCON0_ENVID_F				(1 << 0)
-
-/* VIDOUTCON0 */
-#define VIDOUTCON0				0x4
-
-#define VIDOUTCON0_DUAL_MASK			(0x3 << 24)
-#define VIDOUTCON0_DUAL_ON			(0x3 << 24)
-#define VIDOUTCON0_DISP_IF_1_ON			(0x2 << 24)
-#define VIDOUTCON0_DISP_IF_0_ON			(0x1 << 24)
-#define VIDOUTCON0_DUAL_OFF			(0x0 << 24)
-#define VIDOUTCON0_IF_SHIFT			23
-#define VIDOUTCON0_IF_MASK			(0x1 << 23)
-#define VIDOUTCON0_RGBIF			(0x0 << 23)
-#define VIDOUTCON0_I80IF			(0x1 << 23)
-
-/* VIDCON3 */
-#define VIDCON3					0x8
-
-/* VIDCON4 */
-#define VIDCON4					0xC
-#define VIDCON4_FIFOCNT_START_EN		(1 << 0)
-
-/* VCLKCON0 */
-#define VCLKCON0				0x10
-#define VCLKCON0_CLKVALUP			(1 << 8)
-#define VCLKCON0_VCLKFREE			(1 << 0)
-
-/* VCLKCON */
-#define VCLKCON1				0x14
-#define VCLKCON1_CLKVAL_NUM_VCLK(val)		(((val) & 0xff) << 0)
-#define VCLKCON2				0x18
-
-/* SHADOWCON */
-#define SHADOWCON				0x30
-
-#define SHADOWCON_WINx_PROTECT(_win)		(1 << (10 + (_win)))
-
-/* WINCONx */
-#define WINCON(_win)				(0x50 + ((_win) * 4))
-
-#define WINCONx_BUFSTATUS			(0x3 << 30)
-#define WINCONx_BUFSEL_MASK			(0x3 << 28)
-#define WINCONx_BUFSEL_SHIFT			28
-#define WINCONx_TRIPLE_BUF_MODE			(0x1 << 18)
-#define WINCONx_DOUBLE_BUF_MODE			(0x0 << 18)
-#define WINCONx_BURSTLEN_16WORD			(0x0 << 11)
-#define WINCONx_BURSTLEN_8WORD			(0x1 << 11)
-#define WINCONx_BURSTLEN_MASK			(0x1 << 11)
-#define WINCONx_BURSTLEN_SHIFT			11
-#define WINCONx_BLD_PLANE			(0 << 8)
-#define WINCONx_BLD_PIX				(1 << 8)
-#define WINCONx_ALPHA_MUL			(1 << 7)
-
-#define WINCONx_BPPMODE_MASK			(0xf << 2)
-#define WINCONx_BPPMODE_SHIFT			2
-#define WINCONx_BPPMODE_16BPP_565		(0x8 << 2)
-#define WINCONx_BPPMODE_24BPP_BGRx		(0x7 << 2)
-#define WINCONx_BPPMODE_24BPP_RGBx		(0x6 << 2)
-#define WINCONx_BPPMODE_24BPP_xBGR		(0x5 << 2)
-#define WINCONx_BPPMODE_24BPP_xRGB		(0x4 << 2)
-#define WINCONx_BPPMODE_32BPP_BGRA		(0x3 << 2)
-#define WINCONx_BPPMODE_32BPP_RGBA		(0x2 << 2)
-#define WINCONx_BPPMODE_32BPP_ABGR		(0x1 << 2)
-#define WINCONx_BPPMODE_32BPP_ARGB		(0x0 << 2)
-#define WINCONx_ALPHA_SEL			(1 << 1)
-#define WINCONx_ENWIN				(1 << 0)
-
-#define WINCON1_ALPHA_MUL_F			(1 << 7)
-#define WINCON2_ALPHA_MUL_F			(1 << 7)
-#define WINCON3_ALPHA_MUL_F			(1 << 7)
-#define WINCON4_ALPHA_MUL_F			(1 << 7)
-
-/*  VIDOSDxH: The height for the OSD image(READ ONLY)*/
-#define VIDOSD_H(_x)				(0x80 + ((_x) * 4))
-
-/* Frame buffer start addresses: VIDWxxADD0n */
-#define VIDW_BUF_START(_win)			(0x80 + ((_win) * 0x10))
-#define VIDW_BUF_START1(_win)			(0x84 + ((_win) * 0x10))
-#define VIDW_BUF_START2(_win)			(0x88 + ((_win) * 0x10))
-
-#define VIDW_WHOLE_X(_win)			(0x0130 + ((_win) * 8))
-#define VIDW_WHOLE_Y(_win)			(0x0134 + ((_win) * 8))
-#define VIDW_OFFSET_X(_win)			(0x0170 + ((_win) * 8))
-#define VIDW_OFFSET_Y(_win)			(0x0174 + ((_win) * 8))
-#define VIDW_BLKOFFSET(_win)			(0x01B0 + ((_win) * 4))
-#define VIDW_BLKSIZE(win)			(0x0200 + ((_win) * 4))
-
-/* Interrupt controls register */
-#define VIDINTCON2				0x228
-
-#define VIDINTCON1_INTEXTRA1_EN			(1 << 1)
-#define VIDINTCON1_INTEXTRA0_EN			(1 << 0)
-
-/* Interrupt controls and status register */
-#define VIDINTCON3				0x22C
-
-#define VIDINTCON1_INTEXTRA1_PEND		(1 << 1)
-#define VIDINTCON1_INTEXTRA0_PEND		(1 << 0)
-
-/* VIDOSDxA ~ VIDOSDxE */
-#define VIDOSD_BASE				0x230
-
-#define OSD_STRIDE				0x20
-
-#define VIDOSD_A(_win)				(VIDOSD_BASE + \
-						((_win) * OSD_STRIDE) + 0x00)
-#define VIDOSD_B(_win)				(VIDOSD_BASE + \
-						((_win) * OSD_STRIDE) + 0x04)
-#define VIDOSD_C(_win)				(VIDOSD_BASE + \
-						((_win) * OSD_STRIDE) + 0x08)
-#define VIDOSD_D(_win)				(VIDOSD_BASE + \
-						((_win) * OSD_STRIDE) + 0x0C)
-#define VIDOSD_E(_win)				(VIDOSD_BASE + \
-						((_win) * OSD_STRIDE) + 0x10)
-
-#define VIDOSDxA_TOPLEFT_X_MASK			(0x1fff << 13)
-#define VIDOSDxA_TOPLEFT_X_SHIFT		13
-#define VIDOSDxA_TOPLEFT_X_LIMIT		0x1fff
-#define VIDOSDxA_TOPLEFT_X(_x)			(((_x) & 0x1fff) << 13)
-
-#define VIDOSDxA_TOPLEFT_Y_MASK			(0x1fff << 0)
-#define VIDOSDxA_TOPLEFT_Y_SHIFT		0
-#define VIDOSDxA_TOPLEFT_Y_LIMIT		0x1fff
-#define VIDOSDxA_TOPLEFT_Y(_x)			(((_x) & 0x1fff) << 0)
-
-#define VIDOSDxB_BOTRIGHT_X_MASK		(0x1fff << 13)
-#define VIDOSDxB_BOTRIGHT_X_SHIFT		13
-#define VIDOSDxB_BOTRIGHT_X_LIMIT		0x1fff
-#define VIDOSDxB_BOTRIGHT_X(_x)			(((_x) & 0x1fff) << 13)
-
-#define VIDOSDxB_BOTRIGHT_Y_MASK		(0x1fff << 0)
-#define VIDOSDxB_BOTRIGHT_Y_SHIFT		0
-#define VIDOSDxB_BOTRIGHT_Y_LIMIT		0x1fff
-#define VIDOSDxB_BOTRIGHT_Y(_x)			(((_x) & 0x1fff) << 0)
-
-#define VIDOSDxC_ALPHA0_R_F(_x)			(((_x) & 0xFF) << 16)
-#define VIDOSDxC_ALPHA0_G_F(_x)			(((_x) & 0xFF) << 8)
-#define VIDOSDxC_ALPHA0_B_F(_x)			(((_x) & 0xFF) << 0)
-
-#define VIDOSDxD_ALPHA1_R_F(_x)			(((_x) & 0xFF) << 16)
-#define VIDOSDxD_ALPHA1_G_F(_x)			(((_x) & 0xFF) << 8)
-#define VIDOSDxD_ALPHA1_B_F(_x)			(((_x) & 0xFF) >> 0)
-
-/* Window MAP (Color map) */
-#define WINxMAP(_win)				(0x340 + ((_win) * 4))
-
-#define WINxMAP_MAP				(1 << 24)
-#define WINxMAP_MAP_COLOUR_MASK			(0xffffff << 0)
-#define WINxMAP_MAP_COLOUR_SHIFT		0
-#define WINxMAP_MAP_COLOUR_LIMIT		0xffffff
-#define WINxMAP_MAP_COLOUR(_x)			((_x) << 0)
-
-/* Window colour-key control registers */
-#define WKEYCON					0x370
-
-#define WKEYCON0				0x00
-#define WKEYCON1				0x04
-#define WxKEYCON0_KEYBL_EN			(1 << 26)
-#define WxKEYCON0_KEYEN_F			(1 << 25)
-#define WxKEYCON0_DIRCON			(1 << 24)
-#define WxKEYCON0_COMPKEY_MASK			(0xffffff << 0)
-#define WxKEYCON0_COMPKEY_SHIFT			0
-#define WxKEYCON0_COMPKEY_LIMIT			0xffffff
-#define WxKEYCON0_COMPKEY(_x)			((_x) << 0)
-#define WxKEYCON1_COLVAL_MASK			(0xffffff << 0)
-#define WxKEYCON1_COLVAL_SHIFT			0
-#define WxKEYCON1_COLVAL_LIMIT			0xffffff
-#define WxKEYCON1_COLVAL(_x)			((_x) << 0)
-
-/* color key control register for hardware window 1 ~ 4. */
-#define WKEYCON0_BASE(x)		((WKEYCON + WKEYCON0) + ((x - 1) * 8))
-/* color key value register for hardware window 1 ~ 4. */
-#define WKEYCON1_BASE(x)		((WKEYCON + WKEYCON1) + ((x - 1) * 8))
-
-/* Window KEY Alpha value */
-#define WxKEYALPHA(_win)			(0x3A0 + (((_win) - 1) * 0x4))
-
-#define Wx_KEYALPHA_R_F_SHIFT			16
-#define Wx_KEYALPHA_G_F_SHIFT			8
-#define Wx_KEYALPHA_B_F_SHIFT			0
-
-/* Blending equation */
-#define BLENDE(_win)				(0x03C0 + ((_win) * 4))
-#define BLENDE_COEF_ZERO			0x0
-#define BLENDE_COEF_ONE				0x1
-#define BLENDE_COEF_ALPHA_A			0x2
-#define BLENDE_COEF_ONE_MINUS_ALPHA_A		0x3
-#define BLENDE_COEF_ALPHA_B			0x4
-#define BLENDE_COEF_ONE_MINUS_ALPHA_B		0x5
-#define BLENDE_COEF_ALPHA0			0x6
-#define BLENDE_COEF_A				0xA
-#define BLENDE_COEF_ONE_MINUS_A			0xB
-#define BLENDE_COEF_B				0xC
-#define BLENDE_COEF_ONE_MINUS_B			0xD
-#define BLENDE_Q_FUNC(_v)			((_v) << 18)
-#define BLENDE_P_FUNC(_v)			((_v) << 12)
-#define BLENDE_B_FUNC(_v)			((_v) << 6)
-#define BLENDE_A_FUNC(_v)			((_v) << 0)
-
-/* Blending equation control */
-#define BLENDCON				0x3D8
-#define BLENDCON_NEW_MASK			(1 << 0)
-#define BLENDCON_NEW_8BIT_ALPHA_VALUE		(1 << 0)
-#define BLENDCON_NEW_4BIT_ALPHA_VALUE		(0 << 0)
-
-/* Interrupt control register */
-#define VIDINTCON0				0x500
-
-#define VIDINTCON0_WAKEUP_MASK			(0x3f << 26)
-#define VIDINTCON0_INTEXTRAEN			(1 << 21)
-
-#define VIDINTCON0_FRAMESEL0_SHIFT		15
-#define VIDINTCON0_FRAMESEL0_MASK		(0x3 << 15)
-#define VIDINTCON0_FRAMESEL0_BACKPORCH		(0x0 << 15)
-#define VIDINTCON0_FRAMESEL0_VSYNC		(0x1 << 15)
-#define VIDINTCON0_FRAMESEL0_ACTIVE		(0x2 << 15)
-#define VIDINTCON0_FRAMESEL0_FRONTPORCH		(0x3 << 15)
-
-#define VIDINTCON0_INT_FRAME			(1 << 11)
-
-#define VIDINTCON0_FIFOLEVEL_MASK		(0x7 << 3)
-#define VIDINTCON0_FIFOLEVEL_SHIFT		3
-#define VIDINTCON0_FIFOLEVEL_EMPTY		(0x0 << 3)
-#define VIDINTCON0_FIFOLEVEL_TO25PC		(0x1 << 3)
-#define VIDINTCON0_FIFOLEVEL_TO50PC		(0x2 << 3)
-#define VIDINTCON0_FIFOLEVEL_FULL		(0x4 << 3)
-
-#define VIDINTCON0_FIFOSEL_MAIN_EN		(1 << 1)
-#define VIDINTCON0_INT_FIFO			(1 << 1)
-
-#define VIDINTCON0_INT_ENABLE			(1 << 0)
-
-/* Interrupt controls and status register */
-#define VIDINTCON1				0x504
-
-#define VIDINTCON1_INT_EXTRA			(1 << 3)
-#define VIDINTCON1_INT_I80			(1 << 2)
-#define VIDINTCON1_INT_FRAME			(1 << 1)
-#define VIDINTCON1_INT_FIFO			(1 << 0)
-
-/* VIDCON1 */
-#define VIDCON1(_x)				(0x0600 + ((_x) * 0x50))
-#define VIDCON1_LINECNT_GET(_v)			(((_v) >> 17) & 0x1fff)
-#define VIDCON1_VCLK_MASK			(0x3 << 9)
-#define VIDCON1_VCLK_HOLD			(0x0 << 9)
-#define VIDCON1_VCLK_RUN			(0x1 << 9)
-#define VIDCON1_VCLK_RUN_VDEN_DISABLE		(0x3 << 9)
-#define VIDCON1_RGB_ORDER_O_MASK		(0x7 << 4)
-#define VIDCON1_RGB_ORDER_O_RGB			(0x0 << 4)
-#define VIDCON1_RGB_ORDER_O_GBR			(0x1 << 4)
-#define VIDCON1_RGB_ORDER_O_BRG			(0x2 << 4)
-#define VIDCON1_RGB_ORDER_O_BGR			(0x4 << 4)
-#define VIDCON1_RGB_ORDER_O_RBG			(0x5 << 4)
-#define VIDCON1_RGB_ORDER_O_GRB			(0x6 << 4)
-
-/* VIDTCON0 */
-#define VIDTCON0				0x610
-
-#define VIDTCON0_VBPD_MASK			(0xffff << 16)
-#define VIDTCON0_VBPD_SHIFT			16
-#define VIDTCON0_VBPD_LIMIT			0xffff
-#define VIDTCON0_VBPD(_x)			((_x) << 16)
-
-#define VIDTCON0_VFPD_MASK			(0xffff << 0)
-#define VIDTCON0_VFPD_SHIFT			0
-#define VIDTCON0_VFPD_LIMIT			0xffff
-#define VIDTCON0_VFPD(_x)			((_x) << 0)
-
-/* VIDTCON1 */
-#define VIDTCON1				0x614
-
-#define VIDTCON1_VSPW_MASK			(0xffff << 16)
-#define VIDTCON1_VSPW_SHIFT			16
-#define VIDTCON1_VSPW_LIMIT			0xffff
-#define VIDTCON1_VSPW(_x)			((_x) << 16)
-
-/* VIDTCON2 */
-#define VIDTCON2				0x618
-
-#define VIDTCON2_HBPD_MASK			(0xffff << 16)
-#define VIDTCON2_HBPD_SHIFT			16
-#define VIDTCON2_HBPD_LIMIT			0xffff
-#define VIDTCON2_HBPD(_x)			((_x) << 16)
-
-#define VIDTCON2_HFPD_MASK			(0xffff << 0)
-#define VIDTCON2_HFPD_SHIFT			0
-#define VIDTCON2_HFPD_LIMIT			0xffff
-#define VIDTCON2_HFPD(_x)			((_x) << 0)
-
-/* VIDTCON3 */
-#define VIDTCON3				0x61C
-
-#define VIDTCON3_HSPW_MASK			(0xffff << 16)
-#define VIDTCON3_HSPW_SHIFT			16
-#define VIDTCON3_HSPW_LIMIT			0xffff
-#define VIDTCON3_HSPW(_x)			((_x) << 16)
-
-/* VIDTCON4 */
-#define VIDTCON4				0x620
-
-#define VIDTCON4_LINEVAL_MASK			(0xfff << 16)
-#define VIDTCON4_LINEVAL_SHIFT			16
-#define VIDTCON4_LINEVAL_LIMIT			0xfff
-#define VIDTCON4_LINEVAL(_x)			(((_x) & 0xfff) << 16)
-
-#define VIDTCON4_HOZVAL_MASK			(0xfff << 0)
-#define VIDTCON4_HOZVAL_SHIFT			0
-#define VIDTCON4_HOZVAL_LIMIT			0xfff
-#define VIDTCON4_HOZVAL(_x)			(((_x) & 0xfff) << 0)
-
-/* LINECNT OP THRSHOLD*/
-#define LINECNT_OP_THRESHOLD			0x630
-
-/* CRCCTRL */
-#define CRCCTRL					0x6C8
-#define CRCCTRL_CRCCLKEN			(0x1 << 2)
-#define CRCCTRL_CRCSTART_F			(0x1 << 1)
-#define CRCCTRL_CRCEN				(0x1 << 0)
-
-/* DECON_CMU */
-#define DECON_CMU				0x704
-
-#define DECON_CMU_ALL_CLKGATE_ENABLE		0x3
-#define DECON_CMU_SE_CLKGATE_ENABLE		(0x1 << 2)
-#define DECON_CMU_SFR_CLKGATE_ENABLE		(0x1 << 1)
-#define DECON_CMU_MEM_CLKGATE_ENABLE		(0x1 << 0)
-
-/* DECON_UPDATE */
-#define DECON_UPDATE				0x710
-
-#define DECON_UPDATE_SLAVE_SYNC			(1 << 4)
-#define DECON_UPDATE_STANDALONE_F		(1 << 0)