From: Daniel Golle <daniel@makrotopia.org>
Date: Sat, 5 Feb 2022 17:14:17 +0000 (+0000)
Subject: realtek: drop support for Linux 5.4
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=58b82e6ca503aea3f67b4692f2c3196cb0a2ca2c;p=openwrt%2Fstaging%2Fxback.git

realtek: drop support for Linux 5.4

Drop patches and files for Linux 5.4 now that we've been using 5.10
for a while and support for Linux 5.4 has gone out-of-sync.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---

diff --git a/target/linux/realtek/config-5.4 b/target/linux/realtek/config-5.4
deleted file mode 100644
index 5e29879798..0000000000
--- a/target/linux/realtek/config-5.4
+++ /dev/null
@@ -1,192 +0,0 @@
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_CEVT_R4K=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_HAVE_CLK=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_BOSTON=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_LOAD_STORE_LR=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_SECTION_MISMATCH=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EARLY_PRINTK_8250=y
-CONFIG_EFI_EARLYCON=y
-CONFIG_ETHERNET_PACKET_MANGLE=y
-CONFIG_EXTRA_FIRMWARE="rtl838x_phy/rtl838x_8214fc.fw rtl838x_phy/rtl838x_8218b.fw rtl838x_phy/rtl838x_8380.fw"
-CONFIG_EXTRA_FIRMWARE_DIR="firmware"
-CONFIG_FIXED_PHY=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_AUTOSELECT=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_RTL8231=y
-CONFIG_GPIO_RTL838X=y
-CONFIG_REALTEK_SOC_PHY=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_HWMON=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_GPIO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_I2C=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CBPF_JIT=y
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-# CONFIG_MIPS_ELF_APPENDED_DTB is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_BRNIMAGE_FW=y
-CONFIG_MTD_SPLIT_EVA_FW=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_TPLINK_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_RTL83XX=y
-CONFIG_NET_DSA_TAG_TRAILER=y
-CONFIG_NET_RTL838X=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_PSB6970_PHY=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RTL838X=y
-CONFIG_RTL9300_TIMER=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SFP=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_RTL838X=y
-CONFIG_SRCU=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y
-CONFIG_USE_OF=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/realtek/dts-5.4/rtl8380_netgear_gigabit.dtsi b/target/linux/realtek/dts-5.4/rtl8380_netgear_gigabit.dtsi
deleted file mode 100644
index 8ba66d6023..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8380_netgear_gigabit.dtsi
+++ /dev/null
@@ -1,78 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "realtek,rtl838x-soc";
-
-	chosen {
-		bootargs = "console=ttyS0,115200";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x8000000>;
-	};
-
-	keys {
-		compatible = "gpio-keys-polled";
-		poll-interval = <20>;
-
-		mode {
-			label = "reset";
-			gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-&gpio0 {
-	indirect-access-bus-id = <0>;
-};
-
-&ethernet0 {
-	mdio: mdio-bus {
-		compatible = "realtek,rtl838x-mdio";
-		regmap = <&ethernet0>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		INTERNAL_PHY(8)
-		INTERNAL_PHY(9)
-		INTERNAL_PHY(10)
-		INTERNAL_PHY(11)
-		INTERNAL_PHY(12)
-		INTERNAL_PHY(13)
-		INTERNAL_PHY(14)
-		INTERNAL_PHY(15)
-	};
-};
-
-&switch0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		SWITCH_PORT(8, 1, internal)
-		SWITCH_PORT(9, 2, internal)
-		SWITCH_PORT(10, 3, internal)
-		SWITCH_PORT(11, 4, internal)
-		SWITCH_PORT(12, 5, internal)
-		SWITCH_PORT(13, 6, internal)
-		SWITCH_PORT(14, 7, internal)
-		SWITCH_PORT(15, 8, internal)
-
-		port@28 {
-			ethernet = <&ethernet0>;
-			reg = <28>;
-			phy-mode = "internal";
-			fixed-link {
-				speed = <1000>;
-				full-duplex;
-			};
-		};
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8380_netgear_gigabit_1xx.dtsi b/target/linux/realtek/dts-5.4/rtl8380_netgear_gigabit_1xx.dtsi
deleted file mode 100644
index 7eccfcb5a2..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8380_netgear_gigabit_1xx.dtsi
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_netgear_gigabit.dtsi"
-
-&spi0 {
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <50000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "u-boot";
-				reg = <0x0000000 0x00e0000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "u-boot-env";
-				reg = <0x00e0000 0x0010000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "u-boot-env2";
-				reg = <0x00f0000 0x0010000>;
-			};
-
-			partition@100000 {
-				label = "jffs";
-				reg = <0x0100000 0x0100000>;
-				read-only;
-			};
-
-			partition@200000 {
-				label = "jffs2";
-				reg = <0x0200000 0x0100000>;
-				read-only;
-			};
-
-			partition@300000 {
-				label = "firmware";
-				compatible = "openwrt,uimage", "denx,uimage";
-				openwrt,ih-magic = <0x4e474520>;
-				reg = <0x0300000 0x0e80000>;
-			};
-
-			partition@1180000 {
-				label = "runtime2";
-				reg = <0x1180000 0x0e80000>;
-				read-only;
-			};
-		};
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8380_netgear_gigabit_3xx.dtsi b/target/linux/realtek/dts-5.4/rtl8380_netgear_gigabit_3xx.dtsi
deleted file mode 100644
index efb146a25a..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8380_netgear_gigabit_3xx.dtsi
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_netgear_gigabit.dtsi"
-
-&spi0 {
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <50000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "u-boot";
-				reg = <0x0000000 0x00e0000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "u-boot-env";
-				reg = <0x00e0000 0x0010000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "u-boot-env2";
-				reg = <0x00f0000 0x0010000>;
-			};
-
-			partition@100000 {
-				label = "jffs";
-				reg = <0x0100000 0x0100000>;
-				read-only;
-			};
-
-			partition@200000 {
-				label = "jffs2";
-				reg = <0x0200000 0x0100000>;
-				read-only;
-			};
-
-			partition@300000 {
-				label = "firmware";
-				compatible = "openwrt,uimage", "denx,uimage";
-				openwrt,ih-magic = <0x4e474335>;
-				reg = <0x0300000 0x0e80000>;
-			};
-
-			partition@1180000 {
-				label = "runtime2";
-				reg = <0x1180000 0x0e80000>;
-				read-only;
-			};
-		};
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8380_netgear_gs108t-v3.dts b/target/linux/realtek/dts-5.4/rtl8380_netgear_gs108t-v3.dts
deleted file mode 100644
index b701e88d1a..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8380_netgear_gs108t-v3.dts
+++ /dev/null
@@ -1,8 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_netgear_gigabit_1xx.dtsi"
-
-/ {
-	compatible = "netgear,gs108t-v3", "realtek,rtl838x-soc";
-	model = "Netgear GS108T v3";
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8380_netgear_gs110tpp-v1.dts b/target/linux/realtek/dts-5.4/rtl8380_netgear_gs110tpp-v1.dts
deleted file mode 100644
index 646f4ed516..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8380_netgear_gs110tpp-v1.dts
+++ /dev/null
@@ -1,8 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_netgear_gigabit_1xx.dtsi"
-
-/ {
-	compatible = "netgear,gs110tpp-v1", "realtek,rtl838x-soc";
-	model = "Netgear GS110TPP v1";
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8380_netgear_gs308t-v1.dts b/target/linux/realtek/dts-5.4/rtl8380_netgear_gs308t-v1.dts
deleted file mode 100644
index 016ed8beb6..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8380_netgear_gs308t-v1.dts
+++ /dev/null
@@ -1,8 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_netgear_gigabit_3xx.dtsi"
-
-/ {
-	compatible = "netgear,gs308t-v1", "realtek,rtl838x-soc";
-	model = "Netgear GS308T v1";
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8380_netgear_gs310tp-v1.dts b/target/linux/realtek/dts-5.4/rtl8380_netgear_gs310tp-v1.dts
deleted file mode 100644
index e3f59bde69..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8380_netgear_gs310tp-v1.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_netgear_gigabit_3xx.dtsi"
-
-/ {
-	compatible = "netgear,gs310tp-v1", "realtek,rtl838x-soc";
-	model = "Netgear GS310TP v1";
-
-};
-
-&mdio {
-	INTERNAL_PHY(24)
-	INTERNAL_PHY(26)
-};
-
-&switch0 {
-	ports {
-		SWITCH_SFP_PORT(24, 9, rgmii-id)
-		SWITCH_SFP_PORT(26, 10, rgmii-id)
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900-10hp.dts b/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900-10hp.dts
deleted file mode 100644
index c16028788e..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900-10hp.dts
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
-	compatible = "zyxel,gs1900-10hp", "realtek,rtl838x-soc";
-	model = "ZyXEL GS1900-10HP Switch";
-
-	/* i2c of the left SFP cage: port 9 */
-	i2c0: i2c-gpio-0 {
-		compatible = "i2c-gpio";
-		sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		i2c-gpio,delay-us = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	sfp0: sfp-p9 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c0>;
-		los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
-	};
-
-	/* i2c of the right SFP cage: port 10 */
-	i2c1: i2c-gpio-1 {
-		compatible = "i2c-gpio";
-		sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		i2c-gpio,delay-us = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	sfp1: sfp-p10 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c1>;
-		los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&mdio {
-	INTERNAL_PHY(24)
-	INTERNAL_PHY(26)
-};
-
-&switch0 {
-	ports {
-		port@24 {
-			reg = <24>;
-			label = "lan9";
-			phy-mode = "1000base-x";
-			managed = "in-band-status";
-			sfp = <&sfp0>;
-		};
-
-		port@26 {
-			reg = <26>;
-			label = "lan10";
-			phy-mode = "1000base-x";
-			managed = "in-band-status";
-			sfp = <&sfp1>;
-		};
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900-8.dts b/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900-8.dts
deleted file mode 100644
index e9c5efe603..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900-8.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
-	compatible = "zyxel,gs1900-8", "realtek,rtl838x-soc";
-	model = "ZyXEL GS1900-8 Switch";
-};
-
-&gpio1 {
-	/delete-node/ poe_enable;
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900-8hp-v1.dts b/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900-8hp-v1.dts
deleted file mode 100644
index 0d9b7c97c0..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900-8hp-v1.dts
+++ /dev/null
@@ -1,8 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
-	compatible = "zyxel,gs1900-8hp-v1", "realtek,rtl838x-soc";
-	model = "ZyXEL GS1900-8HP v1 Switch";
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900-8hp-v2.dts b/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900-8hp-v2.dts
deleted file mode 100644
index cdc4aed6d1..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900-8hp-v2.dts
+++ /dev/null
@@ -1,8 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
-	compatible = "zyxel,gs1900-8hp-v2", "realtek,rtl838x-soc";
-	model = "ZyXEL GS1900-8HP v2 Switch";
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900.dtsi b/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900.dtsi
deleted file mode 100644
index d61ac3b2b8..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8380_zyxel_gs1900.dtsi
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	aliases {
-		led-boot = &led_sys;
-		led-failsafe = &led_sys;
-		led-running = &led_sys;
-		led-upgrade = &led_sys;
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x8000000>;
-	};
-
-	gpio1: rtl8231-gpio {
-		status = "okay";
-
-		poe_enable {
-			gpio-hog;
-			gpios = <13 0>;
-			output-high;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys-polled";
-		poll-interval = <20>;
-
-		reset {
-			label = "reset";
-			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_sys: sys {
-			label = "green:sys";
-			gpios = <&gpio0 47 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&spi0 {
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "u-boot";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "u-boot-env";
-				reg = <0x40000 0x10000>;
-				read-only;
-			};
-			partition@50000 {
-				label = "u-boot-env2";
-				reg = <0x50000 0x10000>;
-			};
-			partition@60000 {
-				label = "jffs";
-				reg = <0x60000 0x100000>;
-			};
-			partition@160000 {
-				label = "jffs2";
-				reg = <0x160000 0x100000>;
-			};
-			partition@b260000 {
-				label = "firmware";
-				reg = <0x260000 0x6d0000>;
-				compatible = "openwrt,uimage", "denx,uimage";
-				openwrt,ih-magic = <0x83800000>;
-			};
-			partition@930000 {
-				label = "runtime2";
-				reg = <0x930000 0x6d0000>;
-			};
-		};
-	};
-};
-
-&ethernet0 {
-	mdio: mdio-bus {
-		compatible = "realtek,rtl838x-mdio";
-		regmap = <&ethernet0>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		INTERNAL_PHY(8)
-		INTERNAL_PHY(9)
-		INTERNAL_PHY(10)
-		INTERNAL_PHY(11)
-		INTERNAL_PHY(12)
-		INTERNAL_PHY(13)
-		INTERNAL_PHY(14)
-		INTERNAL_PHY(15)
-	};
-};
-
-&switch0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		SWITCH_PORT(8, 1, internal)
-		SWITCH_PORT(9, 2, internal)
-		SWITCH_PORT(10, 3, internal)
-		SWITCH_PORT(11, 4, internal)
-		SWITCH_PORT(12, 5, internal)
-		SWITCH_PORT(13, 6, internal)
-		SWITCH_PORT(14, 7, internal)
-		SWITCH_PORT(15, 8, internal)
-
-		port@28 {
-			ethernet = <&ethernet0>;
-			reg = <28>;
-			phy-mode = "internal";
-
-			fixed-link {
-				speed = <1000>;
-				full-duplex;
-			};
-		};
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8382_allnet_all-sg8208m.dts b/target/linux/realtek/dts-5.4/rtl8382_allnet_all-sg8208m.dts
deleted file mode 100644
index fdcc01fdac..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8382_allnet_all-sg8208m.dts
+++ /dev/null
@@ -1,146 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "allnet,all-sg8208m", "realtek,rtl838x-soc";
-	model = "ALLNET ALL-SG8208M";
-
-	aliases {
-		led-boot = &led_sys;
-		led-failsafe = &led_sys;
-		led-running = &led_sys;
-		led-upgrade = &led_sys;
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x8000000>;
-	};
-
-	keys {
-		compatible = "gpio-keys-polled";
-		poll-interval = <20>;
-
-		reset {
-			label = "reset";
-			gpios = <&gpio0 67 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_sys: sys {
-			label = "green:sys";
-			gpios = <&gpio0 47 GPIO_ACTIVE_HIGH>;
-		};
-		// GPIO 25: power on/off all port leds
-	};
-};
-
-&gpio0 {
-	indirect-access-bus-id = <0>;
-};
-
-&spi0 {
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "u-boot";
-				reg = <0x0 0x80000>;
-				read-only;
-			};
-
-			partition@80000 {
-				label = "u-boot-env";
-				reg = <0x80000 0x10000>;
-				read-only;
-			};
-
-			partition@90000 {
-				label = "u-boot-env2";
-				reg = <0x90000 0x10000>;
-			};
-
-			partition@a0000 {
-				label = "jffs";
-				reg = <0xa0000 0x100000>;
-			};
-
-			partition@1a0000 {
-				label = "jffs2";
-				reg = <0x1a0000 0x100000>;
-			};
-
-			partition@2a0000 {
-				label = "firmware";
-				reg = <0x2a0000 0xd60000>;
-				compatible = "openwrt,uimage", "denx,uimage";
-				openwrt,ih-magic = <0x00000006>;
-			};
-		};
-	};
-};
-
-&ethernet0 {
-	mdio: mdio-bus {
-		compatible = "realtek,rtl838x-mdio";
-		regmap = <&ethernet0>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		INTERNAL_PHY(8)
-		INTERNAL_PHY(9)
-		INTERNAL_PHY(10)
-		INTERNAL_PHY(11)
-		INTERNAL_PHY(12)
-		INTERNAL_PHY(13)
-		INTERNAL_PHY(14)
-		INTERNAL_PHY(15)
-	};
-};
-
-&switch0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		SWITCH_PORT(8, 1, internal)
-		SWITCH_PORT(9, 2, internal)
-		SWITCH_PORT(10, 3, internal)
-		SWITCH_PORT(11, 4, internal)
-		SWITCH_PORT(12, 5, internal)
-		SWITCH_PORT(13, 6, internal)
-		SWITCH_PORT(14, 7, internal)
-		SWITCH_PORT(15, 8, internal)
-
-		port@28 {
-			ethernet = <&ethernet0>;
-			reg = <28>;
-			phy-mode = "internal";
-			fixed-link {
-				speed = <1000>;
-				full-duplex;
-			};
-		};
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8382_d-link_dgs-1210-10p.dts b/target/linux/realtek/dts-5.4/rtl8382_d-link_dgs-1210-10p.dts
deleted file mode 100644
index e2f5e7a4c0..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8382_d-link_dgs-1210-10p.dts
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "d-link,dgs-1210-10p", "realtek,rtl838x-soc";
-	model = "D-Link DGS-1210-10P";
-
-	aliases {
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x8000000>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_power: power {
-			// GPIO 24 seems to provide power to the leds
-			label = "green:power";
-			gpios = <&gpio0 47 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys-polled";
-		poll-interval = <20>;
-
-		mode {
-			label = "reset";
-			gpios = <&gpio0 94 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-
-&gpio0 {
-	indirect-access-bus-id = <0>;
-};
-
-&spi0 {
-	status = "okay";
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "u-boot";
-				reg = <0x00000000 0x80000>;
-				read-only;
-			};
-			partition@80000 {
-				label = "u-boot-env";
-				reg = <0x00080000 0x40000>;
-				read-only;
-			};
-			partition@c0000 {
-				label = "u-boot-env2";
-				reg = <0x000c0000 0x40000>;
-			};
-			partition@280000 {
-				label = "firmware";
-				compatible = "denx,uimage";
-				reg = <0x00100000 0xd80000>;
-			};
-			partition@be80000 {
-				label = "kernel2";
-				reg = <0x00e80000 0x180000>;
-			};
-			partition@1000000 {
-				label = "sysinfo";
-				reg = <0x01000000 0x40000>;
-			};
-			partition@1040000 {
-				label = "rootfs2";
-				reg = <0x01040000 0xc00000>;
-			};
-			partition@1c40000 {
-				label = "jffs2";
-				reg = <0x01c40000 0x3c0000>;
-			};
-		};
-	};
-};
-
-&ethernet0 {
-	mdio: mdio-bus {
-		compatible = "realtek,rtl838x-mdio";
-		regmap = <&ethernet0>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		INTERNAL_PHY(8)
-		INTERNAL_PHY(9)
-		INTERNAL_PHY(10)
-		INTERNAL_PHY(11)
-		INTERNAL_PHY(12)
-		INTERNAL_PHY(13)
-		INTERNAL_PHY(14)
-		INTERNAL_PHY(15)
-		INTERNAL_PHY(24)
-		INTERNAL_PHY(26)
-	};
-};
-
-&switch0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		SWITCH_PORT(8, 1, internal)
-		SWITCH_PORT(9, 2, internal)
-		SWITCH_PORT(10, 3, internal)
-		SWITCH_PORT(11, 4, internal)
-		SWITCH_PORT(12, 5, internal)
-		SWITCH_PORT(13, 6, internal)
-		SWITCH_PORT(14, 7, internal)
-		SWITCH_PORT(15, 8, internal)
-		SWITCH_SFP_PORT(24, 9, rgmii-id)
-		SWITCH_SFP_PORT(26, 10, rgmii-id)
-
-		port@28 {
-			ethernet = <&ethernet0>;
-			reg = <28>;
-			phy-mode = "internal";
-			fixed-link {
-				speed = <1000>;
-				full-duplex;
-			};
-		};
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8382_d-link_dgs-1210-16.dts b/target/linux/realtek/dts-5.4/rtl8382_d-link_dgs-1210-16.dts
deleted file mode 100644
index ac51185ed0..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8382_d-link_dgs-1210-16.dts
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl8382_d-link_dgs-1210.dtsi"
-
-/ {
-	compatible = "d-link,dgs-1210-16", "realtek,rtl838x-soc";
-	model = "D-Link DGS-1210-16";
-};
-
-&ethernet0 {
-	mdio: mdio-bus {
-		compatible = "realtek,rtl838x-mdio";
-		regmap = <&ethernet0>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		EXTERNAL_PHY(0)
-		EXTERNAL_PHY(1)
-		EXTERNAL_PHY(2)
-		EXTERNAL_PHY(3)
-		EXTERNAL_PHY(4)
-		EXTERNAL_PHY(5)
-		EXTERNAL_PHY(6)
-		EXTERNAL_PHY(7)
-
-		INTERNAL_PHY(8)
-		INTERNAL_PHY(9)
-		INTERNAL_PHY(10)
-		INTERNAL_PHY(11)
-		INTERNAL_PHY(12)
-		INTERNAL_PHY(13)
-		INTERNAL_PHY(14)
-		INTERNAL_PHY(15)
-
-		EXTERNAL_SFP_PHY(24)
-		EXTERNAL_SFP_PHY(25)
-		EXTERNAL_SFP_PHY(26)
-		EXTERNAL_SFP_PHY(27)
-	};
-};
-
-&switch0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		SWITCH_PORT(0, 1, qsgmii)
-		SWITCH_PORT(1, 2, qsgmii)
-		SWITCH_PORT(2, 3, qsgmii)
-		SWITCH_PORT(3, 4, qsgmii)
-		SWITCH_PORT(4, 5, qsgmii)
-		SWITCH_PORT(5, 6, qsgmii)
-		SWITCH_PORT(6, 7, qsgmii)
-		SWITCH_PORT(7, 8, qsgmii)
-
-		SWITCH_PORT(8, 9, internal)
-		SWITCH_PORT(9, 10, internal)
-		SWITCH_PORT(10, 11, internal)
-		SWITCH_PORT(11, 12, internal)
-		SWITCH_PORT(12, 13, internal)
-		SWITCH_PORT(13, 14, internal)
-		SWITCH_PORT(14, 15, internal)
-		SWITCH_PORT(15, 16, internal)
-
-		SWITCH_PORT(24, 17, qsgmii)
-		SWITCH_PORT(25, 18, qsgmii)
-		SWITCH_PORT(26, 19, qsgmii)
-		SWITCH_PORT(27, 20, qsgmii)
-
-		port@28 {
-			ethernet = <&ethernet0>;
-			reg = <28>;
-			phy-mode = "internal";
-			fixed-link {
-				speed = <1000>;
-				full-duplex;
-			};
-		};
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8382_d-link_dgs-1210-28.dts b/target/linux/realtek/dts-5.4/rtl8382_d-link_dgs-1210-28.dts
deleted file mode 100644
index edd4fb140f..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8382_d-link_dgs-1210-28.dts
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl8382_d-link_dgs-1210.dtsi"
-
-/ {
-	compatible = "d-link,dgs-1210-28", "realtek,rtl838x-soc";
-	model = "D-Link DGS-1210-28";
-};
-
-&ethernet0 {
-	mdio: mdio-bus {
-		compatible = "realtek,rtl838x-mdio";
-		regmap = <&ethernet0>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		EXTERNAL_PHY(0)
-		EXTERNAL_PHY(1)
-		EXTERNAL_PHY(2)
-		EXTERNAL_PHY(3)
-		EXTERNAL_PHY(4)
-		EXTERNAL_PHY(5)
-		EXTERNAL_PHY(6)
-		EXTERNAL_PHY(7)
-
-		INTERNAL_PHY(8)
-		INTERNAL_PHY(9)
-		INTERNAL_PHY(10)
-		INTERNAL_PHY(11)
-		INTERNAL_PHY(12)
-		INTERNAL_PHY(13)
-		INTERNAL_PHY(14)
-		INTERNAL_PHY(15)
-
-		EXTERNAL_PHY(16)
-		EXTERNAL_PHY(17)
-		EXTERNAL_PHY(18)
-		EXTERNAL_PHY(19)
-		EXTERNAL_PHY(20)
-		EXTERNAL_PHY(21)
-		EXTERNAL_PHY(22)
-		EXTERNAL_PHY(23)
-
-		EXTERNAL_SFP_PHY(24)
-		EXTERNAL_SFP_PHY(25)
-		EXTERNAL_SFP_PHY(26)
-		EXTERNAL_SFP_PHY(27)
-	};
-};
-
-&switch0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		SWITCH_PORT(0, 1, qsgmii)
-		SWITCH_PORT(1, 2, qsgmii)
-		SWITCH_PORT(2, 3, qsgmii)
-		SWITCH_PORT(3, 4, qsgmii)
-		SWITCH_PORT(4, 5, qsgmii)
-		SWITCH_PORT(5, 6, qsgmii)
-		SWITCH_PORT(6, 7, qsgmii)
-		SWITCH_PORT(7, 8, qsgmii)
-
-		SWITCH_PORT(8, 9, internal)
-		SWITCH_PORT(9, 10, internal)
-		SWITCH_PORT(10, 11, internal)
-		SWITCH_PORT(11, 12, internal)
-		SWITCH_PORT(12, 13, internal)
-		SWITCH_PORT(13, 14, internal)
-		SWITCH_PORT(14, 15, internal)
-		SWITCH_PORT(15, 16, internal)
-
-		SWITCH_PORT(16, 17, qsgmii)
-		SWITCH_PORT(17, 18, qsgmii)
-		SWITCH_PORT(18, 19, qsgmii)
-		SWITCH_PORT(19, 20, qsgmii)
-		SWITCH_PORT(20, 21, qsgmii)
-		SWITCH_PORT(21, 22, qsgmii)
-		SWITCH_PORT(22, 23, qsgmii)
-		SWITCH_PORT(23, 24, qsgmii)
-
-		SWITCH_PORT(24, 25, qsgmii)
-		SWITCH_PORT(25, 26, qsgmii)
-		SWITCH_PORT(26, 27, qsgmii)
-		SWITCH_PORT(27, 28, qsgmii)
-
-		port@28 {
-			ethernet = <&ethernet0>;
-			reg = <28>;
-			phy-mode = "internal";
-			fixed-link {
-				speed = <1000>;
-				full-duplex;
-			};
-		};
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8382_d-link_dgs-1210.dtsi b/target/linux/realtek/dts-5.4/rtl8382_d-link_dgs-1210.dtsi
deleted file mode 100644
index a14738c8a9..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8382_d-link_dgs-1210.dtsi
+++ /dev/null
@@ -1,88 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	aliases {
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x8000000>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_power: power {
-			label = "green:power";
-			gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&gpio0 {
-	indirect-access-bus-id = <0>;
-};
-
-&spi0 {
-	status = "okay";
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "u-boot";
-				reg = <0x00000000 0x80000>;
-				read-only;
-			};
-			partition@80000 {
-				label = "u-boot-env";
-				reg = <0x00080000 0x40000>;
-				read-only;
-			};
-			partition@c0000 {
-				label = "u-boot-env2";
-				reg = <0x000c0000 0x40000>;
-			};
-			partition@280000 {
-				label = "firmware";
-				compatible = "denx,uimage";
-				reg = <0x00100000 0xd80000>;
-			};
-			partition@be80000 {
-				label = "kernel2";
-				reg = <0x00e80000 0x180000>;
-			};
-			partition@1000000 {
-				label = "sysinfo";
-				reg = <0x01000000 0x40000>;
-			};
-			partition@1040000 {
-				label = "rootfs2";
-				reg = <0x01040000 0xc00000>;
-			};
-			partition@1c40000 {
-				label = "jffs2";
-				reg = <0x01c40000 0x3c0000>;
-			};
-		};
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8382_inaba_aml2-17gp.dts b/target/linux/realtek/dts-5.4/rtl8382_inaba_aml2-17gp.dts
deleted file mode 100644
index 87761ac462..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8382_inaba_aml2-17gp.dts
+++ /dev/null
@@ -1,164 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "inaba,aml2-17gp", "realtek,rtl838x-soc";
-	model = "INABA Abaniact AML2-17GP";
-
-	chosen {
-		bootargs = "console=ttyS0,115200";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x8000000>;
-	};
-
-	keys {
-		compatible = "gpio-keys-polled";
-		poll-interval = <20>;
-
-		reset {
-			label = "reset";
-			gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-&gpio0 {
-	indirect-access-bus-id = <0>;
-};
-
-&spi0 {
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "u-boot";
-				reg = <0x0 0x80000>;
-				read-only;
-			};
-
-			partition@80000 {
-				label = "u-boot-env";
-				reg = <0x80000 0x10000>;
-				read-only;
-			};
-
-			partition@90000 {
-				label = "u-boot-env2";
-				reg = <0x90000 0x10000>;
-			};
-
-			partition@a0000 {
-				label = "jffs2_cfg";
-				reg = <0xa0000 0x400000>;
-				read-only;
-			};
-
-			partition@4a0000 {
-				label = "jffs2_log";
-				reg = <0x4a0000 0x100000>;
-				read-only;
-			};
-
-			partition@5a0000 {
-				compatible = "openwrt,uimage", "denx,uimage";
-				label = "firmware";
-				reg = <0x5a0000 0xd30000>;
-				openwrt,ih-magic = <0x83800000>;
-			};
-
-			partition@12d0000 {
-				label = "runtime2";
-				reg = <0x12d0000 0xd30000>;
-			};
-		};
-	};
-};
-
-&ethernet0 {
-	mdio-bus {
-		compatible = "realtek,rtl838x-mdio";
-		regmap = <&ethernet0>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		INTERNAL_PHY(8)
-		INTERNAL_PHY(9)
-		INTERNAL_PHY(10)
-		INTERNAL_PHY(11)
-		INTERNAL_PHY(12)
-		INTERNAL_PHY(13)
-		INTERNAL_PHY(14)
-		INTERNAL_PHY(15)
-
-		EXTERNAL_PHY(16)
-		EXTERNAL_PHY(17)
-		EXTERNAL_PHY(18)
-		EXTERNAL_PHY(19)
-		EXTERNAL_PHY(20)
-		EXTERNAL_PHY(21)
-		EXTERNAL_PHY(22)
-		EXTERNAL_PHY(23)
-
-		EXTERNAL_PHY(24)
-	};
-};
-
-&switch0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		SWITCH_PORT(8, 1, internal)
-		SWITCH_PORT(9, 2, internal)
-		SWITCH_PORT(10, 3, internal)
-		SWITCH_PORT(11, 4, internal)
-		SWITCH_PORT(12, 5, internal)
-		SWITCH_PORT(13, 6, internal)
-		SWITCH_PORT(14, 7, internal)
-		SWITCH_PORT(15, 8, internal)
-
-		SWITCH_PORT(16, 9, qsgmii)
-		SWITCH_PORT(17, 10, qsgmii)
-		SWITCH_PORT(18, 11, qsgmii)
-		SWITCH_PORT(19, 12, qsgmii)
-		SWITCH_PORT(20, 13, qsgmii)
-		SWITCH_PORT(21, 14, qsgmii)
-		SWITCH_PORT(22, 15, qsgmii)
-		SWITCH_PORT(23, 16, qsgmii)
-
-		port@24 {
-			reg = <24>;
-			label = "wan";
-			phy-handle = <&phy24>;
-			phy-mode = "qsgmii";
-		};
-
-		port@28 {
-			ethernet = <&ethernet0>;
-			reg = <28>;
-			phy-mode = "internal";
-
-			fixed-link {
-				speed = <1000>;
-				full-duplex;
-			};
-		};
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl8382_zyxel_gs1900-24hp-v2.dts b/target/linux/realtek/dts-5.4/rtl8382_zyxel_gs1900-24hp-v2.dts
deleted file mode 100644
index c16152521e..0000000000
--- a/target/linux/realtek/dts-5.4/rtl8382_zyxel_gs1900-24hp-v2.dts
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
-	compatible = "zyxel,gs1900-24hp-v2", "realtek,rtl838x-soc";
-	model = "ZyXEL GS1900-24HP v2 Switch";
-
-	/* i2c of the left SFP cage: port 25 */
-	i2c0: i2c-gpio-0 {
-		compatible = "i2c-gpio";
-		sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		i2c-gpio,delay-us = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	sfp0: sfp-p25 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c0>;
-		los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
-	};
-
-	/* i2c of the right SFP cage: port 26 */
-	i2c1: i2c-gpio-1 {
-		compatible = "i2c-gpio";
-		sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-		i2c-gpio,delay-us = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	sfp1: sfp-p26 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c1>;
-		los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&mdio {
-	EXTERNAL_PHY(0)
-	EXTERNAL_PHY(1)
-	EXTERNAL_PHY(2)
-	EXTERNAL_PHY(3)
-	EXTERNAL_PHY(4)
-	EXTERNAL_PHY(5)
-	EXTERNAL_PHY(6)
-	EXTERNAL_PHY(7)
-
-	EXTERNAL_PHY(16)
-	EXTERNAL_PHY(17)
-	EXTERNAL_PHY(18)
-	EXTERNAL_PHY(19)
-	EXTERNAL_PHY(20)
-	EXTERNAL_PHY(21)
-	EXTERNAL_PHY(22)
-	EXTERNAL_PHY(23)
-
-	INTERNAL_PHY(24)
-	INTERNAL_PHY(26)
-};
-
-&switch0 {
-	ports {
-		SWITCH_PORT(0, 1, qsgmii)
-		SWITCH_PORT(1, 2, qsgmii)
-		SWITCH_PORT(2, 3, qsgmii)
-		SWITCH_PORT(3, 4, qsgmii)
-		SWITCH_PORT(4, 5, qsgmii)
-		SWITCH_PORT(5, 6, qsgmii)
-		SWITCH_PORT(6, 7, qsgmii)
-		SWITCH_PORT(7, 8, qsgmii)
-
-		SWITCH_PORT(8, 9, internal)
-		SWITCH_PORT(9, 10, internal)
-		SWITCH_PORT(10, 11, internal)
-		SWITCH_PORT(11, 12, internal)
-		SWITCH_PORT(12, 13, internal)
-		SWITCH_PORT(13, 14, internal)
-		SWITCH_PORT(14, 15, internal)
-		SWITCH_PORT(15, 16, internal)
-
-		SWITCH_PORT(16, 17, qsgmii)
-		SWITCH_PORT(17, 18, qsgmii)
-		SWITCH_PORT(18, 19, qsgmii)
-		SWITCH_PORT(19, 20, qsgmii)
-		SWITCH_PORT(20, 21, qsgmii)
-		SWITCH_PORT(21, 22, qsgmii)
-		SWITCH_PORT(22, 23, qsgmii)
-		SWITCH_PORT(23, 24, qsgmii)
-
-
-		port@24 {
-			reg = <24>;
-			label = "lan25";
-			phy-mode = "1000base-x";
-			managed = "in-band-status";
-			sfp = <&sfp0>;
-		};
-
-		port@26 {
-			reg = <26>;
-			label = "lan26";
-			phy-mode = "1000base-x";
-			managed = "in-band-status";
-			sfp = <&sfp1>;
-		};
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl838x.dtsi b/target/linux/realtek/dts-5.4/rtl838x.dtsi
deleted file mode 100644
index b59b141f66..0000000000
--- a/target/linux/realtek/dts-5.4/rtl838x.dtsi
+++ /dev/null
@@ -1,188 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/dts-v1/;
-
-#define STRINGIZE(s) #s
-#define LAN_LABEL(p, s) STRINGIZE(p ## s)
-#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
-
-#define INTERNAL_PHY(n) \
-	phy##n: ethernet-phy@##n { \
-		reg = <##n>; \
-		compatible = "ethernet-phy-ieee802.3-c22"; \
-		phy-is-integrated; \
-	};
-
-#define EXTERNAL_PHY(n) \
-	phy##n: ethernet-phy@##n { \
-		reg = <##n>; \
-		compatible = "ethernet-phy-ieee802.3-c22"; \
-	};
-
-#define EXTERNAL_SFP_PHY(n) \
-	phy##n: ethernet-phy@##n { \
-		compatible = "ethernet-phy-ieee802.3-c22"; \
-		sfp; \
-		media = "fibre"; \
-		reg = <##n>; \
-	};
-
-#define SWITCH_PORT(n, s, m) \
-	port@##n { \
-		reg = <##n>; \
-		label = SWITCH_PORT_LABEL(s) ; \
-		phy-handle = <&phy##n>; \
-		phy-mode = #m ; \
-	};
-
-#define SWITCH_SFP_PORT(n, s, m) \
-	port@##n { \
-		reg = <##n>; \
-		label = SWITCH_PORT_LABEL(s) ; \
-		phy-handle = <&phy##n>; \
-		phy-mode = #m ; \
-		fixed-link { \
-			speed = <1000>; \
-			full-duplex; \
-		}; \
-	};
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	compatible = "realtek,rtl838x-soc";
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		frequency = <500000000>;
-
-		cpu@0 {
-			compatible = "mips,mips4KEc";
-			reg = <0>;
-		};
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,38400";
-	};
-
-	cpuintc: cpuintc {
-		#address-cells = <0>;
-		#interrupt-cells = <1>;
-		interrupt-controller;
-		compatible = "mti,cpu-interrupt-controller";
-	};
-
-	intc: rtlintc {
-		#address-cells = <0>;
-		#interrupt-cells = <1>;
-		interrupt-controller;
-		compatible = "realtek,rt8380-intc";
-		reg = <0xb8003000 0x20>;
-	};
-
-	spi0: spi@b8001200 {
-		status = "okay";
-
-		compatible = "realtek,rtl838x-nor";
-		reg = <0xb8001200 0x100>;
-
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	uart0: uart@b8002000 {
-		status = "okay";
-
-		compatible = "ns16550a";
-		reg = <0xb8002000 0x100>;
-
-		clock-frequency = <200000000>;
-
-		interrupt-parent = <&intc>;
-		interrupts = <31>;
-
-		reg-io-width = <1>;
-		reg-shift = <2>;
-		fifo-size = <1>;
-		no-loopback-test;
-	};
-
-	uart1: uart@b8002100 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&enable_uart1>;
-
-		status = "okay";
-
-		compatible = "ns16550a";
-		reg = <0xb8002100 0x100>;
-
-		clock-frequency = <200000000>;
-
-		interrupt-parent = <&intc>;
-		interrupts = <30>;
-
-		reg-io-width = <1>;
-		reg-shift = <2>;
-		fifo-size = <1>;
-		no-loopback-test;
-	};
-
-	gpio0: gpio-controller@b8003500 {
-		compatible = "realtek,rtl838x-gpio";
-		reg = <0xb8003500 0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&intc>;
-		interrupts = <23>;
-	};
-
-	gpio1: rtl8231-gpio {
-		status = "disabled";
-		compatible = "realtek,rtl8231-gpio";
-		#gpio-cells = <2>;
-		indirect-access-bus-id = <0>;
-		gpio-controller;
-	};
-
-	pinmux: pinmux@bb001000 {
-		compatible = "pinctrl-single";
-		reg = <0xbb001000 0x4>;
-
-		pinctrl-single,bit-per-mux;
-		pinctrl-single,register-width = <32>;
-		pinctrl-single,function-mask = <0x1>;
-		#pinctrl-cells = <2>;
-
-		enable_uart1: pinmux_enable_uart1 {
-			pinctrl-single,bits = <0x0 0x10 0x10>;
-		};
-	};
-
-	ethernet0: ethernet@bb00a300 {
-		status = "okay";
-
-		compatible = "realtek,rtl838x-eth";
-		reg = <0xbb00a300 0x100>;
-		interrupt-parent = <&intc>;
-		interrupts = <24>;
-		#interrupt-cells = <1>;
-		phy-mode = "internal";
-
-		fixed-link {
-			speed = <1000>;
-			full-duplex;
-		};
-	};
-
-	switch0: switch@bb000000 {
-		status = "okay";
-
-		interrupt-parent = <&intc>;
-		interrupts = <20>;
-
-		compatible = "realtek,rtl83xx-switch";
-	};
-};
diff --git a/target/linux/realtek/dts-5.4/rtl930x.dtsi b/target/linux/realtek/dts-5.4/rtl930x.dtsi
deleted file mode 100644
index 5d13fc31b3..0000000000
--- a/target/linux/realtek/dts-5.4/rtl930x.dtsi
+++ /dev/null
@@ -1,182 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/dts-v1/;
-
-#define STRINGIZE(s) #s
-#define LAN_LABEL(p, s) STRINGIZE(p ## s)
-#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
-
-#define INTERNAL_PHY(n) \
-	phy##n: ethernet-phy@##n { \
-		reg = <##n>; \
-		compatible = "ethernet-phy-ieee802.3-c22"; \
-		phy-is-integrated; \
-	};
-
-#define EXTERNAL_PHY(n) \
-	phy##n: ethernet-phy@##n { \
-		reg = <##n>; \
-		compatible = "ethernet-phy-ieee802.3-c22"; \
-	};
-
-#define EXTERNAL_SFP_PHY(n) \
-	phy##n: ethernet-phy@##n { \
-		compatible = "ethernet-phy-ieee802.3-c22"; \
-		sfp; \
-		media = "fibre"; \
-		reg = <##n>; \
-	};
-
-#define SWITCH_PORT(n, s, m) \
-	port@##n { \
-		reg = <##n>; \
-		label = SWITCH_PORT_LABEL(s) ; \
-		phy-handle = <&phy##n>; \
-		phy-mode = #m ; \
-	};
-
-#define SWITCH_SFP_PORT(n, s, m) \
-	port@##n { \
-		reg = <##n>; \
-		label = SWITCH_PORT_LABEL(s) ; \
-		phy-handle = <&phy##n>; \
-		phy-mode = #m ; \
-		fixed-link { \
-			speed = <1000>; \
-			full-duplex; \
-		}; \
-	};
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	compatible = "realtek,rtl838x-soc";
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		frequency = <800000000>;
-
-		cpu@0 {
-			compatible = "mips,mips34Kc";
-			reg = <0>;
-		};
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x8000000>;
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,38400";
-	};
-
-	cpuintc: cpuintc {
-		#address-cells = <0>;
-		#interrupt-cells = <1>;
-		interrupt-controller;
-		compatible = "mti,cpu-interrupt-controller";
-	};
-
-	intc: rtlintc {
-		#address-cells = <0>;
-		#interrupt-cells = <1>;
-		interrupt-controller;
-		compatible = "realtek,rt9300-intc";
-		reg = <0xb8003000 0x20>;
-	};
-
-	osc: oscillator {
-		compatible = "fixed-clock";
-		#clock-cells = <1>;
-		clock-frequency  = <175000000>;
-		clock-output-names = "osc";
-	};
-
-	timer: timer@b8003200 {
-		compatible = "realtek,rtl9300-timer";
-		reg = <0xb8003200 0x60>;
-		interrupt-parent = <&intc>;
-		interrupts = <8>;
-		interrupt-names = "ostimer";
-		clocks = <&osc 0>;
-	};
-
-	spi0: spi@b8001200 {
-		status = "okay";
-
-		compatible = "realtek,rtl838x-nor";
-		reg = <0xb8001200 0x100>;
-
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	uart0: uart@b8002000 {
-		compatible = "ns16550a";
-		reg = <0xb8002000 0x100>;
-
-		clock-frequency = <175000000>;
-
-		interrupt-parent = <&intc>;
-		interrupts = <30>;
-
-		reg-io-width = <1>;
-		reg-shift = <2>;
-		fifo-size = <1>;
-		no-loopback-test;
-
-		status = "okay";
-	};
-
-	uart1: uart@b8002100 {
-		compatible = "ns16550a";
-		reg = <0xb8002100 0x100>;
-
-		clock-frequency = <175000000>;
-
-		interrupt-parent = <&intc>;
-		interrupts = <31>;
-
-		reg-io-width = <1>;
-		reg-shift = <2>;
-		fifo-size = <1>;
-		no-loopback-test;
-
-		status = "okay";
-	};
-
-	gpio0: gpio-controller@b8003500 {
-		compatible = "realtek,rtl838x-gpio";
-		reg = <0xb8003500 0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&intc>;
-		interrupts = <31>;
-	};
-
-	ethernet0: ethernet@bb00a300 {
-		status = "okay";
-		compatible = "realtek,rtl838x-eth";
-		reg = <0xbb00a300 0x100>;
-		interrupt-parent = <&intc>;
-		interrupts = <24>;
-		#interrupt-cells = <1>;
-		phy-mode = "internal";
-		fixed-link {
-			speed = <1000>;
-			full-duplex;
-		};
-	};
-
-	switch0: switch@bb000000 {
-		status = "okay";
-
-		interrupt-parent = <&intc>;
-		interrupts = <20>;
-
-		compatible = "realtek,rtl83xx-switch";
-	};
-};
diff --git a/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h b/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h
deleted file mode 100644
index e7a5bfaffc..0000000000
--- a/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef RTL838X_IOREMAP_H_
-#define RTL838X_IOREMAP_H_
-
-static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
-{
-	return phys_addr;
-}
-
-static inline int is_rtl838x_internal_registers(phys_addr_t offset)
-{
-	/* IO-Block */
-	if (offset >= 0xb8000000 && offset < 0xb9000000)
-		return 1;
-	/* Switch block */
-	if (offset >= 0xbb000000 && offset < 0xbc000000)
-		return 1;
-	return 0;
-}
-
-static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
-					 unsigned long flags)
-{
-	if (is_rtl838x_internal_registers(offset))
-		return (void __iomem *)offset;
-	return NULL;
-}
-
-static inline int plat_iounmap(const volatile void __iomem *addr)
-{
-	return is_rtl838x_internal_registers((unsigned long)addr);
-}
-
-#endif
diff --git a/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h b/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h
deleted file mode 100644
index a4e95ab511..0000000000
--- a/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h
+++ /dev/null
@@ -1,93 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#ifndef _RTL83XX_IRQ_H_
-#define _RTL83XX_IRQ_H_
-
-#define NR_IRQS 32
-#include_next <irq.h>
-
-/* Global Interrupt Mask Register */
-#define RTL83XX_ICTL_GIMR	0x00
-/* Global Interrupt Status Register */
-#define RTL83XX_ICTL_GISR	0x04
-
-#define RTL83XX_IRQ_CPU_BASE	0
-#define RTL83XX_IRQ_CPU_NUM	8
-#define RTL83XX_IRQ_ICTL_BASE	(RTL83XX_IRQ_CPU_BASE + RTL83XX_IRQ_CPU_NUM)
-#define RTL83XX_IRQ_ICTL_NUM	32
-
-/* Cascaded interrupts */
-#define RTL83XX_ICTL1_IRQ	(RTL83XX_IRQ_CPU_BASE + 2)
-#define RTL83XX_ICTL2_IRQ	(RTL83XX_IRQ_CPU_BASE + 3)
-#define RTL83XX_ICTL3_IRQ	(RTL83XX_IRQ_CPU_BASE + 4)
-#define RTL83XX_ICTL4_IRQ	(RTL83XX_IRQ_CPU_BASE + 5)
-#define RTL83XX_ICTL5_IRQ	(RTL83XX_IRQ_CPU_BASE + 6)
-
-/* Interrupt routing register */
-#define RTL83XX_IRR0		0x08
-#define RTL83XX_IRR1		0x0c
-#define RTL83XX_IRR2		0x10
-#define RTL83XX_IRR3		0x14
-
-/* Cascade map */
-#define UART0_CASCADE		2
-#define UART1_CASCADE		1
-#define TC0_CASCADE		5
-#define TC1_CASCADE		1
-#define TC2_CASCADE		1
-#define TC3_CASCADE		1
-#define TC4_CASCADE		1
-#define OCPTO_CASCADE		1
-#define HLXTO_CASCADE		1
-#define SLXTO_CASCADE		1
-#define NIC_CASCADE		4
-#define GPIO_ABCD_CASCADE	4
-#define GPIO_EFGH_CASCADE	4
-#define RTC_CASCADE		4
-#define	SWCORE_CASCADE		3
-#define WDT_IP1_CASCADE		4
-#define WDT_IP2_CASCADE		5
-#define USB_H2_CASCADE		1
-
-/* Pack cascade map into interrupt routing registers */
-#define RTL83XX_IRR0_SETTING (\
-	(UART0_CASCADE		<< 28) | \
-	(UART1_CASCADE		<< 24) | \
-	(TC0_CASCADE		<< 20) | \
-	(TC1_CASCADE		<< 16) | \
-	(OCPTO_CASCADE		<< 12) | \
-	(HLXTO_CASCADE		<< 8)  | \
-	(SLXTO_CASCADE		<< 4)  | \
-	(NIC_CASCADE		<< 0))
-#define RTL83XX_IRR1_SETTING (\
-	(GPIO_ABCD_CASCADE	<< 28) | \
-	(GPIO_EFGH_CASCADE	<< 24) | \
-	(RTC_CASCADE		<< 20) | \
-	(SWCORE_CASCADE		<< 16))
-#define RTL83XX_IRR2_SETTING	0
-#define RTL83XX_IRR3_SETTING	0
-
-/* On the RTL8390 there is no GPIO_EFGH and RTC IRQ */
-#define RTL8390_IRR1_SETTING (\
-	(GPIO_ABCD_CASCADE	<< 28) | \
-	(SWCORE_CASCADE		<< 16))
-
-/* The RTL9300 has a different external IRQ numbering scheme */
-#define RTL9300_IRR0_SETTING (\
-	(UART1_CASCADE		<< 28) | \
-	(UART0_CASCADE		<< 24) | \
-	(USB_H2_CASCADE		<< 16) | \
-	(NIC_CASCADE		<< 0))
-#define RTL9300_IRR1_SETTING (\
-	(SWCORE_CASCADE		<< 28))
-#define RTL9300_IRR2_SETTING (\
-	(GPIO_ABCD_CASCADE	<< 20) | \
-	(TC4_CASCADE		<< 12) | \
-	(TC3_CASCADE		<< 8) | \
-	(TC2_CASCADE		<< 4) | \
-	(TC1_CASCADE		<< 0))
-#define RTL9300_IRR3_SETTING (\
-	(TC0_CASCADE		<< 28) | \
-	(WDT_IP1_CASCADE	<< 20))
-
-#endif /* _RTL83XX_IRQ_H_ */
diff --git a/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h b/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h
deleted file mode 100644
index 0abfc6f4d2..0000000000
--- a/target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h
+++ /dev/null
@@ -1,418 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
- * Copyright (C) 2020 B. Koblitz
- */
-#ifndef _MACH_RTL838X_H_
-#define _MACH_RTL838X_H_
-
-#include <asm/types.h>
-/*
- * Register access macros
- */
-
-#define RTL838X_SW_BASE		((volatile void *) 0xBB000000)
-
-#define rtl83xx_r32(reg)	readl(reg)
-#define rtl83xx_w32(val, reg)	writel(val, reg)
-#define rtl83xx_w32_mask(clear, set, reg) rtl83xx_w32((rtl83xx_r32(reg) & ~(clear)) | (set), reg)
-
-#define rtl83xx_r8(reg)		readb(reg)
-#define rtl83xx_w8(val, reg)	writeb(val, reg)
-
-#define sw_r32(reg)		readl(RTL838X_SW_BASE + reg)
-#define sw_w32(val, reg)	writel(val, RTL838X_SW_BASE + reg)
-#define sw_w32_mask(clear, set, reg)	\
-				sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
-#define sw_r64(reg)		((((u64)readl(RTL838X_SW_BASE + reg)) << 32) | \
-				readl(RTL838X_SW_BASE + reg + 4))
-
-#define sw_w64(val, reg)	do { \
-					writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \
-					writel((u32)((val) & 0xffffffff), \
-							RTL838X_SW_BASE + reg + 4); \
-				} while (0)
-
-/*
- * SPRAM
- */
-#define RTL838X_ISPRAM_BASE	0x0
-#define RTL838X_DSPRAM_BASE	0x0
-
-/*
- * IRQ Controller
- */
-#define RTL838X_IRQ_CPU_BASE	0
-#define RTL838X_IRQ_CPU_NUM	8
-#define RTL838X_IRQ_ICTL_BASE	(RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM)
-#define RTL838X_IRQ_ICTL_NUM	32
-
-#define RTL83XX_IRQ_UART0		31
-#define RTL83XX_IRQ_UART1		30
-#define RTL83XX_IRQ_TC0			29
-#define RTL83XX_IRQ_TC1			28
-#define RTL83XX_IRQ_OCPTO		27
-#define RTL83XX_IRQ_HLXTO		26
-#define RTL83XX_IRQ_SLXTO		25
-#define RTL83XX_IRQ_NIC			24
-#define RTL83XX_IRQ_GPIO_ABCD		23
-#define RTL83XX_IRQ_GPIO_EFGH		22
-#define RTL83XX_IRQ_RTC			21
-#define RTL83XX_IRQ_SWCORE		20
-#define RTL83XX_IRQ_WDT_IP1		19
-#define RTL83XX_IRQ_WDT_IP2		18
-
-#define RTL9300_UART1_IRQ		31
-#define RTL9300_UART0_IRQ		30
-#define RTL9300_USB_H2_IRQ		28
-#define RTL9300_NIC_IRQ			24
-#define RTL9300_SWCORE_IRQ		23
-#define RTL9300_GPIO_ABC_IRQ		13
-#define RTL9300_TC4_IRQ			11
-#define RTL9300_TC3_IRQ			10
-#define RTL9300_TC2_IRQ			 9
-#define RTL9300_TC1_IRQ			 8
-#define RTL9300_TC0_IRQ			 7
-
-
-/*
- * MIPS32R2 counter
- */
-#define RTL838X_COMPARE_IRQ	(RTL838X_IRQ_CPU_BASE + 7)
-
-/*
- *  ICTL
- *  Base address 0xb8003000UL
- */
-#define RTL838X_ICTL1_IRQ	(RTL838X_IRQ_CPU_BASE + 2)
-#define RTL838X_ICTL2_IRQ	(RTL838X_IRQ_CPU_BASE + 3)
-#define RTL838X_ICTL3_IRQ	(RTL838X_IRQ_CPU_BASE + 4)
-#define RTL838X_ICTL4_IRQ	(RTL838X_IRQ_CPU_BASE + 5)
-#define RTL838X_ICTL5_IRQ	(RTL838X_IRQ_CPU_BASE + 6)
-
-#define GIMR			(0x00)
-#define UART0_IE		(1 << 31)
-#define UART1_IE		(1 << 30)
-#define TC0_IE			(1 << 29)
-#define TC1_IE			(1 << 28)
-#define OCPTO_IE		(1 << 27)
-#define HLXTO_IE		(1 << 26)
-#define SLXTO_IE		(1 << 25)
-#define NIC_IE			(1 << 24)
-#define GPIO_ABCD_IE		(1 << 23)
-#define GPIO_EFGH_IE		(1 << 22)
-#define RTC_IE			(1 << 21)
-#define WDT_IP1_IE		(1 << 19)
-#define WDT_IP2_IE		(1 << 18)
-
-#define GISR			(0x04)
-#define UART0_IP		(1 << 31)
-#define UART1_IP		(1 << 30)
-#define TC0_IP			(1 << 29)
-#define TC1_IP			(1 << 28)
-#define OCPTO_IP		(1 << 27)
-#define HLXTO_IP		(1 << 26)
-#define SLXTO_IP		(1 << 25)
-#define NIC_IP			(1 << 24)
-#define GPIO_ABCD_IP		(1 << 23)
-#define GPIO_EFGH_IP		(1 << 22)
-#define RTC_IP			(1 << 21)
-#define WDT_IP1_IP		(1 << 19)
-#define WDT_IP2_IP		(1 << 18)
-
-
-/* Interrupt Routing Selection */
-#define UART0_RS		2
-#define UART1_RS		1
-#define TC0_RS			5
-#define TC1_RS			1
-#define OCPTO_RS		1
-#define HLXTO_RS		1
-#define SLXTO_RS		1
-#define NIC_RS			4
-#define GPIO_ABCD_RS		4
-#define GPIO_EFGH_RS		4
-#define RTC_RS			4
-#define	SWCORE_RS		3
-#define WDT_IP1_RS		4
-#define WDT_IP2_RS		5
-
-/* Interrupt IRQ Assignments */
-#define UART0_IRQ		31
-#define UART1_IRQ		30
-#define TC0_IRQ			29
-#define TC1_IRQ			28
-#define OCPTO_IRQ		27
-#define HLXTO_IRQ		26
-#define SLXTO_IRQ		25
-#define NIC_IRQ			24
-#define GPIO_ABCD_IRQ		23
-#define GPIO_EFGH_IRQ		22
-#define RTC_IRQ			21
-#define	SWCORE_IRQ		20
-#define WDT_IP1_IRQ		19
-#define WDT_IP2_IRQ		18
-
-#define SYSTEM_FREQ		200000000
-#define RTL838X_UART0_BASE	((volatile void *)(0xb8002000UL))
-#define RTL838X_UART0_BAUD	38400  /* ex. 19200 or 38400 or 57600 or 115200 */
-#define RTL838X_UART0_FREQ	(SYSTEM_FREQ - RTL838X_UART0_BAUD * 24)
-#define RTL838X_UART0_MAPBASE	0x18002000UL
-#define RTL838X_UART0_MAPSIZE	0x100
-#define RTL838X_UART0_IRQ	UART0_IRQ
-
-#define RTL838X_UART1_BASE	((volatile void *)(0xb8002100UL))
-#define RTL838X_UART1_BAUD	38400  /* ex. 19200 or 38400 or 57600 or 115200 */
-#define RTL838X_UART1_FREQ	(SYSTEM_FREQ - RTL838X_UART1_BAUD * 24)
-#define RTL838X_UART1_MAPBASE	0x18002100UL
-#define RTL838X_UART1_MAPSIZE	0x100
-#define RTL838X_UART1_IRQ	UART1_IRQ
-
-#define UART0_RBR		(RTL838X_UART0_BASE + 0x000)
-#define UART0_THR		(RTL838X_UART0_BASE + 0x000)
-#define UART0_DLL		(RTL838X_UART0_BASE + 0x000)
-#define UART0_IER		(RTL838X_UART0_BASE + 0x004)
-#define UART0_DLM		(RTL838X_UART0_BASE + 0x004)
-#define UART0_IIR		(RTL838X_UART0_BASE + 0x008)
-#define UART0_FCR		(RTL838X_UART0_BASE + 0x008)
-#define UART0_LCR		(RTL838X_UART0_BASE + 0x00C)
-#define UART0_MCR		(RTL838X_UART0_BASE + 0x010)
-#define UART0_LSR		(RTL838X_UART0_BASE + 0x014)
-
-#define UART1_RBR		(RTL838X_UART1_BASE + 0x000)
-#define UART1_THR		(RTL838X_UART1_BASE + 0x000)
-#define UART1_DLL		(RTL838X_UART1_BASE + 0x000)
-#define UART1_IER		(RTL838X_UART1_BASE + 0x004)
-#define UART1_DLM		(RTL838X_UART1_BASE + 0x004)
-#define UART1_IIR		(RTL838X_UART1_BASE + 0x008)
-#define UART1_FCR		(RTL838X_UART1_BASE + 0x008)
-#define UART1_LCR		(RTL838X_UART1_BASE + 0x00C)
-#define UART1_MCR		(RTL838X_UART1_BASE + 0x010)
-#define UART1_LSR		(RTL838X_UART1_BASE + 0x014)
-
-/*
- * Memory Controller
- */
-#define MC_MCR			0xB8001000
-#define MC_MCR_VAL		0x00000000
-
-#define MC_DCR			0xB8001004
-#define MC_DCR0_VAL		0x54480000
-
-#define MC_DTCR			0xB8001008
-#define MC_DTCR_VAL		0xFFFF05C0
-
-/*
- * GPIO
- */
-#define GPIO_CTRL_REG_BASE		((volatile void *) 0xb8003500)
-#define RTL838X_GPIO_PABC_CNR		(GPIO_CTRL_REG_BASE + 0x0)
-#define RTL838X_GPIO_PABC_TYPE		(GPIO_CTRL_REG_BASE + 0x04)
-#define RTL838X_GPIO_PABC_DIR		(GPIO_CTRL_REG_BASE + 0x8)
-#define RTL838X_GPIO_PABC_DATA		(GPIO_CTRL_REG_BASE + 0xc)
-#define RTL838X_GPIO_PABC_ISR		(GPIO_CTRL_REG_BASE + 0x10)
-#define RTL838X_GPIO_PAB_IMR		(GPIO_CTRL_REG_BASE + 0x14)
-#define RTL838X_GPIO_PC_IMR		(GPIO_CTRL_REG_BASE + 0x18)
-
-#define RTL838X_MODEL_NAME_INFO		(0x00D4)
-#define RTL839X_MODEL_NAME_INFO		(0x0FF0)
-#define RTL93XX_MODEL_NAME_INFO		(0x0004)
-
-#define RTL838X_LED_GLB_CTRL		(0xA000)
-#define RTL839X_LED_GLB_CTRL		(0x00E4)
-#define RTL9302_LED_GLB_CTRL		(0xcc00)
-#define RTL930X_LED_GLB_CTRL		(0xC400)
-#define RTL931X_LED_GLB_CTRL		(0x0600)
-
-#define RTL838X_EXT_GPIO_DIR		(0xA08C)
-#define RTL839X_EXT_GPIO_DIR		(0x0214)
-#define RTL838X_EXT_GPIO_DATA		(0xA094)
-#define RTL839X_EXT_GPIO_DATA		(0x021c)
-#define RTL838X_EXT_GPIO_INDRT_ACCESS	(0xA09C)
-#define RTL839X_EXT_GPIO_INDRT_ACCESS	(0x0224)
-#define RTL838X_EXTRA_GPIO_CTRL		(0xA0E0)
-#define RTL838X_DMY_REG5		(0x0144)
-#define RTL838X_EXTRA_GPIO_CTRL		(0xA0E0)
-
-#define RTL838X_GMII_INTF_SEL		(0x1000)
-#define RTL838X_IO_DRIVING_ABILITY_CTRL	(0x1010)
-
-#define RTL838X_GPIO_A7		31
-#define RTL838X_GPIO_A6		30
-#define RTL838X_GPIO_A5		29
-#define RTL838X_GPIO_A4		28
-#define RTL838X_GPIO_A3		27
-#define RTL838X_GPIO_A2		26
-#define RTL838X_GPIO_A1		25
-#define RTL838X_GPIO_A0		24
-#define RTL838X_GPIO_B7		23
-#define RTL838X_GPIO_B6		22
-#define RTL838X_GPIO_B5		21
-#define RTL838X_GPIO_B4		20
-#define RTL838X_GPIO_B3		19
-#define RTL838X_GPIO_B2		18
-#define RTL838X_GPIO_B1		17
-#define RTL838X_GPIO_B0		16
-#define RTL838X_GPIO_C7		15
-#define RTL838X_GPIO_C6		14
-#define RTL838X_GPIO_C5		13
-#define RTL838X_GPIO_C4		12
-#define RTL838X_GPIO_C3		11
-#define RTL838X_GPIO_C2		10
-#define RTL838X_GPIO_C1		9
-#define RTL838X_GPIO_C0		8
-
-#define RTL838X_INT_RW_CTRL		(0x0058)
-#define RTL838X_EXT_VERSION		(0x00D0)
-#define RTL838X_PLL_CML_CTRL		(0x0FF8)
-#define RTL838X_STRAP_DBG		(0x100C)
-
-/*
- * Reset
- */
-#define	RGCR				(0x1E70)
-#define RTL838X_RST_GLB_CTRL_0		(0x003c)
-#define RTL838X_RST_GLB_CTRL_1		(0x0040)
-#define RTL839X_RST_GLB_CTRL		(0x0014)
-#define RTL930X_RST_GLB_CTRL_0		(0x000c)
-#define RTL931X_RST_GLB_CTRL		(0x0400)
-
-/* LED control by switch */
-#define RTL838X_LED_MODE_SEL		(0x1004)
-#define RTL838X_LED_MODE_CTRL		(0xA004)
-#define RTL838X_LED_P_EN_CTRL		(0xA008)
-
-/* LED control by software */
-#define RTL838X_LED_SW_CTRL		(0x0128)
-#define RTL839X_LED_SW_CTRL		(0xA00C)
-#define RTL838X_LED_SW_P_EN_CTRL	(0xA010)
-#define RTL839X_LED_SW_P_EN_CTRL	(0x012C)
-#define RTL838X_LED0_SW_P_EN_CTRL	(0xA010)
-#define RTL839X_LED0_SW_P_EN_CTRL	(0x012C)
-#define RTL838X_LED1_SW_P_EN_CTRL	(0xA014)
-#define RTL839X_LED1_SW_P_EN_CTRL	(0x0130)
-#define RTL838X_LED2_SW_P_EN_CTRL	(0xA018)
-#define RTL839X_LED2_SW_P_EN_CTRL	(0x0134)
-#define RTL838X_LED_SW_P_CTRL		(0xA01C)
-#define RTL839X_LED_SW_P_CTRL		(0x0144)
-
-#define RTL839X_MAC_EFUSE_CTRL		(0x02ac)
-
-/*
- * MDIO via Realtek's SMI interface
- */
-#define RTL838X_SMI_GLB_CTRL		(0xa100)
-#define RTL838X_SMI_ACCESS_PHY_CTRL_0	(0xa1b8)
-#define RTL838X_SMI_ACCESS_PHY_CTRL_1	(0xa1bc)
-#define RTL838X_SMI_ACCESS_PHY_CTRL_2	(0xa1c0)
-#define RTL838X_SMI_ACCESS_PHY_CTRL_3	(0xa1c4)
-#define RTL838X_SMI_PORT0_5_ADDR_CTRL	(0xa1c8)
-#define RTL838X_SMI_POLL_CTRL		(0xa17c)
-
-#define RTL839X_SMI_GLB_CTRL		(0x03f8)
-#define RTL839X_SMI_PORT_POLLING_CTRL	(0x03fc)
-#define RTL839X_PHYREG_ACCESS_CTRL	(0x03DC)
-#define RTL839X_PHYREG_CTRL		(0x03E0)
-#define RTL839X_PHYREG_PORT_CTRL	(0x03E4)
-#define RTL839X_PHYREG_DATA_CTRL	(0x03F0)
-#define RTL839X_PHYREG_MMD_CTRL		(0x3F4)
-
-#define RTL930X_SMI_GLB_CTRL		(0xCA00)
-#define RTL930X_SMI_POLL_CTRL		(0xca90)
-#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08)
-#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C)
-#define RTL930X_SMI_PORT0_5_ADDR	(0xCB80)
-#define RTL930X_SMI_ACCESS_PHY_CTRL_0	(0xCB70)
-#define RTL930X_SMI_ACCESS_PHY_CTRL_1	(0xCB74)
-#define RTL930X_SMI_ACCESS_PHY_CTRL_2	(0xCB78)
-#define RTL930X_SMI_ACCESS_PHY_CTRL_3	(0xCB7C)
-
-#define RTL931X_SMI_GLB_CTRL1		(0x0CBC)
-#define RTL931X_SMI_GLB_CTRL0		(0x0CC0)
-#define RTL931X_SMI_PORT_POLLING_CTRL	(0x0CCC)
-#define RTL931X_SMI_INDRT_ACCESS_CTRL_0	(0x0C00)
-#define RTL931X_SMI_INDRT_ACCESS_CTRL_1	(0x0C04)
-#define RTL931X_SMI_INDRT_ACCESS_CTRL_2	(0x0C08)
-#define RTL931X_SMI_INDRT_ACCESS_CTRL_3	(0x0C10)
-#define RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL (0x0C14)
-#define RTL931X_SMI_INDRT_ACCESS_MMD_CTRL (0xC18)
-
-#define RTL930X_SMI_GLB_CTRL		(0xCA00)
-#define RTL930X_SMI_POLL_CTRL		(0xca90)
-#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08)
-#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C)
-#define RTL930X_SMI_PORT0_5_ADDR	(0xCB80)
-#define RTL930X_SMI_ACCESS_PHY_CTRL_0	(0xCB70)
-#define RTL930X_SMI_ACCESS_PHY_CTRL_1	(0xCB74)
-#define RTL930X_SMI_ACCESS_PHY_CTRL_2	(0xCB78)
-#define RTL930X_SMI_ACCESS_PHY_CTRL_3	(0xCB7C)
-
-#define RTL931X_SMI_GLB_CTRL1		(0x0CBC)
-#define RTL931X_SMI_GLB_CTRL0		(0x0CC0)
-#define RTL931X_SMI_PORT_POLLING_CTRL	(0x0CCC)
-#define RTL931X_SMI_INDRT_ACCESS_CTRL_0	(0x0C00)
-#define RTL931X_SMI_INDRT_ACCESS_CTRL_1	(0x0C04)
-#define RTL931X_SMI_INDRT_ACCESS_CTRL_2	(0x0C08)
-#define RTL931X_SMI_INDRT_ACCESS_CTRL_3	(0x0C10)
-
-/*
- * Switch interrupts
- */
-#define RTL838X_IMR_GLB			(0x1100)
-#define RTL838X_IMR_PORT_LINK_STS_CHG	(0x1104)
-#define RTL838X_ISR_GLB_SRC		(0x1148)
-#define RTL838X_ISR_PORT_LINK_STS_CHG	(0x114C)
-
-#define RTL839X_IMR_GLB			(0x0064)
-#define RTL839X_IMR_PORT_LINK_STS_CHG	(0x0068)
-#define RTL839X_ISR_GLB_SRC		(0x009c)
-#define RTL839X_ISR_PORT_LINK_STS_CHG	(0x00a0)
-
-#define RTL930X_IMR_GLB			(0xC628)
-#define RTL930X_IMR_PORT_LINK_STS_CHG	(0xC62C)
-#define RTL930X_ISR_GLB			(0xC658)
-#define RTL930X_ISR_PORT_LINK_STS_CHG	(0xC660)
-
-// IMR_GLB does not exit on RTL931X
-#define RTL931X_IMR_PORT_LINK_STS_CHG	(0x126C)
-#define RTL931X_ISR_GLB_SRC		(0x12B4)
-#define RTL931X_ISR_PORT_LINK_STS_CHG	(0x12B8)
-
-/* Definition of family IDs */
-#define RTL8389_FAMILY_ID   (0x8389)
-#define RTL8328_FAMILY_ID   (0x8328)
-#define RTL8390_FAMILY_ID   (0x8390)
-#define RTL8350_FAMILY_ID   (0x8350)
-#define RTL8380_FAMILY_ID   (0x8380)
-#define RTL8330_FAMILY_ID   (0x8330)
-#define RTL9300_FAMILY_ID   (0x9300)
-#define RTL9310_FAMILY_ID   (0x9310)
-
-/* Basic SoC Features */
-#define RTL838X_CPU_PORT			28
-#define RTL839X_CPU_PORT			52
-#define RTL930X_CPU_PORT			28
-#define RTL931X_CPU_PORT			56
-
-struct rtl83xx_soc_info {
-	unsigned char *name;
-	unsigned int id;
-	unsigned int family;
-	unsigned char *compatible;
-	volatile void *sw_base;
-	volatile void *icu_base;
-	int cpu_port;
-};
-
-/* rtl83xx-related functions used across subsystems */
-int rtl838x_smi_wait_op(int timeout);
-int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
-int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
-int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
-int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
-int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
-int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val);
-int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
-int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val);
-
-#endif   /* _MACH_RTL838X_H_ */
diff --git a/target/linux/realtek/files-5.4/arch/mips/rtl838x/Makefile b/target/linux/realtek/files-5.4/arch/mips/rtl838x/Makefile
deleted file mode 100644
index 8212dc3f48..0000000000
--- a/target/linux/realtek/files-5.4/arch/mips/rtl838x/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the rtl838x specific parts of the kernel
-#
-
-obj-y := setup.o prom.o irq.o
diff --git a/target/linux/realtek/files-5.4/arch/mips/rtl838x/Platform b/target/linux/realtek/files-5.4/arch/mips/rtl838x/Platform
deleted file mode 100644
index 4d48932d80..0000000000
--- a/target/linux/realtek/files-5.4/arch/mips/rtl838x/Platform
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Realtek RTL838x SoCs
-#
-platform-$(CONFIG_RTL838X) += rtl838x/
-cflags-$(CONFIG_RTL838X)   += -I$(srctree)/arch/mips/include/asm/mach-rtl838x/
-load-$(CONFIG_RTL838X)     += 0xffffffff80000000
diff --git a/target/linux/realtek/files-5.4/arch/mips/rtl838x/irq.c b/target/linux/realtek/files-5.4/arch/mips/rtl838x/irq.c
deleted file mode 100644
index c0dd2f608c..0000000000
--- a/target/linux/realtek/files-5.4/arch/mips/rtl838x/irq.c
+++ /dev/null
@@ -1,226 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Realtek RTL83XX architecture specific IRQ handling
- *
- * based on the original BSP
- * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
- * Copyright (C) 2020 B. Koblitz
- * Copyright (C) 2020 Bert Vermeulen <bert@biot.com>
- * Copyright (C) 2020 John Crispin <john@phrozen.org>
- */
-
-#include <linux/irqchip.h>
-#include <linux/spinlock.h>
-#include <linux/of_address.h>
-#include <asm/irq_cpu.h>
-#include <linux/of_irq.h>
-#include <asm/cevt-r4k.h>
-
-#include <mach-rtl83xx.h>
-#include "irq.h"
-
-#define REALTEK_CPU_IRQ_SHARED0		(MIPS_CPU_IRQ_BASE + 2)
-#define REALTEK_CPU_IRQ_UART		(MIPS_CPU_IRQ_BASE + 3)
-#define REALTEK_CPU_IRQ_SWITCH		(MIPS_CPU_IRQ_BASE + 4)
-#define REALTEK_CPU_IRQ_SHARED1		(MIPS_CPU_IRQ_BASE + 5)
-#define REALTEK_CPU_IRQ_EXTERNAL	(MIPS_CPU_IRQ_BASE + 6)
-#define REALTEK_CPU_IRQ_COUNTER		(MIPS_CPU_IRQ_BASE + 7)
-
-#define REG(x)				(rtl83xx_ictl_base + x)
-
-extern struct rtl83xx_soc_info soc_info;
-
-static DEFINE_RAW_SPINLOCK(irq_lock);
-static void __iomem *rtl83xx_ictl_base;
-
-static void rtl83xx_ictl_enable_irq(struct irq_data *i)
-{
-	unsigned long flags;
-	u32 value;
-
-	raw_spin_lock_irqsave(&irq_lock, flags);
-
-	value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR));
-	value |= BIT(i->hwirq);
-	rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR));
-
-	raw_spin_unlock_irqrestore(&irq_lock, flags);
-}
-
-static void rtl83xx_ictl_disable_irq(struct irq_data *i)
-{
-	unsigned long flags;
-	u32 value;
-
-	raw_spin_lock_irqsave(&irq_lock, flags);
-
-	value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR));
-	value &= ~BIT(i->hwirq);
-	rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR));
-
-	raw_spin_unlock_irqrestore(&irq_lock, flags);
-}
-
-static struct irq_chip rtl83xx_ictl_irq = {
-	.name = "RTL83xx",
-	.irq_enable = rtl83xx_ictl_enable_irq,
-	.irq_disable = rtl83xx_ictl_disable_irq,
-	.irq_ack = rtl83xx_ictl_disable_irq,
-	.irq_mask = rtl83xx_ictl_disable_irq,
-	.irq_unmask = rtl83xx_ictl_enable_irq,
-	.irq_eoi = rtl83xx_ictl_enable_irq,
-};
-
-static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-{
-	irq_set_chip_and_handler(hw, &rtl83xx_ictl_irq, handle_level_irq);
-
-	return 0;
-}
-
-static const struct irq_domain_ops irq_domain_ops = {
-	.map = intc_map,
-	.xlate = irq_domain_xlate_onecell,
-};
-
-static void rtl838x_irq_dispatch(struct irq_desc *desc)
-{
-	unsigned int pending = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR)) &
-				rtl83xx_r32(REG(RTL83XX_ICTL_GISR));
-
-	if (pending) {
-		struct irq_domain *domain = irq_desc_get_handler_data(desc);
-		generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
-	} else {
-		spurious_interrupt();
-	}
-}
-
-asmlinkage void plat_rtl83xx_irq_dispatch(void)
-{
-	unsigned int pending;
-
-	pending =  read_c0_cause() & read_c0_status() & ST0_IM;
-
-	if (pending & CAUSEF_IP7)
-		do_IRQ(REALTEK_CPU_IRQ_COUNTER);
-
-	else if (pending & CAUSEF_IP6)
-		do_IRQ(REALTEK_CPU_IRQ_EXTERNAL);
-
-	else if (pending & CAUSEF_IP5)
-		do_IRQ(REALTEK_CPU_IRQ_SHARED1);
-
-	else if (pending & CAUSEF_IP4)
-		do_IRQ(REALTEK_CPU_IRQ_SWITCH);
-
-	else if (pending & CAUSEF_IP3)
-		do_IRQ(REALTEK_CPU_IRQ_UART);
-
-	else if (pending & CAUSEF_IP2)
-		do_IRQ(REALTEK_CPU_IRQ_SHARED0);
-
-	else
-		spurious_interrupt();
-}
-
-static int icu_setup_domain(struct device_node *node)
-{
-	struct irq_domain *domain;
-
-	domain = irq_domain_add_simple(node, 32, 0,
-				       &irq_domain_ops, NULL);
-	irq_set_chained_handler_and_data(2, rtl838x_irq_dispatch, domain);
-	irq_set_chained_handler_and_data(3, rtl838x_irq_dispatch, domain);
-	irq_set_chained_handler_and_data(4, rtl838x_irq_dispatch, domain);
-	irq_set_chained_handler_and_data(5, rtl838x_irq_dispatch, domain);
-
-	rtl83xx_ictl_base = of_iomap(node, 0);
-	if (!rtl83xx_ictl_base)
-		return -EINVAL;
-
-	return 0;
-}
-
-static void __init rtl8380_icu_of_init(struct device_node *node, struct device_node *parent)
-{
-	if (icu_setup_domain(node))
-		return;
-
-	/* Disable all cascaded interrupts */
-	rtl83xx_w32(0, REG(RTL83XX_ICTL_GIMR));
-
-	/* Set up interrupt routing */
-	rtl83xx_w32(RTL83XX_IRR0_SETTING, REG(RTL83XX_IRR0));
-	rtl83xx_w32(RTL83XX_IRR1_SETTING, REG(RTL83XX_IRR1));
-	rtl83xx_w32(RTL83XX_IRR2_SETTING, REG(RTL83XX_IRR2));
-	rtl83xx_w32(RTL83XX_IRR3_SETTING, REG(RTL83XX_IRR3));
-
-	/* Clear timer interrupt */
-	write_c0_compare(0);
-
-	/* Enable all CPU interrupts */
-	write_c0_status(read_c0_status() | ST0_IM);
-
-	/* Enable timer0 and uart0 interrupts */
-	rtl83xx_w32(BIT(RTL83XX_IRQ_TC0) | BIT(RTL83XX_IRQ_UART0), REG(RTL83XX_ICTL_GIMR));
-}
-
-static void __init rtl8390_icu_of_init(struct device_node *node, struct device_node *parent)
-{
-	if (icu_setup_domain(node))
-		return;
-
-	/* Disable all cascaded interrupts */
-	rtl83xx_w32(0, REG(RTL83XX_ICTL_GIMR));
-
-	/* Set up interrupt routing */
-	rtl83xx_w32(RTL83XX_IRR0_SETTING, REG(RTL83XX_IRR0));
-	rtl83xx_w32(RTL8390_IRR1_SETTING, REG(RTL83XX_IRR1));
-	rtl83xx_w32(RTL83XX_IRR2_SETTING, REG(RTL83XX_IRR2));
-	rtl83xx_w32(RTL83XX_IRR3_SETTING, REG(RTL83XX_IRR3));
-
-	/* Clear timer interrupt */
-	write_c0_compare(0);
-
-	/* Enable all CPU interrupts */
-	write_c0_status(read_c0_status() | ST0_IM);
-
-	/* Enable timer0 and uart0 interrupts */
-	rtl83xx_w32(BIT(RTL83XX_IRQ_TC0) | BIT(RTL83XX_IRQ_UART0), REG(RTL83XX_ICTL_GIMR));
-}
-
-static void __init rtl9300_icu_of_init(struct device_node *node, struct device_node *parent)
-{
-	pr_info("RTL9300: Setting up IRQs\n");
-	if (icu_setup_domain(node))
-		return;
-
-	/* Disable all cascaded interrupts */
-	rtl83xx_w32(0, REG(RTL83XX_ICTL_GIMR));
-
-	/* Set up interrupt routing */
-	rtl83xx_w32(RTL9300_IRR0_SETTING, REG(RTL83XX_IRR0));
-	rtl83xx_w32(RTL9300_IRR1_SETTING, REG(RTL83XX_IRR1));
-	rtl83xx_w32(RTL9300_IRR2_SETTING, REG(RTL83XX_IRR2));
-	rtl83xx_w32(RTL9300_IRR3_SETTING, REG(RTL83XX_IRR3));
-
-	/* Clear timer interrupt */
-	write_c0_compare(0);
-
-	/* Enable all CPU interrupts */
-	write_c0_status(read_c0_status() | ST0_IM);
-}
-
-static struct of_device_id __initdata of_irq_ids[] = {
-	{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
-	{ .compatible = "realtek,rt8380-intc", .data = rtl8380_icu_of_init },
-	{ .compatible = "realtek,rt8390-intc", .data = rtl8390_icu_of_init },
-	{ .compatible = "realtek,rt9300-intc", .data = rtl9300_icu_of_init },
-	{},
-};
-
-void __init arch_init_irq(void)
-{
-	of_irq_init(of_irq_ids);
-}
diff --git a/target/linux/realtek/files-5.4/arch/mips/rtl838x/prom.c b/target/linux/realtek/files-5.4/arch/mips/rtl838x/prom.c
deleted file mode 100644
index 3390c04334..0000000000
--- a/target/linux/realtek/files-5.4/arch/mips/rtl838x/prom.c
+++ /dev/null
@@ -1,183 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * prom.c
- * Early intialization code for the Realtek RTL838X SoC
- *
- * based on the original BSP by
- * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
- * Copyright (C) 2020 B. Koblitz
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/of_fdt.h>
-#include <linux/libfdt.h>
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-#include <asm/page.h>
-#include <asm/cpu.h>
-
-#include <mach-rtl83xx.h>
-
-extern char arcs_cmdline[];
-extern const char __appended_dtb;
-
-struct rtl83xx_soc_info soc_info;
-const void *fdt;
-
-const char *get_system_type(void)
-{
-	return soc_info.name;
-}
-
-void __init prom_free_prom_memory(void)
-{
-
-}
-
-void __init device_tree_init(void)
-{
-	if (!fdt_check_header(&__appended_dtb)) {
-		fdt = &__appended_dtb;
-		pr_info("Using appended Device Tree.\n");
-	}
-	initial_boot_params = (void *)fdt;
-	unflatten_and_copy_device_tree();
-}
-
-static void __init prom_init_cmdline(void)
-{
-	int argc = fw_arg0;
-	char **argv = (char **) KSEG1ADDR(fw_arg1);
-	int i;
-
-	arcs_cmdline[0] = '\0';
-
-	for (i = 0; i < argc; i++) {
-		char *p = (char *) KSEG1ADDR(argv[i]);
-
-		if (CPHYSADDR(p) && *p) {
-			strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
-			strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
-		}
-	}
-	pr_info("Kernel command line: %s\n", arcs_cmdline);
-}
-
-void __init identify_rtl9302(void)
-{
-	switch (sw_r32(RTL93XX_MODEL_NAME_INFO) & 0xfffffff0) {
-	case 0x93020810:
-		soc_info.name = "RTL9302A 12x2.5G";
-		break;
-	case 0x93021010:
-		soc_info.name = "RTL9302B 8x2.5G";
-		break;
-	case 0x93021810:
-		soc_info.name = "RTL9302C 16x2.5G";
-		break;
-	case 0x93022010:
-		soc_info.name = "RTL9302D 24x2.5G";
-		break;
-	case 0x93020800:
-		soc_info.name = "RTL9302A";
-		break;
-	case 0x93021000:
-		soc_info.name = "RTL9302B";
-		break;
-	case 0x93021800:
-		soc_info.name = "RTL9302C";
-		break;
-	case 0x93022000:
-		soc_info.name = "RTL9302D";
-		break;
-	case 0x93023001:
-		soc_info.name = "RTL9302F";
-		break;
-	default:
-		soc_info.name = "RTL9302";
-	}
-}
-
-void __init prom_init(void)
-{
-	uint32_t model;
-
-	/* uart0 */
-	setup_8250_early_printk_port(0xb8002000, 2, 0);
-
-	model = sw_r32(RTL838X_MODEL_NAME_INFO);
-	pr_info("RTL838X model is %x\n", model);
-	model = model >> 16 & 0xFFFF;
-
-	if ((model != 0x8328) && (model != 0x8330) && (model != 0x8332)
-	    && (model != 0x8380) && (model != 0x8382)) {
-		model = sw_r32(RTL839X_MODEL_NAME_INFO);
-		pr_info("RTL839X model is %x\n", model);
-		model = model >> 16 & 0xFFFF;
-	}
-
-	if ((model & 0x8390) != 0x8380 && (model & 0x8390) != 0x8390) {
-		model = sw_r32(RTL93XX_MODEL_NAME_INFO);
-		pr_info("RTL93XX model is %x\n", model);
-		model = model >> 16 & 0xFFFF;
-	}
-
-	soc_info.id = model;
-
-	switch (model) {
-	case 0x8328:
-		soc_info.name = "RTL8328";
-		soc_info.family = RTL8328_FAMILY_ID;
-		break;
-	case 0x8332:
-		soc_info.name = "RTL8332";
-		soc_info.family = RTL8380_FAMILY_ID;
-		break;
-	case 0x8380:
-		soc_info.name = "RTL8380";
-		soc_info.family = RTL8380_FAMILY_ID;
-		break;
-	case 0x8382:
-		soc_info.name = "RTL8382";
-		soc_info.family = RTL8380_FAMILY_ID;
-		break;
-	case 0x8390:
-		soc_info.name = "RTL8390";
-		soc_info.family = RTL8390_FAMILY_ID;
-		break;
-	case 0x8391:
-		soc_info.name = "RTL8391";
-		soc_info.family = RTL8390_FAMILY_ID;
-		break;
-	case 0x8392:
-		soc_info.name = "RTL8392";
-		soc_info.family = RTL8390_FAMILY_ID;
-		break;
-	case 0x8393:
-		soc_info.name = "RTL8393";
-		soc_info.family = RTL8390_FAMILY_ID;
-		break;
-	case 0x9301:
-		soc_info.name = "RTL9301";
-		soc_info.family = RTL9300_FAMILY_ID;
-		break;
-	case 0x9302:
-		identify_rtl9302();
-		soc_info.family = RTL9300_FAMILY_ID;
-		break;
-	case 0x9313:
-		soc_info.name = "RTL9313";
-		soc_info.family = RTL9310_FAMILY_ID;
-		break;
-	default:
-		soc_info.name = "DEFAULT";
-		soc_info.family = 0;
-	}
-
-	pr_info("SoC Type: %s\n", get_system_type());
-
-	prom_init_cmdline();
-}
diff --git a/target/linux/realtek/files-5.4/arch/mips/rtl838x/setup.c b/target/linux/realtek/files-5.4/arch/mips/rtl838x/setup.c
deleted file mode 100644
index ef97d485e1..0000000000
--- a/target/linux/realtek/files-5.4/arch/mips/rtl838x/setup.c
+++ /dev/null
@@ -1,195 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Setup for the Realtek RTL838X SoC:
- *	Memory, Timer and Serial
- *
- * Copyright (C) 2020 B. Koblitz
- * based on the original BSP by
- * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
- *
- */
-
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/delay.h>
-#include <linux/of_fdt.h>
-
-#include <asm/addrspace.h>
-#include <asm/io.h>
-#include <asm/bootinfo.h>
-#include <asm/reboot.h>
-#include <asm/time.h>
-#include <asm/prom.h>
-#include <asm/smp-ops.h>
-
-#include "mach-rtl83xx.h"
-
-extern struct rtl83xx_soc_info soc_info;
-
-u32 pll_reset_value;
-
-static void rtl838x_restart(char *command)
-{
-	u32 pll = sw_r32(RTL838X_PLL_CML_CTRL);
-
-	pr_info("System restart.\n");
-	pr_info("PLL control register: %x, applying reset value %x\n",
-		pll, pll_reset_value);
-
-	sw_w32(3, RTL838X_INT_RW_CTRL);
-	sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL);
-	sw_w32(0, RTL838X_INT_RW_CTRL);
-
-	/* Reset Global Control1 Register */
-	sw_w32(1, RTL838X_RST_GLB_CTRL_1);
-}
-
-static void rtl839x_restart(char *command)
-{
-	/* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
-	void (*f)(void) = (void *) 0xbfc00000;
-
-	pr_info("System restart.\n");
-	/* Reset SoC */
-	sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL);
-	/* and call reset vector */
-	f();
-	/* If this fails, halt the CPU */
-	while
-		(1);
-}
-
-static void rtl930x_restart(char *command)
-{
-	pr_info("System restart.\n");
-	sw_w32(0x1, RTL930X_RST_GLB_CTRL_0);
-	while
-		(1);
-}
-
-static void rtl931x_restart(char *command)
-{
-	u32 v;
-
-	pr_info("System restart.\n");
-	sw_w32(1, RTL931X_RST_GLB_CTRL);
-	v = sw_r32(RTL931X_RST_GLB_CTRL);
-	sw_w32(0x101, RTL931X_RST_GLB_CTRL);
-	msleep(15);
-	sw_w32(v, RTL931X_RST_GLB_CTRL);
-	msleep(15);
-	sw_w32(0x101, RTL931X_RST_GLB_CTRL);
-}
-
-static void rtl838x_halt(void)
-{
-	pr_info("System halted.\n");
-	while
-		(1);
-}
-
-static void __init rtl838x_setup(void)
-{
-	pr_info("Registering _machine_restart\n");
-	_machine_restart = rtl838x_restart;
-	_machine_halt = rtl838x_halt;
-
-	/* This PLL value needs to be restored before a reset and will then be
-	 * preserved over a SoC reset. A wrong value prevents the SoC from
-	 * connecting to the SPI flash controller at boot and reading the
-	 * reset routine */
-	pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
-
-	/* Setup System LED. Bit 15 then allows to toggle it */
-	sw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL);
-}
-
-static void __init rtl839x_setup(void)
-{
-	pr_info("Registering _machine_restart\n");
-	_machine_restart = rtl839x_restart;
-	_machine_halt = rtl838x_halt;
-
-	/* Setup System LED. Bit 14 of RTL839X_LED_GLB_CTRL then allows to toggle it */
-	sw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL);
-}
-
-static void __init rtl930x_setup(void)
-{
-	pr_info("Registering _machine_restart\n");
-	_machine_restart = rtl930x_restart;
-	_machine_halt = rtl838x_halt;
-
-	if (soc_info.id == 0x9302)
-		sw_w32_mask(0, 3 << 13, RTL9302_LED_GLB_CTRL);
-	else
-		sw_w32_mask(0, 3 << 13, RTL930X_LED_GLB_CTRL);
-}
-
-static void __init rtl931x_setup(void)
-{
-	pr_info("Registering _machine_restart\n");
-	_machine_restart = rtl931x_restart;
-	_machine_halt = rtl838x_halt;
-	sw_w32_mask(0, 3 << 12, RTL931X_LED_GLB_CTRL);
-}
-
-void __init plat_mem_setup(void)
-{
-	void *dtb;
-
-	set_io_port_base(KSEG1);
-	_machine_restart = rtl838x_restart;
-
-	if (fw_passed_dtb) /* UHI interface */
-		dtb = (void *)fw_passed_dtb;
-	else if (__dtb_start != __dtb_end)
-		dtb = (void *)__dtb_start;
-	else
-		panic("no dtb found");
-
-	/*
-	 * Load the devicetree. This causes the chosen node to be
-	 * parsed resulting in our memory appearing
-	 */
-	__dt_setup_arch(dtb);
-
-	switch (soc_info.family) {
-	case RTL8380_FAMILY_ID:
-		rtl838x_setup();
-		break;
-	case RTL8390_FAMILY_ID:
-		rtl839x_setup();
-		break;
-	case RTL9300_FAMILY_ID:
-		rtl930x_setup();
-		break;
-	case RTL9310_FAMILY_ID:
-		rtl931x_setup();
-		break;
-	}
-}
-
-void __init plat_time_init(void)
-{
-	struct device_node *np;
-	u32 freq = 500000000;
-
-	of_clk_init(NULL);
-	timer_probe();
-
-	np = of_find_node_by_name(NULL, "cpus");
-	if (!np) {
-		pr_err("Missing 'cpus' DT node, using default frequency.");
-	} else {
-		if (of_property_read_u32(np, "frequency", &freq) < 0)
-			pr_err("No 'frequency' property in DT, using default.");
-		else
-			pr_info("CPU frequency from device tree: %dMHz", freq / 1000000);
-		of_node_put(np);
-	}
-
-	mips_hpt_frequency = freq / 2;
-}
diff --git a/target/linux/realtek/files-5.4/drivers/clocksource/timer-rtl9300.c b/target/linux/realtek/files-5.4/drivers/clocksource/timer-rtl9300.c
deleted file mode 100644
index 9ab1733fe3..0000000000
--- a/target/linux/realtek/files-5.4/drivers/clocksource/timer-rtl9300.c
+++ /dev/null
@@ -1,196 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <linux/clockchips.h>
-#include <linux/init.h>
-#include <asm/time.h>
-#include <linux/interrupt.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/sched_clock.h>
-#include "timer-of.h"
-
-#include <mach-rtl83xx.h>
-
-/* 
- * Timer registers
- * the RTL9300/9310 SoCs have 6 timers, each register block 0x10 apart
- */
-#define RTL9300_TC_DATA		0x0
-#define RTL9300_TC_CNT		0x4
-#define RTL9300_TC_CTRL		0x8
-#define RTL9300_TC_CTRL_MODE	BIT(24)
-#define RTL9300_TC_CTRL_EN	BIT(28)
-#define RTL9300_TC_INT		0xc
-#define RTL9300_TC_INT_IP	BIT(16)
-#define RTL9300_TC_INT_IE	BIT(20)
-
-// Clocksource is using timer 0, clock event uses timer 1
-#define TIMER_CLK_SRC		0
-#define TIMER_CLK_EVT		1
-#define TIMER_BLK_EVT		(TIMER_CLK_EVT << 4)
-
-// Timer modes
-#define TIMER_MODE_REPEAT	1
-#define TIMER_MODE_ONCE		0
-
-// Minimum divider is 2
-#define DIVISOR_RTL9300		2
-
-#define N_BITS			28
-
-static void __iomem *rtl9300_sched_reg __read_mostly;
-
-static u64 notrace rtl9300_sched_clock_read(void)
-{
-/*	pr_info("In %s: %x\n", __func__, readl_relaxed(rtl9300_sched_reg));
-	dump_stack();*/
-	return readl_relaxed(rtl9300_sched_reg);
-}
-
-static irqreturn_t rtl9300_timer_interrupt(int irq, void *dev_id)
-{
-	struct clock_event_device *clk = dev_id;
-	struct timer_of *to = to_timer_of(clk);
-	u32 v = readl(timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
-
-	// Acknowledge the IRQ
-	v |= RTL9300_TC_INT_IP;
-	writel(v, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
-
-	clk->event_handler(clk);
-	return IRQ_HANDLED;
-}
-
-static void rtl9300_timer_stop(struct timer_of *to)
-{
-	u32 v;
-
-	writel(0, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_CTRL);
-
-	// Acknowledge possibly pending IRQ
-	v = readl(timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
-	if (v & RTL9300_TC_INT_IP)
-		writel(v, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
-}
-
-static void rtl9300_timer_start(struct timer_of *to, int timer, bool periodic)
-{
-	u32 v = (periodic ? RTL9300_TC_CTRL_MODE : 0) | RTL9300_TC_CTRL_EN | DIVISOR_RTL9300;
-	writel(v, timer_of_base(to) + timer * 0x10 + RTL9300_TC_CTRL);
-}
-
-static int rtl9300_set_next_event(unsigned long delta, struct clock_event_device *clk)
-{
-	struct timer_of *to = to_timer_of(clk);
-
-	rtl9300_timer_stop(to);
-	writel(delta, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA);
-	rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_ONCE);
-	return 0;
-}
-
-static int rtl9300_set_state_periodic(struct clock_event_device *clk)
-{
-	struct timer_of *to = to_timer_of(clk);
-
-	rtl9300_timer_stop(to);
-	writel(to->of_clk.period, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA);
-	rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_REPEAT);
-	return 0;
-}
-
-static int rtl9300_set_state_oneshot(struct clock_event_device *clk)
-{
-	struct timer_of *to = to_timer_of(clk);
-
-	rtl9300_timer_stop(to);
-	writel(to->of_clk.period, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA);
-	rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_ONCE);
-	return 0;
-}
-
-static int rtl9300_set_state_shutdown(struct clock_event_device *clk)
-{
-	struct timer_of *to = to_timer_of(clk);
-
-	rtl9300_timer_stop(to);
-	return 0;
-}
-
-static struct timer_of t_of = {
-	.flags = TIMER_OF_BASE | TIMER_OF_IRQ | TIMER_OF_CLOCK,
-
-	.clkevt = {
-		.name = "rtl9300_timer",
-		.rating = 350,
-		.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-		.set_next_event	= rtl9300_set_next_event,
-		.set_state_oneshot = rtl9300_set_state_oneshot,
-		.set_state_periodic = rtl9300_set_state_periodic,
-		.set_state_shutdown = rtl9300_set_state_shutdown,
-	},
-
-	.of_irq = {
-		.name = "ostimer",
-		.handler = rtl9300_timer_interrupt,
-		.flags = IRQF_TIMER,
-	},
-};
-
-static void __init rtl9300_timer_setup(u8 timer)
-{
-	u32 v;
-
-	// Disable timer
-	writel(0, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_CTRL);
-
-	// Acknowledge possibly pending IRQ
-	v = readl(timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_INT);
-	if (v & RTL9300_TC_INT_IP)
-		writel(v, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_INT);
-
-	// Setup maximum period (for use as clock-source)
-	writel(0x0fffffff, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_DATA);
-}
-
-
-static int __init rtl9300_timer_init(struct device_node *node)
-{
-	int err = 0;
-	unsigned long rate;
-
-	pr_info("%s: setting up timer\n", __func__);
-
-	err = timer_of_init(node, &t_of);
-	if (err)
-		return err;
-
-	rate = timer_of_rate(&t_of) / DIVISOR_RTL9300;
-	pr_info("Frequency in dts: %ld, my rate is %ld, period %ld\n",
-		timer_of_rate(&t_of), rate, timer_of_period(&t_of));
-	pr_info("With base %08x IRQ: %d\n", (u32)timer_of_base(&t_of), timer_of_irq(&t_of));
-
-	// Configure clock source and register it for scheduling
-	rtl9300_timer_setup(TIMER_CLK_SRC);
-	rtl9300_timer_start(&t_of, TIMER_CLK_SRC, TIMER_MODE_REPEAT);
-
-	rtl9300_sched_reg = timer_of_base(&t_of) + TIMER_CLK_SRC * 0x10 + RTL9300_TC_CNT;
-
-	err = clocksource_mmio_init(rtl9300_sched_reg, node->name, rate , 100, N_BITS,
-				    clocksource_mmio_readl_up);
-	if (err)
-		return err;
-
-	sched_clock_register(rtl9300_sched_clock_read, N_BITS, rate);
-
-	// Configure clock event source
-	rtl9300_timer_setup(TIMER_CLK_EVT);
-	clockevents_config_and_register(&t_of.clkevt, rate, 100, 0x0fffffff);
-
-	// Enable interrupt
-	writel(RTL9300_TC_INT_IE, timer_of_base(&t_of) + TIMER_BLK_EVT + RTL9300_TC_INT);
-
-	return err;
-}
-
-TIMER_OF_DECLARE(rtl9300_timer, "realtek,rtl9300-timer", rtl9300_timer_init);
diff --git a/target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl8231.c b/target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl8231.c
deleted file mode 100644
index f4f5621e0c..0000000000
--- a/target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl8231.c
+++ /dev/null
@@ -1,342 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <linux/gpio/driver.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <asm/mach-rtl838x/mach-rtl83xx.h>
-
-/* RTL8231 registers for LED control */
-#define RTL8231_LED_FUNC0			0x0000
-#define RTL8231_GPIO_PIN_SEL(gpio)		((0x0002) + ((gpio) >> 4))
-#define RTL8231_GPIO_DIR(gpio)			((0x0005) + ((gpio) >> 4))
-#define RTL8231_GPIO_DATA(gpio)			((0x001C) + ((gpio) >> 4))
-
-#define USEC_TIMEOUT 5000
-
-struct rtl8231_gpios {
-	struct gpio_chip gc;
-	struct device *dev;
-	u32 id;
-	int smi_bus_id;
-	u16 reg_shadow[0x20];
-	u32 reg_cached;
-	int ext_gpio_indrt_access;
-};
-
-extern struct mutex smi_lock;
-extern struct rtl83xx_soc_info soc_info;
-
-static u32 rtl8231_read(struct rtl8231_gpios *gpios, u32 reg)
-{
-	u32 t = 0, n = 0;
-	u8 bus_id = gpios->smi_bus_id;
-
-	reg &= 0x1f;
-	bus_id &= 0x1f;
-
-	/* Calculate read register address */
-	t = (bus_id << 2) | (reg << 7);
-
-	/* Set execution bit: cleared when operation completed */
-	t |= 1;
-
-	// Start execution
-	sw_w32(t, gpios->ext_gpio_indrt_access);
-	do {
-		udelay(1);
-		t = sw_r32(gpios->ext_gpio_indrt_access);
-		n++;
-	} while ((t & 1) && (n < USEC_TIMEOUT));
-
-	if (n >= USEC_TIMEOUT)
-		return 0x80000000;
-	
-	pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, (t & 0xffff0000) >> 16);
-
-	return (t & 0xffff0000) >> 16;
-}
-
-static int rtl8231_write(struct rtl8231_gpios *gpios, u32 reg, u32 data)
-{
-	u32 t = 0, n = 0;
-	u8 bus_id = gpios->smi_bus_id;
-
-	pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, data);
-	reg &= 0x1f;
-	bus_id &= 0x1f;
-
-	t = (bus_id << 2) | (reg << 7) | (data << 16);
-	/* Set write bit */
-	t |= 2;
-
-	/* Set execution bit: cleared when operation completed */
-	t |= 1;
-
-	// Start execution
-	sw_w32(t, gpios->ext_gpio_indrt_access);
-	do {
-		udelay(1);
-		t = sw_r32(gpios->ext_gpio_indrt_access);
-	} while ((t & 1) && (n < USEC_TIMEOUT));
-
-	if (n >= USEC_TIMEOUT)
-		return -1;
-
-	return 0;
-}
-
-static u32 rtl8231_read_cached(struct rtl8231_gpios *gpios, u32 reg)
-{
-	if (reg > 0x1f)
-		return 0;
-
-	if (gpios->reg_cached & (1 << reg))
-		return gpios->reg_shadow[reg];
-
-	return rtl8231_read(gpios, reg);
-}
-
-/* Set Direction of the RTL8231 pin:
- * dir 1: input
- * dir 0: output
- */
-static int rtl8231_pin_dir(struct rtl8231_gpios *gpios, u32 gpio, u32 dir)
-{
-	u32 v;
-	int pin_sel_addr = RTL8231_GPIO_PIN_SEL(gpio);
-	int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
-	int dpin = gpio % 16;
-
-	if (gpio > 31) {
-		pr_debug("WARNING: HIGH pin\n");
-		dpin += 5;
-		pin_dir_addr = pin_sel_addr;
-	}
-
-	v = rtl8231_read_cached(gpios, pin_dir_addr);
-	if (v & 0x80000000) {
-		pr_err("Error reading RTL8231\n");
-		return -1;
-	}
-
-	v = (v & ~(1 << dpin)) | (dir << dpin);
-	rtl8231_write(gpios, pin_dir_addr, v);
-	gpios->reg_shadow[pin_dir_addr] = v;
-	gpios->reg_cached |= 1 << pin_dir_addr;
-	return 0;
-}
-
-static int rtl8231_pin_dir_get(struct rtl8231_gpios *gpios, u32 gpio, u32 *dir)
-{
-	/* dir 1: input
-	 * dir 0: output
-	 */
-
-	u32  v;
-	int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
-	int pin = gpio % 16;
-
-	if (gpio > 31) {
-		pin_dir_addr = RTL8231_GPIO_PIN_SEL(gpio);
-		pin += 5;
-	}
-
-	v = rtl8231_read(gpios, pin_dir_addr);
-	if (v & (1 << pin))
-		*dir = 1;
-	else
-		*dir = 0;
-	return 0;
-}
-
-static int rtl8231_pin_set(struct rtl8231_gpios *gpios, u32 gpio, u32 data)
-{
-	u32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio));
-
-	pr_debug("%s: %d to %d\n", __func__, gpio, data);
-	if (v & 0x80000000) {
-		pr_err("Error reading RTL8231\n");
-		return -1;
-	}
-	v = (v & ~(1 << (gpio % 16))) | (data << (gpio % 16));
-	rtl8231_write(gpios, RTL8231_GPIO_DATA(gpio), v);
-	gpios->reg_shadow[RTL8231_GPIO_DATA(gpio)] = v;
-	gpios->reg_cached |= 1 << RTL8231_GPIO_DATA(gpio);
-	return 0;
-}
-
-static int rtl8231_pin_get(struct rtl8231_gpios *gpios, u32 gpio, u16 *state)
-{
-	u32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio));
-
-	if (v & 0x80000000) {
-		pr_err("Error reading RTL8231\n");
-		return -1;
-	}
-
-	*state = v & 0xffff;
-	return 0;
-}
-
-static int rtl8231_direction_input(struct gpio_chip *gc, unsigned int offset)
-{
-	int err;
-	struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
-
-	pr_debug("%s: %d\n", __func__, offset);
-	mutex_lock(&smi_lock);
-	err = rtl8231_pin_dir(gpios, offset, 1);
-	mutex_unlock(&smi_lock);
-	return err;
-}
-
-static int rtl8231_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
-{
-	int err;
-	struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
-
-	pr_debug("%s: %d\n", __func__, offset);
-	mutex_lock(&smi_lock);
-	err = rtl8231_pin_dir(gpios, offset, 0);
-	mutex_unlock(&smi_lock);
-	if (!err)
-		err = rtl8231_pin_set(gpios, offset, value);
-	return err;
-}
-
-static int rtl8231_get_direction(struct gpio_chip *gc, unsigned int offset)
-{
-	u32 v = 0;
-	struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
-
-	pr_debug("%s: %d\n", __func__, offset);
-	mutex_lock(&smi_lock);
-	rtl8231_pin_dir_get(gpios, offset, &v);
-	mutex_unlock(&smi_lock);
-	return v;
-}
-
-static int rtl8231_gpio_get(struct gpio_chip *gc, unsigned int offset)
-{
-	u16 state = 0;
-	struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
-
-	mutex_lock(&smi_lock);
-	rtl8231_pin_get(gpios, offset, &state);
-	mutex_unlock(&smi_lock);
-	if (state & (1 << (offset % 16)))
-		return 1;
-	return 0;
-}
-
-void rtl8231_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
-{
-	struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
-
-	rtl8231_pin_set(gpios, offset, value);
-}
-
-int rtl8231_init(struct rtl8231_gpios *gpios)
-{
-	pr_info("%s called, MDIO bus ID: %d\n", __func__, gpios->smi_bus_id);
-
-	gpios->reg_cached = 0;
-
-	if (soc_info.family == RTL8390_FAMILY_ID) {
-		// RTL8390: Enable external gpio in global led control register
-		sw_w32_mask(0x7 << 18, 0x4 << 18, RTL839X_LED_GLB_CTRL);
-	} else if (soc_info.family == RTL8380_FAMILY_ID) {
-		// RTL8380: Enable RTL8231 indirect access mode
-		sw_w32_mask(0, 1, RTL838X_EXTRA_GPIO_CTRL);
-		sw_w32_mask(3, 1, RTL838X_DMY_REG5);
-	}
-
-	/* Select GPIO functionality and force input direction for pins 0-36 */
-	rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(0), 0xffff);
-	rtl8231_write(gpios, RTL8231_GPIO_DIR(0), 0xffff);
-	rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(16), 0xffff);
-	rtl8231_write(gpios, RTL8231_GPIO_DIR(16), 0xffff);
-	rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(32), 0x03ff);
-
-	/* Set LED_Start to enable drivers for output mode */
-	rtl8231_write(gpios, RTL8231_LED_FUNC0, 1 << 1);
-
-	return 0;
-}
-
-static const struct of_device_id rtl8231_gpio_of_match[] = {
-	{ .compatible = "realtek,rtl8231-gpio" },
-	{},
-};
-
-MODULE_DEVICE_TABLE(of, rtl8231_gpio_of_match);
-
-static int rtl8231_gpio_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct device_node *np = dev->of_node;
-	struct rtl8231_gpios *gpios;
-	int err;
-	u32 indirect_bus_id;
-
-	pr_info("Probing RTL8231 GPIOs\n");
-
-	if (!np) {
-		dev_err(&pdev->dev, "No DT found\n");
-		return -EINVAL;
-	}
-
-	gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL);
-	if (!gpios)
-		return -ENOMEM;
-
-	gpios->id = soc_info.id;
-	if (soc_info.family == RTL8380_FAMILY_ID) {
-		gpios->ext_gpio_indrt_access = RTL838X_EXT_GPIO_INDRT_ACCESS;
-	}
-
-	if (soc_info.family == RTL8390_FAMILY_ID) {
-		gpios->ext_gpio_indrt_access = RTL839X_EXT_GPIO_INDRT_ACCESS;
-	}
-
-	/*
-	 * We use a default MDIO bus ID for the 8231 of 0, which can be overriden
-	 * by the indirect-access-bus-id property in the dts.
-	 */
-	gpios->smi_bus_id = 0;
-	of_property_read_u32(np, "indirect-access-bus-id", &indirect_bus_id);
-	gpios->smi_bus_id = indirect_bus_id;
-
-	rtl8231_init(gpios);
-
-	gpios->dev = dev;
-	gpios->gc.base = 160;
-	gpios->gc.ngpio = 36;
-	gpios->gc.label = "rtl8231";
-	gpios->gc.parent = dev;
-	gpios->gc.owner = THIS_MODULE;
-	gpios->gc.can_sleep = true;
-
-	gpios->gc.direction_input = rtl8231_direction_input;
-	gpios->gc.direction_output = rtl8231_direction_output;
-	gpios->gc.set = rtl8231_gpio_set;
-	gpios->gc.get = rtl8231_gpio_get;
-	gpios->gc.get_direction = rtl8231_get_direction;
-
-	err = devm_gpiochip_add_data(dev, &gpios->gc, gpios);
-	return err;
-}
-
-static struct platform_driver rtl8231_gpio_driver = {
-	.driver = {
-		.name = "rtl8231-gpio",
-		.of_match_table	= rtl8231_gpio_of_match,
-	},
-	.probe = rtl8231_gpio_probe,
-};
-
-module_platform_driver(rtl8231_gpio_driver);
-
-MODULE_DESCRIPTION("Realtek RTL8231 GPIO expansion chip support");
-MODULE_LICENSE("GPL v2");
diff --git a/target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl838x.c b/target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl838x.c
deleted file mode 100644
index 8207e4bb73..0000000000
--- a/target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl838x.c
+++ /dev/null
@@ -1,425 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <linux/gpio/driver.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <asm/mach-rtl838x/mach-rtl83xx.h>
-
-/* RTL8231 registers for LED control */
-#define RTL8231_LED_FUNC0			0x0000
-#define RTL8231_GPIO_PIN_SEL(gpio)		((0x0002) + ((gpio) >> 4))
-#define RTL8231_GPIO_DIR(gpio)			((0x0005) + ((gpio) >> 4))
-#define RTL8231_GPIO_DATA(gpio)			((0x001C) + ((gpio) >> 4))
-
-struct rtl838x_gpios {
-	struct gpio_chip gc;
-	u32 id;
-	struct device *dev;
-	int irq;
-	int num_leds;
-	int min_led;
-	int leds_per_port;
-	u32 led_mode;
-	int led_glb_ctrl;
-	int led_sw_ctrl;
-	int (*led_sw_p_ctrl)(int port);
-	int (*led_sw_p_en_ctrl)(int port);
-	int (*ext_gpio_dir)(int i);
-	int (*ext_gpio_data)(int i);
-};
-
-inline int rtl838x_ext_gpio_dir(int i)
-{
-	return RTL838X_EXT_GPIO_DIR + ((i >>5) << 2);
-}
-
-inline int rtl839x_ext_gpio_dir(int i)
-{
-	return RTL839X_EXT_GPIO_DIR + ((i >>5) << 2);
-}
-
-inline int rtl838x_ext_gpio_data(int i)
-{
-	return RTL838X_EXT_GPIO_DATA + ((i >>5) << 2);
-}
-
-inline int rtl839x_ext_gpio_data(int i)
-{
-	return RTL839X_EXT_GPIO_DATA + ((i >>5) << 2);
-}
-
-inline int rtl838x_led_sw_p_ctrl(int p)
-{
-	return RTL838X_LED_SW_P_CTRL + (p << 2);
-}
-
-inline int rtl839x_led_sw_p_ctrl(int p)
-{
-	return RTL839X_LED_SW_P_CTRL + (p << 2);
-}
-
-inline int rtl838x_led_sw_p_en_ctrl(int p)
-{
-	return RTL838X_LED_SW_P_EN_CTRL + ((p / 10) << 2);
-}
-
-inline int rtl839x_led_sw_p_en_ctrl(int p)
-{
-	return RTL839X_LED_SW_P_EN_CTRL + ((p / 10) << 2);
-}
-
-extern struct mutex smi_lock;
-extern struct rtl83xx_soc_info soc_info;
-
-
-void rtl838x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
-{
-	int bit;
-	struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
-
-	pr_debug("rtl838x_set: %d, value: %d\n", offset, value);
-	/* Internal GPIO of the RTL8380 */
-	if (offset < 32) {
-		if (value)
-			rtl83xx_w32_mask(0, BIT(offset), RTL838X_GPIO_PABC_DATA);
-		else
-			rtl83xx_w32_mask(BIT(offset), 0, RTL838X_GPIO_PABC_DATA);
-	}
-
-	/* LED driver for PWR and SYS */
-	if (offset >= 32 && offset < 64) {
-		bit = offset - 32;
-		if (value)
-			sw_w32_mask(0, BIT(bit), gpios->led_glb_ctrl);
-		else
-			sw_w32_mask(BIT(bit), 0, gpios->led_glb_ctrl);
-		return;
-	}
-
-	bit = (offset - 64) % 32;
-	/* First Port-LED */
-	if (offset >= 64 && offset < 96
-	   && offset >= (64 + gpios->min_led)
-	   && offset < (64 + gpios->min_led + gpios->num_leds)) {
-		if (value)
-			sw_w32_mask(7, 5, gpios->led_sw_p_ctrl(bit));
-		else
-			sw_w32_mask(7, 0, gpios->led_sw_p_ctrl(bit));
-	}
-	if (offset >= 96 && offset < 128
-	    && offset >= (96 + gpios->min_led)
-	    && offset < (96 + gpios->min_led + gpios->num_leds)) {
-		if (value)
-			sw_w32_mask(7 << 3, 5 << 3, gpios->led_sw_p_ctrl(bit));
-		else
-			sw_w32_mask(7 << 3, 0, gpios->led_sw_p_ctrl(bit));
-	}
-	if (offset >= 128 && offset < 160
-	    && offset >= (128 + gpios->min_led)
-	    && offset < (128 + gpios->min_led + gpios->num_leds)) {
-		if (value)
-			sw_w32_mask(7 << 6, 5 << 6, gpios->led_sw_p_ctrl(bit));
-		else
-			sw_w32_mask(7 << 6, 0, gpios->led_sw_p_ctrl(bit));
-	}
-	__asm__ volatile ("sync");
-}
-
-static int rtl838x_direction_input(struct gpio_chip *gc, unsigned int offset)
-{
-	pr_debug("%s: %d\n", __func__, offset);
-
-	if (offset < 32) {
-		rtl83xx_w32_mask(BIT(offset), 0, RTL838X_GPIO_PABC_DIR);
-		return 0;
-	}
-
-	/* Internal LED driver does not support input */
-	return -ENOTSUPP;
-}
-
-static int rtl838x_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
-{
-	pr_debug("%s: %d\n", __func__, offset);
-	if (offset < 32)
-		rtl83xx_w32_mask(0, BIT(offset), RTL838X_GPIO_PABC_DIR);
-	rtl838x_gpio_set(gc, offset, value);
-
-	/* LED for PWR and SYS driver is direction output by default */
-	return 0;
-}
-
-static int rtl838x_get_direction(struct gpio_chip *gc, unsigned int offset)
-{
-	u32 v = 0;
-
-	pr_debug("%s: %d\n", __func__, offset);
-	if (offset < 32) {
-		v = rtl83xx_r32(RTL838X_GPIO_PABC_DIR);
-		if (v & BIT(offset))
-			return 0;
-		return 1;
-	}
-
-	/* LED driver for PWR and SYS is direction output by default */
-	if (offset >= 32 && offset < 64)
-		return 0;
-
-	return 0;
-}
-
-static int rtl838x_gpio_get(struct gpio_chip *gc, unsigned int offset)
-{
-	u32 v;
-	struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
-
-	pr_debug("%s: %d\n", __func__, offset);
-
-	/* Internal GPIO of the RTL8380 */
-	if (offset < 32) {
-		v = rtl83xx_r32(RTL838X_GPIO_PABC_DATA);
-		if (v & BIT(offset))
-			return 1;
-		return 0;
-	}
-
-	/* LED driver for PWR and SYS */
-	if (offset >= 32 && offset < 64) {
-		v = sw_r32(gpios->led_glb_ctrl);
-		if (v & BIT(offset-32))
-			return 1;
-		return 0;
-	}
-
-/* BUG:
-	bit = (offset - 64) % 32;
-	if (offset >= 64 && offset < 96) {
-		if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & BIT(bit))
-			return 1;
-		return 0;
-	}
-	if (offset >= 96 && offset < 128) {
-		if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & BIT(bit))
-			return 1;
-		return 0;
-	}
-	if (offset >= 128 && offset < 160) {
-		if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & BIT(bit))
-			return 1;
-		return 0;
-	}
-	*/ 
-	return 0;
-}
-
-void rtl8380_led_test(struct rtl838x_gpios *gpios, u32 mask)
-{
-	int i;
-	u32 led_gbl = sw_r32(gpios->led_glb_ctrl);
-	u32 mode_sel, led_p_en;
-
-	if (soc_info.family == RTL8380_FAMILY_ID) {
-		mode_sel = sw_r32(RTL838X_LED_MODE_SEL);
-		led_p_en = sw_r32(RTL838X_LED_P_EN_CTRL);
-	}
-
-	/* 2 Leds for ports 0-23 and 24-27, 3 would be 0x7 */
-	sw_w32_mask(0x3f, 0x3 | (0x3 << 3), gpios->led_glb_ctrl);
-
-	if(soc_info.family == RTL8380_FAMILY_ID) {
-		/* Enable all leds */
-		sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL);
-	}
-	/* Enable software control of all leds */
-	sw_w32(0xFFFFFFF, gpios->led_sw_ctrl);
-	sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(0));
-	sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(10));
-	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(20));
-
-	for (i = 0; i < 28; i++) {
-		if (mask & BIT(i))
-			sw_w32(5 | (5 << 3) | (5 << 6), gpios->led_sw_p_ctrl(i));
-	}
-	msleep(3000);
-
-	if (soc_info.family == RTL8380_FAMILY_ID)
-		sw_w32(led_p_en, RTL838X_LED_P_EN_CTRL);
-	/* Disable software control of all leds */
-	sw_w32(0x0000000, gpios->led_sw_ctrl);
-	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(0));
-	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(10));
-	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(20));
-
-	sw_w32(led_gbl, gpios->led_glb_ctrl);
-	if (soc_info.family == RTL8380_FAMILY_ID)
-		sw_w32(mode_sel, RTL838X_LED_MODE_SEL);
-}
-
-void take_port_leds(struct rtl838x_gpios *gpios)
-{
-	int leds_per_port = gpios->leds_per_port;
-	int mode = gpios->led_mode;
-
-	pr_info("%s, %d, %x\n", __func__, leds_per_port, mode);
-	pr_debug("Bootloader settings: %x %x %x\n",
-		sw_r32(gpios->led_sw_p_en_ctrl(0)),
-		sw_r32(gpios->led_sw_p_en_ctrl(10)),
-		sw_r32(gpios->led_sw_p_en_ctrl(20))
-	);
-
-	if (soc_info.family == RTL8380_FAMILY_ID) {
-		pr_debug("led glb: %x, sel %x\n",
-			sw_r32(gpios->led_glb_ctrl), sw_r32(RTL838X_LED_MODE_SEL));
-		pr_debug("RTL838X_LED_P_EN_CTRL: %x", sw_r32(RTL838X_LED_P_EN_CTRL));
-		pr_debug("RTL838X_LED_MODE_CTRL: %x", sw_r32(RTL838X_LED_MODE_CTRL));
-		sw_w32_mask(3, 0, RTL838X_LED_MODE_SEL);
-		sw_w32(mode, RTL838X_LED_MODE_CTRL);
-	}
-
-	/* Enable software control of all leds */
-	sw_w32(0xFFFFFFF, gpios->led_sw_ctrl);
-	if (soc_info.family == RTL8380_FAMILY_ID)
-		sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL);
-
-	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(0));
-	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(10));
-	sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(20));
-
-	sw_w32_mask(0x3f, 0, gpios->led_glb_ctrl);
-	switch (leds_per_port) {
-	case 3:
-		sw_w32_mask(0, 0x7 | (0x7 << 3), gpios->led_glb_ctrl);
-		sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(20));
-		/* FALLTHRU */
-	case 2:
-		sw_w32_mask(0, 0x3 | (0x3 << 3), gpios->led_glb_ctrl);
-		sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(10));
-		/* FALLTHRU */
-	case 1:
-		sw_w32_mask(0, 0x1 | (0x1 << 3), gpios->led_glb_ctrl);
-		sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(0));
-		break;
-	default:
-		pr_err("No LEDS configured for software control\n");
-	}
-}
-
-static const struct of_device_id rtl838x_gpio_of_match[] = {
-	{ .compatible = "realtek,rtl838x-gpio" },
-	{},
-};
-
-MODULE_DEVICE_TABLE(of, rtl838x_gpio_of_match);
-
-static int rtl838x_gpio_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct device_node *np = dev->of_node;
-	struct rtl838x_gpios *gpios;
-	int err;
-
-	pr_info("Probing RTL838X GPIOs\n");
-
-	if (!np) {
-		dev_err(&pdev->dev, "No DT found\n");
-		return -EINVAL;
-	}
-
-	gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL);
-	if (!gpios)
-		return -ENOMEM;
-
-	gpios->id = soc_info.id;
-
-	switch (gpios->id) {
-	case 0x8332:
-		pr_debug("Found RTL8332M GPIO\n");
-		break;
-	case 0x8380:
-		pr_debug("Found RTL8380M GPIO\n");
-		break;
-	case 0x8381:
-		pr_debug("Found RTL8381M GPIO\n");
-		break;
-	case 0x8382:
-		pr_debug("Found RTL8382M GPIO\n");
-		break;
-	case 0x8391:
-		pr_debug("Found RTL8391 GPIO\n");
-		break;
-	case 0x8393:
-		pr_debug("Found RTL8393 GPIO\n");
-		break;
-	default:
-		pr_err("Unknown GPIO chip id (%04x)\n", gpios->id);
-		return -ENODEV;
-	}
-
-	if (soc_info.family == RTL8380_FAMILY_ID) {
-		gpios->led_glb_ctrl = RTL838X_LED_GLB_CTRL;
-		gpios->led_sw_ctrl = RTL838X_LED_SW_CTRL;
-		gpios->led_sw_p_ctrl = rtl838x_led_sw_p_ctrl;
-		gpios->led_sw_p_en_ctrl = rtl838x_led_sw_p_en_ctrl;
-		gpios->ext_gpio_dir = rtl838x_ext_gpio_dir;
-		gpios->ext_gpio_data = rtl838x_ext_gpio_data;
-	}
-
-	if (soc_info.family == RTL8390_FAMILY_ID) {
-		gpios->led_glb_ctrl = RTL839X_LED_GLB_CTRL;
-		gpios->led_sw_ctrl = RTL839X_LED_SW_CTRL;
-		gpios->led_sw_p_ctrl = rtl839x_led_sw_p_ctrl;
-		gpios->led_sw_p_en_ctrl = rtl839x_led_sw_p_en_ctrl;
-		gpios->ext_gpio_dir = rtl839x_ext_gpio_dir;
-		gpios->ext_gpio_data = rtl839x_ext_gpio_data;
-	}
-
-	gpios->dev = dev;
-	gpios->gc.base = 0;
-	/* 0-31: internal
-	 * 32-63, LED control register
-	 * 64-95: PORT-LED 0
-	 * 96-127: PORT-LED 1
-	 * 128-159: PORT-LED 2
-	 */
-	gpios->gc.ngpio = 160;
-	gpios->gc.label = "rtl838x";
-	gpios->gc.parent = dev;
-	gpios->gc.owner = THIS_MODULE;
-	gpios->gc.can_sleep = true;
-	gpios->irq = 31;
-
-	gpios->gc.direction_input = rtl838x_direction_input;
-	gpios->gc.direction_output = rtl838x_direction_output;
-	gpios->gc.set = rtl838x_gpio_set;
-	gpios->gc.get = rtl838x_gpio_get;
-	gpios->gc.get_direction = rtl838x_get_direction;
-
-	if (of_property_read_bool(np, "take-port-leds")) {
-		if (of_property_read_u32(np, "leds-per-port", &gpios->leds_per_port))
-			gpios->leds_per_port = 2;
-		if (of_property_read_u32(np, "led-mode", &gpios->led_mode))
-			gpios->led_mode = (0x1ea << 15) | 0x1ea;
-		if (of_property_read_u32(np, "num-leds", &gpios->num_leds))
-			gpios->num_leds = 32;
-		if (of_property_read_u32(np, "min-led", &gpios->min_led))
-			gpios->min_led = 0;
-		take_port_leds(gpios);
-	}
-
-	err = devm_gpiochip_add_data(dev, &gpios->gc, gpios);
-	return err;
-}
-
-static struct platform_driver rtl838x_gpio_driver = {
-	.driver = {
-		.name = "rtl838x-gpio",
-		.of_match_table	= rtl838x_gpio_of_match,
-	},
-	.probe = rtl838x_gpio_probe,
-};
-
-module_platform_driver(rtl838x_gpio_driver);
-
-MODULE_DESCRIPTION("Realtek RTL838X GPIO API support");
-MODULE_LICENSE("GPL v2");
diff --git a/target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c b/target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c
deleted file mode 100644
index 35bf53ea5a..0000000000
--- a/target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c
+++ /dev/null
@@ -1,603 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <linux/device.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/spi-nor.h>
-
-#include "rtl838x-spi.h"
-#include <asm/mach-rtl838x/mach-rtl83xx.h>
-
-extern struct rtl83xx_soc_info soc_info;
-
-struct rtl838x_nor {
-	struct spi_nor nor;
-	struct device *dev;
-	volatile void __iomem *base;
-	bool fourByteMode;
-	u32 chipSize;
-	uint32_t flags;
-	uint32_t io_status;
-};
-
-static uint32_t spi_prep(struct rtl838x_nor *rtl838x_nor)
-{
-	/* Needed because of MMU constraints */
-	SPI_WAIT_READY;
-	spi_w32w(SPI_CS_INIT, SFCSR);	//deactivate CS0, CS1
-	spi_w32w(0, SFCSR);		//activate CS0,CS1
-	spi_w32w(SPI_CS_INIT, SFCSR);	//deactivate CS0, CS1
-
-	return (CS0 & rtl838x_nor->flags) ? (SPI_eCS0 & SPI_LEN_INIT)
-			: ((SPI_eCS1 & SPI_LEN_INIT) | SFCSR_CHIP_SEL);
-}
-
-static uint32_t rtl838x_nor_get_SR(struct rtl838x_nor *rtl838x_nor)
-{
-	uint32_t sfcsr, sfdr;
-
-	sfcsr = spi_prep(rtl838x_nor);
-	sfdr  = (SPINOR_OP_RDSR)<<24;
-
-	pr_debug("%s: rdid,sfcsr_val = %.8x,SFDR = %.8x\n", __func__, sfcsr, sfdr);
-	pr_debug("rdid,sfcsr = %.8x\n", sfcsr | SPI_LEN4);
-	spi_w32w(sfcsr, SFCSR);
-	spi_w32w(sfdr, SFDR);
-	spi_w32_mask(0, SPI_LEN4, SFCSR);
-	SPI_WAIT_READY;
-
-	return spi_r32(SFDR);
-}
-
-static void spi_write_disable(struct rtl838x_nor *rtl838x_nor)
-{
-	uint32_t sfcsr, sfdr;
-
-	sfcsr = spi_prep(rtl838x_nor);
-	sfdr = (SPINOR_OP_WRDI) << 24;
-	spi_w32w(sfcsr, SFCSR);
-	spi_w32w(sfdr, SFDR);
-	pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
-
-	spi_prep(rtl838x_nor);
-}
-
-static void spi_write_enable(struct rtl838x_nor *rtl838x_nor)
-{
-	uint32_t sfcsr, sfdr;
-
-	sfcsr = spi_prep(rtl838x_nor);
-	sfdr = (SPINOR_OP_WREN) << 24;
-	spi_w32w(sfcsr, SFCSR);
-	spi_w32w(sfdr, SFDR);
-	pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
-
-	spi_prep(rtl838x_nor);
-}
-
-static void spi_4b_set(struct rtl838x_nor *rtl838x_nor, bool enable)
-{
-	uint32_t sfcsr, sfdr;
-
-	sfcsr = spi_prep(rtl838x_nor);
-	if (enable)
-		sfdr = (SPINOR_OP_EN4B) << 24;
-	else
-		sfdr = (SPINOR_OP_EX4B) << 24;
-
-	spi_w32w(sfcsr, SFCSR);
-	spi_w32w(sfdr, SFDR);
-	pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
-
-	spi_prep(rtl838x_nor);
-}
-
-static int rtl838x_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
-{
-	int res = 3;
-	u32 reg;
-
-	sw_w32(0x3, RTL838X_INT_RW_CTRL);
-	if (!sw_r32(RTL838X_EXT_VERSION)) {
-		if (sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
-			res = 4;
-	} else {
-		reg = sw_r32(RTL838X_PLL_CML_CTRL);
-		if ((reg & (1 << 30)) && (reg & (1 << 31)))
-			res = 4;
-		if ((!(reg & (1 << 30)))
-		     && sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
-			res = 4;
-	}
-	sw_w32(0x0, RTL838X_INT_RW_CTRL);
-	return res;
-}
-
-static int rtl8390_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
-{
-	if (spi_r32(RTL8390_SOC_SPI_MMIO_CONF) & (1 << 9))
-		return 4;
-	return 3;
-}
-
-ssize_t rtl838x_do_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
-			       size_t length, u_char *buffer, uint8_t command)
-{
-	uint32_t sfcsr, sfdr;
-	uint32_t len = length;
-
-	sfcsr = spi_prep(rtl838x_nor);
-	sfdr = command << 24;
-
-	/* Perform SPINOR_OP_READ: 1 byte command & 3 byte addr*/
-	sfcsr |= SPI_LEN4;
-	sfdr |= from;
-
-	spi_w32w(sfcsr, SFCSR);
-	spi_w32w(sfdr, SFDR);
-
-	/* Read Data, 4 bytes at a time */
-	while (length >= 4) {
-		SPI_WAIT_READY;
-		*((uint32_t *) buffer) = spi_r32(SFDR);
-		buffer += 4;
-		length -= 4;
-	}
-
-	/* The rest needs to be read 1 byte a time */
-	sfcsr &= SPI_LEN_INIT|SPI_LEN1;
-	SPI_WAIT_READY;
-	spi_w32w(sfcsr, SFCSR);
-	while (length > 0) {
-		SPI_WAIT_READY;
-		*(buffer) = spi_r32(SFDR) >> 24;
-		buffer++;
-		length--;
-	}
-	return len;
-}
-
-/*
- * Do fast read in 3 or 4 Byte addressing mode
- */
-static ssize_t rtl838x_do_4bf_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
-			       size_t length, u_char *buffer, uint8_t command)
-{
-	int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
-	int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
-	uint32_t sfcsr;
-	uint32_t len = length;
-
-	pr_debug("Fast read from %llx, len %x, shift %d\n",
-		 from, sfcsr_addr_len, sfdr_addr_shift);
-	sfcsr = spi_prep(rtl838x_nor);
-
-	/* Send read command */
-	spi_w32w(sfcsr | SPI_LEN1, SFCSR);
-	spi_w32w(command << 24, SFDR);
-
-	/* Send address */
-	spi_w32w(sfcsr | (sfcsr_addr_len << 28), SFCSR);
-	spi_w32w(from << sfdr_addr_shift, SFDR);
-
-	/* Dummy cycles */
-	spi_w32w(sfcsr | SPI_LEN1, SFCSR);
-	spi_w32w(0, SFDR);
-
-	/* Start reading */
-	spi_w32w(sfcsr | SPI_LEN4, SFCSR);
-
-	/* Read Data, 4 bytes at a time */
-	while (length >= 4) {
-		SPI_WAIT_READY;
-		*((uint32_t *) buffer) = spi_r32(SFDR);
-		buffer += 4;
-		length -= 4;
-	}
-
-	/* The rest needs to be read 1 byte a time */
-	sfcsr &= SPI_LEN_INIT|SPI_LEN1;
-	SPI_WAIT_READY;
-	spi_w32w(sfcsr, SFCSR);
-	while (length > 0) {
-		SPI_WAIT_READY;
-		*(buffer) = spi_r32(SFDR) >> 24;
-		buffer++;
-		length--;
-	}
-	return len;
-
-}
-
-/*
- * Do write (Page Programming) in 3 or 4 Byte addressing mode
- */
-static ssize_t rtl838x_do_4b_write(struct rtl838x_nor *rtl838x_nor, loff_t to,
-				    size_t length, const u_char *buffer,
-				    uint8_t command)
-{
-	int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
-	int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
-	uint32_t sfcsr;
-	uint32_t len = length;
-
-	pr_debug("Write to %llx, len %x, shift %d\n",
-		 to, sfcsr_addr_len, sfdr_addr_shift);
-	sfcsr = spi_prep(rtl838x_nor);
-
-	/* Send write command, command IO-width is 1 (bit 25/26) */
-	spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
-	spi_w32w(command << 24, SFDR);
-
-	/* Send address */
-	spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
-	spi_w32w(to << sfdr_addr_shift, SFDR);
-
-	/* Write Data, 1 byte at a time, if we are not 4-byte aligned */
-	if (((long)buffer) % 4) {
-		spi_w32w(sfcsr | SPI_LEN1, SFCSR);
-		while (length > 0 && (((long)buffer) % 4)) {
-			SPI_WAIT_READY;
-			spi_w32(*(buffer) << 24, SFDR);
-			buffer += 1;
-			length -= 1;
-		}
-	}
-
-	/* Now we can write 4 bytes at a time */
-	SPI_WAIT_READY;
-	spi_w32w(sfcsr | SPI_LEN4, SFCSR);
-	while (length >= 4) {
-		SPI_WAIT_READY;
-		spi_w32(*((uint32_t *)buffer), SFDR);
-		buffer += 4;
-		length -= 4;
-	}
-
-	/* Final bytes might need to be written 1 byte at a time, again */
-	SPI_WAIT_READY;
-	spi_w32w(sfcsr | SPI_LEN1, SFCSR);
-	while (length > 0) {
-		SPI_WAIT_READY;
-		spi_w32(*(buffer) << 24, SFDR);
-		buffer++;
-		length--;
-	}
-	return len;
-}
-
-static ssize_t rtl838x_nor_write(struct spi_nor *nor, loff_t to, size_t len,
-				 const u_char *buffer)
-{
-	int ret = 0;
-	uint32_t offset = 0;
-	struct rtl838x_nor *rtl838x_nor = nor->priv;
-	size_t l = len;
-	uint8_t cmd = SPINOR_OP_PP;
-
-	/* Do write in 4-byte mode on large Macronix chips */
-	if (rtl838x_nor->fourByteMode) {
-		cmd = SPINOR_OP_PP_4B;
-		spi_4b_set(rtl838x_nor, true);
-	}
-
-	pr_debug("In %s %8x to: %llx\n", __func__,
-		 (unsigned int) rtl838x_nor, to);
-
-	while (l >= SPI_MAX_TRANSFER_SIZE) {
-		while
-			(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
-		do {
-			spi_write_enable(rtl838x_nor);
-		} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
-		ret = rtl838x_do_4b_write(rtl838x_nor, to + offset,
-				SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
-		l -= SPI_MAX_TRANSFER_SIZE;
-		offset += SPI_MAX_TRANSFER_SIZE;
-	}
-
-	if (l > 0) {
-		while
-			(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
-		do {
-			spi_write_enable(rtl838x_nor);
-		} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
-		ret = rtl838x_do_4b_write(rtl838x_nor, to+offset,
-					  len, buffer+offset, cmd);
-	}
-
-	return len;
-}
-
-static ssize_t rtl838x_nor_read(struct spi_nor *nor, loff_t from,
-				size_t length, u_char *buffer)
-{
-	uint32_t offset = 0;
-	uint8_t cmd = SPINOR_OP_READ_FAST;
-	size_t l = length;
-	struct rtl838x_nor *rtl838x_nor = nor->priv;
-
-	/* Do fast read in 3, or 4-byte mode on large Macronix chips */
-	if (rtl838x_nor->fourByteMode) {
-		cmd = SPINOR_OP_READ_FAST_4B;
-		spi_4b_set(rtl838x_nor, true);
-	}
-
-	/* TODO: do timeout and return error */
-	pr_debug("Waiting for pending writes\n");
-	while
-		(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
-	do {
-		spi_write_enable(rtl838x_nor);
-	} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
-
-	pr_debug("cmd is %d\n", cmd);
-	pr_debug("%s: addr %.8llx to addr %.8x, cmd %.8x, size %d\n", __func__,
-		 from, (u32)buffer, (u32)cmd, length);
-
-	while (l >= SPI_MAX_TRANSFER_SIZE) {
-		rtl838x_do_4bf_read(rtl838x_nor, from + offset,
-				    SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
-		l -= SPI_MAX_TRANSFER_SIZE;
-		offset += SPI_MAX_TRANSFER_SIZE;
-	}
-
-	if (l > 0)
-		rtl838x_do_4bf_read(rtl838x_nor, from + offset, l, buffer+offset, cmd);
-
-	return length;
-}
-
-static int rtl838x_erase(struct spi_nor *nor, loff_t offs)
-{
-	struct rtl838x_nor *rtl838x_nor = nor->priv;
-	int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
-	int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
-	uint32_t sfcsr;
-	uint8_t cmd = SPINOR_OP_SE;
-
-	pr_debug("Erasing sector at %llx\n", offs);
-
-	/* Do erase in 4-byte mode on large Macronix chips */
-	if (rtl838x_nor->fourByteMode) {
-		cmd = SPINOR_OP_SE_4B;
-		spi_4b_set(rtl838x_nor, true);
-	}
-	/* TODO: do timeout and return error */
-	while
-		(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
-	do {
-		spi_write_enable(rtl838x_nor);
-	} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
-
-	sfcsr = spi_prep(rtl838x_nor);
-
-	/* Send erase command, command IO-width is 1 (bit 25/26) */
-	spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
-	spi_w32w(cmd << 24, SFDR);
-
-	/* Send address */
-	spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
-	spi_w32w(offs << sfdr_addr_shift, SFDR);
-
-	return 0;
-}
-
-static int rtl838x_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
-{
-	int length = len;
-	u8 *buffer = buf;
-	uint32_t sfcsr, sfdr;
-	struct rtl838x_nor *rtl838x_nor = nor->priv;
-
-	pr_debug("In %s: opcode %x, len %x\n", __func__, opcode, len);
-
-	sfcsr = spi_prep(rtl838x_nor);
-	sfdr = opcode << 24;
-
-	sfcsr |= SPI_LEN1;
-
-	spi_w32w(sfcsr, SFCSR);
-	spi_w32w(sfdr, SFDR);
-
-	while (length > 0) {
-		SPI_WAIT_READY;
-		*(buffer) = spi_r32(SFDR) >> 24;
-		buffer++;
-		length--;
-	}
-
-	return len;
-}
-
-static int rtl838x_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
-{
-	uint32_t sfcsr, sfdr;
-	struct rtl838x_nor *rtl838x_nor = nor->priv;
-
-	pr_debug("In %s, opcode %x, len %x\n", __func__, opcode, len);
-	sfcsr = spi_prep(rtl838x_nor);
-	sfdr = opcode << 24;
-
-	if (len == 1) { /* SPINOR_OP_WRSR */
-		sfdr |= buf[0];
-		sfcsr |= SPI_LEN2;
-	}
-	spi_w32w(sfcsr, SFCSR);
-	spi_w32w(sfdr, SFDR);
-	return 0;
-}
-
-static int spi_enter_sio(struct spi_nor *nor)
-{
-	uint32_t sfcsr, sfcr2, sfdr;
-	uint32_t ret = 0, reg = 0, size_bits;
-	struct rtl838x_nor *rtl838x_nor = nor->priv;
-
-	pr_debug("In %s\n", __func__);
-	rtl838x_nor->io_status = 0;
-	sfdr = SPI_C_RSTQIO << 24;
-	sfcsr = spi_prep(rtl838x_nor);
-
-	reg = spi_r32(SFCR2);
-	pr_debug("SFCR2: %x, size %x, rdopt: %x\n", reg, SFCR2_GETSIZE(reg),
-						  (reg & SFCR2_RDOPT));
-	size_bits = rtl838x_nor->fourByteMode ? SFCR2_SIZE(0x6) : SFCR2_SIZE(0x7);
-
-	sfcr2 = SFCR2_HOLD_TILL_SFDR2 | size_bits
-		| (reg & SFCR2_RDOPT) | SFCR2_CMDIO(0)
-		| SFCR2_ADDRIO(0) | SFCR2_DUMMYCYCLE(4)
-		| SFCR2_DATAIO(0) | SFCR2_SFCMD(SPINOR_OP_READ_FAST);
-	pr_debug("SFCR2: %x, size %x\n", reg, SFCR2_GETSIZE(reg));
-
-	SPI_WAIT_READY;
-	spi_w32w(sfcr2, SFCR2);
-	spi_w32w(sfcsr, SFCSR);
-	spi_w32w(sfdr, SFDR);
-
-	spi_w32_mask(SFCR2_HOLD_TILL_SFDR2, 0, SFCR2);
-	rtl838x_nor->io_status &= ~IOSTATUS_CIO_MASK;
-	rtl838x_nor->io_status |= CIO1;
-
-	spi_prep(rtl838x_nor);
-
-	return ret;
-}
-
-int rtl838x_spi_nor_scan(struct spi_nor *nor, const char *name)
-{
-	static const struct spi_nor_hwcaps hwcaps = {
-		.mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_PP
-			| SNOR_HWCAPS_READ_FAST
-	};
-
-	struct rtl838x_nor *rtl838x_nor = nor->priv;
-
-	pr_debug("In %s\n", __func__);
-
-	spi_w32_mask(0, SFCR_EnableWBO, SFCR);
-	spi_w32_mask(0, SFCR_EnableRBO, SFCR);
-
-	rtl838x_nor->flags = CS0 | R_MODE;
-
-	spi_nor_scan(nor, NULL, &hwcaps);
-	pr_debug("------------- Got size: %llx\n", nor->mtd.size);
-
-	return 0;
-}
-
-int rtl838x_nor_init(struct rtl838x_nor *rtl838x_nor,
-			struct device_node *flash_node)
-{
-	int ret;
-	struct spi_nor *nor;
-
-	pr_info("%s called\n", __func__);
-	nor = &rtl838x_nor->nor;
-	nor->dev = rtl838x_nor->dev;
-	nor->priv = rtl838x_nor;
-	spi_nor_set_flash_node(nor, flash_node);
-
-	nor->read_reg = rtl838x_nor_read_reg;
-	nor->write_reg = rtl838x_nor_write_reg;
-	nor->read = rtl838x_nor_read;
-	nor->write = rtl838x_nor_write;
-	nor->erase = rtl838x_erase;
-	nor->mtd.name = "rtl838x_nor";
-	nor->erase_opcode = rtl838x_nor->fourByteMode ? SPINOR_OP_SE_4B
-					: SPINOR_OP_SE;
-	/* initialized with NULL */
-	ret = rtl838x_spi_nor_scan(nor, NULL);
-	if (ret)
-		return ret;
-
-	spi_enter_sio(nor);
-	spi_write_disable(rtl838x_nor);
-
-	ret = mtd_device_parse_register(&nor->mtd, NULL, NULL, NULL, 0);
-	return ret;
-}
-
-static int rtl838x_nor_drv_probe(struct platform_device *pdev)
-{
-	struct device_node *flash_np;
-	struct resource *res;
-	int ret;
-	struct rtl838x_nor *rtl838x_nor;
-	int addrMode;
-
-	pr_info("Initializing rtl838x_nor_driver\n");
-	if (!pdev->dev.of_node) {
-		dev_err(&pdev->dev, "No DT found\n");
-		return -EINVAL;
-	}
-
-	rtl838x_nor = devm_kzalloc(&pdev->dev, sizeof(*rtl838x_nor), GFP_KERNEL);
-	if (!rtl838x_nor)
-		return -ENOMEM;
-	platform_set_drvdata(pdev, rtl838x_nor);
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	rtl838x_nor->base = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR((void *)rtl838x_nor->base))
-		return PTR_ERR((void *)rtl838x_nor->base);
-
-	pr_info("SPI resource base is %08x\n", (u32)rtl838x_nor->base);
-	rtl838x_nor->dev = &pdev->dev;
-
-	/* only support one attached flash */
-	flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
-	if (!flash_np) {
-		dev_err(&pdev->dev, "no SPI flash device to configure\n");
-		ret = -ENODEV;
-		goto nor_free;
-	}
-
-	/* Get the 3/4 byte address mode as configure by bootloader */
-	if (soc_info.family == RTL8390_FAMILY_ID)
-		addrMode = rtl8390_get_addr_mode(rtl838x_nor);
-	else
-		addrMode = rtl838x_get_addr_mode(rtl838x_nor);
-	pr_info("Address mode is %d bytes\n", addrMode);
-	if (addrMode == 4)
-		rtl838x_nor->fourByteMode = true;
-
-	ret = rtl838x_nor_init(rtl838x_nor, flash_np);
-
-nor_free:
-	return ret;
-}
-
-static int rtl838x_nor_drv_remove(struct platform_device *pdev)
-{
-/*	struct rtl8xx_nor *rtl838x_nor = platform_get_drvdata(pdev); */
-	return 0;
-}
-
-static const struct of_device_id rtl838x_nor_of_ids[] = {
-	{ .compatible = "realtek,rtl838x-nor"},
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, rtl838x_nor_of_ids);
-
-static struct platform_driver rtl838x_nor_driver = {
-	.probe = rtl838x_nor_drv_probe,
-	.remove = rtl838x_nor_drv_remove,
-	.driver = {
-		.name = "rtl838x-nor",
-		.pm = NULL,
-		.of_match_table = rtl838x_nor_of_ids,
-	},
-};
-
-module_platform_driver(rtl838x_nor_driver);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("RTL838x SPI NOR Flash Driver");
diff --git a/target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h b/target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h
deleted file mode 100644
index de424c647a..0000000000
--- a/target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2009 Realtek Semiconductor Corp.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _RTL838X_SPI_H
-#define _RTL838X_SPI_H
-
-
-/*
- * Register access macros
- */
-
-#define spi_r32(reg)		readl(rtl838x_nor->base + reg)
-#define spi_w32(val, reg)	writel(val, rtl838x_nor->base + reg)
-#define spi_w32_mask(clear, set, reg)	\
-	spi_w32((spi_r32(reg) & ~(clear)) | (set), reg)
-
-#define SPI_WAIT_READY		do { \
-				} while (!(spi_r32(SFCSR) & SFCSR_SPI_RDY))
-
-#define spi_w32w(val, reg)	do { \
-					writel(val, rtl838x_nor->base + reg); \
-					SPI_WAIT_READY; \
-				} while (0)
-
-#define SFCR   (0x00)			/*SPI Flash Configuration Register*/
-	#define SFCR_CLK_DIV(val)	((val)<<29)
-	#define SFCR_EnableRBO		(1<<28)
-	#define SFCR_EnableWBO		(1<<27)
-	#define SFCR_SPI_TCS(val)	((val)<<23) /*4 bit, 1111 */
-
-#define SFCR2  (0x04)	/*For memory mapped I/O */
-	#define SFCR2_SFCMD(val)	((val)<<24) /*8 bit, 1111_1111 */
-	#define SFCR2_SIZE(val)		((val)<<21) /*3 bit, 111 */
-	#define SFCR2_RDOPT		(1<<20)
-	#define SFCR2_CMDIO(val)	((val)<<18) /*2 bit, 11 */
-	#define SFCR2_ADDRIO(val)	((val)<<16) /*2 bit, 11 */
-	#define SFCR2_DUMMYCYCLE(val)	((val)<<13) /*3 bit, 111 */
-	#define SFCR2_DATAIO(val)	((val)<<11) /*2 bit, 11 */
-	#define SFCR2_HOLD_TILL_SFDR2	(1<<10)
-	#define SFCR2_GETSIZE(x)	(((x)&0x00E00000)>>21)
-
-#define SFCSR  (0x08)	/*SPI Flash Control&Status Register*/
-	#define SFCSR_SPI_CSB0		(1<<31)
-	#define SFCSR_SPI_CSB1		(1<<30)
-	#define SFCSR_LEN(val)		((val)<<28)  /*2 bits*/
-	#define SFCSR_SPI_RDY		(1<<27)
-	#define SFCSR_IO_WIDTH(val)	((val)<<25)  /*2 bits*/
-	#define SFCSR_CHIP_SEL		(1<<24)
-	#define SFCSR_CMD_BYTE(val)	((val)<<16)  /*8 bit, 1111_1111 */
-
-#define SFDR   (0x0C)	/*SPI Flash Data Register*/
-#define SFDR2  (0x10)	/*SPI Flash Data Register - for post SPI bootup setting*/
-	#define SPI_CS_INIT		(SFCSR_SPI_CSB0 | SFCSR_SPI_CSB1 | SPI_LEN1)
-	#define SPI_CS0			SFCSR_SPI_CSB0
-	#define SPI_CS1			SFCSR_SPI_CSB1
-	#define SPI_eCS0		((SFCSR_SPI_CSB1)) /*and SFCSR to active CS0*/
-	#define SPI_eCS1		((SFCSR_SPI_CSB0)) /*and SFCSR to active CS1*/
-
-	#define SPI_WIP (1)		/* Write In Progress */
-	#define SPI_WEL (1<<1)		/* Write Enable Latch*/
-	#define SPI_SST_QIO_WIP (1<<7)	/* SST QIO Flash Write In Progress */
-	#define SPI_LEN_INIT 0xCFFFFFFF /* and SFCSR to init   */
-	#define SPI_LEN4    0x30000000	/* or SFCSR to set */
-	#define SPI_LEN3    0x20000000	/* or SFCSR to set */
-	#define SPI_LEN2    0x10000000	/* or SFCSR to set */
-	#define SPI_LEN1    0x00000000	/* or SFCSR to set */
-	#define SPI_SETLEN(val) do {		\
-			SPI_REG(SFCSR) &= 0xCFFFFFFF;   \
-			SPI_REG(SFCSR) |= (val-1)<<28;	\
-		} while (0)
-/*
- * SPI interface control
- */
-#define RTL8390_SOC_SPI_MMIO_CONF (0x04)
-
-#define IOSTATUS_CIO_MASK (0x00000038)
-
-/* Chip select: bits 4-7*/
-#define CS0 (1<<4)
-#define R_MODE 0x04
-
-/* io_status */
-#define IO1 (1<<0)
-#define IO2 (1<<1)
-#define CIO1 (1<<3)
-#define CIO2 (1<<4)
-#define CMD_IO1 (1<<6)
-#define W_ADDR_IO1 ((1)<<12)
-#define R_ADDR_IO2 ((2)<<9)
-#define R_DATA_IO2 ((2)<<15)
-#define W_DATA_IO1 ((1)<<18)
-
-/* Commands */
-#define SPI_C_RSTQIO 0xFF
-
-#define SPI_MAX_TRANSFER_SIZE 256
-
-#endif		/* _RTL838X_SPI_H */
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Kconfig b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Kconfig
deleted file mode 100644
index f293832eb5..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Kconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-config NET_DSA_RTL83XX
-	tristate "Realtek RTL838x/RTL839x switch support"
-	depends on RTL838X
-	select NET_DSA_TAG_TRAILER
-	---help---
-	  This driver adds support for Realtek RTL83xx series switching.
-
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Makefile b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Makefile
deleted file mode 100644
index 016184c3d9..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_NET_DSA_RTL83XX)	+= common.o dsa.o \
-	rtl838x.o rtl839x.o rtl930x.o rtl931x.o debugfs.o qos.o
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/common.c
deleted file mode 100644
index a380906b92..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/common.c
+++ /dev/null
@@ -1,722 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <linux/of_mdio.h>
-#include <linux/of_platform.h>
-
-#include <asm/mach-rtl838x/mach-rtl83xx.h>
-#include "rtl83xx.h"
-
-extern struct rtl83xx_soc_info soc_info;
-
-extern const struct rtl838x_reg rtl838x_reg;
-extern const struct rtl838x_reg rtl839x_reg;
-extern const struct rtl838x_reg rtl930x_reg;
-extern const struct rtl838x_reg rtl931x_reg;
-
-extern const struct dsa_switch_ops rtl83xx_switch_ops;
-extern const struct dsa_switch_ops rtl930x_switch_ops;
-
-DEFINE_MUTEX(smi_lock);
-
-int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
-{
-	u32 msti = 0;
-	u32 port_state[4];
-	int index, bit;
-	int pos = port;
-	int n = priv->port_width << 1;
-
-	/* Ports above or equal CPU port can never be configured */
-	if (port >= priv->cpu_port)
-		return -1;
-
-	mutex_lock(&priv->reg_mutex);
-
-	/* For the RTL839x and following, the bits are left-aligned in the 64/128 bit field */
-	if (priv->family_id == RTL8390_FAMILY_ID)
-		pos += 12;
-	if (priv->family_id == RTL9300_FAMILY_ID)
-		pos += 3;
-	if (priv->family_id == RTL9310_FAMILY_ID)
-		pos += 8;
-
-	index = n - (pos >> 4) - 1;
-	bit = (pos << 1) % 32;
-
-	priv->r->stp_get(priv, msti, port_state);
-
-	mutex_unlock(&priv->reg_mutex);
-
-	return (port_state[index] >> bit) & 3;
-}
-
-static struct table_reg rtl838x_tbl_regs[] = {
-	TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1),		// RTL8380_TBL_L2
-	TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1),	// RTL8380_TBL_0
-	TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1),		// RTL8380_TBL_1
-
-	TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0),		// RTL8390_TBL_L2
-	TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0),	// RTL8390_TBL_0
-	TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0),		// RTL8390_TBL_1
-	TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0),		// RTL8390_TBL_2
-
-	TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0),		// RTL9300_TBL_L2
-	TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0),	// RTL9300_TBL_0
-	TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0),	// RTL9300_TBL_1
-	TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0),		// RTL9300_TBL_2
-	TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0),		// RTL9300_TBL_HSB
-	TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0),		// RTL9300_TBL_HSA
-
-	TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0),		// RTL9310_TBL_0
-	TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0),	// RTL9310_TBL_1
-	TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0),		// RTL9310_TBL_2
-	TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0),		// RTL9310_TBL_3
-	TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0),		// RTL9310_TBL_4
-	TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0),		// RTL9310_TBL_5
-};
-
-void rtl_table_init(void)
-{
-	int i;
-
-	for (i = 0; i < RTL_TBL_END; i++)
-		mutex_init(&rtl838x_tbl_regs[i].lock);
-}
-
-/*
- * Request access to table t in table access register r
- * Returns a handle to a lock for that table
- */
-struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t)
-{
-	if (r >= RTL_TBL_END)
-		return NULL;
-
-	if (t >= BIT(rtl838x_tbl_regs[r].c_bit-rtl838x_tbl_regs[r].t_bit))
-		return NULL;
-
-	mutex_lock(&rtl838x_tbl_regs[r].lock);
-	rtl838x_tbl_regs[r].tbl = t;
-
-	return &rtl838x_tbl_regs[r];
-}
-
-/*
- * Release a table r, unlock the corresponding lock
- */
-void rtl_table_release(struct table_reg *r)
-{
-	if (!r)
-		return;
-
-//	pr_info("Unlocking %08x\n", (u32)r);
-	mutex_unlock(&r->lock);
-//	pr_info("Unlock done\n");
-}
-
-/*
- * Reads table index idx into the data registers of the table
- */
-void rtl_table_read(struct table_reg *r, int idx)
-{
-	u32 cmd = r->rmode ? BIT(r->c_bit) : 0;
-
-	cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
-	sw_w32(cmd, r->addr);
-	do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
-}
-
-/*
- * Writes the content of the table data registers into the table at index idx
- */
-void rtl_table_write(struct table_reg *r, int idx)
-{
-	u32 cmd = r->rmode ? 0 : BIT(r->c_bit);
-
-	cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
-	sw_w32(cmd, r->addr);
-	do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
-}
-
-/*
- * Returns the address of the ith data register of table register r
- * the address is relative to the beginning of the Switch-IO block at 0xbb000000
- */
-inline u16 rtl_table_data(struct table_reg *r, int i)
-{
-	if (i >= r->max_data)
-		i = r->max_data - 1;
-	return r->data + i * 4;
-}
-
-inline u32 rtl_table_data_r(struct table_reg *r, int i)
-{
-	return sw_r32(rtl_table_data(r, i));
-}
-
-inline void rtl_table_data_w(struct table_reg *r, u32 v, int i)
-{
-	sw_w32(v, rtl_table_data(r, i));
-}
-
-/* Port register accessor functions for the RTL838x and RTL930X SoCs */
-void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
-{
-	sw_w32_mask((u32)clear, (u32)set, reg);
-}
-
-void rtl838x_set_port_reg(u64 set, int reg)
-{
-	sw_w32((u32)set, reg);
-}
-
-u64 rtl838x_get_port_reg(int reg)
-{
-	return ((u64) sw_r32(reg));
-}
-
-/* Port register accessor functions for the RTL839x and RTL931X SoCs */
-void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)
-{
-	sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);
-	sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);
-}
-
-u64 rtl839x_get_port_reg_be(int reg)
-{
-	u64 v = sw_r32(reg);
-
-	v <<= 32;
-	v |= sw_r32(reg + 4);
-	return v;
-}
-
-void rtl839x_set_port_reg_be(u64 set, int reg)
-{
-	sw_w32(set >> 32, reg);
-	sw_w32(set & 0xffffffff, reg + 4);
-}
-
-void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)
-{
-	sw_w32_mask((u32)clear, (u32)set, reg);
-	sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);
-}
-
-void rtl839x_set_port_reg_le(u64 set, int reg)
-{
-	sw_w32(set, reg);
-	sw_w32(set >> 32, reg + 4);
-}
-
-u64 rtl839x_get_port_reg_le(int reg)
-{
-	u64 v = sw_r32(reg + 4);
-
-	v <<= 32;
-	v |= sw_r32(reg);
-	return v;
-}
-
-int read_phy(u32 port, u32 page, u32 reg, u32 *val)
-{
-	switch (soc_info.family) {
-	case RTL8380_FAMILY_ID:
-		return rtl838x_read_phy(port, page, reg, val);
-	case RTL8390_FAMILY_ID:
-		return rtl839x_read_phy(port, page, reg, val);
-	case RTL9300_FAMILY_ID:
-		return rtl930x_read_phy(port, page, reg, val);
-	case RTL9310_FAMILY_ID:
-		return rtl931x_read_phy(port, page, reg, val);
-	}
-	return -1;
-}
-
-int write_phy(u32 port, u32 page, u32 reg, u32 val)
-{
-	switch (soc_info.family) {
-	case RTL8380_FAMILY_ID:
-		return rtl838x_write_phy(port, page, reg, val);
-	case RTL8390_FAMILY_ID:
-		return rtl839x_write_phy(port, page, reg, val);
-	case RTL9300_FAMILY_ID:
-		return rtl930x_write_phy(port, page, reg, val);
-	case RTL9310_FAMILY_ID:
-		return rtl931x_write_phy(port, page, reg, val);
-	}
-	return -1;
-}
-
-static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
-{
-	struct device *dev = priv->dev;
-	struct device_node *dn, *mii_np = dev->of_node;
-	struct mii_bus *bus;
-	int ret;
-	u32 pn;
-
-	pr_debug("In %s\n", __func__);
-	mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
-	if (mii_np) {
-		pr_debug("Found compatible MDIO node!\n");
-	} else {
-		dev_err(priv->dev, "no %s child node found", "mdio-bus");
-		return -ENODEV;
-	}
-
-	priv->mii_bus = of_mdio_find_bus(mii_np);
-	if (!priv->mii_bus) {
-		pr_debug("Deferring probe of mdio bus\n");
-		return -EPROBE_DEFER;
-	}
-	if (!of_device_is_available(mii_np))
-		ret = -ENODEV;
-
-	bus = devm_mdiobus_alloc(priv->ds->dev);
-	if (!bus)
-		return -ENOMEM;
-
-	bus->name = "rtl838x slave mii";
-
-	/*
-	 * Since the NIC driver is loaded first, we can use the mdio rw functions
-	 * assigned there.
-	 */
-	bus->read = priv->mii_bus->read;
-	bus->write = priv->mii_bus->write;
-	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
-
-	bus->parent = dev;
-	priv->ds->slave_mii_bus = bus;
-	priv->ds->slave_mii_bus->priv = priv;
-
-	ret = mdiobus_register(priv->ds->slave_mii_bus);
-	if (ret && mii_np) {
-		of_node_put(dn);
-		return ret;
-	}
-
-	dn = mii_np;
-	for_each_node_by_name(dn, "ethernet-phy") {
-		if (of_property_read_u32(dn, "reg", &pn))
-			continue;
-
-		priv->ports[pn].dp = dsa_to_port(priv->ds, pn);
-
-		// Check for the integrated SerDes of the RTL8380M first
-		if (of_property_read_bool(dn, "phy-is-integrated")
-			&& priv->id == 0x8380 && pn >= 24) {
-			pr_debug("----> FÓUND A SERDES\n");
-			priv->ports[pn].phy = PHY_RTL838X_SDS;
-			continue;
-		}
-
-		if (of_property_read_bool(dn, "phy-is-integrated")
-			&& !of_property_read_bool(dn, "sfp")) {
-			priv->ports[pn].phy = PHY_RTL8218B_INT;
-			continue;
-		}
-
-		if (!of_property_read_bool(dn, "phy-is-integrated")
-			&& of_property_read_bool(dn, "sfp")) {
-			priv->ports[pn].phy = PHY_RTL8214FC;
-			continue;
-		}
-
-		if (!of_property_read_bool(dn, "phy-is-integrated")
-			&& !of_property_read_bool(dn, "sfp")) {
-			priv->ports[pn].phy = PHY_RTL8218B_EXT;
-			continue;
-		}
-	}
-
-	// TODO: Do this needs to come from the .dts, at least the SerDes number
-	if (priv->family_id == RTL9300_FAMILY_ID) {
-		priv->ports[24].is2G5 = true;
-		priv->ports[25].is2G5 = true;
-		priv->ports[24].sds_num = 1;
-		priv->ports[24].sds_num = 2;
-	}
-
-	/* Disable MAC polling the PHY so that we can start configuration */
-	priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
-
-	/* Enable PHY control via SoC */
-	if (priv->family_id == RTL8380_FAMILY_ID) {
-		/* Enable SerDes NWAY and PHY control via SoC */
-		sw_w32_mask(BIT(7), BIT(15), RTL838X_SMI_GLB_CTRL);
-	} else {
-		/* Disable PHY polling via SoC */
-		sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
-	}
-
-	/* Power on fibre ports and reset them if necessary */
-	if (priv->ports[24].phy == PHY_RTL838X_SDS) {
-		pr_debug("Powering on fibre ports & reset\n");
-		rtl8380_sds_power(24, 1);
-		rtl8380_sds_power(26, 1);
-	}
-
-	// TODO: Only power on SerDes with external PHYs connected
-	if (priv->family_id == RTL9300_FAMILY_ID) {
-		pr_info("RTL9300 Powering on SerDes ports\n");
-		rtl9300_sds_power(24, 1);
-		rtl9300_sds_power(25, 1);
-		rtl9300_sds_power(26, 1);
-		rtl9300_sds_power(27, 1);
-	}
-
-	pr_debug("%s done\n", __func__);
-	return 0;
-}
-
-static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
-{
-	int t = sw_r32(priv->r->l2_ctrl_1);
-
-	t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
-
-	if (priv->family_id == RTL8380_FAMILY_ID)
-		t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
-	else
-		t = (t * 3) / 5;
-
-	pr_debug("L2 AGING time: %d sec\n", t);
-	pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out));
-	return t;
-}
-
-/* Caller must hold priv->reg_mutex */
-int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	int i;
-
-	pr_info("%s: Adding port %d to LA-group %d\n", __func__, port, group);
-	if (group >= priv->n_lags) {
-		pr_err("Link Agrregation group too large.\n");
-		return -EINVAL;
-	}
-
-	if (port >= priv->cpu_port) {
-		pr_err("Invalid port number.\n");
-		return -EINVAL;
-	}
-
-	for (i = 0; i < priv->n_lags; i++) {
-		if (priv->lags_port_members[i] & BIT_ULL(i))
-			break;
-	}
-	if (i != priv->n_lags) {
-		pr_err("%s: Port already member of LAG: %d\n", __func__, i);
-		return -ENOSPC;
-	}
-
-	priv->r->mask_port_reg_be(0, BIT_ULL(port), priv->r->trk_mbr_ctr(group));
-	priv->lags_port_members[group] |= BIT_ULL(port);
-
-	pr_info("lags_port_members %d now %016llx\n", group, priv->lags_port_members[group]);
-	return 0;
-}
-
-/* Caller must hold priv->reg_mutex */
-int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-
-	pr_info("%s: Removing port %d from LA-group %d\n", __func__, port, group);
-
-	if (group >= priv->n_lags) {
-		pr_err("Link Agrregation group too large.\n");
-		return -EINVAL;
-	}
-
-	if (port >= priv->cpu_port) {
-		pr_err("Invalid port number.\n");
-		return -EINVAL;
-	}
-
-
-	if (!(priv->lags_port_members[group] & BIT_ULL(port))) {
-		pr_err("%s: Port not member of LAG: %d\n", __func__, group
-		);
-		return -ENOSPC;
-	}
-
-	priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->trk_mbr_ctr(group));
-	priv->lags_port_members[group] &= ~BIT_ULL(port);
-
-	pr_info("lags_port_members %d now %016llx\n", group, priv->lags_port_members[group]);
-	return 0;
-}
-
-static int rtl83xx_handle_changeupper(struct rtl838x_switch_priv *priv,
-				      struct net_device *ndev,
-				      struct netdev_notifier_changeupper_info *info)
-{
-	struct net_device *upper = info->upper_dev;
-	int i, j, err;
-
-	if (!netif_is_lag_master(upper))
-		return 0;
-
-	mutex_lock(&priv->reg_mutex);
-
-	for (i = 0; i < priv->n_lags; i++) {
-		if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == upper))
-			break;
-	}
-	for (j = 0; j < priv->cpu_port; j++) {
-		if (priv->ports[j].dp->slave == ndev)
-			break;
-	}
-	if (j >= priv->cpu_port) {
-		err = -EINVAL;
-		goto out;
-	}
-
-	if (info->linking) {
-		if (!priv->lag_devs[i])
-			priv->lag_devs[i] = upper;
-		err = rtl83xx_lag_add(priv->ds, i, priv->ports[j].dp->index);
-		if (err) {
-			err = -EINVAL;
-			goto out;
-		}
-	} else {
-		if (!priv->lag_devs[i])
-			err = -EINVAL;
-		err = rtl83xx_lag_del(priv->ds, i, priv->ports[j].dp->index);
-		if (err) {
-			err = -EINVAL;
-			goto out;
-		}
-		if (!priv->lags_port_members[i])
-			priv->lag_devs[i] = NULL;
-	}
-
-out:
-	mutex_unlock(&priv->reg_mutex);
-	return 0;
-}
-
-static int rtl83xx_netdevice_event(struct notifier_block *this,
-				   unsigned long event, void *ptr)
-{
-	struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
-	struct rtl838x_switch_priv *priv;
-	int err;
-
-	pr_debug("In: %s, event: %lu\n", __func__, event);
-
-	if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE))
-		return NOTIFY_DONE;
-
-	priv = container_of(this, struct rtl838x_switch_priv, nb);
-	switch (event) {
-	case NETDEV_CHANGEUPPER:
-		err = rtl83xx_handle_changeupper(priv, ndev, ptr);
-		break;
-	}
-
-	if (err)
-		return err;
-
-	return NOTIFY_DONE;
-}
-
-static int __init rtl83xx_sw_probe(struct platform_device *pdev)
-{
-	int err = 0, i;
-	struct rtl838x_switch_priv *priv;
-	struct device *dev = &pdev->dev;
-	u64 bpdu_mask;
-
-	pr_debug("Probing RTL838X switch device\n");
-	if (!pdev->dev.of_node) {
-		dev_err(dev, "No DT found\n");
-		return -EINVAL;
-	}
-
-	// Initialize access to RTL switch tables
-	rtl_table_init();
-
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
-
-	if (!priv->ds)
-		return -ENOMEM;
-	priv->ds->dev = dev;
-	priv->ds->priv = priv;
-	priv->ds->ops = &rtl83xx_switch_ops;
-	priv->dev = dev;
-
-	priv->family_id = soc_info.family;
-	priv->id = soc_info.id;
-	switch(soc_info.family) {
-	case RTL8380_FAMILY_ID:
-		priv->ds->ops = &rtl83xx_switch_ops;
-		priv->cpu_port = RTL838X_CPU_PORT;
-		priv->port_mask = 0x1f;
-		priv->port_width = 1;
-		priv->irq_mask = 0x0FFFFFFF;
-		priv->r = &rtl838x_reg;
-		priv->ds->num_ports = 29;
-		priv->fib_entries = 8192;
-		rtl8380_get_version(priv);
-		priv->n_lags = 8;
-		priv->l2_bucket_size = 4;
-		break;
-	case RTL8390_FAMILY_ID:
-		priv->ds->ops = &rtl83xx_switch_ops;
-		priv->cpu_port = RTL839X_CPU_PORT;
-		priv->port_mask = 0x3f;
-		priv->port_width = 2;
-		priv->irq_mask = 0xFFFFFFFFFFFFFULL;
-		priv->r = &rtl839x_reg;
-		priv->ds->num_ports = 53;
-		priv->fib_entries = 16384;
-		rtl8390_get_version(priv);
-		priv->n_lags = 16;
-		priv->l2_bucket_size = 4;
-		break;
-	case RTL9300_FAMILY_ID:
-		priv->ds->ops = &rtl930x_switch_ops;
-		priv->cpu_port = RTL930X_CPU_PORT;
-		priv->port_mask = 0x1f;
-		priv->port_width = 1;
-		priv->irq_mask = 0x0FFFFFFF;
-		priv->r = &rtl930x_reg;
-		priv->ds->num_ports = 29;
-		priv->fib_entries = 16384;
-		priv->version = RTL8390_VERSION_A;
-		priv->n_lags = 16;
-		sw_w32(1, RTL930X_ST_CTRL);
-		priv->l2_bucket_size = 8;
-		break;
-	case RTL9310_FAMILY_ID:
-		priv->ds->ops = &rtl930x_switch_ops;
-		priv->cpu_port = RTL931X_CPU_PORT;
-		priv->port_mask = 0x3f;
-		priv->port_width = 2;
-		priv->irq_mask = 0xFFFFFFFFFFFFFULL;
-		priv->r = &rtl931x_reg;
-		priv->ds->num_ports = 57;
-		priv->fib_entries = 16384;
-		priv->version = RTL8390_VERSION_A;
-		priv->n_lags = 16;
-		priv->l2_bucket_size = 8;
-		break;
-	}
-	pr_debug("Chip version %c\n", priv->version);
-
-	err = rtl83xx_mdio_probe(priv);
-	if (err) {
-		/* Probing fails the 1st time because of missing ethernet driver
-		 * initialization. Use this to disable traffic in case the bootloader left if on
-		 */
-		return err;
-	}
-	err = dsa_register_switch(priv->ds);
-	if (err) {
-		dev_err(dev, "Error registering switch: %d\n", err);
-		return err;
-	}
-
-	/* Enable link and media change interrupts. Are the SERDES masks needed? */
-	sw_w32_mask(0, 3, priv->r->isr_glb_src);
-
-	priv->r->set_port_reg_le(priv->irq_mask, priv->r->isr_port_link_sts_chg);
-	priv->r->set_port_reg_le(priv->irq_mask, priv->r->imr_port_link_sts_chg);
-
-	priv->link_state_irq = platform_get_irq(pdev, 0);
-	pr_info("LINK state irq: %d\n", priv->link_state_irq);
-	switch (priv->family_id) {
-	case RTL8380_FAMILY_ID:
-		err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
-				IRQF_SHARED, "rtl838x-link-state", priv->ds);
-		break;
-	case RTL8390_FAMILY_ID:
-		err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
-				IRQF_SHARED, "rtl839x-link-state", priv->ds);
-		break;
-	case RTL9300_FAMILY_ID:
-		err = request_irq(priv->link_state_irq, rtl930x_switch_irq,
-				IRQF_SHARED, "rtl930x-link-state", priv->ds);
-		break;
-	case RTL9310_FAMILY_ID:
-		err = request_irq(priv->link_state_irq, rtl931x_switch_irq,
-				IRQF_SHARED, "rtl931x-link-state", priv->ds);
-		break;
-	}
-	if (err) {
-		dev_err(dev, "Error setting up switch interrupt.\n");
-		/* Need to free allocated switch here */
-	}
-
-	/* Enable interrupts for switch, on RTL931x, the IRQ is always on globally */
-	if (soc_info.family != RTL9310_FAMILY_ID)
-		sw_w32(0x1, priv->r->imr_glb);
-
-	rtl83xx_get_l2aging(priv);
-
-	rtl83xx_setup_qos(priv);
-
-	/* Clear all destination ports for mirror groups */
-	for (i = 0; i < 4; i++)
-		priv->mirror_group_ports[i] = -1;
-
-	priv->nb.notifier_call = rtl83xx_netdevice_event;
-		if (register_netdevice_notifier(&priv->nb)) {
-			priv->nb.notifier_call = NULL;
-			dev_err(dev, "Failed to register LAG netdev notifier\n");
-	}
-
-	// Flood BPDUs to all ports including cpu-port
-	if (soc_info.family != RTL9300_FAMILY_ID) { // TODO: Port this functionality
-		bpdu_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF;
-		priv->r->set_port_reg_be(bpdu_mask, priv->r->rma_bpdu_fld_pmask);
-
-		// TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs
-		sw_w32(7, priv->r->spcl_trap_eapol_ctrl);
-
-		rtl838x_dbgfs_init(priv);
-	}
-
-	return err;
-}
-
-static int rtl83xx_sw_remove(struct platform_device *pdev)
-{
-	// TODO:
-	pr_debug("Removing platform driver for rtl83xx-sw\n");
-	return 0;
-}
-
-static const struct of_device_id rtl83xx_switch_of_ids[] = {
-	{ .compatible = "realtek,rtl83xx-switch"},
-	{ /* sentinel */ }
-};
-
-
-MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);
-
-static struct platform_driver rtl83xx_switch_driver = {
-	.probe = rtl83xx_sw_probe,
-	.remove = rtl83xx_sw_remove,
-	.driver = {
-		.name = "rtl83xx-switch",
-		.pm = NULL,
-		.of_match_table = rtl83xx_switch_of_ids,
-	},
-};
-
-module_platform_driver(rtl83xx_switch_driver);
-
-MODULE_AUTHOR("B. Koblitz");
-MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
-MODULE_LICENSE("GPL");
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/debugfs.c
deleted file mode 100644
index 4f81408453..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/debugfs.c
+++ /dev/null
@@ -1,476 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <linux/debugfs.h>
-#include <linux/kernel.h>
-
-#include <asm/mach-rtl838x/mach-rtl83xx.h>
-#include "rtl83xx.h"
-
-#define RTL838X_DRIVER_NAME "rtl838x"
-
-#define RTL8380_LED_GLB_CTRL			(0xA000)
-#define RTL8380_LED_MODE_SEL			(0x1004)
-#define RTL8380_LED_MODE_CTRL			(0xA004)
-#define RTL8380_LED_P_EN_CTRL			(0xA008)
-#define RTL8380_LED_SW_CTRL			(0xA00C)
-#define RTL8380_LED0_SW_P_EN_CTRL		(0xA010)
-#define RTL8380_LED1_SW_P_EN_CTRL		(0xA014)
-#define RTL8380_LED2_SW_P_EN_CTRL		(0xA018)
-#define RTL8380_LED_SW_P_CTRL(p)		(0xA01C + (((p) << 2)))
-
-#define RTL8390_LED_GLB_CTRL			(0x00E4)
-#define RTL8390_LED_SET_2_3_CTRL		(0x00E8)
-#define RTL8390_LED_SET_0_1_CTRL		(0x00EC)
-#define RTL8390_LED_COPR_SET_SEL_CTRL(p)	(0x00F0 + (((p >> 4) << 2)))
-#define RTL8390_LED_FIB_SET_SEL_CTRL(p)		(0x0100 + (((p >> 4) << 2)))
-#define RTL8390_LED_COPR_PMASK_CTRL(p)		(0x0110 + (((p >> 5) << 2)))
-#define RTL8390_LED_FIB_PMASK_CTRL(p)		(0x00118 + (((p >> 5) << 2)))
-#define RTL8390_LED_COMBO_CTRL(p)		(0x0120 + (((p >> 5) << 2)))
-#define RTL8390_LED_SW_CTRL			(0x0128)
-#define RTL8390_LED_SW_P_EN_CTRL(p)		(0x012C + (((p / 10) << 2)))
-#define RTL8390_LED_SW_P_CTRL(p)		(0x0144 + (((p) << 2)))
-
-#define RTL838X_MIR_QID_CTRL(grp)		(0xAD44 + (((grp) << 2)))
-#define RTL838X_MIR_RSPAN_VLAN_CTRL(grp)	(0xA340 + (((grp) << 2)))
-#define RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(grp)	(0xAA70 + (((grp) << 2)))
-#define RTL838X_MIR_RSPAN_TX_CTRL		(0xA350)
-#define RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL	(0xAA80)
-#define RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL	(0xAA84)
-#define RTL839X_MIR_RSPAN_VLAN_CTRL(grp)	(0xA340 + (((grp) << 2)))
-#define RTL839X_MIR_RSPAN_TX_CTRL		(0x69b0)
-#define RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL	(0x2550)
-#define RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL	(0x2554)
-#define RTL839X_MIR_SAMPLE_RATE_CTRL                (0x2558)
-
-int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port);
-void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
-void rtl83xx_fast_age(struct dsa_switch *ds, int port);
-u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port);
-u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port);
-int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate);
-int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate);
-
-static ssize_t rtl838x_common_read(char __user *buffer, size_t count,
-					loff_t *ppos, unsigned int value)
-{
-	char *buf;
-	ssize_t len;
-
-	if (*ppos != 0)
-		return 0;
-
-	buf = kasprintf(GFP_KERNEL, "0x%08x\n", value);
-	if (!buf)
-		return -ENOMEM;
-
-	if (count < strlen(buf)) {
-		kfree(buf);
-		return -ENOSPC;
-	}
-
-	len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
-	kfree(buf);
-
-	return len;
-}
-
-static ssize_t rtl838x_common_write(const char __user *buffer, size_t count,
-				 loff_t *ppos, unsigned int *value)
-{
-	char b[32];
-	ssize_t len;
-	int ret;
-
-	if (*ppos != 0)
-		return -EINVAL;
-
-	if (count >= sizeof(b))
-		return -ENOSPC;
-
-	len = simple_write_to_buffer(b, sizeof(b) - 1, ppos,
-				     buffer, count);
-	if (len < 0)
-		return len;
-
-	b[len] = '\0';
-	ret = kstrtouint(b, 16, value);
-	if (ret)
-		return -EIO;
-
-	return len;
-}
-
-static ssize_t stp_state_read(struct file *filp, char __user *buffer, size_t count,
-			     loff_t *ppos)
-{
-	struct rtl838x_port *p = filp->private_data;
-	struct dsa_switch *ds = p->dp->ds;
-	int value = rtl83xx_port_get_stp_state(ds->priv, p->dp->index);
-
-	if (value < 0)
-		return -EINVAL;
-
-	return rtl838x_common_read(buffer, count, ppos, (u32)value);
-}
-
-static ssize_t stp_state_write(struct file *filp, const char __user *buffer,
-				size_t count, loff_t *ppos)
-{
-	struct rtl838x_port *p = filp->private_data;
-	u32 value;
-	size_t res = rtl838x_common_write(buffer, count, ppos, &value);
-	if (res < 0)
-		return res;
-
-	rtl83xx_port_stp_state_set(p->dp->ds, p->dp->index, (u8)value);
-
-	return res;
-}
-
-static const struct file_operations stp_state_fops = {
-	.owner = THIS_MODULE,
-	.open = simple_open,
-	.read = stp_state_read,
-	.write = stp_state_write,
-};
-
-static ssize_t age_out_read(struct file *filp, char __user *buffer, size_t count,
-			     loff_t *ppos)
-{
-	struct rtl838x_port *p = filp->private_data;
-	struct dsa_switch *ds = p->dp->ds;
-	struct rtl838x_switch_priv *priv = ds->priv;
-	int value = sw_r32(priv->r->l2_port_aging_out);
-
-	if (value < 0)
-		return -EINVAL;
-
-	return rtl838x_common_read(buffer, count, ppos, (u32)value);
-}
-
-static ssize_t age_out_write(struct file *filp, const char __user *buffer,
-				size_t count, loff_t *ppos)
-{
-	struct rtl838x_port *p = filp->private_data;
-	u32 value;
-	size_t res = rtl838x_common_write(buffer, count, ppos, &value);
-	if (res < 0)
-		return res;
-
-	rtl83xx_fast_age(p->dp->ds, p->dp->index);
-
-	return res;
-}
-
-static const struct file_operations age_out_fops = {
-	.owner = THIS_MODULE,
-	.open = simple_open,
-	.read = age_out_read,
-	.write = age_out_write,
-};
-
-static ssize_t port_egress_rate_read(struct file *filp, char __user *buffer, size_t count,
-				loff_t *ppos)
-{
-	struct rtl838x_port *p = filp->private_data;
-	struct dsa_switch *ds = p->dp->ds;
-	struct rtl838x_switch_priv *priv = ds->priv;
-	int value;
-	if (priv->family_id == RTL8380_FAMILY_ID)
-		value = rtl838x_get_egress_rate(priv, p->dp->index);
-	else
-		value = rtl839x_get_egress_rate(priv, p->dp->index);
-
-	if (value < 0)
-		return -EINVAL;
-
-	return rtl838x_common_read(buffer, count, ppos, (u32)value);
-}
-
-static ssize_t port_egress_rate_write(struct file *filp, const char __user *buffer,
-				size_t count, loff_t *ppos)
-{
-	struct rtl838x_port *p = filp->private_data;
-	struct dsa_switch *ds = p->dp->ds;
-	struct rtl838x_switch_priv *priv = ds->priv;
-	u32 value;
-	size_t res = rtl838x_common_write(buffer, count, ppos, &value);
-	if (res < 0)
-		return res;
-
-	if (priv->family_id == RTL8380_FAMILY_ID)
-		rtl838x_set_egress_rate(priv, p->dp->index, value);
-	else
-		rtl839x_set_egress_rate(priv, p->dp->index, value);
-
-	return res;
-}
-
-static const struct file_operations port_egress_fops = {
-	.owner = THIS_MODULE,
-	.open = simple_open,
-	.read = port_egress_rate_read,
-	.write = port_egress_rate_write,
-};
-
-
-static const struct debugfs_reg32 port_ctrl_regs[] = {
-	{ .name = "port_isolation", .offset = RTL838X_PORT_ISO_CTRL(0), },
-	{ .name = "mac_force_mode", .offset = RTL838X_MAC_FORCE_MODE_CTRL, },
-};
-
-void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv)
-{
-	debugfs_remove_recursive(priv->dbgfs_dir);
-
-//	kfree(priv->dbgfs_entries);
-}
-
-static int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_priv *priv,
-				   int port)
-{
-	struct dentry *port_dir;
-	struct debugfs_regset32 *port_ctrl_regset;
-
-	port_dir = debugfs_create_dir(priv->ports[port].dp->name, parent);
-
-	if (priv->family_id == RTL8380_FAMILY_ID) {
-		debugfs_create_x32("storm_rate_uc", 0644, port_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port)));
-
-		debugfs_create_x32("storm_rate_mc", 0644, port_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_MC(port)));
-
-		debugfs_create_x32("storm_rate_bc", 0644, port_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port)));
-
-		debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_PORT_TAG_STS_CTRL 
-				+ (port << 2)));
-	} else {
-		debugfs_create_x32("storm_rate_uc", 0644, port_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_UC_0(port)));
-
-		debugfs_create_x32("storm_rate_mc", 0644, port_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_MC_0(port)));
-
-		debugfs_create_x32("storm_rate_bc", 0644, port_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_BC_0(port)));
-
-		debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_PORT_TAG_STS_CTRL
-				+ (port << 2)));
-	}
-
-	debugfs_create_u32("id", 0444, port_dir, (u32 *)&priv->ports[port].dp->index);
-
-	port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
-	if (!port_ctrl_regset)
-		return -ENOMEM;
-
-	port_ctrl_regset->regs = port_ctrl_regs;
-	port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
-	port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (port << 2));
-	debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
-
-	debugfs_create_file("stp_state", 0600, port_dir, &priv->ports[port], &stp_state_fops);
-	debugfs_create_file("age_out", 0600, port_dir, &priv->ports[port], &age_out_fops);
-	debugfs_create_file("port_egress_rate", 0600, port_dir, &priv->ports[port],
-			    &port_egress_fops);
-	return 0;
-}
-
-static int rtl838x_dbgfs_leds(struct dentry *parent, struct rtl838x_switch_priv *priv)
-{
-	struct dentry *led_dir;
-	int p;
-	char led_sw_p_ctrl_name[20];
-	char port_led_name[20];
-
-	led_dir = debugfs_create_dir("led", parent);
-
-	if (priv->family_id == RTL8380_FAMILY_ID) {
-		debugfs_create_x32("led_glb_ctrl", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8380_LED_GLB_CTRL));
-		debugfs_create_x32("led_mode_sel", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8380_LED_MODE_SEL));
-		debugfs_create_x32("led_mode_ctrl", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8380_LED_MODE_CTRL));
-		debugfs_create_x32("led_p_en_ctrl", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8380_LED_P_EN_CTRL));
-		debugfs_create_x32("led_sw_ctrl", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8380_LED_SW_CTRL));
-		debugfs_create_x32("led0_sw_p_en_ctrl", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8380_LED0_SW_P_EN_CTRL));
-		debugfs_create_x32("led1_sw_p_en_ctrl", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8380_LED1_SW_P_EN_CTRL));
-		debugfs_create_x32("led2_sw_p_en_ctrl", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8380_LED2_SW_P_EN_CTRL));
-		for (p = 0; p < 28; p++) {
-			snprintf(led_sw_p_ctrl_name, sizeof(led_sw_p_ctrl_name),
-				 "led_sw_p_ctrl.%02d", p);
-			debugfs_create_x32(led_sw_p_ctrl_name, 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8380_LED_SW_P_CTRL(p)));
-		}
-	} else if (priv->family_id == RTL8390_FAMILY_ID) {
-		debugfs_create_x32("led_glb_ctrl", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_GLB_CTRL));
-		debugfs_create_x32("led_set_2_3", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_2_3_CTRL));
-		debugfs_create_x32("led_set_0_1", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_0_1_CTRL));
-		for (p = 0; p < 4; p++) {
-			snprintf(port_led_name, sizeof(port_led_name), "led_copr_set_sel.%1d", p);
-			debugfs_create_x32(port_led_name, 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_SET_SEL_CTRL(p << 4)));
-			snprintf(port_led_name, sizeof(port_led_name), "led_fib_set_sel.%1d", p);
-			debugfs_create_x32(port_led_name, 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_SET_SEL_CTRL(p << 4)));
-		}
-		debugfs_create_x32("led_copr_pmask_ctrl_0", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(0)));
-		debugfs_create_x32("led_copr_pmask_ctrl_1", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(32)));
-		debugfs_create_x32("led_fib_pmask_ctrl_0", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(0)));
-		debugfs_create_x32("led_fib_pmask_ctrl_1", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(32)));
-		debugfs_create_x32("led_combo_ctrl_0", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(0)));
-		debugfs_create_x32("led_combo_ctrl_1", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(32)));
-		debugfs_create_x32("led_sw_ctrl", 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_CTRL));
-		for (p = 0; p < 5; p++) {
-			snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_en_ctrl.%1d", p);
-			debugfs_create_x32(port_led_name, 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_EN_CTRL(p * 10)));
-		}
-		for (p = 0; p < 28; p++) {
-			snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_ctrl.%02d", p);
-			debugfs_create_x32(port_led_name, 0644, led_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_CTRL(p)));
-		}
-	}
-	return 0;
-}
-
-void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv)
-{
-	struct dentry *rtl838x_dir;
-	struct dentry *port_dir;
-	struct dentry *mirror_dir;
-	struct debugfs_regset32 *port_ctrl_regset;
-	int ret, i;
-	char lag_name[10];
-	char mirror_name[10];
-
-	pr_info("%s called\n", __func__);
-	rtl838x_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL);
-	if (!rtl838x_dir)
-		rtl838x_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL);
-
-	priv->dbgfs_dir = rtl838x_dir;
-
-	debugfs_create_u32("soc", 0444, rtl838x_dir,
-			   (u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO));
-
-	/* Create one directory per port */
-	for (i = 0; i < priv->cpu_port; i++) {
-		if (priv->ports[i].phy) {
-			ret = rtl838x_dbgfs_port_init(rtl838x_dir, priv, i);
-			if (ret)
-				goto err;
-		}
-	}
-
-	/* Create directory for CPU-port */
-	port_dir = debugfs_create_dir("cpu_port", rtl838x_dir);
-	port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
-	if (!port_ctrl_regset) {
-		ret = -ENOMEM;
-		goto err;
-	}
-
-	port_ctrl_regset->regs = port_ctrl_regs;
-	port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
-	port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (priv->cpu_port << 2));
-	debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
-	debugfs_create_u8("id", 0444, port_dir, &priv->cpu_port);
-
-	/* Create entries for LAGs */
-	for (i = 0; i < priv->n_lags; i++) {
-		snprintf(lag_name, sizeof(lag_name), "lag.%02d", i);
-		if (priv->family_id == RTL8380_FAMILY_ID)
-			debugfs_create_x32(lag_name, 0644, rtl838x_dir,
-				(u32 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));
-		else
-			debugfs_create_x64(lag_name, 0644, rtl838x_dir,
-				(u64 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));
-	}
-
-	/* Create directories for mirror groups */
-	for (i = 0; i < 4; i++) {
-		snprintf(mirror_name, sizeof(mirror_name), "mirror.%1d", i);
-		mirror_dir = debugfs_create_dir(mirror_name, rtl838x_dir);
-		if (priv->family_id == RTL8380_FAMILY_ID) {
-			debugfs_create_x32("ctrl", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_CTRL + i * 4));
-			debugfs_create_x32("ingress_pm", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + priv->r->mir_spm + i * 4));
-			debugfs_create_x32("egress_pm", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + priv->r->mir_dpm + i * 4));
-			debugfs_create_x32("qid", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_QID_CTRL(i)));
-			debugfs_create_x32("rspan_vlan", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL(i)));
-			debugfs_create_x32("rspan_vlan_mac", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(i)));
-			debugfs_create_x32("rspan_tx", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_CTRL));
-			debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL));
-			debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL));
-		} else {
-			debugfs_create_x32("ctrl", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_CTRL + i * 4));
-			debugfs_create_x64("ingress_pm", 0644, mirror_dir,
-				(u64 *)(RTL838X_SW_BASE + priv->r->mir_spm + i * 8));
-			debugfs_create_x64("egress_pm", 0644, mirror_dir,
-				(u64 *)(RTL838X_SW_BASE + priv->r->mir_dpm + i * 8));
-			debugfs_create_x32("rspan_vlan", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_VLAN_CTRL(i)));
-			debugfs_create_x32("rspan_tx", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_CTRL));
-			debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL));
-			debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL));
-			debugfs_create_x64("sample_rate", 0644, mirror_dir,
-				(u64 *)(RTL838X_SW_BASE + RTL839X_MIR_SAMPLE_RATE_CTRL));
-		}
-	}
-
-	if (priv->family_id == RTL8380_FAMILY_ID)
-		debugfs_create_x32("bpdu_flood_mask", 0644, rtl838x_dir,
-				(u32 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));
-	else
-		debugfs_create_x64("bpdu_flood_mask", 0644, rtl838x_dir,
-				(u64 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));
-
-	if (priv->family_id == RTL8380_FAMILY_ID)
-		debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_CTRL));
-	else
-		debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir,
-				(u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_CTRL));
-
-	ret = rtl838x_dbgfs_leds(rtl838x_dir, priv);
-	if (ret)
-		goto err;
-
-	return;
-err:
-	rtl838x_dbgfs_cleanup(priv);
-}
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c
deleted file mode 100644
index c2a230c4cb..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c
+++ /dev/null
@@ -1,1587 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <net/dsa.h>
-#include <linux/if_bridge.h>
-
-#include <asm/mach-rtl838x/mach-rtl83xx.h>
-#include "rtl83xx.h"
-
-
-extern struct rtl83xx_soc_info soc_info;
-
-
-static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
-{
-	mutex_lock(&priv->reg_mutex);
-
-	/* Enable statistics module: all counters plus debug.
-	 * On RTL839x all counters are enabled by default
-	 */
-	if (priv->family_id == RTL8380_FAMILY_ID)
-		sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
-
-	/* Reset statistics counters */
-	sw_w32_mask(0, 1, priv->r->stat_rst);
-
-	mutex_unlock(&priv->reg_mutex);
-}
-
-static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
-{
-	int i;
-	u64 v = 0;
-
-	msleep(1000);
-	/* Enable all ports with a PHY, including the SFP-ports */
-	for (i = 0; i < priv->cpu_port; i++) {
-		if (priv->ports[i].phy)
-			v |= BIT_ULL(i);
-	}
-
-	pr_debug("%s: %16llx\n", __func__, v);
-	priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
-
-	/* PHY update complete, there is no global PHY polling enable bit on the 9300 */
-	if (priv->family_id == RTL8390_FAMILY_ID)
-		sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
-	else if(priv->family_id == RTL9300_FAMILY_ID)
-		sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
-}
-
-const struct rtl83xx_mib_desc rtl83xx_mib[] = {
-	MIB_DESC(2, 0xf8, "ifInOctets"),
-	MIB_DESC(2, 0xf0, "ifOutOctets"),
-	MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
-	MIB_DESC(1, 0xe8, "ifInUcastPkts"),
-	MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
-	MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
-	MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
-	MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
-	MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
-	MIB_DESC(1, 0xd0, "ifOutDiscards"),
-	MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
-	MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
-	MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
-	MIB_DESC(1, 0xc0, ".3LateCollisions"),
-	MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
-	MIB_DESC(1, 0xb8, ".3SymbolErrors"),
-	MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
-	MIB_DESC(1, 0xb0, ".3InPauseFrames"),
-	MIB_DESC(1, 0xac, ".3OutPauseFrames"),
-	MIB_DESC(1, 0xa8, "DropEvents"),
-	MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
-	MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
-	MIB_DESC(1, 0x9c, "CRCAlignErrors"),
-	MIB_DESC(1, 0x98, "tx_UndersizePkts"),
-	MIB_DESC(1, 0x94, "rx_UndersizePkts"),
-	MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
-	MIB_DESC(1, 0x8c, "tx_OversizePkts"),
-	MIB_DESC(1, 0x88, "rx_OversizePkts"),
-	MIB_DESC(1, 0x84, "Fragments"),
-	MIB_DESC(1, 0x80, "Jabbers"),
-	MIB_DESC(1, 0x7c, "Collisions"),
-	MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
-	MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
-	MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
-	MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
-	MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
-	MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
-	MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
-	MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
-	MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
-	MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
-	MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
-	MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
-	MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
-	MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
-	MIB_DESC(1, 0x40, "rxMacDiscards")
-};
-
-
-/* DSA callbacks */
-
-
-static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds, int port)
-{
-	/* The switch does not tag the frames, instead internally the header
-	 * structure for each packet is tagged accordingly.
-	 */
-	return DSA_TAG_PROTO_TRAILER;
-}
-
-/*
- * Initialize all VLANS
- */
-static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
-{
-	struct rtl838x_vlan_info info;
-	int i;
-
-	pr_info("In %s\n", __func__);
-
-	priv->r->vlan_profile_setup(0);
-	priv->r->vlan_profile_setup(1);
-	pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
-	priv->r->vlan_profile_dump(0);
-
-	info.fid = 0;			// Default Forwarding ID / MSTI
-	info.hash_uc_fid = false;	// Do not build the L2 lookup hash with FID, but VID
-	info.hash_mc_fid = false;	// Do the same for Multicast packets
-	info.profile_id = 0;		// Use default Vlan Profile 0
-	info.tagged_ports = 0;		// Initially no port members
-
-	// Initialize all vlans 0-4095
-	for (i = 0; i < MAX_VLANS; i ++)
-		priv->r->vlan_set_tagged(i, &info);
-
-	// reset PVIDs; defaults to 1 on reset
-	for (i = 0; i <= priv->ds->num_ports; i++)
-		sw_w32(0, priv->r->vlan_port_pb + (i << 2));
-
-	// Set forwarding action based on inner VLAN tag
-	for (i = 0; i < priv->cpu_port; i++)
-		priv->r->vlan_fwd_on_inner(i, true);
-}
-
-static int rtl83xx_setup(struct dsa_switch *ds)
-{
-	int i;
-	struct rtl838x_switch_priv *priv = ds->priv;
-	u64 port_bitmap = BIT_ULL(priv->cpu_port);
-
-	pr_debug("%s called\n", __func__);
-
-	/* Disable MAC polling the PHY so that we can start configuration */
-	priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
-
-	for (i = 0; i < ds->num_ports; i++)
-		priv->ports[i].enable = false;
-	priv->ports[priv->cpu_port].enable = true;
-
-	/* Isolate ports from each other: traffic only CPU <-> port */
-	/* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
-	 * traffic from source port i to destination port j
-	 */
-	for (i = 0; i < priv->cpu_port; i++) {
-		if (priv->ports[i].phy) {
-			priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
-					      priv->r->port_iso_ctrl(i));
-			port_bitmap |= BIT_ULL(i);
-		}
-	}
-	priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
-
-	if (priv->family_id == RTL8380_FAMILY_ID)
-		rtl838x_print_matrix();
-	else
-		rtl839x_print_matrix();
-
-	rtl83xx_init_stats(priv);
-
-	rtl83xx_vlan_setup(priv);
-
-	ds->configure_vlan_while_not_filtering = true;
-
-	/* Enable MAC Polling PHY again */
-	rtl83xx_enable_phy_polling(priv);
-	pr_debug("Please wait until PHY is settled\n");
-	msleep(1000);
-	return 0;
-}
-
-static int rtl930x_setup(struct dsa_switch *ds)
-{
-	int i;
-	struct rtl838x_switch_priv *priv = ds->priv;
-	u32 port_bitmap = BIT(priv->cpu_port);
-
-	pr_info("%s called\n", __func__);
-
-	// Enable CSTI STP mode
-//	sw_w32(1, RTL930X_ST_CTRL);
-
-	/* Disable MAC polling the PHY so that we can start configuration */
-	sw_w32(0, RTL930X_SMI_POLL_CTRL);
-
-	// Disable all ports except CPU port
-	for (i = 0; i < ds->num_ports; i++)
-		priv->ports[i].enable = false;
-	priv->ports[priv->cpu_port].enable = true;
-
-	for (i = 0; i < priv->cpu_port; i++) {
-		if (priv->ports[i].phy) {
-			priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
-			port_bitmap |= BIT_ULL(i);
-		}
-	}
-	priv->r->traffic_set(priv->cpu_port, port_bitmap);
-
-	rtl930x_print_matrix();
-
-	// TODO: Initialize statistics
-
-	rtl83xx_vlan_setup(priv);
-
-	ds->configure_vlan_while_not_filtering = true;
-
-	rtl83xx_enable_phy_polling(priv);
-
-	return 0;
-}
-
-static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
-				     unsigned long *supported,
-				     struct phylink_link_state *state)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
-
-	pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
-
-	if (!phy_interface_mode_is_rgmii(state->interface) &&
-	    state->interface != PHY_INTERFACE_MODE_NA &&
-	    state->interface != PHY_INTERFACE_MODE_1000BASEX &&
-	    state->interface != PHY_INTERFACE_MODE_MII &&
-	    state->interface != PHY_INTERFACE_MODE_REVMII &&
-	    state->interface != PHY_INTERFACE_MODE_GMII &&
-	    state->interface != PHY_INTERFACE_MODE_QSGMII &&
-	    state->interface != PHY_INTERFACE_MODE_INTERNAL &&
-	    state->interface != PHY_INTERFACE_MODE_SGMII) {
-		bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
-		dev_err(ds->dev,
-			"Unsupported interface: %d for port %d\n",
-			state->interface, port);
-		return;
-	}
-
-	/* Allow all the expected bits */
-	phylink_set(mask, Autoneg);
-	phylink_set_port_modes(mask);
-	phylink_set(mask, Pause);
-	phylink_set(mask, Asym_Pause);
-
-	/* With the exclusion of MII and Reverse MII, we support Gigabit,
-	 * including Half duplex
-	 */
-	if (state->interface != PHY_INTERFACE_MODE_MII &&
-	    state->interface != PHY_INTERFACE_MODE_REVMII) {
-		phylink_set(mask, 1000baseT_Full);
-		phylink_set(mask, 1000baseT_Half);
-	}
-
-	/* On both the 8380 and 8382, ports 24-27 are SFP ports */
-	if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
-		phylink_set(mask, 1000baseX_Full);
-
-	/* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
-	if (port >=48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
-		phylink_set(mask, 1000baseX_Full);
-
-	phylink_set(mask, 10baseT_Half);
-	phylink_set(mask, 10baseT_Full);
-	phylink_set(mask, 100baseT_Half);
-	phylink_set(mask, 100baseT_Full);
-
-	bitmap_and(supported, supported, mask,
-		   __ETHTOOL_LINK_MODE_MASK_NBITS);
-	bitmap_and(state->advertising, state->advertising, mask,
-		   __ETHTOOL_LINK_MODE_MASK_NBITS);
-}
-
-static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
-					  struct phylink_link_state *state)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	u64 speed;
-	u64 link;
-
-	if (port < 0 || port > priv->cpu_port)
-		return -EINVAL;
-
-	/*
-	 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
-	 * state needs to be read twice in order to read a correct result.
-	 * This would not be necessary for ports connected e.g. to RTL8218D
-	 * PHYs.
-	 */
-	state->link = 0;
-	link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
-	link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
-	if (link & BIT_ULL(port))
-		state->link = 1;
-	pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
-
-	state->duplex = 0;
-	if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
-		state->duplex = 1;
-
-	speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
-	speed >>= (port % 16) << 1;
-	switch (speed & 0x3) {
-	case 0:
-		state->speed = SPEED_10;
-		break;
-	case 1:
-		state->speed = SPEED_100;
-		break;
-	case 2:
-		state->speed = SPEED_1000;
-		break;
-	case 3:
-		if (priv->family_id == RTL9300_FAMILY_ID
-			&& (port == 24 || port == 26)) /* Internal serdes */
-			state->speed = SPEED_2500;
-		else
-			state->speed = SPEED_100; /* Is in fact 500Mbit */
-	}
-
-	state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
-	if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
-		state->pause |= MLO_PAUSE_RX;
-	if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
-		state->pause |= MLO_PAUSE_TX;
-	return 1;
-}
-
-static void rtl83xx_config_interface(int port, phy_interface_t interface)
-{
-	u32 old, int_shift, sds_shift;
-
-	switch (port) {
-	case 24:
-		int_shift = 0;
-		sds_shift = 5;
-		break;
-	case 26:
-		int_shift = 3;
-		sds_shift = 0;
-		break;
-	default:
-		return;
-	}
-
-	old = sw_r32(RTL838X_SDS_MODE_SEL);
-	switch (interface) {
-	case PHY_INTERFACE_MODE_1000BASEX:
-		if ((old >> sds_shift & 0x1f) == 4)
-			return;
-		sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
-		sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
-		break;
-	case PHY_INTERFACE_MODE_SGMII:
-		if ((old >> sds_shift & 0x1f) == 2)
-			return;
-		sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
-		sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
-		break;
-	default:
-		return;
-	}
-	pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
-}
-
-static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
-					unsigned int mode,
-					const struct phylink_link_state *state)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	u32 reg;
-	int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
-
-	pr_debug("%s port %d, mode %x\n", __func__, port, mode);
-
-	// BUG: Make this work on RTL93XX
-	if (priv->family_id >= RTL9300_FAMILY_ID)
-		return;
-
-	if (port == priv->cpu_port) {
-		/* Set Speed, duplex, flow control
-		 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
-		 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
-		 * | MEDIA_SEL
-		 */
-		if (priv->family_id == RTL8380_FAMILY_ID) {
-			sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
-			/* allow CRC errors on CPU-port */
-			sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
-		} else {
-			sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
-		}
-		return;
-	}
-
-	reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
-	/* Auto-Negotiation does not work for MAC in RTL8390 */
-	if (priv->family_id == RTL8380_FAMILY_ID) {
-		if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
-			pr_debug("PHY autonegotiates\n");
-			reg |= BIT(2);
-			sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
-			rtl83xx_config_interface(port, state->interface);
-			return;
-		}
-	}
-
-	if (mode != MLO_AN_FIXED)
-		pr_debug("Fixed state.\n");
-
-	if (priv->family_id == RTL8380_FAMILY_ID) {
-		/* Clear id_mode_dis bit, and the existing port mode, let
-		 * RGMII_MODE_EN bet set by mac_link_{up,down}
-		 */
-		reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
-
-		if (state->pause & MLO_PAUSE_TXRX_MASK) {
-			if (state->pause & MLO_PAUSE_TX)
-				reg |= TX_PAUSE_EN;
-			reg |= RX_PAUSE_EN;
-		}
-	}
-
-	reg &= ~(3 << speed_bit);
-	switch (state->speed) {
-	case SPEED_1000:
-		reg |= 2 << speed_bit;
-		break;
-	case SPEED_100:
-		reg |= 1 << speed_bit;
-		break;
-	}
-
-	if (priv->family_id == RTL8380_FAMILY_ID) {
-		reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
-		if (state->link)
-			reg |= FORCE_LINK_EN;
-		if (state->duplex == DUPLEX_FULL)
-			reg |= DUPLX_MODE;
-	}
-
-	// Disable AN
-	if (priv->family_id == RTL8380_FAMILY_ID)
-		reg &= ~BIT(2);
-	sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
-}
-
-static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
-				     unsigned int mode,
-				     phy_interface_t interface)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	/* Stop TX/RX to port */
-	sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
-}
-
-static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
-				   unsigned int mode,
-				   phy_interface_t interface,
-				   struct phy_device *phydev)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	/* Restart TX/RX to port */
-	sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
-}
-
-static void rtl83xx_get_strings(struct dsa_switch *ds,
-				int port, u32 stringset, u8 *data)
-{
-	int i;
-
-	if (stringset != ETH_SS_STATS)
-		return;
-
-	for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
-		strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
-			ETH_GSTRING_LEN);
-}
-
-static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
-				      uint64_t *data)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	const struct rtl83xx_mib_desc *mib;
-	int i;
-	u64 h;
-
-	for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
-		mib = &rtl83xx_mib[i];
-
-		data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
-		if (mib->size == 2) {
-			h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
-			data[i] |= h << 32;
-		}
-	}
-}
-
-static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
-{
-	if (sset != ETH_SS_STATS)
-		return 0;
-
-	return ARRAY_SIZE(rtl83xx_mib);
-}
-
-static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
-				struct phy_device *phydev)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	u64 v;
-
-	pr_debug("%s: %x %d", __func__, (u32) priv, port);
-	priv->ports[port].enable = true;
-
-	/* enable inner tagging on egress, do not keep any tags */
-	if (priv->family_id == RTL9310_FAMILY_ID)
-		sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
-	else
-		sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
-
-	if (dsa_is_cpu_port(ds, port))
-		return 0;
-
-	/* add port to switch mask of CPU_PORT */
-	priv->r->traffic_enable(priv->cpu_port, port);
-
-	/* add all other ports in the same bridge to switch mask of port */
-	v = priv->r->traffic_get(port);
-	v |= priv->ports[port].pm;
-	priv->r->traffic_set(port, v);
-
-	// TODO: Figure out if this is necessary
-	if (priv->family_id == RTL9300_FAMILY_ID) {
-		sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
-		sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
-	}
-
-	return 0;
-}
-
-static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	u64 v;
-
-	pr_debug("%s %x: %d", __func__, (u32)priv, port);
-	/* you can only disable user ports */
-	if (!dsa_is_user_port(ds, port))
-		return;
-
-	// BUG: This does not work on RTL931X
-	/* remove port from switch mask of CPU_PORT */
-	priv->r->traffic_disable(priv->cpu_port, port);
-
-	/* remove all other ports in the same bridge from switch mask of port */
-	v = priv->r->traffic_get(port);
-	v &= ~priv->ports[port].pm;
-	priv->r->traffic_set(port, v);
-
-	priv->ports[port].enable = false;
-}
-
-static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
-			       struct ethtool_eee *e)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-
-	if (e->eee_enabled && !priv->eee_enabled) {
-		pr_info("Globally enabling EEE\n");
-		priv->r->init_eee(priv, true);
-	}
-
-	priv->r->port_eee_set(priv, port, e->eee_enabled);
-
-	if (e->eee_enabled)
-		pr_info("Enabled EEE for port %d\n", port);
-	else
-		pr_info("Disabled EEE for port %d\n", port);
-	return 0;
-}
-
-static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
-			       struct ethtool_eee *e)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-
-	e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
-
-	priv->r->eee_port_ability(priv, e, port);
-
-	e->eee_enabled = priv->ports[port].eee_enabled;
-
-	e->eee_active = !!(e->advertised & e->lp_advertised);
-
-	return 0;
-}
-
-static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
-			       struct ethtool_eee *e)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-
-	e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
-			| SUPPORTED_2500baseX_Full;
-
-	priv->r->eee_port_ability(priv, e, port);
-
-	e->eee_enabled = priv->ports[port].eee_enabled;
-
-	e->eee_active = !!(e->advertised & e->lp_advertised);
-
-	return 0;
-}
-
-/*
- * Set Switch L2 Aging time, t is time in milliseconds
- * t = 0: aging is disabled
- */
-static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
-
-	/* Convert time in mseconds to internal value */
-	if (t > 0x10000000) { /* Set to maximum */
-		t = t_max;
-	} else {
-		if (priv->family_id == RTL8380_FAMILY_ID)
-			t = ((t * 625) / 1000 + 127) / 128;
-		else
-			t = (t * 5 + 2) / 3;
-	}
-	sw_w32(t, priv->r->l2_ctrl_1);
-	return 0;
-}
-
-static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
-					struct net_device *bridge)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
-	int i;
-
-	pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
-	mutex_lock(&priv->reg_mutex);
-	for (i = 0; i < ds->num_ports; i++) {
-		/* Add this port to the port matrix of the other ports in the
-		 * same bridge. If the port is disabled, port matrix is kept
-		 * and not being setup until the port becomes enabled.
-		 */
-		if (dsa_is_user_port(ds, i) && i != port) {
-			if (dsa_to_port(ds, i)->bridge_dev != bridge)
-				continue;
-			if (priv->ports[i].enable)
-				priv->r->traffic_enable(i, port);
-
-			priv->ports[i].pm |= BIT_ULL(port);
-			port_bitmap |= BIT_ULL(i);
-		}
-	}
-
-	/* Add all other ports to this port matrix. */
-	if (priv->ports[port].enable) {
-		priv->r->traffic_enable(priv->cpu_port, port);
-		v = priv->r->traffic_get(port);
-		v |= port_bitmap;
-		priv->r->traffic_set(port, v);
-	}
-	priv->ports[port].pm |= port_bitmap;
-	mutex_unlock(&priv->reg_mutex);
-
-	return 0;
-}
-
-static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
-					struct net_device *bridge)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
-	int i;
-
-	pr_debug("%s %x: %d", __func__, (u32)priv, port);
-	mutex_lock(&priv->reg_mutex);
-	for (i = 0; i < ds->num_ports; i++) {
-		/* Remove this port from the port matrix of the other ports
-		 * in the same bridge. If the port is disabled, port matrix
-		 * is kept and not being setup until the port becomes enabled.
-		 * And the other port's port matrix cannot be broken when the
-		 * other port is still a VLAN-aware port.
-		 */
-		if (dsa_is_user_port(ds, i) && i != port) {
-			if (dsa_to_port(ds, i)->bridge_dev != bridge)
-				continue;
-			if (priv->ports[i].enable)
-				priv->r->traffic_disable(i, port);
-
-			priv->ports[i].pm |= BIT_ULL(port);
-			port_bitmap &= ~BIT_ULL(i);
-		}
-	}
-
-	/* Add all other ports to this port matrix. */
-	if (priv->ports[port].enable) {
-		v = priv->r->traffic_get(port);
-		v |= port_bitmap;
-		priv->r->traffic_set(port, v);
-	}
-	priv->ports[port].pm &= ~port_bitmap;
-
-	mutex_unlock(&priv->reg_mutex);
-}
-
-void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
-{
-	u32 msti = 0;
-	u32 port_state[4];
-	int index, bit;
-	int pos = port;
-	struct rtl838x_switch_priv *priv = ds->priv;
-	int n = priv->port_width << 1;
-
-	/* Ports above or equal CPU port can never be configured */
-	if (port >= priv->cpu_port)
-		return;
-
-	mutex_lock(&priv->reg_mutex);
-
-	/* For the RTL839x and following, the bits are left-aligned, 838x and 930x
-	 * have 64 bit fields, 839x and 931x have 128 bit fields
-	 */
-	if (priv->family_id == RTL8390_FAMILY_ID)
-		pos += 12;
-	if (priv->family_id == RTL9300_FAMILY_ID)
-		pos += 3;
-	if (priv->family_id == RTL9310_FAMILY_ID)
-		pos += 8;
-
-	index = n - (pos >> 4) - 1;
-	bit = (pos << 1) % 32;
-
-	priv->r->stp_get(priv, msti, port_state);
-
-	pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
-	port_state[index] &= ~(3 << bit);
-
-	switch (state) {
-	case BR_STATE_DISABLED: /* 0 */
-		port_state[index] |= (0 << bit);
-		break;
-	case BR_STATE_BLOCKING:  /* 4 */
-	case BR_STATE_LISTENING: /* 1 */
-		port_state[index] |= (1 << bit);
-		break;
-	case BR_STATE_LEARNING: /* 2 */
-		port_state[index] |= (2 << bit);
-		break;
-	case BR_STATE_FORWARDING: /* 3*/
-		port_state[index] |= (3 << bit);
-	default:
-		break;
-	}
-
-	priv->r->stp_set(priv, msti, port_state);
-
-	mutex_unlock(&priv->reg_mutex);
-}
-
-void rtl83xx_fast_age(struct dsa_switch *ds, int port)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
-
-	pr_debug("FAST AGE port %d\n", port);
-	mutex_lock(&priv->reg_mutex);
-	/* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
-	 * port fields:
-	 * 0-4: Replacing port
-	 * 5-9: Flushed/replaced port
-	 * 10-21: FVID
-	 * 22: Entry types: 1: dynamic, 0: also static
-	 * 23: Match flush port
-	 * 24: Match FVID
-	 * 25: Flush (0) or replace (1) L2 entries
-	 * 26: Status of action (1: Start, 0: Done)
-	 */
-	sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
-
-	do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
-
-	mutex_unlock(&priv->reg_mutex);
-}
-
-void rtl930x_fast_age(struct dsa_switch *ds, int port)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-
-	pr_debug("FAST AGE port %d\n", port);
-	mutex_lock(&priv->reg_mutex);
-	sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
-
-	sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
-
-	do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
-
-	mutex_unlock(&priv->reg_mutex);
-}
-
-static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
-				  bool vlan_filtering)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-
-	pr_debug("%s: port %d\n", __func__, port);
-	mutex_lock(&priv->reg_mutex);
-
-	if (vlan_filtering) {
-		/* Enable ingress and egress filtering
-		 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
-		 * the filter action:
-		 * 0: Always Forward
-		 * 1: Drop packet
-		 * 2: Trap packet to CPU port
-		 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
-		 */
-		if (port != priv->cpu_port)
-			sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
-				    priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
-		sw_w32_mask(0, BIT(port % 32), priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
-	} else {
-		/* Disable ingress and egress filtering */
-		if (port != priv->cpu_port)
-			sw_w32_mask(0b11 << ((port % 16) << 1), 0,
-				    priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
-		sw_w32_mask(BIT(port % 32), 0, priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
-	}
-
-	/* Do we need to do something to the CPU-Port, too? */
-	mutex_unlock(&priv->reg_mutex);
-
-	return 0;
-}
-
-static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
-				const struct switchdev_obj_port_vlan *vlan)
-{
-	struct rtl838x_vlan_info info;
-	struct rtl838x_switch_priv *priv = ds->priv;
-
-	priv->r->vlan_tables_read(0, &info);
-
-	pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
-		info.tagged_ports, info.untagged_ports, info.profile_id,
-		info.hash_mc_fid, info.hash_uc_fid, info.fid);
-
-	priv->r->vlan_tables_read(1, &info);
-	pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
-		info.tagged_ports, info.untagged_ports, info.profile_id,
-		info.hash_mc_fid, info.hash_uc_fid, info.fid);
-	priv->r->vlan_set_untagged(1, info.untagged_ports);
-	pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
-
-	priv->r->vlan_set_tagged(1, &info);
-	pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
-
-	mutex_unlock(&priv->reg_mutex);
-	return 0;
-}
-
-static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
-			    const struct switchdev_obj_port_vlan *vlan)
-{
-	struct rtl838x_vlan_info info;
-	struct rtl838x_switch_priv *priv = ds->priv;
-	int v;
-
-	pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
-		port, vlan->vid_begin, vlan->vid_end, vlan->flags);
-
-	if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
-		dev_err(priv->dev, "VLAN out of range: %d - %d",
-			vlan->vid_begin, vlan->vid_end);
-		return;
-	}
-
-	mutex_lock(&priv->reg_mutex);
-
-	if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
-		for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
-			if (!v)
-				continue;
-			/* Set both inner and outer PVID of the port */
-			sw_w32((v << 16) | v << 2, priv->r->vlan_port_pb + (port << 2));
-			priv->ports[port].pvid = vlan->vid_end;
-		}
-	}
-
-	for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
-		/* Get port memberships of this vlan */
-		priv->r->vlan_tables_read(v, &info);
-
-		/* new VLAN? */
-		if (!info.tagged_ports) {
-			info.fid = 0;
-			info.hash_mc_fid = false;
-			info.hash_uc_fid = false;
-			info.profile_id = 0;
-		}
-
-		/* sanitize untagged_ports - must be a subset */
-		if (info.untagged_ports & ~info.tagged_ports)
-			info.untagged_ports = 0;
-
-		info.tagged_ports |= BIT_ULL(port);
-		if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
-			info.untagged_ports |= BIT_ULL(port);
-
-		priv->r->vlan_set_untagged(v, info.untagged_ports);
-		pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
-
-		priv->r->vlan_set_tagged(v, &info);
-		pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
-	}
-
-	mutex_unlock(&priv->reg_mutex);
-}
-
-static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
-			    const struct switchdev_obj_port_vlan *vlan)
-{
-	struct rtl838x_vlan_info info;
-	struct rtl838x_switch_priv *priv = ds->priv;
-	int v;
-	u16 pvid;
-
-	pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
-		port, vlan->vid_begin, vlan->vid_end, vlan->flags);
-
-	if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
-		dev_err(priv->dev, "VLAN out of range: %d - %d",
-			vlan->vid_begin, vlan->vid_end);
-		return -ENOTSUPP;
-	}
-
-	mutex_lock(&priv->reg_mutex);
-	pvid = priv->ports[port].pvid;
-
-	for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
-		/* Reset to default if removing the current PVID */
-		if (v == pvid)
-			sw_w32(0, priv->r->vlan_port_pb + (port << 2));
-
-		/* Get port memberships of this vlan */
-		priv->r->vlan_tables_read(v, &info);
-
-		/* remove port from both tables */
-		info.untagged_ports &= (~BIT_ULL(port));
-		info.tagged_ports &= (~BIT_ULL(port));
-
-		priv->r->vlan_set_untagged(v, info.untagged_ports);
-		pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
-
-		priv->r->vlan_set_tagged(v, &info);
-		pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
-	}
-	mutex_unlock(&priv->reg_mutex);
-
-	return 0;
-}
-
-static void dump_l2_entry(struct rtl838x_l2_entry *e)
-{
-	pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
-		e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
-		e->vid, e->rvid, e->port, e->valid);
-
-	if (e->type != L2_MULTICAST) {
-		pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
-			e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
-		pr_info("  block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n",
-		e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
-	}
-	if (e->type == L2_MULTICAST)
-		pr_info("  L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index);
-	if (e->is_ip_mc || e->is_ipv6_mc)
-		pr_info("  mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
-			e->mc_portmask_index, e->mc_gip, e->mc_sip);
-	pr_info("  stack_dev: %d\n", e->stack_dev);
-	if (e->next_hop)
-		pr_info("  nh_route_id: %d\n", e->nh_route_id);
-}
-
-static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
-{
-	e->is_ip_mc = e->is_ipv6_mc  = false;
-	e->valid = true;
-	e->age = 3;
-	e->port = port,
-	e->vid = vid;
-	u64_to_ether_addr(mac, e->mac);
-}
-
-static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,
-				      struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
-{
-	e->is_ip_mc = e->is_ipv6_mc  = false;
-	e->valid = true;
-	e->mc_portmask_index = mc_group;
-	e->type = L2_MULTICAST;
-	e->rvid = e->vid = vid;
-	pr_debug("%s: vid: %d, rvid: %d\n", __func__, e->vid, e->rvid);
-	u64_to_ether_addr(mac, e->mac);
-}
-
-/*
- * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
- * over the entries in the bucket until either a matching entry is found or an empty slot
- * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
- * when an empty slot was found and must exist is false, the index of the slot is returned
- * when no slots are available returns -1
- */
-static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
-				     bool must_exist, struct rtl838x_l2_entry *e)
-{
-	int i, idx = -1;
-	u32 key = priv->r->l2_hash_key(priv, seed);
-	u64 entry;
-
-	pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
-	// Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
-	for (i = 0; i < priv->l2_bucket_size; i++) {
-		entry = priv->r->read_l2_entry_using_hash(key, i, e);
-		pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
-		if (must_exist && !e->valid)
-			continue;
-		if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
-			idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
-			break;
-		}
-	}
-
-	return idx;
-}
-
-/*
- * Uses the seed to identify an entry in the CAM by looping over all its entries
- * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
- * when an empty slot was found the index of the slot is returned
- * when no slots are available returns -1
- */
-static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
-				     bool must_exist, struct rtl838x_l2_entry *e)
-{
-	int i, idx = -1;
-	u64 entry;
-
-	for (i = 0; i < 64; i++) {
-		entry = priv->r->read_cam(i, e);
-		if (!must_exist && !e->valid) {
-			if (idx < 0) /* First empty entry? */
-				idx = i;
-			break;
-		} else if ((entry & 0x0fffffffffffffffULL) == seed) {
-			pr_debug("Found entry in CAM\n");
-			idx = i;
-			break;
-		}
-	}
-	return idx;
-}
-
-static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
-				const unsigned char *addr, u16 vid)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	u64 mac = ether_addr_to_u64(addr);
-	struct rtl838x_l2_entry e;
-	int err = 0, idx;
-	u64 seed = priv->r->l2_hash_seed(mac, vid);
-
-	mutex_lock(&priv->reg_mutex);
-
-	idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
-
-	// Found an existing or empty entry
-	if (idx >= 0) {
-		rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
-		priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
-		goto out;
-	}
-
-	// Hash buckets full, try CAM
-	rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
-
-	if (idx >= 0) {
-		rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
-		priv->r->write_cam(idx, &e);
-		goto out;
-	}
-
-	err = -ENOTSUPP;
-out:
-	mutex_unlock(&priv->reg_mutex);
-	return err;
-}
-
-static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
-			   const unsigned char *addr, u16 vid)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	u64 mac = ether_addr_to_u64(addr);
-	struct rtl838x_l2_entry e;
-	int err = 0, idx;
-	u64 seed = priv->r->l2_hash_seed(mac, vid);
-
-	pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
-	mutex_lock(&priv->reg_mutex);
-
-	idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
-
-	pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
-	if (idx >= 0) {
-		e.valid = false;
-		dump_l2_entry(&e);
-		priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
-		goto out;
-	}
-
-	/* Check CAM for spillover from hash buckets */
-	rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
-
-	if (idx >= 0) {
-		e.valid = false;
-		priv->r->write_cam(idx, &e);
-		goto out;
-	}
-	err = -ENOENT;
-out:
-	mutex_unlock(&priv->reg_mutex);
-	return err;
-}
-
-static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
-				 dsa_fdb_dump_cb_t *cb, void *data)
-{
-	struct rtl838x_l2_entry e;
-	struct rtl838x_switch_priv *priv = ds->priv;
-	int i;
-	u32 fid, pkey;
-	u64 mac;
-
-	mutex_lock(&priv->reg_mutex);
-
-	for (i = 0; i < priv->fib_entries; i++) {
-		priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
-
-		if (!e.valid)
-			continue;
-
-		if (e.port == port) {
-			fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff);
-			mac = ether_addr_to_u64(&e.mac[0]);
-			pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid));
-			fid = (pkey & 0x3ff) | (fid & ~0x3ff);
-			pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n",
-				i, i >> 2, i & 0x3, mac, fid, e.rvid);
-			dump_l2_entry(&e);
-			u64 seed = priv->r->l2_hash_seed(mac, e.rvid);
-			u32 key = priv->r->l2_hash_key(priv, seed);
-			pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key);
-			cb(e.mac, e.vid, e.is_static, data);
-		}
-		if (e.type == L2_MULTICAST) {
-			u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index);
-			if (portmask & BIT_ULL(port)) {
-				dump_l2_entry(&e);
-				pr_info("  PM: %016llx\n", portmask);
-			}
-		}
-	}
-
-	for (i = 0; i < 64; i++) {
-		priv->r->read_cam(i, &e);
-
-		if (!e.valid)
-			continue;
-
-		if (e.port == port)
-			cb(e.mac, e.vid, e.is_static, data);
-	}
-
-	mutex_unlock(&priv->reg_mutex);
-	return 0;
-}
-
-static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
-					const struct switchdev_obj_port_mdb *mdb)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-
-	if (priv->id >= 0x9300)
-		return -EOPNOTSUPP;
-
-	return 0;
-}
-
-static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
-{
-	int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
-	u64 portmask;
-
-	if (mc_group >= MAX_MC_GROUPS - 1)
-		return -1;
-
-	pr_debug("Using MC group %d\n", mc_group);
-	set_bit(mc_group, priv->mc_group_bm);
-	mc_group++;  // We cannot use group 0, as this is used for lookup miss flooding
-	portmask = BIT_ULL(port);
-	priv->r->write_mcast_pmask(mc_group, portmask);
-
-	return mc_group;
-}
-
-static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
-{
-	u64 portmask = priv->r->read_mcast_pmask(mc_group);
-
-	portmask |= BIT_ULL(port);
-	priv->r->write_mcast_pmask(mc_group, portmask);
-
-	return portmask;
-}
-
-static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
-{
-	u64 portmask = priv->r->read_mcast_pmask(mc_group);
-
-	portmask &= ~BIT_ULL(port);
-	priv->r->write_mcast_pmask(mc_group, portmask);
-	if (!portmask)
-		clear_bit(mc_group, priv->mc_group_bm);
-
-	return portmask;
-}
-
-static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
-			const struct switchdev_obj_port_mdb *mdb)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	u64 mac = ether_addr_to_u64(mdb->addr);
-	struct rtl838x_l2_entry e;
-	int err = 0, idx;
-	int vid = mdb->vid;
-	u64 seed = priv->r->l2_hash_seed(mac, vid);
-	int mc_group;
-
-	pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
-	mutex_lock(&priv->reg_mutex);
-
-	idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
-
-	// Found an existing or empty entry
-	if (idx >= 0) {
-		if (e.valid) {
-			pr_debug("Found an existing entry %016llx, mc_group %d\n",
-				ether_addr_to_u64(e.mac), e.mc_portmask_index);
-			rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
-		} else {
-			pr_debug("New entry for seed %016llx\n", seed);
-			mc_group = rtl83xx_mc_group_alloc(priv, port);
-			if (mc_group < 0) {
-				err = -ENOTSUPP;
-				goto out;
-			}
-			rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
-			priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
-		}
-		goto out;
-	}
-
-	// Hash buckets full, try CAM
-	rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
-
-	if (idx >= 0) {
-		if (e.valid) {
-			pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
-				 ether_addr_to_u64(e.mac), e.mc_portmask_index);
-			rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
-		} else {
-			pr_debug("New entry\n");
-			mc_group = rtl83xx_mc_group_alloc(priv, port);
-			if (mc_group < 0) {
-				err = -ENOTSUPP;
-				goto out;
-			}
-			rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
-			priv->r->write_cam(idx, &e);
-		}
-		goto out;
-	}
-
-	err = -ENOTSUPP;
-out:
-	mutex_unlock(&priv->reg_mutex);
-	if (err)
-		dev_err(ds->dev, "failed to add MDB entry\n");
-}
-
-int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
-			const struct switchdev_obj_port_mdb *mdb)
-{
-	struct rtl838x_switch_priv *priv = ds->priv;
-	u64 mac = ether_addr_to_u64(mdb->addr);
-	struct rtl838x_l2_entry e;
-	int err = 0, idx;
-	int vid = mdb->vid;
-	u64 seed = priv->r->l2_hash_seed(mac, vid);
-	u64 portmask;
-
-	pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
-	mutex_lock(&priv->reg_mutex);
-
-	idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
-
-	pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
-	if (idx >= 0) {
-		portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
-		if (!portmask) {
-			e.valid = false;
-			// dump_l2_entry(&e);
-			priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
-		}
-		goto out;
-	}
-
-	/* Check CAM for spillover from hash buckets */
-	rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
-
-	if (idx >= 0) {
-		portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
-		if (!portmask) {
-			e.valid = false;
-			// dump_l2_entry(&e);
-			priv->r->write_cam(idx, &e);
-		}
-		goto out;
-	}
-	// TODO: Re-enable with a newer kernel: err = -ENOENT;
-out:
-	mutex_unlock(&priv->reg_mutex);
-	return err;
-}
-
-static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
-				   struct dsa_mall_mirror_tc_entry *mirror,
-				   bool ingress)
-{
-	/* We support 4 mirror groups, one destination port per group */
-	int group;
-	struct rtl838x_switch_priv *priv = ds->priv;
-	int ctrl_reg, dpm_reg, spm_reg;	
-
-	pr_debug("In %s\n", __func__);
-
-	for (group = 0; group < 4; group++) {
-		if (priv->mirror_group_ports[group] == mirror->to_local_port)
-			break;
-	}
-	if (group >= 4) {
-		for (group = 0; group < 4; group++) {
-			if (priv->mirror_group_ports[group] < 0)
-				break;
-		}
-	}
-
-	if (group >= 4)
-		return -ENOSPC;
-
-	ctrl_reg = priv->r->mir_ctrl + group * 4;
-	dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
-	spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
-
-	pr_debug("Using group %d\n", group);
-	mutex_lock(&priv->reg_mutex);
-
-	if (priv->family_id == RTL8380_FAMILY_ID) {
-		/* Enable mirroring to port across VLANs (bit 11) */
-		sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
-	} else {
-		/* Enable mirroring to destination port */
-		sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
-	}
-
-	if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
-		mutex_unlock(&priv->reg_mutex);
-		return -EEXIST;
-	}
-	if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
-		mutex_unlock(&priv->reg_mutex);
-		return -EEXIST;
-	}
-
-	if (ingress)
-		priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
-	else
-		priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
-
-	priv->mirror_group_ports[group] = mirror->to_local_port;
-	mutex_unlock(&priv->reg_mutex);
-	return 0;
-}
-
-static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
-				    struct dsa_mall_mirror_tc_entry *mirror)
-{
-	int group = 0;
-	struct rtl838x_switch_priv *priv = ds->priv;
-	int ctrl_reg, dpm_reg, spm_reg;
-
-	pr_debug("In %s\n", __func__);
-	for (group = 0; group < 4; group++) {
-		if (priv->mirror_group_ports[group] == mirror->to_local_port)
-			break;
-	}
-	if (group >= 4)
-		return;
-
-	ctrl_reg = priv->r->mir_ctrl + group * 4;
-	dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
-	spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
-
-	mutex_lock(&priv->reg_mutex);
-	if (mirror->ingress) {
-		/* Ingress, clear source port matrix */
-		priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
-	} else {
-		/* Egress, clear destination port matrix */
-		priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
-	}
-
-	if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
-		priv->mirror_group_ports[group] = -1;
-		sw_w32(0, ctrl_reg);
-	}
-
-	mutex_unlock(&priv->reg_mutex);
-}
-
-int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
-{
-	u32 val;
-	u32 offset = 0;
-	struct rtl838x_switch_priv *priv = ds->priv;
-
-	if (phy_addr >= 24 && phy_addr <= 27
-		&& priv->ports[24].phy == PHY_RTL838X_SDS) {
-		if (phy_addr == 26)
-			offset = 0x100;
-		val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
-		return val;
-	}
-
-	read_phy(phy_addr, 0, phy_reg, &val);
-	return val;
-}
-
-int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
-{
-	u32 offset = 0;
-	struct rtl838x_switch_priv *priv = ds->priv;
-
-	if (phy_addr >= 24 && phy_addr <= 27
-	     && priv->ports[24].phy == PHY_RTL838X_SDS) {
-		if (phy_addr == 26)
-			offset = 0x100;
-		sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
-		return 0;
-	}
-	return write_phy(phy_addr, 0, phy_reg, val);
-}
-
-const struct dsa_switch_ops rtl83xx_switch_ops = {
-	.get_tag_protocol	= rtl83xx_get_tag_protocol,
-	.setup			= rtl83xx_setup,
-
-	.phy_read		= dsa_phy_read,
-	.phy_write		= dsa_phy_write,
-
-	.phylink_validate	= rtl83xx_phylink_validate,
-	.phylink_mac_link_state	= rtl83xx_phylink_mac_link_state,
-	.phylink_mac_config	= rtl83xx_phylink_mac_config,
-	.phylink_mac_link_down	= rtl83xx_phylink_mac_link_down,
-	.phylink_mac_link_up	= rtl83xx_phylink_mac_link_up,
-
-	.get_strings		= rtl83xx_get_strings,
-	.get_ethtool_stats	= rtl83xx_get_ethtool_stats,
-	.get_sset_count		= rtl83xx_get_sset_count,
-
-	.port_enable		= rtl83xx_port_enable,
-	.port_disable		= rtl83xx_port_disable,
-
-	.get_mac_eee		= rtl83xx_get_mac_eee,
-	.set_mac_eee		= rtl83xx_set_mac_eee,
-
-	.set_ageing_time	= rtl83xx_set_l2aging,
-	.port_bridge_join	= rtl83xx_port_bridge_join,
-	.port_bridge_leave	= rtl83xx_port_bridge_leave,
-	.port_stp_state_set	= rtl83xx_port_stp_state_set,
-	.port_fast_age		= rtl83xx_fast_age,
-
-	.port_vlan_filtering	= rtl83xx_vlan_filtering,
-	.port_vlan_prepare	= rtl83xx_vlan_prepare,
-	.port_vlan_add		= rtl83xx_vlan_add,
-	.port_vlan_del		= rtl83xx_vlan_del,
-
-	.port_fdb_add		= rtl83xx_port_fdb_add,
-	.port_fdb_del		= rtl83xx_port_fdb_del,
-	.port_fdb_dump		= rtl83xx_port_fdb_dump,
-
-	.port_mdb_prepare	= rtl83xx_port_mdb_prepare,
-	.port_mdb_add		= rtl83xx_port_mdb_add,
-	.port_mdb_del		= rtl83xx_port_mdb_del,
-
-	.port_mirror_add	= rtl83xx_port_mirror_add,
-	.port_mirror_del	= rtl83xx_port_mirror_del,
-};
-
-const struct dsa_switch_ops rtl930x_switch_ops = {
-	.get_tag_protocol	= rtl83xx_get_tag_protocol,
-	.setup			= rtl930x_setup,
-
-	.phy_read		= dsa_phy_read,
-	.phy_write		= dsa_phy_write,
-
-	.phylink_validate	= rtl83xx_phylink_validate,
-	.phylink_mac_link_state	= rtl83xx_phylink_mac_link_state,
-	.phylink_mac_config	= rtl83xx_phylink_mac_config,
-	.phylink_mac_link_down	= rtl83xx_phylink_mac_link_down,
-	.phylink_mac_link_up	= rtl83xx_phylink_mac_link_up,
-
-	.get_strings		= rtl83xx_get_strings,
-	.get_ethtool_stats	= rtl83xx_get_ethtool_stats,
-	.get_sset_count		= rtl83xx_get_sset_count,
-
-	.port_enable		= rtl83xx_port_enable,
-	.port_disable		= rtl83xx_port_disable,
-
-	.get_mac_eee		= rtl93xx_get_mac_eee,
-	.set_mac_eee		= rtl83xx_set_mac_eee,
-
-	.set_ageing_time	= rtl83xx_set_l2aging,
-	.port_bridge_join	= rtl83xx_port_bridge_join,
-	.port_bridge_leave	= rtl83xx_port_bridge_leave,
-	.port_stp_state_set	= rtl83xx_port_stp_state_set,
-	.port_fast_age		= rtl930x_fast_age,
-
-	.port_vlan_filtering	= rtl83xx_vlan_filtering,
-	.port_vlan_prepare	= rtl83xx_vlan_prepare,
-	.port_vlan_add		= rtl83xx_vlan_add,
-	.port_vlan_del		= rtl83xx_vlan_del,
-
-	.port_fdb_add		= rtl83xx_port_fdb_add,
-	.port_fdb_del		= rtl83xx_port_fdb_del,
-	.port_fdb_dump		= rtl83xx_port_fdb_dump,
-
-	.port_mdb_prepare	= rtl83xx_port_mdb_prepare,
-	.port_mdb_add		= rtl83xx_port_mdb_add,
-	.port_mdb_del		= rtl83xx_port_mdb_del,
-
-};
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/qos.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/qos.c
deleted file mode 100644
index 2fc8d37f3e..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/qos.c
+++ /dev/null
@@ -1,576 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <net/dsa.h>
-#include <linux/delay.h>
-
-#include <asm/mach-rtl838x/mach-rtl83xx.h>
-#include "rtl83xx.h"
-
-static struct rtl838x_switch_priv *switch_priv;
-extern struct rtl83xx_soc_info soc_info;
-
-enum scheduler_type {
-	WEIGHTED_FAIR_QUEUE = 0,
-	WEIGHTED_ROUND_ROBIN,
-};
-
-int max_available_queue[] = {0, 1, 2, 3, 4, 5, 6, 7};
-int default_queue_weights[] = {1, 1, 1, 1, 1, 1, 1, 1};
-int dot1p_priority_remapping[] = {0, 1, 2, 3, 4, 5, 6, 7};
-
-static void rtl839x_read_scheduling_table(int port)
-{
-	u32 cmd = 1 << 9 /* Execute cmd */
-		| 0 << 8 /* Read */
-		| 0 << 6 /* Table type 0b00 */
-		| (port & 0x3f);
-	rtl839x_exec_tbl2_cmd(cmd);
-}
-
-static void rtl839x_write_scheduling_table(int port)
-{
-	u32 cmd = 1 << 9 /* Execute cmd */
-		| 1 << 8 /* Write */
-		| 0 << 6 /* Table type 0b00 */
-		| (port & 0x3f);
-	rtl839x_exec_tbl2_cmd(cmd);
-}
-
-static void rtl839x_read_out_q_table(int port)
-{
-	u32 cmd = 1 << 9 /* Execute cmd */
-		| 0 << 8 /* Read */
-		| 2 << 6 /* Table type 0b10 */
-		| (port & 0x3f);
-	rtl839x_exec_tbl2_cmd(cmd);
-}
-
-static void rtl838x_storm_enable(struct rtl838x_switch_priv *priv, int port, bool enable)
-{
-	// Enable Storm control for that port for UC, MC, and BC
-	if (enable)
-		sw_w32(0x7, RTL838X_STORM_CTRL_LB_CTRL(port));
-	else
-		sw_w32(0x0, RTL838X_STORM_CTRL_LB_CTRL(port));
-}
-
-u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port)
-{
-	u32 rate;
-
-	if (port > priv->cpu_port)
-		return 0;
-	rate = sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port)) & 0x3fff;
-	return rate;
-}
-
-/* Sets the rate limit, 10MBit/s is equal to a rate value of 625 */
-int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate)
-{
-	u32 old_rate;
-
-	if (port > priv->cpu_port)
-		return -1;
-
-	old_rate = sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port));
-	sw_w32(rate, RTL838X_SCHED_P_EGR_RATE_CTRL(port));
-
-	return old_rate;
-}
-
-/* Set the rate limit for a particular queue in Bits/s
- * units of the rate is 16Kbps
- */
-void rtl838x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port,
-					    int queue, u32 rate)
-{
-	if (port > priv->cpu_port)
-		return;
-	if (queue > 7)
-		return;
-	sw_w32(rate, RTL838X_SCHED_Q_EGR_RATE_CTRL(port, queue));
-}
-
-static void rtl838x_rate_control_init(struct rtl838x_switch_priv *priv)
-{
-	int i;
-
-	pr_info("Enabling Storm control\n");
-	// TICK_PERIOD_PPS
-	if (priv->id == 0x8380)
-		sw_w32_mask(0x3ff << 20, 434 << 20, RTL838X_SCHED_LB_TICK_TKN_CTRL_0);
-
-	// Set burst rate
-	sw_w32(0x00008000, RTL838X_STORM_CTRL_BURST_0); // UC
-	sw_w32(0x80008000, RTL838X_STORM_CTRL_BURST_1); // MC and BC
-
-	// Set burst Packets per Second to 32
-	sw_w32(0x00000020, RTL838X_STORM_CTRL_BURST_PPS_0); // UC
-	sw_w32(0x00200020, RTL838X_STORM_CTRL_BURST_PPS_1); // MC and BC
-
-	// Include IFG in storm control, rate based on bytes/s (0 = packets)
-	sw_w32_mask(0, 1 << 6 | 1 << 5, RTL838X_STORM_CTRL);
-	// Bandwidth control includes preamble and IFG (10 Bytes)
-	sw_w32_mask(0, 1, RTL838X_SCHED_CTRL);
-
-	// On SoCs except RTL8382M, set burst size of port egress
-	if (priv->id != 0x8382)
-		sw_w32_mask(0xffff, 0x800, RTL838X_SCHED_LB_THR);
-
-	/* Enable storm control on all ports with a PHY and limit rates,
-	 * for UC and MC for both known and unknown addresses */
-	for (i = 0; i < priv->cpu_port; i++) {
-		if (priv->ports[i].phy) {
-			sw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_UC(i));
-			sw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_MC(i));
-			sw_w32(0x8000, RTL838X_STORM_CTRL_PORT_BC(i));
-			rtl838x_storm_enable(priv, i, true);
-		}
-	}
-
-	// Attack prevention, enable all attack prevention measures
-	//sw_w32(0x1ffff, RTL838X_ATK_PRVNT_CTRL);
-	/* Attack prevention, drop (bit = 0) problematic packets on all ports.
-	 * Setting bit = 1 means: trap to CPU
-	 */
-	//sw_w32(0, RTL838X_ATK_PRVNT_ACT);
-	// Enable attack prevention on all ports
-	//sw_w32(0x0fffffff, RTL838X_ATK_PRVNT_PORT_EN);
-}
-
-/* Sets the rate limit, 10MBit/s is equal to a rate value of 625 */
-u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port)
-{
-	u32 rate;
-
-	pr_debug("%s: Getting egress rate on port %d to %d\n", __func__, port, rate);
-	if (port >= priv->cpu_port)
-		return 0;
-
-	mutex_lock(&priv->reg_mutex);
-
-	rtl839x_read_scheduling_table(port);
-
-	rate = sw_r32(RTL839X_TBL_ACCESS_DATA_2(7));
-	rate <<= 12;
-	rate |= sw_r32(RTL839X_TBL_ACCESS_DATA_2(8)) >> 20;
-
-	mutex_unlock(&priv->reg_mutex);
-
-	return rate;
-}
-
-/* Sets the rate limit, 10MBit/s is equal to a rate value of 625, returns previous rate */
-int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate)
-{
-	u32 old_rate;
-
-	pr_debug("%s: Setting egress rate on port %d to %d\n", __func__, port, rate);
-	if (port >= priv->cpu_port)
-		return -1;
-
-	mutex_lock(&priv->reg_mutex);
-
-	rtl839x_read_scheduling_table(port);
-
-	old_rate = sw_r32(RTL839X_TBL_ACCESS_DATA_2(7)) & 0xff;
-	old_rate <<= 12;
-	old_rate |= sw_r32(RTL839X_TBL_ACCESS_DATA_2(8)) >> 20;
-	sw_w32_mask(0xff, (rate >> 12) & 0xff, RTL839X_TBL_ACCESS_DATA_2(7));
-	sw_w32_mask(0xfff << 20, rate << 20, RTL839X_TBL_ACCESS_DATA_2(8));
-
-	rtl839x_write_scheduling_table(port);
-	
-	mutex_unlock(&priv->reg_mutex);
-
-	return old_rate;
-}
-
-/* Set the rate limit for a particular queue in Bits/s
- * units of the rate is 16Kbps
- */
-void rtl839x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port,
-					int queue, u32 rate)
-{
-	int lsb = 128 + queue * 20;
-	int low_byte = 8 - (lsb >> 5);
-	int start_bit = lsb - (low_byte << 5);
-	u32 high_mask = 0xfffff	>> (32 - start_bit);
-
-	pr_debug("%s: Setting egress rate on port %d, queue %d to %d\n",
-		__func__, port, queue, rate);
-	if (port >= priv->cpu_port)
-		return;
-	if (queue > 7)
-		return;
-
-	mutex_lock(&priv->reg_mutex);
-
-	rtl839x_read_scheduling_table(port);
-
-	sw_w32_mask(0xfffff << start_bit, (rate & 0xfffff) << start_bit,
-		    RTL839X_TBL_ACCESS_DATA_2(low_byte));
-	if (high_mask)
-		sw_w32_mask(high_mask, (rate & 0xfffff) >> (32- start_bit),
-			    RTL839X_TBL_ACCESS_DATA_2(low_byte - 1));
-
-	rtl839x_write_scheduling_table(port);
-
-	mutex_unlock(&priv->reg_mutex);
-}
-
-static void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv)
-{
-	int p, q;
-
-	pr_info("%s: enabling rate control\n", __func__);
-	/* Tick length and token size settings for SoC with 250MHz,
-	 * RTL8350 family would use 50MHz
-	 */
-	// Set the special tick period
-	sw_w32(976563, RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL);
-	// Ingress tick period and token length 10G
-	sw_w32(18 << 11 | 151, RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0);
-	// Ingress tick period and token length 1G
-	sw_w32(245 << 11 | 129, RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1);
-	// Egress tick period 10G, bytes/token 10G and tick period 1G, bytes/token 1G
-	sw_w32(18 << 24 | 151 << 16 | 185 << 8 | 97, RTL839X_SCHED_LB_TICK_TKN_CTRL);
-	// Set the tick period of the CPU and the Token Len
-	sw_w32(3815 << 8 | 1, RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL);
-
-	// Set the Weighted Fair Queueing burst size
-	sw_w32_mask(0xffff, 4500, RTL839X_SCHED_LB_THR);
-
-	// Storm-rate calculation is based on bytes/sec (bit 5), include IFG (bit 6)
-	sw_w32_mask(0, 1 << 5 | 1 << 6, RTL839X_STORM_CTRL);
-
-	/* Based on the rate control mode being bytes/s
-	 * set tick period and token length for 10G
-	 */
-	sw_w32(18 << 10 | 151, RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_0);
-	/* and for 1G ports */
-	sw_w32(246 << 10 | 129, RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_1);
-
-	/* Set default burst rates on all ports (the same for 1G / 10G) with a PHY
-	 * for UC, MC and BC
-	 * For 1G port, the minimum burst rate is 1700, maximum 65535,
-	 * For 10G ports it is 2650 and 1048575 respectively */
-	for (p = 0; p < priv->cpu_port; p++) {
-		if (priv->ports[p].phy && !priv->ports[p].is10G) {
-			sw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_UC_1(p));
-			sw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_MC_1(p));
-			sw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_BC_1(p));
-		}
-	}
-
-	/* Setup ingress/egress per-port rate control */
-	for (p = 0; p < priv->cpu_port; p++) {
-		if (!priv->ports[p].phy)
-			continue;
-
-		if (priv->ports[p].is10G)
-			rtl839x_set_egress_rate(priv, p, 625000); // 10GB/s
-		else
-			rtl839x_set_egress_rate(priv, p, 62500);  // 1GB/s
-
-		// Setup queues: all RTL83XX SoCs have 8 queues, maximum rate
-		for (q = 0; q < 8; q++)
-			rtl839x_egress_rate_queue_limit(priv, p, q, 0xfffff);
-
-		if (priv->ports[p].is10G) {
-			// Set high threshold to maximum
-			sw_w32_mask(0xffff, 0xffff, RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p));
-		} else {
-			// Set high threshold to maximum
-			sw_w32_mask(0xffff, 0xffff, RTL839X_IGR_BWCTRL_PORT_CTRL_1(p));
-		}
-	}
-
-	// Set global ingress low watermark rate
-	sw_w32(65532, RTL839X_IGR_BWCTRL_CTRL_LB_THR);
-}
-
-
-
-void rtl838x_setup_prio2queue_matrix(int *min_queues)
-{
-	int i;
-	u32 v;
-
-	pr_info("Current Intprio2queue setting: %08x\n", sw_r32(RTL838X_QM_INTPRI2QID_CTRL));
-	for (i = 0; i < MAX_PRIOS; i++)
-		v |= i << (min_queues[i] * 3);
-	sw_w32(v, RTL838X_QM_INTPRI2QID_CTRL);
-}
-
-void rtl839x_setup_prio2queue_matrix(int *min_queues)
-{
-	int i, q;
-
-	pr_info("Current Intprio2queue setting: %08x\n", sw_r32(RTL839X_QM_INTPRI2QID_CTRL(0)));
-	for (i = 0; i < MAX_PRIOS; i++) {
-		q = min_queues[i];
-		sw_w32(i << (q * 3), RTL839X_QM_INTPRI2QID_CTRL(q));
-	}
-}
-
-/* Sets the CPU queue depending on the internal priority of a packet */
-void rtl83xx_setup_prio2queue_cpu_matrix(int *max_queues)
-{
-	int reg = soc_info.family == RTL8380_FAMILY_ID ? RTL838X_QM_PKT2CPU_INTPRI_MAP 
-					: RTL839X_QM_PKT2CPU_INTPRI_MAP;
-	int i;
-	u32 v;
-
-	pr_info("QM_PKT2CPU_INTPRI_MAP: %08x\n", sw_r32(reg));
-	for (i = 0; i < MAX_PRIOS; i++)
-		v |= max_queues[i] << (i * 3);
-	sw_w32(v, reg);
-}
-
-void rtl83xx_setup_default_prio2queue(void)
-{
-	if (soc_info.family == RTL8380_FAMILY_ID) {
-		rtl838x_setup_prio2queue_matrix(max_available_queue);
-	} else {
-		rtl839x_setup_prio2queue_matrix(max_available_queue);
-	}
-	rtl83xx_setup_prio2queue_cpu_matrix(max_available_queue);
-}
-
-/* Sets the output queue assigned to a port, the port can be the CPU-port */
-void rtl839x_set_egress_queue(int port, int queue)
-{
-	sw_w32(queue << ((port % 10) *3), RTL839X_QM_PORT_QNUM(port));
-}
-
-/* Sets the priority assigned of an ingress port, the port can be the CPU-port */
-void rtl83xx_set_ingress_priority(int port, int priority)
-{
-	if (soc_info.family == RTL8380_FAMILY_ID)
-		sw_w32(priority << ((port % 10) *3), RTL838X_PRI_SEL_PORT_PRI(port));
-	else
-		sw_w32(priority << ((port % 10) *3), RTL839X_PRI_SEL_PORT_PRI(port));
-	
-}
-
-int rtl839x_get_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port)
-{
-	u32 v;
-
-	mutex_lock(&priv->reg_mutex);
-
-	rtl839x_read_scheduling_table(port);
-	v = sw_r32(RTL839X_TBL_ACCESS_DATA_2(8));
-
-	mutex_unlock(&priv->reg_mutex);
-
-	if (v & BIT(19))
-		return WEIGHTED_ROUND_ROBIN;
-	return WEIGHTED_FAIR_QUEUE;
-}
-
-void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port,
-				      enum scheduler_type sched)
-{
-	enum scheduler_type t = rtl839x_get_scheduling_algorithm(priv, port);
-	u32 v, oam_state, oam_port_state;
-	u32 count;
-	int i, egress_rate;
-
-	mutex_lock(&priv->reg_mutex);
-	/* Check whether we need to empty the egress queue of that port due to Errata E0014503 */
-	if (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->cpu_port) {
-		// Read Operations, Adminstatrion and Management control register
-		oam_state = sw_r32(RTL839X_OAM_CTRL);
-
-		// Get current OAM state
-		oam_port_state = sw_r32(RTL839X_OAM_PORT_ACT_CTRL(port));
-	
-		// Disable OAM to block traffice
-		v = sw_r32(RTL839X_OAM_CTRL);
-		sw_w32_mask(0, 1, RTL839X_OAM_CTRL);
-		v = sw_r32(RTL839X_OAM_CTRL);
-
-		// Set to trap action OAM forward (bits 1, 2) and OAM Mux Action Drop (bit 0)
-		sw_w32(0x2, RTL839X_OAM_PORT_ACT_CTRL(port));
-
-		// Set port egress rate to unlimited
-		egress_rate = rtl839x_set_egress_rate(priv, port, 0xFFFFF);
-	
-		// Wait until the egress used page count of that port is 0
-		i = 0;
-		do {
-			usleep_range(100, 200);
-			rtl839x_read_out_q_table(port);
-			count = sw_r32(RTL839X_TBL_ACCESS_DATA_2(6));
-			count >>= 20;
-			i++;
-		} while (i < 3500 && count > 0);
-	}
-
-	// Actually set the scheduling algorithm
-	rtl839x_read_scheduling_table(port);
-	sw_w32_mask(BIT(19), sched ? BIT(19) : 0, RTL839X_TBL_ACCESS_DATA_2(8));
-	rtl839x_write_scheduling_table(port);
-
-	if (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->cpu_port) {
-		// Restore OAM state to control register
-		sw_w32(oam_state, RTL839X_OAM_CTRL);
-
-		// Restore trap action state
-		sw_w32(oam_port_state, RTL839X_OAM_PORT_ACT_CTRL(port));
-
-		// Restore port egress rate
-		rtl839x_set_egress_rate(priv, port, egress_rate);
-	}
-
-	mutex_unlock(&priv->reg_mutex);
-}
-
-void rtl839x_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv, int port,
-					  int *queue_weights)
-{
-	int i, lsb, low_byte, start_bit, high_mask;
-
-	mutex_lock(&priv->reg_mutex);
-
-	rtl839x_read_scheduling_table(port);
-
-	for (i = 0; i < 8; i++) {
-		lsb = 48 + i * 8;
-		low_byte = 8 - (lsb >> 5);
-		start_bit = lsb - (low_byte << 5);
-		high_mask = 0x3ff >> (32 - start_bit);
-		sw_w32_mask(0x3ff << start_bit, (queue_weights[i] & 0x3ff) << start_bit,
-				RTL839X_TBL_ACCESS_DATA_2(low_byte));
-		if (high_mask)
-			sw_w32_mask(high_mask, (queue_weights[i] & 0x3ff) >> (32- start_bit),
-					RTL839X_TBL_ACCESS_DATA_2(low_byte - 1));
-	}
-
-	rtl839x_write_scheduling_table(port);
-	mutex_unlock(&priv->reg_mutex);
-}
-
-void rtl838x_config_qos(void)
-{
-	int i, p;
-	u32 v;
-
-	pr_info("Setting up RTL838X QoS\n");
-	pr_info("RTL838X_PRI_SEL_TBL_CTRL(i): %08x\n", sw_r32(RTL838X_PRI_SEL_TBL_CTRL(0)));
-	rtl83xx_setup_default_prio2queue();
-
-	// Enable inner (bit 12) and outer (bit 13) priority remapping from DSCP
-	sw_w32_mask(0, BIT(12) | BIT(13), RTL838X_PRI_DSCP_INVLD_CTRL0);
-
-	/* Set default weight for calculating internal priority, in prio selection group 0
-	 * Port based (prio 3), Port outer-tag (4), DSCP (5), Inner Tag (6), Outer Tag (7)
-	 */
-	v = 3 | (4 << 3) | (5 << 6) | (6 << 9) | (7 << 12);
-	sw_w32(v, RTL838X_PRI_SEL_TBL_CTRL(0));
-
-	// Set the inner and outer priority one-to-one to re-marked outer dot1p priority
-	v = 0;
-	for (p = 0; p < 8; p++)
-		v |= p << (3 * p);
-	sw_w32(v, RTL838X_RMK_OPRI_CTRL);
-	sw_w32(v, RTL838X_RMK_IPRI_CTRL);
-
-	v = 0;
-	for (p = 0; p < 8; p++)
-		v |= (dot1p_priority_remapping[p] & 0x7) << (p * 3);
-	sw_w32(v, RTL838X_PRI_SEL_IPRI_REMAP);
-
-	// On all ports set scheduler type to WFQ
-	for (i = 0; i <= soc_info.cpu_port; i++)
-		sw_w32(0, RTL838X_SCHED_P_TYPE_CTRL(i));
-
-	// Enable egress scheduler for CPU-Port
-	sw_w32_mask(0, BIT(8), RTL838X_SCHED_LB_CTRL(soc_info.cpu_port));
-
-	// Enable egress drop allways on
-	sw_w32_mask(0, BIT(11), RTL838X_FC_P_EGR_DROP_CTRL(soc_info.cpu_port));
-
-	// Give special trap frames priority 7 (BPDUs) and routing exceptions:
-	sw_w32_mask(0, 7 << 3 | 7, RTL838X_QM_PKT2CPU_INTPRI_2);
-	// Give RMA frames priority 7:
-	sw_w32_mask(0, 7, RTL838X_QM_PKT2CPU_INTPRI_1);
-}
-
-void rtl839x_config_qos(void)
-{
-	int port, p, q;
-	u32 v;
-	struct rtl838x_switch_priv *priv = switch_priv;
-
-	pr_info("Setting up RTL839X QoS\n");
-	pr_info("RTL839X_PRI_SEL_TBL_CTRL(i): %08x\n", sw_r32(RTL839X_PRI_SEL_TBL_CTRL(0)));
-	rtl83xx_setup_default_prio2queue();
-
-	for (port = 0; port < soc_info.cpu_port; port++)
-		sw_w32(7, RTL839X_QM_PORT_QNUM(port));
-
-	// CPU-port gets queue number 7
-	sw_w32(7, RTL839X_QM_PORT_QNUM(soc_info.cpu_port));
-
-	for (port = 0; port <= soc_info.cpu_port; port++) {
-		rtl83xx_set_ingress_priority(port, 0);
-		rtl839x_set_scheduling_algorithm(priv, port, WEIGHTED_FAIR_QUEUE);
-		rtl839x_set_scheduling_queue_weights(priv, port, default_queue_weights);
-		// Do re-marking based on outer tag
-		sw_w32_mask(0, BIT(port % 32), RTL839X_RMK_PORT_DEI_TAG_CTRL(port));
-	}
-
-	// Remap dot1p priorities to internal priority, for this the outer tag needs be re-marked
-	v = 0;
-	for (p = 0; p < 8; p++)
-		v |= (dot1p_priority_remapping[p] & 0x7) << (p * 3);
-	sw_w32(v, RTL839X_PRI_SEL_IPRI_REMAP);
-	
-	/* Configure Drop Precedence for Drop Eligible Indicator (DEI)
-	 * Index 0: 0
-	 * Index 1: 2
-	 * Each indicator is 2 bits long
-	 */
-	sw_w32(2 << 2, RTL839X_PRI_SEL_DEI2DP_REMAP);
-
-	// Re-mark DEI: 4 bit-fields of 2 bits each, field 0 is bits 0-1, ...
-	sw_w32((0x1 << 2) | (0x1 << 4), RTL839X_RMK_DEI_CTRL);
-
-	/* Set Congestion avoidance drop probability to 0 for drop precedences 0-2 (bits 24-31)
-	 * low threshold (bits 0-11) to 4095 and high threshold (bits 12-23) to 4095
-	 * Weighted Random Early Detection (WRED) is used
-	 */
-	sw_w32(4095 << 12| 4095, RTL839X_WRED_PORT_THR_CTRL(0));
-	sw_w32(4095 << 12| 4095, RTL839X_WRED_PORT_THR_CTRL(1));
-	sw_w32(4095 << 12| 4095, RTL839X_WRED_PORT_THR_CTRL(2));
-
-	/* Set queue-based congestion avoidance properties, register fields are as
-	 * for forward RTL839X_WRED_PORT_THR_CTRL
-	 */
-	for (q = 0; q < 8; q++) {
-		sw_w32(255 << 24 | 78 << 12 | 68, RTL839X_WRED_QUEUE_THR_CTRL(q, 0));
-		sw_w32(255 << 24 | 74 << 12 | 64, RTL839X_WRED_QUEUE_THR_CTRL(q, 0));
-		sw_w32(255 << 24 | 70 << 12 | 60, RTL839X_WRED_QUEUE_THR_CTRL(q, 0));
-	}
-}
-
-void __init rtl83xx_setup_qos(struct rtl838x_switch_priv *priv)
-{
-	switch_priv = priv;
-
-	pr_info("In %s\n", __func__);
-
-	if (priv->family_id == RTL8380_FAMILY_ID)
-		return rtl838x_config_qos();
-	else if (priv->family_id == RTL8390_FAMILY_ID)
-		return rtl839x_config_qos();
-
-	if (priv->family_id == RTL8380_FAMILY_ID)
-		rtl838x_rate_control_init(priv);
-	else if (priv->family_id == RTL8390_FAMILY_ID)
-		rtl839x_rate_control_init(priv);
-	
-}
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c
deleted file mode 100644
index 5d764b6a32..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c
+++ /dev/null
@@ -1,859 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <asm/mach-rtl838x/mach-rtl83xx.h>
-#include "rtl83xx.h"
-
-extern struct mutex smi_lock;
-
-void rtl838x_print_matrix(void)
-{
-	unsigned volatile int *ptr8;
-	int i;
-
-	ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
-	for (i = 0; i < 28; i += 8)
-		pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
-			ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],
-			ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);
-	pr_debug("CPU_PORT> %8x\n", ptr8[28]);
-}
-
-static inline int rtl838x_port_iso_ctrl(int p)
-{
-	return RTL838X_PORT_ISO_CTRL(p);
-}
-
-static inline void rtl838x_exec_tbl0_cmd(u32 cmd)
-{
-	sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);
-	do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15));
-}
-
-static inline void rtl838x_exec_tbl1_cmd(u32 cmd)
-{
-	sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);
-	do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15));
-}
-
-static inline int rtl838x_tbl_access_data_0(int i)
-{
-	return RTL838X_TBL_ACCESS_DATA_0(i);
-}
-
-static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
-{
-	u32 v;
-	// Read VLAN table (0) via register 0
-	struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
-
-	rtl_table_read(r, vlan);
-	info->tagged_ports = sw_r32(rtl_table_data(r, 0));
-	v = sw_r32(rtl_table_data(r, 1));
-	pr_debug("VLAN_READ %d: %016llx %08x\n", vlan, info->tagged_ports, v);
-	rtl_table_release(r);
-
-	info->profile_id = v & 0x7;
-	info->hash_mc_fid = !!(v & 0x8);
-	info->hash_uc_fid = !!(v & 0x10);
-	info->fid = (v >> 5) & 0x3f;
-
-	// Read UNTAG table (0) via table register 1
-	r = rtl_table_get(RTL8380_TBL_1, 0);
-	rtl_table_read(r, vlan);
-	info->untagged_ports = sw_r32(rtl_table_data(r, 0));
-	rtl_table_release(r);
-}
-
-static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
-{
-	u32 v;
-	// Access VLAN table (0) via register 0
-	struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);
-
-	sw_w32(info->tagged_ports, rtl_table_data(r, 0));
-
-	v = info->profile_id;
-	v |= info->hash_mc_fid ? 0x8 : 0;
-	v |= info->hash_uc_fid ? 0x10 : 0;
-	v |= ((u32)info->fid) << 5;
-	sw_w32(v, rtl_table_data(r, 1));
-
-	rtl_table_write(r, vlan);
-	rtl_table_release(r);
-}
-
-static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
-{
-	// Access UNTAG table (0) via register 1
-	struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 0);
-
-	sw_w32(portmask & 0x1fffffff, rtl_table_data(r, 0));
-	rtl_table_write(r, vlan);
-	rtl_table_release(r);
-}
-
-/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
- */
-static void rtl838x_vlan_fwd_on_inner(int port, bool is_set)
-{
-	if (is_set)
-		sw_w32_mask(BIT(port), 0, RTL838X_VLAN_PORT_FWD);
-	else
-		sw_w32_mask(0, BIT(port), RTL838X_VLAN_PORT_FWD);
-}
-
-static u64 rtl838x_l2_hash_seed(u64 mac, u32 vid)
-{
-	return mac << 12 | vid;
-}
-
-/*
- * Applies the same hash algorithm as the one used currently by the ASIC to the seed
- * and returns a key into the L2 hash table
- */
-static u32 rtl838x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
-{
-	u32 h1, h2, h3, h;
-
-	if (sw_r32(priv->r->l2_ctrl_0) & 1) {
-		h1 = (seed >> 11) & 0x7ff;
-		h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
-
-		h2 = (seed >> 33) & 0x7ff;
-		h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f);
-
-		h3 = (seed >> 44) & 0x7ff;
-		h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf);
-
-		h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff);
-		h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff);
-	} else {
-		h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff)
-			^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
-			^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff);
-	}
-
-	return h;
-}
-
-static inline int rtl838x_mac_force_mode_ctrl(int p)
-{
-	return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
-}
-
-static inline int rtl838x_mac_port_ctrl(int p)
-{
-	return RTL838X_MAC_PORT_CTRL(p);
-}
-
-static inline int rtl838x_l2_port_new_salrn(int p)
-{
-	return RTL838X_L2_PORT_NEW_SALRN(p);
-}
-
-static inline int rtl838x_l2_port_new_sa_fwd(int p)
-{
-	return RTL838X_L2_PORT_NEW_SA_FWD(p);
-}
-
-static inline int rtl838x_mac_link_spd_sts(int p)
-{
-	return RTL838X_MAC_LINK_SPD_STS(p);
-}
-
-inline static int rtl838x_trk_mbr_ctr(int group)
-{
-	return RTL838X_TRK_MBR_CTR + (group << 2);
-}
-
-/*
- * Fills an L2 entry structure from the SoC registers
- */
-static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
-{
-	/* Table contains different entry types, we need to identify the right one:
-	 * Check for MC entries, first
-	 * In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to
-	 * identify valid entries
-	 */
-	e->is_ip_mc = !!(r[0] & BIT(22));
-	e->is_ipv6_mc = !!(r[0] & BIT(21));
-	e->type = L2_INVALID;
-
-	if (!e->is_ip_mc && !e->is_ipv6_mc) {
-		e->mac[0] = (r[1] >> 20);
-		e->mac[1] = (r[1] >> 12);
-		e->mac[2] = (r[1] >> 4);
-		e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
-		e->mac[4] = (r[2] >> 20);
-		e->mac[5] = (r[2] >> 12);
-
-		e->rvid = r[2] & 0xfff;
-		e->vid = r[0] & 0xfff;
-
-		/* Is it a unicast entry? check multicast bit */
-		if (!(e->mac[0] & 1)) {
-			e->is_static = !!((r[0] >> 19) & 1);
-			e->port = (r[0] >> 12) & 0x1f;
-			e->block_da = !!(r[1] & BIT(30));
-			e->block_sa = !!(r[1] & BIT(31));
-			e->suspended = !!(r[1] & BIT(29));
-			e->next_hop = !!(r[1] & BIT(28));
-			if (e->next_hop) {
-				pr_info("Found next hop entry, need to read extra data\n");
-				e->nh_vlan_target = !!(r[0] & BIT(9));
-				e->nh_route_id = r[0] & 0x1ff;
-			}
-			e->age = (r[0] >> 17) & 0x3;
-			e->valid = true;
-			
-			/* A valid entry has one of mutli-cast, aging, sa/da-blocking,
-			 * next-hop or static entry bit set */
-			if (!(r[0] & 0x007c0000) && !(r[1] & 0xd0000000))
-				e->valid = false;
-			else
-				e->type = L2_UNICAST;
-		} else { // L2 multicast
-			pr_info("Got L2 MC entry: %08x %08x %08x\n", r[0], r[1], r[2]);
-			e->valid = true;
-			e->type = L2_MULTICAST;
-			e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
-		}
-	} else { // IPv4 and IPv6 multicast
-		e->valid = true;
-		e->mc_portmask_index = (r[0] >> 12) & 0x1ff;
-		e->mc_gip = r[1];
-		e->mc_sip = r[2];
-		e->rvid = r[0] & 0xfff;
-	}
-	if (e->is_ip_mc)
-		e->type = IP4_MULTICAST;
-	if (e->is_ipv6_mc)
-		e->type = IP6_MULTICAST;
-}
-
-/*
- * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry
- */
-static void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
-{
-	u64 mac = ether_addr_to_u64(e->mac);
-
-	if (!e->valid) {
-		r[0] = r[1] = r[2] = 0;
-		return;
-	}
-
-	r[0] = e->is_ip_mc ? BIT(22) : 0;
-	r[0] |= e->is_ipv6_mc ? BIT(21) : 0;
-
-	if (!e->is_ip_mc && !e->is_ipv6_mc) {
-		r[1] = mac >> 20;
-		r[2] = (mac & 0xfffff) << 12;
-
-		/* Is it a unicast entry? check multicast bit */
-		if (!(e->mac[0] & 1)) {
-			r[0] |= e->is_static ? BIT(19) : 0;
-			r[0] |= (e->port & 0x3f) << 12;
-			r[0] |= e->vid;
-			r[1] |= e->block_da ? BIT(30) : 0;
-			r[1] |= e->block_sa ? BIT(31) : 0;
-			r[1] |= e->suspended ? BIT(29) : 0;
-			r[2] |= e->rvid & 0xfff;
-			if (e->next_hop) {
-				r[1] |= BIT(28);
-				r[0] |= e->nh_vlan_target ? BIT(9) : 0;
-				r[0] |= e->nh_route_id &0x1ff;
-			}
-			r[0] |= (e->age & 0x3) << 17;
-		} else { // L2 Multicast
-			r[0] |= (e->mc_portmask_index & 0x1ff) << 12;
-			r[2] |= e->rvid & 0xfff;
-			r[0] |= e->vid & 0xfff;
-			pr_info("FILL MC: %08x %08x %08x\n", r[0], r[1], r[2]);
-		}
-	} else { // IPv4 and IPv6 multicast
-		r[1] = e->mc_gip;
-		r[2] = e->mc_sip;
-		r[0] |= e->rvid;
-	}
-}
-
-/*
- * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
- * hash is the id of the bucket and pos is the position of the entry in that bucket
- * The data read from the SoC is filled into rtl838x_l2_entry
- */
-static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
-{
-	u64 entry;
-	u32 r[3];
-	struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); // Access L2 Table 0
-	u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket
-	int i;
-
-	rtl_table_read(q, idx);
-	for (i= 0; i < 3; i++)
-		r[i] = sw_r32(rtl_table_data(q, i));
-
-	rtl_table_release(q);
-
-	rtl838x_fill_l2_entry(r, e);
-	if (!e->valid)
-		return 0;
-
-	entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff);
-	return entry;
-}
-
-static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
-{
-	u32 r[3];
-	struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0);
-	int i;
-
-	u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket
-
-	rtl838x_fill_l2_row(r, e);
-
-	for (i= 0; i < 3; i++)
-		sw_w32(r[i], rtl_table_data(q, i));
-
-	rtl_table_write(q, idx);
-	rtl_table_release(q);
-}
-
-static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)
-{
-	u64 entry;
-	u32 r[3];
-	struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1
-	int i;
-
-	rtl_table_read(q, idx);
-	for (i= 0; i < 3; i++)
-		r[i] = sw_r32(rtl_table_data(q, i));
-
-	rtl_table_release(q);
-
-	rtl838x_fill_l2_entry(r, e);
-	if (!e->valid)
-		return 0;
-
-	pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
-
-	// Return MAC with concatenated VID ac concatenated ID
-	entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff);
-	return entry;
-}
-
-static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e)
-{
-	u32 r[3];
-	struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1
-	int i;
-
-	rtl838x_fill_l2_row(r, e);
-
-	for (i= 0; i < 3; i++)
-		sw_w32(r[i], rtl_table_data(q, i));
-
-	rtl_table_write(q, idx);
-	rtl_table_release(q);
-}
-
-static u64 rtl838x_read_mcast_pmask(int idx)
-{
-	u32 portmask;
-	// Read MC_PMSK (2) via register RTL8380_TBL_L2
-	struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
-
-	rtl_table_read(q, idx);
-	portmask = sw_r32(rtl_table_data(q, 0));
-	rtl_table_release(q);
-
-	return portmask;
-}
-
-static void rtl838x_write_mcast_pmask(int idx, u64 portmask)
-{
-	// Access MC_PMSK (2) via register RTL8380_TBL_L2
-	struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);
-
-	sw_w32(((u32)portmask) & 0x1fffffff, rtl_table_data(q, 0));
-	rtl_table_write(q, idx);
-	rtl_table_release(q);
-}
-
-static void rtl838x_vlan_profile_setup(int profile)
-{
-	u32 pmask_id = UNKNOWN_MC_PMASK;
-	// Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding
-	u32 p = 1 | pmask_id << 1 | pmask_id << 10 | pmask_id << 19;
-
-	sw_w32(p, RTL838X_VLAN_PROFILE(profile));
-
-	/* RTL8380 and RTL8390 use an index into the portmask table to set the
-	 * unknown multicast portmask, setup a default at a safe location
-	 * On RTL93XX, the portmask is directly set in the profile,
-	 * see e.g. rtl9300_vlan_profile_setup
-	 */
-	rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x1fffffff);
-}
-
-static inline int rtl838x_vlan_port_egr_filter(int port)
-{
-	return RTL838X_VLAN_PORT_EGR_FLTR;
-}
-
-static inline int rtl838x_vlan_port_igr_filter(int port)
-{
-	return RTL838X_VLAN_PORT_IGR_FLTR(port);
-}
-
-static void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
-{
-	int i;
-	u32 cmd = 1 << 15 /* Execute cmd */
-		| 1 << 14 /* Read */
-		| 2 << 12 /* Table type 0b10 */
-		| (msti & 0xfff);
-	priv->r->exec_tbl0_cmd(cmd);
-
-	for (i = 0; i < 2; i++)
-		port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
-}
-
-static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
-{
-	int i;
-	u32 cmd = 1 << 15 /* Execute cmd */
-		| 0 << 14 /* Write */
-		| 2 << 12 /* Table type 0b10 */
-		| (msti & 0xfff);
-
-	for (i = 0; i < 2; i++)
-		sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
-	priv->r->exec_tbl0_cmd(cmd);
-}
-
-u64 rtl838x_traffic_get(int source)
-{
-	return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source));
-}
-
-void rtl838x_traffic_set(int source, u64 dest_matrix)
-{
-	rtl838x_set_port_reg(dest_matrix, rtl838x_port_iso_ctrl(source));
-}
-
-void rtl838x_traffic_enable(int source, int dest)
-{
-	rtl838x_mask_port_reg(0, BIT(dest), rtl838x_port_iso_ctrl(source));
-}
-
-void rtl838x_traffic_disable(int source, int dest)
-{
-	rtl838x_mask_port_reg(BIT(dest), 0, rtl838x_port_iso_ctrl(source));
-}
-
-/*
- * Enables or disables the EEE/EEEP capability of a port
- */
-static void rtl838x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
-{
-	u32 v;
-
-	// This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP
-	if (port >= 24)
-		return;
-
-	pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
-	v = enable ? 0x3 : 0x0;
-
-	// Set EEE state for 100 (bit 9) & 1000MBit (bit 10)
-	sw_w32_mask(0x3 << 9, v << 9, priv->r->mac_force_mode_ctrl(port));
-
-	// Set TX/RX EEE state
-	if (enable) {
-		sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
-		sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
-	} else {
-		sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
-		sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
-	}
-	priv->ports[port].eee_enabled = enable;
-}
-
-
-/*
- * Get EEE own capabilities and negotiation result
- */
-static int rtl838x_eee_port_ability(struct rtl838x_switch_priv *priv,
-				    struct ethtool_eee *e, int port)
-{
-	u64 link;
-
-	if (port >= 24)
-		return 0;
-
-	link = rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS);
-	if (!(link & BIT(port)))
-		return 0;
-
-	if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(9))
-		e->advertised |= ADVERTISED_100baseT_Full;
-
-	if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(10))
-		e->advertised |= ADVERTISED_1000baseT_Full;
-
-	if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
-		e->lp_advertised = ADVERTISED_100baseT_Full;
-		e->lp_advertised |= ADVERTISED_1000baseT_Full;
-		return 1;
-	}
-
-	return 0;
-}
-
-static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
-{
-	int i;
-
-	pr_info("Setting up EEE, state: %d\n", enable);
-	sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
-
-	/* Set timers for EEE */
-	sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
-	sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
-
-	// Enable EEE MAC support on ports
-	for (i = 0; i < priv->cpu_port; i++) {
-		if (priv->ports[i].phy)
-			rtl838x_port_eee_set(priv, i, enable);
-	}
-	priv->eee_enabled = enable;
-}
-
-const struct rtl838x_reg rtl838x_reg = {
-	.mask_port_reg_be = rtl838x_mask_port_reg,
-	.set_port_reg_be = rtl838x_set_port_reg,
-	.get_port_reg_be = rtl838x_get_port_reg,
-	.mask_port_reg_le = rtl838x_mask_port_reg,
-	.set_port_reg_le = rtl838x_set_port_reg,
-	.get_port_reg_le = rtl838x_get_port_reg,
-	.stat_port_rst = RTL838X_STAT_PORT_RST,
-	.stat_rst = RTL838X_STAT_RST,
-	.stat_port_std_mib = RTL838X_STAT_PORT_STD_MIB,
-	.port_iso_ctrl = rtl838x_port_iso_ctrl,
-	.traffic_enable = rtl838x_traffic_enable,
-	.traffic_disable = rtl838x_traffic_disable,
-	.traffic_get = rtl838x_traffic_get,
-	.traffic_set = rtl838x_traffic_set,
-	.l2_ctrl_0 = RTL838X_L2_CTRL_0,
-	.l2_ctrl_1 = RTL838X_L2_CTRL_1,
-	.l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT,
-	.smi_poll_ctrl = RTL838X_SMI_POLL_CTRL,
-	.l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
-	.exec_tbl0_cmd = rtl838x_exec_tbl0_cmd,
-	.exec_tbl1_cmd = rtl838x_exec_tbl1_cmd,
-	.tbl_access_data_0 = rtl838x_tbl_access_data_0,
-	.isr_glb_src = RTL838X_ISR_GLB_SRC,
-	.isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG,
-	.imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG,
-	.imr_glb = RTL838X_IMR_GLB,
-	.vlan_tables_read = rtl838x_vlan_tables_read,
-	.vlan_set_tagged = rtl838x_vlan_set_tagged,
-	.vlan_set_untagged = rtl838x_vlan_set_untagged,
-	.mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,
-	.vlan_profile_dump = rtl838x_vlan_profile_dump,
-	.vlan_profile_setup = rtl838x_vlan_profile_setup,
-	.vlan_fwd_on_inner = rtl838x_vlan_fwd_on_inner,
-	.stp_get = rtl838x_stp_get,
-	.stp_set = rtl838x_stp_set,
-	.mac_port_ctrl = rtl838x_mac_port_ctrl,
-	.l2_port_new_salrn = rtl838x_l2_port_new_salrn,
-	.l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd,
-	.mir_ctrl = RTL838X_MIR_CTRL,
-	.mir_dpm = RTL838X_MIR_DPM_CTRL,
-	.mir_spm = RTL838X_MIR_SPM_CTRL,
-	.mac_link_sts = RTL838X_MAC_LINK_STS,
-	.mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS,
-	.mac_link_spd_sts = rtl838x_mac_link_spd_sts,
-	.mac_rx_pause_sts = RTL838X_MAC_RX_PAUSE_STS,
-	.mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS,
-	.read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash,
-	.write_l2_entry_using_hash = rtl838x_write_l2_entry_using_hash,
-	.read_cam = rtl838x_read_cam,
-	.write_cam = rtl838x_write_cam,
-	.vlan_port_egr_filter = RTL838X_VLAN_PORT_EGR_FLTR,
-	.vlan_port_igr_filter = RTL838X_VLAN_PORT_IGR_FLTR(0),
-	.vlan_port_pb = RTL838X_VLAN_PORT_PB_VLAN,
-	.vlan_port_tag_sts_ctrl = RTL838X_VLAN_PORT_TAG_STS_CTRL,
-	.trk_mbr_ctr = rtl838x_trk_mbr_ctr,
-	.rma_bpdu_fld_pmask = RTL838X_RMA_BPDU_FLD_PMSK,
-	.spcl_trap_eapol_ctrl = RTL838X_SPCL_TRAP_EAPOL_CTRL,
-	.init_eee = rtl838x_init_eee,
-	.port_eee_set = rtl838x_port_eee_set,
-	.eee_port_ability = rtl838x_eee_port_ability,
-	.l2_hash_seed = rtl838x_l2_hash_seed, 
-	.l2_hash_key = rtl838x_l2_hash_key,
-	.read_mcast_pmask = rtl838x_read_mcast_pmask,
-	.write_mcast_pmask = rtl838x_write_mcast_pmask,
-};
-
-irqreturn_t rtl838x_switch_irq(int irq, void *dev_id)
-{
-	struct dsa_switch *ds = dev_id;
-	u32 status = sw_r32(RTL838X_ISR_GLB_SRC);
-	u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG);
-	u32 link;
-	int i;
-
-	/* Clear status */
-	sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG);
-	pr_info("RTL8380 Link change: status: %x, ports %x\n", status, ports);
-
-	for (i = 0; i < 28; i++) {
-		if (ports & BIT(i)) {
-			link = sw_r32(RTL838X_MAC_LINK_STS);
-			if (link & BIT(i))
-				dsa_port_phylink_mac_change(ds, i, true);
-			else
-				dsa_port_phylink_mac_change(ds, i, false);
-		}
-	}
-	return IRQ_HANDLED;
-}
-
-int rtl838x_smi_wait_op(int timeout)
-{
-	do {
-		timeout--;
-		udelay(10);
-	} while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & 0x1) && (timeout >= 0));
-	if (timeout <= 0)
-		return -1;
-	return 0;
-}
-
-/*
- * Reads a register in a page from the PHY
- */
-int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
-{
-	u32 v;
-	u32 park_page;
-
-	if (port > 31) {
-		*val = 0xffff;
-		return 0;
-	}
-
-	if (page > 4095 || reg > 31)
-		return -ENOTSUPP;
-
-	mutex_lock(&smi_lock);
-
-	if (rtl838x_smi_wait_op(10000))
-		goto timeout;
-
-	sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
-
-	park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
-	v = reg << 20 | page << 3;
-	sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
-	sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
-
-	if (rtl838x_smi_wait_op(10000))
-		goto timeout;
-
-	*val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
-
-	mutex_unlock(&smi_lock);
-	return 0;
-
-timeout:
-	mutex_unlock(&smi_lock);
-	return -ETIMEDOUT;
-}
-
-/*
- * Write to a register in a page of the PHY
- */
-int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
-{
-	u32 v;
-	u32 park_page;
-
-	val &= 0xffff;
-	if (port > 31 || page > 4095 || reg > 31)
-		return -ENOTSUPP;
-
-	mutex_lock(&smi_lock);
-	if (rtl838x_smi_wait_op(10000))
-		goto timeout;
-
-	sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
-	mdelay(10);
-
-	sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
-
-	park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
-	v = reg << 20 | page << 3 | 0x4;
-	sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
-	sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
-
-	if (rtl838x_smi_wait_op(10000))
-		goto timeout;
-
-	mutex_unlock(&smi_lock);
-	return 0;
-
-timeout:
-	mutex_unlock(&smi_lock);
-	return -ETIMEDOUT;
-}
-
-/*
- * Read an mmd register of a PHY
- */
-int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
-{
-	u32 v;
-
-	mutex_lock(&smi_lock);
-
-	if (rtl838x_smi_wait_op(10000))
-		goto timeout;
-
-	sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
-	mdelay(10);
-
-	sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
-
-	v = addr << 16 | reg;
-	sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
-
-	/* mmd-access | read | cmd-start */
-	v = 1 << 1 | 0 << 2 | 1;
-	sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
-
-	if (rtl838x_smi_wait_op(10000))
-		goto timeout;
-
-	*val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
-
-	mutex_unlock(&smi_lock);
-	return 0;
-
-timeout:
-	mutex_unlock(&smi_lock);
-	return -ETIMEDOUT;
-}
-
-/*
- * Write to an mmd register of a PHY
- */
-int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
-{
-	u32 v;
-
-	pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val);
-	val &= 0xffff;
-	mutex_lock(&smi_lock);
-
-	if (rtl838x_smi_wait_op(10000))
-		goto timeout;
-
-	sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
-	mdelay(10);
-
-	sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
-
-	sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
-	sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
-	/* mmd-access | write | cmd-start */
-	v = 1 << 1 | 1 << 2 | 1;
-	sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
-
-	if (rtl838x_smi_wait_op(10000))
-		goto timeout;
-
-	mutex_unlock(&smi_lock);
-	return 0;
-
-timeout:
-	mutex_unlock(&smi_lock);
-	return -ETIMEDOUT;
-}
-
-void rtl8380_get_version(struct rtl838x_switch_priv *priv)
-{
-	u32 rw_save, info_save;
-	u32 info;
-
-	rw_save = sw_r32(RTL838X_INT_RW_CTRL);
-	sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL);
-
-	info_save = sw_r32(RTL838X_CHIP_INFO);
-	sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO);
-
-	info = sw_r32(RTL838X_CHIP_INFO);
-	sw_w32(info_save, RTL838X_CHIP_INFO);
-	sw_w32(rw_save, RTL838X_INT_RW_CTRL);
-
-	if ((info & 0xFFFF) == 0x6275) {
-		if (((info >> 16) & 0x1F) == 0x1)
-			priv->version = RTL8380_VERSION_A;
-		else if (((info >> 16) & 0x1F) == 0x2)
-			priv->version = RTL8380_VERSION_B;
-		else
-			priv->version = RTL8380_VERSION_B;
-	} else {
-		priv->version = '-';
-	}
-}
-
-void rtl838x_vlan_profile_dump(int profile)
-{
-	u32 p;
-
-	if (profile < 0 || profile > 7)
-		return;
-
-	p = sw_r32(RTL838X_VLAN_PROFILE(profile));
-
-	pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
-		UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
-		profile, p & 1, (p >> 1) & 0x1ff, (p >> 10) & 0x1ff, (p >> 19) & 0x1ff);
-}
-
-void rtl8380_sds_rst(int mac)
-{
-	u32 offset = (mac == 24) ? 0 : 0x100;
-
-	sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0 + offset);
-	sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
-	sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
-	sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
-	sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
-	pr_debug("SERDES reset: %d\n", mac);
-}
-
-int rtl8380_sds_power(int mac, int val)
-{
-	u32 mode = (val == 1) ? 0x4 : 0x9;
-	u32 offset = (mac == 24) ? 5 : 0;
-
-	if ((mac != 24) && (mac != 26)) {
-		pr_err("%s: not a fibre port: %d\n", __func__, mac);
-		return -1;
-	}
-
-	sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
-
-	rtl8380_sds_rst(mac);
-
-	return 0;
-}
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.h
deleted file mode 100644
index b2097363b9..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.h
+++ /dev/null
@@ -1,526 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _RTL838X_H
-#define _RTL838X_H
-
-#include <net/dsa.h>
-
-/*
- * Register definition
- */
-#define RTL838X_MAC_PORT_CTRL(port)		(0xd560 + (((port) << 7)))
-#define RTL839X_MAC_PORT_CTRL(port)		(0x8004 + (((port) << 7)))
-#define RTL930X_MAC_PORT_CTRL(port)		(0x3260 + (((port) << 6)))
-#define RTL930X_MAC_L2_PORT_CTRL(port)		(0x3268 + (((port) << 6)))
-#define RTL931X_MAC_PORT_CTRL(port)		(0x6004 + (((port) << 7)))
-
-#define RTL838X_RST_GLB_CTRL_0			(0x003c)
-
-#define RTL838X_MAC_FORCE_MODE_CTRL		(0xa104)
-#define RTL839X_MAC_FORCE_MODE_CTRL		(0x02bc)
-#define RTL930X_MAC_FORCE_MODE_CTRL		(0xCA1C)
-#define RTL931X_MAC_FORCE_MODE_CTRL		(0x0DCC)
-
-#define RTL838X_DMY_REG31			(0x3b28)
-#define RTL838X_SDS_MODE_SEL			(0x0028)
-#define RTL838X_SDS_CFG_REG			(0x0034)
-#define RTL838X_INT_MODE_CTRL			(0x005c)
-#define RTL838X_CHIP_INFO			(0x00d8)
-#define RTL839X_CHIP_INFO			(0x0ff4)
-#define RTL838X_PORT_ISO_CTRL(port)		(0x4100 + ((port) << 2))
-#define RTL839X_PORT_ISO_CTRL(port)		(0x1400 + ((port) << 3))
-
-/* Packet statistics */
-#define RTL838X_STAT_PORT_STD_MIB		(0x1200)
-#define RTL839X_STAT_PORT_STD_MIB		(0xC000)
-#define RTL930X_STAT_PORT_MIB_CNTR		(0x0664)
-#define RTL838X_STAT_RST			(0x3100)
-#define RTL839X_STAT_RST			(0xF504)
-#define RTL930X_STAT_RST			(0x3240)
-#define RTL931X_STAT_RST			(0x7ef4)
-#define RTL838X_STAT_PORT_RST			(0x3104)
-#define RTL839X_STAT_PORT_RST			(0xF508)
-#define RTL930X_STAT_PORT_RST			(0x3244)
-#define RTL931X_STAT_PORT_RST			(0x7ef8)
-#define RTL838X_STAT_CTRL			(0x3108)
-#define RTL839X_STAT_CTRL			(0x04cc)
-#define RTL930X_STAT_CTRL			(0x3248)
-#define RTL931X_STAT_CTRL			(0x5720)
-
-/* Registers of the internal Serdes of the 8390 */
-#define RTL8390_SDS0_1_XSG0			(0xA000)
-#define RTL8390_SDS0_1_XSG1			(0xA100)
-#define RTL839X_SDS12_13_XSG0			(0xB800)
-#define RTL839X_SDS12_13_XSG1			(0xB900)
-#define RTL839X_SDS12_13_PWR0			(0xb880)
-#define RTL839X_SDS12_13_PWR1			(0xb980)
-
-/* Registers of the internal Serdes of the 8380 */
-#define RTL838X_SDS4_FIB_REG0			(0xF800)
-#define RTL838X_SDS4_REG28			(0xef80)
-#define RTL838X_SDS4_DUMMY0			(0xef8c)
-#define RTL838X_SDS5_EXT_REG6			(0xf18c)
-
-/* VLAN registers */
-#define RTL838X_VLAN_CTRL			(0x3A74)
-#define RTL838X_VLAN_PROFILE(idx)		(0x3A88 + ((idx) << 2))
-#define RTL838X_VLAN_PORT_EGR_FLTR		(0x3A84)
-#define RTL838X_VLAN_PORT_PB_VLAN		(0x3C00)
-#define RTL838X_VLAN_PORT_IGR_FLTR(port)	(0x3A7C + (((port >> 4) << 2)))
-#define RTL838X_VLAN_PORT_IGR_FLTR_0		(0x3A7C)
-#define RTL838X_VLAN_PORT_IGR_FLTR_1		(0x3A7C + 4)
-#define RTL838X_VLAN_PORT_TAG_STS_CTRL		(0xA530)
-
-#define RTL839X_VLAN_PROFILE(idx)		(0x25C0 + (((idx) << 3)))
-#define RTL839X_VLAN_CTRL			(0x26D4)
-#define RTL839X_VLAN_PORT_PB_VLAN		(0x26D8)
-#define RTL839X_VLAN_PORT_IGR_FLTR(port)	(0x27B4 + (((port >> 4) << 2)))
-#define RTL839X_VLAN_PORT_EGR_FLTR(port)	(0x27C4 + (((port >> 5) << 2)))
-#define RTL839X_VLAN_PORT_TAG_STS_CTRL		(0x6828)
-
-#define RTL930X_VLAN_PROFILE_SET(idx)		(0x9c60 + (((idx) * 20)))
-#define RTL930X_VLAN_CTRL			(0x82D4)
-#define RTL930X_VLAN_PORT_PB_VLAN		(0x82D8)
-#define RTL930X_VLAN_PORT_IGR_FLTR(port)	(0x83C0 + (((port >> 4) << 2)))
-#define RTL930X_VLAN_PORT_EGR_FLTR		(0x83C8)
-#define RTL930X_VLAN_PORT_TAG_STS_CTRL		(0xCE24)
-
-#define RTL931X_VLAN_PROFILE_SET(idx)		(0x9800 + (((idx) * 28)))
-#define RTL931X_VLAN_CTRL			(0x94E4)
-#define RTL931X_VLAN_PORT_IGR_FLTR(port)	(0x96B4 + (((port >> 4) << 2)))
-#define RTL931X_VLAN_PORT_EGR_FLTR(port)	(0x96C4 + (((port >> 5) << 2)))
-#define RTL931X_VLAN_PORT_TAG_CTRL		(0x4860)
-
-/* Table access registers */
-#define RTL838X_TBL_ACCESS_CTRL_0		(0x6914)
-#define RTL838X_TBL_ACCESS_DATA_0(idx)		(0x6918 + ((idx) << 2))
-#define RTL838X_TBL_ACCESS_CTRL_1		(0xA4C8)
-#define RTL838X_TBL_ACCESS_DATA_1(idx)		(0xA4CC + ((idx) << 2))
-
-#define RTL839X_TBL_ACCESS_CTRL_0		(0x1190)
-#define RTL839X_TBL_ACCESS_DATA_0(idx)		(0x1194 + ((idx) << 2))
-#define RTL839X_TBL_ACCESS_CTRL_1		(0x6b80)
-#define RTL839X_TBL_ACCESS_DATA_1(idx)		(0x6b84 + ((idx) << 2))
-#define RTL839X_TBL_ACCESS_CTRL_2		(0x611C)
-#define RTL839X_TBL_ACCESS_DATA_2(i)		(0x6120 + (((i) << 2)))
-
-#define RTL930X_TBL_ACCESS_CTRL_0		(0xB340)
-#define RTL930X_TBL_ACCESS_DATA_0(idx)		(0xB344 + ((idx) << 2))
-#define RTL930X_TBL_ACCESS_CTRL_1		(0xB3A0)
-#define RTL930X_TBL_ACCESS_DATA_1(idx)		(0xB3A4 + ((idx) << 2))
-#define RTL930X_TBL_ACCESS_CTRL_2		(0xCE04)
-#define RTL930X_TBL_ACCESS_DATA_2(i)		(0xCE08 + (((i) << 2)))
-
-#define RTL931X_TBL_ACCESS_CTRL_0		(0x8500)
-#define RTL931X_TBL_ACCESS_DATA_0(idx)		(0x8508 + ((idx) << 2))
-#define RTL931X_TBL_ACCESS_CTRL_1		(0x40C0)
-#define RTL931X_TBL_ACCESS_DATA_1(idx)		(0x40C4 + ((idx) << 2))
-#define RTL931X_TBL_ACCESS_CTRL_2		(0x8528)
-#define RTL931X_TBL_ACCESS_DATA_2(i)		(0x852C + (((i) << 2)))
-#define RTL931X_TBL_ACCESS_CTRL_3		(0x0200)
-#define RTL931X_TBL_ACCESS_DATA_3(i)		(0x0204 + (((i) << 2)))
-#define RTL931X_TBL_ACCESS_CTRL_4		(0x20DC)
-#define RTL931X_TBL_ACCESS_DATA_4(i)		(0x20E0 + (((i) << 2)))
-#define RTL931X_TBL_ACCESS_CTRL_5		(0x7E1C)
-#define RTL931X_TBL_ACCESS_DATA_5(i)		(0x7E20 + (((i) << 2)))
-
-/* MAC handling */
-#define RTL838X_MAC_LINK_STS			(0xa188)
-#define RTL839X_MAC_LINK_STS			(0x0390)
-#define RTL930X_MAC_LINK_STS			(0xCB10)
-#define RTL931X_MAC_LINK_STS			(0x0EC0)
-#define RTL838X_MAC_LINK_SPD_STS(p)		(0xa190 + (((p >> 4) << 2)))
-#define RTL839X_MAC_LINK_SPD_STS(p)		(0x03a0 + (((p >> 4) << 2)))
-#define RTL930X_MAC_LINK_SPD_STS(p)		(0xCB18 + (((p >> 3) << 2)))
-#define RTL931X_MAC_LINK_SPD_STS(p)		(0x0ED0 + (((p >> 3) << 2)))
-#define RTL838X_MAC_LINK_DUP_STS		(0xa19c)
-#define RTL839X_MAC_LINK_DUP_STS		(0x03b0)
-#define RTL930X_MAC_LINK_DUP_STS		(0xCB28)
-#define RTL931X_MAC_LINK_DUP_STS		(0x0EF0)
-#define RTL838X_MAC_TX_PAUSE_STS		(0xa1a0)
-#define RTL839X_MAC_TX_PAUSE_STS		(0x03b8)
-#define RTL930X_MAC_TX_PAUSE_STS		(0xCB2C)
-#define RTL931X_MAC_TX_PAUSE_STS		(0x0EF8)
-#define RTL838X_MAC_RX_PAUSE_STS		(0xa1a4)
-#define RTL839X_MAC_RX_PAUSE_STS		(0x03c0)
-#define RTL930X_MAC_RX_PAUSE_STS		(0xCB30)
-#define RTL931X_MAC_RX_PAUSE_STS		(0x0F00)
-
-/* MAC link state bits */
-#define FORCE_EN				(1 << 0)
-#define FORCE_LINK_EN				(1 << 1)
-#define NWAY_EN					(1 << 2)
-#define DUPLX_MODE				(1 << 3)
-#define TX_PAUSE_EN				(1 << 6)
-#define RX_PAUSE_EN				(1 << 7)
-
-/* EEE */
-#define RTL838X_MAC_EEE_ABLTY			(0xa1a8)
-#define RTL838X_EEE_PORT_TX_EN			(0x014c)
-#define RTL838X_EEE_PORT_RX_EN			(0x0150)
-#define RTL838X_EEE_CLK_STOP_CTRL		(0x0148)
-#define RTL838X_EEE_TX_TIMER_GIGA_CTRL		(0xaa04)
-#define RTL838X_EEE_TX_TIMER_GELITE_CTRL	(0xaa08)
-
-#define RTL839X_EEE_TX_TIMER_GELITE_CTRL	(0x042C)
-#define RTL839X_EEE_TX_TIMER_GIGA_CTRL		(0x0430)
-#define RTL839X_EEE_TX_TIMER_10G_CTRL		(0x0434)
-#define RTL839X_EEE_CTRL(p)			(0x8008 + ((p) << 7))
-#define RTL839X_MAC_EEE_ABLTY			(0x03C8)
-
-#define RTL930X_MAC_EEE_ABLTY			(0xCB34)
-#define RTL930X_EEE_CTRL(p)			(0x3274 + ((p) << 6))
-#define RTL930X_EEEP_PORT_CTRL(p)		(0x3278 + ((p) << 6))
-
-/* L2 functionality */
-#define RTL838X_L2_CTRL_0			(0x3200)
-#define RTL839X_L2_CTRL_0			(0x3800)
-#define RTL930X_L2_CTRL				(0x8FD8)
-#define RTL931X_L2_CTRL				(0xC800)
-#define RTL838X_L2_CTRL_1			(0x3204)
-#define RTL839X_L2_CTRL_1			(0x3804)
-#define RTL930X_L2_AGE_CTRL			(0x8FDC)
-#define RTL931X_L2_AGE_CTRL			(0xC804)
-#define RTL838X_L2_PORT_AGING_OUT		(0x3358)
-#define RTL839X_L2_PORT_AGING_OUT		(0x3b74)
-#define	RTL930X_L2_PORT_AGE_CTRL		(0x8FE0)
-#define	RTL931X_L2_PORT_AGE_CTRL		(0xc808)
-#define RTL838X_TBL_ACCESS_L2_CTRL		(0x6900)
-#define RTL839X_TBL_ACCESS_L2_CTRL		(0x1180)
-#define RTL930X_TBL_ACCESS_L2_CTRL		(0xB320)
-#define RTL930X_TBL_ACCESS_L2_METHOD_CTRL	(0xB324)
-#define RTL838X_TBL_ACCESS_L2_DATA(idx)		(0x6908 + ((idx) << 2))
-#define RTL839X_TBL_ACCESS_L2_DATA(idx)		(0x1184 + ((idx) << 2))
-#define RTL930X_TBL_ACCESS_L2_DATA(idx)		(0xab08 + ((idx) << 2))
-#define RTL838X_L2_TBL_FLUSH_CTRL		(0x3370)
-#define RTL839X_L2_TBL_FLUSH_CTRL		(0x3ba0)
-#define RTL930X_L2_TBL_FLUSH_CTRL		(0x9404)
-#define RTL931X_L2_TBL_FLUSH_CTRL		(0xCD9C)
-
-#define RTL838X_L2_PORT_NEW_SALRN(p)		(0x328c + (((p >> 4) << 2)))
-#define RTL839X_L2_PORT_NEW_SALRN(p)		(0x38F0 + (((p >> 4) << 2)))
-#define RTL930X_L2_PORT_SALRN(p)		(0x8FEC + (((p >> 4) << 2)))
-#define RTL931X_L2_PORT_NEW_SALRN(p)		(0xC820 + (((p >> 4) << 2)))
-#define RTL838X_L2_PORT_NEW_SA_FWD(p)		(0x3294 + (((p >> 4) << 2)))
-#define RTL839X_L2_PORT_NEW_SA_FWD(p)		(0x3900 + (((p >> 4) << 2)))
-#define RTL930X_L2_PORT_NEW_SA_FWD(p)		(0x8FF4 + (((p / 10) << 2)))
-#define RTL931X_L2_PORT_NEW_SA_FWD(p)		(0xC830 + (((p / 10) << 2)))
-
-#define RTL930X_ST_CTRL				(0x8798)
-
-#define RTL930X_L2_PORT_SABLK_CTRL		(0x905c)
-#define RTL930X_L2_PORT_DABLK_CTRL		(0x9060)
-
-#define RTL838X_RMA_BPDU_FLD_PMSK		(0x4348)
-#define RTL930X_RMA_BPDU_FLD_PMSK		(0x9F18)
-#define RTL931X_RMA_BPDU_FLD_PMSK		(0x8950)
-#define RTL839X_RMA_BPDU_FLD_PMSK		(0x125C)
-
-#define RTL838X_L2_PORT_LM_ACT(p)		(0x3208 + ((p) << 2))
-#define RTL838X_VLAN_PORT_FWD			(0x3A78)
-#define RTL839X_VLAN_PORT_FWD			(0x27AC)
-#define RTL930X_VLAN_PORT_FWD			(0x834C)
-#define RTL838X_VLAN_FID_CTRL			(0x3aa8)
-
-/* Port Mirroring */
-#define RTL838X_MIR_CTRL			(0x5D00)
-#define RTL838X_MIR_DPM_CTRL			(0x5D20)
-#define RTL838X_MIR_SPM_CTRL			(0x5D10)
-
-#define RTL839X_MIR_CTRL			(0x2500)
-#define RTL839X_MIR_DPM_CTRL			(0x2530)
-#define RTL839X_MIR_SPM_CTRL			(0x2510)
-
-#define RTL930X_MIR_CTRL			(0xA2A0)
-#define RTL930X_MIR_DPM_CTRL			(0xA2C0)
-#define RTL930X_MIR_SPM_CTRL			(0xA2B0)
-
-#define RTL931X_MIR_CTRL			(0xAF00)
-#define RTL931X_MIR_DPM_CTRL			(0xAF30)
-#define RTL931X_MIR_SPM_CTRL			(0xAF10)
-
-/* Storm/rate control and scheduling */
-#define RTL838X_STORM_CTRL			(0x4700)
-#define RTL839X_STORM_CTRL			(0x1800)
-#define RTL838X_STORM_CTRL_LB_CTRL(p)		(0x4884 + (((p) << 2)))
-#define RTL838X_STORM_CTRL_BURST_PPS_0		(0x4874)
-#define RTL838X_STORM_CTRL_BURST_PPS_1		(0x4878)
-#define RTL838X_STORM_CTRL_BURST_0		(0x487c)
-#define RTL838X_STORM_CTRL_BURST_1		(0x4880)
-#define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_0	(0x1804)
-#define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_1	(0x1808)
-#define RTL838X_SCHED_CTRL			(0xB980)
-#define RTL839X_SCHED_CTRL			(0x60F4)
-#define RTL838X_SCHED_LB_TICK_TKN_CTRL_0	(0xAD58)
-#define RTL838X_SCHED_LB_TICK_TKN_CTRL_1	(0xAD5C)
-#define RTL839X_SCHED_LB_TICK_TKN_CTRL_0	(0x1804)
-#define RTL839X_SCHED_LB_TICK_TKN_CTRL_1	(0x1808)
-#define RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL (0x2000)
-#define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0	(0x1604)
-#define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1	(0x1608)
-#define RTL839X_SCHED_LB_TICK_TKN_CTRL		(0x60F8)
-#define RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL	(0x6200)
-#define RTL838X_SCHED_LB_THR			(0xB984)
-#define RTL839X_SCHED_LB_THR			(0x60FC)
-#define RTL838X_SCHED_P_EGR_RATE_CTRL(p)	(0xC008 + (((p) << 7)))
-#define RTL838X_SCHED_Q_EGR_RATE_CTRL(p, q)	(0xC00C + (p << 7) + (((q) << 2)))
-#define RTL838X_STORM_CTRL_PORT_BC_EXCEED	(0x470C)
-#define RTL838X_STORM_CTRL_PORT_MC_EXCEED	(0x4710)
-#define RTL838X_STORM_CTRL_PORT_UC_EXCEED	(0x4714)
-#define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p)	(0x180c + (((p >> 5) << 2)))
-#define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p)	(0x1814 + (((p >> 5) << 2)))
-#define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p)	(0x181c + (((p >> 5) << 2)))
-#define RTL838X_STORM_CTRL_PORT_UC(p)		(0x4718 + (((p) << 2)))
-#define RTL838X_STORM_CTRL_PORT_MC(p)		(0x478c + (((p) << 2)))
-#define RTL838X_STORM_CTRL_PORT_BC(p)		(0x4800 + (((p) << 2)))
-#define RTL839X_STORM_CTRL_PORT_UC_0(p)		(0x185C + (((p) << 3)))
-#define RTL839X_STORM_CTRL_PORT_UC_1(p)		(0x1860 + (((p) << 3)))
-#define RTL839X_STORM_CTRL_PORT_MC_0(p)		(0x19FC + (((p) << 3)))
-#define RTL839X_STORM_CTRL_PORT_MC_1(p)		(0x1a00 + (((p) << 3)))
-#define RTL839X_STORM_CTRL_PORT_BC_0(p)		(0x1B9C + (((p) << 3)))
-#define RTL839X_STORM_CTRL_PORT_BC_1(p)		(0x1BA0 + (((p) << 3)))
-#define RTL839X_TBL_ACCESS_CTRL_2		(0x611C)
-#define RTL839X_TBL_ACCESS_DATA_2(i)		(0x6120 + (((i) << 2)))
-#define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p)	(0x1618 + (((p) << 3)))
-#define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_1(p)	(0x161C + (((p) << 3)))
-#define RTL839X_IGR_BWCTRL_PORT_CTRL_0(p)	(0x1640 + (((p) << 3)))
-#define RTL839X_IGR_BWCTRL_PORT_CTRL_1(p)	(0x1644 + (((p) << 3)))
-#define RTL839X_IGR_BWCTRL_CTRL_LB_THR		(0x1614)
-
-/* Link aggregation (Trunking) */
-#define RTL839X_TRK_MBR_CTR			(0x2200)
-#define RTL838X_TRK_MBR_CTR			(0x3E00)
-#define RTL930X_TRK_MBR_CTRL			(0xA41C)
-#define RTL931X_TRK_MBR_CTRL			(0xB8D0)
-
-/* Attack prevention */
-#define RTL838X_ATK_PRVNT_PORT_EN		(0x5B00)
-#define RTL838X_ATK_PRVNT_CTRL			(0x5B04)
-#define RTL838X_ATK_PRVNT_ACT			(0x5B08)
-#define RTL838X_ATK_PRVNT_STS			(0x5B1C)
-
-/* 802.1X */
-#define RTL838X_SPCL_TRAP_EAPOL_CTRL		(0x6988)
-#define RTL839X_SPCL_TRAP_EAPOL_CTRL		(0x105C)
-
-/* QoS */
-#define RTL838X_QM_INTPRI2QID_CTRL		(0x5F00)
-#define RTL839X_QM_INTPRI2QID_CTRL(q)		(0x1110 + (q << 2))
-#define RTL839X_QM_PORT_QNUM(p)			(0x1130 + (((p / 10) << 2)))
-#define RTL838X_PRI_SEL_PORT_PRI(p)		(0x5FB8 + (((p / 10) << 2)))
-#define RTL839X_PRI_SEL_PORT_PRI(p)		(0x10A8 + (((p / 10) << 2)))
-#define RTL838X_QM_PKT2CPU_INTPRI_MAP		(0x5F10)
-#define RTL839X_QM_PKT2CPU_INTPRI_MAP		(0x1154)
-#define RTL838X_PRI_SEL_CTRL			(0x10E0)
-#define RTL839X_PRI_SEL_CTRL			(0x10E0)
-#define RTL838X_PRI_SEL_TBL_CTRL(i)		(0x5FD8 + (((i) << 2)))
-#define RTL839X_PRI_SEL_TBL_CTRL(i)		(0x10D0 + (((i) << 2)))
-#define RTL838X_QM_PKT2CPU_INTPRI_0		(0x5F04)
-#define RTL838X_QM_PKT2CPU_INTPRI_1		(0x5F08)
-#define RTL838X_QM_PKT2CPU_INTPRI_2		(0x5F0C)
-#define RTL839X_OAM_CTRL			(0x2100)
-#define RTL839X_OAM_PORT_ACT_CTRL(p)	 	(0x2104 + (((p) << 2)))
-#define RTL839X_RMK_PORT_DEI_TAG_CTRL(p)	(0x6A9C + (((p >> 5) << 2)))
-#define RTL839X_PRI_SEL_IPRI_REMAP		(0x1080)
-#define RTL838X_PRI_SEL_IPRI_REMAP		(0x5F8C)
-#define RTL839X_PRI_SEL_DEI2DP_REMAP		(0x10EC)
-#define RTL839X_PRI_SEL_DSCP2DP_REMAP_ADDR(i)	(0x10F0 + (((i >> 4) << 2)))
-#define RTL839X_RMK_DEI_CTRL			(0x6AA4)
-#define RTL839X_WRED_PORT_THR_CTRL(i)		(0x6084 + ((i) << 2))
-#define RTL839X_WRED_QUEUE_THR_CTRL(q, i) 	(0x6090 + ((q) * 12) + ((i) << 2))
-#define RTL838X_PRI_DSCP_INVLD_CTRL0		(0x5FE8)
-#define RTL838X_RMK_IPRI_CTRL			(0xA460)
-#define RTL838X_RMK_OPRI_CTRL			(0xA464)
-#define RTL838X_SCHED_P_TYPE_CTRL(p)		(0xC04C + (((p) << 7)))
-#define RTL838X_SCHED_LB_CTRL(p)		(0xC004 + (((p) << 7)))
-#define RTL838X_FC_P_EGR_DROP_CTRL(p)		(0x6B1C + (((p) << 2)))
-
-/* Debug features */
-#define RTL930X_STAT_PRVTE_DROP_COUNTER0	(0xB5B8)
-
-#define MAX_VLANS 4096
-#define MAX_LAGS 16
-#define MAX_PRIOS 8
-#define RTL930X_PORT_IGNORE 0x3f
-#define MAX_MC_GROUPS 512
-#define UNKNOWN_MC_PMASK (MAX_MC_GROUPS - 1)
-
-enum phy_type {
-	PHY_NONE = 0,
-	PHY_RTL838X_SDS = 1,
-	PHY_RTL8218B_INT = 2,
-	PHY_RTL8218B_EXT = 3,
-	PHY_RTL8214FC = 4,
-	PHY_RTL839X_SDS = 5,
-};
-
-struct rtl838x_port {
-	bool enable;
-	u64 pm;
-	u16 pvid;
-	bool eee_enabled;
-	enum phy_type phy;
-	bool is10G;
-	bool is2G5;
-	u8 sds_num;
-	const struct dsa_port *dp;
-};
-
-struct rtl838x_vlan_info {
-	u64 untagged_ports;
-	u64 tagged_ports;
-	u8 profile_id;
-	bool hash_mc_fid;
-	bool hash_uc_fid;
-	u8 fid;
-};
-
-enum l2_entry_type {
-	L2_INVALID = 0,
-	L2_UNICAST = 1,
-	L2_MULTICAST = 2,
-	IP4_MULTICAST = 3,
-	IP6_MULTICAST = 4,
-};
-
-struct rtl838x_l2_entry {
-	u8 mac[6];
-	u16 vid;
-	u16 rvid;
-	u8 port;
-	bool valid;
-	enum l2_entry_type type;
-	bool is_static;
-	bool is_ip_mc;
-	bool is_ipv6_mc;
-	bool block_da;
-	bool block_sa;
-	bool suspended;
-	bool next_hop;
-	int age;
-	u8 trunk;
-	bool is_trunk;
-	u8 stack_dev;
-	u16 mc_portmask_index;
-	u32 mc_gip;
-	u32 mc_sip;
-	u16 mc_mac_index;
-	u16 nh_route_id;
-	bool nh_vlan_target;  // Only RTL83xx: VLAN used for next hop
-};
-
-struct rtl838x_nexthop {
-	u16 id;		// ID in HW Nexthop table
-	u32 ip;		// IP Addres of nexthop
-	u32 dev_id;
-	u16 port;
-	u16 vid;
-	u16 fid;
-	u64 mac;
-	u16 mac_id;
-	u16 l2_id;	// Index of this next hop forwarding entry in L2 FIB table
-	u16 if_id;
-};
-
-struct rtl838x_switch_priv;
-
-struct rtl838x_reg {
-	void (*mask_port_reg_be)(u64 clear, u64 set, int reg);
-	void (*set_port_reg_be)(u64 set, int reg);
-	u64 (*get_port_reg_be)(int reg);
-	void (*mask_port_reg_le)(u64 clear, u64 set, int reg);
-	void (*set_port_reg_le)(u64 set, int reg);
-	u64 (*get_port_reg_le)(int reg);
-	int stat_port_rst;
-	int stat_rst;
-	int stat_port_std_mib;
-	int (*port_iso_ctrl)(int p);
-	void (*traffic_enable)(int source, int dest);
-	void (*traffic_disable)(int source, int dest);
-	void (*traffic_set)(int source, u64 dest_matrix);
-	u64 (*traffic_get)(int source);
-	int l2_ctrl_0;
-	int l2_ctrl_1;
-	int l2_port_aging_out;
-	int smi_poll_ctrl;
-	int l2_tbl_flush_ctrl;
-	void (*exec_tbl0_cmd)(u32 cmd);
-	void (*exec_tbl1_cmd)(u32 cmd);
-	int (*tbl_access_data_0)(int i);
-	int isr_glb_src;
-	int isr_port_link_sts_chg;
-	int imr_port_link_sts_chg;
-	int imr_glb;
-	void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
-	void (*vlan_set_tagged)(u32 vlan, struct rtl838x_vlan_info *info);
-	void (*vlan_set_untagged)(u32 vlan, u64 portmask);
-	void (*vlan_profile_dump)(int index);
-	void (*vlan_profile_setup)(int profile);
-	void (*stp_get)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]);
-	void (*stp_set)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]);
-	int  (*mac_force_mode_ctrl)(int port);
-	int  (*mac_port_ctrl)(int port);
-	int  (*l2_port_new_salrn)(int port);
-	int  (*l2_port_new_sa_fwd)(int port);
-	int mir_ctrl;
-	int mir_dpm;
-	int mir_spm;
-	int mac_link_sts;
-	int mac_link_dup_sts;
-	int  (*mac_link_spd_sts)(int port);
-	int mac_rx_pause_sts;
-	int mac_tx_pause_sts;
-	u64 (*read_l2_entry_using_hash)(u32 hash, u32 position, struct rtl838x_l2_entry *e);
-	void (*write_l2_entry_using_hash)(u32 hash, u32 pos, struct rtl838x_l2_entry *e);
-	u64 (*read_cam)(int idx, struct rtl838x_l2_entry *e);
-	void (*write_cam)(int idx, struct rtl838x_l2_entry *e);
-	int vlan_port_egr_filter;
-	int vlan_port_igr_filter;
-	int vlan_port_pb;
-	int vlan_port_tag_sts_ctrl;
-	int (*rtl838x_vlan_port_tag_sts_ctrl)(int port);
-	int (*trk_mbr_ctr)(int group);
-	int rma_bpdu_fld_pmask;
-	int spcl_trap_eapol_ctrl;
-	void (*init_eee)(struct rtl838x_switch_priv *priv, bool enable);
-	void (*port_eee_set)(struct rtl838x_switch_priv *priv, int port, bool enable);
-	int (*eee_port_ability)(struct rtl838x_switch_priv *priv,
-				struct ethtool_eee *e, int port);
-	u64 (*l2_hash_seed)(u64 mac, u32 vid);
-	u32 (*l2_hash_key)(struct rtl838x_switch_priv *priv, u64 seed);
-	u64 (*read_mcast_pmask)(int idx);
-	void (*write_mcast_pmask)(int idx, u64 portmask);
-	void (*vlan_fwd_on_inner)(int port, bool is_set);
-};
-
-struct rtl838x_switch_priv {
-	/* Switch operation */
-	struct dsa_switch *ds;
-	struct device *dev;
-	u16 id;
-	u16 family_id;
-	char version;
-	struct rtl838x_port ports[57];
-	struct mutex reg_mutex;
-	int link_state_irq;
-	int mirror_group_ports[4];
-	struct mii_bus *mii_bus;
-	const struct rtl838x_reg *r;
-	u8 cpu_port;
-	u8 port_mask;
-	u8 port_width;
-	u64 irq_mask;
-	u32 fib_entries;
-	int l2_bucket_size;
-	struct dentry *dbgfs_dir;
-	int n_lags;
-	u64 lags_port_members[MAX_LAGS];
-	struct net_device *lag_devs[MAX_LAGS];
-	struct notifier_block nb;
-	bool eee_enabled;
-	unsigned long int mc_group_bm[MAX_MC_GROUPS >> 5];
-};
-
-void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv);
-
-#endif /* _RTL838X_H */
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c
deleted file mode 100644
index c62dc441c1..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c
+++ /dev/null
@@ -1,807 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <asm/mach-rtl838x/mach-rtl83xx.h>
-#include "rtl83xx.h"
-
-extern struct mutex smi_lock;
-extern struct rtl83xx_soc_info soc_info;
-
-void rtl839x_print_matrix(void)
-{
-	volatile u64 *ptr9;
-	int i;
-
-	ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
-	for (i = 0; i < 52; i += 4)
-		pr_debug("> %16llx %16llx %16llx %16llx\n",
-			ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
-	pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
-}
-
-static inline int rtl839x_port_iso_ctrl(int p)
-{
-	return RTL839X_PORT_ISO_CTRL(p);
-}
-
-static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
-{
-	sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
-	do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
-}
-
-static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
-{
-	sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
-	do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
-}
-
-inline void rtl839x_exec_tbl2_cmd(u32 cmd)
-{
-	sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_2);
-	do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2) & (1 << 9));
-}
-
-static inline int rtl839x_tbl_access_data_0(int i)
-{
-	return RTL839X_TBL_ACCESS_DATA_0(i);
-}
-
-static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
-{
-	u32 u, v, w;
-	// Read VLAN table (0) via register 0
-	struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
-
-	rtl_table_read(r, vlan);
-	u = sw_r32(rtl_table_data(r, 0));
-	v = sw_r32(rtl_table_data(r, 1));
-	w = sw_r32(rtl_table_data(r, 2));
-	rtl_table_release(r);
-
-	info->tagged_ports = u;
-	info->tagged_ports = (info->tagged_ports << 21) | ((v >> 11) & 0x1fffff);
-	info->profile_id = w >> 30 | ((v & 1) << 2);
-	info->hash_mc_fid = !!(w & BIT(2));
-	info->hash_uc_fid = !!(w & BIT(3));
-	info->fid = (v >> 3) & 0xff;
-
-	// Read UNTAG table (0) via table register 1
-	r = rtl_table_get(RTL8390_TBL_1, 0);
-	rtl_table_read(r, vlan);
-	u = sw_r32(rtl_table_data(r, 0));
-	v = sw_r32(rtl_table_data(r, 1));
-	rtl_table_release(r);
-
-	info->untagged_ports = u;
-	info->untagged_ports = (info->untagged_ports << 21) | ((v >> 11) & 0x1fffff);
-}
-
-static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
-{
-	u32 u, v, w;
-	// Access VLAN table (0) via register 0
-	struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
-
-	u = info->tagged_ports >> 21;
-	v = info->tagged_ports << 11;
-	v |= ((u32)info->fid) << 3;
-	v |= info->hash_uc_fid ? BIT(2) : 0;
-	v |= info->hash_mc_fid ? BIT(1) : 0;
-	v |= (info->profile_id & 0x4) ? 1 : 0;
-	w = ((u32)(info->profile_id & 3)) << 30;
-
-	sw_w32(u, rtl_table_data(r, 0));
-	sw_w32(v, rtl_table_data(r, 1));
-	sw_w32(w, rtl_table_data(r, 2));
-
-	rtl_table_write(r, vlan);
-	rtl_table_release(r);
-}
-
-static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
-{
-	u32 u, v;
-
-	// Access UNTAG table (0) via table register 1
-	struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 0);
-
-	u = portmask >> 21;
-	v = portmask << 11;
-
-	sw_w32(u, rtl_table_data(r, 0));
-	sw_w32(v, rtl_table_data(r, 1));
-	rtl_table_write(r, vlan);
-
-	rtl_table_release(r);
-}
-
-/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
- */
-static void rtl839x_vlan_fwd_on_inner(int port, bool is_set)
-{
-	if (is_set)
-		rtl839x_mask_port_reg_be(BIT_ULL(port), 0ULL, RTL839X_VLAN_PORT_FWD);
-	else
-		rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port), RTL839X_VLAN_PORT_FWD);
-}
-
-/*
- * Hash seed is vid (actually rvid) concatenated with the MAC address
- */
-static u64 rtl839x_l2_hash_seed(u64 mac, u32 vid)
-{
-	u64 v = vid;
-
-	v <<= 48;
-	v |= mac;
-
-	return v;
-}
-
-/*
- * Applies the same hash algorithm as the one used currently by the ASIC to the seed
- * and returns a key into the L2 hash table
- */
-static u32 rtl839x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
-{
-	u32 h1, h2, h;
-
-	if (sw_r32(priv->r->l2_ctrl_0) & 1) {
-		h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)
-				^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)
-				^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
-		h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)
-				^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)
-				^ (seed & 0x3f));
-		h = (h1 << 6) | h2;
-	} else {
-		h = (seed >> 60)
-			^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))
-			^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)
-			^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
-	}
-
-	return h;
-}
-
-static inline int rtl839x_mac_force_mode_ctrl(int p)
-{
-	return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
-}
-
-static inline int rtl839x_mac_port_ctrl(int p)
-{
-	return RTL839X_MAC_PORT_CTRL(p);
-}
-
-static inline int rtl839x_l2_port_new_salrn(int p)
-{
-	return RTL839X_L2_PORT_NEW_SALRN(p);
-}
-
-static inline int rtl839x_l2_port_new_sa_fwd(int p)
-{
-	return RTL839X_L2_PORT_NEW_SA_FWD(p);
-}
-
-static inline int rtl839x_mac_link_spd_sts(int p)
-{
-	return RTL839X_MAC_LINK_SPD_STS(p);
-}
-
-static inline int rtl839x_trk_mbr_ctr(int group)
-{
-	return RTL839X_TRK_MBR_CTR + (group << 3);
-}
-
-static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
-{
-	/* Table contains different entry types, we need to identify the right one:
-	 * Check for MC entries, first
-	 */
-	e->is_ip_mc = !!(r[2] & BIT(31));
-	e->is_ipv6_mc = !!(r[2] & BIT(30));
-	e->type = L2_INVALID;
-	if (!e->is_ip_mc) {
-		e->mac[0] = (r[0] >> 12);
-		e->mac[1] = (r[0] >> 4);
-		e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
-		e->mac[3] = (r[1] >> 20);
-		e->mac[4] = (r[1] >> 12);
-		e->mac[5] = (r[1] >> 4);
-
-		/* Is it a unicast entry? check multicast bit */
-		if (!(e->mac[0] & 1)) {
-			e->is_static = !!((r[2] >> 18) & 1);
-			e->vid = (r[2] >> 4) & 0xfff;
-			e->rvid = (r[0] >> 20) & 0xfff;
-			e->port = (r[2] >> 24) & 0x3f;
-			e->block_da = !!(r[2] & (1 << 19));
-			e->block_sa = !!(r[2] & (1 << 20));
-			e->suspended = !!(r[2] & (1 << 17));
-			e->next_hop = !!(r[2] & (1 << 16));
-			if (e->next_hop)
-				pr_info("Found next hop entry, need to read data\n");
-			e->age = (r[2] >> 21) & 3;
-			e->valid = true;
-			if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
-				e->valid = false;
-			else
-				e->type = L2_UNICAST;
-		} else {
-			e->valid = true;
-			e->type = L2_MULTICAST;
-			e->mc_portmask_index = (r[2]>>6) & 0xfff;
-		}
-	}
-	if (e->is_ip_mc) {
-		e->valid = true;
-		e->type = IP4_MULTICAST;
-	}
-	if (e->is_ipv6_mc) {
-		e->valid = true;
-		e->type = IP6_MULTICAST;
-	}
-}
-
-/*
- * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry
- */
-static void rtl839x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
-{
-	if (!e->valid) {
-		r[0] = r[1] = r[2] = 0;
-		return;
-	}
-
-	r[2] = e->is_ip_mc ? BIT(31) : 0;
-	r[2] |= e->is_ipv6_mc ? BIT(30) : 0;
-
-	if (!e->is_ip_mc  && !e->is_ipv6_mc) {
-		r[0] = ((u32)e->mac[0]) << 12;
-		r[0] |= ((u32)e->mac[1]) << 4;
-		r[0] |= ((u32)e->mac[2]) >> 4;
-		r[1] = ((u32)e->mac[2]) << 28;
-		r[1] |= ((u32)e->mac[3]) << 20;
-		r[1] |= ((u32)e->mac[4]) << 12;
-		r[1] |= ((u32)e->mac[5]) << 4;
-
-		if (!(e->mac[0] & 1)) { // Not multicast
-			r[2] |= e->is_static ? BIT(18) : 0;
-			r[2] |= e->vid << 4;
-			r[0] |= ((u32)e->rvid) << 20;
-			r[2] |= e->port << 24;
-			r[2] |= e->block_da ? BIT(19) : 0;
-			r[2] |= e->block_sa ? BIT(20) : 0;
-			r[2] |= e->suspended ? BIT(17) : 0;
-			if (e->next_hop) {
-				r[2] |= BIT(16);
-				r[2] |= e->nh_vlan_target ? BIT(15) : 0;
-				r[2] |= (e->nh_route_id & 0x7ff) << 4;
-			}
-			r[2] |= ((u32)e->age) << 21;
-		} else {  // L2 Multicast
-			r[0] |= ((u32)e->rvid) << 20;
-			r[2] |= ((u32)e->mc_portmask_index) << 6;
-			pr_debug("Write L2 MC entry: %08x %08x %08x\n", r[0], r[1], r[2]);
-		}
-	} else { // IPv4 or IPv6 MC entry
-		r[0] = ((u32)e->rvid) << 20;
-		r[2] |= ((u32)e->mc_portmask_index) << 6;
-		r[1] = e->mc_gip;
-	}
-}
-
-/*
- * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
- * hash is the id of the bucket and pos is the position of the entry in that bucket
- * The data read from the SoC is filled into rtl838x_l2_entry
- */
-static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
-{
-	u32 r[3];
-	struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);
-	u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket
-	int i;
-
-	rtl_table_read(q, idx);
-	for (i= 0; i < 3; i++)
-		r[i] = sw_r32(rtl_table_data(q, i));
-
-	rtl_table_release(q);
-
-	rtl839x_fill_l2_entry(r, e);
-	if (!e->valid)
-		return 0;
-
-	return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);
-}
-
-static void rtl839x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
-{
-	u32 r[3];
-	struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);
-	int i;
-
-	u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket
-
-	rtl839x_fill_l2_row(r, e);
-
-	for (i= 0; i < 3; i++)
-		sw_w32(r[i], rtl_table_data(q, i));
-
-	rtl_table_write(q, idx);
-	rtl_table_release(q);
-}
-
-static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
-{
-	u32 r[3];
-	struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1
-	int i;
-
-	rtl_table_read(q, idx);
-	for (i= 0; i < 3; i++)
-		r[i] = sw_r32(rtl_table_data(q, i));
-
-	rtl_table_release(q);
-
-	rtl839x_fill_l2_entry(r, e);
-	if (!e->valid)
-		return 0;
-
-	pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
-
-	// Return MAC with concatenated VID ac concatenated ID
-	return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);
-}
-
-static void rtl839x_write_cam(int idx, struct rtl838x_l2_entry *e)
-{
-	u32 r[3];
-	struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1
-	int i;
-
-	rtl839x_fill_l2_row(r, e);
-
-	for (i= 0; i < 3; i++)
-		sw_w32(r[i], rtl_table_data(q, i));
-
-	rtl_table_write(q, idx);
-	rtl_table_release(q);
-}
-
-static u64 rtl839x_read_mcast_pmask(int idx)
-{
-	u64 portmask;
-	// Read MC_PMSK (2) via register RTL8390_TBL_L2
-	struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
-
-	rtl_table_read(q, idx);
-	portmask = sw_r32(rtl_table_data(q, 0));
-	portmask <<= 32;
-	portmask |= sw_r32(rtl_table_data(q, 1));
-	portmask >>= 11;  // LSB is bit 11 in data registers
-	rtl_table_release(q);
-
-	return portmask;
-}
-
-static void rtl839x_write_mcast_pmask(int idx, u64 portmask)
-{
-	// Access MC_PMSK (2) via register RTL8380_TBL_L2
-	struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
-
-	portmask <<= 11; // LSB is bit 11 in data registers
-	sw_w32((u32)(portmask >> 32), rtl_table_data(q, 0));
-	sw_w32((u32)((portmask & 0xfffff800)), rtl_table_data(q, 1));
-	rtl_table_write(q, idx);
-	rtl_table_release(q);
-}
-
-static void rtl839x_vlan_profile_setup(int profile)
-{
-	u32 p[2];
-	u32 pmask_id = UNKNOWN_MC_PMASK;
-
-	p[0] = pmask_id; // Use portmaks 0xfff for unknown IPv6 MC flooding
-	// Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding
-	p[1] = 1 | pmask_id << 1 | pmask_id << 13;
-
-	sw_w32(p[0], RTL839X_VLAN_PROFILE(profile));
-	sw_w32(p[1], RTL839X_VLAN_PROFILE(profile) + 4);
-
-	rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x001fffffffffffff);
-}
-
-static inline int rtl839x_vlan_port_egr_filter(int port)
-{
-	return RTL839X_VLAN_PORT_EGR_FLTR(port);
-}
-
-static inline int rtl839x_vlan_port_igr_filter(int port)
-{
-	return RTL839X_VLAN_PORT_IGR_FLTR(port);
-}
-
-u64 rtl839x_traffic_get(int source)
-{
-	return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source));
-}
-
-void rtl839x_traffic_set(int source, u64 dest_matrix)
-{
-	rtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source));
-}
-
-void rtl839x_traffic_enable(int source, int dest)
-{
-	rtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source));
-}
-
-void rtl839x_traffic_disable(int source, int dest)
-{
-	rtl839x_mask_port_reg_be(BIT_ULL(dest), 0, rtl839x_port_iso_ctrl(source));
-}
-
-irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
-{
-	struct dsa_switch *ds = dev_id;
-	u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
-	u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
-	u64 link;
-	int i;
-
-	/* Clear status */
-	rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
-	pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
-
-	for (i = 0; i < RTL839X_CPU_PORT; i++) {
-		if (ports & BIT_ULL(i)) {
-			link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
-			if (link & BIT_ULL(i))
-				dsa_port_phylink_mac_change(ds, i, true);
-			else
-				dsa_port_phylink_mac_change(ds, i, false);
-		}
-	}
-	return IRQ_HANDLED;
-}
-
-// TODO: unused
-int rtl8390_sds_power(int mac, int val)
-{
-	u32 offset = (mac == 48) ? 0x0 : 0x100;
-	u32 mode = val ? 0 : 1;
-
-	pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
-
-	if ((mac != 48) && (mac != 49)) {
-		pr_err("%s: not an SFP port: %d\n", __func__, mac);
-		return -1;
-	}
-
-	// Set bit 1003. 1000 starts at 7c
-	sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
-
-	return 0;
-}
-
-int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
-{
-	u32 v;
-
-	if (port > 63 || page > 4095 || reg > 31)
-		return -ENOTSUPP;
-
-	mutex_lock(&smi_lock);
-
-	sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
-	v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
-	sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
-
-	sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
-
-	v |= 1;
-	sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
-
-	do {
-	} while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
-
-	*val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
-
-	mutex_unlock(&smi_lock);
-	return 0;
-}
-
-int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
-{
-	u32 v;
-	int err = 0;
-
-	val &= 0xffff;
-	if (port > 63 || page > 4095 || reg > 31)
-		return -ENOTSUPP;
-
-	mutex_lock(&smi_lock);
-
-	// Set PHY to access
-	rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
-
-	sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
-
-	v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
-	sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
-
-	sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
-
-	v |= BIT(3) | 1; /* Write operation and execute */
-	sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
-
-	do {
-	} while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
-
-	if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
-		err = -EIO;
-
-	mutex_unlock(&smi_lock);
-	return err;
-}
-
-/*
- * Read an mmd register of the PHY
- */
-int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
-{
-	int err = 0;
-	u32 v;
-
-	mutex_lock(&smi_lock);
-
-	// Set PHY to access
-	sw_w32_mask(0xffff << 16, port << 16, RTL839X_PHYREG_DATA_CTRL);
-
-	// Set MMD device number and register to write to
-	sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
-
-	v = BIT(2) | BIT(0); // MMD-access | EXEC
-	sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
-
-	do {
-		v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);
-	} while (v & BIT(0));
-	// There is no error-checking via BIT 1 of v, as it does not seem to be set correctly
-	*val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff);
-	pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
-
-	mutex_unlock(&smi_lock);
-
-	return err;
-}
-
-/*
- * Write to an mmd register of the PHY
- */
-int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
-{
-	int err = 0;
-	u32 v;
-
-	mutex_lock(&smi_lock);
-
-	// Set PHY to access
-	rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
-
-	// Set data to write
-	sw_w32_mask(0xffff << 16, val << 16, RTL839X_PHYREG_DATA_CTRL);
-
-	// Set MMD device number and register to write to
-	sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
-
-	v = BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC
-	sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
-
-	do {
-		v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);
-	} while (v & BIT(0));
-
-	pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
-	mutex_unlock(&smi_lock);
-	return err;
-}
-
-void rtl8390_get_version(struct rtl838x_switch_priv *priv)
-{
-	u32 info;
-
-	sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
-	info = sw_r32(RTL839X_CHIP_INFO);
-	pr_debug("Chip-Info: %x\n", info);
-	priv->version = RTL8390_VERSION_A;
-}
-
-void rtl839x_vlan_profile_dump(int profile)
-{
-	u32 p[2];
-
-	if (profile < 0 || profile > 7)
-		return;
-
-	p[0] = sw_r32(RTL839X_VLAN_PROFILE(profile));
-	p[1] = sw_r32(RTL839X_VLAN_PROFILE(profile) + 4);
-
-	pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
-		UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
-		profile, p[1] & 1, (p[1] >> 1) & 0xfff, (p[1] >> 13) & 0xfff,
-		(p[0]) & 0xfff);
-	pr_info("VLAN profile %d: raw %08x, %08x\n", profile, p[0], p[1]);
-}
-
-static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
-{
-	int i;
-	u32 cmd = 1 << 16 /* Execute cmd */
-		| 0 << 15 /* Read */
-		| 5 << 12 /* Table type 0b101 */
-		| (msti & 0xfff);
-	priv->r->exec_tbl0_cmd(cmd);
-
-	for (i = 0; i < 4; i++)
-		port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
-}
-
-static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
-{
-	int i;
-	u32 cmd = 1 << 16 /* Execute cmd */
-		| 1 << 15 /* Write */
-		| 5 << 12 /* Table type 0b101 */
-		| (msti & 0xfff);
-	for (i = 0; i < 4; i++)
-		sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
-	priv->r->exec_tbl0_cmd(cmd);
-}
-
-/*
- * Enables or disables the EEE/EEEP capability of a port
- */
-void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
-{
-	u32 v;
-
-	// This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP
-	if (port >= 48)
-		return;
-
-	enable = true;
-	pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
-	v = enable ? 0xf : 0x0;
-
-	// Set EEE for 100, 500, 1000MBit and 10GBit
-	sw_w32_mask(0xf << 8, v << 8, rtl839x_mac_force_mode_ctrl(port));
-
-	// Set TX/RX EEE state
-	v = enable ? 0x3 : 0x0;
-	sw_w32(v, RTL839X_EEE_CTRL(port));
-
-	priv->ports[port].eee_enabled = enable;
-}
-
-/*
- * Get EEE own capabilities and negotiation result
- */
-int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
-{
-	u64 link, a;
-
-	if (port >= 48)
-		return 0;
-
-	link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
-	if (!(link & BIT_ULL(port)))
-		return 0;
-
-	if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(8))
-		e->advertised |= ADVERTISED_100baseT_Full;
-
-	if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(10))
-		e->advertised |= ADVERTISED_1000baseT_Full;
-
-	a = rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY);
-	pr_info("Link partner: %016llx\n", a);
-	if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY) & BIT_ULL(port)) {
-		e->lp_advertised = ADVERTISED_100baseT_Full;
-		e->lp_advertised |= ADVERTISED_1000baseT_Full;
-		return 1;
-	}
-
-	return 0;
-}
-
-static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
-{
-	int i;
-
-	pr_info("Setting up EEE, state: %d\n", enable);
-
-	// Set wake timer for TX and pause timer both to 0x21
-	sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL);
-	// Set pause wake timer for GIGA-EEE to 0x11
-	sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL);
-	// Set pause wake timer for 10GBit ports to 0x11
-	sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL);
-
-	// Setup EEE on all ports
-	for (i = 0; i < priv->cpu_port; i++) {
-		if (priv->ports[i].phy)
-			rtl839x_port_eee_set(priv, i, enable);
-	}
-	priv->eee_enabled = enable;
-}
-
-const struct rtl838x_reg rtl839x_reg = {
-	.mask_port_reg_be = rtl839x_mask_port_reg_be,
-	.set_port_reg_be = rtl839x_set_port_reg_be,
-	.get_port_reg_be = rtl839x_get_port_reg_be,
-	.mask_port_reg_le = rtl839x_mask_port_reg_le,
-	.set_port_reg_le = rtl839x_set_port_reg_le,
-	.get_port_reg_le = rtl839x_get_port_reg_le,
-	.stat_port_rst = RTL839X_STAT_PORT_RST,
-	.stat_rst = RTL839X_STAT_RST,
-	.stat_port_std_mib = RTL839X_STAT_PORT_STD_MIB,
-	.traffic_enable = rtl839x_traffic_enable,
-	.traffic_disable = rtl839x_traffic_disable,
-	.traffic_get = rtl839x_traffic_get,
-	.traffic_set = rtl839x_traffic_set,
-	.port_iso_ctrl = rtl839x_port_iso_ctrl,
-	.l2_ctrl_0 = RTL839X_L2_CTRL_0,
-	.l2_ctrl_1 = RTL839X_L2_CTRL_1,
-	.l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
-	.smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
-	.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
-	.exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
-	.exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
-	.tbl_access_data_0 = rtl839x_tbl_access_data_0,
-	.isr_glb_src = RTL839X_ISR_GLB_SRC,
-	.isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
-	.imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
-	.imr_glb = RTL839X_IMR_GLB,
-	.vlan_tables_read = rtl839x_vlan_tables_read,
-	.vlan_set_tagged = rtl839x_vlan_set_tagged,
-	.vlan_set_untagged = rtl839x_vlan_set_untagged,
-	.vlan_profile_dump = rtl839x_vlan_profile_dump,
-	.vlan_profile_setup = rtl839x_vlan_profile_setup,
-	.vlan_fwd_on_inner = rtl839x_vlan_fwd_on_inner,
-	.stp_get = rtl839x_stp_get,
-	.stp_set = rtl839x_stp_set,
-	.mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
-	.mac_port_ctrl = rtl839x_mac_port_ctrl,
-	.l2_port_new_salrn = rtl839x_l2_port_new_salrn,
-	.l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
-	.mir_ctrl = RTL839X_MIR_CTRL,
-	.mir_dpm = RTL839X_MIR_DPM_CTRL,
-	.mir_spm = RTL839X_MIR_SPM_CTRL,
-	.mac_link_sts = RTL839X_MAC_LINK_STS,
-	.mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
-	.mac_link_spd_sts = rtl839x_mac_link_spd_sts,
-	.mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
-	.mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
-	.read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
-	.write_l2_entry_using_hash = rtl839x_write_l2_entry_using_hash,
-	.read_cam = rtl839x_read_cam,
-	.write_cam = rtl839x_write_cam,
-	.vlan_port_egr_filter = RTL839X_VLAN_PORT_EGR_FLTR(0),
-	.vlan_port_igr_filter = RTL839X_VLAN_PORT_IGR_FLTR(0),
-	.vlan_port_pb = RTL839X_VLAN_PORT_PB_VLAN,
-	.vlan_port_tag_sts_ctrl = RTL839X_VLAN_PORT_TAG_STS_CTRL,
-	.trk_mbr_ctr = rtl839x_trk_mbr_ctr,
-	.rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK,
-	.spcl_trap_eapol_ctrl = RTL839X_SPCL_TRAP_EAPOL_CTRL,
-	.init_eee = rtl839x_init_eee,
-	.port_eee_set = rtl839x_port_eee_set,
-	.eee_port_ability = rtl839x_eee_port_ability,
-	.l2_hash_seed = rtl839x_l2_hash_seed, 
-	.l2_hash_key = rtl839x_l2_hash_key,
-	.read_mcast_pmask = rtl839x_read_mcast_pmask,
-	.write_mcast_pmask = rtl839x_write_mcast_pmask,
-};
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl83xx.h b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl83xx.h
deleted file mode 100644
index fd0455a6cd..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl83xx.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _NET_DSA_RTL83XX_H
-#define _NET_DSA_RTL83XX_H
-
-#include <net/dsa.h>
-#include "rtl838x.h"
-
-
-#define RTL8380_VERSION_A 'A'
-#define RTL8390_VERSION_A 'A'
-#define RTL8380_VERSION_B 'B'
-
-struct fdb_update_work {
-	struct work_struct work;
-	struct net_device *ndev;
-	u64 macs[];
-};
-
-#define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
-struct rtl83xx_mib_desc {
-	unsigned int size;
-	unsigned int offset;
-	const char *name;
-};
-
-/* API for switch table access */
-struct table_reg {
-	u16 addr;
-	u16 data;
-	u8  max_data;
-	u8 c_bit;
-	u8 t_bit;
-	u8 rmode;
-	u8 tbl;
-	struct mutex lock;
-};
-
-#define TBL_DESC(_addr, _data, _max_data, _c_bit, _t_bit, _rmode) \
-		{  .addr = _addr, .data = _data, .max_data = _max_data, .c_bit = _c_bit, \
-		    .t_bit = _t_bit, .rmode = _rmode \
-		}
-
-typedef enum {
-	RTL8380_TBL_L2 = 0,
-	RTL8380_TBL_0,
-	RTL8380_TBL_1,
-	RTL8390_TBL_L2,
-	RTL8390_TBL_0,
-	RTL8390_TBL_1,
-	RTL8390_TBL_2,
-	RTL9300_TBL_L2,
-	RTL9300_TBL_0,
-	RTL9300_TBL_1,
-	RTL9300_TBL_2,
-	RTL9300_TBL_HSB,
-	RTL9300_TBL_HSA,
-	RTL9310_TBL_0,
-	RTL9310_TBL_1,
-	RTL9310_TBL_2,
-	RTL9310_TBL_3,
-	RTL9310_TBL_4,
-	RTL9310_TBL_5,
-	RTL_TBL_END
-} rtl838x_tbl_reg_t;
-
-void rtl_table_init(void);
-struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t);
-void rtl_table_release(struct table_reg *r);
-void rtl_table_read(struct table_reg *r, int idx);
-void rtl_table_write(struct table_reg *r, int idx);
-inline u16 rtl_table_data(struct table_reg *r, int i);
-inline u32 rtl_table_data_r(struct table_reg *r, int i);
-inline void rtl_table_data_w(struct table_reg *r, u32 v, int i);
-
-void __init rtl83xx_setup_qos(struct rtl838x_switch_priv *priv);
-int read_phy(u32 port, u32 page, u32 reg, u32 *val);
-int write_phy(u32 port, u32 page, u32 reg, u32 val);
-
-/* Port register accessor functions for the RTL839x and RTL931X SoCs */
-void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg);
-u64 rtl839x_get_port_reg_be(int reg);
-void rtl839x_set_port_reg_be(u64 set, int reg);
-void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg);
-void rtl839x_set_port_reg_le(u64 set, int reg);
-u64 rtl839x_get_port_reg_le(int reg);
-
-/* Port register accessor functions for the RTL838x and RTL930X SoCs */
-void rtl838x_mask_port_reg(u64 clear, u64 set, int reg);
-void rtl838x_set_port_reg(u64 set, int reg);
-u64 rtl838x_get_port_reg(int reg);
-
-/* RTL838x-specific */
-u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed);
-irqreturn_t rtl838x_switch_irq(int irq, void *dev_id);
-void rtl8380_get_version(struct rtl838x_switch_priv *priv);
-void rtl838x_vlan_profile_dump(int index);
-int rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg);
-void rtl8380_sds_rst(int mac);
-int rtl8380_sds_power(int mac, int val);
-void rtl838x_print_matrix(void);
-
-/* RTL839x-specific */
-u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed);
-irqreturn_t rtl839x_switch_irq(int irq, void *dev_id);
-void rtl8390_get_version(struct rtl838x_switch_priv *priv);
-void rtl839x_vlan_profile_dump(int index);
-int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val);
-void rtl839x_exec_tbl2_cmd(u32 cmd);
-void rtl839x_print_matrix(void);
-
-/* RTL930x-specific */
-u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed);
-irqreturn_t rtl930x_switch_irq(int irq, void *dev_id);
-irqreturn_t rtl839x_switch_irq(int irq, void *dev_id);
-void rtl930x_vlan_profile_dump(int index);
-int rtl9300_sds_power(int mac, int val);
-void rtl9300_sds_rst(int sds_num, u32 mode);
-void rtl930x_print_matrix(void);
-
-/* RTL931x-specific */
-irqreturn_t rtl931x_switch_irq(int irq, void *dev_id);
-
-#endif /* _NET_DSA_RTL83XX_H */
-
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl930x.c
deleted file mode 100644
index f1de39f0bc..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl930x.c
+++ /dev/null
@@ -1,1039 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <asm/mach-rtl838x/mach-rtl83xx.h>
-#include "rtl83xx.h"
-
-extern struct mutex smi_lock;
-extern struct rtl83xx_soc_info soc_info;
-
-void rtl930x_print_matrix(void)
-{
-	int i;
-	struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
-
-	for (i = 0; i < 29; i++) {
-		rtl_table_read(r, i);
-		pr_debug("> %08x\n", sw_r32(rtl_table_data(r, 0)));
-	}
-	rtl_table_release(r);
-}
-
-inline void rtl930x_exec_tbl0_cmd(u32 cmd)
-{
-	sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_0);
-	do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_0) & (1 << 17));
-}
-
-inline void rtl930x_exec_tbl1_cmd(u32 cmd)
-{
-	sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_1);
-	do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_1) & (1 << 17));
-}
-
-inline int rtl930x_tbl_access_data_0(int i)
-{
-	return RTL930X_TBL_ACCESS_DATA_0(i);
-}
-
-static inline int rtl930x_l2_port_new_salrn(int p)
-{
-	return RTL930X_L2_PORT_SALRN(p);
-}
-
-static inline int rtl930x_l2_port_new_sa_fwd(int p)
-{
-	// TODO: The definition of the fields changed, because of the master-cpu in a stack
-	return RTL930X_L2_PORT_NEW_SA_FWD(p);
-}
-
-inline static int rtl930x_trk_mbr_ctr(int group)
-{
-	return RTL930X_TRK_MBR_CTRL + (group << 2);
-}
-
-static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
-{
-	u32 v, w;
-	// Read VLAN table (1) via register 0
-	struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
-
-	rtl_table_read(r, vlan);
-	v = sw_r32(rtl_table_data(r, 0));
-	w = sw_r32(rtl_table_data(r, 1));
-	pr_debug("VLAN_READ %d: %08x %08x\n", vlan, v, w);
-	rtl_table_release(r);
-
-	info->tagged_ports = v >> 3;
-	info->profile_id = (w >> 24) & 7;
-	info->hash_mc_fid = !!(w & BIT(27));
-	info->hash_uc_fid = !!(w & BIT(28));
-	info->fid = ((v & 0x7) << 3) | ((w >> 29) & 0x7);
-
-	// Read UNTAG table via table register 2
-	r = rtl_table_get(RTL9300_TBL_2, 0);
-	rtl_table_read(r, vlan);
-	v = sw_r32(rtl_table_data(r, 0));
-	rtl_table_release(r);
-
-	info->untagged_ports = v >> 3;
-}
-
-static void rtl930x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
-{
-	u32 v, w;
-	// Access VLAN table (1) via register 0
-	struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
-
-	v = info->tagged_ports << 3;
-	v |= ((u32)info->fid) >> 3;
-
-	w = ((u32)info->fid) << 29;
-	w |= info->hash_mc_fid ? BIT(27) : 0;
-	w |= info->hash_uc_fid ? BIT(28) : 0;
-	w |= info->profile_id << 24;
-
-	sw_w32(v, rtl_table_data(r, 0));
-	sw_w32(w, rtl_table_data(r, 1));
-
-	rtl_table_write(r, vlan);
-	rtl_table_release(r);
-}
-
-void rtl930x_vlan_profile_dump(int profile)
-{
-	u32 p[5];
-
-	if (profile < 0 || profile > 7)
-		return;
-
-	p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
-	p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
-	p[2] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 8) & 0x1FFFFFFF;
-	p[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 12) & 0x1FFFFFFF;
-	p[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 16) & 0x1FFFFFFF;
-
-	pr_info("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x",
-		profile, p[0] & (3 << 21), p[2], p[3], p[4]);
-	pr_info("  Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n",
-		p[0] & BIT(17) ? 'y' : 'n', p[0] & BIT(16) ? 'y' : 'n',
-		p[0] & BIT(13) ? 'y' : 'n', p[0] & BIT(12) ? 'y' : 'n');
-	pr_info("  Bridge enabled: IPv4 MC %c, IPv6 MC %c,\n",
-		p[0] & BIT(15) ? 'y' : 'n', p[0] & BIT(14) ? 'y' : 'n');
-	pr_info("VLAN profile %d: raw %08x %08x %08x %08x %08x\n",
-		profile, p[0], p[1], p[2], p[3], p[4]);
-}
-
-static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask)
-{
-	struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 0);
-
-	sw_w32(portmask << 3, rtl_table_data(r, 0));
-	rtl_table_write(r, vlan);
-	rtl_table_release(r);
-}
-
-/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
- */
-static void rtl930x_vlan_fwd_on_inner(int port, bool is_set)
-{
-	// Always set all tag modes to fwd based on either inner or outer tag
-	if (is_set)
-		sw_w32_mask(0, 0xf, RTL930X_VLAN_PORT_FWD + (port << 2));
-	else
-		sw_w32_mask(0xf, 0, RTL930X_VLAN_PORT_FWD + (port << 2));
-}
-
-static void rtl930x_vlan_profile_setup(int profile)
-{
-	u32 p[5];
-
-	pr_info("In %s\n", __func__);
-	p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
-	p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
-
-	// Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic
-	p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12);
-	p[2] = 0x1fffffff; // L2 unknown MC flooding portmask all ports, including the CPU-port
-	p[3] = 0x1fffffff; // IPv4 unknown MC flooding portmask
-	p[4] = 0x1fffffff; // IPv6 unknown MC flooding portmask
-
-	sw_w32(p[0], RTL930X_VLAN_PROFILE_SET(profile));
-	sw_w32(p[1], RTL930X_VLAN_PROFILE_SET(profile) + 4);
-	sw_w32(p[2], RTL930X_VLAN_PROFILE_SET(profile) + 8);
-	sw_w32(p[3], RTL930X_VLAN_PROFILE_SET(profile) + 12);
-	sw_w32(p[4], RTL930X_VLAN_PROFILE_SET(profile) + 16);
-	pr_info("Leaving %s\n", __func__);
-}
-
-static void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
-{
-	int i;
-	u32 cmd = 1 << 17 /* Execute cmd */
-		| 0 << 16 /* Read */
-		| 4 << 12 /* Table type 0b10 */
-		| (msti & 0xfff);
-	priv->r->exec_tbl0_cmd(cmd);
-
-	for (i = 0; i < 2; i++)
-		port_state[i] = sw_r32(RTL930X_TBL_ACCESS_DATA_0(i));
-	pr_debug("MSTI: %d STATE: %08x, %08x\n", msti, port_state[0], port_state[1]);
-}
-
-static void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
-{
-	int i;
-	u32 cmd = 1 << 17 /* Execute cmd */
-		| 1 << 16 /* Write */
-		| 4 << 12 /* Table type 4 */
-		| (msti & 0xfff);
-
-	for (i = 0; i < 2; i++)
-		sw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i));
-	priv->r->exec_tbl0_cmd(cmd);
-}
-
-static inline int rtl930x_mac_force_mode_ctrl(int p)
-{
-	return RTL930X_MAC_FORCE_MODE_CTRL + (p << 2);
-}
-
-static inline int rtl930x_mac_port_ctrl(int p)
-{
-	return RTL930X_MAC_L2_PORT_CTRL(p);
-}
-
-static inline int rtl930x_mac_link_spd_sts(int p)
-{
-	return RTL930X_MAC_LINK_SPD_STS(p);
-}
-
-static u64 rtl930x_l2_hash_seed(u64 mac, u32 vid)
-{
-	u64 v = vid;
-
-	v <<= 48;
-	v |= mac;
-
-	return v;
-}
-
-/*
- * Calculate both the block 0 and the block 1 hash by applyingthe same hash
- * algorithm as the one used currently by the ASIC to the seed, and return
- * both hashes in the lower and higher word of the return value since only 12 bit of
- * the hash are significant
- */
-static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
-{
-	u32 k0, k1, h1, h2, h;
-
-	k0 = (u32) (((seed >> 55) & 0x1f) ^ ((seed >> 44) & 0x7ff)
-		^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
-		^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff));
-
-	h1 = (seed >> 11) & 0x7ff;
-	h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
-
-	h2 = (seed >> 33) & 0x7ff;
-	h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);
-
-	k1 = (u32) (((seed << 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) ^ h2
-		    ^ ((seed >> 22) & 0x7ff) ^ h1
-		    ^ (seed & 0x7ff));
-
-	// Algorithm choice for block 0
-	if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
-		h = k1;
-	else
-		h = k0;
-
-	/* Algorithm choice for block 1
-	 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
-	 * half of hash-space
-	 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
-	 * divided by 2 to divide the hash space in 2
-	 */
-	if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
-		h |= (k1 + 2048) << 16;
-	else
-		h |= (k0 + 2048) << 16;
-
-	return h;
-}
-
-/*
- * Fills an L2 entry structure from the SoC registers
- */
-static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
-{
-	pr_debug("In %s valid?\n", __func__);
-	e->valid = !!(r[2] & BIT(31));
-	if (!e->valid)
-		return;
-
-	pr_debug("In %s is valid\n", __func__);
-	e->is_ip_mc = false;
-	e->is_ipv6_mc = false;
-
-	// TODO: Is there not a function to copy directly MAC memory?
-	e->mac[0] = (r[0] >> 24);
-	e->mac[1] = (r[0] >> 16);
-	e->mac[2] = (r[0] >> 8);
-	e->mac[3] = r[0];
-	e->mac[4] = (r[1] >> 24);
-	e->mac[5] = (r[1] >> 16);
-
-	e->next_hop = !!(r[2] & BIT(12));
-	e->rvid = r[1] & 0xfff;
-
-	/* Is it a unicast entry? check multicast bit */
-	if (!(e->mac[0] & 1)) {
-		e->type = L2_UNICAST;
-		e->is_static = !!(r[2] & BIT(14));
-		e->port = (r[2] >> 20) & 0x3ff;
-		// Check for trunk port
-		if (r[2] & BIT(30)) {
-			e->is_trunk = true;
-			e->stack_dev = (e->port >> 9) & 1;
-			e->trunk = e->port & 0x3f;
-		} else {
-			e->is_trunk = false;
-			e->stack_dev = (e->port >> 6) & 0xf;
-			e->port = e->port & 0x3f;
-		}
-
-		e->block_da = !!(r[2] & BIT(15));
-		e->block_sa = !!(r[2] & BIT(16));
-		e->suspended = !!(r[2] & BIT(13));
-		e->age = (r[2] >> 17) & 3;
-		e->valid = true;
-		// the UC_VID field in hardware is used for the VID or for the route id
-		if (e->next_hop) {
-			e->nh_route_id = r[2] & 0xfff;
-			e->vid = 0;
-		} else {
-			e->vid = r[2] & 0xfff;
-			e->nh_route_id = 0;
-		}
-	} else {
-		e->valid = true;
-		e->type = L2_MULTICAST;
-		e->mc_portmask_index = (r[2] >> 16) & 0x3ff;
-	}
-}
-
-/*
- * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry
- */
-static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
-{
-	u32 port;
-
-	if (!e->valid) {
-		r[0] = r[1] = r[2] = 0;
-		return;
-	}
-
-	r[2] = BIT(31);	// Set valid bit
-
-	r[0] = ((u32)e->mac[0]) << 24 | ((u32)e->mac[1]) << 16 
-		| ((u32)e->mac[2]) << 8 | ((u32)e->mac[3]);
-	r[1] = ((u32)e->mac[4]) << 24 | ((u32)e->mac[5]) << 16;
-
-	r[2] |= e->next_hop ? BIT(12) : 0;
-
-	if (e->type == L2_UNICAST) {
-		r[2] |= e->is_static ? BIT(14) : 0;
-		r[1] |= e->rvid & 0xfff;
-		r[2] |= (e->port & 0x3ff) << 20;
-		if (e->is_trunk) {
-			r[2] |= BIT(30);
-			port = e->stack_dev << 9 | (e->port & 0x3f);
-		} else {
-			port = (e->stack_dev & 0xf) << 6;
-			port |= e->port & 0x3f;
-		}
-		r[2] |= port << 20;
-		r[2] |= e->block_da ? BIT(15) : 0;
-		r[2] |= e->block_sa ? BIT(17) : 0;
-		r[2] |= e->suspended ? BIT(13) : 0;
-		r[2] |= (e->age & 0x3) << 17;
-		// the UC_VID field in hardware is used for the VID or for the route id
-		if (e->next_hop)
-			r[2] |= e->nh_route_id & 0xfff;
-		else
-			r[2] |= e->vid & 0xfff;
-	} else { // L2_MULTICAST
-		r[2] |= (e->mc_portmask_index & 0x3ff) << 16;
-		r[2] |= e->mc_mac_index & 0x7ff;
-	}
-}
-
-/*
- * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
- * hash is the id of the bucket and pos is the position of the entry in that bucket
- * The data read from the SoC is filled into rtl838x_l2_entry
- */
-static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
-{
-	u32 r[3];
-	struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
-	u32 idx;
-	int i;
-	u64 mac;
-	u64 seed;
-
-	pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos);
-
-	/* On the RTL93xx, 2 different hash algorithms are used making it a total of
-	 * 8 buckets that need to be searched, 4 for each hash-half
-	 * Use second hash space when bucket is between 4 and 8 */
-	if (pos >= 4) {
-		pos -= 4;
-		hash >>= 16;
-	} else {
-		hash &= 0xffff;
-	}
-
-	idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket
-	pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos);
-
-	rtl_table_read(q, idx);
-	for (i = 0; i < 3; i++)
-		r[i] = sw_r32(rtl_table_data(q, i));
-
-	rtl_table_release(q);
-
-	rtl930x_fill_l2_entry(r, e);
-
-	pr_debug("%s: valid: %d, nh: %d\n", __func__, e->valid, e->next_hop);
-	if (!e->valid)
-		return 0;
-
-	mac = ((u64)e->mac[0]) << 40 | ((u64)e->mac[1]) << 32 | ((u64)e->mac[2]) << 24
-		| ((u64)e->mac[3]) << 16 | ((u64)e->mac[4]) << 8 | ((u64)e->mac[5]);
-
-	seed = rtl930x_l2_hash_seed(mac, e->rvid);
-	pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed);
-	// return vid with concatenated mac as unique id
-	return seed;
-}
-
-static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
-{
-	u32 r[3];
-	struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
-	u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket
-	int i;
-
-	pr_info("%s: hash %d, pos %d\n", __func__, hash, pos);
-	pr_info("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
-		e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);
-
-	rtl930x_fill_l2_row(r, e);
-
-	for (i= 0; i < 3; i++)
-		sw_w32(r[i], rtl_table_data(q, i));
-
-	rtl_table_write(q, idx);
-	rtl_table_release(q);
-}
-
-static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e)
-{
-	u32 r[3];
-	struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1);
-	int i;
-
-	rtl_table_read(q, idx);
-	for (i= 0; i < 3; i++)
-		r[i] = sw_r32(rtl_table_data(q, i));
-
-	rtl_table_release(q);
-
-	rtl930x_fill_l2_entry(r, e);
-	if (!e->valid)
-		return 0;
-
-	// return mac with concatenated vid as unique id
-	return ((u64)r[0] << 28) | ((r[1] & 0xffff0000) >> 4) | e->vid;
-}
-
-static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e)
-{
-	u32 r[3];
-	struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); // Access L2 Table 1
-	int i;
-
-	rtl930x_fill_l2_row(r, e);
-
-	for (i= 0; i < 3; i++)
-		sw_w32(r[i], rtl_table_data(q, i));
-
-	rtl_table_write(q, idx);
-	rtl_table_release(q);
-}
-
-static void dump_l2_entry(struct rtl838x_l2_entry *e)
-{
-	pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
-		e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
-		e->vid, e->rvid, e->port, e->valid);
-	pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
-		e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
-	pr_info("  block_sa: %d, suspended: %d, next_hop: %d, age: %d, is_trunk: %d, trunk: %d\n",
-		e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
-	if (e->is_ip_mc || e->is_ipv6_mc)
-		pr_info("  mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
-			e->mc_portmask_index, e->mc_gip, e->mc_sip);
-	pr_info("  stac_dev: %d, nh_route_id: %d, port: %d, dev_id\n",
-		e->stack_dev, e->nh_route_id, e->port);
-}
-
-/*
- * Add an L2 nexthop entry for the L3 routing system in the SoC
- * Use VID and MAC in rtl838x_l2_entry to identify either a free slot in the L2 hash table
- * or mark an existing entry as a nexthop by setting it's nexthop bit
- * Called from the L3 layer
- * The index in the L2 hash table is filled into nh->l2_id;
- */
-static int rtl930x_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl838x_nexthop *nh)
-{
-	struct rtl838x_l2_entry e;
-	u64 seed = rtl930x_l2_hash_seed(nh->mac, nh->vid);
-	u32 key = rtl930x_l2_hash_key(priv, seed);
-	int i, idx = -1;
-	u64 entry;
-
-	pr_info("%s searching for %08llx vid %d with key %d, seed: %016llx\n",
-		__func__, nh->mac, nh->vid, key, seed);
-	
-	e.type = L2_UNICAST;
-	e.rvid = nh->fid; // Verify its the forwarding ID!!! l2_entry.un.unicast.fid
-	u64_to_ether_addr(nh->mac, &e.mac[0]);
-	e.port = RTL930X_PORT_IGNORE;
-
-	// Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
-	for (i = 0; i < priv->l2_bucket_size; i++) {
-		entry = rtl930x_read_l2_entry_using_hash(key, i, &e);
-		pr_info("%s i: %d, entry %016llx, seed %016llx\n", __func__, i, entry, seed);
-		if (e.valid && e.next_hop)
-			continue;
-		if (!e.valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
-			idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1
-					: ((key << 2) | i) & 0xffff;
-			break;
-		}
-	}
-
-	pr_info("%s: found idx %d and i %d\n", __func__, idx, i);
-
-	if (idx < 0) {
-		pr_err("%s: No more L2 forwarding entries available\n", __func__);
-		return -1;
-	}
-
-	// Found an existing or empty entry, make it a nexthop entry
-	pr_info("%s BEFORE -> key %d, pos: %d, index: %d\n", __func__, key, i, idx);
-	dump_l2_entry(&e);
-	nh->l2_id = idx;
-
-	// Found an existing (e->valid is true) or empty entry, make it a nexthop entry
-	if (e.valid) {
-		nh->port = e.port;
-		nh->fid = e.rvid;
-		nh->vid = e.vid;
-		nh->dev_id = e.stack_dev;
-	} else {
-		e.valid = true;
-		e.is_static = false;
-		e.vid = nh->vid;
-		e.rvid = nh->fid;
-		e.port = RTL930X_PORT_IGNORE;
-		u64_to_ether_addr(nh->mac, &e.mac[0]);
-	}
-	e.next_hop = true;
-	// For nexthop entries, the vid field in the table is used to denote the dest mac_id
-	e.nh_route_id = nh->mac_id;
-	pr_info("%s AFTER\n", __func__);
-	dump_l2_entry(&e);
-
-	rtl930x_write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
-
-	// _dal_longan_l2_nexthop_add
-	return 0;
-}
-
-static u64 rtl930x_read_mcast_pmask(int idx)
-{
-	u32 portmask;
-	// Read MC_PORTMASK (2) via register RTL9300_TBL_L2
-	struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
-
-	rtl_table_read(q, idx);
-	portmask = sw_r32(rtl_table_data(q, 0));
-	portmask >>= 3;
-	rtl_table_release(q);
-
-	pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, portmask);
-	return portmask;
-}
-
-static void rtl930x_write_mcast_pmask(int idx, u64 portmask)
-{
-	u32 pm = portmask;
-
-	// Access MC_PORTMASK (2) via register RTL9300_TBL_L2
-	struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
-
-	pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, pm);
-	pm <<= 3;
-	sw_w32(pm, rtl_table_data(q, 0));
-	rtl_table_write(q, idx);
-	rtl_table_release(q);
-}
-
-u64 rtl930x_traffic_get(int source)
-{
-	u32 v;
-	struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
-
-	rtl_table_read(r, source);
-	v = sw_r32(rtl_table_data(r, 0));
-	rtl_table_release(r);
-	return v >> 3;
-}
-
-/*
- * Enable traffic between a source port and a destination port matrix
- */
-void rtl930x_traffic_set(int source, u64 dest_matrix)
-{
-	struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
-
-	sw_w32((dest_matrix << 3), rtl_table_data(r, 0));
-	rtl_table_write(r, source);
-	rtl_table_release(r);
-}
-
-void rtl930x_traffic_enable(int source, int dest)
-{
-	struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
-	rtl_table_read(r, source);
-	sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0));
-	rtl_table_write(r, source);
-	rtl_table_release(r);
-}
-
-void rtl930x_traffic_disable(int source, int dest)
-{
-	struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
-	rtl_table_read(r, source);
-	sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0));
-	rtl_table_write(r, source);
-	rtl_table_release(r);
-}
-
-void rtl9300_dump_debug(void)
-{
-	int i;
-	u16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0;
-
-	for (i = 0; i < 10; i ++) {
-		pr_info("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8,
-			sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12),
-			sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28));
-		r += 32;
-	}
-	pr_info("# %08x %08x %08x %08x %08x\n",
-		sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16));
-	rtl930x_print_matrix();
-	pr_info("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n",
-		sw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL)
-
-	);
-}
-
-irqreturn_t rtl930x_switch_irq(int irq, void *dev_id)
-{
-	struct dsa_switch *ds = dev_id;
-	u32 status = sw_r32(RTL930X_ISR_GLB);
-	u32 ports = sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG);
-	u32 link;
-	int i;
-
-	/* Clear status */
-	sw_w32(ports, RTL930X_ISR_PORT_LINK_STS_CHG);
-	pr_info("RTL9300 Link change: status: %x, ports %x\n", status, ports);
-
-	rtl9300_dump_debug();
-
-	for (i = 0; i < 28; i++) {
-		if (ports & BIT(i)) {
-			/* Read the register twice because of issues with latency at least
-			 * with the external RTL8226 PHY on the XGS1210 */
-			link = sw_r32(RTL930X_MAC_LINK_STS);
-			link = sw_r32(RTL930X_MAC_LINK_STS);
-			if (link & BIT(i))
-				dsa_port_phylink_mac_change(ds, i, true);
-			else
-				dsa_port_phylink_mac_change(ds, i, false);
-		}
-	}
-
-	return IRQ_HANDLED;
-}
-
-int rtl9300_sds_power(int mac, int val)
-{
-	int sds_num;
-	u32 mode;
-
-	// TODO: these numbers are hard-coded for the Zyxel XGS1210 12 Switch
-	pr_info("SerDes: %s %d\n", __func__, mac);
-	switch (mac) {
-	case 24:
-		sds_num = 6;
-		mode = 0x12; // HISGMII
-		break;
-	case 25:
-		sds_num = 7;
-		mode = 0x12; // HISGMII
-		break;
-	case 26:
-		sds_num = 8;
-		mode = 0x1b; // 10GR/1000BX auto
-		break;
-	case 27:
-		sds_num = 9;
-		mode = 0x1b; // 10GR/1000BX auto
-		break;
-	default:
-		return -1;
-	}
-	if (!val)
-		mode = 0x1f; // OFF
-
-	rtl9300_sds_rst(sds_num, mode);
-
-	return 0;
-}
-
-int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val)
-{
-	u32 v;
-	int err = 0;
-
-	pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, val);
-
-	if (port > 63 || page > 4095 || reg > 31)
-		return -ENOTSUPP;
-
-	val &= 0xffff;
-	mutex_lock(&smi_lock);
-
-	sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
-	sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
-	v = reg << 20 | page << 3 | 0x1f << 15 | BIT(2) | BIT(0);
-	sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
-
-	do {
-		v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
-	} while (v & 0x1);
-
-	if (v & 0x2)
-		err = -EIO;
-
-	mutex_unlock(&smi_lock);
-
-	return err;
-}
-
-int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
-{
-	u32 v;
-	int err = 0;
-
-	if (port > 63 || page > 4095 || reg > 31)
-		return -ENOTSUPP;
-
-	mutex_lock(&smi_lock);
-
-	sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
-	v = reg << 20 | page << 3 | 0x1f << 15 | 1;
-	sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
-
-	do {
-		v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
-	} while ( v & 0x1);
-
-	if (v & BIT(25)) {
-		pr_debug("Error reading phy %d, register %d\n", port, reg);
-		err = -EIO;
-	}
-	*val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
-
-	pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, *val);
-
-	mutex_unlock(&smi_lock);
-
-	return err;
-}
-
-/*
- * Write to an mmd register of the PHY
- */
-int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
-{
-	int err = 0;
-	u32 v;
-
-	mutex_lock(&smi_lock);
-
-	// Set PHY to access
-	sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
-
-	// Set data to write
-	sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
-
-	// Set MMD device number and register to write to
-	sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
-
-	v = BIT(2) | BIT(1) | BIT(0); // WRITE | MMD-access | EXEC
-	sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
-
-	do {
-		v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
-	} while (v & BIT(0));
-
-	pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
-	mutex_unlock(&smi_lock);
-	return err;
-}
-
-/*
- * Read an mmd register of the PHY
- */
-int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
-{
-	int err = 0;
-	u32 v;
-
-	mutex_lock(&smi_lock);
-
-	// Set PHY to access
-	sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
-
-	// Set MMD device number and register to write to
-	sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
-
-	v = BIT(1) | BIT(0); // MMD-access | EXEC
-	sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
-
-	do {
-		v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
-	} while (v & BIT(0));
-	// There is no error-checking via BIT 25 of v, as it does not seem to be set correctly
-	*val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
-	pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
-
-	mutex_unlock(&smi_lock);
-
-	return err;
-}
-
-/*
- * Calculate both the block 0 and the block 1 hash, and return in
- * lower and higher word of the return value since only 12 bit of
- * the hash are significant
- */
-u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed)
-{
-	u32 k0, k1, h1, h2, h;
-
-	k0 = (u32) (((seed >> 55) & 0x1f) ^ ((seed >> 44) & 0x7ff)
-		^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
-		^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff));
-
-	h1 = (seed >> 11) & 0x7ff;
-	h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
-
-	h2 = (seed >> 33) & 0x7ff;
-	h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);
-
-	k1 = (u32) (((seed << 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) ^ h2
-		    ^ ((seed >> 22) & 0x7ff) ^ h1
-		    ^ (seed & 0x7ff));
-
-	// Algorithm choice for block 0
-	if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
-		h = k1;
-	else
-		h = k0;
-
-	/* Algorithm choice for block 1
-	 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
-	 * half of hash-space
-	 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
-	 * divided by 2 to divide the hash space in 2
-	 */
-	if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
-		h |= (k1 + 2048) << 16;
-	else
-		h |= (k0 + 2048) << 16;
-
-	return h;
-}
-
-/*
- * Enables or disables the EEE/EEEP capability of a port
- */
-void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
-{
-	u32 v;
-
-	// This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP
-	if (port >= 26)
-		return;
-
-	pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
-	v = enable ? 0x3f : 0x0;
-
-	// Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit
-	sw_w32_mask(0, v << 10, rtl930x_mac_force_mode_ctrl(port));
-
-	// Set TX/RX EEE state
-	v = enable ? 0x3 : 0x0;
-	sw_w32(v, RTL930X_EEE_CTRL(port));
-
-	priv->ports[port].eee_enabled = enable;
-}
-
-/*
- * Get EEE own capabilities and negotiation result
- */
-int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
-{
-	u32 link, a;
-
-	if (port >= 26)
-		return -ENOTSUPP;
-
-	pr_info("In %s, port %d\n", __func__, port);
-	link = sw_r32(RTL930X_MAC_LINK_STS);
-	link = sw_r32(RTL930X_MAC_LINK_STS);
-	if (!(link & BIT(port)))
-		return 0;
-
-	pr_info("Setting advertised\n");
-	if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(10))
-		e->advertised |= ADVERTISED_100baseT_Full;
-
-	if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(12))
-		e->advertised |= ADVERTISED_1000baseT_Full;
-
-	if (priv->ports[port].is2G5 && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(13)) {
-		pr_info("ADVERTISING 2.5G EEE\n");
-		e->advertised |= ADVERTISED_2500baseX_Full;
-	}
-
-	if (priv->ports[port].is10G && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(15))
-		e->advertised |= ADVERTISED_10000baseT_Full;
-
-	a = sw_r32(RTL930X_MAC_EEE_ABLTY);
-	a = sw_r32(RTL930X_MAC_EEE_ABLTY);
-	pr_info("Link partner: %08x\n", a);
-	if (a & BIT(port)) {
-		e->lp_advertised = ADVERTISED_100baseT_Full;
-		e->lp_advertised |= ADVERTISED_1000baseT_Full;
-		if (priv->ports[port].is2G5)
-			e->lp_advertised |= ADVERTISED_2500baseX_Full;
-		if (priv->ports[port].is10G)
-			e->lp_advertised |= ADVERTISED_10000baseT_Full;
-	}
-
-	// Read 2x to clear latched state
-	a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
-	a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
-	pr_info("%s RTL930X_EEEP_PORT_CTRL: %08x\n", __func__, a);
-
-	return 0;
-}
-
-static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
-{
-	int i;
-
-	pr_info("Setting up EEE, state: %d\n", enable);
-
-	// Setup EEE on all ports
-	for (i = 0; i < priv->cpu_port; i++) {
-		if (priv->ports[i].phy)
-			rtl930x_port_eee_set(priv, i, enable);
-	}
-
-	priv->eee_enabled = enable;
-}
-
-const struct rtl838x_reg rtl930x_reg = {
-	.mask_port_reg_be = rtl838x_mask_port_reg,
-	.set_port_reg_be = rtl838x_set_port_reg,
-	.get_port_reg_be = rtl838x_get_port_reg,
-	.mask_port_reg_le = rtl838x_mask_port_reg,
-	.set_port_reg_le = rtl838x_set_port_reg,
-	.get_port_reg_le = rtl838x_get_port_reg,
-	.stat_port_rst = RTL930X_STAT_PORT_RST,
-	.stat_rst = RTL930X_STAT_RST,
-	.stat_port_std_mib = RTL930X_STAT_PORT_MIB_CNTR,
-	.traffic_enable = rtl930x_traffic_enable,
-	.traffic_disable = rtl930x_traffic_disable,
-	.traffic_get = rtl930x_traffic_get,
-	.traffic_set = rtl930x_traffic_set,
-	.l2_ctrl_0 = RTL930X_L2_CTRL,
-	.l2_ctrl_1 = RTL930X_L2_AGE_CTRL,
-	.l2_port_aging_out = RTL930X_L2_PORT_AGE_CTRL,
-	.smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, // TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL
-	.l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
-	.exec_tbl0_cmd = rtl930x_exec_tbl0_cmd,
-	.exec_tbl1_cmd = rtl930x_exec_tbl1_cmd,
-	.tbl_access_data_0 = rtl930x_tbl_access_data_0,
-	.isr_glb_src = RTL930X_ISR_GLB,
-	.isr_port_link_sts_chg = RTL930X_ISR_PORT_LINK_STS_CHG,
-	.imr_port_link_sts_chg = RTL930X_IMR_PORT_LINK_STS_CHG,
-	.imr_glb = RTL930X_IMR_GLB,
-	.vlan_tables_read = rtl930x_vlan_tables_read,
-	.vlan_set_tagged = rtl930x_vlan_set_tagged,
-	.vlan_set_untagged = rtl930x_vlan_set_untagged,
-	.vlan_profile_dump = rtl930x_vlan_profile_dump,
-	.vlan_profile_setup = rtl930x_vlan_profile_setup,
-	.vlan_fwd_on_inner = rtl930x_vlan_fwd_on_inner,
-	.stp_get = rtl930x_stp_get,
-	.stp_set = rtl930x_stp_set,
-	.mac_force_mode_ctrl = rtl930x_mac_force_mode_ctrl,
-	.mac_port_ctrl = rtl930x_mac_port_ctrl,
-	.l2_port_new_salrn = rtl930x_l2_port_new_salrn,
-	.l2_port_new_sa_fwd = rtl930x_l2_port_new_sa_fwd,
-	.mir_ctrl = RTL930X_MIR_CTRL,
-	.mir_dpm = RTL930X_MIR_DPM_CTRL,
-	.mir_spm = RTL930X_MIR_SPM_CTRL,
-	.mac_link_sts = RTL930X_MAC_LINK_STS,
-	.mac_link_dup_sts = RTL930X_MAC_LINK_DUP_STS,
-	.mac_link_spd_sts = rtl930x_mac_link_spd_sts,
-	.mac_rx_pause_sts = RTL930X_MAC_RX_PAUSE_STS,
-	.mac_tx_pause_sts = RTL930X_MAC_TX_PAUSE_STS,
-	.read_l2_entry_using_hash = rtl930x_read_l2_entry_using_hash,
-	.write_l2_entry_using_hash = rtl930x_write_l2_entry_using_hash,
-	.read_cam = rtl930x_read_cam,
-	.write_cam = rtl930x_write_cam,
-	.vlan_port_egr_filter = RTL930X_VLAN_PORT_EGR_FLTR,
-	.vlan_port_igr_filter = RTL930X_VLAN_PORT_IGR_FLTR(0),
-	.vlan_port_pb = RTL930X_VLAN_PORT_PB_VLAN,
-	.vlan_port_tag_sts_ctrl = RTL930X_VLAN_PORT_TAG_STS_CTRL,
-	.trk_mbr_ctr = rtl930x_trk_mbr_ctr,
-	.rma_bpdu_fld_pmask = RTL930X_RMA_BPDU_FLD_PMSK,
-	.init_eee = rtl930x_init_eee,
-	.port_eee_set = rtl930x_port_eee_set,
-	.eee_port_ability = rtl930x_eee_port_ability,
-	.read_mcast_pmask = rtl930x_read_mcast_pmask,
-	.write_mcast_pmask = rtl930x_write_mcast_pmask,
-};
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl931x.c
deleted file mode 100644
index f98bf7df29..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl931x.c
+++ /dev/null
@@ -1,393 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-#include <asm/mach-rtl838x/mach-rtl83xx.h>
-#include "rtl83xx.h"
-
-extern struct mutex smi_lock;
-extern struct rtl83xx_soc_info soc_info;
-
-inline void rtl931x_exec_tbl0_cmd(u32 cmd)
-{
-	sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_0);
-	do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_0) & (1 << 20));
-}
-
-inline void rtl931x_exec_tbl1_cmd(u32 cmd)
-{
-	sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_1);
-	do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_1) & (1 << 17));
-}
-
-inline int rtl931x_tbl_access_data_0(int i)
-{
-	return RTL931X_TBL_ACCESS_DATA_0(i);
-}
-
-void rtl931x_vlan_profile_dump(int index)
-{
-	u64 profile[4];
-
-	if (index < 0 || index > 15)
-		return;
-
-	profile[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(index));
-	profile[1] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 4) & 0x1FFFFFFFULL) << 32
-		| (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 8) & 0xFFFFFFFF);
-	profile[2] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 16) & 0xFFFFFFFFULL) << 32
-		| (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 12) & 0x1FFFFFFULL);
-	profile[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20) & 0x1FFFFFFFULL) << 32
-		| (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF);
-
-	pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, \
-		IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx",
-		index, (u32) (profile[0] & (3 << 14)), profile[1], profile[2], profile[3]);
-}
-
-static void rtl931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
-{
-	int i;
-	u32 cmd = 1 << 20 /* Execute cmd */
-		| 0 << 19 /* Read */
-		| 2 << 15 /* Table type 0b10 */
-		| (msti & 0x3fff);
-	priv->r->exec_tbl0_cmd(cmd);
-
-	for (i = 0; i < 4; i++)
-		port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
-}
-
-static void rtl931x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
-{
-	int i;
-	u32 cmd = 1 << 20 /* Execute cmd */
-		| 1 << 19 /* Write */
-		| 5 << 15 /* Table type 0b101 */
-		| (msti & 0x3fff);
-	for (i = 0; i < 4; i++)
-		sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
-	priv->r->exec_tbl0_cmd(cmd);
-}
-
-inline static int rtl931x_trk_mbr_ctr(int group)
-{
-	return RTL931X_TRK_MBR_CTRL + (group << 2);
-}
-
-static void rtl931x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
-{
-	u32 v, w, x, y;
-	// Read VLAN table (3) via register 0
-	struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3);
-
-	rtl_table_read(r, vlan);
-	v = sw_r32(rtl_table_data(r, 0));
-	w = sw_r32(rtl_table_data(r, 1));
-	x = sw_r32(rtl_table_data(r, 2));
-	y = sw_r32(rtl_table_data(r, 3));
-	pr_debug("VLAN_READ %d: %08x %08x\n", vlan, v, w);
-	rtl_table_release(r);
-
-	info->tagged_ports = ((u64) v) << 25 | (w >> 7);
-	info->profile_id = (x >> 16) & 0xf;
-	info->hash_mc_fid = !!(x & BIT(30));
-	info->hash_uc_fid = !!(x & BIT(31));
-	info->fid = w & 0x7f;
-	// TODO: use also info in 4th register
-
-	// Read UNTAG table via table register 3
-	r = rtl_table_get(RTL9310_TBL_3, 0);
-	rtl_table_read(r, vlan);
-	v = ((u64)sw_r32(rtl_table_data(r, 0))) << 25;
-	v |= sw_r32(rtl_table_data(r, 1)) >> 7;
-	rtl_table_release(r);
-
-	info->untagged_ports = v;
-}
-
-static void rtl931x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
-{
-	u32 v, w, x;
-	// Access VLAN table (1) via register 0
-	struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3);
-
-	v = info->tagged_ports << 7;
-	w = (info->tagged_ports & 0x7f000000) << 25;
-	w |= (u32)info->fid;
-	x = info->profile_id << 16;
-	w |= info->hash_mc_fid ? BIT(30) : 0;
-	w |= info->hash_uc_fid ? BIT(31) : 0;
-	// TODO: use also info in 4th register
-
-	sw_w32(v, rtl_table_data(r, 0));
-	sw_w32(w, rtl_table_data(r, 1));
-	sw_w32(x, rtl_table_data(r, 2));
-
-	rtl_table_write(r, vlan);
-	rtl_table_release(r);
-}
-
-static void rtl931x_vlan_set_untagged(u32 vlan, u64 portmask)
-{
-	struct table_reg *r = rtl_table_get(RTL9310_TBL_3, 0);
-
-	rtl839x_set_port_reg_be(portmask << 7, rtl_table_data(r, 0));
-	rtl_table_write(r, vlan);
-	rtl_table_release(r);
-}
-
-static inline int rtl931x_mac_force_mode_ctrl(int p)
-{
-	return RTL931X_MAC_FORCE_MODE_CTRL + (p << 2);
-}
-
-static inline int rtl931x_mac_link_spd_sts(int p)
-{
-	return RTL931X_MAC_LINK_SPD_STS(p);
-}
-
-static inline int rtl931x_mac_port_ctrl(int p)
-{
-	return RTL931X_MAC_PORT_CTRL(p);
-}
-
-static inline int rtl931x_l2_port_new_salrn(int p)
-{
-	return RTL931X_L2_PORT_NEW_SALRN(p);
-}
-
-static inline int rtl931x_l2_port_new_sa_fwd(int p)
-{
-	return RTL931X_L2_PORT_NEW_SA_FWD(p);
-}
-
-static u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
-{
-	u64 entry = 0;
-
-	// TODO: Implement
-	return entry;
-}
-
-static u64 rtl931x_read_cam(int idx, struct rtl838x_l2_entry *e)
-{
-	u64 entry = 0;
-
-	// TODO: Implement
-	return entry;
-}
-
-irqreturn_t rtl931x_switch_irq(int irq, void *dev_id)
-{
-	struct dsa_switch *ds = dev_id;
-	u32 status = sw_r32(RTL931X_ISR_GLB_SRC);
-	u64 ports = rtl839x_get_port_reg_le(RTL931X_ISR_PORT_LINK_STS_CHG);
-	u64 link;
-	int i;
-
-	/* Clear status */
-	rtl839x_set_port_reg_le(ports, RTL931X_ISR_PORT_LINK_STS_CHG);
-	pr_info("RTL9310 Link change: status: %x, ports %llx\n", status, ports);
-
-	for (i = 0; i < 56; i++) {
-		if (ports & BIT_ULL(i)) {
-			link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS);
-			if (link & BIT_ULL(i))
-				dsa_port_phylink_mac_change(ds, i, true);
-			else
-				dsa_port_phylink_mac_change(ds, i, false);
-		}
-	}
-	return IRQ_HANDLED;
-}
-
-int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val)
-{
-	u32 v;
-	int err = 0;
-
-	val &= 0xffff;
-	if (port > 63 || page > 4095 || reg > 31)
-		return -ENOTSUPP;
-
-	mutex_lock(&smi_lock);
-	/* Clear both port registers */
-	sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2);
-	sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4);
-	sw_w32_mask(0, BIT(port), RTL931X_SMI_INDRT_ACCESS_CTRL_2+ (port % 32) * 4);
-
-	sw_w32_mask(0xffff0000, val << 16, RTL931X_SMI_INDRT_ACCESS_CTRL_3);
-
-	v = reg << 6 | page << 11 ;
-	sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
-
-	sw_w32(0x1ff, RTL931X_SMI_INDRT_ACCESS_CTRL_1);
-
-	v |= 1 << 3 | 1; /* Write operation and execute */
-	sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
-
-	do {
-	} while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1);
-
-	if (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x2)
-		err = -EIO;
-
-	mutex_unlock(&smi_lock);
-	return err;
-}
-
-int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
-{
-	u32 v;
-
-	if (port > 63 || page > 4095 || reg > 31)
-		return -ENOTSUPP;
-
-	mutex_lock(&smi_lock);
-
-	sw_w32_mask(0xffff, port, RTL931X_SMI_INDRT_ACCESS_CTRL_3);
-	v = reg << 6 | page << 11; // TODO: ACCESS Offset? Park page
-	sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
-
-	sw_w32(0x1ff, RTL931X_SMI_INDRT_ACCESS_CTRL_1);
-
-	v |= 1;
-	sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
-
-	do {
-	} while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1);
-
-	*val = (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3) & 0xffff0000) >> 16;
-
-	pr_info("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, *val);
-
-	mutex_unlock(&smi_lock);
-	return 0;
-}
-
-/*
- * Read an mmd register of the PHY
- */
-int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
-{
-	int err = 0;
-	u32 v;
-	int type = 1; // TODO: For C45 PHYs need to set to 2
-
-	mutex_lock(&smi_lock);
-
-	// Set PHY to access via port-number
-	sw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL);
-
-	// Set MMD device number and register to write to
-	sw_w32(devnum << 16 | (regnum & 0xffff), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);
-
-	v = type << 2 | BIT(0); // MMD-access-type | EXEC
-	sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
-
-	do {
-		v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
-	} while (v & BIT(0));
-
-	// There is no error-checking via BIT 1 of v, as it does not seem to be set correctly
-
-	*val = (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3) & 0xffff);
-
-	pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
-
-	mutex_unlock(&smi_lock);
-
-	return err;
-}
-
-/*
- * Write to an mmd register of the PHY
- */
-int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
-{
-	int err = 0;
-	u32 v;
-	int type = 1; // TODO: For C45 PHYs need to set to 2
-
-	mutex_lock(&smi_lock);
-
-	// Set PHY to access via port-number
-	sw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL);
-
-	// Set data to write
-	sw_w32_mask(0xffff << 16, val << 16, RTL931X_SMI_INDRT_ACCESS_CTRL_3);
-
-	// Set MMD device number and register to write to
-	sw_w32(devnum << 16 | (regnum & 0xffff), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);
-
-	v = BIT(4) | type << 2 | BIT(0); // WRITE | MMD-access-type | EXEC
-	sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
-
-	do {
-		v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
-	} while (v & BIT(0));
-
-	pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
-	mutex_unlock(&smi_lock);
-	return err;
-}
-
-void rtl931x_print_matrix(void)
-{
-	volatile u64 *ptr = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
-	int i;
-
-	for (i = 0; i < 52; i += 4)
-		pr_info("> %16llx %16llx %16llx %16llx\n",
-			ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3]);
-	pr_info("CPU_PORT> %16llx\n", ptr[52]);
-}
-
-const struct rtl838x_reg rtl931x_reg = {
-	.mask_port_reg_be = rtl839x_mask_port_reg_be,
-	.set_port_reg_be = rtl839x_set_port_reg_be,
-	.get_port_reg_be = rtl839x_get_port_reg_be,
-	.mask_port_reg_le = rtl839x_mask_port_reg_le,
-	.set_port_reg_le = rtl839x_set_port_reg_le,
-	.get_port_reg_le = rtl839x_get_port_reg_le,
-	.stat_port_rst = RTL931X_STAT_PORT_RST,
-	.stat_rst = RTL931X_STAT_RST,
-	.stat_port_std_mib = 0,  // Not defined
-	.l2_ctrl_0 = RTL931X_L2_CTRL,
-	.l2_ctrl_1 = RTL931X_L2_AGE_CTRL,
-	.l2_port_aging_out = RTL931X_L2_PORT_AGE_CTRL,
-	// .smi_poll_ctrl does not exist
-	.l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
-	.exec_tbl0_cmd = rtl931x_exec_tbl0_cmd,
-	.exec_tbl1_cmd = rtl931x_exec_tbl1_cmd,
-	.tbl_access_data_0 = rtl931x_tbl_access_data_0,
-	.isr_glb_src = RTL931X_ISR_GLB_SRC,
-	.isr_port_link_sts_chg = RTL931X_ISR_PORT_LINK_STS_CHG,
-	.imr_port_link_sts_chg = RTL931X_IMR_PORT_LINK_STS_CHG,
-	// imr_glb does not exist on RTL931X
-	.vlan_tables_read = rtl931x_vlan_tables_read,
-	.vlan_set_tagged = rtl931x_vlan_set_tagged,
-	.vlan_set_untagged = rtl931x_vlan_set_untagged,
-	.vlan_profile_dump = rtl931x_vlan_profile_dump,
-	.stp_get = rtl931x_stp_get,
-	.stp_set = rtl931x_stp_set,
-	.mac_force_mode_ctrl = rtl931x_mac_force_mode_ctrl,
-	.mac_port_ctrl = rtl931x_mac_port_ctrl,
-	.l2_port_new_salrn = rtl931x_l2_port_new_salrn,
-	.l2_port_new_sa_fwd = rtl931x_l2_port_new_sa_fwd,
-	.mir_ctrl = RTL931X_MIR_CTRL,
-	.mir_dpm = RTL931X_MIR_DPM_CTRL,
-	.mir_spm = RTL931X_MIR_SPM_CTRL,
-	.mac_link_sts = RTL931X_MAC_LINK_STS,
-	.mac_link_dup_sts = RTL931X_MAC_LINK_DUP_STS,
-	.mac_link_spd_sts = rtl931x_mac_link_spd_sts,
-	.mac_rx_pause_sts = RTL931X_MAC_RX_PAUSE_STS,
-	.mac_tx_pause_sts = RTL931X_MAC_TX_PAUSE_STS,
-	.read_l2_entry_using_hash = rtl931x_read_l2_entry_using_hash,
-	.read_cam = rtl931x_read_cam,
-	.vlan_port_egr_filter = RTL931X_VLAN_PORT_EGR_FLTR(0),
-	.vlan_port_igr_filter = RTL931X_VLAN_PORT_IGR_FLTR(0),
-//	.vlan_port_pb = does not exist
-	.vlan_port_tag_sts_ctrl = RTL931X_VLAN_PORT_TAG_CTRL,
-	.trk_mbr_ctr = rtl931x_trk_mbr_ctr,
-};
-
diff --git a/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.c
deleted file mode 100644
index 3f98e3bf81..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.c
+++ /dev/null
@@ -1,2201 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/drivers/net/ethernet/rtl838x_eth.c
- * Copyright (C) 2020 B. Koblitz
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/etherdevice.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/of.h>
-#include <linux/of_net.h>
-#include <linux/of_mdio.h>
-#include <linux/module.h>
-#include <linux/phylink.h>
-#include <linux/pkt_sched.h>
-#include <net/dsa.h>
-#include <net/switchdev.h>
-#include <asm/cacheflush.h>
-
-#include <asm/mach-rtl838x/mach-rtl83xx.h>
-#include "rtl838x_eth.h"
-
-extern struct rtl83xx_soc_info soc_info;
-
-/*
- * Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
- * The ring is assigned by switch based on packet/port priortity
- * Maximum number of TX rings is 2, Ring 2 being the high priority
- * ring on the RTL93xx SoCs. MAX_RING_SIZE * RING_BUFFER gives
- * the memory used for the ring buffer.
- */
-#define MAX_RXRINGS	32
-#define MAX_RXLEN	100
-#define MAX_ENTRIES	(200 * 8)
-#define TXRINGS		2
-// BUG: TXRINGLEN can be 160
-#define TXRINGLEN	16
-#define NOTIFY_EVENTS	10
-#define NOTIFY_BLOCKS	10
-#define TX_EN		0x8
-#define RX_EN		0x4
-#define TX_EN_93XX	0x20
-#define RX_EN_93XX	0x10
-#define TX_DO		0x2
-#define WRAP		0x2
-
-#define RING_BUFFER	1600
-
-#define RTL838X_STORM_CTRL_PORT_BC_EXCEED	(0x470C)
-#define RTL838X_STORM_CTRL_PORT_MC_EXCEED	(0x4710)
-#define RTL838X_STORM_CTRL_PORT_UC_EXCEED	(0x4714)
-#define RTL838X_ATK_PRVNT_STS			(0x5B1C)
-
-struct p_hdr {
-	uint8_t		*buf;
-	uint16_t	reserved;
-	uint16_t	size;		/* buffer size */
-	uint16_t	offset;
-	uint16_t	len;		/* pkt len */
-	uint16_t	cpu_tag[10];
-} __packed __aligned(1);
-
-struct n_event {
-	uint32_t	type:2;
-	uint32_t	fidVid:12;
-	uint64_t	mac:48;
-	uint32_t	slp:6;
-	uint32_t	valid:1;
-	uint32_t	reserved:27;
-} __packed __aligned(1);
-
-struct ring_b {
-	uint32_t	rx_r[MAX_RXRINGS][MAX_RXLEN];
-	uint32_t	tx_r[TXRINGS][TXRINGLEN];
-	struct	p_hdr	rx_header[MAX_RXRINGS][MAX_RXLEN];
-	struct	p_hdr	tx_header[TXRINGS][TXRINGLEN];
-	uint32_t	c_rx[MAX_RXRINGS];
-	uint32_t	c_tx[TXRINGS];
-	uint8_t		tx_space[TXRINGS * TXRINGLEN * RING_BUFFER];
-	uint8_t		*rx_space;
-};
-
-struct notify_block {
-	struct n_event	events[NOTIFY_EVENTS];
-};
-
-struct notify_b {
-	struct notify_block	blocks[NOTIFY_BLOCKS];
-	u32			reserved1[8];
-	u32			ring[NOTIFY_BLOCKS];
-	u32			reserved2[8];
-};
-
-void rtl838x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
-{
-	prio &= 0x7;
-
-	if (dest_port > 0) {
-		// cpu_tag[0] is reserved on the RTL83XX SoCs
-		h->cpu_tag[1] = 0x0400;
-		h->cpu_tag[2] = 0x0200;
-		h->cpu_tag[3] = 0x0000;
-		h->cpu_tag[4] = BIT(dest_port) >> 16;
-		h->cpu_tag[5] = BIT(dest_port) & 0xffff;
-		// Set internal priority and AS_PRIO
-		if (prio >= 0)
-			h->cpu_tag[2] |= (prio | 0x8) << 12;
-	}
-}
-
-void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
-{
-	prio &= 0x7;
-
-	if (dest_port > 0) {
-		// cpu_tag[0] is reserved on the RTL83XX SoCs
-		h->cpu_tag[1] = 0x0100;
-		h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
-		if (dest_port >= 32) {
-			dest_port -= 32;
-			h->cpu_tag[2] = BIT(dest_port) >> 16;
-			h->cpu_tag[3] = BIT(dest_port) & 0xffff;
-		} else {
-			h->cpu_tag[4] = BIT(dest_port) >> 16;
-			h->cpu_tag[5] = BIT(dest_port) & 0xffff;
-		}
-		h->cpu_tag[6] |= BIT(21); // Enable destination port mask use
-		// Set internal priority and AS_PRIO
-		if (prio >= 0)
-			h->cpu_tag[1] |= prio | BIT(3);
-	}
-}
-
-void rtl930x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
-{
-	h->cpu_tag[0] = 0x8000;
-	h->cpu_tag[1] = 0;  // TODO: Fill port and prio
-	h->cpu_tag[2] = 0;
-	h->cpu_tag[3] = 0;
-	h->cpu_tag[4] = 0;
-	h->cpu_tag[5] = 0;
-	h->cpu_tag[6] = 0;
-	h->cpu_tag[7] = 0xffff;
-}
-
-void rtl931x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
-{
-	h->cpu_tag[0] = 0x8000;
-	h->cpu_tag[1] = 0;  // TODO: Fill port and prio
-	h->cpu_tag[2] = 0;
-	h->cpu_tag[3] = 0;
-	h->cpu_tag[4] = 0;
-	h->cpu_tag[5] = 0;
-	h->cpu_tag[6] = 0;
-	h->cpu_tag[7] = 0xffff;
-}
-
-struct rtl838x_rx_q {
-	int id;
-	struct rtl838x_eth_priv *priv;
-	struct napi_struct napi;
-};
-
-struct rtl838x_eth_priv {
-	struct net_device *netdev;
-	struct platform_device *pdev;
-	void		*membase;
-	spinlock_t	lock;
-	struct mii_bus	*mii_bus;
-	struct rtl838x_rx_q rx_qs[MAX_RXRINGS];
-	struct phylink *phylink;
-	struct phylink_config phylink_config;
-	u16 id;
-	u16 family_id;
-	const struct rtl838x_reg *r;
-	u8 cpu_port;
-	u32 lastEvent;
-	u16 rxrings;
-	u16 rxringlen;
-};
-
-extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv);
-extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg);
-extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
-extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);
-extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);
-extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
-extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
-extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
-
-/*
- * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of 
- * the rings. Writing x into these registers substracts x from its content.
- * When the content reaches the ring size, the ASIC no longer adds
- * packets to this receive queue.
- */
-void rtl838x_update_cntr(int r, int released)
-{
-	// This feature is not available on RTL838x SoCs
-}
-
-void rtl839x_update_cntr(int r, int released)
-{
-	// This feature is not available on RTL839x SoCs
-}
-
-void rtl930x_update_cntr(int r, int released)
-{
-	int pos = (r % 3) * 10;
-	u32 reg = RTL930X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
-	u32 v = sw_r32(reg);
-
-	v = (v >> pos) & 0x3ff;
-	pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released, v, pos, reg);
-	sw_w32_mask(0x3ff << pos, released << pos, reg);
-	sw_w32(v, reg);
-}
-
-void rtl931x_update_cntr(int r, int released)
-{
-	int pos = (r % 3) * 10;
-	u32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
-
-	sw_w32_mask(0x3ff << pos, released << pos, reg);
-}
-
-struct dsa_tag {
-	u8	reason;
-	u8	queue;
-	u16	port;
-	u8	l2_offloaded;
-	u8	prio;
-	bool	crc_error;
-};
-
-bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
-{
-	t->reason = h->cpu_tag[3] & 0xf;
-	t->queue = (h->cpu_tag[0] & 0xe0) >> 5;
-	t->port = h->cpu_tag[1] & 0x1f;
-	t->crc_error = t->reason == 13;
-
-	pr_debug("Reason: %d\n", t->reason);
-	if (t->reason != 4) // NIC_RX_REASON_SPECIAL_TRAP
-		t->l2_offloaded = 1;
-	else
-		t->l2_offloaded = 0;
-
-	return t->l2_offloaded;
-}
-
-bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
-{
-	t->reason = h->cpu_tag[4] & 0x1f;
-	t->queue = (h->cpu_tag[3] & 0xe000) >> 13;
-	t->port = h->cpu_tag[1] & 0x3f;
-	t->crc_error = h->cpu_tag[3] & BIT(2);
-
-	pr_debug("Reason: %d\n", t->reason);
-	if ((t->reason != 7) && (t->reason != 8)) // NIC_RX_REASON_RMA_USR
-		t->l2_offloaded = 1;
-	else
-		t->l2_offloaded = 0;
-
-	return t->l2_offloaded;
-}
-
-bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
-{
-	t->reason = h->cpu_tag[7] & 0x3f;
-	t->queue =  (h->cpu_tag[2] >> 11) & 0x1f;
-	t->port = (h->cpu_tag[0] >> 8) & 0x1f;
-	t->crc_error = h->cpu_tag[1] & BIT(6);
-
-	pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue);
-	if (t->reason >= 19 && t->reason <= 27)
-		t->l2_offloaded = 0;
-	else
-		t->l2_offloaded = 1;
-
-	return t->l2_offloaded;
-}
-
-bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
-{
-	t->reason = h->cpu_tag[7] & 0x3f;
-	t->queue =  (h->cpu_tag[2] >> 11) & 0x1f;
-	t->port = (h->cpu_tag[0] >> 8) & 0x3f;
-	t->crc_error = h->cpu_tag[1] & BIT(6);
-
-	pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue);
-	if (t->reason >= 19 && t->reason <= 27)
-		t->l2_offloaded = 0;
-	else
-		t->l2_offloaded = 1;
-
-	return t->l2_offloaded;
-}
-
-/*
- * Discard the RX ring-buffers, called as part of the net-ISR
- * when the buffer runs over
- * Caller needs to hold priv->lock
- */
-static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status)
-{
-	int r;
-	u32	*last;
-	struct p_hdr *h;
-	struct ring_b *ring = priv->membase;
-
-	for (r = 0; r < priv->rxrings; r++) {
-		pr_debug("In %s working on r: %d\n", __func__, r);
-		last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
-		do {
-			if ((ring->rx_r[r][ring->c_rx[r]] & 0x1))
-				break;
-			pr_debug("Got something: %d\n", ring->c_rx[r]);
-			h = &ring->rx_header[r][ring->c_rx[r]];
-			memset(h, 0, sizeof(struct p_hdr));
-			h->buf = (u8 *)KSEG1ADDR(ring->rx_space
-					+ r * priv->rxringlen * RING_BUFFER
-					+ ring->c_rx[r] * RING_BUFFER);
-			h->size = RING_BUFFER;
-			/* make sure the header is visible to the ASIC */
-			mb();
-
-			ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
-				| (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
-			ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
-		} while (&ring->rx_r[r][ring->c_rx[r]] != last);
-	}
-}
-
-struct fdb_update_work {
-	struct work_struct work;
-	struct net_device *ndev;
-	u64 macs[NOTIFY_EVENTS + 1];
-};
-
-void rtl838x_fdb_sync(struct work_struct *work)
-{
-	const struct fdb_update_work *uw =
-		container_of(work, struct fdb_update_work, work);
-	struct switchdev_notifier_fdb_info info;
-	u8 addr[ETH_ALEN];
-	int i = 0;
-	int action;
-
-	while (uw->macs[i]) {
-		action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
-				: SWITCHDEV_FDB_DEL_TO_BRIDGE;
-		u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
-		info.addr = &addr[0];
-		info.vid = 0;
-		info.offloaded = 1;
-		pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action);
-		call_switchdev_notifiers(action, uw->ndev, &info.info, NULL);
-		i++;
-	}
-	kfree(work);
-}
-
-static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
-{
-	struct notify_b *nb = priv->membase + sizeof(struct ring_b);
-	u32 e = priv->lastEvent;
-	struct n_event *event;
-	int i;
-	u64 mac;
-	struct fdb_update_work *w;
-
-	while (!(nb->ring[e] & 1)) {
-		w = kzalloc(sizeof(*w), GFP_ATOMIC);
-		if (!w) {
-			pr_err("Out of memory: %s", __func__);
-			return;
-		}
-		INIT_WORK(&w->work, rtl838x_fdb_sync);
-
-		for (i = 0; i < NOTIFY_EVENTS; i++) {
-			event = &nb->blocks[e].events[i];
-			if (!event->valid)
-				continue;
-			mac = event->mac;
-			if (event->type)
-				mac |= 1ULL << 63;
-			w->ndev = priv->netdev;
-			w->macs[i] = mac;
-		}
-
-		/* Hand the ring entry back to the switch */
-		nb->ring[e] = nb->ring[e] | 1;
-		e = (e + 1) % NOTIFY_BLOCKS;
-
-		w->macs[i] = 0ULL;
-		schedule_work(&w->work);
-	}
-	priv->lastEvent = e;
-}
-
-static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id)
-{
-	struct net_device *dev = dev_id;
-	struct rtl838x_eth_priv *priv = netdev_priv(dev);
-	u32 status = sw_r32(priv->r->dma_if_intr_sts);
-	bool triggered = false;
-	u32 atk = sw_r32(RTL838X_ATK_PRVNT_STS);
-	int i;
-	u32 storm_uc = sw_r32(RTL838X_STORM_CTRL_PORT_UC_EXCEED);
-	u32 storm_mc = sw_r32(RTL838X_STORM_CTRL_PORT_MC_EXCEED);
-	u32 storm_bc = sw_r32(RTL838X_STORM_CTRL_PORT_BC_EXCEED);
-
-	pr_debug("IRQ: %08x\n", status);
-	if (storm_uc || storm_mc || storm_bc) {
-		pr_warn("Storm control UC: %08x, MC: %08x, BC: %08x\n",
-			storm_uc, storm_mc, storm_bc);
-
-		sw_w32(storm_uc, RTL838X_STORM_CTRL_PORT_UC_EXCEED);
-		sw_w32(storm_mc, RTL838X_STORM_CTRL_PORT_MC_EXCEED);
-		sw_w32(storm_bc, RTL838X_STORM_CTRL_PORT_BC_EXCEED);
-
-		triggered = true;
-	}
-
-	if (atk) {
-		pr_debug("Attack prevention triggered: %08x\n", atk);
-		sw_w32(atk, RTL838X_ATK_PRVNT_STS);
-	}
-
-	spin_lock(&priv->lock);
-	/*  Ignore TX interrupt */
-	if ((status & 0xf0000)) {
-		/* Clear ISR */
-		sw_w32(0x000f0000, priv->r->dma_if_intr_sts);
-	}
-
-	/* RX interrupt */
-	if (status & 0x0ff00) {
-		/* ACK and disable RX interrupt for this ring */
-		sw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk);
-		sw_w32(0x0000ff00 & status, priv->r->dma_if_intr_sts);
-		for (i = 0; i < priv->rxrings; i++) {
-			if (status & BIT(i + 8)) {
-				pr_debug("Scheduling queue: %d\n", i);
-				napi_schedule(&priv->rx_qs[i].napi);
-			}
-		}
-	}
-
-	/* RX buffer overrun */
-	if (status & 0x000ff) {
-		pr_info("RX buffer overrun: status %x, mask: %x\n",
-			 status, sw_r32(priv->r->dma_if_intr_msk));
-		sw_w32(status, priv->r->dma_if_intr_sts);
-		rtl838x_rb_cleanup(priv, status & 0xff);
-	}
-
-	if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {
-		sw_w32(0x00100000, priv->r->dma_if_intr_sts);
-		rtl839x_l2_notification_handler(priv);
-	}
-
-	if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) {
-		sw_w32(0x00200000, priv->r->dma_if_intr_sts);
-		rtl839x_l2_notification_handler(priv);
-	}
-
-	if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) {
-		sw_w32(0x00400000, priv->r->dma_if_intr_sts);
-		rtl839x_l2_notification_handler(priv);
-	}
-
-	spin_unlock(&priv->lock);
-	return IRQ_HANDLED;
-}
-
-static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id)
-{
-	struct net_device *dev = dev_id;
-	struct rtl838x_eth_priv *priv = netdev_priv(dev);
-	u32 status_rx_r = sw_r32(priv->r->dma_if_intr_rx_runout_sts);
-	u32 status_rx = sw_r32(priv->r->dma_if_intr_rx_done_sts);
-	u32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts);
-	int i;
-
-	pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
-		__func__, status_tx, status_rx, status_rx_r);
-	spin_lock(&priv->lock);
-
-	/*  Ignore TX interrupt */
-	if (status_tx) {
-		/* Clear ISR */
-		pr_debug("TX done\n");
-		sw_w32(status_tx, priv->r->dma_if_intr_tx_done_sts);
-	}
-
-	/* RX interrupt */
-	if (status_rx) {
-		pr_debug("RX IRQ\n");
-		/* ACK and disable RX interrupt for given rings */
-		sw_w32(status_rx, priv->r->dma_if_intr_rx_done_sts);
-		sw_w32_mask(status_rx, 0, priv->r->dma_if_intr_rx_done_msk);
-		for (i = 0; i < priv->rxrings; i++) {
-			if (status_rx & BIT(i)) {
-				pr_debug("Scheduling queue: %d\n", i);
-				napi_schedule(&priv->rx_qs[i].napi);
-			}
-		}
-	}
-
-	/* RX buffer overrun */
-	if (status_rx_r) {
-		pr_debug("RX buffer overrun: status %x, mask: %x\n",
-			 status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk));
-		sw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts);
-		rtl838x_rb_cleanup(priv, status_rx_r);
-	}
-
-	spin_unlock(&priv->lock);
-	return IRQ_HANDLED;
-}
-
-static const struct rtl838x_reg rtl838x_reg = {
-	.net_irq = rtl83xx_net_irq,
-	.mac_port_ctrl = rtl838x_mac_port_ctrl,
-	.dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,
-	.dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,
-	.dma_if_ctrl = RTL838X_DMA_IF_CTRL,
-	.mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL,
-	.dma_rx_base = RTL838X_DMA_RX_BASE,
-	.dma_tx_base = RTL838X_DMA_TX_BASE,
-	.dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
-	.dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,
-	.dma_if_rx_cur = RTL838X_DMA_IF_RX_CUR,
-	.rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
-	.get_mac_link_sts = rtl838x_get_mac_link_sts,
-	.get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,
-	.get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
-	.get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
-	.get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
-	.mac = RTL838X_MAC,
-	.l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
-	.update_cntr = rtl838x_update_cntr,
-	.create_tx_header = rtl838x_create_tx_header,
-	.decode_tag = rtl838x_decode_tag,
-};
-
-static const struct rtl838x_reg rtl839x_reg = {
-	.net_irq = rtl83xx_net_irq,
-	.mac_port_ctrl = rtl839x_mac_port_ctrl,
-	.dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,
-	.dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,
-	.dma_if_ctrl = RTL839X_DMA_IF_CTRL,
-	.mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL,
-	.dma_rx_base = RTL839X_DMA_RX_BASE,
-	.dma_tx_base = RTL839X_DMA_TX_BASE,
-	.dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
-	.dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,
-	.dma_if_rx_cur = RTL839X_DMA_IF_RX_CUR,
-	.rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
-	.get_mac_link_sts = rtl839x_get_mac_link_sts,
-	.get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,
-	.get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
-	.get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
-	.get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
-	.mac = RTL839X_MAC,
-	.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
-	.update_cntr = rtl839x_update_cntr,
-	.create_tx_header = rtl839x_create_tx_header,
-	.decode_tag = rtl839x_decode_tag,
-};
-
-static const struct rtl838x_reg rtl930x_reg = {
-	.net_irq = rtl93xx_net_irq,
-	.mac_port_ctrl = rtl930x_mac_port_ctrl,
-	.dma_if_intr_rx_runout_sts = RTL930X_DMA_IF_INTR_RX_RUNOUT_STS,
-	.dma_if_intr_rx_done_sts = RTL930X_DMA_IF_INTR_RX_DONE_STS,
-	.dma_if_intr_tx_done_sts = RTL930X_DMA_IF_INTR_TX_DONE_STS,
-	.dma_if_intr_rx_runout_msk = RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK,
-	.dma_if_intr_rx_done_msk = RTL930X_DMA_IF_INTR_RX_DONE_MSK,
-	.dma_if_intr_tx_done_msk = RTL930X_DMA_IF_INTR_TX_DONE_MSK,
-	.l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
-	.l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,
-	.dma_if_ctrl = RTL930X_DMA_IF_CTRL,
-	.mac_force_mode_ctrl = RTL930X_MAC_FORCE_MODE_CTRL,
-	.dma_rx_base = RTL930X_DMA_RX_BASE,
-	.dma_tx_base = RTL930X_DMA_TX_BASE,
-	.dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size,
-	.dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr,
-	.dma_if_rx_cur = RTL930X_DMA_IF_RX_CUR,
-	.rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,
-	.get_mac_link_sts = rtl930x_get_mac_link_sts,
-	.get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts,
-	.get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,
-	.get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,
-	.get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,
-	.mac = RTL930X_MAC_L2_ADDR_CTRL,
-	.l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
-	.update_cntr = rtl930x_update_cntr,
-	.create_tx_header = rtl930x_create_tx_header,
-	.decode_tag = rtl930x_decode_tag,
-};
-
-static const struct rtl838x_reg rtl931x_reg = {
-	.net_irq = rtl93xx_net_irq,
-	.mac_port_ctrl = rtl931x_mac_port_ctrl,
-	.dma_if_intr_rx_runout_sts = RTL931X_DMA_IF_INTR_RX_RUNOUT_STS,
-	.dma_if_intr_rx_done_sts = RTL931X_DMA_IF_INTR_RX_DONE_STS,
-	.dma_if_intr_tx_done_sts = RTL931X_DMA_IF_INTR_TX_DONE_STS,
-	.dma_if_intr_rx_runout_msk = RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK,
-	.dma_if_intr_rx_done_msk = RTL931X_DMA_IF_INTR_RX_DONE_MSK,
-	.dma_if_intr_tx_done_msk = RTL931X_DMA_IF_INTR_TX_DONE_MSK,
-	.l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
-	.l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,
-	.dma_if_ctrl = RTL931X_DMA_IF_CTRL,
-	.mac_force_mode_ctrl = RTL931X_MAC_FORCE_MODE_CTRL,
-	.dma_rx_base = RTL931X_DMA_RX_BASE,
-	.dma_tx_base = RTL931X_DMA_TX_BASE,
-	.dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size,
-	.dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr,
-	.dma_if_rx_cur = RTL931X_DMA_IF_RX_CUR,
-	.rst_glb_ctrl = RTL931X_RST_GLB_CTRL,
-	.get_mac_link_sts = rtl931x_get_mac_link_sts,
-	.get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts,
-	.get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,
-	.get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,
-	.get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,
-	.mac = RTL931X_MAC_L2_ADDR_CTRL,
-	.l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
-	.update_cntr = rtl931x_update_cntr,
-	.create_tx_header = rtl931x_create_tx_header,
-	.decode_tag = rtl931x_decode_tag,
-};
-
-static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
-{
-	u32 int_saved, nbuf;
-	int i, pos;
-	
-	pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
-	sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
-	mdelay(100);
-
-	/* Disable and clear interrupts */
-	if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
-		sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
-		sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
-		sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
-		sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
-		sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
-		sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
-	} else {
-		sw_w32(0x00000000, priv->r->dma_if_intr_msk);
-		sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
-	}
-
-	if (priv->family_id == RTL8390_FAMILY_ID) {
-		/* Preserve L2 notification and NBUF settings */
-		int_saved = sw_r32(priv->r->dma_if_intr_msk);
-		nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
-
-		/* Disable link change interrupt on RTL839x */
-		sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG);
-		sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
-
-		sw_w32(0x00000000, priv->r->dma_if_intr_msk);
-		sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
-	}
-
-	/* Reset NIC  */
-	if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
-		sw_w32(0x4, priv->r->rst_glb_ctrl);
-	else
-		sw_w32(0x8, priv->r->rst_glb_ctrl);
-
-	do { /* Wait for reset of NIC and Queues done */
-		udelay(20);
-	} while (sw_r32(priv->r->rst_glb_ctrl) & 0xc);
-	mdelay(100);
-
-	/* Setup Head of Line */
-	if (priv->family_id == RTL8380_FAMILY_ID)
-		sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE);  // Disabled on RTL8380
-	if (priv->family_id == RTL8390_FAMILY_ID)
-		sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
-	if (priv->family_id == RTL9300_FAMILY_ID) {
-		for (i = 0; i < priv->rxrings; i++) {
-			pos = (i % 3) * 10;
-			sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i));
-			sw_w32_mask(0x3ff << pos, priv->rxringlen,
-				    priv->r->dma_if_rx_ring_cntr(i));
-		}
-	}
-
-	/* Re-enable link change interrupt */
-	if (priv->family_id == RTL8390_FAMILY_ID) {
-		sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);
-		sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);
-		sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);
-		sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
-
-		/* Restore notification settings: on RTL838x these bits are null */
-		sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
-		sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
-	}
-}
-
-static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)
-{
-	int i;
-	struct ring_b *ring = priv->membase;
-
-	for (i = 0; i < priv->rxrings; i++)
-		sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base + i * 4);
-
-	for (i = 0; i < TXRINGS; i++)
-		sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base + i * 4);
-}
-
-static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
-{
-	/* Disable Head of Line features for all RX rings */
-	sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
-
-	/* Truncate RX buffer to 0x640 (1600) bytes, pad TX */
-	sw_w32(0x06400020, priv->r->dma_if_ctrl);
-
-	/* Enable RX done, RX overflow and TX done interrupts */
-	sw_w32(0xfffff, priv->r->dma_if_intr_msk);
-
-	/* Enable DMA, engine expects empty FCS field */
-	sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
-
-	/* Restart TX/RX to CPU port */
-	sw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port));
-	/* Set Speed, duplex, flow control
-	 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
-	 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
-	 * | MEDIA_SEL
-	 */
-	sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
-
-	/* Enable CRC checks on CPU-port */
-	sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
-}
-
-static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
-{
-	/* Setup CPU-Port: RX Buffer */
-	sw_w32(0x0000c808, priv->r->dma_if_ctrl);
-
-	/* Enable Notify, RX done, RX overflow and TX done interrupts */
-	sw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ!
-
-	/* Enable DMA */
-	sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
-
-	/* Restart TX/RX to CPU port, enable CRC checking */
-	sw_w32_mask(0x0, 0x3 | BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
-
-	/* CPU port joins Lookup Miss Flooding Portmask */
-	// TODO: The code below should also work for the RTL838x
-	sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
-	sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
-	sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
-
-	/* Force CPU port link up */
-	sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
-}
-
-static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv)
-{
-	int i, pos;
-	u32 v;
-
-	/* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */
-	sw_w32(0x06400040, priv->r->dma_if_ctrl);
-
-	for (i = 0; i < priv->rxrings; i++) {
-		pos = (i % 3) * 10;
-		sw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i));
-
-		// Some SoCs have issues with missing underflow protection
-		v = (sw_r32(priv->r->dma_if_rx_ring_cntr(i)) >> pos) & 0x3ff;
-		sw_w32_mask(0x3ff << pos, v, priv->r->dma_if_rx_ring_cntr(i));
-	}
-
-	/* Enable Notify, RX done, RX overflow and TX done interrupts */
-	sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_msk);
-	sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
-	sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_msk);
-
-	/* Enable DMA */
-	sw_w32_mask(0, RX_EN_93XX | TX_EN_93XX, priv->r->dma_if_ctrl);
-
-	/* Restart TX/RX to CPU port, enable CRC checking */
-	sw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
-
-	sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);
-	sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
-}
-
-static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring)
-{
-	int i, j;
-
-	struct p_hdr *h;
-
-	for (i = 0; i < priv->rxrings; i++) {
-		for (j = 0; j < priv->rxringlen; j++) {
-			h = &ring->rx_header[i][j];
-			memset(h, 0, sizeof(struct p_hdr));
-			h->buf = (u8 *)KSEG1ADDR(ring->rx_space
-					+ i * priv->rxringlen * RING_BUFFER
-					+ j * RING_BUFFER);
-			h->size = RING_BUFFER;
-			/* All rings owned by switch, last one wraps */
-			ring->rx_r[i][j] = KSEG1ADDR(h) | 1 
-					   | (j == (priv->rxringlen - 1) ? WRAP : 0);
-		}
-		ring->c_rx[i] = 0;
-	}
-
-	for (i = 0; i < TXRINGS; i++) {
-		for (j = 0; j < TXRINGLEN; j++) {
-			h = &ring->tx_header[i][j];
-			memset(h, 0, sizeof(struct p_hdr));
-			h->buf = (u8 *)KSEG1ADDR(ring->tx_space
-					+ i * TXRINGLEN * RING_BUFFER
-					+ j * RING_BUFFER);
-			h->size = RING_BUFFER;
-			ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);
-		}
-		/* Last header is wrapping around */
-		ring->tx_r[i][j-1] |= WRAP;
-		ring->c_tx[i] = 0;
-	}
-}
-
-static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)
-{
-	int i;
-	struct notify_b *b = priv->membase + sizeof(struct ring_b);
-
-	for (i = 0; i < NOTIFY_BLOCKS; i++)
-		b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);
-
-	sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
-	sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);
-
-	/* Setup notification events */
-	sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN
-	sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN
-
-	/* Enable Notification */
-	sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL);
-	priv->lastEvent = 0;
-}
-
-static int rtl838x_eth_open(struct net_device *ndev)
-{
-	unsigned long flags;
-	struct rtl838x_eth_priv *priv = netdev_priv(ndev);
-	struct ring_b *ring = priv->membase;
-	int i, err;
-
-	pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
-		__func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN);
-
-	spin_lock_irqsave(&priv->lock, flags);
-	rtl838x_hw_reset(priv);
-	rtl838x_setup_ring_buffer(priv, ring);
-	if (priv->family_id == RTL8390_FAMILY_ID) {
-		rtl839x_setup_notify_ring_buffer(priv);
-		/* Make sure the ring structure is visible to the ASIC */
-		mb();
-		flush_cache_all();
-	}
-
-	rtl838x_hw_ring_setup(priv);
-	err = request_irq(ndev->irq, priv->r->net_irq, IRQF_SHARED, ndev->name, ndev);
-	if (err) {
-		netdev_err(ndev, "%s: could not acquire interrupt: %d\n",
-			   __func__, err);
-		return err;
-	}
-	phylink_start(priv->phylink);
-
-	for (i = 0; i < priv->rxrings; i++)
-		napi_enable(&priv->rx_qs[i].napi);
-
-	switch (priv->family_id) {
-	case RTL8380_FAMILY_ID:
-		rtl838x_hw_en_rxtx(priv);
-		/* Trap IGMP/MLD traffic to CPU-Port */
-		sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL);
-		/* Flush learned FDB entries on link down of a port */
-		sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0);
-		break;
-
-	case RTL8390_FAMILY_ID:
-		rtl839x_hw_en_rxtx(priv);
-		// Trap MLD and IGMP messages to CPU_PORT
-		sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL);
-		/* Flush learned FDB entries on link down of a port */
-		sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0);
-		break;
-
-	case RTL9300_FAMILY_ID:
-		rtl93xx_hw_en_rxtx(priv);
-		/* Flush learned FDB entries on link down of a port */
-		sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL);
-		// Trap MLD and IGMP messages to CPU_PORT
-		sw_w32((0x2 << 3) | 0x2,  RTL930X_VLAN_APP_PKT_CTRL);
-		break;
-
-	case RTL9310_FAMILY_ID:
-		rtl93xx_hw_en_rxtx(priv);
-		break;
-	}
-
-	netif_tx_start_all_queues(ndev);
-
-	spin_unlock_irqrestore(&priv->lock, flags);
-
-	return 0;
-}
-
-static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
-{
-	u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75;
-	u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
-	int i;
-
-	// Disable RX/TX from/to CPU-port
-	sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
-
-	/* Disable traffic */
-	if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
-		sw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl);
-	else
-		sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
-	mdelay(200); // Test, whether this is needed
-
-	/* Block all ports */
-	if (priv->family_id == RTL8380_FAMILY_ID) {
-		sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
-		sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
-		sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);
-	}
-
-	/* Flush L2 address cache */
-	if (priv->family_id == RTL8380_FAMILY_ID) {
-		for (i = 0; i <= priv->cpu_port; i++) {
-			sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);
-			do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));
-		}
-	} else if (priv->family_id == RTL8390_FAMILY_ID) {
-		for (i = 0; i <= priv->cpu_port; i++) {
-			sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl);
-			do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28));
-		}
-	}
-	// TODO: L2 flush register is 64 bit on RTL931X and 930X
-
-	/* CPU-Port: Link down */
-	if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)
-		sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
-	else
-		sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
-	mdelay(100);
-
-	/* Disable all TX/RX interrupts */
-	if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
-		sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
-		sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
-		sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
-		sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
-		sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
-		sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
-	} else {
-		sw_w32(0x00000000, priv->r->dma_if_intr_msk);
-		sw_w32(clear_irq, priv->r->dma_if_intr_sts);
-	}
-
-	/* Disable TX/RX DMA */
-	sw_w32(0x00000000, priv->r->dma_if_ctrl);
-	mdelay(200);
-}
-
-static int rtl838x_eth_stop(struct net_device *ndev)
-{
-	unsigned long flags;
-	int i;
-	struct rtl838x_eth_priv *priv = netdev_priv(ndev);
-
-	pr_info("in %s\n", __func__);
-
-	spin_lock_irqsave(&priv->lock, flags);
-	phylink_stop(priv->phylink);
-	rtl838x_hw_stop(priv);
-	free_irq(ndev->irq, ndev);
-
-	for (i = 0; i < priv->rxrings; i++)
-		napi_disable(&priv->rx_qs[i].napi);
-
-	netif_tx_stop_all_queues(ndev);
-
-	spin_unlock_irqrestore(&priv->lock, flags);
-
-	return 0;
-}
-
-static void rtl839x_eth_set_multicast_list(struct net_device *ndev)
-{
-	if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
-		sw_w32(0x0, RTL839X_RMA_CTRL_0);
-		sw_w32(0x0, RTL839X_RMA_CTRL_1);
-		sw_w32(0x0, RTL839X_RMA_CTRL_2);
-		sw_w32(0x0, RTL839X_RMA_CTRL_3);
-	}
-	if (ndev->flags & IFF_ALLMULTI) {
-		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
-		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
-		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
-	}
-	if (ndev->flags & IFF_PROMISC) {
-		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
-		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
-		sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
-		sw_w32(0x3ff, RTL839X_RMA_CTRL_3);
-	}
-}
-
-static void rtl838x_eth_set_multicast_list(struct net_device *ndev)
-{
-	struct rtl838x_eth_priv *priv = netdev_priv(ndev);
-
-	if (priv->family_id == RTL8390_FAMILY_ID)
-		return rtl839x_eth_set_multicast_list(ndev);
-
-	if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
-		sw_w32(0x0, RTL838X_RMA_CTRL_0);
-		sw_w32(0x0, RTL838X_RMA_CTRL_1);
-	}
-	if (ndev->flags & IFF_ALLMULTI)
-		sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
-	if (ndev->flags & IFF_PROMISC) {
-		sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
-		sw_w32(0x7fff, RTL838X_RMA_CTRL_1);
-	}
-}
-
-static void rtl930x_eth_set_multicast_list(struct net_device *ndev)
-{
-	if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
-		sw_w32(0x0, RTL930X_RMA_CTRL_0);
-		sw_w32(0x0, RTL930X_RMA_CTRL_1);
-		sw_w32(0x0, RTL930X_RMA_CTRL_2);
-	}
-	if (ndev->flags & IFF_ALLMULTI) {
-		sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
-		sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
-		sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
-	}
-	if (ndev->flags & IFF_PROMISC) {
-		sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
-		sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
-		sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
-	}
-}
-
-static void rtl931x_eth_set_multicast_list(struct net_device *ndev)
-{
-	if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
-		sw_w32(0x0, RTL931X_RMA_CTRL_0);
-		sw_w32(0x0, RTL931X_RMA_CTRL_1);
-		sw_w32(0x0, RTL931X_RMA_CTRL_2);
-	}
-	if (ndev->flags & IFF_ALLMULTI) {
-		sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
-		sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
-		sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
-	}
-	if (ndev->flags & IFF_PROMISC) {
-		sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
-		sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
-		sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
-	}
-}
-
-static void rtl838x_eth_tx_timeout(struct net_device *ndev)
-{
-	unsigned long flags;
-	struct rtl838x_eth_priv *priv = netdev_priv(ndev);
-
-	pr_warn("%s\n", __func__);
-	spin_lock_irqsave(&priv->lock, flags);
-	rtl838x_hw_stop(priv);
-	rtl838x_hw_ring_setup(priv);
-	rtl838x_hw_en_rxtx(priv);
-	netif_trans_update(ndev);
-	netif_start_queue(ndev);
-	spin_unlock_irqrestore(&priv->lock, flags);
-}
-
-static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
-{
-	int len, i;
-	struct rtl838x_eth_priv *priv = netdev_priv(dev);
-	struct ring_b *ring = priv->membase;
-	uint32_t val;
-	int ret;
-	unsigned long flags;
-	struct p_hdr *h;
-	int dest_port = -1;
-	int q = skb_get_queue_mapping(skb) % TXRINGS;
-
-	if (q) // Check for high prio queue
-		pr_debug("SKB priority: %d\n", skb->priority);
-
-	spin_lock_irqsave(&priv->lock, flags);
-	len = skb->len;
-
-	/* Check for DSA tagging at the end of the buffer */
-	if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80 && skb->data[len-3] > 0
-			&& skb->data[len-3] < priv->cpu_port &&  skb->data[len-2] == 0x10
-			&&  skb->data[len-1] == 0x00) {
-		/* Reuse tag space for CRC if possible */
-		dest_port = skb->data[len-3];
-		skb->data[len-4] = skb->data[len-3] = skb->data[len-2] = skb->data[len-1] = 0x00;
-		len -= 4;
-	}
-
-	len += 4; // Add space for CRC
-
-	if (skb_padto(skb, len)) {
-		ret = NETDEV_TX_OK;
-		goto txdone;
-	}
-
-	/* We can send this packet if CPU owns the descriptor */
-	if (!(ring->tx_r[q][ring->c_tx[q]] & 0x1)) {
-
-		/* Set descriptor for tx */
-		h = &ring->tx_header[q][ring->c_tx[q]];
-		h->size = len;
-		h->len = len;
-		// On RTL8380 SoCs, small packet lengths being sent need adjustments
-		if (priv->family_id == RTL8380_FAMILY_ID) {
-			if (len < ETH_ZLEN - 4)
-				h->len -= 4;
-		}
-
-		priv->r->create_tx_header(h, dest_port, skb->priority >> 1);
-
-		/* Copy packet data to tx buffer */
-		memcpy((void *)KSEG1ADDR(h->buf), skb->data, len);
-		/* Make sure packet data is visible to ASIC */
-		wmb();
-
-		/* Hand over to switch */
-		ring->tx_r[q][ring->c_tx[q]] |= 1;
-
-		// Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs
-		if (priv->family_id == RTL8380_FAMILY_ID) {
-			for (i = 0; i < 10; i++) {
-				val = sw_r32(priv->r->dma_if_ctrl);
-				if ((val & 0xc) == 0xc)
-					break;
-			}
-		}
-
-		/* Tell switch to send data */
-		if (priv->family_id == RTL9310_FAMILY_ID
-			|| priv->family_id == RTL9300_FAMILY_ID) {
-			// Ring ID q == 0: Low priority, Ring ID = 1: High prio queue
-			if (!q)
-				sw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl);
-			else
-				sw_w32_mask(0, BIT(3), priv->r->dma_if_ctrl);
-		} else {
-			sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl);
-		}
-
-		dev->stats.tx_packets++;
-		dev->stats.tx_bytes += len;
-		dev_kfree_skb(skb);
-		ring->c_tx[q] = (ring->c_tx[q] + 1) % TXRINGLEN;
-		ret = NETDEV_TX_OK;
-	} else {
-		dev_warn(&priv->pdev->dev, "Data is owned by switch\n");
-		ret = NETDEV_TX_BUSY;
-	}
-txdone:
-	spin_unlock_irqrestore(&priv->lock, flags);
-	return ret;
-}
-
-/*
- * Return queue number for TX. On the RTL83XX, these queues have equal priority
- * so we do round-robin
- */
-u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
-			  struct net_device *sb_dev)
-{
-	static u8 last = 0;
-
-	last++;
-	return last % TXRINGS;
-}
-
-/*
- * Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue
- */
-u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
-			  struct net_device *sb_dev)
-{
-	if (skb->priority >= TC_PRIO_CONTROL)
-		return 1;
-	return 0;
-}
-
-static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
-{
-	struct rtl838x_eth_priv *priv = netdev_priv(dev);
-	struct ring_b *ring = priv->membase;
-	struct sk_buff *skb;
-	unsigned long flags;
-	int i, len, work_done = 0;
-	u8 *data, *skb_data;
-	unsigned int val;
-	u32	*last;
-	struct p_hdr *h;
-	bool dsa = netdev_uses_dsa(dev);
-	struct dsa_tag tag;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
-	pr_debug("---------------------------------------------------------- RX - %d\n", r);
-
-	do {
-		if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {
-			if (&ring->rx_r[r][ring->c_rx[r]] != last) {
-				netdev_warn(dev, "Ring contention: r: %x, last %x, cur %x\n",
-				    r, (uint32_t)last, (u32) &ring->rx_r[r][ring->c_rx[r]]);
-			}
-			break;
-		}
-
-		h = &ring->rx_header[r][ring->c_rx[r]];
-		data = (u8 *)KSEG1ADDR(h->buf);
-		len = h->len;
-		if (!len)
-			break;
-		work_done++;
-
-		len -= 4; /* strip the CRC */
-		/* Add 4 bytes for cpu_tag */
-		if (dsa)
-			len += 4;
-
-		skb = alloc_skb(len + 4, GFP_KERNEL);
-		skb_reserve(skb, NET_IP_ALIGN);
-
-		if (likely(skb)) {
-			/* BUG: Prevent bug on RTL838x SoCs*/
-			if (priv->family_id == RTL8380_FAMILY_ID) {
-				sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
-				for (i = 0; i < priv->rxrings; i++) {
-					/* Update each ring cnt */
-					val = sw_r32(priv->r->dma_if_rx_ring_cntr(i));
-					sw_w32(val, priv->r->dma_if_rx_ring_cntr(i));
-				}
-			}
-
-			skb_data = skb_put(skb, len);
-			/* Make sure data is visible */
-			mb();
-			memcpy(skb->data, (u8 *)KSEG1ADDR(data), len);
-			/* Overwrite CRC with cpu_tag */
-			if (dsa) {
-				priv->r->decode_tag(h, &tag);
-				skb->data[len-4] = 0x80;
-				skb->data[len-3] = tag.port;
-				skb->data[len-2] = 0x10;
-				skb->data[len-1] = 0x00;
-				if (tag.l2_offloaded)
-					skb->data[len-3] |= 0x40;
-			}
-
-			if (tag.queue >= 0)
-				pr_debug("Queue: %d, len: %d, reason %d port %d\n",
-					 tag.queue, len, tag.reason, tag.port);
-
-			skb->protocol = eth_type_trans(skb, dev);
-			if (dev->features & NETIF_F_RXCSUM) {
-				if (tag.crc_error)
-					skb_checksum_none_assert(skb);
-				else
-					skb->ip_summed = CHECKSUM_UNNECESSARY;
-			}
-			dev->stats.rx_packets++;
-			dev->stats.rx_bytes += len;
-
-			netif_receive_skb(skb);
-		} else {
-			if (net_ratelimit())
-				dev_warn(&dev->dev, "low on memory - packet dropped\n");
-			dev->stats.rx_dropped++;
-		}
-
-		/* Reset header structure */
-		memset(h, 0, sizeof(struct p_hdr));
-		h->buf = data;
-		h->size = RING_BUFFER;
-
-		ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1 
-			| (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
-		ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
-		last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
-	} while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);
-
-	// Update counters
-	priv->r->update_cntr(r, 0);
-
-	spin_unlock_irqrestore(&priv->lock, flags);
-	return work_done;
-}
-
-static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
-{
-	struct rtl838x_rx_q *rx_q = container_of(napi, struct rtl838x_rx_q, napi);
-	struct rtl838x_eth_priv *priv = rx_q->priv;
-	int work_done = 0;
-	int r = rx_q->id;
-	int work;
-
-	while (work_done < budget) {
-		work = rtl838x_hw_receive(priv->netdev, r, budget - work_done);
-		if (!work)
-			break;
-		work_done += work;
-	}
-
-	if (work_done < budget) {
-		napi_complete_done(napi, work_done);
-
-		/* Enable RX interrupt */
-		if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
-			sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
-		else
-			sw_w32_mask(0, 0xf00ff | BIT(r + 8), priv->r->dma_if_intr_msk);
-	}
-	return work_done;
-}
-
-
-static void rtl838x_validate(struct phylink_config *config,
-			 unsigned long *supported,
-			 struct phylink_link_state *state)
-{
-	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
-
-	pr_debug("In %s\n", __func__);
-
-	if (!phy_interface_mode_is_rgmii(state->interface) &&
-	    state->interface != PHY_INTERFACE_MODE_1000BASEX &&
-	    state->interface != PHY_INTERFACE_MODE_MII &&
-	    state->interface != PHY_INTERFACE_MODE_REVMII &&
-	    state->interface != PHY_INTERFACE_MODE_GMII &&
-	    state->interface != PHY_INTERFACE_MODE_QSGMII &&
-	    state->interface != PHY_INTERFACE_MODE_INTERNAL &&
-	    state->interface != PHY_INTERFACE_MODE_SGMII) {
-		bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
-		pr_err("Unsupported interface: %d\n", state->interface);
-		return;
-	}
-
-	/* Allow all the expected bits */
-	phylink_set(mask, Autoneg);
-	phylink_set_port_modes(mask);
-	phylink_set(mask, Pause);
-	phylink_set(mask, Asym_Pause);
-
-	/* With the exclusion of MII and Reverse MII, we support Gigabit,
-	 * including Half duplex
-	 */
-	if (state->interface != PHY_INTERFACE_MODE_MII &&
-	    state->interface != PHY_INTERFACE_MODE_REVMII) {
-		phylink_set(mask, 1000baseT_Full);
-		phylink_set(mask, 1000baseT_Half);
-	}
-
-	phylink_set(mask, 10baseT_Half);
-	phylink_set(mask, 10baseT_Full);
-	phylink_set(mask, 100baseT_Half);
-	phylink_set(mask, 100baseT_Full);
-
-	bitmap_and(supported, supported, mask,
-		   __ETHTOOL_LINK_MODE_MASK_NBITS);
-	bitmap_and(state->advertising, state->advertising, mask,
-		   __ETHTOOL_LINK_MODE_MASK_NBITS);
-}
-
-
-static void rtl838x_mac_config(struct phylink_config *config,
-			       unsigned int mode,
-			       const struct phylink_link_state *state)
-{
-	/* This is only being called for the master device,
-	 * i.e. the CPU-Port. We don't need to do anything.
-	 */
-
-	pr_info("In %s, mode %x\n", __func__, mode);
-}
-
-static void rtl838x_mac_an_restart(struct phylink_config *config)
-{
-	struct net_device *dev = container_of(config->dev, struct net_device, dev);
-	struct rtl838x_eth_priv *priv = netdev_priv(dev);
-
-	/* This works only on RTL838x chips */
-	if (priv->family_id != RTL8380_FAMILY_ID)
-		return;
-
-	pr_debug("In %s\n", __func__);
-	/* Restart by disabling and re-enabling link */
-	sw_w32(0x6192D, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
-	mdelay(20);
-	sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
-}
-
-static int rtl838x_mac_pcs_get_state(struct phylink_config *config,
-				  struct phylink_link_state *state)
-{
-	u32 speed;
-	struct net_device *dev = container_of(config->dev, struct net_device, dev);
-	struct rtl838x_eth_priv *priv = netdev_priv(dev);
-	int port = priv->cpu_port;
-
-	pr_debug("In %s\n", __func__);
-
-	state->link = priv->r->get_mac_link_sts(port) ? 1 : 0;
-	state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0;
-
-	speed = priv->r->get_mac_link_spd_sts(port);
-	switch (speed) {
-	case 0:
-		state->speed = SPEED_10;
-		break;
-	case 1:
-		state->speed = SPEED_100;
-		break;
-	case 2:
-		state->speed = SPEED_1000;
-		break;
-	default:
-		state->speed = SPEED_UNKNOWN;
-		break;
-	}
-
-	state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
-	if (priv->r->get_mac_rx_pause_sts(port))
-		state->pause |= MLO_PAUSE_RX;
-	if (priv->r->get_mac_tx_pause_sts(port))
-		state->pause |= MLO_PAUSE_TX;
-
-	return 1;
-}
-
-static void rtl838x_mac_link_down(struct phylink_config *config,
-				  unsigned int mode,
-				  phy_interface_t interface)
-{
-	struct net_device *dev = container_of(config->dev, struct net_device, dev);
-	struct rtl838x_eth_priv *priv = netdev_priv(dev);
-
-	pr_debug("In %s\n", __func__);
-	/* Stop TX/RX to port */
-	sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port));
-}
-
-static void rtl838x_mac_link_up(struct phylink_config *config, unsigned int mode,
-			    phy_interface_t interface,
-			    struct phy_device *phy)
-{
-	struct net_device *dev = container_of(config->dev, struct net_device, dev);
-	struct rtl838x_eth_priv *priv = netdev_priv(dev);
-
-	pr_debug("In %s\n", __func__);
-	/* Restart TX/RX to port */
-	sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port));
-}
-
-static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac)
-{
-	struct rtl838x_eth_priv *priv = netdev_priv(dev);
-	unsigned long flags;
-
-	spin_lock_irqsave(&priv->lock, flags);
-	pr_debug("In %s\n", __func__);
-	sw_w32((mac[0] << 8) | mac[1], priv->r->mac);
-	sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4);
-
-	if (priv->family_id == RTL8380_FAMILY_ID) {
-		/* 2 more registers, ALE/MAC block */
-		sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
-		sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
-		       (RTL838X_MAC_ALE + 4));
-
-		sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);
-		sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
-		       RTL838X_MAC2 + 4);
-	}
-	spin_unlock_irqrestore(&priv->lock, flags);
-}
-
-static int rtl838x_set_mac_address(struct net_device *dev, void *p)
-{
-	struct rtl838x_eth_priv *priv = netdev_priv(dev);
-	const struct sockaddr *addr = p;
-	u8 *mac = (u8 *) (addr->sa_data);
-
-	if (!is_valid_ether_addr(addr->sa_data))
-		return -EADDRNOTAVAIL;
-
-	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
-	rtl838x_set_mac_hw(dev, mac);
-
-	pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4));
-	return 0;
-}
-
-static int rtl8390_init_mac(struct rtl838x_eth_priv *priv)
-{
-	// We will need to set-up EEE and the egress-rate limitation
-	return 0;
-}
-
-static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
-{
-	int i;
-
-	if (priv->family_id == 0x8390)
-		return rtl8390_init_mac(priv);
-
-	pr_info("%s\n", __func__);
-	/* fix timer for EEE */
-	sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
-	sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
-
-	/* Init VLAN */
-	if (priv->id == 0x8382) {
-		for (i = 0; i <= 28; i++)
-			sw_w32(0, 0xd57c + i * 0x80);
-	}
-	if (priv->id == 0x8380) {
-		for (i = 8; i <= 28; i++)
-			sw_w32(0, 0xd57c + i * 0x80);
-	}
-	return 0;
-}
-
-static int rtl838x_get_link_ksettings(struct net_device *ndev,
-				      struct ethtool_link_ksettings *cmd)
-{
-	struct rtl838x_eth_priv *priv = netdev_priv(ndev);
-
-	pr_debug("%s called\n", __func__);
-	return phylink_ethtool_ksettings_get(priv->phylink, cmd);
-}
-
-static int rtl838x_set_link_ksettings(struct net_device *ndev,
-				      const struct ethtool_link_ksettings *cmd)
-{
-	struct rtl838x_eth_priv *priv = netdev_priv(ndev);
-
-	pr_debug("%s called\n", __func__);
-	return phylink_ethtool_ksettings_set(priv->phylink, cmd);
-}
-
-static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
-{
-	u32 val;
-	int err;
-	struct rtl838x_eth_priv *priv = bus->priv;
-
-	if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380)
-		return rtl838x_read_sds_phy(mii_id, regnum);
-	err = rtl838x_read_phy(mii_id, 0, regnum, &val);
-	if (err)
-		return err;
-	return val;
-}
-
-static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
-{
-	u32 val;
-	int err;
-	struct rtl838x_eth_priv *priv = bus->priv;
-
-	if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
-		return rtl839x_read_sds_phy(mii_id, regnum);
-
-	err = rtl839x_read_phy(mii_id, 0, regnum, &val);
-	if (err)
-		return err;
-	return val;
-}
-
-static int rtl930x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
-{
-	u32 val;
-	int err;
-
-	// TODO: These are hard-coded for the 2 Fibre Ports of the XGS1210
-	if (mii_id >= 26 && mii_id <= 27)
-		return rtl930x_read_sds_phy(mii_id - 18, 0, regnum);
-
-	if (regnum & MII_ADDR_C45) {
-		regnum &= ~MII_ADDR_C45;
-		err = rtl930x_read_mmd_phy(mii_id, regnum >> 16, regnum & 0xffff, &val);
-	} else {
-		err = rtl930x_read_phy(mii_id, 0, regnum, &val);
-	}
-	if (err)
-		return err;
-	return val;
-}
-
-static int rtl931x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
-{
-	u32 val;
-	int err;
-//	struct rtl838x_eth_priv *priv = bus->priv;
-
-//	if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
-//		return rtl839x_read_sds_phy(mii_id, regnum);
-
-	err = rtl931x_read_phy(mii_id, 0, regnum, &val);
-	if (err)
-		return err;
-	return val;
-}
-
-static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id,
-			      int regnum, u16 value)
-{
-	u32 offset = 0;
-	struct rtl838x_eth_priv *priv = bus->priv;
-
-	if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {
-		if (mii_id == 26)
-			offset = 0x100;
-		sw_w32(value, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2));
-		return 0;
-	}
-	return rtl838x_write_phy(mii_id, 0, regnum, value);
-}
-
-static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,
-			      int regnum, u16 value)
-{
-	struct rtl838x_eth_priv *priv = bus->priv;
-
-	if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
-		return rtl839x_write_sds_phy(mii_id, regnum, value);
-
-	return rtl839x_write_phy(mii_id, 0, regnum, value);
-}
-
-static int rtl930x_mdio_write(struct mii_bus *bus, int mii_id,
-			      int regnum, u16 value)
-{
-//	struct rtl838x_eth_priv *priv = bus->priv;
-
-//	if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
-//		return rtl839x_write_sds_phy(mii_id, regnum, value);
-	if (regnum & MII_ADDR_C45) {
-		regnum &= ~MII_ADDR_C45;
-		return rtl930x_write_mmd_phy(mii_id, regnum >> 16, regnum & 0xffff, value);
-	}
-
-	return rtl930x_write_phy(mii_id, 0, regnum, value);
-}
-
-static int rtl931x_mdio_write(struct mii_bus *bus, int mii_id,
-			      int regnum, u16 value)
-{
-//	struct rtl838x_eth_priv *priv = bus->priv;
-
-//	if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
-//		return rtl839x_write_sds_phy(mii_id, regnum, value);
-
-	return rtl931x_write_phy(mii_id, 0, regnum, value);
-}
-
-static int rtl838x_mdio_reset(struct mii_bus *bus)
-{
-	pr_debug("%s called\n", __func__);
-	/* Disable MAC polling the PHY so that we can start configuration */
-	sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL);
-
-	/* Enable PHY control via SoC */
-	sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
-
-	// Probably should reset all PHYs here...
-	return 0;
-}
-
-static int rtl839x_mdio_reset(struct mii_bus *bus)
-{
-	return 0;
-
-	pr_debug("%s called\n", __func__);
-	/* BUG: The following does not work, but should! */
-	/* Disable MAC polling the PHY so that we can start configuration */
-	sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL);
-	sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4);
-	/* Disable PHY polling via SoC */
-	sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
-
-	// Probably should reset all PHYs here...
-	return 0;
-}
-
-static int rtl931x_mdio_reset(struct mii_bus *bus)
-{
-	sw_w32(0x00000000, RTL931X_SMI_PORT_POLLING_CTRL);
-	sw_w32(0x00000000, RTL931X_SMI_PORT_POLLING_CTRL + 4);
-
-	pr_debug("%s called\n", __func__);
-
-	return 0;
-}
-
-static int rtl930x_mdio_reset(struct mii_bus *bus)
-{
-	int i;
-	int pos;
-
-	pr_info("RTL930X_SMI_PORT0_15_POLLING_SEL %08x 16-27: %08x\n",
-		sw_r32(RTL930X_SMI_PORT0_15_POLLING_SEL),
-		sw_r32(RTL930X_SMI_PORT16_27_POLLING_SEL));
-
-	pr_info("%s: Enable SMI polling on SMI bus 0, SMI1, SMI2, disable on SMI3\n", __func__);
-	sw_w32_mask(BIT(20) | BIT(21) | BIT(22), BIT(23), RTL930X_SMI_GLB_CTRL);
-
-	pr_info("RTL9300 Powering on SerDes ports\n");
-	rtl9300_sds_power(24, 1);
-	rtl9300_sds_power(25, 1);
-	rtl9300_sds_power(26, 1);
-	rtl9300_sds_power(27, 1);
-	mdelay(200);
-
-	// RTL930X_SMI_PORT0_15_POLLING_SEL 55550000 16-27: 00f9aaaa
-	// i.e SMI=0 for all ports
-	for (i = 0; i < 5; i++)
-		pr_info("port phy: %08x\n", sw_r32(RTL930X_SMI_PORT0_5_ADDR + i *4));
-
-	// 1-to-1 mapping of port to phy-address
-	for (i = 0; i < 24; i++) {
-		pos = (i % 6) * 5;
-		sw_w32_mask(0x1f << pos, i << pos, RTL930X_SMI_PORT0_5_ADDR + (i / 6) * 4);
-	}
-
-	// ports 24 and 25 have PHY addresses 8 and 9, ports 26/27 PHY 26/27
-	sw_w32(8 | 9 << 5 | 26 << 10 | 27 << 15, RTL930X_SMI_PORT0_5_ADDR + 4 * 4);
-
-	// Ports 24 and 25 live on SMI bus 1 and 2
-	sw_w32_mask(0x3 << 16, 0x1 << 16, RTL930X_SMI_PORT16_27_POLLING_SEL);
-	sw_w32_mask(0x3 << 18, 0x2 << 18, RTL930X_SMI_PORT16_27_POLLING_SEL);
-
-	// SMI bus 1 and 2 speak Clause 45 TODO: Configure from .dts
-	sw_w32_mask(0, BIT(17) | BIT(18), RTL930X_SMI_GLB_CTRL);
-
-	// Ports 24 and 25 are 2.5 Gig, set this type (1)
-	sw_w32_mask(0x7 << 12, 1 << 12, RTL930X_SMI_MAC_TYPE_CTRL);
-	sw_w32_mask(0x7 << 15, 1 << 15, RTL930X_SMI_MAC_TYPE_CTRL);
-
-	return 0;
-}
-
-static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
-{
-	struct device_node *mii_np;
-	int ret;
-
-	pr_debug("%s called\n", __func__);
-	mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
-
-	if (!mii_np) {
-		dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus");
-		return -ENODEV;
-	}
-
-	if (!of_device_is_available(mii_np)) {
-		ret = -ENODEV;
-		goto err_put_node;
-	}
-
-	priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev);
-	if (!priv->mii_bus) {
-		ret = -ENOMEM;
-		goto err_put_node;
-	}
-
-	switch(priv->family_id) {
-	case RTL8380_FAMILY_ID:
-		priv->mii_bus->name = "rtl838x-eth-mdio";
-		priv->mii_bus->read = rtl838x_mdio_read;
-		priv->mii_bus->write = rtl838x_mdio_write;
-		priv->mii_bus->reset = rtl838x_mdio_reset;
-		break;
-	case RTL8390_FAMILY_ID:
-		priv->mii_bus->name = "rtl839x-eth-mdio";
-		priv->mii_bus->read = rtl839x_mdio_read;
-		priv->mii_bus->write = rtl839x_mdio_write;
-		priv->mii_bus->reset = rtl839x_mdio_reset;
-		break;
-	case RTL9300_FAMILY_ID:
-		priv->mii_bus->name = "rtl930x-eth-mdio";
-		priv->mii_bus->read = rtl930x_mdio_read;
-		priv->mii_bus->write = rtl930x_mdio_write;
-		priv->mii_bus->reset = rtl930x_mdio_reset;
-	//	priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45; TODO for linux 5.9
-		break;
-	case RTL9310_FAMILY_ID:
-		priv->mii_bus->name = "rtl931x-eth-mdio";
-		priv->mii_bus->read = rtl931x_mdio_read;
-		priv->mii_bus->write = rtl931x_mdio_write;
-		priv->mii_bus->reset = rtl931x_mdio_reset;
-//		priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45;  TODO for linux 5.9
-		break;
-	}
-	priv->mii_bus->priv = priv;
-	priv->mii_bus->parent = &priv->pdev->dev;
-
-	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
-	ret = of_mdiobus_register(priv->mii_bus, mii_np);
-
-err_put_node:
-	of_node_put(mii_np);
-	return ret;
-}
-
-static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv)
-{
-	pr_debug("%s called\n", __func__);
-	if (!priv->mii_bus)
-		return 0;
-
-	mdiobus_unregister(priv->mii_bus);
-	mdiobus_free(priv->mii_bus);
-
-	return 0;
-}
-
-static netdev_features_t rtl838x_fix_features(struct net_device *dev,
-					  netdev_features_t features)
-{
-	return features;
-}
-
-static int rtl83xx_set_features(struct net_device *dev, netdev_features_t features)
-{
-	struct rtl838x_eth_priv *priv = netdev_priv(dev);
-
-	if ((features ^ dev->features) & NETIF_F_RXCSUM) {
-		if (!(features & NETIF_F_RXCSUM))
-			sw_w32_mask(BIT(3), 0, priv->r->mac_port_ctrl(priv->cpu_port));
-		else
-			sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
-	}
-
-	return 0;
-}
-
-static int rtl93xx_set_features(struct net_device *dev, netdev_features_t features)
-{
-	struct rtl838x_eth_priv *priv = netdev_priv(dev);
-
-	if ((features ^ dev->features) & NETIF_F_RXCSUM) {
-		if (!(features & NETIF_F_RXCSUM))
-			sw_w32_mask(BIT(4), 0, priv->r->mac_port_ctrl(priv->cpu_port));
-		else
-			sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
-	}
-
-	return 0;
-}
-
-static const struct net_device_ops rtl838x_eth_netdev_ops = {
-	.ndo_open = rtl838x_eth_open,
-	.ndo_stop = rtl838x_eth_stop,
-	.ndo_start_xmit = rtl838x_eth_tx,
-	.ndo_select_queue = rtl83xx_pick_tx_queue,
-	.ndo_set_mac_address = rtl838x_set_mac_address,
-	.ndo_validate_addr = eth_validate_addr,
-	.ndo_set_rx_mode = rtl838x_eth_set_multicast_list,
-	.ndo_tx_timeout = rtl838x_eth_tx_timeout,
-	.ndo_set_features = rtl83xx_set_features,
-	.ndo_fix_features = rtl838x_fix_features,
-};
-
-static const struct net_device_ops rtl839x_eth_netdev_ops = {
-	.ndo_open = rtl838x_eth_open,
-	.ndo_stop = rtl838x_eth_stop,
-	.ndo_start_xmit = rtl838x_eth_tx,
-	.ndo_select_queue = rtl83xx_pick_tx_queue,
-	.ndo_set_mac_address = rtl838x_set_mac_address,
-	.ndo_validate_addr = eth_validate_addr,
-	.ndo_set_rx_mode = rtl839x_eth_set_multicast_list,
-	.ndo_tx_timeout = rtl838x_eth_tx_timeout,
-	.ndo_set_features = rtl83xx_set_features,
-	.ndo_fix_features = rtl838x_fix_features,
-};
-
-static const struct net_device_ops rtl930x_eth_netdev_ops = {
-	.ndo_open = rtl838x_eth_open,
-	.ndo_stop = rtl838x_eth_stop,
-	.ndo_start_xmit = rtl838x_eth_tx,
-	.ndo_select_queue = rtl93xx_pick_tx_queue,
-	.ndo_set_mac_address = rtl838x_set_mac_address,
-	.ndo_validate_addr = eth_validate_addr,
-	.ndo_set_rx_mode = rtl930x_eth_set_multicast_list,
-	.ndo_tx_timeout = rtl838x_eth_tx_timeout,
-	.ndo_set_features = rtl93xx_set_features,
-	.ndo_fix_features = rtl838x_fix_features,
-};
-
-static const struct net_device_ops rtl931x_eth_netdev_ops = {
-	.ndo_open = rtl838x_eth_open,
-	.ndo_stop = rtl838x_eth_stop,
-	.ndo_start_xmit = rtl838x_eth_tx,
-	.ndo_select_queue = rtl93xx_pick_tx_queue,
-	.ndo_set_mac_address = rtl838x_set_mac_address,
-	.ndo_validate_addr = eth_validate_addr,
-	.ndo_set_rx_mode = rtl931x_eth_set_multicast_list,
-	.ndo_tx_timeout = rtl838x_eth_tx_timeout,
-	.ndo_set_features = rtl93xx_set_features,
-	.ndo_fix_features = rtl838x_fix_features,
-};
-
-static const struct phylink_mac_ops rtl838x_phylink_ops = {
-	.validate = rtl838x_validate,
-	.mac_link_state = rtl838x_mac_pcs_get_state,
-	.mac_an_restart = rtl838x_mac_an_restart,
-	.mac_config = rtl838x_mac_config,
-	.mac_link_down = rtl838x_mac_link_down,
-	.mac_link_up = rtl838x_mac_link_up,
-};
-
-static const struct ethtool_ops rtl838x_ethtool_ops = {
-	.get_link_ksettings     = rtl838x_get_link_ksettings,
-	.set_link_ksettings     = rtl838x_set_link_ksettings,
-};
-
-static int __init rtl838x_eth_probe(struct platform_device *pdev)
-{
-	struct net_device *dev;
-	struct device_node *dn = pdev->dev.of_node;
-	struct rtl838x_eth_priv *priv;
-	struct resource *res, *mem;
-	phy_interface_t phy_mode;
-	struct phylink *phylink;
-	int err = 0, i, rxrings, rxringlen;
-	struct ring_b *ring;
-
-	pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
-		(u32)pdev, (u32)(&(pdev->dev)));
-
-	if (!dn) {
-		dev_err(&pdev->dev, "No DT found\n");
-		return -EINVAL;
-	}
-
-	rxrings = (soc_info.family == RTL8380_FAMILY_ID 
-			|| soc_info.family == RTL8390_FAMILY_ID) ? 8 : 32;
-	rxrings = rxrings > MAX_RXRINGS ? MAX_RXRINGS : rxrings;
-	rxringlen = MAX_ENTRIES / rxrings;
-	rxringlen = rxringlen > MAX_RXLEN ? MAX_RXLEN : rxringlen;
-
-	dev = alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv), TXRINGS, rxrings);
-	if (!dev) {
-		err = -ENOMEM;
-		goto err_free;
-	}
-	SET_NETDEV_DEV(dev, &pdev->dev);
-	priv = netdev_priv(dev);
-
-	/* obtain buffer memory space */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (res) {
-		mem = devm_request_mem_region(&pdev->dev, res->start,
-			resource_size(res), res->name);
-		if (!mem) {
-			dev_err(&pdev->dev, "cannot request memory space\n");
-			err = -ENXIO;
-			goto err_free;
-		}
-
-		dev->mem_start = mem->start;
-		dev->mem_end   = mem->end;
-	} else {
-		dev_err(&pdev->dev, "cannot request IO resource\n");
-		err = -ENXIO;
-		goto err_free;
-	}
-
-	/* Allocate buffer memory */
-	priv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER
-				+ sizeof(struct ring_b) + sizeof(struct notify_b),
-				(void *)&dev->mem_start, GFP_KERNEL);
-	if (!priv->membase) {
-		dev_err(&pdev->dev, "cannot allocate DMA buffer\n");
-		err = -ENOMEM;
-		goto err_free;
-	}
-
-	// Allocate ring-buffer space at the end of the allocated memory
-	ring = priv->membase;
-	ring->rx_space = priv->membase + sizeof(struct ring_b) + sizeof(struct notify_b);
-
-	spin_lock_init(&priv->lock);
-
-	/* obtain device IRQ number */
-	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (!res) {
-		dev_err(&pdev->dev, "cannot obtain IRQ, using default 24\n");
-		dev->irq = 24;
-	} else {
-		dev->irq = res->start;
-	}
-	dev->ethtool_ops = &rtl838x_ethtool_ops;
-	dev->min_mtu = ETH_ZLEN;
-	dev->max_mtu = 1536;
-	dev->features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM;
-	dev->hw_features = NETIF_F_RXCSUM;
-
-	priv->id = soc_info.id;
-	priv->family_id = soc_info.family;
-	if (priv->id) {
-		pr_info("Found SoC ID: %4x: %s, family %x\n",
-			priv->id, soc_info.name, priv->family_id);
-	} else {
-		pr_err("Unknown chip id (%04x)\n", priv->id);
-		return -ENODEV;
-	}
-
-	switch (priv->family_id) {
-	case RTL8380_FAMILY_ID:
-		priv->cpu_port = RTL838X_CPU_PORT;
-		priv->r = &rtl838x_reg;
-		dev->netdev_ops = &rtl838x_eth_netdev_ops;
-		break;
-	case RTL8390_FAMILY_ID:
-		priv->cpu_port = RTL839X_CPU_PORT;
-		priv->r = &rtl839x_reg;
-		dev->netdev_ops = &rtl839x_eth_netdev_ops;
-		break;
-	case RTL9300_FAMILY_ID:
-		priv->cpu_port = RTL930X_CPU_PORT;
-		priv->r = &rtl930x_reg;
-		dev->netdev_ops = &rtl930x_eth_netdev_ops;
-		break;
-	case RTL9310_FAMILY_ID:
-		priv->cpu_port = RTL931X_CPU_PORT;
-		priv->r = &rtl931x_reg;
-		dev->netdev_ops = &rtl931x_eth_netdev_ops;
-		break;
-	default:
-		pr_err("Unknown SoC family\n");
-		return -ENODEV;
-	}
-	priv->rxringlen = rxringlen;
-	priv->rxrings = rxrings;
-
-	rtl8380_init_mac(priv);
-
-	/* try to get mac address in the following order:
-	 * 1) from device tree data
-	 * 2) from internal registers set by bootloader
-	 */
-	of_get_mac_address(pdev->dev.of_node, dev->dev_addr);
-	if (is_valid_ether_addr(dev->dev_addr)) {
-		rtl838x_set_mac_hw(dev, (u8 *)dev->dev_addr);
-	} else {
-		dev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff;
-		dev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff;
-		dev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff;
-		dev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff;
-		dev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff;
-		dev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff;
-	}
-	/* if the address is invalid, use a random value */
-	if (!is_valid_ether_addr(dev->dev_addr)) {
-		struct sockaddr sa = { AF_UNSPEC };
-
-		netdev_warn(dev, "Invalid MAC address, using random\n");
-		eth_hw_addr_random(dev);
-		memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
-		if (rtl838x_set_mac_address(dev, &sa))
-			netdev_warn(dev, "Failed to set MAC address.\n");
-	}
-	pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac),
-					sw_r32(priv->r->mac + 4));
-	strcpy(dev->name, "eth%d");
-	priv->pdev = pdev;
-	priv->netdev = dev;
-
-	err = rtl838x_mdio_init(priv);
-	if (err)
-		goto err_free;
-
-	err = register_netdev(dev);
-	if (err)
-		goto err_free;
-
-	for (i = 0; i < priv->rxrings; i++) {
-		priv->rx_qs[i].id = i;
-		priv->rx_qs[i].priv = priv;
-		netif_napi_add(dev, &priv->rx_qs[i].napi, rtl838x_poll_rx, 64);
-	}
-
-	platform_set_drvdata(pdev, dev);
-
-	phy_mode = of_get_phy_mode(dn);
-	if (phy_mode < 0) {
-		dev_err(&pdev->dev, "incorrect phy-mode\n");
-		err = -EINVAL;
-		goto err_free;
-	}
-	priv->phylink_config.dev = &dev->dev;
-	priv->phylink_config.type = PHYLINK_NETDEV;
-
-	phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode,
-				 phy_mode, &rtl838x_phylink_ops);
-	if (IS_ERR(phylink)) {
-		err = PTR_ERR(phylink);
-		goto err_free;
-	}
-	priv->phylink = phylink;
-
-	return 0;
-
-err_free:
-	pr_err("Error setting up netdev, freeing it again.\n");
-	free_netdev(dev);
-	return err;
-}
-
-static int rtl838x_eth_remove(struct platform_device *pdev)
-{
-	struct net_device *dev = platform_get_drvdata(pdev);
-	struct rtl838x_eth_priv *priv = netdev_priv(dev);
-	int i;
-
-	if (dev) {
-		pr_info("Removing platform driver for rtl838x-eth\n");
-		rtl838x_mdio_remove(priv);
-		rtl838x_hw_stop(priv);
-
-		netif_tx_stop_all_queues(dev);
-
-		for (i = 0; i < priv->rxrings; i++)
-			netif_napi_del(&priv->rx_qs[i].napi);
-
-		unregister_netdev(dev);
-		free_netdev(dev);
-	}
-	return 0;
-}
-
-static const struct of_device_id rtl838x_eth_of_ids[] = {
-	{ .compatible = "realtek,rtl838x-eth"},
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);
-
-static struct platform_driver rtl838x_eth_driver = {
-	.probe = rtl838x_eth_probe,
-	.remove = rtl838x_eth_remove,
-	.driver = {
-		.name = "rtl838x-eth",
-		.pm = NULL,
-		.of_match_table = rtl838x_eth_of_ids,
-	},
-};
-
-module_platform_driver(rtl838x_eth_driver);
-
-MODULE_AUTHOR("B. Koblitz");
-MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
-MODULE_LICENSE("GPL");
diff --git a/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.h b/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.h
deleted file mode 100644
index c7e97057b3..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.h
+++ /dev/null
@@ -1,429 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _RTL838X_ETH_H
-#define _RTL838X_ETH_H
-
-/*
- * Register definition
- */
-
-/* Per port MAC control */
-#define RTL838X_MAC_PORT_CTRL			(0xd560)
-#define RTL839X_MAC_PORT_CTRL			(0x8004)
-#define RTL930X_MAC_L2_PORT_CTRL		(0x3268)
-#define RTL930X_MAC_PORT_CTRL			(0x3260)
-#define RTL931X_MAC_L2_PORT_CTRL		(0x6000)
-#define RTL931X_MAC_PORT_CTRL			(0x6004)
-
-/* DMA interrupt control and status registers */
-#define RTL838X_DMA_IF_CTRL			(0x9f58)
-#define RTL838X_DMA_IF_INTR_STS			(0x9f54)
-#define RTL838X_DMA_IF_INTR_MSK			(0x9f50)
-
-#define RTL839X_DMA_IF_CTRL			(0x786c)
-#define RTL839X_DMA_IF_INTR_STS			(0x7868)
-#define RTL839X_DMA_IF_INTR_MSK			(0x7864)
-
-#define RTL930X_DMA_IF_CTRL			(0xe028)
-#define RTL930X_DMA_IF_INTR_RX_RUNOUT_STS	(0xe01C)
-#define RTL930X_DMA_IF_INTR_RX_DONE_STS		(0xe020)
-#define RTL930X_DMA_IF_INTR_TX_DONE_STS		(0xe024)
-#define RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK	(0xe010)
-#define RTL930X_DMA_IF_INTR_RX_DONE_MSK		(0xe014)
-#define RTL930X_DMA_IF_INTR_TX_DONE_MSK		(0xe018)
-#define RTL930X_L2_NTFY_IF_INTR_MSK		(0xe04C)
-#define RTL930X_L2_NTFY_IF_INTR_STS		(0xe050)
-
-/* TODO: RTL931X_DMA_IF_CTRL has different bits meanings */
-#define RTL931X_DMA_IF_CTRL			(0x0928)
-#define RTL931X_DMA_IF_INTR_RX_RUNOUT_STS	(0x091c)
-#define RTL931X_DMA_IF_INTR_RX_DONE_STS		(0x0920)
-#define RTL931X_DMA_IF_INTR_TX_DONE_STS		(0x0924)
-#define RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK	(0x0910)
-#define RTL931X_DMA_IF_INTR_RX_DONE_MSK		(0x0914)
-#define RTL931X_DMA_IF_INTR_TX_DONE_MSK		(0x0918)
-#define RTL931X_L2_NTFY_IF_INTR_MSK		(0x09E4)
-#define RTL931X_L2_NTFY_IF_INTR_STS		(0x09E8)
-
-#define RTL838X_MAC_FORCE_MODE_CTRL		(0xa104)
-#define RTL839X_MAC_FORCE_MODE_CTRL		(0x02bc)
-#define RTL930X_MAC_FORCE_MODE_CTRL		(0xCA1C)
-#define RTL931X_MAC_FORCE_MODE_CTRL		(0x0ddc)
-
-/* MAC address settings */
-#define RTL838X_MAC				(0xa9ec)
-#define RTL839X_MAC				(0x02b4)
-#define RTL838X_MAC_ALE				(0x6b04)
-#define RTL838X_MAC2				(0xa320)
-#define RTL930X_MAC_L2_ADDR_CTRL		(0xC714)
-#define RTL931X_MAC_L2_ADDR_CTRL		(0x135c)
-
-/* Ringbuffer setup */
-#define RTL838X_DMA_RX_BASE			(0x9f00)
-#define RTL839X_DMA_RX_BASE			(0x780c)
-#define RTL930X_DMA_RX_BASE			(0xdf00)
-#define RTL931X_DMA_RX_BASE			(0x0800)
-
-#define RTL838X_DMA_TX_BASE			(0x9f40)
-#define RTL839X_DMA_TX_BASE			(0x784c)
-#define RTL930X_DMA_TX_BASE			(0xe000)
-#define RTL931X_DMA_TX_BASE			(0x0900)
-
-#define RTL838X_DMA_IF_RX_RING_SIZE		(0xB7E4)
-#define RTL839X_DMA_IF_RX_RING_SIZE		(0x6038)
-#define RTL930X_DMA_IF_RX_RING_SIZE		(0x7C60)
-#define RTL931X_DMA_IF_RX_RING_SIZE		(0x2080)
-
-#define RTL838X_DMA_IF_RX_RING_CNTR		(0xB7E8)
-#define RTL839X_DMA_IF_RX_RING_CNTR		(0x603c)
-#define RTL930X_DMA_IF_RX_RING_CNTR		(0x7C8C)
-#define RTL931X_DMA_IF_RX_RING_CNTR		(0x20AC)
-
-#define RTL838X_DMA_IF_RX_CUR			(0x9F20)
-#define RTL839X_DMA_IF_RX_CUR			(0x782c)
-#define RTL930X_DMA_IF_RX_CUR			(0xdf80)
-#define RTL931X_DMA_IF_RX_CUR			(0x0880)
-
-#define RTL838X_DMA_IF_TX_CUR_DESC_ADDR_CTRL	(0x9F48)
-#define RTL930X_DMA_IF_TX_CUR_DESC_ADDR_CTRL	(0xE008)
-
-#define RTL838X_DMY_REG31			(0x3b28)
-#define RTL838X_SDS_MODE_SEL			(0x0028)
-#define RTL838X_SDS_CFG_REG			(0x0034)
-#define RTL838X_INT_MODE_CTRL			(0x005c)
-#define RTL838X_CHIP_INFO			(0x00d8)
-#define RTL838X_SDS4_REG28			(0xef80)
-#define RTL838X_SDS4_DUMMY0			(0xef8c)
-#define RTL838X_SDS5_EXT_REG6			(0xf18c)
-
-/* L2 features */
-#define RTL839X_TBL_ACCESS_L2_CTRL		(0x1180)
-#define RTL839X_TBL_ACCESS_L2_DATA(idx)		(0x1184 + ((idx) << 2))
-#define RTL838X_TBL_ACCESS_CTRL_0		(0x6914)
-#define RTL838X_TBL_ACCESS_DATA_0(idx)		(0x6918 + ((idx) << 2))
-
-/* MAC-side link state handling */
-#define RTL838X_MAC_LINK_STS			(0xa188)
-#define RTL839X_MAC_LINK_STS			(0x0390)
-#define RTL930X_MAC_LINK_STS			(0xCB10)
-#define RTL931X_MAC_LINK_STS			(0x0ec0)
-
-#define RTL838X_MAC_LINK_SPD_STS		(0xa190)
-#define RTL839X_MAC_LINK_SPD_STS		(0x03a0)
-#define RTL930X_MAC_LINK_SPD_STS		(0xCB18)
-#define RTL931X_MAC_LINK_SPD_STS		(0x0ed0)
-
-#define RTL838X_MAC_LINK_DUP_STS		(0xa19c)
-#define RTL839X_MAC_LINK_DUP_STS		(0x03b0)
-#define RTL930X_MAC_LINK_DUP_STS		(0xCB28)
-#define RTL931X_MAC_LINK_DUP_STS		(0x0ef0)
-
-// TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ???
-
-#define RTL838X_MAC_TX_PAUSE_STS		(0xa1a0)
-#define RTL839X_MAC_TX_PAUSE_STS		(0x03b8)
-#define RTL930X_MAC_TX_PAUSE_STS		(0xCB2C)
-#define RTL931X_MAC_TX_PAUSE_STS		(0x0ef8)
-
-#define RTL838X_MAC_RX_PAUSE_STS		(0xa1a4)
-#define RTL839X_MAC_RX_PAUSE_STS		(0xCB30)
-#define RTL930X_MAC_RX_PAUSE_STS		(0xC2F8)
-#define RTL931X_MAC_RX_PAUSE_STS		(0x0f00)
-
-#define RTL838X_EEE_TX_TIMER_GIGA_CTRL		(0xaa04)
-#define RTL838X_EEE_TX_TIMER_GELITE_CTRL	(0xaa08)
-
-#define RTL930X_L2_UNKN_UC_FLD_PMSK		(0x9064)
-
-#define RTL839X_MAC_GLB_CTRL			(0x02a8)
-#define RTL839X_SCHED_LB_TICK_TKN_CTRL		(0x60f8)
-
-#define RTL838X_L2_TBL_FLUSH_CTRL		(0x3370)
-#define RTL839X_L2_TBL_FLUSH_CTRL		(0x3ba0)
-#define RTL930X_L2_TBL_FLUSH_CTRL		(0x9404)
-#define RTL931X_L2_TBL_FLUSH_CTRL		(0xCD9C)
-
-#define RTL930X_L2_PORT_SABLK_CTRL		(0x905c)
-#define RTL930X_L2_PORT_DABLK_CTRL		(0x9060)
-
-/* MAC link state bits */
-#define FORCE_EN				(1 << 0)
-#define FORCE_LINK_EN				(1 << 1)
-#define NWAY_EN					(1 << 2)
-#define DUPLX_MODE				(1 << 3)
-#define TX_PAUSE_EN				(1 << 6)
-#define RX_PAUSE_EN				(1 << 7)
-
-/* L2 Notification DMA interface */
-#define RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL	(0x785C)
-#define RTL839X_L2_NOTIFICATION_CTRL		(0x7808)
-#define RTL931X_L2_NTFY_RING_BASE_ADDR		(0x09DC)
-#define RTL931X_L2_NTFY_RING_CUR_ADDR		(0x09E0)
-#define RTL839X_L2_NOTIFICATION_CTRL		(0x7808)
-#define RTL931X_L2_NTFY_CTRL			(0xCDC8)
-#define RTL838X_L2_CTRL_0			(0x3200)
-#define RTL839X_L2_CTRL_0			(0x3800)
-#define RTL930X_L2_CTRL				(0x8FD8)
-#define RTL931X_L2_CTRL				(0xC800)
-
-/* TRAPPING to CPU-PORT */
-#define RTL838X_SPCL_TRAP_IGMP_CTRL		(0x6984)
-#define RTL838X_RMA_CTRL_0			(0x4300)
-#define RTL838X_RMA_CTRL_1			(0x4304)
-#define RTL839X_RMA_CTRL_0			(0x1200)
-
-#define RTL839X_SPCL_TRAP_IGMP_CTRL		(0x1058)
-#define RTL839X_RMA_CTRL_1			(0x1204)
-#define RTL839X_RMA_CTRL_2			(0x1208)
-#define RTL839X_RMA_CTRL_3			(0x120C)
-
-#define RTL930X_VLAN_APP_PKT_CTRL		(0xA23C)
-#define RTL930X_RMA_CTRL_0			(0x9E60)
-#define RTL930X_RMA_CTRL_1			(0x9E64)
-#define RTL930X_RMA_CTRL_2			(0x9E68)
-
-#define RTL931X_RMA_CTRL_0			(0x8800)
-#define RTL931X_RMA_CTRL_1			(0x8804)
-#define RTL931X_RMA_CTRL_2			(0x8808)
-
-/* Advanced SMI control for clause 45 PHYs */
-#define RTL930X_SMI_MAC_TYPE_CTRL		(0xCA04)
-#define RTL930X_SMI_PORT24_27_ADDR_CTRL		(0xCB90)
-#define RTL930X_SMI_PORT0_15_POLLING_SEL	(0xCA08)
-#define RTL930X_SMI_PORT16_27_POLLING_SEL	(0xCA0C)
-
-/* Registers of the internal Serdes of the 8390 */
-#define RTL839X_SDS12_13_XSG0			(0xB800)
-
-/* Registers of the internal Serdes of the 8380 */
-#define RTL838X_SDS4_FIB_REG0			(0xF800)
-
-inline int rtl838x_mac_port_ctrl(int p)
-{
-	return RTL838X_MAC_PORT_CTRL + (p << 7);
-}
-
-inline int rtl839x_mac_port_ctrl(int p)
-{
-	return RTL839X_MAC_PORT_CTRL + (p << 7);
-}
-
-/* On the RTL931XX, the functionality of the MAC port control register is split up
- * into RTL931X_MAC_L2_PORT_CTRL and RTL931X_MAC_PORT_CTRL the functionality used
- * by the Ethernet driver is in the same bits now in RTL931X_MAC_L2_PORT_CTRL
- */
-
-inline int rtl930x_mac_port_ctrl(int p)
-{
-	return RTL930X_MAC_L2_PORT_CTRL + (p << 6);
-}
-
-inline int rtl931x_mac_port_ctrl(int p)
-{
-	return RTL931X_MAC_L2_PORT_CTRL + (p << 7);
-}
-
-inline int rtl838x_dma_if_rx_ring_size(int i)
-{
-	return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
-}
-
-inline int rtl839x_dma_if_rx_ring_size(int i)
-{
-	return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
-}
-
-inline int rtl930x_dma_if_rx_ring_size(int i)
-{
-	return RTL930X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2);
-}
-
-inline int rtl931x_dma_if_rx_ring_size(int i)
-{
-	return RTL931X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2);
-}
-
-inline int rtl838x_dma_if_rx_ring_cntr(int i)
-{
-	return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
-}
-
-inline int rtl839x_dma_if_rx_ring_cntr(int i)
-{
-	return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
-}
-
-inline int rtl930x_dma_if_rx_ring_cntr(int i)
-{
-	return RTL930X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2);
-}
-
-inline int rtl931x_dma_if_rx_ring_cntr(int i)
-{
-	return RTL931X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2);
-}
-
-inline u32 rtl838x_get_mac_link_sts(int port)
-{
-	return (sw_r32(RTL838X_MAC_LINK_STS) & BIT(port));
-}
-
-inline u32 rtl839x_get_mac_link_sts(int p)
-{
-	return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32));
-}
-
-inline u32 rtl930x_get_mac_link_sts(int port)
-{
-	return (sw_r32(RTL930X_MAC_LINK_STS) & BIT(port));
-}
-
-inline u32 rtl931x_get_mac_link_sts(int p)
-{
-	return (sw_r32(RTL931X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32));
-}
-
-inline u32 rtl838x_get_mac_link_dup_sts(int port)
-{
-	return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & BIT(port));
-}
-
-inline u32 rtl839x_get_mac_link_dup_sts(int p)
-{
-	return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));
-}
-
-inline u32 rtl930x_get_mac_link_dup_sts(int port)
-{
-	return (sw_r32(RTL930X_MAC_LINK_DUP_STS) & BIT(port));
-}
-
-inline u32 rtl931x_get_mac_link_dup_sts(int p)
-{
-	return (sw_r32(RTL931X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));
-}
-
-inline u32 rtl838x_get_mac_link_spd_sts(int port)
-{
-	int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
-	u32 speed = sw_r32(r);
-
-	speed >>= (port % 16) << 1;
-	return (speed & 0x3);
-}
-
-inline u32 rtl839x_get_mac_link_spd_sts(int port)
-{
-	int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
-	u32 speed = sw_r32(r);
-
-	speed >>= (port % 16) << 1;
-	return (speed & 0x3);
-}
-
-
-inline u32 rtl930x_get_mac_link_spd_sts(int port)
-{
-	int r = RTL930X_MAC_LINK_SPD_STS + ((port / 10) << 2);
-	u32 speed = sw_r32(r);
-
-	speed >>= (port % 10) * 3;
-	return (speed & 0x7);
-}
-
-inline u32 rtl931x_get_mac_link_spd_sts(int port)
-{
-	int r = RTL931X_MAC_LINK_SPD_STS + ((port >> 3) << 2);
-	u32 speed = sw_r32(r);
-
-	speed >>= (port % 8) << 2;
-	return (speed & 0xf);
-}
-
-inline u32 rtl838x_get_mac_rx_pause_sts(int port)
-{
-	return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port));
-}
-
-inline u32 rtl839x_get_mac_rx_pause_sts(int p)
-{
-	return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
-}
-
-inline u32 rtl930x_get_mac_rx_pause_sts(int port)
-{
-	return (sw_r32(RTL930X_MAC_RX_PAUSE_STS) & (1 << port));
-}
-
-inline u32 rtl931x_get_mac_rx_pause_sts(int p)
-{
-	return (sw_r32(RTL931X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
-}
-
-inline u32 rtl838x_get_mac_tx_pause_sts(int port)
-{
-	return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port));
-}
-
-inline u32 rtl839x_get_mac_tx_pause_sts(int p)
-{
-	return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
-}
-
-inline u32 rtl930x_get_mac_tx_pause_sts(int port)
-{
-	return (sw_r32(RTL930X_MAC_TX_PAUSE_STS) & (1 << port));
-}
-
-inline u32 rtl931x_get_mac_tx_pause_sts(int p)
-{
-	return (sw_r32(RTL931X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
-}
-
-struct p_hdr;
-struct dsa_tag;
-
-struct rtl838x_reg {
-	irqreturn_t (*net_irq)(int irq, void *dev_id);
-	int (*mac_port_ctrl)(int port);
-	int dma_if_intr_sts;
-	int dma_if_intr_msk;
-	int dma_if_intr_rx_runout_sts;
-	int dma_if_intr_rx_done_sts;
-	int dma_if_intr_tx_done_sts;
-	int dma_if_intr_rx_runout_msk;
-	int dma_if_intr_rx_done_msk;
-	int dma_if_intr_tx_done_msk;
-	int l2_ntfy_if_intr_sts;
-	int l2_ntfy_if_intr_msk;
-	int dma_if_ctrl;
-	int mac_force_mode_ctrl;
-	int dma_rx_base;
-	int dma_tx_base;
-	int (*dma_if_rx_ring_size)(int ring);
-	int (*dma_if_rx_ring_cntr)(int ring);
-	int dma_if_rx_cur;
-	int rst_glb_ctrl;
-	u32 (*get_mac_link_sts)(int port);
-	u32 (*get_mac_link_dup_sts)(int port);
-	u32 (*get_mac_link_spd_sts)(int port);
-	u32 (*get_mac_rx_pause_sts)(int port);
-	u32 (*get_mac_tx_pause_sts)(int port);
-	int mac;
-	int l2_tbl_flush_ctrl;
-	void (*update_cntr)(int r, int work_done);
-	void (*create_tx_header)(struct p_hdr *h, int dest_port, int prio);
-	bool (*decode_tag)(struct p_hdr *h, struct dsa_tag *tag);
-};
-
-int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
-int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
-int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
-int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
-int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val);
-int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
-int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val);
-int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
-void rtl9300_sds_power(int sds_num, int val);
-
-#endif /* _RTL838X_ETH_H */
diff --git a/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.c
deleted file mode 100644
index 3e187228a9..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.c
+++ /dev/null
@@ -1,1983 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/* Realtek RTL838X Ethernet MDIO interface driver
- *
- * Copyright (C) 2020 B. Koblitz
- */
-
-#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/phy.h>
-#include <linux/netdevice.h>
-#include <linux/firmware.h>
-#include <linux/crc32.h>
-
-#include <asm/mach-rtl838x/mach-rtl83xx.h>
-#include "rtl83xx-phy.h"
-
-
-extern struct rtl83xx_soc_info soc_info;
-extern struct mutex smi_lock;
-
-/*
- * This lock protects the state of the SoC automatically polling the PHYs over the SMI
- * bus to detect e.g. link and media changes. For operations on the PHYs such as
- * patching or other configuration changes such as EEE, polling needs to be disabled
- * since otherwise these operations may fails or lead to unpredictable results.
- */
-DEFINE_MUTEX(poll_lock);
-
-static const struct firmware rtl838x_8380_fw;
-static const struct firmware rtl838x_8214fc_fw;
-static const struct firmware rtl838x_8218b_fw;
-
-int rtl838x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
-int rtl838x_write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val);
-int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
-int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val);
-int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
-int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val);
-int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
-int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val);
-
-static int read_phy(u32 port, u32 page, u32 reg, u32 *val)
-{	switch (soc_info.family) {
-	case RTL8380_FAMILY_ID:
-		return rtl838x_read_phy(port, page, reg, val);
-	case RTL8390_FAMILY_ID:
-		return rtl839x_read_phy(port, page, reg, val);
-	case RTL9300_FAMILY_ID:
-		return rtl930x_read_phy(port, page, reg, val);
-	case RTL9310_FAMILY_ID:
-		return rtl931x_read_phy(port, page, reg, val);
-	}
-	return -1;
-}
-
-static int write_phy(u32 port, u32 page, u32 reg, u32 val)
-{
-	switch (soc_info.family) {
-	case RTL8380_FAMILY_ID:
-		return rtl838x_write_phy(port, page, reg, val);
-	case RTL8390_FAMILY_ID:
-		return rtl839x_write_phy(port, page, reg, val);
-	case RTL9300_FAMILY_ID:
-		return rtl930x_write_phy(port, page, reg, val);
-	case RTL9310_FAMILY_ID:
-		return rtl931x_write_phy(port, page, reg, val);
-	}
-	return -1;
-}
-
-static int read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
-{
-	switch (soc_info.family) {
-	case RTL8380_FAMILY_ID:
-		return rtl838x_read_mmd_phy(port, devnum, regnum, val);
-	case RTL8390_FAMILY_ID:
-		return rtl839x_read_mmd_phy(port, devnum, regnum, val);
-	case RTL9300_FAMILY_ID:
-		return rtl930x_read_mmd_phy(port, devnum, regnum, val);
-	case RTL9310_FAMILY_ID:
-		return rtl931x_read_mmd_phy(port, devnum, regnum, val);
-	}
-	return -1;
-}
-
-int write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val)
-{
-	switch (soc_info.family) {
-	case RTL8380_FAMILY_ID:
-		return rtl838x_write_mmd_phy(port, devnum, reg, val);
-	case RTL8390_FAMILY_ID:
-		return rtl839x_write_mmd_phy(port, devnum, reg, val);
-	case RTL9300_FAMILY_ID:
-		return rtl930x_write_mmd_phy(port, devnum, reg, val);
-	case RTL9310_FAMILY_ID:
-		return rtl931x_write_mmd_phy(port, devnum, reg, val);
-	}
-	return -1;
-}
-
-static u64 disable_polling(int port)
-{
-	u64 saved_state;
-
-	mutex_lock(&poll_lock);
-
-	switch (soc_info.family) {
-	case RTL8380_FAMILY_ID:
-		saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
-		sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
-		break;
-	case RTL8390_FAMILY_ID:
-		saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
-		saved_state <<= 32;
-		saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
-		sw_w32_mask(BIT(port % 32), 0,
-			    RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
-		break;
-	case RTL9300_FAMILY_ID:
-		saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
-		sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
-		break;
-	case RTL9310_FAMILY_ID:
-		pr_warn("%s not implemented for RTL931X\n", __func__);
-		break;
-	}
-
-	mutex_unlock(&poll_lock);
-
-	return saved_state;
-}
-
-static int resume_polling(u64 saved_state)
-{
-	mutex_lock(&poll_lock);
-
-	switch (soc_info.family) {
-	case RTL8380_FAMILY_ID:
-		sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
-		break;
-	case RTL8390_FAMILY_ID:
-		sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
-		sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
-		break;
-	case RTL9300_FAMILY_ID:
-		sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
-		break;
-	case RTL9310_FAMILY_ID:
-		pr_warn("%s not implemented for RTL931X\n", __func__);
-		break;
-	}
-
-	mutex_unlock(&poll_lock);
-
-	return 0;
-}
-
-static void rtl8380_int_phy_on_off(int mac, bool on)
-{
-	u32 val;
-
-	read_phy(mac, 0, 0, &val);
-	if (on)
-		write_phy(mac, 0, 0, val & ~BIT(11));
-	else
-		write_phy(mac, 0, 0, val | BIT(11));
-}
-
-static void rtl8380_rtl8214fc_on_off(int mac, bool on)
-{
-	u32 val;
-
-	/* fiber ports */
-	write_phy(mac, 4095, 30, 3);
-	read_phy(mac, 0, 16, &val);
-	if (on)
-		write_phy(mac, 0, 16, val & ~BIT(11));
-	else
-		write_phy(mac, 0, 16, val | BIT(11));
-
-	/* copper ports */
-	write_phy(mac, 4095, 30, 1);
-	read_phy(mac, 0, 16, &val);
-	if (on)
-		write_phy(mac, 0xa40, 16, val & ~BIT(11));
-	else
-		write_phy(mac, 0xa40, 16, val | BIT(11));
-}
-
-static void rtl8380_phy_reset(int mac)
-{
-	u32 val;
-
-	read_phy(mac, 0, 0, &val);
-	write_phy(mac, 0, 0, val | BIT(15));
-}
-
-/*
- * Reset the SerDes by powering it off and set a new operations mode
- * of the SerDes. 0x1f is off. Other modes are
- * 0x01: QSGMII		0x04: 1000BX_FIBER	0x05: FIBER100
- * 0x06: QSGMII		0x09: RSGMII		0x0d: USXGMII
- * 0x10: XSGMII		0x12: HISGMII		0x16: 2500Base_X
- * 0x17: RXAUI_LITE	0x19: RXAUI_PLUS	0x1a: 10G Base-R
- * 0x1b: 10GR1000BX_AUTO			0x1f: OFF
- */
-void rtl9300_sds_rst(int sds_num, u32 mode)
-{
-	// The access registers for SDS_MODE_SEL and the LSB for each SDS within
-	u16 regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
-		       0x02A4, 0x02A4, 0x0198, 0x0198 };
-	u8  lsb[]  = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
-
-	pr_info("SerDes: %s %d\n", __func__, mode);
-	if (sds_num < 0 || sds_num > 11) {
-		pr_err("Wrong SerDes number: %d\n", sds_num);
-		return;
-	}
-
-	sw_w32_mask(0x1f << lsb[sds_num], 0x1f << lsb[sds_num], regs[sds_num]);
-	mdelay(10);
-
-	sw_w32_mask(0x1f << lsb[sds_num], mode << lsb[sds_num], regs[sds_num]);
-	mdelay(10);
-
-	pr_info("SDS: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n",
-		sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
-}
-
-/*
- * On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
- * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
- */
-int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
-{
-	int offset = 0;
-	int reg;
-	u32 val;
-
-	if (phy_addr == 49)
-		offset = 0x100;
-
-	/*
-	 * For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
-	 * which would otherwise read as 0.
-	 */
-	if (soc_info.id == 0x8393) {
-		if (phy_reg == 2)
-			return 0x1c;
-		if (phy_reg == 3)
-			return 0x8393;
-	}
-
-	/*
-	 * Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
-	 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
-	 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
-	 * one 32 bit register.
-	 */
-	reg = (phy_reg << 1) & 0xfc;
-	val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
-
-	if (phy_reg & 1)
-		val = (val >> 16) & 0xffff;
-	else
-		val &= 0xffff;
-	return val;
-}
-
-/*
- * On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
- * register which simulates commands to an internal MDIO bus.
- */
-int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
-{
-	int i;
-	u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
-
-	pr_info("%s: phy_addr %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
-	sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
-
-	for (i = 0; i < 100; i++) {
-		if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
-			break;
-		mdelay(1);
-	}
-
-	if (i >= 100)
-		return -EIO;
-
-	pr_info("%s: returning %04x\n", __func__, sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff);
-	return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
-}
-
-int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
-{
-	int i;
-	u32 cmd;
-
-	sw_w32(v, RTL930X_SDS_INDACS_DATA);
-	cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
-
-	for (i = 0; i < 100; i++) {
-		if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
-			break;
-		mdelay(1);
-	}
-
-	if (i >= 100)
-		return -EIO;
-
-	return 0;
-}
-
-/*
- * On the RTL838x SoCs, the internal SerDes is accessed through direct access to
- * standard PHY registers, where a 32 bit register holds a 16 bit word as found
- * in a standard page 0 of a PHY
- */
-int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
-{
-	int offset = 0;
-	u32 val;
-
-	if (phy_addr == 26)
-		offset = 0x100;
-	val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
-
-	return val;
-}
-
-int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
-{
-	int offset = 0;
-	int reg;
-	u32 val;
-
-	if (phy_addr == 49)
-		offset = 0x100;
-
-	reg = (phy_reg << 1) & 0xfc;
-	val = v;
-	if (phy_reg & 1) {
-		val = val << 16;
-		sw_w32_mask(0xffff0000, val,
-			    RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
-	} else {
-		sw_w32_mask(0xffff, val,
-			    RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
-	}
-
-	return 0;
-}
-
-/* Read the link and speed status of the 2 internal SGMII/1000Base-X
- * ports of the RTL838x SoCs
- */
-static int rtl8380_read_status(struct phy_device *phydev)
-{
-	int err;
-
-	err = genphy_read_status(phydev);
-
-	if (phydev->link) {
-		phydev->speed = SPEED_1000;
-		phydev->duplex = DUPLEX_FULL;
-	}
-
-	return err;
-}
-
-/* Read the link and speed status of the 2 internal SGMII/1000Base-X
- * ports of the RTL8393 SoC
- */
-static int rtl8393_read_status(struct phy_device *phydev)
-{
-	int offset = 0;
-	int err;
-	int phy_addr = phydev->mdio.addr;
-	u32 v;
-
-	err = genphy_read_status(phydev);
-	if (phy_addr == 49)
-		offset = 0x100;
-
-	if (phydev->link) {
-		phydev->speed = SPEED_100;
-		/* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
-		 * PHY registers
-		 */
-		v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
-		if (!(v & (1 << 13)) && (v & (1 << 6)))
-			phydev->speed = SPEED_1000;
-		phydev->duplex = DUPLEX_FULL;
-	}
-
-	return err;
-}
-
-static int rtl8226_read_page(struct phy_device *phydev)
-{
-	return __phy_read(phydev, 0x1f);
-}
-
-static int rtl8226_write_page(struct phy_device *phydev, int page)
-{
-	return __phy_write(phydev, 0x1f, page);
-}
-
-static int rtl8226_read_status(struct phy_device *phydev)
-{
-	int ret = 0, i;
-	u32 val;
-	int port = phydev->mdio.addr;
-
-// TODO: ret = genphy_read_status(phydev);
-// 	if (ret < 0) {
-// 		pr_info("%s: genphy_read_status failed\n", __func__);
-// 		return ret;
-// 	}
-
-	// Link status must be read twice
-	for (i = 0; i < 2; i++) {
-		read_mmd_phy(port, MMD_VEND2, 0xA402, &val);
-	}
-	phydev->link = val & BIT(2) ? 1 : 0;
-	if (!phydev->link)
-		goto out;
-
-	// Read duplex status
-	ret = read_mmd_phy(port, MMD_VEND2, 0xA434, &val);
-	if (ret)
-		goto out;
-	phydev->duplex = !!(val & BIT(3));
-
-	// Read speed
-	ret = read_mmd_phy(port, MMD_VEND2, 0xA434, &val);
-	switch (val & 0x0630) {
-	case 0x0000:
-		phydev->speed = SPEED_10;
-		break;
-	case 0x0010:
-		phydev->speed = SPEED_100;
-		break;
-	case 0x0020:
-		phydev->speed = SPEED_1000;
-		break;
-	case 0x0200:
-		phydev->speed = SPEED_10000;
-		break;
-	case 0x0210:
-		phydev->speed = SPEED_2500;
-		break;
-	case 0x0220:
-		phydev->speed = SPEED_5000;
-		break;
-	default:
-		break;
-	}
-out:
-	return ret;
-}
-
-static int rtl8226_advertise_aneg(struct phy_device *phydev)
-{
-	int ret = 0;
-	u32 v;
-	int port = phydev->mdio.addr;
-
-	pr_info("In %s\n", __func__);
-
-	ret = read_mmd_phy(port, MMD_AN, 16, &v);
-	if (ret)
-		goto out;
-
-	v |= BIT(5); // HD 10M
-	v |= BIT(6); // FD 10M
-	v |= BIT(7); // HD 100M
-	v |= BIT(8); // FD 100M
-
-	ret = write_mmd_phy(port, MMD_AN, 16, v);
-
-	// Allow 1GBit
-	ret = read_mmd_phy(port, MMD_VEND2, 0xA412, &v);
-	if (ret)
-		goto out;
-	v |= BIT(9); // FD 1000M
-
-	ret = write_mmd_phy(port, MMD_VEND2, 0xA412, v);
-	if (ret)
-		goto out;
-
-	// Allow 2.5G
-	ret = read_mmd_phy(port, MMD_AN, 32, &v);
-	if (ret)
-		goto out;
-
-	v |= BIT(7);
-	ret = write_mmd_phy(port, MMD_AN, 32, v);
-
-out:
-	return ret;
-}
-
-static int rtl8226_config_aneg(struct phy_device *phydev)
-{
-	int ret = 0;
-	u32 v;
-	int port = phydev->mdio.addr;
-
-	pr_info("In %s\n", __func__);
-	if (phydev->autoneg == AUTONEG_ENABLE) {
-		ret = rtl8226_advertise_aneg(phydev);
-		if (ret)
-			goto out;
-		// AutoNegotiationEnable
-		ret = read_mmd_phy(port, MMD_AN, 0, &v);
-		if (ret)
-			goto out;
-
-		v |= BIT(12); // Enable AN
-		ret = write_mmd_phy(port, MMD_AN, 0, v);
-		if (ret)
-			goto out;
-
-		// RestartAutoNegotiation
-		ret = read_mmd_phy(port, MMD_VEND2, 0xA400, &v);
-		if (ret)
-			goto out;
-		v |= BIT(9);
-
-		ret = write_mmd_phy(port, MMD_VEND2, 0xA400, v);
-	}
-
-	pr_info("%s: Ret is already: %d\n", __func__, ret);
-//	TODO: ret = __genphy_config_aneg(phydev, ret);
-
-out:
-	pr_info("%s: And ret is now: %d\n", __func__, ret);
-	return ret;
-}
-
-static int rtl8226_get_eee(struct phy_device *phydev,
-				     struct ethtool_eee *e)
-{
-	u32 val;
-	int addr = phydev->mdio.addr;
-
-	pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
-
-	read_mmd_phy(addr, MMD_AN, 60, &val);
-	if (e->eee_enabled) {
-		e->eee_enabled = !!(val & BIT(1));
-		if (!e->eee_enabled) {
-			read_mmd_phy(addr, MMD_AN, 62, &val);
-			e->eee_enabled = !!(val & BIT(0));
-		}
-	}
-	pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
-
-	return 0;
-}
-
-static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
-{
-	int port = phydev->mdio.addr;
-	u64 poll_state;
-	bool an_enabled;
-	u32 val;
-
-	pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
-
-	poll_state = disable_polling(port);
-
-	// Remember aneg state
-	read_mmd_phy(port, MMD_AN, 0, &val);
-	an_enabled = !!(val & BIT(12));
-
-	// Setup 100/1000MBit
-	read_mmd_phy(port, MMD_AN, 60, &val);
-	if (e->eee_enabled)
-		val |= 0x6;
-	else
-		val &= 0x6;
-	write_mmd_phy(port, MMD_AN, 60, val);
-
-	// Setup 2.5GBit
-	read_mmd_phy(port, MMD_AN, 62, &val);
-	if (e->eee_enabled)
-		val |= 0x1;
-	else
-		val &= 0x1;
-	write_mmd_phy(port, MMD_AN, 62, val);
-
-	// RestartAutoNegotiation
-	read_mmd_phy(port, MMD_VEND2, 0xA400, &val);
-	val |= BIT(9);
-	write_mmd_phy(port, MMD_VEND2, 0xA400, val);
-
-	resume_polling(poll_state);
-
-	return 0;
-}
-
-static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
-					    const struct firmware *fw,
-					    const char *name)
-{
-	struct device *dev = &phydev->mdio.dev;
-	int err;
-	struct fw_header *h;
-	uint32_t checksum, my_checksum;
-
-	err = request_firmware(&fw, name, dev);
-	if (err < 0)
-		goto out;
-
-	if (fw->size < sizeof(struct fw_header)) {
-		pr_err("Firmware size too small.\n");
-		err = -EINVAL;
-		goto out;
-	}
-
-	h = (struct fw_header *) fw->data;
-	pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
-
-	if (h->magic != 0x83808380) {
-		pr_err("Wrong firmware file: MAGIC mismatch.\n");
-		goto out;
-	}
-
-	checksum = h->checksum;
-	h->checksum = 0;
-	my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
-	if (checksum != my_checksum) {
-		pr_err("Firmware checksum mismatch.\n");
-		err = -EINVAL;
-		goto out;
-	}
-	h->checksum = checksum;
-
-	return h;
-out:
-	dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
-	return NULL;
-}
-
-static int rtl8390_configure_generic(struct phy_device *phydev)
-{
-	u32 val, phy_id;
-	int mac = phydev->mdio.addr;
-
-	read_phy(mac, 0, 2, &val);
-	phy_id = val << 16;
-	read_phy(mac, 0, 3, &val);
-	phy_id |= val;
-	pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
-
-	/* Read internal PHY ID */
-	write_phy(mac, 31, 27, 0x0002);
-	read_phy(mac, 31, 28, &val);
-
-	/* Internal RTL8218B, version 2 */
-	phydev_info(phydev, "Detected unknown %x\n", val);
-	return 0;
-}
-
-static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
-{
-	u32 val, phy_id;
-	int i, p, ipd_flag;
-	int mac = phydev->mdio.addr;
-	struct fw_header *h;
-	u32 *rtl838x_6275B_intPhy_perport;
-	u32 *rtl8218b_6276B_hwEsd_perport;
-
-
-	read_phy(mac, 0, 2, &val);
-	phy_id = val << 16;
-	read_phy(mac, 0, 3, &val);
-	phy_id |= val;
-	pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
-
-	/* Read internal PHY ID */
-	write_phy(mac, 31, 27, 0x0002);
-	read_phy(mac, 31, 28, &val);
-	if (val != 0x6275) {
-		phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
-		return -1;
-	}
-
-	/* Internal RTL8218B, version 2 */
-	phydev_info(phydev, "Detected internal RTL8218B\n");
-
-	h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
-	if (!h)
-		return -1;
-
-	if (h->phy != 0x83800000) {
-		phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
-		return -1;
-	}
-
-	rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header)
-			+ h->parts[8].start;
-
-	rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header)
-			+ h->parts[9].start;
-
-	if (sw_r32(RTL838X_DMY_REG31) == 0x1)
-		ipd_flag = 1;
-
-	read_phy(mac, 0, 0, &val);
-	if (val & (1 << 11))
-		rtl8380_int_phy_on_off(mac, true);
-	else
-		rtl8380_phy_reset(mac);
-	msleep(100);
-
-	/* Ready PHY for patch */
-	for (p = 0; p < 8; p++) {
-		write_phy(mac + p, 0xfff, 0x1f, 0x0b82);
-		write_phy(mac + p, 0xfff, 0x10, 0x0010);
-	}
-	msleep(500);
-	for (p = 0; p < 8; p++) {
-		for (i = 0; i < 100 ; i++) {
-			read_phy(mac + p, 0x0b80, 0x10, &val);
-			if (val & 0x40)
-				break;
-		}
-		if (i >= 100) {
-			phydev_err(phydev,
-				   "ERROR: Port %d not ready for patch.\n",
-				   mac + p);
-			return -1;
-		}
-	}
-	for (p = 0; p < 8; p++) {
-		i = 0;
-		while (rtl838x_6275B_intPhy_perport[i * 2]) {
-			write_phy(mac + p, 0xfff,
-				rtl838x_6275B_intPhy_perport[i * 2],
-				rtl838x_6275B_intPhy_perport[i * 2 + 1]);
-			i++;
-		}
-		i = 0;
-		while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
-			write_phy(mac + p, 0xfff,
-				rtl8218b_6276B_hwEsd_perport[i * 2],
-				rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
-			i++;
-		}
-	}
-	return 0;
-}
-
-static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
-{
-	u32 val, ipd, phy_id;
-	int i, l;
-	int mac = phydev->mdio.addr;
-	struct fw_header *h;
-	u32 *rtl8380_rtl8218b_perchip;
-	u32 *rtl8218B_6276B_rtl8380_perport;
-	u32 *rtl8380_rtl8218b_perport;
-
-	if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
-		phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
-		return -1;
-	}
-	read_phy(mac, 0, 2, &val);
-	phy_id = val << 16;
-	read_phy(mac, 0, 3, &val);
-	phy_id |= val;
-	pr_info("Phy on MAC %d: %x\n", mac, phy_id);
-
-	/* Read internal PHY ID */
-	write_phy(mac, 31, 27, 0x0002);
-	read_phy(mac, 31, 28, &val);
-	if (val != 0x6276) {
-		phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
-		return -1;
-	}
-	phydev_info(phydev, "Detected external RTL8218B\n");
-
-	h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
-	if (!h)
-		return -1;
-
-	if (h->phy != 0x8218b000) {
-		phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
-		return -1;
-	}
-
-	rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header)
-			+ h->parts[0].start;
-
-	rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header)
-			+ h->parts[1].start;
-
-	rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header)
-			+ h->parts[2].start;
-
-	read_phy(mac, 0, 0, &val);
-	if (val & (1 << 11))
-		rtl8380_int_phy_on_off(mac, true);
-	else
-		rtl8380_phy_reset(mac);
-	msleep(100);
-
-	/* Get Chip revision */
-	write_phy(mac, 0xfff, 0x1f, 0x0);
-	write_phy(mac,  0xfff, 0x1b, 0x4);
-	read_phy(mac, 0xfff, 0x1c, &val);
-
-	i = 0;
-	while (rtl8380_rtl8218b_perchip[i * 3]
-		&& rtl8380_rtl8218b_perchip[i * 3 + 1]) {
-		write_phy(mac + rtl8380_rtl8218b_perchip[i * 3],
-					  0xfff, rtl8380_rtl8218b_perchip[i * 3 + 1],
-					  rtl8380_rtl8218b_perchip[i * 3 + 2]);
-		i++;
-	}
-
-	/* Enable PHY */
-	for (i = 0; i < 8; i++) {
-		write_phy(mac + i, 0xfff, 0x1f, 0x0000);
-		write_phy(mac + i, 0xfff, 0x00, 0x1140);
-	}
-	mdelay(100);
-
-	/* Request patch */
-	for (i = 0; i < 8; i++) {
-		write_phy(mac + i,  0xfff, 0x1f, 0x0b82);
-		write_phy(mac + i,  0xfff, 0x10, 0x0010);
-	}
-	mdelay(300);
-
-	/* Verify patch readiness */
-	for (i = 0; i < 8; i++) {
-		for (l = 0; l < 100; l++) {
-			read_phy(mac + i, 0xb80, 0x10, &val);
-			if (val & 0x40)
-				break;
-		}
-		if (l >= 100) {
-			phydev_err(phydev, "Could not patch PHY\n");
-			return -1;
-		}
-	}
-
-	/* Use Broadcast ID method for patching */
-	write_phy(mac, 0xfff, 0x1f, 0x0000);
-	write_phy(mac, 0xfff, 0x1d, 0x0008);
-	write_phy(mac, 0xfff, 0x1f, 0x0266);
-	write_phy(mac, 0xfff, 0x16, 0xff00 + mac);
-	write_phy(mac, 0xfff, 0x1f, 0x0000);
-	write_phy(mac, 0xfff, 0x1d, 0x0000);
-	mdelay(1);
-
-	write_phy(mac, 0xfff, 30, 8);
-	write_phy(mac, 0x26e, 17, 0xb);
-	write_phy(mac, 0x26e, 16, 0x2);
-	mdelay(1);
-	read_phy(mac, 0x26e, 19, &ipd);
-	write_phy(mac, 0, 30, 0);
-	ipd = (ipd >> 4) & 0xf;
-
-	i = 0;
-	while (rtl8218B_6276B_rtl8380_perport[i * 2]) {
-		write_phy(mac, 0xfff, rtl8218B_6276B_rtl8380_perport[i * 2],
-				  rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
-		i++;
-	}
-
-	/*Disable broadcast ID*/
-	write_phy(mac, 0xfff, 0x1f, 0x0000);
-	write_phy(mac, 0xfff, 0x1d, 0x0008);
-	write_phy(mac, 0xfff, 0x1f, 0x0266);
-	write_phy(mac, 0xfff, 0x16, 0x00 + mac);
-	write_phy(mac, 0xfff, 0x1f, 0x0000);
-	write_phy(mac, 0xfff, 0x1d, 0x0000);
-	mdelay(1);
-
-	return 0;
-}
-
-static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
-{
-	int addr = phydev->mdio.addr;
-
-	/* Both the RTL8214FC and the external RTL8218B have the same
-	 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
-	 * at PHY IDs 0-7, while the RTL8214FC must be attached via
-	 * the pair of SGMII/1000Base-X with higher PHY-IDs
-	 */
-	if (soc_info.family == RTL8380_FAMILY_ID)
-		return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
-	else
-		return phydev->phy_id == PHY_ID_RTL8218B_E;
-}
-
-static int rtl8218b_read_mmd(struct phy_device *phydev,
-				     int devnum, u16 regnum)
-{
-	int ret;
-	u32 val;
-	int addr = phydev->mdio.addr;
-
-	ret = read_mmd_phy(addr, devnum, regnum, &val);
-	if (ret)
-		return ret;
-	return val;
-}
-
-static int rtl8218b_write_mmd(struct phy_device *phydev,
-				      int devnum, u16 regnum, u16 val)
-{
-	int addr = phydev->mdio.addr;
-
-	return rtl838x_write_mmd_phy(addr, devnum, regnum, val);
-}
-
-static int rtl8226_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
-{
-	int port = phydev->mdio.addr;  // the SoC translates port addresses to PHY addr
-	int err;
-	u32 val;
-
-	err = read_mmd_phy(port, devnum, regnum, &val);
-	if (err)
-		return err;
-	return val;
-}
-
-static int rtl8226_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, u16 val)
-{
-	int port = phydev->mdio.addr; // the SoC translates port addresses to PHY addr
-
-	return write_mmd_phy(port, devnum, regnum, val);
-}
-
-static void rtl8380_rtl8214fc_media_set(int mac, bool set_fibre)
-{
-	int base = mac - (mac % 4);
-	static int reg[] = {16, 19, 20, 21};
-	int val, media, power;
-
-	pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
-	write_phy(base, 0xfff, 29, 8);
-	read_phy(base, 0x266, reg[mac % 4], &val);
-
-	media = (val >> 10) & 0x3;
-	pr_info("Current media %x\n", media);
-	if (media & 0x2) {
-		pr_info("Powering off COPPER\n");
-		write_phy(base, 0xfff, 29, 1);
-		/* Ensure power is off */
-		read_phy(base, 0xa40, 16, &power);
-		if (!(power & (1 << 11)))
-			write_phy(base, 0xa40, 16, power | (1 << 11));
-	} else {
-		pr_info("Powering off FIBRE");
-		write_phy(base, 0xfff, 29, 3);
-		/* Ensure power is off */
-		read_phy(base, 0xa40, 16, &power);
-		if (!(power & (1 << 11)))
-			write_phy(base, 0xa40, 16, power | (1 << 11));
-	}
-
-	if (set_fibre) {
-		val |= 1 << 10;
-		val &= ~(1 << 11);
-	} else {
-		val |= 1 << 10;
-		val |= 1 << 11;
-	}
-	write_phy(base, 0xfff, 29, 8);
-	write_phy(base, 0x266, reg[mac % 4], val);
-	write_phy(base, 0xfff, 29, 0);
-
-	if (set_fibre) {
-		pr_info("Powering on FIBRE");
-		write_phy(base, 0xfff, 29, 3);
-		/* Ensure power is off */
-		read_phy(base, 0xa40, 16, &power);
-		if (power & (1 << 11))
-			write_phy(base, 0xa40, 16, power & ~(1 << 11));
-	} else {
-		pr_info("Powering on COPPER\n");
-		write_phy(base, 0xfff, 29, 1);
-		/* Ensure power is off */
-		read_phy(base, 0xa40, 16, &power);
-		if (power & (1 << 11))
-			write_phy(base, 0xa40, 16, power & ~(1 << 11));
-	}
-
-	write_phy(base, 0xfff, 29, 0);
-}
-
-static bool rtl8380_rtl8214fc_media_is_fibre(int mac)
-{
-	int base = mac - (mac % 4);
-	static int reg[] = {16, 19, 20, 21};
-	u32 val;
-
-	write_phy(base, 0xfff, 29, 8);
-	read_phy(base, 0x266, reg[mac % 4], &val);
-	write_phy(base, 0xfff, 29, 0);
-	if (val & (1 << 11))
-		return false;
-	return true;
-}
-
-static int rtl8214fc_set_port(struct phy_device *phydev, int port)
-{
-	bool is_fibre = (port == PORT_FIBRE ? true : false);
-	int addr = phydev->mdio.addr;
-
-	pr_debug("%s port %d to %d\n", __func__, addr, port);
-
-	rtl8380_rtl8214fc_media_set(addr, is_fibre);
-	return 0;
-}
-
-static int rtl8214fc_get_port(struct phy_device *phydev)
-{
-	int addr = phydev->mdio.addr;
-
-	pr_debug("%s: port %d\n", __func__, addr);
-	if (rtl8380_rtl8214fc_media_is_fibre(addr))
-		return PORT_FIBRE;
-	return PORT_MII;
-}
-
-/*
- * Enable EEE on the RTL8218B PHYs
- * The method used is not the preferred way (which would be based on the MAC-EEE state,
- * but the only way that works since the kernel first enables EEE in the MAC
- * and then sets up the PHY. The MAC-based approach would require the oppsite.
- */
-void rtl8218d_eee_set(int port, bool enable)
-{
-	u32 val;
-	bool an_enabled;
-
-	pr_debug("In %s %d, enable %d\n", __func__, port, enable);
-	/* Set GPHY page to copper */
-	write_phy(port, 0xa42, 30, 0x0001);
-
-	read_phy(port, 0, 0, &val);
-	an_enabled = val & BIT(12);
-
-	/* Enable 100M (bit 1) / 1000M (bit 2) EEE */
-	read_mmd_phy(port, 7, 60, &val);
-	val |= BIT(2) | BIT(1);
-	write_mmd_phy(port, 7, 60, enable ? 0x6 : 0);
-
-	/* 500M EEE ability */
-	read_phy(port, 0xa42, 20, &val);
-	if (enable)
-		val |= BIT(7);
-	else
-		val &= ~BIT(7);
-	write_phy(port, 0xa42, 20, val);
-
-	/* Restart AN if enabled */
-	if (an_enabled) {
-		read_phy(port, 0, 0, &val);
-		val |= BIT(9);
-		write_phy(port, 0, 0, val);
-	}
-
-	/* GPHY page back to auto*/
-	write_phy(port, 0xa42, 30, 0);
-}
-
-static int rtl8218b_get_eee(struct phy_device *phydev,
-				     struct ethtool_eee *e)
-{
-	u32 val;
-	int addr = phydev->mdio.addr;
-
-	pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
-
-	/* Set GPHY page to copper */
-	write_phy(addr, 0xa42, 29, 0x0001);
-
-	read_phy(addr, 7, 60, &val);
-	if (e->eee_enabled) {
-		// Verify vs MAC-based EEE
-		e->eee_enabled = !!(val & BIT(7));
-		if (!e->eee_enabled) {
-			read_phy(addr, 0x0A43, 25, &val);
-			e->eee_enabled = !!(val & BIT(4));
-		}
-	}
-	pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
-
-	/* GPHY page to auto */
-	write_phy(addr, 0xa42, 29, 0x0000);
-
-	return 0;
-}
-
-static int rtl8218d_get_eee(struct phy_device *phydev,
-				     struct ethtool_eee *e)
-{
-	u32 val;
-	int addr = phydev->mdio.addr;
-
-	pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
-
-	/* Set GPHY page to copper */
-	write_phy(addr, 0xa42, 30, 0x0001);
-
-	read_phy(addr, 7, 60, &val);
-	if (e->eee_enabled)
-		e->eee_enabled = !!(val & BIT(7));
-	pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
-
-	/* GPHY page to auto */
-	write_phy(addr, 0xa42, 30, 0x0000);
-
-	return 0;
-}
-
-static int rtl8214fc_set_eee(struct phy_device *phydev,
-				     struct ethtool_eee *e)
-{
-	u32 poll_state;
-	int port = phydev->mdio.addr;
-	bool an_enabled;
-	u32 val;
-
-	pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled);
-
-	if (rtl8380_rtl8214fc_media_is_fibre(port)) {
-		netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port);
-		return -ENOTSUPP;
-	}
-
-	poll_state = disable_polling(port);
-
-	/* Set GPHY page to copper */
-	write_phy(port, 0xa42, 29, 0x0001);
-
-	// Get auto-negotiation status
-	read_phy(port, 0, 0, &val);
-	an_enabled = val & BIT(12);
-
-	pr_info("%s: aneg: %d\n", __func__, an_enabled);
-	read_phy(port, 0x0A43, 25, &val);
-	val &= ~BIT(5);  // Use MAC-based EEE
-	write_phy(port, 0x0A43, 25, val);
-
-	/* Enable 100M (bit 1) / 1000M (bit 2) EEE */
-	write_phy(port, 7, 60, e->eee_enabled ? 0x6 : 0);
-
-	/* 500M EEE ability */
-	read_phy(port, 0xa42, 20, &val);
-	if (e->eee_enabled)
-		val |= BIT(7);
-	else
-		val &= ~BIT(7);
-	write_phy(port, 0xa42, 20, val);
-
-	/* Restart AN if enabled */
-	if (an_enabled) {
-		pr_info("%s: doing aneg\n", __func__);
-		read_phy(port, 0, 0, &val);
-		val |= BIT(9);
-		write_phy(port, 0, 0, val);
-	}
-
-	/* GPHY page back to auto*/
-	write_phy(port, 0xa42, 29, 0);
-
-	resume_polling(poll_state);
-
-	return 0;
-}
-
-static int rtl8214fc_get_eee(struct phy_device *phydev,
-				      struct ethtool_eee *e)
-{
-	int addr = phydev->mdio.addr;
-
-	pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
-	if (rtl8380_rtl8214fc_media_is_fibre(addr)) {
-		netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
-		return -ENOTSUPP;
-	}
-
-	return rtl8218b_get_eee(phydev, e);
-}
-
-static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
-{
-	int port = phydev->mdio.addr;
-	u64 poll_state;
-	u32 val;
-	bool an_enabled;
-
-	pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
-
-	poll_state = disable_polling(port);
-
-	/* Set GPHY page to copper */
-	write_phy(port, 0, 30, 0x0001);
-	read_phy(port, 0, 0, &val);
-	an_enabled = val & BIT(12);
-
-	if (e->eee_enabled) {
-		/* 100/1000M EEE Capability */
-		write_phy(port, 0, 13, 0x0007);
-		write_phy(port, 0, 14, 0x003C);
-		write_phy(port, 0, 13, 0x4007);
-		write_phy(port, 0, 14, 0x0006);
-
-		read_phy(port, 0x0A43, 25, &val);
-		val |= BIT(4);
-		write_phy(port, 0x0A43, 25, val);
-	} else {
-		/* 100/1000M EEE Capability */
-		write_phy(port, 0, 13, 0x0007);
-		write_phy(port, 0, 14, 0x003C);
-		write_phy(port, 0, 13, 0x0007);
-		write_phy(port, 0, 14, 0x0000);
-
-		read_phy(port, 0x0A43, 25, &val);
-		val &= ~BIT(4);
-		write_phy(port, 0x0A43, 25, val);
-	}
-
-	/* Restart AN if enabled */
-	if (an_enabled) {
-		read_phy(port, 0, 0, &val);
-		val |= BIT(9);
-		write_phy(port, 0, 0, val);
-	}
-
-	/* GPHY page back to auto*/
-	write_phy(port, 0xa42, 30, 0);
-
-	pr_info("%s done\n", __func__);
-	resume_polling(poll_state);
-
-	return 0;
-}
-
-static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
-{
-	int addr = phydev->mdio.addr;
-	u64 poll_state;
-
-	pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
-
-	poll_state = disable_polling(addr);
-
-	rtl8218d_eee_set(addr, (bool) e->eee_enabled);
-
-	resume_polling(poll_state);
-
-	return 0;
-}
-
-static int rtl8214c_match_phy_device(struct phy_device *phydev)
-{
-	return phydev->phy_id == PHY_ID_RTL8214C;
-}
-
-static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
-{
-	u32 phy_id, val;
-	int mac = phydev->mdio.addr;
-
-	read_phy(mac, 0, 2, &val);
-	phy_id = val << 16;
-	read_phy(mac, 0, 3, &val);
-	phy_id |= val;
-	pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
-
-	phydev_info(phydev, "Detected external RTL8214C\n");
-
-	/* GPHY auto conf */
-	write_phy(mac, 0xa42, 29, 0);
-	return 0;
-}
-
-static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
-{
-	u32 phy_id, val, page = 0;
-	int i, l;
-	int mac = phydev->mdio.addr;
-	struct fw_header *h;
-	u32 *rtl8380_rtl8214fc_perchip;
-	u32 *rtl8380_rtl8214fc_perport;
-
-	read_phy(mac, 0, 2, &val);
-	phy_id = val << 16;
-	read_phy(mac, 0, 3, &val);
-	phy_id |= val;
-	pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
-
-	/* Read internal PHY id */
-	write_phy(mac, 0, 30, 0x0001);
-	write_phy(mac, 0, 31, 0x0a42);
-	write_phy(mac, 31, 27, 0x0002);
-	read_phy(mac, 31, 28, &val);
-	if (val != 0x6276) {
-		phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
-		return -1;
-	}
-	phydev_info(phydev, "Detected external RTL8214FC\n");
-
-	h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
-	if (!h)
-		return -1;
-
-	if (h->phy != 0x8214fc00) {
-		phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
-		return -1;
-	}
-
-	rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header)
-		   + h->parts[0].start;
-
-	rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header)
-		   + h->parts[1].start;
-
-	/* detect phy version */
-	write_phy(mac, 0xfff, 27, 0x0004);
-	read_phy(mac, 0xfff, 28, &val);
-
-	read_phy(mac, 0, 16, &val);
-	if (val & (1 << 11))
-		rtl8380_rtl8214fc_on_off(mac, true);
-	else
-		rtl8380_phy_reset(mac);
-
-	msleep(100);
-	write_phy(mac, 0, 30, 0x0001);
-
-	i = 0;
-	while (rtl8380_rtl8214fc_perchip[i * 3]
-	       && rtl8380_rtl8214fc_perchip[i * 3 + 1]) {
-		if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
-			page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
-		if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
-			read_phy(mac + rtl8380_rtl8214fc_perchip[i * 3], 0x260, 13, &val);
-			val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2]
-				& 0xe0ff);
-			write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3],
-					  0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
-		} else {
-			write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3],
-					  0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1],
-					  rtl8380_rtl8214fc_perchip[i * 3 + 2]);
-		}
-		i++;
-	}
-
-	/* Force copper medium */
-	for (i = 0; i < 4; i++) {
-		write_phy(mac + i, 0xfff, 0x1f, 0x0000);
-		write_phy(mac + i, 0xfff, 0x1e, 0x0001);
-	}
-
-	/* Enable PHY */
-	for (i = 0; i < 4; i++) {
-		write_phy(mac + i, 0xfff, 0x1f, 0x0000);
-		write_phy(mac + i, 0xfff, 0x00, 0x1140);
-	}
-	mdelay(100);
-
-	/* Disable Autosensing */
-	for (i = 0; i < 4; i++) {
-		for (l = 0; l < 100; l++) {
-			read_phy(mac + i, 0x0a42, 0x10, &val);
-			if ((val & 0x7) >= 3)
-				break;
-		}
-		if (l >= 100) {
-			phydev_err(phydev, "Could not disable autosensing\n");
-			return -1;
-		}
-	}
-
-	/* Request patch */
-	for (i = 0; i < 4; i++) {
-		write_phy(mac + i,  0xfff, 0x1f, 0x0b82);
-		write_phy(mac + i,  0xfff, 0x10, 0x0010);
-	}
-	mdelay(300);
-
-	/* Verify patch readiness */
-	for (i = 0; i < 4; i++) {
-		for (l = 0; l < 100; l++) {
-			read_phy(mac + i, 0xb80, 0x10, &val);
-			if (val & 0x40)
-				break;
-		}
-		if (l >= 100) {
-			phydev_err(phydev, "Could not patch PHY\n");
-			return -1;
-		}
-	}
-
-	/* Use Broadcast ID method for patching */
-	write_phy(mac, 0xfff, 0x1f, 0x0000);
-	write_phy(mac, 0xfff, 0x1d, 0x0008);
-	write_phy(mac, 0xfff, 0x1f, 0x0266);
-	write_phy(mac, 0xfff, 0x16, 0xff00 + mac);
-	write_phy(mac, 0xfff, 0x1f, 0x0000);
-	write_phy(mac, 0xfff, 0x1d, 0x0000);
-	mdelay(1);
-
-	i = 0;
-	while (rtl8380_rtl8214fc_perport[i * 2]) {
-		write_phy(mac, 0xfff, rtl8380_rtl8214fc_perport[i * 2],
-				  rtl8380_rtl8214fc_perport[i * 2 + 1]);
-		i++;
-	}
-
-	/*Disable broadcast ID*/
-	write_phy(mac, 0xfff, 0x1f, 0x0000);
-	write_phy(mac, 0xfff, 0x1d, 0x0008);
-	write_phy(mac, 0xfff, 0x1f, 0x0266);
-	write_phy(mac, 0xfff, 0x16, 0x00 + mac);
-	write_phy(mac, 0xfff, 0x1f, 0x0000);
-	write_phy(mac, 0xfff, 0x1d, 0x0000);
-	mdelay(1);
-
-	/* Auto medium selection */
-	for (i = 0; i < 4; i++) {
-		write_phy(mac + i, 0xfff, 0x1f, 0x0000);
-		write_phy(mac + i, 0xfff, 0x1e, 0x0000);
-	}
-
-	return 0;
-}
-
-static int rtl8214fc_match_phy_device(struct phy_device *phydev)
-{
-	int addr = phydev->mdio.addr;
-
-	return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
-}
-
-static int rtl8380_configure_serdes(struct phy_device *phydev)
-{
-	u32 v;
-	u32 sds_conf_value;
-	int i;
-	struct fw_header *h;
-	u32 *rtl8380_sds_take_reset;
-	u32 *rtl8380_sds_common;
-	u32 *rtl8380_sds01_qsgmii_6275b;
-	u32 *rtl8380_sds23_qsgmii_6275b;
-	u32 *rtl8380_sds4_fiber_6275b;
-	u32 *rtl8380_sds5_fiber_6275b;
-	u32 *rtl8380_sds_reset;
-	u32 *rtl8380_sds_release_reset;
-
-	phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
-
-	h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
-	if (!h)
-		return -1;
-
-	if (h->magic != 0x83808380) {
-		phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
-		return -1;
-	}
-
-	rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header)
-		   + h->parts[0].start;
-
-	rtl8380_sds_common = (void *)h + sizeof(struct fw_header)
-		   + h->parts[1].start;
-
-	rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
-		   + h->parts[2].start;
-
-	rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
-		   + h->parts[3].start;
-
-	rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header)
-		   + h->parts[4].start;
-
-	rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header)
-		   + h->parts[5].start;
-
-	rtl8380_sds_reset = (void *)h + sizeof(struct fw_header)
-		   + h->parts[6].start;
-
-	rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header)
-		   + h->parts[7].start;
-
-	/* Back up serdes power off value */
-	sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
-	pr_info("SDS power down value: %x\n", sds_conf_value);
-
-	/* take serdes into reset */
-	i = 0;
-	while (rtl8380_sds_take_reset[2 * i]) {
-		sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
-		i++;
-		udelay(1000);
-	}
-
-	/* apply common serdes patch */
-	i = 0;
-	while (rtl8380_sds_common[2 * i]) {
-		sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
-		i++;
-		udelay(1000);
-	}
-
-	/* internal R/W enable */
-	sw_w32(3, RTL838X_INT_RW_CTRL);
-
-	/* SerDes ports 4 and 5 are FIBRE ports */
-	sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
-
-	/* SerDes module settings, SerDes 0-3 are QSGMII */
-	v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
-	/* SerDes 4 and 5 are 1000BX FIBRE */
-	v |= 0x4 << 5 | 0x4;
-	sw_w32(v, RTL838X_SDS_MODE_SEL);
-
-	pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
-	sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
-	i = 0;
-	while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
-		sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
-			rtl8380_sds01_qsgmii_6275b[2 * i]);
-		i++;
-	}
-
-	i = 0;
-	while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
-		sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
-		i++;
-	}
-
-	i = 0;
-	while (rtl8380_sds4_fiber_6275b[2 * i]) {
-		sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
-		i++;
-	}
-
-	i = 0;
-	while (rtl8380_sds5_fiber_6275b[2 * i]) {
-		sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
-		i++;
-	}
-
-	i = 0;
-	while (rtl8380_sds_reset[2 * i]) {
-		sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
-		i++;
-	}
-
-	i = 0;
-	while (rtl8380_sds_release_reset[2 * i]) {
-		sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
-		i++;
-	}
-
-	pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
-	sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
-
-	pr_info("Configuration of SERDES done\n");
-	return 0;
-}
-
-static int rtl8390_configure_serdes(struct phy_device *phydev)
-{
-	phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
-
-	/* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
-	sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
-
-	/* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
-	 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
-	 * and FRE16_EEE_QUIET_FIB1G
-	 */
-	sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
-
-	return 0;
-}
-
-int rtl9300_configure_serdes(struct phy_device *phydev)
-{
-	struct device *dev = &phydev->mdio.dev;
-	int phy_addr = phydev->mdio.addr;
-	int sds_num = 0;
-	int v;
-
-	phydev_info(phydev, "Configuring internal RTL9300 SERDES\n");
-
-	switch (phy_addr) {
-	case 26:
-		sds_num = 8;
-		break;
-	case 27:
-		sds_num = 9;
-		break;
-	default:
-		dev_err(dev, "Not a SerDes PHY\n");
-		return -EINVAL;
-	}
-
-	/* Set default Medium to fibre */
-	v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
-	if (v < 0) {
-		dev_err(dev, "Cannot access SerDes PHY %d\n", phy_addr);
-		return -EINVAL;
-	}
-	v |= BIT(2);
-	rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
-
-	// TODO: this needs to be configurable via ethtool/.dts
-	pr_info("Setting 10G/1000BX auto fibre medium\n");
-	rtl9300_sds_rst(sds_num, 0x1b);
-
-	// TODO: Apply patch set for fibre type
-
-	return 0;
-}
-
-static int rtl8214fc_phy_probe(struct phy_device *phydev)
-{
-	struct device *dev = &phydev->mdio.dev;
-	struct rtl838x_phy_priv *priv;
-	int addr = phydev->mdio.addr;
-
-	/* 839x has internal SerDes */
-	if (soc_info.id == 0x8393)
-		return -ENODEV;
-
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->name = "RTL8214FC";
-
-	/* All base addresses of the PHYs start at multiples of 8 */
-	if (!(addr % 8)) {
-		/* Configuration must be done whil patching still possible */
-		return rtl8380_configure_rtl8214fc(phydev);
-	}
-	return 0;
-}
-
-static int rtl8214c_phy_probe(struct phy_device *phydev)
-{
-	struct device *dev = &phydev->mdio.dev;
-	struct rtl838x_phy_priv *priv;
-	int addr = phydev->mdio.addr;
-
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->name = "RTL8214C";
-
-	/* All base addresses of the PHYs start at multiples of 8 */
-	if (!(addr % 8)) {
-		/* Configuration must be done whil patching still possible */
-		return rtl8380_configure_rtl8214c(phydev);
-	}
-	return 0;
-}
-
-static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
-{
-	struct device *dev = &phydev->mdio.dev;
-	struct rtl838x_phy_priv *priv;
-	int addr = phydev->mdio.addr;
-
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->name = "RTL8218B (external)";
-
-	/* All base addresses of the PHYs start at multiples of 8 */
-	if (!(addr % 8) && soc_info.family == RTL8380_FAMILY_ID) {
-		/* Configuration must be done while patching still possible */
-		return rtl8380_configure_ext_rtl8218b(phydev);
-	}
-	return 0;
-}
-
-static int rtl8218b_int_phy_probe(struct phy_device *phydev)
-{
-	struct device *dev = &phydev->mdio.dev;
-	struct rtl838x_phy_priv *priv;
-	int addr = phydev->mdio.addr;
-
-	if (soc_info.family != RTL8380_FAMILY_ID)
-		return -ENODEV;
-	if (addr >= 24)
-		return -ENODEV;
-
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->name = "RTL8218B (internal)";
-
-	/* All base addresses of the PHYs start at multiples of 8 */
-	if (!(addr % 8)) {
-		/* Configuration must be done while patching still possible */
-		return rtl8380_configure_int_rtl8218b(phydev);
-	}
-	return 0;
-}
-
-static int rtl8218d_phy_probe(struct phy_device *phydev)
-{
-	struct device *dev = &phydev->mdio.dev;
-	struct rtl838x_phy_priv *priv;
-	int addr = phydev->mdio.addr;
-
-	pr_info("%s: id: %d\n", __func__, addr);
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->name = "RTL8218D";
-
-	/* All base addresses of the PHYs start at multiples of 8 */
-	if (!(addr % 8)) {
-		/* Configuration must be done while patching still possible */
-// TODO:		return configure_rtl8218d(phydev);
-	}
-	return 0;
-}
-
-static int rtl8226_phy_probe(struct phy_device *phydev)
-{
-	struct device *dev = &phydev->mdio.dev;
-	struct rtl838x_phy_priv *priv;
-	int addr = phydev->mdio.addr;
-
-	pr_info("%s: id: %d\n", __func__, addr);
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->name = "RTL8226";
-
-	return 0;
-}
-
-static int rtl838x_serdes_probe(struct phy_device *phydev)
-{
-	struct device *dev = &phydev->mdio.dev;
-	struct rtl838x_phy_priv *priv;
-	int addr = phydev->mdio.addr;
-
-	if (soc_info.family != RTL8380_FAMILY_ID)
-		return -ENODEV;
-	if (addr < 24)
-		return -ENODEV;
-
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->name = "RTL8380 Serdes";
-
-	/* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
-	if (soc_info.id == 0x8380) {
-		if (addr == 24)
-			return rtl8380_configure_serdes(phydev);
-		return 0;
-	}
-	return -ENODEV;
-}
-
-static int rtl8393_serdes_probe(struct phy_device *phydev)
-{
-	struct device *dev = &phydev->mdio.dev;
-	struct rtl838x_phy_priv *priv;
-	int addr = phydev->mdio.addr;
-
-	pr_info("%s: id: %d\n", __func__, addr);
-	if (soc_info.family != RTL8390_FAMILY_ID)
-		return -ENODEV;
-
-	if (addr < 24)
-		return -ENODEV;
-
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->name = "RTL8393 Serdes";
-	return rtl8390_configure_serdes(phydev);
-}
-
-static int rtl8390_serdes_probe(struct phy_device *phydev)
-{
-	struct device *dev = &phydev->mdio.dev;
-	struct rtl838x_phy_priv *priv;
-	int addr = phydev->mdio.addr;
-
-	if (soc_info.family != RTL8390_FAMILY_ID)
-		return -ENODEV;
-
-	if (addr < 24)
-		return -ENODEV;
-
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->name = "RTL8390 Serdes";
-	return rtl8390_configure_generic(phydev);
-}
-
-static int rtl9300_serdes_probe(struct phy_device *phydev)
-{
-	struct device *dev = &phydev->mdio.dev;
-	struct rtl838x_phy_priv *priv;
-	int addr = phydev->mdio.addr;
-
-	if (soc_info.family != RTL9300_FAMILY_ID)
-		return -ENODEV;
-
-	if (addr < 24)
-		return -ENODEV;
-
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
-
-	priv->name = "RTL9300 Serdes";
-	return rtl9300_configure_serdes(phydev);
-}
-
-static struct phy_driver rtl83xx_phy_driver[] = {
-	{
-		PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
-		.name		= "Realtek RTL8214C",
-		.features	= PHY_GBIT_FEATURES,
-		.match_phy_device = rtl8214c_match_phy_device,
-		.probe		= rtl8214c_phy_probe,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-		.set_loopback	= genphy_loopback,
-	},
-	{
-		PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
-		.name		= "Realtek RTL8214FC",
-		.features	= PHY_GBIT_FIBRE_FEATURES,
-		.match_phy_device = rtl8214fc_match_phy_device,
-		.probe		= rtl8214fc_phy_probe,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-		.set_loopback	= genphy_loopback,
-		.read_mmd	= rtl8218b_read_mmd,
-		.write_mmd	= rtl8218b_write_mmd,
-		.set_port	= rtl8214fc_set_port,
-		.get_port	= rtl8214fc_get_port,
-		.set_eee	= rtl8214fc_set_eee,
-		.get_eee	= rtl8214fc_get_eee,
-	},
-	{
-		PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
-		.name		= "Realtek RTL8218B (external)",
-		.features	= PHY_GBIT_FEATURES,
-		.match_phy_device = rtl8218b_ext_match_phy_device,
-		.probe		= rtl8218b_ext_phy_probe,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-		.set_loopback	= genphy_loopback,
-		.read_mmd	= rtl8218b_read_mmd,
-		.write_mmd	= rtl8218b_write_mmd,
-		.set_eee	= rtl8218b_set_eee,
-		.get_eee	= rtl8218b_get_eee,
-	},
-	{
-		PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
-		.name		= "REALTEK RTL8218D",
-		.features	= PHY_GBIT_FEATURES,
-		.probe		= rtl8218d_phy_probe,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-		.set_loopback	= genphy_loopback,
-		.set_eee	= rtl8218d_set_eee,
-		.get_eee	= rtl8218d_get_eee,
-	},
-	{
-		PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
-		.name		= "REALTEK RTL8226",
-		.features	= PHY_GBIT_FEATURES,
-		.probe		= rtl8226_phy_probe,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-		.set_loopback	= genphy_loopback,
-		.read_mmd	= rtl8226_read_mmd,
-		.write_mmd	= rtl8226_write_mmd,
-		.read_page	= rtl8226_read_page,
-		.write_page	= rtl8226_write_page,
-		.read_status	= rtl8226_read_status,
-		.config_aneg	= rtl8226_config_aneg,
-		.set_eee	= rtl8226_set_eee,
-		.get_eee	= rtl8226_get_eee,
-	},
-	{
-		PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
-		.name		= "Realtek RTL8218B (internal)",
-		.features	= PHY_GBIT_FEATURES,
-		.probe		= rtl8218b_int_phy_probe,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-		.set_loopback	= genphy_loopback,
-		.read_mmd	= rtl8218b_read_mmd,
-		.write_mmd	= rtl8218b_write_mmd,
-		.set_eee	= rtl8218b_set_eee,
-		.get_eee	= rtl8218b_get_eee,
-	},
-	{
-		PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
-		.name		= "Realtek RTL8380 SERDES",
-		.features	= PHY_GBIT_FIBRE_FEATURES,
-		.probe		= rtl838x_serdes_probe,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-		.set_loopback	= genphy_loopback,
-		.read_mmd	= rtl8218b_read_mmd,
-		.write_mmd	= rtl8218b_write_mmd,
-		.read_status	= rtl8380_read_status,
-	},
-	{
-		PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
-		.name		= "Realtek RTL8393 SERDES",
-		.features	= PHY_GBIT_FIBRE_FEATURES,
-		.probe		= rtl8393_serdes_probe,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-		.set_loopback	= genphy_loopback,
-		.read_status	= rtl8393_read_status,
-	},
-	{
-		PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
-		.name		= "Realtek RTL8390 Generic",
-		.features	= PHY_GBIT_FIBRE_FEATURES,
-		.probe		= rtl8390_serdes_probe,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-		.set_loopback	= genphy_loopback,
-	},
-	{
-		PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
-		.name		= "REALTEK RTL9300 SERDES",
-		.features	= PHY_GBIT_FIBRE_FEATURES,
-		.probe		= rtl9300_serdes_probe,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-		.set_loopback	= genphy_loopback,
-	},
-};
-
-module_phy_driver(rtl83xx_phy_driver);
-
-static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
-	{ PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
-	{ }
-};
-
-MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
-
-MODULE_AUTHOR("B. Koblitz");
-MODULE_DESCRIPTION("RTL83xx PHY driver");
-MODULE_LICENSE("GPL");
diff --git a/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h b/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h
deleted file mode 100644
index 031ec8a0e9..0000000000
--- a/target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-
-// TODO: not really used
-struct rtl838x_phy_priv {
-	char *name;
-};
-
-struct __attribute__ ((__packed__)) part {
-	uint16_t start;
-	uint8_t wordsize;
-	uint8_t words;
-};
-
-struct __attribute__ ((__packed__)) fw_header {
-	uint32_t magic;
-	uint32_t phy;
-	uint32_t checksum;
-	uint32_t version;
-	struct part parts[10];
-};
-
-// TODO: fixed path?
-#define FIRMWARE_838X_8380_1	"rtl838x_phy/rtl838x_8380.fw"
-#define FIRMWARE_838X_8214FC_1	"rtl838x_phy/rtl838x_8214fc.fw"
-#define FIRMWARE_838X_8218b_1	"rtl838x_phy/rtl838x_8218b.fw"
-
-/* External RTL8218B and RTL8214FC IDs are identical */
-#define PHY_ID_RTL8214C		0x001cc942
-#define PHY_ID_RTL8214FC	0x001cc981
-#define PHY_ID_RTL8218B_E	0x001cc981
-#define PHY_ID_RTL8218D		0x001cc983
-#define PHY_ID_RTL8218B_I	0x001cca40
-#define PHY_ID_RTL8226		0x001cc838
-#define PHY_ID_RTL8390_GENERIC	0x001ccab0
-#define PHY_ID_RTL8393_I	0x001c8393
-#define PHY_ID_RTL9300_I	0x70d03106
-
-// PHY MMD devices
-#define MMD_AN		7
-#define MMD_VEND2	31
-
-/* Registers of the internal Serdes of the 8380 */
-#define RTL838X_SDS_MODE_SEL			(0x0028)
-#define RTL838X_SDS_CFG_REG			(0x0034)
-#define RTL838X_INT_MODE_CTRL			(0x005c)
-#define RTL838X_DMY_REG31			(0x3b28)
-
-#define RTL8380_SDS4_FIB_REG0			(0xF800)
-#define RTL838X_SDS4_REG28			(0xef80)
-#define RTL838X_SDS4_DUMMY0			(0xef8c)
-#define RTL838X_SDS5_EXT_REG6			(0xf18c)
-#define RTL838X_SDS4_FIB_REG0			(RTL838X_SDS4_REG28 + 0x880)
-#define RTL838X_SDS5_FIB_REG0			(RTL838X_SDS4_REG28 + 0x980)
-
-/* Registers of the internal SerDes of the RTL8390 */
-#define RTL839X_SDS12_13_XSG0			(0xB800)
-
-/* Registers of the internal Serdes of the 9300 */
-#define RTL930X_SDS_INDACS_CMD			(0x03B0)
-#define RTL930X_SDS_INDACS_DATA			(0x03B4)
diff --git a/target/linux/realtek/patches-5.4/300-mips-add-rtl838x-platform.patch b/target/linux/realtek/patches-5.4/300-mips-add-rtl838x-platform.patch
deleted file mode 100644
index b47f6f5ffa..0000000000
--- a/target/linux/realtek/patches-5.4/300-mips-add-rtl838x-platform.patch
+++ /dev/null
@@ -1,39 +0,0 @@
---- a/arch/mips/Kbuild.platforms
-+++ b/arch/mips/Kbuild.platforms
-@@ -27,6 +27,7 @@ platforms += pistachio
- platforms += pmcs-msp71xx
- platforms += pnx833x
- platforms += ralink
-+platforms += rtl838x
- platforms += rb532
- platforms += sgi-ip22
- platforms += sgi-ip27
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -636,6 +636,26 @@ config RALINK
- 	select ARCH_HAS_RESET_CONTROLLER
- 	select RESET_CONTROLLER
- 
-+config RTL838X
-+	bool "Realtek based platforms"
-+	select DMA_NONCOHERENT
-+	select IRQ_MIPS_CPU
-+	select CSRC_R4K
-+	select CEVT_R4K
-+	select SYS_HAS_CPU_MIPS32_R1
-+	select SYS_HAS_CPU_MIPS32_R2
-+	select SYS_SUPPORTS_BIG_ENDIAN
-+	select SYS_SUPPORTS_32BIT_KERNEL
-+	select SYS_SUPPORTS_MIPS16
-+	select SYS_HAS_EARLY_PRINTK
-+	select SYS_HAS_EARLY_PRINTK_8250
-+	select USE_GENERIC_EARLY_PRINTK_8250
-+	select BOOT_RAW
-+	select PINCTRL
-+	select ARCH_HAS_RESET_CONTROLLER
-+	select RESET_CONTROLLER
-+	select USE_OF
-+
- config SGI_IP22
- 	bool "SGI IP22 (Indy/Indigo2)"
- 	select FW_ARC
diff --git a/target/linux/realtek/patches-5.4/301-gpio-add-rtl838x-driver.patch b/target/linux/realtek/patches-5.4/301-gpio-add-rtl838x-driver.patch
deleted file mode 100644
index 4f5901d87f..0000000000
--- a/target/linux/realtek/patches-5.4/301-gpio-add-rtl838x-driver.patch
+++ /dev/null
@@ -1,32 +0,0 @@
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -441,6 +441,18 @@ config GPIO_REG
- 	  A 32-bit single register GPIO fixed in/out implementation.  This
- 	  can be used to represent any register as a set of GPIO signals.
- 
-+config GPIO_RTL8231
-+	tristate "RTL8231 GPIO"
-+	depends on GPIO_RTL838X
-+	help
-+	  Say yes here to support Realtek RTL8231 GPIO expansion chips.
-+
-+config GPIO_RTL838X
-+	tristate "RTL838X GPIO"
-+	depends on RTL838X
-+	help
-+	  Say yes here to support RTL838X GPIO devices.
-+
- config GPIO_SAMA5D2_PIOBU
- 	tristate "SAMA5D2 PIOBU GPIO support"
- 	depends on MFD_SYSCON
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -117,6 +117,8 @@ obj-$(CONFIG_GPIO_RC5T583)		+= gpio-rc5t
- obj-$(CONFIG_GPIO_RCAR)			+= gpio-rcar.o
- obj-$(CONFIG_GPIO_RDC321X)		+= gpio-rdc321x.o
- obj-$(CONFIG_GPIO_REG)			+= gpio-reg.o
-+obj-$(CONFIG_GPIO_RTL8231)		+= gpio-rtl8231.o
-+obj-$(CONFIG_GPIO_RTL838X)		+= gpio-rtl838x.o
- obj-$(CONFIG_ARCH_SA1100)		+= gpio-sa1100.o
- obj-$(CONFIG_GPIO_SAMA5D2_PIOBU)	+= gpio-sama5d2-piobu.o
- obj-$(CONFIG_GPIO_SCH311X)		+= gpio-sch311x.o
diff --git a/target/linux/realtek/patches-5.4/302-clocksource-add-rtl9300-driver.patch b/target/linux/realtek/patches-5.4/302-clocksource-add-rtl9300-driver.patch
deleted file mode 100644
index db8f22bf02..0000000000
--- a/target/linux/realtek/patches-5.4/302-clocksource-add-rtl9300-driver.patch
+++ /dev/null
@@ -1,34 +0,0 @@
---- a/drivers/clocksource/Kconfig
-+++ b/drivers/clocksource/Kconfig
-@@ -128,6 +128,15 @@ config RDA_TIMER
- 	help
- 	  Enables the support for the RDA Micro timer driver.
- 
-+config RTL9300_TIMER
-+	bool "Clocksource/timer for the Realtek RTL9300 family of SoCs"
-+	depends on MIPS
-+	select COMMON_CLK
-+	select TIMER_OF
-+	select CLKSRC_MMIO
-+	help
-+	  Enables support for the Realtek RTL9300 timer driver.
-+
- config SUN4I_TIMER
- 	bool "Sun4i timer driver" if COMPILE_TEST
- 	depends on HAS_IOMEM
-@@ -697,5 +706,4 @@ config INGENIC_TIMER
- 	select IRQ_DOMAIN
- 	help
- 	  Support for the timer/counter unit of the Ingenic JZ SoCs.
--
- endmenu
---- a/drivers/clocksource/Makefile
-+++ b/drivers/clocksource/Makefile
-@@ -61,6 +61,7 @@ obj-$(CONFIG_MILBEAUT_TIMER)	+= timer-mi
- obj-$(CONFIG_SPRD_TIMER)	+= timer-sprd.o
- obj-$(CONFIG_NPCM7XX_TIMER)	+= timer-npcm7xx.o
- obj-$(CONFIG_RDA_TIMER)		+= timer-rda.o
-+obj-$(CONFIG_RTL9300_TIMER)	+= timer-rtl9300.o
- 
- obj-$(CONFIG_ARC_TIMERS)		+= arc_timer.o
- obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
diff --git a/target/linux/realtek/patches-5.4/400-mtd-add-rtl838x-spi-flash-driver.patch b/target/linux/realtek/patches-5.4/400-mtd-add-rtl838x-spi-flash-driver.patch
deleted file mode 100644
index 16cff75308..0000000000
--- a/target/linux/realtek/patches-5.4/400-mtd-add-rtl838x-spi-flash-driver.patch
+++ /dev/null
@@ -1,23 +0,0 @@
---- a/drivers/mtd/spi-nor/Kconfig
-+++ b/drivers/mtd/spi-nor/Kconfig
-@@ -118,4 +118,13 @@ config SPI_INTEL_SPI_PLATFORM
- 	  To compile this driver as a module, choose M here: the module
- 	  will be called intel-spi-platform.
- 
-+config SPI_RTL838X
-+	tristate "Realtek RTl838X SPI flash platform driver"
-+	depends on RTL838X
-+	help
-+	  This driver provides support for accessing SPI flash
-+	  in the RTL838X SoC.
-+
-+	  Say N here unless you know what you are doing.
-+
- endif # MTD_SPI_NOR
---- a/drivers/mtd/spi-nor/Makefile
-+++ b/drivers/mtd/spi-nor/Makefile
-@@ -8,3 +8,4 @@ obj-$(CONFIG_SPI_NXP_SPIFI)	+= nxp-spifi
- obj-$(CONFIG_SPI_INTEL_SPI)	+= intel-spi.o
- obj-$(CONFIG_SPI_INTEL_SPI_PCI)	+= intel-spi-pci.o
- obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM)	+= intel-spi-platform.o
-+obj-$(CONFIG_SPI_RTL838X)	+= rtl838x-nor.o
diff --git a/target/linux/realtek/patches-5.4/700-net-dsa-add-support-for-rtl838x-switch.patch b/target/linux/realtek/patches-5.4/700-net-dsa-add-support-for-rtl838x-switch.patch
deleted file mode 100644
index bb6f83e55d..0000000000
--- a/target/linux/realtek/patches-5.4/700-net-dsa-add-support-for-rtl838x-switch.patch
+++ /dev/null
@@ -1,18 +0,0 @@
---- a/drivers/net/dsa/Kconfig
-+++ b/drivers/net/dsa/Kconfig
-@@ -63,6 +63,8 @@ config NET_DSA_QCA8K
- 	  This enables support for the Qualcomm Atheros QCA8K Ethernet
- 	  switch chips.
- 
-+source "drivers/net/dsa/rtl83xx/Kconfig"
-+
- config NET_DSA_REALTEK_SMI
- 	tristate "Realtek SMI Ethernet switch family support"
- 	depends on NET_DSA
---- a/drivers/net/dsa/Makefile
-+++ b/drivers/net/dsa/Makefile
-@@ -21,3 +21,4 @@ obj-y				+= b53/
- obj-y				+= microchip/
- obj-y				+= mv88e6xxx/
- obj-y				+= sja1105/
-+obj-y				+= rtl83xx/
diff --git a/target/linux/realtek/patches-5.4/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch b/target/linux/realtek/patches-5.4/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch
deleted file mode 100644
index 803614e7c0..0000000000
--- a/target/linux/realtek/patches-5.4/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch
+++ /dev/null
@@ -1,40 +0,0 @@
---- a/net/dsa/tag_trailer.c
-+++ b/net/dsa/tag_trailer.c
-@@ -44,7 +44,12 @@ static struct sk_buff *trailer_xmit(stru
- 
- 	trailer = skb_put(nskb, 4);
- 	trailer[0] = 0x80;
-+
-+#ifdef CONFIG_NET_DSA_RTL83XX
-+	trailer[1] = dp->index;
-+#else
- 	trailer[1] = 1 << dp->index;
-+#endif /* CONFIG_NET_DSA_RTL838X */
- 	trailer[2] = 0x10;
- 	trailer[3] = 0x00;
- 
-@@ -61,12 +66,23 @@ static struct sk_buff *trailer_rcv(struc
- 		return NULL;
- 
- 	trailer = skb_tail_pointer(skb) - 4;
-+
-+#ifdef CONFIG_NET_DSA_RTL83XX
-+	if (trailer[0] != 0x80 || (trailer[1] & 0x80) != 0x00 ||
-+	    (trailer[2] & 0xef) != 0x00 || trailer[3] != 0x00)
-+		return NULL;
-+
-+	if (trailer[1] & 0x40)
-+		skb->offload_fwd_mark = 1;
-+
-+	source_port = trailer[1] & 0x3f;
-+#else
- 	if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 ||
- 	    (trailer[2] & 0xef) != 0x00 || trailer[3] != 0x00)
- 		return NULL;
- 
- 	source_port = trailer[1] & 7;
--
-+#endif
- 	skb->dev = dsa_master_find_slave(dev, 0, source_port);
- 	if (!skb->dev)
- 		return NULL;
diff --git a/target/linux/realtek/patches-5.4/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch b/target/linux/realtek/patches-5.4/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch
deleted file mode 100644
index 929f2b9444..0000000000
--- a/target/linux/realtek/patches-5.4/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/include/linux/platform_data/dsa.h
-+++ b/include/linux/platform_data/dsa.h
-@@ -6,7 +6,7 @@ struct device;
- struct net_device;
- 
- #define DSA_MAX_SWITCHES	4
--#define DSA_MAX_PORTS		12
-+#define DSA_MAX_PORTS		54
- #define DSA_RTABLE_NONE		-1
- 
- struct dsa_chip_data {
diff --git a/target/linux/realtek/patches-5.4/702-net-ethernet-add-support-for-rtl838x-ethernet.patch b/target/linux/realtek/patches-5.4/702-net-ethernet-add-support-for-rtl838x-ethernet.patch
deleted file mode 100644
index 952384ac89..0000000000
--- a/target/linux/realtek/patches-5.4/702-net-ethernet-add-support-for-rtl838x-ethernet.patch
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/drivers/net/ethernet/Kconfig
-+++ b/drivers/net/ethernet/Kconfig
-@@ -164,6 +164,13 @@ source "drivers/net/ethernet/rdc/Kconfig
- source "drivers/net/ethernet/realtek/Kconfig"
- source "drivers/net/ethernet/renesas/Kconfig"
- source "drivers/net/ethernet/rocker/Kconfig"
-+
-+config NET_RTL838X
-+	tristate "Realtek rtl838x Ethernet MAC support"
-+	depends on RTL838X
-+	---help---
-+	  Say Y here if you want to use the Realtek rtl838x Gbps Ethernet MAC.
-+
- source "drivers/net/ethernet/samsung/Kconfig"
- source "drivers/net/ethernet/seeq/Kconfig"
- source "drivers/net/ethernet/sfc/Kconfig"
---- a/drivers/net/ethernet/Makefile
-+++ b/drivers/net/ethernet/Makefile
-@@ -76,6 +76,7 @@ obj-$(CONFIG_NET_VENDOR_REALTEK) += real
- obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/
- obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
- obj-$(CONFIG_NET_VENDOR_ROCKER) += rocker/
-+obj-$(CONFIG_NET_RTL838X) += rtl838x_eth.o
- obj-$(CONFIG_NET_VENDOR_SAMSUNG) += samsung/
- obj-$(CONFIG_NET_VENDOR_SEEQ) += seeq/
- obj-$(CONFIG_NET_VENDOR_SILAN) += silan/
diff --git a/target/linux/realtek/patches-5.4/703-include-linux-add-phy-ops-for-rtl838x.patch b/target/linux/realtek/patches-5.4/703-include-linux-add-phy-ops-for-rtl838x.patch
deleted file mode 100644
index 3682eb30a3..0000000000
--- a/target/linux/realtek/patches-5.4/703-include-linux-add-phy-ops-for-rtl838x.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -645,6 +645,10 @@ struct phy_driver {
- 			    struct ethtool_tunable *tuna,
- 			    const void *data);
- 	int (*set_loopback)(struct phy_device *dev, bool enable);
-+	int (*get_port)(struct phy_device *dev);
-+	int (*set_port)(struct phy_device *dev, int port);
-+	int (*get_eee)(struct phy_device *dev, struct ethtool_eee *e);
-+	int (*set_eee)(struct phy_device *dev, struct ethtool_eee *e);
- };
- #define to_phy_driver(d) container_of(to_mdio_common_driver(d),		\
- 				      struct phy_driver, mdiodrv)
diff --git a/target/linux/realtek/patches-5.4/704-drivers-net-phy-eee-support-for-rtl838x.patch b/target/linux/realtek/patches-5.4/704-drivers-net-phy-eee-support-for-rtl838x.patch
deleted file mode 100644
index 7743147ea3..0000000000
--- a/target/linux/realtek/patches-5.4/704-drivers-net-phy-eee-support-for-rtl838x.patch
+++ /dev/null
@@ -1,41 +0,0 @@
---- a/drivers/net/phy/phylink.c
-+++ b/drivers/net/phy/phylink.c
-@@ -1242,6 +1242,11 @@ int phylink_ethtool_ksettings_set(struct
- 
- 	/* If we have a PHY, configure the phy */
- 	if (pl->phydev) {
-+		if (pl->phydev->drv->get_port && pl->phydev->drv->set_port) {
-+			if(pl->phydev->drv->get_port(pl->phydev) != kset->base.port) {
-+				pl->phydev->drv->set_port(pl->phydev, kset->base.port);
-+			}
-+		}
- 		ret = phy_ethtool_ksettings_set(pl->phydev, &our_kset);
- 		if (ret)
- 			return ret;
-@@ -1420,8 +1425,11 @@ int phylink_ethtool_get_eee(struct phyli
- 
- 	ASSERT_RTNL();
- 
--	if (pl->phydev)
-+	if (pl->phydev) {
-+		if (pl->phydev->drv->get_eee)
-+			return pl->phydev->drv->get_eee(pl->phydev, eee);
- 		ret = phy_ethtool_get_eee(pl->phydev, eee);
-+	}
- 
- 	return ret;
- }
-@@ -1438,9 +1446,11 @@ int phylink_ethtool_set_eee(struct phyli
- 
- 	ASSERT_RTNL();
- 
--	if (pl->phydev)
-+	if (pl->phydev) {
-+		if (pl->phydev->drv->set_eee)
-+			return pl->phydev->drv->set_eee(pl->phydev, eee);
- 		ret = phy_ethtool_set_eee(pl->phydev, eee);
--
-+	}
- 	return ret;
- }
- EXPORT_SYMBOL_GPL(phylink_ethtool_set_eee);
diff --git a/target/linux/realtek/patches-5.4/705-add-rtl-phy.patch b/target/linux/realtek/patches-5.4/705-add-rtl-phy.patch
deleted file mode 100644
index 1ab9e212d4..0000000000
--- a/target/linux/realtek/patches-5.4/705-add-rtl-phy.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -536,6 +536,12 @@ config REALTEK_PHY
- 	---help---
- 	  Supports the Realtek 821x PHY.
- 
-+config REALTEK_SOC_PHY
-+	tristate "Realtek SoC PHYs"
-+	depends on RTL838X
-+	---help---
-+	  Supports the PHYs found in combination with Realtek Switch SoCs
-+
- config RENESAS_PHY
- 	tristate "Driver for Renesas PHYs"
- 	---help---
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -101,6 +101,7 @@ obj-$(CONFIG_NATIONAL_PHY)	+= national.o
- obj-$(CONFIG_NXP_TJA11XX_PHY)	+= nxp-tja11xx.o
- obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
- obj-$(CONFIG_REALTEK_PHY)	+= realtek.o
-+obj-$(CONFIG_REALTEK_SOC_PHY)   += rtl83xx-phy.o
- obj-$(CONFIG_RENESAS_PHY)	+= uPD60620.o
- obj-$(CONFIG_ROCKCHIP_PHY)	+= rockchip.o
- obj-$(CONFIG_SMSC_PHY)		+= smsc.o
diff --git a/target/linux/realtek/patches-5.4/705-include-linux-phy-increase-phy-address-number-for-rtl839x.patch b/target/linux/realtek/patches-5.4/705-include-linux-phy-increase-phy-address-number-for-rtl839x.patch
deleted file mode 100644
index ca6deb74d8..0000000000
--- a/target/linux/realtek/patches-5.4/705-include-linux-phy-increase-phy-address-number-for-rtl839x.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -188,7 +188,7 @@ static inline const char *phy_modes(phy_
- #define PHY_INIT_TIMEOUT	100000
- #define PHY_FORCE_TIMEOUT	10
- 
--#define PHY_MAX_ADDR	32
-+#define PHY_MAX_ADDR	64
- 
- /* Used when trying to connect to a specific phy (mii bus id:phy device id) */
- #define PHY_ID_FMT "%s:%02x"