From: Chon Ming Lee Date: Wed, 25 Sep 2013 07:47:51 +0000 (+0800) Subject: drm/i915: Fix VLV eDP timing v2 X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=58f6e632d5d24f1f510bafccc4c963a06f6a55a8;p=openwrt%2Fstaging%2Fblogic.git drm/i915: Fix VLV eDP timing v2 Fix the typo in previous commit for DP 1.62 divisor. drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2 v2: sigh, the m1 div is 3. Reported-by: Jesse Barnes Signed-off-by: Chon Ming Lee Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5e1de353a5b7..a5e4e612d8f9 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -59,7 +59,7 @@ static const struct dp_link_dpll pch_dpll[] = { static const struct dp_link_dpll vlv_dpll[] = { { DP_LINK_BW_1_62, - { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 } }, + { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, { DP_LINK_BW_2_7, { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } };