From: Gregory CLEMENT <gregory.clement@bootlin.com>
Date: Thu, 1 Mar 2018 13:18:19 +0000 (+0100)
Subject: ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodes
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=597667d889517c6085d57aac92dbf1cc624cd8ae;p=openwrt%2Fstaging%2Fblogic.git

ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodes

This extra clock is needed to access the registers of the UARTs used on
CP110 component of the Armada 7K/8K SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---

diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index d3f422f8f086..355bb295e4d9 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -303,7 +303,9 @@
 			reg-shift = <2>;
 			interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <1>;
-			clocks = <&CP110_LABEL(clk) 1 21>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&CP110_LABEL(clk) 1 21>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "disabled";
 		};
 
@@ -313,7 +315,9 @@
 			reg-shift = <2>;
 			interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <1>;
-			clocks = <&CP110_LABEL(clk) 1 21>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&CP110_LABEL(clk) 1 21>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "disabled";
 		};
 
@@ -323,7 +327,9 @@
 			reg-shift = <2>;
 			interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <1>;
-			clocks = <&CP110_LABEL(clk) 1 21>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&CP110_LABEL(clk) 1 21>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "disabled";
 		};
 
@@ -333,7 +339,9 @@
 			reg-shift = <2>;
 			interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <1>;
-			clocks = <&CP110_LABEL(clk) 1 21>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&CP110_LABEL(clk) 1 21>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "disabled";
 		};