From: Chris Wilson Date: Thu, 29 Jun 2017 12:59:25 +0000 (+0100) Subject: dma-buf/sw-sync: Fix the is-signaled test to handle u32 wraparound X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=61894b02716f122dd7662d5d89f5b2245ca551e2;p=openwrt%2Fstaging%2Fblogic.git dma-buf/sw-sync: Fix the is-signaled test to handle u32 wraparound Use the canonical __dma_fence_is_later() to compare the fence seqno against the timeline seqno to check if the fence is signaled. Signed-off-by: Chris Wilson Cc: Sumit Semwal Cc: Sean Paul Cc: Gustavo Padovan Reviewed-by: Sean Paul Signed-off-by: Gustavo Padovan Link: http://patchwork.freedesktop.org/patch/msgid/20170629125930.821-2-chris@chris-wilson.co.uk --- diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c index 69c5ff36e2f9..4d5d8c5e2534 100644 --- a/drivers/dma-buf/sw_sync.c +++ b/drivers/dma-buf/sw_sync.c @@ -219,7 +219,7 @@ static bool timeline_fence_signaled(struct dma_fence *fence) { struct sync_timeline *parent = dma_fence_parent(fence); - return (fence->seqno > parent->value) ? false : true; + return !__dma_fence_is_later(fence->seqno, parent->value); } static bool timeline_fence_enable_signaling(struct dma_fence *fence)