From: Daniel Golle Date: Mon, 31 Jul 2023 23:08:56 +0000 (+0100) Subject: mediatek: filogic: update MT7988 device tree X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=64b99802a61a477ed23fc1f3426fb19d1bc0c6f3;p=openwrt%2Fstaging%2Fwigyori.git mediatek: filogic: update MT7988 device tree * move ethernet to mt7988a.dtsi * move switch definition to mt7988a.dtsi * add PHY LEDs Signed-off-by: Daniel Golle --- diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts index e204dc4f16..27ef19c46d 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "mt7988a-rfb-spim-nand.dtsi" #include +#include / { model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; @@ -29,173 +30,105 @@ pinctrl-0 = <&mdio0_pins>; pinctrl-names = "default"; status = "okay"; +}; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "internal"; +&gmac0 { + status = "okay"; +}; - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; +&gmac1 { + status = "okay"; + phy-mode = "internal"; + phy-connection-type = "internal"; + phy = <&int_2p5g_phy>; +}; + +&gmac2 { + status = "okay"; + phy-mode = "usxgmii"; + phy-connection-type = "usxgmii"; + phy = <&phy8>; +}; + +&mdio_bus { + /* external Aquantia AQR113C */ + phy0: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 72 1>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; }; - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "internal"; - phy-connection-type = "internal"; - phy = <&phy15>; + /* external Aquantia AQR113C */ + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 71 1>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; }; - gmac2: mac@2 { - compatible = "mediatek,eth-mac"; - reg = <2>; - phy-mode = "10gbase-kr"; - phy-connection-type = "10gbase-kr"; - phy = <&phy8>; + /* external Maxlinear GPY211C */ + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; }; - mdio0: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - /* external Aquantia AQR113C */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 72 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Aquantia AQR113C */ - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 71 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Maxlinear GPY211C */ - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - - /* external Maxlinear GPY211C */ - phy13: ethernet-phy@13 { - reg = <13>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - - /* internal 2.5G PHY */ - phy15: ethernet-phy@15 { - reg = <15>; - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "internal"; - }; + /* external Maxlinear GPY211C */ + phy13: ethernet-phy@13 { + reg = <13>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; }; }; +&int_2p5g_phy { + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; +}; + &switch { status = "okay"; +}; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - phy-mode = "internal"; - phy-handle = <&gsw_phy0>; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-mode = "internal"; - phy-handle = <&gsw_phy1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-mode = "internal"; - phy-handle = <&gsw_phy2>; - }; - - port@3 { - reg = <3>; - label = "lan3"; - phy-mode = "internal"; - phy-handle = <&gsw_phy3>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "internal"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - }; +&gsw_phy0 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe0_led0_pins>; +}; - mdio { - #address-cells = <1>; - #size-cells = <0>; - mediatek,pio = <&pio>; - - gsw_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <0>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; - nvmem-cells = <&phy_calibration_p0>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <1>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; - nvmem-cells = <&phy_calibration_p1>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy2: ethernet-phy@2 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <2>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; - nvmem-cells = <&phy_calibration_p2>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy3: ethernet-phy@3 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <3>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; - nvmem-cells = <&phy_calibration_p3>; - nvmem-cell-names = "phy-cal-data"; - }; - }; +&gsw_phy0_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy1 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe1_led0_pins>; +}; + +&gsw_phy1_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy2 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe2_led0_pins>; +}; + +&gsw_phy2_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy3 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe3_led0_pins>; +}; + +&gsw_phy3_led0 { + status = "okay"; + color = ; }; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 94aa8251bd..462218c65d 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -4,12 +4,13 @@ * Author: Sam.Shih */ -#include +#include #include +#include +#include #include -#include -#include #include +#include #include / { @@ -144,9 +145,9 @@ #size-cells = <2>; ranges; - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; + reg = <0 0x43000000 0 0x50000>; no-map; }; }; @@ -228,7 +229,7 @@ "iocfg_lb_base", "iocfg_tl_base", "eint"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 83>; + gpio-ranges = <&pio 0 0 84>; interrupt-controller; interrupts = ; interrupt-parent = <&gic>; @@ -260,47 +261,131 @@ }; }; - i2c2_pins: i2c2-pins-g0 { + i2c1_sfp_pins: i2c1-sfp-pins-g0 { + mux { + function = "i2c"; + groups = "i2c1_sfp"; + }; + }; + + i2c2_pins: i2c2-pins { + mux { + function = "i2c"; + groups = "i2c2"; + }; + }; + + i2c2_0_pins: i2c2-pins-g0 { + mux { + function = "i2c"; + groups = "i2c2_0"; + }; + }; + + i2c2_1_pins: i2c2-pins-g1 { mux { function = "i2c"; groups = "i2c2_1"; }; }; - gbe0_led0_pins: gbe0-pins { + gbe0_led0_pins: gbe0-led0-pins { mux { function = "led"; groups = "gbe0_led0"; }; }; - gbe1_led0_pins: gbe1-pins { + gbe1_led0_pins: gbe1-led0-pins { mux { function = "led"; groups = "gbe1_led0"; }; }; - gbe2_led0_pins: gbe2-pins { + gbe2_led0_pins: gbe2-led0-pins { mux { function = "led"; groups = "gbe2_led0"; }; }; - gbe3_led0_pins: gbe3-pins { + gbe3_led0_pins: gbe3-led0-pins { mux { function = "led"; groups = "gbe3_led0"; }; }; - i2p5gbe_led0_pins: 2p5gbe-pins { + gbe0_led1_pins: gbe0-led1-pins { + mux { + function = "led"; + groups = "gbe0_led1"; + }; + }; + + gbe1_led1_pins: gbe1-led1-pins { + mux { + function = "led"; + groups = "gbe1_led1"; + }; + }; + + gbe2_led1_pins: gbe2-led1-pins { + mux { + function = "led"; + groups = "gbe2_led1"; + }; + }; + + gbe3_led1_pins: gbe3-led1-pins { + mux { + function = "led"; + groups = "gbe3_led1"; + }; + }; + + i2p5gbe_led0_pins: 2p5gbe-led0-pins { mux { function = "led"; groups = "2p5gbe_led0"; }; }; + + i2p5gbe_led1_pins: 2p5gbe-led1-pins { + mux { + function = "led"; + groups = "2p5gbe_led1"; + }; + }; + + mmc0_pins_emmc_45: mmc0-pins-emmc-45 { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; + + mmc0_pins_emmc_51: mmc0-pins-emmc-51 { + mux { + function = "flash"; + groups = "emmc_51"; + }; + }; + + mmc0_pins_sdcard: mmc0-pins-sdcard { + mux { + function = "flash"; + groups = "sdcard"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; }; sgmiisys0: syscon@10060000 { @@ -380,6 +465,8 @@ <&infracfg CLK_INFRA_MUX_UART0_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, <&topckgen CLK_TOP_UART_SEL>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; status = "disabled"; }; @@ -645,6 +732,29 @@ status = "disabled"; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt7986-mmc", + "mediatek,mt7981-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11D60000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_MSDC400>, + <&infracfg CLK_INFRA_MSDC2_HCK>, + <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, + <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; + assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, + <&topckgen CLK_TOP_EMMC_400M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, + <&apmixedsys CLK_APMIXED_MSDCPLL>; + clock-names = "source", + "hclk", + "axi_cg", + "ahb_cg"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + tphy: tphy@11c50000 { compatible = "mediatek,mt7988", "mediatek,generic-tphy-v2"; @@ -747,6 +857,157 @@ interrupt-parent = <&gic>; interrupts = ; resets = <ðrst 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-mode = "internal"; + phy-handle = <&gsw_phy0>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&gsw_phy1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&gsw_phy2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&gsw_phy3>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + mediatek,pio = <&pio>; + + gsw_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <0>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p0>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy0_led0: gsw-phy0-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy0_led1: gsw-phy0-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + + gsw_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <1>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p1>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy1_led0: gsw-phy1-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy1_led1: gsw-phy1-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + + gsw_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <2>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p2>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy2_led0: gsw-phy2-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy2_led1: gsw-phy2-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + + gsw_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <3>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p3>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy3_led0: gsw-phy3-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy3_led1: gsw-phy3-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + }; }; ethwarp: syscon@15031000 { @@ -843,6 +1104,40 @@ #address-cells = <1>; #size-cells = <0>; status = "disabled"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + }; + + gmac2: mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + }; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* internal 2.5G PHY */ + int_2p5g_phy: ethernet-phy@15 { + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; + }; + }; }; }; }; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts index e204dc4f16..27ef19c46d 100644 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "mt7988a-rfb-spim-nand.dtsi" #include +#include / { model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; @@ -29,173 +30,105 @@ pinctrl-0 = <&mdio0_pins>; pinctrl-names = "default"; status = "okay"; +}; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "internal"; +&gmac0 { + status = "okay"; +}; - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; +&gmac1 { + status = "okay"; + phy-mode = "internal"; + phy-connection-type = "internal"; + phy = <&int_2p5g_phy>; +}; + +&gmac2 { + status = "okay"; + phy-mode = "usxgmii"; + phy-connection-type = "usxgmii"; + phy = <&phy8>; +}; + +&mdio_bus { + /* external Aquantia AQR113C */ + phy0: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 72 1>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; }; - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "internal"; - phy-connection-type = "internal"; - phy = <&phy15>; + /* external Aquantia AQR113C */ + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 71 1>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; }; - gmac2: mac@2 { - compatible = "mediatek,eth-mac"; - reg = <2>; - phy-mode = "10gbase-kr"; - phy-connection-type = "10gbase-kr"; - phy = <&phy8>; + /* external Maxlinear GPY211C */ + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; }; - mdio0: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - /* external Aquantia AQR113C */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 72 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Aquantia AQR113C */ - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 71 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Maxlinear GPY211C */ - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - - /* external Maxlinear GPY211C */ - phy13: ethernet-phy@13 { - reg = <13>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - - /* internal 2.5G PHY */ - phy15: ethernet-phy@15 { - reg = <15>; - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "internal"; - }; + /* external Maxlinear GPY211C */ + phy13: ethernet-phy@13 { + reg = <13>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; }; }; +&int_2p5g_phy { + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; +}; + &switch { status = "okay"; +}; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - phy-mode = "internal"; - phy-handle = <&gsw_phy0>; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-mode = "internal"; - phy-handle = <&gsw_phy1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-mode = "internal"; - phy-handle = <&gsw_phy2>; - }; - - port@3 { - reg = <3>; - label = "lan3"; - phy-mode = "internal"; - phy-handle = <&gsw_phy3>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "internal"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - }; +&gsw_phy0 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe0_led0_pins>; +}; - mdio { - #address-cells = <1>; - #size-cells = <0>; - mediatek,pio = <&pio>; - - gsw_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <0>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; - nvmem-cells = <&phy_calibration_p0>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <1>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; - nvmem-cells = <&phy_calibration_p1>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy2: ethernet-phy@2 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <2>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; - nvmem-cells = <&phy_calibration_p2>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy3: ethernet-phy@3 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <3>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; - nvmem-cells = <&phy_calibration_p3>; - nvmem-cell-names = "phy-cal-data"; - }; - }; +&gsw_phy0_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy1 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe1_led0_pins>; +}; + +&gsw_phy1_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy2 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe2_led0_pins>; +}; + +&gsw_phy2_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy3 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe3_led0_pins>; +}; + +&gsw_phy3_led0 { + status = "okay"; + color = ; }; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 94aa8251bd..462218c65d 100644 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -4,12 +4,13 @@ * Author: Sam.Shih */ -#include +#include #include +#include +#include #include -#include -#include #include +#include #include / { @@ -144,9 +145,9 @@ #size-cells = <2>; ranges; - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; + reg = <0 0x43000000 0 0x50000>; no-map; }; }; @@ -228,7 +229,7 @@ "iocfg_lb_base", "iocfg_tl_base", "eint"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 83>; + gpio-ranges = <&pio 0 0 84>; interrupt-controller; interrupts = ; interrupt-parent = <&gic>; @@ -260,47 +261,131 @@ }; }; - i2c2_pins: i2c2-pins-g0 { + i2c1_sfp_pins: i2c1-sfp-pins-g0 { + mux { + function = "i2c"; + groups = "i2c1_sfp"; + }; + }; + + i2c2_pins: i2c2-pins { + mux { + function = "i2c"; + groups = "i2c2"; + }; + }; + + i2c2_0_pins: i2c2-pins-g0 { + mux { + function = "i2c"; + groups = "i2c2_0"; + }; + }; + + i2c2_1_pins: i2c2-pins-g1 { mux { function = "i2c"; groups = "i2c2_1"; }; }; - gbe0_led0_pins: gbe0-pins { + gbe0_led0_pins: gbe0-led0-pins { mux { function = "led"; groups = "gbe0_led0"; }; }; - gbe1_led0_pins: gbe1-pins { + gbe1_led0_pins: gbe1-led0-pins { mux { function = "led"; groups = "gbe1_led0"; }; }; - gbe2_led0_pins: gbe2-pins { + gbe2_led0_pins: gbe2-led0-pins { mux { function = "led"; groups = "gbe2_led0"; }; }; - gbe3_led0_pins: gbe3-pins { + gbe3_led0_pins: gbe3-led0-pins { mux { function = "led"; groups = "gbe3_led0"; }; }; - i2p5gbe_led0_pins: 2p5gbe-pins { + gbe0_led1_pins: gbe0-led1-pins { + mux { + function = "led"; + groups = "gbe0_led1"; + }; + }; + + gbe1_led1_pins: gbe1-led1-pins { + mux { + function = "led"; + groups = "gbe1_led1"; + }; + }; + + gbe2_led1_pins: gbe2-led1-pins { + mux { + function = "led"; + groups = "gbe2_led1"; + }; + }; + + gbe3_led1_pins: gbe3-led1-pins { + mux { + function = "led"; + groups = "gbe3_led1"; + }; + }; + + i2p5gbe_led0_pins: 2p5gbe-led0-pins { mux { function = "led"; groups = "2p5gbe_led0"; }; }; + + i2p5gbe_led1_pins: 2p5gbe-led1-pins { + mux { + function = "led"; + groups = "2p5gbe_led1"; + }; + }; + + mmc0_pins_emmc_45: mmc0-pins-emmc-45 { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; + + mmc0_pins_emmc_51: mmc0-pins-emmc-51 { + mux { + function = "flash"; + groups = "emmc_51"; + }; + }; + + mmc0_pins_sdcard: mmc0-pins-sdcard { + mux { + function = "flash"; + groups = "sdcard"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; }; sgmiisys0: syscon@10060000 { @@ -380,6 +465,8 @@ <&infracfg CLK_INFRA_MUX_UART0_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, <&topckgen CLK_TOP_UART_SEL>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; status = "disabled"; }; @@ -645,6 +732,29 @@ status = "disabled"; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt7986-mmc", + "mediatek,mt7981-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11D60000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_MSDC400>, + <&infracfg CLK_INFRA_MSDC2_HCK>, + <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, + <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; + assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, + <&topckgen CLK_TOP_EMMC_400M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, + <&apmixedsys CLK_APMIXED_MSDCPLL>; + clock-names = "source", + "hclk", + "axi_cg", + "ahb_cg"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + tphy: tphy@11c50000 { compatible = "mediatek,mt7988", "mediatek,generic-tphy-v2"; @@ -747,6 +857,157 @@ interrupt-parent = <&gic>; interrupts = ; resets = <ðrst 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-mode = "internal"; + phy-handle = <&gsw_phy0>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&gsw_phy1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&gsw_phy2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&gsw_phy3>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + mediatek,pio = <&pio>; + + gsw_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <0>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p0>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy0_led0: gsw-phy0-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy0_led1: gsw-phy0-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + + gsw_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <1>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p1>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy1_led0: gsw-phy1-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy1_led1: gsw-phy1-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + + gsw_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <2>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p2>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy2_led0: gsw-phy2-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy2_led1: gsw-phy2-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + + gsw_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <3>; + phy-mode = "internal"; + nvmem-cells = <&phy_calibration_p3>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy3_led0: gsw-phy3-led0@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + + gsw_phy3_led1: gsw-phy3-led1@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + status = "disabled"; + }; + }; + }; + }; }; ethwarp: syscon@15031000 { @@ -843,6 +1104,40 @@ #address-cells = <1>; #size-cells = <0>; status = "disabled"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + }; + + gmac2: mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + }; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* internal 2.5G PHY */ + int_2p5g_phy: ethernet-phy@15 { + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; + }; + }; }; }; };