From: Luwei Kang Date: Wed, 24 Oct 2018 08:05:08 +0000 (+0800) Subject: perf/x86/intel/pt: Add new bit definitions for PT MSRs X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=69843a913fc86b3d0ef503d6cc15886ef8943626;p=openwrt%2Fstaging%2Fblogic.git perf/x86/intel/pt: Add new bit definitions for PT MSRs Add bit definitions for Intel PT MSRs to support trace output directed to the memeory subsystem and holds a count if packet bytes that have been sent out. These are required by the upcoming PT support in KVM guests for MSRs read/write emulation. Signed-off-by: Luwei Kang Signed-off-by: Paolo Bonzini --- diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 9c8618b885a0..6a900150184b 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -127,6 +127,7 @@ #define RTIT_CTL_USR BIT(3) #define RTIT_CTL_PWR_EVT_EN BIT(4) #define RTIT_CTL_FUP_ON_PTW BIT(5) +#define RTIT_CTL_FABRIC_EN BIT(6) #define RTIT_CTL_CR3EN BIT(7) #define RTIT_CTL_TOPA BIT(8) #define RTIT_CTL_MTC_EN BIT(9) @@ -155,6 +156,8 @@ #define RTIT_STATUS_BUFFOVF BIT(3) #define RTIT_STATUS_ERROR BIT(4) #define RTIT_STATUS_STOPPED BIT(5) +#define RTIT_STATUS_BYTECNT_OFFSET 32 +#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) #define MSR_IA32_RTIT_ADDR0_A 0x00000580 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 #define MSR_IA32_RTIT_ADDR1_A 0x00000582