From: Bjorn Helgaas <bhelgaas@google.com>
Date: Fri, 12 Jul 2019 22:08:37 +0000 (-0500)
Subject: Merge branch 'remotes/lorenzo/pci/tegra'
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=6bfc0c07cdb775ff5648df4afbe3ac7ce1c766ab;p=openwrt%2Fstaging%2Fblogic.git

Merge branch 'remotes/lorenzo/pci/tegra'

  - Reorganize Tegra AFI/PHY/REFCLK/etc functions (Manikanta Maddireddy)

  - Mask Tegra AFI_INTR in runtime suspend (Manikanta Maddireddy)

  - Fix Tegra AFI/PCIe powerup sequence (Manikanta Maddireddy)

  - Add Tegra124, Tegra132, Tegra210, and Tegra186 support for Gen2 link
    speed (Manikanta Maddireddy)

  - Advertise Tegra AER support (Manikanta Maddireddy)

  - Program Tegra210 UPHY settings (Manikanta Maddireddy)

  - Enable Tegra opportunistic UpdateFC and ACK (Manikanta Maddireddy)

  - Disable Tegra AFI dynamic clock gating (Manikanta Maddireddy)

  - Process Tegra pending DLL transactions before entering L1 or L2 to
    prevent receiver errors (Manikanta Maddireddy)

  - Enable Tegra xclk clock clamping in L1 (Manikanta Maddireddy)

  - Increase Tegra deskew retry time (Manikanta Maddireddy)

  - Work around Tegra hardware RAW erratum (Manikanta Maddireddy)

  - Update Tegra210 flow control timer frequency (Manikanta Maddireddy)

  - Work around Tegra Gen1/Gen2 link number negotiation issue (Manikanta
    Maddireddy)

  - Work around Tegra PLLE power down issue (Manikanta Maddireddy)

  - Program Tegra20 to support cacheable upstream transactions (Manikanta
    Maddireddy)

  - Log Tegra PRSNT_SENSE_IRQ as debug, not err (Manikanta Maddireddy)

  - Add register offset for third Root Port on Tegra186 and Tegra30
    (Manikanta Maddireddy)

  - Document Tegra PCIe DPD pinctrl property (Manikanta Maddireddy)

  - Put Tegra PEX CLK & BIAS pads in DPD mode to reduce power usage when
    powergated (Manikanta Maddireddy)

  - Add generic DT binding for "reset-gpios" property (Manikanta
    Maddireddy)

  - Add Tegra support for GPIO-based PERST# (Manikanta Maddireddy)

  - Enable Relaxed Ordering only for Tegra20 & Tegra30 (Vidya Sagar)

* remotes/lorenzo/pci/tegra:
  PCI: tegra: Enable Relaxed Ordering only for Tegra20 & Tegra30
  PCI: tegra: Change link retry log level to debug
  PCI: tegra: Add support for GPIO based PERST#
  PCI: Add DT binding for "reset-gpios" property
  PCI: tegra: Put PEX CLK & BIAS pads in DPD mode
  dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop
  PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC struct
  PCI: tegra: Change PRSNT_SENSE IRQ log to debug
  PCI: tegra: Program AFI_CACHE_BAR_{0,1}_{ST,SZ} registers only for Tegra20
  PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal
  PCI: tegra: Set target speed as Gen1 before starting LTSSM
  PCI: tegra: Update flow control timer frequency in Tegra210
  PCI: tegra: Add SW fixup for RAW violations
  PCI: tegra: Increase the deskew retry time
  PCI: tegra: Enable PCIe xclk clock clamping
  PCI: tegra: Process pending DLL transactions before entering L1 or L2
  PCI: tegra: Disable AFI dynamic clock gating
  PCI: tegra: Enable opportunistic UpdateFC and ACK
  PCI: tegra: Program UPHY electrical settings for Tegra210
  PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability
  PCI: tegra: Add PCIe Gen2 link speed support
  PCI: tegra: Fix PCIe host power up sequence
  PCI: tegra: Mask AFI_INTR in runtime suspend
  PCI: tegra: Rearrange Tegra PCIe driver functions
  PCI: tegra: Handle failure cases in tegra_pcie_power_on()
  soc/tegra: pmc: Export tegra_powergate_power_on()
---

6bfc0c07cdb775ff5648df4afbe3ac7ce1c766ab