From: Li Yang <leoli@freescale.com>
Date: Tue, 19 Jun 2007 09:33:48 +0000 (+0800)
Subject: USB: fsl_usb2_udc: fix bug for portsc bit masking
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=7542548fd843f3d49068f17a082069319f19992a;p=openwrt%2Fstaging%2Fblogic.git

USB: fsl_usb2_udc: fix bug for portsc bit masking

Fix a bug that PORT_TYPE and PORT_WIDTH aren't masked correctly in portsc.

Signed-off-by: Christopher Cason <chris.cason@nec.com.au>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
---

diff --git a/drivers/usb/gadget/fsl_usb2_udc.c b/drivers/usb/gadget/fsl_usb2_udc.c
index e4aa29fc2939..4e14bcd7c3b1 100644
--- a/drivers/usb/gadget/fsl_usb2_udc.c
+++ b/drivers/usb/gadget/fsl_usb2_udc.c
@@ -228,7 +228,7 @@ static int dr_controller_setup(struct fsl_udc *udc)
 
 	/* Config PHY interface */
 	portctrl = fsl_readl(&dr_regs->portsc1);
-	portctrl &= ~(PORTSCX_PHY_TYPE_SEL & PORTSCX_PORT_WIDTH);
+	portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
 	switch (udc->phy_mode) {
 	case FSL_USB2_PHY_ULPI:
 		portctrl |= PORTSCX_PTS_ULPI;