From: Laurent Pinchart Date: Sun, 3 Mar 2019 20:29:21 +0000 (+0200) Subject: drm: rcar-du: lvds: Adjust operating frequency for D3 and E3 X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=871370308675e477abd57a69ce66ca4730a4249c;p=openwrt%2Fstaging%2Fblogic.git drm: rcar-du: lvds: Adjust operating frequency for D3 and E3 The D3 and E3 SoCs have different pixel clock frequency limits for the LVDS encoder than the other SoCs in the Gen3 family. Adjust the mode fixup implementation accordingly. Signed-off-by: Laurent Pinchart Reviewed-by: Jacopo Mondi --- diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c index 9f5ff1acab4e..9d8058d5c20a 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c @@ -531,11 +531,16 @@ static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { + struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); + int min_freq; + /* * The internal LVDS encoder has a restricted clock frequency operating - * range (31MHz to 148.5MHz). Clamp the clock accordingly. + * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to + * 148.5MHz on all other platforms. Clamp the clock accordingly. */ - adjusted_mode->clock = clamp(adjusted_mode->clock, 31000, 148500); + min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000; + adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500); return true; }