From: Alexandre Belloni <alexandre.belloni@bootlin.com>
Date: Mon, 14 May 2018 20:04:59 +0000 (+0200)
Subject: MIPS: mscc: Connect phys to ports on ocelot_pcb123
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=8798e3921e3000a046d336920588745b6651959b;p=openwrt%2Fstaging%2Fblogic.git

MIPS: mscc: Connect phys to ports on ocelot_pcb123

Add phy to switch port connections for PCB123 for internal PHYs.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: linux-mips@linux-mips.org
Cc: netdev@vger.kernel.org
Signed-off-by: James Hogan <jhogan@kernel.org>
---

diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
index 29d6414f8886..4ccd65379059 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
@@ -25,3 +25,23 @@
 &uart2 {
 	status = "okay";
 };
+
+&mdio0 {
+	status = "okay";
+};
+
+&port0 {
+	phy-handle = <&phy0>;
+};
+
+&port1 {
+	phy-handle = <&phy1>;
+};
+
+&port2 {
+	phy-handle = <&phy2>;
+};
+
+&port3 {
+	phy-handle = <&phy3>;
+};