From: Maxim Anisimov Date: Fri, 8 Dec 2023 05:34:30 +0000 (+0300) Subject: ramips: dts: rt3352: reset FE and ESW cores together X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=8d75b1de0ff7b9e9e0138f822a5475bb8ad7fedf;p=openwrt%2Fstaging%2Fdangole.git ramips: dts: rt3352: reset FE and ESW cores together Failing to do so will cause the DMA engine to not initialize properly and fail to forward packets between them, and in some cases will cause spurious transmission with size exceeding allowed packet size, causing a kernel panic. Fixes: 60fadae62b64 ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe") Signed-off-by: Maxim Anisimov [Provide commit description, split into logical changes] Signed-off-by: Lech Perczak --- diff --git a/target/linux/ramips/dts/rt3352.dtsi b/target/linux/ramips/dts/rt3352.dtsi index 0ac3227ce0..b4829cb1b1 100644 --- a/target/linux/ramips/dts/rt3352.dtsi +++ b/target/linux/ramips/dts/rt3352.dtsi @@ -319,8 +319,8 @@ clocks = <&sysc 12>; - resets = <&sysc 21>; - reset-names = "fe"; + resets = <&sysc 21>, <&sysc 23>; + reset-names = "fe", "esw"; interrupt-parent = <&cpuintc>; interrupts = <5>; @@ -332,8 +332,8 @@ compatible = "ralink,rt3352-esw", "ralink,rt3050-esw"; reg = <0x10110000 0x8000>; - resets = <&sysc 23>, <&sysc 24>; - reset-names = "esw", "ephy"; + resets = <&sysc 24>; + reset-names = "ephy"; interrupt-parent = <&intc>; interrupts = <17>;