From: Jonas Gorski <jogo@openwrt.org>
Date: Tue, 3 Jul 2012 21:42:07 +0000 (+0000)
Subject: bcm63xx: update patches to latest upstream versions
X-Git-Tag: reboot~13469
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=988147111c71cc07c0e2080424c201cd4ded7150;p=openwrt%2Fstaging%2Fblogic.git

bcm63xx: update patches to latest upstream versions

SVN-Revision: 32591
---

diff --git a/target/linux/brcm63xx/patches-3.3/017-MIPS-BCM63XX-fix-BCM6368-IPSec-clock-bit.patch b/target/linux/brcm63xx/patches-3.3/017-MIPS-BCM63XX-fix-BCM6368-IPSec-clock-bit.patch
new file mode 100644
index 000000000000..81f87c610073
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/017-MIPS-BCM63XX-fix-BCM6368-IPSec-clock-bit.patch
@@ -0,0 +1,23 @@
+From 41ee87b6ddd525fab54e21ede506f2084bcabed3 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Wed, 25 Jan 2012 17:39:52 +0100
+Subject: [PATCH 14/63] MIPS: BCM63XX: fix BCM6368 IPSec clock bit
+
+The IPsec clock bit is 18 and not 17.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -99,7 +99,7 @@
+ #define CKCTL_6368_USBH_EN		(1 << 15)
+ #define CKCTL_6368_DISABLE_GLESS_EN	(1 << 16)
+ #define CKCTL_6368_NAND_EN		(1 << 17)
+-#define CKCTL_6368_IPSEC_EN		(1 << 17)
++#define CKCTL_6368_IPSEC_EN		(1 << 18)
+ 
+ #define CKCTL_6368_ALL_SAFE_EN		(CKCTL_6368_SWPKT_USB_EN |	\
+ 					CKCTL_6368_SWPKT_SAR_EN |	\
diff --git a/target/linux/brcm63xx/patches-3.3/018-MIPS-BCM63XX-add-support-for-ipsec-clock.patch b/target/linux/brcm63xx/patches-3.3/018-MIPS-BCM63XX-add-support-for-ipsec-clock.patch
new file mode 100644
index 000000000000..6fffc1925e06
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/018-MIPS-BCM63XX-add-support-for-ipsec-clock.patch
@@ -0,0 +1,48 @@
+From 0fec0136456ce214ea4df6b8ff3b3728befc816a Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Tue, 31 Jan 2012 15:12:22 +0100
+Subject: [PATCH 3/6] MIPS: BCM63XX: add support for "ipsec" clock
+
+This module is only available on BCM6368 so far and does not require
+resetting the block.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: mpm@selenic.com
+Cc: herbert@gondor.apana.org.au
+Patchwork: https://patchwork.linux-mips.org/patch/3324/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/clk.c |   14 ++++++++++++++
+ 1 files changed, 14 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -224,6 +224,18 @@ static struct clk clk_xtm = {
+ };
+ 
+ /*
++ * IPsec clock
++ */
++static void ipsec_set(struct clk *clk, int enable)
++{
++	bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable);
++}
++
++static struct clk clk_ipsec = {
++	.set	= ipsec_set,
++};
++
++/*
+  * Internal peripheral clock
+  */
+ static struct clk clk_periph = {
+@@ -280,6 +292,8 @@ struct clk *clk_get(struct device *dev,
+ 		return &clk_periph;
+ 	if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
+ 		return &clk_pcm;
++	if (BCMCPU_IS_6368() && !strcmp(id, "ipsec"))
++		return &clk_ipsec;
+ 	return ERR_PTR(-ENOENT);
+ }
+ 
diff --git a/target/linux/brcm63xx/patches-3.3/019-MIPS-BCM63XX-add-RNG-peripheral-definitions.patch b/target/linux/brcm63xx/patches-3.3/019-MIPS-BCM63XX-add-RNG-peripheral-definitions.patch
new file mode 100644
index 000000000000..cd7bf37e9fd7
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/019-MIPS-BCM63XX-add-RNG-peripheral-definitions.patch
@@ -0,0 +1,113 @@
+From 357761c423c0f9e4af4aafe85be7889dc36f3584 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Tue, 31 Jan 2012 15:12:23 +0100
+Subject: [PATCH 4/6] MIPS: BCM63XX: add RNG peripheral definitions
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: mpm@selenic.com
+Cc: herbert@gondor.apana.org.au
+Patchwork: https://patchwork.linux-mips.org/patch/3326/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |    9 +++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   14 ++++++++++++++
+ 2 files changed, 23 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -129,6 +129,7 @@ enum bcm63xx_regs_set {
+ 	RSET_PCMDMA,
+ 	RSET_PCMDMAC,
+ 	RSET_PCMDMAS,
++	RSET_RNG
+ };
+ 
+ #define RSET_DSL_LMEM_SIZE		(64 * 1024 * 4)
+@@ -152,6 +153,7 @@ enum bcm63xx_regs_set {
+ #define RSET_XTMDMA_SIZE		256
+ #define RSET_XTMDMAC_SIZE(chans)	(16 * (chans))
+ #define RSET_XTMDMAS_SIZE(chans)	(16 * (chans))
++#define RSET_RNG_SIZE			20
+ 
+ /*
+  * 6338 register sets base address
+@@ -195,6 +197,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6338_PCMDMA_BASE		(0xdeadbeef)
+ #define BCM_6338_PCMDMAC_BASE		(0xdeadbeef)
+ #define BCM_6338_PCMDMAS_BASE		(0xdeadbeef)
++#define BCM_6338_RNG_BASE		(0xdeadbeef)
+ 
+ /*
+  * 6345 register sets base address
+@@ -238,6 +241,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6345_PCMDMA_BASE		(0xdeadbeef)
+ #define BCM_6345_PCMDMAC_BASE		(0xdeadbeef)
+ #define BCM_6345_PCMDMAS_BASE		(0xdeadbeef)
++#define BCM_6345_RNG_BASE		(0xdeadbeef)
+ 
+ /*
+  * 6348 register sets base address
+@@ -278,6 +282,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6348_PCMDMA_BASE		(0xdeadbeef)
+ #define BCM_6348_PCMDMAC_BASE		(0xdeadbeef)
+ #define BCM_6348_PCMDMAS_BASE		(0xdeadbeef)
++#define BCM_6348_RNG_BASE		(0xdeadbeef)
+ 
+ /*
+  * 6358 register sets base address
+@@ -318,6 +323,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6358_PCMDMA_BASE		(0xfffe1800)
+ #define BCM_6358_PCMDMAC_BASE		(0xfffe1900)
+ #define BCM_6358_PCMDMAS_BASE		(0xfffe1a00)
++#define BCM_6358_RNG_BASE		(0xdeadbeef)
+ 
+ 
+ /*
+@@ -359,6 +365,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6368_PCMDMA_BASE		(0xb0005800)
+ #define BCM_6368_PCMDMAC_BASE		(0xb0005a00)
+ #define BCM_6368_PCMDMAS_BASE		(0xb0005c00)
++#define BCM_6368_RNG_BASE		(0xb0004180)
+ 
+ 
+ extern const unsigned long *bcm63xx_regs_base;
+@@ -404,6 +411,7 @@ extern const unsigned long *bcm63xx_regs
+ 	__GEN_RSET_BASE(__cpu, PCMDMA)					\
+ 	__GEN_RSET_BASE(__cpu, PCMDMAC)					\
+ 	__GEN_RSET_BASE(__cpu, PCMDMAS)					\
++	__GEN_RSET_BASE(__cpu, RNG)					\
+ 	}
+ 
+ #define __GEN_CPU_REGS_TABLE(__cpu)					\
+@@ -442,6 +450,7 @@ extern const unsigned long *bcm63xx_regs
+ 	[RSET_PCMDMA]		= BCM_## __cpu ##_PCMDMA_BASE,		\
+ 	[RSET_PCMDMAC]		= BCM_## __cpu ##_PCMDMAC_BASE,		\
+ 	[RSET_PCMDMAS]		= BCM_## __cpu ##_PCMDMAS_BASE,		\
++	[RSET_RNG]		= BCM_## __cpu ##_RNG_BASE,		\
+ 
+ 
+ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -974,6 +974,20 @@
+ #define M2M_DSTID_REG(x)		((x) * 0x40 + 0x18)
+ 
+ /*************************************************************************
++ * _REG relative to RSET_RNG
++ *************************************************************************/
++
++#define RNG_CTRL			0x00
++#define RNG_EN				(1 << 0)
++
++#define RNG_STAT			0x04
++#define RNG_AVAIL_MASK			(0xff000000)
++
++#define RNG_DATA			0x08
++#define RNG_THRES			0x0c
++#define RNG_MASK			0x10
++
++/*************************************************************************
+  * _REG relative to RSET_SPI
+  *************************************************************************/
+ 
diff --git a/target/linux/brcm63xx/patches-3.3/020-MIPS-BCM63XX-add-RNG-driver-platform_device-stub.patch b/target/linux/brcm63xx/patches-3.3/020-MIPS-BCM63XX-add-RNG-driver-platform_device-stub.patch
new file mode 100644
index 000000000000..d759c5722361
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/020-MIPS-BCM63XX-add-RNG-driver-platform_device-stub.patch
@@ -0,0 +1,71 @@
+From 79fed26f65c22e0d67c9523f7a374f0585bd2803 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Tue, 31 Jan 2012 15:12:24 +0100
+Subject: [PATCH 5/6] MIPS: BCM63XX: add RNG driver platform_device stub
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: mpm@selenic.com
+Cc: herbert@gondor.apana.org.au
+Patchwork: https://patchwork.linux-mips.org/patch/3325/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/Makefile  |    4 ++--
+ arch/mips/bcm63xx/dev-rng.c |   40 ++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 42 insertions(+), 2 deletions(-)
+ create mode 100644 arch/mips/bcm63xx/dev-rng.c
+
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -1,6 +1,6 @@
+ obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
+-		   dev-dsp.o dev-enet.o dev-pcmcia.o dev-spi.o dev-uart.o \
+-		   dev-wdt.o
++		   dev-dsp.o dev-enet.o dev-pcmcia.o dev-rng.o dev-spi.o \
++		   dev-uart.o dev-wdt.o
+ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+ 
+ obj-y		+= boards/
+--- /dev/null
++++ b/arch/mips/bcm63xx/dev-rng.c
+@@ -0,0 +1,40 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2011 Florian Fainelli <florian@openwrt.org>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <bcm63xx_cpu.h>
++
++static struct resource rng_resources[] = {
++	{
++		.start		= -1, /* filled at runtime */
++		.end		= -1, /* filled at runtime */
++		.flags		= IORESOURCE_MEM,
++	},
++};
++
++static struct platform_device bcm63xx_rng_device = {
++	.name		= "bcm63xx-rng",
++	.id		= -1,
++	.num_resources	= ARRAY_SIZE(rng_resources),
++	.resource	= rng_resources,
++};
++
++int __init bcm63xx_rng_register(void)
++{
++	if (!BCMCPU_IS_6368())
++		return -ENODEV;
++
++	rng_resources[0].start = bcm63xx_regset_address(RSET_RNG);
++	rng_resources[0].end = rng_resources[0].start;
++	rng_resources[0].end += RSET_RNG_SIZE - 1;
++
++	return platform_device_register(&bcm63xx_rng_device);
++}
++arch_initcall(bcm63xx_rng_register);
diff --git a/target/linux/brcm63xx/patches-3.3/021-hw_random-add-Broadcom-BCM63xx-RNG-driver.patch b/target/linux/brcm63xx/patches-3.3/021-hw_random-add-Broadcom-BCM63xx-RNG-driver.patch
new file mode 100644
index 000000000000..7e66fd52a088
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/021-hw_random-add-Broadcom-BCM63xx-RNG-driver.patch
@@ -0,0 +1,229 @@
+From 1cfc5c76c5f48359716bd804daef2f2f7554fb4a Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Tue, 31 Jan 2012 15:12:25 +0100
+Subject: [PATCH 6/6] hw_random: add Broadcom BCM63xx RNG driver
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: mpm@selenic.com
+Cc: herbert@gondor.apana.org.au
+Patchwork: https://patchwork.linux-mips.org/patch/3327/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ drivers/char/hw_random/Kconfig       |   14 +++
+ drivers/char/hw_random/Makefile      |    1 +
+ drivers/char/hw_random/bcm63xx-rng.c |  175 ++++++++++++++++++++++++++++++++++
+ 3 files changed, 190 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/char/hw_random/bcm63xx-rng.c
+
+--- a/drivers/char/hw_random/Kconfig
++++ b/drivers/char/hw_random/Kconfig
+@@ -73,6 +73,20 @@ config HW_RANDOM_ATMEL
+ 
+ 	  If unsure, say Y.
+ 
++config HW_RANDOM_BCM63XX
++	tristate "Broadcom BCM63xx Random Number Generator support"
++	depends on HW_RANDOM && BCM63XX
++	default HW_RANDOM
++	---help---
++	  This driver provides kernel-side support for the Random Number
++	  Generator hardware found on the Broadcom BCM63xx SoCs.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called bcm63xx-rng
++
++	  If unusure, say Y.
++
++
+ config HW_RANDOM_GEODE
+ 	tristate "AMD Geode HW Random Number Generator support"
+ 	depends on HW_RANDOM && X86_32 && PCI
+--- a/drivers/char/hw_random/Makefile
++++ b/drivers/char/hw_random/Makefile
+@@ -8,6 +8,7 @@ obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += ti
+ obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o
+ obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o
+ obj-$(CONFIG_HW_RANDOM_ATMEL) += atmel-rng.o
++obj-$(CONFIG_HW_RANDOM_BCM63XX)	+= bcm63xx-rng.o
+ obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o
+ obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o
+ n2-rng-y := n2-drv.o n2-asm.o
+--- /dev/null
++++ b/drivers/char/hw_random/bcm63xx-rng.c
+@@ -0,0 +1,175 @@
++/*
++ * Broadcom BCM63xx Random Number Generator support
++ *
++ * Copyright (C) 2011, Florian Fainelli <florian@openwrt.org>
++ * Copyright (C) 2009, Broadcom Corporation
++ *
++ */
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/io.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <linux/hw_random.h>
++
++#include <bcm63xx_io.h>
++#include <bcm63xx_regs.h>
++
++struct bcm63xx_rng_priv {
++	struct clk *clk;
++	void __iomem *regs;
++};
++
++#define to_rng_priv(rng)	((struct bcm63xx_rng_priv *)rng->priv)
++
++static int bcm63xx_rng_init(struct hwrng *rng)
++{
++	struct bcm63xx_rng_priv *priv = to_rng_priv(rng);
++	u32 val;
++
++	val = bcm_readl(priv->regs + RNG_CTRL);
++	val |= RNG_EN;
++	bcm_writel(val, priv->regs + RNG_CTRL);
++
++	return 0;
++}
++
++static void bcm63xx_rng_cleanup(struct hwrng *rng)
++{
++	struct bcm63xx_rng_priv *priv = to_rng_priv(rng);
++	u32 val;
++
++	val = bcm_readl(priv->regs + RNG_CTRL);
++	val &= ~RNG_EN;
++	bcm_writel(val, priv->regs + RNG_CTRL);
++}
++
++static int bcm63xx_rng_data_present(struct hwrng *rng, int wait)
++{
++	struct bcm63xx_rng_priv *priv = to_rng_priv(rng);
++
++	return bcm_readl(priv->regs + RNG_STAT) & RNG_AVAIL_MASK;
++}
++
++static int bcm63xx_rng_data_read(struct hwrng *rng, u32 *data)
++{
++	struct bcm63xx_rng_priv *priv = to_rng_priv(rng);
++
++	*data = bcm_readl(priv->regs + RNG_DATA);
++
++	return 4;
++}
++
++static int __init bcm63xx_rng_probe(struct platform_device *pdev)
++{
++	struct resource *r;
++	struct clk *clk;
++	int ret;
++	struct bcm63xx_rng_priv *priv;
++	struct hwrng *rng;
++
++	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!r) {
++		dev_err(&pdev->dev, "no iomem resource\n");
++		ret = -ENXIO;
++		goto out;
++	}
++
++	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
++	if (!priv) {
++		dev_err(&pdev->dev, "no memory for private structure\n");
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	rng = kzalloc(sizeof(*rng), GFP_KERNEL);
++	if (!rng) {
++		dev_err(&pdev->dev, "no memory for rng structure\n");
++		ret = -ENOMEM;
++		goto out_free_priv;
++	}
++
++	platform_set_drvdata(pdev, rng);
++	rng->priv = (unsigned long)priv;
++	rng->name = pdev->name;
++	rng->init = bcm63xx_rng_init;
++	rng->cleanup = bcm63xx_rng_cleanup;
++	rng->data_present = bcm63xx_rng_data_present;
++	rng->data_read = bcm63xx_rng_data_read;
++
++	clk = clk_get(&pdev->dev, "ipsec");
++	if (IS_ERR(clk)) {
++		dev_err(&pdev->dev, "no clock for device\n");
++		ret = PTR_ERR(clk);
++		goto out_free_rng;
++	}
++
++	priv->clk = clk;
++
++	if (!devm_request_mem_region(&pdev->dev, r->start,
++					resource_size(r), pdev->name)) {
++		dev_err(&pdev->dev, "request mem failed");
++		ret = -ENOMEM;
++		goto out_free_rng;
++	}
++
++	priv->regs = devm_ioremap_nocache(&pdev->dev, r->start,
++					resource_size(r));
++	if (!priv->regs) {
++		dev_err(&pdev->dev, "ioremap failed");
++		ret = -ENOMEM;
++		goto out_free_rng;
++	}
++
++	clk_enable(clk);
++
++	ret = hwrng_register(rng);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to register rng device\n");
++		goto out_clk_disable;
++	}
++
++	dev_info(&pdev->dev, "registered RNG driver\n");
++
++	return 0;
++
++out_clk_disable:
++	clk_disable(clk);
++out_free_rng:
++	platform_set_drvdata(pdev, NULL);
++	kfree(rng);
++out_free_priv:
++	kfree(priv);
++out:
++	return ret;
++}
++
++static int __devexit bcm63xx_rng_remove(struct platform_device *pdev)
++{
++	struct hwrng *rng = platform_get_drvdata(pdev);
++	struct bcm63xx_rng_priv *priv = to_rng_priv(rng);
++
++	hwrng_unregister(rng);
++	clk_disable(priv->clk);
++	kfree(priv);
++	kfree(rng);
++	platform_set_drvdata(pdev, NULL);
++
++	return 0;
++}
++
++static struct platform_driver bcm63xx_rng_driver = {
++	.probe		= bcm63xx_rng_probe,
++	.remove		= __devexit_p(bcm63xx_rng_remove),
++	.driver		= {
++		.name	= "bcm63xx-rng",
++		.owner	= THIS_MODULE,
++	},
++};
++
++module_platform_driver(bcm63xx_rng_driver);
++
++MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
++MODULE_DESCRIPTION("Broadcom BCM63xx RNG driver");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/brcm63xx/patches-3.3/022-MIPS-BCM63XX-Move-flash-registration-out-of-board_bc.patch b/target/linux/brcm63xx/patches-3.3/022-MIPS-BCM63XX-Move-flash-registration-out-of-board_bc.patch
new file mode 100644
index 000000000000..e9c85a2a6645
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/022-MIPS-BCM63XX-Move-flash-registration-out-of-board_bc.patch
@@ -0,0 +1,202 @@
+From bfe47f0f68b5f7a3a92d07266cba58b188fe10e7 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Tue, 12 Jun 2012 10:23:38 +0200
+Subject: [PATCH 1/8] MIPS: BCM63XX: Move flash registration out of board_bcm963xx.c
+
+board_bcm963xx.c is already large enough.
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Maxime Bizon <mbizon@freebox.fr>
+Cc: Florian Fainelli <florian@openwrt.org>
+Cc: Kevin Cernekee <cernekee@gmail.com>
+Patchwork: https://patchwork.linux-mips.org/patch/3952/
+Reviewed-by: Florian Fainelli <florian@openwrt.org>
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/Makefile                         |    4 +-
+ arch/mips/bcm63xx/boards/board_bcm963xx.c          |   49 +-------------
+ arch/mips/bcm63xx/dev-flash.c                      |   69 ++++++++++++++++++++
+ .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h   |    6 ++
+ 4 files changed, 79 insertions(+), 49 deletions(-)
+ create mode 100644 arch/mips/bcm63xx/dev-flash.c
+ create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
+
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -1,6 +1,6 @@
+ obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
+-		   dev-dsp.o dev-enet.o dev-pcmcia.o dev-rng.o dev-spi.o \
+-		   dev-uart.o dev-wdt.o
++		   dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \
++		   dev-spi.o dev-uart.o dev-wdt.o
+ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+ 
+ obj-y		+= boards/
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -11,9 +11,6 @@
+ #include <linux/kernel.h>
+ #include <linux/string.h>
+ #include <linux/platform_device.h>
+-#include <linux/mtd/mtd.h>
+-#include <linux/mtd/partitions.h>
+-#include <linux/mtd/physmap.h>
+ #include <linux/ssb/ssb.h>
+ #include <asm/addrspace.h>
+ #include <bcm63xx_board.h>
+@@ -24,6 +21,7 @@
+ #include <bcm63xx_dev_pci.h>
+ #include <bcm63xx_dev_enet.h>
+ #include <bcm63xx_dev_dsp.h>
++#include <bcm63xx_dev_flash.h>
+ #include <bcm63xx_dev_pcmcia.h>
+ #include <bcm63xx_dev_spi.h>
+ #include <board_bcm963xx.h>
+@@ -809,40 +807,6 @@ void __init board_setup(void)
+ 		panic("unexpected CPU for bcm963xx board");
+ }
+ 
+-static struct mtd_partition mtd_partitions[] = {
+-	{
+-		.name		= "cfe",
+-		.offset		= 0x0,
+-		.size		= 0x40000,
+-	}
+-};
+-
+-static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL };
+-
+-static struct physmap_flash_data flash_data = {
+-	.width			= 2,
+-	.nr_parts		= ARRAY_SIZE(mtd_partitions),
+-	.parts			= mtd_partitions,
+-	.part_probe_types	= bcm63xx_part_types,
+-};
+-
+-static struct resource mtd_resources[] = {
+-	{
+-		.start		= 0,	/* filled at runtime */
+-		.end		= 0,	/* filled at runtime */
+-		.flags		= IORESOURCE_MEM,
+-	}
+-};
+-
+-static struct platform_device mtd_dev = {
+-	.name			= "physmap-flash",
+-	.resource		= mtd_resources,
+-	.num_resources		= ARRAY_SIZE(mtd_resources),
+-	.dev			= {
+-		.platform_data	= &flash_data,
+-	},
+-};
+-
+ static struct gpio_led_platform_data bcm63xx_led_data;
+ 
+ static struct platform_device bcm63xx_gpio_leds = {
+@@ -856,8 +820,6 @@ static struct platform_device bcm63xx_gp
+  */
+ int __init board_register_devices(void)
+ {
+-	u32 val;
+-
+ 	if (board.has_uart0)
+ 		bcm63xx_uart_register(0);
+ 
+@@ -893,14 +855,7 @@ int __init board_register_devices(void)
+ 
+ 	bcm63xx_spi_register();
+ 
+-	/* read base address of boot chip select (0) */
+-	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+-	val &= MPI_CSBASE_BASE_MASK;
+-
+-	mtd_resources[0].start = val;
+-	mtd_resources[0].end = 0x1FFFFFFF;
+-
+-	platform_device_register(&mtd_dev);
++	bcm63xx_flash_register();
+ 
+ 	bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);
+ 	bcm63xx_led_data.leds = board.leds;
+--- /dev/null
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -0,0 +1,69 @@
++/*
++ * Broadcom BCM63xx flash registration
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/mtd/physmap.h>
++
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_dev_flash.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++
++static struct mtd_partition mtd_partitions[] = {
++	{
++		.name		= "cfe",
++		.offset		= 0x0,
++		.size		= 0x40000,
++	}
++};
++
++static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL };
++
++static struct physmap_flash_data flash_data = {
++	.width			= 2,
++	.parts			= mtd_partitions,
++	.part_probe_types	= bcm63xx_part_types,
++};
++
++static struct resource mtd_resources[] = {
++	{
++		.start		= 0,	/* filled at runtime */
++		.end		= 0,	/* filled at runtime */
++		.flags		= IORESOURCE_MEM,
++	}
++};
++
++static struct platform_device mtd_dev = {
++	.name			= "physmap-flash",
++	.resource		= mtd_resources,
++	.num_resources		= ARRAY_SIZE(mtd_resources),
++	.dev			= {
++		.platform_data	= &flash_data,
++	},
++};
++
++int __init bcm63xx_flash_register(void)
++{
++	u32 val;
++
++	/* read base address of boot chip select (0) */
++	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
++	val &= MPI_CSBASE_BASE_MASK;
++
++	mtd_resources[0].start = val;
++	mtd_resources[0].end = 0x1FFFFFFF;
++
++	return platform_device_register(&mtd_dev);
++}
+--- /dev/null
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
+@@ -0,0 +1,6 @@
++#ifndef __BCM63XX_FLASH_H
++#define __BCM63XX_FLASH_H
++
++int __init bcm63xx_flash_register(void);
++
++#endif /* __BCM63XX_FLASH_H */
diff --git a/target/linux/brcm63xx/patches-3.3/023-MIPS-BCM63XX-Add-flash-type-detection.patch b/target/linux/brcm63xx/patches-3.3/023-MIPS-BCM63XX-Add-flash-type-detection.patch
new file mode 100644
index 000000000000..b0f13abbafb0
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/023-MIPS-BCM63XX-Add-flash-type-detection.patch
@@ -0,0 +1,137 @@
+From 0c921d542eb4359791cffd1737bf45184f6ae352 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Tue, 12 Jun 2012 10:23:39 +0200
+Subject: [PATCH 2/8] MIPS: BCM63XX: Add flash type detection
+
+On BCM6358 and BCM6368 the attached flash type is exposed through a
+bootstrapping register. Use it for auto detecting the flash type on
+those and default to parallel flash for earlier SoCs.
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Maxime Bizon <mbizon@freebox.fr>
+Cc: Florian Fainelli <florian@openwrt.org>
+Cc: Kevin Cernekee <cernekee@gmail.com>
+Patchwork: https://patchwork.linux-mips.org/patch/3954/
+Reviewed-by: Florian Fainelli <florian@openwrt.org>
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/dev-flash.c                      |   60 ++++++++++++++++++--
+ .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h   |    6 ++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h  |    9 +++
+ 3 files changed, 69 insertions(+), 6 deletions(-)
+
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -7,6 +7,7 @@
+  *
+  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+  * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
++ * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
+  */
+ 
+ #include <linux/init.h>
+@@ -54,16 +55,63 @@ static struct platform_device mtd_dev =
+ 	},
+ };
+ 
+-int __init bcm63xx_flash_register(void)
++static int __init bcm63xx_detect_flash_type(void)
+ {
+ 	u32 val;
+ 
+-	/* read base address of boot chip select (0) */
+-	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+-	val &= MPI_CSBASE_BASE_MASK;
++	switch (bcm63xx_get_cpu_id()) {
++	case BCM6338_CPU_ID:
++	case BCM6345_CPU_ID:
++	case BCM6348_CPU_ID:
++		/* no way to auto detect so assume parallel */
++		return BCM63XX_FLASH_TYPE_PARALLEL;
++	case BCM6358_CPU_ID:
++		val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
++		if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)
++			return BCM63XX_FLASH_TYPE_PARALLEL;
++		else
++			return BCM63XX_FLASH_TYPE_SERIAL;
++	case BCM6368_CPU_ID:
++		val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
++		switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
++		case STRAPBUS_6368_BOOT_SEL_NAND:
++			return BCM63XX_FLASH_TYPE_NAND;
++		case STRAPBUS_6368_BOOT_SEL_SERIAL:
++			return BCM63XX_FLASH_TYPE_SERIAL;
++		case STRAPBUS_6368_BOOT_SEL_PARALLEL:
++			return BCM63XX_FLASH_TYPE_PARALLEL;
++		}
++	default:
++		return -EINVAL;
++	}
++}
++
++int __init bcm63xx_flash_register(void)
++{
++	int flash_type;
++	u32 val;
+ 
+-	mtd_resources[0].start = val;
+-	mtd_resources[0].end = 0x1FFFFFFF;
++	flash_type = bcm63xx_detect_flash_type();
+ 
+-	return platform_device_register(&mtd_dev);
++	switch (flash_type) {
++	case BCM63XX_FLASH_TYPE_PARALLEL:
++		/* read base address of boot chip select (0) */
++		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
++		val &= MPI_CSBASE_BASE_MASK;
++
++		mtd_resources[0].start = val;
++		mtd_resources[0].end = 0x1FFFFFFF;
++
++		return platform_device_register(&mtd_dev);
++	case BCM63XX_FLASH_TYPE_SERIAL:
++		pr_warn("unsupported serial flash detected\n");
++		return -ENODEV;
++	case BCM63XX_FLASH_TYPE_NAND:
++		pr_warn("unsupported NAND flash detected\n");
++		return -ENODEV;
++	default:
++		pr_err("flash detection failed for BCM%x: %d\n",
++		       bcm63xx_get_cpu_id(), flash_type);
++		return -ENODEV;
++	}
+ }
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
+@@ -1,6 +1,12 @@
+ #ifndef __BCM63XX_FLASH_H
+ #define __BCM63XX_FLASH_H
+ 
++enum {
++	BCM63XX_FLASH_TYPE_PARALLEL,
++	BCM63XX_FLASH_TYPE_SERIAL,
++	BCM63XX_FLASH_TYPE_NAND,
++};
++
+ int __init bcm63xx_flash_register(void);
+ 
+ #endif /* __BCM63XX_FLASH_H */
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -507,6 +507,15 @@
+ #define GPIO_BASEMODE_6368_MASK		0x7
+ /* those bits must be kept as read in gpio basemode register*/
+ 
++#define GPIO_STRAPBUS_REG		0x40
++#define STRAPBUS_6358_BOOT_SEL_PARALLEL	(1 << 1)
++#define STRAPBUS_6358_BOOT_SEL_SERIAL	(0 << 1)
++#define STRAPBUS_6368_BOOT_SEL_MASK	0x3
++#define STRAPBUS_6368_BOOT_SEL_NAND	0
++#define STRAPBUS_6368_BOOT_SEL_SERIAL	1
++#define STRAPBUS_6368_BOOT_SEL_PARALLEL	3
++
++
+ /*************************************************************************
+  * _REG relative to RSET_ENET
+  *************************************************************************/
diff --git a/target/linux/brcm63xx/patches-3.3/024-MIPS-BCM63XX-Use-the-Chip-ID-register-for-identifyin.patch b/target/linux/brcm63xx/patches-3.3/024-MIPS-BCM63XX-Use-the-Chip-ID-register-for-identifyin.patch
new file mode 100644
index 000000000000..e45a0d1634ce
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/024-MIPS-BCM63XX-Use-the-Chip-ID-register-for-identifyin.patch
@@ -0,0 +1,53 @@
+From a9168d99658bd050e49afc06880d140e2fc2c231 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Tue, 12 Jun 2012 10:23:40 +0200
+Subject: [PATCH 3/8] MIPS: BCM63XX: Use the Chip ID register for identifying the SoC
+
+Newer BCM63XX SoCs use virtually the same CPU ID, differing only in the
+revision bits. But since they all have the Chip ID register at the same
+location, we can use that to identify the SoC we are running on.
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Maxime Bizon <mbizon@freebox.fr>
+Cc: Florian Fainelli <florian@openwrt.org>
+Cc: Kevin Cernekee <cernekee@gmail.com>
+Patchwork: https://patchwork.linux-mips.org/patch/3955/
+Reviewed-by: Florian Fainelli <florian@openwrt.org>
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/cpu.c |   20 ++++++++++++--------
+ 1 files changed, 12 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -228,17 +228,21 @@ void __init bcm63xx_cpu_init(void)
+ 		bcm63xx_irqs = bcm6345_irqs;
+ 		break;
+ 	case CPU_BMIPS4350:
+-		switch (read_c0_prid() & 0xf0) {
+-		case 0x10:
++		if ((read_c0_prid() & 0xf0) == 0x10) {
+ 			expected_cpu_id = BCM6358_CPU_ID;
+ 			bcm63xx_regs_base = bcm6358_regs_base;
+ 			bcm63xx_irqs = bcm6358_irqs;
+-			break;
+-		case 0x30:
+-			expected_cpu_id = BCM6368_CPU_ID;
+-			bcm63xx_regs_base = bcm6368_regs_base;
+-			bcm63xx_irqs = bcm6368_irqs;
+-			break;
++		} else {
++			/* all newer chips have the same chip id location */
++			u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
++
++			switch (chip_id) {
++			case BCM6368_CPU_ID:
++				expected_cpu_id = BCM6368_CPU_ID;
++				bcm63xx_regs_base = bcm6368_regs_base;
++				bcm63xx_irqs = bcm6368_irqs;
++				break;
++			}
+ 		}
+ 		break;
+ 	}
diff --git a/target/linux/brcm63xx/patches-3.3/025-MIPS-BCM63XX-Add-basic-BCM6328-support.patch b/target/linux/brcm63xx/patches-3.3/025-MIPS-BCM63XX-Add-basic-BCM6328-support.patch
new file mode 100644
index 000000000000..a64eca85b8db
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/025-MIPS-BCM63XX-Add-basic-BCM6328-support.patch
@@ -0,0 +1,590 @@
+From 8f9ed2e5502ed3ba3d4c89678cb44f43ccd5b9e0 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Wed, 13 Jun 2012 16:46:54 +0100
+Subject: [PATCH 4/8] MIPS: BCM63XX: Add basic BCM6328 support
+
+This includes CPU speed, memory size detection and working UART, but
+lacking the appropriate drivers, no support for attached flash.
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Maxime Bizon <mbizon@freebox.fr>
+Cc: Florian Fainelli <florian@openwrt.org>
+Cc: Kevin Cernekee <cernekee@gmail.com>
+Patchwork: https://patchwork.linux-mips.org/patch/3951/
+Reviewed-by: Florian Fainelli <florian@openwrt.org>
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/Kconfig                         |    3 +
+ arch/mips/bcm63xx/boards/board_bcm963xx.c         |   12 ++-
+ arch/mips/bcm63xx/cpu.c                           |   43 ++++++++
+ arch/mips/bcm63xx/dev-flash.c                     |    6 +
+ arch/mips/bcm63xx/dev-spi.c                       |    2 +-
+ arch/mips/bcm63xx/irq.c                           |   21 ++++
+ arch/mips/bcm63xx/prom.c                          |    4 +-
+ arch/mips/bcm63xx/setup.c                         |   13 ++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |  111 ++++++++++++++++++++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |    2 +
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h   |    2 +
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   54 ++++++++++
+ arch/mips/include/asm/mach-bcm63xx/ioremap.h      |    1 +
+ 13 files changed, 265 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -1,6 +1,9 @@
+ menu "CPU support"
+ 	depends on BCM63XX
+ 
++config BCM63XX_CPU_6328
++	bool "support 6328 CPU"
++
+ config BCM63XX_CPU_6338
+ 	bool "support 6338 CPU"
+ 	select HW_HAS_PCI
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -708,9 +708,15 @@ void __init board_prom_init(void)
+ 	char cfe_version[32];
+ 	u32 val;
+ 
+-	/* read base address of boot chip select (0) */
+-	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+-	val &= MPI_CSBASE_BASE_MASK;
++	/* read base address of boot chip select (0)
++	 * 6328 does not have MPI but boots from a fixed address
++	 */
++	if (BCMCPU_IS_6328())
++		val = 0x18000000;
++	else {
++		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
++		val &= MPI_CSBASE_BASE_MASK;
++	}
+ 	boot_addr = (u8 *)KSEG1ADDR(val);
+ 
+ 	/* dump cfe version */
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -29,6 +29,14 @@ static u16 bcm63xx_cpu_rev;
+ static unsigned int bcm63xx_cpu_freq;
+ static unsigned int bcm63xx_memory_size;
+ 
++static const unsigned long bcm6328_regs_base[] = {
++	__GEN_CPU_REGS_TABLE(6328)
++};
++
++static const int bcm6328_irqs[] = {
++	__GEN_CPU_IRQ_TABLE(6328)
++};
++
+ static const unsigned long bcm6338_regs_base[] = {
+ 	__GEN_CPU_REGS_TABLE(6338)
+ };
+@@ -99,6 +107,33 @@ unsigned int bcm63xx_get_memory_size(voi
+ static unsigned int detect_cpu_clock(void)
+ {
+ 	switch (bcm63xx_get_cpu_id()) {
++	case BCM6328_CPU_ID:
++	{
++		unsigned int tmp, mips_pll_fcvo;
++
++		tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
++		mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
++				>> STRAPBUS_6328_FCVO_SHIFT;
++
++		switch (mips_pll_fcvo) {
++		case 0x12:
++		case 0x14:
++		case 0x19:
++			return 160000000;
++		case 0x1c:
++			return 192000000;
++		case 0x13:
++		case 0x15:
++			return 200000000;
++		case 0x1a:
++			return 384000000;
++		case 0x16:
++			return 400000000;
++		default:
++			return 320000000;
++		}
++
++	}
+ 	case BCM6338_CPU_ID:
+ 		/* BCM6338 has a fixed 240 Mhz frequency */
+ 		return 240000000;
+@@ -170,6 +205,9 @@ static unsigned int detect_memory_size(v
+ 	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+ 	u32 val;
+ 
++	if (BCMCPU_IS_6328())
++		return bcm_ddr_readl(DDR_CSEND_REG) << 24;
++
+ 	if (BCMCPU_IS_6345()) {
+ 		val = bcm_sdram_readl(SDRAM_MBASE_REG);
+ 		return (val * 8 * 1024 * 1024);
+@@ -237,6 +275,11 @@ void __init bcm63xx_cpu_init(void)
+ 			u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
+ 
+ 			switch (chip_id) {
++			case BCM6328_CPU_ID:
++				expected_cpu_id = BCM6328_CPU_ID;
++				bcm63xx_regs_base = bcm6328_regs_base;
++				bcm63xx_irqs = bcm6328_irqs;
++				break;
+ 			case BCM6368_CPU_ID:
+ 				expected_cpu_id = BCM6368_CPU_ID;
+ 				bcm63xx_regs_base = bcm6368_regs_base;
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -60,6 +60,12 @@ static int __init bcm63xx_detect_flash_t
+ 	u32 val;
+ 
+ 	switch (bcm63xx_get_cpu_id()) {
++	case BCM6328_CPU_ID:
++		val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
++		if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
++			return BCM63XX_FLASH_TYPE_SERIAL;
++		else
++			return BCM63XX_FLASH_TYPE_NAND;
+ 	case BCM6338_CPU_ID:
+ 	case BCM6345_CPU_ID:
+ 	case BCM6348_CPU_ID:
+--- a/arch/mips/bcm63xx/dev-spi.c
++++ b/arch/mips/bcm63xx/dev-spi.c
+@@ -87,7 +87,7 @@ int __init bcm63xx_spi_register(void)
+ {
+ 	struct clk *periph_clk;
+ 
+-	if (BCMCPU_IS_6345())
++	if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
+ 		return -ENODEV;
+ 
+ 	periph_clk = clk_get(NULL, "periph");
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(uns
+ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
+ 
+ #ifndef BCMCPU_RUNTIME_DETECT
++#ifdef CONFIG_BCM63XX_CPU_6328
++#define irq_stat_reg		PERF_IRQSTAT_6328_REG
++#define irq_mask_reg		PERF_IRQMASK_6328_REG
++#define irq_bits		64
++#define is_ext_irq_cascaded	1
++#define ext_irq_start		(BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
++#define ext_irq_end		(BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE)
++#define ext_irq_count		4
++#define ext_irq_cfg_reg1	PERF_EXTIRQ_CFG_REG_6328
++#define ext_irq_cfg_reg2	0
++#endif
+ #ifdef CONFIG_BCM63XX_CPU_6338
+ #define irq_stat_reg		PERF_IRQSTAT_6338_REG
+ #define irq_mask_reg		PERF_IRQMASK_6338_REG
+@@ -118,6 +129,16 @@ static void bcm63xx_init_irq(void)
+ 	irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
+ 
+ 	switch (bcm63xx_get_cpu_id()) {
++	case BCM6328_CPU_ID:
++		irq_stat_addr += PERF_IRQSTAT_6328_REG;
++		irq_mask_addr += PERF_IRQMASK_6328_REG;
++		irq_bits = 64;
++		ext_irq_count = 4;
++		is_ext_irq_cascaded = 1;
++		ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
++		ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
++		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
++		break;
+ 	case BCM6338_CPU_ID:
+ 		irq_stat_addr += PERF_IRQSTAT_6338_REG;
+ 		irq_mask_addr += PERF_IRQMASK_6338_REG;
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -26,7 +26,9 @@ void __init prom_init(void)
+ 	bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
+ 
+ 	/* disable all hardware blocks clock for now */
+-	if (BCMCPU_IS_6338())
++	if (BCMCPU_IS_6328())
++		mask = CKCTL_6328_ALL_SAFE_EN;
++	else if (BCMCPU_IS_6338())
+ 		mask = CKCTL_6338_ALL_SAFE_EN;
+ 	else if (BCMCPU_IS_6345())
+ 		mask = CKCTL_6345_ALL_SAFE_EN;
+--- a/arch/mips/bcm63xx/setup.c
++++ b/arch/mips/bcm63xx/setup.c
+@@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
+ 
+ 	/* mask and clear all external irq */
+ 	switch (bcm63xx_get_cpu_id()) {
++	case BCM6328_CPU_ID:
++		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
++		break;
+ 	case BCM6338_CPU_ID:
+ 		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
+ 		break;
+@@ -95,9 +98,13 @@ void bcm63xx_machine_reboot(void)
+ 		bcm6348_a1_reboot();
+ 
+ 	printk(KERN_INFO "triggering watchdog soft-reset...\n");
+-	reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
+-	reg |= SYS_PLL_SOFT_RESET;
+-	bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
++	if (BCMCPU_IS_6328()) {
++		bcm_wdt_writel(1, WDT_SOFTRESET_REG);
++	} else {
++		reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
++		reg |= SYS_PLL_SOFT_RESET;
++		bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
++	}
+ 	while (1)
+ 		;
+ }
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -9,6 +9,7 @@
+  * compile time if only one CPU support is enabled (idea stolen from
+  * arm mach-types)
+  */
++#define BCM6328_CPU_ID		0x6328
+ #define BCM6338_CPU_ID		0x6338
+ #define BCM6345_CPU_ID		0x6345
+ #define BCM6348_CPU_ID		0x6348
+@@ -20,6 +21,19 @@ u16 __bcm63xx_get_cpu_id(void);
+ u16 bcm63xx_get_cpu_rev(void);
+ unsigned int bcm63xx_get_cpu_freq(void);
+ 
++#ifdef CONFIG_BCM63XX_CPU_6328
++# ifdef bcm63xx_get_cpu_id
++#  undef bcm63xx_get_cpu_id
++#  define bcm63xx_get_cpu_id()	__bcm63xx_get_cpu_id()
++#  define BCMCPU_RUNTIME_DETECT
++# else
++#  define bcm63xx_get_cpu_id()	BCM6328_CPU_ID
++# endif
++# define BCMCPU_IS_6328()	(bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
++#else
++# define BCMCPU_IS_6328()	(0)
++#endif
++
+ #ifdef CONFIG_BCM63XX_CPU_6338
+ # ifdef bcm63xx_get_cpu_id
+ #  undef bcm63xx_get_cpu_id
+@@ -129,7 +143,8 @@ enum bcm63xx_regs_set {
+ 	RSET_PCMDMA,
+ 	RSET_PCMDMAC,
+ 	RSET_PCMDMAS,
+-	RSET_RNG
++	RSET_RNG,
++	RSET_MISC
+ };
+ 
+ #define RSET_DSL_LMEM_SIZE		(64 * 1024 * 4)
+@@ -156,6 +171,49 @@ enum bcm63xx_regs_set {
+ #define RSET_RNG_SIZE			20
+ 
+ /*
++ * 6328 register sets base address
++ */
++#define BCM_6328_DSL_LMEM_BASE		(0xdeadbeef)
++#define BCM_6328_PERF_BASE		(0xb0000000)
++#define BCM_6328_TIMER_BASE		(0xb0000040)
++#define BCM_6328_WDT_BASE		(0xb000005c)
++#define BCM_6328_UART0_BASE             (0xb0000100)
++#define BCM_6328_UART1_BASE		(0xb0000120)
++#define BCM_6328_GPIO_BASE		(0xb0000080)
++#define BCM_6328_SPI_BASE		(0xdeadbeef)
++#define BCM_6328_UDC0_BASE		(0xdeadbeef)
++#define BCM_6328_USBDMA_BASE		(0xdeadbeef)
++#define BCM_6328_OHCI0_BASE		(0xdeadbeef)
++#define BCM_6328_OHCI_PRIV_BASE		(0xdeadbeef)
++#define BCM_6328_USBH_PRIV_BASE		(0xdeadbeef)
++#define BCM_6328_MPI_BASE		(0xdeadbeef)
++#define BCM_6328_PCMCIA_BASE		(0xdeadbeef)
++#define BCM_6328_SDRAM_REGS_BASE	(0xdeadbeef)
++#define BCM_6328_DSL_BASE		(0xb0001900)
++#define BCM_6328_UBUS_BASE		(0xdeadbeef)
++#define BCM_6328_ENET0_BASE		(0xdeadbeef)
++#define BCM_6328_ENET1_BASE		(0xdeadbeef)
++#define BCM_6328_ENETDMA_BASE		(0xb000d800)
++#define BCM_6328_ENETDMAC_BASE		(0xb000da00)
++#define BCM_6328_ENETDMAS_BASE		(0xb000dc00)
++#define BCM_6328_ENETSW_BASE		(0xb0e00000)
++#define BCM_6328_EHCI0_BASE		(0x10002500)
++#define BCM_6328_SDRAM_BASE		(0xdeadbeef)
++#define BCM_6328_MEMC_BASE		(0xdeadbeef)
++#define BCM_6328_DDR_BASE		(0xb0003000)
++#define BCM_6328_M2M_BASE		(0xdeadbeef)
++#define BCM_6328_ATM_BASE		(0xdeadbeef)
++#define BCM_6328_XTM_BASE		(0xdeadbeef)
++#define BCM_6328_XTMDMA_BASE		(0xb000b800)
++#define BCM_6328_XTMDMAC_BASE		(0xdeadbeef)
++#define BCM_6328_XTMDMAS_BASE		(0xdeadbeef)
++#define BCM_6328_PCM_BASE		(0xb000a800)
++#define BCM_6328_PCMDMA_BASE		(0xdeadbeef)
++#define BCM_6328_PCMDMAC_BASE		(0xdeadbeef)
++#define BCM_6328_PCMDMAS_BASE		(0xdeadbeef)
++#define BCM_6328_RNG_BASE		(0xdeadbeef)
++#define BCM_6328_MISC_BASE		(0xb0001800)
++/*
+  * 6338 register sets base address
+  */
+ #define BCM_6338_DSL_LMEM_BASE		(0xfff00000)
+@@ -198,6 +256,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6338_PCMDMAC_BASE		(0xdeadbeef)
+ #define BCM_6338_PCMDMAS_BASE		(0xdeadbeef)
+ #define BCM_6338_RNG_BASE		(0xdeadbeef)
++#define BCM_6338_MISC_BASE		(0xdeadbeef)
+ 
+ /*
+  * 6345 register sets base address
+@@ -242,6 +301,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6345_PCMDMAC_BASE		(0xdeadbeef)
+ #define BCM_6345_PCMDMAS_BASE		(0xdeadbeef)
+ #define BCM_6345_RNG_BASE		(0xdeadbeef)
++#define BCM_6345_MISC_BASE		(0xdeadbeef)
+ 
+ /*
+  * 6348 register sets base address
+@@ -283,6 +343,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6348_PCMDMAC_BASE		(0xdeadbeef)
+ #define BCM_6348_PCMDMAS_BASE		(0xdeadbeef)
+ #define BCM_6348_RNG_BASE		(0xdeadbeef)
++#define BCM_6348_MISC_BASE		(0xdeadbeef)
+ 
+ /*
+  * 6358 register sets base address
+@@ -324,6 +385,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6358_PCMDMAC_BASE		(0xfffe1900)
+ #define BCM_6358_PCMDMAS_BASE		(0xfffe1a00)
+ #define BCM_6358_RNG_BASE		(0xdeadbeef)
++#define BCM_6358_MISC_BASE		(0xdeadbeef)
+ 
+ 
+ /*
+@@ -366,6 +428,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6368_PCMDMAC_BASE		(0xb0005a00)
+ #define BCM_6368_PCMDMAS_BASE		(0xb0005c00)
+ #define BCM_6368_RNG_BASE		(0xb0004180)
++#define BCM_6368_MISC_BASE		(0xdeadbeef)
+ 
+ 
+ extern const unsigned long *bcm63xx_regs_base;
+@@ -412,6 +475,7 @@ extern const unsigned long *bcm63xx_regs
+ 	__GEN_RSET_BASE(__cpu, PCMDMAC)					\
+ 	__GEN_RSET_BASE(__cpu, PCMDMAS)					\
+ 	__GEN_RSET_BASE(__cpu, RNG)					\
++	__GEN_RSET_BASE(__cpu, MISC)					\
+ 	}
+ 
+ #define __GEN_CPU_REGS_TABLE(__cpu)					\
+@@ -451,6 +515,7 @@ extern const unsigned long *bcm63xx_regs
+ 	[RSET_PCMDMAC]		= BCM_## __cpu ##_PCMDMAC_BASE,		\
+ 	[RSET_PCMDMAS]		= BCM_## __cpu ##_PCMDMAS_BASE,		\
+ 	[RSET_RNG]		= BCM_## __cpu ##_RNG_BASE,		\
++	[RSET_MISC]		= BCM_## __cpu ##_MISC_BASE,		\
+ 
+ 
+ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
+@@ -458,6 +523,9 @@ static inline unsigned long bcm63xx_regs
+ #ifdef BCMCPU_RUNTIME_DETECT
+ 	return bcm63xx_regs_base[set];
+ #else
++#ifdef CONFIG_BCM63XX_CPU_6328
++	__GEN_RSET(6328)
++#endif
+ #ifdef CONFIG_BCM63XX_CPU_6338
+ 	__GEN_RSET(6338)
+ #endif
+@@ -512,6 +580,47 @@ enum bcm63xx_irq {
+ };
+ 
+ /*
++ * 6328 irqs
++ */
++#define BCM_6328_HIGH_IRQ_BASE		(IRQ_INTERNAL_BASE + 32)
++
++#define BCM_6328_TIMER_IRQ		(IRQ_INTERNAL_BASE + 31)
++#define BCM_6328_SPI_IRQ		0
++#define BCM_6328_UART0_IRQ		(IRQ_INTERNAL_BASE + 28)
++#define BCM_6328_UART1_IRQ		(BCM_6328_HIGH_IRQ_BASE + 7)
++#define BCM_6328_DSL_IRQ		(IRQ_INTERNAL_BASE + 4)
++#define BCM_6328_UDC0_IRQ		0
++#define BCM_6328_ENET0_IRQ		0
++#define BCM_6328_ENET1_IRQ		0
++#define BCM_6328_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
++#define BCM_6328_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 9)
++#define BCM_6328_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
++#define BCM_6328_PCMCIA_IRQ		0
++#define BCM_6328_ENET0_RXDMA_IRQ	0
++#define BCM_6328_ENET0_TXDMA_IRQ	0
++#define BCM_6328_ENET1_RXDMA_IRQ	0
++#define BCM_6328_ENET1_TXDMA_IRQ	0
++#define BCM_6328_PCI_IRQ		(IRQ_INTERNAL_BASE + 23)
++#define BCM_6328_ATM_IRQ		0
++#define BCM_6328_ENETSW_RXDMA0_IRQ	(BCM_6328_HIGH_IRQ_BASE + 0)
++#define BCM_6328_ENETSW_RXDMA1_IRQ	(BCM_6328_HIGH_IRQ_BASE + 1)
++#define BCM_6328_ENETSW_RXDMA2_IRQ	(BCM_6328_HIGH_IRQ_BASE + 2)
++#define BCM_6328_ENETSW_RXDMA3_IRQ	(BCM_6328_HIGH_IRQ_BASE + 3)
++#define BCM_6328_ENETSW_TXDMA0_IRQ	(BCM_6328_HIGH_IRQ_BASE + 4)
++#define BCM_6328_ENETSW_TXDMA1_IRQ	(BCM_6328_HIGH_IRQ_BASE + 5)
++#define BCM_6328_ENETSW_TXDMA2_IRQ	(BCM_6328_HIGH_IRQ_BASE + 6)
++#define BCM_6328_ENETSW_TXDMA3_IRQ	(BCM_6328_HIGH_IRQ_BASE + 7)
++#define BCM_6328_XTM_IRQ		(BCM_6328_HIGH_IRQ_BASE + 31)
++#define BCM_6328_XTM_DMA0_IRQ		(BCM_6328_HIGH_IRQ_BASE + 11)
++
++#define BCM_6328_PCM_DMA0_IRQ		(IRQ_INTERNAL_BASE + 2)
++#define BCM_6328_PCM_DMA1_IRQ		(IRQ_INTERNAL_BASE + 3)
++#define BCM_6328_EXT_IRQ0		(IRQ_INTERNAL_BASE + 24)
++#define BCM_6328_EXT_IRQ1		(IRQ_INTERNAL_BASE + 25)
++#define BCM_6328_EXT_IRQ2		(IRQ_INTERNAL_BASE + 26)
++#define BCM_6328_EXT_IRQ3		(IRQ_INTERNAL_BASE + 27)
++
++/*
+  * 6338 irqs
+  */
+ #define BCM_6338_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+@@ -8,6 +8,8 @@ int __init bcm63xx_gpio_init(void);
+ static inline unsigned long bcm63xx_gpio_count(void)
+ {
+ 	switch (bcm63xx_get_cpu_id()) {
++	case BCM6328_CPU_ID:
++		return 32;
+ 	case BCM6358_CPU_ID:
+ 		return 40;
+ 	case BCM6338_CPU_ID:
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -91,5 +91,7 @@
+ #define bcm_memc_writel(v, o)	bcm_rset_writel(RSET_MEMC, (v), (o))
+ #define bcm_ddr_readl(o)	bcm_rset_readl(RSET_DDR, (o))
+ #define bcm_ddr_writel(v, o)	bcm_rset_writel(RSET_DDR, (v), (o))
++#define bcm_misc_readl(o)	bcm_rset_readl(RSET_MISC, (o))
++#define bcm_misc_writel(v, o)	bcm_rset_writel(RSET_MISC, (v), (o))
+ 
+ #endif /* ! BCM63XX_IO_H_ */
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -15,6 +15,30 @@
+ /* Clock Control register */
+ #define PERF_CKCTL_REG			0x4
+ 
++#define CKCTL_6328_PHYMIPS_EN		(1 << 0)
++#define CKCTL_6328_ADSL_QPROC_EN	(1 << 1)
++#define CKCTL_6328_ADSL_AFE_EN		(1 << 2)
++#define CKCTL_6328_ADSL_EN		(1 << 3)
++#define CKCTL_6328_MIPS_EN		(1 << 4)
++#define CKCTL_6328_SAR_EN		(1 << 5)
++#define CKCTL_6328_PCM_EN		(1 << 6)
++#define CKCTL_6328_USBD_EN		(1 << 7)
++#define CKCTL_6328_USBH_EN		(1 << 8)
++#define CKCTL_6328_HSSPI_EN		(1 << 9)
++#define CKCTL_6328_PCIE_EN		(1 << 10)
++#define CKCTL_6328_ROBOSW_EN		(1 << 11)
++
++#define CKCTL_6328_ALL_SAFE_EN		(CKCTL_6328_PHYMIPS_EN |	\
++					CKCTL_6328_ADSL_QPROC_EN |	\
++					CKCTL_6328_ADSL_AFE_EN |	\
++					CKCTL_6328_ADSL_EN |		\
++					CKCTL_6328_SAR_EN  |		\
++					CKCTL_6328_PCM_EN  |		\
++					CKCTL_6328_USBD_EN |		\
++					CKCTL_6328_USBH_EN |		\
++					CKCTL_6328_ROBOSW_EN |		\
++					CKCTL_6328_PCIE_EN)
++
+ #define CKCTL_6338_ADSLPHY_EN		(1 << 0)
+ #define CKCTL_6338_MPI_EN		(1 << 1)
+ #define CKCTL_6338_DRAM_EN		(1 << 2)
+@@ -119,6 +143,7 @@
+ #define SYS_PLL_SOFT_RESET		0x1
+ 
+ /* Interrupt Mask register */
++#define PERF_IRQMASK_6328_REG		0x20
+ #define PERF_IRQMASK_6338_REG		0xc
+ #define PERF_IRQMASK_6345_REG		0xc
+ #define PERF_IRQMASK_6348_REG		0xc
+@@ -126,6 +151,7 @@
+ #define PERF_IRQMASK_6368_REG		0x20
+ 
+ /* Interrupt Status register */
++#define PERF_IRQSTAT_6328_REG		0x28
+ #define PERF_IRQSTAT_6338_REG		0x10
+ #define PERF_IRQSTAT_6345_REG		0x10
+ #define PERF_IRQSTAT_6348_REG		0x10
+@@ -133,6 +159,7 @@
+ #define PERF_IRQSTAT_6368_REG		0x28
+ 
+ /* External Interrupt Configuration register */
++#define PERF_EXTIRQ_CFG_REG_6328	0x18
+ #define PERF_EXTIRQ_CFG_REG_6338	0x14
+ #define PERF_EXTIRQ_CFG_REG_6348	0x14
+ #define PERF_EXTIRQ_CFG_REG_6358	0x14
+@@ -162,8 +189,21 @@
+ 
+ /* Soft Reset register */
+ #define PERF_SOFTRESET_REG		0x28
++#define PERF_SOFTRESET_6328_REG		0x10
+ #define PERF_SOFTRESET_6368_REG		0x10
+ 
++#define SOFTRESET_6328_SPI_MASK		(1 << 0)
++#define SOFTRESET_6328_EPHY_MASK	(1 << 1)
++#define SOFTRESET_6328_SAR_MASK		(1 << 2)
++#define SOFTRESET_6328_ENETSW_MASK	(1 << 3)
++#define SOFTRESET_6328_USBS_MASK	(1 << 4)
++#define SOFTRESET_6328_USBH_MASK	(1 << 5)
++#define SOFTRESET_6328_PCM_MASK		(1 << 6)
++#define SOFTRESET_6328_PCIE_CORE_MASK	(1 << 7)
++#define SOFTRESET_6328_PCIE_MASK	(1 << 8)
++#define SOFTRESET_6328_PCIE_EXT_MASK	(1 << 9)
++#define SOFTRESET_6328_PCIE_HARD_MASK	(1 << 10)
++
+ #define SOFTRESET_6338_SPI_MASK		(1 << 0)
+ #define SOFTRESET_6338_ENET_MASK	(1 << 2)
+ #define SOFTRESET_6338_USBH_MASK	(1 << 3)
+@@ -307,6 +347,8 @@
+ /* Watchdog reset length register */
+ #define WDT_RSTLEN_REG			0x8
+ 
++/* Watchdog soft reset register (BCM6328 only) */
++#define WDT_SOFTRESET_REG		0xc
+ 
+ /*************************************************************************
+  * _REG relative to RSET_UARTx
+@@ -933,6 +975,8 @@
+  * _REG relative to RSET_DDR
+  *************************************************************************/
+ 
++#define DDR_CSEND_REG			0x8
++
+ #define DDR_DMIPSPLLCFG_REG		0x18
+ #define DMIPSPLLCFG_M1_SHIFT		0
+ #define DMIPSPLLCFG_M1_MASK		(0xff << DMIPSPLLCFG_M1_SHIFT)
+@@ -1122,4 +1166,14 @@
+ #define SPI_SSOFFTIME_SHIFT		3
+ #define SPI_BYTE_SWAP			0x80
+ 
++/*************************************************************************
++ * _REG relative to RSET_MISC
++ *************************************************************************/
++
++#define MISC_STRAPBUS_6328_REG		0x240
++#define STRAPBUS_6328_FCVO_SHIFT	7
++#define STRAPBUS_6328_FCVO_MASK		(0x1f << STRAPBUS_6328_FCVO_SHIFT)
++#define STRAPBUS_6328_BOOT_SEL_SERIAL	(1 << 28)
++#define STRAPBUS_6328_BOOT_SEL_NAND	(0 << 28)
++
+ #endif /* BCM63XX_REGS_H_ */
+--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+@@ -18,6 +18,7 @@ static inline int is_bcm63xx_internal_re
+ 		if (offset >= 0xfff00000)
+ 			return 1;
+ 		break;
++	case BCM6328_CPU_ID:
+ 	case BCM6368_CPU_ID:
+ 		if (offset >= 0xb0000000 && offset < 0xb1000000)
+ 			return 1;
diff --git a/target/linux/brcm63xx/patches-3.3/026-MIPS-BCM63XX-Move-the-PCI-initialization-into-its-ow.patch b/target/linux/brcm63xx/patches-3.3/026-MIPS-BCM63XX-Move-the-PCI-initialization-into-its-ow.patch
new file mode 100644
index 000000000000..0f44b4910a6f
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/026-MIPS-BCM63XX-Move-the-PCI-initialization-into-its-ow.patch
@@ -0,0 +1,61 @@
+From b8420b9150fa03fcdfacd32e8c5ad286e208d5e9 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Wed, 13 Jun 2012 16:48:02 +0100
+Subject: [PATCH 5/8] MIPS: BCM63XX: Move the PCI initialization into its own function
+
+Also make the cpu check a bit more explicit.
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Maxime Bizon <mbizon@freebox.fr>
+Cc: Florian Fainelli <florian@openwrt.org>
+Cc: Kevin Cernekee <cernekee@gmail.com>
+Patchwork: https://patchwork.linux-mips.org/patch/3953/
+Reviewed-by: Florian Fainelli <florian@openwrt.org>
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/pci/pci-bcm63xx.c |   25 +++++++++++++++++--------
+ 1 files changed, 17 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -94,17 +94,10 @@ static void bcm63xx_int_cfg_writel(u32 v
+ 
+ void __iomem *pci_iospace_start;
+ 
+-static int __init bcm63xx_pci_init(void)
++static int __init bcm63xx_register_pci(void)
+ {
+ 	unsigned int mem_size;
+ 	u32 val;
+-
+-	if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
+-		return -ENODEV;
+-
+-	if (!bcm63xx_pci_enabled)
+-		return -ENODEV;
+-
+ 	/*
+ 	 * configuration  access are  done through  IO space,  remap 4
+ 	 * first bytes to access it from CPU.
+@@ -221,4 +214,20 @@ static int __init bcm63xx_pci_init(void)
+ 	return 0;
+ }
+ 
++
++static int __init bcm63xx_pci_init(void)
++{
++	if (!bcm63xx_pci_enabled)
++		return -ENODEV;
++
++	switch (bcm63xx_get_cpu_id()) {
++	case BCM6348_CPU_ID:
++	case BCM6358_CPU_ID:
++	case BCM6368_CPU_ID:
++		return bcm63xx_register_pci();
++	default:
++		return -ENODEV;
++	}
++}
++
+ arch_initcall(bcm63xx_pci_init);
diff --git a/target/linux/brcm63xx/patches-3.3/027-MIPS-BCM63XX-Add-PCIe-Support-for-BCM6328.patch b/target/linux/brcm63xx/patches-3.3/027-MIPS-BCM63XX-Add-PCIe-Support-for-BCM6328.patch
new file mode 100644
index 000000000000..ff375cd2a909
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/027-MIPS-BCM63XX-Add-PCIe-Support-for-BCM6328.patch
@@ -0,0 +1,427 @@
+From 45655e79f84e35c13b8964b961d804e64b3aca91 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Wed, 13 Jun 2012 17:07:13 +0100
+Subject: [PATCH 6/8] MIPS: BCM63XX: Add PCIe Support for BCM6328
+
+Add support for the PCIe port found on BCM6328.
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Maxime Bizon <mbizon@freebox.fr>
+Cc: Florian Fainelli <florian@openwrt.org>
+Cc: Kevin Cernekee <cernekee@gmail.com>
+Patchwork: https://patchwork.linux-mips.org/patch/3956/
+Reviewed-by: Florian Fainelli <florian@openwrt.org>
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/Kconfig                         |    1 +
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |    9 ++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h   |    6 +
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   54 ++++++++++
+ arch/mips/pci/ops-bcm63xx.c                       |   61 +++++++++++
+ arch/mips/pci/pci-bcm63xx.c                       |  112 +++++++++++++++++++++
+ arch/mips/pci/pci-bcm63xx.h                       |    5 +
+ 7 files changed, 248 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -3,6 +3,7 @@ menu "CPU support"
+ 
+ config BCM63XX_CPU_6328
+ 	bool "support 6328 CPU"
++	select HW_HAS_PCI
+ 
+ config BCM63XX_CPU_6338
+ 	bool "support 6338 CPU"
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -122,6 +122,7 @@ enum bcm63xx_regs_set {
+ 	RSET_USBH_PRIV,
+ 	RSET_MPI,
+ 	RSET_PCMCIA,
++	RSET_PCIE,
+ 	RSET_DSL,
+ 	RSET_ENET0,
+ 	RSET_ENET1,
+@@ -188,6 +189,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6328_USBH_PRIV_BASE		(0xdeadbeef)
+ #define BCM_6328_MPI_BASE		(0xdeadbeef)
+ #define BCM_6328_PCMCIA_BASE		(0xdeadbeef)
++#define BCM_6328_PCIE_BASE		(0xb0e40000)
+ #define BCM_6328_SDRAM_REGS_BASE	(0xdeadbeef)
+ #define BCM_6328_DSL_BASE		(0xb0001900)
+ #define BCM_6328_UBUS_BASE		(0xdeadbeef)
+@@ -232,6 +234,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6338_USBH_PRIV_BASE		(0xdeadbeef)
+ #define BCM_6338_MPI_BASE		(0xfffe3160)
+ #define BCM_6338_PCMCIA_BASE		(0xdeadbeef)
++#define BCM_6338_PCIE_BASE		(0xdeadbeef)
+ #define BCM_6338_SDRAM_REGS_BASE	(0xfffe3100)
+ #define BCM_6338_DSL_BASE		(0xfffe1000)
+ #define BCM_6338_UBUS_BASE		(0xdeadbeef)
+@@ -279,6 +282,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6345_ENETSW_BASE		(0xdeadbeef)
+ #define BCM_6345_PCMCIA_BASE		(0xfffe2028)
+ #define BCM_6345_MPI_BASE		(0xfffe2000)
++#define BCM_6345_PCIE_BASE		(0xdeadbeef)
+ #define BCM_6345_OHCI0_BASE		(0xfffe2100)
+ #define BCM_6345_OHCI_PRIV_BASE		(0xfffe2200)
+ #define BCM_6345_USBH_PRIV_BASE		(0xdeadbeef)
+@@ -320,6 +324,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6348_USBH_PRIV_BASE		(0xdeadbeef)
+ #define BCM_6348_MPI_BASE		(0xfffe2000)
+ #define BCM_6348_PCMCIA_BASE		(0xfffe2054)
++#define BCM_6348_PCIE_BASE		(0xdeadbeef)
+ #define BCM_6348_SDRAM_REGS_BASE	(0xfffe2300)
+ #define BCM_6348_M2M_BASE		(0xfffe2800)
+ #define BCM_6348_DSL_BASE		(0xfffe3000)
+@@ -362,6 +367,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6358_USBH_PRIV_BASE		(0xfffe1500)
+ #define BCM_6358_MPI_BASE		(0xfffe1000)
+ #define BCM_6358_PCMCIA_BASE		(0xfffe1054)
++#define BCM_6358_PCIE_BASE		(0xdeadbeef)
+ #define BCM_6358_SDRAM_REGS_BASE	(0xfffe2300)
+ #define BCM_6358_M2M_BASE		(0xdeadbeef)
+ #define BCM_6358_DSL_BASE		(0xfffe3000)
+@@ -405,6 +411,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6368_USBH_PRIV_BASE		(0xb0001700)
+ #define BCM_6368_MPI_BASE		(0xb0001000)
+ #define BCM_6368_PCMCIA_BASE		(0xb0001054)
++#define BCM_6368_PCIE_BASE		(0xdeadbeef)
+ #define BCM_6368_SDRAM_REGS_BASE	(0xdeadbeef)
+ #define BCM_6368_M2M_BASE		(0xdeadbeef)
+ #define BCM_6368_DSL_BASE		(0xdeadbeef)
+@@ -453,6 +460,7 @@ extern const unsigned long *bcm63xx_regs
+ 	__GEN_RSET_BASE(__cpu, USBH_PRIV)				\
+ 	__GEN_RSET_BASE(__cpu, MPI)					\
+ 	__GEN_RSET_BASE(__cpu, PCMCIA)					\
++	__GEN_RSET_BASE(__cpu, PCIE)					\
+ 	__GEN_RSET_BASE(__cpu, DSL)					\
+ 	__GEN_RSET_BASE(__cpu, ENET0)					\
+ 	__GEN_RSET_BASE(__cpu, ENET1)					\
+@@ -493,6 +501,7 @@ extern const unsigned long *bcm63xx_regs
+ 	[RSET_USBH_PRIV]	= BCM_## __cpu ##_USBH_PRIV_BASE,	\
+ 	[RSET_MPI]		= BCM_## __cpu ##_MPI_BASE,		\
+ 	[RSET_PCMCIA]		= BCM_## __cpu ##_PCMCIA_BASE,		\
++	[RSET_PCIE]		= BCM_## __cpu ##_PCIE_BASE,		\
+ 	[RSET_DSL]		= BCM_## __cpu ##_DSL_BASE,		\
+ 	[RSET_ENET0]		= BCM_## __cpu ##_ENET0_BASE,		\
+ 	[RSET_ENET1]		= BCM_## __cpu ##_ENET1_BASE,		\
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -40,6 +40,10 @@
+ #define BCM_CB_MEM_END_PA		(BCM_CB_MEM_BASE_PA +		\
+ 					BCM_CB_MEM_SIZE - 1)
+ 
++#define BCM_PCIE_MEM_BASE_PA		0x10f00000
++#define BCM_PCIE_MEM_SIZE		(16 * 1024 * 1024)
++#define BCM_PCIE_MEM_END_PA		(BCM_PCIE_MEM_BASE_PA +		\
++					BCM_PCIE_MEM_SIZE - 1)
+ 
+ /*
+  * Internal registers are accessed through KSEG3
+@@ -85,6 +89,8 @@
+ #define bcm_mpi_writel(v, o)	bcm_rset_writel(RSET_MPI, (v), (o))
+ #define bcm_pcmcia_readl(o)	bcm_rset_readl(RSET_PCMCIA, (o))
+ #define bcm_pcmcia_writel(v, o)	bcm_rset_writel(RSET_PCMCIA, (v), (o))
++#define bcm_pcie_readl(o)	bcm_rset_readl(RSET_PCIE, (o))
++#define bcm_pcie_writel(v, o)	bcm_rset_writel(RSET_PCIE, (v), (o))
+ #define bcm_sdram_readl(o)	bcm_rset_readl(RSET_SDRAM, (o))
+ #define bcm_sdram_writel(v, o)	bcm_rset_writel(RSET_SDRAM, (v), (o))
+ #define bcm_memc_readl(o)	bcm_rset_readl(RSET_MEMC, (o))
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1169,6 +1169,9 @@
+ /*************************************************************************
+  * _REG relative to RSET_MISC
+  *************************************************************************/
++#define MISC_SERDES_CTRL_REG		0x0
++#define SERDES_PCIE_EN			(1 << 0)
++#define SERDES_PCIE_EXD_EN		(1 << 15)
+ 
+ #define MISC_STRAPBUS_6328_REG		0x240
+ #define STRAPBUS_6328_FCVO_SHIFT	7
+@@ -1176,4 +1179,55 @@
+ #define STRAPBUS_6328_BOOT_SEL_SERIAL	(1 << 28)
+ #define STRAPBUS_6328_BOOT_SEL_NAND	(0 << 28)
+ 
++/*************************************************************************
++ * _REG relative to RSET_PCIE
++ *************************************************************************/
++
++#define PCIE_CONFIG2_REG		0x408
++#define CONFIG2_BAR1_SIZE_EN		1
++#define CONFIG2_BAR1_SIZE_MASK		0xf
++
++#define PCIE_IDVAL3_REG			0x43c
++#define IDVAL3_CLASS_CODE_MASK		0xffffff
++#define IDVAL3_SUBCLASS_SHIFT		8
++#define IDVAL3_CLASS_SHIFT		16
++
++#define PCIE_DLSTATUS_REG		0x1048
++#define DLSTATUS_PHYLINKUP		(1 << 13)
++
++#define PCIE_BRIDGE_OPT1_REG		0x2820
++#define OPT1_RD_BE_OPT_EN		(1 << 7)
++#define OPT1_RD_REPLY_BE_FIX_EN		(1 << 9)
++#define OPT1_PCIE_BRIDGE_HOLE_DET_EN	(1 << 11)
++#define OPT1_L1_INT_STATUS_MASK_POL	(1 << 12)
++
++#define PCIE_BRIDGE_OPT2_REG		0x2824
++#define OPT2_UBUS_UR_DECODE_DIS		(1 << 2)
++#define OPT2_TX_CREDIT_CHK_EN		(1 << 4)
++#define OPT2_CFG_TYPE1_BD_SEL		(1 << 7)
++#define OPT2_CFG_TYPE1_BUS_NO_SHIFT	16
++#define OPT2_CFG_TYPE1_BUS_NO_MASK	(0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
++
++#define PCIE_BRIDGE_BAR0_BASEMASK_REG	0x2828
++#define PCIE_BRIDGE_BAR1_BASEMASK_REG	0x2830
++#define BASEMASK_REMAP_EN		(1 << 0)
++#define BASEMASK_SWAP_EN		(1 << 1)
++#define BASEMASK_MASK_SHIFT		4
++#define BASEMASK_MASK_MASK		(0xfff << BASEMASK_MASK_SHIFT)
++#define BASEMASK_BASE_SHIFT		20
++#define BASEMASK_BASE_MASK		(0xfff << BASEMASK_BASE_SHIFT)
++
++#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
++#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
++#define REBASE_ADDR_BASE_SHIFT		20
++#define REBASE_ADDR_BASE_MASK		(0xfff << REBASE_ADDR_BASE_SHIFT)
++
++#define PCIE_BRIDGE_RC_INT_MASK_REG	0x2854
++#define PCIE_RC_INT_A			(1 << 0)
++#define PCIE_RC_INT_B			(1 << 1)
++#define PCIE_RC_INT_C			(1 << 2)
++#define PCIE_RC_INT_D			(1 << 3)
++
++#define PCIE_DEVICE_OFFSET		0x8000
++
+ #endif /* BCM63XX_REGS_H_ */
+--- a/arch/mips/pci/ops-bcm63xx.c
++++ b/arch/mips/pci/ops-bcm63xx.c
+@@ -465,3 +465,64 @@ static void bcm63xx_fixup(struct pci_dev
+ 
+ DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
+ #endif
++
++static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
++{
++	switch (bus->number) {
++	case PCIE_BUS_BRIDGE:
++		return (PCI_SLOT(devfn) == 0);
++	case PCIE_BUS_DEVICE:
++		if (PCI_SLOT(devfn) == 0)
++			return bcm_pcie_readl(PCIE_DLSTATUS_REG)
++					& DLSTATUS_PHYLINKUP;
++	default:
++		return false;
++	}
++}
++
++static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn,
++			     int where, int size, u32 *val)
++{
++	u32 data;
++	u32 reg = where & ~3;
++
++	if (!bcm63xx_pcie_can_access(bus, devfn))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	if (bus->number == PCIE_BUS_DEVICE)
++		reg += PCIE_DEVICE_OFFSET;
++
++	data = bcm_pcie_readl(reg);
++
++	*val = postprocess_read(data, where, size);
++
++	return PCIBIOS_SUCCESSFUL;
++
++}
++
++static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
++			      int where, int size, u32 val)
++{
++	u32 data;
++	u32 reg = where & ~3;
++
++	if (!bcm63xx_pcie_can_access(bus, devfn))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	if (bus->number == PCIE_BUS_DEVICE)
++		reg += PCIE_DEVICE_OFFSET;
++
++
++	data = bcm_pcie_readl(reg);
++
++	data = preprocess_write(data, val, where, size);
++	bcm_pcie_writel(data, reg);
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++
++struct pci_ops bcm63xx_pcie_ops = {
++	.read   = bcm63xx_pcie_read,
++	.write  = bcm63xx_pcie_write
++};
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -10,6 +10,7 @@
+ #include <linux/pci.h>
+ #include <linux/kernel.h>
+ #include <linux/init.h>
++#include <linux/delay.h>
+ #include <asm/bootinfo.h>
+ 
+ #include "pci-bcm63xx.h"
+@@ -71,6 +72,26 @@ struct pci_controller bcm63xx_cb_control
+ };
+ #endif
+ 
++static struct resource bcm_pcie_mem_resource = {
++	.name   = "bcm63xx PCIe memory space",
++	.start  = BCM_PCIE_MEM_BASE_PA,
++	.end    = BCM_PCIE_MEM_END_PA,
++	.flags  = IORESOURCE_MEM,
++};
++
++static struct resource bcm_pcie_io_resource = {
++	.name   = "bcm63xx PCIe IO space",
++	.start  = 0,
++	.end    = 0,
++	.flags  = 0,
++};
++
++struct pci_controller bcm63xx_pcie_controller = {
++	.pci_ops	= &bcm63xx_pcie_ops,
++	.io_resource	= &bcm_pcie_io_resource,
++	.mem_resource	= &bcm_pcie_mem_resource,
++};
++
+ static u32 bcm63xx_int_cfg_readl(u32 reg)
+ {
+ 	u32 tmp;
+@@ -94,6 +115,95 @@ static void bcm63xx_int_cfg_writel(u32 v
+ 
+ void __iomem *pci_iospace_start;
+ 
++static void __init bcm63xx_reset_pcie(void)
++{
++	u32 val;
++
++	/* enable clock */
++	val = bcm_perf_readl(PERF_CKCTL_REG);
++	val |= CKCTL_6328_PCIE_EN;
++	bcm_perf_writel(val, PERF_CKCTL_REG);
++
++	/* enable SERDES */
++	val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
++	val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
++	bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
++
++	/* reset the PCIe core */
++	val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
++
++	val &= ~SOFTRESET_6328_PCIE_MASK;
++	val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
++	val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
++	val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
++	bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
++	mdelay(10);
++
++	val |= SOFTRESET_6328_PCIE_MASK;
++	val |= SOFTRESET_6328_PCIE_CORE_MASK;
++	val |= SOFTRESET_6328_PCIE_HARD_MASK;
++	bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
++	mdelay(10);
++
++	val |= SOFTRESET_6328_PCIE_EXT_MASK;
++	bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
++	mdelay(200);
++}
++
++static int __init bcm63xx_register_pcie(void)
++{
++	u32 val;
++
++	bcm63xx_reset_pcie();
++
++	/* configure the PCIe bridge */
++	val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
++	val |= OPT1_RD_BE_OPT_EN;
++	val |= OPT1_RD_REPLY_BE_FIX_EN;
++	val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
++	val |= OPT1_L1_INT_STATUS_MASK_POL;
++	bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
++
++	/* setup the interrupts */
++	val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
++	val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
++	bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
++
++	val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
++	/* enable credit checking and error checking */
++	val |= OPT2_TX_CREDIT_CHK_EN;
++	val |= OPT2_UBUS_UR_DECODE_DIS;
++
++	/* set device bus/func for the pcie device */
++	val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
++	val |= OPT2_CFG_TYPE1_BD_SEL;
++	bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
++
++	/* setup class code as bridge */
++	val = bcm_pcie_readl(PCIE_IDVAL3_REG);
++	val &= ~IDVAL3_CLASS_CODE_MASK;
++	val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
++	bcm_pcie_writel(val, PCIE_IDVAL3_REG);
++
++	/* disable bar1 size */
++	val = bcm_pcie_readl(PCIE_CONFIG2_REG);
++	val &= ~CONFIG2_BAR1_SIZE_MASK;
++	bcm_pcie_writel(val, PCIE_CONFIG2_REG);
++
++	/* set bar0 to little endian */
++	val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
++	val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
++	val |= BASEMASK_REMAP_EN;
++	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
++
++	val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
++	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
++
++	register_pci_controller(&bcm63xx_pcie_controller);
++
++	return 0;
++}
++
+ static int __init bcm63xx_register_pci(void)
+ {
+ 	unsigned int mem_size;
+@@ -221,6 +331,8 @@ static int __init bcm63xx_pci_init(void)
+ 		return -ENODEV;
+ 
+ 	switch (bcm63xx_get_cpu_id()) {
++	case BCM6328_CPU_ID:
++		return bcm63xx_register_pcie();
+ 	case BCM6348_CPU_ID:
+ 	case BCM6358_CPU_ID:
+ 	case BCM6368_CPU_ID:
+--- a/arch/mips/pci/pci-bcm63xx.h
++++ b/arch/mips/pci/pci-bcm63xx.h
+@@ -13,11 +13,16 @@
+  */
+ #define CARDBUS_PCI_IDSEL	0x8
+ 
++
++#define PCIE_BUS_BRIDGE		0
++#define PCIE_BUS_DEVICE		1
++
+ /*
+  * defined in ops-bcm63xx.c
+  */
+ extern struct pci_ops bcm63xx_pci_ops;
+ extern struct pci_ops bcm63xx_cb_ops;
++extern struct pci_ops bcm63xx_pcie_ops;
+ 
+ /*
+  * defined in pci-bcm63xx.c
diff --git a/target/linux/brcm63xx/patches-3.3/028-MIPS-Expose-PCIe-drivers-for-MIPS.patch b/target/linux/brcm63xx/patches-3.3/028-MIPS-Expose-PCIe-drivers-for-MIPS.patch
new file mode 100644
index 000000000000..3169ca2fae1d
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/028-MIPS-Expose-PCIe-drivers-for-MIPS.patch
@@ -0,0 +1,28 @@
+From 4831929b8c37aa866afca1498001c939377e5a67 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Wed, 13 Jun 2012 17:07:16 +0100
+Subject: [PATCH 7/8] MIPS: Expose PCIe drivers for MIPS
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Maxime Bizon <mbizon@freebox.fr>
+Cc: Florian Fainelli <florian@openwrt.org>
+Cc: Kevin Cernekee <cernekee@gmail.com>
+Patchwork: https://patchwork.linux-mips.org/patch/3957/
+Reviewed-by: Florian Fainelli <florian@openwrt.org>
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/Kconfig |    2 ++
+ 1 files changed, 2 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -2392,6 +2392,8 @@ config PCI_DOMAINS
+ 
+ source "drivers/pci/Kconfig"
+ 
++source "drivers/pci/pcie/Kconfig"
++
+ #
+ # ISA support is now enabled via select.  Too many systems still have the one
+ # or other ISA chip on the board that users don't know about so don't expect
diff --git a/target/linux/brcm63xx/patches-3.3/101-MIPS-BCM63XX-fix-BCM6368-IPSec-clock-bit.patch b/target/linux/brcm63xx/patches-3.3/101-MIPS-BCM63XX-fix-BCM6368-IPSec-clock-bit.patch
deleted file mode 100644
index 81f87c610073..000000000000
--- a/target/linux/brcm63xx/patches-3.3/101-MIPS-BCM63XX-fix-BCM6368-IPSec-clock-bit.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From 41ee87b6ddd525fab54e21ede506f2084bcabed3 Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <florian@openwrt.org>
-Date: Wed, 25 Jan 2012 17:39:52 +0100
-Subject: [PATCH 14/63] MIPS: BCM63XX: fix BCM6368 IPSec clock bit
-
-The IPsec clock bit is 18 and not 17.
-
-Signed-off-by: Florian Fainelli <florian@openwrt.org>
----
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    2 +-
- 1 files changed, 1 insertions(+), 1 deletions(-)
-
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -99,7 +99,7 @@
- #define CKCTL_6368_USBH_EN		(1 << 15)
- #define CKCTL_6368_DISABLE_GLESS_EN	(1 << 16)
- #define CKCTL_6368_NAND_EN		(1 << 17)
--#define CKCTL_6368_IPSEC_EN		(1 << 17)
-+#define CKCTL_6368_IPSEC_EN		(1 << 18)
- 
- #define CKCTL_6368_ALL_SAFE_EN		(CKCTL_6368_SWPKT_USB_EN |	\
- 					CKCTL_6368_SWPKT_SAR_EN |	\
diff --git a/target/linux/brcm63xx/patches-3.3/102-MIPS-BCM63XX-add-support-for-ipsec-clock.patch b/target/linux/brcm63xx/patches-3.3/102-MIPS-BCM63XX-add-support-for-ipsec-clock.patch
deleted file mode 100644
index b8e2f4e726bb..000000000000
--- a/target/linux/brcm63xx/patches-3.3/102-MIPS-BCM63XX-add-support-for-ipsec-clock.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 69b21096e25889d7db7cfc159202ef0a16530e6b Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <florian@openwrt.org>
-Date: Wed, 25 Jan 2012 17:39:54 +0100
-Subject: [PATCH 15/63] MIPS: BCM63XX: add support for "ipsec" clock
-
-This module is only available on BCM6368 so far and does not require
-resetting the block.
-
-Signed-off-by: Florian Fainelli <florian@openwrt.org>
----
- arch/mips/bcm63xx/clk.c |   14 ++++++++++++++
- 1 files changed, 14 insertions(+), 0 deletions(-)
-
---- a/arch/mips/bcm63xx/clk.c
-+++ b/arch/mips/bcm63xx/clk.c
-@@ -224,6 +224,18 @@ static struct clk clk_xtm = {
- };
- 
- /*
-+ * IPsec clock
-+ */
-+static void ipsec_set(struct clk *clk, int enable)
-+{
-+	bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable);
-+}
-+
-+static struct clk clk_ipsec = {
-+	.set	= ipsec_set,
-+};
-+
-+/*
-  * Internal peripheral clock
-  */
- static struct clk clk_periph = {
-@@ -280,6 +292,8 @@ struct clk *clk_get(struct device *dev,
- 		return &clk_periph;
- 	if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
- 		return &clk_pcm;
-+	if (BCMCPU_IS_6368() && !strcmp(id, "ipsec"))
-+		return &clk_ipsec;
- 	return ERR_PTR(-ENOENT);
- }
- 
diff --git a/target/linux/brcm63xx/patches-3.3/103-MIPS-BCM63XX-add-TRNG-peripheral-definitions.patch b/target/linux/brcm63xx/patches-3.3/103-MIPS-BCM63XX-add-TRNG-peripheral-definitions.patch
deleted file mode 100644
index a656de6c779d..000000000000
--- a/target/linux/brcm63xx/patches-3.3/103-MIPS-BCM63XX-add-TRNG-peripheral-definitions.patch
+++ /dev/null
@@ -1,106 +0,0 @@
-From 913c171ebfe0d589bdf6efb8fd607258c96ea54a Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <florian@openwrt.org>
-Date: Wed, 25 Jan 2012 17:39:58 +0100
-Subject: [PATCH 16/63] MIPS: BCM63XX: add TRNG peripheral definitions
-
-Signed-off-by: Florian Fainelli <florian@openwrt.org>
----
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |    9 +++++++++
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   14 ++++++++++++++
- 2 files changed, 23 insertions(+), 0 deletions(-)
-
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -129,6 +129,7 @@ enum bcm63xx_regs_set {
- 	RSET_PCMDMA,
- 	RSET_PCMDMAC,
- 	RSET_PCMDMAS,
-+	RSET_TRNG
- };
- 
- #define RSET_DSL_LMEM_SIZE		(64 * 1024 * 4)
-@@ -152,6 +153,7 @@ enum bcm63xx_regs_set {
- #define RSET_XTMDMA_SIZE		256
- #define RSET_XTMDMAC_SIZE(chans)	(16 * (chans))
- #define RSET_XTMDMAS_SIZE(chans)	(16 * (chans))
-+#define RSET_TRNG_SIZE			20
- 
- /*
-  * 6338 register sets base address
-@@ -195,6 +197,7 @@ enum bcm63xx_regs_set {
- #define BCM_6338_PCMDMA_BASE		(0xdeadbeef)
- #define BCM_6338_PCMDMAC_BASE		(0xdeadbeef)
- #define BCM_6338_PCMDMAS_BASE		(0xdeadbeef)
-+#define BCM_6338_TRNG_BASE		(0xdeadbeef)
- 
- /*
-  * 6345 register sets base address
-@@ -238,6 +241,7 @@ enum bcm63xx_regs_set {
- #define BCM_6345_PCMDMA_BASE		(0xdeadbeef)
- #define BCM_6345_PCMDMAC_BASE		(0xdeadbeef)
- #define BCM_6345_PCMDMAS_BASE		(0xdeadbeef)
-+#define BCM_6345_TRNG_BASE		(0xdeadbeef)
- 
- /*
-  * 6348 register sets base address
-@@ -278,6 +282,7 @@ enum bcm63xx_regs_set {
- #define BCM_6348_PCMDMA_BASE		(0xdeadbeef)
- #define BCM_6348_PCMDMAC_BASE		(0xdeadbeef)
- #define BCM_6348_PCMDMAS_BASE		(0xdeadbeef)
-+#define BCM_6348_TRNG_BASE		(0xdeadbeef)
- 
- /*
-  * 6358 register sets base address
-@@ -318,6 +323,7 @@ enum bcm63xx_regs_set {
- #define BCM_6358_PCMDMA_BASE		(0xfffe1800)
- #define BCM_6358_PCMDMAC_BASE		(0xfffe1900)
- #define BCM_6358_PCMDMAS_BASE		(0xfffe1a00)
-+#define BCM_6358_TRNG_BASE		(0xdeadbeef)
- 
- 
- /*
-@@ -359,6 +365,7 @@ enum bcm63xx_regs_set {
- #define BCM_6368_PCMDMA_BASE		(0xb0005800)
- #define BCM_6368_PCMDMAC_BASE		(0xb0005a00)
- #define BCM_6368_PCMDMAS_BASE		(0xb0005c00)
-+#define BCM_6368_TRNG_BASE		(0xb0004180)
- 
- 
- extern const unsigned long *bcm63xx_regs_base;
-@@ -404,6 +411,7 @@ extern const unsigned long *bcm63xx_regs
- 	__GEN_RSET_BASE(__cpu, PCMDMA)					\
- 	__GEN_RSET_BASE(__cpu, PCMDMAC)					\
- 	__GEN_RSET_BASE(__cpu, PCMDMAS)					\
-+	__GEN_RSET_BASE(__cpu, TRNG)					\
- 	}
- 
- #define __GEN_CPU_REGS_TABLE(__cpu)					\
-@@ -442,6 +450,7 @@ extern const unsigned long *bcm63xx_regs
- 	[RSET_PCMDMA]		= BCM_## __cpu ##_PCMDMA_BASE,		\
- 	[RSET_PCMDMAC]		= BCM_## __cpu ##_PCMDMAC_BASE,		\
- 	[RSET_PCMDMAS]		= BCM_## __cpu ##_PCMDMAS_BASE,		\
-+	[RSET_TRNG]		= BCM_## __cpu ##_TRNG_BASE,		\
- 
- 
- static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1099,4 +1099,18 @@
- #define SPI_SSOFFTIME_SHIFT		3
- #define SPI_BYTE_SWAP			0x80
- 
-+/*************************************************************************
-+ * _REG relative to RSET_TRNG
-+ *************************************************************************/
-+
-+#define TRNG_CTRL			0x00
-+#define TRNG_EN				(1 << 0)
-+
-+#define TRNG_STAT			0x04
-+#define TRNG_AVAIL_MASK			(0xff000000)
-+
-+#define TRNG_DATA			0x08
-+#define TRNG_THRES			0x0c
-+#define TRNG_MASK			0x10
-+
- #endif /* BCM63XX_REGS_H_ */
diff --git a/target/linux/brcm63xx/patches-3.3/104-MIPS-BCM63XX-add-RNG-driver-platform_device-stub.patch b/target/linux/brcm63xx/patches-3.3/104-MIPS-BCM63XX-add-RNG-driver-platform_device-stub.patch
deleted file mode 100644
index aec00807844b..000000000000
--- a/target/linux/brcm63xx/patches-3.3/104-MIPS-BCM63XX-add-RNG-driver-platform_device-stub.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From cfcc8526e97bdcbfcbf945246b878262389b8842 Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <florian@openwrt.org>
-Date: Wed, 25 Jan 2012 17:39:59 +0100
-Subject: [PATCH 17/63] MIPS: BCM63XX: add RNG driver platform_device stub
-
-Signed-off-by: Florian Fainelli <florian@openwrt.org>
----
- arch/mips/bcm63xx/Makefile   |    4 ++--
- arch/mips/bcm63xx/dev-trng.c |   40 ++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 42 insertions(+), 2 deletions(-)
- create mode 100644 arch/mips/bcm63xx/dev-trng.c
-
---- a/arch/mips/bcm63xx/Makefile
-+++ b/arch/mips/bcm63xx/Makefile
-@@ -1,6 +1,6 @@
- obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
--		   dev-dsp.o dev-enet.o dev-pcmcia.o dev-spi.o dev-uart.o \
--		   dev-wdt.o
-+		   dev-dsp.o dev-enet.o dev-pcmcia.o dev-spi.o dev-trng.o \
-+		   dev-uart.o dev-wdt.o
- obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
- 
- obj-y		+= boards/
---- /dev/null
-+++ b/arch/mips/bcm63xx/dev-trng.c
-@@ -0,0 +1,40 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2011 Florian Fainelli <florian@openwrt.org>
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <bcm63xx_cpu.h>
-+
-+static struct resource trng_resources[] = {
-+	{
-+		.start		= -1, /* filled at runtime */
-+		.end		= -1, /* filled at runtime */
-+		.flags		= IORESOURCE_MEM,
-+	},
-+};
-+
-+static struct platform_device bcm63xx_trng_device = {
-+	.name		= "bcm63xx-trng",
-+	.id		= -1,
-+	.num_resources	= ARRAY_SIZE(trng_resources),
-+	.resource	= trng_resources,
-+};
-+
-+int __init bcm63xx_trng_register(void)
-+{
-+	if (!BCMCPU_IS_6368())
-+		return -ENODEV;
-+
-+	trng_resources[0].start = bcm63xx_regset_address(RSET_TRNG);
-+	trng_resources[0].end = trng_resources[0].start;
-+	trng_resources[0].end += RSET_TRNG_SIZE - 1;
-+
-+	return platform_device_register(&bcm63xx_trng_device);
-+}
-+arch_initcall(bcm63xx_trng_register);
diff --git a/target/linux/brcm63xx/patches-3.3/105-hw_random-add-Broadcom-BCM63xx-RNG-driver.patch b/target/linux/brcm63xx/patches-3.3/105-hw_random-add-Broadcom-BCM63xx-RNG-driver.patch
deleted file mode 100644
index 8e14bd7dccbd..000000000000
--- a/target/linux/brcm63xx/patches-3.3/105-hw_random-add-Broadcom-BCM63xx-RNG-driver.patch
+++ /dev/null
@@ -1,224 +0,0 @@
-From 21a474b37f905387d8908384a24c13d4f8513113 Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <florian@openwrt.org>
-Date: Wed, 25 Jan 2012 17:40:02 +0100
-Subject: [PATCH 18/63] hw_random: add Broadcom BCM63xx RNG driver
-
-Signed-off-by: Florian Fainelli <florian@openwrt.org>
----
- drivers/char/hw_random/Kconfig       |   14 +++
- drivers/char/hw_random/Makefile      |    1 +
- drivers/char/hw_random/bcm63xx-rng.c |  175 ++++++++++++++++++++++++++++++++++
- 3 files changed, 190 insertions(+), 0 deletions(-)
- create mode 100644 drivers/char/hw_random/bcm63xx-rng.c
-
---- a/drivers/char/hw_random/Kconfig
-+++ b/drivers/char/hw_random/Kconfig
-@@ -73,6 +73,20 @@ config HW_RANDOM_ATMEL
- 
- 	  If unsure, say Y.
- 
-+config HW_RANDOM_BCM63XX
-+	tristate "Broadcom BCM63xx Random Number Generator support"
-+	depends on HW_RANDOM && BCM63XX
-+	default HW_RANDOM
-+	---help---
-+	  This driver provides kernel-side support for the Random Number
-+	  Generator hardware found on the Broadcom BCM63xx SoCs.
-+
-+	  To compile this driver as a module, choose M here: the
-+	  module will be called bcm63xx-rng
-+
-+	  If unusure, say Y.
-+
-+
- config HW_RANDOM_GEODE
- 	tristate "AMD Geode HW Random Number Generator support"
- 	depends on HW_RANDOM && X86_32 && PCI
---- a/drivers/char/hw_random/Makefile
-+++ b/drivers/char/hw_random/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += ti
- obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o
- obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o
- obj-$(CONFIG_HW_RANDOM_ATMEL) += atmel-rng.o
-+obj-$(CONFIG_HW_RANDOM_BCM63XX)	+= bcm63xx-rng.o
- obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o
- obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o
- n2-rng-y := n2-drv.o n2-asm.o
---- /dev/null
-+++ b/drivers/char/hw_random/bcm63xx-rng.c
-@@ -0,0 +1,175 @@
-+/*
-+ * Broadcom BCM63xx Random Number Generator support
-+ *
-+ * Copyright (C) 2011, Florian Fainelli <florian@openwrt.org>
-+ * Copyright (C) 2009, Broadcom Corporation
-+ *
-+ */
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/io.h>
-+#include <linux/err.h>
-+#include <linux/clk.h>
-+#include <linux/platform_device.h>
-+#include <linux/hw_random.h>
-+
-+#include <bcm63xx_io.h>
-+#include <bcm63xx_regs.h>
-+
-+struct bcm63xx_trng_priv {
-+	struct clk *clk;
-+	void __iomem *regs;
-+};
-+
-+#define to_trng_priv(rng)	((struct bcm63xx_trng_priv *)rng->priv)
-+
-+static int bcm63xx_trng_init(struct hwrng *rng)
-+{
-+	struct bcm63xx_trng_priv *priv = to_trng_priv(rng);
-+	u32 val;
-+
-+	val = bcm_readl(priv->regs + TRNG_CTRL);
-+	val |= TRNG_EN;
-+	bcm_writel(val, priv->regs + TRNG_CTRL);
-+
-+	return 0;
-+}
-+
-+static void bcm63xx_trng_cleanup(struct hwrng *rng)
-+{
-+	struct bcm63xx_trng_priv *priv = to_trng_priv(rng);
-+	u32 val;
-+
-+	val = bcm_readl(priv->regs + TRNG_CTRL);
-+	val &= ~TRNG_EN;
-+	bcm_writel(val, priv->regs + TRNG_CTRL);
-+}
-+
-+static int bcm63xx_trng_data_present(struct hwrng *rng, int wait)
-+{
-+	struct bcm63xx_trng_priv *priv = to_trng_priv(rng);
-+
-+	return bcm_readl(priv->regs + TRNG_STAT) & TRNG_AVAIL_MASK;
-+}
-+
-+static int bcm63xx_trng_data_read(struct hwrng *rng, u32 *data)
-+{
-+	struct bcm63xx_trng_priv *priv = to_trng_priv(rng);
-+
-+	*data = bcm_readl(priv->regs + TRNG_DATA);
-+
-+	return 4;
-+}
-+
-+static int __devinit bcm63xx_trng_probe(struct platform_device *pdev)
-+{
-+	struct resource *r;
-+	struct clk *clk;
-+	int ret;
-+	struct bcm63xx_trng_priv *priv;
-+	struct hwrng *rng;
-+
-+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!r) {
-+		dev_err(&pdev->dev, "no iomem resource\n");
-+		ret = -ENXIO;
-+		goto out;
-+	}
-+
-+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-+	if (!priv) {
-+		dev_err(&pdev->dev, "no memory for private structure\n");
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	rng = kzalloc(sizeof(*rng), GFP_KERNEL);
-+	if (!rng) {
-+		dev_err(&pdev->dev, "no memory for rng structure\n");
-+		ret = -ENOMEM;
-+		goto out_free_priv;
-+	}
-+
-+	platform_set_drvdata(pdev, rng);
-+	rng->priv = (unsigned long)priv;
-+	rng->name = pdev->name;
-+	rng->init = bcm63xx_trng_init;
-+	rng->cleanup = bcm63xx_trng_cleanup;
-+	rng->data_present = bcm63xx_trng_data_present;
-+	rng->data_read = bcm63xx_trng_data_read;
-+
-+	clk = clk_get(&pdev->dev, "ipsec");
-+	if (IS_ERR(clk)) {
-+		dev_err(&pdev->dev, "no clock for device\n");
-+		ret = PTR_ERR(clk);
-+		goto out_free_rng;
-+	}
-+
-+	priv->clk = clk;
-+
-+	if (!devm_request_mem_region(&pdev->dev, r->start,
-+					resource_size(r), pdev->name)) {
-+		dev_err(&pdev->dev, "request mem failed");
-+		ret = -ENOMEM;
-+		goto out_free_rng;
-+	}
-+
-+	priv->regs = devm_ioremap_nocache(&pdev->dev, r->start,
-+					resource_size(r));
-+	if (!priv->regs) {
-+		dev_err(&pdev->dev, "ioremap failed");
-+		ret = -ENOMEM;
-+		goto out_free_rng;
-+	}
-+
-+	clk_enable(clk);
-+
-+	ret = hwrng_register(rng);
-+	if (ret) {
-+		dev_err(&pdev->dev, "failed to register rng device\n");
-+		goto out_clk_disable;
-+	}
-+
-+	dev_info(&pdev->dev, "registered RNG driver\n");
-+
-+	return 0;
-+
-+out_clk_disable:
-+	clk_disable(clk);
-+out_free_rng:
-+	platform_set_drvdata(pdev, NULL);
-+	kfree(rng);
-+out_free_priv:
-+	kfree(priv);
-+out:
-+	return ret;
-+}
-+
-+static int __devexit bcm63xx_trng_remove(struct platform_device *pdev)
-+{
-+	struct hwrng *rng = platform_get_drvdata(pdev);
-+	struct bcm63xx_trng_priv *priv = to_trng_priv(rng);
-+
-+	hwrng_unregister(rng);
-+	clk_disable(priv->clk);
-+	kfree(priv);
-+	kfree(rng);
-+	platform_set_drvdata(pdev, NULL);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver bcm63xx_trng_driver = {
-+	.probe		= bcm63xx_trng_probe,
-+	.remove		= __devexit_p(bcm63xx_trng_remove),
-+	.driver		= {
-+		.name	= "bcm63xx-trng",
-+		.owner	= THIS_MODULE,
-+	},
-+};
-+
-+module_platform_driver(bcm63xx_trng_driver);
-+
-+MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
-+MODULE_DESCRIPTION("Broadcom BCM63xx RNG driver");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/brcm63xx/patches-3.3/200-MIPS-expose-PCIe-drivers-for-MIPS.patch b/target/linux/brcm63xx/patches-3.3/200-MIPS-expose-PCIe-drivers-for-MIPS.patch
deleted file mode 100644
index 9006f1a42e62..000000000000
--- a/target/linux/brcm63xx/patches-3.3/200-MIPS-expose-PCIe-drivers-for-MIPS.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From a3f65b46e32acd29c613b35fab588e4d28e5d432 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Sun, 3 Jul 2011 13:11:19 +0200
-Subject: [PATCH 48/79] MIPS: expose PCIe drivers for MIPS
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/Kconfig |    2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -2392,6 +2392,8 @@ config PCI_DOMAINS
- 
- source "drivers/pci/Kconfig"
- 
-+source "drivers/pci/pcie/Kconfig"
-+
- #
- # ISA support is now enabled via select.  Too many systems still have the one
- # or other ISA chip on the board that users don't know about so don't expect
diff --git a/target/linux/brcm63xx/patches-3.3/300-reset_buttons.patch b/target/linux/brcm63xx/patches-3.3/300-reset_buttons.patch
index f73c608bd9f4..0e1d6f8d95c6 100644
--- a/target/linux/brcm63xx/patches-3.3/300-reset_buttons.patch
+++ b/target/linux/brcm63xx/patches-3.3/300-reset_buttons.patch
@@ -1,15 +1,15 @@
 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -15,6 +15,8 @@
- #include <linux/mtd/partitions.h>
- #include <linux/mtd/physmap.h>
+@@ -12,6 +12,8 @@
+ #include <linux/string.h>
+ #include <linux/platform_device.h>
  #include <linux/ssb/ssb.h>
 +#include <linux/gpio_keys.h>
 +#include <linux/input.h>
  #include <asm/addrspace.h>
  #include <bcm63xx_board.h>
  #include <bcm63xx_cpu.h>
-@@ -30,6 +32,9 @@
+@@ -28,6 +30,9 @@
  
  #define PFX	"board_bcm963xx: "
  
@@ -19,7 +19,7 @@
  static struct bcm963xx_nvram nvram;
  static unsigned int mac_addr_used;
  static struct board_info board;
-@@ -295,6 +300,16 @@ static struct board_info __initdata boar
+@@ -293,6 +298,16 @@ static struct board_info __initdata boar
  			.active_low	= 1,
  		},
  	},
@@ -36,7 +36,7 @@
  };
  
  static struct board_info __initdata board_96348gw = {
-@@ -353,6 +368,16 @@ static struct board_info __initdata boar
+@@ -351,6 +366,16 @@ static struct board_info __initdata boar
  			.active_low	= 1,
  		},
  	},
@@ -53,7 +53,7 @@
  };
  
  static struct board_info __initdata board_FAST2404 = {
-@@ -851,12 +876,23 @@ static struct platform_device bcm63xx_gp
+@@ -821,11 +846,23 @@ static struct platform_device bcm63xx_gp
  	.dev.platform_data	= &bcm63xx_led_data,
  };
  
@@ -72,12 +72,12 @@
   */
  int __init board_register_devices(void)
  {
- 	u32 val;
 +	int button_count = 0;
- 
++
  	if (board.has_uart0)
  		bcm63xx_uart_register(0);
-@@ -907,5 +943,16 @@ int __init board_register_devices(void)
+ 
+@@ -868,5 +905,16 @@ int __init board_register_devices(void)
  
  	platform_device_register(&bcm63xx_gpio_leds);
  
diff --git a/target/linux/brcm63xx/patches-3.3/301-led_count.patch b/target/linux/brcm63xx/patches-3.3/301-led_count.patch
index 208ae65bb4ec..84d57a00ddf3 100644
--- a/target/linux/brcm63xx/patches-3.3/301-led_count.patch
+++ b/target/linux/brcm63xx/patches-3.3/301-led_count.patch
@@ -1,16 +1,16 @@
 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -893,6 +893,7 @@ int __init board_register_devices(void)
+@@ -862,6 +862,7 @@ static struct platform_device bcm63xx_gp
+ int __init board_register_devices(void)
  {
- 	u32 val;
  	int button_count = 0;
 +	int led_count = 0;
  
  	if (board.has_uart0)
  		bcm63xx_uart_register(0);
-@@ -938,7 +939,11 @@ int __init board_register_devices(void)
+@@ -900,7 +901,11 @@ int __init board_register_devices(void)
  
- 	platform_device_register(&mtd_dev);
+ 	bcm63xx_flash_register();
  
 -	bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);
 +	/* count number of LEDs defined by this device */
diff --git a/target/linux/brcm63xx/patches-3.3/302-extended-platform-devices.patch b/target/linux/brcm63xx/patches-3.3/302-extended-platform-devices.patch
index 1aa97ea3f4e8..b48ef733bfbd 100644
--- a/target/linux/brcm63xx/patches-3.3/302-extended-platform-devices.patch
+++ b/target/linux/brcm63xx/patches-3.3/302-extended-platform-devices.patch
@@ -1,15 +1,15 @@
 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -930,6 +930,9 @@ int __init board_register_devices(void)
+@@ -899,6 +899,9 @@ int __init board_register_devices(void)
  
  	bcm63xx_spi_register();
  
 +	if (board.num_devs)
 +		platform_add_devices(board.devs, board.num_devs);
 +
- 	/* read base address of boot chip select (0) */
- 	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
- 	val &= MPI_CSBASE_BASE_MASK;
+ 	bcm63xx_flash_register();
+ 
+ 	/* count number of LEDs defined by this device */
 --- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
 @@ -61,6 +61,10 @@ struct board_info {
diff --git a/target/linux/brcm63xx/patches-3.3/303-spi-board-info.patch b/target/linux/brcm63xx/patches-3.3/303-spi-board-info.patch
index 41ceaf7234da..517a53b56593 100644
--- a/target/linux/brcm63xx/patches-3.3/303-spi-board-info.patch
+++ b/target/linux/brcm63xx/patches-3.3/303-spi-board-info.patch
@@ -1,6 +1,6 @@
 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -17,6 +17,7 @@
+@@ -14,6 +14,7 @@
  #include <linux/ssb/ssb.h>
  #include <linux/gpio_keys.h>
  #include <linux/input.h>
@@ -8,16 +8,16 @@
  #include <asm/addrspace.h>
  #include <bcm63xx_board.h>
  #include <bcm63xx_cpu.h>
-@@ -933,6 +934,9 @@ int __init board_register_devices(void)
+@@ -902,6 +903,9 @@ int __init board_register_devices(void)
  	if (board.num_devs)
  		platform_add_devices(board.devs, board.num_devs);
  
 +	if (board.num_spis)
 +		spi_register_board_info(board.spis, board.num_spis);
 +
- 	/* read base address of boot chip select (0) */
- 	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
- 	val &= MPI_CSBASE_BASE_MASK;
+ 	bcm63xx_flash_register();
+ 
+ 	/* count number of LEDs defined by this device */
 --- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
 @@ -65,6 +65,10 @@ struct board_info {
diff --git a/target/linux/brcm63xx/patches-3.3/304-boardid_fixup.patch b/target/linux/brcm63xx/patches-3.3/304-boardid_fixup.patch
index c8da9932d443..0c2fab57538f 100644
--- a/target/linux/brcm63xx/patches-3.3/304-boardid_fixup.patch
+++ b/target/linux/brcm63xx/patches-3.3/304-boardid_fixup.patch
@@ -1,6 +1,6 @@
 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -30,12 +30,16 @@
+@@ -28,12 +28,16 @@
  #include <bcm63xx_dev_pcmcia.h>
  #include <bcm63xx_dev_spi.h>
  #include <board_bcm963xx.h>
@@ -17,7 +17,7 @@
  static struct bcm963xx_nvram nvram;
  static unsigned int mac_addr_used;
  static struct board_info board;
-@@ -726,6 +730,29 @@ static int board_get_mac_address(u8 *mac
+@@ -724,6 +728,29 @@ static int board_get_mac_address(u8 *mac
  	return 0;
  }
  
@@ -47,7 +47,7 @@
  /*
   * early init callback, read nvram data from flash and checksum it
   */
-@@ -767,6 +794,11 @@ void __init board_prom_init(void)
+@@ -771,6 +798,11 @@ void __init board_prom_init(void)
  		return;
  	}
  
diff --git a/target/linux/brcm63xx/patches-3.3/305-missing_ext_irq_bits.patch b/target/linux/brcm63xx/patches-3.3/305-missing_ext_irq_bits.patch
index a350c4d554ff..703f4b54b164 100644
--- a/target/linux/brcm63xx/patches-3.3/305-missing_ext_irq_bits.patch
+++ b/target/linux/brcm63xx/patches-3.3/305-missing_ext_irq_bits.patch
@@ -1,6 +1,6 @@
 --- a/arch/mips/bcm63xx/irq.c
 +++ b/arch/mips/bcm63xx/irq.c
-@@ -45,8 +45,8 @@ static void __internal_irq_unmask_64(uns
+@@ -56,8 +56,8 @@ static void __internal_irq_unmask_64(uns
  #define is_ext_irq_cascaded	0
  #define ext_irq_start		0
  #define ext_irq_end		0
@@ -11,7 +11,7 @@
  #define ext_irq_cfg_reg2	0
  #endif
  #ifdef CONFIG_BCM63XX_CPU_6348
-@@ -122,11 +122,15 @@ static void bcm63xx_init_irq(void)
+@@ -143,11 +143,15 @@ static void bcm63xx_init_irq(void)
  		irq_stat_addr += PERF_IRQSTAT_6338_REG;
  		irq_mask_addr += PERF_IRQMASK_6338_REG;
  		irq_bits = 32;
@@ -27,7 +27,7 @@
  		break;
  	case BCM6348_CPU_ID:
  		irq_stat_addr += PERF_IRQSTAT_6348_REG;
-@@ -413,7 +417,8 @@ static int bcm63xx_external_irq_set_type
+@@ -434,7 +438,8 @@ static int bcm63xx_external_irq_set_type
  	reg = bcm_perf_readl(regaddr);
  	irq %= 4;
  
@@ -37,7 +37,7 @@
  		if (levelsense)
  			reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
  		else
-@@ -426,9 +431,12 @@ static int bcm63xx_external_irq_set_type
+@@ -447,9 +452,12 @@ static int bcm63xx_external_irq_set_type
  			reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
  		else
  			reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
@@ -52,7 +52,7 @@
  		if (levelsense)
  			reg |= EXTIRQ_CFG_LEVELSENSE(irq);
  		else
-@@ -441,6 +449,9 @@ static int bcm63xx_external_irq_set_type
+@@ -462,6 +470,9 @@ static int bcm63xx_external_irq_set_type
  			reg |= EXTIRQ_CFG_BOTHEDGE(irq);
  		else
  			reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
@@ -64,7 +64,7 @@
  	bcm_perf_writel(reg, regaddr);
 --- a/arch/mips/bcm63xx/setup.c
 +++ b/arch/mips/bcm63xx/setup.c
-@@ -71,6 +71,9 @@ void bcm63xx_machine_reboot(void)
+@@ -74,6 +74,9 @@ void bcm63xx_machine_reboot(void)
  	case BCM6338_CPU_ID:
  		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
  		break;
@@ -74,7 +74,7 @@
  	case BCM6348_CPU_ID:
  		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348;
  		break;
-@@ -80,6 +83,9 @@ void bcm63xx_machine_reboot(void)
+@@ -83,6 +86,9 @@ void bcm63xx_machine_reboot(void)
  	}
  
  	for (i = 0; i < 2; i++) {
@@ -86,9 +86,9 @@
  			reg &= ~EXTIRQ_CFG_MASK_ALL_6348;
 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -134,6 +134,7 @@
- 
+@@ -161,6 +161,7 @@
  /* External Interrupt Configuration register */
+ #define PERF_EXTIRQ_CFG_REG_6328	0x18
  #define PERF_EXTIRQ_CFG_REG_6338	0x14
 +#define PERF_EXTIRQ_CFG_REG_6345	0x14
  #define PERF_EXTIRQ_CFG_REG_6348	0x14
diff --git a/target/linux/brcm63xx/patches-3.3/306-MIPS-BCM63XX-register-devices-earlier.patch b/target/linux/brcm63xx/patches-3.3/306-MIPS-BCM63XX-register-devices-earlier.patch
deleted file mode 100644
index 3e74e976300f..000000000000
--- a/target/linux/brcm63xx/patches-3.3/306-MIPS-BCM63XX-register-devices-earlier.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From d42f3f75a5d1abe9f7c5275fb59f3e894e83043d Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Sun, 6 May 2012 15:05:48 +0200
-Subject: [PATCH 1/2] MIPS: BCM63XX: register devices earlier
-
-Register devices as an arch initcall so that the fallback sprom gets
-installed in the same phase as the pci bus gets registered.
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/bcm63xx/setup.c |    2 +-
- 1 files changed, 1 insertions(+), 1 deletions(-)
-
---- a/arch/mips/bcm63xx/setup.c
-+++ b/arch/mips/bcm63xx/setup.c
-@@ -150,4 +150,4 @@ int __init bcm63xx_register_devices(void
- 	return board_register_devices();
- }
- 
--device_initcall(bcm63xx_register_devices);
-+arch_initcall(bcm63xx_register_devices);
diff --git a/target/linux/brcm63xx/patches-3.3/306-Revert-MIPS-BCM63XX-Call-board_register_device-from-.patch b/target/linux/brcm63xx/patches-3.3/306-Revert-MIPS-BCM63XX-Call-board_register_device-from-.patch
new file mode 100644
index 000000000000..aa7ef8bbdb6b
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/306-Revert-MIPS-BCM63XX-Call-board_register_device-from-.patch
@@ -0,0 +1,23 @@
+From a7d2622b6614fdca504c074a0cd307d5a1165c30 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Tue, 8 May 2012 09:39:01 +0200
+Subject: [PATCH 04/59] Revert "MIPS: BCM63XX: Call board_register_device from device_initcall()"
+
+This commit causes a race between PCI scan and SSB fallback SPROM handler
+registration, causing the wifi to not work on slower systems. The only
+subsystem touched from board_register_device is platform device
+registration, which should be safe as an arch init call.
+
+This reverts commit d64ed7ada2f689d2c62af1892ca55e47d3653e36.
+---
+ arch/mips/bcm63xx/setup.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/bcm63xx/setup.c
++++ b/arch/mips/bcm63xx/setup.c
+@@ -157,4 +157,4 @@ int __init bcm63xx_register_devices(void
+ 	return board_register_devices();
+ }
+ 
+-device_initcall(bcm63xx_register_devices);
++arch_initcall(bcm63xx_register_devices);
diff --git a/target/linux/brcm63xx/patches-3.3/307-MIPS-BCM63XX-allow-second-UART-on-BCM6328.patch b/target/linux/brcm63xx/patches-3.3/307-MIPS-BCM63XX-allow-second-UART-on-BCM6328.patch
new file mode 100644
index 000000000000..1418d65bf4c7
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/307-MIPS-BCM63XX-allow-second-UART-on-BCM6328.patch
@@ -0,0 +1,22 @@
+From c110865541e2d3782c412af9d48c016de5a64d9c Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Tue, 14 Jun 2011 21:14:39 +0200
+Subject: [PATCH 42/79] MIPS: BCM63XX: allow second UART on BCM6328
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/bcm63xx/dev-uart.c |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/dev-uart.c
++++ b/arch/mips/bcm63xx/dev-uart.c
+@@ -54,7 +54,8 @@ int __init bcm63xx_uart_register(unsigne
+ 	if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
+ 		return -ENODEV;
+ 
+-	if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
++	if (id == 1 && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
++	    !BCMCPU_IS_6368())
+ 		return -ENODEV;
+ 
+ 	if (id == 0) {
diff --git a/target/linux/brcm63xx/patches-3.3/307-MIPS-BCM63XX-explicitly-register-the-pci-bus.patch b/target/linux/brcm63xx/patches-3.3/307-MIPS-BCM63XX-explicitly-register-the-pci-bus.patch
deleted file mode 100644
index a502a66a2cab..000000000000
--- a/target/linux/brcm63xx/patches-3.3/307-MIPS-BCM63XX-explicitly-register-the-pci-bus.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 45aebb9465e22b236a201deef1b234693d99e174 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Sun, 6 May 2012 15:13:48 +0200
-Subject: [PATCH 2/2] MIPS: BCM63XX: explicitly register the PCI bus
-
-Instead of setting a global variable toggling the PCI registration,
-register it in the device_register phase after setting the fallback
-sprom to ensure there cannot be a race between them.
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/bcm63xx/boards/board_bcm963xx.c          |    6 +++++-
- .../include/asm/mach-bcm63xx/bcm63xx_dev_pci.h     |    4 +++-
- arch/mips/pci/pci-bcm63xx.c                        |   13 +------------
- 3 files changed, 9 insertions(+), 14 deletions(-)
-
---- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
-+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -826,7 +826,6 @@ void __init board_prom_init(void)
- 
- #ifdef CONFIG_PCI
- 	if (board.has_pci) {
--		bcm63xx_pci_enabled = 1;
- 		if (BCMCPU_IS_6348())
- 			val |= GPIO_MODE_6348_G2_PCI;
- 	}
-@@ -998,5 +997,10 @@ int __init board_register_devices(void)
- 		platform_device_register(&bcm63xx_gpio_keys_device);
- 	}
- 
-+#ifdef CONFIG_PCI
-+	if (board.has_pci)
-+		bcm63xx_pci_register();
-+#endif
-+
- 	return 0;
- }
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h
-@@ -1,6 +1,8 @@
- #ifndef BCM63XX_DEV_PCI_H_
- #define BCM63XX_DEV_PCI_H_
- 
--extern int bcm63xx_pci_enabled;
-+#include <linux/init.h>
-+
-+int __init bcm63xx_pci_register(void);
- 
- #endif /* BCM63XX_DEV_PCI_H_ */
---- a/arch/mips/pci/pci-bcm63xx.c
-+++ b/arch/mips/pci/pci-bcm63xx.c
-@@ -14,12 +14,6 @@
- 
- #include "pci-bcm63xx.h"
- 
--/*
-- * Allow PCI to be disabled at runtime depending on board nvram
-- * configuration
-- */
--int bcm63xx_pci_enabled;
--
- static struct resource bcm_pci_mem_resource = {
- 	.name   = "bcm63xx PCI memory space",
- 	.start  = BCM_PCI_MEM_BASE_PA,
-@@ -94,7 +88,7 @@ static void bcm63xx_int_cfg_writel(u32 v
- 
- void __iomem *pci_iospace_start;
- 
--static int __init bcm63xx_pci_init(void)
-+int __init bcm63xx_pci_register(void)
- {
- 	unsigned int mem_size;
- 	u32 val;
-@@ -102,9 +96,6 @@ static int __init bcm63xx_pci_init(void)
- 	if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
- 		return -ENODEV;
- 
--	if (!bcm63xx_pci_enabled)
--		return -ENODEV;
--
- 	/*
- 	 * configuration  access are  done through  IO space,  remap 4
- 	 * first bytes to access it from CPU.
-@@ -220,5 +211,3 @@ static int __init bcm63xx_pci_init(void)
- 			   "bcm63xx PCI IO space");
- 	return 0;
- }
--
--arch_initcall(bcm63xx_pci_init);
diff --git a/target/linux/brcm63xx/patches-3.3/308-MIPS-BCM63XX-expose-the-HS-SPI-clock.patch b/target/linux/brcm63xx/patches-3.3/308-MIPS-BCM63XX-expose-the-HS-SPI-clock.patch
new file mode 100644
index 000000000000..8a11f8266e03
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/308-MIPS-BCM63XX-expose-the-HS-SPI-clock.patch
@@ -0,0 +1,48 @@
+From 5aeb6273a610f8aab090b3499827177eb41311ba Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Sat, 12 Nov 2011 12:19:09 +0100
+Subject: [PATCH 53/79] MIPS: BCM63XX: expose the HS SPI clock
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/bcm63xx/clk.c |   22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -194,6 +194,26 @@ static struct clk clk_spi = {
+ };
+ 
+ /*
++ * SPI clock
++ */
++static void hsspi_set(struct clk *clk, int enable)
++{
++	u32 mask;
++
++	if (BCMCPU_IS_6328())
++		mask = CKCTL_6328_HSSPI_EN;
++	else
++		return;
++
++	bcm_hwclock_set(mask, enable);
++}
++
++static struct clk clk_hsspi = {
++	.set	= hsspi_set,
++};
++
++
++/*
+  * XTM clock
+  */
+ static void xtm_set(struct clk *clk, int enable)
+@@ -286,6 +306,8 @@ struct clk *clk_get(struct device *dev,
+ 		return &clk_usbh;
+ 	if (!strcmp(id, "spi"))
+ 		return &clk_spi;
++	if (!strcmp(id, "hsspi"))
++		return &clk_hsspi;
+ 	if (!strcmp(id, "xtm"))
+ 		return &clk_xtm;
+ 	if (!strcmp(id, "periph"))
diff --git a/target/linux/brcm63xx/patches-3.3/308-MIPS-BCM63XX-move-flash-registration-out-of-board_bc.patch b/target/linux/brcm63xx/patches-3.3/308-MIPS-BCM63XX-move-flash-registration-out-of-board_bc.patch
deleted file mode 100644
index 35f40186ca4f..000000000000
--- a/target/linux/brcm63xx/patches-3.3/308-MIPS-BCM63XX-move-flash-registration-out-of-board_bc.patch
+++ /dev/null
@@ -1,194 +0,0 @@
-From b620329db3d6646a172a599b0e960baca081fff1 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Sat, 12 Nov 2011 11:17:32 +0100
-Subject: [PATCH 25/79] MIPS: BCM63XX: move flash registration out of
- board_bcm963xx.c
-
-board_bcm963xx.c is already large enough.
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/bcm63xx/Makefile                         |    4 +-
- arch/mips/bcm63xx/boards/board_bcm963xx.c          |   49 +-------------
- arch/mips/bcm63xx/dev-flash.c                      |   68 ++++++++++++++++++++
- .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h   |    6 ++
- 4 files changed, 78 insertions(+), 49 deletions(-)
- create mode 100644 arch/mips/bcm63xx/dev-flash.c
- create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
-
---- a/arch/mips/bcm63xx/Makefile
-+++ b/arch/mips/bcm63xx/Makefile
-@@ -1,6 +1,6 @@
- obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
--		   dev-dsp.o dev-enet.o dev-pcmcia.o dev-spi.o dev-trng.o \
--		   dev-uart.o dev-wdt.o
-+		   dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-spi.o \
-+		   dev-trng.o dev-uart.o dev-wdt.o
- obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
- 
- obj-y		+= boards/
---- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
-+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -11,9 +11,6 @@
- #include <linux/kernel.h>
- #include <linux/string.h>
- #include <linux/platform_device.h>
--#include <linux/mtd/mtd.h>
--#include <linux/mtd/partitions.h>
--#include <linux/mtd/physmap.h>
- #include <linux/ssb/ssb.h>
- #include <linux/gpio_keys.h>
- #include <linux/input.h>
-@@ -27,6 +24,7 @@
- #include <bcm63xx_dev_pci.h>
- #include <bcm63xx_dev_enet.h>
- #include <bcm63xx_dev_dsp.h>
-+#include <bcm63xx_dev_flash.h>
- #include <bcm63xx_dev_pcmcia.h>
- #include <bcm63xx_dev_spi.h>
- #include <board_bcm963xx.h>
-@@ -866,40 +864,6 @@ void __init board_setup(void)
- 		panic("unexpected CPU for bcm963xx board");
- }
- 
--static struct mtd_partition mtd_partitions[] = {
--	{
--		.name		= "cfe",
--		.offset		= 0x0,
--		.size		= 0x40000,
--	}
--};
--
--static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL };
--
--static struct physmap_flash_data flash_data = {
--	.width			= 2,
--	.nr_parts		= ARRAY_SIZE(mtd_partitions),
--	.parts			= mtd_partitions,
--	.part_probe_types	= bcm63xx_part_types,
--};
--
--static struct resource mtd_resources[] = {
--	{
--		.start		= 0,	/* filled at runtime */
--		.end		= 0,	/* filled at runtime */
--		.flags		= IORESOURCE_MEM,
--	}
--};
--
--static struct platform_device mtd_dev = {
--	.name			= "physmap-flash",
--	.resource		= mtd_resources,
--	.num_resources		= ARRAY_SIZE(mtd_resources),
--	.dev			= {
--		.platform_data	= &flash_data,
--	},
--};
--
- static struct gpio_led_platform_data bcm63xx_led_data;
- 
- static struct platform_device bcm63xx_gpio_leds = {
-@@ -923,7 +887,6 @@ static struct platform_device bcm63xx_gp
-  */
- int __init board_register_devices(void)
- {
--	u32 val;
- 	int button_count = 0;
- 	int led_count = 0;
- 
-@@ -968,14 +931,7 @@ int __init board_register_devices(void)
- 	if (board.num_spis)
- 		spi_register_board_info(board.spis, board.num_spis);
- 
--	/* read base address of boot chip select (0) */
--	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
--	val &= MPI_CSBASE_BASE_MASK;
--
--	mtd_resources[0].start = val;
--	mtd_resources[0].end = 0x1FFFFFFF;
--
--	platform_device_register(&mtd_dev);
-+	bcm63xx_flash_register();
- 
- 	/* count number of LEDs defined by this device */
- 	while (led_count < ARRAY_SIZE(board.leds) && board.leds[led_count].name)
---- /dev/null
-+++ b/arch/mips/bcm63xx/dev-flash.c
-@@ -0,0 +1,68 @@
-+/*
-+ * Broadcom BCM63xx flash registration
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/mtd/physmap.h>
-+
-+#include <bcm63xx_cpu.h>
-+#include <bcm63xx_dev_flash.h>
-+#include <bcm63xx_regs.h>
-+#include <bcm63xx_io.h>
-+
-+static struct mtd_partition mtd_partitions[] = {
-+	{
-+		.name		= "cfe",
-+		.offset		= 0x0,
-+		.size		= 0x40000,
-+	}
-+};
-+
-+static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL };
-+
-+static struct physmap_flash_data flash_data = {
-+	.width			= 2,
-+	.parts			= mtd_partitions,
-+	.part_probe_types	= bcm63xx_part_types,
-+};
-+
-+static struct resource mtd_resources[] = {
-+	{
-+		.start		= 0,	/* filled at runtime */
-+		.end		= 0,	/* filled at runtime */
-+		.flags		= IORESOURCE_MEM,
-+	}
-+};
-+
-+static struct platform_device mtd_dev = {
-+	.name			= "physmap-flash",
-+	.resource		= mtd_resources,
-+	.num_resources		= ARRAY_SIZE(mtd_resources),
-+	.dev			= {
-+		.platform_data	= &flash_data,
-+	},
-+};
-+
-+int __init bcm63xx_flash_register(void)
-+{
-+	u32 val;
-+
-+	/* read base address of boot chip select (0) */
-+	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-+	val &= MPI_CSBASE_BASE_MASK;
-+
-+	mtd_resources[0].start = val;
-+	mtd_resources[0].end = 0x1FFFFFFF;
-+
-+	return platform_device_register(&mtd_dev);
-+}
---- /dev/null
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
-@@ -0,0 +1,6 @@
-+#ifndef __BCM63XX_FLASH_H
-+#define __BCM63XX_FLASH_H
-+
-+int __init bcm63xx_flash_register(void);
-+
-+#endif /* __BCM63XX_FLASH_H */
diff --git a/target/linux/brcm63xx/patches-3.3/309-MIPS-BCM63XX-add-HSSPI-register-definitions.patch b/target/linux/brcm63xx/patches-3.3/309-MIPS-BCM63XX-add-HSSPI-register-definitions.patch
new file mode 100644
index 000000000000..1720ed6b5b93
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/309-MIPS-BCM63XX-add-HSSPI-register-definitions.patch
@@ -0,0 +1,211 @@
+From 70f970222bc1096689ae1bffeb9ed09a7c4bed07 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Sat, 12 Nov 2011 12:19:55 +0100
+Subject: [PATCH 28/60] MIPS: BCM63XX: add HSSPI register definitions
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |   18 ++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   47 +++++++++++++++++++++
+ 2 files changed, 65 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -116,6 +116,7 @@ enum bcm63xx_regs_set {
+ 	RSET_UART1,
+ 	RSET_GPIO,
+ 	RSET_SPI,
++	RSET_HSSPI,
+ 	RSET_UDC0,
+ 	RSET_OHCI0,
+ 	RSET_OHCI_PRIV,
+@@ -159,6 +160,7 @@ enum bcm63xx_regs_set {
+ #define RSET_ENETDMA_SIZE		2048
+ #define RSET_ENETSW_SIZE		65536
+ #define RSET_UART_SIZE			24
++#define RSET_HSSPI_SIZE			1536
+ #define RSET_UDC_SIZE			256
+ #define RSET_OHCI_SIZE			256
+ #define RSET_EHCI_SIZE			256
+@@ -182,6 +184,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6328_UART1_BASE		(0xb0000120)
+ #define BCM_6328_GPIO_BASE		(0xb0000080)
+ #define BCM_6328_SPI_BASE		(0xdeadbeef)
++#define BCM_6328_HSSPI_BASE		(0xb0001000)
+ #define BCM_6328_UDC0_BASE		(0xdeadbeef)
+ #define BCM_6328_USBDMA_BASE		(0xdeadbeef)
+ #define BCM_6328_OHCI0_BASE		(0xdeadbeef)
+@@ -227,6 +230,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6338_UART1_BASE		(0xdeadbeef)
+ #define BCM_6338_GPIO_BASE		(0xfffe0400)
+ #define BCM_6338_SPI_BASE		(0xfffe0c00)
++#define BCM_6338_HSSPI_BASE		(0xdeadbeef)
+ #define BCM_6338_UDC0_BASE		(0xdeadbeef)
+ #define BCM_6338_USBDMA_BASE		(0xfffe2400)
+ #define BCM_6338_OHCI0_BASE		(0xdeadbeef)
+@@ -273,6 +277,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6345_UART1_BASE		(0xdeadbeef)
+ #define BCM_6345_GPIO_BASE		(0xfffe0400)
+ #define BCM_6345_SPI_BASE		(0xdeadbeef)
++#define BCM_6345_HSSPI_BASE		(0xdeadbeef)
+ #define BCM_6345_UDC0_BASE		(0xdeadbeef)
+ #define BCM_6345_USBDMA_BASE		(0xfffe2800)
+ #define BCM_6345_ENET0_BASE		(0xfffe1800)
+@@ -318,6 +323,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6348_UART1_BASE		(0xdeadbeef)
+ #define BCM_6348_GPIO_BASE		(0xfffe0400)
+ #define BCM_6348_SPI_BASE		(0xfffe0c00)
++#define BCM_6348_HSSPI_BASE		(0xdeadbeef)
+ #define BCM_6348_UDC0_BASE		(0xfffe1000)
+ #define BCM_6348_OHCI0_BASE		(0xfffe1b00)
+ #define BCM_6348_OHCI_PRIV_BASE		(0xfffe1c00)
+@@ -361,6 +367,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6358_UART1_BASE		(0xfffe0120)
+ #define BCM_6358_GPIO_BASE		(0xfffe0080)
+ #define BCM_6358_SPI_BASE		(0xfffe0800)
++#define BCM_6358_HSSPI_BASE		(0xdeadbeef)
+ #define BCM_6358_UDC0_BASE		(0xfffe0800)
+ #define BCM_6358_OHCI0_BASE		(0xfffe1400)
+ #define BCM_6358_OHCI_PRIV_BASE		(0xdeadbeef)
+@@ -405,6 +412,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6368_UART1_BASE		(0xb0000120)
+ #define BCM_6368_GPIO_BASE		(0xb0000080)
+ #define BCM_6368_SPI_BASE		(0xb0000800)
++#define BCM_6368_HSSPI_BASE		(0xdeadbeef)
+ #define BCM_6368_UDC0_BASE		(0xdeadbeef)
+ #define BCM_6368_OHCI0_BASE		(0xb0001600)
+ #define BCM_6368_OHCI_PRIV_BASE		(0xdeadbeef)
+@@ -454,6 +462,7 @@ extern const unsigned long *bcm63xx_regs
+ 	__GEN_RSET_BASE(__cpu, UART1)					\
+ 	__GEN_RSET_BASE(__cpu, GPIO)					\
+ 	__GEN_RSET_BASE(__cpu, SPI)					\
++	__GEN_RSET_BASE(__cpu, HSSPI)					\
+ 	__GEN_RSET_BASE(__cpu, UDC0)					\
+ 	__GEN_RSET_BASE(__cpu, OHCI0)					\
+ 	__GEN_RSET_BASE(__cpu, OHCI_PRIV)				\
+@@ -495,6 +504,7 @@ extern const unsigned long *bcm63xx_regs
+ 	[RSET_UART1]		= BCM_## __cpu ##_UART1_BASE,		\
+ 	[RSET_GPIO]		= BCM_## __cpu ##_GPIO_BASE,		\
+ 	[RSET_SPI]		= BCM_## __cpu ##_SPI_BASE,		\
++	[RSET_HSSPI]		= BCM_## __cpu ##_HSSPI_BASE,		\
+ 	[RSET_UDC0]		= BCM_## __cpu ##_UDC0_BASE,		\
+ 	[RSET_OHCI0]		= BCM_## __cpu ##_OHCI0_BASE,		\
+ 	[RSET_OHCI_PRIV]	= BCM_## __cpu ##_OHCI_PRIV_BASE,	\
+@@ -567,6 +577,7 @@ enum bcm63xx_irq {
+ 	IRQ_ENET0,
+ 	IRQ_ENET1,
+ 	IRQ_ENET_PHY,
++	IRQ_HSSPI,
+ 	IRQ_OHCI0,
+ 	IRQ_EHCI0,
+ 	IRQ_ENET0_RXDMA,
+@@ -602,6 +613,7 @@ enum bcm63xx_irq {
+ #define BCM_6328_ENET0_IRQ		0
+ #define BCM_6328_ENET1_IRQ		0
+ #define BCM_6328_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
++#define BCM_6328_HSSPI_IRQ		(IRQ_INTERNAL_BASE + 29)
+ #define BCM_6328_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 9)
+ #define BCM_6328_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
+ #define BCM_6328_PCMCIA_IRQ		0
+@@ -640,6 +652,7 @@ enum bcm63xx_irq {
+ #define BCM_6338_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
+ #define BCM_6338_ENET1_IRQ		0
+ #define BCM_6338_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
++#define BCM_6338_HSSPI_IRQ		0
+ #define BCM_6338_OHCI0_IRQ		0
+ #define BCM_6338_EHCI0_IRQ		0
+ #define BCM_6338_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
+@@ -671,6 +684,7 @@ enum bcm63xx_irq {
+ #define BCM_6345_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
+ #define BCM_6345_ENET1_IRQ		0
+ #define BCM_6345_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
++#define BCM_6345_HSSPI_IRQ		0
+ #define BCM_6345_OHCI0_IRQ		0
+ #define BCM_6345_EHCI0_IRQ		0
+ #define BCM_6345_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 1)
+@@ -702,6 +716,7 @@ enum bcm63xx_irq {
+ #define BCM_6348_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
+ #define BCM_6348_ENET1_IRQ		(IRQ_INTERNAL_BASE + 7)
+ #define BCM_6348_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
++#define BCM_6348_HSSPI_IRQ		0
+ #define BCM_6348_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 12)
+ #define BCM_6348_EHCI0_IRQ		0
+ #define BCM_6348_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 20)
+@@ -733,6 +748,7 @@ enum bcm63xx_irq {
+ #define BCM_6358_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
+ #define BCM_6358_ENET1_IRQ		(IRQ_INTERNAL_BASE + 6)
+ #define BCM_6358_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
++#define BCM_6358_HSSPI_IRQ		0
+ #define BCM_6358_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
+ #define BCM_6358_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
+ #define BCM_6358_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
+@@ -773,6 +789,7 @@ enum bcm63xx_irq {
+ #define BCM_6368_ENET0_IRQ		0
+ #define BCM_6368_ENET1_IRQ		0
+ #define BCM_6368_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 15)
++#define BCM_6368_HSSPI_IRQ		0
+ #define BCM_6368_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
+ #define BCM_6368_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 7)
+ #define BCM_6368_PCMCIA_IRQ		0
+@@ -813,6 +830,7 @@ extern const int *bcm63xx_irqs;
+ 	[IRQ_ENET0]		= BCM_## __cpu ##_ENET0_IRQ,		\
+ 	[IRQ_ENET1]		= BCM_## __cpu ##_ENET1_IRQ,		\
+ 	[IRQ_ENET_PHY]		= BCM_## __cpu ##_ENET_PHY_IRQ,		\
++	[IRQ_HSSPI]		= BCM_## __cpu ##_HSSPI_IRQ,		\
+ 	[IRQ_OHCI0]		= BCM_## __cpu ##_OHCI0_IRQ,		\
+ 	[IRQ_EHCI0]		= BCM_## __cpu ##_EHCI0_IRQ,		\
+ 	[IRQ_ENET0_RXDMA]	= BCM_## __cpu ##_ENET0_RXDMA_IRQ,	\
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1231,4 +1231,51 @@
+ 
+ #define PCIE_DEVICE_OFFSET		0x8000
+ 
++/*************************************************************************
++ * _REG relative to RSET_HSSPI
++ *************************************************************************/
++
++#define HSSPI_GLOBAL_CTRL_REG			0x0
++#define GLOBAL_CTRL_CLK_POLARITY		(1 << 17)
++#define GLOBAL_CTRL_CLK_GATE_SSOFF		(1 << 16)
++
++#define HSSPI_GLOBAL_EXT_TRIGGER_REG		0x4
++
++#define HSSPI_INT_STATUS_REG			0x8
++#define HSSPI_INT_STATUS_MASKED_REG		0xc
++#define HSSPI_INT_MASK_REG			0x10
++
++#define HSSPI_PING0_CMD_DONE			(1 << 0)
++
++#define HSSPI_INT_CLEAR_ALL			0xff001f1f
++
++#define HSSPI_PINGPONG_COMMAND_REG(x)		(0x80 + (x) * 0x40)
++#define PINGPONG_CMD_COMMAND_MASK		0xf
++#define PINGPONG_COMMAND_NOOP			0
++#define PINGPONG_COMMAND_START_NOW		1
++#define PINGPONG_COMMAND_START_TRIGGER		2
++#define PINGPONG_COMMAND_HALT			3
++#define PINGPONG_COMMAND_FLUSH			4
++#define PINGPONG_CMD_PROFILE_SHIFT		8
++#define PINGPONG_CMD_SS_SHIFT			12
++
++#define HSSPI_PINGPONG_STATUS_REG(x)		(0x84 + (x) * 0x40)
++
++#define HSSPI_PROFILE_CLK_CTRL_REG(x)		(0x100 + (x) * 0x20)
++#define CLK_CTRL_ACCUM_RST_ON_LOOP		(1 << 15)
++
++#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x)	(0x104 + (x) * 0x20)
++#define SIGNAL_CTRL_LATCH_RISING		(1 << 12)
++#define SIGNAL_CTRL_LAUNCH_RISING		(1 << 13)
++#define SIGNAL_CTRL_ASYNC_INPUT_PATH		(1 << 16)
++
++#define HSSPI_PROFILE_MODE_CTRL_REG(x)		(0x108 + (x) * 0x20)
++#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT	8
++#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT	12
++#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT	16
++#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT	18
++#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT		24
++
++#define HSSPI_FIFO_REG(x)			(0x200 + (x) * 0x200)
++
+ #endif /* BCM63XX_REGS_H_ */
diff --git a/target/linux/brcm63xx/patches-3.3/309-MIPS-BCM63XX-add-flash-type-detection.patch b/target/linux/brcm63xx/patches-3.3/309-MIPS-BCM63XX-add-flash-type-detection.patch
deleted file mode 100644
index d8d3e247a874..000000000000
--- a/target/linux/brcm63xx/patches-3.3/309-MIPS-BCM63XX-add-flash-type-detection.patch
+++ /dev/null
@@ -1,130 +0,0 @@
-From 0b2451b1cdab390b0b86c60a4765208bb2724d22 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Sat, 2 Jul 2011 14:44:28 +0200
-Subject: [PATCH 26/79] MIPS: BCM63XX: add flash type detection
-
-On BCM6358 and BCM6368 the attached flash type is exposed through a
-bootstrapping register. Use it for auto detecting the flash type on
-those and default to parallel flash for earlier SoCs.
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/bcm63xx/dev-flash.c                      |   60 ++++++++++++++++++--
- .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h   |    6 ++
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h  |    9 +++
- 3 files changed, 69 insertions(+), 6 deletions(-)
-
---- a/arch/mips/bcm63xx/dev-flash.c
-+++ b/arch/mips/bcm63xx/dev-flash.c
-@@ -6,6 +6,7 @@
-  * for more details.
-  *
-  * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
-+ * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
-  */
- 
- #include <linux/init.h>
-@@ -53,16 +54,63 @@ static struct platform_device mtd_dev =
- 	},
- };
- 
--int __init bcm63xx_flash_register(void)
-+static int __init bcm63xx_detect_flash_type(void)
- {
- 	u32 val;
- 
--	/* read base address of boot chip select (0) */
--	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
--	val &= MPI_CSBASE_BASE_MASK;
-+	switch (bcm63xx_get_cpu_id()) {
-+	case BCM6338_CPU_ID:
-+	case BCM6345_CPU_ID:
-+	case BCM6348_CPU_ID:
-+		/* no way to auto detect so assume parallel */
-+		return BCM63XX_FLASH_TYPE_PARALLEL;
-+	case BCM6358_CPU_ID:
-+		val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
-+		if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)
-+			return BCM63XX_FLASH_TYPE_PARALLEL;
-+		else
-+			return BCM63XX_FLASH_TYPE_SERIAL;
-+	case BCM6368_CPU_ID:
-+		val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
-+		switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
-+		case STRAPBUS_6368_BOOT_SEL_NAND:
-+			return BCM63XX_FLASH_TYPE_NAND;
-+		case STRAPBUS_6368_BOOT_SEL_SERIAL:
-+			return BCM63XX_FLASH_TYPE_SERIAL;
-+		case STRAPBUS_6368_BOOT_SEL_PARALLEL:
-+			return BCM63XX_FLASH_TYPE_PARALLEL;
-+		}
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
-+int __init bcm63xx_flash_register(void)
-+{
-+	int flash_type;
-+	u32 val;
- 
--	mtd_resources[0].start = val;
--	mtd_resources[0].end = 0x1FFFFFFF;
-+	flash_type = bcm63xx_detect_flash_type();
- 
--	return platform_device_register(&mtd_dev);
-+	switch (flash_type) {
-+	case BCM63XX_FLASH_TYPE_PARALLEL:
-+		/* read base address of boot chip select (0) */
-+		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-+		val &= MPI_CSBASE_BASE_MASK;
-+
-+		mtd_resources[0].start = val;
-+		mtd_resources[0].end = 0x1FFFFFFF;
-+
-+		return platform_device_register(&mtd_dev);
-+	case BCM63XX_FLASH_TYPE_SERIAL:
-+		pr_warn("unsupported serial flash detected\n");
-+		return -ENODEV;
-+	case BCM63XX_FLASH_TYPE_NAND:
-+		pr_warn("unsupported NAND flash detected\n");
-+		return -ENODEV;
-+	default:
-+		pr_err("flash detection failed for BCM%x: %d",
-+		       bcm63xx_get_cpu_id(), flash_type);
-+		return -ENODEV;
-+	}
- }
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
-@@ -1,6 +1,12 @@
- #ifndef __BCM63XX_FLASH_H
- #define __BCM63XX_FLASH_H
- 
-+enum {
-+	BCM63XX_FLASH_TYPE_PARALLEL,
-+	BCM63XX_FLASH_TYPE_SERIAL,
-+	BCM63XX_FLASH_TYPE_NAND,
-+};
-+
- int __init bcm63xx_flash_register(void);
- 
- #endif /* __BCM63XX_FLASH_H */
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -508,6 +508,15 @@
- #define GPIO_BASEMODE_6368_MASK		0x7
- /* those bits must be kept as read in gpio basemode register*/
- 
-+#define GPIO_STRAPBUS_REG		0x40
-+#define STRAPBUS_6358_BOOT_SEL_PARALLEL	(1 << 1)
-+#define STRAPBUS_6358_BOOT_SEL_SERIAL	(0 << 1)
-+#define STRAPBUS_6368_BOOT_SEL_MASK	0x3
-+#define STRAPBUS_6368_BOOT_SEL_NAND	0
-+#define STRAPBUS_6368_BOOT_SEL_SERIAL	1
-+#define STRAPBUS_6368_BOOT_SEL_PARALLEL	3
-+
-+
- /*************************************************************************
-  * _REG relative to RSET_ENET
-  *************************************************************************/
diff --git a/target/linux/brcm63xx/patches-3.3/310-MIPS-BCM63XX-use-the-Chip-ID-register-for-identifyin.patch b/target/linux/brcm63xx/patches-3.3/310-MIPS-BCM63XX-use-the-Chip-ID-register-for-identifyin.patch
deleted file mode 100644
index 30adbd19855a..000000000000
--- a/target/linux/brcm63xx/patches-3.3/310-MIPS-BCM63XX-use-the-Chip-ID-register-for-identifyin.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From d831de57b1995eff51f43310b4bbfa85b1a3df42 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Fri, 30 Dec 2011 02:37:47 +0100
-Subject: [PATCH 38/79] MIPS: BCM63XX: use the Chip ID register for
- identifying the SoC
-
-Newer BCM63XX SoCs use virtually the same cpu ID. But since they all have
-the Chip ID register at the same location, we can use that to identify
-the SoC we are running on.
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/bcm63xx/cpu.c |   20 ++++++++++++--------
- 1 file changed, 12 insertions(+), 8 deletions(-)
-
---- a/arch/mips/bcm63xx/cpu.c
-+++ b/arch/mips/bcm63xx/cpu.c
-@@ -228,17 +228,21 @@ void __init bcm63xx_cpu_init(void)
- 		bcm63xx_irqs = bcm6345_irqs;
- 		break;
- 	case CPU_BMIPS4350:
--		switch (read_c0_prid() & 0xf0) {
--		case 0x10:
-+		if ((read_c0_prid() & 0xf0) == 0x10) {
- 			expected_cpu_id = BCM6358_CPU_ID;
- 			bcm63xx_regs_base = bcm6358_regs_base;
- 			bcm63xx_irqs = bcm6358_irqs;
--			break;
--		case 0x30:
--			expected_cpu_id = BCM6368_CPU_ID;
--			bcm63xx_regs_base = bcm6368_regs_base;
--			bcm63xx_irqs = bcm6368_irqs;
--			break;
-+		} else {
-+			/* all newer chips have the same chip id location */
-+			u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
-+
-+			switch (chip_id) {
-+			case BCM6368_CPU_ID:
-+				expected_cpu_id = BCM6368_CPU_ID;
-+				bcm63xx_regs_base = bcm6368_regs_base;
-+				bcm63xx_irqs = bcm6368_irqs;
-+				break;
-+			}
- 		}
- 		break;
- 	}
diff --git a/target/linux/brcm63xx/patches-3.3/310-board_leds_naming.patch b/target/linux/brcm63xx/patches-3.3/310-board_leds_naming.patch
new file mode 100644
index 000000000000..798e8018fc55
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/310-board_leds_naming.patch
@@ -0,0 +1,267 @@
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -61,28 +61,28 @@ static struct board_info __initdata boar
+ 
+ 	.leds = {
+ 		{
+-			.name		= "adsl",
++			.name		= "96338GW:green:adsl",
+ 			.gpio		= 3,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ses",
++			.name		= "96338GW:green:ses",
+ 			.gpio		= 5,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ppp-fail",
++			.name		= "96338GW:green:ppp-fail",
+ 			.gpio		= 4,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "power",
++			.name		= "96338GW!green:power",
+ 			.gpio		= 0,
+ 			.active_low	= 1,
+ 			.default_trigger = "default-on",
+ 		},
+ 		{
+-			.name		= "stop",
++			.name		= "96338GW:green:stop",
+ 			.gpio		= 1,
+ 			.active_low	= 1,
+ 		}
+@@ -102,28 +102,28 @@ static struct board_info __initdata boar
+ 
+ 	.leds = {
+ 		{
+-			.name		= "adsl",
++			.name		= "96338W:green:adsl",
+ 			.gpio		= 3,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ses",
++			.name		= "96338W:green:ses",
+ 			.gpio		= 5,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ppp-fail",
++			.name		= "96338W:green:ppp-fail",
+ 			.gpio		= 4,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "power",
++			.name		= "96338W:green:power",
+ 			.gpio		= 0,
+ 			.active_low	= 1,
+ 			.default_trigger = "default-on",
+ 		},
+ 		{
+-			.name		= "stop",
++			.name		= "96338W:green:stop",
+ 			.gpio		= 1,
+ 			.active_low	= 1,
+ 		},
+@@ -162,29 +162,29 @@ static struct board_info __initdata boar
+ 
+ 	.leds = {
+ 		{
+-			.name		= "adsl-fail",
++			.name		= "96348R:green:adsl-fail",
+ 			.gpio		= 2,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ppp",
++			.name		= "96348R:green:ppp",
+ 			.gpio		= 3,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ppp-fail",
++			.name		= "96348R:green:ppp-fail",
+ 			.gpio		= 4,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "power",
++			.name		= "96348R:green:power",
+ 			.gpio		= 0,
+ 			.active_low	= 1,
+ 			.default_trigger = "default-on",
+ 
+ 		},
+ 		{
+-			.name		= "stop",
++			.name		= "96348R:green:stop",
+ 			.gpio		= 1,
+ 			.active_low	= 1,
+ 		},
+@@ -223,28 +223,28 @@ static struct board_info __initdata boar
+ 
+ 	.leds = {
+ 		{
+-			.name		= "adsl-fail",
++			.name		= "96348GW-10:green:adsl-fail",
+ 			.gpio		= 2,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ppp",
++			.name		= "96348GW-10:green:ppp",
+ 			.gpio		= 3,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ppp-fail",
++			.name		= "96348GW-10:green:ppp-fail",
+ 			.gpio		= 4,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "power",
++			.name		= "96348GW-10:green:power",
+ 			.gpio		= 0,
+ 			.active_low	= 1,
+ 			.default_trigger = "default-on",
+ 		},
+ 		{
+-			.name		= "stop",
++			.name		= "96348GW-10:green:stop",
+ 			.gpio		= 1,
+ 			.active_low	= 1,
+ 		},
+@@ -277,28 +277,28 @@ static struct board_info __initdata boar
+ 
+ 	.leds = {
+ 		{
+-			.name		= "adsl-fail",
++			.name		= "96348GW-11:green:adsl-fail",
+ 			.gpio		= 2,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ppp",
++			.name		= "96348GW-11:green:ppp",
+ 			.gpio		= 3,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ppp-fail",
++			.name		= "96348GW-11:green:ppp-fail",
+ 			.gpio		= 4,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "power",
++			.name		= "96348GW-11:green:power",
+ 			.gpio		= 0,
+ 			.active_low	= 1,
+ 			.default_trigger = "default-on",
+ 		},
+ 		{
+-			.name		= "stop",
++			.name		= "96348GW-11:green:stop",
+ 			.gpio		= 1,
+ 			.active_low	= 1,
+ 		},
+@@ -345,28 +345,28 @@ static struct board_info __initdata boar
+ 
+ 	.leds = {
+ 		{
+-			.name		= "adsl-fail",
++			.name		= "96348GW:green:adsl-fail",
+ 			.gpio		= 2,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ppp",
++			.name		= "96348GW:green:ppp",
+ 			.gpio		= 3,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ppp-fail",
++			.name		= "96348GW:green:ppp-fail",
+ 			.gpio		= 4,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "power",
++			.name		= "96348GW:green:power",
+ 			.gpio		= 0,
+ 			.active_low	= 1,
+ 			.default_trigger = "default-on",
+ 		},
+ 		{
+-			.name		= "stop",
++			.name		= "96348GW:green:stop",
+ 			.gpio		= 1,
+ 			.active_low	= 1,
+ 		},
+@@ -498,27 +498,27 @@ static struct board_info __initdata boar
+ 
+ 	.leds = {
+ 		{
+-			.name		= "adsl-fail",
++			.name		= "96358VW:green:adsl-fail",
+ 			.gpio		= 15,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ppp",
++			.name		= "96358VW:green:ppp",
+ 			.gpio		= 22,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ppp-fail",
++			.name		= "96358VW:green:ppp-fail",
+ 			.gpio		= 23,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "power",
++			.name		= "96358VW:green:power",
+ 			.gpio		= 4,
+ 			.default_trigger = "default-on",
+ 		},
+ 		{
+-			.name		= "stop",
++			.name		= "96358VW:green:stop",
+ 			.gpio		= 5,
+ 		},
+ 	},
+@@ -550,22 +550,22 @@ static struct board_info __initdata boar
+ 
+ 	.leds = {
+ 		{
+-			.name		= "adsl",
++			.name		= "96358VW2:green:adsl",
+ 			.gpio		= 22,
+ 			.active_low	= 1,
+ 		},
+ 		{
+-			.name		= "ppp-fail",
++			.name		= "96358VW2:green:ppp-fail",
+ 			.gpio		= 23,
+ 		},
+ 		{
+-			.name		= "power",
++			.name		= "96358VW2:green:power",
+ 			.gpio		= 5,
+ 			.active_low	= 1,
+ 			.default_trigger = "default-on",
+ 		},
+ 		{
+-			.name		= "stop",
++			.name		= "96358VW2:green:stop",
+ 			.gpio		= 4,
+ 			.active_low	= 1,
+ 		},
diff --git a/target/linux/brcm63xx/patches-3.3/311-MIPS-BCM63XX-add-MISC-register-set-definition.patch b/target/linux/brcm63xx/patches-3.3/311-MIPS-BCM63XX-add-MISC-register-set-definition.patch
deleted file mode 100644
index 8d2d9b9da1ab..000000000000
--- a/target/linux/brcm63xx/patches-3.3/311-MIPS-BCM63XX-add-MISC-register-set-definition.patch
+++ /dev/null
@@ -1,107 +0,0 @@
-From 48d3ed67982d2d1cecb5b33bf396d21f6fd7b088 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Tue, 14 Jun 2011 21:14:39 +0200
-Subject: [PATCH 39/79] MIPS: BCM63XX: add MISC register set definition
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |   10 +++++++++-
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h   |    2 ++
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   10 ++++++++++
- 3 files changed, 21 insertions(+), 1 deletion(-)
-
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -129,7 +129,8 @@ enum bcm63xx_regs_set {
- 	RSET_PCMDMA,
- 	RSET_PCMDMAC,
- 	RSET_PCMDMAS,
--	RSET_TRNG
-+	RSET_TRNG,
-+	RSET_MISC
- };
- 
- #define RSET_DSL_LMEM_SIZE		(64 * 1024 * 4)
-@@ -198,6 +199,7 @@ enum bcm63xx_regs_set {
- #define BCM_6338_PCMDMAC_BASE		(0xdeadbeef)
- #define BCM_6338_PCMDMAS_BASE		(0xdeadbeef)
- #define BCM_6338_TRNG_BASE		(0xdeadbeef)
-+#define BCM_6338_MISC_BASE		(0xdeadbeef)
- 
- /*
-  * 6345 register sets base address
-@@ -242,6 +244,7 @@ enum bcm63xx_regs_set {
- #define BCM_6345_PCMDMAC_BASE		(0xdeadbeef)
- #define BCM_6345_PCMDMAS_BASE		(0xdeadbeef)
- #define BCM_6345_TRNG_BASE		(0xdeadbeef)
-+#define BCM_6345_MISC_BASE		(0xdeadbeef)
- 
- /*
-  * 6348 register sets base address
-@@ -283,6 +286,7 @@ enum bcm63xx_regs_set {
- #define BCM_6348_PCMDMAC_BASE		(0xdeadbeef)
- #define BCM_6348_PCMDMAS_BASE		(0xdeadbeef)
- #define BCM_6348_TRNG_BASE		(0xdeadbeef)
-+#define BCM_6348_MISC_BASE		(0xdeadbeef)
- 
- /*
-  * 6358 register sets base address
-@@ -324,6 +328,7 @@ enum bcm63xx_regs_set {
- #define BCM_6358_PCMDMAC_BASE		(0xfffe1900)
- #define BCM_6358_PCMDMAS_BASE		(0xfffe1a00)
- #define BCM_6358_TRNG_BASE		(0xdeadbeef)
-+#define BCM_6358_MISC_BASE		(0xdeadbeef)
- 
- 
- /*
-@@ -366,6 +371,7 @@ enum bcm63xx_regs_set {
- #define BCM_6368_PCMDMAC_BASE		(0xb0005a00)
- #define BCM_6368_PCMDMAS_BASE		(0xb0005c00)
- #define BCM_6368_TRNG_BASE		(0xb0004180)
-+#define BCM_6368_MISC_BASE		(0xdeadbeef)
- 
- 
- extern const unsigned long *bcm63xx_regs_base;
-@@ -412,6 +418,7 @@ extern const unsigned long *bcm63xx_regs
- 	__GEN_RSET_BASE(__cpu, PCMDMAC)					\
- 	__GEN_RSET_BASE(__cpu, PCMDMAS)					\
- 	__GEN_RSET_BASE(__cpu, TRNG)					\
-+	__GEN_RSET_BASE(__cpu, MISC)					\
- 	}
- 
- #define __GEN_CPU_REGS_TABLE(__cpu)					\
-@@ -451,6 +458,7 @@ extern const unsigned long *bcm63xx_regs
- 	[RSET_PCMDMAC]		= BCM_## __cpu ##_PCMDMAC_BASE,		\
- 	[RSET_PCMDMAS]		= BCM_## __cpu ##_PCMDMAS_BASE,		\
- 	[RSET_TRNG]		= BCM_## __cpu ##_TRNG_BASE,		\
-+	[RSET_MISC]		= BCM_## __cpu ##_MISC_BASE,		\
- 
- 
- static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
-@@ -91,5 +91,7 @@
- #define bcm_memc_writel(v, o)	bcm_rset_writel(RSET_MEMC, (v), (o))
- #define bcm_ddr_readl(o)	bcm_rset_readl(RSET_DDR, (o))
- #define bcm_ddr_writel(v, o)	bcm_rset_writel(RSET_DDR, (v), (o))
-+#define bcm_misc_readl(o)	bcm_rset_readl(RSET_MISC, (o))
-+#define bcm_misc_writel(v, o)	bcm_rset_writel(RSET_MISC, (v), (o))
- 
- #endif /* ! BCM63XX_IO_H_ */
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1123,4 +1123,14 @@
- #define TRNG_THRES			0x0c
- #define TRNG_MASK			0x10
- 
-+/*************************************************************************
-+ * _REG relative to RSET_MISC
-+ *************************************************************************/
-+
-+#define MISC_STRAPBUS_6328_REG		0x240
-+#define STRAPBUS_6328_FCVO_SHIFT	7
-+#define STRAPBUS_6328_FCVO_MASK		(0x1f << STRAPBUS_6328_FCVO_SHIFT)
-+#define STRAPBUS_6328_BOOT_SEL_SERIAL	(1 << 28)
-+#define STRAPBUS_6328_BOOT_SEL_NAND	(0 << 28)
-+
- #endif /* BCM63XX_REGS_H_ */
diff --git a/target/linux/brcm63xx/patches-3.3/312-MIPS-BCM63XX-add-basic-BCM6328-CPU-support.patch b/target/linux/brcm63xx/patches-3.3/312-MIPS-BCM63XX-add-basic-BCM6328-CPU-support.patch
deleted file mode 100644
index 69d8ea13f04a..000000000000
--- a/target/linux/brcm63xx/patches-3.3/312-MIPS-BCM63XX-add-basic-BCM6328-CPU-support.patch
+++ /dev/null
@@ -1,472 +0,0 @@
-From e7fd2a00f5d6c5e50976ed931c26fdbfbbacf835 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Tue, 14 Jun 2011 21:14:39 +0200
-Subject: [PATCH 40/79] MIPS: BCM63XX: add basic BCM6328 CPU support
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/bcm63xx/Kconfig                         |    4 +
- arch/mips/bcm63xx/boards/board_bcm963xx.c         |   11 ++-
- arch/mips/bcm63xx/cpu.c                           |   43 +++++++++
- arch/mips/bcm63xx/dev-spi.c                       |    2 +-
- arch/mips/bcm63xx/irq.c                           |   21 +++++
- arch/mips/bcm63xx/prom.c                          |    4 +-
- arch/mips/bcm63xx/setup.c                         |   13 ++-
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |  101 +++++++++++++++++++++
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |    2 +
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   44 +++++++++
- arch/mips/include/asm/mach-bcm63xx/ioremap.h      |    1 +
- 11 files changed, 238 insertions(+), 8 deletions(-)
-
---- a/arch/mips/bcm63xx/Kconfig
-+++ b/arch/mips/bcm63xx/Kconfig
-@@ -1,6 +1,10 @@
- menu "CPU support"
- 	depends on BCM63XX
- 
-+config BCM63XX_CPU_6328
-+	bool "support 6328 CPU"
-+	select HW_HAS_PCI
-+
- config BCM63XX_CPU_6338
- 	bool "support 6338 CPU"
- 	select HW_HAS_PCI
---- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
-+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -761,9 +761,14 @@ void __init board_prom_init(void)
- 	char cfe_version[32];
- 	u32 val;
- 
--	/* read base address of boot chip select (0) */
--	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
--	val &= MPI_CSBASE_BASE_MASK;
-+	/* read base address of boot chip select (0)
-+	 * 6328 does not have MPI but boots from a fixed address */
-+	if (BCMCPU_IS_6328())
-+		val = 0x18000000;
-+	else {
-+		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-+		val &= MPI_CSBASE_BASE_MASK;
-+	}
- 	boot_addr = (u8 *)KSEG1ADDR(val);
- 
- 	/* dump cfe version */
---- a/arch/mips/bcm63xx/cpu.c
-+++ b/arch/mips/bcm63xx/cpu.c
-@@ -29,6 +29,14 @@ static u16 bcm63xx_cpu_rev;
- static unsigned int bcm63xx_cpu_freq;
- static unsigned int bcm63xx_memory_size;
- 
-+static const unsigned long bcm6328_regs_base[] = {
-+	__GEN_CPU_REGS_TABLE(6328)
-+};
-+
-+static const int bcm6328_irqs[] = {
-+	__GEN_CPU_IRQ_TABLE(6328)
-+};
-+
- static const unsigned long bcm6338_regs_base[] = {
- 	__GEN_CPU_REGS_TABLE(6338)
- };
-@@ -99,6 +107,33 @@ unsigned int bcm63xx_get_memory_size(voi
- static unsigned int detect_cpu_clock(void)
- {
- 	switch (bcm63xx_get_cpu_id()) {
-+	case BCM6328_CPU_ID:
-+	{
-+		unsigned int tmp, mips_pll_fcvo;
-+
-+		tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
-+		mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
-+				>> STRAPBUS_6328_FCVO_SHIFT;
-+
-+		switch (mips_pll_fcvo) {
-+		case 0x12:
-+		case 0x14:
-+		case 0x19:
-+			return 160000000;
-+		case 0x1c:
-+			return 192000000;
-+		case 0x13:
-+		case 0x15:
-+			return 200000000;
-+		case 0x1a:
-+			return 384000000;
-+		case 0x16:
-+			return 400000000;
-+		default:
-+			return 320000000;
-+		}
-+
-+	}
- 	case BCM6338_CPU_ID:
- 		/* BCM6338 has a fixed 240 Mhz frequency */
- 		return 240000000;
-@@ -170,6 +205,9 @@ static unsigned int detect_memory_size(v
- 	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
- 	u32 val;
- 
-+	if (BCMCPU_IS_6328())
-+		return bcm_ddr_readl(DDR_CSEND_REG) << 24;
-+
- 	if (BCMCPU_IS_6345()) {
- 		val = bcm_sdram_readl(SDRAM_MBASE_REG);
- 		return (val * 8 * 1024 * 1024);
-@@ -237,6 +275,11 @@ void __init bcm63xx_cpu_init(void)
- 			u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
- 
- 			switch (chip_id) {
-+			case BCM6328_CPU_ID:
-+				expected_cpu_id = BCM6328_CPU_ID;
-+				bcm63xx_regs_base = bcm6328_regs_base;
-+				bcm63xx_irqs = bcm6328_irqs;
-+				break;
- 			case BCM6368_CPU_ID:
- 				expected_cpu_id = BCM6368_CPU_ID;
- 				bcm63xx_regs_base = bcm6368_regs_base;
---- a/arch/mips/bcm63xx/dev-spi.c
-+++ b/arch/mips/bcm63xx/dev-spi.c
-@@ -87,7 +87,7 @@ int __init bcm63xx_spi_register(void)
- {
- 	struct clk *periph_clk;
- 
--	if (BCMCPU_IS_6345())
-+	if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
- 		return -ENODEV;
- 
- 	periph_clk = clk_get(NULL, "periph");
---- a/arch/mips/bcm63xx/irq.c
-+++ b/arch/mips/bcm63xx/irq.c
-@@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(uns
- static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
- 
- #ifndef BCMCPU_RUNTIME_DETECT
-+#ifdef CONFIG_BCM63XX_CPU_6328
-+#define irq_stat_reg		PERF_IRQSTAT_6328_REG
-+#define irq_mask_reg		PERF_IRQMASK_6328_REG
-+#define irq_bits		64
-+#define is_ext_irq_cascaded	1
-+#define ext_irq_start		(BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-+#define ext_irq_end		(BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE)
-+#define ext_irq_count		4
-+#define ext_irq_cfg_reg1	PERF_EXTIRQ_CFG_REG_6328
-+#define ext_irq_cfg_reg2	0
-+#endif
- #ifdef CONFIG_BCM63XX_CPU_6338
- #define irq_stat_reg		PERF_IRQSTAT_6338_REG
- #define irq_mask_reg		PERF_IRQMASK_6338_REG
-@@ -118,6 +129,16 @@ static void bcm63xx_init_irq(void)
- 	irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
- 
- 	switch (bcm63xx_get_cpu_id()) {
-+	case BCM6328_CPU_ID:
-+		irq_stat_addr += PERF_IRQSTAT_6328_REG;
-+		irq_mask_addr += PERF_IRQMASK_6328_REG;
-+		irq_bits = 64;
-+		ext_irq_count = 4;
-+		is_ext_irq_cascaded = 1;
-+		ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
-+		ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
-+		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
-+		break;
- 	case BCM6338_CPU_ID:
- 		irq_stat_addr += PERF_IRQSTAT_6338_REG;
- 		irq_mask_addr += PERF_IRQMASK_6338_REG;
---- a/arch/mips/bcm63xx/prom.c
-+++ b/arch/mips/bcm63xx/prom.c
-@@ -26,7 +26,9 @@ void __init prom_init(void)
- 	bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
- 
- 	/* disable all hardware blocks clock for now */
--	if (BCMCPU_IS_6338())
-+	if (BCMCPU_IS_6328())
-+		mask = CKCTL_6328_ALL_SAFE_EN;
-+	else if (BCMCPU_IS_6338())
- 		mask = CKCTL_6338_ALL_SAFE_EN;
- 	else if (BCMCPU_IS_6345())
- 		mask = CKCTL_6345_ALL_SAFE_EN;
---- a/arch/mips/bcm63xx/setup.c
-+++ b/arch/mips/bcm63xx/setup.c
-@@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
- 
- 	/* mask and clear all external irq */
- 	switch (bcm63xx_get_cpu_id()) {
-+	case BCM6328_CPU_ID:
-+		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
-+		break;
- 	case BCM6338_CPU_ID:
- 		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
- 		break;
-@@ -101,9 +104,13 @@ void bcm63xx_machine_reboot(void)
- 		bcm6348_a1_reboot();
- 
- 	printk(KERN_INFO "triggering watchdog soft-reset...\n");
--	reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
--	reg |= SYS_PLL_SOFT_RESET;
--	bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
-+	if (BCMCPU_IS_6328()) {
-+		bcm_wdt_writel(1, WDT_SOFTRESET_REG);
-+	} else {
-+		reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
-+		reg |= SYS_PLL_SOFT_RESET;
-+		bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
-+	}
- 	while (1)
- 		;
- }
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -9,6 +9,7 @@
-  * compile time if only one CPU support is enabled (idea stolen from
-  * arm mach-types)
-  */
-+#define BCM6328_CPU_ID		0x6328
- #define BCM6338_CPU_ID		0x6338
- #define BCM6345_CPU_ID		0x6345
- #define BCM6348_CPU_ID		0x6348
-@@ -20,6 +21,19 @@ u16 __bcm63xx_get_cpu_id(void);
- u16 bcm63xx_get_cpu_rev(void);
- unsigned int bcm63xx_get_cpu_freq(void);
- 
-+#ifdef CONFIG_BCM63XX_CPU_6328
-+# ifdef bcm63xx_get_cpu_id
-+#  undef bcm63xx_get_cpu_id
-+#  define bcm63xx_get_cpu_id()	__bcm63xx_get_cpu_id()
-+#  define BCMCPU_RUNTIME_DETECT
-+# else
-+#  define bcm63xx_get_cpu_id()	BCM6328_CPU_ID
-+# endif
-+# define BCMCPU_IS_6328()	(bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
-+#else
-+# define BCMCPU_IS_6328()	(0)
-+#endif
-+
- #ifdef CONFIG_BCM63XX_CPU_6338
- # ifdef bcm63xx_get_cpu_id
- #  undef bcm63xx_get_cpu_id
-@@ -157,6 +171,49 @@ enum bcm63xx_regs_set {
- #define RSET_TRNG_SIZE			20
- 
- /*
-+ * 6328 register sets base address
-+ */
-+#define BCM_6328_DSL_LMEM_BASE		(0xdeadbeef)
-+#define BCM_6328_PERF_BASE		(0xb0000000)
-+#define BCM_6328_TIMER_BASE		(0xb0000040)
-+#define BCM_6328_WDT_BASE		(0xb000005c)
-+#define BCM_6328_UART0_BASE             (0xb0000100)
-+#define BCM_6328_UART1_BASE		(0xb0000120)
-+#define BCM_6328_GPIO_BASE		(0xb0000080)
-+#define BCM_6328_SPI_BASE		(0xdeadbeef)
-+#define BCM_6328_UDC0_BASE		(0xdeadbeef)
-+#define BCM_6328_USBDMA_BASE		(0xdeadbeef)
-+#define BCM_6328_OHCI0_BASE		(0xdeadbeef)
-+#define BCM_6328_OHCI_PRIV_BASE		(0xdeadbeef)
-+#define BCM_6328_USBH_PRIV_BASE		(0xdeadbeef)
-+#define BCM_6328_MPI_BASE		(0xdeadbeef)
-+#define BCM_6328_PCMCIA_BASE		(0xdeadbeef)
-+#define BCM_6328_SDRAM_REGS_BASE	(0xdeadbeef)
-+#define BCM_6328_DSL_BASE		(0xb0001900)
-+#define BCM_6328_UBUS_BASE		(0xdeadbeef)
-+#define BCM_6328_ENET0_BASE		(0xdeadbeef)
-+#define BCM_6328_ENET1_BASE		(0xdeadbeef)
-+#define BCM_6328_ENETDMA_BASE		(0xb000d800)
-+#define BCM_6328_ENETDMAC_BASE		(0xb000da00)
-+#define BCM_6328_ENETDMAS_BASE		(0xb000dc00)
-+#define BCM_6328_ENETSW_BASE		(0xb0e00000)
-+#define BCM_6328_EHCI0_BASE		(0x10002500)
-+#define BCM_6328_SDRAM_BASE		(0xdeadbeef)
-+#define BCM_6328_MEMC_BASE		(0xdeadbeef)
-+#define BCM_6328_DDR_BASE		(0xb0003000)
-+#define BCM_6328_M2M_BASE		(0xdeadbeef)
-+#define BCM_6328_ATM_BASE		(0xdeadbeef)
-+#define BCM_6328_XTM_BASE		(0xdeadbeef)
-+#define BCM_6328_XTMDMA_BASE		(0xb000b800)
-+#define BCM_6328_XTMDMAC_BASE		(0xdeadbeef)
-+#define BCM_6328_XTMDMAS_BASE		(0xdeadbeef)
-+#define BCM_6328_PCM_BASE		(0xb000a800)
-+#define BCM_6328_PCMDMA_BASE		(0xdeadbeef)
-+#define BCM_6328_PCMDMAC_BASE		(0xdeadbeef)
-+#define BCM_6328_PCMDMAS_BASE		(0xdeadbeef)
-+#define BCM_6328_TRNG_BASE		(0xdeadbeef)
-+#define BCM_6328_MISC_BASE		(0xb0001800)
-+/*
-  * 6338 register sets base address
-  */
- #define BCM_6338_DSL_LMEM_BASE		(0xfff00000)
-@@ -466,6 +523,9 @@ static inline unsigned long bcm63xx_regs
- #ifdef BCMCPU_RUNTIME_DETECT
- 	return bcm63xx_regs_base[set];
- #else
-+#ifdef CONFIG_BCM63XX_CPU_6328
-+	__GEN_RSET(6328)
-+#endif
- #ifdef CONFIG_BCM63XX_CPU_6338
- 	__GEN_RSET(6338)
- #endif
-@@ -520,6 +580,47 @@ enum bcm63xx_irq {
- };
- 
- /*
-+ * 6328 irqs
-+ */
-+#define BCM_6328_HIGH_IRQ_BASE		(IRQ_INTERNAL_BASE + 32)
-+
-+#define BCM_6328_TIMER_IRQ		(IRQ_INTERNAL_BASE + 31)
-+#define BCM_6328_SPI_IRQ		0
-+#define BCM_6328_UART0_IRQ		(IRQ_INTERNAL_BASE + 28)
-+#define BCM_6328_UART1_IRQ		(BCM_6328_HIGH_IRQ_BASE + 7)
-+#define BCM_6328_DSL_IRQ		(IRQ_INTERNAL_BASE + 4)
-+#define BCM_6328_UDC0_IRQ		0
-+#define BCM_6328_ENET0_IRQ		0
-+#define BCM_6328_ENET1_IRQ		0
-+#define BCM_6328_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
-+#define BCM_6328_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 9)
-+#define BCM_6328_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
-+#define BCM_6328_PCMCIA_IRQ		0
-+#define BCM_6328_ENET0_RXDMA_IRQ	0
-+#define BCM_6328_ENET0_TXDMA_IRQ	0
-+#define BCM_6328_ENET1_RXDMA_IRQ	0
-+#define BCM_6328_ENET1_TXDMA_IRQ	0
-+#define BCM_6328_PCI_IRQ		(IRQ_INTERNAL_BASE + 23)
-+#define BCM_6328_ATM_IRQ		0
-+#define BCM_6328_ENETSW_RXDMA0_IRQ	(BCM_6328_HIGH_IRQ_BASE + 0)
-+#define BCM_6328_ENETSW_RXDMA1_IRQ	(BCM_6328_HIGH_IRQ_BASE + 1)
-+#define BCM_6328_ENETSW_RXDMA2_IRQ	(BCM_6328_HIGH_IRQ_BASE + 2)
-+#define BCM_6328_ENETSW_RXDMA3_IRQ	(BCM_6328_HIGH_IRQ_BASE + 3)
-+#define BCM_6328_ENETSW_TXDMA0_IRQ	(BCM_6328_HIGH_IRQ_BASE + 4)
-+#define BCM_6328_ENETSW_TXDMA1_IRQ	(BCM_6328_HIGH_IRQ_BASE + 5)
-+#define BCM_6328_ENETSW_TXDMA2_IRQ	(BCM_6328_HIGH_IRQ_BASE + 6)
-+#define BCM_6328_ENETSW_TXDMA3_IRQ	(BCM_6328_HIGH_IRQ_BASE + 7)
-+#define BCM_6328_XTM_IRQ		(BCM_6328_HIGH_IRQ_BASE + 31)
-+#define BCM_6328_XTM_DMA0_IRQ		(BCM_6328_HIGH_IRQ_BASE + 11)
-+
-+#define BCM_6328_PCM_DMA0_IRQ		(IRQ_INTERNAL_BASE + 2)
-+#define BCM_6328_PCM_DMA1_IRQ		(IRQ_INTERNAL_BASE + 3)
-+#define BCM_6328_EXT_IRQ0		(IRQ_INTERNAL_BASE + 24)
-+#define BCM_6328_EXT_IRQ1		(IRQ_INTERNAL_BASE + 25)
-+#define BCM_6328_EXT_IRQ2		(IRQ_INTERNAL_BASE + 26)
-+#define BCM_6328_EXT_IRQ3		(IRQ_INTERNAL_BASE + 27)
-+
-+/*
-  * 6338 irqs
-  */
- #define BCM_6338_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
-@@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void);
- static inline unsigned long bcm63xx_gpio_count(void)
- {
- 	switch (bcm63xx_get_cpu_id()) {
-+	case BCM6328_CPU_ID:
-+		return 32;
- 	case BCM6358_CPU_ID:
- 		return 40;
- 	case BCM6338_CPU_ID:
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -15,6 +15,30 @@
- /* Clock Control register */
- #define PERF_CKCTL_REG			0x4
- 
-+#define CKCTL_6328_PHYMIPS_EN		(1 << 0)
-+#define CKCTL_6328_ADSL_QPROC_EN	(1 << 1)
-+#define CKCTL_6328_ADSL_AFE_EN		(1 << 2)
-+#define CKCTL_6328_ADSL_EN		(1 << 3)
-+#define CKCTL_6328_MIPS_EN		(1 << 4)
-+#define CKCTL_6328_SAR_EN		(1 << 5)
-+#define CKCTL_6328_PCM_EN		(1 << 6)
-+#define CKCTL_6328_USBD_EN		(1 << 7)
-+#define CKCTL_6328_USBH_EN		(1 << 8)
-+#define CKCTL_6328_HSSPI_EN		(1 << 9)
-+#define CKCTL_6328_PCIE_EN		(1 << 10)
-+#define CKCTL_6328_ROBOSW_EN		(1 << 11)
-+
-+#define CKCTL_6328_ALL_SAFE_EN		(CKCTL_6328_PHYMIPS_EN |	\
-+					CKCTL_6328_ADSL_QPROC_EN |	\
-+					CKCTL_6328_ADSL_AFE_EN |	\
-+					CKCTL_6328_ADSL_EN |		\
-+					CKCTL_6328_SAR_EN  |		\
-+					CKCTL_6328_PCM_EN  |		\
-+					CKCTL_6328_USBD_EN |		\
-+					CKCTL_6328_USBH_EN |		\
-+					CKCTL_6328_ROBOSW_EN |		\
-+					CKCTL_6328_PCIE_EN)
-+
- #define CKCTL_6338_ADSLPHY_EN		(1 << 0)
- #define CKCTL_6338_MPI_EN		(1 << 1)
- #define CKCTL_6338_DRAM_EN		(1 << 2)
-@@ -119,6 +143,7 @@
- #define SYS_PLL_SOFT_RESET		0x1
- 
- /* Interrupt Mask register */
-+#define PERF_IRQMASK_6328_REG		0x20
- #define PERF_IRQMASK_6338_REG		0xc
- #define PERF_IRQMASK_6345_REG		0xc
- #define PERF_IRQMASK_6348_REG		0xc
-@@ -126,6 +151,7 @@
- #define PERF_IRQMASK_6368_REG		0x20
- 
- /* Interrupt Status register */
-+#define PERF_IRQSTAT_6328_REG		0x28
- #define PERF_IRQSTAT_6338_REG		0x10
- #define PERF_IRQSTAT_6345_REG		0x10
- #define PERF_IRQSTAT_6348_REG		0x10
-@@ -133,6 +159,7 @@
- #define PERF_IRQSTAT_6368_REG		0x28
- 
- /* External Interrupt Configuration register */
-+#define PERF_EXTIRQ_CFG_REG_6328	0x18
- #define PERF_EXTIRQ_CFG_REG_6338	0x14
- #define PERF_EXTIRQ_CFG_REG_6345	0x14
- #define PERF_EXTIRQ_CFG_REG_6348	0x14
-@@ -163,8 +190,21 @@
- 
- /* Soft Reset register */
- #define PERF_SOFTRESET_REG		0x28
-+#define PERF_SOFTRESET_6328_REG		0x10
- #define PERF_SOFTRESET_6368_REG		0x10
- 
-+#define SOFTRESET_6328_SPI_MASK		(1 << 0)
-+#define SOFTRESET_6328_EPHY_MASK	(1 << 1)
-+#define SOFTRESET_6328_SAR_MASK		(1 << 2)
-+#define SOFTRESET_6328_ENETSW_MASK	(1 << 3)
-+#define SOFTRESET_6328_USBS_MASK	(1 << 4)
-+#define SOFTRESET_6328_USBH_MASK	(1 << 5)
-+#define SOFTRESET_6328_PCM_MASK		(1 << 6)
-+#define SOFTRESET_6328_PCIE_CORE_MASK	(1 << 7)
-+#define SOFTRESET_6328_PCIE_MASK	(1 << 8)
-+#define SOFTRESET_6328_PCIE_EXT_MASK	(1 << 9)
-+#define SOFTRESET_6328_PCIE_HARD_MASK	(1 << 10)
-+
- #define SOFTRESET_6338_SPI_MASK		(1 << 0)
- #define SOFTRESET_6338_ENET_MASK	(1 << 2)
- #define SOFTRESET_6338_USBH_MASK	(1 << 3)
-@@ -308,6 +348,8 @@
- /* Watchdog reset length register */
- #define WDT_RSTLEN_REG			0x8
- 
-+/* Watchdog soft reset register (BCM6328 only) */
-+#define WDT_SOFTRESET_REG		0xc
- 
- /*************************************************************************
-  * _REG relative to RSET_UARTx
-@@ -934,6 +976,8 @@
-  * _REG relative to RSET_DDR
-  *************************************************************************/
- 
-+#define DDR_CSEND_REG			0x8
-+
- #define DDR_DMIPSPLLCFG_REG		0x18
- #define DMIPSPLLCFG_M1_SHIFT		0
- #define DMIPSPLLCFG_M1_MASK		(0xff << DMIPSPLLCFG_M1_SHIFT)
---- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
-@@ -18,6 +18,7 @@ static inline int is_bcm63xx_internal_re
- 		if (offset >= 0xfff00000)
- 			return 1;
- 		break;
-+	case BCM6328_CPU_ID:
- 	case BCM6368_CPU_ID:
- 		if (offset >= 0xb0000000 && offset < 0xb1000000)
- 			return 1;
diff --git a/target/linux/brcm63xx/patches-3.3/313-MIPS-BCM63XX-add-flash-type-detection-for-BCM6328.patch b/target/linux/brcm63xx/patches-3.3/313-MIPS-BCM63XX-add-flash-type-detection-for-BCM6328.patch
deleted file mode 100644
index ca6d4d4dc5dd..000000000000
--- a/target/linux/brcm63xx/patches-3.3/313-MIPS-BCM63XX-add-flash-type-detection-for-BCM6328.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From dc087ed1d9d4ae326a47e4a1eef3a079acf4a1f5 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Tue, 14 Jun 2011 21:14:39 +0200
-Subject: [PATCH 41/79] MIPS: BCM63XX: add flash type detection for BCM6328
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/bcm63xx/dev-flash.c |    6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/arch/mips/bcm63xx/dev-flash.c
-+++ b/arch/mips/bcm63xx/dev-flash.c
-@@ -59,6 +59,12 @@ static int __init bcm63xx_detect_flash_t
- 	u32 val;
- 
- 	switch (bcm63xx_get_cpu_id()) {
-+	case BCM6328_CPU_ID:
-+		val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
-+		if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
-+			return BCM63XX_FLASH_TYPE_SERIAL;
-+		else
-+			return BCM63XX_FLASH_TYPE_NAND;
- 	case BCM6338_CPU_ID:
- 	case BCM6345_CPU_ID:
- 	case BCM6348_CPU_ID:
diff --git a/target/linux/brcm63xx/patches-3.3/314-MIPS-BCM63XX-allow-second-UART-on-BCM6328.patch b/target/linux/brcm63xx/patches-3.3/314-MIPS-BCM63XX-allow-second-UART-on-BCM6328.patch
deleted file mode 100644
index 1418d65bf4c7..000000000000
--- a/target/linux/brcm63xx/patches-3.3/314-MIPS-BCM63XX-allow-second-UART-on-BCM6328.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From c110865541e2d3782c412af9d48c016de5a64d9c Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Tue, 14 Jun 2011 21:14:39 +0200
-Subject: [PATCH 42/79] MIPS: BCM63XX: allow second UART on BCM6328
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/bcm63xx/dev-uart.c |    3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/arch/mips/bcm63xx/dev-uart.c
-+++ b/arch/mips/bcm63xx/dev-uart.c
-@@ -54,7 +54,8 @@ int __init bcm63xx_uart_register(unsigne
- 	if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
- 		return -ENODEV;
- 
--	if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
-+	if (id == 1 && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
-+	    !BCMCPU_IS_6368())
- 		return -ENODEV;
- 
- 	if (id == 0) {
diff --git a/target/linux/brcm63xx/patches-3.3/315-MIPS-BCM63XX-Move-the-PCI-initialization-into-its-ow.patch b/target/linux/brcm63xx/patches-3.3/315-MIPS-BCM63XX-Move-the-PCI-initialization-into-its-ow.patch
deleted file mode 100644
index fe343e0e104b..000000000000
--- a/target/linux/brcm63xx/patches-3.3/315-MIPS-BCM63XX-Move-the-PCI-initialization-into-its-ow.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From f7d09679600b187fcfa1d70819e53f190fb1c231 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Sun, 3 Jul 2011 03:08:11 +0200
-Subject: [PATCH 45/79] MIPS: BCM63XX: Move the PCI initialization into its
- own function
-
-Also make the cpu check a bit more explicit.
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/pci/pci-bcm63xx.c |   25 +++++++++++++++++--------
- 1 file changed, 17 insertions(+), 8 deletions(-)
-
---- a/arch/mips/pci/pci-bcm63xx.c
-+++ b/arch/mips/pci/pci-bcm63xx.c
-@@ -88,14 +88,10 @@ static void bcm63xx_int_cfg_writel(u32 v
- 
- void __iomem *pci_iospace_start;
- 
--int __init bcm63xx_pci_register(void)
-+static int __init bcm63xx_register_pci(void)
- {
- 	unsigned int mem_size;
- 	u32 val;
--
--	if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
--		return -ENODEV;
--
- 	/*
- 	 * configuration  access are  done through  IO space,  remap 4
- 	 * first bytes to access it from CPU.
-@@ -211,3 +207,16 @@ int __init bcm63xx_pci_register(void)
- 			   "bcm63xx PCI IO space");
- 	return 0;
- }
-+
-+int __init bcm63xx_pci_register(void)
-+{
-+	switch (bcm63xx_get_cpu_id()) {
-+	case BCM6348_CPU_ID:
-+	case BCM6358_CPU_ID:
-+	case BCM6368_CPU_ID:
-+		return bcm63xx_register_pci();
-+	default:
-+		return -ENODEV;
-+	}
-+}
-+
diff --git a/target/linux/brcm63xx/patches-3.3/316-MIPS-BCM63XX-Add-PCIe-register-set-definitions.patch b/target/linux/brcm63xx/patches-3.3/316-MIPS-BCM63XX-Add-PCIe-register-set-definitions.patch
deleted file mode 100644
index b561bf143f01..000000000000
--- a/target/linux/brcm63xx/patches-3.3/316-MIPS-BCM63XX-Add-PCIe-register-set-definitions.patch
+++ /dev/null
@@ -1,176 +0,0 @@
-From 9a16718a325c1969422eb9d9b644eb89ce06692c Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Sun, 3 Jul 2011 03:41:02 +0200
-Subject: [PATCH 46/79] MIPS: BCM63XX: Add PCIe register set definitions
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |    9 ++++
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h   |    6 +++
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   54 +++++++++++++++++++++
- 3 files changed, 69 insertions(+)
-
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -122,6 +122,7 @@ enum bcm63xx_regs_set {
- 	RSET_USBH_PRIV,
- 	RSET_MPI,
- 	RSET_PCMCIA,
-+	RSET_PCIE,
- 	RSET_DSL,
- 	RSET_ENET0,
- 	RSET_ENET1,
-@@ -188,6 +189,7 @@ enum bcm63xx_regs_set {
- #define BCM_6328_USBH_PRIV_BASE		(0xdeadbeef)
- #define BCM_6328_MPI_BASE		(0xdeadbeef)
- #define BCM_6328_PCMCIA_BASE		(0xdeadbeef)
-+#define BCM_6328_PCIE_BASE		(0xb0e40000)
- #define BCM_6328_SDRAM_REGS_BASE	(0xdeadbeef)
- #define BCM_6328_DSL_BASE		(0xb0001900)
- #define BCM_6328_UBUS_BASE		(0xdeadbeef)
-@@ -232,6 +234,7 @@ enum bcm63xx_regs_set {
- #define BCM_6338_USBH_PRIV_BASE		(0xdeadbeef)
- #define BCM_6338_MPI_BASE		(0xfffe3160)
- #define BCM_6338_PCMCIA_BASE		(0xdeadbeef)
-+#define BCM_6338_PCIE_BASE		(0xdeadbeef)
- #define BCM_6338_SDRAM_REGS_BASE	(0xfffe3100)
- #define BCM_6338_DSL_BASE		(0xfffe1000)
- #define BCM_6338_UBUS_BASE		(0xdeadbeef)
-@@ -279,6 +282,7 @@ enum bcm63xx_regs_set {
- #define BCM_6345_ENETSW_BASE		(0xdeadbeef)
- #define BCM_6345_PCMCIA_BASE		(0xfffe2028)
- #define BCM_6345_MPI_BASE		(0xfffe2000)
-+#define BCM_6345_PCIE_BASE		(0xdeadbeef)
- #define BCM_6345_OHCI0_BASE		(0xfffe2100)
- #define BCM_6345_OHCI_PRIV_BASE		(0xfffe2200)
- #define BCM_6345_USBH_PRIV_BASE		(0xdeadbeef)
-@@ -320,6 +324,7 @@ enum bcm63xx_regs_set {
- #define BCM_6348_USBH_PRIV_BASE		(0xdeadbeef)
- #define BCM_6348_MPI_BASE		(0xfffe2000)
- #define BCM_6348_PCMCIA_BASE		(0xfffe2054)
-+#define BCM_6348_PCIE_BASE		(0xdeadbeef)
- #define BCM_6348_SDRAM_REGS_BASE	(0xfffe2300)
- #define BCM_6348_M2M_BASE		(0xfffe2800)
- #define BCM_6348_DSL_BASE		(0xfffe3000)
-@@ -362,6 +367,7 @@ enum bcm63xx_regs_set {
- #define BCM_6358_USBH_PRIV_BASE		(0xfffe1500)
- #define BCM_6358_MPI_BASE		(0xfffe1000)
- #define BCM_6358_PCMCIA_BASE		(0xfffe1054)
-+#define BCM_6358_PCIE_BASE		(0xdeadbeef)
- #define BCM_6358_SDRAM_REGS_BASE	(0xfffe2300)
- #define BCM_6358_M2M_BASE		(0xdeadbeef)
- #define BCM_6358_DSL_BASE		(0xfffe3000)
-@@ -405,6 +411,7 @@ enum bcm63xx_regs_set {
- #define BCM_6368_USBH_PRIV_BASE		(0xb0001700)
- #define BCM_6368_MPI_BASE		(0xb0001000)
- #define BCM_6368_PCMCIA_BASE		(0xb0001054)
-+#define BCM_6368_PCIE_BASE		(0xdeadbeef)
- #define BCM_6368_SDRAM_REGS_BASE	(0xdeadbeef)
- #define BCM_6368_M2M_BASE		(0xdeadbeef)
- #define BCM_6368_DSL_BASE		(0xdeadbeef)
-@@ -453,6 +460,7 @@ extern const unsigned long *bcm63xx_regs
- 	__GEN_RSET_BASE(__cpu, USBH_PRIV)				\
- 	__GEN_RSET_BASE(__cpu, MPI)					\
- 	__GEN_RSET_BASE(__cpu, PCMCIA)					\
-+	__GEN_RSET_BASE(__cpu, PCIE)					\
- 	__GEN_RSET_BASE(__cpu, DSL)					\
- 	__GEN_RSET_BASE(__cpu, ENET0)					\
- 	__GEN_RSET_BASE(__cpu, ENET1)					\
-@@ -493,6 +501,7 @@ extern const unsigned long *bcm63xx_regs
- 	[RSET_USBH_PRIV]	= BCM_## __cpu ##_USBH_PRIV_BASE,	\
- 	[RSET_MPI]		= BCM_## __cpu ##_MPI_BASE,		\
- 	[RSET_PCMCIA]		= BCM_## __cpu ##_PCMCIA_BASE,		\
-+	[RSET_PCIE]		= BCM_## __cpu ##_PCIE_BASE,		\
- 	[RSET_DSL]		= BCM_## __cpu ##_DSL_BASE,		\
- 	[RSET_ENET0]		= BCM_## __cpu ##_ENET0_BASE,		\
- 	[RSET_ENET1]		= BCM_## __cpu ##_ENET1_BASE,		\
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
-@@ -40,6 +40,10 @@
- #define BCM_CB_MEM_END_PA		(BCM_CB_MEM_BASE_PA +		\
- 					BCM_CB_MEM_SIZE - 1)
- 
-+#define BCM_PCIE_MEM_BASE_PA		0x10f00000
-+#define BCM_PCIE_MEM_SIZE		(16 * 1024 * 1024)
-+#define BCM_PCIE_MEM_END_PA		(BCM_PCIE_MEM_BASE_PA +		\
-+					BCM_PCIE_MEM_SIZE - 1)
- 
- /*
-  * Internal registers are accessed through KSEG3
-@@ -85,6 +89,8 @@
- #define bcm_mpi_writel(v, o)	bcm_rset_writel(RSET_MPI, (v), (o))
- #define bcm_pcmcia_readl(o)	bcm_rset_readl(RSET_PCMCIA, (o))
- #define bcm_pcmcia_writel(v, o)	bcm_rset_writel(RSET_PCMCIA, (v), (o))
-+#define bcm_pcie_readl(o)	bcm_rset_readl(RSET_PCIE, (o))
-+#define bcm_pcie_writel(v, o)	bcm_rset_writel(RSET_PCIE, (v), (o))
- #define bcm_sdram_readl(o)	bcm_rset_readl(RSET_SDRAM, (o))
- #define bcm_sdram_writel(v, o)	bcm_rset_writel(RSET_SDRAM, (v), (o))
- #define bcm_memc_readl(o)	bcm_rset_readl(RSET_MEMC, (o))
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1170,6 +1170,9 @@
- /*************************************************************************
-  * _REG relative to RSET_MISC
-  *************************************************************************/
-+#define MISC_SERDES_CTRL_REG		0x0
-+#define SERDES_PCIE_EN			(1 << 0)
-+#define SERDES_PCIE_EXD_EN		(1 << 15)
- 
- #define MISC_STRAPBUS_6328_REG		0x240
- #define STRAPBUS_6328_FCVO_SHIFT	7
-@@ -1177,4 +1180,55 @@
- #define STRAPBUS_6328_BOOT_SEL_SERIAL	(1 << 28)
- #define STRAPBUS_6328_BOOT_SEL_NAND	(0 << 28)
- 
-+/*************************************************************************
-+ * _REG relative to RSET_PCIE
-+ *************************************************************************/
-+
-+#define PCIE_CONFIG2_REG		0x408
-+#define CONFIG2_BAR1_SIZE_EN		1
-+#define CONFIG2_BAR1_SIZE_MASK		0xf
-+
-+#define PCIE_IDVAL3_REG			0x43c
-+#define IDVAL3_CLASS_CODE_MASK		0xffffff
-+#define IDVAL3_SUBCLASS_SHIFT		8
-+#define IDVAL3_CLASS_SHIFT		16
-+
-+#define PCIE_DLSTATUS_REG		0x1048
-+#define DLSTATUS_PHYLINKUP		(1 << 13)
-+
-+#define PCIE_BRIDGE_OPT1_REG		0x2820
-+#define OPT1_RD_BE_OPT_EN		(1 << 7)
-+#define OPT1_RD_REPLY_BE_FIX_EN		(1 << 9)
-+#define OPT1_PCIE_BRIDGE_HOLE_DET_EN	(1 << 11)
-+#define OPT1_L1_INT_STATUS_MASK_POL	(1 << 12)
-+
-+#define PCIE_BRIDGE_OPT2_REG		0x2824
-+#define OPT2_UBUS_UR_DECODE_DIS		(1 << 2)
-+#define OPT2_TX_CREDIT_CHK_EN		(1 << 4)
-+#define OPT2_CFG_TYPE1_BD_SEL		(1 << 7)
-+#define OPT2_CFG_TYPE1_BUS_NO_SHIFT	16
-+#define OPT2_CFG_TYPE1_BUS_NO_MASK	(0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
-+
-+#define PCIE_BRIDGE_BAR0_BASEMASK_REG	0x2828
-+#define PCIE_BRIDGE_BAR1_BASEMASK_REG	0x2830
-+#define BASEMASK_REMAP_EN		(1 << 0)
-+#define BASEMASK_SWAP_EN		(1 << 1)
-+#define BASEMASK_MASK_SHIFT		4
-+#define BASEMASK_MASK_MASK		(0xfff << BASEMASK_MASK_SHIFT)
-+#define BASEMASK_BASE_SHIFT		20
-+#define BASEMASK_BASE_MASK		(0xfff << BASEMASK_BASE_SHIFT)
-+
-+#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
-+#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
-+#define REBASE_ADDR_BASE_SHIFT		20
-+#define REBASE_ADDR_BASE_MASK		(0xfff << REBASE_ADDR_BASE_SHIFT)
-+
-+#define PCIE_BRIDGE_RC_INT_MASK_REG	0x2854
-+#define PCIE_RC_INT_A			(1 << 0)
-+#define PCIE_RC_INT_B			(1 << 1)
-+#define PCIE_RC_INT_C			(1 << 2)
-+#define PCIE_RC_INT_D			(1 << 3)
-+
-+#define PCIE_DEVICE_OFFSET		0x8000
-+
- #endif /* BCM63XX_REGS_H_ */
diff --git a/target/linux/brcm63xx/patches-3.3/317-MIPS-BCM63XX-Add-PCIe-Support-for-BCM6328.patch b/target/linux/brcm63xx/patches-3.3/317-MIPS-BCM63XX-Add-PCIe-Support-for-BCM6328.patch
deleted file mode 100644
index c33aaa438b1a..000000000000
--- a/target/linux/brcm63xx/patches-3.3/317-MIPS-BCM63XX-Add-PCIe-Support-for-BCM6328.patch
+++ /dev/null
@@ -1,240 +0,0 @@
-From e170282d7d12f4a26f10d4b666b158d24810d2f6 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Sun, 3 Jul 2011 03:41:02 +0200
-Subject: [PATCH 47/79] MIPS: BCM63XX: Add PCIe Support for BCM6328
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/pci/ops-bcm63xx.c |   61 +++++++++++++++++++++++
- arch/mips/pci/pci-bcm63xx.c |  112 +++++++++++++++++++++++++++++++++++++++++++
- arch/mips/pci/pci-bcm63xx.h |    5 ++
- 3 files changed, 178 insertions(+)
-
---- a/arch/mips/pci/ops-bcm63xx.c
-+++ b/arch/mips/pci/ops-bcm63xx.c
-@@ -465,3 +465,64 @@ static void bcm63xx_fixup(struct pci_dev
- 
- DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
- #endif
-+
-+static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
-+{
-+	switch (bus->number) {
-+	case PCIE_BUS_BRIDGE:
-+		return (PCI_SLOT(devfn) == 0);
-+	case PCIE_BUS_DEVICE:
-+		if (PCI_SLOT(devfn) == 0)
-+			return bcm_pcie_readl(PCIE_DLSTATUS_REG)
-+					& DLSTATUS_PHYLINKUP;
-+	default:
-+		return false;
-+	}
-+}
-+
-+static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn,
-+			     int where, int size, u32 *val)
-+{
-+	u32 data;
-+	u32 reg = where & ~3;
-+
-+	if (!bcm63xx_pcie_can_access(bus, devfn))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	if (bus->number == PCIE_BUS_DEVICE)
-+		reg += PCIE_DEVICE_OFFSET;
-+
-+	data = bcm_pcie_readl(reg);
-+
-+	*val = postprocess_read(data, where, size);
-+
-+	return PCIBIOS_SUCCESSFUL;
-+
-+}
-+
-+static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
-+			      int where, int size, u32 val)
-+{
-+	u32 data;
-+	u32 reg = where & ~3;
-+
-+	if (!bcm63xx_pcie_can_access(bus, devfn))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	if (bus->number == PCIE_BUS_DEVICE)
-+		reg += PCIE_DEVICE_OFFSET;
-+
-+
-+	data = bcm_pcie_readl(reg);
-+
-+	data = preprocess_write(data, val, where, size);
-+	bcm_pcie_writel(data, reg);
-+
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+
-+struct pci_ops bcm63xx_pcie_ops = {
-+	.read   = bcm63xx_pcie_read,
-+	.write  = bcm63xx_pcie_write
-+};
---- a/arch/mips/pci/pci-bcm63xx.c
-+++ b/arch/mips/pci/pci-bcm63xx.c
-@@ -10,6 +10,7 @@
- #include <linux/pci.h>
- #include <linux/kernel.h>
- #include <linux/init.h>
-+#include <linux/delay.h>
- #include <asm/bootinfo.h>
- 
- #include "pci-bcm63xx.h"
-@@ -65,6 +66,26 @@ struct pci_controller bcm63xx_cb_control
- };
- #endif
- 
-+static struct resource bcm_pcie_mem_resource = {
-+	.name   = "bcm63xx PCIe memory space",
-+	.start  = BCM_PCIE_MEM_BASE_PA,
-+	.end    = BCM_PCIE_MEM_END_PA,
-+	.flags  = IORESOURCE_MEM,
-+};
-+
-+static struct resource bcm_pcie_io_resource = {
-+	.name   = "bcm63xx PCIe IO space",
-+	.start  = 0,
-+	.end    = 0,
-+	.flags  = 0,
-+};
-+
-+struct pci_controller bcm63xx_pcie_controller = {
-+	.pci_ops	= &bcm63xx_pcie_ops,
-+	.io_resource	= &bcm_pcie_io_resource,
-+	.mem_resource	= &bcm_pcie_mem_resource,
-+};
-+
- static u32 bcm63xx_int_cfg_readl(u32 reg)
- {
- 	u32 tmp;
-@@ -88,6 +109,95 @@ static void bcm63xx_int_cfg_writel(u32 v
- 
- void __iomem *pci_iospace_start;
- 
-+static void __init bcm63xx_reset_pcie(void)
-+{
-+	u32 val;
-+
-+	/* enable clock */
-+	val = bcm_perf_readl(PERF_CKCTL_REG);
-+	val |= CKCTL_6328_PCIE_EN;
-+	bcm_perf_writel(val, PERF_CKCTL_REG);
-+
-+	/* enable SERDES */
-+	val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
-+	val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
-+	bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
-+
-+	/* reset the PCIe core */
-+	val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
-+
-+	val &= ~SOFTRESET_6328_PCIE_MASK;
-+	val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
-+	val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
-+	val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
-+	bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
-+	mdelay(10);
-+
-+	val |= SOFTRESET_6328_PCIE_MASK;
-+	val |= SOFTRESET_6328_PCIE_CORE_MASK;
-+	val |= SOFTRESET_6328_PCIE_HARD_MASK;
-+	bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
-+	mdelay(10);
-+
-+	val |= SOFTRESET_6328_PCIE_EXT_MASK;
-+	bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
-+	mdelay(200);
-+}
-+
-+static int __init bcm63xx_register_pcie(void)
-+{
-+	u32 val;
-+
-+	bcm63xx_reset_pcie();
-+
-+	/* configure the PCIe bridge */
-+	val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
-+	val |= OPT1_RD_BE_OPT_EN;
-+	val |= OPT1_RD_REPLY_BE_FIX_EN;
-+	val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
-+	val |= OPT1_L1_INT_STATUS_MASK_POL;
-+	bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
-+
-+	/* setup the interrupts */
-+	val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
-+	val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
-+	bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
-+
-+	val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
-+	/* enable credit checking and error checking */
-+	val |= OPT2_TX_CREDIT_CHK_EN;
-+	val |= OPT2_UBUS_UR_DECODE_DIS;
-+
-+	/* set device bus/func for the pcie device */
-+	val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
-+	val |= OPT2_CFG_TYPE1_BD_SEL;
-+	bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
-+
-+	/* setup class code as bridge */
-+	val = bcm_pcie_readl(PCIE_IDVAL3_REG);
-+	val &= ~IDVAL3_CLASS_CODE_MASK;
-+	val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
-+	bcm_pcie_writel(val, PCIE_IDVAL3_REG);
-+
-+	/* disable bar1 size */
-+	val = bcm_pcie_readl(PCIE_CONFIG2_REG);
-+	val &= ~CONFIG2_BAR1_SIZE_MASK;
-+	bcm_pcie_writel(val, PCIE_CONFIG2_REG);
-+
-+	/* set bar0 to little endian */
-+	val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
-+	val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
-+	val |= BASEMASK_REMAP_EN;
-+	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
-+
-+	val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
-+	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
-+
-+	register_pci_controller(&bcm63xx_pcie_controller);
-+
-+	return 0;
-+}
-+
- static int __init bcm63xx_register_pci(void)
- {
- 	unsigned int mem_size;
-@@ -211,6 +321,8 @@ static int __init bcm63xx_register_pci(v
- int __init bcm63xx_pci_register(void)
- {
- 	switch (bcm63xx_get_cpu_id()) {
-+	case BCM6328_CPU_ID:
-+		return bcm63xx_register_pcie();
- 	case BCM6348_CPU_ID:
- 	case BCM6358_CPU_ID:
- 	case BCM6368_CPU_ID:
---- a/arch/mips/pci/pci-bcm63xx.h
-+++ b/arch/mips/pci/pci-bcm63xx.h
-@@ -13,11 +13,16 @@
-  */
- #define CARDBUS_PCI_IDSEL	0x8
- 
-+
-+#define PCIE_BUS_BRIDGE		0
-+#define PCIE_BUS_DEVICE		1
-+
- /*
-  * defined in ops-bcm63xx.c
-  */
- extern struct pci_ops bcm63xx_pci_ops;
- extern struct pci_ops bcm63xx_cb_ops;
-+extern struct pci_ops bcm63xx_pcie_ops;
- 
- /*
-  * defined in pci-bcm63xx.c
diff --git a/target/linux/brcm63xx/patches-3.3/318-MIPS-BCM63XX-expose-the-HS-SPI-clock.patch b/target/linux/brcm63xx/patches-3.3/318-MIPS-BCM63XX-expose-the-HS-SPI-clock.patch
deleted file mode 100644
index 8a11f8266e03..000000000000
--- a/target/linux/brcm63xx/patches-3.3/318-MIPS-BCM63XX-expose-the-HS-SPI-clock.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 5aeb6273a610f8aab090b3499827177eb41311ba Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Sat, 12 Nov 2011 12:19:09 +0100
-Subject: [PATCH 53/79] MIPS: BCM63XX: expose the HS SPI clock
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/bcm63xx/clk.c |   22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/mips/bcm63xx/clk.c
-+++ b/arch/mips/bcm63xx/clk.c
-@@ -194,6 +194,26 @@ static struct clk clk_spi = {
- };
- 
- /*
-+ * SPI clock
-+ */
-+static void hsspi_set(struct clk *clk, int enable)
-+{
-+	u32 mask;
-+
-+	if (BCMCPU_IS_6328())
-+		mask = CKCTL_6328_HSSPI_EN;
-+	else
-+		return;
-+
-+	bcm_hwclock_set(mask, enable);
-+}
-+
-+static struct clk clk_hsspi = {
-+	.set	= hsspi_set,
-+};
-+
-+
-+/*
-  * XTM clock
-  */
- static void xtm_set(struct clk *clk, int enable)
-@@ -286,6 +306,8 @@ struct clk *clk_get(struct device *dev,
- 		return &clk_usbh;
- 	if (!strcmp(id, "spi"))
- 		return &clk_spi;
-+	if (!strcmp(id, "hsspi"))
-+		return &clk_hsspi;
- 	if (!strcmp(id, "xtm"))
- 		return &clk_xtm;
- 	if (!strcmp(id, "periph"))
diff --git a/target/linux/brcm63xx/patches-3.3/319-board_leds_naming.patch b/target/linux/brcm63xx/patches-3.3/319-board_leds_naming.patch
deleted file mode 100644
index 798e8018fc55..000000000000
--- a/target/linux/brcm63xx/patches-3.3/319-board_leds_naming.patch
+++ /dev/null
@@ -1,267 +0,0 @@
---- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
-+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -61,28 +61,28 @@ static struct board_info __initdata boar
- 
- 	.leds = {
- 		{
--			.name		= "adsl",
-+			.name		= "96338GW:green:adsl",
- 			.gpio		= 3,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ses",
-+			.name		= "96338GW:green:ses",
- 			.gpio		= 5,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ppp-fail",
-+			.name		= "96338GW:green:ppp-fail",
- 			.gpio		= 4,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "power",
-+			.name		= "96338GW!green:power",
- 			.gpio		= 0,
- 			.active_low	= 1,
- 			.default_trigger = "default-on",
- 		},
- 		{
--			.name		= "stop",
-+			.name		= "96338GW:green:stop",
- 			.gpio		= 1,
- 			.active_low	= 1,
- 		}
-@@ -102,28 +102,28 @@ static struct board_info __initdata boar
- 
- 	.leds = {
- 		{
--			.name		= "adsl",
-+			.name		= "96338W:green:adsl",
- 			.gpio		= 3,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ses",
-+			.name		= "96338W:green:ses",
- 			.gpio		= 5,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ppp-fail",
-+			.name		= "96338W:green:ppp-fail",
- 			.gpio		= 4,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "power",
-+			.name		= "96338W:green:power",
- 			.gpio		= 0,
- 			.active_low	= 1,
- 			.default_trigger = "default-on",
- 		},
- 		{
--			.name		= "stop",
-+			.name		= "96338W:green:stop",
- 			.gpio		= 1,
- 			.active_low	= 1,
- 		},
-@@ -162,29 +162,29 @@ static struct board_info __initdata boar
- 
- 	.leds = {
- 		{
--			.name		= "adsl-fail",
-+			.name		= "96348R:green:adsl-fail",
- 			.gpio		= 2,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ppp",
-+			.name		= "96348R:green:ppp",
- 			.gpio		= 3,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ppp-fail",
-+			.name		= "96348R:green:ppp-fail",
- 			.gpio		= 4,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "power",
-+			.name		= "96348R:green:power",
- 			.gpio		= 0,
- 			.active_low	= 1,
- 			.default_trigger = "default-on",
- 
- 		},
- 		{
--			.name		= "stop",
-+			.name		= "96348R:green:stop",
- 			.gpio		= 1,
- 			.active_low	= 1,
- 		},
-@@ -223,28 +223,28 @@ static struct board_info __initdata boar
- 
- 	.leds = {
- 		{
--			.name		= "adsl-fail",
-+			.name		= "96348GW-10:green:adsl-fail",
- 			.gpio		= 2,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ppp",
-+			.name		= "96348GW-10:green:ppp",
- 			.gpio		= 3,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ppp-fail",
-+			.name		= "96348GW-10:green:ppp-fail",
- 			.gpio		= 4,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "power",
-+			.name		= "96348GW-10:green:power",
- 			.gpio		= 0,
- 			.active_low	= 1,
- 			.default_trigger = "default-on",
- 		},
- 		{
--			.name		= "stop",
-+			.name		= "96348GW-10:green:stop",
- 			.gpio		= 1,
- 			.active_low	= 1,
- 		},
-@@ -277,28 +277,28 @@ static struct board_info __initdata boar
- 
- 	.leds = {
- 		{
--			.name		= "adsl-fail",
-+			.name		= "96348GW-11:green:adsl-fail",
- 			.gpio		= 2,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ppp",
-+			.name		= "96348GW-11:green:ppp",
- 			.gpio		= 3,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ppp-fail",
-+			.name		= "96348GW-11:green:ppp-fail",
- 			.gpio		= 4,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "power",
-+			.name		= "96348GW-11:green:power",
- 			.gpio		= 0,
- 			.active_low	= 1,
- 			.default_trigger = "default-on",
- 		},
- 		{
--			.name		= "stop",
-+			.name		= "96348GW-11:green:stop",
- 			.gpio		= 1,
- 			.active_low	= 1,
- 		},
-@@ -345,28 +345,28 @@ static struct board_info __initdata boar
- 
- 	.leds = {
- 		{
--			.name		= "adsl-fail",
-+			.name		= "96348GW:green:adsl-fail",
- 			.gpio		= 2,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ppp",
-+			.name		= "96348GW:green:ppp",
- 			.gpio		= 3,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ppp-fail",
-+			.name		= "96348GW:green:ppp-fail",
- 			.gpio		= 4,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "power",
-+			.name		= "96348GW:green:power",
- 			.gpio		= 0,
- 			.active_low	= 1,
- 			.default_trigger = "default-on",
- 		},
- 		{
--			.name		= "stop",
-+			.name		= "96348GW:green:stop",
- 			.gpio		= 1,
- 			.active_low	= 1,
- 		},
-@@ -498,27 +498,27 @@ static struct board_info __initdata boar
- 
- 	.leds = {
- 		{
--			.name		= "adsl-fail",
-+			.name		= "96358VW:green:adsl-fail",
- 			.gpio		= 15,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ppp",
-+			.name		= "96358VW:green:ppp",
- 			.gpio		= 22,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ppp-fail",
-+			.name		= "96358VW:green:ppp-fail",
- 			.gpio		= 23,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "power",
-+			.name		= "96358VW:green:power",
- 			.gpio		= 4,
- 			.default_trigger = "default-on",
- 		},
- 		{
--			.name		= "stop",
-+			.name		= "96358VW:green:stop",
- 			.gpio		= 5,
- 		},
- 	},
-@@ -550,22 +550,22 @@ static struct board_info __initdata boar
- 
- 	.leds = {
- 		{
--			.name		= "adsl",
-+			.name		= "96358VW2:green:adsl",
- 			.gpio		= 22,
- 			.active_low	= 1,
- 		},
- 		{
--			.name		= "ppp-fail",
-+			.name		= "96358VW2:green:ppp-fail",
- 			.gpio		= 23,
- 		},
- 		{
--			.name		= "power",
-+			.name		= "96358VW2:green:power",
- 			.gpio		= 5,
- 			.active_low	= 1,
- 			.default_trigger = "default-on",
- 		},
- 		{
--			.name		= "stop",
-+			.name		= "96358VW2:green:stop",
- 			.gpio		= 4,
- 			.active_low	= 1,
- 		},
diff --git a/target/linux/brcm63xx/patches-3.3/401-MIPS-BCM63XX-register-ohci-device.patch b/target/linux/brcm63xx/patches-3.3/401-MIPS-BCM63XX-register-ohci-device.patch
index fc7040978840..57988788103c 100644
--- a/target/linux/brcm63xx/patches-3.3/401-MIPS-BCM63XX-register-ohci-device.patch
+++ b/target/linux/brcm63xx/patches-3.3/401-MIPS-BCM63XX-register-ohci-device.patch
@@ -50,9 +50,9 @@ Subject: [PATCH 24/63] MIPS: BCM63XX: register ohci device.
 +++ b/arch/mips/bcm63xx/Makefile
 @@ -1,6 +1,6 @@
  obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
- 		   dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-spi.o \
--		   dev-trng.o dev-uart.o dev-wdt.o
-+		   dev-trng.o dev-uart.o dev-usb-ohci.o dev-wdt.o
+ 		   dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \
+-		   dev-spi.o dev-uart.o dev-wdt.o
++		   dev-spi.o dev-uart.o dev-usb-ohci.o dev-wdt.o
  obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
  
  obj-y		+= boards/
@@ -66,7 +66,7 @@ Subject: [PATCH 24/63] MIPS: BCM63XX: register ohci device.
  #include <board_bcm963xx.h>
  #include <bcm_tag.h>
  
-@@ -912,6 +913,9 @@ int __init board_register_devices(void)
+@@ -914,6 +915,9 @@ int __init board_register_devices(void)
  	    !board_get_mac_address(board.enet1.mac_addr))
  		bcm63xx_enet_register(1, &board.enet1);
  
diff --git a/target/linux/brcm63xx/patches-3.3/403-MIPS-BCM63XX-register-ehci-device.patch b/target/linux/brcm63xx/patches-3.3/403-MIPS-BCM63XX-register-ehci-device.patch
index f182961e4667..36f6c2ee20d3 100644
--- a/target/linux/brcm63xx/patches-3.3/403-MIPS-BCM63XX-register-ehci-device.patch
+++ b/target/linux/brcm63xx/patches-3.3/403-MIPS-BCM63XX-register-ehci-device.patch
@@ -33,9 +33,9 @@ Subject: [PATCH 26/63] MIPS: BCM63XX: register ehci device.
 +++ b/arch/mips/bcm63xx/Makefile
 @@ -1,6 +1,6 @@
  obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
- 		   dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-spi.o \
--		   dev-trng.o dev-uart.o dev-usb-ohci.o dev-wdt.o
-+		   dev-trng.o dev-uart.o dev-usb-ehci.o dev-usb-ohci.o dev-wdt.o
+ 		   dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \
+-		   dev-spi.o dev-uart.o dev-usb-ohci.o dev-wdt.o
++		   dev-spi.o dev-uart.o dev-usb-ehci.o dev-usb-ohci.o dev-wdt.o
  obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
  
  obj-y		+= boards/
@@ -49,7 +49,7 @@ Subject: [PATCH 26/63] MIPS: BCM63XX: register ehci device.
  #include <board_bcm963xx.h>
  #include <bcm_tag.h>
  
-@@ -913,6 +914,9 @@ int __init board_register_devices(void)
+@@ -915,6 +916,9 @@ int __init board_register_devices(void)
  	    !board_get_mac_address(board.enet1.mac_addr))
  		bcm63xx_enet_register(1, &board.enet1);
  
diff --git a/target/linux/brcm63xx/patches-3.3/404-bcm963xx_flashmap.patch b/target/linux/brcm63xx/patches-3.3/404-bcm963xx_flashmap.patch
index 5b226006b1d4..8338962e5bd9 100644
--- a/target/linux/brcm63xx/patches-3.3/404-bcm963xx_flashmap.patch
+++ b/target/linux/brcm63xx/patches-3.3/404-bcm963xx_flashmap.patch
@@ -12,7 +12,7 @@ Signed-off-by: Axel Gembe <ago@bastart.eu.org>
 
 --- a/arch/mips/bcm63xx/dev-flash.c
 +++ b/arch/mips/bcm63xx/dev-flash.c
-@@ -29,7 +29,7 @@ static struct mtd_partition mtd_partitio
+@@ -30,7 +30,7 @@ static struct mtd_partition mtd_partitio
  	}
  };
  
diff --git a/target/linux/brcm63xx/patches-3.3/408-6358-enet1-external-mii-clk.patch b/target/linux/brcm63xx/patches-3.3/408-6358-enet1-external-mii-clk.patch
index e504552f3dff..708e988b119b 100644
--- a/target/linux/brcm63xx/patches-3.3/408-6358-enet1-external-mii-clk.patch
+++ b/target/linux/brcm63xx/patches-3.3/408-6358-enet1-external-mii-clk.patch
@@ -1,6 +1,6 @@
 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -851,6 +851,8 @@ void __init board_prom_init(void)
+@@ -853,6 +853,8 @@ void __init board_prom_init(void)
  		if (BCMCPU_IS_6348())
  			val |= GPIO_MODE_6348_G3_EXT_MII |
  				GPIO_MODE_6348_G0_EXT_MII;
diff --git a/target/linux/brcm63xx/patches-3.3/414-bcm63xx_enet-split-dma-registers-access.patch b/target/linux/brcm63xx/patches-3.3/414-bcm63xx_enet-split-dma-registers-access.patch
index 512f53f9f00c..280cd01d25ba 100644
--- a/target/linux/brcm63xx/patches-3.3/414-bcm63xx_enet-split-dma-registers-access.patch
+++ b/target/linux/brcm63xx/patches-3.3/414-bcm63xx_enet-split-dma-registers-access.patch
@@ -50,7 +50,7 @@ Subject: [PATCH 30/63] bcm63xx_enet: split dma registers access.
  		if (ret)
 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -156,7 +156,9 @@ enum bcm63xx_regs_set {
+@@ -157,7 +157,9 @@ enum bcm63xx_regs_set {
  #define BCM_6358_RSET_SPI_SIZE		1804
  #define BCM_6368_RSET_SPI_SIZE		1804
  #define RSET_ENET_SIZE			2048
@@ -60,7 +60,7 @@ Subject: [PATCH 30/63] bcm63xx_enet: split dma registers access.
 +#define RSET_ENETDMAS_SIZE(chans)	(16 * (chans))
  #define RSET_ENETSW_SIZE		65536
  #define RSET_UART_SIZE			24
- #define RSET_UDC_SIZE			256
+ #define RSET_HSSPI_SIZE			1536
 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
 +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
 @@ -41,8 +41,8 @@ static int copybreak __read_mostly = 128
diff --git a/target/linux/brcm63xx/patches-3.3/415-bcm63xx_enet-add-support-for-bcm6368-internal-ethern.patch b/target/linux/brcm63xx/patches-3.3/415-bcm63xx_enet-add-support-for-bcm6368-internal-ethern.patch
index d6dbaa0bfa7b..7ed32cfe54d4 100644
--- a/target/linux/brcm63xx/patches-3.3/415-bcm63xx_enet-add-support-for-bcm6368-internal-ethern.patch
+++ b/target/linux/brcm63xx/patches-3.3/415-bcm63xx_enet-add-support-for-bcm6368-internal-ethern.patch
@@ -13,7 +13,7 @@ Subject: [PATCH 31/63] bcm63xx_enet: add support for bcm6368 internal ethernet s
 
 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -916,6 +916,10 @@ int __init board_register_devices(void)
+@@ -918,6 +918,10 @@ int __init board_register_devices(void)
  	    !board_get_mac_address(board.enet1.mac_addr))
  		bcm63xx_enet_register(1, &board.enet1);
  
diff --git a/target/linux/brcm63xx/patches-3.3/418-MIPS-BCM63XX-add-HS-SPI-platform-device-and-register.patch b/target/linux/brcm63xx/patches-3.3/418-MIPS-BCM63XX-add-HS-SPI-platform-device-and-register.patch
index a1f43bed2493..dd58c335c833 100644
--- a/target/linux/brcm63xx/patches-3.3/418-MIPS-BCM63XX-add-HS-SPI-platform-device-and-register.patch
+++ b/target/linux/brcm63xx/patches-3.3/418-MIPS-BCM63XX-add-HS-SPI-platform-device-and-register.patch
@@ -1,16 +1,15 @@
-From a2b75f344cdc0f9e12c7909511d95b27be72c6b9 Mon Sep 17 00:00:00 2001
+From 56be5a2d7e08faa7bb306faaf352ac4e6ac52c01 Mon Sep 17 00:00:00 2001
 From: Jonas Gorski <jonas.gorski@gmail.com>
 Date: Sat, 12 Nov 2011 12:18:26 +0100
-Subject: [PATCH 52/79] MIPS: BCM63XX: add HS SPI platform device and register
- it
+Subject: [PATCH 26/60] MIPS: BCM63XX: add HS SPI platform device and register it
 
 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 ---
  arch/mips/bcm63xx/Makefile                         |    5 +-
  arch/mips/bcm63xx/boards/board_bcm963xx.c          |    2 +
- arch/mips/bcm63xx/dev-hsspi.c                      |   58 ++++++++++++++++++++
- .../include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h   |   26 +++++++++
- 4 files changed, 89 insertions(+), 2 deletions(-)
+ arch/mips/bcm63xx/dev-hsspi.c                      |   57 ++++++++++++++++++++
+ .../include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h   |   20 +++++++
+ 4 files changed, 82 insertions(+), 2 deletions(-)
  create mode 100644 arch/mips/bcm63xx/dev-hsspi.c
  create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
 
@@ -18,10 +17,10 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +++ b/arch/mips/bcm63xx/Makefile
 @@ -1,6 +1,7 @@
  obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
--		   dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-spi.o \
--		   dev-trng.o dev-uart.o dev-usb-ehci.o dev-usb-ohci.o dev-wdt.o
+-		   dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \
+-		   dev-spi.o dev-uart.o dev-usb-ehci.o dev-usb-ohci.o dev-wdt.o
 +		   dev-dsp.o dev-enet.o dev-flash.o dev-hsspi.o dev-pcmcia.o \
-+		   dev-spi.o dev-trng.o dev-uart.o dev-usb-ehci.o \
++		   dev-rng.o dev-spi.o dev-uart.o dev-usb-ehci.o \
 +		   dev-usb-ohci.o dev-wdt.o
  obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
  
@@ -36,7 +35,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  #include <bcm63xx_dev_pcmcia.h>
  #include <bcm63xx_dev_spi.h>
  #include <bcm63xx_dev_usb_ohci.h>
-@@ -941,6 +942,7 @@ int __init board_register_devices(void)
+@@ -943,6 +944,7 @@ int __init board_register_devices(void)
  			pr_err(PFX "failed to register fallback SPROM\n");
  	}
  #endif
@@ -46,14 +45,13 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  
 --- /dev/null
 +++ b/arch/mips/bcm63xx/dev-hsspi.c
-@@ -0,0 +1,58 @@
+@@ -0,0 +1,57 @@
 +/*
 + * This file is subject to the terms and conditions of the GNU General Public
 + * License.  See the file "COPYING" in the main directory of this archive
 + * for more details.
 + *
-+ * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
-+ * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
++ * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
 + */
 +
 +#include <linux/init.h>
@@ -107,7 +105,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +}
 --- /dev/null
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
-@@ -0,0 +1,26 @@
+@@ -0,0 +1,20 @@
 +#ifndef BCM63XX_DEV_HSSPI_H
 +#define BCM63XX_DEV_HSSPI_H
 +
@@ -127,10 +125,4 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +
 +#define HSSPI_PLL_HZ_6328	133333333
 +
-+#define HSSPI_OP_CODE_SHIFT	13
-+#define HSSPI_OP_SLEEP		(0 << HSSPI_OP_CODE_SHIFT)
-+#define HSSPI_OP_READ_WRITE	(1 << HSSPI_OP_CODE_SHIFT)
-+#define HSSPI_OP_WRITE		(2 << HSSPI_OP_CODE_SHIFT)
-+#define HSSPI_OP_READ		(3 << HSSPI_OP_CODE_SHIFT)
-+
 +#endif /* BCM63XX_DEV_HSSPI_H */
diff --git a/target/linux/brcm63xx/patches-3.3/419-SPI-MIPS-BCM63XX-Add-HS-SPI-driver.patch b/target/linux/brcm63xx/patches-3.3/419-SPI-MIPS-BCM63XX-Add-HS-SPI-driver.patch
index 44e69587387a..739c2c60f7c7 100644
--- a/target/linux/brcm63xx/patches-3.3/419-SPI-MIPS-BCM63XX-Add-HS-SPI-driver.patch
+++ b/target/linux/brcm63xx/patches-3.3/419-SPI-MIPS-BCM63XX-Add-HS-SPI-driver.patch
@@ -1,231 +1,28 @@
-From 2982127b8a0127667cb5354e03987cd3baa84b8c Mon Sep 17 00:00:00 2001
+From 4b27423676485d05bcd6fc6f3809164fb8f9d22d Mon Sep 17 00:00:00 2001
 From: Jonas Gorski <jonas.gorski@gmail.com>
 Date: Sat, 12 Nov 2011 12:19:55 +0100
-Subject: [PATCH 54/79] SPI: MIPS: BCM63XX: Add HS SPI driver
+Subject: [PATCH 30/60] SPI: MIPS: BCM63XX: Add HSSPI driver
 
 Add a driver for the High Speed SPI controller found on newer BCM63XX SoCs.
 
 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 ---
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h   |   18 +
- .../include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h   |    3 +
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h  |   47 ++
+ .../include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h   |    2 +
  drivers/spi/Kconfig                                |    7 +
  drivers/spi/Makefile                               |    1 +
- drivers/spi/spi-bcm63xx-hsspi.c                    |  502 ++++++++++++++++++++
- 6 files changed, 578 insertions(+)
+ drivers/spi/spi-bcm63xx-hsspi.c                    |  427 ++++++++++++++++++++
+ 4 files changed, 437 insertions(+), 0 deletions(-)
  create mode 100644 drivers/spi/spi-bcm63xx-hsspi.c
 
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -116,6 +116,7 @@ enum bcm63xx_regs_set {
- 	RSET_UART1,
- 	RSET_GPIO,
- 	RSET_SPI,
-+	RSET_HSSPI,
- 	RSET_UDC0,
- 	RSET_OHCI0,
- 	RSET_OHCI_PRIV,
-@@ -161,6 +162,7 @@ enum bcm63xx_regs_set {
- #define RSET_ENETDMAS_SIZE(chans)	(16 * (chans))
- #define RSET_ENETSW_SIZE		65536
- #define RSET_UART_SIZE			24
-+#define RSET_HSSPI_SIZE			2048
- #define RSET_UDC_SIZE			256
- #define RSET_OHCI_SIZE			256
- #define RSET_EHCI_SIZE			256
-@@ -184,6 +186,7 @@ enum bcm63xx_regs_set {
- #define BCM_6328_UART1_BASE		(0xb0000120)
- #define BCM_6328_GPIO_BASE		(0xb0000080)
- #define BCM_6328_SPI_BASE		(0xdeadbeef)
-+#define BCM_6328_HSSPI_BASE		(0xb0001000)
- #define BCM_6328_UDC0_BASE		(0xdeadbeef)
- #define BCM_6328_USBDMA_BASE		(0xdeadbeef)
- #define BCM_6328_OHCI0_BASE		(0xdeadbeef)
-@@ -229,6 +232,7 @@ enum bcm63xx_regs_set {
- #define BCM_6338_UART1_BASE		(0xdeadbeef)
- #define BCM_6338_GPIO_BASE		(0xfffe0400)
- #define BCM_6338_SPI_BASE		(0xfffe0c00)
-+#define BCM_6338_HSSPI_BASE		(0xdeadbeef)
- #define BCM_6338_UDC0_BASE		(0xdeadbeef)
- #define BCM_6338_USBDMA_BASE		(0xfffe2400)
- #define BCM_6338_OHCI0_BASE		(0xdeadbeef)
-@@ -275,6 +279,7 @@ enum bcm63xx_regs_set {
- #define BCM_6345_UART1_BASE		(0xdeadbeef)
- #define BCM_6345_GPIO_BASE		(0xfffe0400)
- #define BCM_6345_SPI_BASE		(0xdeadbeef)
-+#define BCM_6345_HSSPI_BASE		(0xdeadbeef)
- #define BCM_6345_UDC0_BASE		(0xdeadbeef)
- #define BCM_6345_USBDMA_BASE		(0xfffe2800)
- #define BCM_6345_ENET0_BASE		(0xfffe1800)
-@@ -320,6 +325,7 @@ enum bcm63xx_regs_set {
- #define BCM_6348_UART1_BASE		(0xdeadbeef)
- #define BCM_6348_GPIO_BASE		(0xfffe0400)
- #define BCM_6348_SPI_BASE		(0xfffe0c00)
-+#define BCM_6348_HSSPI_BASE		(0xdeadbeef)
- #define BCM_6348_UDC0_BASE		(0xfffe1000)
- #define BCM_6348_OHCI0_BASE		(0xfffe1b00)
- #define BCM_6348_OHCI_PRIV_BASE		(0xfffe1c00)
-@@ -363,6 +369,7 @@ enum bcm63xx_regs_set {
- #define BCM_6358_UART1_BASE		(0xfffe0120)
- #define BCM_6358_GPIO_BASE		(0xfffe0080)
- #define BCM_6358_SPI_BASE		(0xfffe0800)
-+#define BCM_6358_HSSPI_BASE		(0xdeadbeef)
- #define BCM_6358_UDC0_BASE		(0xfffe0800)
- #define BCM_6358_OHCI0_BASE		(0xfffe1400)
- #define BCM_6358_OHCI_PRIV_BASE		(0xdeadbeef)
-@@ -407,6 +414,7 @@ enum bcm63xx_regs_set {
- #define BCM_6368_UART1_BASE		(0xb0000120)
- #define BCM_6368_GPIO_BASE		(0xb0000080)
- #define BCM_6368_SPI_BASE		(0xb0000800)
-+#define BCM_6368_HSSPI_BASE		(0xdeadbeef)
- #define BCM_6368_UDC0_BASE		(0xdeadbeef)
- #define BCM_6368_OHCI0_BASE		(0xb0001600)
- #define BCM_6368_OHCI_PRIV_BASE		(0xdeadbeef)
-@@ -456,6 +464,7 @@ extern const unsigned long *bcm63xx_regs
- 	__GEN_RSET_BASE(__cpu, UART1)					\
- 	__GEN_RSET_BASE(__cpu, GPIO)					\
- 	__GEN_RSET_BASE(__cpu, SPI)					\
-+	__GEN_RSET_BASE(__cpu, HSSPI)					\
- 	__GEN_RSET_BASE(__cpu, UDC0)					\
- 	__GEN_RSET_BASE(__cpu, OHCI0)					\
- 	__GEN_RSET_BASE(__cpu, OHCI_PRIV)				\
-@@ -497,6 +506,7 @@ extern const unsigned long *bcm63xx_regs
- 	[RSET_UART1]		= BCM_## __cpu ##_UART1_BASE,		\
- 	[RSET_GPIO]		= BCM_## __cpu ##_GPIO_BASE,		\
- 	[RSET_SPI]		= BCM_## __cpu ##_SPI_BASE,		\
-+	[RSET_HSSPI]		= BCM_## __cpu ##_HSSPI_BASE,		\
- 	[RSET_UDC0]		= BCM_## __cpu ##_UDC0_BASE,		\
- 	[RSET_OHCI0]		= BCM_## __cpu ##_OHCI0_BASE,		\
- 	[RSET_OHCI_PRIV]	= BCM_## __cpu ##_OHCI_PRIV_BASE,	\
-@@ -569,6 +579,7 @@ enum bcm63xx_irq {
- 	IRQ_ENET0,
- 	IRQ_ENET1,
- 	IRQ_ENET_PHY,
-+	IRQ_HSSPI,
- 	IRQ_OHCI0,
- 	IRQ_EHCI0,
- 	IRQ_ENET0_RXDMA,
-@@ -604,6 +615,7 @@ enum bcm63xx_irq {
- #define BCM_6328_ENET0_IRQ		0
- #define BCM_6328_ENET1_IRQ		0
- #define BCM_6328_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
-+#define BCM_6328_HSSPI_IRQ		(IRQ_INTERNAL_BASE + 29)
- #define BCM_6328_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 9)
- #define BCM_6328_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
- #define BCM_6328_PCMCIA_IRQ		0
-@@ -642,6 +654,7 @@ enum bcm63xx_irq {
- #define BCM_6338_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
- #define BCM_6338_ENET1_IRQ		0
- #define BCM_6338_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
-+#define BCM_6338_HSSPI_IRQ		0
- #define BCM_6338_OHCI0_IRQ		0
- #define BCM_6338_EHCI0_IRQ		0
- #define BCM_6338_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
-@@ -673,6 +686,7 @@ enum bcm63xx_irq {
- #define BCM_6345_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
- #define BCM_6345_ENET1_IRQ		0
- #define BCM_6345_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
-+#define BCM_6345_HSSPI_IRQ		0
- #define BCM_6345_OHCI0_IRQ		0
- #define BCM_6345_EHCI0_IRQ		0
- #define BCM_6345_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 1)
-@@ -704,6 +718,7 @@ enum bcm63xx_irq {
- #define BCM_6348_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
- #define BCM_6348_ENET1_IRQ		(IRQ_INTERNAL_BASE + 7)
- #define BCM_6348_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
-+#define BCM_6348_HSSPI_IRQ		0
- #define BCM_6348_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 12)
- #define BCM_6348_EHCI0_IRQ		0
- #define BCM_6348_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 20)
-@@ -735,6 +750,7 @@ enum bcm63xx_irq {
- #define BCM_6358_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
- #define BCM_6358_ENET1_IRQ		(IRQ_INTERNAL_BASE + 6)
- #define BCM_6358_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
-+#define BCM_6358_HSSPI_IRQ		0
- #define BCM_6358_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
- #define BCM_6358_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
- #define BCM_6358_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
-@@ -775,6 +791,7 @@ enum bcm63xx_irq {
- #define BCM_6368_ENET0_IRQ		0
- #define BCM_6368_ENET1_IRQ		0
- #define BCM_6368_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 15)
-+#define BCM_6368_HSSPI_IRQ		0
- #define BCM_6368_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
- #define BCM_6368_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 7)
- #define BCM_6368_PCMCIA_IRQ		0
-@@ -815,6 +832,7 @@ extern const int *bcm63xx_irqs;
- 	[IRQ_ENET0]		= BCM_## __cpu ##_ENET0_IRQ,		\
- 	[IRQ_ENET1]		= BCM_## __cpu ##_ENET1_IRQ,		\
- 	[IRQ_ENET_PHY]		= BCM_## __cpu ##_ENET_PHY_IRQ,		\
-+	[IRQ_HSSPI]		= BCM_## __cpu ##_HSSPI_IRQ,		\
- 	[IRQ_OHCI0]		= BCM_## __cpu ##_OHCI0_IRQ,		\
- 	[IRQ_EHCI0]		= BCM_## __cpu ##_EHCI0_IRQ,		\
- 	[IRQ_ENET0_RXDMA]	= BCM_## __cpu ##_ENET0_RXDMA_IRQ,	\
 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
-@@ -23,4 +23,7 @@ struct bcm63xx_hsspi_pdata {
- #define HSSPI_OP_WRITE		(2 << HSSPI_OP_CODE_SHIFT)
- #define HSSPI_OP_READ		(3 << HSSPI_OP_CODE_SHIFT)
+@@ -17,4 +17,6 @@ struct bcm63xx_hsspi_pdata {
  
-+#define HS_SPI_CLOCK_DEF    40000000
-+#define HS_SPI_BUFFER_LEN   512
-+
- #endif /* BCM63XX_DEV_HSSPI_H */
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1283,4 +1283,51 @@
- 
- #define PCIE_DEVICE_OFFSET		0x8000
+ #define HSSPI_PLL_HZ_6328	133333333
  
-+/*************************************************************************
-+ * _REG relative to RSET_HSSPI
-+ *************************************************************************/
-+
-+#define HSSPI_GLOBAL_CTRL_REG			0x0
-+#define GLOBAL_CTRL_CLK_POLARITY		BIT(17)
-+#define GLOBAL_CTRL_CLK_GATE_SSOFF		BIT(16)
-+
-+#define HSSPI_GLOBAL_EXT_TRIGGER_REG		0x4
-+
-+#define HSSPI_INT_STATUS_REG			0x8
-+#define HSSPI_INT_STATUS_MASKED_REG		0xc
-+#define HSSPI_INT_MASK_REG			0x10
-+
-+#define HSSPI_PING0_CMD_DONE			BIT(0)
-+
-+#define HSSPI_INT_CLEAR_ALL			0xff001f1f
-+
-+#define HSSPI_PINGPONG_COMMAND_REG(x)		(0x80 + (x) * 0x40)
-+#define PINGPONG_CMD_COMMAND_MASK		0xf
-+#define PINGPONG_COMMAND_NOOP			0
-+#define PINGPONG_COMMAND_START_NOW		1
-+#define PINGPONG_COMMAND_START_TRIGGER		2
-+#define PINGPONG_COMMAND_HALT			3
-+#define PINGPONG_COMMAND_FLUSH			4
-+#define PINGPONG_CMD_PROFILE_SHIFT		8
-+#define PINGPONG_CMD_SS_SHIFT			12
++#define HSSPI_BUFFER_LEN   	512
 +
-+#define HSSPI_PINGPONG_STATUS_REG(x)		(0x84 + (x) * 0x40)
-+
-+#define HSSPI_PROFILE_CLK_CTRL_REG(x)		(0x100 + (x) * 0x20)
-+#define CLK_CTRL_ACCUM_RST_ON_LOOP		BIT(15)
-+
-+#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x)	(0x104 + (x) * 0x20)
-+#define SIGNAL_CTRL_LATCH_RISING		BIT(12)
-+#define SIGNAL_CTRL_LAUNCH_RISING		BIT(13)
-+#define SIGNAL_CTRL_ASYNC_INPUT_PATH		BIT(16)
-+
-+#define HSSPI_PROFILE_MODE_CTRL_REG(x)		(0x108 + (x) * 0x20)
-+#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT	8
-+#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT	12
-+#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT	16
-+#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT	18
-+#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT		24
-+
-+#define HSSPI_FIFO_REG(x)			(0x200 + (x) * 0x200)
-+
- #endif /* BCM63XX_REGS_H_ */
+ #endif /* BCM63XX_DEV_HSSPI_H */
 --- a/drivers/spi/Kconfig
 +++ b/drivers/spi/Kconfig
 @@ -100,6 +100,13 @@ config SPI_BCM63XX
@@ -254,18 +51,19 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  obj-$(CONFIG_SPI_BITBANG)		+= spi-bitbang.o
 --- /dev/null
 +++ b/drivers/spi/spi-bcm63xx-hsspi.c
-@@ -0,0 +1,502 @@
+@@ -0,0 +1,427 @@
 +/*
 + * Broadcom BCM63XX High Speed SPI Controller driver
 + *
 + * Copyright 2000-2010 Broadcom Corporation
-+ * Copyright 2011 Jonas Gorski <jonas.gorski@gmail.com>
++ * Copyright 2012 Jonas Gorski <jonas.gorski@gmail.com>
 + *
 + * Licensed under the GNU/GPL. See COPYING for details.
 + */
 +
 +#include <linux/kernel.h>
 +#include <linux/init.h>
++#include <linux/io.h>
 +#include <linux/clk.h>
 +#include <linux/module.h>
 +#include <linux/platform_device.h>
@@ -279,49 +77,44 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +#include <bcm63xx_regs.h>
 +#include <bcm63xx_dev_hsspi.h>
 +
++#define HSSPI_OP_CODE_SHIFT	13
++#define HSSPI_OP_SLEEP		(0 << HSSPI_OP_CODE_SHIFT)
++#define HSSPI_OP_READ_WRITE	(1 << HSSPI_OP_CODE_SHIFT)
++#define HSSPI_OP_WRITE		(2 << HSSPI_OP_CODE_SHIFT)
++#define HSSPI_OP_READ		(3 << HSSPI_OP_CODE_SHIFT)
 +
-+#define PFX		KBUILD_MODNAME
++#define HSSPI_MAX_PREPEND_LEN	15
 +
-+struct bcm63xx_hsspi {
-+	spinlock_t		lock;
-+	int			irq;
-+	u8			stopping;
++#define HSSPI_MAX_SYNC_CLOCK	30000000
 +
-+	struct list_head	queue;
-+	struct workqueue_struct	*workqueue;
-+	struct work_struct	ws;
++struct bcm63xx_hsspi {
 +	struct completion	done;
-+
 +	struct spi_transfer	*curr_trans;
 +
 +	struct platform_device  *pdev;
-+	void __iomem		*regs;
 +	struct clk		*clk;
-+
-+	/* Platform data */
-+	u32			speed_hz;
-+
-+	/* data iomem */
++	void __iomem		*regs;
 +	u8 __iomem		*fifo;
 +
-+
++	u32			speed_hz;
++	int			irq;
 +};
 +
 +static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, int hz,
 +				  int profile)
 +{
-+	int clock;
-+
-+	clock = bs->speed_hz / hz;
-+	if (bs->speed_hz % HS_SPI_CLOCK_DEF)
-+		clock++;
-+
-+	clock = 2048 / clock;
-+	if (2048 % clock)
-+		clock++;
++	u32 reg;
 +
-+	bcm_hsspi_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | clock,
++	reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
++	bcm_hsspi_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
 +			 HSSPI_PROFILE_CLK_CTRL_REG(profile));
++
++	reg = bcm_hsspi_readl(HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
++	if (hz > HSSPI_MAX_SYNC_CLOCK)
++		reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
++	else
++		reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
++	bcm_hsspi_writel(reg, HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
 +}
 +
 +static int bcm63xx_hsspi_do_txrx(struct spi_device *spi,
@@ -331,20 +124,19 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
 +	u8 chip_select = spi->chip_select;
 +	u16 opcode = 0;
-+	int prepend_size = 0;
++	int len, prepend_size = 0;
 +
 +	init_completion(&bs->done);
++
 +	bs->curr_trans = t2 ? t2 : t1;
 +	bcm63xx_hsspi_set_clk(bs, bs->curr_trans->speed_hz, chip_select);
 +
-+	BUG_ON(t2 && !t1->tx_buf && t1->rx_buf && t2->tx_buf && !t2->rx_buf);
-+
 +	if (t2 && !t2->tx_buf)
 +		prepend_size = t1->len;
 +
-+	bcm_hsspi_writel(prepend_size<<MODE_CTRL_PREPENDBYTE_CNT_SHIFT |
-+			 2<<MODE_CTRL_MULTIDATA_WR_STRT_SHIFT |
-+			 2<<MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff,
++	bcm_hsspi_writel(prepend_size << MODE_CTRL_PREPENDBYTE_CNT_SHIFT |
++			 2 << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT |
++			 2 << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff,
 +			 HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
 +
 +	if (t1->rx_buf && t1->tx_buf)
@@ -354,22 +146,21 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +	else if (t1->tx_buf)
 +		opcode = HSSPI_OP_WRITE;
 +
-+	BUG_ON(opcode == 0);
-+
 +	if (opcode == HSSPI_OP_READ && t2)
-+		opcode |= t2->len;
++		len = t2->len;
 +	else
-+		opcode |= t1->len;
++		len = t1->len;
 +
 +	if (t1->tx_buf) {
 +		memcpy_toio(bs->fifo + 2, t1->tx_buf, t1->len);
 +		if (t2 && t2->tx_buf) {
 +			memcpy_toio(bs->fifo + 2 + t1->len,
 +				    t2->tx_buf, t2->len);
-+			opcode += t2->len;
++			len += t2->len;
 +		}
 +	}
 +
++	opcode |= len;
 +	memcpy_toio(bs->fifo, &opcode, sizeof(opcode));
 +
 +	/* enable interrupt */
@@ -381,20 +172,17 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +			 PINGPONG_COMMAND_START_NOW,
 +			 HSSPI_PINGPONG_COMMAND_REG(0));
 +
-+	wait_for_completion(&bs->done);
++	if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
++		dev_err(&bs->pdev->dev, "transfer timed out!\n");
++		return -ETIMEDOUT;
++	}
++
 +	return t1->len + (t2 ? t2->len : 0);
 +}
++
 +static int bcm63xx_hsspi_setup(struct spi_device *spi)
 +{
-+	struct bcm63xx_hsspi *bs;
 +	u32 reg;
-+	bs = spi_master_get_devdata(spi->master);
-+
-+	if (bs->stopping)
-+		return -ESHUTDOWN;
-+
-+	if (!spi->bits_per_word)
-+		spi->bits_per_word = 8;
 +
 +	if (spi->bits_per_word != 8)
 +		return -EINVAL;
@@ -404,133 +192,109 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +
 +	reg = bcm_hsspi_readl(HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
 +	reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
-+
 +	if (spi->mode & SPI_CPHA)
 +		reg |= SIGNAL_CTRL_LAUNCH_RISING;
 +	else
 +		reg |= SIGNAL_CTRL_LATCH_RISING;
-+
 +	bcm_hsspi_writel(reg, HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
 +
 +	return 0;
 +}
 +
-+
-+static int bcm63xx_hsspi_transfer(struct spi_device *spi,
-+				  struct spi_message *msg)
++static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
++				      struct spi_message *msg)
 +{
-+	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
 +	struct spi_transfer *t, *prev = NULL;
++	struct spi_device *spi = msg->spi;
++	u32 reg;
++	int ret = -EINVAL;
++	int len = 0;
 +
-+	if (unlikely(list_empty(&msg->transfers)))
-+		return -EINVAL;
-+
-+	if (bs->stopping)
-+		return -ESHUTDOWN;
-+
-+	list_for_each_entry(t, &msg->transfers, transfer_list)	{
-+		/* check transfer parameters */
++	/* check if we are able to make these transfers */
++	list_for_each_entry(t, &msg->transfers, transfer_list) {
 +		if (!t->tx_buf && !t->rx_buf)
-+			return -EINVAL;
++			goto out;
 +
 +		if (t->speed_hz == 0)
 +			t->speed_hz = spi->max_speed_hz;
 +
 +		if (t->speed_hz > spi->max_speed_hz)
-+			return -EINVAL;
++			goto out;
 +
-+		if (t->len > HS_SPI_BUFFER_LEN)
-+			return -EINVAL;
++		if (t->len > HSSPI_BUFFER_LEN)
++			goto out;
 +
-+		/* reject if we have to combine two tx transfers and their
-+		 * combined length is bigger than the buffer
++		/*
++		 * This controller does not support keeping the chip select
++		 * active between transfers.
++		 * This logic currently supports combining:
++		 *  write then read with no cs_change (e.g. m25p80 RDSR)
++		 *  write then write with no cs_change (e.g. m25p80 PP)
 +		 */
-+		if (prev && !prev->cs_change && !t->cs_change && prev->tx_buf &&
-+		    t->tx_buf && (prev->len + t->len) > HS_SPI_BUFFER_LEN)
-+			return -EINVAL;
-+
-+		prev = t;
-+	}
-+
-+
-+	msg->actual_length = 0;
-+
-+#if 0
-+	/* disable interrupts for the SPI controller
-+	   using spin_lock_irqsave would disable all interrupts */
-+	bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
-+#endif
-+	spin_lock(&bs->lock);
-+	list_add_tail(&msg->queue, &bs->queue);
-+	queue_work(bs->workqueue, &bs->ws);
-+	spin_unlock(&bs->lock);
-+
-+#if 0
-+	bcm_hsspi_writel(HSSPI_PING0_CMD_DONE, HSSPI_INT_MASK_REG);
-+#endif
-+	return 0;
-+}
-+
-+static void bcm63xx_hsspi_do_work(struct work_struct *work)
-+{
-+	struct bcm63xx_hsspi *bs = container_of(work, struct bcm63xx_hsspi,
-+						ws);
-+	struct spi_message *msg;
-+	struct spi_transfer *prev = NULL;
-+	struct spi_transfer *t;
-+	u32 reg;
-+
-+	int len = 0;
-+
-+	spin_lock(&bs->lock);
-+	msg = list_entry(bs->queue.next, struct spi_message, queue);
-+	list_del(&msg->queue);
-+	spin_unlock(&bs->lock);
++		if (prev && prev->tx_buf && !prev->cs_change && !t->cs_change) {
++			/*
++			 * reject if we have to combine two tx transfers and
++			 * their combined length is bigger than the buffer
++			 */
++			if (prev->tx_buf && t->tx_buf &&
++			    (prev->len + t->len) > HSSPI_BUFFER_LEN)
++				goto out;
++			/*
++			 * reject if we need write more than 15 bytes in read
++			 * then write.
++			 */
++			if (prev->tx_buf && t->rx_buf &&
++			    prev->len > HSSPI_MAX_PREPEND_LEN)
++				goto out;
++		}
 +
-+	if (bs->stopping) {
-+		msg->status = -ESHUTDOWN;
-+		goto out;
 +	}
 +
 +	/* setup clock polarity */
 +	reg = bcm_hsspi_readl(HSSPI_GLOBAL_CTRL_REG);
 +	reg &= ~GLOBAL_CTRL_CLK_POLARITY;
-+
-+	if (msg->spi->mode & SPI_CPOL)
++	if (spi->mode & SPI_CPOL)
 +		reg |= GLOBAL_CTRL_CLK_POLARITY;
-+
 +	bcm_hsspi_writel(reg, HSSPI_GLOBAL_CTRL_REG);
 +
 +	list_for_each_entry(t, &msg->transfers, transfer_list) {
-+		/*
-+		 * This controller does not support keeping the chip select
-+		 * active between transfers.
-+		 * This logic currently supports combining:
-+		 *  write then read with no cs_change (e.g. m25p80 RDSR)
-+		 *  write then write with no cs_change (e.g. m25p80 PP)
-+		 */
 +		if (prev && prev->tx_buf && !prev->cs_change && !t->cs_change) {
 +			/* combine write with following transfer */
-+			len += bcm63xx_hsspi_do_txrx(msg->spi, prev, t);
++			ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, t);
++			if (ret < 0)
++				goto out;
++
++			len += ret;
 +			prev = NULL;
 +			continue;
 +		}
 +
 +		/* write the previous pending transfer */
-+		if (prev != NULL)
-+			len += bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
++		if (prev != NULL) {
++			ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
++			if (ret < 0)
++				goto out;
++
++			len += ret;
++		}
 +
 +		prev = t;
 +	}
 +
 +	/* do last pending transfer */
-+	if (prev != NULL)
-+		len += bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
++	if (prev != NULL) {
++		ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
++		if (ret < 0)
++			goto out;
++		len += ret;
++	}
 +
-+	msg->status = 0;
 +	msg->actual_length = len;
++	ret = 0;
 +out:
-+	msg->complete(msg->context);
++	msg->status = ret;
++	spi_finalize_current_message(master);
++	return 0;
 +}
 +
 +static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
@@ -544,55 +308,48 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +	bcm_hsspi_writel(HSSPI_INT_CLEAR_ALL, HSSPI_INT_STATUS_REG);
 +	bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
 +
-+	spin_lock(&bs->lock);
-+
 +	if (bs->curr_trans && bs->curr_trans->rx_buf)
 +		memcpy_fromio(bs->curr_trans->rx_buf,  bs->fifo,
 +			      bs->curr_trans->len);
-+
 +	complete(&bs->done);
-+	spin_unlock(&bs->lock);
 +
 +	return IRQ_HANDLED;
 +}
 +
-+
-+static void bcm63xx_hsspi_cleanup(struct spi_device *spi)
-+{
-+	/* would free spi_controller memory here if any was allocated */
-+}
-+
 +static int __devinit bcm63xx_hsspi_probe(struct platform_device *pdev)
 +{
 +
 +	struct spi_master *master;
 +	struct bcm63xx_hsspi *bs;
 +	struct resource *res_mem;
++	void __iomem *regs;
 +	struct device *dev = &pdev->dev;
 +	struct bcm63xx_hsspi_pdata *pdata = pdev->dev.platform_data;
 +	struct clk *clk;
 +	int irq;
 +	int ret;
 +
-+	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!res_mem) {
-+		dev_err(dev, "no iomem\n");
-+		return -ENXIO;
-+	}
-+
 +	irq = platform_get_irq(pdev, 0);
 +	if (irq < 0) {
 +		dev_err(dev, "no irq\n");
 +		return -ENXIO;
 +	}
 +
++	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	regs = devm_request_and_ioremap(dev, res_mem);
++	if (!regs) {
++		dev_err(dev, "unable to ioremap regs\n");
++		return -ENXIO;
++	}
++
 +	clk = clk_get(dev, "hsspi");
 +
 +	if (IS_ERR(clk)) {
 +		ret = PTR_ERR(clk);
 +		goto out_release;
 +	}
-+	clk_enable(clk);
++
++	clk_prepare_enable(clk);
 +
 +	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
 +	if (!master) {
@@ -601,51 +358,38 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +	}
 +
 +	bs = spi_master_get_devdata(master);
-+	init_completion(&bs->done);
 +	bs->pdev = pdev;
 +	bs->clk = clk;
++	bs->regs = regs;
 +
-+	bs->regs = devm_request_and_ioremap(dev, res_mem);
-+	if (!bs->regs) {
-+		dev_err(dev, "unable to ioremap regs\n");
-+		ret = -ENOMEM;
-+		goto out_put_master;
-+	}
-+
-+	master->bus_num        = pdata->bus_num;
++	master->bus_num = pdata->bus_num;
 +	master->num_chipselect = 8;
-+	master->setup          = bcm63xx_hsspi_setup;
-+	master->transfer       = bcm63xx_hsspi_transfer;
-+	master->cleanup        = bcm63xx_hsspi_cleanup;
-+	master->mode_bits      = SPI_CPOL | SPI_CPHA;
++	master->setup = bcm63xx_hsspi_setup;
++	master->transfer_one_message = bcm63xx_hsspi_transfer_one;
++	master->mode_bits = SPI_CPOL | SPI_CPHA;
 +
 +	bs->speed_hz = pdata->speed_hz;
-+	bs->fifo = (u8 *)(bs->regs + HSSPI_FIFO_REG(0));
++	bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
 +
 +	platform_set_drvdata(pdev, master);
 +
-+	spin_lock_init(&bs->lock);
-+	INIT_LIST_HEAD(&bs->queue);
-+	INIT_WORK(&bs->ws, bcm63xx_hsspi_do_work);
-+	bs->workqueue = create_singlethread_workqueue(pdev->name);
 +	bs->curr_trans = NULL;
 +
 +	/* Initialize the hardware */
 +	bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
 +
++	/* clean up any pending interrupts */
++	bcm_hsspi_writel(HSSPI_INT_CLEAR_ALL, HSSPI_INT_STATUS_REG);
++
 +	bcm_hsspi_writel(bcm_hsspi_readl(HSSPI_GLOBAL_CTRL_REG) |
 +			 GLOBAL_CTRL_CLK_GATE_SSOFF,
 +			 HSSPI_GLOBAL_CTRL_REG);
 +
-+	ret = request_irq(irq, bcm63xx_hsspi_interrupt, IRQF_SHARED, pdev->name,
-+			  master);
++	ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
++			       pdev->name, master);
 +
 +	if (ret)
-+		goto out_destroy_workqueue;
-+
-+	spin_lock(&bs->lock);
-+	bs->irq = irq;
-+	spin_unlock(&bs->lock);
++		goto out_put_master;
 +
 +	/* register and we are done */
 +	ret = spi_register_master(master);
@@ -655,18 +399,14 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +	return 0;
 +
 +out_free_irq:
-+	free_irq(bs->irq, master);
-+out_destroy_workqueue:
-+	flush_workqueue(bs->workqueue);
-+	destroy_workqueue(bs->workqueue);
-+	iounmap(bs->regs);
++	devm_free_irq(dev, bs->irq, master);
 +out_put_master:
 +	spi_master_put(master);
 +out_disable_clk:
-+	clk_disable(clk);
++	clk_disable_unprepare(clk);
 +	clk_put(clk);
 +out_release:
-+	release_mem_region(res_mem->start, resource_size(res_mem));
++	devm_ioremap_release(dev, regs);
 +
 +	return ret;
 +}
@@ -676,34 +416,14 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +{
 +	struct spi_master *master = platform_get_drvdata(pdev);
 +	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
-+	struct spi_message *msg;
 +
-+	cancel_work_sync(&bs->ws);
++	spi_unregister_master(master);
 +
 +	/* reset the hardware and block queue progress */
 +	bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
-+
-+	spin_lock(&bs->lock);
-+	/* HW shutdown */
-+	bs->stopping = 1;
-+	spin_unlock(&bs->lock);
-+
-+
-+	/* Terminate remaining queued transfers */
-+	list_for_each_entry(msg, &bs->queue, queue) {
-+		msg->status = -ESHUTDOWN;
-+		msg->complete(msg->context);
-+	}
-+
-+
-+	free_irq(bs->irq, master);
-+	flush_workqueue(bs->workqueue);
-+	destroy_workqueue(bs->workqueue);
-+
-+	clk_disable(bs->clk);
++	clk_disable_unprepare(bs->clk);
 +	clk_put(bs->clk);
 +
-+	spi_unregister_master(master);
 +	return 0;
 +}
 +
@@ -711,9 +431,10 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +static int bcm63xx_hsspi_suspend(struct platform_device *pdev,
 +				 pm_message_t mesg)
 +{
-+	struct spi_master	*master = platform_get_drvdata(pdev);
-+	struct bcm63xx_hsspi	*bs = spi_master_get_devdata(master);
++	struct spi_master *master = platform_get_drvdata(pdev);
++	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 +
++	spi_master_suspend(master);
 +	clk_disable(bs->clk);
 +
 +	return 0;
@@ -721,10 +442,11 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 +
 +static int bcm63xx_hsspi_resume(struct platform_device *pdev)
 +{
-+	struct spi_master	*master = platform_get_drvdata(pdev);
-+	struct bcm63xx_hsspi	*bs = spi_master_get_devdata(master);
++	struct spi_master *master = platform_get_drvdata(pdev);
++	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 +
 +	clk_enable(bs->clk);
++	spi_master_resume(master);
 +
 +	return 0;
 +}
diff --git a/target/linux/brcm63xx/patches-3.3/420-MIPS-BCM63XX-Register-SPI-flash-if-present.patch b/target/linux/brcm63xx/patches-3.3/420-MIPS-BCM63XX-Register-SPI-flash-if-present.patch
index f83dbcffd7c4..49bbdf916b52 100644
--- a/target/linux/brcm63xx/patches-3.3/420-MIPS-BCM63XX-Register-SPI-flash-if-present.patch
+++ b/target/linux/brcm63xx/patches-3.3/420-MIPS-BCM63XX-Register-SPI-flash-if-present.patch
@@ -1,17 +1,17 @@
-From a1e3ef9af3e3a7283ced5fd079ef7e8bc4e2deca Mon Sep 17 00:00:00 2001
+From d135d94b3d1fe599d13e7198d5f502912d694c13 Mon Sep 17 00:00:00 2001
 From: Jonas Gorski <jonas.gorski@gmail.com>
 Date: Sun, 3 Jul 2011 15:00:38 +0200
-Subject: [PATCH 55/79] MIPS: BCM63XX: Register SPI flash if present
+Subject: [PATCH 29/60] MIPS: BCM63XX: Register SPI flash if present
 
 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 ---
- arch/mips/bcm63xx/dev-flash.c                     |   29 +++++++++++++++++++--
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    1 +
- 2 files changed, 28 insertions(+), 2 deletions(-)
+ arch/mips/bcm63xx/dev-flash.c                     |   33 +++++++++++++++++++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    2 +
+ 2 files changed, 33 insertions(+), 2 deletions(-)
 
 --- a/arch/mips/bcm63xx/dev-flash.c
 +++ b/arch/mips/bcm63xx/dev-flash.c
-@@ -15,9 +15,12 @@
+@@ -16,9 +16,12 @@
  #include <linux/mtd/mtd.h>
  #include <linux/mtd/partitions.h>
  #include <linux/mtd/physmap.h>
@@ -24,7 +24,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  #include <bcm63xx_regs.h>
  #include <bcm63xx_io.h>
  
-@@ -54,12 +57,28 @@ static struct platform_device mtd_dev =
+@@ -55,6 +58,21 @@ static struct platform_device mtd_dev =
  	},
  };
  
@@ -46,14 +46,19 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  static int __init bcm63xx_detect_flash_type(void)
  {
  	u32 val;
- 
+@@ -62,6 +80,11 @@ static int __init bcm63xx_detect_flash_t
  	switch (bcm63xx_get_cpu_id()) {
  	case BCM6328_CPU_ID:
-+		bcm63xx_spi_flash_info[0].max_speed_hz = 40000000;
  		val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
++		if (val & STRAPBUS_6328_HSSPI_CLK_FAST)
++			bcm63xx_spi_flash_info[0].max_speed_hz = 33333334;
++		else
++			bcm63xx_spi_flash_info[0].max_speed_hz = 16666667;
++
  		if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
  			return BCM63XX_FLASH_TYPE_SERIAL;
-@@ -78,6 +97,9 @@ static int __init bcm63xx_detect_flash_t
+ 		else
+@@ -79,6 +102,9 @@ static int __init bcm63xx_detect_flash_t
  			return BCM63XX_FLASH_TYPE_SERIAL;
  	case BCM6368_CPU_ID:
  		val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
@@ -63,14 +68,14 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  		switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
  		case STRAPBUS_6368_BOOT_SEL_NAND:
  			return BCM63XX_FLASH_TYPE_NAND;
-@@ -109,8 +131,11 @@ int __init bcm63xx_flash_register(void)
+@@ -110,8 +136,11 @@ int __init bcm63xx_flash_register(void)
  
  		return platform_device_register(&mtd_dev);
  	case BCM63XX_FLASH_TYPE_SERIAL:
 -		pr_warn("unsupported serial flash detected\n");
 -		return -ENODEV;
 +		if (BCMCPU_IS_6328())
-+			bcm63xx_flash_data.max_transfer_len = HS_SPI_BUFFER_LEN;
++			bcm63xx_flash_data.max_transfer_len = HSSPI_BUFFER_LEN;
 +
 +		return spi_register_board_info(bcm63xx_spi_flash_info,
 +					ARRAY_SIZE(bcm63xx_spi_flash_info));
@@ -87,3 +92,11 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  #define STRAPBUS_6368_BOOT_SEL_MASK	0x3
  #define STRAPBUS_6368_BOOT_SEL_NAND	0
  #define STRAPBUS_6368_BOOT_SEL_SERIAL	1
+@@ -1227,6 +1228,7 @@
+ #define SERDES_PCIE_EXD_EN		(1 << 15)
+ 
+ #define MISC_STRAPBUS_6328_REG		0x240
++#define STRAPBUS_6328_HSSPI_CLK_FAST	(1 << 4)
+ #define STRAPBUS_6328_FCVO_SHIFT	7
+ #define STRAPBUS_6328_FCVO_MASK		(0x1f << STRAPBUS_6328_FCVO_SHIFT)
+ #define STRAPBUS_6328_BOOT_SEL_SERIAL	(1 << 28)
diff --git a/target/linux/brcm63xx/patches-3.3/421-MIPS-BCM63XX-move-nvram-related-functions-into-their.patch b/target/linux/brcm63xx/patches-3.3/421-MIPS-BCM63XX-move-nvram-related-functions-into-their.patch
index 4afbe23cc815..db1891c948dc 100644
--- a/target/linux/brcm63xx/patches-3.3/421-MIPS-BCM63XX-move-nvram-related-functions-into-their.patch
+++ b/target/linux/brcm63xx/patches-3.3/421-MIPS-BCM63XX-move-nvram-related-functions-into-their.patch
@@ -20,10 +20,10 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
 @@ -1,6 +1,6 @@
 -obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
 -		   dev-dsp.o dev-enet.o dev-flash.o dev-hsspi.o dev-pcmcia.o \
--		   dev-spi.o dev-trng.o dev-uart.o dev-usb-ehci.o \
+-		   dev-rng.o dev-spi.o dev-uart.o dev-usb-ehci.o \
 +obj-y		+= clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o setup.o \
 +		   timer.o dev-dsp.o dev-enet.o dev-flash.o dev-hsspi.o \
-+		   dev-pcmcia.o dev-spi.o dev-trng.o dev-uart.o dev-usb-ehci.o \
++		   dev-pcmcia.o dev-rng.o dev-spi.o dev-uart.o dev-usb-ehci.o \
  		   dev-usb-ohci.o dev-wdt.o
  obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
  
@@ -125,7 +125,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  	u32 val;
  
  	/* read base address of boot chip select (0)
-@@ -783,32 +749,19 @@ void __init board_prom_init(void)
+@@ -784,32 +750,19 @@ void __init board_prom_init(void)
  		strcpy(cfe_version, "unknown");
  	printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
  
@@ -162,7 +162,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  			continue;
  		/* copy, board desc array is marked initdata */
  		memcpy(&board, bcm963xx_boards[i], sizeof(board));
-@@ -818,7 +771,7 @@ void __init board_prom_init(void)
+@@ -819,7 +772,7 @@ void __init board_prom_init(void)
  	/* bail out if board is not found, will complain later */
  	if (!board.name[0]) {
  		char name[17];
@@ -171,7 +171,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  		name[16] = 0;
  		printk(KERN_ERR PFX "unknown bcm963xx board: %s\n",
  		       name);
-@@ -910,15 +863,15 @@ int __init board_register_devices(void)
+@@ -912,15 +865,15 @@ int __init board_register_devices(void)
  		bcm63xx_pcmcia_register();
  
  	if (board.has_enet0 &&
@@ -190,7 +190,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  		bcm63xx_enetsw_register(&board.enetsw);
  
  	if (board.has_ehci0)
-@@ -934,7 +887,7 @@ int __init board_register_devices(void)
+@@ -936,7 +889,7 @@ int __init board_register_devices(void)
  	 * do this after registering enet devices
  	 */
  #ifdef CONFIG_SSB_PCIHOST
diff --git a/target/linux/brcm63xx/patches-3.3/425-BCM63XX-allow-providing-fixup-data-in-board-data.patch b/target/linux/brcm63xx/patches-3.3/425-BCM63XX-allow-providing-fixup-data-in-board-data.patch
index f0b1cbf21f3c..18e2aaa7a551 100644
--- a/target/linux/brcm63xx/patches-3.3/425-BCM63XX-allow-providing-fixup-data-in-board-data.patch
+++ b/target/linux/brcm63xx/patches-3.3/425-BCM63XX-allow-providing-fixup-data-in-board-data.patch
@@ -18,7 +18,7 @@ Subject: [PATCH 67/80] BCM63XX: allow providing fixup data in board data
  
  #define PFX	"board_bcm963xx: "
  
-@@ -852,6 +853,7 @@ int __init board_register_devices(void)
+@@ -854,6 +855,7 @@ int __init board_register_devices(void)
  {
  	int button_count = 0;
  	int led_count = 0;
@@ -26,7 +26,7 @@ Subject: [PATCH 67/80] BCM63XX: allow providing fixup data in board data
  
  	if (board.has_uart0)
  		bcm63xx_uart_register(0);
-@@ -887,7 +889,8 @@ int __init board_register_devices(void)
+@@ -889,7 +891,8 @@ int __init board_register_devices(void)
  	 * do this after registering enet devices
  	 */
  #ifdef CONFIG_SSB_PCIHOST
@@ -36,9 +36,9 @@ Subject: [PATCH 67/80] BCM63XX: allow providing fixup data in board data
  		memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
  		memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
  		if (ssb_arch_register_fallback_sprom(
-@@ -932,5 +935,9 @@ int __init board_register_devices(void)
- 		bcm63xx_pci_register();
- #endif
+@@ -929,5 +932,9 @@ int __init board_register_devices(void)
+ 		platform_device_register(&bcm63xx_gpio_keys_device);
+ 	}
  
 +	/* register any fixups */
 +	for (i = 0; i < board.has_caldata; i++)
diff --git a/target/linux/brcm63xx/patches-3.3/427-MTD-m25p80-allow-passing-pp_data.patch b/target/linux/brcm63xx/patches-3.3/427-MTD-m25p80-allow-passing-pp_data.patch
index 51836f56175b..6e5cdbe840bf 100644
--- a/target/linux/brcm63xx/patches-3.3/427-MTD-m25p80-allow-passing-pp_data.patch
+++ b/target/linux/brcm63xx/patches-3.3/427-MTD-m25p80-allow-passing-pp_data.patch
@@ -1,16 +1,16 @@
-From 087a67d5750a51f5b0851228b5b2518f3300f7d8 Mon Sep 17 00:00:00 2001
+From f888824d352df894ab721a5ca067b0313500efe7 Mon Sep 17 00:00:00 2001
 From: Jonas Gorski <jonas.gorski@gmail.com>
 Date: Thu, 3 May 2012 12:17:54 +0200
-Subject: [PATCH 65/79] MIPS: BCM63XX: store the flash type in global variable
+Subject: [PATCH 38/59] MIPS: BCM63XX: store the flash type in global variable
 
 ---
- arch/mips/bcm63xx/dev-flash.c                      |   36 +++++++++++++-------
- .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h   |    2 ++
+ arch/mips/bcm63xx/dev-flash.c                      |   36 +++++++++++++------
+ .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h   |    2 +
  2 files changed, 26 insertions(+), 12 deletions(-)
 
 --- a/arch/mips/bcm63xx/dev-flash.c
 +++ b/arch/mips/bcm63xx/dev-flash.c
-@@ -24,6 +24,8 @@
+@@ -25,6 +25,8 @@
  #include <bcm63xx_regs.h>
  #include <bcm63xx_io.h>
  
@@ -19,9 +19,9 @@ Subject: [PATCH 65/79] MIPS: BCM63XX: store the flash type in global variable
  static struct mtd_partition mtd_partitions[] = {
  	{
  		.name		= "cfe",
-@@ -81,20 +83,23 @@ static int __init bcm63xx_detect_flash_t
- 		bcm63xx_spi_flash_info[0].max_speed_hz = 40000000;
- 		val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
+@@ -86,20 +88,23 @@ static int __init bcm63xx_detect_flash_t
+ 			bcm63xx_spi_flash_info[0].max_speed_hz = 16666667;
+ 
  		if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
 -			return BCM63XX_FLASH_TYPE_SERIAL;
 +			bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_SERIAL;
@@ -48,7 +48,7 @@ Subject: [PATCH 65/79] MIPS: BCM63XX: store the flash type in global variable
  	case BCM6368_CPU_ID:
  		val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
  		if (val & STRAPBUS_6368_SPI_CLK_FAST)
-@@ -102,25 +107,32 @@ static int __init bcm63xx_detect_flash_t
+@@ -107,25 +112,32 @@ static int __init bcm63xx_detect_flash_t
  
  		switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
  		case STRAPBUS_6368_BOOT_SEL_NAND:
@@ -87,10 +87,10 @@ Subject: [PATCH 65/79] MIPS: BCM63XX: store the flash type in global variable
  	case BCM63XX_FLASH_TYPE_PARALLEL:
  		/* read base address of boot chip select (0) */
  		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-@@ -141,7 +153,7 @@ int __init bcm63xx_flash_register(void)
+@@ -146,7 +158,7 @@ int __init bcm63xx_flash_register(void)
  		return -ENODEV;
  	default:
- 		pr_err("flash detection failed for BCM%x: %d",
+ 		pr_err("flash detection failed for BCM%x: %d\n",
 -		       bcm63xx_get_cpu_id(), flash_type);
 +		       bcm63xx_get_cpu_id(), bcm63xx_attached_flash);
  		return -ENODEV;
diff --git a/target/linux/brcm63xx/patches-3.3/428-BCM63XX-add-a-fixup-for-ath9k-devices.patch b/target/linux/brcm63xx/patches-3.3/428-BCM63XX-add-a-fixup-for-ath9k-devices.patch
index 42a799862f41..a3b30e444353 100644
--- a/target/linux/brcm63xx/patches-3.3/428-BCM63XX-add-a-fixup-for-ath9k-devices.patch
+++ b/target/linux/brcm63xx/patches-3.3/428-BCM63XX-add-a-fixup-for-ath9k-devices.patch
@@ -16,7 +16,7 @@ Subject: [PATCH 66/80] BCM63XX: add a fixup for ath9k devices
 @@ -1,7 +1,7 @@
  obj-y		+= clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o setup.o \
  		   timer.o dev-dsp.o dev-enet.o dev-flash.o dev-hsspi.o \
- 		   dev-pcmcia.o dev-spi.o dev-trng.o dev-uart.o dev-usb-ehci.o \
+ 		   dev-pcmcia.o dev-rng.o dev-spi.o dev-uart.o dev-usb-ehci.o \
 -		   dev-usb-ohci.o dev-wdt.o
 +		   dev-usb-ohci.o dev-wdt.o pci-ath9k-fixup.o
  obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
diff --git a/target/linux/brcm63xx/patches-3.3/430-MIPS-BCM63XX-pass-caldata-info-to-flash.patch b/target/linux/brcm63xx/patches-3.3/430-MIPS-BCM63XX-pass-caldata-info-to-flash.patch
index 0a406faed17b..5553d0b37f00 100644
--- a/target/linux/brcm63xx/patches-3.3/430-MIPS-BCM63XX-pass-caldata-info-to-flash.patch
+++ b/target/linux/brcm63xx/patches-3.3/430-MIPS-BCM63XX-pass-caldata-info-to-flash.patch
@@ -11,7 +11,7 @@ Subject: [PATCH 69/80] MIPS: BCM63XX: pass caldata info to flash
 
 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -908,7 +908,7 @@ int __init board_register_devices(void)
+@@ -910,7 +910,7 @@ int __init board_register_devices(void)
  	if (board.num_spis)
  		spi_register_board_info(board.spis, board.num_spis);
  
@@ -22,7 +22,7 @@ Subject: [PATCH 69/80] MIPS: BCM63XX: pass caldata info to flash
  	while (led_count < ARRAY_SIZE(board.leds) && board.leds[led_count].name)
 --- a/arch/mips/bcm63xx/dev-flash.c
 +++ b/arch/mips/bcm63xx/dev-flash.c
-@@ -34,12 +34,15 @@ static struct mtd_partition mtd_partitio
+@@ -35,12 +35,15 @@ static struct mtd_partition mtd_partitio
  	}
  };
  
@@ -38,7 +38,7 @@ Subject: [PATCH 69/80] MIPS: BCM63XX: pass caldata info to flash
  };
  
  static struct resource mtd_resources[] = {
-@@ -61,6 +64,7 @@ static struct platform_device mtd_dev =
+@@ -62,6 +65,7 @@ static struct platform_device mtd_dev =
  
  static struct flash_platform_data bcm63xx_flash_data = {
  	.part_probe_types	= bcm63xx_part_types,
@@ -46,7 +46,7 @@ Subject: [PATCH 69/80] MIPS: BCM63XX: pass caldata info to flash
  };
  
  static struct spi_board_info bcm63xx_spi_flash_info[] = {
-@@ -125,10 +129,13 @@ static int __init bcm63xx_detect_flash_t
+@@ -130,10 +134,13 @@ static int __init bcm63xx_detect_flash_t
  	return 0;
  }
  
diff --git a/target/linux/brcm63xx/patches-3.3/501-board-NB4.patch b/target/linux/brcm63xx/patches-3.3/501-board-NB4.patch
index 2432b3a0be0b..02ffc6ae2be4 100644
--- a/target/linux/brcm63xx/patches-3.3/501-board-NB4.patch
+++ b/target/linux/brcm63xx/patches-3.3/501-board-NB4.patch
@@ -551,7 +551,7 @@
  /*
   * Register a sane SPROMv2 to make the on-board
   * bcm4318 WLAN work
-@@ -807,6 +1327,9 @@ void __init board_prom_init(void)
+@@ -808,6 +1328,9 @@ void __init board_prom_init(void)
  		boardid_fixup(boot_addr);
  	}
  
diff --git a/target/linux/brcm63xx/patches-3.3/511-board_V2500V.patch b/target/linux/brcm63xx/patches-3.3/511-board_V2500V.patch
index 376b57e2fa94..6fca36f2a1ac 100644
--- a/target/linux/brcm63xx/patches-3.3/511-board_V2500V.patch
+++ b/target/linux/brcm63xx/patches-3.3/511-board_V2500V.patch
@@ -72,7 +72,7 @@
  #endif
  
  #ifdef CONFIG_BCM63XX_CPU_6358
-@@ -1908,6 +1966,23 @@ void __init board_prom_init(void)
+@@ -1909,6 +1967,23 @@ void __init board_prom_init(void)
  		val &= MPI_CSBASE_BASE_MASK;
  	}
  	boot_addr = (u8 *)KSEG1ADDR(val);
@@ -98,7 +98,7 @@
  	cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET;
 --- a/arch/mips/bcm63xx/dev-flash.c
 +++ b/arch/mips/bcm63xx/dev-flash.c
-@@ -18,6 +18,7 @@
+@@ -19,6 +19,7 @@
  #include <linux/spi/spi.h>
  #include <linux/spi/flash.h>
  
@@ -106,7 +106,7 @@
  #include <bcm63xx_cpu.h>
  #include <bcm63xx_dev_flash.h>
  #include <bcm63xx_dev_hsspi.h>
-@@ -145,6 +146,13 @@ int __init bcm63xx_flash_register(int nu
+@@ -150,6 +151,13 @@ int __init bcm63xx_flash_register(int nu
  		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
  		val &= MPI_CSBASE_BASE_MASK;
  
diff --git a/target/linux/brcm63xx/patches-3.3/520-bcm63xx-add-support-for-96368MVWG-board.patch b/target/linux/brcm63xx/patches-3.3/520-bcm63xx-add-support-for-96368MVWG-board.patch
index f408a8c737a3..b1ac91c125bc 100644
--- a/target/linux/brcm63xx/patches-3.3/520-bcm63xx-add-support-for-96368MVWG-board.patch
+++ b/target/linux/brcm63xx/patches-3.3/520-bcm63xx-add-support-for-96368MVWG-board.patch
@@ -102,8 +102,8 @@ Subject: [PATCH 32/63] bcm63xx: add support for 96368MVWG board.
  };
  
  static void __init nb4_nvram_fixup(void)
-@@ -2240,12 +2318,25 @@ void __init board_prom_init(void)
- 	if (board.has_pci) {
+@@ -2242,12 +2320,25 @@ void __init board_prom_init(void)
+ 		bcm63xx_pci_enabled = 1;
  		if (BCMCPU_IS_6348())
  			val |= GPIO_MODE_6348_G2_PCI;
 +