From: INAGAKI Hiroshi Date: Fri, 26 Apr 2024 14:53:58 +0000 (+0900) Subject: ath79: fix PCIe initialization on AR934x X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=98f73552a78e1c6d825dc3ba9845b4c63c3f16c6;p=openwrt%2Fstaging%2Fstintel.git ath79: fix PCIe initialization on AR934x Fix PCIe initialization on AR934x by clearing PLL_PWD bit in addition to PPL(PLL?)_RESET bit of AR724x. Refresh patches by `make target/linux/refresh`. Signed-off-by: INAGAKI Hiroshi Link: https://github.com/openwrt/openwrt/pull/15432 Signed-off-by: Hauke Mehrtens --- diff --git a/target/linux/ath79/patches-6.6/317-MIPS-pci-ar724x-clear-power-down-of-pll-on-AR934x.patch b/target/linux/ath79/patches-6.6/317-MIPS-pci-ar724x-clear-power-down-of-pll-on-AR934x.patch new file mode 100644 index 0000000000..dfb7e483a7 --- /dev/null +++ b/target/linux/ath79/patches-6.6/317-MIPS-pci-ar724x-clear-power-down-of-pll-on-AR934x.patch @@ -0,0 +1,34 @@ +From f2ca10b22ace3ce53b4e3f189bf1dd53a4482475 Mon Sep 17 00:00:00 2001 +From: INAGAKI Hiroshi +Date: Fri, 26 Apr 2024 23:53:58 +0900 +Subject: [PATCH 1/2] MIPS: pci-ar724x: clear power down of pll on AR934x + +Fix PCIe initialization on AR934x by clearing PLL_PWD bit in addition to +PPL_RESET bit of AR724x. + +Signed-off-by: INAGAKI Hiroshi +--- + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -347,6 +347,8 @@ + #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) + #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define AR934X_PLL_PCIE_CONFIG_PLL_PWD BIT(30) ++ + #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) + + #define QCA953X_PLL_CPU_CONFIG_REG 0x00 +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -360,7 +360,8 @@ static void ar724x_pci_hw_init(struct ar + } else { + /* remove the reset of the PCIE PLL */ + ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); +- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET; ++ ppl &= ~(AR934X_PLL_PCIE_CONFIG_PLL_PWD | ++ AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET); + ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); + + /* deassert bypass for the PCIE PLL */ diff --git a/target/linux/ath79/patches-6.6/330-missing-registers.patch b/target/linux/ath79/patches-6.6/330-missing-registers.patch index 74789437ec..d05e741c7e 100644 --- a/target/linux/ath79/patches-6.6/330-missing-registers.patch +++ b/target/linux/ath79/patches-6.6/330-missing-registers.patch @@ -7,7 +7,7 @@ Subject: [PATCH] ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -1231,6 +1231,10 @@ +@@ -1233,6 +1233,10 @@ #define AR934X_ETH_CFG_RDV_DELAY BIT(16) #define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 diff --git a/target/linux/ath79/patches-6.6/331-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch b/target/linux/ath79/patches-6.6/331-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch index c2f228dfe1..5d9c77c69f 100644 --- a/target/linux/ath79/patches-6.6/331-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch +++ b/target/linux/ath79/patches-6.6/331-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch @@ -16,7 +16,7 @@ Signed-off-by: David Bauer --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -1251,7 +1251,12 @@ +@@ -1253,7 +1253,12 @@ */ #define QCA955X_GMAC_REG_ETH_CFG 0x00 @@ -29,7 +29,7 @@ Signed-off-by: David Bauer #define QCA955X_ETH_CFG_RGMII_EN BIT(0) #define QCA955X_ETH_CFG_MII_GE0 BIT(1) -@@ -1273,9 +1278,58 @@ +@@ -1275,9 +1280,58 @@ #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 diff --git a/target/linux/ath79/patches-6.6/332-ath79-sgmii-config.patch b/target/linux/ath79/patches-6.6/332-ath79-sgmii-config.patch index a6a50e4a8a..6f6217ce75 100644 --- a/target/linux/ath79/patches-6.6/332-ath79-sgmii-config.patch +++ b/target/linux/ath79/patches-6.6/332-ath79-sgmii-config.patch @@ -21,7 +21,7 @@ Submitted-by: David Bauer --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -1380,5 +1380,6 @@ +@@ -1382,5 +1382,6 @@ #define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 #define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 diff --git a/target/linux/ath79/patches-6.6/360-MIPS-ath79-export-UART1-reference-clock.patch b/target/linux/ath79/patches-6.6/360-MIPS-ath79-export-UART1-reference-clock.patch index b24ff21692..ae2f5aa0cd 100644 --- a/target/linux/ath79/patches-6.6/360-MIPS-ath79-export-UART1-reference-clock.patch +++ b/target/linux/ath79/patches-6.6/360-MIPS-ath79-export-UART1-reference-clock.patch @@ -45,8 +45,8 @@ Submitted-by: Daniel Golle goto err_iounmap; --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -348,6 +348,7 @@ - #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) +@@ -350,6 +350,7 @@ + #define AR934X_PLL_PCIE_CONFIG_PLL_PWD BIT(30) #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL BIT(7)