From: hersen wu Date: Wed, 13 Mar 2019 20:21:26 +0000 (-0400) Subject: drm/amd/display: skip dsc config for navi10 bring up X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=9e14d4f17e23ce46d346a6a22a295b4a65b9d918;p=openwrt%2Fstaging%2Fblogic.git drm/amd/display: skip dsc config for navi10 bring up [why] we meet a bug when program dsc register even dsc mode is not enabled. disable dsc config for now. we will re-visit this issue. Signed-off-by: hersen wu Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c index 724b5a9e47d0..34f5a7d671b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c @@ -191,6 +191,15 @@ void optc2_set_dsc_config(struct timing_generator *optc, uint32_t dsc_slice_width) { struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t data_format = 0; + /* skip if dsc mode is not changed */ + data_format = dm_read_reg(CTX, REG(OPTC_DATA_FORMAT_CONTROL)); + + data_format = data_format & 0x30; /* bit5:4 */ + data_format = data_format >> 4; + + if (data_format == dsc_mode) + return; REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, dsc_mode); diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index c4fa0b9e7138..e2a6e80013f3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -670,7 +670,7 @@ static const struct dc_debug_options debug_defaults_drv = { .max_downscale_src_width = 5120,/*upto 5K*/ .disable_pplib_wm_range = false, .scl_reset_length10 = true, - .sanity_checks = true, + .sanity_checks = false, .disable_tri_buf = true, };