From: Akshu Agrawal <akshu.agrawal@amd.com>
Date: Tue, 21 Aug 2018 06:59:43 +0000 (+0530)
Subject: ASoC: AMD: Change MCLK to 48Mhz
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=a1b1e9880f0c2754a5ac416a546d9f295f72eabc;p=openwrt%2Fstaging%2Fblogic.git

ASoC: AMD: Change MCLK to 48Mhz

25Mhz MCLK which was earlier used was of spread type.
Thus, we were not getting accurate rate. The 48Mhz system
clk is of non-spread type and we are changing to it to get
accurate rate.

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---

diff --git a/sound/soc/amd/acp-da7219-max98357a.c b/sound/soc/amd/acp-da7219-max98357a.c
index 95c5701e2a30..3879cccbd2c0 100644
--- a/sound/soc/amd/acp-da7219-max98357a.c
+++ b/sound/soc/amd/acp-da7219-max98357a.c
@@ -42,7 +42,7 @@
 #include "../codecs/da7219.h"
 #include "../codecs/da7219-aad.h"
 
-#define CZ_PLAT_CLK 25000000
+#define CZ_PLAT_CLK 48000000
 #define DUAL_CHANNEL		2
 
 static struct snd_soc_jack cz_jack;