From: Felix Fietkau <nbd@openwrt.org>
Date: Sun, 4 May 2014 23:26:20 +0000 (+0000)
Subject: ar71xx/ath9k: fix reading the WMAC revision on AR953x (fixes #15581)
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=b4d93a52cfdc75fde4e56979f6749977197effca;p=openwrt%2Fstaging%2Fthess.git

ar71xx/ath9k: fix reading the WMAC revision on AR953x (fixes #15581)

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 40695
---

diff --git a/package/kernel/mac80211/patches/567-ath9k_ar953x_read_mac_rev.patch b/package/kernel/mac80211/patches/567-ath9k_ar953x_read_mac_rev.patch
new file mode 100644
index 0000000000..31778a4a21
--- /dev/null
+++ b/package/kernel/mac80211/patches/567-ath9k_ar953x_read_mac_rev.patch
@@ -0,0 +1,11 @@
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -260,6 +260,8 @@ static void ath9k_hw_read_revisions(stru
+ 		return;
+ 	case AR9300_DEVID_AR953X:
+ 		ah->hw_version.macVersion = AR_SREV_VERSION_9531;
++		if (ah->get_mac_revision)
++			ah->hw_version.macRev = ah->get_mac_revision();
+ 		return;
+ 	}
+ 
diff --git a/target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index 05ef22bdb5..00458d2843 100644
--- a/target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -168,7 +168,25 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  		platform_device_register(&ath79_uart_device);
 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
-@@ -149,6 +149,24 @@ static void ar934x_wmac_setup(void)
+@@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)
+ 	return -ETIMEDOUT;
+ }
+ 
+-static int ar933x_r1_get_wmac_revision(void)
++static int ar93xx_get_soc_revision(void)
+ {
+ 	return ath79_soc_rev;
+ }
+@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi
+ 		ath79_wmac_data.is_clk_25mhz = true;
+ 
+ 	if (ath79_soc_rev == 1)
+-		ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
++		ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
+ 
+ 	ath79_wmac_data.external_reset = ar933x_wmac_reset;
+ }
+@@ -149,6 +149,26 @@ static void ar934x_wmac_setup(void)
  		ath79_wmac_data.is_clk_25mhz = true;
  }
  
@@ -188,12 +206,14 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
 +		ath79_wmac_data.is_clk_25mhz = false;
 +	else
 +		ath79_wmac_data.is_clk_25mhz = true;
++
++	ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
 +}
 +
  static void qca955x_wmac_setup(void)
  {
  	u32 t;
-@@ -366,6 +384,8 @@ void __init ath79_register_wmac(u8 *cal_
+@@ -366,6 +386,8 @@ void __init ath79_register_wmac(u8 *cal_
  		ar933x_wmac_setup();
  	else if (soc_is_ar934x())
  		ar934x_wmac_setup();