From: Scott Telford <stelford@cadence.com>
Date: Thu, 15 Sep 2016 15:26:45 +0000 (+0100)
Subject: xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=bebbc4bcf36f015a5a051cc8817b11de209fbe8b;p=openwrt%2Fstaging%2Fblogic.git

xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.

Add module parameter xilinx_uartps.rx_trigger_level=32 to command line
options for CSP to set Rx watermark for xuartps driver lower than the
default value, to avoid UART overruns at 115200 bps.

Signed-off-by: Scott Telford <stelford@cadence.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---

diff --git a/arch/xtensa/boot/dts/csp.dts b/arch/xtensa/boot/dts/csp.dts
index 197aeadb3f90..4082f26716b9 100644
--- a/arch/xtensa/boot/dts/csp.dts
+++ b/arch/xtensa/boot/dts/csp.dts
@@ -7,7 +7,7 @@
 	interrupt-parent = <&pic>;
 
 	chosen {
-		bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk loglevel=8 nohz=off ignore_loglevel";
+		bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel";
 	};
 
 	memory@0 {