From: John Crispin <john@openwrt.org>
Date: Thu, 6 Nov 2014 12:19:53 +0000 (+0000)
Subject: ralink: improve r43200
X-Git-Tag: reboot~5406
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=c32ad22e40062f7786777d58c96d505057b8a41c;p=openwrt%2Fstaging%2Fblogic.git

ralink: improve r43200

r43200 tries to detect if the fixup is needed or not. control the behaviour via
OF instead and disable unused ports.

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 43201
---

diff --git a/target/linux/ramips/dts/E1700.dts b/target/linux/ramips/dts/E1700.dts
index c95b50107436..c9d03cdc2333 100644
--- a/target/linux/ramips/dts/E1700.dts
+++ b/target/linux/ramips/dts/E1700.dts
@@ -109,6 +109,7 @@
 
 	gsw@10110000 {
 		ralink,port4 = "gmac";
+		mediatek,mt7530 = <1>;
 	};
 
 	wmac@10180000 {
diff --git a/target/linux/ramips/dts/MT7620a_MT7530.dts b/target/linux/ramips/dts/MT7620a_MT7530.dts
index 2888efd5f1d7..4f311441dcec 100644
--- a/target/linux/ramips/dts/MT7620a_MT7530.dts
+++ b/target/linux/ramips/dts/MT7620a_MT7530.dts
@@ -99,6 +99,7 @@
 
 	gsw@10110000 {
 		ralink,port4 = "gmac";
+		mediatek,mt7530 = <1>;
 	};
 
 	pcie@10140000 {
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c
index 0f9fc35fe3e1..e31dd29b4202 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c
@@ -73,7 +73,6 @@
 #define GSW_REG_IMR		0x7008
 #define GSW_REG_ISR		0x700c
 #define GSW_REG_GPC1		0x7014
-#define GSW_PHY1_DISABLE	BIT(25)
 
 #define SYSC_REG_CFG1		0x14
 
@@ -409,15 +408,19 @@ void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
 	}
 }
 
-static void gsw_hw_init(struct mt7620_gsw *gsw)
+static void gsw_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
 {
 	u32 is_BGA = mt7620_is_bga();
 
 	rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
 	gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
 
-	/* EPHY1 fixup - only run if the ephy is enabled */
-	if (gsw_r32(gsw, GSW_REG_GPC1) & GSW_PHY1_DISABLE == GSW_PHY1_DISABLE) {
+	if (of_property_read_bool(np, "mediatek,mt7530")) {
+		gsw_w32(gsw, gsw_r32(gsw, GSW_REG_GPC1) | (0x1f << 24), GSW_REG_GPC1);
+		pr_info("gsw: truning EPHY off\n");
+	} else {
+		/* EPHY1 fixup - only run if the ephy is enabled */
+
 		/*correct  PHY  setting L3.0 BGA*/
 		_mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
 
@@ -565,7 +568,7 @@ int mt7620_gsw_probe(struct fe_priv *priv)
 	else
 		WARN_ON(port4);
 
-	gsw_hw_init(gsw);
+	gsw_hw_init(gsw, np);
 
 	gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
 	request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);