From: Ville Syrjälä Date: Fri, 18 Aug 2017 18:37:01 +0000 (+0300) Subject: drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=c5498089463b94690085158eba7dd29835c8c9b8;p=openwrt%2Fstaging%2Fblogic.git drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode The execlist code already masks everything in the ring HWSTAM, but the ringbuffer code doesn't. Let's go ahead and do that. Pre-gen6 platforms setup HWSTAM during irq setup already since there's just the one register, and it also contains bits for non-ring interrupts. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20170818183705.27850-13-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson --- diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 8af8871a8594..22e5ea8516b6 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -428,6 +428,9 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) mmio = RING_HWS_PGA(engine->mmio_base); } + if (INTEL_GEN(dev_priv) >= 6) + I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); + I915_WRITE(mmio, engine->status_page.ggtt_offset); POSTING_READ(mmio);