From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Date: Tue, 27 Nov 2007 18:31:33 +0000 (+0100)
Subject: [MIPS] Use correct dma flushing in dma_cache_sync()
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=c7c6b39050aed4af913c17970ebfb592bae757fc;p=openwrt%2Fstaging%2Fblogic.git

[MIPS] Use correct dma flushing in dma_cache_sync()

Not cache coherent R10k systems (like IP28) need to do real cache
invalidates in dma_cache_sync().

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 810535dd091b..ae39dd88b9aa 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -383,7 +383,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
 	BUG_ON(direction == DMA_NONE);
 
 	if (!plat_device_is_coherent(dev))
-		dma_cache_wback_inv((unsigned long)vaddr, size);
+		__dma_sync((unsigned long)vaddr, size, direction);
 }
 
 EXPORT_SYMBOL(dma_cache_sync);