From: Daniel Kestrel Date: Mon, 31 May 2021 12:13:42 +0000 (+0200) Subject: ltq-deu: set correct control register for AES X-Git-Tag: v22.03.0-rc1~824 X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=c8967d6d12b25cf50b7e060485004c1332a40367;p=openwrt%2Fopenwrt.git ltq-deu: set correct control register for AES Some devices initialize AES during boot and AES works out of the box and the correct endianess is set. NDC means (No Danube Compatibility Mode) and the endianess setting has no effect if its set to 0. NDC 0: OFF ENDI bit cannot be written as in Danube To make it work for other devices, the NDC control register needs to be set to 1. Signed-off-by: Daniel Kestrel --- diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c index aaa7bce237..8063672613 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c @@ -107,7 +107,7 @@ void aes_chip_init (void) // start crypto engine with write to ILR aes->controlr.SM = 1; - aes->controlr.NDC = 0; + aes->controlr.NDC = 1; asm("sync"); aes->controlr.ENDI = 1; asm("sync");