From: Ben Skeggs Date: Wed, 14 Jan 2015 02:11:28 +0000 (+1000) Subject: drm/nouveau/pm: rename from perfmon (no binary change) X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=d5752b9b86fbfb8febd9d45ac4431325031e25e0;p=openwrt%2Fstaging%2Fblogic.git drm/nouveau/pm: rename from perfmon (no binary change) Switch to NVIDIA's name for the device. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs --- diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index 952e36cdb71c..3d87d3daa5a8 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -58,7 +58,7 @@ enum nv_subdev_type { NVDEV_ENGINE_VIC, NVDEV_ENGINE_VENC, NVDEV_ENGINE_DISP, - NVDEV_ENGINE_PERFMON, + NVDEV_ENGINE_PM, NVDEV_ENGINE_MSVLD, NVDEV_ENGINE_SEC, diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/perfmon.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/perfmon.h deleted file mode 100644 index 251c8545ca58..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/perfmon.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef __NVKM_PERFMON_H__ -#define __NVKM_PERFMON_H__ - -#include -#include -#include - -struct nouveau_perfdom; -struct nouveau_perfctr; -struct nouveau_perfmon { - struct nouveau_engine base; - - struct nouveau_perfctx *context; - void *profile_data; - - struct list_head domains; - u32 sequence; - - /*XXX: temp for daemon backend */ - u32 pwr[8]; - u32 last; -}; - -static inline struct nouveau_perfmon * -nouveau_perfmon(void *obj) -{ - return (void *)nouveau_engine(obj, NVDEV_ENGINE_PERFMON); -} - -extern struct nouveau_oclass *nv40_perfmon_oclass; -extern struct nouveau_oclass *nv50_perfmon_oclass; -extern struct nouveau_oclass *nv84_perfmon_oclass; -extern struct nouveau_oclass *nva3_perfmon_oclass; -extern struct nouveau_oclass nvc0_perfmon_oclass; -extern struct nouveau_oclass nve0_perfmon_oclass; -extern struct nouveau_oclass nvf0_perfmon_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h new file mode 100644 index 000000000000..c9ffe2c70746 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h @@ -0,0 +1,38 @@ +#ifndef __NVKM_PM_H__ +#define __NVKM_PM_H__ + +#include +#include +#include + +struct nouveau_perfdom; +struct nouveau_perfctr; +struct nouveau_pm { + struct nouveau_engine base; + + struct nouveau_perfctx *context; + void *profile_data; + + struct list_head domains; + u32 sequence; + + /*XXX: temp for daemon backend */ + u32 pwr[8]; + u32 last; +}; + +static inline struct nouveau_pm * +nouveau_pm(void *obj) +{ + return (void *)nouveau_engine(obj, NVDEV_ENGINE_PM); +} + +extern struct nouveau_oclass *nv40_pm_oclass; +extern struct nouveau_oclass *nv50_pm_oclass; +extern struct nouveau_oclass *nv84_pm_oclass; +extern struct nouveau_oclass *nva3_pm_oclass; +extern struct nouveau_oclass nvc0_pm_oclass; +extern struct nouveau_oclass nve0_pm_oclass; +extern struct nouveau_oclass nvf0_pm_oclass; + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild index 183475e2a924..16c3a91b7e4a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild @@ -11,7 +11,7 @@ include $(src)/nvkm/engine/fifo/Kbuild include $(src)/nvkm/engine/gr/Kbuild include $(src)/nvkm/engine/mpeg/Kbuild include $(src)/nvkm/engine/msvld/Kbuild -include $(src)/nvkm/engine/perfmon/Kbuild +include $(src)/nvkm/engine/pm/Kbuild include $(src)/nvkm/engine/ppp/Kbuild include $(src)/nvkm/engine/sec/Kbuild include $(src)/nvkm/engine/software/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index baad4ad22058..5b226cb04298 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -225,7 +225,7 @@ static const u64 disable_map[] = { [NVDEV_SUBDEV_PMU] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_SUBDEV_FUSE] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_V0_DISABLE_CORE, - [NVDEV_ENGINE_PERFMON] = NV_DEVICE_V0_DISABLE_CORE, + [NVDEV_ENGINE_PM ] = NV_DEVICE_V0_DISABLE_CORE, [NVDEV_ENGINE_FIFO] = NV_DEVICE_V0_DISABLE_FIFO, [NVDEV_ENGINE_SW] = NV_DEVICE_V0_DISABLE_FIFO, [NVDEV_ENGINE_GR] = NV_DEVICE_V0_DISABLE_GR, @@ -319,7 +319,7 @@ nouveau_devobj_ctor(struct nouveau_object *parent, (1ULL << NVDEV_ENGINE_DMAOBJ) | (1ULL << NVDEV_ENGINE_FIFO) | (1ULL << NVDEV_ENGINE_DISP) | - (1ULL << NVDEV_ENGINE_PERFMON), &devobj); + (1ULL << NVDEV_ENGINE_PM ), &devobj); *pobject = nv_object(devobj); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index e7289fd2da9b..2ea1dbcf641f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -53,7 +53,7 @@ #include #include #include -#include +#include int gm100_identify(struct nouveau_device *device) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index 3b16fdc4c95e..cd859b081db4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -44,7 +44,7 @@ #include #include #include -#include +#include int nv40_identify(struct nouveau_device *device) @@ -71,7 +71,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x41: device->cname = "NV41"; @@ -94,7 +94,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x42: device->cname = "NV42"; @@ -117,7 +117,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x43: device->cname = "NV43"; @@ -140,7 +140,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x45: device->cname = "NV45"; @@ -163,7 +163,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x47: device->cname = "G70"; @@ -186,7 +186,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x49: device->cname = "G71"; @@ -209,7 +209,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4b: device->cname = "G73"; @@ -232,7 +232,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x44: device->cname = "NV44"; @@ -255,7 +255,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x46: device->cname = "G72"; @@ -278,7 +278,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4a: device->cname = "NV44A"; @@ -301,7 +301,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4c: device->cname = "C61"; @@ -324,7 +324,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4e: device->cname = "C51"; @@ -347,7 +347,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x63: device->cname = "C73"; @@ -370,7 +370,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x67: device->cname = "C67"; @@ -393,7 +393,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x68: device->cname = "C68"; @@ -416,7 +416,7 @@ nv40_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; default: nv_fatal(device, "unknown Curie chipset\n"); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index a9788b4999c6..6e5ccb371372 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -54,7 +54,7 @@ #include #include #include -#include +#include int nv50_identify(struct nouveau_device *device) @@ -84,7 +84,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; break; case 0x84: device->cname = "G84"; @@ -113,7 +113,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; break; case 0x86: device->cname = "G86"; @@ -142,7 +142,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; break; case 0x92: device->cname = "G92"; @@ -171,7 +171,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; break; case 0x94: device->cname = "G94"; @@ -200,7 +200,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; break; case 0x96: device->cname = "G96"; @@ -229,7 +229,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; break; case 0x98: device->cname = "G98"; @@ -258,7 +258,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; break; case 0xa0: device->cname = "G200"; @@ -287,7 +287,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; break; case 0xaa: device->cname = "MCP77/MCP78"; @@ -316,7 +316,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; break; case 0xac: device->cname = "MCP79/MCP7A"; @@ -345,7 +345,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; break; case 0xa3: device->cname = "GT215"; @@ -376,7 +376,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; break; case 0xa5: device->cname = "GT216"; @@ -406,7 +406,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; break; case 0xa8: device->cname = "GT218"; @@ -436,7 +436,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; break; case 0xaf: device->cname = "MCP89"; @@ -466,7 +466,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; break; default: nv_fatal(device, "unknown Tesla chipset\n"); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index 1f93c9611f37..d159d2993043 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c @@ -53,7 +53,7 @@ #include #include #include -#include +#include int nvc0_identify(struct nouveau_device *device) @@ -90,7 +90,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; case 0xc4: device->cname = "GF104"; @@ -123,7 +123,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; case 0xc3: device->cname = "GF106"; @@ -155,7 +155,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; case 0xce: device->cname = "GF114"; @@ -188,7 +188,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; case 0xcf: device->cname = "GF116"; @@ -220,7 +220,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; case 0xc1: device->cname = "GF108"; @@ -252,7 +252,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; case 0xc8: device->cname = "GF110"; @@ -285,7 +285,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; case 0xd9: device->cname = "GF119"; @@ -317,7 +317,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; case 0xd7: device->cname = "GF117"; @@ -347,7 +347,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; default: nv_fatal(device, "unknown Fermi chipset\n"); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index c18f5821c3cf..c68e76b40d51 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c @@ -53,7 +53,7 @@ #include #include #include -#include +#include int nve0_identify(struct nouveau_device *device) @@ -91,7 +91,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; break; case 0xe7: device->cname = "GK107"; @@ -125,7 +125,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; break; case 0xe6: device->cname = "GK106"; @@ -159,7 +159,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; break; case 0xea: device->cname = "GK20A"; @@ -179,7 +179,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass; break; @@ -215,7 +215,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass; break; case 0xf1: device->cname = "GK110B"; @@ -249,7 +249,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; - device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass; + device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass; break; case 0x106: device->cname = "GK208B"; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/Kbuild deleted file mode 100644 index d5f574c4e7b2..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/Kbuild +++ /dev/null @@ -1,9 +0,0 @@ -nvkm-y += nvkm/engine/perfmon/base.o -nvkm-y += nvkm/engine/perfmon/daemon.o -nvkm-y += nvkm/engine/perfmon/nv40.o -nvkm-y += nvkm/engine/perfmon/nv50.o -nvkm-y += nvkm/engine/perfmon/nv84.o -nvkm-y += nvkm/engine/perfmon/nva3.o -nvkm-y += nvkm/engine/perfmon/nvc0.o -nvkm-y += nvkm/engine/perfmon/nve0.o -nvkm-y += nvkm/engine/perfmon/nvf0.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c deleted file mode 100644 index 3a9359e29179..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c +++ /dev/null @@ -1,483 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include -#include -#include - -#include - -#include "priv.h" - -#define QUAD_MASK 0x0f -#define QUAD_FREE 0x01 - -static struct nouveau_perfsig * -nouveau_perfsig_find_(struct nouveau_perfdom *dom, const char *name, u32 size) -{ - char path[64]; - int i; - - if (name[0] != '/') { - for (i = 0; i < dom->signal_nr; i++) { - if ( dom->signal[i].name && - !strncmp(name, dom->signal[i].name, size)) - return &dom->signal[i]; - } - } else { - for (i = 0; i < dom->signal_nr; i++) { - snprintf(path, sizeof(path), "/%s/%02x", dom->name, i); - if (!strncmp(name, path, size)) - return &dom->signal[i]; - } - } - - return NULL; -} - -struct nouveau_perfsig * -nouveau_perfsig_find(struct nouveau_perfmon *ppm, const char *name, u32 size, - struct nouveau_perfdom **pdom) -{ - struct nouveau_perfdom *dom = *pdom; - struct nouveau_perfsig *sig; - - if (dom == NULL) { - list_for_each_entry(dom, &ppm->domains, head) { - sig = nouveau_perfsig_find_(dom, name, size); - if (sig) { - *pdom = dom; - return sig; - } - } - - return NULL; - } - - return nouveau_perfsig_find_(dom, name, size); -} - -struct nouveau_perfctr * -nouveau_perfsig_wrap(struct nouveau_perfmon *ppm, const char *name, - struct nouveau_perfdom **pdom) -{ - struct nouveau_perfsig *sig; - struct nouveau_perfctr *ctr; - - sig = nouveau_perfsig_find(ppm, name, strlen(name), pdom); - if (!sig) - return NULL; - - ctr = kzalloc(sizeof(*ctr), GFP_KERNEL); - if (ctr) { - ctr->signal[0] = sig; - ctr->logic_op = 0xaaaa; - } - - return ctr; -} - -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ -static int -nouveau_perfctr_query(struct nouveau_object *object, void *data, u32 size) -{ - union { - struct nvif_perfctr_query_v0 v0; - } *args = data; - struct nouveau_device *device = nv_device(object); - struct nouveau_perfmon *ppm = (void *)object->engine; - struct nouveau_perfdom *dom = NULL, *chk; - const bool all = nouveau_boolopt(device->cfgopt, "NvPmShowAll", false); - const bool raw = nouveau_boolopt(device->cfgopt, "NvPmUnnamed", all); - const char *name; - int tmp = 0, di, si; - int ret; - - nv_ioctl(object, "perfctr query size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nv_ioctl(object, "perfctr query vers %d iter %08x\n", - args->v0.version, args->v0.iter); - di = (args->v0.iter & 0xff000000) >> 24; - si = (args->v0.iter & 0x00ffffff) - 1; - } else - return ret; - - list_for_each_entry(chk, &ppm->domains, head) { - if (tmp++ == di) { - dom = chk; - break; - } - } - - if (dom == NULL || si >= (int)dom->signal_nr) - return -EINVAL; - - if (si >= 0) { - if (raw || !(name = dom->signal[si].name)) { - snprintf(args->v0.name, sizeof(args->v0.name), - "/%s/%02x", dom->name, si); - } else { - strncpy(args->v0.name, name, sizeof(args->v0.name)); - } - } - - do { - while (++si < dom->signal_nr) { - if (all || dom->signal[si].name) { - args->v0.iter = (di << 24) | ++si; - return 0; - } - } - si = -1; - di = di + 1; - dom = list_entry(dom->head.next, typeof(*dom), head); - } while (&dom->head != &ppm->domains); - - args->v0.iter = 0xffffffff; - return 0; -} - -static int -nouveau_perfctr_sample(struct nouveau_object *object, void *data, u32 size) -{ - union { - struct nvif_perfctr_sample none; - } *args = data; - struct nouveau_perfmon *ppm = (void *)object->engine; - struct nouveau_perfctr *ctr, *tmp; - struct nouveau_perfdom *dom; - int ret; - - nv_ioctl(object, "perfctr sample size %d\n", size); - if (nvif_unvers(args->none)) { - nv_ioctl(object, "perfctr sample\n"); - } else - return ret; - ppm->sequence++; - - list_for_each_entry(dom, &ppm->domains, head) { - /* sample previous batch of counters */ - if (dom->quad != QUAD_MASK) { - dom->func->next(ppm, dom); - tmp = NULL; - while (!list_empty(&dom->list)) { - ctr = list_first_entry(&dom->list, - typeof(*ctr), head); - if (ctr->slot < 0) break; - if ( tmp && tmp == ctr) break; - if (!tmp) tmp = ctr; - dom->func->read(ppm, dom, ctr); - ctr->slot = -1; - list_move_tail(&ctr->head, &dom->list); - } - } - - dom->quad = QUAD_MASK; - - /* setup next batch of counters for sampling */ - list_for_each_entry(ctr, &dom->list, head) { - ctr->slot = ffs(dom->quad) - 1; - if (ctr->slot < 0) - break; - dom->quad &= ~(QUAD_FREE << ctr->slot); - dom->func->init(ppm, dom, ctr); - } - - if (dom->quad != QUAD_MASK) - dom->func->next(ppm, dom); - } - - return 0; -} - -static int -nouveau_perfctr_read(struct nouveau_object *object, void *data, u32 size) -{ - union { - struct nvif_perfctr_read_v0 v0; - } *args = data; - struct nouveau_perfctr *ctr = (void *)object; - int ret; - - nv_ioctl(object, "perfctr read size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nv_ioctl(object, "perfctr read vers %d\n", args->v0.version); - } else - return ret; - - if (!ctr->clk) - return -EAGAIN; - - args->v0.clk = ctr->clk; - args->v0.ctr = ctr->ctr; - return 0; -} - -static int -nouveau_perfctr_mthd(struct nouveau_object *object, u32 mthd, - void *data, u32 size) -{ - switch (mthd) { - case NVIF_PERFCTR_V0_QUERY: - return nouveau_perfctr_query(object, data, size); - case NVIF_PERFCTR_V0_SAMPLE: - return nouveau_perfctr_sample(object, data, size); - case NVIF_PERFCTR_V0_READ: - return nouveau_perfctr_read(object, data, size); - default: - break; - } - return -EINVAL; -} - -static void -nouveau_perfctr_dtor(struct nouveau_object *object) -{ - struct nouveau_perfctr *ctr = (void *)object; - if (ctr->head.next) - list_del(&ctr->head); - nouveau_object_destroy(&ctr->base); -} - -static int -nouveau_perfctr_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - union { - struct nvif_perfctr_v0 v0; - } *args = data; - struct nouveau_perfmon *ppm = (void *)engine; - struct nouveau_perfdom *dom = NULL; - struct nouveau_perfsig *sig[4] = {}; - struct nouveau_perfctr *ctr; - int ret, i; - - nv_ioctl(parent, "create perfctr size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nv_ioctl(parent, "create perfctr vers %d logic_op %04x\n", - args->v0.version, args->v0.logic_op); - } else - return ret; - - for (i = 0; i < ARRAY_SIZE(args->v0.name) && args->v0.name[i][0]; i++) { - sig[i] = nouveau_perfsig_find(ppm, args->v0.name[i], - strnlen(args->v0.name[i], - sizeof(args->v0.name[i])), - &dom); - if (!sig[i]) - return -EINVAL; - } - - ret = nouveau_object_create(parent, engine, oclass, 0, &ctr); - *pobject = nv_object(ctr); - if (ret) - return ret; - - ctr->slot = -1; - ctr->logic_op = args->v0.logic_op; - ctr->signal[0] = sig[0]; - ctr->signal[1] = sig[1]; - ctr->signal[2] = sig[2]; - ctr->signal[3] = sig[3]; - if (dom) - list_add_tail(&ctr->head, &dom->list); - return 0; -} - -static struct nouveau_ofuncs -nouveau_perfctr_ofuncs = { - .ctor = nouveau_perfctr_ctor, - .dtor = nouveau_perfctr_dtor, - .init = nouveau_object_init, - .fini = nouveau_object_fini, - .mthd = nouveau_perfctr_mthd, -}; - -struct nouveau_oclass -nouveau_perfmon_sclass[] = { - { .handle = NVIF_IOCTL_NEW_V0_PERFCTR, - .ofuncs = &nouveau_perfctr_ofuncs, - }, - {}, -}; - -/******************************************************************************* - * PPM context - ******************************************************************************/ -static void -nouveau_perfctx_dtor(struct nouveau_object *object) -{ - struct nouveau_perfmon *ppm = (void *)object->engine; - mutex_lock(&nv_subdev(ppm)->mutex); - nouveau_engctx_destroy(&ppm->context->base); - ppm->context = NULL; - mutex_unlock(&nv_subdev(ppm)->mutex); -} - -static int -nouveau_perfctx_ctor(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_perfmon *ppm = (void *)engine; - struct nouveau_perfctx *ctx; - int ret; - - ret = nouveau_engctx_create(parent, engine, oclass, NULL, - 0, 0, 0, &ctx); - *pobject = nv_object(ctx); - if (ret) - return ret; - - mutex_lock(&nv_subdev(ppm)->mutex); - if (ppm->context == NULL) - ppm->context = ctx; - mutex_unlock(&nv_subdev(ppm)->mutex); - - if (ctx != ppm->context) - return -EBUSY; - - return 0; -} - -struct nouveau_oclass -nouveau_perfmon_cclass = { - .handle = NV_ENGCTX(PERFMON, 0x00), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nouveau_perfctx_ctor, - .dtor = nouveau_perfctx_dtor, - .init = _nouveau_engctx_init, - .fini = _nouveau_engctx_fini, - }, -}; - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ -int -nouveau_perfdom_new(struct nouveau_perfmon *ppm, const char *name, u32 mask, - u32 base, u32 size_unit, u32 size_domain, - const struct nouveau_specdom *spec) -{ - const struct nouveau_specdom *sdom; - const struct nouveau_specsig *ssig; - struct nouveau_perfdom *dom; - int i; - - for (i = 0; i == 0 || mask; i++) { - u32 addr = base + (i * size_unit); - if (i && !(mask & (1 << i))) - continue; - - sdom = spec; - while (sdom->signal_nr) { - dom = kzalloc(sizeof(*dom) + sdom->signal_nr * - sizeof(*dom->signal), GFP_KERNEL); - if (!dom) - return -ENOMEM; - - if (mask) { - snprintf(dom->name, sizeof(dom->name), - "%s/%02x/%02x", name, i, - (int)(sdom - spec)); - } else { - snprintf(dom->name, sizeof(dom->name), - "%s/%02x", name, (int)(sdom - spec)); - } - - list_add_tail(&dom->head, &ppm->domains); - INIT_LIST_HEAD(&dom->list); - dom->func = sdom->func; - dom->addr = addr; - dom->quad = QUAD_MASK; - dom->signal_nr = sdom->signal_nr; - - ssig = (sdom++)->signal; - while (ssig->name) { - dom->signal[ssig->signal].name = ssig->name; - ssig++; - } - - addr += size_domain; - } - - mask &= ~(1 << i); - } - - return 0; -} - -int -_nouveau_perfmon_fini(struct nouveau_object *object, bool suspend) -{ - struct nouveau_perfmon *ppm = (void *)object; - return nouveau_engine_fini(&ppm->base, suspend); -} - -int -_nouveau_perfmon_init(struct nouveau_object *object) -{ - struct nouveau_perfmon *ppm = (void *)object; - return nouveau_engine_init(&ppm->base); -} - -void -_nouveau_perfmon_dtor(struct nouveau_object *object) -{ - struct nouveau_perfmon *ppm = (void *)object; - struct nouveau_perfdom *dom, *tmp; - - list_for_each_entry_safe(dom, tmp, &ppm->domains, head) { - list_del(&dom->head); - kfree(dom); - } - - nouveau_engine_destroy(&ppm->base); -} - -int -nouveau_perfmon_create_(struct nouveau_object *parent, - struct nouveau_object *engine, - struct nouveau_oclass *oclass, - int length, void **pobject) -{ - struct nouveau_perfmon *ppm; - int ret; - - ret = nouveau_engine_create_(parent, engine, oclass, true, "PPM", - "perfmon", length, pobject); - ppm = *pobject; - if (ret) - return ret; - - INIT_LIST_HEAD(&ppm->domains); - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/daemon.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/daemon.c deleted file mode 100644 index 50696cc7b7d7..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/daemon.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "priv.h" - -static void -pwr_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, - struct nouveau_perfctr *ctr) -{ - u32 mask = 0x00000000; - u32 ctrl = 0x00000001; - int i; - - for (i = 0; i < ARRAY_SIZE(ctr->signal) && ctr->signal[i]; i++) - mask |= 1 << (ctr->signal[i] - dom->signal); - - nv_wr32(ppm, 0x10a504 + (ctr->slot * 0x10), mask); - nv_wr32(ppm, 0x10a50c + (ctr->slot * 0x10), ctrl); - nv_wr32(ppm, 0x10a50c + (ppm->last * 0x10), 0x00000003); -} - -static void -pwr_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, - struct nouveau_perfctr *ctr) -{ - ctr->ctr = ppm->pwr[ctr->slot]; - ctr->clk = ppm->pwr[ppm->last]; -} - -static void -pwr_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom) -{ - int i; - - for (i = 0; i <= ppm->last; i++) { - ppm->pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10)); - nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x80000000); - } -} - -static const struct nouveau_funcdom -pwr_perfctr_func = { - .init = pwr_perfctr_init, - .read = pwr_perfctr_read, - .next = pwr_perfctr_next, -}; - -const struct nouveau_specdom -nva3_perfmon_pwr[] = { - { 0x20, (const struct nouveau_specsig[]) { - { 0x00, "pwr_gr_idle" }, - { 0x04, "pwr_bsp_idle" }, - { 0x05, "pwr_vp_idle" }, - { 0x06, "pwr_ppp_idle" }, - { 0x13, "pwr_ce0_idle" }, - {} - }, &pwr_perfctr_func }, - {} -}; - -const struct nouveau_specdom -nvc0_perfmon_pwr[] = { - { 0x20, (const struct nouveau_specsig[]) { - { 0x00, "pwr_gr_idle" }, - { 0x04, "pwr_bsp_idle" }, - { 0x05, "pwr_vp_idle" }, - { 0x06, "pwr_ppp_idle" }, - { 0x13, "pwr_ce0_idle" }, - { 0x14, "pwr_ce1_idle" }, - {} - }, &pwr_perfctr_func }, - {} -}; - -const struct nouveau_specdom -nve0_perfmon_pwr[] = { - { 0x20, (const struct nouveau_specsig[]) { - { 0x00, "pwr_gr_idle" }, - { 0x04, "pwr_bsp_idle" }, - { 0x05, "pwr_vp_idle" }, - { 0x06, "pwr_ppp_idle" }, - { 0x13, "pwr_ce0_idle" }, - { 0x14, "pwr_ce1_idle" }, - { 0x15, "pwr_ce2_idle" }, - {} - }, &pwr_perfctr_func }, - {} -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.c deleted file mode 100644 index b2a10785adb1..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nv40.h" - -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - -static void -nv40_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, - struct nouveau_perfctr *ctr) -{ - struct nv40_perfmon_priv *priv = (void *)ppm; - struct nv40_perfmon_cntr *cntr = (void *)ctr; - u32 log = ctr->logic_op; - u32 src = 0x00000000; - int i; - - for (i = 0; i < 4 && ctr->signal[i]; i++) - src |= (ctr->signal[i] - dom->signal) << (i * 8); - - nv_wr32(priv, 0x00a7c0 + dom->addr, 0x00000001); - nv_wr32(priv, 0x00a400 + dom->addr + (cntr->base.slot * 0x40), src); - nv_wr32(priv, 0x00a420 + dom->addr + (cntr->base.slot * 0x40), log); -} - -static void -nv40_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, - struct nouveau_perfctr *ctr) -{ - struct nv40_perfmon_priv *priv = (void *)ppm; - struct nv40_perfmon_cntr *cntr = (void *)ctr; - - switch (cntr->base.slot) { - case 0: cntr->base.ctr = nv_rd32(priv, 0x00a700 + dom->addr); break; - case 1: cntr->base.ctr = nv_rd32(priv, 0x00a6c0 + dom->addr); break; - case 2: cntr->base.ctr = nv_rd32(priv, 0x00a680 + dom->addr); break; - case 3: cntr->base.ctr = nv_rd32(priv, 0x00a740 + dom->addr); break; - } - cntr->base.clk = nv_rd32(priv, 0x00a600 + dom->addr); -} - -static void -nv40_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom) -{ - struct nv40_perfmon_priv *priv = (void *)ppm; - if (priv->sequence != ppm->sequence) { - nv_wr32(priv, 0x400084, 0x00000020); - priv->sequence = ppm->sequence; - } -} - -const struct nouveau_funcdom -nv40_perfctr_func = { - .init = nv40_perfctr_init, - .read = nv40_perfctr_read, - .next = nv40_perfctr_next, -}; - -static const struct nouveau_specdom -nv40_perfmon[] = { - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - {} -}; - -int -nv40_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv40_perfmon_oclass *mclass = (void *)oclass; - struct nv40_perfmon_priv *priv; - int ret; - - ret = nouveau_perfmon_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - ret = nouveau_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms); - if (ret) - return ret; - - nv_engine(priv)->cclass = &nouveau_perfmon_cclass; - nv_engine(priv)->sclass = nouveau_perfmon_sclass; - return 0; -} - -struct nouveau_oclass * -nv40_perfmon_oclass = &(struct nv40_perfmon_oclass) { - .base.handle = NV_ENGINE(PERFMON, 0x40), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv40_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = _nouveau_perfmon_fini, - }, - .doms = nv40_perfmon, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.h deleted file mode 100644 index 1b5792d1df14..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv40.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __NVKM_PM_NV40_H__ -#define __NVKM_PM_NV40_H__ - -#include "priv.h" - -struct nv40_perfmon_oclass { - struct nouveau_oclass base; - const struct nouveau_specdom *doms; -}; - -struct nv40_perfmon_priv { - struct nouveau_perfmon base; - u32 sequence; -}; - -int nv40_perfmon_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *data, u32 size, - struct nouveau_object **pobject); - -struct nv40_perfmon_cntr { - struct nouveau_perfctr base; -}; - -extern const struct nouveau_funcdom nv40_perfctr_func; - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv50.c deleted file mode 100644 index 94217691fe67..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv50.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nv40.h" - -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - -static const struct nouveau_specdom -nv50_perfmon[] = { - { 0x040, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x100, (const struct nouveau_specsig[]) { - { 0xc8, "gr_idle" }, - {} - }, &nv40_perfctr_func }, - { 0x100, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x020, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x040, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - {} -}; - -struct nouveau_oclass * -nv50_perfmon_oclass = &(struct nv40_perfmon_oclass) { - .base.handle = NV_ENGINE(PERFMON, 0x50), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv40_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = _nouveau_perfmon_fini, - }, - .doms = nv50_perfmon, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv84.c deleted file mode 100644 index 9232c7fc6253..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nv84.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nv40.h" - -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - -static const struct nouveau_specdom -nv84_perfmon[] = { - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - {} -}; - -struct nouveau_oclass * -nv84_perfmon_oclass = &(struct nv40_perfmon_oclass) { - .base.handle = NV_ENGINE(PERFMON, 0x84), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv40_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = _nouveau_perfmon_fini, - }, - .doms = nv84_perfmon, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nva3.c deleted file mode 100644 index 6197ebdeb648..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nva3.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nv40.h" - -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - -static const struct nouveau_specdom -nva3_perfmon[] = { - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - { 0x20, (const struct nouveau_specsig[]) { - {} - }, &nv40_perfctr_func }, - {} -}; - -static int -nva3_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **object) -{ - int ret = nv40_perfmon_ctor(parent, engine, oclass, data, size, object); - if (ret == 0) { - struct nv40_perfmon_priv *priv = (void *)*object; - ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, - nva3_perfmon_pwr); - if (ret) - return ret; - - priv->base.last = 3; - } - return ret; -} - -struct nouveau_oclass * -nva3_perfmon_oclass = &(struct nv40_perfmon_oclass) { - .base.handle = NV_ENGINE(PERFMON, 0xa3), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nva3_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = _nouveau_perfmon_fini, - }, - .doms = nva3_perfmon, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.c deleted file mode 100644 index 74b241042502..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" - -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - -static const struct nouveau_specdom -nvc0_perfmon_hub[] = { - {} -}; - -static const struct nouveau_specdom -nvc0_perfmon_gpc[] = { - {} -}; - -static const struct nouveau_specdom -nvc0_perfmon_part[] = { - {} -}; - -static void -nvc0_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, - struct nouveau_perfctr *ctr) -{ - struct nvc0_perfmon_priv *priv = (void *)ppm; - struct nvc0_perfmon_cntr *cntr = (void *)ctr; - u32 log = ctr->logic_op; - u32 src = 0x00000000; - int i; - - for (i = 0; i < 4 && ctr->signal[i]; i++) - src |= (ctr->signal[i] - dom->signal) << (i * 8); - - nv_wr32(priv, dom->addr + 0x09c, 0x00040002); - nv_wr32(priv, dom->addr + 0x100, 0x00000000); - nv_wr32(priv, dom->addr + 0x040 + (cntr->base.slot * 0x08), src); - nv_wr32(priv, dom->addr + 0x044 + (cntr->base.slot * 0x08), log); -} - -static void -nvc0_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, - struct nouveau_perfctr *ctr) -{ - struct nvc0_perfmon_priv *priv = (void *)ppm; - struct nvc0_perfmon_cntr *cntr = (void *)ctr; - - switch (cntr->base.slot) { - case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break; - case 1: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x088); break; - case 2: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x080); break; - case 3: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x090); break; - } - cntr->base.clk = nv_rd32(priv, dom->addr + 0x070); -} - -static void -nvc0_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom) -{ - struct nvc0_perfmon_priv *priv = (void *)ppm; - nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27); - nv_wr32(priv, dom->addr + 0x0ec, 0x00000011); -} - -const struct nouveau_funcdom -nvc0_perfctr_func = { - .init = nvc0_perfctr_init, - .read = nvc0_perfctr_read, - .next = nvc0_perfctr_next, -}; - -int -nvc0_perfmon_fini(struct nouveau_object *object, bool suspend) -{ - struct nvc0_perfmon_priv *priv = (void *)object; - nv_mask(priv, 0x000200, 0x10000000, 0x00000000); - nv_mask(priv, 0x000200, 0x10000000, 0x10000000); - return nouveau_perfmon_fini(&priv->base, suspend); -} - -static int -nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_perfmon_priv *priv; - u32 mask; - int ret; - - ret = nouveau_perfmon_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, - nvc0_perfmon_pwr); - if (ret) - return ret; - - /* HUB */ - ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200, - nvc0_perfmon_hub); - if (ret) - return ret; - - /* GPC */ - mask = (1 << nv_rd32(priv, 0x022430)) - 1; - mask &= ~nv_rd32(priv, 0x022504); - mask &= ~nv_rd32(priv, 0x022584); - - ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000, - 0x1000, 0x200, nvc0_perfmon_gpc); - if (ret) - return ret; - - /* PART */ - mask = (1 << nv_rd32(priv, 0x022438)) - 1; - mask &= ~nv_rd32(priv, 0x022548); - mask &= ~nv_rd32(priv, 0x0225c8); - - ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000, - 0x1000, 0x200, nvc0_perfmon_part); - if (ret) - return ret; - - nv_engine(priv)->cclass = &nouveau_perfmon_cclass; - nv_engine(priv)->sclass = nouveau_perfmon_sclass; - priv->base.last = 7; - return 0; -} - -struct nouveau_oclass -nvc0_perfmon_oclass = { - .handle = NV_ENGINE(PERFMON, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = nvc0_perfmon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.h deleted file mode 100644 index f66bca484263..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvc0.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __NVKM_PM_NVC0_H__ -#define __NVKM_PM_NVC0_H__ - -#include "priv.h" - -struct nvc0_perfmon_priv { - struct nouveau_perfmon base; -}; - -struct nvc0_perfmon_cntr { - struct nouveau_perfctr base; -}; - -extern const struct nouveau_funcdom nvc0_perfctr_func; -int nvc0_perfmon_fini(struct nouveau_object *, bool); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nve0.c deleted file mode 100644 index 71d718c12075..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nve0.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" - -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - -static const struct nouveau_specdom -nve0_perfmon_hub[] = { - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "hub00_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x40, (const struct nouveau_specsig[]) { - { 0x27, "hub01_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "hub02_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "hub03_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x40, (const struct nouveau_specsig[]) { - { 0x03, "host_mmio_rd" }, - { 0x27, "hub04_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "hub05_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0xc0, (const struct nouveau_specsig[]) { - { 0x74, "host_fb_rd3x" }, - { 0x75, "host_fb_rd3x_2" }, - { 0xa7, "hub06_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "hub07_user_0" }, - {} - }, &nvc0_perfctr_func }, - {} -}; - -static const struct nouveau_specdom -nve0_perfmon_gpc[] = { - { 0xe0, (const struct nouveau_specsig[]) { - { 0xc7, "gpc00_user_0" }, - {} - }, &nvc0_perfctr_func }, - {} -}; - -static const struct nouveau_specdom -nve0_perfmon_part[] = { - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "part00_user_0" }, - {} - }, &nvc0_perfctr_func }, - { 0x60, (const struct nouveau_specsig[]) { - { 0x47, "part01_user_0" }, - {} - }, &nvc0_perfctr_func }, - {} -}; - -static int -nve0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_perfmon_priv *priv; - u32 mask; - int ret; - - ret = nouveau_perfmon_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - /* PDAEMON */ - ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, - nve0_perfmon_pwr); - if (ret) - return ret; - - /* HUB */ - ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200, - nve0_perfmon_hub); - if (ret) - return ret; - - /* GPC */ - mask = (1 << nv_rd32(priv, 0x022430)) - 1; - mask &= ~nv_rd32(priv, 0x022504); - mask &= ~nv_rd32(priv, 0x022584); - - ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000, - 0x1000, 0x200, nve0_perfmon_gpc); - if (ret) - return ret; - - /* PART */ - mask = (1 << nv_rd32(priv, 0x022438)) - 1; - mask &= ~nv_rd32(priv, 0x022548); - mask &= ~nv_rd32(priv, 0x0225c8); - - ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000, - 0x1000, 0x200, nve0_perfmon_part); - if (ret) - return ret; - - nv_engine(priv)->cclass = &nouveau_perfmon_cclass; - nv_engine(priv)->sclass = nouveau_perfmon_sclass; - priv->base.last = 7; - return 0; -} - -struct nouveau_oclass -nve0_perfmon_oclass = { - .handle = NV_ENGINE(PERFMON, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = nvc0_perfmon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvf0.c deleted file mode 100644 index 47256f78a895..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/nvf0.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" - -/******************************************************************************* - * Perfmon object classes - ******************************************************************************/ - -/******************************************************************************* - * PPM context - ******************************************************************************/ - -/******************************************************************************* - * PPM engine/subdev functions - ******************************************************************************/ - -static int -nvf0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_perfmon_priv *priv; - int ret; - - ret = nouveau_perfmon_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, - nve0_perfmon_pwr); - if (ret) - return ret; - - nv_engine(priv)->cclass = &nouveau_perfmon_cclass; - nv_engine(priv)->sclass = nouveau_perfmon_sclass; - return 0; -} - -struct nouveau_oclass -nvf0_perfmon_oclass = { - .handle = NV_ENGINE(PERFMON, 0xf0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvf0_perfmon_ctor, - .dtor = _nouveau_perfmon_dtor, - .init = _nouveau_perfmon_init, - .fini = nvc0_perfmon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/priv.h deleted file mode 100644 index 0ac8714fe0ba..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/priv.h +++ /dev/null @@ -1,91 +0,0 @@ -#ifndef __NVKM_PERFMON_PRIV_H__ -#define __NVKM_PERFMON_PRIV_H__ - -#include - -struct nouveau_perfctr { - struct nouveau_object base; - struct list_head head; - struct nouveau_perfsig *signal[4]; - int slot; - u32 logic_op; - u32 clk; - u32 ctr; -}; - -extern struct nouveau_oclass nouveau_perfmon_sclass[]; - -struct nouveau_perfctx { - struct nouveau_engctx base; -}; - -extern struct nouveau_oclass nouveau_perfmon_cclass; - -struct nouveau_specsig { - u8 signal; - const char *name; -}; - -struct nouveau_perfsig { - const char *name; -}; - -struct nouveau_perfdom; -struct nouveau_perfctr * -nouveau_perfsig_wrap(struct nouveau_perfmon *, const char *, - struct nouveau_perfdom **); - -struct nouveau_specdom { - u16 signal_nr; - const struct nouveau_specsig *signal; - const struct nouveau_funcdom *func; -}; - -extern const struct nouveau_specdom nva3_perfmon_pwr[]; -extern const struct nouveau_specdom nvc0_perfmon_pwr[]; -extern const struct nouveau_specdom nve0_perfmon_pwr[]; - -struct nouveau_perfdom { - struct list_head head; - struct list_head list; - const struct nouveau_funcdom *func; - char name[32]; - u32 addr; - u8 quad; - u32 signal_nr; - struct nouveau_perfsig signal[]; -}; - -struct nouveau_funcdom { - void (*init)(struct nouveau_perfmon *, struct nouveau_perfdom *, - struct nouveau_perfctr *); - void (*read)(struct nouveau_perfmon *, struct nouveau_perfdom *, - struct nouveau_perfctr *); - void (*next)(struct nouveau_perfmon *, struct nouveau_perfdom *); -}; - -int nouveau_perfdom_new(struct nouveau_perfmon *, const char *, u32, - u32, u32, u32, const struct nouveau_specdom *); - -#define nouveau_perfmon_create(p,e,o,d) \ - nouveau_perfmon_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nouveau_perfmon_dtor(p) ({ \ - struct nouveau_perfmon *c = (p); \ - _nouveau_perfmon_dtor(nv_object(c)); \ -}) -#define nouveau_perfmon_init(p) ({ \ - struct nouveau_perfmon *c = (p); \ - _nouveau_perfmon_init(nv_object(c)); \ -}) -#define nouveau_perfmon_fini(p,s) ({ \ - struct nouveau_perfmon *c = (p); \ - _nouveau_perfmon_fini(nv_object(c), (s)); \ -}) - -int nouveau_perfmon_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -void _nouveau_perfmon_dtor(struct nouveau_object *); -int _nouveau_perfmon_init(struct nouveau_object *); -int _nouveau_perfmon_fini(struct nouveau_object *, bool); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild new file mode 100644 index 000000000000..fde0dc250b55 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild @@ -0,0 +1,9 @@ +nvkm-y += nvkm/engine/pm/base.o +nvkm-y += nvkm/engine/pm/daemon.o +nvkm-y += nvkm/engine/pm/nv40.o +nvkm-y += nvkm/engine/pm/nv50.o +nvkm-y += nvkm/engine/pm/nv84.o +nvkm-y += nvkm/engine/pm/nva3.o +nvkm-y += nvkm/engine/pm/nvc0.o +nvkm-y += nvkm/engine/pm/nve0.o +nvkm-y += nvkm/engine/pm/nvf0.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c new file mode 100644 index 000000000000..5efb308e5d1c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c @@ -0,0 +1,483 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include +#include +#include +#include + +#include + +#include "priv.h" + +#define QUAD_MASK 0x0f +#define QUAD_FREE 0x01 + +static struct nouveau_perfsig * +nouveau_perfsig_find_(struct nouveau_perfdom *dom, const char *name, u32 size) +{ + char path[64]; + int i; + + if (name[0] != '/') { + for (i = 0; i < dom->signal_nr; i++) { + if ( dom->signal[i].name && + !strncmp(name, dom->signal[i].name, size)) + return &dom->signal[i]; + } + } else { + for (i = 0; i < dom->signal_nr; i++) { + snprintf(path, sizeof(path), "/%s/%02x", dom->name, i); + if (!strncmp(name, path, size)) + return &dom->signal[i]; + } + } + + return NULL; +} + +struct nouveau_perfsig * +nouveau_perfsig_find(struct nouveau_pm *ppm, const char *name, u32 size, + struct nouveau_perfdom **pdom) +{ + struct nouveau_perfdom *dom = *pdom; + struct nouveau_perfsig *sig; + + if (dom == NULL) { + list_for_each_entry(dom, &ppm->domains, head) { + sig = nouveau_perfsig_find_(dom, name, size); + if (sig) { + *pdom = dom; + return sig; + } + } + + return NULL; + } + + return nouveau_perfsig_find_(dom, name, size); +} + +struct nouveau_perfctr * +nouveau_perfsig_wrap(struct nouveau_pm *ppm, const char *name, + struct nouveau_perfdom **pdom) +{ + struct nouveau_perfsig *sig; + struct nouveau_perfctr *ctr; + + sig = nouveau_perfsig_find(ppm, name, strlen(name), pdom); + if (!sig) + return NULL; + + ctr = kzalloc(sizeof(*ctr), GFP_KERNEL); + if (ctr) { + ctr->signal[0] = sig; + ctr->logic_op = 0xaaaa; + } + + return ctr; +} + +/******************************************************************************* + * Perfmon object classes + ******************************************************************************/ +static int +nouveau_perfctr_query(struct nouveau_object *object, void *data, u32 size) +{ + union { + struct nvif_perfctr_query_v0 v0; + } *args = data; + struct nouveau_device *device = nv_device(object); + struct nouveau_pm *ppm = (void *)object->engine; + struct nouveau_perfdom *dom = NULL, *chk; + const bool all = nouveau_boolopt(device->cfgopt, "NvPmShowAll", false); + const bool raw = nouveau_boolopt(device->cfgopt, "NvPmUnnamed", all); + const char *name; + int tmp = 0, di, si; + int ret; + + nv_ioctl(object, "perfctr query size %d\n", size); + if (nvif_unpack(args->v0, 0, 0, false)) { + nv_ioctl(object, "perfctr query vers %d iter %08x\n", + args->v0.version, args->v0.iter); + di = (args->v0.iter & 0xff000000) >> 24; + si = (args->v0.iter & 0x00ffffff) - 1; + } else + return ret; + + list_for_each_entry(chk, &ppm->domains, head) { + if (tmp++ == di) { + dom = chk; + break; + } + } + + if (dom == NULL || si >= (int)dom->signal_nr) + return -EINVAL; + + if (si >= 0) { + if (raw || !(name = dom->signal[si].name)) { + snprintf(args->v0.name, sizeof(args->v0.name), + "/%s/%02x", dom->name, si); + } else { + strncpy(args->v0.name, name, sizeof(args->v0.name)); + } + } + + do { + while (++si < dom->signal_nr) { + if (all || dom->signal[si].name) { + args->v0.iter = (di << 24) | ++si; + return 0; + } + } + si = -1; + di = di + 1; + dom = list_entry(dom->head.next, typeof(*dom), head); + } while (&dom->head != &ppm->domains); + + args->v0.iter = 0xffffffff; + return 0; +} + +static int +nouveau_perfctr_sample(struct nouveau_object *object, void *data, u32 size) +{ + union { + struct nvif_perfctr_sample none; + } *args = data; + struct nouveau_pm *ppm = (void *)object->engine; + struct nouveau_perfctr *ctr, *tmp; + struct nouveau_perfdom *dom; + int ret; + + nv_ioctl(object, "perfctr sample size %d\n", size); + if (nvif_unvers(args->none)) { + nv_ioctl(object, "perfctr sample\n"); + } else + return ret; + ppm->sequence++; + + list_for_each_entry(dom, &ppm->domains, head) { + /* sample previous batch of counters */ + if (dom->quad != QUAD_MASK) { + dom->func->next(ppm, dom); + tmp = NULL; + while (!list_empty(&dom->list)) { + ctr = list_first_entry(&dom->list, + typeof(*ctr), head); + if (ctr->slot < 0) break; + if ( tmp && tmp == ctr) break; + if (!tmp) tmp = ctr; + dom->func->read(ppm, dom, ctr); + ctr->slot = -1; + list_move_tail(&ctr->head, &dom->list); + } + } + + dom->quad = QUAD_MASK; + + /* setup next batch of counters for sampling */ + list_for_each_entry(ctr, &dom->list, head) { + ctr->slot = ffs(dom->quad) - 1; + if (ctr->slot < 0) + break; + dom->quad &= ~(QUAD_FREE << ctr->slot); + dom->func->init(ppm, dom, ctr); + } + + if (dom->quad != QUAD_MASK) + dom->func->next(ppm, dom); + } + + return 0; +} + +static int +nouveau_perfctr_read(struct nouveau_object *object, void *data, u32 size) +{ + union { + struct nvif_perfctr_read_v0 v0; + } *args = data; + struct nouveau_perfctr *ctr = (void *)object; + int ret; + + nv_ioctl(object, "perfctr read size %d\n", size); + if (nvif_unpack(args->v0, 0, 0, false)) { + nv_ioctl(object, "perfctr read vers %d\n", args->v0.version); + } else + return ret; + + if (!ctr->clk) + return -EAGAIN; + + args->v0.clk = ctr->clk; + args->v0.ctr = ctr->ctr; + return 0; +} + +static int +nouveau_perfctr_mthd(struct nouveau_object *object, u32 mthd, + void *data, u32 size) +{ + switch (mthd) { + case NVIF_PERFCTR_V0_QUERY: + return nouveau_perfctr_query(object, data, size); + case NVIF_PERFCTR_V0_SAMPLE: + return nouveau_perfctr_sample(object, data, size); + case NVIF_PERFCTR_V0_READ: + return nouveau_perfctr_read(object, data, size); + default: + break; + } + return -EINVAL; +} + +static void +nouveau_perfctr_dtor(struct nouveau_object *object) +{ + struct nouveau_perfctr *ctr = (void *)object; + if (ctr->head.next) + list_del(&ctr->head); + nouveau_object_destroy(&ctr->base); +} + +static int +nouveau_perfctr_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + union { + struct nvif_perfctr_v0 v0; + } *args = data; + struct nouveau_pm *ppm = (void *)engine; + struct nouveau_perfdom *dom = NULL; + struct nouveau_perfsig *sig[4] = {}; + struct nouveau_perfctr *ctr; + int ret, i; + + nv_ioctl(parent, "create perfctr size %d\n", size); + if (nvif_unpack(args->v0, 0, 0, false)) { + nv_ioctl(parent, "create perfctr vers %d logic_op %04x\n", + args->v0.version, args->v0.logic_op); + } else + return ret; + + for (i = 0; i < ARRAY_SIZE(args->v0.name) && args->v0.name[i][0]; i++) { + sig[i] = nouveau_perfsig_find(ppm, args->v0.name[i], + strnlen(args->v0.name[i], + sizeof(args->v0.name[i])), + &dom); + if (!sig[i]) + return -EINVAL; + } + + ret = nouveau_object_create(parent, engine, oclass, 0, &ctr); + *pobject = nv_object(ctr); + if (ret) + return ret; + + ctr->slot = -1; + ctr->logic_op = args->v0.logic_op; + ctr->signal[0] = sig[0]; + ctr->signal[1] = sig[1]; + ctr->signal[2] = sig[2]; + ctr->signal[3] = sig[3]; + if (dom) + list_add_tail(&ctr->head, &dom->list); + return 0; +} + +static struct nouveau_ofuncs +nouveau_perfctr_ofuncs = { + .ctor = nouveau_perfctr_ctor, + .dtor = nouveau_perfctr_dtor, + .init = nouveau_object_init, + .fini = nouveau_object_fini, + .mthd = nouveau_perfctr_mthd, +}; + +struct nouveau_oclass +nouveau_pm_sclass[] = { + { .handle = NVIF_IOCTL_NEW_V0_PERFCTR, + .ofuncs = &nouveau_perfctr_ofuncs, + }, + {}, +}; + +/******************************************************************************* + * PPM context + ******************************************************************************/ +static void +nouveau_perfctx_dtor(struct nouveau_object *object) +{ + struct nouveau_pm *ppm = (void *)object->engine; + mutex_lock(&nv_subdev(ppm)->mutex); + nouveau_engctx_destroy(&ppm->context->base); + ppm->context = NULL; + mutex_unlock(&nv_subdev(ppm)->mutex); +} + +static int +nouveau_perfctx_ctor(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nouveau_pm *ppm = (void *)engine; + struct nouveau_perfctx *ctx; + int ret; + + ret = nouveau_engctx_create(parent, engine, oclass, NULL, + 0, 0, 0, &ctx); + *pobject = nv_object(ctx); + if (ret) + return ret; + + mutex_lock(&nv_subdev(ppm)->mutex); + if (ppm->context == NULL) + ppm->context = ctx; + mutex_unlock(&nv_subdev(ppm)->mutex); + + if (ctx != ppm->context) + return -EBUSY; + + return 0; +} + +struct nouveau_oclass +nouveau_pm_cclass = { + .handle = NV_ENGCTX(PM, 0x00), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nouveau_perfctx_ctor, + .dtor = nouveau_perfctx_dtor, + .init = _nouveau_engctx_init, + .fini = _nouveau_engctx_fini, + }, +}; + +/******************************************************************************* + * PPM engine/subdev functions + ******************************************************************************/ +int +nouveau_perfdom_new(struct nouveau_pm *ppm, const char *name, u32 mask, + u32 base, u32 size_unit, u32 size_domain, + const struct nouveau_specdom *spec) +{ + const struct nouveau_specdom *sdom; + const struct nouveau_specsig *ssig; + struct nouveau_perfdom *dom; + int i; + + for (i = 0; i == 0 || mask; i++) { + u32 addr = base + (i * size_unit); + if (i && !(mask & (1 << i))) + continue; + + sdom = spec; + while (sdom->signal_nr) { + dom = kzalloc(sizeof(*dom) + sdom->signal_nr * + sizeof(*dom->signal), GFP_KERNEL); + if (!dom) + return -ENOMEM; + + if (mask) { + snprintf(dom->name, sizeof(dom->name), + "%s/%02x/%02x", name, i, + (int)(sdom - spec)); + } else { + snprintf(dom->name, sizeof(dom->name), + "%s/%02x", name, (int)(sdom - spec)); + } + + list_add_tail(&dom->head, &ppm->domains); + INIT_LIST_HEAD(&dom->list); + dom->func = sdom->func; + dom->addr = addr; + dom->quad = QUAD_MASK; + dom->signal_nr = sdom->signal_nr; + + ssig = (sdom++)->signal; + while (ssig->name) { + dom->signal[ssig->signal].name = ssig->name; + ssig++; + } + + addr += size_domain; + } + + mask &= ~(1 << i); + } + + return 0; +} + +int +_nouveau_pm_fini(struct nouveau_object *object, bool suspend) +{ + struct nouveau_pm *ppm = (void *)object; + return nouveau_engine_fini(&ppm->base, suspend); +} + +int +_nouveau_pm_init(struct nouveau_object *object) +{ + struct nouveau_pm *ppm = (void *)object; + return nouveau_engine_init(&ppm->base); +} + +void +_nouveau_pm_dtor(struct nouveau_object *object) +{ + struct nouveau_pm *ppm = (void *)object; + struct nouveau_perfdom *dom, *tmp; + + list_for_each_entry_safe(dom, tmp, &ppm->domains, head) { + list_del(&dom->head); + kfree(dom); + } + + nouveau_engine_destroy(&ppm->base); +} + +int +nouveau_pm_create_(struct nouveau_object *parent, + struct nouveau_object *engine, + struct nouveau_oclass *oclass, + int length, void **pobject) +{ + struct nouveau_pm *ppm; + int ret; + + ret = nouveau_engine_create_(parent, engine, oclass, true, "PPM", + "pm", length, pobject); + ppm = *pobject; + if (ret) + return ret; + + INIT_LIST_HEAD(&ppm->domains); + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c new file mode 100644 index 000000000000..1fd51b815707 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/daemon.c @@ -0,0 +1,109 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "priv.h" + +static void +pwr_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom, + struct nouveau_perfctr *ctr) +{ + u32 mask = 0x00000000; + u32 ctrl = 0x00000001; + int i; + + for (i = 0; i < ARRAY_SIZE(ctr->signal) && ctr->signal[i]; i++) + mask |= 1 << (ctr->signal[i] - dom->signal); + + nv_wr32(ppm, 0x10a504 + (ctr->slot * 0x10), mask); + nv_wr32(ppm, 0x10a50c + (ctr->slot * 0x10), ctrl); + nv_wr32(ppm, 0x10a50c + (ppm->last * 0x10), 0x00000003); +} + +static void +pwr_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom, + struct nouveau_perfctr *ctr) +{ + ctr->ctr = ppm->pwr[ctr->slot]; + ctr->clk = ppm->pwr[ppm->last]; +} + +static void +pwr_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom) +{ + int i; + + for (i = 0; i <= ppm->last; i++) { + ppm->pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10)); + nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x80000000); + } +} + +static const struct nouveau_funcdom +pwr_perfctr_func = { + .init = pwr_perfctr_init, + .read = pwr_perfctr_read, + .next = pwr_perfctr_next, +}; + +const struct nouveau_specdom +nva3_pm_pwr[] = { + { 0x20, (const struct nouveau_specsig[]) { + { 0x00, "pwr_gr_idle" }, + { 0x04, "pwr_bsp_idle" }, + { 0x05, "pwr_vp_idle" }, + { 0x06, "pwr_ppp_idle" }, + { 0x13, "pwr_ce0_idle" }, + {} + }, &pwr_perfctr_func }, + {} +}; + +const struct nouveau_specdom +nvc0_pm_pwr[] = { + { 0x20, (const struct nouveau_specsig[]) { + { 0x00, "pwr_gr_idle" }, + { 0x04, "pwr_bsp_idle" }, + { 0x05, "pwr_vp_idle" }, + { 0x06, "pwr_ppp_idle" }, + { 0x13, "pwr_ce0_idle" }, + { 0x14, "pwr_ce1_idle" }, + {} + }, &pwr_perfctr_func }, + {} +}; + +const struct nouveau_specdom +nve0_pm_pwr[] = { + { 0x20, (const struct nouveau_specsig[]) { + { 0x00, "pwr_gr_idle" }, + { 0x04, "pwr_bsp_idle" }, + { 0x05, "pwr_vp_idle" }, + { 0x06, "pwr_ppp_idle" }, + { 0x13, "pwr_ce0_idle" }, + { 0x14, "pwr_ce1_idle" }, + { 0x15, "pwr_ce2_idle" }, + {} + }, &pwr_perfctr_func }, + {} +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c new file mode 100644 index 000000000000..82a1777a3e11 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c @@ -0,0 +1,143 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nv40.h" + +/******************************************************************************* + * Perfmon object classes + ******************************************************************************/ + +/******************************************************************************* + * PPM context + ******************************************************************************/ + +/******************************************************************************* + * PPM engine/subdev functions + ******************************************************************************/ + +static void +nv40_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom, + struct nouveau_perfctr *ctr) +{ + struct nv40_pm_priv *priv = (void *)ppm; + struct nv40_pm_cntr *cntr = (void *)ctr; + u32 log = ctr->logic_op; + u32 src = 0x00000000; + int i; + + for (i = 0; i < 4 && ctr->signal[i]; i++) + src |= (ctr->signal[i] - dom->signal) << (i * 8); + + nv_wr32(priv, 0x00a7c0 + dom->addr, 0x00000001); + nv_wr32(priv, 0x00a400 + dom->addr + (cntr->base.slot * 0x40), src); + nv_wr32(priv, 0x00a420 + dom->addr + (cntr->base.slot * 0x40), log); +} + +static void +nv40_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom, + struct nouveau_perfctr *ctr) +{ + struct nv40_pm_priv *priv = (void *)ppm; + struct nv40_pm_cntr *cntr = (void *)ctr; + + switch (cntr->base.slot) { + case 0: cntr->base.ctr = nv_rd32(priv, 0x00a700 + dom->addr); break; + case 1: cntr->base.ctr = nv_rd32(priv, 0x00a6c0 + dom->addr); break; + case 2: cntr->base.ctr = nv_rd32(priv, 0x00a680 + dom->addr); break; + case 3: cntr->base.ctr = nv_rd32(priv, 0x00a740 + dom->addr); break; + } + cntr->base.clk = nv_rd32(priv, 0x00a600 + dom->addr); +} + +static void +nv40_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom) +{ + struct nv40_pm_priv *priv = (void *)ppm; + if (priv->sequence != ppm->sequence) { + nv_wr32(priv, 0x400084, 0x00000020); + priv->sequence = ppm->sequence; + } +} + +const struct nouveau_funcdom +nv40_perfctr_func = { + .init = nv40_perfctr_init, + .read = nv40_perfctr_read, + .next = nv40_perfctr_next, +}; + +static const struct nouveau_specdom +nv40_pm[] = { + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + {} +}; + +int +nv40_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nv40_pm_oclass *mclass = (void *)oclass; + struct nv40_pm_priv *priv; + int ret; + + ret = nouveau_pm_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + ret = nouveau_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms); + if (ret) + return ret; + + nv_engine(priv)->cclass = &nouveau_pm_cclass; + nv_engine(priv)->sclass = nouveau_pm_sclass; + return 0; +} + +struct nouveau_oclass * +nv40_pm_oclass = &(struct nv40_pm_oclass) { + .base.handle = NV_ENGINE(PM, 0x40), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv40_pm_ctor, + .dtor = _nouveau_pm_dtor, + .init = _nouveau_pm_init, + .fini = _nouveau_pm_fini, + }, + .doms = nv40_pm, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h new file mode 100644 index 000000000000..e83a0efd5d89 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h @@ -0,0 +1,26 @@ +#ifndef __NVKM_PM_NV40_H__ +#define __NVKM_PM_NV40_H__ + +#include "priv.h" + +struct nv40_pm_oclass { + struct nouveau_oclass base; + const struct nouveau_specdom *doms; +}; + +struct nv40_pm_priv { + struct nouveau_pm base; + u32 sequence; +}; + +int nv40_pm_ctor(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, void *data, u32 size, + struct nouveau_object **pobject); + +struct nv40_pm_cntr { + struct nouveau_perfctr base; +}; + +extern const struct nouveau_funcdom nv40_perfctr_func; + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c new file mode 100644 index 000000000000..db2f9a17abb5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c @@ -0,0 +1,70 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nv40.h" + +/******************************************************************************* + * Perfmon object classes + ******************************************************************************/ + +/******************************************************************************* + * PPM context + ******************************************************************************/ + +/******************************************************************************* + * PPM engine/subdev functions + ******************************************************************************/ + +static const struct nouveau_specdom +nv50_pm[] = { + { 0x040, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x100, (const struct nouveau_specsig[]) { + { 0xc8, "gr_idle" }, + {} + }, &nv40_perfctr_func }, + { 0x100, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x020, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x040, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + {} +}; + +struct nouveau_oclass * +nv50_pm_oclass = &(struct nv40_pm_oclass) { + .base.handle = NV_ENGINE(PM, 0x50), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv40_pm_ctor, + .dtor = _nouveau_pm_dtor, + .init = _nouveau_pm_init, + .fini = _nouveau_pm_fini, + }, + .doms = nv50_pm, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv84.c new file mode 100644 index 000000000000..37a4fc9c346b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv84.c @@ -0,0 +1,78 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nv40.h" + +/******************************************************************************* + * Perfmon object classes + ******************************************************************************/ + +/******************************************************************************* + * PPM context + ******************************************************************************/ + +/******************************************************************************* + * PPM engine/subdev functions + ******************************************************************************/ + +static const struct nouveau_specdom +nv84_pm[] = { + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + {} +}; + +struct nouveau_oclass * +nv84_pm_oclass = &(struct nv40_pm_oclass) { + .base.handle = NV_ENGINE(PM, 0x84), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nv40_pm_ctor, + .dtor = _nouveau_pm_dtor, + .init = _nouveau_pm_init, + .fini = _nouveau_pm_fini, + }, + .doms = nv84_pm, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nva3.c new file mode 100644 index 000000000000..d54dc57c4e61 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nva3.c @@ -0,0 +1,96 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nv40.h" + +/******************************************************************************* + * Perfmon object classes + ******************************************************************************/ + +/******************************************************************************* + * PPM context + ******************************************************************************/ + +/******************************************************************************* + * PPM engine/subdev functions + ******************************************************************************/ + +static const struct nouveau_specdom +nva3_pm[] = { + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + { 0x20, (const struct nouveau_specsig[]) { + {} + }, &nv40_perfctr_func }, + {} +}; + +static int +nva3_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **object) +{ + int ret = nv40_pm_ctor(parent, engine, oclass, data, size, object); + if (ret == 0) { + struct nv40_pm_priv *priv = (void *)*object; + ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, + nva3_pm_pwr); + if (ret) + return ret; + + priv->base.last = 3; + } + return ret; +} + +struct nouveau_oclass * +nva3_pm_oclass = &(struct nv40_pm_oclass) { + .base.handle = NV_ENGINE(PM, 0xa3), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nva3_pm_ctor, + .dtor = _nouveau_pm_dtor, + .init = _nouveau_pm_init, + .fini = _nouveau_pm_fini, + }, + .doms = nva3_pm, +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.c new file mode 100644 index 000000000000..fb00e82bbed0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.c @@ -0,0 +1,173 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nvc0.h" + +/******************************************************************************* + * Perfmon object classes + ******************************************************************************/ + +/******************************************************************************* + * PPM context + ******************************************************************************/ + +/******************************************************************************* + * PPM engine/subdev functions + ******************************************************************************/ + +static const struct nouveau_specdom +nvc0_pm_hub[] = { + {} +}; + +static const struct nouveau_specdom +nvc0_pm_gpc[] = { + {} +}; + +static const struct nouveau_specdom +nvc0_pm_part[] = { + {} +}; + +static void +nvc0_perfctr_init(struct nouveau_pm *ppm, struct nouveau_perfdom *dom, + struct nouveau_perfctr *ctr) +{ + struct nvc0_pm_priv *priv = (void *)ppm; + struct nvc0_pm_cntr *cntr = (void *)ctr; + u32 log = ctr->logic_op; + u32 src = 0x00000000; + int i; + + for (i = 0; i < 4 && ctr->signal[i]; i++) + src |= (ctr->signal[i] - dom->signal) << (i * 8); + + nv_wr32(priv, dom->addr + 0x09c, 0x00040002); + nv_wr32(priv, dom->addr + 0x100, 0x00000000); + nv_wr32(priv, dom->addr + 0x040 + (cntr->base.slot * 0x08), src); + nv_wr32(priv, dom->addr + 0x044 + (cntr->base.slot * 0x08), log); +} + +static void +nvc0_perfctr_read(struct nouveau_pm *ppm, struct nouveau_perfdom *dom, + struct nouveau_perfctr *ctr) +{ + struct nvc0_pm_priv *priv = (void *)ppm; + struct nvc0_pm_cntr *cntr = (void *)ctr; + + switch (cntr->base.slot) { + case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break; + case 1: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x088); break; + case 2: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x080); break; + case 3: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x090); break; + } + cntr->base.clk = nv_rd32(priv, dom->addr + 0x070); +} + +static void +nvc0_perfctr_next(struct nouveau_pm *ppm, struct nouveau_perfdom *dom) +{ + struct nvc0_pm_priv *priv = (void *)ppm; + nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27); + nv_wr32(priv, dom->addr + 0x0ec, 0x00000011); +} + +const struct nouveau_funcdom +nvc0_perfctr_func = { + .init = nvc0_perfctr_init, + .read = nvc0_perfctr_read, + .next = nvc0_perfctr_next, +}; + +int +nvc0_pm_fini(struct nouveau_object *object, bool suspend) +{ + struct nvc0_pm_priv *priv = (void *)object; + nv_mask(priv, 0x000200, 0x10000000, 0x00000000); + nv_mask(priv, 0x000200, 0x10000000, 0x10000000); + return nouveau_pm_fini(&priv->base, suspend); +} + +static int +nvc0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nvc0_pm_priv *priv; + u32 mask; + int ret; + + ret = nouveau_pm_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, + nvc0_pm_pwr); + if (ret) + return ret; + + /* HUB */ + ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200, + nvc0_pm_hub); + if (ret) + return ret; + + /* GPC */ + mask = (1 << nv_rd32(priv, 0x022430)) - 1; + mask &= ~nv_rd32(priv, 0x022504); + mask &= ~nv_rd32(priv, 0x022584); + + ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000, + 0x1000, 0x200, nvc0_pm_gpc); + if (ret) + return ret; + + /* PART */ + mask = (1 << nv_rd32(priv, 0x022438)) - 1; + mask &= ~nv_rd32(priv, 0x022548); + mask &= ~nv_rd32(priv, 0x0225c8); + + ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000, + 0x1000, 0x200, nvc0_pm_part); + if (ret) + return ret; + + nv_engine(priv)->cclass = &nouveau_pm_cclass; + nv_engine(priv)->sclass = nouveau_pm_sclass; + priv->base.last = 7; + return 0; +} + +struct nouveau_oclass +nvc0_pm_oclass = { + .handle = NV_ENGINE(PM, 0xc0), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_pm_ctor, + .dtor = _nouveau_pm_dtor, + .init = _nouveau_pm_init, + .fini = nvc0_pm_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.h new file mode 100644 index 000000000000..e0e0e02600d4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvc0.h @@ -0,0 +1,17 @@ +#ifndef __NVKM_PM_NVC0_H__ +#define __NVKM_PM_NVC0_H__ + +#include "priv.h" + +struct nvc0_pm_priv { + struct nouveau_pm base; +}; + +struct nvc0_pm_cntr { + struct nouveau_perfctr base; +}; + +extern const struct nouveau_funcdom nvc0_perfctr_func; +int nvc0_pm_fini(struct nouveau_object *, bool); + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nve0.c new file mode 100644 index 000000000000..11b17cced966 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nve0.c @@ -0,0 +1,162 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nvc0.h" + +/******************************************************************************* + * Perfmon object classes + ******************************************************************************/ + +/******************************************************************************* + * PPM context + ******************************************************************************/ + +/******************************************************************************* + * PPM engine/subdev functions + ******************************************************************************/ + +static const struct nouveau_specdom +nve0_pm_hub[] = { + { 0x60, (const struct nouveau_specsig[]) { + { 0x47, "hub00_user_0" }, + {} + }, &nvc0_perfctr_func }, + { 0x40, (const struct nouveau_specsig[]) { + { 0x27, "hub01_user_0" }, + {} + }, &nvc0_perfctr_func }, + { 0x60, (const struct nouveau_specsig[]) { + { 0x47, "hub02_user_0" }, + {} + }, &nvc0_perfctr_func }, + { 0x60, (const struct nouveau_specsig[]) { + { 0x47, "hub03_user_0" }, + {} + }, &nvc0_perfctr_func }, + { 0x40, (const struct nouveau_specsig[]) { + { 0x03, "host_mmio_rd" }, + { 0x27, "hub04_user_0" }, + {} + }, &nvc0_perfctr_func }, + { 0x60, (const struct nouveau_specsig[]) { + { 0x47, "hub05_user_0" }, + {} + }, &nvc0_perfctr_func }, + { 0xc0, (const struct nouveau_specsig[]) { + { 0x74, "host_fb_rd3x" }, + { 0x75, "host_fb_rd3x_2" }, + { 0xa7, "hub06_user_0" }, + {} + }, &nvc0_perfctr_func }, + { 0x60, (const struct nouveau_specsig[]) { + { 0x47, "hub07_user_0" }, + {} + }, &nvc0_perfctr_func }, + {} +}; + +static const struct nouveau_specdom +nve0_pm_gpc[] = { + { 0xe0, (const struct nouveau_specsig[]) { + { 0xc7, "gpc00_user_0" }, + {} + }, &nvc0_perfctr_func }, + {} +}; + +static const struct nouveau_specdom +nve0_pm_part[] = { + { 0x60, (const struct nouveau_specsig[]) { + { 0x47, "part00_user_0" }, + {} + }, &nvc0_perfctr_func }, + { 0x60, (const struct nouveau_specsig[]) { + { 0x47, "part01_user_0" }, + {} + }, &nvc0_perfctr_func }, + {} +}; + +static int +nve0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nvc0_pm_priv *priv; + u32 mask; + int ret; + + ret = nouveau_pm_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + /* PDAEMON */ + ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, + nve0_pm_pwr); + if (ret) + return ret; + + /* HUB */ + ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200, + nve0_pm_hub); + if (ret) + return ret; + + /* GPC */ + mask = (1 << nv_rd32(priv, 0x022430)) - 1; + mask &= ~nv_rd32(priv, 0x022504); + mask &= ~nv_rd32(priv, 0x022584); + + ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000, + 0x1000, 0x200, nve0_pm_gpc); + if (ret) + return ret; + + /* PART */ + mask = (1 << nv_rd32(priv, 0x022438)) - 1; + mask &= ~nv_rd32(priv, 0x022548); + mask &= ~nv_rd32(priv, 0x0225c8); + + ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000, + 0x1000, 0x200, nve0_pm_part); + if (ret) + return ret; + + nv_engine(priv)->cclass = &nouveau_pm_cclass; + nv_engine(priv)->sclass = nouveau_pm_sclass; + priv->base.last = 7; + return 0; +} + +struct nouveau_oclass +nve0_pm_oclass = { + .handle = NV_ENGINE(PM, 0xe0), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nve0_pm_ctor, + .dtor = _nouveau_pm_dtor, + .init = _nouveau_pm_init, + .fini = nvc0_pm_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvf0.c new file mode 100644 index 000000000000..7d5a8dddae9d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/nvf0.c @@ -0,0 +1,71 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include "nvc0.h" + +/******************************************************************************* + * Perfmon object classes + ******************************************************************************/ + +/******************************************************************************* + * PPM context + ******************************************************************************/ + +/******************************************************************************* + * PPM engine/subdev functions + ******************************************************************************/ + +static int +nvf0_pm_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *oclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nvc0_pm_priv *priv; + int ret; + + ret = nouveau_pm_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, + nve0_pm_pwr); + if (ret) + return ret; + + nv_engine(priv)->cclass = &nouveau_pm_cclass; + nv_engine(priv)->sclass = nouveau_pm_sclass; + return 0; +} + +struct nouveau_oclass +nvf0_pm_oclass = { + .handle = NV_ENGINE(PM, 0xf0), + .ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvf0_pm_ctor, + .dtor = _nouveau_pm_dtor, + .init = _nouveau_pm_init, + .fini = nvc0_pm_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h new file mode 100644 index 000000000000..af3938fb19e0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h @@ -0,0 +1,91 @@ +#ifndef __NVKM_PM_PRIV_H__ +#define __NVKM_PM_PRIV_H__ + +#include + +struct nouveau_perfctr { + struct nouveau_object base; + struct list_head head; + struct nouveau_perfsig *signal[4]; + int slot; + u32 logic_op; + u32 clk; + u32 ctr; +}; + +extern struct nouveau_oclass nouveau_pm_sclass[]; + +struct nouveau_perfctx { + struct nouveau_engctx base; +}; + +extern struct nouveau_oclass nouveau_pm_cclass; + +struct nouveau_specsig { + u8 signal; + const char *name; +}; + +struct nouveau_perfsig { + const char *name; +}; + +struct nouveau_perfdom; +struct nouveau_perfctr * +nouveau_perfsig_wrap(struct nouveau_pm *, const char *, + struct nouveau_perfdom **); + +struct nouveau_specdom { + u16 signal_nr; + const struct nouveau_specsig *signal; + const struct nouveau_funcdom *func; +}; + +extern const struct nouveau_specdom nva3_pm_pwr[]; +extern const struct nouveau_specdom nvc0_pm_pwr[]; +extern const struct nouveau_specdom nve0_pm_pwr[]; + +struct nouveau_perfdom { + struct list_head head; + struct list_head list; + const struct nouveau_funcdom *func; + char name[32]; + u32 addr; + u8 quad; + u32 signal_nr; + struct nouveau_perfsig signal[]; +}; + +struct nouveau_funcdom { + void (*init)(struct nouveau_pm *, struct nouveau_perfdom *, + struct nouveau_perfctr *); + void (*read)(struct nouveau_pm *, struct nouveau_perfdom *, + struct nouveau_perfctr *); + void (*next)(struct nouveau_pm *, struct nouveau_perfdom *); +}; + +int nouveau_perfdom_new(struct nouveau_pm *, const char *, u32, + u32, u32, u32, const struct nouveau_specdom *); + +#define nouveau_pm_create(p,e,o,d) \ + nouveau_pm_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nouveau_pm_dtor(p) ({ \ + struct nouveau_pm *c = (p); \ + _nouveau_pm_dtor(nv_object(c)); \ +}) +#define nouveau_pm_init(p) ({ \ + struct nouveau_pm *c = (p); \ + _nouveau_pm_init(nv_object(c)); \ +}) +#define nouveau_pm_fini(p,s) ({ \ + struct nouveau_pm *c = (p); \ + _nouveau_pm_fini(nv_object(c), (s)); \ +}) + +int nouveau_pm_create_(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, int, void **); +void _nouveau_pm_dtor(struct nouveau_object *); +int _nouveau_pm_init(struct nouveau_object *); +int _nouveau_pm_fini(struct nouveau_object *, bool); + +#endif