From: Zhenyu Wang Date: Mon, 19 Mar 2018 09:09:05 +0000 (+0800) Subject: drm/i915/gvt: force to set all context control bits from guest X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=d8303075699292008ae5b2c8fc728d455b994c26;p=openwrt%2Fstaging%2Fblogic.git drm/i915/gvt: force to set all context control bits from guest Our shadow context content is from guest but with masked control reg like CTX_CONTEXT_CONTROL, we need to make sure all settings from guest would be set when this context is on hw, this trys to force mask enable bits for all to ensure every bits setting would be effective on hw. One regression found related to once inhibit bit is set, gpu engine are working on inhibit state until MI_LOAD_REG_IMM command or context image clear inhibit bit with mask bit set to 1, and val bit set to 0. In gvt-g currently workload has the highest priority, so gvt-g workload could trigger preempt context easily, preempt context set inhibit bit, then gvt-g workload is scheduled in, but gvt-g workload shadow context image usually doesn't set inhibit mask bit, so gpu is still in inhibit state when gvt workload is running. This caused gpu hang. Suggested-by: Zhang, Xiong Signed-off-by: Zhenyu Wang Reviewed-by: Zhang, Xiong --- diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 1127bd77fc6e..a55b4975c154 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -124,8 +124,14 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload) #define COPY_REG(name) \ intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) +#define COPY_REG_MASKED(name) {\ + intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ + + RING_CTX_OFF(name.val),\ + &shadow_ring_context->name.val, 4);\ + shadow_ring_context->name.val |= 0xffff << 16;\ + } - COPY_REG(ctx_ctrl); + COPY_REG_MASKED(ctx_ctrl); COPY_REG(ctx_timestamp); if (ring_id == RCS) { @@ -134,6 +140,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload) COPY_REG(rcs_indirect_ctx_offset); } #undef COPY_REG +#undef COPY_REG_MASKED intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa +