From: Zoltan HERPAI Date: Fri, 22 Sep 2023 17:47:01 +0000 (+0200) Subject: sifiveu: remove upstreamed patches, refresh remaining ones X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=d9a8747a3dd7608c1ace77a85fb38e43c497129c;p=openwrt%2Fstaging%2Frobimarko.git sifiveu: remove upstreamed patches, refresh remaining ones Upstreamed: 0002-riscv-sifive-unmatched-update-regulators-values.patch 0003-riscv-sifive-unmatched-define-PWM-LEDs.patch 0006-riscv-sbi-srst-support.patch Compile-tested: HiFive Unleashed / Unmatched Runtime-tested: HiFive Unleashed / Unmatched Signed-off-by: Zoltan HERPAI --- diff --git a/target/linux/sifiveu/patches-6.1/0002-riscv-sifive-unmatched-update-regulators-values.patch b/target/linux/sifiveu/patches-6.1/0002-riscv-sifive-unmatched-update-regulators-values.patch deleted file mode 100644 index ac316e9d9b..0000000000 --- a/target/linux/sifiveu/patches-6.1/0002-riscv-sifive-unmatched-update-regulators-values.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 657819ff477dd73cd71075609698aa57ba098d8c Mon Sep 17 00:00:00 2001 -From: David Abdurachmanov -Date: Wed, 15 Sep 2021 07:10:02 -0700 -Subject: [PATCH 2/7] riscv: sifive: unmatched: update regulators values - -These are the regulators values from the schematics for Rev3{A,B} boards. - -Note this is not fully correct as bcore1/bcore2 and bmem/bio are merged, but -it's only supported in v5.15 kernel. See: - -541ee8f640327f951e7039278057827322231ab0 ("regulator: da9063: Add support for -full-current mode.") - -This will be changed for v5.15 kernel based on the patch above. - -Signed-off-by: David Abdurachmanov ---- - .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 32 +++++++++++----------- - 1 file changed, 16 insertions(+), 16 deletions(-) - ---- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -@@ -73,16 +73,16 @@ - - regulators { - vdd_bcore1: bcore1 { -- regulator-min-microvolt = <900000>; -- regulator-max-microvolt = <900000>; -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; - regulator-min-microamp = <5000000>; - regulator-max-microamp = <5000000>; - regulator-always-on; - }; - - vdd_bcore2: bcore2 { -- regulator-min-microvolt = <900000>; -- regulator-max-microvolt = <900000>; -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; - regulator-min-microamp = <5000000>; - regulator-max-microamp = <5000000>; - regulator-always-on; -@@ -137,48 +137,48 @@ - }; - - vdd_ldo3: ldo3 { -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; - regulator-always-on; - }; - - vdd_ldo4: ldo4 { -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <2500000>; -+ regulator-max-microvolt = <2500000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; - regulator-always-on; - }; - - vdd_ldo5: ldo5 { -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; - regulator-min-microamp = <100000>; - regulator-max-microamp = <100000>; - regulator-always-on; - }; - - vdd_ldo6: ldo6 { -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; - regulator-always-on; - }; - - vdd_ldo7: ldo7 { -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; - regulator-always-on; - }; - - vdd_ldo8: ldo8 { -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; - regulator-always-on; diff --git a/target/linux/sifiveu/patches-6.1/0003-riscv-sifive-unmatched-define-PWM-LEDs.patch b/target/linux/sifiveu/patches-6.1/0003-riscv-sifive-unmatched-define-PWM-LEDs.patch deleted file mode 100644 index 661e15905f..0000000000 --- a/target/linux/sifiveu/patches-6.1/0003-riscv-sifive-unmatched-define-PWM-LEDs.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 2c2d8ac8c124a2938c9326c14b2dffd46d76b4a8 Mon Sep 17 00:00:00 2001 -From: David Abdurachmanov -Date: Mon, 13 Sep 2021 02:15:37 -0700 -Subject: [PATCH 3/7] riscv: sifive: unmatched: define PWM LEDs - -Add D2 (RGB) and D12 (green) LEDs for SiFive Unmatched board. - -Signed-off-by: David Abdurachmanov ---- - .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 41 ++++++++++++++++++++++ - 1 file changed, 41 insertions(+) - ---- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -@@ -4,6 +4,8 @@ - #include "fu740-c000.dtsi" - #include - #include -+#include -+#include - - /* Clock frequency (in Hz) of the PCB crystal for rtcclk */ - #define RTCCLK_FREQ 1000000 -@@ -31,6 +33,45 @@ - soc { - }; - -+ pwmleds { -+ compatible = "pwm-leds"; -+ green-d12 { -+ label = "green:d12"; -+ color = ; -+ pwms = <&pwm0 0 7812500 PWM_POLARITY_INVERTED>; -+ active-low = <1>; -+ max-brightness = <255>; -+ linux,default-trigger = "none"; -+ }; -+ -+ green-d2 { -+ label = "green:d2"; -+ color = ; -+ pwms = <&pwm0 1 7812500 PWM_POLARITY_INVERTED>; -+ active-low = <1>; -+ max-brightness = <255>; -+ linux,default-trigger = "none"; -+ }; -+ -+ red-d2 { -+ label = "red:d2"; -+ color = ; -+ pwms = <&pwm0 2 7812500 PWM_POLARITY_INVERTED>; -+ active-low = <1>; -+ max-brightness = <255>; -+ linux,default-trigger = "none"; -+ }; -+ -+ blue-d2 { -+ label = "blue:d2"; -+ color = ; -+ pwms = <&pwm0 3 7812500 PWM_POLARITY_INVERTED>; -+ active-low = <1>; -+ max-brightness = <255>; -+ linux,default-trigger = "none"; -+ }; -+ }; -+ - hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; diff --git a/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch b/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch index 6d09628cb3..07170d7c76 100644 --- a/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch +++ b/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch @@ -12,9 +12,9 @@ Signed-off-by: David Abdurachmanov --- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts +++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -@@ -85,6 +85,11 @@ - clock-frequency = ; - clock-output-names = "rtcclk"; +@@ -86,6 +86,11 @@ + }; + }; }; + + gpio-poweroff { diff --git a/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch b/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch index c6b997dbbe..c4242c6f07 100644 --- a/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch +++ b/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch @@ -14,9 +14,9 @@ Signed-off-by: David Abdurachmanov --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig -@@ -566,6 +566,14 @@ config BUILTIN_DTB - depends on OF - default y if XIP_KERNEL +@@ -711,6 +711,14 @@ config PORTABLE + select OF + select MMU +menu "CPU Power Management" + @@ -35,7 +35,7 @@ Signed-off-by: David Abdurachmanov i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; -+ clocks = <&prci PRCI_CLK_COREPLL>; ++ clocks = <&prci FU540_PRCI_CLK_COREPLL>; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -43,7 +43,7 @@ Signed-off-by: David Abdurachmanov reg = <1>; riscv,isa = "rv64imafdc"; tlb-split; -+ clocks = <&prci PRCI_CLK_COREPLL>; ++ clocks = <&prci FU540_PRCI_CLK_COREPLL>; next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; @@ -51,7 +51,7 @@ Signed-off-by: David Abdurachmanov reg = <2>; riscv,isa = "rv64imafdc"; tlb-split; -+ clocks = <&prci PRCI_CLK_COREPLL>; ++ clocks = <&prci FU540_PRCI_CLK_COREPLL>; next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; @@ -59,7 +59,7 @@ Signed-off-by: David Abdurachmanov reg = <3>; riscv,isa = "rv64imafdc"; tlb-split; -+ clocks = <&prci PRCI_CLK_COREPLL>; ++ clocks = <&prci FU540_PRCI_CLK_COREPLL>; next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; @@ -67,13 +67,13 @@ Signed-off-by: David Abdurachmanov reg = <4>; riscv,isa = "rv64imafdc"; tlb-split; -+ clocks = <&prci PRCI_CLK_COREPLL>; ++ clocks = <&prci FU540_PRCI_CLK_COREPLL>; next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts -@@ -84,6 +84,40 @@ +@@ -80,6 +80,40 @@ label = "d4"; }; }; diff --git a/target/linux/sifiveu/patches-6.1/0006-riscv-sbi-srst-support.patch b/target/linux/sifiveu/patches-6.1/0006-riscv-sbi-srst-support.patch deleted file mode 100644 index 409001bcfa..0000000000 --- a/target/linux/sifiveu/patches-6.1/0006-riscv-sbi-srst-support.patch +++ /dev/null @@ -1,301 +0,0 @@ -From mboxrd@z Thu Jan 1 00:00:00 1970 -Return-Path: -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -X-Spam-Level: -X-Spam-Status: No, score=-21.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, - DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, - INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,MSGID_FROM_MTA_HEADER, - SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable - autolearn_force=no version=3.4.0 -Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) - by smtp.lore.kernel.org (Postfix) with ESMTP id 9A34CC48BCD - for ; Wed, 9 Jun 2021 12:50:08 +0000 (UTC) -Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by mail.kernel.org (Postfix) with ESMTPS id 69795611C9 - for ; Wed, 9 Jun 2021 12:50:08 +0000 (UTC) -DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 69795611C9 -Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com -Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org -DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; - d=lists.infradead.org; s=bombadil.20210309; h=Sender: - Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: - List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: - Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: - Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: - List-Owner; bh=64gRxQ9bX8C6wjLq0KuJ2lv98bQdXijt0LPnNpch3NU=; b=rgeSpoSWQ+Nca2 - 9PLsgI7dOYVdTu48CyVJStiizsvIvVFN2rBAgELHF2nRCCtoSiPMxgcpCKtDcm7sh9lC8AblCoBjN - LXiPRHVYJAcRNiWiQ0qOTqHdTbezFdzSjNOs6drbaiI4B8AZtychw1hP+ubsb5czAaz6510OEVct/ - h5M4Tlljcn/WIyulBd/tnuUOZPT0XL6rb2+TvRQvjXDBFHN+bWqP8OjXKnE1FTvy5MF8OTlUgI6wr - 3f4t/eS/PPbtXRD5raJzEwEQLJ6XY6NJABs40tKpWZNuUaqTfmonNdbP9y1htWhByhsAk+fw5WK/C - /KocvM6IzPmqGIBWcTdQ==; -Received: from localhost ([::1] helo=bombadil.infradead.org) - by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) - id 1lqxeS-00Do8i-Hj; Wed, 09 Jun 2021 12:49:44 +0000 -Received: from esa4.hgst.iphmx.com ([216.71.154.42]) - by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) - id 1lqx5h-00DbCQ-K0 - for linux-riscv@lists.infradead.org; Wed, 09 Jun 2021 12:13:51 +0000 -DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; - d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; - t=1623240829; x=1654776829; - h=from:to:cc:subject:date:message-id:in-reply-to: - references:content-transfer-encoding:mime-version; - bh=s4va/Owvq7MQI8rUsD/e02RmaYfJNzYNcxlXspGRY7g=; - b=G5GD9eN+rv669E7jyRnRAt0jw83CxhIrSiDIjXuPmhWyMhKeQGD7ACRm - ii6o0zmOREhGihtwB6X/xpY/2ZvK+cxcHmJXa+Ykyn8QN+/YKFtg3svfj - eiTN7U/mEozCoGNd1wXu59RQj11Xz60DN/qEUlYFaL6SjukUgifFVgbvG - uUj8AM8+xf1jKHi3Q/6nVPpJX8uiW/NPFHrwI8hxUwYr9viQwxXvc7FNr - fR8bH2c/HiGacGYEHosgP0WT//d9Huqn4JNINvjidK4ZSJ74cXlr8KwMG - 8snmfx4UjEWMhK1lCYalJEU7nxXFfih/6DMuFRorETpWQ+424BAKUJdDH Q==; -IronPort-SDR: pYhRsIZkhfmi45K4HfnZj39kxfUGpxs1e+q+Wh8kDE+ySh35HkJaaUcpP04mb7VeIVtPRx/h6Q - imv6sn8fYo/V8ezHAq4jpd1QadqInKi1ubLnCE3Zy7GnhVBepoV6FbI14Y01V+5QIUwYdFNcGG - RsxDOTQyU5AljH0Rc6WkrpdVf5jsrXXMddmlDdi6QsfKGy7MwQ/NYojNIqyLhRSgu5w2uTIE7X - atSbjb8j2a+EJUY0WgYTGfNHKCdQLAhjcsWZgU7Iu0vSaBU6A7seCkqun24dvF/zYuzEj7wedD - TvE= -X-IronPort-AV: E=Sophos;i="5.83,260,1616428800"; d="scan'208";a="170575129" -Received: from mail-dm6nam12lp2169.outbound.protection.outlook.com (HELO - NAM12-DM6-obe.outbound.protection.outlook.com) ([104.47.59.169]) - by ob1.hgst.iphmx.com with ESMTP; 09 Jun 2021 20:13:48 +0800 -ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; - b=hrlr4Qi66FmbQW45zI7QeA9nEYSvxO+tR++vUyFHxjRqnr6WtjKgHM8hPpp8oHXaK82U0+KQUc2+WjLbe8LihexXFQs5zRwBDwuArmkKt85cL3utD3OBzTkr4A9ZhRS5mzztnn9kvTFNplPjSydXPetJQIZ9WKmihJrdeaGQ+zQ//6TdDWVpLyBbqiBVUbUwlKQbpbbfHvzQCHYQbIiUcGn4vaSXYp2Xp1Z5yYVtrfDK+TemKG/8fKQoJjg/tdmDtQ97Cgw7nX6Oc9kdmoTIxFilMy4XjPciPcNOPdLmboGCt6+TMBeftLc1VFNnr7PwuxOogv4I7eJ/P9UaK57k5A== -ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; - s=arcselector9901; - h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; - bh=Ibi36Vj2s7bu56DZaU1uSl4xNA3OB2FHlI/rBKn+8xo=; - b=CE3o+0GFLPMQuw0AK1IRf/vX00diXsjayn0MmpS7ntSVXgxXIAPT9aDtk7x0NovJBTk2LHI5Mtxvz6SwVnJzUqZmNsXUktEj5Iwdd8EPIIxgCOjugo/6WC0FqaFKNvJB4hQ0tjFxv+J5DexSJ8+mPx6Ucr4DwtUXrCWzOeXyF5YK68mU5FgttbyutW3CGsGkPgaPAdOxXOgJqyYu8X25unmzG12Jq2xC4oVKsbA+RfDiaMKm97q2Bhy+LcgJNS6/ktlFKSOVu1HQ0POYgba3mtldN3vg73wLbxrfsdoe4261aJpkM05GJFDzdTNp4t3rEGhNuLR1+8OmKfLlPeSU9w== -ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass - smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass - header.d=wdc.com; arc=none -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; - d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; - h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; - bh=Ibi36Vj2s7bu56DZaU1uSl4xNA3OB2FHlI/rBKn+8xo=; - b=Z76YsVxTHK6/ta19C5vwaBPYmtDa2GIM/ml4myQZfIaHFNzXPzZ+PFcYy/Xf1Ixd0GZHcuSZQYgs/SPHWATh+rOWBAislGv1zmSAG/g0tiDckB8WaCwh1e3qGW4ZmUTmAU7dxB0vn0pRSLTnc1hdCUZ73buM78qo9qwsQZv41d0= -Authentication-Results: dabbelt.com; dkim=none (message not signed) - header.d=none;dabbelt.com; dmarc=none action=none header.from=wdc.com; -Received: from CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) - by CO6PR04MB7794.namprd04.prod.outlook.com (2603:10b6:303:13f::7) - with Microsoft SMTP Server (version=TLS1_2, - cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.21; Wed, 9 Jun - 2021 12:13:47 +0000 -Received: from CO6PR04MB7812.namprd04.prod.outlook.com - ([fe80::a153:b7f8:c87f:89f8]) by CO6PR04MB7812.namprd04.prod.outlook.com - ([fe80::a153:b7f8:c87f:89f8%9]) with mapi id 15.20.4219.021; Wed, 9 Jun 2021 - 12:13:47 +0000 -From: Anup Patel -To: Palmer Dabbelt , - Palmer Dabbelt , - Paul Walmsley , Albert Ou -Cc: Atish Patra , - Alistair Francis , - Anup Patel , linux-riscv@lists.infradead.org, - linux-kernel@vger.kernel.org, Anup Patel -Subject: [PATCH v7 1/1] RISC-V: Use SBI SRST extension when available -Date: Wed, 9 Jun 2021 17:43:22 +0530 -Message-Id: <20210609121322.3058-2-anup.patel@wdc.com> -X-Mailer: git-send-email 2.25.1 -In-Reply-To: <20210609121322.3058-1-anup.patel@wdc.com> -References: <20210609121322.3058-1-anup.patel@wdc.com> -X-Originating-IP: [122.172.176.125] -X-ClientProxiedBy: MA1PR0101CA0036.INDPRD01.PROD.OUTLOOK.COM - (2603:1096:a00:22::22) To CO6PR04MB7812.namprd04.prod.outlook.com - (2603:10b6:303:138::6) -MIME-Version: 1.0 -X-MS-Exchange-MessageSentRepresentingType: 1 -Received: from wdc.com (122.172.176.125) by - MA1PR0101CA0036.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::22) with - Microsoft SMTP Server (version=TLS1_2, - cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.21 via Frontend - Transport; Wed, 9 Jun 2021 12:13:44 +0000 -X-MS-PublicTrafficType: Email -X-MS-Office365-Filtering-Correlation-Id: 17406ef0-e8d7-4dc3-eee9-08d92b40085b -X-MS-TrafficTypeDiagnostic: CO6PR04MB7794: -X-MS-Exchange-Transport-Forked: True -X-Microsoft-Antispam-PRVS: -WDCIPOUTBOUND: EOP-TRUE -X-MS-Oob-TLC-OOBClassifiers: OLM:2887; -X-MS-Exchange-SenderADCheck: 1 -X-Microsoft-Antispam: BCL:0; -X-Microsoft-Antispam-Message-Info: IxB9oKL9LkeXCQ7mZ1A5qIcKlICr/TPZ/8V0ErM5hbqnvfK6Mf0mQL0tqqlJAOvLpCEVIyX7FllGqSlWsNG3ik/WbbDYQb9wAFCuFSAlGAeGppnJjJf0zfDAmp4NONB7kshKqtUYfGltTHTkV4ni+VEwWf/Q3T4vA0k3Jkt34iZFi9tOsSHkSWxPTsQyviBdCp3/36ZCVhYs6bXkf8sh0sA4Ql/l8t2zpcEUwjAm14ie3hOUBEp1W9qOz6StmR4xyl+zy49U38byeHu5XDF/qFT8FI4WclwFwxbDeTm8cU7MMg4D0xeR0Ytm2wVrgAdiapgQYLmxPIjIG96TRTbCupyuaJXmYcI6/x27PtiQYFwcpbRUjXDKRVX2WW74WHm88OOlTexD/OsbGHD6PVnc+InniK38yNcx06U9fIkDGSYWrJqLysALlO0V5gfkc35Fhttum638ES0S2sldGkFufM372EZeooczK7jeLMpoOTAnaLtPdTCGsHnnEDDbOK7NiptQlrLMhrNQ/70harAMmB6Vvdl+jvJi34DsuX+57WeQU8Ya1cyVxzFkWX2DwvPRsAnp/VNHzeQLc5MAIUYpwQvkJBcqihYMKrLMNOT94HmxBYmY2bcW/K9fXrPQ/whyJ5HoQuxydeiy7+QKg6FWnhguTACaaTKGKKIDIlfYA5FXYlZOaQ2iJFtiZP1GbxQnDEwz4SfGgCgBdiwqFm1NfGG7wRhqQa/Kgp3jBTHwaysCwcWu/Xdz/yiCV4lfQD/PTiOr5hmtld29G7WVDy9m6Q== -X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; - IPV:NLI; SFV:NSPM; H:CO6PR04MB7812.namprd04.prod.outlook.com; PTR:; CAT:NONE; - SFS:(4636009)(396003)(39860400002)(136003)(346002)(366004)(376002)(8676002)(316002)(55236004)(38100700002)(38350700002)(110136005)(86362001)(54906003)(4326008)(956004)(966005)(478600001)(26005)(186003)(55016002)(8936002)(2616005)(7696005)(52116002)(16526019)(5660300002)(8886007)(6666004)(1076003)(66476007)(66556008)(36756003)(66946007)(83380400001)(2906002)(44832011); - DIR:OUT; SFP:1102; -X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 -X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?2kfiFAcyFkAMcwkoCUqJGxdVnwsuTm5WWTXA4Pq0ZNAjWsfYI4MNugTA9f8C?= - =?us-ascii?Q?WaQrYEizTkvIlgRDqeKVRS0vaMaeU9XaSzO6UAJMnd0jY3BzkJgKUU9xj1aU?= - =?us-ascii?Q?vmwXKxCS+vZ2VKgLifaU1JCeemiJqV9aW+6AJEycq722bz9yXmcaJsaHWtX3?= - =?us-ascii?Q?4sSoLeVPvfzwzDZEEoGsZZi1G7inY2imGEgY/r3m5/qYvavJQ3An4e4sjEqZ?= - =?us-ascii?Q?Z4a4FAd/6c3X8cjmNwGvgWoAIM5WaJYFQe30MQ79alCUfZyiKB4tR0+5OGFd?= - =?us-ascii?Q?P/rQ169Z644JNKKcEabikpL7qZZJ6OMPTS7XR9x/7GzWOJ7soV3/3I2tfCdi?= - =?us-ascii?Q?xVsOK1DRF4y6gi5udvnb+Uu1U5wC1NlT0U/+TrnTSeY/IuLmMgFUysw+fQ+D?= - =?us-ascii?Q?DIVN44TKrMoEZKx9SKcx4jYpUGYvaCH4sVOAx3zWQC0Oz1Nz3/a/isywpQW9?= - =?us-ascii?Q?1I1kl/2N97K0EoWIPf6qPjyLVWXg1dOHfk6SjNW64JIIPUNnM3h7k2igDX3o?= - =?us-ascii?Q?d7lWyFfzoWhNC7opS71uzta+ti8aHxo+xzvYvf2wLb+fdyEP9t+oQVrEQYIW?= - =?us-ascii?Q?rAUKPqjEfAZOYBB28SaabfVt/QF6hFfV/0yJ/JV/Ie8ivC1t6iO+QZQscV7K?= - =?us-ascii?Q?d4Pg+xVSE+m+LsgNwO36cTTe6hSLBPnWU1NMOW2cxTRKGm0Lwd2HyjyKTBMD?= - =?us-ascii?Q?BcnKo9GXAVgOAGCG5cwEBN76q6sXxbWy0pjni3O2bLYBg4CIYCB/JNzOIfE0?= - =?us-ascii?Q?Toz6Qwc4aw5NxRLqz9IygGT6ZunRVUWUsgJrIt5U20elX+lRmtX1cqrQNTON?= - =?us-ascii?Q?ZHzuAI587pB0zK4EiS25hc9C8RtwjlY67heuMsYZDww5TU+NV3+0WN1/NrCX?= - =?us-ascii?Q?3kB7O188tvm1sWVhCaC6hk9s19nKGRgMS5OHXTMxhmyw1Dn/zorMYff3r9ZE?= - =?us-ascii?Q?sNiBI7fwru/Jsxt2/jNCpFaEYUa9JkrdSse76BXo/UxLALnxO3bzpym3Dq+T?= - =?us-ascii?Q?s4uEA8UncKM0e+Mhp9hW1c3DR61Qjj8wb+LV3XB0qYK/1rHs8IDdJ97tw1fp?= - =?us-ascii?Q?Ux9SlgS9YE2bEp6wxcX6TpA5DoYjqdlK50/4/DZ3YTXWlPTaQbt/j36TbEgZ?= - =?us-ascii?Q?hhIV08WX7EDjBz1QrFRppEtBghOJikHLdvPo6GnZkHNQ9cxaa8Jrk0iypK4d?= - =?us-ascii?Q?bMj47kiugWCGY+ZW2ioGV1GgH1aZEvAukQgTiAAiyGU83td11Q5Pv2N5ytvk?= - =?us-ascii?Q?i+Ux/DUoeU4VyqYnb69asjdyKI5RzIxQPdQAQ7x/TBlyPp/Yj2/v31b6lCYT?= - =?us-ascii?Q?b1iYdeIKK+6I6A+e/EUnPOKC?= -X-OriginatorOrg: wdc.com -X-MS-Exchange-CrossTenant-Network-Message-Id: 17406ef0-e8d7-4dc3-eee9-08d92b40085b -X-MS-Exchange-CrossTenant-AuthSource: CO6PR04MB7812.namprd04.prod.outlook.com -X-MS-Exchange-CrossTenant-AuthAs: Internal -X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2021 12:13:47.1304 (UTC) -X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted -X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 -X-MS-Exchange-CrossTenant-MailboxType: HOSTED -X-MS-Exchange-CrossTenant-UserPrincipalName: rHld9c5jovIZF30ZL04ehEJ81O0isWetsUM3vlp/0cN1LoJ5z8guKzUTANDGVGM0Eua+2cZ1jQGTC49NwWH4hA== -X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR04MB7794 -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20210609_051349_766689_30430D67 -X-CRM114-Status: GOOD ( 15.29 ) -X-BeenThere: linux-riscv@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Content-Type: text/plain; charset="us-ascii" -Content-Transfer-Encoding: 7bit -Sender: "linux-riscv" -Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org - -The SBI SRST extension provides a standard way to poweroff and -reboot the system irrespective to whether Linux RISC-V S-mode -is running natively (HS-mode) or inside Guest/VM (VS-mode). - -The SBI SRST extension is available in the SBI v0.3 specification. -(Refer, https://github.com/riscv/riscv-sbi-doc/releases/tag/v0.3.0-rc1) - -This patch extends Linux RISC-V SBI implementation to detect -and use SBI SRST extension. - -Signed-off-by: Anup Patel -Reviewed-by: Atish Patra ---- - arch/riscv/include/asm/sbi.h | 24 ++++++++++++++++++++++++ - arch/riscv/kernel/sbi.c | 35 +++++++++++++++++++++++++++++++++++ - 2 files changed, 59 insertions(+) - ---- a/arch/riscv/include/asm/sbi.h -+++ b/arch/riscv/include/asm/sbi.h -@@ -27,6 +27,7 @@ enum sbi_ext_id { - SBI_EXT_IPI = 0x735049, - SBI_EXT_RFENCE = 0x52464E43, - SBI_EXT_HSM = 0x48534D, -+ SBI_EXT_SRST = 0x53525354, - }; - - enum sbi_ext_base_fid { -@@ -70,6 +71,21 @@ enum sbi_hsm_hart_status { - SBI_HSM_HART_STATUS_STOP_PENDING, - }; - -+enum sbi_ext_srst_fid { -+ SBI_EXT_SRST_RESET = 0, -+}; -+ -+enum sbi_srst_reset_type { -+ SBI_SRST_RESET_TYPE_SHUTDOWN = 0, -+ SBI_SRST_RESET_TYPE_COLD_REBOOT, -+ SBI_SRST_RESET_TYPE_WARM_REBOOT, -+}; -+ -+enum sbi_srst_reset_reason { -+ SBI_SRST_RESET_REASON_NONE = 0, -+ SBI_SRST_RESET_REASON_SYS_FAILURE, -+}; -+ - #define SBI_SPEC_VERSION_DEFAULT 0x1 - #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 - #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f -@@ -148,6 +164,14 @@ static inline unsigned long sbi_minor_ve - return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK; - } - -+/* Make SBI version */ -+static inline unsigned long sbi_mk_version(unsigned long major, -+ unsigned long minor) -+{ -+ return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << -+ SBI_SPEC_VERSION_MAJOR_SHIFT) | minor; -+} -+ - int sbi_err_map_linux_errno(int err); - #else /* CONFIG_RISCV_SBI */ - static inline int sbi_remote_fence_i(const unsigned long *hart_mask) { return -1; } ---- a/arch/riscv/kernel/sbi.c -+++ b/arch/riscv/kernel/sbi.c -@@ -7,6 +7,7 @@ - - #include - #include -+#include - #include - #include - -@@ -501,6 +502,32 @@ int sbi_remote_hfence_vvma_asid(const un - } - EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid); - -+static void sbi_srst_reset(unsigned long type, unsigned long reason) -+{ -+ sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason, -+ 0, 0, 0, 0); -+ pr_warn("%s: type=0x%lx reason=0x%lx failed\n", -+ __func__, type, reason); -+} -+ -+static int sbi_srst_reboot(struct notifier_block *this, -+ unsigned long mode, void *cmd) -+{ -+ sbi_srst_reset((mode == REBOOT_WARM || mode == REBOOT_SOFT) ? -+ SBI_SRST_RESET_TYPE_WARM_REBOOT : -+ SBI_SRST_RESET_TYPE_COLD_REBOOT, -+ SBI_SRST_RESET_REASON_NONE); -+ return NOTIFY_DONE; -+} -+ -+static struct notifier_block sbi_srst_reboot_nb; -+ -+static void sbi_srst_power_off(void) -+{ -+ sbi_srst_reset(SBI_SRST_RESET_TYPE_SHUTDOWN, -+ SBI_SRST_RESET_REASON_NONE); -+} -+ - /** - * sbi_probe_extension() - Check if an SBI extension ID is supported or not. - * @extid: The extension ID to be probed. -@@ -608,6 +635,14 @@ void __init sbi_init(void) - } else { - __sbi_rfence = __sbi_rfence_v01; - } -+ if ((sbi_spec_version >= sbi_mk_version(0, 3)) && -+ (sbi_probe_extension(SBI_EXT_SRST) > 0)) { -+ pr_info("SBI SRST extension detected\n"); -+ pm_power_off = sbi_srst_power_off; -+ sbi_srst_reboot_nb.notifier_call = sbi_srst_reboot; -+ sbi_srst_reboot_nb.priority = 192; -+ register_restart_handler(&sbi_srst_reboot_nb); -+ } - } else { - __sbi_set_timer = __sbi_set_timer_v01; - __sbi_send_ipi = __sbi_send_ipi_v01;