From: David Woodhouse Date: Fri, 19 Jun 2020 11:43:10 +0000 (+0100) Subject: mediatek: fix U-Boot pinctrl setup for mt7623 eMMC X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=dc4699470bb634faf683b30494afeb4c0d9a0073;p=openwrt%2Fstaging%2Fzorun.git mediatek: fix U-Boot pinctrl setup for mt7623 eMMC The U-Boot pinctrl driver for mt7623 was incomplete and didn't handle the settings required for eMMC to work. Submitted upstream at https://patchwork.ozlabs.org/project/uboot/list/?series=184529 Signed-off-by: David Woodhouse --- diff --git a/package/boot/uboot-mediatek/patches/006-mt7623-pinctrl-fix.patch b/package/boot/uboot-mediatek/patches/006-mt7623-pinctrl-fix.patch new file mode 100644 index 0000000000..c5a0cb9c6d --- /dev/null +++ b/package/boot/uboot-mediatek/patches/006-mt7623-pinctrl-fix.patch @@ -0,0 +1,236 @@ +From eca387ea507bde160558a0e5301bf2e0f1985b3b Mon Sep 17 00:00:00 2001 +From: David Woodhouse +Date: Fri, 19 Jun 2020 11:34:32 +0100 +Subject: [PATCH] pinctrl: mediatek: add PUPD/R0/R1 support for MT7623 + +The pins for the MMC controller weren't being set up correctly because the +pinctrl driver only sets the GPIO pullup/pulldown config and doesn't +handle the special cases with PUPD/R0/R1 control. + +Signed-off-by: David Woodhouse +--- + drivers/pinctrl/mediatek/pinctrl-mt7623.c | 129 ++++++++++++++++++ + drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 19 ++- + drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 3 + + 3 files changed, 146 insertions(+), 5 deletions(-) + +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c +index d58d840e08..0f5dcb2c63 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c +@@ -262,6 +262,132 @@ static const struct mtk_pin_field_calc mt7623_pin_drv_range[] = { + PIN_FIELD16(278, 278, 0xf70, 0x10, 8, 4), + }; + ++static const struct mtk_pin_field_calc mt7623_pin_pupd_range[] = { ++ /* MSDC0 */ ++ PIN_FIELD16(111, 111, 0xd00, 0x10, 12, 1), ++ PIN_FIELD16(112, 112, 0xd00, 0x10, 8, 1), ++ PIN_FIELD16(113, 113, 0xd00, 0x10, 4, 1), ++ PIN_FIELD16(114, 114, 0xd00, 0x10, 0, 1), ++ PIN_FIELD16(115, 115, 0xd10, 0x10, 0, 1), ++ PIN_FIELD16(116, 116, 0xcd0, 0x10, 8, 1), ++ PIN_FIELD16(117, 117, 0xcc0, 0x10, 8, 1), ++ PIN_FIELD16(118, 118, 0xcf0, 0x10, 12, 1), ++ PIN_FIELD16(119, 119, 0xcf0, 0x10, 8, 1), ++ PIN_FIELD16(120, 120, 0xcf0, 0x10, 4, 1), ++ PIN_FIELD16(121, 121, 0xcf0, 0x10, 0, 1), ++ /* MSDC1 */ ++ PIN_FIELD16(105, 105, 0xd40, 0x10, 8, 1), ++ PIN_FIELD16(106, 106, 0xd30, 0x10, 8, 1), ++ PIN_FIELD16(107, 107, 0xd60, 0x10, 0, 1), ++ PIN_FIELD16(108, 108, 0xd60, 0x10, 10, 1), ++ PIN_FIELD16(109, 109, 0xd60, 0x10, 4, 1), ++ PIN_FIELD16(110, 110, 0xc60, 0x10, 12, 1), ++ /* MSDC1 */ ++ PIN_FIELD16(85, 85, 0xda0, 0x10, 8, 1), ++ PIN_FIELD16(86, 86, 0xd90, 0x10, 8, 1), ++ PIN_FIELD16(87, 87, 0xdc0, 0x10, 0, 1), ++ PIN_FIELD16(88, 88, 0xdc0, 0x10, 10, 1), ++ PIN_FIELD16(89, 89, 0xdc0, 0x10, 4, 1), ++ PIN_FIELD16(90, 90, 0xdc0, 0x10, 12, 1), ++ /* MSDC0E */ ++ PIN_FIELD16(249, 249, 0x140, 0x10, 0, 1), ++ PIN_FIELD16(250, 250, 0x130, 0x10, 12, 1), ++ PIN_FIELD16(251, 251, 0x130, 0x10, 8, 1), ++ PIN_FIELD16(252, 252, 0x130, 0x10, 4, 1), ++ PIN_FIELD16(253, 253, 0x130, 0x10, 0, 1), ++ PIN_FIELD16(254, 254, 0xf40, 0x10, 12, 1), ++ PIN_FIELD16(255, 255, 0xf40, 0x10, 8, 1), ++ PIN_FIELD16(256, 256, 0xf40, 0x10, 4, 1), ++ PIN_FIELD16(257, 257, 0xf40, 0x10, 0, 1), ++ PIN_FIELD16(258, 258, 0xcb0, 0x10, 8, 1), ++ PIN_FIELD16(259, 259, 0xc90, 0x10, 8, 1), ++ PIN_FIELD16(261, 261, 0x140, 0x10, 8, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_r1_range[] = { ++ /* MSDC0 */ ++ PIN_FIELD16(111, 111, 0xd00, 0x10, 13, 1), ++ PIN_FIELD16(112, 112, 0xd00, 0x10, 9, 1), ++ PIN_FIELD16(113, 113, 0xd00, 0x10, 5, 1), ++ PIN_FIELD16(114, 114, 0xd00, 0x10, 1, 1), ++ PIN_FIELD16(115, 115, 0xd10, 0x10, 1, 1), ++ PIN_FIELD16(116, 116, 0xcd0, 0x10, 9, 1), ++ PIN_FIELD16(117, 117, 0xcc0, 0x10, 9, 1), ++ PIN_FIELD16(118, 118, 0xcf0, 0x10, 13, 1), ++ PIN_FIELD16(119, 119, 0xcf0, 0x10, 9, 1), ++ PIN_FIELD16(120, 120, 0xcf0, 0x10, 5, 1), ++ PIN_FIELD16(121, 121, 0xcf0, 0x10, 1, 1), ++ /* MSDC1 */ ++ PIN_FIELD16(105, 105, 0xd40, 0x10, 9, 1), ++ PIN_FIELD16(106, 106, 0xd30, 0x10, 9, 1), ++ PIN_FIELD16(107, 107, 0xd60, 0x10, 1, 1), ++ PIN_FIELD16(108, 108, 0xd60, 0x10, 9, 1), ++ PIN_FIELD16(109, 109, 0xd60, 0x10, 5, 1), ++ PIN_FIELD16(110, 110, 0xc60, 0x10, 13, 1), ++ /* MSDC2 */ ++ PIN_FIELD16(85, 85, 0xda0, 0x10, 9, 1), ++ PIN_FIELD16(86, 86, 0xd90, 0x10, 9, 1), ++ PIN_FIELD16(87, 87, 0xdc0, 0x10, 1, 1), ++ PIN_FIELD16(88, 88, 0xdc0, 0x10, 9, 1), ++ PIN_FIELD16(89, 89, 0xdc0, 0x10, 5, 1), ++ PIN_FIELD16(90, 90, 0xdc0, 0x10, 13, 1), ++ /* MSDC0E */ ++ PIN_FIELD16(249, 249, 0x140, 0x10, 1, 1), ++ PIN_FIELD16(250, 250, 0x130, 0x10, 13, 1), ++ PIN_FIELD16(251, 251, 0x130, 0x10, 9, 1), ++ PIN_FIELD16(252, 252, 0x130, 0x10, 5, 1), ++ PIN_FIELD16(253, 253, 0x130, 0x10, 1, 1), ++ PIN_FIELD16(254, 254, 0xf40, 0x10, 13, 1), ++ PIN_FIELD16(255, 255, 0xf40, 0x10, 9, 1), ++ PIN_FIELD16(256, 256, 0xf40, 0x10, 5, 1), ++ PIN_FIELD16(257, 257, 0xf40, 0x10, 1, 1), ++ PIN_FIELD16(258, 258, 0xcb0, 0x10, 9, 1), ++ PIN_FIELD16(259, 259, 0xc90, 0x10, 9, 1), ++ PIN_FIELD16(261, 261, 0x140, 0x10, 9, 1), ++}; ++ ++static const struct mtk_pin_field_calc mt7623_pin_r0_range[] = { ++ /* MSDC0 */ ++ PIN_FIELD16(111, 111, 0xd00, 0x10, 14, 1), ++ PIN_FIELD16(112, 112, 0xd00, 0x10, 10, 1), ++ PIN_FIELD16(113, 113, 0xd00, 0x10, 6, 1), ++ PIN_FIELD16(114, 114, 0xd00, 0x10, 2, 1), ++ PIN_FIELD16(115, 115, 0xd10, 0x10, 2, 1), ++ PIN_FIELD16(116, 116, 0xcd0, 0x10, 10, 1), ++ PIN_FIELD16(117, 117, 0xcc0, 0x10, 10, 1), ++ PIN_FIELD16(118, 118, 0xcf0, 0x10, 14, 1), ++ PIN_FIELD16(119, 119, 0xcf0, 0x10, 10, 1), ++ PIN_FIELD16(120, 120, 0xcf0, 0x10, 6, 1), ++ PIN_FIELD16(121, 121, 0xcf0, 0x10, 2, 1), ++ /* MSDC1 */ ++ PIN_FIELD16(105, 105, 0xd40, 0x10, 10, 1), ++ PIN_FIELD16(106, 106, 0xd30, 0x10, 10, 1), ++ PIN_FIELD16(107, 107, 0xd60, 0x10, 2, 1), ++ PIN_FIELD16(108, 108, 0xd60, 0x10, 8, 1), ++ PIN_FIELD16(109, 109, 0xd60, 0x10, 6, 1), ++ PIN_FIELD16(110, 110, 0xc60, 0x10, 14, 1), ++ /* MSDC2 */ ++ PIN_FIELD16(85, 85, 0xda0, 0x10, 10, 1), ++ PIN_FIELD16(86, 86, 0xd90, 0x10, 10, 1), ++ PIN_FIELD16(87, 87, 0xdc0, 0x10, 2, 1), ++ PIN_FIELD16(88, 88, 0xdc0, 0x10, 8, 1), ++ PIN_FIELD16(89, 89, 0xdc0, 0x10, 6, 1), ++ PIN_FIELD16(90, 90, 0xdc0, 0x10, 14, 1), ++ /* MSDC0E */ ++ PIN_FIELD16(249, 249, 0x140, 0x10, 2, 1), ++ PIN_FIELD16(250, 250, 0x130, 0x10, 14, 1), ++ PIN_FIELD16(251, 251, 0x130, 0x10, 10, 1), ++ PIN_FIELD16(252, 252, 0x130, 0x10, 6, 1), ++ PIN_FIELD16(253, 253, 0x130, 0x10, 2, 1), ++ PIN_FIELD16(254, 254, 0xf40, 0x10, 14, 1), ++ PIN_FIELD16(255, 255, 0xf40, 0x10, 10, 1), ++ PIN_FIELD16(256, 256, 0xf40, 0x10, 6, 1), ++ PIN_FIELD16(257, 257, 0xf40, 0x10, 5, 1), ++ PIN_FIELD16(258, 258, 0xcb0, 0x10, 10, 1), ++ PIN_FIELD16(259, 259, 0xc90, 0x10, 10, 1), ++ PIN_FIELD16(261, 261, 0x140, 0x10, 10, 1), ++}; ++ + static const struct mtk_pin_reg_calc mt7623_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7623_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7623_pin_dir_range), +@@ -272,6 +398,9 @@ static const struct mtk_pin_reg_calc mt7623_reg_cals[] = { + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7623_pin_pullsel_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7623_pin_pullen_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7623_pin_drv_range), ++ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7623_pin_pupd_range), ++ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7623_pin_r0_range), ++ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7623_pin_r1_range), + }; + + static const struct mtk_pin_desc mt7623_pins[] = { +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +index 5fdc150295..f5199fc574 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +@@ -296,7 +296,7 @@ static const struct pinconf_param mtk_conf_params[] = { + }; + + +-int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg) ++int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg, u32 val) + { + int err, disable, pullup; + +@@ -323,12 +323,14 @@ int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg) + return 0; + } + +-int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg) ++int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg, u32 val) + { +- int err, disable, pullup; ++ int err, disable, pullup, r0, r1; + + disable = (arg == PIN_CONFIG_BIAS_DISABLE); + pullup = (arg == PIN_CONFIG_BIAS_PULL_UP); ++ r0 = !!(val & 1); ++ r1 = !!(val & 2); + + if (disable) { + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 0); +@@ -344,6 +346,13 @@ int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg) + return err; + } + ++ /* Also set PUPD/R0/R1 if the pin has them */ ++ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup); ++ if (err != -EINVAL) { ++ mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0); ++ mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1); ++ } ++ + return 0; + } + +@@ -419,9 +428,9 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin, + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + if (rev == MTK_PINCTRL_V0) +- err = mtk_pinconf_bias_set_v0(dev, pin, param); ++ err = mtk_pinconf_bias_set_v0(dev, pin, param, arg); + else +- err = mtk_pinconf_bias_set_v1(dev, pin, param); ++ err = mtk_pinconf_bias_set_v1(dev, pin, param, arg); + if (err) + goto err; + break; +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +index e815761450..5e51a9a90c 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +@@ -51,6 +51,9 @@ enum { + PINCTRL_PIN_REG_PULLEN, + PINCTRL_PIN_REG_PULLSEL, + PINCTRL_PIN_REG_DRV, ++ PINCTRL_PIN_REG_PUPD, ++ PINCTRL_PIN_REG_R0, ++ PINCTRL_PIN_REG_R1, + PINCTRL_PIN_REG_MAX, + }; + +-- +2.26.2 +