From: Ansuel Smith Date: Sat, 8 Aug 2020 15:05:48 +0000 (+0200) Subject: ipq806x: replace patches with upstream version X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=df3ad130d561c55bf7c48ad5cff1a79de144413e;p=openwrt%2Fstaging%2Fynezz.git ipq806x: replace patches with upstream version Replace all the custom patches with the backported upstream version Signed-off-by: Ansuel Smith [refresh patches] Signed-off-by: Adrian Schmutzler --- diff --git a/target/linux/ipq806x/patches-5.4/0053-regulator-add-smb208-support.patch b/target/linux/ipq806x/patches-5.4/0053-regulator-add-smb208-support.patch deleted file mode 100644 index 058b303798..0000000000 --- a/target/linux/ipq806x/patches-5.4/0053-regulator-add-smb208-support.patch +++ /dev/null @@ -1,55 +0,0 @@ -From ef10381ca4d01848ebedb4afb2c78feb8052f103 Mon Sep 17 00:00:00 2001 -From: Adrian Panella -Date: Thu, 9 Mar 2017 08:26:54 +0100 -Subject: [PATCH 53/69] regulator: add smb208 support - -Signed-off-by: Adrian Panella ---- - Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 4 ++++ - drivers/regulator/qcom_rpm-regulator.c | 9 +++++++++ - 2 files changed, 13 insertions(+) - ---- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt -+++ b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt -@@ -61,6 +61,7 @@ Regulator nodes are identified by their - "qcom,rpm-pm8901-regulators" - "qcom,rpm-pm8921-regulators" - "qcom,rpm-pm8018-regulators" -+ "qcom,rpm-smb208-regulators" - - - vdd_l0_l1_lvs-supply: - - vdd_l2_l11_l12-supply: -@@ -171,6 +172,9 @@ pm8018: - s1, s2, s3, s4, s5, , l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, - l12, l14, lvs1 - -+smb208: -+ s1a, s1b, s2a, s2b -+ - The content of each sub-node is defined by the standard binding for regulators - - see regulator.txt - with additional custom properties described below: - ---- a/drivers/regulator/qcom_rpm-regulator.c -+++ b/drivers/regulator/qcom_rpm-regulator.c -@@ -925,12 +925,21 @@ static const struct rpm_regulator_data r - { } - }; - -+static const struct rpm_regulator_data rpm_smb208_regulators[] = { -+ { "s1a", QCOM_RPM_SMB208_S1a, &smb208_smps, "vin_s1a" }, -+ { "s1b", QCOM_RPM_SMB208_S1b, &smb208_smps, "vin_s1b" }, -+ { "s2a", QCOM_RPM_SMB208_S2a, &smb208_smps, "vin_s2a" }, -+ { "s2b", QCOM_RPM_SMB208_S2b, &smb208_smps, "vin_s2b" }, -+ { } -+}; -+ - static const struct of_device_id rpm_of_match[] = { - { .compatible = "qcom,rpm-pm8018-regulators", - .data = &rpm_pm8018_regulators }, - { .compatible = "qcom,rpm-pm8058-regulators", .data = &rpm_pm8058_regulators }, - { .compatible = "qcom,rpm-pm8901-regulators", .data = &rpm_pm8901_regulators }, - { .compatible = "qcom,rpm-pm8921-regulators", .data = &rpm_pm8921_regulators }, -+ { .compatible = "qcom,rpm-smb208-regulators", .data = &rpm_smb208_regulators }, - { } - }; - MODULE_DEVICE_TABLE(of, rpm_of_match); diff --git a/target/linux/ipq806x/patches-5.4/0062-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch b/target/linux/ipq806x/patches-5.4/0062-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch deleted file mode 100644 index 0965a31d90..0000000000 --- a/target/linux/ipq806x/patches-5.4/0062-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch +++ /dev/null @@ -1,25 +0,0 @@ -From a16fcf911a020e46439a3bb3e702463fc3159831 Mon Sep 17 00:00:00 2001 -From: Abhishek Sahu -Date: Wed, 18 Nov 2015 12:38:56 +0530 -Subject: [PATCH 62/69] ipq806x: gcc: Added the enable regs and mask for PRNG - -kernel got hanged while reading from /dev/hwrng at the -time of PRNG clock enable - -Change-Id: I89856c7e19e6639508e6a2774304583a3ec91172 -Signed-off-by: Abhishek Sahu ---- - drivers/clk/qcom/gcc-ipq806x.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -1225,6 +1225,8 @@ static struct clk_rcg prng_src = { - .parent_map = gcc_pxo_pll8_map, - }, - .clkr = { -+ .enable_reg = 0x2e80, -+ .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "prng_src", - .parent_names = gcc_pxo_pll8, diff --git a/target/linux/ipq806x/patches-5.4/0064-clk-clk-rpm-fixes.patch b/target/linux/ipq806x/patches-5.4/0064-clk-clk-rpm-fixes.patch deleted file mode 100644 index e3a955b659..0000000000 --- a/target/linux/ipq806x/patches-5.4/0064-clk-clk-rpm-fixes.patch +++ /dev/null @@ -1,95 +0,0 @@ -From d30840e2b1cf79d90392e6051b0c0b6006d29d8b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 9 Mar 2017 09:32:40 +0100 -Subject: [PATCH 64/69] clk: clk-rpm fixes - -Signed-off-by: John Crispin ---- - .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 + - drivers/clk/qcom/clk-rpm.c | 35 ++++++++++++++++++++++ - include/dt-bindings/clock/qcom,rpmcc.h | 4 +++ - 3 files changed, 40 insertions(+) - ---- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt -+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt -@@ -16,6 +16,7 @@ Required properties : - "qcom,rpmcc-msm8974", "qcom,rpmcc" - "qcom,rpmcc-apq8064", "qcom,rpmcc" - "qcom,rpmcc-msm8996", "qcom,rpmcc" -+ "qcom,rpmcc-ipq806x", "qcom,rpmcc" - "qcom,rpmcc-msm8998", "qcom,rpmcc" - "qcom,rpmcc-qcs404", "qcom,rpmcc" - ---- a/include/dt-bindings/clock/qcom,rpmcc.h -+++ b/include/dt-bindings/clock/qcom,rpmcc.h -@@ -37,6 +37,10 @@ - #define RPM_XO_A0 27 - #define RPM_XO_A1 28 - #define RPM_XO_A2 29 -+#define RPM_NSS_FABRIC_0_CLK 30 -+#define RPM_NSS_FABRIC_0_A_CLK 31 -+#define RPM_NSS_FABRIC_1_CLK 32 -+#define RPM_NSS_FABRIC_1_A_CLK 33 - - /* SMD RPM clocks */ - #define RPM_SMD_XO_CLK_SRC 0 ---- a/drivers/clk/qcom/clk-rpm.c -+++ b/drivers/clk/qcom/clk-rpm.c -@@ -512,6 +512,16 @@ DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_ - DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, xo_a1_a_clk, 24); - DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, xo_a2_a_clk, 28); - -+/* ipq806x */ -+DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); -+DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); -+DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK); -+DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); -+DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); -+DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); -+DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK); -+DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK); -+ - static struct clk_rpm *apq8064_clks[] = { - [RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk, - [RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk, -@@ -538,15 +548,40 @@ static struct clk_rpm *apq8064_clks[] = - [RPM_XO_A2] = &apq8064_xo_a2_clk, - }; - -+static struct clk_rpm *ipq806x_clks[] = { -+ [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk, -+ [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk, -+ [RPM_CFPB_CLK] = &ipq806x_cfpb_clk, -+ [RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk, -+ [RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk, -+ [RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk, -+ [RPM_EBI1_CLK] = &ipq806x_ebi1_clk, -+ [RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk, -+ [RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk, -+ [RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk, -+ [RPM_SFPB_CLK] = &ipq806x_sfpb_clk, -+ [RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk, -+ [RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk, -+ [RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk, -+ [RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk, -+ [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk, -+}; -+ - static const struct rpm_clk_desc rpm_clk_apq8064 = { - .clks = apq8064_clks, - .num_clks = ARRAY_SIZE(apq8064_clks), - }; - -+static const struct rpm_clk_desc rpm_clk_ipq806x = { -+ .clks = ipq806x_clks, -+ .num_clks = ARRAY_SIZE(ipq806x_clks), -+}; -+ - static const struct of_device_id rpm_clk_match_table[] = { - { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 }, - { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 }, - { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 }, -+ { .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x }, - { } - }; - MODULE_DEVICE_TABLE(of, rpm_clk_match_table); diff --git a/target/linux/ipq806x/patches-5.4/0073-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch b/target/linux/ipq806x/patches-5.4/0073-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch deleted file mode 100644 index 53e81b7a78..0000000000 --- a/target/linux/ipq806x/patches-5.4/0073-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 2034addc7e193dc81d7ca60d8884832751b76758 Mon Sep 17 00:00:00 2001 -From: Ajay Kishore -Date: Tue, 24 Jan 2017 14:14:16 +0530 -Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps - -For IPQ806x targets, TZ protects the registers that are used to -configure the routing of interrupts to a target processor. -To resolve this, this patch uses scm call to route GPIO interrupts -to application processor. Also the scm call interface is changed. - -Change-Id: Ib6c06829d04bc8c20483c36e63da92e26cdef9ce -Signed-off-by: Ajay Kishore ---- - ---- a/drivers/pinctrl/qcom/pinctrl-msm.c -+++ b/drivers/pinctrl/qcom/pinctrl-msm.c -@@ -22,7 +22,8 @@ - #include - #include - #include -- -+#include -+#include - #include "../core.h" - #include "../pinconf.h" - #include "pinctrl-msm.h" -@@ -706,6 +707,9 @@ static void msm_gpio_irq_mask(struct irq - const struct msm_pingroup *g; - unsigned long flags; - u32 val; -+ u32 addr; -+ int ret; -+ const __be32 *reg; - - g = &pctrl->soc->groups[d->hwirq]; - -@@ -819,6 +823,7 @@ static int msm_gpio_irq_set_type(struct - const struct msm_pingroup *g; - unsigned long flags; - u32 val; -+ int ret; - - g = &pctrl->soc->groups[d->hwirq]; - -@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct - else - clear_bit(d->hwirq, pctrl->dual_edge_irqs); - -+ ret = of_device_is_compatible(pctrl->dev->of_node, -+ "qcom,ipq8064-pinctrl"); - /* Route interrupts to application cpu */ -- val = msm_readl_intr_target(pctrl, g); -- val &= ~(7 << g->intr_target_bit); -- val |= g->intr_target_kpss_val << g->intr_target_bit; -- msm_writel_intr_target(val, pctrl, g); -+ if (!ret) { -+ val = msm_readl_intr_target(pctrl, g); -+ val &= ~(7 << g->intr_target_bit); -+ val |= g->intr_target_kpss_val << g->intr_target_bit; -+ msm_writel_intr_target(val, pctrl, g); -+ } else { -+ const __be32 *reg = of_get_property(pctrl->dev->of_node, "reg", NULL); -+ if (reg) { -+ u32 addr = be32_to_cpup(reg) + g->intr_target_reg; -+ qcom_scm_io_readl(addr, &val); -+ __iormb(); -+ -+ val &= ~(7 << g->intr_target_bit); -+ val |= g->intr_target_kpss_val << g->intr_target_bit; -+ -+ __iowmb(); -+ ret = qcom_scm_io_writel(addr, val); -+ if (ret) -+ pr_err("\n Routing interrupts to Apps proc failed"); -+ } -+ } - - /* Update configuration for gpio. - * RAW_STATUS_EN is left on for all gpio irqs. Due to the diff --git a/target/linux/ipq806x/patches-5.4/0075-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch b/target/linux/ipq806x/patches-5.4/0075-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch deleted file mode 100644 index a0ea8eba54..0000000000 --- a/target/linux/ipq806x/patches-5.4/0075-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch +++ /dev/null @@ -1,50 +0,0 @@ -From a3488aa9bed37c56e405967d44e821c484b5d6b9 Mon Sep 17 00:00:00 2001 -From: Ram Chandra Jangir -Date: Fri, 28 Sep 2018 15:19:50 +0530 -Subject: [PATCH] ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions - -Signed-off-by: Ram Chandra Jangir ---- - drivers/pinctrl/qcom/pinctrl-ipq8064.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c -+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c -@@ -299,7 +299,7 @@ static const char * const gpio_groups[] - }; - - static const char * const mdio_groups[] = { -- "gpio0", "gpio1", "gpio10", "gpio11", -+ "gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66", - }; - - static const char * const mi2s_groups[] = { -@@ -403,8 +403,8 @@ static const char * const usb2_hsic_grou - }; - - static const char * const rgmii2_groups[] = { -- "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", -- "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", -+ "gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", -+ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66", - }; - - static const char * const sata_groups[] = { -@@ -539,7 +539,7 @@ static const struct msm_function ipq8064 - static const struct msm_pingroup ipq8064_groups[] = { - PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), -- PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA), -+ PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), -@@ -603,7 +603,7 @@ static const struct msm_pingroup ipq8064 - PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA), -- PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), -+ PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6), diff --git a/target/linux/ipq806x/patches-5.4/0076-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch b/target/linux/ipq806x/patches-5.4/0076-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch deleted file mode 100644 index cc60cd7a08..0000000000 --- a/target/linux/ipq806x/patches-5.4/0076-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 53ae145a7afa7686e03332d61eed90b7fa7c2529 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 4 Feb 2020 19:38:06 +0100 -Subject: [PATCH v2] watchdog: qcom-wdt: disable pretimeout on timer platform - -Some platform like ipq806x doesn't support pretimeout and define -some interrupts used by qcom,msm-timer. Change the driver to check -and use pretimeout only on qcom,kpss-wdt as it's the only platform -that actually supports it. - -Signed-off-by: Ansuel Smith ---- - drivers/watchdog/qcom-wdt.c | 31 +++++++++++++++++++++++-------- - 1 file changed, 23 insertions(+), 8 deletions(-) - ---- a/drivers/watchdog/qcom-wdt.c -+++ b/drivers/watchdog/qcom-wdt.c -@@ -40,6 +40,11 @@ static const u32 reg_offset_data_kpss[] - [WDT_BITE_TIME] = 0x14, - }; - -+struct qcom_wdt_match_data { -+ const u32 *offset; -+ bool pretimeout; -+}; -+ - struct qcom_wdt { - struct watchdog_device wdd; - unsigned long rate; -@@ -179,19 +184,29 @@ static void qcom_clk_disable_unprepare(v - clk_disable_unprepare(data); - } - -+static const struct qcom_wdt_match_data match_data_apcs_tmr = { -+ .offset = reg_offset_data_apcs_tmr, -+ .pretimeout = false, -+}; -+ -+static const struct qcom_wdt_match_data match_data_kpss = { -+ .offset = reg_offset_data_kpss, -+ .pretimeout = true, -+}; -+ - static int qcom_wdt_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; - struct qcom_wdt *wdt; - struct resource *res; - struct device_node *np = dev->of_node; -- const u32 *regs; -+ const struct qcom_wdt_match_data *data; - u32 percpu_offset; - int irq, ret; - struct clk *clk; - -- regs = of_device_get_match_data(dev); -- if (!regs) { -+ data = of_device_get_match_data(dev); -+ if (!data) { - dev_err(dev, "Unsupported QCOM WDT module\n"); - return -ENODEV; - } -@@ -247,7 +262,7 @@ static int qcom_wdt_probe(struct platfor - - /* check if there is pretimeout support */ - irq = platform_get_irq_optional(pdev, 0); -- if (irq > 0) { -+ if (data->pretimeout && irq > 0) { - ret = devm_request_irq(dev, irq, qcom_wdt_isr, - IRQF_TRIGGER_RISING, - "wdt_bark", &wdt->wdd); -@@ -267,7 +282,7 @@ static int qcom_wdt_probe(struct platfor - wdt->wdd.min_timeout = 1; - wdt->wdd.max_timeout = 0x10000000U / wdt->rate; - wdt->wdd.parent = dev; -- wdt->layout = regs; -+ wdt->layout = data->offset; - - if (readl(wdt_addr(wdt, WDT_STS)) & 1) - wdt->wdd.bootstatus = WDIOF_CARDRESET; -@@ -311,9 +326,9 @@ static int __maybe_unused qcom_wdt_resum - static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume); - - static const struct of_device_id qcom_wdt_of_table[] = { -- { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr }, -- { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr }, -- { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss }, -+ { .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr }, -+ { .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr }, -+ { .compatible = "qcom,kpss-wdt", .data = &match_data_kpss }, - { }, - }; - MODULE_DEVICE_TABLE(of, qcom_wdt_of_table); diff --git a/target/linux/ipq806x/patches-5.4/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch b/target/linux/ipq806x/patches-5.4/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch new file mode 100644 index 0000000000..2b5171fc54 --- /dev/null +++ b/target/linux/ipq806x/patches-5.4/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch @@ -0,0 +1,104 @@ +From 13bec8d49bdf10aab4e1570ef42417f6bfbb6126 Mon Sep 17 00:00:00 2001 +From: Ajay Kishore +Date: Fri, 27 Mar 2020 23:32:08 +0100 +Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps + +For IPQ806x targets, TZ protects the registers that are used to +configure the routing of interrupts to a target processor. +To resolve this, this patch uses scm call to route GPIO interrupts +to application processor. Also the scm call interface is changed. + +Signed-off-by: Ajay Kishore +Signed-off-by: Ansuel Smith +Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com +Reviewed-by: Bjorn Andersson +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/qcom/pinctrl-msm.c | 43 ++++++++++++++++++++++++++++++++------ + 1 file changed, 37 insertions(+), 6 deletions(-) + +(limited to 'drivers/pinctrl/qcom/pinctrl-msm.c') + +--- a/drivers/pinctrl/qcom/pinctrl-msm.c ++++ b/drivers/pinctrl/qcom/pinctrl-msm.c +@@ -22,6 +22,8 @@ + #include + #include + #include ++#include ++#include + + #include "../core.h" + #include "../pinconf.h" +@@ -57,6 +59,8 @@ struct msm_pinctrl { + struct irq_chip irq_chip; + int irq; + ++ bool intr_target_use_scm; ++ + raw_spinlock_t lock; + + DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); +@@ -64,6 +68,7 @@ struct msm_pinctrl { + + const struct msm_pinctrl_soc_data *soc; + void __iomem *regs[MAX_NR_TILES]; ++ u32 phys_base[MAX_NR_TILES]; + }; + + #define MSM_ACCESSOR(name) \ +@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct + else + clear_bit(d->hwirq, pctrl->dual_edge_irqs); + +- /* Route interrupts to application cpu */ +- val = msm_readl_intr_target(pctrl, g); +- val &= ~(7 << g->intr_target_bit); +- val |= g->intr_target_kpss_val << g->intr_target_bit; +- msm_writel_intr_target(val, pctrl, g); ++ /* Route interrupts to application cpu. ++ * With intr_target_use_scm interrupts are routed to ++ * application cpu using scm calls. ++ */ ++ if (pctrl->intr_target_use_scm) { ++ u32 addr = pctrl->phys_base[0] + g->intr_target_reg; ++ int ret; ++ ++ qcom_scm_io_readl(addr, &val); ++ ++ val &= ~(7 << g->intr_target_bit); ++ val |= g->intr_target_kpss_val << g->intr_target_bit; ++ ++ ret = qcom_scm_io_writel(addr, val); ++ if (ret) ++ dev_err(pctrl->dev, ++ "Failed routing %lu interrupt to Apps proc", ++ d->hwirq); ++ } else { ++ val = msm_readl_intr_target(pctrl, g); ++ val &= ~(7 << g->intr_target_bit); ++ val |= g->intr_target_kpss_val << g->intr_target_bit; ++ msm_writel_intr_target(val, pctrl, g); ++ } + + /* Update configuration for gpio. + * RAW_STATUS_EN is left on for all gpio irqs. Due to the +@@ -1138,6 +1162,9 @@ int msm_pinctrl_probe(struct platform_de + pctrl->dev = &pdev->dev; + pctrl->soc = soc_data; + pctrl->chip = msm_gpio_template; ++ pctrl->intr_target_use_scm = of_device_is_compatible( ++ pctrl->dev->of_node, ++ "qcom,ipq8064-pinctrl"); + + raw_spin_lock_init(&pctrl->lock); + +@@ -1154,6 +1181,8 @@ int msm_pinctrl_probe(struct platform_de + pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctrl->regs[0])) + return PTR_ERR(pctrl->regs[0]); ++ ++ pctrl->phys_base[0] = res->start; + } + + msm_pinctrl_setup_pm_reset(pctrl); diff --git a/target/linux/ipq806x/patches-5.4/087-v5.8-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch b/target/linux/ipq806x/patches-5.4/087-v5.8-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch new file mode 100644 index 0000000000..612c33cd0e --- /dev/null +++ b/target/linux/ipq806x/patches-5.4/087-v5.8-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch @@ -0,0 +1,56 @@ +From 8d8cec9bf6e9260397872785f249dfb59a417d08 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 19 Feb 2020 18:59:39 +0100 +Subject: ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions + +Add missing gpio definition for mdio and rgmii2. + +Signed-off-by: Ram Chandra Jangir +Signed-off-by: Ansuel Smith +Link: https://lore.kernel.org/r/20200219175940.744-1-ansuelsmth@gmail.com +Acked-by: Bjorn Andersson +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/qcom/pinctrl-ipq8064.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c ++++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c +@@ -299,7 +299,7 @@ static const char * const gpio_groups[] + }; + + static const char * const mdio_groups[] = { +- "gpio0", "gpio1", "gpio10", "gpio11", ++ "gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66", + }; + + static const char * const mi2s_groups[] = { +@@ -403,8 +403,8 @@ static const char * const usb2_hsic_grou + }; + + static const char * const rgmii2_groups[] = { +- "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", +- "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", ++ "gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", ++ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66", + }; + + static const char * const sata_groups[] = { +@@ -539,7 +539,7 @@ static const struct msm_function ipq8064 + static const struct msm_pingroup ipq8064_groups[] = { + PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), +- PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), +@@ -603,7 +603,7 @@ static const struct msm_pingroup ipq8064 + PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA), +- PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6), diff --git a/target/linux/ipq806x/patches-5.4/088-v5.8-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch b/target/linux/ipq806x/patches-5.4/088-v5.8-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch new file mode 100644 index 0000000000..605eb7d07b --- /dev/null +++ b/target/linux/ipq806x/patches-5.4/088-v5.8-watchdog-qcom-wdt-disable-pretimeout-on-timer-platfo.patch @@ -0,0 +1,98 @@ +From 000de5417107623925a4cf0310579f744ff43c28 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 4 Feb 2020 20:56:48 +0100 +Subject: watchdog: qcom-wdt: disable pretimeout on timer platform + +Some platform like ipq806x doesn't support pretimeout and define +some interrupts used by qcom,msm-timer. Change the driver to check +and use pretimeout only on qcom,kpss-wdt as it's the only platform +that actually supports it. + +Signed-off-by: Ansuel Smith +Reviewed-by: Guenter Roeck +Link: https://lore.kernel.org/r/20200204195648.23350-1-ansuelsmth@gmail.com +[groeck: Conflict resolution] +Signed-off-by: Guenter Roeck +Signed-off-by: Wim Van Sebroeck +--- + drivers/watchdog/qcom-wdt.c | 31 +++++++++++++++++++++++-------- + 1 file changed, 23 insertions(+), 8 deletions(-) + +--- a/drivers/watchdog/qcom-wdt.c ++++ b/drivers/watchdog/qcom-wdt.c +@@ -40,6 +40,11 @@ static const u32 reg_offset_data_kpss[] + [WDT_BITE_TIME] = 0x14, + }; + ++struct qcom_wdt_match_data { ++ const u32 *offset; ++ bool pretimeout; ++}; ++ + struct qcom_wdt { + struct watchdog_device wdd; + unsigned long rate; +@@ -179,19 +184,29 @@ static void qcom_clk_disable_unprepare(v + clk_disable_unprepare(data); + } + ++static const struct qcom_wdt_match_data match_data_apcs_tmr = { ++ .offset = reg_offset_data_apcs_tmr, ++ .pretimeout = false, ++}; ++ ++static const struct qcom_wdt_match_data match_data_kpss = { ++ .offset = reg_offset_data_kpss, ++ .pretimeout = true, ++}; ++ + static int qcom_wdt_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; + struct qcom_wdt *wdt; + struct resource *res; + struct device_node *np = dev->of_node; +- const u32 *regs; ++ const struct qcom_wdt_match_data *data; + u32 percpu_offset; + int irq, ret; + struct clk *clk; + +- regs = of_device_get_match_data(dev); +- if (!regs) { ++ data = of_device_get_match_data(dev); ++ if (!data) { + dev_err(dev, "Unsupported QCOM WDT module\n"); + return -ENODEV; + } +@@ -247,7 +262,7 @@ static int qcom_wdt_probe(struct platfor + + /* check if there is pretimeout support */ + irq = platform_get_irq_optional(pdev, 0); +- if (irq > 0) { ++ if (data->pretimeout && irq > 0) { + ret = devm_request_irq(dev, irq, qcom_wdt_isr, + IRQF_TRIGGER_RISING, + "wdt_bark", &wdt->wdd); +@@ -267,7 +282,7 @@ static int qcom_wdt_probe(struct platfor + wdt->wdd.min_timeout = 1; + wdt->wdd.max_timeout = 0x10000000U / wdt->rate; + wdt->wdd.parent = dev; +- wdt->layout = regs; ++ wdt->layout = data->offset; + + if (readl(wdt_addr(wdt, WDT_STS)) & 1) + wdt->wdd.bootstatus = WDIOF_CARDRESET; +@@ -311,9 +326,9 @@ static int __maybe_unused qcom_wdt_resum + static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume); + + static const struct of_device_id qcom_wdt_of_table[] = { +- { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr }, +- { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr }, +- { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss }, ++ { .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr }, ++ { .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr }, ++ { .compatible = "qcom,kpss-wdt", .data = &match_data_kpss }, + { }, + }; + MODULE_DEVICE_TABLE(of, qcom_wdt_of_table); diff --git a/target/linux/ipq806x/patches-5.4/089-v5.8-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch b/target/linux/ipq806x/patches-5.4/089-v5.8-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch new file mode 100644 index 0000000000..015a917e20 --- /dev/null +++ b/target/linux/ipq806x/patches-5.4/089-v5.8-ipq806x-gcc-Added-the-enable-regs-and-mask-for-PRNG.patch @@ -0,0 +1,28 @@ +From 1aec193ea41d672d11592714cdda8167eb3b38fc Mon Sep 17 00:00:00 2001 +From: Abhishek Sahu +Date: Wed, 18 Mar 2020 14:16:56 +0100 +Subject: ipq806x: gcc: Added the enable regs and mask for PRNG + +Kernel got hanged while reading from /dev/hwrng at the +time of PRNG clock enable + +Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)" +Signed-off-by: Abhishek Sahu +Signed-off-by: Ansuel Smith +Link: https://lkml.kernel.org/r/20200318131657.345-1-ansuelsmth@gmail.com +Signed-off-by: Stephen Boyd +--- + drivers/clk/qcom/gcc-ipq806x.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -1225,6 +1225,8 @@ static struct clk_rcg prng_src = { + .parent_map = gcc_pxo_pll8_map, + }, + .clkr = { ++ .enable_reg = 0x2e80, ++ .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "prng_src", + .parent_names = gcc_pxo_pll8, diff --git a/target/linux/ipq806x/patches-5.4/090-v5.8-clk-clk-rpm-fixes.patch b/target/linux/ipq806x/patches-5.4/090-v5.8-clk-clk-rpm-fixes.patch new file mode 100644 index 0000000000..a28570974e --- /dev/null +++ b/target/linux/ipq806x/patches-5.4/090-v5.8-clk-clk-rpm-fixes.patch @@ -0,0 +1,90 @@ +From eec152734be10c72d2d413a27ca9d282c28cdb61 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 10 Mar 2020 15:37:56 +0100 +Subject: clk: qcom: clk-rpm: add missing rpm clk for ipq806x + +Add missing definition of rpm clk for ipq806x soc + +Signed-off-by: John Crispin +Signed-off-by: Ansuel Smith +Acked-by: John Crispin +Reviewed-by: Rob Herring +Link: https://lkml.kernel.org/r/20200310143756.244-1-ansuelsmth@gmail.com +Signed-off-by: Stephen Boyd +--- + .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 + + drivers/clk/qcom/clk-rpm.c | 35 ++++++++++++++++++++++ + include/dt-bindings/clock/qcom,rpmcc.h | 4 +++ + 3 files changed, 40 insertions(+) + +--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt ++++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +@@ -15,6 +15,7 @@ Required properties : + "qcom,rpmcc-msm8916", "qcom,rpmcc" + "qcom,rpmcc-msm8974", "qcom,rpmcc" + "qcom,rpmcc-apq8064", "qcom,rpmcc" ++ "qcom,rpmcc-ipq806x", "qcom,rpmcc" + "qcom,rpmcc-msm8996", "qcom,rpmcc" + "qcom,rpmcc-msm8998", "qcom,rpmcc" + "qcom,rpmcc-qcs404", "qcom,rpmcc" +--- a/drivers/clk/qcom/clk-rpm.c ++++ b/drivers/clk/qcom/clk-rpm.c +@@ -543,10 +543,45 @@ static const struct rpm_clk_desc rpm_clk + .num_clks = ARRAY_SIZE(apq8064_clks), + }; + ++/* ipq806x */ ++DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); ++DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); ++DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK); ++DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); ++DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); ++DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); ++DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK); ++DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK); ++ ++static struct clk_rpm *ipq806x_clks[] = { ++ [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk, ++ [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk, ++ [RPM_CFPB_CLK] = &ipq806x_cfpb_clk, ++ [RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk, ++ [RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk, ++ [RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk, ++ [RPM_EBI1_CLK] = &ipq806x_ebi1_clk, ++ [RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk, ++ [RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk, ++ [RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk, ++ [RPM_SFPB_CLK] = &ipq806x_sfpb_clk, ++ [RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk, ++ [RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk, ++ [RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk, ++ [RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk, ++ [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk, ++}; ++ ++static const struct rpm_clk_desc rpm_clk_ipq806x = { ++ .clks = ipq806x_clks, ++ .num_clks = ARRAY_SIZE(ipq806x_clks), ++}; ++ + static const struct of_device_id rpm_clk_match_table[] = { + { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 }, + { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 }, + { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 }, ++ { .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x }, + { } + }; + MODULE_DEVICE_TABLE(of, rpm_clk_match_table); +--- a/include/dt-bindings/clock/qcom,rpmcc.h ++++ b/include/dt-bindings/clock/qcom,rpmcc.h +@@ -37,6 +37,10 @@ + #define RPM_XO_A0 27 + #define RPM_XO_A1 28 + #define RPM_XO_A2 29 ++#define RPM_NSS_FABRIC_0_CLK 30 ++#define RPM_NSS_FABRIC_0_A_CLK 31 ++#define RPM_NSS_FABRIC_1_CLK 32 ++#define RPM_NSS_FABRIC_1_A_CLK 33 + + /* SMD RPM clocks */ + #define RPM_SMD_XO_CLK_SRC 0 diff --git a/target/linux/ipq806x/patches-5.4/091-v5.8-regulator-add-smb208-support.patch b/target/linux/ipq806x/patches-5.4/091-v5.8-regulator-add-smb208-support.patch new file mode 100644 index 0000000000..42a02865a3 --- /dev/null +++ b/target/linux/ipq806x/patches-5.4/091-v5.8-regulator-add-smb208-support.patch @@ -0,0 +1,63 @@ +From b5f25304aece9f2e7eaab275bbb5461c666bf38c Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 19 Feb 2020 17:37:11 +0100 +Subject: regulator: add smb208 support + +Smb208 regulators are used on some ipq806x soc. +Add support for it to make it avaiable on some routers +that use it. + +Signed-off-by: Ansuel Smith +Signed-off-by: Adrian Panella +Acked-by: Lee Jones +Link: https://lore.kernel.org/r/20200219163711.479-1-ansuelsmth@gmail.com +Signed-off-by: Mark Brown +--- + Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 4 ++++ + drivers/regulator/qcom_rpm-regulator.c | 9 +++++++++ + 2 files changed, 13 insertions(+) + +--- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt ++++ b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt +@@ -61,6 +61,7 @@ Regulator nodes are identified by their + "qcom,rpm-pm8901-regulators" + "qcom,rpm-pm8921-regulators" + "qcom,rpm-pm8018-regulators" ++ "qcom,rpm-smb208-regulators" + + - vdd_l0_l1_lvs-supply: + - vdd_l2_l11_l12-supply: +@@ -171,6 +172,9 @@ pm8018: + s1, s2, s3, s4, s5, , l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, + l12, l14, lvs1 + ++smb208: ++ s1a, s1b, s2a, s2b ++ + The content of each sub-node is defined by the standard binding for regulators - + see regulator.txt - with additional custom properties described below: + +--- a/drivers/regulator/qcom_rpm-regulator.c ++++ b/drivers/regulator/qcom_rpm-regulator.c +@@ -925,12 +925,21 @@ static const struct rpm_regulator_data r + { } + }; + ++static const struct rpm_regulator_data rpm_smb208_regulators[] = { ++ { "s1a", QCOM_RPM_SMB208_S1a, &smb208_smps, "vin_s1a" }, ++ { "s1b", QCOM_RPM_SMB208_S1b, &smb208_smps, "vin_s1b" }, ++ { "s2a", QCOM_RPM_SMB208_S2a, &smb208_smps, "vin_s2a" }, ++ { "s2b", QCOM_RPM_SMB208_S2b, &smb208_smps, "vin_s2b" }, ++ { } ++}; ++ + static const struct of_device_id rpm_of_match[] = { + { .compatible = "qcom,rpm-pm8018-regulators", + .data = &rpm_pm8018_regulators }, + { .compatible = "qcom,rpm-pm8058-regulators", .data = &rpm_pm8058_regulators }, + { .compatible = "qcom,rpm-pm8901-regulators", .data = &rpm_pm8901_regulators }, + { .compatible = "qcom,rpm-pm8921-regulators", .data = &rpm_pm8921_regulators }, ++ { .compatible = "qcom,rpm-smb208-regulators", .data = &rpm_smb208_regulators }, + { } + }; + MODULE_DEVICE_TABLE(of, rpm_of_match); diff --git a/target/linux/ipq806x/patches-5.4/094-v5.7-ipq806x-net-mdio-add-ipq8064-mdio-driver.patch b/target/linux/ipq806x/patches-5.4/094-v5.7-ipq806x-net-mdio-add-ipq8064-mdio-driver.patch new file mode 100644 index 0000000000..fb8c827d65 --- /dev/null +++ b/target/linux/ipq806x/patches-5.4/094-v5.7-ipq806x-net-mdio-add-ipq8064-mdio-driver.patch @@ -0,0 +1,216 @@ +From caaa71fac36ec8c19145dbf8262a9b77ab09f1a1 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 4 Mar 2020 22:38:32 +0100 +Subject: net: mdio: add ipq8064 mdio driver + +Currently ipq806x soc use generic bitbang driver to +comunicate with the gmac ethernet interface. +Add a dedicated driver created by chunkeey to fix this. + +Co-developed-by: Christian Lamparter +Signed-off-by: Christian Lamparter +Signed-off-by: Ansuel Smith +Signed-off-by: David S. Miller +--- + drivers/net/phy/Kconfig | 8 ++ + drivers/net/phy/Makefile | 1 + + drivers/net/phy/mdio-ipq8064.c | 166 +++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 175 insertions(+) + create mode 100644 drivers/net/phy/mdio-ipq8064.c + +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -156,6 +156,14 @@ config MDIO_I2C + + This is library mode. + ++config MDIO_IPQ8064 ++ tristate "Qualcomm IPQ8064 MDIO interface support" ++ depends on HAS_IOMEM && OF_MDIO ++ depends on MFD_SYSCON ++ help ++ This driver supports the MDIO interface found in the network ++ interface units of the IPQ8064 SoC ++ + config MDIO_MOXART + tristate "MOXA ART MDIO interface support" + depends on ARCH_MOXART || COMPILE_TEST +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -51,6 +51,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium + obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o + obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o + obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o ++obj-$(CONFIG_MDIO_IPQ8064) += mdio-ipq8064.o + obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o + obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o + obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o +--- /dev/null ++++ b/drivers/net/phy/mdio-ipq8064.c +@@ -0,0 +1,166 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Qualcomm IPQ8064 MDIO interface driver ++ * ++ * Copyright (C) 2019 Christian Lamparter ++ * Copyright (C) 2020 Ansuel Smith ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* MII address register definitions */ ++#define MII_ADDR_REG_ADDR 0x10 ++#define MII_BUSY BIT(0) ++#define MII_WRITE BIT(1) ++#define MII_CLKRANGE_60_100M (0 << 2) ++#define MII_CLKRANGE_100_150M (1 << 2) ++#define MII_CLKRANGE_20_35M (2 << 2) ++#define MII_CLKRANGE_35_60M (3 << 2) ++#define MII_CLKRANGE_150_250M (4 << 2) ++#define MII_CLKRANGE_250_300M (5 << 2) ++#define MII_CLKRANGE_MASK GENMASK(4, 2) ++#define MII_REG_SHIFT 6 ++#define MII_REG_MASK GENMASK(10, 6) ++#define MII_ADDR_SHIFT 11 ++#define MII_ADDR_MASK GENMASK(15, 11) ++ ++#define MII_DATA_REG_ADDR 0x14 ++ ++#define MII_MDIO_DELAY_USEC (1000) ++#define MII_MDIO_RETRY_MSEC (10) ++ ++struct ipq8064_mdio { ++ struct regmap *base; /* NSS_GMAC0_BASE */ ++}; ++ ++static int ++ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv) ++{ ++ u32 busy; ++ ++ return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy, ++ !(busy & MII_BUSY), MII_MDIO_DELAY_USEC, ++ MII_MDIO_RETRY_MSEC * USEC_PER_MSEC); ++} ++ ++static int ++ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset) ++{ ++ u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M; ++ struct ipq8064_mdio *priv = bus->priv; ++ u32 ret_val; ++ int err; ++ ++ /* Reject clause 45 */ ++ if (reg_offset & MII_ADDR_C45) ++ return -EOPNOTSUPP; ++ ++ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | ++ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); ++ ++ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); ++ usleep_range(8, 10); ++ ++ err = ipq8064_mdio_wait_busy(priv); ++ if (err) ++ return err; ++ ++ regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val); ++ return (int)ret_val; ++} ++ ++static int ++ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data) ++{ ++ u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M; ++ struct ipq8064_mdio *priv = bus->priv; ++ ++ /* Reject clause 45 */ ++ if (reg_offset & MII_ADDR_C45) ++ return -EOPNOTSUPP; ++ ++ regmap_write(priv->base, MII_DATA_REG_ADDR, data); ++ ++ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | ++ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); ++ ++ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); ++ usleep_range(8, 10); ++ ++ return ipq8064_mdio_wait_busy(priv); ++} ++ ++static int ++ipq8064_mdio_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct ipq8064_mdio *priv; ++ struct mii_bus *bus; ++ int ret; ++ ++ bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv)); ++ if (!bus) ++ return -ENOMEM; ++ ++ bus->name = "ipq8064_mdio_bus"; ++ bus->read = ipq8064_mdio_read; ++ bus->write = ipq8064_mdio_write; ++ snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev)); ++ bus->parent = &pdev->dev; ++ ++ priv = bus->priv; ++ priv->base = device_node_to_regmap(np); ++ if (IS_ERR(priv->base)) { ++ if (priv->base == ERR_PTR(-EPROBE_DEFER)) ++ return -EPROBE_DEFER; ++ ++ dev_err(&pdev->dev, "error getting device regmap, error=%pe\n", ++ priv->base); ++ return PTR_ERR(priv->base); ++ } ++ ++ ret = of_mdiobus_register(bus, np); ++ if (ret) ++ return ret; ++ ++ platform_set_drvdata(pdev, bus); ++ return 0; ++} ++ ++static int ++ipq8064_mdio_remove(struct platform_device *pdev) ++{ ++ struct mii_bus *bus = platform_get_drvdata(pdev); ++ ++ mdiobus_unregister(bus); ++ ++ return 0; ++} ++ ++static const struct of_device_id ipq8064_mdio_dt_ids[] = { ++ { .compatible = "qcom,ipq8064-mdio" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids); ++ ++static struct platform_driver ipq8064_mdio_driver = { ++ .probe = ipq8064_mdio_probe, ++ .remove = ipq8064_mdio_remove, ++ .driver = { ++ .name = "ipq8064-mdio", ++ .of_match_table = ipq8064_mdio_dt_ids, ++ }, ++}; ++ ++module_platform_driver(ipq8064_mdio_driver); ++ ++MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver"); ++MODULE_AUTHOR("Christian Lamparter "); ++MODULE_AUTHOR("Ansuel Smith "); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/ipq806x/patches-5.4/700-net-mdio-add-ipq8064-mdio-driver.patch b/target/linux/ipq806x/patches-5.4/700-net-mdio-add-ipq8064-mdio-driver.patch deleted file mode 100644 index 8ed3e035fd..0000000000 --- a/target/linux/ipq806x/patches-5.4/700-net-mdio-add-ipq8064-mdio-driver.patch +++ /dev/null @@ -1,206 +0,0 @@ -From 5de1da6c862de6a92ac9aed521f21fd5a180f22b Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sat, 2 Feb 2019 02:48:35 +0100 -Subject: [PATCH] net: mdio: add ipq8064 mdio driver - -Signed-off-by: Christian Lamparter ---- - drivers/net/phy/Kconfig | 8 ++ - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mdio-ipq8064.c | 163 +++++++++++++++++++++++++++++++++ - 3 files changed, 172 insertions(+) - create mode 100644 drivers/net/phy/mdio-ipq8064.c - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -156,6 +156,14 @@ config MDIO_I2C - - This is library mode. - -+config MDIO_IPQ8064 -+ tristate "Qualcomm IPQ8064 MDIO interface support" -+ depends on HAS_IOMEM && OF_MDIO -+ depends on MFD_SYSCON -+ help -+ This driver supports the MDIO interface found in the network -+ interface units of the IPQ8064 SoC -+ - config MDIO_MOXART - tristate "MOXA ART MDIO interface support" - depends on ARCH_MOXART || COMPILE_TEST ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -51,6 +51,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium - obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o - obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o - obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o -+obj-$(CONFIG_MDIO_IPQ8064) += mdio-ipq8064.o - obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o - obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o - obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o ---- /dev/null -+++ b/drivers/net/phy/mdio-ipq8064.c -@@ -0,0 +1,163 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// -+// Qualcomm IPQ8064 MDIO interface driver -+// -+// Copyright (C) 2019 Christian Lamparter -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* MII address register definitions */ -+#define MII_ADDR_REG_ADDR 0x10 -+#define MII_BUSY BIT(0) -+#define MII_WRITE BIT(1) -+#define MII_CLKRANGE_60_100M (0 << 2) -+#define MII_CLKRANGE_100_150M (1 << 2) -+#define MII_CLKRANGE_20_35M (2 << 2) -+#define MII_CLKRANGE_35_60M (3 << 2) -+#define MII_CLKRANGE_150_250M (4 << 2) -+#define MII_CLKRANGE_250_300M (5 << 2) -+#define MII_CLKRANGE_MASK GENMASK(4, 2) -+#define MII_REG_SHIFT 6 -+#define MII_REG_MASK GENMASK(10, 6) -+#define MII_ADDR_SHIFT 11 -+#define MII_ADDR_MASK GENMASK(15, 11) -+ -+#define MII_DATA_REG_ADDR 0x14 -+ -+#define MII_MDIO_DELAY (1000) -+#define MII_MDIO_RETRY (10) -+ -+struct ipq8064_mdio { -+ struct regmap *base; /* NSS_GMAC0_BASE */ -+}; -+ -+static int -+ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv) -+{ -+ int i; -+ -+ for (i = 0; i < MII_MDIO_RETRY; i++) { -+ unsigned int busy; -+ -+ regmap_read(priv->base, MII_ADDR_REG_ADDR, &busy); -+ if (!(busy & MII_BUSY)) -+ return 0; -+ -+ udelay(MII_MDIO_DELAY); -+ } -+ -+ return -ETIMEDOUT; -+} -+ -+static int -+ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset) -+{ -+ struct ipq8064_mdio *priv = bus->priv; -+ u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M; -+ u32 ret_val; -+ int err; -+ -+ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | -+ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); -+ -+ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); -+ udelay(10); -+ -+ err = ipq8064_mdio_wait_busy(priv); -+ if (err) -+ return err; -+ -+ regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val); -+ return (int)ret_val; -+} -+ -+static int -+ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data) -+{ -+ struct ipq8064_mdio *priv = bus->priv; -+ u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M; -+ -+ regmap_write(priv->base, MII_DATA_REG_ADDR, data); -+ -+ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | -+ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); -+ -+ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); -+ udelay(10); -+ -+ return ipq8064_mdio_wait_busy(priv); -+} -+ -+static int -+ipq8064_mdio_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct ipq8064_mdio *priv; -+ struct mii_bus *bus; -+ int ret; -+ -+ bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv)); -+ if (!bus) -+ return -ENOMEM; -+ -+ bus->name = "ipq8064_mdio_bus"; -+ bus->read = ipq8064_mdio_read; -+ bus->write = ipq8064_mdio_write; -+ snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev)); -+ bus->parent = &pdev->dev; -+ -+ priv = bus->priv; -+ priv->base = syscon_node_to_regmap(np); -+ if (IS_ERR_OR_NULL(priv->base)) { -+ priv->base = syscon_regmap_lookup_by_phandle(np, "master"); -+ if (IS_ERR_OR_NULL(priv->base)) { -+ pr_err("master phandle not found\n"); -+ return -EINVAL; -+ } -+ } -+ -+ ret = of_mdiobus_register(bus, np); -+ if (ret) -+ return ret; -+ -+ platform_set_drvdata(pdev, bus); -+ return 0; -+} -+ -+static int -+ipq8064_mdio_remove(struct platform_device *pdev) -+{ -+ struct mii_bus *bus = platform_get_drvdata(pdev); -+ -+ mdiobus_unregister(bus); -+ -+ return 0; -+} -+ -+static const struct of_device_id ipq8064_mdio_dt_ids[] = { -+ { .compatible = "qcom,ipq8064-mdio" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids); -+ -+static struct platform_driver ipq8064_mdio_driver = { -+ .probe = ipq8064_mdio_probe, -+ .remove = ipq8064_mdio_remove, -+ .driver = { -+ .name = "ipq8064-mdio", -+ .of_match_table = ipq8064_mdio_dt_ids, -+ }, -+}; -+ -+module_platform_driver(ipq8064_mdio_driver); -+ -+MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver"); -+MODULE_AUTHOR("Christian Lamparter "); -+MODULE_LICENSE("GPL");