From: Dongjin Kim Date: Tue, 5 Feb 2013 05:30:15 +0000 (-0800) Subject: ARM: dts: Fix the timing property of MSHC controller for exynos4412-odroidx X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=ec34d52e2adb48d961dc51037886f2373a3407d2;p=openwrt%2Fstaging%2Fblogic.git ARM: dts: Fix the timing property of MSHC controller for exynos4412-odroidx This fixes the property of dw-mshc-sdr-timing and dw-mshc-ddr-timing as per its current binding, it only has two cells. Signed-off-by: Dongjin Kim Signed-off-by: Kukjin Kim --- diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index f41a84e00f5d..009a9c2a0df7 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -49,8 +49,8 @@ fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3 3>; - samsung,dw-mshc-ddr-timing = <1 2 3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>;