From: Viresh Kumar Date: Thu, 4 Apr 2013 12:54:15 +0000 (+0000) Subject: cpufreq: s3c24xx: move cpufreq driver to drivers/cpufreq X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=f023f8dd59bf93e29e9b9bd98a92eeef43b1a32a;p=openwrt%2Fstaging%2Fblogic.git cpufreq: s3c24xx: move cpufreq driver to drivers/cpufreq This patch moves cpufreq driver of Samsung's ARM based s3c24xx platform to drivers/cpufreq. Signed-off-by: Viresh Kumar Acked-by: Arnd Bergmann Acked-by: Rafael J. Wysocki Signed-off-by: Kukjin Kim --- diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d423d58f938d..f6762794fbb4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2053,53 +2053,6 @@ menu "CPU Power Management" if ARCH_HAS_CPUFREQ source "drivers/cpufreq/Kconfig" - -config CPU_FREQ_S3C - bool - help - Internal configuration node for common cpufreq on Samsung SoC - -config CPU_FREQ_S3C24XX - bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" - depends on ARCH_S3C24XX && CPU_FREQ - select CPU_FREQ_S3C - help - This enables the CPUfreq driver for the Samsung S3C24XX family - of CPUs. - - For details, take a look at . - - If in doubt, say N. - -config CPU_FREQ_S3C24XX_PLL - bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" - depends on CPU_FREQ_S3C24XX - help - Compile in support for changing the PLL frequency from the - S3C24XX series CPUfreq driver. The PLL takes time to settle - after a frequency change, so by default it is not enabled. - - This also means that the PLL tables for the selected CPU(s) will - be built which may increase the size of the kernel image. - -config CPU_FREQ_S3C24XX_DEBUG - bool "Debug CPUfreq Samsung driver core" - depends on CPU_FREQ_S3C24XX - help - Enable s3c_freq_dbg for the Samsung S3C CPUfreq core - -config CPU_FREQ_S3C24XX_IODEBUG - bool "Debug CPUfreq Samsung driver IO timing" - depends on CPU_FREQ_S3C24XX - help - Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core - -config CPU_FREQ_S3C24XX_DEBUGFS - bool "Export debugfs for CPUFreq" - depends on CPU_FREQ_S3C24XX && DEBUG_FS - help - Export status information via debugfs. - endif source "drivers/cpuidle/Kconfig" diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index f2f7088bfd22..ed8aadc646f9 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -28,7 +28,7 @@ config CPU_S3C2410 select CPU_ARM920T select CPU_LLSERIAL_S3C2410 select S3C2410_CLOCK - select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX + select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ select S3C2410_PM if PM select SAMSUNG_HRT help @@ -204,27 +204,38 @@ config S3C24XX_GPIO_EXTRA128 Add an extra 128 gpio numbers to the available GPIO pool. This is available for boards that need extra gpios for external devices. +config S3C24XX_PLL + bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" + depends on ARM_S3C24XX + help + Compile in support for changing the PLL frequency from the + S3C24XX series CPUfreq driver. The PLL takes time to settle + after a frequency change, so by default it is not enabled. + + This also means that the PLL tables for the selected CPU(s) will + be built which may increase the size of the kernel image. + # cpu frequency items common between s3c2410 and s3c2440/s3c2442 config S3C2410_IOTIMING bool - depends on CPU_FREQ_S3C24XX + depends on ARM_S3C24XX_CPUFREQ help Internal node to select io timing code that is common to the s3c2410 and s3c2440/s3c2442 cpu frequency support. config S3C2410_CPUFREQ_UTILS - bool - depends on CPU_FREQ_S3C24XX - help - Internal node to select timing code that is common to the s3c2410 - and s3c2440/s3c244 cpu frequency support. + bool + depends on ARM_S3C24XX_CPUFREQ + help + Internal node to select timing code that is common to the s3c2410 + and s3c2440/s3c244 cpu frequency support. # cpu frequency support common to s3c2412, s3c2413 and s3c2442 config S3C2412_IOTIMING bool - depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443) + depends on ARM_S3C24XX_CPUFREQ && (CPU_S3C2412 || CPU_S3C2443) help Intel node to select io timing code that is common to the s3c2412 and the s3c2443. @@ -233,16 +244,9 @@ config S3C2412_IOTIMING if CPU_S3C2410 -config S3C2410_CPUFREQ - bool - depends on CPU_FREQ_S3C24XX - select S3C2410_CPUFREQ_UTILS - help - CPU Frequency scaling support for S3C2410 - config S3C2410_PLL bool - depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL + depends on ARM_S3C2410_CPUFREQ && S3C24XX_PLL default y help Select the PLL table for the S3C2410 @@ -278,7 +282,7 @@ config ARCH_BAST bool "Simtec Electronics BAST (EB2410ITX)" select ISA select MACH_BAST_IDE - select S3C2410_IOTIMING if S3C2410_CPUFREQ + select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ select S3C24XX_DCLK select S3C24XX_SIMTEC_NOR select S3C24XX_SIMTEC_PM if PM @@ -385,14 +389,6 @@ config CPU_S3C2412_ONLY !CPU_S3C2442 && !CPU_S3C2443 default y -config S3C2412_CPUFREQ - bool - depends on CPU_FREQ_S3C24XX - default y - select S3C2412_IOTIMING - help - CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs. - config S3C2412_DMA bool help @@ -494,14 +490,6 @@ endif # CPU_S3C2416 if CPU_S3C2440 -config S3C2440_CPUFREQ - bool "S3C2440/S3C2442 CPU Frequency scaling support" - depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442) - default y - select S3C2410_CPUFREQ_UTILS - help - CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs. - config S3C2440_DMA bool help @@ -521,15 +509,15 @@ config S3C2440_XTAL_16934400 config S3C2440_PLL_12000000 bool - depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000 - default y if CPU_FREQ_S3C24XX_PLL + depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_12000000 + default y if S3C24XX_PLL help PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals. config S3C2440_PLL_16934400 bool - depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400 - default y if CPU_FREQ_S3C24XX_PLL + depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_16934400 + default y if S3C24XX_PLL help PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals. @@ -583,7 +571,7 @@ config MACH_NEXCODER_2440 config MACH_OSIRIS bool "Simtec IM2440D20 (OSIRIS) module" - select S3C2410_IOTIMING if S3C2440_CPUFREQ + select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ select S3C2440_XTAL_12000000 select S3C24XX_DCLK select S3C24XX_GPIO_EXTRA128 @@ -655,7 +643,7 @@ config MACH_RX1950 bool "HP iPAQ rx1950" select I2C select PM_H1940 if PM - select S3C2410_IOTIMING if S3C2440_CPUFREQ + select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ select S3C2440_XTAL_16934400 select S3C24XX_DCLK select S3C24XX_PWM diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile index 6f46ecfc8396..a3b495a4bba0 100644 --- a/arch/arm/mach-s3c24xx/Makefile +++ b/arch/arm/mach-s3c24xx/Makefile @@ -17,13 +17,11 @@ obj- := obj-y += common.o obj-$(CONFIG_CPU_S3C2410) += s3c2410.o -obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o obj-$(CONFIG_CPU_S3C2412) += s3c2412.o clock-s3c2412.o -obj-$(CONFIG_S3C2412_CPUFREQ) += cpufreq-s3c2412.o obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o @@ -34,7 +32,6 @@ obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o obj-$(CONFIG_CPU_S3C2440) += s3c2440.o clock-s3c2440.o obj-$(CONFIG_CPU_S3C2442) += s3c2442.o obj-$(CONFIG_CPU_S3C244X) += s3c244x.o clock-s3c244x.o -obj-$(CONFIG_S3C2440_CPUFREQ) += cpufreq-s3c2440.o obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o @@ -59,9 +56,6 @@ obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o -obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpufreq.o -obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpufreq-debugfs.o - # # machine support # following is ordered alphabetically by option text. diff --git a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c deleted file mode 100644 index 9b7b4289d66c..000000000000 --- a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2009 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C24XX CPU Frequency scaling - debugfs status support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -static struct dentry *dbgfs_root; -static struct dentry *dbgfs_file_io; -static struct dentry *dbgfs_file_info; -static struct dentry *dbgfs_file_board; - -#define print_ns(x) ((x) / 10), ((x) % 10) - -static void show_max(struct seq_file *seq, struct s3c_freq *f) -{ - seq_printf(seq, "MAX: F=%lu, H=%lu, P=%lu, A=%lu\n", - f->fclk, f->hclk, f->pclk, f->armclk); -} - -static int board_show(struct seq_file *seq, void *p) -{ - struct s3c_cpufreq_config *cfg; - struct s3c_cpufreq_board *brd; - - cfg = s3c_cpufreq_getconfig(); - if (!cfg) { - seq_printf(seq, "no configuration registered\n"); - return 0; - } - - brd = cfg->board; - if (!brd) { - seq_printf(seq, "no board definition set?\n"); - return 0; - } - - seq_printf(seq, "SDRAM refresh %u ns\n", brd->refresh); - seq_printf(seq, "auto_io=%u\n", brd->auto_io); - seq_printf(seq, "need_io=%u\n", brd->need_io); - - show_max(seq, &brd->max); - - - return 0; -} - -static int fops_board_open(struct inode *inode, struct file *file) -{ - return single_open(file, board_show, NULL); -} - -static const struct file_operations fops_board = { - .open = fops_board_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, - .owner = THIS_MODULE, -}; - -static int info_show(struct seq_file *seq, void *p) -{ - struct s3c_cpufreq_config *cfg; - - cfg = s3c_cpufreq_getconfig(); - if (!cfg) { - seq_printf(seq, "no configuration registered\n"); - return 0; - } - - seq_printf(seq, " FCLK %ld Hz\n", cfg->freq.fclk); - seq_printf(seq, " HCLK %ld Hz (%lu.%lu ns)\n", - cfg->freq.hclk, print_ns(cfg->freq.hclk_tns)); - seq_printf(seq, " PCLK %ld Hz\n", cfg->freq.hclk); - seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk); - seq_printf(seq, "\n"); - - show_max(seq, &cfg->max); - - seq_printf(seq, "Divisors: P=%d, H=%d, A=%d, dvs=%s\n", - cfg->divs.h_divisor, cfg->divs.p_divisor, - cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off"); - seq_printf(seq, "\n"); - - seq_printf(seq, "lock_pll=%u\n", cfg->lock_pll); - - return 0; -} - -static int fops_info_open(struct inode *inode, struct file *file) -{ - return single_open(file, info_show, NULL); -} - -static const struct file_operations fops_info = { - .open = fops_info_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, - .owner = THIS_MODULE, -}; - -static int io_show(struct seq_file *seq, void *p) -{ - void (*show_bank)(struct seq_file *, struct s3c_cpufreq_config *, union s3c_iobank *); - struct s3c_cpufreq_config *cfg; - struct s3c_iotimings *iot; - union s3c_iobank *iob; - int bank; - - cfg = s3c_cpufreq_getconfig(); - if (!cfg) { - seq_printf(seq, "no configuration registered\n"); - return 0; - } - - show_bank = cfg->info->debug_io_show; - if (!show_bank) { - seq_printf(seq, "no code to show bank timing\n"); - return 0; - } - - iot = s3c_cpufreq_getiotimings(); - if (!iot) { - seq_printf(seq, "no io timings registered\n"); - return 0; - } - - seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns)); - - for (bank = 0; bank < MAX_BANKS; bank++) { - iob = &iot->bank[bank]; - - seq_printf(seq, "bank %d: ", bank); - - if (!iob->io_2410) { - seq_printf(seq, "nothing set\n"); - continue; - } - - show_bank(seq, cfg, iob); - } - - return 0; -} - -static int fops_io_open(struct inode *inode, struct file *file) -{ - return single_open(file, io_show, NULL); -} - -static const struct file_operations fops_io = { - .open = fops_io_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, - .owner = THIS_MODULE, -}; - - -static int __init s3c_freq_debugfs_init(void) -{ - dbgfs_root = debugfs_create_dir("s3c-cpufreq", NULL); - if (IS_ERR(dbgfs_root)) { - printk(KERN_ERR "%s: error creating debugfs root\n", __func__); - return PTR_ERR(dbgfs_root); - } - - dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root, - NULL, &fops_io); - - dbgfs_file_info = debugfs_create_file("info", S_IRUGO, dbgfs_root, - NULL, &fops_info); - - dbgfs_file_board = debugfs_create_file("board", S_IRUGO, dbgfs_root, - NULL, &fops_board); - - return 0; -} - -late_initcall(s3c_freq_debugfs_init); - diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c deleted file mode 100644 index cfa0dd8723ec..000000000000 --- a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (c) 2006-2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C2410 CPU Frequency scaling - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include - -/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */ - -static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) -{ - u32 clkdiv = 0; - - if (cfg->divs.h_divisor == 2) - clkdiv |= S3C2410_CLKDIVN_HDIVN; - - if (cfg->divs.p_divisor != cfg->divs.h_divisor) - clkdiv |= S3C2410_CLKDIVN_PDIVN; - - __raw_writel(clkdiv, S3C2410_CLKDIVN); -} - -static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) -{ - unsigned long hclk, fclk, pclk; - unsigned int hdiv, pdiv; - unsigned long hclk_max; - - fclk = cfg->freq.fclk; - hclk_max = cfg->max.hclk; - - cfg->freq.armclk = fclk; - - s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n", - __func__, fclk, hclk_max); - - hdiv = (fclk > cfg->max.hclk) ? 2 : 1; - hclk = fclk / hdiv; - - if (hclk > cfg->max.hclk) { - s3c_freq_dbg("%s: hclk too big\n", __func__); - return -EINVAL; - } - - pdiv = (hclk > cfg->max.pclk) ? 2 : 1; - pclk = hclk / pdiv; - - if (pclk > cfg->max.pclk) { - s3c_freq_dbg("%s: pclk too big\n", __func__); - return -EINVAL; - } - - pdiv *= hdiv; - - /* record the result */ - cfg->divs.p_divisor = pdiv; - cfg->divs.h_divisor = hdiv; - - return 0; -} - -static struct s3c_cpufreq_info s3c2410_cpufreq_info = { - .max = { - .fclk = 200000000, - .hclk = 100000000, - .pclk = 50000000, - }, - - /* transition latency is about 5ms worst-case, so - * set 10ms to be sure */ - .latency = 10000000, - - .locktime_m = 150, - .locktime_u = 150, - .locktime_bits = 12, - - .need_pll = 1, - - .name = "s3c2410", - .calc_iotiming = s3c2410_iotiming_calc, - .set_iotiming = s3c2410_iotiming_set, - .get_iotiming = s3c2410_iotiming_get, - .resume_clocks = s3c2410_setup_clocks, - - .set_fvco = s3c2410_set_fvco, - .set_refresh = s3c2410_cpufreq_setrefresh, - .set_divs = s3c2410_cpufreq_setdivs, - .calc_divs = s3c2410_cpufreq_calcdivs, - - .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), -}; - -static int s3c2410_cpufreq_add(struct device *dev, - struct subsys_interface *sif) -{ - return s3c_cpufreq_register(&s3c2410_cpufreq_info); -} - -static struct subsys_interface s3c2410_cpufreq_interface = { - .name = "s3c2410_cpufreq", - .subsys = &s3c2410_subsys, - .add_dev = s3c2410_cpufreq_add, -}; - -static int __init s3c2410_cpufreq_init(void) -{ - return subsys_interface_register(&s3c2410_cpufreq_interface); -} -arch_initcall(s3c2410_cpufreq_init); - -static int s3c2410a_cpufreq_add(struct device *dev, - struct subsys_interface *sif) -{ - /* alter the maximum freq settings for S3C2410A. If a board knows - * it only has a maximum of 200, then it should register its own - * limits. */ - - s3c2410_cpufreq_info.max.fclk = 266000000; - s3c2410_cpufreq_info.max.hclk = 133000000; - s3c2410_cpufreq_info.max.pclk = 66500000; - s3c2410_cpufreq_info.name = "s3c2410a"; - - return s3c2410_cpufreq_add(dev, sif); -} - -static struct subsys_interface s3c2410a_cpufreq_interface = { - .name = "s3c2410a_cpufreq", - .subsys = &s3c2410a_subsys, - .add_dev = s3c2410a_cpufreq_add, -}; - -static int __init s3c2410a_cpufreq_init(void) -{ - return subsys_interface_register(&s3c2410a_cpufreq_interface); -} -arch_initcall(s3c2410a_cpufreq_init); diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c deleted file mode 100644 index 8bf0f3a77476..000000000000 --- a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C2412 CPU Frequency scalling - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include - -#include "s3c2412.h" - -/* our clock resources. */ -static struct clk *xtal; -static struct clk *fclk; -static struct clk *hclk; -static struct clk *armclk; - -/* HDIV: 1, 2, 3, 4, 6, 8 */ - -static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) -{ - unsigned int hdiv, pdiv, armdiv, dvs; - unsigned long hclk, fclk, armclk, armdiv_clk; - unsigned long hclk_max; - - fclk = cfg->freq.fclk; - armclk = cfg->freq.armclk; - hclk_max = cfg->max.hclk; - - /* We can't run hclk above armclk as at the best we have to - * have armclk and hclk in dvs mode. */ - - if (hclk_max > armclk) - hclk_max = armclk; - - s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n", - __func__, fclk, armclk, hclk_max); - s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n", - __func__, cfg->freq.fclk, cfg->freq.armclk, - cfg->freq.hclk, cfg->freq.pclk); - - armdiv = fclk / armclk; - - if (armdiv < 1) - armdiv = 1; - if (armdiv > 2) - armdiv = 2; - - cfg->divs.arm_divisor = armdiv; - armdiv_clk = fclk / armdiv; - - hdiv = armdiv_clk / hclk_max; - if (hdiv < 1) - hdiv = 1; - - cfg->freq.hclk = hclk = armdiv_clk / hdiv; - - /* set dvs depending on whether we reached armclk or not. */ - cfg->divs.dvs = dvs = armclk < armdiv_clk; - - /* update the actual armclk we achieved. */ - cfg->freq.armclk = dvs ? hclk : armdiv_clk; - - s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n", - __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs); - - if (hdiv > 4) - goto invalid; - - pdiv = (hclk > cfg->max.pclk) ? 2 : 1; - - if ((hclk / pdiv) > cfg->max.pclk) - pdiv++; - - cfg->freq.pclk = hclk / pdiv; - - s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); - - if (pdiv > 2) - goto invalid; - - pdiv *= hdiv; - - /* store the result, and then return */ - - cfg->divs.h_divisor = hdiv * armdiv; - cfg->divs.p_divisor = pdiv * armdiv; - - return 0; - -invalid: - return -EINVAL; -} - -static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) -{ - unsigned long clkdiv; - unsigned long olddiv; - - olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN); - - /* clear off current clock info */ - - clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN; - clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK; - clkdiv &= ~S3C2412_CLKDIVN_PDIVN; - - if (cfg->divs.arm_divisor == 2) - clkdiv |= S3C2412_CLKDIVN_ARMDIVN; - - clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1); - - if (cfg->divs.p_divisor != cfg->divs.h_divisor) - clkdiv |= S3C2412_CLKDIVN_PDIVN; - - s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv); - __raw_writel(clkdiv, S3C2410_CLKDIVN); - - clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); -} - -static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) -{ - struct s3c_cpufreq_board *board = cfg->board; - unsigned long refresh; - - s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__, - board->refresh, cfg->freq.hclk); - - /* Reduce both the refresh time (in ns) and the frequency (in MHz) - * by 10 each to ensure that we do not overflow 32 bit numbers. This - * should work for HCLK up to 133MHz and refresh period up to 30usec. - */ - - refresh = (board->refresh / 10); - refresh *= (cfg->freq.hclk / 100); - refresh /= (1 * 1000 * 1000); /* 10^6 */ - - s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh); - __raw_writel(refresh, S3C2412_REFRESH); -} - -/* set the default cpu frequency information, based on an 200MHz part - * as we have no other way of detecting the speed rating in software. - */ - -static struct s3c_cpufreq_info s3c2412_cpufreq_info = { - .max = { - .fclk = 200000000, - .hclk = 100000000, - .pclk = 50000000, - }, - - .latency = 5000000, /* 5ms */ - - .locktime_m = 150, - .locktime_u = 150, - .locktime_bits = 16, - - .name = "s3c2412", - .set_refresh = s3c2412_cpufreq_setrefresh, - .set_divs = s3c2412_cpufreq_setdivs, - .calc_divs = s3c2412_cpufreq_calcdivs, - - .calc_iotiming = s3c2412_iotiming_calc, - .set_iotiming = s3c2412_iotiming_set, - .get_iotiming = s3c2412_iotiming_get, - - .resume_clocks = s3c2412_setup_clocks, - - .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs), -}; - -static int s3c2412_cpufreq_add(struct device *dev, - struct subsys_interface *sif) -{ - unsigned long fclk_rate; - - hclk = clk_get(NULL, "hclk"); - if (IS_ERR(hclk)) { - printk(KERN_ERR "%s: cannot find hclk clock\n", __func__); - return -ENOENT; - } - - fclk = clk_get(NULL, "fclk"); - if (IS_ERR(fclk)) { - printk(KERN_ERR "%s: cannot find fclk clock\n", __func__); - goto err_fclk; - } - - fclk_rate = clk_get_rate(fclk); - if (fclk_rate > 200000000) { - printk(KERN_INFO - "%s: fclk %ld MHz, assuming 266MHz capable part\n", - __func__, fclk_rate / 1000000); - s3c2412_cpufreq_info.max.fclk = 266000000; - s3c2412_cpufreq_info.max.hclk = 133000000; - s3c2412_cpufreq_info.max.pclk = 66000000; - } - - armclk = clk_get(NULL, "armclk"); - if (IS_ERR(armclk)) { - printk(KERN_ERR "%s: cannot find arm clock\n", __func__); - goto err_armclk; - } - - xtal = clk_get(NULL, "xtal"); - if (IS_ERR(xtal)) { - printk(KERN_ERR "%s: cannot find xtal clock\n", __func__); - goto err_xtal; - } - - return s3c_cpufreq_register(&s3c2412_cpufreq_info); - -err_xtal: - clk_put(armclk); -err_armclk: - clk_put(fclk); -err_fclk: - clk_put(hclk); - - return -ENOENT; -} - -static struct subsys_interface s3c2412_cpufreq_interface = { - .name = "s3c2412_cpufreq", - .subsys = &s3c2412_subsys, - .add_dev = s3c2412_cpufreq_add, -}; - -static int s3c2412_cpufreq_init(void) -{ - return subsys_interface_register(&s3c2412_cpufreq_interface); -} -arch_initcall(s3c2412_cpufreq_init); diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c deleted file mode 100644 index 72b2cc8a5a85..000000000000 --- a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c +++ /dev/null @@ -1,312 +0,0 @@ -/* - * Copyright (c) 2006-2009 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * Vincent Sanders - * - * S3C2440/S3C2442 CPU Frequency scaling - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include - -#include -#include -#include - -static struct clk *xtal; -static struct clk *fclk; -static struct clk *hclk; -static struct clk *armclk; - -/* HDIV: 1, 2, 3, 4, 6, 8 */ - -static inline int within_khz(unsigned long a, unsigned long b) -{ - long diff = a - b; - - return (diff >= -1000 && diff <= 1000); -} - -/** - * s3c2440_cpufreq_calcdivs - calculate divider settings - * @cfg: The cpu frequency settings. - * - * Calcualte the divider values for the given frequency settings - * specified in @cfg. The values are stored in @cfg for later use - * by the relevant set routine if the request settings can be reached. - */ -int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) -{ - unsigned int hdiv, pdiv; - unsigned long hclk, fclk, armclk; - unsigned long hclk_max; - - fclk = cfg->freq.fclk; - armclk = cfg->freq.armclk; - hclk_max = cfg->max.hclk; - - s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n", - __func__, fclk, armclk, hclk_max); - - if (armclk > fclk) { - printk(KERN_WARNING "%s: armclk > fclk\n", __func__); - armclk = fclk; - } - - /* if we are in DVS, we need HCLK to be <= ARMCLK */ - if (armclk < fclk && armclk < hclk_max) - hclk_max = armclk; - - for (hdiv = 1; hdiv < 9; hdiv++) { - if (hdiv == 5 || hdiv == 7) - hdiv++; - - hclk = (fclk / hdiv); - if (hclk <= hclk_max || within_khz(hclk, hclk_max)) - break; - } - - s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv); - - if (hdiv > 8) - goto invalid; - - pdiv = (hclk > cfg->max.pclk) ? 2 : 1; - - if ((hclk / pdiv) > cfg->max.pclk) - pdiv++; - - s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); - - if (pdiv > 2) - goto invalid; - - pdiv *= hdiv; - - /* calculate a valid armclk */ - - if (armclk < hclk) - armclk = hclk; - - /* if we're running armclk lower than fclk, this really means - * that the system should go into dvs mode, which means that - * armclk is connected to hclk. */ - if (armclk < fclk) { - cfg->divs.dvs = 1; - armclk = hclk; - } else - cfg->divs.dvs = 0; - - cfg->freq.armclk = armclk; - - /* store the result, and then return */ - - cfg->divs.h_divisor = hdiv; - cfg->divs.p_divisor = pdiv; - - return 0; - - invalid: - return -EINVAL; -} - -#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \ - S3C2440_CAMDIVN_HCLK4_HALF) - -/** - * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings - * @cfg: The cpu frequency settings. - * - * Set the divisors from the settings in @cfg, which where generated - * during the calculation phase by s3c2440_cpufreq_calcdivs(). - */ -static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) -{ - unsigned long clkdiv, camdiv; - - s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__, - cfg->divs.h_divisor, cfg->divs.p_divisor); - - clkdiv = __raw_readl(S3C2410_CLKDIVN); - camdiv = __raw_readl(S3C2440_CAMDIVN); - - clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN); - camdiv &= ~CAMDIVN_HCLK_HALF; - - switch (cfg->divs.h_divisor) { - case 1: - clkdiv |= S3C2440_CLKDIVN_HDIVN_1; - break; - - case 2: - clkdiv |= S3C2440_CLKDIVN_HDIVN_2; - break; - - case 6: - camdiv |= S3C2440_CAMDIVN_HCLK3_HALF; - case 3: - clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6; - break; - - case 8: - camdiv |= S3C2440_CAMDIVN_HCLK4_HALF; - case 4: - clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8; - break; - - default: - BUG(); /* we don't expect to get here. */ - } - - if (cfg->divs.p_divisor != cfg->divs.h_divisor) - clkdiv |= S3C2440_CLKDIVN_PDIVN; - - /* todo - set pclk. */ - - /* Write the divisors first with hclk intentionally halved so that - * when we write clkdiv we will under-frequency instead of over. We - * then make a short delay and remove the hclk halving if necessary. - */ - - __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN); - __raw_writel(clkdiv, S3C2410_CLKDIVN); - - ndelay(20); - __raw_writel(camdiv, S3C2440_CAMDIVN); - - clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); -} - -static int run_freq_for(unsigned long max_hclk, unsigned long fclk, - int *divs, - struct cpufreq_frequency_table *table, - size_t table_size) -{ - unsigned long freq; - int index = 0; - int div; - - for (div = *divs; div > 0; div = *divs++) { - freq = fclk / div; - - if (freq > max_hclk && div != 1) - continue; - - freq /= 1000; /* table is in kHz */ - index = s3c_cpufreq_addfreq(table, index, table_size, freq); - if (index < 0) - break; - } - - return index; -} - -static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 }; - -static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg, - struct cpufreq_frequency_table *table, - size_t table_size) -{ - int ret; - - WARN_ON(cfg->info == NULL); - WARN_ON(cfg->board == NULL); - - ret = run_freq_for(cfg->info->max.hclk, - cfg->info->max.fclk, - hclk_divs, - table, table_size); - - s3c_freq_dbg("%s: returning %d\n", __func__, ret); - - return ret; -} - -struct s3c_cpufreq_info s3c2440_cpufreq_info = { - .max = { - .fclk = 400000000, - .hclk = 133333333, - .pclk = 66666666, - }, - - .locktime_m = 300, - .locktime_u = 300, - .locktime_bits = 16, - - .name = "s3c244x", - .calc_iotiming = s3c2410_iotiming_calc, - .set_iotiming = s3c2410_iotiming_set, - .get_iotiming = s3c2410_iotiming_get, - .set_fvco = s3c2410_set_fvco, - - .set_refresh = s3c2410_cpufreq_setrefresh, - .set_divs = s3c2440_cpufreq_setdivs, - .calc_divs = s3c2440_cpufreq_calcdivs, - .calc_freqtable = s3c2440_cpufreq_calctable, - - .resume_clocks = s3c244x_setup_clocks, - - .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), -}; - -static int s3c2440_cpufreq_add(struct device *dev, - struct subsys_interface *sif) -{ - xtal = s3c_cpufreq_clk_get(NULL, "xtal"); - hclk = s3c_cpufreq_clk_get(NULL, "hclk"); - fclk = s3c_cpufreq_clk_get(NULL, "fclk"); - armclk = s3c_cpufreq_clk_get(NULL, "armclk"); - - if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) { - printk(KERN_ERR "%s: failed to get clocks\n", __func__); - return -ENOENT; - } - - return s3c_cpufreq_register(&s3c2440_cpufreq_info); -} - -static struct subsys_interface s3c2440_cpufreq_interface = { - .name = "s3c2440_cpufreq", - .subsys = &s3c2440_subsys, - .add_dev = s3c2440_cpufreq_add, -}; - -static int s3c2440_cpufreq_init(void) -{ - return subsys_interface_register(&s3c2440_cpufreq_interface); -} - -/* arch_initcall adds the clocks we need, so use subsys_initcall. */ -subsys_initcall(s3c2440_cpufreq_init); - -static struct subsys_interface s3c2442_cpufreq_interface = { - .name = "s3c2442_cpufreq", - .subsys = &s3c2442_subsys, - .add_dev = s3c2440_cpufreq_add, -}; - -static int s3c2442_cpufreq_init(void) -{ - return subsys_interface_register(&s3c2442_cpufreq_interface); -} -subsys_initcall(s3c2442_cpufreq_init); diff --git a/arch/arm/mach-s3c24xx/cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq.c deleted file mode 100644 index 3c0e78ede0da..000000000000 --- a/arch/arm/mach-s3c24xx/cpufreq.c +++ /dev/null @@ -1,711 +0,0 @@ -/* - * Copyright (c) 2006-2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C24XX CPU Frequency scaling - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include - -/* note, cpufreq support deals in kHz, no Hz */ - -static struct cpufreq_driver s3c24xx_driver; -static struct s3c_cpufreq_config cpu_cur; -static struct s3c_iotimings s3c24xx_iotiming; -static struct cpufreq_frequency_table *pll_reg; -static unsigned int last_target = ~0; -static unsigned int ftab_size; -static struct cpufreq_frequency_table *ftab; - -static struct clk *_clk_mpll; -static struct clk *_clk_xtal; -static struct clk *clk_fclk; -static struct clk *clk_hclk; -static struct clk *clk_pclk; -static struct clk *clk_arm; - -#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS -struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void) -{ - return &cpu_cur; -} - -struct s3c_iotimings *s3c_cpufreq_getiotimings(void) -{ - return &s3c24xx_iotiming; -} -#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUGFS */ - -static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg) -{ - unsigned long fclk, pclk, hclk, armclk; - - cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); - cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); - cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); - cfg->freq.armclk = armclk = clk_get_rate(clk_arm); - - cfg->pll.index = __raw_readl(S3C2410_MPLLCON); - cfg->pll.frequency = fclk; - - cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); - - cfg->divs.h_divisor = fclk / hclk; - cfg->divs.p_divisor = fclk / pclk; -} - -static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg) -{ - unsigned long pll = cfg->pll.frequency; - - cfg->freq.fclk = pll; - cfg->freq.hclk = pll / cfg->divs.h_divisor; - cfg->freq.pclk = pll / cfg->divs.p_divisor; - - /* convert hclk into 10ths of nanoseconds for io calcs */ - cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); -} - -static inline int closer(unsigned int target, unsigned int n, unsigned int c) -{ - int diff_cur = abs(target - c); - int diff_new = abs(target - n); - - return (diff_new < diff_cur); -} - -static void s3c_cpufreq_show(const char *pfx, - struct s3c_cpufreq_config *cfg) -{ - s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n", - pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, - cfg->freq.hclk, cfg->divs.h_divisor, - cfg->freq.pclk, cfg->divs.p_divisor); -} - -/* functions to wrapper the driver info calls to do the cpu specific work */ - -static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg) -{ - if (cfg->info->set_iotiming) - (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming); -} - -static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg) -{ - if (cfg->info->calc_iotiming) - return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming); - - return 0; -} - -static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) -{ - (cfg->info->set_refresh)(cfg); -} - -static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) -{ - (cfg->info->set_divs)(cfg); -} - -static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) -{ - return (cfg->info->calc_divs)(cfg); -} - -static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg) -{ - (cfg->info->set_fvco)(cfg); -} - -static inline void s3c_cpufreq_resume_clocks(void) -{ - cpu_cur.info->resume_clocks(); -} - -static inline void s3c_cpufreq_updateclk(struct clk *clk, - unsigned int freq) -{ - clk_set_rate(clk, freq); -} - -static int s3c_cpufreq_settarget(struct cpufreq_policy *policy, - unsigned int target_freq, - struct cpufreq_frequency_table *pll) -{ - struct s3c_cpufreq_freqs freqs; - struct s3c_cpufreq_config cpu_new; - unsigned long flags; - - cpu_new = cpu_cur; /* copy new from current */ - - s3c_cpufreq_show("cur", &cpu_cur); - - /* TODO - check for DMA currently outstanding */ - - cpu_new.pll = pll ? *pll : cpu_cur.pll; - - if (pll) - freqs.pll_changing = 1; - - /* update our frequencies */ - - cpu_new.freq.armclk = target_freq; - cpu_new.freq.fclk = cpu_new.pll.frequency; - - if (s3c_cpufreq_calcdivs(&cpu_new) < 0) { - printk(KERN_ERR "no divisors for %d\n", target_freq); - goto err_notpossible; - } - - s3c_freq_dbg("%s: got divs\n", __func__); - - s3c_cpufreq_calc(&cpu_new); - - s3c_freq_dbg("%s: calculated frequencies for new\n", __func__); - - if (cpu_new.freq.hclk != cpu_cur.freq.hclk) { - if (s3c_cpufreq_calcio(&cpu_new) < 0) { - printk(KERN_ERR "%s: no IO timings\n", __func__); - goto err_notpossible; - } - } - - s3c_cpufreq_show("new", &cpu_new); - - /* setup our cpufreq parameters */ - - freqs.old = cpu_cur.freq; - freqs.new = cpu_new.freq; - - freqs.freqs.old = cpu_cur.freq.armclk / 1000; - freqs.freqs.new = cpu_new.freq.armclk / 1000; - - /* update f/h/p clock settings before we issue the change - * notification, so that drivers do not need to do anything - * special if they want to recalculate on CPUFREQ_PRECHANGE. */ - - s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency); - s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk); - s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk); - s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk); - - /* start the frequency change */ - cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_PRECHANGE); - - /* If hclk is staying the same, then we do not need to - * re-write the IO or the refresh timings whilst we are changing - * speed. */ - - local_irq_save(flags); - - /* is our memory clock slowing down? */ - if (cpu_new.freq.hclk < cpu_cur.freq.hclk) { - s3c_cpufreq_setrefresh(&cpu_new); - s3c_cpufreq_setio(&cpu_new); - } - - if (cpu_new.freq.fclk == cpu_cur.freq.fclk) { - /* not changing PLL, just set the divisors */ - - s3c_cpufreq_setdivs(&cpu_new); - } else { - if (cpu_new.freq.fclk < cpu_cur.freq.fclk) { - /* slow the cpu down, then set divisors */ - - s3c_cpufreq_setfvco(&cpu_new); - s3c_cpufreq_setdivs(&cpu_new); - } else { - /* set the divisors, then speed up */ - - s3c_cpufreq_setdivs(&cpu_new); - s3c_cpufreq_setfvco(&cpu_new); - } - } - - /* did our memory clock speed up */ - if (cpu_new.freq.hclk > cpu_cur.freq.hclk) { - s3c_cpufreq_setrefresh(&cpu_new); - s3c_cpufreq_setio(&cpu_new); - } - - /* update our current settings */ - cpu_cur = cpu_new; - - local_irq_restore(flags); - - /* notify everyone we've done this */ - cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_POSTCHANGE); - - s3c_freq_dbg("%s: finished\n", __func__); - return 0; - - err_notpossible: - printk(KERN_ERR "no compatible settings for %d\n", target_freq); - return -EINVAL; -} - -/* s3c_cpufreq_target - * - * called by the cpufreq core to adjust the frequency that the CPU - * is currently running at. - */ - -static int s3c_cpufreq_target(struct cpufreq_policy *policy, - unsigned int target_freq, - unsigned int relation) -{ - struct cpufreq_frequency_table *pll; - unsigned int index; - - /* avoid repeated calls which cause a needless amout of duplicated - * logging output (and CPU time as the calculation process is - * done) */ - if (target_freq == last_target) - return 0; - - last_target = target_freq; - - s3c_freq_dbg("%s: policy %p, target %u, relation %u\n", - __func__, policy, target_freq, relation); - - if (ftab) { - if (cpufreq_frequency_table_target(policy, ftab, - target_freq, relation, - &index)) { - s3c_freq_dbg("%s: table failed\n", __func__); - return -EINVAL; - } - - s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__, - target_freq, index, ftab[index].frequency); - target_freq = ftab[index].frequency; - } - - target_freq *= 1000; /* convert target to Hz */ - - /* find the settings for our new frequency */ - - if (!pll_reg || cpu_cur.lock_pll) { - /* either we've not got any PLL values, or we've locked - * to the current one. */ - pll = NULL; - } else { - struct cpufreq_policy tmp_policy; - int ret; - - /* we keep the cpu pll table in Hz, to ensure we get an - * accurate value for the PLL output. */ - - tmp_policy.min = policy->min * 1000; - tmp_policy.max = policy->max * 1000; - tmp_policy.cpu = policy->cpu; - - /* cpufreq_frequency_table_target uses a pointer to 'index' - * which is the number of the table entry, not the value of - * the table entry's index field. */ - - ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg, - target_freq, relation, - &index); - - if (ret < 0) { - printk(KERN_ERR "%s: no PLL available\n", __func__); - goto err_notpossible; - } - - pll = pll_reg + index; - - s3c_freq_dbg("%s: target %u => %u\n", - __func__, target_freq, pll->frequency); - - target_freq = pll->frequency; - } - - return s3c_cpufreq_settarget(policy, target_freq, pll); - - err_notpossible: - printk(KERN_ERR "no compatible settings for %d\n", target_freq); - return -EINVAL; -} - -static unsigned int s3c_cpufreq_get(unsigned int cpu) -{ - return clk_get_rate(clk_arm) / 1000; -} - -struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name) -{ - struct clk *clk; - - clk = clk_get(dev, name); - if (IS_ERR(clk)) - printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name); - - return clk; -} - -static int s3c_cpufreq_init(struct cpufreq_policy *policy) -{ - printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy); - - if (policy->cpu != 0) - return -EINVAL; - - policy->cur = s3c_cpufreq_get(0); - policy->min = policy->cpuinfo.min_freq = 0; - policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000; - policy->governor = CPUFREQ_DEFAULT_GOVERNOR; - - /* feed the latency information from the cpu driver */ - policy->cpuinfo.transition_latency = cpu_cur.info->latency; - - if (ftab) - cpufreq_frequency_table_cpuinfo(policy, ftab); - - return 0; -} - -static __init int s3c_cpufreq_initclks(void) -{ - _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll"); - _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal"); - clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk"); - clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk"); - clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk"); - clk_arm = s3c_cpufreq_clk_get(NULL, "armclk"); - - if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) || - IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) { - printk(KERN_ERR "%s: could not get clock(s)\n", __func__); - return -ENOENT; - } - - printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__, - clk_get_rate(clk_fclk) / 1000, - clk_get_rate(clk_hclk) / 1000, - clk_get_rate(clk_pclk) / 1000, - clk_get_rate(clk_arm) / 1000); - - return 0; -} - -static int s3c_cpufreq_verify(struct cpufreq_policy *policy) -{ - if (policy->cpu != 0) - return -EINVAL; - - return 0; -} - -#ifdef CONFIG_PM -static struct cpufreq_frequency_table suspend_pll; -static unsigned int suspend_freq; - -static int s3c_cpufreq_suspend(struct cpufreq_policy *policy) -{ - suspend_pll.frequency = clk_get_rate(_clk_mpll); - suspend_pll.index = __raw_readl(S3C2410_MPLLCON); - suspend_freq = s3c_cpufreq_get(0) * 1000; - - return 0; -} - -static int s3c_cpufreq_resume(struct cpufreq_policy *policy) -{ - int ret; - - s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy); - - last_target = ~0; /* invalidate last_target setting */ - - /* first, find out what speed we resumed at. */ - s3c_cpufreq_resume_clocks(); - - /* whilst we will be called later on, we try and re-set the - * cpu frequencies as soon as possible so that we do not end - * up resuming devices and then immediately having to re-set - * a number of settings once these devices have restarted. - * - * as a note, it is expected devices are not used until they - * have been un-suspended and at that time they should have - * used the updated clock settings. - */ - - ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll); - if (ret) { - printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__); - return ret; - } - - return 0; -} -#else -#define s3c_cpufreq_resume NULL -#define s3c_cpufreq_suspend NULL -#endif - -static struct cpufreq_driver s3c24xx_driver = { - .flags = CPUFREQ_STICKY, - .verify = s3c_cpufreq_verify, - .target = s3c_cpufreq_target, - .get = s3c_cpufreq_get, - .init = s3c_cpufreq_init, - .suspend = s3c_cpufreq_suspend, - .resume = s3c_cpufreq_resume, - .name = "s3c24xx", -}; - - -int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info) -{ - if (!info || !info->name) { - printk(KERN_ERR "%s: failed to pass valid information\n", - __func__); - return -EINVAL; - } - - printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n", - info->name); - - /* check our driver info has valid data */ - - BUG_ON(info->set_refresh == NULL); - BUG_ON(info->set_divs == NULL); - BUG_ON(info->calc_divs == NULL); - - /* info->set_fvco is optional, depending on whether there - * is a need to set the clock code. */ - - cpu_cur.info = info; - - /* Note, driver registering should probably update locktime */ - - return 0; -} - -int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) -{ - struct s3c_cpufreq_board *ours; - - if (!board) { - printk(KERN_INFO "%s: no board data\n", __func__); - return -EINVAL; - } - - /* Copy the board information so that each board can make this - * initdata. */ - - ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL); - if (ours == NULL) { - printk(KERN_ERR "%s: no memory\n", __func__); - return -ENOMEM; - } - - *ours = *board; - cpu_cur.board = ours; - - return 0; -} - -int __init s3c_cpufreq_auto_io(void) -{ - int ret; - - if (!cpu_cur.info->get_iotiming) { - printk(KERN_ERR "%s: get_iotiming undefined\n", __func__); - return -ENOENT; - } - - printk(KERN_INFO "%s: working out IO settings\n", __func__); - - ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming); - if (ret) - printk(KERN_ERR "%s: failed to get timings\n", __func__); - - return ret; -} - -/* if one or is zero, then return the other, otherwise return the min */ -#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b)) - -/** - * s3c_cpufreq_freq_min - find the minimum settings for the given freq. - * @dst: The destination structure - * @a: One argument. - * @b: The other argument. - * - * Create a minimum of each frequency entry in the 'struct s3c_freq', - * unless the entry is zero when it is ignored and the non-zero argument - * used. - */ -static void s3c_cpufreq_freq_min(struct s3c_freq *dst, - struct s3c_freq *a, struct s3c_freq *b) -{ - dst->fclk = do_min(a->fclk, b->fclk); - dst->hclk = do_min(a->hclk, b->hclk); - dst->pclk = do_min(a->pclk, b->pclk); - dst->armclk = do_min(a->armclk, b->armclk); -} - -static inline u32 calc_locktime(u32 freq, u32 time_us) -{ - u32 result; - - result = freq * time_us; - result = DIV_ROUND_UP(result, 1000 * 1000); - - return result; -} - -static void s3c_cpufreq_update_loctkime(void) -{ - unsigned int bits = cpu_cur.info->locktime_bits; - u32 rate = (u32)clk_get_rate(_clk_xtal); - u32 val; - - if (bits == 0) { - WARN_ON(1); - return; - } - - val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits; - val |= calc_locktime(rate, cpu_cur.info->locktime_m); - - printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val); - __raw_writel(val, S3C2410_LOCKTIME); -} - -static int s3c_cpufreq_build_freq(void) -{ - int size, ret; - - if (!cpu_cur.info->calc_freqtable) - return -EINVAL; - - kfree(ftab); - ftab = NULL; - - size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0); - size++; - - ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL); - if (!ftab) { - printk(KERN_ERR "%s: no memory for tables\n", __func__); - return -ENOMEM; - } - - ftab_size = size; - - ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size); - s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END); - - return 0; -} - -static int __init s3c_cpufreq_initcall(void) -{ - int ret = 0; - - if (cpu_cur.info && cpu_cur.board) { - ret = s3c_cpufreq_initclks(); - if (ret) - goto out; - - /* get current settings */ - s3c_cpufreq_getcur(&cpu_cur); - s3c_cpufreq_show("cur", &cpu_cur); - - if (cpu_cur.board->auto_io) { - ret = s3c_cpufreq_auto_io(); - if (ret) { - printk(KERN_ERR "%s: failed to get io timing\n", - __func__); - goto out; - } - } - - if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) { - printk(KERN_ERR "%s: no IO support registered\n", - __func__); - ret = -EINVAL; - goto out; - } - - if (!cpu_cur.info->need_pll) - cpu_cur.lock_pll = 1; - - s3c_cpufreq_update_loctkime(); - - s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max, - &cpu_cur.info->max); - - if (cpu_cur.info->calc_freqtable) - s3c_cpufreq_build_freq(); - - ret = cpufreq_register_driver(&s3c24xx_driver); - } - - out: - return ret; -} - -late_initcall(s3c_cpufreq_initcall); - -/** - * s3c_plltab_register - register CPU PLL table. - * @plls: The list of PLL entries. - * @plls_no: The size of the PLL entries @plls. - * - * Register the given set of PLLs with the system. - */ -int __init s3c_plltab_register(struct cpufreq_frequency_table *plls, - unsigned int plls_no) -{ - struct cpufreq_frequency_table *vals; - unsigned int size; - - size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1); - - vals = kmalloc(size, GFP_KERNEL); - if (vals) { - memcpy(vals, plls, size); - pll_reg = vals; - - /* write a terminating entry, we don't store it in the - * table that is stored in the kernel */ - vals += plls_no; - vals->frequency = CPUFREQ_TABLE_END; - - printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no); - } else - printk(KERN_ERR "cpufreq: no memory for PLL tables\n"); - - return vals ? 0 : -ENOMEM; -} diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h new file mode 100644 index 000000000000..548ced42cbb7 --- /dev/null +++ b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H +#define __ARCH_ARM_REGS_S3C24XX_S3C2412_H __FILE__ + +#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) +#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) + +#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x)) +#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o))) + +#define S3C2412_REFRESH S3C2412_MEMREG(0x10) + +#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x4) + +#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x0) + +#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_H */ diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c index 663436d9db01..bd064c05c473 100644 --- a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c +++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c @@ -31,7 +31,7 @@ #include #include -#include "s3c2412.h" +#include #define print_ns(x) ((x) / 10), ((x) % 10) diff --git a/arch/arm/mach-s3c24xx/s3c2412.h b/arch/arm/mach-s3c24xx/s3c2412.h deleted file mode 100644 index 548ced42cbb7..000000000000 --- a/arch/arm/mach-s3c24xx/s3c2412.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H -#define __ARCH_ARM_REGS_S3C24XX_S3C2412_H __FILE__ - -#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) - -#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x)) -#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o))) - -#define S3C2412_REFRESH S3C2412_MEMREG(0x10) - -#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x4) - -#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x0) - -#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_H */ diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h index 95509d8eb140..d7e17150028a 100644 --- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h +++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h @@ -202,7 +202,7 @@ extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void); extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void); -#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS +#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS #define s3c_cpufreq_debugfs_call(x) x #else #define s3c_cpufreq_debugfs_call(x) NULL @@ -259,17 +259,17 @@ extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, #define s3c2412_iotiming_set NULL #endif /* CONFIG_S3C2412_IOTIMING */ -#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG +#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG #define s3c_freq_dbg(x...) printk(KERN_INFO x) #else #define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0) -#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */ +#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */ -#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG +#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG #define s3c_freq_iodbg(x...) printk(KERN_INFO x) #else #define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0) -#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */ +#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */ static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table, int index, size_t table_size, diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq.h b/arch/arm/plat-samsung/include/plat/cpu-freq.h index 80c4a809c721..85517ab962ae 100644 --- a/arch/arm/plat-samsung/include/plat/cpu-freq.h +++ b/arch/arm/plat-samsung/include/plat/cpu-freq.h @@ -126,7 +126,7 @@ struct s3c_cpufreq_board { }; /* Things depending on frequency scaling. */ -#ifdef CONFIG_CPU_FREQ_S3C +#ifdef CONFIG_ARM_S3C_CPUFREQ #define __init_or_cpufreq #else #define __init_or_cpufreq __init @@ -134,7 +134,7 @@ struct s3c_cpufreq_board { /* Board functions */ -#ifdef CONFIG_CPU_FREQ_S3C +#ifdef CONFIG_ARM_S3C_CPUFREQ extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board); #else @@ -142,4 +142,4 @@ static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) { return 0; } -#endif /* CONFIG_CPU_FREQ_S3C */ +#endif /* CONFIG_ARM_S3C_CPUFREQ */ diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index f3af18b9acc5..bbcd7199257b 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -95,6 +95,56 @@ config ARM_OMAP2PLUS_CPUFREQ default ARCH_OMAP2PLUS select CPU_FREQ_TABLE +config ARM_S3C_CPUFREQ + bool + help + Internal configuration node for common cpufreq on Samsung SoC + +config ARM_S3C24XX_CPUFREQ + bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" + depends on ARCH_S3C24XX + select ARM_S3C_CPUFREQ + help + This enables the CPUfreq driver for the Samsung S3C24XX family + of CPUs. + + For details, take a look at . + + If in doubt, say N. + +config ARM_S3C24XX_CPUFREQ_DEBUG + bool "Debug CPUfreq Samsung driver core" + depends on ARM_S3C24XX_CPUFREQ + help + Enable s3c_freq_dbg for the Samsung S3C CPUfreq core + +config ARM_S3C24XX_CPUFREQ_IODEBUG + bool "Debug CPUfreq Samsung driver IO timing" + depends on ARM_S3C24XX_CPUFREQ + help + Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core + +config ARM_S3C24XX_CPUFREQ_DEBUGFS + bool "Export debugfs for CPUFreq" + depends on ARM_S3C24XX_CPUFREQ && DEBUG_FS + help + Export status information via debugfs. + +config ARM_S3C2410_CPUFREQ + bool + depends on ARM_S3C24XX_CPUFREQ && CPU_S3C2410 + select S3C2410_CPUFREQ_UTILS + help + CPU Frequency scaling support for S3C2410 + +config ARM_S3C2412_CPUFREQ + bool + depends on ARM_S3C24XX_CPUFREQ && CPU_S3C2412 + default y + select S3C2412_IOTIMING + help + CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs. + config ARM_S3C2416_CPUFREQ bool "S3C2416 CPU Frequency scaling support" depends on CPU_S3C2416 @@ -117,6 +167,14 @@ config ARM_S3C2416_CPUFREQ_VCORESCALE If in doubt, say N. +config ARM_S3C2440_CPUFREQ + bool "S3C2440/S3C2442 CPU Frequency scaling support" + depends on ARM_S3C24XX_CPUFREQ && (CPU_S3C2440 || CPU_S3C2442) + select S3C2410_CPUFREQ_UTILS + default y + help + CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs. + config ARM_S3C64XX_CPUFREQ bool "Samsung S3C64XX" depends on CPU_S3C6410 diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 315b9231feb1..6ad0b913ca17 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -65,7 +65,12 @@ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_PXA25x) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA27x) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o +obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += s3c24xx-cpufreq.o +obj-$(CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS) += s3c24xx-cpufreq-debugfs.o +obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o +obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o +obj-$(CONFIG_ARM_S3C2440_CPUFREQ) += s3c2440-cpufreq.o obj-$(CONFIG_ARM_S3C64XX_CPUFREQ) += s3c64xx-cpufreq.o obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o obj-$(CONFIG_ARM_SA1100_CPUFREQ) += sa1100-cpufreq.o diff --git a/drivers/cpufreq/s3c2410-cpufreq.c b/drivers/cpufreq/s3c2410-cpufreq.c new file mode 100644 index 000000000000..cfa0dd8723ec --- /dev/null +++ b/drivers/cpufreq/s3c2410-cpufreq.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2006-2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C2410 CPU Frequency scaling + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include + +/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */ + +static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) +{ + u32 clkdiv = 0; + + if (cfg->divs.h_divisor == 2) + clkdiv |= S3C2410_CLKDIVN_HDIVN; + + if (cfg->divs.p_divisor != cfg->divs.h_divisor) + clkdiv |= S3C2410_CLKDIVN_PDIVN; + + __raw_writel(clkdiv, S3C2410_CLKDIVN); +} + +static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) +{ + unsigned long hclk, fclk, pclk; + unsigned int hdiv, pdiv; + unsigned long hclk_max; + + fclk = cfg->freq.fclk; + hclk_max = cfg->max.hclk; + + cfg->freq.armclk = fclk; + + s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n", + __func__, fclk, hclk_max); + + hdiv = (fclk > cfg->max.hclk) ? 2 : 1; + hclk = fclk / hdiv; + + if (hclk > cfg->max.hclk) { + s3c_freq_dbg("%s: hclk too big\n", __func__); + return -EINVAL; + } + + pdiv = (hclk > cfg->max.pclk) ? 2 : 1; + pclk = hclk / pdiv; + + if (pclk > cfg->max.pclk) { + s3c_freq_dbg("%s: pclk too big\n", __func__); + return -EINVAL; + } + + pdiv *= hdiv; + + /* record the result */ + cfg->divs.p_divisor = pdiv; + cfg->divs.h_divisor = hdiv; + + return 0; +} + +static struct s3c_cpufreq_info s3c2410_cpufreq_info = { + .max = { + .fclk = 200000000, + .hclk = 100000000, + .pclk = 50000000, + }, + + /* transition latency is about 5ms worst-case, so + * set 10ms to be sure */ + .latency = 10000000, + + .locktime_m = 150, + .locktime_u = 150, + .locktime_bits = 12, + + .need_pll = 1, + + .name = "s3c2410", + .calc_iotiming = s3c2410_iotiming_calc, + .set_iotiming = s3c2410_iotiming_set, + .get_iotiming = s3c2410_iotiming_get, + .resume_clocks = s3c2410_setup_clocks, + + .set_fvco = s3c2410_set_fvco, + .set_refresh = s3c2410_cpufreq_setrefresh, + .set_divs = s3c2410_cpufreq_setdivs, + .calc_divs = s3c2410_cpufreq_calcdivs, + + .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), +}; + +static int s3c2410_cpufreq_add(struct device *dev, + struct subsys_interface *sif) +{ + return s3c_cpufreq_register(&s3c2410_cpufreq_info); +} + +static struct subsys_interface s3c2410_cpufreq_interface = { + .name = "s3c2410_cpufreq", + .subsys = &s3c2410_subsys, + .add_dev = s3c2410_cpufreq_add, +}; + +static int __init s3c2410_cpufreq_init(void) +{ + return subsys_interface_register(&s3c2410_cpufreq_interface); +} +arch_initcall(s3c2410_cpufreq_init); + +static int s3c2410a_cpufreq_add(struct device *dev, + struct subsys_interface *sif) +{ + /* alter the maximum freq settings for S3C2410A. If a board knows + * it only has a maximum of 200, then it should register its own + * limits. */ + + s3c2410_cpufreq_info.max.fclk = 266000000; + s3c2410_cpufreq_info.max.hclk = 133000000; + s3c2410_cpufreq_info.max.pclk = 66500000; + s3c2410_cpufreq_info.name = "s3c2410a"; + + return s3c2410_cpufreq_add(dev, sif); +} + +static struct subsys_interface s3c2410a_cpufreq_interface = { + .name = "s3c2410a_cpufreq", + .subsys = &s3c2410a_subsys, + .add_dev = s3c2410a_cpufreq_add, +}; + +static int __init s3c2410a_cpufreq_init(void) +{ + return subsys_interface_register(&s3c2410a_cpufreq_interface); +} +arch_initcall(s3c2410a_cpufreq_init); diff --git a/drivers/cpufreq/s3c2412-cpufreq.c b/drivers/cpufreq/s3c2412-cpufreq.c new file mode 100644 index 000000000000..4645b4898996 --- /dev/null +++ b/drivers/cpufreq/s3c2412-cpufreq.c @@ -0,0 +1,257 @@ +/* + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C2412 CPU Frequency scalling + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include +#include + +/* our clock resources. */ +static struct clk *xtal; +static struct clk *fclk; +static struct clk *hclk; +static struct clk *armclk; + +/* HDIV: 1, 2, 3, 4, 6, 8 */ + +static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) +{ + unsigned int hdiv, pdiv, armdiv, dvs; + unsigned long hclk, fclk, armclk, armdiv_clk; + unsigned long hclk_max; + + fclk = cfg->freq.fclk; + armclk = cfg->freq.armclk; + hclk_max = cfg->max.hclk; + + /* We can't run hclk above armclk as at the best we have to + * have armclk and hclk in dvs mode. */ + + if (hclk_max > armclk) + hclk_max = armclk; + + s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n", + __func__, fclk, armclk, hclk_max); + s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n", + __func__, cfg->freq.fclk, cfg->freq.armclk, + cfg->freq.hclk, cfg->freq.pclk); + + armdiv = fclk / armclk; + + if (armdiv < 1) + armdiv = 1; + if (armdiv > 2) + armdiv = 2; + + cfg->divs.arm_divisor = armdiv; + armdiv_clk = fclk / armdiv; + + hdiv = armdiv_clk / hclk_max; + if (hdiv < 1) + hdiv = 1; + + cfg->freq.hclk = hclk = armdiv_clk / hdiv; + + /* set dvs depending on whether we reached armclk or not. */ + cfg->divs.dvs = dvs = armclk < armdiv_clk; + + /* update the actual armclk we achieved. */ + cfg->freq.armclk = dvs ? hclk : armdiv_clk; + + s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n", + __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs); + + if (hdiv > 4) + goto invalid; + + pdiv = (hclk > cfg->max.pclk) ? 2 : 1; + + if ((hclk / pdiv) > cfg->max.pclk) + pdiv++; + + cfg->freq.pclk = hclk / pdiv; + + s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); + + if (pdiv > 2) + goto invalid; + + pdiv *= hdiv; + + /* store the result, and then return */ + + cfg->divs.h_divisor = hdiv * armdiv; + cfg->divs.p_divisor = pdiv * armdiv; + + return 0; + +invalid: + return -EINVAL; +} + +static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) +{ + unsigned long clkdiv; + unsigned long olddiv; + + olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN); + + /* clear off current clock info */ + + clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN; + clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK; + clkdiv &= ~S3C2412_CLKDIVN_PDIVN; + + if (cfg->divs.arm_divisor == 2) + clkdiv |= S3C2412_CLKDIVN_ARMDIVN; + + clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1); + + if (cfg->divs.p_divisor != cfg->divs.h_divisor) + clkdiv |= S3C2412_CLKDIVN_PDIVN; + + s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv); + __raw_writel(clkdiv, S3C2410_CLKDIVN); + + clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); +} + +static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) +{ + struct s3c_cpufreq_board *board = cfg->board; + unsigned long refresh; + + s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__, + board->refresh, cfg->freq.hclk); + + /* Reduce both the refresh time (in ns) and the frequency (in MHz) + * by 10 each to ensure that we do not overflow 32 bit numbers. This + * should work for HCLK up to 133MHz and refresh period up to 30usec. + */ + + refresh = (board->refresh / 10); + refresh *= (cfg->freq.hclk / 100); + refresh /= (1 * 1000 * 1000); /* 10^6 */ + + s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh); + __raw_writel(refresh, S3C2412_REFRESH); +} + +/* set the default cpu frequency information, based on an 200MHz part + * as we have no other way of detecting the speed rating in software. + */ + +static struct s3c_cpufreq_info s3c2412_cpufreq_info = { + .max = { + .fclk = 200000000, + .hclk = 100000000, + .pclk = 50000000, + }, + + .latency = 5000000, /* 5ms */ + + .locktime_m = 150, + .locktime_u = 150, + .locktime_bits = 16, + + .name = "s3c2412", + .set_refresh = s3c2412_cpufreq_setrefresh, + .set_divs = s3c2412_cpufreq_setdivs, + .calc_divs = s3c2412_cpufreq_calcdivs, + + .calc_iotiming = s3c2412_iotiming_calc, + .set_iotiming = s3c2412_iotiming_set, + .get_iotiming = s3c2412_iotiming_get, + + .resume_clocks = s3c2412_setup_clocks, + + .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs), +}; + +static int s3c2412_cpufreq_add(struct device *dev, + struct subsys_interface *sif) +{ + unsigned long fclk_rate; + + hclk = clk_get(NULL, "hclk"); + if (IS_ERR(hclk)) { + printk(KERN_ERR "%s: cannot find hclk clock\n", __func__); + return -ENOENT; + } + + fclk = clk_get(NULL, "fclk"); + if (IS_ERR(fclk)) { + printk(KERN_ERR "%s: cannot find fclk clock\n", __func__); + goto err_fclk; + } + + fclk_rate = clk_get_rate(fclk); + if (fclk_rate > 200000000) { + printk(KERN_INFO + "%s: fclk %ld MHz, assuming 266MHz capable part\n", + __func__, fclk_rate / 1000000); + s3c2412_cpufreq_info.max.fclk = 266000000; + s3c2412_cpufreq_info.max.hclk = 133000000; + s3c2412_cpufreq_info.max.pclk = 66000000; + } + + armclk = clk_get(NULL, "armclk"); + if (IS_ERR(armclk)) { + printk(KERN_ERR "%s: cannot find arm clock\n", __func__); + goto err_armclk; + } + + xtal = clk_get(NULL, "xtal"); + if (IS_ERR(xtal)) { + printk(KERN_ERR "%s: cannot find xtal clock\n", __func__); + goto err_xtal; + } + + return s3c_cpufreq_register(&s3c2412_cpufreq_info); + +err_xtal: + clk_put(armclk); +err_armclk: + clk_put(fclk); +err_fclk: + clk_put(hclk); + + return -ENOENT; +} + +static struct subsys_interface s3c2412_cpufreq_interface = { + .name = "s3c2412_cpufreq", + .subsys = &s3c2412_subsys, + .add_dev = s3c2412_cpufreq_add, +}; + +static int s3c2412_cpufreq_init(void) +{ + return subsys_interface_register(&s3c2412_cpufreq_interface); +} +arch_initcall(s3c2412_cpufreq_init); diff --git a/drivers/cpufreq/s3c2440-cpufreq.c b/drivers/cpufreq/s3c2440-cpufreq.c new file mode 100644 index 000000000000..72b2cc8a5a85 --- /dev/null +++ b/drivers/cpufreq/s3c2440-cpufreq.c @@ -0,0 +1,312 @@ +/* + * Copyright (c) 2006-2009 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * Vincent Sanders + * + * S3C2440/S3C2442 CPU Frequency scaling + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include + +#include +#include +#include + +static struct clk *xtal; +static struct clk *fclk; +static struct clk *hclk; +static struct clk *armclk; + +/* HDIV: 1, 2, 3, 4, 6, 8 */ + +static inline int within_khz(unsigned long a, unsigned long b) +{ + long diff = a - b; + + return (diff >= -1000 && diff <= 1000); +} + +/** + * s3c2440_cpufreq_calcdivs - calculate divider settings + * @cfg: The cpu frequency settings. + * + * Calcualte the divider values for the given frequency settings + * specified in @cfg. The values are stored in @cfg for later use + * by the relevant set routine if the request settings can be reached. + */ +int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) +{ + unsigned int hdiv, pdiv; + unsigned long hclk, fclk, armclk; + unsigned long hclk_max; + + fclk = cfg->freq.fclk; + armclk = cfg->freq.armclk; + hclk_max = cfg->max.hclk; + + s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n", + __func__, fclk, armclk, hclk_max); + + if (armclk > fclk) { + printk(KERN_WARNING "%s: armclk > fclk\n", __func__); + armclk = fclk; + } + + /* if we are in DVS, we need HCLK to be <= ARMCLK */ + if (armclk < fclk && armclk < hclk_max) + hclk_max = armclk; + + for (hdiv = 1; hdiv < 9; hdiv++) { + if (hdiv == 5 || hdiv == 7) + hdiv++; + + hclk = (fclk / hdiv); + if (hclk <= hclk_max || within_khz(hclk, hclk_max)) + break; + } + + s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv); + + if (hdiv > 8) + goto invalid; + + pdiv = (hclk > cfg->max.pclk) ? 2 : 1; + + if ((hclk / pdiv) > cfg->max.pclk) + pdiv++; + + s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); + + if (pdiv > 2) + goto invalid; + + pdiv *= hdiv; + + /* calculate a valid armclk */ + + if (armclk < hclk) + armclk = hclk; + + /* if we're running armclk lower than fclk, this really means + * that the system should go into dvs mode, which means that + * armclk is connected to hclk. */ + if (armclk < fclk) { + cfg->divs.dvs = 1; + armclk = hclk; + } else + cfg->divs.dvs = 0; + + cfg->freq.armclk = armclk; + + /* store the result, and then return */ + + cfg->divs.h_divisor = hdiv; + cfg->divs.p_divisor = pdiv; + + return 0; + + invalid: + return -EINVAL; +} + +#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \ + S3C2440_CAMDIVN_HCLK4_HALF) + +/** + * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings + * @cfg: The cpu frequency settings. + * + * Set the divisors from the settings in @cfg, which where generated + * during the calculation phase by s3c2440_cpufreq_calcdivs(). + */ +static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) +{ + unsigned long clkdiv, camdiv; + + s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__, + cfg->divs.h_divisor, cfg->divs.p_divisor); + + clkdiv = __raw_readl(S3C2410_CLKDIVN); + camdiv = __raw_readl(S3C2440_CAMDIVN); + + clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN); + camdiv &= ~CAMDIVN_HCLK_HALF; + + switch (cfg->divs.h_divisor) { + case 1: + clkdiv |= S3C2440_CLKDIVN_HDIVN_1; + break; + + case 2: + clkdiv |= S3C2440_CLKDIVN_HDIVN_2; + break; + + case 6: + camdiv |= S3C2440_CAMDIVN_HCLK3_HALF; + case 3: + clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6; + break; + + case 8: + camdiv |= S3C2440_CAMDIVN_HCLK4_HALF; + case 4: + clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8; + break; + + default: + BUG(); /* we don't expect to get here. */ + } + + if (cfg->divs.p_divisor != cfg->divs.h_divisor) + clkdiv |= S3C2440_CLKDIVN_PDIVN; + + /* todo - set pclk. */ + + /* Write the divisors first with hclk intentionally halved so that + * when we write clkdiv we will under-frequency instead of over. We + * then make a short delay and remove the hclk halving if necessary. + */ + + __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN); + __raw_writel(clkdiv, S3C2410_CLKDIVN); + + ndelay(20); + __raw_writel(camdiv, S3C2440_CAMDIVN); + + clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); +} + +static int run_freq_for(unsigned long max_hclk, unsigned long fclk, + int *divs, + struct cpufreq_frequency_table *table, + size_t table_size) +{ + unsigned long freq; + int index = 0; + int div; + + for (div = *divs; div > 0; div = *divs++) { + freq = fclk / div; + + if (freq > max_hclk && div != 1) + continue; + + freq /= 1000; /* table is in kHz */ + index = s3c_cpufreq_addfreq(table, index, table_size, freq); + if (index < 0) + break; + } + + return index; +} + +static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 }; + +static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg, + struct cpufreq_frequency_table *table, + size_t table_size) +{ + int ret; + + WARN_ON(cfg->info == NULL); + WARN_ON(cfg->board == NULL); + + ret = run_freq_for(cfg->info->max.hclk, + cfg->info->max.fclk, + hclk_divs, + table, table_size); + + s3c_freq_dbg("%s: returning %d\n", __func__, ret); + + return ret; +} + +struct s3c_cpufreq_info s3c2440_cpufreq_info = { + .max = { + .fclk = 400000000, + .hclk = 133333333, + .pclk = 66666666, + }, + + .locktime_m = 300, + .locktime_u = 300, + .locktime_bits = 16, + + .name = "s3c244x", + .calc_iotiming = s3c2410_iotiming_calc, + .set_iotiming = s3c2410_iotiming_set, + .get_iotiming = s3c2410_iotiming_get, + .set_fvco = s3c2410_set_fvco, + + .set_refresh = s3c2410_cpufreq_setrefresh, + .set_divs = s3c2440_cpufreq_setdivs, + .calc_divs = s3c2440_cpufreq_calcdivs, + .calc_freqtable = s3c2440_cpufreq_calctable, + + .resume_clocks = s3c244x_setup_clocks, + + .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), +}; + +static int s3c2440_cpufreq_add(struct device *dev, + struct subsys_interface *sif) +{ + xtal = s3c_cpufreq_clk_get(NULL, "xtal"); + hclk = s3c_cpufreq_clk_get(NULL, "hclk"); + fclk = s3c_cpufreq_clk_get(NULL, "fclk"); + armclk = s3c_cpufreq_clk_get(NULL, "armclk"); + + if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) { + printk(KERN_ERR "%s: failed to get clocks\n", __func__); + return -ENOENT; + } + + return s3c_cpufreq_register(&s3c2440_cpufreq_info); +} + +static struct subsys_interface s3c2440_cpufreq_interface = { + .name = "s3c2440_cpufreq", + .subsys = &s3c2440_subsys, + .add_dev = s3c2440_cpufreq_add, +}; + +static int s3c2440_cpufreq_init(void) +{ + return subsys_interface_register(&s3c2440_cpufreq_interface); +} + +/* arch_initcall adds the clocks we need, so use subsys_initcall. */ +subsys_initcall(s3c2440_cpufreq_init); + +static struct subsys_interface s3c2442_cpufreq_interface = { + .name = "s3c2442_cpufreq", + .subsys = &s3c2442_subsys, + .add_dev = s3c2440_cpufreq_add, +}; + +static int s3c2442_cpufreq_init(void) +{ + return subsys_interface_register(&s3c2442_cpufreq_interface); +} +subsys_initcall(s3c2442_cpufreq_init); diff --git a/drivers/cpufreq/s3c24xx-cpufreq-debugfs.c b/drivers/cpufreq/s3c24xx-cpufreq-debugfs.c new file mode 100644 index 000000000000..9b7b4289d66c --- /dev/null +++ b/drivers/cpufreq/s3c24xx-cpufreq-debugfs.c @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2009 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C24XX CPU Frequency scaling - debugfs status support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static struct dentry *dbgfs_root; +static struct dentry *dbgfs_file_io; +static struct dentry *dbgfs_file_info; +static struct dentry *dbgfs_file_board; + +#define print_ns(x) ((x) / 10), ((x) % 10) + +static void show_max(struct seq_file *seq, struct s3c_freq *f) +{ + seq_printf(seq, "MAX: F=%lu, H=%lu, P=%lu, A=%lu\n", + f->fclk, f->hclk, f->pclk, f->armclk); +} + +static int board_show(struct seq_file *seq, void *p) +{ + struct s3c_cpufreq_config *cfg; + struct s3c_cpufreq_board *brd; + + cfg = s3c_cpufreq_getconfig(); + if (!cfg) { + seq_printf(seq, "no configuration registered\n"); + return 0; + } + + brd = cfg->board; + if (!brd) { + seq_printf(seq, "no board definition set?\n"); + return 0; + } + + seq_printf(seq, "SDRAM refresh %u ns\n", brd->refresh); + seq_printf(seq, "auto_io=%u\n", brd->auto_io); + seq_printf(seq, "need_io=%u\n", brd->need_io); + + show_max(seq, &brd->max); + + + return 0; +} + +static int fops_board_open(struct inode *inode, struct file *file) +{ + return single_open(file, board_show, NULL); +} + +static const struct file_operations fops_board = { + .open = fops_board_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .owner = THIS_MODULE, +}; + +static int info_show(struct seq_file *seq, void *p) +{ + struct s3c_cpufreq_config *cfg; + + cfg = s3c_cpufreq_getconfig(); + if (!cfg) { + seq_printf(seq, "no configuration registered\n"); + return 0; + } + + seq_printf(seq, " FCLK %ld Hz\n", cfg->freq.fclk); + seq_printf(seq, " HCLK %ld Hz (%lu.%lu ns)\n", + cfg->freq.hclk, print_ns(cfg->freq.hclk_tns)); + seq_printf(seq, " PCLK %ld Hz\n", cfg->freq.hclk); + seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk); + seq_printf(seq, "\n"); + + show_max(seq, &cfg->max); + + seq_printf(seq, "Divisors: P=%d, H=%d, A=%d, dvs=%s\n", + cfg->divs.h_divisor, cfg->divs.p_divisor, + cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off"); + seq_printf(seq, "\n"); + + seq_printf(seq, "lock_pll=%u\n", cfg->lock_pll); + + return 0; +} + +static int fops_info_open(struct inode *inode, struct file *file) +{ + return single_open(file, info_show, NULL); +} + +static const struct file_operations fops_info = { + .open = fops_info_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .owner = THIS_MODULE, +}; + +static int io_show(struct seq_file *seq, void *p) +{ + void (*show_bank)(struct seq_file *, struct s3c_cpufreq_config *, union s3c_iobank *); + struct s3c_cpufreq_config *cfg; + struct s3c_iotimings *iot; + union s3c_iobank *iob; + int bank; + + cfg = s3c_cpufreq_getconfig(); + if (!cfg) { + seq_printf(seq, "no configuration registered\n"); + return 0; + } + + show_bank = cfg->info->debug_io_show; + if (!show_bank) { + seq_printf(seq, "no code to show bank timing\n"); + return 0; + } + + iot = s3c_cpufreq_getiotimings(); + if (!iot) { + seq_printf(seq, "no io timings registered\n"); + return 0; + } + + seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns)); + + for (bank = 0; bank < MAX_BANKS; bank++) { + iob = &iot->bank[bank]; + + seq_printf(seq, "bank %d: ", bank); + + if (!iob->io_2410) { + seq_printf(seq, "nothing set\n"); + continue; + } + + show_bank(seq, cfg, iob); + } + + return 0; +} + +static int fops_io_open(struct inode *inode, struct file *file) +{ + return single_open(file, io_show, NULL); +} + +static const struct file_operations fops_io = { + .open = fops_io_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .owner = THIS_MODULE, +}; + + +static int __init s3c_freq_debugfs_init(void) +{ + dbgfs_root = debugfs_create_dir("s3c-cpufreq", NULL); + if (IS_ERR(dbgfs_root)) { + printk(KERN_ERR "%s: error creating debugfs root\n", __func__); + return PTR_ERR(dbgfs_root); + } + + dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root, + NULL, &fops_io); + + dbgfs_file_info = debugfs_create_file("info", S_IRUGO, dbgfs_root, + NULL, &fops_info); + + dbgfs_file_board = debugfs_create_file("board", S_IRUGO, dbgfs_root, + NULL, &fops_board); + + return 0; +} + +late_initcall(s3c_freq_debugfs_init); + diff --git a/drivers/cpufreq/s3c24xx-cpufreq.c b/drivers/cpufreq/s3c24xx-cpufreq.c new file mode 100644 index 000000000000..3c0e78ede0da --- /dev/null +++ b/drivers/cpufreq/s3c24xx-cpufreq.c @@ -0,0 +1,711 @@ +/* + * Copyright (c) 2006-2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C24XX CPU Frequency scaling + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include + +/* note, cpufreq support deals in kHz, no Hz */ + +static struct cpufreq_driver s3c24xx_driver; +static struct s3c_cpufreq_config cpu_cur; +static struct s3c_iotimings s3c24xx_iotiming; +static struct cpufreq_frequency_table *pll_reg; +static unsigned int last_target = ~0; +static unsigned int ftab_size; +static struct cpufreq_frequency_table *ftab; + +static struct clk *_clk_mpll; +static struct clk *_clk_xtal; +static struct clk *clk_fclk; +static struct clk *clk_hclk; +static struct clk *clk_pclk; +static struct clk *clk_arm; + +#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS +struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void) +{ + return &cpu_cur; +} + +struct s3c_iotimings *s3c_cpufreq_getiotimings(void) +{ + return &s3c24xx_iotiming; +} +#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUGFS */ + +static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg) +{ + unsigned long fclk, pclk, hclk, armclk; + + cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); + cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); + cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); + cfg->freq.armclk = armclk = clk_get_rate(clk_arm); + + cfg->pll.index = __raw_readl(S3C2410_MPLLCON); + cfg->pll.frequency = fclk; + + cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); + + cfg->divs.h_divisor = fclk / hclk; + cfg->divs.p_divisor = fclk / pclk; +} + +static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg) +{ + unsigned long pll = cfg->pll.frequency; + + cfg->freq.fclk = pll; + cfg->freq.hclk = pll / cfg->divs.h_divisor; + cfg->freq.pclk = pll / cfg->divs.p_divisor; + + /* convert hclk into 10ths of nanoseconds for io calcs */ + cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); +} + +static inline int closer(unsigned int target, unsigned int n, unsigned int c) +{ + int diff_cur = abs(target - c); + int diff_new = abs(target - n); + + return (diff_new < diff_cur); +} + +static void s3c_cpufreq_show(const char *pfx, + struct s3c_cpufreq_config *cfg) +{ + s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n", + pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, + cfg->freq.hclk, cfg->divs.h_divisor, + cfg->freq.pclk, cfg->divs.p_divisor); +} + +/* functions to wrapper the driver info calls to do the cpu specific work */ + +static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg) +{ + if (cfg->info->set_iotiming) + (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming); +} + +static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg) +{ + if (cfg->info->calc_iotiming) + return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming); + + return 0; +} + +static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) +{ + (cfg->info->set_refresh)(cfg); +} + +static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) +{ + (cfg->info->set_divs)(cfg); +} + +static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) +{ + return (cfg->info->calc_divs)(cfg); +} + +static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg) +{ + (cfg->info->set_fvco)(cfg); +} + +static inline void s3c_cpufreq_resume_clocks(void) +{ + cpu_cur.info->resume_clocks(); +} + +static inline void s3c_cpufreq_updateclk(struct clk *clk, + unsigned int freq) +{ + clk_set_rate(clk, freq); +} + +static int s3c_cpufreq_settarget(struct cpufreq_policy *policy, + unsigned int target_freq, + struct cpufreq_frequency_table *pll) +{ + struct s3c_cpufreq_freqs freqs; + struct s3c_cpufreq_config cpu_new; + unsigned long flags; + + cpu_new = cpu_cur; /* copy new from current */ + + s3c_cpufreq_show("cur", &cpu_cur); + + /* TODO - check for DMA currently outstanding */ + + cpu_new.pll = pll ? *pll : cpu_cur.pll; + + if (pll) + freqs.pll_changing = 1; + + /* update our frequencies */ + + cpu_new.freq.armclk = target_freq; + cpu_new.freq.fclk = cpu_new.pll.frequency; + + if (s3c_cpufreq_calcdivs(&cpu_new) < 0) { + printk(KERN_ERR "no divisors for %d\n", target_freq); + goto err_notpossible; + } + + s3c_freq_dbg("%s: got divs\n", __func__); + + s3c_cpufreq_calc(&cpu_new); + + s3c_freq_dbg("%s: calculated frequencies for new\n", __func__); + + if (cpu_new.freq.hclk != cpu_cur.freq.hclk) { + if (s3c_cpufreq_calcio(&cpu_new) < 0) { + printk(KERN_ERR "%s: no IO timings\n", __func__); + goto err_notpossible; + } + } + + s3c_cpufreq_show("new", &cpu_new); + + /* setup our cpufreq parameters */ + + freqs.old = cpu_cur.freq; + freqs.new = cpu_new.freq; + + freqs.freqs.old = cpu_cur.freq.armclk / 1000; + freqs.freqs.new = cpu_new.freq.armclk / 1000; + + /* update f/h/p clock settings before we issue the change + * notification, so that drivers do not need to do anything + * special if they want to recalculate on CPUFREQ_PRECHANGE. */ + + s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency); + s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk); + s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk); + s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk); + + /* start the frequency change */ + cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_PRECHANGE); + + /* If hclk is staying the same, then we do not need to + * re-write the IO or the refresh timings whilst we are changing + * speed. */ + + local_irq_save(flags); + + /* is our memory clock slowing down? */ + if (cpu_new.freq.hclk < cpu_cur.freq.hclk) { + s3c_cpufreq_setrefresh(&cpu_new); + s3c_cpufreq_setio(&cpu_new); + } + + if (cpu_new.freq.fclk == cpu_cur.freq.fclk) { + /* not changing PLL, just set the divisors */ + + s3c_cpufreq_setdivs(&cpu_new); + } else { + if (cpu_new.freq.fclk < cpu_cur.freq.fclk) { + /* slow the cpu down, then set divisors */ + + s3c_cpufreq_setfvco(&cpu_new); + s3c_cpufreq_setdivs(&cpu_new); + } else { + /* set the divisors, then speed up */ + + s3c_cpufreq_setdivs(&cpu_new); + s3c_cpufreq_setfvco(&cpu_new); + } + } + + /* did our memory clock speed up */ + if (cpu_new.freq.hclk > cpu_cur.freq.hclk) { + s3c_cpufreq_setrefresh(&cpu_new); + s3c_cpufreq_setio(&cpu_new); + } + + /* update our current settings */ + cpu_cur = cpu_new; + + local_irq_restore(flags); + + /* notify everyone we've done this */ + cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_POSTCHANGE); + + s3c_freq_dbg("%s: finished\n", __func__); + return 0; + + err_notpossible: + printk(KERN_ERR "no compatible settings for %d\n", target_freq); + return -EINVAL; +} + +/* s3c_cpufreq_target + * + * called by the cpufreq core to adjust the frequency that the CPU + * is currently running at. + */ + +static int s3c_cpufreq_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + struct cpufreq_frequency_table *pll; + unsigned int index; + + /* avoid repeated calls which cause a needless amout of duplicated + * logging output (and CPU time as the calculation process is + * done) */ + if (target_freq == last_target) + return 0; + + last_target = target_freq; + + s3c_freq_dbg("%s: policy %p, target %u, relation %u\n", + __func__, policy, target_freq, relation); + + if (ftab) { + if (cpufreq_frequency_table_target(policy, ftab, + target_freq, relation, + &index)) { + s3c_freq_dbg("%s: table failed\n", __func__); + return -EINVAL; + } + + s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__, + target_freq, index, ftab[index].frequency); + target_freq = ftab[index].frequency; + } + + target_freq *= 1000; /* convert target to Hz */ + + /* find the settings for our new frequency */ + + if (!pll_reg || cpu_cur.lock_pll) { + /* either we've not got any PLL values, or we've locked + * to the current one. */ + pll = NULL; + } else { + struct cpufreq_policy tmp_policy; + int ret; + + /* we keep the cpu pll table in Hz, to ensure we get an + * accurate value for the PLL output. */ + + tmp_policy.min = policy->min * 1000; + tmp_policy.max = policy->max * 1000; + tmp_policy.cpu = policy->cpu; + + /* cpufreq_frequency_table_target uses a pointer to 'index' + * which is the number of the table entry, not the value of + * the table entry's index field. */ + + ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg, + target_freq, relation, + &index); + + if (ret < 0) { + printk(KERN_ERR "%s: no PLL available\n", __func__); + goto err_notpossible; + } + + pll = pll_reg + index; + + s3c_freq_dbg("%s: target %u => %u\n", + __func__, target_freq, pll->frequency); + + target_freq = pll->frequency; + } + + return s3c_cpufreq_settarget(policy, target_freq, pll); + + err_notpossible: + printk(KERN_ERR "no compatible settings for %d\n", target_freq); + return -EINVAL; +} + +static unsigned int s3c_cpufreq_get(unsigned int cpu) +{ + return clk_get_rate(clk_arm) / 1000; +} + +struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name) +{ + struct clk *clk; + + clk = clk_get(dev, name); + if (IS_ERR(clk)) + printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name); + + return clk; +} + +static int s3c_cpufreq_init(struct cpufreq_policy *policy) +{ + printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy); + + if (policy->cpu != 0) + return -EINVAL; + + policy->cur = s3c_cpufreq_get(0); + policy->min = policy->cpuinfo.min_freq = 0; + policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000; + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + + /* feed the latency information from the cpu driver */ + policy->cpuinfo.transition_latency = cpu_cur.info->latency; + + if (ftab) + cpufreq_frequency_table_cpuinfo(policy, ftab); + + return 0; +} + +static __init int s3c_cpufreq_initclks(void) +{ + _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll"); + _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal"); + clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk"); + clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk"); + clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk"); + clk_arm = s3c_cpufreq_clk_get(NULL, "armclk"); + + if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) || + IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) { + printk(KERN_ERR "%s: could not get clock(s)\n", __func__); + return -ENOENT; + } + + printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__, + clk_get_rate(clk_fclk) / 1000, + clk_get_rate(clk_hclk) / 1000, + clk_get_rate(clk_pclk) / 1000, + clk_get_rate(clk_arm) / 1000); + + return 0; +} + +static int s3c_cpufreq_verify(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -EINVAL; + + return 0; +} + +#ifdef CONFIG_PM +static struct cpufreq_frequency_table suspend_pll; +static unsigned int suspend_freq; + +static int s3c_cpufreq_suspend(struct cpufreq_policy *policy) +{ + suspend_pll.frequency = clk_get_rate(_clk_mpll); + suspend_pll.index = __raw_readl(S3C2410_MPLLCON); + suspend_freq = s3c_cpufreq_get(0) * 1000; + + return 0; +} + +static int s3c_cpufreq_resume(struct cpufreq_policy *policy) +{ + int ret; + + s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy); + + last_target = ~0; /* invalidate last_target setting */ + + /* first, find out what speed we resumed at. */ + s3c_cpufreq_resume_clocks(); + + /* whilst we will be called later on, we try and re-set the + * cpu frequencies as soon as possible so that we do not end + * up resuming devices and then immediately having to re-set + * a number of settings once these devices have restarted. + * + * as a note, it is expected devices are not used until they + * have been un-suspended and at that time they should have + * used the updated clock settings. + */ + + ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll); + if (ret) { + printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__); + return ret; + } + + return 0; +} +#else +#define s3c_cpufreq_resume NULL +#define s3c_cpufreq_suspend NULL +#endif + +static struct cpufreq_driver s3c24xx_driver = { + .flags = CPUFREQ_STICKY, + .verify = s3c_cpufreq_verify, + .target = s3c_cpufreq_target, + .get = s3c_cpufreq_get, + .init = s3c_cpufreq_init, + .suspend = s3c_cpufreq_suspend, + .resume = s3c_cpufreq_resume, + .name = "s3c24xx", +}; + + +int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info) +{ + if (!info || !info->name) { + printk(KERN_ERR "%s: failed to pass valid information\n", + __func__); + return -EINVAL; + } + + printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n", + info->name); + + /* check our driver info has valid data */ + + BUG_ON(info->set_refresh == NULL); + BUG_ON(info->set_divs == NULL); + BUG_ON(info->calc_divs == NULL); + + /* info->set_fvco is optional, depending on whether there + * is a need to set the clock code. */ + + cpu_cur.info = info; + + /* Note, driver registering should probably update locktime */ + + return 0; +} + +int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) +{ + struct s3c_cpufreq_board *ours; + + if (!board) { + printk(KERN_INFO "%s: no board data\n", __func__); + return -EINVAL; + } + + /* Copy the board information so that each board can make this + * initdata. */ + + ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL); + if (ours == NULL) { + printk(KERN_ERR "%s: no memory\n", __func__); + return -ENOMEM; + } + + *ours = *board; + cpu_cur.board = ours; + + return 0; +} + +int __init s3c_cpufreq_auto_io(void) +{ + int ret; + + if (!cpu_cur.info->get_iotiming) { + printk(KERN_ERR "%s: get_iotiming undefined\n", __func__); + return -ENOENT; + } + + printk(KERN_INFO "%s: working out IO settings\n", __func__); + + ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming); + if (ret) + printk(KERN_ERR "%s: failed to get timings\n", __func__); + + return ret; +} + +/* if one or is zero, then return the other, otherwise return the min */ +#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b)) + +/** + * s3c_cpufreq_freq_min - find the minimum settings for the given freq. + * @dst: The destination structure + * @a: One argument. + * @b: The other argument. + * + * Create a minimum of each frequency entry in the 'struct s3c_freq', + * unless the entry is zero when it is ignored and the non-zero argument + * used. + */ +static void s3c_cpufreq_freq_min(struct s3c_freq *dst, + struct s3c_freq *a, struct s3c_freq *b) +{ + dst->fclk = do_min(a->fclk, b->fclk); + dst->hclk = do_min(a->hclk, b->hclk); + dst->pclk = do_min(a->pclk, b->pclk); + dst->armclk = do_min(a->armclk, b->armclk); +} + +static inline u32 calc_locktime(u32 freq, u32 time_us) +{ + u32 result; + + result = freq * time_us; + result = DIV_ROUND_UP(result, 1000 * 1000); + + return result; +} + +static void s3c_cpufreq_update_loctkime(void) +{ + unsigned int bits = cpu_cur.info->locktime_bits; + u32 rate = (u32)clk_get_rate(_clk_xtal); + u32 val; + + if (bits == 0) { + WARN_ON(1); + return; + } + + val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits; + val |= calc_locktime(rate, cpu_cur.info->locktime_m); + + printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val); + __raw_writel(val, S3C2410_LOCKTIME); +} + +static int s3c_cpufreq_build_freq(void) +{ + int size, ret; + + if (!cpu_cur.info->calc_freqtable) + return -EINVAL; + + kfree(ftab); + ftab = NULL; + + size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0); + size++; + + ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL); + if (!ftab) { + printk(KERN_ERR "%s: no memory for tables\n", __func__); + return -ENOMEM; + } + + ftab_size = size; + + ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size); + s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END); + + return 0; +} + +static int __init s3c_cpufreq_initcall(void) +{ + int ret = 0; + + if (cpu_cur.info && cpu_cur.board) { + ret = s3c_cpufreq_initclks(); + if (ret) + goto out; + + /* get current settings */ + s3c_cpufreq_getcur(&cpu_cur); + s3c_cpufreq_show("cur", &cpu_cur); + + if (cpu_cur.board->auto_io) { + ret = s3c_cpufreq_auto_io(); + if (ret) { + printk(KERN_ERR "%s: failed to get io timing\n", + __func__); + goto out; + } + } + + if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) { + printk(KERN_ERR "%s: no IO support registered\n", + __func__); + ret = -EINVAL; + goto out; + } + + if (!cpu_cur.info->need_pll) + cpu_cur.lock_pll = 1; + + s3c_cpufreq_update_loctkime(); + + s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max, + &cpu_cur.info->max); + + if (cpu_cur.info->calc_freqtable) + s3c_cpufreq_build_freq(); + + ret = cpufreq_register_driver(&s3c24xx_driver); + } + + out: + return ret; +} + +late_initcall(s3c_cpufreq_initcall); + +/** + * s3c_plltab_register - register CPU PLL table. + * @plls: The list of PLL entries. + * @plls_no: The size of the PLL entries @plls. + * + * Register the given set of PLLs with the system. + */ +int __init s3c_plltab_register(struct cpufreq_frequency_table *plls, + unsigned int plls_no) +{ + struct cpufreq_frequency_table *vals; + unsigned int size; + + size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1); + + vals = kmalloc(size, GFP_KERNEL); + if (vals) { + memcpy(vals, plls, size); + pll_reg = vals; + + /* write a terminating entry, we don't store it in the + * table that is stored in the kernel */ + vals += plls_no; + vals->frequency = CPUFREQ_TABLE_END; + + printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no); + } else + printk(KERN_ERR "cpufreq: no memory for PLL tables\n"); + + return vals ? 0 : -ENOMEM; +}