From: Jan Hoffmann Date: Sat, 23 Jul 2022 20:53:19 +0000 (+0200) Subject: realtek: add support for HPE 1920 series X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=f2f09bc00280f5bd60b36d525a5e229550958b6d;p=openwrt%2Fstaging%2Fstintel.git realtek: add support for HPE 1920 series Hardware information: --------------------- - HPE 1920-8G: - RTL8380 SoC - 8 Gigabit RJ45 ports (built-in RTL8218B) - 2 SFP ports (built-in SerDes) - HPE 1920-16G / HPE 1920-24G (same board): - RTL8382 SoC - 16/24 Gigabit RJ45 ports (built-in RTL8218B, 1/2 external RTL8218D) - 4 SFP ports (external RTL8214FC) - Common: - RJ45 RS232 port on front panel - 32 MiB NOR Flash - 128 MiB DDR3 DRAM - PT7A7514 watchdog Booting initramfs image: ------------------------ - Prepare a FTP or TFTP server serving the OpenWrt initramfs image and connect the server to a switch port. - Connect to the console port of the device and enter the extended boot menu by typing Ctrl+B when prompted. - Choose the menu option "<3> Enter Ethernet SubMenu". - Set network parameters via the option "<5> Modify Ethernet Parameter". Enter the FTP/TFTP filename as "Load File Name" ("Target File Name" can be left blank, it is not required for booting from RAM). Note that the configuration is saved on flash, so it only needs to be done once. - Select "<1> Download Application Program To SDRAM And Run". Initial installation: --------------------- - Boot an initramfs image as described above, then use sysupgrade to install OpenWrt permanently. After initial installation, the bootloader needs to be configured to load the correct image file - Enter the extended boot menu again and choose "<4> File Control", then select "<2> Set Application File type". - Enter the number of the file "openwrt-kernel.bin" (should be 1), and use the option "<1> +Main" to select it as boot image. - Choose "<0> Exit To Main Menu" and then "<1> Boot System". NOTE: The bootloader on these devices can only boot from the VFS filesystem which normally spans most of the flash. With OpenWrt, only the first part of the firmware partition contains a valid filesystem, the rest is used for rootfs. As the bootloader does not know about this, you must not do any file operations in the bootloader, as this may corrupt the OpenWrt installation (selecting the boot image is an exception, as it only stores a flag in the bootloader data, but doesn't write to the filesystem). Signed-off-by: Jan Hoffmann --- diff --git a/target/linux/realtek/base-files/etc/board.d/02_network b/target/linux/realtek/base-files/etc/board.d/02_network index af9db848dd..5356bcac65 100644 --- a/target/linux/realtek/base-files/etc/board.d/02_network +++ b/target/linux/realtek/base-files/etc/board.d/02_network @@ -22,9 +22,20 @@ ucidef_set_bridge_device switch ucidef_set_interface_lan "$lan_list" lan_mac="" +lan_mac_start="" lan_mac_end="" label_mac="" case $board in +hpe,1920-8g|\ +hpe,1920-16g|\ +hpe,1920-24g) + label_mac=$(mtd_get_mac_binary factory 0x68) + lan_mac=$label_mac + mac_count1=$(hexdump -v -n 4 -s 0x110 -e '4 "%d"' $(find_mtd_part factory) 2>/dev/null) + mac_count2=$(hexdump -v -n 4 -s 0x114 -e '4 "%d"' $(find_mtd_part factory) 2>/dev/null) + lan_mac_start=$(macaddr_add $lan_mac 2) + lan_mac_end=$(macaddr_add $lan_mac $((mac_count2-mac_count1))) + ;; *) lan_mac=$(mtd_get_mac_ascii u-boot-env2 mac_start) lan_mac_end=$(mtd_get_mac_ascii u-boot-env2 mac_end) @@ -36,10 +47,11 @@ esac ucidef_set_interface_macaddr "lan" $lan_mac ucidef_set_bridge_mac "$lan_mac" ucidef_set_network_device_mac eth0 $lan_mac +[ -z "$lan_mac_start" ] && lan_mac_start=$lan_mac for lan in $lan_list; do - ucidef_set_network_device_mac $lan $lan_mac - [ -z "$lan_mac_end" ] || [ "$lan_mac" == "$lan_mac_end" ] && lan_mac=$(macaddr_setbit_la $lan_mac) - lan_mac=$(macaddr_add $lan_mac 1) + ucidef_set_network_device_mac $lan $lan_mac_start + [ -z "$lan_mac_end" ] || [ "$lan_mac_start" == "$lan_mac_end" ] && lan_mac_start=$(macaddr_setbit_la $lan_mac_start) + lan_mac_start=$(macaddr_add $lan_mac_start 1) done [ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac diff --git a/target/linux/realtek/dts-5.10/rtl8380_hpe_1920-8g.dts b/target/linux/realtek/dts-5.10/rtl8380_hpe_1920-8g.dts new file mode 100644 index 0000000000..b51c75f355 --- /dev/null +++ b/target/linux/realtek/dts-5.10/rtl8380_hpe_1920-8g.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rtl838x.dtsi" +#include "rtl838x_hpe_1920.dtsi" + +/ { + compatible = "hpe,1920-8g", "realtek,rtl838x-soc"; + model = "HPE 1920-8G (JG920A)"; + + gpio1: rtl8231-gpio { + compatible = "realtek,rtl8231-gpio"; + #gpio-cells = <2>; + gpio-controller; + indirect-access-bus-id = <0>; + }; + + i2c0: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp0: sfp-0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c0>; + los-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 25 GPIO_ACTIVE_LOW>; + // tx-fault and tx-disable unconnected + }; + + i2c1: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp1: sfp-1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>; + // tx-fault and tx-disable unconnected + }; +}; + +ðernet0 { + mdio: mdio-bus { + compatible = "realtek,rtl838x-mdio"; + regmap = <ðernet0>; + #address-cells = <1>; + #size-cells = <0>; + + INTERNAL_PHY(8) + INTERNAL_PHY(9) + INTERNAL_PHY(10) + INTERNAL_PHY(11) + INTERNAL_PHY(12) + INTERNAL_PHY(13) + INTERNAL_PHY(14) + INTERNAL_PHY(15) + + INTERNAL_PHY(24) + INTERNAL_PHY(26) + }; +}; + +&switch0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + SWITCH_PORT(8, 1, internal) + SWITCH_PORT(9, 2, internal) + SWITCH_PORT(10, 3, internal) + SWITCH_PORT(11, 4, internal) + SWITCH_PORT(12, 5, internal) + SWITCH_PORT(13, 6, internal) + SWITCH_PORT(14, 7, internal) + SWITCH_PORT(15, 8, internal) + + port@24 { + reg = <24>; + label = "lan9"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sfp0>; + }; + + port@26 { + reg = <26>; + label = "lan10"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sfp1>; + }; + + port@28 { + ethernet = <ðernet0>; + reg = <28>; + phy-mode = "internal"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-16g.dts b/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-16g.dts new file mode 100644 index 0000000000..59043b2f6f --- /dev/null +++ b/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-16g.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rtl8382_hpe_1920.dtsi" + +/ { + compatible = "hpe,1920-16g", "realtek,rtl838x-soc"; + model = "HPE 1920-16G (JG923A)"; +}; + +&switch0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + SWITCH_PORT(8, 1, internal) + SWITCH_PORT(9, 2, internal) + SWITCH_PORT(10, 3, internal) + SWITCH_PORT(11, 4, internal) + SWITCH_PORT(12, 5, internal) + SWITCH_PORT(13, 6, internal) + SWITCH_PORT(14, 7, internal) + SWITCH_PORT(15, 8, internal) + + SWITCH_PORT(16, 9, qsgmii) + SWITCH_PORT(17, 10, qsgmii) + SWITCH_PORT(18, 11, qsgmii) + SWITCH_PORT(19, 12, qsgmii) + SWITCH_PORT(20, 13, qsgmii) + SWITCH_PORT(21, 14, qsgmii) + SWITCH_PORT(22, 15, qsgmii) + SWITCH_PORT(23, 16, qsgmii) + + SWITCH_PORT(24, 17, qsgmii) + SWITCH_PORT(25, 18, qsgmii) + SWITCH_PORT(26, 19, qsgmii) + SWITCH_PORT(27, 20, qsgmii) + + port@28 { + ethernet = <ðernet0>; + reg = <28>; + phy-mode = "internal"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-24g.dts b/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-24g.dts new file mode 100644 index 0000000000..61781c708e --- /dev/null +++ b/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-24g.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rtl8382_hpe_1920.dtsi" + +/ { + compatible = "hpe,1920-24g", "realtek,rtl838x-soc"; + model = "HPE 1920-24G (JG924A)"; +}; + +&mdio { + EXTERNAL_PHY(0) + EXTERNAL_PHY(1) + EXTERNAL_PHY(2) + EXTERNAL_PHY(3) + EXTERNAL_PHY(4) + EXTERNAL_PHY(5) + EXTERNAL_PHY(6) + EXTERNAL_PHY(7) +}; + +&switch0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + SWITCH_PORT(0, 1, qsgmii) + SWITCH_PORT(1, 2, qsgmii) + SWITCH_PORT(2, 3, qsgmii) + SWITCH_PORT(3, 4, qsgmii) + SWITCH_PORT(4, 5, qsgmii) + SWITCH_PORT(5, 6, qsgmii) + SWITCH_PORT(6, 7, qsgmii) + SWITCH_PORT(7, 8, qsgmii) + + SWITCH_PORT(8, 9, internal) + SWITCH_PORT(9, 10, internal) + SWITCH_PORT(10, 11, internal) + SWITCH_PORT(11, 12, internal) + SWITCH_PORT(12, 13, internal) + SWITCH_PORT(13, 14, internal) + SWITCH_PORT(14, 15, internal) + SWITCH_PORT(15, 16, internal) + + SWITCH_PORT(16, 17, qsgmii) + SWITCH_PORT(17, 18, qsgmii) + SWITCH_PORT(18, 19, qsgmii) + SWITCH_PORT(19, 20, qsgmii) + SWITCH_PORT(20, 21, qsgmii) + SWITCH_PORT(21, 22, qsgmii) + SWITCH_PORT(22, 23, qsgmii) + SWITCH_PORT(23, 24, qsgmii) + + SWITCH_PORT(24, 25, qsgmii) + SWITCH_PORT(25, 26, qsgmii) + SWITCH_PORT(26, 27, qsgmii) + SWITCH_PORT(27, 28, qsgmii) + + port@28 { + ethernet = <ðernet0>; + reg = <28>; + phy-mode = "internal"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_hpe_1920.dtsi b/target/linux/realtek/dts-5.10/rtl8382_hpe_1920.dtsi new file mode 100644 index 0000000000..5368b41c27 --- /dev/null +++ b/target/linux/realtek/dts-5.10/rtl8382_hpe_1920.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rtl838x.dtsi" +#include "rtl838x_hpe_1920.dtsi" + +/ { + gpio1: rtl8231-gpio { + compatible = "realtek,rtl8231-gpio"; + #gpio-cells = <2>; + gpio-controller; + indirect-access-bus-id = <0>; + }; + + i2c0: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp0: sfp-0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c0>; + los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>; + // tx-fault unconnected + // tx-disable connected to RTL8214FC + }; + + i2c1: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp1: sfp-1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 25 GPIO_ACTIVE_LOW>; + // tx-fault unconnected + // tx-disable connected to RTL8214FC + }; + + i2c2: i2c-gpio-2 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp2: sfp-2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c2>; + los-gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + // tx-fault unconnected + // tx-disable connected to RTL8214FC + }; + + i2c3: i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp3: sfp-3 { + compatible = "sff,sfp"; + i2c-bus = <&i2c3>; + los-gpio = <&gpio1 34 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 33 GPIO_ACTIVE_LOW>; + // tx-fault unconnected + // tx-disable connected to RTL8214FC + }; +}; + +ðernet0 { + mdio: mdio-bus { + compatible = "realtek,rtl838x-mdio"; + regmap = <ðernet0>; + #address-cells = <1>; + #size-cells = <0>; + + INTERNAL_PHY(8) + INTERNAL_PHY(9) + INTERNAL_PHY(10) + INTERNAL_PHY(11) + INTERNAL_PHY(12) + INTERNAL_PHY(13) + INTERNAL_PHY(14) + INTERNAL_PHY(15) + + EXTERNAL_PHY(16) + EXTERNAL_PHY(17) + EXTERNAL_PHY(18) + EXTERNAL_PHY(19) + EXTERNAL_PHY(20) + EXTERNAL_PHY(21) + EXTERNAL_PHY(22) + EXTERNAL_PHY(23) + + EXTERNAL_SFP_PHY_FULL(24, 0) + EXTERNAL_SFP_PHY_FULL(25, 1) + EXTERNAL_SFP_PHY_FULL(26, 2) + EXTERNAL_SFP_PHY_FULL(27, 3) + }; +}; diff --git a/target/linux/realtek/dts-5.10/rtl838x.dtsi b/target/linux/realtek/dts-5.10/rtl838x.dtsi index 11cabc3f63..41fdbdae20 100644 --- a/target/linux/realtek/dts-5.10/rtl838x.dtsi +++ b/target/linux/realtek/dts-5.10/rtl838x.dtsi @@ -27,6 +27,13 @@ reg = <##n>; \ }; +#define EXTERNAL_SFP_PHY_FULL(n, s) \ + phy##n: ethernet-phy@##n { \ + compatible = "ethernet-phy-ieee802.3-c22"; \ + sfp = <&sfp##s>; \ + reg = <##n>; \ + }; + #define SWITCH_PORT(n, s, m) \ port@##n { \ reg = <##n>; \ diff --git a/target/linux/realtek/dts-5.10/rtl838x_hpe_1920.dtsi b/target/linux/realtek/dts-5.10/rtl838x_hpe_1920.dtsi new file mode 100644 index 0000000000..8e29af62bb --- /dev/null +++ b/target/linux/realtek/dts-5.10/rtl838x_hpe_1920.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include +#include + +/ { + chosen { + bootargs = "console=ttyS0,38400"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + watchdog1: watchdog { + // PT7A7514 + compatible = "linux,wdt-gpio"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + hw_algo = "toggle"; + hw_margin_ms = <1000>; + always-running; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_disable_sys_led>; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootware_basic"; + reg = <0x0 0x50000>; + read-only; + }; + + partition@0x60000 { + label = "bootware_data"; + reg = <0x60000 0x30000>; + read-only; + }; + + partition@0x90000 { + label = "bootware_extend"; + reg = <0x90000 0x40000>; + read-only; + }; + + partition@0x100000 { + label = "bootware_basic_backup"; + reg = <0x100000 0x50000>; + read-only; + }; + + partition@0x160000 { + label = "bootware_data_backup"; + reg = <0x160000 0x30000>; + read-only; + }; + + partition@0x190000 { + label = "bootware_extend_backup"; + reg = <0x190000 0x40000>; + read-only; + }; + + partition@0x300000 { + label = "firmware"; + compatible = "h3c,vfs-firmware"; + reg = <0x300000 0x1cf0000>; + }; + + partition@0x1ff0000 { + label = "factory"; + reg = <0x1ff0000 0x10000>; + read-only; + }; + }; + }; +}; diff --git a/target/linux/realtek/image/Makefile b/target/linux/realtek/image/Makefile index cf779002e8..6165d99bfc 100644 --- a/target/linux/realtek/image/Makefile +++ b/target/linux/realtek/image/Makefile @@ -8,6 +8,7 @@ KERNEL_ENTRY = 0x80000400 DEVICE_VARS += ZYXEL_VERS DLINK_KERNEL_PART_SIZE DEVICE_VARS += CAMEO_KERNEL_PART CAMEO_ROOTFS_PART CAMEO_CUSTOMER_SIGNATURE CAMEO_BOARD_VERSION +DEVICE_VARS += H3C_PRODUCT_ID H3C_DEVICE_ID define Build/zyxel-vers ( echo VERS;\ @@ -41,6 +42,43 @@ define Build/dlink-headers cat $@.kernel_part.hex $@.rootfs_part.hex > $@ endef +define Build/7z + $(STAGING_DIR_HOST)/bin/7zr a $(@).new -t7z -m0=lzma $(@) + mv $@.new $@ +endef + +define Build/h3c-image + $(STAGING_DIR_HOST)/bin/mkh3cimg \ + -i $(@) \ + -o $(@).new \ + -c 7z \ + -p $(H3C_PRODUCT_ID) \ + -d $(H3C_DEVICE_ID) + mv $@.new $@ +endef + +define Build/h3c-vfs + $(STAGING_DIR_HOST)/bin/mkh3cvfs \ + -i $(@) \ + -o $(@).new \ + -f openwrt-kernel.bin + mv $@.new $@ +endef + +define Build/relocate-kernel + rm -rf $@.relocate + $(CP) ../../generic/image/relocate $@.relocate + $(MAKE) -j1 -C $@.relocate KERNEL_ADDR=$(KERNEL_LOADADDR) LZMA_TEXT_START=0x82000000 \ + CROSS_COMPILE=$(TARGET_CROSS) + ( \ + dd if=$@.relocate/loader.bin bs=32 conv=sync && \ + perl -e '@s = stat("$@"); print pack("N", @s[7])' && \ + cat "$@" \ + ) > "$@.new" + mv "$@.new" "$@" + rm -rf $@.relocate +endef + define Device/Default PROFILES = Default KERNEL := kernel-bin | append-dtb | gzip | uImage gzip @@ -52,6 +90,17 @@ define Device/Default check-size | append-metadata endef +define Device/hpe_1920 + DEVICE_VENDOR := HPE + IMAGE_SIZE := 29632k + BLOCKSIZE := 64k + H3C_PRODUCT_ID := 0x3c010501 + KERNEL := kernel-bin | append-dtb | relocate-kernel | 7z | h3c-image | h3c-vfs + KERNEL_INITRAMFS := kernel-bin | append-dtb | relocate-kernel | 7z | h3c-image + IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | \ + pad-rootfs | check-size | append-metadata +endef + # "NGE" refers to the uImage magic define Device/netgear_nge KERNEL := kernel-bin | append-dtb | lzma | uImage lzma diff --git a/target/linux/realtek/image/rtl838x.mk b/target/linux/realtek/image/rtl838x.mk index 887f82e385..60eda5359d 100644 --- a/target/linux/realtek/image/rtl838x.mk +++ b/target/linux/realtek/image/rtl838x.mk @@ -65,6 +65,30 @@ define Device/engenius_ews2910p endef TARGET_DEVICES += engenius_ews2910p +define Device/hpe_1920-8g + $(Device/hpe_1920) + SOC := rtl8380 + DEVICE_MODEL := 1920-8G (JG920A) + H3C_DEVICE_ID := 0x00010023 +endef +TARGET_DEVICES += hpe_1920-8g + +define Device/hpe_1920-16g + $(Device/hpe_1920) + SOC := rtl8382 + DEVICE_MODEL := 1920-16G (JG923A) + H3C_DEVICE_ID := 0x00010026 +endef +TARGET_DEVICES += hpe_1920-16g + +define Device/hpe_1920-24g + $(Device/hpe_1920) + SOC := rtl8382 + DEVICE_MODEL := 1920-24G (JG924A) + H3C_DEVICE_ID := 0x00010027 +endef +TARGET_DEVICES += hpe_1920-24g + define Device/inaba_aml2-17gp SOC := rtl8382 IMAGE_SIZE := 13504k diff --git a/target/linux/realtek/rtl838x/config-5.10 b/target/linux/realtek/rtl838x/config-5.10 index c117fc489a..9075aa6d3c 100644 --- a/target/linux/realtek/rtl838x/config-5.10 +++ b/target/linux/realtek/rtl838x/config-5.10 @@ -74,6 +74,8 @@ CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_REALTEK_OTTO=y CONFIG_GPIO_RTL8231=y +CONFIG_GPIO_WATCHDOG=y +# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set CONFIG_GRO_CELLS=y CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_HARDWARE_WATCHPOINTS=y @@ -134,6 +136,7 @@ CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPLIT_BRNIMAGE_FW=y CONFIG_MTD_SPLIT_EVA_FW=y CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_H3C_VFS=y CONFIG_MTD_SPLIT_TPLINK_FW=y CONFIG_MTD_SPLIT_UIMAGE_FW=y CONFIG_NEED_DMA_MAP_STATE=y