From: Trent Piepho <tpiepho@freescale.com>
Date: Wed, 19 Nov 2008 18:40:55 +0000 (-0800)
Subject: powerpc/85xx: L2 cache size wrong in 8572DS dts
X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=f464ff581c247d82fcc0e7ef40c1ca6df9739068;p=openwrt%2Fstaging%2Fblogic.git

powerpc/85xx: L2 cache size wrong in 8572DS dts

It's 1MB, not 512KB.  Newer U-Boots will fix this entry, but that's no
reason to have the wrong value in the dts.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index cadd4652a695..5c69b2fafd32 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -90,7 +90,7 @@
 			compatible = "fsl,mpc8572-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
-			cache-size = <0x80000>;	// L2, 512K
+			cache-size = <0x100000>; // L2, 1M
 			interrupt-parent = <&mpic>;
 			interrupts = <16 2>;
 		};