From: Tom St Denis Date: Thu, 31 Aug 2017 13:14:41 +0000 (-0400) Subject: drm/amd/amdgpu: Tidy up gfx_v9_0_enable_gfx_cg_power_gating() X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=f55ee212ee263de6f9a56530095bfafbecc5863d;p=openwrt%2Fstaging%2Fblogic.git drm/amd/amdgpu: Tidy up gfx_v9_0_enable_gfx_cg_power_gating() Make it consistent in style with the other CG/PG enable functions... Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 61b3362d3c20..b0805b1e7b29 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1883,10 +1883,9 @@ static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, uint32_t data, default_data; default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); - if (enable == true) - data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; - else - data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; + data = REG_SET_FIELD(data, RLC_PG_CNTL, + GFX_POWER_GATING_ENABLE, + enable ? 1 : 0); if(default_data != data) WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); }