From: Marko Ratkaj Date: Fri, 7 Apr 2017 09:07:54 +0000 (+0200) Subject: mvebu: add ClearFog Base device tree files X-Git-Tag: v18.06.0-rc1~2969 X-Git-Url: http://git.cdn.openwrt.org/?a=commitdiff_plain;h=f564fcc6bfb7bae4ca7768f8b30f5348fb472d97;p=openwrt%2Fstaging%2Fxback.git mvebu: add ClearFog Base device tree files Add device tree files for Solidrun ClearFog Base board. We also need to backport some improvements for Armada 388 MicroSoM. The base model is a smaller version of ClearFog Pro without the DSA switch, replacing it with a second copper gigabit port, and only one PCIe socket. Signed-off-by: Marko Ratkaj --- diff --git a/target/linux/mvebu/patches-4.9/471-add-ClearFog-Base-device-tree-files.patch b/target/linux/mvebu/patches-4.9/471-add-ClearFog-Base-device-tree-files.patch new file mode 100644 index 0000000000..c075c4b02a --- /dev/null +++ b/target/linux/mvebu/patches-4.9/471-add-ClearFog-Base-device-tree-files.patch @@ -0,0 +1,540 @@ +From b4ac5820bdc98ee24a2f73b8bd7fdf7f82db3a46 Mon Sep 17 00:00:00 2001 +From: Marko Ratkaj +Date: Fri, 7 Apr 2017 11:02:30 +0200 +Subject: [PATCH 2/2] add ClearFog Base device tree files + +Signed-off-by: Marko Ratkaj +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/armada-388-clearfog-base.dts | 161 ++++++++++++ + arch/arm/boot/dts/armada-388-clearfog.dtsi | 282 +++++++++++++++++++++ + .../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 +++++ + 4 files changed, 506 insertions(+) + create mode 100644 arch/arm/boot/dts/armada-388-clearfog-base.dts + create mode 100644 arch/arm/boot/dts/armada-388-clearfog.dtsi + create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -925,6 +925,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-385-linksys-shelby.dtb \ + armada-388-clearfog.dtb \ + armada-388-clearfog-pro.dtb \ ++ armada-388-clearfog-base.dtb \ + armada-388-db.dtb \ + armada-388-gp.dtb \ + armada-388-rd.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts +@@ -0,0 +1,161 @@ ++/* ++ * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828) ++ * ++ * Copyright (C) 2015 Russell King ++ * ++ * This board is in development; the contents of this file work with ++ * the A1 rev 2.0 of the board, which does not represent final ++ * production board. Things will change, don't expect this file to ++ * remain compatible info the future. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "armada-388-clearfog.dtsi" ++#include "armada-38x-solidrun-microsom-emmc.dtsi" ++ ++/ { ++ model = "SolidRun Clearfog Base A1"; ++ compatible = "solidrun,clearfog-base-a1", ++ "solidrun,clearfog-a1", "marvell,armada388", ++ "marvell,armada385", "marvell,armada380"; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&rear_button_pins>; ++ pinctrl-names = "default"; ++ ++ button_0 { ++ /* The rear SW3 button */ ++ label = "Rear Button"; ++ gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; ++ linux,can-disable; ++ linux,code = ; ++ }; ++ }; ++}; ++ ++ð1 { ++ phy = <&phy1>; ++}; ++ ++&gpio0 { ++ phy1_reset { ++ gpio-hog; ++ gpios = <19 GPIO_ACTIVE_LOW>; ++ output-low; ++ line-name = "phy1-reset"; ++ }; ++}; ++ ++&mdio { ++ pinctrl-0 = <&mdio_pins µsom_phy_clk_pins &clearfog_phy_pins>; ++ phy1: ethernet-phy@1 { ++ /* ++ * Annoyingly, the marvell phy driver configures the LED ++ * register, rather than preserving reset-loaded setting. ++ * We undo that rubbish here. ++ */ ++ marvell,reg-init = <3 16 0 0x101e>; ++ reg = <1>; ++ }; ++}; ++ ++&pinctrl { ++ /* phy1 reset */ ++ clearfog_phy_pins: clearfog-phy-pins { ++ marvell,pins = "mpp19"; ++ marvell,function = "gpio"; ++ }; ++ rear_button_pins: rear-button-pins { ++ marvell,pins = "mpp44"; ++ marvell,function = "gpio"; ++ }; ++}; ++ ++/* ++MPP ++18: pu gpio pca9655 int ++19: gpio phy reset ++20: pu gpio sd0 detect ++21: sd0:cmd ++22: pd gpio mikro int ++23: ++ ++24: ua1:rxd mikro rx ++25: ua1:txd mikro tx ++26: pu i2c1:sck ++27: pu i2c1:sda ++28: sd0:clk ++29: pd gpio mikro rst ++30: ++31: ++ ++32: ++33: ++34: ++35: ++36: ++37: sd0:d3 ++38: sd0:d0 ++39: sd0:d1 ++ ++40: sd0:d2 ++41: ++42: ++43: spi1:cs2 mikro cs ++44: gpio rear button sw3 ++45: ref:clk_out0 phy#0 clock ++46: ref:clk_out1 phy#1 clock ++47: ++ ++48: gpio J18 spare gpio ++49: gpio U10 I2C_IRQ(GNSS) ++50: gpio board id? ++51: ++52: ++53: ++54: gpio mikro pwm ++55: ++ ++56: pu spi1:mosi mikro mosi ++57: pd spi1:sck mikro sck ++58: spi1:miso mikro miso ++59: ++*/ +--- /dev/null ++++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi +@@ -0,0 +1,282 @@ ++/* ++ * Device Tree include file for SolidRun Clearfog 88F6828 based boards ++ * ++ * Copyright (C) 2015 Russell King ++ * ++ * This board is in development; the contents of this file work with ++ * the A1 rev 2.0 of the board, which does not represent final ++ * production board. Things will change, don't expect this file to ++ * remain compatible info the future. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This file is distributed in the hope that it will be useful ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include "armada-388.dtsi" ++#include "armada-38x-solidrun-microsom.dtsi" ++ ++/ { ++ aliases { ++ /* So that mvebu u-boot can update the MAC addresses */ ++ ethernet1 = ð0; ++ ethernet2 = ð1; ++ ethernet3 = ð2; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ soc { ++ internal-regs { ++ sata@a8000 { ++ /* pinctrl? */ ++ status = "okay"; ++ }; ++ ++ sata@e0000 { ++ /* pinctrl? */ ++ status = "okay"; ++ }; ++ ++ sdhci@d8000 { ++ bus-width = <4>; ++ cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; ++ no-1-8-v; ++ pinctrl-0 = <µsom_sdhci_pins ++ &clearfog_sdhci_cd_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ vmmc = <®_3p3v>; ++ wp-inverted; ++ }; ++ ++ usb@58000 { ++ /* CON3, nearest power. */ ++ status = "okay"; ++ }; ++ ++ usb3@f8000 { ++ /* CON7 */ ++ status = "okay"; ++ }; ++ }; ++ ++ pcie-controller { ++ status = "okay"; ++ /* ++ * The two PCIe units are accessible through ++ * the mini-PCIe connectors on the board. ++ */ ++ pcie@2,0 { ++ /* Port 1, Lane 0. CON3, nearest power. */ ++ reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ sfp: sfp { ++ compatible = "sff,sfp"; ++ i2c-bus = <&i2c1>; ++ los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; ++ moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; ++ sfp,ethernet = <ð2>; ++ tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; ++ tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++ð1 { ++ /* ethernet@30000 */ ++ bm,pool-long = <2>; ++ bm,pool-short = <1>; ++ buffer-manager = <&bm>; ++ phy-mode = "sgmii"; ++ status = "okay"; ++}; ++ ++ð2 { ++ /* ethernet@34000 */ ++ bm,pool-long = <3>; ++ bm,pool-short = <1>; ++ buffer-manager = <&bm>; ++ managed = "in-band-status"; ++ phy-mode = "sgmii"; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ pinctrl-0 = <&i2c0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ /* ++ * PCA9655 GPIO expander, up to 1MHz clock. ++ * 0-CON3 CLKREQ# ++ * 1-CON3 PERST# ++ * 2- ++ * 3-CON3 W_DISABLE ++ * 4- ++ * 5-USB3 overcurrent ++ * 6-USB3 power ++ * 7- ++ * 8-JP4 P1 ++ * 9-JP4 P4 ++ * 10-JP4 P5 ++ * 11-m.2 DEVSLP ++ * 12-SFP_LOS ++ * 13-SFP_TX_FAULT ++ * 14-SFP_TX_DISABLE ++ * 15-SFP_MOD_DEF0 ++ */ ++ expander0: gpio-expander@20 { ++ /* ++ * This is how it should be: ++ * compatible = "onnn,pca9655", "nxp,pca9555"; ++ * but you can't do this because of the way I2C works. ++ */ ++ compatible = "nxp,pca9555"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ reg = <0x20>; ++ ++ pcie1_0_clkreq { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_LOW>; ++ input; ++ line-name = "pcie1.0-clkreq"; ++ }; ++ pcie1_0_w_disable { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_LOW>; ++ output-low; ++ line-name = "pcie1.0-w-disable"; ++ }; ++ usb3_ilimit { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_LOW>; ++ input; ++ line-name = "usb3-current-limit"; ++ }; ++ usb3_power { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "usb3-power"; ++ }; ++ m2_devslp { ++ gpio-hog; ++ gpios = <11 GPIO_ACTIVE_HIGH>; ++ output-low; ++ line-name = "m.2 devslp"; ++ }; ++ }; ++ ++ /* The MCP3021 supports standard and fast modes */ ++ mikrobus_adc: mcp3021@4c { ++ compatible = "microchip,mcp3021"; ++ reg = <0x4c>; ++ }; ++}; ++ ++&i2c1 { ++ /* ++ * Routed to SFP, mikrobus, and PCIe. ++ * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with ++ * address pins tied low, which takes addresses 0x50 and 0x51. ++ * Mikrobus doesn't specify beyond an I2C bus being present. ++ * PCIe uses ARP to assign addresses, or 0x63-0x64. ++ */ ++ clock-frequency = <100000>; ++ pinctrl-0 = <&clearfog_i2c1_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ clearfog_i2c1_pins: i2c1-pins { ++ /* SFP, PCIe, mSATA, mikrobus */ ++ marvell,pins = "mpp26", "mpp27"; ++ marvell,function = "i2c1"; ++ }; ++ clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { ++ marvell,pins = "mpp20"; ++ marvell,function = "gpio"; ++ }; ++ mikro_pins: mikro-pins { ++ /* int: mpp22 rst: mpp29 */ ++ marvell,pins = "mpp22", "mpp29"; ++ marvell,function = "gpio"; ++ }; ++ mikro_spi_pins: mikro-spi-pins { ++ marvell,pins = "mpp43"; ++ marvell,function = "spi1"; ++ }; ++ mikro_uart_pins: mikro-uart-pins { ++ marvell,pins = "mpp24", "mpp25"; ++ marvell,function = "ua1"; ++ }; ++}; ++ ++&spi1 { ++ /* ++ * Add SPI CS pins for clearfog: ++ * CS0: W25Q32 (not populated on uSOM) ++ * CS1: PIC microcontroller (Pro models) ++ * CS2: mikrobus ++ */ ++ pinctrl-0 = <&spi1_pins &mikro_spi_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&uart1 { ++ /* mikrobus uart */ ++ pinctrl-0 = <&mikro_uart_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi +@@ -0,0 +1,62 @@ ++/* ++ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC ++ * ++ * Copyright (C) 2015 Russell King ++ * ++ * This board is in development; the contents of this file work with ++ * the A1 rev 2.0 of the board, which does not represent final ++ * production board. Things will change, don't expect this file to ++ * remain compatible info the future. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This file is distributed in the hope that it will be useful ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++/ { ++ soc { ++ internal-regs { ++ sdhci@d8000 { ++ bus-width = <4>; ++ no-1-8-v; ++ non-removable; ++ pinctrl-0 = <µsom_sdhci_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ wp-inverted; ++ }; ++ }; ++ }; ++}; diff --git a/target/linux/mvebu/patches-4.9/472-armada-solidrun-microsom-backport-improvements.patch b/target/linux/mvebu/patches-4.9/472-armada-solidrun-microsom-backport-improvements.patch new file mode 100644 index 0000000000..9195d4e793 --- /dev/null +++ b/target/linux/mvebu/patches-4.9/472-armada-solidrun-microsom-backport-improvements.patch @@ -0,0 +1,185 @@ +From fc5783a00be9251196091be6b9cdd54fe196630b Mon Sep 17 00:00:00 2001 +From: Marko Ratkaj +Date: Fri, 7 Apr 2017 11:24:19 +0200 +Subject: [PATCH] armada-38x-solidrun-microsom backport improvements from + upstream + +Signed-off-by: Marko Ratkaj +--- + .../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 130 ++++++++++++--------- + 1 file changed, 74 insertions(+), 56 deletions(-) + +--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi ++++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi +@@ -17,17 +17,17 @@ + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * +- * This file is distributed in the hope that it will be useful ++ * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * +- * Or, alternatively ++ * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use ++ * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following +@@ -36,11 +36,11 @@ + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * +- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. +@@ -62,45 +62,6 @@ + MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; + + internal-regs { +- ethernet@70000 { +- pinctrl-0 = <&ge0_rgmii_pins>; +- pinctrl-names = "default"; +- phy = <&phy_dedicated>; +- phy-mode = "rgmii-id"; +- buffer-manager = <&bm>; +- bm,pool-long = <0>; +- bm,pool-short = <1>; +- status = "okay"; +- }; +- +- mdio@72004 { +- /* +- * Add the phy clock here, so the phy can be +- * accessed to read its IDs prior to binding +- * with the driver. +- */ +- pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>; +- pinctrl-names = "default"; +- +- phy_dedicated: ethernet-phy@0 { +- /* +- * Annoyingly, the marvell phy driver +- * configures the LED register, rather +- * than preserving reset-loaded setting. +- * We undo that rubbish here. +- */ +- marvell,reg-init = <3 16 0 0x101e>; +- reg = <0>; +- }; +- }; +- +- pinctrl@18000 { +- microsom_phy_clk_pins: microsom-phy-clk-pins { +- marvell,pins = "mpp45"; +- marvell,function = "ref"; +- }; +- }; +- + rtc@a3800 { + /* + * If the rtc doesn't work, run "date reset" +@@ -108,21 +69,78 @@ + */ + status = "okay"; + }; ++ }; ++ }; ++}; + +- serial@12000 { +- pinctrl-0 = <&uart0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- }; ++&bm { ++ status = "okay"; ++}; + +- bm@c8000 { +- status = "okay"; +- }; +- }; ++&bm_bppi { ++ status = "okay"; ++}; + +- bm-bppi { +- status = "okay"; +- }; ++ð0 { ++ /* ethernet@70000 */ ++ pinctrl-0 = <&ge0_rgmii_pins>; ++ pinctrl-names = "default"; ++ phy = <&phy_dedicated>; ++ phy-mode = "rgmii-id"; ++ buffer-manager = <&bm>; ++ bm,pool-long = <0>; ++ bm,pool-short = <1>; ++ status = "okay"; ++}; + ++&mdio { ++ /* ++ * Add the phy clock here, so the phy can be accessed to read its ++ * IDs prior to binding with the driver. ++ */ ++ pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>; ++ pinctrl-names = "default"; ++ ++ phy_dedicated: ethernet-phy@0 { ++ /* ++ * Annoyingly, the marvell phy driver configures the LED ++ * register, rather than preserving reset-loaded setting. ++ * We undo that rubbish here. ++ */ ++ marvell,reg-init = <3 16 0 0x101e>; ++ reg = <0>; + }; + }; ++ ++&pinctrl { ++ microsom_phy_clk_pins: microsom-phy-clk-pins { ++ marvell,pins = "mpp45"; ++ marvell,function = "ref"; ++ }; ++ /* Optional eMMC */ ++ microsom_sdhci_pins: microsom-sdhci-pins { ++ marvell,pins = "mpp21", "mpp28", "mpp37", ++ "mpp38", "mpp39", "mpp40"; ++ marvell,function = "sd0"; ++ }; ++}; ++ ++&spi1 { ++ /* The microsom has an optional W25Q32 on board, connected to CS0 */ ++ pinctrl-0 = <&spi1_pins>; ++ ++ w25q32: spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "w25q32", "jedec,spi-nor"; ++ reg = <0>; /* Chip select 0 */ ++ spi-max-frequency = <3000000>; ++ status = "disabled"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-0 = <&uart0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++};