openwrt/staging/blogic.git
7 years agodrm/amdgpu: fix before and after mapping judgement for replace mapping
Junwei Zhang [Thu, 16 Mar 2017 08:09:24 +0000 (16:09 +0800)]
drm/amdgpu: fix before and after mapping judgement for replace mapping

If the before mapping is 1 page size, so its start and last will be same.
Thus below condition will become false, then to free the before mapping.
   > if (before->it.start != before->it.last)
But in this case, we need the before mapping of 1 page size.
So does after mapping.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add a VM mapping replace operation v2
Christian König [Mon, 13 Mar 2017 09:13:39 +0000 (10:13 +0100)]
drm/amdgpu: add a VM mapping replace operation v2

Add a new operation to replace mappings in a VM with a new one.

v2: Fix Jerry's comment, separate out clear operation.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: implement AMDGPU_VA_OP_CLEAR v2
Christian König [Mon, 13 Mar 2017 09:13:38 +0000 (10:13 +0100)]
drm/amdgpu: implement AMDGPU_VA_OP_CLEAR v2

A new VM operation to remove all mappings in a range.

v2: limit unmapped area as noted by Jerry

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: separate page table allocation from mapping
Christian König [Mon, 13 Mar 2017 09:13:37 +0000 (10:13 +0100)]
drm/amdgpu: separate page table allocation from mapping

This makes it easier to implement a replace operation.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: make set_prt callback optional and fix error handling
Christian König [Mon, 13 Mar 2017 09:13:36 +0000 (10:13 +0100)]
drm/amdgpu: make set_prt callback optional and fix error handling

PRT support is completely implemented now and we left it
turned on accidentially in the error path.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/vi: add missing error handling when setting uvd dclk
Alex Deucher [Thu, 16 Mar 2017 02:05:20 +0000 (22:05 -0400)]
drm/amdgpu/vi: add missing error handling when setting uvd dclk

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reported-by: David Binderman <dcb314@hotmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/vi: remove duplicate CG flags
Alex Deucher [Thu, 16 Mar 2017 02:03:08 +0000 (22:03 -0400)]
drm/amdgpu/vi: remove duplicate CG flags

GFX_MGLS was added twice.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reported-by: David Binderman <dcb314@hotmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/powerplay: remove unneeded conversions to bool
Andrew F. Davis [Wed, 15 Mar 2017 16:20:24 +0000 (11:20 -0500)]
drm/amd/powerplay: remove unneeded conversions to bool

Found with scripts/coccinelle/misc/boolconv.cocci.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: remove unneeded conversions to bool
Andrew F. Davis [Wed, 15 Mar 2017 16:20:23 +0000 (11:20 -0500)]
drm/amdgpu: remove unneeded conversions to bool

Found with scripts/coccinelle/misc/boolconv.cocci.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add macro to retrieve timeline name v2
Andres Rodriguez [Sat, 11 Mar 2017 15:50:34 +0000 (10:50 -0500)]
drm/amdgpu: add macro to retrieve timeline name v2

This helps de-duplicate a long expression and removes overly long lines.

v2: Rename macro and undef it

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: replace fence pointer with fence data in traces
Andres Rodriguez [Fri, 10 Mar 2017 02:25:54 +0000 (21:25 -0500)]
drm/amdgpu: replace fence pointer with fence data in traces

Fence data is easier to read and allows us to correlate to identify
corresponding dma_fence ftrace events.

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: remove useless pointers from traces
Andres Rodriguez [Fri, 10 Mar 2017 02:25:53 +0000 (21:25 -0500)]
drm/amdgpu: remove useless pointers from traces

Remove pointers which provide redundant information which is already
easier to deduce from other fields.

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: use sched_job id instead of pointer for tracing
Andres Rodriguez [Fri, 10 Mar 2017 02:25:52 +0000 (21:25 -0500)]
drm/amdgpu: use sched_job id instead of pointer for tracing

Pointers get reallocated and they are hard to read for humans. Use ids
instead.

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: more ftrace formatting consistency fixes
Andres Rodriguez [Fri, 10 Mar 2017 02:25:51 +0000 (21:25 -0500)]
drm/amdgpu: more ftrace formatting consistency fixes

Consistent formatting makes it easier to read the logs and apply simple
awk oneliners.

I missed some of these on my last patch.

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/sched: add a unique job id to amd_sched_job
Andres Rodriguez [Fri, 10 Mar 2017 02:25:50 +0000 (21:25 -0500)]
drm/amd/sched: add a unique job id to amd_sched_job

A unique id is useful for debugging and tracing. Intended to replace
pointers in ftrace output.

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: increase IH ring buffer size to avoid overflow
Roger.He [Tue, 14 Mar 2017 08:47:30 +0000 (16:47 +0800)]
drm/amdgpu: increase IH ring buffer size to avoid overflow

We originally limited the IH to 4k on tonga since it
uses bus addresses directly rather than GPU MC addresses,
so it needs contigous physical memory.  This brings it
inline with other asics.

Signed-off-by: Roger.He <Hongbo.He@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: don't init GDS pool if GDS size is 0 (v2)
Alex Deucher [Wed, 15 Mar 2017 13:45:48 +0000 (09:45 -0400)]
drm/amdgpu: don't init GDS pool if GDS size is 0 (v2)

SI cards don't expose GDS as a separate pool.  The CP manages
GDS and the UMDs use special CP packets to allocate GDS memory.

v2: drop extra whitespace change

bug: https://bugzilla.kernel.org/show_bug.cgi?id=194867

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx6: drop gds unrefs
Alex Deucher [Wed, 15 Mar 2017 13:42:03 +0000 (09:42 -0400)]
drm/amdgpu/gfx6: drop gds unrefs

Leftover from gfx7 code.  gfx6 never sets up the gds buffers
in the first place.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: refine vce_3.0 code.
Rex Zhu [Mon, 13 Mar 2017 08:05:32 +0000 (16:05 +0800)]
drm/amdgpu: refine vce_3.0 code.

fix logic error in hw_fini and
set_clockgating_state functions.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: refine vce2.0 dpm sequence
Rex Zhu [Mon, 6 Mar 2017 03:29:26 +0000 (11:29 +0800)]
drm/amdgpu: refine vce2.0 dpm sequence

start vce first then enable vce dpm.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/radeon: add new ATIF ACPI method
Alex Deucher [Fri, 10 Mar 2017 20:41:54 +0000 (15:41 -0500)]
drm/radeon: add new ATIF ACPI method

Used for fetching external GPU information.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add new ATIF ACPI method
Alex Deucher [Fri, 10 Mar 2017 20:34:34 +0000 (15:34 -0500)]
drm/amdgpu: add new ATIF ACPI method

Used for fetching external GPU information.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: get cs support of AMDGPU_HW_IP_UVD_ENC
Leo Liu [Tue, 10 Jan 2017 16:57:24 +0000 (11:57 -0500)]
drm/amdgpu: get cs support of AMDGPU_HW_IP_UVD_ENC

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add AMDGPU_HW_IP_UVD_ENC to info query
Leo Liu [Tue, 10 Jan 2017 16:50:08 +0000 (11:50 -0500)]
drm/amdgpu: add AMDGPU_HW_IP_UVD_ENC to info query

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agouapi/drm: add AMDGPU_HW_IP_UVD_ENC
Leo Liu [Tue, 10 Jan 2017 16:49:08 +0000 (11:49 -0500)]
uapi/drm: add AMDGPU_HW_IP_UVD_ENC

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add uvd enc ring type and functions
Leo Liu [Thu, 12 Jan 2017 18:19:46 +0000 (13:19 -0500)]
drm/amdgpu: add uvd enc ring type and functions

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add uvd enc run queue
Leo Liu [Thu, 12 Jan 2017 18:15:37 +0000 (13:15 -0500)]
drm/amdgpu: add uvd enc run queue

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add uvd enc rings
Leo Liu [Tue, 10 Jan 2017 16:23:23 +0000 (11:23 -0500)]
drm/amdgpu: add uvd enc rings

And initialize them

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: move amdgpu_vce structure to vce header
Leo Liu [Tue, 10 Jan 2017 16:02:58 +0000 (11:02 -0500)]
drm/amdgpu: move amdgpu_vce structure to vce header

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: move amdgpu_uvd structure to uvd header
Leo Liu [Mon, 2 Jan 2017 15:07:33 +0000 (10:07 -0500)]
drm/amdgpu: move amdgpu_uvd structure to uvd header

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add a ring func for end command
Leo Liu [Wed, 14 Dec 2016 20:05:00 +0000 (15:05 -0500)]
drm/amdgpu: add a ring func for end command

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add DF MGCG flag
Huang Rui [Tue, 17 Jan 2017 02:18:31 +0000 (10:18 +0800)]
drm/amdgpu: add DF MGCG flag

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add DRM MGCG header
Huang Rui [Wed, 18 Jan 2017 08:53:16 +0000 (16:53 +0800)]
drm/amdgpu: add DRM MGCG header

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add asic callback to get memsize register
Alex Deucher [Fri, 3 Mar 2017 22:26:10 +0000 (17:26 -0500)]
drm/amdgpu: add asic callback to get memsize register

Newer asics use different registers so abstract it.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: check function points valid before use. (v3)
Rex Zhu [Wed, 22 Feb 2017 07:33:46 +0000 (15:33 +0800)]
drm/amdgpu: check function points valid before use. (v3)

v2: agd: integrate Christian's comments.
v3: print error message if call fails

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add a callback to set vm mapping flags
Alex Xie [Tue, 14 Feb 2017 17:22:57 +0000 (12:22 -0500)]
drm/amdgpu: add a callback to set vm mapping flags

This lets each asic set whichever flags it supports.

Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: set GART PTE asic specific flags
Alex Xie [Tue, 14 Feb 2017 17:31:36 +0000 (12:31 -0500)]
drm/amdgpu: set GART PTE asic specific flags

Set asic specific gart pte flags in the gmc IP module for
each asic.

Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add a ucode size member into firmware info
Huang Rui [Mon, 10 Oct 2016 07:19:06 +0000 (15:19 +0800)]
drm/amdgpu: add a ucode size member into firmware info

This will be used for newer asics.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: expand pte flags to uint64_t
Chunming Zhou [Wed, 21 Sep 2016 08:19:19 +0000 (16:19 +0800)]
drm/amdgpu: expand pte flags to uint64_t

Necessary for new asics.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/ih: store the full context id
Alex Deucher [Tue, 29 Nov 2016 23:02:12 +0000 (18:02 -0500)]
drm/amdgpu/ih: store the full context id

The contextID field (formerly known as src_data) of the IH
vector stores client specific information about an interrupt.
It was expanded from 32 bits to 128 on newer asics.  Expand the
src_id field to handle this.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: switch ih handling to two levels (v3)
Alex Deucher [Tue, 29 Mar 2016 22:28:50 +0000 (18:28 -0400)]
drm/amdgpu: switch ih handling to two levels (v3)

Newer asics have a two levels of irq ids now:
client id - the IP
src id - the interrupt src within the IP

v2: integrated Christian's comments.
v3: fix rebase fail in SI and CIK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add 64bit doorbell functions (v2)
Ken Wang [Fri, 18 Mar 2016 07:23:08 +0000 (15:23 +0800)]
drm/amdgpu: add 64bit doorbell functions (v2)

Newer asics need 64 bit doorbells.

v2: fix comment (Nils)

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add 64bit wb functions
Ken Wang [Fri, 18 Mar 2016 07:08:49 +0000 (15:08 +0800)]
drm/amdgpu: add 64bit wb functions

Newer asics need 64 bit writeback slots.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: change wptr to 64 bits (v2)
Ken Wang [Sat, 12 Mar 2016 01:32:30 +0000 (09:32 +0800)]
drm/amdgpu: change wptr to 64 bits (v2)

Newer asics need 64 bit wptrs.  If the wptr is now
smaller than the rptr that doesn't indicate a wrap-around
anymore.

v2: integrate Christian's comments.

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: init aperture definitions (v2)
Junwei Zhang [Thu, 10 Mar 2016 06:20:39 +0000 (14:20 +0800)]
drm/amdgpu: init aperture definitions (v2)

v2: agd: move apertures to mc structure

Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: Merge pre/postclose hooks
Daniel Vetter [Wed, 8 Mar 2017 14:12:52 +0000 (15:12 +0100)]
drm/amdgpu: Merge pre/postclose hooks

Again no apparent explanation for the split except hysterical raisins.
Merging them also makes it a bit more obviuos what's going on wrt the
runtime pm refdancing.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/radeon: Merge pre/postclose hooks
Daniel Vetter [Wed, 8 Mar 2017 14:12:48 +0000 (15:12 +0100)]
drm/radeon: Merge pre/postclose hooks

Again no apparent explanation for the split except hysterical raisins.
Merging them also makes it a bit more obviuos what's going on wrt the
runtime pm refdancing.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: trace fence details in amdgpu_sched_run_job
Andres Rodriguez [Fri, 24 Feb 2017 18:20:58 +0000 (13:20 -0500)]
drm/amdgpu: trace fence details in amdgpu_sched_run_job

This information is intended to provide the required data to associate
amdgpu tracepoints with their corresponding dma_fence_* events.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: make trace format uniform csv name=value
Andres Rodriguez [Fri, 24 Feb 2017 18:20:57 +0000 (13:20 -0500)]
drm/amdgpu: make trace format uniform csv name=value

Most of the traces have uniform format except for two of them. Having
all the traces match makes it simple to run awk on the ftrace output.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx8: move CE&DE meta data structure to vi_structs.h
Xiangliang Yu [Mon, 6 Mar 2017 07:27:51 +0000 (15:27 +0800)]
drm/amdgpu/gfx8: move CE&DE meta data structure to vi_structs.h

Because different HWs have different definition for CE & DE meta
data, follow mqd design to move the structures to vi_structs.h.

And change the prefix from amdgpu to vi as the structures is only
for VI family.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/amdgpu: add DID for Polaris10
Junshan Fang [Thu, 19 Jan 2017 02:36:18 +0000 (10:36 +0800)]
drm/amd/amdgpu: add DID for Polaris10

Signed-off-by: Junshan Fang <Junshan.Fang@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add polaris12 to virtual dce handling
Alex Deucher [Fri, 3 Mar 2017 17:57:37 +0000 (12:57 -0500)]
drm/amdgpu: add polaris12 to virtual dce handling

Was missed when polaris12 support was added.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: remove unused sync testing
Christian König [Tue, 15 Nov 2016 13:15:28 +0000 (08:15 -0500)]
drm/amdgpu: remove unused sync testing

Not used in a while.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/powerplay: simplify avfs control code in smu7
Eric Huang [Wed, 1 Mar 2017 21:49:06 +0000 (16:49 -0500)]
drm/amd/powerplay: simplify avfs control code in smu7

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/powerplay: add function avfs control in smu7
Eric Huang [Wed, 1 Mar 2017 20:56:17 +0000 (15:56 -0500)]
drm/amd/powerplay: add function avfs control in smu7

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/powerplay: add voltage change support through pp_table
Eric Huang [Wed, 1 Mar 2017 20:49:31 +0000 (15:49 -0500)]
drm/amd/powerplay: add voltage change support through pp_table

Disable avfs to make voltage change take effect.

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/radeon: remove useless and potentially wrong message
Andy Shevchenko [Thu, 1 Dec 2016 01:21:10 +0000 (03:21 +0200)]
drm/radeon: remove useless and potentially wrong message

There is no need to repeat information that printed by PCI core at boot time.

Besides that printing was potentially wrong since resource_size_t might be
bigger than 32 bits and there is a dedicated specifier for such type, i.e.
%pap. Someone can fix it and use even better approach, i.e. %pR.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: print full bios version in dmesg.
Rex Zhu [Mon, 6 Mar 2017 03:33:25 +0000 (11:33 +0800)]
drm/amdgpu: print full bios version in dmesg.

v2: fix merge error.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: disable HDP flushes on APUs
Christian König [Fri, 17 Feb 2017 14:04:31 +0000 (15:04 +0100)]
drm/amdgpu: disable HDP flushes on APUs

We completely bypass the HDP now.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agogpu: drm: amd/radeon: Convert printk(KERN_<LEVEL> to pr_<level>
Joe Perches [Tue, 28 Feb 2017 12:55:52 +0000 (04:55 -0800)]
gpu: drm: amd/radeon: Convert printk(KERN_<LEVEL> to pr_<level>

Use a more common logging style.

Miscellanea:

o Coalesce formats and realign arguments
o Neaten a few macros now using pr_<level>

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm: Use pr_cont where appropriate
Joe Perches [Tue, 28 Feb 2017 01:31:03 +0000 (17:31 -0800)]
drm: Use pr_cont where appropriate

Using 'printk("\n")' is not preferred anymore and
using printk to continue logging messages now produces
multiple line logging output unless the continuations
use KERN_CONT.

Convert these uses to appropriately use pr_cont or a
single printk where possible.

Miscellanea:

o Use a temporary const char * instead of multiple printks
o Remove trailing space from logging by using a leading space instead

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: put gtt at 0 in the internal address space
Alex Deucher [Thu, 17 Nov 2016 20:40:22 +0000 (15:40 -0500)]
drm/amdgpu: put gtt at 0 in the internal address space

There still seem to be some blocks that make accesses
in the lower part of the address space.  This works around
this.

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/vce2: fix vce bar programming
Alex Deucher [Fri, 17 Feb 2017 18:50:15 +0000 (13:50 -0500)]
drm/amdgpu/vce2: fix vce bar programming

Program the VCE BAR and offsets properly.  The current code
was carried over from a limitation from older VCE versions.

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrivers/gpu: Convert remaining uses of pr_warning to pr_warn
Joe Perches [Fri, 17 Feb 2017 07:11:30 +0000 (23:11 -0800)]
drivers/gpu: Convert remaining uses of pr_warning to pr_warn

To enable eventual removal of pr_warning

This makes pr_warn use consistent for drivers/gpu

Prior to this patch, there were 15 uses of pr_warning and
20 uses of pr_warn in drivers/gpu

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd: Spelling s/SDMA_WRTIE_SUB_OPCODE_TILED/SDMA_WRITE_SUB_OPCODE_TILED/
Geert Uytterhoeven [Fri, 17 Feb 2017 15:36:38 +0000 (16:36 +0100)]
drm/amd: Spelling s/SDMA_WRTIE_SUB_OPCODE_TILED/SDMA_WRITE_SUB_OPCODE_TILED/

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: dri-devel@lists.freedesktop.orgamd-gfx@lists.freedesktop.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/radeon/dp_auxch: Ratelimit aux transfer debug messages
Lyude [Wed, 22 Feb 2017 21:34:53 +0000 (16:34 -0500)]
drm/radeon/dp_auxch: Ratelimit aux transfer debug messages

Aux transfers always fail with non-zero status flags when there's
nothing connected on the port, so we don't usually need to see all of
the debugging information from it. Also, we try reprobing a -lot-, so
without ratelimiting most of the kernel log is filled up with messages
from radeon_dp_aux_transfer_native.

Signed-off-by: Lyude <lyude@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/powerplay: enable LEDs on Fiji boards
Alex Deucher [Wed, 22 Feb 2017 16:20:17 +0000 (11:20 -0500)]
drm/amdgpu/powerplay: enable LEDs on Fiji boards

This enables the LEDs that light up based on DPM states
on some Fiji boards.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=97590

Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: rename amdgpu_gca_config to amdgpu_gfx_config
Junwei Zhang [Tue, 21 Feb 2017 02:32:37 +0000 (10:32 +0800)]
drm/amdgpu: rename amdgpu_gca_config to amdgpu_gfx_config

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: Fix module unload hang by KIQ IRQ set
Trigger Huang [Mon, 20 Feb 2017 02:57:39 +0000 (21:57 -0500)]
drm/amdgpu: Fix module unload hang by KIQ IRQ set

In some cases, manually insmod/rmmod amdgpu is necessary. When
unloading amdgpu, the KIQ IRQ enable/disable function will case
system hang. The root cause is, in the sequence of function
amdgpu_fini, the sw_fini of IP block AMD_IP_BLOCK_TYPE_GFX will be
invoked earlier than that of AMD_IP_BLOCK_TYPE_IH. So continue to use
the variable freed by AMD_IP_BLOCK_TYPE_GFX will cause system hang.

Signed-off-by: Trigger Huang <trigger.huang@amd.com>
Reviewed-by: Xiangliang Yu < Xiangliang.Yu@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: bump driver version for new lds buffer query
Alex Deucher [Wed, 8 Mar 2017 23:27:07 +0000 (18:27 -0500)]
drm/amdgpu: bump driver version for new lds buffer query

v2: agd: bump version

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: export gfx config double offchip LDS buffers (v3)
Junwei Zhang [Fri, 17 Feb 2017 03:05:49 +0000 (11:05 +0800)]
drm/amdgpu: export gfx config double offchip LDS buffers (v3)

v2: move the config struct to drm_amdgpu_info_device
v3: move the config feature to amdgpu_gca_config

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx: free memory of mqd backup
Xiangliang Yu [Thu, 16 Feb 2017 07:20:04 +0000 (15:20 +0800)]
drm/amdgpu/gfx: free memory of mqd backup

Need to free mqd backup when destroying ring.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/virt: fix typo
Xiangliang Yu [Thu, 16 Feb 2017 07:07:06 +0000 (15:07 +0800)]
drm/amdgpu/virt: fix typo

When send messages to hypervior, the messages format should be is
idh_request, not idh_event.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: change pointer of mqd_ptr & mqd_backup to void
Xiangliang Yu [Fri, 17 Feb 2017 08:03:10 +0000 (16:03 +0800)]
drm/amdgpu: change pointer of mqd_ptr & mqd_backup to void

vi_mqd is only used by VI family but mqd_ptr and mqd_backup is
common for all ASIC, so change the pointer to void.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:fix kiq_resume routine (V2)
Monk Liu [Thu, 26 Jan 2017 07:36:37 +0000 (15:36 +0800)]
drm/amdgpu:fix kiq_resume routine (V2)

v2:
use in_rest to fix compute ring test failure issue
which occured after FLR/gpu_reset.

we need backup a clean status of MQD which was created in drv load
stage, and use it in resume stage, otherwise KCQ and KIQ all may
faild in ring/ib test.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:use clear_ring to clr RB
Monk Liu [Wed, 8 Feb 2017 08:51:06 +0000 (16:51 +0800)]
drm/amdgpu:use clear_ring to clr RB

In resume routine, we need clr RB prior to the
ring test of engine, otherwise some engine hang
duplicated during GPU reset.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:imple ring clear
Monk Liu [Wed, 8 Feb 2017 08:49:46 +0000 (16:49 +0800)]
drm/amdgpu:imple ring clear

we can use it clear ring buffer instead of fullfill
0, which is not correct for engine

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:alloc mqd backup
Monk Liu [Thu, 26 Jan 2017 07:33:52 +0000 (15:33 +0800)]
drm/amdgpu:alloc mqd backup

this is required for restoring the mqds after GPU reset.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:new field in_reset introduced for gfx
Monk Liu [Thu, 26 Jan 2017 07:32:16 +0000 (15:32 +0800)]
drm/amdgpu:new field in_reset introduced for gfx

use it to seperate driver load and gpu reset/resume
because gfx IP need different approach for different
hw_init trigger source

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:RUNTIME flag should clr later
Monk Liu [Thu, 26 Jan 2017 07:31:15 +0000 (15:31 +0800)]
drm/amdgpu:RUNTIME flag should clr later

this flag will get cleared by request gpu access

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:use work instead of delay-work
Monk Liu [Mon, 6 Feb 2017 05:56:47 +0000 (13:56 +0800)]
drm/amdgpu:use work instead of delay-work

no need to use a delay work since we don't know how
much time hypervisor takes on FLR, so just polling
and waiting in a work.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:no kiq for mailbox registers access
Monk Liu [Wed, 25 Jan 2017 08:49:32 +0000 (16:49 +0800)]
drm/amdgpu:no kiq for mailbox registers access

Use no kiq version reg access due to:
1) better performance
2) INTR context consideration (some routine in mailbox is in
   INTR context e.g.xgpu_vi_mailbox_rcv_irq)

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:Refine handshake of mailbox
Ken Xue [Wed, 25 Jan 2017 05:14:17 +0000 (13:14 +0800)]
drm/amdgpu:Refine handshake of mailbox

Signed-off-by: Ken Xue <Ken.Xue@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:impl RREG32 no kiq version
Monk Liu [Wed, 25 Jan 2017 07:07:40 +0000 (15:07 +0800)]
drm/amdgpu:impl RREG32 no kiq version

some registers are PF & VF copy, and we can safely use
mmio method to access them.

and sometime we are forbid to use kiq to access registers
for example in INTR context.

we need a MACRO that always disable KIQ for regs accessing

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:use MACRO like other places
Monk Liu [Wed, 8 Feb 2017 07:10:24 +0000 (15:10 +0800)]
drm/amdgpu:use MACRO like other places

Change-Id: Ica8f86577a50d817119de4b4fb95068dc72652a9
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: simplify reservation handling during buffer creation
Nicolai Hähnle [Thu, 16 Feb 2017 10:01:44 +0000 (11:01 +0100)]
drm/amdgpu: simplify reservation handling during buffer creation

By using ttm_bo_init_reserved instead of the manual initialization of
the reservation object, the reservation lock will be properly unlocked
and destroyed when the TTM BO initialization fails.

Actual deadlocks caused by the missing unlock should have been fixed
by "drm/ttm: never add BO that failed to validate to the LRU list",
superseding the flawed fix in commit 38fc4856ad98 ("drm/amdgpu: fix
a potential deadlock in amdgpu_bo_create_restricted()").

This change fixes remaining recursive locking errors that can be seen
with lock debugging enabled, and avoids the error of freeing a locked
mutex.

As an additional minor bonus, buffers created with resv == NULL and
the AMDGPU_GEM_CREATE_VRAM_CLEARED flag are now only added to the
global LRU list after the fill commands have been issued.

v2: use amdgpu_bo_unreserve instead of ttm_bo_unreserve

Fixes: 12a852219583 ("drm/amdgpu: improve AMDGPU_GEM_CREATE_VRAM_CLEARED handling (v2)")
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/ttm: add ttm_bo_init_reserved
Nicolai Hähnle [Thu, 16 Feb 2017 09:56:40 +0000 (10:56 +0100)]
drm/ttm: add ttm_bo_init_reserved

This variant of ttm_bo_init returns the validated buffer object with
the reservation lock held when resv == NULL. This is convenient for
callers that want to use the BO immediately, e.g. for initializing its
contents.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/ttm: fix the documentation of ttm_bo_init
Nicolai Hähnle [Tue, 14 Feb 2017 09:37:41 +0000 (10:37 +0100)]
drm/ttm: fix the documentation of ttm_bo_init

As the comment says: callers of ttm_bo_init cannot rely on having the
only reference to the BO when the function returns successfully.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agoRevert "drm/amdgpu: fix a potential deadlock in amdgpu_bo_create_restricted()"
Nicolai Hähnle [Tue, 14 Feb 2017 08:47:36 +0000 (09:47 +0100)]
Revert "drm/amdgpu: fix a potential deadlock in amdgpu_bo_create_restricted()"

This reverts commit 38fc4856ad98f230bc91da0421dec69e4aee40f8, which
introduces a use-after-free.

The underlying bug should be properly fixed with "drm/ttm: never add BO
that failed to validate to the LRU list".

Cc: zhoucm1 <david1.zhou@amd.com>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/ttm: never add BO that failed to validate to the LRU list
Nicolai Hähnle [Tue, 14 Feb 2017 08:37:12 +0000 (09:37 +0100)]
drm/ttm: never add BO that failed to validate to the LRU list

Fixes a potential race condition in amdgpu that looks as follows:

Task 1: attempt ttm_bo_init, but ttm_bo_validate fails
Task 1: add BO to global list anyway
Task 2: grabs hold of the BO, waits on its reservation lock
Task 1: releases its reference of the BO; never gives up the
        reservation lock

The patch "drm/amdgpu: fix a potential deadlock in
amdgpu_bo_create_restricted()" attempts to fix that by releasing
the reservation lock in amdgpu code; unfortunately, it introduces
a use-after-free when this race _doesn't_ happen.

This patch should fix the race properly by never adding the BO
to the global list in the first place.

Cc: zhoucm1 <david1.zhou@amd.com>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: expose GPU sensor related information
Alex Deucher [Wed, 8 Mar 2017 23:25:15 +0000 (18:25 -0500)]
drm/amdgpu: expose GPU sensor related information

This includes shader/memory clocks, temperature, GPU load, etc.

v2: - add sub-queries for AMDPGU_INFO_GPU_SENSOR_*
    - do not break the ABI
v3: - return -ENOENT when amdgpu_dpm == 0
    - expose more sensor queries
v4: - s/GPU_POWER/GPU_AVG_POWER/
    - improve VDDNB/VDDGFX query description
    - fix amdgpu_dpm check
v5: - agd: fix warning
v6: - agd: bump version

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: expose amdgpu_sensors on pre-powerplay chips
Samuel Pitoiset [Wed, 15 Feb 2017 18:32:29 +0000 (19:32 +0100)]
drm/amdgpu: expose amdgpu_sensors on pre-powerplay chips

read_sensor() has been recently implemented for dpm based boards
which means amdgpu_sensors can now be exposed.

v2: - make sure read_sensor is not NULL on dpm chips
    - keep sanity check for powerplay chips
v3: - make sure amdgpu_dpm != 0

Cc: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: implement read_sensor() for pre-powerplay chips
Samuel Pitoiset [Tue, 14 Feb 2017 00:00:49 +0000 (01:00 +0100)]
drm/amdgpu: implement read_sensor() for pre-powerplay chips

Add the GPU temperature, the shader clock and eventually the
memory clock (as well as the GPU load on CI). The main goal is
to expose this info to the userspace like Radeon.

v2: - add AMDGPU_PP_SENSOR_GPU_LOAD on CI
    - update the commit description

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/radeon: allow unaligned shader loads on CIK
Marek Olšák [Mon, 13 Feb 2017 16:37:05 +0000 (17:37 +0100)]
drm/radeon: allow unaligned shader loads on CIK

Set alignment mode to unaligned on CIK to align with amdgpu.  This is
needed for unaligned loads to work properly in mesa.  The current setting
requires dword alignment.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: fix PRT teardown on VM fini v3
Christian König [Tue, 14 Feb 2017 15:02:52 +0000 (16:02 +0100)]
drm/amdgpu: fix PRT teardown on VM fini v3

v2: new approach fixing this by registering a fence callback for
    all users of the VM on teardown
v3: agd: rebase

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add OOM fallback on PRT teardown (v2)
Christian König [Tue, 14 Feb 2017 14:47:03 +0000 (15:47 +0100)]
drm/amdgpu: add OOM fallback on PRT teardown (v2)

Don't assume kmalloc will always succeed.

v2: agd: rebase

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: minor PRT turnoff fix (v2)
Christian König [Tue, 14 Feb 2017 13:50:50 +0000 (14:50 +0100)]
drm/amdgpu: minor PRT turnoff fix (v2)

When two VMs stop using PRT support at the same time we might
not disable it in the right order otherwise.

v2: agd: rebase

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: change pte definitions to 64 bit
Alex Xie [Wed, 15 Feb 2017 19:10:19 +0000 (14:10 -0500)]
drm/amdgpu: change pte definitions to 64 bit

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: fix PTE defines
Christian König [Mon, 13 Feb 2017 13:22:58 +0000 (14:22 +0100)]
drm/amdgpu: fix PTE defines

Those should be 64bit, even on a 32bit system.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/amdgpu: Update read_sensor calls to have size parameter (v3)
Tom St Denis [Thu, 9 Feb 2017 19:29:01 +0000 (14:29 -0500)]
drm/amd/amdgpu: Update read_sensor calls to have size parameter (v3)

This update allows sensors to return more than 1 value and
indicates to the caller how many bytes are written.

The debugfs interface has been updated to handle reading all
of the values.  Simply seek to the enum value (multiplied
by 4) and then read as many bytes as the sensor provides.

(v2):  Don't set size to 4 before reading GPU_POWER
(v3): agd: rebase

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>