Huang Rui [Wed, 20 Feb 2019 12:00:21 +0000 (20:00 +0800)]
drm/amdgpu: fix the issue of checking on message mapping
The navi10_message_map[index] scope should be in PPSMC_Message_Count not in
SMU_MSG_MAX_COUNT.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 20 Feb 2019 11:43:36 +0000 (19:43 +0800)]
drm/amdgpu: bump smc firmware header version to v2 (v2)
This patch bumps smc firmware header version to v2 for storing soft pptable.
v2: fix the typo, and add prints for v2 header
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 13 Feb 2019 02:44:50 +0000 (10:44 +0800)]
drm/amd/powerplay: update smu11 driver if header for navi10 (v2)
This patch updates smu11 driver if header for navi10 to match 42.09.00 smu
firmware.
v2: clean up comments
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Sat, 2 Feb 2019 03:43:12 +0000 (11:43 +0800)]
drm/amd/powerplay: enable backdoor smu fw loading (v2)
enable backdoor smu fw loading on navi10
v2: squash in define fix (Alex)
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 13:11:11 +0000 (21:11 +0800)]
drm/amd/powerplay: move bootup value before read pptable from vbios
In navi10, we need read the pp_table_id from bootup value, then decide whether
use load the soft pptable.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 12:49:59 +0000 (20:49 +0800)]
drm/amd/powerplay: add navi10 smc ucode init and navi10 ppt functions setting
This patch adds navi10 smc ucode init and ppt functions setting.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 12:32:54 +0000 (20:32 +0800)]
drm/amd/powerplay: set smu v11 funcs for navi10
Naiv10 also uses smu v11 functions.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 11:46:26 +0000 (19:46 +0800)]
drm/amd/powerplay: introduce the navi10 pptable implementation
This patch introduces the navi10 pptable implementation, so far it is already
has firmware loading, pptable side loading, writing back to smc, and feature
mask enabling.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 13:03:24 +0000 (21:03 +0800)]
drm/amd/powerplay: fix the mp/smuio header for navi10
SMU11 should use mp11 and smuio11 headers.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 11:21:25 +0000 (19:21 +0800)]
drm/amd/powerplay: update smu 11 driver if header for navi10
This patch updates smu 11 driver if header for navi10.
UVD/VCE won't be used for navi10. Here, reverve them for vega20.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 31 Jan 2019 11:19:48 +0000 (19:19 +0800)]
drm/amd/powerplay: update smu v11 ppsmc header
This patch updates smu v11 ppsmc header for navi10.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 19 Jul 2017 01:45:26 +0000 (09:45 +0800)]
drm/amdgpu: add to set navi ip blocks
Set the IPs for navi10 in early_init like other asics.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 19 Apr 2019 22:58:21 +0000 (17:58 -0500)]
drm/amdgpu: add Navi10 pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Cox [Thu, 30 May 2019 04:03:45 +0000 (23:03 -0500)]
drm/amdkfd: Add navi10 support to amdkfd. (v3)
KFD (kernel fusion driver) is the kernel driver
for the compute backend for usermode compute
stack.
v2: squash in updates (Alex)
v3: squash in rebase fixes (Alex)
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 8 Jun 2018 10:10:57 +0000 (18:10 +0800)]
drm/amdgpu: update golden setting programming logic
Since from soc15, make sure only AndMasked bit get changed
when applied or_mask
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 5 Mar 2019 11:59:30 +0000 (19:59 +0800)]
drm/amdgpu: Add navi10 kfd support for amdgpu (v3)
KFD (Kernel Fusion Driver) is the compute backend driver
for AMD GPUs.
v2: squash in updates (Alex)
v3: fix warnings (Alex)
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 4 Mar 2019 06:07:37 +0000 (14:07 +0800)]
drm/amdgpu: add navi10 common ip block (v3)
This adds the core SOC code for navi asics.
v1: add place holder and initial basic function (Ray)
v2: add new introduced functions to avoid reference
NULL pointer (Hawking)
v3L squash in updates (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 10 May 2019 16:05:13 +0000 (11:05 -0500)]
drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10
Move to the header file.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 4 Mar 2019 06:41:42 +0000 (14:41 +0800)]
drm/amdgpu: add gfx v10 implementation (v10)
GFX is the graphics and compute block on the GPU.
v1: add initial gfx v10 implementation (Ray)
v2: convert to new get_vm_pde function in emit_vm_flush (Hawking)
v3: switch to new emit ib interfaces (Hawking)
v4: squash in updates (Alex)
v5: remove unused variables (Alex)
v6: v6: some golden regs moved to vbios (Alex)
v7: squash in some cleanups (Alex)
v8: squash in golden settings update (Alex)
v9: squash in whitespace fixes (Ernst Sjöstrand, Alex)
v10: squash in GDS backup size fix and GDS/GWS/OA removal rebase fixes (Hawking)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 25 Jan 2019 07:25:15 +0000 (15:25 +0800)]
drm/amdgpu/mes10.1: add ip block mes10.1 (v2)
MES takes over the scheduling capability of GFX and SDMA,
add MES as a standalone ip.
v2: squash in updates (Alex)
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 25 Jan 2019 06:56:01 +0000 (14:56 +0800)]
drm/amdgpu/mes: enable mes on navi10 and later asic
When amdgpu_mes is enabled and asic family is navi10 and
later asic, enable mes per device.
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 25 Jan 2019 09:54:58 +0000 (17:54 +0800)]
drm/amdgpu/mes: add definitions of ip callback function
Abstract mes ip independent function layer.
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 25 Jan 2019 06:36:23 +0000 (14:36 +0800)]
drm/amdgpu/mes: add mes header file and definition
Add dummy header file and definitions of mes.
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 25 Jan 2019 06:11:35 +0000 (14:11 +0800)]
drm/amdgpu/mes: add amdgpu_mes driver parameter
amdgpu_mes, which is a driver scope parameter, is used
to whether enable mes or not.
MES (Micro Engine Scheduler) is the new on chip hw scheduling
microcontroller. It can be used to handle queue scheduling and
preemption and priorities.
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Mon, 15 Oct 2018 15:38:59 +0000 (11:38 -0400)]
drm/amdgpu: add initial VCN2.0 support (v2)
VCN (Video Core Next) is the video encode/decode block.
Porting over the same functions from VCN1.0
v2: squash in updates (Alex)
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Mon, 15 Oct 2018 20:17:27 +0000 (16:17 -0400)]
drm/amdgpu: add JPEG2.0 decode ring ib test
Add internal register offset for registers involving in ib tests
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Mon, 3 Dec 2018 16:42:28 +0000 (11:42 -0500)]
drm/amdgpu: add JPEG2.0 decode ring test
Use register from JPEG tile, the UVD tile reg won't work for JPEG
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Mon, 15 Oct 2018 19:41:36 +0000 (15:41 -0400)]
drm/amdgpu: add VCN2.0 decode ib test
Add internal register offset for registers involving in ib tests
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Wed, 17 Oct 2018 18:33:48 +0000 (14:33 -0400)]
drm/amdgpu: add VCN2.0 decode ring test
Add internal register offset for registers involving in ring tests
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Mon, 15 Oct 2018 19:07:08 +0000 (15:07 -0400)]
drm/amdgpu: add Navi10 VCN firmware support
Add Navi10 to VCN family
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 31 Mar 2019 14:13:57 +0000 (22:13 +0800)]
drm/amdgpu: add initial support for sdma v5.0 (v6)
SDMA (System DMA) is a general purpose DMA engine usable
by UMDs for transfers or the kernel for paging or GPUVM
updates.
v1: support basic funcitonalites includes rb, ib, vm,
copy buffer and trap irq
v2: convert to use new get_vm_pde in emit_vm_flush
v3: retire amdgpu_ttm_set_active_vram_size from sdma v5
v4: retire the redundant hdp_invalidate implementation
v5: squash in updates
v6: some golden regs moved to vbios
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 12 Jun 2018 10:31:24 +0000 (18:31 +0800)]
drm/amdgpu: set the default value of pa_sc_tile_steering_override
So userspace can access it.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 12 Jun 2018 10:30:04 +0000 (18:30 +0800)]
drm/amdgpu: add pa_sc_tile_steering_override to drm_amdgpu_info_device
the initial/default value of pa_sc_tile_steering_override need to
be exposed to user mode driver
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 7 Feb 2019 11:10:29 +0000 (12:10 +0100)]
drm/amdgpu: disable concurrent flushes for Navi10 v2
Navi10 have a bug in the SDMA which can theoretically cause memory
corruption with concurrent VMID flushes
v2: explicitely check Navi10
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 27 Mar 2019 09:58:25 +0000 (17:58 +0800)]
drm/amdgpu/discovery: refactor ip list traversal
for each ip, check whether it is needed by amdgpu driver,
if yes, record its base addresses
v2: change some DRM_INFO to DRM_DEBUG
v3: remove unused variable (Alex)
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 27 Mar 2019 04:39:18 +0000 (12:39 +0800)]
drm/amdgpu/discovery: add module param for ip discovery enablement
to control enablement.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 27 Mar 2019 12:27:20 +0000 (20:27 +0800)]
drm/amdgpu/discovery: stop converting the units of base addresses
the unit is already in dword
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 27 Mar 2019 09:46:04 +0000 (17:46 +0800)]
drm/amdgpu/discovery: update definition for struct die_header
Update to latest spec.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 27 Mar 2019 04:21:40 +0000 (12:21 +0800)]
drm/amdgpu/discovery: stop taking psp header into account
psp will write a header to vram, but the value exposed in
RCC_CONFIG_MEMSIZE does not include the memory that this header is
written to. Therefore, the interpretation of the table does not need to
take the psp header into account.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 27 Mar 2019 04:19:20 +0000 (12:19 +0800)]
drm/amdgpu/discovery: fix hwid for nbio
Properly set this.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 27 Mar 2019 04:29:49 +0000 (12:29 +0800)]
drm/amdgpu/discovery: use hardcoded mmRCC_CONFIG_MEMSIZE
register base offset of nbio is not known before IP Discovery table is
parsed, so hardcode this value.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 21 Feb 2019 09:55:30 +0000 (17:55 +0800)]
drm/amdgpu/discovery: add harvest info data table
Add support for the harvest tables.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 21 Feb 2019 09:55:05 +0000 (17:55 +0800)]
drm/amdgpu/discovery: update definitions of table_info and binary_header
Use the proper definitions.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 21 Feb 2019 06:05:47 +0000 (14:05 +0800)]
drm/amdgpu/discovery: fix calculations of some gfx info
fix gfx info table handling.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 20 Jun 2019 15:18:50 +0000 (10:18 -0500)]
drm/amdgpu/discovery: add ip discovery initial support
The IP discovery table lists is populated by the psp at power on
and includes all of the hw details on the board:
- List of IPs and MMIO offsets
- IP harvest details
- IP configuration details
v2: prefix struct and function names with 'amdgpu'
v3: read table binary from vram using mmMM_INDEX and mmMM_DATA
update TABLE_BINARY_MAX_SIZE to 64kb (1 TMR)
add 'instance_number' field per ip info
consider endianness and replace uint8/16/32_t with u8/16/32
initialize register base addresses
initialize adev->gfx.config and adev->gfx.cu_info to replace gpu info fw
get major and minor version using a single api
don't expose internal data structures in amdgpu_discovery.h
v4: RCC_CONFIG_MEMSIZE is in MB units
hold mmio_idx_lock while reading ip discovery binary
v5: pick out discovery.h as a cross-OS header
do structure pointer cast directly
consider endianness while using the member of structure
convert base addresses to dword
at boot up, PSP BL copies ip discovery binary from VBIOS(SPIROM) image to the
top of the frame buffer (just below the reserved regions for PSP & SMU).
ip discovery data table includes the collection of each ip's identification
number, base addresses, version number, and harvest setting placeholder.
gc data table includes gfx info structure.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 23 Jan 2019 05:54:26 +0000 (13:54 +0800)]
drm/amdgpu: mark the partial job as preempted in mcbp unit test
In mcbp unit test, the test should detect the preempted job which may
be a partial execution ib and mark it as preempted; so that the gfx
block can correctly generate PM4 frame.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 20 Jun 2019 15:17:31 +0000 (10:17 -0500)]
drm/amdgpu: add mcbp unit test in debugfs (v3)
The MCBP unit test is used to test the functionality of MCBP.
It emualtes to send preemption request and resubmit the unfinished
jobs.
v2: squash in fixes (Alex)
v3: squash in memory leak fix (Jack)
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 8 Jan 2019 07:28:52 +0000 (15:28 +0800)]
drm/amdgpu: program for resuming preempted ib
For new submission ib, CE/DE metadata should be programmed to 0;
for partially execution ib, CE/DE metadata should be restored.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 7 Jan 2019 07:28:01 +0000 (15:28 +0800)]
drm/amdgpu/sdma: allocate CSA per sdma ring
Allocate CSA for the given sdma ring.
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 17 Jan 2019 07:47:36 +0000 (15:47 +0800)]
drm/amdgpu: add ib preemption status in amdgpu_job (v2)
Add ib preemption status in amdgpu_job, so that ring level function
can detect preemption and program for resuming it.
v2: squash in fix to restore job->preamble_status back to status value (Jack)
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 10 Jan 2019 07:50:10 +0000 (15:50 +0800)]
drm/amdgpu: enable the static csa when mcbp enabled
CSA is the Context Save Area for preemption.
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 10 Jan 2019 07:43:33 +0000 (15:43 +0800)]
drm/amdgpu: add mcbp driver parameter
Add mcbp driver parameter, so that mcbp feature can be
enabled/disabled by driver parameter.
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 31 Oct 2018 12:21:55 +0000 (20:21 +0800)]
drm/amdgpu: Add new ring interface preempt_ib
Used to trigger preemtption
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 10 Jan 2019 06:28:08 +0000 (14:28 +0800)]
drm/amdgpu: add the trailing fence per ring
The trailing fence for ring is used to track the
completion of preemption.
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 8 Oct 2018 06:55:42 +0000 (14:55 +0800)]
drm/amdgpu: Add helper function amdgpu_ring_set_preempt_cond_exec
can preempt the ring by setting cond_exec to false
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le.Ma [Fri, 5 Jan 2018 08:21:18 +0000 (16:21 +0800)]
drm/amdgpu: enable virtual display feature for navi10
Virtual display is a pure sw implementation of KMS for use
in virtualization and for bring up and emulation.
Signed-off-by: Le.Ma <Le.Ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sat, 16 Feb 2019 14:22:46 +0000 (22:22 +0800)]
drm/amdgpu/psp11: skip ta firmware for navi10
Not used on Navi10.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sat, 16 Feb 2019 14:17:35 +0000 (22:17 +0800)]
drm/amdgpu: declare navi10 asd firmware
So the dependencies are properly handled.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 14 Feb 2019 11:08:22 +0000 (19:08 +0800)]
drm/amdgpu: load smc ucode at first with psp while rlc auto load is supported
This patch loades smc ucode at first with psp while rlc auto load is supported
on navi10.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 31 Jan 2019 04:19:54 +0000 (12:19 +0800)]
drm/amdgpu: enable psp front door loading by default on navi10
Required for production hw and vddgfx.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 12 Dec 2018 17:29:53 +0000 (01:29 +0800)]
drm/amdgpu/psp: skip mec jt when autoload is enabled
When autoload is enabled, there is no need to load mec jt,
RLC will handle it automatically
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 12 Dec 2018 17:21:30 +0000 (01:21 +0800)]
drm/amd/amdgpu: add flag to mark whether autoload is supported or not
rlc autoload is supported since navi10
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 12 Dec 2018 17:23:56 +0000 (01:23 +0800)]
drm/amdgpu/psp: initialize autoload_supported flag in psp_sw_init
RLC autoload is supported since from Navi10
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 10 May 2019 15:58:44 +0000 (10:58 -0500)]
drm/amdgpu/psp: update psp gfx interface to match with psp fw (v2)
new psp gfx cmd is introuduced for rlc autoload
v2: rebase (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 12 Nov 2018 08:33:08 +0000 (16:33 +0800)]
drm/amdgpu/psp: perform tmr_init and asd_init after loading sysdrv/sos
Since from navi10, the tmr_size should be decided by psp sos according to
toc header. Driver should issue LOAD_TOC to psp sos to get the tmr_size needed.
The allocation of tmr_size then should be done only when sos/sysdrv loading
completed
Accordingly, asd_init also move to psp_hw_start after sos fw loading to make
calling sequence consistent.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 9 Nov 2018 10:09:36 +0000 (18:09 +0800)]
drm/amdgpu/psp: switch to use sos_offset_bytes member as sys_bin_size
Navi10 will have toc built-in sos binary so that using header.ucode_size_bytes
minus sos_size_bytes actually is not sys_bin_size.
Using sos_offset_bytes works for both vega20 (psp_firmware_header_v1_0) and
navi10 (psp_firmware_header_v1_1)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 24 Oct 2018 11:41:13 +0000 (19:41 +0800)]
drm/amdgpu/psp: start rlc autoload after psp recieved all gfx firmware
RLC handles firmware loading for gfx to support vddgfx feature.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 24 Oct 2018 07:25:38 +0000 (15:25 +0800)]
drm/amdgpu/psp: add support to load TOC to psp
Add support for the new load TOC command.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 10 May 2019 15:06:19 +0000 (10:06 -0500)]
drm/amdgpu/psp: add structure to support load toc in psp (v2)
Update the psp interface for the new commands.
v2: rebase (Alex)
FIXME:
GFX_CMD_ID_PROG_REG = 0x0000000B, /* program regs */
GFX_CMD_ID_LOAD_TOC = 0x0000000B, /* Load TOC and obtain TMR size */
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 23 Oct 2018 09:55:38 +0000 (17:55 +0800)]
drm/amdgpu/psp: support print out psp firmware header v1_1 info
Support version 1.1.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 23 Oct 2018 09:49:17 +0000 (17:49 +0800)]
drm/amdgpu/psp: print out psp v11 ucode hdr in drm debug mode
Print the psp header data if requested.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 23 Oct 2018 09:46:17 +0000 (17:46 +0800)]
drm/amdgpu: add helper function to print psp hdr
print the psp header data like we do for other firmwares.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 23 Oct 2018 08:49:11 +0000 (16:49 +0800)]
drm/amdgpu: rename rlc autoload to backdoor autoload
This is to differentiate rlc backdoor autoload from rlc
frontdoor autoload
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 23 Oct 2018 08:27:48 +0000 (16:27 +0800)]
drm/amdgpu: use rlc toc from psp sos binary
Instead of putting toc into driver source code, the toc will
be part of psp_sos fw. Driver need to get and parse it from
psp fw
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 22 Oct 2018 12:34:17 +0000 (20:34 +0800)]
drm/amdgpu/psp: support init psp sos microcode with build-in toc
psp_firmware_header_v1_1 is used for psp sos with build-in toc
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 19 Oct 2018 13:46:05 +0000 (21:46 +0800)]
drm/amdgpu: add structure to support build-in toc to psp sos
Table Of Content (TOC) is used by RLC to auto load gc firmwares.
PSP need to parse the toc to calculate the tmr size needed and
load gc firmwares to tmr for RLC to auto load them finally
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 21 May 2018 08:32:05 +0000 (16:32 +0800)]
drm/amdgpu: Add psp 11.0 support for navi10.
Add psp 11.0 code for navi10. psp 11.0 is not enabled for now.
Will enable it when psp 11.0 firmware is available.
Signed-off-by: Tao Zhou <Tao.Zhou1@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 18 Jul 2017 11:29:37 +0000 (19:29 +0800)]
drm/amdgpu: set navi10's fw loading type as direct
For bring up.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le.Ma [Thu, 26 Apr 2018 08:15:39 +0000 (16:15 +0800)]
drm/amdgpu: add fw load type flag for rlc autoload
Add another firmware load type AMDGPU_FW_LOAD_RLC_AUTO to support firmware
autoloading new feature in gfx10.
This flag can be leveraged for future engines that need autoload fw.
Signed-off-by: Le.Ma <Le.Ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le.Ma [Thu, 26 Apr 2018 08:13:14 +0000 (16:13 +0800)]
drm/amdgpu: add structures for buffer allocate/release for rlc autoload
Allocate a visible framebuffer to store all gfxip ucodes as the format of TOC.
Signed-off-by: Le.Ma <Le.Ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 05:02:40 +0000 (13:02 +0800)]
drm/amdgpu: add navi10 ih ip block (v3)
IH is the interrupt handler block.
v1: add initial ih support (Ray)
v2: add dummy prescreen iv function for navi10 (Hawking)
v3: squash in additional updates (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 5 Mar 2019 11:52:22 +0000 (19:52 +0800)]
drm/amd/display: move dcn v1_0 irq source header to ivsrcid/dcn/
interrupt source packet definitions for the display block (DCN).
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 5 Dec 2018 21:25:51 +0000 (05:25 +0800)]
drm/amdgpu: add irq sources for vcn v2_0 (v2)
Add the interrupt source packet definitions.
v2: update (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sat, 8 Dec 2018 15:06:41 +0000 (23:06 +0800)]
drm/amdgpu: add irq sources for sdma v5_0
Add the interrupt source packet definitions.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 5 Dec 2018 21:23:34 +0000 (05:23 +0800)]
drm/amdgpu: add irq sources for gfx v10_1
Add the interrupt source packet definitions.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 4 Mar 2019 08:27:14 +0000 (16:27 +0800)]
drm/amdgpu: add gmc v10 ip block for navi10 (v6)
GMC in the GPU memory controller.
v1: add place holder and initial basic implementation (Ray)
v2: retire unused amdgpu_gart_set_defaults (Hawking)
v3: re-work get_vm_pde function (Hawking)
v4: replace legacy amdgpu_vram/gtt_location with
amdgpu_gmc_vram/gtt_location (Hawking)
v5: squash in updates (Alex)
v6: use get_vbios_fb_size (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 4 Mar 2019 05:49:28 +0000 (13:49 +0800)]
drm/amdgpu: add mmhub v2 block for navi10 (v4)
mmhub is the memory controller hub for multi-media (VCN).
v1: add place holder and initial functions (Ray)
v2: replace legacy amdgpu_mc structure with amdgpu_gmc (Hawking)
v3: switch to use amdgpu_gmc_pd_addr (Hawking)
v4: squash in updates (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 4 Mar 2019 08:18:27 +0000 (16:18 +0800)]
drm/amdgpu: add gfxhub v2.0 block for navi10 (v4)
gfxhub is the memory controller hub for gfx and sdma.
v1: add place holder and initial basic functions (Ray)
v2: replace the refernce to legacy mc structure with gmc structure
remove the direct use of gart.table_addr (Hawking)
v3: switch to use amdgpu_gmc_pd_addr (Hawking)
v4: squash in updates (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 22 Feb 2019 07:34:00 +0000 (15:34 +0800)]
drm/amdgpu: refine the PTE encoding of PRT for navi10
Due to GCR change from navi10, the PTE encoding of PRT
needs change VSCTL = 01111 (was 0XX1X).
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 25 Jun 2018 13:03:40 +0000 (21:03 +0800)]
drm/amd/gmc9: rename AMDGPU_PTE_MTYPE to AMDGPU_PTE_MTYPE_VG10
To differentiate the mtypes across asics.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 12 Apr 2019 23:17:24 +0000 (18:17 -0500)]
drm/amdgpu: correct pte mtype field for navi
The MTYPE filed moves from bits 58:57 to 50:48 for NV10
And the size of MTYPE field is now 3bits
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 13 Feb 2019 10:43:03 +0000 (18:43 +0800)]
drm/amdgpu/athub2: enable athub2 clock gating
Enable athub2 clock gating and light sleep
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sat, 2 Feb 2019 07:03:11 +0000 (15:03 +0800)]
drm/amdgpu: add flag to support IH clock gating
Add new flag for IH (interrupt handler) clockgating.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 29 Aug 2018 13:18:19 +0000 (21:18 +0800)]
drm/amdgpu: add new HDP CG flags
HDP 5.0 supports SRAM power gating. all the LS (Light Sleep)/
DS (Deep Sleep)/SD (Shut Down) modes are supported. However,
only one of these modes can be enabled at one time.
There is no dynamic power mode switch support. clock/power gating
has to be disabled before making any power mode change.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 14 Aug 2018 12:54:35 +0000 (20:54 +0800)]
drm/amdgpu: create mqd for gfx queues on navi10
mqd is the memory queue descriptor for gfx and compute.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 21 Mar 2019 10:20:23 +0000 (18:20 +0800)]
drm/amdgpu: enable async gfx ring by default
VDDGFX requires gfx queue to be installed via MAP_QUEUES packet.
Hence, enable async gfx ring by default.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 31 Jul 2018 07:00:40 +0000 (15:00 +0800)]
drm/amdgpu: add module parameter for async_gfx_ring enablement
0 means disable async_gfx_ring and is the default setting
1 means enable async_gfx_ring
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 11 Mar 2019 14:04:44 +0000 (22:04 +0800)]
drm/amdgpu: enable gfx eop interrupt per gfx pipe
Navi10 has 2 gfx pipe and need to enable gfx eop interrupt
per pipe, instead of enable eop int for all gfx pipes at one
time.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 8 Jan 2019 05:33:46 +0000 (13:33 +0800)]
drm/amdgpu/gfx10: add special unmap_queues packet for preemption
CP introduced a special unmap_queues packet for gfx preemtion.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 5 Mar 2019 14:05:02 +0000 (22:05 +0800)]
drm/amdgpu: Move common code to amdgpu_gfx.c
move common code to amdgpu_gfx_enable_kcq,so
this function can be shared with gfx8 and gfx9
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / openwrt / staging / blogic.git / log