openwrt/staging/blogic.git
5 years agoMerge branch 'drm-next-5.1' of git://people.freedesktop.org/~agd5f/linux into drm...
Dave Airlie [Thu, 31 Jan 2019 04:19:45 +0000 (14:19 +1000)]
Merge branch 'drm-next-5.1' of git://people.freedesktop.org/~agd5f/linux into drm-next

New stuff for 5.1.
amdgpu:
- DC bandwidth formula updates
- Support for DCC on scanout surfaces
- Support for multiple IH rings on soc15 asics
- Fix xgmi locking
- Add sysfs interface to get pcie usage stats
- Simplify DC i2c/aux code
- Initial support for BACO on vega10/20
- New runtime SMU feature debug interface
- Expand existing sysfs power interfaces to new clock domains
- Handle kexec properly
- Simplify IH programming
- Rework doorbell handling across asics
- Drop old CI DPM implementation
- DC page flipping fixes
- Misc SR-IOV fixes

amdkfd:
- Simplify the interfaces between amdkfd and amdgpu

ttm:
- Add a callback to notify the driver when the lru changes

sched:
- Refactor mirror list handling
- Rework hw fence processing

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190125231517.26268-1-alexander.deucher@amd.com
5 years agodrm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined...
ndesaulniers@google.com [Fri, 25 Jan 2019 00:52:59 +0000 (16:52 -0800)]
drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines

arch/x86/Makefile disables SSE and SSE2 for the whole kernel.  The
AMDGPU drivers modified in this patch re-enable SSE but not SSE2.  Turn
on SSE2 to support emitting double precision floating point instructions
rather than calls to non-existent (usually available from gcc_s or
compiler_rt) floating point helper routines.

Link: https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html
Link: https://github.com/ClangBuiltLinux/linux/issues/327
Cc: stable@vger.kernel.org # 4.19
Reported-by: S, Shirish <Shirish.S@amd.com>
Reported-by: Matthias Kaehlcke <mka@google.com>
Suggested-by: James Y Knight <jyknight@google.com>
Suggested-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Matthias Kaehlcke <mka@chromium.org>
Tested-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: support Vega12 retrieving and setting ppfeatures
Evan Quan [Fri, 25 Jan 2019 06:15:10 +0000 (14:15 +0800)]
drm/amd/powerplay: support Vega12 retrieving and setting ppfeatures

Enable retrieving and setting ppfeatures on Vega12.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: support Vega12 SOCclk and DCEFclk dpm level settings
Evan Quan [Fri, 25 Jan 2019 06:12:40 +0000 (14:12 +0800)]
drm/amd/powerplay: support Vega12 SOCclk and DCEFclk dpm level settings

Enable SOCclk and DCEFclk dpm level retrieving and setting on Vega12.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: support Vega10 retrieving and setting ppfeatures
Evan Quan [Fri, 25 Jan 2019 06:11:31 +0000 (14:11 +0800)]
drm/amd/powerplay: support Vega10 retrieving and setting ppfeatures

Enable retrieving and setting ppfeatures on Vega10.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: support Vega10 SOCclk and DCEFclk dpm level settings
Evan Quan [Fri, 25 Jan 2019 06:09:40 +0000 (14:09 +0800)]
drm/amd/powerplay: support Vega10 SOCclk and DCEFclk dpm level settings

Enable SOCclk and DCEFclk dpm level retrieving and setting on Vega10.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: avoid frequent metrics table export
Evan Quan [Thu, 24 Jan 2019 09:55:39 +0000 (17:55 +0800)]
drm/amd/powerplay: avoid frequent metrics table export

That's unnecessary. Also it makes more sense to show all the clocks
on one metrics table export.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: correct Vega20 gfxclk readout under DS
Evan Quan [Thu, 24 Jan 2019 09:50:39 +0000 (17:50 +0800)]
drm/amd/powerplay: correct Vega20 gfxclk readout under DS

Current implementation cannot report the correct gfxclk under DS.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Connect dig_fe to otg directly instead of calling bios
hersen wu [Fri, 11 Jan 2019 17:43:20 +0000 (12:43 -0500)]
drm/amd/display: Connect dig_fe to otg directly instead of calling bios

[Why] After call bios table crtc_source_select, dal will program fmt
again. The bios table program dig_source_select and other fmt register
for bios usage which is redundancy and uncessary.

[How] Program dig_soruce_select register directly

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: 3.2.15
Steven Chiu [Fri, 11 Jan 2019 21:55:54 +0000 (16:55 -0500)]
drm/amd/display: 3.2.15

Signed-off-by: Steven Chiu <steven.chiu@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: take dpms_off into account for edp turn off logic
Eric Yang [Fri, 11 Jan 2019 22:09:18 +0000 (17:09 -0500)]
drm/amd/display: take dpms_off into account for edp turn off logic

[why]
Previously we incorrectly skipped backlight control when stream is
present but dpms_off = true. This causes backlight to remain on in
the we boot up or resume into a external display only configuration
where VBIOS posted on the eDP.

[How]
Add dpms_off into the condition for edp need to turn off.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agorevert "drm/amd/display: Add condition to sync eDP SW status and HW status"
Eric Yang [Fri, 11 Jan 2019 21:54:05 +0000 (16:54 -0500)]
revert "drm/amd/display: Add condition to sync eDP SW status and HW status"

[Why]
This change causes regression for S4 resume where gamma is not
programmed. The change incorrectly updates the requested dpms_off
state.

This reverts commit d2b1d6bbc56afab8ebae9d52d7ca0ea3569bd600.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Adjust ABM 2.2 contrast parameters
Josip Pavic [Thu, 10 Jan 2019 20:23:07 +0000 (15:23 -0500)]
drm/amd/display: Adjust ABM 2.2 contrast parameters

[Why]
Improved contrast in ABM 2.2 is desired

[How]
Increase the contrast factor for ABM levels 2, 3 and 4

Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Default to linear output gamma
Krunoslav Kovac [Tue, 8 Jan 2019 23:32:34 +0000 (18:32 -0500)]
drm/amd/display: Default to linear output gamma

[Why] Our output TF calculation doesn't work if no user-specified gamma
correction. Normally, user provides this, but driver sohuld just assume
default (linear) gamma otherwise.

[How] Remove output TF dependency on user gamma being provided.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Fix use of uninitialized union
John Barberiz [Tue, 8 Jan 2019 22:43:08 +0000 (17:43 -0500)]
drm/amd/display: Fix use of uninitialized union

[Why]
An uninitialized variable would randomly initialize to a large
value. This caused enough delay to fail DP Compliance Test 400.2.1.

[How]
Initialize the variable.

Signed-off-by: John Barberiz <John.Barberiz@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Create switching mechanism for ABM 2.2
Josip Pavic [Tue, 8 Jan 2019 19:46:05 +0000 (14:46 -0500)]
drm/amd/display: Create switching mechanism for ABM 2.2

[Why]
Need method of detecting which version of the DMCU FW is loaded and
load the appropriate iRAM.

[How]
Create definition for ABM 2.2 iRAM, and load it if the DMCU FW version
number matches the ABM 2.2 version; otherwise load ABM 2.1 iRAM.

Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Update DMCU versioning mechanism
Josip Pavic [Tue, 8 Jan 2019 19:43:10 +0000 (14:43 -0500)]
drm/amd/display: Update DMCU versioning mechanism

[Why]
Current date based versioning doesn't tell us about feature version
and build version, and is not useful for debug.

[How]
Add versioning based on feature and build

Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Know what a pageflip is
David Francis [Wed, 12 Dec 2018 19:11:53 +0000 (14:11 -0500)]
drm/amd/display: Know what a pageflip is

[Why]
We were assuming that any commit with allow_modeset == false
was a pageflip.  This was against drm intention and only
worked by sheer luck

[How]
A pageflip is the change from one framebuffer to another

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Perform plane updates only when needed
David Francis [Wed, 19 Dec 2018 15:45:16 +0000 (10:45 -0500)]
drm/amd/display: Perform plane updates only when needed

[Why]
Our old logic: if pageflip, update freesync and plane address.
Otherwise, update everything.
This over-updated on non-pageflip cases, and it failed to
update if pageflip and non-pageflip changes occurred on
the same commit

[How]
Update flip_addrs on pageflips.
Update scaling_info when it changes.
Update color fields on color changes.
Updates plane_info always because we don't have a good way of
knowing when it needs to be updated.

Unfortunately, this means that every stream commit involves two
calls into DC.  In particular, on pageflips there is a second,
pointless update that changes nothing but costs several
microseconds (about a 50% increase in time taken). The update is
fast, but there are comparisons and some useless programming.

Leave TODOs indicating dissatisfaction.

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Call into DC once per multiplane flip
David Francis [Tue, 11 Dec 2018 20:17:15 +0000 (15:17 -0500)]
drm/amd/display: Call into DC once per multiplane flip

[Why]
amdgpu_dm_commit_planes was performing multi-plane
flips incorrectly:

It waited for vblank once per flipped plane

It prepared flip ISR and acquired the corresponding vblank ref
once per plane, although it closed ISR and put the ref once
per crtc

It called into dc once per flipped plane, duplicating some work

[How]
Wait for vblank, get vblank ref, prepare flip ISR, and call into
DC only once, and only if there is a pageflip

Make freesync continue to update planes even if vrr information
has already been changed

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Simplify underscan and ABM commit
David Francis [Tue, 18 Dec 2018 20:30:19 +0000 (15:30 -0500)]
drm/amd/display: Simplify underscan and ABM commit

[Why]
Underscan and ABM are connector properties but require updates
to DC stream state.  Previously, on updates to these properties
the affected stream and all its planes were committed.
This is unnecessary; only a few fields on the stream need
to be changed.

[How]
If scaling or ABM have changed, change the stream and
create a stream update with those changes.  Call
DC with only those fields.

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Let updates with no scaling changes be fast
David Francis [Thu, 3 Jan 2019 19:38:06 +0000 (14:38 -0500)]
drm/amd/display: Let updates with no scaling changes be fast

[Why]
DC was assuming that any surface_update->scaling_info
meant the update was at least medium.  However, if nothing
has changed there is no scaling to program, so there is
no problem with the update being fast

[How]
If every update flag is not set, the update is fast

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Introduce DC VM interface
Eryk Brol [Fri, 7 Dec 2018 15:25:13 +0000 (10:25 -0500)]
drm/amd/display: Introduce DC VM interface

Virtual memory allows display to support flipping to surfaces which
are not allocated contiguously in memory with physical addresses,
instead a 1-4 level page table is used.

This is beneficial because it allows the scattering of large surfaces
to improve memory efficiency and security.

Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Restructure DCN10 hubbub
Eryk Brol [Fri, 4 Jan 2019 15:29:00 +0000 (10:29 -0500)]
drm/amd/display: Restructure DCN10 hubbub

[Why]
Change DCN10 hubbub to use hubbub as a base and allow all future DCN
hubbubs to do the same instead of using DCN10_hubbub. This increases
readability and doesn't require future hubbubs to inherit anything
other than the base hubbub struct.

[How]
Create separate DCN10_hubbub struct which uses the hubbub struct as
a base.

Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: fix eDP fast bootup for pre-raven asic
hersen wu [Fri, 11 Jan 2019 15:39:30 +0000 (10:39 -0500)]
drm/amd/display: fix eDP fast bootup for pre-raven asic

[Why]
For fastboot, Bios will light up eDP before SW driver is loaded. SW
driver will check if eDP is lit by bios through reading the
BIOS_SCRATCH_3 register. If lit, SW driver will not power down eDP
power and phy to save time.

Definition of BIOS_SCRATCH_3 are missing for pre-raven asic. This
causes eDP fast boot to not work property. For some eDP panels, even
if dp tx sends NoVideoStream_flag =1 and dpcd 0x600=2, eDP rx may not
handle properly. This may cause a short flash on screen.

[How] Add definition of BIOS_SCRATCH_3 for all asic

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Yongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/sched: Rework HW fence processing.
Andrey Grodzovsky [Wed, 5 Dec 2018 19:21:28 +0000 (14:21 -0500)]
drm/sched: Rework HW fence processing.

Expedite job deletion from ring mirror list to the HW fence signal
callback instead from finish_work, together with waiting for all
such fences to signal in drm_sched_stop we garantee that
already signaled job will not be processed twice.
Remove the sched finish fence callback and just submit finish_work
directly from the HW fence callback.

v2: Fix comments.
v3: Attach  hw fence cb to sched_job
v5: Rebase

Suggested-by: Christian Koenig <Christian.Koenig@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/sched: Refactor ring mirror list handling.
Andrey Grodzovsky [Tue, 4 Dec 2018 21:56:14 +0000 (16:56 -0500)]
drm/sched: Refactor ring mirror list handling.

Decauple sched threads stop and start and ring mirror
list handling from the policy of what to do about the
guilty jobs.
When stoppping the sched thread and detaching sched fences
from non signaled HW fenes wait for all signaled HW fences
to complete before rerunning the jobs.

v2: Fix resubmission of guilty job into HW after refactoring.

v4:
Full restart for all the jobs, not only from guilty ring.
Extract karma increase into standalone function.

v5:
Rework waiting for signaled jobs without relying on the job
struct itself as those might already be freed for non 'guilty'
job's schedulers.
Expose karma increase to drivers.

v6:
Use list_for_each_entry_safe_continue and drm_sched_process_job
in case fence already signaled.
Call drm_sched_increase_karma only once for amdgpu and add documentation.

v7:
Wait only for the latest job's fence.

Suggested-by: Christian Koenig <Christian.Koenig@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: enable MGPU fan boost feature on Vega10
Evan Quan [Tue, 22 Jan 2019 10:05:54 +0000 (18:05 +0800)]
drm/amd/powerplay: enable MGPU fan boost feature on Vega10

For those SKUs which support this feature only.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: support Vega10 fan table V3
Evan Quan [Tue, 22 Jan 2019 09:54:22 +0000 (17:54 +0800)]
drm/amd/powerplay: support Vega10 fan table V3

MGPU fan boost related parameter is added.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: remove old CI DPM implementation
Alex Deucher [Wed, 16 Jan 2019 16:55:04 +0000 (11:55 -0500)]
drm/amdgpu: remove old CI DPM implementation

The power smu7 powerplay code is much more robust and has
been the default for a while now.  Remove the old code.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/radeon: check if device is root before getting pci speed caps
Alex Deucher [Tue, 15 Jan 2019 17:05:16 +0000 (12:05 -0500)]
drm/radeon: check if device is root before getting pci speed caps

Check if the device is root rather before attempting to see what
speeds the pcie port supports.  Fixes a crash with pci passthrough
in a VM.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109366
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Add missing power attribute to APU check
Alex Deucher [Thu, 10 Jan 2019 03:19:28 +0000 (22:19 -0500)]
drm/amdgpu: Add missing power attribute to APU check

Add missing power_average to visible check for power
attributes for APUs.  Was missed before.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: change the max clock level to 16
Evan Quan [Mon, 21 Jan 2019 09:57:29 +0000 (17:57 +0800)]
drm/amd/display: change the max clock level to 16

As the gfxclk for SMU11 can have at most 16 discrete levels.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: run btc before enabling all SMU features
Evan Quan [Mon, 21 Jan 2019 06:39:26 +0000 (14:39 +0800)]
drm/amd/powerplay: run btc before enabling all SMU features

BTC is needed before enabling all SMU features.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: fit the SOC clock also to the new performance level
Evan Quan [Mon, 21 Jan 2019 06:05:37 +0000 (14:05 +0800)]
drm/amd/powerplay: fit the SOC clock also to the new performance level

The SOC clock needs also to fit the new performance level.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: enforce display related settings only on needed
Evan Quan [Thu, 17 Jan 2019 09:52:41 +0000 (17:52 +0800)]
drm/amd/powerplay: enforce display related settings only on needed

No display related settings are needed on dpm level change.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: avoid unnecessary dpm level setting
Evan Quan [Thu, 17 Jan 2019 09:48:30 +0000 (17:48 +0800)]
drm/amd/powerplay: avoid unnecessary dpm level setting

No dpm level setting is needed when the request level
is actually same as current.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: add flags to emit_ib interface v2
Jack Xiao [Fri, 18 Jan 2019 10:13:36 +0000 (18:13 +0800)]
drm/amdgpu: add flags to emit_ib interface v2

Replace the last bool type parameter with a general flags parameter,
to make the last parameter be able to contain more information.

v2: drop setting need_ctx_switch = false

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: OD setting fix on Vega10
Kenneth Feng [Fri, 18 Jan 2019 10:08:19 +0000 (18:08 +0800)]
drm/amd/powerplay: OD setting fix on Vega10

gfxclk for OD setting is limited to 1980M for non-acg
ASICs of Vega10

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: sriov should skip asic_reset in device_init
wentalou [Thu, 17 Jan 2019 09:38:33 +0000 (17:38 +0800)]
drm/amdgpu: sriov should skip asic_reset in device_init

sriov would meet guest driver load failure,
if calling amdgpu_asic_reset in amdgpu_device_init.
sriov should skip asic_reset in device_init.

Signed-off-by: Wentao Lou <Wentao.Lou@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Add APTX quirk for Lenovo laptop
Alex Deucher [Tue, 15 Jan 2019 17:09:09 +0000 (12:09 -0500)]
drm/amdgpu: Add APTX quirk for Lenovo laptop

Needs ATPX rather than _PR3 for dGPU power control.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=202263
Reviewed-by: Jim Qu <Jim.Qu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
5 years agodrm/amdgpu: fix wrong APU judgement
Evan Quan [Wed, 16 Jan 2019 06:11:50 +0000 (14:11 +0800)]
drm/amdgpu: fix wrong APU judgement

Fix the APU judgement to make it really work as expected.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: check PSP support before adding the ip block
Evan Quan [Tue, 8 Jan 2019 05:57:29 +0000 (13:57 +0800)]
drm/amdgpu: check PSP support before adding the ip block

So that we do not need to check this in every internal function.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Replace kzalloc with kcalloc
Gustavo A. R. Silva [Tue, 15 Jan 2019 05:22:02 +0000 (23:22 -0600)]
drm/amdgpu: Replace kzalloc with kcalloc

Replace kzalloc() function with its 2-factor argument form, kcalloc().

This patch replaces cases of:

kzalloc(a * b, gfp)

with:
kcalloc(a, b, gfp)

Also, improve the coding style and the use of sizeof during
allocation by changing sizeof(struct dc_surface_update) and
sizeof(struct dc_plane_state) to sizeof(*updates) and
sizeof(*surfaces), correspondingly.

This code was detected with the help of Coccinelle.

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: add support for self irq on Vega10 v2
Christian König [Wed, 26 Sep 2018 12:15:21 +0000 (14:15 +0200)]
drm/amdgpu: add support for self irq on Vega10 v2

This finally enables processing of ring 1 & 2.

v2: fix copy&paste error

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: add support for processing IH ring 1 & 2
Christian König [Wed, 26 Sep 2018 11:45:38 +0000 (13:45 +0200)]
drm/amdgpu: add support for processing IH ring 1 & 2

Previously we only added the ring buffer memory, now add the handling as
well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: enable IH ring 1 and ring 2 v4
Christian König [Tue, 18 Sep 2018 12:51:35 +0000 (14:51 +0200)]
drm/amdgpu: enable IH ring 1 and ring 2 v4

The entries are ignored for now, but it at least stops crashing the
hardware when somebody tries to push something to the other IH rings.

v2: limit ring size, add TODO comment
v3: only program rings if they are actually allocated
v4: limit the ring init to Vega10

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: set the executable flag on unused Vega10 PTEs v2
Christian König [Wed, 12 Dec 2018 14:13:10 +0000 (15:13 +0100)]
drm/amdgpu: set the executable flag on unused Vega10 PTEs v2

Otherwise we run into a non-retry fault on access.

It seems to be a hardware bug that the executable bit has
higher priority than the valid bit.

v2: handle clears as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/ttm: stop always moving BOs on the LRU on page fault
Christian König [Fri, 11 Jan 2019 13:12:58 +0000 (14:12 +0100)]
drm/ttm: stop always moving BOs on the LRU on page fault

Move the BO on the LRU only when it is actually moved by a DMA
operation.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-And-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: support retrieving and adjusting dcefclock power levels V2
Evan Quan [Mon, 14 Jan 2019 09:37:26 +0000 (17:37 +0800)]
drm/amd/powerplay: support retrieving and adjusting dcefclock power levels V2

User can use "pp_dpm_dcefclk" to retrieve and adjust dcefclock power
levels.

V2: expose this interface for Vega10 and later ASICs only

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: support retrieving and adjusting fclock power levels V2
Evan Quan [Mon, 14 Jan 2019 07:44:44 +0000 (15:44 +0800)]
drm/amd/powerplay: support retrieving and adjusting fclock power levels V2

User can use "pp_dpm_fclk" to retrieve and adjust fclock power
levels.

V2: expose this interface for Vega20 and later ASICs only

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: support retrieving and adjusting SOC clock power levels V2
Evan Quan [Mon, 14 Jan 2019 06:45:47 +0000 (14:45 +0800)]
drm/amd/powerplay: support retrieving and adjusting SOC clock power levels V2

User can use "pp_dpm_socclk" to retrieve and adjust SOC clock power
levels.

V2: expose this interface for Vega10 and later ASICs only

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: support enabled ppfeatures retrieving and setting V3
Evan Quan [Mon, 14 Jan 2019 06:06:54 +0000 (14:06 +0800)]
drm/amd/powerplay: support enabled ppfeatures retrieving and setting V3

User can use "ppfeatures" sysfs interface to retrieve and set enabled
powerplay features.

V2: expose this feature for Vega10 and later dGPUs
V3: squash in removal of unused variable (Alex)

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: set bulk_moveable to false when lru changed v2
Chunming Zhou [Thu, 10 Jan 2019 07:49:54 +0000 (15:49 +0800)]
drm/amdgpu: set bulk_moveable to false when lru changed v2

if lru is changed, we cannot do bulk moving.
v2:
root bo isn't in bulk moving, skip its change.

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/ttm: add lru notify to bo driver v2
Chunming Zhou [Thu, 10 Jan 2019 09:56:39 +0000 (17:56 +0800)]
drm/ttm: add lru notify to bo driver v2

allow driver do somethings when lru changed.
v2:
address Michel's comments.

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/psp: ignore psp response status
Aaron Liu [Mon, 14 Jan 2019 08:08:32 +0000 (16:08 +0800)]
drm/amdgpu/psp: ignore psp response status

In some cases, psp response status is not 0 even there is no
problem while the command is submitted. Some version of PSP FW
doesn't write 0 to that field.
So here we would like to only print a warning instead of an error
during psp initialization to avoid breaking hw_init and it doesn't
return -EINVAL.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Xiangliang Yu<Xiangliang.Yu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Paul Menzel <pmenzel+amd-gfx@molgen.mpg.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Setting doorbell range registers earlier
Oak Zeng [Mon, 14 Jan 2019 22:32:53 +0000 (16:32 -0600)]
drm/amdgpu: Setting doorbell range registers earlier

HW doorbell writing routing policy: writing to doorbell
not in SDMA/IH/MM/ACV doorbell range will be routed to CP.
So CP doorbell routing depends on doorbell range setting
of above blocks. Setting doorbell range of above blocks
earlier (soc15_common_hw_init) to make sure CP doorbell
writing be routed to CP block.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Fix sdma doorbell range setting
Oak Zeng [Tue, 18 Dec 2018 02:03:45 +0000 (20:03 -0600)]
drm/amdgpu: Fix sdma doorbell range setting

Different ASIC has different SDMA queue number so
different SDMA doorbell range. Introduce an extra
parameter to sdma_doorbell_range function and set
sdma doorbell range correctly.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Add per device sdma_doorbell_range field
Oak Zeng [Tue, 18 Dec 2018 01:42:58 +0000 (19:42 -0600)]
drm/amdgpu: Add per device sdma_doorbell_range field

Different ASIC has different sdma doorbell range. Add
a per device sdma_doorbell_range field and initialize
it.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/soc15: return proper error codes in baco reset
Alex Deucher [Mon, 14 Jan 2019 19:56:42 +0000 (14:56 -0500)]
drm/amdgpu/soc15: return proper error codes in baco reset

Rather than just -1.

Reviewed-by: JimQu <Jim.Qu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Include names of all PP clock types
Rafał Miłecki [Sun, 13 Jan 2019 13:24:07 +0000 (14:24 +0100)]
drm/amd/display: Include names of all PP clock types

This fixes printing clock names in cases like:
[    5.352311] [drm] DM_PPLIB: values for Invalid clock
[    5.352313] [drm] DM_PPLIB:   400000 in kHz
[    5.352313] [drm] DM_PPLIB:   933000 in kHz
[    5.352314] [drm] DM_PPLIB:   1067000 in kHz
[    5.352315] [drm] DM_PPLIB:   1200000 in kHz
[    5.352317] [drm] DM_PPLIB: values for Invalid clock
[    5.352318] [drm] DM_PPLIB:   300000 in kHz
[    5.352318] [drm] DM_PPLIB:   600000 in kHz
[    5.352319] [drm] DM_PPLIB:   626000 in kHz
[    5.352320] [drm] DM_PPLIB:   654000 in kHz
(source: HP EliteBook 745 G5 w. RAVEN 0x1002:0x15DD 0x103C:0x83D5 0xD1)

On my system above "Invalid" names got replaced by "F" and "DCF".

The same problem was occurring on Huawei Matebook D with just 667000 kHz
instead of 400000 kHz.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd: fix typo
Matteo Croce [Mon, 7 Jan 2019 13:06:00 +0000 (14:06 +0100)]
drm/amd: fix typo

Fix spelling mistake: "lenght" -> "length"

Signed-off-by: Matteo Croce <mcroce@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Skip create new stream if crtc state doesn't change
Jerry (Fangzhi) Zuo [Fri, 11 Jan 2019 21:34:31 +0000 (16:34 -0500)]
drm/amd/display: Skip create new stream if crtc state doesn't change

Need to check if crtc state is changed so that mode set is
required before trying to create new stream.

It deals with the MST hotplug use case when plug back to the
same connector where the failure to create new stream for the
inactive crtc on the old connector.

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: use BACO reset on vega20 if platform support
Jim Qu [Thu, 8 Nov 2018 06:07:22 +0000 (14:07 +0800)]
drm/amdgpu: use BACO reset on vega20 if platform support

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: use BACO reset if platform support (v2)
Jim Qu [Wed, 7 Nov 2018 04:29:39 +0000 (12:29 +0800)]
drm/amdgpu: use BACO reset if platform support (v2)

It will fall back to use mode1 reset if platform does not support BACO
feature.

v2: squash in warning fix (Alex)

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/powerper: add vega20 BACO functions
Jim Qu [Thu, 8 Nov 2018 05:02:00 +0000 (13:02 +0800)]
drm/amdgpu/powerper: add vega20 BACO functions

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: update THM IP register header to support BACO
Jim Qu [Thu, 8 Nov 2018 10:32:41 +0000 (18:32 +0800)]
drm/amdgpu: update THM IP register header to support BACO

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: also include NBIO v7.4 register mask header
Jim Qu [Thu, 8 Nov 2018 10:26:22 +0000 (18:26 +0800)]
drm/amdgpu: also include NBIO v7.4 register mask header

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: update NBIO v7.4 to support BACO
Jim Qu [Thu, 8 Nov 2018 10:21:05 +0000 (18:21 +0800)]
drm/amdgpu: update NBIO v7.4 to support BACO

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: expose BACO interfaces to upper level from PP
Jim Qu [Wed, 9 Jan 2019 08:42:05 +0000 (16:42 +0800)]
drm/amdgpu: expose BACO interfaces to upper level from PP

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: add BACO interfaces for vega10
Jim Qu [Wed, 7 Nov 2018 03:24:45 +0000 (11:24 +0800)]
drm/amdgpu: add BACO interfaces for vega10

V2: delay 20ms before BACO out.
V3: rename function to vega10_baco_xxx

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdpgu: add common functions for BACO feature in PP (v2)
Jim Qu [Tue, 20 Nov 2018 02:58:25 +0000 (10:58 +0800)]
drm/amdpgu: add common functions for BACO feature in PP (v2)

V2: squash in crash fix for non-register commands (Alex)

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agoMerge tag 'drm-misc-next-2019-01-23' of git://anongit.freedesktop.org/drm/drm-misc...
Dave Airlie [Thu, 24 Jan 2019 09:52:46 +0000 (19:52 +1000)]
Merge tag 'drm-misc-next-2019-01-23' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

drm-misc-next for 5.1:

UAPI Changes:
 - Addition of the Allwinner tiled format modifier

Cross-subsystem Changes:

Core Changes:
 - dma-buf documentation improvements
 - Removal of now unused fbdev helpers
 - Addition of new drm fbdev helpers
 - Improvements to tinydrm
 - Addition of new drm_fourcc helpers
 - Impromevents to i2c-over-aux to handle I2C_M_STOP

Driver Changes:
 - Add support for the TI DS90C185 LVDS bridge
 - Improvements to the thc63lvdm83d bridge
 - Improvements to sun4i YUV and scaler support
 - Fix to the powerdown sequence of panel-innolux

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190123110317.h4tovujaydo2bfz2@flea
5 years agoMerge tag 'drm-intel-next-2019-01-10' of git://anongit.freedesktop.org/drm/drm-intel...
Dave Airlie [Thu, 24 Jan 2019 09:44:16 +0000 (19:44 +1000)]
Merge tag 'drm-intel-next-2019-01-10' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

- Unwind failure on pinning the gen7 PPGTT (Chris)
- Fastset updates to make sure DRRS and PSR are properly enabled (Hans)
- Header include clean-up (Brajeswar, Jani)
- Improvements and clean-up on debugfs (Chris, Jani)
- Avoid division by zero on CNL clocks setup (Xiao)
- Restrict PSMI context load w/a to Haswell GT1 (Chris)
- Remove HW semaphores for gen7 inter-engine sync (Chris)
- Pull the render flush into breadcrumb emission (Chris)
- i915_params copy and free helpers and other reorgs and docs (Jani)
- Remove has_pooled_eu static initializer (Tvrtko)
- Updates on kerneldoc (Chris)
- Remove redundant trailing request flush (Chris)
- ringbuffer irq seqno fixes and clean-up (Chris)
- splitting off runtime device info and other clean-up around (Jani)
- Selftests improvements (Chris, Daniele)
- Flush RING_IMR changes before changing the global GT IMR on gen6 and HSW (Chris)
- Some improvements and fixes around GPU reset and GPU hang report (Chris)
- Remove partial attempt to swizzle on pread/pwrite (Chris)
- Return immediately if trylock fails for direct-reclaim (Chris)
- Downgrade scare message for unknown HuC firmware (Jani)
- ACPI / PMIC for MIPI / DSI (Hans)
- Reduce i915_request_alloc retirement to local context (Chris)
- Init per-engine WAs for all engines (Daniele)
- drop DPF code for gen8+ (Daniele)
- Guard error capture against unpinned vma (Chris)
- Use mutex_lock_killable from inside the shrinker (Chris)
- Removing pooling from struct_mutex from vmap shrinker (Chris)

Signed-off-by: Dave Airlie <airlied@redhat.com>
# gpg: Signature made Fri 11 Jan 2019 09:58:18 AEST
# gpg:                using RSA key FA625F640EEB13CA
# gpg: Good signature from "Rodrigo Vivi <rodrigo.vivi@intel.com>"
# gpg:                 aka "Rodrigo Vivi <rodrigo.vivi@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6D20 7068 EEDD 6509 1C2C  E2A3 FA62 5F64 0EEB 13CA

# Conflicts:
# drivers/gpu/drm/i915/intel_dp.c
# drivers/gpu/drm/i915/intel_drv.h
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190114183820.GA2855@intel.com
5 years agodrm/panel: panel-innolux: set display off in innolux_panel_unprepare
Hsin-Yi, Wang [Wed, 9 Jan 2019 06:59:22 +0000 (14:59 +0800)]
drm/panel: panel-innolux: set display off in innolux_panel_unprepare

Move mipi_dsi_dcs_set_display_off() from innolux_panel_disable()
to innolux_panel_unprepare(), so they are consistent with
innolux_panel_enable() and innolux_panel_prepare().

This also fixes some mode check and irq timeout issue in MTK dsi code.

Since some dsi code (e.g. mtk_dsi) have following call trace:
1. drm_panel_disable(), which calls innolux_panel_disable()
2. switch to cmd mode
3. drm_panel_unprepare(), which calls innolux_panel_unprepare()

However, mtk_dsi needs to be in cmd mode to be able to send commands
(e.g. mipi_dsi_dcs_set_display_off() and mipi_dsi_dcs_enter_sleep_mode()),
so we need these functions to be called after the switch to cmd mode happens,
i.e. in innolux_panel_unprepare.

Signed-off-by: Hsin-Yi, Wang <hsinyi@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190109065922.231753-1-hsinyi@chromium.org
5 years agodrm/dp: Implement I2C_M_STOP for i2c-over-aux
Ville Syrjälä [Fri, 28 Sep 2018 18:04:01 +0000 (21:04 +0300)]
drm/dp: Implement I2C_M_STOP for i2c-over-aux

Consult the I2C_M_STOP flag to determine whether to set the MOT bit or
not. Makes it possible to send multiple messages in one go with
stop+start generated between the messages (as opposed nothing or
repstart depending on whether thr address/rw changed).

Not sure anyone has actual use for this but figured I'd handle it
since I started to look at that flag for MST remote i2c xfers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180928180403.22499-3-ville.syrjala@linux.intel.com
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
5 years agodrm/dp: use DRM_DEBUG_DP() instead of drm_dbg for logging
Jani Nikula [Mon, 21 Jan 2019 11:27:58 +0000 (13:27 +0200)]
drm/dp: use DRM_DEBUG_DP() instead of drm_dbg for logging

We have a wrapper for a reason.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190121112758.10978-1-jani.nikula@intel.com
5 years agodrm: fix drm_can_sleep() comment
Sam Ravnborg [Sun, 20 Jan 2019 17:12:17 +0000 (18:12 +0100)]
drm: fix drm_can_sleep() comment

Reversed logic when writing the original comment, now fixed.

Fixes: e9eafcb58921 ("drm: move drm_can_sleep() to drm_util.h")
Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Sean Paul <sean@poorly.run>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20190120171217.12508-1-sam@ravnborg.org
5 years agodrm/stm: ltdc: remove set but not used variable 'src_h'
YueHaibing [Fri, 28 Sep 2018 10:39:40 +0000 (10:39 +0000)]
drm/stm: ltdc: remove set but not used variable 'src_h'

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/stm/ltdc.c: In function 'ltdc_plane_atomic_check':
drivers/gpu/drm/stm/ltdc.c:694:13: warning:
 variable 'src_y' set but not used [-Wunused-but-set-variable]
  u32 src_x, src_y, src_w, src_h;
             ^
             ^
drivers/gpu/drm/stm/ltdc.c:694:6: warning:
 variable 'src_x' set but not used [-Wunused-but-set-variable]
  u32 src_x, src_y, src_w, src_h;
      ^

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/1538131180-34108-1-git-send-email-yuehaibing@huawei.com
5 years agodrm/sun4i: frontend: Hook-in support for the A20
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:33 +0000 (15:51 +0100)]
drm/sun4i: frontend: Hook-in support for the A20

This adds the appropriate device-tree compatible for hooking frontend
support for the A20. Since the hardware is very similar to the A10, it
shares the same quirks (which were already introduced).

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-24-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: frontend: Hook-in support for the A10, with specific quirks
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:32 +0000 (15:51 +0100)]
drm/sun4i: frontend: Hook-in support for the A10, with specific quirks

This adds the appropriate device-tree compatible and quirk data for
hooking frontend support for the A20. It supports the FIR coefficients
ready bit but not the access control bit. It also takes different phase
values than the A33 for these coefficients.

The compatible is already used in the A10 device-tree and already
documented in the device-tree bindings.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-23-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: frontend: Move the FIR filter phases to our quirks
Maxime Ripard [Fri, 18 Jan 2019 14:51:31 +0000 (15:51 +0100)]
drm/sun4i: frontend: Move the FIR filter phases to our quirks

The FIR filters phase depend on the SoC, so let's move it to our quirks
structure instead of removing them.

Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-22-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: Make COEF_RDY conditional
Maxime Ripard [Fri, 18 Jan 2019 14:51:30 +0000 (15:51 +0100)]
drm/sun4i: Make COEF_RDY conditional

The COEF_RDY bit isn't found in all the SoCs featuring some variant of the
frontend.

Add it to our quirks structure.

Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-21-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: Set the coef_rdy bit right after the coef have been set
Maxime Ripard [Fri, 18 Jan 2019 14:51:29 +0000 (15:51 +0100)]
drm/sun4i: Set the coef_rdy bit right after the coef have been set

The COEF_RDY bit is used to tell the hardware that new FIR filters
coefficients have been written to the registers and that the hardware
should take them into account starting next frame.

Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-20-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: frontend: Add a quirk structure
Maxime Ripard [Fri, 18 Jan 2019 14:51:28 +0000 (15:51 +0100)]
drm/sun4i: frontend: Add a quirk structure

The ACCESS_CTRL bit is not found on all the variants of the frontend, so
let's introduce a structure that will hold whether or not we need to set
it, and associate it with the compatible.

This will be extended for further similar quirks later on.

Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-19-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: Move access control before setting the register as documented
Maxime Ripard [Fri, 18 Jan 2019 14:51:27 +0000 (15:51 +0100)]
drm/sun4i: Move access control before setting the register as documented

Unlike what is currently being done, the ACCESS_CTRL bit documentation asks
that this bit should be set before modifying any register. The code in the
BSP also does this, so make sure we do this as well.

Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-18-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: drv: Allow framebuffer modifiers in mode config
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:26 +0000 (15:51 +0100)]
drm/sun4i: drv: Allow framebuffer modifiers in mode config

This is the final step to indicate to the core that our driver
supports framebuffer modifiers.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-17-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: layer: Add tiled modifier support and helper
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:25 +0000 (15:51 +0100)]
drm/sun4i: layer: Add tiled modifier support and helper

This introduces a list of supported modifiers for the driver, that
includes the Allwinner tiled modifier, as well as a format_mod_supported
callback.

The callback uses both the backend and frontend helpers to indicate
per-format modifier support (including for the linear modifier).

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-16-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: frontend: Add and use helper for checking tiling support
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:24 +0000 (15:51 +0100)]
drm/sun4i: frontend: Add and use helper for checking tiling support

This introduces a helper to check whether a frontend input format
supports tiling mode. This helper is used when tiling is requested in
the frontend format support helper.

Only semiplanar and planar YUV formats are supported by the hardware.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-15-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: Add buffer stride and offset configuration for tiling mode
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:23 +0000 (15:51 +0100)]
drm/sun4i: Add buffer stride and offset configuration for tiling mode

This introduces stride and offset configuration for the VPU tiling mode.
Stride is calculated differently than it is for linear formats and an
offset is calculated, for which new register definitions are introduced.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-14-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: frontend: Add support for tiled YUV input mode configuration
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:22 +0000 (15:51 +0100)]
drm/sun4i: frontend: Add support for tiled YUV input mode configuration

This introduces the data input mode definitions for the tiled YUV mode,
that are used in the input mode helper if tiling is requested.

The modifier is passed to the helper from the framebuffer to determine
if tiling is requested.

Only semiplanar and planar YUV formats are supported for tiling mode.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-13-paul.kocialkowski@bootlin.com
5 years agodrm/fourcc: Add definitions for Allwinner vendor and VPU tiled format
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:21 +0000 (15:51 +0100)]
drm/fourcc: Add definitions for Allwinner vendor and VPU tiled format

This introduces specific definitions for vendor Allwinner and its
associated tiled format modifier. This modifier is used for the output
format of the VPU, that can be imported directly with the display
engine hardware supported by the sun4i-drm driver.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-12-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: frontend: Add support for planar YUV input formats
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:20 +0000 (15:51 +0100)]
drm/sun4i: frontend: Add support for planar YUV input formats

Planar YUV formats come with 3 distinct planes, which requires
configuring the frontend line stride and address registers for the
third plane.

Our hardware only supports the YUV planes order and in order to support
formats with a YVU plane order, a helper is introduced to indicate
whether to invert the address of the two chroma planes.

Missing definitions for YUV411 and YUV444 input format configuration are
also introduced as support is added for these formats. For the input
sequence part, no configuration is required for planar YUV formats so
zero is returned in that case.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-11-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: frontend: Add support for semi-planar YUV input formats
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:19 +0000 (15:51 +0100)]
drm/sun4i: frontend: Add support for semi-planar YUV input formats

Semi-planar YUV formats use two distinct planes, one for luminance and
one for chrominance. To add support for them, we need to configure the
second line stride and buffer address registers to setup the second YUV
plane.

New definitions are introduced to configure the input format register
for the YUV420 and YUV422 semi-planar formats.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-10-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: frontend: Add support for packed YUV422 input formats
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:18 +0000 (15:51 +0100)]
drm/sun4i: frontend: Add support for packed YUV422 input formats

This introduces support for packed YUV formats with 4:2:2 sampling using
the frontend. Definitions are introduced for the data format and pixel
sequence input format register values.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-9-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: frontend: Configure and enable YUV to RGB CSC when needed
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:17 +0000 (15:51 +0100)]
drm/sun4i: frontend: Configure and enable YUV to RGB CSC when needed

In prevision of adding support for YUV formats, set the YUV to RGB
colorspace conversion coefficients if required and don't bypass the
CSC engine when converting.

The BT601 coefficients from the A33 BSP are copied over from the backend
code. Because of module inter-dependency, we can't have the frontend use
these coefficients from the backend directly.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-8-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: Move the BT.601 CSC coefficients to the frontend
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:16 +0000 (15:51 +0100)]
drm/sun4i: Move the BT.601 CSC coefficients to the frontend

Both the backend and the frontend need the BT.601 CSC coefficients for
YUV to RGB conversion. Since the backend has a dependency on the
frontend (and not the other way round), move the coefficients there
so that both can access them without having to duplicate them.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-7-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: frontend: Determine input format based on colorspace
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:15 +0000 (15:51 +0100)]
drm/sun4i: frontend: Determine input format based on colorspace

Since all the RGB input formats have the same value for the DATA_FMT
field of the INPUT_FMT register, we can group them when the format is
known to be RGB. Here, we assume that a non-YUV format is RGB, because
the hardware does not support any other colorspace than RGB and YUV.

Use the DRM format info structure to check whether the format uses a
YUV colorspace.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-6-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: frontend: Pass DRM format info to input format helpers
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:14 +0000 (15:51 +0100)]
drm/sun4i: frontend: Pass DRM format info to input format helpers

The helper returning the input mode needs to know the number of planes
for the provided format. Passing the fourcc requires iterating through
the format info list in order to return the number of planes.

Pass the DRM format info structure directly instead to all helpers
related to configuring the input format, since it's available to the
caller. Also rename the input format in the caller function to keep
things consistent.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-5-paul.kocialkowski@bootlin.com
5 years agodrm/sun4i: backend: Use explicit fourcc helpers for packed YUV422 check
Paul Kocialkowski [Fri, 18 Jan 2019 14:51:13 +0000 (15:51 +0100)]
drm/sun4i: backend: Use explicit fourcc helpers for packed YUV422 check

Checking for the number of planes is not sufficient to en ensure that
the format is a packed YUV422.

Use explicit fourcc helpers for the check instead.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-4-paul.kocialkowski@bootlin.com