Andre Przywara [Mon, 22 Jul 2019 09:31:10 +0000 (10:31 +0100)]
rpi4: Add initial documentation file
As the Raspberry Pi4 port is now in a usable state, add the build
instructions together with some background information to the
documentation directory.
The port differs quite a bit from the Raspberry Pi 3, so we use a
separate file for that.
Change-Id: I7d9f5967fdf3ec3bfe97d78141f59cbcf03388d4
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Mon, 15 Jul 2019 17:07:51 +0000 (18:07 +0100)]
rpi4: Add stdout-path to device tree
Some device tree users like to find a pointer to the standard serial
console in the device tree, in the "stdout-path" property of the /chosen
node.
Add the location of the Mini UART in that property, so that DT users are
happy, for instance Linux' earlycon detection.
Change-Id: I178e55016e5640de5ab0bc6e061944bd3583ea96
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sun, 21 Jul 2019 00:45:31 +0000 (01:45 +0100)]
rpi4: Add GIC maintenance interrupt to GIC DT node
For being able to use the virtualisation support the GIC offers, we need
to know the interrupt number of the maintenance interrupt. This
information is missing from the official RPi4 device tree.
Use libfdt to add the "interrupts" property to the GIC node, which
allows hypervisors like KVM or Xen to be able to use the GIC's help on
virtualising interrupts.
Change-Id: Iab84f0885a5bf29fb84ca8f385e8a39d27700c75
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Mon, 15 Jul 2019 08:04:27 +0000 (09:04 +0100)]
rpi4: Cleanup memory regions, move pens to first page
Now that we have the SMP pens in the first page of DRAM, we can get rid
of all the fancy RPi3 memory regions that our RPi4 port does not really
need. This avoids using up memory all over the place, restricting ATF
to just run in the first 512KB of DRAM.
Remove the now unused regions. This also moves the SMP pens into our
first memory page (holding the firmware magic), where the original
firmware put them, but where there is also enough space for them.
Since the pens will require code execution privileges, we amend the
memory attributes used for that page to include write and execution
rights.
Change-Id: I131633abeb4a4d7b9057e737b9b0d163b73e47c6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sun, 21 Jul 2019 23:04:40 +0000 (00:04 +0100)]
rpi4: Reserve resident BL31 region from non-secure world
The GPU firmware loads the armstub8.bin (BL31) image at address 0, the
beginning of DRAM. As this holds the resident PSCI code and the SMP
pens, the non-secure world should better know about this, to avoid
accessing memory owned by TF-A. This is particularly criticial as the
Raspberry Pi 4 does not feature a secure memory controller, so
overwriting code is a very real danger.
Use the newly introduced function to add a node into reserved-memory
node, where non-secure world can check for regions to be excluded from
its mappings.
Reserve the first 512KB of memory for now. We can refine this later if
need be.
Change-Id: I00e55e70c5c02615320d79ff35bc32b805d30770
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 11 Jul 2019 00:45:39 +0000 (01:45 +0100)]
rpi4: Amend DTB to advertise PSCI
The device tree provided by the official Raspberry Pi firmware uses
spin tables for SMP bringup.
One of the benefit of having TF-A is that it provides PSCI services, so
let's rewrite the DTB to advertise PSCI instead of spin tables.
This uses the (newly exported) routine from the QEMU platform port.
Change-Id: Ifddcb14041ca253a333f8c2d5e97a42db152470c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 11 Jul 2019 00:42:12 +0000 (01:42 +0100)]
rpi4: Determine BL33 entry point at runtime
Now that we have the armstub magic value in place, the GPU firmware will
write the kernel load address (and DTB address) into our special page,
so we can always easily access the actual location without hardcoding
any addresses into the BL31 image.
Make the compile-time defined PRELOADED_BL33_BASE macro optional, and
read the BL33 entry point from the magic location, if the macro was not
defined. We do the same for the DTB address.
This also splits the currently "common" definition of
plat_get_ns_image_entrypoint() to be separate between RPi3 and RPi4.
Change-Id: I6f26c0adc6fce2df47786b271c490928b4529abb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 10 Jul 2019 17:09:18 +0000 (18:09 +0100)]
rpi4: Accommodate "armstub8.bin" header at the beginning of BL31 image
The Raspberry Pi GPU firmware checks for a magic value at offset 240
(0xf0) of the armstub8.bin image it loads. If that value matches,
it writes the kernel load address and the DTB address into subsequent
memory locations.
We can use these addresses to avoid hardcoding these values into the BL31
image, to make it more flexible and a drop-in replacement for the
official armstub8.bin.
Reserving just 16 bytes at offset 240 of the final image file is not easily
possible, though, as this location is in the middle of the generic BL31
entry point code.
However we can prepend an extra section before the actual BL31 image, to
contain the magic and addresses. This needs to be 4KB, because the
actual BL31 entry point needs to be page aligned.
Use the platform linker script hook that the generic code provides, to
add an almost empty 4KB code block before the entry point code. The very
first word contains a branch instruction to jump over this page, into
the actual entry code.
This also gives us plenty of room for the SMP pens later.
Change-Id: I38caa5e7195fa39cbef8600933a03d86f09263d6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 9 Jul 2019 10:25:57 +0000 (11:25 +0100)]
Add basic support for Raspberry Pi 4
The Raspberry Pi 4 is a single board computer with four Cortex-A72
cores. From a TF-A perspective it is quite similar to the Raspberry Pi
3, although it comes with more memory (up to 4GB) and has a GIC.
This initial port though differs quite a lot from the existing rpi3
platform port, mainly due to taking a much simpler and more robust
approach to loading the non-secure payload:
The GPU firmware of the SoC, which is responsible for initial platform
setup (including DRAM initialisation), already loads the kernel, device
tree and the "armstub" into DRAM. We take advantage of this, by placing
just a BL31 component into the armstub8.bin component, which will be
executed first, in AArch64 EL3.
The non-secure payload can be a kernel or a boot loader (U-Boot or
EDK-2), disguised as the "kernel" image and loaded by the GPU firmware.
So this is just a BL31-only port, which directly drops into EL2
and executes whatever has been loaded as the "kernel" image, handing
over the DTB address in x0.
Change-Id: I636f4d1f661821566ad9e341d69ba36f6bbfb546
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sun, 4 Aug 2019 09:46:21 +0000 (10:46 +0100)]
rpi3: Allow runtime determination of UART base clock rate
At the moment the UART input clock rate is hard coded at compile time.
This works as long as the GPU firmware always sets up the same rate,
which does not seem to be true for the Raspberry Pi 4.
In preparation for being able to change this at runtime, add a base
clock parameter to the console setup function. This is still hardcoded
for the Raspberry Pi 3.
Change-Id: I398bc2f1e9b46f7af9a84cb0b33cbe8e78f2d900
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 19 Sep 2019 09:55:25 +0000 (10:55 +0100)]
FDT helper functions: Respect architecture in PSCI function IDs
PSCI uses different function IDs for CPU_SUSPEND and CPU_ON, depending on
the architecture used (AArch64 or AArch32).
For recent PSCI versions the client will determine the right version,
but for PSCI v0.1 we need to put some ID in the DT node. At the moment
we always add the 64-bit IDs, which is not correct if TF-A is built for
AArch32.
Use the function IDs matching the TF-A build architecture, for the two
IDs where this differs. This only affects legacy OSes using PSCI v0.1.
On the way remove the sys_poweroff and sys_reset properties, which were
never described in the official PSCI DT binding.
Change-Id: If77bc6daec215faeb2dc67112e765aacafd17f33
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 19 Sep 2019 09:45:28 +0000 (10:45 +0100)]
FDT helper functions: Add function documentation
Since we moved some functions that amend a DT blob in memory to common
code, let's add proper function documentation.
This covers the three exported functions in common/fdt_fixup.c.
Change-Id: I67d7d27344e62172c789d308662f78d54903cf57
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Sandrine Bailleux [Wed, 18 Sep 2019 15:22:03 +0000 (15:22 +0000)]
Merge "amlogic: scpi: Add support to retrieve chip ID" into integration
Sandrine Bailleux [Wed, 18 Sep 2019 14:51:13 +0000 (14:51 +0000)]
Merge changes I93ecff4d,I30dd9a95,I8207eea9,Id4197b07,Ib810125b, ... into integration
* changes:
mediatek: mt8183: add MTK MCDI driver
mediatek: mt8183: add MTK SSPM driver
mediatek: mt8183: add MTK SPM driver
mediatek: mt8183: add MTK uart driver for controlling clock gate
mediatek: mt8183: configure MCUSYS DCM
mediatek: mt8173: refactor RTC and PMIC drivers
Sandrine Bailleux [Wed, 18 Sep 2019 14:30:09 +0000 (14:30 +0000)]
Merge changes from topic "db/unsigned_long" into integration
* changes:
Unsigned long should not be used as per coding guidelines
SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64
Sandrine Bailleux [Wed, 18 Sep 2019 14:28:01 +0000 (14:28 +0000)]
Merge changes from topic "qemu_sbsa" into integration
* changes:
qemu: Simplify the image size calculation
qemu: introducing sub-platforms to qemu platform
Radoslaw Biernacki [Thu, 17 May 2018 20:19:35 +0000 (22:19 +0200)]
qemu: Simplify the image size calculation
Patch introduce the macro NS_IMAGE_MAX_SIZE to simplify the image size
calculation. Use of additional parenthesis removes the possibility of
improper calculations due nested macro expansion for subtraction.
In case of platforms with DRAM window over 32bits, patch also removes
potential problems with type casting, as meminfo.image_size is uint32_t
but macro calculations were done in 64bit space.
Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I2d05a2d9dd6000dba6114df53262995cf85af018
Radoslaw Biernacki [Thu, 17 May 2018 20:19:11 +0000 (22:19 +0200)]
qemu: introducing sub-platforms to qemu platform
This commit change the plat/qemu directory structure into:
`-- plat
`-- qemu
|-- common (files shared with all qemu subplatforms)
|-- qemu (original qemu platform)
|-- qemu_sbsa (new sqemu_sbsa platform)
|-- subplat1
`-- subplat2
This opens the possibility of adding new qemu sub-platforms which reuse
existing common platform code. The first platform which will leverage new
structure will be SBSA platform.
Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Id0d8133e1fffc1b574b69aa2770ebc02bb837a9b
Carlo Caione [Mon, 16 Sep 2019 11:13:49 +0000 (12:13 +0100)]
amlogic: scpi: Add support to retrieve chip ID
Both kernel and U-Boot use a SMC call to the secure monitor to get the
chip ID. This call is translated by BL31 to a call to the SCP to
retrieve the ID. Add a new SiP call and the backing SCPI command.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ib128f5645ee92866e7ebbcd550dacd33f573524b
Sandrine Bailleux [Mon, 16 Sep 2019 15:17:11 +0000 (15:17 +0000)]
Merge changes from topic "raspberry-pi-4-support" into integration
* changes:
rpi3: Do prescaler and control setup in C
rpi3: Prepare for supporting a GIC (in RPi4)
rpi3: Make SHARED_RAM optional
rpi3: Rename RPI3_IO_BASE to RPI_IO_BASE
rpi3: Move shared rpi3 files into common directory
Sandrine Bailleux [Mon, 16 Sep 2019 14:21:04 +0000 (14:21 +0000)]
Merge changes from topic "raspberry-pi-4-support" into integration
* changes:
Add fdt_add_reserved_memory() helper function
qemu: Move and generalise FDT PSCI fixup
Sandrine Bailleux [Mon, 16 Sep 2019 12:31:55 +0000 (12:31 +0000)]
Merge changes from topic "raspberry-pi-4-support" into integration
* changes:
rpi3: Move rng driver to drivers
rpi3: Move VC mailbox driver into generic drivers directory
rpi3: Move rpi3_hw.h header file to include/rpi_hw.h
Sandrine Bailleux [Mon, 16 Sep 2019 12:14:18 +0000 (12:14 +0000)]
Merge "rpi3: Add "rpi" platform directory" into integration
kenny liang [Wed, 21 Aug 2019 14:49:49 +0000 (22:49 +0800)]
mediatek: mt8183: add MTK MCDI driver
Add MCDI driver for power saving.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I93ecff4d7581f678be09dd8fb5dfaaccd5f2c22c
kenny liang [Wed, 21 Aug 2019 13:17:49 +0000 (21:17 +0800)]
mediatek: mt8183: add MTK SSPM driver
Add MTK SSPM driver.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I30dd9a95456b8c3c8d18fd22120824eec97634ee
kenny liang [Wed, 21 Aug 2019 12:50:20 +0000 (20:50 +0800)]
mediatek: mt8183: add MTK SPM driver
Add MTK SPM driver for suspend/resume scenario.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I8207eea95914da9e63c62f3afc8329f3ccd9a22c
kenny liang [Tue, 20 Aug 2019 14:27:44 +0000 (22:27 +0800)]
mediatek: mt8183: add MTK uart driver for controlling clock gate
Add uart clock gate contol for suspend/resume scenario.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: Id4197b0720630ec6c74aec206a9b206511bf515a
kenny liang [Wed, 21 Aug 2019 13:16:29 +0000 (21:16 +0800)]
mediatek: mt8183: configure MCUSYS DCM
Configure MCUSYS DCM.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: Ib810125b514cbcc43c770377bc71a29a05a19320
kenny liang [Thu, 2 May 2019 13:06:05 +0000 (21:06 +0800)]
mediatek: mt8173: refactor RTC and PMIC drivers
Refactor RTC and PMIC drivers.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I74fca536cd61e00c962f080f1ba3759287682ecf
Deepika Bhavnani [Tue, 3 Sep 2019 18:51:09 +0000 (21:51 +0300)]
Unsigned long should not be used as per coding guidelines
We should either change them to `unsigned int` or `unsigned long long`
when the size of the variable is the same in AArch64 and AArch32 or
to `u_register_t` if it is supposed to be 32 bit wide in AArch32
and 64 bit wide in AArch64.
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I80e2a6edb33248ee88be395829abbd4c36c89abe
Deepika Bhavnani [Tue, 3 Sep 2019 18:08:51 +0000 (21:08 +0300)]
SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64
AArch64 System register SCTLR_EL1[31:0] is architecturally mapped
to AArch32 System register SCTLR[31:0]
AArch64 System register ACTLR_EL1[31:0] is architecturally mapped
to AArch32 System register ACTLR[31:0].
`u_register_t` should be used when it's important to store the
contents of a register in its native size
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I0055422f8cc0454405e011f53c1c4ddcaceb5779
Andre Przywara [Mon, 15 Jul 2019 08:02:15 +0000 (09:02 +0100)]
rpi3: Do prescaler and control setup in C
To initialise the arch timer configuration and some clock prescaler, we
need to do two MMIO access *once*, early during boot.
As tempting as it may sound, plat_reset_handler() is not the right place
to do this, as it will be called on every CPU coming up, both for
secondary cores as well as during warmboots. So this access will be done
multiple times, and even during a rich OS' runtime. Whether doing so anyway
is actually harmful is hard to say, but we should definitely avoid this if
possible.
Move the initialisation of these registers to C code in
bl1_early_platform_setup(), where it will still be executed early enough
(before enabling the console), but only once during the whole boot
process.
Change-Id: I081c41a5476d424411411488ff8f633e87d3bcc5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Mon, 15 Jul 2019 08:00:23 +0000 (09:00 +0100)]
Add fdt_add_reserved_memory() helper function
If a firmware component like TF-A reserves special memory regions for
its own or secure payload services, it should announce the location and
size of those regions to the non-secure world. This will avoid
disappointment when some rich OS tries to acccess this memory, which
will likely end in a crash.
The traditional way of advertising reserved memory using device tree is
using the special memreserve feature of the device tree blob (DTB).
However by definition those regions mentioned there do not prevent the
rich OS to map this memory, which may lead to speculative accesses to
this memory and hence spurious bus errors.
A safer way of carving out memory is to use the /reserved-memory node as
part of the normal DT structure. Besides being easier to setup, this
also defines an explicit "no-map" property to signify the secure-only
nature of certain memory regions, which avoids the rich OS to
accidentally step on it.
Add a helper function to allow platform ports to easily add a region.
Change-Id: I2b92676cf48fd3bdacda05b5c6b1c7952ebed68c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 9 Jul 2019 13:29:24 +0000 (14:29 +0100)]
rpi3: Move rng driver to drivers
To allow sharing the driver between the RPi3 and RPi4, move the random
number generator driver into the generic driver directory.
Change-Id: Iae94d7cb22c6bce3af9bff709d76d4caf87b14d1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 9 Jul 2019 10:18:59 +0000 (11:18 +0100)]
rpi3: Add "rpi" platform directory
With the incoming support for the Raspberry Pi 4 boards, one directory
to serve both versions will not end up well.
Create an additional layer by inserting a "rpi" directory betweeen /plat
and rpi3, so that we can more easily share or separate files between the
two later.
Change-Id: I75adbb054fe7902f34db0fd5e579a55612dd8a5f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Mon, 15 Jul 2019 22:04:26 +0000 (23:04 +0100)]
rpi3: Prepare for supporting a GIC (in RPi4)
As the PSCI "power" management functions for the Raspberry Pi 3 port
will be shared with the upcoming RPi4 support, we need to prepare them
for dealing with the GIC interrupt controller.
Splitting this code just for those simple calls to the generic GIC
routines does not seem worthwhile, so just use a #define the protect the
GIC code from being included by the existing RPi3 code.
Change-Id: Iaca6b0214563852b28ad4a088ec45348ae8be40d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 10 Jul 2019 16:27:17 +0000 (17:27 +0100)]
qemu: Move and generalise FDT PSCI fixup
The QEMU platform port scans its device tree to advertise PSCI as the
CPU enable method. It does this by scanning *every* node in the DT and
check whether its compatible string starts with "arm,cortex-a". Then it
sets the enable-method to PSCI, if it doesn't already have one.
Other platforms might want to use this functionality as well, so let's
move it out of the QEMU platform directory and make it more robust by
fixing some shortcomings:
- A compatible string starting with a certain prefix is not a good way
to find the CPU nodes. For instance a "arm,cortex-a72-pmu" node will
match as well and is in turn favoured with an enable-method.
- If the DT already has an enable-method, we won't change this to PSCI.
Those two issues will for instance fail on the Raspberry Pi 4 DT.
To fix those problems, we adjust the scanning method:
The DT spec says that all CPU nodes are subnodes of the mandatory
/cpus node, which is a subnode of the root node. Also each CPU node has
to have a device_type = "cpu" property. So we find the /cpus node, then
scan for a subnode with the proper device_type, forcing the
enable-method to "psci".
We have to restart this search after a property has been patched, as the
node offsets might have changed meanwhile.
This allows this routine to be reused for the Raspberry Pi 4 later.
Change-Id: I00cae16cc923d9f8bb96a9b2a2933b9a79b06139
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 9 Jul 2019 12:54:56 +0000 (13:54 +0100)]
rpi3: Move VC mailbox driver into generic drivers directory
To allow sharing the driver between the RPi3 and RPi4, move the mailbox
driver into the generic driver directory.
Change-Id: I463e49acf82b02bf004f3d56482b7791f3020bc0
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Mon, 15 Jul 2019 07:58:23 +0000 (08:58 +0100)]
rpi3: Make SHARED_RAM optional
The existing Raspberry Pi 3 port sports a number of memory regions,
which are used for several purposes. The upcoming RPi4 port will not use
all of those, so make the SHARED_RAM region optional, by only mapping it
if it has actually been defined. This helps to get a cleaner RPi4 port.
Change-Id: Id69677b7fb6ed48d9f238854b610896785db8cab
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 9 Jul 2019 10:44:14 +0000 (11:44 +0100)]
rpi3: Move rpi3_hw.h header file to include/rpi_hw.h
With the advent of Raspberry Pi 4 support, we need to separate some
board specific headers between the RPi3 and RPi4.
Rename and move the "rpi3_hw.h" header, so that .c files just include
rpi_hw.h, and automatically get the correct version.
Change-Id: I03b39063028d2bee1429bffccde71dddfe2dcde8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 9 Jul 2019 14:59:26 +0000 (15:59 +0100)]
rpi3: Rename RPI3_IO_BASE to RPI_IO_BASE
The location of the MMIO window is different between a Raspberry Pi 3
and 4: the former has it just below 1GB, the latter below 4GB.
The relative location of the peripherals is mostly compatible though.
To allow sharing code between the two models, let's rename the symbol
used for the MMIO base to the more generic RPI_IO_BASE name.
Change-Id: I3c2762fb30fd56cca743348e79d72ef8c60ddb03
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 9 Jul 2019 13:32:11 +0000 (14:32 +0100)]
rpi3: Move shared rpi3 files into common directory
To be able to share code more easily between the existing Raspberry Pi 3
and the upcoming Raspberry Pi 4 platform, move some code which is not
board specific into a "common" directory.
Change-Id: I9211ab2d754b040128fac13c2f0a30a5cc8c7f2c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Soby Mathew [Fri, 13 Sep 2019 15:22:23 +0000 (15:22 +0000)]
Merge "Refactor ARMv8.3 Pointer Authentication support code" into integration
Soby Mathew [Fri, 13 Sep 2019 14:19:37 +0000 (14:19 +0000)]
Merge "Add Linux DTS files for 32 bit threaded FVPs" into integration
Soby Mathew [Fri, 13 Sep 2019 14:18:36 +0000 (14:18 +0000)]
Merge "Modify FVP makefile for cores that support both AArch64/32" into integration
Soby Mathew [Fri, 13 Sep 2019 14:17:26 +0000 (14:17 +0000)]
Merge "amlogic: console: Move console driver to common directory" into integration
Alexei Fedorov [Fri, 13 Sep 2019 13:11:59 +0000 (14:11 +0100)]
Refactor ARMv8.3 Pointer Authentication support code
This patch provides the following features and makes modifications
listed below:
- Individual APIAKey key generation for each CPU.
- New key generation on every BL31 warm boot and TSP CPU On event.
- Per-CPU storage of APIAKey added in percpu_data[]
of cpu_data structure.
- `plat_init_apiakey()` function replaced with `plat_init_apkey()`
which returns 128-bit value and uses Generic timer physical counter
value to increase the randomness of the generated key.
The new function can be used for generation of all ARMv8.3-PAuth keys
- ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`.
- New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions
generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively;
pauth_disable_el1()` and `pauth_disable_el3()` functions disable
PAuth for EL1 and EL3 respectively;
`pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from
cpu-data structure.
- Combined `save_gp_pauth_registers()` function replaces calls to
`save_gp_registers()` and `pauth_context_save()`;
`restore_gp_pauth_registers()` replaces `pauth_context_restore()`
and `restore_gp_registers()` calls.
- `restore_gp_registers_eret()` function removed with corresponding
code placed in `el3_exit()`.
- Fixed the issue when `pauth_t pauth_ctx` structure allocated space
for 12 uint64_t PAuth registers instead of 10 by removal of macro
CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h`
and assigning its value to CTX_PAUTH_REGS_END.
- Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions
in `msr spsel` instruction instead of hard-coded values.
- Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI.
Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Soby Mathew [Fri, 13 Sep 2019 12:09:21 +0000 (12:09 +0000)]
Merge "stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver" into integration
Soby Mathew [Fri, 13 Sep 2019 12:02:11 +0000 (12:02 +0000)]
Merge "Assert if power level value greater then PSCI_INVALID_PWR_LVL" into integration
Soby Mathew [Fri, 13 Sep 2019 12:00:59 +0000 (12:00 +0000)]
Merge changes from topic "jc/rsa-pkcs" into integration
* changes:
Remove RSA PKCS#1 v1.5 support from cert_tool
Add documentation for new KEY_SIZE option
Add cert_create tool support for RSA key sizes
Support larger RSA key sizes when using MBEDTLS
Soby Mathew [Fri, 13 Sep 2019 11:51:49 +0000 (11:51 +0000)]
Merge changes I08cf22df,I535ee414,Ie84cfc96,I8c35ce4e,If7649764, ... into integration
* changes:
mediatek: mt8183: Support coreboot configuration
mediatek: mt8183: support system reset
mediatek: mt8183: pass platform parameters
mediatek: mt8183: add GPIO driver
mediatek: mt8183: support system off
mediatek: mt8183: support CPU hotplug
mediatek: mt8183: refine GIC driver
Soby Mathew [Fri, 13 Sep 2019 11:35:56 +0000 (11:35 +0000)]
Merge "Unify type of "cpu_idx" across PSCI module." into integration
Sandrine Bailleux [Fri, 13 Sep 2019 07:03:01 +0000 (07:03 +0000)]
Merge "mediatek: mt8173: apply MULTI_CONSOLE framework" into integration
Deepika Bhavnani [Mon, 26 Aug 2019 21:32:24 +0000 (00:32 +0300)]
Unify type of "cpu_idx" across PSCI module.
cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places. This change is to unify the
cpu_idx as `unsigned int` as underlying API;s `plat_my_core_pos`
returns `unsigned int`
It was discovered via coverity issue CID 354715
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I4f0adb0c596ff1177210c5fe803bff853f2e54ce
Carlo Caione [Thu, 5 Sep 2019 11:27:39 +0000 (12:27 +0100)]
amlogic: console: Move console driver to common directory
The code managing the console is the same for all the platforms
currently supported. Since it is unlikely to change in the future move
the code to an external file in the common directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I6df555ea82d483b4f08a4a1e2cb0a7488fbaa015
kenny liang [Thu, 2 May 2019 12:33:58 +0000 (20:33 +0800)]
mediatek: mt8173: apply MULTI_CONSOLE framework
- Switch uart driver from Mediatek 8250 to TI 16550
- Enable MULTI_CONSOLE
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: Ie3948d9e64d05d29a1f69592792e277b680c4ed4
Soby Mathew [Thu, 12 Sep 2019 16:14:36 +0000 (16:14 +0000)]
Merge "Add python configuration for editorconfig" into integration
Soby Mathew [Thu, 12 Sep 2019 16:10:29 +0000 (16:10 +0000)]
Merge "Tegra: memctrl_v2: fix "overflow before widen" coverity issue" into integration
Soby Mathew [Thu, 12 Sep 2019 16:09:56 +0000 (16:09 +0000)]
Merge "Invalidate dcache build option for bl2 entry at EL3" into integration
Justin Chadwell [Mon, 9 Sep 2019 14:24:31 +0000 (15:24 +0100)]
Remove RSA PKCS#1 v1.5 support from cert_tool
Support for PKCS#1 v1.5 was deprecated in SHA
1001202 and fully removed
in SHA
fe199e3, however, cert_tool is still able to generate
certificates in that form. This patch fully removes the ability for
cert_tool to generate these certificates.
Additionally, this patch also fixes a bug where the issuing certificate
was a RSA and the issued certificate was EcDSA. In this case, the issued
certificate would be signed using PKCS#1 v1.5 instead of RSAPSS per
PKCS#1 v2.1, preventing TF-A from verifying the image signatures. Now
that PKCS#1 v1.5 support is removed, all certificates that are signed
with RSA now use the more modern padding scheme.
Change-Id: Id87d7d915be594a1876a73080528d968e65c4e9a
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Justin Chadwell [Mon, 29 Jul 2019 16:18:21 +0000 (17:18 +0100)]
Add documentation for new KEY_SIZE option
This patch adds documentation for the new KEY_SIZE build option that is
exposed by cert_create, and instructions on how to use it.
Change-Id: I09b9b052bfdeeaca837e0f0026e2b01144f2472c
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Justin Chadwell [Mon, 29 Jul 2019 16:13:45 +0000 (17:13 +0100)]
Add cert_create tool support for RSA key sizes
cert_tool is now able to accept a command line option for specifying the
key size. It now supports the following options: 1024, 2048 (default),
3072 and 4096. This is also modifiable by TFA using the build flag
KEY_SIZE.
Change-Id: Ifadecf84ade3763249ee8cc7123a8178f606f0e5
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Justin Chadwell [Mon, 29 Jul 2019 16:13:10 +0000 (17:13 +0100)]
Support larger RSA key sizes when using MBEDTLS
Previously, TF-A could not support large RSA key sizes as the
configuration options passed to MBEDTLS prevented storing and performing
calculations with the larger, higher-precision numbers required. With
these changes to the arguments passed to MBEDTLS, TF-A now supports
using 3072 (3K) and 4096 (4K) keys in certificates.
Change-Id: Ib73a6773145d2faa25c28d04f9a42e86f2fd555f
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Hadi Asyrafi [Tue, 20 Aug 2019 07:33:27 +0000 (15:33 +0800)]
Invalidate dcache build option for bl2 entry at EL3
Some of the platform (ie. Agilex) make use of CCU IPs which will only be
initialized during bl2_el3_early_platform_setup. Any operation to the
cache beforehand will crash the platform. Hence, this will provide an
option to skip the data cache invalidation upon bl2 entry at EL3
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06
Soby Mathew [Thu, 12 Sep 2019 12:34:27 +0000 (12:34 +0000)]
Merge "libc: fix sparse warning for __assert()" into integration
Soby Mathew [Thu, 12 Sep 2019 12:33:20 +0000 (12:33 +0000)]
Merge "doc: Updated user guide with new Mbed TLS version number" into integration
Soby Mathew [Thu, 12 Sep 2019 12:33:02 +0000 (12:33 +0000)]
Merge "intel: agilex: Fix psci power domain off" into integration
Soby Mathew [Thu, 12 Sep 2019 12:31:22 +0000 (12:31 +0000)]
Merge changes from topic "jc/mte_enable" into integration
* changes:
Add documentation for CTX_INCLUDE_MTE_REGS
Enable MTE support in both secure and non-secure worlds
Soby Mathew [Thu, 12 Sep 2019 12:29:46 +0000 (12:29 +0000)]
Merge "plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()" into integration
Soby Mathew [Thu, 12 Sep 2019 11:38:42 +0000 (11:38 +0000)]
Merge "Zeus: apply the MSR SSBS instruction" into integration
Soby Mathew [Thu, 12 Sep 2019 11:14:21 +0000 (11:14 +0000)]
Merge "Add UBSAN support and handlers" into integration
Soby Mathew [Thu, 12 Sep 2019 11:11:34 +0000 (11:11 +0000)]
Merge changes I072c0f61,I798401f4,I9648ef55,I7225d9fa,Ife682288, ... into integration
* changes:
rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N
rcar_gen3: drivers: qos: update QoS setting
rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers
rcar_gen3: drivers: ddr_b: Fix line-over-80s
rcar_gen3: drivers: ddr_b: Further checkpatch cleanups
rcar_gen3: drivers: ddr_b: Clean up camel case
rcar_get3: drivers: ddr_b: Basic checkpatch fixes
rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B
rcar_get3: drivers: ddr: Clean up common code
Soby Mathew [Thu, 12 Sep 2019 10:58:43 +0000 (10:58 +0000)]
Merge changes from topic "amlogic-refactoring" into integration
* changes:
amlogic: Fix includes order
amlogic: Fix header guards
amlogic: Fix prefixes in the SoC specific files
amlogic: Fix prefixes in the PM code
amlogic: Fix prefixes in the SCPI related code
amlogic: Fix prefixes in the MHU code
amlogic: Fix prefixes in the SIP/SVC code
amlogic: Fix prefixes in the thermal driver
amlogic: Fix prefixes in the private header file
amlogic: Fix prefixes in the efuse driver
amlogic: Fix prefixes in the platform macros file
amlogic: Fix prefixes in the helpers file
amlogic: Rework Makefiles
amlogic: Move the SIP SVC code to common directory
amlogic: Move topology file to common directory
amlogic: Move thermal code to common directory
amlogic: Move MHU code to common directory
amlogic: Move efuse code to common directory
amlogic: Move platform macros assembly file to common directory
amlogic: Introduce unified private header file
amlogic: Move SCPI code to common directory
amlogic: Move the SHA256 DMA driver to common directory
amlogic: Move assembly helpers to common directory
amlogic: Introduce directory parameters in the makefiles
meson: Rename platform directory to amlogic
Hadi Asyrafi [Thu, 12 Sep 2019 07:14:01 +0000 (15:14 +0800)]
intel: agilex: Fix psci power domain off
Disable gic cpu interface for powered down cpu. This patch also removes
core reset during power off as core reset will be done during power on
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673
Carlo Caione [Tue, 3 Sep 2019 11:38:58 +0000 (12:38 +0100)]
amlogic: Fix includes order
As part of the code refactoring fix the order of the include files
across all the source files.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ice72f687cc26ee881a9051168149467688100cfb
Carlo Caione [Wed, 28 Aug 2019 09:14:46 +0000 (10:14 +0100)]
amlogic: Fix header guards
Make the header guards more generic and contextually remove the
GXBB_BL31_PLAT_PARAM_VAL value that is unused on the GXL platform.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I842fa2e084e71280ae17b39c67877e844821a171
Soby Mathew [Wed, 11 Sep 2019 16:21:29 +0000 (16:21 +0000)]
Merge "mbedtls: use #include <...> instead of "..."" into integration
John Tsichritzis [Tue, 13 Aug 2019 09:11:41 +0000 (10:11 +0100)]
Modify FVP makefile for cores that support both AArch64/32
Some cores support only AArch64 from EL1 and above, e.g. A76, N1 etc. If
TF-A is compiled with CTX_INCLUDE_AARCH32_REGS=0 so as to properly
handle those cores, only the AArch64 cores' assembly is included in the
TF-A binary. In other words, for FVP, TF-A assumes that AArch64 only
cores will never exist in the same cluster with cores that also support
AArch32.
However, A55 and A75 can be used as AArch64 only cores, despite
supporting AArch32, too. This patch enables A55 and A75 to exist in
clusters together with AArch64 cores.
Change-Id: I58750ad6c3d76ce77eb354784c2a42f2c179031d
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
John Tsichritzis [Tue, 13 Aug 2019 09:28:25 +0000 (10:28 +0100)]
Zeus: apply the MSR SSBS instruction
Zeus supports the SSBS mechanism and also the new MSR instruction to
immediately apply the mitigation. Hence, the new instruction is utilised
in the Zeus-specific reset function.
Change-Id: I962747c28afe85a15207a0eba4146f9a115b27e7
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Justin Chadwell [Tue, 20 Aug 2019 10:01:52 +0000 (11:01 +0100)]
Add UBSAN support and handlers
This patch adds support for the Undefined Behaviour sanitizer. There are
two types of support offered - minimalistic trapping support which
essentially immediately crashes on undefined behaviour and full support
with full debug messages.
The full support relies on ubsan.c which has been adapted from code used
by OPTEE.
Change-Id: I417c810f4fc43dcb56db6a6a555bfd0b38440727
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Masahiro Yamada [Fri, 26 Jul 2019 11:21:39 +0000 (20:21 +0900)]
libc: fix sparse warning for __assert()
Sparse warns this:
lib/libc/assert.c:29:6: error: symbol '__assert' redeclared with different type (originally declared at include/lib/libc/assert.h:36) - different modifiers
Add __dead2 to match the header declaration and C definition.
I also changed '__dead2 void' to 'void __dead2' for the consistency
with other parts.
Change-Id: Iefa4f0e787c24fa7e7e499d2e7baf54d4deb49ef
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Jolly Shah [Tue, 27 Aug 2019 18:23:08 +0000 (11:23 -0700)]
plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()
Common ipi_table needs to be initialized before using any
IPI command (i.e send/receive). Move zynqmp ipi config table
initialization from sip_svc_setup() to zynqmp_config_setup().
Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Yann Gautier [Wed, 4 Sep 2019 09:55:10 +0000 (11:55 +0200)]
stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver
The STM32 console driver was pre-pending '\r' before '\n'.
It is now managed by the framework with the flag:
CONSOLE_FLAG_TRANSLATE_CRLF.
Remove the code in driver, and add the flag for STM32MP1.
Change-Id: I5d0d5d5c4abee0b7dc11c2f8707b1b5cf10149ab
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Soby Mathew [Tue, 10 Sep 2019 14:32:59 +0000 (14:32 +0000)]
Merge changes from topic "yg/stm32mp1_wdg_updates" into integration
* changes:
mmc: stm32_sdmmc2: correctly manage block size
mmc: stm32_sdmmc2: manage max-frequency property from DT
stm32mp1: move check_header() to common code
stm32mp1: keep console during runtime
stm32mp1: sp_min: initialize MMU and cache earlier
stm32mp1: add support for LpDDR3
stm32mp1: use a common function to check spinlock is available
clk: stm32mp: enable RTCAPB clock for dual-core chips
stm32mp1: check if the SoC is single core
stm32mp1: print information about board
stm32mp1: print information about SoC
stm32mp1: add watchdog support
Justin Chadwell [Tue, 27 Aug 2019 08:43:47 +0000 (09:43 +0100)]
Add python configuration for editorconfig
As it currently is, python files are formatted using the general rules
in .editorconfig - this means that 8-character hard tabs are used, which
is not the recommended behaviour according to the PEP-8 standard. This
patch correct this, and additionally limits the line length to 79
characters as required by the standard.
Change-Id: I3b5c0aff12034c4184d4555aab36490cdb3885da
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Hung-Te Lin [Thu, 2 May 2019 13:42:41 +0000 (21:42 +0800)]
mediatek: mt8183: Support coreboot configuration
When built for coreboot, we want to enable coreboot library to have
better integration. For example, serial console should be initialized by
coreboot_serial instead of hard-coded values.
Most coreboot configuration will enable memory console, which needs
larger XLAT_TABLES so MAX_XLAT_TABLES is increased; and to support that,
TZRAM_SIZE also need to be enlarged.
Change-Id: I08cf22df2fa26e48284e323d22ad8ce73a6ea803
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
kenny liang [Fri, 3 May 2019 09:02:46 +0000 (17:02 +0800)]
mediatek: mt8183: support system reset
Implement system reset handler.
Change-Id: I535ee414616dde8d2b59dec5a723a540a3a1341d
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
kenny liang [Fri, 3 May 2019 08:59:07 +0000 (16:59 +0800)]
mediatek: mt8183: pass platform parameters
Add plat parameter structs to support BL2 to pass
variable-length, variable-type parameters to BL31.
The parameters are structured as a link list.
During BL31 setup time, we traverse the list to process
each parameter.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: Ie84cfc9606656fb1d2780a68cadf27e09afa6628
kenny liang [Thu, 2 May 2019 12:24:50 +0000 (20:24 +0800)]
mediatek: mt8183: add GPIO driver
Add GPIO driver.
Change-Id: I8c35ce4ea247f3726081b0bbb95f0930c2b82517
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
kenny liang [Thu, 2 May 2019 12:02:05 +0000 (20:02 +0800)]
mediatek: mt8183: support system off
- Add PMIC driver
- Add RTC drvier
- Refactor PMIC and RTC to mediatek/common
- Implement system off handler
Change-Id: If76497646ace1b78bc9a5fa0110b652fe512281a
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
kenny liang [Thu, 2 May 2019 11:29:25 +0000 (19:29 +0800)]
mediatek: mt8183: support CPU hotplug
- Add DCM driver
- Add SPMC driver
- Implement core and cluster power on/off handlers
Change-Id: I902002f8ea6f98fd73bf259188162b10d3939c72
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
kenny liang [Tue, 25 Jun 2019 07:33:48 +0000 (15:33 +0800)]
mediatek: mt8183: refine GIC driver
Refine MTK GIC driver.
Remove unused codes.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I39e05ce7aa3c257e237fbc8e661cdde65cbcec7c
Deepika Bhavnani [Fri, 16 Aug 2019 22:10:02 +0000 (01:10 +0300)]
Assert if power level value greater then PSCI_INVALID_PWR_LVL
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I4a496d5a8e7a9a127cd6224c968539eb74932fca
Justin Chadwell [Thu, 18 Jul 2019 15:16:32 +0000 (16:16 +0100)]
Add documentation for CTX_INCLUDE_MTE_REGS
A new build flag, CTX_INCLUDE_MTE_REGS, has been added; this patch adds
documentation for it in the User Guide along with instructions of what
different values mean.
Change-Id: I430a9c6ced06b1b6be317edbeff4f5530e30f63a
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Justin Chadwell [Thu, 18 Jul 2019 13:25:33 +0000 (14:25 +0100)]
Enable MTE support in both secure and non-secure worlds
This patch adds support for the new Memory Tagging Extension arriving in
ARMv8.5. MTE support is now enabled by default on systems that support
at EL0. To enable it at ELx for both the non-secure and the secure
world, the compiler flag CTX_INCLUDE_MTE_REGS includes register saving
and restoring when necessary in order to prevent register leakage
between the worlds.
Change-Id: I2d4ea993d6b11654ea0d4757d00ca20d23acf36c
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Imre Kis [Thu, 8 Aug 2019 17:06:12 +0000 (19:06 +0200)]
Add Linux DTS files for 32 bit threaded FVPs
RevC models have the MT bit set and the affinities shifted in the MPIDR
register. To make the Linux able to boot all CPUs it needs a modified
DTS file containing the shifted affinity values.
Beside these values the DTS files should be the same so the common part
was moved into a new file which is included in the DTS files with
shifted and non-shifted affinities.
The same setup already exists for 64 bit systems.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: I90f7b9c8d8a24c9b3f97232441dbe0a29aa8976d
Varun Wadekar [Thu, 5 Sep 2019 15:17:02 +0000 (08:17 -0700)]
Tegra: memctrl_v2: fix "overflow before widen" coverity issue
This patch fixes a coding error, where the size of the protected memory area
was truncated due to an incorrect typecast.
This defect was found by coverity and reported as CID 336781.
Change-Id: I41878b0a9a5e5cd78ef3393fdc7b9ea7f7403ed3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Carlo Caione [Wed, 28 Aug 2019 14:32:22 +0000 (15:32 +0100)]
amlogic: Fix prefixes in the SoC specific files
Remove the GXBB prefix where needed and add SoC specific prefixes for
GXBB/GXL.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ic3eb3a77ca2d9c779a9dee5cee786e9c16ecdb27
Carlo Caione [Wed, 28 Aug 2019 14:19:56 +0000 (15:19 +0100)]
amlogic: Fix prefixes in the PM code
Remove the GXBB prefix from the code in the common directory and add
SoC-specific prefixes in the SoC specific code.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ic983ef70b0ef23f95088dd8df488d8c42c3bc030
Carlo Caione [Wed, 28 Aug 2019 09:08:24 +0000 (10:08 +0100)]
amlogic: Fix prefixes in the SCPI related code
Add a new aml_* prefix to the SCPI related function calls.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I697812ac1c0df28cbb639a1dc3e838f1107fb739