Alex Deucher [Tue, 25 Jul 2017 03:18:44 +0000 (23:18 -0400)]
drm/amdgpu/gmc9: disable legacy vga features in gmc init
Needs to be done when the MC is set up.
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 25 Jul 2017 03:05:20 +0000 (23:05 -0400)]
drm/amdgpu/gmc8: disable legacy vga features in gmc init
Needs to be done when the MC is set up.
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 25 Jul 2017 02:58:36 +0000 (22:58 -0400)]
drm/amdgpu/gmc7: disable legacy vga features in gmc init
Needs to be done when the MC is set up.
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 25 Jul 2017 02:52:12 +0000 (22:52 -0400)]
drm/amdgpu/gmc6: disable legacy vga features in gmc init (v2)
Needs to be done when the MC is set up.
v2: make consistent with other asics
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Egbert Eich [Tue, 18 Jul 2017 15:20:53 +0000 (17:20 +0200)]
drm/radeon: Set depth on low mem to 16 bpp instead of 8 bpp
The radeon driver reduces the framebuffer resolution to 8bpp if a
device with less than 32MB VRAM is found. This causes the framebuffer
to run in 8 bit paletted mode. For a text console this is not an
issue as 256 different colors is more than one gets on a VGA text
console. However this leads to a poor 8bit pseudo-color visual when
running X on fbdev, too, which is quite ugly.
In this patch, we try to give some moderate compromise: limit the
framebuffer bpp to 8 only when VRAM is 8MB or less, and use 16 bpp
otherwise for 32MB or less VRAM.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Egbert Eich <eich@suse.de>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 20 Jul 2017 07:32:31 +0000 (15:32 +0800)]
drm/amdgpu: fix the incorrect scratch reg number on gfx v6
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 20 Jul 2017 07:31:21 +0000 (15:31 +0800)]
drm/amdgpu: fix the incorrect scratch reg number on gfx v7
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 20 Jul 2017 07:03:56 +0000 (15:03 +0800)]
drm/amdgpu: fix the incorrect scratch reg number on gfx v8
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Mon, 10 Jul 2017 02:17:08 +0000 (10:17 +0800)]
drm/amdgpu: fix the incorrect scratch reg number on gfx v9
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 21 Jul 2017 05:27:07 +0000 (13:27 +0800)]
drm/amd/powerplay: add support for 3DP 4K@120Hz on vega10.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 25 Jul 2017 20:35:38 +0000 (16:35 -0400)]
drm/amdgpu: enable huge page handling in the VM v5
The hardware can use huge pages to map 2MB of address space with only one PDE.
v2: few cleanups and rebased
v3: skip PT updates if we are using the PDE
v4: rebased, added support for CPU based updates
v5: fix CPU based updates once more
v6: fix ndw estimation
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-and-tested-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 23 May 2017 16:35:22 +0000 (18:35 +0200)]
drm/amdgpu: increase fragmentation size for Vega10 v2
The fragment bits work differently for Vega10 compared to previous generations.
Increase the fragment size to 2MB for now to better handle that.
v2: handle the hardware setup as well
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-and-tested-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Wed, 12 Jul 2017 04:36:47 +0000 (12:36 +0800)]
drm/amdgpu: ttm_bind only when user needs gpu_addr in bo pin
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Fri, 26 May 2017 09:29:51 +0000 (17:29 +0800)]
drm/amdgpu: correct clock info for SRIOV
Currently, get clock info from default clk of pm if dpm is disable.
Buf SRIOV doesn't support dpm and pm, can't get anything from pm.
Only get clock info only from default clk of amdgpu for SRIOV.
And driver get pm default clk also from amdgpu default clk and never
be changed by others. So use amdgpu default clk value for SRIOV
and non-dpm cases.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Emily Deng [Thu, 20 Jul 2017 04:14:45 +0000 (12:14 +0800)]
drm/amdgpu/gmc8: SRIOV need to program fb location
SRIOV won't do vbios post in guest OS, and the mmMC_VM_FB_LOCATION
is pf and vf copy, so still need to program fb location for SRIOV.
v2: No need to stop mc, and update gmc_v8_0_vram_gtt_location as well.
v3: New line after the stack variables
BUG: SWDEV-126629
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Junwei Zhang [Wed, 19 Jul 2017 00:23:24 +0000 (08:23 +0800)]
drm/amdgpu: disable firmware loading for psp v10
Now asd firmware is not ready for psp v10, will enable it when it's available
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 19 Jun 2017 14:19:41 +0000 (10:19 -0400)]
drm/amdgpu:fix gfx fence allocate size
1, for sriov, we need 8dw for the gfx fence due to CP
behaviour
2, cleanup wrong logic in wptr/rptr wb alloc and free
Change-Id: Ifbfed17a4621dae57244942ffac7de1743de0294
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Mon, 3 Jul 2017 18:18:27 +0000 (14:18 -0400)]
drm/amdgpu: Implement ttm_bo_driver.access_memory callback v2
Allows gdb to access contents of user mode mapped VRAM BOs.
v2: return error for non-VRAM pools
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Thu, 13 Jul 2017 21:01:16 +0000 (17:01 -0400)]
drm/ttm: Implement vm_operations_struct.access v2
Allows gdb to access contents of user mode mapped BOs. System memory
is handled by TTM using kmap. Other memory pools require a new driver
callback in ttm_bo_driver.
v2:
* kmap only one page at a time
* swap in BO if needed
* make driver callback more generic to handle private memory pools
* document callback return value
* WARN_ON -> WARN_ON_ONCE
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Mon, 17 Jul 2017 21:18:33 +0000 (17:18 -0400)]
drm/amd/powerplay: fix AVFS voltage offset for Vega10
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhang, Jerry [Fri, 14 Jul 2017 10:20:17 +0000 (18:20 +0800)]
drm/amdgpu: read reg in each iterator of psp_wait_for loop
v2: fix the SOS loading failure for PSP v3.1
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Acked-by: Huang Rui <ray.huang@amd.com> (v1)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicolai Hähnle [Fri, 14 Jul 2017 11:00:04 +0000 (13:00 +0200)]
drm/amdgpu/gfx9: simplify and fix GRBM index selection
Copy the approach taken by gfx8, which simplifies the code, and set the
instance index properly. The latter is required for debugging, e.g. for
reading wave status by UMR.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Junwei Zhang [Fri, 14 Jul 2017 10:37:44 +0000 (18:37 +0800)]
drm/amdgpu: add ring_destroy for psp v10
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Junwei Zhang [Fri, 14 Jul 2017 10:34:48 +0000 (18:34 +0800)]
drm/amdgpu: add ring_create function for psp v10
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Junwei Zhang [Fri, 14 Jul 2017 10:31:18 +0000 (18:31 +0800)]
drm/amdgpu: add init microcode function for psp v10
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Junwei Zhang [Fri, 14 Jul 2017 10:27:57 +0000 (18:27 +0800)]
drm/amdgpu: remove unncessary code in psp v10 ring init func
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Thu, 20 Jul 2017 04:02:08 +0000 (00:02 -0400)]
drm/amdgpu: Fix blocking in RCU critical section(v2)
In RCU read-side critical sections, blocking or sleeping is prohibited.
v2: Unlock RCU for the code path where result==NULL. (David Zhou)
Update subject
Tested-by and reported by: Dave Airlie <airlied@redhat.com>
[ 141.965723] =============================
[ 141.965724] WARNING: suspicious RCU usage
[ 141.965726] 4.12.0-rc7 #221 Not tainted
[ 141.965727] -----------------------------
[ 141.965728] /home/airlied/devel/kernel/linux-2.6/include/linux/rcupdate.h:531
Illegal context switch in RCU read-side critical section!
[ 141.965730]
other info that might help us debug this:
[ 141.965731]
rcu_scheduler_active = 2, debug_locks = 0
[ 141.965732] 1 lock held by amdgpu_cs:0/1332:
[ 141.965733] #0: (rcu_read_lock){......}, at: [<
ffffffffa01a0d07>]
amdgpu_bo_list_get+0x0/0x109 [amdgpu]
[ 141.965774]
stack backtrace:
[ 141.965776] CPU: 6 PID: 1332 Comm: amdgpu_cs:0 Not tainted 4.12.0-rc7 #221
[ 141.965777] Hardware name: To be filled by O.E.M. To be filled by
O.E.M./M5A97 R2.0, BIOS 2603 06/26/2015
[ 141.965778] Call Trace:
[ 141.965782] dump_stack+0x68/0x92
[ 141.965785] lockdep_rcu_suspicious+0xf7/0x100
[ 141.965788] ___might_sleep+0x56/0x1fc
[ 141.965790] __might_sleep+0x68/0x6f
[ 141.965793] __mutex_lock+0x4e/0x7b5
[ 141.965817] ? amdgpu_bo_list_get+0xa4/0x109 [amdgpu]
[ 141.965820] ? lock_acquire+0x125/0x1b9
[ 141.965844] ? amdgpu_bo_list_set+0x464/0x464 [amdgpu]
[ 141.965846] mutex_lock_nested+0x16/0x18
[ 141.965848] ? mutex_lock_nested+0x16/0x18
[ 141.965872] amdgpu_bo_list_get+0xa4/0x109 [amdgpu]
[ 141.965895] amdgpu_cs_ioctl+0x4a0/0x17dd [amdgpu]
[ 141.965898] ? radix_tree_node_alloc.constprop.11+0x77/0xab
[ 141.965916] drm_ioctl+0x264/0x393 [drm]
[ 141.965939] ? amdgpu_cs_find_mapping+0x83/0x83 [amdgpu]
[ 141.965942] ? trace_hardirqs_on_caller+0x16a/0x186
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 12 Jul 2017 11:28:03 +0000 (19:28 +0800)]
drm/amd/powerplay: add profile mode for vega10.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 13 Jul 2017 10:21:00 +0000 (12:21 +0200)]
drm/amdgpu: fix amdgpu_bo_gpu_accessible()
The test was relaxed a bit to much.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-and-Tested-by: Roger He <Hongbo.He@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 12 Jul 2017 08:01:48 +0000 (10:01 +0200)]
drm/amdgpu: map VM BOs for CPU based updates only once
No need to try to map them every time.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 11 Jul 2017 15:25:49 +0000 (17:25 +0200)]
drm/amdgpu: make sure BOs are always kunmapped
When a BO is moved or destroyed it shouldn't be kmapped any more.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 11 Jul 2017 15:23:29 +0000 (17:23 +0200)]
drm/amdgpu: flush the HDP only once for CPU based VM updates
No need to do this after every single update.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 11 Jul 2017 15:15:37 +0000 (17:15 +0200)]
drm/amdgpu: trace setting VM page tables with the CPU as well
Handy for debugging.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 13 Jul 2017 19:37:11 +0000 (15:37 -0400)]
drm/amdgpu: remove VM shadow WARN_ONs
Printing a warning into the logs that we will certainly run into a BUG() is
completely nonsense, the BUG() is more than noisy enough.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 11 Jul 2017 15:13:00 +0000 (17:13 +0200)]
drm/amdgpu: fix amdgpu_vm_bo_wait
We need to wait with the correct owner on unmap operations or otherwise can run
into VM faults.
Also always wait for the page directory since this is where the reservation
object comes from. So rename the function to amdgpu_vm_wait_pd instead as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 11 Jul 2017 14:59:21 +0000 (16:59 +0200)]
drm/amdgpu: fix VM flush for CPU based updates
We don't have any update fence in that case, so the need
for flushing isn't detected automatically.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 11 Jul 2017 15:11:41 +0000 (11:11 -0400)]
drm/amdgpu/gfx: keep all compute queues on the same pipe
Spreading them causes performance regressions using compute
queues on Polaris 11.
Cc: Jim Qu <jim.qu@amd.com>
Acked-by: Jim Qu <Jim.Qu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jim Qu [Wed, 12 Jul 2017 07:52:26 +0000 (15:52 +0800)]
drm/amd/amdgpu: fix si_enable_smc_cac() failed issue
Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dan Carpenter [Tue, 11 Jul 2017 19:53:29 +0000 (22:53 +0300)]
drm/amdgpu: Off by one sanity checks
This is just future proofing code, not something that can be triggered
in real life. We're testing to make sure we don't shift wrap when we
do "1ull << i" so "i" has to be in the 0-63 range. If it's 64 then we
have gone too far.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 12 Jul 2017 13:18:07 +0000 (09:18 -0400)]
drm/amdgpu: implement si_read_bios_from_rom
This allows us to read the vbios image directly from ROM.
This is already implemented for other asics, but was not
yet available for SI.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 11 Jul 2017 22:59:24 +0000 (18:59 -0400)]
drm/amdgpu/soc15: drop dead function
Maybe a leftover from bringup?
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 10 Jul 2017 14:43:10 +0000 (10:43 -0400)]
drm/amdgpu: call atomfirmware get_clock_info for atomfirmware systems
Rather than the legacy atombios version.
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 10 Jul 2017 14:39:09 +0000 (10:39 -0400)]
drm/amdgpu: add get_clock_info for atomfirmware
The information has moved to different tables, notably
smu_info for core refclk and umc_info for mem refclk.
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Wed, 26 Apr 2017 19:51:57 +0000 (14:51 -0500)]
drm/amdgpu: Send no-retry XNACK for all fault types
A subset of VM fault types currently send retry XNACK to the client.
This causes a storm of interrupts from the VM to the host.
Until the storm is throttled by other means send no-retry XNACK for
all fault types instead. No change in behavior to the client which
will stall indefinitely with the current configuration in any case.
Improves system stability under GC or MMHUB faults.
Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: John Bridgman <John.Bridgman@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yong Zhao [Mon, 9 Nov 2015 22:21:45 +0000 (17:21 -0500)]
drm/amdgpu: Correctly establish the suspend/resume hook for amdkfd
Signed-off-by: Yong Zhao <yong.zhao@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Fri, 15 Jul 2016 22:37:05 +0000 (18:37 -0400)]
drm/amdgpu: Make SDMA phase quantum configurable
Set a configurable SDMA phase quantum when enabling SDMA context
switching. The default value significantly reduces SDMA latency
in page table updates when user-mode SDMA queues have concurrent
activity, compared to the initial HW setting.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Andres Rodriguez <andres.rodriguez@amd.com>
Reviewed-by: Shaoyun Liu <shaoyun.liu@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Wed, 15 Jun 2016 20:33:15 +0000 (16:33 -0400)]
drm/amdgpu: Enable SDMA context switching for CIK
Enable SDMA context switching on CIK (copied from sdma_v3_0.c).
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
shaoyunl [Fri, 4 Dec 2015 20:01:22 +0000 (15:01 -0500)]
drm/amdgpu: Enable SDMA_CNTL.ATC_L1_ENABLE for SDMA on CZ
For GFX context, the ATC bit in SDMA*_GFX_VIRTUAL_ADDRESS can be cleared
to perform in VM mode. For RLC context, to support ATC mode , ATC bit in
SDMA*_RLC*_VIRTUAL_ADDRESS should be set. SDMA_CNTL.ATC_L1_ENABLE bit is
global setting that enables the L1-L2 translation for ATC address.
Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Tue, 4 Jul 2017 08:16:42 +0000 (17:16 +0900)]
drm/amdgpu: Try evicting from CPU visible to invisible VRAM first
This gives BOs which haven't been accessed by the CPU since they were
moved to visible VRAM another chance to stay in VRAM when another BO
needs to go to visible VRAM.
This should allow BOs to stay in VRAM longer in some cases.
v2:
* Only do this for BOs which don't have the
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED flag set.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Brooks [Wed, 28 Jun 2017 02:33:21 +0000 (22:33 -0400)]
drm/amdgpu: Don't force BOs into visible VRAM for page faults
There is no need for page faults to force BOs into visible VRAM if it's
full, and the time it takes to do so is great enough to cause noticeable
stuttering. Add GTT as a possible placement so that if visible VRAM is
full, page faults move BOs to GTT instead of evicting other BOs from VRAM.
Suggested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: John Brooks <john@fastquake.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Brooks [Fri, 30 Jun 2017 15:31:08 +0000 (11:31 -0400)]
drm/amdgpu: Set/clear CPU_ACCESS flag on page fault and move to VRAM
When a BO is moved to VRAM, clear AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED.
This allows it to potentially later move to invisible VRAM if the CPU
does not access it again.
Setting the CPU_ACCESS flag in amdgpu_bo_fault_reserve_notify() also means
that we can remove the loop to restrict lpfn to the end of visible VRAM,
because amdgpu_ttm_placement_init() will do it for us.
v3 [Michel Dänzer]
* Use AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED instead of a new flag
(Christian König)
* Clear flag in amdgpu_bo_move instead of amdgpu_move_ram_vram
(Christian)
* Explicitly mention amdgpu_bo_fault_reserve_notify in amdgpu_bo_move
* Also clear flag in amdgpu_bo_create_restricted
Suggested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: John Brooks <john@fastquake.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Brooks [Wed, 28 Jun 2017 02:33:18 +0000 (22:33 -0400)]
drm/amdgpu: Throttle visible VRAM moves separately
The BO move throttling code is designed to allow VRAM to fill quickly if it
is relatively empty. However, this does not take into account situations
where the visible VRAM is smaller than total VRAM, and total VRAM may not
be close to full but the visible VRAM segment is under pressure. In such
situations, visible VRAM would experience unrestricted swapping and
performance would drop.
Add a separate counter specifically for moves involving visible VRAM, and
check it before moving BOs there.
v2: Only perform calculations for separate counter if visible VRAM is
smaller than total VRAM. (Michel Dänzer)
v3: [Michel Dänzer]
* Use BO's location rather than the AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
flag to determine whether to account a move for visible VRAM in most
cases.
* Use a single
if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
block in amdgpu_cs_get_threshold_for_moves.
Fixes: 95844d20ae02 (drm/amdgpu: throttle buffer migrations at CS using a fixed MBps limit (v2))
Signed-off-by: John Brooks <john@fastquake.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Brooks [Wed, 28 Jun 2017 02:33:17 +0000 (22:33 -0400)]
drm/amdgpu: Add vis_vramlimit module parameter
Allow specifying a limit on visible VRAM via a module parameter. This is
helpful for testing performance under visible VRAM pressure.
v2: Add cast to 64-bit (Christian König)
Signed-off-by: John Brooks <john@fastquake.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 7 Jul 2017 11:44:05 +0000 (13:44 +0200)]
drm/amdgpu: change gartsize default to 256MB
Limit the default GART size and save a lot of VRAM.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 7 Jul 2017 11:17:45 +0000 (13:17 +0200)]
drm/amdgpu: add new gttsize module parameter v2
This allows setting the gtt size independent of the gart size.
v2: fix copy and paste typo
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 7 Jul 2017 11:16:37 +0000 (13:16 +0200)]
drm/amdgpu: limit the GTT manager address space
We should only cover the GART size with the GTT manager.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 7 Jul 2017 09:56:59 +0000 (11:56 +0200)]
drm/amdgpu: consistent name all GART related parts
Rename symbols from gtt_ to gart_ as appropriate.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 6 Jul 2017 20:26:05 +0000 (22:26 +0200)]
drm/amdgpu: remove gtt_base_align handling
Not used any more.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 6 Jul 2017 20:02:41 +0000 (22:02 +0200)]
drm/amdgpu: move GART struct and function into amdgpu_gart.h v2
No functional change, just cleanup.
v2: rebased, keep gart name.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 30 Jun 2017 21:26:47 +0000 (17:26 -0400)]
drm/amdgpu: check scratch registers to see if we need post (v2)
Rather than checking the CONGIG_MEMSIZE register as that may
not be reliable on some APUs.
v2: The scratch register is only used on CIK+
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 6 Jul 2017 17:43:55 +0000 (13:43 -0400)]
drm/amdgpu/soc15: init nbio registers for vega10
Call nbio init registers on hw_init to set up any
nbio registers that need initialization at hw init time.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 6 Jul 2017 17:38:09 +0000 (13:38 -0400)]
drm/amdgpu: add nbio 6.1 register init function
Used for nbio registers that need to be initialized. Currently
only used for a golden setting that got missed on some boards.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 5 Jul 2017 07:33:00 +0000 (15:33 +0800)]
drm/amd/powerplay: added didt support for vega10
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 4 Jul 2017 07:37:09 +0000 (15:37 +0800)]
drm/amd/powerplay: added grbm_idx_mutex lock/unlock to cgs v2
- v2: rename param 'en' as 'lock'
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 4 Jul 2017 01:24:34 +0000 (09:24 +0800)]
drm/amd/powerplay: added support for new se_cac_idx APIs to cgs
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 4 Jul 2017 01:23:01 +0000 (09:23 +0800)]
drm/amd/powerplay: added soc15 support for new se_cac_idx APIs
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 4 Jul 2017 01:21:50 +0000 (09:21 +0800)]
drm/amd/powerplay: added new se_cac_idx r/w APIs v2
- v2: added missing spinlock init
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 3 Jul 2017 14:37:44 +0000 (22:37 +0800)]
drm/amd/powerplay: added index gc cac read/write apis for vega10
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 30 Jun 2017 12:37:02 +0000 (14:37 +0200)]
drm/amdgpu: use TTM values instead of MC values for the info queries
Use the TTM values instead of the hardware config here.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 30 Jun 2017 10:20:45 +0000 (12:20 +0200)]
drm/amdgpu: remove maximum BO size limitation v2
We can finally remove this now.
v2: remove now unused max_size variable as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 30 Jun 2017 10:19:42 +0000 (12:19 +0200)]
drm/amdgpu: stop mapping BOs to GTT
No need to map BOs to GTT on eviction and intermediate transfers any more.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 30 Jun 2017 09:05:54 +0000 (11:05 +0200)]
drm/amdgpu: use the GTT windows for BO moves v2
This way we don't need to map the full BO at a time any more.
v2: use fixed windows for src/dst
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 29 Jun 2017 15:24:26 +0000 (17:24 +0200)]
drm/amdgpu: add amdgpu_gart_map function v2
This allows us to write the mapped PTEs into
an IB instead of the table directly.
v2: fix build with debugfs enabled, remove unused assignment
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 28 Jun 2017 10:18:54 +0000 (12:18 +0200)]
drm/amdgpu: reserve the first 2x512 pages of GART
We want to use them as remap address space.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Thu, 6 Jul 2017 14:15:46 +0000 (10:15 -0400)]
drm/amdgpu: make arrays pctl0_data and pctl1_data static
The arrays pctl0_data and pctl1_data do not need to be in global scope,
so them both static.
Cleans up sparse warnings:
symbol 'pctl0_data' was not declared. Should it be static?
symbol 'pctl1_data' was not declared. Should it be static?
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 5 Jul 2017 19:37:35 +0000 (15:37 -0400)]
drm/amdgpu/gmc9: get vram width from atom for Raven
Get it from the system info table.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 5 Jul 2017 19:26:48 +0000 (15:26 -0400)]
drm/amdgpu/atomfirmware: implement vram_width for APUs
Implement support using the new atomfirmware system info table.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 5 Jul 2017 19:17:00 +0000 (15:17 -0400)]
drm/amdgpu/atom: fix atom_fw check
Not all vbios images seem to set the version appropriately.
Switch the check based on asic type instead.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Wed, 5 Jul 2017 22:02:04 +0000 (18:02 -0400)]
drm/amdgpu: Free resources of bo_list when idr_alloc fails
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König<christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 3 Jul 2017 09:50:45 +0000 (17:50 +0800)]
drm/amd/powerplay: add avfs check for old asics on Vi.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 5 Jul 2017 10:12:46 +0000 (18:12 +0800)]
drm/amd/powerplay: move VI common AVFS code to smu7_smumgr.c
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 15 Jun 2017 06:02:51 +0000 (14:02 +0800)]
drm/amd/powerplay: refine avfs enable code on fiji.
1. simplify avfs state switch.
2. delete save/restore VFT table functions as not support
by fiji.
3. implement thermal_avfs_enable funciton.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 15 Jun 2017 05:58:41 +0000 (13:58 +0800)]
drm/amd/powerplay: fix avfs state update error on polaris.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 6 Jul 2017 01:36:27 +0000 (09:36 +0800)]
drm/amd/powerplay: fixed wrong data type declaration for ppfeaturemask
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 4 Jul 2017 08:14:06 +0000 (16:14 +0800)]
drm/amdgpu: set firmware loading type as direct by default for raven
In previous case, driver can't enable psp via the kernel parameter for raven.
We should open this path and set it as direct by default till psp firmware
loading is workable.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 11 Jun 2017 10:57:08 +0000 (18:57 +0800)]
drm/amdgpu: make psp cmd buffer as a reserve memory
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 11 Jun 2017 10:28:00 +0000 (18:28 +0800)]
drm/amdgpu: fix missed asd bo free when hw_fini
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 2 Jun 2017 02:42:28 +0000 (10:42 +0800)]
drm/amdgpu: remove superfluous check
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shaoyun Liu [Wed, 5 Jul 2017 14:56:14 +0000 (10:56 -0400)]
drm/amdgpu: NO KIQ usage on nbio hdp flush routine
nbio hdp flush routine are called within atomic context.
Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL register
since this register has its own VF copy
Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shaoyun Liu [Wed, 5 Jul 2017 14:53:55 +0000 (10:53 -0400)]
drm/amdgpu: Add WREG32_SOC15_NO_KIQ macro define
Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 6 Jun 2017 09:25:13 +0000 (17:25 +0800)]
drm/amdgpu:fix world switch hang
for SR-IOV, we must keep the pipeline-sync in the protection
of COND_EXEC, otherwise the command consumed by CPG is not
consistent when world switch triggerd, e.g.:
world switch hit and the IB frame is skipped so the fence
won't signal, thus CP will jump to the next DMAframe's pipeline-sync
command, and it will make CP hang foever.
after pipelin-sync moved into COND_EXEC the consistency can be
guaranteed
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 24 Jun 2017 10:13:26 +0000 (18:13 +0800)]
drm/amd/powerplay: enable ACG feature on vega10.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 24 Jun 2017 10:11:53 +0000 (18:11 +0800)]
drm/amd/powerplay: add acg support in pptable for vega10
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 24 Jun 2017 10:27:07 +0000 (18:27 +0800)]
drm/amd/powerplay: export ACG related smu message for vega10
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 24 Jun 2017 08:45:58 +0000 (16:45 +0800)]
drm/amd/powerplay: add avfs profiling_info_v4_2 support on Vega10.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 23 Jun 2017 07:08:15 +0000 (15:08 +0800)]
drm/amdgpu: add ACG SMU firmware for other vega10 variants
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 23 Jun 2017 07:06:37 +0000 (15:06 +0800)]
drm/amdgpu: drop SMU_DRIVER_IF_VERSION check for some vega10 variants
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ken Wang [Tue, 4 Jul 2017 05:11:52 +0000 (13:11 +0800)]
drm/amdgpu: add workaround for S3 issues on some vega10 boards
Certain MC registers need a delay after writing them to properly
update in the init sequence.
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 30 Jun 2017 21:21:42 +0000 (17:21 -0400)]
drm/amdgpu/atombios: add function for whether we need asic_init
Check the atom scratch registers to see if asic_init is complete
or not.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 30 Jun 2017 21:08:45 +0000 (17:08 -0400)]
drm/amdgpu: unify some atombios/atomfirmware scratch reg functions
Now that we use a pointer to the scratch reg start offset,
most of the functions were duplicated.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>