openwrt/staging/blogic.git
5 years agodrm/amd/display: update calculated bounding box logic for NV
Jun Lei [Thu, 9 May 2019 19:32:27 +0000 (15:32 -0400)]
drm/amd/display: update calculated bounding box logic for NV

[why]
Current calculation of bounding box will cause DML to increase voltage
state due to DPP or DISPCLK, this is unnecessary since from DML perspective
we can max DPP/DISP can be supported at DPM0.  This is because
increasing voltage for DPP/DISP is done separately via actual minimum values
of DISP and DPP CLK

[how]
For each calculated state, DPP, DISP, PHY, and DSC clk should always be set to
maximum.  FCLK, SOCCLK, and DCFCLK should be based of UCLK.

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: disable PSR/ABM before destroy DMCU struct
Paul Hsieh [Tue, 7 May 2019 09:58:58 +0000 (17:58 +0800)]
drm/amd/display: disable PSR/ABM before destroy DMCU struct

[Why]
1. DMCU is not running on some platform but driver still send ABM
   command. It may cause assert due to DMCU is not alive.
2. To make sure PSR disable when driver disable

[How]
1. Add dmcu_is_running in ABM struct, driver can check this flag to
   determine driver should send ABM command or not.
2. Send PSR disable command when destroy PSR

Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Ensure DRR triggers in BP
Eryk Brol [Tue, 23 Apr 2019 15:53:52 +0000 (11:53 -0400)]
drm/amd/display: Ensure DRR triggers in BP

[Why]
In the previous implementation DRR event sometimes came
in during FP2 region which is a keep-out zone. This
would cause the frame not to latch until the next frame
which resulted in heavy flicker. To fix this we need
to make sure that it triggers in the BP.

[How]
1. Remove DRR programming during flip
2. Setup manual trigger for DRR event and trigger it
after surface programming is complete

Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display/dc: fix azalia workaround sw implementation bug
hersen wu [Sat, 1 Jun 2019 22:23:38 +0000 (18:23 -0400)]
drm/amd/display/dc: fix azalia workaround sw implementation bug

caller of pp_nv_set_pme_wa_enable pass incorrect pp_smu:
dc->res_pool->pp_smu. it should be dc->res_pool->pp_smu->nv_funcs.pp_smu.
with incorrect input, pp->dm = NULL. This causes system crash.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Program VTG params after programming Global Sync for DCN2
Joshua Aberback [Mon, 29 Apr 2019 21:21:19 +0000 (17:21 -0400)]
drm/amd/display: Program VTG params after programming Global Sync for DCN2

[Why]
VTG has a parameter FP2, which is defined as:
    if VSTARTUP is before VSYNC:
        FP2 = number of lines in between VSTARTUP and VSYNC
    else
        FP2 = 0
Currently, FP2 is only programmed during "program_timing". However, the
position of VSTARTUP is affected by the prefetching requirements on all pipes,
so the position might change when we do memory request control on another pipe, so we need
to make sure that FP2 stays up-to-date whenever we adjust VSTARTUP.

[How]
 - refactor VTG_CONTROL programming into a new function "set_vtg_params"
 - call it after calling "program_global_sync"
   - make sure it's called after because it relies on the cached dlg params

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Jun Lei <Jun.Lei@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DSC support for Navi (v2)
Harry Wentland [Mon, 25 Feb 2019 18:26:34 +0000 (13:26 -0500)]
drm/amd/display: Add DSC support for Navi (v2)

Add support for DCN2 DSC (Display Stream Compression)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |                     ^
        v                     |
    +--------+            +--------+
    |  DPP   |            |  DWB   |
    +--------+            +--------+
        |
        v                      ^
    +--------+                 |
    |  MPC   |                 |
    +--------+                 |
        |                      |
        v                      |
    +-------+      +-------+   |
    |  OPP  | <--> |  DSC  |   |
    +-------+      +-------+   |
        |                      |
        v                      |
    +--------+                /
    |  OPTC  |  --------------
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

v2: rebase (Alex)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Enable DC support for Navi10
Harry Wentland [Tue, 26 Feb 2019 21:25:27 +0000 (16:25 -0500)]
drm/amdgpu: Enable DC support for Navi10

Enable the IP for navi10.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)
Harry Wentland [Fri, 22 Feb 2019 21:52:52 +0000 (16:52 -0500)]
drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)

Enable DCN2 support in DM (Display Manager).

v2: fix spurious raven change (Alex)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: update dcn2 dc_plane_cap
Alex Deucher [Mon, 22 Apr 2019 21:49:04 +0000 (16:49 -0500)]
drm/amd/display: update dcn2 dc_plane_cap

To deal with rebasing the code.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: updates for dcn20_update_bandwidth
Alex Deucher [Mon, 22 Apr 2019 21:41:54 +0000 (16:41 -0500)]
drm/amd/display: updates for dcn20_update_bandwidth

Pass extra parameter to validate_bandwidth() callback.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: add fast_validate parameter to dcn20_validate_bandwidth
Alex Deucher [Mon, 22 Apr 2019 21:38:24 +0000 (16:38 -0500)]
drm/amd/display: add fast_validate parameter to dcn20_validate_bandwidth

To deal with changes from rebasing.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: hook navi10 pplib functions
hersen wu [Thu, 23 May 2019 17:23:25 +0000 (13:23 -0400)]
drm/amd/display: hook navi10 pplib functions

during bring up time, before window dc-ppplib interface
design, linux dc use raven dc-pplib interface.
now nvai10 dc-pplib-smu interface is changed and verified
under window, navi10 need its specific dc-pplib-smu
interface. todo: hook set_hard_min_uclk_by_freq,
get_maximum_sustainable_clocks

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add interface to get uclk dpm table
hersen wu [Tue, 21 May 2019 19:02:23 +0000 (15:02 -0400)]
drm/amd/powerplay: add interface to get uclk dpm table

dc needs get uclk dpm table for bandwidth calculation

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powrplay: add interface for dc to get max clock values
hersen wu [Tue, 21 May 2019 17:07:57 +0000 (13:07 -0400)]
drm/amd/powrplay: add interface for dc to get max clock values

dc (display component) needs maximum clock values of uclock,
socclk, dcefclk, to calculate display bandwidth.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DC core changes for DCN2
Harry Wentland [Fri, 22 Feb 2019 21:52:34 +0000 (16:52 -0500)]
drm/amd/display: Add DC core changes for DCN2

Core DC changes for DCN2.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 HW Sequencer and Resource
Harry Wentland [Fri, 22 Feb 2019 21:52:08 +0000 (16:52 -0500)]
drm/amd/display: Add DCN2 HW Sequencer and Resource

Add DCN2 resource definition and HW Sequencer changes.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 VMID
Harry Wentland [Fri, 22 Feb 2019 21:38:28 +0000 (16:38 -0500)]
drm/amd/display: Add DCN2 VMID

Add support to program DCN2 VMID (Virtual Memory Support)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 IPP
Harry Wentland [Fri, 22 Feb 2019 21:37:36 +0000 (16:37 -0500)]
drm/amd/display: Add DCN2 IPP

Add support to program DCN2 cursor (IPP)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 DWB
Harry Wentland [Fri, 22 Feb 2019 20:54:43 +0000 (15:54 -0500)]
drm/amd/display: Add DCN2 DWB

Add support to program the DCN2 DWB (Display Writeback)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |                     ^
        v                     |
    +--------+            +--------+
    |  DPP   |            |  DWB   |
    +--------+            +--------+
        |
        v                      ^
    +--------+                 |
    |  MPC   |                 |
    +--------+                 |
        |                      |
        v                      |
    +-------+                  |
    |  OPP  |                  |
    +-------+                  |
        |                      |
        v                      |
    +--------+                /
    |  OPTC  |  --------------
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 MMHUBBUB
Harry Wentland [Fri, 22 Feb 2019 20:53:49 +0000 (15:53 -0500)]
drm/amd/display: Add DCN2 MMHUBBUB

Add support to program the DCN2 MMHUBBUB (Multimedia HUB interface)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 HUBP and HUBBUB
Harry Wentland [Tue, 7 May 2019 19:58:48 +0000 (14:58 -0500)]
drm/amd/display: Add DCN2 HUBP and HUBBUB

Add support to program the DCN2 HUBP (Display to data fabric interface
pipe) and HUBBUB (DCN memory HUB interface)

HW Blocks:

 +--------++------+
 | HUBBUB || HUBP |
 +--------++------+
        |
        v
    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 DPP
Harry Wentland [Fri, 22 Feb 2019 20:50:50 +0000 (15:50 -0500)]
drm/amd/display: Add DCN2 DPP

Add support to program the DCN2 DPP (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 MPC
Harry Wentland [Fri, 22 Feb 2019 15:49:04 +0000 (10:49 -0500)]
drm/amd/display: Add DCN2 MPC

Add support to program the DCN2 MPC (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 OPP
Harry Wentland [Fri, 22 Feb 2019 20:45:23 +0000 (15:45 -0500)]
drm/amd/display: Add DCN2 OPP

Add support to program the DCN2 OPP (Output Plane Processing)

HW Blocks:

    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 OPTC
Harry Wentland [Fri, 22 Feb 2019 15:19:04 +0000 (10:19 -0500)]
drm/amd/display: Add DCN2 OPTC

Add support for programming the DCN2 OPTC (Output Timing Controller)

HW Blocks:

    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 clk mgr
Harry Wentland [Tue, 7 May 2019 19:57:07 +0000 (14:57 -0500)]
drm/amd/display: Add DCN2 clk mgr

Adds support for handling of clocking relevant to the DCN2 block,
including programming of the DCCG (Display Controller Clock Generator)
block:

HW Blocks:

    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 DIO
Harry Wentland [Tue, 7 May 2019 19:50:05 +0000 (14:50 -0500)]
drm/amd/display: Add DCN2 DIO

Add support for the DIO (Display IO)  block of DCN2, which entails our
stream and link encoders.

HW Blocks:

    +--------+
    |  DIO   |
    +--------+

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 changes to DML
Harry Wentland [Fri, 22 Feb 2019 14:59:43 +0000 (09:59 -0500)]
drm/amd/display: Add DCN2 changes to DML

Update DML (Display Mode Lib) to support DCN2

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 IRQ handling
Harry Wentland [Fri, 22 Feb 2019 14:59:12 +0000 (09:59 -0500)]
drm/amd/display: Add DCN2 IRQ handling

Add support to program DCN2 IRQ handling

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 BIOS parsing
Harry Wentland [Fri, 22 Feb 2019 14:58:49 +0000 (09:58 -0500)]
drm/amd/display: Add DCN2 BIOS parsing

Handle BIOS parsing for DCN2

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add GPIO support for DCN2
Harry Wentland [Fri, 22 Feb 2019 14:45:07 +0000 (09:45 -0500)]
drm/amd/display: Add GPIO support for DCN2

Adding support to program GPIO HW block of DCN2

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: add AUX and I2C for DCN2
Harry Wentland [Tue, 7 May 2019 19:47:35 +0000 (14:47 -0500)]
drm/amd/display: add AUX and I2C for DCN2

Adding support to program DCN2 AUX and I2C HW.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Add DCN2 and NV ASIC ID
Harry Wentland [Fri, 22 Feb 2019 15:11:16 +0000 (10:11 -0500)]
drm/amd/display: Add DCN2 and NV ASIC ID

DCN2.0 (Display Core Next) is the display block in Navi10.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: use fixed-width data type for soc bounding box struct
Xiaojie Yuan [Tue, 19 Mar 2019 06:27:04 +0000 (14:27 +0800)]
drm/amd/display: use fixed-width data type for soc bounding box struct

since it's firmware.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: Split gpu_info_soc_bounding_box out from amdgpu_ucode.h
Leo Li [Wed, 3 Apr 2019 21:20:49 +0000 (17:20 -0400)]
drm/amdgpu: Split gpu_info_soc_bounding_box out from amdgpu_ucode.h

DC needs to include the soc bounding box when initializing HW resources.

Including amdgpu_ucode.h directly will cause warnings, since amdgpu.h is
required to define amdgpu_device. The solution here is to split the
bounding box structs into a different header, then include it in both
amdgpu_ucode.h, and relevant DC HW resource files.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/display: Read soc_bounding_box from gpu_info (v2)
Harry Wentland [Tue, 7 May 2019 19:34:21 +0000 (14:34 -0500)]
drm/amd/display: Read soc_bounding_box from gpu_info (v2)

[WHY]
We don't want to expose sensitive ASIC information before ASIC release.

[HOW]
Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it
at driver load.

v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: notify smu with active display count
hersen wu [Tue, 21 May 2019 20:03:28 +0000 (16:03 -0400)]
drm/amd/powerplay: notify smu with active display count

when dc update clocks via smu, smu needs to know how many
displays active. this interface is for dc notify number
of active displays to smu.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: allow dc request uclk change
hersen wu [Wed, 22 May 2019 14:57:40 +0000 (10:57 -0400)]
drm/amd/powerplay: allow dc request uclk change

when dc set mode or color format in frame buffer
change, it may request clock changes, like dispclk,
dcfclk, uclk. after smu get clock requests, smu
will make decision.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: initialize THM & CLK IP registers base address
Hawking Zhang [Sat, 15 Jun 2019 15:14:30 +0000 (23:14 +0800)]
drm/amdgpu: initialize THM & CLK IP registers base address

was missed before.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: fix PA_SC_FIFO_SIZE for Navi10 (v2)
Marek Olšák [Tue, 28 May 2019 22:13:00 +0000 (18:13 -0400)]
drm/amdgpu: fix PA_SC_FIFO_SIZE for Navi10 (v2)

Proper size is 0.

v2: squash in whitespace fixes (Ernst Sjöstrand)

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: remove unsupport function set_thermal_fan_table for navi10
Kevin Wang [Thu, 30 May 2019 11:22:28 +0000 (19:22 +0800)]
drm/amd/powerplay: remove unsupport function set_thermal_fan_table for navi10

the PPSMC_MSG_SetFanTemperatureTarget is not support on navi10

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: enable BACO feature as WAR
Jack Xiao [Sat, 1 Jun 2019 02:35:12 +0000 (10:35 +0800)]
drm/amd/powerplay: enable BACO feature as WAR

It would hit SMU fw bug without BACO enablement when audio
driver put audio device to D3 state. Before the bug in SMU fw
get fixed, enable BACO feature as WAR.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: use pp_feature_mask to control uclk(mclk) dpm enabled
Kevin Wang [Thu, 30 May 2019 02:28:11 +0000 (10:28 +0800)]
drm/amd/powerplay: use pp_feature_mask to control uclk(mclk) dpm enabled

the uclk dpm feature is not work well on all navi10 asic,
use pp feature mask module parameter to control it.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: add new navi10 DIDs
tiancyin [Thu, 30 May 2019 03:04:11 +0000 (11:04 +0800)]
drm/amdgpu: add new navi10 DIDs

Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add ppt interface version log
tiancyin [Mon, 20 May 2019 10:21:59 +0000 (18:21 +0800)]
drm/amd/powerplay: add ppt interface version log

Include the interface version as well.

Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/gfx10: update to latest golden setting
Alex Deucher [Tue, 4 Jun 2019 19:37:05 +0000 (14:37 -0500)]
drm/amdgpu/gfx10: update to latest golden setting

Fix UTCL1_CGTT_CLK_CTRL

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/powerplay/vega20: use correct table index
Alex Deucher [Thu, 30 May 2019 05:51:44 +0000 (00:51 -0500)]
drm/amdgpu/powerplay/vega20: use correct table index

Use the SMU_* variant so we look up the correct index.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/VCN: enable indirect DPG SRAM mode
Leo Liu [Mon, 27 May 2019 14:49:19 +0000 (10:49 -0400)]
drm/amdgpu/VCN: enable indirect DPG SRAM mode

This is default mode for VCN2.x now

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/VCN: implement indirect DPG SRAM mode
Leo Liu [Mon, 27 May 2019 14:46:25 +0000 (10:46 -0400)]
drm/amdgpu/VCN: implement indirect DPG SRAM mode

SRAM will be programmed by PSP

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/VCN: add buffer for indirect SRAM usage
Leo Liu [Fri, 24 May 2019 18:07:41 +0000 (14:07 -0400)]
drm/amdgpu/VCN: add buffer for indirect SRAM usage

This will be used later for indirect SRAM mode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: disable fw dstate when gfxoff is enabled
Jack Xiao [Tue, 28 May 2019 13:47:05 +0000 (21:47 +0800)]
drm/amd/powerplay: disable fw dstate when gfxoff is enabled

SMU FW has bug that it would cause hung when both fw dstate and
gfxoff are enabled at the same time.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: update smu11_driver_if_navi10.h
Jack Xiao [Tue, 28 May 2019 07:43:02 +0000 (15:43 +0800)]
drm/amd/powerplay: update smu11_driver_if_navi10.h

update the smu11_driver_if_navi10.h since navi10 smu fw
update to 42.23

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/psp: add new psp interface for vcn updating sram
Jack Xiao [Tue, 14 May 2019 03:31:04 +0000 (11:31 +0800)]
drm/amdgpu/psp: add new psp interface for vcn updating sram

PSP leverages the existing fw loading function for vcn updating sram.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/psp: convert ucode id to psp ucode id
Jack Xiao [Tue, 14 May 2019 03:53:57 +0000 (11:53 +0800)]
drm/amdgpu/psp: convert ucode id to psp ucode id

Convert ucode id to the corresponding psp ucode id.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: add corresponding vcn ram ucode id
Jack Xiao [Tue, 14 May 2019 03:36:33 +0000 (11:36 +0800)]
drm/amdgpu: add corresponding vcn ram ucode id

Add VCN RAM ucode id in corresponding to psp ucode id.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/psp: add new VCN RAM ucode id to psp
Jack Xiao [Tue, 14 May 2019 03:26:52 +0000 (11:26 +0800)]
drm/amdgpu/psp: add new VCN RAM ucode id to psp

PSP supports to program vcn sram by ucode loading interface.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: enable VCN2.0 DPG mode
Leo Liu [Wed, 15 May 2019 17:58:20 +0000 (13:58 -0400)]
drm/amdgpu: enable VCN2.0 DPG mode

It will be the default for VCN2.x family

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/VCN2.0: add DPG pause mode
Leo Liu [Fri, 24 May 2019 16:51:48 +0000 (12:51 -0400)]
drm/amdgpu/VCN2.0: add DPG pause mode

Pause the DPG when not doing decode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/VCN2.0: add DPG mode start and stop (v2)
Leo Liu [Tue, 14 May 2019 18:36:42 +0000 (14:36 -0400)]
drm/amdgpu/VCN2.0: add DPG mode start and stop (v2)

This is for using SRAM directly

v2: rebase (Alex)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/VCN2.0: add direct SRAM read and write
Leo Liu [Fri, 24 May 2019 16:19:00 +0000 (12:19 -0400)]
drm/amdgpu/VCN2.0: add direct SRAM read and write

This will be the basic and used for DPG mode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/VCN2.0 remove unused Macro and declaration
Leo Liu [Tue, 14 May 2019 16:55:54 +0000 (12:55 -0400)]
drm/amdgpu/VCN2.0 remove unused Macro and declaration

Just for cleanup

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: simplified od_settings for each asic
Kevin Wang [Mon, 17 Jun 2019 18:17:27 +0000 (13:17 -0500)]
drm/amd/powerplay: simplified od_settings for each asic

the od_settings is asic related data, so move it to asic file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: move od_default_setting callback to asic file
Kevin Wang [Tue, 21 May 2019 07:37:24 +0000 (15:37 +0800)]
drm/amd/powerplay: move od_default_setting callback to asic file

the set default od_setting is asic related function,
so move thic code to vega20_ppt file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: move od8_setting helper function to vega20_ppt
Kevin Wang [Tue, 21 May 2019 07:19:22 +0000 (15:19 +0800)]
drm/amd/powerplay: move od8_setting helper function to vega20_ppt

these callback functions is only used for vega20 asic, to be compatible
other asics,need to move this code to vega20_ppt file

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: fix clk type name error OD_SCLK OD_MCLK
Kevin Wang [Thu, 16 May 2019 10:24:08 +0000 (18:24 +0800)]
drm/amd/powerplay: fix clk type name error OD_SCLK OD_MCLK

use sw-smu clk type name to replace legacy clk type name

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: fix deadlock issue for smu_force_performance_level
Kevin Wang [Wed, 15 May 2019 07:59:38 +0000 (15:59 +0800)]
drm/amd/powerplay: fix deadlock issue for smu_force_performance_level

the smu->mutex is internal lock resource in sw-smu, some functions will use
it at the same time, so it maybe will cause deadlock issue.
this patch fix this issue in smu_force_performance_level function.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd: the data retured from PRT is expected to be 0
Jack Xiao [Mon, 20 May 2019 04:16:19 +0000 (12:16 +0800)]
drm/amd: the data retured from PRT is expected to be 0

The dummy page for returning from PRT resides inside system memory,
need set system flag bit in VM_L2_CNTL.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/gfx10: update gfx golden settings
tiancyin [Wed, 5 Jun 2019 21:57:44 +0000 (16:57 -0500)]
drm/amdgpu/gfx10: update gfx golden settings

add new registers: mmPA_SC_ENHANCE_1, mmTCP_CNTL,
update registers: mmDB_DEBUG4, mmUTCL1_CTRL

Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu/powerplay: add license to smu11 header
Alex Deucher [Wed, 22 May 2019 16:58:18 +0000 (11:58 -0500)]
drm/amdgpu/powerplay: add license to smu11 header

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add interface to get uclk dpm table
hersen wu [Tue, 21 May 2019 19:02:23 +0000 (15:02 -0400)]
drm/amd/powerplay: add interface to get uclk dpm table

dc needs get uclk dpm table for bandwidth calculation

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: wake up azalia from d3 by sending smu message
hersen wu [Tue, 21 May 2019 19:38:59 +0000 (15:38 -0400)]
drm/amd/powerplay: wake up azalia from d3 by sending smu message

this is hw workaround to wake up azalia from d3. display asic
and azalia are two different pci devices. while display asic
wake from d3, current hw does not send signal to azalia.
workaround: display driver ask smu send message to azalia device
to let azalia wake up.

Defintion of SMU message, like PPSMC_MSG_BacroAudioD3PME, is per
asic. It is shared by different OS.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: notify smu with active display count
hersen wu [Thu, 30 May 2019 04:30:32 +0000 (23:30 -0500)]
drm/amd/powerplay: notify smu with active display count

when dc update clocks via smu, smu needs to know how many
displays active. this interface is for dc notify number
of active displays to smu.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: allow dc request uclk change
hersen wu [Thu, 30 May 2019 04:28:55 +0000 (23:28 -0500)]
drm/amd/powerplay: allow dc request uclk change

when dc set mode or color format in frame buffer
change, it may request clock changes, like dispclk,
dcfclk, uclk. after smu get clock requests, smu
will make decision.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: remove smu callback funciton get_mclk(get_sclk)
Kevin Wang [Tue, 4 Jun 2019 09:38:42 +0000 (17:38 +0800)]
drm/amd/powerplay: remove smu callback funciton get_mclk(get_sclk)

remove smu callback: get_mclk, get_sclk.
because the function smu_get_dpm_freq_range has the same function.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: remove smu mutex lock in smu_hw_init
Kevin Wang [Tue, 4 Jun 2019 09:41:48 +0000 (17:41 +0800)]
drm/amd/powerplay: remove smu mutex lock in smu_hw_init

the smu mutex lock is unnecessary in smu hw init.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add thermal ctf support for navi10
Kevin Wang [Thu, 30 May 2019 10:00:22 +0000 (18:00 +0800)]
drm/amd/powerplay: add thermal ctf support for navi10

add sw-CTF support for navi10

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: fix no statements in function returning non-void
Hawking Zhang [Fri, 21 Jun 2019 16:29:29 +0000 (11:29 -0500)]
drm/amd/powerplay: fix no statements in function returning non-void

Add missing return (rebase fix).

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: move get_thermal_temperature_range to ppt funcs
Hawking Zhang [Mon, 10 Jun 2019 13:39:29 +0000 (21:39 +0800)]
drm/amd/powerplay: move get_thermal_temperature_range to ppt funcs

The thermal policy could be ASIC specific ones and depends on structures
in pptable. As a result, get_thermal_temperature_range should be implemented
as ppt funcs instead of smu funcs

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: move function thermal_get_temperature to veag20_ppt
Kevin Wang [Fri, 17 May 2019 06:12:51 +0000 (14:12 +0800)]
drm/amd/powerplay: move function thermal_get_temperature to veag20_ppt

the fcuntion thermal_get_temperature will be access SmuMetrics_t data,
the data structure is asic related, so move vega20_ppt to implement.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: move function get_metrics_table to vega20_ppt
Kevin Wang [Fri, 17 May 2019 06:02:15 +0000 (14:02 +0800)]
drm/amd/powerplay: move function get_metrics_table to vega20_ppt

the SmuMetrics_t table is asic related data structure.
so move vega20_ppt file to implement.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: move power_dpm_force_performance_level to amdgpu_smu file
Kevin Wang [Wed, 15 May 2019 04:59:58 +0000 (12:59 +0800)]
drm/amd/powerplay: move power_dpm_force_performance_level to amdgpu_smu file

because this callback is not asic related function, so move it to top
code level to support more asic (eg: navi10)

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: enable uclk dpm default on navi10
Kevin Wang [Thu, 16 May 2019 07:06:25 +0000 (15:06 +0800)]
drm/amd/powerplay: enable uclk dpm default on navi10

enable uclk (mclk) dpm by default on navi10

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: enable ac/dc feature on navi10
Kenneth Feng [Tue, 14 May 2019 09:34:55 +0000 (17:34 +0800)]
drm/amd/powerplay: enable ac/dc feature on navi10

enable ac/dc feature on navi10. currently we don't have
the case to verify it.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: enable gfxclk ds,dcefclk ds and fw dstate on navi10
Kenneth Feng [Tue, 14 May 2019 09:08:36 +0000 (17:08 +0800)]
drm/amd/powerplay: enable gfxclk ds,dcefclk ds and fw dstate on navi10

on navi10, by default the below four features are enabled.
gfxclk deep sleep: enabled and verified
fw dstate: enabled and then soc ulv is verified
dcefclk deep sleep: enabled and verified. notice that on different boards,
due to the minimum dcefclk deep sleep setting in VBIOS, we may not see dcefclk
deep sleep kicking in.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add sclk sysfs interface support for navi10
Kevin Wang [Tue, 14 May 2019 06:01:01 +0000 (14:01 +0800)]
drm/amd/powerplay: add sclk sysfs interface support for navi10

miss sclk support in force_clk_levels function

Signed-off-by: Kevin Wang <kevin1.Wang@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amdgpu: correct reference clock value on navi10
Tao Zhou [Tue, 14 May 2019 03:37:32 +0000 (11:37 +0800)]
drm/amdgpu: correct reference clock value on navi10

remove the divisor 4

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay/smu11: disable some pp features on navi10 A0 secure board
Tao Zhou [Mon, 13 May 2019 08:52:22 +0000 (16:52 +0800)]
drm/amd/powerplay/smu11: disable some pp features on navi10 A0 secure board

disable DPM UCLK and SOC DS on A0 secure board

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay/smu11: add secure board check function (v2)
Tao Zhou [Fri, 10 May 2019 08:31:57 +0000 (16:31 +0800)]
drm/amd/powerplay/smu11: add secure board check function (v2)

To determine whether the board is secure or not.

v2: rebase (Alex)

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay/smu11: enable ds socclk by default
Tao Zhou [Mon, 13 May 2019 08:56:17 +0000 (16:56 +0800)]
drm/amd/powerplay/smu11: enable ds socclk by default

Enable soc clk deep sleep.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: fix amdgpu_pm_info show gpu load error
Kevin Wang [Fri, 10 May 2019 07:29:11 +0000 (15:29 +0800)]
drm/amd/powerplay: fix amdgpu_pm_info show gpu load error

due to the smu dma/RTOS restriction, the interval of catching smu
metric table should be more than 1ms. otherwise it will cause the gpu
activity data corruption.

Signed-off-by:Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: simplify the interface of get_gpu_power
Kevin Wang [Fri, 21 Jun 2019 16:26:18 +0000 (11:26 -0500)]
drm/amd/powerplay: simplify the interface of get_gpu_power

this callback function is only call in read_sensor in smu_v11_0.c,
so move this code to {asic}_ppt.c to implement as asic related function.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: simplify the interface of get_current_activity_percent
Kevin Wang [Fri, 21 Jun 2019 16:25:00 +0000 (11:25 -0500)]
drm/amd/powerplay: simplify the interface of get_current_activity_percent

this callback function is only call in read_sensor in smu_v11_0.c,
so move this code to {asic}_ppt.c to implement as asic related function.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: fix dpm freq unit error (10KHz -> Mhz)
Kevin Wang [Wed, 8 May 2019 06:37:08 +0000 (14:37 +0800)]
drm/amd/powerplay: fix dpm freq unit error (10KHz -> Mhz)

the interface smu_v11_0_get_current_clk_freq should be return 10Khz not
Mhz unit to adapt vega20 and navi10 asic at the same time.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agoamd/powerplay: update the vcn pg
Kenneth Feng [Sun, 28 Apr 2019 09:43:36 +0000 (17:43 +0800)]
amd/powerplay: update the vcn pg

update the vcn pg function in navi10.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add function read_sensor for navi10
Kevin Wang [Sun, 28 Apr 2019 10:40:11 +0000 (18:40 +0800)]
drm/amd/powerplay: add function read_sensor for navi10

add callback function read_sensor for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add function set_watermarks_table function for navi10
Kevin Wang [Thu, 25 Apr 2019 10:02:14 +0000 (18:02 +0800)]
drm/amd/powerplay: add function set_watermarks_table function for navi10

add callback function set_watermarks_table for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add function notify_smc_display_config_change for navi10
Kevin Wang [Thu, 25 Apr 2019 08:15:21 +0000 (16:15 +0800)]
drm/amd/powerplay: add function notify_smc_display_config_change for navi10

add callback function notify_smc_display_config_change for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add function get_profiling_clk_mask for navi10
Kevin Wang [Thu, 25 Apr 2019 07:52:54 +0000 (15:52 +0800)]
drm/amd/powerplay: add function get_profiling_clk_mask for navi10

add callback function get_profiling_clk_mask for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add funciton get[set]_power_profile_mode for navi10 (v2)
Kevin Wang [Thu, 25 Apr 2019 07:41:13 +0000 (15:41 +0800)]
drm/amd/powerplay: add funciton get[set]_power_profile_mode for navi10 (v2)

add callback function get[set]_power_profile_mode for navi10 asic

v2: fix smu_update_table for rebase (Alex)

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5 years agodrm/amd/powerplay: add function get_workload_type_map for swsmu
Kevin Wang [Fri, 21 Jun 2019 16:19:15 +0000 (11:19 -0500)]
drm/amd/powerplay: add function get_workload_type_map for swsmu

1.add new callback function get_workload_byte for smu
2.remove old workload map function

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>