From 1d60047dd6fcd8bb840f3652ce25ab478a69c7ef Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 8 Nov 2017 13:18:31 +0100 Subject: [PATCH] drm/tegra: hdmi: Register debugfs in ->late_register() The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/hdmi.c | 510 +++++++++++++++++------------------ 1 file changed, 245 insertions(+), 265 deletions(-) diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index a68d80476e46..784739a9f497 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c @@ -79,8 +79,6 @@ struct tegra_hdmi { bool dvi; struct drm_info_list *debugfs_files; - struct drm_minor *minor; - struct dentry *debugfs; }; static inline struct tegra_hdmi * @@ -910,6 +908,249 @@ tegra_hdmi_connector_detect(struct drm_connector *connector, bool force) return status; } +#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } + +static const struct debugfs_reg32 tegra_hdmi_regs[] = { + DEBUGFS_REG32(HDMI_CTXSW), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB), + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2), + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0), + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N), + DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK), + DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL), + DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL), + DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH), + DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG), + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE), + DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS), + DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK), + DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE), + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT), +}; + +static int tegra_hdmi_show_regs(struct seq_file *s, void *data) +{ + struct drm_info_node *node = s->private; + struct tegra_hdmi *hdmi = node->info_ent->data; + struct drm_crtc *crtc = hdmi->output.encoder.crtc; + struct drm_device *drm = node->minor->dev; + unsigned int i; + int err = 0; + + drm_modeset_lock_all(drm); + + if (!crtc || !crtc->state->active) { + err = -EBUSY; + goto unlock; + } + + for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) { + unsigned int offset = tegra_hdmi_regs[i].offset; + + seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name, + offset, tegra_hdmi_readl(hdmi, offset)); + } + +unlock: + drm_modeset_unlock_all(drm); + return err; +} + +static struct drm_info_list debugfs_files[] = { + { "regs", tegra_hdmi_show_regs, 0, NULL }, +}; + +static int tegra_hdmi_late_register(struct drm_connector *connector) +{ + struct tegra_output *output = connector_to_output(connector); + unsigned int i, count = ARRAY_SIZE(debugfs_files); + struct drm_minor *minor = connector->dev->primary; + struct dentry *root = connector->debugfs_entry; + struct tegra_hdmi *hdmi = to_hdmi(output); + int err; + + hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), + GFP_KERNEL); + if (!hdmi->debugfs_files) + return -ENOMEM; + + for (i = 0; i < count; i++) + hdmi->debugfs_files[i].data = hdmi; + + err = drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor); + if (err < 0) + goto free; + + return 0; + +free: + kfree(hdmi->debugfs_files); + hdmi->debugfs_files = NULL; + + return err; +} + +static void tegra_hdmi_early_unregister(struct drm_connector *connector) +{ + struct tegra_output *output = connector_to_output(connector); + struct drm_minor *minor = connector->dev->primary; + unsigned int count = ARRAY_SIZE(debugfs_files); + struct tegra_hdmi *hdmi = to_hdmi(output); + + drm_debugfs_remove_files(hdmi->debugfs_files, count, minor); + kfree(hdmi->debugfs_files); + hdmi->debugfs_files = NULL; +} + static const struct drm_connector_funcs tegra_hdmi_connector_funcs = { .reset = drm_atomic_helper_connector_reset, .detect = tegra_hdmi_connector_detect, @@ -917,6 +1158,8 @@ static const struct drm_connector_funcs tegra_hdmi_connector_funcs = { .destroy = tegra_output_connector_destroy, .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, + .late_register = tegra_hdmi_late_register, + .early_unregister = tegra_hdmi_early_unregister, }; static enum drm_mode_status @@ -1225,260 +1468,6 @@ static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = { .atomic_check = tegra_hdmi_encoder_atomic_check, }; -#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } - -static const struct debugfs_reg32 tegra_hdmi_regs[] = { - DEBUGFS_REG32(HDMI_CTXSW), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB), - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2), - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0), - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N), - DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK), - DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL), - DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL), - DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH), - DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG), - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE), - DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS), - DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK), - DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE), - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT), -}; - -static int tegra_hdmi_show_regs(struct seq_file *s, void *data) -{ - struct drm_info_node *node = s->private; - struct tegra_hdmi *hdmi = node->info_ent->data; - struct drm_crtc *crtc = hdmi->output.encoder.crtc; - struct drm_device *drm = node->minor->dev; - unsigned int i; - int err = 0; - - drm_modeset_lock_all(drm); - - if (!crtc || !crtc->state->active) { - err = -EBUSY; - goto unlock; - } - - for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) { - unsigned int offset = tegra_hdmi_regs[i].offset; - - seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name, - offset, tegra_hdmi_readl(hdmi, offset)); - } - -unlock: - drm_modeset_unlock_all(drm); - return err; -} - -static struct drm_info_list debugfs_files[] = { - { "regs", tegra_hdmi_show_regs, 0, NULL }, -}; - -static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi, - struct drm_minor *minor) -{ - unsigned int i; - int err; - - hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root); - if (!hdmi->debugfs) - return -ENOMEM; - - hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), - GFP_KERNEL); - if (!hdmi->debugfs_files) { - err = -ENOMEM; - goto remove; - } - - for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) - hdmi->debugfs_files[i].data = hdmi; - - err = drm_debugfs_create_files(hdmi->debugfs_files, - ARRAY_SIZE(debugfs_files), - hdmi->debugfs, minor); - if (err < 0) - goto free; - - hdmi->minor = minor; - - return 0; - -free: - kfree(hdmi->debugfs_files); - hdmi->debugfs_files = NULL; -remove: - debugfs_remove(hdmi->debugfs); - hdmi->debugfs = NULL; - - return err; -} - -static void tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi) -{ - drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files), - hdmi->minor); - hdmi->minor = NULL; - - kfree(hdmi->debugfs_files); - hdmi->debugfs_files = NULL; - - debugfs_remove(hdmi->debugfs); - hdmi->debugfs = NULL; -} - static int tegra_hdmi_init(struct host1x_client *client) { struct drm_device *drm = dev_get_drvdata(client->parent); @@ -1511,12 +1500,6 @@ static int tegra_hdmi_init(struct host1x_client *client) hdmi->output.encoder.possible_crtcs = 0x3; - if (IS_ENABLED(CONFIG_DEBUG_FS)) { - err = tegra_hdmi_debugfs_init(hdmi, drm->primary); - if (err < 0) - dev_err(client->dev, "debugfs setup failed: %d\n", err); - } - err = regulator_enable(hdmi->hdmi); if (err < 0) { dev_err(client->dev, "failed to enable HDMI regulator: %d\n", @@ -1549,9 +1532,6 @@ static int tegra_hdmi_exit(struct host1x_client *client) regulator_disable(hdmi->pll); regulator_disable(hdmi->hdmi); - if (IS_ENABLED(CONFIG_DEBUG_FS)) - tegra_hdmi_debugfs_exit(hdmi); - return 0; } -- 2.30.2